1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 /* 120 * File organization: 121 * - private structures 122 * - iflib private utility functions 123 * - ifnet functions 124 * - vlan registry and other exported functions 125 * - iflib public core functions 126 * 127 * 128 */ 129 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 130 131 #define IFLIB_RXEOF_MORE (1U << 0) 132 #define IFLIB_RXEOF_EMPTY (2U << 0) 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 146 typedef struct iflib_filter_info { 147 driver_filter_t *ifi_filter; 148 void *ifi_filter_arg; 149 struct grouptask *ifi_task; 150 void *ifi_ctx; 151 } *iflib_filter_info_t; 152 153 struct iflib_ctx { 154 KOBJ_FIELDS; 155 /* 156 * Pointer to hardware driver's softc 157 */ 158 void *ifc_softc; 159 device_t ifc_dev; 160 if_t ifc_ifp; 161 162 cpuset_t ifc_cpus; 163 if_shared_ctx_t ifc_sctx; 164 struct if_softc_ctx ifc_softc_ctx; 165 166 struct sx ifc_ctx_sx; 167 struct mtx ifc_state_mtx; 168 169 iflib_txq_t ifc_txqs; 170 iflib_rxq_t ifc_rxqs; 171 uint32_t ifc_if_flags; 172 uint32_t ifc_flags; 173 uint32_t ifc_max_fl_buf_size; 174 uint32_t ifc_rx_mbuf_sz; 175 176 int ifc_link_state; 177 int ifc_watchdog_events; 178 struct cdev *ifc_led_dev; 179 struct resource *ifc_msix_mem; 180 181 struct if_irq ifc_legacy_irq; 182 struct grouptask ifc_admin_task; 183 struct grouptask ifc_vflr_task; 184 struct iflib_filter_info ifc_filter_info; 185 struct ifmedia ifc_media; 186 struct ifmedia *ifc_mediap; 187 188 struct sysctl_oid *ifc_sysctl_node; 189 uint16_t ifc_sysctl_ntxqs; 190 uint16_t ifc_sysctl_nrxqs; 191 uint16_t ifc_sysctl_qs_eq_override; 192 uint16_t ifc_sysctl_rx_budget; 193 uint16_t ifc_sysctl_tx_abdicate; 194 uint16_t ifc_sysctl_core_offset; 195 #define CORE_OFFSET_UNSPECIFIED 0xffff 196 uint8_t ifc_sysctl_separate_txrx; 197 198 qidx_t ifc_sysctl_ntxds[8]; 199 qidx_t ifc_sysctl_nrxds[8]; 200 struct if_txrx ifc_txrx; 201 #define isc_txd_encap ifc_txrx.ift_txd_encap 202 #define isc_txd_flush ifc_txrx.ift_txd_flush 203 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 204 #define isc_rxd_available ifc_txrx.ift_rxd_available 205 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 207 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 209 eventhandler_tag ifc_vlan_attach_event; 210 eventhandler_tag ifc_vlan_detach_event; 211 struct ether_addr ifc_mac; 212 }; 213 214 void * 215 iflib_get_softc(if_ctx_t ctx) 216 { 217 218 return (ctx->ifc_softc); 219 } 220 221 device_t 222 iflib_get_dev(if_ctx_t ctx) 223 { 224 225 return (ctx->ifc_dev); 226 } 227 228 if_t 229 iflib_get_ifp(if_ctx_t ctx) 230 { 231 232 return (ctx->ifc_ifp); 233 } 234 235 struct ifmedia * 236 iflib_get_media(if_ctx_t ctx) 237 { 238 239 return (ctx->ifc_mediap); 240 } 241 242 uint32_t 243 iflib_get_flags(if_ctx_t ctx) 244 { 245 return (ctx->ifc_flags); 246 } 247 248 void 249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 250 { 251 252 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 253 } 254 255 if_softc_ctx_t 256 iflib_get_softc_ctx(if_ctx_t ctx) 257 { 258 259 return (&ctx->ifc_softc_ctx); 260 } 261 262 if_shared_ctx_t 263 iflib_get_sctx(if_ctx_t ctx) 264 { 265 266 return (ctx->ifc_sctx); 267 } 268 269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 272 273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 275 276 typedef struct iflib_sw_rx_desc_array { 277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 278 struct mbuf **ifsd_m; /* pkthdr mbufs */ 279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 281 } iflib_rxsd_array_t; 282 283 typedef struct iflib_sw_tx_desc_array { 284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 286 struct mbuf **ifsd_m; /* pkthdr mbufs */ 287 } if_txsd_vec_t; 288 289 /* magic number that should be high enough for any hardware */ 290 #define IFLIB_MAX_TX_SEGS 128 291 #define IFLIB_RX_COPY_THRESH 128 292 #define IFLIB_MAX_RX_REFRESH 32 293 /* The minimum descriptors per second before we start coalescing */ 294 #define IFLIB_MIN_DESC_SEC 16384 295 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 296 #define IFLIB_QUEUE_IDLE 0 297 #define IFLIB_QUEUE_HUNG 1 298 #define IFLIB_QUEUE_WORKING 2 299 /* maximum number of txqs that can share an rx interrupt */ 300 #define IFLIB_MAX_TX_SHARED_INTR 4 301 302 /* this should really scale with ring size - this is a fairly arbitrary value */ 303 #define TX_BATCH_SIZE 32 304 305 #define IFLIB_RESTART_BUDGET 8 306 307 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 308 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 309 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 310 311 struct iflib_txq { 312 qidx_t ift_in_use; 313 qidx_t ift_cidx; 314 qidx_t ift_cidx_processed; 315 qidx_t ift_pidx; 316 uint8_t ift_gen; 317 uint8_t ift_br_offset; 318 uint16_t ift_npending; 319 uint16_t ift_db_pending; 320 uint16_t ift_rs_pending; 321 /* implicit pad */ 322 uint8_t ift_txd_size[8]; 323 uint64_t ift_processed; 324 uint64_t ift_cleaned; 325 uint64_t ift_cleaned_prev; 326 #if MEMORY_LOGGING 327 uint64_t ift_enqueued; 328 uint64_t ift_dequeued; 329 #endif 330 uint64_t ift_no_tx_dma_setup; 331 uint64_t ift_no_desc_avail; 332 uint64_t ift_mbuf_defrag_failed; 333 uint64_t ift_mbuf_defrag; 334 uint64_t ift_map_failed; 335 uint64_t ift_txd_encap_efbig; 336 uint64_t ift_pullups; 337 uint64_t ift_last_timer_tick; 338 339 struct mtx ift_mtx; 340 struct mtx ift_db_mtx; 341 342 /* constant values */ 343 if_ctx_t ift_ctx; 344 struct ifmp_ring *ift_br; 345 struct grouptask ift_task; 346 qidx_t ift_size; 347 uint16_t ift_id; 348 struct callout ift_timer; 349 #ifdef DEV_NETMAP 350 struct callout ift_netmap_timer; 351 #endif /* DEV_NETMAP */ 352 353 if_txsd_vec_t ift_sds; 354 uint8_t ift_qstatus; 355 uint8_t ift_closed; 356 uint8_t ift_update_freq; 357 struct iflib_filter_info ift_filter_info; 358 bus_dma_tag_t ift_buf_tag; 359 bus_dma_tag_t ift_tso_buf_tag; 360 iflib_dma_info_t ift_ifdi; 361 #define MTX_NAME_LEN 32 362 char ift_mtx_name[MTX_NAME_LEN]; 363 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 364 #ifdef IFLIB_DIAGNOSTICS 365 uint64_t ift_cpu_exec_count[256]; 366 #endif 367 } __aligned(CACHE_LINE_SIZE); 368 369 struct iflib_fl { 370 qidx_t ifl_cidx; 371 qidx_t ifl_pidx; 372 qidx_t ifl_credits; 373 uint8_t ifl_gen; 374 uint8_t ifl_rxd_size; 375 #if MEMORY_LOGGING 376 uint64_t ifl_m_enqueued; 377 uint64_t ifl_m_dequeued; 378 uint64_t ifl_cl_enqueued; 379 uint64_t ifl_cl_dequeued; 380 #endif 381 /* implicit pad */ 382 bitstr_t *ifl_rx_bitmap; 383 qidx_t ifl_fragidx; 384 /* constant */ 385 qidx_t ifl_size; 386 uint16_t ifl_buf_size; 387 uint16_t ifl_cltype; 388 uma_zone_t ifl_zone; 389 iflib_rxsd_array_t ifl_sds; 390 iflib_rxq_t ifl_rxq; 391 uint8_t ifl_id; 392 bus_dma_tag_t ifl_buf_tag; 393 iflib_dma_info_t ifl_ifdi; 394 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 395 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 396 } __aligned(CACHE_LINE_SIZE); 397 398 static inline qidx_t 399 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 400 { 401 qidx_t used; 402 403 if (pidx > cidx) 404 used = pidx - cidx; 405 else if (pidx < cidx) 406 used = size - cidx + pidx; 407 else if (gen == 0 && pidx == cidx) 408 used = 0; 409 else if (gen == 1 && pidx == cidx) 410 used = size; 411 else 412 panic("bad state"); 413 414 return (used); 415 } 416 417 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 418 419 #define IDXDIFF(head, tail, wrap) \ 420 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 421 422 struct iflib_rxq { 423 if_ctx_t ifr_ctx; 424 iflib_fl_t ifr_fl; 425 uint64_t ifr_rx_irq; 426 struct pfil_head *pfil; 427 /* 428 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 429 * the completion queue consumer index. Otherwise it's unused. 430 */ 431 qidx_t ifr_cq_cidx; 432 uint16_t ifr_id; 433 uint8_t ifr_nfl; 434 uint8_t ifr_ntxqirq; 435 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 436 uint8_t ifr_fl_offset; 437 struct lro_ctrl ifr_lc; 438 struct grouptask ifr_task; 439 struct callout ifr_watchdog; 440 struct iflib_filter_info ifr_filter_info; 441 iflib_dma_info_t ifr_ifdi; 442 443 /* dynamically allocate if any drivers need a value substantially larger than this */ 444 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 445 #ifdef IFLIB_DIAGNOSTICS 446 uint64_t ifr_cpu_exec_count[256]; 447 #endif 448 } __aligned(CACHE_LINE_SIZE); 449 450 typedef struct if_rxsd { 451 caddr_t *ifsd_cl; 452 iflib_fl_t ifsd_fl; 453 } *if_rxsd_t; 454 455 /* multiple of word size */ 456 #ifdef __LP64__ 457 #define PKT_INFO_SIZE 6 458 #define RXD_INFO_SIZE 5 459 #define PKT_TYPE uint64_t 460 #else 461 #define PKT_INFO_SIZE 11 462 #define RXD_INFO_SIZE 8 463 #define PKT_TYPE uint32_t 464 #endif 465 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 466 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 467 468 typedef struct if_pkt_info_pad { 469 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 470 } *if_pkt_info_pad_t; 471 typedef struct if_rxd_info_pad { 472 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 473 } *if_rxd_info_pad_t; 474 475 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 476 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 477 478 static inline void 479 pkt_info_zero(if_pkt_info_t pi) 480 { 481 if_pkt_info_pad_t pi_pad; 482 483 pi_pad = (if_pkt_info_pad_t)pi; 484 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 485 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 486 #ifndef __LP64__ 487 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 488 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 489 #endif 490 } 491 492 static device_method_t iflib_pseudo_methods[] = { 493 DEVMETHOD(device_attach, noop_attach), 494 DEVMETHOD(device_detach, iflib_pseudo_detach), 495 DEVMETHOD_END 496 }; 497 498 driver_t iflib_pseudodriver = { 499 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 500 }; 501 502 static inline void 503 rxd_info_zero(if_rxd_info_t ri) 504 { 505 if_rxd_info_pad_t ri_pad; 506 int i; 507 508 ri_pad = (if_rxd_info_pad_t)ri; 509 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 510 ri_pad->rxd_val[i] = 0; 511 ri_pad->rxd_val[i+1] = 0; 512 ri_pad->rxd_val[i+2] = 0; 513 ri_pad->rxd_val[i+3] = 0; 514 } 515 #ifdef __LP64__ 516 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 517 #endif 518 } 519 520 /* 521 * Only allow a single packet to take up most 1/nth of the tx ring 522 */ 523 #define MAX_SINGLE_PACKET_FRACTION 12 524 #define IF_BAD_DMA (bus_addr_t)-1 525 526 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 527 528 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 529 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 530 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 531 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 532 533 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 534 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 535 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 536 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 537 538 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 539 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 540 541 void 542 iflib_set_detach(if_ctx_t ctx) 543 { 544 STATE_LOCK(ctx); 545 ctx->ifc_flags |= IFC_IN_DETACH; 546 STATE_UNLOCK(ctx); 547 } 548 549 /* Our boot-time initialization hook */ 550 static int iflib_module_event_handler(module_t, int, void *); 551 552 static moduledata_t iflib_moduledata = { 553 "iflib", 554 iflib_module_event_handler, 555 NULL 556 }; 557 558 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 559 MODULE_VERSION(iflib, 1); 560 561 MODULE_DEPEND(iflib, pci, 1, 1, 1); 562 MODULE_DEPEND(iflib, ether, 1, 1, 1); 563 564 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 565 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 566 567 #ifndef IFLIB_DEBUG_COUNTERS 568 #ifdef INVARIANTS 569 #define IFLIB_DEBUG_COUNTERS 1 570 #else 571 #define IFLIB_DEBUG_COUNTERS 0 572 #endif /* !INVARIANTS */ 573 #endif 574 575 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 576 "iflib driver parameters"); 577 578 /* 579 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 580 */ 581 static int iflib_min_tx_latency = 0; 582 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 583 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 584 static int iflib_no_tx_batch = 0; 585 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 586 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 587 588 #if IFLIB_DEBUG_COUNTERS 589 590 static int iflib_tx_seen; 591 static int iflib_tx_sent; 592 static int iflib_tx_encap; 593 static int iflib_rx_allocs; 594 static int iflib_fl_refills; 595 static int iflib_fl_refills_large; 596 static int iflib_tx_frees; 597 598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 599 &iflib_tx_seen, 0, "# TX mbufs seen"); 600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 601 &iflib_tx_sent, 0, "# TX mbufs sent"); 602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 603 &iflib_tx_encap, 0, "# TX mbufs encapped"); 604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 605 &iflib_tx_frees, 0, "# TX frees"); 606 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 607 &iflib_rx_allocs, 0, "# RX allocations"); 608 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 609 &iflib_fl_refills, 0, "# refills"); 610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 611 &iflib_fl_refills_large, 0, "# large refills"); 612 613 static int iflib_txq_drain_flushing; 614 static int iflib_txq_drain_oactive; 615 static int iflib_txq_drain_notready; 616 617 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 618 &iflib_txq_drain_flushing, 0, "# drain flushes"); 619 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 620 &iflib_txq_drain_oactive, 0, "# drain oactives"); 621 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 622 &iflib_txq_drain_notready, 0, "# drain notready"); 623 624 static int iflib_encap_load_mbuf_fail; 625 static int iflib_encap_pad_mbuf_fail; 626 static int iflib_encap_txq_avail_fail; 627 static int iflib_encap_txd_encap_fail; 628 629 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 630 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 632 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 634 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 636 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 637 638 static int iflib_task_fn_rxs; 639 static int iflib_rx_intr_enables; 640 static int iflib_fast_intrs; 641 static int iflib_rx_unavail; 642 static int iflib_rx_ctx_inactive; 643 static int iflib_rx_if_input; 644 static int iflib_rxd_flush; 645 646 static int iflib_verbose_debug; 647 648 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 649 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 650 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 651 &iflib_rx_intr_enables, 0, "# RX intr enables"); 652 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 653 &iflib_fast_intrs, 0, "# fast_intr calls"); 654 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 655 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 657 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 659 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 661 &iflib_rxd_flush, 0, "# times rxd_flush called"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 663 &iflib_verbose_debug, 0, "enable verbose debugging"); 664 665 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 666 static void 667 iflib_debug_reset(void) 668 { 669 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 670 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 671 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 672 iflib_txq_drain_notready = 673 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 674 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 675 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 676 iflib_rx_unavail = 677 iflib_rx_ctx_inactive = iflib_rx_if_input = 678 iflib_rxd_flush = 0; 679 } 680 681 #else 682 #define DBG_COUNTER_INC(name) 683 static void iflib_debug_reset(void) {} 684 #endif 685 686 #define IFLIB_DEBUG 0 687 688 static void iflib_tx_structures_free(if_ctx_t ctx); 689 static void iflib_rx_structures_free(if_ctx_t ctx); 690 static int iflib_queues_alloc(if_ctx_t ctx); 691 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 692 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 693 static int iflib_qset_structures_setup(if_ctx_t ctx); 694 static int iflib_msix_init(if_ctx_t ctx); 695 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 696 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 697 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 698 #ifdef ALTQ 699 static void iflib_altq_if_start(if_t ifp); 700 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 701 #endif 702 static int iflib_register(if_ctx_t); 703 static void iflib_deregister(if_ctx_t); 704 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 705 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 706 static void iflib_init_locked(if_ctx_t ctx); 707 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 708 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 709 static void iflib_ifmp_purge(iflib_txq_t txq); 710 static void _iflib_pre_assert(if_softc_ctx_t scctx); 711 static void iflib_if_init_locked(if_ctx_t ctx); 712 static void iflib_free_intr_mem(if_ctx_t ctx); 713 #ifndef __NO_STRICT_ALIGNMENT 714 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 715 #endif 716 717 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 718 SLIST_HEAD_INITIALIZER(cpu_offsets); 719 struct cpu_offset { 720 SLIST_ENTRY(cpu_offset) entries; 721 cpuset_t set; 722 unsigned int refcount; 723 uint16_t offset; 724 }; 725 static struct mtx cpu_offset_mtx; 726 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 727 MTX_DEF); 728 729 DEBUGNET_DEFINE(iflib); 730 731 static int 732 iflib_num_rx_descs(if_ctx_t ctx) 733 { 734 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 735 if_shared_ctx_t sctx = ctx->ifc_sctx; 736 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 737 738 return scctx->isc_nrxd[first_rxq]; 739 } 740 741 static int 742 iflib_num_tx_descs(if_ctx_t ctx) 743 { 744 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 745 if_shared_ctx_t sctx = ctx->ifc_sctx; 746 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 747 748 return scctx->isc_ntxd[first_txq]; 749 } 750 751 #ifdef DEV_NETMAP 752 #include <sys/selinfo.h> 753 #include <net/netmap.h> 754 #include <dev/netmap/netmap_kern.h> 755 756 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 757 758 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 759 static void iflib_netmap_timer(void *arg); 760 761 /* 762 * device-specific sysctl variables: 763 * 764 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 765 * During regular operations the CRC is stripped, but on some 766 * hardware reception of frames not multiple of 64 is slower, 767 * so using crcstrip=0 helps in benchmarks. 768 * 769 * iflib_rx_miss, iflib_rx_miss_bufs: 770 * count packets that might be missed due to lost interrupts. 771 */ 772 SYSCTL_DECL(_dev_netmap); 773 /* 774 * The xl driver by default strips CRCs and we do not override it. 775 */ 776 777 int iflib_crcstrip = 1; 778 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 779 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 780 781 int iflib_rx_miss, iflib_rx_miss_bufs; 782 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 783 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 784 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 785 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 786 787 /* 788 * Register/unregister. We are already under netmap lock. 789 * Only called on the first register or the last unregister. 790 */ 791 static int 792 iflib_netmap_register(struct netmap_adapter *na, int onoff) 793 { 794 if_t ifp = na->ifp; 795 if_ctx_t ctx = ifp->if_softc; 796 int status; 797 798 CTX_LOCK(ctx); 799 IFDI_INTR_DISABLE(ctx); 800 801 /* Tell the stack that the interface is no longer active */ 802 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 803 804 if (!CTX_IS_VF(ctx)) 805 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 806 807 iflib_stop(ctx); 808 809 /* 810 * Enable (or disable) netmap flags, and intercept (or restore) 811 * ifp->if_transmit. This is done once the device has been stopped 812 * to prevent race conditions. 813 */ 814 if (onoff) { 815 nm_set_native_flags(na); 816 } else { 817 nm_clear_native_flags(na); 818 } 819 820 iflib_init_locked(ctx); 821 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 822 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 823 if (status) 824 nm_clear_native_flags(na); 825 CTX_UNLOCK(ctx); 826 return (status); 827 } 828 829 static int 830 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 831 { 832 struct netmap_adapter *na = kring->na; 833 u_int const lim = kring->nkr_num_slots - 1; 834 u_int nm_i = kring->nr_hwcur; 835 struct netmap_ring *ring = kring->ring; 836 bus_dmamap_t *map; 837 struct if_rxd_update iru; 838 if_ctx_t ctx = rxq->ifr_ctx; 839 iflib_fl_t fl = &rxq->ifr_fl[0]; 840 u_int nic_i_first, nic_i; 841 int i, n; 842 #if IFLIB_DEBUG_COUNTERS 843 int rf_count = 0; 844 #endif 845 846 /* 847 * This function is used both at initialization and in rxsync. 848 * At initialization we need to prepare (with isc_rxd_refill()) 849 * all the (N) netmap buffers in the ring, in such a way to keep 850 * fl->ifl_pidx and kring->nr_hwcur in sync (except for 851 * kring->nkr_hwofs); at rxsync time, both indexes point to the 852 * next buffer to be refilled. 853 * In any case we publish (with isc_rxd_flush()) up to 854 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 855 * pointer to overrun the head/cons pointer, although this is 856 * not necessary for some NICs (e.g. vmx). 857 */ 858 if (__predict_false(init)) 859 n = kring->nkr_num_slots; 860 else { 861 n = kring->rhead - nm_i; 862 if (n == 0) 863 return (0); /* Nothing to do. */ 864 if (n < 0) 865 n += kring->nkr_num_slots; 866 } 867 868 /* Start to refill from nr_hwcur, publishing n buffers. */ 869 iru_init(&iru, rxq, 0 /* flid */); 870 map = fl->ifl_sds.ifsd_map; 871 nic_i = fl->ifl_pidx; 872 MPASS(nic_i == netmap_idx_k2n(kring, nm_i)); 873 DBG_COUNTER_INC(fl_refills); 874 while (n > 0) { 875 #if IFLIB_DEBUG_COUNTERS 876 if (++rf_count == 9) 877 DBG_COUNTER_INC(fl_refills_large); 878 #endif 879 nic_i_first = nic_i; 880 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 881 struct netmap_slot *slot = &ring->slot[nm_i]; 882 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]); 883 884 MPASS(i < IFLIB_MAX_RX_REFRESH); 885 886 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 887 return netmap_ring_reinit(kring); 888 889 fl->ifl_rxd_idxs[i] = nic_i; 890 891 if (__predict_false(init)) { 892 netmap_load_map(na, fl->ifl_buf_tag, 893 map[nic_i], addr); 894 } else if (slot->flags & NS_BUF_CHANGED) { 895 /* buffer has changed, reload map */ 896 netmap_reload_map(na, fl->ifl_buf_tag, 897 map[nic_i], addr); 898 } 899 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 900 BUS_DMASYNC_PREREAD); 901 slot->flags &= ~NS_BUF_CHANGED; 902 903 nm_i = nm_next(nm_i, lim); 904 nic_i = nm_next(nic_i, lim); 905 } 906 907 iru.iru_pidx = nic_i_first; 908 iru.iru_count = i; 909 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 910 } 911 fl->ifl_pidx = nic_i; 912 MPASS(!init || nm_i == 0); 913 MPASS(nm_i == kring->rhead); 914 kring->nr_hwcur = nm_i; 915 916 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 917 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 918 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 919 nm_prev(nic_i, lim)); 920 DBG_COUNTER_INC(rxd_flush); 921 922 return (0); 923 } 924 925 #define NETMAP_TX_TIMER_US 90 926 927 /* 928 * Reconcile kernel and user view of the transmit ring. 929 * 930 * All information is in the kring. 931 * Userspace wants to send packets up to the one before kring->rhead, 932 * kernel knows kring->nr_hwcur is the first unsent packet. 933 * 934 * Here we push packets out (as many as possible), and possibly 935 * reclaim buffers from previously completed transmission. 936 * 937 * The caller (netmap) guarantees that there is only one instance 938 * running at any time. Any interference with other driver 939 * methods should be handled by the individual drivers. 940 */ 941 static int 942 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 943 { 944 struct netmap_adapter *na = kring->na; 945 if_t ifp = na->ifp; 946 struct netmap_ring *ring = kring->ring; 947 u_int nm_i; /* index into the netmap kring */ 948 u_int nic_i; /* index into the NIC ring */ 949 u_int n; 950 u_int const lim = kring->nkr_num_slots - 1; 951 u_int const head = kring->rhead; 952 struct if_pkt_info pi; 953 954 /* 955 * interrupts on every tx packet are expensive so request 956 * them every half ring, or where NS_REPORT is set 957 */ 958 u_int report_frequency = kring->nkr_num_slots >> 1; 959 /* device-specific */ 960 if_ctx_t ctx = ifp->if_softc; 961 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 962 963 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 964 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 965 966 /* 967 * First part: process new packets to send. 968 * nm_i is the current index in the netmap kring, 969 * nic_i is the corresponding index in the NIC ring. 970 * 971 * If we have packets to send (nm_i != head) 972 * iterate over the netmap ring, fetch length and update 973 * the corresponding slot in the NIC ring. Some drivers also 974 * need to update the buffer's physical address in the NIC slot 975 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 976 * 977 * The netmap_reload_map() calls is especially expensive, 978 * even when (as in this case) the tag is 0, so do only 979 * when the buffer has actually changed. 980 * 981 * If possible do not set the report/intr bit on all slots, 982 * but only a few times per ring or when NS_REPORT is set. 983 * 984 * Finally, on 10G and faster drivers, it might be useful 985 * to prefetch the next slot and txr entry. 986 */ 987 988 nm_i = kring->nr_hwcur; 989 if (nm_i != head) { /* we have new packets to send */ 990 pkt_info_zero(&pi); 991 pi.ipi_segs = txq->ift_segs; 992 pi.ipi_qsidx = kring->ring_id; 993 nic_i = netmap_idx_k2n(kring, nm_i); 994 995 __builtin_prefetch(&ring->slot[nm_i]); 996 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 997 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 998 999 for (n = 0; nm_i != head; n++) { 1000 struct netmap_slot *slot = &ring->slot[nm_i]; 1001 u_int len = slot->len; 1002 uint64_t paddr; 1003 void *addr = PNMB(na, slot, &paddr); 1004 int flags = (slot->flags & NS_REPORT || 1005 nic_i == 0 || nic_i == report_frequency) ? 1006 IPI_TX_INTR : 0; 1007 1008 /* device-specific */ 1009 pi.ipi_len = len; 1010 pi.ipi_segs[0].ds_addr = paddr; 1011 pi.ipi_segs[0].ds_len = len; 1012 pi.ipi_nsegs = 1; 1013 pi.ipi_ndescs = 0; 1014 pi.ipi_pidx = nic_i; 1015 pi.ipi_flags = flags; 1016 1017 /* Fill the slot in the NIC ring. */ 1018 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1019 DBG_COUNTER_INC(tx_encap); 1020 1021 /* prefetch for next round */ 1022 __builtin_prefetch(&ring->slot[nm_i + 1]); 1023 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1024 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1025 1026 NM_CHECK_ADDR_LEN(na, addr, len); 1027 1028 if (slot->flags & NS_BUF_CHANGED) { 1029 /* buffer has changed, reload map */ 1030 netmap_reload_map(na, txq->ift_buf_tag, 1031 txq->ift_sds.ifsd_map[nic_i], addr); 1032 } 1033 /* make sure changes to the buffer are synced */ 1034 bus_dmamap_sync(txq->ift_buf_tag, 1035 txq->ift_sds.ifsd_map[nic_i], 1036 BUS_DMASYNC_PREWRITE); 1037 1038 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1039 nm_i = nm_next(nm_i, lim); 1040 nic_i = nm_next(nic_i, lim); 1041 } 1042 kring->nr_hwcur = nm_i; 1043 1044 /* synchronize the NIC ring */ 1045 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1046 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1047 1048 /* (re)start the tx unit up to slot nic_i (excluded) */ 1049 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1050 } 1051 1052 /* 1053 * Second part: reclaim buffers for completed transmissions. 1054 * 1055 * If there are unclaimed buffers, attempt to reclaim them. 1056 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1057 * trigger a per-tx-queue timer to try again later. 1058 */ 1059 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1060 if (iflib_tx_credits_update(ctx, txq)) { 1061 /* some tx completed, increment avail */ 1062 nic_i = txq->ift_cidx_processed; 1063 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1064 } 1065 } 1066 1067 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1068 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1069 callout_reset_sbt_on(&txq->ift_netmap_timer, 1070 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1071 iflib_netmap_timer, txq, 1072 txq->ift_netmap_timer.c_cpu, 0); 1073 } 1074 return (0); 1075 } 1076 1077 /* 1078 * Reconcile kernel and user view of the receive ring. 1079 * Same as for the txsync, this routine must be efficient. 1080 * The caller guarantees a single invocations, but races against 1081 * the rest of the driver should be handled here. 1082 * 1083 * On call, kring->rhead is the first packet that userspace wants 1084 * to keep, and kring->rcur is the wakeup point. 1085 * The kernel has previously reported packets up to kring->rtail. 1086 * 1087 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1088 * of whether or not we received an interrupt. 1089 */ 1090 static int 1091 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1092 { 1093 struct netmap_adapter *na = kring->na; 1094 struct netmap_ring *ring = kring->ring; 1095 if_t ifp = na->ifp; 1096 uint32_t nm_i; /* index into the netmap ring */ 1097 uint32_t nic_i; /* index into the NIC ring */ 1098 u_int n; 1099 u_int const lim = kring->nkr_num_slots - 1; 1100 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1101 1102 if_ctx_t ctx = ifp->if_softc; 1103 if_shared_ctx_t sctx = ctx->ifc_sctx; 1104 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1105 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1106 iflib_fl_t fl = &rxq->ifr_fl[0]; 1107 struct if_rxd_info ri; 1108 qidx_t *cidxp; 1109 1110 /* 1111 * netmap only uses free list 0, to avoid out of order consumption 1112 * of receive buffers 1113 */ 1114 1115 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1116 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1117 1118 /* 1119 * First part: import newly received packets. 1120 * 1121 * nm_i is the index of the next free slot in the netmap ring, 1122 * nic_i is the index of the next received packet in the NIC ring 1123 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1124 * differ in case if_init() has been called while 1125 * in netmap mode. For the receive ring we have 1126 * 1127 * nic_i = fl->ifl_cidx; 1128 * nm_i = kring->nr_hwtail (previous) 1129 * and 1130 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1131 * 1132 * fl->ifl_cidx is set to 0 on a ring reinit 1133 */ 1134 if (netmap_no_pendintr || force_update) { 1135 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1136 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1137 int crclen = iflib_crcstrip ? 0 : 4; 1138 int error, avail; 1139 1140 /* 1141 * For the free list consumer index, we use the same 1142 * logic as in iflib_rxeof(). 1143 */ 1144 if (have_rxcq) 1145 cidxp = &rxq->ifr_cq_cidx; 1146 else 1147 cidxp = &fl->ifl_cidx; 1148 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1149 rxq->ifr_id, *cidxp, USHRT_MAX); 1150 1151 nic_i = fl->ifl_cidx; 1152 nm_i = netmap_idx_n2k(kring, nic_i); 1153 MPASS(nm_i == kring->nr_hwtail); 1154 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1155 rxd_info_zero(&ri); 1156 ri.iri_frags = rxq->ifr_frags; 1157 ri.iri_qsidx = kring->ring_id; 1158 ri.iri_ifp = ctx->ifc_ifp; 1159 ri.iri_cidx = *cidxp; 1160 1161 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1162 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1163 ring->slot[nm_i].flags = 0; 1164 if (have_rxcq) { 1165 *cidxp = ri.iri_cidx; 1166 while (*cidxp >= scctx->isc_nrxd[0]) 1167 *cidxp -= scctx->isc_nrxd[0]; 1168 } 1169 bus_dmamap_sync(fl->ifl_buf_tag, 1170 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1171 nm_i = nm_next(nm_i, lim); 1172 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1173 } 1174 if (n) { /* update the state variables */ 1175 if (netmap_no_pendintr && !force_update) { 1176 /* diagnostics */ 1177 iflib_rx_miss ++; 1178 iflib_rx_miss_bufs += n; 1179 } 1180 kring->nr_hwtail = nm_i; 1181 } 1182 kring->nr_kflags &= ~NKR_PENDINTR; 1183 } 1184 /* 1185 * Second part: skip past packets that userspace has released. 1186 * (kring->nr_hwcur to head excluded), 1187 * and make the buffers available for reception. 1188 * As usual nm_i is the index in the netmap ring, 1189 * nic_i is the index in the NIC ring, and 1190 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1191 */ 1192 netmap_fl_refill(rxq, kring, false); 1193 1194 return (0); 1195 } 1196 1197 static void 1198 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1199 { 1200 if_ctx_t ctx = na->ifp->if_softc; 1201 1202 CTX_LOCK(ctx); 1203 if (onoff) { 1204 IFDI_INTR_ENABLE(ctx); 1205 } else { 1206 IFDI_INTR_DISABLE(ctx); 1207 } 1208 CTX_UNLOCK(ctx); 1209 } 1210 1211 static int 1212 iflib_netmap_attach(if_ctx_t ctx) 1213 { 1214 struct netmap_adapter na; 1215 1216 bzero(&na, sizeof(na)); 1217 1218 na.ifp = ctx->ifc_ifp; 1219 na.na_flags = NAF_BDG_MAYSLEEP; 1220 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1221 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1222 1223 na.num_tx_desc = iflib_num_tx_descs(ctx); 1224 na.num_rx_desc = iflib_num_rx_descs(ctx); 1225 na.nm_txsync = iflib_netmap_txsync; 1226 na.nm_rxsync = iflib_netmap_rxsync; 1227 na.nm_register = iflib_netmap_register; 1228 na.nm_intr = iflib_netmap_intr; 1229 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1230 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1231 return (netmap_attach(&na)); 1232 } 1233 1234 static int 1235 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1236 { 1237 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1238 struct netmap_slot *slot; 1239 1240 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1241 if (slot == NULL) 1242 return (0); 1243 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1244 /* 1245 * In netmap mode, set the map for the packet buffer. 1246 * NOTE: Some drivers (not this one) also need to set 1247 * the physical buffer address in the NIC ring. 1248 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1249 * netmap slot index, si 1250 */ 1251 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1252 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1253 NMB(na, slot + si)); 1254 } 1255 return (1); 1256 } 1257 1258 static int 1259 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1260 { 1261 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1262 struct netmap_kring *kring; 1263 struct netmap_slot *slot; 1264 1265 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1266 if (slot == NULL) 1267 return (0); 1268 kring = na->rx_rings[rxq->ifr_id]; 1269 netmap_fl_refill(rxq, kring, true); 1270 return (1); 1271 } 1272 1273 static void 1274 iflib_netmap_timer(void *arg) 1275 { 1276 iflib_txq_t txq = arg; 1277 if_ctx_t ctx = txq->ift_ctx; 1278 1279 /* 1280 * Wake up the netmap application, to give it a chance to 1281 * call txsync and reclaim more completed TX buffers. 1282 */ 1283 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1284 } 1285 1286 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1287 1288 #else 1289 #define iflib_netmap_txq_init(ctx, txq) (0) 1290 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1291 #define iflib_netmap_detach(ifp) 1292 1293 #define iflib_netmap_attach(ctx) (0) 1294 #define netmap_rx_irq(ifp, qid, budget) (0) 1295 #endif 1296 1297 #if defined(__i386__) || defined(__amd64__) 1298 static __inline void 1299 prefetch(void *x) 1300 { 1301 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1302 } 1303 static __inline void 1304 prefetch2cachelines(void *x) 1305 { 1306 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1307 #if (CACHE_LINE_SIZE < 128) 1308 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1309 #endif 1310 } 1311 #else 1312 #define prefetch(x) 1313 #define prefetch2cachelines(x) 1314 #endif 1315 1316 static void 1317 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1318 { 1319 iflib_fl_t fl; 1320 1321 fl = &rxq->ifr_fl[flid]; 1322 iru->iru_paddrs = fl->ifl_bus_addrs; 1323 iru->iru_idxs = fl->ifl_rxd_idxs; 1324 iru->iru_qsidx = rxq->ifr_id; 1325 iru->iru_buf_size = fl->ifl_buf_size; 1326 iru->iru_flidx = fl->ifl_id; 1327 } 1328 1329 static void 1330 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1331 { 1332 if (err) 1333 return; 1334 *(bus_addr_t *) arg = segs[0].ds_addr; 1335 } 1336 1337 int 1338 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1339 { 1340 int err; 1341 device_t dev = ctx->ifc_dev; 1342 1343 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1344 align, 0, /* alignment, bounds */ 1345 BUS_SPACE_MAXADDR, /* lowaddr */ 1346 BUS_SPACE_MAXADDR, /* highaddr */ 1347 NULL, NULL, /* filter, filterarg */ 1348 size, /* maxsize */ 1349 1, /* nsegments */ 1350 size, /* maxsegsize */ 1351 BUS_DMA_ALLOCNOW, /* flags */ 1352 NULL, /* lockfunc */ 1353 NULL, /* lockarg */ 1354 &dma->idi_tag); 1355 if (err) { 1356 device_printf(dev, 1357 "%s: bus_dma_tag_create failed: %d\n", 1358 __func__, err); 1359 goto fail_0; 1360 } 1361 1362 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1363 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1364 if (err) { 1365 device_printf(dev, 1366 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1367 __func__, (uintmax_t)size, err); 1368 goto fail_1; 1369 } 1370 1371 dma->idi_paddr = IF_BAD_DMA; 1372 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1373 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1374 if (err || dma->idi_paddr == IF_BAD_DMA) { 1375 device_printf(dev, 1376 "%s: bus_dmamap_load failed: %d\n", 1377 __func__, err); 1378 goto fail_2; 1379 } 1380 1381 dma->idi_size = size; 1382 return (0); 1383 1384 fail_2: 1385 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1386 fail_1: 1387 bus_dma_tag_destroy(dma->idi_tag); 1388 fail_0: 1389 dma->idi_tag = NULL; 1390 1391 return (err); 1392 } 1393 1394 int 1395 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1396 { 1397 if_shared_ctx_t sctx = ctx->ifc_sctx; 1398 1399 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1400 1401 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1402 } 1403 1404 int 1405 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1406 { 1407 int i, err; 1408 iflib_dma_info_t *dmaiter; 1409 1410 dmaiter = dmalist; 1411 for (i = 0; i < count; i++, dmaiter++) { 1412 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1413 break; 1414 } 1415 if (err) 1416 iflib_dma_free_multi(dmalist, i); 1417 return (err); 1418 } 1419 1420 void 1421 iflib_dma_free(iflib_dma_info_t dma) 1422 { 1423 if (dma->idi_tag == NULL) 1424 return; 1425 if (dma->idi_paddr != IF_BAD_DMA) { 1426 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1427 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1428 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1429 dma->idi_paddr = IF_BAD_DMA; 1430 } 1431 if (dma->idi_vaddr != NULL) { 1432 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1433 dma->idi_vaddr = NULL; 1434 } 1435 bus_dma_tag_destroy(dma->idi_tag); 1436 dma->idi_tag = NULL; 1437 } 1438 1439 void 1440 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1441 { 1442 int i; 1443 iflib_dma_info_t *dmaiter = dmalist; 1444 1445 for (i = 0; i < count; i++, dmaiter++) 1446 iflib_dma_free(*dmaiter); 1447 } 1448 1449 static int 1450 iflib_fast_intr(void *arg) 1451 { 1452 iflib_filter_info_t info = arg; 1453 struct grouptask *gtask = info->ifi_task; 1454 int result; 1455 1456 DBG_COUNTER_INC(fast_intrs); 1457 if (info->ifi_filter != NULL) { 1458 result = info->ifi_filter(info->ifi_filter_arg); 1459 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1460 return (result); 1461 } 1462 1463 GROUPTASK_ENQUEUE(gtask); 1464 return (FILTER_HANDLED); 1465 } 1466 1467 static int 1468 iflib_fast_intr_rxtx(void *arg) 1469 { 1470 iflib_filter_info_t info = arg; 1471 struct grouptask *gtask = info->ifi_task; 1472 if_ctx_t ctx; 1473 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1474 iflib_txq_t txq; 1475 void *sc; 1476 int i, cidx, result; 1477 qidx_t txqid; 1478 bool intr_enable, intr_legacy; 1479 1480 DBG_COUNTER_INC(fast_intrs); 1481 if (info->ifi_filter != NULL) { 1482 result = info->ifi_filter(info->ifi_filter_arg); 1483 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1484 return (result); 1485 } 1486 1487 ctx = rxq->ifr_ctx; 1488 sc = ctx->ifc_softc; 1489 intr_enable = false; 1490 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1491 MPASS(rxq->ifr_ntxqirq); 1492 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1493 txqid = rxq->ifr_txqid[i]; 1494 txq = &ctx->ifc_txqs[txqid]; 1495 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1496 BUS_DMASYNC_POSTREAD); 1497 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1498 if (intr_legacy) 1499 intr_enable = true; 1500 else 1501 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1502 continue; 1503 } 1504 GROUPTASK_ENQUEUE(&txq->ift_task); 1505 } 1506 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1507 cidx = rxq->ifr_cq_cidx; 1508 else 1509 cidx = rxq->ifr_fl[0].ifl_cidx; 1510 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1511 GROUPTASK_ENQUEUE(gtask); 1512 else { 1513 if (intr_legacy) 1514 intr_enable = true; 1515 else 1516 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1517 DBG_COUNTER_INC(rx_intr_enables); 1518 } 1519 if (intr_enable) 1520 IFDI_INTR_ENABLE(ctx); 1521 return (FILTER_HANDLED); 1522 } 1523 1524 static int 1525 iflib_fast_intr_ctx(void *arg) 1526 { 1527 iflib_filter_info_t info = arg; 1528 struct grouptask *gtask = info->ifi_task; 1529 int result; 1530 1531 DBG_COUNTER_INC(fast_intrs); 1532 if (info->ifi_filter != NULL) { 1533 result = info->ifi_filter(info->ifi_filter_arg); 1534 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1535 return (result); 1536 } 1537 1538 GROUPTASK_ENQUEUE(gtask); 1539 return (FILTER_HANDLED); 1540 } 1541 1542 static int 1543 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1544 driver_filter_t filter, driver_intr_t handler, void *arg, 1545 const char *name) 1546 { 1547 struct resource *res; 1548 void *tag = NULL; 1549 device_t dev = ctx->ifc_dev; 1550 int flags, i, rc; 1551 1552 flags = RF_ACTIVE; 1553 if (ctx->ifc_flags & IFC_LEGACY) 1554 flags |= RF_SHAREABLE; 1555 MPASS(rid < 512); 1556 i = rid; 1557 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1558 if (res == NULL) { 1559 device_printf(dev, 1560 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1561 return (ENOMEM); 1562 } 1563 irq->ii_res = res; 1564 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1565 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1566 filter, handler, arg, &tag); 1567 if (rc != 0) { 1568 device_printf(dev, 1569 "failed to setup interrupt for rid %d, name %s: %d\n", 1570 rid, name ? name : "unknown", rc); 1571 return (rc); 1572 } else if (name) 1573 bus_describe_intr(dev, res, tag, "%s", name); 1574 1575 irq->ii_tag = tag; 1576 return (0); 1577 } 1578 1579 /********************************************************************* 1580 * 1581 * Allocate DMA resources for TX buffers as well as memory for the TX 1582 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1583 * iflib_sw_tx_desc_array structure, storing all the information that 1584 * is needed to transmit a packet on the wire. This is called only 1585 * once at attach, setup is done every reset. 1586 * 1587 **********************************************************************/ 1588 static int 1589 iflib_txsd_alloc(iflib_txq_t txq) 1590 { 1591 if_ctx_t ctx = txq->ift_ctx; 1592 if_shared_ctx_t sctx = ctx->ifc_sctx; 1593 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1594 device_t dev = ctx->ifc_dev; 1595 bus_size_t tsomaxsize; 1596 int err, nsegments, ntsosegments; 1597 bool tso; 1598 1599 nsegments = scctx->isc_tx_nsegments; 1600 ntsosegments = scctx->isc_tx_tso_segments_max; 1601 tsomaxsize = scctx->isc_tx_tso_size_max; 1602 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1603 tsomaxsize += sizeof(struct ether_vlan_header); 1604 MPASS(scctx->isc_ntxd[0] > 0); 1605 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1606 MPASS(nsegments > 0); 1607 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1608 MPASS(ntsosegments > 0); 1609 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1610 } 1611 1612 /* 1613 * Set up DMA tags for TX buffers. 1614 */ 1615 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1616 1, 0, /* alignment, bounds */ 1617 BUS_SPACE_MAXADDR, /* lowaddr */ 1618 BUS_SPACE_MAXADDR, /* highaddr */ 1619 NULL, NULL, /* filter, filterarg */ 1620 sctx->isc_tx_maxsize, /* maxsize */ 1621 nsegments, /* nsegments */ 1622 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1623 0, /* flags */ 1624 NULL, /* lockfunc */ 1625 NULL, /* lockfuncarg */ 1626 &txq->ift_buf_tag))) { 1627 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1628 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1629 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1630 goto fail; 1631 } 1632 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1633 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1634 1, 0, /* alignment, bounds */ 1635 BUS_SPACE_MAXADDR, /* lowaddr */ 1636 BUS_SPACE_MAXADDR, /* highaddr */ 1637 NULL, NULL, /* filter, filterarg */ 1638 tsomaxsize, /* maxsize */ 1639 ntsosegments, /* nsegments */ 1640 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1641 0, /* flags */ 1642 NULL, /* lockfunc */ 1643 NULL, /* lockfuncarg */ 1644 &txq->ift_tso_buf_tag))) { 1645 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1646 err); 1647 goto fail; 1648 } 1649 1650 /* Allocate memory for the TX mbuf map. */ 1651 if (!(txq->ift_sds.ifsd_m = 1652 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1653 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1654 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1655 err = ENOMEM; 1656 goto fail; 1657 } 1658 1659 /* 1660 * Create the DMA maps for TX buffers. 1661 */ 1662 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1663 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1664 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1665 device_printf(dev, 1666 "Unable to allocate TX buffer DMA map memory\n"); 1667 err = ENOMEM; 1668 goto fail; 1669 } 1670 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1671 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1672 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1673 device_printf(dev, 1674 "Unable to allocate TSO TX buffer map memory\n"); 1675 err = ENOMEM; 1676 goto fail; 1677 } 1678 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1679 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1680 &txq->ift_sds.ifsd_map[i]); 1681 if (err != 0) { 1682 device_printf(dev, "Unable to create TX DMA map\n"); 1683 goto fail; 1684 } 1685 if (!tso) 1686 continue; 1687 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1688 &txq->ift_sds.ifsd_tso_map[i]); 1689 if (err != 0) { 1690 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1691 goto fail; 1692 } 1693 } 1694 return (0); 1695 fail: 1696 /* We free all, it handles case where we are in the middle */ 1697 iflib_tx_structures_free(ctx); 1698 return (err); 1699 } 1700 1701 static void 1702 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1703 { 1704 bus_dmamap_t map; 1705 1706 if (txq->ift_sds.ifsd_map != NULL) { 1707 map = txq->ift_sds.ifsd_map[i]; 1708 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1709 bus_dmamap_unload(txq->ift_buf_tag, map); 1710 bus_dmamap_destroy(txq->ift_buf_tag, map); 1711 txq->ift_sds.ifsd_map[i] = NULL; 1712 } 1713 1714 if (txq->ift_sds.ifsd_tso_map != NULL) { 1715 map = txq->ift_sds.ifsd_tso_map[i]; 1716 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1717 BUS_DMASYNC_POSTWRITE); 1718 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1719 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1720 txq->ift_sds.ifsd_tso_map[i] = NULL; 1721 } 1722 } 1723 1724 static void 1725 iflib_txq_destroy(iflib_txq_t txq) 1726 { 1727 if_ctx_t ctx = txq->ift_ctx; 1728 1729 for (int i = 0; i < txq->ift_size; i++) 1730 iflib_txsd_destroy(ctx, txq, i); 1731 1732 if (txq->ift_br != NULL) { 1733 ifmp_ring_free(txq->ift_br); 1734 txq->ift_br = NULL; 1735 } 1736 1737 mtx_destroy(&txq->ift_mtx); 1738 1739 if (txq->ift_sds.ifsd_map != NULL) { 1740 free(txq->ift_sds.ifsd_map, M_IFLIB); 1741 txq->ift_sds.ifsd_map = NULL; 1742 } 1743 if (txq->ift_sds.ifsd_tso_map != NULL) { 1744 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1745 txq->ift_sds.ifsd_tso_map = NULL; 1746 } 1747 if (txq->ift_sds.ifsd_m != NULL) { 1748 free(txq->ift_sds.ifsd_m, M_IFLIB); 1749 txq->ift_sds.ifsd_m = NULL; 1750 } 1751 if (txq->ift_buf_tag != NULL) { 1752 bus_dma_tag_destroy(txq->ift_buf_tag); 1753 txq->ift_buf_tag = NULL; 1754 } 1755 if (txq->ift_tso_buf_tag != NULL) { 1756 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1757 txq->ift_tso_buf_tag = NULL; 1758 } 1759 if (txq->ift_ifdi != NULL) { 1760 free(txq->ift_ifdi, M_IFLIB); 1761 } 1762 } 1763 1764 static void 1765 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1766 { 1767 struct mbuf **mp; 1768 1769 mp = &txq->ift_sds.ifsd_m[i]; 1770 if (*mp == NULL) 1771 return; 1772 1773 if (txq->ift_sds.ifsd_map != NULL) { 1774 bus_dmamap_sync(txq->ift_buf_tag, 1775 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1776 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1777 } 1778 if (txq->ift_sds.ifsd_tso_map != NULL) { 1779 bus_dmamap_sync(txq->ift_tso_buf_tag, 1780 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1781 bus_dmamap_unload(txq->ift_tso_buf_tag, 1782 txq->ift_sds.ifsd_tso_map[i]); 1783 } 1784 m_freem(*mp); 1785 DBG_COUNTER_INC(tx_frees); 1786 *mp = NULL; 1787 } 1788 1789 static int 1790 iflib_txq_setup(iflib_txq_t txq) 1791 { 1792 if_ctx_t ctx = txq->ift_ctx; 1793 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1794 if_shared_ctx_t sctx = ctx->ifc_sctx; 1795 iflib_dma_info_t di; 1796 int i; 1797 1798 /* Set number of descriptors available */ 1799 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1800 /* XXX make configurable */ 1801 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1802 1803 /* Reset indices */ 1804 txq->ift_cidx_processed = 0; 1805 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1806 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1807 1808 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1809 bzero((void *)di->idi_vaddr, di->idi_size); 1810 1811 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1812 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1813 bus_dmamap_sync(di->idi_tag, di->idi_map, 1814 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1815 return (0); 1816 } 1817 1818 /********************************************************************* 1819 * 1820 * Allocate DMA resources for RX buffers as well as memory for the RX 1821 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1822 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1823 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1824 * Since we use use one entry in iflib_sw_rx_desc_array per received 1825 * packet, the maximum number of entries we'll need is equal to the 1826 * number of hardware receive descriptors that we've allocated. 1827 * 1828 **********************************************************************/ 1829 static int 1830 iflib_rxsd_alloc(iflib_rxq_t rxq) 1831 { 1832 if_ctx_t ctx = rxq->ifr_ctx; 1833 if_shared_ctx_t sctx = ctx->ifc_sctx; 1834 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1835 device_t dev = ctx->ifc_dev; 1836 iflib_fl_t fl; 1837 int err; 1838 1839 MPASS(scctx->isc_nrxd[0] > 0); 1840 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1841 1842 fl = rxq->ifr_fl; 1843 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1844 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1845 /* Set up DMA tag for RX buffers. */ 1846 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1847 1, 0, /* alignment, bounds */ 1848 BUS_SPACE_MAXADDR, /* lowaddr */ 1849 BUS_SPACE_MAXADDR, /* highaddr */ 1850 NULL, NULL, /* filter, filterarg */ 1851 sctx->isc_rx_maxsize, /* maxsize */ 1852 sctx->isc_rx_nsegments, /* nsegments */ 1853 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1854 0, /* flags */ 1855 NULL, /* lockfunc */ 1856 NULL, /* lockarg */ 1857 &fl->ifl_buf_tag); 1858 if (err) { 1859 device_printf(dev, 1860 "Unable to allocate RX DMA tag: %d\n", err); 1861 goto fail; 1862 } 1863 1864 /* Allocate memory for the RX mbuf map. */ 1865 if (!(fl->ifl_sds.ifsd_m = 1866 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1867 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1868 device_printf(dev, 1869 "Unable to allocate RX mbuf map memory\n"); 1870 err = ENOMEM; 1871 goto fail; 1872 } 1873 1874 /* Allocate memory for the direct RX cluster pointer map. */ 1875 if (!(fl->ifl_sds.ifsd_cl = 1876 (caddr_t *) malloc(sizeof(caddr_t) * 1877 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1878 device_printf(dev, 1879 "Unable to allocate RX cluster map memory\n"); 1880 err = ENOMEM; 1881 goto fail; 1882 } 1883 1884 /* Allocate memory for the RX cluster bus address map. */ 1885 if (!(fl->ifl_sds.ifsd_ba = 1886 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1887 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1888 device_printf(dev, 1889 "Unable to allocate RX bus address map memory\n"); 1890 err = ENOMEM; 1891 goto fail; 1892 } 1893 1894 /* 1895 * Create the DMA maps for RX buffers. 1896 */ 1897 if (!(fl->ifl_sds.ifsd_map = 1898 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1899 device_printf(dev, 1900 "Unable to allocate RX buffer DMA map memory\n"); 1901 err = ENOMEM; 1902 goto fail; 1903 } 1904 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1905 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1906 &fl->ifl_sds.ifsd_map[i]); 1907 if (err != 0) { 1908 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1909 goto fail; 1910 } 1911 } 1912 } 1913 return (0); 1914 1915 fail: 1916 iflib_rx_structures_free(ctx); 1917 return (err); 1918 } 1919 1920 /* 1921 * Internal service routines 1922 */ 1923 1924 struct rxq_refill_cb_arg { 1925 int error; 1926 bus_dma_segment_t seg; 1927 int nseg; 1928 }; 1929 1930 static void 1931 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1932 { 1933 struct rxq_refill_cb_arg *cb_arg = arg; 1934 1935 cb_arg->error = error; 1936 cb_arg->seg = segs[0]; 1937 cb_arg->nseg = nseg; 1938 } 1939 1940 /** 1941 * iflib_fl_refill - refill an rxq free-buffer list 1942 * @ctx: the iflib context 1943 * @fl: the free list to refill 1944 * @count: the number of new buffers to allocate 1945 * 1946 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 1947 * The caller must assure that @count does not exceed the queue's capacity 1948 * minus one (since we always leave a descriptor unavailable). 1949 */ 1950 static uint8_t 1951 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1952 { 1953 struct if_rxd_update iru; 1954 struct rxq_refill_cb_arg cb_arg; 1955 struct mbuf *m; 1956 caddr_t cl, *sd_cl; 1957 struct mbuf **sd_m; 1958 bus_dmamap_t *sd_map; 1959 bus_addr_t bus_addr, *sd_ba; 1960 int err, frag_idx, i, idx, n, pidx; 1961 qidx_t credits; 1962 1963 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 1964 1965 sd_m = fl->ifl_sds.ifsd_m; 1966 sd_map = fl->ifl_sds.ifsd_map; 1967 sd_cl = fl->ifl_sds.ifsd_cl; 1968 sd_ba = fl->ifl_sds.ifsd_ba; 1969 pidx = fl->ifl_pidx; 1970 idx = pidx; 1971 frag_idx = fl->ifl_fragidx; 1972 credits = fl->ifl_credits; 1973 1974 i = 0; 1975 n = count; 1976 MPASS(n > 0); 1977 MPASS(credits + n <= fl->ifl_size); 1978 1979 if (pidx < fl->ifl_cidx) 1980 MPASS(pidx + n <= fl->ifl_cidx); 1981 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1982 MPASS(fl->ifl_gen == 0); 1983 if (pidx > fl->ifl_cidx) 1984 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1985 1986 DBG_COUNTER_INC(fl_refills); 1987 if (n > 8) 1988 DBG_COUNTER_INC(fl_refills_large); 1989 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1990 while (n-- > 0) { 1991 /* 1992 * We allocate an uninitialized mbuf + cluster, mbuf is 1993 * initialized after rx. 1994 * 1995 * If the cluster is still set then we know a minimum sized 1996 * packet was received 1997 */ 1998 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 1999 &frag_idx); 2000 if (frag_idx < 0) 2001 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2002 MPASS(frag_idx >= 0); 2003 if ((cl = sd_cl[frag_idx]) == NULL) { 2004 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2005 if (__predict_false(cl == NULL)) 2006 break; 2007 2008 cb_arg.error = 0; 2009 MPASS(sd_map != NULL); 2010 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2011 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2012 BUS_DMA_NOWAIT); 2013 if (__predict_false(err != 0 || cb_arg.error)) { 2014 uma_zfree(fl->ifl_zone, cl); 2015 break; 2016 } 2017 2018 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2019 sd_cl[frag_idx] = cl; 2020 #if MEMORY_LOGGING 2021 fl->ifl_cl_enqueued++; 2022 #endif 2023 } else { 2024 bus_addr = sd_ba[frag_idx]; 2025 } 2026 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2027 BUS_DMASYNC_PREREAD); 2028 2029 if (sd_m[frag_idx] == NULL) { 2030 m = m_gethdr(M_NOWAIT, MT_NOINIT); 2031 if (__predict_false(m == NULL)) 2032 break; 2033 sd_m[frag_idx] = m; 2034 } 2035 bit_set(fl->ifl_rx_bitmap, frag_idx); 2036 #if MEMORY_LOGGING 2037 fl->ifl_m_enqueued++; 2038 #endif 2039 2040 DBG_COUNTER_INC(rx_allocs); 2041 fl->ifl_rxd_idxs[i] = frag_idx; 2042 fl->ifl_bus_addrs[i] = bus_addr; 2043 credits++; 2044 i++; 2045 MPASS(credits <= fl->ifl_size); 2046 if (++idx == fl->ifl_size) { 2047 #ifdef INVARIANTS 2048 fl->ifl_gen = 1; 2049 #endif 2050 idx = 0; 2051 } 2052 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2053 iru.iru_pidx = pidx; 2054 iru.iru_count = i; 2055 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2056 fl->ifl_pidx = idx; 2057 fl->ifl_credits = credits; 2058 pidx = idx; 2059 i = 0; 2060 } 2061 } 2062 2063 if (n < count - 1) { 2064 if (i != 0) { 2065 iru.iru_pidx = pidx; 2066 iru.iru_count = i; 2067 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2068 fl->ifl_pidx = idx; 2069 fl->ifl_credits = credits; 2070 } 2071 DBG_COUNTER_INC(rxd_flush); 2072 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2073 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2074 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2075 fl->ifl_id, fl->ifl_pidx); 2076 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2077 fl->ifl_fragidx = frag_idx + 1; 2078 if (fl->ifl_fragidx == fl->ifl_size) 2079 fl->ifl_fragidx = 0; 2080 } else { 2081 fl->ifl_fragidx = frag_idx; 2082 } 2083 } 2084 2085 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2086 } 2087 2088 static inline uint8_t 2089 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2090 { 2091 /* 2092 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2093 * This is important as it confuses most NICs. For instance, 2094 * Intel NICs have (per receive ring) RDH and RDT registers, where 2095 * RDH points to the next receive descriptor to be used by the NIC, 2096 * and RDT for the next receive descriptor to be published by the 2097 * driver to the NIC (RDT - 1 is thus the last valid one). 2098 * The condition RDH == RDT means no descriptors are available to 2099 * the NIC, and thus it would be ambiguous if it also meant that 2100 * all the descriptors are available to the NIC. 2101 */ 2102 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2103 #ifdef INVARIANTS 2104 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2105 #endif 2106 2107 MPASS(fl->ifl_credits <= fl->ifl_size); 2108 MPASS(reclaimable == delta); 2109 2110 if (reclaimable > 0) 2111 return (iflib_fl_refill(ctx, fl, reclaimable)); 2112 return (0); 2113 } 2114 2115 uint8_t 2116 iflib_in_detach(if_ctx_t ctx) 2117 { 2118 bool in_detach; 2119 2120 STATE_LOCK(ctx); 2121 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2122 STATE_UNLOCK(ctx); 2123 return (in_detach); 2124 } 2125 2126 static void 2127 iflib_fl_bufs_free(iflib_fl_t fl) 2128 { 2129 iflib_dma_info_t idi = fl->ifl_ifdi; 2130 bus_dmamap_t sd_map; 2131 uint32_t i; 2132 2133 for (i = 0; i < fl->ifl_size; i++) { 2134 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2135 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2136 2137 if (*sd_cl != NULL) { 2138 sd_map = fl->ifl_sds.ifsd_map[i]; 2139 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2140 BUS_DMASYNC_POSTREAD); 2141 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2142 uma_zfree(fl->ifl_zone, *sd_cl); 2143 *sd_cl = NULL; 2144 if (*sd_m != NULL) { 2145 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2146 uma_zfree(zone_mbuf, *sd_m); 2147 *sd_m = NULL; 2148 } 2149 } else { 2150 MPASS(*sd_m == NULL); 2151 } 2152 #if MEMORY_LOGGING 2153 fl->ifl_m_dequeued++; 2154 fl->ifl_cl_dequeued++; 2155 #endif 2156 } 2157 #ifdef INVARIANTS 2158 for (i = 0; i < fl->ifl_size; i++) { 2159 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2160 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2161 } 2162 #endif 2163 /* 2164 * Reset free list values 2165 */ 2166 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2167 bzero(idi->idi_vaddr, idi->idi_size); 2168 } 2169 2170 /********************************************************************* 2171 * 2172 * Initialize a free list and its buffers. 2173 * 2174 **********************************************************************/ 2175 static int 2176 iflib_fl_setup(iflib_fl_t fl) 2177 { 2178 iflib_rxq_t rxq = fl->ifl_rxq; 2179 if_ctx_t ctx = rxq->ifr_ctx; 2180 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2181 int qidx; 2182 2183 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2184 /* 2185 ** Free current RX buffer structs and their mbufs 2186 */ 2187 iflib_fl_bufs_free(fl); 2188 /* Now replenish the mbufs */ 2189 MPASS(fl->ifl_credits == 0); 2190 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2191 if (scctx->isc_rxd_buf_size[qidx] != 0) 2192 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2193 else 2194 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2195 /* 2196 * ifl_buf_size may be a driver-supplied value, so pull it up 2197 * to the selected mbuf size. 2198 */ 2199 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2200 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2201 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2202 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2203 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2204 2205 /* 2206 * Avoid pre-allocating zillions of clusters to an idle card 2207 * potentially speeding up attach. In any case make sure 2208 * to leave a descriptor unavailable. See the comment in 2209 * iflib_fl_refill_all(). 2210 */ 2211 MPASS(fl->ifl_size > 0); 2212 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2213 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2214 return (ENOBUFS); 2215 /* 2216 * handle failure 2217 */ 2218 MPASS(rxq != NULL); 2219 MPASS(fl->ifl_ifdi != NULL); 2220 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2221 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2222 return (0); 2223 } 2224 2225 /********************************************************************* 2226 * 2227 * Free receive ring data structures 2228 * 2229 **********************************************************************/ 2230 static void 2231 iflib_rx_sds_free(iflib_rxq_t rxq) 2232 { 2233 iflib_fl_t fl; 2234 int i, j; 2235 2236 if (rxq->ifr_fl != NULL) { 2237 for (i = 0; i < rxq->ifr_nfl; i++) { 2238 fl = &rxq->ifr_fl[i]; 2239 if (fl->ifl_buf_tag != NULL) { 2240 if (fl->ifl_sds.ifsd_map != NULL) { 2241 for (j = 0; j < fl->ifl_size; j++) { 2242 bus_dmamap_sync( 2243 fl->ifl_buf_tag, 2244 fl->ifl_sds.ifsd_map[j], 2245 BUS_DMASYNC_POSTREAD); 2246 bus_dmamap_unload( 2247 fl->ifl_buf_tag, 2248 fl->ifl_sds.ifsd_map[j]); 2249 bus_dmamap_destroy( 2250 fl->ifl_buf_tag, 2251 fl->ifl_sds.ifsd_map[j]); 2252 } 2253 } 2254 bus_dma_tag_destroy(fl->ifl_buf_tag); 2255 fl->ifl_buf_tag = NULL; 2256 } 2257 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2258 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2259 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2260 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2261 fl->ifl_sds.ifsd_m = NULL; 2262 fl->ifl_sds.ifsd_cl = NULL; 2263 fl->ifl_sds.ifsd_ba = NULL; 2264 fl->ifl_sds.ifsd_map = NULL; 2265 } 2266 free(rxq->ifr_fl, M_IFLIB); 2267 rxq->ifr_fl = NULL; 2268 free(rxq->ifr_ifdi, M_IFLIB); 2269 rxq->ifr_ifdi = NULL; 2270 rxq->ifr_cq_cidx = 0; 2271 } 2272 } 2273 2274 /* 2275 * Timer routine 2276 */ 2277 static void 2278 iflib_timer(void *arg) 2279 { 2280 iflib_txq_t txq = arg; 2281 if_ctx_t ctx = txq->ift_ctx; 2282 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2283 uint64_t this_tick = ticks; 2284 2285 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2286 return; 2287 2288 /* 2289 ** Check on the state of the TX queue(s), this 2290 ** can be done without the lock because its RO 2291 ** and the HUNG state will be static if set. 2292 */ 2293 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2294 txq->ift_last_timer_tick = this_tick; 2295 IFDI_TIMER(ctx, txq->ift_id); 2296 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2297 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2298 (sctx->isc_pause_frames == 0))) 2299 goto hung; 2300 2301 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2302 ifmp_ring_is_stalled(txq->ift_br)) { 2303 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down")); 2304 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2305 } 2306 txq->ift_cleaned_prev = txq->ift_cleaned; 2307 } 2308 /* handle any laggards */ 2309 if (txq->ift_db_pending) 2310 GROUPTASK_ENQUEUE(&txq->ift_task); 2311 2312 sctx->isc_pause_frames = 0; 2313 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2314 callout_reset_on(&txq->ift_timer, hz / 2, iflib_timer, txq, txq->ift_timer.c_cpu); 2315 return; 2316 2317 hung: 2318 device_printf(ctx->ifc_dev, 2319 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2320 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2321 STATE_LOCK(ctx); 2322 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2323 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2324 iflib_admin_intr_deferred(ctx); 2325 STATE_UNLOCK(ctx); 2326 } 2327 2328 static uint16_t 2329 iflib_get_mbuf_size_for(unsigned int size) 2330 { 2331 2332 if (size <= MCLBYTES) 2333 return (MCLBYTES); 2334 else 2335 return (MJUMPAGESIZE); 2336 } 2337 2338 static void 2339 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2340 { 2341 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2342 2343 /* 2344 * XXX don't set the max_frame_size to larger 2345 * than the hardware can handle 2346 */ 2347 ctx->ifc_rx_mbuf_sz = 2348 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2349 } 2350 2351 uint32_t 2352 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2353 { 2354 2355 return (ctx->ifc_rx_mbuf_sz); 2356 } 2357 2358 static void 2359 iflib_init_locked(if_ctx_t ctx) 2360 { 2361 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2362 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2363 if_t ifp = ctx->ifc_ifp; 2364 iflib_fl_t fl; 2365 iflib_txq_t txq; 2366 iflib_rxq_t rxq; 2367 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2368 2369 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2370 IFDI_INTR_DISABLE(ctx); 2371 2372 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2373 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2374 /* Set hardware offload abilities */ 2375 if_clearhwassist(ifp); 2376 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2377 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2378 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2379 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2380 if (if_getcapenable(ifp) & IFCAP_TSO4) 2381 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2382 if (if_getcapenable(ifp) & IFCAP_TSO6) 2383 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2384 2385 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2386 CALLOUT_LOCK(txq); 2387 callout_stop(&txq->ift_timer); 2388 #ifdef DEV_NETMAP 2389 callout_stop(&txq->ift_netmap_timer); 2390 #endif /* DEV_NETMAP */ 2391 CALLOUT_UNLOCK(txq); 2392 iflib_netmap_txq_init(ctx, txq); 2393 } 2394 2395 /* 2396 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2397 * that drivers can use the value when setting up the hardware receive 2398 * buffers. 2399 */ 2400 iflib_calc_rx_mbuf_sz(ctx); 2401 2402 #ifdef INVARIANTS 2403 i = if_getdrvflags(ifp); 2404 #endif 2405 IFDI_INIT(ctx); 2406 MPASS(if_getdrvflags(ifp) == i); 2407 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2408 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2409 /* This rxq is in netmap mode. Skip normal init. */ 2410 continue; 2411 } 2412 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2413 if (iflib_fl_setup(fl)) { 2414 device_printf(ctx->ifc_dev, 2415 "setting up free list %d failed - " 2416 "check cluster settings\n", j); 2417 goto done; 2418 } 2419 } 2420 } 2421 done: 2422 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2423 IFDI_INTR_ENABLE(ctx); 2424 txq = ctx->ifc_txqs; 2425 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2426 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2427 txq->ift_timer.c_cpu); 2428 } 2429 2430 static int 2431 iflib_media_change(if_t ifp) 2432 { 2433 if_ctx_t ctx = if_getsoftc(ifp); 2434 int err; 2435 2436 CTX_LOCK(ctx); 2437 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2438 iflib_init_locked(ctx); 2439 CTX_UNLOCK(ctx); 2440 return (err); 2441 } 2442 2443 static void 2444 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2445 { 2446 if_ctx_t ctx = if_getsoftc(ifp); 2447 2448 CTX_LOCK(ctx); 2449 IFDI_UPDATE_ADMIN_STATUS(ctx); 2450 IFDI_MEDIA_STATUS(ctx, ifmr); 2451 CTX_UNLOCK(ctx); 2452 } 2453 2454 void 2455 iflib_stop(if_ctx_t ctx) 2456 { 2457 iflib_txq_t txq = ctx->ifc_txqs; 2458 iflib_rxq_t rxq = ctx->ifc_rxqs; 2459 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2460 if_shared_ctx_t sctx = ctx->ifc_sctx; 2461 iflib_dma_info_t di; 2462 iflib_fl_t fl; 2463 int i, j; 2464 2465 /* Tell the stack that the interface is no longer active */ 2466 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2467 2468 IFDI_INTR_DISABLE(ctx); 2469 DELAY(1000); 2470 IFDI_STOP(ctx); 2471 DELAY(1000); 2472 2473 iflib_debug_reset(); 2474 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2475 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2476 /* make sure all transmitters have completed before proceeding XXX */ 2477 2478 CALLOUT_LOCK(txq); 2479 callout_stop(&txq->ift_timer); 2480 #ifdef DEV_NETMAP 2481 callout_stop(&txq->ift_netmap_timer); 2482 #endif /* DEV_NETMAP */ 2483 CALLOUT_UNLOCK(txq); 2484 2485 /* clean any enqueued buffers */ 2486 iflib_ifmp_purge(txq); 2487 /* Free any existing tx buffers. */ 2488 for (j = 0; j < txq->ift_size; j++) { 2489 iflib_txsd_free(ctx, txq, j); 2490 } 2491 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2492 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2493 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2494 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2495 txq->ift_pullups = 0; 2496 ifmp_ring_reset_stats(txq->ift_br); 2497 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2498 bzero((void *)di->idi_vaddr, di->idi_size); 2499 } 2500 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2501 /* make sure all transmitters have completed before proceeding XXX */ 2502 2503 rxq->ifr_cq_cidx = 0; 2504 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2505 bzero((void *)di->idi_vaddr, di->idi_size); 2506 /* also resets the free lists pidx/cidx */ 2507 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2508 iflib_fl_bufs_free(fl); 2509 } 2510 } 2511 2512 static inline caddr_t 2513 calc_next_rxd(iflib_fl_t fl, int cidx) 2514 { 2515 qidx_t size; 2516 int nrxd; 2517 caddr_t start, end, cur, next; 2518 2519 nrxd = fl->ifl_size; 2520 size = fl->ifl_rxd_size; 2521 start = fl->ifl_ifdi->idi_vaddr; 2522 2523 if (__predict_false(size == 0)) 2524 return (start); 2525 cur = start + size*cidx; 2526 end = start + size*nrxd; 2527 next = CACHE_PTR_NEXT(cur); 2528 return (next < end ? next : start); 2529 } 2530 2531 static inline void 2532 prefetch_pkts(iflib_fl_t fl, int cidx) 2533 { 2534 int nextptr; 2535 int nrxd = fl->ifl_size; 2536 caddr_t next_rxd; 2537 2538 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2539 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2540 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2541 next_rxd = calc_next_rxd(fl, cidx); 2542 prefetch(next_rxd); 2543 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2544 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2545 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2546 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2547 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2548 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2549 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2550 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2551 } 2552 2553 static struct mbuf * 2554 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2555 int *pf_rv, if_rxd_info_t ri) 2556 { 2557 bus_dmamap_t map; 2558 iflib_fl_t fl; 2559 caddr_t payload; 2560 struct mbuf *m; 2561 int flid, cidx, len, next; 2562 2563 map = NULL; 2564 flid = irf->irf_flid; 2565 cidx = irf->irf_idx; 2566 fl = &rxq->ifr_fl[flid]; 2567 sd->ifsd_fl = fl; 2568 m = fl->ifl_sds.ifsd_m[cidx]; 2569 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2570 fl->ifl_credits--; 2571 #if MEMORY_LOGGING 2572 fl->ifl_m_dequeued++; 2573 #endif 2574 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2575 prefetch_pkts(fl, cidx); 2576 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2577 prefetch(&fl->ifl_sds.ifsd_map[next]); 2578 map = fl->ifl_sds.ifsd_map[cidx]; 2579 2580 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2581 2582 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2583 irf->irf_len != 0) { 2584 payload = *sd->ifsd_cl; 2585 payload += ri->iri_pad; 2586 len = ri->iri_len - ri->iri_pad; 2587 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2588 len | PFIL_MEMPTR | PFIL_IN, NULL); 2589 switch (*pf_rv) { 2590 case PFIL_DROPPED: 2591 case PFIL_CONSUMED: 2592 /* 2593 * The filter ate it. Everything is recycled. 2594 */ 2595 m = NULL; 2596 unload = 0; 2597 break; 2598 case PFIL_REALLOCED: 2599 /* 2600 * The filter copied it. Everything is recycled. 2601 */ 2602 m = pfil_mem2mbuf(payload); 2603 unload = 0; 2604 break; 2605 case PFIL_PASS: 2606 /* 2607 * Filter said it was OK, so receive like 2608 * normal 2609 */ 2610 fl->ifl_sds.ifsd_m[cidx] = NULL; 2611 break; 2612 default: 2613 MPASS(0); 2614 } 2615 } else { 2616 fl->ifl_sds.ifsd_m[cidx] = NULL; 2617 *pf_rv = PFIL_PASS; 2618 } 2619 2620 if (unload && irf->irf_len != 0) 2621 bus_dmamap_unload(fl->ifl_buf_tag, map); 2622 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2623 if (__predict_false(fl->ifl_cidx == 0)) 2624 fl->ifl_gen = 0; 2625 bit_clear(fl->ifl_rx_bitmap, cidx); 2626 return (m); 2627 } 2628 2629 static struct mbuf * 2630 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2631 { 2632 struct mbuf *m, *mh, *mt; 2633 caddr_t cl; 2634 int *pf_rv_ptr, flags, i, padlen; 2635 bool consumed; 2636 2637 i = 0; 2638 mh = NULL; 2639 consumed = false; 2640 *pf_rv = PFIL_PASS; 2641 pf_rv_ptr = pf_rv; 2642 do { 2643 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2644 pf_rv_ptr, ri); 2645 2646 MPASS(*sd->ifsd_cl != NULL); 2647 2648 /* 2649 * Exclude zero-length frags & frags from 2650 * packets the filter has consumed or dropped 2651 */ 2652 if (ri->iri_frags[i].irf_len == 0 || consumed || 2653 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2654 if (mh == NULL) { 2655 /* everything saved here */ 2656 consumed = true; 2657 pf_rv_ptr = NULL; 2658 continue; 2659 } 2660 /* XXX we can save the cluster here, but not the mbuf */ 2661 m_init(m, M_NOWAIT, MT_DATA, 0); 2662 m_free(m); 2663 continue; 2664 } 2665 if (mh == NULL) { 2666 flags = M_PKTHDR|M_EXT; 2667 mh = mt = m; 2668 padlen = ri->iri_pad; 2669 } else { 2670 flags = M_EXT; 2671 mt->m_next = m; 2672 mt = m; 2673 /* assuming padding is only on the first fragment */ 2674 padlen = 0; 2675 } 2676 cl = *sd->ifsd_cl; 2677 *sd->ifsd_cl = NULL; 2678 2679 /* Can these two be made one ? */ 2680 m_init(m, M_NOWAIT, MT_DATA, flags); 2681 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2682 /* 2683 * These must follow m_init and m_cljset 2684 */ 2685 m->m_data += padlen; 2686 ri->iri_len -= padlen; 2687 m->m_len = ri->iri_frags[i].irf_len; 2688 } while (++i < ri->iri_nfrags); 2689 2690 return (mh); 2691 } 2692 2693 /* 2694 * Process one software descriptor 2695 */ 2696 static struct mbuf * 2697 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2698 { 2699 struct if_rxsd sd; 2700 struct mbuf *m; 2701 int pf_rv; 2702 2703 /* should I merge this back in now that the two paths are basically duplicated? */ 2704 if (ri->iri_nfrags == 1 && 2705 ri->iri_frags[0].irf_len != 0 && 2706 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2707 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2708 &pf_rv, ri); 2709 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2710 return (m); 2711 if (pf_rv == PFIL_PASS) { 2712 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2713 #ifndef __NO_STRICT_ALIGNMENT 2714 if (!IP_ALIGNED(m)) 2715 m->m_data += 2; 2716 #endif 2717 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2718 m->m_len = ri->iri_frags[0].irf_len; 2719 } 2720 } else { 2721 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2722 if (m == NULL) 2723 return (NULL); 2724 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2725 return (m); 2726 } 2727 m->m_pkthdr.len = ri->iri_len; 2728 m->m_pkthdr.rcvif = ri->iri_ifp; 2729 m->m_flags |= ri->iri_flags; 2730 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2731 m->m_pkthdr.flowid = ri->iri_flowid; 2732 M_HASHTYPE_SET(m, ri->iri_rsstype); 2733 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2734 m->m_pkthdr.csum_data = ri->iri_csum_data; 2735 return (m); 2736 } 2737 2738 #if defined(INET6) || defined(INET) 2739 static void 2740 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2741 { 2742 CURVNET_SET(lc->ifp->if_vnet); 2743 #if defined(INET6) 2744 *v6 = V_ip6_forwarding; 2745 #endif 2746 #if defined(INET) 2747 *v4 = V_ipforwarding; 2748 #endif 2749 CURVNET_RESTORE(); 2750 } 2751 2752 /* 2753 * Returns true if it's possible this packet could be LROed. 2754 * if it returns false, it is guaranteed that tcp_lro_rx() 2755 * would not return zero. 2756 */ 2757 static bool 2758 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2759 { 2760 struct ether_header *eh; 2761 2762 eh = mtod(m, struct ether_header *); 2763 switch (eh->ether_type) { 2764 #if defined(INET6) 2765 case htons(ETHERTYPE_IPV6): 2766 return (!v6_forwarding); 2767 #endif 2768 #if defined (INET) 2769 case htons(ETHERTYPE_IP): 2770 return (!v4_forwarding); 2771 #endif 2772 } 2773 2774 return false; 2775 } 2776 #else 2777 static void 2778 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2779 { 2780 } 2781 #endif 2782 2783 static void 2784 _task_fn_rx_watchdog(void *context) 2785 { 2786 iflib_rxq_t rxq = context; 2787 2788 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2789 } 2790 2791 static uint8_t 2792 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2793 { 2794 if_t ifp; 2795 if_ctx_t ctx = rxq->ifr_ctx; 2796 if_shared_ctx_t sctx = ctx->ifc_sctx; 2797 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2798 int avail, i; 2799 qidx_t *cidxp; 2800 struct if_rxd_info ri; 2801 int err, budget_left, rx_bytes, rx_pkts; 2802 iflib_fl_t fl; 2803 int lro_enabled; 2804 bool v4_forwarding, v6_forwarding, lro_possible; 2805 uint8_t retval = 0; 2806 2807 /* 2808 * XXX early demux data packets so that if_input processing only handles 2809 * acks in interrupt context 2810 */ 2811 struct mbuf *m, *mh, *mt, *mf; 2812 2813 NET_EPOCH_ASSERT(); 2814 2815 lro_possible = v4_forwarding = v6_forwarding = false; 2816 ifp = ctx->ifc_ifp; 2817 mh = mt = NULL; 2818 MPASS(budget > 0); 2819 rx_pkts = rx_bytes = 0; 2820 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2821 cidxp = &rxq->ifr_cq_cidx; 2822 else 2823 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2824 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2825 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2826 retval |= iflib_fl_refill_all(ctx, fl); 2827 DBG_COUNTER_INC(rx_unavail); 2828 return (retval); 2829 } 2830 2831 /* pfil needs the vnet to be set */ 2832 CURVNET_SET_QUIET(ifp->if_vnet); 2833 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2834 if (__predict_false(!CTX_ACTIVE(ctx))) { 2835 DBG_COUNTER_INC(rx_ctx_inactive); 2836 break; 2837 } 2838 /* 2839 * Reset client set fields to their default values 2840 */ 2841 rxd_info_zero(&ri); 2842 ri.iri_qsidx = rxq->ifr_id; 2843 ri.iri_cidx = *cidxp; 2844 ri.iri_ifp = ifp; 2845 ri.iri_frags = rxq->ifr_frags; 2846 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2847 2848 if (err) 2849 goto err; 2850 rx_pkts += 1; 2851 rx_bytes += ri.iri_len; 2852 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2853 *cidxp = ri.iri_cidx; 2854 /* Update our consumer index */ 2855 /* XXX NB: shurd - check if this is still safe */ 2856 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2857 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2858 /* was this only a completion queue message? */ 2859 if (__predict_false(ri.iri_nfrags == 0)) 2860 continue; 2861 } 2862 MPASS(ri.iri_nfrags != 0); 2863 MPASS(ri.iri_len != 0); 2864 2865 /* will advance the cidx on the corresponding free lists */ 2866 m = iflib_rxd_pkt_get(rxq, &ri); 2867 avail--; 2868 budget_left--; 2869 if (avail == 0 && budget_left) 2870 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2871 2872 if (__predict_false(m == NULL)) 2873 continue; 2874 2875 /* imm_pkt: -- cxgb */ 2876 if (mh == NULL) 2877 mh = mt = m; 2878 else { 2879 mt->m_nextpkt = m; 2880 mt = m; 2881 } 2882 } 2883 CURVNET_RESTORE(); 2884 /* make sure that we can refill faster than drain */ 2885 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2886 retval |= iflib_fl_refill_all(ctx, fl); 2887 2888 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2889 if (lro_enabled) 2890 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2891 mt = mf = NULL; 2892 while (mh != NULL) { 2893 m = mh; 2894 mh = mh->m_nextpkt; 2895 m->m_nextpkt = NULL; 2896 #ifndef __NO_STRICT_ALIGNMENT 2897 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2898 continue; 2899 #endif 2900 rx_bytes += m->m_pkthdr.len; 2901 rx_pkts++; 2902 #if defined(INET6) || defined(INET) 2903 if (lro_enabled) { 2904 if (!lro_possible) { 2905 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2906 if (lro_possible && mf != NULL) { 2907 ifp->if_input(ifp, mf); 2908 DBG_COUNTER_INC(rx_if_input); 2909 mt = mf = NULL; 2910 } 2911 } 2912 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2913 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2914 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2915 continue; 2916 } 2917 } 2918 #endif 2919 if (lro_possible) { 2920 ifp->if_input(ifp, m); 2921 DBG_COUNTER_INC(rx_if_input); 2922 continue; 2923 } 2924 2925 if (mf == NULL) 2926 mf = m; 2927 if (mt != NULL) 2928 mt->m_nextpkt = m; 2929 mt = m; 2930 } 2931 if (mf != NULL) { 2932 ifp->if_input(ifp, mf); 2933 DBG_COUNTER_INC(rx_if_input); 2934 } 2935 2936 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2937 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2938 2939 /* 2940 * Flush any outstanding LRO work 2941 */ 2942 #if defined(INET6) || defined(INET) 2943 tcp_lro_flush_all(&rxq->ifr_lc); 2944 #endif 2945 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 2946 retval |= IFLIB_RXEOF_MORE; 2947 return (retval); 2948 err: 2949 STATE_LOCK(ctx); 2950 ctx->ifc_flags |= IFC_DO_RESET; 2951 iflib_admin_intr_deferred(ctx); 2952 STATE_UNLOCK(ctx); 2953 return (0); 2954 } 2955 2956 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2957 static inline qidx_t 2958 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2959 { 2960 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2961 qidx_t minthresh = txq->ift_size / 8; 2962 if (in_use > 4*minthresh) 2963 return (notify_count); 2964 if (in_use > 2*minthresh) 2965 return (notify_count >> 1); 2966 if (in_use > minthresh) 2967 return (notify_count >> 3); 2968 return (0); 2969 } 2970 2971 static inline qidx_t 2972 txq_max_rs_deferred(iflib_txq_t txq) 2973 { 2974 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2975 qidx_t minthresh = txq->ift_size / 8; 2976 if (txq->ift_in_use > 4*minthresh) 2977 return (notify_count); 2978 if (txq->ift_in_use > 2*minthresh) 2979 return (notify_count >> 1); 2980 if (txq->ift_in_use > minthresh) 2981 return (notify_count >> 2); 2982 return (2); 2983 } 2984 2985 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2986 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2987 2988 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2989 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2990 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2991 2992 /* forward compatibility for cxgb */ 2993 #define FIRST_QSET(ctx) 0 2994 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2995 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2996 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2997 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2998 2999 /* XXX we should be setting this to something other than zero */ 3000 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 3001 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3002 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3003 3004 static inline bool 3005 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 3006 { 3007 qidx_t dbval, max; 3008 bool rang; 3009 3010 rang = false; 3011 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 3012 if (ring || txq->ift_db_pending >= max) { 3013 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3014 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3015 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3016 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3017 txq->ift_db_pending = txq->ift_npending = 0; 3018 rang = true; 3019 } 3020 return (rang); 3021 } 3022 3023 #ifdef PKT_DEBUG 3024 static void 3025 print_pkt(if_pkt_info_t pi) 3026 { 3027 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3028 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3029 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3030 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3031 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3032 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3033 } 3034 #endif 3035 3036 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3037 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3038 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3039 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3040 3041 static int 3042 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3043 { 3044 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3045 struct ether_vlan_header *eh; 3046 struct mbuf *m; 3047 3048 m = *mp; 3049 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3050 M_WRITABLE(m) == 0) { 3051 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3052 return (ENOMEM); 3053 } else { 3054 m_freem(*mp); 3055 DBG_COUNTER_INC(tx_frees); 3056 *mp = m; 3057 } 3058 } 3059 3060 /* 3061 * Determine where frame payload starts. 3062 * Jump over vlan headers if already present, 3063 * helpful for QinQ too. 3064 */ 3065 if (__predict_false(m->m_len < sizeof(*eh))) { 3066 txq->ift_pullups++; 3067 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3068 return (ENOMEM); 3069 } 3070 eh = mtod(m, struct ether_vlan_header *); 3071 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3072 pi->ipi_etype = ntohs(eh->evl_proto); 3073 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3074 } else { 3075 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3076 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3077 } 3078 3079 switch (pi->ipi_etype) { 3080 #ifdef INET 3081 case ETHERTYPE_IP: 3082 { 3083 struct mbuf *n; 3084 struct ip *ip = NULL; 3085 struct tcphdr *th = NULL; 3086 int minthlen; 3087 3088 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3089 if (__predict_false(m->m_len < minthlen)) { 3090 /* 3091 * if this code bloat is causing too much of a hit 3092 * move it to a separate function and mark it noinline 3093 */ 3094 if (m->m_len == pi->ipi_ehdrlen) { 3095 n = m->m_next; 3096 MPASS(n); 3097 if (n->m_len >= sizeof(*ip)) { 3098 ip = (struct ip *)n->m_data; 3099 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3100 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3101 } else { 3102 txq->ift_pullups++; 3103 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3104 return (ENOMEM); 3105 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3106 } 3107 } else { 3108 txq->ift_pullups++; 3109 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3110 return (ENOMEM); 3111 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3112 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3113 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3114 } 3115 } else { 3116 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3117 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3118 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3119 } 3120 pi->ipi_ip_hlen = ip->ip_hl << 2; 3121 pi->ipi_ipproto = ip->ip_p; 3122 pi->ipi_flags |= IPI_TX_IPV4; 3123 3124 /* TCP checksum offload may require TCP header length */ 3125 if (IS_TX_OFFLOAD4(pi)) { 3126 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3127 if (__predict_false(th == NULL)) { 3128 txq->ift_pullups++; 3129 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3130 return (ENOMEM); 3131 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3132 } 3133 pi->ipi_tcp_hflags = th->th_flags; 3134 pi->ipi_tcp_hlen = th->th_off << 2; 3135 pi->ipi_tcp_seq = th->th_seq; 3136 } 3137 if (IS_TSO4(pi)) { 3138 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3139 return (ENXIO); 3140 /* 3141 * TSO always requires hardware checksum offload. 3142 */ 3143 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3144 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3145 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3146 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3147 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3148 ip->ip_sum = 0; 3149 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3150 } 3151 } 3152 } 3153 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3154 ip->ip_sum = 0; 3155 3156 break; 3157 } 3158 #endif 3159 #ifdef INET6 3160 case ETHERTYPE_IPV6: 3161 { 3162 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3163 struct tcphdr *th; 3164 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3165 3166 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3167 txq->ift_pullups++; 3168 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3169 return (ENOMEM); 3170 } 3171 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3172 3173 /* XXX-BZ this will go badly in case of ext hdrs. */ 3174 pi->ipi_ipproto = ip6->ip6_nxt; 3175 pi->ipi_flags |= IPI_TX_IPV6; 3176 3177 /* TCP checksum offload may require TCP header length */ 3178 if (IS_TX_OFFLOAD6(pi)) { 3179 if (pi->ipi_ipproto == IPPROTO_TCP) { 3180 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3181 txq->ift_pullups++; 3182 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3183 return (ENOMEM); 3184 } 3185 pi->ipi_tcp_hflags = th->th_flags; 3186 pi->ipi_tcp_hlen = th->th_off << 2; 3187 pi->ipi_tcp_seq = th->th_seq; 3188 } 3189 if (IS_TSO6(pi)) { 3190 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3191 return (ENXIO); 3192 /* 3193 * TSO always requires hardware checksum offload. 3194 */ 3195 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3196 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3197 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3198 } 3199 } 3200 break; 3201 } 3202 #endif 3203 default: 3204 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3205 pi->ipi_ip_hlen = 0; 3206 break; 3207 } 3208 *mp = m; 3209 3210 return (0); 3211 } 3212 3213 /* 3214 * If dodgy hardware rejects the scatter gather chain we've handed it 3215 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3216 * m_defrag'd mbufs 3217 */ 3218 static __noinline struct mbuf * 3219 iflib_remove_mbuf(iflib_txq_t txq) 3220 { 3221 int ntxd, pidx; 3222 struct mbuf *m, **ifsd_m; 3223 3224 ifsd_m = txq->ift_sds.ifsd_m; 3225 ntxd = txq->ift_size; 3226 pidx = txq->ift_pidx & (ntxd - 1); 3227 ifsd_m = txq->ift_sds.ifsd_m; 3228 m = ifsd_m[pidx]; 3229 ifsd_m[pidx] = NULL; 3230 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3231 if (txq->ift_sds.ifsd_tso_map != NULL) 3232 bus_dmamap_unload(txq->ift_tso_buf_tag, 3233 txq->ift_sds.ifsd_tso_map[pidx]); 3234 #if MEMORY_LOGGING 3235 txq->ift_dequeued++; 3236 #endif 3237 return (m); 3238 } 3239 3240 static inline caddr_t 3241 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3242 { 3243 qidx_t size; 3244 int ntxd; 3245 caddr_t start, end, cur, next; 3246 3247 ntxd = txq->ift_size; 3248 size = txq->ift_txd_size[qid]; 3249 start = txq->ift_ifdi[qid].idi_vaddr; 3250 3251 if (__predict_false(size == 0)) 3252 return (start); 3253 cur = start + size*cidx; 3254 end = start + size*ntxd; 3255 next = CACHE_PTR_NEXT(cur); 3256 return (next < end ? next : start); 3257 } 3258 3259 /* 3260 * Pad an mbuf to ensure a minimum ethernet frame size. 3261 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3262 */ 3263 static __noinline int 3264 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3265 { 3266 /* 3267 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3268 * and ARP message is the smallest common payload I can think of 3269 */ 3270 static char pad[18]; /* just zeros */ 3271 int n; 3272 struct mbuf *new_head; 3273 3274 if (!M_WRITABLE(*m_head)) { 3275 new_head = m_dup(*m_head, M_NOWAIT); 3276 if (new_head == NULL) { 3277 m_freem(*m_head); 3278 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3279 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3280 DBG_COUNTER_INC(tx_frees); 3281 return ENOMEM; 3282 } 3283 m_freem(*m_head); 3284 *m_head = new_head; 3285 } 3286 3287 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3288 n > 0; n -= sizeof(pad)) 3289 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3290 break; 3291 3292 if (n > 0) { 3293 m_freem(*m_head); 3294 device_printf(dev, "cannot pad short frame\n"); 3295 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3296 DBG_COUNTER_INC(tx_frees); 3297 return (ENOBUFS); 3298 } 3299 3300 return 0; 3301 } 3302 3303 static int 3304 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3305 { 3306 if_ctx_t ctx; 3307 if_shared_ctx_t sctx; 3308 if_softc_ctx_t scctx; 3309 bus_dma_tag_t buf_tag; 3310 bus_dma_segment_t *segs; 3311 struct mbuf *m_head, **ifsd_m; 3312 void *next_txd; 3313 bus_dmamap_t map; 3314 struct if_pkt_info pi; 3315 int remap = 0; 3316 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3317 3318 ctx = txq->ift_ctx; 3319 sctx = ctx->ifc_sctx; 3320 scctx = &ctx->ifc_softc_ctx; 3321 segs = txq->ift_segs; 3322 ntxd = txq->ift_size; 3323 m_head = *m_headp; 3324 map = NULL; 3325 3326 /* 3327 * If we're doing TSO the next descriptor to clean may be quite far ahead 3328 */ 3329 cidx = txq->ift_cidx; 3330 pidx = txq->ift_pidx; 3331 if (ctx->ifc_flags & IFC_PREFETCH) { 3332 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3333 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3334 next_txd = calc_next_txd(txq, cidx, 0); 3335 prefetch(next_txd); 3336 } 3337 3338 /* prefetch the next cache line of mbuf pointers and flags */ 3339 prefetch(&txq->ift_sds.ifsd_m[next]); 3340 prefetch(&txq->ift_sds.ifsd_map[next]); 3341 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3342 } 3343 map = txq->ift_sds.ifsd_map[pidx]; 3344 ifsd_m = txq->ift_sds.ifsd_m; 3345 3346 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3347 buf_tag = txq->ift_tso_buf_tag; 3348 max_segs = scctx->isc_tx_tso_segments_max; 3349 map = txq->ift_sds.ifsd_tso_map[pidx]; 3350 MPASS(buf_tag != NULL); 3351 MPASS(max_segs > 0); 3352 } else { 3353 buf_tag = txq->ift_buf_tag; 3354 max_segs = scctx->isc_tx_nsegments; 3355 map = txq->ift_sds.ifsd_map[pidx]; 3356 } 3357 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3358 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3359 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3360 if (err) { 3361 DBG_COUNTER_INC(encap_txd_encap_fail); 3362 return err; 3363 } 3364 } 3365 m_head = *m_headp; 3366 3367 pkt_info_zero(&pi); 3368 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3369 pi.ipi_pidx = pidx; 3370 pi.ipi_qsidx = txq->ift_id; 3371 pi.ipi_len = m_head->m_pkthdr.len; 3372 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3373 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3374 3375 /* deliberate bitwise OR to make one condition */ 3376 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3377 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3378 DBG_COUNTER_INC(encap_txd_encap_fail); 3379 return (err); 3380 } 3381 m_head = *m_headp; 3382 } 3383 3384 retry: 3385 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3386 BUS_DMA_NOWAIT); 3387 defrag: 3388 if (__predict_false(err)) { 3389 switch (err) { 3390 case EFBIG: 3391 /* try collapse once and defrag once */ 3392 if (remap == 0) { 3393 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3394 /* try defrag if collapsing fails */ 3395 if (m_head == NULL) 3396 remap++; 3397 } 3398 if (remap == 1) { 3399 txq->ift_mbuf_defrag++; 3400 m_head = m_defrag(*m_headp, M_NOWAIT); 3401 } 3402 /* 3403 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3404 * failed to map an mbuf that was run through m_defrag 3405 */ 3406 MPASS(remap <= 1); 3407 if (__predict_false(m_head == NULL || remap > 1)) 3408 goto defrag_failed; 3409 remap++; 3410 *m_headp = m_head; 3411 goto retry; 3412 break; 3413 case ENOMEM: 3414 txq->ift_no_tx_dma_setup++; 3415 break; 3416 default: 3417 txq->ift_no_tx_dma_setup++; 3418 m_freem(*m_headp); 3419 DBG_COUNTER_INC(tx_frees); 3420 *m_headp = NULL; 3421 break; 3422 } 3423 txq->ift_map_failed++; 3424 DBG_COUNTER_INC(encap_load_mbuf_fail); 3425 DBG_COUNTER_INC(encap_txd_encap_fail); 3426 return (err); 3427 } 3428 ifsd_m[pidx] = m_head; 3429 /* 3430 * XXX assumes a 1 to 1 relationship between segments and 3431 * descriptors - this does not hold true on all drivers, e.g. 3432 * cxgb 3433 */ 3434 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3435 txq->ift_no_desc_avail++; 3436 bus_dmamap_unload(buf_tag, map); 3437 DBG_COUNTER_INC(encap_txq_avail_fail); 3438 DBG_COUNTER_INC(encap_txd_encap_fail); 3439 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3440 GROUPTASK_ENQUEUE(&txq->ift_task); 3441 return (ENOBUFS); 3442 } 3443 /* 3444 * On Intel cards we can greatly reduce the number of TX interrupts 3445 * we see by only setting report status on every Nth descriptor. 3446 * However, this also means that the driver will need to keep track 3447 * of the descriptors that RS was set on to check them for the DD bit. 3448 */ 3449 txq->ift_rs_pending += nsegs + 1; 3450 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3451 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3452 pi.ipi_flags |= IPI_TX_INTR; 3453 txq->ift_rs_pending = 0; 3454 } 3455 3456 pi.ipi_segs = segs; 3457 pi.ipi_nsegs = nsegs; 3458 3459 MPASS(pidx >= 0 && pidx < txq->ift_size); 3460 #ifdef PKT_DEBUG 3461 print_pkt(&pi); 3462 #endif 3463 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3464 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3465 DBG_COUNTER_INC(tx_encap); 3466 MPASS(pi.ipi_new_pidx < txq->ift_size); 3467 3468 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3469 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3470 ndesc += txq->ift_size; 3471 txq->ift_gen = 1; 3472 } 3473 /* 3474 * drivers can need as many as 3475 * two sentinels 3476 */ 3477 MPASS(ndesc <= pi.ipi_nsegs + 2); 3478 MPASS(pi.ipi_new_pidx != pidx); 3479 MPASS(ndesc > 0); 3480 txq->ift_in_use += ndesc; 3481 3482 /* 3483 * We update the last software descriptor again here because there may 3484 * be a sentinel and/or there may be more mbufs than segments 3485 */ 3486 txq->ift_pidx = pi.ipi_new_pidx; 3487 txq->ift_npending += pi.ipi_ndescs; 3488 } else { 3489 *m_headp = m_head = iflib_remove_mbuf(txq); 3490 if (err == EFBIG) { 3491 txq->ift_txd_encap_efbig++; 3492 if (remap < 2) { 3493 remap = 1; 3494 goto defrag; 3495 } 3496 } 3497 goto defrag_failed; 3498 } 3499 /* 3500 * err can't possibly be non-zero here, so we don't neet to test it 3501 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3502 */ 3503 return (err); 3504 3505 defrag_failed: 3506 txq->ift_mbuf_defrag_failed++; 3507 txq->ift_map_failed++; 3508 m_freem(*m_headp); 3509 DBG_COUNTER_INC(tx_frees); 3510 *m_headp = NULL; 3511 DBG_COUNTER_INC(encap_txd_encap_fail); 3512 return (ENOMEM); 3513 } 3514 3515 static void 3516 iflib_tx_desc_free(iflib_txq_t txq, int n) 3517 { 3518 uint32_t qsize, cidx, mask, gen; 3519 struct mbuf *m, **ifsd_m; 3520 bool do_prefetch; 3521 3522 cidx = txq->ift_cidx; 3523 gen = txq->ift_gen; 3524 qsize = txq->ift_size; 3525 mask = qsize-1; 3526 ifsd_m = txq->ift_sds.ifsd_m; 3527 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3528 3529 while (n-- > 0) { 3530 if (do_prefetch) { 3531 prefetch(ifsd_m[(cidx + 3) & mask]); 3532 prefetch(ifsd_m[(cidx + 4) & mask]); 3533 } 3534 if ((m = ifsd_m[cidx]) != NULL) { 3535 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3536 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3537 bus_dmamap_sync(txq->ift_tso_buf_tag, 3538 txq->ift_sds.ifsd_tso_map[cidx], 3539 BUS_DMASYNC_POSTWRITE); 3540 bus_dmamap_unload(txq->ift_tso_buf_tag, 3541 txq->ift_sds.ifsd_tso_map[cidx]); 3542 } else { 3543 bus_dmamap_sync(txq->ift_buf_tag, 3544 txq->ift_sds.ifsd_map[cidx], 3545 BUS_DMASYNC_POSTWRITE); 3546 bus_dmamap_unload(txq->ift_buf_tag, 3547 txq->ift_sds.ifsd_map[cidx]); 3548 } 3549 /* XXX we don't support any drivers that batch packets yet */ 3550 MPASS(m->m_nextpkt == NULL); 3551 m_freem(m); 3552 ifsd_m[cidx] = NULL; 3553 #if MEMORY_LOGGING 3554 txq->ift_dequeued++; 3555 #endif 3556 DBG_COUNTER_INC(tx_frees); 3557 } 3558 if (__predict_false(++cidx == qsize)) { 3559 cidx = 0; 3560 gen = 0; 3561 } 3562 } 3563 txq->ift_cidx = cidx; 3564 txq->ift_gen = gen; 3565 } 3566 3567 static __inline int 3568 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3569 { 3570 int reclaim; 3571 if_ctx_t ctx = txq->ift_ctx; 3572 3573 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3574 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3575 3576 /* 3577 * Need a rate-limiting check so that this isn't called every time 3578 */ 3579 iflib_tx_credits_update(ctx, txq); 3580 reclaim = DESC_RECLAIMABLE(txq); 3581 3582 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3583 #ifdef INVARIANTS 3584 if (iflib_verbose_debug) { 3585 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3586 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3587 reclaim, thresh); 3588 } 3589 #endif 3590 return (0); 3591 } 3592 iflib_tx_desc_free(txq, reclaim); 3593 txq->ift_cleaned += reclaim; 3594 txq->ift_in_use -= reclaim; 3595 3596 return (reclaim); 3597 } 3598 3599 static struct mbuf ** 3600 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3601 { 3602 int next, size; 3603 struct mbuf **items; 3604 3605 size = r->size; 3606 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3607 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3608 3609 prefetch(items[(cidx + offset) & (size-1)]); 3610 if (remaining > 1) { 3611 prefetch2cachelines(&items[next]); 3612 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3613 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3614 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3615 } 3616 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3617 } 3618 3619 static void 3620 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3621 { 3622 3623 ifmp_ring_check_drainage(txq->ift_br, budget); 3624 } 3625 3626 static uint32_t 3627 iflib_txq_can_drain(struct ifmp_ring *r) 3628 { 3629 iflib_txq_t txq = r->cookie; 3630 if_ctx_t ctx = txq->ift_ctx; 3631 3632 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3633 return (1); 3634 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3635 BUS_DMASYNC_POSTREAD); 3636 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3637 false)); 3638 } 3639 3640 static uint32_t 3641 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3642 { 3643 iflib_txq_t txq = r->cookie; 3644 if_ctx_t ctx = txq->ift_ctx; 3645 if_t ifp = ctx->ifc_ifp; 3646 struct mbuf *m, **mp; 3647 int avail, bytes_sent, consumed, count, err, i, in_use_prev; 3648 int mcast_sent, pkt_sent, reclaimed, txq_avail; 3649 bool do_prefetch, rang, ring; 3650 3651 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3652 !LINK_ACTIVE(ctx))) { 3653 DBG_COUNTER_INC(txq_drain_notready); 3654 return (0); 3655 } 3656 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3657 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3658 avail = IDXDIFF(pidx, cidx, r->size); 3659 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3660 DBG_COUNTER_INC(txq_drain_flushing); 3661 for (i = 0; i < avail; i++) { 3662 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3663 m_freem(r->items[(cidx + i) & (r->size-1)]); 3664 r->items[(cidx + i) & (r->size-1)] = NULL; 3665 } 3666 return (avail); 3667 } 3668 3669 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3670 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3671 CALLOUT_LOCK(txq); 3672 callout_stop(&txq->ift_timer); 3673 CALLOUT_UNLOCK(txq); 3674 DBG_COUNTER_INC(txq_drain_oactive); 3675 return (0); 3676 } 3677 if (reclaimed) 3678 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3679 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3680 count = MIN(avail, TX_BATCH_SIZE); 3681 #ifdef INVARIANTS 3682 if (iflib_verbose_debug) 3683 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3684 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3685 #endif 3686 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3687 txq_avail = TXQ_AVAIL(txq); 3688 err = 0; 3689 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) { 3690 int rem = do_prefetch ? count - i : 0; 3691 3692 mp = _ring_peek_one(r, cidx, i, rem); 3693 MPASS(mp != NULL && *mp != NULL); 3694 if (__predict_false(*mp == (struct mbuf *)txq)) { 3695 consumed++; 3696 continue; 3697 } 3698 in_use_prev = txq->ift_in_use; 3699 err = iflib_encap(txq, mp); 3700 if (__predict_false(err)) { 3701 /* no room - bail out */ 3702 if (err == ENOBUFS) 3703 break; 3704 consumed++; 3705 /* we can't send this packet - skip it */ 3706 continue; 3707 } 3708 consumed++; 3709 pkt_sent++; 3710 m = *mp; 3711 DBG_COUNTER_INC(tx_sent); 3712 bytes_sent += m->m_pkthdr.len; 3713 mcast_sent += !!(m->m_flags & M_MCAST); 3714 txq_avail = TXQ_AVAIL(txq); 3715 3716 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3717 ETHER_BPF_MTAP(ifp, m); 3718 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3719 break; 3720 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3721 } 3722 3723 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3724 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3725 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3726 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3727 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3728 if (mcast_sent) 3729 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3730 #ifdef INVARIANTS 3731 if (iflib_verbose_debug) 3732 printf("consumed=%d\n", consumed); 3733 #endif 3734 return (consumed); 3735 } 3736 3737 static uint32_t 3738 iflib_txq_drain_always(struct ifmp_ring *r) 3739 { 3740 return (1); 3741 } 3742 3743 static uint32_t 3744 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3745 { 3746 int i, avail; 3747 struct mbuf **mp; 3748 iflib_txq_t txq; 3749 3750 txq = r->cookie; 3751 3752 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3753 CALLOUT_LOCK(txq); 3754 callout_stop(&txq->ift_timer); 3755 CALLOUT_UNLOCK(txq); 3756 3757 avail = IDXDIFF(pidx, cidx, r->size); 3758 for (i = 0; i < avail; i++) { 3759 mp = _ring_peek_one(r, cidx, i, avail - i); 3760 if (__predict_false(*mp == (struct mbuf *)txq)) 3761 continue; 3762 m_freem(*mp); 3763 DBG_COUNTER_INC(tx_frees); 3764 } 3765 MPASS(ifmp_ring_is_stalled(r) == 0); 3766 return (avail); 3767 } 3768 3769 static void 3770 iflib_ifmp_purge(iflib_txq_t txq) 3771 { 3772 struct ifmp_ring *r; 3773 3774 r = txq->ift_br; 3775 r->drain = iflib_txq_drain_free; 3776 r->can_drain = iflib_txq_drain_always; 3777 3778 ifmp_ring_check_drainage(r, r->size); 3779 3780 r->drain = iflib_txq_drain; 3781 r->can_drain = iflib_txq_can_drain; 3782 } 3783 3784 static void 3785 _task_fn_tx(void *context) 3786 { 3787 iflib_txq_t txq = context; 3788 if_ctx_t ctx = txq->ift_ctx; 3789 if_t ifp = ctx->ifc_ifp; 3790 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3791 3792 #ifdef IFLIB_DIAGNOSTICS 3793 txq->ift_cpu_exec_count[curcpu]++; 3794 #endif 3795 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 3796 return; 3797 #ifdef DEV_NETMAP 3798 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 3799 netmap_tx_irq(ifp, txq->ift_id)) 3800 goto skip_ifmp; 3801 #endif 3802 #ifdef ALTQ 3803 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3804 iflib_altq_if_start(ifp); 3805 #endif 3806 if (txq->ift_db_pending) 3807 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3808 else if (!abdicate) 3809 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3810 /* 3811 * When abdicating, we always need to check drainage, not just when we don't enqueue 3812 */ 3813 if (abdicate) 3814 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3815 #ifdef DEV_NETMAP 3816 skip_ifmp: 3817 #endif 3818 if (ctx->ifc_flags & IFC_LEGACY) 3819 IFDI_INTR_ENABLE(ctx); 3820 else 3821 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3822 } 3823 3824 static void 3825 _task_fn_rx(void *context) 3826 { 3827 iflib_rxq_t rxq = context; 3828 if_ctx_t ctx = rxq->ifr_ctx; 3829 uint8_t more; 3830 uint16_t budget; 3831 #ifdef DEV_NETMAP 3832 u_int work = 0; 3833 int nmirq; 3834 #endif 3835 3836 #ifdef IFLIB_DIAGNOSTICS 3837 rxq->ifr_cpu_exec_count[curcpu]++; 3838 #endif 3839 DBG_COUNTER_INC(task_fn_rxs); 3840 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3841 return; 3842 #ifdef DEV_NETMAP 3843 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 3844 if (nmirq != NM_IRQ_PASS) { 3845 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 3846 goto skip_rxeof; 3847 } 3848 #endif 3849 budget = ctx->ifc_sysctl_rx_budget; 3850 if (budget == 0) 3851 budget = 16; /* XXX */ 3852 more = iflib_rxeof(rxq, budget); 3853 #ifdef DEV_NETMAP 3854 skip_rxeof: 3855 #endif 3856 if ((more & IFLIB_RXEOF_MORE) == 0) { 3857 if (ctx->ifc_flags & IFC_LEGACY) 3858 IFDI_INTR_ENABLE(ctx); 3859 else 3860 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3861 DBG_COUNTER_INC(rx_intr_enables); 3862 } 3863 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3864 return; 3865 3866 if (more & IFLIB_RXEOF_MORE) 3867 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3868 else if (more & IFLIB_RXEOF_EMPTY) 3869 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 3870 } 3871 3872 static void 3873 _task_fn_admin(void *context) 3874 { 3875 if_ctx_t ctx = context; 3876 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3877 iflib_txq_t txq; 3878 int i; 3879 bool oactive, running, do_reset, do_watchdog, in_detach; 3880 3881 STATE_LOCK(ctx); 3882 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3883 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3884 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3885 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3886 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3887 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3888 STATE_UNLOCK(ctx); 3889 3890 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3891 return; 3892 if (in_detach) 3893 return; 3894 3895 CTX_LOCK(ctx); 3896 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3897 CALLOUT_LOCK(txq); 3898 callout_stop(&txq->ift_timer); 3899 CALLOUT_UNLOCK(txq); 3900 } 3901 if (do_watchdog) { 3902 ctx->ifc_watchdog_events++; 3903 IFDI_WATCHDOG_RESET(ctx); 3904 } 3905 IFDI_UPDATE_ADMIN_STATUS(ctx); 3906 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3907 callout_reset_on(&txq->ift_timer, hz / 2, iflib_timer, txq, 3908 txq->ift_timer.c_cpu); 3909 } 3910 IFDI_LINK_INTR_ENABLE(ctx); 3911 if (do_reset) 3912 iflib_if_init_locked(ctx); 3913 CTX_UNLOCK(ctx); 3914 3915 if (LINK_ACTIVE(ctx) == 0) 3916 return; 3917 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3918 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3919 } 3920 3921 static void 3922 _task_fn_iov(void *context) 3923 { 3924 if_ctx_t ctx = context; 3925 3926 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3927 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3928 return; 3929 3930 CTX_LOCK(ctx); 3931 IFDI_VFLR_HANDLE(ctx); 3932 CTX_UNLOCK(ctx); 3933 } 3934 3935 static int 3936 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3937 { 3938 int err; 3939 if_int_delay_info_t info; 3940 if_ctx_t ctx; 3941 3942 info = (if_int_delay_info_t)arg1; 3943 ctx = info->iidi_ctx; 3944 info->iidi_req = req; 3945 info->iidi_oidp = oidp; 3946 CTX_LOCK(ctx); 3947 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3948 CTX_UNLOCK(ctx); 3949 return (err); 3950 } 3951 3952 /********************************************************************* 3953 * 3954 * IFNET FUNCTIONS 3955 * 3956 **********************************************************************/ 3957 3958 static void 3959 iflib_if_init_locked(if_ctx_t ctx) 3960 { 3961 iflib_stop(ctx); 3962 iflib_init_locked(ctx); 3963 } 3964 3965 static void 3966 iflib_if_init(void *arg) 3967 { 3968 if_ctx_t ctx = arg; 3969 3970 CTX_LOCK(ctx); 3971 iflib_if_init_locked(ctx); 3972 CTX_UNLOCK(ctx); 3973 } 3974 3975 static int 3976 iflib_if_transmit(if_t ifp, struct mbuf *m) 3977 { 3978 if_ctx_t ctx = if_getsoftc(ifp); 3979 3980 iflib_txq_t txq; 3981 int err, qidx; 3982 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3983 3984 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3985 DBG_COUNTER_INC(tx_frees); 3986 m_freem(m); 3987 return (ENETDOWN); 3988 } 3989 3990 MPASS(m->m_nextpkt == NULL); 3991 /* ALTQ-enabled interfaces always use queue 0. */ 3992 qidx = 0; 3993 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3994 qidx = QIDX(ctx, m); 3995 /* 3996 * XXX calculate buf_ring based on flowid (divvy up bits?) 3997 */ 3998 txq = &ctx->ifc_txqs[qidx]; 3999 4000 #ifdef DRIVER_BACKPRESSURE 4001 if (txq->ift_closed) { 4002 while (m != NULL) { 4003 next = m->m_nextpkt; 4004 m->m_nextpkt = NULL; 4005 m_freem(m); 4006 DBG_COUNTER_INC(tx_frees); 4007 m = next; 4008 } 4009 return (ENOBUFS); 4010 } 4011 #endif 4012 #ifdef notyet 4013 qidx = count = 0; 4014 mp = marr; 4015 next = m; 4016 do { 4017 count++; 4018 next = next->m_nextpkt; 4019 } while (next != NULL); 4020 4021 if (count > nitems(marr)) 4022 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4023 /* XXX check nextpkt */ 4024 m_freem(m); 4025 /* XXX simplify for now */ 4026 DBG_COUNTER_INC(tx_frees); 4027 return (ENOBUFS); 4028 } 4029 for (next = m, i = 0; next != NULL; i++) { 4030 mp[i] = next; 4031 next = next->m_nextpkt; 4032 mp[i]->m_nextpkt = NULL; 4033 } 4034 #endif 4035 DBG_COUNTER_INC(tx_seen); 4036 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4037 4038 if (abdicate) 4039 GROUPTASK_ENQUEUE(&txq->ift_task); 4040 if (err) { 4041 if (!abdicate) 4042 GROUPTASK_ENQUEUE(&txq->ift_task); 4043 /* support forthcoming later */ 4044 #ifdef DRIVER_BACKPRESSURE 4045 txq->ift_closed = TRUE; 4046 #endif 4047 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4048 m_freem(m); 4049 DBG_COUNTER_INC(tx_frees); 4050 } 4051 4052 return (err); 4053 } 4054 4055 #ifdef ALTQ 4056 /* 4057 * The overall approach to integrating iflib with ALTQ is to continue to use 4058 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4059 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4060 * is redundant/unnecessary, but doing so minimizes the amount of 4061 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4062 * redundantly queueing to an intermediate mp_ring is swamped by the 4063 * performance limitations inherent in using ALTQ. 4064 * 4065 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4066 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4067 * given interface. If ALTQ is enabled for an interface, then all 4068 * transmitted packets for that interface will be submitted to the ALTQ 4069 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4070 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4071 * update stats that the iflib machinery handles, and which is sensitve to 4072 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4073 * will be installed as the start routine for use by ALTQ facilities that 4074 * need to trigger queue drains on a scheduled basis. 4075 * 4076 */ 4077 static void 4078 iflib_altq_if_start(if_t ifp) 4079 { 4080 struct ifaltq *ifq = &ifp->if_snd; 4081 struct mbuf *m; 4082 4083 IFQ_LOCK(ifq); 4084 IFQ_DEQUEUE_NOLOCK(ifq, m); 4085 while (m != NULL) { 4086 iflib_if_transmit(ifp, m); 4087 IFQ_DEQUEUE_NOLOCK(ifq, m); 4088 } 4089 IFQ_UNLOCK(ifq); 4090 } 4091 4092 static int 4093 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4094 { 4095 int err; 4096 4097 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4098 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4099 if (err == 0) 4100 iflib_altq_if_start(ifp); 4101 } else 4102 err = iflib_if_transmit(ifp, m); 4103 4104 return (err); 4105 } 4106 #endif /* ALTQ */ 4107 4108 static void 4109 iflib_if_qflush(if_t ifp) 4110 { 4111 if_ctx_t ctx = if_getsoftc(ifp); 4112 iflib_txq_t txq = ctx->ifc_txqs; 4113 int i; 4114 4115 STATE_LOCK(ctx); 4116 ctx->ifc_flags |= IFC_QFLUSH; 4117 STATE_UNLOCK(ctx); 4118 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4119 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4120 iflib_txq_check_drain(txq, 0); 4121 STATE_LOCK(ctx); 4122 ctx->ifc_flags &= ~IFC_QFLUSH; 4123 STATE_UNLOCK(ctx); 4124 4125 /* 4126 * When ALTQ is enabled, this will also take care of purging the 4127 * ALTQ queue(s). 4128 */ 4129 if_qflush(ifp); 4130 } 4131 4132 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4133 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4134 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4135 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP) 4136 4137 static int 4138 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4139 { 4140 if_ctx_t ctx = if_getsoftc(ifp); 4141 struct ifreq *ifr = (struct ifreq *)data; 4142 #if defined(INET) || defined(INET6) 4143 struct ifaddr *ifa = (struct ifaddr *)data; 4144 #endif 4145 bool avoid_reset = false; 4146 int err = 0, reinit = 0, bits; 4147 4148 switch (command) { 4149 case SIOCSIFADDR: 4150 #ifdef INET 4151 if (ifa->ifa_addr->sa_family == AF_INET) 4152 avoid_reset = true; 4153 #endif 4154 #ifdef INET6 4155 if (ifa->ifa_addr->sa_family == AF_INET6) 4156 avoid_reset = true; 4157 #endif 4158 /* 4159 ** Calling init results in link renegotiation, 4160 ** so we avoid doing it when possible. 4161 */ 4162 if (avoid_reset) { 4163 if_setflagbits(ifp, IFF_UP,0); 4164 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4165 reinit = 1; 4166 #ifdef INET 4167 if (!(if_getflags(ifp) & IFF_NOARP)) 4168 arp_ifinit(ifp, ifa); 4169 #endif 4170 } else 4171 err = ether_ioctl(ifp, command, data); 4172 break; 4173 case SIOCSIFMTU: 4174 CTX_LOCK(ctx); 4175 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4176 CTX_UNLOCK(ctx); 4177 break; 4178 } 4179 bits = if_getdrvflags(ifp); 4180 /* stop the driver and free any clusters before proceeding */ 4181 iflib_stop(ctx); 4182 4183 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4184 STATE_LOCK(ctx); 4185 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4186 ctx->ifc_flags |= IFC_MULTISEG; 4187 else 4188 ctx->ifc_flags &= ~IFC_MULTISEG; 4189 STATE_UNLOCK(ctx); 4190 err = if_setmtu(ifp, ifr->ifr_mtu); 4191 } 4192 iflib_init_locked(ctx); 4193 STATE_LOCK(ctx); 4194 if_setdrvflags(ifp, bits); 4195 STATE_UNLOCK(ctx); 4196 CTX_UNLOCK(ctx); 4197 break; 4198 case SIOCSIFFLAGS: 4199 CTX_LOCK(ctx); 4200 if (if_getflags(ifp) & IFF_UP) { 4201 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4202 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4203 (IFF_PROMISC | IFF_ALLMULTI)) { 4204 CTX_UNLOCK(ctx); 4205 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4206 CTX_LOCK(ctx); 4207 } 4208 } else 4209 reinit = 1; 4210 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4211 iflib_stop(ctx); 4212 } 4213 ctx->ifc_if_flags = if_getflags(ifp); 4214 CTX_UNLOCK(ctx); 4215 break; 4216 case SIOCADDMULTI: 4217 case SIOCDELMULTI: 4218 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4219 CTX_LOCK(ctx); 4220 IFDI_INTR_DISABLE(ctx); 4221 IFDI_MULTI_SET(ctx); 4222 IFDI_INTR_ENABLE(ctx); 4223 CTX_UNLOCK(ctx); 4224 } 4225 break; 4226 case SIOCSIFMEDIA: 4227 CTX_LOCK(ctx); 4228 IFDI_MEDIA_SET(ctx); 4229 CTX_UNLOCK(ctx); 4230 /* FALLTHROUGH */ 4231 case SIOCGIFMEDIA: 4232 case SIOCGIFXMEDIA: 4233 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4234 break; 4235 case SIOCGI2C: 4236 { 4237 struct ifi2creq i2c; 4238 4239 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4240 if (err != 0) 4241 break; 4242 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4243 err = EINVAL; 4244 break; 4245 } 4246 if (i2c.len > sizeof(i2c.data)) { 4247 err = EINVAL; 4248 break; 4249 } 4250 4251 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4252 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4253 sizeof(i2c)); 4254 break; 4255 } 4256 case SIOCSIFCAP: 4257 { 4258 int mask, setmask, oldmask; 4259 4260 oldmask = if_getcapenable(ifp); 4261 mask = ifr->ifr_reqcap ^ oldmask; 4262 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP; 4263 setmask = 0; 4264 #ifdef TCP_OFFLOAD 4265 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4266 #endif 4267 setmask |= (mask & IFCAP_FLAGS); 4268 setmask |= (mask & IFCAP_WOL); 4269 4270 /* 4271 * If any RX csum has changed, change all the ones that 4272 * are supported by the driver. 4273 */ 4274 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4275 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4276 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4277 } 4278 4279 /* 4280 * want to ensure that traffic has stopped before we change any of the flags 4281 */ 4282 if (setmask) { 4283 CTX_LOCK(ctx); 4284 bits = if_getdrvflags(ifp); 4285 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4286 iflib_stop(ctx); 4287 STATE_LOCK(ctx); 4288 if_togglecapenable(ifp, setmask); 4289 STATE_UNLOCK(ctx); 4290 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4291 iflib_init_locked(ctx); 4292 STATE_LOCK(ctx); 4293 if_setdrvflags(ifp, bits); 4294 STATE_UNLOCK(ctx); 4295 CTX_UNLOCK(ctx); 4296 } 4297 if_vlancap(ifp); 4298 break; 4299 } 4300 case SIOCGPRIVATE_0: 4301 case SIOCSDRVSPEC: 4302 case SIOCGDRVSPEC: 4303 CTX_LOCK(ctx); 4304 err = IFDI_PRIV_IOCTL(ctx, command, data); 4305 CTX_UNLOCK(ctx); 4306 break; 4307 default: 4308 err = ether_ioctl(ifp, command, data); 4309 break; 4310 } 4311 if (reinit) 4312 iflib_if_init(ctx); 4313 return (err); 4314 } 4315 4316 static uint64_t 4317 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4318 { 4319 if_ctx_t ctx = if_getsoftc(ifp); 4320 4321 return (IFDI_GET_COUNTER(ctx, cnt)); 4322 } 4323 4324 /********************************************************************* 4325 * 4326 * OTHER FUNCTIONS EXPORTED TO THE STACK 4327 * 4328 **********************************************************************/ 4329 4330 static void 4331 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4332 { 4333 if_ctx_t ctx = if_getsoftc(ifp); 4334 4335 if ((void *)ctx != arg) 4336 return; 4337 4338 if ((vtag == 0) || (vtag > 4095)) 4339 return; 4340 4341 if (iflib_in_detach(ctx)) 4342 return; 4343 4344 CTX_LOCK(ctx); 4345 /* Driver may need all untagged packets to be flushed */ 4346 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4347 iflib_stop(ctx); 4348 IFDI_VLAN_REGISTER(ctx, vtag); 4349 /* Re-init to load the changes, if required */ 4350 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4351 iflib_init_locked(ctx); 4352 CTX_UNLOCK(ctx); 4353 } 4354 4355 static void 4356 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4357 { 4358 if_ctx_t ctx = if_getsoftc(ifp); 4359 4360 if ((void *)ctx != arg) 4361 return; 4362 4363 if ((vtag == 0) || (vtag > 4095)) 4364 return; 4365 4366 CTX_LOCK(ctx); 4367 /* Driver may need all tagged packets to be flushed */ 4368 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4369 iflib_stop(ctx); 4370 IFDI_VLAN_UNREGISTER(ctx, vtag); 4371 /* Re-init to load the changes, if required */ 4372 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4373 iflib_init_locked(ctx); 4374 CTX_UNLOCK(ctx); 4375 } 4376 4377 static void 4378 iflib_led_func(void *arg, int onoff) 4379 { 4380 if_ctx_t ctx = arg; 4381 4382 CTX_LOCK(ctx); 4383 IFDI_LED_FUNC(ctx, onoff); 4384 CTX_UNLOCK(ctx); 4385 } 4386 4387 /********************************************************************* 4388 * 4389 * BUS FUNCTION DEFINITIONS 4390 * 4391 **********************************************************************/ 4392 4393 int 4394 iflib_device_probe(device_t dev) 4395 { 4396 const pci_vendor_info_t *ent; 4397 if_shared_ctx_t sctx; 4398 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4399 uint16_t pci_vendor_id; 4400 4401 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4402 return (ENOTSUP); 4403 4404 pci_vendor_id = pci_get_vendor(dev); 4405 pci_device_id = pci_get_device(dev); 4406 pci_subvendor_id = pci_get_subvendor(dev); 4407 pci_subdevice_id = pci_get_subdevice(dev); 4408 pci_rev_id = pci_get_revid(dev); 4409 if (sctx->isc_parse_devinfo != NULL) 4410 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4411 4412 ent = sctx->isc_vendor_info; 4413 while (ent->pvi_vendor_id != 0) { 4414 if (pci_vendor_id != ent->pvi_vendor_id) { 4415 ent++; 4416 continue; 4417 } 4418 if ((pci_device_id == ent->pvi_device_id) && 4419 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4420 (ent->pvi_subvendor_id == 0)) && 4421 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4422 (ent->pvi_subdevice_id == 0)) && 4423 ((pci_rev_id == ent->pvi_rev_id) || 4424 (ent->pvi_rev_id == 0))) { 4425 device_set_desc_copy(dev, ent->pvi_name); 4426 /* this needs to be changed to zero if the bus probing code 4427 * ever stops re-probing on best match because the sctx 4428 * may have its values over written by register calls 4429 * in subsequent probes 4430 */ 4431 return (BUS_PROBE_DEFAULT); 4432 } 4433 ent++; 4434 } 4435 return (ENXIO); 4436 } 4437 4438 int 4439 iflib_device_probe_vendor(device_t dev) 4440 { 4441 int probe; 4442 4443 probe = iflib_device_probe(dev); 4444 if (probe == BUS_PROBE_DEFAULT) 4445 return (BUS_PROBE_VENDOR); 4446 else 4447 return (probe); 4448 } 4449 4450 static void 4451 iflib_reset_qvalues(if_ctx_t ctx) 4452 { 4453 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4454 if_shared_ctx_t sctx = ctx->ifc_sctx; 4455 device_t dev = ctx->ifc_dev; 4456 int i; 4457 4458 if (ctx->ifc_sysctl_ntxqs != 0) 4459 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4460 if (ctx->ifc_sysctl_nrxqs != 0) 4461 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4462 4463 for (i = 0; i < sctx->isc_ntxqs; i++) { 4464 if (ctx->ifc_sysctl_ntxds[i] != 0) 4465 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4466 else 4467 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4468 } 4469 4470 for (i = 0; i < sctx->isc_nrxqs; i++) { 4471 if (ctx->ifc_sysctl_nrxds[i] != 0) 4472 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4473 else 4474 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4475 } 4476 4477 for (i = 0; i < sctx->isc_nrxqs; i++) { 4478 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4479 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4480 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4481 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4482 } 4483 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4484 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4485 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4486 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4487 } 4488 if (!powerof2(scctx->isc_nrxd[i])) { 4489 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4490 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4491 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4492 } 4493 } 4494 4495 for (i = 0; i < sctx->isc_ntxqs; i++) { 4496 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4497 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4498 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4499 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4500 } 4501 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4502 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4503 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4504 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4505 } 4506 if (!powerof2(scctx->isc_ntxd[i])) { 4507 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4508 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4509 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4510 } 4511 } 4512 } 4513 4514 static void 4515 iflib_add_pfil(if_ctx_t ctx) 4516 { 4517 struct pfil_head *pfil; 4518 struct pfil_head_args pa; 4519 iflib_rxq_t rxq; 4520 int i; 4521 4522 pa.pa_version = PFIL_VERSION; 4523 pa.pa_flags = PFIL_IN; 4524 pa.pa_type = PFIL_TYPE_ETHERNET; 4525 pa.pa_headname = ctx->ifc_ifp->if_xname; 4526 pfil = pfil_head_register(&pa); 4527 4528 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4529 rxq->pfil = pfil; 4530 } 4531 } 4532 4533 static void 4534 iflib_rem_pfil(if_ctx_t ctx) 4535 { 4536 struct pfil_head *pfil; 4537 iflib_rxq_t rxq; 4538 int i; 4539 4540 rxq = ctx->ifc_rxqs; 4541 pfil = rxq->pfil; 4542 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4543 rxq->pfil = NULL; 4544 } 4545 pfil_head_unregister(pfil); 4546 } 4547 4548 static uint16_t 4549 get_ctx_core_offset(if_ctx_t ctx) 4550 { 4551 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4552 struct cpu_offset *op; 4553 uint16_t qc; 4554 uint16_t ret = ctx->ifc_sysctl_core_offset; 4555 4556 if (ret != CORE_OFFSET_UNSPECIFIED) 4557 return (ret); 4558 4559 if (ctx->ifc_sysctl_separate_txrx) 4560 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets; 4561 else 4562 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets); 4563 4564 mtx_lock(&cpu_offset_mtx); 4565 SLIST_FOREACH(op, &cpu_offsets, entries) { 4566 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4567 ret = op->offset; 4568 op->offset += qc; 4569 MPASS(op->refcount < UINT_MAX); 4570 op->refcount++; 4571 break; 4572 } 4573 } 4574 if (ret == CORE_OFFSET_UNSPECIFIED) { 4575 ret = 0; 4576 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4577 M_NOWAIT | M_ZERO); 4578 if (op == NULL) { 4579 device_printf(ctx->ifc_dev, 4580 "allocation for cpu offset failed.\n"); 4581 } else { 4582 op->offset = qc; 4583 op->refcount = 1; 4584 CPU_COPY(&ctx->ifc_cpus, &op->set); 4585 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4586 } 4587 } 4588 mtx_unlock(&cpu_offset_mtx); 4589 4590 return (ret); 4591 } 4592 4593 static void 4594 unref_ctx_core_offset(if_ctx_t ctx) 4595 { 4596 struct cpu_offset *op, *top; 4597 4598 mtx_lock(&cpu_offset_mtx); 4599 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4600 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4601 MPASS(op->refcount > 0); 4602 op->refcount--; 4603 if (op->refcount == 0) { 4604 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4605 free(op, M_IFLIB); 4606 } 4607 break; 4608 } 4609 } 4610 mtx_unlock(&cpu_offset_mtx); 4611 } 4612 4613 int 4614 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4615 { 4616 if_ctx_t ctx; 4617 if_t ifp; 4618 if_softc_ctx_t scctx; 4619 kobjop_desc_t kobj_desc; 4620 kobj_method_t *kobj_method; 4621 int err, msix, rid; 4622 int num_txd, num_rxd; 4623 4624 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4625 4626 if (sc == NULL) { 4627 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4628 device_set_softc(dev, ctx); 4629 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4630 } 4631 4632 ctx->ifc_sctx = sctx; 4633 ctx->ifc_dev = dev; 4634 ctx->ifc_softc = sc; 4635 4636 if ((err = iflib_register(ctx)) != 0) { 4637 device_printf(dev, "iflib_register failed %d\n", err); 4638 goto fail_ctx_free; 4639 } 4640 iflib_add_device_sysctl_pre(ctx); 4641 4642 scctx = &ctx->ifc_softc_ctx; 4643 ifp = ctx->ifc_ifp; 4644 4645 iflib_reset_qvalues(ctx); 4646 CTX_LOCK(ctx); 4647 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4648 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4649 goto fail_unlock; 4650 } 4651 _iflib_pre_assert(scctx); 4652 ctx->ifc_txrx = *scctx->isc_txrx; 4653 4654 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 4655 ctx->ifc_mediap = scctx->isc_media; 4656 4657 #ifdef INVARIANTS 4658 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4659 MPASS(scctx->isc_tx_csum_flags); 4660 #endif 4661 4662 if_setcapabilities(ifp, 4663 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP); 4664 if_setcapenable(ifp, 4665 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP); 4666 4667 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4668 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4669 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4670 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4671 4672 num_txd = iflib_num_tx_descs(ctx); 4673 num_rxd = iflib_num_rx_descs(ctx); 4674 4675 /* XXX change for per-queue sizes */ 4676 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4677 num_txd, num_rxd); 4678 4679 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 4680 scctx->isc_tx_nsegments = max(1, num_txd / 4681 MAX_SINGLE_PACKET_FRACTION); 4682 if (scctx->isc_tx_tso_segments_max > num_txd / 4683 MAX_SINGLE_PACKET_FRACTION) 4684 scctx->isc_tx_tso_segments_max = max(1, 4685 num_txd / MAX_SINGLE_PACKET_FRACTION); 4686 4687 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4688 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4689 /* 4690 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4691 * but some MACs do. 4692 */ 4693 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4694 IP_MAXPACKET)); 4695 /* 4696 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4697 * into account. In the worst case, each of these calls will 4698 * add another mbuf and, thus, the requirement for another DMA 4699 * segment. So for best performance, it doesn't make sense to 4700 * advertize a maximum of TSO segments that typically will 4701 * require defragmentation in iflib_encap(). 4702 */ 4703 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4704 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4705 } 4706 if (scctx->isc_rss_table_size == 0) 4707 scctx->isc_rss_table_size = 64; 4708 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4709 4710 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4711 /* XXX format name */ 4712 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4713 NULL, NULL, "admin"); 4714 4715 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4716 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4717 device_printf(dev, "Unable to fetch CPU list\n"); 4718 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4719 } 4720 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4721 4722 /* 4723 ** Now set up MSI or MSI-X, should return us the number of supported 4724 ** vectors (will be 1 for a legacy interrupt and MSI). 4725 */ 4726 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4727 msix = scctx->isc_vectors; 4728 } else if (scctx->isc_msix_bar != 0) 4729 /* 4730 * The simple fact that isc_msix_bar is not 0 does not mean we 4731 * we have a good value there that is known to work. 4732 */ 4733 msix = iflib_msix_init(ctx); 4734 else { 4735 scctx->isc_vectors = 1; 4736 scctx->isc_ntxqsets = 1; 4737 scctx->isc_nrxqsets = 1; 4738 scctx->isc_intr = IFLIB_INTR_LEGACY; 4739 msix = 0; 4740 } 4741 /* Get memory for the station queues */ 4742 if ((err = iflib_queues_alloc(ctx))) { 4743 device_printf(dev, "Unable to allocate queue memory\n"); 4744 goto fail_intr_free; 4745 } 4746 4747 if ((err = iflib_qset_structures_setup(ctx))) 4748 goto fail_queues; 4749 4750 /* 4751 * Now that we know how many queues there are, get the core offset. 4752 */ 4753 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 4754 4755 if (msix > 1) { 4756 /* 4757 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 4758 * aren't the default NULL implementation. 4759 */ 4760 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 4761 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4762 kobj_desc); 4763 if (kobj_method == &kobj_desc->deflt) { 4764 device_printf(dev, 4765 "MSI-X requires ifdi_rx_queue_intr_enable method"); 4766 err = EOPNOTSUPP; 4767 goto fail_queues; 4768 } 4769 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 4770 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4771 kobj_desc); 4772 if (kobj_method == &kobj_desc->deflt) { 4773 device_printf(dev, 4774 "MSI-X requires ifdi_tx_queue_intr_enable method"); 4775 err = EOPNOTSUPP; 4776 goto fail_queues; 4777 } 4778 4779 /* 4780 * Assign the MSI-X vectors. 4781 * Note that the default NULL ifdi_msix_intr_assign method will 4782 * fail here, too. 4783 */ 4784 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 4785 if (err != 0) { 4786 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 4787 err); 4788 goto fail_queues; 4789 } 4790 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 4791 rid = 0; 4792 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4793 MPASS(msix == 1); 4794 rid = 1; 4795 } 4796 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4797 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4798 goto fail_queues; 4799 } 4800 } else { 4801 device_printf(dev, 4802 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 4803 err = ENODEV; 4804 goto fail_intr_free; 4805 } 4806 4807 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4808 4809 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4810 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4811 goto fail_detach; 4812 } 4813 4814 /* 4815 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4816 * This must appear after the call to ether_ifattach() because 4817 * ether_ifattach() sets if_hdrlen to the default value. 4818 */ 4819 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4820 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4821 4822 if ((err = iflib_netmap_attach(ctx))) { 4823 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4824 goto fail_detach; 4825 } 4826 *ctxp = ctx; 4827 4828 DEBUGNET_SET(ctx->ifc_ifp, iflib); 4829 4830 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4831 iflib_add_device_sysctl_post(ctx); 4832 iflib_add_pfil(ctx); 4833 ctx->ifc_flags |= IFC_INIT_DONE; 4834 CTX_UNLOCK(ctx); 4835 4836 return (0); 4837 4838 fail_detach: 4839 ether_ifdetach(ctx->ifc_ifp); 4840 fail_intr_free: 4841 iflib_free_intr_mem(ctx); 4842 fail_queues: 4843 iflib_tx_structures_free(ctx); 4844 iflib_rx_structures_free(ctx); 4845 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task); 4846 IFDI_DETACH(ctx); 4847 fail_unlock: 4848 CTX_UNLOCK(ctx); 4849 iflib_deregister(ctx); 4850 fail_ctx_free: 4851 device_set_softc(ctx->ifc_dev, NULL); 4852 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4853 free(ctx->ifc_softc, M_IFLIB); 4854 free(ctx, M_IFLIB); 4855 return (err); 4856 } 4857 4858 int 4859 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4860 struct iflib_cloneattach_ctx *clctx) 4861 { 4862 int num_txd, num_rxd; 4863 int err; 4864 if_ctx_t ctx; 4865 if_t ifp; 4866 if_softc_ctx_t scctx; 4867 int i; 4868 void *sc; 4869 4870 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4871 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4872 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4873 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4874 ctx->ifc_flags |= IFC_PSEUDO; 4875 4876 ctx->ifc_sctx = sctx; 4877 ctx->ifc_softc = sc; 4878 ctx->ifc_dev = dev; 4879 4880 if ((err = iflib_register(ctx)) != 0) { 4881 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4882 goto fail_ctx_free; 4883 } 4884 iflib_add_device_sysctl_pre(ctx); 4885 4886 scctx = &ctx->ifc_softc_ctx; 4887 ifp = ctx->ifc_ifp; 4888 4889 iflib_reset_qvalues(ctx); 4890 CTX_LOCK(ctx); 4891 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4892 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4893 goto fail_unlock; 4894 } 4895 if (sctx->isc_flags & IFLIB_GEN_MAC) 4896 ether_gen_addr(ifp, &ctx->ifc_mac); 4897 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4898 clctx->cc_params)) != 0) { 4899 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4900 goto fail_unlock; 4901 } 4902 #ifdef INVARIANTS 4903 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4904 MPASS(scctx->isc_tx_csum_flags); 4905 #endif 4906 4907 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4908 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4909 4910 ifp->if_flags |= IFF_NOGROUP; 4911 if (sctx->isc_flags & IFLIB_PSEUDO) { 4912 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4913 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4914 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) { 4915 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4916 } else { 4917 if_attach(ctx->ifc_ifp); 4918 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t)); 4919 } 4920 4921 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4922 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4923 goto fail_detach; 4924 } 4925 *ctxp = ctx; 4926 4927 /* 4928 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4929 * This must appear after the call to ether_ifattach() because 4930 * ether_ifattach() sets if_hdrlen to the default value. 4931 */ 4932 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4933 if_setifheaderlen(ifp, 4934 sizeof(struct ether_vlan_header)); 4935 4936 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4937 iflib_add_device_sysctl_post(ctx); 4938 ctx->ifc_flags |= IFC_INIT_DONE; 4939 CTX_UNLOCK(ctx); 4940 return (0); 4941 } 4942 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4943 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4944 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4945 4946 _iflib_pre_assert(scctx); 4947 ctx->ifc_txrx = *scctx->isc_txrx; 4948 4949 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4950 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4951 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4952 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4953 4954 num_txd = iflib_num_tx_descs(ctx); 4955 num_rxd = iflib_num_rx_descs(ctx); 4956 4957 /* XXX change for per-queue sizes */ 4958 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4959 num_txd, num_rxd); 4960 4961 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 4962 scctx->isc_tx_nsegments = max(1, num_txd / 4963 MAX_SINGLE_PACKET_FRACTION); 4964 if (scctx->isc_tx_tso_segments_max > num_txd / 4965 MAX_SINGLE_PACKET_FRACTION) 4966 scctx->isc_tx_tso_segments_max = max(1, 4967 num_txd / MAX_SINGLE_PACKET_FRACTION); 4968 4969 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4970 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4971 /* 4972 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4973 * but some MACs do. 4974 */ 4975 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4976 IP_MAXPACKET)); 4977 /* 4978 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4979 * into account. In the worst case, each of these calls will 4980 * add another mbuf and, thus, the requirement for another DMA 4981 * segment. So for best performance, it doesn't make sense to 4982 * advertize a maximum of TSO segments that typically will 4983 * require defragmentation in iflib_encap(). 4984 */ 4985 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4986 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4987 } 4988 if (scctx->isc_rss_table_size == 0) 4989 scctx->isc_rss_table_size = 64; 4990 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4991 4992 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4993 /* XXX format name */ 4994 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4995 NULL, NULL, "admin"); 4996 4997 /* XXX --- can support > 1 -- but keep it simple for now */ 4998 scctx->isc_intr = IFLIB_INTR_LEGACY; 4999 5000 /* Get memory for the station queues */ 5001 if ((err = iflib_queues_alloc(ctx))) { 5002 device_printf(dev, "Unable to allocate queue memory\n"); 5003 goto fail_iflib_detach; 5004 } 5005 5006 if ((err = iflib_qset_structures_setup(ctx))) { 5007 device_printf(dev, "qset structure setup failed %d\n", err); 5008 goto fail_queues; 5009 } 5010 5011 /* 5012 * XXX What if anything do we want to do about interrupts? 5013 */ 5014 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5015 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5016 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5017 goto fail_detach; 5018 } 5019 5020 /* 5021 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5022 * This must appear after the call to ether_ifattach() because 5023 * ether_ifattach() sets if_hdrlen to the default value. 5024 */ 5025 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5026 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5027 5028 /* XXX handle more than one queue */ 5029 for (i = 0; i < scctx->isc_nrxqsets; i++) 5030 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 5031 5032 *ctxp = ctx; 5033 5034 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5035 iflib_add_device_sysctl_post(ctx); 5036 ctx->ifc_flags |= IFC_INIT_DONE; 5037 CTX_UNLOCK(ctx); 5038 5039 return (0); 5040 fail_detach: 5041 ether_ifdetach(ctx->ifc_ifp); 5042 fail_queues: 5043 iflib_tx_structures_free(ctx); 5044 iflib_rx_structures_free(ctx); 5045 fail_iflib_detach: 5046 IFDI_DETACH(ctx); 5047 fail_unlock: 5048 CTX_UNLOCK(ctx); 5049 iflib_deregister(ctx); 5050 fail_ctx_free: 5051 free(ctx->ifc_softc, M_IFLIB); 5052 free(ctx, M_IFLIB); 5053 return (err); 5054 } 5055 5056 int 5057 iflib_pseudo_deregister(if_ctx_t ctx) 5058 { 5059 if_t ifp = ctx->ifc_ifp; 5060 if_shared_ctx_t sctx = ctx->ifc_sctx; 5061 iflib_txq_t txq; 5062 iflib_rxq_t rxq; 5063 int i, j; 5064 struct taskqgroup *tqg; 5065 iflib_fl_t fl; 5066 5067 /* Unregister VLAN event handlers early */ 5068 iflib_unregister_vlan_handlers(ctx); 5069 5070 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5071 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) { 5072 bpfdetach(ifp); 5073 if_detach(ifp); 5074 } else { 5075 ether_ifdetach(ifp); 5076 } 5077 /* XXX drain any dependent tasks */ 5078 tqg = qgroup_if_io_tqg; 5079 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5080 callout_drain(&txq->ift_timer); 5081 #ifdef DEV_NETMAP 5082 callout_drain(&txq->ift_netmap_timer); 5083 #endif /* DEV_NETMAP */ 5084 if (txq->ift_task.gt_uniq != NULL) 5085 taskqgroup_detach(tqg, &txq->ift_task); 5086 } 5087 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5088 callout_drain(&rxq->ifr_watchdog); 5089 if (rxq->ifr_task.gt_uniq != NULL) 5090 taskqgroup_detach(tqg, &rxq->ifr_task); 5091 5092 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5093 free(fl->ifl_rx_bitmap, M_IFLIB); 5094 } 5095 tqg = qgroup_if_config_tqg; 5096 if (ctx->ifc_admin_task.gt_uniq != NULL) 5097 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5098 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5099 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5100 5101 iflib_tx_structures_free(ctx); 5102 iflib_rx_structures_free(ctx); 5103 5104 iflib_deregister(ctx); 5105 5106 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5107 free(ctx->ifc_softc, M_IFLIB); 5108 free(ctx, M_IFLIB); 5109 return (0); 5110 } 5111 5112 int 5113 iflib_device_attach(device_t dev) 5114 { 5115 if_ctx_t ctx; 5116 if_shared_ctx_t sctx; 5117 5118 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5119 return (ENOTSUP); 5120 5121 pci_enable_busmaster(dev); 5122 5123 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5124 } 5125 5126 int 5127 iflib_device_deregister(if_ctx_t ctx) 5128 { 5129 if_t ifp = ctx->ifc_ifp; 5130 iflib_txq_t txq; 5131 iflib_rxq_t rxq; 5132 device_t dev = ctx->ifc_dev; 5133 int i, j; 5134 struct taskqgroup *tqg; 5135 iflib_fl_t fl; 5136 5137 /* Make sure VLANS are not using driver */ 5138 if (if_vlantrunkinuse(ifp)) { 5139 device_printf(dev, "Vlan in use, detach first\n"); 5140 return (EBUSY); 5141 } 5142 #ifdef PCI_IOV 5143 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5144 device_printf(dev, "SR-IOV in use; detach first.\n"); 5145 return (EBUSY); 5146 } 5147 #endif 5148 5149 STATE_LOCK(ctx); 5150 ctx->ifc_flags |= IFC_IN_DETACH; 5151 STATE_UNLOCK(ctx); 5152 5153 /* Unregister VLAN handlers before calling iflib_stop() */ 5154 iflib_unregister_vlan_handlers(ctx); 5155 5156 iflib_netmap_detach(ifp); 5157 ether_ifdetach(ifp); 5158 5159 CTX_LOCK(ctx); 5160 iflib_stop(ctx); 5161 CTX_UNLOCK(ctx); 5162 5163 iflib_rem_pfil(ctx); 5164 if (ctx->ifc_led_dev != NULL) 5165 led_destroy(ctx->ifc_led_dev); 5166 /* XXX drain any dependent tasks */ 5167 tqg = qgroup_if_io_tqg; 5168 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5169 callout_drain(&txq->ift_timer); 5170 #ifdef DEV_NETMAP 5171 callout_drain(&txq->ift_netmap_timer); 5172 #endif /* DEV_NETMAP */ 5173 if (txq->ift_task.gt_uniq != NULL) 5174 taskqgroup_detach(tqg, &txq->ift_task); 5175 } 5176 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5177 if (rxq->ifr_task.gt_uniq != NULL) 5178 taskqgroup_detach(tqg, &rxq->ifr_task); 5179 5180 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5181 free(fl->ifl_rx_bitmap, M_IFLIB); 5182 } 5183 tqg = qgroup_if_config_tqg; 5184 if (ctx->ifc_admin_task.gt_uniq != NULL) 5185 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5186 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5187 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5188 CTX_LOCK(ctx); 5189 IFDI_DETACH(ctx); 5190 CTX_UNLOCK(ctx); 5191 5192 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5193 iflib_free_intr_mem(ctx); 5194 5195 bus_generic_detach(dev); 5196 5197 iflib_tx_structures_free(ctx); 5198 iflib_rx_structures_free(ctx); 5199 5200 iflib_deregister(ctx); 5201 5202 device_set_softc(ctx->ifc_dev, NULL); 5203 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5204 free(ctx->ifc_softc, M_IFLIB); 5205 unref_ctx_core_offset(ctx); 5206 free(ctx, M_IFLIB); 5207 return (0); 5208 } 5209 5210 static void 5211 iflib_free_intr_mem(if_ctx_t ctx) 5212 { 5213 5214 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5215 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5216 } 5217 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5218 pci_release_msi(ctx->ifc_dev); 5219 } 5220 if (ctx->ifc_msix_mem != NULL) { 5221 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5222 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5223 ctx->ifc_msix_mem = NULL; 5224 } 5225 } 5226 5227 int 5228 iflib_device_detach(device_t dev) 5229 { 5230 if_ctx_t ctx = device_get_softc(dev); 5231 5232 return (iflib_device_deregister(ctx)); 5233 } 5234 5235 int 5236 iflib_device_suspend(device_t dev) 5237 { 5238 if_ctx_t ctx = device_get_softc(dev); 5239 5240 CTX_LOCK(ctx); 5241 IFDI_SUSPEND(ctx); 5242 CTX_UNLOCK(ctx); 5243 5244 return bus_generic_suspend(dev); 5245 } 5246 int 5247 iflib_device_shutdown(device_t dev) 5248 { 5249 if_ctx_t ctx = device_get_softc(dev); 5250 5251 CTX_LOCK(ctx); 5252 IFDI_SHUTDOWN(ctx); 5253 CTX_UNLOCK(ctx); 5254 5255 return bus_generic_suspend(dev); 5256 } 5257 5258 int 5259 iflib_device_resume(device_t dev) 5260 { 5261 if_ctx_t ctx = device_get_softc(dev); 5262 iflib_txq_t txq = ctx->ifc_txqs; 5263 5264 CTX_LOCK(ctx); 5265 IFDI_RESUME(ctx); 5266 iflib_if_init_locked(ctx); 5267 CTX_UNLOCK(ctx); 5268 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5269 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5270 5271 return (bus_generic_resume(dev)); 5272 } 5273 5274 int 5275 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5276 { 5277 int error; 5278 if_ctx_t ctx = device_get_softc(dev); 5279 5280 CTX_LOCK(ctx); 5281 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5282 CTX_UNLOCK(ctx); 5283 5284 return (error); 5285 } 5286 5287 void 5288 iflib_device_iov_uninit(device_t dev) 5289 { 5290 if_ctx_t ctx = device_get_softc(dev); 5291 5292 CTX_LOCK(ctx); 5293 IFDI_IOV_UNINIT(ctx); 5294 CTX_UNLOCK(ctx); 5295 } 5296 5297 int 5298 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5299 { 5300 int error; 5301 if_ctx_t ctx = device_get_softc(dev); 5302 5303 CTX_LOCK(ctx); 5304 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5305 CTX_UNLOCK(ctx); 5306 5307 return (error); 5308 } 5309 5310 /********************************************************************* 5311 * 5312 * MODULE FUNCTION DEFINITIONS 5313 * 5314 **********************************************************************/ 5315 5316 /* 5317 * - Start a fast taskqueue thread for each core 5318 * - Start a taskqueue for control operations 5319 */ 5320 static int 5321 iflib_module_init(void) 5322 { 5323 return (0); 5324 } 5325 5326 static int 5327 iflib_module_event_handler(module_t mod, int what, void *arg) 5328 { 5329 int err; 5330 5331 switch (what) { 5332 case MOD_LOAD: 5333 if ((err = iflib_module_init()) != 0) 5334 return (err); 5335 break; 5336 case MOD_UNLOAD: 5337 return (EBUSY); 5338 default: 5339 return (EOPNOTSUPP); 5340 } 5341 5342 return (0); 5343 } 5344 5345 /********************************************************************* 5346 * 5347 * PUBLIC FUNCTION DEFINITIONS 5348 * ordered as in iflib.h 5349 * 5350 **********************************************************************/ 5351 5352 static void 5353 _iflib_assert(if_shared_ctx_t sctx) 5354 { 5355 int i; 5356 5357 MPASS(sctx->isc_tx_maxsize); 5358 MPASS(sctx->isc_tx_maxsegsize); 5359 5360 MPASS(sctx->isc_rx_maxsize); 5361 MPASS(sctx->isc_rx_nsegments); 5362 MPASS(sctx->isc_rx_maxsegsize); 5363 5364 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5365 for (i = 0; i < sctx->isc_nrxqs; i++) { 5366 MPASS(sctx->isc_nrxd_min[i]); 5367 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5368 MPASS(sctx->isc_nrxd_max[i]); 5369 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5370 MPASS(sctx->isc_nrxd_default[i]); 5371 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5372 } 5373 5374 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5375 for (i = 0; i < sctx->isc_ntxqs; i++) { 5376 MPASS(sctx->isc_ntxd_min[i]); 5377 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5378 MPASS(sctx->isc_ntxd_max[i]); 5379 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5380 MPASS(sctx->isc_ntxd_default[i]); 5381 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5382 } 5383 } 5384 5385 static void 5386 _iflib_pre_assert(if_softc_ctx_t scctx) 5387 { 5388 5389 MPASS(scctx->isc_txrx->ift_txd_encap); 5390 MPASS(scctx->isc_txrx->ift_txd_flush); 5391 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5392 MPASS(scctx->isc_txrx->ift_rxd_available); 5393 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5394 MPASS(scctx->isc_txrx->ift_rxd_refill); 5395 MPASS(scctx->isc_txrx->ift_rxd_flush); 5396 } 5397 5398 static int 5399 iflib_register(if_ctx_t ctx) 5400 { 5401 if_shared_ctx_t sctx = ctx->ifc_sctx; 5402 driver_t *driver = sctx->isc_driver; 5403 device_t dev = ctx->ifc_dev; 5404 if_t ifp; 5405 u_char type; 5406 int iflags; 5407 5408 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0) 5409 _iflib_assert(sctx); 5410 5411 CTX_LOCK_INIT(ctx); 5412 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5413 if (sctx->isc_flags & IFLIB_PSEUDO) { 5414 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) 5415 type = IFT_ETHER; 5416 else 5417 type = IFT_PPP; 5418 } else 5419 type = IFT_ETHER; 5420 ifp = ctx->ifc_ifp = if_alloc(type); 5421 if (ifp == NULL) { 5422 device_printf(dev, "can not allocate ifnet structure\n"); 5423 return (ENOMEM); 5424 } 5425 5426 /* 5427 * Initialize our context's device specific methods 5428 */ 5429 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5430 kobj_class_compile((kobj_class_t) driver); 5431 5432 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5433 if_setsoftc(ifp, ctx); 5434 if_setdev(ifp, dev); 5435 if_setinitfn(ifp, iflib_if_init); 5436 if_setioctlfn(ifp, iflib_if_ioctl); 5437 #ifdef ALTQ 5438 if_setstartfn(ifp, iflib_altq_if_start); 5439 if_settransmitfn(ifp, iflib_altq_if_transmit); 5440 if_setsendqready(ifp); 5441 #else 5442 if_settransmitfn(ifp, iflib_if_transmit); 5443 #endif 5444 if_setqflushfn(ifp, iflib_if_qflush); 5445 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH; 5446 5447 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5448 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) 5449 iflags |= IFF_POINTOPOINT; 5450 else 5451 iflags |= IFF_BROADCAST | IFF_SIMPLEX; 5452 if_setflags(ifp, iflags); 5453 ctx->ifc_vlan_attach_event = 5454 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5455 EVENTHANDLER_PRI_FIRST); 5456 ctx->ifc_vlan_detach_event = 5457 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5458 EVENTHANDLER_PRI_FIRST); 5459 5460 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5461 ctx->ifc_mediap = &ctx->ifc_media; 5462 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5463 iflib_media_change, iflib_media_status); 5464 } 5465 return (0); 5466 } 5467 5468 static void 5469 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5470 { 5471 /* Unregister VLAN events */ 5472 if (ctx->ifc_vlan_attach_event != NULL) { 5473 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5474 ctx->ifc_vlan_attach_event = NULL; 5475 } 5476 if (ctx->ifc_vlan_detach_event != NULL) { 5477 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5478 ctx->ifc_vlan_detach_event = NULL; 5479 } 5480 5481 } 5482 5483 static void 5484 iflib_deregister(if_ctx_t ctx) 5485 { 5486 if_t ifp = ctx->ifc_ifp; 5487 5488 /* Remove all media */ 5489 ifmedia_removeall(&ctx->ifc_media); 5490 5491 /* Ensure that VLAN event handlers are unregistered */ 5492 iflib_unregister_vlan_handlers(ctx); 5493 5494 /* Release kobject reference */ 5495 kobj_delete((kobj_t) ctx, NULL); 5496 5497 /* Free the ifnet structure */ 5498 if_free(ifp); 5499 5500 STATE_LOCK_DESTROY(ctx); 5501 5502 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5503 CTX_LOCK_DESTROY(ctx); 5504 } 5505 5506 static int 5507 iflib_queues_alloc(if_ctx_t ctx) 5508 { 5509 if_shared_ctx_t sctx = ctx->ifc_sctx; 5510 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5511 device_t dev = ctx->ifc_dev; 5512 int nrxqsets = scctx->isc_nrxqsets; 5513 int ntxqsets = scctx->isc_ntxqsets; 5514 iflib_txq_t txq; 5515 iflib_rxq_t rxq; 5516 iflib_fl_t fl = NULL; 5517 int i, j, cpu, err, txconf, rxconf; 5518 iflib_dma_info_t ifdip; 5519 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5520 uint32_t *txqsizes = scctx->isc_txqsizes; 5521 uint8_t nrxqs = sctx->isc_nrxqs; 5522 uint8_t ntxqs = sctx->isc_ntxqs; 5523 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5524 caddr_t *vaddrs; 5525 uint64_t *paddrs; 5526 5527 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5528 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5529 5530 /* Allocate the TX ring struct memory */ 5531 if (!(ctx->ifc_txqs = 5532 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5533 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5534 device_printf(dev, "Unable to allocate TX ring memory\n"); 5535 err = ENOMEM; 5536 goto fail; 5537 } 5538 5539 /* Now allocate the RX */ 5540 if (!(ctx->ifc_rxqs = 5541 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5542 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5543 device_printf(dev, "Unable to allocate RX ring memory\n"); 5544 err = ENOMEM; 5545 goto rx_fail; 5546 } 5547 5548 txq = ctx->ifc_txqs; 5549 rxq = ctx->ifc_rxqs; 5550 5551 /* 5552 * XXX handle allocation failure 5553 */ 5554 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5555 /* Set up some basics */ 5556 5557 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5558 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5559 device_printf(dev, 5560 "Unable to allocate TX DMA info memory\n"); 5561 err = ENOMEM; 5562 goto err_tx_desc; 5563 } 5564 txq->ift_ifdi = ifdip; 5565 for (j = 0; j < ntxqs; j++, ifdip++) { 5566 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5567 device_printf(dev, 5568 "Unable to allocate TX descriptors\n"); 5569 err = ENOMEM; 5570 goto err_tx_desc; 5571 } 5572 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5573 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5574 } 5575 txq->ift_ctx = ctx; 5576 txq->ift_id = i; 5577 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5578 txq->ift_br_offset = 1; 5579 } else { 5580 txq->ift_br_offset = 0; 5581 } 5582 5583 if (iflib_txsd_alloc(txq)) { 5584 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5585 err = ENOMEM; 5586 goto err_tx_desc; 5587 } 5588 5589 /* Initialize the TX lock */ 5590 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5591 device_get_nameunit(dev), txq->ift_id); 5592 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5593 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5594 txq->ift_timer.c_cpu = cpu; 5595 #ifdef DEV_NETMAP 5596 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 5597 txq->ift_netmap_timer.c_cpu = cpu; 5598 #endif /* DEV_NETMAP */ 5599 5600 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5601 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5602 if (err) { 5603 /* XXX free any allocated rings */ 5604 device_printf(dev, "Unable to allocate buf_ring\n"); 5605 goto err_tx_desc; 5606 } 5607 } 5608 5609 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5610 /* Set up some basics */ 5611 callout_init(&rxq->ifr_watchdog, 1); 5612 5613 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5614 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5615 device_printf(dev, 5616 "Unable to allocate RX DMA info memory\n"); 5617 err = ENOMEM; 5618 goto err_tx_desc; 5619 } 5620 5621 rxq->ifr_ifdi = ifdip; 5622 /* XXX this needs to be changed if #rx queues != #tx queues */ 5623 rxq->ifr_ntxqirq = 1; 5624 rxq->ifr_txqid[0] = i; 5625 for (j = 0; j < nrxqs; j++, ifdip++) { 5626 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5627 device_printf(dev, 5628 "Unable to allocate RX descriptors\n"); 5629 err = ENOMEM; 5630 goto err_tx_desc; 5631 } 5632 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5633 } 5634 rxq->ifr_ctx = ctx; 5635 rxq->ifr_id = i; 5636 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5637 rxq->ifr_fl_offset = 1; 5638 } else { 5639 rxq->ifr_fl_offset = 0; 5640 } 5641 rxq->ifr_nfl = nfree_lists; 5642 if (!(fl = 5643 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5644 device_printf(dev, "Unable to allocate free list memory\n"); 5645 err = ENOMEM; 5646 goto err_tx_desc; 5647 } 5648 rxq->ifr_fl = fl; 5649 for (j = 0; j < nfree_lists; j++) { 5650 fl[j].ifl_rxq = rxq; 5651 fl[j].ifl_id = j; 5652 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5653 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5654 } 5655 /* Allocate receive buffers for the ring */ 5656 if (iflib_rxsd_alloc(rxq)) { 5657 device_printf(dev, 5658 "Critical Failure setting up receive buffers\n"); 5659 err = ENOMEM; 5660 goto err_rx_desc; 5661 } 5662 5663 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5664 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5665 M_WAITOK); 5666 } 5667 5668 /* TXQs */ 5669 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5670 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5671 for (i = 0; i < ntxqsets; i++) { 5672 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5673 5674 for (j = 0; j < ntxqs; j++, di++) { 5675 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5676 paddrs[i*ntxqs + j] = di->idi_paddr; 5677 } 5678 } 5679 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5680 device_printf(ctx->ifc_dev, 5681 "Unable to allocate device TX queue\n"); 5682 iflib_tx_structures_free(ctx); 5683 free(vaddrs, M_IFLIB); 5684 free(paddrs, M_IFLIB); 5685 goto err_rx_desc; 5686 } 5687 free(vaddrs, M_IFLIB); 5688 free(paddrs, M_IFLIB); 5689 5690 /* RXQs */ 5691 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5692 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5693 for (i = 0; i < nrxqsets; i++) { 5694 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5695 5696 for (j = 0; j < nrxqs; j++, di++) { 5697 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5698 paddrs[i*nrxqs + j] = di->idi_paddr; 5699 } 5700 } 5701 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5702 device_printf(ctx->ifc_dev, 5703 "Unable to allocate device RX queue\n"); 5704 iflib_tx_structures_free(ctx); 5705 free(vaddrs, M_IFLIB); 5706 free(paddrs, M_IFLIB); 5707 goto err_rx_desc; 5708 } 5709 free(vaddrs, M_IFLIB); 5710 free(paddrs, M_IFLIB); 5711 5712 return (0); 5713 5714 /* XXX handle allocation failure changes */ 5715 err_rx_desc: 5716 err_tx_desc: 5717 rx_fail: 5718 if (ctx->ifc_rxqs != NULL) 5719 free(ctx->ifc_rxqs, M_IFLIB); 5720 ctx->ifc_rxqs = NULL; 5721 if (ctx->ifc_txqs != NULL) 5722 free(ctx->ifc_txqs, M_IFLIB); 5723 ctx->ifc_txqs = NULL; 5724 fail: 5725 return (err); 5726 } 5727 5728 static int 5729 iflib_tx_structures_setup(if_ctx_t ctx) 5730 { 5731 iflib_txq_t txq = ctx->ifc_txqs; 5732 int i; 5733 5734 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5735 iflib_txq_setup(txq); 5736 5737 return (0); 5738 } 5739 5740 static void 5741 iflib_tx_structures_free(if_ctx_t ctx) 5742 { 5743 iflib_txq_t txq = ctx->ifc_txqs; 5744 if_shared_ctx_t sctx = ctx->ifc_sctx; 5745 int i, j; 5746 5747 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5748 for (j = 0; j < sctx->isc_ntxqs; j++) 5749 iflib_dma_free(&txq->ift_ifdi[j]); 5750 iflib_txq_destroy(txq); 5751 } 5752 free(ctx->ifc_txqs, M_IFLIB); 5753 ctx->ifc_txqs = NULL; 5754 IFDI_QUEUES_FREE(ctx); 5755 } 5756 5757 /********************************************************************* 5758 * 5759 * Initialize all receive rings. 5760 * 5761 **********************************************************************/ 5762 static int 5763 iflib_rx_structures_setup(if_ctx_t ctx) 5764 { 5765 iflib_rxq_t rxq = ctx->ifc_rxqs; 5766 int q; 5767 #if defined(INET6) || defined(INET) 5768 int err, i; 5769 #endif 5770 5771 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5772 #if defined(INET6) || defined(INET) 5773 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) { 5774 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5775 TCP_LRO_ENTRIES, min(1024, 5776 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 5777 if (err != 0) { 5778 device_printf(ctx->ifc_dev, 5779 "LRO Initialization failed!\n"); 5780 goto fail; 5781 } 5782 } 5783 #endif 5784 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5785 } 5786 return (0); 5787 #if defined(INET6) || defined(INET) 5788 fail: 5789 /* 5790 * Free LRO resources allocated so far, we will only handle 5791 * the rings that completed, the failing case will have 5792 * cleaned up for itself. 'q' failed, so its the terminus. 5793 */ 5794 rxq = ctx->ifc_rxqs; 5795 for (i = 0; i < q; ++i, rxq++) { 5796 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5797 tcp_lro_free(&rxq->ifr_lc); 5798 } 5799 return (err); 5800 #endif 5801 } 5802 5803 /********************************************************************* 5804 * 5805 * Free all receive rings. 5806 * 5807 **********************************************************************/ 5808 static void 5809 iflib_rx_structures_free(if_ctx_t ctx) 5810 { 5811 iflib_rxq_t rxq = ctx->ifc_rxqs; 5812 if_shared_ctx_t sctx = ctx->ifc_sctx; 5813 int i, j; 5814 5815 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5816 for (j = 0; j < sctx->isc_nrxqs; j++) 5817 iflib_dma_free(&rxq->ifr_ifdi[j]); 5818 iflib_rx_sds_free(rxq); 5819 #if defined(INET6) || defined(INET) 5820 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5821 tcp_lro_free(&rxq->ifr_lc); 5822 #endif 5823 } 5824 free(ctx->ifc_rxqs, M_IFLIB); 5825 ctx->ifc_rxqs = NULL; 5826 } 5827 5828 static int 5829 iflib_qset_structures_setup(if_ctx_t ctx) 5830 { 5831 int err; 5832 5833 /* 5834 * It is expected that the caller takes care of freeing queues if this 5835 * fails. 5836 */ 5837 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5838 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5839 return (err); 5840 } 5841 5842 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5843 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5844 5845 return (err); 5846 } 5847 5848 int 5849 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5850 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5851 { 5852 5853 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5854 } 5855 5856 #ifdef SMP 5857 static int 5858 find_nth(if_ctx_t ctx, int qid) 5859 { 5860 cpuset_t cpus; 5861 int i, cpuid, eqid, count; 5862 5863 CPU_COPY(&ctx->ifc_cpus, &cpus); 5864 count = CPU_COUNT(&cpus); 5865 eqid = qid % count; 5866 /* clear up to the qid'th bit */ 5867 for (i = 0; i < eqid; i++) { 5868 cpuid = CPU_FFS(&cpus); 5869 MPASS(cpuid != 0); 5870 CPU_CLR(cpuid-1, &cpus); 5871 } 5872 cpuid = CPU_FFS(&cpus); 5873 MPASS(cpuid != 0); 5874 return (cpuid-1); 5875 } 5876 5877 #ifdef SCHED_ULE 5878 extern struct cpu_group *cpu_top; /* CPU topology */ 5879 5880 static int 5881 find_child_with_core(int cpu, struct cpu_group *grp) 5882 { 5883 int i; 5884 5885 if (grp->cg_children == 0) 5886 return -1; 5887 5888 MPASS(grp->cg_child); 5889 for (i = 0; i < grp->cg_children; i++) { 5890 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5891 return i; 5892 } 5893 5894 return -1; 5895 } 5896 5897 /* 5898 * Find the nth "close" core to the specified core 5899 * "close" is defined as the deepest level that shares 5900 * at least an L2 cache. With threads, this will be 5901 * threads on the same core. If the shared cache is L3 5902 * or higher, simply returns the same core. 5903 */ 5904 static int 5905 find_close_core(int cpu, int core_offset) 5906 { 5907 struct cpu_group *grp; 5908 int i; 5909 int fcpu; 5910 cpuset_t cs; 5911 5912 grp = cpu_top; 5913 if (grp == NULL) 5914 return cpu; 5915 i = 0; 5916 while ((i = find_child_with_core(cpu, grp)) != -1) { 5917 /* If the child only has one cpu, don't descend */ 5918 if (grp->cg_child[i].cg_count <= 1) 5919 break; 5920 grp = &grp->cg_child[i]; 5921 } 5922 5923 /* If they don't share at least an L2 cache, use the same CPU */ 5924 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5925 return cpu; 5926 5927 /* Now pick one */ 5928 CPU_COPY(&grp->cg_mask, &cs); 5929 5930 /* Add the selected CPU offset to core offset. */ 5931 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5932 if (fcpu - 1 == cpu) 5933 break; 5934 CPU_CLR(fcpu - 1, &cs); 5935 } 5936 MPASS(fcpu); 5937 5938 core_offset += i; 5939 5940 CPU_COPY(&grp->cg_mask, &cs); 5941 for (i = core_offset % grp->cg_count; i > 0; i--) { 5942 MPASS(CPU_FFS(&cs)); 5943 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5944 } 5945 MPASS(CPU_FFS(&cs)); 5946 return CPU_FFS(&cs) - 1; 5947 } 5948 #else 5949 static int 5950 find_close_core(int cpu, int core_offset __unused) 5951 { 5952 return cpu; 5953 } 5954 #endif 5955 5956 static int 5957 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5958 { 5959 switch (type) { 5960 case IFLIB_INTR_TX: 5961 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5962 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5963 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5964 case IFLIB_INTR_RX: 5965 case IFLIB_INTR_RXTX: 5966 /* RX queues get the specified core */ 5967 return qid / CPU_COUNT(&ctx->ifc_cpus); 5968 default: 5969 return -1; 5970 } 5971 } 5972 #else 5973 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5974 #define find_close_core(cpuid, tid) CPU_FIRST() 5975 #define find_nth(ctx, gid) CPU_FIRST() 5976 #endif 5977 5978 /* Just to avoid copy/paste */ 5979 static inline int 5980 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5981 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5982 const char *name) 5983 { 5984 device_t dev; 5985 int co, cpuid, err, tid; 5986 5987 dev = ctx->ifc_dev; 5988 co = ctx->ifc_sysctl_core_offset; 5989 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX) 5990 co += ctx->ifc_softc_ctx.isc_nrxqsets; 5991 cpuid = find_nth(ctx, qid + co); 5992 tid = get_core_offset(ctx, type, qid); 5993 if (tid < 0) { 5994 device_printf(dev, "get_core_offset failed\n"); 5995 return (EOPNOTSUPP); 5996 } 5997 cpuid = find_close_core(cpuid, tid); 5998 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 5999 name); 6000 if (err) { 6001 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6002 return (err); 6003 } 6004 #ifdef notyet 6005 if (cpuid > ctx->ifc_cpuid_highest) 6006 ctx->ifc_cpuid_highest = cpuid; 6007 #endif 6008 return (0); 6009 } 6010 6011 int 6012 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6013 iflib_intr_type_t type, driver_filter_t *filter, 6014 void *filter_arg, int qid, const char *name) 6015 { 6016 device_t dev; 6017 struct grouptask *gtask; 6018 struct taskqgroup *tqg; 6019 iflib_filter_info_t info; 6020 gtask_fn_t *fn; 6021 int tqrid, err; 6022 driver_filter_t *intr_fast; 6023 void *q; 6024 6025 info = &ctx->ifc_filter_info; 6026 tqrid = rid; 6027 6028 switch (type) { 6029 /* XXX merge tx/rx for netmap? */ 6030 case IFLIB_INTR_TX: 6031 q = &ctx->ifc_txqs[qid]; 6032 info = &ctx->ifc_txqs[qid].ift_filter_info; 6033 gtask = &ctx->ifc_txqs[qid].ift_task; 6034 tqg = qgroup_if_io_tqg; 6035 fn = _task_fn_tx; 6036 intr_fast = iflib_fast_intr; 6037 GROUPTASK_INIT(gtask, 0, fn, q); 6038 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6039 break; 6040 case IFLIB_INTR_RX: 6041 q = &ctx->ifc_rxqs[qid]; 6042 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6043 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6044 tqg = qgroup_if_io_tqg; 6045 fn = _task_fn_rx; 6046 intr_fast = iflib_fast_intr; 6047 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6048 break; 6049 case IFLIB_INTR_RXTX: 6050 q = &ctx->ifc_rxqs[qid]; 6051 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6052 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6053 tqg = qgroup_if_io_tqg; 6054 fn = _task_fn_rx; 6055 intr_fast = iflib_fast_intr_rxtx; 6056 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6057 break; 6058 case IFLIB_INTR_ADMIN: 6059 q = ctx; 6060 tqrid = -1; 6061 info = &ctx->ifc_filter_info; 6062 gtask = &ctx->ifc_admin_task; 6063 tqg = qgroup_if_config_tqg; 6064 fn = _task_fn_admin; 6065 intr_fast = iflib_fast_intr_ctx; 6066 break; 6067 default: 6068 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6069 __func__); 6070 return (EINVAL); 6071 } 6072 6073 info->ifi_filter = filter; 6074 info->ifi_filter_arg = filter_arg; 6075 info->ifi_task = gtask; 6076 info->ifi_ctx = q; 6077 6078 dev = ctx->ifc_dev; 6079 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6080 if (err != 0) { 6081 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6082 return (err); 6083 } 6084 if (type == IFLIB_INTR_ADMIN) 6085 return (0); 6086 6087 if (tqrid != -1) { 6088 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6089 q, name); 6090 if (err) 6091 return (err); 6092 } else { 6093 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6094 } 6095 6096 return (0); 6097 } 6098 6099 void 6100 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6101 { 6102 struct grouptask *gtask; 6103 struct taskqgroup *tqg; 6104 gtask_fn_t *fn; 6105 void *q; 6106 int err; 6107 6108 switch (type) { 6109 case IFLIB_INTR_TX: 6110 q = &ctx->ifc_txqs[qid]; 6111 gtask = &ctx->ifc_txqs[qid].ift_task; 6112 tqg = qgroup_if_io_tqg; 6113 fn = _task_fn_tx; 6114 GROUPTASK_INIT(gtask, 0, fn, q); 6115 break; 6116 case IFLIB_INTR_RX: 6117 q = &ctx->ifc_rxqs[qid]; 6118 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6119 tqg = qgroup_if_io_tqg; 6120 fn = _task_fn_rx; 6121 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6122 break; 6123 case IFLIB_INTR_IOV: 6124 q = ctx; 6125 gtask = &ctx->ifc_vflr_task; 6126 tqg = qgroup_if_config_tqg; 6127 fn = _task_fn_iov; 6128 GROUPTASK_INIT(gtask, 0, fn, q); 6129 break; 6130 default: 6131 panic("unknown net intr type"); 6132 } 6133 if (irq != NULL) { 6134 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6135 q, name); 6136 if (err) 6137 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 6138 irq->ii_res, name); 6139 } else { 6140 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 6141 } 6142 } 6143 6144 void 6145 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6146 { 6147 6148 if (irq->ii_tag) 6149 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6150 6151 if (irq->ii_res) 6152 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6153 rman_get_rid(irq->ii_res), irq->ii_res); 6154 } 6155 6156 static int 6157 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6158 { 6159 iflib_txq_t txq = ctx->ifc_txqs; 6160 iflib_rxq_t rxq = ctx->ifc_rxqs; 6161 if_irq_t irq = &ctx->ifc_legacy_irq; 6162 iflib_filter_info_t info; 6163 device_t dev; 6164 struct grouptask *gtask; 6165 struct resource *res; 6166 struct taskqgroup *tqg; 6167 void *q; 6168 int err, tqrid; 6169 bool rx_only; 6170 6171 q = &ctx->ifc_rxqs[0]; 6172 info = &rxq[0].ifr_filter_info; 6173 gtask = &rxq[0].ifr_task; 6174 tqg = qgroup_if_io_tqg; 6175 tqrid = *rid; 6176 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6177 6178 ctx->ifc_flags |= IFC_LEGACY; 6179 info->ifi_filter = filter; 6180 info->ifi_filter_arg = filter_arg; 6181 info->ifi_task = gtask; 6182 info->ifi_ctx = rx_only ? ctx : q; 6183 6184 dev = ctx->ifc_dev; 6185 /* We allocate a single interrupt resource */ 6186 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6187 iflib_fast_intr_rxtx, NULL, info, name); 6188 if (err != 0) 6189 return (err); 6190 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6191 res = irq->ii_res; 6192 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6193 6194 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6195 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6196 "tx"); 6197 return (0); 6198 } 6199 6200 void 6201 iflib_led_create(if_ctx_t ctx) 6202 { 6203 6204 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6205 device_get_nameunit(ctx->ifc_dev)); 6206 } 6207 6208 void 6209 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6210 { 6211 6212 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6213 } 6214 6215 void 6216 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6217 { 6218 6219 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6220 } 6221 6222 void 6223 iflib_admin_intr_deferred(if_ctx_t ctx) 6224 { 6225 6226 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6227 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6228 } 6229 6230 void 6231 iflib_iov_intr_deferred(if_ctx_t ctx) 6232 { 6233 6234 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6235 } 6236 6237 void 6238 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6239 { 6240 6241 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6242 name); 6243 } 6244 6245 void 6246 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6247 const char *name) 6248 { 6249 6250 GROUPTASK_INIT(gtask, 0, fn, ctx); 6251 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6252 name); 6253 } 6254 6255 void 6256 iflib_config_gtask_deinit(struct grouptask *gtask) 6257 { 6258 6259 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6260 } 6261 6262 void 6263 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6264 { 6265 if_t ifp = ctx->ifc_ifp; 6266 iflib_txq_t txq = ctx->ifc_txqs; 6267 6268 if_setbaudrate(ifp, baudrate); 6269 if (baudrate >= IF_Gbps(10)) { 6270 STATE_LOCK(ctx); 6271 ctx->ifc_flags |= IFC_PREFETCH; 6272 STATE_UNLOCK(ctx); 6273 } 6274 /* If link down, disable watchdog */ 6275 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6276 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6277 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6278 } 6279 ctx->ifc_link_state = link_state; 6280 if_link_state_change(ifp, link_state); 6281 } 6282 6283 static int 6284 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6285 { 6286 int credits; 6287 #ifdef INVARIANTS 6288 int credits_pre = txq->ift_cidx_processed; 6289 #endif 6290 6291 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6292 BUS_DMASYNC_POSTREAD); 6293 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6294 return (0); 6295 6296 txq->ift_processed += credits; 6297 txq->ift_cidx_processed += credits; 6298 6299 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6300 if (txq->ift_cidx_processed >= txq->ift_size) 6301 txq->ift_cidx_processed -= txq->ift_size; 6302 return (credits); 6303 } 6304 6305 static int 6306 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6307 { 6308 iflib_fl_t fl; 6309 u_int i; 6310 6311 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6312 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6313 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6314 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6315 budget)); 6316 } 6317 6318 void 6319 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6320 const char *description, if_int_delay_info_t info, 6321 int offset, int value) 6322 { 6323 info->iidi_ctx = ctx; 6324 info->iidi_offset = offset; 6325 info->iidi_value = value; 6326 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6327 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6328 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6329 info, 0, iflib_sysctl_int_delay, "I", description); 6330 } 6331 6332 struct sx * 6333 iflib_ctx_lock_get(if_ctx_t ctx) 6334 { 6335 6336 return (&ctx->ifc_ctx_sx); 6337 } 6338 6339 static int 6340 iflib_msix_init(if_ctx_t ctx) 6341 { 6342 device_t dev = ctx->ifc_dev; 6343 if_shared_ctx_t sctx = ctx->ifc_sctx; 6344 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6345 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6346 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6347 6348 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6349 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6350 6351 if (bootverbose) 6352 device_printf(dev, "msix_init qsets capped at %d\n", 6353 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6354 6355 /* Override by tuneable */ 6356 if (scctx->isc_disable_msix) 6357 goto msi; 6358 6359 /* First try MSI-X */ 6360 if ((msgs = pci_msix_count(dev)) == 0) { 6361 if (bootverbose) 6362 device_printf(dev, "MSI-X not supported or disabled\n"); 6363 goto msi; 6364 } 6365 6366 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6367 /* 6368 * bar == -1 => "trust me I know what I'm doing" 6369 * Some drivers are for hardware that is so shoddily 6370 * documented that no one knows which bars are which 6371 * so the developer has to map all bars. This hack 6372 * allows shoddy garbage to use MSI-X in this framework. 6373 */ 6374 if (bar != -1) { 6375 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6376 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6377 if (ctx->ifc_msix_mem == NULL) { 6378 device_printf(dev, "Unable to map MSI-X table\n"); 6379 goto msi; 6380 } 6381 } 6382 6383 admincnt = sctx->isc_admin_intrcnt; 6384 #if IFLIB_DEBUG 6385 /* use only 1 qset in debug mode */ 6386 queuemsgs = min(msgs - admincnt, 1); 6387 #else 6388 queuemsgs = msgs - admincnt; 6389 #endif 6390 #ifdef RSS 6391 queues = imin(queuemsgs, rss_getnumbuckets()); 6392 #else 6393 queues = queuemsgs; 6394 #endif 6395 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6396 if (bootverbose) 6397 device_printf(dev, 6398 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6399 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6400 #ifdef RSS 6401 /* If we're doing RSS, clamp at the number of RSS buckets */ 6402 if (queues > rss_getnumbuckets()) 6403 queues = rss_getnumbuckets(); 6404 #endif 6405 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6406 rx_queues = iflib_num_rx_queues; 6407 else 6408 rx_queues = queues; 6409 6410 if (rx_queues > scctx->isc_nrxqsets) 6411 rx_queues = scctx->isc_nrxqsets; 6412 6413 /* 6414 * We want this to be all logical CPUs by default 6415 */ 6416 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6417 tx_queues = iflib_num_tx_queues; 6418 else 6419 tx_queues = mp_ncpus; 6420 6421 if (tx_queues > scctx->isc_ntxqsets) 6422 tx_queues = scctx->isc_ntxqsets; 6423 6424 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6425 #ifdef INVARIANTS 6426 if (tx_queues != rx_queues) 6427 device_printf(dev, 6428 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6429 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6430 #endif 6431 tx_queues = min(rx_queues, tx_queues); 6432 rx_queues = min(rx_queues, tx_queues); 6433 } 6434 6435 vectors = rx_queues + admincnt; 6436 if (msgs < vectors) { 6437 device_printf(dev, 6438 "insufficient number of MSI-X vectors " 6439 "(supported %d, need %d)\n", msgs, vectors); 6440 goto msi; 6441 } 6442 6443 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6444 tx_queues); 6445 msgs = vectors; 6446 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6447 if (vectors != msgs) { 6448 device_printf(dev, 6449 "Unable to allocate sufficient MSI-X vectors " 6450 "(got %d, need %d)\n", vectors, msgs); 6451 pci_release_msi(dev); 6452 if (bar != -1) { 6453 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6454 ctx->ifc_msix_mem); 6455 ctx->ifc_msix_mem = NULL; 6456 } 6457 goto msi; 6458 } 6459 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6460 vectors); 6461 scctx->isc_vectors = vectors; 6462 scctx->isc_nrxqsets = rx_queues; 6463 scctx->isc_ntxqsets = tx_queues; 6464 scctx->isc_intr = IFLIB_INTR_MSIX; 6465 6466 return (vectors); 6467 } else { 6468 device_printf(dev, 6469 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6470 err); 6471 if (bar != -1) { 6472 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6473 ctx->ifc_msix_mem); 6474 ctx->ifc_msix_mem = NULL; 6475 } 6476 } 6477 6478 msi: 6479 vectors = pci_msi_count(dev); 6480 scctx->isc_nrxqsets = 1; 6481 scctx->isc_ntxqsets = 1; 6482 scctx->isc_vectors = vectors; 6483 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6484 device_printf(dev,"Using an MSI interrupt\n"); 6485 scctx->isc_intr = IFLIB_INTR_MSI; 6486 } else { 6487 scctx->isc_vectors = 1; 6488 device_printf(dev,"Using a Legacy interrupt\n"); 6489 scctx->isc_intr = IFLIB_INTR_LEGACY; 6490 } 6491 6492 return (vectors); 6493 } 6494 6495 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6496 6497 static int 6498 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6499 { 6500 int rc; 6501 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6502 struct sbuf *sb; 6503 const char *ring_state = "UNKNOWN"; 6504 6505 /* XXX needed ? */ 6506 rc = sysctl_wire_old_buffer(req, 0); 6507 MPASS(rc == 0); 6508 if (rc != 0) 6509 return (rc); 6510 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6511 MPASS(sb != NULL); 6512 if (sb == NULL) 6513 return (ENOMEM); 6514 if (state[3] <= 3) 6515 ring_state = ring_states[state[3]]; 6516 6517 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6518 state[0], state[1], state[2], ring_state); 6519 rc = sbuf_finish(sb); 6520 sbuf_delete(sb); 6521 return(rc); 6522 } 6523 6524 enum iflib_ndesc_handler { 6525 IFLIB_NTXD_HANDLER, 6526 IFLIB_NRXD_HANDLER, 6527 }; 6528 6529 static int 6530 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6531 { 6532 if_ctx_t ctx = (void *)arg1; 6533 enum iflib_ndesc_handler type = arg2; 6534 char buf[256] = {0}; 6535 qidx_t *ndesc; 6536 char *p, *next; 6537 int nqs, rc, i; 6538 6539 nqs = 8; 6540 switch(type) { 6541 case IFLIB_NTXD_HANDLER: 6542 ndesc = ctx->ifc_sysctl_ntxds; 6543 if (ctx->ifc_sctx) 6544 nqs = ctx->ifc_sctx->isc_ntxqs; 6545 break; 6546 case IFLIB_NRXD_HANDLER: 6547 ndesc = ctx->ifc_sysctl_nrxds; 6548 if (ctx->ifc_sctx) 6549 nqs = ctx->ifc_sctx->isc_nrxqs; 6550 break; 6551 default: 6552 printf("%s: unhandled type\n", __func__); 6553 return (EINVAL); 6554 } 6555 if (nqs == 0) 6556 nqs = 8; 6557 6558 for (i=0; i<8; i++) { 6559 if (i >= nqs) 6560 break; 6561 if (i) 6562 strcat(buf, ","); 6563 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6564 } 6565 6566 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6567 if (rc || req->newptr == NULL) 6568 return rc; 6569 6570 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6571 i++, p = strsep(&next, " ,")) { 6572 ndesc[i] = strtoul(p, NULL, 10); 6573 } 6574 6575 return(rc); 6576 } 6577 6578 #define NAME_BUFLEN 32 6579 static void 6580 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6581 { 6582 device_t dev = iflib_get_dev(ctx); 6583 struct sysctl_oid_list *child, *oid_list; 6584 struct sysctl_ctx_list *ctx_list; 6585 struct sysctl_oid *node; 6586 6587 ctx_list = device_get_sysctl_ctx(dev); 6588 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6589 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6590 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 6591 oid_list = SYSCTL_CHILDREN(node); 6592 6593 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6594 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6595 "driver version"); 6596 6597 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6598 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6599 "# of txqs to use, 0 => use default #"); 6600 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6601 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6602 "# of rxqs to use, 0 => use default #"); 6603 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6604 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6605 "permit #txq != #rxq"); 6606 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6607 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6608 "disable MSI-X (default 0)"); 6609 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6610 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6611 "set the RX budget"); 6612 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6613 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6614 "cause TX to abdicate instead of running to completion"); 6615 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6616 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6617 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6618 "offset to start using cores at"); 6619 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6620 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6621 "use separate cores for TX and RX"); 6622 6623 /* XXX change for per-queue sizes */ 6624 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6625 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6626 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6627 "list of # of TX descriptors to use, 0 = use default #"); 6628 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6629 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6630 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6631 "list of # of RX descriptors to use, 0 = use default #"); 6632 } 6633 6634 static void 6635 iflib_add_device_sysctl_post(if_ctx_t ctx) 6636 { 6637 if_shared_ctx_t sctx = ctx->ifc_sctx; 6638 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6639 device_t dev = iflib_get_dev(ctx); 6640 struct sysctl_oid_list *child; 6641 struct sysctl_ctx_list *ctx_list; 6642 iflib_fl_t fl; 6643 iflib_txq_t txq; 6644 iflib_rxq_t rxq; 6645 int i, j; 6646 char namebuf[NAME_BUFLEN]; 6647 char *qfmt; 6648 struct sysctl_oid *queue_node, *fl_node, *node; 6649 struct sysctl_oid_list *queue_list, *fl_list; 6650 ctx_list = device_get_sysctl_ctx(dev); 6651 6652 node = ctx->ifc_sysctl_node; 6653 child = SYSCTL_CHILDREN(node); 6654 6655 if (scctx->isc_ntxqsets > 100) 6656 qfmt = "txq%03d"; 6657 else if (scctx->isc_ntxqsets > 10) 6658 qfmt = "txq%02d"; 6659 else 6660 qfmt = "txq%d"; 6661 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6662 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6663 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6664 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6665 queue_list = SYSCTL_CHILDREN(queue_node); 6666 #if MEMORY_LOGGING 6667 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6668 CTLFLAG_RD, 6669 &txq->ift_dequeued, "total mbufs freed"); 6670 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6671 CTLFLAG_RD, 6672 &txq->ift_enqueued, "total mbufs enqueued"); 6673 #endif 6674 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6675 CTLFLAG_RD, 6676 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6677 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6678 CTLFLAG_RD, 6679 &txq->ift_pullups, "# of times m_pullup was called"); 6680 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6681 CTLFLAG_RD, 6682 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6683 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6684 CTLFLAG_RD, 6685 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6686 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6687 CTLFLAG_RD, 6688 &txq->ift_map_failed, "# of times DMA map failed"); 6689 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6690 CTLFLAG_RD, 6691 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6692 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6693 CTLFLAG_RD, 6694 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6695 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6696 CTLFLAG_RD, 6697 &txq->ift_pidx, 1, "Producer Index"); 6698 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6699 CTLFLAG_RD, 6700 &txq->ift_cidx, 1, "Consumer Index"); 6701 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6702 CTLFLAG_RD, 6703 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6704 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6705 CTLFLAG_RD, 6706 &txq->ift_in_use, 1, "descriptors in use"); 6707 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6708 CTLFLAG_RD, 6709 &txq->ift_processed, "descriptors procesed for clean"); 6710 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6711 CTLFLAG_RD, 6712 &txq->ift_cleaned, "total cleaned"); 6713 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6714 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6715 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6716 mp_ring_state_handler, "A", "soft ring state"); 6717 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6718 CTLFLAG_RD, &txq->ift_br->enqueues, 6719 "# of enqueues to the mp_ring for this queue"); 6720 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6721 CTLFLAG_RD, &txq->ift_br->drops, 6722 "# of drops in the mp_ring for this queue"); 6723 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6724 CTLFLAG_RD, &txq->ift_br->starts, 6725 "# of normal consumer starts in the mp_ring for this queue"); 6726 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6727 CTLFLAG_RD, &txq->ift_br->stalls, 6728 "# of consumer stalls in the mp_ring for this queue"); 6729 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6730 CTLFLAG_RD, &txq->ift_br->restarts, 6731 "# of consumer restarts in the mp_ring for this queue"); 6732 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6733 CTLFLAG_RD, &txq->ift_br->abdications, 6734 "# of consumer abdications in the mp_ring for this queue"); 6735 } 6736 6737 if (scctx->isc_nrxqsets > 100) 6738 qfmt = "rxq%03d"; 6739 else if (scctx->isc_nrxqsets > 10) 6740 qfmt = "rxq%02d"; 6741 else 6742 qfmt = "rxq%d"; 6743 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6744 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6745 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6746 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6747 queue_list = SYSCTL_CHILDREN(queue_node); 6748 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6749 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6750 CTLFLAG_RD, 6751 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6752 } 6753 6754 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6755 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6756 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6757 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 6758 fl_list = SYSCTL_CHILDREN(fl_node); 6759 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6760 CTLFLAG_RD, 6761 &fl->ifl_pidx, 1, "Producer Index"); 6762 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6763 CTLFLAG_RD, 6764 &fl->ifl_cidx, 1, "Consumer Index"); 6765 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6766 CTLFLAG_RD, 6767 &fl->ifl_credits, 1, "credits available"); 6768 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 6769 CTLFLAG_RD, 6770 &fl->ifl_buf_size, 1, "buffer size"); 6771 #if MEMORY_LOGGING 6772 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6773 CTLFLAG_RD, 6774 &fl->ifl_m_enqueued, "mbufs allocated"); 6775 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6776 CTLFLAG_RD, 6777 &fl->ifl_m_dequeued, "mbufs freed"); 6778 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6779 CTLFLAG_RD, 6780 &fl->ifl_cl_enqueued, "clusters allocated"); 6781 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6782 CTLFLAG_RD, 6783 &fl->ifl_cl_dequeued, "clusters freed"); 6784 #endif 6785 } 6786 } 6787 6788 } 6789 6790 void 6791 iflib_request_reset(if_ctx_t ctx) 6792 { 6793 6794 STATE_LOCK(ctx); 6795 ctx->ifc_flags |= IFC_DO_RESET; 6796 STATE_UNLOCK(ctx); 6797 } 6798 6799 #ifndef __NO_STRICT_ALIGNMENT 6800 static struct mbuf * 6801 iflib_fixup_rx(struct mbuf *m) 6802 { 6803 struct mbuf *n; 6804 6805 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6806 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6807 m->m_data += ETHER_HDR_LEN; 6808 n = m; 6809 } else { 6810 MGETHDR(n, M_NOWAIT, MT_DATA); 6811 if (n == NULL) { 6812 m_freem(m); 6813 return (NULL); 6814 } 6815 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6816 m->m_data += ETHER_HDR_LEN; 6817 m->m_len -= ETHER_HDR_LEN; 6818 n->m_len = ETHER_HDR_LEN; 6819 M_MOVE_PKTHDR(n, m); 6820 n->m_next = m; 6821 } 6822 return (n); 6823 } 6824 #endif 6825 6826 #ifdef DEBUGNET 6827 static void 6828 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6829 { 6830 if_ctx_t ctx; 6831 6832 ctx = if_getsoftc(ifp); 6833 CTX_LOCK(ctx); 6834 *nrxr = NRXQSETS(ctx); 6835 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6836 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6837 CTX_UNLOCK(ctx); 6838 } 6839 6840 static void 6841 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 6842 { 6843 if_ctx_t ctx; 6844 if_softc_ctx_t scctx; 6845 iflib_fl_t fl; 6846 iflib_rxq_t rxq; 6847 int i, j; 6848 6849 ctx = if_getsoftc(ifp); 6850 scctx = &ctx->ifc_softc_ctx; 6851 6852 switch (event) { 6853 case DEBUGNET_START: 6854 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6855 rxq = &ctx->ifc_rxqs[i]; 6856 for (j = 0; j < rxq->ifr_nfl; j++) { 6857 fl = rxq->ifr_fl; 6858 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6859 } 6860 } 6861 iflib_no_tx_batch = 1; 6862 break; 6863 default: 6864 break; 6865 } 6866 } 6867 6868 static int 6869 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 6870 { 6871 if_ctx_t ctx; 6872 iflib_txq_t txq; 6873 int error; 6874 6875 ctx = if_getsoftc(ifp); 6876 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6877 IFF_DRV_RUNNING) 6878 return (EBUSY); 6879 6880 txq = &ctx->ifc_txqs[0]; 6881 error = iflib_encap(txq, &m); 6882 if (error == 0) 6883 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6884 return (error); 6885 } 6886 6887 static int 6888 iflib_debugnet_poll(if_t ifp, int count) 6889 { 6890 struct epoch_tracker et; 6891 if_ctx_t ctx; 6892 if_softc_ctx_t scctx; 6893 iflib_txq_t txq; 6894 int i; 6895 6896 ctx = if_getsoftc(ifp); 6897 scctx = &ctx->ifc_softc_ctx; 6898 6899 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6900 IFF_DRV_RUNNING) 6901 return (EBUSY); 6902 6903 txq = &ctx->ifc_txqs[0]; 6904 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6905 6906 NET_EPOCH_ENTER(et); 6907 for (i = 0; i < scctx->isc_nrxqsets; i++) 6908 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6909 NET_EPOCH_EXIT(et); 6910 return (0); 6911 } 6912 #endif /* DEBUGNET */ 6913