1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include "opt_inet.h" 30 #include "opt_inet6.h" 31 #include "opt_acpi.h" 32 #include "opt_sched.h" 33 34 #include <sys/param.h> 35 #include <sys/types.h> 36 #include <sys/bus.h> 37 #include <sys/eventhandler.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/module.h> 42 #include <sys/kobj.h> 43 #include <sys/rman.h> 44 #include <sys/sbuf.h> 45 #include <sys/smp.h> 46 #include <sys/socket.h> 47 #include <sys/sockio.h> 48 #include <sys/sysctl.h> 49 #include <sys/syslog.h> 50 #include <sys/taskqueue.h> 51 #include <sys/limits.h> 52 53 #include <net/if.h> 54 #include <net/if_var.h> 55 #include <net/if_private.h> 56 #include <net/if_types.h> 57 #include <net/if_media.h> 58 #include <net/bpf.h> 59 #include <net/ethernet.h> 60 #include <net/mp_ring.h> 61 #include <net/debugnet.h> 62 #include <net/pfil.h> 63 #include <net/vnet.h> 64 65 #include <netinet/in.h> 66 #include <netinet/in_pcb.h> 67 #include <netinet/tcp_lro.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/if_ether.h> 70 #include <netinet/ip.h> 71 #include <netinet/ip6.h> 72 #include <netinet/tcp.h> 73 #include <netinet/udp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 90 #include "ifdi_if.h" 91 92 #ifdef PCI_IOV 93 #include <dev/pci/pci_iov.h> 94 #endif 95 96 #include <sys/bitstring.h> 97 /* 98 * enable accounting of every mbuf as it comes in to and goes out of 99 * iflib's software descriptor references 100 */ 101 #define MEMORY_LOGGING 0 102 /* 103 * Enable mbuf vectors for compressing long mbuf chains 104 */ 105 106 /* 107 * NB: 108 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 109 * we prefetch needs to be determined by the time spent in m_free vis a vis 110 * the cost of a prefetch. This will of course vary based on the workload: 111 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 112 * is quite expensive, thus suggesting very little prefetch. 113 * - small packet forwarding which is just returning a single mbuf to 114 * UMA will typically be very fast vis a vis the cost of a memory 115 * access. 116 */ 117 118 /* 119 * File organization: 120 * - private structures 121 * - iflib private utility functions 122 * - ifnet functions 123 * - vlan registry and other exported functions 124 * - iflib public core functions 125 * 126 * 127 */ 128 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 129 130 #define IFLIB_RXEOF_MORE (1U << 0) 131 #define IFLIB_RXEOF_EMPTY (2U << 0) 132 133 struct iflib_txq; 134 typedef struct iflib_txq *iflib_txq_t; 135 struct iflib_rxq; 136 typedef struct iflib_rxq *iflib_rxq_t; 137 struct iflib_fl; 138 typedef struct iflib_fl *iflib_fl_t; 139 140 struct iflib_ctx; 141 142 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 143 static void iflib_timer(void *arg); 144 static void iflib_tqg_detach(if_ctx_t ctx); 145 #ifndef ALTQ 146 static int iflib_simple_transmit(if_t ifp, struct mbuf *m); 147 #endif 148 149 typedef struct iflib_filter_info { 150 driver_filter_t *ifi_filter; 151 void *ifi_filter_arg; 152 struct grouptask *ifi_task; 153 void *ifi_ctx; 154 } *iflib_filter_info_t; 155 156 struct iflib_ctx { 157 KOBJ_FIELDS; 158 /* 159 * Pointer to hardware driver's softc 160 */ 161 void *ifc_softc; 162 device_t ifc_dev; 163 if_t ifc_ifp; 164 165 cpuset_t ifc_cpus; 166 if_shared_ctx_t ifc_sctx; 167 struct if_softc_ctx ifc_softc_ctx; 168 169 struct sx ifc_ctx_sx; 170 struct mtx ifc_state_mtx; 171 172 iflib_txq_t ifc_txqs; 173 iflib_rxq_t ifc_rxqs; 174 uint32_t ifc_if_flags; 175 uint32_t ifc_flags; 176 uint32_t ifc_max_fl_buf_size; 177 uint32_t ifc_rx_mbuf_sz; 178 179 int ifc_link_state; 180 int ifc_watchdog_events; 181 struct cdev *ifc_led_dev; 182 struct resource *ifc_msix_mem; 183 184 struct if_irq ifc_legacy_irq; 185 struct task ifc_admin_task; 186 struct task ifc_vflr_task; 187 struct taskqueue *ifc_tq; 188 struct iflib_filter_info ifc_filter_info; 189 struct ifmedia ifc_media; 190 struct ifmedia *ifc_mediap; 191 192 struct sysctl_oid *ifc_sysctl_node; 193 uint16_t ifc_sysctl_ntxqs; 194 uint16_t ifc_sysctl_nrxqs; 195 uint16_t ifc_sysctl_qs_eq_override; 196 uint16_t ifc_sysctl_rx_budget; 197 uint16_t ifc_sysctl_tx_abdicate; 198 uint16_t ifc_sysctl_core_offset; 199 #define CORE_OFFSET_UNSPECIFIED 0xffff 200 uint8_t ifc_sysctl_separate_txrx; 201 uint8_t ifc_sysctl_use_logical_cores; 202 uint16_t ifc_sysctl_extra_msix_vectors; 203 bool ifc_cpus_are_physical_cores; 204 bool ifc_sysctl_simple_tx; 205 uint16_t ifc_sysctl_tx_reclaim_thresh; 206 uint16_t ifc_sysctl_tx_reclaim_ticks; 207 208 qidx_t ifc_sysctl_ntxds[8]; 209 qidx_t ifc_sysctl_nrxds[8]; 210 struct if_txrx ifc_txrx; 211 #define isc_txd_encap ifc_txrx.ift_txd_encap 212 #define isc_txd_flush ifc_txrx.ift_txd_flush 213 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 214 #define isc_rxd_available ifc_txrx.ift_rxd_available 215 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 216 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 217 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 218 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 219 #define isc_txq_select ifc_txrx.ift_txq_select 220 #define isc_txq_select_v2 ifc_txrx.ift_txq_select_v2 221 222 eventhandler_tag ifc_vlan_attach_event; 223 eventhandler_tag ifc_vlan_detach_event; 224 struct ether_addr ifc_mac; 225 }; 226 227 void * 228 iflib_get_softc(if_ctx_t ctx) 229 { 230 231 return (ctx->ifc_softc); 232 } 233 234 device_t 235 iflib_get_dev(if_ctx_t ctx) 236 { 237 238 return (ctx->ifc_dev); 239 } 240 241 if_t 242 iflib_get_ifp(if_ctx_t ctx) 243 { 244 245 return (ctx->ifc_ifp); 246 } 247 248 struct ifmedia * 249 iflib_get_media(if_ctx_t ctx) 250 { 251 252 return (ctx->ifc_mediap); 253 } 254 255 void 256 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 257 { 258 259 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 260 } 261 262 if_softc_ctx_t 263 iflib_get_softc_ctx(if_ctx_t ctx) 264 { 265 266 return (&ctx->ifc_softc_ctx); 267 } 268 269 if_shared_ctx_t 270 iflib_get_sctx(if_ctx_t ctx) 271 { 272 273 return (ctx->ifc_sctx); 274 } 275 276 uint16_t 277 iflib_get_extra_msix_vectors_sysctl(if_ctx_t ctx) 278 { 279 280 return (ctx->ifc_sysctl_extra_msix_vectors); 281 } 282 283 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 284 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE / sizeof(void *)) 285 #define CACHE_PTR_NEXT(ptr) ((void *)(roundup2(ptr, CACHE_LINE_SIZE))) 286 287 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 288 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 289 290 typedef struct iflib_sw_rx_desc_array { 291 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 292 struct mbuf **ifsd_m; /* pkthdr mbufs */ 293 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 294 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 295 } iflib_rxsd_array_t; 296 297 typedef struct iflib_sw_tx_desc_array { 298 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 299 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 300 struct mbuf **ifsd_m; /* pkthdr mbufs */ 301 } if_txsd_vec_t; 302 303 /* magic number that should be high enough for any hardware */ 304 #define IFLIB_MAX_TX_SEGS 128 305 #define IFLIB_RX_COPY_THRESH 128 306 #define IFLIB_MAX_RX_REFRESH 32 307 /* The minimum descriptors per second before we start coalescing */ 308 #define IFLIB_MIN_DESC_SEC 16384 309 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 310 #define IFLIB_QUEUE_IDLE 0 311 #define IFLIB_QUEUE_HUNG 1 312 #define IFLIB_QUEUE_WORKING 2 313 /* maximum number of txqs that can share an rx interrupt */ 314 #define IFLIB_MAX_TX_SHARED_INTR 4 315 316 /* this should really scale with ring size - this is a fairly arbitrary value */ 317 #define TX_BATCH_SIZE 32 318 319 #define IFLIB_RESTART_BUDGET 8 320 321 #define IFC_LEGACY 0x001 322 #define IFC_QFLUSH 0x002 323 #define IFC_MULTISEG 0x004 324 #define IFC_SPARE1 0x008 325 #define IFC_SC_ALLOCATED 0x010 326 #define IFC_INIT_DONE 0x020 327 #define IFC_PREFETCH 0x040 328 #define IFC_DO_RESET 0x080 329 #define IFC_DO_WATCHDOG 0x100 330 #define IFC_SPARE0 0x200 331 #define IFC_SPARE2 0x400 332 #define IFC_IN_DETACH 0x800 333 334 #define IFC_NETMAP_TX_IRQ 0x80000000 335 336 #define CSUM_OFFLOAD (CSUM_IP_TSO | CSUM_IP6_TSO | CSUM_IP | \ 337 CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_SCTP | \ 338 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_SCTP) 339 340 struct iflib_txq { 341 qidx_t ift_in_use; 342 qidx_t ift_cidx; 343 qidx_t ift_cidx_processed; 344 qidx_t ift_pidx; 345 uint8_t ift_gen; 346 uint8_t ift_br_offset; 347 uint16_t ift_npending; 348 uint16_t ift_db_pending; 349 uint16_t ift_rs_pending; 350 uint32_t ift_last_reclaim; 351 uint16_t ift_reclaim_thresh; 352 uint16_t ift_reclaim_ticks; 353 uint8_t ift_txd_size[8]; 354 uint64_t ift_processed; 355 uint64_t ift_cleaned; 356 uint64_t ift_cleaned_prev; 357 #if MEMORY_LOGGING 358 uint64_t ift_enqueued; 359 uint64_t ift_dequeued; 360 #endif 361 uint64_t ift_no_tx_dma_setup; 362 uint64_t ift_no_desc_avail; 363 uint64_t ift_mbuf_defrag_failed; 364 uint64_t ift_mbuf_defrag; 365 uint64_t ift_map_failed; 366 uint64_t ift_txd_encap_efbig; 367 uint64_t ift_pullups; 368 uint64_t ift_last_timer_tick; 369 370 struct mtx ift_mtx; 371 struct mtx ift_db_mtx; 372 373 /* constant values */ 374 if_ctx_t ift_ctx; 375 struct ifmp_ring *ift_br; 376 struct grouptask ift_task; 377 qidx_t ift_size; 378 qidx_t ift_pad; 379 uint16_t ift_id; 380 struct callout ift_timer; 381 #ifdef DEV_NETMAP 382 struct callout ift_netmap_timer; 383 #endif /* DEV_NETMAP */ 384 385 if_txsd_vec_t ift_sds; 386 uint8_t ift_qstatus; 387 uint8_t ift_closed; 388 uint8_t ift_update_freq; 389 struct iflib_filter_info ift_filter_info; 390 bus_dma_tag_t ift_buf_tag; 391 bus_dma_tag_t ift_tso_buf_tag; 392 iflib_dma_info_t ift_ifdi; 393 #define MTX_NAME_LEN 32 394 char ift_mtx_name[MTX_NAME_LEN]; 395 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 396 #ifdef IFLIB_DIAGNOSTICS 397 uint64_t ift_cpu_exec_count[256]; 398 #endif 399 } __aligned(CACHE_LINE_SIZE); 400 401 struct iflib_fl { 402 qidx_t ifl_cidx; 403 qidx_t ifl_pidx; 404 qidx_t ifl_credits; 405 uint8_t ifl_gen; 406 uint8_t ifl_rxd_size; 407 #if MEMORY_LOGGING 408 uint64_t ifl_m_enqueued; 409 uint64_t ifl_m_dequeued; 410 uint64_t ifl_cl_enqueued; 411 uint64_t ifl_cl_dequeued; 412 #endif 413 /* implicit pad */ 414 bitstr_t *ifl_rx_bitmap; 415 qidx_t ifl_fragidx; 416 /* constant */ 417 qidx_t ifl_size; 418 uint16_t ifl_buf_size; 419 uint16_t ifl_cltype; 420 uma_zone_t ifl_zone; 421 iflib_rxsd_array_t ifl_sds; 422 iflib_rxq_t ifl_rxq; 423 uint8_t ifl_id; 424 bus_dma_tag_t ifl_buf_tag; 425 iflib_dma_info_t ifl_ifdi; 426 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 427 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 428 } __aligned(CACHE_LINE_SIZE); 429 430 static inline qidx_t 431 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 432 { 433 qidx_t used; 434 435 if (pidx > cidx) 436 used = pidx - cidx; 437 else if (pidx < cidx) 438 used = size - cidx + pidx; 439 else if (gen == 0 && pidx == cidx) 440 used = 0; 441 else if (gen == 1 && pidx == cidx) 442 used = size; 443 else 444 panic("bad state"); 445 446 return (used); 447 } 448 449 #define TXQ_AVAIL(txq) ((txq->ift_size - txq->ift_pad) -\ 450 get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 451 452 #define IDXDIFF(head, tail, wrap) \ 453 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 454 455 struct iflib_rxq { 456 if_ctx_t ifr_ctx; 457 iflib_fl_t ifr_fl; 458 uint64_t ifr_rx_irq; 459 struct pfil_head *pfil; 460 /* 461 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 462 * the completion queue consumer index. Otherwise it's unused. 463 */ 464 qidx_t ifr_cq_cidx; 465 uint16_t ifr_id; 466 uint8_t ifr_nfl; 467 uint8_t ifr_ntxqirq; 468 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 469 uint8_t ifr_fl_offset; 470 struct lro_ctrl ifr_lc; 471 struct grouptask ifr_task; 472 struct callout ifr_watchdog; 473 struct iflib_filter_info ifr_filter_info; 474 iflib_dma_info_t ifr_ifdi; 475 476 /* dynamically allocate if any drivers need a value substantially larger than this */ 477 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 478 #ifdef IFLIB_DIAGNOSTICS 479 uint64_t ifr_cpu_exec_count[256]; 480 #endif 481 } __aligned(CACHE_LINE_SIZE); 482 483 typedef struct if_rxsd { 484 caddr_t *ifsd_cl; 485 iflib_fl_t ifsd_fl; 486 } *if_rxsd_t; 487 488 /* multiple of word size */ 489 #ifdef __LP64__ 490 #define PKT_INFO_SIZE 7 491 #define RXD_INFO_SIZE 5 492 #define PKT_TYPE uint64_t 493 #else 494 #define PKT_INFO_SIZE 12 495 #define RXD_INFO_SIZE 8 496 #define PKT_TYPE uint32_t 497 #endif 498 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE / 3) * 3) 499 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE / 4) * 4) 500 501 typedef struct if_pkt_info_pad { 502 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 503 } *if_pkt_info_pad_t; 504 typedef struct if_rxd_info_pad { 505 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 506 } *if_rxd_info_pad_t; 507 508 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 509 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 510 511 static inline void 512 pkt_info_zero(if_pkt_info_t pi) 513 { 514 if_pkt_info_pad_t pi_pad; 515 516 pi_pad = (if_pkt_info_pad_t)pi; 517 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 518 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 519 #ifndef __LP64__ 520 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 521 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 522 #endif 523 } 524 525 static inline void 526 rxd_info_zero(if_rxd_info_t ri) 527 { 528 if_rxd_info_pad_t ri_pad; 529 int i; 530 531 ri_pad = (if_rxd_info_pad_t)ri; 532 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 533 ri_pad->rxd_val[i] = 0; 534 ri_pad->rxd_val[i + 1] = 0; 535 ri_pad->rxd_val[i + 2] = 0; 536 ri_pad->rxd_val[i + 3] = 0; 537 } 538 #ifdef __LP64__ 539 ri_pad->rxd_val[RXD_INFO_SIZE - 1] = 0; 540 #endif 541 } 542 543 /* 544 * Only allow a single packet to take up most 1/nth of the tx ring 545 */ 546 #define MAX_SINGLE_PACKET_FRACTION 12 547 #define IF_BAD_DMA ((bus_addr_t)-1) 548 549 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 550 551 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 552 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 553 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 554 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 555 556 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 557 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 558 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 559 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 560 561 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 562 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 563 564 /* Our boot-time initialization hook */ 565 static int iflib_module_event_handler(module_t, int, void *); 566 567 static moduledata_t iflib_moduledata = { 568 "iflib", 569 iflib_module_event_handler, 570 NULL 571 }; 572 573 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 574 MODULE_VERSION(iflib, 1); 575 576 MODULE_DEPEND(iflib, pci, 1, 1, 1); 577 MODULE_DEPEND(iflib, ether, 1, 1, 1); 578 579 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 580 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 581 582 #ifndef IFLIB_DEBUG_COUNTERS 583 #ifdef INVARIANTS 584 #define IFLIB_DEBUG_COUNTERS 1 585 #else 586 #define IFLIB_DEBUG_COUNTERS 0 587 #endif /* !INVARIANTS */ 588 #endif 589 590 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 591 "iflib driver parameters"); 592 593 /* 594 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 595 */ 596 static int iflib_min_tx_latency = 0; 597 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 598 &iflib_min_tx_latency, 0, 599 "minimize transmit latency at the possible expense of throughput"); 600 static int iflib_no_tx_batch = 0; 601 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 602 &iflib_no_tx_batch, 0, 603 "minimize transmit latency at the possible expense of throughput"); 604 static int iflib_timer_default = 1000; 605 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW, 606 &iflib_timer_default, 0, "number of ticks between iflib_timer calls"); 607 608 609 #if IFLIB_DEBUG_COUNTERS 610 611 static int iflib_tx_seen; 612 static int iflib_tx_sent; 613 static int iflib_tx_encap; 614 static int iflib_rx_allocs; 615 static int iflib_fl_refills; 616 static int iflib_fl_refills_large; 617 static int iflib_tx_frees; 618 619 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, &iflib_tx_seen, 0, 620 "# TX mbufs seen"); 621 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, &iflib_tx_sent, 0, 622 "# TX mbufs sent"); 623 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, &iflib_tx_encap, 0, 624 "# TX mbufs encapped"); 625 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, &iflib_tx_frees, 0, 626 "# TX frees"); 627 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, &iflib_rx_allocs, 0, 628 "# RX allocations"); 629 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, &iflib_fl_refills, 0, 630 "# refills"); 631 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 632 &iflib_fl_refills_large, 0, "# large refills"); 633 634 static int iflib_txq_drain_flushing; 635 static int iflib_txq_drain_oactive; 636 static int iflib_txq_drain_notready; 637 638 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 639 &iflib_txq_drain_flushing, 0, "# drain flushes"); 640 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 641 &iflib_txq_drain_oactive, 0, "# drain oactives"); 642 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 643 &iflib_txq_drain_notready, 0, "# drain notready"); 644 645 static int iflib_encap_load_mbuf_fail; 646 static int iflib_encap_pad_mbuf_fail; 647 static int iflib_encap_txq_avail_fail; 648 static int iflib_encap_txd_encap_fail; 649 650 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 651 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 652 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 653 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 654 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 655 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 656 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 657 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 658 659 static int iflib_task_fn_rxs; 660 static int iflib_rx_intr_enables; 661 static int iflib_fast_intrs; 662 static int iflib_rx_unavail; 663 static int iflib_rx_ctx_inactive; 664 static int iflib_rx_if_input; 665 static int iflib_rxd_flush; 666 667 static int iflib_verbose_debug; 668 669 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, &iflib_task_fn_rxs, 0, 670 "# task_fn_rx calls"); 671 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 672 &iflib_rx_intr_enables, 0, "# RX intr enables"); 673 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, &iflib_fast_intrs, 0, 674 "# fast_intr calls"); 675 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, &iflib_rx_unavail, 0, 676 "# times rxeof called with no available data"); 677 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 678 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 679 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, &iflib_rx_if_input, 680 0, "# times rxeof called if_input"); 681 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, &iflib_rxd_flush, 0, 682 "# times rxd_flush called"); 683 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 684 &iflib_verbose_debug, 0, "enable verbose debugging"); 685 686 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 687 static void 688 iflib_debug_reset(void) 689 { 690 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 691 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 692 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 693 iflib_txq_drain_notready = 694 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 695 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 696 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 697 iflib_rx_unavail = 698 iflib_rx_ctx_inactive = iflib_rx_if_input = 699 iflib_rxd_flush = 0; 700 } 701 702 #else 703 #define DBG_COUNTER_INC(name) 704 static void iflib_debug_reset(void) {} 705 #endif 706 707 #define IFLIB_DEBUG 0 708 709 static void iflib_tx_structures_free(if_ctx_t ctx); 710 static void iflib_rx_structures_free(if_ctx_t ctx); 711 static int iflib_queues_alloc(if_ctx_t ctx); 712 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 713 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 714 static int iflib_qset_structures_setup(if_ctx_t ctx); 715 static int iflib_msix_init(if_ctx_t ctx); 716 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 717 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 718 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 719 #ifdef ALTQ 720 static void iflib_altq_if_start(if_t ifp); 721 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 722 #endif 723 static void iflib_register(if_ctx_t); 724 static void iflib_deregister(if_ctx_t); 725 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 726 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 727 static void iflib_init_locked(if_ctx_t ctx); 728 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 729 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 730 static void iflib_ifmp_purge(iflib_txq_t txq); 731 static void _iflib_pre_assert(if_softc_ctx_t scctx); 732 static void iflib_stop(if_ctx_t ctx); 733 static void iflib_if_init_locked(if_ctx_t ctx); 734 static void iflib_free_intr_mem(if_ctx_t ctx); 735 #ifndef __NO_STRICT_ALIGNMENT 736 static struct mbuf *iflib_fixup_rx(struct mbuf *m); 737 #endif 738 static __inline int iflib_completed_tx_reclaim(iflib_txq_t txq); 739 740 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 741 SLIST_HEAD_INITIALIZER(cpu_offsets); 742 struct cpu_offset { 743 SLIST_ENTRY(cpu_offset) entries; 744 cpuset_t set; 745 unsigned int refcount; 746 uint16_t next_cpuid; 747 }; 748 static struct mtx cpu_offset_mtx; 749 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 750 MTX_DEF); 751 752 DEBUGNET_DEFINE(iflib); 753 754 static int 755 iflib_num_rx_descs(if_ctx_t ctx) 756 { 757 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 758 if_shared_ctx_t sctx = ctx->ifc_sctx; 759 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 760 761 return (scctx->isc_nrxd[first_rxq]); 762 } 763 764 static int 765 iflib_num_tx_descs(if_ctx_t ctx) 766 { 767 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 768 if_shared_ctx_t sctx = ctx->ifc_sctx; 769 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 770 771 return (scctx->isc_ntxd[first_txq]); 772 } 773 774 #ifdef DEV_NETMAP 775 #include <sys/selinfo.h> 776 #include <net/netmap.h> 777 #include <dev/netmap/netmap_kern.h> 778 779 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 780 781 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 782 static void iflib_netmap_timer(void *arg); 783 784 /* 785 * device-specific sysctl variables: 786 * 787 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 788 * During regular operations the CRC is stripped, but on some 789 * hardware reception of frames not multiple of 64 is slower, 790 * so using crcstrip=0 helps in benchmarks. 791 * 792 * iflib_rx_miss, iflib_rx_miss_bufs: 793 * count packets that might be missed due to lost interrupts. 794 */ 795 SYSCTL_DECL(_dev_netmap); 796 /* 797 * The xl driver by default strips CRCs and we do not override it. 798 */ 799 800 int iflib_crcstrip = 1; 801 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 802 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 803 804 int iflib_rx_miss, iflib_rx_miss_bufs; 805 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 806 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 807 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 808 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 809 810 /* 811 * Register/unregister. We are already under netmap lock. 812 * Only called on the first register or the last unregister. 813 */ 814 static int 815 iflib_netmap_register(struct netmap_adapter *na, int onoff) 816 { 817 if_t ifp = na->ifp; 818 if_ctx_t ctx = if_getsoftc(ifp); 819 int status; 820 821 CTX_LOCK(ctx); 822 if (!CTX_IS_VF(ctx)) 823 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 824 825 iflib_stop(ctx); 826 827 /* 828 * Enable (or disable) netmap flags, and intercept (or restore) 829 * ifp->if_transmit. This is done once the device has been stopped 830 * to prevent race conditions. Also, this must be done after 831 * calling netmap_disable_all_rings() and before calling 832 * netmap_enable_all_rings(), so that these two functions see the 833 * updated state of the NAF_NETMAP_ON bit. 834 */ 835 if (onoff) { 836 nm_set_native_flags(na); 837 } else { 838 nm_clear_native_flags(na); 839 } 840 841 iflib_init_locked(ctx); 842 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 843 status = if_getdrvflags(ifp) & IFF_DRV_RUNNING ? 0 : 1; 844 if (status) 845 nm_clear_native_flags(na); 846 CTX_UNLOCK(ctx); 847 return (status); 848 } 849 850 static int 851 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info) 852 { 853 if_t ifp = na->ifp; 854 if_ctx_t ctx = if_getsoftc(ifp); 855 iflib_rxq_t rxq = &ctx->ifc_rxqs[0]; 856 iflib_fl_t fl = &rxq->ifr_fl[0]; 857 858 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 859 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 860 info->num_tx_descs = iflib_num_tx_descs(ctx); 861 info->num_rx_descs = iflib_num_rx_descs(ctx); 862 info->rx_buf_maxsize = fl->ifl_buf_size; 863 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u", 864 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs, 865 info->num_rx_descs, info->rx_buf_maxsize); 866 867 return (0); 868 } 869 870 static int 871 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 872 { 873 struct netmap_adapter *na = kring->na; 874 u_int const lim = kring->nkr_num_slots - 1; 875 struct netmap_ring *ring = kring->ring; 876 bus_dmamap_t *map; 877 struct if_rxd_update iru; 878 if_ctx_t ctx = rxq->ifr_ctx; 879 iflib_fl_t fl = &rxq->ifr_fl[0]; 880 u_int nic_i_first, nic_i; 881 u_int nm_i; 882 int i, n; 883 #if IFLIB_DEBUG_COUNTERS 884 int rf_count = 0; 885 #endif 886 887 /* 888 * This function is used both at initialization and in rxsync. 889 * At initialization we need to prepare (with isc_rxd_refill()) 890 * all the netmap buffers currently owned by the kernel, in 891 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync 892 * (except for kring->nkr_hwofs). These may be less than 893 * kring->nkr_num_slots if netmap_reset() was called while 894 * an application using the kring that still owned some 895 * buffers. 896 * At rxsync time, both indexes point to the next buffer to be 897 * refilled. 898 * In any case we publish (with isc_rxd_flush()) up to 899 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 900 * pointer to overrun the head/cons pointer, although this is 901 * not necessary for some NICs (e.g. vmx). 902 */ 903 if (__predict_false(init)) { 904 n = kring->nkr_num_slots - nm_kr_rxspace(kring); 905 } else { 906 n = kring->rhead - kring->nr_hwcur; 907 if (n == 0) 908 return (0); /* Nothing to do. */ 909 if (n < 0) 910 n += kring->nkr_num_slots; 911 } 912 913 iru_init(&iru, rxq, 0 /* flid */); 914 map = fl->ifl_sds.ifsd_map; 915 nic_i = fl->ifl_pidx; 916 nm_i = netmap_idx_n2k(kring, nic_i); 917 if (__predict_false(init)) { 918 /* 919 * On init/reset, nic_i must be 0, and we must 920 * start to refill from hwtail (see netmap_reset()). 921 */ 922 MPASS(nic_i == 0); 923 MPASS(nm_i == kring->nr_hwtail); 924 } else 925 MPASS(nm_i == kring->nr_hwcur); 926 DBG_COUNTER_INC(fl_refills); 927 while (n > 0) { 928 #if IFLIB_DEBUG_COUNTERS 929 if (++rf_count == 9) 930 DBG_COUNTER_INC(fl_refills_large); 931 #endif 932 nic_i_first = nic_i; 933 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 934 struct netmap_slot *slot = &ring->slot[nm_i]; 935 uint64_t paddr; 936 void *addr = PNMB(na, slot, &paddr); 937 938 MPASS(i < IFLIB_MAX_RX_REFRESH); 939 940 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 941 return (netmap_ring_reinit(kring)); 942 943 fl->ifl_bus_addrs[i] = paddr + 944 nm_get_offset(kring, slot); 945 fl->ifl_rxd_idxs[i] = nic_i; 946 947 if (__predict_false(init)) { 948 netmap_load_map(na, fl->ifl_buf_tag, 949 map[nic_i], addr); 950 } else if (slot->flags & NS_BUF_CHANGED) { 951 /* buffer has changed, reload map */ 952 netmap_reload_map(na, fl->ifl_buf_tag, 953 map[nic_i], addr); 954 } 955 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 956 BUS_DMASYNC_PREREAD); 957 slot->flags &= ~NS_BUF_CHANGED; 958 959 nm_i = nm_next(nm_i, lim); 960 nic_i = nm_next(nic_i, lim); 961 } 962 963 iru.iru_pidx = nic_i_first; 964 iru.iru_count = i; 965 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 966 } 967 fl->ifl_pidx = nic_i; 968 /* 969 * At the end of the loop we must have refilled everything 970 * we could possibly refill. 971 */ 972 MPASS(nm_i == kring->rhead); 973 kring->nr_hwcur = nm_i; 974 975 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 976 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 977 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 978 nm_prev(nic_i, lim)); 979 DBG_COUNTER_INC(rxd_flush); 980 981 return (0); 982 } 983 984 #define NETMAP_TX_TIMER_US 90 985 986 /* 987 * Reconcile kernel and user view of the transmit ring. 988 * 989 * All information is in the kring. 990 * Userspace wants to send packets up to the one before kring->rhead, 991 * kernel knows kring->nr_hwcur is the first unsent packet. 992 * 993 * Here we push packets out (as many as possible), and possibly 994 * reclaim buffers from previously completed transmission. 995 * 996 * The caller (netmap) guarantees that there is only one instance 997 * running at any time. Any interference with other driver 998 * methods should be handled by the individual drivers. 999 */ 1000 static int 1001 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 1002 { 1003 struct netmap_adapter *na = kring->na; 1004 if_t ifp = na->ifp; 1005 struct netmap_ring *ring = kring->ring; 1006 u_int nm_i; /* index into the netmap kring */ 1007 u_int nic_i; /* index into the NIC ring */ 1008 u_int const lim = kring->nkr_num_slots - 1; 1009 u_int const head = kring->rhead; 1010 struct if_pkt_info pi; 1011 int tx_pkts = 0, tx_bytes = 0; 1012 1013 /* 1014 * interrupts on every tx packet are expensive so request 1015 * them every half ring, or where NS_REPORT is set 1016 */ 1017 u_int report_frequency = kring->nkr_num_slots >> 1; 1018 /* device-specific */ 1019 if_ctx_t ctx = if_getsoftc(ifp); 1020 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 1021 1022 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1023 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1024 1025 /* 1026 * First part: process new packets to send. 1027 * nm_i is the current index in the netmap kring, 1028 * nic_i is the corresponding index in the NIC ring. 1029 * 1030 * If we have packets to send (nm_i != head) 1031 * iterate over the netmap ring, fetch length and update 1032 * the corresponding slot in the NIC ring. Some drivers also 1033 * need to update the buffer's physical address in the NIC slot 1034 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 1035 * 1036 * The netmap_reload_map() calls is especially expensive, 1037 * even when (as in this case) the tag is 0, so do only 1038 * when the buffer has actually changed. 1039 * 1040 * If possible do not set the report/intr bit on all slots, 1041 * but only a few times per ring or when NS_REPORT is set. 1042 * 1043 * Finally, on 10G and faster drivers, it might be useful 1044 * to prefetch the next slot and txr entry. 1045 */ 1046 1047 nm_i = kring->nr_hwcur; 1048 if (nm_i != head) { /* we have new packets to send */ 1049 uint32_t pkt_len = 0, seg_idx = 0; 1050 int nic_i_start = -1, flags = 0; 1051 pkt_info_zero(&pi); 1052 pi.ipi_segs = txq->ift_segs; 1053 pi.ipi_qsidx = kring->ring_id; 1054 nic_i = netmap_idx_k2n(kring, nm_i); 1055 1056 __builtin_prefetch(&ring->slot[nm_i]); 1057 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 1058 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 1059 1060 while (nm_i != head) { 1061 struct netmap_slot *slot = &ring->slot[nm_i]; 1062 uint64_t offset = nm_get_offset(kring, slot); 1063 u_int len = slot->len; 1064 uint64_t paddr; 1065 void *addr = PNMB(na, slot, &paddr); 1066 1067 flags |= (slot->flags & NS_REPORT || 1068 nic_i == 0 || nic_i == report_frequency) ? 1069 IPI_TX_INTR : 0; 1070 1071 /* 1072 * If this is the first packet fragment, save the 1073 * index of the first NIC slot for later. 1074 */ 1075 if (nic_i_start < 0) 1076 nic_i_start = nic_i; 1077 1078 pi.ipi_segs[seg_idx].ds_addr = paddr + offset; 1079 pi.ipi_segs[seg_idx].ds_len = len; 1080 if (len) { 1081 pkt_len += len; 1082 seg_idx++; 1083 } 1084 1085 if (!(slot->flags & NS_MOREFRAG)) { 1086 pi.ipi_len = pkt_len; 1087 pi.ipi_nsegs = seg_idx; 1088 pi.ipi_pidx = nic_i_start; 1089 pi.ipi_ndescs = 0; 1090 pi.ipi_flags = flags; 1091 1092 /* Prepare the NIC TX ring. */ 1093 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1094 DBG_COUNTER_INC(tx_encap); 1095 1096 /* Update transmit counters */ 1097 tx_bytes += pi.ipi_len; 1098 tx_pkts++; 1099 1100 /* Reinit per-packet info for the next one. */ 1101 flags = seg_idx = pkt_len = 0; 1102 nic_i_start = -1; 1103 } 1104 1105 /* prefetch for next round */ 1106 __builtin_prefetch(&ring->slot[nm_i + 1]); 1107 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1108 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1109 1110 NM_CHECK_ADDR_LEN_OFF(na, len, offset); 1111 1112 if (slot->flags & NS_BUF_CHANGED) { 1113 /* buffer has changed, reload map */ 1114 netmap_reload_map(na, txq->ift_buf_tag, 1115 txq->ift_sds.ifsd_map[nic_i], addr); 1116 } 1117 /* make sure changes to the buffer are synced */ 1118 bus_dmamap_sync(txq->ift_buf_tag, 1119 txq->ift_sds.ifsd_map[nic_i], 1120 BUS_DMASYNC_PREWRITE); 1121 1122 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG); 1123 nm_i = nm_next(nm_i, lim); 1124 nic_i = nm_next(nic_i, lim); 1125 } 1126 kring->nr_hwcur = nm_i; 1127 1128 /* synchronize the NIC ring */ 1129 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1130 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1131 1132 /* (re)start the tx unit up to slot nic_i (excluded) */ 1133 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1134 } 1135 1136 /* 1137 * Second part: reclaim buffers for completed transmissions. 1138 * 1139 * If there are unclaimed buffers, attempt to reclaim them. 1140 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1141 * trigger a per-tx-queue timer to try again later. 1142 */ 1143 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1144 if (iflib_tx_credits_update(ctx, txq)) { 1145 /* some tx completed, increment avail */ 1146 nic_i = txq->ift_cidx_processed; 1147 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1148 } 1149 } 1150 1151 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1152 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1153 callout_reset_sbt_on(&txq->ift_netmap_timer, 1154 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1155 iflib_netmap_timer, txq, 1156 txq->ift_netmap_timer.c_cpu, 0); 1157 } 1158 1159 if_inc_counter(ifp, IFCOUNTER_OBYTES, tx_bytes); 1160 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tx_pkts); 1161 1162 return (0); 1163 } 1164 1165 /* 1166 * Reconcile kernel and user view of the receive ring. 1167 * Same as for the txsync, this routine must be efficient. 1168 * The caller guarantees a single invocations, but races against 1169 * the rest of the driver should be handled here. 1170 * 1171 * On call, kring->rhead is the first packet that userspace wants 1172 * to keep, and kring->rcur is the wakeup point. 1173 * The kernel has previously reported packets up to kring->rtail. 1174 * 1175 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1176 * of whether or not we received an interrupt. 1177 */ 1178 static int 1179 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1180 { 1181 struct netmap_adapter *na = kring->na; 1182 struct netmap_ring *ring = kring->ring; 1183 if_t ifp = na->ifp; 1184 uint32_t nm_i; /* index into the netmap ring */ 1185 uint32_t nic_i; /* index into the NIC ring */ 1186 u_int n; 1187 u_int const lim = kring->nkr_num_slots - 1; 1188 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1189 int i = 0, rx_bytes = 0, rx_pkts = 0; 1190 1191 if_ctx_t ctx = if_getsoftc(ifp); 1192 if_shared_ctx_t sctx = ctx->ifc_sctx; 1193 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1194 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1195 iflib_fl_t fl = &rxq->ifr_fl[0]; 1196 struct if_rxd_info ri; 1197 qidx_t *cidxp; 1198 1199 /* 1200 * netmap only uses free list 0, to avoid out of order consumption 1201 * of receive buffers 1202 */ 1203 1204 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1205 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1206 1207 /* 1208 * First part: import newly received packets. 1209 * 1210 * nm_i is the index of the next free slot in the netmap ring, 1211 * nic_i is the index of the next received packet in the NIC ring 1212 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1213 * differ in case if_init() has been called while 1214 * in netmap mode. For the receive ring we have 1215 * 1216 * nic_i = fl->ifl_cidx; 1217 * nm_i = kring->nr_hwtail (previous) 1218 * and 1219 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1220 * 1221 * fl->ifl_cidx is set to 0 on a ring reinit 1222 */ 1223 if (netmap_no_pendintr || force_update) { 1224 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1225 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1226 int crclen = iflib_crcstrip ? 0 : 4; 1227 int error, avail; 1228 1229 /* 1230 * For the free list consumer index, we use the same 1231 * logic as in iflib_rxeof(). 1232 */ 1233 if (have_rxcq) 1234 cidxp = &rxq->ifr_cq_cidx; 1235 else 1236 cidxp = &fl->ifl_cidx; 1237 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1238 rxq->ifr_id, *cidxp, USHRT_MAX); 1239 1240 nic_i = fl->ifl_cidx; 1241 nm_i = netmap_idx_n2k(kring, nic_i); 1242 MPASS(nm_i == kring->nr_hwtail); 1243 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1244 rxd_info_zero(&ri); 1245 ri.iri_frags = rxq->ifr_frags; 1246 ri.iri_qsidx = kring->ring_id; 1247 ri.iri_ifp = ctx->ifc_ifp; 1248 ri.iri_cidx = *cidxp; 1249 1250 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1251 for (i = 0; i < ri.iri_nfrags; i++) { 1252 if (error) { 1253 ring->slot[nm_i].len = 0; 1254 ring->slot[nm_i].flags = 0; 1255 } else { 1256 ring->slot[nm_i].len = ri.iri_frags[i].irf_len; 1257 if (i == (ri.iri_nfrags - 1)) { 1258 ring->slot[nm_i].len -= crclen; 1259 ring->slot[nm_i].flags = 0; 1260 1261 /* Update receive counters */ 1262 rx_bytes += ri.iri_len; 1263 rx_pkts++; 1264 } else 1265 ring->slot[nm_i].flags = NS_MOREFRAG; 1266 } 1267 1268 bus_dmamap_sync(fl->ifl_buf_tag, 1269 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1270 nm_i = nm_next(nm_i, lim); 1271 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1272 } 1273 1274 if (have_rxcq) { 1275 *cidxp = ri.iri_cidx; 1276 while (*cidxp >= scctx->isc_nrxd[0]) 1277 *cidxp -= scctx->isc_nrxd[0]; 1278 } 1279 1280 } 1281 if (n) { /* update the state variables */ 1282 if (netmap_no_pendintr && !force_update) { 1283 /* diagnostics */ 1284 iflib_rx_miss++; 1285 iflib_rx_miss_bufs += n; 1286 } 1287 kring->nr_hwtail = nm_i; 1288 } 1289 kring->nr_kflags &= ~NKR_PENDINTR; 1290 } 1291 /* 1292 * Second part: skip past packets that userspace has released. 1293 * (kring->nr_hwcur to head excluded), 1294 * and make the buffers available for reception. 1295 * As usual nm_i is the index in the netmap ring, 1296 * nic_i is the index in the NIC ring, and 1297 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1298 */ 1299 netmap_fl_refill(rxq, kring, false); 1300 1301 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 1302 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 1303 1304 return (0); 1305 } 1306 1307 static void 1308 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1309 { 1310 if_ctx_t ctx = if_getsoftc(na->ifp); 1311 1312 CTX_LOCK(ctx); 1313 if (onoff) { 1314 IFDI_INTR_ENABLE(ctx); 1315 } else { 1316 IFDI_INTR_DISABLE(ctx); 1317 } 1318 CTX_UNLOCK(ctx); 1319 } 1320 1321 static int 1322 iflib_netmap_attach(if_ctx_t ctx) 1323 { 1324 struct netmap_adapter na; 1325 1326 bzero(&na, sizeof(na)); 1327 1328 na.ifp = ctx->ifc_ifp; 1329 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS; 1330 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1331 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1332 1333 na.num_tx_desc = iflib_num_tx_descs(ctx); 1334 na.num_rx_desc = iflib_num_rx_descs(ctx); 1335 na.nm_txsync = iflib_netmap_txsync; 1336 na.nm_rxsync = iflib_netmap_rxsync; 1337 na.nm_register = iflib_netmap_register; 1338 na.nm_intr = iflib_netmap_intr; 1339 na.nm_config = iflib_netmap_config; 1340 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1341 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1342 return (netmap_attach(&na)); 1343 } 1344 1345 static int 1346 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1347 { 1348 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1349 struct netmap_slot *slot; 1350 1351 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1352 if (slot == NULL) 1353 return (0); 1354 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1355 /* 1356 * In netmap mode, set the map for the packet buffer. 1357 * NOTE: Some drivers (not this one) also need to set 1358 * the physical buffer address in the NIC ring. 1359 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1360 * netmap slot index, si 1361 */ 1362 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1363 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1364 NMB(na, slot + si)); 1365 } 1366 return (1); 1367 } 1368 1369 static int 1370 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1371 { 1372 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1373 struct netmap_kring *kring; 1374 struct netmap_slot *slot; 1375 1376 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1377 if (slot == NULL) 1378 return (0); 1379 kring = na->rx_rings[rxq->ifr_id]; 1380 netmap_fl_refill(rxq, kring, true); 1381 return (1); 1382 } 1383 1384 static void 1385 iflib_netmap_timer(void *arg) 1386 { 1387 iflib_txq_t txq = arg; 1388 if_ctx_t ctx = txq->ift_ctx; 1389 1390 /* 1391 * Wake up the netmap application, to give it a chance to 1392 * call txsync and reclaim more completed TX buffers. 1393 */ 1394 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1395 } 1396 1397 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1398 1399 #else 1400 #define iflib_netmap_txq_init(ctx, txq) (0) 1401 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1402 #define iflib_netmap_detach(ifp) 1403 #define netmap_enable_all_rings(ifp) 1404 #define netmap_disable_all_rings(ifp) 1405 1406 #define iflib_netmap_attach(ctx) (0) 1407 #define netmap_rx_irq(ifp, qid, budget) (0) 1408 #endif 1409 1410 #if defined(__i386__) || defined(__amd64__) 1411 static __inline void 1412 prefetch(void *x) 1413 { 1414 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1415 } 1416 1417 static __inline void 1418 prefetch2cachelines(void *x) 1419 { 1420 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1421 #if (CACHE_LINE_SIZE < 128) 1422 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x) + CACHE_LINE_SIZE / (sizeof(unsigned long))))); 1423 #endif 1424 } 1425 #else 1426 static __inline void 1427 prefetch(void *x) 1428 { 1429 } 1430 1431 static __inline void 1432 prefetch2cachelines(void *x) 1433 { 1434 } 1435 #endif 1436 1437 static void 1438 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1439 { 1440 iflib_fl_t fl; 1441 1442 fl = &rxq->ifr_fl[flid]; 1443 iru->iru_paddrs = fl->ifl_bus_addrs; 1444 iru->iru_idxs = fl->ifl_rxd_idxs; 1445 iru->iru_qsidx = rxq->ifr_id; 1446 iru->iru_buf_size = fl->ifl_buf_size; 1447 iru->iru_flidx = fl->ifl_id; 1448 } 1449 1450 static void 1451 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1452 { 1453 if (err) 1454 return; 1455 *(bus_addr_t *) arg = segs[0].ds_addr; 1456 } 1457 1458 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \ 1459 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \ 1460 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL) 1461 1462 int 1463 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1464 { 1465 int err; 1466 device_t dev = ctx->ifc_dev; 1467 bus_addr_t lowaddr; 1468 1469 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width); 1470 1471 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1472 align, 0, /* alignment, bounds */ 1473 lowaddr, /* lowaddr */ 1474 BUS_SPACE_MAXADDR, /* highaddr */ 1475 NULL, NULL, /* filter, filterarg */ 1476 size, /* maxsize */ 1477 1, /* nsegments */ 1478 size, /* maxsegsize */ 1479 BUS_DMA_ALLOCNOW, /* flags */ 1480 NULL, /* lockfunc */ 1481 NULL, /* lockarg */ 1482 &dma->idi_tag); 1483 if (err) { 1484 device_printf(dev, 1485 "%s: bus_dma_tag_create failed: %d (size=%d, align=%d)\n", 1486 __func__, err, size, align); 1487 goto fail_0; 1488 } 1489 1490 err = bus_dmamem_alloc(dma->idi_tag, (void **)&dma->idi_vaddr, 1491 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1492 if (err) { 1493 device_printf(dev, 1494 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1495 __func__, (uintmax_t)size, err); 1496 goto fail_1; 1497 } 1498 1499 dma->idi_paddr = IF_BAD_DMA; 1500 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1501 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1502 if (err || dma->idi_paddr == IF_BAD_DMA) { 1503 device_printf(dev, 1504 "%s: bus_dmamap_load failed: %d\n", 1505 __func__, err); 1506 goto fail_2; 1507 } 1508 1509 dma->idi_size = size; 1510 return (0); 1511 1512 fail_2: 1513 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1514 fail_1: 1515 bus_dma_tag_destroy(dma->idi_tag); 1516 fail_0: 1517 dma->idi_tag = NULL; 1518 1519 return (err); 1520 } 1521 1522 int 1523 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1524 { 1525 if_shared_ctx_t sctx = ctx->ifc_sctx; 1526 1527 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1528 1529 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1530 } 1531 1532 int 1533 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1534 { 1535 int i, err; 1536 iflib_dma_info_t *dmaiter; 1537 1538 dmaiter = dmalist; 1539 for (i = 0; i < count; i++, dmaiter++) { 1540 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1541 break; 1542 } 1543 if (err) 1544 iflib_dma_free_multi(dmalist, i); 1545 return (err); 1546 } 1547 1548 void 1549 iflib_dma_free(iflib_dma_info_t dma) 1550 { 1551 if (dma->idi_tag == NULL) 1552 return; 1553 if (dma->idi_paddr != IF_BAD_DMA) { 1554 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1555 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1556 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1557 dma->idi_paddr = IF_BAD_DMA; 1558 } 1559 if (dma->idi_vaddr != NULL) { 1560 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1561 dma->idi_vaddr = NULL; 1562 } 1563 bus_dma_tag_destroy(dma->idi_tag); 1564 dma->idi_tag = NULL; 1565 } 1566 1567 void 1568 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1569 { 1570 int i; 1571 iflib_dma_info_t *dmaiter = dmalist; 1572 1573 for (i = 0; i < count; i++, dmaiter++) 1574 iflib_dma_free(*dmaiter); 1575 } 1576 1577 static int 1578 iflib_fast_intr(void *arg) 1579 { 1580 iflib_filter_info_t info = arg; 1581 struct grouptask *gtask = info->ifi_task; 1582 int result; 1583 1584 DBG_COUNTER_INC(fast_intrs); 1585 if (info->ifi_filter != NULL) { 1586 result = info->ifi_filter(info->ifi_filter_arg); 1587 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1588 return (result); 1589 } 1590 1591 GROUPTASK_ENQUEUE(gtask); 1592 return (FILTER_HANDLED); 1593 } 1594 1595 static int 1596 iflib_fast_intr_rxtx(void *arg) 1597 { 1598 iflib_filter_info_t info = arg; 1599 struct grouptask *gtask = info->ifi_task; 1600 if_ctx_t ctx; 1601 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1602 iflib_txq_t txq; 1603 void *sc; 1604 int i, cidx, result; 1605 qidx_t txqid; 1606 bool intr_enable, intr_legacy; 1607 1608 DBG_COUNTER_INC(fast_intrs); 1609 if (info->ifi_filter != NULL) { 1610 result = info->ifi_filter(info->ifi_filter_arg); 1611 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1612 return (result); 1613 } 1614 1615 ctx = rxq->ifr_ctx; 1616 sc = ctx->ifc_softc; 1617 intr_enable = false; 1618 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1619 MPASS(rxq->ifr_ntxqirq); 1620 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1621 txqid = rxq->ifr_txqid[i]; 1622 txq = &ctx->ifc_txqs[txqid]; 1623 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1624 BUS_DMASYNC_POSTREAD); 1625 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1626 if (intr_legacy) 1627 intr_enable = true; 1628 else 1629 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1630 continue; 1631 } 1632 GROUPTASK_ENQUEUE(&txq->ift_task); 1633 } 1634 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1635 cidx = rxq->ifr_cq_cidx; 1636 else 1637 cidx = rxq->ifr_fl[0].ifl_cidx; 1638 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1639 GROUPTASK_ENQUEUE(gtask); 1640 else { 1641 if (intr_legacy) 1642 intr_enable = true; 1643 else 1644 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1645 DBG_COUNTER_INC(rx_intr_enables); 1646 } 1647 if (intr_enable) 1648 IFDI_INTR_ENABLE(ctx); 1649 return (FILTER_HANDLED); 1650 } 1651 1652 static int 1653 iflib_fast_intr_ctx(void *arg) 1654 { 1655 iflib_filter_info_t info = arg; 1656 if_ctx_t ctx = info->ifi_ctx; 1657 int result; 1658 1659 DBG_COUNTER_INC(fast_intrs); 1660 if (info->ifi_filter != NULL) { 1661 result = info->ifi_filter(info->ifi_filter_arg); 1662 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1663 return (result); 1664 } 1665 1666 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_admin_task); 1667 return (FILTER_HANDLED); 1668 } 1669 1670 static int 1671 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1672 driver_filter_t filter, driver_intr_t handler, void *arg, 1673 const char *name) 1674 { 1675 struct resource *res; 1676 void *tag = NULL; 1677 device_t dev = ctx->ifc_dev; 1678 int flags, i, rc; 1679 1680 flags = RF_ACTIVE; 1681 if (ctx->ifc_flags & IFC_LEGACY) 1682 flags |= RF_SHAREABLE; 1683 MPASS(rid < 512); 1684 i = rid; 1685 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1686 if (res == NULL) { 1687 device_printf(dev, 1688 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1689 return (ENOMEM); 1690 } 1691 irq->ii_res = res; 1692 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1693 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1694 filter, handler, arg, &tag); 1695 if (rc != 0) { 1696 device_printf(dev, 1697 "failed to setup interrupt for rid %d, name %s: %d\n", 1698 rid, name ? name : "unknown", rc); 1699 return (rc); 1700 } else if (name) 1701 bus_describe_intr(dev, res, tag, "%s", name); 1702 1703 irq->ii_tag = tag; 1704 return (0); 1705 } 1706 1707 /********************************************************************* 1708 * 1709 * Allocate DMA resources for TX buffers as well as memory for the TX 1710 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1711 * iflib_sw_tx_desc_array structure, storing all the information that 1712 * is needed to transmit a packet on the wire. This is called only 1713 * once at attach, setup is done every reset. 1714 * 1715 **********************************************************************/ 1716 static int 1717 iflib_txsd_alloc(iflib_txq_t txq) 1718 { 1719 if_ctx_t ctx = txq->ift_ctx; 1720 if_shared_ctx_t sctx = ctx->ifc_sctx; 1721 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1722 device_t dev = ctx->ifc_dev; 1723 bus_size_t tsomaxsize; 1724 bus_addr_t lowaddr; 1725 int err, nsegments, ntsosegments; 1726 bool tso; 1727 1728 nsegments = scctx->isc_tx_nsegments; 1729 ntsosegments = scctx->isc_tx_tso_segments_max; 1730 tsomaxsize = scctx->isc_tx_tso_size_max; 1731 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1732 tsomaxsize += sizeof(struct ether_vlan_header); 1733 MPASS(scctx->isc_ntxd[0] > 0); 1734 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1735 MPASS(nsegments > 0); 1736 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1737 MPASS(ntsosegments > 0); 1738 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1739 } 1740 1741 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1742 1743 /* 1744 * Set up DMA tags for TX buffers. 1745 */ 1746 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1747 1, 0, /* alignment, bounds */ 1748 lowaddr, /* lowaddr */ 1749 BUS_SPACE_MAXADDR, /* highaddr */ 1750 NULL, NULL, /* filter, filterarg */ 1751 sctx->isc_tx_maxsize, /* maxsize */ 1752 nsegments, /* nsegments */ 1753 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1754 0, /* flags */ 1755 NULL, /* lockfunc */ 1756 NULL, /* lockfuncarg */ 1757 &txq->ift_buf_tag))) { 1758 device_printf(dev, "Unable to allocate TX DMA tag: %d\n", err); 1759 device_printf(dev, "maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1760 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1761 goto fail; 1762 } 1763 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1764 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1765 1, 0, /* alignment, bounds */ 1766 lowaddr, /* lowaddr */ 1767 BUS_SPACE_MAXADDR, /* highaddr */ 1768 NULL, NULL, /* filter, filterarg */ 1769 tsomaxsize, /* maxsize */ 1770 ntsosegments, /* nsegments */ 1771 sctx->isc_tso_maxsegsize, /* maxsegsize */ 1772 0, /* flags */ 1773 NULL, /* lockfunc */ 1774 NULL, /* lockfuncarg */ 1775 &txq->ift_tso_buf_tag))) { 1776 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1777 err); 1778 goto fail; 1779 } 1780 1781 /* Allocate memory for the TX mbuf map. */ 1782 if (!(txq->ift_sds.ifsd_m = 1783 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1784 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1785 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1786 err = ENOMEM; 1787 goto fail; 1788 } 1789 1790 /* 1791 * Create the DMA maps for TX buffers. 1792 */ 1793 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1794 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1795 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1796 device_printf(dev, 1797 "Unable to allocate TX buffer DMA map memory\n"); 1798 err = ENOMEM; 1799 goto fail; 1800 } 1801 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1802 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1803 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1804 device_printf(dev, 1805 "Unable to allocate TSO TX buffer map memory\n"); 1806 err = ENOMEM; 1807 goto fail; 1808 } 1809 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1810 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1811 &txq->ift_sds.ifsd_map[i]); 1812 if (err != 0) { 1813 device_printf(dev, "Unable to create TX DMA map\n"); 1814 goto fail; 1815 } 1816 if (!tso) 1817 continue; 1818 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1819 &txq->ift_sds.ifsd_tso_map[i]); 1820 if (err != 0) { 1821 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1822 goto fail; 1823 } 1824 } 1825 return (0); 1826 fail: 1827 /* We free all, it handles case where we are in the middle */ 1828 iflib_tx_structures_free(ctx); 1829 return (err); 1830 } 1831 1832 static void 1833 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1834 { 1835 bus_dmamap_t map; 1836 1837 if (txq->ift_sds.ifsd_map != NULL) { 1838 map = txq->ift_sds.ifsd_map[i]; 1839 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1840 bus_dmamap_unload(txq->ift_buf_tag, map); 1841 bus_dmamap_destroy(txq->ift_buf_tag, map); 1842 txq->ift_sds.ifsd_map[i] = NULL; 1843 } 1844 1845 if (txq->ift_sds.ifsd_tso_map != NULL) { 1846 map = txq->ift_sds.ifsd_tso_map[i]; 1847 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1848 BUS_DMASYNC_POSTWRITE); 1849 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1850 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1851 txq->ift_sds.ifsd_tso_map[i] = NULL; 1852 } 1853 } 1854 1855 static void 1856 iflib_txq_destroy(iflib_txq_t txq) 1857 { 1858 if_ctx_t ctx = txq->ift_ctx; 1859 1860 for (int i = 0; i < txq->ift_size; i++) 1861 iflib_txsd_destroy(ctx, txq, i); 1862 1863 if (txq->ift_br != NULL) { 1864 ifmp_ring_free(txq->ift_br); 1865 txq->ift_br = NULL; 1866 } 1867 1868 mtx_destroy(&txq->ift_mtx); 1869 1870 if (txq->ift_sds.ifsd_map != NULL) { 1871 free(txq->ift_sds.ifsd_map, M_IFLIB); 1872 txq->ift_sds.ifsd_map = NULL; 1873 } 1874 if (txq->ift_sds.ifsd_tso_map != NULL) { 1875 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1876 txq->ift_sds.ifsd_tso_map = NULL; 1877 } 1878 if (txq->ift_sds.ifsd_m != NULL) { 1879 free(txq->ift_sds.ifsd_m, M_IFLIB); 1880 txq->ift_sds.ifsd_m = NULL; 1881 } 1882 if (txq->ift_buf_tag != NULL) { 1883 bus_dma_tag_destroy(txq->ift_buf_tag); 1884 txq->ift_buf_tag = NULL; 1885 } 1886 if (txq->ift_tso_buf_tag != NULL) { 1887 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1888 txq->ift_tso_buf_tag = NULL; 1889 } 1890 if (txq->ift_ifdi != NULL) { 1891 free(txq->ift_ifdi, M_IFLIB); 1892 } 1893 } 1894 1895 static void 1896 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1897 { 1898 struct mbuf **mp; 1899 1900 mp = &txq->ift_sds.ifsd_m[i]; 1901 if (*mp == NULL) 1902 return; 1903 1904 if (txq->ift_sds.ifsd_map != NULL) { 1905 bus_dmamap_sync(txq->ift_buf_tag, 1906 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1907 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1908 } 1909 if (txq->ift_sds.ifsd_tso_map != NULL) { 1910 bus_dmamap_sync(txq->ift_tso_buf_tag, 1911 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1912 bus_dmamap_unload(txq->ift_tso_buf_tag, 1913 txq->ift_sds.ifsd_tso_map[i]); 1914 } 1915 m_freem(*mp); 1916 DBG_COUNTER_INC(tx_frees); 1917 *mp = NULL; 1918 } 1919 1920 static int 1921 iflib_txq_setup(iflib_txq_t txq) 1922 { 1923 if_ctx_t ctx = txq->ift_ctx; 1924 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1925 if_shared_ctx_t sctx = ctx->ifc_sctx; 1926 iflib_dma_info_t di; 1927 int i; 1928 1929 /* Set number of descriptors available */ 1930 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1931 /* XXX make configurable */ 1932 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1933 1934 /* Reset indices */ 1935 txq->ift_cidx_processed = 0; 1936 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1937 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1938 txq->ift_pad = scctx->isc_tx_pad; 1939 1940 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1941 bzero((void *)di->idi_vaddr, di->idi_size); 1942 1943 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1944 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1945 bus_dmamap_sync(di->idi_tag, di->idi_map, 1946 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1947 return (0); 1948 } 1949 1950 /********************************************************************* 1951 * 1952 * Allocate DMA resources for RX buffers as well as memory for the RX 1953 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1954 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1955 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1956 * Since we use use one entry in iflib_sw_rx_desc_array per received 1957 * packet, the maximum number of entries we'll need is equal to the 1958 * number of hardware receive descriptors that we've allocated. 1959 * 1960 **********************************************************************/ 1961 static int 1962 iflib_rxsd_alloc(iflib_rxq_t rxq) 1963 { 1964 if_ctx_t ctx = rxq->ifr_ctx; 1965 if_shared_ctx_t sctx = ctx->ifc_sctx; 1966 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1967 device_t dev = ctx->ifc_dev; 1968 iflib_fl_t fl; 1969 bus_addr_t lowaddr; 1970 int err; 1971 1972 MPASS(scctx->isc_nrxd[0] > 0); 1973 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1974 1975 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1976 1977 fl = rxq->ifr_fl; 1978 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1979 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1980 /* Set up DMA tag for RX buffers. */ 1981 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1982 1, 0, /* alignment, bounds */ 1983 lowaddr, /* lowaddr */ 1984 BUS_SPACE_MAXADDR, /* highaddr */ 1985 NULL, NULL, /* filter, filterarg */ 1986 sctx->isc_rx_maxsize, /* maxsize */ 1987 sctx->isc_rx_nsegments, /* nsegments */ 1988 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1989 0, /* flags */ 1990 NULL, /* lockfunc */ 1991 NULL, /* lockarg */ 1992 &fl->ifl_buf_tag); 1993 if (err) { 1994 device_printf(dev, 1995 "Unable to allocate RX DMA tag: %d\n", err); 1996 goto fail; 1997 } 1998 1999 /* Allocate memory for the RX mbuf map. */ 2000 if (!(fl->ifl_sds.ifsd_m = 2001 (struct mbuf **) malloc(sizeof(struct mbuf *) * 2002 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2003 device_printf(dev, 2004 "Unable to allocate RX mbuf map memory\n"); 2005 err = ENOMEM; 2006 goto fail; 2007 } 2008 2009 /* Allocate memory for the direct RX cluster pointer map. */ 2010 if (!(fl->ifl_sds.ifsd_cl = 2011 (caddr_t *) malloc(sizeof(caddr_t) * 2012 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2013 device_printf(dev, 2014 "Unable to allocate RX cluster map memory\n"); 2015 err = ENOMEM; 2016 goto fail; 2017 } 2018 2019 /* Allocate memory for the RX cluster bus address map. */ 2020 if (!(fl->ifl_sds.ifsd_ba = 2021 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 2022 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2023 device_printf(dev, 2024 "Unable to allocate RX bus address map memory\n"); 2025 err = ENOMEM; 2026 goto fail; 2027 } 2028 2029 /* 2030 * Create the DMA maps for RX buffers. 2031 */ 2032 if (!(fl->ifl_sds.ifsd_map = 2033 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2034 device_printf(dev, 2035 "Unable to allocate RX buffer DMA map memory\n"); 2036 err = ENOMEM; 2037 goto fail; 2038 } 2039 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 2040 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 2041 &fl->ifl_sds.ifsd_map[i]); 2042 if (err != 0) { 2043 device_printf(dev, "Unable to create RX buffer DMA map\n"); 2044 goto fail; 2045 } 2046 } 2047 } 2048 return (0); 2049 2050 fail: 2051 iflib_rx_structures_free(ctx); 2052 return (err); 2053 } 2054 2055 /* 2056 * Internal service routines 2057 */ 2058 2059 struct rxq_refill_cb_arg { 2060 int error; 2061 bus_dma_segment_t seg; 2062 int nseg; 2063 }; 2064 2065 static void 2066 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2067 { 2068 struct rxq_refill_cb_arg *cb_arg = arg; 2069 2070 cb_arg->error = error; 2071 cb_arg->seg = segs[0]; 2072 cb_arg->nseg = nseg; 2073 } 2074 2075 /** 2076 * iflib_fl_refill - refill an rxq free-buffer list 2077 * @ctx: the iflib context 2078 * @fl: the free list to refill 2079 * @count: the number of new buffers to allocate 2080 * 2081 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 2082 * The caller must assure that @count does not exceed the queue's capacity 2083 * minus one (since we always leave a descriptor unavailable). 2084 */ 2085 static uint8_t 2086 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 2087 { 2088 struct if_rxd_update iru; 2089 struct rxq_refill_cb_arg cb_arg; 2090 struct mbuf *m; 2091 caddr_t cl, *sd_cl; 2092 struct mbuf **sd_m; 2093 bus_dmamap_t *sd_map; 2094 bus_addr_t bus_addr, *sd_ba; 2095 int err, frag_idx, i, idx, n, pidx; 2096 qidx_t credits; 2097 2098 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 2099 2100 sd_m = fl->ifl_sds.ifsd_m; 2101 sd_map = fl->ifl_sds.ifsd_map; 2102 sd_cl = fl->ifl_sds.ifsd_cl; 2103 sd_ba = fl->ifl_sds.ifsd_ba; 2104 pidx = fl->ifl_pidx; 2105 idx = pidx; 2106 frag_idx = fl->ifl_fragidx; 2107 credits = fl->ifl_credits; 2108 2109 i = 0; 2110 n = count; 2111 MPASS(n > 0); 2112 MPASS(credits + n <= fl->ifl_size); 2113 2114 if (pidx < fl->ifl_cidx) 2115 MPASS(pidx + n <= fl->ifl_cidx); 2116 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 2117 MPASS(fl->ifl_gen == 0); 2118 if (pidx > fl->ifl_cidx) 2119 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 2120 2121 DBG_COUNTER_INC(fl_refills); 2122 if (n > 8) 2123 DBG_COUNTER_INC(fl_refills_large); 2124 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 2125 while (n-- > 0) { 2126 /* 2127 * We allocate an uninitialized mbuf + cluster, mbuf is 2128 * initialized after rx. 2129 * 2130 * If the cluster is still set then we know a minimum sized 2131 * packet was received 2132 */ 2133 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2134 &frag_idx); 2135 if (frag_idx < 0) 2136 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2137 MPASS(frag_idx >= 0); 2138 if ((cl = sd_cl[frag_idx]) == NULL) { 2139 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2140 if (__predict_false(cl == NULL)) 2141 break; 2142 2143 cb_arg.error = 0; 2144 MPASS(sd_map != NULL); 2145 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2146 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2147 BUS_DMA_NOWAIT); 2148 if (__predict_false(err != 0 || cb_arg.error)) { 2149 uma_zfree(fl->ifl_zone, cl); 2150 break; 2151 } 2152 2153 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2154 sd_cl[frag_idx] = cl; 2155 #if MEMORY_LOGGING 2156 fl->ifl_cl_enqueued++; 2157 #endif 2158 } else { 2159 bus_addr = sd_ba[frag_idx]; 2160 } 2161 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2162 BUS_DMASYNC_PREREAD); 2163 2164 if (sd_m[frag_idx] == NULL) { 2165 m = m_gethdr_raw(M_NOWAIT, 0); 2166 if (__predict_false(m == NULL)) 2167 break; 2168 sd_m[frag_idx] = m; 2169 } 2170 bit_set(fl->ifl_rx_bitmap, frag_idx); 2171 #if MEMORY_LOGGING 2172 fl->ifl_m_enqueued++; 2173 #endif 2174 2175 DBG_COUNTER_INC(rx_allocs); 2176 fl->ifl_rxd_idxs[i] = frag_idx; 2177 fl->ifl_bus_addrs[i] = bus_addr; 2178 credits++; 2179 i++; 2180 MPASS(credits <= fl->ifl_size); 2181 if (++idx == fl->ifl_size) { 2182 #ifdef INVARIANTS 2183 fl->ifl_gen = 1; 2184 #endif 2185 idx = 0; 2186 } 2187 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2188 iru.iru_pidx = pidx; 2189 iru.iru_count = i; 2190 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2191 fl->ifl_pidx = idx; 2192 fl->ifl_credits = credits; 2193 pidx = idx; 2194 i = 0; 2195 } 2196 } 2197 2198 if (n < count - 1) { 2199 if (i != 0) { 2200 iru.iru_pidx = pidx; 2201 iru.iru_count = i; 2202 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2203 fl->ifl_pidx = idx; 2204 fl->ifl_credits = credits; 2205 } 2206 DBG_COUNTER_INC(rxd_flush); 2207 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2208 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2209 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2210 fl->ifl_id, fl->ifl_pidx); 2211 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2212 fl->ifl_fragidx = frag_idx + 1; 2213 if (fl->ifl_fragidx == fl->ifl_size) 2214 fl->ifl_fragidx = 0; 2215 } else { 2216 fl->ifl_fragidx = frag_idx; 2217 } 2218 } 2219 2220 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2221 } 2222 2223 static inline uint8_t 2224 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2225 { 2226 /* 2227 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2228 * This is important as it confuses most NICs. For instance, 2229 * Intel NICs have (per receive ring) RDH and RDT registers, where 2230 * RDH points to the next receive descriptor to be used by the NIC, 2231 * and RDT for the next receive descriptor to be published by the 2232 * driver to the NIC (RDT - 1 is thus the last valid one). 2233 * The condition RDH == RDT means no descriptors are available to 2234 * the NIC, and thus it would be ambiguous if it also meant that 2235 * all the descriptors are available to the NIC. 2236 */ 2237 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2238 #ifdef INVARIANTS 2239 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2240 #endif 2241 2242 MPASS(fl->ifl_credits <= fl->ifl_size); 2243 MPASS(reclaimable == delta); 2244 2245 if (reclaimable > 0) 2246 return (iflib_fl_refill(ctx, fl, reclaimable)); 2247 return (0); 2248 } 2249 2250 uint8_t 2251 iflib_in_detach(if_ctx_t ctx) 2252 { 2253 bool in_detach; 2254 2255 STATE_LOCK(ctx); 2256 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2257 STATE_UNLOCK(ctx); 2258 return (in_detach); 2259 } 2260 2261 static void 2262 iflib_fl_bufs_free(iflib_fl_t fl) 2263 { 2264 iflib_dma_info_t idi = fl->ifl_ifdi; 2265 bus_dmamap_t sd_map; 2266 uint32_t i; 2267 2268 for (i = 0; i < fl->ifl_size; i++) { 2269 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2270 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2271 2272 if (*sd_cl != NULL) { 2273 sd_map = fl->ifl_sds.ifsd_map[i]; 2274 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2275 BUS_DMASYNC_POSTREAD); 2276 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2277 uma_zfree(fl->ifl_zone, *sd_cl); 2278 *sd_cl = NULL; 2279 if (*sd_m != NULL) { 2280 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2281 m_free_raw(*sd_m); 2282 *sd_m = NULL; 2283 } 2284 } else { 2285 MPASS(*sd_m == NULL); 2286 } 2287 #if MEMORY_LOGGING 2288 fl->ifl_m_dequeued++; 2289 fl->ifl_cl_dequeued++; 2290 #endif 2291 } 2292 #ifdef INVARIANTS 2293 for (i = 0; i < fl->ifl_size; i++) { 2294 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2295 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2296 } 2297 #endif 2298 /* 2299 * Reset free list values 2300 */ 2301 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2302 bzero(idi->idi_vaddr, idi->idi_size); 2303 } 2304 2305 /********************************************************************* 2306 * 2307 * Initialize a free list and its buffers. 2308 * 2309 **********************************************************************/ 2310 static int 2311 iflib_fl_setup(iflib_fl_t fl) 2312 { 2313 iflib_rxq_t rxq = fl->ifl_rxq; 2314 if_ctx_t ctx = rxq->ifr_ctx; 2315 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2316 int qidx; 2317 2318 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2319 /* 2320 * Free current RX buffer structs and their mbufs 2321 */ 2322 iflib_fl_bufs_free(fl); 2323 /* Now replenish the mbufs */ 2324 MPASS(fl->ifl_credits == 0); 2325 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2326 if (scctx->isc_rxd_buf_size[qidx] != 0) 2327 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2328 else 2329 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2330 /* 2331 * ifl_buf_size may be a driver-supplied value, so pull it up 2332 * to the selected mbuf size. 2333 */ 2334 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2335 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2336 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2337 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2338 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2339 2340 /* 2341 * Avoid pre-allocating zillions of clusters to an idle card 2342 * potentially speeding up attach. In any case make sure 2343 * to leave a descriptor unavailable. See the comment in 2344 * iflib_fl_refill_all(). 2345 */ 2346 MPASS(fl->ifl_size > 0); 2347 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2348 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2349 return (ENOBUFS); 2350 /* 2351 * handle failure 2352 */ 2353 MPASS(rxq != NULL); 2354 MPASS(fl->ifl_ifdi != NULL); 2355 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2356 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2357 return (0); 2358 } 2359 2360 /********************************************************************* 2361 * 2362 * Free receive ring data structures 2363 * 2364 **********************************************************************/ 2365 static void 2366 iflib_rx_sds_free(iflib_rxq_t rxq) 2367 { 2368 iflib_fl_t fl; 2369 int i, j; 2370 2371 if (rxq->ifr_fl != NULL) { 2372 for (i = 0; i < rxq->ifr_nfl; i++) { 2373 fl = &rxq->ifr_fl[i]; 2374 if (fl->ifl_buf_tag != NULL) { 2375 if (fl->ifl_sds.ifsd_map != NULL) { 2376 for (j = 0; j < fl->ifl_size; j++) { 2377 bus_dmamap_sync( 2378 fl->ifl_buf_tag, 2379 fl->ifl_sds.ifsd_map[j], 2380 BUS_DMASYNC_POSTREAD); 2381 bus_dmamap_unload( 2382 fl->ifl_buf_tag, 2383 fl->ifl_sds.ifsd_map[j]); 2384 bus_dmamap_destroy( 2385 fl->ifl_buf_tag, 2386 fl->ifl_sds.ifsd_map[j]); 2387 } 2388 } 2389 bus_dma_tag_destroy(fl->ifl_buf_tag); 2390 fl->ifl_buf_tag = NULL; 2391 } 2392 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2393 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2394 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2395 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2396 free(fl->ifl_rx_bitmap, M_IFLIB); 2397 fl->ifl_sds.ifsd_m = NULL; 2398 fl->ifl_sds.ifsd_cl = NULL; 2399 fl->ifl_sds.ifsd_ba = NULL; 2400 fl->ifl_sds.ifsd_map = NULL; 2401 fl->ifl_rx_bitmap = NULL; 2402 } 2403 free(rxq->ifr_fl, M_IFLIB); 2404 rxq->ifr_fl = NULL; 2405 free(rxq->ifr_ifdi, M_IFLIB); 2406 rxq->ifr_ifdi = NULL; 2407 rxq->ifr_cq_cidx = 0; 2408 } 2409 } 2410 2411 /* 2412 * Timer routine 2413 */ 2414 static void 2415 iflib_timer(void *arg) 2416 { 2417 iflib_txq_t txq = arg; 2418 if_ctx_t ctx = txq->ift_ctx; 2419 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2420 uint64_t this_tick = ticks; 2421 2422 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2423 return; 2424 2425 /* 2426 ** Check on the state of the TX queue(s), this 2427 ** can be done without the lock because its RO 2428 ** and the HUNG state will be static if set. 2429 */ 2430 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) { 2431 txq->ift_last_timer_tick = this_tick; 2432 IFDI_TIMER(ctx, txq->ift_id); 2433 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2434 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2435 (sctx->isc_pause_frames == 0))) 2436 goto hung; 2437 2438 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2439 ifmp_ring_is_stalled(txq->ift_br)) { 2440 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, 2441 ("queue can't be marked as hung if interface is down")); 2442 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2443 } 2444 txq->ift_cleaned_prev = txq->ift_cleaned; 2445 } 2446 /* handle any laggards */ 2447 if (txq->ift_db_pending) 2448 GROUPTASK_ENQUEUE(&txq->ift_task); 2449 2450 sctx->isc_pause_frames = 0; 2451 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2452 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, 2453 txq, txq->ift_timer.c_cpu); 2454 return; 2455 2456 hung: 2457 device_printf(ctx->ifc_dev, 2458 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2459 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2460 STATE_LOCK(ctx); 2461 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2462 ctx->ifc_flags |= (IFC_DO_WATCHDOG | IFC_DO_RESET); 2463 iflib_admin_intr_deferred(ctx); 2464 STATE_UNLOCK(ctx); 2465 } 2466 2467 static uint16_t 2468 iflib_get_mbuf_size_for(unsigned int size) 2469 { 2470 2471 if (size <= MCLBYTES) 2472 return (MCLBYTES); 2473 else 2474 return (MJUMPAGESIZE); 2475 } 2476 2477 static void 2478 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2479 { 2480 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2481 2482 /* 2483 * XXX don't set the max_frame_size to larger 2484 * than the hardware can handle 2485 */ 2486 ctx->ifc_rx_mbuf_sz = 2487 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2488 } 2489 2490 uint32_t 2491 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2492 { 2493 2494 return (ctx->ifc_rx_mbuf_sz); 2495 } 2496 2497 static void 2498 iflib_init_locked(if_ctx_t ctx) 2499 { 2500 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2501 if_t ifp = ctx->ifc_ifp; 2502 iflib_fl_t fl; 2503 iflib_txq_t txq; 2504 iflib_rxq_t rxq; 2505 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2506 2507 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2508 IFDI_INTR_DISABLE(ctx); 2509 2510 /* 2511 * See iflib_stop(). Useful in case iflib_init_locked() is 2512 * called without first calling iflib_stop(). 2513 */ 2514 netmap_disable_all_rings(ifp); 2515 2516 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2517 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2518 /* Set hardware offload abilities */ 2519 if_clearhwassist(ifp); 2520 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2521 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2522 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2523 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2524 if (if_getcapenable(ifp) & IFCAP_TSO4) 2525 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2526 if (if_getcapenable(ifp) & IFCAP_TSO6) 2527 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2528 2529 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 2530 CALLOUT_LOCK(txq); 2531 callout_stop(&txq->ift_timer); 2532 #ifdef DEV_NETMAP 2533 callout_stop(&txq->ift_netmap_timer); 2534 #endif /* DEV_NETMAP */ 2535 CALLOUT_UNLOCK(txq); 2536 (void)iflib_netmap_txq_init(ctx, txq); 2537 } 2538 2539 /* 2540 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2541 * that drivers can use the value when setting up the hardware receive 2542 * buffers. 2543 */ 2544 iflib_calc_rx_mbuf_sz(ctx); 2545 2546 #ifdef INVARIANTS 2547 i = if_getdrvflags(ifp); 2548 #endif 2549 IFDI_INIT(ctx); 2550 MPASS(if_getdrvflags(ifp) == i); 2551 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 2552 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2553 /* This rxq is in netmap mode. Skip normal init. */ 2554 continue; 2555 } 2556 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2557 if (iflib_fl_setup(fl)) { 2558 device_printf(ctx->ifc_dev, 2559 "setting up free list %d failed - " 2560 "check cluster settings\n", j); 2561 goto done; 2562 } 2563 } 2564 } 2565 done: 2566 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2567 IFDI_INTR_ENABLE(ctx); 2568 txq = ctx->ifc_txqs; 2569 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) 2570 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 2571 txq->ift_timer.c_cpu); 2572 2573 /* Re-enable txsync/rxsync. */ 2574 netmap_enable_all_rings(ifp); 2575 } 2576 2577 static int 2578 iflib_media_change(if_t ifp) 2579 { 2580 if_ctx_t ctx = if_getsoftc(ifp); 2581 int err; 2582 2583 CTX_LOCK(ctx); 2584 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2585 iflib_if_init_locked(ctx); 2586 CTX_UNLOCK(ctx); 2587 return (err); 2588 } 2589 2590 static void 2591 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2592 { 2593 if_ctx_t ctx = if_getsoftc(ifp); 2594 2595 CTX_LOCK(ctx); 2596 IFDI_UPDATE_ADMIN_STATUS(ctx); 2597 IFDI_MEDIA_STATUS(ctx, ifmr); 2598 CTX_UNLOCK(ctx); 2599 } 2600 2601 static void 2602 iflib_stop(if_ctx_t ctx) 2603 { 2604 iflib_txq_t txq = ctx->ifc_txqs; 2605 iflib_rxq_t rxq = ctx->ifc_rxqs; 2606 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2607 if_shared_ctx_t sctx = ctx->ifc_sctx; 2608 iflib_dma_info_t di; 2609 iflib_fl_t fl; 2610 int i, j; 2611 2612 /* Tell the stack that the interface is no longer active */ 2613 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2614 2615 IFDI_INTR_DISABLE(ctx); 2616 DELAY(1000); 2617 IFDI_STOP(ctx); 2618 DELAY(1000); 2619 2620 /* 2621 * Stop any pending txsync/rxsync and prevent new ones 2622 * form starting. Processes blocked in poll() will get 2623 * POLLERR. 2624 */ 2625 netmap_disable_all_rings(ctx->ifc_ifp); 2626 2627 iflib_debug_reset(); 2628 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2629 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2630 /* make sure all transmitters have completed before proceeding XXX */ 2631 2632 CALLOUT_LOCK(txq); 2633 callout_stop(&txq->ift_timer); 2634 #ifdef DEV_NETMAP 2635 callout_stop(&txq->ift_netmap_timer); 2636 #endif /* DEV_NETMAP */ 2637 CALLOUT_UNLOCK(txq); 2638 2639 if (!ctx->ifc_sysctl_simple_tx) { 2640 /* clean any enqueued buffers */ 2641 iflib_ifmp_purge(txq); 2642 } 2643 /* Free any existing tx buffers. */ 2644 for (j = 0; j < txq->ift_size; j++) { 2645 iflib_txsd_free(ctx, txq, j); 2646 } 2647 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2648 txq->ift_in_use = txq->ift_gen = txq->ift_no_desc_avail = 0; 2649 if (sctx->isc_flags & IFLIB_PRESERVE_TX_INDICES) 2650 txq->ift_cidx = txq->ift_pidx; 2651 else 2652 txq->ift_cidx = txq->ift_pidx = 0; 2653 2654 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2655 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2656 txq->ift_pullups = 0; 2657 ifmp_ring_reset_stats(txq->ift_br); 2658 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2659 bzero((void *)di->idi_vaddr, di->idi_size); 2660 } 2661 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2662 if (rxq->ifr_task.gt_taskqueue != NULL) 2663 gtaskqueue_drain(rxq->ifr_task.gt_taskqueue, 2664 &rxq->ifr_task.gt_task); 2665 2666 rxq->ifr_cq_cidx = 0; 2667 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2668 bzero((void *)di->idi_vaddr, di->idi_size); 2669 /* also resets the free lists pidx/cidx */ 2670 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2671 iflib_fl_bufs_free(fl); 2672 } 2673 } 2674 2675 static inline caddr_t 2676 calc_next_rxd(iflib_fl_t fl, int cidx) 2677 { 2678 qidx_t size; 2679 int nrxd; 2680 caddr_t start, end, cur, next; 2681 2682 nrxd = fl->ifl_size; 2683 size = fl->ifl_rxd_size; 2684 start = fl->ifl_ifdi->idi_vaddr; 2685 2686 if (__predict_false(size == 0)) 2687 return (start); 2688 cur = start + size * cidx; 2689 end = start + size * nrxd; 2690 next = CACHE_PTR_NEXT(cur); 2691 return (next < end ? next : start); 2692 } 2693 2694 static inline void 2695 prefetch_pkts(iflib_fl_t fl, int cidx) 2696 { 2697 int nextptr; 2698 int nrxd = fl->ifl_size; 2699 caddr_t next_rxd; 2700 2701 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd - 1); 2702 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2703 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2704 next_rxd = calc_next_rxd(fl, cidx); 2705 prefetch(next_rxd); 2706 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd - 1)]); 2707 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd - 1)]); 2708 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd - 1)]); 2709 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd - 1)]); 2710 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd - 1)]); 2711 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd - 1)]); 2712 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd - 1)]); 2713 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd - 1)]); 2714 } 2715 2716 static struct mbuf * 2717 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2718 int *pf_rv, if_rxd_info_t ri) 2719 { 2720 bus_dmamap_t map; 2721 iflib_fl_t fl; 2722 caddr_t payload; 2723 struct mbuf *m; 2724 int flid, cidx, len, next; 2725 2726 map = NULL; 2727 flid = irf->irf_flid; 2728 cidx = irf->irf_idx; 2729 fl = &rxq->ifr_fl[flid]; 2730 sd->ifsd_fl = fl; 2731 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2732 fl->ifl_credits--; 2733 #if MEMORY_LOGGING 2734 fl->ifl_m_dequeued++; 2735 #endif 2736 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2737 prefetch_pkts(fl, cidx); 2738 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size - 1); 2739 prefetch(&fl->ifl_sds.ifsd_map[next]); 2740 map = fl->ifl_sds.ifsd_map[cidx]; 2741 2742 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2743 2744 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2745 irf->irf_len != 0) { 2746 payload = *sd->ifsd_cl; 2747 payload += ri->iri_pad; 2748 len = ri->iri_len - ri->iri_pad; 2749 *pf_rv = pfil_mem_in(rxq->pfil, payload, len, ri->iri_ifp, &m); 2750 switch (*pf_rv) { 2751 case PFIL_DROPPED: 2752 case PFIL_CONSUMED: 2753 /* 2754 * The filter ate it. Everything is recycled. 2755 */ 2756 m = NULL; 2757 unload = 0; 2758 break; 2759 case PFIL_REALLOCED: 2760 /* 2761 * The filter copied it. Everything is recycled. 2762 * 'm' points at new mbuf. 2763 */ 2764 unload = 0; 2765 break; 2766 case PFIL_PASS: 2767 /* 2768 * Filter said it was OK, so receive like 2769 * normal 2770 */ 2771 m = fl->ifl_sds.ifsd_m[cidx]; 2772 fl->ifl_sds.ifsd_m[cidx] = NULL; 2773 break; 2774 default: 2775 MPASS(0); 2776 } 2777 } else { 2778 m = fl->ifl_sds.ifsd_m[cidx]; 2779 fl->ifl_sds.ifsd_m[cidx] = NULL; 2780 if (pf_rv != NULL) 2781 *pf_rv = PFIL_PASS; 2782 } 2783 2784 if (unload && irf->irf_len != 0) 2785 bus_dmamap_unload(fl->ifl_buf_tag, map); 2786 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size - 1); 2787 if (__predict_false(fl->ifl_cidx == 0)) 2788 fl->ifl_gen = 0; 2789 bit_clear(fl->ifl_rx_bitmap, cidx); 2790 return (m); 2791 } 2792 2793 static struct mbuf * 2794 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2795 { 2796 struct mbuf *m, *mh, *mt; 2797 caddr_t cl; 2798 int *pf_rv_ptr, flags, i, padlen; 2799 bool consumed; 2800 2801 i = 0; 2802 mh = NULL; 2803 consumed = false; 2804 *pf_rv = PFIL_PASS; 2805 pf_rv_ptr = pf_rv; 2806 do { 2807 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2808 pf_rv_ptr, ri); 2809 2810 MPASS(*sd->ifsd_cl != NULL); 2811 2812 /* 2813 * Exclude zero-length frags & frags from 2814 * packets the filter has consumed or dropped 2815 */ 2816 if (ri->iri_frags[i].irf_len == 0 || consumed || 2817 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2818 if (mh == NULL) { 2819 /* everything saved here */ 2820 consumed = true; 2821 pf_rv_ptr = NULL; 2822 continue; 2823 } 2824 /* XXX we can save the cluster here, but not the mbuf */ 2825 m_init(m, M_NOWAIT, MT_DATA, 0); 2826 m_free(m); 2827 continue; 2828 } 2829 if (mh == NULL) { 2830 flags = M_PKTHDR | M_EXT; 2831 mh = mt = m; 2832 padlen = ri->iri_pad; 2833 } else { 2834 flags = M_EXT; 2835 mt->m_next = m; 2836 mt = m; 2837 /* assuming padding is only on the first fragment */ 2838 padlen = 0; 2839 } 2840 cl = *sd->ifsd_cl; 2841 *sd->ifsd_cl = NULL; 2842 2843 /* Can these two be made one ? */ 2844 m_init(m, M_NOWAIT, MT_DATA, flags); 2845 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2846 /* 2847 * These must follow m_init and m_cljset 2848 */ 2849 m->m_data += padlen; 2850 ri->iri_len -= padlen; 2851 m->m_len = ri->iri_frags[i].irf_len; 2852 } while (++i < ri->iri_nfrags); 2853 2854 return (mh); 2855 } 2856 2857 /* 2858 * Process one software descriptor 2859 */ 2860 static struct mbuf * 2861 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2862 { 2863 struct if_rxsd sd; 2864 struct mbuf *m; 2865 int pf_rv; 2866 2867 /* should I merge this back in now that the two paths are basically duplicated? */ 2868 if (ri->iri_nfrags == 1 && 2869 ri->iri_frags[0].irf_len != 0 && 2870 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2871 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2872 &pf_rv, ri); 2873 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2874 return (m); 2875 if (pf_rv == PFIL_PASS) { 2876 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2877 #ifndef __NO_STRICT_ALIGNMENT 2878 if (!IP_ALIGNED(m) && ri->iri_pad == 0) 2879 m->m_data += 2; 2880 #endif 2881 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2882 m->m_len = ri->iri_frags[0].irf_len; 2883 m->m_data += ri->iri_pad; 2884 ri->iri_len -= ri->iri_pad; 2885 } 2886 } else { 2887 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2888 if (m == NULL) 2889 return (NULL); 2890 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2891 return (m); 2892 } 2893 m->m_pkthdr.len = ri->iri_len; 2894 m->m_pkthdr.rcvif = ri->iri_ifp; 2895 m->m_flags |= ri->iri_flags; 2896 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2897 m->m_pkthdr.flowid = ri->iri_flowid; 2898 #ifdef NUMA 2899 m->m_pkthdr.numa_domain = if_getnumadomain(ri->iri_ifp); 2900 #endif 2901 M_HASHTYPE_SET(m, ri->iri_rsstype); 2902 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2903 m->m_pkthdr.csum_data = ri->iri_csum_data; 2904 return (m); 2905 } 2906 2907 static void 2908 _task_fn_rx_watchdog(void *context) 2909 { 2910 iflib_rxq_t rxq = context; 2911 2912 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2913 } 2914 2915 static uint8_t 2916 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2917 { 2918 if_t ifp; 2919 if_ctx_t ctx = rxq->ifr_ctx; 2920 if_shared_ctx_t sctx = ctx->ifc_sctx; 2921 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2922 int avail, i; 2923 qidx_t *cidxp; 2924 struct if_rxd_info ri; 2925 int err, budget_left, rx_bytes, rx_pkts; 2926 iflib_fl_t fl; 2927 #if defined(INET6) || defined(INET) 2928 int lro_enabled; 2929 #endif 2930 uint8_t retval = 0; 2931 2932 /* 2933 * XXX early demux data packets so that if_input processing only handles 2934 * acks in interrupt context 2935 */ 2936 struct mbuf *m, *mh, *mt; 2937 2938 NET_EPOCH_ASSERT(); 2939 2940 ifp = ctx->ifc_ifp; 2941 mh = mt = NULL; 2942 MPASS(budget > 0); 2943 rx_pkts = rx_bytes = 0; 2944 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2945 cidxp = &rxq->ifr_cq_cidx; 2946 else 2947 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2948 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2949 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2950 retval |= iflib_fl_refill_all(ctx, fl); 2951 DBG_COUNTER_INC(rx_unavail); 2952 return (retval); 2953 } 2954 2955 #if defined(INET6) || defined(INET) 2956 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2957 #endif 2958 2959 /* pfil needs the vnet to be set */ 2960 CURVNET_SET_QUIET(if_getvnet(ifp)); 2961 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2962 if (__predict_false(!CTX_ACTIVE(ctx))) { 2963 DBG_COUNTER_INC(rx_ctx_inactive); 2964 break; 2965 } 2966 /* 2967 * Reset client set fields to their default values 2968 */ 2969 rxd_info_zero(&ri); 2970 ri.iri_qsidx = rxq->ifr_id; 2971 ri.iri_cidx = *cidxp; 2972 ri.iri_ifp = ifp; 2973 ri.iri_frags = rxq->ifr_frags; 2974 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2975 2976 if (err) 2977 goto err; 2978 rx_pkts += 1; 2979 rx_bytes += ri.iri_len; 2980 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2981 *cidxp = ri.iri_cidx; 2982 /* Update our consumer index */ 2983 /* XXX NB: shurd - check if this is still safe */ 2984 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2985 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2986 /* was this only a completion queue message? */ 2987 if (__predict_false(ri.iri_nfrags == 0)) 2988 continue; 2989 } 2990 MPASS(ri.iri_nfrags != 0); 2991 MPASS(ri.iri_len != 0); 2992 2993 /* will advance the cidx on the corresponding free lists */ 2994 m = iflib_rxd_pkt_get(rxq, &ri); 2995 avail--; 2996 budget_left--; 2997 if (avail == 0 && budget_left) 2998 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2999 3000 if (__predict_false(m == NULL)) 3001 continue; 3002 3003 #ifndef __NO_STRICT_ALIGNMENT 3004 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 3005 continue; 3006 #endif 3007 #if defined(INET6) || defined(INET) 3008 if (lro_enabled) { 3009 tcp_lro_queue_mbuf(&rxq->ifr_lc, m); 3010 continue; 3011 } 3012 #endif 3013 3014 if (mh == NULL) 3015 mh = mt = m; 3016 else { 3017 mt->m_nextpkt = m; 3018 mt = m; 3019 } 3020 } 3021 CURVNET_RESTORE(); 3022 /* make sure that we can refill faster than drain */ 3023 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3024 retval |= iflib_fl_refill_all(ctx, fl); 3025 3026 if (mh != NULL) { 3027 if_input(ifp, mh); 3028 DBG_COUNTER_INC(rx_if_input); 3029 } 3030 3031 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 3032 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 3033 3034 /* 3035 * Flush any outstanding LRO work 3036 */ 3037 #if defined(INET6) || defined(INET) 3038 tcp_lro_flush_all(&rxq->ifr_lc); 3039 #endif 3040 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 3041 retval |= IFLIB_RXEOF_MORE; 3042 return (retval); 3043 err: 3044 STATE_LOCK(ctx); 3045 ctx->ifc_flags |= IFC_DO_RESET; 3046 iflib_admin_intr_deferred(ctx); 3047 STATE_UNLOCK(ctx); 3048 return (0); 3049 } 3050 3051 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq) - 1) 3052 static inline qidx_t 3053 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 3054 { 3055 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3056 qidx_t minthresh = txq->ift_size / 8; 3057 if (in_use > 4 * minthresh) 3058 return (notify_count); 3059 if (in_use > 2 * minthresh) 3060 return (notify_count >> 1); 3061 if (in_use > minthresh) 3062 return (notify_count >> 3); 3063 return (0); 3064 } 3065 3066 static inline qidx_t 3067 txq_max_rs_deferred(iflib_txq_t txq) 3068 { 3069 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3070 qidx_t minthresh = txq->ift_size / 8; 3071 if (txq->ift_in_use > 4 * minthresh) 3072 return (notify_count); 3073 if (txq->ift_in_use > 2 * minthresh) 3074 return (notify_count >> 1); 3075 if (txq->ift_in_use > minthresh) 3076 return (notify_count >> 2); 3077 return (2); 3078 } 3079 3080 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 3081 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 3082 3083 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 3084 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 3085 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 3086 3087 /* forward compatibility for cxgb */ 3088 #define FIRST_QSET(ctx) 0 3089 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3090 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3091 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3092 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3093 3094 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3095 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3096 3097 static inline bool 3098 iflib_txd_db_check(iflib_txq_t txq, int ring) 3099 { 3100 if_ctx_t ctx = txq->ift_ctx; 3101 qidx_t dbval, max; 3102 3103 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use); 3104 3105 /* force || threshold exceeded || at the edge of the ring */ 3106 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx))) { 3107 3108 /* 3109 * 'npending' is used if the card's doorbell is in terms of the number of descriptors 3110 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the 3111 * producer index explicitly (INTC). 3112 */ 3113 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3114 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3115 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3116 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3117 3118 /* 3119 * Absent bugs there are zero packets pending so reset pending counts to zero. 3120 */ 3121 txq->ift_db_pending = txq->ift_npending = 0; 3122 return (true); 3123 } 3124 return (false); 3125 } 3126 3127 #ifdef PKT_DEBUG 3128 static void 3129 print_pkt(if_pkt_info_t pi) 3130 { 3131 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3132 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3133 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3134 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3135 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3136 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3137 } 3138 #endif 3139 3140 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3141 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3142 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3143 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3144 3145 /** 3146 * Parses out ethernet header information in the given mbuf. 3147 * Returns in pi: ipi_etype (EtherType) and ipi_ehdrlen (Ethernet header length) 3148 * 3149 * This will account for the VLAN header if present. 3150 * 3151 * XXX: This doesn't handle QinQ, which could prevent TX offloads for those 3152 * types of packets. 3153 */ 3154 static int 3155 iflib_parse_ether_header(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3156 { 3157 struct ether_vlan_header *eh; 3158 struct mbuf *m; 3159 3160 m = *mp; 3161 if (__predict_false(m->m_len < sizeof(*eh))) { 3162 (*pullups)++; 3163 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3164 return (ENOMEM); 3165 } 3166 eh = mtod(m, struct ether_vlan_header *); 3167 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3168 pi->ipi_etype = ntohs(eh->evl_proto); 3169 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3170 } else { 3171 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3172 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3173 } 3174 *mp = m; 3175 3176 return (0); 3177 } 3178 3179 /** 3180 * Parse up to the L3 header and extract IPv4/IPv6 header information into pi. 3181 * Currently this information includes: IP ToS value, IP header version/presence 3182 * 3183 * This is missing some checks and doesn't edit the packet content as it goes, 3184 * unlike iflib_parse_header(), in order to keep the amount of code here minimal. 3185 */ 3186 static int 3187 iflib_parse_header_partial(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3188 { 3189 struct mbuf *m; 3190 int err; 3191 3192 *pullups = 0; 3193 m = *mp; 3194 if (!M_WRITABLE(m)) { 3195 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3196 return (ENOMEM); 3197 } else { 3198 m_freem(*mp); 3199 DBG_COUNTER_INC(tx_frees); 3200 *mp = m; 3201 } 3202 } 3203 3204 /* Fills out pi->ipi_etype */ 3205 err = iflib_parse_ether_header(pi, mp, pullups); 3206 if (err) 3207 return (err); 3208 m = *mp; 3209 3210 switch (pi->ipi_etype) { 3211 #ifdef INET 3212 case ETHERTYPE_IP: 3213 { 3214 struct mbuf *n; 3215 struct ip *ip = NULL; 3216 int miniplen; 3217 3218 miniplen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip)); 3219 if (__predict_false(m->m_len < miniplen)) { 3220 /* 3221 * Check for common case where the first mbuf only contains 3222 * the Ethernet header 3223 */ 3224 if (m->m_len == pi->ipi_ehdrlen) { 3225 n = m->m_next; 3226 MPASS(n); 3227 /* If next mbuf contains at least the minimal IP header, then stop */ 3228 if (n->m_len >= sizeof(*ip)) { 3229 ip = (struct ip *)n->m_data; 3230 } else { 3231 (*pullups)++; 3232 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3233 return (ENOMEM); 3234 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3235 } 3236 } else { 3237 (*pullups)++; 3238 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3239 return (ENOMEM); 3240 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3241 } 3242 } else { 3243 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3244 } 3245 3246 /* Have the IPv4 header w/ no options here */ 3247 pi->ipi_ip_hlen = ip->ip_hl << 2; 3248 pi->ipi_ipproto = ip->ip_p; 3249 pi->ipi_ip_tos = ip->ip_tos; 3250 pi->ipi_flags |= IPI_TX_IPV4; 3251 3252 break; 3253 } 3254 #endif 3255 #ifdef INET6 3256 case ETHERTYPE_IPV6: 3257 { 3258 struct ip6_hdr *ip6; 3259 3260 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3261 (*pullups)++; 3262 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3263 return (ENOMEM); 3264 } 3265 ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3266 3267 /* Have the IPv6 fixed header here */ 3268 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3269 pi->ipi_ipproto = ip6->ip6_nxt; 3270 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3271 pi->ipi_flags |= IPI_TX_IPV6; 3272 3273 break; 3274 } 3275 #endif 3276 default: 3277 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3278 pi->ipi_ip_hlen = 0; 3279 break; 3280 } 3281 *mp = m; 3282 3283 return (0); 3284 3285 } 3286 3287 static int 3288 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3289 { 3290 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3291 struct mbuf *m; 3292 int err; 3293 3294 m = *mp; 3295 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3296 M_WRITABLE(m) == 0) { 3297 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3298 return (ENOMEM); 3299 } else { 3300 m_freem(*mp); 3301 DBG_COUNTER_INC(tx_frees); 3302 *mp = m; 3303 } 3304 } 3305 3306 /* Fills out pi->ipi_etype */ 3307 err = iflib_parse_ether_header(pi, mp, &txq->ift_pullups); 3308 if (__predict_false(err)) 3309 return (err); 3310 m = *mp; 3311 3312 switch (pi->ipi_etype) { 3313 #ifdef INET 3314 case ETHERTYPE_IP: 3315 { 3316 struct ip *ip; 3317 struct tcphdr *th; 3318 uint8_t hlen; 3319 3320 hlen = pi->ipi_ehdrlen + sizeof(*ip); 3321 if (__predict_false(m->m_len < hlen)) { 3322 txq->ift_pullups++; 3323 if (__predict_false((m = m_pullup(m, hlen)) == NULL)) 3324 return (ENOMEM); 3325 } 3326 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3327 hlen = pi->ipi_ehdrlen + (ip->ip_hl << 2); 3328 if (ip->ip_p == IPPROTO_TCP) { 3329 hlen += sizeof(*th); 3330 th = (struct tcphdr *)((char *)ip + (ip->ip_hl << 2)); 3331 } else if (ip->ip_p == IPPROTO_UDP) { 3332 hlen += sizeof(struct udphdr); 3333 } 3334 if (__predict_false(m->m_len < hlen)) { 3335 txq->ift_pullups++; 3336 if ((m = m_pullup(m, hlen)) == NULL) 3337 return (ENOMEM); 3338 } 3339 pi->ipi_ip_hlen = ip->ip_hl << 2; 3340 pi->ipi_ipproto = ip->ip_p; 3341 pi->ipi_ip_tos = ip->ip_tos; 3342 pi->ipi_flags |= IPI_TX_IPV4; 3343 3344 /* TCP checksum offload may require TCP header length */ 3345 if (IS_TX_OFFLOAD4(pi)) { 3346 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3347 pi->ipi_tcp_hflags = tcp_get_flags(th); 3348 pi->ipi_tcp_hlen = th->th_off << 2; 3349 pi->ipi_tcp_seq = th->th_seq; 3350 } 3351 if (IS_TSO4(pi)) { 3352 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3353 return (ENXIO); 3354 /* 3355 * TSO always requires hardware checksum offload. 3356 */ 3357 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3358 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3359 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3360 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3361 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3362 ip->ip_sum = 0; 3363 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3364 } 3365 } 3366 } 3367 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3368 ip->ip_sum = 0; 3369 3370 break; 3371 } 3372 #endif 3373 #ifdef INET6 3374 case ETHERTYPE_IPV6: 3375 { 3376 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3377 struct tcphdr *th; 3378 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3379 3380 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3381 txq->ift_pullups++; 3382 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3383 return (ENOMEM); 3384 } 3385 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3386 3387 /* XXX-BZ this will go badly in case of ext hdrs. */ 3388 pi->ipi_ipproto = ip6->ip6_nxt; 3389 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3390 pi->ipi_flags |= IPI_TX_IPV6; 3391 3392 /* TCP checksum offload may require TCP header length */ 3393 if (IS_TX_OFFLOAD6(pi)) { 3394 if (pi->ipi_ipproto == IPPROTO_TCP) { 3395 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3396 txq->ift_pullups++; 3397 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3398 return (ENOMEM); 3399 } 3400 pi->ipi_tcp_hflags = tcp_get_flags(th); 3401 pi->ipi_tcp_hlen = th->th_off << 2; 3402 pi->ipi_tcp_seq = th->th_seq; 3403 } 3404 if (IS_TSO6(pi)) { 3405 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3406 return (ENXIO); 3407 /* 3408 * TSO always requires hardware checksum offload. 3409 */ 3410 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3411 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3412 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3413 } 3414 } 3415 break; 3416 } 3417 #endif 3418 default: 3419 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3420 pi->ipi_ip_hlen = 0; 3421 break; 3422 } 3423 *mp = m; 3424 3425 return (0); 3426 } 3427 3428 /* 3429 * If dodgy hardware rejects the scatter gather chain we've handed it 3430 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3431 * m_defrag'd mbufs 3432 */ 3433 static __noinline struct mbuf * 3434 iflib_remove_mbuf(iflib_txq_t txq) 3435 { 3436 int ntxd, pidx; 3437 struct mbuf *m, **ifsd_m; 3438 3439 ifsd_m = txq->ift_sds.ifsd_m; 3440 ntxd = txq->ift_size; 3441 pidx = txq->ift_pidx & (ntxd - 1); 3442 ifsd_m = txq->ift_sds.ifsd_m; 3443 m = ifsd_m[pidx]; 3444 ifsd_m[pidx] = NULL; 3445 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3446 if (txq->ift_sds.ifsd_tso_map != NULL) 3447 bus_dmamap_unload(txq->ift_tso_buf_tag, 3448 txq->ift_sds.ifsd_tso_map[pidx]); 3449 #if MEMORY_LOGGING 3450 txq->ift_dequeued++; 3451 #endif 3452 return (m); 3453 } 3454 3455 /* 3456 * Pad an mbuf to ensure a minimum ethernet frame size. 3457 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3458 */ 3459 static __noinline int 3460 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3461 { 3462 /* 3463 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3464 * and ARP message is the smallest common payload I can think of 3465 */ 3466 static char pad[18]; /* just zeros */ 3467 int n; 3468 struct mbuf *new_head; 3469 3470 if (!M_WRITABLE(*m_head)) { 3471 new_head = m_dup(*m_head, M_NOWAIT); 3472 if (new_head == NULL) { 3473 m_freem(*m_head); 3474 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3475 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3476 DBG_COUNTER_INC(tx_frees); 3477 return (ENOMEM); 3478 } 3479 m_freem(*m_head); 3480 *m_head = new_head; 3481 } 3482 3483 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3484 n > 0; n -= sizeof(pad)) 3485 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3486 break; 3487 3488 if (n > 0) { 3489 m_freem(*m_head); 3490 device_printf(dev, "cannot pad short frame\n"); 3491 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3492 DBG_COUNTER_INC(tx_frees); 3493 return (ENOBUFS); 3494 } 3495 3496 return (0); 3497 } 3498 3499 static int 3500 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3501 { 3502 if_ctx_t ctx; 3503 if_shared_ctx_t sctx; 3504 if_softc_ctx_t scctx; 3505 bus_dma_tag_t buf_tag; 3506 bus_dma_segment_t *segs; 3507 struct mbuf *m_head, **ifsd_m; 3508 bus_dmamap_t map; 3509 struct if_pkt_info pi; 3510 int remap = 0; 3511 int err, nsegs, ndesc, max_segs, pidx; 3512 3513 ctx = txq->ift_ctx; 3514 sctx = ctx->ifc_sctx; 3515 scctx = &ctx->ifc_softc_ctx; 3516 segs = txq->ift_segs; 3517 m_head = *m_headp; 3518 map = NULL; 3519 3520 /* 3521 * If we're doing TSO the next descriptor to clean may be quite far ahead 3522 */ 3523 pidx = txq->ift_pidx; 3524 map = txq->ift_sds.ifsd_map[pidx]; 3525 ifsd_m = txq->ift_sds.ifsd_m; 3526 3527 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3528 buf_tag = txq->ift_tso_buf_tag; 3529 max_segs = scctx->isc_tx_tso_segments_max; 3530 map = txq->ift_sds.ifsd_tso_map[pidx]; 3531 MPASS(buf_tag != NULL); 3532 MPASS(max_segs > 0); 3533 } else { 3534 buf_tag = txq->ift_buf_tag; 3535 max_segs = scctx->isc_tx_nsegments; 3536 map = txq->ift_sds.ifsd_map[pidx]; 3537 } 3538 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3539 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3540 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3541 if (err) { 3542 DBG_COUNTER_INC(encap_txd_encap_fail); 3543 return (err); 3544 } 3545 } 3546 m_head = *m_headp; 3547 3548 pkt_info_zero(&pi); 3549 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG | M_BCAST | M_MCAST)); 3550 pi.ipi_pidx = pidx; 3551 pi.ipi_qsidx = txq->ift_id; 3552 pi.ipi_len = m_head->m_pkthdr.len; 3553 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3554 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3555 3556 /* deliberate bitwise OR to make one condition */ 3557 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3558 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3559 DBG_COUNTER_INC(encap_txd_encap_fail); 3560 return (err); 3561 } 3562 m_head = *m_headp; 3563 } 3564 3565 retry: 3566 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3567 BUS_DMA_NOWAIT); 3568 defrag: 3569 if (__predict_false(err)) { 3570 switch (err) { 3571 case EFBIG: 3572 /* try collapse once and defrag once */ 3573 if (remap == 0) { 3574 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3575 /* try defrag if collapsing fails */ 3576 if (m_head == NULL) 3577 remap++; 3578 } 3579 if (remap == 1) { 3580 txq->ift_mbuf_defrag++; 3581 m_head = m_defrag(*m_headp, M_NOWAIT); 3582 } 3583 /* 3584 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3585 * failed to map an mbuf that was run through m_defrag 3586 */ 3587 MPASS(remap <= 1); 3588 if (__predict_false(m_head == NULL || remap > 1)) 3589 goto defrag_failed; 3590 remap++; 3591 *m_headp = m_head; 3592 goto retry; 3593 break; 3594 case ENOMEM: 3595 txq->ift_no_tx_dma_setup++; 3596 break; 3597 default: 3598 txq->ift_no_tx_dma_setup++; 3599 m_freem(*m_headp); 3600 DBG_COUNTER_INC(tx_frees); 3601 *m_headp = NULL; 3602 break; 3603 } 3604 txq->ift_map_failed++; 3605 DBG_COUNTER_INC(encap_load_mbuf_fail); 3606 DBG_COUNTER_INC(encap_txd_encap_fail); 3607 return (err); 3608 } 3609 ifsd_m[pidx] = m_head; 3610 if (m_head->m_pkthdr.csum_flags & CSUM_SND_TAG) 3611 pi.ipi_mbuf = m_head; 3612 else 3613 pi.ipi_mbuf = NULL; 3614 /* 3615 * XXX assumes a 1 to 1 relationship between segments and 3616 * descriptors - this does not hold true on all drivers, e.g. 3617 * cxgb 3618 */ 3619 if (__predict_false(nsegs > TXQ_AVAIL(txq))) { 3620 (void)iflib_completed_tx_reclaim(txq); 3621 if (__predict_false(nsegs > TXQ_AVAIL(txq))) { 3622 txq->ift_no_desc_avail++; 3623 bus_dmamap_unload(buf_tag, map); 3624 DBG_COUNTER_INC(encap_txq_avail_fail); 3625 DBG_COUNTER_INC(encap_txd_encap_fail); 3626 if (ctx->ifc_sysctl_simple_tx) { 3627 *m_headp = m_head = iflib_remove_mbuf(txq); 3628 m_freem(*m_headp); 3629 DBG_COUNTER_INC(tx_frees); 3630 *m_headp = NULL; 3631 } 3632 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3633 GROUPTASK_ENQUEUE(&txq->ift_task); 3634 return (ENOBUFS); 3635 } 3636 } 3637 /* 3638 * On Intel cards we can greatly reduce the number of TX interrupts 3639 * we see by only setting report status on every Nth descriptor. 3640 * However, this also means that the driver will need to keep track 3641 * of the descriptors that RS was set on to check them for the DD bit. 3642 */ 3643 txq->ift_rs_pending += nsegs + 1; 3644 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3645 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx)) { 3646 pi.ipi_flags |= IPI_TX_INTR; 3647 txq->ift_rs_pending = 0; 3648 } 3649 3650 pi.ipi_segs = segs; 3651 pi.ipi_nsegs = nsegs; 3652 3653 MPASS(pidx >= 0 && pidx < txq->ift_size); 3654 #ifdef PKT_DEBUG 3655 print_pkt(&pi); 3656 #endif 3657 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3658 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3659 DBG_COUNTER_INC(tx_encap); 3660 MPASS(pi.ipi_new_pidx < txq->ift_size); 3661 3662 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3663 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3664 ndesc += txq->ift_size; 3665 txq->ift_gen = 1; 3666 } 3667 /* 3668 * drivers can need up to ift_pad sentinels 3669 */ 3670 MPASS(ndesc <= pi.ipi_nsegs + txq->ift_pad); 3671 MPASS(pi.ipi_new_pidx != pidx); 3672 MPASS(ndesc > 0); 3673 txq->ift_in_use += ndesc; 3674 txq->ift_db_pending += ndesc; 3675 3676 /* 3677 * We update the last software descriptor again here because there may 3678 * be a sentinel and/or there may be more mbufs than segments 3679 */ 3680 txq->ift_pidx = pi.ipi_new_pidx; 3681 txq->ift_npending += pi.ipi_ndescs; 3682 } else { 3683 *m_headp = m_head = iflib_remove_mbuf(txq); 3684 if (err == EFBIG) { 3685 txq->ift_txd_encap_efbig++; 3686 if (remap < 2) { 3687 remap = 1; 3688 goto defrag; 3689 } 3690 } 3691 goto defrag_failed; 3692 } 3693 /* 3694 * err can't possibly be non-zero here, so we don't neet to test it 3695 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3696 */ 3697 return (err); 3698 3699 defrag_failed: 3700 txq->ift_mbuf_defrag_failed++; 3701 txq->ift_map_failed++; 3702 m_freem(*m_headp); 3703 DBG_COUNTER_INC(tx_frees); 3704 *m_headp = NULL; 3705 DBG_COUNTER_INC(encap_txd_encap_fail); 3706 return (ENOMEM); 3707 } 3708 3709 static void 3710 iflib_tx_desc_free(iflib_txq_t txq, int n) 3711 { 3712 uint32_t qsize, cidx, gen; 3713 struct mbuf *m, **ifsd_m; 3714 3715 cidx = txq->ift_cidx; 3716 gen = txq->ift_gen; 3717 qsize = txq->ift_size; 3718 ifsd_m = txq->ift_sds.ifsd_m; 3719 3720 while (n-- > 0) { 3721 if ((m = ifsd_m[cidx]) != NULL) { 3722 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3723 bus_dmamap_sync(txq->ift_tso_buf_tag, 3724 txq->ift_sds.ifsd_tso_map[cidx], 3725 BUS_DMASYNC_POSTWRITE); 3726 bus_dmamap_unload(txq->ift_tso_buf_tag, 3727 txq->ift_sds.ifsd_tso_map[cidx]); 3728 } else { 3729 bus_dmamap_sync(txq->ift_buf_tag, 3730 txq->ift_sds.ifsd_map[cidx], 3731 BUS_DMASYNC_POSTWRITE); 3732 bus_dmamap_unload(txq->ift_buf_tag, 3733 txq->ift_sds.ifsd_map[cidx]); 3734 } 3735 /* XXX we don't support any drivers that batch packets yet */ 3736 MPASS(m->m_nextpkt == NULL); 3737 m_freem(m); 3738 ifsd_m[cidx] = NULL; 3739 #if MEMORY_LOGGING 3740 txq->ift_dequeued++; 3741 #endif 3742 DBG_COUNTER_INC(tx_frees); 3743 } 3744 if (__predict_false(++cidx == qsize)) { 3745 cidx = 0; 3746 gen = 0; 3747 } 3748 } 3749 txq->ift_cidx = cidx; 3750 txq->ift_gen = gen; 3751 } 3752 3753 static __inline int 3754 iflib_completed_tx_reclaim(iflib_txq_t txq) 3755 { 3756 int reclaim, thresh; 3757 uint32_t now; 3758 if_ctx_t ctx = txq->ift_ctx; 3759 3760 thresh = txq->ift_reclaim_thresh; 3761 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3762 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3763 3764 now = ticks; 3765 if (now <= (txq->ift_last_reclaim + txq->ift_reclaim_ticks) && 3766 txq->ift_in_use < thresh) 3767 return (0); 3768 txq->ift_last_reclaim = now; 3769 /* 3770 * Need a rate-limiting check so that this isn't called every time 3771 */ 3772 iflib_tx_credits_update(ctx, txq); 3773 reclaim = DESC_RECLAIMABLE(txq); 3774 3775 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3776 #ifdef INVARIANTS 3777 if (iflib_verbose_debug) { 3778 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __func__, 3779 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3780 reclaim, thresh); 3781 } 3782 #endif 3783 return (0); 3784 } 3785 iflib_tx_desc_free(txq, reclaim); 3786 txq->ift_cleaned += reclaim; 3787 txq->ift_in_use -= reclaim; 3788 3789 return (reclaim); 3790 } 3791 3792 static struct mbuf ** 3793 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3794 { 3795 int next, size; 3796 struct mbuf **items; 3797 3798 size = r->size; 3799 next = (cidx + CACHE_PTR_INCREMENT) & (size - 1); 3800 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3801 3802 prefetch(items[(cidx + offset) & (size - 1)]); 3803 if (remaining > 1) { 3804 prefetch2cachelines(&items[next]); 3805 prefetch2cachelines(items[(cidx + offset + 1) & (size - 1)]); 3806 prefetch2cachelines(items[(cidx + offset + 2) & (size - 1)]); 3807 prefetch2cachelines(items[(cidx + offset + 3) & (size - 1)]); 3808 } 3809 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size - 1)])); 3810 } 3811 3812 static void 3813 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3814 { 3815 3816 ifmp_ring_check_drainage(txq->ift_br, budget); 3817 } 3818 3819 static uint32_t 3820 iflib_txq_can_drain(struct ifmp_ring *r) 3821 { 3822 iflib_txq_t txq = r->cookie; 3823 if_ctx_t ctx = txq->ift_ctx; 3824 3825 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx)) 3826 return (1); 3827 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3828 BUS_DMASYNC_POSTREAD); 3829 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3830 false)); 3831 } 3832 3833 static uint32_t 3834 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3835 { 3836 iflib_txq_t txq = r->cookie; 3837 if_ctx_t ctx = txq->ift_ctx; 3838 if_t ifp = ctx->ifc_ifp; 3839 struct mbuf *m, **mp; 3840 int avail, bytes_sent, skipped, count, err, i; 3841 int mcast_sent, pkt_sent, reclaimed; 3842 bool do_prefetch, rang, ring; 3843 3844 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3845 !LINK_ACTIVE(ctx))) { 3846 DBG_COUNTER_INC(txq_drain_notready); 3847 return (0); 3848 } 3849 reclaimed = iflib_completed_tx_reclaim(txq); 3850 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending); 3851 avail = IDXDIFF(pidx, cidx, r->size); 3852 3853 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3854 /* 3855 * The driver is unloading so we need to free all pending packets. 3856 */ 3857 DBG_COUNTER_INC(txq_drain_flushing); 3858 for (i = 0; i < avail; i++) { 3859 if (__predict_true(r->items[(cidx + i) & (r->size - 1)] != (void *)txq)) 3860 m_freem(r->items[(cidx + i) & (r->size - 1)]); 3861 r->items[(cidx + i) & (r->size - 1)] = NULL; 3862 } 3863 return (avail); 3864 } 3865 3866 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3867 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3868 CALLOUT_LOCK(txq); 3869 callout_stop(&txq->ift_timer); 3870 CALLOUT_UNLOCK(txq); 3871 DBG_COUNTER_INC(txq_drain_oactive); 3872 return (0); 3873 } 3874 3875 /* 3876 * If we've reclaimed any packets this queue cannot be hung. 3877 */ 3878 if (reclaimed) 3879 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3880 skipped = mcast_sent = bytes_sent = pkt_sent = 0; 3881 count = MIN(avail, TX_BATCH_SIZE); 3882 #ifdef INVARIANTS 3883 if (iflib_verbose_debug) 3884 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __func__, 3885 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3886 #endif 3887 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3888 err = 0; 3889 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx); i++) { 3890 int rem = do_prefetch ? count - i : 0; 3891 3892 mp = _ring_peek_one(r, cidx, i, rem); 3893 MPASS(mp != NULL && *mp != NULL); 3894 3895 /* 3896 * Completion interrupts will use the address of the txq 3897 * as a sentinel to enqueue _something_ in order to acquire 3898 * the lock on the mp_ring (there's no direct lock call). 3899 * We obviously whave to check for these sentinel cases 3900 * and skip them. 3901 */ 3902 if (__predict_false(*mp == (struct mbuf *)txq)) { 3903 skipped++; 3904 continue; 3905 } 3906 err = iflib_encap(txq, mp); 3907 if (__predict_false(err)) { 3908 /* no room - bail out */ 3909 if (err == ENOBUFS) 3910 break; 3911 skipped++; 3912 /* we can't send this packet - skip it */ 3913 continue; 3914 } 3915 pkt_sent++; 3916 m = *mp; 3917 DBG_COUNTER_INC(tx_sent); 3918 bytes_sent += m->m_pkthdr.len; 3919 mcast_sent += !!(m->m_flags & M_MCAST); 3920 3921 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))) 3922 break; 3923 ETHER_BPF_MTAP(ifp, m); 3924 rang = iflib_txd_db_check(txq, false); 3925 } 3926 3927 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3928 ring = rang ? false : (iflib_min_tx_latency | err | (!!txq->ift_reclaim_thresh)); 3929 iflib_txd_db_check(txq, ring); 3930 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3931 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3932 if (mcast_sent) 3933 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3934 #ifdef INVARIANTS 3935 if (iflib_verbose_debug) 3936 printf("consumed=%d\n", skipped + pkt_sent); 3937 #endif 3938 return (skipped + pkt_sent); 3939 } 3940 3941 static uint32_t 3942 iflib_txq_drain_always(struct ifmp_ring *r) 3943 { 3944 return (1); 3945 } 3946 3947 static uint32_t 3948 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3949 { 3950 int i, avail; 3951 struct mbuf **mp; 3952 iflib_txq_t txq; 3953 3954 txq = r->cookie; 3955 3956 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3957 CALLOUT_LOCK(txq); 3958 callout_stop(&txq->ift_timer); 3959 CALLOUT_UNLOCK(txq); 3960 3961 avail = IDXDIFF(pidx, cidx, r->size); 3962 for (i = 0; i < avail; i++) { 3963 mp = _ring_peek_one(r, cidx, i, avail - i); 3964 if (__predict_false(*mp == (struct mbuf *)txq)) 3965 continue; 3966 m_freem(*mp); 3967 DBG_COUNTER_INC(tx_frees); 3968 } 3969 MPASS(ifmp_ring_is_stalled(r) == 0); 3970 return (avail); 3971 } 3972 3973 static void 3974 iflib_ifmp_purge(iflib_txq_t txq) 3975 { 3976 struct ifmp_ring *r; 3977 3978 r = txq->ift_br; 3979 r->drain = iflib_txq_drain_free; 3980 r->can_drain = iflib_txq_drain_always; 3981 3982 ifmp_ring_check_drainage(r, r->size); 3983 3984 r->drain = iflib_txq_drain; 3985 r->can_drain = iflib_txq_can_drain; 3986 } 3987 3988 static void 3989 _task_fn_tx(void *context) 3990 { 3991 iflib_txq_t txq = context; 3992 if_ctx_t ctx = txq->ift_ctx; 3993 if_t ifp = ctx->ifc_ifp; 3994 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3995 3996 #ifdef IFLIB_DIAGNOSTICS 3997 txq->ift_cpu_exec_count[curcpu]++; 3998 #endif 3999 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4000 return; 4001 #ifdef DEV_NETMAP 4002 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 4003 netmap_tx_irq(ifp, txq->ift_id)) 4004 goto skip_ifmp; 4005 #endif 4006 if (ctx->ifc_sysctl_simple_tx) { 4007 mtx_lock(&txq->ift_mtx); 4008 (void)iflib_completed_tx_reclaim(txq); 4009 mtx_unlock(&txq->ift_mtx); 4010 goto skip_ifmp; 4011 } 4012 #ifdef ALTQ 4013 if (if_altq_is_enabled(ifp)) 4014 iflib_altq_if_start(ifp); 4015 #endif 4016 if (txq->ift_db_pending) 4017 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 4018 else if (!abdicate) 4019 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4020 /* 4021 * When abdicating, we always need to check drainage, not just when we don't enqueue 4022 */ 4023 if (abdicate) 4024 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4025 4026 skip_ifmp: 4027 if (ctx->ifc_flags & IFC_LEGACY) 4028 IFDI_INTR_ENABLE(ctx); 4029 else 4030 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 4031 } 4032 4033 static void 4034 _task_fn_rx(void *context) 4035 { 4036 iflib_rxq_t rxq = context; 4037 if_ctx_t ctx = rxq->ifr_ctx; 4038 uint8_t more; 4039 uint16_t budget; 4040 #ifdef DEV_NETMAP 4041 u_int work = 0; 4042 int nmirq; 4043 #endif 4044 4045 #ifdef IFLIB_DIAGNOSTICS 4046 rxq->ifr_cpu_exec_count[curcpu]++; 4047 #endif 4048 DBG_COUNTER_INC(task_fn_rxs); 4049 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4050 return; 4051 #ifdef DEV_NETMAP 4052 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 4053 if (nmirq != NM_IRQ_PASS) { 4054 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 4055 goto skip_rxeof; 4056 } 4057 #endif 4058 budget = ctx->ifc_sysctl_rx_budget; 4059 if (budget == 0) 4060 budget = 16; /* XXX */ 4061 more = iflib_rxeof(rxq, budget); 4062 #ifdef DEV_NETMAP 4063 skip_rxeof: 4064 #endif 4065 if ((more & IFLIB_RXEOF_MORE) == 0) { 4066 if (ctx->ifc_flags & IFC_LEGACY) 4067 IFDI_INTR_ENABLE(ctx); 4068 else 4069 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 4070 DBG_COUNTER_INC(rx_intr_enables); 4071 } 4072 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4073 return; 4074 4075 if (more & IFLIB_RXEOF_MORE) 4076 GROUPTASK_ENQUEUE(&rxq->ifr_task); 4077 else if (more & IFLIB_RXEOF_EMPTY) 4078 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 4079 } 4080 4081 static void 4082 _task_fn_admin(void *context, int pending) 4083 { 4084 if_ctx_t ctx = context; 4085 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 4086 iflib_txq_t txq; 4087 int i; 4088 bool oactive, running, do_reset, do_watchdog, in_detach; 4089 4090 STATE_LOCK(ctx); 4091 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 4092 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 4093 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 4094 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 4095 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 4096 ctx->ifc_flags &= ~(IFC_DO_RESET | IFC_DO_WATCHDOG); 4097 STATE_UNLOCK(ctx); 4098 4099 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4100 return; 4101 if (in_detach) 4102 return; 4103 4104 CTX_LOCK(ctx); 4105 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4106 CALLOUT_LOCK(txq); 4107 callout_stop(&txq->ift_timer); 4108 CALLOUT_UNLOCK(txq); 4109 } 4110 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ) 4111 IFDI_ADMIN_COMPLETION_HANDLE(ctx); 4112 if (do_watchdog) { 4113 ctx->ifc_watchdog_events++; 4114 IFDI_WATCHDOG_RESET(ctx); 4115 } 4116 IFDI_UPDATE_ADMIN_STATUS(ctx); 4117 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4118 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 4119 txq->ift_timer.c_cpu); 4120 } 4121 IFDI_LINK_INTR_ENABLE(ctx); 4122 if (do_reset) 4123 iflib_if_init_locked(ctx); 4124 CTX_UNLOCK(ctx); 4125 4126 if (LINK_ACTIVE(ctx) == 0) 4127 return; 4128 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 4129 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4130 } 4131 4132 static void 4133 _task_fn_iov(void *context, int pending) 4134 { 4135 if_ctx_t ctx = context; 4136 4137 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 4138 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4139 return; 4140 4141 CTX_LOCK(ctx); 4142 IFDI_VFLR_HANDLE(ctx); 4143 CTX_UNLOCK(ctx); 4144 } 4145 4146 static int 4147 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4148 { 4149 int err; 4150 if_int_delay_info_t info; 4151 if_ctx_t ctx; 4152 4153 info = (if_int_delay_info_t)arg1; 4154 ctx = info->iidi_ctx; 4155 info->iidi_req = req; 4156 info->iidi_oidp = oidp; 4157 CTX_LOCK(ctx); 4158 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 4159 CTX_UNLOCK(ctx); 4160 return (err); 4161 } 4162 4163 /********************************************************************* 4164 * 4165 * IFNET FUNCTIONS 4166 * 4167 **********************************************************************/ 4168 4169 static void 4170 iflib_if_init_locked(if_ctx_t ctx) 4171 { 4172 iflib_stop(ctx); 4173 iflib_init_locked(ctx); 4174 } 4175 4176 static void 4177 iflib_if_init(void *arg) 4178 { 4179 if_ctx_t ctx = arg; 4180 4181 CTX_LOCK(ctx); 4182 iflib_if_init_locked(ctx); 4183 CTX_UNLOCK(ctx); 4184 } 4185 4186 static int 4187 iflib_if_transmit(if_t ifp, struct mbuf *m) 4188 { 4189 if_ctx_t ctx = if_getsoftc(ifp); 4190 iflib_txq_t txq; 4191 int err, qidx; 4192 int abdicate; 4193 4194 if (__predict_false((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 4195 DBG_COUNTER_INC(tx_frees); 4196 m_freem(m); 4197 return (ENETDOWN); 4198 } 4199 4200 MPASS(m->m_nextpkt == NULL); 4201 /* ALTQ-enabled interfaces always use queue 0. */ 4202 qidx = 0; 4203 /* Use driver-supplied queue selection method if it exists */ 4204 if (ctx->isc_txq_select_v2) { 4205 struct if_pkt_info pi; 4206 uint64_t early_pullups = 0; 4207 pkt_info_zero(&pi); 4208 4209 err = iflib_parse_header_partial(&pi, &m, &early_pullups); 4210 if (__predict_false(err != 0)) { 4211 /* Assign pullups for bad pkts to default queue */ 4212 ctx->ifc_txqs[0].ift_pullups += early_pullups; 4213 DBG_COUNTER_INC(encap_txd_encap_fail); 4214 return (err); 4215 } 4216 /* Let driver make queueing decision */ 4217 qidx = ctx->isc_txq_select_v2(ctx->ifc_softc, m, &pi); 4218 ctx->ifc_txqs[qidx].ift_pullups += early_pullups; 4219 } 4220 /* Backwards compatibility w/ simpler queue select */ 4221 else if (ctx->isc_txq_select) 4222 qidx = ctx->isc_txq_select(ctx->ifc_softc, m); 4223 /* If not, use iflib's standard method */ 4224 else if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !if_altq_is_enabled(ifp)) 4225 qidx = QIDX(ctx, m); 4226 4227 /* Set TX queue */ 4228 txq = &ctx->ifc_txqs[qidx]; 4229 4230 #ifdef DRIVER_BACKPRESSURE 4231 if (txq->ift_closed) { 4232 while (m != NULL) { 4233 next = m->m_nextpkt; 4234 m->m_nextpkt = NULL; 4235 m_freem(m); 4236 DBG_COUNTER_INC(tx_frees); 4237 m = next; 4238 } 4239 return (ENOBUFS); 4240 } 4241 #endif 4242 #ifdef notyet 4243 qidx = count = 0; 4244 mp = marr; 4245 next = m; 4246 do { 4247 count++; 4248 next = next->m_nextpkt; 4249 } while (next != NULL); 4250 4251 if (count > nitems(marr)) 4252 if ((mp = malloc(count * sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4253 /* XXX check nextpkt */ 4254 m_freem(m); 4255 /* XXX simplify for now */ 4256 DBG_COUNTER_INC(tx_frees); 4257 return (ENOBUFS); 4258 } 4259 for (next = m, i = 0; next != NULL; i++) { 4260 mp[i] = next; 4261 next = next->m_nextpkt; 4262 mp[i]->m_nextpkt = NULL; 4263 } 4264 #endif 4265 DBG_COUNTER_INC(tx_seen); 4266 abdicate = ctx->ifc_sysctl_tx_abdicate; 4267 4268 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4269 4270 if (abdicate) 4271 GROUPTASK_ENQUEUE(&txq->ift_task); 4272 if (err) { 4273 if (!abdicate) 4274 GROUPTASK_ENQUEUE(&txq->ift_task); 4275 /* support forthcoming later */ 4276 #ifdef DRIVER_BACKPRESSURE 4277 txq->ift_closed = TRUE; 4278 #endif 4279 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4280 m_freem(m); 4281 DBG_COUNTER_INC(tx_frees); 4282 if (err == ENOBUFS) 4283 if_inc_counter(ifp, IFCOUNTER_OQDROPS, 1); 4284 else 4285 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 4286 } 4287 4288 return (err); 4289 } 4290 4291 #ifdef ALTQ 4292 /* 4293 * The overall approach to integrating iflib with ALTQ is to continue to use 4294 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4295 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4296 * is redundant/unnecessary, but doing so minimizes the amount of 4297 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4298 * redundantly queueing to an intermediate mp_ring is swamped by the 4299 * performance limitations inherent in using ALTQ. 4300 * 4301 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4302 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4303 * given interface. If ALTQ is enabled for an interface, then all 4304 * transmitted packets for that interface will be submitted to the ALTQ 4305 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4306 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4307 * update stats that the iflib machinery handles, and which is sensitve to 4308 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4309 * will be installed as the start routine for use by ALTQ facilities that 4310 * need to trigger queue drains on a scheduled basis. 4311 * 4312 */ 4313 static void 4314 iflib_altq_if_start(if_t ifp) 4315 { 4316 struct ifaltq *ifq = &ifp->if_snd; /* XXX - DRVAPI */ 4317 struct mbuf *m; 4318 4319 IFQ_LOCK(ifq); 4320 IFQ_DEQUEUE_NOLOCK(ifq, m); 4321 while (m != NULL) { 4322 iflib_if_transmit(ifp, m); 4323 IFQ_DEQUEUE_NOLOCK(ifq, m); 4324 } 4325 IFQ_UNLOCK(ifq); 4326 } 4327 4328 static int 4329 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4330 { 4331 int err; 4332 4333 if (if_altq_is_enabled(ifp)) { 4334 IFQ_ENQUEUE(&ifp->if_snd, m, err); /* XXX - DRVAPI */ 4335 if (err == 0) 4336 iflib_altq_if_start(ifp); 4337 } else 4338 err = iflib_if_transmit(ifp, m); 4339 4340 return (err); 4341 } 4342 #endif /* ALTQ */ 4343 4344 static void 4345 iflib_if_qflush(if_t ifp) 4346 { 4347 if_ctx_t ctx = if_getsoftc(ifp); 4348 iflib_txq_t txq = ctx->ifc_txqs; 4349 int i; 4350 4351 STATE_LOCK(ctx); 4352 ctx->ifc_flags |= IFC_QFLUSH; 4353 STATE_UNLOCK(ctx); 4354 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4355 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4356 iflib_txq_check_drain(txq, 0); 4357 STATE_LOCK(ctx); 4358 ctx->ifc_flags &= ~IFC_QFLUSH; 4359 STATE_UNLOCK(ctx); 4360 4361 /* 4362 * When ALTQ is enabled, this will also take care of purging the 4363 * ALTQ queue(s). 4364 */ 4365 if_qflush(ifp); 4366 } 4367 4368 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4369 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4370 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4371 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG) 4372 4373 static int 4374 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4375 { 4376 if_ctx_t ctx = if_getsoftc(ifp); 4377 struct ifreq *ifr = (struct ifreq *)data; 4378 #if defined(INET) || defined(INET6) 4379 struct ifaddr *ifa = (struct ifaddr *)data; 4380 #endif 4381 bool avoid_reset = false; 4382 int err = 0, reinit = 0, bits; 4383 4384 switch (command) { 4385 case SIOCSIFADDR: 4386 #ifdef INET 4387 if (ifa->ifa_addr->sa_family == AF_INET) 4388 avoid_reset = true; 4389 #endif 4390 #ifdef INET6 4391 if (ifa->ifa_addr->sa_family == AF_INET6) 4392 avoid_reset = true; 4393 #endif 4394 /* 4395 * Calling init results in link renegotiation, 4396 * so we avoid doing it when possible. 4397 */ 4398 if (avoid_reset) { 4399 if_setflagbits(ifp, IFF_UP, 0); 4400 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4401 reinit = 1; 4402 #ifdef INET 4403 if (!(if_getflags(ifp) & IFF_NOARP)) 4404 arp_ifinit(ifp, ifa); 4405 #endif 4406 } else 4407 err = ether_ioctl(ifp, command, data); 4408 break; 4409 case SIOCSIFMTU: 4410 CTX_LOCK(ctx); 4411 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4412 CTX_UNLOCK(ctx); 4413 break; 4414 } 4415 bits = if_getdrvflags(ifp); 4416 /* stop the driver and free any clusters before proceeding */ 4417 iflib_stop(ctx); 4418 4419 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4420 STATE_LOCK(ctx); 4421 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4422 ctx->ifc_flags |= IFC_MULTISEG; 4423 else 4424 ctx->ifc_flags &= ~IFC_MULTISEG; 4425 STATE_UNLOCK(ctx); 4426 err = if_setmtu(ifp, ifr->ifr_mtu); 4427 } 4428 iflib_init_locked(ctx); 4429 STATE_LOCK(ctx); 4430 if_setdrvflags(ifp, bits); 4431 STATE_UNLOCK(ctx); 4432 CTX_UNLOCK(ctx); 4433 break; 4434 case SIOCSIFFLAGS: 4435 CTX_LOCK(ctx); 4436 if (if_getflags(ifp) & IFF_UP) { 4437 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4438 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4439 (IFF_PROMISC | IFF_ALLMULTI)) { 4440 CTX_UNLOCK(ctx); 4441 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4442 CTX_LOCK(ctx); 4443 } 4444 } else 4445 reinit = 1; 4446 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4447 iflib_stop(ctx); 4448 } 4449 ctx->ifc_if_flags = if_getflags(ifp); 4450 CTX_UNLOCK(ctx); 4451 break; 4452 case SIOCADDMULTI: 4453 case SIOCDELMULTI: 4454 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4455 CTX_LOCK(ctx); 4456 IFDI_INTR_DISABLE(ctx); 4457 IFDI_MULTI_SET(ctx); 4458 IFDI_INTR_ENABLE(ctx); 4459 CTX_UNLOCK(ctx); 4460 } 4461 break; 4462 case SIOCSIFMEDIA: 4463 CTX_LOCK(ctx); 4464 IFDI_MEDIA_SET(ctx); 4465 CTX_UNLOCK(ctx); 4466 /* FALLTHROUGH */ 4467 case SIOCGIFMEDIA: 4468 case SIOCGIFXMEDIA: 4469 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4470 break; 4471 case SIOCGI2C: 4472 { 4473 struct ifi2creq i2c; 4474 4475 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4476 if (err != 0) 4477 break; 4478 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4479 err = EINVAL; 4480 break; 4481 } 4482 if (i2c.len > sizeof(i2c.data)) { 4483 err = EINVAL; 4484 break; 4485 } 4486 4487 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4488 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4489 sizeof(i2c)); 4490 break; 4491 } 4492 case SIOCSIFCAP: 4493 { 4494 int mask, setmask, oldmask; 4495 4496 oldmask = if_getcapenable(ifp); 4497 mask = ifr->ifr_reqcap ^ oldmask; 4498 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG; 4499 setmask = 0; 4500 #ifdef TCP_OFFLOAD 4501 setmask |= mask & (IFCAP_TOE4 | IFCAP_TOE6); 4502 #endif 4503 setmask |= (mask & IFCAP_FLAGS); 4504 setmask |= (mask & IFCAP_WOL); 4505 4506 /* 4507 * If any RX csum has changed, change all the ones that 4508 * are supported by the driver. 4509 */ 4510 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4511 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4512 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4513 } 4514 4515 /* 4516 * want to ensure that traffic has stopped before we change any of the flags 4517 */ 4518 if (setmask) { 4519 CTX_LOCK(ctx); 4520 bits = if_getdrvflags(ifp); 4521 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4522 iflib_stop(ctx); 4523 STATE_LOCK(ctx); 4524 if_togglecapenable(ifp, setmask); 4525 ctx->ifc_softc_ctx.isc_capenable ^= setmask; 4526 STATE_UNLOCK(ctx); 4527 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4528 iflib_init_locked(ctx); 4529 STATE_LOCK(ctx); 4530 if_setdrvflags(ifp, bits); 4531 STATE_UNLOCK(ctx); 4532 CTX_UNLOCK(ctx); 4533 } 4534 if_vlancap(ifp); 4535 break; 4536 } 4537 case SIOCGPRIVATE_0: 4538 case SIOCSDRVSPEC: 4539 case SIOCGDRVSPEC: 4540 CTX_LOCK(ctx); 4541 err = IFDI_PRIV_IOCTL(ctx, command, data); 4542 CTX_UNLOCK(ctx); 4543 break; 4544 default: 4545 err = ether_ioctl(ifp, command, data); 4546 break; 4547 } 4548 if (reinit) 4549 iflib_if_init(ctx); 4550 return (err); 4551 } 4552 4553 static uint64_t 4554 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4555 { 4556 if_ctx_t ctx = if_getsoftc(ifp); 4557 4558 return (IFDI_GET_COUNTER(ctx, cnt)); 4559 } 4560 4561 /********************************************************************* 4562 * 4563 * OTHER FUNCTIONS EXPORTED TO THE STACK 4564 * 4565 **********************************************************************/ 4566 4567 static void 4568 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4569 { 4570 if_ctx_t ctx = if_getsoftc(ifp); 4571 4572 if ((void *)ctx != arg) 4573 return; 4574 4575 if ((vtag == 0) || (vtag > 4095)) 4576 return; 4577 4578 if (iflib_in_detach(ctx)) 4579 return; 4580 4581 CTX_LOCK(ctx); 4582 /* Driver may need all untagged packets to be flushed */ 4583 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4584 iflib_stop(ctx); 4585 IFDI_VLAN_REGISTER(ctx, vtag); 4586 /* Re-init to load the changes, if required */ 4587 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4588 iflib_init_locked(ctx); 4589 CTX_UNLOCK(ctx); 4590 } 4591 4592 static void 4593 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4594 { 4595 if_ctx_t ctx = if_getsoftc(ifp); 4596 4597 if ((void *)ctx != arg) 4598 return; 4599 4600 if ((vtag == 0) || (vtag > 4095)) 4601 return; 4602 4603 CTX_LOCK(ctx); 4604 /* Driver may need all tagged packets to be flushed */ 4605 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4606 iflib_stop(ctx); 4607 IFDI_VLAN_UNREGISTER(ctx, vtag); 4608 /* Re-init to load the changes, if required */ 4609 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4610 iflib_init_locked(ctx); 4611 CTX_UNLOCK(ctx); 4612 } 4613 4614 static void 4615 iflib_led_func(void *arg, int onoff) 4616 { 4617 if_ctx_t ctx = arg; 4618 4619 CTX_LOCK(ctx); 4620 IFDI_LED_FUNC(ctx, onoff); 4621 CTX_UNLOCK(ctx); 4622 } 4623 4624 /********************************************************************* 4625 * 4626 * BUS FUNCTION DEFINITIONS 4627 * 4628 **********************************************************************/ 4629 4630 int 4631 iflib_device_probe(device_t dev) 4632 { 4633 const pci_vendor_info_t *ent; 4634 if_shared_ctx_t sctx; 4635 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4636 uint16_t pci_vendor_id; 4637 4638 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4639 return (ENOTSUP); 4640 4641 pci_vendor_id = pci_get_vendor(dev); 4642 pci_device_id = pci_get_device(dev); 4643 pci_subvendor_id = pci_get_subvendor(dev); 4644 pci_subdevice_id = pci_get_subdevice(dev); 4645 pci_rev_id = pci_get_revid(dev); 4646 if (sctx->isc_parse_devinfo != NULL) 4647 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4648 4649 ent = sctx->isc_vendor_info; 4650 while (ent->pvi_vendor_id != 0) { 4651 if (pci_vendor_id != ent->pvi_vendor_id) { 4652 ent++; 4653 continue; 4654 } 4655 if ((pci_device_id == ent->pvi_device_id) && 4656 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4657 (ent->pvi_subvendor_id == 0)) && 4658 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4659 (ent->pvi_subdevice_id == 0)) && 4660 ((pci_rev_id == ent->pvi_rev_id) || 4661 (ent->pvi_rev_id == 0))) { 4662 device_set_desc_copy(dev, ent->pvi_name); 4663 /* this needs to be changed to zero if the bus probing code 4664 * ever stops re-probing on best match because the sctx 4665 * may have its values over written by register calls 4666 * in subsequent probes 4667 */ 4668 return (BUS_PROBE_DEFAULT); 4669 } 4670 ent++; 4671 } 4672 return (ENXIO); 4673 } 4674 4675 int 4676 iflib_device_probe_vendor(device_t dev) 4677 { 4678 int probe; 4679 4680 probe = iflib_device_probe(dev); 4681 if (probe == BUS_PROBE_DEFAULT) 4682 return (BUS_PROBE_VENDOR); 4683 else 4684 return (probe); 4685 } 4686 4687 static void 4688 iflib_reset_qvalues(if_ctx_t ctx) 4689 { 4690 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4691 if_shared_ctx_t sctx = ctx->ifc_sctx; 4692 device_t dev = ctx->ifc_dev; 4693 int i; 4694 4695 if (ctx->ifc_sysctl_ntxqs != 0) 4696 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4697 if (ctx->ifc_sysctl_nrxqs != 0) 4698 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4699 4700 for (i = 0; i < sctx->isc_ntxqs; i++) { 4701 if (ctx->ifc_sysctl_ntxds[i] != 0) 4702 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4703 else 4704 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4705 } 4706 4707 for (i = 0; i < sctx->isc_nrxqs; i++) { 4708 if (ctx->ifc_sysctl_nrxds[i] != 0) 4709 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4710 else 4711 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4712 } 4713 4714 for (i = 0; i < sctx->isc_nrxqs; i++) { 4715 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4716 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4717 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4718 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4719 } 4720 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4721 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4722 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4723 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4724 } 4725 if (!powerof2(scctx->isc_nrxd[i])) { 4726 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4727 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4728 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4729 } 4730 } 4731 4732 for (i = 0; i < sctx->isc_ntxqs; i++) { 4733 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4734 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4735 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4736 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4737 } 4738 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4739 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4740 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4741 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4742 } 4743 if (!powerof2(scctx->isc_ntxd[i])) { 4744 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4745 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4746 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4747 } 4748 } 4749 scctx->isc_tx_pad = 2; 4750 } 4751 4752 static void 4753 iflib_add_pfil(if_ctx_t ctx) 4754 { 4755 struct pfil_head *pfil; 4756 struct pfil_head_args pa; 4757 iflib_rxq_t rxq; 4758 int i; 4759 4760 pa.pa_version = PFIL_VERSION; 4761 pa.pa_flags = PFIL_IN; 4762 pa.pa_type = PFIL_TYPE_ETHERNET; 4763 pa.pa_headname = if_name(ctx->ifc_ifp); 4764 pfil = pfil_head_register(&pa); 4765 4766 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4767 rxq->pfil = pfil; 4768 } 4769 } 4770 4771 static void 4772 iflib_rem_pfil(if_ctx_t ctx) 4773 { 4774 struct pfil_head *pfil; 4775 iflib_rxq_t rxq; 4776 int i; 4777 4778 rxq = ctx->ifc_rxqs; 4779 pfil = rxq->pfil; 4780 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4781 rxq->pfil = NULL; 4782 } 4783 pfil_head_unregister(pfil); 4784 } 4785 4786 4787 /* 4788 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from 4789 * cpuid and wrapping as necessary. 4790 */ 4791 static unsigned int 4792 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n) 4793 { 4794 unsigned int first_valid; 4795 unsigned int last_valid; 4796 4797 /* cpuid should always be in the valid set */ 4798 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4799 4800 /* valid set should never be empty */ 4801 MPASS(!CPU_EMPTY(&ctx->ifc_cpus)); 4802 4803 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4804 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4805 n = n % CPU_COUNT(&ctx->ifc_cpus); 4806 while (n > 0) { 4807 do { 4808 cpuid++; 4809 if (cpuid > last_valid) 4810 cpuid = first_valid; 4811 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4812 n--; 4813 } 4814 4815 return (cpuid); 4816 } 4817 4818 #if defined(SMP) && defined(SCHED_ULE) 4819 extern struct cpu_group *cpu_top; /* CPU topology */ 4820 4821 static int 4822 find_child_with_core(int cpu, struct cpu_group *grp) 4823 { 4824 int i; 4825 4826 if (grp->cg_children == 0) 4827 return (-1); 4828 4829 MPASS(grp->cg_child); 4830 for (i = 0; i < grp->cg_children; i++) { 4831 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 4832 return (i); 4833 } 4834 4835 return (-1); 4836 } 4837 4838 4839 /* 4840 * Find an L2 neighbor of the given CPU or return -1 if none found. This 4841 * does not distinguish among multiple L2 neighbors if the given CPU has 4842 * more than one (it will always return the same result in that case). 4843 */ 4844 static int 4845 find_l2_neighbor(int cpu) 4846 { 4847 struct cpu_group *grp; 4848 int i; 4849 4850 grp = cpu_top; 4851 if (grp == NULL) 4852 return (-1); 4853 4854 /* 4855 * Find the smallest CPU group that contains the given core. 4856 */ 4857 i = 0; 4858 while ((i = find_child_with_core(cpu, grp)) != -1) { 4859 /* 4860 * If the smallest group containing the given CPU has less 4861 * than two members, we conclude the given CPU has no 4862 * L2 neighbor. 4863 */ 4864 if (grp->cg_child[i].cg_count <= 1) 4865 return (-1); 4866 grp = &grp->cg_child[i]; 4867 } 4868 4869 /* Must share L2. */ 4870 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 4871 return (-1); 4872 4873 /* 4874 * Select the first member of the set that isn't the reference 4875 * CPU, which at this point is guaranteed to exist. 4876 */ 4877 for (i = 0; i < CPU_SETSIZE; i++) { 4878 if (CPU_ISSET(i, &grp->cg_mask) && i != cpu) 4879 return (i); 4880 } 4881 4882 /* Should never be reached */ 4883 return (-1); 4884 } 4885 4886 #else 4887 static int 4888 find_l2_neighbor(int cpu) 4889 { 4890 4891 return (-1); 4892 } 4893 #endif 4894 4895 /* 4896 * CPU mapping behaviors 4897 * --------------------- 4898 * 'separate txrx' refers to the separate_txrx sysctl 4899 * 'use logical' refers to the use_logical_cores sysctl 4900 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded 4901 * 4902 * separate use INTR 4903 * txrx logical CPUS result 4904 * ---------- --------- ------ ------------------------------------------------ 4905 * - - X RX and TX queues mapped to consecutive physical 4906 * cores with RX/TX pairs on same core and excess 4907 * of either following 4908 * - X X RX and TX queues mapped to consecutive cores 4909 * of any type with RX/TX pairs on same core and 4910 * excess of either following 4911 * X - X RX and TX queues mapped to consecutive physical 4912 * cores; all RX then all TX 4913 * X X X RX queues mapped to consecutive physical cores 4914 * first, then TX queues mapped to L2 neighbor of 4915 * the corresponding RX queue if one exists, 4916 * otherwise to consecutive physical cores 4917 * - n/a - RX and TX queues mapped to consecutive cores of 4918 * any type with RX/TX pairs on same core and excess 4919 * of either following 4920 * X n/a - RX and TX queues mapped to consecutive cores of 4921 * any type; all RX then all TX 4922 */ 4923 static unsigned int 4924 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid, 4925 bool is_tx) 4926 { 4927 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4928 unsigned int core_index; 4929 4930 if (ctx->ifc_sysctl_separate_txrx) { 4931 /* 4932 * When using separate CPUs for TX and RX, the assignment 4933 * will always be of a consecutive CPU out of the set of 4934 * context CPUs, except for the specific case where the 4935 * context CPUs are phsyical cores, the use of logical cores 4936 * has been enabled, the assignment is for TX, the TX qid 4937 * corresponds to an RX qid, and the CPU assigned to the 4938 * corresponding RX queue has an L2 neighbor. 4939 */ 4940 if (ctx->ifc_sysctl_use_logical_cores && 4941 ctx->ifc_cpus_are_physical_cores && 4942 is_tx && qid < scctx->isc_nrxqsets) { 4943 int l2_neighbor; 4944 unsigned int rx_cpuid; 4945 4946 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid); 4947 l2_neighbor = find_l2_neighbor(rx_cpuid); 4948 if (l2_neighbor != -1) { 4949 return (l2_neighbor); 4950 } 4951 /* 4952 * ... else fall through to the normal 4953 * consecutive-after-RX assignment scheme. 4954 * 4955 * Note that we are assuming that all RX queue CPUs 4956 * have an L2 neighbor, or all do not. If a mixed 4957 * scenario is possible, we will have to keep track 4958 * separately of how many queues prior to this one 4959 * were not able to be assigned to an L2 neighbor. 4960 */ 4961 } 4962 if (is_tx) 4963 core_index = scctx->isc_nrxqsets + qid; 4964 else 4965 core_index = qid; 4966 } else { 4967 core_index = qid; 4968 } 4969 4970 return (cpuid_advance(ctx, base_cpuid, core_index)); 4971 } 4972 4973 static uint16_t 4974 get_ctx_core_offset(if_ctx_t ctx) 4975 { 4976 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4977 struct cpu_offset *op; 4978 cpuset_t assigned_cpus; 4979 unsigned int cores_consumed; 4980 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset; 4981 unsigned int first_valid; 4982 unsigned int last_valid; 4983 unsigned int i; 4984 4985 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4986 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4987 4988 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) { 4989 /* 4990 * Align the user-chosen base CPU ID to the next valid CPU 4991 * for this device. If the chosen base CPU ID is smaller 4992 * than the first valid CPU or larger than the last valid 4993 * CPU, we assume the user does not know what the valid 4994 * range is for this device and is thinking in terms of a 4995 * zero-based reference frame, and so we shift the given 4996 * value into the valid range (and wrap accordingly) so the 4997 * intent is translated to the proper frame of reference. 4998 * If the base CPU ID is within the valid first/last, but 4999 * does not correspond to a valid CPU, it is advanced to the 5000 * next valid CPU (wrapping if necessary). 5001 */ 5002 if (base_cpuid < first_valid || base_cpuid > last_valid) { 5003 /* shift from zero-based to first_valid-based */ 5004 base_cpuid += first_valid; 5005 /* wrap to range [first_valid, last_valid] */ 5006 base_cpuid = (base_cpuid - first_valid) % 5007 (last_valid - first_valid + 1); 5008 } 5009 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) { 5010 /* 5011 * base_cpuid is in [first_valid, last_valid], but 5012 * not a member of the valid set. In this case, 5013 * there will always be a member of the valid set 5014 * with a CPU ID that is greater than base_cpuid, 5015 * and we simply advance to it. 5016 */ 5017 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) 5018 base_cpuid++; 5019 } 5020 return (base_cpuid); 5021 } 5022 5023 /* 5024 * Determine how many cores will be consumed by performing the CPU 5025 * assignments and counting how many of the assigned CPUs correspond 5026 * to CPUs in the set of context CPUs. This is done using the CPU 5027 * ID first_valid as the base CPU ID, as the base CPU must be within 5028 * the set of context CPUs. 5029 * 5030 * Note not all assigned CPUs will be in the set of context CPUs 5031 * when separate CPUs are being allocated to TX and RX queues, 5032 * assignment to logical cores has been enabled, the set of context 5033 * CPUs contains only physical CPUs, and TX queues are mapped to L2 5034 * neighbors of CPUs that RX queues have been mapped to - in this 5035 * case we do only want to count how many CPUs in the set of context 5036 * CPUs have been consumed, as that determines the next CPU in that 5037 * set to start allocating at for the next device for which 5038 * core_offset is not set. 5039 */ 5040 CPU_ZERO(&assigned_cpus); 5041 for (i = 0; i < scctx->isc_ntxqsets; i++) 5042 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true), 5043 &assigned_cpus); 5044 for (i = 0; i < scctx->isc_nrxqsets; i++) 5045 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false), 5046 &assigned_cpus); 5047 CPU_AND(&assigned_cpus, &assigned_cpus, &ctx->ifc_cpus); 5048 cores_consumed = CPU_COUNT(&assigned_cpus); 5049 5050 mtx_lock(&cpu_offset_mtx); 5051 SLIST_FOREACH(op, &cpu_offsets, entries) { 5052 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5053 base_cpuid = op->next_cpuid; 5054 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid, 5055 cores_consumed); 5056 MPASS(op->refcount < UINT_MAX); 5057 op->refcount++; 5058 break; 5059 } 5060 } 5061 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) { 5062 base_cpuid = first_valid; 5063 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 5064 M_NOWAIT | M_ZERO); 5065 if (op == NULL) { 5066 device_printf(ctx->ifc_dev, 5067 "allocation for cpu offset failed.\n"); 5068 } else { 5069 op->next_cpuid = cpuid_advance(ctx, base_cpuid, 5070 cores_consumed); 5071 op->refcount = 1; 5072 CPU_COPY(&ctx->ifc_cpus, &op->set); 5073 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 5074 } 5075 } 5076 mtx_unlock(&cpu_offset_mtx); 5077 5078 return (base_cpuid); 5079 } 5080 5081 static void 5082 unref_ctx_core_offset(if_ctx_t ctx) 5083 { 5084 struct cpu_offset *op, *top; 5085 5086 mtx_lock(&cpu_offset_mtx); 5087 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 5088 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5089 MPASS(op->refcount > 0); 5090 op->refcount--; 5091 if (op->refcount == 0) { 5092 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 5093 free(op, M_IFLIB); 5094 } 5095 break; 5096 } 5097 } 5098 mtx_unlock(&cpu_offset_mtx); 5099 } 5100 5101 int 5102 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 5103 { 5104 if_ctx_t ctx; 5105 if_t ifp; 5106 if_softc_ctx_t scctx; 5107 kobjop_desc_t kobj_desc; 5108 kobj_method_t *kobj_method; 5109 int err, msix, rid; 5110 int num_txd, num_rxd; 5111 char namebuf[TASKQUEUE_NAMELEN]; 5112 5113 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK | M_ZERO); 5114 5115 if (sc == NULL) { 5116 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK | M_ZERO); 5117 device_set_softc(dev, ctx); 5118 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5119 } 5120 5121 ctx->ifc_sctx = sctx; 5122 ctx->ifc_dev = dev; 5123 ctx->ifc_softc = sc; 5124 5125 iflib_register(ctx); 5126 iflib_add_device_sysctl_pre(ctx); 5127 5128 scctx = &ctx->ifc_softc_ctx; 5129 ifp = ctx->ifc_ifp; 5130 if (ctx->ifc_sysctl_simple_tx) { 5131 #ifndef ALTQ 5132 if_settransmitfn(ifp, iflib_simple_transmit); 5133 device_printf(dev, "using simple if_transmit\n"); 5134 #else 5135 device_printf(dev, "ALTQ prevents using simple if_transmit\n"); 5136 #endif 5137 } 5138 iflib_reset_qvalues(ctx); 5139 IFNET_WLOCK(); 5140 CTX_LOCK(ctx); 5141 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5142 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5143 goto fail_unlock; 5144 } 5145 _iflib_pre_assert(scctx); 5146 ctx->ifc_txrx = *scctx->isc_txrx; 5147 5148 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR)); 5149 5150 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 5151 ctx->ifc_mediap = scctx->isc_media; 5152 5153 #ifdef INVARIANTS 5154 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5155 MPASS(scctx->isc_tx_csum_flags); 5156 #endif 5157 5158 if_setcapabilities(ifp, 5159 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG); 5160 if_setcapenable(ifp, 5161 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG); 5162 5163 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5164 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5165 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5166 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5167 5168 num_txd = iflib_num_tx_descs(ctx); 5169 num_rxd = iflib_num_rx_descs(ctx); 5170 5171 /* XXX change for per-queue sizes */ 5172 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5173 num_txd, num_rxd); 5174 5175 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5176 scctx->isc_tx_nsegments = max(1, num_txd / 5177 MAX_SINGLE_PACKET_FRACTION); 5178 if (scctx->isc_tx_tso_segments_max > num_txd / 5179 MAX_SINGLE_PACKET_FRACTION) 5180 scctx->isc_tx_tso_segments_max = max(1, 5181 num_txd / MAX_SINGLE_PACKET_FRACTION); 5182 5183 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5184 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5185 /* 5186 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5187 * but some MACs do. 5188 */ 5189 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5190 IP_MAXPACKET)); 5191 /* 5192 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5193 * into account. In the worst case, each of these calls will 5194 * add another mbuf and, thus, the requirement for another DMA 5195 * segment. So for best performance, it doesn't make sense to 5196 * advertize a maximum of TSO segments that typically will 5197 * require defragmentation in iflib_encap(). 5198 */ 5199 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5200 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5201 } 5202 if (scctx->isc_rss_table_size == 0) 5203 scctx->isc_rss_table_size = 64; 5204 scctx->isc_rss_table_mask = scctx->isc_rss_table_size - 1; 5205 5206 /* Create and start admin taskqueue */ 5207 snprintf(namebuf, TASKQUEUE_NAMELEN, "if_%s_tq", device_get_nameunit(dev)); 5208 ctx->ifc_tq = taskqueue_create_fast(namebuf, M_NOWAIT, 5209 taskqueue_thread_enqueue, &ctx->ifc_tq); 5210 if (ctx->ifc_tq == NULL) { 5211 device_printf(dev, "Unable to create admin taskqueue\n"); 5212 return (ENOMEM); 5213 } 5214 5215 err = taskqueue_start_threads(&ctx->ifc_tq, 1, PI_NET, "%s", namebuf); 5216 if (err) { 5217 device_printf(dev, 5218 "Unable to start admin taskqueue threads error: %d\n", 5219 err); 5220 taskqueue_free(ctx->ifc_tq); 5221 return (err); 5222 } 5223 5224 TASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5225 5226 /* Set up cpu set. If it fails, use the set of all CPUs. */ 5227 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 5228 device_printf(dev, "Unable to fetch CPU list\n"); 5229 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 5230 ctx->ifc_cpus_are_physical_cores = false; 5231 } else 5232 ctx->ifc_cpus_are_physical_cores = true; 5233 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 5234 5235 /* 5236 * Now set up MSI or MSI-X, should return us the number of supported 5237 * vectors (will be 1 for a legacy interrupt and MSI). 5238 */ 5239 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 5240 msix = scctx->isc_vectors; 5241 } else if (scctx->isc_msix_bar != 0) 5242 /* 5243 * The simple fact that isc_msix_bar is not 0 does not mean we 5244 * we have a good value there that is known to work. 5245 */ 5246 msix = iflib_msix_init(ctx); 5247 else { 5248 scctx->isc_vectors = 1; 5249 scctx->isc_ntxqsets = 1; 5250 scctx->isc_nrxqsets = 1; 5251 scctx->isc_intr = IFLIB_INTR_LEGACY; 5252 msix = 0; 5253 } 5254 /* Get memory for the station queues */ 5255 if ((err = iflib_queues_alloc(ctx))) { 5256 device_printf(dev, "Unable to allocate queue memory\n"); 5257 goto fail_intr_free; 5258 } 5259 5260 if ((err = iflib_qset_structures_setup(ctx))) 5261 goto fail_queues; 5262 5263 /* 5264 * Now that we know how many queues there are, get the core offset. 5265 */ 5266 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 5267 5268 if (msix > 1) { 5269 /* 5270 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 5271 * aren't the default NULL implementation. 5272 */ 5273 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 5274 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5275 kobj_desc); 5276 if (kobj_method == &kobj_desc->deflt) { 5277 device_printf(dev, 5278 "MSI-X requires ifdi_rx_queue_intr_enable method"); 5279 err = EOPNOTSUPP; 5280 goto fail_queues; 5281 } 5282 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 5283 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5284 kobj_desc); 5285 if (kobj_method == &kobj_desc->deflt) { 5286 device_printf(dev, 5287 "MSI-X requires ifdi_tx_queue_intr_enable method"); 5288 err = EOPNOTSUPP; 5289 goto fail_queues; 5290 } 5291 5292 /* 5293 * Assign the MSI-X vectors. 5294 * Note that the default NULL ifdi_msix_intr_assign method will 5295 * fail here, too. 5296 */ 5297 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 5298 if (err != 0) { 5299 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 5300 err); 5301 goto fail_queues; 5302 } 5303 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 5304 rid = 0; 5305 if (scctx->isc_intr == IFLIB_INTR_MSI) { 5306 MPASS(msix == 1); 5307 rid = 1; 5308 } 5309 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 5310 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 5311 goto fail_queues; 5312 } 5313 } else { 5314 device_printf(dev, 5315 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 5316 err = ENODEV; 5317 goto fail_queues; 5318 } 5319 5320 /* 5321 * It prevents a double-locking panic with iflib_media_status when 5322 * the driver loads. 5323 */ 5324 CTX_UNLOCK(ctx); 5325 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5326 CTX_LOCK(ctx); 5327 5328 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5329 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5330 goto fail_detach; 5331 } 5332 5333 /* 5334 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5335 * This must appear after the call to ether_ifattach() because 5336 * ether_ifattach() sets if_hdrlen to the default value. 5337 */ 5338 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5339 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5340 5341 if ((err = iflib_netmap_attach(ctx))) { 5342 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 5343 goto fail_detach; 5344 } 5345 *ctxp = ctx; 5346 5347 DEBUGNET_SET(ctx->ifc_ifp, iflib); 5348 5349 iflib_add_device_sysctl_post(ctx); 5350 iflib_add_pfil(ctx); 5351 ctx->ifc_flags |= IFC_INIT_DONE; 5352 CTX_UNLOCK(ctx); 5353 IFNET_WUNLOCK(); 5354 5355 return (0); 5356 5357 fail_detach: 5358 ether_ifdetach(ctx->ifc_ifp); 5359 fail_queues: 5360 taskqueue_free(ctx->ifc_tq); 5361 iflib_tqg_detach(ctx); 5362 iflib_tx_structures_free(ctx); 5363 iflib_rx_structures_free(ctx); 5364 IFDI_DETACH(ctx); 5365 IFDI_QUEUES_FREE(ctx); 5366 fail_intr_free: 5367 iflib_free_intr_mem(ctx); 5368 fail_unlock: 5369 CTX_UNLOCK(ctx); 5370 IFNET_WUNLOCK(); 5371 iflib_deregister(ctx); 5372 device_set_softc(ctx->ifc_dev, NULL); 5373 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5374 free(ctx->ifc_softc, M_IFLIB); 5375 free(ctx, M_IFLIB); 5376 return (err); 5377 } 5378 5379 int 5380 iflib_device_attach(device_t dev) 5381 { 5382 if_ctx_t ctx; 5383 if_shared_ctx_t sctx; 5384 5385 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5386 return (ENOTSUP); 5387 5388 pci_enable_busmaster(dev); 5389 5390 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5391 } 5392 5393 int 5394 iflib_device_deregister(if_ctx_t ctx) 5395 { 5396 if_t ifp = ctx->ifc_ifp; 5397 device_t dev = ctx->ifc_dev; 5398 5399 /* Make sure VLANS are not using driver */ 5400 if (if_vlantrunkinuse(ifp)) { 5401 device_printf(dev, "Vlan in use, detach first\n"); 5402 return (EBUSY); 5403 } 5404 #ifdef PCI_IOV 5405 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5406 device_printf(dev, "SR-IOV in use; detach first.\n"); 5407 return (EBUSY); 5408 } 5409 #endif 5410 5411 STATE_LOCK(ctx); 5412 ctx->ifc_flags |= IFC_IN_DETACH; 5413 STATE_UNLOCK(ctx); 5414 5415 /* Unregister VLAN handlers before calling iflib_stop() */ 5416 iflib_unregister_vlan_handlers(ctx); 5417 5418 iflib_netmap_detach(ifp); 5419 ether_ifdetach(ifp); 5420 5421 CTX_LOCK(ctx); 5422 iflib_stop(ctx); 5423 CTX_UNLOCK(ctx); 5424 5425 iflib_rem_pfil(ctx); 5426 if (ctx->ifc_led_dev != NULL) 5427 led_destroy(ctx->ifc_led_dev); 5428 5429 iflib_tqg_detach(ctx); 5430 iflib_tx_structures_free(ctx); 5431 iflib_rx_structures_free(ctx); 5432 5433 CTX_LOCK(ctx); 5434 IFDI_DETACH(ctx); 5435 IFDI_QUEUES_FREE(ctx); 5436 CTX_UNLOCK(ctx); 5437 5438 taskqueue_free(ctx->ifc_tq); 5439 ctx->ifc_tq = NULL; 5440 5441 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5442 iflib_free_intr_mem(ctx); 5443 5444 bus_generic_detach(dev); 5445 5446 iflib_deregister(ctx); 5447 5448 device_set_softc(ctx->ifc_dev, NULL); 5449 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5450 free(ctx->ifc_softc, M_IFLIB); 5451 unref_ctx_core_offset(ctx); 5452 free(ctx, M_IFLIB); 5453 return (0); 5454 } 5455 5456 static void 5457 iflib_tqg_detach(if_ctx_t ctx) 5458 { 5459 iflib_txq_t txq; 5460 iflib_rxq_t rxq; 5461 int i; 5462 struct taskqgroup *tqg; 5463 5464 /* XXX drain any dependent tasks */ 5465 tqg = qgroup_if_io_tqg; 5466 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5467 callout_drain(&txq->ift_timer); 5468 #ifdef DEV_NETMAP 5469 callout_drain(&txq->ift_netmap_timer); 5470 #endif /* DEV_NETMAP */ 5471 if (txq->ift_task.gt_uniq != NULL) 5472 taskqgroup_detach(tqg, &txq->ift_task); 5473 } 5474 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5475 if (rxq->ifr_task.gt_uniq != NULL) 5476 taskqgroup_detach(tqg, &rxq->ifr_task); 5477 } 5478 } 5479 5480 static void 5481 iflib_free_intr_mem(if_ctx_t ctx) 5482 { 5483 5484 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5485 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5486 } 5487 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5488 pci_release_msi(ctx->ifc_dev); 5489 } 5490 if (ctx->ifc_msix_mem != NULL) { 5491 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5492 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5493 ctx->ifc_msix_mem = NULL; 5494 } 5495 } 5496 5497 int 5498 iflib_device_detach(device_t dev) 5499 { 5500 if_ctx_t ctx = device_get_softc(dev); 5501 5502 return (iflib_device_deregister(ctx)); 5503 } 5504 5505 int 5506 iflib_device_suspend(device_t dev) 5507 { 5508 if_ctx_t ctx = device_get_softc(dev); 5509 5510 CTX_LOCK(ctx); 5511 IFDI_SUSPEND(ctx); 5512 CTX_UNLOCK(ctx); 5513 5514 return (bus_generic_suspend(dev)); 5515 } 5516 int 5517 iflib_device_shutdown(device_t dev) 5518 { 5519 if_ctx_t ctx = device_get_softc(dev); 5520 5521 CTX_LOCK(ctx); 5522 IFDI_SHUTDOWN(ctx); 5523 CTX_UNLOCK(ctx); 5524 5525 return (bus_generic_suspend(dev)); 5526 } 5527 5528 int 5529 iflib_device_resume(device_t dev) 5530 { 5531 if_ctx_t ctx = device_get_softc(dev); 5532 iflib_txq_t txq = ctx->ifc_txqs; 5533 5534 CTX_LOCK(ctx); 5535 IFDI_RESUME(ctx); 5536 iflib_if_init_locked(ctx); 5537 CTX_UNLOCK(ctx); 5538 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5539 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5540 5541 return (bus_generic_resume(dev)); 5542 } 5543 5544 int 5545 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5546 { 5547 int error; 5548 if_ctx_t ctx = device_get_softc(dev); 5549 5550 CTX_LOCK(ctx); 5551 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5552 CTX_UNLOCK(ctx); 5553 5554 return (error); 5555 } 5556 5557 void 5558 iflib_device_iov_uninit(device_t dev) 5559 { 5560 if_ctx_t ctx = device_get_softc(dev); 5561 5562 CTX_LOCK(ctx); 5563 IFDI_IOV_UNINIT(ctx); 5564 CTX_UNLOCK(ctx); 5565 } 5566 5567 int 5568 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5569 { 5570 int error; 5571 if_ctx_t ctx = device_get_softc(dev); 5572 5573 CTX_LOCK(ctx); 5574 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5575 CTX_UNLOCK(ctx); 5576 5577 return (error); 5578 } 5579 5580 /********************************************************************* 5581 * 5582 * MODULE FUNCTION DEFINITIONS 5583 * 5584 **********************************************************************/ 5585 5586 /* 5587 * - Start a fast taskqueue thread for each core 5588 * - Start a taskqueue for control operations 5589 */ 5590 static int 5591 iflib_module_init(void) 5592 { 5593 iflib_timer_default = hz / 2; 5594 return (0); 5595 } 5596 5597 static int 5598 iflib_module_event_handler(module_t mod, int what, void *arg) 5599 { 5600 int err; 5601 5602 switch (what) { 5603 case MOD_LOAD: 5604 if ((err = iflib_module_init()) != 0) 5605 return (err); 5606 break; 5607 case MOD_UNLOAD: 5608 return (EBUSY); 5609 default: 5610 return (EOPNOTSUPP); 5611 } 5612 5613 return (0); 5614 } 5615 5616 /********************************************************************* 5617 * 5618 * PUBLIC FUNCTION DEFINITIONS 5619 * ordered as in iflib.h 5620 * 5621 **********************************************************************/ 5622 5623 static void 5624 _iflib_assert(if_shared_ctx_t sctx) 5625 { 5626 int i; 5627 5628 MPASS(sctx->isc_tx_maxsize); 5629 MPASS(sctx->isc_tx_maxsegsize); 5630 5631 MPASS(sctx->isc_rx_maxsize); 5632 MPASS(sctx->isc_rx_nsegments); 5633 MPASS(sctx->isc_rx_maxsegsize); 5634 5635 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5636 for (i = 0; i < sctx->isc_nrxqs; i++) { 5637 MPASS(sctx->isc_nrxd_min[i]); 5638 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5639 MPASS(sctx->isc_nrxd_max[i]); 5640 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5641 MPASS(sctx->isc_nrxd_default[i]); 5642 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5643 } 5644 5645 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5646 for (i = 0; i < sctx->isc_ntxqs; i++) { 5647 MPASS(sctx->isc_ntxd_min[i]); 5648 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5649 MPASS(sctx->isc_ntxd_max[i]); 5650 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5651 MPASS(sctx->isc_ntxd_default[i]); 5652 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5653 } 5654 } 5655 5656 static void 5657 _iflib_pre_assert(if_softc_ctx_t scctx) 5658 { 5659 5660 MPASS(scctx->isc_txrx->ift_txd_encap); 5661 MPASS(scctx->isc_txrx->ift_txd_flush); 5662 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5663 MPASS(scctx->isc_txrx->ift_rxd_available); 5664 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5665 MPASS(scctx->isc_txrx->ift_rxd_refill); 5666 MPASS(scctx->isc_txrx->ift_rxd_flush); 5667 } 5668 5669 static void 5670 iflib_register(if_ctx_t ctx) 5671 { 5672 if_shared_ctx_t sctx = ctx->ifc_sctx; 5673 driver_t *driver = sctx->isc_driver; 5674 device_t dev = ctx->ifc_dev; 5675 if_t ifp; 5676 5677 _iflib_assert(sctx); 5678 5679 CTX_LOCK_INIT(ctx); 5680 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5681 ifp = ctx->ifc_ifp = if_alloc_dev(IFT_ETHER, dev); 5682 5683 /* 5684 * Initialize our context's device specific methods 5685 */ 5686 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5687 kobj_class_compile((kobj_class_t) driver); 5688 5689 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5690 if_setsoftc(ifp, ctx); 5691 if_setdev(ifp, dev); 5692 if_setinitfn(ifp, iflib_if_init); 5693 if_setioctlfn(ifp, iflib_if_ioctl); 5694 #ifdef ALTQ 5695 if_setstartfn(ifp, iflib_altq_if_start); 5696 if_settransmitfn(ifp, iflib_altq_if_transmit); 5697 if_setsendqready(ifp); 5698 #else 5699 if_settransmitfn(ifp, iflib_if_transmit); 5700 #endif 5701 if_setqflushfn(ifp, iflib_if_qflush); 5702 if_setgetcounterfn(ifp, iflib_if_get_counter); 5703 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5704 ctx->ifc_vlan_attach_event = 5705 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5706 EVENTHANDLER_PRI_FIRST); 5707 ctx->ifc_vlan_detach_event = 5708 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5709 EVENTHANDLER_PRI_FIRST); 5710 5711 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5712 ctx->ifc_mediap = &ctx->ifc_media; 5713 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5714 iflib_media_change, iflib_media_status); 5715 } 5716 } 5717 5718 static void 5719 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5720 { 5721 /* Unregister VLAN events */ 5722 if (ctx->ifc_vlan_attach_event != NULL) { 5723 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5724 ctx->ifc_vlan_attach_event = NULL; 5725 } 5726 if (ctx->ifc_vlan_detach_event != NULL) { 5727 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5728 ctx->ifc_vlan_detach_event = NULL; 5729 } 5730 5731 } 5732 5733 static void 5734 iflib_deregister(if_ctx_t ctx) 5735 { 5736 if_t ifp = ctx->ifc_ifp; 5737 5738 /* Remove all media */ 5739 ifmedia_removeall(&ctx->ifc_media); 5740 5741 /* Ensure that VLAN event handlers are unregistered */ 5742 iflib_unregister_vlan_handlers(ctx); 5743 5744 /* Release kobject reference */ 5745 kobj_delete((kobj_t) ctx, NULL); 5746 5747 /* Free the ifnet structure */ 5748 if_free(ifp); 5749 5750 STATE_LOCK_DESTROY(ctx); 5751 5752 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5753 CTX_LOCK_DESTROY(ctx); 5754 } 5755 5756 static int 5757 iflib_queues_alloc(if_ctx_t ctx) 5758 { 5759 if_shared_ctx_t sctx = ctx->ifc_sctx; 5760 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5761 device_t dev = ctx->ifc_dev; 5762 int nrxqsets = scctx->isc_nrxqsets; 5763 int ntxqsets = scctx->isc_ntxqsets; 5764 iflib_txq_t txq; 5765 iflib_rxq_t rxq; 5766 iflib_fl_t fl = NULL; 5767 int i, j, cpu, err, txconf, rxconf; 5768 iflib_dma_info_t ifdip; 5769 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5770 uint32_t *txqsizes = scctx->isc_txqsizes; 5771 uint8_t nrxqs = sctx->isc_nrxqs; 5772 uint8_t ntxqs = sctx->isc_ntxqs; 5773 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5774 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0); 5775 caddr_t *vaddrs; 5776 uint64_t *paddrs; 5777 5778 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5779 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5780 KASSERT(nrxqs >= fl_offset + nfree_lists, 5781 ("there must be at least a rxq for each free list")); 5782 5783 /* Allocate the TX ring struct memory */ 5784 if (!(ctx->ifc_txqs = 5785 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5786 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5787 device_printf(dev, "Unable to allocate TX ring memory\n"); 5788 err = ENOMEM; 5789 goto fail; 5790 } 5791 5792 /* Now allocate the RX */ 5793 if (!(ctx->ifc_rxqs = 5794 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5795 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5796 device_printf(dev, "Unable to allocate RX ring memory\n"); 5797 err = ENOMEM; 5798 goto rx_fail; 5799 } 5800 5801 txq = ctx->ifc_txqs; 5802 rxq = ctx->ifc_rxqs; 5803 5804 /* 5805 * XXX handle allocation failure 5806 */ 5807 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5808 /* Set up some basics */ 5809 5810 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5811 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5812 device_printf(dev, 5813 "Unable to allocate TX DMA info memory\n"); 5814 err = ENOMEM; 5815 goto err_tx_desc; 5816 } 5817 txq->ift_ifdi = ifdip; 5818 for (j = 0; j < ntxqs; j++, ifdip++) { 5819 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5820 device_printf(dev, 5821 "Unable to allocate TX descriptors\n"); 5822 err = ENOMEM; 5823 goto err_tx_desc; 5824 } 5825 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5826 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5827 } 5828 txq->ift_ctx = ctx; 5829 txq->ift_id = i; 5830 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5831 txq->ift_br_offset = 1; 5832 } else { 5833 txq->ift_br_offset = 0; 5834 } 5835 5836 if (iflib_txsd_alloc(txq)) { 5837 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5838 err = ENOMEM; 5839 goto err_tx_desc; 5840 } 5841 5842 /* Initialize the TX lock */ 5843 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5844 device_get_nameunit(dev), txq->ift_id); 5845 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5846 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5847 txq->ift_timer.c_cpu = cpu; 5848 #ifdef DEV_NETMAP 5849 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 5850 txq->ift_netmap_timer.c_cpu = cpu; 5851 #endif /* DEV_NETMAP */ 5852 5853 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5854 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5855 if (err) { 5856 /* XXX free any allocated rings */ 5857 device_printf(dev, "Unable to allocate buf_ring\n"); 5858 goto err_tx_desc; 5859 } 5860 txq->ift_reclaim_thresh = ctx->ifc_sysctl_tx_reclaim_thresh; 5861 } 5862 5863 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5864 /* Set up some basics */ 5865 callout_init(&rxq->ifr_watchdog, 1); 5866 5867 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5868 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5869 device_printf(dev, 5870 "Unable to allocate RX DMA info memory\n"); 5871 err = ENOMEM; 5872 goto err_tx_desc; 5873 } 5874 5875 rxq->ifr_ifdi = ifdip; 5876 /* XXX this needs to be changed if #rx queues != #tx queues */ 5877 rxq->ifr_ntxqirq = 1; 5878 rxq->ifr_txqid[0] = i; 5879 for (j = 0; j < nrxqs; j++, ifdip++) { 5880 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5881 device_printf(dev, 5882 "Unable to allocate RX descriptors\n"); 5883 err = ENOMEM; 5884 goto err_tx_desc; 5885 } 5886 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5887 } 5888 rxq->ifr_ctx = ctx; 5889 rxq->ifr_id = i; 5890 rxq->ifr_fl_offset = fl_offset; 5891 rxq->ifr_nfl = nfree_lists; 5892 if (!(fl = 5893 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5894 device_printf(dev, "Unable to allocate free list memory\n"); 5895 err = ENOMEM; 5896 goto err_tx_desc; 5897 } 5898 rxq->ifr_fl = fl; 5899 for (j = 0; j < nfree_lists; j++) { 5900 fl[j].ifl_rxq = rxq; 5901 fl[j].ifl_id = j; 5902 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5903 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5904 } 5905 /* Allocate receive buffers for the ring */ 5906 if (iflib_rxsd_alloc(rxq)) { 5907 device_printf(dev, 5908 "Critical Failure setting up receive buffers\n"); 5909 err = ENOMEM; 5910 goto err_rx_desc; 5911 } 5912 5913 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5914 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5915 M_WAITOK); 5916 } 5917 5918 /* TXQs */ 5919 vaddrs = malloc(sizeof(caddr_t) * ntxqsets * ntxqs, M_IFLIB, M_WAITOK); 5920 paddrs = malloc(sizeof(uint64_t) * ntxqsets * ntxqs, M_IFLIB, M_WAITOK); 5921 for (i = 0; i < ntxqsets; i++) { 5922 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5923 5924 for (j = 0; j < ntxqs; j++, di++) { 5925 vaddrs[i * ntxqs + j] = di->idi_vaddr; 5926 paddrs[i * ntxqs + j] = di->idi_paddr; 5927 } 5928 } 5929 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5930 device_printf(ctx->ifc_dev, 5931 "Unable to allocate device TX queue\n"); 5932 iflib_tx_structures_free(ctx); 5933 free(vaddrs, M_IFLIB); 5934 free(paddrs, M_IFLIB); 5935 goto err_rx_desc; 5936 } 5937 free(vaddrs, M_IFLIB); 5938 free(paddrs, M_IFLIB); 5939 5940 /* RXQs */ 5941 vaddrs = malloc(sizeof(caddr_t) * nrxqsets * nrxqs, M_IFLIB, M_WAITOK); 5942 paddrs = malloc(sizeof(uint64_t) * nrxqsets * nrxqs, M_IFLIB, M_WAITOK); 5943 for (i = 0; i < nrxqsets; i++) { 5944 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5945 5946 for (j = 0; j < nrxqs; j++, di++) { 5947 vaddrs[i * nrxqs + j] = di->idi_vaddr; 5948 paddrs[i * nrxqs + j] = di->idi_paddr; 5949 } 5950 } 5951 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5952 device_printf(ctx->ifc_dev, 5953 "Unable to allocate device RX queue\n"); 5954 iflib_tx_structures_free(ctx); 5955 free(vaddrs, M_IFLIB); 5956 free(paddrs, M_IFLIB); 5957 goto err_rx_desc; 5958 } 5959 free(vaddrs, M_IFLIB); 5960 free(paddrs, M_IFLIB); 5961 5962 return (0); 5963 5964 /* XXX handle allocation failure changes */ 5965 err_rx_desc: 5966 err_tx_desc: 5967 rx_fail: 5968 if (ctx->ifc_rxqs != NULL) 5969 free(ctx->ifc_rxqs, M_IFLIB); 5970 ctx->ifc_rxqs = NULL; 5971 if (ctx->ifc_txqs != NULL) 5972 free(ctx->ifc_txqs, M_IFLIB); 5973 ctx->ifc_txqs = NULL; 5974 fail: 5975 return (err); 5976 } 5977 5978 static int 5979 iflib_tx_structures_setup(if_ctx_t ctx) 5980 { 5981 iflib_txq_t txq = ctx->ifc_txqs; 5982 int i; 5983 5984 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5985 iflib_txq_setup(txq); 5986 5987 return (0); 5988 } 5989 5990 static void 5991 iflib_tx_structures_free(if_ctx_t ctx) 5992 { 5993 iflib_txq_t txq = ctx->ifc_txqs; 5994 if_shared_ctx_t sctx = ctx->ifc_sctx; 5995 int i, j; 5996 5997 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5998 for (j = 0; j < sctx->isc_ntxqs; j++) 5999 iflib_dma_free(&txq->ift_ifdi[j]); 6000 iflib_txq_destroy(txq); 6001 } 6002 free(ctx->ifc_txqs, M_IFLIB); 6003 ctx->ifc_txqs = NULL; 6004 } 6005 6006 /********************************************************************* 6007 * 6008 * Initialize all receive rings. 6009 * 6010 **********************************************************************/ 6011 static int 6012 iflib_rx_structures_setup(if_ctx_t ctx) 6013 { 6014 iflib_rxq_t rxq = ctx->ifc_rxqs; 6015 int q; 6016 #if defined(INET6) || defined(INET) 6017 int err, i; 6018 #endif 6019 6020 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 6021 #if defined(INET6) || defined(INET) 6022 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 6023 TCP_LRO_ENTRIES, min(1024, 6024 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 6025 if (err != 0) { 6026 device_printf(ctx->ifc_dev, 6027 "LRO Initialization failed!\n"); 6028 goto fail; 6029 } 6030 #endif 6031 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 6032 } 6033 return (0); 6034 #if defined(INET6) || defined(INET) 6035 fail: 6036 /* 6037 * Free LRO resources allocated so far, we will only handle 6038 * the rings that completed, the failing case will have 6039 * cleaned up for itself. 'q' failed, so its the terminus. 6040 */ 6041 rxq = ctx->ifc_rxqs; 6042 for (i = 0; i < q; ++i, rxq++) { 6043 tcp_lro_free(&rxq->ifr_lc); 6044 } 6045 return (err); 6046 #endif 6047 } 6048 6049 /********************************************************************* 6050 * 6051 * Free all receive rings. 6052 * 6053 **********************************************************************/ 6054 static void 6055 iflib_rx_structures_free(if_ctx_t ctx) 6056 { 6057 iflib_rxq_t rxq = ctx->ifc_rxqs; 6058 if_shared_ctx_t sctx = ctx->ifc_sctx; 6059 int i, j; 6060 6061 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 6062 for (j = 0; j < sctx->isc_nrxqs; j++) 6063 iflib_dma_free(&rxq->ifr_ifdi[j]); 6064 iflib_rx_sds_free(rxq); 6065 #if defined(INET6) || defined(INET) 6066 tcp_lro_free(&rxq->ifr_lc); 6067 #endif 6068 } 6069 free(ctx->ifc_rxqs, M_IFLIB); 6070 ctx->ifc_rxqs = NULL; 6071 } 6072 6073 static int 6074 iflib_qset_structures_setup(if_ctx_t ctx) 6075 { 6076 int err; 6077 6078 /* 6079 * It is expected that the caller takes care of freeing queues if this 6080 * fails. 6081 */ 6082 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 6083 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 6084 return (err); 6085 } 6086 6087 if ((err = iflib_rx_structures_setup(ctx)) != 0) 6088 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 6089 6090 return (err); 6091 } 6092 6093 int 6094 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 6095 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 6096 { 6097 6098 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 6099 } 6100 6101 /* Just to avoid copy/paste */ 6102 static inline int 6103 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6104 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 6105 const char *name) 6106 { 6107 device_t dev; 6108 unsigned int base_cpuid, cpuid; 6109 int err; 6110 6111 dev = ctx->ifc_dev; 6112 base_cpuid = ctx->ifc_sysctl_core_offset; 6113 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX); 6114 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, 6115 irq ? irq->ii_res : NULL, name); 6116 if (err) { 6117 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6118 return (err); 6119 } 6120 #ifdef notyet 6121 if (cpuid > ctx->ifc_cpuid_highest) 6122 ctx->ifc_cpuid_highest = cpuid; 6123 #endif 6124 return (0); 6125 } 6126 6127 /* 6128 * Allocate a hardware interrupt for subctx using the parent (ctx)'s hardware 6129 * resources. 6130 * 6131 * Similar to iflib_irq_alloc_generic(), but for interrupt type IFLIB_INTR_RXTX 6132 * only. 6133 * 6134 * XXX: Could be removed if subctx's dev has its intr resource allocation 6135 * methods replaced with custom ones? 6136 */ 6137 int 6138 iflib_irq_alloc_generic_subctx(if_ctx_t ctx, if_ctx_t subctx, if_irq_t irq, 6139 int rid, iflib_intr_type_t type, 6140 driver_filter_t *filter, void *filter_arg, 6141 int qid, const char *name) 6142 { 6143 device_t dev, subdev; 6144 struct grouptask *gtask; 6145 struct taskqgroup *tqg; 6146 iflib_filter_info_t info; 6147 gtask_fn_t *fn; 6148 int tqrid, err; 6149 driver_filter_t *intr_fast; 6150 void *q; 6151 6152 MPASS(ctx != NULL); 6153 MPASS(subctx != NULL); 6154 6155 tqrid = rid; 6156 dev = ctx->ifc_dev; 6157 subdev = subctx->ifc_dev; 6158 6159 switch (type) { 6160 case IFLIB_INTR_RXTX: 6161 q = &subctx->ifc_rxqs[qid]; 6162 info = &subctx->ifc_rxqs[qid].ifr_filter_info; 6163 gtask = &subctx->ifc_rxqs[qid].ifr_task; 6164 tqg = qgroup_if_io_tqg; 6165 fn = _task_fn_rx; 6166 intr_fast = iflib_fast_intr_rxtx; 6167 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6168 break; 6169 default: 6170 device_printf(dev, "%s: unknown net intr type for subctx %s (%d)\n", 6171 __func__, device_get_nameunit(subdev), type); 6172 return (EINVAL); 6173 } 6174 6175 info->ifi_filter = filter; 6176 info->ifi_filter_arg = filter_arg; 6177 info->ifi_task = gtask; 6178 info->ifi_ctx = q; 6179 6180 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6181 6182 /* Allocate interrupts from hardware using parent context */ 6183 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6184 if (err != 0) { 6185 device_printf(dev, "_iflib_irq_alloc failed for subctx %s: %d\n", 6186 device_get_nameunit(subdev), err); 6187 return (err); 6188 } 6189 6190 if (tqrid != -1) { 6191 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6192 name); 6193 if (err) 6194 return (err); 6195 } else { 6196 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6197 } 6198 6199 return (0); 6200 } 6201 6202 int 6203 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6204 iflib_intr_type_t type, driver_filter_t *filter, 6205 void *filter_arg, int qid, const char *name) 6206 { 6207 device_t dev; 6208 struct grouptask *gtask; 6209 struct taskqgroup *tqg; 6210 iflib_filter_info_t info; 6211 gtask_fn_t *fn; 6212 int tqrid, err; 6213 driver_filter_t *intr_fast; 6214 void *q; 6215 6216 info = &ctx->ifc_filter_info; 6217 tqrid = rid; 6218 6219 switch (type) { 6220 /* XXX merge tx/rx for netmap? */ 6221 case IFLIB_INTR_TX: 6222 q = &ctx->ifc_txqs[qid]; 6223 info = &ctx->ifc_txqs[qid].ift_filter_info; 6224 gtask = &ctx->ifc_txqs[qid].ift_task; 6225 tqg = qgroup_if_io_tqg; 6226 fn = _task_fn_tx; 6227 intr_fast = iflib_fast_intr; 6228 GROUPTASK_INIT(gtask, 0, fn, q); 6229 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6230 break; 6231 case IFLIB_INTR_RX: 6232 q = &ctx->ifc_rxqs[qid]; 6233 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6234 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6235 tqg = qgroup_if_io_tqg; 6236 fn = _task_fn_rx; 6237 intr_fast = iflib_fast_intr; 6238 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6239 break; 6240 case IFLIB_INTR_RXTX: 6241 q = &ctx->ifc_rxqs[qid]; 6242 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6243 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6244 tqg = qgroup_if_io_tqg; 6245 fn = _task_fn_rx; 6246 intr_fast = iflib_fast_intr_rxtx; 6247 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6248 break; 6249 case IFLIB_INTR_ADMIN: 6250 q = ctx; 6251 tqrid = -1; 6252 info = &ctx->ifc_filter_info; 6253 gtask = NULL; 6254 intr_fast = iflib_fast_intr_ctx; 6255 break; 6256 default: 6257 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6258 __func__); 6259 return (EINVAL); 6260 } 6261 6262 info->ifi_filter = filter; 6263 info->ifi_filter_arg = filter_arg; 6264 info->ifi_task = gtask; 6265 info->ifi_ctx = q; 6266 6267 dev = ctx->ifc_dev; 6268 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6269 if (err != 0) { 6270 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6271 return (err); 6272 } 6273 if (type == IFLIB_INTR_ADMIN) 6274 return (0); 6275 6276 if (tqrid != -1) { 6277 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6278 name); 6279 if (err) 6280 return (err); 6281 } else { 6282 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6283 } 6284 6285 return (0); 6286 } 6287 6288 void 6289 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6290 void *arg, int qid, const char *name) 6291 { 6292 device_t dev; 6293 struct grouptask *gtask; 6294 struct taskqgroup *tqg; 6295 gtask_fn_t *fn; 6296 void *q; 6297 int err; 6298 6299 switch (type) { 6300 case IFLIB_INTR_TX: 6301 q = &ctx->ifc_txqs[qid]; 6302 gtask = &ctx->ifc_txqs[qid].ift_task; 6303 tqg = qgroup_if_io_tqg; 6304 fn = _task_fn_tx; 6305 GROUPTASK_INIT(gtask, 0, fn, q); 6306 break; 6307 case IFLIB_INTR_RX: 6308 q = &ctx->ifc_rxqs[qid]; 6309 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6310 tqg = qgroup_if_io_tqg; 6311 fn = _task_fn_rx; 6312 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6313 break; 6314 case IFLIB_INTR_IOV: 6315 TASK_INIT(&ctx->ifc_vflr_task, 0, _task_fn_iov, ctx); 6316 return; 6317 default: 6318 panic("unknown net intr type"); 6319 } 6320 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name); 6321 if (err) { 6322 dev = ctx->ifc_dev; 6323 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL, 6324 name); 6325 } 6326 } 6327 6328 void 6329 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6330 { 6331 6332 if (irq->ii_tag) 6333 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6334 6335 if (irq->ii_res) 6336 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6337 rman_get_rid(irq->ii_res), irq->ii_res); 6338 } 6339 6340 static int 6341 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6342 { 6343 iflib_txq_t txq = ctx->ifc_txqs; 6344 iflib_rxq_t rxq = ctx->ifc_rxqs; 6345 if_irq_t irq = &ctx->ifc_legacy_irq; 6346 iflib_filter_info_t info; 6347 device_t dev; 6348 struct grouptask *gtask; 6349 struct resource *res; 6350 int err, tqrid; 6351 bool rx_only; 6352 6353 info = &rxq->ifr_filter_info; 6354 gtask = &rxq->ifr_task; 6355 tqrid = *rid; 6356 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6357 6358 ctx->ifc_flags |= IFC_LEGACY; 6359 info->ifi_filter = filter; 6360 info->ifi_filter_arg = filter_arg; 6361 info->ifi_task = gtask; 6362 info->ifi_ctx = rxq; 6363 6364 dev = ctx->ifc_dev; 6365 /* We allocate a single interrupt resource */ 6366 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr : 6367 iflib_fast_intr_rxtx, NULL, info, name); 6368 if (err != 0) 6369 return (err); 6370 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, rxq); 6371 res = irq->ii_res; 6372 taskqgroup_attach(qgroup_if_io_tqg, gtask, rxq, dev, res, name); 6373 6374 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6375 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6376 "tx"); 6377 return (0); 6378 } 6379 6380 void 6381 iflib_led_create(if_ctx_t ctx) 6382 { 6383 6384 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6385 device_get_nameunit(ctx->ifc_dev)); 6386 } 6387 6388 void 6389 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6390 { 6391 6392 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6393 } 6394 6395 void 6396 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6397 { 6398 6399 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6400 } 6401 6402 void 6403 iflib_admin_intr_deferred(if_ctx_t ctx) 6404 { 6405 6406 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_admin_task); 6407 } 6408 6409 void 6410 iflib_iov_intr_deferred(if_ctx_t ctx) 6411 { 6412 6413 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_vflr_task); 6414 } 6415 6416 void 6417 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6418 { 6419 6420 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6421 name); 6422 } 6423 6424 void 6425 iflib_config_task_init(if_ctx_t ctx, struct task *config_task, task_fn_t *fn) 6426 { 6427 TASK_INIT(config_task, 0, fn, ctx); 6428 } 6429 6430 void 6431 iflib_config_task_enqueue(if_ctx_t ctx, struct task *config_task) 6432 { 6433 taskqueue_enqueue(ctx->ifc_tq, config_task); 6434 } 6435 6436 void 6437 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6438 { 6439 if_t ifp = ctx->ifc_ifp; 6440 iflib_txq_t txq = ctx->ifc_txqs; 6441 6442 if_setbaudrate(ifp, baudrate); 6443 if (baudrate >= IF_Gbps(10)) { 6444 STATE_LOCK(ctx); 6445 ctx->ifc_flags |= IFC_PREFETCH; 6446 STATE_UNLOCK(ctx); 6447 } 6448 /* If link down, disable watchdog */ 6449 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6450 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6451 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6452 } 6453 ctx->ifc_link_state = link_state; 6454 if_link_state_change(ifp, link_state); 6455 } 6456 6457 static int 6458 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6459 { 6460 int credits; 6461 #ifdef INVARIANTS 6462 int credits_pre = txq->ift_cidx_processed; 6463 #endif 6464 6465 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6466 BUS_DMASYNC_POSTREAD); 6467 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6468 return (0); 6469 6470 txq->ift_processed += credits; 6471 txq->ift_cidx_processed += credits; 6472 6473 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6474 if (txq->ift_cidx_processed >= txq->ift_size) 6475 txq->ift_cidx_processed -= txq->ift_size; 6476 return (credits); 6477 } 6478 6479 static int 6480 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6481 { 6482 iflib_fl_t fl; 6483 u_int i; 6484 6485 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6486 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6487 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6488 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6489 budget)); 6490 } 6491 6492 void 6493 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6494 const char *description, if_int_delay_info_t info, 6495 int offset, int value) 6496 { 6497 info->iidi_ctx = ctx; 6498 info->iidi_offset = offset; 6499 info->iidi_value = value; 6500 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6501 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6502 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6503 info, 0, iflib_sysctl_int_delay, "I", description); 6504 } 6505 6506 struct sx * 6507 iflib_ctx_lock_get(if_ctx_t ctx) 6508 { 6509 6510 return (&ctx->ifc_ctx_sx); 6511 } 6512 6513 static int 6514 iflib_msix_init(if_ctx_t ctx) 6515 { 6516 device_t dev = ctx->ifc_dev; 6517 if_shared_ctx_t sctx = ctx->ifc_sctx; 6518 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6519 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6520 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6521 6522 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6523 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6524 6525 if (bootverbose) 6526 device_printf(dev, "msix_init qsets capped at %d\n", 6527 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6528 6529 /* Override by tuneable */ 6530 if (scctx->isc_disable_msix) 6531 goto msi; 6532 6533 /* First try MSI-X */ 6534 if ((msgs = pci_msix_count(dev)) == 0) { 6535 if (bootverbose) 6536 device_printf(dev, "MSI-X not supported or disabled\n"); 6537 goto msi; 6538 } 6539 6540 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6541 /* 6542 * bar == -1 => "trust me I know what I'm doing" 6543 * Some drivers are for hardware that is so shoddily 6544 * documented that no one knows which bars are which 6545 * so the developer has to map all bars. This hack 6546 * allows shoddy garbage to use MSI-X in this framework. 6547 */ 6548 if (bar != -1) { 6549 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6550 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6551 if (ctx->ifc_msix_mem == NULL) { 6552 device_printf(dev, "Unable to map MSI-X table\n"); 6553 goto msi; 6554 } 6555 } 6556 6557 admincnt = sctx->isc_admin_intrcnt; 6558 #if IFLIB_DEBUG 6559 /* use only 1 qset in debug mode */ 6560 queuemsgs = min(msgs - admincnt, 1); 6561 #else 6562 queuemsgs = msgs - admincnt; 6563 #endif 6564 #ifdef RSS 6565 queues = imin(queuemsgs, rss_getnumbuckets()); 6566 #else 6567 queues = queuemsgs; 6568 #endif 6569 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6570 if (bootverbose) 6571 device_printf(dev, 6572 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6573 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6574 #ifdef RSS 6575 /* If we're doing RSS, clamp at the number of RSS buckets */ 6576 if (queues > rss_getnumbuckets()) 6577 queues = rss_getnumbuckets(); 6578 #endif 6579 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6580 rx_queues = iflib_num_rx_queues; 6581 else 6582 rx_queues = queues; 6583 6584 if (rx_queues > scctx->isc_nrxqsets) 6585 rx_queues = scctx->isc_nrxqsets; 6586 6587 /* 6588 * We want this to be all logical CPUs by default 6589 */ 6590 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6591 tx_queues = iflib_num_tx_queues; 6592 else 6593 tx_queues = mp_ncpus; 6594 6595 if (tx_queues > scctx->isc_ntxqsets) 6596 tx_queues = scctx->isc_ntxqsets; 6597 6598 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6599 #ifdef INVARIANTS 6600 if (tx_queues != rx_queues) 6601 device_printf(dev, 6602 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6603 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6604 #endif 6605 tx_queues = min(rx_queues, tx_queues); 6606 rx_queues = min(rx_queues, tx_queues); 6607 } 6608 6609 vectors = rx_queues + admincnt; 6610 if (msgs < vectors) { 6611 device_printf(dev, 6612 "insufficient number of MSI-X vectors " 6613 "(supported %d, need %d)\n", msgs, vectors); 6614 goto msi; 6615 } 6616 6617 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6618 tx_queues); 6619 msgs = vectors; 6620 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6621 if (vectors != msgs) { 6622 device_printf(dev, 6623 "Unable to allocate sufficient MSI-X vectors " 6624 "(got %d, need %d)\n", vectors, msgs); 6625 pci_release_msi(dev); 6626 if (bar != -1) { 6627 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6628 ctx->ifc_msix_mem); 6629 ctx->ifc_msix_mem = NULL; 6630 } 6631 goto msi; 6632 } 6633 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6634 vectors); 6635 scctx->isc_vectors = vectors; 6636 scctx->isc_nrxqsets = rx_queues; 6637 scctx->isc_ntxqsets = tx_queues; 6638 scctx->isc_intr = IFLIB_INTR_MSIX; 6639 6640 return (vectors); 6641 } else { 6642 device_printf(dev, 6643 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6644 err); 6645 if (bar != -1) { 6646 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6647 ctx->ifc_msix_mem); 6648 ctx->ifc_msix_mem = NULL; 6649 } 6650 } 6651 6652 msi: 6653 vectors = pci_msi_count(dev); 6654 scctx->isc_nrxqsets = 1; 6655 scctx->isc_ntxqsets = 1; 6656 scctx->isc_vectors = vectors; 6657 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6658 device_printf(dev, "Using an MSI interrupt\n"); 6659 scctx->isc_intr = IFLIB_INTR_MSI; 6660 } else { 6661 scctx->isc_vectors = 1; 6662 device_printf(dev, "Using a Legacy interrupt\n"); 6663 scctx->isc_intr = IFLIB_INTR_LEGACY; 6664 } 6665 6666 return (vectors); 6667 } 6668 6669 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6670 6671 static int 6672 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6673 { 6674 int rc; 6675 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6676 struct sbuf *sb; 6677 const char *ring_state = "UNKNOWN"; 6678 6679 /* XXX needed ? */ 6680 rc = sysctl_wire_old_buffer(req, 0); 6681 MPASS(rc == 0); 6682 if (rc != 0) 6683 return (rc); 6684 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6685 MPASS(sb != NULL); 6686 if (sb == NULL) 6687 return (ENOMEM); 6688 if (state[3] <= 3) 6689 ring_state = ring_states[state[3]]; 6690 6691 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6692 state[0], state[1], state[2], ring_state); 6693 rc = sbuf_finish(sb); 6694 sbuf_delete(sb); 6695 return (rc); 6696 } 6697 6698 enum iflib_ndesc_handler { 6699 IFLIB_NTXD_HANDLER, 6700 IFLIB_NRXD_HANDLER, 6701 }; 6702 6703 static int 6704 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6705 { 6706 if_ctx_t ctx = (void *)arg1; 6707 enum iflib_ndesc_handler type = arg2; 6708 char buf[256] = {0}; 6709 qidx_t *ndesc; 6710 char *p, *next; 6711 int nqs, rc, i; 6712 6713 nqs = 8; 6714 switch (type) { 6715 case IFLIB_NTXD_HANDLER: 6716 ndesc = ctx->ifc_sysctl_ntxds; 6717 if (ctx->ifc_sctx) 6718 nqs = ctx->ifc_sctx->isc_ntxqs; 6719 break; 6720 case IFLIB_NRXD_HANDLER: 6721 ndesc = ctx->ifc_sysctl_nrxds; 6722 if (ctx->ifc_sctx) 6723 nqs = ctx->ifc_sctx->isc_nrxqs; 6724 break; 6725 default: 6726 printf("%s: unhandled type\n", __func__); 6727 return (EINVAL); 6728 } 6729 if (nqs == 0) 6730 nqs = 8; 6731 6732 for (i = 0; i < 8; i++) { 6733 if (i >= nqs) 6734 break; 6735 if (i) 6736 strcat(buf, ","); 6737 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6738 } 6739 6740 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6741 if (rc || req->newptr == NULL) 6742 return (rc); 6743 6744 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6745 i++, p = strsep(&next, " ,")) { 6746 ndesc[i] = strtoul(p, NULL, 10); 6747 } 6748 6749 return (rc); 6750 } 6751 6752 static int 6753 iflib_handle_tx_reclaim_thresh(SYSCTL_HANDLER_ARGS) 6754 { 6755 if_ctx_t ctx = (void *)arg1; 6756 iflib_txq_t txq; 6757 int i, err; 6758 int thresh; 6759 6760 thresh = ctx->ifc_sysctl_tx_reclaim_thresh; 6761 err = sysctl_handle_int(oidp, &thresh, arg2, req); 6762 if (err != 0) { 6763 return err; 6764 } 6765 6766 if (thresh == ctx->ifc_sysctl_tx_reclaim_thresh) 6767 return 0; 6768 6769 if (thresh > ctx->ifc_softc_ctx.isc_ntxd[0] / 2) { 6770 device_printf(ctx->ifc_dev, "TX Reclaim thresh must be <= %d\n", 6771 ctx->ifc_softc_ctx.isc_ntxd[0] / 2); 6772 return (EINVAL); 6773 } 6774 6775 ctx->ifc_sysctl_tx_reclaim_thresh = thresh; 6776 if (ctx->ifc_txqs == NULL) 6777 return (err); 6778 6779 txq = &ctx->ifc_txqs[0]; 6780 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6781 txq->ift_reclaim_thresh = thresh; 6782 } 6783 return (err); 6784 } 6785 6786 static int 6787 iflib_handle_tx_reclaim_ticks(SYSCTL_HANDLER_ARGS) 6788 { 6789 if_ctx_t ctx = (void *)arg1; 6790 iflib_txq_t txq; 6791 int i, err; 6792 int ticks; 6793 6794 ticks = ctx->ifc_sysctl_tx_reclaim_ticks; 6795 err = sysctl_handle_int(oidp, &ticks, arg2, req); 6796 if (err != 0) { 6797 return err; 6798 } 6799 6800 if (ticks == ctx->ifc_sysctl_tx_reclaim_ticks) 6801 return 0; 6802 6803 if (ticks > hz) { 6804 device_printf(ctx->ifc_dev, 6805 "TX Reclaim ticks must be <= hz (%d)\n", hz); 6806 return (EINVAL); 6807 } 6808 6809 ctx->ifc_sysctl_tx_reclaim_ticks = ticks; 6810 if (ctx->ifc_txqs == NULL) 6811 return (err); 6812 6813 txq = &ctx->ifc_txqs[0]; 6814 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6815 txq->ift_reclaim_ticks = ticks; 6816 } 6817 return (err); 6818 } 6819 6820 #define NAME_BUFLEN 32 6821 static void 6822 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6823 { 6824 device_t dev = iflib_get_dev(ctx); 6825 struct sysctl_oid_list *child, *oid_list; 6826 struct sysctl_ctx_list *ctx_list; 6827 struct sysctl_oid *node; 6828 6829 ctx_list = device_get_sysctl_ctx(dev); 6830 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6831 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, 6832 OID_AUTO, "iflib", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 6833 "IFLIB fields"); 6834 oid_list = SYSCTL_CHILDREN(node); 6835 6836 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6837 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, "driver version"); 6838 6839 SYSCTL_ADD_BOOL(ctx_list, oid_list, OID_AUTO, "simple_tx", 6840 CTLFLAG_RDTUN, &ctx->ifc_sysctl_simple_tx, 0, 6841 "use simple tx ring"); 6842 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6843 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6844 "# of txqs to use, 0 => use default #"); 6845 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6846 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6847 "# of rxqs to use, 0 => use default #"); 6848 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6849 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6850 "permit #txq != #rxq"); 6851 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6852 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6853 "disable MSI-X (default 0)"); 6854 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6855 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, "set the RX budget"); 6856 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6857 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6858 "cause TX to abdicate instead of running to completion"); 6859 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6860 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6861 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6862 "offset to start using cores at"); 6863 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6864 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6865 "use separate cores for TX and RX"); 6866 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "use_logical_cores", 6867 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0, 6868 "try to make use of logical cores for TX and RX"); 6869 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "use_extra_msix_vectors", 6870 CTLFLAG_RDTUN, &ctx->ifc_sysctl_extra_msix_vectors, 0, 6871 "attempt to reserve the given number of extra MSI-X vectors during driver load for the creation of additional interfaces later"); 6872 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "allocated_msix_vectors", 6873 CTLFLAG_RDTUN, &ctx->ifc_softc_ctx.isc_vectors, 0, 6874 "total # of MSI-X vectors allocated by driver"); 6875 6876 /* XXX change for per-queue sizes */ 6877 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6878 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6879 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6880 "list of # of TX descriptors to use, 0 = use default #"); 6881 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6882 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6883 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6884 "list of # of RX descriptors to use, 0 = use default #"); 6885 } 6886 6887 static void 6888 iflib_add_device_sysctl_post(if_ctx_t ctx) 6889 { 6890 if_shared_ctx_t sctx = ctx->ifc_sctx; 6891 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6892 device_t dev = iflib_get_dev(ctx); 6893 struct sysctl_oid_list *child; 6894 struct sysctl_ctx_list *ctx_list; 6895 iflib_fl_t fl; 6896 iflib_txq_t txq; 6897 iflib_rxq_t rxq; 6898 int i, j; 6899 char namebuf[NAME_BUFLEN]; 6900 char *qfmt; 6901 struct sysctl_oid *queue_node, *fl_node, *node; 6902 struct sysctl_oid_list *queue_list, *fl_list; 6903 ctx_list = device_get_sysctl_ctx(dev); 6904 6905 node = ctx->ifc_sysctl_node; 6906 child = SYSCTL_CHILDREN(node); 6907 6908 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_reclaim_thresh", 6909 CTLTYPE_INT | CTLFLAG_RWTUN, ctx, 6910 0, iflib_handle_tx_reclaim_thresh, "I", 6911 "Number of TX descs outstanding before reclaim is called"); 6912 6913 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_reclaim_ticks", 6914 CTLTYPE_INT | CTLFLAG_RWTUN, ctx, 6915 0, iflib_handle_tx_reclaim_ticks, "I", 6916 "Number of ticks before a TX reclaim is forced"); 6917 6918 if (scctx->isc_ntxqsets > 100) 6919 qfmt = "txq%03d"; 6920 else if (scctx->isc_ntxqsets > 10) 6921 qfmt = "txq%02d"; 6922 else 6923 qfmt = "txq%d"; 6924 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6925 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6926 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6927 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6928 queue_list = SYSCTL_CHILDREN(queue_node); 6929 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 6930 CTLFLAG_RD, &txq->ift_task.gt_cpu, 0, 6931 "cpu this queue is bound to"); 6932 #if MEMORY_LOGGING 6933 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6934 CTLFLAG_RD, &txq->ift_dequeued, "total mbufs freed"); 6935 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6936 CTLFLAG_RD, &txq->ift_enqueued, "total mbufs enqueued"); 6937 #endif 6938 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6939 CTLFLAG_RD, &txq->ift_mbuf_defrag, 6940 "# of times m_defrag was called"); 6941 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6942 CTLFLAG_RD, &txq->ift_pullups, 6943 "# of times m_pullup was called"); 6944 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 6945 "mbuf_defrag_failed", CTLFLAG_RD, 6946 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6947 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 6948 "no_desc_avail", CTLFLAG_RD, &txq->ift_no_desc_avail, 6949 "# of times no descriptors were available"); 6950 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 6951 "tx_map_failed", CTLFLAG_RD, &txq->ift_map_failed, 6952 "# of times DMA map failed"); 6953 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 6954 "txd_encap_efbig", CTLFLAG_RD, &txq->ift_txd_encap_efbig, 6955 "# of times txd_encap returned EFBIG"); 6956 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 6957 "no_tx_dma_setup", CTLFLAG_RD, &txq->ift_no_tx_dma_setup, 6958 "# of times map failed for other than EFBIG"); 6959 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6960 CTLFLAG_RD, &txq->ift_pidx, 1, "Producer Index"); 6961 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6962 CTLFLAG_RD, &txq->ift_cidx, 1, "Consumer Index"); 6963 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, 6964 "txq_cidx_processed", CTLFLAG_RD, &txq->ift_cidx_processed, 6965 1, "Consumer Index seen by credit update"); 6966 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6967 CTLFLAG_RD, &txq->ift_in_use, 1, "descriptors in use"); 6968 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 6969 "txq_processed", CTLFLAG_RD, &txq->ift_processed, 6970 "descriptors procesed for clean"); 6971 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6972 CTLFLAG_RD, &txq->ift_cleaned, "total cleaned"); 6973 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6974 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6975 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6976 mp_ring_state_handler, "A", "soft ring state"); 6977 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 6978 "r_enqueues", CTLFLAG_RD, &txq->ift_br->enqueues, 6979 "# of enqueues to the mp_ring for this queue"); 6980 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 6981 "r_drops", CTLFLAG_RD, &txq->ift_br->drops, 6982 "# of drops in the mp_ring for this queue"); 6983 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 6984 "r_starts", CTLFLAG_RD, &txq->ift_br->starts, 6985 "# of normal consumer starts in mp_ring for this queue"); 6986 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 6987 "r_stalls", CTLFLAG_RD, &txq->ift_br->stalls, 6988 "# of consumer stalls in the mp_ring for this queue"); 6989 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 6990 "r_restarts", CTLFLAG_RD, &txq->ift_br->restarts, 6991 "# of consumer restarts in the mp_ring for this queue"); 6992 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 6993 "r_abdications", CTLFLAG_RD, &txq->ift_br->abdications, 6994 "# of consumer abdications in the mp_ring for this queue"); 6995 } 6996 6997 if (scctx->isc_nrxqsets > 100) 6998 qfmt = "rxq%03d"; 6999 else if (scctx->isc_nrxqsets > 10) 7000 qfmt = "rxq%02d"; 7001 else 7002 qfmt = "rxq%d"; 7003 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 7004 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 7005 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 7006 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 7007 queue_list = SYSCTL_CHILDREN(queue_node); 7008 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 7009 CTLFLAG_RD, &rxq->ifr_task.gt_cpu, 0, 7010 "cpu this queue is bound to"); 7011 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 7012 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, 7013 "rxq_cq_cidx", CTLFLAG_RD, &rxq->ifr_cq_cidx, 1, 7014 "Consumer Index"); 7015 } 7016 7017 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 7018 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 7019 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, 7020 OID_AUTO, namebuf, CTLFLAG_RD | CTLFLAG_MPSAFE, 7021 NULL, "freelist Name"); 7022 fl_list = SYSCTL_CHILDREN(fl_node); 7023 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 7024 CTLFLAG_RD, &fl->ifl_pidx, 1, "Producer Index"); 7025 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 7026 CTLFLAG_RD, &fl->ifl_cidx, 1, "Consumer Index"); 7027 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 7028 CTLFLAG_RD, &fl->ifl_credits, 1, 7029 "credits available"); 7030 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 7031 CTLFLAG_RD, &fl->ifl_buf_size, 1, "buffer size"); 7032 #if MEMORY_LOGGING 7033 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7034 "fl_m_enqueued", CTLFLAG_RD, &fl->ifl_m_enqueued, 7035 "mbufs allocated"); 7036 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7037 "fl_m_dequeued", CTLFLAG_RD, &fl->ifl_m_dequeued, 7038 "mbufs freed"); 7039 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7040 "fl_cl_enqueued", CTLFLAG_RD, &fl->ifl_cl_enqueued, 7041 "clusters allocated"); 7042 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7043 "fl_cl_dequeued", CTLFLAG_RD, &fl->ifl_cl_dequeued, 7044 "clusters freed"); 7045 #endif 7046 } 7047 } 7048 7049 } 7050 7051 void 7052 iflib_request_reset(if_ctx_t ctx) 7053 { 7054 7055 STATE_LOCK(ctx); 7056 ctx->ifc_flags |= IFC_DO_RESET; 7057 STATE_UNLOCK(ctx); 7058 } 7059 7060 #ifndef __NO_STRICT_ALIGNMENT 7061 static struct mbuf * 7062 iflib_fixup_rx(struct mbuf *m) 7063 { 7064 struct mbuf *n; 7065 7066 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 7067 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 7068 m->m_data += ETHER_HDR_LEN; 7069 n = m; 7070 } else { 7071 MGETHDR(n, M_NOWAIT, MT_DATA); 7072 if (n == NULL) { 7073 m_freem(m); 7074 return (NULL); 7075 } 7076 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 7077 m->m_data += ETHER_HDR_LEN; 7078 m->m_len -= ETHER_HDR_LEN; 7079 n->m_len = ETHER_HDR_LEN; 7080 M_MOVE_PKTHDR(n, m); 7081 n->m_next = m; 7082 } 7083 return (n); 7084 } 7085 #endif 7086 7087 #ifdef DEBUGNET 7088 static void 7089 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 7090 { 7091 if_ctx_t ctx; 7092 7093 ctx = if_getsoftc(ifp); 7094 CTX_LOCK(ctx); 7095 *nrxr = NRXQSETS(ctx); 7096 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 7097 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 7098 CTX_UNLOCK(ctx); 7099 } 7100 7101 static void 7102 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 7103 { 7104 if_ctx_t ctx; 7105 if_softc_ctx_t scctx; 7106 iflib_fl_t fl; 7107 iflib_rxq_t rxq; 7108 int i, j; 7109 7110 ctx = if_getsoftc(ifp); 7111 scctx = &ctx->ifc_softc_ctx; 7112 7113 switch (event) { 7114 case DEBUGNET_START: 7115 for (i = 0; i < scctx->isc_nrxqsets; i++) { 7116 rxq = &ctx->ifc_rxqs[i]; 7117 for (j = 0; j < rxq->ifr_nfl; j++) { 7118 fl = rxq->ifr_fl; 7119 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 7120 } 7121 } 7122 iflib_no_tx_batch = 1; 7123 break; 7124 default: 7125 break; 7126 } 7127 } 7128 7129 static int 7130 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 7131 { 7132 if_ctx_t ctx; 7133 iflib_txq_t txq; 7134 int error; 7135 7136 ctx = if_getsoftc(ifp); 7137 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7138 IFF_DRV_RUNNING) 7139 return (EBUSY); 7140 7141 txq = &ctx->ifc_txqs[0]; 7142 error = iflib_encap(txq, &m); 7143 if (error == 0) 7144 (void)iflib_txd_db_check(txq, true); 7145 return (error); 7146 } 7147 7148 static int 7149 iflib_debugnet_poll(if_t ifp, int count) 7150 { 7151 struct epoch_tracker et; 7152 if_ctx_t ctx; 7153 if_softc_ctx_t scctx; 7154 iflib_txq_t txq; 7155 int i; 7156 7157 ctx = if_getsoftc(ifp); 7158 scctx = &ctx->ifc_softc_ctx; 7159 7160 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7161 IFF_DRV_RUNNING) 7162 return (EBUSY); 7163 7164 txq = &ctx->ifc_txqs[0]; 7165 (void)iflib_completed_tx_reclaim(txq); 7166 7167 NET_EPOCH_ENTER(et); 7168 for (i = 0; i < scctx->isc_nrxqsets; i++) 7169 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 7170 NET_EPOCH_EXIT(et); 7171 return (0); 7172 } 7173 #endif /* DEBUGNET */ 7174 7175 #ifndef ALTQ 7176 static inline iflib_txq_t 7177 iflib_simple_select_queue(if_ctx_t ctx, struct mbuf *m) 7178 { 7179 int qidx; 7180 7181 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 7182 qidx = QIDX(ctx, m); 7183 else 7184 qidx = NTXQSETS(ctx) + FIRST_QSET(ctx) - 1; 7185 return (&ctx->ifc_txqs[qidx]); 7186 } 7187 7188 static int 7189 iflib_simple_transmit(if_t ifp, struct mbuf *m) 7190 { 7191 if_ctx_t ctx; 7192 iflib_txq_t txq; 7193 int error; 7194 int bytes_sent = 0, pkt_sent = 0, mcast_sent = 0; 7195 7196 7197 ctx = if_getsoftc(ifp); 7198 if (__predict_false((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 7199 || !LINK_ACTIVE(ctx))) { 7200 DBG_COUNTER_INC(tx_frees); 7201 m_freem(m); 7202 return (ENETDOWN); 7203 } 7204 7205 txq = iflib_simple_select_queue(ctx, m); 7206 mtx_lock(&txq->ift_mtx); 7207 error = iflib_encap(txq, &m); 7208 if (error == 0) { 7209 pkt_sent++; 7210 bytes_sent += m->m_pkthdr.len; 7211 mcast_sent += !!(m->m_flags & M_MCAST); 7212 (void)iflib_txd_db_check(txq, true); 7213 } else { 7214 if (error == ENOBUFS) 7215 if_inc_counter(ifp, IFCOUNTER_OQDROPS, 1); 7216 else 7217 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 7218 } 7219 (void)iflib_completed_tx_reclaim(txq); 7220 mtx_unlock(&txq->ift_mtx); 7221 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 7222 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 7223 if (mcast_sent) 7224 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 7225 7226 return (error); 7227 } 7228 #endif 7229