xref: /freebsd/sys/net/iflib.c (revision ddc0daea20280c3a06a910b72b14ffe3f624df71)
1 /*-
2  * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  *  1. Redistributions of source code must retain the above copyright notice,
9  *     this list of conditions and the following disclaimer.
10  *
11  *  2. Neither the name of Matthew Macy nor the names of its
12  *     contributors may be used to endorse or promote products derived from
13  *     this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25  * POSSIBILITY OF SUCH DAMAGE.
26  */
27 
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30 
31 #include "opt_inet.h"
32 #include "opt_inet6.h"
33 #include "opt_acpi.h"
34 #include "opt_sched.h"
35 
36 #include <sys/param.h>
37 #include <sys/types.h>
38 #include <sys/bus.h>
39 #include <sys/eventhandler.h>
40 #include <sys/kernel.h>
41 #include <sys/lock.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
44 #include <sys/kobj.h>
45 #include <sys/rman.h>
46 #include <sys/sbuf.h>
47 #include <sys/smp.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
54 
55 #include <net/if.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
59 #include <net/bpf.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
62 #include <net/pfil.h>
63 #include <net/vnet.h>
64 
65 #include <netinet/in.h>
66 #include <netinet/in_pcb.h>
67 #include <netinet/tcp_lro.h>
68 #include <netinet/in_systm.h>
69 #include <netinet/if_ether.h>
70 #include <netinet/ip.h>
71 #include <netinet/ip6.h>
72 #include <netinet/tcp.h>
73 #include <netinet/ip_var.h>
74 #include <netinet/netdump/netdump.h>
75 #include <netinet6/ip6_var.h>
76 
77 #include <machine/bus.h>
78 #include <machine/in_cksum.h>
79 
80 #include <vm/vm.h>
81 #include <vm/pmap.h>
82 
83 #include <dev/led/led.h>
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
86 #include <dev/pci/pci_private.h>
87 
88 #include <net/iflib.h>
89 #include <net/iflib_private.h>
90 
91 #include "ifdi_if.h"
92 
93 #ifdef PCI_IOV
94 #include <dev/pci/pci_iov.h>
95 #endif
96 
97 #include <sys/bitstring.h>
98 /*
99  * enable accounting of every mbuf as it comes in to and goes out of
100  * iflib's software descriptor references
101  */
102 #define MEMORY_LOGGING 0
103 /*
104  * Enable mbuf vectors for compressing long mbuf chains
105  */
106 
107 /*
108  * NB:
109  * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110  *   we prefetch needs to be determined by the time spent in m_free vis a vis
111  *   the cost of a prefetch. This will of course vary based on the workload:
112  *      - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
113  *        is quite expensive, thus suggesting very little prefetch.
114  *      - small packet forwarding which is just returning a single mbuf to
115  *        UMA will typically be very fast vis a vis the cost of a memory
116  *        access.
117  */
118 
119 
120 /*
121  * File organization:
122  *  - private structures
123  *  - iflib private utility functions
124  *  - ifnet functions
125  *  - vlan registry and other exported functions
126  *  - iflib public core functions
127  *
128  *
129  */
130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
131 
132 struct iflib_txq;
133 typedef struct iflib_txq *iflib_txq_t;
134 struct iflib_rxq;
135 typedef struct iflib_rxq *iflib_rxq_t;
136 struct iflib_fl;
137 typedef struct iflib_fl *iflib_fl_t;
138 
139 struct iflib_ctx;
140 
141 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
142 static void iflib_timer(void *arg);
143 
144 typedef struct iflib_filter_info {
145 	driver_filter_t *ifi_filter;
146 	void *ifi_filter_arg;
147 	struct grouptask *ifi_task;
148 	void *ifi_ctx;
149 } *iflib_filter_info_t;
150 
151 struct iflib_ctx {
152 	KOBJ_FIELDS;
153 	/*
154 	 * Pointer to hardware driver's softc
155 	 */
156 	void *ifc_softc;
157 	device_t ifc_dev;
158 	if_t ifc_ifp;
159 
160 	cpuset_t ifc_cpus;
161 	if_shared_ctx_t ifc_sctx;
162 	struct if_softc_ctx ifc_softc_ctx;
163 
164 	struct sx ifc_ctx_sx;
165 	struct mtx ifc_state_mtx;
166 
167 	iflib_txq_t ifc_txqs;
168 	iflib_rxq_t ifc_rxqs;
169 	uint32_t ifc_if_flags;
170 	uint32_t ifc_flags;
171 	uint32_t ifc_max_fl_buf_size;
172 	uint32_t ifc_rx_mbuf_sz;
173 
174 	int ifc_link_state;
175 	int ifc_watchdog_events;
176 	struct cdev *ifc_led_dev;
177 	struct resource *ifc_msix_mem;
178 
179 	struct if_irq ifc_legacy_irq;
180 	struct grouptask ifc_admin_task;
181 	struct grouptask ifc_vflr_task;
182 	struct iflib_filter_info ifc_filter_info;
183 	struct ifmedia	ifc_media;
184 	struct ifmedia	*ifc_mediap;
185 
186 	struct sysctl_oid *ifc_sysctl_node;
187 	uint16_t ifc_sysctl_ntxqs;
188 	uint16_t ifc_sysctl_nrxqs;
189 	uint16_t ifc_sysctl_qs_eq_override;
190 	uint16_t ifc_sysctl_rx_budget;
191 	uint16_t ifc_sysctl_tx_abdicate;
192 	uint16_t ifc_sysctl_core_offset;
193 #define	CORE_OFFSET_UNSPECIFIED	0xffff
194 	uint8_t  ifc_sysctl_separate_txrx;
195 
196 	qidx_t ifc_sysctl_ntxds[8];
197 	qidx_t ifc_sysctl_nrxds[8];
198 	struct if_txrx ifc_txrx;
199 #define isc_txd_encap  ifc_txrx.ift_txd_encap
200 #define isc_txd_flush  ifc_txrx.ift_txd_flush
201 #define isc_txd_credits_update  ifc_txrx.ift_txd_credits_update
202 #define isc_rxd_available ifc_txrx.ift_rxd_available
203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
209 	eventhandler_tag ifc_vlan_attach_event;
210 	eventhandler_tag ifc_vlan_detach_event;
211 	struct ether_addr ifc_mac;
212 };
213 
214 void *
215 iflib_get_softc(if_ctx_t ctx)
216 {
217 
218 	return (ctx->ifc_softc);
219 }
220 
221 device_t
222 iflib_get_dev(if_ctx_t ctx)
223 {
224 
225 	return (ctx->ifc_dev);
226 }
227 
228 if_t
229 iflib_get_ifp(if_ctx_t ctx)
230 {
231 
232 	return (ctx->ifc_ifp);
233 }
234 
235 struct ifmedia *
236 iflib_get_media(if_ctx_t ctx)
237 {
238 
239 	return (ctx->ifc_mediap);
240 }
241 
242 uint32_t
243 iflib_get_flags(if_ctx_t ctx)
244 {
245 	return (ctx->ifc_flags);
246 }
247 
248 void
249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
250 {
251 
252 	bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
253 }
254 
255 if_softc_ctx_t
256 iflib_get_softc_ctx(if_ctx_t ctx)
257 {
258 
259 	return (&ctx->ifc_softc_ctx);
260 }
261 
262 if_shared_ctx_t
263 iflib_get_sctx(if_ctx_t ctx)
264 {
265 
266 	return (ctx->ifc_sctx);
267 }
268 
269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
272 
273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
275 
276 typedef struct iflib_sw_rx_desc_array {
277 	bus_dmamap_t	*ifsd_map;         /* bus_dma maps for packet */
278 	struct mbuf	**ifsd_m;           /* pkthdr mbufs */
279 	caddr_t		*ifsd_cl;          /* direct cluster pointer for rx */
280 	bus_addr_t	*ifsd_ba;          /* bus addr of cluster for rx */
281 } iflib_rxsd_array_t;
282 
283 typedef struct iflib_sw_tx_desc_array {
284 	bus_dmamap_t    *ifsd_map;         /* bus_dma maps for packet */
285 	bus_dmamap_t	*ifsd_tso_map;     /* bus_dma maps for TSO packet */
286 	struct mbuf    **ifsd_m;           /* pkthdr mbufs */
287 } if_txsd_vec_t;
288 
289 /* magic number that should be high enough for any hardware */
290 #define IFLIB_MAX_TX_SEGS		128
291 #define IFLIB_RX_COPY_THRESH		128
292 #define IFLIB_MAX_RX_REFRESH		32
293 /* The minimum descriptors per second before we start coalescing */
294 #define IFLIB_MIN_DESC_SEC		16384
295 #define IFLIB_DEFAULT_TX_UPDATE_FREQ	16
296 #define IFLIB_QUEUE_IDLE		0
297 #define IFLIB_QUEUE_HUNG		1
298 #define IFLIB_QUEUE_WORKING		2
299 /* maximum number of txqs that can share an rx interrupt */
300 #define IFLIB_MAX_TX_SHARED_INTR	4
301 
302 /* this should really scale with ring size - this is a fairly arbitrary value */
303 #define TX_BATCH_SIZE			32
304 
305 #define IFLIB_RESTART_BUDGET		8
306 
307 #define CSUM_OFFLOAD		(CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
308 				 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
309 				 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
310 
311 struct iflib_txq {
312 	qidx_t		ift_in_use;
313 	qidx_t		ift_cidx;
314 	qidx_t		ift_cidx_processed;
315 	qidx_t		ift_pidx;
316 	uint8_t		ift_gen;
317 	uint8_t		ift_br_offset;
318 	uint16_t	ift_npending;
319 	uint16_t	ift_db_pending;
320 	uint16_t	ift_rs_pending;
321 	/* implicit pad */
322 	uint8_t		ift_txd_size[8];
323 	uint64_t	ift_processed;
324 	uint64_t	ift_cleaned;
325 	uint64_t	ift_cleaned_prev;
326 #if MEMORY_LOGGING
327 	uint64_t	ift_enqueued;
328 	uint64_t	ift_dequeued;
329 #endif
330 	uint64_t	ift_no_tx_dma_setup;
331 	uint64_t	ift_no_desc_avail;
332 	uint64_t	ift_mbuf_defrag_failed;
333 	uint64_t	ift_mbuf_defrag;
334 	uint64_t	ift_map_failed;
335 	uint64_t	ift_txd_encap_efbig;
336 	uint64_t	ift_pullups;
337 	uint64_t	ift_last_timer_tick;
338 
339 	struct mtx	ift_mtx;
340 	struct mtx	ift_db_mtx;
341 
342 	/* constant values */
343 	if_ctx_t	ift_ctx;
344 	struct ifmp_ring        *ift_br;
345 	struct grouptask	ift_task;
346 	qidx_t		ift_size;
347 	uint16_t	ift_id;
348 	struct callout	ift_timer;
349 
350 	if_txsd_vec_t	ift_sds;
351 	uint8_t		ift_qstatus;
352 	uint8_t		ift_closed;
353 	uint8_t		ift_update_freq;
354 	struct iflib_filter_info ift_filter_info;
355 	bus_dma_tag_t	ift_buf_tag;
356 	bus_dma_tag_t	ift_tso_buf_tag;
357 	iflib_dma_info_t	ift_ifdi;
358 #define MTX_NAME_LEN 16
359 	char                    ift_mtx_name[MTX_NAME_LEN];
360 	bus_dma_segment_t	ift_segs[IFLIB_MAX_TX_SEGS]  __aligned(CACHE_LINE_SIZE);
361 #ifdef IFLIB_DIAGNOSTICS
362 	uint64_t ift_cpu_exec_count[256];
363 #endif
364 } __aligned(CACHE_LINE_SIZE);
365 
366 struct iflib_fl {
367 	qidx_t		ifl_cidx;
368 	qidx_t		ifl_pidx;
369 	qidx_t		ifl_credits;
370 	uint8_t		ifl_gen;
371 	uint8_t		ifl_rxd_size;
372 #if MEMORY_LOGGING
373 	uint64_t	ifl_m_enqueued;
374 	uint64_t	ifl_m_dequeued;
375 	uint64_t	ifl_cl_enqueued;
376 	uint64_t	ifl_cl_dequeued;
377 #endif
378 	/* implicit pad */
379 	bitstr_t 	*ifl_rx_bitmap;
380 	qidx_t		ifl_fragidx;
381 	/* constant */
382 	qidx_t		ifl_size;
383 	uint16_t	ifl_buf_size;
384 	uint16_t	ifl_cltype;
385 	uma_zone_t	ifl_zone;
386 	iflib_rxsd_array_t	ifl_sds;
387 	iflib_rxq_t	ifl_rxq;
388 	uint8_t		ifl_id;
389 	bus_dma_tag_t	ifl_buf_tag;
390 	iflib_dma_info_t	ifl_ifdi;
391 	uint64_t	ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
392 	caddr_t		ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
393 	qidx_t	ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
394 }  __aligned(CACHE_LINE_SIZE);
395 
396 static inline qidx_t
397 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
398 {
399 	qidx_t used;
400 
401 	if (pidx > cidx)
402 		used = pidx - cidx;
403 	else if (pidx < cidx)
404 		used = size - cidx + pidx;
405 	else if (gen == 0 && pidx == cidx)
406 		used = 0;
407 	else if (gen == 1 && pidx == cidx)
408 		used = size;
409 	else
410 		panic("bad state");
411 
412 	return (used);
413 }
414 
415 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
416 
417 #define IDXDIFF(head, tail, wrap) \
418 	((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
419 
420 struct iflib_rxq {
421 	if_ctx_t	ifr_ctx;
422 	iflib_fl_t	ifr_fl;
423 	uint64_t	ifr_rx_irq;
424 	struct pfil_head	*pfil;
425 	/*
426 	 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
427 	 * the command queue consumer index.  Otherwise it's unused.
428 	 */
429 	qidx_t		ifr_cq_cidx;
430 	uint16_t	ifr_id;
431 	uint8_t		ifr_nfl;
432 	uint8_t		ifr_ntxqirq;
433 	uint8_t		ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
434 	uint8_t		ifr_fl_offset;
435 	struct lro_ctrl			ifr_lc;
436 	struct grouptask        ifr_task;
437 	struct iflib_filter_info ifr_filter_info;
438 	iflib_dma_info_t		ifr_ifdi;
439 
440 	/* dynamically allocate if any drivers need a value substantially larger than this */
441 	struct if_rxd_frag	ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
442 #ifdef IFLIB_DIAGNOSTICS
443 	uint64_t ifr_cpu_exec_count[256];
444 #endif
445 }  __aligned(CACHE_LINE_SIZE);
446 
447 typedef struct if_rxsd {
448 	caddr_t *ifsd_cl;
449 	iflib_fl_t ifsd_fl;
450 	qidx_t ifsd_cidx;
451 } *if_rxsd_t;
452 
453 /* multiple of word size */
454 #ifdef __LP64__
455 #define PKT_INFO_SIZE	6
456 #define RXD_INFO_SIZE	5
457 #define PKT_TYPE uint64_t
458 #else
459 #define PKT_INFO_SIZE	11
460 #define RXD_INFO_SIZE	8
461 #define PKT_TYPE uint32_t
462 #endif
463 #define PKT_LOOP_BOUND  ((PKT_INFO_SIZE/3)*3)
464 #define RXD_LOOP_BOUND  ((RXD_INFO_SIZE/4)*4)
465 
466 typedef struct if_pkt_info_pad {
467 	PKT_TYPE pkt_val[PKT_INFO_SIZE];
468 } *if_pkt_info_pad_t;
469 typedef struct if_rxd_info_pad {
470 	PKT_TYPE rxd_val[RXD_INFO_SIZE];
471 } *if_rxd_info_pad_t;
472 
473 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
474 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
475 
476 
477 static inline void
478 pkt_info_zero(if_pkt_info_t pi)
479 {
480 	if_pkt_info_pad_t pi_pad;
481 
482 	pi_pad = (if_pkt_info_pad_t)pi;
483 	pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
484 	pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
485 #ifndef __LP64__
486 	pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
487 	pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
488 #endif
489 }
490 
491 static device_method_t iflib_pseudo_methods[] = {
492 	DEVMETHOD(device_attach, noop_attach),
493 	DEVMETHOD(device_detach, iflib_pseudo_detach),
494 	DEVMETHOD_END
495 };
496 
497 driver_t iflib_pseudodriver = {
498 	"iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
499 };
500 
501 static inline void
502 rxd_info_zero(if_rxd_info_t ri)
503 {
504 	if_rxd_info_pad_t ri_pad;
505 	int i;
506 
507 	ri_pad = (if_rxd_info_pad_t)ri;
508 	for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
509 		ri_pad->rxd_val[i] = 0;
510 		ri_pad->rxd_val[i+1] = 0;
511 		ri_pad->rxd_val[i+2] = 0;
512 		ri_pad->rxd_val[i+3] = 0;
513 	}
514 #ifdef __LP64__
515 	ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
516 #endif
517 }
518 
519 /*
520  * Only allow a single packet to take up most 1/nth of the tx ring
521  */
522 #define MAX_SINGLE_PACKET_FRACTION 12
523 #define IF_BAD_DMA (bus_addr_t)-1
524 
525 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
526 
527 #define CTX_LOCK_INIT(_sc)  sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
528 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
529 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
530 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
531 
532 #define STATE_LOCK_INIT(_sc, _name)  mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
533 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
534 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
535 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
536 
537 #define CALLOUT_LOCK(txq)	mtx_lock(&txq->ift_mtx)
538 #define CALLOUT_UNLOCK(txq) 	mtx_unlock(&txq->ift_mtx)
539 
540 void
541 iflib_set_detach(if_ctx_t ctx)
542 {
543 	STATE_LOCK(ctx);
544 	ctx->ifc_flags |= IFC_IN_DETACH;
545 	STATE_UNLOCK(ctx);
546 }
547 
548 /* Our boot-time initialization hook */
549 static int	iflib_module_event_handler(module_t, int, void *);
550 
551 static moduledata_t iflib_moduledata = {
552 	"iflib",
553 	iflib_module_event_handler,
554 	NULL
555 };
556 
557 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
558 MODULE_VERSION(iflib, 1);
559 
560 MODULE_DEPEND(iflib, pci, 1, 1, 1);
561 MODULE_DEPEND(iflib, ether, 1, 1, 1);
562 
563 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
564 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
565 
566 #ifndef IFLIB_DEBUG_COUNTERS
567 #ifdef INVARIANTS
568 #define IFLIB_DEBUG_COUNTERS 1
569 #else
570 #define IFLIB_DEBUG_COUNTERS 0
571 #endif /* !INVARIANTS */
572 #endif
573 
574 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
575                    "iflib driver parameters");
576 
577 /*
578  * XXX need to ensure that this can't accidentally cause the head to be moved backwards
579  */
580 static int iflib_min_tx_latency = 0;
581 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
582 		   &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
583 static int iflib_no_tx_batch = 0;
584 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
585 		   &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
586 
587 
588 #if IFLIB_DEBUG_COUNTERS
589 
590 static int iflib_tx_seen;
591 static int iflib_tx_sent;
592 static int iflib_tx_encap;
593 static int iflib_rx_allocs;
594 static int iflib_fl_refills;
595 static int iflib_fl_refills_large;
596 static int iflib_tx_frees;
597 
598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
599 		   &iflib_tx_seen, 0, "# TX mbufs seen");
600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
601 		   &iflib_tx_sent, 0, "# TX mbufs sent");
602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
603 		   &iflib_tx_encap, 0, "# TX mbufs encapped");
604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
605 		   &iflib_tx_frees, 0, "# TX frees");
606 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
607 		   &iflib_rx_allocs, 0, "# RX allocations");
608 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
609 		   &iflib_fl_refills, 0, "# refills");
610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
611 		   &iflib_fl_refills_large, 0, "# large refills");
612 
613 
614 static int iflib_txq_drain_flushing;
615 static int iflib_txq_drain_oactive;
616 static int iflib_txq_drain_notready;
617 
618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
619 		   &iflib_txq_drain_flushing, 0, "# drain flushes");
620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
621 		   &iflib_txq_drain_oactive, 0, "# drain oactives");
622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
623 		   &iflib_txq_drain_notready, 0, "# drain notready");
624 
625 
626 static int iflib_encap_load_mbuf_fail;
627 static int iflib_encap_pad_mbuf_fail;
628 static int iflib_encap_txq_avail_fail;
629 static int iflib_encap_txd_encap_fail;
630 
631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
632 		   &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
634 		   &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
636 		   &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
638 		   &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
639 
640 static int iflib_task_fn_rxs;
641 static int iflib_rx_intr_enables;
642 static int iflib_fast_intrs;
643 static int iflib_rx_unavail;
644 static int iflib_rx_ctx_inactive;
645 static int iflib_rx_if_input;
646 static int iflib_rxd_flush;
647 
648 static int iflib_verbose_debug;
649 
650 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
651 		   &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
652 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
653 		   &iflib_rx_intr_enables, 0, "# RX intr enables");
654 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
655 		   &iflib_fast_intrs, 0, "# fast_intr calls");
656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
657 		   &iflib_rx_unavail, 0, "# times rxeof called with no available data");
658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
659 		   &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
661 		   &iflib_rx_if_input, 0, "# times rxeof called if_input");
662 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
663 	         &iflib_rxd_flush, 0, "# times rxd_flush called");
664 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
665 		   &iflib_verbose_debug, 0, "enable verbose debugging");
666 
667 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
668 static void
669 iflib_debug_reset(void)
670 {
671 	iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
672 		iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
673 		iflib_txq_drain_flushing = iflib_txq_drain_oactive =
674 		iflib_txq_drain_notready =
675 		iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
676 		iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
677 		iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
678 		iflib_rx_unavail =
679 		iflib_rx_ctx_inactive = iflib_rx_if_input =
680 		iflib_rxd_flush = 0;
681 }
682 
683 #else
684 #define DBG_COUNTER_INC(name)
685 static void iflib_debug_reset(void) {}
686 #endif
687 
688 #define IFLIB_DEBUG 0
689 
690 static void iflib_tx_structures_free(if_ctx_t ctx);
691 static void iflib_rx_structures_free(if_ctx_t ctx);
692 static int iflib_queues_alloc(if_ctx_t ctx);
693 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
694 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
695 static int iflib_qset_structures_setup(if_ctx_t ctx);
696 static int iflib_msix_init(if_ctx_t ctx);
697 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
698 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
699 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
700 #ifdef ALTQ
701 static void iflib_altq_if_start(if_t ifp);
702 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
703 #endif
704 static int iflib_register(if_ctx_t);
705 static void iflib_deregister(if_ctx_t);
706 static void iflib_init_locked(if_ctx_t ctx);
707 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
708 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
709 static void iflib_ifmp_purge(iflib_txq_t txq);
710 static void _iflib_pre_assert(if_softc_ctx_t scctx);
711 static void iflib_if_init_locked(if_ctx_t ctx);
712 static void iflib_free_intr_mem(if_ctx_t ctx);
713 #ifndef __NO_STRICT_ALIGNMENT
714 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
715 #endif
716 
717 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
718     SLIST_HEAD_INITIALIZER(cpu_offsets);
719 struct cpu_offset {
720 	SLIST_ENTRY(cpu_offset) entries;
721 	cpuset_t	set;
722 	unsigned int	refcount;
723 	uint16_t	offset;
724 };
725 static struct mtx cpu_offset_mtx;
726 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
727     MTX_DEF);
728 
729 NETDUMP_DEFINE(iflib);
730 
731 #ifdef DEV_NETMAP
732 #include <sys/selinfo.h>
733 #include <net/netmap.h>
734 #include <dev/netmap/netmap_kern.h>
735 
736 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
737 
738 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
739 
740 /*
741  * device-specific sysctl variables:
742  *
743  * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
744  *	During regular operations the CRC is stripped, but on some
745  *	hardware reception of frames not multiple of 64 is slower,
746  *	so using crcstrip=0 helps in benchmarks.
747  *
748  * iflib_rx_miss, iflib_rx_miss_bufs:
749  *	count packets that might be missed due to lost interrupts.
750  */
751 SYSCTL_DECL(_dev_netmap);
752 /*
753  * The xl driver by default strips CRCs and we do not override it.
754  */
755 
756 int iflib_crcstrip = 1;
757 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
758     CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
759 
760 int iflib_rx_miss, iflib_rx_miss_bufs;
761 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
762     CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
763 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
764     CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
765 
766 /*
767  * Register/unregister. We are already under netmap lock.
768  * Only called on the first register or the last unregister.
769  */
770 static int
771 iflib_netmap_register(struct netmap_adapter *na, int onoff)
772 {
773 	if_t ifp = na->ifp;
774 	if_ctx_t ctx = ifp->if_softc;
775 	int status;
776 
777 	CTX_LOCK(ctx);
778 	IFDI_INTR_DISABLE(ctx);
779 
780 	/* Tell the stack that the interface is no longer active */
781 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
782 
783 	if (!CTX_IS_VF(ctx))
784 		IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
785 
786 	/* enable or disable flags and callbacks in na and ifp */
787 	if (onoff) {
788 		nm_set_native_flags(na);
789 	} else {
790 		nm_clear_native_flags(na);
791 	}
792 	iflib_stop(ctx);
793 	iflib_init_locked(ctx);
794 	IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
795 	status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
796 	if (status)
797 		nm_clear_native_flags(na);
798 	CTX_UNLOCK(ctx);
799 	return (status);
800 }
801 
802 static int
803 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
804 {
805 	struct netmap_adapter *na = kring->na;
806 	u_int const lim = kring->nkr_num_slots - 1;
807 	u_int head = kring->rhead;
808 	struct netmap_ring *ring = kring->ring;
809 	bus_dmamap_t *map;
810 	struct if_rxd_update iru;
811 	if_ctx_t ctx = rxq->ifr_ctx;
812 	iflib_fl_t fl = &rxq->ifr_fl[0];
813 	uint32_t refill_pidx, nic_i;
814 #if IFLIB_DEBUG_COUNTERS
815 	int rf_count = 0;
816 #endif
817 
818 	if (nm_i == head && __predict_true(!init))
819 		return 0;
820 	iru_init(&iru, rxq, 0 /* flid */);
821 	map = fl->ifl_sds.ifsd_map;
822 	refill_pidx = netmap_idx_k2n(kring, nm_i);
823 	/*
824 	 * IMPORTANT: we must leave one free slot in the ring,
825 	 * so move head back by one unit
826 	 */
827 	head = nm_prev(head, lim);
828 	nic_i = UINT_MAX;
829 	DBG_COUNTER_INC(fl_refills);
830 	while (nm_i != head) {
831 #if IFLIB_DEBUG_COUNTERS
832 		if (++rf_count == 9)
833 			DBG_COUNTER_INC(fl_refills_large);
834 #endif
835 		for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
836 			struct netmap_slot *slot = &ring->slot[nm_i];
837 			void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
838 			uint32_t nic_i_dma = refill_pidx;
839 			nic_i = netmap_idx_k2n(kring, nm_i);
840 
841 			MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
842 
843 			if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
844 			        return netmap_ring_reinit(kring);
845 
846 			fl->ifl_vm_addrs[tmp_pidx] = addr;
847 			if (__predict_false(init)) {
848 				netmap_load_map(na, fl->ifl_buf_tag,
849 				    map[nic_i], addr);
850 			} else if (slot->flags & NS_BUF_CHANGED) {
851 				/* buffer has changed, reload map */
852 				netmap_reload_map(na, fl->ifl_buf_tag,
853 				    map[nic_i], addr);
854 			}
855 			slot->flags &= ~NS_BUF_CHANGED;
856 
857 			nm_i = nm_next(nm_i, lim);
858 			fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
859 			if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
860 				continue;
861 
862 			iru.iru_pidx = refill_pidx;
863 			iru.iru_count = tmp_pidx+1;
864 			ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
865 			refill_pidx = nic_i;
866 			for (int n = 0; n < iru.iru_count; n++) {
867 				bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma],
868 						BUS_DMASYNC_PREREAD);
869 				/* XXX - change this to not use the netmap func*/
870 				nic_i_dma = nm_next(nic_i_dma, lim);
871 			}
872 		}
873 	}
874 	kring->nr_hwcur = head;
875 
876 	bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
877 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
878 	if (__predict_true(nic_i != UINT_MAX)) {
879 		ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
880 		DBG_COUNTER_INC(rxd_flush);
881 	}
882 	return (0);
883 }
884 
885 /*
886  * Reconcile kernel and user view of the transmit ring.
887  *
888  * All information is in the kring.
889  * Userspace wants to send packets up to the one before kring->rhead,
890  * kernel knows kring->nr_hwcur is the first unsent packet.
891  *
892  * Here we push packets out (as many as possible), and possibly
893  * reclaim buffers from previously completed transmission.
894  *
895  * The caller (netmap) guarantees that there is only one instance
896  * running at any time. Any interference with other driver
897  * methods should be handled by the individual drivers.
898  */
899 static int
900 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
901 {
902 	struct netmap_adapter *na = kring->na;
903 	if_t ifp = na->ifp;
904 	struct netmap_ring *ring = kring->ring;
905 	u_int nm_i;	/* index into the netmap kring */
906 	u_int nic_i;	/* index into the NIC ring */
907 	u_int n;
908 	u_int const lim = kring->nkr_num_slots - 1;
909 	u_int const head = kring->rhead;
910 	struct if_pkt_info pi;
911 
912 	/*
913 	 * interrupts on every tx packet are expensive so request
914 	 * them every half ring, or where NS_REPORT is set
915 	 */
916 	u_int report_frequency = kring->nkr_num_slots >> 1;
917 	/* device-specific */
918 	if_ctx_t ctx = ifp->if_softc;
919 	iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
920 
921 	bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
922 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
923 
924 	/*
925 	 * First part: process new packets to send.
926 	 * nm_i is the current index in the netmap kring,
927 	 * nic_i is the corresponding index in the NIC ring.
928 	 *
929 	 * If we have packets to send (nm_i != head)
930 	 * iterate over the netmap ring, fetch length and update
931 	 * the corresponding slot in the NIC ring. Some drivers also
932 	 * need to update the buffer's physical address in the NIC slot
933 	 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
934 	 *
935 	 * The netmap_reload_map() calls is especially expensive,
936 	 * even when (as in this case) the tag is 0, so do only
937 	 * when the buffer has actually changed.
938 	 *
939 	 * If possible do not set the report/intr bit on all slots,
940 	 * but only a few times per ring or when NS_REPORT is set.
941 	 *
942 	 * Finally, on 10G and faster drivers, it might be useful
943 	 * to prefetch the next slot and txr entry.
944 	 */
945 
946 	nm_i = kring->nr_hwcur;
947 	if (nm_i != head) {	/* we have new packets to send */
948 		pkt_info_zero(&pi);
949 		pi.ipi_segs = txq->ift_segs;
950 		pi.ipi_qsidx = kring->ring_id;
951 		nic_i = netmap_idx_k2n(kring, nm_i);
952 
953 		__builtin_prefetch(&ring->slot[nm_i]);
954 		__builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
955 		__builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
956 
957 		for (n = 0; nm_i != head; n++) {
958 			struct netmap_slot *slot = &ring->slot[nm_i];
959 			u_int len = slot->len;
960 			uint64_t paddr;
961 			void *addr = PNMB(na, slot, &paddr);
962 			int flags = (slot->flags & NS_REPORT ||
963 				nic_i == 0 || nic_i == report_frequency) ?
964 				IPI_TX_INTR : 0;
965 
966 			/* device-specific */
967 			pi.ipi_len = len;
968 			pi.ipi_segs[0].ds_addr = paddr;
969 			pi.ipi_segs[0].ds_len = len;
970 			pi.ipi_nsegs = 1;
971 			pi.ipi_ndescs = 0;
972 			pi.ipi_pidx = nic_i;
973 			pi.ipi_flags = flags;
974 
975 			/* Fill the slot in the NIC ring. */
976 			ctx->isc_txd_encap(ctx->ifc_softc, &pi);
977 			DBG_COUNTER_INC(tx_encap);
978 
979 			/* prefetch for next round */
980 			__builtin_prefetch(&ring->slot[nm_i + 1]);
981 			__builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
982 			__builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
983 
984 			NM_CHECK_ADDR_LEN(na, addr, len);
985 
986 			if (slot->flags & NS_BUF_CHANGED) {
987 				/* buffer has changed, reload map */
988 				netmap_reload_map(na, txq->ift_buf_tag,
989 				    txq->ift_sds.ifsd_map[nic_i], addr);
990 			}
991 			/* make sure changes to the buffer are synced */
992 			bus_dmamap_sync(txq->ift_buf_tag,
993 			    txq->ift_sds.ifsd_map[nic_i],
994 			    BUS_DMASYNC_PREWRITE);
995 
996 			slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
997 			nm_i = nm_next(nm_i, lim);
998 			nic_i = nm_next(nic_i, lim);
999 		}
1000 		kring->nr_hwcur = nm_i;
1001 
1002 		/* synchronize the NIC ring */
1003 		bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1004 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1005 
1006 		/* (re)start the tx unit up to slot nic_i (excluded) */
1007 		ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1008 	}
1009 
1010 	/*
1011 	 * Second part: reclaim buffers for completed transmissions.
1012 	 *
1013 	 * If there are unclaimed buffers, attempt to reclaim them.
1014 	 * If none are reclaimed, and TX IRQs are not in use, do an initial
1015 	 * minimal delay, then trigger the tx handler which will spin in the
1016 	 * group task queue.
1017 	 */
1018 	if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1019 		if (iflib_tx_credits_update(ctx, txq)) {
1020 			/* some tx completed, increment avail */
1021 			nic_i = txq->ift_cidx_processed;
1022 			kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1023 		}
1024 	}
1025 	if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1026 		if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1027 			callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1028 			    iflib_timer, txq, txq->ift_timer.c_cpu);
1029 	}
1030 	return (0);
1031 }
1032 
1033 /*
1034  * Reconcile kernel and user view of the receive ring.
1035  * Same as for the txsync, this routine must be efficient.
1036  * The caller guarantees a single invocations, but races against
1037  * the rest of the driver should be handled here.
1038  *
1039  * On call, kring->rhead is the first packet that userspace wants
1040  * to keep, and kring->rcur is the wakeup point.
1041  * The kernel has previously reported packets up to kring->rtail.
1042  *
1043  * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1044  * of whether or not we received an interrupt.
1045  */
1046 static int
1047 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1048 {
1049 	struct netmap_adapter *na = kring->na;
1050 	struct netmap_ring *ring = kring->ring;
1051 	if_t ifp = na->ifp;
1052 	iflib_fl_t fl;
1053 	uint32_t nm_i;	/* index into the netmap ring */
1054 	uint32_t nic_i;	/* index into the NIC ring */
1055 	u_int i, n;
1056 	u_int const lim = kring->nkr_num_slots - 1;
1057 	u_int const head = kring->rhead;
1058 	int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1059 	struct if_rxd_info ri;
1060 
1061 	if_ctx_t ctx = ifp->if_softc;
1062 	iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1063 	if (head > lim)
1064 		return netmap_ring_reinit(kring);
1065 
1066 	/*
1067 	 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far.
1068 	 */
1069 
1070 	for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1071 		bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1072 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1073 	}
1074 
1075 	/*
1076 	 * First part: import newly received packets.
1077 	 *
1078 	 * nm_i is the index of the next free slot in the netmap ring,
1079 	 * nic_i is the index of the next received packet in the NIC ring,
1080 	 * and they may differ in case if_init() has been called while
1081 	 * in netmap mode. For the receive ring we have
1082 	 *
1083 	 *	nic_i = rxr->next_check;
1084 	 *	nm_i = kring->nr_hwtail (previous)
1085 	 * and
1086 	 *	nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1087 	 *
1088 	 * rxr->next_check is set to 0 on a ring reinit
1089 	 */
1090 	if (netmap_no_pendintr || force_update) {
1091 		int crclen = iflib_crcstrip ? 0 : 4;
1092 		int error, avail;
1093 
1094 		for (i = 0; i < rxq->ifr_nfl; i++) {
1095 			fl = &rxq->ifr_fl[i];
1096 			nic_i = fl->ifl_cidx;
1097 			nm_i = netmap_idx_n2k(kring, nic_i);
1098 			avail = ctx->isc_rxd_available(ctx->ifc_softc,
1099 			    rxq->ifr_id, nic_i, USHRT_MAX);
1100 			for (n = 0; avail > 0; n++, avail--) {
1101 				rxd_info_zero(&ri);
1102 				ri.iri_frags = rxq->ifr_frags;
1103 				ri.iri_qsidx = kring->ring_id;
1104 				ri.iri_ifp = ctx->ifc_ifp;
1105 				ri.iri_cidx = nic_i;
1106 
1107 				error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1108 				ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1109 				ring->slot[nm_i].flags = 0;
1110 				bus_dmamap_sync(fl->ifl_buf_tag,
1111 				    fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1112 				nm_i = nm_next(nm_i, lim);
1113 				nic_i = nm_next(nic_i, lim);
1114 			}
1115 			if (n) { /* update the state variables */
1116 				if (netmap_no_pendintr && !force_update) {
1117 					/* diagnostics */
1118 					iflib_rx_miss ++;
1119 					iflib_rx_miss_bufs += n;
1120 				}
1121 				fl->ifl_cidx = nic_i;
1122 				kring->nr_hwtail = nm_i;
1123 			}
1124 			kring->nr_kflags &= ~NKR_PENDINTR;
1125 		}
1126 	}
1127 	/*
1128 	 * Second part: skip past packets that userspace has released.
1129 	 * (kring->nr_hwcur to head excluded),
1130 	 * and make the buffers available for reception.
1131 	 * As usual nm_i is the index in the netmap ring,
1132 	 * nic_i is the index in the NIC ring, and
1133 	 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1134 	 */
1135 	/* XXX not sure how this will work with multiple free lists */
1136 	nm_i = kring->nr_hwcur;
1137 
1138 	return (netmap_fl_refill(rxq, kring, nm_i, false));
1139 }
1140 
1141 static void
1142 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1143 {
1144 	if_ctx_t ctx = na->ifp->if_softc;
1145 
1146 	CTX_LOCK(ctx);
1147 	if (onoff) {
1148 		IFDI_INTR_ENABLE(ctx);
1149 	} else {
1150 		IFDI_INTR_DISABLE(ctx);
1151 	}
1152 	CTX_UNLOCK(ctx);
1153 }
1154 
1155 
1156 static int
1157 iflib_netmap_attach(if_ctx_t ctx)
1158 {
1159 	struct netmap_adapter na;
1160 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1161 
1162 	bzero(&na, sizeof(na));
1163 
1164 	na.ifp = ctx->ifc_ifp;
1165 	na.na_flags = NAF_BDG_MAYSLEEP;
1166 	MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1167 	MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1168 
1169 	na.num_tx_desc = scctx->isc_ntxd[0];
1170 	na.num_rx_desc = scctx->isc_nrxd[0];
1171 	na.nm_txsync = iflib_netmap_txsync;
1172 	na.nm_rxsync = iflib_netmap_rxsync;
1173 	na.nm_register = iflib_netmap_register;
1174 	na.nm_intr = iflib_netmap_intr;
1175 	na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1176 	na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1177 	return (netmap_attach(&na));
1178 }
1179 
1180 static void
1181 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1182 {
1183 	struct netmap_adapter *na = NA(ctx->ifc_ifp);
1184 	struct netmap_slot *slot;
1185 
1186 	slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1187 	if (slot == NULL)
1188 		return;
1189 	for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1190 
1191 		/*
1192 		 * In netmap mode, set the map for the packet buffer.
1193 		 * NOTE: Some drivers (not this one) also need to set
1194 		 * the physical buffer address in the NIC ring.
1195 		 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1196 		 * netmap slot index, si
1197 		 */
1198 		int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1199 		netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1200 		    NMB(na, slot + si));
1201 	}
1202 }
1203 
1204 static void
1205 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1206 {
1207 	struct netmap_adapter *na = NA(ctx->ifc_ifp);
1208 	struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1209 	struct netmap_slot *slot;
1210 	uint32_t nm_i;
1211 
1212 	slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1213 	if (slot == NULL)
1214 		return;
1215 	nm_i = netmap_idx_n2k(kring, 0);
1216 	netmap_fl_refill(rxq, kring, nm_i, true);
1217 }
1218 
1219 static void
1220 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on)
1221 {
1222 	struct netmap_kring *kring;
1223 	uint16_t txqid;
1224 
1225 	txqid = txq->ift_id;
1226 	kring = NA(ctx->ifc_ifp)->tx_rings[txqid];
1227 
1228 	if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1229 		bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1230 		    BUS_DMASYNC_POSTREAD);
1231 		if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1232 			netmap_tx_irq(ctx->ifc_ifp, txqid);
1233 		if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1234 			if (hz < 2000)
1235 				*reset_on = 1;
1236 			else
1237 				*reset_on = hz / 1000;
1238 		}
1239 	}
1240 }
1241 
1242 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1243 
1244 #else
1245 #define iflib_netmap_txq_init(ctx, txq)
1246 #define iflib_netmap_rxq_init(ctx, rxq)
1247 #define iflib_netmap_detach(ifp)
1248 
1249 #define iflib_netmap_attach(ctx) (0)
1250 #define netmap_rx_irq(ifp, qid, budget) (0)
1251 #define netmap_tx_irq(ifp, qid) do {} while (0)
1252 #define iflib_netmap_timer_adjust(ctx, txq, reset_on)
1253 #endif
1254 
1255 #if defined(__i386__) || defined(__amd64__)
1256 static __inline void
1257 prefetch(void *x)
1258 {
1259 	__asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1260 }
1261 static __inline void
1262 prefetch2cachelines(void *x)
1263 {
1264 	__asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1265 #if (CACHE_LINE_SIZE < 128)
1266 	__asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1267 #endif
1268 }
1269 #else
1270 #define prefetch(x)
1271 #define prefetch2cachelines(x)
1272 #endif
1273 
1274 static void
1275 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1276 {
1277 	iflib_fl_t fl;
1278 
1279 	fl = &rxq->ifr_fl[flid];
1280 	iru->iru_paddrs = fl->ifl_bus_addrs;
1281 	iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1282 	iru->iru_idxs = fl->ifl_rxd_idxs;
1283 	iru->iru_qsidx = rxq->ifr_id;
1284 	iru->iru_buf_size = fl->ifl_buf_size;
1285 	iru->iru_flidx = fl->ifl_id;
1286 }
1287 
1288 static void
1289 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1290 {
1291 	if (err)
1292 		return;
1293 	*(bus_addr_t *) arg = segs[0].ds_addr;
1294 }
1295 
1296 int
1297 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1298 {
1299 	int err;
1300 	device_t dev = ctx->ifc_dev;
1301 
1302 	err = bus_dma_tag_create(bus_get_dma_tag(dev),	/* parent */
1303 				align, 0,		/* alignment, bounds */
1304 				BUS_SPACE_MAXADDR,	/* lowaddr */
1305 				BUS_SPACE_MAXADDR,	/* highaddr */
1306 				NULL, NULL,		/* filter, filterarg */
1307 				size,			/* maxsize */
1308 				1,			/* nsegments */
1309 				size,			/* maxsegsize */
1310 				BUS_DMA_ALLOCNOW,	/* flags */
1311 				NULL,			/* lockfunc */
1312 				NULL,			/* lockarg */
1313 				&dma->idi_tag);
1314 	if (err) {
1315 		device_printf(dev,
1316 		    "%s: bus_dma_tag_create failed: %d\n",
1317 		    __func__, err);
1318 		goto fail_0;
1319 	}
1320 
1321 	err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1322 	    BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1323 	if (err) {
1324 		device_printf(dev,
1325 		    "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1326 		    __func__, (uintmax_t)size, err);
1327 		goto fail_1;
1328 	}
1329 
1330 	dma->idi_paddr = IF_BAD_DMA;
1331 	err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1332 	    size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1333 	if (err || dma->idi_paddr == IF_BAD_DMA) {
1334 		device_printf(dev,
1335 		    "%s: bus_dmamap_load failed: %d\n",
1336 		    __func__, err);
1337 		goto fail_2;
1338 	}
1339 
1340 	dma->idi_size = size;
1341 	return (0);
1342 
1343 fail_2:
1344 	bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1345 fail_1:
1346 	bus_dma_tag_destroy(dma->idi_tag);
1347 fail_0:
1348 	dma->idi_tag = NULL;
1349 
1350 	return (err);
1351 }
1352 
1353 int
1354 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1355 {
1356 	if_shared_ctx_t sctx = ctx->ifc_sctx;
1357 
1358 	KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1359 
1360 	return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1361 }
1362 
1363 int
1364 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1365 {
1366 	int i, err;
1367 	iflib_dma_info_t *dmaiter;
1368 
1369 	dmaiter = dmalist;
1370 	for (i = 0; i < count; i++, dmaiter++) {
1371 		if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1372 			break;
1373 	}
1374 	if (err)
1375 		iflib_dma_free_multi(dmalist, i);
1376 	return (err);
1377 }
1378 
1379 void
1380 iflib_dma_free(iflib_dma_info_t dma)
1381 {
1382 	if (dma->idi_tag == NULL)
1383 		return;
1384 	if (dma->idi_paddr != IF_BAD_DMA) {
1385 		bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1386 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1387 		bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1388 		dma->idi_paddr = IF_BAD_DMA;
1389 	}
1390 	if (dma->idi_vaddr != NULL) {
1391 		bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1392 		dma->idi_vaddr = NULL;
1393 	}
1394 	bus_dma_tag_destroy(dma->idi_tag);
1395 	dma->idi_tag = NULL;
1396 }
1397 
1398 void
1399 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1400 {
1401 	int i;
1402 	iflib_dma_info_t *dmaiter = dmalist;
1403 
1404 	for (i = 0; i < count; i++, dmaiter++)
1405 		iflib_dma_free(*dmaiter);
1406 }
1407 
1408 #ifdef EARLY_AP_STARTUP
1409 static const int iflib_started = 1;
1410 #else
1411 /*
1412  * We used to abuse the smp_started flag to decide if the queues have been
1413  * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1414  * That gave bad races, since the SYSINIT() runs strictly after smp_started
1415  * is set.  Run a SYSINIT() strictly after that to just set a usable
1416  * completion flag.
1417  */
1418 
1419 static int iflib_started;
1420 
1421 static void
1422 iflib_record_started(void *arg)
1423 {
1424 	iflib_started = 1;
1425 }
1426 
1427 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1428 	iflib_record_started, NULL);
1429 #endif
1430 
1431 static int
1432 iflib_fast_intr(void *arg)
1433 {
1434 	iflib_filter_info_t info = arg;
1435 	struct grouptask *gtask = info->ifi_task;
1436 	int result;
1437 
1438 	if (!iflib_started)
1439 		return (FILTER_STRAY);
1440 
1441 	DBG_COUNTER_INC(fast_intrs);
1442 	if (info->ifi_filter != NULL) {
1443 		result = info->ifi_filter(info->ifi_filter_arg);
1444 		if ((result & FILTER_SCHEDULE_THREAD) == 0)
1445 			return (result);
1446 	}
1447 
1448 	GROUPTASK_ENQUEUE(gtask);
1449 	return (FILTER_HANDLED);
1450 }
1451 
1452 static int
1453 iflib_fast_intr_rxtx(void *arg)
1454 {
1455 	iflib_filter_info_t info = arg;
1456 	struct grouptask *gtask = info->ifi_task;
1457 	if_ctx_t ctx;
1458 	iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1459 	iflib_txq_t txq;
1460 	void *sc;
1461 	int i, cidx, result;
1462 	qidx_t txqid;
1463 	bool intr_enable, intr_legacy;
1464 
1465 	if (!iflib_started)
1466 		return (FILTER_STRAY);
1467 
1468 	DBG_COUNTER_INC(fast_intrs);
1469 	if (info->ifi_filter != NULL) {
1470 		result = info->ifi_filter(info->ifi_filter_arg);
1471 		if ((result & FILTER_SCHEDULE_THREAD) == 0)
1472 			return (result);
1473 	}
1474 
1475 	ctx = rxq->ifr_ctx;
1476 	sc = ctx->ifc_softc;
1477 	intr_enable = false;
1478 	intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1479 	MPASS(rxq->ifr_ntxqirq);
1480 	for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1481 		txqid = rxq->ifr_txqid[i];
1482 		txq = &ctx->ifc_txqs[txqid];
1483 		bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1484 		    BUS_DMASYNC_POSTREAD);
1485 		if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1486 			if (intr_legacy)
1487 				intr_enable = true;
1488 			else
1489 				IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1490 			continue;
1491 		}
1492 		GROUPTASK_ENQUEUE(&txq->ift_task);
1493 	}
1494 	if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1495 		cidx = rxq->ifr_cq_cidx;
1496 	else
1497 		cidx = rxq->ifr_fl[0].ifl_cidx;
1498 	if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1499 		GROUPTASK_ENQUEUE(gtask);
1500 	else {
1501 		if (intr_legacy)
1502 			intr_enable = true;
1503 		else
1504 			IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1505 		DBG_COUNTER_INC(rx_intr_enables);
1506 	}
1507 	if (intr_enable)
1508 		IFDI_INTR_ENABLE(ctx);
1509 	return (FILTER_HANDLED);
1510 }
1511 
1512 
1513 static int
1514 iflib_fast_intr_ctx(void *arg)
1515 {
1516 	iflib_filter_info_t info = arg;
1517 	struct grouptask *gtask = info->ifi_task;
1518 	int result;
1519 
1520 	if (!iflib_started)
1521 		return (FILTER_STRAY);
1522 
1523 	DBG_COUNTER_INC(fast_intrs);
1524 	if (info->ifi_filter != NULL) {
1525 		result = info->ifi_filter(info->ifi_filter_arg);
1526 		if ((result & FILTER_SCHEDULE_THREAD) == 0)
1527 			return (result);
1528 	}
1529 
1530 	GROUPTASK_ENQUEUE(gtask);
1531 	return (FILTER_HANDLED);
1532 }
1533 
1534 static int
1535 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1536 		 driver_filter_t filter, driver_intr_t handler, void *arg,
1537 		 const char *name)
1538 {
1539 	struct resource *res;
1540 	void *tag = NULL;
1541 	device_t dev = ctx->ifc_dev;
1542 	int flags, i, rc;
1543 
1544 	flags = RF_ACTIVE;
1545 	if (ctx->ifc_flags & IFC_LEGACY)
1546 		flags |= RF_SHAREABLE;
1547 	MPASS(rid < 512);
1548 	i = rid;
1549 	res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags);
1550 	if (res == NULL) {
1551 		device_printf(dev,
1552 		    "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1553 		return (ENOMEM);
1554 	}
1555 	irq->ii_res = res;
1556 	KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1557 	rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1558 						filter, handler, arg, &tag);
1559 	if (rc != 0) {
1560 		device_printf(dev,
1561 		    "failed to setup interrupt for rid %d, name %s: %d\n",
1562 					  rid, name ? name : "unknown", rc);
1563 		return (rc);
1564 	} else if (name)
1565 		bus_describe_intr(dev, res, tag, "%s", name);
1566 
1567 	irq->ii_tag = tag;
1568 	return (0);
1569 }
1570 
1571 /*********************************************************************
1572  *
1573  *  Allocate DMA resources for TX buffers as well as memory for the TX
1574  *  mbuf map.  TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1575  *  iflib_sw_tx_desc_array structure, storing all the information that
1576  *  is needed to transmit a packet on the wire.  This is called only
1577  *  once at attach, setup is done every reset.
1578  *
1579  **********************************************************************/
1580 static int
1581 iflib_txsd_alloc(iflib_txq_t txq)
1582 {
1583 	if_ctx_t ctx = txq->ift_ctx;
1584 	if_shared_ctx_t sctx = ctx->ifc_sctx;
1585 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1586 	device_t dev = ctx->ifc_dev;
1587 	bus_size_t tsomaxsize;
1588 	int err, nsegments, ntsosegments;
1589 	bool tso;
1590 
1591 	nsegments = scctx->isc_tx_nsegments;
1592 	ntsosegments = scctx->isc_tx_tso_segments_max;
1593 	tsomaxsize = scctx->isc_tx_tso_size_max;
1594 	if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1595 		tsomaxsize += sizeof(struct ether_vlan_header);
1596 	MPASS(scctx->isc_ntxd[0] > 0);
1597 	MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1598 	MPASS(nsegments > 0);
1599 	if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1600 		MPASS(ntsosegments > 0);
1601 		MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1602 	}
1603 
1604 	/*
1605 	 * Set up DMA tags for TX buffers.
1606 	 */
1607 	if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1608 			       1, 0,			/* alignment, bounds */
1609 			       BUS_SPACE_MAXADDR,	/* lowaddr */
1610 			       BUS_SPACE_MAXADDR,	/* highaddr */
1611 			       NULL, NULL,		/* filter, filterarg */
1612 			       sctx->isc_tx_maxsize,		/* maxsize */
1613 			       nsegments,	/* nsegments */
1614 			       sctx->isc_tx_maxsegsize,	/* maxsegsize */
1615 			       0,			/* flags */
1616 			       NULL,			/* lockfunc */
1617 			       NULL,			/* lockfuncarg */
1618 			       &txq->ift_buf_tag))) {
1619 		device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1620 		device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1621 		    (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1622 		goto fail;
1623 	}
1624 	tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1625 	if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1626 			       1, 0,			/* alignment, bounds */
1627 			       BUS_SPACE_MAXADDR,	/* lowaddr */
1628 			       BUS_SPACE_MAXADDR,	/* highaddr */
1629 			       NULL, NULL,		/* filter, filterarg */
1630 			       tsomaxsize,		/* maxsize */
1631 			       ntsosegments,	/* nsegments */
1632 			       sctx->isc_tso_maxsegsize,/* maxsegsize */
1633 			       0,			/* flags */
1634 			       NULL,			/* lockfunc */
1635 			       NULL,			/* lockfuncarg */
1636 			       &txq->ift_tso_buf_tag))) {
1637 		device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1638 		    err);
1639 		goto fail;
1640 	}
1641 
1642 	/* Allocate memory for the TX mbuf map. */
1643 	if (!(txq->ift_sds.ifsd_m =
1644 	    (struct mbuf **) malloc(sizeof(struct mbuf *) *
1645 	    scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1646 		device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1647 		err = ENOMEM;
1648 		goto fail;
1649 	}
1650 
1651 	/*
1652 	 * Create the DMA maps for TX buffers.
1653 	 */
1654 	if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1655 	    sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1656 	    M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1657 		device_printf(dev,
1658 		    "Unable to allocate TX buffer DMA map memory\n");
1659 		err = ENOMEM;
1660 		goto fail;
1661 	}
1662 	if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1663 	    sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1664 	    M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1665 		device_printf(dev,
1666 		    "Unable to allocate TSO TX buffer map memory\n");
1667 		err = ENOMEM;
1668 		goto fail;
1669 	}
1670 	for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1671 		err = bus_dmamap_create(txq->ift_buf_tag, 0,
1672 		    &txq->ift_sds.ifsd_map[i]);
1673 		if (err != 0) {
1674 			device_printf(dev, "Unable to create TX DMA map\n");
1675 			goto fail;
1676 		}
1677 		if (!tso)
1678 			continue;
1679 		err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1680 		    &txq->ift_sds.ifsd_tso_map[i]);
1681 		if (err != 0) {
1682 			device_printf(dev, "Unable to create TSO TX DMA map\n");
1683 			goto fail;
1684 		}
1685 	}
1686 	return (0);
1687 fail:
1688 	/* We free all, it handles case where we are in the middle */
1689 	iflib_tx_structures_free(ctx);
1690 	return (err);
1691 }
1692 
1693 static void
1694 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1695 {
1696 	bus_dmamap_t map;
1697 
1698 	map = NULL;
1699 	if (txq->ift_sds.ifsd_map != NULL)
1700 		map = txq->ift_sds.ifsd_map[i];
1701 	if (map != NULL) {
1702 		bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1703 		bus_dmamap_unload(txq->ift_buf_tag, map);
1704 		bus_dmamap_destroy(txq->ift_buf_tag, map);
1705 		txq->ift_sds.ifsd_map[i] = NULL;
1706 	}
1707 
1708 	map = NULL;
1709 	if (txq->ift_sds.ifsd_tso_map != NULL)
1710 		map = txq->ift_sds.ifsd_tso_map[i];
1711 	if (map != NULL) {
1712 		bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1713 		    BUS_DMASYNC_POSTWRITE);
1714 		bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1715 		bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1716 		txq->ift_sds.ifsd_tso_map[i] = NULL;
1717 	}
1718 }
1719 
1720 static void
1721 iflib_txq_destroy(iflib_txq_t txq)
1722 {
1723 	if_ctx_t ctx = txq->ift_ctx;
1724 
1725 	for (int i = 0; i < txq->ift_size; i++)
1726 		iflib_txsd_destroy(ctx, txq, i);
1727 	if (txq->ift_sds.ifsd_map != NULL) {
1728 		free(txq->ift_sds.ifsd_map, M_IFLIB);
1729 		txq->ift_sds.ifsd_map = NULL;
1730 	}
1731 	if (txq->ift_sds.ifsd_tso_map != NULL) {
1732 		free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1733 		txq->ift_sds.ifsd_tso_map = NULL;
1734 	}
1735 	if (txq->ift_sds.ifsd_m != NULL) {
1736 		free(txq->ift_sds.ifsd_m, M_IFLIB);
1737 		txq->ift_sds.ifsd_m = NULL;
1738 	}
1739 	if (txq->ift_buf_tag != NULL) {
1740 		bus_dma_tag_destroy(txq->ift_buf_tag);
1741 		txq->ift_buf_tag = NULL;
1742 	}
1743 	if (txq->ift_tso_buf_tag != NULL) {
1744 		bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1745 		txq->ift_tso_buf_tag = NULL;
1746 	}
1747 }
1748 
1749 static void
1750 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1751 {
1752 	struct mbuf **mp;
1753 
1754 	mp = &txq->ift_sds.ifsd_m[i];
1755 	if (*mp == NULL)
1756 		return;
1757 
1758 	if (txq->ift_sds.ifsd_map != NULL) {
1759 		bus_dmamap_sync(txq->ift_buf_tag,
1760 		    txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1761 		bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1762 	}
1763 	if (txq->ift_sds.ifsd_tso_map != NULL) {
1764 		bus_dmamap_sync(txq->ift_tso_buf_tag,
1765 		    txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1766 		bus_dmamap_unload(txq->ift_tso_buf_tag,
1767 		    txq->ift_sds.ifsd_tso_map[i]);
1768 	}
1769 	m_free(*mp);
1770 	DBG_COUNTER_INC(tx_frees);
1771 	*mp = NULL;
1772 }
1773 
1774 static int
1775 iflib_txq_setup(iflib_txq_t txq)
1776 {
1777 	if_ctx_t ctx = txq->ift_ctx;
1778 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1779 	if_shared_ctx_t sctx = ctx->ifc_sctx;
1780 	iflib_dma_info_t di;
1781 	int i;
1782 
1783 	/* Set number of descriptors available */
1784 	txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1785 	/* XXX make configurable */
1786 	txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1787 
1788 	/* Reset indices */
1789 	txq->ift_cidx_processed = 0;
1790 	txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1791 	txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1792 
1793 	for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1794 		bzero((void *)di->idi_vaddr, di->idi_size);
1795 
1796 	IFDI_TXQ_SETUP(ctx, txq->ift_id);
1797 	for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1798 		bus_dmamap_sync(di->idi_tag, di->idi_map,
1799 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1800 	return (0);
1801 }
1802 
1803 /*********************************************************************
1804  *
1805  *  Allocate DMA resources for RX buffers as well as memory for the RX
1806  *  mbuf map, direct RX cluster pointer map and RX cluster bus address
1807  *  map.  RX DMA map, RX mbuf map, direct RX cluster pointer map and
1808  *  RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1809  *  Since we use use one entry in iflib_sw_rx_desc_array per received
1810  *  packet, the maximum number of entries we'll need is equal to the
1811  *  number of hardware receive descriptors that we've allocated.
1812  *
1813  **********************************************************************/
1814 static int
1815 iflib_rxsd_alloc(iflib_rxq_t rxq)
1816 {
1817 	if_ctx_t ctx = rxq->ifr_ctx;
1818 	if_shared_ctx_t sctx = ctx->ifc_sctx;
1819 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1820 	device_t dev = ctx->ifc_dev;
1821 	iflib_fl_t fl;
1822 	int			err;
1823 
1824 	MPASS(scctx->isc_nrxd[0] > 0);
1825 	MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1826 
1827 	fl = rxq->ifr_fl;
1828 	for (int i = 0; i <  rxq->ifr_nfl; i++, fl++) {
1829 		fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1830 		/* Set up DMA tag for RX buffers. */
1831 		err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1832 					 1, 0,			/* alignment, bounds */
1833 					 BUS_SPACE_MAXADDR,	/* lowaddr */
1834 					 BUS_SPACE_MAXADDR,	/* highaddr */
1835 					 NULL, NULL,		/* filter, filterarg */
1836 					 sctx->isc_rx_maxsize,	/* maxsize */
1837 					 sctx->isc_rx_nsegments,	/* nsegments */
1838 					 sctx->isc_rx_maxsegsize,	/* maxsegsize */
1839 					 0,			/* flags */
1840 					 NULL,			/* lockfunc */
1841 					 NULL,			/* lockarg */
1842 					 &fl->ifl_buf_tag);
1843 		if (err) {
1844 			device_printf(dev,
1845 			    "Unable to allocate RX DMA tag: %d\n", err);
1846 			goto fail;
1847 		}
1848 
1849 		/* Allocate memory for the RX mbuf map. */
1850 		if (!(fl->ifl_sds.ifsd_m =
1851 		      (struct mbuf **) malloc(sizeof(struct mbuf *) *
1852 					      scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1853 			device_printf(dev,
1854 			    "Unable to allocate RX mbuf map memory\n");
1855 			err = ENOMEM;
1856 			goto fail;
1857 		}
1858 
1859 		/* Allocate memory for the direct RX cluster pointer map. */
1860 		if (!(fl->ifl_sds.ifsd_cl =
1861 		      (caddr_t *) malloc(sizeof(caddr_t) *
1862 					      scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1863 			device_printf(dev,
1864 			    "Unable to allocate RX cluster map memory\n");
1865 			err = ENOMEM;
1866 			goto fail;
1867 		}
1868 
1869 		/* Allocate memory for the RX cluster bus address map. */
1870 		if (!(fl->ifl_sds.ifsd_ba =
1871 		      (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1872 					      scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1873 			device_printf(dev,
1874 			    "Unable to allocate RX bus address map memory\n");
1875 			err = ENOMEM;
1876 			goto fail;
1877 		}
1878 
1879 		/*
1880 		 * Create the DMA maps for RX buffers.
1881 		 */
1882 		if (!(fl->ifl_sds.ifsd_map =
1883 		      (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1884 			device_printf(dev,
1885 			    "Unable to allocate RX buffer DMA map memory\n");
1886 			err = ENOMEM;
1887 			goto fail;
1888 		}
1889 		for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1890 			err = bus_dmamap_create(fl->ifl_buf_tag, 0,
1891 			    &fl->ifl_sds.ifsd_map[i]);
1892 			if (err != 0) {
1893 				device_printf(dev, "Unable to create RX buffer DMA map\n");
1894 				goto fail;
1895 			}
1896 		}
1897 	}
1898 	return (0);
1899 
1900 fail:
1901 	iflib_rx_structures_free(ctx);
1902 	return (err);
1903 }
1904 
1905 
1906 /*
1907  * Internal service routines
1908  */
1909 
1910 struct rxq_refill_cb_arg {
1911 	int               error;
1912 	bus_dma_segment_t seg;
1913 	int               nseg;
1914 };
1915 
1916 static void
1917 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1918 {
1919 	struct rxq_refill_cb_arg *cb_arg = arg;
1920 
1921 	cb_arg->error = error;
1922 	cb_arg->seg = segs[0];
1923 	cb_arg->nseg = nseg;
1924 }
1925 
1926 /**
1927  * _iflib_fl_refill - refill an rxq free-buffer list
1928  * @ctx: the iflib context
1929  * @fl: the free list to refill
1930  * @count: the number of new buffers to allocate
1931  *
1932  * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
1933  * The caller must assure that @count does not exceed the queue's capacity.
1934  */
1935 static void
1936 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1937 {
1938 	struct if_rxd_update iru;
1939 	struct rxq_refill_cb_arg cb_arg;
1940 	struct mbuf *m;
1941 	caddr_t cl, *sd_cl;
1942 	struct mbuf **sd_m;
1943 	bus_dmamap_t *sd_map;
1944 	bus_addr_t bus_addr, *sd_ba;
1945 	int err, frag_idx, i, idx, n, pidx;
1946 	qidx_t credits;
1947 
1948 	sd_m = fl->ifl_sds.ifsd_m;
1949 	sd_map = fl->ifl_sds.ifsd_map;
1950 	sd_cl = fl->ifl_sds.ifsd_cl;
1951 	sd_ba = fl->ifl_sds.ifsd_ba;
1952 	pidx = fl->ifl_pidx;
1953 	idx = pidx;
1954 	frag_idx = fl->ifl_fragidx;
1955 	credits = fl->ifl_credits;
1956 
1957 	i = 0;
1958 	n = count;
1959 	MPASS(n > 0);
1960 	MPASS(credits + n <= fl->ifl_size);
1961 
1962 	if (pidx < fl->ifl_cidx)
1963 		MPASS(pidx + n <= fl->ifl_cidx);
1964 	if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1965 		MPASS(fl->ifl_gen == 0);
1966 	if (pidx > fl->ifl_cidx)
1967 		MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1968 
1969 	DBG_COUNTER_INC(fl_refills);
1970 	if (n > 8)
1971 		DBG_COUNTER_INC(fl_refills_large);
1972 	iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1973 	while (n--) {
1974 		/*
1975 		 * We allocate an uninitialized mbuf + cluster, mbuf is
1976 		 * initialized after rx.
1977 		 *
1978 		 * If the cluster is still set then we know a minimum sized packet was received
1979 		 */
1980 		bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
1981 		    &frag_idx);
1982 		if (frag_idx < 0)
1983 			bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1984 		MPASS(frag_idx >= 0);
1985 		if ((cl = sd_cl[frag_idx]) == NULL) {
1986 			if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1987 				break;
1988 
1989 			cb_arg.error = 0;
1990 			MPASS(sd_map != NULL);
1991 			err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
1992 			    cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
1993 			    BUS_DMA_NOWAIT);
1994 			if (err != 0 || cb_arg.error) {
1995 				/*
1996 				 * !zone_pack ?
1997 				 */
1998 				if (fl->ifl_zone == zone_pack)
1999 					uma_zfree(fl->ifl_zone, cl);
2000 				break;
2001 			}
2002 
2003 			sd_ba[frag_idx] =  bus_addr = cb_arg.seg.ds_addr;
2004 			sd_cl[frag_idx] = cl;
2005 #if MEMORY_LOGGING
2006 			fl->ifl_cl_enqueued++;
2007 #endif
2008 		} else {
2009 			bus_addr = sd_ba[frag_idx];
2010 		}
2011 		bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2012 		    BUS_DMASYNC_PREREAD);
2013 
2014 		if (sd_m[frag_idx] == NULL) {
2015 			if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
2016 				break;
2017 			}
2018 			sd_m[frag_idx] = m;
2019 		}
2020 		bit_set(fl->ifl_rx_bitmap, frag_idx);
2021 #if MEMORY_LOGGING
2022 		fl->ifl_m_enqueued++;
2023 #endif
2024 
2025 		DBG_COUNTER_INC(rx_allocs);
2026 		fl->ifl_rxd_idxs[i] = frag_idx;
2027 		fl->ifl_bus_addrs[i] = bus_addr;
2028 		fl->ifl_vm_addrs[i] = cl;
2029 		credits++;
2030 		i++;
2031 		MPASS(credits <= fl->ifl_size);
2032 		if (++idx == fl->ifl_size) {
2033 			fl->ifl_gen = 1;
2034 			idx = 0;
2035 		}
2036 		if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2037 			iru.iru_pidx = pidx;
2038 			iru.iru_count = i;
2039 			ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2040 			i = 0;
2041 			pidx = idx;
2042 			fl->ifl_pidx = idx;
2043 			fl->ifl_credits = credits;
2044 		}
2045 	}
2046 
2047 	if (i) {
2048 		iru.iru_pidx = pidx;
2049 		iru.iru_count = i;
2050 		ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2051 		fl->ifl_pidx = idx;
2052 		fl->ifl_credits = credits;
2053 	}
2054 	DBG_COUNTER_INC(rxd_flush);
2055 	if (fl->ifl_pidx == 0)
2056 		pidx = fl->ifl_size - 1;
2057 	else
2058 		pidx = fl->ifl_pidx - 1;
2059 
2060 	bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2061 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2062 	ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
2063 	fl->ifl_fragidx = frag_idx;
2064 }
2065 
2066 static __inline void
2067 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
2068 {
2069 	/* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2070 	int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2071 #ifdef INVARIANTS
2072 	int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2073 #endif
2074 
2075 	MPASS(fl->ifl_credits <= fl->ifl_size);
2076 	MPASS(reclaimable == delta);
2077 
2078 	if (reclaimable > 0)
2079 		_iflib_fl_refill(ctx, fl, min(max, reclaimable));
2080 }
2081 
2082 uint8_t
2083 iflib_in_detach(if_ctx_t ctx)
2084 {
2085 	bool in_detach;
2086 
2087 	STATE_LOCK(ctx);
2088 	in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2089 	STATE_UNLOCK(ctx);
2090 	return (in_detach);
2091 }
2092 
2093 static void
2094 iflib_fl_bufs_free(iflib_fl_t fl)
2095 {
2096 	iflib_dma_info_t idi = fl->ifl_ifdi;
2097 	bus_dmamap_t sd_map;
2098 	uint32_t i;
2099 
2100 	for (i = 0; i < fl->ifl_size; i++) {
2101 		struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2102 		caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2103 
2104 		if (*sd_cl != NULL) {
2105 			sd_map = fl->ifl_sds.ifsd_map[i];
2106 			bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2107 			    BUS_DMASYNC_POSTREAD);
2108 			bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2109 			if (*sd_cl != NULL)
2110 				uma_zfree(fl->ifl_zone, *sd_cl);
2111 			// XXX: Should this get moved out?
2112 			if (iflib_in_detach(fl->ifl_rxq->ifr_ctx))
2113 				bus_dmamap_destroy(fl->ifl_buf_tag, sd_map);
2114 			if (*sd_m != NULL) {
2115 				m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2116 				uma_zfree(zone_mbuf, *sd_m);
2117 			}
2118 		} else {
2119 			MPASS(*sd_cl == NULL);
2120 			MPASS(*sd_m == NULL);
2121 		}
2122 #if MEMORY_LOGGING
2123 		fl->ifl_m_dequeued++;
2124 		fl->ifl_cl_dequeued++;
2125 #endif
2126 		*sd_cl = NULL;
2127 		*sd_m = NULL;
2128 	}
2129 #ifdef INVARIANTS
2130 	for (i = 0; i < fl->ifl_size; i++) {
2131 		MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2132 		MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2133 	}
2134 #endif
2135 	/*
2136 	 * Reset free list values
2137 	 */
2138 	fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2139 	bzero(idi->idi_vaddr, idi->idi_size);
2140 }
2141 
2142 /*********************************************************************
2143  *
2144  *  Initialize a free list and its buffers.
2145  *
2146  **********************************************************************/
2147 static int
2148 iflib_fl_setup(iflib_fl_t fl)
2149 {
2150 	iflib_rxq_t rxq = fl->ifl_rxq;
2151 	if_ctx_t ctx = rxq->ifr_ctx;
2152 
2153 	bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2154 	/*
2155 	** Free current RX buffer structs and their mbufs
2156 	*/
2157 	iflib_fl_bufs_free(fl);
2158 	/* Now replenish the mbufs */
2159 	MPASS(fl->ifl_credits == 0);
2160 	fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2161 	if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2162 		ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2163 	fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2164 	fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2165 
2166 
2167 	/* avoid pre-allocating zillions of clusters to an idle card
2168 	 * potentially speeding up attach
2169 	 */
2170 	_iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2171 	MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2172 	if (min(128, fl->ifl_size) != fl->ifl_credits)
2173 		return (ENOBUFS);
2174 	/*
2175 	 * handle failure
2176 	 */
2177 	MPASS(rxq != NULL);
2178 	MPASS(fl->ifl_ifdi != NULL);
2179 	bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2180 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2181 	return (0);
2182 }
2183 
2184 /*********************************************************************
2185  *
2186  *  Free receive ring data structures
2187  *
2188  **********************************************************************/
2189 static void
2190 iflib_rx_sds_free(iflib_rxq_t rxq)
2191 {
2192 	iflib_fl_t fl;
2193 	int i, j;
2194 
2195 	if (rxq->ifr_fl != NULL) {
2196 		for (i = 0; i < rxq->ifr_nfl; i++) {
2197 			fl = &rxq->ifr_fl[i];
2198 			if (fl->ifl_buf_tag != NULL) {
2199 				if (fl->ifl_sds.ifsd_map != NULL) {
2200 					for (j = 0; j < fl->ifl_size; j++) {
2201 						if (fl->ifl_sds.ifsd_map[j] ==
2202 						    NULL)
2203 							continue;
2204 						bus_dmamap_sync(
2205 						    fl->ifl_buf_tag,
2206 						    fl->ifl_sds.ifsd_map[j],
2207 						    BUS_DMASYNC_POSTREAD);
2208 						bus_dmamap_unload(
2209 						    fl->ifl_buf_tag,
2210 						    fl->ifl_sds.ifsd_map[j]);
2211 					}
2212 				}
2213 				bus_dma_tag_destroy(fl->ifl_buf_tag);
2214 				fl->ifl_buf_tag = NULL;
2215 			}
2216 			free(fl->ifl_sds.ifsd_m, M_IFLIB);
2217 			free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2218 			free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2219 			free(fl->ifl_sds.ifsd_map, M_IFLIB);
2220 			fl->ifl_sds.ifsd_m = NULL;
2221 			fl->ifl_sds.ifsd_cl = NULL;
2222 			fl->ifl_sds.ifsd_ba = NULL;
2223 			fl->ifl_sds.ifsd_map = NULL;
2224 		}
2225 		free(rxq->ifr_fl, M_IFLIB);
2226 		rxq->ifr_fl = NULL;
2227 		rxq->ifr_cq_cidx = 0;
2228 	}
2229 }
2230 
2231 /*
2232  * Timer routine
2233  */
2234 static void
2235 iflib_timer(void *arg)
2236 {
2237 	iflib_txq_t txq = arg;
2238 	if_ctx_t ctx = txq->ift_ctx;
2239 	if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2240 	uint64_t this_tick = ticks;
2241 	uint32_t reset_on = hz / 2;
2242 
2243 	if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2244 		return;
2245 
2246 	/*
2247 	** Check on the state of the TX queue(s), this
2248 	** can be done without the lock because its RO
2249 	** and the HUNG state will be static if set.
2250 	*/
2251 	if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2252 		txq->ift_last_timer_tick = this_tick;
2253 		IFDI_TIMER(ctx, txq->ift_id);
2254 		if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2255 		    ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2256 		     (sctx->isc_pause_frames == 0)))
2257 			goto hung;
2258 
2259 		if (ifmp_ring_is_stalled(txq->ift_br))
2260 			txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2261 		txq->ift_cleaned_prev = txq->ift_cleaned;
2262 	}
2263 #ifdef DEV_NETMAP
2264 	if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2265 		iflib_netmap_timer_adjust(ctx, txq, &reset_on);
2266 #endif
2267 	/* handle any laggards */
2268 	if (txq->ift_db_pending)
2269 		GROUPTASK_ENQUEUE(&txq->ift_task);
2270 
2271 	sctx->isc_pause_frames = 0;
2272 	if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2273 		callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2274 	return;
2275 
2276  hung:
2277 	device_printf(ctx->ifc_dev,
2278 	    "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2279 	    txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2280 	STATE_LOCK(ctx);
2281 	if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2282 	ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2283 	iflib_admin_intr_deferred(ctx);
2284 	STATE_UNLOCK(ctx);
2285 }
2286 
2287 static void
2288 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2289 {
2290 	if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2291 
2292 	/*
2293 	 * XXX don't set the max_frame_size to larger
2294 	 * than the hardware can handle
2295 	 */
2296 	if (sctx->isc_max_frame_size <= MCLBYTES)
2297 		ctx->ifc_rx_mbuf_sz = MCLBYTES;
2298 	else
2299 		ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE;
2300 }
2301 
2302 uint32_t
2303 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2304 {
2305 
2306 	return (ctx->ifc_rx_mbuf_sz);
2307 }
2308 
2309 static void
2310 iflib_init_locked(if_ctx_t ctx)
2311 {
2312 	if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2313 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2314 	if_t ifp = ctx->ifc_ifp;
2315 	iflib_fl_t fl;
2316 	iflib_txq_t txq;
2317 	iflib_rxq_t rxq;
2318 	int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2319 
2320 	if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2321 	IFDI_INTR_DISABLE(ctx);
2322 
2323 	tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2324 	tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2325 	/* Set hardware offload abilities */
2326 	if_clearhwassist(ifp);
2327 	if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2328 		if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2329 	if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2330 		if_sethwassistbits(ifp,  tx_ip6_csum_flags, 0);
2331 	if (if_getcapenable(ifp) & IFCAP_TSO4)
2332 		if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2333 	if (if_getcapenable(ifp) & IFCAP_TSO6)
2334 		if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2335 
2336 	for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2337 		CALLOUT_LOCK(txq);
2338 		callout_stop(&txq->ift_timer);
2339 		CALLOUT_UNLOCK(txq);
2340 		iflib_netmap_txq_init(ctx, txq);
2341 	}
2342 
2343 	/*
2344 	 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2345 	 * that drivers can use the value when setting up the hardware receive
2346 	 * buffers.
2347 	 */
2348 	iflib_calc_rx_mbuf_sz(ctx);
2349 
2350 #ifdef INVARIANTS
2351 	i = if_getdrvflags(ifp);
2352 #endif
2353 	IFDI_INIT(ctx);
2354 	MPASS(if_getdrvflags(ifp) == i);
2355 	for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2356 		/* XXX this should really be done on a per-queue basis */
2357 		if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2358 			MPASS(rxq->ifr_id == i);
2359 			iflib_netmap_rxq_init(ctx, rxq);
2360 			continue;
2361 		}
2362 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2363 			if (iflib_fl_setup(fl)) {
2364 				device_printf(ctx->ifc_dev,
2365 				    "setting up free list %d failed - "
2366 				    "check cluster settings\n", j);
2367 				goto done;
2368 			}
2369 		}
2370 	}
2371 done:
2372 	if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2373 	IFDI_INTR_ENABLE(ctx);
2374 	txq = ctx->ifc_txqs;
2375 	for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2376 		callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2377 			txq->ift_timer.c_cpu);
2378 }
2379 
2380 static int
2381 iflib_media_change(if_t ifp)
2382 {
2383 	if_ctx_t ctx = if_getsoftc(ifp);
2384 	int err;
2385 
2386 	CTX_LOCK(ctx);
2387 	if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2388 		iflib_init_locked(ctx);
2389 	CTX_UNLOCK(ctx);
2390 	return (err);
2391 }
2392 
2393 static void
2394 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2395 {
2396 	if_ctx_t ctx = if_getsoftc(ifp);
2397 
2398 	CTX_LOCK(ctx);
2399 	IFDI_UPDATE_ADMIN_STATUS(ctx);
2400 	IFDI_MEDIA_STATUS(ctx, ifmr);
2401 	CTX_UNLOCK(ctx);
2402 }
2403 
2404 void
2405 iflib_stop(if_ctx_t ctx)
2406 {
2407 	iflib_txq_t txq = ctx->ifc_txqs;
2408 	iflib_rxq_t rxq = ctx->ifc_rxqs;
2409 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2410 	if_shared_ctx_t sctx = ctx->ifc_sctx;
2411 	iflib_dma_info_t di;
2412 	iflib_fl_t fl;
2413 	int i, j;
2414 
2415 	/* Tell the stack that the interface is no longer active */
2416 	if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2417 
2418 	IFDI_INTR_DISABLE(ctx);
2419 	DELAY(1000);
2420 	IFDI_STOP(ctx);
2421 	DELAY(1000);
2422 
2423 	iflib_debug_reset();
2424 	/* Wait for current tx queue users to exit to disarm watchdog timer. */
2425 	for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2426 		/* make sure all transmitters have completed before proceeding XXX */
2427 
2428 		CALLOUT_LOCK(txq);
2429 		callout_stop(&txq->ift_timer);
2430 		CALLOUT_UNLOCK(txq);
2431 
2432 		/* clean any enqueued buffers */
2433 		iflib_ifmp_purge(txq);
2434 		/* Free any existing tx buffers. */
2435 		for (j = 0; j < txq->ift_size; j++) {
2436 			iflib_txsd_free(ctx, txq, j);
2437 		}
2438 		txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2439 		txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2440 		txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2441 		txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2442 		txq->ift_pullups = 0;
2443 		ifmp_ring_reset_stats(txq->ift_br);
2444 		for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2445 			bzero((void *)di->idi_vaddr, di->idi_size);
2446 	}
2447 	for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2448 		/* make sure all transmitters have completed before proceeding XXX */
2449 
2450 		rxq->ifr_cq_cidx = 0;
2451 		for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2452 			bzero((void *)di->idi_vaddr, di->idi_size);
2453 		/* also resets the free lists pidx/cidx */
2454 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2455 			iflib_fl_bufs_free(fl);
2456 	}
2457 }
2458 
2459 static inline caddr_t
2460 calc_next_rxd(iflib_fl_t fl, int cidx)
2461 {
2462 	qidx_t size;
2463 	int nrxd;
2464 	caddr_t start, end, cur, next;
2465 
2466 	nrxd = fl->ifl_size;
2467 	size = fl->ifl_rxd_size;
2468 	start = fl->ifl_ifdi->idi_vaddr;
2469 
2470 	if (__predict_false(size == 0))
2471 		return (start);
2472 	cur = start + size*cidx;
2473 	end = start + size*nrxd;
2474 	next = CACHE_PTR_NEXT(cur);
2475 	return (next < end ? next : start);
2476 }
2477 
2478 static inline void
2479 prefetch_pkts(iflib_fl_t fl, int cidx)
2480 {
2481 	int nextptr;
2482 	int nrxd = fl->ifl_size;
2483 	caddr_t next_rxd;
2484 
2485 
2486 	nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2487 	prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2488 	prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2489 	next_rxd = calc_next_rxd(fl, cidx);
2490 	prefetch(next_rxd);
2491 	prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2492 	prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2493 	prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2494 	prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2495 	prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2496 	prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2497 	prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2498 	prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2499 }
2500 
2501 static struct mbuf *
2502 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2503     int *pf_rv, if_rxd_info_t ri)
2504 {
2505 	bus_dmamap_t map;
2506 	iflib_fl_t fl;
2507 	caddr_t payload;
2508 	struct mbuf *m;
2509 	int flid, cidx, len, next;
2510 
2511 	map = NULL;
2512 	flid = irf->irf_flid;
2513 	cidx = irf->irf_idx;
2514 	fl = &rxq->ifr_fl[flid];
2515 	sd->ifsd_fl = fl;
2516 	sd->ifsd_cidx = cidx;
2517 	m = fl->ifl_sds.ifsd_m[cidx];
2518 	sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2519 	fl->ifl_credits--;
2520 #if MEMORY_LOGGING
2521 	fl->ifl_m_dequeued++;
2522 #endif
2523 	if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2524 		prefetch_pkts(fl, cidx);
2525 	next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2526 	prefetch(&fl->ifl_sds.ifsd_map[next]);
2527 	map = fl->ifl_sds.ifsd_map[cidx];
2528 	next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2529 
2530 	/* not valid assert if bxe really does SGE from non-contiguous elements */
2531 	MPASS(fl->ifl_cidx == cidx);
2532 	bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2533 
2534 	if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL) {
2535 		payload  = *sd->ifsd_cl;
2536 		payload +=  ri->iri_pad;
2537 		len = ri->iri_len - ri->iri_pad;
2538 		*pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp,
2539 		    len | PFIL_MEMPTR | PFIL_IN, NULL);
2540 		switch (*pf_rv) {
2541 		case PFIL_DROPPED:
2542 		case PFIL_CONSUMED:
2543 			/*
2544 			 * The filter ate it.  Everything is recycled.
2545 			 */
2546 			m = NULL;
2547 			unload = 0;
2548 			break;
2549 		case PFIL_REALLOCED:
2550 			/*
2551 			 * The filter copied it.  Everything is recycled.
2552 			 */
2553 			m = pfil_mem2mbuf(payload);
2554 			unload = 0;
2555 			break;
2556 		case PFIL_PASS:
2557 			/*
2558 			 * Filter said it was OK, so receive like
2559 			 * normal
2560 			 */
2561 			fl->ifl_sds.ifsd_m[cidx] = NULL;
2562 			break;
2563 		default:
2564 			MPASS(0);
2565 		}
2566 	} else {
2567 		fl->ifl_sds.ifsd_m[cidx] = NULL;
2568 		*pf_rv = PFIL_PASS;
2569 	}
2570 
2571 	if (unload)
2572 		bus_dmamap_unload(fl->ifl_buf_tag, map);
2573 	fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2574 	if (__predict_false(fl->ifl_cidx == 0))
2575 		fl->ifl_gen = 0;
2576 	bit_clear(fl->ifl_rx_bitmap, cidx);
2577 	return (m);
2578 }
2579 
2580 static struct mbuf *
2581 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2582 {
2583 	struct mbuf *m, *mh, *mt;
2584 	caddr_t cl;
2585 	int  *pf_rv_ptr, flags, i, padlen;
2586 	bool consumed;
2587 
2588 	i = 0;
2589 	mh = NULL;
2590 	consumed = false;
2591 	*pf_rv = PFIL_PASS;
2592 	pf_rv_ptr = pf_rv;
2593 	do {
2594 		m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2595 		    pf_rv_ptr, ri);
2596 
2597 		MPASS(*sd->ifsd_cl != NULL);
2598 
2599 		/*
2600 		 * Exclude zero-length frags & frags from
2601 		 * packets the filter has consumed or dropped
2602 		 */
2603 		if (ri->iri_frags[i].irf_len == 0 || consumed ||
2604 		    *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2605 			if (mh == NULL) {
2606 				/* everything saved here */
2607 				consumed = true;
2608 				pf_rv_ptr = NULL;
2609 				continue;
2610 			}
2611 			/* XXX we can save the cluster here, but not the mbuf */
2612 			m_init(m, M_NOWAIT, MT_DATA, 0);
2613 			m_free(m);
2614 			continue;
2615 		}
2616 		if (mh == NULL) {
2617 			flags = M_PKTHDR|M_EXT;
2618 			mh = mt = m;
2619 			padlen = ri->iri_pad;
2620 		} else {
2621 			flags = M_EXT;
2622 			mt->m_next = m;
2623 			mt = m;
2624 			/* assuming padding is only on the first fragment */
2625 			padlen = 0;
2626 		}
2627 		cl = *sd->ifsd_cl;
2628 		*sd->ifsd_cl = NULL;
2629 
2630 		/* Can these two be made one ? */
2631 		m_init(m, M_NOWAIT, MT_DATA, flags);
2632 		m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2633 		/*
2634 		 * These must follow m_init and m_cljset
2635 		 */
2636 		m->m_data += padlen;
2637 		ri->iri_len -= padlen;
2638 		m->m_len = ri->iri_frags[i].irf_len;
2639 	} while (++i < ri->iri_nfrags);
2640 
2641 	return (mh);
2642 }
2643 
2644 /*
2645  * Process one software descriptor
2646  */
2647 static struct mbuf *
2648 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2649 {
2650 	struct if_rxsd sd;
2651 	struct mbuf *m;
2652 	int pf_rv;
2653 
2654 	/* should I merge this back in now that the two paths are basically duplicated? */
2655 	if (ri->iri_nfrags == 1 &&
2656 	    ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2657 		m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2658 		    &pf_rv, ri);
2659 		if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2660 			return (m);
2661 		if (pf_rv == PFIL_PASS) {
2662 			m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2663 #ifndef __NO_STRICT_ALIGNMENT
2664 			if (!IP_ALIGNED(m))
2665 				m->m_data += 2;
2666 #endif
2667 			memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2668 			m->m_len = ri->iri_frags[0].irf_len;
2669 		}
2670 	} else {
2671 		m = assemble_segments(rxq, ri, &sd, &pf_rv);
2672 		if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2673 			return (m);
2674 	}
2675 	m->m_pkthdr.len = ri->iri_len;
2676 	m->m_pkthdr.rcvif = ri->iri_ifp;
2677 	m->m_flags |= ri->iri_flags;
2678 	m->m_pkthdr.ether_vtag = ri->iri_vtag;
2679 	m->m_pkthdr.flowid = ri->iri_flowid;
2680 	M_HASHTYPE_SET(m, ri->iri_rsstype);
2681 	m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2682 	m->m_pkthdr.csum_data = ri->iri_csum_data;
2683 	return (m);
2684 }
2685 
2686 #if defined(INET6) || defined(INET)
2687 static void
2688 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2689 {
2690 	CURVNET_SET(lc->ifp->if_vnet);
2691 #if defined(INET6)
2692 	*v6 = V_ip6_forwarding;
2693 #endif
2694 #if defined(INET)
2695 	*v4 = V_ipforwarding;
2696 #endif
2697 	CURVNET_RESTORE();
2698 }
2699 
2700 /*
2701  * Returns true if it's possible this packet could be LROed.
2702  * if it returns false, it is guaranteed that tcp_lro_rx()
2703  * would not return zero.
2704  */
2705 static bool
2706 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2707 {
2708 	struct ether_header *eh;
2709 
2710 	eh = mtod(m, struct ether_header *);
2711 	switch (eh->ether_type) {
2712 #if defined(INET6)
2713 		case htons(ETHERTYPE_IPV6):
2714 			return (!v6_forwarding);
2715 #endif
2716 #if defined (INET)
2717 		case htons(ETHERTYPE_IP):
2718 			return (!v4_forwarding);
2719 #endif
2720 	}
2721 
2722 	return false;
2723 }
2724 #else
2725 static void
2726 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2727 {
2728 }
2729 #endif
2730 
2731 static bool
2732 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2733 {
2734 	if_t ifp;
2735 	if_ctx_t ctx = rxq->ifr_ctx;
2736 	if_shared_ctx_t sctx = ctx->ifc_sctx;
2737 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2738 	int avail, i;
2739 	qidx_t *cidxp;
2740 	struct if_rxd_info ri;
2741 	int err, budget_left, rx_bytes, rx_pkts;
2742 	iflib_fl_t fl;
2743 	int lro_enabled;
2744 	bool v4_forwarding, v6_forwarding, lro_possible;
2745 
2746 	/*
2747 	 * XXX early demux data packets so that if_input processing only handles
2748 	 * acks in interrupt context
2749 	 */
2750 	struct mbuf *m, *mh, *mt, *mf;
2751 
2752 	lro_possible = v4_forwarding = v6_forwarding = false;
2753 	ifp = ctx->ifc_ifp;
2754 	mh = mt = NULL;
2755 	MPASS(budget > 0);
2756 	rx_pkts	= rx_bytes = 0;
2757 	if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2758 		cidxp = &rxq->ifr_cq_cidx;
2759 	else
2760 		cidxp = &rxq->ifr_fl[0].ifl_cidx;
2761 	if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2762 		for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2763 			__iflib_fl_refill_lt(ctx, fl, budget + 8);
2764 		DBG_COUNTER_INC(rx_unavail);
2765 		return (false);
2766 	}
2767 
2768 	/* pfil needs the vnet to be set */
2769 	CURVNET_SET_QUIET(ifp->if_vnet);
2770 	for (budget_left = budget; budget_left > 0 && avail > 0;) {
2771 		if (__predict_false(!CTX_ACTIVE(ctx))) {
2772 			DBG_COUNTER_INC(rx_ctx_inactive);
2773 			break;
2774 		}
2775 		/*
2776 		 * Reset client set fields to their default values
2777 		 */
2778 		rxd_info_zero(&ri);
2779 		ri.iri_qsidx = rxq->ifr_id;
2780 		ri.iri_cidx = *cidxp;
2781 		ri.iri_ifp = ifp;
2782 		ri.iri_frags = rxq->ifr_frags;
2783 		err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2784 
2785 		if (err)
2786 			goto err;
2787 		rx_pkts += 1;
2788 		rx_bytes += ri.iri_len;
2789 		if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2790 			*cidxp = ri.iri_cidx;
2791 			/* Update our consumer index */
2792 			/* XXX NB: shurd - check if this is still safe */
2793 			while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
2794 				rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2795 			/* was this only a completion queue message? */
2796 			if (__predict_false(ri.iri_nfrags == 0))
2797 				continue;
2798 		}
2799 		MPASS(ri.iri_nfrags != 0);
2800 		MPASS(ri.iri_len != 0);
2801 
2802 		/* will advance the cidx on the corresponding free lists */
2803 		m = iflib_rxd_pkt_get(rxq, &ri);
2804 		avail--;
2805 		budget_left--;
2806 		if (avail == 0 && budget_left)
2807 			avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2808 
2809 		if (__predict_false(m == NULL))
2810 			continue;
2811 
2812 		/* imm_pkt: -- cxgb */
2813 		if (mh == NULL)
2814 			mh = mt = m;
2815 		else {
2816 			mt->m_nextpkt = m;
2817 			mt = m;
2818 		}
2819 	}
2820 	CURVNET_RESTORE();
2821 	/* make sure that we can refill faster than drain */
2822 	for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2823 		__iflib_fl_refill_lt(ctx, fl, budget + 8);
2824 
2825 	lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2826 	if (lro_enabled)
2827 		iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2828 	mt = mf = NULL;
2829 	while (mh != NULL) {
2830 		m = mh;
2831 		mh = mh->m_nextpkt;
2832 		m->m_nextpkt = NULL;
2833 #ifndef __NO_STRICT_ALIGNMENT
2834 		if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2835 			continue;
2836 #endif
2837 		rx_bytes += m->m_pkthdr.len;
2838 		rx_pkts++;
2839 #if defined(INET6) || defined(INET)
2840 		if (lro_enabled) {
2841 			if (!lro_possible) {
2842 				lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2843 				if (lro_possible && mf != NULL) {
2844 					ifp->if_input(ifp, mf);
2845 					DBG_COUNTER_INC(rx_if_input);
2846 					mt = mf = NULL;
2847 				}
2848 			}
2849 			if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2850 			    (CSUM_L4_CALC|CSUM_L4_VALID)) {
2851 				if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2852 					continue;
2853 			}
2854 		}
2855 #endif
2856 		if (lro_possible) {
2857 			ifp->if_input(ifp, m);
2858 			DBG_COUNTER_INC(rx_if_input);
2859 			continue;
2860 		}
2861 
2862 		if (mf == NULL)
2863 			mf = m;
2864 		if (mt != NULL)
2865 			mt->m_nextpkt = m;
2866 		mt = m;
2867 	}
2868 	if (mf != NULL) {
2869 		ifp->if_input(ifp, mf);
2870 		DBG_COUNTER_INC(rx_if_input);
2871 	}
2872 
2873 	if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2874 	if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2875 
2876 	/*
2877 	 * Flush any outstanding LRO work
2878 	 */
2879 #if defined(INET6) || defined(INET)
2880 	tcp_lro_flush_all(&rxq->ifr_lc);
2881 #endif
2882 	if (avail)
2883 		return true;
2884 	return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2885 err:
2886 	STATE_LOCK(ctx);
2887 	ctx->ifc_flags |= IFC_DO_RESET;
2888 	iflib_admin_intr_deferred(ctx);
2889 	STATE_UNLOCK(ctx);
2890 	return (false);
2891 }
2892 
2893 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2894 static inline qidx_t
2895 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2896 {
2897 	qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2898 	qidx_t minthresh = txq->ift_size / 8;
2899 	if (in_use > 4*minthresh)
2900 		return (notify_count);
2901 	if (in_use > 2*minthresh)
2902 		return (notify_count >> 1);
2903 	if (in_use > minthresh)
2904 		return (notify_count >> 3);
2905 	return (0);
2906 }
2907 
2908 static inline qidx_t
2909 txq_max_rs_deferred(iflib_txq_t txq)
2910 {
2911 	qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2912 	qidx_t minthresh = txq->ift_size / 8;
2913 	if (txq->ift_in_use > 4*minthresh)
2914 		return (notify_count);
2915 	if (txq->ift_in_use > 2*minthresh)
2916 		return (notify_count >> 1);
2917 	if (txq->ift_in_use > minthresh)
2918 		return (notify_count >> 2);
2919 	return (2);
2920 }
2921 
2922 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2923 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2924 
2925 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2926 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2927 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2928 
2929 /* forward compatibility for cxgb */
2930 #define FIRST_QSET(ctx) 0
2931 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2932 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2933 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2934 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2935 
2936 /* XXX we should be setting this to something other than zero */
2937 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2938 #define	MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2939     (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2940 
2941 static inline bool
2942 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2943 {
2944 	qidx_t dbval, max;
2945 	bool rang;
2946 
2947 	rang = false;
2948 	max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2949 	if (ring || txq->ift_db_pending >= max) {
2950 		dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2951 		bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
2952 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2953 		ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2954 		txq->ift_db_pending = txq->ift_npending = 0;
2955 		rang = true;
2956 	}
2957 	return (rang);
2958 }
2959 
2960 #ifdef PKT_DEBUG
2961 static void
2962 print_pkt(if_pkt_info_t pi)
2963 {
2964 	printf("pi len:  %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2965 	       pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2966 	printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2967 	       pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2968 	printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2969 	       pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2970 }
2971 #endif
2972 
2973 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2974 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
2975 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2976 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
2977 
2978 static int
2979 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2980 {
2981 	if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2982 	struct ether_vlan_header *eh;
2983 	struct mbuf *m;
2984 
2985 	m = *mp;
2986 	if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2987 	    M_WRITABLE(m) == 0) {
2988 		if ((m = m_dup(m, M_NOWAIT)) == NULL) {
2989 			return (ENOMEM);
2990 		} else {
2991 			m_freem(*mp);
2992 			DBG_COUNTER_INC(tx_frees);
2993 			*mp = m;
2994 		}
2995 	}
2996 
2997 	/*
2998 	 * Determine where frame payload starts.
2999 	 * Jump over vlan headers if already present,
3000 	 * helpful for QinQ too.
3001 	 */
3002 	if (__predict_false(m->m_len < sizeof(*eh))) {
3003 		txq->ift_pullups++;
3004 		if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3005 			return (ENOMEM);
3006 	}
3007 	eh = mtod(m, struct ether_vlan_header *);
3008 	if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3009 		pi->ipi_etype = ntohs(eh->evl_proto);
3010 		pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3011 	} else {
3012 		pi->ipi_etype = ntohs(eh->evl_encap_proto);
3013 		pi->ipi_ehdrlen = ETHER_HDR_LEN;
3014 	}
3015 
3016 	switch (pi->ipi_etype) {
3017 #ifdef INET
3018 	case ETHERTYPE_IP:
3019 	{
3020 		struct mbuf *n;
3021 		struct ip *ip = NULL;
3022 		struct tcphdr *th = NULL;
3023 		int minthlen;
3024 
3025 		minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3026 		if (__predict_false(m->m_len < minthlen)) {
3027 			/*
3028 			 * if this code bloat is causing too much of a hit
3029 			 * move it to a separate function and mark it noinline
3030 			 */
3031 			if (m->m_len == pi->ipi_ehdrlen) {
3032 				n = m->m_next;
3033 				MPASS(n);
3034 				if (n->m_len >= sizeof(*ip))  {
3035 					ip = (struct ip *)n->m_data;
3036 					if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3037 						th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3038 				} else {
3039 					txq->ift_pullups++;
3040 					if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3041 						return (ENOMEM);
3042 					ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3043 				}
3044 			} else {
3045 				txq->ift_pullups++;
3046 				if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3047 					return (ENOMEM);
3048 				ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3049 				if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3050 					th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3051 			}
3052 		} else {
3053 			ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3054 			if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3055 				th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3056 		}
3057 		pi->ipi_ip_hlen = ip->ip_hl << 2;
3058 		pi->ipi_ipproto = ip->ip_p;
3059 		pi->ipi_flags |= IPI_TX_IPV4;
3060 
3061 		/* TCP checksum offload may require TCP header length */
3062 		if (IS_TX_OFFLOAD4(pi)) {
3063 			if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3064 				if (__predict_false(th == NULL)) {
3065 					txq->ift_pullups++;
3066 					if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3067 						return (ENOMEM);
3068 					th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3069 				}
3070 				pi->ipi_tcp_hflags = th->th_flags;
3071 				pi->ipi_tcp_hlen = th->th_off << 2;
3072 				pi->ipi_tcp_seq = th->th_seq;
3073 			}
3074 			if (IS_TSO4(pi)) {
3075 				if (__predict_false(ip->ip_p != IPPROTO_TCP))
3076 					return (ENXIO);
3077 				/*
3078 				 * TSO always requires hardware checksum offload.
3079 				 */
3080 				pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3081 				th->th_sum = in_pseudo(ip->ip_src.s_addr,
3082 						       ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3083 				pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3084 				if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3085 					ip->ip_sum = 0;
3086 					ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3087 				}
3088 			}
3089 		}
3090 		if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3091                        ip->ip_sum = 0;
3092 
3093 		break;
3094 	}
3095 #endif
3096 #ifdef INET6
3097 	case ETHERTYPE_IPV6:
3098 	{
3099 		struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3100 		struct tcphdr *th;
3101 		pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3102 
3103 		if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3104 			txq->ift_pullups++;
3105 			if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3106 				return (ENOMEM);
3107 		}
3108 		th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3109 
3110 		/* XXX-BZ this will go badly in case of ext hdrs. */
3111 		pi->ipi_ipproto = ip6->ip6_nxt;
3112 		pi->ipi_flags |= IPI_TX_IPV6;
3113 
3114 		/* TCP checksum offload may require TCP header length */
3115 		if (IS_TX_OFFLOAD6(pi)) {
3116 			if (pi->ipi_ipproto == IPPROTO_TCP) {
3117 				if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3118 					txq->ift_pullups++;
3119 					if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3120 						return (ENOMEM);
3121 				}
3122 				pi->ipi_tcp_hflags = th->th_flags;
3123 				pi->ipi_tcp_hlen = th->th_off << 2;
3124 				pi->ipi_tcp_seq = th->th_seq;
3125 			}
3126 			if (IS_TSO6(pi)) {
3127 				if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3128 					return (ENXIO);
3129 				/*
3130 				 * TSO always requires hardware checksum offload.
3131 				 */
3132 				pi->ipi_csum_flags |= CSUM_IP6_TCP;
3133 				th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3134 				pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3135 			}
3136 		}
3137 		break;
3138 	}
3139 #endif
3140 	default:
3141 		pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3142 		pi->ipi_ip_hlen = 0;
3143 		break;
3144 	}
3145 	*mp = m;
3146 
3147 	return (0);
3148 }
3149 
3150 /*
3151  * If dodgy hardware rejects the scatter gather chain we've handed it
3152  * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3153  * m_defrag'd mbufs
3154  */
3155 static __noinline struct mbuf *
3156 iflib_remove_mbuf(iflib_txq_t txq)
3157 {
3158 	int ntxd, pidx;
3159 	struct mbuf *m, **ifsd_m;
3160 
3161 	ifsd_m = txq->ift_sds.ifsd_m;
3162 	ntxd = txq->ift_size;
3163 	pidx = txq->ift_pidx & (ntxd - 1);
3164 	ifsd_m = txq->ift_sds.ifsd_m;
3165 	m = ifsd_m[pidx];
3166 	ifsd_m[pidx] = NULL;
3167 	bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3168 	if (txq->ift_sds.ifsd_tso_map != NULL)
3169 		bus_dmamap_unload(txq->ift_tso_buf_tag,
3170 		    txq->ift_sds.ifsd_tso_map[pidx]);
3171 #if MEMORY_LOGGING
3172 	txq->ift_dequeued++;
3173 #endif
3174 	return (m);
3175 }
3176 
3177 static inline caddr_t
3178 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3179 {
3180 	qidx_t size;
3181 	int ntxd;
3182 	caddr_t start, end, cur, next;
3183 
3184 	ntxd = txq->ift_size;
3185 	size = txq->ift_txd_size[qid];
3186 	start = txq->ift_ifdi[qid].idi_vaddr;
3187 
3188 	if (__predict_false(size == 0))
3189 		return (start);
3190 	cur = start + size*cidx;
3191 	end = start + size*ntxd;
3192 	next = CACHE_PTR_NEXT(cur);
3193 	return (next < end ? next : start);
3194 }
3195 
3196 /*
3197  * Pad an mbuf to ensure a minimum ethernet frame size.
3198  * min_frame_size is the frame size (less CRC) to pad the mbuf to
3199  */
3200 static __noinline int
3201 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3202 {
3203 	/*
3204 	 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3205 	 * and ARP message is the smallest common payload I can think of
3206 	 */
3207 	static char pad[18];	/* just zeros */
3208 	int n;
3209 	struct mbuf *new_head;
3210 
3211 	if (!M_WRITABLE(*m_head)) {
3212 		new_head = m_dup(*m_head, M_NOWAIT);
3213 		if (new_head == NULL) {
3214 			m_freem(*m_head);
3215 			device_printf(dev, "cannot pad short frame, m_dup() failed");
3216 			DBG_COUNTER_INC(encap_pad_mbuf_fail);
3217 			DBG_COUNTER_INC(tx_frees);
3218 			return ENOMEM;
3219 		}
3220 		m_freem(*m_head);
3221 		*m_head = new_head;
3222 	}
3223 
3224 	for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3225 	     n > 0; n -= sizeof(pad))
3226 		if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3227 			break;
3228 
3229 	if (n > 0) {
3230 		m_freem(*m_head);
3231 		device_printf(dev, "cannot pad short frame\n");
3232 		DBG_COUNTER_INC(encap_pad_mbuf_fail);
3233 		DBG_COUNTER_INC(tx_frees);
3234 		return (ENOBUFS);
3235 	}
3236 
3237 	return 0;
3238 }
3239 
3240 static int
3241 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3242 {
3243 	if_ctx_t		ctx;
3244 	if_shared_ctx_t		sctx;
3245 	if_softc_ctx_t		scctx;
3246 	bus_dma_tag_t		buf_tag;
3247 	bus_dma_segment_t	*segs;
3248 	struct mbuf		*m_head, **ifsd_m;
3249 	void			*next_txd;
3250 	bus_dmamap_t		map;
3251 	struct if_pkt_info	pi;
3252 	int remap = 0;
3253 	int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3254 
3255 	ctx = txq->ift_ctx;
3256 	sctx = ctx->ifc_sctx;
3257 	scctx = &ctx->ifc_softc_ctx;
3258 	segs = txq->ift_segs;
3259 	ntxd = txq->ift_size;
3260 	m_head = *m_headp;
3261 	map = NULL;
3262 
3263 	/*
3264 	 * If we're doing TSO the next descriptor to clean may be quite far ahead
3265 	 */
3266 	cidx = txq->ift_cidx;
3267 	pidx = txq->ift_pidx;
3268 	if (ctx->ifc_flags & IFC_PREFETCH) {
3269 		next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3270 		if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3271 			next_txd = calc_next_txd(txq, cidx, 0);
3272 			prefetch(next_txd);
3273 		}
3274 
3275 		/* prefetch the next cache line of mbuf pointers and flags */
3276 		prefetch(&txq->ift_sds.ifsd_m[next]);
3277 		prefetch(&txq->ift_sds.ifsd_map[next]);
3278 		next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3279 	}
3280 	map = txq->ift_sds.ifsd_map[pidx];
3281 	ifsd_m = txq->ift_sds.ifsd_m;
3282 
3283 	if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3284 		buf_tag = txq->ift_tso_buf_tag;
3285 		max_segs = scctx->isc_tx_tso_segments_max;
3286 		map = txq->ift_sds.ifsd_tso_map[pidx];
3287 		MPASS(buf_tag != NULL);
3288 		MPASS(max_segs > 0);
3289 	} else {
3290 		buf_tag = txq->ift_buf_tag;
3291 		max_segs = scctx->isc_tx_nsegments;
3292 		map = txq->ift_sds.ifsd_map[pidx];
3293 	}
3294 	if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3295 	    __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3296 		err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3297 		if (err) {
3298 			DBG_COUNTER_INC(encap_txd_encap_fail);
3299 			return err;
3300 		}
3301 	}
3302 	m_head = *m_headp;
3303 
3304 	pkt_info_zero(&pi);
3305 	pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3306 	pi.ipi_pidx = pidx;
3307 	pi.ipi_qsidx = txq->ift_id;
3308 	pi.ipi_len = m_head->m_pkthdr.len;
3309 	pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3310 	pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3311 
3312 	/* deliberate bitwise OR to make one condition */
3313 	if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3314 		if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3315 			DBG_COUNTER_INC(encap_txd_encap_fail);
3316 			return (err);
3317 		}
3318 		m_head = *m_headp;
3319 	}
3320 
3321 retry:
3322 	err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3323 	    BUS_DMA_NOWAIT);
3324 defrag:
3325 	if (__predict_false(err)) {
3326 		switch (err) {
3327 		case EFBIG:
3328 			/* try collapse once and defrag once */
3329 			if (remap == 0) {
3330 				m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3331 				/* try defrag if collapsing fails */
3332 				if (m_head == NULL)
3333 					remap++;
3334 			}
3335 			if (remap == 1) {
3336 				txq->ift_mbuf_defrag++;
3337 				m_head = m_defrag(*m_headp, M_NOWAIT);
3338 			}
3339 			/*
3340 			 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3341 			 * failed to map an mbuf that was run through m_defrag
3342 			 */
3343 			MPASS(remap <= 1);
3344 			if (__predict_false(m_head == NULL || remap > 1))
3345 				goto defrag_failed;
3346 			remap++;
3347 			*m_headp = m_head;
3348 			goto retry;
3349 			break;
3350 		case ENOMEM:
3351 			txq->ift_no_tx_dma_setup++;
3352 			break;
3353 		default:
3354 			txq->ift_no_tx_dma_setup++;
3355 			m_freem(*m_headp);
3356 			DBG_COUNTER_INC(tx_frees);
3357 			*m_headp = NULL;
3358 			break;
3359 		}
3360 		txq->ift_map_failed++;
3361 		DBG_COUNTER_INC(encap_load_mbuf_fail);
3362 		DBG_COUNTER_INC(encap_txd_encap_fail);
3363 		return (err);
3364 	}
3365 	ifsd_m[pidx] = m_head;
3366 	/*
3367 	 * XXX assumes a 1 to 1 relationship between segments and
3368 	 *        descriptors - this does not hold true on all drivers, e.g.
3369 	 *        cxgb
3370 	 */
3371 	if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3372 		txq->ift_no_desc_avail++;
3373 		bus_dmamap_unload(buf_tag, map);
3374 		DBG_COUNTER_INC(encap_txq_avail_fail);
3375 		DBG_COUNTER_INC(encap_txd_encap_fail);
3376 		if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3377 			GROUPTASK_ENQUEUE(&txq->ift_task);
3378 		return (ENOBUFS);
3379 	}
3380 	/*
3381 	 * On Intel cards we can greatly reduce the number of TX interrupts
3382 	 * we see by only setting report status on every Nth descriptor.
3383 	 * However, this also means that the driver will need to keep track
3384 	 * of the descriptors that RS was set on to check them for the DD bit.
3385 	 */
3386 	txq->ift_rs_pending += nsegs + 1;
3387 	if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3388 	     iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3389 		pi.ipi_flags |= IPI_TX_INTR;
3390 		txq->ift_rs_pending = 0;
3391 	}
3392 
3393 	pi.ipi_segs = segs;
3394 	pi.ipi_nsegs = nsegs;
3395 
3396 	MPASS(pidx >= 0 && pidx < txq->ift_size);
3397 #ifdef PKT_DEBUG
3398 	print_pkt(&pi);
3399 #endif
3400 	if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3401 		bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3402 		DBG_COUNTER_INC(tx_encap);
3403 		MPASS(pi.ipi_new_pidx < txq->ift_size);
3404 
3405 		ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3406 		if (pi.ipi_new_pidx < pi.ipi_pidx) {
3407 			ndesc += txq->ift_size;
3408 			txq->ift_gen = 1;
3409 		}
3410 		/*
3411 		 * drivers can need as many as
3412 		 * two sentinels
3413 		 */
3414 		MPASS(ndesc <= pi.ipi_nsegs + 2);
3415 		MPASS(pi.ipi_new_pidx != pidx);
3416 		MPASS(ndesc > 0);
3417 		txq->ift_in_use += ndesc;
3418 
3419 		/*
3420 		 * We update the last software descriptor again here because there may
3421 		 * be a sentinel and/or there may be more mbufs than segments
3422 		 */
3423 		txq->ift_pidx = pi.ipi_new_pidx;
3424 		txq->ift_npending += pi.ipi_ndescs;
3425 	} else {
3426 		*m_headp = m_head = iflib_remove_mbuf(txq);
3427 		if (err == EFBIG) {
3428 			txq->ift_txd_encap_efbig++;
3429 			if (remap < 2) {
3430 				remap = 1;
3431 				goto defrag;
3432 			}
3433 		}
3434 		goto defrag_failed;
3435 	}
3436 	/*
3437 	 * err can't possibly be non-zero here, so we don't neet to test it
3438 	 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3439 	 */
3440 	return (err);
3441 
3442 defrag_failed:
3443 	txq->ift_mbuf_defrag_failed++;
3444 	txq->ift_map_failed++;
3445 	m_freem(*m_headp);
3446 	DBG_COUNTER_INC(tx_frees);
3447 	*m_headp = NULL;
3448 	DBG_COUNTER_INC(encap_txd_encap_fail);
3449 	return (ENOMEM);
3450 }
3451 
3452 static void
3453 iflib_tx_desc_free(iflib_txq_t txq, int n)
3454 {
3455 	uint32_t qsize, cidx, mask, gen;
3456 	struct mbuf *m, **ifsd_m;
3457 	bool do_prefetch;
3458 
3459 	cidx = txq->ift_cidx;
3460 	gen = txq->ift_gen;
3461 	qsize = txq->ift_size;
3462 	mask = qsize-1;
3463 	ifsd_m = txq->ift_sds.ifsd_m;
3464 	do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3465 
3466 	while (n-- > 0) {
3467 		if (do_prefetch) {
3468 			prefetch(ifsd_m[(cidx + 3) & mask]);
3469 			prefetch(ifsd_m[(cidx + 4) & mask]);
3470 		}
3471 		if ((m = ifsd_m[cidx]) != NULL) {
3472 			prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3473 			if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3474 				bus_dmamap_sync(txq->ift_tso_buf_tag,
3475 				    txq->ift_sds.ifsd_tso_map[cidx],
3476 				    BUS_DMASYNC_POSTWRITE);
3477 				bus_dmamap_unload(txq->ift_tso_buf_tag,
3478 				    txq->ift_sds.ifsd_tso_map[cidx]);
3479 			} else {
3480 				bus_dmamap_sync(txq->ift_buf_tag,
3481 				    txq->ift_sds.ifsd_map[cidx],
3482 				    BUS_DMASYNC_POSTWRITE);
3483 				bus_dmamap_unload(txq->ift_buf_tag,
3484 				    txq->ift_sds.ifsd_map[cidx]);
3485 			}
3486 			/* XXX we don't support any drivers that batch packets yet */
3487 			MPASS(m->m_nextpkt == NULL);
3488 			m_freem(m);
3489 			ifsd_m[cidx] = NULL;
3490 #if MEMORY_LOGGING
3491 			txq->ift_dequeued++;
3492 #endif
3493 			DBG_COUNTER_INC(tx_frees);
3494 		}
3495 		if (__predict_false(++cidx == qsize)) {
3496 			cidx = 0;
3497 			gen = 0;
3498 		}
3499 	}
3500 	txq->ift_cidx = cidx;
3501 	txq->ift_gen = gen;
3502 }
3503 
3504 static __inline int
3505 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3506 {
3507 	int reclaim;
3508 	if_ctx_t ctx = txq->ift_ctx;
3509 
3510 	KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3511 	MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3512 
3513 	/*
3514 	 * Need a rate-limiting check so that this isn't called every time
3515 	 */
3516 	iflib_tx_credits_update(ctx, txq);
3517 	reclaim = DESC_RECLAIMABLE(txq);
3518 
3519 	if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3520 #ifdef INVARIANTS
3521 		if (iflib_verbose_debug) {
3522 			printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3523 			       txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3524 			       reclaim, thresh);
3525 
3526 		}
3527 #endif
3528 		return (0);
3529 	}
3530 	iflib_tx_desc_free(txq, reclaim);
3531 	txq->ift_cleaned += reclaim;
3532 	txq->ift_in_use -= reclaim;
3533 
3534 	return (reclaim);
3535 }
3536 
3537 static struct mbuf **
3538 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3539 {
3540 	int next, size;
3541 	struct mbuf **items;
3542 
3543 	size = r->size;
3544 	next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3545 	items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3546 
3547 	prefetch(items[(cidx + offset) & (size-1)]);
3548 	if (remaining > 1) {
3549 		prefetch2cachelines(&items[next]);
3550 		prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3551 		prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3552 		prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3553 	}
3554 	return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3555 }
3556 
3557 static void
3558 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3559 {
3560 
3561 	ifmp_ring_check_drainage(txq->ift_br, budget);
3562 }
3563 
3564 static uint32_t
3565 iflib_txq_can_drain(struct ifmp_ring *r)
3566 {
3567 	iflib_txq_t txq = r->cookie;
3568 	if_ctx_t ctx = txq->ift_ctx;
3569 
3570 	if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3571 		return (1);
3572 	bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3573 	    BUS_DMASYNC_POSTREAD);
3574 	return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3575 	    false));
3576 }
3577 
3578 static uint32_t
3579 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3580 {
3581 	iflib_txq_t txq = r->cookie;
3582 	if_ctx_t ctx = txq->ift_ctx;
3583 	if_t ifp = ctx->ifc_ifp;
3584 	struct mbuf *m, **mp;
3585 	int avail, bytes_sent, consumed, count, err, i, in_use_prev;
3586 	int mcast_sent, pkt_sent, reclaimed, txq_avail;
3587 	bool do_prefetch, rang, ring;
3588 
3589 	if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3590 			    !LINK_ACTIVE(ctx))) {
3591 		DBG_COUNTER_INC(txq_drain_notready);
3592 		return (0);
3593 	}
3594 	reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3595 	rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3596 	avail = IDXDIFF(pidx, cidx, r->size);
3597 	if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3598 		DBG_COUNTER_INC(txq_drain_flushing);
3599 		for (i = 0; i < avail; i++) {
3600 			if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3601 				m_free(r->items[(cidx + i) & (r->size-1)]);
3602 			r->items[(cidx + i) & (r->size-1)] = NULL;
3603 		}
3604 		return (avail);
3605 	}
3606 
3607 	if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3608 		txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3609 		CALLOUT_LOCK(txq);
3610 		callout_stop(&txq->ift_timer);
3611 		CALLOUT_UNLOCK(txq);
3612 		DBG_COUNTER_INC(txq_drain_oactive);
3613 		return (0);
3614 	}
3615 	if (reclaimed)
3616 		txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3617 	consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3618 	count = MIN(avail, TX_BATCH_SIZE);
3619 #ifdef INVARIANTS
3620 	if (iflib_verbose_debug)
3621 		printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3622 		       avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3623 #endif
3624 	do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3625 	txq_avail = TXQ_AVAIL(txq);
3626 	err = 0;
3627 	for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) {
3628 		int rem = do_prefetch ? count - i : 0;
3629 
3630 		mp = _ring_peek_one(r, cidx, i, rem);
3631 		MPASS(mp != NULL && *mp != NULL);
3632 		if (__predict_false(*mp == (struct mbuf *)txq)) {
3633 			consumed++;
3634 			continue;
3635 		}
3636 		in_use_prev = txq->ift_in_use;
3637 		err = iflib_encap(txq, mp);
3638 		if (__predict_false(err)) {
3639 			/* no room - bail out */
3640 			if (err == ENOBUFS)
3641 				break;
3642 			consumed++;
3643 			/* we can't send this packet - skip it */
3644 			continue;
3645 		}
3646 		consumed++;
3647 		pkt_sent++;
3648 		m = *mp;
3649 		DBG_COUNTER_INC(tx_sent);
3650 		bytes_sent += m->m_pkthdr.len;
3651 		mcast_sent += !!(m->m_flags & M_MCAST);
3652 		txq_avail = TXQ_AVAIL(txq);
3653 
3654 		txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3655 		ETHER_BPF_MTAP(ifp, m);
3656 		if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3657 			break;
3658 		rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3659 	}
3660 
3661 	/* deliberate use of bitwise or to avoid gratuitous short-circuit */
3662 	ring = rang ? false  : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3663 	iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3664 	if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3665 	if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3666 	if (mcast_sent)
3667 		if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3668 #ifdef INVARIANTS
3669 	if (iflib_verbose_debug)
3670 		printf("consumed=%d\n", consumed);
3671 #endif
3672 	return (consumed);
3673 }
3674 
3675 static uint32_t
3676 iflib_txq_drain_always(struct ifmp_ring *r)
3677 {
3678 	return (1);
3679 }
3680 
3681 static uint32_t
3682 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3683 {
3684 	int i, avail;
3685 	struct mbuf **mp;
3686 	iflib_txq_t txq;
3687 
3688 	txq = r->cookie;
3689 
3690 	txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3691 	CALLOUT_LOCK(txq);
3692 	callout_stop(&txq->ift_timer);
3693 	CALLOUT_UNLOCK(txq);
3694 
3695 	avail = IDXDIFF(pidx, cidx, r->size);
3696 	for (i = 0; i < avail; i++) {
3697 		mp = _ring_peek_one(r, cidx, i, avail - i);
3698 		if (__predict_false(*mp == (struct mbuf *)txq))
3699 			continue;
3700 		m_freem(*mp);
3701 		DBG_COUNTER_INC(tx_frees);
3702 	}
3703 	MPASS(ifmp_ring_is_stalled(r) == 0);
3704 	return (avail);
3705 }
3706 
3707 static void
3708 iflib_ifmp_purge(iflib_txq_t txq)
3709 {
3710 	struct ifmp_ring *r;
3711 
3712 	r = txq->ift_br;
3713 	r->drain = iflib_txq_drain_free;
3714 	r->can_drain = iflib_txq_drain_always;
3715 
3716 	ifmp_ring_check_drainage(r, r->size);
3717 
3718 	r->drain = iflib_txq_drain;
3719 	r->can_drain = iflib_txq_can_drain;
3720 }
3721 
3722 static void
3723 _task_fn_tx(void *context)
3724 {
3725 	iflib_txq_t txq = context;
3726 	if_ctx_t ctx = txq->ift_ctx;
3727 #if defined(ALTQ) || defined(DEV_NETMAP)
3728 	if_t ifp = ctx->ifc_ifp;
3729 #endif
3730 	int abdicate = ctx->ifc_sysctl_tx_abdicate;
3731 
3732 #ifdef IFLIB_DIAGNOSTICS
3733 	txq->ift_cpu_exec_count[curcpu]++;
3734 #endif
3735 	if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3736 		return;
3737 #ifdef DEV_NETMAP
3738 	if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3739 		bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3740 		    BUS_DMASYNC_POSTREAD);
3741 		if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3742 			netmap_tx_irq(ifp, txq->ift_id);
3743 		if (ctx->ifc_flags & IFC_LEGACY)
3744 			IFDI_INTR_ENABLE(ctx);
3745 		else
3746 			IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3747 		return;
3748 	}
3749 #endif
3750 #ifdef ALTQ
3751 	if (ALTQ_IS_ENABLED(&ifp->if_snd))
3752 		iflib_altq_if_start(ifp);
3753 #endif
3754 	if (txq->ift_db_pending)
3755 		ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3756 	else if (!abdicate)
3757 		ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3758 	/*
3759 	 * When abdicating, we always need to check drainage, not just when we don't enqueue
3760 	 */
3761 	if (abdicate)
3762 		ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3763 	if (ctx->ifc_flags & IFC_LEGACY)
3764 		IFDI_INTR_ENABLE(ctx);
3765 	else
3766 		IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3767 }
3768 
3769 static void
3770 _task_fn_rx(void *context)
3771 {
3772 	iflib_rxq_t rxq = context;
3773 	if_ctx_t ctx = rxq->ifr_ctx;
3774 	bool more;
3775 	uint16_t budget;
3776 
3777 #ifdef IFLIB_DIAGNOSTICS
3778 	rxq->ifr_cpu_exec_count[curcpu]++;
3779 #endif
3780 	DBG_COUNTER_INC(task_fn_rxs);
3781 	if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3782 		return;
3783 	more = true;
3784 #ifdef DEV_NETMAP
3785 	if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3786 		u_int work = 0;
3787 		if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3788 			more = false;
3789 		}
3790 	}
3791 #endif
3792 	budget = ctx->ifc_sysctl_rx_budget;
3793 	if (budget == 0)
3794 		budget = 16;	/* XXX */
3795 	if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3796 		if (ctx->ifc_flags & IFC_LEGACY)
3797 			IFDI_INTR_ENABLE(ctx);
3798 		else
3799 			IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3800 		DBG_COUNTER_INC(rx_intr_enables);
3801 	}
3802 	if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3803 		return;
3804 	if (more)
3805 		GROUPTASK_ENQUEUE(&rxq->ifr_task);
3806 }
3807 
3808 static void
3809 _task_fn_admin(void *context)
3810 {
3811 	if_ctx_t ctx = context;
3812 	if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3813 	iflib_txq_t txq;
3814 	int i;
3815 	bool oactive, running, do_reset, do_watchdog, in_detach;
3816 	uint32_t reset_on = hz / 2;
3817 
3818 	STATE_LOCK(ctx);
3819 	running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3820 	oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3821 	do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3822 	do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3823 	in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3824 	ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3825 	STATE_UNLOCK(ctx);
3826 
3827 	if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3828 		return;
3829 	if (in_detach)
3830 		return;
3831 
3832 	CTX_LOCK(ctx);
3833 	for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3834 		CALLOUT_LOCK(txq);
3835 		callout_stop(&txq->ift_timer);
3836 		CALLOUT_UNLOCK(txq);
3837 	}
3838 	if (do_watchdog) {
3839 		ctx->ifc_watchdog_events++;
3840 		IFDI_WATCHDOG_RESET(ctx);
3841 	}
3842 	IFDI_UPDATE_ADMIN_STATUS(ctx);
3843 	for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3844 #ifdef DEV_NETMAP
3845 		reset_on = hz / 2;
3846 		if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3847 			iflib_netmap_timer_adjust(ctx, txq, &reset_on);
3848 #endif
3849 		callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3850 	}
3851 	IFDI_LINK_INTR_ENABLE(ctx);
3852 	if (do_reset)
3853 		iflib_if_init_locked(ctx);
3854 	CTX_UNLOCK(ctx);
3855 
3856 	if (LINK_ACTIVE(ctx) == 0)
3857 		return;
3858 	for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3859 		iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3860 }
3861 
3862 
3863 static void
3864 _task_fn_iov(void *context)
3865 {
3866 	if_ctx_t ctx = context;
3867 
3868 	if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3869 	    !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3870 		return;
3871 
3872 	CTX_LOCK(ctx);
3873 	IFDI_VFLR_HANDLE(ctx);
3874 	CTX_UNLOCK(ctx);
3875 }
3876 
3877 static int
3878 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3879 {
3880 	int err;
3881 	if_int_delay_info_t info;
3882 	if_ctx_t ctx;
3883 
3884 	info = (if_int_delay_info_t)arg1;
3885 	ctx = info->iidi_ctx;
3886 	info->iidi_req = req;
3887 	info->iidi_oidp = oidp;
3888 	CTX_LOCK(ctx);
3889 	err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3890 	CTX_UNLOCK(ctx);
3891 	return (err);
3892 }
3893 
3894 /*********************************************************************
3895  *
3896  *  IFNET FUNCTIONS
3897  *
3898  **********************************************************************/
3899 
3900 static void
3901 iflib_if_init_locked(if_ctx_t ctx)
3902 {
3903 	iflib_stop(ctx);
3904 	iflib_init_locked(ctx);
3905 }
3906 
3907 
3908 static void
3909 iflib_if_init(void *arg)
3910 {
3911 	if_ctx_t ctx = arg;
3912 
3913 	CTX_LOCK(ctx);
3914 	iflib_if_init_locked(ctx);
3915 	CTX_UNLOCK(ctx);
3916 }
3917 
3918 static int
3919 iflib_if_transmit(if_t ifp, struct mbuf *m)
3920 {
3921 	if_ctx_t	ctx = if_getsoftc(ifp);
3922 
3923 	iflib_txq_t txq;
3924 	int err, qidx;
3925 	int abdicate = ctx->ifc_sysctl_tx_abdicate;
3926 
3927 	if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3928 		DBG_COUNTER_INC(tx_frees);
3929 		m_freem(m);
3930 		return (ENETDOWN);
3931 	}
3932 
3933 	MPASS(m->m_nextpkt == NULL);
3934 	/* ALTQ-enabled interfaces always use queue 0. */
3935 	qidx = 0;
3936 	if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3937 		qidx = QIDX(ctx, m);
3938 	/*
3939 	 * XXX calculate buf_ring based on flowid (divvy up bits?)
3940 	 */
3941 	txq = &ctx->ifc_txqs[qidx];
3942 
3943 #ifdef DRIVER_BACKPRESSURE
3944 	if (txq->ift_closed) {
3945 		while (m != NULL) {
3946 			next = m->m_nextpkt;
3947 			m->m_nextpkt = NULL;
3948 			m_freem(m);
3949 			DBG_COUNTER_INC(tx_frees);
3950 			m = next;
3951 		}
3952 		return (ENOBUFS);
3953 	}
3954 #endif
3955 #ifdef notyet
3956 	qidx = count = 0;
3957 	mp = marr;
3958 	next = m;
3959 	do {
3960 		count++;
3961 		next = next->m_nextpkt;
3962 	} while (next != NULL);
3963 
3964 	if (count > nitems(marr))
3965 		if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3966 			/* XXX check nextpkt */
3967 			m_freem(m);
3968 			/* XXX simplify for now */
3969 			DBG_COUNTER_INC(tx_frees);
3970 			return (ENOBUFS);
3971 		}
3972 	for (next = m, i = 0; next != NULL; i++) {
3973 		mp[i] = next;
3974 		next = next->m_nextpkt;
3975 		mp[i]->m_nextpkt = NULL;
3976 	}
3977 #endif
3978 	DBG_COUNTER_INC(tx_seen);
3979 	err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
3980 
3981 	if (abdicate)
3982 		GROUPTASK_ENQUEUE(&txq->ift_task);
3983  	if (err) {
3984 		if (!abdicate)
3985 			GROUPTASK_ENQUEUE(&txq->ift_task);
3986 		/* support forthcoming later */
3987 #ifdef DRIVER_BACKPRESSURE
3988 		txq->ift_closed = TRUE;
3989 #endif
3990 		ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3991 		m_freem(m);
3992 		DBG_COUNTER_INC(tx_frees);
3993 	}
3994 
3995 	return (err);
3996 }
3997 
3998 #ifdef ALTQ
3999 /*
4000  * The overall approach to integrating iflib with ALTQ is to continue to use
4001  * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4002  * ring.  Technically, when using ALTQ, queueing to an intermediate mp_ring
4003  * is redundant/unnecessary, but doing so minimizes the amount of
4004  * ALTQ-specific code required in iflib.  It is assumed that the overhead of
4005  * redundantly queueing to an intermediate mp_ring is swamped by the
4006  * performance limitations inherent in using ALTQ.
4007  *
4008  * When ALTQ support is compiled in, all iflib drivers will use a transmit
4009  * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4010  * given interface.  If ALTQ is enabled for an interface, then all
4011  * transmitted packets for that interface will be submitted to the ALTQ
4012  * subsystem via IFQ_ENQUEUE().  We don't use the legacy if_transmit()
4013  * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4014  * update stats that the iflib machinery handles, and which is sensitve to
4015  * the disused IFF_DRV_OACTIVE flag.  Additionally, iflib_altq_if_start()
4016  * will be installed as the start routine for use by ALTQ facilities that
4017  * need to trigger queue drains on a scheduled basis.
4018  *
4019  */
4020 static void
4021 iflib_altq_if_start(if_t ifp)
4022 {
4023 	struct ifaltq *ifq = &ifp->if_snd;
4024 	struct mbuf *m;
4025 
4026 	IFQ_LOCK(ifq);
4027 	IFQ_DEQUEUE_NOLOCK(ifq, m);
4028 	while (m != NULL) {
4029 		iflib_if_transmit(ifp, m);
4030 		IFQ_DEQUEUE_NOLOCK(ifq, m);
4031 	}
4032 	IFQ_UNLOCK(ifq);
4033 }
4034 
4035 static int
4036 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4037 {
4038 	int err;
4039 
4040 	if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4041 		IFQ_ENQUEUE(&ifp->if_snd, m, err);
4042 		if (err == 0)
4043 			iflib_altq_if_start(ifp);
4044 	} else
4045 		err = iflib_if_transmit(ifp, m);
4046 
4047 	return (err);
4048 }
4049 #endif /* ALTQ */
4050 
4051 static void
4052 iflib_if_qflush(if_t ifp)
4053 {
4054 	if_ctx_t ctx = if_getsoftc(ifp);
4055 	iflib_txq_t txq = ctx->ifc_txqs;
4056 	int i;
4057 
4058 	STATE_LOCK(ctx);
4059 	ctx->ifc_flags |= IFC_QFLUSH;
4060 	STATE_UNLOCK(ctx);
4061 	for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4062 		while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4063 			iflib_txq_check_drain(txq, 0);
4064 	STATE_LOCK(ctx);
4065 	ctx->ifc_flags &= ~IFC_QFLUSH;
4066 	STATE_UNLOCK(ctx);
4067 
4068 	/*
4069 	 * When ALTQ is enabled, this will also take care of purging the
4070 	 * ALTQ queue(s).
4071 	 */
4072 	if_qflush(ifp);
4073 }
4074 
4075 
4076 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4077 		     IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4078 		     IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4079 		     IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM)
4080 
4081 static int
4082 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4083 {
4084 	if_ctx_t ctx = if_getsoftc(ifp);
4085 	struct ifreq	*ifr = (struct ifreq *)data;
4086 #if defined(INET) || defined(INET6)
4087 	struct ifaddr	*ifa = (struct ifaddr *)data;
4088 #endif
4089 	bool		avoid_reset = false;
4090 	int		err = 0, reinit = 0, bits;
4091 
4092 	switch (command) {
4093 	case SIOCSIFADDR:
4094 #ifdef INET
4095 		if (ifa->ifa_addr->sa_family == AF_INET)
4096 			avoid_reset = true;
4097 #endif
4098 #ifdef INET6
4099 		if (ifa->ifa_addr->sa_family == AF_INET6)
4100 			avoid_reset = true;
4101 #endif
4102 		/*
4103 		** Calling init results in link renegotiation,
4104 		** so we avoid doing it when possible.
4105 		*/
4106 		if (avoid_reset) {
4107 			if_setflagbits(ifp, IFF_UP,0);
4108 			if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4109 				reinit = 1;
4110 #ifdef INET
4111 			if (!(if_getflags(ifp) & IFF_NOARP))
4112 				arp_ifinit(ifp, ifa);
4113 #endif
4114 		} else
4115 			err = ether_ioctl(ifp, command, data);
4116 		break;
4117 	case SIOCSIFMTU:
4118 		CTX_LOCK(ctx);
4119 		if (ifr->ifr_mtu == if_getmtu(ifp)) {
4120 			CTX_UNLOCK(ctx);
4121 			break;
4122 		}
4123 		bits = if_getdrvflags(ifp);
4124 		/* stop the driver and free any clusters before proceeding */
4125 		iflib_stop(ctx);
4126 
4127 		if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4128 			STATE_LOCK(ctx);
4129 			if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4130 				ctx->ifc_flags |= IFC_MULTISEG;
4131 			else
4132 				ctx->ifc_flags &= ~IFC_MULTISEG;
4133 			STATE_UNLOCK(ctx);
4134 			err = if_setmtu(ifp, ifr->ifr_mtu);
4135 		}
4136 		iflib_init_locked(ctx);
4137 		STATE_LOCK(ctx);
4138 		if_setdrvflags(ifp, bits);
4139 		STATE_UNLOCK(ctx);
4140 		CTX_UNLOCK(ctx);
4141 		break;
4142 	case SIOCSIFFLAGS:
4143 		CTX_LOCK(ctx);
4144 		if (if_getflags(ifp) & IFF_UP) {
4145 			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4146 				if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4147 				    (IFF_PROMISC | IFF_ALLMULTI)) {
4148 					err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4149 				}
4150 			} else
4151 				reinit = 1;
4152 		} else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4153 			iflib_stop(ctx);
4154 		}
4155 		ctx->ifc_if_flags = if_getflags(ifp);
4156 		CTX_UNLOCK(ctx);
4157 		break;
4158 	case SIOCADDMULTI:
4159 	case SIOCDELMULTI:
4160 		if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4161 			CTX_LOCK(ctx);
4162 			IFDI_INTR_DISABLE(ctx);
4163 			IFDI_MULTI_SET(ctx);
4164 			IFDI_INTR_ENABLE(ctx);
4165 			CTX_UNLOCK(ctx);
4166 		}
4167 		break;
4168 	case SIOCSIFMEDIA:
4169 		CTX_LOCK(ctx);
4170 		IFDI_MEDIA_SET(ctx);
4171 		CTX_UNLOCK(ctx);
4172 		/* FALLTHROUGH */
4173 	case SIOCGIFMEDIA:
4174 	case SIOCGIFXMEDIA:
4175 		err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4176 		break;
4177 	case SIOCGI2C:
4178 	{
4179 		struct ifi2creq i2c;
4180 
4181 		err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4182 		if (err != 0)
4183 			break;
4184 		if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4185 			err = EINVAL;
4186 			break;
4187 		}
4188 		if (i2c.len > sizeof(i2c.data)) {
4189 			err = EINVAL;
4190 			break;
4191 		}
4192 
4193 		if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4194 			err = copyout(&i2c, ifr_data_get_ptr(ifr),
4195 			    sizeof(i2c));
4196 		break;
4197 	}
4198 	case SIOCSIFCAP:
4199 	{
4200 		int mask, setmask, oldmask;
4201 
4202 		oldmask = if_getcapenable(ifp);
4203 		mask = ifr->ifr_reqcap ^ oldmask;
4204 		mask &= ctx->ifc_softc_ctx.isc_capabilities;
4205 		setmask = 0;
4206 #ifdef TCP_OFFLOAD
4207 		setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4208 #endif
4209 		setmask |= (mask & IFCAP_FLAGS);
4210 		setmask |= (mask & IFCAP_WOL);
4211 
4212 		/*
4213 		 * If any RX csum has changed, change all the ones that
4214 		 * are supported by the driver.
4215 		 */
4216 		if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4217 			setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4218 			    (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4219 		}
4220 
4221 		/*
4222 		 * want to ensure that traffic has stopped before we change any of the flags
4223 		 */
4224 		if (setmask) {
4225 			CTX_LOCK(ctx);
4226 			bits = if_getdrvflags(ifp);
4227 			if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4228 				iflib_stop(ctx);
4229 			STATE_LOCK(ctx);
4230 			if_togglecapenable(ifp, setmask);
4231 			STATE_UNLOCK(ctx);
4232 			if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4233 				iflib_init_locked(ctx);
4234 			STATE_LOCK(ctx);
4235 			if_setdrvflags(ifp, bits);
4236 			STATE_UNLOCK(ctx);
4237 			CTX_UNLOCK(ctx);
4238 		}
4239 		if_vlancap(ifp);
4240 		break;
4241 	}
4242 	case SIOCGPRIVATE_0:
4243 	case SIOCSDRVSPEC:
4244 	case SIOCGDRVSPEC:
4245 		CTX_LOCK(ctx);
4246 		err = IFDI_PRIV_IOCTL(ctx, command, data);
4247 		CTX_UNLOCK(ctx);
4248 		break;
4249 	default:
4250 		err = ether_ioctl(ifp, command, data);
4251 		break;
4252 	}
4253 	if (reinit)
4254 		iflib_if_init(ctx);
4255 	return (err);
4256 }
4257 
4258 static uint64_t
4259 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4260 {
4261 	if_ctx_t ctx = if_getsoftc(ifp);
4262 
4263 	return (IFDI_GET_COUNTER(ctx, cnt));
4264 }
4265 
4266 /*********************************************************************
4267  *
4268  *  OTHER FUNCTIONS EXPORTED TO THE STACK
4269  *
4270  **********************************************************************/
4271 
4272 static void
4273 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4274 {
4275 	if_ctx_t ctx = if_getsoftc(ifp);
4276 
4277 	if ((void *)ctx != arg)
4278 		return;
4279 
4280 	if ((vtag == 0) || (vtag > 4095))
4281 		return;
4282 
4283 	CTX_LOCK(ctx);
4284 	IFDI_VLAN_REGISTER(ctx, vtag);
4285 	/* Re-init to load the changes */
4286 	if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4287 		iflib_if_init_locked(ctx);
4288 	CTX_UNLOCK(ctx);
4289 }
4290 
4291 static void
4292 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4293 {
4294 	if_ctx_t ctx = if_getsoftc(ifp);
4295 
4296 	if ((void *)ctx != arg)
4297 		return;
4298 
4299 	if ((vtag == 0) || (vtag > 4095))
4300 		return;
4301 
4302 	CTX_LOCK(ctx);
4303 	IFDI_VLAN_UNREGISTER(ctx, vtag);
4304 	/* Re-init to load the changes */
4305 	if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4306 		iflib_if_init_locked(ctx);
4307 	CTX_UNLOCK(ctx);
4308 }
4309 
4310 static void
4311 iflib_led_func(void *arg, int onoff)
4312 {
4313 	if_ctx_t ctx = arg;
4314 
4315 	CTX_LOCK(ctx);
4316 	IFDI_LED_FUNC(ctx, onoff);
4317 	CTX_UNLOCK(ctx);
4318 }
4319 
4320 /*********************************************************************
4321  *
4322  *  BUS FUNCTION DEFINITIONS
4323  *
4324  **********************************************************************/
4325 
4326 int
4327 iflib_device_probe(device_t dev)
4328 {
4329 	const pci_vendor_info_t *ent;
4330 	if_shared_ctx_t sctx;
4331 	uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id;
4332 	uint16_t pci_vendor_id;
4333 
4334 	if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4335 		return (ENOTSUP);
4336 
4337 	pci_vendor_id = pci_get_vendor(dev);
4338 	pci_device_id = pci_get_device(dev);
4339 	pci_subvendor_id = pci_get_subvendor(dev);
4340 	pci_subdevice_id = pci_get_subdevice(dev);
4341 	pci_rev_id = pci_get_revid(dev);
4342 	if (sctx->isc_parse_devinfo != NULL)
4343 		sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4344 
4345 	ent = sctx->isc_vendor_info;
4346 	while (ent->pvi_vendor_id != 0) {
4347 		if (pci_vendor_id != ent->pvi_vendor_id) {
4348 			ent++;
4349 			continue;
4350 		}
4351 		if ((pci_device_id == ent->pvi_device_id) &&
4352 		    ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4353 		     (ent->pvi_subvendor_id == 0)) &&
4354 		    ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4355 		     (ent->pvi_subdevice_id == 0)) &&
4356 		    ((pci_rev_id == ent->pvi_rev_id) ||
4357 		     (ent->pvi_rev_id == 0))) {
4358 
4359 			device_set_desc_copy(dev, ent->pvi_name);
4360 			/* this needs to be changed to zero if the bus probing code
4361 			 * ever stops re-probing on best match because the sctx
4362 			 * may have its values over written by register calls
4363 			 * in subsequent probes
4364 			 */
4365 			return (BUS_PROBE_DEFAULT);
4366 		}
4367 		ent++;
4368 	}
4369 	return (ENXIO);
4370 }
4371 
4372 int
4373 iflib_device_probe_vendor(device_t dev)
4374 {
4375 	int probe;
4376 
4377 	probe = iflib_device_probe(dev);
4378 	if (probe == BUS_PROBE_DEFAULT)
4379 		return (BUS_PROBE_VENDOR);
4380 	else
4381 		return (probe);
4382 }
4383 
4384 static void
4385 iflib_reset_qvalues(if_ctx_t ctx)
4386 {
4387 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4388 	if_shared_ctx_t sctx = ctx->ifc_sctx;
4389 	device_t dev = ctx->ifc_dev;
4390 	int i;
4391 
4392 	if (ctx->ifc_sysctl_ntxqs != 0)
4393 		scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4394 	if (ctx->ifc_sysctl_nrxqs != 0)
4395 		scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4396 
4397 	for (i = 0; i < sctx->isc_ntxqs; i++) {
4398 		if (ctx->ifc_sysctl_ntxds[i] != 0)
4399 			scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4400 		else
4401 			scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4402 	}
4403 
4404 	for (i = 0; i < sctx->isc_nrxqs; i++) {
4405 		if (ctx->ifc_sysctl_nrxds[i] != 0)
4406 			scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4407 		else
4408 			scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4409 	}
4410 
4411 	for (i = 0; i < sctx->isc_nrxqs; i++) {
4412 		if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4413 			device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4414 				      i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4415 			scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4416 		}
4417 		if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4418 			device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4419 				      i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4420 			scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4421 		}
4422 		if (!powerof2(scctx->isc_nrxd[i])) {
4423 			device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4424 				      i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4425 			scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4426 		}
4427 	}
4428 
4429 	for (i = 0; i < sctx->isc_ntxqs; i++) {
4430 		if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4431 			device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4432 				      i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4433 			scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4434 		}
4435 		if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4436 			device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4437 				      i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4438 			scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4439 		}
4440 		if (!powerof2(scctx->isc_ntxd[i])) {
4441 			device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4442 				      i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4443 			scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4444 		}
4445 	}
4446 }
4447 
4448 static void
4449 iflib_add_pfil(if_ctx_t ctx)
4450 {
4451 	struct pfil_head *pfil;
4452 	struct pfil_head_args pa;
4453 	iflib_rxq_t rxq;
4454 	int i;
4455 
4456 	pa.pa_version = PFIL_VERSION;
4457 	pa.pa_flags = PFIL_IN;
4458 	pa.pa_type = PFIL_TYPE_ETHERNET;
4459 	pa.pa_headname = ctx->ifc_ifp->if_xname;
4460 	pfil = pfil_head_register(&pa);
4461 
4462 	for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4463 		rxq->pfil = pfil;
4464 	}
4465 }
4466 
4467 static void
4468 iflib_rem_pfil(if_ctx_t ctx)
4469 {
4470 	struct pfil_head *pfil;
4471 	iflib_rxq_t rxq;
4472 	int i;
4473 
4474 	rxq = ctx->ifc_rxqs;
4475 	pfil = rxq->pfil;
4476 	for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4477 		rxq->pfil = NULL;
4478 	}
4479 	pfil_head_unregister(pfil);
4480 }
4481 
4482 static uint16_t
4483 get_ctx_core_offset(if_ctx_t ctx)
4484 {
4485 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4486 	struct cpu_offset *op;
4487 	uint16_t qc;
4488 	uint16_t ret = ctx->ifc_sysctl_core_offset;
4489 
4490 	if (ret != CORE_OFFSET_UNSPECIFIED)
4491 		return (ret);
4492 
4493 	if (ctx->ifc_sysctl_separate_txrx)
4494 		qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets;
4495 	else
4496 		qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets);
4497 
4498 	mtx_lock(&cpu_offset_mtx);
4499 	SLIST_FOREACH(op, &cpu_offsets, entries) {
4500 		if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4501 			ret = op->offset;
4502 			op->offset += qc;
4503 			MPASS(op->refcount < UINT_MAX);
4504 			op->refcount++;
4505 			break;
4506 		}
4507 	}
4508 	if (ret == CORE_OFFSET_UNSPECIFIED) {
4509 		ret = 0;
4510 		op = malloc(sizeof(struct cpu_offset), M_IFLIB,
4511 		    M_NOWAIT | M_ZERO);
4512 		if (op == NULL) {
4513 			device_printf(ctx->ifc_dev,
4514 			    "allocation for cpu offset failed.\n");
4515 		} else {
4516 			op->offset = qc;
4517 			op->refcount = 1;
4518 			CPU_COPY(&ctx->ifc_cpus, &op->set);
4519 			SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
4520 		}
4521 	}
4522 	mtx_unlock(&cpu_offset_mtx);
4523 
4524 	return (ret);
4525 }
4526 
4527 static void
4528 unref_ctx_core_offset(if_ctx_t ctx)
4529 {
4530 	struct cpu_offset *op, *top;
4531 
4532 	mtx_lock(&cpu_offset_mtx);
4533 	SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
4534 		if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4535 			MPASS(op->refcount > 0);
4536 			op->refcount--;
4537 			if (op->refcount == 0) {
4538 				SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
4539 				free(op, M_IFLIB);
4540 			}
4541 			break;
4542 		}
4543 	}
4544 	mtx_unlock(&cpu_offset_mtx);
4545 }
4546 
4547 int
4548 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4549 {
4550 	if_ctx_t ctx;
4551 	if_t ifp;
4552 	if_softc_ctx_t scctx;
4553 	kobjop_desc_t kobj_desc;
4554 	kobj_method_t *kobj_method;
4555 	int err, msix, rid;
4556 	uint16_t main_rxq, main_txq;
4557 
4558 	ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4559 
4560 	if (sc == NULL) {
4561 		sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4562 		device_set_softc(dev, ctx);
4563 		ctx->ifc_flags |= IFC_SC_ALLOCATED;
4564 	}
4565 
4566 	ctx->ifc_sctx = sctx;
4567 	ctx->ifc_dev = dev;
4568 	ctx->ifc_softc = sc;
4569 
4570 	if ((err = iflib_register(ctx)) != 0) {
4571 		device_printf(dev, "iflib_register failed %d\n", err);
4572 		goto fail_ctx_free;
4573 	}
4574 	iflib_add_device_sysctl_pre(ctx);
4575 
4576 	scctx = &ctx->ifc_softc_ctx;
4577 	ifp = ctx->ifc_ifp;
4578 
4579 	iflib_reset_qvalues(ctx);
4580 	CTX_LOCK(ctx);
4581 	if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4582 		device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4583 		goto fail_unlock;
4584 	}
4585 	_iflib_pre_assert(scctx);
4586 	ctx->ifc_txrx = *scctx->isc_txrx;
4587 
4588 	if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
4589 		ctx->ifc_mediap = scctx->isc_media;
4590 
4591 #ifdef INVARIANTS
4592 	if (scctx->isc_capabilities & IFCAP_TXCSUM)
4593 		MPASS(scctx->isc_tx_csum_flags);
4594 #endif
4595 
4596 	if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS);
4597 	if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS);
4598 
4599 	if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4600 		scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4601 	if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4602 		scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4603 
4604 	main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4605 	main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4606 
4607 	/* XXX change for per-queue sizes */
4608 	device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4609 	    scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4610 
4611 	if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4612 	    MAX_SINGLE_PACKET_FRACTION)
4613 		scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4614 		    MAX_SINGLE_PACKET_FRACTION);
4615 	if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4616 	    MAX_SINGLE_PACKET_FRACTION)
4617 		scctx->isc_tx_tso_segments_max = max(1,
4618 		    scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4619 
4620 	/* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4621 	if (if_getcapabilities(ifp) & IFCAP_TSO) {
4622 		/*
4623 		 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4624 		 * but some MACs do.
4625 		 */
4626 		if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4627 		    IP_MAXPACKET));
4628 		/*
4629 		 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4630 		 * into account.  In the worst case, each of these calls will
4631 		 * add another mbuf and, thus, the requirement for another DMA
4632 		 * segment.  So for best performance, it doesn't make sense to
4633 		 * advertize a maximum of TSO segments that typically will
4634 		 * require defragmentation in iflib_encap().
4635 		 */
4636 		if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4637 		if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4638 	}
4639 	if (scctx->isc_rss_table_size == 0)
4640 		scctx->isc_rss_table_size = 64;
4641 	scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4642 
4643 	GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4644 	/* XXX format name */
4645 	taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4646 	    NULL, NULL, "admin");
4647 
4648 	/* Set up cpu set.  If it fails, use the set of all CPUs. */
4649 	if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4650 		device_printf(dev, "Unable to fetch CPU list\n");
4651 		CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4652 	}
4653 	MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4654 
4655 	/*
4656 	** Now set up MSI or MSI-X, should return us the number of supported
4657 	** vectors (will be 1 for a legacy interrupt and MSI).
4658 	*/
4659 	if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4660 		msix = scctx->isc_vectors;
4661 	} else if (scctx->isc_msix_bar != 0)
4662 	       /*
4663 		* The simple fact that isc_msix_bar is not 0 does not mean we
4664 		* we have a good value there that is known to work.
4665 		*/
4666 		msix = iflib_msix_init(ctx);
4667 	else {
4668 		scctx->isc_vectors = 1;
4669 		scctx->isc_ntxqsets = 1;
4670 		scctx->isc_nrxqsets = 1;
4671 		scctx->isc_intr = IFLIB_INTR_LEGACY;
4672 		msix = 0;
4673 	}
4674 	/* Get memory for the station queues */
4675 	if ((err = iflib_queues_alloc(ctx))) {
4676 		device_printf(dev, "Unable to allocate queue memory\n");
4677 		goto fail_intr_free;
4678 	}
4679 
4680 	if ((err = iflib_qset_structures_setup(ctx)))
4681 		goto fail_queues;
4682 
4683 	/*
4684 	 * Now that we know how many queues there are, get the core offset.
4685 	 */
4686 	ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
4687 
4688 	/*
4689 	 * Group taskqueues aren't properly set up until SMP is started,
4690 	 * so we disable interrupts until we can handle them post
4691 	 * SI_SUB_SMP.
4692 	 *
4693 	 * XXX: disabling interrupts doesn't actually work, at least for
4694 	 * the non-MSI case.  When they occur before SI_SUB_SMP completes,
4695 	 * we do null handling and depend on this not causing too large an
4696 	 * interrupt storm.
4697 	 */
4698 	IFDI_INTR_DISABLE(ctx);
4699 
4700 	if (msix > 1) {
4701 		/*
4702 		 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
4703 		 * aren't the default NULL implementation.
4704 		 */
4705 		kobj_desc = &ifdi_rx_queue_intr_enable_desc;
4706 		kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4707 		    kobj_desc);
4708 		if (kobj_method == &kobj_desc->deflt) {
4709 			device_printf(dev,
4710 			    "MSI-X requires ifdi_rx_queue_intr_enable method");
4711 			err = EOPNOTSUPP;
4712 			goto fail_queues;
4713 		}
4714 		kobj_desc = &ifdi_tx_queue_intr_enable_desc;
4715 		kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4716 		    kobj_desc);
4717 		if (kobj_method == &kobj_desc->deflt) {
4718 			device_printf(dev,
4719 			    "MSI-X requires ifdi_tx_queue_intr_enable method");
4720 			err = EOPNOTSUPP;
4721 			goto fail_queues;
4722 		}
4723 
4724 		/*
4725 		 * Assign the MSI-X vectors.
4726 		 * Note that the default NULL ifdi_msix_intr_assign method will
4727 		 * fail here, too.
4728 		 */
4729 		err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
4730 		if (err != 0) {
4731 			device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
4732 			    err);
4733 			goto fail_queues;
4734 		}
4735 	} else if (scctx->isc_intr != IFLIB_INTR_MSIX) {
4736 		rid = 0;
4737 		if (scctx->isc_intr == IFLIB_INTR_MSI) {
4738 			MPASS(msix == 1);
4739 			rid = 1;
4740 		}
4741 		if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4742 			device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4743 			goto fail_queues;
4744 		}
4745 	} else {
4746 		device_printf(dev,
4747 		    "Cannot use iflib with only 1 MSI-X interrupt!\n");
4748 		err = ENODEV;
4749 		goto fail_intr_free;
4750 	}
4751 
4752 	ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4753 
4754 	if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4755 		device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4756 		goto fail_detach;
4757 	}
4758 
4759 	/*
4760 	 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4761 	 * This must appear after the call to ether_ifattach() because
4762 	 * ether_ifattach() sets if_hdrlen to the default value.
4763 	 */
4764 	if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4765 		if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4766 
4767 	if ((err = iflib_netmap_attach(ctx))) {
4768 		device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4769 		goto fail_detach;
4770 	}
4771 	*ctxp = ctx;
4772 
4773 	NETDUMP_SET(ctx->ifc_ifp, iflib);
4774 
4775 	if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4776 	iflib_add_device_sysctl_post(ctx);
4777 	iflib_add_pfil(ctx);
4778 	ctx->ifc_flags |= IFC_INIT_DONE;
4779 	CTX_UNLOCK(ctx);
4780 
4781 	return (0);
4782 
4783 fail_detach:
4784 	ether_ifdetach(ctx->ifc_ifp);
4785 fail_intr_free:
4786 	iflib_free_intr_mem(ctx);
4787 fail_queues:
4788 	iflib_tx_structures_free(ctx);
4789 	iflib_rx_structures_free(ctx);
4790 	taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task);
4791 	IFDI_DETACH(ctx);
4792 fail_unlock:
4793 	CTX_UNLOCK(ctx);
4794 	iflib_deregister(ctx);
4795 fail_ctx_free:
4796 	device_set_softc(ctx->ifc_dev, NULL);
4797         if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4798                 free(ctx->ifc_softc, M_IFLIB);
4799         free(ctx, M_IFLIB);
4800 	return (err);
4801 }
4802 
4803 int
4804 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4805 					  struct iflib_cloneattach_ctx *clctx)
4806 {
4807 	int err;
4808 	if_ctx_t ctx;
4809 	if_t ifp;
4810 	if_softc_ctx_t scctx;
4811 	int i;
4812 	void *sc;
4813 	uint16_t main_txq;
4814 	uint16_t main_rxq;
4815 
4816 	ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4817 	sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4818 	ctx->ifc_flags |= IFC_SC_ALLOCATED;
4819 	if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4820 		ctx->ifc_flags |= IFC_PSEUDO;
4821 
4822 	ctx->ifc_sctx = sctx;
4823 	ctx->ifc_softc = sc;
4824 	ctx->ifc_dev = dev;
4825 
4826 	if ((err = iflib_register(ctx)) != 0) {
4827 		device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4828 		goto fail_ctx_free;
4829 	}
4830 	iflib_add_device_sysctl_pre(ctx);
4831 
4832 	scctx = &ctx->ifc_softc_ctx;
4833 	ifp = ctx->ifc_ifp;
4834 
4835 	iflib_reset_qvalues(ctx);
4836 	CTX_LOCK(ctx);
4837 	if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4838 		device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4839 		goto fail_unlock;
4840 	}
4841 	if (sctx->isc_flags & IFLIB_GEN_MAC)
4842 		ether_gen_addr(ifp, &ctx->ifc_mac);
4843 	if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4844 								clctx->cc_params)) != 0) {
4845 		device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4846 		goto fail_ctx_free;
4847 	}
4848 	ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4849 	ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4850 	ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4851 
4852 #ifdef INVARIANTS
4853 	if (scctx->isc_capabilities & IFCAP_TXCSUM)
4854 		MPASS(scctx->isc_tx_csum_flags);
4855 #endif
4856 
4857 	if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4858 	if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4859 
4860 	ifp->if_flags |= IFF_NOGROUP;
4861 	if (sctx->isc_flags & IFLIB_PSEUDO) {
4862 		ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4863 
4864 		if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4865 			device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4866 			goto fail_detach;
4867 		}
4868 		*ctxp = ctx;
4869 
4870 		/*
4871 		 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4872 		 * This must appear after the call to ether_ifattach() because
4873 		 * ether_ifattach() sets if_hdrlen to the default value.
4874 		 */
4875 		if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4876 			if_setifheaderlen(ifp,
4877 			    sizeof(struct ether_vlan_header));
4878 
4879 		if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4880 		iflib_add_device_sysctl_post(ctx);
4881 		ctx->ifc_flags |= IFC_INIT_DONE;
4882 		return (0);
4883 	}
4884 	_iflib_pre_assert(scctx);
4885 	ctx->ifc_txrx = *scctx->isc_txrx;
4886 
4887 	if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4888 		scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4889 	if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4890 		scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4891 
4892 	main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4893 	main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4894 
4895 	/* XXX change for per-queue sizes */
4896 	device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4897 	    scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4898 
4899 	if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4900 	    MAX_SINGLE_PACKET_FRACTION)
4901 		scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4902 		    MAX_SINGLE_PACKET_FRACTION);
4903 	if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4904 	    MAX_SINGLE_PACKET_FRACTION)
4905 		scctx->isc_tx_tso_segments_max = max(1,
4906 		    scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4907 
4908 	/* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4909 	if (if_getcapabilities(ifp) & IFCAP_TSO) {
4910 		/*
4911 		 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4912 		 * but some MACs do.
4913 		 */
4914 		if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4915 		    IP_MAXPACKET));
4916 		/*
4917 		 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4918 		 * into account.  In the worst case, each of these calls will
4919 		 * add another mbuf and, thus, the requirement for another DMA
4920 		 * segment.  So for best performance, it doesn't make sense to
4921 		 * advertize a maximum of TSO segments that typically will
4922 		 * require defragmentation in iflib_encap().
4923 		 */
4924 		if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4925 		if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4926 	}
4927 	if (scctx->isc_rss_table_size == 0)
4928 		scctx->isc_rss_table_size = 64;
4929 	scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4930 
4931 	GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4932 	/* XXX format name */
4933 	taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4934 	    NULL, NULL, "admin");
4935 
4936 	/* XXX --- can support > 1 -- but keep it simple for now */
4937 	scctx->isc_intr = IFLIB_INTR_LEGACY;
4938 
4939 	/* Get memory for the station queues */
4940 	if ((err = iflib_queues_alloc(ctx))) {
4941 		device_printf(dev, "Unable to allocate queue memory\n");
4942 		goto fail_iflib_detach;
4943 	}
4944 
4945 	if ((err = iflib_qset_structures_setup(ctx))) {
4946 		device_printf(dev, "qset structure setup failed %d\n", err);
4947 		goto fail_queues;
4948 	}
4949 
4950 	/*
4951 	 * XXX What if anything do we want to do about interrupts?
4952 	 */
4953 	ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4954 	if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4955 		device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4956 		goto fail_detach;
4957 	}
4958 
4959 	/*
4960 	 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4961 	 * This must appear after the call to ether_ifattach() because
4962 	 * ether_ifattach() sets if_hdrlen to the default value.
4963 	 */
4964 	if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4965 		if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4966 
4967 	/* XXX handle more than one queue */
4968 	for (i = 0; i < scctx->isc_nrxqsets; i++)
4969 		IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
4970 
4971 	*ctxp = ctx;
4972 
4973 	if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4974 	iflib_add_device_sysctl_post(ctx);
4975 	ctx->ifc_flags |= IFC_INIT_DONE;
4976 	CTX_UNLOCK(ctx);
4977 
4978 	return (0);
4979 fail_detach:
4980 	ether_ifdetach(ctx->ifc_ifp);
4981 fail_queues:
4982 	iflib_tx_structures_free(ctx);
4983 	iflib_rx_structures_free(ctx);
4984 fail_iflib_detach:
4985 	IFDI_DETACH(ctx);
4986 fail_unlock:
4987 	CTX_UNLOCK(ctx);
4988 	iflib_deregister(ctx);
4989 fail_ctx_free:
4990 	free(ctx->ifc_softc, M_IFLIB);
4991 	free(ctx, M_IFLIB);
4992 	return (err);
4993 }
4994 
4995 int
4996 iflib_pseudo_deregister(if_ctx_t ctx)
4997 {
4998 	if_t ifp = ctx->ifc_ifp;
4999 	iflib_txq_t txq;
5000 	iflib_rxq_t rxq;
5001 	int i, j;
5002 	struct taskqgroup *tqg;
5003 	iflib_fl_t fl;
5004 
5005 	ether_ifdetach(ifp);
5006 	/* XXX drain any dependent tasks */
5007 	tqg = qgroup_if_io_tqg;
5008 	for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5009 		callout_drain(&txq->ift_timer);
5010 		if (txq->ift_task.gt_uniq != NULL)
5011 			taskqgroup_detach(tqg, &txq->ift_task);
5012 	}
5013 	for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5014 		if (rxq->ifr_task.gt_uniq != NULL)
5015 			taskqgroup_detach(tqg, &rxq->ifr_task);
5016 
5017 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5018 			free(fl->ifl_rx_bitmap, M_IFLIB);
5019 	}
5020 	tqg = qgroup_if_config_tqg;
5021 	if (ctx->ifc_admin_task.gt_uniq != NULL)
5022 		taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5023 	if (ctx->ifc_vflr_task.gt_uniq != NULL)
5024 		taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5025 
5026 	iflib_tx_structures_free(ctx);
5027 	iflib_rx_structures_free(ctx);
5028 
5029 	iflib_deregister(ctx);
5030 
5031 	if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5032 		free(ctx->ifc_softc, M_IFLIB);
5033 	free(ctx, M_IFLIB);
5034 	return (0);
5035 }
5036 
5037 int
5038 iflib_device_attach(device_t dev)
5039 {
5040 	if_ctx_t ctx;
5041 	if_shared_ctx_t sctx;
5042 
5043 	if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5044 		return (ENOTSUP);
5045 
5046 	pci_enable_busmaster(dev);
5047 
5048 	return (iflib_device_register(dev, NULL, sctx, &ctx));
5049 }
5050 
5051 int
5052 iflib_device_deregister(if_ctx_t ctx)
5053 {
5054 	if_t ifp = ctx->ifc_ifp;
5055 	iflib_txq_t txq;
5056 	iflib_rxq_t rxq;
5057 	device_t dev = ctx->ifc_dev;
5058 	int i, j;
5059 	struct taskqgroup *tqg;
5060 	iflib_fl_t fl;
5061 
5062 	/* Make sure VLANS are not using driver */
5063 	if (if_vlantrunkinuse(ifp)) {
5064 		device_printf(dev, "Vlan in use, detach first\n");
5065 		return (EBUSY);
5066 	}
5067 #ifdef PCI_IOV
5068 	if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5069 		device_printf(dev, "SR-IOV in use; detach first.\n");
5070 		return (EBUSY);
5071 	}
5072 #endif
5073 
5074 	STATE_LOCK(ctx);
5075 	ctx->ifc_flags |= IFC_IN_DETACH;
5076 	STATE_UNLOCK(ctx);
5077 
5078 	CTX_LOCK(ctx);
5079 	iflib_stop(ctx);
5080 	CTX_UNLOCK(ctx);
5081 
5082 	/* Unregister VLAN events */
5083 	if (ctx->ifc_vlan_attach_event != NULL)
5084 		EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5085 	if (ctx->ifc_vlan_detach_event != NULL)
5086 		EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5087 
5088 	iflib_netmap_detach(ifp);
5089 	ether_ifdetach(ifp);
5090 	iflib_rem_pfil(ctx);
5091 	if (ctx->ifc_led_dev != NULL)
5092 		led_destroy(ctx->ifc_led_dev);
5093 	/* XXX drain any dependent tasks */
5094 	tqg = qgroup_if_io_tqg;
5095 	for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5096 		callout_drain(&txq->ift_timer);
5097 		if (txq->ift_task.gt_uniq != NULL)
5098 			taskqgroup_detach(tqg, &txq->ift_task);
5099 	}
5100 	for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5101 		if (rxq->ifr_task.gt_uniq != NULL)
5102 			taskqgroup_detach(tqg, &rxq->ifr_task);
5103 
5104 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5105 			free(fl->ifl_rx_bitmap, M_IFLIB);
5106 	}
5107 	tqg = qgroup_if_config_tqg;
5108 	if (ctx->ifc_admin_task.gt_uniq != NULL)
5109 		taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5110 	if (ctx->ifc_vflr_task.gt_uniq != NULL)
5111 		taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5112 	CTX_LOCK(ctx);
5113 	IFDI_DETACH(ctx);
5114 	CTX_UNLOCK(ctx);
5115 
5116 	/* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5117 	iflib_free_intr_mem(ctx);
5118 
5119 	bus_generic_detach(dev);
5120 
5121 	iflib_tx_structures_free(ctx);
5122 	iflib_rx_structures_free(ctx);
5123 
5124 	iflib_deregister(ctx);
5125 
5126 	device_set_softc(ctx->ifc_dev, NULL);
5127 	if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5128 		free(ctx->ifc_softc, M_IFLIB);
5129 	unref_ctx_core_offset(ctx);
5130 	free(ctx, M_IFLIB);
5131 	return (0);
5132 }
5133 
5134 static void
5135 iflib_free_intr_mem(if_ctx_t ctx)
5136 {
5137 
5138 	if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5139 		iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5140 	}
5141 	if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5142 		pci_release_msi(ctx->ifc_dev);
5143 	}
5144 	if (ctx->ifc_msix_mem != NULL) {
5145 		bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5146 		    rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5147 		ctx->ifc_msix_mem = NULL;
5148 	}
5149 }
5150 
5151 int
5152 iflib_device_detach(device_t dev)
5153 {
5154 	if_ctx_t ctx = device_get_softc(dev);
5155 
5156 	return (iflib_device_deregister(ctx));
5157 }
5158 
5159 int
5160 iflib_device_suspend(device_t dev)
5161 {
5162 	if_ctx_t ctx = device_get_softc(dev);
5163 
5164 	CTX_LOCK(ctx);
5165 	IFDI_SUSPEND(ctx);
5166 	CTX_UNLOCK(ctx);
5167 
5168 	return bus_generic_suspend(dev);
5169 }
5170 int
5171 iflib_device_shutdown(device_t dev)
5172 {
5173 	if_ctx_t ctx = device_get_softc(dev);
5174 
5175 	CTX_LOCK(ctx);
5176 	IFDI_SHUTDOWN(ctx);
5177 	CTX_UNLOCK(ctx);
5178 
5179 	return bus_generic_suspend(dev);
5180 }
5181 
5182 
5183 int
5184 iflib_device_resume(device_t dev)
5185 {
5186 	if_ctx_t ctx = device_get_softc(dev);
5187 	iflib_txq_t txq = ctx->ifc_txqs;
5188 
5189 	CTX_LOCK(ctx);
5190 	IFDI_RESUME(ctx);
5191 	iflib_if_init_locked(ctx);
5192 	CTX_UNLOCK(ctx);
5193 	for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5194 		iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5195 
5196 	return (bus_generic_resume(dev));
5197 }
5198 
5199 int
5200 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5201 {
5202 	int error;
5203 	if_ctx_t ctx = device_get_softc(dev);
5204 
5205 	CTX_LOCK(ctx);
5206 	error = IFDI_IOV_INIT(ctx, num_vfs, params);
5207 	CTX_UNLOCK(ctx);
5208 
5209 	return (error);
5210 }
5211 
5212 void
5213 iflib_device_iov_uninit(device_t dev)
5214 {
5215 	if_ctx_t ctx = device_get_softc(dev);
5216 
5217 	CTX_LOCK(ctx);
5218 	IFDI_IOV_UNINIT(ctx);
5219 	CTX_UNLOCK(ctx);
5220 }
5221 
5222 int
5223 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5224 {
5225 	int error;
5226 	if_ctx_t ctx = device_get_softc(dev);
5227 
5228 	CTX_LOCK(ctx);
5229 	error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5230 	CTX_UNLOCK(ctx);
5231 
5232 	return (error);
5233 }
5234 
5235 /*********************************************************************
5236  *
5237  *  MODULE FUNCTION DEFINITIONS
5238  *
5239  **********************************************************************/
5240 
5241 /*
5242  * - Start a fast taskqueue thread for each core
5243  * - Start a taskqueue for control operations
5244  */
5245 static int
5246 iflib_module_init(void)
5247 {
5248 	return (0);
5249 }
5250 
5251 static int
5252 iflib_module_event_handler(module_t mod, int what, void *arg)
5253 {
5254 	int err;
5255 
5256 	switch (what) {
5257 	case MOD_LOAD:
5258 		if ((err = iflib_module_init()) != 0)
5259 			return (err);
5260 		break;
5261 	case MOD_UNLOAD:
5262 		return (EBUSY);
5263 	default:
5264 		return (EOPNOTSUPP);
5265 	}
5266 
5267 	return (0);
5268 }
5269 
5270 /*********************************************************************
5271  *
5272  *  PUBLIC FUNCTION DEFINITIONS
5273  *     ordered as in iflib.h
5274  *
5275  **********************************************************************/
5276 
5277 
5278 static void
5279 _iflib_assert(if_shared_ctx_t sctx)
5280 {
5281 	int i;
5282 
5283 	MPASS(sctx->isc_tx_maxsize);
5284 	MPASS(sctx->isc_tx_maxsegsize);
5285 
5286 	MPASS(sctx->isc_rx_maxsize);
5287 	MPASS(sctx->isc_rx_nsegments);
5288 	MPASS(sctx->isc_rx_maxsegsize);
5289 
5290 	MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5291 	for (i = 0; i < sctx->isc_nrxqs; i++) {
5292 		MPASS(sctx->isc_nrxd_min[i]);
5293 		MPASS(powerof2(sctx->isc_nrxd_min[i]));
5294 		MPASS(sctx->isc_nrxd_max[i]);
5295 		MPASS(powerof2(sctx->isc_nrxd_max[i]));
5296 		MPASS(sctx->isc_nrxd_default[i]);
5297 		MPASS(powerof2(sctx->isc_nrxd_default[i]));
5298 	}
5299 
5300 	MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5301 	for (i = 0; i < sctx->isc_ntxqs; i++) {
5302 		MPASS(sctx->isc_ntxd_min[i]);
5303 		MPASS(powerof2(sctx->isc_ntxd_min[i]));
5304 		MPASS(sctx->isc_ntxd_max[i]);
5305 		MPASS(powerof2(sctx->isc_ntxd_max[i]));
5306 		MPASS(sctx->isc_ntxd_default[i]);
5307 		MPASS(powerof2(sctx->isc_ntxd_default[i]));
5308 	}
5309 }
5310 
5311 static void
5312 _iflib_pre_assert(if_softc_ctx_t scctx)
5313 {
5314 
5315 	MPASS(scctx->isc_txrx->ift_txd_encap);
5316 	MPASS(scctx->isc_txrx->ift_txd_flush);
5317 	MPASS(scctx->isc_txrx->ift_txd_credits_update);
5318 	MPASS(scctx->isc_txrx->ift_rxd_available);
5319 	MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5320 	MPASS(scctx->isc_txrx->ift_rxd_refill);
5321 	MPASS(scctx->isc_txrx->ift_rxd_flush);
5322 }
5323 
5324 static int
5325 iflib_register(if_ctx_t ctx)
5326 {
5327 	if_shared_ctx_t sctx = ctx->ifc_sctx;
5328 	driver_t *driver = sctx->isc_driver;
5329 	device_t dev = ctx->ifc_dev;
5330 	if_t ifp;
5331 
5332 	_iflib_assert(sctx);
5333 
5334 	CTX_LOCK_INIT(ctx);
5335 	STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5336 	ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER);
5337 	if (ifp == NULL) {
5338 		device_printf(dev, "can not allocate ifnet structure\n");
5339 		return (ENOMEM);
5340 	}
5341 
5342 	/*
5343 	 * Initialize our context's device specific methods
5344 	 */
5345 	kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5346 	kobj_class_compile((kobj_class_t) driver);
5347 
5348 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5349 	if_setsoftc(ifp, ctx);
5350 	if_setdev(ifp, dev);
5351 	if_setinitfn(ifp, iflib_if_init);
5352 	if_setioctlfn(ifp, iflib_if_ioctl);
5353 #ifdef ALTQ
5354 	if_setstartfn(ifp, iflib_altq_if_start);
5355 	if_settransmitfn(ifp, iflib_altq_if_transmit);
5356 	if_setsendqready(ifp);
5357 #else
5358 	if_settransmitfn(ifp, iflib_if_transmit);
5359 #endif
5360 	if_setqflushfn(ifp, iflib_if_qflush);
5361 	if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
5362 
5363 	ctx->ifc_vlan_attach_event =
5364 		EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5365 							  EVENTHANDLER_PRI_FIRST);
5366 	ctx->ifc_vlan_detach_event =
5367 		EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5368 							  EVENTHANDLER_PRI_FIRST);
5369 
5370 	if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
5371 		ctx->ifc_mediap = &ctx->ifc_media;
5372 		ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
5373 		    iflib_media_change, iflib_media_status);
5374 	}
5375 	return (0);
5376 }
5377 
5378 static void
5379 iflib_deregister(if_ctx_t ctx)
5380 {
5381 	if_t ifp = ctx->ifc_ifp;
5382 
5383 	/* Remove all media */
5384 	ifmedia_removeall(&ctx->ifc_media);
5385 
5386 	/* Unregister VLAN events */
5387 	if (ctx->ifc_vlan_attach_event != NULL) {
5388 		EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5389 		ctx->ifc_vlan_attach_event = NULL;
5390 	}
5391 	if (ctx->ifc_vlan_detach_event != NULL) {
5392 		EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5393 		ctx->ifc_vlan_detach_event = NULL;
5394 	}
5395 
5396 	/* Release kobject reference */
5397 	kobj_delete((kobj_t) ctx, NULL);
5398 
5399 	/* Free the ifnet structure */
5400 	if_free(ifp);
5401 
5402 	STATE_LOCK_DESTROY(ctx);
5403 
5404 	/* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5405 	CTX_LOCK_DESTROY(ctx);
5406 }
5407 
5408 static int
5409 iflib_queues_alloc(if_ctx_t ctx)
5410 {
5411 	if_shared_ctx_t sctx = ctx->ifc_sctx;
5412 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5413 	device_t dev = ctx->ifc_dev;
5414 	int nrxqsets = scctx->isc_nrxqsets;
5415 	int ntxqsets = scctx->isc_ntxqsets;
5416 	iflib_txq_t txq;
5417 	iflib_rxq_t rxq;
5418 	iflib_fl_t fl = NULL;
5419 	int i, j, cpu, err, txconf, rxconf;
5420 	iflib_dma_info_t ifdip;
5421 	uint32_t *rxqsizes = scctx->isc_rxqsizes;
5422 	uint32_t *txqsizes = scctx->isc_txqsizes;
5423 	uint8_t nrxqs = sctx->isc_nrxqs;
5424 	uint8_t ntxqs = sctx->isc_ntxqs;
5425 	int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5426 	caddr_t *vaddrs;
5427 	uint64_t *paddrs;
5428 
5429 	KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5430 	KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5431 
5432 	/* Allocate the TX ring struct memory */
5433 	if (!(ctx->ifc_txqs =
5434 	    (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5435 	    ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5436 		device_printf(dev, "Unable to allocate TX ring memory\n");
5437 		err = ENOMEM;
5438 		goto fail;
5439 	}
5440 
5441 	/* Now allocate the RX */
5442 	if (!(ctx->ifc_rxqs =
5443 	    (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5444 	    nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5445 		device_printf(dev, "Unable to allocate RX ring memory\n");
5446 		err = ENOMEM;
5447 		goto rx_fail;
5448 	}
5449 
5450 	txq = ctx->ifc_txqs;
5451 	rxq = ctx->ifc_rxqs;
5452 
5453 	/*
5454 	 * XXX handle allocation failure
5455 	 */
5456 	for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5457 		/* Set up some basics */
5458 
5459 		if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5460 		    M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5461 			device_printf(dev,
5462 			    "Unable to allocate TX DMA info memory\n");
5463 			err = ENOMEM;
5464 			goto err_tx_desc;
5465 		}
5466 		txq->ift_ifdi = ifdip;
5467 		for (j = 0; j < ntxqs; j++, ifdip++) {
5468 			if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5469 				device_printf(dev,
5470 				    "Unable to allocate TX descriptors\n");
5471 				err = ENOMEM;
5472 				goto err_tx_desc;
5473 			}
5474 			txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5475 			bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5476 		}
5477 		txq->ift_ctx = ctx;
5478 		txq->ift_id = i;
5479 		if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5480 			txq->ift_br_offset = 1;
5481 		} else {
5482 			txq->ift_br_offset = 0;
5483 		}
5484 		/* XXX fix this */
5485 		txq->ift_timer.c_cpu = cpu;
5486 
5487 		if (iflib_txsd_alloc(txq)) {
5488 			device_printf(dev, "Critical Failure setting up TX buffers\n");
5489 			err = ENOMEM;
5490 			goto err_tx_desc;
5491 		}
5492 
5493 		/* Initialize the TX lock */
5494 		snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
5495 		    device_get_nameunit(dev), txq->ift_id);
5496 		mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5497 		callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5498 
5499 		err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5500 				      iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5501 		if (err) {
5502 			/* XXX free any allocated rings */
5503 			device_printf(dev, "Unable to allocate buf_ring\n");
5504 			goto err_tx_desc;
5505 		}
5506 	}
5507 
5508 	for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5509 		/* Set up some basics */
5510 
5511 		if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5512 		   M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5513 			device_printf(dev,
5514 			    "Unable to allocate RX DMA info memory\n");
5515 			err = ENOMEM;
5516 			goto err_tx_desc;
5517 		}
5518 
5519 		rxq->ifr_ifdi = ifdip;
5520 		/* XXX this needs to be changed if #rx queues != #tx queues */
5521 		rxq->ifr_ntxqirq = 1;
5522 		rxq->ifr_txqid[0] = i;
5523 		for (j = 0; j < nrxqs; j++, ifdip++) {
5524 			if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5525 				device_printf(dev,
5526 				    "Unable to allocate RX descriptors\n");
5527 				err = ENOMEM;
5528 				goto err_tx_desc;
5529 			}
5530 			bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5531 		}
5532 		rxq->ifr_ctx = ctx;
5533 		rxq->ifr_id = i;
5534 		if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5535 			rxq->ifr_fl_offset = 1;
5536 		} else {
5537 			rxq->ifr_fl_offset = 0;
5538 		}
5539 		rxq->ifr_nfl = nfree_lists;
5540 		if (!(fl =
5541 			  (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5542 			device_printf(dev, "Unable to allocate free list memory\n");
5543 			err = ENOMEM;
5544 			goto err_tx_desc;
5545 		}
5546 		rxq->ifr_fl = fl;
5547 		for (j = 0; j < nfree_lists; j++) {
5548 			fl[j].ifl_rxq = rxq;
5549 			fl[j].ifl_id = j;
5550 			fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5551 			fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5552 		}
5553 		/* Allocate receive buffers for the ring */
5554 		if (iflib_rxsd_alloc(rxq)) {
5555 			device_printf(dev,
5556 			    "Critical Failure setting up receive buffers\n");
5557 			err = ENOMEM;
5558 			goto err_rx_desc;
5559 		}
5560 
5561 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5562 			fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5563 			    M_WAITOK);
5564 	}
5565 
5566 	/* TXQs */
5567 	vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5568 	paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5569 	for (i = 0; i < ntxqsets; i++) {
5570 		iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5571 
5572 		for (j = 0; j < ntxqs; j++, di++) {
5573 			vaddrs[i*ntxqs + j] = di->idi_vaddr;
5574 			paddrs[i*ntxqs + j] = di->idi_paddr;
5575 		}
5576 	}
5577 	if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5578 		device_printf(ctx->ifc_dev,
5579 		    "Unable to allocate device TX queue\n");
5580 		iflib_tx_structures_free(ctx);
5581 		free(vaddrs, M_IFLIB);
5582 		free(paddrs, M_IFLIB);
5583 		goto err_rx_desc;
5584 	}
5585 	free(vaddrs, M_IFLIB);
5586 	free(paddrs, M_IFLIB);
5587 
5588 	/* RXQs */
5589 	vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5590 	paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5591 	for (i = 0; i < nrxqsets; i++) {
5592 		iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5593 
5594 		for (j = 0; j < nrxqs; j++, di++) {
5595 			vaddrs[i*nrxqs + j] = di->idi_vaddr;
5596 			paddrs[i*nrxqs + j] = di->idi_paddr;
5597 		}
5598 	}
5599 	if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5600 		device_printf(ctx->ifc_dev,
5601 		    "Unable to allocate device RX queue\n");
5602 		iflib_tx_structures_free(ctx);
5603 		free(vaddrs, M_IFLIB);
5604 		free(paddrs, M_IFLIB);
5605 		goto err_rx_desc;
5606 	}
5607 	free(vaddrs, M_IFLIB);
5608 	free(paddrs, M_IFLIB);
5609 
5610 	return (0);
5611 
5612 /* XXX handle allocation failure changes */
5613 err_rx_desc:
5614 err_tx_desc:
5615 rx_fail:
5616 	if (ctx->ifc_rxqs != NULL)
5617 		free(ctx->ifc_rxqs, M_IFLIB);
5618 	ctx->ifc_rxqs = NULL;
5619 	if (ctx->ifc_txqs != NULL)
5620 		free(ctx->ifc_txqs, M_IFLIB);
5621 	ctx->ifc_txqs = NULL;
5622 fail:
5623 	return (err);
5624 }
5625 
5626 static int
5627 iflib_tx_structures_setup(if_ctx_t ctx)
5628 {
5629 	iflib_txq_t txq = ctx->ifc_txqs;
5630 	int i;
5631 
5632 	for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5633 		iflib_txq_setup(txq);
5634 
5635 	return (0);
5636 }
5637 
5638 static void
5639 iflib_tx_structures_free(if_ctx_t ctx)
5640 {
5641 	iflib_txq_t txq = ctx->ifc_txqs;
5642 	if_shared_ctx_t sctx = ctx->ifc_sctx;
5643 	int i, j;
5644 
5645 	for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5646 		iflib_txq_destroy(txq);
5647 		for (j = 0; j < sctx->isc_ntxqs; j++)
5648 			iflib_dma_free(&txq->ift_ifdi[j]);
5649 	}
5650 	free(ctx->ifc_txqs, M_IFLIB);
5651 	ctx->ifc_txqs = NULL;
5652 	IFDI_QUEUES_FREE(ctx);
5653 }
5654 
5655 /*********************************************************************
5656  *
5657  *  Initialize all receive rings.
5658  *
5659  **********************************************************************/
5660 static int
5661 iflib_rx_structures_setup(if_ctx_t ctx)
5662 {
5663 	iflib_rxq_t rxq = ctx->ifc_rxqs;
5664 	int q;
5665 #if defined(INET6) || defined(INET)
5666 	int err, i;
5667 #endif
5668 
5669 	for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5670 #if defined(INET6) || defined(INET)
5671 		if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) {
5672 			err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5673 			    TCP_LRO_ENTRIES, min(1024,
5674 			    ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
5675 			if (err != 0) {
5676 				device_printf(ctx->ifc_dev,
5677 				    "LRO Initialization failed!\n");
5678 				goto fail;
5679 			}
5680 		}
5681 #endif
5682 		IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5683 	}
5684 	return (0);
5685 #if defined(INET6) || defined(INET)
5686 fail:
5687 	/*
5688 	 * Free LRO resources allocated so far, we will only handle
5689 	 * the rings that completed, the failing case will have
5690 	 * cleaned up for itself.  'q' failed, so its the terminus.
5691 	 */
5692 	rxq = ctx->ifc_rxqs;
5693 	for (i = 0; i < q; ++i, rxq++) {
5694 		if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5695 			tcp_lro_free(&rxq->ifr_lc);
5696 	}
5697 	return (err);
5698 #endif
5699 }
5700 
5701 /*********************************************************************
5702  *
5703  *  Free all receive rings.
5704  *
5705  **********************************************************************/
5706 static void
5707 iflib_rx_structures_free(if_ctx_t ctx)
5708 {
5709 	iflib_rxq_t rxq = ctx->ifc_rxqs;
5710 	int i;
5711 
5712 	for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5713 		iflib_rx_sds_free(rxq);
5714 #if defined(INET6) || defined(INET)
5715 		if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5716 			tcp_lro_free(&rxq->ifr_lc);
5717 #endif
5718 	}
5719 	free(ctx->ifc_rxqs, M_IFLIB);
5720 	ctx->ifc_rxqs = NULL;
5721 }
5722 
5723 static int
5724 iflib_qset_structures_setup(if_ctx_t ctx)
5725 {
5726 	int err;
5727 
5728 	/*
5729 	 * It is expected that the caller takes care of freeing queues if this
5730 	 * fails.
5731 	 */
5732 	if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5733 		device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5734 		return (err);
5735 	}
5736 
5737 	if ((err = iflib_rx_structures_setup(ctx)) != 0)
5738 		device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5739 
5740 	return (err);
5741 }
5742 
5743 int
5744 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5745 		driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5746 {
5747 
5748 	return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5749 }
5750 
5751 #ifdef SMP
5752 static int
5753 find_nth(if_ctx_t ctx, int qid)
5754 {
5755 	cpuset_t cpus;
5756 	int i, cpuid, eqid, count;
5757 
5758 	CPU_COPY(&ctx->ifc_cpus, &cpus);
5759 	count = CPU_COUNT(&cpus);
5760 	eqid = qid % count;
5761 	/* clear up to the qid'th bit */
5762 	for (i = 0; i < eqid; i++) {
5763 		cpuid = CPU_FFS(&cpus);
5764 		MPASS(cpuid != 0);
5765 		CPU_CLR(cpuid-1, &cpus);
5766 	}
5767 	cpuid = CPU_FFS(&cpus);
5768 	MPASS(cpuid != 0);
5769 	return (cpuid-1);
5770 }
5771 
5772 #ifdef SCHED_ULE
5773 extern struct cpu_group *cpu_top;              /* CPU topology */
5774 
5775 static int
5776 find_child_with_core(int cpu, struct cpu_group *grp)
5777 {
5778 	int i;
5779 
5780 	if (grp->cg_children == 0)
5781 		return -1;
5782 
5783 	MPASS(grp->cg_child);
5784 	for (i = 0; i < grp->cg_children; i++) {
5785 		if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5786 			return i;
5787 	}
5788 
5789 	return -1;
5790 }
5791 
5792 /*
5793  * Find the nth "close" core to the specified core
5794  * "close" is defined as the deepest level that shares
5795  * at least an L2 cache.  With threads, this will be
5796  * threads on the same core.  If the shared cache is L3
5797  * or higher, simply returns the same core.
5798  */
5799 static int
5800 find_close_core(int cpu, int core_offset)
5801 {
5802 	struct cpu_group *grp;
5803 	int i;
5804 	int fcpu;
5805 	cpuset_t cs;
5806 
5807 	grp = cpu_top;
5808 	if (grp == NULL)
5809 		return cpu;
5810 	i = 0;
5811 	while ((i = find_child_with_core(cpu, grp)) != -1) {
5812 		/* If the child only has one cpu, don't descend */
5813 		if (grp->cg_child[i].cg_count <= 1)
5814 			break;
5815 		grp = &grp->cg_child[i];
5816 	}
5817 
5818 	/* If they don't share at least an L2 cache, use the same CPU */
5819 	if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5820 		return cpu;
5821 
5822 	/* Now pick one */
5823 	CPU_COPY(&grp->cg_mask, &cs);
5824 
5825 	/* Add the selected CPU offset to core offset. */
5826 	for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5827 		if (fcpu - 1 == cpu)
5828 			break;
5829 		CPU_CLR(fcpu - 1, &cs);
5830 	}
5831 	MPASS(fcpu);
5832 
5833 	core_offset += i;
5834 
5835 	CPU_COPY(&grp->cg_mask, &cs);
5836 	for (i = core_offset % grp->cg_count; i > 0; i--) {
5837 		MPASS(CPU_FFS(&cs));
5838 		CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5839 	}
5840 	MPASS(CPU_FFS(&cs));
5841 	return CPU_FFS(&cs) - 1;
5842 }
5843 #else
5844 static int
5845 find_close_core(int cpu, int core_offset __unused)
5846 {
5847 	return cpu;
5848 }
5849 #endif
5850 
5851 static int
5852 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5853 {
5854 	switch (type) {
5855 	case IFLIB_INTR_TX:
5856 		/* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5857 		/* XXX handle multiple RX threads per core and more than two core per L2 group */
5858 		return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5859 	case IFLIB_INTR_RX:
5860 	case IFLIB_INTR_RXTX:
5861 		/* RX queues get the specified core */
5862 		return qid / CPU_COUNT(&ctx->ifc_cpus);
5863 	default:
5864 		return -1;
5865 	}
5866 }
5867 #else
5868 #define get_core_offset(ctx, type, qid)	CPU_FIRST()
5869 #define find_close_core(cpuid, tid)	CPU_FIRST()
5870 #define find_nth(ctx, gid)		CPU_FIRST()
5871 #endif
5872 
5873 /* Just to avoid copy/paste */
5874 static inline int
5875 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
5876     int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
5877     const char *name)
5878 {
5879 	device_t dev;
5880 	int co, cpuid, err, tid;
5881 
5882 	dev = ctx->ifc_dev;
5883 	co = ctx->ifc_sysctl_core_offset;
5884 	if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX)
5885 		co += ctx->ifc_softc_ctx.isc_nrxqsets;
5886 	cpuid = find_nth(ctx, qid + co);
5887 	tid = get_core_offset(ctx, type, qid);
5888 	if (tid < 0) {
5889 		device_printf(dev, "get_core_offset failed\n");
5890 		return (EOPNOTSUPP);
5891 	}
5892 	cpuid = find_close_core(cpuid, tid);
5893 	err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res,
5894 	    name);
5895 	if (err) {
5896 		device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
5897 		return (err);
5898 	}
5899 #ifdef notyet
5900 	if (cpuid > ctx->ifc_cpuid_highest)
5901 		ctx->ifc_cpuid_highest = cpuid;
5902 #endif
5903 	return (0);
5904 }
5905 
5906 int
5907 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5908 			iflib_intr_type_t type, driver_filter_t *filter,
5909 			void *filter_arg, int qid, const char *name)
5910 {
5911 	device_t dev;
5912 	struct grouptask *gtask;
5913 	struct taskqgroup *tqg;
5914 	iflib_filter_info_t info;
5915 	gtask_fn_t *fn;
5916 	int tqrid, err;
5917 	driver_filter_t *intr_fast;
5918 	void *q;
5919 
5920 	info = &ctx->ifc_filter_info;
5921 	tqrid = rid;
5922 
5923 	switch (type) {
5924 	/* XXX merge tx/rx for netmap? */
5925 	case IFLIB_INTR_TX:
5926 		q = &ctx->ifc_txqs[qid];
5927 		info = &ctx->ifc_txqs[qid].ift_filter_info;
5928 		gtask = &ctx->ifc_txqs[qid].ift_task;
5929 		tqg = qgroup_if_io_tqg;
5930 		fn = _task_fn_tx;
5931 		intr_fast = iflib_fast_intr;
5932 		GROUPTASK_INIT(gtask, 0, fn, q);
5933 		ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
5934 		break;
5935 	case IFLIB_INTR_RX:
5936 		q = &ctx->ifc_rxqs[qid];
5937 		info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5938 		gtask = &ctx->ifc_rxqs[qid].ifr_task;
5939 		tqg = qgroup_if_io_tqg;
5940 		fn = _task_fn_rx;
5941 		intr_fast = iflib_fast_intr;
5942 		GROUPTASK_INIT(gtask, 0, fn, q);
5943 		break;
5944 	case IFLIB_INTR_RXTX:
5945 		q = &ctx->ifc_rxqs[qid];
5946 		info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5947 		gtask = &ctx->ifc_rxqs[qid].ifr_task;
5948 		tqg = qgroup_if_io_tqg;
5949 		fn = _task_fn_rx;
5950 		intr_fast = iflib_fast_intr_rxtx;
5951 		GROUPTASK_INIT(gtask, 0, fn, q);
5952 		break;
5953 	case IFLIB_INTR_ADMIN:
5954 		q = ctx;
5955 		tqrid = -1;
5956 		info = &ctx->ifc_filter_info;
5957 		gtask = &ctx->ifc_admin_task;
5958 		tqg = qgroup_if_config_tqg;
5959 		fn = _task_fn_admin;
5960 		intr_fast = iflib_fast_intr_ctx;
5961 		break;
5962 	default:
5963 		device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
5964 		    __func__);
5965 		return (EINVAL);
5966 	}
5967 
5968 	info->ifi_filter = filter;
5969 	info->ifi_filter_arg = filter_arg;
5970 	info->ifi_task = gtask;
5971 	info->ifi_ctx = q;
5972 
5973 	dev = ctx->ifc_dev;
5974 	err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info,  name);
5975 	if (err != 0) {
5976 		device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
5977 		return (err);
5978 	}
5979 	if (type == IFLIB_INTR_ADMIN)
5980 		return (0);
5981 
5982 	if (tqrid != -1) {
5983 		err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
5984 		    q, name);
5985 		if (err)
5986 			return (err);
5987 	} else {
5988 		taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
5989 	}
5990 
5991 	return (0);
5992 }
5993 
5994 void
5995 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
5996 {
5997 	struct grouptask *gtask;
5998 	struct taskqgroup *tqg;
5999 	gtask_fn_t *fn;
6000 	void *q;
6001 	int err;
6002 
6003 	switch (type) {
6004 	case IFLIB_INTR_TX:
6005 		q = &ctx->ifc_txqs[qid];
6006 		gtask = &ctx->ifc_txqs[qid].ift_task;
6007 		tqg = qgroup_if_io_tqg;
6008 		fn = _task_fn_tx;
6009 		break;
6010 	case IFLIB_INTR_RX:
6011 		q = &ctx->ifc_rxqs[qid];
6012 		gtask = &ctx->ifc_rxqs[qid].ifr_task;
6013 		tqg = qgroup_if_io_tqg;
6014 		fn = _task_fn_rx;
6015 		break;
6016 	case IFLIB_INTR_IOV:
6017 		q = ctx;
6018 		gtask = &ctx->ifc_vflr_task;
6019 		tqg = qgroup_if_config_tqg;
6020 		fn = _task_fn_iov;
6021 		break;
6022 	default:
6023 		panic("unknown net intr type");
6024 	}
6025 	GROUPTASK_INIT(gtask, 0, fn, q);
6026 	if (irq != NULL) {
6027 		err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6028 		    q, name);
6029 		if (err)
6030 			taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev,
6031 			    irq->ii_res, name);
6032 	} else {
6033 		taskqgroup_attach(tqg, gtask, q, NULL, NULL, name);
6034 	}
6035 }
6036 
6037 void
6038 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6039 {
6040 
6041 	if (irq->ii_tag)
6042 		bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6043 
6044 	if (irq->ii_res)
6045 		bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6046 		    rman_get_rid(irq->ii_res), irq->ii_res);
6047 }
6048 
6049 static int
6050 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6051 {
6052 	iflib_txq_t txq = ctx->ifc_txqs;
6053 	iflib_rxq_t rxq = ctx->ifc_rxqs;
6054 	if_irq_t irq = &ctx->ifc_legacy_irq;
6055 	iflib_filter_info_t info;
6056 	device_t dev;
6057 	struct grouptask *gtask;
6058 	struct resource *res;
6059 	struct taskqgroup *tqg;
6060 	gtask_fn_t *fn;
6061 	void *q;
6062 	int err, tqrid;
6063 
6064 	q = &ctx->ifc_rxqs[0];
6065 	info = &rxq[0].ifr_filter_info;
6066 	gtask = &rxq[0].ifr_task;
6067 	tqg = qgroup_if_io_tqg;
6068 	tqrid = *rid;
6069 	fn = _task_fn_rx;
6070 
6071 	ctx->ifc_flags |= IFC_LEGACY;
6072 	info->ifi_filter = filter;
6073 	info->ifi_filter_arg = filter_arg;
6074 	info->ifi_task = gtask;
6075 	info->ifi_ctx = q;
6076 
6077 	dev = ctx->ifc_dev;
6078 	/* We allocate a single interrupt resource */
6079 	if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_rxtx,
6080 	    NULL, info, name)) != 0)
6081 		return (err);
6082 	GROUPTASK_INIT(gtask, 0, fn, q);
6083 	res = irq->ii_res;
6084 	taskqgroup_attach(tqg, gtask, q, dev, res, name);
6085 
6086 	GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6087 	taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6088 	    "tx");
6089 	return (0);
6090 }
6091 
6092 void
6093 iflib_led_create(if_ctx_t ctx)
6094 {
6095 
6096 	ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6097 	    device_get_nameunit(ctx->ifc_dev));
6098 }
6099 
6100 void
6101 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6102 {
6103 
6104 	GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6105 }
6106 
6107 void
6108 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6109 {
6110 
6111 	GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6112 }
6113 
6114 void
6115 iflib_admin_intr_deferred(if_ctx_t ctx)
6116 {
6117 #ifdef INVARIANTS
6118 	struct grouptask *gtask;
6119 
6120 	gtask = &ctx->ifc_admin_task;
6121 	MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
6122 #endif
6123 
6124 	GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
6125 }
6126 
6127 void
6128 iflib_iov_intr_deferred(if_ctx_t ctx)
6129 {
6130 
6131 	GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6132 }
6133 
6134 void
6135 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name)
6136 {
6137 
6138 	taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6139 	    name);
6140 }
6141 
6142 void
6143 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6144 	const char *name)
6145 {
6146 
6147 	GROUPTASK_INIT(gtask, 0, fn, ctx);
6148 	taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
6149 	    name);
6150 }
6151 
6152 void
6153 iflib_config_gtask_deinit(struct grouptask *gtask)
6154 {
6155 
6156 	taskqgroup_detach(qgroup_if_config_tqg, gtask);
6157 }
6158 
6159 void
6160 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6161 {
6162 	if_t ifp = ctx->ifc_ifp;
6163 	iflib_txq_t txq = ctx->ifc_txqs;
6164 
6165 	if_setbaudrate(ifp, baudrate);
6166 	if (baudrate >= IF_Gbps(10)) {
6167 		STATE_LOCK(ctx);
6168 		ctx->ifc_flags |= IFC_PREFETCH;
6169 		STATE_UNLOCK(ctx);
6170 	}
6171 	/* If link down, disable watchdog */
6172 	if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6173 		for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6174 			txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6175 	}
6176 	ctx->ifc_link_state = link_state;
6177 	if_link_state_change(ifp, link_state);
6178 }
6179 
6180 static int
6181 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6182 {
6183 	int credits;
6184 #ifdef INVARIANTS
6185 	int credits_pre = txq->ift_cidx_processed;
6186 #endif
6187 
6188 	bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6189 	    BUS_DMASYNC_POSTREAD);
6190 	if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6191 		return (0);
6192 
6193 	txq->ift_processed += credits;
6194 	txq->ift_cidx_processed += credits;
6195 
6196 	MPASS(credits_pre + credits == txq->ift_cidx_processed);
6197 	if (txq->ift_cidx_processed >= txq->ift_size)
6198 		txq->ift_cidx_processed -= txq->ift_size;
6199 	return (credits);
6200 }
6201 
6202 static int
6203 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6204 {
6205 	iflib_fl_t fl;
6206 	u_int i;
6207 
6208 	for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6209 		bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6210 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6211 	return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6212 	    budget));
6213 }
6214 
6215 void
6216 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6217 	const char *description, if_int_delay_info_t info,
6218 	int offset, int value)
6219 {
6220 	info->iidi_ctx = ctx;
6221 	info->iidi_offset = offset;
6222 	info->iidi_value = value;
6223 	SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6224 	    SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6225 	    OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
6226 	    info, 0, iflib_sysctl_int_delay, "I", description);
6227 }
6228 
6229 struct sx *
6230 iflib_ctx_lock_get(if_ctx_t ctx)
6231 {
6232 
6233 	return (&ctx->ifc_ctx_sx);
6234 }
6235 
6236 static int
6237 iflib_msix_init(if_ctx_t ctx)
6238 {
6239 	device_t dev = ctx->ifc_dev;
6240 	if_shared_ctx_t sctx = ctx->ifc_sctx;
6241 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6242 	int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6243 	int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6244 
6245 	iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6246 	iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6247 
6248 	if (bootverbose)
6249 		device_printf(dev, "msix_init qsets capped at %d\n",
6250 		    imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6251 
6252 	/* Override by tuneable */
6253 	if (scctx->isc_disable_msix)
6254 		goto msi;
6255 
6256 	/* First try MSI-X */
6257 	if ((msgs = pci_msix_count(dev)) == 0) {
6258 		if (bootverbose)
6259 			device_printf(dev, "MSI-X not supported or disabled\n");
6260 		goto msi;
6261 	}
6262 
6263 	bar = ctx->ifc_softc_ctx.isc_msix_bar;
6264 	/*
6265 	 * bar == -1 => "trust me I know what I'm doing"
6266 	 * Some drivers are for hardware that is so shoddily
6267 	 * documented that no one knows which bars are which
6268 	 * so the developer has to map all bars. This hack
6269 	 * allows shoddy garbage to use MSI-X in this framework.
6270 	 */
6271 	if (bar != -1) {
6272 		ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6273 	            SYS_RES_MEMORY, &bar, RF_ACTIVE);
6274 		if (ctx->ifc_msix_mem == NULL) {
6275 			device_printf(dev, "Unable to map MSI-X table\n");
6276 			goto msi;
6277 		}
6278 	}
6279 
6280 	admincnt = sctx->isc_admin_intrcnt;
6281 #if IFLIB_DEBUG
6282 	/* use only 1 qset in debug mode */
6283 	queuemsgs = min(msgs - admincnt, 1);
6284 #else
6285 	queuemsgs = msgs - admincnt;
6286 #endif
6287 #ifdef RSS
6288 	queues = imin(queuemsgs, rss_getnumbuckets());
6289 #else
6290 	queues = queuemsgs;
6291 #endif
6292 	queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6293 	if (bootverbose)
6294 		device_printf(dev,
6295 		    "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6296 		    CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6297 #ifdef  RSS
6298 	/* If we're doing RSS, clamp at the number of RSS buckets */
6299 	if (queues > rss_getnumbuckets())
6300 		queues = rss_getnumbuckets();
6301 #endif
6302 	if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6303 		rx_queues = iflib_num_rx_queues;
6304 	else
6305 		rx_queues = queues;
6306 
6307 	if (rx_queues > scctx->isc_nrxqsets)
6308 		rx_queues = scctx->isc_nrxqsets;
6309 
6310 	/*
6311 	 * We want this to be all logical CPUs by default
6312 	 */
6313 	if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6314 		tx_queues = iflib_num_tx_queues;
6315 	else
6316 		tx_queues = mp_ncpus;
6317 
6318 	if (tx_queues > scctx->isc_ntxqsets)
6319 		tx_queues = scctx->isc_ntxqsets;
6320 
6321 	if (ctx->ifc_sysctl_qs_eq_override == 0) {
6322 #ifdef INVARIANTS
6323 		if (tx_queues != rx_queues)
6324 			device_printf(dev,
6325 			    "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6326 			    min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6327 #endif
6328 		tx_queues = min(rx_queues, tx_queues);
6329 		rx_queues = min(rx_queues, tx_queues);
6330 	}
6331 
6332 	vectors = rx_queues + admincnt;
6333 	if (msgs < vectors) {
6334 		device_printf(dev,
6335 		    "insufficient number of MSI-X vectors "
6336 		    "(supported %d, need %d)\n", msgs, vectors);
6337 		goto msi;
6338 	}
6339 
6340 	device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6341 	    tx_queues);
6342 	msgs = vectors;
6343 	if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6344 		if (vectors != msgs) {
6345 			device_printf(dev,
6346 			    "Unable to allocate sufficient MSI-X vectors "
6347 			    "(got %d, need %d)\n", vectors, msgs);
6348 			pci_release_msi(dev);
6349 			if (bar != -1) {
6350 				bus_release_resource(dev, SYS_RES_MEMORY, bar,
6351 				    ctx->ifc_msix_mem);
6352 				ctx->ifc_msix_mem = NULL;
6353 			}
6354 			goto msi;
6355 		}
6356 		device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6357 		    vectors);
6358 		scctx->isc_vectors = vectors;
6359 		scctx->isc_nrxqsets = rx_queues;
6360 		scctx->isc_ntxqsets = tx_queues;
6361 		scctx->isc_intr = IFLIB_INTR_MSIX;
6362 
6363 		return (vectors);
6364 	} else {
6365 		device_printf(dev,
6366 		    "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6367 		    err);
6368 		if (bar != -1) {
6369 			bus_release_resource(dev, SYS_RES_MEMORY, bar,
6370 			    ctx->ifc_msix_mem);
6371 			ctx->ifc_msix_mem = NULL;
6372 		}
6373 	}
6374 
6375 msi:
6376 	vectors = pci_msi_count(dev);
6377 	scctx->isc_nrxqsets = 1;
6378 	scctx->isc_ntxqsets = 1;
6379 	scctx->isc_vectors = vectors;
6380 	if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6381 		device_printf(dev,"Using an MSI interrupt\n");
6382 		scctx->isc_intr = IFLIB_INTR_MSI;
6383 	} else {
6384 		scctx->isc_vectors = 1;
6385 		device_printf(dev,"Using a Legacy interrupt\n");
6386 		scctx->isc_intr = IFLIB_INTR_LEGACY;
6387 	}
6388 
6389 	return (vectors);
6390 }
6391 
6392 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6393 
6394 static int
6395 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6396 {
6397 	int rc;
6398 	uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6399 	struct sbuf *sb;
6400 	const char *ring_state = "UNKNOWN";
6401 
6402 	/* XXX needed ? */
6403 	rc = sysctl_wire_old_buffer(req, 0);
6404 	MPASS(rc == 0);
6405 	if (rc != 0)
6406 		return (rc);
6407 	sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6408 	MPASS(sb != NULL);
6409 	if (sb == NULL)
6410 		return (ENOMEM);
6411 	if (state[3] <= 3)
6412 		ring_state = ring_states[state[3]];
6413 
6414 	sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6415 		    state[0], state[1], state[2], ring_state);
6416 	rc = sbuf_finish(sb);
6417 	sbuf_delete(sb);
6418         return(rc);
6419 }
6420 
6421 enum iflib_ndesc_handler {
6422 	IFLIB_NTXD_HANDLER,
6423 	IFLIB_NRXD_HANDLER,
6424 };
6425 
6426 static int
6427 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6428 {
6429 	if_ctx_t ctx = (void *)arg1;
6430 	enum iflib_ndesc_handler type = arg2;
6431 	char buf[256] = {0};
6432 	qidx_t *ndesc;
6433 	char *p, *next;
6434 	int nqs, rc, i;
6435 
6436 	nqs = 8;
6437 	switch(type) {
6438 	case IFLIB_NTXD_HANDLER:
6439 		ndesc = ctx->ifc_sysctl_ntxds;
6440 		if (ctx->ifc_sctx)
6441 			nqs = ctx->ifc_sctx->isc_ntxqs;
6442 		break;
6443 	case IFLIB_NRXD_HANDLER:
6444 		ndesc = ctx->ifc_sysctl_nrxds;
6445 		if (ctx->ifc_sctx)
6446 			nqs = ctx->ifc_sctx->isc_nrxqs;
6447 		break;
6448 	default:
6449 		printf("%s: unhandled type\n", __func__);
6450 		return (EINVAL);
6451 	}
6452 	if (nqs == 0)
6453 		nqs = 8;
6454 
6455 	for (i=0; i<8; i++) {
6456 		if (i >= nqs)
6457 			break;
6458 		if (i)
6459 			strcat(buf, ",");
6460 		sprintf(strchr(buf, 0), "%d", ndesc[i]);
6461 	}
6462 
6463 	rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6464 	if (rc || req->newptr == NULL)
6465 		return rc;
6466 
6467 	for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6468 	    i++, p = strsep(&next, " ,")) {
6469 		ndesc[i] = strtoul(p, NULL, 10);
6470 	}
6471 
6472 	return(rc);
6473 }
6474 
6475 #define NAME_BUFLEN 32
6476 static void
6477 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6478 {
6479         device_t dev = iflib_get_dev(ctx);
6480 	struct sysctl_oid_list *child, *oid_list;
6481 	struct sysctl_ctx_list *ctx_list;
6482 	struct sysctl_oid *node;
6483 
6484 	ctx_list = device_get_sysctl_ctx(dev);
6485 	child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6486 	ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6487 						      CTLFLAG_RD, NULL, "IFLIB fields");
6488 	oid_list = SYSCTL_CHILDREN(node);
6489 
6490 	SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6491 		       CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
6492 		       "driver version");
6493 
6494 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6495 		       CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6496 			"# of txqs to use, 0 => use default #");
6497 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6498 		       CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6499 			"# of rxqs to use, 0 => use default #");
6500 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6501 		       CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6502                        "permit #txq != #rxq");
6503 	SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6504                       CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6505                       "disable MSI-X (default 0)");
6506 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6507 		       CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6508 		       "set the RX budget");
6509 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6510 		       CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6511 		       "cause TX to abdicate instead of running to completion");
6512 	ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6513 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6514 		       CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6515 		       "offset to start using cores at");
6516 	SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6517 		       CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6518 		       "use separate cores for TX and RX");
6519 
6520 	/* XXX change for per-queue sizes */
6521 	SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6522 		       CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
6523                        mp_ndesc_handler, "A",
6524 		       "list of # of TX descriptors to use, 0 = use default #");
6525 	SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6526 		       CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
6527                        mp_ndesc_handler, "A",
6528 		       "list of # of RX descriptors to use, 0 = use default #");
6529 }
6530 
6531 static void
6532 iflib_add_device_sysctl_post(if_ctx_t ctx)
6533 {
6534 	if_shared_ctx_t sctx = ctx->ifc_sctx;
6535 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6536         device_t dev = iflib_get_dev(ctx);
6537 	struct sysctl_oid_list *child;
6538 	struct sysctl_ctx_list *ctx_list;
6539 	iflib_fl_t fl;
6540 	iflib_txq_t txq;
6541 	iflib_rxq_t rxq;
6542 	int i, j;
6543 	char namebuf[NAME_BUFLEN];
6544 	char *qfmt;
6545 	struct sysctl_oid *queue_node, *fl_node, *node;
6546 	struct sysctl_oid_list *queue_list, *fl_list;
6547 	ctx_list = device_get_sysctl_ctx(dev);
6548 
6549 	node = ctx->ifc_sysctl_node;
6550 	child = SYSCTL_CHILDREN(node);
6551 
6552 	if (scctx->isc_ntxqsets > 100)
6553 		qfmt = "txq%03d";
6554 	else if (scctx->isc_ntxqsets > 10)
6555 		qfmt = "txq%02d";
6556 	else
6557 		qfmt = "txq%d";
6558 	for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6559 		snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6560 		queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6561 					     CTLFLAG_RD, NULL, "Queue Name");
6562 		queue_list = SYSCTL_CHILDREN(queue_node);
6563 #if MEMORY_LOGGING
6564 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6565 				CTLFLAG_RD,
6566 				&txq->ift_dequeued, "total mbufs freed");
6567 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6568 				CTLFLAG_RD,
6569 				&txq->ift_enqueued, "total mbufs enqueued");
6570 #endif
6571 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6572 				   CTLFLAG_RD,
6573 				   &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6574 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6575 				   CTLFLAG_RD,
6576 				   &txq->ift_pullups, "# of times m_pullup was called");
6577 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6578 				   CTLFLAG_RD,
6579 				   &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6580 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6581 				   CTLFLAG_RD,
6582 				   &txq->ift_no_desc_avail, "# of times no descriptors were available");
6583 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6584 				   CTLFLAG_RD,
6585 				   &txq->ift_map_failed, "# of times DMA map failed");
6586 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6587 				   CTLFLAG_RD,
6588 				   &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6589 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6590 				   CTLFLAG_RD,
6591 				   &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6592 		SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6593 				   CTLFLAG_RD,
6594 				   &txq->ift_pidx, 1, "Producer Index");
6595 		SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6596 				   CTLFLAG_RD,
6597 				   &txq->ift_cidx, 1, "Consumer Index");
6598 		SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6599 				   CTLFLAG_RD,
6600 				   &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6601 		SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6602 				   CTLFLAG_RD,
6603 				   &txq->ift_in_use, 1, "descriptors in use");
6604 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6605 				   CTLFLAG_RD,
6606 				   &txq->ift_processed, "descriptors procesed for clean");
6607 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6608 				   CTLFLAG_RD,
6609 				   &txq->ift_cleaned, "total cleaned");
6610 		SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6611 				CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
6612 				0, mp_ring_state_handler, "A", "soft ring state");
6613 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6614 				       CTLFLAG_RD, &txq->ift_br->enqueues,
6615 				       "# of enqueues to the mp_ring for this queue");
6616 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6617 				       CTLFLAG_RD, &txq->ift_br->drops,
6618 				       "# of drops in the mp_ring for this queue");
6619 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6620 				       CTLFLAG_RD, &txq->ift_br->starts,
6621 				       "# of normal consumer starts in the mp_ring for this queue");
6622 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6623 				       CTLFLAG_RD, &txq->ift_br->stalls,
6624 					       "# of consumer stalls in the mp_ring for this queue");
6625 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6626 			       CTLFLAG_RD, &txq->ift_br->restarts,
6627 				       "# of consumer restarts in the mp_ring for this queue");
6628 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6629 				       CTLFLAG_RD, &txq->ift_br->abdications,
6630 				       "# of consumer abdications in the mp_ring for this queue");
6631 	}
6632 
6633 	if (scctx->isc_nrxqsets > 100)
6634 		qfmt = "rxq%03d";
6635 	else if (scctx->isc_nrxqsets > 10)
6636 		qfmt = "rxq%02d";
6637 	else
6638 		qfmt = "rxq%d";
6639 	for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6640 		snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6641 		queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6642 					     CTLFLAG_RD, NULL, "Queue Name");
6643 		queue_list = SYSCTL_CHILDREN(queue_node);
6644 		if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6645 			SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6646 				       CTLFLAG_RD,
6647 				       &rxq->ifr_cq_cidx, 1, "Consumer Index");
6648 		}
6649 
6650 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6651 			snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6652 			fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6653 						     CTLFLAG_RD, NULL, "freelist Name");
6654 			fl_list = SYSCTL_CHILDREN(fl_node);
6655 			SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6656 				       CTLFLAG_RD,
6657 				       &fl->ifl_pidx, 1, "Producer Index");
6658 			SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6659 				       CTLFLAG_RD,
6660 				       &fl->ifl_cidx, 1, "Consumer Index");
6661 			SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6662 				       CTLFLAG_RD,
6663 				       &fl->ifl_credits, 1, "credits available");
6664 #if MEMORY_LOGGING
6665 			SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6666 					CTLFLAG_RD,
6667 					&fl->ifl_m_enqueued, "mbufs allocated");
6668 			SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6669 					CTLFLAG_RD,
6670 					&fl->ifl_m_dequeued, "mbufs freed");
6671 			SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6672 					CTLFLAG_RD,
6673 					&fl->ifl_cl_enqueued, "clusters allocated");
6674 			SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6675 					CTLFLAG_RD,
6676 					&fl->ifl_cl_dequeued, "clusters freed");
6677 #endif
6678 
6679 		}
6680 	}
6681 
6682 }
6683 
6684 void
6685 iflib_request_reset(if_ctx_t ctx)
6686 {
6687 
6688 	STATE_LOCK(ctx);
6689 	ctx->ifc_flags |= IFC_DO_RESET;
6690 	STATE_UNLOCK(ctx);
6691 }
6692 
6693 #ifndef __NO_STRICT_ALIGNMENT
6694 static struct mbuf *
6695 iflib_fixup_rx(struct mbuf *m)
6696 {
6697 	struct mbuf *n;
6698 
6699 	if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6700 		bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6701 		m->m_data += ETHER_HDR_LEN;
6702 		n = m;
6703 	} else {
6704 		MGETHDR(n, M_NOWAIT, MT_DATA);
6705 		if (n == NULL) {
6706 			m_freem(m);
6707 			return (NULL);
6708 		}
6709 		bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6710 		m->m_data += ETHER_HDR_LEN;
6711 		m->m_len -= ETHER_HDR_LEN;
6712 		n->m_len = ETHER_HDR_LEN;
6713 		M_MOVE_PKTHDR(n, m);
6714 		n->m_next = m;
6715 	}
6716 	return (n);
6717 }
6718 #endif
6719 
6720 #ifdef NETDUMP
6721 static void
6722 iflib_netdump_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6723 {
6724 	if_ctx_t ctx;
6725 
6726 	ctx = if_getsoftc(ifp);
6727 	CTX_LOCK(ctx);
6728 	*nrxr = NRXQSETS(ctx);
6729 	*ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6730 	*clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6731 	CTX_UNLOCK(ctx);
6732 }
6733 
6734 static void
6735 iflib_netdump_event(if_t ifp, enum netdump_ev event)
6736 {
6737 	if_ctx_t ctx;
6738 	if_softc_ctx_t scctx;
6739 	iflib_fl_t fl;
6740 	iflib_rxq_t rxq;
6741 	int i, j;
6742 
6743 	ctx = if_getsoftc(ifp);
6744 	scctx = &ctx->ifc_softc_ctx;
6745 
6746 	switch (event) {
6747 	case NETDUMP_START:
6748 		for (i = 0; i < scctx->isc_nrxqsets; i++) {
6749 			rxq = &ctx->ifc_rxqs[i];
6750 			for (j = 0; j < rxq->ifr_nfl; j++) {
6751 				fl = rxq->ifr_fl;
6752 				fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6753 			}
6754 		}
6755 		iflib_no_tx_batch = 1;
6756 		break;
6757 	default:
6758 		break;
6759 	}
6760 }
6761 
6762 static int
6763 iflib_netdump_transmit(if_t ifp, struct mbuf *m)
6764 {
6765 	if_ctx_t ctx;
6766 	iflib_txq_t txq;
6767 	int error;
6768 
6769 	ctx = if_getsoftc(ifp);
6770 	if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6771 	    IFF_DRV_RUNNING)
6772 		return (EBUSY);
6773 
6774 	txq = &ctx->ifc_txqs[0];
6775 	error = iflib_encap(txq, &m);
6776 	if (error == 0)
6777 		(void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6778 	return (error);
6779 }
6780 
6781 static int
6782 iflib_netdump_poll(if_t ifp, int count)
6783 {
6784 	if_ctx_t ctx;
6785 	if_softc_ctx_t scctx;
6786 	iflib_txq_t txq;
6787 	int i;
6788 
6789 	ctx = if_getsoftc(ifp);
6790 	scctx = &ctx->ifc_softc_ctx;
6791 
6792 	if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6793 	    IFF_DRV_RUNNING)
6794 		return (EBUSY);
6795 
6796 	txq = &ctx->ifc_txqs[0];
6797 	(void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6798 
6799 	for (i = 0; i < scctx->isc_nrxqsets; i++)
6800 		(void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6801 	return (0);
6802 }
6803 #endif /* NETDUMP */
6804