1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/jail.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/md5.h> 44 #include <sys/mutex.h> 45 #include <sys/module.h> 46 #include <sys/kobj.h> 47 #include <sys/rman.h> 48 #include <sys/proc.h> 49 #include <sys/sbuf.h> 50 #include <sys/smp.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/syslog.h> 55 #include <sys/taskqueue.h> 56 #include <sys/limits.h> 57 58 #include <net/if.h> 59 #include <net/if_var.h> 60 #include <net/if_types.h> 61 #include <net/if_media.h> 62 #include <net/bpf.h> 63 #include <net/ethernet.h> 64 #include <net/mp_ring.h> 65 #include <net/vnet.h> 66 67 #include <netinet/in.h> 68 #include <netinet/in_pcb.h> 69 #include <netinet/tcp_lro.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/if_ether.h> 72 #include <netinet/ip.h> 73 #include <netinet/ip6.h> 74 #include <netinet/tcp.h> 75 #include <netinet/ip_var.h> 76 #include <netinet/netdump/netdump.h> 77 #include <netinet6/ip6_var.h> 78 79 #include <machine/bus.h> 80 #include <machine/in_cksum.h> 81 82 #include <vm/vm.h> 83 #include <vm/pmap.h> 84 85 #include <dev/led/led.h> 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pci_private.h> 89 90 #include <net/iflib.h> 91 #include <net/iflib_private.h> 92 93 #include "ifdi_if.h" 94 95 #if defined(__i386__) || defined(__amd64__) 96 #include <sys/memdesc.h> 97 #include <machine/bus.h> 98 #include <machine/md_var.h> 99 #include <machine/specialreg.h> 100 #include <x86/include/busdma_impl.h> 101 #include <x86/iommu/busdma_dmar.h> 102 #endif 103 104 #include <sys/bitstring.h> 105 /* 106 * enable accounting of every mbuf as it comes in to and goes out of 107 * iflib's software descriptor references 108 */ 109 #define MEMORY_LOGGING 0 110 /* 111 * Enable mbuf vectors for compressing long mbuf chains 112 */ 113 114 /* 115 * NB: 116 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 117 * we prefetch needs to be determined by the time spent in m_free vis a vis 118 * the cost of a prefetch. This will of course vary based on the workload: 119 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 120 * is quite expensive, thus suggesting very little prefetch. 121 * - small packet forwarding which is just returning a single mbuf to 122 * UMA will typically be very fast vis a vis the cost of a memory 123 * access. 124 */ 125 126 127 /* 128 * File organization: 129 * - private structures 130 * - iflib private utility functions 131 * - ifnet functions 132 * - vlan registry and other exported functions 133 * - iflib public core functions 134 * 135 * 136 */ 137 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 138 139 struct iflib_txq; 140 typedef struct iflib_txq *iflib_txq_t; 141 struct iflib_rxq; 142 typedef struct iflib_rxq *iflib_rxq_t; 143 struct iflib_fl; 144 typedef struct iflib_fl *iflib_fl_t; 145 146 struct iflib_ctx; 147 148 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 149 static void iflib_timer(void *arg); 150 151 typedef struct iflib_filter_info { 152 driver_filter_t *ifi_filter; 153 void *ifi_filter_arg; 154 struct grouptask *ifi_task; 155 void *ifi_ctx; 156 } *iflib_filter_info_t; 157 158 struct iflib_ctx { 159 KOBJ_FIELDS; 160 /* 161 * Pointer to hardware driver's softc 162 */ 163 void *ifc_softc; 164 device_t ifc_dev; 165 if_t ifc_ifp; 166 167 cpuset_t ifc_cpus; 168 if_shared_ctx_t ifc_sctx; 169 struct if_softc_ctx ifc_softc_ctx; 170 171 struct sx ifc_ctx_sx; 172 struct mtx ifc_state_mtx; 173 174 uint16_t ifc_nhwtxqs; 175 176 iflib_txq_t ifc_txqs; 177 iflib_rxq_t ifc_rxqs; 178 uint32_t ifc_if_flags; 179 uint32_t ifc_flags; 180 uint32_t ifc_max_fl_buf_size; 181 int ifc_in_detach; 182 183 int ifc_link_state; 184 int ifc_link_irq; 185 int ifc_watchdog_events; 186 struct cdev *ifc_led_dev; 187 struct resource *ifc_msix_mem; 188 189 struct if_irq ifc_legacy_irq; 190 struct grouptask ifc_admin_task; 191 struct grouptask ifc_vflr_task; 192 struct iflib_filter_info ifc_filter_info; 193 struct ifmedia ifc_media; 194 195 struct sysctl_oid *ifc_sysctl_node; 196 uint16_t ifc_sysctl_ntxqs; 197 uint16_t ifc_sysctl_nrxqs; 198 uint16_t ifc_sysctl_qs_eq_override; 199 uint16_t ifc_sysctl_rx_budget; 200 201 qidx_t ifc_sysctl_ntxds[8]; 202 qidx_t ifc_sysctl_nrxds[8]; 203 struct if_txrx ifc_txrx; 204 #define isc_txd_encap ifc_txrx.ift_txd_encap 205 #define isc_txd_flush ifc_txrx.ift_txd_flush 206 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 207 #define isc_rxd_available ifc_txrx.ift_rxd_available 208 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 209 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 210 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 211 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 212 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 213 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 214 eventhandler_tag ifc_vlan_attach_event; 215 eventhandler_tag ifc_vlan_detach_event; 216 uint8_t ifc_mac[ETHER_ADDR_LEN]; 217 char ifc_mtx_name[16]; 218 }; 219 220 221 void * 222 iflib_get_softc(if_ctx_t ctx) 223 { 224 225 return (ctx->ifc_softc); 226 } 227 228 device_t 229 iflib_get_dev(if_ctx_t ctx) 230 { 231 232 return (ctx->ifc_dev); 233 } 234 235 if_t 236 iflib_get_ifp(if_ctx_t ctx) 237 { 238 239 return (ctx->ifc_ifp); 240 } 241 242 struct ifmedia * 243 iflib_get_media(if_ctx_t ctx) 244 { 245 246 return (&ctx->ifc_media); 247 } 248 249 uint32_t 250 iflib_get_flags(if_ctx_t ctx) 251 { 252 return (ctx->ifc_flags); 253 } 254 255 void 256 iflib_set_detach(if_ctx_t ctx) 257 { 258 ctx->ifc_in_detach = 1; 259 } 260 261 void 262 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 263 { 264 265 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 266 } 267 268 if_softc_ctx_t 269 iflib_get_softc_ctx(if_ctx_t ctx) 270 { 271 272 return (&ctx->ifc_softc_ctx); 273 } 274 275 if_shared_ctx_t 276 iflib_get_sctx(if_ctx_t ctx) 277 { 278 279 return (ctx->ifc_sctx); 280 } 281 282 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 283 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 284 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 285 286 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 287 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 288 289 #define RX_SW_DESC_MAP_CREATED (1 << 0) 290 #define TX_SW_DESC_MAP_CREATED (1 << 1) 291 #define RX_SW_DESC_INUSE (1 << 3) 292 #define TX_SW_DESC_MAPPED (1 << 4) 293 294 #define M_TOOBIG M_PROTO1 295 296 typedef struct iflib_sw_rx_desc_array { 297 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 298 struct mbuf **ifsd_m; /* pkthdr mbufs */ 299 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 300 uint8_t *ifsd_flags; 301 } iflib_rxsd_array_t; 302 303 typedef struct iflib_sw_tx_desc_array { 304 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 305 struct mbuf **ifsd_m; /* pkthdr mbufs */ 306 uint8_t *ifsd_flags; 307 } if_txsd_vec_t; 308 309 310 /* magic number that should be high enough for any hardware */ 311 #define IFLIB_MAX_TX_SEGS 128 312 /* bnxt supports 64 with hardware LRO enabled */ 313 #define IFLIB_MAX_RX_SEGS 64 314 #define IFLIB_RX_COPY_THRESH 128 315 #define IFLIB_MAX_RX_REFRESH 32 316 /* The minimum descriptors per second before we start coalescing */ 317 #define IFLIB_MIN_DESC_SEC 16384 318 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 319 #define IFLIB_QUEUE_IDLE 0 320 #define IFLIB_QUEUE_HUNG 1 321 #define IFLIB_QUEUE_WORKING 2 322 /* maximum number of txqs that can share an rx interrupt */ 323 #define IFLIB_MAX_TX_SHARED_INTR 4 324 325 /* this should really scale with ring size - this is a fairly arbitrary value */ 326 #define TX_BATCH_SIZE 32 327 328 #define IFLIB_RESTART_BUDGET 8 329 330 331 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 332 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 333 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 334 struct iflib_txq { 335 qidx_t ift_in_use; 336 qidx_t ift_cidx; 337 qidx_t ift_cidx_processed; 338 qidx_t ift_pidx; 339 uint8_t ift_gen; 340 uint8_t ift_br_offset; 341 uint16_t ift_npending; 342 uint16_t ift_db_pending; 343 uint16_t ift_rs_pending; 344 /* implicit pad */ 345 uint8_t ift_txd_size[8]; 346 uint64_t ift_processed; 347 uint64_t ift_cleaned; 348 uint64_t ift_cleaned_prev; 349 #if MEMORY_LOGGING 350 uint64_t ift_enqueued; 351 uint64_t ift_dequeued; 352 #endif 353 uint64_t ift_no_tx_dma_setup; 354 uint64_t ift_no_desc_avail; 355 uint64_t ift_mbuf_defrag_failed; 356 uint64_t ift_mbuf_defrag; 357 uint64_t ift_map_failed; 358 uint64_t ift_txd_encap_efbig; 359 uint64_t ift_pullups; 360 uint64_t ift_last_timer_tick; 361 362 struct mtx ift_mtx; 363 struct mtx ift_db_mtx; 364 365 /* constant values */ 366 if_ctx_t ift_ctx; 367 struct ifmp_ring *ift_br; 368 struct grouptask ift_task; 369 qidx_t ift_size; 370 uint16_t ift_id; 371 struct callout ift_timer; 372 373 if_txsd_vec_t ift_sds; 374 uint8_t ift_qstatus; 375 uint8_t ift_closed; 376 uint8_t ift_update_freq; 377 struct iflib_filter_info ift_filter_info; 378 bus_dma_tag_t ift_desc_tag; 379 bus_dma_tag_t ift_tso_desc_tag; 380 iflib_dma_info_t ift_ifdi; 381 #define MTX_NAME_LEN 16 382 char ift_mtx_name[MTX_NAME_LEN]; 383 char ift_db_mtx_name[MTX_NAME_LEN]; 384 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 385 #ifdef IFLIB_DIAGNOSTICS 386 uint64_t ift_cpu_exec_count[256]; 387 #endif 388 } __aligned(CACHE_LINE_SIZE); 389 390 struct iflib_fl { 391 qidx_t ifl_cidx; 392 qidx_t ifl_pidx; 393 qidx_t ifl_credits; 394 uint8_t ifl_gen; 395 uint8_t ifl_rxd_size; 396 #if MEMORY_LOGGING 397 uint64_t ifl_m_enqueued; 398 uint64_t ifl_m_dequeued; 399 uint64_t ifl_cl_enqueued; 400 uint64_t ifl_cl_dequeued; 401 #endif 402 /* implicit pad */ 403 404 bitstr_t *ifl_rx_bitmap; 405 qidx_t ifl_fragidx; 406 /* constant */ 407 qidx_t ifl_size; 408 uint16_t ifl_buf_size; 409 uint16_t ifl_cltype; 410 uma_zone_t ifl_zone; 411 iflib_rxsd_array_t ifl_sds; 412 iflib_rxq_t ifl_rxq; 413 uint8_t ifl_id; 414 bus_dma_tag_t ifl_desc_tag; 415 iflib_dma_info_t ifl_ifdi; 416 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 417 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 418 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 419 } __aligned(CACHE_LINE_SIZE); 420 421 static inline qidx_t 422 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 423 { 424 qidx_t used; 425 426 if (pidx > cidx) 427 used = pidx - cidx; 428 else if (pidx < cidx) 429 used = size - cidx + pidx; 430 else if (gen == 0 && pidx == cidx) 431 used = 0; 432 else if (gen == 1 && pidx == cidx) 433 used = size; 434 else 435 panic("bad state"); 436 437 return (used); 438 } 439 440 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 441 442 #define IDXDIFF(head, tail, wrap) \ 443 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 444 445 struct iflib_rxq { 446 /* If there is a separate completion queue - 447 * these are the cq cidx and pidx. Otherwise 448 * these are unused. 449 */ 450 qidx_t ifr_size; 451 qidx_t ifr_cq_cidx; 452 qidx_t ifr_cq_pidx; 453 uint8_t ifr_cq_gen; 454 uint8_t ifr_fl_offset; 455 456 if_ctx_t ifr_ctx; 457 iflib_fl_t ifr_fl; 458 uint64_t ifr_rx_irq; 459 uint16_t ifr_id; 460 uint8_t ifr_lro_enabled; 461 uint8_t ifr_nfl; 462 uint8_t ifr_ntxqirq; 463 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 464 struct lro_ctrl ifr_lc; 465 struct grouptask ifr_task; 466 struct iflib_filter_info ifr_filter_info; 467 iflib_dma_info_t ifr_ifdi; 468 469 /* dynamically allocate if any drivers need a value substantially larger than this */ 470 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 471 #ifdef IFLIB_DIAGNOSTICS 472 uint64_t ifr_cpu_exec_count[256]; 473 #endif 474 } __aligned(CACHE_LINE_SIZE); 475 476 typedef struct if_rxsd { 477 caddr_t *ifsd_cl; 478 struct mbuf **ifsd_m; 479 iflib_fl_t ifsd_fl; 480 qidx_t ifsd_cidx; 481 } *if_rxsd_t; 482 483 /* multiple of word size */ 484 #ifdef __LP64__ 485 #define PKT_INFO_SIZE 6 486 #define RXD_INFO_SIZE 5 487 #define PKT_TYPE uint64_t 488 #else 489 #define PKT_INFO_SIZE 11 490 #define RXD_INFO_SIZE 8 491 #define PKT_TYPE uint32_t 492 #endif 493 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 494 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 495 496 typedef struct if_pkt_info_pad { 497 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 498 } *if_pkt_info_pad_t; 499 typedef struct if_rxd_info_pad { 500 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 501 } *if_rxd_info_pad_t; 502 503 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 504 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 505 506 507 static inline void 508 pkt_info_zero(if_pkt_info_t pi) 509 { 510 if_pkt_info_pad_t pi_pad; 511 512 pi_pad = (if_pkt_info_pad_t)pi; 513 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 514 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 515 #ifndef __LP64__ 516 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 517 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 518 #endif 519 } 520 521 static device_method_t iflib_pseudo_methods[] = { 522 DEVMETHOD(device_attach, noop_attach), 523 DEVMETHOD(device_detach, iflib_pseudo_detach), 524 DEVMETHOD_END 525 }; 526 527 driver_t iflib_pseudodriver = { 528 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 529 }; 530 531 static inline void 532 rxd_info_zero(if_rxd_info_t ri) 533 { 534 if_rxd_info_pad_t ri_pad; 535 int i; 536 537 ri_pad = (if_rxd_info_pad_t)ri; 538 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 539 ri_pad->rxd_val[i] = 0; 540 ri_pad->rxd_val[i+1] = 0; 541 ri_pad->rxd_val[i+2] = 0; 542 ri_pad->rxd_val[i+3] = 0; 543 } 544 #ifdef __LP64__ 545 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 546 #endif 547 } 548 549 /* 550 * Only allow a single packet to take up most 1/nth of the tx ring 551 */ 552 #define MAX_SINGLE_PACKET_FRACTION 12 553 #define IF_BAD_DMA (bus_addr_t)-1 554 555 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 556 557 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 558 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 559 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 560 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 561 562 563 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 564 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 565 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 566 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 567 568 569 570 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 571 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 572 573 574 /* Our boot-time initialization hook */ 575 static int iflib_module_event_handler(module_t, int, void *); 576 577 static moduledata_t iflib_moduledata = { 578 "iflib", 579 iflib_module_event_handler, 580 NULL 581 }; 582 583 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 584 MODULE_VERSION(iflib, 1); 585 586 MODULE_DEPEND(iflib, pci, 1, 1, 1); 587 MODULE_DEPEND(iflib, ether, 1, 1, 1); 588 589 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 590 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 591 592 #ifndef IFLIB_DEBUG_COUNTERS 593 #ifdef INVARIANTS 594 #define IFLIB_DEBUG_COUNTERS 1 595 #else 596 #define IFLIB_DEBUG_COUNTERS 0 597 #endif /* !INVARIANTS */ 598 #endif 599 600 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 601 "iflib driver parameters"); 602 603 /* 604 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 605 */ 606 static int iflib_min_tx_latency = 0; 607 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 608 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 609 static int iflib_no_tx_batch = 0; 610 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 611 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 612 613 614 #if IFLIB_DEBUG_COUNTERS 615 616 static int iflib_tx_seen; 617 static int iflib_tx_sent; 618 static int iflib_tx_encap; 619 static int iflib_rx_allocs; 620 static int iflib_fl_refills; 621 static int iflib_fl_refills_large; 622 static int iflib_tx_frees; 623 624 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 625 &iflib_tx_seen, 0, "# tx mbufs seen"); 626 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 627 &iflib_tx_sent, 0, "# tx mbufs sent"); 628 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 629 &iflib_tx_encap, 0, "# tx mbufs encapped"); 630 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 631 &iflib_tx_frees, 0, "# tx frees"); 632 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 633 &iflib_rx_allocs, 0, "# rx allocations"); 634 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 635 &iflib_fl_refills, 0, "# refills"); 636 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 637 &iflib_fl_refills_large, 0, "# large refills"); 638 639 640 static int iflib_txq_drain_flushing; 641 static int iflib_txq_drain_oactive; 642 static int iflib_txq_drain_notready; 643 static int iflib_txq_drain_encapfail; 644 645 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 646 &iflib_txq_drain_flushing, 0, "# drain flushes"); 647 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 648 &iflib_txq_drain_oactive, 0, "# drain oactives"); 649 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 650 &iflib_txq_drain_notready, 0, "# drain notready"); 651 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 652 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 653 654 655 static int iflib_encap_load_mbuf_fail; 656 static int iflib_encap_pad_mbuf_fail; 657 static int iflib_encap_txq_avail_fail; 658 static int iflib_encap_txd_encap_fail; 659 660 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 661 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 663 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 665 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 666 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 667 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 668 669 static int iflib_task_fn_rxs; 670 static int iflib_rx_intr_enables; 671 static int iflib_fast_intrs; 672 static int iflib_intr_link; 673 static int iflib_intr_msix; 674 static int iflib_rx_unavail; 675 static int iflib_rx_ctx_inactive; 676 static int iflib_rx_zero_len; 677 static int iflib_rx_if_input; 678 static int iflib_rx_mbuf_null; 679 static int iflib_rxd_flush; 680 681 static int iflib_verbose_debug; 682 683 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 684 &iflib_intr_link, 0, "# intr link calls"); 685 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 686 &iflib_intr_msix, 0, "# intr msix calls"); 687 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 688 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 689 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 690 &iflib_rx_intr_enables, 0, "# rx intr enables"); 691 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 692 &iflib_fast_intrs, 0, "# fast_intr calls"); 693 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 694 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 695 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 696 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 697 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 698 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 699 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 700 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 701 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 702 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 703 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 704 &iflib_rxd_flush, 0, "# times rxd_flush called"); 705 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 706 &iflib_verbose_debug, 0, "enable verbose debugging"); 707 708 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 709 static void 710 iflib_debug_reset(void) 711 { 712 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 713 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 714 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 715 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 716 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 717 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 718 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 719 iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 720 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 721 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 722 } 723 724 #else 725 #define DBG_COUNTER_INC(name) 726 static void iflib_debug_reset(void) {} 727 #endif 728 729 #define IFLIB_DEBUG 0 730 731 static void iflib_tx_structures_free(if_ctx_t ctx); 732 static void iflib_rx_structures_free(if_ctx_t ctx); 733 static int iflib_queues_alloc(if_ctx_t ctx); 734 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 735 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 736 static int iflib_qset_structures_setup(if_ctx_t ctx); 737 static int iflib_msix_init(if_ctx_t ctx); 738 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 739 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 740 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 741 static int iflib_register(if_ctx_t); 742 static void iflib_init_locked(if_ctx_t ctx); 743 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 744 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 745 static void iflib_ifmp_purge(iflib_txq_t txq); 746 static void _iflib_pre_assert(if_softc_ctx_t scctx); 747 static void iflib_if_init_locked(if_ctx_t ctx); 748 #ifndef __NO_STRICT_ALIGNMENT 749 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 750 #endif 751 752 NETDUMP_DEFINE(iflib); 753 754 #ifdef DEV_NETMAP 755 #include <sys/selinfo.h> 756 #include <net/netmap.h> 757 #include <dev/netmap/netmap_kern.h> 758 759 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 760 761 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 762 763 /* 764 * device-specific sysctl variables: 765 * 766 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 767 * During regular operations the CRC is stripped, but on some 768 * hardware reception of frames not multiple of 64 is slower, 769 * so using crcstrip=0 helps in benchmarks. 770 * 771 * iflib_rx_miss, iflib_rx_miss_bufs: 772 * count packets that might be missed due to lost interrupts. 773 */ 774 SYSCTL_DECL(_dev_netmap); 775 /* 776 * The xl driver by default strips CRCs and we do not override it. 777 */ 778 779 int iflib_crcstrip = 1; 780 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 781 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 782 783 int iflib_rx_miss, iflib_rx_miss_bufs; 784 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 785 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 786 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 787 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 788 789 /* 790 * Register/unregister. We are already under netmap lock. 791 * Only called on the first register or the last unregister. 792 */ 793 static int 794 iflib_netmap_register(struct netmap_adapter *na, int onoff) 795 { 796 struct ifnet *ifp = na->ifp; 797 if_ctx_t ctx = ifp->if_softc; 798 int status; 799 800 CTX_LOCK(ctx); 801 IFDI_INTR_DISABLE(ctx); 802 803 /* Tell the stack that the interface is no longer active */ 804 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 805 806 if (!CTX_IS_VF(ctx)) 807 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 808 809 /* enable or disable flags and callbacks in na and ifp */ 810 if (onoff) { 811 nm_set_native_flags(na); 812 } else { 813 nm_clear_native_flags(na); 814 } 815 iflib_stop(ctx); 816 iflib_init_locked(ctx); 817 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 818 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 819 if (status) 820 nm_clear_native_flags(na); 821 CTX_UNLOCK(ctx); 822 return (status); 823 } 824 825 static int 826 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 827 { 828 struct netmap_adapter *na = kring->na; 829 u_int const lim = kring->nkr_num_slots - 1; 830 u_int head = kring->rhead; 831 struct netmap_ring *ring = kring->ring; 832 bus_dmamap_t *map; 833 struct if_rxd_update iru; 834 if_ctx_t ctx = rxq->ifr_ctx; 835 iflib_fl_t fl = &rxq->ifr_fl[0]; 836 uint32_t refill_pidx, nic_i; 837 838 if (nm_i == head && __predict_true(!init)) 839 return 0; 840 iru_init(&iru, rxq, 0 /* flid */); 841 map = fl->ifl_sds.ifsd_map; 842 refill_pidx = netmap_idx_k2n(kring, nm_i); 843 /* 844 * IMPORTANT: we must leave one free slot in the ring, 845 * so move head back by one unit 846 */ 847 head = nm_prev(head, lim); 848 nic_i = UINT_MAX; 849 while (nm_i != head) { 850 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 851 struct netmap_slot *slot = &ring->slot[nm_i]; 852 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 853 uint32_t nic_i_dma = refill_pidx; 854 nic_i = netmap_idx_k2n(kring, nm_i); 855 856 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 857 858 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 859 return netmap_ring_reinit(kring); 860 861 fl->ifl_vm_addrs[tmp_pidx] = addr; 862 if (__predict_false(init) && map) { 863 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 864 } else if (map && (slot->flags & NS_BUF_CHANGED)) { 865 /* buffer has changed, reload map */ 866 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 867 } 868 slot->flags &= ~NS_BUF_CHANGED; 869 870 nm_i = nm_next(nm_i, lim); 871 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 872 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 873 continue; 874 875 iru.iru_pidx = refill_pidx; 876 iru.iru_count = tmp_pidx+1; 877 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 878 879 refill_pidx = nic_i; 880 if (map == NULL) 881 continue; 882 883 for (int n = 0; n < iru.iru_count; n++) { 884 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma], 885 BUS_DMASYNC_PREREAD); 886 /* XXX - change this to not use the netmap func*/ 887 nic_i_dma = nm_next(nic_i_dma, lim); 888 } 889 } 890 } 891 kring->nr_hwcur = head; 892 893 if (map) 894 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 895 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 896 if (__predict_true(nic_i != UINT_MAX)) 897 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 898 return (0); 899 } 900 901 /* 902 * Reconcile kernel and user view of the transmit ring. 903 * 904 * All information is in the kring. 905 * Userspace wants to send packets up to the one before kring->rhead, 906 * kernel knows kring->nr_hwcur is the first unsent packet. 907 * 908 * Here we push packets out (as many as possible), and possibly 909 * reclaim buffers from previously completed transmission. 910 * 911 * The caller (netmap) guarantees that there is only one instance 912 * running at any time. Any interference with other driver 913 * methods should be handled by the individual drivers. 914 */ 915 static int 916 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 917 { 918 struct netmap_adapter *na = kring->na; 919 struct ifnet *ifp = na->ifp; 920 struct netmap_ring *ring = kring->ring; 921 u_int nm_i; /* index into the netmap kring */ 922 u_int nic_i; /* index into the NIC ring */ 923 u_int n; 924 u_int const lim = kring->nkr_num_slots - 1; 925 u_int const head = kring->rhead; 926 struct if_pkt_info pi; 927 928 /* 929 * interrupts on every tx packet are expensive so request 930 * them every half ring, or where NS_REPORT is set 931 */ 932 u_int report_frequency = kring->nkr_num_slots >> 1; 933 /* device-specific */ 934 if_ctx_t ctx = ifp->if_softc; 935 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 936 937 if (txq->ift_sds.ifsd_map) 938 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 939 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 940 941 942 /* 943 * First part: process new packets to send. 944 * nm_i is the current index in the netmap kring, 945 * nic_i is the corresponding index in the NIC ring. 946 * 947 * If we have packets to send (nm_i != head) 948 * iterate over the netmap ring, fetch length and update 949 * the corresponding slot in the NIC ring. Some drivers also 950 * need to update the buffer's physical address in the NIC slot 951 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 952 * 953 * The netmap_reload_map() calls is especially expensive, 954 * even when (as in this case) the tag is 0, so do only 955 * when the buffer has actually changed. 956 * 957 * If possible do not set the report/intr bit on all slots, 958 * but only a few times per ring or when NS_REPORT is set. 959 * 960 * Finally, on 10G and faster drivers, it might be useful 961 * to prefetch the next slot and txr entry. 962 */ 963 964 nm_i = kring->nr_hwcur; 965 if (nm_i != head) { /* we have new packets to send */ 966 pkt_info_zero(&pi); 967 pi.ipi_segs = txq->ift_segs; 968 pi.ipi_qsidx = kring->ring_id; 969 nic_i = netmap_idx_k2n(kring, nm_i); 970 971 __builtin_prefetch(&ring->slot[nm_i]); 972 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 973 if (txq->ift_sds.ifsd_map) 974 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 975 976 for (n = 0; nm_i != head; n++) { 977 struct netmap_slot *slot = &ring->slot[nm_i]; 978 u_int len = slot->len; 979 uint64_t paddr; 980 void *addr = PNMB(na, slot, &paddr); 981 int flags = (slot->flags & NS_REPORT || 982 nic_i == 0 || nic_i == report_frequency) ? 983 IPI_TX_INTR : 0; 984 985 /* device-specific */ 986 pi.ipi_len = len; 987 pi.ipi_segs[0].ds_addr = paddr; 988 pi.ipi_segs[0].ds_len = len; 989 pi.ipi_nsegs = 1; 990 pi.ipi_ndescs = 0; 991 pi.ipi_pidx = nic_i; 992 pi.ipi_flags = flags; 993 994 /* Fill the slot in the NIC ring. */ 995 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 996 997 /* prefetch for next round */ 998 __builtin_prefetch(&ring->slot[nm_i + 1]); 999 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1000 if (txq->ift_sds.ifsd_map) { 1001 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1002 1003 NM_CHECK_ADDR_LEN(na, addr, len); 1004 1005 if (slot->flags & NS_BUF_CHANGED) { 1006 /* buffer has changed, reload map */ 1007 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 1008 } 1009 /* make sure changes to the buffer are synced */ 1010 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 1011 BUS_DMASYNC_PREWRITE); 1012 } 1013 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1014 nm_i = nm_next(nm_i, lim); 1015 nic_i = nm_next(nic_i, lim); 1016 } 1017 kring->nr_hwcur = nm_i; 1018 1019 /* synchronize the NIC ring */ 1020 if (txq->ift_sds.ifsd_map) 1021 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 1022 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1023 1024 /* (re)start the tx unit up to slot nic_i (excluded) */ 1025 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1026 } 1027 1028 /* 1029 * Second part: reclaim buffers for completed transmissions. 1030 * 1031 * If there are unclaimed buffers, attempt to reclaim them. 1032 * If none are reclaimed, and TX IRQs are not in use, do an initial 1033 * minimal delay, then trigger the tx handler which will spin in the 1034 * group task queue. 1035 */ 1036 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1037 if (iflib_tx_credits_update(ctx, txq)) { 1038 /* some tx completed, increment avail */ 1039 nic_i = txq->ift_cidx_processed; 1040 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1041 } 1042 } 1043 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1044 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1045 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1046 iflib_timer, txq, txq->ift_timer.c_cpu); 1047 } 1048 return (0); 1049 } 1050 1051 /* 1052 * Reconcile kernel and user view of the receive ring. 1053 * Same as for the txsync, this routine must be efficient. 1054 * The caller guarantees a single invocations, but races against 1055 * the rest of the driver should be handled here. 1056 * 1057 * On call, kring->rhead is the first packet that userspace wants 1058 * to keep, and kring->rcur is the wakeup point. 1059 * The kernel has previously reported packets up to kring->rtail. 1060 * 1061 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1062 * of whether or not we received an interrupt. 1063 */ 1064 static int 1065 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1066 { 1067 struct netmap_adapter *na = kring->na; 1068 struct netmap_ring *ring = kring->ring; 1069 uint32_t nm_i; /* index into the netmap ring */ 1070 uint32_t nic_i; /* index into the NIC ring */ 1071 u_int i, n; 1072 u_int const lim = kring->nkr_num_slots - 1; 1073 u_int const head = kring->rhead; 1074 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1075 struct if_rxd_info ri; 1076 1077 struct ifnet *ifp = na->ifp; 1078 if_ctx_t ctx = ifp->if_softc; 1079 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1080 iflib_fl_t fl = rxq->ifr_fl; 1081 if (head > lim) 1082 return netmap_ring_reinit(kring); 1083 1084 /* XXX check sync modes */ 1085 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1086 if (fl->ifl_sds.ifsd_map == NULL) 1087 continue; 1088 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 1089 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1090 } 1091 /* 1092 * First part: import newly received packets. 1093 * 1094 * nm_i is the index of the next free slot in the netmap ring, 1095 * nic_i is the index of the next received packet in the NIC ring, 1096 * and they may differ in case if_init() has been called while 1097 * in netmap mode. For the receive ring we have 1098 * 1099 * nic_i = rxr->next_check; 1100 * nm_i = kring->nr_hwtail (previous) 1101 * and 1102 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1103 * 1104 * rxr->next_check is set to 0 on a ring reinit 1105 */ 1106 if (netmap_no_pendintr || force_update) { 1107 int crclen = iflib_crcstrip ? 0 : 4; 1108 int error, avail; 1109 1110 for (i = 0; i < rxq->ifr_nfl; i++) { 1111 fl = &rxq->ifr_fl[i]; 1112 nic_i = fl->ifl_cidx; 1113 nm_i = netmap_idx_n2k(kring, nic_i); 1114 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 1115 for (n = 0; avail > 0; n++, avail--) { 1116 rxd_info_zero(&ri); 1117 ri.iri_frags = rxq->ifr_frags; 1118 ri.iri_qsidx = kring->ring_id; 1119 ri.iri_ifp = ctx->ifc_ifp; 1120 ri.iri_cidx = nic_i; 1121 1122 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1123 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1124 ring->slot[nm_i].flags = 0; 1125 if (fl->ifl_sds.ifsd_map) 1126 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1127 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1128 nm_i = nm_next(nm_i, lim); 1129 nic_i = nm_next(nic_i, lim); 1130 } 1131 if (n) { /* update the state variables */ 1132 if (netmap_no_pendintr && !force_update) { 1133 /* diagnostics */ 1134 iflib_rx_miss ++; 1135 iflib_rx_miss_bufs += n; 1136 } 1137 fl->ifl_cidx = nic_i; 1138 kring->nr_hwtail = nm_i; 1139 } 1140 kring->nr_kflags &= ~NKR_PENDINTR; 1141 } 1142 } 1143 /* 1144 * Second part: skip past packets that userspace has released. 1145 * (kring->nr_hwcur to head excluded), 1146 * and make the buffers available for reception. 1147 * As usual nm_i is the index in the netmap ring, 1148 * nic_i is the index in the NIC ring, and 1149 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1150 */ 1151 /* XXX not sure how this will work with multiple free lists */ 1152 nm_i = kring->nr_hwcur; 1153 1154 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1155 } 1156 1157 static void 1158 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1159 { 1160 struct ifnet *ifp = na->ifp; 1161 if_ctx_t ctx = ifp->if_softc; 1162 1163 CTX_LOCK(ctx); 1164 if (onoff) { 1165 IFDI_INTR_ENABLE(ctx); 1166 } else { 1167 IFDI_INTR_DISABLE(ctx); 1168 } 1169 CTX_UNLOCK(ctx); 1170 } 1171 1172 1173 static int 1174 iflib_netmap_attach(if_ctx_t ctx) 1175 { 1176 struct netmap_adapter na; 1177 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1178 1179 bzero(&na, sizeof(na)); 1180 1181 na.ifp = ctx->ifc_ifp; 1182 na.na_flags = NAF_BDG_MAYSLEEP; 1183 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1184 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1185 1186 na.num_tx_desc = scctx->isc_ntxd[0]; 1187 na.num_rx_desc = scctx->isc_nrxd[0]; 1188 na.nm_txsync = iflib_netmap_txsync; 1189 na.nm_rxsync = iflib_netmap_rxsync; 1190 na.nm_register = iflib_netmap_register; 1191 na.nm_intr = iflib_netmap_intr; 1192 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1193 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1194 return (netmap_attach(&na)); 1195 } 1196 1197 static void 1198 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1199 { 1200 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1201 struct netmap_slot *slot; 1202 1203 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1204 if (slot == NULL) 1205 return; 1206 if (txq->ift_sds.ifsd_map == NULL) 1207 return; 1208 1209 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1210 1211 /* 1212 * In netmap mode, set the map for the packet buffer. 1213 * NOTE: Some drivers (not this one) also need to set 1214 * the physical buffer address in the NIC ring. 1215 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1216 * netmap slot index, si 1217 */ 1218 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1219 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1220 } 1221 } 1222 1223 static void 1224 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1225 { 1226 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1227 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1228 struct netmap_slot *slot; 1229 uint32_t nm_i; 1230 1231 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1232 if (slot == NULL) 1233 return; 1234 nm_i = netmap_idx_n2k(kring, 0); 1235 netmap_fl_refill(rxq, kring, nm_i, true); 1236 } 1237 1238 static void 1239 iflib_netmap_timer_adjust(if_ctx_t ctx, uint16_t txqid, uint32_t *reset_on) 1240 { 1241 struct netmap_kring *kring; 1242 1243 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1244 1245 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1246 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1247 netmap_tx_irq(ctx->ifc_ifp, txqid); 1248 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1249 if (hz < 2000) 1250 *reset_on = 1; 1251 else 1252 *reset_on = hz / 1000; 1253 } 1254 } 1255 } 1256 1257 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1258 1259 #else 1260 #define iflib_netmap_txq_init(ctx, txq) 1261 #define iflib_netmap_rxq_init(ctx, rxq) 1262 #define iflib_netmap_detach(ifp) 1263 1264 #define iflib_netmap_attach(ctx) (0) 1265 #define netmap_rx_irq(ifp, qid, budget) (0) 1266 #define netmap_tx_irq(ifp, qid) do {} while (0) 1267 #define iflib_netmap_timer_adjust(ctx, txqid, reset_on) 1268 1269 #endif 1270 1271 #if defined(__i386__) || defined(__amd64__) 1272 static __inline void 1273 prefetch(void *x) 1274 { 1275 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1276 } 1277 static __inline void 1278 prefetch2cachelines(void *x) 1279 { 1280 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1281 #if (CACHE_LINE_SIZE < 128) 1282 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1283 #endif 1284 } 1285 #else 1286 #define prefetch(x) 1287 #define prefetch2cachelines(x) 1288 #endif 1289 1290 static void 1291 iflib_gen_mac(if_ctx_t ctx) 1292 { 1293 struct thread *td; 1294 MD5_CTX mdctx; 1295 char uuid[HOSTUUIDLEN+1]; 1296 char buf[HOSTUUIDLEN+16]; 1297 uint8_t *mac; 1298 unsigned char digest[16]; 1299 1300 td = curthread; 1301 mac = ctx->ifc_mac; 1302 uuid[HOSTUUIDLEN] = 0; 1303 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN); 1304 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev)); 1305 /* 1306 * Generate a pseudo-random, deterministic MAC 1307 * address based on the UUID and unit number. 1308 * The FreeBSD Foundation OUI of 58-9C-FC is used. 1309 */ 1310 MD5Init(&mdctx); 1311 MD5Update(&mdctx, buf, strlen(buf)); 1312 MD5Final(digest, &mdctx); 1313 1314 mac[0] = 0x58; 1315 mac[1] = 0x9C; 1316 mac[2] = 0xFC; 1317 mac[3] = digest[0]; 1318 mac[4] = digest[1]; 1319 mac[5] = digest[2]; 1320 } 1321 1322 static void 1323 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1324 { 1325 iflib_fl_t fl; 1326 1327 fl = &rxq->ifr_fl[flid]; 1328 iru->iru_paddrs = fl->ifl_bus_addrs; 1329 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1330 iru->iru_idxs = fl->ifl_rxd_idxs; 1331 iru->iru_qsidx = rxq->ifr_id; 1332 iru->iru_buf_size = fl->ifl_buf_size; 1333 iru->iru_flidx = fl->ifl_id; 1334 } 1335 1336 static void 1337 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1338 { 1339 if (err) 1340 return; 1341 *(bus_addr_t *) arg = segs[0].ds_addr; 1342 } 1343 1344 int 1345 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1346 { 1347 int err; 1348 if_shared_ctx_t sctx = ctx->ifc_sctx; 1349 device_t dev = ctx->ifc_dev; 1350 1351 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1352 1353 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1354 sctx->isc_q_align, 0, /* alignment, bounds */ 1355 BUS_SPACE_MAXADDR, /* lowaddr */ 1356 BUS_SPACE_MAXADDR, /* highaddr */ 1357 NULL, NULL, /* filter, filterarg */ 1358 size, /* maxsize */ 1359 1, /* nsegments */ 1360 size, /* maxsegsize */ 1361 BUS_DMA_ALLOCNOW, /* flags */ 1362 NULL, /* lockfunc */ 1363 NULL, /* lockarg */ 1364 &dma->idi_tag); 1365 if (err) { 1366 device_printf(dev, 1367 "%s: bus_dma_tag_create failed: %d\n", 1368 __func__, err); 1369 goto fail_0; 1370 } 1371 1372 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1373 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1374 if (err) { 1375 device_printf(dev, 1376 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1377 __func__, (uintmax_t)size, err); 1378 goto fail_1; 1379 } 1380 1381 dma->idi_paddr = IF_BAD_DMA; 1382 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1383 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1384 if (err || dma->idi_paddr == IF_BAD_DMA) { 1385 device_printf(dev, 1386 "%s: bus_dmamap_load failed: %d\n", 1387 __func__, err); 1388 goto fail_2; 1389 } 1390 1391 dma->idi_size = size; 1392 return (0); 1393 1394 fail_2: 1395 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1396 fail_1: 1397 bus_dma_tag_destroy(dma->idi_tag); 1398 fail_0: 1399 dma->idi_tag = NULL; 1400 1401 return (err); 1402 } 1403 1404 int 1405 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1406 { 1407 int i, err; 1408 iflib_dma_info_t *dmaiter; 1409 1410 dmaiter = dmalist; 1411 for (i = 0; i < count; i++, dmaiter++) { 1412 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1413 break; 1414 } 1415 if (err) 1416 iflib_dma_free_multi(dmalist, i); 1417 return (err); 1418 } 1419 1420 void 1421 iflib_dma_free(iflib_dma_info_t dma) 1422 { 1423 if (dma->idi_tag == NULL) 1424 return; 1425 if (dma->idi_paddr != IF_BAD_DMA) { 1426 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1427 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1428 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1429 dma->idi_paddr = IF_BAD_DMA; 1430 } 1431 if (dma->idi_vaddr != NULL) { 1432 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1433 dma->idi_vaddr = NULL; 1434 } 1435 bus_dma_tag_destroy(dma->idi_tag); 1436 dma->idi_tag = NULL; 1437 } 1438 1439 void 1440 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1441 { 1442 int i; 1443 iflib_dma_info_t *dmaiter = dmalist; 1444 1445 for (i = 0; i < count; i++, dmaiter++) 1446 iflib_dma_free(*dmaiter); 1447 } 1448 1449 #ifdef EARLY_AP_STARTUP 1450 static const int iflib_started = 1; 1451 #else 1452 /* 1453 * We used to abuse the smp_started flag to decide if the queues have been 1454 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1455 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1456 * is set. Run a SYSINIT() strictly after that to just set a usable 1457 * completion flag. 1458 */ 1459 1460 static int iflib_started; 1461 1462 static void 1463 iflib_record_started(void *arg) 1464 { 1465 iflib_started = 1; 1466 } 1467 1468 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1469 iflib_record_started, NULL); 1470 #endif 1471 1472 static int 1473 iflib_fast_intr(void *arg) 1474 { 1475 iflib_filter_info_t info = arg; 1476 struct grouptask *gtask = info->ifi_task; 1477 if (!iflib_started) 1478 return (FILTER_HANDLED); 1479 1480 DBG_COUNTER_INC(fast_intrs); 1481 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1482 return (FILTER_HANDLED); 1483 1484 GROUPTASK_ENQUEUE(gtask); 1485 return (FILTER_HANDLED); 1486 } 1487 1488 static int 1489 iflib_fast_intr_rxtx(void *arg) 1490 { 1491 iflib_filter_info_t info = arg; 1492 struct grouptask *gtask = info->ifi_task; 1493 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1494 if_ctx_t ctx = NULL;; 1495 int i, cidx; 1496 1497 if (!iflib_started) 1498 return (FILTER_HANDLED); 1499 1500 DBG_COUNTER_INC(fast_intrs); 1501 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1502 return (FILTER_HANDLED); 1503 1504 MPASS(rxq->ifr_ntxqirq); 1505 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1506 qidx_t txqid = rxq->ifr_txqid[i]; 1507 1508 ctx = rxq->ifr_ctx; 1509 1510 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1511 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1512 continue; 1513 } 1514 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1515 } 1516 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1517 cidx = rxq->ifr_cq_cidx; 1518 else 1519 cidx = rxq->ifr_fl[0].ifl_cidx; 1520 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1521 GROUPTASK_ENQUEUE(gtask); 1522 else 1523 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1524 return (FILTER_HANDLED); 1525 } 1526 1527 1528 static int 1529 iflib_fast_intr_ctx(void *arg) 1530 { 1531 iflib_filter_info_t info = arg; 1532 struct grouptask *gtask = info->ifi_task; 1533 1534 if (!iflib_started) 1535 return (FILTER_HANDLED); 1536 1537 DBG_COUNTER_INC(fast_intrs); 1538 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1539 return (FILTER_HANDLED); 1540 1541 GROUPTASK_ENQUEUE(gtask); 1542 return (FILTER_HANDLED); 1543 } 1544 1545 static int 1546 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1547 driver_filter_t filter, driver_intr_t handler, void *arg, 1548 const char *name) 1549 { 1550 int rc, flags; 1551 struct resource *res; 1552 void *tag = NULL; 1553 device_t dev = ctx->ifc_dev; 1554 1555 flags = RF_ACTIVE; 1556 if (ctx->ifc_flags & IFC_LEGACY) 1557 flags |= RF_SHAREABLE; 1558 MPASS(rid < 512); 1559 irq->ii_rid = rid; 1560 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1561 if (res == NULL) { 1562 device_printf(dev, 1563 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1564 return (ENOMEM); 1565 } 1566 irq->ii_res = res; 1567 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1568 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1569 filter, handler, arg, &tag); 1570 if (rc != 0) { 1571 device_printf(dev, 1572 "failed to setup interrupt for rid %d, name %s: %d\n", 1573 rid, name ? name : "unknown", rc); 1574 return (rc); 1575 } else if (name) 1576 bus_describe_intr(dev, res, tag, "%s", name); 1577 1578 irq->ii_tag = tag; 1579 return (0); 1580 } 1581 1582 1583 /********************************************************************* 1584 * 1585 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1586 * the information needed to transmit a packet on the wire. This is 1587 * called only once at attach, setup is done every reset. 1588 * 1589 **********************************************************************/ 1590 1591 static int 1592 iflib_txsd_alloc(iflib_txq_t txq) 1593 { 1594 if_ctx_t ctx = txq->ift_ctx; 1595 if_shared_ctx_t sctx = ctx->ifc_sctx; 1596 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1597 device_t dev = ctx->ifc_dev; 1598 bus_size_t tsomaxsize; 1599 int err, nsegments, ntsosegments; 1600 1601 nsegments = scctx->isc_tx_nsegments; 1602 ntsosegments = scctx->isc_tx_tso_segments_max; 1603 tsomaxsize = scctx->isc_tx_tso_size_max; 1604 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1605 tsomaxsize += sizeof(struct ether_vlan_header); 1606 MPASS(scctx->isc_ntxd[0] > 0); 1607 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1608 MPASS(nsegments > 0); 1609 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1610 MPASS(ntsosegments > 0); 1611 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1612 } 1613 1614 /* 1615 * Setup DMA descriptor areas. 1616 */ 1617 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1618 1, 0, /* alignment, bounds */ 1619 BUS_SPACE_MAXADDR, /* lowaddr */ 1620 BUS_SPACE_MAXADDR, /* highaddr */ 1621 NULL, NULL, /* filter, filterarg */ 1622 sctx->isc_tx_maxsize, /* maxsize */ 1623 nsegments, /* nsegments */ 1624 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1625 0, /* flags */ 1626 NULL, /* lockfunc */ 1627 NULL, /* lockfuncarg */ 1628 &txq->ift_desc_tag))) { 1629 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1630 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1631 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1632 goto fail; 1633 } 1634 if ((if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) & 1635 (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1636 1, 0, /* alignment, bounds */ 1637 BUS_SPACE_MAXADDR, /* lowaddr */ 1638 BUS_SPACE_MAXADDR, /* highaddr */ 1639 NULL, NULL, /* filter, filterarg */ 1640 tsomaxsize, /* maxsize */ 1641 ntsosegments, /* nsegments */ 1642 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1643 0, /* flags */ 1644 NULL, /* lockfunc */ 1645 NULL, /* lockfuncarg */ 1646 &txq->ift_tso_desc_tag))) { 1647 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1648 1649 goto fail; 1650 } 1651 if (!(txq->ift_sds.ifsd_flags = 1652 (uint8_t *) malloc(sizeof(uint8_t) * 1653 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1654 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1655 err = ENOMEM; 1656 goto fail; 1657 } 1658 if (!(txq->ift_sds.ifsd_m = 1659 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1660 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1661 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1662 err = ENOMEM; 1663 goto fail; 1664 } 1665 1666 /* Create the descriptor buffer dma maps */ 1667 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1668 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1669 return (0); 1670 1671 if (!(txq->ift_sds.ifsd_map = 1672 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1673 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1674 err = ENOMEM; 1675 goto fail; 1676 } 1677 1678 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1679 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1680 if (err != 0) { 1681 device_printf(dev, "Unable to create TX DMA map\n"); 1682 goto fail; 1683 } 1684 } 1685 #endif 1686 return (0); 1687 fail: 1688 /* We free all, it handles case where we are in the middle */ 1689 iflib_tx_structures_free(ctx); 1690 return (err); 1691 } 1692 1693 static void 1694 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1695 { 1696 bus_dmamap_t map; 1697 1698 map = NULL; 1699 if (txq->ift_sds.ifsd_map != NULL) 1700 map = txq->ift_sds.ifsd_map[i]; 1701 if (map != NULL) { 1702 bus_dmamap_unload(txq->ift_desc_tag, map); 1703 bus_dmamap_destroy(txq->ift_desc_tag, map); 1704 txq->ift_sds.ifsd_map[i] = NULL; 1705 } 1706 } 1707 1708 static void 1709 iflib_txq_destroy(iflib_txq_t txq) 1710 { 1711 if_ctx_t ctx = txq->ift_ctx; 1712 1713 for (int i = 0; i < txq->ift_size; i++) 1714 iflib_txsd_destroy(ctx, txq, i); 1715 if (txq->ift_sds.ifsd_map != NULL) { 1716 free(txq->ift_sds.ifsd_map, M_IFLIB); 1717 txq->ift_sds.ifsd_map = NULL; 1718 } 1719 if (txq->ift_sds.ifsd_m != NULL) { 1720 free(txq->ift_sds.ifsd_m, M_IFLIB); 1721 txq->ift_sds.ifsd_m = NULL; 1722 } 1723 if (txq->ift_sds.ifsd_flags != NULL) { 1724 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1725 txq->ift_sds.ifsd_flags = NULL; 1726 } 1727 if (txq->ift_desc_tag != NULL) { 1728 bus_dma_tag_destroy(txq->ift_desc_tag); 1729 txq->ift_desc_tag = NULL; 1730 } 1731 if (txq->ift_tso_desc_tag != NULL) { 1732 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1733 txq->ift_tso_desc_tag = NULL; 1734 } 1735 } 1736 1737 static void 1738 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1739 { 1740 struct mbuf **mp; 1741 1742 mp = &txq->ift_sds.ifsd_m[i]; 1743 if (*mp == NULL) 1744 return; 1745 1746 if (txq->ift_sds.ifsd_map != NULL) { 1747 bus_dmamap_sync(txq->ift_desc_tag, 1748 txq->ift_sds.ifsd_map[i], 1749 BUS_DMASYNC_POSTWRITE); 1750 bus_dmamap_unload(txq->ift_desc_tag, 1751 txq->ift_sds.ifsd_map[i]); 1752 } 1753 m_free(*mp); 1754 DBG_COUNTER_INC(tx_frees); 1755 *mp = NULL; 1756 } 1757 1758 static int 1759 iflib_txq_setup(iflib_txq_t txq) 1760 { 1761 if_ctx_t ctx = txq->ift_ctx; 1762 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1763 iflib_dma_info_t di; 1764 int i; 1765 1766 /* Set number of descriptors available */ 1767 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1768 /* XXX make configurable */ 1769 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1770 1771 /* Reset indices */ 1772 txq->ift_cidx_processed = 0; 1773 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1774 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1775 1776 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1777 bzero((void *)di->idi_vaddr, di->idi_size); 1778 1779 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1780 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1781 bus_dmamap_sync(di->idi_tag, di->idi_map, 1782 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1783 return (0); 1784 } 1785 1786 /********************************************************************* 1787 * 1788 * Allocate memory for rx_buffer structures. Since we use one 1789 * rx_buffer per received packet, the maximum number of rx_buffer's 1790 * that we'll need is equal to the number of receive descriptors 1791 * that we've allocated. 1792 * 1793 **********************************************************************/ 1794 static int 1795 iflib_rxsd_alloc(iflib_rxq_t rxq) 1796 { 1797 if_ctx_t ctx = rxq->ifr_ctx; 1798 if_shared_ctx_t sctx = ctx->ifc_sctx; 1799 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1800 device_t dev = ctx->ifc_dev; 1801 iflib_fl_t fl; 1802 int err; 1803 1804 MPASS(scctx->isc_nrxd[0] > 0); 1805 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1806 1807 fl = rxq->ifr_fl; 1808 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1809 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1810 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1811 1, 0, /* alignment, bounds */ 1812 BUS_SPACE_MAXADDR, /* lowaddr */ 1813 BUS_SPACE_MAXADDR, /* highaddr */ 1814 NULL, NULL, /* filter, filterarg */ 1815 sctx->isc_rx_maxsize, /* maxsize */ 1816 sctx->isc_rx_nsegments, /* nsegments */ 1817 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1818 0, /* flags */ 1819 NULL, /* lockfunc */ 1820 NULL, /* lockarg */ 1821 &fl->ifl_desc_tag); 1822 if (err) { 1823 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1824 __func__, err); 1825 goto fail; 1826 } 1827 if (!(fl->ifl_sds.ifsd_flags = 1828 (uint8_t *) malloc(sizeof(uint8_t) * 1829 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1830 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1831 err = ENOMEM; 1832 goto fail; 1833 } 1834 if (!(fl->ifl_sds.ifsd_m = 1835 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1836 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1837 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1838 err = ENOMEM; 1839 goto fail; 1840 } 1841 if (!(fl->ifl_sds.ifsd_cl = 1842 (caddr_t *) malloc(sizeof(caddr_t) * 1843 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1844 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1845 err = ENOMEM; 1846 goto fail; 1847 } 1848 1849 /* Create the descriptor buffer dma maps */ 1850 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1851 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1852 continue; 1853 1854 if (!(fl->ifl_sds.ifsd_map = 1855 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1856 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1857 err = ENOMEM; 1858 goto fail; 1859 } 1860 1861 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1862 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1863 if (err != 0) { 1864 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1865 goto fail; 1866 } 1867 } 1868 #endif 1869 } 1870 return (0); 1871 1872 fail: 1873 iflib_rx_structures_free(ctx); 1874 return (err); 1875 } 1876 1877 1878 /* 1879 * Internal service routines 1880 */ 1881 1882 struct rxq_refill_cb_arg { 1883 int error; 1884 bus_dma_segment_t seg; 1885 int nseg; 1886 }; 1887 1888 static void 1889 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1890 { 1891 struct rxq_refill_cb_arg *cb_arg = arg; 1892 1893 cb_arg->error = error; 1894 cb_arg->seg = segs[0]; 1895 cb_arg->nseg = nseg; 1896 } 1897 1898 1899 #ifdef ACPI_DMAR 1900 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1901 #else 1902 #define IS_DMAR(ctx) (0) 1903 #endif 1904 1905 /** 1906 * rxq_refill - refill an rxq free-buffer list 1907 * @ctx: the iflib context 1908 * @rxq: the free-list to refill 1909 * @n: the number of new buffers to allocate 1910 * 1911 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1912 * The caller must assure that @n does not exceed the queue's capacity. 1913 */ 1914 static void 1915 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1916 { 1917 struct mbuf *m; 1918 int idx, frag_idx = fl->ifl_fragidx; 1919 int pidx = fl->ifl_pidx; 1920 caddr_t cl, *sd_cl; 1921 struct mbuf **sd_m; 1922 uint8_t *sd_flags; 1923 struct if_rxd_update iru; 1924 bus_dmamap_t *sd_map; 1925 int n, i = 0; 1926 uint64_t bus_addr; 1927 int err; 1928 qidx_t credits; 1929 1930 sd_m = fl->ifl_sds.ifsd_m; 1931 sd_map = fl->ifl_sds.ifsd_map; 1932 sd_cl = fl->ifl_sds.ifsd_cl; 1933 sd_flags = fl->ifl_sds.ifsd_flags; 1934 idx = pidx; 1935 credits = fl->ifl_credits; 1936 1937 n = count; 1938 MPASS(n > 0); 1939 MPASS(credits + n <= fl->ifl_size); 1940 1941 if (pidx < fl->ifl_cidx) 1942 MPASS(pidx + n <= fl->ifl_cidx); 1943 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1944 MPASS(fl->ifl_gen == 0); 1945 if (pidx > fl->ifl_cidx) 1946 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1947 1948 DBG_COUNTER_INC(fl_refills); 1949 if (n > 8) 1950 DBG_COUNTER_INC(fl_refills_large); 1951 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1952 while (n--) { 1953 /* 1954 * We allocate an uninitialized mbuf + cluster, mbuf is 1955 * initialized after rx. 1956 * 1957 * If the cluster is still set then we know a minimum sized packet was received 1958 */ 1959 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1960 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1961 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1962 if ((cl = sd_cl[frag_idx]) == NULL) { 1963 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1964 break; 1965 #if MEMORY_LOGGING 1966 fl->ifl_cl_enqueued++; 1967 #endif 1968 } 1969 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1970 break; 1971 } 1972 #if MEMORY_LOGGING 1973 fl->ifl_m_enqueued++; 1974 #endif 1975 1976 DBG_COUNTER_INC(rx_allocs); 1977 #if defined(__i386__) || defined(__amd64__) 1978 if (!IS_DMAR(ctx)) { 1979 bus_addr = pmap_kextract((vm_offset_t)cl); 1980 } else 1981 #endif 1982 { 1983 struct rxq_refill_cb_arg cb_arg; 1984 1985 cb_arg.error = 0; 1986 MPASS(sd_map != NULL); 1987 MPASS(sd_map[frag_idx] != NULL); 1988 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1989 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1990 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 1991 BUS_DMASYNC_PREREAD); 1992 1993 if (err != 0 || cb_arg.error) { 1994 /* 1995 * !zone_pack ? 1996 */ 1997 if (fl->ifl_zone == zone_pack) 1998 uma_zfree(fl->ifl_zone, cl); 1999 m_free(m); 2000 n = 0; 2001 goto done; 2002 } 2003 bus_addr = cb_arg.seg.ds_addr; 2004 } 2005 bit_set(fl->ifl_rx_bitmap, frag_idx); 2006 sd_flags[frag_idx] |= RX_SW_DESC_INUSE; 2007 2008 MPASS(sd_m[frag_idx] == NULL); 2009 sd_cl[frag_idx] = cl; 2010 sd_m[frag_idx] = m; 2011 fl->ifl_rxd_idxs[i] = frag_idx; 2012 fl->ifl_bus_addrs[i] = bus_addr; 2013 fl->ifl_vm_addrs[i] = cl; 2014 credits++; 2015 i++; 2016 MPASS(credits <= fl->ifl_size); 2017 if (++idx == fl->ifl_size) { 2018 fl->ifl_gen = 1; 2019 idx = 0; 2020 } 2021 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2022 iru.iru_pidx = pidx; 2023 iru.iru_count = i; 2024 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2025 i = 0; 2026 pidx = idx; 2027 fl->ifl_pidx = idx; 2028 fl->ifl_credits = credits; 2029 } 2030 2031 } 2032 done: 2033 if (i) { 2034 iru.iru_pidx = pidx; 2035 iru.iru_count = i; 2036 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2037 fl->ifl_pidx = idx; 2038 fl->ifl_credits = credits; 2039 } 2040 DBG_COUNTER_INC(rxd_flush); 2041 if (fl->ifl_pidx == 0) 2042 pidx = fl->ifl_size - 1; 2043 else 2044 pidx = fl->ifl_pidx - 1; 2045 2046 if (sd_map) 2047 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2048 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2049 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2050 fl->ifl_fragidx = frag_idx; 2051 } 2052 2053 static __inline void 2054 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2055 { 2056 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2057 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2058 #ifdef INVARIANTS 2059 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2060 #endif 2061 2062 MPASS(fl->ifl_credits <= fl->ifl_size); 2063 MPASS(reclaimable == delta); 2064 2065 if (reclaimable > 0) 2066 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2067 } 2068 2069 static void 2070 iflib_fl_bufs_free(iflib_fl_t fl) 2071 { 2072 iflib_dma_info_t idi = fl->ifl_ifdi; 2073 uint32_t i; 2074 2075 for (i = 0; i < fl->ifl_size; i++) { 2076 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2077 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 2078 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2079 2080 if (*sd_flags & RX_SW_DESC_INUSE) { 2081 if (fl->ifl_sds.ifsd_map != NULL) { 2082 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 2083 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 2084 if (fl->ifl_rxq->ifr_ctx->ifc_in_detach) 2085 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 2086 } 2087 if (*sd_m != NULL) { 2088 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2089 uma_zfree(zone_mbuf, *sd_m); 2090 } 2091 if (*sd_cl != NULL) 2092 uma_zfree(fl->ifl_zone, *sd_cl); 2093 *sd_flags = 0; 2094 } else { 2095 MPASS(*sd_cl == NULL); 2096 MPASS(*sd_m == NULL); 2097 } 2098 #if MEMORY_LOGGING 2099 fl->ifl_m_dequeued++; 2100 fl->ifl_cl_dequeued++; 2101 #endif 2102 *sd_cl = NULL; 2103 *sd_m = NULL; 2104 } 2105 #ifdef INVARIANTS 2106 for (i = 0; i < fl->ifl_size; i++) { 2107 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 2108 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2109 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2110 } 2111 #endif 2112 /* 2113 * Reset free list values 2114 */ 2115 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2116 bzero(idi->idi_vaddr, idi->idi_size); 2117 } 2118 2119 /********************************************************************* 2120 * 2121 * Initialize a receive ring and its buffers. 2122 * 2123 **********************************************************************/ 2124 static int 2125 iflib_fl_setup(iflib_fl_t fl) 2126 { 2127 iflib_rxq_t rxq = fl->ifl_rxq; 2128 if_ctx_t ctx = rxq->ifr_ctx; 2129 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2130 2131 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2132 /* 2133 ** Free current RX buffer structs and their mbufs 2134 */ 2135 iflib_fl_bufs_free(fl); 2136 /* Now replenish the mbufs */ 2137 MPASS(fl->ifl_credits == 0); 2138 /* 2139 * XXX don't set the max_frame_size to larger 2140 * than the hardware can handle 2141 */ 2142 if (sctx->isc_max_frame_size <= 2048) 2143 fl->ifl_buf_size = MCLBYTES; 2144 #ifndef CONTIGMALLOC_WORKS 2145 else 2146 fl->ifl_buf_size = MJUMPAGESIZE; 2147 #else 2148 else if (sctx->isc_max_frame_size <= 4096) 2149 fl->ifl_buf_size = MJUMPAGESIZE; 2150 else if (sctx->isc_max_frame_size <= 9216) 2151 fl->ifl_buf_size = MJUM9BYTES; 2152 else 2153 fl->ifl_buf_size = MJUM16BYTES; 2154 #endif 2155 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2156 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2157 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2158 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2159 2160 2161 /* avoid pre-allocating zillions of clusters to an idle card 2162 * potentially speeding up attach 2163 */ 2164 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2165 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2166 if (min(128, fl->ifl_size) != fl->ifl_credits) 2167 return (ENOBUFS); 2168 /* 2169 * handle failure 2170 */ 2171 MPASS(rxq != NULL); 2172 MPASS(fl->ifl_ifdi != NULL); 2173 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2174 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2175 return (0); 2176 } 2177 2178 /********************************************************************* 2179 * 2180 * Free receive ring data structures 2181 * 2182 **********************************************************************/ 2183 static void 2184 iflib_rx_sds_free(iflib_rxq_t rxq) 2185 { 2186 iflib_fl_t fl; 2187 int i; 2188 2189 if (rxq->ifr_fl != NULL) { 2190 for (i = 0; i < rxq->ifr_nfl; i++) { 2191 fl = &rxq->ifr_fl[i]; 2192 if (fl->ifl_desc_tag != NULL) { 2193 bus_dma_tag_destroy(fl->ifl_desc_tag); 2194 fl->ifl_desc_tag = NULL; 2195 } 2196 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2197 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2198 /* XXX destroy maps first */ 2199 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2200 fl->ifl_sds.ifsd_m = NULL; 2201 fl->ifl_sds.ifsd_cl = NULL; 2202 fl->ifl_sds.ifsd_map = NULL; 2203 } 2204 free(rxq->ifr_fl, M_IFLIB); 2205 rxq->ifr_fl = NULL; 2206 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2207 } 2208 } 2209 2210 /* 2211 * MI independent logic 2212 * 2213 */ 2214 static void 2215 iflib_timer(void *arg) 2216 { 2217 iflib_txq_t txq = arg; 2218 if_ctx_t ctx = txq->ift_ctx; 2219 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2220 uint64_t this_tick = ticks; 2221 uint32_t reset_on = hz / 2; 2222 2223 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2224 return; 2225 /* 2226 ** Check on the state of the TX queue(s), this 2227 ** can be done without the lock because its RO 2228 ** and the HUNG state will be static if set. 2229 */ 2230 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2231 txq->ift_last_timer_tick = this_tick; 2232 IFDI_TIMER(ctx, txq->ift_id); 2233 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2234 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2235 (sctx->isc_pause_frames == 0))) 2236 goto hung; 2237 2238 if (ifmp_ring_is_stalled(txq->ift_br)) 2239 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2240 txq->ift_cleaned_prev = txq->ift_cleaned; 2241 } 2242 #ifdef DEV_NETMAP 2243 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2244 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on); 2245 #endif 2246 /* handle any laggards */ 2247 if (txq->ift_db_pending) 2248 GROUPTASK_ENQUEUE(&txq->ift_task); 2249 2250 sctx->isc_pause_frames = 0; 2251 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2252 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2253 return; 2254 hung: 2255 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2256 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2257 STATE_LOCK(ctx); 2258 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2259 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2260 iflib_admin_intr_deferred(ctx); 2261 STATE_UNLOCK(ctx); 2262 } 2263 2264 static void 2265 iflib_init_locked(if_ctx_t ctx) 2266 { 2267 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2268 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2269 if_t ifp = ctx->ifc_ifp; 2270 iflib_fl_t fl; 2271 iflib_txq_t txq; 2272 iflib_rxq_t rxq; 2273 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2274 2275 2276 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2277 IFDI_INTR_DISABLE(ctx); 2278 2279 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2280 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2281 /* Set hardware offload abilities */ 2282 if_clearhwassist(ifp); 2283 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2284 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2285 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2286 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2287 if (if_getcapenable(ifp) & IFCAP_TSO4) 2288 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2289 if (if_getcapenable(ifp) & IFCAP_TSO6) 2290 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2291 2292 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2293 CALLOUT_LOCK(txq); 2294 callout_stop(&txq->ift_timer); 2295 CALLOUT_UNLOCK(txq); 2296 iflib_netmap_txq_init(ctx, txq); 2297 } 2298 #ifdef INVARIANTS 2299 i = if_getdrvflags(ifp); 2300 #endif 2301 IFDI_INIT(ctx); 2302 MPASS(if_getdrvflags(ifp) == i); 2303 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2304 /* XXX this should really be done on a per-queue basis */ 2305 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2306 MPASS(rxq->ifr_id == i); 2307 iflib_netmap_rxq_init(ctx, rxq); 2308 continue; 2309 } 2310 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2311 if (iflib_fl_setup(fl)) { 2312 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2313 goto done; 2314 } 2315 } 2316 } 2317 done: 2318 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2319 IFDI_INTR_ENABLE(ctx); 2320 txq = ctx->ifc_txqs; 2321 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2322 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2323 txq->ift_timer.c_cpu); 2324 } 2325 2326 static int 2327 iflib_media_change(if_t ifp) 2328 { 2329 if_ctx_t ctx = if_getsoftc(ifp); 2330 int err; 2331 2332 CTX_LOCK(ctx); 2333 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2334 iflib_init_locked(ctx); 2335 CTX_UNLOCK(ctx); 2336 return (err); 2337 } 2338 2339 static void 2340 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2341 { 2342 if_ctx_t ctx = if_getsoftc(ifp); 2343 2344 CTX_LOCK(ctx); 2345 IFDI_UPDATE_ADMIN_STATUS(ctx); 2346 IFDI_MEDIA_STATUS(ctx, ifmr); 2347 CTX_UNLOCK(ctx); 2348 } 2349 2350 void 2351 iflib_stop(if_ctx_t ctx) 2352 { 2353 iflib_txq_t txq = ctx->ifc_txqs; 2354 iflib_rxq_t rxq = ctx->ifc_rxqs; 2355 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2356 iflib_dma_info_t di; 2357 iflib_fl_t fl; 2358 int i, j; 2359 2360 /* Tell the stack that the interface is no longer active */ 2361 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2362 2363 IFDI_INTR_DISABLE(ctx); 2364 DELAY(1000); 2365 IFDI_STOP(ctx); 2366 DELAY(1000); 2367 2368 iflib_debug_reset(); 2369 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2370 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2371 /* make sure all transmitters have completed before proceeding XXX */ 2372 2373 CALLOUT_LOCK(txq); 2374 callout_stop(&txq->ift_timer); 2375 CALLOUT_UNLOCK(txq); 2376 2377 /* clean any enqueued buffers */ 2378 iflib_ifmp_purge(txq); 2379 /* Free any existing tx buffers. */ 2380 for (j = 0; j < txq->ift_size; j++) { 2381 iflib_txsd_free(ctx, txq, j); 2382 } 2383 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2384 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2385 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2386 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2387 txq->ift_pullups = 0; 2388 ifmp_ring_reset_stats(txq->ift_br); 2389 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2390 bzero((void *)di->idi_vaddr, di->idi_size); 2391 } 2392 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2393 /* make sure all transmitters have completed before proceeding XXX */ 2394 2395 for (j = 0, di = rxq->ifr_ifdi; j < rxq->ifr_nfl; j++, di++) 2396 bzero((void *)di->idi_vaddr, di->idi_size); 2397 /* also resets the free lists pidx/cidx */ 2398 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2399 iflib_fl_bufs_free(fl); 2400 } 2401 } 2402 2403 static inline caddr_t 2404 calc_next_rxd(iflib_fl_t fl, int cidx) 2405 { 2406 qidx_t size; 2407 int nrxd; 2408 caddr_t start, end, cur, next; 2409 2410 nrxd = fl->ifl_size; 2411 size = fl->ifl_rxd_size; 2412 start = fl->ifl_ifdi->idi_vaddr; 2413 2414 if (__predict_false(size == 0)) 2415 return (start); 2416 cur = start + size*cidx; 2417 end = start + size*nrxd; 2418 next = CACHE_PTR_NEXT(cur); 2419 return (next < end ? next : start); 2420 } 2421 2422 static inline void 2423 prefetch_pkts(iflib_fl_t fl, int cidx) 2424 { 2425 int nextptr; 2426 int nrxd = fl->ifl_size; 2427 caddr_t next_rxd; 2428 2429 2430 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2431 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2432 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2433 next_rxd = calc_next_rxd(fl, cidx); 2434 prefetch(next_rxd); 2435 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2436 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2437 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2438 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2439 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2440 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2441 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2442 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2443 } 2444 2445 static void 2446 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2447 { 2448 int flid, cidx; 2449 bus_dmamap_t map; 2450 iflib_fl_t fl; 2451 iflib_dma_info_t di; 2452 int next; 2453 2454 map = NULL; 2455 flid = irf->irf_flid; 2456 cidx = irf->irf_idx; 2457 fl = &rxq->ifr_fl[flid]; 2458 sd->ifsd_fl = fl; 2459 sd->ifsd_cidx = cidx; 2460 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2461 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2462 fl->ifl_credits--; 2463 #if MEMORY_LOGGING 2464 fl->ifl_m_dequeued++; 2465 #endif 2466 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2467 prefetch_pkts(fl, cidx); 2468 if (fl->ifl_sds.ifsd_map != NULL) { 2469 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2470 prefetch(&fl->ifl_sds.ifsd_map[next]); 2471 map = fl->ifl_sds.ifsd_map[cidx]; 2472 di = fl->ifl_ifdi; 2473 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2474 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2475 bus_dmamap_sync(di->idi_tag, di->idi_map, 2476 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2477 2478 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2479 MPASS(fl->ifl_cidx == cidx); 2480 if (unload) 2481 bus_dmamap_unload(fl->ifl_desc_tag, map); 2482 } 2483 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2484 if (__predict_false(fl->ifl_cidx == 0)) 2485 fl->ifl_gen = 0; 2486 if (map != NULL) 2487 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2488 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2489 bit_clear(fl->ifl_rx_bitmap, cidx); 2490 } 2491 2492 static struct mbuf * 2493 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2494 { 2495 int i, padlen , flags; 2496 struct mbuf *m, *mh, *mt; 2497 caddr_t cl; 2498 2499 i = 0; 2500 mh = NULL; 2501 do { 2502 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2503 2504 MPASS(*sd->ifsd_cl != NULL); 2505 MPASS(*sd->ifsd_m != NULL); 2506 2507 /* Don't include zero-length frags */ 2508 if (ri->iri_frags[i].irf_len == 0) { 2509 /* XXX we can save the cluster here, but not the mbuf */ 2510 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2511 m_free(*sd->ifsd_m); 2512 *sd->ifsd_m = NULL; 2513 continue; 2514 } 2515 m = *sd->ifsd_m; 2516 *sd->ifsd_m = NULL; 2517 if (mh == NULL) { 2518 flags = M_PKTHDR|M_EXT; 2519 mh = mt = m; 2520 padlen = ri->iri_pad; 2521 } else { 2522 flags = M_EXT; 2523 mt->m_next = m; 2524 mt = m; 2525 /* assuming padding is only on the first fragment */ 2526 padlen = 0; 2527 } 2528 cl = *sd->ifsd_cl; 2529 *sd->ifsd_cl = NULL; 2530 2531 /* Can these two be made one ? */ 2532 m_init(m, M_NOWAIT, MT_DATA, flags); 2533 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2534 /* 2535 * These must follow m_init and m_cljset 2536 */ 2537 m->m_data += padlen; 2538 ri->iri_len -= padlen; 2539 m->m_len = ri->iri_frags[i].irf_len; 2540 } while (++i < ri->iri_nfrags); 2541 2542 return (mh); 2543 } 2544 2545 /* 2546 * Process one software descriptor 2547 */ 2548 static struct mbuf * 2549 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2550 { 2551 struct if_rxsd sd; 2552 struct mbuf *m; 2553 2554 /* should I merge this back in now that the two paths are basically duplicated? */ 2555 if (ri->iri_nfrags == 1 && 2556 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2557 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2558 m = *sd.ifsd_m; 2559 *sd.ifsd_m = NULL; 2560 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2561 #ifndef __NO_STRICT_ALIGNMENT 2562 if (!IP_ALIGNED(m)) 2563 m->m_data += 2; 2564 #endif 2565 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2566 m->m_len = ri->iri_frags[0].irf_len; 2567 } else { 2568 m = assemble_segments(rxq, ri, &sd); 2569 } 2570 m->m_pkthdr.len = ri->iri_len; 2571 m->m_pkthdr.rcvif = ri->iri_ifp; 2572 m->m_flags |= ri->iri_flags; 2573 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2574 m->m_pkthdr.flowid = ri->iri_flowid; 2575 M_HASHTYPE_SET(m, ri->iri_rsstype); 2576 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2577 m->m_pkthdr.csum_data = ri->iri_csum_data; 2578 return (m); 2579 } 2580 2581 #if defined(INET6) || defined(INET) 2582 static void 2583 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2584 { 2585 CURVNET_SET(lc->ifp->if_vnet); 2586 #if defined(INET6) 2587 *v6 = VNET(ip6_forwarding); 2588 #endif 2589 #if defined(INET) 2590 *v4 = VNET(ipforwarding); 2591 #endif 2592 CURVNET_RESTORE(); 2593 } 2594 2595 /* 2596 * Returns true if it's possible this packet could be LROed. 2597 * if it returns false, it is guaranteed that tcp_lro_rx() 2598 * would not return zero. 2599 */ 2600 static bool 2601 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2602 { 2603 struct ether_header *eh; 2604 uint16_t eh_type; 2605 2606 eh = mtod(m, struct ether_header *); 2607 eh_type = ntohs(eh->ether_type); 2608 switch (eh_type) { 2609 #if defined(INET6) 2610 case ETHERTYPE_IPV6: 2611 return !v6_forwarding; 2612 #endif 2613 #if defined (INET) 2614 case ETHERTYPE_IP: 2615 return !v4_forwarding; 2616 #endif 2617 } 2618 2619 return false; 2620 } 2621 #else 2622 static void 2623 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2624 { 2625 } 2626 #endif 2627 2628 static bool 2629 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2630 { 2631 if_ctx_t ctx = rxq->ifr_ctx; 2632 if_shared_ctx_t sctx = ctx->ifc_sctx; 2633 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2634 int avail, i; 2635 qidx_t *cidxp; 2636 struct if_rxd_info ri; 2637 int err, budget_left, rx_bytes, rx_pkts; 2638 iflib_fl_t fl; 2639 struct ifnet *ifp; 2640 int lro_enabled; 2641 bool v4_forwarding, v6_forwarding, lro_possible; 2642 2643 /* 2644 * XXX early demux data packets so that if_input processing only handles 2645 * acks in interrupt context 2646 */ 2647 struct mbuf *m, *mh, *mt, *mf; 2648 2649 lro_possible = v4_forwarding = v6_forwarding = false; 2650 ifp = ctx->ifc_ifp; 2651 mh = mt = NULL; 2652 MPASS(budget > 0); 2653 rx_pkts = rx_bytes = 0; 2654 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2655 cidxp = &rxq->ifr_cq_cidx; 2656 else 2657 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2658 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2659 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2660 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2661 DBG_COUNTER_INC(rx_unavail); 2662 return (false); 2663 } 2664 2665 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2666 if (__predict_false(!CTX_ACTIVE(ctx))) { 2667 DBG_COUNTER_INC(rx_ctx_inactive); 2668 break; 2669 } 2670 /* 2671 * Reset client set fields to their default values 2672 */ 2673 rxd_info_zero(&ri); 2674 ri.iri_qsidx = rxq->ifr_id; 2675 ri.iri_cidx = *cidxp; 2676 ri.iri_ifp = ifp; 2677 ri.iri_frags = rxq->ifr_frags; 2678 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2679 2680 if (err) 2681 goto err; 2682 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2683 *cidxp = ri.iri_cidx; 2684 /* Update our consumer index */ 2685 /* XXX NB: shurd - check if this is still safe */ 2686 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2687 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2688 rxq->ifr_cq_gen = 0; 2689 } 2690 /* was this only a completion queue message? */ 2691 if (__predict_false(ri.iri_nfrags == 0)) 2692 continue; 2693 } 2694 MPASS(ri.iri_nfrags != 0); 2695 MPASS(ri.iri_len != 0); 2696 2697 /* will advance the cidx on the corresponding free lists */ 2698 m = iflib_rxd_pkt_get(rxq, &ri); 2699 if (avail == 0 && budget_left) 2700 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2701 2702 if (__predict_false(m == NULL)) { 2703 DBG_COUNTER_INC(rx_mbuf_null); 2704 continue; 2705 } 2706 /* imm_pkt: -- cxgb */ 2707 if (mh == NULL) 2708 mh = mt = m; 2709 else { 2710 mt->m_nextpkt = m; 2711 mt = m; 2712 } 2713 } 2714 /* make sure that we can refill faster than drain */ 2715 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2716 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2717 2718 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2719 if (lro_enabled) 2720 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2721 mt = mf = NULL; 2722 while (mh != NULL) { 2723 m = mh; 2724 mh = mh->m_nextpkt; 2725 m->m_nextpkt = NULL; 2726 #ifndef __NO_STRICT_ALIGNMENT 2727 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2728 continue; 2729 #endif 2730 rx_bytes += m->m_pkthdr.len; 2731 rx_pkts++; 2732 #if defined(INET6) || defined(INET) 2733 if (lro_enabled) { 2734 if (!lro_possible) { 2735 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2736 if (lro_possible && mf != NULL) { 2737 ifp->if_input(ifp, mf); 2738 DBG_COUNTER_INC(rx_if_input); 2739 mt = mf = NULL; 2740 } 2741 } 2742 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2743 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2744 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2745 continue; 2746 } 2747 } 2748 #endif 2749 if (lro_possible) { 2750 ifp->if_input(ifp, m); 2751 DBG_COUNTER_INC(rx_if_input); 2752 continue; 2753 } 2754 2755 if (mf == NULL) 2756 mf = m; 2757 if (mt != NULL) 2758 mt->m_nextpkt = m; 2759 mt = m; 2760 } 2761 if (mf != NULL) { 2762 ifp->if_input(ifp, mf); 2763 DBG_COUNTER_INC(rx_if_input); 2764 } 2765 2766 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2767 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2768 2769 /* 2770 * Flush any outstanding LRO work 2771 */ 2772 #if defined(INET6) || defined(INET) 2773 tcp_lro_flush_all(&rxq->ifr_lc); 2774 #endif 2775 if (avail) 2776 return true; 2777 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2778 err: 2779 STATE_LOCK(ctx); 2780 ctx->ifc_flags |= IFC_DO_RESET; 2781 iflib_admin_intr_deferred(ctx); 2782 STATE_UNLOCK(ctx); 2783 return (false); 2784 } 2785 2786 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2787 static inline qidx_t 2788 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2789 { 2790 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2791 qidx_t minthresh = txq->ift_size / 8; 2792 if (in_use > 4*minthresh) 2793 return (notify_count); 2794 if (in_use > 2*minthresh) 2795 return (notify_count >> 1); 2796 if (in_use > minthresh) 2797 return (notify_count >> 3); 2798 return (0); 2799 } 2800 2801 static inline qidx_t 2802 txq_max_rs_deferred(iflib_txq_t txq) 2803 { 2804 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2805 qidx_t minthresh = txq->ift_size / 8; 2806 if (txq->ift_in_use > 4*minthresh) 2807 return (notify_count); 2808 if (txq->ift_in_use > 2*minthresh) 2809 return (notify_count >> 1); 2810 if (txq->ift_in_use > minthresh) 2811 return (notify_count >> 2); 2812 return (2); 2813 } 2814 2815 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2816 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2817 2818 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2819 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2820 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2821 2822 /* forward compatibility for cxgb */ 2823 #define FIRST_QSET(ctx) 0 2824 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2825 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2826 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2827 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2828 2829 /* XXX we should be setting this to something other than zero */ 2830 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2831 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2832 2833 static inline bool 2834 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2835 { 2836 qidx_t dbval, max; 2837 bool rang; 2838 2839 rang = false; 2840 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2841 if (ring || txq->ift_db_pending >= max) { 2842 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2843 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2844 txq->ift_db_pending = txq->ift_npending = 0; 2845 rang = true; 2846 } 2847 return (rang); 2848 } 2849 2850 #ifdef PKT_DEBUG 2851 static void 2852 print_pkt(if_pkt_info_t pi) 2853 { 2854 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2855 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2856 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2857 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2858 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2859 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2860 } 2861 #endif 2862 2863 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2864 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2865 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2866 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2867 2868 static int 2869 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2870 { 2871 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2872 struct ether_vlan_header *eh; 2873 struct mbuf *m, *n; 2874 2875 n = m = *mp; 2876 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2877 M_WRITABLE(m) == 0) { 2878 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2879 return (ENOMEM); 2880 } else { 2881 m_freem(*mp); 2882 n = *mp = m; 2883 } 2884 } 2885 2886 /* 2887 * Determine where frame payload starts. 2888 * Jump over vlan headers if already present, 2889 * helpful for QinQ too. 2890 */ 2891 if (__predict_false(m->m_len < sizeof(*eh))) { 2892 txq->ift_pullups++; 2893 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2894 return (ENOMEM); 2895 } 2896 eh = mtod(m, struct ether_vlan_header *); 2897 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2898 pi->ipi_etype = ntohs(eh->evl_proto); 2899 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2900 } else { 2901 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2902 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2903 } 2904 2905 switch (pi->ipi_etype) { 2906 #ifdef INET 2907 case ETHERTYPE_IP: 2908 { 2909 struct ip *ip = NULL; 2910 struct tcphdr *th = NULL; 2911 int minthlen; 2912 2913 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2914 if (__predict_false(m->m_len < minthlen)) { 2915 /* 2916 * if this code bloat is causing too much of a hit 2917 * move it to a separate function and mark it noinline 2918 */ 2919 if (m->m_len == pi->ipi_ehdrlen) { 2920 n = m->m_next; 2921 MPASS(n); 2922 if (n->m_len >= sizeof(*ip)) { 2923 ip = (struct ip *)n->m_data; 2924 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2925 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2926 } else { 2927 txq->ift_pullups++; 2928 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2929 return (ENOMEM); 2930 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2931 } 2932 } else { 2933 txq->ift_pullups++; 2934 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2935 return (ENOMEM); 2936 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2937 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2938 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2939 } 2940 } else { 2941 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2942 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2943 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2944 } 2945 pi->ipi_ip_hlen = ip->ip_hl << 2; 2946 pi->ipi_ipproto = ip->ip_p; 2947 pi->ipi_flags |= IPI_TX_IPV4; 2948 2949 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 2950 ip->ip_sum = 0; 2951 2952 /* TCP checksum offload may require TCP header length */ 2953 if (IS_TX_OFFLOAD4(pi)) { 2954 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 2955 if (__predict_false(th == NULL)) { 2956 txq->ift_pullups++; 2957 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2958 return (ENOMEM); 2959 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2960 } 2961 pi->ipi_tcp_hflags = th->th_flags; 2962 pi->ipi_tcp_hlen = th->th_off << 2; 2963 pi->ipi_tcp_seq = th->th_seq; 2964 } 2965 if (IS_TSO4(pi)) { 2966 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2967 return (ENXIO); 2968 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2969 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2970 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2971 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2972 ip->ip_sum = 0; 2973 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2974 } 2975 } 2976 } 2977 break; 2978 } 2979 #endif 2980 #ifdef INET6 2981 case ETHERTYPE_IPV6: 2982 { 2983 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2984 struct tcphdr *th; 2985 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2986 2987 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2988 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2989 return (ENOMEM); 2990 } 2991 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2992 2993 /* XXX-BZ this will go badly in case of ext hdrs. */ 2994 pi->ipi_ipproto = ip6->ip6_nxt; 2995 pi->ipi_flags |= IPI_TX_IPV6; 2996 2997 /* TCP checksum offload may require TCP header length */ 2998 if (IS_TX_OFFLOAD6(pi)) { 2999 if (pi->ipi_ipproto == IPPROTO_TCP) { 3000 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3001 txq->ift_pullups++; 3002 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3003 return (ENOMEM); 3004 } 3005 pi->ipi_tcp_hflags = th->th_flags; 3006 pi->ipi_tcp_hlen = th->th_off << 2; 3007 pi->ipi_tcp_seq = th->th_seq; 3008 } 3009 if (IS_TSO6(pi)) { 3010 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3011 return (ENXIO); 3012 /* 3013 * The corresponding flag is set by the stack in the IPv4 3014 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 3015 * So, set it here because the rest of the flow requires it. 3016 */ 3017 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3018 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3019 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3020 } 3021 } 3022 break; 3023 } 3024 #endif 3025 default: 3026 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3027 pi->ipi_ip_hlen = 0; 3028 break; 3029 } 3030 *mp = m; 3031 3032 return (0); 3033 } 3034 3035 static __noinline struct mbuf * 3036 collapse_pkthdr(struct mbuf *m0) 3037 { 3038 struct mbuf *m, *m_next, *tmp; 3039 3040 m = m0; 3041 m_next = m->m_next; 3042 while (m_next != NULL && m_next->m_len == 0) { 3043 m = m_next; 3044 m->m_next = NULL; 3045 m_free(m); 3046 m_next = m_next->m_next; 3047 } 3048 m = m0; 3049 m->m_next = m_next; 3050 if ((m_next->m_flags & M_EXT) == 0) { 3051 m = m_defrag(m, M_NOWAIT); 3052 } else { 3053 tmp = m_next->m_next; 3054 memcpy(m_next, m, MPKTHSIZE); 3055 m = m_next; 3056 m->m_next = tmp; 3057 } 3058 return (m); 3059 } 3060 3061 /* 3062 * If dodgy hardware rejects the scatter gather chain we've handed it 3063 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3064 * m_defrag'd mbufs 3065 */ 3066 static __noinline struct mbuf * 3067 iflib_remove_mbuf(iflib_txq_t txq) 3068 { 3069 int ntxd, i, pidx; 3070 struct mbuf *m, *mh, **ifsd_m; 3071 3072 pidx = txq->ift_pidx; 3073 ifsd_m = txq->ift_sds.ifsd_m; 3074 ntxd = txq->ift_size; 3075 mh = m = ifsd_m[pidx]; 3076 ifsd_m[pidx] = NULL; 3077 #if MEMORY_LOGGING 3078 txq->ift_dequeued++; 3079 #endif 3080 i = 1; 3081 3082 while (m) { 3083 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 3084 #if MEMORY_LOGGING 3085 txq->ift_dequeued++; 3086 #endif 3087 m = m->m_next; 3088 i++; 3089 } 3090 return (mh); 3091 } 3092 3093 static int 3094 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 3095 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 3096 int max_segs, int flags) 3097 { 3098 if_ctx_t ctx; 3099 if_shared_ctx_t sctx; 3100 if_softc_ctx_t scctx; 3101 int i, next, pidx, err, ntxd, count; 3102 struct mbuf *m, *tmp, **ifsd_m; 3103 3104 m = *m0; 3105 3106 /* 3107 * Please don't ever do this 3108 */ 3109 if (__predict_false(m->m_len == 0)) 3110 *m0 = m = collapse_pkthdr(m); 3111 3112 ctx = txq->ift_ctx; 3113 sctx = ctx->ifc_sctx; 3114 scctx = &ctx->ifc_softc_ctx; 3115 ifsd_m = txq->ift_sds.ifsd_m; 3116 ntxd = txq->ift_size; 3117 pidx = txq->ift_pidx; 3118 if (map != NULL) { 3119 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 3120 3121 err = bus_dmamap_load_mbuf_sg(tag, map, 3122 *m0, segs, nsegs, BUS_DMA_NOWAIT); 3123 if (err) 3124 return (err); 3125 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 3126 count = 0; 3127 m = *m0; 3128 do { 3129 if (__predict_false(m->m_len <= 0)) { 3130 tmp = m; 3131 m = m->m_next; 3132 tmp->m_next = NULL; 3133 m_free(tmp); 3134 continue; 3135 } 3136 m = m->m_next; 3137 count++; 3138 } while (m != NULL); 3139 if (count > *nsegs) { 3140 ifsd_m[pidx] = *m0; 3141 ifsd_m[pidx]->m_flags |= M_TOOBIG; 3142 return (0); 3143 } 3144 m = *m0; 3145 count = 0; 3146 do { 3147 next = (pidx + count) & (ntxd-1); 3148 MPASS(ifsd_m[next] == NULL); 3149 ifsd_m[next] = m; 3150 count++; 3151 tmp = m; 3152 m = m->m_next; 3153 } while (m != NULL); 3154 } else { 3155 int buflen, sgsize, maxsegsz, max_sgsize; 3156 vm_offset_t vaddr; 3157 vm_paddr_t curaddr; 3158 3159 count = i = 0; 3160 m = *m0; 3161 if (m->m_pkthdr.csum_flags & CSUM_TSO) 3162 maxsegsz = scctx->isc_tx_tso_segsize_max; 3163 else 3164 maxsegsz = sctx->isc_tx_maxsegsize; 3165 3166 do { 3167 if (__predict_false(m->m_len <= 0)) { 3168 tmp = m; 3169 m = m->m_next; 3170 tmp->m_next = NULL; 3171 m_free(tmp); 3172 continue; 3173 } 3174 buflen = m->m_len; 3175 vaddr = (vm_offset_t)m->m_data; 3176 /* 3177 * see if we can't be smarter about physically 3178 * contiguous mappings 3179 */ 3180 next = (pidx + count) & (ntxd-1); 3181 MPASS(ifsd_m[next] == NULL); 3182 #if MEMORY_LOGGING 3183 txq->ift_enqueued++; 3184 #endif 3185 ifsd_m[next] = m; 3186 while (buflen > 0) { 3187 if (i >= max_segs) 3188 goto err; 3189 max_sgsize = MIN(buflen, maxsegsz); 3190 curaddr = pmap_kextract(vaddr); 3191 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 3192 sgsize = MIN(sgsize, max_sgsize); 3193 segs[i].ds_addr = curaddr; 3194 segs[i].ds_len = sgsize; 3195 vaddr += sgsize; 3196 buflen -= sgsize; 3197 i++; 3198 } 3199 count++; 3200 tmp = m; 3201 m = m->m_next; 3202 } while (m != NULL); 3203 *nsegs = i; 3204 } 3205 return (0); 3206 err: 3207 *m0 = iflib_remove_mbuf(txq); 3208 return (EFBIG); 3209 } 3210 3211 static inline caddr_t 3212 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3213 { 3214 qidx_t size; 3215 int ntxd; 3216 caddr_t start, end, cur, next; 3217 3218 ntxd = txq->ift_size; 3219 size = txq->ift_txd_size[qid]; 3220 start = txq->ift_ifdi[qid].idi_vaddr; 3221 3222 if (__predict_false(size == 0)) 3223 return (start); 3224 cur = start + size*cidx; 3225 end = start + size*ntxd; 3226 next = CACHE_PTR_NEXT(cur); 3227 return (next < end ? next : start); 3228 } 3229 3230 /* 3231 * Pad an mbuf to ensure a minimum ethernet frame size. 3232 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3233 */ 3234 static __noinline int 3235 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3236 { 3237 /* 3238 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3239 * and ARP message is the smallest common payload I can think of 3240 */ 3241 static char pad[18]; /* just zeros */ 3242 int n; 3243 struct mbuf *new_head; 3244 3245 if (!M_WRITABLE(*m_head)) { 3246 new_head = m_dup(*m_head, M_NOWAIT); 3247 if (new_head == NULL) { 3248 m_freem(*m_head); 3249 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3250 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3251 return ENOMEM; 3252 } 3253 m_freem(*m_head); 3254 *m_head = new_head; 3255 } 3256 3257 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3258 n > 0; n -= sizeof(pad)) 3259 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3260 break; 3261 3262 if (n > 0) { 3263 m_freem(*m_head); 3264 device_printf(dev, "cannot pad short frame\n"); 3265 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3266 return (ENOBUFS); 3267 } 3268 3269 return 0; 3270 } 3271 3272 static int 3273 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3274 { 3275 if_ctx_t ctx; 3276 if_shared_ctx_t sctx; 3277 if_softc_ctx_t scctx; 3278 bus_dma_segment_t *segs; 3279 struct mbuf *m_head; 3280 void *next_txd; 3281 bus_dmamap_t map; 3282 struct if_pkt_info pi; 3283 int remap = 0; 3284 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3285 bus_dma_tag_t desc_tag; 3286 3287 segs = txq->ift_segs; 3288 ctx = txq->ift_ctx; 3289 sctx = ctx->ifc_sctx; 3290 scctx = &ctx->ifc_softc_ctx; 3291 segs = txq->ift_segs; 3292 ntxd = txq->ift_size; 3293 m_head = *m_headp; 3294 map = NULL; 3295 3296 /* 3297 * If we're doing TSO the next descriptor to clean may be quite far ahead 3298 */ 3299 cidx = txq->ift_cidx; 3300 pidx = txq->ift_pidx; 3301 if (ctx->ifc_flags & IFC_PREFETCH) { 3302 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3303 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3304 next_txd = calc_next_txd(txq, cidx, 0); 3305 prefetch(next_txd); 3306 } 3307 3308 /* prefetch the next cache line of mbuf pointers and flags */ 3309 prefetch(&txq->ift_sds.ifsd_m[next]); 3310 if (txq->ift_sds.ifsd_map != NULL) { 3311 prefetch(&txq->ift_sds.ifsd_map[next]); 3312 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3313 prefetch(&txq->ift_sds.ifsd_flags[next]); 3314 } 3315 } else if (txq->ift_sds.ifsd_map != NULL) 3316 map = txq->ift_sds.ifsd_map[pidx]; 3317 3318 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3319 desc_tag = txq->ift_tso_desc_tag; 3320 max_segs = scctx->isc_tx_tso_segments_max; 3321 MPASS(desc_tag != NULL); 3322 MPASS(max_segs > 0); 3323 } else { 3324 desc_tag = txq->ift_desc_tag; 3325 max_segs = scctx->isc_tx_nsegments; 3326 } 3327 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3328 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3329 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3330 if (err) 3331 return err; 3332 } 3333 m_head = *m_headp; 3334 3335 pkt_info_zero(&pi); 3336 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3337 pi.ipi_pidx = pidx; 3338 pi.ipi_qsidx = txq->ift_id; 3339 pi.ipi_len = m_head->m_pkthdr.len; 3340 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3341 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3342 3343 /* deliberate bitwise OR to make one condition */ 3344 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3345 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3346 return (err); 3347 m_head = *m_headp; 3348 } 3349 3350 retry: 3351 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3352 defrag: 3353 if (__predict_false(err)) { 3354 switch (err) { 3355 case EFBIG: 3356 /* try collapse once and defrag once */ 3357 if (remap == 0) { 3358 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3359 /* try defrag if collapsing fails */ 3360 if (m_head == NULL) 3361 remap++; 3362 } 3363 if (remap == 1) 3364 m_head = m_defrag(*m_headp, M_NOWAIT); 3365 remap++; 3366 if (__predict_false(m_head == NULL)) 3367 goto defrag_failed; 3368 txq->ift_mbuf_defrag++; 3369 *m_headp = m_head; 3370 goto retry; 3371 break; 3372 case ENOMEM: 3373 txq->ift_no_tx_dma_setup++; 3374 break; 3375 default: 3376 txq->ift_no_tx_dma_setup++; 3377 m_freem(*m_headp); 3378 DBG_COUNTER_INC(tx_frees); 3379 *m_headp = NULL; 3380 break; 3381 } 3382 txq->ift_map_failed++; 3383 DBG_COUNTER_INC(encap_load_mbuf_fail); 3384 return (err); 3385 } 3386 3387 /* 3388 * XXX assumes a 1 to 1 relationship between segments and 3389 * descriptors - this does not hold true on all drivers, e.g. 3390 * cxgb 3391 */ 3392 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3393 txq->ift_no_desc_avail++; 3394 if (map != NULL) 3395 bus_dmamap_unload(desc_tag, map); 3396 DBG_COUNTER_INC(encap_txq_avail_fail); 3397 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3398 GROUPTASK_ENQUEUE(&txq->ift_task); 3399 return (ENOBUFS); 3400 } 3401 /* 3402 * On Intel cards we can greatly reduce the number of TX interrupts 3403 * we see by only setting report status on every Nth descriptor. 3404 * However, this also means that the driver will need to keep track 3405 * of the descriptors that RS was set on to check them for the DD bit. 3406 */ 3407 txq->ift_rs_pending += nsegs + 1; 3408 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3409 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3410 pi.ipi_flags |= IPI_TX_INTR; 3411 txq->ift_rs_pending = 0; 3412 } 3413 3414 pi.ipi_segs = segs; 3415 pi.ipi_nsegs = nsegs; 3416 3417 MPASS(pidx >= 0 && pidx < txq->ift_size); 3418 #ifdef PKT_DEBUG 3419 print_pkt(&pi); 3420 #endif 3421 if (map != NULL) 3422 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3423 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3424 if (map != NULL) 3425 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3426 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3427 DBG_COUNTER_INC(tx_encap); 3428 MPASS(pi.ipi_new_pidx < txq->ift_size); 3429 3430 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3431 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3432 ndesc += txq->ift_size; 3433 txq->ift_gen = 1; 3434 } 3435 /* 3436 * drivers can need as many as 3437 * two sentinels 3438 */ 3439 MPASS(ndesc <= pi.ipi_nsegs + 2); 3440 MPASS(pi.ipi_new_pidx != pidx); 3441 MPASS(ndesc > 0); 3442 txq->ift_in_use += ndesc; 3443 3444 /* 3445 * We update the last software descriptor again here because there may 3446 * be a sentinel and/or there may be more mbufs than segments 3447 */ 3448 txq->ift_pidx = pi.ipi_new_pidx; 3449 txq->ift_npending += pi.ipi_ndescs; 3450 } else { 3451 *m_headp = m_head = iflib_remove_mbuf(txq); 3452 if (err == EFBIG) { 3453 txq->ift_txd_encap_efbig++; 3454 if (remap < 2) { 3455 remap = 1; 3456 goto defrag; 3457 } 3458 } 3459 DBG_COUNTER_INC(encap_txd_encap_fail); 3460 goto defrag_failed; 3461 } 3462 return (err); 3463 3464 defrag_failed: 3465 txq->ift_mbuf_defrag_failed++; 3466 txq->ift_map_failed++; 3467 m_freem(*m_headp); 3468 DBG_COUNTER_INC(tx_frees); 3469 *m_headp = NULL; 3470 return (ENOMEM); 3471 } 3472 3473 static void 3474 iflib_tx_desc_free(iflib_txq_t txq, int n) 3475 { 3476 int hasmap; 3477 uint32_t qsize, cidx, mask, gen; 3478 struct mbuf *m, **ifsd_m; 3479 uint8_t *ifsd_flags; 3480 bus_dmamap_t *ifsd_map; 3481 bool do_prefetch; 3482 3483 cidx = txq->ift_cidx; 3484 gen = txq->ift_gen; 3485 qsize = txq->ift_size; 3486 mask = qsize-1; 3487 hasmap = txq->ift_sds.ifsd_map != NULL; 3488 ifsd_flags = txq->ift_sds.ifsd_flags; 3489 ifsd_m = txq->ift_sds.ifsd_m; 3490 ifsd_map = txq->ift_sds.ifsd_map; 3491 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3492 3493 while (n-- > 0) { 3494 if (do_prefetch) { 3495 prefetch(ifsd_m[(cidx + 3) & mask]); 3496 prefetch(ifsd_m[(cidx + 4) & mask]); 3497 } 3498 if (ifsd_m[cidx] != NULL) { 3499 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3500 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3501 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3502 /* 3503 * does it matter if it's not the TSO tag? If so we'll 3504 * have to add the type to flags 3505 */ 3506 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3507 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3508 } 3509 if ((m = ifsd_m[cidx]) != NULL) { 3510 /* XXX we don't support any drivers that batch packets yet */ 3511 MPASS(m->m_nextpkt == NULL); 3512 /* if the number of clusters exceeds the number of segments 3513 * there won't be space on the ring to save a pointer to each 3514 * cluster so we simply free the list here 3515 */ 3516 if (m->m_flags & M_TOOBIG) { 3517 m_freem(m); 3518 } else { 3519 m_free(m); 3520 } 3521 ifsd_m[cidx] = NULL; 3522 #if MEMORY_LOGGING 3523 txq->ift_dequeued++; 3524 #endif 3525 DBG_COUNTER_INC(tx_frees); 3526 } 3527 } 3528 if (__predict_false(++cidx == qsize)) { 3529 cidx = 0; 3530 gen = 0; 3531 } 3532 } 3533 txq->ift_cidx = cidx; 3534 txq->ift_gen = gen; 3535 } 3536 3537 static __inline int 3538 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3539 { 3540 int reclaim; 3541 if_ctx_t ctx = txq->ift_ctx; 3542 3543 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3544 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3545 3546 /* 3547 * Need a rate-limiting check so that this isn't called every time 3548 */ 3549 iflib_tx_credits_update(ctx, txq); 3550 reclaim = DESC_RECLAIMABLE(txq); 3551 3552 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3553 #ifdef INVARIANTS 3554 if (iflib_verbose_debug) { 3555 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3556 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3557 reclaim, thresh); 3558 3559 } 3560 #endif 3561 return (0); 3562 } 3563 iflib_tx_desc_free(txq, reclaim); 3564 txq->ift_cleaned += reclaim; 3565 txq->ift_in_use -= reclaim; 3566 3567 return (reclaim); 3568 } 3569 3570 static struct mbuf ** 3571 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3572 { 3573 int next, size; 3574 struct mbuf **items; 3575 3576 size = r->size; 3577 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3578 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3579 3580 prefetch(items[(cidx + offset) & (size-1)]); 3581 if (remaining > 1) { 3582 prefetch2cachelines(&items[next]); 3583 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3584 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3585 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3586 } 3587 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3588 } 3589 3590 static void 3591 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3592 { 3593 3594 ifmp_ring_check_drainage(txq->ift_br, budget); 3595 } 3596 3597 static uint32_t 3598 iflib_txq_can_drain(struct ifmp_ring *r) 3599 { 3600 iflib_txq_t txq = r->cookie; 3601 if_ctx_t ctx = txq->ift_ctx; 3602 3603 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3604 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3605 } 3606 3607 static uint32_t 3608 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3609 { 3610 iflib_txq_t txq = r->cookie; 3611 if_ctx_t ctx = txq->ift_ctx; 3612 struct ifnet *ifp = ctx->ifc_ifp; 3613 struct mbuf **mp, *m; 3614 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3615 int reclaimed, err, in_use_prev, desc_used; 3616 bool do_prefetch, ring, rang; 3617 3618 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3619 !LINK_ACTIVE(ctx))) { 3620 DBG_COUNTER_INC(txq_drain_notready); 3621 return (0); 3622 } 3623 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3624 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3625 avail = IDXDIFF(pidx, cidx, r->size); 3626 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3627 DBG_COUNTER_INC(txq_drain_flushing); 3628 for (i = 0; i < avail; i++) { 3629 m_free(r->items[(cidx + i) & (r->size-1)]); 3630 r->items[(cidx + i) & (r->size-1)] = NULL; 3631 } 3632 return (avail); 3633 } 3634 3635 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3636 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3637 CALLOUT_LOCK(txq); 3638 callout_stop(&txq->ift_timer); 3639 CALLOUT_UNLOCK(txq); 3640 DBG_COUNTER_INC(txq_drain_oactive); 3641 return (0); 3642 } 3643 if (reclaimed) 3644 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3645 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3646 count = MIN(avail, TX_BATCH_SIZE); 3647 #ifdef INVARIANTS 3648 if (iflib_verbose_debug) 3649 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3650 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3651 #endif 3652 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3653 avail = TXQ_AVAIL(txq); 3654 err = 0; 3655 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3656 int rem = do_prefetch ? count - i : 0; 3657 3658 mp = _ring_peek_one(r, cidx, i, rem); 3659 MPASS(mp != NULL && *mp != NULL); 3660 if (__predict_false(*mp == (struct mbuf *)txq)) { 3661 consumed++; 3662 reclaimed++; 3663 continue; 3664 } 3665 in_use_prev = txq->ift_in_use; 3666 err = iflib_encap(txq, mp); 3667 if (__predict_false(err)) { 3668 DBG_COUNTER_INC(txq_drain_encapfail); 3669 /* no room - bail out */ 3670 if (err == ENOBUFS) 3671 break; 3672 consumed++; 3673 DBG_COUNTER_INC(txq_drain_encapfail); 3674 /* we can't send this packet - skip it */ 3675 continue; 3676 } 3677 consumed++; 3678 pkt_sent++; 3679 m = *mp; 3680 DBG_COUNTER_INC(tx_sent); 3681 bytes_sent += m->m_pkthdr.len; 3682 mcast_sent += !!(m->m_flags & M_MCAST); 3683 avail = TXQ_AVAIL(txq); 3684 3685 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3686 desc_used += (txq->ift_in_use - in_use_prev); 3687 ETHER_BPF_MTAP(ifp, m); 3688 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3689 break; 3690 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3691 } 3692 3693 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3694 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3695 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3696 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3697 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3698 if (mcast_sent) 3699 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3700 #ifdef INVARIANTS 3701 if (iflib_verbose_debug) 3702 printf("consumed=%d\n", consumed); 3703 #endif 3704 return (consumed); 3705 } 3706 3707 static uint32_t 3708 iflib_txq_drain_always(struct ifmp_ring *r) 3709 { 3710 return (1); 3711 } 3712 3713 static uint32_t 3714 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3715 { 3716 int i, avail; 3717 struct mbuf **mp; 3718 iflib_txq_t txq; 3719 3720 txq = r->cookie; 3721 3722 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3723 CALLOUT_LOCK(txq); 3724 callout_stop(&txq->ift_timer); 3725 CALLOUT_UNLOCK(txq); 3726 3727 avail = IDXDIFF(pidx, cidx, r->size); 3728 for (i = 0; i < avail; i++) { 3729 mp = _ring_peek_one(r, cidx, i, avail - i); 3730 if (__predict_false(*mp == (struct mbuf *)txq)) 3731 continue; 3732 m_freem(*mp); 3733 } 3734 MPASS(ifmp_ring_is_stalled(r) == 0); 3735 return (avail); 3736 } 3737 3738 static void 3739 iflib_ifmp_purge(iflib_txq_t txq) 3740 { 3741 struct ifmp_ring *r; 3742 3743 r = txq->ift_br; 3744 r->drain = iflib_txq_drain_free; 3745 r->can_drain = iflib_txq_drain_always; 3746 3747 ifmp_ring_check_drainage(r, r->size); 3748 3749 r->drain = iflib_txq_drain; 3750 r->can_drain = iflib_txq_can_drain; 3751 } 3752 3753 static void 3754 _task_fn_tx(void *context) 3755 { 3756 iflib_txq_t txq = context; 3757 if_ctx_t ctx = txq->ift_ctx; 3758 struct ifnet *ifp = ctx->ifc_ifp; 3759 3760 #ifdef IFLIB_DIAGNOSTICS 3761 txq->ift_cpu_exec_count[curcpu]++; 3762 #endif 3763 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3764 return; 3765 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3766 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3767 netmap_tx_irq(ifp, txq->ift_id); 3768 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3769 return; 3770 } 3771 if (txq->ift_db_pending) 3772 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); 3773 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3774 if (ctx->ifc_flags & IFC_LEGACY) 3775 IFDI_INTR_ENABLE(ctx); 3776 else { 3777 #ifdef INVARIANTS 3778 int rc = 3779 #endif 3780 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3781 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3782 } 3783 } 3784 3785 static void 3786 _task_fn_rx(void *context) 3787 { 3788 iflib_rxq_t rxq = context; 3789 if_ctx_t ctx = rxq->ifr_ctx; 3790 bool more; 3791 uint16_t budget; 3792 3793 #ifdef IFLIB_DIAGNOSTICS 3794 rxq->ifr_cpu_exec_count[curcpu]++; 3795 #endif 3796 DBG_COUNTER_INC(task_fn_rxs); 3797 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3798 return; 3799 more = true; 3800 #ifdef DEV_NETMAP 3801 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3802 u_int work = 0; 3803 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3804 more = false; 3805 } 3806 } 3807 #endif 3808 budget = ctx->ifc_sysctl_rx_budget; 3809 if (budget == 0) 3810 budget = 16; /* XXX */ 3811 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3812 if (ctx->ifc_flags & IFC_LEGACY) 3813 IFDI_INTR_ENABLE(ctx); 3814 else { 3815 #ifdef INVARIANTS 3816 int rc = 3817 #endif 3818 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3819 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3820 DBG_COUNTER_INC(rx_intr_enables); 3821 } 3822 } 3823 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3824 return; 3825 if (more) 3826 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3827 } 3828 3829 static void 3830 _task_fn_admin(void *context) 3831 { 3832 if_ctx_t ctx = context; 3833 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3834 iflib_txq_t txq; 3835 int i; 3836 bool oactive, running, do_reset, do_watchdog; 3837 uint32_t reset_on = hz / 2; 3838 3839 STATE_LOCK(ctx); 3840 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3841 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3842 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3843 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3844 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3845 STATE_UNLOCK(ctx); 3846 3847 if ((!running & !oactive) && 3848 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3849 return; 3850 3851 CTX_LOCK(ctx); 3852 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3853 CALLOUT_LOCK(txq); 3854 callout_stop(&txq->ift_timer); 3855 CALLOUT_UNLOCK(txq); 3856 } 3857 if (do_watchdog) { 3858 ctx->ifc_watchdog_events++; 3859 IFDI_WATCHDOG_RESET(ctx); 3860 } 3861 IFDI_UPDATE_ADMIN_STATUS(ctx); 3862 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3863 #ifdef DEV_NETMAP 3864 reset_on = hz / 2; 3865 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3866 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on); 3867 #endif 3868 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3869 } 3870 IFDI_LINK_INTR_ENABLE(ctx); 3871 if (do_reset) 3872 iflib_if_init_locked(ctx); 3873 CTX_UNLOCK(ctx); 3874 3875 if (LINK_ACTIVE(ctx) == 0) 3876 return; 3877 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3878 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3879 } 3880 3881 3882 static void 3883 _task_fn_iov(void *context) 3884 { 3885 if_ctx_t ctx = context; 3886 3887 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3888 return; 3889 3890 CTX_LOCK(ctx); 3891 IFDI_VFLR_HANDLE(ctx); 3892 CTX_UNLOCK(ctx); 3893 } 3894 3895 static int 3896 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3897 { 3898 int err; 3899 if_int_delay_info_t info; 3900 if_ctx_t ctx; 3901 3902 info = (if_int_delay_info_t)arg1; 3903 ctx = info->iidi_ctx; 3904 info->iidi_req = req; 3905 info->iidi_oidp = oidp; 3906 CTX_LOCK(ctx); 3907 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3908 CTX_UNLOCK(ctx); 3909 return (err); 3910 } 3911 3912 /********************************************************************* 3913 * 3914 * IFNET FUNCTIONS 3915 * 3916 **********************************************************************/ 3917 3918 static void 3919 iflib_if_init_locked(if_ctx_t ctx) 3920 { 3921 iflib_stop(ctx); 3922 iflib_init_locked(ctx); 3923 } 3924 3925 3926 static void 3927 iflib_if_init(void *arg) 3928 { 3929 if_ctx_t ctx = arg; 3930 3931 CTX_LOCK(ctx); 3932 iflib_if_init_locked(ctx); 3933 CTX_UNLOCK(ctx); 3934 } 3935 3936 static int 3937 iflib_if_transmit(if_t ifp, struct mbuf *m) 3938 { 3939 if_ctx_t ctx = if_getsoftc(ifp); 3940 3941 iflib_txq_t txq; 3942 int err, qidx; 3943 3944 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3945 DBG_COUNTER_INC(tx_frees); 3946 m_freem(m); 3947 return (ENOBUFS); 3948 } 3949 3950 MPASS(m->m_nextpkt == NULL); 3951 qidx = 0; 3952 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3953 qidx = QIDX(ctx, m); 3954 /* 3955 * XXX calculate buf_ring based on flowid (divvy up bits?) 3956 */ 3957 txq = &ctx->ifc_txqs[qidx]; 3958 3959 #ifdef DRIVER_BACKPRESSURE 3960 if (txq->ift_closed) { 3961 while (m != NULL) { 3962 next = m->m_nextpkt; 3963 m->m_nextpkt = NULL; 3964 m_freem(m); 3965 m = next; 3966 } 3967 return (ENOBUFS); 3968 } 3969 #endif 3970 #ifdef notyet 3971 qidx = count = 0; 3972 mp = marr; 3973 next = m; 3974 do { 3975 count++; 3976 next = next->m_nextpkt; 3977 } while (next != NULL); 3978 3979 if (count > nitems(marr)) 3980 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3981 /* XXX check nextpkt */ 3982 m_freem(m); 3983 /* XXX simplify for now */ 3984 DBG_COUNTER_INC(tx_frees); 3985 return (ENOBUFS); 3986 } 3987 for (next = m, i = 0; next != NULL; i++) { 3988 mp[i] = next; 3989 next = next->m_nextpkt; 3990 mp[i]->m_nextpkt = NULL; 3991 } 3992 #endif 3993 DBG_COUNTER_INC(tx_seen); 3994 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); 3995 3996 GROUPTASK_ENQUEUE(&txq->ift_task); 3997 if (err) { 3998 /* support forthcoming later */ 3999 #ifdef DRIVER_BACKPRESSURE 4000 txq->ift_closed = TRUE; 4001 #endif 4002 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4003 m_freem(m); 4004 } 4005 4006 return (err); 4007 } 4008 4009 static void 4010 iflib_if_qflush(if_t ifp) 4011 { 4012 if_ctx_t ctx = if_getsoftc(ifp); 4013 iflib_txq_t txq = ctx->ifc_txqs; 4014 int i; 4015 4016 STATE_LOCK(ctx); 4017 ctx->ifc_flags |= IFC_QFLUSH; 4018 STATE_UNLOCK(ctx); 4019 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4020 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4021 iflib_txq_check_drain(txq, 0); 4022 STATE_LOCK(ctx); 4023 ctx->ifc_flags &= ~IFC_QFLUSH; 4024 STATE_UNLOCK(ctx); 4025 4026 if_qflush(ifp); 4027 } 4028 4029 4030 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4031 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4032 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 4033 4034 static int 4035 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4036 { 4037 if_ctx_t ctx = if_getsoftc(ifp); 4038 struct ifreq *ifr = (struct ifreq *)data; 4039 #if defined(INET) || defined(INET6) 4040 struct ifaddr *ifa = (struct ifaddr *)data; 4041 #endif 4042 bool avoid_reset = FALSE; 4043 int err = 0, reinit = 0, bits; 4044 4045 switch (command) { 4046 case SIOCSIFADDR: 4047 #ifdef INET 4048 if (ifa->ifa_addr->sa_family == AF_INET) 4049 avoid_reset = TRUE; 4050 #endif 4051 #ifdef INET6 4052 if (ifa->ifa_addr->sa_family == AF_INET6) 4053 avoid_reset = TRUE; 4054 #endif 4055 /* 4056 ** Calling init results in link renegotiation, 4057 ** so we avoid doing it when possible. 4058 */ 4059 if (avoid_reset) { 4060 if_setflagbits(ifp, IFF_UP,0); 4061 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4062 reinit = 1; 4063 #ifdef INET 4064 if (!(if_getflags(ifp) & IFF_NOARP)) 4065 arp_ifinit(ifp, ifa); 4066 #endif 4067 } else 4068 err = ether_ioctl(ifp, command, data); 4069 break; 4070 case SIOCSIFMTU: 4071 CTX_LOCK(ctx); 4072 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4073 CTX_UNLOCK(ctx); 4074 break; 4075 } 4076 bits = if_getdrvflags(ifp); 4077 /* stop the driver and free any clusters before proceeding */ 4078 iflib_stop(ctx); 4079 4080 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4081 STATE_LOCK(ctx); 4082 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4083 ctx->ifc_flags |= IFC_MULTISEG; 4084 else 4085 ctx->ifc_flags &= ~IFC_MULTISEG; 4086 STATE_UNLOCK(ctx); 4087 err = if_setmtu(ifp, ifr->ifr_mtu); 4088 } 4089 iflib_init_locked(ctx); 4090 STATE_LOCK(ctx); 4091 if_setdrvflags(ifp, bits); 4092 STATE_UNLOCK(ctx); 4093 CTX_UNLOCK(ctx); 4094 break; 4095 case SIOCSIFFLAGS: 4096 CTX_LOCK(ctx); 4097 if (if_getflags(ifp) & IFF_UP) { 4098 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4099 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4100 (IFF_PROMISC | IFF_ALLMULTI)) { 4101 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4102 } 4103 } else 4104 reinit = 1; 4105 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4106 iflib_stop(ctx); 4107 } 4108 ctx->ifc_if_flags = if_getflags(ifp); 4109 CTX_UNLOCK(ctx); 4110 break; 4111 case SIOCADDMULTI: 4112 case SIOCDELMULTI: 4113 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4114 CTX_LOCK(ctx); 4115 IFDI_INTR_DISABLE(ctx); 4116 IFDI_MULTI_SET(ctx); 4117 IFDI_INTR_ENABLE(ctx); 4118 CTX_UNLOCK(ctx); 4119 } 4120 break; 4121 case SIOCSIFMEDIA: 4122 CTX_LOCK(ctx); 4123 IFDI_MEDIA_SET(ctx); 4124 CTX_UNLOCK(ctx); 4125 /* falls thru */ 4126 case SIOCGIFMEDIA: 4127 case SIOCGIFXMEDIA: 4128 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 4129 break; 4130 case SIOCGI2C: 4131 { 4132 struct ifi2creq i2c; 4133 4134 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4135 if (err != 0) 4136 break; 4137 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4138 err = EINVAL; 4139 break; 4140 } 4141 if (i2c.len > sizeof(i2c.data)) { 4142 err = EINVAL; 4143 break; 4144 } 4145 4146 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4147 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4148 sizeof(i2c)); 4149 break; 4150 } 4151 case SIOCSIFCAP: 4152 { 4153 int mask, setmask; 4154 4155 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 4156 setmask = 0; 4157 #ifdef TCP_OFFLOAD 4158 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4159 #endif 4160 setmask |= (mask & IFCAP_FLAGS); 4161 4162 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 4163 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4164 if ((mask & IFCAP_WOL) && 4165 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 4166 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 4167 if_vlancap(ifp); 4168 /* 4169 * want to ensure that traffic has stopped before we change any of the flags 4170 */ 4171 if (setmask) { 4172 CTX_LOCK(ctx); 4173 bits = if_getdrvflags(ifp); 4174 if (bits & IFF_DRV_RUNNING) 4175 iflib_stop(ctx); 4176 STATE_LOCK(ctx); 4177 if_togglecapenable(ifp, setmask); 4178 STATE_UNLOCK(ctx); 4179 if (bits & IFF_DRV_RUNNING) 4180 iflib_init_locked(ctx); 4181 STATE_LOCK(ctx); 4182 if_setdrvflags(ifp, bits); 4183 STATE_UNLOCK(ctx); 4184 CTX_UNLOCK(ctx); 4185 } 4186 break; 4187 } 4188 case SIOCGPRIVATE_0: 4189 case SIOCSDRVSPEC: 4190 case SIOCGDRVSPEC: 4191 CTX_LOCK(ctx); 4192 err = IFDI_PRIV_IOCTL(ctx, command, data); 4193 CTX_UNLOCK(ctx); 4194 break; 4195 default: 4196 err = ether_ioctl(ifp, command, data); 4197 break; 4198 } 4199 if (reinit) 4200 iflib_if_init(ctx); 4201 return (err); 4202 } 4203 4204 static uint64_t 4205 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4206 { 4207 if_ctx_t ctx = if_getsoftc(ifp); 4208 4209 return (IFDI_GET_COUNTER(ctx, cnt)); 4210 } 4211 4212 /********************************************************************* 4213 * 4214 * OTHER FUNCTIONS EXPORTED TO THE STACK 4215 * 4216 **********************************************************************/ 4217 4218 static void 4219 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4220 { 4221 if_ctx_t ctx = if_getsoftc(ifp); 4222 4223 if ((void *)ctx != arg) 4224 return; 4225 4226 if ((vtag == 0) || (vtag > 4095)) 4227 return; 4228 4229 CTX_LOCK(ctx); 4230 IFDI_VLAN_REGISTER(ctx, vtag); 4231 /* Re-init to load the changes */ 4232 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4233 iflib_if_init_locked(ctx); 4234 CTX_UNLOCK(ctx); 4235 } 4236 4237 static void 4238 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4239 { 4240 if_ctx_t ctx = if_getsoftc(ifp); 4241 4242 if ((void *)ctx != arg) 4243 return; 4244 4245 if ((vtag == 0) || (vtag > 4095)) 4246 return; 4247 4248 CTX_LOCK(ctx); 4249 IFDI_VLAN_UNREGISTER(ctx, vtag); 4250 /* Re-init to load the changes */ 4251 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4252 iflib_if_init_locked(ctx); 4253 CTX_UNLOCK(ctx); 4254 } 4255 4256 static void 4257 iflib_led_func(void *arg, int onoff) 4258 { 4259 if_ctx_t ctx = arg; 4260 4261 CTX_LOCK(ctx); 4262 IFDI_LED_FUNC(ctx, onoff); 4263 CTX_UNLOCK(ctx); 4264 } 4265 4266 /********************************************************************* 4267 * 4268 * BUS FUNCTION DEFINITIONS 4269 * 4270 **********************************************************************/ 4271 4272 int 4273 iflib_device_probe(device_t dev) 4274 { 4275 pci_vendor_info_t *ent; 4276 4277 uint16_t pci_vendor_id, pci_device_id; 4278 uint16_t pci_subvendor_id, pci_subdevice_id; 4279 uint16_t pci_rev_id; 4280 if_shared_ctx_t sctx; 4281 4282 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4283 return (ENOTSUP); 4284 4285 pci_vendor_id = pci_get_vendor(dev); 4286 pci_device_id = pci_get_device(dev); 4287 pci_subvendor_id = pci_get_subvendor(dev); 4288 pci_subdevice_id = pci_get_subdevice(dev); 4289 pci_rev_id = pci_get_revid(dev); 4290 if (sctx->isc_parse_devinfo != NULL) 4291 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4292 4293 ent = sctx->isc_vendor_info; 4294 while (ent->pvi_vendor_id != 0) { 4295 if (pci_vendor_id != ent->pvi_vendor_id) { 4296 ent++; 4297 continue; 4298 } 4299 if ((pci_device_id == ent->pvi_device_id) && 4300 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4301 (ent->pvi_subvendor_id == 0)) && 4302 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4303 (ent->pvi_subdevice_id == 0)) && 4304 ((pci_rev_id == ent->pvi_rev_id) || 4305 (ent->pvi_rev_id == 0))) { 4306 4307 device_set_desc_copy(dev, ent->pvi_name); 4308 /* this needs to be changed to zero if the bus probing code 4309 * ever stops re-probing on best match because the sctx 4310 * may have its values over written by register calls 4311 * in subsequent probes 4312 */ 4313 return (BUS_PROBE_DEFAULT); 4314 } 4315 ent++; 4316 } 4317 return (ENXIO); 4318 } 4319 4320 static void 4321 iflib_reset_qvalues(if_ctx_t ctx) 4322 { 4323 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4324 if_shared_ctx_t sctx = ctx->ifc_sctx; 4325 device_t dev = ctx->ifc_dev; 4326 int i; 4327 4328 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES; 4329 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH; 4330 /* 4331 * XXX sanity check that ntxd & nrxd are a power of 2 4332 */ 4333 if (ctx->ifc_sysctl_ntxqs != 0) 4334 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4335 if (ctx->ifc_sysctl_nrxqs != 0) 4336 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4337 4338 for (i = 0; i < sctx->isc_ntxqs; i++) { 4339 if (ctx->ifc_sysctl_ntxds[i] != 0) 4340 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4341 else 4342 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4343 } 4344 4345 for (i = 0; i < sctx->isc_nrxqs; i++) { 4346 if (ctx->ifc_sysctl_nrxds[i] != 0) 4347 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4348 else 4349 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4350 } 4351 4352 for (i = 0; i < sctx->isc_nrxqs; i++) { 4353 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4354 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4355 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4356 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4357 } 4358 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4359 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4360 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4361 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4362 } 4363 } 4364 4365 for (i = 0; i < sctx->isc_ntxqs; i++) { 4366 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4367 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4368 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4369 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4370 } 4371 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4372 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4373 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4374 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4375 } 4376 } 4377 } 4378 4379 int 4380 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4381 { 4382 int err, rid, msix; 4383 if_ctx_t ctx; 4384 if_t ifp; 4385 if_softc_ctx_t scctx; 4386 int i; 4387 uint16_t main_txq; 4388 uint16_t main_rxq; 4389 4390 4391 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4392 4393 if (sc == NULL) { 4394 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4395 device_set_softc(dev, ctx); 4396 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4397 } 4398 4399 ctx->ifc_sctx = sctx; 4400 ctx->ifc_dev = dev; 4401 ctx->ifc_softc = sc; 4402 4403 if ((err = iflib_register(ctx)) != 0) { 4404 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4405 free(sc, M_IFLIB); 4406 free(ctx, M_IFLIB); 4407 device_printf(dev, "iflib_register failed %d\n", err); 4408 return (err); 4409 } 4410 iflib_add_device_sysctl_pre(ctx); 4411 4412 scctx = &ctx->ifc_softc_ctx; 4413 ifp = ctx->ifc_ifp; 4414 4415 iflib_reset_qvalues(ctx); 4416 CTX_LOCK(ctx); 4417 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4418 CTX_UNLOCK(ctx); 4419 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4420 return (err); 4421 } 4422 _iflib_pre_assert(scctx); 4423 ctx->ifc_txrx = *scctx->isc_txrx; 4424 4425 #ifdef INVARIANTS 4426 MPASS(scctx->isc_capabilities); 4427 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4428 MPASS(scctx->isc_tx_csum_flags); 4429 #endif 4430 4431 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS); 4432 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4433 4434 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4435 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4436 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4437 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4438 4439 #ifdef ACPI_DMAR 4440 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4441 ctx->ifc_flags |= IFC_DMAR; 4442 #elif !(defined(__i386__) || defined(__amd64__)) 4443 /* set unconditionally for !x86 */ 4444 ctx->ifc_flags |= IFC_DMAR; 4445 #endif 4446 4447 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4448 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4449 4450 /* XXX change for per-queue sizes */ 4451 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4452 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4453 for (i = 0; i < sctx->isc_nrxqs; i++) { 4454 if (!powerof2(scctx->isc_nrxd[i])) { 4455 /* round down instead? */ 4456 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4457 err = EINVAL; 4458 goto fail; 4459 } 4460 } 4461 for (i = 0; i < sctx->isc_ntxqs; i++) { 4462 if (!powerof2(scctx->isc_ntxd[i])) { 4463 device_printf(dev, 4464 "# tx descriptors must be a power of 2"); 4465 err = EINVAL; 4466 goto fail; 4467 } 4468 } 4469 4470 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4471 MAX_SINGLE_PACKET_FRACTION) 4472 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4473 MAX_SINGLE_PACKET_FRACTION); 4474 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4475 MAX_SINGLE_PACKET_FRACTION) 4476 scctx->isc_tx_tso_segments_max = max(1, 4477 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4478 4479 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4480 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4481 /* 4482 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4483 * but some MACs do. 4484 */ 4485 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4486 IP_MAXPACKET)); 4487 /* 4488 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4489 * into account. In the worst case, each of these calls will 4490 * add another mbuf and, thus, the requirement for another DMA 4491 * segment. So for best performance, it doesn't make sense to 4492 * advertize a maximum of TSO segments that typically will 4493 * require defragmentation in iflib_encap(). 4494 */ 4495 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4496 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4497 } 4498 if (scctx->isc_rss_table_size == 0) 4499 scctx->isc_rss_table_size = 64; 4500 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4501 4502 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4503 /* XXX format name */ 4504 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4505 4506 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4507 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4508 device_printf(dev, "Unable to fetch CPU list\n"); 4509 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4510 } 4511 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4512 4513 /* 4514 ** Now setup MSI or MSI/X, should 4515 ** return us the number of supported 4516 ** vectors. (Will be 1 for MSI) 4517 */ 4518 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4519 msix = scctx->isc_vectors; 4520 } else if (scctx->isc_msix_bar != 0) 4521 /* 4522 * The simple fact that isc_msix_bar is not 0 does not mean we 4523 * we have a good value there that is known to work. 4524 */ 4525 msix = iflib_msix_init(ctx); 4526 else { 4527 scctx->isc_vectors = 1; 4528 scctx->isc_ntxqsets = 1; 4529 scctx->isc_nrxqsets = 1; 4530 scctx->isc_intr = IFLIB_INTR_LEGACY; 4531 msix = 0; 4532 } 4533 /* Get memory for the station queues */ 4534 if ((err = iflib_queues_alloc(ctx))) { 4535 device_printf(dev, "Unable to allocate queue memory\n"); 4536 goto fail; 4537 } 4538 4539 if ((err = iflib_qset_structures_setup(ctx))) 4540 goto fail_queues; 4541 4542 /* 4543 * Group taskqueues aren't properly set up until SMP is started, 4544 * so we disable interrupts until we can handle them post 4545 * SI_SUB_SMP. 4546 * 4547 * XXX: disabling interrupts doesn't actually work, at least for 4548 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4549 * we do null handling and depend on this not causing too large an 4550 * interrupt storm. 4551 */ 4552 IFDI_INTR_DISABLE(ctx); 4553 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4554 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4555 goto fail_intr_free; 4556 } 4557 if (msix <= 1) { 4558 rid = 0; 4559 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4560 MPASS(msix == 1); 4561 rid = 1; 4562 } 4563 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4564 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4565 goto fail_intr_free; 4566 } 4567 } 4568 4569 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4570 4571 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4572 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4573 goto fail_detach; 4574 } 4575 4576 /* 4577 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4578 * This must appear after the call to ether_ifattach() because 4579 * ether_ifattach() sets if_hdrlen to the default value. 4580 */ 4581 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4582 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4583 4584 if ((err = iflib_netmap_attach(ctx))) { 4585 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4586 goto fail_detach; 4587 } 4588 *ctxp = ctx; 4589 4590 NETDUMP_SET(ctx->ifc_ifp, iflib); 4591 4592 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4593 iflib_add_device_sysctl_post(ctx); 4594 ctx->ifc_flags |= IFC_INIT_DONE; 4595 CTX_UNLOCK(ctx); 4596 return (0); 4597 fail_detach: 4598 ether_ifdetach(ctx->ifc_ifp); 4599 fail_intr_free: 4600 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4601 pci_release_msi(ctx->ifc_dev); 4602 fail_queues: 4603 iflib_tx_structures_free(ctx); 4604 iflib_rx_structures_free(ctx); 4605 fail: 4606 IFDI_DETACH(ctx); 4607 CTX_UNLOCK(ctx); 4608 return (err); 4609 } 4610 4611 int 4612 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4613 struct iflib_cloneattach_ctx *clctx) 4614 { 4615 int err; 4616 if_ctx_t ctx; 4617 if_t ifp; 4618 if_softc_ctx_t scctx; 4619 int i; 4620 void *sc; 4621 uint16_t main_txq; 4622 uint16_t main_rxq; 4623 4624 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4625 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4626 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4627 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4628 ctx->ifc_flags |= IFC_PSEUDO; 4629 4630 ctx->ifc_sctx = sctx; 4631 ctx->ifc_softc = sc; 4632 ctx->ifc_dev = dev; 4633 4634 if ((err = iflib_register(ctx)) != 0) { 4635 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4636 free(sc, M_IFLIB); 4637 free(ctx, M_IFLIB); 4638 return (err); 4639 } 4640 iflib_add_device_sysctl_pre(ctx); 4641 4642 scctx = &ctx->ifc_softc_ctx; 4643 ifp = ctx->ifc_ifp; 4644 4645 /* 4646 * XXX sanity check that ntxd & nrxd are a power of 2 4647 */ 4648 iflib_reset_qvalues(ctx); 4649 4650 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4651 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4652 return (err); 4653 } 4654 if (sctx->isc_flags & IFLIB_GEN_MAC) 4655 iflib_gen_mac(ctx); 4656 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4657 clctx->cc_params)) != 0) { 4658 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4659 return (err); 4660 } 4661 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4662 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 4663 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO); 4664 4665 #ifdef INVARIANTS 4666 MPASS(scctx->isc_capabilities); 4667 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4668 MPASS(scctx->isc_tx_csum_flags); 4669 #endif 4670 4671 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4672 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4673 4674 ifp->if_flags |= IFF_NOGROUP; 4675 if (sctx->isc_flags & IFLIB_PSEUDO) { 4676 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4677 4678 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4679 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4680 goto fail_detach; 4681 } 4682 *ctxp = ctx; 4683 4684 /* 4685 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4686 * This must appear after the call to ether_ifattach() because 4687 * ether_ifattach() sets if_hdrlen to the default value. 4688 */ 4689 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4690 if_setifheaderlen(ifp, 4691 sizeof(struct ether_vlan_header)); 4692 4693 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4694 iflib_add_device_sysctl_post(ctx); 4695 ctx->ifc_flags |= IFC_INIT_DONE; 4696 return (0); 4697 } 4698 _iflib_pre_assert(scctx); 4699 ctx->ifc_txrx = *scctx->isc_txrx; 4700 4701 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4702 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4703 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4704 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4705 4706 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4707 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4708 4709 /* XXX change for per-queue sizes */ 4710 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4711 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4712 for (i = 0; i < sctx->isc_nrxqs; i++) { 4713 if (!powerof2(scctx->isc_nrxd[i])) { 4714 /* round down instead? */ 4715 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4716 err = EINVAL; 4717 goto fail; 4718 } 4719 } 4720 for (i = 0; i < sctx->isc_ntxqs; i++) { 4721 if (!powerof2(scctx->isc_ntxd[i])) { 4722 device_printf(dev, 4723 "# tx descriptors must be a power of 2"); 4724 err = EINVAL; 4725 goto fail; 4726 } 4727 } 4728 4729 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4730 MAX_SINGLE_PACKET_FRACTION) 4731 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4732 MAX_SINGLE_PACKET_FRACTION); 4733 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4734 MAX_SINGLE_PACKET_FRACTION) 4735 scctx->isc_tx_tso_segments_max = max(1, 4736 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4737 4738 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4739 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4740 /* 4741 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4742 * but some MACs do. 4743 */ 4744 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4745 IP_MAXPACKET)); 4746 /* 4747 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4748 * into account. In the worst case, each of these calls will 4749 * add another mbuf and, thus, the requirement for another DMA 4750 * segment. So for best performance, it doesn't make sense to 4751 * advertize a maximum of TSO segments that typically will 4752 * require defragmentation in iflib_encap(). 4753 */ 4754 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4755 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4756 } 4757 if (scctx->isc_rss_table_size == 0) 4758 scctx->isc_rss_table_size = 64; 4759 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4760 4761 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4762 /* XXX format name */ 4763 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4764 4765 /* XXX --- can support > 1 -- but keep it simple for now */ 4766 scctx->isc_intr = IFLIB_INTR_LEGACY; 4767 4768 /* Get memory for the station queues */ 4769 if ((err = iflib_queues_alloc(ctx))) { 4770 device_printf(dev, "Unable to allocate queue memory\n"); 4771 goto fail; 4772 } 4773 4774 if ((err = iflib_qset_structures_setup(ctx))) { 4775 device_printf(dev, "qset structure setup failed %d\n", err); 4776 goto fail_queues; 4777 } 4778 4779 /* 4780 * XXX What if anything do we want to do about interrupts? 4781 */ 4782 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4783 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4784 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4785 goto fail_detach; 4786 } 4787 4788 /* 4789 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4790 * This must appear after the call to ether_ifattach() because 4791 * ether_ifattach() sets if_hdrlen to the default value. 4792 */ 4793 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4794 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4795 4796 /* XXX handle more than one queue */ 4797 for (i = 0; i < scctx->isc_nrxqsets; i++) 4798 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4799 4800 *ctxp = ctx; 4801 4802 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4803 iflib_add_device_sysctl_post(ctx); 4804 ctx->ifc_flags |= IFC_INIT_DONE; 4805 return (0); 4806 fail_detach: 4807 ether_ifdetach(ctx->ifc_ifp); 4808 fail_queues: 4809 iflib_tx_structures_free(ctx); 4810 iflib_rx_structures_free(ctx); 4811 fail: 4812 IFDI_DETACH(ctx); 4813 return (err); 4814 } 4815 4816 int 4817 iflib_pseudo_deregister(if_ctx_t ctx) 4818 { 4819 if_t ifp = ctx->ifc_ifp; 4820 iflib_txq_t txq; 4821 iflib_rxq_t rxq; 4822 int i, j; 4823 struct taskqgroup *tqg; 4824 iflib_fl_t fl; 4825 4826 /* Unregister VLAN events */ 4827 if (ctx->ifc_vlan_attach_event != NULL) 4828 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4829 if (ctx->ifc_vlan_detach_event != NULL) 4830 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4831 4832 ether_ifdetach(ifp); 4833 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4834 CTX_LOCK_DESTROY(ctx); 4835 /* XXX drain any dependent tasks */ 4836 tqg = qgroup_if_io_tqg; 4837 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4838 callout_drain(&txq->ift_timer); 4839 if (txq->ift_task.gt_uniq != NULL) 4840 taskqgroup_detach(tqg, &txq->ift_task); 4841 } 4842 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4843 if (rxq->ifr_task.gt_uniq != NULL) 4844 taskqgroup_detach(tqg, &rxq->ifr_task); 4845 4846 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4847 free(fl->ifl_rx_bitmap, M_IFLIB); 4848 } 4849 tqg = qgroup_if_config_tqg; 4850 if (ctx->ifc_admin_task.gt_uniq != NULL) 4851 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4852 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4853 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4854 4855 if_free(ifp); 4856 4857 iflib_tx_structures_free(ctx); 4858 iflib_rx_structures_free(ctx); 4859 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4860 free(ctx->ifc_softc, M_IFLIB); 4861 free(ctx, M_IFLIB); 4862 return (0); 4863 } 4864 4865 int 4866 iflib_device_attach(device_t dev) 4867 { 4868 if_ctx_t ctx; 4869 if_shared_ctx_t sctx; 4870 4871 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4872 return (ENOTSUP); 4873 4874 pci_enable_busmaster(dev); 4875 4876 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4877 } 4878 4879 int 4880 iflib_device_deregister(if_ctx_t ctx) 4881 { 4882 if_t ifp = ctx->ifc_ifp; 4883 iflib_txq_t txq; 4884 iflib_rxq_t rxq; 4885 device_t dev = ctx->ifc_dev; 4886 int i, j; 4887 struct taskqgroup *tqg; 4888 iflib_fl_t fl; 4889 4890 /* Make sure VLANS are not using driver */ 4891 if (if_vlantrunkinuse(ifp)) { 4892 device_printf(dev,"Vlan in use, detach first\n"); 4893 return (EBUSY); 4894 } 4895 4896 CTX_LOCK(ctx); 4897 ctx->ifc_in_detach = 1; 4898 iflib_stop(ctx); 4899 CTX_UNLOCK(ctx); 4900 4901 /* Unregister VLAN events */ 4902 if (ctx->ifc_vlan_attach_event != NULL) 4903 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4904 if (ctx->ifc_vlan_detach_event != NULL) 4905 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4906 4907 iflib_netmap_detach(ifp); 4908 ether_ifdetach(ifp); 4909 if (ctx->ifc_led_dev != NULL) 4910 led_destroy(ctx->ifc_led_dev); 4911 /* XXX drain any dependent tasks */ 4912 tqg = qgroup_if_io_tqg; 4913 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4914 callout_drain(&txq->ift_timer); 4915 if (txq->ift_task.gt_uniq != NULL) 4916 taskqgroup_detach(tqg, &txq->ift_task); 4917 } 4918 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4919 if (rxq->ifr_task.gt_uniq != NULL) 4920 taskqgroup_detach(tqg, &rxq->ifr_task); 4921 4922 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4923 free(fl->ifl_rx_bitmap, M_IFLIB); 4924 4925 } 4926 tqg = qgroup_if_config_tqg; 4927 if (ctx->ifc_admin_task.gt_uniq != NULL) 4928 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4929 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4930 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4931 CTX_LOCK(ctx); 4932 IFDI_DETACH(ctx); 4933 CTX_UNLOCK(ctx); 4934 4935 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4936 CTX_LOCK_DESTROY(ctx); 4937 device_set_softc(ctx->ifc_dev, NULL); 4938 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4939 pci_release_msi(dev); 4940 } 4941 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4942 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4943 } 4944 if (ctx->ifc_msix_mem != NULL) { 4945 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4946 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4947 ctx->ifc_msix_mem = NULL; 4948 } 4949 4950 bus_generic_detach(dev); 4951 if_free(ifp); 4952 4953 iflib_tx_structures_free(ctx); 4954 iflib_rx_structures_free(ctx); 4955 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4956 free(ctx->ifc_softc, M_IFLIB); 4957 free(ctx, M_IFLIB); 4958 return (0); 4959 } 4960 4961 4962 int 4963 iflib_device_detach(device_t dev) 4964 { 4965 if_ctx_t ctx = device_get_softc(dev); 4966 4967 return (iflib_device_deregister(ctx)); 4968 } 4969 4970 int 4971 iflib_device_suspend(device_t dev) 4972 { 4973 if_ctx_t ctx = device_get_softc(dev); 4974 4975 CTX_LOCK(ctx); 4976 IFDI_SUSPEND(ctx); 4977 CTX_UNLOCK(ctx); 4978 4979 return bus_generic_suspend(dev); 4980 } 4981 int 4982 iflib_device_shutdown(device_t dev) 4983 { 4984 if_ctx_t ctx = device_get_softc(dev); 4985 4986 CTX_LOCK(ctx); 4987 IFDI_SHUTDOWN(ctx); 4988 CTX_UNLOCK(ctx); 4989 4990 return bus_generic_suspend(dev); 4991 } 4992 4993 4994 int 4995 iflib_device_resume(device_t dev) 4996 { 4997 if_ctx_t ctx = device_get_softc(dev); 4998 iflib_txq_t txq = ctx->ifc_txqs; 4999 5000 CTX_LOCK(ctx); 5001 IFDI_RESUME(ctx); 5002 iflib_init_locked(ctx); 5003 CTX_UNLOCK(ctx); 5004 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5005 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5006 5007 return (bus_generic_resume(dev)); 5008 } 5009 5010 int 5011 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5012 { 5013 int error; 5014 if_ctx_t ctx = device_get_softc(dev); 5015 5016 CTX_LOCK(ctx); 5017 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5018 CTX_UNLOCK(ctx); 5019 5020 return (error); 5021 } 5022 5023 void 5024 iflib_device_iov_uninit(device_t dev) 5025 { 5026 if_ctx_t ctx = device_get_softc(dev); 5027 5028 CTX_LOCK(ctx); 5029 IFDI_IOV_UNINIT(ctx); 5030 CTX_UNLOCK(ctx); 5031 } 5032 5033 int 5034 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5035 { 5036 int error; 5037 if_ctx_t ctx = device_get_softc(dev); 5038 5039 CTX_LOCK(ctx); 5040 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5041 CTX_UNLOCK(ctx); 5042 5043 return (error); 5044 } 5045 5046 /********************************************************************* 5047 * 5048 * MODULE FUNCTION DEFINITIONS 5049 * 5050 **********************************************************************/ 5051 5052 /* 5053 * - Start a fast taskqueue thread for each core 5054 * - Start a taskqueue for control operations 5055 */ 5056 static int 5057 iflib_module_init(void) 5058 { 5059 return (0); 5060 } 5061 5062 static int 5063 iflib_module_event_handler(module_t mod, int what, void *arg) 5064 { 5065 int err; 5066 5067 switch (what) { 5068 case MOD_LOAD: 5069 if ((err = iflib_module_init()) != 0) 5070 return (err); 5071 break; 5072 case MOD_UNLOAD: 5073 return (EBUSY); 5074 default: 5075 return (EOPNOTSUPP); 5076 } 5077 5078 return (0); 5079 } 5080 5081 /********************************************************************* 5082 * 5083 * PUBLIC FUNCTION DEFINITIONS 5084 * ordered as in iflib.h 5085 * 5086 **********************************************************************/ 5087 5088 5089 static void 5090 _iflib_assert(if_shared_ctx_t sctx) 5091 { 5092 MPASS(sctx->isc_tx_maxsize); 5093 MPASS(sctx->isc_tx_maxsegsize); 5094 5095 MPASS(sctx->isc_rx_maxsize); 5096 MPASS(sctx->isc_rx_nsegments); 5097 MPASS(sctx->isc_rx_maxsegsize); 5098 5099 MPASS(sctx->isc_nrxd_min[0]); 5100 MPASS(sctx->isc_nrxd_max[0]); 5101 MPASS(sctx->isc_nrxd_default[0]); 5102 MPASS(sctx->isc_ntxd_min[0]); 5103 MPASS(sctx->isc_ntxd_max[0]); 5104 MPASS(sctx->isc_ntxd_default[0]); 5105 } 5106 5107 static void 5108 _iflib_pre_assert(if_softc_ctx_t scctx) 5109 { 5110 5111 MPASS(scctx->isc_txrx->ift_txd_encap); 5112 MPASS(scctx->isc_txrx->ift_txd_flush); 5113 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5114 MPASS(scctx->isc_txrx->ift_rxd_available); 5115 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5116 MPASS(scctx->isc_txrx->ift_rxd_refill); 5117 MPASS(scctx->isc_txrx->ift_rxd_flush); 5118 } 5119 5120 static int 5121 iflib_register(if_ctx_t ctx) 5122 { 5123 if_shared_ctx_t sctx = ctx->ifc_sctx; 5124 driver_t *driver = sctx->isc_driver; 5125 device_t dev = ctx->ifc_dev; 5126 if_t ifp; 5127 5128 _iflib_assert(sctx); 5129 5130 CTX_LOCK_INIT(ctx); 5131 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5132 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 5133 if (ifp == NULL) { 5134 device_printf(dev, "can not allocate ifnet structure\n"); 5135 return (ENOMEM); 5136 } 5137 5138 /* 5139 * Initialize our context's device specific methods 5140 */ 5141 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5142 kobj_class_compile((kobj_class_t) driver); 5143 driver->refs++; 5144 5145 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5146 if_setsoftc(ifp, ctx); 5147 if_setdev(ifp, dev); 5148 if_setinitfn(ifp, iflib_if_init); 5149 if_setioctlfn(ifp, iflib_if_ioctl); 5150 if_settransmitfn(ifp, iflib_if_transmit); 5151 if_setqflushfn(ifp, iflib_if_qflush); 5152 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5153 5154 ctx->ifc_vlan_attach_event = 5155 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5156 EVENTHANDLER_PRI_FIRST); 5157 ctx->ifc_vlan_detach_event = 5158 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5159 EVENTHANDLER_PRI_FIRST); 5160 5161 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 5162 iflib_media_change, iflib_media_status); 5163 5164 return (0); 5165 } 5166 5167 5168 static int 5169 iflib_queues_alloc(if_ctx_t ctx) 5170 { 5171 if_shared_ctx_t sctx = ctx->ifc_sctx; 5172 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5173 device_t dev = ctx->ifc_dev; 5174 int nrxqsets = scctx->isc_nrxqsets; 5175 int ntxqsets = scctx->isc_ntxqsets; 5176 iflib_txq_t txq; 5177 iflib_rxq_t rxq; 5178 iflib_fl_t fl = NULL; 5179 int i, j, cpu, err, txconf, rxconf; 5180 iflib_dma_info_t ifdip; 5181 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5182 uint32_t *txqsizes = scctx->isc_txqsizes; 5183 uint8_t nrxqs = sctx->isc_nrxqs; 5184 uint8_t ntxqs = sctx->isc_ntxqs; 5185 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5186 caddr_t *vaddrs; 5187 uint64_t *paddrs; 5188 5189 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5190 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5191 5192 /* Allocate the TX ring struct memory */ 5193 if (!(ctx->ifc_txqs = 5194 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5195 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5196 device_printf(dev, "Unable to allocate TX ring memory\n"); 5197 err = ENOMEM; 5198 goto fail; 5199 } 5200 5201 /* Now allocate the RX */ 5202 if (!(ctx->ifc_rxqs = 5203 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5204 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5205 device_printf(dev, "Unable to allocate RX ring memory\n"); 5206 err = ENOMEM; 5207 goto rx_fail; 5208 } 5209 5210 txq = ctx->ifc_txqs; 5211 rxq = ctx->ifc_rxqs; 5212 5213 /* 5214 * XXX handle allocation failure 5215 */ 5216 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5217 /* Set up some basics */ 5218 5219 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 5220 device_printf(dev, "failed to allocate iflib_dma_info\n"); 5221 err = ENOMEM; 5222 goto err_tx_desc; 5223 } 5224 txq->ift_ifdi = ifdip; 5225 for (j = 0; j < ntxqs; j++, ifdip++) { 5226 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 5227 device_printf(dev, "Unable to allocate Descriptor memory\n"); 5228 err = ENOMEM; 5229 goto err_tx_desc; 5230 } 5231 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5232 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5233 } 5234 txq->ift_ctx = ctx; 5235 txq->ift_id = i; 5236 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5237 txq->ift_br_offset = 1; 5238 } else { 5239 txq->ift_br_offset = 0; 5240 } 5241 /* XXX fix this */ 5242 txq->ift_timer.c_cpu = cpu; 5243 5244 if (iflib_txsd_alloc(txq)) { 5245 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5246 err = ENOMEM; 5247 goto err_tx_desc; 5248 } 5249 5250 /* Initialize the TX lock */ 5251 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 5252 device_get_nameunit(dev), txq->ift_id); 5253 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5254 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5255 5256 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 5257 device_get_nameunit(dev), txq->ift_id); 5258 5259 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5260 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5261 if (err) { 5262 /* XXX free any allocated rings */ 5263 device_printf(dev, "Unable to allocate buf_ring\n"); 5264 goto err_tx_desc; 5265 } 5266 } 5267 5268 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5269 /* Set up some basics */ 5270 5271 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 5272 device_printf(dev, "failed to allocate iflib_dma_info\n"); 5273 err = ENOMEM; 5274 goto err_tx_desc; 5275 } 5276 5277 rxq->ifr_ifdi = ifdip; 5278 /* XXX this needs to be changed if #rx queues != #tx queues */ 5279 rxq->ifr_ntxqirq = 1; 5280 rxq->ifr_txqid[0] = i; 5281 for (j = 0; j < nrxqs; j++, ifdip++) { 5282 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 5283 device_printf(dev, "Unable to allocate Descriptor memory\n"); 5284 err = ENOMEM; 5285 goto err_tx_desc; 5286 } 5287 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5288 } 5289 rxq->ifr_ctx = ctx; 5290 rxq->ifr_id = i; 5291 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5292 rxq->ifr_fl_offset = 1; 5293 } else { 5294 rxq->ifr_fl_offset = 0; 5295 } 5296 rxq->ifr_nfl = nfree_lists; 5297 if (!(fl = 5298 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5299 device_printf(dev, "Unable to allocate free list memory\n"); 5300 err = ENOMEM; 5301 goto err_tx_desc; 5302 } 5303 rxq->ifr_fl = fl; 5304 for (j = 0; j < nfree_lists; j++) { 5305 fl[j].ifl_rxq = rxq; 5306 fl[j].ifl_id = j; 5307 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5308 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5309 } 5310 /* Allocate receive buffers for the ring*/ 5311 if (iflib_rxsd_alloc(rxq)) { 5312 device_printf(dev, 5313 "Critical Failure setting up receive buffers\n"); 5314 err = ENOMEM; 5315 goto err_rx_desc; 5316 } 5317 5318 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5319 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 5320 } 5321 5322 /* TXQs */ 5323 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5324 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5325 for (i = 0; i < ntxqsets; i++) { 5326 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5327 5328 for (j = 0; j < ntxqs; j++, di++) { 5329 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5330 paddrs[i*ntxqs + j] = di->idi_paddr; 5331 } 5332 } 5333 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5334 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 5335 iflib_tx_structures_free(ctx); 5336 free(vaddrs, M_IFLIB); 5337 free(paddrs, M_IFLIB); 5338 goto err_rx_desc; 5339 } 5340 free(vaddrs, M_IFLIB); 5341 free(paddrs, M_IFLIB); 5342 5343 /* RXQs */ 5344 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5345 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5346 for (i = 0; i < nrxqsets; i++) { 5347 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5348 5349 for (j = 0; j < nrxqs; j++, di++) { 5350 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5351 paddrs[i*nrxqs + j] = di->idi_paddr; 5352 } 5353 } 5354 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5355 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 5356 iflib_tx_structures_free(ctx); 5357 free(vaddrs, M_IFLIB); 5358 free(paddrs, M_IFLIB); 5359 goto err_rx_desc; 5360 } 5361 free(vaddrs, M_IFLIB); 5362 free(paddrs, M_IFLIB); 5363 5364 return (0); 5365 5366 /* XXX handle allocation failure changes */ 5367 err_rx_desc: 5368 err_tx_desc: 5369 rx_fail: 5370 if (ctx->ifc_rxqs != NULL) 5371 free(ctx->ifc_rxqs, M_IFLIB); 5372 ctx->ifc_rxqs = NULL; 5373 if (ctx->ifc_txqs != NULL) 5374 free(ctx->ifc_txqs, M_IFLIB); 5375 ctx->ifc_txqs = NULL; 5376 fail: 5377 return (err); 5378 } 5379 5380 static int 5381 iflib_tx_structures_setup(if_ctx_t ctx) 5382 { 5383 iflib_txq_t txq = ctx->ifc_txqs; 5384 int i; 5385 5386 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5387 iflib_txq_setup(txq); 5388 5389 return (0); 5390 } 5391 5392 static void 5393 iflib_tx_structures_free(if_ctx_t ctx) 5394 { 5395 iflib_txq_t txq = ctx->ifc_txqs; 5396 int i, j; 5397 5398 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5399 iflib_txq_destroy(txq); 5400 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 5401 iflib_dma_free(&txq->ift_ifdi[j]); 5402 } 5403 free(ctx->ifc_txqs, M_IFLIB); 5404 ctx->ifc_txqs = NULL; 5405 IFDI_QUEUES_FREE(ctx); 5406 } 5407 5408 /********************************************************************* 5409 * 5410 * Initialize all receive rings. 5411 * 5412 **********************************************************************/ 5413 static int 5414 iflib_rx_structures_setup(if_ctx_t ctx) 5415 { 5416 iflib_rxq_t rxq = ctx->ifc_rxqs; 5417 int q; 5418 #if defined(INET6) || defined(INET) 5419 int i, err; 5420 #endif 5421 5422 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5423 #if defined(INET6) || defined(INET) 5424 tcp_lro_free(&rxq->ifr_lc); 5425 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5426 TCP_LRO_ENTRIES, min(1024, 5427 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 5428 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 5429 goto fail; 5430 } 5431 rxq->ifr_lro_enabled = TRUE; 5432 #endif 5433 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5434 } 5435 return (0); 5436 #if defined(INET6) || defined(INET) 5437 fail: 5438 /* 5439 * Free RX software descriptors allocated so far, we will only handle 5440 * the rings that completed, the failing case will have 5441 * cleaned up for itself. 'q' failed, so its the terminus. 5442 */ 5443 rxq = ctx->ifc_rxqs; 5444 for (i = 0; i < q; ++i, rxq++) { 5445 iflib_rx_sds_free(rxq); 5446 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5447 } 5448 return (err); 5449 #endif 5450 } 5451 5452 /********************************************************************* 5453 * 5454 * Free all receive rings. 5455 * 5456 **********************************************************************/ 5457 static void 5458 iflib_rx_structures_free(if_ctx_t ctx) 5459 { 5460 iflib_rxq_t rxq = ctx->ifc_rxqs; 5461 5462 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5463 iflib_rx_sds_free(rxq); 5464 } 5465 } 5466 5467 static int 5468 iflib_qset_structures_setup(if_ctx_t ctx) 5469 { 5470 int err; 5471 5472 /* 5473 * It is expected that the caller takes care of freeing queues if this 5474 * fails. 5475 */ 5476 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5477 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5478 return (err); 5479 } 5480 5481 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5482 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5483 5484 return (err); 5485 } 5486 5487 int 5488 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5489 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5490 { 5491 5492 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5493 } 5494 5495 #ifdef SMP 5496 static int 5497 find_nth(if_ctx_t ctx, int qid) 5498 { 5499 cpuset_t cpus; 5500 int i, cpuid, eqid, count; 5501 5502 CPU_COPY(&ctx->ifc_cpus, &cpus); 5503 count = CPU_COUNT(&cpus); 5504 eqid = qid % count; 5505 /* clear up to the qid'th bit */ 5506 for (i = 0; i < eqid; i++) { 5507 cpuid = CPU_FFS(&cpus); 5508 MPASS(cpuid != 0); 5509 CPU_CLR(cpuid-1, &cpus); 5510 } 5511 cpuid = CPU_FFS(&cpus); 5512 MPASS(cpuid != 0); 5513 return (cpuid-1); 5514 } 5515 5516 #ifdef SCHED_ULE 5517 extern struct cpu_group *cpu_top; /* CPU topology */ 5518 5519 static int 5520 find_child_with_core(int cpu, struct cpu_group *grp) 5521 { 5522 int i; 5523 5524 if (grp->cg_children == 0) 5525 return -1; 5526 5527 MPASS(grp->cg_child); 5528 for (i = 0; i < grp->cg_children; i++) { 5529 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5530 return i; 5531 } 5532 5533 return -1; 5534 } 5535 5536 /* 5537 * Find the nth "close" core to the specified core 5538 * "close" is defined as the deepest level that shares 5539 * at least an L2 cache. With threads, this will be 5540 * threads on the same core. If the sahred cache is L3 5541 * or higher, simply returns the same core. 5542 */ 5543 static int 5544 find_close_core(int cpu, int core_offset) 5545 { 5546 struct cpu_group *grp; 5547 int i; 5548 int fcpu; 5549 cpuset_t cs; 5550 5551 grp = cpu_top; 5552 if (grp == NULL) 5553 return cpu; 5554 i = 0; 5555 while ((i = find_child_with_core(cpu, grp)) != -1) { 5556 /* If the child only has one cpu, don't descend */ 5557 if (grp->cg_child[i].cg_count <= 1) 5558 break; 5559 grp = &grp->cg_child[i]; 5560 } 5561 5562 /* If they don't share at least an L2 cache, use the same CPU */ 5563 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5564 return cpu; 5565 5566 /* Now pick one */ 5567 CPU_COPY(&grp->cg_mask, &cs); 5568 5569 /* Add the selected CPU offset to core offset. */ 5570 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5571 if (fcpu - 1 == cpu) 5572 break; 5573 CPU_CLR(fcpu - 1, &cs); 5574 } 5575 MPASS(fcpu); 5576 5577 core_offset += i; 5578 5579 CPU_COPY(&grp->cg_mask, &cs); 5580 for (i = core_offset % grp->cg_count; i > 0; i--) { 5581 MPASS(CPU_FFS(&cs)); 5582 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5583 } 5584 MPASS(CPU_FFS(&cs)); 5585 return CPU_FFS(&cs) - 1; 5586 } 5587 #else 5588 static int 5589 find_close_core(int cpu, int core_offset __unused) 5590 { 5591 return cpu; 5592 } 5593 #endif 5594 5595 static int 5596 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5597 { 5598 switch (type) { 5599 case IFLIB_INTR_TX: 5600 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5601 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5602 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5603 case IFLIB_INTR_RX: 5604 case IFLIB_INTR_RXTX: 5605 /* RX queues get the specified core */ 5606 return qid / CPU_COUNT(&ctx->ifc_cpus); 5607 default: 5608 return -1; 5609 } 5610 } 5611 #else 5612 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5613 #define find_close_core(cpuid, tid) CPU_FIRST() 5614 #define find_nth(ctx, gid) CPU_FIRST() 5615 #endif 5616 5617 /* Just to avoid copy/paste */ 5618 static inline int 5619 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid, 5620 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, const char *name) 5621 { 5622 int cpuid; 5623 int err, tid; 5624 5625 cpuid = find_nth(ctx, qid); 5626 tid = get_core_offset(ctx, type, qid); 5627 MPASS(tid >= 0); 5628 cpuid = find_close_core(cpuid, tid); 5629 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name); 5630 if (err) { 5631 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err); 5632 return (err); 5633 } 5634 #ifdef notyet 5635 if (cpuid > ctx->ifc_cpuid_highest) 5636 ctx->ifc_cpuid_highest = cpuid; 5637 #endif 5638 return 0; 5639 } 5640 5641 int 5642 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5643 iflib_intr_type_t type, driver_filter_t *filter, 5644 void *filter_arg, int qid, const char *name) 5645 { 5646 struct grouptask *gtask; 5647 struct taskqgroup *tqg; 5648 iflib_filter_info_t info; 5649 gtask_fn_t *fn; 5650 int tqrid, err; 5651 driver_filter_t *intr_fast; 5652 void *q; 5653 5654 info = &ctx->ifc_filter_info; 5655 tqrid = rid; 5656 5657 switch (type) { 5658 /* XXX merge tx/rx for netmap? */ 5659 case IFLIB_INTR_TX: 5660 q = &ctx->ifc_txqs[qid]; 5661 info = &ctx->ifc_txqs[qid].ift_filter_info; 5662 gtask = &ctx->ifc_txqs[qid].ift_task; 5663 tqg = qgroup_if_io_tqg; 5664 fn = _task_fn_tx; 5665 intr_fast = iflib_fast_intr; 5666 GROUPTASK_INIT(gtask, 0, fn, q); 5667 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5668 break; 5669 case IFLIB_INTR_RX: 5670 q = &ctx->ifc_rxqs[qid]; 5671 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5672 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5673 tqg = qgroup_if_io_tqg; 5674 fn = _task_fn_rx; 5675 intr_fast = iflib_fast_intr; 5676 GROUPTASK_INIT(gtask, 0, fn, q); 5677 break; 5678 case IFLIB_INTR_RXTX: 5679 q = &ctx->ifc_rxqs[qid]; 5680 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5681 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5682 tqg = qgroup_if_io_tqg; 5683 fn = _task_fn_rx; 5684 intr_fast = iflib_fast_intr_rxtx; 5685 GROUPTASK_INIT(gtask, 0, fn, q); 5686 break; 5687 case IFLIB_INTR_ADMIN: 5688 q = ctx; 5689 tqrid = -1; 5690 info = &ctx->ifc_filter_info; 5691 gtask = &ctx->ifc_admin_task; 5692 tqg = qgroup_if_config_tqg; 5693 fn = _task_fn_admin; 5694 intr_fast = iflib_fast_intr_ctx; 5695 break; 5696 default: 5697 panic("unknown net intr type"); 5698 } 5699 5700 info->ifi_filter = filter; 5701 info->ifi_filter_arg = filter_arg; 5702 info->ifi_task = gtask; 5703 info->ifi_ctx = q; 5704 5705 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5706 if (err != 0) { 5707 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 5708 return (err); 5709 } 5710 if (type == IFLIB_INTR_ADMIN) 5711 return (0); 5712 5713 if (tqrid != -1) { 5714 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name); 5715 if (err) 5716 return (err); 5717 } else { 5718 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5719 } 5720 5721 return (0); 5722 } 5723 5724 void 5725 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 5726 { 5727 struct grouptask *gtask; 5728 struct taskqgroup *tqg; 5729 gtask_fn_t *fn; 5730 void *q; 5731 int irq_num = -1; 5732 int err; 5733 5734 switch (type) { 5735 case IFLIB_INTR_TX: 5736 q = &ctx->ifc_txqs[qid]; 5737 gtask = &ctx->ifc_txqs[qid].ift_task; 5738 tqg = qgroup_if_io_tqg; 5739 fn = _task_fn_tx; 5740 if (irq != NULL) 5741 irq_num = rman_get_start(irq->ii_res); 5742 break; 5743 case IFLIB_INTR_RX: 5744 q = &ctx->ifc_rxqs[qid]; 5745 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5746 tqg = qgroup_if_io_tqg; 5747 fn = _task_fn_rx; 5748 if (irq != NULL) 5749 irq_num = rman_get_start(irq->ii_res); 5750 break; 5751 case IFLIB_INTR_IOV: 5752 q = ctx; 5753 gtask = &ctx->ifc_vflr_task; 5754 tqg = qgroup_if_config_tqg; 5755 fn = _task_fn_iov; 5756 break; 5757 default: 5758 panic("unknown net intr type"); 5759 } 5760 GROUPTASK_INIT(gtask, 0, fn, q); 5761 if (irq_num != -1) { 5762 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name); 5763 if (err) 5764 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5765 } 5766 else { 5767 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5768 } 5769 } 5770 5771 void 5772 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5773 { 5774 if (irq->ii_tag) 5775 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5776 5777 if (irq->ii_res) 5778 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5779 } 5780 5781 static int 5782 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 5783 { 5784 iflib_txq_t txq = ctx->ifc_txqs; 5785 iflib_rxq_t rxq = ctx->ifc_rxqs; 5786 if_irq_t irq = &ctx->ifc_legacy_irq; 5787 iflib_filter_info_t info; 5788 struct grouptask *gtask; 5789 struct taskqgroup *tqg; 5790 gtask_fn_t *fn; 5791 int tqrid; 5792 void *q; 5793 int err; 5794 5795 q = &ctx->ifc_rxqs[0]; 5796 info = &rxq[0].ifr_filter_info; 5797 gtask = &rxq[0].ifr_task; 5798 tqg = qgroup_if_io_tqg; 5799 tqrid = irq->ii_rid = *rid; 5800 fn = _task_fn_rx; 5801 5802 ctx->ifc_flags |= IFC_LEGACY; 5803 info->ifi_filter = filter; 5804 info->ifi_filter_arg = filter_arg; 5805 info->ifi_task = gtask; 5806 info->ifi_ctx = ctx; 5807 5808 /* We allocate a single interrupt resource */ 5809 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5810 return (err); 5811 GROUPTASK_INIT(gtask, 0, fn, q); 5812 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5813 5814 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5815 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx"); 5816 return (0); 5817 } 5818 5819 void 5820 iflib_led_create(if_ctx_t ctx) 5821 { 5822 5823 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5824 device_get_nameunit(ctx->ifc_dev)); 5825 } 5826 5827 void 5828 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5829 { 5830 5831 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5832 } 5833 5834 void 5835 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5836 { 5837 5838 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5839 } 5840 5841 void 5842 iflib_admin_intr_deferred(if_ctx_t ctx) 5843 { 5844 #ifdef INVARIANTS 5845 struct grouptask *gtask; 5846 5847 gtask = &ctx->ifc_admin_task; 5848 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5849 #endif 5850 5851 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5852 } 5853 5854 void 5855 iflib_iov_intr_deferred(if_ctx_t ctx) 5856 { 5857 5858 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5859 } 5860 5861 void 5862 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5863 { 5864 5865 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5866 } 5867 5868 void 5869 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 5870 const char *name) 5871 { 5872 5873 GROUPTASK_INIT(gtask, 0, fn, ctx); 5874 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5875 } 5876 5877 void 5878 iflib_config_gtask_deinit(struct grouptask *gtask) 5879 { 5880 5881 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5882 } 5883 5884 void 5885 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5886 { 5887 if_t ifp = ctx->ifc_ifp; 5888 iflib_txq_t txq = ctx->ifc_txqs; 5889 5890 if_setbaudrate(ifp, baudrate); 5891 if (baudrate >= IF_Gbps(10)) { 5892 STATE_LOCK(ctx); 5893 ctx->ifc_flags |= IFC_PREFETCH; 5894 STATE_UNLOCK(ctx); 5895 } 5896 /* If link down, disable watchdog */ 5897 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5898 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5899 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5900 } 5901 ctx->ifc_link_state = link_state; 5902 if_link_state_change(ifp, link_state); 5903 } 5904 5905 static int 5906 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5907 { 5908 int credits; 5909 #ifdef INVARIANTS 5910 int credits_pre = txq->ift_cidx_processed; 5911 #endif 5912 5913 if (ctx->isc_txd_credits_update == NULL) 5914 return (0); 5915 5916 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5917 return (0); 5918 5919 txq->ift_processed += credits; 5920 txq->ift_cidx_processed += credits; 5921 5922 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5923 if (txq->ift_cidx_processed >= txq->ift_size) 5924 txq->ift_cidx_processed -= txq->ift_size; 5925 return (credits); 5926 } 5927 5928 static int 5929 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5930 { 5931 5932 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5933 budget)); 5934 } 5935 5936 void 5937 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5938 const char *description, if_int_delay_info_t info, 5939 int offset, int value) 5940 { 5941 info->iidi_ctx = ctx; 5942 info->iidi_offset = offset; 5943 info->iidi_value = value; 5944 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5945 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5946 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5947 info, 0, iflib_sysctl_int_delay, "I", description); 5948 } 5949 5950 struct sx * 5951 iflib_ctx_lock_get(if_ctx_t ctx) 5952 { 5953 5954 return (&ctx->ifc_ctx_sx); 5955 } 5956 5957 static int 5958 iflib_msix_init(if_ctx_t ctx) 5959 { 5960 device_t dev = ctx->ifc_dev; 5961 if_shared_ctx_t sctx = ctx->ifc_sctx; 5962 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5963 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5964 int iflib_num_tx_queues, iflib_num_rx_queues; 5965 int err, admincnt, bar; 5966 5967 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 5968 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 5969 5970 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 5971 5972 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5973 admincnt = sctx->isc_admin_intrcnt; 5974 /* Override by tuneable */ 5975 if (scctx->isc_disable_msix) 5976 goto msi; 5977 5978 /* 5979 * bar == -1 => "trust me I know what I'm doing" 5980 * Some drivers are for hardware that is so shoddily 5981 * documented that no one knows which bars are which 5982 * so the developer has to map all bars. This hack 5983 * allows shoddy garbage to use msix in this framework. 5984 */ 5985 if (bar != -1) { 5986 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5987 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5988 if (ctx->ifc_msix_mem == NULL) { 5989 /* May not be enabled */ 5990 device_printf(dev, "Unable to map MSIX table \n"); 5991 goto msi; 5992 } 5993 } 5994 /* First try MSI/X */ 5995 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5996 device_printf(dev, "System has MSIX disabled \n"); 5997 bus_release_resource(dev, SYS_RES_MEMORY, 5998 bar, ctx->ifc_msix_mem); 5999 ctx->ifc_msix_mem = NULL; 6000 goto msi; 6001 } 6002 #if IFLIB_DEBUG 6003 /* use only 1 qset in debug mode */ 6004 queuemsgs = min(msgs - admincnt, 1); 6005 #else 6006 queuemsgs = msgs - admincnt; 6007 #endif 6008 #ifdef RSS 6009 queues = imin(queuemsgs, rss_getnumbuckets()); 6010 #else 6011 queues = queuemsgs; 6012 #endif 6013 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6014 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 6015 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6016 #ifdef RSS 6017 /* If we're doing RSS, clamp at the number of RSS buckets */ 6018 if (queues > rss_getnumbuckets()) 6019 queues = rss_getnumbuckets(); 6020 #endif 6021 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6022 rx_queues = iflib_num_rx_queues; 6023 else 6024 rx_queues = queues; 6025 6026 if (rx_queues > scctx->isc_nrxqsets) 6027 rx_queues = scctx->isc_nrxqsets; 6028 6029 /* 6030 * We want this to be all logical CPUs by default 6031 */ 6032 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6033 tx_queues = iflib_num_tx_queues; 6034 else 6035 tx_queues = mp_ncpus; 6036 6037 if (tx_queues > scctx->isc_ntxqsets) 6038 tx_queues = scctx->isc_ntxqsets; 6039 6040 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6041 #ifdef INVARIANTS 6042 if (tx_queues != rx_queues) 6043 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6044 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6045 #endif 6046 tx_queues = min(rx_queues, tx_queues); 6047 rx_queues = min(rx_queues, tx_queues); 6048 } 6049 6050 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 6051 6052 vectors = rx_queues + admincnt; 6053 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6054 device_printf(dev, 6055 "Using MSIX interrupts with %d vectors\n", vectors); 6056 scctx->isc_vectors = vectors; 6057 scctx->isc_nrxqsets = rx_queues; 6058 scctx->isc_ntxqsets = tx_queues; 6059 scctx->isc_intr = IFLIB_INTR_MSIX; 6060 6061 return (vectors); 6062 } else { 6063 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 6064 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6065 ctx->ifc_msix_mem); 6066 ctx->ifc_msix_mem = NULL; 6067 } 6068 msi: 6069 vectors = pci_msi_count(dev); 6070 scctx->isc_nrxqsets = 1; 6071 scctx->isc_ntxqsets = 1; 6072 scctx->isc_vectors = vectors; 6073 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6074 device_printf(dev,"Using an MSI interrupt\n"); 6075 scctx->isc_intr = IFLIB_INTR_MSI; 6076 } else { 6077 scctx->isc_vectors = 1; 6078 device_printf(dev,"Using a Legacy interrupt\n"); 6079 scctx->isc_intr = IFLIB_INTR_LEGACY; 6080 } 6081 6082 return (vectors); 6083 } 6084 6085 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6086 6087 static int 6088 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6089 { 6090 int rc; 6091 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6092 struct sbuf *sb; 6093 const char *ring_state = "UNKNOWN"; 6094 6095 /* XXX needed ? */ 6096 rc = sysctl_wire_old_buffer(req, 0); 6097 MPASS(rc == 0); 6098 if (rc != 0) 6099 return (rc); 6100 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6101 MPASS(sb != NULL); 6102 if (sb == NULL) 6103 return (ENOMEM); 6104 if (state[3] <= 3) 6105 ring_state = ring_states[state[3]]; 6106 6107 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6108 state[0], state[1], state[2], ring_state); 6109 rc = sbuf_finish(sb); 6110 sbuf_delete(sb); 6111 return(rc); 6112 } 6113 6114 enum iflib_ndesc_handler { 6115 IFLIB_NTXD_HANDLER, 6116 IFLIB_NRXD_HANDLER, 6117 }; 6118 6119 static int 6120 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6121 { 6122 if_ctx_t ctx = (void *)arg1; 6123 enum iflib_ndesc_handler type = arg2; 6124 char buf[256] = {0}; 6125 qidx_t *ndesc; 6126 char *p, *next; 6127 int nqs, rc, i; 6128 6129 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 6130 6131 nqs = 8; 6132 switch(type) { 6133 case IFLIB_NTXD_HANDLER: 6134 ndesc = ctx->ifc_sysctl_ntxds; 6135 if (ctx->ifc_sctx) 6136 nqs = ctx->ifc_sctx->isc_ntxqs; 6137 break; 6138 case IFLIB_NRXD_HANDLER: 6139 ndesc = ctx->ifc_sysctl_nrxds; 6140 if (ctx->ifc_sctx) 6141 nqs = ctx->ifc_sctx->isc_nrxqs; 6142 break; 6143 default: 6144 panic("unhandled type"); 6145 } 6146 if (nqs == 0) 6147 nqs = 8; 6148 6149 for (i=0; i<8; i++) { 6150 if (i >= nqs) 6151 break; 6152 if (i) 6153 strcat(buf, ","); 6154 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6155 } 6156 6157 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6158 if (rc || req->newptr == NULL) 6159 return rc; 6160 6161 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6162 i++, p = strsep(&next, " ,")) { 6163 ndesc[i] = strtoul(p, NULL, 10); 6164 } 6165 6166 return(rc); 6167 } 6168 6169 #define NAME_BUFLEN 32 6170 static void 6171 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6172 { 6173 device_t dev = iflib_get_dev(ctx); 6174 struct sysctl_oid_list *child, *oid_list; 6175 struct sysctl_ctx_list *ctx_list; 6176 struct sysctl_oid *node; 6177 6178 ctx_list = device_get_sysctl_ctx(dev); 6179 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6180 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6181 CTLFLAG_RD, NULL, "IFLIB fields"); 6182 oid_list = SYSCTL_CHILDREN(node); 6183 6184 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6185 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 6186 "driver version"); 6187 6188 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6189 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6190 "# of txqs to use, 0 => use default #"); 6191 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6192 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6193 "# of rxqs to use, 0 => use default #"); 6194 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6195 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6196 "permit #txq != #rxq"); 6197 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6198 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6199 "disable MSIX (default 0)"); 6200 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6201 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6202 "set the rx budget"); 6203 6204 /* XXX change for per-queue sizes */ 6205 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6206 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6207 mp_ndesc_handler, "A", 6208 "list of # of tx descriptors to use, 0 = use default #"); 6209 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6210 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6211 mp_ndesc_handler, "A", 6212 "list of # of rx descriptors to use, 0 = use default #"); 6213 } 6214 6215 static void 6216 iflib_add_device_sysctl_post(if_ctx_t ctx) 6217 { 6218 if_shared_ctx_t sctx = ctx->ifc_sctx; 6219 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6220 device_t dev = iflib_get_dev(ctx); 6221 struct sysctl_oid_list *child; 6222 struct sysctl_ctx_list *ctx_list; 6223 iflib_fl_t fl; 6224 iflib_txq_t txq; 6225 iflib_rxq_t rxq; 6226 int i, j; 6227 char namebuf[NAME_BUFLEN]; 6228 char *qfmt; 6229 struct sysctl_oid *queue_node, *fl_node, *node; 6230 struct sysctl_oid_list *queue_list, *fl_list; 6231 ctx_list = device_get_sysctl_ctx(dev); 6232 6233 node = ctx->ifc_sysctl_node; 6234 child = SYSCTL_CHILDREN(node); 6235 6236 if (scctx->isc_ntxqsets > 100) 6237 qfmt = "txq%03d"; 6238 else if (scctx->isc_ntxqsets > 10) 6239 qfmt = "txq%02d"; 6240 else 6241 qfmt = "txq%d"; 6242 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6243 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6244 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6245 CTLFLAG_RD, NULL, "Queue Name"); 6246 queue_list = SYSCTL_CHILDREN(queue_node); 6247 #if MEMORY_LOGGING 6248 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6249 CTLFLAG_RD, 6250 &txq->ift_dequeued, "total mbufs freed"); 6251 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6252 CTLFLAG_RD, 6253 &txq->ift_enqueued, "total mbufs enqueued"); 6254 #endif 6255 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6256 CTLFLAG_RD, 6257 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6258 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6259 CTLFLAG_RD, 6260 &txq->ift_pullups, "# of times m_pullup was called"); 6261 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6262 CTLFLAG_RD, 6263 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6264 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6265 CTLFLAG_RD, 6266 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6267 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6268 CTLFLAG_RD, 6269 &txq->ift_map_failed, "# of times dma map failed"); 6270 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6271 CTLFLAG_RD, 6272 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6273 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6274 CTLFLAG_RD, 6275 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6276 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6277 CTLFLAG_RD, 6278 &txq->ift_pidx, 1, "Producer Index"); 6279 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6280 CTLFLAG_RD, 6281 &txq->ift_cidx, 1, "Consumer Index"); 6282 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6283 CTLFLAG_RD, 6284 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6285 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6286 CTLFLAG_RD, 6287 &txq->ift_in_use, 1, "descriptors in use"); 6288 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6289 CTLFLAG_RD, 6290 &txq->ift_processed, "descriptors procesed for clean"); 6291 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6292 CTLFLAG_RD, 6293 &txq->ift_cleaned, "total cleaned"); 6294 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6295 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6296 0, mp_ring_state_handler, "A", "soft ring state"); 6297 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6298 CTLFLAG_RD, &txq->ift_br->enqueues, 6299 "# of enqueues to the mp_ring for this queue"); 6300 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6301 CTLFLAG_RD, &txq->ift_br->drops, 6302 "# of drops in the mp_ring for this queue"); 6303 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6304 CTLFLAG_RD, &txq->ift_br->starts, 6305 "# of normal consumer starts in the mp_ring for this queue"); 6306 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6307 CTLFLAG_RD, &txq->ift_br->stalls, 6308 "# of consumer stalls in the mp_ring for this queue"); 6309 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6310 CTLFLAG_RD, &txq->ift_br->restarts, 6311 "# of consumer restarts in the mp_ring for this queue"); 6312 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6313 CTLFLAG_RD, &txq->ift_br->abdications, 6314 "# of consumer abdications in the mp_ring for this queue"); 6315 } 6316 6317 if (scctx->isc_nrxqsets > 100) 6318 qfmt = "rxq%03d"; 6319 else if (scctx->isc_nrxqsets > 10) 6320 qfmt = "rxq%02d"; 6321 else 6322 qfmt = "rxq%d"; 6323 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6324 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6325 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6326 CTLFLAG_RD, NULL, "Queue Name"); 6327 queue_list = SYSCTL_CHILDREN(queue_node); 6328 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6329 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 6330 CTLFLAG_RD, 6331 &rxq->ifr_cq_pidx, 1, "Producer Index"); 6332 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6333 CTLFLAG_RD, 6334 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6335 } 6336 6337 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6338 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6339 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6340 CTLFLAG_RD, NULL, "freelist Name"); 6341 fl_list = SYSCTL_CHILDREN(fl_node); 6342 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6343 CTLFLAG_RD, 6344 &fl->ifl_pidx, 1, "Producer Index"); 6345 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6346 CTLFLAG_RD, 6347 &fl->ifl_cidx, 1, "Consumer Index"); 6348 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6349 CTLFLAG_RD, 6350 &fl->ifl_credits, 1, "credits available"); 6351 #if MEMORY_LOGGING 6352 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6353 CTLFLAG_RD, 6354 &fl->ifl_m_enqueued, "mbufs allocated"); 6355 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6356 CTLFLAG_RD, 6357 &fl->ifl_m_dequeued, "mbufs freed"); 6358 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6359 CTLFLAG_RD, 6360 &fl->ifl_cl_enqueued, "clusters allocated"); 6361 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6362 CTLFLAG_RD, 6363 &fl->ifl_cl_dequeued, "clusters freed"); 6364 #endif 6365 6366 } 6367 } 6368 6369 } 6370 6371 #ifndef __NO_STRICT_ALIGNMENT 6372 static struct mbuf * 6373 iflib_fixup_rx(struct mbuf *m) 6374 { 6375 struct mbuf *n; 6376 6377 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6378 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6379 m->m_data += ETHER_HDR_LEN; 6380 n = m; 6381 } else { 6382 MGETHDR(n, M_NOWAIT, MT_DATA); 6383 if (n == NULL) { 6384 m_freem(m); 6385 return (NULL); 6386 } 6387 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6388 m->m_data += ETHER_HDR_LEN; 6389 m->m_len -= ETHER_HDR_LEN; 6390 n->m_len = ETHER_HDR_LEN; 6391 M_MOVE_PKTHDR(n, m); 6392 n->m_next = m; 6393 } 6394 return (n); 6395 } 6396 #endif 6397 6398 #ifdef NETDUMP 6399 static void 6400 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 6401 { 6402 if_ctx_t ctx; 6403 6404 ctx = if_getsoftc(ifp); 6405 CTX_LOCK(ctx); 6406 *nrxr = NRXQSETS(ctx); 6407 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6408 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6409 CTX_UNLOCK(ctx); 6410 } 6411 6412 static void 6413 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event) 6414 { 6415 if_ctx_t ctx; 6416 if_softc_ctx_t scctx; 6417 iflib_fl_t fl; 6418 iflib_rxq_t rxq; 6419 int i, j; 6420 6421 ctx = if_getsoftc(ifp); 6422 scctx = &ctx->ifc_softc_ctx; 6423 6424 switch (event) { 6425 case NETDUMP_START: 6426 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6427 rxq = &ctx->ifc_rxqs[i]; 6428 for (j = 0; j < rxq->ifr_nfl; j++) { 6429 fl = rxq->ifr_fl; 6430 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6431 } 6432 } 6433 iflib_no_tx_batch = 1; 6434 break; 6435 default: 6436 break; 6437 } 6438 } 6439 6440 static int 6441 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m) 6442 { 6443 if_ctx_t ctx; 6444 iflib_txq_t txq; 6445 int error; 6446 6447 ctx = if_getsoftc(ifp); 6448 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6449 IFF_DRV_RUNNING) 6450 return (EBUSY); 6451 6452 txq = &ctx->ifc_txqs[0]; 6453 error = iflib_encap(txq, &m); 6454 if (error == 0) 6455 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6456 return (error); 6457 } 6458 6459 static int 6460 iflib_netdump_poll(struct ifnet *ifp, int count) 6461 { 6462 if_ctx_t ctx; 6463 if_softc_ctx_t scctx; 6464 iflib_txq_t txq; 6465 int i; 6466 6467 ctx = if_getsoftc(ifp); 6468 scctx = &ctx->ifc_softc_ctx; 6469 6470 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6471 IFF_DRV_RUNNING) 6472 return (EBUSY); 6473 6474 txq = &ctx->ifc_txqs[0]; 6475 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6476 6477 for (i = 0; i < scctx->isc_nrxqsets; i++) 6478 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6479 return (0); 6480 } 6481 #endif /* NETDUMP */ 6482