1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 /* 120 * File organization: 121 * - private structures 122 * - iflib private utility functions 123 * - ifnet functions 124 * - vlan registry and other exported functions 125 * - iflib public core functions 126 * 127 * 128 */ 129 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 130 131 #define IFLIB_RXEOF_MORE (1U << 0) 132 #define IFLIB_RXEOF_EMPTY (2U << 0) 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 static void iflib_tqg_detach(if_ctx_t ctx); 146 147 typedef struct iflib_filter_info { 148 driver_filter_t *ifi_filter; 149 void *ifi_filter_arg; 150 struct grouptask *ifi_task; 151 void *ifi_ctx; 152 } *iflib_filter_info_t; 153 154 struct iflib_ctx { 155 KOBJ_FIELDS; 156 /* 157 * Pointer to hardware driver's softc 158 */ 159 void *ifc_softc; 160 device_t ifc_dev; 161 if_t ifc_ifp; 162 163 cpuset_t ifc_cpus; 164 if_shared_ctx_t ifc_sctx; 165 struct if_softc_ctx ifc_softc_ctx; 166 167 struct sx ifc_ctx_sx; 168 struct mtx ifc_state_mtx; 169 170 iflib_txq_t ifc_txqs; 171 iflib_rxq_t ifc_rxqs; 172 uint32_t ifc_if_flags; 173 uint32_t ifc_flags; 174 uint32_t ifc_max_fl_buf_size; 175 uint32_t ifc_rx_mbuf_sz; 176 177 int ifc_link_state; 178 int ifc_watchdog_events; 179 struct cdev *ifc_led_dev; 180 struct resource *ifc_msix_mem; 181 182 struct if_irq ifc_legacy_irq; 183 struct grouptask ifc_admin_task; 184 struct grouptask ifc_vflr_task; 185 struct iflib_filter_info ifc_filter_info; 186 struct ifmedia ifc_media; 187 struct ifmedia *ifc_mediap; 188 189 struct sysctl_oid *ifc_sysctl_node; 190 uint16_t ifc_sysctl_ntxqs; 191 uint16_t ifc_sysctl_nrxqs; 192 uint16_t ifc_sysctl_qs_eq_override; 193 uint16_t ifc_sysctl_rx_budget; 194 uint16_t ifc_sysctl_tx_abdicate; 195 uint16_t ifc_sysctl_core_offset; 196 #define CORE_OFFSET_UNSPECIFIED 0xffff 197 uint8_t ifc_sysctl_separate_txrx; 198 uint8_t ifc_sysctl_use_logical_cores; 199 bool ifc_cpus_are_physical_cores; 200 201 qidx_t ifc_sysctl_ntxds[8]; 202 qidx_t ifc_sysctl_nrxds[8]; 203 struct if_txrx ifc_txrx; 204 #define isc_txd_encap ifc_txrx.ift_txd_encap 205 #define isc_txd_flush ifc_txrx.ift_txd_flush 206 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 207 #define isc_rxd_available ifc_txrx.ift_rxd_available 208 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 209 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 210 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 211 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 212 eventhandler_tag ifc_vlan_attach_event; 213 eventhandler_tag ifc_vlan_detach_event; 214 struct ether_addr ifc_mac; 215 }; 216 217 void * 218 iflib_get_softc(if_ctx_t ctx) 219 { 220 221 return (ctx->ifc_softc); 222 } 223 224 device_t 225 iflib_get_dev(if_ctx_t ctx) 226 { 227 228 return (ctx->ifc_dev); 229 } 230 231 if_t 232 iflib_get_ifp(if_ctx_t ctx) 233 { 234 235 return (ctx->ifc_ifp); 236 } 237 238 struct ifmedia * 239 iflib_get_media(if_ctx_t ctx) 240 { 241 242 return (ctx->ifc_mediap); 243 } 244 245 uint32_t 246 iflib_get_flags(if_ctx_t ctx) 247 { 248 return (ctx->ifc_flags); 249 } 250 251 void 252 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 253 { 254 255 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 256 } 257 258 if_softc_ctx_t 259 iflib_get_softc_ctx(if_ctx_t ctx) 260 { 261 262 return (&ctx->ifc_softc_ctx); 263 } 264 265 if_shared_ctx_t 266 iflib_get_sctx(if_ctx_t ctx) 267 { 268 269 return (ctx->ifc_sctx); 270 } 271 272 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 273 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 274 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 275 276 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 277 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 278 279 typedef struct iflib_sw_rx_desc_array { 280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 281 struct mbuf **ifsd_m; /* pkthdr mbufs */ 282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 283 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 284 } iflib_rxsd_array_t; 285 286 typedef struct iflib_sw_tx_desc_array { 287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 288 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 289 struct mbuf **ifsd_m; /* pkthdr mbufs */ 290 } if_txsd_vec_t; 291 292 /* magic number that should be high enough for any hardware */ 293 #define IFLIB_MAX_TX_SEGS 128 294 #define IFLIB_RX_COPY_THRESH 128 295 #define IFLIB_MAX_RX_REFRESH 32 296 /* The minimum descriptors per second before we start coalescing */ 297 #define IFLIB_MIN_DESC_SEC 16384 298 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 299 #define IFLIB_QUEUE_IDLE 0 300 #define IFLIB_QUEUE_HUNG 1 301 #define IFLIB_QUEUE_WORKING 2 302 /* maximum number of txqs that can share an rx interrupt */ 303 #define IFLIB_MAX_TX_SHARED_INTR 4 304 305 /* this should really scale with ring size - this is a fairly arbitrary value */ 306 #define TX_BATCH_SIZE 32 307 308 #define IFLIB_RESTART_BUDGET 8 309 310 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 311 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 312 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 313 314 struct iflib_txq { 315 qidx_t ift_in_use; 316 qidx_t ift_cidx; 317 qidx_t ift_cidx_processed; 318 qidx_t ift_pidx; 319 uint8_t ift_gen; 320 uint8_t ift_br_offset; 321 uint16_t ift_npending; 322 uint16_t ift_db_pending; 323 uint16_t ift_rs_pending; 324 /* implicit pad */ 325 uint8_t ift_txd_size[8]; 326 uint64_t ift_processed; 327 uint64_t ift_cleaned; 328 uint64_t ift_cleaned_prev; 329 #if MEMORY_LOGGING 330 uint64_t ift_enqueued; 331 uint64_t ift_dequeued; 332 #endif 333 uint64_t ift_no_tx_dma_setup; 334 uint64_t ift_no_desc_avail; 335 uint64_t ift_mbuf_defrag_failed; 336 uint64_t ift_mbuf_defrag; 337 uint64_t ift_map_failed; 338 uint64_t ift_txd_encap_efbig; 339 uint64_t ift_pullups; 340 uint64_t ift_last_timer_tick; 341 342 struct mtx ift_mtx; 343 struct mtx ift_db_mtx; 344 345 /* constant values */ 346 if_ctx_t ift_ctx; 347 struct ifmp_ring *ift_br; 348 struct grouptask ift_task; 349 qidx_t ift_size; 350 uint16_t ift_id; 351 struct callout ift_timer; 352 #ifdef DEV_NETMAP 353 struct callout ift_netmap_timer; 354 #endif /* DEV_NETMAP */ 355 356 if_txsd_vec_t ift_sds; 357 uint8_t ift_qstatus; 358 uint8_t ift_closed; 359 uint8_t ift_update_freq; 360 struct iflib_filter_info ift_filter_info; 361 bus_dma_tag_t ift_buf_tag; 362 bus_dma_tag_t ift_tso_buf_tag; 363 iflib_dma_info_t ift_ifdi; 364 #define MTX_NAME_LEN 32 365 char ift_mtx_name[MTX_NAME_LEN]; 366 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 367 #ifdef IFLIB_DIAGNOSTICS 368 uint64_t ift_cpu_exec_count[256]; 369 #endif 370 } __aligned(CACHE_LINE_SIZE); 371 372 struct iflib_fl { 373 qidx_t ifl_cidx; 374 qidx_t ifl_pidx; 375 qidx_t ifl_credits; 376 uint8_t ifl_gen; 377 uint8_t ifl_rxd_size; 378 #if MEMORY_LOGGING 379 uint64_t ifl_m_enqueued; 380 uint64_t ifl_m_dequeued; 381 uint64_t ifl_cl_enqueued; 382 uint64_t ifl_cl_dequeued; 383 #endif 384 /* implicit pad */ 385 bitstr_t *ifl_rx_bitmap; 386 qidx_t ifl_fragidx; 387 /* constant */ 388 qidx_t ifl_size; 389 uint16_t ifl_buf_size; 390 uint16_t ifl_cltype; 391 uma_zone_t ifl_zone; 392 iflib_rxsd_array_t ifl_sds; 393 iflib_rxq_t ifl_rxq; 394 uint8_t ifl_id; 395 bus_dma_tag_t ifl_buf_tag; 396 iflib_dma_info_t ifl_ifdi; 397 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 398 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 399 } __aligned(CACHE_LINE_SIZE); 400 401 static inline qidx_t 402 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 403 { 404 qidx_t used; 405 406 if (pidx > cidx) 407 used = pidx - cidx; 408 else if (pidx < cidx) 409 used = size - cidx + pidx; 410 else if (gen == 0 && pidx == cidx) 411 used = 0; 412 else if (gen == 1 && pidx == cidx) 413 used = size; 414 else 415 panic("bad state"); 416 417 return (used); 418 } 419 420 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 421 422 #define IDXDIFF(head, tail, wrap) \ 423 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 424 425 struct iflib_rxq { 426 if_ctx_t ifr_ctx; 427 iflib_fl_t ifr_fl; 428 uint64_t ifr_rx_irq; 429 struct pfil_head *pfil; 430 /* 431 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 432 * the completion queue consumer index. Otherwise it's unused. 433 */ 434 qidx_t ifr_cq_cidx; 435 uint16_t ifr_id; 436 uint8_t ifr_nfl; 437 uint8_t ifr_ntxqirq; 438 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 439 uint8_t ifr_fl_offset; 440 struct lro_ctrl ifr_lc; 441 struct grouptask ifr_task; 442 struct callout ifr_watchdog; 443 struct iflib_filter_info ifr_filter_info; 444 iflib_dma_info_t ifr_ifdi; 445 446 /* dynamically allocate if any drivers need a value substantially larger than this */ 447 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 448 #ifdef IFLIB_DIAGNOSTICS 449 uint64_t ifr_cpu_exec_count[256]; 450 #endif 451 } __aligned(CACHE_LINE_SIZE); 452 453 typedef struct if_rxsd { 454 caddr_t *ifsd_cl; 455 iflib_fl_t ifsd_fl; 456 } *if_rxsd_t; 457 458 /* multiple of word size */ 459 #ifdef __LP64__ 460 #define PKT_INFO_SIZE 6 461 #define RXD_INFO_SIZE 5 462 #define PKT_TYPE uint64_t 463 #else 464 #define PKT_INFO_SIZE 11 465 #define RXD_INFO_SIZE 8 466 #define PKT_TYPE uint32_t 467 #endif 468 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 469 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 470 471 typedef struct if_pkt_info_pad { 472 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 473 } *if_pkt_info_pad_t; 474 typedef struct if_rxd_info_pad { 475 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 476 } *if_rxd_info_pad_t; 477 478 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 479 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 480 481 static inline void 482 pkt_info_zero(if_pkt_info_t pi) 483 { 484 if_pkt_info_pad_t pi_pad; 485 486 pi_pad = (if_pkt_info_pad_t)pi; 487 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 488 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 489 #ifndef __LP64__ 490 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 491 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 492 #endif 493 } 494 495 static device_method_t iflib_pseudo_methods[] = { 496 DEVMETHOD(device_attach, noop_attach), 497 DEVMETHOD(device_detach, iflib_pseudo_detach), 498 DEVMETHOD_END 499 }; 500 501 driver_t iflib_pseudodriver = { 502 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 503 }; 504 505 static inline void 506 rxd_info_zero(if_rxd_info_t ri) 507 { 508 if_rxd_info_pad_t ri_pad; 509 int i; 510 511 ri_pad = (if_rxd_info_pad_t)ri; 512 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 513 ri_pad->rxd_val[i] = 0; 514 ri_pad->rxd_val[i+1] = 0; 515 ri_pad->rxd_val[i+2] = 0; 516 ri_pad->rxd_val[i+3] = 0; 517 } 518 #ifdef __LP64__ 519 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 520 #endif 521 } 522 523 /* 524 * Only allow a single packet to take up most 1/nth of the tx ring 525 */ 526 #define MAX_SINGLE_PACKET_FRACTION 12 527 #define IF_BAD_DMA (bus_addr_t)-1 528 529 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 530 531 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 532 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 533 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 534 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 535 536 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 537 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 538 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 539 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 540 541 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 542 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 543 544 void 545 iflib_set_detach(if_ctx_t ctx) 546 { 547 STATE_LOCK(ctx); 548 ctx->ifc_flags |= IFC_IN_DETACH; 549 STATE_UNLOCK(ctx); 550 } 551 552 /* Our boot-time initialization hook */ 553 static int iflib_module_event_handler(module_t, int, void *); 554 555 static moduledata_t iflib_moduledata = { 556 "iflib", 557 iflib_module_event_handler, 558 NULL 559 }; 560 561 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 562 MODULE_VERSION(iflib, 1); 563 564 MODULE_DEPEND(iflib, pci, 1, 1, 1); 565 MODULE_DEPEND(iflib, ether, 1, 1, 1); 566 567 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 568 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 569 570 #ifndef IFLIB_DEBUG_COUNTERS 571 #ifdef INVARIANTS 572 #define IFLIB_DEBUG_COUNTERS 1 573 #else 574 #define IFLIB_DEBUG_COUNTERS 0 575 #endif /* !INVARIANTS */ 576 #endif 577 578 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 579 "iflib driver parameters"); 580 581 /* 582 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 583 */ 584 static int iflib_min_tx_latency = 0; 585 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 586 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 587 static int iflib_no_tx_batch = 0; 588 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 589 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 590 static int iflib_timer_default = 1000; 591 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW, 592 &iflib_timer_default, 0, "number of ticks between iflib_timer calls"); 593 594 595 #if IFLIB_DEBUG_COUNTERS 596 597 static int iflib_tx_seen; 598 static int iflib_tx_sent; 599 static int iflib_tx_encap; 600 static int iflib_rx_allocs; 601 static int iflib_fl_refills; 602 static int iflib_fl_refills_large; 603 static int iflib_tx_frees; 604 605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 606 &iflib_tx_seen, 0, "# TX mbufs seen"); 607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 608 &iflib_tx_sent, 0, "# TX mbufs sent"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 610 &iflib_tx_encap, 0, "# TX mbufs encapped"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 612 &iflib_tx_frees, 0, "# TX frees"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 614 &iflib_rx_allocs, 0, "# RX allocations"); 615 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 616 &iflib_fl_refills, 0, "# refills"); 617 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 618 &iflib_fl_refills_large, 0, "# large refills"); 619 620 static int iflib_txq_drain_flushing; 621 static int iflib_txq_drain_oactive; 622 static int iflib_txq_drain_notready; 623 624 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 625 &iflib_txq_drain_flushing, 0, "# drain flushes"); 626 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 627 &iflib_txq_drain_oactive, 0, "# drain oactives"); 628 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 629 &iflib_txq_drain_notready, 0, "# drain notready"); 630 631 static int iflib_encap_load_mbuf_fail; 632 static int iflib_encap_pad_mbuf_fail; 633 static int iflib_encap_txq_avail_fail; 634 static int iflib_encap_txd_encap_fail; 635 636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 637 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 638 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 639 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 640 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 641 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 642 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 643 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 644 645 static int iflib_task_fn_rxs; 646 static int iflib_rx_intr_enables; 647 static int iflib_fast_intrs; 648 static int iflib_rx_unavail; 649 static int iflib_rx_ctx_inactive; 650 static int iflib_rx_if_input; 651 static int iflib_rxd_flush; 652 653 static int iflib_verbose_debug; 654 655 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 656 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 657 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 658 &iflib_rx_intr_enables, 0, "# RX intr enables"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 660 &iflib_fast_intrs, 0, "# fast_intr calls"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 662 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 664 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 666 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 668 &iflib_rxd_flush, 0, "# times rxd_flush called"); 669 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 670 &iflib_verbose_debug, 0, "enable verbose debugging"); 671 672 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 673 static void 674 iflib_debug_reset(void) 675 { 676 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 677 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 678 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 679 iflib_txq_drain_notready = 680 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 681 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 682 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 683 iflib_rx_unavail = 684 iflib_rx_ctx_inactive = iflib_rx_if_input = 685 iflib_rxd_flush = 0; 686 } 687 688 #else 689 #define DBG_COUNTER_INC(name) 690 static void iflib_debug_reset(void) {} 691 #endif 692 693 #define IFLIB_DEBUG 0 694 695 static void iflib_tx_structures_free(if_ctx_t ctx); 696 static void iflib_rx_structures_free(if_ctx_t ctx); 697 static int iflib_queues_alloc(if_ctx_t ctx); 698 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 699 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 700 static int iflib_qset_structures_setup(if_ctx_t ctx); 701 static int iflib_msix_init(if_ctx_t ctx); 702 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 703 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 704 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 705 #ifdef ALTQ 706 static void iflib_altq_if_start(if_t ifp); 707 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 708 #endif 709 static int iflib_register(if_ctx_t); 710 static void iflib_deregister(if_ctx_t); 711 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 712 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 713 static void iflib_init_locked(if_ctx_t ctx); 714 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 715 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 716 static void iflib_ifmp_purge(iflib_txq_t txq); 717 static void _iflib_pre_assert(if_softc_ctx_t scctx); 718 static void iflib_if_init_locked(if_ctx_t ctx); 719 static void iflib_free_intr_mem(if_ctx_t ctx); 720 #ifndef __NO_STRICT_ALIGNMENT 721 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 722 #endif 723 724 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 725 SLIST_HEAD_INITIALIZER(cpu_offsets); 726 struct cpu_offset { 727 SLIST_ENTRY(cpu_offset) entries; 728 cpuset_t set; 729 unsigned int refcount; 730 uint16_t next_cpuid; 731 }; 732 static struct mtx cpu_offset_mtx; 733 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 734 MTX_DEF); 735 736 DEBUGNET_DEFINE(iflib); 737 738 static int 739 iflib_num_rx_descs(if_ctx_t ctx) 740 { 741 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 742 if_shared_ctx_t sctx = ctx->ifc_sctx; 743 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 744 745 return scctx->isc_nrxd[first_rxq]; 746 } 747 748 static int 749 iflib_num_tx_descs(if_ctx_t ctx) 750 { 751 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 752 if_shared_ctx_t sctx = ctx->ifc_sctx; 753 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 754 755 return scctx->isc_ntxd[first_txq]; 756 } 757 758 #ifdef DEV_NETMAP 759 #include <sys/selinfo.h> 760 #include <net/netmap.h> 761 #include <dev/netmap/netmap_kern.h> 762 763 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 764 765 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 766 static void iflib_netmap_timer(void *arg); 767 768 /* 769 * device-specific sysctl variables: 770 * 771 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 772 * During regular operations the CRC is stripped, but on some 773 * hardware reception of frames not multiple of 64 is slower, 774 * so using crcstrip=0 helps in benchmarks. 775 * 776 * iflib_rx_miss, iflib_rx_miss_bufs: 777 * count packets that might be missed due to lost interrupts. 778 */ 779 SYSCTL_DECL(_dev_netmap); 780 /* 781 * The xl driver by default strips CRCs and we do not override it. 782 */ 783 784 int iflib_crcstrip = 1; 785 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 786 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 787 788 int iflib_rx_miss, iflib_rx_miss_bufs; 789 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 790 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 791 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 792 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 793 794 /* 795 * Register/unregister. We are already under netmap lock. 796 * Only called on the first register or the last unregister. 797 */ 798 static int 799 iflib_netmap_register(struct netmap_adapter *na, int onoff) 800 { 801 if_t ifp = na->ifp; 802 if_ctx_t ctx = ifp->if_softc; 803 int status; 804 805 CTX_LOCK(ctx); 806 if (!CTX_IS_VF(ctx)) 807 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 808 809 iflib_stop(ctx); 810 811 /* 812 * Enable (or disable) netmap flags, and intercept (or restore) 813 * ifp->if_transmit. This is done once the device has been stopped 814 * to prevent race conditions. Also, this must be done after 815 * calling netmap_disable_all_rings() and before calling 816 * netmap_enable_all_rings(), so that these two functions see the 817 * updated state of the NAF_NETMAP_ON bit. 818 */ 819 if (onoff) { 820 nm_set_native_flags(na); 821 } else { 822 nm_clear_native_flags(na); 823 } 824 825 iflib_init_locked(ctx); 826 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 827 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 828 if (status) 829 nm_clear_native_flags(na); 830 CTX_UNLOCK(ctx); 831 return (status); 832 } 833 834 static int 835 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info) 836 { 837 if_t ifp = na->ifp; 838 if_ctx_t ctx = ifp->if_softc; 839 iflib_rxq_t rxq = &ctx->ifc_rxqs[0]; 840 iflib_fl_t fl = &rxq->ifr_fl[0]; 841 842 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 843 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 844 info->num_tx_descs = iflib_num_tx_descs(ctx); 845 info->num_rx_descs = iflib_num_rx_descs(ctx); 846 info->rx_buf_maxsize = fl->ifl_buf_size; 847 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u", 848 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs, 849 info->num_rx_descs, info->rx_buf_maxsize); 850 851 return 0; 852 } 853 854 static int 855 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 856 { 857 struct netmap_adapter *na = kring->na; 858 u_int const lim = kring->nkr_num_slots - 1; 859 struct netmap_ring *ring = kring->ring; 860 bus_dmamap_t *map; 861 struct if_rxd_update iru; 862 if_ctx_t ctx = rxq->ifr_ctx; 863 iflib_fl_t fl = &rxq->ifr_fl[0]; 864 u_int nic_i_first, nic_i; 865 u_int nm_i; 866 int i, n; 867 #if IFLIB_DEBUG_COUNTERS 868 int rf_count = 0; 869 #endif 870 871 /* 872 * This function is used both at initialization and in rxsync. 873 * At initialization we need to prepare (with isc_rxd_refill()) 874 * all the netmap buffers currently owned by the kernel, in 875 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync 876 * (except for kring->nkr_hwofs). These may be less than 877 * kring->nkr_num_slots if netmap_reset() was called while 878 * an application using the kring that still owned some 879 * buffers. 880 * At rxsync time, both indexes point to the next buffer to be 881 * refilled. 882 * In any case we publish (with isc_rxd_flush()) up to 883 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 884 * pointer to overrun the head/cons pointer, although this is 885 * not necessary for some NICs (e.g. vmx). 886 */ 887 if (__predict_false(init)) { 888 n = kring->nkr_num_slots - nm_kr_rxspace(kring); 889 } else { 890 n = kring->rhead - kring->nr_hwcur; 891 if (n == 0) 892 return (0); /* Nothing to do. */ 893 if (n < 0) 894 n += kring->nkr_num_slots; 895 } 896 897 iru_init(&iru, rxq, 0 /* flid */); 898 map = fl->ifl_sds.ifsd_map; 899 nic_i = fl->ifl_pidx; 900 nm_i = netmap_idx_n2k(kring, nic_i); 901 if (__predict_false(init)) { 902 /* 903 * On init/reset, nic_i must be 0, and we must 904 * start to refill from hwtail (see netmap_reset()). 905 */ 906 MPASS(nic_i == 0); 907 MPASS(nm_i == kring->nr_hwtail); 908 } else 909 MPASS(nm_i == kring->nr_hwcur); 910 DBG_COUNTER_INC(fl_refills); 911 while (n > 0) { 912 #if IFLIB_DEBUG_COUNTERS 913 if (++rf_count == 9) 914 DBG_COUNTER_INC(fl_refills_large); 915 #endif 916 nic_i_first = nic_i; 917 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 918 struct netmap_slot *slot = &ring->slot[nm_i]; 919 uint64_t paddr; 920 void *addr = PNMB(na, slot, &paddr); 921 922 MPASS(i < IFLIB_MAX_RX_REFRESH); 923 924 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 925 return netmap_ring_reinit(kring); 926 927 fl->ifl_bus_addrs[i] = paddr + 928 nm_get_offset(kring, slot); 929 fl->ifl_rxd_idxs[i] = nic_i; 930 931 if (__predict_false(init)) { 932 netmap_load_map(na, fl->ifl_buf_tag, 933 map[nic_i], addr); 934 } else if (slot->flags & NS_BUF_CHANGED) { 935 /* buffer has changed, reload map */ 936 netmap_reload_map(na, fl->ifl_buf_tag, 937 map[nic_i], addr); 938 } 939 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 940 BUS_DMASYNC_PREREAD); 941 slot->flags &= ~NS_BUF_CHANGED; 942 943 nm_i = nm_next(nm_i, lim); 944 nic_i = nm_next(nic_i, lim); 945 } 946 947 iru.iru_pidx = nic_i_first; 948 iru.iru_count = i; 949 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 950 } 951 fl->ifl_pidx = nic_i; 952 /* 953 * At the end of the loop we must have refilled everything 954 * we could possibly refill. 955 */ 956 MPASS(nm_i == kring->rhead); 957 kring->nr_hwcur = nm_i; 958 959 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 960 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 961 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 962 nm_prev(nic_i, lim)); 963 DBG_COUNTER_INC(rxd_flush); 964 965 return (0); 966 } 967 968 #define NETMAP_TX_TIMER_US 90 969 970 /* 971 * Reconcile kernel and user view of the transmit ring. 972 * 973 * All information is in the kring. 974 * Userspace wants to send packets up to the one before kring->rhead, 975 * kernel knows kring->nr_hwcur is the first unsent packet. 976 * 977 * Here we push packets out (as many as possible), and possibly 978 * reclaim buffers from previously completed transmission. 979 * 980 * The caller (netmap) guarantees that there is only one instance 981 * running at any time. Any interference with other driver 982 * methods should be handled by the individual drivers. 983 */ 984 static int 985 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 986 { 987 struct netmap_adapter *na = kring->na; 988 if_t ifp = na->ifp; 989 struct netmap_ring *ring = kring->ring; 990 u_int nm_i; /* index into the netmap kring */ 991 u_int nic_i; /* index into the NIC ring */ 992 u_int n; 993 u_int const lim = kring->nkr_num_slots - 1; 994 u_int const head = kring->rhead; 995 struct if_pkt_info pi; 996 997 /* 998 * interrupts on every tx packet are expensive so request 999 * them every half ring, or where NS_REPORT is set 1000 */ 1001 u_int report_frequency = kring->nkr_num_slots >> 1; 1002 /* device-specific */ 1003 if_ctx_t ctx = ifp->if_softc; 1004 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 1005 1006 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1007 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1008 1009 /* 1010 * First part: process new packets to send. 1011 * nm_i is the current index in the netmap kring, 1012 * nic_i is the corresponding index in the NIC ring. 1013 * 1014 * If we have packets to send (nm_i != head) 1015 * iterate over the netmap ring, fetch length and update 1016 * the corresponding slot in the NIC ring. Some drivers also 1017 * need to update the buffer's physical address in the NIC slot 1018 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 1019 * 1020 * The netmap_reload_map() calls is especially expensive, 1021 * even when (as in this case) the tag is 0, so do only 1022 * when the buffer has actually changed. 1023 * 1024 * If possible do not set the report/intr bit on all slots, 1025 * but only a few times per ring or when NS_REPORT is set. 1026 * 1027 * Finally, on 10G and faster drivers, it might be useful 1028 * to prefetch the next slot and txr entry. 1029 */ 1030 1031 nm_i = kring->nr_hwcur; 1032 if (nm_i != head) { /* we have new packets to send */ 1033 uint32_t pkt_len = 0, seg_idx = 0; 1034 int nic_i_start = -1, flags = 0; 1035 pkt_info_zero(&pi); 1036 pi.ipi_segs = txq->ift_segs; 1037 pi.ipi_qsidx = kring->ring_id; 1038 nic_i = netmap_idx_k2n(kring, nm_i); 1039 1040 __builtin_prefetch(&ring->slot[nm_i]); 1041 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 1042 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 1043 1044 for (n = 0; nm_i != head; n++) { 1045 struct netmap_slot *slot = &ring->slot[nm_i]; 1046 uint64_t offset = nm_get_offset(kring, slot); 1047 u_int len = slot->len; 1048 uint64_t paddr; 1049 void *addr = PNMB(na, slot, &paddr); 1050 1051 flags |= (slot->flags & NS_REPORT || 1052 nic_i == 0 || nic_i == report_frequency) ? 1053 IPI_TX_INTR : 0; 1054 1055 /* 1056 * If this is the first packet fragment, save the 1057 * index of the first NIC slot for later. 1058 */ 1059 if (nic_i_start < 0) 1060 nic_i_start = nic_i; 1061 1062 pi.ipi_segs[seg_idx].ds_addr = paddr + offset; 1063 pi.ipi_segs[seg_idx].ds_len = len; 1064 if (len) { 1065 pkt_len += len; 1066 seg_idx++; 1067 } 1068 1069 if (!(slot->flags & NS_MOREFRAG)) { 1070 pi.ipi_len = pkt_len; 1071 pi.ipi_nsegs = seg_idx; 1072 pi.ipi_pidx = nic_i_start; 1073 pi.ipi_ndescs = 0; 1074 pi.ipi_flags = flags; 1075 1076 /* Prepare the NIC TX ring. */ 1077 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1078 DBG_COUNTER_INC(tx_encap); 1079 1080 /* Reinit per-packet info for the next one. */ 1081 flags = seg_idx = pkt_len = 0; 1082 nic_i_start = -1; 1083 } 1084 1085 /* prefetch for next round */ 1086 __builtin_prefetch(&ring->slot[nm_i + 1]); 1087 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1088 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1089 1090 NM_CHECK_ADDR_LEN_OFF(na, len, offset); 1091 1092 if (slot->flags & NS_BUF_CHANGED) { 1093 /* buffer has changed, reload map */ 1094 netmap_reload_map(na, txq->ift_buf_tag, 1095 txq->ift_sds.ifsd_map[nic_i], addr); 1096 } 1097 /* make sure changes to the buffer are synced */ 1098 bus_dmamap_sync(txq->ift_buf_tag, 1099 txq->ift_sds.ifsd_map[nic_i], 1100 BUS_DMASYNC_PREWRITE); 1101 1102 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG); 1103 nm_i = nm_next(nm_i, lim); 1104 nic_i = nm_next(nic_i, lim); 1105 } 1106 kring->nr_hwcur = nm_i; 1107 1108 /* synchronize the NIC ring */ 1109 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1110 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1111 1112 /* (re)start the tx unit up to slot nic_i (excluded) */ 1113 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1114 } 1115 1116 /* 1117 * Second part: reclaim buffers for completed transmissions. 1118 * 1119 * If there are unclaimed buffers, attempt to reclaim them. 1120 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1121 * trigger a per-tx-queue timer to try again later. 1122 */ 1123 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1124 if (iflib_tx_credits_update(ctx, txq)) { 1125 /* some tx completed, increment avail */ 1126 nic_i = txq->ift_cidx_processed; 1127 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1128 } 1129 } 1130 1131 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1132 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1133 callout_reset_sbt_on(&txq->ift_netmap_timer, 1134 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1135 iflib_netmap_timer, txq, 1136 txq->ift_netmap_timer.c_cpu, 0); 1137 } 1138 return (0); 1139 } 1140 1141 /* 1142 * Reconcile kernel and user view of the receive ring. 1143 * Same as for the txsync, this routine must be efficient. 1144 * The caller guarantees a single invocations, but races against 1145 * the rest of the driver should be handled here. 1146 * 1147 * On call, kring->rhead is the first packet that userspace wants 1148 * to keep, and kring->rcur is the wakeup point. 1149 * The kernel has previously reported packets up to kring->rtail. 1150 * 1151 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1152 * of whether or not we received an interrupt. 1153 */ 1154 static int 1155 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1156 { 1157 struct netmap_adapter *na = kring->na; 1158 struct netmap_ring *ring = kring->ring; 1159 if_t ifp = na->ifp; 1160 uint32_t nm_i; /* index into the netmap ring */ 1161 uint32_t nic_i; /* index into the NIC ring */ 1162 u_int n; 1163 u_int const lim = kring->nkr_num_slots - 1; 1164 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1165 int i = 0; 1166 1167 if_ctx_t ctx = ifp->if_softc; 1168 if_shared_ctx_t sctx = ctx->ifc_sctx; 1169 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1170 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1171 iflib_fl_t fl = &rxq->ifr_fl[0]; 1172 struct if_rxd_info ri; 1173 qidx_t *cidxp; 1174 1175 /* 1176 * netmap only uses free list 0, to avoid out of order consumption 1177 * of receive buffers 1178 */ 1179 1180 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1181 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1182 1183 /* 1184 * First part: import newly received packets. 1185 * 1186 * nm_i is the index of the next free slot in the netmap ring, 1187 * nic_i is the index of the next received packet in the NIC ring 1188 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1189 * differ in case if_init() has been called while 1190 * in netmap mode. For the receive ring we have 1191 * 1192 * nic_i = fl->ifl_cidx; 1193 * nm_i = kring->nr_hwtail (previous) 1194 * and 1195 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1196 * 1197 * fl->ifl_cidx is set to 0 on a ring reinit 1198 */ 1199 if (netmap_no_pendintr || force_update) { 1200 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1201 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1202 int crclen = iflib_crcstrip ? 0 : 4; 1203 int error, avail; 1204 1205 /* 1206 * For the free list consumer index, we use the same 1207 * logic as in iflib_rxeof(). 1208 */ 1209 if (have_rxcq) 1210 cidxp = &rxq->ifr_cq_cidx; 1211 else 1212 cidxp = &fl->ifl_cidx; 1213 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1214 rxq->ifr_id, *cidxp, USHRT_MAX); 1215 1216 nic_i = fl->ifl_cidx; 1217 nm_i = netmap_idx_n2k(kring, nic_i); 1218 MPASS(nm_i == kring->nr_hwtail); 1219 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1220 rxd_info_zero(&ri); 1221 ri.iri_frags = rxq->ifr_frags; 1222 ri.iri_qsidx = kring->ring_id; 1223 ri.iri_ifp = ctx->ifc_ifp; 1224 ri.iri_cidx = *cidxp; 1225 1226 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1227 for (i = 0; i < ri.iri_nfrags; i++) { 1228 if (error) { 1229 ring->slot[nm_i].len = 0; 1230 ring->slot[nm_i].flags = 0; 1231 } else { 1232 ring->slot[nm_i].len = ri.iri_frags[i].irf_len; 1233 if (i == (ri.iri_nfrags - 1)) { 1234 ring->slot[nm_i].len -= crclen; 1235 ring->slot[nm_i].flags = 0; 1236 } else 1237 ring->slot[nm_i].flags = NS_MOREFRAG; 1238 } 1239 1240 bus_dmamap_sync(fl->ifl_buf_tag, 1241 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1242 nm_i = nm_next(nm_i, lim); 1243 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1244 } 1245 1246 if (have_rxcq) { 1247 *cidxp = ri.iri_cidx; 1248 while (*cidxp >= scctx->isc_nrxd[0]) 1249 *cidxp -= scctx->isc_nrxd[0]; 1250 } 1251 1252 } 1253 if (n) { /* update the state variables */ 1254 if (netmap_no_pendintr && !force_update) { 1255 /* diagnostics */ 1256 iflib_rx_miss ++; 1257 iflib_rx_miss_bufs += n; 1258 } 1259 kring->nr_hwtail = nm_i; 1260 } 1261 kring->nr_kflags &= ~NKR_PENDINTR; 1262 } 1263 /* 1264 * Second part: skip past packets that userspace has released. 1265 * (kring->nr_hwcur to head excluded), 1266 * and make the buffers available for reception. 1267 * As usual nm_i is the index in the netmap ring, 1268 * nic_i is the index in the NIC ring, and 1269 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1270 */ 1271 netmap_fl_refill(rxq, kring, false); 1272 1273 return (0); 1274 } 1275 1276 static void 1277 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1278 { 1279 if_ctx_t ctx = na->ifp->if_softc; 1280 1281 CTX_LOCK(ctx); 1282 if (onoff) { 1283 IFDI_INTR_ENABLE(ctx); 1284 } else { 1285 IFDI_INTR_DISABLE(ctx); 1286 } 1287 CTX_UNLOCK(ctx); 1288 } 1289 1290 static int 1291 iflib_netmap_attach(if_ctx_t ctx) 1292 { 1293 struct netmap_adapter na; 1294 1295 bzero(&na, sizeof(na)); 1296 1297 na.ifp = ctx->ifc_ifp; 1298 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS; 1299 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1300 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1301 1302 na.num_tx_desc = iflib_num_tx_descs(ctx); 1303 na.num_rx_desc = iflib_num_rx_descs(ctx); 1304 na.nm_txsync = iflib_netmap_txsync; 1305 na.nm_rxsync = iflib_netmap_rxsync; 1306 na.nm_register = iflib_netmap_register; 1307 na.nm_intr = iflib_netmap_intr; 1308 na.nm_config = iflib_netmap_config; 1309 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1310 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1311 return (netmap_attach(&na)); 1312 } 1313 1314 static int 1315 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1316 { 1317 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1318 struct netmap_slot *slot; 1319 1320 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1321 if (slot == NULL) 1322 return (0); 1323 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1324 /* 1325 * In netmap mode, set the map for the packet buffer. 1326 * NOTE: Some drivers (not this one) also need to set 1327 * the physical buffer address in the NIC ring. 1328 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1329 * netmap slot index, si 1330 */ 1331 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1332 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1333 NMB(na, slot + si)); 1334 } 1335 return (1); 1336 } 1337 1338 static int 1339 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1340 { 1341 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1342 struct netmap_kring *kring; 1343 struct netmap_slot *slot; 1344 1345 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1346 if (slot == NULL) 1347 return (0); 1348 kring = na->rx_rings[rxq->ifr_id]; 1349 netmap_fl_refill(rxq, kring, true); 1350 return (1); 1351 } 1352 1353 static void 1354 iflib_netmap_timer(void *arg) 1355 { 1356 iflib_txq_t txq = arg; 1357 if_ctx_t ctx = txq->ift_ctx; 1358 1359 /* 1360 * Wake up the netmap application, to give it a chance to 1361 * call txsync and reclaim more completed TX buffers. 1362 */ 1363 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1364 } 1365 1366 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1367 1368 #else 1369 #define iflib_netmap_txq_init(ctx, txq) (0) 1370 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1371 #define iflib_netmap_detach(ifp) 1372 #define netmap_enable_all_rings(ifp) 1373 #define netmap_disable_all_rings(ifp) 1374 1375 #define iflib_netmap_attach(ctx) (0) 1376 #define netmap_rx_irq(ifp, qid, budget) (0) 1377 #endif 1378 1379 #if defined(__i386__) || defined(__amd64__) 1380 static __inline void 1381 prefetch(void *x) 1382 { 1383 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1384 } 1385 static __inline void 1386 prefetch2cachelines(void *x) 1387 { 1388 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1389 #if (CACHE_LINE_SIZE < 128) 1390 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1391 #endif 1392 } 1393 #else 1394 #define prefetch(x) 1395 #define prefetch2cachelines(x) 1396 #endif 1397 1398 static void 1399 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1400 { 1401 iflib_fl_t fl; 1402 1403 fl = &rxq->ifr_fl[flid]; 1404 iru->iru_paddrs = fl->ifl_bus_addrs; 1405 iru->iru_idxs = fl->ifl_rxd_idxs; 1406 iru->iru_qsidx = rxq->ifr_id; 1407 iru->iru_buf_size = fl->ifl_buf_size; 1408 iru->iru_flidx = fl->ifl_id; 1409 } 1410 1411 static void 1412 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1413 { 1414 if (err) 1415 return; 1416 *(bus_addr_t *) arg = segs[0].ds_addr; 1417 } 1418 1419 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \ 1420 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \ 1421 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL) 1422 1423 int 1424 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1425 { 1426 int err; 1427 device_t dev = ctx->ifc_dev; 1428 bus_addr_t lowaddr; 1429 1430 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width); 1431 1432 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1433 align, 0, /* alignment, bounds */ 1434 lowaddr, /* lowaddr */ 1435 BUS_SPACE_MAXADDR, /* highaddr */ 1436 NULL, NULL, /* filter, filterarg */ 1437 size, /* maxsize */ 1438 1, /* nsegments */ 1439 size, /* maxsegsize */ 1440 BUS_DMA_ALLOCNOW, /* flags */ 1441 NULL, /* lockfunc */ 1442 NULL, /* lockarg */ 1443 &dma->idi_tag); 1444 if (err) { 1445 device_printf(dev, 1446 "%s: bus_dma_tag_create failed: %d\n", 1447 __func__, err); 1448 goto fail_0; 1449 } 1450 1451 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1452 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1453 if (err) { 1454 device_printf(dev, 1455 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1456 __func__, (uintmax_t)size, err); 1457 goto fail_1; 1458 } 1459 1460 dma->idi_paddr = IF_BAD_DMA; 1461 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1462 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1463 if (err || dma->idi_paddr == IF_BAD_DMA) { 1464 device_printf(dev, 1465 "%s: bus_dmamap_load failed: %d\n", 1466 __func__, err); 1467 goto fail_2; 1468 } 1469 1470 dma->idi_size = size; 1471 return (0); 1472 1473 fail_2: 1474 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1475 fail_1: 1476 bus_dma_tag_destroy(dma->idi_tag); 1477 fail_0: 1478 dma->idi_tag = NULL; 1479 1480 return (err); 1481 } 1482 1483 int 1484 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1485 { 1486 if_shared_ctx_t sctx = ctx->ifc_sctx; 1487 1488 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1489 1490 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1491 } 1492 1493 int 1494 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1495 { 1496 int i, err; 1497 iflib_dma_info_t *dmaiter; 1498 1499 dmaiter = dmalist; 1500 for (i = 0; i < count; i++, dmaiter++) { 1501 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1502 break; 1503 } 1504 if (err) 1505 iflib_dma_free_multi(dmalist, i); 1506 return (err); 1507 } 1508 1509 void 1510 iflib_dma_free(iflib_dma_info_t dma) 1511 { 1512 if (dma->idi_tag == NULL) 1513 return; 1514 if (dma->idi_paddr != IF_BAD_DMA) { 1515 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1516 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1517 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1518 dma->idi_paddr = IF_BAD_DMA; 1519 } 1520 if (dma->idi_vaddr != NULL) { 1521 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1522 dma->idi_vaddr = NULL; 1523 } 1524 bus_dma_tag_destroy(dma->idi_tag); 1525 dma->idi_tag = NULL; 1526 } 1527 1528 void 1529 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1530 { 1531 int i; 1532 iflib_dma_info_t *dmaiter = dmalist; 1533 1534 for (i = 0; i < count; i++, dmaiter++) 1535 iflib_dma_free(*dmaiter); 1536 } 1537 1538 static int 1539 iflib_fast_intr(void *arg) 1540 { 1541 iflib_filter_info_t info = arg; 1542 struct grouptask *gtask = info->ifi_task; 1543 int result; 1544 1545 DBG_COUNTER_INC(fast_intrs); 1546 if (info->ifi_filter != NULL) { 1547 result = info->ifi_filter(info->ifi_filter_arg); 1548 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1549 return (result); 1550 } 1551 1552 GROUPTASK_ENQUEUE(gtask); 1553 return (FILTER_HANDLED); 1554 } 1555 1556 static int 1557 iflib_fast_intr_rxtx(void *arg) 1558 { 1559 iflib_filter_info_t info = arg; 1560 struct grouptask *gtask = info->ifi_task; 1561 if_ctx_t ctx; 1562 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1563 iflib_txq_t txq; 1564 void *sc; 1565 int i, cidx, result; 1566 qidx_t txqid; 1567 bool intr_enable, intr_legacy; 1568 1569 DBG_COUNTER_INC(fast_intrs); 1570 if (info->ifi_filter != NULL) { 1571 result = info->ifi_filter(info->ifi_filter_arg); 1572 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1573 return (result); 1574 } 1575 1576 ctx = rxq->ifr_ctx; 1577 sc = ctx->ifc_softc; 1578 intr_enable = false; 1579 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1580 MPASS(rxq->ifr_ntxqirq); 1581 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1582 txqid = rxq->ifr_txqid[i]; 1583 txq = &ctx->ifc_txqs[txqid]; 1584 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1585 BUS_DMASYNC_POSTREAD); 1586 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1587 if (intr_legacy) 1588 intr_enable = true; 1589 else 1590 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1591 continue; 1592 } 1593 GROUPTASK_ENQUEUE(&txq->ift_task); 1594 } 1595 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1596 cidx = rxq->ifr_cq_cidx; 1597 else 1598 cidx = rxq->ifr_fl[0].ifl_cidx; 1599 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1600 GROUPTASK_ENQUEUE(gtask); 1601 else { 1602 if (intr_legacy) 1603 intr_enable = true; 1604 else 1605 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1606 DBG_COUNTER_INC(rx_intr_enables); 1607 } 1608 if (intr_enable) 1609 IFDI_INTR_ENABLE(ctx); 1610 return (FILTER_HANDLED); 1611 } 1612 1613 static int 1614 iflib_fast_intr_ctx(void *arg) 1615 { 1616 iflib_filter_info_t info = arg; 1617 struct grouptask *gtask = info->ifi_task; 1618 int result; 1619 1620 DBG_COUNTER_INC(fast_intrs); 1621 if (info->ifi_filter != NULL) { 1622 result = info->ifi_filter(info->ifi_filter_arg); 1623 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1624 return (result); 1625 } 1626 1627 GROUPTASK_ENQUEUE(gtask); 1628 return (FILTER_HANDLED); 1629 } 1630 1631 static int 1632 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1633 driver_filter_t filter, driver_intr_t handler, void *arg, 1634 const char *name) 1635 { 1636 struct resource *res; 1637 void *tag = NULL; 1638 device_t dev = ctx->ifc_dev; 1639 int flags, i, rc; 1640 1641 flags = RF_ACTIVE; 1642 if (ctx->ifc_flags & IFC_LEGACY) 1643 flags |= RF_SHAREABLE; 1644 MPASS(rid < 512); 1645 i = rid; 1646 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1647 if (res == NULL) { 1648 device_printf(dev, 1649 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1650 return (ENOMEM); 1651 } 1652 irq->ii_res = res; 1653 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1654 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1655 filter, handler, arg, &tag); 1656 if (rc != 0) { 1657 device_printf(dev, 1658 "failed to setup interrupt for rid %d, name %s: %d\n", 1659 rid, name ? name : "unknown", rc); 1660 return (rc); 1661 } else if (name) 1662 bus_describe_intr(dev, res, tag, "%s", name); 1663 1664 irq->ii_tag = tag; 1665 return (0); 1666 } 1667 1668 /********************************************************************* 1669 * 1670 * Allocate DMA resources for TX buffers as well as memory for the TX 1671 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1672 * iflib_sw_tx_desc_array structure, storing all the information that 1673 * is needed to transmit a packet on the wire. This is called only 1674 * once at attach, setup is done every reset. 1675 * 1676 **********************************************************************/ 1677 static int 1678 iflib_txsd_alloc(iflib_txq_t txq) 1679 { 1680 if_ctx_t ctx = txq->ift_ctx; 1681 if_shared_ctx_t sctx = ctx->ifc_sctx; 1682 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1683 device_t dev = ctx->ifc_dev; 1684 bus_size_t tsomaxsize; 1685 bus_addr_t lowaddr; 1686 int err, nsegments, ntsosegments; 1687 bool tso; 1688 1689 nsegments = scctx->isc_tx_nsegments; 1690 ntsosegments = scctx->isc_tx_tso_segments_max; 1691 tsomaxsize = scctx->isc_tx_tso_size_max; 1692 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1693 tsomaxsize += sizeof(struct ether_vlan_header); 1694 MPASS(scctx->isc_ntxd[0] > 0); 1695 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1696 MPASS(nsegments > 0); 1697 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1698 MPASS(ntsosegments > 0); 1699 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1700 } 1701 1702 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1703 1704 /* 1705 * Set up DMA tags for TX buffers. 1706 */ 1707 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1708 1, 0, /* alignment, bounds */ 1709 lowaddr, /* lowaddr */ 1710 BUS_SPACE_MAXADDR, /* highaddr */ 1711 NULL, NULL, /* filter, filterarg */ 1712 sctx->isc_tx_maxsize, /* maxsize */ 1713 nsegments, /* nsegments */ 1714 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1715 0, /* flags */ 1716 NULL, /* lockfunc */ 1717 NULL, /* lockfuncarg */ 1718 &txq->ift_buf_tag))) { 1719 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1720 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1721 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1722 goto fail; 1723 } 1724 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1725 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1726 1, 0, /* alignment, bounds */ 1727 lowaddr, /* lowaddr */ 1728 BUS_SPACE_MAXADDR, /* highaddr */ 1729 NULL, NULL, /* filter, filterarg */ 1730 tsomaxsize, /* maxsize */ 1731 ntsosegments, /* nsegments */ 1732 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1733 0, /* flags */ 1734 NULL, /* lockfunc */ 1735 NULL, /* lockfuncarg */ 1736 &txq->ift_tso_buf_tag))) { 1737 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1738 err); 1739 goto fail; 1740 } 1741 1742 /* Allocate memory for the TX mbuf map. */ 1743 if (!(txq->ift_sds.ifsd_m = 1744 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1745 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1746 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1747 err = ENOMEM; 1748 goto fail; 1749 } 1750 1751 /* 1752 * Create the DMA maps for TX buffers. 1753 */ 1754 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1755 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1756 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1757 device_printf(dev, 1758 "Unable to allocate TX buffer DMA map memory\n"); 1759 err = ENOMEM; 1760 goto fail; 1761 } 1762 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1763 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1764 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1765 device_printf(dev, 1766 "Unable to allocate TSO TX buffer map memory\n"); 1767 err = ENOMEM; 1768 goto fail; 1769 } 1770 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1771 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1772 &txq->ift_sds.ifsd_map[i]); 1773 if (err != 0) { 1774 device_printf(dev, "Unable to create TX DMA map\n"); 1775 goto fail; 1776 } 1777 if (!tso) 1778 continue; 1779 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1780 &txq->ift_sds.ifsd_tso_map[i]); 1781 if (err != 0) { 1782 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1783 goto fail; 1784 } 1785 } 1786 return (0); 1787 fail: 1788 /* We free all, it handles case where we are in the middle */ 1789 iflib_tx_structures_free(ctx); 1790 return (err); 1791 } 1792 1793 static void 1794 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1795 { 1796 bus_dmamap_t map; 1797 1798 if (txq->ift_sds.ifsd_map != NULL) { 1799 map = txq->ift_sds.ifsd_map[i]; 1800 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1801 bus_dmamap_unload(txq->ift_buf_tag, map); 1802 bus_dmamap_destroy(txq->ift_buf_tag, map); 1803 txq->ift_sds.ifsd_map[i] = NULL; 1804 } 1805 1806 if (txq->ift_sds.ifsd_tso_map != NULL) { 1807 map = txq->ift_sds.ifsd_tso_map[i]; 1808 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1809 BUS_DMASYNC_POSTWRITE); 1810 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1811 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1812 txq->ift_sds.ifsd_tso_map[i] = NULL; 1813 } 1814 } 1815 1816 static void 1817 iflib_txq_destroy(iflib_txq_t txq) 1818 { 1819 if_ctx_t ctx = txq->ift_ctx; 1820 1821 for (int i = 0; i < txq->ift_size; i++) 1822 iflib_txsd_destroy(ctx, txq, i); 1823 1824 if (txq->ift_br != NULL) { 1825 ifmp_ring_free(txq->ift_br); 1826 txq->ift_br = NULL; 1827 } 1828 1829 mtx_destroy(&txq->ift_mtx); 1830 1831 if (txq->ift_sds.ifsd_map != NULL) { 1832 free(txq->ift_sds.ifsd_map, M_IFLIB); 1833 txq->ift_sds.ifsd_map = NULL; 1834 } 1835 if (txq->ift_sds.ifsd_tso_map != NULL) { 1836 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1837 txq->ift_sds.ifsd_tso_map = NULL; 1838 } 1839 if (txq->ift_sds.ifsd_m != NULL) { 1840 free(txq->ift_sds.ifsd_m, M_IFLIB); 1841 txq->ift_sds.ifsd_m = NULL; 1842 } 1843 if (txq->ift_buf_tag != NULL) { 1844 bus_dma_tag_destroy(txq->ift_buf_tag); 1845 txq->ift_buf_tag = NULL; 1846 } 1847 if (txq->ift_tso_buf_tag != NULL) { 1848 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1849 txq->ift_tso_buf_tag = NULL; 1850 } 1851 if (txq->ift_ifdi != NULL) { 1852 free(txq->ift_ifdi, M_IFLIB); 1853 } 1854 } 1855 1856 static void 1857 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1858 { 1859 struct mbuf **mp; 1860 1861 mp = &txq->ift_sds.ifsd_m[i]; 1862 if (*mp == NULL) 1863 return; 1864 1865 if (txq->ift_sds.ifsd_map != NULL) { 1866 bus_dmamap_sync(txq->ift_buf_tag, 1867 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1868 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1869 } 1870 if (txq->ift_sds.ifsd_tso_map != NULL) { 1871 bus_dmamap_sync(txq->ift_tso_buf_tag, 1872 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1873 bus_dmamap_unload(txq->ift_tso_buf_tag, 1874 txq->ift_sds.ifsd_tso_map[i]); 1875 } 1876 m_freem(*mp); 1877 DBG_COUNTER_INC(tx_frees); 1878 *mp = NULL; 1879 } 1880 1881 static int 1882 iflib_txq_setup(iflib_txq_t txq) 1883 { 1884 if_ctx_t ctx = txq->ift_ctx; 1885 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1886 if_shared_ctx_t sctx = ctx->ifc_sctx; 1887 iflib_dma_info_t di; 1888 int i; 1889 1890 /* Set number of descriptors available */ 1891 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1892 /* XXX make configurable */ 1893 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1894 1895 /* Reset indices */ 1896 txq->ift_cidx_processed = 0; 1897 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1898 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1899 1900 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1901 bzero((void *)di->idi_vaddr, di->idi_size); 1902 1903 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1904 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1905 bus_dmamap_sync(di->idi_tag, di->idi_map, 1906 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1907 return (0); 1908 } 1909 1910 /********************************************************************* 1911 * 1912 * Allocate DMA resources for RX buffers as well as memory for the RX 1913 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1914 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1915 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1916 * Since we use use one entry in iflib_sw_rx_desc_array per received 1917 * packet, the maximum number of entries we'll need is equal to the 1918 * number of hardware receive descriptors that we've allocated. 1919 * 1920 **********************************************************************/ 1921 static int 1922 iflib_rxsd_alloc(iflib_rxq_t rxq) 1923 { 1924 if_ctx_t ctx = rxq->ifr_ctx; 1925 if_shared_ctx_t sctx = ctx->ifc_sctx; 1926 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1927 device_t dev = ctx->ifc_dev; 1928 iflib_fl_t fl; 1929 bus_addr_t lowaddr; 1930 int err; 1931 1932 MPASS(scctx->isc_nrxd[0] > 0); 1933 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1934 1935 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1936 1937 fl = rxq->ifr_fl; 1938 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1939 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1940 /* Set up DMA tag for RX buffers. */ 1941 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1942 1, 0, /* alignment, bounds */ 1943 lowaddr, /* lowaddr */ 1944 BUS_SPACE_MAXADDR, /* highaddr */ 1945 NULL, NULL, /* filter, filterarg */ 1946 sctx->isc_rx_maxsize, /* maxsize */ 1947 sctx->isc_rx_nsegments, /* nsegments */ 1948 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1949 0, /* flags */ 1950 NULL, /* lockfunc */ 1951 NULL, /* lockarg */ 1952 &fl->ifl_buf_tag); 1953 if (err) { 1954 device_printf(dev, 1955 "Unable to allocate RX DMA tag: %d\n", err); 1956 goto fail; 1957 } 1958 1959 /* Allocate memory for the RX mbuf map. */ 1960 if (!(fl->ifl_sds.ifsd_m = 1961 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1962 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1963 device_printf(dev, 1964 "Unable to allocate RX mbuf map memory\n"); 1965 err = ENOMEM; 1966 goto fail; 1967 } 1968 1969 /* Allocate memory for the direct RX cluster pointer map. */ 1970 if (!(fl->ifl_sds.ifsd_cl = 1971 (caddr_t *) malloc(sizeof(caddr_t) * 1972 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1973 device_printf(dev, 1974 "Unable to allocate RX cluster map memory\n"); 1975 err = ENOMEM; 1976 goto fail; 1977 } 1978 1979 /* Allocate memory for the RX cluster bus address map. */ 1980 if (!(fl->ifl_sds.ifsd_ba = 1981 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1982 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1983 device_printf(dev, 1984 "Unable to allocate RX bus address map memory\n"); 1985 err = ENOMEM; 1986 goto fail; 1987 } 1988 1989 /* 1990 * Create the DMA maps for RX buffers. 1991 */ 1992 if (!(fl->ifl_sds.ifsd_map = 1993 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1994 device_printf(dev, 1995 "Unable to allocate RX buffer DMA map memory\n"); 1996 err = ENOMEM; 1997 goto fail; 1998 } 1999 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 2000 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 2001 &fl->ifl_sds.ifsd_map[i]); 2002 if (err != 0) { 2003 device_printf(dev, "Unable to create RX buffer DMA map\n"); 2004 goto fail; 2005 } 2006 } 2007 } 2008 return (0); 2009 2010 fail: 2011 iflib_rx_structures_free(ctx); 2012 return (err); 2013 } 2014 2015 /* 2016 * Internal service routines 2017 */ 2018 2019 struct rxq_refill_cb_arg { 2020 int error; 2021 bus_dma_segment_t seg; 2022 int nseg; 2023 }; 2024 2025 static void 2026 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2027 { 2028 struct rxq_refill_cb_arg *cb_arg = arg; 2029 2030 cb_arg->error = error; 2031 cb_arg->seg = segs[0]; 2032 cb_arg->nseg = nseg; 2033 } 2034 2035 /** 2036 * iflib_fl_refill - refill an rxq free-buffer list 2037 * @ctx: the iflib context 2038 * @fl: the free list to refill 2039 * @count: the number of new buffers to allocate 2040 * 2041 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 2042 * The caller must assure that @count does not exceed the queue's capacity 2043 * minus one (since we always leave a descriptor unavailable). 2044 */ 2045 static uint8_t 2046 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 2047 { 2048 struct if_rxd_update iru; 2049 struct rxq_refill_cb_arg cb_arg; 2050 struct mbuf *m; 2051 caddr_t cl, *sd_cl; 2052 struct mbuf **sd_m; 2053 bus_dmamap_t *sd_map; 2054 bus_addr_t bus_addr, *sd_ba; 2055 int err, frag_idx, i, idx, n, pidx; 2056 qidx_t credits; 2057 2058 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 2059 2060 sd_m = fl->ifl_sds.ifsd_m; 2061 sd_map = fl->ifl_sds.ifsd_map; 2062 sd_cl = fl->ifl_sds.ifsd_cl; 2063 sd_ba = fl->ifl_sds.ifsd_ba; 2064 pidx = fl->ifl_pidx; 2065 idx = pidx; 2066 frag_idx = fl->ifl_fragidx; 2067 credits = fl->ifl_credits; 2068 2069 i = 0; 2070 n = count; 2071 MPASS(n > 0); 2072 MPASS(credits + n <= fl->ifl_size); 2073 2074 if (pidx < fl->ifl_cidx) 2075 MPASS(pidx + n <= fl->ifl_cidx); 2076 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 2077 MPASS(fl->ifl_gen == 0); 2078 if (pidx > fl->ifl_cidx) 2079 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 2080 2081 DBG_COUNTER_INC(fl_refills); 2082 if (n > 8) 2083 DBG_COUNTER_INC(fl_refills_large); 2084 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 2085 while (n-- > 0) { 2086 /* 2087 * We allocate an uninitialized mbuf + cluster, mbuf is 2088 * initialized after rx. 2089 * 2090 * If the cluster is still set then we know a minimum sized 2091 * packet was received 2092 */ 2093 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2094 &frag_idx); 2095 if (frag_idx < 0) 2096 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2097 MPASS(frag_idx >= 0); 2098 if ((cl = sd_cl[frag_idx]) == NULL) { 2099 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2100 if (__predict_false(cl == NULL)) 2101 break; 2102 2103 cb_arg.error = 0; 2104 MPASS(sd_map != NULL); 2105 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2106 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2107 BUS_DMA_NOWAIT); 2108 if (__predict_false(err != 0 || cb_arg.error)) { 2109 uma_zfree(fl->ifl_zone, cl); 2110 break; 2111 } 2112 2113 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2114 sd_cl[frag_idx] = cl; 2115 #if MEMORY_LOGGING 2116 fl->ifl_cl_enqueued++; 2117 #endif 2118 } else { 2119 bus_addr = sd_ba[frag_idx]; 2120 } 2121 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2122 BUS_DMASYNC_PREREAD); 2123 2124 if (sd_m[frag_idx] == NULL) { 2125 m = m_gethdr(M_NOWAIT, MT_NOINIT); 2126 if (__predict_false(m == NULL)) 2127 break; 2128 sd_m[frag_idx] = m; 2129 } 2130 bit_set(fl->ifl_rx_bitmap, frag_idx); 2131 #if MEMORY_LOGGING 2132 fl->ifl_m_enqueued++; 2133 #endif 2134 2135 DBG_COUNTER_INC(rx_allocs); 2136 fl->ifl_rxd_idxs[i] = frag_idx; 2137 fl->ifl_bus_addrs[i] = bus_addr; 2138 credits++; 2139 i++; 2140 MPASS(credits <= fl->ifl_size); 2141 if (++idx == fl->ifl_size) { 2142 #ifdef INVARIANTS 2143 fl->ifl_gen = 1; 2144 #endif 2145 idx = 0; 2146 } 2147 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2148 iru.iru_pidx = pidx; 2149 iru.iru_count = i; 2150 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2151 fl->ifl_pidx = idx; 2152 fl->ifl_credits = credits; 2153 pidx = idx; 2154 i = 0; 2155 } 2156 } 2157 2158 if (n < count - 1) { 2159 if (i != 0) { 2160 iru.iru_pidx = pidx; 2161 iru.iru_count = i; 2162 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2163 fl->ifl_pidx = idx; 2164 fl->ifl_credits = credits; 2165 } 2166 DBG_COUNTER_INC(rxd_flush); 2167 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2168 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2169 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2170 fl->ifl_id, fl->ifl_pidx); 2171 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2172 fl->ifl_fragidx = frag_idx + 1; 2173 if (fl->ifl_fragidx == fl->ifl_size) 2174 fl->ifl_fragidx = 0; 2175 } else { 2176 fl->ifl_fragidx = frag_idx; 2177 } 2178 } 2179 2180 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2181 } 2182 2183 static inline uint8_t 2184 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2185 { 2186 /* 2187 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2188 * This is important as it confuses most NICs. For instance, 2189 * Intel NICs have (per receive ring) RDH and RDT registers, where 2190 * RDH points to the next receive descriptor to be used by the NIC, 2191 * and RDT for the next receive descriptor to be published by the 2192 * driver to the NIC (RDT - 1 is thus the last valid one). 2193 * The condition RDH == RDT means no descriptors are available to 2194 * the NIC, and thus it would be ambiguous if it also meant that 2195 * all the descriptors are available to the NIC. 2196 */ 2197 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2198 #ifdef INVARIANTS 2199 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2200 #endif 2201 2202 MPASS(fl->ifl_credits <= fl->ifl_size); 2203 MPASS(reclaimable == delta); 2204 2205 if (reclaimable > 0) 2206 return (iflib_fl_refill(ctx, fl, reclaimable)); 2207 return (0); 2208 } 2209 2210 uint8_t 2211 iflib_in_detach(if_ctx_t ctx) 2212 { 2213 bool in_detach; 2214 2215 STATE_LOCK(ctx); 2216 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2217 STATE_UNLOCK(ctx); 2218 return (in_detach); 2219 } 2220 2221 static void 2222 iflib_fl_bufs_free(iflib_fl_t fl) 2223 { 2224 iflib_dma_info_t idi = fl->ifl_ifdi; 2225 bus_dmamap_t sd_map; 2226 uint32_t i; 2227 2228 for (i = 0; i < fl->ifl_size; i++) { 2229 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2230 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2231 2232 if (*sd_cl != NULL) { 2233 sd_map = fl->ifl_sds.ifsd_map[i]; 2234 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2235 BUS_DMASYNC_POSTREAD); 2236 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2237 uma_zfree(fl->ifl_zone, *sd_cl); 2238 *sd_cl = NULL; 2239 if (*sd_m != NULL) { 2240 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2241 uma_zfree(zone_mbuf, *sd_m); 2242 *sd_m = NULL; 2243 } 2244 } else { 2245 MPASS(*sd_m == NULL); 2246 } 2247 #if MEMORY_LOGGING 2248 fl->ifl_m_dequeued++; 2249 fl->ifl_cl_dequeued++; 2250 #endif 2251 } 2252 #ifdef INVARIANTS 2253 for (i = 0; i < fl->ifl_size; i++) { 2254 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2255 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2256 } 2257 #endif 2258 /* 2259 * Reset free list values 2260 */ 2261 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2262 bzero(idi->idi_vaddr, idi->idi_size); 2263 } 2264 2265 /********************************************************************* 2266 * 2267 * Initialize a free list and its buffers. 2268 * 2269 **********************************************************************/ 2270 static int 2271 iflib_fl_setup(iflib_fl_t fl) 2272 { 2273 iflib_rxq_t rxq = fl->ifl_rxq; 2274 if_ctx_t ctx = rxq->ifr_ctx; 2275 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2276 int qidx; 2277 2278 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2279 /* 2280 ** Free current RX buffer structs and their mbufs 2281 */ 2282 iflib_fl_bufs_free(fl); 2283 /* Now replenish the mbufs */ 2284 MPASS(fl->ifl_credits == 0); 2285 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2286 if (scctx->isc_rxd_buf_size[qidx] != 0) 2287 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2288 else 2289 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2290 /* 2291 * ifl_buf_size may be a driver-supplied value, so pull it up 2292 * to the selected mbuf size. 2293 */ 2294 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2295 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2296 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2297 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2298 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2299 2300 /* 2301 * Avoid pre-allocating zillions of clusters to an idle card 2302 * potentially speeding up attach. In any case make sure 2303 * to leave a descriptor unavailable. See the comment in 2304 * iflib_fl_refill_all(). 2305 */ 2306 MPASS(fl->ifl_size > 0); 2307 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2308 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2309 return (ENOBUFS); 2310 /* 2311 * handle failure 2312 */ 2313 MPASS(rxq != NULL); 2314 MPASS(fl->ifl_ifdi != NULL); 2315 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2316 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2317 return (0); 2318 } 2319 2320 /********************************************************************* 2321 * 2322 * Free receive ring data structures 2323 * 2324 **********************************************************************/ 2325 static void 2326 iflib_rx_sds_free(iflib_rxq_t rxq) 2327 { 2328 iflib_fl_t fl; 2329 int i, j; 2330 2331 if (rxq->ifr_fl != NULL) { 2332 for (i = 0; i < rxq->ifr_nfl; i++) { 2333 fl = &rxq->ifr_fl[i]; 2334 if (fl->ifl_buf_tag != NULL) { 2335 if (fl->ifl_sds.ifsd_map != NULL) { 2336 for (j = 0; j < fl->ifl_size; j++) { 2337 bus_dmamap_sync( 2338 fl->ifl_buf_tag, 2339 fl->ifl_sds.ifsd_map[j], 2340 BUS_DMASYNC_POSTREAD); 2341 bus_dmamap_unload( 2342 fl->ifl_buf_tag, 2343 fl->ifl_sds.ifsd_map[j]); 2344 bus_dmamap_destroy( 2345 fl->ifl_buf_tag, 2346 fl->ifl_sds.ifsd_map[j]); 2347 } 2348 } 2349 bus_dma_tag_destroy(fl->ifl_buf_tag); 2350 fl->ifl_buf_tag = NULL; 2351 } 2352 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2353 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2354 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2355 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2356 free(fl->ifl_rx_bitmap, M_IFLIB); 2357 fl->ifl_sds.ifsd_m = NULL; 2358 fl->ifl_sds.ifsd_cl = NULL; 2359 fl->ifl_sds.ifsd_ba = NULL; 2360 fl->ifl_sds.ifsd_map = NULL; 2361 fl->ifl_rx_bitmap = NULL; 2362 } 2363 free(rxq->ifr_fl, M_IFLIB); 2364 rxq->ifr_fl = NULL; 2365 free(rxq->ifr_ifdi, M_IFLIB); 2366 rxq->ifr_ifdi = NULL; 2367 rxq->ifr_cq_cidx = 0; 2368 } 2369 } 2370 2371 /* 2372 * Timer routine 2373 */ 2374 static void 2375 iflib_timer(void *arg) 2376 { 2377 iflib_txq_t txq = arg; 2378 if_ctx_t ctx = txq->ift_ctx; 2379 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2380 uint64_t this_tick = ticks; 2381 2382 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2383 return; 2384 2385 /* 2386 ** Check on the state of the TX queue(s), this 2387 ** can be done without the lock because its RO 2388 ** and the HUNG state will be static if set. 2389 */ 2390 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) { 2391 txq->ift_last_timer_tick = this_tick; 2392 IFDI_TIMER(ctx, txq->ift_id); 2393 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2394 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2395 (sctx->isc_pause_frames == 0))) 2396 goto hung; 2397 2398 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2399 ifmp_ring_is_stalled(txq->ift_br)) { 2400 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, 2401 ("queue can't be marked as hung if interface is down")); 2402 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2403 } 2404 txq->ift_cleaned_prev = txq->ift_cleaned; 2405 } 2406 /* handle any laggards */ 2407 if (txq->ift_db_pending) 2408 GROUPTASK_ENQUEUE(&txq->ift_task); 2409 2410 sctx->isc_pause_frames = 0; 2411 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2412 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, 2413 txq, txq->ift_timer.c_cpu); 2414 return; 2415 2416 hung: 2417 device_printf(ctx->ifc_dev, 2418 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2419 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2420 STATE_LOCK(ctx); 2421 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2422 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2423 iflib_admin_intr_deferred(ctx); 2424 STATE_UNLOCK(ctx); 2425 } 2426 2427 static uint16_t 2428 iflib_get_mbuf_size_for(unsigned int size) 2429 { 2430 2431 if (size <= MCLBYTES) 2432 return (MCLBYTES); 2433 else 2434 return (MJUMPAGESIZE); 2435 } 2436 2437 static void 2438 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2439 { 2440 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2441 2442 /* 2443 * XXX don't set the max_frame_size to larger 2444 * than the hardware can handle 2445 */ 2446 ctx->ifc_rx_mbuf_sz = 2447 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2448 } 2449 2450 uint32_t 2451 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2452 { 2453 2454 return (ctx->ifc_rx_mbuf_sz); 2455 } 2456 2457 static void 2458 iflib_init_locked(if_ctx_t ctx) 2459 { 2460 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2461 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2462 if_t ifp = ctx->ifc_ifp; 2463 iflib_fl_t fl; 2464 iflib_txq_t txq; 2465 iflib_rxq_t rxq; 2466 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2467 2468 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2469 IFDI_INTR_DISABLE(ctx); 2470 2471 /* 2472 * See iflib_stop(). Useful in case iflib_init_locked() is 2473 * called without first calling iflib_stop(). 2474 */ 2475 netmap_disable_all_rings(ifp); 2476 2477 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2478 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2479 /* Set hardware offload abilities */ 2480 if_clearhwassist(ifp); 2481 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2482 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2483 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2484 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2485 if (if_getcapenable(ifp) & IFCAP_TSO4) 2486 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2487 if (if_getcapenable(ifp) & IFCAP_TSO6) 2488 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2489 2490 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2491 CALLOUT_LOCK(txq); 2492 callout_stop(&txq->ift_timer); 2493 #ifdef DEV_NETMAP 2494 callout_stop(&txq->ift_netmap_timer); 2495 #endif /* DEV_NETMAP */ 2496 CALLOUT_UNLOCK(txq); 2497 (void)iflib_netmap_txq_init(ctx, txq); 2498 } 2499 2500 /* 2501 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2502 * that drivers can use the value when setting up the hardware receive 2503 * buffers. 2504 */ 2505 iflib_calc_rx_mbuf_sz(ctx); 2506 2507 #ifdef INVARIANTS 2508 i = if_getdrvflags(ifp); 2509 #endif 2510 IFDI_INIT(ctx); 2511 MPASS(if_getdrvflags(ifp) == i); 2512 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2513 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2514 /* This rxq is in netmap mode. Skip normal init. */ 2515 continue; 2516 } 2517 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2518 if (iflib_fl_setup(fl)) { 2519 device_printf(ctx->ifc_dev, 2520 "setting up free list %d failed - " 2521 "check cluster settings\n", j); 2522 goto done; 2523 } 2524 } 2525 } 2526 done: 2527 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2528 IFDI_INTR_ENABLE(ctx); 2529 txq = ctx->ifc_txqs; 2530 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2531 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 2532 txq->ift_timer.c_cpu); 2533 2534 /* Re-enable txsync/rxsync. */ 2535 netmap_enable_all_rings(ifp); 2536 } 2537 2538 static int 2539 iflib_media_change(if_t ifp) 2540 { 2541 if_ctx_t ctx = if_getsoftc(ifp); 2542 int err; 2543 2544 CTX_LOCK(ctx); 2545 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2546 iflib_if_init_locked(ctx); 2547 CTX_UNLOCK(ctx); 2548 return (err); 2549 } 2550 2551 static void 2552 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2553 { 2554 if_ctx_t ctx = if_getsoftc(ifp); 2555 2556 CTX_LOCK(ctx); 2557 IFDI_UPDATE_ADMIN_STATUS(ctx); 2558 IFDI_MEDIA_STATUS(ctx, ifmr); 2559 CTX_UNLOCK(ctx); 2560 } 2561 2562 void 2563 iflib_stop(if_ctx_t ctx) 2564 { 2565 iflib_txq_t txq = ctx->ifc_txqs; 2566 iflib_rxq_t rxq = ctx->ifc_rxqs; 2567 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2568 if_shared_ctx_t sctx = ctx->ifc_sctx; 2569 iflib_dma_info_t di; 2570 iflib_fl_t fl; 2571 int i, j; 2572 2573 /* Tell the stack that the interface is no longer active */ 2574 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2575 2576 IFDI_INTR_DISABLE(ctx); 2577 DELAY(1000); 2578 IFDI_STOP(ctx); 2579 DELAY(1000); 2580 2581 /* 2582 * Stop any pending txsync/rxsync and prevent new ones 2583 * form starting. Processes blocked in poll() will get 2584 * POLLERR. 2585 */ 2586 netmap_disable_all_rings(ctx->ifc_ifp); 2587 2588 iflib_debug_reset(); 2589 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2590 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2591 /* make sure all transmitters have completed before proceeding XXX */ 2592 2593 CALLOUT_LOCK(txq); 2594 callout_stop(&txq->ift_timer); 2595 #ifdef DEV_NETMAP 2596 callout_stop(&txq->ift_netmap_timer); 2597 #endif /* DEV_NETMAP */ 2598 CALLOUT_UNLOCK(txq); 2599 2600 /* clean any enqueued buffers */ 2601 iflib_ifmp_purge(txq); 2602 /* Free any existing tx buffers. */ 2603 for (j = 0; j < txq->ift_size; j++) { 2604 iflib_txsd_free(ctx, txq, j); 2605 } 2606 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2607 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2608 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2609 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2610 txq->ift_pullups = 0; 2611 ifmp_ring_reset_stats(txq->ift_br); 2612 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2613 bzero((void *)di->idi_vaddr, di->idi_size); 2614 } 2615 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2616 /* make sure all transmitters have completed before proceeding XXX */ 2617 2618 rxq->ifr_cq_cidx = 0; 2619 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2620 bzero((void *)di->idi_vaddr, di->idi_size); 2621 /* also resets the free lists pidx/cidx */ 2622 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2623 iflib_fl_bufs_free(fl); 2624 } 2625 } 2626 2627 static inline caddr_t 2628 calc_next_rxd(iflib_fl_t fl, int cidx) 2629 { 2630 qidx_t size; 2631 int nrxd; 2632 caddr_t start, end, cur, next; 2633 2634 nrxd = fl->ifl_size; 2635 size = fl->ifl_rxd_size; 2636 start = fl->ifl_ifdi->idi_vaddr; 2637 2638 if (__predict_false(size == 0)) 2639 return (start); 2640 cur = start + size*cidx; 2641 end = start + size*nrxd; 2642 next = CACHE_PTR_NEXT(cur); 2643 return (next < end ? next : start); 2644 } 2645 2646 static inline void 2647 prefetch_pkts(iflib_fl_t fl, int cidx) 2648 { 2649 int nextptr; 2650 int nrxd = fl->ifl_size; 2651 caddr_t next_rxd; 2652 2653 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2654 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2655 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2656 next_rxd = calc_next_rxd(fl, cidx); 2657 prefetch(next_rxd); 2658 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2659 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2660 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2661 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2662 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2663 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2664 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2665 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2666 } 2667 2668 static struct mbuf * 2669 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2670 int *pf_rv, if_rxd_info_t ri) 2671 { 2672 bus_dmamap_t map; 2673 iflib_fl_t fl; 2674 caddr_t payload; 2675 struct mbuf *m; 2676 int flid, cidx, len, next; 2677 2678 map = NULL; 2679 flid = irf->irf_flid; 2680 cidx = irf->irf_idx; 2681 fl = &rxq->ifr_fl[flid]; 2682 sd->ifsd_fl = fl; 2683 m = fl->ifl_sds.ifsd_m[cidx]; 2684 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2685 fl->ifl_credits--; 2686 #if MEMORY_LOGGING 2687 fl->ifl_m_dequeued++; 2688 #endif 2689 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2690 prefetch_pkts(fl, cidx); 2691 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2692 prefetch(&fl->ifl_sds.ifsd_map[next]); 2693 map = fl->ifl_sds.ifsd_map[cidx]; 2694 2695 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2696 2697 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2698 irf->irf_len != 0) { 2699 payload = *sd->ifsd_cl; 2700 payload += ri->iri_pad; 2701 len = ri->iri_len - ri->iri_pad; 2702 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2703 len | PFIL_MEMPTR | PFIL_IN, NULL); 2704 switch (*pf_rv) { 2705 case PFIL_DROPPED: 2706 case PFIL_CONSUMED: 2707 /* 2708 * The filter ate it. Everything is recycled. 2709 */ 2710 m = NULL; 2711 unload = 0; 2712 break; 2713 case PFIL_REALLOCED: 2714 /* 2715 * The filter copied it. Everything is recycled. 2716 */ 2717 m = pfil_mem2mbuf(payload); 2718 unload = 0; 2719 break; 2720 case PFIL_PASS: 2721 /* 2722 * Filter said it was OK, so receive like 2723 * normal 2724 */ 2725 fl->ifl_sds.ifsd_m[cidx] = NULL; 2726 break; 2727 default: 2728 MPASS(0); 2729 } 2730 } else { 2731 fl->ifl_sds.ifsd_m[cidx] = NULL; 2732 if (pf_rv != NULL) 2733 *pf_rv = PFIL_PASS; 2734 } 2735 2736 if (unload && irf->irf_len != 0) 2737 bus_dmamap_unload(fl->ifl_buf_tag, map); 2738 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2739 if (__predict_false(fl->ifl_cidx == 0)) 2740 fl->ifl_gen = 0; 2741 bit_clear(fl->ifl_rx_bitmap, cidx); 2742 return (m); 2743 } 2744 2745 static struct mbuf * 2746 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2747 { 2748 struct mbuf *m, *mh, *mt; 2749 caddr_t cl; 2750 int *pf_rv_ptr, flags, i, padlen; 2751 bool consumed; 2752 2753 i = 0; 2754 mh = NULL; 2755 consumed = false; 2756 *pf_rv = PFIL_PASS; 2757 pf_rv_ptr = pf_rv; 2758 do { 2759 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2760 pf_rv_ptr, ri); 2761 2762 MPASS(*sd->ifsd_cl != NULL); 2763 2764 /* 2765 * Exclude zero-length frags & frags from 2766 * packets the filter has consumed or dropped 2767 */ 2768 if (ri->iri_frags[i].irf_len == 0 || consumed || 2769 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2770 if (mh == NULL) { 2771 /* everything saved here */ 2772 consumed = true; 2773 pf_rv_ptr = NULL; 2774 continue; 2775 } 2776 /* XXX we can save the cluster here, but not the mbuf */ 2777 m_init(m, M_NOWAIT, MT_DATA, 0); 2778 m_free(m); 2779 continue; 2780 } 2781 if (mh == NULL) { 2782 flags = M_PKTHDR|M_EXT; 2783 mh = mt = m; 2784 padlen = ri->iri_pad; 2785 } else { 2786 flags = M_EXT; 2787 mt->m_next = m; 2788 mt = m; 2789 /* assuming padding is only on the first fragment */ 2790 padlen = 0; 2791 } 2792 cl = *sd->ifsd_cl; 2793 *sd->ifsd_cl = NULL; 2794 2795 /* Can these two be made one ? */ 2796 m_init(m, M_NOWAIT, MT_DATA, flags); 2797 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2798 /* 2799 * These must follow m_init and m_cljset 2800 */ 2801 m->m_data += padlen; 2802 ri->iri_len -= padlen; 2803 m->m_len = ri->iri_frags[i].irf_len; 2804 } while (++i < ri->iri_nfrags); 2805 2806 return (mh); 2807 } 2808 2809 /* 2810 * Process one software descriptor 2811 */ 2812 static struct mbuf * 2813 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2814 { 2815 struct if_rxsd sd; 2816 struct mbuf *m; 2817 int pf_rv; 2818 2819 /* should I merge this back in now that the two paths are basically duplicated? */ 2820 if (ri->iri_nfrags == 1 && 2821 ri->iri_frags[0].irf_len != 0 && 2822 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2823 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2824 &pf_rv, ri); 2825 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2826 return (m); 2827 if (pf_rv == PFIL_PASS) { 2828 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2829 #ifndef __NO_STRICT_ALIGNMENT 2830 if (!IP_ALIGNED(m) && ri->iri_pad == 0) 2831 m->m_data += 2; 2832 #endif 2833 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2834 m->m_len = ri->iri_frags[0].irf_len; 2835 m->m_data += ri->iri_pad; 2836 ri->iri_len -= ri->iri_pad; 2837 } 2838 } else { 2839 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2840 if (m == NULL) 2841 return (NULL); 2842 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2843 return (m); 2844 } 2845 m->m_pkthdr.len = ri->iri_len; 2846 m->m_pkthdr.rcvif = ri->iri_ifp; 2847 m->m_flags |= ri->iri_flags; 2848 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2849 m->m_pkthdr.flowid = ri->iri_flowid; 2850 M_HASHTYPE_SET(m, ri->iri_rsstype); 2851 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2852 m->m_pkthdr.csum_data = ri->iri_csum_data; 2853 return (m); 2854 } 2855 2856 #if defined(INET6) || defined(INET) 2857 static void 2858 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2859 { 2860 CURVNET_SET(lc->ifp->if_vnet); 2861 #if defined(INET6) 2862 *v6 = V_ip6_forwarding; 2863 #endif 2864 #if defined(INET) 2865 *v4 = V_ipforwarding; 2866 #endif 2867 CURVNET_RESTORE(); 2868 } 2869 2870 /* 2871 * Returns true if it's possible this packet could be LROed. 2872 * if it returns false, it is guaranteed that tcp_lro_rx() 2873 * would not return zero. 2874 */ 2875 static bool 2876 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2877 { 2878 struct ether_header *eh; 2879 2880 eh = mtod(m, struct ether_header *); 2881 switch (eh->ether_type) { 2882 #if defined(INET6) 2883 case htons(ETHERTYPE_IPV6): 2884 return (!v6_forwarding); 2885 #endif 2886 #if defined (INET) 2887 case htons(ETHERTYPE_IP): 2888 return (!v4_forwarding); 2889 #endif 2890 } 2891 2892 return false; 2893 } 2894 #else 2895 static void 2896 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2897 { 2898 } 2899 #endif 2900 2901 static void 2902 _task_fn_rx_watchdog(void *context) 2903 { 2904 iflib_rxq_t rxq = context; 2905 2906 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2907 } 2908 2909 static uint8_t 2910 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2911 { 2912 if_t ifp; 2913 if_ctx_t ctx = rxq->ifr_ctx; 2914 if_shared_ctx_t sctx = ctx->ifc_sctx; 2915 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2916 int avail, i; 2917 qidx_t *cidxp; 2918 struct if_rxd_info ri; 2919 int err, budget_left, rx_bytes, rx_pkts; 2920 iflib_fl_t fl; 2921 int lro_enabled; 2922 bool v4_forwarding, v6_forwarding, lro_possible; 2923 uint8_t retval = 0; 2924 2925 /* 2926 * XXX early demux data packets so that if_input processing only handles 2927 * acks in interrupt context 2928 */ 2929 struct mbuf *m, *mh, *mt, *mf; 2930 2931 NET_EPOCH_ASSERT(); 2932 2933 lro_possible = v4_forwarding = v6_forwarding = false; 2934 ifp = ctx->ifc_ifp; 2935 mh = mt = NULL; 2936 MPASS(budget > 0); 2937 rx_pkts = rx_bytes = 0; 2938 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2939 cidxp = &rxq->ifr_cq_cidx; 2940 else 2941 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2942 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2943 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2944 retval |= iflib_fl_refill_all(ctx, fl); 2945 DBG_COUNTER_INC(rx_unavail); 2946 return (retval); 2947 } 2948 2949 /* pfil needs the vnet to be set */ 2950 CURVNET_SET_QUIET(ifp->if_vnet); 2951 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2952 if (__predict_false(!CTX_ACTIVE(ctx))) { 2953 DBG_COUNTER_INC(rx_ctx_inactive); 2954 break; 2955 } 2956 /* 2957 * Reset client set fields to their default values 2958 */ 2959 rxd_info_zero(&ri); 2960 ri.iri_qsidx = rxq->ifr_id; 2961 ri.iri_cidx = *cidxp; 2962 ri.iri_ifp = ifp; 2963 ri.iri_frags = rxq->ifr_frags; 2964 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2965 2966 if (err) 2967 goto err; 2968 rx_pkts += 1; 2969 rx_bytes += ri.iri_len; 2970 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2971 *cidxp = ri.iri_cidx; 2972 /* Update our consumer index */ 2973 /* XXX NB: shurd - check if this is still safe */ 2974 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2975 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2976 /* was this only a completion queue message? */ 2977 if (__predict_false(ri.iri_nfrags == 0)) 2978 continue; 2979 } 2980 MPASS(ri.iri_nfrags != 0); 2981 MPASS(ri.iri_len != 0); 2982 2983 /* will advance the cidx on the corresponding free lists */ 2984 m = iflib_rxd_pkt_get(rxq, &ri); 2985 avail--; 2986 budget_left--; 2987 if (avail == 0 && budget_left) 2988 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2989 2990 if (__predict_false(m == NULL)) 2991 continue; 2992 2993 /* imm_pkt: -- cxgb */ 2994 if (mh == NULL) 2995 mh = mt = m; 2996 else { 2997 mt->m_nextpkt = m; 2998 mt = m; 2999 } 3000 } 3001 CURVNET_RESTORE(); 3002 /* make sure that we can refill faster than drain */ 3003 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3004 retval |= iflib_fl_refill_all(ctx, fl); 3005 3006 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 3007 if (lro_enabled) 3008 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 3009 mt = mf = NULL; 3010 while (mh != NULL) { 3011 m = mh; 3012 mh = mh->m_nextpkt; 3013 m->m_nextpkt = NULL; 3014 #ifndef __NO_STRICT_ALIGNMENT 3015 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 3016 continue; 3017 #endif 3018 #if defined(INET6) || defined(INET) 3019 if (lro_enabled) { 3020 if (!lro_possible) { 3021 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 3022 if (lro_possible && mf != NULL) { 3023 ifp->if_input(ifp, mf); 3024 DBG_COUNTER_INC(rx_if_input); 3025 mt = mf = NULL; 3026 } 3027 } 3028 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 3029 (CSUM_L4_CALC|CSUM_L4_VALID)) { 3030 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 3031 continue; 3032 } 3033 } 3034 #endif 3035 if (lro_possible) { 3036 ifp->if_input(ifp, m); 3037 DBG_COUNTER_INC(rx_if_input); 3038 continue; 3039 } 3040 3041 if (mf == NULL) 3042 mf = m; 3043 if (mt != NULL) 3044 mt->m_nextpkt = m; 3045 mt = m; 3046 } 3047 if (mf != NULL) { 3048 ifp->if_input(ifp, mf); 3049 DBG_COUNTER_INC(rx_if_input); 3050 } 3051 3052 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 3053 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 3054 3055 /* 3056 * Flush any outstanding LRO work 3057 */ 3058 #if defined(INET6) || defined(INET) 3059 tcp_lro_flush_all(&rxq->ifr_lc); 3060 #endif 3061 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 3062 retval |= IFLIB_RXEOF_MORE; 3063 return (retval); 3064 err: 3065 STATE_LOCK(ctx); 3066 ctx->ifc_flags |= IFC_DO_RESET; 3067 iflib_admin_intr_deferred(ctx); 3068 STATE_UNLOCK(ctx); 3069 return (0); 3070 } 3071 3072 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 3073 static inline qidx_t 3074 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 3075 { 3076 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3077 qidx_t minthresh = txq->ift_size / 8; 3078 if (in_use > 4*minthresh) 3079 return (notify_count); 3080 if (in_use > 2*minthresh) 3081 return (notify_count >> 1); 3082 if (in_use > minthresh) 3083 return (notify_count >> 3); 3084 return (0); 3085 } 3086 3087 static inline qidx_t 3088 txq_max_rs_deferred(iflib_txq_t txq) 3089 { 3090 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3091 qidx_t minthresh = txq->ift_size / 8; 3092 if (txq->ift_in_use > 4*minthresh) 3093 return (notify_count); 3094 if (txq->ift_in_use > 2*minthresh) 3095 return (notify_count >> 1); 3096 if (txq->ift_in_use > minthresh) 3097 return (notify_count >> 2); 3098 return (2); 3099 } 3100 3101 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 3102 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 3103 3104 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 3105 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 3106 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 3107 3108 /* forward compatibility for cxgb */ 3109 #define FIRST_QSET(ctx) 0 3110 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3111 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3112 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3113 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3114 3115 /* XXX we should be setting this to something other than zero */ 3116 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 3117 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3118 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3119 3120 static inline bool 3121 iflib_txd_db_check(iflib_txq_t txq, int ring) 3122 { 3123 if_ctx_t ctx = txq->ift_ctx; 3124 qidx_t dbval, max; 3125 3126 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use); 3127 3128 /* force || threshold exceeded || at the edge of the ring */ 3129 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2)) { 3130 3131 /* 3132 * 'npending' is used if the card's doorbell is in terms of the number of descriptors 3133 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the 3134 * producer index explicitly (INTC). 3135 */ 3136 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3137 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3138 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3139 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3140 3141 /* 3142 * Absent bugs there are zero packets pending so reset pending counts to zero. 3143 */ 3144 txq->ift_db_pending = txq->ift_npending = 0; 3145 return (true); 3146 } 3147 return (false); 3148 } 3149 3150 #ifdef PKT_DEBUG 3151 static void 3152 print_pkt(if_pkt_info_t pi) 3153 { 3154 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3155 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3156 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3157 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3158 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3159 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3160 } 3161 #endif 3162 3163 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3164 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3165 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3166 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3167 3168 static int 3169 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3170 { 3171 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3172 struct ether_vlan_header *eh; 3173 struct mbuf *m; 3174 3175 m = *mp; 3176 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3177 M_WRITABLE(m) == 0) { 3178 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3179 return (ENOMEM); 3180 } else { 3181 m_freem(*mp); 3182 DBG_COUNTER_INC(tx_frees); 3183 *mp = m; 3184 } 3185 } 3186 3187 /* 3188 * Determine where frame payload starts. 3189 * Jump over vlan headers if already present, 3190 * helpful for QinQ too. 3191 */ 3192 if (__predict_false(m->m_len < sizeof(*eh))) { 3193 txq->ift_pullups++; 3194 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3195 return (ENOMEM); 3196 } 3197 eh = mtod(m, struct ether_vlan_header *); 3198 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3199 pi->ipi_etype = ntohs(eh->evl_proto); 3200 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3201 } else { 3202 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3203 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3204 } 3205 3206 switch (pi->ipi_etype) { 3207 #ifdef INET 3208 case ETHERTYPE_IP: 3209 { 3210 struct mbuf *n; 3211 struct ip *ip = NULL; 3212 struct tcphdr *th = NULL; 3213 int minthlen; 3214 3215 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3216 if (__predict_false(m->m_len < minthlen)) { 3217 /* 3218 * if this code bloat is causing too much of a hit 3219 * move it to a separate function and mark it noinline 3220 */ 3221 if (m->m_len == pi->ipi_ehdrlen) { 3222 n = m->m_next; 3223 MPASS(n); 3224 if (n->m_len >= sizeof(*ip)) { 3225 ip = (struct ip *)n->m_data; 3226 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3227 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3228 } else { 3229 txq->ift_pullups++; 3230 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3231 return (ENOMEM); 3232 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3233 } 3234 } else { 3235 txq->ift_pullups++; 3236 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3237 return (ENOMEM); 3238 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3239 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3240 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3241 } 3242 } else { 3243 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3244 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3245 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3246 } 3247 pi->ipi_ip_hlen = ip->ip_hl << 2; 3248 pi->ipi_ipproto = ip->ip_p; 3249 pi->ipi_flags |= IPI_TX_IPV4; 3250 3251 /* TCP checksum offload may require TCP header length */ 3252 if (IS_TX_OFFLOAD4(pi)) { 3253 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3254 if (__predict_false(th == NULL)) { 3255 txq->ift_pullups++; 3256 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3257 return (ENOMEM); 3258 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3259 } 3260 pi->ipi_tcp_hflags = th->th_flags; 3261 pi->ipi_tcp_hlen = th->th_off << 2; 3262 pi->ipi_tcp_seq = th->th_seq; 3263 } 3264 if (IS_TSO4(pi)) { 3265 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3266 return (ENXIO); 3267 /* 3268 * TSO always requires hardware checksum offload. 3269 */ 3270 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3271 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3272 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3273 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3274 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3275 ip->ip_sum = 0; 3276 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3277 } 3278 } 3279 } 3280 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3281 ip->ip_sum = 0; 3282 3283 break; 3284 } 3285 #endif 3286 #ifdef INET6 3287 case ETHERTYPE_IPV6: 3288 { 3289 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3290 struct tcphdr *th; 3291 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3292 3293 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3294 txq->ift_pullups++; 3295 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3296 return (ENOMEM); 3297 } 3298 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3299 3300 /* XXX-BZ this will go badly in case of ext hdrs. */ 3301 pi->ipi_ipproto = ip6->ip6_nxt; 3302 pi->ipi_flags |= IPI_TX_IPV6; 3303 3304 /* TCP checksum offload may require TCP header length */ 3305 if (IS_TX_OFFLOAD6(pi)) { 3306 if (pi->ipi_ipproto == IPPROTO_TCP) { 3307 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3308 txq->ift_pullups++; 3309 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3310 return (ENOMEM); 3311 } 3312 pi->ipi_tcp_hflags = th->th_flags; 3313 pi->ipi_tcp_hlen = th->th_off << 2; 3314 pi->ipi_tcp_seq = th->th_seq; 3315 } 3316 if (IS_TSO6(pi)) { 3317 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3318 return (ENXIO); 3319 /* 3320 * TSO always requires hardware checksum offload. 3321 */ 3322 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3323 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3324 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3325 } 3326 } 3327 break; 3328 } 3329 #endif 3330 default: 3331 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3332 pi->ipi_ip_hlen = 0; 3333 break; 3334 } 3335 *mp = m; 3336 3337 return (0); 3338 } 3339 3340 /* 3341 * If dodgy hardware rejects the scatter gather chain we've handed it 3342 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3343 * m_defrag'd mbufs 3344 */ 3345 static __noinline struct mbuf * 3346 iflib_remove_mbuf(iflib_txq_t txq) 3347 { 3348 int ntxd, pidx; 3349 struct mbuf *m, **ifsd_m; 3350 3351 ifsd_m = txq->ift_sds.ifsd_m; 3352 ntxd = txq->ift_size; 3353 pidx = txq->ift_pidx & (ntxd - 1); 3354 ifsd_m = txq->ift_sds.ifsd_m; 3355 m = ifsd_m[pidx]; 3356 ifsd_m[pidx] = NULL; 3357 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3358 if (txq->ift_sds.ifsd_tso_map != NULL) 3359 bus_dmamap_unload(txq->ift_tso_buf_tag, 3360 txq->ift_sds.ifsd_tso_map[pidx]); 3361 #if MEMORY_LOGGING 3362 txq->ift_dequeued++; 3363 #endif 3364 return (m); 3365 } 3366 3367 static inline caddr_t 3368 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3369 { 3370 qidx_t size; 3371 int ntxd; 3372 caddr_t start, end, cur, next; 3373 3374 ntxd = txq->ift_size; 3375 size = txq->ift_txd_size[qid]; 3376 start = txq->ift_ifdi[qid].idi_vaddr; 3377 3378 if (__predict_false(size == 0)) 3379 return (start); 3380 cur = start + size*cidx; 3381 end = start + size*ntxd; 3382 next = CACHE_PTR_NEXT(cur); 3383 return (next < end ? next : start); 3384 } 3385 3386 /* 3387 * Pad an mbuf to ensure a minimum ethernet frame size. 3388 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3389 */ 3390 static __noinline int 3391 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3392 { 3393 /* 3394 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3395 * and ARP message is the smallest common payload I can think of 3396 */ 3397 static char pad[18]; /* just zeros */ 3398 int n; 3399 struct mbuf *new_head; 3400 3401 if (!M_WRITABLE(*m_head)) { 3402 new_head = m_dup(*m_head, M_NOWAIT); 3403 if (new_head == NULL) { 3404 m_freem(*m_head); 3405 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3406 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3407 DBG_COUNTER_INC(tx_frees); 3408 return ENOMEM; 3409 } 3410 m_freem(*m_head); 3411 *m_head = new_head; 3412 } 3413 3414 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3415 n > 0; n -= sizeof(pad)) 3416 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3417 break; 3418 3419 if (n > 0) { 3420 m_freem(*m_head); 3421 device_printf(dev, "cannot pad short frame\n"); 3422 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3423 DBG_COUNTER_INC(tx_frees); 3424 return (ENOBUFS); 3425 } 3426 3427 return 0; 3428 } 3429 3430 static int 3431 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3432 { 3433 if_ctx_t ctx; 3434 if_shared_ctx_t sctx; 3435 if_softc_ctx_t scctx; 3436 bus_dma_tag_t buf_tag; 3437 bus_dma_segment_t *segs; 3438 struct mbuf *m_head, **ifsd_m; 3439 void *next_txd; 3440 bus_dmamap_t map; 3441 struct if_pkt_info pi; 3442 int remap = 0; 3443 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3444 3445 ctx = txq->ift_ctx; 3446 sctx = ctx->ifc_sctx; 3447 scctx = &ctx->ifc_softc_ctx; 3448 segs = txq->ift_segs; 3449 ntxd = txq->ift_size; 3450 m_head = *m_headp; 3451 map = NULL; 3452 3453 /* 3454 * If we're doing TSO the next descriptor to clean may be quite far ahead 3455 */ 3456 cidx = txq->ift_cidx; 3457 pidx = txq->ift_pidx; 3458 if (ctx->ifc_flags & IFC_PREFETCH) { 3459 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3460 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3461 next_txd = calc_next_txd(txq, cidx, 0); 3462 prefetch(next_txd); 3463 } 3464 3465 /* prefetch the next cache line of mbuf pointers and flags */ 3466 prefetch(&txq->ift_sds.ifsd_m[next]); 3467 prefetch(&txq->ift_sds.ifsd_map[next]); 3468 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3469 } 3470 map = txq->ift_sds.ifsd_map[pidx]; 3471 ifsd_m = txq->ift_sds.ifsd_m; 3472 3473 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3474 buf_tag = txq->ift_tso_buf_tag; 3475 max_segs = scctx->isc_tx_tso_segments_max; 3476 map = txq->ift_sds.ifsd_tso_map[pidx]; 3477 MPASS(buf_tag != NULL); 3478 MPASS(max_segs > 0); 3479 } else { 3480 buf_tag = txq->ift_buf_tag; 3481 max_segs = scctx->isc_tx_nsegments; 3482 map = txq->ift_sds.ifsd_map[pidx]; 3483 } 3484 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3485 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3486 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3487 if (err) { 3488 DBG_COUNTER_INC(encap_txd_encap_fail); 3489 return err; 3490 } 3491 } 3492 m_head = *m_headp; 3493 3494 pkt_info_zero(&pi); 3495 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3496 pi.ipi_pidx = pidx; 3497 pi.ipi_qsidx = txq->ift_id; 3498 pi.ipi_len = m_head->m_pkthdr.len; 3499 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3500 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3501 3502 /* deliberate bitwise OR to make one condition */ 3503 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3504 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3505 DBG_COUNTER_INC(encap_txd_encap_fail); 3506 return (err); 3507 } 3508 m_head = *m_headp; 3509 } 3510 3511 retry: 3512 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3513 BUS_DMA_NOWAIT); 3514 defrag: 3515 if (__predict_false(err)) { 3516 switch (err) { 3517 case EFBIG: 3518 /* try collapse once and defrag once */ 3519 if (remap == 0) { 3520 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3521 /* try defrag if collapsing fails */ 3522 if (m_head == NULL) 3523 remap++; 3524 } 3525 if (remap == 1) { 3526 txq->ift_mbuf_defrag++; 3527 m_head = m_defrag(*m_headp, M_NOWAIT); 3528 } 3529 /* 3530 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3531 * failed to map an mbuf that was run through m_defrag 3532 */ 3533 MPASS(remap <= 1); 3534 if (__predict_false(m_head == NULL || remap > 1)) 3535 goto defrag_failed; 3536 remap++; 3537 *m_headp = m_head; 3538 goto retry; 3539 break; 3540 case ENOMEM: 3541 txq->ift_no_tx_dma_setup++; 3542 break; 3543 default: 3544 txq->ift_no_tx_dma_setup++; 3545 m_freem(*m_headp); 3546 DBG_COUNTER_INC(tx_frees); 3547 *m_headp = NULL; 3548 break; 3549 } 3550 txq->ift_map_failed++; 3551 DBG_COUNTER_INC(encap_load_mbuf_fail); 3552 DBG_COUNTER_INC(encap_txd_encap_fail); 3553 return (err); 3554 } 3555 ifsd_m[pidx] = m_head; 3556 /* 3557 * XXX assumes a 1 to 1 relationship between segments and 3558 * descriptors - this does not hold true on all drivers, e.g. 3559 * cxgb 3560 */ 3561 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3562 txq->ift_no_desc_avail++; 3563 bus_dmamap_unload(buf_tag, map); 3564 DBG_COUNTER_INC(encap_txq_avail_fail); 3565 DBG_COUNTER_INC(encap_txd_encap_fail); 3566 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3567 GROUPTASK_ENQUEUE(&txq->ift_task); 3568 return (ENOBUFS); 3569 } 3570 /* 3571 * On Intel cards we can greatly reduce the number of TX interrupts 3572 * we see by only setting report status on every Nth descriptor. 3573 * However, this also means that the driver will need to keep track 3574 * of the descriptors that RS was set on to check them for the DD bit. 3575 */ 3576 txq->ift_rs_pending += nsegs + 1; 3577 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3578 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3579 pi.ipi_flags |= IPI_TX_INTR; 3580 txq->ift_rs_pending = 0; 3581 } 3582 3583 pi.ipi_segs = segs; 3584 pi.ipi_nsegs = nsegs; 3585 3586 MPASS(pidx >= 0 && pidx < txq->ift_size); 3587 #ifdef PKT_DEBUG 3588 print_pkt(&pi); 3589 #endif 3590 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3591 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3592 DBG_COUNTER_INC(tx_encap); 3593 MPASS(pi.ipi_new_pidx < txq->ift_size); 3594 3595 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3596 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3597 ndesc += txq->ift_size; 3598 txq->ift_gen = 1; 3599 } 3600 /* 3601 * drivers can need as many as 3602 * two sentinels 3603 */ 3604 MPASS(ndesc <= pi.ipi_nsegs + 2); 3605 MPASS(pi.ipi_new_pidx != pidx); 3606 MPASS(ndesc > 0); 3607 txq->ift_in_use += ndesc; 3608 txq->ift_db_pending += ndesc; 3609 3610 /* 3611 * We update the last software descriptor again here because there may 3612 * be a sentinel and/or there may be more mbufs than segments 3613 */ 3614 txq->ift_pidx = pi.ipi_new_pidx; 3615 txq->ift_npending += pi.ipi_ndescs; 3616 } else { 3617 *m_headp = m_head = iflib_remove_mbuf(txq); 3618 if (err == EFBIG) { 3619 txq->ift_txd_encap_efbig++; 3620 if (remap < 2) { 3621 remap = 1; 3622 goto defrag; 3623 } 3624 } 3625 goto defrag_failed; 3626 } 3627 /* 3628 * err can't possibly be non-zero here, so we don't neet to test it 3629 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3630 */ 3631 return (err); 3632 3633 defrag_failed: 3634 txq->ift_mbuf_defrag_failed++; 3635 txq->ift_map_failed++; 3636 m_freem(*m_headp); 3637 DBG_COUNTER_INC(tx_frees); 3638 *m_headp = NULL; 3639 DBG_COUNTER_INC(encap_txd_encap_fail); 3640 return (ENOMEM); 3641 } 3642 3643 static void 3644 iflib_tx_desc_free(iflib_txq_t txq, int n) 3645 { 3646 uint32_t qsize, cidx, mask, gen; 3647 struct mbuf *m, **ifsd_m; 3648 bool do_prefetch; 3649 3650 cidx = txq->ift_cidx; 3651 gen = txq->ift_gen; 3652 qsize = txq->ift_size; 3653 mask = qsize-1; 3654 ifsd_m = txq->ift_sds.ifsd_m; 3655 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3656 3657 while (n-- > 0) { 3658 if (do_prefetch) { 3659 prefetch(ifsd_m[(cidx + 3) & mask]); 3660 prefetch(ifsd_m[(cidx + 4) & mask]); 3661 } 3662 if ((m = ifsd_m[cidx]) != NULL) { 3663 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3664 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3665 bus_dmamap_sync(txq->ift_tso_buf_tag, 3666 txq->ift_sds.ifsd_tso_map[cidx], 3667 BUS_DMASYNC_POSTWRITE); 3668 bus_dmamap_unload(txq->ift_tso_buf_tag, 3669 txq->ift_sds.ifsd_tso_map[cidx]); 3670 } else { 3671 bus_dmamap_sync(txq->ift_buf_tag, 3672 txq->ift_sds.ifsd_map[cidx], 3673 BUS_DMASYNC_POSTWRITE); 3674 bus_dmamap_unload(txq->ift_buf_tag, 3675 txq->ift_sds.ifsd_map[cidx]); 3676 } 3677 /* XXX we don't support any drivers that batch packets yet */ 3678 MPASS(m->m_nextpkt == NULL); 3679 m_freem(m); 3680 ifsd_m[cidx] = NULL; 3681 #if MEMORY_LOGGING 3682 txq->ift_dequeued++; 3683 #endif 3684 DBG_COUNTER_INC(tx_frees); 3685 } 3686 if (__predict_false(++cidx == qsize)) { 3687 cidx = 0; 3688 gen = 0; 3689 } 3690 } 3691 txq->ift_cidx = cidx; 3692 txq->ift_gen = gen; 3693 } 3694 3695 static __inline int 3696 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3697 { 3698 int reclaim; 3699 if_ctx_t ctx = txq->ift_ctx; 3700 3701 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3702 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3703 3704 /* 3705 * Need a rate-limiting check so that this isn't called every time 3706 */ 3707 iflib_tx_credits_update(ctx, txq); 3708 reclaim = DESC_RECLAIMABLE(txq); 3709 3710 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3711 #ifdef INVARIANTS 3712 if (iflib_verbose_debug) { 3713 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3714 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3715 reclaim, thresh); 3716 } 3717 #endif 3718 return (0); 3719 } 3720 iflib_tx_desc_free(txq, reclaim); 3721 txq->ift_cleaned += reclaim; 3722 txq->ift_in_use -= reclaim; 3723 3724 return (reclaim); 3725 } 3726 3727 static struct mbuf ** 3728 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3729 { 3730 int next, size; 3731 struct mbuf **items; 3732 3733 size = r->size; 3734 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3735 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3736 3737 prefetch(items[(cidx + offset) & (size-1)]); 3738 if (remaining > 1) { 3739 prefetch2cachelines(&items[next]); 3740 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3741 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3742 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3743 } 3744 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3745 } 3746 3747 static void 3748 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3749 { 3750 3751 ifmp_ring_check_drainage(txq->ift_br, budget); 3752 } 3753 3754 static uint32_t 3755 iflib_txq_can_drain(struct ifmp_ring *r) 3756 { 3757 iflib_txq_t txq = r->cookie; 3758 if_ctx_t ctx = txq->ift_ctx; 3759 3760 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3761 return (1); 3762 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3763 BUS_DMASYNC_POSTREAD); 3764 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3765 false)); 3766 } 3767 3768 static uint32_t 3769 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3770 { 3771 iflib_txq_t txq = r->cookie; 3772 if_ctx_t ctx = txq->ift_ctx; 3773 if_t ifp = ctx->ifc_ifp; 3774 struct mbuf *m, **mp; 3775 int avail, bytes_sent, skipped, count, err, i; 3776 int mcast_sent, pkt_sent, reclaimed; 3777 bool do_prefetch, rang, ring; 3778 3779 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3780 !LINK_ACTIVE(ctx))) { 3781 DBG_COUNTER_INC(txq_drain_notready); 3782 return (0); 3783 } 3784 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3785 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending); 3786 avail = IDXDIFF(pidx, cidx, r->size); 3787 3788 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3789 /* 3790 * The driver is unloading so we need to free all pending packets. 3791 */ 3792 DBG_COUNTER_INC(txq_drain_flushing); 3793 for (i = 0; i < avail; i++) { 3794 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3795 m_freem(r->items[(cidx + i) & (r->size-1)]); 3796 r->items[(cidx + i) & (r->size-1)] = NULL; 3797 } 3798 return (avail); 3799 } 3800 3801 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3802 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3803 CALLOUT_LOCK(txq); 3804 callout_stop(&txq->ift_timer); 3805 CALLOUT_UNLOCK(txq); 3806 DBG_COUNTER_INC(txq_drain_oactive); 3807 return (0); 3808 } 3809 3810 /* 3811 * If we've reclaimed any packets this queue cannot be hung. 3812 */ 3813 if (reclaimed) 3814 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3815 skipped = mcast_sent = bytes_sent = pkt_sent = 0; 3816 count = MIN(avail, TX_BATCH_SIZE); 3817 #ifdef INVARIANTS 3818 if (iflib_verbose_debug) 3819 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3820 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3821 #endif 3822 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3823 err = 0; 3824 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx) + 2; i++) { 3825 int rem = do_prefetch ? count - i : 0; 3826 3827 mp = _ring_peek_one(r, cidx, i, rem); 3828 MPASS(mp != NULL && *mp != NULL); 3829 3830 /* 3831 * Completion interrupts will use the address of the txq 3832 * as a sentinel to enqueue _something_ in order to acquire 3833 * the lock on the mp_ring (there's no direct lock call). 3834 * We obviously whave to check for these sentinel cases 3835 * and skip them. 3836 */ 3837 if (__predict_false(*mp == (struct mbuf *)txq)) { 3838 skipped++; 3839 continue; 3840 } 3841 err = iflib_encap(txq, mp); 3842 if (__predict_false(err)) { 3843 /* no room - bail out */ 3844 if (err == ENOBUFS) 3845 break; 3846 skipped++; 3847 /* we can't send this packet - skip it */ 3848 continue; 3849 } 3850 pkt_sent++; 3851 m = *mp; 3852 DBG_COUNTER_INC(tx_sent); 3853 bytes_sent += m->m_pkthdr.len; 3854 mcast_sent += !!(m->m_flags & M_MCAST); 3855 3856 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3857 break; 3858 ETHER_BPF_MTAP(ifp, m); 3859 rang = iflib_txd_db_check(txq, false); 3860 } 3861 3862 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3863 ring = rang ? false : (iflib_min_tx_latency | err); 3864 iflib_txd_db_check(txq, ring); 3865 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3866 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3867 if (mcast_sent) 3868 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3869 #ifdef INVARIANTS 3870 if (iflib_verbose_debug) 3871 printf("consumed=%d\n", skipped + pkt_sent); 3872 #endif 3873 return (skipped + pkt_sent); 3874 } 3875 3876 static uint32_t 3877 iflib_txq_drain_always(struct ifmp_ring *r) 3878 { 3879 return (1); 3880 } 3881 3882 static uint32_t 3883 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3884 { 3885 int i, avail; 3886 struct mbuf **mp; 3887 iflib_txq_t txq; 3888 3889 txq = r->cookie; 3890 3891 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3892 CALLOUT_LOCK(txq); 3893 callout_stop(&txq->ift_timer); 3894 CALLOUT_UNLOCK(txq); 3895 3896 avail = IDXDIFF(pidx, cidx, r->size); 3897 for (i = 0; i < avail; i++) { 3898 mp = _ring_peek_one(r, cidx, i, avail - i); 3899 if (__predict_false(*mp == (struct mbuf *)txq)) 3900 continue; 3901 m_freem(*mp); 3902 DBG_COUNTER_INC(tx_frees); 3903 } 3904 MPASS(ifmp_ring_is_stalled(r) == 0); 3905 return (avail); 3906 } 3907 3908 static void 3909 iflib_ifmp_purge(iflib_txq_t txq) 3910 { 3911 struct ifmp_ring *r; 3912 3913 r = txq->ift_br; 3914 r->drain = iflib_txq_drain_free; 3915 r->can_drain = iflib_txq_drain_always; 3916 3917 ifmp_ring_check_drainage(r, r->size); 3918 3919 r->drain = iflib_txq_drain; 3920 r->can_drain = iflib_txq_can_drain; 3921 } 3922 3923 static void 3924 _task_fn_tx(void *context) 3925 { 3926 iflib_txq_t txq = context; 3927 if_ctx_t ctx = txq->ift_ctx; 3928 if_t ifp = ctx->ifc_ifp; 3929 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3930 3931 #ifdef IFLIB_DIAGNOSTICS 3932 txq->ift_cpu_exec_count[curcpu]++; 3933 #endif 3934 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 3935 return; 3936 #ifdef DEV_NETMAP 3937 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 3938 netmap_tx_irq(ifp, txq->ift_id)) 3939 goto skip_ifmp; 3940 #endif 3941 #ifdef ALTQ 3942 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3943 iflib_altq_if_start(ifp); 3944 #endif 3945 if (txq->ift_db_pending) 3946 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3947 else if (!abdicate) 3948 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3949 /* 3950 * When abdicating, we always need to check drainage, not just when we don't enqueue 3951 */ 3952 if (abdicate) 3953 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3954 #ifdef DEV_NETMAP 3955 skip_ifmp: 3956 #endif 3957 if (ctx->ifc_flags & IFC_LEGACY) 3958 IFDI_INTR_ENABLE(ctx); 3959 else 3960 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3961 } 3962 3963 static void 3964 _task_fn_rx(void *context) 3965 { 3966 iflib_rxq_t rxq = context; 3967 if_ctx_t ctx = rxq->ifr_ctx; 3968 uint8_t more; 3969 uint16_t budget; 3970 #ifdef DEV_NETMAP 3971 u_int work = 0; 3972 int nmirq; 3973 #endif 3974 3975 #ifdef IFLIB_DIAGNOSTICS 3976 rxq->ifr_cpu_exec_count[curcpu]++; 3977 #endif 3978 DBG_COUNTER_INC(task_fn_rxs); 3979 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3980 return; 3981 #ifdef DEV_NETMAP 3982 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 3983 if (nmirq != NM_IRQ_PASS) { 3984 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 3985 goto skip_rxeof; 3986 } 3987 #endif 3988 budget = ctx->ifc_sysctl_rx_budget; 3989 if (budget == 0) 3990 budget = 16; /* XXX */ 3991 more = iflib_rxeof(rxq, budget); 3992 #ifdef DEV_NETMAP 3993 skip_rxeof: 3994 #endif 3995 if ((more & IFLIB_RXEOF_MORE) == 0) { 3996 if (ctx->ifc_flags & IFC_LEGACY) 3997 IFDI_INTR_ENABLE(ctx); 3998 else 3999 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 4000 DBG_COUNTER_INC(rx_intr_enables); 4001 } 4002 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4003 return; 4004 4005 if (more & IFLIB_RXEOF_MORE) 4006 GROUPTASK_ENQUEUE(&rxq->ifr_task); 4007 else if (more & IFLIB_RXEOF_EMPTY) 4008 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 4009 } 4010 4011 static void 4012 _task_fn_admin(void *context) 4013 { 4014 if_ctx_t ctx = context; 4015 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 4016 iflib_txq_t txq; 4017 int i; 4018 bool oactive, running, do_reset, do_watchdog, in_detach; 4019 4020 STATE_LOCK(ctx); 4021 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 4022 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 4023 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 4024 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 4025 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 4026 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 4027 STATE_UNLOCK(ctx); 4028 4029 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4030 return; 4031 if (in_detach) 4032 return; 4033 4034 CTX_LOCK(ctx); 4035 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4036 CALLOUT_LOCK(txq); 4037 callout_stop(&txq->ift_timer); 4038 CALLOUT_UNLOCK(txq); 4039 } 4040 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ) 4041 IFDI_ADMIN_COMPLETION_HANDLE(ctx); 4042 if (do_watchdog) { 4043 ctx->ifc_watchdog_events++; 4044 IFDI_WATCHDOG_RESET(ctx); 4045 } 4046 IFDI_UPDATE_ADMIN_STATUS(ctx); 4047 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4048 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 4049 txq->ift_timer.c_cpu); 4050 } 4051 IFDI_LINK_INTR_ENABLE(ctx); 4052 if (do_reset) 4053 iflib_if_init_locked(ctx); 4054 CTX_UNLOCK(ctx); 4055 4056 if (LINK_ACTIVE(ctx) == 0) 4057 return; 4058 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 4059 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4060 } 4061 4062 static void 4063 _task_fn_iov(void *context) 4064 { 4065 if_ctx_t ctx = context; 4066 4067 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 4068 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4069 return; 4070 4071 CTX_LOCK(ctx); 4072 IFDI_VFLR_HANDLE(ctx); 4073 CTX_UNLOCK(ctx); 4074 } 4075 4076 static int 4077 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4078 { 4079 int err; 4080 if_int_delay_info_t info; 4081 if_ctx_t ctx; 4082 4083 info = (if_int_delay_info_t)arg1; 4084 ctx = info->iidi_ctx; 4085 info->iidi_req = req; 4086 info->iidi_oidp = oidp; 4087 CTX_LOCK(ctx); 4088 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 4089 CTX_UNLOCK(ctx); 4090 return (err); 4091 } 4092 4093 /********************************************************************* 4094 * 4095 * IFNET FUNCTIONS 4096 * 4097 **********************************************************************/ 4098 4099 static void 4100 iflib_if_init_locked(if_ctx_t ctx) 4101 { 4102 iflib_stop(ctx); 4103 iflib_init_locked(ctx); 4104 } 4105 4106 static void 4107 iflib_if_init(void *arg) 4108 { 4109 if_ctx_t ctx = arg; 4110 4111 CTX_LOCK(ctx); 4112 iflib_if_init_locked(ctx); 4113 CTX_UNLOCK(ctx); 4114 } 4115 4116 static int 4117 iflib_if_transmit(if_t ifp, struct mbuf *m) 4118 { 4119 if_ctx_t ctx = if_getsoftc(ifp); 4120 4121 iflib_txq_t txq; 4122 int err, qidx; 4123 int abdicate = ctx->ifc_sysctl_tx_abdicate; 4124 4125 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 4126 DBG_COUNTER_INC(tx_frees); 4127 m_freem(m); 4128 return (ENETDOWN); 4129 } 4130 4131 MPASS(m->m_nextpkt == NULL); 4132 /* ALTQ-enabled interfaces always use queue 0. */ 4133 qidx = 0; 4134 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 4135 qidx = QIDX(ctx, m); 4136 /* 4137 * XXX calculate buf_ring based on flowid (divvy up bits?) 4138 */ 4139 txq = &ctx->ifc_txqs[qidx]; 4140 4141 #ifdef DRIVER_BACKPRESSURE 4142 if (txq->ift_closed) { 4143 while (m != NULL) { 4144 next = m->m_nextpkt; 4145 m->m_nextpkt = NULL; 4146 m_freem(m); 4147 DBG_COUNTER_INC(tx_frees); 4148 m = next; 4149 } 4150 return (ENOBUFS); 4151 } 4152 #endif 4153 #ifdef notyet 4154 qidx = count = 0; 4155 mp = marr; 4156 next = m; 4157 do { 4158 count++; 4159 next = next->m_nextpkt; 4160 } while (next != NULL); 4161 4162 if (count > nitems(marr)) 4163 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4164 /* XXX check nextpkt */ 4165 m_freem(m); 4166 /* XXX simplify for now */ 4167 DBG_COUNTER_INC(tx_frees); 4168 return (ENOBUFS); 4169 } 4170 for (next = m, i = 0; next != NULL; i++) { 4171 mp[i] = next; 4172 next = next->m_nextpkt; 4173 mp[i]->m_nextpkt = NULL; 4174 } 4175 #endif 4176 DBG_COUNTER_INC(tx_seen); 4177 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4178 4179 if (abdicate) 4180 GROUPTASK_ENQUEUE(&txq->ift_task); 4181 if (err) { 4182 if (!abdicate) 4183 GROUPTASK_ENQUEUE(&txq->ift_task); 4184 /* support forthcoming later */ 4185 #ifdef DRIVER_BACKPRESSURE 4186 txq->ift_closed = TRUE; 4187 #endif 4188 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4189 m_freem(m); 4190 DBG_COUNTER_INC(tx_frees); 4191 } 4192 4193 return (err); 4194 } 4195 4196 #ifdef ALTQ 4197 /* 4198 * The overall approach to integrating iflib with ALTQ is to continue to use 4199 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4200 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4201 * is redundant/unnecessary, but doing so minimizes the amount of 4202 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4203 * redundantly queueing to an intermediate mp_ring is swamped by the 4204 * performance limitations inherent in using ALTQ. 4205 * 4206 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4207 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4208 * given interface. If ALTQ is enabled for an interface, then all 4209 * transmitted packets for that interface will be submitted to the ALTQ 4210 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4211 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4212 * update stats that the iflib machinery handles, and which is sensitve to 4213 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4214 * will be installed as the start routine for use by ALTQ facilities that 4215 * need to trigger queue drains on a scheduled basis. 4216 * 4217 */ 4218 static void 4219 iflib_altq_if_start(if_t ifp) 4220 { 4221 struct ifaltq *ifq = &ifp->if_snd; 4222 struct mbuf *m; 4223 4224 IFQ_LOCK(ifq); 4225 IFQ_DEQUEUE_NOLOCK(ifq, m); 4226 while (m != NULL) { 4227 iflib_if_transmit(ifp, m); 4228 IFQ_DEQUEUE_NOLOCK(ifq, m); 4229 } 4230 IFQ_UNLOCK(ifq); 4231 } 4232 4233 static int 4234 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4235 { 4236 int err; 4237 4238 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4239 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4240 if (err == 0) 4241 iflib_altq_if_start(ifp); 4242 } else 4243 err = iflib_if_transmit(ifp, m); 4244 4245 return (err); 4246 } 4247 #endif /* ALTQ */ 4248 4249 static void 4250 iflib_if_qflush(if_t ifp) 4251 { 4252 if_ctx_t ctx = if_getsoftc(ifp); 4253 iflib_txq_t txq = ctx->ifc_txqs; 4254 int i; 4255 4256 STATE_LOCK(ctx); 4257 ctx->ifc_flags |= IFC_QFLUSH; 4258 STATE_UNLOCK(ctx); 4259 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4260 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4261 iflib_txq_check_drain(txq, 0); 4262 STATE_LOCK(ctx); 4263 ctx->ifc_flags &= ~IFC_QFLUSH; 4264 STATE_UNLOCK(ctx); 4265 4266 /* 4267 * When ALTQ is enabled, this will also take care of purging the 4268 * ALTQ queue(s). 4269 */ 4270 if_qflush(ifp); 4271 } 4272 4273 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4274 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4275 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4276 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG) 4277 4278 static int 4279 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4280 { 4281 if_ctx_t ctx = if_getsoftc(ifp); 4282 struct ifreq *ifr = (struct ifreq *)data; 4283 #if defined(INET) || defined(INET6) 4284 struct ifaddr *ifa = (struct ifaddr *)data; 4285 #endif 4286 bool avoid_reset = false; 4287 int err = 0, reinit = 0, bits; 4288 4289 switch (command) { 4290 case SIOCSIFADDR: 4291 #ifdef INET 4292 if (ifa->ifa_addr->sa_family == AF_INET) 4293 avoid_reset = true; 4294 #endif 4295 #ifdef INET6 4296 if (ifa->ifa_addr->sa_family == AF_INET6) 4297 avoid_reset = true; 4298 #endif 4299 /* 4300 ** Calling init results in link renegotiation, 4301 ** so we avoid doing it when possible. 4302 */ 4303 if (avoid_reset) { 4304 if_setflagbits(ifp, IFF_UP,0); 4305 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4306 reinit = 1; 4307 #ifdef INET 4308 if (!(if_getflags(ifp) & IFF_NOARP)) 4309 arp_ifinit(ifp, ifa); 4310 #endif 4311 } else 4312 err = ether_ioctl(ifp, command, data); 4313 break; 4314 case SIOCSIFMTU: 4315 CTX_LOCK(ctx); 4316 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4317 CTX_UNLOCK(ctx); 4318 break; 4319 } 4320 bits = if_getdrvflags(ifp); 4321 /* stop the driver and free any clusters before proceeding */ 4322 iflib_stop(ctx); 4323 4324 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4325 STATE_LOCK(ctx); 4326 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4327 ctx->ifc_flags |= IFC_MULTISEG; 4328 else 4329 ctx->ifc_flags &= ~IFC_MULTISEG; 4330 STATE_UNLOCK(ctx); 4331 err = if_setmtu(ifp, ifr->ifr_mtu); 4332 } 4333 iflib_init_locked(ctx); 4334 STATE_LOCK(ctx); 4335 if_setdrvflags(ifp, bits); 4336 STATE_UNLOCK(ctx); 4337 CTX_UNLOCK(ctx); 4338 break; 4339 case SIOCSIFFLAGS: 4340 CTX_LOCK(ctx); 4341 if (if_getflags(ifp) & IFF_UP) { 4342 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4343 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4344 (IFF_PROMISC | IFF_ALLMULTI)) { 4345 CTX_UNLOCK(ctx); 4346 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4347 CTX_LOCK(ctx); 4348 } 4349 } else 4350 reinit = 1; 4351 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4352 iflib_stop(ctx); 4353 } 4354 ctx->ifc_if_flags = if_getflags(ifp); 4355 CTX_UNLOCK(ctx); 4356 break; 4357 case SIOCADDMULTI: 4358 case SIOCDELMULTI: 4359 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4360 CTX_LOCK(ctx); 4361 IFDI_INTR_DISABLE(ctx); 4362 IFDI_MULTI_SET(ctx); 4363 IFDI_INTR_ENABLE(ctx); 4364 CTX_UNLOCK(ctx); 4365 } 4366 break; 4367 case SIOCSIFMEDIA: 4368 CTX_LOCK(ctx); 4369 IFDI_MEDIA_SET(ctx); 4370 CTX_UNLOCK(ctx); 4371 /* FALLTHROUGH */ 4372 case SIOCGIFMEDIA: 4373 case SIOCGIFXMEDIA: 4374 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4375 break; 4376 case SIOCGI2C: 4377 { 4378 struct ifi2creq i2c; 4379 4380 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4381 if (err != 0) 4382 break; 4383 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4384 err = EINVAL; 4385 break; 4386 } 4387 if (i2c.len > sizeof(i2c.data)) { 4388 err = EINVAL; 4389 break; 4390 } 4391 4392 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4393 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4394 sizeof(i2c)); 4395 break; 4396 } 4397 case SIOCSIFCAP: 4398 { 4399 int mask, setmask, oldmask; 4400 4401 oldmask = if_getcapenable(ifp); 4402 mask = ifr->ifr_reqcap ^ oldmask; 4403 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG; 4404 setmask = 0; 4405 #ifdef TCP_OFFLOAD 4406 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4407 #endif 4408 setmask |= (mask & IFCAP_FLAGS); 4409 setmask |= (mask & IFCAP_WOL); 4410 4411 /* 4412 * If any RX csum has changed, change all the ones that 4413 * are supported by the driver. 4414 */ 4415 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4416 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4417 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4418 } 4419 4420 /* 4421 * want to ensure that traffic has stopped before we change any of the flags 4422 */ 4423 if (setmask) { 4424 CTX_LOCK(ctx); 4425 bits = if_getdrvflags(ifp); 4426 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4427 iflib_stop(ctx); 4428 STATE_LOCK(ctx); 4429 if_togglecapenable(ifp, setmask); 4430 STATE_UNLOCK(ctx); 4431 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4432 iflib_init_locked(ctx); 4433 STATE_LOCK(ctx); 4434 if_setdrvflags(ifp, bits); 4435 STATE_UNLOCK(ctx); 4436 CTX_UNLOCK(ctx); 4437 } 4438 if_vlancap(ifp); 4439 break; 4440 } 4441 case SIOCGPRIVATE_0: 4442 case SIOCSDRVSPEC: 4443 case SIOCGDRVSPEC: 4444 CTX_LOCK(ctx); 4445 err = IFDI_PRIV_IOCTL(ctx, command, data); 4446 CTX_UNLOCK(ctx); 4447 break; 4448 default: 4449 err = ether_ioctl(ifp, command, data); 4450 break; 4451 } 4452 if (reinit) 4453 iflib_if_init(ctx); 4454 return (err); 4455 } 4456 4457 static uint64_t 4458 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4459 { 4460 if_ctx_t ctx = if_getsoftc(ifp); 4461 4462 return (IFDI_GET_COUNTER(ctx, cnt)); 4463 } 4464 4465 /********************************************************************* 4466 * 4467 * OTHER FUNCTIONS EXPORTED TO THE STACK 4468 * 4469 **********************************************************************/ 4470 4471 static void 4472 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4473 { 4474 if_ctx_t ctx = if_getsoftc(ifp); 4475 4476 if ((void *)ctx != arg) 4477 return; 4478 4479 if ((vtag == 0) || (vtag > 4095)) 4480 return; 4481 4482 if (iflib_in_detach(ctx)) 4483 return; 4484 4485 CTX_LOCK(ctx); 4486 /* Driver may need all untagged packets to be flushed */ 4487 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4488 iflib_stop(ctx); 4489 IFDI_VLAN_REGISTER(ctx, vtag); 4490 /* Re-init to load the changes, if required */ 4491 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4492 iflib_init_locked(ctx); 4493 CTX_UNLOCK(ctx); 4494 } 4495 4496 static void 4497 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4498 { 4499 if_ctx_t ctx = if_getsoftc(ifp); 4500 4501 if ((void *)ctx != arg) 4502 return; 4503 4504 if ((vtag == 0) || (vtag > 4095)) 4505 return; 4506 4507 CTX_LOCK(ctx); 4508 /* Driver may need all tagged packets to be flushed */ 4509 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4510 iflib_stop(ctx); 4511 IFDI_VLAN_UNREGISTER(ctx, vtag); 4512 /* Re-init to load the changes, if required */ 4513 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4514 iflib_init_locked(ctx); 4515 CTX_UNLOCK(ctx); 4516 } 4517 4518 static void 4519 iflib_led_func(void *arg, int onoff) 4520 { 4521 if_ctx_t ctx = arg; 4522 4523 CTX_LOCK(ctx); 4524 IFDI_LED_FUNC(ctx, onoff); 4525 CTX_UNLOCK(ctx); 4526 } 4527 4528 /********************************************************************* 4529 * 4530 * BUS FUNCTION DEFINITIONS 4531 * 4532 **********************************************************************/ 4533 4534 int 4535 iflib_device_probe(device_t dev) 4536 { 4537 const pci_vendor_info_t *ent; 4538 if_shared_ctx_t sctx; 4539 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4540 uint16_t pci_vendor_id; 4541 4542 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4543 return (ENOTSUP); 4544 4545 pci_vendor_id = pci_get_vendor(dev); 4546 pci_device_id = pci_get_device(dev); 4547 pci_subvendor_id = pci_get_subvendor(dev); 4548 pci_subdevice_id = pci_get_subdevice(dev); 4549 pci_rev_id = pci_get_revid(dev); 4550 if (sctx->isc_parse_devinfo != NULL) 4551 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4552 4553 ent = sctx->isc_vendor_info; 4554 while (ent->pvi_vendor_id != 0) { 4555 if (pci_vendor_id != ent->pvi_vendor_id) { 4556 ent++; 4557 continue; 4558 } 4559 if ((pci_device_id == ent->pvi_device_id) && 4560 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4561 (ent->pvi_subvendor_id == 0)) && 4562 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4563 (ent->pvi_subdevice_id == 0)) && 4564 ((pci_rev_id == ent->pvi_rev_id) || 4565 (ent->pvi_rev_id == 0))) { 4566 device_set_desc_copy(dev, ent->pvi_name); 4567 /* this needs to be changed to zero if the bus probing code 4568 * ever stops re-probing on best match because the sctx 4569 * may have its values over written by register calls 4570 * in subsequent probes 4571 */ 4572 return (BUS_PROBE_DEFAULT); 4573 } 4574 ent++; 4575 } 4576 return (ENXIO); 4577 } 4578 4579 int 4580 iflib_device_probe_vendor(device_t dev) 4581 { 4582 int probe; 4583 4584 probe = iflib_device_probe(dev); 4585 if (probe == BUS_PROBE_DEFAULT) 4586 return (BUS_PROBE_VENDOR); 4587 else 4588 return (probe); 4589 } 4590 4591 static void 4592 iflib_reset_qvalues(if_ctx_t ctx) 4593 { 4594 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4595 if_shared_ctx_t sctx = ctx->ifc_sctx; 4596 device_t dev = ctx->ifc_dev; 4597 int i; 4598 4599 if (ctx->ifc_sysctl_ntxqs != 0) 4600 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4601 if (ctx->ifc_sysctl_nrxqs != 0) 4602 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4603 4604 for (i = 0; i < sctx->isc_ntxqs; i++) { 4605 if (ctx->ifc_sysctl_ntxds[i] != 0) 4606 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4607 else 4608 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4609 } 4610 4611 for (i = 0; i < sctx->isc_nrxqs; i++) { 4612 if (ctx->ifc_sysctl_nrxds[i] != 0) 4613 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4614 else 4615 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4616 } 4617 4618 for (i = 0; i < sctx->isc_nrxqs; i++) { 4619 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4620 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4621 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4622 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4623 } 4624 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4625 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4626 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4627 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4628 } 4629 if (!powerof2(scctx->isc_nrxd[i])) { 4630 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4631 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4632 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4633 } 4634 } 4635 4636 for (i = 0; i < sctx->isc_ntxqs; i++) { 4637 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4638 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4639 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4640 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4641 } 4642 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4643 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4644 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4645 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4646 } 4647 if (!powerof2(scctx->isc_ntxd[i])) { 4648 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4649 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4650 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4651 } 4652 } 4653 } 4654 4655 static void 4656 iflib_add_pfil(if_ctx_t ctx) 4657 { 4658 struct pfil_head *pfil; 4659 struct pfil_head_args pa; 4660 iflib_rxq_t rxq; 4661 int i; 4662 4663 pa.pa_version = PFIL_VERSION; 4664 pa.pa_flags = PFIL_IN; 4665 pa.pa_type = PFIL_TYPE_ETHERNET; 4666 pa.pa_headname = ctx->ifc_ifp->if_xname; 4667 pfil = pfil_head_register(&pa); 4668 4669 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4670 rxq->pfil = pfil; 4671 } 4672 } 4673 4674 static void 4675 iflib_rem_pfil(if_ctx_t ctx) 4676 { 4677 struct pfil_head *pfil; 4678 iflib_rxq_t rxq; 4679 int i; 4680 4681 rxq = ctx->ifc_rxqs; 4682 pfil = rxq->pfil; 4683 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4684 rxq->pfil = NULL; 4685 } 4686 pfil_head_unregister(pfil); 4687 } 4688 4689 4690 /* 4691 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from 4692 * cpuid and wrapping as necessary. 4693 */ 4694 static unsigned int 4695 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n) 4696 { 4697 unsigned int first_valid; 4698 unsigned int last_valid; 4699 4700 /* cpuid should always be in the valid set */ 4701 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4702 4703 /* valid set should never be empty */ 4704 MPASS(!CPU_EMPTY(&ctx->ifc_cpus)); 4705 4706 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4707 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4708 n = n % CPU_COUNT(&ctx->ifc_cpus); 4709 while (n > 0) { 4710 do { 4711 cpuid++; 4712 if (cpuid > last_valid) 4713 cpuid = first_valid; 4714 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4715 n--; 4716 } 4717 4718 return (cpuid); 4719 } 4720 4721 #if defined(SMP) && defined(SCHED_ULE) 4722 extern struct cpu_group *cpu_top; /* CPU topology */ 4723 4724 static int 4725 find_child_with_core(int cpu, struct cpu_group *grp) 4726 { 4727 int i; 4728 4729 if (grp->cg_children == 0) 4730 return -1; 4731 4732 MPASS(grp->cg_child); 4733 for (i = 0; i < grp->cg_children; i++) { 4734 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 4735 return i; 4736 } 4737 4738 return -1; 4739 } 4740 4741 4742 /* 4743 * Find an L2 neighbor of the given CPU or return -1 if none found. This 4744 * does not distinguish among multiple L2 neighbors if the given CPU has 4745 * more than one (it will always return the same result in that case). 4746 */ 4747 static int 4748 find_l2_neighbor(int cpu) 4749 { 4750 struct cpu_group *grp; 4751 int i; 4752 4753 grp = cpu_top; 4754 if (grp == NULL) 4755 return -1; 4756 4757 /* 4758 * Find the smallest CPU group that contains the given core. 4759 */ 4760 i = 0; 4761 while ((i = find_child_with_core(cpu, grp)) != -1) { 4762 /* 4763 * If the smallest group containing the given CPU has less 4764 * than two members, we conclude the given CPU has no 4765 * L2 neighbor. 4766 */ 4767 if (grp->cg_child[i].cg_count <= 1) 4768 return (-1); 4769 grp = &grp->cg_child[i]; 4770 } 4771 4772 /* Must share L2. */ 4773 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 4774 return -1; 4775 4776 /* 4777 * Select the first member of the set that isn't the reference 4778 * CPU, which at this point is guaranteed to exist. 4779 */ 4780 for (i = 0; i < CPU_SETSIZE; i++) { 4781 if (CPU_ISSET(i, &grp->cg_mask) && i != cpu) 4782 return (i); 4783 } 4784 4785 /* Should never be reached */ 4786 return (-1); 4787 } 4788 4789 #else 4790 static int 4791 find_l2_neighbor(int cpu) 4792 { 4793 4794 return (-1); 4795 } 4796 #endif 4797 4798 /* 4799 * CPU mapping behaviors 4800 * --------------------- 4801 * 'separate txrx' refers to the separate_txrx sysctl 4802 * 'use logical' refers to the use_logical_cores sysctl 4803 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded 4804 * 4805 * separate use INTR 4806 * txrx logical CPUS result 4807 * ---------- --------- ------ ------------------------------------------------ 4808 * - - X RX and TX queues mapped to consecutive physical 4809 * cores with RX/TX pairs on same core and excess 4810 * of either following 4811 * - X X RX and TX queues mapped to consecutive cores 4812 * of any type with RX/TX pairs on same core and 4813 * excess of either following 4814 * X - X RX and TX queues mapped to consecutive physical 4815 * cores; all RX then all TX 4816 * X X X RX queues mapped to consecutive physical cores 4817 * first, then TX queues mapped to L2 neighbor of 4818 * the corresponding RX queue if one exists, 4819 * otherwise to consecutive physical cores 4820 * - n/a - RX and TX queues mapped to consecutive cores of 4821 * any type with RX/TX pairs on same core and excess 4822 * of either following 4823 * X n/a - RX and TX queues mapped to consecutive cores of 4824 * any type; all RX then all TX 4825 */ 4826 static unsigned int 4827 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid, 4828 bool is_tx) 4829 { 4830 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4831 unsigned int core_index; 4832 4833 if (ctx->ifc_sysctl_separate_txrx) { 4834 /* 4835 * When using separate CPUs for TX and RX, the assignment 4836 * will always be of a consecutive CPU out of the set of 4837 * context CPUs, except for the specific case where the 4838 * context CPUs are phsyical cores, the use of logical cores 4839 * has been enabled, the assignment is for TX, the TX qid 4840 * corresponds to an RX qid, and the CPU assigned to the 4841 * corresponding RX queue has an L2 neighbor. 4842 */ 4843 if (ctx->ifc_sysctl_use_logical_cores && 4844 ctx->ifc_cpus_are_physical_cores && 4845 is_tx && qid < scctx->isc_nrxqsets) { 4846 int l2_neighbor; 4847 unsigned int rx_cpuid; 4848 4849 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid); 4850 l2_neighbor = find_l2_neighbor(rx_cpuid); 4851 if (l2_neighbor != -1) { 4852 return (l2_neighbor); 4853 } 4854 /* 4855 * ... else fall through to the normal 4856 * consecutive-after-RX assignment scheme. 4857 * 4858 * Note that we are assuming that all RX queue CPUs 4859 * have an L2 neighbor, or all do not. If a mixed 4860 * scenario is possible, we will have to keep track 4861 * separately of how many queues prior to this one 4862 * were not able to be assigned to an L2 neighbor. 4863 */ 4864 } 4865 if (is_tx) 4866 core_index = scctx->isc_nrxqsets + qid; 4867 else 4868 core_index = qid; 4869 } else { 4870 core_index = qid; 4871 } 4872 4873 return (cpuid_advance(ctx, base_cpuid, core_index)); 4874 } 4875 4876 static uint16_t 4877 get_ctx_core_offset(if_ctx_t ctx) 4878 { 4879 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4880 struct cpu_offset *op; 4881 cpuset_t assigned_cpus; 4882 unsigned int cores_consumed; 4883 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset; 4884 unsigned int first_valid; 4885 unsigned int last_valid; 4886 unsigned int i; 4887 4888 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4889 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4890 4891 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) { 4892 /* 4893 * Align the user-chosen base CPU ID to the next valid CPU 4894 * for this device. If the chosen base CPU ID is smaller 4895 * than the first valid CPU or larger than the last valid 4896 * CPU, we assume the user does not know what the valid 4897 * range is for this device and is thinking in terms of a 4898 * zero-based reference frame, and so we shift the given 4899 * value into the valid range (and wrap accordingly) so the 4900 * intent is translated to the proper frame of reference. 4901 * If the base CPU ID is within the valid first/last, but 4902 * does not correspond to a valid CPU, it is advanced to the 4903 * next valid CPU (wrapping if necessary). 4904 */ 4905 if (base_cpuid < first_valid || base_cpuid > last_valid) { 4906 /* shift from zero-based to first_valid-based */ 4907 base_cpuid += first_valid; 4908 /* wrap to range [first_valid, last_valid] */ 4909 base_cpuid = (base_cpuid - first_valid) % 4910 (last_valid - first_valid + 1); 4911 } 4912 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) { 4913 /* 4914 * base_cpuid is in [first_valid, last_valid], but 4915 * not a member of the valid set. In this case, 4916 * there will always be a member of the valid set 4917 * with a CPU ID that is greater than base_cpuid, 4918 * and we simply advance to it. 4919 */ 4920 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) 4921 base_cpuid++; 4922 } 4923 return (base_cpuid); 4924 } 4925 4926 /* 4927 * Determine how many cores will be consumed by performing the CPU 4928 * assignments and counting how many of the assigned CPUs correspond 4929 * to CPUs in the set of context CPUs. This is done using the CPU 4930 * ID first_valid as the base CPU ID, as the base CPU must be within 4931 * the set of context CPUs. 4932 * 4933 * Note not all assigned CPUs will be in the set of context CPUs 4934 * when separate CPUs are being allocated to TX and RX queues, 4935 * assignment to logical cores has been enabled, the set of context 4936 * CPUs contains only physical CPUs, and TX queues are mapped to L2 4937 * neighbors of CPUs that RX queues have been mapped to - in this 4938 * case we do only want to count how many CPUs in the set of context 4939 * CPUs have been consumed, as that determines the next CPU in that 4940 * set to start allocating at for the next device for which 4941 * core_offset is not set. 4942 */ 4943 CPU_ZERO(&assigned_cpus); 4944 for (i = 0; i < scctx->isc_ntxqsets; i++) 4945 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true), 4946 &assigned_cpus); 4947 for (i = 0; i < scctx->isc_nrxqsets; i++) 4948 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false), 4949 &assigned_cpus); 4950 CPU_AND(&assigned_cpus, &ctx->ifc_cpus); 4951 cores_consumed = CPU_COUNT(&assigned_cpus); 4952 4953 mtx_lock(&cpu_offset_mtx); 4954 SLIST_FOREACH(op, &cpu_offsets, entries) { 4955 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4956 base_cpuid = op->next_cpuid; 4957 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid, 4958 cores_consumed); 4959 MPASS(op->refcount < UINT_MAX); 4960 op->refcount++; 4961 break; 4962 } 4963 } 4964 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) { 4965 base_cpuid = first_valid; 4966 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4967 M_NOWAIT | M_ZERO); 4968 if (op == NULL) { 4969 device_printf(ctx->ifc_dev, 4970 "allocation for cpu offset failed.\n"); 4971 } else { 4972 op->next_cpuid = cpuid_advance(ctx, base_cpuid, 4973 cores_consumed); 4974 op->refcount = 1; 4975 CPU_COPY(&ctx->ifc_cpus, &op->set); 4976 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4977 } 4978 } 4979 mtx_unlock(&cpu_offset_mtx); 4980 4981 return (base_cpuid); 4982 } 4983 4984 static void 4985 unref_ctx_core_offset(if_ctx_t ctx) 4986 { 4987 struct cpu_offset *op, *top; 4988 4989 mtx_lock(&cpu_offset_mtx); 4990 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4991 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4992 MPASS(op->refcount > 0); 4993 op->refcount--; 4994 if (op->refcount == 0) { 4995 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4996 free(op, M_IFLIB); 4997 } 4998 break; 4999 } 5000 } 5001 mtx_unlock(&cpu_offset_mtx); 5002 } 5003 5004 int 5005 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 5006 { 5007 if_ctx_t ctx; 5008 if_t ifp; 5009 if_softc_ctx_t scctx; 5010 kobjop_desc_t kobj_desc; 5011 kobj_method_t *kobj_method; 5012 int err, msix, rid; 5013 int num_txd, num_rxd; 5014 5015 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 5016 5017 if (sc == NULL) { 5018 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 5019 device_set_softc(dev, ctx); 5020 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5021 } 5022 5023 ctx->ifc_sctx = sctx; 5024 ctx->ifc_dev = dev; 5025 ctx->ifc_softc = sc; 5026 5027 if ((err = iflib_register(ctx)) != 0) { 5028 device_printf(dev, "iflib_register failed %d\n", err); 5029 goto fail_ctx_free; 5030 } 5031 iflib_add_device_sysctl_pre(ctx); 5032 5033 scctx = &ctx->ifc_softc_ctx; 5034 ifp = ctx->ifc_ifp; 5035 5036 iflib_reset_qvalues(ctx); 5037 CTX_LOCK(ctx); 5038 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5039 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5040 goto fail_unlock; 5041 } 5042 _iflib_pre_assert(scctx); 5043 ctx->ifc_txrx = *scctx->isc_txrx; 5044 5045 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR)); 5046 5047 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 5048 ctx->ifc_mediap = scctx->isc_media; 5049 5050 #ifdef INVARIANTS 5051 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5052 MPASS(scctx->isc_tx_csum_flags); 5053 #endif 5054 5055 if_setcapabilities(ifp, 5056 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG); 5057 if_setcapenable(ifp, 5058 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG); 5059 5060 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5061 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5062 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5063 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5064 5065 num_txd = iflib_num_tx_descs(ctx); 5066 num_rxd = iflib_num_rx_descs(ctx); 5067 5068 /* XXX change for per-queue sizes */ 5069 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5070 num_txd, num_rxd); 5071 5072 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5073 scctx->isc_tx_nsegments = max(1, num_txd / 5074 MAX_SINGLE_PACKET_FRACTION); 5075 if (scctx->isc_tx_tso_segments_max > num_txd / 5076 MAX_SINGLE_PACKET_FRACTION) 5077 scctx->isc_tx_tso_segments_max = max(1, 5078 num_txd / MAX_SINGLE_PACKET_FRACTION); 5079 5080 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5081 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5082 /* 5083 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5084 * but some MACs do. 5085 */ 5086 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5087 IP_MAXPACKET)); 5088 /* 5089 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5090 * into account. In the worst case, each of these calls will 5091 * add another mbuf and, thus, the requirement for another DMA 5092 * segment. So for best performance, it doesn't make sense to 5093 * advertize a maximum of TSO segments that typically will 5094 * require defragmentation in iflib_encap(). 5095 */ 5096 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5097 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5098 } 5099 if (scctx->isc_rss_table_size == 0) 5100 scctx->isc_rss_table_size = 64; 5101 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5102 5103 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5104 /* XXX format name */ 5105 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5106 NULL, NULL, "admin"); 5107 5108 /* Set up cpu set. If it fails, use the set of all CPUs. */ 5109 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 5110 device_printf(dev, "Unable to fetch CPU list\n"); 5111 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 5112 ctx->ifc_cpus_are_physical_cores = false; 5113 } else 5114 ctx->ifc_cpus_are_physical_cores = true; 5115 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 5116 5117 /* 5118 ** Now set up MSI or MSI-X, should return us the number of supported 5119 ** vectors (will be 1 for a legacy interrupt and MSI). 5120 */ 5121 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 5122 msix = scctx->isc_vectors; 5123 } else if (scctx->isc_msix_bar != 0) 5124 /* 5125 * The simple fact that isc_msix_bar is not 0 does not mean we 5126 * we have a good value there that is known to work. 5127 */ 5128 msix = iflib_msix_init(ctx); 5129 else { 5130 scctx->isc_vectors = 1; 5131 scctx->isc_ntxqsets = 1; 5132 scctx->isc_nrxqsets = 1; 5133 scctx->isc_intr = IFLIB_INTR_LEGACY; 5134 msix = 0; 5135 } 5136 /* Get memory for the station queues */ 5137 if ((err = iflib_queues_alloc(ctx))) { 5138 device_printf(dev, "Unable to allocate queue memory\n"); 5139 goto fail_intr_free; 5140 } 5141 5142 if ((err = iflib_qset_structures_setup(ctx))) 5143 goto fail_queues; 5144 5145 /* 5146 * Now that we know how many queues there are, get the core offset. 5147 */ 5148 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 5149 5150 if (msix > 1) { 5151 /* 5152 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 5153 * aren't the default NULL implementation. 5154 */ 5155 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 5156 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5157 kobj_desc); 5158 if (kobj_method == &kobj_desc->deflt) { 5159 device_printf(dev, 5160 "MSI-X requires ifdi_rx_queue_intr_enable method"); 5161 err = EOPNOTSUPP; 5162 goto fail_queues; 5163 } 5164 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 5165 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5166 kobj_desc); 5167 if (kobj_method == &kobj_desc->deflt) { 5168 device_printf(dev, 5169 "MSI-X requires ifdi_tx_queue_intr_enable method"); 5170 err = EOPNOTSUPP; 5171 goto fail_queues; 5172 } 5173 5174 /* 5175 * Assign the MSI-X vectors. 5176 * Note that the default NULL ifdi_msix_intr_assign method will 5177 * fail here, too. 5178 */ 5179 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 5180 if (err != 0) { 5181 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 5182 err); 5183 goto fail_queues; 5184 } 5185 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 5186 rid = 0; 5187 if (scctx->isc_intr == IFLIB_INTR_MSI) { 5188 MPASS(msix == 1); 5189 rid = 1; 5190 } 5191 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 5192 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 5193 goto fail_queues; 5194 } 5195 } else { 5196 device_printf(dev, 5197 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 5198 err = ENODEV; 5199 goto fail_queues; 5200 } 5201 5202 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5203 5204 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5205 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5206 goto fail_detach; 5207 } 5208 5209 /* 5210 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5211 * This must appear after the call to ether_ifattach() because 5212 * ether_ifattach() sets if_hdrlen to the default value. 5213 */ 5214 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5215 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5216 5217 if ((err = iflib_netmap_attach(ctx))) { 5218 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 5219 goto fail_detach; 5220 } 5221 *ctxp = ctx; 5222 5223 DEBUGNET_SET(ctx->ifc_ifp, iflib); 5224 5225 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5226 iflib_add_device_sysctl_post(ctx); 5227 iflib_add_pfil(ctx); 5228 ctx->ifc_flags |= IFC_INIT_DONE; 5229 CTX_UNLOCK(ctx); 5230 5231 return (0); 5232 5233 fail_detach: 5234 ether_ifdetach(ctx->ifc_ifp); 5235 fail_queues: 5236 iflib_tqg_detach(ctx); 5237 iflib_tx_structures_free(ctx); 5238 iflib_rx_structures_free(ctx); 5239 IFDI_DETACH(ctx); 5240 IFDI_QUEUES_FREE(ctx); 5241 fail_intr_free: 5242 iflib_free_intr_mem(ctx); 5243 fail_unlock: 5244 CTX_UNLOCK(ctx); 5245 iflib_deregister(ctx); 5246 fail_ctx_free: 5247 device_set_softc(ctx->ifc_dev, NULL); 5248 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5249 free(ctx->ifc_softc, M_IFLIB); 5250 free(ctx, M_IFLIB); 5251 return (err); 5252 } 5253 5254 int 5255 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 5256 struct iflib_cloneattach_ctx *clctx) 5257 { 5258 int num_txd, num_rxd; 5259 int err; 5260 if_ctx_t ctx; 5261 if_t ifp; 5262 if_softc_ctx_t scctx; 5263 int i; 5264 void *sc; 5265 5266 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 5267 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 5268 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5269 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 5270 ctx->ifc_flags |= IFC_PSEUDO; 5271 5272 ctx->ifc_sctx = sctx; 5273 ctx->ifc_softc = sc; 5274 ctx->ifc_dev = dev; 5275 5276 if ((err = iflib_register(ctx)) != 0) { 5277 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 5278 goto fail_ctx_free; 5279 } 5280 iflib_add_device_sysctl_pre(ctx); 5281 5282 scctx = &ctx->ifc_softc_ctx; 5283 ifp = ctx->ifc_ifp; 5284 5285 iflib_reset_qvalues(ctx); 5286 CTX_LOCK(ctx); 5287 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5288 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5289 goto fail_unlock; 5290 } 5291 if (sctx->isc_flags & IFLIB_GEN_MAC) 5292 ether_gen_addr(ifp, &ctx->ifc_mac); 5293 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 5294 clctx->cc_params)) != 0) { 5295 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 5296 goto fail_unlock; 5297 } 5298 #ifdef INVARIANTS 5299 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5300 MPASS(scctx->isc_tx_csum_flags); 5301 #endif 5302 5303 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 5304 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 5305 5306 ifp->if_flags |= IFF_NOGROUP; 5307 if (sctx->isc_flags & IFLIB_PSEUDO) { 5308 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 5309 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 5310 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) { 5311 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5312 } else { 5313 if_attach(ctx->ifc_ifp); 5314 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t)); 5315 } 5316 5317 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5318 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5319 goto fail_detach; 5320 } 5321 *ctxp = ctx; 5322 5323 /* 5324 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5325 * This must appear after the call to ether_ifattach() because 5326 * ether_ifattach() sets if_hdrlen to the default value. 5327 */ 5328 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5329 if_setifheaderlen(ifp, 5330 sizeof(struct ether_vlan_header)); 5331 5332 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5333 iflib_add_device_sysctl_post(ctx); 5334 ctx->ifc_flags |= IFC_INIT_DONE; 5335 CTX_UNLOCK(ctx); 5336 return (0); 5337 } 5338 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 5339 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 5340 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 5341 5342 _iflib_pre_assert(scctx); 5343 ctx->ifc_txrx = *scctx->isc_txrx; 5344 5345 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5346 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5347 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5348 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5349 5350 num_txd = iflib_num_tx_descs(ctx); 5351 num_rxd = iflib_num_rx_descs(ctx); 5352 5353 /* XXX change for per-queue sizes */ 5354 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5355 num_txd, num_rxd); 5356 5357 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5358 scctx->isc_tx_nsegments = max(1, num_txd / 5359 MAX_SINGLE_PACKET_FRACTION); 5360 if (scctx->isc_tx_tso_segments_max > num_txd / 5361 MAX_SINGLE_PACKET_FRACTION) 5362 scctx->isc_tx_tso_segments_max = max(1, 5363 num_txd / MAX_SINGLE_PACKET_FRACTION); 5364 5365 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5366 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5367 /* 5368 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5369 * but some MACs do. 5370 */ 5371 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5372 IP_MAXPACKET)); 5373 /* 5374 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5375 * into account. In the worst case, each of these calls will 5376 * add another mbuf and, thus, the requirement for another DMA 5377 * segment. So for best performance, it doesn't make sense to 5378 * advertize a maximum of TSO segments that typically will 5379 * require defragmentation in iflib_encap(). 5380 */ 5381 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5382 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5383 } 5384 if (scctx->isc_rss_table_size == 0) 5385 scctx->isc_rss_table_size = 64; 5386 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5387 5388 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5389 /* XXX format name */ 5390 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5391 NULL, NULL, "admin"); 5392 5393 /* XXX --- can support > 1 -- but keep it simple for now */ 5394 scctx->isc_intr = IFLIB_INTR_LEGACY; 5395 5396 /* Get memory for the station queues */ 5397 if ((err = iflib_queues_alloc(ctx))) { 5398 device_printf(dev, "Unable to allocate queue memory\n"); 5399 goto fail_iflib_detach; 5400 } 5401 5402 if ((err = iflib_qset_structures_setup(ctx))) { 5403 device_printf(dev, "qset structure setup failed %d\n", err); 5404 goto fail_queues; 5405 } 5406 5407 /* 5408 * XXX What if anything do we want to do about interrupts? 5409 */ 5410 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5411 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5412 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5413 goto fail_detach; 5414 } 5415 5416 /* 5417 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5418 * This must appear after the call to ether_ifattach() because 5419 * ether_ifattach() sets if_hdrlen to the default value. 5420 */ 5421 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5422 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5423 5424 /* XXX handle more than one queue */ 5425 for (i = 0; i < scctx->isc_nrxqsets; i++) 5426 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 5427 5428 *ctxp = ctx; 5429 5430 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5431 iflib_add_device_sysctl_post(ctx); 5432 ctx->ifc_flags |= IFC_INIT_DONE; 5433 CTX_UNLOCK(ctx); 5434 5435 return (0); 5436 fail_detach: 5437 ether_ifdetach(ctx->ifc_ifp); 5438 fail_queues: 5439 iflib_tqg_detach(ctx); 5440 iflib_tx_structures_free(ctx); 5441 iflib_rx_structures_free(ctx); 5442 fail_iflib_detach: 5443 IFDI_DETACH(ctx); 5444 IFDI_QUEUES_FREE(ctx); 5445 fail_unlock: 5446 CTX_UNLOCK(ctx); 5447 iflib_deregister(ctx); 5448 fail_ctx_free: 5449 free(ctx->ifc_softc, M_IFLIB); 5450 free(ctx, M_IFLIB); 5451 return (err); 5452 } 5453 5454 int 5455 iflib_pseudo_deregister(if_ctx_t ctx) 5456 { 5457 if_t ifp = ctx->ifc_ifp; 5458 if_shared_ctx_t sctx = ctx->ifc_sctx; 5459 5460 /* Unregister VLAN event handlers early */ 5461 iflib_unregister_vlan_handlers(ctx); 5462 5463 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5464 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) { 5465 bpfdetach(ifp); 5466 if_detach(ifp); 5467 } else { 5468 ether_ifdetach(ifp); 5469 } 5470 5471 iflib_tqg_detach(ctx); 5472 iflib_tx_structures_free(ctx); 5473 iflib_rx_structures_free(ctx); 5474 IFDI_DETACH(ctx); 5475 IFDI_QUEUES_FREE(ctx); 5476 5477 iflib_deregister(ctx); 5478 5479 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5480 free(ctx->ifc_softc, M_IFLIB); 5481 free(ctx, M_IFLIB); 5482 return (0); 5483 } 5484 5485 int 5486 iflib_device_attach(device_t dev) 5487 { 5488 if_ctx_t ctx; 5489 if_shared_ctx_t sctx; 5490 5491 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5492 return (ENOTSUP); 5493 5494 pci_enable_busmaster(dev); 5495 5496 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5497 } 5498 5499 int 5500 iflib_device_deregister(if_ctx_t ctx) 5501 { 5502 if_t ifp = ctx->ifc_ifp; 5503 device_t dev = ctx->ifc_dev; 5504 5505 /* Make sure VLANS are not using driver */ 5506 if (if_vlantrunkinuse(ifp)) { 5507 device_printf(dev, "Vlan in use, detach first\n"); 5508 return (EBUSY); 5509 } 5510 #ifdef PCI_IOV 5511 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5512 device_printf(dev, "SR-IOV in use; detach first.\n"); 5513 return (EBUSY); 5514 } 5515 #endif 5516 5517 STATE_LOCK(ctx); 5518 ctx->ifc_flags |= IFC_IN_DETACH; 5519 STATE_UNLOCK(ctx); 5520 5521 /* Unregister VLAN handlers before calling iflib_stop() */ 5522 iflib_unregister_vlan_handlers(ctx); 5523 5524 iflib_netmap_detach(ifp); 5525 ether_ifdetach(ifp); 5526 5527 CTX_LOCK(ctx); 5528 iflib_stop(ctx); 5529 CTX_UNLOCK(ctx); 5530 5531 iflib_rem_pfil(ctx); 5532 if (ctx->ifc_led_dev != NULL) 5533 led_destroy(ctx->ifc_led_dev); 5534 5535 iflib_tqg_detach(ctx); 5536 iflib_tx_structures_free(ctx); 5537 iflib_rx_structures_free(ctx); 5538 5539 CTX_LOCK(ctx); 5540 IFDI_DETACH(ctx); 5541 IFDI_QUEUES_FREE(ctx); 5542 CTX_UNLOCK(ctx); 5543 5544 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5545 iflib_free_intr_mem(ctx); 5546 5547 bus_generic_detach(dev); 5548 5549 iflib_deregister(ctx); 5550 5551 device_set_softc(ctx->ifc_dev, NULL); 5552 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5553 free(ctx->ifc_softc, M_IFLIB); 5554 unref_ctx_core_offset(ctx); 5555 free(ctx, M_IFLIB); 5556 return (0); 5557 } 5558 5559 static void 5560 iflib_tqg_detach(if_ctx_t ctx) 5561 { 5562 iflib_txq_t txq; 5563 iflib_rxq_t rxq; 5564 int i; 5565 struct taskqgroup *tqg; 5566 5567 /* XXX drain any dependent tasks */ 5568 tqg = qgroup_if_io_tqg; 5569 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5570 callout_drain(&txq->ift_timer); 5571 #ifdef DEV_NETMAP 5572 callout_drain(&txq->ift_netmap_timer); 5573 #endif /* DEV_NETMAP */ 5574 if (txq->ift_task.gt_uniq != NULL) 5575 taskqgroup_detach(tqg, &txq->ift_task); 5576 } 5577 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5578 if (rxq->ifr_task.gt_uniq != NULL) 5579 taskqgroup_detach(tqg, &rxq->ifr_task); 5580 } 5581 tqg = qgroup_if_config_tqg; 5582 if (ctx->ifc_admin_task.gt_uniq != NULL) 5583 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5584 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5585 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5586 } 5587 5588 static void 5589 iflib_free_intr_mem(if_ctx_t ctx) 5590 { 5591 5592 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5593 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5594 } 5595 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5596 pci_release_msi(ctx->ifc_dev); 5597 } 5598 if (ctx->ifc_msix_mem != NULL) { 5599 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5600 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5601 ctx->ifc_msix_mem = NULL; 5602 } 5603 } 5604 5605 int 5606 iflib_device_detach(device_t dev) 5607 { 5608 if_ctx_t ctx = device_get_softc(dev); 5609 5610 return (iflib_device_deregister(ctx)); 5611 } 5612 5613 int 5614 iflib_device_suspend(device_t dev) 5615 { 5616 if_ctx_t ctx = device_get_softc(dev); 5617 5618 CTX_LOCK(ctx); 5619 IFDI_SUSPEND(ctx); 5620 CTX_UNLOCK(ctx); 5621 5622 return bus_generic_suspend(dev); 5623 } 5624 int 5625 iflib_device_shutdown(device_t dev) 5626 { 5627 if_ctx_t ctx = device_get_softc(dev); 5628 5629 CTX_LOCK(ctx); 5630 IFDI_SHUTDOWN(ctx); 5631 CTX_UNLOCK(ctx); 5632 5633 return bus_generic_suspend(dev); 5634 } 5635 5636 int 5637 iflib_device_resume(device_t dev) 5638 { 5639 if_ctx_t ctx = device_get_softc(dev); 5640 iflib_txq_t txq = ctx->ifc_txqs; 5641 5642 CTX_LOCK(ctx); 5643 IFDI_RESUME(ctx); 5644 iflib_if_init_locked(ctx); 5645 CTX_UNLOCK(ctx); 5646 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5647 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5648 5649 return (bus_generic_resume(dev)); 5650 } 5651 5652 int 5653 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5654 { 5655 int error; 5656 if_ctx_t ctx = device_get_softc(dev); 5657 5658 CTX_LOCK(ctx); 5659 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5660 CTX_UNLOCK(ctx); 5661 5662 return (error); 5663 } 5664 5665 void 5666 iflib_device_iov_uninit(device_t dev) 5667 { 5668 if_ctx_t ctx = device_get_softc(dev); 5669 5670 CTX_LOCK(ctx); 5671 IFDI_IOV_UNINIT(ctx); 5672 CTX_UNLOCK(ctx); 5673 } 5674 5675 int 5676 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5677 { 5678 int error; 5679 if_ctx_t ctx = device_get_softc(dev); 5680 5681 CTX_LOCK(ctx); 5682 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5683 CTX_UNLOCK(ctx); 5684 5685 return (error); 5686 } 5687 5688 /********************************************************************* 5689 * 5690 * MODULE FUNCTION DEFINITIONS 5691 * 5692 **********************************************************************/ 5693 5694 /* 5695 * - Start a fast taskqueue thread for each core 5696 * - Start a taskqueue for control operations 5697 */ 5698 static int 5699 iflib_module_init(void) 5700 { 5701 iflib_timer_default = hz / 2; 5702 return (0); 5703 } 5704 5705 static int 5706 iflib_module_event_handler(module_t mod, int what, void *arg) 5707 { 5708 int err; 5709 5710 switch (what) { 5711 case MOD_LOAD: 5712 if ((err = iflib_module_init()) != 0) 5713 return (err); 5714 break; 5715 case MOD_UNLOAD: 5716 return (EBUSY); 5717 default: 5718 return (EOPNOTSUPP); 5719 } 5720 5721 return (0); 5722 } 5723 5724 /********************************************************************* 5725 * 5726 * PUBLIC FUNCTION DEFINITIONS 5727 * ordered as in iflib.h 5728 * 5729 **********************************************************************/ 5730 5731 static void 5732 _iflib_assert(if_shared_ctx_t sctx) 5733 { 5734 int i; 5735 5736 MPASS(sctx->isc_tx_maxsize); 5737 MPASS(sctx->isc_tx_maxsegsize); 5738 5739 MPASS(sctx->isc_rx_maxsize); 5740 MPASS(sctx->isc_rx_nsegments); 5741 MPASS(sctx->isc_rx_maxsegsize); 5742 5743 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5744 for (i = 0; i < sctx->isc_nrxqs; i++) { 5745 MPASS(sctx->isc_nrxd_min[i]); 5746 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5747 MPASS(sctx->isc_nrxd_max[i]); 5748 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5749 MPASS(sctx->isc_nrxd_default[i]); 5750 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5751 } 5752 5753 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5754 for (i = 0; i < sctx->isc_ntxqs; i++) { 5755 MPASS(sctx->isc_ntxd_min[i]); 5756 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5757 MPASS(sctx->isc_ntxd_max[i]); 5758 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5759 MPASS(sctx->isc_ntxd_default[i]); 5760 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5761 } 5762 } 5763 5764 static void 5765 _iflib_pre_assert(if_softc_ctx_t scctx) 5766 { 5767 5768 MPASS(scctx->isc_txrx->ift_txd_encap); 5769 MPASS(scctx->isc_txrx->ift_txd_flush); 5770 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5771 MPASS(scctx->isc_txrx->ift_rxd_available); 5772 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5773 MPASS(scctx->isc_txrx->ift_rxd_refill); 5774 MPASS(scctx->isc_txrx->ift_rxd_flush); 5775 } 5776 5777 static int 5778 iflib_register(if_ctx_t ctx) 5779 { 5780 if_shared_ctx_t sctx = ctx->ifc_sctx; 5781 driver_t *driver = sctx->isc_driver; 5782 device_t dev = ctx->ifc_dev; 5783 if_t ifp; 5784 u_char type; 5785 int iflags; 5786 5787 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0) 5788 _iflib_assert(sctx); 5789 5790 CTX_LOCK_INIT(ctx); 5791 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5792 if (sctx->isc_flags & IFLIB_PSEUDO) { 5793 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) 5794 type = IFT_ETHER; 5795 else 5796 type = IFT_PPP; 5797 } else 5798 type = IFT_ETHER; 5799 ifp = ctx->ifc_ifp = if_alloc(type); 5800 if (ifp == NULL) { 5801 device_printf(dev, "can not allocate ifnet structure\n"); 5802 return (ENOMEM); 5803 } 5804 5805 /* 5806 * Initialize our context's device specific methods 5807 */ 5808 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5809 kobj_class_compile((kobj_class_t) driver); 5810 5811 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5812 if_setsoftc(ifp, ctx); 5813 if_setdev(ifp, dev); 5814 if_setinitfn(ifp, iflib_if_init); 5815 if_setioctlfn(ifp, iflib_if_ioctl); 5816 #ifdef ALTQ 5817 if_setstartfn(ifp, iflib_altq_if_start); 5818 if_settransmitfn(ifp, iflib_altq_if_transmit); 5819 if_setsendqready(ifp); 5820 #else 5821 if_settransmitfn(ifp, iflib_if_transmit); 5822 #endif 5823 if_setqflushfn(ifp, iflib_if_qflush); 5824 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH; 5825 5826 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5827 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) 5828 iflags |= IFF_POINTOPOINT; 5829 else 5830 iflags |= IFF_BROADCAST | IFF_SIMPLEX; 5831 if_setflags(ifp, iflags); 5832 ctx->ifc_vlan_attach_event = 5833 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5834 EVENTHANDLER_PRI_FIRST); 5835 ctx->ifc_vlan_detach_event = 5836 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5837 EVENTHANDLER_PRI_FIRST); 5838 5839 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5840 ctx->ifc_mediap = &ctx->ifc_media; 5841 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5842 iflib_media_change, iflib_media_status); 5843 } 5844 return (0); 5845 } 5846 5847 static void 5848 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5849 { 5850 /* Unregister VLAN events */ 5851 if (ctx->ifc_vlan_attach_event != NULL) { 5852 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5853 ctx->ifc_vlan_attach_event = NULL; 5854 } 5855 if (ctx->ifc_vlan_detach_event != NULL) { 5856 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5857 ctx->ifc_vlan_detach_event = NULL; 5858 } 5859 5860 } 5861 5862 static void 5863 iflib_deregister(if_ctx_t ctx) 5864 { 5865 if_t ifp = ctx->ifc_ifp; 5866 5867 /* Remove all media */ 5868 ifmedia_removeall(&ctx->ifc_media); 5869 5870 /* Ensure that VLAN event handlers are unregistered */ 5871 iflib_unregister_vlan_handlers(ctx); 5872 5873 /* Release kobject reference */ 5874 kobj_delete((kobj_t) ctx, NULL); 5875 5876 /* Free the ifnet structure */ 5877 if_free(ifp); 5878 5879 STATE_LOCK_DESTROY(ctx); 5880 5881 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5882 CTX_LOCK_DESTROY(ctx); 5883 } 5884 5885 static int 5886 iflib_queues_alloc(if_ctx_t ctx) 5887 { 5888 if_shared_ctx_t sctx = ctx->ifc_sctx; 5889 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5890 device_t dev = ctx->ifc_dev; 5891 int nrxqsets = scctx->isc_nrxqsets; 5892 int ntxqsets = scctx->isc_ntxqsets; 5893 iflib_txq_t txq; 5894 iflib_rxq_t rxq; 5895 iflib_fl_t fl = NULL; 5896 int i, j, cpu, err, txconf, rxconf; 5897 iflib_dma_info_t ifdip; 5898 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5899 uint32_t *txqsizes = scctx->isc_txqsizes; 5900 uint8_t nrxqs = sctx->isc_nrxqs; 5901 uint8_t ntxqs = sctx->isc_ntxqs; 5902 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5903 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0); 5904 caddr_t *vaddrs; 5905 uint64_t *paddrs; 5906 5907 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5908 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5909 KASSERT(nrxqs >= fl_offset + nfree_lists, 5910 ("there must be at least a rxq for each free list")); 5911 5912 /* Allocate the TX ring struct memory */ 5913 if (!(ctx->ifc_txqs = 5914 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5915 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5916 device_printf(dev, "Unable to allocate TX ring memory\n"); 5917 err = ENOMEM; 5918 goto fail; 5919 } 5920 5921 /* Now allocate the RX */ 5922 if (!(ctx->ifc_rxqs = 5923 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5924 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5925 device_printf(dev, "Unable to allocate RX ring memory\n"); 5926 err = ENOMEM; 5927 goto rx_fail; 5928 } 5929 5930 txq = ctx->ifc_txqs; 5931 rxq = ctx->ifc_rxqs; 5932 5933 /* 5934 * XXX handle allocation failure 5935 */ 5936 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5937 /* Set up some basics */ 5938 5939 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5940 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5941 device_printf(dev, 5942 "Unable to allocate TX DMA info memory\n"); 5943 err = ENOMEM; 5944 goto err_tx_desc; 5945 } 5946 txq->ift_ifdi = ifdip; 5947 for (j = 0; j < ntxqs; j++, ifdip++) { 5948 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5949 device_printf(dev, 5950 "Unable to allocate TX descriptors\n"); 5951 err = ENOMEM; 5952 goto err_tx_desc; 5953 } 5954 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5955 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5956 } 5957 txq->ift_ctx = ctx; 5958 txq->ift_id = i; 5959 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5960 txq->ift_br_offset = 1; 5961 } else { 5962 txq->ift_br_offset = 0; 5963 } 5964 5965 if (iflib_txsd_alloc(txq)) { 5966 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5967 err = ENOMEM; 5968 goto err_tx_desc; 5969 } 5970 5971 /* Initialize the TX lock */ 5972 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5973 device_get_nameunit(dev), txq->ift_id); 5974 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5975 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5976 txq->ift_timer.c_cpu = cpu; 5977 #ifdef DEV_NETMAP 5978 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 5979 txq->ift_netmap_timer.c_cpu = cpu; 5980 #endif /* DEV_NETMAP */ 5981 5982 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5983 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5984 if (err) { 5985 /* XXX free any allocated rings */ 5986 device_printf(dev, "Unable to allocate buf_ring\n"); 5987 goto err_tx_desc; 5988 } 5989 } 5990 5991 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5992 /* Set up some basics */ 5993 callout_init(&rxq->ifr_watchdog, 1); 5994 5995 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5996 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5997 device_printf(dev, 5998 "Unable to allocate RX DMA info memory\n"); 5999 err = ENOMEM; 6000 goto err_tx_desc; 6001 } 6002 6003 rxq->ifr_ifdi = ifdip; 6004 /* XXX this needs to be changed if #rx queues != #tx queues */ 6005 rxq->ifr_ntxqirq = 1; 6006 rxq->ifr_txqid[0] = i; 6007 for (j = 0; j < nrxqs; j++, ifdip++) { 6008 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 6009 device_printf(dev, 6010 "Unable to allocate RX descriptors\n"); 6011 err = ENOMEM; 6012 goto err_tx_desc; 6013 } 6014 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 6015 } 6016 rxq->ifr_ctx = ctx; 6017 rxq->ifr_id = i; 6018 rxq->ifr_fl_offset = fl_offset; 6019 rxq->ifr_nfl = nfree_lists; 6020 if (!(fl = 6021 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 6022 device_printf(dev, "Unable to allocate free list memory\n"); 6023 err = ENOMEM; 6024 goto err_tx_desc; 6025 } 6026 rxq->ifr_fl = fl; 6027 for (j = 0; j < nfree_lists; j++) { 6028 fl[j].ifl_rxq = rxq; 6029 fl[j].ifl_id = j; 6030 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 6031 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 6032 } 6033 /* Allocate receive buffers for the ring */ 6034 if (iflib_rxsd_alloc(rxq)) { 6035 device_printf(dev, 6036 "Critical Failure setting up receive buffers\n"); 6037 err = ENOMEM; 6038 goto err_rx_desc; 6039 } 6040 6041 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 6042 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 6043 M_WAITOK); 6044 } 6045 6046 /* TXQs */ 6047 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 6048 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 6049 for (i = 0; i < ntxqsets; i++) { 6050 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 6051 6052 for (j = 0; j < ntxqs; j++, di++) { 6053 vaddrs[i*ntxqs + j] = di->idi_vaddr; 6054 paddrs[i*ntxqs + j] = di->idi_paddr; 6055 } 6056 } 6057 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 6058 device_printf(ctx->ifc_dev, 6059 "Unable to allocate device TX queue\n"); 6060 iflib_tx_structures_free(ctx); 6061 free(vaddrs, M_IFLIB); 6062 free(paddrs, M_IFLIB); 6063 goto err_rx_desc; 6064 } 6065 free(vaddrs, M_IFLIB); 6066 free(paddrs, M_IFLIB); 6067 6068 /* RXQs */ 6069 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6070 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6071 for (i = 0; i < nrxqsets; i++) { 6072 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 6073 6074 for (j = 0; j < nrxqs; j++, di++) { 6075 vaddrs[i*nrxqs + j] = di->idi_vaddr; 6076 paddrs[i*nrxqs + j] = di->idi_paddr; 6077 } 6078 } 6079 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 6080 device_printf(ctx->ifc_dev, 6081 "Unable to allocate device RX queue\n"); 6082 iflib_tx_structures_free(ctx); 6083 free(vaddrs, M_IFLIB); 6084 free(paddrs, M_IFLIB); 6085 goto err_rx_desc; 6086 } 6087 free(vaddrs, M_IFLIB); 6088 free(paddrs, M_IFLIB); 6089 6090 return (0); 6091 6092 /* XXX handle allocation failure changes */ 6093 err_rx_desc: 6094 err_tx_desc: 6095 rx_fail: 6096 if (ctx->ifc_rxqs != NULL) 6097 free(ctx->ifc_rxqs, M_IFLIB); 6098 ctx->ifc_rxqs = NULL; 6099 if (ctx->ifc_txqs != NULL) 6100 free(ctx->ifc_txqs, M_IFLIB); 6101 ctx->ifc_txqs = NULL; 6102 fail: 6103 return (err); 6104 } 6105 6106 static int 6107 iflib_tx_structures_setup(if_ctx_t ctx) 6108 { 6109 iflib_txq_t txq = ctx->ifc_txqs; 6110 int i; 6111 6112 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 6113 iflib_txq_setup(txq); 6114 6115 return (0); 6116 } 6117 6118 static void 6119 iflib_tx_structures_free(if_ctx_t ctx) 6120 { 6121 iflib_txq_t txq = ctx->ifc_txqs; 6122 if_shared_ctx_t sctx = ctx->ifc_sctx; 6123 int i, j; 6124 6125 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6126 for (j = 0; j < sctx->isc_ntxqs; j++) 6127 iflib_dma_free(&txq->ift_ifdi[j]); 6128 iflib_txq_destroy(txq); 6129 } 6130 free(ctx->ifc_txqs, M_IFLIB); 6131 ctx->ifc_txqs = NULL; 6132 } 6133 6134 /********************************************************************* 6135 * 6136 * Initialize all receive rings. 6137 * 6138 **********************************************************************/ 6139 static int 6140 iflib_rx_structures_setup(if_ctx_t ctx) 6141 { 6142 iflib_rxq_t rxq = ctx->ifc_rxqs; 6143 int q; 6144 #if defined(INET6) || defined(INET) 6145 int err, i; 6146 #endif 6147 6148 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 6149 #if defined(INET6) || defined(INET) 6150 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 6151 TCP_LRO_ENTRIES, min(1024, 6152 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 6153 if (err != 0) { 6154 device_printf(ctx->ifc_dev, 6155 "LRO Initialization failed!\n"); 6156 goto fail; 6157 } 6158 #endif 6159 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 6160 } 6161 return (0); 6162 #if defined(INET6) || defined(INET) 6163 fail: 6164 /* 6165 * Free LRO resources allocated so far, we will only handle 6166 * the rings that completed, the failing case will have 6167 * cleaned up for itself. 'q' failed, so its the terminus. 6168 */ 6169 rxq = ctx->ifc_rxqs; 6170 for (i = 0; i < q; ++i, rxq++) { 6171 tcp_lro_free(&rxq->ifr_lc); 6172 } 6173 return (err); 6174 #endif 6175 } 6176 6177 /********************************************************************* 6178 * 6179 * Free all receive rings. 6180 * 6181 **********************************************************************/ 6182 static void 6183 iflib_rx_structures_free(if_ctx_t ctx) 6184 { 6185 iflib_rxq_t rxq = ctx->ifc_rxqs; 6186 if_shared_ctx_t sctx = ctx->ifc_sctx; 6187 int i, j; 6188 6189 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 6190 for (j = 0; j < sctx->isc_nrxqs; j++) 6191 iflib_dma_free(&rxq->ifr_ifdi[j]); 6192 iflib_rx_sds_free(rxq); 6193 #if defined(INET6) || defined(INET) 6194 tcp_lro_free(&rxq->ifr_lc); 6195 #endif 6196 } 6197 free(ctx->ifc_rxqs, M_IFLIB); 6198 ctx->ifc_rxqs = NULL; 6199 } 6200 6201 static int 6202 iflib_qset_structures_setup(if_ctx_t ctx) 6203 { 6204 int err; 6205 6206 /* 6207 * It is expected that the caller takes care of freeing queues if this 6208 * fails. 6209 */ 6210 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 6211 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 6212 return (err); 6213 } 6214 6215 if ((err = iflib_rx_structures_setup(ctx)) != 0) 6216 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 6217 6218 return (err); 6219 } 6220 6221 int 6222 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 6223 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 6224 { 6225 6226 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 6227 } 6228 6229 /* Just to avoid copy/paste */ 6230 static inline int 6231 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6232 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 6233 const char *name) 6234 { 6235 device_t dev; 6236 unsigned int base_cpuid, cpuid; 6237 int err; 6238 6239 dev = ctx->ifc_dev; 6240 base_cpuid = ctx->ifc_sysctl_core_offset; 6241 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX); 6242 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, 6243 irq ? irq->ii_res : NULL, name); 6244 if (err) { 6245 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6246 return (err); 6247 } 6248 #ifdef notyet 6249 if (cpuid > ctx->ifc_cpuid_highest) 6250 ctx->ifc_cpuid_highest = cpuid; 6251 #endif 6252 return (0); 6253 } 6254 6255 int 6256 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6257 iflib_intr_type_t type, driver_filter_t *filter, 6258 void *filter_arg, int qid, const char *name) 6259 { 6260 device_t dev; 6261 struct grouptask *gtask; 6262 struct taskqgroup *tqg; 6263 iflib_filter_info_t info; 6264 gtask_fn_t *fn; 6265 int tqrid, err; 6266 driver_filter_t *intr_fast; 6267 void *q; 6268 6269 info = &ctx->ifc_filter_info; 6270 tqrid = rid; 6271 6272 switch (type) { 6273 /* XXX merge tx/rx for netmap? */ 6274 case IFLIB_INTR_TX: 6275 q = &ctx->ifc_txqs[qid]; 6276 info = &ctx->ifc_txqs[qid].ift_filter_info; 6277 gtask = &ctx->ifc_txqs[qid].ift_task; 6278 tqg = qgroup_if_io_tqg; 6279 fn = _task_fn_tx; 6280 intr_fast = iflib_fast_intr; 6281 GROUPTASK_INIT(gtask, 0, fn, q); 6282 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6283 break; 6284 case IFLIB_INTR_RX: 6285 q = &ctx->ifc_rxqs[qid]; 6286 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6287 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6288 tqg = qgroup_if_io_tqg; 6289 fn = _task_fn_rx; 6290 intr_fast = iflib_fast_intr; 6291 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6292 break; 6293 case IFLIB_INTR_RXTX: 6294 q = &ctx->ifc_rxqs[qid]; 6295 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6296 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6297 tqg = qgroup_if_io_tqg; 6298 fn = _task_fn_rx; 6299 intr_fast = iflib_fast_intr_rxtx; 6300 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6301 break; 6302 case IFLIB_INTR_ADMIN: 6303 q = ctx; 6304 tqrid = -1; 6305 info = &ctx->ifc_filter_info; 6306 gtask = &ctx->ifc_admin_task; 6307 tqg = qgroup_if_config_tqg; 6308 fn = _task_fn_admin; 6309 intr_fast = iflib_fast_intr_ctx; 6310 break; 6311 default: 6312 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6313 __func__); 6314 return (EINVAL); 6315 } 6316 6317 info->ifi_filter = filter; 6318 info->ifi_filter_arg = filter_arg; 6319 info->ifi_task = gtask; 6320 info->ifi_ctx = q; 6321 6322 dev = ctx->ifc_dev; 6323 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6324 if (err != 0) { 6325 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6326 return (err); 6327 } 6328 if (type == IFLIB_INTR_ADMIN) 6329 return (0); 6330 6331 if (tqrid != -1) { 6332 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6333 name); 6334 if (err) 6335 return (err); 6336 } else { 6337 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6338 } 6339 6340 return (0); 6341 } 6342 6343 void 6344 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6345 { 6346 device_t dev; 6347 struct grouptask *gtask; 6348 struct taskqgroup *tqg; 6349 gtask_fn_t *fn; 6350 void *q; 6351 int err; 6352 6353 switch (type) { 6354 case IFLIB_INTR_TX: 6355 q = &ctx->ifc_txqs[qid]; 6356 gtask = &ctx->ifc_txqs[qid].ift_task; 6357 tqg = qgroup_if_io_tqg; 6358 fn = _task_fn_tx; 6359 GROUPTASK_INIT(gtask, 0, fn, q); 6360 break; 6361 case IFLIB_INTR_RX: 6362 q = &ctx->ifc_rxqs[qid]; 6363 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6364 tqg = qgroup_if_io_tqg; 6365 fn = _task_fn_rx; 6366 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6367 break; 6368 case IFLIB_INTR_IOV: 6369 q = ctx; 6370 gtask = &ctx->ifc_vflr_task; 6371 tqg = qgroup_if_config_tqg; 6372 fn = _task_fn_iov; 6373 GROUPTASK_INIT(gtask, 0, fn, q); 6374 break; 6375 default: 6376 panic("unknown net intr type"); 6377 } 6378 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name); 6379 if (err) { 6380 dev = ctx->ifc_dev; 6381 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL, 6382 name); 6383 } 6384 } 6385 6386 void 6387 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6388 { 6389 6390 if (irq->ii_tag) 6391 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6392 6393 if (irq->ii_res) 6394 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6395 rman_get_rid(irq->ii_res), irq->ii_res); 6396 } 6397 6398 static int 6399 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6400 { 6401 iflib_txq_t txq = ctx->ifc_txqs; 6402 iflib_rxq_t rxq = ctx->ifc_rxqs; 6403 if_irq_t irq = &ctx->ifc_legacy_irq; 6404 iflib_filter_info_t info; 6405 device_t dev; 6406 struct grouptask *gtask; 6407 struct resource *res; 6408 struct taskqgroup *tqg; 6409 void *q; 6410 int err, tqrid; 6411 bool rx_only; 6412 6413 q = &ctx->ifc_rxqs[0]; 6414 info = &rxq[0].ifr_filter_info; 6415 gtask = &rxq[0].ifr_task; 6416 tqg = qgroup_if_io_tqg; 6417 tqrid = *rid; 6418 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6419 6420 ctx->ifc_flags |= IFC_LEGACY; 6421 info->ifi_filter = filter; 6422 info->ifi_filter_arg = filter_arg; 6423 info->ifi_task = gtask; 6424 info->ifi_ctx = rx_only ? ctx : q; 6425 6426 dev = ctx->ifc_dev; 6427 /* We allocate a single interrupt resource */ 6428 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6429 iflib_fast_intr_rxtx, NULL, info, name); 6430 if (err != 0) 6431 return (err); 6432 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6433 res = irq->ii_res; 6434 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6435 6436 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6437 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6438 "tx"); 6439 return (0); 6440 } 6441 6442 void 6443 iflib_led_create(if_ctx_t ctx) 6444 { 6445 6446 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6447 device_get_nameunit(ctx->ifc_dev)); 6448 } 6449 6450 void 6451 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6452 { 6453 6454 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6455 } 6456 6457 void 6458 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6459 { 6460 6461 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6462 } 6463 6464 void 6465 iflib_admin_intr_deferred(if_ctx_t ctx) 6466 { 6467 6468 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6469 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6470 } 6471 6472 void 6473 iflib_iov_intr_deferred(if_ctx_t ctx) 6474 { 6475 6476 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6477 } 6478 6479 void 6480 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6481 { 6482 6483 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6484 name); 6485 } 6486 6487 void 6488 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6489 const char *name) 6490 { 6491 6492 GROUPTASK_INIT(gtask, 0, fn, ctx); 6493 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6494 name); 6495 } 6496 6497 void 6498 iflib_config_gtask_deinit(struct grouptask *gtask) 6499 { 6500 6501 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6502 } 6503 6504 void 6505 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6506 { 6507 if_t ifp = ctx->ifc_ifp; 6508 iflib_txq_t txq = ctx->ifc_txqs; 6509 6510 if_setbaudrate(ifp, baudrate); 6511 if (baudrate >= IF_Gbps(10)) { 6512 STATE_LOCK(ctx); 6513 ctx->ifc_flags |= IFC_PREFETCH; 6514 STATE_UNLOCK(ctx); 6515 } 6516 /* If link down, disable watchdog */ 6517 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6518 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6519 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6520 } 6521 ctx->ifc_link_state = link_state; 6522 if_link_state_change(ifp, link_state); 6523 } 6524 6525 static int 6526 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6527 { 6528 int credits; 6529 #ifdef INVARIANTS 6530 int credits_pre = txq->ift_cidx_processed; 6531 #endif 6532 6533 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6534 BUS_DMASYNC_POSTREAD); 6535 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6536 return (0); 6537 6538 txq->ift_processed += credits; 6539 txq->ift_cidx_processed += credits; 6540 6541 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6542 if (txq->ift_cidx_processed >= txq->ift_size) 6543 txq->ift_cidx_processed -= txq->ift_size; 6544 return (credits); 6545 } 6546 6547 static int 6548 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6549 { 6550 iflib_fl_t fl; 6551 u_int i; 6552 6553 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6554 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6555 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6556 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6557 budget)); 6558 } 6559 6560 void 6561 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6562 const char *description, if_int_delay_info_t info, 6563 int offset, int value) 6564 { 6565 info->iidi_ctx = ctx; 6566 info->iidi_offset = offset; 6567 info->iidi_value = value; 6568 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6569 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6570 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6571 info, 0, iflib_sysctl_int_delay, "I", description); 6572 } 6573 6574 struct sx * 6575 iflib_ctx_lock_get(if_ctx_t ctx) 6576 { 6577 6578 return (&ctx->ifc_ctx_sx); 6579 } 6580 6581 static int 6582 iflib_msix_init(if_ctx_t ctx) 6583 { 6584 device_t dev = ctx->ifc_dev; 6585 if_shared_ctx_t sctx = ctx->ifc_sctx; 6586 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6587 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6588 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6589 6590 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6591 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6592 6593 if (bootverbose) 6594 device_printf(dev, "msix_init qsets capped at %d\n", 6595 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6596 6597 /* Override by tuneable */ 6598 if (scctx->isc_disable_msix) 6599 goto msi; 6600 6601 /* First try MSI-X */ 6602 if ((msgs = pci_msix_count(dev)) == 0) { 6603 if (bootverbose) 6604 device_printf(dev, "MSI-X not supported or disabled\n"); 6605 goto msi; 6606 } 6607 6608 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6609 /* 6610 * bar == -1 => "trust me I know what I'm doing" 6611 * Some drivers are for hardware that is so shoddily 6612 * documented that no one knows which bars are which 6613 * so the developer has to map all bars. This hack 6614 * allows shoddy garbage to use MSI-X in this framework. 6615 */ 6616 if (bar != -1) { 6617 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6618 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6619 if (ctx->ifc_msix_mem == NULL) { 6620 device_printf(dev, "Unable to map MSI-X table\n"); 6621 goto msi; 6622 } 6623 } 6624 6625 admincnt = sctx->isc_admin_intrcnt; 6626 #if IFLIB_DEBUG 6627 /* use only 1 qset in debug mode */ 6628 queuemsgs = min(msgs - admincnt, 1); 6629 #else 6630 queuemsgs = msgs - admincnt; 6631 #endif 6632 #ifdef RSS 6633 queues = imin(queuemsgs, rss_getnumbuckets()); 6634 #else 6635 queues = queuemsgs; 6636 #endif 6637 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6638 if (bootverbose) 6639 device_printf(dev, 6640 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6641 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6642 #ifdef RSS 6643 /* If we're doing RSS, clamp at the number of RSS buckets */ 6644 if (queues > rss_getnumbuckets()) 6645 queues = rss_getnumbuckets(); 6646 #endif 6647 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6648 rx_queues = iflib_num_rx_queues; 6649 else 6650 rx_queues = queues; 6651 6652 if (rx_queues > scctx->isc_nrxqsets) 6653 rx_queues = scctx->isc_nrxqsets; 6654 6655 /* 6656 * We want this to be all logical CPUs by default 6657 */ 6658 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6659 tx_queues = iflib_num_tx_queues; 6660 else 6661 tx_queues = mp_ncpus; 6662 6663 if (tx_queues > scctx->isc_ntxqsets) 6664 tx_queues = scctx->isc_ntxqsets; 6665 6666 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6667 #ifdef INVARIANTS 6668 if (tx_queues != rx_queues) 6669 device_printf(dev, 6670 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6671 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6672 #endif 6673 tx_queues = min(rx_queues, tx_queues); 6674 rx_queues = min(rx_queues, tx_queues); 6675 } 6676 6677 vectors = rx_queues + admincnt; 6678 if (msgs < vectors) { 6679 device_printf(dev, 6680 "insufficient number of MSI-X vectors " 6681 "(supported %d, need %d)\n", msgs, vectors); 6682 goto msi; 6683 } 6684 6685 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6686 tx_queues); 6687 msgs = vectors; 6688 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6689 if (vectors != msgs) { 6690 device_printf(dev, 6691 "Unable to allocate sufficient MSI-X vectors " 6692 "(got %d, need %d)\n", vectors, msgs); 6693 pci_release_msi(dev); 6694 if (bar != -1) { 6695 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6696 ctx->ifc_msix_mem); 6697 ctx->ifc_msix_mem = NULL; 6698 } 6699 goto msi; 6700 } 6701 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6702 vectors); 6703 scctx->isc_vectors = vectors; 6704 scctx->isc_nrxqsets = rx_queues; 6705 scctx->isc_ntxqsets = tx_queues; 6706 scctx->isc_intr = IFLIB_INTR_MSIX; 6707 6708 return (vectors); 6709 } else { 6710 device_printf(dev, 6711 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6712 err); 6713 if (bar != -1) { 6714 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6715 ctx->ifc_msix_mem); 6716 ctx->ifc_msix_mem = NULL; 6717 } 6718 } 6719 6720 msi: 6721 vectors = pci_msi_count(dev); 6722 scctx->isc_nrxqsets = 1; 6723 scctx->isc_ntxqsets = 1; 6724 scctx->isc_vectors = vectors; 6725 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6726 device_printf(dev,"Using an MSI interrupt\n"); 6727 scctx->isc_intr = IFLIB_INTR_MSI; 6728 } else { 6729 scctx->isc_vectors = 1; 6730 device_printf(dev,"Using a Legacy interrupt\n"); 6731 scctx->isc_intr = IFLIB_INTR_LEGACY; 6732 } 6733 6734 return (vectors); 6735 } 6736 6737 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6738 6739 static int 6740 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6741 { 6742 int rc; 6743 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6744 struct sbuf *sb; 6745 const char *ring_state = "UNKNOWN"; 6746 6747 /* XXX needed ? */ 6748 rc = sysctl_wire_old_buffer(req, 0); 6749 MPASS(rc == 0); 6750 if (rc != 0) 6751 return (rc); 6752 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6753 MPASS(sb != NULL); 6754 if (sb == NULL) 6755 return (ENOMEM); 6756 if (state[3] <= 3) 6757 ring_state = ring_states[state[3]]; 6758 6759 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6760 state[0], state[1], state[2], ring_state); 6761 rc = sbuf_finish(sb); 6762 sbuf_delete(sb); 6763 return(rc); 6764 } 6765 6766 enum iflib_ndesc_handler { 6767 IFLIB_NTXD_HANDLER, 6768 IFLIB_NRXD_HANDLER, 6769 }; 6770 6771 static int 6772 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6773 { 6774 if_ctx_t ctx = (void *)arg1; 6775 enum iflib_ndesc_handler type = arg2; 6776 char buf[256] = {0}; 6777 qidx_t *ndesc; 6778 char *p, *next; 6779 int nqs, rc, i; 6780 6781 nqs = 8; 6782 switch(type) { 6783 case IFLIB_NTXD_HANDLER: 6784 ndesc = ctx->ifc_sysctl_ntxds; 6785 if (ctx->ifc_sctx) 6786 nqs = ctx->ifc_sctx->isc_ntxqs; 6787 break; 6788 case IFLIB_NRXD_HANDLER: 6789 ndesc = ctx->ifc_sysctl_nrxds; 6790 if (ctx->ifc_sctx) 6791 nqs = ctx->ifc_sctx->isc_nrxqs; 6792 break; 6793 default: 6794 printf("%s: unhandled type\n", __func__); 6795 return (EINVAL); 6796 } 6797 if (nqs == 0) 6798 nqs = 8; 6799 6800 for (i=0; i<8; i++) { 6801 if (i >= nqs) 6802 break; 6803 if (i) 6804 strcat(buf, ","); 6805 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6806 } 6807 6808 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6809 if (rc || req->newptr == NULL) 6810 return rc; 6811 6812 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6813 i++, p = strsep(&next, " ,")) { 6814 ndesc[i] = strtoul(p, NULL, 10); 6815 } 6816 6817 return(rc); 6818 } 6819 6820 #define NAME_BUFLEN 32 6821 static void 6822 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6823 { 6824 device_t dev = iflib_get_dev(ctx); 6825 struct sysctl_oid_list *child, *oid_list; 6826 struct sysctl_ctx_list *ctx_list; 6827 struct sysctl_oid *node; 6828 6829 ctx_list = device_get_sysctl_ctx(dev); 6830 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6831 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6832 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 6833 oid_list = SYSCTL_CHILDREN(node); 6834 6835 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6836 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6837 "driver version"); 6838 6839 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6840 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6841 "# of txqs to use, 0 => use default #"); 6842 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6843 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6844 "# of rxqs to use, 0 => use default #"); 6845 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6846 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6847 "permit #txq != #rxq"); 6848 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6849 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6850 "disable MSI-X (default 0)"); 6851 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6852 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6853 "set the RX budget"); 6854 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6855 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6856 "cause TX to abdicate instead of running to completion"); 6857 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6858 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6859 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6860 "offset to start using cores at"); 6861 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6862 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6863 "use separate cores for TX and RX"); 6864 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "use_logical_cores", 6865 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0, 6866 "try to make use of logical cores for TX and RX"); 6867 6868 /* XXX change for per-queue sizes */ 6869 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6870 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6871 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6872 "list of # of TX descriptors to use, 0 = use default #"); 6873 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6874 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6875 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6876 "list of # of RX descriptors to use, 0 = use default #"); 6877 } 6878 6879 static void 6880 iflib_add_device_sysctl_post(if_ctx_t ctx) 6881 { 6882 if_shared_ctx_t sctx = ctx->ifc_sctx; 6883 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6884 device_t dev = iflib_get_dev(ctx); 6885 struct sysctl_oid_list *child; 6886 struct sysctl_ctx_list *ctx_list; 6887 iflib_fl_t fl; 6888 iflib_txq_t txq; 6889 iflib_rxq_t rxq; 6890 int i, j; 6891 char namebuf[NAME_BUFLEN]; 6892 char *qfmt; 6893 struct sysctl_oid *queue_node, *fl_node, *node; 6894 struct sysctl_oid_list *queue_list, *fl_list; 6895 ctx_list = device_get_sysctl_ctx(dev); 6896 6897 node = ctx->ifc_sysctl_node; 6898 child = SYSCTL_CHILDREN(node); 6899 6900 if (scctx->isc_ntxqsets > 100) 6901 qfmt = "txq%03d"; 6902 else if (scctx->isc_ntxqsets > 10) 6903 qfmt = "txq%02d"; 6904 else 6905 qfmt = "txq%d"; 6906 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6907 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6908 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6909 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6910 queue_list = SYSCTL_CHILDREN(queue_node); 6911 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 6912 CTLFLAG_RD, 6913 &txq->ift_task.gt_cpu, 0, "cpu this queue is bound to"); 6914 #if MEMORY_LOGGING 6915 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6916 CTLFLAG_RD, 6917 &txq->ift_dequeued, "total mbufs freed"); 6918 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6919 CTLFLAG_RD, 6920 &txq->ift_enqueued, "total mbufs enqueued"); 6921 #endif 6922 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6923 CTLFLAG_RD, 6924 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6925 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6926 CTLFLAG_RD, 6927 &txq->ift_pullups, "# of times m_pullup was called"); 6928 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6929 CTLFLAG_RD, 6930 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6931 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6932 CTLFLAG_RD, 6933 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6934 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6935 CTLFLAG_RD, 6936 &txq->ift_map_failed, "# of times DMA map failed"); 6937 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6938 CTLFLAG_RD, 6939 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6940 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6941 CTLFLAG_RD, 6942 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6943 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6944 CTLFLAG_RD, 6945 &txq->ift_pidx, 1, "Producer Index"); 6946 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6947 CTLFLAG_RD, 6948 &txq->ift_cidx, 1, "Consumer Index"); 6949 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6950 CTLFLAG_RD, 6951 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6952 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6953 CTLFLAG_RD, 6954 &txq->ift_in_use, 1, "descriptors in use"); 6955 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6956 CTLFLAG_RD, 6957 &txq->ift_processed, "descriptors procesed for clean"); 6958 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6959 CTLFLAG_RD, 6960 &txq->ift_cleaned, "total cleaned"); 6961 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6962 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6963 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6964 mp_ring_state_handler, "A", "soft ring state"); 6965 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6966 CTLFLAG_RD, &txq->ift_br->enqueues, 6967 "# of enqueues to the mp_ring for this queue"); 6968 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6969 CTLFLAG_RD, &txq->ift_br->drops, 6970 "# of drops in the mp_ring for this queue"); 6971 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6972 CTLFLAG_RD, &txq->ift_br->starts, 6973 "# of normal consumer starts in the mp_ring for this queue"); 6974 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6975 CTLFLAG_RD, &txq->ift_br->stalls, 6976 "# of consumer stalls in the mp_ring for this queue"); 6977 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6978 CTLFLAG_RD, &txq->ift_br->restarts, 6979 "# of consumer restarts in the mp_ring for this queue"); 6980 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6981 CTLFLAG_RD, &txq->ift_br->abdications, 6982 "# of consumer abdications in the mp_ring for this queue"); 6983 } 6984 6985 if (scctx->isc_nrxqsets > 100) 6986 qfmt = "rxq%03d"; 6987 else if (scctx->isc_nrxqsets > 10) 6988 qfmt = "rxq%02d"; 6989 else 6990 qfmt = "rxq%d"; 6991 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6992 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6993 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6994 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6995 queue_list = SYSCTL_CHILDREN(queue_node); 6996 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 6997 CTLFLAG_RD, 6998 &rxq->ifr_task.gt_cpu, 0, "cpu this queue is bound to"); 6999 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 7000 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 7001 CTLFLAG_RD, 7002 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 7003 } 7004 7005 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 7006 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 7007 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 7008 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 7009 fl_list = SYSCTL_CHILDREN(fl_node); 7010 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 7011 CTLFLAG_RD, 7012 &fl->ifl_pidx, 1, "Producer Index"); 7013 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 7014 CTLFLAG_RD, 7015 &fl->ifl_cidx, 1, "Consumer Index"); 7016 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 7017 CTLFLAG_RD, 7018 &fl->ifl_credits, 1, "credits available"); 7019 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 7020 CTLFLAG_RD, 7021 &fl->ifl_buf_size, 1, "buffer size"); 7022 #if MEMORY_LOGGING 7023 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 7024 CTLFLAG_RD, 7025 &fl->ifl_m_enqueued, "mbufs allocated"); 7026 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 7027 CTLFLAG_RD, 7028 &fl->ifl_m_dequeued, "mbufs freed"); 7029 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 7030 CTLFLAG_RD, 7031 &fl->ifl_cl_enqueued, "clusters allocated"); 7032 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 7033 CTLFLAG_RD, 7034 &fl->ifl_cl_dequeued, "clusters freed"); 7035 #endif 7036 } 7037 } 7038 7039 } 7040 7041 void 7042 iflib_request_reset(if_ctx_t ctx) 7043 { 7044 7045 STATE_LOCK(ctx); 7046 ctx->ifc_flags |= IFC_DO_RESET; 7047 STATE_UNLOCK(ctx); 7048 } 7049 7050 #ifndef __NO_STRICT_ALIGNMENT 7051 static struct mbuf * 7052 iflib_fixup_rx(struct mbuf *m) 7053 { 7054 struct mbuf *n; 7055 7056 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 7057 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 7058 m->m_data += ETHER_HDR_LEN; 7059 n = m; 7060 } else { 7061 MGETHDR(n, M_NOWAIT, MT_DATA); 7062 if (n == NULL) { 7063 m_freem(m); 7064 return (NULL); 7065 } 7066 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 7067 m->m_data += ETHER_HDR_LEN; 7068 m->m_len -= ETHER_HDR_LEN; 7069 n->m_len = ETHER_HDR_LEN; 7070 M_MOVE_PKTHDR(n, m); 7071 n->m_next = m; 7072 } 7073 return (n); 7074 } 7075 #endif 7076 7077 #ifdef DEBUGNET 7078 static void 7079 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 7080 { 7081 if_ctx_t ctx; 7082 7083 ctx = if_getsoftc(ifp); 7084 CTX_LOCK(ctx); 7085 *nrxr = NRXQSETS(ctx); 7086 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 7087 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 7088 CTX_UNLOCK(ctx); 7089 } 7090 7091 static void 7092 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 7093 { 7094 if_ctx_t ctx; 7095 if_softc_ctx_t scctx; 7096 iflib_fl_t fl; 7097 iflib_rxq_t rxq; 7098 int i, j; 7099 7100 ctx = if_getsoftc(ifp); 7101 scctx = &ctx->ifc_softc_ctx; 7102 7103 switch (event) { 7104 case DEBUGNET_START: 7105 for (i = 0; i < scctx->isc_nrxqsets; i++) { 7106 rxq = &ctx->ifc_rxqs[i]; 7107 for (j = 0; j < rxq->ifr_nfl; j++) { 7108 fl = rxq->ifr_fl; 7109 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 7110 } 7111 } 7112 iflib_no_tx_batch = 1; 7113 break; 7114 default: 7115 break; 7116 } 7117 } 7118 7119 static int 7120 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 7121 { 7122 if_ctx_t ctx; 7123 iflib_txq_t txq; 7124 int error; 7125 7126 ctx = if_getsoftc(ifp); 7127 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7128 IFF_DRV_RUNNING) 7129 return (EBUSY); 7130 7131 txq = &ctx->ifc_txqs[0]; 7132 error = iflib_encap(txq, &m); 7133 if (error == 0) 7134 (void)iflib_txd_db_check(txq, true); 7135 return (error); 7136 } 7137 7138 static int 7139 iflib_debugnet_poll(if_t ifp, int count) 7140 { 7141 struct epoch_tracker et; 7142 if_ctx_t ctx; 7143 if_softc_ctx_t scctx; 7144 iflib_txq_t txq; 7145 int i; 7146 7147 ctx = if_getsoftc(ifp); 7148 scctx = &ctx->ifc_softc_ctx; 7149 7150 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7151 IFF_DRV_RUNNING) 7152 return (EBUSY); 7153 7154 txq = &ctx->ifc_txqs[0]; 7155 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 7156 7157 NET_EPOCH_ENTER(et); 7158 for (i = 0; i < scctx->isc_nrxqsets; i++) 7159 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 7160 NET_EPOCH_EXIT(et); 7161 return (0); 7162 } 7163 #endif /* DEBUGNET */ 7164