xref: /freebsd/sys/net/iflib.c (revision d65c432aa693043a241e9061d040c4d2b3e86d96)
1 /*-
2  * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  *  1. Redistributions of source code must retain the above copyright notice,
9  *     this list of conditions and the following disclaimer.
10  *
11  *  2. Neither the name of Matthew Macy nor the names of its
12  *     contributors may be used to endorse or promote products derived from
13  *     this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25  * POSSIBILITY OF SUCH DAMAGE.
26  */
27 
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30 
31 #include "opt_inet.h"
32 #include "opt_inet6.h"
33 #include "opt_acpi.h"
34 #include "opt_sched.h"
35 
36 #include <sys/param.h>
37 #include <sys/types.h>
38 #include <sys/bus.h>
39 #include <sys/eventhandler.h>
40 #include <sys/kernel.h>
41 #include <sys/lock.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
44 #include <sys/kobj.h>
45 #include <sys/rman.h>
46 #include <sys/sbuf.h>
47 #include <sys/smp.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
54 
55 #include <net/if.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
59 #include <net/bpf.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
62 #include <net/debugnet.h>
63 #include <net/pfil.h>
64 #include <net/vnet.h>
65 
66 #include <netinet/in.h>
67 #include <netinet/in_pcb.h>
68 #include <netinet/tcp_lro.h>
69 #include <netinet/in_systm.h>
70 #include <netinet/if_ether.h>
71 #include <netinet/ip.h>
72 #include <netinet/ip6.h>
73 #include <netinet/tcp.h>
74 #include <netinet/ip_var.h>
75 #include <netinet6/ip6_var.h>
76 
77 #include <machine/bus.h>
78 #include <machine/in_cksum.h>
79 
80 #include <vm/vm.h>
81 #include <vm/pmap.h>
82 
83 #include <dev/led/led.h>
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
86 #include <dev/pci/pci_private.h>
87 
88 #include <net/iflib.h>
89 #include <net/iflib_private.h>
90 
91 #include "ifdi_if.h"
92 
93 #ifdef PCI_IOV
94 #include <dev/pci/pci_iov.h>
95 #endif
96 
97 #include <sys/bitstring.h>
98 /*
99  * enable accounting of every mbuf as it comes in to and goes out of
100  * iflib's software descriptor references
101  */
102 #define MEMORY_LOGGING 0
103 /*
104  * Enable mbuf vectors for compressing long mbuf chains
105  */
106 
107 /*
108  * NB:
109  * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110  *   we prefetch needs to be determined by the time spent in m_free vis a vis
111  *   the cost of a prefetch. This will of course vary based on the workload:
112  *      - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
113  *        is quite expensive, thus suggesting very little prefetch.
114  *      - small packet forwarding which is just returning a single mbuf to
115  *        UMA will typically be very fast vis a vis the cost of a memory
116  *        access.
117  */
118 
119 
120 /*
121  * File organization:
122  *  - private structures
123  *  - iflib private utility functions
124  *  - ifnet functions
125  *  - vlan registry and other exported functions
126  *  - iflib public core functions
127  *
128  *
129  */
130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
131 
132 struct iflib_txq;
133 typedef struct iflib_txq *iflib_txq_t;
134 struct iflib_rxq;
135 typedef struct iflib_rxq *iflib_rxq_t;
136 struct iflib_fl;
137 typedef struct iflib_fl *iflib_fl_t;
138 
139 struct iflib_ctx;
140 
141 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
142 static void iflib_timer(void *arg);
143 
144 typedef struct iflib_filter_info {
145 	driver_filter_t *ifi_filter;
146 	void *ifi_filter_arg;
147 	struct grouptask *ifi_task;
148 	void *ifi_ctx;
149 } *iflib_filter_info_t;
150 
151 struct iflib_ctx {
152 	KOBJ_FIELDS;
153 	/*
154 	 * Pointer to hardware driver's softc
155 	 */
156 	void *ifc_softc;
157 	device_t ifc_dev;
158 	if_t ifc_ifp;
159 
160 	cpuset_t ifc_cpus;
161 	if_shared_ctx_t ifc_sctx;
162 	struct if_softc_ctx ifc_softc_ctx;
163 
164 	struct sx ifc_ctx_sx;
165 	struct mtx ifc_state_mtx;
166 
167 	iflib_txq_t ifc_txqs;
168 	iflib_rxq_t ifc_rxqs;
169 	uint32_t ifc_if_flags;
170 	uint32_t ifc_flags;
171 	uint32_t ifc_max_fl_buf_size;
172 	uint32_t ifc_rx_mbuf_sz;
173 
174 	int ifc_link_state;
175 	int ifc_watchdog_events;
176 	struct cdev *ifc_led_dev;
177 	struct resource *ifc_msix_mem;
178 
179 	struct if_irq ifc_legacy_irq;
180 	struct grouptask ifc_admin_task;
181 	struct grouptask ifc_vflr_task;
182 	struct iflib_filter_info ifc_filter_info;
183 	struct ifmedia	ifc_media;
184 	struct ifmedia	*ifc_mediap;
185 
186 	struct sysctl_oid *ifc_sysctl_node;
187 	uint16_t ifc_sysctl_ntxqs;
188 	uint16_t ifc_sysctl_nrxqs;
189 	uint16_t ifc_sysctl_qs_eq_override;
190 	uint16_t ifc_sysctl_rx_budget;
191 	uint16_t ifc_sysctl_tx_abdicate;
192 	uint16_t ifc_sysctl_core_offset;
193 #define	CORE_OFFSET_UNSPECIFIED	0xffff
194 	uint8_t  ifc_sysctl_separate_txrx;
195 
196 	qidx_t ifc_sysctl_ntxds[8];
197 	qidx_t ifc_sysctl_nrxds[8];
198 	struct if_txrx ifc_txrx;
199 #define isc_txd_encap  ifc_txrx.ift_txd_encap
200 #define isc_txd_flush  ifc_txrx.ift_txd_flush
201 #define isc_txd_credits_update  ifc_txrx.ift_txd_credits_update
202 #define isc_rxd_available ifc_txrx.ift_rxd_available
203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
209 	eventhandler_tag ifc_vlan_attach_event;
210 	eventhandler_tag ifc_vlan_detach_event;
211 	struct ether_addr ifc_mac;
212 };
213 
214 void *
215 iflib_get_softc(if_ctx_t ctx)
216 {
217 
218 	return (ctx->ifc_softc);
219 }
220 
221 device_t
222 iflib_get_dev(if_ctx_t ctx)
223 {
224 
225 	return (ctx->ifc_dev);
226 }
227 
228 if_t
229 iflib_get_ifp(if_ctx_t ctx)
230 {
231 
232 	return (ctx->ifc_ifp);
233 }
234 
235 struct ifmedia *
236 iflib_get_media(if_ctx_t ctx)
237 {
238 
239 	return (ctx->ifc_mediap);
240 }
241 
242 uint32_t
243 iflib_get_flags(if_ctx_t ctx)
244 {
245 	return (ctx->ifc_flags);
246 }
247 
248 void
249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
250 {
251 
252 	bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
253 }
254 
255 if_softc_ctx_t
256 iflib_get_softc_ctx(if_ctx_t ctx)
257 {
258 
259 	return (&ctx->ifc_softc_ctx);
260 }
261 
262 if_shared_ctx_t
263 iflib_get_sctx(if_ctx_t ctx)
264 {
265 
266 	return (ctx->ifc_sctx);
267 }
268 
269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
272 
273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
275 
276 typedef struct iflib_sw_rx_desc_array {
277 	bus_dmamap_t	*ifsd_map;         /* bus_dma maps for packet */
278 	struct mbuf	**ifsd_m;           /* pkthdr mbufs */
279 	caddr_t		*ifsd_cl;          /* direct cluster pointer for rx */
280 	bus_addr_t	*ifsd_ba;          /* bus addr of cluster for rx */
281 } iflib_rxsd_array_t;
282 
283 typedef struct iflib_sw_tx_desc_array {
284 	bus_dmamap_t    *ifsd_map;         /* bus_dma maps for packet */
285 	bus_dmamap_t	*ifsd_tso_map;     /* bus_dma maps for TSO packet */
286 	struct mbuf    **ifsd_m;           /* pkthdr mbufs */
287 } if_txsd_vec_t;
288 
289 /* magic number that should be high enough for any hardware */
290 #define IFLIB_MAX_TX_SEGS		128
291 #define IFLIB_RX_COPY_THRESH		128
292 #define IFLIB_MAX_RX_REFRESH		32
293 /* The minimum descriptors per second before we start coalescing */
294 #define IFLIB_MIN_DESC_SEC		16384
295 #define IFLIB_DEFAULT_TX_UPDATE_FREQ	16
296 #define IFLIB_QUEUE_IDLE		0
297 #define IFLIB_QUEUE_HUNG		1
298 #define IFLIB_QUEUE_WORKING		2
299 /* maximum number of txqs that can share an rx interrupt */
300 #define IFLIB_MAX_TX_SHARED_INTR	4
301 
302 /* this should really scale with ring size - this is a fairly arbitrary value */
303 #define TX_BATCH_SIZE			32
304 
305 #define IFLIB_RESTART_BUDGET		8
306 
307 #define CSUM_OFFLOAD		(CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
308 				 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
309 				 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
310 
311 struct iflib_txq {
312 	qidx_t		ift_in_use;
313 	qidx_t		ift_cidx;
314 	qidx_t		ift_cidx_processed;
315 	qidx_t		ift_pidx;
316 	uint8_t		ift_gen;
317 	uint8_t		ift_br_offset;
318 	uint16_t	ift_npending;
319 	uint16_t	ift_db_pending;
320 	uint16_t	ift_rs_pending;
321 	/* implicit pad */
322 	uint8_t		ift_txd_size[8];
323 	uint64_t	ift_processed;
324 	uint64_t	ift_cleaned;
325 	uint64_t	ift_cleaned_prev;
326 #if MEMORY_LOGGING
327 	uint64_t	ift_enqueued;
328 	uint64_t	ift_dequeued;
329 #endif
330 	uint64_t	ift_no_tx_dma_setup;
331 	uint64_t	ift_no_desc_avail;
332 	uint64_t	ift_mbuf_defrag_failed;
333 	uint64_t	ift_mbuf_defrag;
334 	uint64_t	ift_map_failed;
335 	uint64_t	ift_txd_encap_efbig;
336 	uint64_t	ift_pullups;
337 	uint64_t	ift_last_timer_tick;
338 
339 	struct mtx	ift_mtx;
340 	struct mtx	ift_db_mtx;
341 
342 	/* constant values */
343 	if_ctx_t	ift_ctx;
344 	struct ifmp_ring        *ift_br;
345 	struct grouptask	ift_task;
346 	qidx_t		ift_size;
347 	uint16_t	ift_id;
348 	struct callout	ift_timer;
349 
350 	if_txsd_vec_t	ift_sds;
351 	uint8_t		ift_qstatus;
352 	uint8_t		ift_closed;
353 	uint8_t		ift_update_freq;
354 	struct iflib_filter_info ift_filter_info;
355 	bus_dma_tag_t	ift_buf_tag;
356 	bus_dma_tag_t	ift_tso_buf_tag;
357 	iflib_dma_info_t	ift_ifdi;
358 #define MTX_NAME_LEN 16
359 	char                    ift_mtx_name[MTX_NAME_LEN];
360 	bus_dma_segment_t	ift_segs[IFLIB_MAX_TX_SEGS]  __aligned(CACHE_LINE_SIZE);
361 #ifdef IFLIB_DIAGNOSTICS
362 	uint64_t ift_cpu_exec_count[256];
363 #endif
364 } __aligned(CACHE_LINE_SIZE);
365 
366 struct iflib_fl {
367 	qidx_t		ifl_cidx;
368 	qidx_t		ifl_pidx;
369 	qidx_t		ifl_credits;
370 	uint8_t		ifl_gen;
371 	uint8_t		ifl_rxd_size;
372 #if MEMORY_LOGGING
373 	uint64_t	ifl_m_enqueued;
374 	uint64_t	ifl_m_dequeued;
375 	uint64_t	ifl_cl_enqueued;
376 	uint64_t	ifl_cl_dequeued;
377 #endif
378 	/* implicit pad */
379 	bitstr_t 	*ifl_rx_bitmap;
380 	qidx_t		ifl_fragidx;
381 	/* constant */
382 	qidx_t		ifl_size;
383 	uint16_t	ifl_buf_size;
384 	uint16_t	ifl_cltype;
385 	uma_zone_t	ifl_zone;
386 	iflib_rxsd_array_t	ifl_sds;
387 	iflib_rxq_t	ifl_rxq;
388 	uint8_t		ifl_id;
389 	bus_dma_tag_t	ifl_buf_tag;
390 	iflib_dma_info_t	ifl_ifdi;
391 	uint64_t	ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
392 	caddr_t		ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
393 	qidx_t	ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
394 }  __aligned(CACHE_LINE_SIZE);
395 
396 static inline qidx_t
397 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
398 {
399 	qidx_t used;
400 
401 	if (pidx > cidx)
402 		used = pidx - cidx;
403 	else if (pidx < cidx)
404 		used = size - cidx + pidx;
405 	else if (gen == 0 && pidx == cidx)
406 		used = 0;
407 	else if (gen == 1 && pidx == cidx)
408 		used = size;
409 	else
410 		panic("bad state");
411 
412 	return (used);
413 }
414 
415 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
416 
417 #define IDXDIFF(head, tail, wrap) \
418 	((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
419 
420 struct iflib_rxq {
421 	if_ctx_t	ifr_ctx;
422 	iflib_fl_t	ifr_fl;
423 	uint64_t	ifr_rx_irq;
424 	struct pfil_head	*pfil;
425 	/*
426 	 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
427 	 * the command queue consumer index.  Otherwise it's unused.
428 	 */
429 	qidx_t		ifr_cq_cidx;
430 	uint16_t	ifr_id;
431 	uint8_t		ifr_nfl;
432 	uint8_t		ifr_ntxqirq;
433 	uint8_t		ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
434 	uint8_t		ifr_fl_offset;
435 	struct lro_ctrl			ifr_lc;
436 	struct grouptask        ifr_task;
437 	struct iflib_filter_info ifr_filter_info;
438 	iflib_dma_info_t		ifr_ifdi;
439 
440 	/* dynamically allocate if any drivers need a value substantially larger than this */
441 	struct if_rxd_frag	ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
442 #ifdef IFLIB_DIAGNOSTICS
443 	uint64_t ifr_cpu_exec_count[256];
444 #endif
445 }  __aligned(CACHE_LINE_SIZE);
446 
447 typedef struct if_rxsd {
448 	caddr_t *ifsd_cl;
449 	iflib_fl_t ifsd_fl;
450 	qidx_t ifsd_cidx;
451 } *if_rxsd_t;
452 
453 /* multiple of word size */
454 #ifdef __LP64__
455 #define PKT_INFO_SIZE	6
456 #define RXD_INFO_SIZE	5
457 #define PKT_TYPE uint64_t
458 #else
459 #define PKT_INFO_SIZE	11
460 #define RXD_INFO_SIZE	8
461 #define PKT_TYPE uint32_t
462 #endif
463 #define PKT_LOOP_BOUND  ((PKT_INFO_SIZE/3)*3)
464 #define RXD_LOOP_BOUND  ((RXD_INFO_SIZE/4)*4)
465 
466 typedef struct if_pkt_info_pad {
467 	PKT_TYPE pkt_val[PKT_INFO_SIZE];
468 } *if_pkt_info_pad_t;
469 typedef struct if_rxd_info_pad {
470 	PKT_TYPE rxd_val[RXD_INFO_SIZE];
471 } *if_rxd_info_pad_t;
472 
473 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
474 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
475 
476 
477 static inline void
478 pkt_info_zero(if_pkt_info_t pi)
479 {
480 	if_pkt_info_pad_t pi_pad;
481 
482 	pi_pad = (if_pkt_info_pad_t)pi;
483 	pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
484 	pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
485 #ifndef __LP64__
486 	pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
487 	pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
488 #endif
489 }
490 
491 static device_method_t iflib_pseudo_methods[] = {
492 	DEVMETHOD(device_attach, noop_attach),
493 	DEVMETHOD(device_detach, iflib_pseudo_detach),
494 	DEVMETHOD_END
495 };
496 
497 driver_t iflib_pseudodriver = {
498 	"iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
499 };
500 
501 static inline void
502 rxd_info_zero(if_rxd_info_t ri)
503 {
504 	if_rxd_info_pad_t ri_pad;
505 	int i;
506 
507 	ri_pad = (if_rxd_info_pad_t)ri;
508 	for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
509 		ri_pad->rxd_val[i] = 0;
510 		ri_pad->rxd_val[i+1] = 0;
511 		ri_pad->rxd_val[i+2] = 0;
512 		ri_pad->rxd_val[i+3] = 0;
513 	}
514 #ifdef __LP64__
515 	ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
516 #endif
517 }
518 
519 /*
520  * Only allow a single packet to take up most 1/nth of the tx ring
521  */
522 #define MAX_SINGLE_PACKET_FRACTION 12
523 #define IF_BAD_DMA (bus_addr_t)-1
524 
525 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
526 
527 #define CTX_LOCK_INIT(_sc)  sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
528 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
529 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
530 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
531 
532 #define STATE_LOCK_INIT(_sc, _name)  mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
533 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
534 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
535 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
536 
537 #define CALLOUT_LOCK(txq)	mtx_lock(&txq->ift_mtx)
538 #define CALLOUT_UNLOCK(txq) 	mtx_unlock(&txq->ift_mtx)
539 
540 void
541 iflib_set_detach(if_ctx_t ctx)
542 {
543 	STATE_LOCK(ctx);
544 	ctx->ifc_flags |= IFC_IN_DETACH;
545 	STATE_UNLOCK(ctx);
546 }
547 
548 /* Our boot-time initialization hook */
549 static int	iflib_module_event_handler(module_t, int, void *);
550 
551 static moduledata_t iflib_moduledata = {
552 	"iflib",
553 	iflib_module_event_handler,
554 	NULL
555 };
556 
557 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
558 MODULE_VERSION(iflib, 1);
559 
560 MODULE_DEPEND(iflib, pci, 1, 1, 1);
561 MODULE_DEPEND(iflib, ether, 1, 1, 1);
562 
563 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
564 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
565 
566 #ifndef IFLIB_DEBUG_COUNTERS
567 #ifdef INVARIANTS
568 #define IFLIB_DEBUG_COUNTERS 1
569 #else
570 #define IFLIB_DEBUG_COUNTERS 0
571 #endif /* !INVARIANTS */
572 #endif
573 
574 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0,
575                    "iflib driver parameters");
576 
577 /*
578  * XXX need to ensure that this can't accidentally cause the head to be moved backwards
579  */
580 static int iflib_min_tx_latency = 0;
581 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
582 		   &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
583 static int iflib_no_tx_batch = 0;
584 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
585 		   &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
586 
587 
588 #if IFLIB_DEBUG_COUNTERS
589 
590 static int iflib_tx_seen;
591 static int iflib_tx_sent;
592 static int iflib_tx_encap;
593 static int iflib_rx_allocs;
594 static int iflib_fl_refills;
595 static int iflib_fl_refills_large;
596 static int iflib_tx_frees;
597 
598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
599 		   &iflib_tx_seen, 0, "# TX mbufs seen");
600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
601 		   &iflib_tx_sent, 0, "# TX mbufs sent");
602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
603 		   &iflib_tx_encap, 0, "# TX mbufs encapped");
604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
605 		   &iflib_tx_frees, 0, "# TX frees");
606 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
607 		   &iflib_rx_allocs, 0, "# RX allocations");
608 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
609 		   &iflib_fl_refills, 0, "# refills");
610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
611 		   &iflib_fl_refills_large, 0, "# large refills");
612 
613 
614 static int iflib_txq_drain_flushing;
615 static int iflib_txq_drain_oactive;
616 static int iflib_txq_drain_notready;
617 
618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
619 		   &iflib_txq_drain_flushing, 0, "# drain flushes");
620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
621 		   &iflib_txq_drain_oactive, 0, "# drain oactives");
622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
623 		   &iflib_txq_drain_notready, 0, "# drain notready");
624 
625 
626 static int iflib_encap_load_mbuf_fail;
627 static int iflib_encap_pad_mbuf_fail;
628 static int iflib_encap_txq_avail_fail;
629 static int iflib_encap_txd_encap_fail;
630 
631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
632 		   &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
634 		   &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
636 		   &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
638 		   &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
639 
640 static int iflib_task_fn_rxs;
641 static int iflib_rx_intr_enables;
642 static int iflib_fast_intrs;
643 static int iflib_rx_unavail;
644 static int iflib_rx_ctx_inactive;
645 static int iflib_rx_if_input;
646 static int iflib_rxd_flush;
647 
648 static int iflib_verbose_debug;
649 
650 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
651 		   &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
652 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
653 		   &iflib_rx_intr_enables, 0, "# RX intr enables");
654 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
655 		   &iflib_fast_intrs, 0, "# fast_intr calls");
656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
657 		   &iflib_rx_unavail, 0, "# times rxeof called with no available data");
658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
659 		   &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
661 		   &iflib_rx_if_input, 0, "# times rxeof called if_input");
662 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
663 	         &iflib_rxd_flush, 0, "# times rxd_flush called");
664 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
665 		   &iflib_verbose_debug, 0, "enable verbose debugging");
666 
667 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
668 static void
669 iflib_debug_reset(void)
670 {
671 	iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
672 		iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
673 		iflib_txq_drain_flushing = iflib_txq_drain_oactive =
674 		iflib_txq_drain_notready =
675 		iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
676 		iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
677 		iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
678 		iflib_rx_unavail =
679 		iflib_rx_ctx_inactive = iflib_rx_if_input =
680 		iflib_rxd_flush = 0;
681 }
682 
683 #else
684 #define DBG_COUNTER_INC(name)
685 static void iflib_debug_reset(void) {}
686 #endif
687 
688 #define IFLIB_DEBUG 0
689 
690 static void iflib_tx_structures_free(if_ctx_t ctx);
691 static void iflib_rx_structures_free(if_ctx_t ctx);
692 static int iflib_queues_alloc(if_ctx_t ctx);
693 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
694 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
695 static int iflib_qset_structures_setup(if_ctx_t ctx);
696 static int iflib_msix_init(if_ctx_t ctx);
697 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
698 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
699 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
700 #ifdef ALTQ
701 static void iflib_altq_if_start(if_t ifp);
702 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
703 #endif
704 static int iflib_register(if_ctx_t);
705 static void iflib_deregister(if_ctx_t);
706 static void iflib_unregister_vlan_handlers(if_ctx_t ctx);
707 static void iflib_init_locked(if_ctx_t ctx);
708 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
709 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
710 static void iflib_ifmp_purge(iflib_txq_t txq);
711 static void _iflib_pre_assert(if_softc_ctx_t scctx);
712 static void iflib_if_init_locked(if_ctx_t ctx);
713 static void iflib_free_intr_mem(if_ctx_t ctx);
714 #ifndef __NO_STRICT_ALIGNMENT
715 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
716 #endif
717 
718 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
719     SLIST_HEAD_INITIALIZER(cpu_offsets);
720 struct cpu_offset {
721 	SLIST_ENTRY(cpu_offset) entries;
722 	cpuset_t	set;
723 	unsigned int	refcount;
724 	uint16_t	offset;
725 };
726 static struct mtx cpu_offset_mtx;
727 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
728     MTX_DEF);
729 
730 DEBUGNET_DEFINE(iflib);
731 
732 #ifdef DEV_NETMAP
733 #include <sys/selinfo.h>
734 #include <net/netmap.h>
735 #include <dev/netmap/netmap_kern.h>
736 
737 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
738 
739 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
740 
741 /*
742  * device-specific sysctl variables:
743  *
744  * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
745  *	During regular operations the CRC is stripped, but on some
746  *	hardware reception of frames not multiple of 64 is slower,
747  *	so using crcstrip=0 helps in benchmarks.
748  *
749  * iflib_rx_miss, iflib_rx_miss_bufs:
750  *	count packets that might be missed due to lost interrupts.
751  */
752 SYSCTL_DECL(_dev_netmap);
753 /*
754  * The xl driver by default strips CRCs and we do not override it.
755  */
756 
757 int iflib_crcstrip = 1;
758 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
759     CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
760 
761 int iflib_rx_miss, iflib_rx_miss_bufs;
762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
763     CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
764 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
765     CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
766 
767 /*
768  * Register/unregister. We are already under netmap lock.
769  * Only called on the first register or the last unregister.
770  */
771 static int
772 iflib_netmap_register(struct netmap_adapter *na, int onoff)
773 {
774 	if_t ifp = na->ifp;
775 	if_ctx_t ctx = ifp->if_softc;
776 	int status;
777 
778 	CTX_LOCK(ctx);
779 	IFDI_INTR_DISABLE(ctx);
780 
781 	/* Tell the stack that the interface is no longer active */
782 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
783 
784 	if (!CTX_IS_VF(ctx))
785 		IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
786 
787 	/* enable or disable flags and callbacks in na and ifp */
788 	if (onoff) {
789 		nm_set_native_flags(na);
790 	} else {
791 		nm_clear_native_flags(na);
792 	}
793 	iflib_stop(ctx);
794 	iflib_init_locked(ctx);
795 	IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
796 	status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
797 	if (status)
798 		nm_clear_native_flags(na);
799 	CTX_UNLOCK(ctx);
800 	return (status);
801 }
802 
803 static int
804 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
805 {
806 	struct netmap_adapter *na = kring->na;
807 	u_int const lim = kring->nkr_num_slots - 1;
808 	u_int head = kring->rhead;
809 	struct netmap_ring *ring = kring->ring;
810 	bus_dmamap_t *map;
811 	struct if_rxd_update iru;
812 	if_ctx_t ctx = rxq->ifr_ctx;
813 	iflib_fl_t fl = &rxq->ifr_fl[0];
814 	uint32_t refill_pidx, nic_i;
815 #if IFLIB_DEBUG_COUNTERS
816 	int rf_count = 0;
817 #endif
818 
819 	if (nm_i == head && __predict_true(!init))
820 		return 0;
821 	iru_init(&iru, rxq, 0 /* flid */);
822 	map = fl->ifl_sds.ifsd_map;
823 	refill_pidx = netmap_idx_k2n(kring, nm_i);
824 	/*
825 	 * IMPORTANT: we must leave one free slot in the ring,
826 	 * so move head back by one unit
827 	 */
828 	head = nm_prev(head, lim);
829 	nic_i = UINT_MAX;
830 	DBG_COUNTER_INC(fl_refills);
831 	while (nm_i != head) {
832 #if IFLIB_DEBUG_COUNTERS
833 		if (++rf_count == 9)
834 			DBG_COUNTER_INC(fl_refills_large);
835 #endif
836 		for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
837 			struct netmap_slot *slot = &ring->slot[nm_i];
838 			void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
839 			uint32_t nic_i_dma = refill_pidx;
840 			nic_i = netmap_idx_k2n(kring, nm_i);
841 
842 			MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
843 
844 			if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
845 			        return netmap_ring_reinit(kring);
846 
847 			fl->ifl_vm_addrs[tmp_pidx] = addr;
848 			if (__predict_false(init)) {
849 				netmap_load_map(na, fl->ifl_buf_tag,
850 				    map[nic_i], addr);
851 			} else if (slot->flags & NS_BUF_CHANGED) {
852 				/* buffer has changed, reload map */
853 				netmap_reload_map(na, fl->ifl_buf_tag,
854 				    map[nic_i], addr);
855 			}
856 			slot->flags &= ~NS_BUF_CHANGED;
857 
858 			nm_i = nm_next(nm_i, lim);
859 			fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
860 			if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
861 				continue;
862 
863 			iru.iru_pidx = refill_pidx;
864 			iru.iru_count = tmp_pidx+1;
865 			ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
866 			refill_pidx = nic_i;
867 			for (int n = 0; n < iru.iru_count; n++) {
868 				bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma],
869 						BUS_DMASYNC_PREREAD);
870 				/* XXX - change this to not use the netmap func*/
871 				nic_i_dma = nm_next(nic_i_dma, lim);
872 			}
873 		}
874 	}
875 	kring->nr_hwcur = head;
876 
877 	bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
878 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
879 	if (__predict_true(nic_i != UINT_MAX)) {
880 		ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
881 		DBG_COUNTER_INC(rxd_flush);
882 	}
883 	return (0);
884 }
885 
886 /*
887  * Reconcile kernel and user view of the transmit ring.
888  *
889  * All information is in the kring.
890  * Userspace wants to send packets up to the one before kring->rhead,
891  * kernel knows kring->nr_hwcur is the first unsent packet.
892  *
893  * Here we push packets out (as many as possible), and possibly
894  * reclaim buffers from previously completed transmission.
895  *
896  * The caller (netmap) guarantees that there is only one instance
897  * running at any time. Any interference with other driver
898  * methods should be handled by the individual drivers.
899  */
900 static int
901 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
902 {
903 	struct netmap_adapter *na = kring->na;
904 	if_t ifp = na->ifp;
905 	struct netmap_ring *ring = kring->ring;
906 	u_int nm_i;	/* index into the netmap kring */
907 	u_int nic_i;	/* index into the NIC ring */
908 	u_int n;
909 	u_int const lim = kring->nkr_num_slots - 1;
910 	u_int const head = kring->rhead;
911 	struct if_pkt_info pi;
912 
913 	/*
914 	 * interrupts on every tx packet are expensive so request
915 	 * them every half ring, or where NS_REPORT is set
916 	 */
917 	u_int report_frequency = kring->nkr_num_slots >> 1;
918 	/* device-specific */
919 	if_ctx_t ctx = ifp->if_softc;
920 	iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
921 
922 	bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
923 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
924 
925 	/*
926 	 * First part: process new packets to send.
927 	 * nm_i is the current index in the netmap kring,
928 	 * nic_i is the corresponding index in the NIC ring.
929 	 *
930 	 * If we have packets to send (nm_i != head)
931 	 * iterate over the netmap ring, fetch length and update
932 	 * the corresponding slot in the NIC ring. Some drivers also
933 	 * need to update the buffer's physical address in the NIC slot
934 	 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
935 	 *
936 	 * The netmap_reload_map() calls is especially expensive,
937 	 * even when (as in this case) the tag is 0, so do only
938 	 * when the buffer has actually changed.
939 	 *
940 	 * If possible do not set the report/intr bit on all slots,
941 	 * but only a few times per ring or when NS_REPORT is set.
942 	 *
943 	 * Finally, on 10G and faster drivers, it might be useful
944 	 * to prefetch the next slot and txr entry.
945 	 */
946 
947 	nm_i = kring->nr_hwcur;
948 	if (nm_i != head) {	/* we have new packets to send */
949 		pkt_info_zero(&pi);
950 		pi.ipi_segs = txq->ift_segs;
951 		pi.ipi_qsidx = kring->ring_id;
952 		nic_i = netmap_idx_k2n(kring, nm_i);
953 
954 		__builtin_prefetch(&ring->slot[nm_i]);
955 		__builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
956 		__builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
957 
958 		for (n = 0; nm_i != head; n++) {
959 			struct netmap_slot *slot = &ring->slot[nm_i];
960 			u_int len = slot->len;
961 			uint64_t paddr;
962 			void *addr = PNMB(na, slot, &paddr);
963 			int flags = (slot->flags & NS_REPORT ||
964 				nic_i == 0 || nic_i == report_frequency) ?
965 				IPI_TX_INTR : 0;
966 
967 			/* device-specific */
968 			pi.ipi_len = len;
969 			pi.ipi_segs[0].ds_addr = paddr;
970 			pi.ipi_segs[0].ds_len = len;
971 			pi.ipi_nsegs = 1;
972 			pi.ipi_ndescs = 0;
973 			pi.ipi_pidx = nic_i;
974 			pi.ipi_flags = flags;
975 
976 			/* Fill the slot in the NIC ring. */
977 			ctx->isc_txd_encap(ctx->ifc_softc, &pi);
978 			DBG_COUNTER_INC(tx_encap);
979 
980 			/* prefetch for next round */
981 			__builtin_prefetch(&ring->slot[nm_i + 1]);
982 			__builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
983 			__builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
984 
985 			NM_CHECK_ADDR_LEN(na, addr, len);
986 
987 			if (slot->flags & NS_BUF_CHANGED) {
988 				/* buffer has changed, reload map */
989 				netmap_reload_map(na, txq->ift_buf_tag,
990 				    txq->ift_sds.ifsd_map[nic_i], addr);
991 			}
992 			/* make sure changes to the buffer are synced */
993 			bus_dmamap_sync(txq->ift_buf_tag,
994 			    txq->ift_sds.ifsd_map[nic_i],
995 			    BUS_DMASYNC_PREWRITE);
996 
997 			slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
998 			nm_i = nm_next(nm_i, lim);
999 			nic_i = nm_next(nic_i, lim);
1000 		}
1001 		kring->nr_hwcur = nm_i;
1002 
1003 		/* synchronize the NIC ring */
1004 		bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1005 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1006 
1007 		/* (re)start the tx unit up to slot nic_i (excluded) */
1008 		ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1009 	}
1010 
1011 	/*
1012 	 * Second part: reclaim buffers for completed transmissions.
1013 	 *
1014 	 * If there are unclaimed buffers, attempt to reclaim them.
1015 	 * If none are reclaimed, and TX IRQs are not in use, do an initial
1016 	 * minimal delay, then trigger the tx handler which will spin in the
1017 	 * group task queue.
1018 	 */
1019 	if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1020 		if (iflib_tx_credits_update(ctx, txq)) {
1021 			/* some tx completed, increment avail */
1022 			nic_i = txq->ift_cidx_processed;
1023 			kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1024 		}
1025 	}
1026 	if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1027 		if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1028 			callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1029 			    iflib_timer, txq, txq->ift_timer.c_cpu);
1030 	}
1031 	return (0);
1032 }
1033 
1034 /*
1035  * Reconcile kernel and user view of the receive ring.
1036  * Same as for the txsync, this routine must be efficient.
1037  * The caller guarantees a single invocations, but races against
1038  * the rest of the driver should be handled here.
1039  *
1040  * On call, kring->rhead is the first packet that userspace wants
1041  * to keep, and kring->rcur is the wakeup point.
1042  * The kernel has previously reported packets up to kring->rtail.
1043  *
1044  * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1045  * of whether or not we received an interrupt.
1046  */
1047 static int
1048 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1049 {
1050 	struct netmap_adapter *na = kring->na;
1051 	struct netmap_ring *ring = kring->ring;
1052 	if_t ifp = na->ifp;
1053 	iflib_fl_t fl;
1054 	uint32_t nm_i;	/* index into the netmap ring */
1055 	uint32_t nic_i;	/* index into the NIC ring */
1056 	u_int i, n;
1057 	u_int const lim = kring->nkr_num_slots - 1;
1058 	u_int const head = kring->rhead;
1059 	int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1060 	struct if_rxd_info ri;
1061 
1062 	if_ctx_t ctx = ifp->if_softc;
1063 	iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1064 	if (head > lim)
1065 		return netmap_ring_reinit(kring);
1066 
1067 	/*
1068 	 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far.
1069 	 */
1070 
1071 	for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1072 		bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1073 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1074 	}
1075 
1076 	/*
1077 	 * First part: import newly received packets.
1078 	 *
1079 	 * nm_i is the index of the next free slot in the netmap ring,
1080 	 * nic_i is the index of the next received packet in the NIC ring,
1081 	 * and they may differ in case if_init() has been called while
1082 	 * in netmap mode. For the receive ring we have
1083 	 *
1084 	 *	nic_i = rxr->next_check;
1085 	 *	nm_i = kring->nr_hwtail (previous)
1086 	 * and
1087 	 *	nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1088 	 *
1089 	 * rxr->next_check is set to 0 on a ring reinit
1090 	 */
1091 	if (netmap_no_pendintr || force_update) {
1092 		int crclen = iflib_crcstrip ? 0 : 4;
1093 		int error, avail;
1094 
1095 		for (i = 0; i < rxq->ifr_nfl; i++) {
1096 			fl = &rxq->ifr_fl[i];
1097 			nic_i = fl->ifl_cidx;
1098 			nm_i = netmap_idx_n2k(kring, nic_i);
1099 			avail = ctx->isc_rxd_available(ctx->ifc_softc,
1100 			    rxq->ifr_id, nic_i, USHRT_MAX);
1101 			for (n = 0; avail > 0; n++, avail--) {
1102 				rxd_info_zero(&ri);
1103 				ri.iri_frags = rxq->ifr_frags;
1104 				ri.iri_qsidx = kring->ring_id;
1105 				ri.iri_ifp = ctx->ifc_ifp;
1106 				ri.iri_cidx = nic_i;
1107 
1108 				error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1109 				ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1110 				ring->slot[nm_i].flags = 0;
1111 				bus_dmamap_sync(fl->ifl_buf_tag,
1112 				    fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1113 				nm_i = nm_next(nm_i, lim);
1114 				nic_i = nm_next(nic_i, lim);
1115 			}
1116 			if (n) { /* update the state variables */
1117 				if (netmap_no_pendintr && !force_update) {
1118 					/* diagnostics */
1119 					iflib_rx_miss ++;
1120 					iflib_rx_miss_bufs += n;
1121 				}
1122 				fl->ifl_cidx = nic_i;
1123 				kring->nr_hwtail = nm_i;
1124 			}
1125 			kring->nr_kflags &= ~NKR_PENDINTR;
1126 		}
1127 	}
1128 	/*
1129 	 * Second part: skip past packets that userspace has released.
1130 	 * (kring->nr_hwcur to head excluded),
1131 	 * and make the buffers available for reception.
1132 	 * As usual nm_i is the index in the netmap ring,
1133 	 * nic_i is the index in the NIC ring, and
1134 	 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1135 	 */
1136 	/* XXX not sure how this will work with multiple free lists */
1137 	nm_i = kring->nr_hwcur;
1138 
1139 	return (netmap_fl_refill(rxq, kring, nm_i, false));
1140 }
1141 
1142 static void
1143 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1144 {
1145 	if_ctx_t ctx = na->ifp->if_softc;
1146 
1147 	CTX_LOCK(ctx);
1148 	if (onoff) {
1149 		IFDI_INTR_ENABLE(ctx);
1150 	} else {
1151 		IFDI_INTR_DISABLE(ctx);
1152 	}
1153 	CTX_UNLOCK(ctx);
1154 }
1155 
1156 
1157 static int
1158 iflib_netmap_attach(if_ctx_t ctx)
1159 {
1160 	struct netmap_adapter na;
1161 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1162 
1163 	bzero(&na, sizeof(na));
1164 
1165 	na.ifp = ctx->ifc_ifp;
1166 	na.na_flags = NAF_BDG_MAYSLEEP;
1167 	MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1168 	MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1169 
1170 	na.num_tx_desc = scctx->isc_ntxd[0];
1171 	na.num_rx_desc = scctx->isc_nrxd[0];
1172 	na.nm_txsync = iflib_netmap_txsync;
1173 	na.nm_rxsync = iflib_netmap_rxsync;
1174 	na.nm_register = iflib_netmap_register;
1175 	na.nm_intr = iflib_netmap_intr;
1176 	na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1177 	na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1178 	return (netmap_attach(&na));
1179 }
1180 
1181 static void
1182 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1183 {
1184 	struct netmap_adapter *na = NA(ctx->ifc_ifp);
1185 	struct netmap_slot *slot;
1186 
1187 	slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1188 	if (slot == NULL)
1189 		return;
1190 	for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1191 
1192 		/*
1193 		 * In netmap mode, set the map for the packet buffer.
1194 		 * NOTE: Some drivers (not this one) also need to set
1195 		 * the physical buffer address in the NIC ring.
1196 		 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1197 		 * netmap slot index, si
1198 		 */
1199 		int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1200 		netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1201 		    NMB(na, slot + si));
1202 	}
1203 }
1204 
1205 static void
1206 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1207 {
1208 	struct netmap_adapter *na = NA(ctx->ifc_ifp);
1209 	struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1210 	struct netmap_slot *slot;
1211 	uint32_t nm_i;
1212 
1213 	slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1214 	if (slot == NULL)
1215 		return;
1216 	nm_i = netmap_idx_n2k(kring, 0);
1217 	netmap_fl_refill(rxq, kring, nm_i, true);
1218 }
1219 
1220 static void
1221 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on)
1222 {
1223 	struct netmap_kring *kring;
1224 	uint16_t txqid;
1225 
1226 	txqid = txq->ift_id;
1227 	kring = NA(ctx->ifc_ifp)->tx_rings[txqid];
1228 
1229 	if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1230 		bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1231 		    BUS_DMASYNC_POSTREAD);
1232 		if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1233 			netmap_tx_irq(ctx->ifc_ifp, txqid);
1234 		if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1235 			if (hz < 2000)
1236 				*reset_on = 1;
1237 			else
1238 				*reset_on = hz / 1000;
1239 		}
1240 	}
1241 }
1242 
1243 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1244 
1245 #else
1246 #define iflib_netmap_txq_init(ctx, txq)
1247 #define iflib_netmap_rxq_init(ctx, rxq)
1248 #define iflib_netmap_detach(ifp)
1249 
1250 #define iflib_netmap_attach(ctx) (0)
1251 #define netmap_rx_irq(ifp, qid, budget) (0)
1252 #define netmap_tx_irq(ifp, qid) do {} while (0)
1253 #define iflib_netmap_timer_adjust(ctx, txq, reset_on)
1254 #endif
1255 
1256 #if defined(__i386__) || defined(__amd64__)
1257 static __inline void
1258 prefetch(void *x)
1259 {
1260 	__asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1261 }
1262 static __inline void
1263 prefetch2cachelines(void *x)
1264 {
1265 	__asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1266 #if (CACHE_LINE_SIZE < 128)
1267 	__asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1268 #endif
1269 }
1270 #else
1271 #define prefetch(x)
1272 #define prefetch2cachelines(x)
1273 #endif
1274 
1275 static void
1276 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1277 {
1278 	iflib_fl_t fl;
1279 
1280 	fl = &rxq->ifr_fl[flid];
1281 	iru->iru_paddrs = fl->ifl_bus_addrs;
1282 	iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1283 	iru->iru_idxs = fl->ifl_rxd_idxs;
1284 	iru->iru_qsidx = rxq->ifr_id;
1285 	iru->iru_buf_size = fl->ifl_buf_size;
1286 	iru->iru_flidx = fl->ifl_id;
1287 }
1288 
1289 static void
1290 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1291 {
1292 	if (err)
1293 		return;
1294 	*(bus_addr_t *) arg = segs[0].ds_addr;
1295 }
1296 
1297 int
1298 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1299 {
1300 	int err;
1301 	device_t dev = ctx->ifc_dev;
1302 
1303 	err = bus_dma_tag_create(bus_get_dma_tag(dev),	/* parent */
1304 				align, 0,		/* alignment, bounds */
1305 				BUS_SPACE_MAXADDR,	/* lowaddr */
1306 				BUS_SPACE_MAXADDR,	/* highaddr */
1307 				NULL, NULL,		/* filter, filterarg */
1308 				size,			/* maxsize */
1309 				1,			/* nsegments */
1310 				size,			/* maxsegsize */
1311 				BUS_DMA_ALLOCNOW,	/* flags */
1312 				NULL,			/* lockfunc */
1313 				NULL,			/* lockarg */
1314 				&dma->idi_tag);
1315 	if (err) {
1316 		device_printf(dev,
1317 		    "%s: bus_dma_tag_create failed: %d\n",
1318 		    __func__, err);
1319 		goto fail_0;
1320 	}
1321 
1322 	err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1323 	    BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1324 	if (err) {
1325 		device_printf(dev,
1326 		    "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1327 		    __func__, (uintmax_t)size, err);
1328 		goto fail_1;
1329 	}
1330 
1331 	dma->idi_paddr = IF_BAD_DMA;
1332 	err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1333 	    size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1334 	if (err || dma->idi_paddr == IF_BAD_DMA) {
1335 		device_printf(dev,
1336 		    "%s: bus_dmamap_load failed: %d\n",
1337 		    __func__, err);
1338 		goto fail_2;
1339 	}
1340 
1341 	dma->idi_size = size;
1342 	return (0);
1343 
1344 fail_2:
1345 	bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1346 fail_1:
1347 	bus_dma_tag_destroy(dma->idi_tag);
1348 fail_0:
1349 	dma->idi_tag = NULL;
1350 
1351 	return (err);
1352 }
1353 
1354 int
1355 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1356 {
1357 	if_shared_ctx_t sctx = ctx->ifc_sctx;
1358 
1359 	KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1360 
1361 	return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1362 }
1363 
1364 int
1365 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1366 {
1367 	int i, err;
1368 	iflib_dma_info_t *dmaiter;
1369 
1370 	dmaiter = dmalist;
1371 	for (i = 0; i < count; i++, dmaiter++) {
1372 		if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1373 			break;
1374 	}
1375 	if (err)
1376 		iflib_dma_free_multi(dmalist, i);
1377 	return (err);
1378 }
1379 
1380 void
1381 iflib_dma_free(iflib_dma_info_t dma)
1382 {
1383 	if (dma->idi_tag == NULL)
1384 		return;
1385 	if (dma->idi_paddr != IF_BAD_DMA) {
1386 		bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1387 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1388 		bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1389 		dma->idi_paddr = IF_BAD_DMA;
1390 	}
1391 	if (dma->idi_vaddr != NULL) {
1392 		bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1393 		dma->idi_vaddr = NULL;
1394 	}
1395 	bus_dma_tag_destroy(dma->idi_tag);
1396 	dma->idi_tag = NULL;
1397 }
1398 
1399 void
1400 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1401 {
1402 	int i;
1403 	iflib_dma_info_t *dmaiter = dmalist;
1404 
1405 	for (i = 0; i < count; i++, dmaiter++)
1406 		iflib_dma_free(*dmaiter);
1407 }
1408 
1409 #ifdef EARLY_AP_STARTUP
1410 static const int iflib_started = 1;
1411 #else
1412 /*
1413  * We used to abuse the smp_started flag to decide if the queues have been
1414  * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1415  * That gave bad races, since the SYSINIT() runs strictly after smp_started
1416  * is set.  Run a SYSINIT() strictly after that to just set a usable
1417  * completion flag.
1418  */
1419 
1420 static int iflib_started;
1421 
1422 static void
1423 iflib_record_started(void *arg)
1424 {
1425 	iflib_started = 1;
1426 }
1427 
1428 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1429 	iflib_record_started, NULL);
1430 #endif
1431 
1432 static int
1433 iflib_fast_intr(void *arg)
1434 {
1435 	iflib_filter_info_t info = arg;
1436 	struct grouptask *gtask = info->ifi_task;
1437 	int result;
1438 
1439 	if (!iflib_started)
1440 		return (FILTER_STRAY);
1441 
1442 	DBG_COUNTER_INC(fast_intrs);
1443 	if (info->ifi_filter != NULL) {
1444 		result = info->ifi_filter(info->ifi_filter_arg);
1445 		if ((result & FILTER_SCHEDULE_THREAD) == 0)
1446 			return (result);
1447 	}
1448 
1449 	GROUPTASK_ENQUEUE(gtask);
1450 	return (FILTER_HANDLED);
1451 }
1452 
1453 static int
1454 iflib_fast_intr_rxtx(void *arg)
1455 {
1456 	iflib_filter_info_t info = arg;
1457 	struct grouptask *gtask = info->ifi_task;
1458 	if_ctx_t ctx;
1459 	iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1460 	iflib_txq_t txq;
1461 	void *sc;
1462 	int i, cidx, result;
1463 	qidx_t txqid;
1464 	bool intr_enable, intr_legacy;
1465 
1466 	if (!iflib_started)
1467 		return (FILTER_STRAY);
1468 
1469 	DBG_COUNTER_INC(fast_intrs);
1470 	if (info->ifi_filter != NULL) {
1471 		result = info->ifi_filter(info->ifi_filter_arg);
1472 		if ((result & FILTER_SCHEDULE_THREAD) == 0)
1473 			return (result);
1474 	}
1475 
1476 	ctx = rxq->ifr_ctx;
1477 	sc = ctx->ifc_softc;
1478 	intr_enable = false;
1479 	intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1480 	MPASS(rxq->ifr_ntxqirq);
1481 	for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1482 		txqid = rxq->ifr_txqid[i];
1483 		txq = &ctx->ifc_txqs[txqid];
1484 		bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1485 		    BUS_DMASYNC_POSTREAD);
1486 		if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1487 			if (intr_legacy)
1488 				intr_enable = true;
1489 			else
1490 				IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1491 			continue;
1492 		}
1493 		GROUPTASK_ENQUEUE(&txq->ift_task);
1494 	}
1495 	if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1496 		cidx = rxq->ifr_cq_cidx;
1497 	else
1498 		cidx = rxq->ifr_fl[0].ifl_cidx;
1499 	if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1500 		GROUPTASK_ENQUEUE(gtask);
1501 	else {
1502 		if (intr_legacy)
1503 			intr_enable = true;
1504 		else
1505 			IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1506 		DBG_COUNTER_INC(rx_intr_enables);
1507 	}
1508 	if (intr_enable)
1509 		IFDI_INTR_ENABLE(ctx);
1510 	return (FILTER_HANDLED);
1511 }
1512 
1513 
1514 static int
1515 iflib_fast_intr_ctx(void *arg)
1516 {
1517 	iflib_filter_info_t info = arg;
1518 	struct grouptask *gtask = info->ifi_task;
1519 	int result;
1520 
1521 	if (!iflib_started)
1522 		return (FILTER_STRAY);
1523 
1524 	DBG_COUNTER_INC(fast_intrs);
1525 	if (info->ifi_filter != NULL) {
1526 		result = info->ifi_filter(info->ifi_filter_arg);
1527 		if ((result & FILTER_SCHEDULE_THREAD) == 0)
1528 			return (result);
1529 	}
1530 
1531 	GROUPTASK_ENQUEUE(gtask);
1532 	return (FILTER_HANDLED);
1533 }
1534 
1535 static int
1536 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1537 		 driver_filter_t filter, driver_intr_t handler, void *arg,
1538 		 const char *name)
1539 {
1540 	struct resource *res;
1541 	void *tag = NULL;
1542 	device_t dev = ctx->ifc_dev;
1543 	int flags, i, rc;
1544 
1545 	flags = RF_ACTIVE;
1546 	if (ctx->ifc_flags & IFC_LEGACY)
1547 		flags |= RF_SHAREABLE;
1548 	MPASS(rid < 512);
1549 	i = rid;
1550 	res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags);
1551 	if (res == NULL) {
1552 		device_printf(dev,
1553 		    "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1554 		return (ENOMEM);
1555 	}
1556 	irq->ii_res = res;
1557 	KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1558 	rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1559 						filter, handler, arg, &tag);
1560 	if (rc != 0) {
1561 		device_printf(dev,
1562 		    "failed to setup interrupt for rid %d, name %s: %d\n",
1563 					  rid, name ? name : "unknown", rc);
1564 		return (rc);
1565 	} else if (name)
1566 		bus_describe_intr(dev, res, tag, "%s", name);
1567 
1568 	irq->ii_tag = tag;
1569 	return (0);
1570 }
1571 
1572 /*********************************************************************
1573  *
1574  *  Allocate DMA resources for TX buffers as well as memory for the TX
1575  *  mbuf map.  TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1576  *  iflib_sw_tx_desc_array structure, storing all the information that
1577  *  is needed to transmit a packet on the wire.  This is called only
1578  *  once at attach, setup is done every reset.
1579  *
1580  **********************************************************************/
1581 static int
1582 iflib_txsd_alloc(iflib_txq_t txq)
1583 {
1584 	if_ctx_t ctx = txq->ift_ctx;
1585 	if_shared_ctx_t sctx = ctx->ifc_sctx;
1586 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1587 	device_t dev = ctx->ifc_dev;
1588 	bus_size_t tsomaxsize;
1589 	int err, nsegments, ntsosegments;
1590 	bool tso;
1591 
1592 	nsegments = scctx->isc_tx_nsegments;
1593 	ntsosegments = scctx->isc_tx_tso_segments_max;
1594 	tsomaxsize = scctx->isc_tx_tso_size_max;
1595 	if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1596 		tsomaxsize += sizeof(struct ether_vlan_header);
1597 	MPASS(scctx->isc_ntxd[0] > 0);
1598 	MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1599 	MPASS(nsegments > 0);
1600 	if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1601 		MPASS(ntsosegments > 0);
1602 		MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1603 	}
1604 
1605 	/*
1606 	 * Set up DMA tags for TX buffers.
1607 	 */
1608 	if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1609 			       1, 0,			/* alignment, bounds */
1610 			       BUS_SPACE_MAXADDR,	/* lowaddr */
1611 			       BUS_SPACE_MAXADDR,	/* highaddr */
1612 			       NULL, NULL,		/* filter, filterarg */
1613 			       sctx->isc_tx_maxsize,		/* maxsize */
1614 			       nsegments,	/* nsegments */
1615 			       sctx->isc_tx_maxsegsize,	/* maxsegsize */
1616 			       0,			/* flags */
1617 			       NULL,			/* lockfunc */
1618 			       NULL,			/* lockfuncarg */
1619 			       &txq->ift_buf_tag))) {
1620 		device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1621 		device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1622 		    (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1623 		goto fail;
1624 	}
1625 	tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1626 	if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1627 			       1, 0,			/* alignment, bounds */
1628 			       BUS_SPACE_MAXADDR,	/* lowaddr */
1629 			       BUS_SPACE_MAXADDR,	/* highaddr */
1630 			       NULL, NULL,		/* filter, filterarg */
1631 			       tsomaxsize,		/* maxsize */
1632 			       ntsosegments,	/* nsegments */
1633 			       sctx->isc_tso_maxsegsize,/* maxsegsize */
1634 			       0,			/* flags */
1635 			       NULL,			/* lockfunc */
1636 			       NULL,			/* lockfuncarg */
1637 			       &txq->ift_tso_buf_tag))) {
1638 		device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1639 		    err);
1640 		goto fail;
1641 	}
1642 
1643 	/* Allocate memory for the TX mbuf map. */
1644 	if (!(txq->ift_sds.ifsd_m =
1645 	    (struct mbuf **) malloc(sizeof(struct mbuf *) *
1646 	    scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1647 		device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1648 		err = ENOMEM;
1649 		goto fail;
1650 	}
1651 
1652 	/*
1653 	 * Create the DMA maps for TX buffers.
1654 	 */
1655 	if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1656 	    sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1657 	    M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1658 		device_printf(dev,
1659 		    "Unable to allocate TX buffer DMA map memory\n");
1660 		err = ENOMEM;
1661 		goto fail;
1662 	}
1663 	if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1664 	    sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1665 	    M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1666 		device_printf(dev,
1667 		    "Unable to allocate TSO TX buffer map memory\n");
1668 		err = ENOMEM;
1669 		goto fail;
1670 	}
1671 	for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1672 		err = bus_dmamap_create(txq->ift_buf_tag, 0,
1673 		    &txq->ift_sds.ifsd_map[i]);
1674 		if (err != 0) {
1675 			device_printf(dev, "Unable to create TX DMA map\n");
1676 			goto fail;
1677 		}
1678 		if (!tso)
1679 			continue;
1680 		err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1681 		    &txq->ift_sds.ifsd_tso_map[i]);
1682 		if (err != 0) {
1683 			device_printf(dev, "Unable to create TSO TX DMA map\n");
1684 			goto fail;
1685 		}
1686 	}
1687 	return (0);
1688 fail:
1689 	/* We free all, it handles case where we are in the middle */
1690 	iflib_tx_structures_free(ctx);
1691 	return (err);
1692 }
1693 
1694 static void
1695 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1696 {
1697 	bus_dmamap_t map;
1698 
1699 	if (txq->ift_sds.ifsd_map != NULL) {
1700 		map = txq->ift_sds.ifsd_map[i];
1701 		bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1702 		bus_dmamap_unload(txq->ift_buf_tag, map);
1703 		bus_dmamap_destroy(txq->ift_buf_tag, map);
1704 		txq->ift_sds.ifsd_map[i] = NULL;
1705 	}
1706 
1707 	if (txq->ift_sds.ifsd_tso_map != NULL) {
1708 		map = txq->ift_sds.ifsd_tso_map[i];
1709 		bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1710 		    BUS_DMASYNC_POSTWRITE);
1711 		bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1712 		bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1713 		txq->ift_sds.ifsd_tso_map[i] = NULL;
1714 	}
1715 }
1716 
1717 static void
1718 iflib_txq_destroy(iflib_txq_t txq)
1719 {
1720 	if_ctx_t ctx = txq->ift_ctx;
1721 
1722 	for (int i = 0; i < txq->ift_size; i++)
1723 		iflib_txsd_destroy(ctx, txq, i);
1724 
1725 	if (txq->ift_br != NULL) {
1726 		ifmp_ring_free(txq->ift_br);
1727 		txq->ift_br = NULL;
1728 	}
1729 
1730 	mtx_destroy(&txq->ift_mtx);
1731 
1732 	if (txq->ift_sds.ifsd_map != NULL) {
1733 		free(txq->ift_sds.ifsd_map, M_IFLIB);
1734 		txq->ift_sds.ifsd_map = NULL;
1735 	}
1736 	if (txq->ift_sds.ifsd_tso_map != NULL) {
1737 		free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1738 		txq->ift_sds.ifsd_tso_map = NULL;
1739 	}
1740 	if (txq->ift_sds.ifsd_m != NULL) {
1741 		free(txq->ift_sds.ifsd_m, M_IFLIB);
1742 		txq->ift_sds.ifsd_m = NULL;
1743 	}
1744 	if (txq->ift_buf_tag != NULL) {
1745 		bus_dma_tag_destroy(txq->ift_buf_tag);
1746 		txq->ift_buf_tag = NULL;
1747 	}
1748 	if (txq->ift_tso_buf_tag != NULL) {
1749 		bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1750 		txq->ift_tso_buf_tag = NULL;
1751 	}
1752 	if (txq->ift_ifdi != NULL) {
1753 		free(txq->ift_ifdi, M_IFLIB);
1754 	}
1755 }
1756 
1757 static void
1758 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1759 {
1760 	struct mbuf **mp;
1761 
1762 	mp = &txq->ift_sds.ifsd_m[i];
1763 	if (*mp == NULL)
1764 		return;
1765 
1766 	if (txq->ift_sds.ifsd_map != NULL) {
1767 		bus_dmamap_sync(txq->ift_buf_tag,
1768 		    txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1769 		bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1770 	}
1771 	if (txq->ift_sds.ifsd_tso_map != NULL) {
1772 		bus_dmamap_sync(txq->ift_tso_buf_tag,
1773 		    txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1774 		bus_dmamap_unload(txq->ift_tso_buf_tag,
1775 		    txq->ift_sds.ifsd_tso_map[i]);
1776 	}
1777 	m_free(*mp);
1778 	DBG_COUNTER_INC(tx_frees);
1779 	*mp = NULL;
1780 }
1781 
1782 static int
1783 iflib_txq_setup(iflib_txq_t txq)
1784 {
1785 	if_ctx_t ctx = txq->ift_ctx;
1786 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1787 	if_shared_ctx_t sctx = ctx->ifc_sctx;
1788 	iflib_dma_info_t di;
1789 	int i;
1790 
1791 	/* Set number of descriptors available */
1792 	txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1793 	/* XXX make configurable */
1794 	txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1795 
1796 	/* Reset indices */
1797 	txq->ift_cidx_processed = 0;
1798 	txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1799 	txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1800 
1801 	for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1802 		bzero((void *)di->idi_vaddr, di->idi_size);
1803 
1804 	IFDI_TXQ_SETUP(ctx, txq->ift_id);
1805 	for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1806 		bus_dmamap_sync(di->idi_tag, di->idi_map,
1807 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1808 	return (0);
1809 }
1810 
1811 /*********************************************************************
1812  *
1813  *  Allocate DMA resources for RX buffers as well as memory for the RX
1814  *  mbuf map, direct RX cluster pointer map and RX cluster bus address
1815  *  map.  RX DMA map, RX mbuf map, direct RX cluster pointer map and
1816  *  RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1817  *  Since we use use one entry in iflib_sw_rx_desc_array per received
1818  *  packet, the maximum number of entries we'll need is equal to the
1819  *  number of hardware receive descriptors that we've allocated.
1820  *
1821  **********************************************************************/
1822 static int
1823 iflib_rxsd_alloc(iflib_rxq_t rxq)
1824 {
1825 	if_ctx_t ctx = rxq->ifr_ctx;
1826 	if_shared_ctx_t sctx = ctx->ifc_sctx;
1827 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1828 	device_t dev = ctx->ifc_dev;
1829 	iflib_fl_t fl;
1830 	int			err;
1831 
1832 	MPASS(scctx->isc_nrxd[0] > 0);
1833 	MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1834 
1835 	fl = rxq->ifr_fl;
1836 	for (int i = 0; i <  rxq->ifr_nfl; i++, fl++) {
1837 		fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1838 		/* Set up DMA tag for RX buffers. */
1839 		err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1840 					 1, 0,			/* alignment, bounds */
1841 					 BUS_SPACE_MAXADDR,	/* lowaddr */
1842 					 BUS_SPACE_MAXADDR,	/* highaddr */
1843 					 NULL, NULL,		/* filter, filterarg */
1844 					 sctx->isc_rx_maxsize,	/* maxsize */
1845 					 sctx->isc_rx_nsegments,	/* nsegments */
1846 					 sctx->isc_rx_maxsegsize,	/* maxsegsize */
1847 					 0,			/* flags */
1848 					 NULL,			/* lockfunc */
1849 					 NULL,			/* lockarg */
1850 					 &fl->ifl_buf_tag);
1851 		if (err) {
1852 			device_printf(dev,
1853 			    "Unable to allocate RX DMA tag: %d\n", err);
1854 			goto fail;
1855 		}
1856 
1857 		/* Allocate memory for the RX mbuf map. */
1858 		if (!(fl->ifl_sds.ifsd_m =
1859 		      (struct mbuf **) malloc(sizeof(struct mbuf *) *
1860 					      scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1861 			device_printf(dev,
1862 			    "Unable to allocate RX mbuf map memory\n");
1863 			err = ENOMEM;
1864 			goto fail;
1865 		}
1866 
1867 		/* Allocate memory for the direct RX cluster pointer map. */
1868 		if (!(fl->ifl_sds.ifsd_cl =
1869 		      (caddr_t *) malloc(sizeof(caddr_t) *
1870 					      scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1871 			device_printf(dev,
1872 			    "Unable to allocate RX cluster map memory\n");
1873 			err = ENOMEM;
1874 			goto fail;
1875 		}
1876 
1877 		/* Allocate memory for the RX cluster bus address map. */
1878 		if (!(fl->ifl_sds.ifsd_ba =
1879 		      (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1880 					      scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1881 			device_printf(dev,
1882 			    "Unable to allocate RX bus address map memory\n");
1883 			err = ENOMEM;
1884 			goto fail;
1885 		}
1886 
1887 		/*
1888 		 * Create the DMA maps for RX buffers.
1889 		 */
1890 		if (!(fl->ifl_sds.ifsd_map =
1891 		      (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1892 			device_printf(dev,
1893 			    "Unable to allocate RX buffer DMA map memory\n");
1894 			err = ENOMEM;
1895 			goto fail;
1896 		}
1897 		for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1898 			err = bus_dmamap_create(fl->ifl_buf_tag, 0,
1899 			    &fl->ifl_sds.ifsd_map[i]);
1900 			if (err != 0) {
1901 				device_printf(dev, "Unable to create RX buffer DMA map\n");
1902 				goto fail;
1903 			}
1904 		}
1905 	}
1906 	return (0);
1907 
1908 fail:
1909 	iflib_rx_structures_free(ctx);
1910 	return (err);
1911 }
1912 
1913 
1914 /*
1915  * Internal service routines
1916  */
1917 
1918 struct rxq_refill_cb_arg {
1919 	int               error;
1920 	bus_dma_segment_t seg;
1921 	int               nseg;
1922 };
1923 
1924 static void
1925 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1926 {
1927 	struct rxq_refill_cb_arg *cb_arg = arg;
1928 
1929 	cb_arg->error = error;
1930 	cb_arg->seg = segs[0];
1931 	cb_arg->nseg = nseg;
1932 }
1933 
1934 /**
1935  * _iflib_fl_refill - refill an rxq free-buffer list
1936  * @ctx: the iflib context
1937  * @fl: the free list to refill
1938  * @count: the number of new buffers to allocate
1939  *
1940  * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
1941  * The caller must assure that @count does not exceed the queue's capacity.
1942  */
1943 static void
1944 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1945 {
1946 	struct if_rxd_update iru;
1947 	struct rxq_refill_cb_arg cb_arg;
1948 	struct mbuf *m;
1949 	caddr_t cl, *sd_cl;
1950 	struct mbuf **sd_m;
1951 	bus_dmamap_t *sd_map;
1952 	bus_addr_t bus_addr, *sd_ba;
1953 	int err, frag_idx, i, idx, n, pidx;
1954 	qidx_t credits;
1955 
1956 	sd_m = fl->ifl_sds.ifsd_m;
1957 	sd_map = fl->ifl_sds.ifsd_map;
1958 	sd_cl = fl->ifl_sds.ifsd_cl;
1959 	sd_ba = fl->ifl_sds.ifsd_ba;
1960 	pidx = fl->ifl_pidx;
1961 	idx = pidx;
1962 	frag_idx = fl->ifl_fragidx;
1963 	credits = fl->ifl_credits;
1964 
1965 	i = 0;
1966 	n = count;
1967 	MPASS(n > 0);
1968 	MPASS(credits + n <= fl->ifl_size);
1969 
1970 	if (pidx < fl->ifl_cidx)
1971 		MPASS(pidx + n <= fl->ifl_cidx);
1972 	if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1973 		MPASS(fl->ifl_gen == 0);
1974 	if (pidx > fl->ifl_cidx)
1975 		MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1976 
1977 	DBG_COUNTER_INC(fl_refills);
1978 	if (n > 8)
1979 		DBG_COUNTER_INC(fl_refills_large);
1980 	iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1981 	while (n--) {
1982 		/*
1983 		 * We allocate an uninitialized mbuf + cluster, mbuf is
1984 		 * initialized after rx.
1985 		 *
1986 		 * If the cluster is still set then we know a minimum sized packet was received
1987 		 */
1988 		bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
1989 		    &frag_idx);
1990 		if (frag_idx < 0)
1991 			bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1992 		MPASS(frag_idx >= 0);
1993 		if ((cl = sd_cl[frag_idx]) == NULL) {
1994 			if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1995 				break;
1996 
1997 			cb_arg.error = 0;
1998 			MPASS(sd_map != NULL);
1999 			err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
2000 			    cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
2001 			    BUS_DMA_NOWAIT);
2002 			if (err != 0 || cb_arg.error) {
2003 				/*
2004 				 * !zone_pack ?
2005 				 */
2006 				if (fl->ifl_zone == zone_pack)
2007 					uma_zfree(fl->ifl_zone, cl);
2008 				break;
2009 			}
2010 
2011 			sd_ba[frag_idx] =  bus_addr = cb_arg.seg.ds_addr;
2012 			sd_cl[frag_idx] = cl;
2013 #if MEMORY_LOGGING
2014 			fl->ifl_cl_enqueued++;
2015 #endif
2016 		} else {
2017 			bus_addr = sd_ba[frag_idx];
2018 		}
2019 		bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2020 		    BUS_DMASYNC_PREREAD);
2021 
2022 		if (sd_m[frag_idx] == NULL) {
2023 			if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
2024 				break;
2025 			}
2026 			sd_m[frag_idx] = m;
2027 		}
2028 		bit_set(fl->ifl_rx_bitmap, frag_idx);
2029 #if MEMORY_LOGGING
2030 		fl->ifl_m_enqueued++;
2031 #endif
2032 
2033 		DBG_COUNTER_INC(rx_allocs);
2034 		fl->ifl_rxd_idxs[i] = frag_idx;
2035 		fl->ifl_bus_addrs[i] = bus_addr;
2036 		fl->ifl_vm_addrs[i] = cl;
2037 		credits++;
2038 		i++;
2039 		MPASS(credits <= fl->ifl_size);
2040 		if (++idx == fl->ifl_size) {
2041 			fl->ifl_gen = 1;
2042 			idx = 0;
2043 		}
2044 		if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2045 			iru.iru_pidx = pidx;
2046 			iru.iru_count = i;
2047 			ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2048 			i = 0;
2049 			pidx = idx;
2050 			fl->ifl_pidx = idx;
2051 			fl->ifl_credits = credits;
2052 		}
2053 	}
2054 
2055 	if (i) {
2056 		iru.iru_pidx = pidx;
2057 		iru.iru_count = i;
2058 		ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2059 		fl->ifl_pidx = idx;
2060 		fl->ifl_credits = credits;
2061 	}
2062 	DBG_COUNTER_INC(rxd_flush);
2063 	if (fl->ifl_pidx == 0)
2064 		pidx = fl->ifl_size - 1;
2065 	else
2066 		pidx = fl->ifl_pidx - 1;
2067 
2068 	bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2069 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2070 	ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
2071 	fl->ifl_fragidx = frag_idx;
2072 }
2073 
2074 static __inline void
2075 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max)
2076 {
2077 	/* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2078 	int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2079 #ifdef INVARIANTS
2080 	int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2081 #endif
2082 
2083 	MPASS(fl->ifl_credits <= fl->ifl_size);
2084 	MPASS(reclaimable == delta);
2085 
2086 	if (reclaimable > 0)
2087 		_iflib_fl_refill(ctx, fl, min(max, reclaimable));
2088 }
2089 
2090 uint8_t
2091 iflib_in_detach(if_ctx_t ctx)
2092 {
2093 	bool in_detach;
2094 
2095 	STATE_LOCK(ctx);
2096 	in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2097 	STATE_UNLOCK(ctx);
2098 	return (in_detach);
2099 }
2100 
2101 static void
2102 iflib_fl_bufs_free(iflib_fl_t fl)
2103 {
2104 	iflib_dma_info_t idi = fl->ifl_ifdi;
2105 	bus_dmamap_t sd_map;
2106 	uint32_t i;
2107 
2108 	for (i = 0; i < fl->ifl_size; i++) {
2109 		struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2110 		caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2111 
2112 		if (*sd_cl != NULL) {
2113 			sd_map = fl->ifl_sds.ifsd_map[i];
2114 			bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2115 			    BUS_DMASYNC_POSTREAD);
2116 			bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2117 			if (*sd_cl != NULL)
2118 				uma_zfree(fl->ifl_zone, *sd_cl);
2119 			if (*sd_m != NULL) {
2120 				m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2121 				uma_zfree(zone_mbuf, *sd_m);
2122 			}
2123 		} else {
2124 			MPASS(*sd_cl == NULL);
2125 			MPASS(*sd_m == NULL);
2126 		}
2127 #if MEMORY_LOGGING
2128 		fl->ifl_m_dequeued++;
2129 		fl->ifl_cl_dequeued++;
2130 #endif
2131 		*sd_cl = NULL;
2132 		*sd_m = NULL;
2133 	}
2134 #ifdef INVARIANTS
2135 	for (i = 0; i < fl->ifl_size; i++) {
2136 		MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2137 		MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2138 	}
2139 #endif
2140 	/*
2141 	 * Reset free list values
2142 	 */
2143 	fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2144 	bzero(idi->idi_vaddr, idi->idi_size);
2145 }
2146 
2147 /*********************************************************************
2148  *
2149  *  Initialize a free list and its buffers.
2150  *
2151  **********************************************************************/
2152 static int
2153 iflib_fl_setup(iflib_fl_t fl)
2154 {
2155 	iflib_rxq_t rxq = fl->ifl_rxq;
2156 	if_ctx_t ctx = rxq->ifr_ctx;
2157 
2158 	bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2159 	/*
2160 	** Free current RX buffer structs and their mbufs
2161 	*/
2162 	iflib_fl_bufs_free(fl);
2163 	/* Now replenish the mbufs */
2164 	MPASS(fl->ifl_credits == 0);
2165 	fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2166 	if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2167 		ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2168 	fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2169 	fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2170 
2171 
2172 	/* avoid pre-allocating zillions of clusters to an idle card
2173 	 * potentially speeding up attach
2174 	 */
2175 	_iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2176 	MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2177 	if (min(128, fl->ifl_size) != fl->ifl_credits)
2178 		return (ENOBUFS);
2179 	/*
2180 	 * handle failure
2181 	 */
2182 	MPASS(rxq != NULL);
2183 	MPASS(fl->ifl_ifdi != NULL);
2184 	bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2185 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2186 	return (0);
2187 }
2188 
2189 /*********************************************************************
2190  *
2191  *  Free receive ring data structures
2192  *
2193  **********************************************************************/
2194 static void
2195 iflib_rx_sds_free(iflib_rxq_t rxq)
2196 {
2197 	iflib_fl_t fl;
2198 	int i, j;
2199 
2200 	if (rxq->ifr_fl != NULL) {
2201 		for (i = 0; i < rxq->ifr_nfl; i++) {
2202 			fl = &rxq->ifr_fl[i];
2203 			if (fl->ifl_buf_tag != NULL) {
2204 				if (fl->ifl_sds.ifsd_map != NULL) {
2205 					for (j = 0; j < fl->ifl_size; j++) {
2206 						bus_dmamap_sync(
2207 						    fl->ifl_buf_tag,
2208 						    fl->ifl_sds.ifsd_map[j],
2209 						    BUS_DMASYNC_POSTREAD);
2210 						bus_dmamap_unload(
2211 						    fl->ifl_buf_tag,
2212 						    fl->ifl_sds.ifsd_map[j]);
2213 						bus_dmamap_destroy(
2214 						    fl->ifl_buf_tag,
2215 						    fl->ifl_sds.ifsd_map[j]);
2216 					}
2217 				}
2218 				bus_dma_tag_destroy(fl->ifl_buf_tag);
2219 				fl->ifl_buf_tag = NULL;
2220 			}
2221 			free(fl->ifl_sds.ifsd_m, M_IFLIB);
2222 			free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2223 			free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2224 			free(fl->ifl_sds.ifsd_map, M_IFLIB);
2225 			fl->ifl_sds.ifsd_m = NULL;
2226 			fl->ifl_sds.ifsd_cl = NULL;
2227 			fl->ifl_sds.ifsd_ba = NULL;
2228 			fl->ifl_sds.ifsd_map = NULL;
2229 		}
2230 		free(rxq->ifr_fl, M_IFLIB);
2231 		rxq->ifr_fl = NULL;
2232 		free(rxq->ifr_ifdi, M_IFLIB);
2233 		rxq->ifr_ifdi = NULL;
2234 		rxq->ifr_cq_cidx = 0;
2235 	}
2236 }
2237 
2238 /*
2239  * Timer routine
2240  */
2241 static void
2242 iflib_timer(void *arg)
2243 {
2244 	iflib_txq_t txq = arg;
2245 	if_ctx_t ctx = txq->ift_ctx;
2246 	if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2247 	uint64_t this_tick = ticks;
2248 	uint32_t reset_on = hz / 2;
2249 
2250 	if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2251 		return;
2252 
2253 	/*
2254 	** Check on the state of the TX queue(s), this
2255 	** can be done without the lock because its RO
2256 	** and the HUNG state will be static if set.
2257 	*/
2258 	if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2259 		txq->ift_last_timer_tick = this_tick;
2260 		IFDI_TIMER(ctx, txq->ift_id);
2261 		if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2262 		    ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2263 		     (sctx->isc_pause_frames == 0)))
2264 			goto hung;
2265 
2266 		if (txq->ift_qstatus != IFLIB_QUEUE_IDLE &&
2267 		    ifmp_ring_is_stalled(txq->ift_br)) {
2268 			KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down"));
2269 			txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2270 		}
2271 		txq->ift_cleaned_prev = txq->ift_cleaned;
2272 	}
2273 #ifdef DEV_NETMAP
2274 	if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2275 		iflib_netmap_timer_adjust(ctx, txq, &reset_on);
2276 #endif
2277 	/* handle any laggards */
2278 	if (txq->ift_db_pending)
2279 		GROUPTASK_ENQUEUE(&txq->ift_task);
2280 
2281 	sctx->isc_pause_frames = 0;
2282 	if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2283 		callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2284 	return;
2285 
2286  hung:
2287 	device_printf(ctx->ifc_dev,
2288 	    "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2289 	    txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2290 	STATE_LOCK(ctx);
2291 	if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2292 	ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2293 	iflib_admin_intr_deferred(ctx);
2294 	STATE_UNLOCK(ctx);
2295 }
2296 
2297 static void
2298 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2299 {
2300 	if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2301 
2302 	/*
2303 	 * XXX don't set the max_frame_size to larger
2304 	 * than the hardware can handle
2305 	 */
2306 	if (sctx->isc_max_frame_size <= MCLBYTES)
2307 		ctx->ifc_rx_mbuf_sz = MCLBYTES;
2308 	else
2309 		ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE;
2310 }
2311 
2312 uint32_t
2313 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2314 {
2315 
2316 	return (ctx->ifc_rx_mbuf_sz);
2317 }
2318 
2319 static void
2320 iflib_init_locked(if_ctx_t ctx)
2321 {
2322 	if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2323 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2324 	if_t ifp = ctx->ifc_ifp;
2325 	iflib_fl_t fl;
2326 	iflib_txq_t txq;
2327 	iflib_rxq_t rxq;
2328 	int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2329 
2330 	if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2331 	IFDI_INTR_DISABLE(ctx);
2332 
2333 	tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2334 	tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2335 	/* Set hardware offload abilities */
2336 	if_clearhwassist(ifp);
2337 	if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2338 		if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2339 	if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2340 		if_sethwassistbits(ifp,  tx_ip6_csum_flags, 0);
2341 	if (if_getcapenable(ifp) & IFCAP_TSO4)
2342 		if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2343 	if (if_getcapenable(ifp) & IFCAP_TSO6)
2344 		if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2345 
2346 	for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2347 		CALLOUT_LOCK(txq);
2348 		callout_stop(&txq->ift_timer);
2349 		CALLOUT_UNLOCK(txq);
2350 		iflib_netmap_txq_init(ctx, txq);
2351 	}
2352 
2353 	/*
2354 	 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2355 	 * that drivers can use the value when setting up the hardware receive
2356 	 * buffers.
2357 	 */
2358 	iflib_calc_rx_mbuf_sz(ctx);
2359 
2360 #ifdef INVARIANTS
2361 	i = if_getdrvflags(ifp);
2362 #endif
2363 	IFDI_INIT(ctx);
2364 	MPASS(if_getdrvflags(ifp) == i);
2365 	for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2366 		/* XXX this should really be done on a per-queue basis */
2367 		if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2368 			MPASS(rxq->ifr_id == i);
2369 			iflib_netmap_rxq_init(ctx, rxq);
2370 			continue;
2371 		}
2372 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2373 			if (iflib_fl_setup(fl)) {
2374 				device_printf(ctx->ifc_dev,
2375 				    "setting up free list %d failed - "
2376 				    "check cluster settings\n", j);
2377 				goto done;
2378 			}
2379 		}
2380 	}
2381 done:
2382 	if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2383 	IFDI_INTR_ENABLE(ctx);
2384 	txq = ctx->ifc_txqs;
2385 	for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2386 		callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2387 			txq->ift_timer.c_cpu);
2388 }
2389 
2390 static int
2391 iflib_media_change(if_t ifp)
2392 {
2393 	if_ctx_t ctx = if_getsoftc(ifp);
2394 	int err;
2395 
2396 	CTX_LOCK(ctx);
2397 	if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2398 		iflib_init_locked(ctx);
2399 	CTX_UNLOCK(ctx);
2400 	return (err);
2401 }
2402 
2403 static void
2404 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2405 {
2406 	if_ctx_t ctx = if_getsoftc(ifp);
2407 
2408 	CTX_LOCK(ctx);
2409 	IFDI_UPDATE_ADMIN_STATUS(ctx);
2410 	IFDI_MEDIA_STATUS(ctx, ifmr);
2411 	CTX_UNLOCK(ctx);
2412 }
2413 
2414 void
2415 iflib_stop(if_ctx_t ctx)
2416 {
2417 	iflib_txq_t txq = ctx->ifc_txqs;
2418 	iflib_rxq_t rxq = ctx->ifc_rxqs;
2419 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2420 	if_shared_ctx_t sctx = ctx->ifc_sctx;
2421 	iflib_dma_info_t di;
2422 	iflib_fl_t fl;
2423 	int i, j;
2424 
2425 	/* Tell the stack that the interface is no longer active */
2426 	if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2427 
2428 	IFDI_INTR_DISABLE(ctx);
2429 	DELAY(1000);
2430 	IFDI_STOP(ctx);
2431 	DELAY(1000);
2432 
2433 	iflib_debug_reset();
2434 	/* Wait for current tx queue users to exit to disarm watchdog timer. */
2435 	for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2436 		/* make sure all transmitters have completed before proceeding XXX */
2437 
2438 		CALLOUT_LOCK(txq);
2439 		callout_stop(&txq->ift_timer);
2440 		CALLOUT_UNLOCK(txq);
2441 
2442 		/* clean any enqueued buffers */
2443 		iflib_ifmp_purge(txq);
2444 		/* Free any existing tx buffers. */
2445 		for (j = 0; j < txq->ift_size; j++) {
2446 			iflib_txsd_free(ctx, txq, j);
2447 		}
2448 		txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2449 		txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2450 		txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2451 		txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2452 		txq->ift_pullups = 0;
2453 		ifmp_ring_reset_stats(txq->ift_br);
2454 		for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2455 			bzero((void *)di->idi_vaddr, di->idi_size);
2456 	}
2457 	for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2458 		/* make sure all transmitters have completed before proceeding XXX */
2459 
2460 		rxq->ifr_cq_cidx = 0;
2461 		for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2462 			bzero((void *)di->idi_vaddr, di->idi_size);
2463 		/* also resets the free lists pidx/cidx */
2464 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2465 			iflib_fl_bufs_free(fl);
2466 	}
2467 }
2468 
2469 static inline caddr_t
2470 calc_next_rxd(iflib_fl_t fl, int cidx)
2471 {
2472 	qidx_t size;
2473 	int nrxd;
2474 	caddr_t start, end, cur, next;
2475 
2476 	nrxd = fl->ifl_size;
2477 	size = fl->ifl_rxd_size;
2478 	start = fl->ifl_ifdi->idi_vaddr;
2479 
2480 	if (__predict_false(size == 0))
2481 		return (start);
2482 	cur = start + size*cidx;
2483 	end = start + size*nrxd;
2484 	next = CACHE_PTR_NEXT(cur);
2485 	return (next < end ? next : start);
2486 }
2487 
2488 static inline void
2489 prefetch_pkts(iflib_fl_t fl, int cidx)
2490 {
2491 	int nextptr;
2492 	int nrxd = fl->ifl_size;
2493 	caddr_t next_rxd;
2494 
2495 
2496 	nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2497 	prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2498 	prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2499 	next_rxd = calc_next_rxd(fl, cidx);
2500 	prefetch(next_rxd);
2501 	prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2502 	prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2503 	prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2504 	prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2505 	prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2506 	prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2507 	prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2508 	prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2509 }
2510 
2511 static struct mbuf *
2512 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2513     int *pf_rv, if_rxd_info_t ri)
2514 {
2515 	bus_dmamap_t map;
2516 	iflib_fl_t fl;
2517 	caddr_t payload;
2518 	struct mbuf *m;
2519 	int flid, cidx, len, next;
2520 
2521 	map = NULL;
2522 	flid = irf->irf_flid;
2523 	cidx = irf->irf_idx;
2524 	fl = &rxq->ifr_fl[flid];
2525 	sd->ifsd_fl = fl;
2526 	sd->ifsd_cidx = cidx;
2527 	m = fl->ifl_sds.ifsd_m[cidx];
2528 	sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2529 	fl->ifl_credits--;
2530 #if MEMORY_LOGGING
2531 	fl->ifl_m_dequeued++;
2532 #endif
2533 	if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2534 		prefetch_pkts(fl, cidx);
2535 	next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2536 	prefetch(&fl->ifl_sds.ifsd_map[next]);
2537 	map = fl->ifl_sds.ifsd_map[cidx];
2538 	next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1);
2539 
2540 	/* not valid assert if bxe really does SGE from non-contiguous elements */
2541 	MPASS(fl->ifl_cidx == cidx);
2542 	bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2543 
2544 	if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL) {
2545 		payload  = *sd->ifsd_cl;
2546 		payload +=  ri->iri_pad;
2547 		len = ri->iri_len - ri->iri_pad;
2548 		*pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp,
2549 		    len | PFIL_MEMPTR | PFIL_IN, NULL);
2550 		switch (*pf_rv) {
2551 		case PFIL_DROPPED:
2552 		case PFIL_CONSUMED:
2553 			/*
2554 			 * The filter ate it.  Everything is recycled.
2555 			 */
2556 			m = NULL;
2557 			unload = 0;
2558 			break;
2559 		case PFIL_REALLOCED:
2560 			/*
2561 			 * The filter copied it.  Everything is recycled.
2562 			 */
2563 			m = pfil_mem2mbuf(payload);
2564 			unload = 0;
2565 			break;
2566 		case PFIL_PASS:
2567 			/*
2568 			 * Filter said it was OK, so receive like
2569 			 * normal
2570 			 */
2571 			fl->ifl_sds.ifsd_m[cidx] = NULL;
2572 			break;
2573 		default:
2574 			MPASS(0);
2575 		}
2576 	} else {
2577 		fl->ifl_sds.ifsd_m[cidx] = NULL;
2578 		*pf_rv = PFIL_PASS;
2579 	}
2580 
2581 	if (unload)
2582 		bus_dmamap_unload(fl->ifl_buf_tag, map);
2583 	fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2584 	if (__predict_false(fl->ifl_cidx == 0))
2585 		fl->ifl_gen = 0;
2586 	bit_clear(fl->ifl_rx_bitmap, cidx);
2587 	return (m);
2588 }
2589 
2590 static struct mbuf *
2591 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2592 {
2593 	struct mbuf *m, *mh, *mt;
2594 	caddr_t cl;
2595 	int  *pf_rv_ptr, flags, i, padlen;
2596 	bool consumed;
2597 
2598 	i = 0;
2599 	mh = NULL;
2600 	consumed = false;
2601 	*pf_rv = PFIL_PASS;
2602 	pf_rv_ptr = pf_rv;
2603 	do {
2604 		m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2605 		    pf_rv_ptr, ri);
2606 
2607 		MPASS(*sd->ifsd_cl != NULL);
2608 
2609 		/*
2610 		 * Exclude zero-length frags & frags from
2611 		 * packets the filter has consumed or dropped
2612 		 */
2613 		if (ri->iri_frags[i].irf_len == 0 || consumed ||
2614 		    *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2615 			if (mh == NULL) {
2616 				/* everything saved here */
2617 				consumed = true;
2618 				pf_rv_ptr = NULL;
2619 				continue;
2620 			}
2621 			/* XXX we can save the cluster here, but not the mbuf */
2622 			m_init(m, M_NOWAIT, MT_DATA, 0);
2623 			m_free(m);
2624 			continue;
2625 		}
2626 		if (mh == NULL) {
2627 			flags = M_PKTHDR|M_EXT;
2628 			mh = mt = m;
2629 			padlen = ri->iri_pad;
2630 		} else {
2631 			flags = M_EXT;
2632 			mt->m_next = m;
2633 			mt = m;
2634 			/* assuming padding is only on the first fragment */
2635 			padlen = 0;
2636 		}
2637 		cl = *sd->ifsd_cl;
2638 		*sd->ifsd_cl = NULL;
2639 
2640 		/* Can these two be made one ? */
2641 		m_init(m, M_NOWAIT, MT_DATA, flags);
2642 		m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2643 		/*
2644 		 * These must follow m_init and m_cljset
2645 		 */
2646 		m->m_data += padlen;
2647 		ri->iri_len -= padlen;
2648 		m->m_len = ri->iri_frags[i].irf_len;
2649 	} while (++i < ri->iri_nfrags);
2650 
2651 	return (mh);
2652 }
2653 
2654 /*
2655  * Process one software descriptor
2656  */
2657 static struct mbuf *
2658 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2659 {
2660 	struct if_rxsd sd;
2661 	struct mbuf *m;
2662 	int pf_rv;
2663 
2664 	/* should I merge this back in now that the two paths are basically duplicated? */
2665 	if (ri->iri_nfrags == 1 &&
2666 	    ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2667 		m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2668 		    &pf_rv, ri);
2669 		if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2670 			return (m);
2671 		if (pf_rv == PFIL_PASS) {
2672 			m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2673 #ifndef __NO_STRICT_ALIGNMENT
2674 			if (!IP_ALIGNED(m))
2675 				m->m_data += 2;
2676 #endif
2677 			memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2678 			m->m_len = ri->iri_frags[0].irf_len;
2679 		}
2680 	} else {
2681 		m = assemble_segments(rxq, ri, &sd, &pf_rv);
2682 		if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2683 			return (m);
2684 	}
2685 	m->m_pkthdr.len = ri->iri_len;
2686 	m->m_pkthdr.rcvif = ri->iri_ifp;
2687 	m->m_flags |= ri->iri_flags;
2688 	m->m_pkthdr.ether_vtag = ri->iri_vtag;
2689 	m->m_pkthdr.flowid = ri->iri_flowid;
2690 	M_HASHTYPE_SET(m, ri->iri_rsstype);
2691 	m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2692 	m->m_pkthdr.csum_data = ri->iri_csum_data;
2693 	return (m);
2694 }
2695 
2696 #if defined(INET6) || defined(INET)
2697 static void
2698 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2699 {
2700 	CURVNET_SET(lc->ifp->if_vnet);
2701 #if defined(INET6)
2702 	*v6 = V_ip6_forwarding;
2703 #endif
2704 #if defined(INET)
2705 	*v4 = V_ipforwarding;
2706 #endif
2707 	CURVNET_RESTORE();
2708 }
2709 
2710 /*
2711  * Returns true if it's possible this packet could be LROed.
2712  * if it returns false, it is guaranteed that tcp_lro_rx()
2713  * would not return zero.
2714  */
2715 static bool
2716 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2717 {
2718 	struct ether_header *eh;
2719 
2720 	eh = mtod(m, struct ether_header *);
2721 	switch (eh->ether_type) {
2722 #if defined(INET6)
2723 		case htons(ETHERTYPE_IPV6):
2724 			return (!v6_forwarding);
2725 #endif
2726 #if defined (INET)
2727 		case htons(ETHERTYPE_IP):
2728 			return (!v4_forwarding);
2729 #endif
2730 	}
2731 
2732 	return false;
2733 }
2734 #else
2735 static void
2736 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2737 {
2738 }
2739 #endif
2740 
2741 static bool
2742 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2743 {
2744 	if_t ifp;
2745 	if_ctx_t ctx = rxq->ifr_ctx;
2746 	if_shared_ctx_t sctx = ctx->ifc_sctx;
2747 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2748 	int avail, i;
2749 	qidx_t *cidxp;
2750 	struct if_rxd_info ri;
2751 	int err, budget_left, rx_bytes, rx_pkts;
2752 	iflib_fl_t fl;
2753 	int lro_enabled;
2754 	bool v4_forwarding, v6_forwarding, lro_possible;
2755 
2756 	/*
2757 	 * XXX early demux data packets so that if_input processing only handles
2758 	 * acks in interrupt context
2759 	 */
2760 	struct mbuf *m, *mh, *mt, *mf;
2761 
2762 	NET_EPOCH_ASSERT();
2763 
2764 	lro_possible = v4_forwarding = v6_forwarding = false;
2765 	ifp = ctx->ifc_ifp;
2766 	mh = mt = NULL;
2767 	MPASS(budget > 0);
2768 	rx_pkts	= rx_bytes = 0;
2769 	if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2770 		cidxp = &rxq->ifr_cq_cidx;
2771 	else
2772 		cidxp = &rxq->ifr_fl[0].ifl_cidx;
2773 	if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2774 		for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2775 			__iflib_fl_refill_lt(ctx, fl, budget + 8);
2776 		DBG_COUNTER_INC(rx_unavail);
2777 		return (false);
2778 	}
2779 
2780 	/* pfil needs the vnet to be set */
2781 	CURVNET_SET_QUIET(ifp->if_vnet);
2782 	for (budget_left = budget; budget_left > 0 && avail > 0;) {
2783 		if (__predict_false(!CTX_ACTIVE(ctx))) {
2784 			DBG_COUNTER_INC(rx_ctx_inactive);
2785 			break;
2786 		}
2787 		/*
2788 		 * Reset client set fields to their default values
2789 		 */
2790 		rxd_info_zero(&ri);
2791 		ri.iri_qsidx = rxq->ifr_id;
2792 		ri.iri_cidx = *cidxp;
2793 		ri.iri_ifp = ifp;
2794 		ri.iri_frags = rxq->ifr_frags;
2795 		err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2796 
2797 		if (err)
2798 			goto err;
2799 		rx_pkts += 1;
2800 		rx_bytes += ri.iri_len;
2801 		if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2802 			*cidxp = ri.iri_cidx;
2803 			/* Update our consumer index */
2804 			/* XXX NB: shurd - check if this is still safe */
2805 			while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
2806 				rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2807 			/* was this only a completion queue message? */
2808 			if (__predict_false(ri.iri_nfrags == 0))
2809 				continue;
2810 		}
2811 		MPASS(ri.iri_nfrags != 0);
2812 		MPASS(ri.iri_len != 0);
2813 
2814 		/* will advance the cidx on the corresponding free lists */
2815 		m = iflib_rxd_pkt_get(rxq, &ri);
2816 		avail--;
2817 		budget_left--;
2818 		if (avail == 0 && budget_left)
2819 			avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2820 
2821 		if (__predict_false(m == NULL))
2822 			continue;
2823 
2824 		/* imm_pkt: -- cxgb */
2825 		if (mh == NULL)
2826 			mh = mt = m;
2827 		else {
2828 			mt->m_nextpkt = m;
2829 			mt = m;
2830 		}
2831 	}
2832 	CURVNET_RESTORE();
2833 	/* make sure that we can refill faster than drain */
2834 	for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2835 		__iflib_fl_refill_lt(ctx, fl, budget + 8);
2836 
2837 	lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2838 	if (lro_enabled)
2839 		iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2840 	mt = mf = NULL;
2841 	while (mh != NULL) {
2842 		m = mh;
2843 		mh = mh->m_nextpkt;
2844 		m->m_nextpkt = NULL;
2845 #ifndef __NO_STRICT_ALIGNMENT
2846 		if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2847 			continue;
2848 #endif
2849 		rx_bytes += m->m_pkthdr.len;
2850 		rx_pkts++;
2851 #if defined(INET6) || defined(INET)
2852 		if (lro_enabled) {
2853 			if (!lro_possible) {
2854 				lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2855 				if (lro_possible && mf != NULL) {
2856 					ifp->if_input(ifp, mf);
2857 					DBG_COUNTER_INC(rx_if_input);
2858 					mt = mf = NULL;
2859 				}
2860 			}
2861 			if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2862 			    (CSUM_L4_CALC|CSUM_L4_VALID)) {
2863 				if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2864 					continue;
2865 			}
2866 		}
2867 #endif
2868 		if (lro_possible) {
2869 			ifp->if_input(ifp, m);
2870 			DBG_COUNTER_INC(rx_if_input);
2871 			continue;
2872 		}
2873 
2874 		if (mf == NULL)
2875 			mf = m;
2876 		if (mt != NULL)
2877 			mt->m_nextpkt = m;
2878 		mt = m;
2879 	}
2880 	if (mf != NULL) {
2881 		ifp->if_input(ifp, mf);
2882 		DBG_COUNTER_INC(rx_if_input);
2883 	}
2884 
2885 	if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2886 	if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2887 
2888 	/*
2889 	 * Flush any outstanding LRO work
2890 	 */
2891 #if defined(INET6) || defined(INET)
2892 	tcp_lro_flush_all(&rxq->ifr_lc);
2893 #endif
2894 	if (avail)
2895 		return true;
2896 	return (iflib_rxd_avail(ctx, rxq, *cidxp, 1));
2897 err:
2898 	STATE_LOCK(ctx);
2899 	ctx->ifc_flags |= IFC_DO_RESET;
2900 	iflib_admin_intr_deferred(ctx);
2901 	STATE_UNLOCK(ctx);
2902 	return (false);
2903 }
2904 
2905 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2906 static inline qidx_t
2907 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2908 {
2909 	qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2910 	qidx_t minthresh = txq->ift_size / 8;
2911 	if (in_use > 4*minthresh)
2912 		return (notify_count);
2913 	if (in_use > 2*minthresh)
2914 		return (notify_count >> 1);
2915 	if (in_use > minthresh)
2916 		return (notify_count >> 3);
2917 	return (0);
2918 }
2919 
2920 static inline qidx_t
2921 txq_max_rs_deferred(iflib_txq_t txq)
2922 {
2923 	qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2924 	qidx_t minthresh = txq->ift_size / 8;
2925 	if (txq->ift_in_use > 4*minthresh)
2926 		return (notify_count);
2927 	if (txq->ift_in_use > 2*minthresh)
2928 		return (notify_count >> 1);
2929 	if (txq->ift_in_use > minthresh)
2930 		return (notify_count >> 2);
2931 	return (2);
2932 }
2933 
2934 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2935 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2936 
2937 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2938 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2939 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2940 
2941 /* forward compatibility for cxgb */
2942 #define FIRST_QSET(ctx) 0
2943 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2944 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2945 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2946 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2947 
2948 /* XXX we should be setting this to something other than zero */
2949 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2950 #define	MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2951     (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2952 
2953 static inline bool
2954 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2955 {
2956 	qidx_t dbval, max;
2957 	bool rang;
2958 
2959 	rang = false;
2960 	max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2961 	if (ring || txq->ift_db_pending >= max) {
2962 		dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2963 		bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
2964 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2965 		ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2966 		txq->ift_db_pending = txq->ift_npending = 0;
2967 		rang = true;
2968 	}
2969 	return (rang);
2970 }
2971 
2972 #ifdef PKT_DEBUG
2973 static void
2974 print_pkt(if_pkt_info_t pi)
2975 {
2976 	printf("pi len:  %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
2977 	       pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
2978 	printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
2979 	       pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
2980 	printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
2981 	       pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
2982 }
2983 #endif
2984 
2985 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
2986 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
2987 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
2988 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
2989 
2990 static int
2991 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
2992 {
2993 	if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
2994 	struct ether_vlan_header *eh;
2995 	struct mbuf *m;
2996 
2997 	m = *mp;
2998 	if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
2999 	    M_WRITABLE(m) == 0) {
3000 		if ((m = m_dup(m, M_NOWAIT)) == NULL) {
3001 			return (ENOMEM);
3002 		} else {
3003 			m_freem(*mp);
3004 			DBG_COUNTER_INC(tx_frees);
3005 			*mp = m;
3006 		}
3007 	}
3008 
3009 	/*
3010 	 * Determine where frame payload starts.
3011 	 * Jump over vlan headers if already present,
3012 	 * helpful for QinQ too.
3013 	 */
3014 	if (__predict_false(m->m_len < sizeof(*eh))) {
3015 		txq->ift_pullups++;
3016 		if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3017 			return (ENOMEM);
3018 	}
3019 	eh = mtod(m, struct ether_vlan_header *);
3020 	if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3021 		pi->ipi_etype = ntohs(eh->evl_proto);
3022 		pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3023 	} else {
3024 		pi->ipi_etype = ntohs(eh->evl_encap_proto);
3025 		pi->ipi_ehdrlen = ETHER_HDR_LEN;
3026 	}
3027 
3028 	switch (pi->ipi_etype) {
3029 #ifdef INET
3030 	case ETHERTYPE_IP:
3031 	{
3032 		struct mbuf *n;
3033 		struct ip *ip = NULL;
3034 		struct tcphdr *th = NULL;
3035 		int minthlen;
3036 
3037 		minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3038 		if (__predict_false(m->m_len < minthlen)) {
3039 			/*
3040 			 * if this code bloat is causing too much of a hit
3041 			 * move it to a separate function and mark it noinline
3042 			 */
3043 			if (m->m_len == pi->ipi_ehdrlen) {
3044 				n = m->m_next;
3045 				MPASS(n);
3046 				if (n->m_len >= sizeof(*ip))  {
3047 					ip = (struct ip *)n->m_data;
3048 					if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3049 						th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3050 				} else {
3051 					txq->ift_pullups++;
3052 					if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3053 						return (ENOMEM);
3054 					ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3055 				}
3056 			} else {
3057 				txq->ift_pullups++;
3058 				if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3059 					return (ENOMEM);
3060 				ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3061 				if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3062 					th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3063 			}
3064 		} else {
3065 			ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3066 			if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3067 				th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3068 		}
3069 		pi->ipi_ip_hlen = ip->ip_hl << 2;
3070 		pi->ipi_ipproto = ip->ip_p;
3071 		pi->ipi_flags |= IPI_TX_IPV4;
3072 
3073 		/* TCP checksum offload may require TCP header length */
3074 		if (IS_TX_OFFLOAD4(pi)) {
3075 			if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3076 				if (__predict_false(th == NULL)) {
3077 					txq->ift_pullups++;
3078 					if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3079 						return (ENOMEM);
3080 					th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3081 				}
3082 				pi->ipi_tcp_hflags = th->th_flags;
3083 				pi->ipi_tcp_hlen = th->th_off << 2;
3084 				pi->ipi_tcp_seq = th->th_seq;
3085 			}
3086 			if (IS_TSO4(pi)) {
3087 				if (__predict_false(ip->ip_p != IPPROTO_TCP))
3088 					return (ENXIO);
3089 				/*
3090 				 * TSO always requires hardware checksum offload.
3091 				 */
3092 				pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3093 				th->th_sum = in_pseudo(ip->ip_src.s_addr,
3094 						       ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3095 				pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3096 				if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3097 					ip->ip_sum = 0;
3098 					ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3099 				}
3100 			}
3101 		}
3102 		if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3103                        ip->ip_sum = 0;
3104 
3105 		break;
3106 	}
3107 #endif
3108 #ifdef INET6
3109 	case ETHERTYPE_IPV6:
3110 	{
3111 		struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3112 		struct tcphdr *th;
3113 		pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3114 
3115 		if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3116 			txq->ift_pullups++;
3117 			if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3118 				return (ENOMEM);
3119 		}
3120 		th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3121 
3122 		/* XXX-BZ this will go badly in case of ext hdrs. */
3123 		pi->ipi_ipproto = ip6->ip6_nxt;
3124 		pi->ipi_flags |= IPI_TX_IPV6;
3125 
3126 		/* TCP checksum offload may require TCP header length */
3127 		if (IS_TX_OFFLOAD6(pi)) {
3128 			if (pi->ipi_ipproto == IPPROTO_TCP) {
3129 				if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3130 					txq->ift_pullups++;
3131 					if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3132 						return (ENOMEM);
3133 				}
3134 				pi->ipi_tcp_hflags = th->th_flags;
3135 				pi->ipi_tcp_hlen = th->th_off << 2;
3136 				pi->ipi_tcp_seq = th->th_seq;
3137 			}
3138 			if (IS_TSO6(pi)) {
3139 				if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3140 					return (ENXIO);
3141 				/*
3142 				 * TSO always requires hardware checksum offload.
3143 				 */
3144 				pi->ipi_csum_flags |= CSUM_IP6_TCP;
3145 				th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3146 				pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3147 			}
3148 		}
3149 		break;
3150 	}
3151 #endif
3152 	default:
3153 		pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3154 		pi->ipi_ip_hlen = 0;
3155 		break;
3156 	}
3157 	*mp = m;
3158 
3159 	return (0);
3160 }
3161 
3162 /*
3163  * If dodgy hardware rejects the scatter gather chain we've handed it
3164  * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3165  * m_defrag'd mbufs
3166  */
3167 static __noinline struct mbuf *
3168 iflib_remove_mbuf(iflib_txq_t txq)
3169 {
3170 	int ntxd, pidx;
3171 	struct mbuf *m, **ifsd_m;
3172 
3173 	ifsd_m = txq->ift_sds.ifsd_m;
3174 	ntxd = txq->ift_size;
3175 	pidx = txq->ift_pidx & (ntxd - 1);
3176 	ifsd_m = txq->ift_sds.ifsd_m;
3177 	m = ifsd_m[pidx];
3178 	ifsd_m[pidx] = NULL;
3179 	bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3180 	if (txq->ift_sds.ifsd_tso_map != NULL)
3181 		bus_dmamap_unload(txq->ift_tso_buf_tag,
3182 		    txq->ift_sds.ifsd_tso_map[pidx]);
3183 #if MEMORY_LOGGING
3184 	txq->ift_dequeued++;
3185 #endif
3186 	return (m);
3187 }
3188 
3189 static inline caddr_t
3190 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3191 {
3192 	qidx_t size;
3193 	int ntxd;
3194 	caddr_t start, end, cur, next;
3195 
3196 	ntxd = txq->ift_size;
3197 	size = txq->ift_txd_size[qid];
3198 	start = txq->ift_ifdi[qid].idi_vaddr;
3199 
3200 	if (__predict_false(size == 0))
3201 		return (start);
3202 	cur = start + size*cidx;
3203 	end = start + size*ntxd;
3204 	next = CACHE_PTR_NEXT(cur);
3205 	return (next < end ? next : start);
3206 }
3207 
3208 /*
3209  * Pad an mbuf to ensure a minimum ethernet frame size.
3210  * min_frame_size is the frame size (less CRC) to pad the mbuf to
3211  */
3212 static __noinline int
3213 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3214 {
3215 	/*
3216 	 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3217 	 * and ARP message is the smallest common payload I can think of
3218 	 */
3219 	static char pad[18];	/* just zeros */
3220 	int n;
3221 	struct mbuf *new_head;
3222 
3223 	if (!M_WRITABLE(*m_head)) {
3224 		new_head = m_dup(*m_head, M_NOWAIT);
3225 		if (new_head == NULL) {
3226 			m_freem(*m_head);
3227 			device_printf(dev, "cannot pad short frame, m_dup() failed");
3228 			DBG_COUNTER_INC(encap_pad_mbuf_fail);
3229 			DBG_COUNTER_INC(tx_frees);
3230 			return ENOMEM;
3231 		}
3232 		m_freem(*m_head);
3233 		*m_head = new_head;
3234 	}
3235 
3236 	for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3237 	     n > 0; n -= sizeof(pad))
3238 		if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3239 			break;
3240 
3241 	if (n > 0) {
3242 		m_freem(*m_head);
3243 		device_printf(dev, "cannot pad short frame\n");
3244 		DBG_COUNTER_INC(encap_pad_mbuf_fail);
3245 		DBG_COUNTER_INC(tx_frees);
3246 		return (ENOBUFS);
3247 	}
3248 
3249 	return 0;
3250 }
3251 
3252 static int
3253 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3254 {
3255 	if_ctx_t		ctx;
3256 	if_shared_ctx_t		sctx;
3257 	if_softc_ctx_t		scctx;
3258 	bus_dma_tag_t		buf_tag;
3259 	bus_dma_segment_t	*segs;
3260 	struct mbuf		*m_head, **ifsd_m;
3261 	void			*next_txd;
3262 	bus_dmamap_t		map;
3263 	struct if_pkt_info	pi;
3264 	int remap = 0;
3265 	int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3266 
3267 	ctx = txq->ift_ctx;
3268 	sctx = ctx->ifc_sctx;
3269 	scctx = &ctx->ifc_softc_ctx;
3270 	segs = txq->ift_segs;
3271 	ntxd = txq->ift_size;
3272 	m_head = *m_headp;
3273 	map = NULL;
3274 
3275 	/*
3276 	 * If we're doing TSO the next descriptor to clean may be quite far ahead
3277 	 */
3278 	cidx = txq->ift_cidx;
3279 	pidx = txq->ift_pidx;
3280 	if (ctx->ifc_flags & IFC_PREFETCH) {
3281 		next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3282 		if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3283 			next_txd = calc_next_txd(txq, cidx, 0);
3284 			prefetch(next_txd);
3285 		}
3286 
3287 		/* prefetch the next cache line of mbuf pointers and flags */
3288 		prefetch(&txq->ift_sds.ifsd_m[next]);
3289 		prefetch(&txq->ift_sds.ifsd_map[next]);
3290 		next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3291 	}
3292 	map = txq->ift_sds.ifsd_map[pidx];
3293 	ifsd_m = txq->ift_sds.ifsd_m;
3294 
3295 	if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3296 		buf_tag = txq->ift_tso_buf_tag;
3297 		max_segs = scctx->isc_tx_tso_segments_max;
3298 		map = txq->ift_sds.ifsd_tso_map[pidx];
3299 		MPASS(buf_tag != NULL);
3300 		MPASS(max_segs > 0);
3301 	} else {
3302 		buf_tag = txq->ift_buf_tag;
3303 		max_segs = scctx->isc_tx_nsegments;
3304 		map = txq->ift_sds.ifsd_map[pidx];
3305 	}
3306 	if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3307 	    __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3308 		err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3309 		if (err) {
3310 			DBG_COUNTER_INC(encap_txd_encap_fail);
3311 			return err;
3312 		}
3313 	}
3314 	m_head = *m_headp;
3315 
3316 	pkt_info_zero(&pi);
3317 	pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3318 	pi.ipi_pidx = pidx;
3319 	pi.ipi_qsidx = txq->ift_id;
3320 	pi.ipi_len = m_head->m_pkthdr.len;
3321 	pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3322 	pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3323 
3324 	/* deliberate bitwise OR to make one condition */
3325 	if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3326 		if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3327 			DBG_COUNTER_INC(encap_txd_encap_fail);
3328 			return (err);
3329 		}
3330 		m_head = *m_headp;
3331 	}
3332 
3333 retry:
3334 	err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3335 	    BUS_DMA_NOWAIT);
3336 defrag:
3337 	if (__predict_false(err)) {
3338 		switch (err) {
3339 		case EFBIG:
3340 			/* try collapse once and defrag once */
3341 			if (remap == 0) {
3342 				m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3343 				/* try defrag if collapsing fails */
3344 				if (m_head == NULL)
3345 					remap++;
3346 			}
3347 			if (remap == 1) {
3348 				txq->ift_mbuf_defrag++;
3349 				m_head = m_defrag(*m_headp, M_NOWAIT);
3350 			}
3351 			/*
3352 			 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3353 			 * failed to map an mbuf that was run through m_defrag
3354 			 */
3355 			MPASS(remap <= 1);
3356 			if (__predict_false(m_head == NULL || remap > 1))
3357 				goto defrag_failed;
3358 			remap++;
3359 			*m_headp = m_head;
3360 			goto retry;
3361 			break;
3362 		case ENOMEM:
3363 			txq->ift_no_tx_dma_setup++;
3364 			break;
3365 		default:
3366 			txq->ift_no_tx_dma_setup++;
3367 			m_freem(*m_headp);
3368 			DBG_COUNTER_INC(tx_frees);
3369 			*m_headp = NULL;
3370 			break;
3371 		}
3372 		txq->ift_map_failed++;
3373 		DBG_COUNTER_INC(encap_load_mbuf_fail);
3374 		DBG_COUNTER_INC(encap_txd_encap_fail);
3375 		return (err);
3376 	}
3377 	ifsd_m[pidx] = m_head;
3378 	/*
3379 	 * XXX assumes a 1 to 1 relationship between segments and
3380 	 *        descriptors - this does not hold true on all drivers, e.g.
3381 	 *        cxgb
3382 	 */
3383 	if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3384 		txq->ift_no_desc_avail++;
3385 		bus_dmamap_unload(buf_tag, map);
3386 		DBG_COUNTER_INC(encap_txq_avail_fail);
3387 		DBG_COUNTER_INC(encap_txd_encap_fail);
3388 		if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3389 			GROUPTASK_ENQUEUE(&txq->ift_task);
3390 		return (ENOBUFS);
3391 	}
3392 	/*
3393 	 * On Intel cards we can greatly reduce the number of TX interrupts
3394 	 * we see by only setting report status on every Nth descriptor.
3395 	 * However, this also means that the driver will need to keep track
3396 	 * of the descriptors that RS was set on to check them for the DD bit.
3397 	 */
3398 	txq->ift_rs_pending += nsegs + 1;
3399 	if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3400 	     iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3401 		pi.ipi_flags |= IPI_TX_INTR;
3402 		txq->ift_rs_pending = 0;
3403 	}
3404 
3405 	pi.ipi_segs = segs;
3406 	pi.ipi_nsegs = nsegs;
3407 
3408 	MPASS(pidx >= 0 && pidx < txq->ift_size);
3409 #ifdef PKT_DEBUG
3410 	print_pkt(&pi);
3411 #endif
3412 	if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3413 		bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3414 		DBG_COUNTER_INC(tx_encap);
3415 		MPASS(pi.ipi_new_pidx < txq->ift_size);
3416 
3417 		ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3418 		if (pi.ipi_new_pidx < pi.ipi_pidx) {
3419 			ndesc += txq->ift_size;
3420 			txq->ift_gen = 1;
3421 		}
3422 		/*
3423 		 * drivers can need as many as
3424 		 * two sentinels
3425 		 */
3426 		MPASS(ndesc <= pi.ipi_nsegs + 2);
3427 		MPASS(pi.ipi_new_pidx != pidx);
3428 		MPASS(ndesc > 0);
3429 		txq->ift_in_use += ndesc;
3430 
3431 		/*
3432 		 * We update the last software descriptor again here because there may
3433 		 * be a sentinel and/or there may be more mbufs than segments
3434 		 */
3435 		txq->ift_pidx = pi.ipi_new_pidx;
3436 		txq->ift_npending += pi.ipi_ndescs;
3437 	} else {
3438 		*m_headp = m_head = iflib_remove_mbuf(txq);
3439 		if (err == EFBIG) {
3440 			txq->ift_txd_encap_efbig++;
3441 			if (remap < 2) {
3442 				remap = 1;
3443 				goto defrag;
3444 			}
3445 		}
3446 		goto defrag_failed;
3447 	}
3448 	/*
3449 	 * err can't possibly be non-zero here, so we don't neet to test it
3450 	 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3451 	 */
3452 	return (err);
3453 
3454 defrag_failed:
3455 	txq->ift_mbuf_defrag_failed++;
3456 	txq->ift_map_failed++;
3457 	m_freem(*m_headp);
3458 	DBG_COUNTER_INC(tx_frees);
3459 	*m_headp = NULL;
3460 	DBG_COUNTER_INC(encap_txd_encap_fail);
3461 	return (ENOMEM);
3462 }
3463 
3464 static void
3465 iflib_tx_desc_free(iflib_txq_t txq, int n)
3466 {
3467 	uint32_t qsize, cidx, mask, gen;
3468 	struct mbuf *m, **ifsd_m;
3469 	bool do_prefetch;
3470 
3471 	cidx = txq->ift_cidx;
3472 	gen = txq->ift_gen;
3473 	qsize = txq->ift_size;
3474 	mask = qsize-1;
3475 	ifsd_m = txq->ift_sds.ifsd_m;
3476 	do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3477 
3478 	while (n-- > 0) {
3479 		if (do_prefetch) {
3480 			prefetch(ifsd_m[(cidx + 3) & mask]);
3481 			prefetch(ifsd_m[(cidx + 4) & mask]);
3482 		}
3483 		if ((m = ifsd_m[cidx]) != NULL) {
3484 			prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3485 			if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3486 				bus_dmamap_sync(txq->ift_tso_buf_tag,
3487 				    txq->ift_sds.ifsd_tso_map[cidx],
3488 				    BUS_DMASYNC_POSTWRITE);
3489 				bus_dmamap_unload(txq->ift_tso_buf_tag,
3490 				    txq->ift_sds.ifsd_tso_map[cidx]);
3491 			} else {
3492 				bus_dmamap_sync(txq->ift_buf_tag,
3493 				    txq->ift_sds.ifsd_map[cidx],
3494 				    BUS_DMASYNC_POSTWRITE);
3495 				bus_dmamap_unload(txq->ift_buf_tag,
3496 				    txq->ift_sds.ifsd_map[cidx]);
3497 			}
3498 			/* XXX we don't support any drivers that batch packets yet */
3499 			MPASS(m->m_nextpkt == NULL);
3500 			m_freem(m);
3501 			ifsd_m[cidx] = NULL;
3502 #if MEMORY_LOGGING
3503 			txq->ift_dequeued++;
3504 #endif
3505 			DBG_COUNTER_INC(tx_frees);
3506 		}
3507 		if (__predict_false(++cidx == qsize)) {
3508 			cidx = 0;
3509 			gen = 0;
3510 		}
3511 	}
3512 	txq->ift_cidx = cidx;
3513 	txq->ift_gen = gen;
3514 }
3515 
3516 static __inline int
3517 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3518 {
3519 	int reclaim;
3520 	if_ctx_t ctx = txq->ift_ctx;
3521 
3522 	KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3523 	MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3524 
3525 	/*
3526 	 * Need a rate-limiting check so that this isn't called every time
3527 	 */
3528 	iflib_tx_credits_update(ctx, txq);
3529 	reclaim = DESC_RECLAIMABLE(txq);
3530 
3531 	if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3532 #ifdef INVARIANTS
3533 		if (iflib_verbose_debug) {
3534 			printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3535 			       txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3536 			       reclaim, thresh);
3537 
3538 		}
3539 #endif
3540 		return (0);
3541 	}
3542 	iflib_tx_desc_free(txq, reclaim);
3543 	txq->ift_cleaned += reclaim;
3544 	txq->ift_in_use -= reclaim;
3545 
3546 	return (reclaim);
3547 }
3548 
3549 static struct mbuf **
3550 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3551 {
3552 	int next, size;
3553 	struct mbuf **items;
3554 
3555 	size = r->size;
3556 	next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3557 	items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3558 
3559 	prefetch(items[(cidx + offset) & (size-1)]);
3560 	if (remaining > 1) {
3561 		prefetch2cachelines(&items[next]);
3562 		prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3563 		prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3564 		prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3565 	}
3566 	return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3567 }
3568 
3569 static void
3570 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3571 {
3572 
3573 	ifmp_ring_check_drainage(txq->ift_br, budget);
3574 }
3575 
3576 static uint32_t
3577 iflib_txq_can_drain(struct ifmp_ring *r)
3578 {
3579 	iflib_txq_t txq = r->cookie;
3580 	if_ctx_t ctx = txq->ift_ctx;
3581 
3582 	if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3583 		return (1);
3584 	bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3585 	    BUS_DMASYNC_POSTREAD);
3586 	return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3587 	    false));
3588 }
3589 
3590 static uint32_t
3591 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3592 {
3593 	iflib_txq_t txq = r->cookie;
3594 	if_ctx_t ctx = txq->ift_ctx;
3595 	if_t ifp = ctx->ifc_ifp;
3596 	struct mbuf *m, **mp;
3597 	int avail, bytes_sent, consumed, count, err, i, in_use_prev;
3598 	int mcast_sent, pkt_sent, reclaimed, txq_avail;
3599 	bool do_prefetch, rang, ring;
3600 
3601 	if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3602 			    !LINK_ACTIVE(ctx))) {
3603 		DBG_COUNTER_INC(txq_drain_notready);
3604 		return (0);
3605 	}
3606 	reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3607 	rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3608 	avail = IDXDIFF(pidx, cidx, r->size);
3609 	if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3610 		DBG_COUNTER_INC(txq_drain_flushing);
3611 		for (i = 0; i < avail; i++) {
3612 			if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3613 				m_free(r->items[(cidx + i) & (r->size-1)]);
3614 			r->items[(cidx + i) & (r->size-1)] = NULL;
3615 		}
3616 		return (avail);
3617 	}
3618 
3619 	if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3620 		txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3621 		CALLOUT_LOCK(txq);
3622 		callout_stop(&txq->ift_timer);
3623 		CALLOUT_UNLOCK(txq);
3624 		DBG_COUNTER_INC(txq_drain_oactive);
3625 		return (0);
3626 	}
3627 	if (reclaimed)
3628 		txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3629 	consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3630 	count = MIN(avail, TX_BATCH_SIZE);
3631 #ifdef INVARIANTS
3632 	if (iflib_verbose_debug)
3633 		printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3634 		       avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3635 #endif
3636 	do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3637 	txq_avail = TXQ_AVAIL(txq);
3638 	err = 0;
3639 	for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) {
3640 		int rem = do_prefetch ? count - i : 0;
3641 
3642 		mp = _ring_peek_one(r, cidx, i, rem);
3643 		MPASS(mp != NULL && *mp != NULL);
3644 		if (__predict_false(*mp == (struct mbuf *)txq)) {
3645 			consumed++;
3646 			continue;
3647 		}
3648 		in_use_prev = txq->ift_in_use;
3649 		err = iflib_encap(txq, mp);
3650 		if (__predict_false(err)) {
3651 			/* no room - bail out */
3652 			if (err == ENOBUFS)
3653 				break;
3654 			consumed++;
3655 			/* we can't send this packet - skip it */
3656 			continue;
3657 		}
3658 		consumed++;
3659 		pkt_sent++;
3660 		m = *mp;
3661 		DBG_COUNTER_INC(tx_sent);
3662 		bytes_sent += m->m_pkthdr.len;
3663 		mcast_sent += !!(m->m_flags & M_MCAST);
3664 		txq_avail = TXQ_AVAIL(txq);
3665 
3666 		txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3667 		ETHER_BPF_MTAP(ifp, m);
3668 		if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3669 			break;
3670 		rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3671 	}
3672 
3673 	/* deliberate use of bitwise or to avoid gratuitous short-circuit */
3674 	ring = rang ? false  : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3675 	iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3676 	if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3677 	if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3678 	if (mcast_sent)
3679 		if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3680 #ifdef INVARIANTS
3681 	if (iflib_verbose_debug)
3682 		printf("consumed=%d\n", consumed);
3683 #endif
3684 	return (consumed);
3685 }
3686 
3687 static uint32_t
3688 iflib_txq_drain_always(struct ifmp_ring *r)
3689 {
3690 	return (1);
3691 }
3692 
3693 static uint32_t
3694 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3695 {
3696 	int i, avail;
3697 	struct mbuf **mp;
3698 	iflib_txq_t txq;
3699 
3700 	txq = r->cookie;
3701 
3702 	txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3703 	CALLOUT_LOCK(txq);
3704 	callout_stop(&txq->ift_timer);
3705 	CALLOUT_UNLOCK(txq);
3706 
3707 	avail = IDXDIFF(pidx, cidx, r->size);
3708 	for (i = 0; i < avail; i++) {
3709 		mp = _ring_peek_one(r, cidx, i, avail - i);
3710 		if (__predict_false(*mp == (struct mbuf *)txq))
3711 			continue;
3712 		m_freem(*mp);
3713 		DBG_COUNTER_INC(tx_frees);
3714 	}
3715 	MPASS(ifmp_ring_is_stalled(r) == 0);
3716 	return (avail);
3717 }
3718 
3719 static void
3720 iflib_ifmp_purge(iflib_txq_t txq)
3721 {
3722 	struct ifmp_ring *r;
3723 
3724 	r = txq->ift_br;
3725 	r->drain = iflib_txq_drain_free;
3726 	r->can_drain = iflib_txq_drain_always;
3727 
3728 	ifmp_ring_check_drainage(r, r->size);
3729 
3730 	r->drain = iflib_txq_drain;
3731 	r->can_drain = iflib_txq_can_drain;
3732 }
3733 
3734 static void
3735 _task_fn_tx(void *context)
3736 {
3737 	iflib_txq_t txq = context;
3738 	if_ctx_t ctx = txq->ift_ctx;
3739 #if defined(ALTQ) || defined(DEV_NETMAP)
3740 	if_t ifp = ctx->ifc_ifp;
3741 #endif
3742 	int abdicate = ctx->ifc_sysctl_tx_abdicate;
3743 
3744 #ifdef IFLIB_DIAGNOSTICS
3745 	txq->ift_cpu_exec_count[curcpu]++;
3746 #endif
3747 	if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3748 		return;
3749 #ifdef DEV_NETMAP
3750 	if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3751 		bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3752 		    BUS_DMASYNC_POSTREAD);
3753 		if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3754 			netmap_tx_irq(ifp, txq->ift_id);
3755 		if (ctx->ifc_flags & IFC_LEGACY)
3756 			IFDI_INTR_ENABLE(ctx);
3757 		else
3758 			IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3759 		return;
3760 	}
3761 #endif
3762 #ifdef ALTQ
3763 	if (ALTQ_IS_ENABLED(&ifp->if_snd))
3764 		iflib_altq_if_start(ifp);
3765 #endif
3766 	if (txq->ift_db_pending)
3767 		ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3768 	else if (!abdicate)
3769 		ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3770 	/*
3771 	 * When abdicating, we always need to check drainage, not just when we don't enqueue
3772 	 */
3773 	if (abdicate)
3774 		ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3775 	if (ctx->ifc_flags & IFC_LEGACY)
3776 		IFDI_INTR_ENABLE(ctx);
3777 	else
3778 		IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3779 }
3780 
3781 static void
3782 _task_fn_rx(void *context)
3783 {
3784 	iflib_rxq_t rxq = context;
3785 	if_ctx_t ctx = rxq->ifr_ctx;
3786 	bool more;
3787 	uint16_t budget;
3788 
3789 #ifdef IFLIB_DIAGNOSTICS
3790 	rxq->ifr_cpu_exec_count[curcpu]++;
3791 #endif
3792 	DBG_COUNTER_INC(task_fn_rxs);
3793 	if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3794 		return;
3795 	more = true;
3796 #ifdef DEV_NETMAP
3797 	if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3798 		u_int work = 0;
3799 		if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3800 			more = false;
3801 		}
3802 	}
3803 #endif
3804 	budget = ctx->ifc_sysctl_rx_budget;
3805 	if (budget == 0)
3806 		budget = 16;	/* XXX */
3807 	if (more == false || (more = iflib_rxeof(rxq, budget)) == false) {
3808 		if (ctx->ifc_flags & IFC_LEGACY)
3809 			IFDI_INTR_ENABLE(ctx);
3810 		else
3811 			IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3812 		DBG_COUNTER_INC(rx_intr_enables);
3813 	}
3814 	if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3815 		return;
3816 	if (more)
3817 		GROUPTASK_ENQUEUE(&rxq->ifr_task);
3818 }
3819 
3820 static void
3821 _task_fn_admin(void *context)
3822 {
3823 	if_ctx_t ctx = context;
3824 	if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3825 	iflib_txq_t txq;
3826 	int i;
3827 	bool oactive, running, do_reset, do_watchdog, in_detach;
3828 	uint32_t reset_on = hz / 2;
3829 
3830 	STATE_LOCK(ctx);
3831 	running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3832 	oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3833 	do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3834 	do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3835 	in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3836 	ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3837 	STATE_UNLOCK(ctx);
3838 
3839 	if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3840 		return;
3841 	if (in_detach)
3842 		return;
3843 
3844 	CTX_LOCK(ctx);
3845 	for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3846 		CALLOUT_LOCK(txq);
3847 		callout_stop(&txq->ift_timer);
3848 		CALLOUT_UNLOCK(txq);
3849 	}
3850 	if (do_watchdog) {
3851 		ctx->ifc_watchdog_events++;
3852 		IFDI_WATCHDOG_RESET(ctx);
3853 	}
3854 	IFDI_UPDATE_ADMIN_STATUS(ctx);
3855 	for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3856 #ifdef DEV_NETMAP
3857 		reset_on = hz / 2;
3858 		if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3859 			iflib_netmap_timer_adjust(ctx, txq, &reset_on);
3860 #endif
3861 		callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3862 	}
3863 	IFDI_LINK_INTR_ENABLE(ctx);
3864 	if (do_reset)
3865 		iflib_if_init_locked(ctx);
3866 	CTX_UNLOCK(ctx);
3867 
3868 	if (LINK_ACTIVE(ctx) == 0)
3869 		return;
3870 	for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3871 		iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3872 }
3873 
3874 
3875 static void
3876 _task_fn_iov(void *context)
3877 {
3878 	if_ctx_t ctx = context;
3879 
3880 	if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3881 	    !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3882 		return;
3883 
3884 	CTX_LOCK(ctx);
3885 	IFDI_VFLR_HANDLE(ctx);
3886 	CTX_UNLOCK(ctx);
3887 }
3888 
3889 static int
3890 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3891 {
3892 	int err;
3893 	if_int_delay_info_t info;
3894 	if_ctx_t ctx;
3895 
3896 	info = (if_int_delay_info_t)arg1;
3897 	ctx = info->iidi_ctx;
3898 	info->iidi_req = req;
3899 	info->iidi_oidp = oidp;
3900 	CTX_LOCK(ctx);
3901 	err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3902 	CTX_UNLOCK(ctx);
3903 	return (err);
3904 }
3905 
3906 /*********************************************************************
3907  *
3908  *  IFNET FUNCTIONS
3909  *
3910  **********************************************************************/
3911 
3912 static void
3913 iflib_if_init_locked(if_ctx_t ctx)
3914 {
3915 	iflib_stop(ctx);
3916 	iflib_init_locked(ctx);
3917 }
3918 
3919 
3920 static void
3921 iflib_if_init(void *arg)
3922 {
3923 	if_ctx_t ctx = arg;
3924 
3925 	CTX_LOCK(ctx);
3926 	iflib_if_init_locked(ctx);
3927 	CTX_UNLOCK(ctx);
3928 }
3929 
3930 static int
3931 iflib_if_transmit(if_t ifp, struct mbuf *m)
3932 {
3933 	if_ctx_t	ctx = if_getsoftc(ifp);
3934 
3935 	iflib_txq_t txq;
3936 	int err, qidx;
3937 	int abdicate = ctx->ifc_sysctl_tx_abdicate;
3938 
3939 	if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3940 		DBG_COUNTER_INC(tx_frees);
3941 		m_freem(m);
3942 		return (ENETDOWN);
3943 	}
3944 
3945 	MPASS(m->m_nextpkt == NULL);
3946 	/* ALTQ-enabled interfaces always use queue 0. */
3947 	qidx = 0;
3948 	if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3949 		qidx = QIDX(ctx, m);
3950 	/*
3951 	 * XXX calculate buf_ring based on flowid (divvy up bits?)
3952 	 */
3953 	txq = &ctx->ifc_txqs[qidx];
3954 
3955 #ifdef DRIVER_BACKPRESSURE
3956 	if (txq->ift_closed) {
3957 		while (m != NULL) {
3958 			next = m->m_nextpkt;
3959 			m->m_nextpkt = NULL;
3960 			m_freem(m);
3961 			DBG_COUNTER_INC(tx_frees);
3962 			m = next;
3963 		}
3964 		return (ENOBUFS);
3965 	}
3966 #endif
3967 #ifdef notyet
3968 	qidx = count = 0;
3969 	mp = marr;
3970 	next = m;
3971 	do {
3972 		count++;
3973 		next = next->m_nextpkt;
3974 	} while (next != NULL);
3975 
3976 	if (count > nitems(marr))
3977 		if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
3978 			/* XXX check nextpkt */
3979 			m_freem(m);
3980 			/* XXX simplify for now */
3981 			DBG_COUNTER_INC(tx_frees);
3982 			return (ENOBUFS);
3983 		}
3984 	for (next = m, i = 0; next != NULL; i++) {
3985 		mp[i] = next;
3986 		next = next->m_nextpkt;
3987 		mp[i]->m_nextpkt = NULL;
3988 	}
3989 #endif
3990 	DBG_COUNTER_INC(tx_seen);
3991 	err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
3992 
3993 	if (abdicate)
3994 		GROUPTASK_ENQUEUE(&txq->ift_task);
3995  	if (err) {
3996 		if (!abdicate)
3997 			GROUPTASK_ENQUEUE(&txq->ift_task);
3998 		/* support forthcoming later */
3999 #ifdef DRIVER_BACKPRESSURE
4000 		txq->ift_closed = TRUE;
4001 #endif
4002 		ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4003 		m_freem(m);
4004 		DBG_COUNTER_INC(tx_frees);
4005 	}
4006 
4007 	return (err);
4008 }
4009 
4010 #ifdef ALTQ
4011 /*
4012  * The overall approach to integrating iflib with ALTQ is to continue to use
4013  * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4014  * ring.  Technically, when using ALTQ, queueing to an intermediate mp_ring
4015  * is redundant/unnecessary, but doing so minimizes the amount of
4016  * ALTQ-specific code required in iflib.  It is assumed that the overhead of
4017  * redundantly queueing to an intermediate mp_ring is swamped by the
4018  * performance limitations inherent in using ALTQ.
4019  *
4020  * When ALTQ support is compiled in, all iflib drivers will use a transmit
4021  * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4022  * given interface.  If ALTQ is enabled for an interface, then all
4023  * transmitted packets for that interface will be submitted to the ALTQ
4024  * subsystem via IFQ_ENQUEUE().  We don't use the legacy if_transmit()
4025  * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4026  * update stats that the iflib machinery handles, and which is sensitve to
4027  * the disused IFF_DRV_OACTIVE flag.  Additionally, iflib_altq_if_start()
4028  * will be installed as the start routine for use by ALTQ facilities that
4029  * need to trigger queue drains on a scheduled basis.
4030  *
4031  */
4032 static void
4033 iflib_altq_if_start(if_t ifp)
4034 {
4035 	struct ifaltq *ifq = &ifp->if_snd;
4036 	struct mbuf *m;
4037 
4038 	IFQ_LOCK(ifq);
4039 	IFQ_DEQUEUE_NOLOCK(ifq, m);
4040 	while (m != NULL) {
4041 		iflib_if_transmit(ifp, m);
4042 		IFQ_DEQUEUE_NOLOCK(ifq, m);
4043 	}
4044 	IFQ_UNLOCK(ifq);
4045 }
4046 
4047 static int
4048 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4049 {
4050 	int err;
4051 
4052 	if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4053 		IFQ_ENQUEUE(&ifp->if_snd, m, err);
4054 		if (err == 0)
4055 			iflib_altq_if_start(ifp);
4056 	} else
4057 		err = iflib_if_transmit(ifp, m);
4058 
4059 	return (err);
4060 }
4061 #endif /* ALTQ */
4062 
4063 static void
4064 iflib_if_qflush(if_t ifp)
4065 {
4066 	if_ctx_t ctx = if_getsoftc(ifp);
4067 	iflib_txq_t txq = ctx->ifc_txqs;
4068 	int i;
4069 
4070 	STATE_LOCK(ctx);
4071 	ctx->ifc_flags |= IFC_QFLUSH;
4072 	STATE_UNLOCK(ctx);
4073 	for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4074 		while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4075 			iflib_txq_check_drain(txq, 0);
4076 	STATE_LOCK(ctx);
4077 	ctx->ifc_flags &= ~IFC_QFLUSH;
4078 	STATE_UNLOCK(ctx);
4079 
4080 	/*
4081 	 * When ALTQ is enabled, this will also take care of purging the
4082 	 * ALTQ queue(s).
4083 	 */
4084 	if_qflush(ifp);
4085 }
4086 
4087 
4088 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4089 		     IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4090 		     IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4091 		     IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP)
4092 
4093 static int
4094 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4095 {
4096 	if_ctx_t ctx = if_getsoftc(ifp);
4097 	struct ifreq	*ifr = (struct ifreq *)data;
4098 #if defined(INET) || defined(INET6)
4099 	struct ifaddr	*ifa = (struct ifaddr *)data;
4100 #endif
4101 	bool		avoid_reset = false;
4102 	int		err = 0, reinit = 0, bits;
4103 
4104 	switch (command) {
4105 	case SIOCSIFADDR:
4106 #ifdef INET
4107 		if (ifa->ifa_addr->sa_family == AF_INET)
4108 			avoid_reset = true;
4109 #endif
4110 #ifdef INET6
4111 		if (ifa->ifa_addr->sa_family == AF_INET6)
4112 			avoid_reset = true;
4113 #endif
4114 		/*
4115 		** Calling init results in link renegotiation,
4116 		** so we avoid doing it when possible.
4117 		*/
4118 		if (avoid_reset) {
4119 			if_setflagbits(ifp, IFF_UP,0);
4120 			if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4121 				reinit = 1;
4122 #ifdef INET
4123 			if (!(if_getflags(ifp) & IFF_NOARP))
4124 				arp_ifinit(ifp, ifa);
4125 #endif
4126 		} else
4127 			err = ether_ioctl(ifp, command, data);
4128 		break;
4129 	case SIOCSIFMTU:
4130 		CTX_LOCK(ctx);
4131 		if (ifr->ifr_mtu == if_getmtu(ifp)) {
4132 			CTX_UNLOCK(ctx);
4133 			break;
4134 		}
4135 		bits = if_getdrvflags(ifp);
4136 		/* stop the driver and free any clusters before proceeding */
4137 		iflib_stop(ctx);
4138 
4139 		if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4140 			STATE_LOCK(ctx);
4141 			if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4142 				ctx->ifc_flags |= IFC_MULTISEG;
4143 			else
4144 				ctx->ifc_flags &= ~IFC_MULTISEG;
4145 			STATE_UNLOCK(ctx);
4146 			err = if_setmtu(ifp, ifr->ifr_mtu);
4147 		}
4148 		iflib_init_locked(ctx);
4149 		STATE_LOCK(ctx);
4150 		if_setdrvflags(ifp, bits);
4151 		STATE_UNLOCK(ctx);
4152 		CTX_UNLOCK(ctx);
4153 		break;
4154 	case SIOCSIFFLAGS:
4155 		CTX_LOCK(ctx);
4156 		if (if_getflags(ifp) & IFF_UP) {
4157 			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4158 				if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4159 				    (IFF_PROMISC | IFF_ALLMULTI)) {
4160 					err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4161 				}
4162 			} else
4163 				reinit = 1;
4164 		} else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4165 			iflib_stop(ctx);
4166 		}
4167 		ctx->ifc_if_flags = if_getflags(ifp);
4168 		CTX_UNLOCK(ctx);
4169 		break;
4170 	case SIOCADDMULTI:
4171 	case SIOCDELMULTI:
4172 		if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4173 			CTX_LOCK(ctx);
4174 			IFDI_INTR_DISABLE(ctx);
4175 			IFDI_MULTI_SET(ctx);
4176 			IFDI_INTR_ENABLE(ctx);
4177 			CTX_UNLOCK(ctx);
4178 		}
4179 		break;
4180 	case SIOCSIFMEDIA:
4181 		CTX_LOCK(ctx);
4182 		IFDI_MEDIA_SET(ctx);
4183 		CTX_UNLOCK(ctx);
4184 		/* FALLTHROUGH */
4185 	case SIOCGIFMEDIA:
4186 	case SIOCGIFXMEDIA:
4187 		err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4188 		break;
4189 	case SIOCGI2C:
4190 	{
4191 		struct ifi2creq i2c;
4192 
4193 		err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4194 		if (err != 0)
4195 			break;
4196 		if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4197 			err = EINVAL;
4198 			break;
4199 		}
4200 		if (i2c.len > sizeof(i2c.data)) {
4201 			err = EINVAL;
4202 			break;
4203 		}
4204 
4205 		if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4206 			err = copyout(&i2c, ifr_data_get_ptr(ifr),
4207 			    sizeof(i2c));
4208 		break;
4209 	}
4210 	case SIOCSIFCAP:
4211 	{
4212 		int mask, setmask, oldmask;
4213 
4214 		oldmask = if_getcapenable(ifp);
4215 		mask = ifr->ifr_reqcap ^ oldmask;
4216 		mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP;
4217 		setmask = 0;
4218 #ifdef TCP_OFFLOAD
4219 		setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4220 #endif
4221 		setmask |= (mask & IFCAP_FLAGS);
4222 		setmask |= (mask & IFCAP_WOL);
4223 
4224 		/*
4225 		 * If any RX csum has changed, change all the ones that
4226 		 * are supported by the driver.
4227 		 */
4228 		if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4229 			setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4230 			    (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4231 		}
4232 
4233 		/*
4234 		 * want to ensure that traffic has stopped before we change any of the flags
4235 		 */
4236 		if (setmask) {
4237 			CTX_LOCK(ctx);
4238 			bits = if_getdrvflags(ifp);
4239 			if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4240 				iflib_stop(ctx);
4241 			STATE_LOCK(ctx);
4242 			if_togglecapenable(ifp, setmask);
4243 			STATE_UNLOCK(ctx);
4244 			if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4245 				iflib_init_locked(ctx);
4246 			STATE_LOCK(ctx);
4247 			if_setdrvflags(ifp, bits);
4248 			STATE_UNLOCK(ctx);
4249 			CTX_UNLOCK(ctx);
4250 		}
4251 		if_vlancap(ifp);
4252 		break;
4253 	}
4254 	case SIOCGPRIVATE_0:
4255 	case SIOCSDRVSPEC:
4256 	case SIOCGDRVSPEC:
4257 		CTX_LOCK(ctx);
4258 		err = IFDI_PRIV_IOCTL(ctx, command, data);
4259 		CTX_UNLOCK(ctx);
4260 		break;
4261 	default:
4262 		err = ether_ioctl(ifp, command, data);
4263 		break;
4264 	}
4265 	if (reinit)
4266 		iflib_if_init(ctx);
4267 	return (err);
4268 }
4269 
4270 static uint64_t
4271 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4272 {
4273 	if_ctx_t ctx = if_getsoftc(ifp);
4274 
4275 	return (IFDI_GET_COUNTER(ctx, cnt));
4276 }
4277 
4278 /*********************************************************************
4279  *
4280  *  OTHER FUNCTIONS EXPORTED TO THE STACK
4281  *
4282  **********************************************************************/
4283 
4284 static void
4285 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4286 {
4287 	if_ctx_t ctx = if_getsoftc(ifp);
4288 
4289 	if ((void *)ctx != arg)
4290 		return;
4291 
4292 	if ((vtag == 0) || (vtag > 4095))
4293 		return;
4294 
4295 	if (iflib_in_detach(ctx))
4296 		return;
4297 
4298 	CTX_LOCK(ctx);
4299 	IFDI_VLAN_REGISTER(ctx, vtag);
4300 	/* Re-init to load the changes */
4301 	if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4302 		iflib_if_init_locked(ctx);
4303 	CTX_UNLOCK(ctx);
4304 }
4305 
4306 static void
4307 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4308 {
4309 	if_ctx_t ctx = if_getsoftc(ifp);
4310 
4311 	if ((void *)ctx != arg)
4312 		return;
4313 
4314 	if ((vtag == 0) || (vtag > 4095))
4315 		return;
4316 
4317 	CTX_LOCK(ctx);
4318 	IFDI_VLAN_UNREGISTER(ctx, vtag);
4319 	/* Re-init to load the changes */
4320 	if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4321 		iflib_if_init_locked(ctx);
4322 	CTX_UNLOCK(ctx);
4323 }
4324 
4325 static void
4326 iflib_led_func(void *arg, int onoff)
4327 {
4328 	if_ctx_t ctx = arg;
4329 
4330 	CTX_LOCK(ctx);
4331 	IFDI_LED_FUNC(ctx, onoff);
4332 	CTX_UNLOCK(ctx);
4333 }
4334 
4335 /*********************************************************************
4336  *
4337  *  BUS FUNCTION DEFINITIONS
4338  *
4339  **********************************************************************/
4340 
4341 int
4342 iflib_device_probe(device_t dev)
4343 {
4344 	const pci_vendor_info_t *ent;
4345 	if_shared_ctx_t sctx;
4346 	uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id;
4347 	uint16_t pci_vendor_id;
4348 
4349 	if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4350 		return (ENOTSUP);
4351 
4352 	pci_vendor_id = pci_get_vendor(dev);
4353 	pci_device_id = pci_get_device(dev);
4354 	pci_subvendor_id = pci_get_subvendor(dev);
4355 	pci_subdevice_id = pci_get_subdevice(dev);
4356 	pci_rev_id = pci_get_revid(dev);
4357 	if (sctx->isc_parse_devinfo != NULL)
4358 		sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4359 
4360 	ent = sctx->isc_vendor_info;
4361 	while (ent->pvi_vendor_id != 0) {
4362 		if (pci_vendor_id != ent->pvi_vendor_id) {
4363 			ent++;
4364 			continue;
4365 		}
4366 		if ((pci_device_id == ent->pvi_device_id) &&
4367 		    ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4368 		     (ent->pvi_subvendor_id == 0)) &&
4369 		    ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4370 		     (ent->pvi_subdevice_id == 0)) &&
4371 		    ((pci_rev_id == ent->pvi_rev_id) ||
4372 		     (ent->pvi_rev_id == 0))) {
4373 
4374 			device_set_desc_copy(dev, ent->pvi_name);
4375 			/* this needs to be changed to zero if the bus probing code
4376 			 * ever stops re-probing on best match because the sctx
4377 			 * may have its values over written by register calls
4378 			 * in subsequent probes
4379 			 */
4380 			return (BUS_PROBE_DEFAULT);
4381 		}
4382 		ent++;
4383 	}
4384 	return (ENXIO);
4385 }
4386 
4387 int
4388 iflib_device_probe_vendor(device_t dev)
4389 {
4390 	int probe;
4391 
4392 	probe = iflib_device_probe(dev);
4393 	if (probe == BUS_PROBE_DEFAULT)
4394 		return (BUS_PROBE_VENDOR);
4395 	else
4396 		return (probe);
4397 }
4398 
4399 static void
4400 iflib_reset_qvalues(if_ctx_t ctx)
4401 {
4402 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4403 	if_shared_ctx_t sctx = ctx->ifc_sctx;
4404 	device_t dev = ctx->ifc_dev;
4405 	int i;
4406 
4407 	if (ctx->ifc_sysctl_ntxqs != 0)
4408 		scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4409 	if (ctx->ifc_sysctl_nrxqs != 0)
4410 		scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4411 
4412 	for (i = 0; i < sctx->isc_ntxqs; i++) {
4413 		if (ctx->ifc_sysctl_ntxds[i] != 0)
4414 			scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4415 		else
4416 			scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4417 	}
4418 
4419 	for (i = 0; i < sctx->isc_nrxqs; i++) {
4420 		if (ctx->ifc_sysctl_nrxds[i] != 0)
4421 			scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4422 		else
4423 			scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4424 	}
4425 
4426 	for (i = 0; i < sctx->isc_nrxqs; i++) {
4427 		if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4428 			device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4429 				      i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4430 			scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4431 		}
4432 		if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4433 			device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4434 				      i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4435 			scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4436 		}
4437 		if (!powerof2(scctx->isc_nrxd[i])) {
4438 			device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4439 				      i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4440 			scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4441 		}
4442 	}
4443 
4444 	for (i = 0; i < sctx->isc_ntxqs; i++) {
4445 		if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4446 			device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4447 				      i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4448 			scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4449 		}
4450 		if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4451 			device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4452 				      i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4453 			scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4454 		}
4455 		if (!powerof2(scctx->isc_ntxd[i])) {
4456 			device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4457 				      i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4458 			scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4459 		}
4460 	}
4461 }
4462 
4463 static void
4464 iflib_add_pfil(if_ctx_t ctx)
4465 {
4466 	struct pfil_head *pfil;
4467 	struct pfil_head_args pa;
4468 	iflib_rxq_t rxq;
4469 	int i;
4470 
4471 	pa.pa_version = PFIL_VERSION;
4472 	pa.pa_flags = PFIL_IN;
4473 	pa.pa_type = PFIL_TYPE_ETHERNET;
4474 	pa.pa_headname = ctx->ifc_ifp->if_xname;
4475 	pfil = pfil_head_register(&pa);
4476 
4477 	for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4478 		rxq->pfil = pfil;
4479 	}
4480 }
4481 
4482 static void
4483 iflib_rem_pfil(if_ctx_t ctx)
4484 {
4485 	struct pfil_head *pfil;
4486 	iflib_rxq_t rxq;
4487 	int i;
4488 
4489 	rxq = ctx->ifc_rxqs;
4490 	pfil = rxq->pfil;
4491 	for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4492 		rxq->pfil = NULL;
4493 	}
4494 	pfil_head_unregister(pfil);
4495 }
4496 
4497 static uint16_t
4498 get_ctx_core_offset(if_ctx_t ctx)
4499 {
4500 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4501 	struct cpu_offset *op;
4502 	uint16_t qc;
4503 	uint16_t ret = ctx->ifc_sysctl_core_offset;
4504 
4505 	if (ret != CORE_OFFSET_UNSPECIFIED)
4506 		return (ret);
4507 
4508 	if (ctx->ifc_sysctl_separate_txrx)
4509 		qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets;
4510 	else
4511 		qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets);
4512 
4513 	mtx_lock(&cpu_offset_mtx);
4514 	SLIST_FOREACH(op, &cpu_offsets, entries) {
4515 		if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4516 			ret = op->offset;
4517 			op->offset += qc;
4518 			MPASS(op->refcount < UINT_MAX);
4519 			op->refcount++;
4520 			break;
4521 		}
4522 	}
4523 	if (ret == CORE_OFFSET_UNSPECIFIED) {
4524 		ret = 0;
4525 		op = malloc(sizeof(struct cpu_offset), M_IFLIB,
4526 		    M_NOWAIT | M_ZERO);
4527 		if (op == NULL) {
4528 			device_printf(ctx->ifc_dev,
4529 			    "allocation for cpu offset failed.\n");
4530 		} else {
4531 			op->offset = qc;
4532 			op->refcount = 1;
4533 			CPU_COPY(&ctx->ifc_cpus, &op->set);
4534 			SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
4535 		}
4536 	}
4537 	mtx_unlock(&cpu_offset_mtx);
4538 
4539 	return (ret);
4540 }
4541 
4542 static void
4543 unref_ctx_core_offset(if_ctx_t ctx)
4544 {
4545 	struct cpu_offset *op, *top;
4546 
4547 	mtx_lock(&cpu_offset_mtx);
4548 	SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
4549 		if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4550 			MPASS(op->refcount > 0);
4551 			op->refcount--;
4552 			if (op->refcount == 0) {
4553 				SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
4554 				free(op, M_IFLIB);
4555 			}
4556 			break;
4557 		}
4558 	}
4559 	mtx_unlock(&cpu_offset_mtx);
4560 }
4561 
4562 int
4563 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4564 {
4565 	if_ctx_t ctx;
4566 	if_t ifp;
4567 	if_softc_ctx_t scctx;
4568 	kobjop_desc_t kobj_desc;
4569 	kobj_method_t *kobj_method;
4570 	int err, msix, rid;
4571 	uint16_t main_rxq, main_txq;
4572 
4573 	ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4574 
4575 	if (sc == NULL) {
4576 		sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4577 		device_set_softc(dev, ctx);
4578 		ctx->ifc_flags |= IFC_SC_ALLOCATED;
4579 	}
4580 
4581 	ctx->ifc_sctx = sctx;
4582 	ctx->ifc_dev = dev;
4583 	ctx->ifc_softc = sc;
4584 
4585 	if ((err = iflib_register(ctx)) != 0) {
4586 		device_printf(dev, "iflib_register failed %d\n", err);
4587 		goto fail_ctx_free;
4588 	}
4589 	iflib_add_device_sysctl_pre(ctx);
4590 
4591 	scctx = &ctx->ifc_softc_ctx;
4592 	ifp = ctx->ifc_ifp;
4593 
4594 	iflib_reset_qvalues(ctx);
4595 	CTX_LOCK(ctx);
4596 	if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4597 		device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4598 		goto fail_unlock;
4599 	}
4600 	_iflib_pre_assert(scctx);
4601 	ctx->ifc_txrx = *scctx->isc_txrx;
4602 
4603 	if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
4604 		ctx->ifc_mediap = scctx->isc_media;
4605 
4606 #ifdef INVARIANTS
4607 	if (scctx->isc_capabilities & IFCAP_TXCSUM)
4608 		MPASS(scctx->isc_tx_csum_flags);
4609 #endif
4610 
4611 	if_setcapabilities(ifp,
4612 	    scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP);
4613 	if_setcapenable(ifp,
4614 	    scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP);
4615 
4616 	if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4617 		scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4618 	if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4619 		scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4620 
4621 	main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4622 	main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4623 
4624 	/* XXX change for per-queue sizes */
4625 	device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4626 	    scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4627 
4628 	if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4629 	    MAX_SINGLE_PACKET_FRACTION)
4630 		scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4631 		    MAX_SINGLE_PACKET_FRACTION);
4632 	if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4633 	    MAX_SINGLE_PACKET_FRACTION)
4634 		scctx->isc_tx_tso_segments_max = max(1,
4635 		    scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4636 
4637 	/* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4638 	if (if_getcapabilities(ifp) & IFCAP_TSO) {
4639 		/*
4640 		 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4641 		 * but some MACs do.
4642 		 */
4643 		if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4644 		    IP_MAXPACKET));
4645 		/*
4646 		 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4647 		 * into account.  In the worst case, each of these calls will
4648 		 * add another mbuf and, thus, the requirement for another DMA
4649 		 * segment.  So for best performance, it doesn't make sense to
4650 		 * advertize a maximum of TSO segments that typically will
4651 		 * require defragmentation in iflib_encap().
4652 		 */
4653 		if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4654 		if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4655 	}
4656 	if (scctx->isc_rss_table_size == 0)
4657 		scctx->isc_rss_table_size = 64;
4658 	scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4659 
4660 	GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4661 	/* XXX format name */
4662 	taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4663 	    NULL, NULL, "admin");
4664 
4665 	/* Set up cpu set.  If it fails, use the set of all CPUs. */
4666 	if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4667 		device_printf(dev, "Unable to fetch CPU list\n");
4668 		CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4669 	}
4670 	MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4671 
4672 	/*
4673 	** Now set up MSI or MSI-X, should return us the number of supported
4674 	** vectors (will be 1 for a legacy interrupt and MSI).
4675 	*/
4676 	if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4677 		msix = scctx->isc_vectors;
4678 	} else if (scctx->isc_msix_bar != 0)
4679 	       /*
4680 		* The simple fact that isc_msix_bar is not 0 does not mean we
4681 		* we have a good value there that is known to work.
4682 		*/
4683 		msix = iflib_msix_init(ctx);
4684 	else {
4685 		scctx->isc_vectors = 1;
4686 		scctx->isc_ntxqsets = 1;
4687 		scctx->isc_nrxqsets = 1;
4688 		scctx->isc_intr = IFLIB_INTR_LEGACY;
4689 		msix = 0;
4690 	}
4691 	/* Get memory for the station queues */
4692 	if ((err = iflib_queues_alloc(ctx))) {
4693 		device_printf(dev, "Unable to allocate queue memory\n");
4694 		goto fail_intr_free;
4695 	}
4696 
4697 	if ((err = iflib_qset_structures_setup(ctx)))
4698 		goto fail_queues;
4699 
4700 	/*
4701 	 * Now that we know how many queues there are, get the core offset.
4702 	 */
4703 	ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
4704 
4705 	/*
4706 	 * Group taskqueues aren't properly set up until SMP is started,
4707 	 * so we disable interrupts until we can handle them post
4708 	 * SI_SUB_SMP.
4709 	 *
4710 	 * XXX: disabling interrupts doesn't actually work, at least for
4711 	 * the non-MSI case.  When they occur before SI_SUB_SMP completes,
4712 	 * we do null handling and depend on this not causing too large an
4713 	 * interrupt storm.
4714 	 */
4715 	IFDI_INTR_DISABLE(ctx);
4716 
4717 	if (msix > 1) {
4718 		/*
4719 		 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
4720 		 * aren't the default NULL implementation.
4721 		 */
4722 		kobj_desc = &ifdi_rx_queue_intr_enable_desc;
4723 		kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4724 		    kobj_desc);
4725 		if (kobj_method == &kobj_desc->deflt) {
4726 			device_printf(dev,
4727 			    "MSI-X requires ifdi_rx_queue_intr_enable method");
4728 			err = EOPNOTSUPP;
4729 			goto fail_queues;
4730 		}
4731 		kobj_desc = &ifdi_tx_queue_intr_enable_desc;
4732 		kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4733 		    kobj_desc);
4734 		if (kobj_method == &kobj_desc->deflt) {
4735 			device_printf(dev,
4736 			    "MSI-X requires ifdi_tx_queue_intr_enable method");
4737 			err = EOPNOTSUPP;
4738 			goto fail_queues;
4739 		}
4740 
4741 		/*
4742 		 * Assign the MSI-X vectors.
4743 		 * Note that the default NULL ifdi_msix_intr_assign method will
4744 		 * fail here, too.
4745 		 */
4746 		err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
4747 		if (err != 0) {
4748 			device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
4749 			    err);
4750 			goto fail_queues;
4751 		}
4752 	} else if (scctx->isc_intr != IFLIB_INTR_MSIX) {
4753 		rid = 0;
4754 		if (scctx->isc_intr == IFLIB_INTR_MSI) {
4755 			MPASS(msix == 1);
4756 			rid = 1;
4757 		}
4758 		if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4759 			device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4760 			goto fail_queues;
4761 		}
4762 	} else {
4763 		device_printf(dev,
4764 		    "Cannot use iflib with only 1 MSI-X interrupt!\n");
4765 		err = ENODEV;
4766 		goto fail_intr_free;
4767 	}
4768 
4769 	ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4770 
4771 	if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4772 		device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4773 		goto fail_detach;
4774 	}
4775 
4776 	/*
4777 	 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4778 	 * This must appear after the call to ether_ifattach() because
4779 	 * ether_ifattach() sets if_hdrlen to the default value.
4780 	 */
4781 	if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4782 		if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4783 
4784 	if ((err = iflib_netmap_attach(ctx))) {
4785 		device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4786 		goto fail_detach;
4787 	}
4788 	*ctxp = ctx;
4789 
4790 	DEBUGNET_SET(ctx->ifc_ifp, iflib);
4791 
4792 	if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4793 	iflib_add_device_sysctl_post(ctx);
4794 	iflib_add_pfil(ctx);
4795 	ctx->ifc_flags |= IFC_INIT_DONE;
4796 	CTX_UNLOCK(ctx);
4797 
4798 	return (0);
4799 
4800 fail_detach:
4801 	ether_ifdetach(ctx->ifc_ifp);
4802 fail_intr_free:
4803 	iflib_free_intr_mem(ctx);
4804 fail_queues:
4805 	iflib_tx_structures_free(ctx);
4806 	iflib_rx_structures_free(ctx);
4807 	taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task);
4808 	IFDI_DETACH(ctx);
4809 fail_unlock:
4810 	CTX_UNLOCK(ctx);
4811 	iflib_deregister(ctx);
4812 fail_ctx_free:
4813 	device_set_softc(ctx->ifc_dev, NULL);
4814         if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4815                 free(ctx->ifc_softc, M_IFLIB);
4816         free(ctx, M_IFLIB);
4817 	return (err);
4818 }
4819 
4820 int
4821 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4822 					  struct iflib_cloneattach_ctx *clctx)
4823 {
4824 	int err;
4825 	if_ctx_t ctx;
4826 	if_t ifp;
4827 	if_softc_ctx_t scctx;
4828 	int i;
4829 	void *sc;
4830 	uint16_t main_txq;
4831 	uint16_t main_rxq;
4832 
4833 	ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4834 	sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4835 	ctx->ifc_flags |= IFC_SC_ALLOCATED;
4836 	if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4837 		ctx->ifc_flags |= IFC_PSEUDO;
4838 
4839 	ctx->ifc_sctx = sctx;
4840 	ctx->ifc_softc = sc;
4841 	ctx->ifc_dev = dev;
4842 
4843 	if ((err = iflib_register(ctx)) != 0) {
4844 		device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4845 		goto fail_ctx_free;
4846 	}
4847 	iflib_add_device_sysctl_pre(ctx);
4848 
4849 	scctx = &ctx->ifc_softc_ctx;
4850 	ifp = ctx->ifc_ifp;
4851 
4852 	iflib_reset_qvalues(ctx);
4853 	CTX_LOCK(ctx);
4854 	if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4855 		device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4856 		goto fail_unlock;
4857 	}
4858 	if (sctx->isc_flags & IFLIB_GEN_MAC)
4859 		ether_gen_addr(ifp, &ctx->ifc_mac);
4860 	if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4861 								clctx->cc_params)) != 0) {
4862 		device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4863 		goto fail_ctx_free;
4864 	}
4865 	ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4866 	ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4867 	ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4868 
4869 #ifdef INVARIANTS
4870 	if (scctx->isc_capabilities & IFCAP_TXCSUM)
4871 		MPASS(scctx->isc_tx_csum_flags);
4872 #endif
4873 
4874 	if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4875 	if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4876 
4877 	ifp->if_flags |= IFF_NOGROUP;
4878 	if (sctx->isc_flags & IFLIB_PSEUDO) {
4879 		ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4880 
4881 		if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4882 			device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4883 			goto fail_detach;
4884 		}
4885 		*ctxp = ctx;
4886 
4887 		/*
4888 		 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4889 		 * This must appear after the call to ether_ifattach() because
4890 		 * ether_ifattach() sets if_hdrlen to the default value.
4891 		 */
4892 		if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4893 			if_setifheaderlen(ifp,
4894 			    sizeof(struct ether_vlan_header));
4895 
4896 		if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4897 		iflib_add_device_sysctl_post(ctx);
4898 		ctx->ifc_flags |= IFC_INIT_DONE;
4899 		return (0);
4900 	}
4901 	_iflib_pre_assert(scctx);
4902 	ctx->ifc_txrx = *scctx->isc_txrx;
4903 
4904 	if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4905 		scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4906 	if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4907 		scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4908 
4909 	main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4910 	main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4911 
4912 	/* XXX change for per-queue sizes */
4913 	device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4914 	    scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4915 
4916 	if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4917 	    MAX_SINGLE_PACKET_FRACTION)
4918 		scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4919 		    MAX_SINGLE_PACKET_FRACTION);
4920 	if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4921 	    MAX_SINGLE_PACKET_FRACTION)
4922 		scctx->isc_tx_tso_segments_max = max(1,
4923 		    scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4924 
4925 	/* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4926 	if (if_getcapabilities(ifp) & IFCAP_TSO) {
4927 		/*
4928 		 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4929 		 * but some MACs do.
4930 		 */
4931 		if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4932 		    IP_MAXPACKET));
4933 		/*
4934 		 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4935 		 * into account.  In the worst case, each of these calls will
4936 		 * add another mbuf and, thus, the requirement for another DMA
4937 		 * segment.  So for best performance, it doesn't make sense to
4938 		 * advertize a maximum of TSO segments that typically will
4939 		 * require defragmentation in iflib_encap().
4940 		 */
4941 		if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4942 		if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4943 	}
4944 	if (scctx->isc_rss_table_size == 0)
4945 		scctx->isc_rss_table_size = 64;
4946 	scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4947 
4948 	GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4949 	/* XXX format name */
4950 	taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4951 	    NULL, NULL, "admin");
4952 
4953 	/* XXX --- can support > 1 -- but keep it simple for now */
4954 	scctx->isc_intr = IFLIB_INTR_LEGACY;
4955 
4956 	/* Get memory for the station queues */
4957 	if ((err = iflib_queues_alloc(ctx))) {
4958 		device_printf(dev, "Unable to allocate queue memory\n");
4959 		goto fail_iflib_detach;
4960 	}
4961 
4962 	if ((err = iflib_qset_structures_setup(ctx))) {
4963 		device_printf(dev, "qset structure setup failed %d\n", err);
4964 		goto fail_queues;
4965 	}
4966 
4967 	/*
4968 	 * XXX What if anything do we want to do about interrupts?
4969 	 */
4970 	ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4971 	if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4972 		device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4973 		goto fail_detach;
4974 	}
4975 
4976 	/*
4977 	 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4978 	 * This must appear after the call to ether_ifattach() because
4979 	 * ether_ifattach() sets if_hdrlen to the default value.
4980 	 */
4981 	if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4982 		if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4983 
4984 	/* XXX handle more than one queue */
4985 	for (i = 0; i < scctx->isc_nrxqsets; i++)
4986 		IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
4987 
4988 	*ctxp = ctx;
4989 
4990 	if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4991 	iflib_add_device_sysctl_post(ctx);
4992 	ctx->ifc_flags |= IFC_INIT_DONE;
4993 	CTX_UNLOCK(ctx);
4994 
4995 	return (0);
4996 fail_detach:
4997 	ether_ifdetach(ctx->ifc_ifp);
4998 fail_queues:
4999 	iflib_tx_structures_free(ctx);
5000 	iflib_rx_structures_free(ctx);
5001 fail_iflib_detach:
5002 	IFDI_DETACH(ctx);
5003 fail_unlock:
5004 	CTX_UNLOCK(ctx);
5005 	iflib_deregister(ctx);
5006 fail_ctx_free:
5007 	free(ctx->ifc_softc, M_IFLIB);
5008 	free(ctx, M_IFLIB);
5009 	return (err);
5010 }
5011 
5012 int
5013 iflib_pseudo_deregister(if_ctx_t ctx)
5014 {
5015 	if_t ifp = ctx->ifc_ifp;
5016 	iflib_txq_t txq;
5017 	iflib_rxq_t rxq;
5018 	int i, j;
5019 	struct taskqgroup *tqg;
5020 	iflib_fl_t fl;
5021 
5022 	/* Unregister VLAN event handlers early */
5023 	iflib_unregister_vlan_handlers(ctx);
5024 
5025 	ether_ifdetach(ifp);
5026 	/* XXX drain any dependent tasks */
5027 	tqg = qgroup_if_io_tqg;
5028 	for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5029 		callout_drain(&txq->ift_timer);
5030 		if (txq->ift_task.gt_uniq != NULL)
5031 			taskqgroup_detach(tqg, &txq->ift_task);
5032 	}
5033 	for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5034 		if (rxq->ifr_task.gt_uniq != NULL)
5035 			taskqgroup_detach(tqg, &rxq->ifr_task);
5036 
5037 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5038 			free(fl->ifl_rx_bitmap, M_IFLIB);
5039 	}
5040 	tqg = qgroup_if_config_tqg;
5041 	if (ctx->ifc_admin_task.gt_uniq != NULL)
5042 		taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5043 	if (ctx->ifc_vflr_task.gt_uniq != NULL)
5044 		taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5045 
5046 	iflib_tx_structures_free(ctx);
5047 	iflib_rx_structures_free(ctx);
5048 
5049 	iflib_deregister(ctx);
5050 
5051 	if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5052 		free(ctx->ifc_softc, M_IFLIB);
5053 	free(ctx, M_IFLIB);
5054 	return (0);
5055 }
5056 
5057 int
5058 iflib_device_attach(device_t dev)
5059 {
5060 	if_ctx_t ctx;
5061 	if_shared_ctx_t sctx;
5062 
5063 	if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5064 		return (ENOTSUP);
5065 
5066 	pci_enable_busmaster(dev);
5067 
5068 	return (iflib_device_register(dev, NULL, sctx, &ctx));
5069 }
5070 
5071 int
5072 iflib_device_deregister(if_ctx_t ctx)
5073 {
5074 	if_t ifp = ctx->ifc_ifp;
5075 	iflib_txq_t txq;
5076 	iflib_rxq_t rxq;
5077 	device_t dev = ctx->ifc_dev;
5078 	int i, j;
5079 	struct taskqgroup *tqg;
5080 	iflib_fl_t fl;
5081 
5082 	/* Make sure VLANS are not using driver */
5083 	if (if_vlantrunkinuse(ifp)) {
5084 		device_printf(dev, "Vlan in use, detach first\n");
5085 		return (EBUSY);
5086 	}
5087 #ifdef PCI_IOV
5088 	if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5089 		device_printf(dev, "SR-IOV in use; detach first.\n");
5090 		return (EBUSY);
5091 	}
5092 #endif
5093 
5094 	STATE_LOCK(ctx);
5095 	ctx->ifc_flags |= IFC_IN_DETACH;
5096 	STATE_UNLOCK(ctx);
5097 
5098 	/* Unregister VLAN handlers before calling iflib_stop() */
5099 	iflib_unregister_vlan_handlers(ctx);
5100 
5101 	iflib_netmap_detach(ifp);
5102 	ether_ifdetach(ifp);
5103 
5104 	CTX_LOCK(ctx);
5105 	iflib_stop(ctx);
5106 	CTX_UNLOCK(ctx);
5107 
5108 	iflib_rem_pfil(ctx);
5109 	if (ctx->ifc_led_dev != NULL)
5110 		led_destroy(ctx->ifc_led_dev);
5111 	/* XXX drain any dependent tasks */
5112 	tqg = qgroup_if_io_tqg;
5113 	for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5114 		callout_drain(&txq->ift_timer);
5115 		if (txq->ift_task.gt_uniq != NULL)
5116 			taskqgroup_detach(tqg, &txq->ift_task);
5117 	}
5118 	for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5119 		if (rxq->ifr_task.gt_uniq != NULL)
5120 			taskqgroup_detach(tqg, &rxq->ifr_task);
5121 
5122 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5123 			free(fl->ifl_rx_bitmap, M_IFLIB);
5124 	}
5125 	tqg = qgroup_if_config_tqg;
5126 	if (ctx->ifc_admin_task.gt_uniq != NULL)
5127 		taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5128 	if (ctx->ifc_vflr_task.gt_uniq != NULL)
5129 		taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5130 	CTX_LOCK(ctx);
5131 	IFDI_DETACH(ctx);
5132 	CTX_UNLOCK(ctx);
5133 
5134 	/* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5135 	iflib_free_intr_mem(ctx);
5136 
5137 	bus_generic_detach(dev);
5138 
5139 	iflib_tx_structures_free(ctx);
5140 	iflib_rx_structures_free(ctx);
5141 
5142 	iflib_deregister(ctx);
5143 
5144 	device_set_softc(ctx->ifc_dev, NULL);
5145 	if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5146 		free(ctx->ifc_softc, M_IFLIB);
5147 	unref_ctx_core_offset(ctx);
5148 	free(ctx, M_IFLIB);
5149 	return (0);
5150 }
5151 
5152 static void
5153 iflib_free_intr_mem(if_ctx_t ctx)
5154 {
5155 
5156 	if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5157 		iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5158 	}
5159 	if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5160 		pci_release_msi(ctx->ifc_dev);
5161 	}
5162 	if (ctx->ifc_msix_mem != NULL) {
5163 		bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5164 		    rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5165 		ctx->ifc_msix_mem = NULL;
5166 	}
5167 }
5168 
5169 int
5170 iflib_device_detach(device_t dev)
5171 {
5172 	if_ctx_t ctx = device_get_softc(dev);
5173 
5174 	return (iflib_device_deregister(ctx));
5175 }
5176 
5177 int
5178 iflib_device_suspend(device_t dev)
5179 {
5180 	if_ctx_t ctx = device_get_softc(dev);
5181 
5182 	CTX_LOCK(ctx);
5183 	IFDI_SUSPEND(ctx);
5184 	CTX_UNLOCK(ctx);
5185 
5186 	return bus_generic_suspend(dev);
5187 }
5188 int
5189 iflib_device_shutdown(device_t dev)
5190 {
5191 	if_ctx_t ctx = device_get_softc(dev);
5192 
5193 	CTX_LOCK(ctx);
5194 	IFDI_SHUTDOWN(ctx);
5195 	CTX_UNLOCK(ctx);
5196 
5197 	return bus_generic_suspend(dev);
5198 }
5199 
5200 
5201 int
5202 iflib_device_resume(device_t dev)
5203 {
5204 	if_ctx_t ctx = device_get_softc(dev);
5205 	iflib_txq_t txq = ctx->ifc_txqs;
5206 
5207 	CTX_LOCK(ctx);
5208 	IFDI_RESUME(ctx);
5209 	iflib_if_init_locked(ctx);
5210 	CTX_UNLOCK(ctx);
5211 	for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5212 		iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5213 
5214 	return (bus_generic_resume(dev));
5215 }
5216 
5217 int
5218 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5219 {
5220 	int error;
5221 	if_ctx_t ctx = device_get_softc(dev);
5222 
5223 	CTX_LOCK(ctx);
5224 	error = IFDI_IOV_INIT(ctx, num_vfs, params);
5225 	CTX_UNLOCK(ctx);
5226 
5227 	return (error);
5228 }
5229 
5230 void
5231 iflib_device_iov_uninit(device_t dev)
5232 {
5233 	if_ctx_t ctx = device_get_softc(dev);
5234 
5235 	CTX_LOCK(ctx);
5236 	IFDI_IOV_UNINIT(ctx);
5237 	CTX_UNLOCK(ctx);
5238 }
5239 
5240 int
5241 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5242 {
5243 	int error;
5244 	if_ctx_t ctx = device_get_softc(dev);
5245 
5246 	CTX_LOCK(ctx);
5247 	error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5248 	CTX_UNLOCK(ctx);
5249 
5250 	return (error);
5251 }
5252 
5253 /*********************************************************************
5254  *
5255  *  MODULE FUNCTION DEFINITIONS
5256  *
5257  **********************************************************************/
5258 
5259 /*
5260  * - Start a fast taskqueue thread for each core
5261  * - Start a taskqueue for control operations
5262  */
5263 static int
5264 iflib_module_init(void)
5265 {
5266 	return (0);
5267 }
5268 
5269 static int
5270 iflib_module_event_handler(module_t mod, int what, void *arg)
5271 {
5272 	int err;
5273 
5274 	switch (what) {
5275 	case MOD_LOAD:
5276 		if ((err = iflib_module_init()) != 0)
5277 			return (err);
5278 		break;
5279 	case MOD_UNLOAD:
5280 		return (EBUSY);
5281 	default:
5282 		return (EOPNOTSUPP);
5283 	}
5284 
5285 	return (0);
5286 }
5287 
5288 /*********************************************************************
5289  *
5290  *  PUBLIC FUNCTION DEFINITIONS
5291  *     ordered as in iflib.h
5292  *
5293  **********************************************************************/
5294 
5295 
5296 static void
5297 _iflib_assert(if_shared_ctx_t sctx)
5298 {
5299 	int i;
5300 
5301 	MPASS(sctx->isc_tx_maxsize);
5302 	MPASS(sctx->isc_tx_maxsegsize);
5303 
5304 	MPASS(sctx->isc_rx_maxsize);
5305 	MPASS(sctx->isc_rx_nsegments);
5306 	MPASS(sctx->isc_rx_maxsegsize);
5307 
5308 	MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5309 	for (i = 0; i < sctx->isc_nrxqs; i++) {
5310 		MPASS(sctx->isc_nrxd_min[i]);
5311 		MPASS(powerof2(sctx->isc_nrxd_min[i]));
5312 		MPASS(sctx->isc_nrxd_max[i]);
5313 		MPASS(powerof2(sctx->isc_nrxd_max[i]));
5314 		MPASS(sctx->isc_nrxd_default[i]);
5315 		MPASS(powerof2(sctx->isc_nrxd_default[i]));
5316 	}
5317 
5318 	MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5319 	for (i = 0; i < sctx->isc_ntxqs; i++) {
5320 		MPASS(sctx->isc_ntxd_min[i]);
5321 		MPASS(powerof2(sctx->isc_ntxd_min[i]));
5322 		MPASS(sctx->isc_ntxd_max[i]);
5323 		MPASS(powerof2(sctx->isc_ntxd_max[i]));
5324 		MPASS(sctx->isc_ntxd_default[i]);
5325 		MPASS(powerof2(sctx->isc_ntxd_default[i]));
5326 	}
5327 }
5328 
5329 static void
5330 _iflib_pre_assert(if_softc_ctx_t scctx)
5331 {
5332 
5333 	MPASS(scctx->isc_txrx->ift_txd_encap);
5334 	MPASS(scctx->isc_txrx->ift_txd_flush);
5335 	MPASS(scctx->isc_txrx->ift_txd_credits_update);
5336 	MPASS(scctx->isc_txrx->ift_rxd_available);
5337 	MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5338 	MPASS(scctx->isc_txrx->ift_rxd_refill);
5339 	MPASS(scctx->isc_txrx->ift_rxd_flush);
5340 }
5341 
5342 static int
5343 iflib_register(if_ctx_t ctx)
5344 {
5345 	if_shared_ctx_t sctx = ctx->ifc_sctx;
5346 	driver_t *driver = sctx->isc_driver;
5347 	device_t dev = ctx->ifc_dev;
5348 	if_t ifp;
5349 
5350 	_iflib_assert(sctx);
5351 
5352 	CTX_LOCK_INIT(ctx);
5353 	STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5354 	ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER);
5355 	if (ifp == NULL) {
5356 		device_printf(dev, "can not allocate ifnet structure\n");
5357 		return (ENOMEM);
5358 	}
5359 
5360 	/*
5361 	 * Initialize our context's device specific methods
5362 	 */
5363 	kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5364 	kobj_class_compile((kobj_class_t) driver);
5365 
5366 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5367 	if_setsoftc(ifp, ctx);
5368 	if_setdev(ifp, dev);
5369 	if_setinitfn(ifp, iflib_if_init);
5370 	if_setioctlfn(ifp, iflib_if_ioctl);
5371 #ifdef ALTQ
5372 	if_setstartfn(ifp, iflib_altq_if_start);
5373 	if_settransmitfn(ifp, iflib_altq_if_transmit);
5374 	if_setsendqready(ifp);
5375 #else
5376 	if_settransmitfn(ifp, iflib_if_transmit);
5377 #endif
5378 	if_setqflushfn(ifp, iflib_if_qflush);
5379 	if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
5380 
5381 	ctx->ifc_vlan_attach_event =
5382 		EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5383 							  EVENTHANDLER_PRI_FIRST);
5384 	ctx->ifc_vlan_detach_event =
5385 		EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5386 							  EVENTHANDLER_PRI_FIRST);
5387 
5388 	if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
5389 		ctx->ifc_mediap = &ctx->ifc_media;
5390 		ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
5391 		    iflib_media_change, iflib_media_status);
5392 	}
5393 	return (0);
5394 }
5395 
5396 static void
5397 iflib_unregister_vlan_handlers(if_ctx_t ctx)
5398 {
5399 	/* Unregister VLAN events */
5400 	if (ctx->ifc_vlan_attach_event != NULL) {
5401 		EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5402 		ctx->ifc_vlan_attach_event = NULL;
5403 	}
5404 	if (ctx->ifc_vlan_detach_event != NULL) {
5405 		EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5406 		ctx->ifc_vlan_detach_event = NULL;
5407 	}
5408 
5409 }
5410 
5411 static void
5412 iflib_deregister(if_ctx_t ctx)
5413 {
5414 	if_t ifp = ctx->ifc_ifp;
5415 
5416 	/* Remove all media */
5417 	ifmedia_removeall(&ctx->ifc_media);
5418 
5419 	/* Ensure that VLAN event handlers are unregistered */
5420 	iflib_unregister_vlan_handlers(ctx);
5421 
5422 	/* Release kobject reference */
5423 	kobj_delete((kobj_t) ctx, NULL);
5424 
5425 	/* Free the ifnet structure */
5426 	if_free(ifp);
5427 
5428 	STATE_LOCK_DESTROY(ctx);
5429 
5430 	/* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5431 	CTX_LOCK_DESTROY(ctx);
5432 }
5433 
5434 static int
5435 iflib_queues_alloc(if_ctx_t ctx)
5436 {
5437 	if_shared_ctx_t sctx = ctx->ifc_sctx;
5438 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5439 	device_t dev = ctx->ifc_dev;
5440 	int nrxqsets = scctx->isc_nrxqsets;
5441 	int ntxqsets = scctx->isc_ntxqsets;
5442 	iflib_txq_t txq;
5443 	iflib_rxq_t rxq;
5444 	iflib_fl_t fl = NULL;
5445 	int i, j, cpu, err, txconf, rxconf;
5446 	iflib_dma_info_t ifdip;
5447 	uint32_t *rxqsizes = scctx->isc_rxqsizes;
5448 	uint32_t *txqsizes = scctx->isc_txqsizes;
5449 	uint8_t nrxqs = sctx->isc_nrxqs;
5450 	uint8_t ntxqs = sctx->isc_ntxqs;
5451 	int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5452 	caddr_t *vaddrs;
5453 	uint64_t *paddrs;
5454 
5455 	KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5456 	KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5457 
5458 	/* Allocate the TX ring struct memory */
5459 	if (!(ctx->ifc_txqs =
5460 	    (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5461 	    ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5462 		device_printf(dev, "Unable to allocate TX ring memory\n");
5463 		err = ENOMEM;
5464 		goto fail;
5465 	}
5466 
5467 	/* Now allocate the RX */
5468 	if (!(ctx->ifc_rxqs =
5469 	    (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5470 	    nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5471 		device_printf(dev, "Unable to allocate RX ring memory\n");
5472 		err = ENOMEM;
5473 		goto rx_fail;
5474 	}
5475 
5476 	txq = ctx->ifc_txqs;
5477 	rxq = ctx->ifc_rxqs;
5478 
5479 	/*
5480 	 * XXX handle allocation failure
5481 	 */
5482 	for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5483 		/* Set up some basics */
5484 
5485 		if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5486 		    M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5487 			device_printf(dev,
5488 			    "Unable to allocate TX DMA info memory\n");
5489 			err = ENOMEM;
5490 			goto err_tx_desc;
5491 		}
5492 		txq->ift_ifdi = ifdip;
5493 		for (j = 0; j < ntxqs; j++, ifdip++) {
5494 			if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5495 				device_printf(dev,
5496 				    "Unable to allocate TX descriptors\n");
5497 				err = ENOMEM;
5498 				goto err_tx_desc;
5499 			}
5500 			txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5501 			bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5502 		}
5503 		txq->ift_ctx = ctx;
5504 		txq->ift_id = i;
5505 		if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5506 			txq->ift_br_offset = 1;
5507 		} else {
5508 			txq->ift_br_offset = 0;
5509 		}
5510 		/* XXX fix this */
5511 		txq->ift_timer.c_cpu = cpu;
5512 
5513 		if (iflib_txsd_alloc(txq)) {
5514 			device_printf(dev, "Critical Failure setting up TX buffers\n");
5515 			err = ENOMEM;
5516 			goto err_tx_desc;
5517 		}
5518 
5519 		/* Initialize the TX lock */
5520 		snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
5521 		    device_get_nameunit(dev), txq->ift_id);
5522 		mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5523 		callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5524 
5525 		err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5526 				      iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5527 		if (err) {
5528 			/* XXX free any allocated rings */
5529 			device_printf(dev, "Unable to allocate buf_ring\n");
5530 			goto err_tx_desc;
5531 		}
5532 	}
5533 
5534 	for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5535 		/* Set up some basics */
5536 
5537 		if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5538 		   M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5539 			device_printf(dev,
5540 			    "Unable to allocate RX DMA info memory\n");
5541 			err = ENOMEM;
5542 			goto err_tx_desc;
5543 		}
5544 
5545 		rxq->ifr_ifdi = ifdip;
5546 		/* XXX this needs to be changed if #rx queues != #tx queues */
5547 		rxq->ifr_ntxqirq = 1;
5548 		rxq->ifr_txqid[0] = i;
5549 		for (j = 0; j < nrxqs; j++, ifdip++) {
5550 			if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5551 				device_printf(dev,
5552 				    "Unable to allocate RX descriptors\n");
5553 				err = ENOMEM;
5554 				goto err_tx_desc;
5555 			}
5556 			bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5557 		}
5558 		rxq->ifr_ctx = ctx;
5559 		rxq->ifr_id = i;
5560 		if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5561 			rxq->ifr_fl_offset = 1;
5562 		} else {
5563 			rxq->ifr_fl_offset = 0;
5564 		}
5565 		rxq->ifr_nfl = nfree_lists;
5566 		if (!(fl =
5567 			  (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5568 			device_printf(dev, "Unable to allocate free list memory\n");
5569 			err = ENOMEM;
5570 			goto err_tx_desc;
5571 		}
5572 		rxq->ifr_fl = fl;
5573 		for (j = 0; j < nfree_lists; j++) {
5574 			fl[j].ifl_rxq = rxq;
5575 			fl[j].ifl_id = j;
5576 			fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5577 			fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5578 		}
5579 		/* Allocate receive buffers for the ring */
5580 		if (iflib_rxsd_alloc(rxq)) {
5581 			device_printf(dev,
5582 			    "Critical Failure setting up receive buffers\n");
5583 			err = ENOMEM;
5584 			goto err_rx_desc;
5585 		}
5586 
5587 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5588 			fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5589 			    M_WAITOK);
5590 	}
5591 
5592 	/* TXQs */
5593 	vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5594 	paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5595 	for (i = 0; i < ntxqsets; i++) {
5596 		iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5597 
5598 		for (j = 0; j < ntxqs; j++, di++) {
5599 			vaddrs[i*ntxqs + j] = di->idi_vaddr;
5600 			paddrs[i*ntxqs + j] = di->idi_paddr;
5601 		}
5602 	}
5603 	if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5604 		device_printf(ctx->ifc_dev,
5605 		    "Unable to allocate device TX queue\n");
5606 		iflib_tx_structures_free(ctx);
5607 		free(vaddrs, M_IFLIB);
5608 		free(paddrs, M_IFLIB);
5609 		goto err_rx_desc;
5610 	}
5611 	free(vaddrs, M_IFLIB);
5612 	free(paddrs, M_IFLIB);
5613 
5614 	/* RXQs */
5615 	vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5616 	paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5617 	for (i = 0; i < nrxqsets; i++) {
5618 		iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5619 
5620 		for (j = 0; j < nrxqs; j++, di++) {
5621 			vaddrs[i*nrxqs + j] = di->idi_vaddr;
5622 			paddrs[i*nrxqs + j] = di->idi_paddr;
5623 		}
5624 	}
5625 	if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5626 		device_printf(ctx->ifc_dev,
5627 		    "Unable to allocate device RX queue\n");
5628 		iflib_tx_structures_free(ctx);
5629 		free(vaddrs, M_IFLIB);
5630 		free(paddrs, M_IFLIB);
5631 		goto err_rx_desc;
5632 	}
5633 	free(vaddrs, M_IFLIB);
5634 	free(paddrs, M_IFLIB);
5635 
5636 	return (0);
5637 
5638 /* XXX handle allocation failure changes */
5639 err_rx_desc:
5640 err_tx_desc:
5641 rx_fail:
5642 	if (ctx->ifc_rxqs != NULL)
5643 		free(ctx->ifc_rxqs, M_IFLIB);
5644 	ctx->ifc_rxqs = NULL;
5645 	if (ctx->ifc_txqs != NULL)
5646 		free(ctx->ifc_txqs, M_IFLIB);
5647 	ctx->ifc_txqs = NULL;
5648 fail:
5649 	return (err);
5650 }
5651 
5652 static int
5653 iflib_tx_structures_setup(if_ctx_t ctx)
5654 {
5655 	iflib_txq_t txq = ctx->ifc_txqs;
5656 	int i;
5657 
5658 	for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5659 		iflib_txq_setup(txq);
5660 
5661 	return (0);
5662 }
5663 
5664 static void
5665 iflib_tx_structures_free(if_ctx_t ctx)
5666 {
5667 	iflib_txq_t txq = ctx->ifc_txqs;
5668 	if_shared_ctx_t sctx = ctx->ifc_sctx;
5669 	int i, j;
5670 
5671 	for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5672 		for (j = 0; j < sctx->isc_ntxqs; j++)
5673 			iflib_dma_free(&txq->ift_ifdi[j]);
5674 		iflib_txq_destroy(txq);
5675 	}
5676 	free(ctx->ifc_txqs, M_IFLIB);
5677 	ctx->ifc_txqs = NULL;
5678 	IFDI_QUEUES_FREE(ctx);
5679 }
5680 
5681 /*********************************************************************
5682  *
5683  *  Initialize all receive rings.
5684  *
5685  **********************************************************************/
5686 static int
5687 iflib_rx_structures_setup(if_ctx_t ctx)
5688 {
5689 	iflib_rxq_t rxq = ctx->ifc_rxqs;
5690 	int q;
5691 #if defined(INET6) || defined(INET)
5692 	int err, i;
5693 #endif
5694 
5695 	for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5696 #if defined(INET6) || defined(INET)
5697 		if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) {
5698 			err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5699 			    TCP_LRO_ENTRIES, min(1024,
5700 			    ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
5701 			if (err != 0) {
5702 				device_printf(ctx->ifc_dev,
5703 				    "LRO Initialization failed!\n");
5704 				goto fail;
5705 			}
5706 		}
5707 #endif
5708 		IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5709 	}
5710 	return (0);
5711 #if defined(INET6) || defined(INET)
5712 fail:
5713 	/*
5714 	 * Free LRO resources allocated so far, we will only handle
5715 	 * the rings that completed, the failing case will have
5716 	 * cleaned up for itself.  'q' failed, so its the terminus.
5717 	 */
5718 	rxq = ctx->ifc_rxqs;
5719 	for (i = 0; i < q; ++i, rxq++) {
5720 		if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5721 			tcp_lro_free(&rxq->ifr_lc);
5722 	}
5723 	return (err);
5724 #endif
5725 }
5726 
5727 /*********************************************************************
5728  *
5729  *  Free all receive rings.
5730  *
5731  **********************************************************************/
5732 static void
5733 iflib_rx_structures_free(if_ctx_t ctx)
5734 {
5735 	iflib_rxq_t rxq = ctx->ifc_rxqs;
5736 	if_shared_ctx_t sctx = ctx->ifc_sctx;
5737 	int i, j;
5738 
5739 	for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5740 		for (j = 0; j < sctx->isc_nrxqs; j++)
5741 			iflib_dma_free(&rxq->ifr_ifdi[j]);
5742 		iflib_rx_sds_free(rxq);
5743 #if defined(INET6) || defined(INET)
5744 		if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5745 			tcp_lro_free(&rxq->ifr_lc);
5746 #endif
5747 	}
5748 	free(ctx->ifc_rxqs, M_IFLIB);
5749 	ctx->ifc_rxqs = NULL;
5750 }
5751 
5752 static int
5753 iflib_qset_structures_setup(if_ctx_t ctx)
5754 {
5755 	int err;
5756 
5757 	/*
5758 	 * It is expected that the caller takes care of freeing queues if this
5759 	 * fails.
5760 	 */
5761 	if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5762 		device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5763 		return (err);
5764 	}
5765 
5766 	if ((err = iflib_rx_structures_setup(ctx)) != 0)
5767 		device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5768 
5769 	return (err);
5770 }
5771 
5772 int
5773 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5774 		driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5775 {
5776 
5777 	return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5778 }
5779 
5780 #ifdef SMP
5781 static int
5782 find_nth(if_ctx_t ctx, int qid)
5783 {
5784 	cpuset_t cpus;
5785 	int i, cpuid, eqid, count;
5786 
5787 	CPU_COPY(&ctx->ifc_cpus, &cpus);
5788 	count = CPU_COUNT(&cpus);
5789 	eqid = qid % count;
5790 	/* clear up to the qid'th bit */
5791 	for (i = 0; i < eqid; i++) {
5792 		cpuid = CPU_FFS(&cpus);
5793 		MPASS(cpuid != 0);
5794 		CPU_CLR(cpuid-1, &cpus);
5795 	}
5796 	cpuid = CPU_FFS(&cpus);
5797 	MPASS(cpuid != 0);
5798 	return (cpuid-1);
5799 }
5800 
5801 #ifdef SCHED_ULE
5802 extern struct cpu_group *cpu_top;              /* CPU topology */
5803 
5804 static int
5805 find_child_with_core(int cpu, struct cpu_group *grp)
5806 {
5807 	int i;
5808 
5809 	if (grp->cg_children == 0)
5810 		return -1;
5811 
5812 	MPASS(grp->cg_child);
5813 	for (i = 0; i < grp->cg_children; i++) {
5814 		if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5815 			return i;
5816 	}
5817 
5818 	return -1;
5819 }
5820 
5821 /*
5822  * Find the nth "close" core to the specified core
5823  * "close" is defined as the deepest level that shares
5824  * at least an L2 cache.  With threads, this will be
5825  * threads on the same core.  If the shared cache is L3
5826  * or higher, simply returns the same core.
5827  */
5828 static int
5829 find_close_core(int cpu, int core_offset)
5830 {
5831 	struct cpu_group *grp;
5832 	int i;
5833 	int fcpu;
5834 	cpuset_t cs;
5835 
5836 	grp = cpu_top;
5837 	if (grp == NULL)
5838 		return cpu;
5839 	i = 0;
5840 	while ((i = find_child_with_core(cpu, grp)) != -1) {
5841 		/* If the child only has one cpu, don't descend */
5842 		if (grp->cg_child[i].cg_count <= 1)
5843 			break;
5844 		grp = &grp->cg_child[i];
5845 	}
5846 
5847 	/* If they don't share at least an L2 cache, use the same CPU */
5848 	if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5849 		return cpu;
5850 
5851 	/* Now pick one */
5852 	CPU_COPY(&grp->cg_mask, &cs);
5853 
5854 	/* Add the selected CPU offset to core offset. */
5855 	for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5856 		if (fcpu - 1 == cpu)
5857 			break;
5858 		CPU_CLR(fcpu - 1, &cs);
5859 	}
5860 	MPASS(fcpu);
5861 
5862 	core_offset += i;
5863 
5864 	CPU_COPY(&grp->cg_mask, &cs);
5865 	for (i = core_offset % grp->cg_count; i > 0; i--) {
5866 		MPASS(CPU_FFS(&cs));
5867 		CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5868 	}
5869 	MPASS(CPU_FFS(&cs));
5870 	return CPU_FFS(&cs) - 1;
5871 }
5872 #else
5873 static int
5874 find_close_core(int cpu, int core_offset __unused)
5875 {
5876 	return cpu;
5877 }
5878 #endif
5879 
5880 static int
5881 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5882 {
5883 	switch (type) {
5884 	case IFLIB_INTR_TX:
5885 		/* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5886 		/* XXX handle multiple RX threads per core and more than two core per L2 group */
5887 		return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5888 	case IFLIB_INTR_RX:
5889 	case IFLIB_INTR_RXTX:
5890 		/* RX queues get the specified core */
5891 		return qid / CPU_COUNT(&ctx->ifc_cpus);
5892 	default:
5893 		return -1;
5894 	}
5895 }
5896 #else
5897 #define get_core_offset(ctx, type, qid)	CPU_FIRST()
5898 #define find_close_core(cpuid, tid)	CPU_FIRST()
5899 #define find_nth(ctx, gid)		CPU_FIRST()
5900 #endif
5901 
5902 /* Just to avoid copy/paste */
5903 static inline int
5904 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
5905     int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
5906     const char *name)
5907 {
5908 	device_t dev;
5909 	int co, cpuid, err, tid;
5910 
5911 	dev = ctx->ifc_dev;
5912 	co = ctx->ifc_sysctl_core_offset;
5913 	if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX)
5914 		co += ctx->ifc_softc_ctx.isc_nrxqsets;
5915 	cpuid = find_nth(ctx, qid + co);
5916 	tid = get_core_offset(ctx, type, qid);
5917 	if (tid < 0) {
5918 		device_printf(dev, "get_core_offset failed\n");
5919 		return (EOPNOTSUPP);
5920 	}
5921 	cpuid = find_close_core(cpuid, tid);
5922 	err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res,
5923 	    name);
5924 	if (err) {
5925 		device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
5926 		return (err);
5927 	}
5928 #ifdef notyet
5929 	if (cpuid > ctx->ifc_cpuid_highest)
5930 		ctx->ifc_cpuid_highest = cpuid;
5931 #endif
5932 	return (0);
5933 }
5934 
5935 int
5936 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5937 			iflib_intr_type_t type, driver_filter_t *filter,
5938 			void *filter_arg, int qid, const char *name)
5939 {
5940 	device_t dev;
5941 	struct grouptask *gtask;
5942 	struct taskqgroup *tqg;
5943 	iflib_filter_info_t info;
5944 	gtask_fn_t *fn;
5945 	int tqrid, err;
5946 	driver_filter_t *intr_fast;
5947 	void *q;
5948 
5949 	info = &ctx->ifc_filter_info;
5950 	tqrid = rid;
5951 
5952 	switch (type) {
5953 	/* XXX merge tx/rx for netmap? */
5954 	case IFLIB_INTR_TX:
5955 		q = &ctx->ifc_txqs[qid];
5956 		info = &ctx->ifc_txqs[qid].ift_filter_info;
5957 		gtask = &ctx->ifc_txqs[qid].ift_task;
5958 		tqg = qgroup_if_io_tqg;
5959 		fn = _task_fn_tx;
5960 		intr_fast = iflib_fast_intr;
5961 		GROUPTASK_INIT(gtask, 0, fn, q);
5962 		ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
5963 		break;
5964 	case IFLIB_INTR_RX:
5965 		q = &ctx->ifc_rxqs[qid];
5966 		info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5967 		gtask = &ctx->ifc_rxqs[qid].ifr_task;
5968 		tqg = qgroup_if_io_tqg;
5969 		fn = _task_fn_rx;
5970 		intr_fast = iflib_fast_intr;
5971 		NET_GROUPTASK_INIT(gtask, 0, fn, q);
5972 		break;
5973 	case IFLIB_INTR_RXTX:
5974 		q = &ctx->ifc_rxqs[qid];
5975 		info = &ctx->ifc_rxqs[qid].ifr_filter_info;
5976 		gtask = &ctx->ifc_rxqs[qid].ifr_task;
5977 		tqg = qgroup_if_io_tqg;
5978 		fn = _task_fn_rx;
5979 		intr_fast = iflib_fast_intr_rxtx;
5980 		NET_GROUPTASK_INIT(gtask, 0, fn, q);
5981 		break;
5982 	case IFLIB_INTR_ADMIN:
5983 		q = ctx;
5984 		tqrid = -1;
5985 		info = &ctx->ifc_filter_info;
5986 		gtask = &ctx->ifc_admin_task;
5987 		tqg = qgroup_if_config_tqg;
5988 		fn = _task_fn_admin;
5989 		intr_fast = iflib_fast_intr_ctx;
5990 		break;
5991 	default:
5992 		device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
5993 		    __func__);
5994 		return (EINVAL);
5995 	}
5996 
5997 	info->ifi_filter = filter;
5998 	info->ifi_filter_arg = filter_arg;
5999 	info->ifi_task = gtask;
6000 	info->ifi_ctx = q;
6001 
6002 	dev = ctx->ifc_dev;
6003 	err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info,  name);
6004 	if (err != 0) {
6005 		device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
6006 		return (err);
6007 	}
6008 	if (type == IFLIB_INTR_ADMIN)
6009 		return (0);
6010 
6011 	if (tqrid != -1) {
6012 		err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6013 		    q, name);
6014 		if (err)
6015 			return (err);
6016 	} else {
6017 		taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
6018 	}
6019 
6020 	return (0);
6021 }
6022 
6023 void
6024 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
6025 {
6026 	struct grouptask *gtask;
6027 	struct taskqgroup *tqg;
6028 	gtask_fn_t *fn;
6029 	void *q;
6030 	int err;
6031 
6032 	switch (type) {
6033 	case IFLIB_INTR_TX:
6034 		q = &ctx->ifc_txqs[qid];
6035 		gtask = &ctx->ifc_txqs[qid].ift_task;
6036 		tqg = qgroup_if_io_tqg;
6037 		fn = _task_fn_tx;
6038 		break;
6039 	case IFLIB_INTR_RX:
6040 		q = &ctx->ifc_rxqs[qid];
6041 		gtask = &ctx->ifc_rxqs[qid].ifr_task;
6042 		tqg = qgroup_if_io_tqg;
6043 		fn = _task_fn_rx;
6044 		break;
6045 	case IFLIB_INTR_IOV:
6046 		q = ctx;
6047 		gtask = &ctx->ifc_vflr_task;
6048 		tqg = qgroup_if_config_tqg;
6049 		fn = _task_fn_iov;
6050 		break;
6051 	default:
6052 		panic("unknown net intr type");
6053 	}
6054 	GROUPTASK_INIT(gtask, 0, fn, q);
6055 	if (irq != NULL) {
6056 		err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6057 		    q, name);
6058 		if (err)
6059 			taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev,
6060 			    irq->ii_res, name);
6061 	} else {
6062 		taskqgroup_attach(tqg, gtask, q, NULL, NULL, name);
6063 	}
6064 }
6065 
6066 void
6067 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6068 {
6069 
6070 	if (irq->ii_tag)
6071 		bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6072 
6073 	if (irq->ii_res)
6074 		bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6075 		    rman_get_rid(irq->ii_res), irq->ii_res);
6076 }
6077 
6078 static int
6079 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6080 {
6081 	iflib_txq_t txq = ctx->ifc_txqs;
6082 	iflib_rxq_t rxq = ctx->ifc_rxqs;
6083 	if_irq_t irq = &ctx->ifc_legacy_irq;
6084 	iflib_filter_info_t info;
6085 	device_t dev;
6086 	struct grouptask *gtask;
6087 	struct resource *res;
6088 	struct taskqgroup *tqg;
6089 	gtask_fn_t *fn;
6090 	void *q;
6091 	int err, tqrid;
6092 	bool rx_only;
6093 
6094 	q = &ctx->ifc_rxqs[0];
6095 	info = &rxq[0].ifr_filter_info;
6096 	gtask = &rxq[0].ifr_task;
6097 	tqg = qgroup_if_io_tqg;
6098 	tqrid = *rid;
6099 	fn = _task_fn_rx;
6100 	rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0;
6101 
6102 	ctx->ifc_flags |= IFC_LEGACY;
6103 	info->ifi_filter = filter;
6104 	info->ifi_filter_arg = filter_arg;
6105 	info->ifi_task = gtask;
6106 	info->ifi_ctx = rx_only ? ctx : q;
6107 
6108 	dev = ctx->ifc_dev;
6109 	/* We allocate a single interrupt resource */
6110 	err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx :
6111 	    iflib_fast_intr_rxtx, NULL, info, name);
6112 	if (err != 0)
6113 		return (err);
6114 	GROUPTASK_INIT(gtask, 0, fn, q);
6115 	res = irq->ii_res;
6116 	taskqgroup_attach(tqg, gtask, q, dev, res, name);
6117 
6118 	GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6119 	taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6120 	    "tx");
6121 	return (0);
6122 }
6123 
6124 void
6125 iflib_led_create(if_ctx_t ctx)
6126 {
6127 
6128 	ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6129 	    device_get_nameunit(ctx->ifc_dev));
6130 }
6131 
6132 void
6133 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6134 {
6135 
6136 	GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6137 }
6138 
6139 void
6140 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6141 {
6142 
6143 	GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6144 }
6145 
6146 void
6147 iflib_admin_intr_deferred(if_ctx_t ctx)
6148 {
6149 #ifdef INVARIANTS
6150 	struct grouptask *gtask;
6151 
6152 	gtask = &ctx->ifc_admin_task;
6153 	MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
6154 #endif
6155 
6156 	GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
6157 }
6158 
6159 void
6160 iflib_iov_intr_deferred(if_ctx_t ctx)
6161 {
6162 
6163 	GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6164 }
6165 
6166 void
6167 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name)
6168 {
6169 
6170 	taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6171 	    name);
6172 }
6173 
6174 void
6175 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6176 	const char *name)
6177 {
6178 
6179 	GROUPTASK_INIT(gtask, 0, fn, ctx);
6180 	taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
6181 	    name);
6182 }
6183 
6184 void
6185 iflib_config_gtask_deinit(struct grouptask *gtask)
6186 {
6187 
6188 	taskqgroup_detach(qgroup_if_config_tqg, gtask);
6189 }
6190 
6191 void
6192 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6193 {
6194 	if_t ifp = ctx->ifc_ifp;
6195 	iflib_txq_t txq = ctx->ifc_txqs;
6196 
6197 	if_setbaudrate(ifp, baudrate);
6198 	if (baudrate >= IF_Gbps(10)) {
6199 		STATE_LOCK(ctx);
6200 		ctx->ifc_flags |= IFC_PREFETCH;
6201 		STATE_UNLOCK(ctx);
6202 	}
6203 	/* If link down, disable watchdog */
6204 	if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6205 		for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6206 			txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6207 	}
6208 	ctx->ifc_link_state = link_state;
6209 	if_link_state_change(ifp, link_state);
6210 }
6211 
6212 static int
6213 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6214 {
6215 	int credits;
6216 #ifdef INVARIANTS
6217 	int credits_pre = txq->ift_cidx_processed;
6218 #endif
6219 
6220 	bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6221 	    BUS_DMASYNC_POSTREAD);
6222 	if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6223 		return (0);
6224 
6225 	txq->ift_processed += credits;
6226 	txq->ift_cidx_processed += credits;
6227 
6228 	MPASS(credits_pre + credits == txq->ift_cidx_processed);
6229 	if (txq->ift_cidx_processed >= txq->ift_size)
6230 		txq->ift_cidx_processed -= txq->ift_size;
6231 	return (credits);
6232 }
6233 
6234 static int
6235 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6236 {
6237 	iflib_fl_t fl;
6238 	u_int i;
6239 
6240 	for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6241 		bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6242 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6243 	return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6244 	    budget));
6245 }
6246 
6247 void
6248 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6249 	const char *description, if_int_delay_info_t info,
6250 	int offset, int value)
6251 {
6252 	info->iidi_ctx = ctx;
6253 	info->iidi_offset = offset;
6254 	info->iidi_value = value;
6255 	SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6256 	    SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6257 	    OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
6258 	    info, 0, iflib_sysctl_int_delay, "I", description);
6259 }
6260 
6261 struct sx *
6262 iflib_ctx_lock_get(if_ctx_t ctx)
6263 {
6264 
6265 	return (&ctx->ifc_ctx_sx);
6266 }
6267 
6268 static int
6269 iflib_msix_init(if_ctx_t ctx)
6270 {
6271 	device_t dev = ctx->ifc_dev;
6272 	if_shared_ctx_t sctx = ctx->ifc_sctx;
6273 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6274 	int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6275 	int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6276 
6277 	iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6278 	iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6279 
6280 	if (bootverbose)
6281 		device_printf(dev, "msix_init qsets capped at %d\n",
6282 		    imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6283 
6284 	/* Override by tuneable */
6285 	if (scctx->isc_disable_msix)
6286 		goto msi;
6287 
6288 	/* First try MSI-X */
6289 	if ((msgs = pci_msix_count(dev)) == 0) {
6290 		if (bootverbose)
6291 			device_printf(dev, "MSI-X not supported or disabled\n");
6292 		goto msi;
6293 	}
6294 
6295 	bar = ctx->ifc_softc_ctx.isc_msix_bar;
6296 	/*
6297 	 * bar == -1 => "trust me I know what I'm doing"
6298 	 * Some drivers are for hardware that is so shoddily
6299 	 * documented that no one knows which bars are which
6300 	 * so the developer has to map all bars. This hack
6301 	 * allows shoddy garbage to use MSI-X in this framework.
6302 	 */
6303 	if (bar != -1) {
6304 		ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6305 	            SYS_RES_MEMORY, &bar, RF_ACTIVE);
6306 		if (ctx->ifc_msix_mem == NULL) {
6307 			device_printf(dev, "Unable to map MSI-X table\n");
6308 			goto msi;
6309 		}
6310 	}
6311 
6312 	admincnt = sctx->isc_admin_intrcnt;
6313 #if IFLIB_DEBUG
6314 	/* use only 1 qset in debug mode */
6315 	queuemsgs = min(msgs - admincnt, 1);
6316 #else
6317 	queuemsgs = msgs - admincnt;
6318 #endif
6319 #ifdef RSS
6320 	queues = imin(queuemsgs, rss_getnumbuckets());
6321 #else
6322 	queues = queuemsgs;
6323 #endif
6324 	queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6325 	if (bootverbose)
6326 		device_printf(dev,
6327 		    "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6328 		    CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6329 #ifdef  RSS
6330 	/* If we're doing RSS, clamp at the number of RSS buckets */
6331 	if (queues > rss_getnumbuckets())
6332 		queues = rss_getnumbuckets();
6333 #endif
6334 	if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6335 		rx_queues = iflib_num_rx_queues;
6336 	else
6337 		rx_queues = queues;
6338 
6339 	if (rx_queues > scctx->isc_nrxqsets)
6340 		rx_queues = scctx->isc_nrxqsets;
6341 
6342 	/*
6343 	 * We want this to be all logical CPUs by default
6344 	 */
6345 	if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6346 		tx_queues = iflib_num_tx_queues;
6347 	else
6348 		tx_queues = mp_ncpus;
6349 
6350 	if (tx_queues > scctx->isc_ntxqsets)
6351 		tx_queues = scctx->isc_ntxqsets;
6352 
6353 	if (ctx->ifc_sysctl_qs_eq_override == 0) {
6354 #ifdef INVARIANTS
6355 		if (tx_queues != rx_queues)
6356 			device_printf(dev,
6357 			    "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6358 			    min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6359 #endif
6360 		tx_queues = min(rx_queues, tx_queues);
6361 		rx_queues = min(rx_queues, tx_queues);
6362 	}
6363 
6364 	vectors = rx_queues + admincnt;
6365 	if (msgs < vectors) {
6366 		device_printf(dev,
6367 		    "insufficient number of MSI-X vectors "
6368 		    "(supported %d, need %d)\n", msgs, vectors);
6369 		goto msi;
6370 	}
6371 
6372 	device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6373 	    tx_queues);
6374 	msgs = vectors;
6375 	if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6376 		if (vectors != msgs) {
6377 			device_printf(dev,
6378 			    "Unable to allocate sufficient MSI-X vectors "
6379 			    "(got %d, need %d)\n", vectors, msgs);
6380 			pci_release_msi(dev);
6381 			if (bar != -1) {
6382 				bus_release_resource(dev, SYS_RES_MEMORY, bar,
6383 				    ctx->ifc_msix_mem);
6384 				ctx->ifc_msix_mem = NULL;
6385 			}
6386 			goto msi;
6387 		}
6388 		device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6389 		    vectors);
6390 		scctx->isc_vectors = vectors;
6391 		scctx->isc_nrxqsets = rx_queues;
6392 		scctx->isc_ntxqsets = tx_queues;
6393 		scctx->isc_intr = IFLIB_INTR_MSIX;
6394 
6395 		return (vectors);
6396 	} else {
6397 		device_printf(dev,
6398 		    "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6399 		    err);
6400 		if (bar != -1) {
6401 			bus_release_resource(dev, SYS_RES_MEMORY, bar,
6402 			    ctx->ifc_msix_mem);
6403 			ctx->ifc_msix_mem = NULL;
6404 		}
6405 	}
6406 
6407 msi:
6408 	vectors = pci_msi_count(dev);
6409 	scctx->isc_nrxqsets = 1;
6410 	scctx->isc_ntxqsets = 1;
6411 	scctx->isc_vectors = vectors;
6412 	if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6413 		device_printf(dev,"Using an MSI interrupt\n");
6414 		scctx->isc_intr = IFLIB_INTR_MSI;
6415 	} else {
6416 		scctx->isc_vectors = 1;
6417 		device_printf(dev,"Using a Legacy interrupt\n");
6418 		scctx->isc_intr = IFLIB_INTR_LEGACY;
6419 	}
6420 
6421 	return (vectors);
6422 }
6423 
6424 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6425 
6426 static int
6427 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6428 {
6429 	int rc;
6430 	uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6431 	struct sbuf *sb;
6432 	const char *ring_state = "UNKNOWN";
6433 
6434 	/* XXX needed ? */
6435 	rc = sysctl_wire_old_buffer(req, 0);
6436 	MPASS(rc == 0);
6437 	if (rc != 0)
6438 		return (rc);
6439 	sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6440 	MPASS(sb != NULL);
6441 	if (sb == NULL)
6442 		return (ENOMEM);
6443 	if (state[3] <= 3)
6444 		ring_state = ring_states[state[3]];
6445 
6446 	sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6447 		    state[0], state[1], state[2], ring_state);
6448 	rc = sbuf_finish(sb);
6449 	sbuf_delete(sb);
6450         return(rc);
6451 }
6452 
6453 enum iflib_ndesc_handler {
6454 	IFLIB_NTXD_HANDLER,
6455 	IFLIB_NRXD_HANDLER,
6456 };
6457 
6458 static int
6459 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6460 {
6461 	if_ctx_t ctx = (void *)arg1;
6462 	enum iflib_ndesc_handler type = arg2;
6463 	char buf[256] = {0};
6464 	qidx_t *ndesc;
6465 	char *p, *next;
6466 	int nqs, rc, i;
6467 
6468 	nqs = 8;
6469 	switch(type) {
6470 	case IFLIB_NTXD_HANDLER:
6471 		ndesc = ctx->ifc_sysctl_ntxds;
6472 		if (ctx->ifc_sctx)
6473 			nqs = ctx->ifc_sctx->isc_ntxqs;
6474 		break;
6475 	case IFLIB_NRXD_HANDLER:
6476 		ndesc = ctx->ifc_sysctl_nrxds;
6477 		if (ctx->ifc_sctx)
6478 			nqs = ctx->ifc_sctx->isc_nrxqs;
6479 		break;
6480 	default:
6481 		printf("%s: unhandled type\n", __func__);
6482 		return (EINVAL);
6483 	}
6484 	if (nqs == 0)
6485 		nqs = 8;
6486 
6487 	for (i=0; i<8; i++) {
6488 		if (i >= nqs)
6489 			break;
6490 		if (i)
6491 			strcat(buf, ",");
6492 		sprintf(strchr(buf, 0), "%d", ndesc[i]);
6493 	}
6494 
6495 	rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6496 	if (rc || req->newptr == NULL)
6497 		return rc;
6498 
6499 	for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6500 	    i++, p = strsep(&next, " ,")) {
6501 		ndesc[i] = strtoul(p, NULL, 10);
6502 	}
6503 
6504 	return(rc);
6505 }
6506 
6507 #define NAME_BUFLEN 32
6508 static void
6509 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6510 {
6511         device_t dev = iflib_get_dev(ctx);
6512 	struct sysctl_oid_list *child, *oid_list;
6513 	struct sysctl_ctx_list *ctx_list;
6514 	struct sysctl_oid *node;
6515 
6516 	ctx_list = device_get_sysctl_ctx(dev);
6517 	child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6518 	ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6519 						      CTLFLAG_RD, NULL, "IFLIB fields");
6520 	oid_list = SYSCTL_CHILDREN(node);
6521 
6522 	SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6523 		       CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
6524 		       "driver version");
6525 
6526 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6527 		       CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6528 			"# of txqs to use, 0 => use default #");
6529 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6530 		       CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6531 			"# of rxqs to use, 0 => use default #");
6532 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6533 		       CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6534                        "permit #txq != #rxq");
6535 	SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6536                       CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6537                       "disable MSI-X (default 0)");
6538 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6539 		       CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6540 		       "set the RX budget");
6541 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6542 		       CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6543 		       "cause TX to abdicate instead of running to completion");
6544 	ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6545 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6546 		       CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6547 		       "offset to start using cores at");
6548 	SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6549 		       CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6550 		       "use separate cores for TX and RX");
6551 
6552 	/* XXX change for per-queue sizes */
6553 	SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6554 		       CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER,
6555                        mp_ndesc_handler, "A",
6556 		       "list of # of TX descriptors to use, 0 = use default #");
6557 	SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6558 		       CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER,
6559                        mp_ndesc_handler, "A",
6560 		       "list of # of RX descriptors to use, 0 = use default #");
6561 }
6562 
6563 static void
6564 iflib_add_device_sysctl_post(if_ctx_t ctx)
6565 {
6566 	if_shared_ctx_t sctx = ctx->ifc_sctx;
6567 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6568         device_t dev = iflib_get_dev(ctx);
6569 	struct sysctl_oid_list *child;
6570 	struct sysctl_ctx_list *ctx_list;
6571 	iflib_fl_t fl;
6572 	iflib_txq_t txq;
6573 	iflib_rxq_t rxq;
6574 	int i, j;
6575 	char namebuf[NAME_BUFLEN];
6576 	char *qfmt;
6577 	struct sysctl_oid *queue_node, *fl_node, *node;
6578 	struct sysctl_oid_list *queue_list, *fl_list;
6579 	ctx_list = device_get_sysctl_ctx(dev);
6580 
6581 	node = ctx->ifc_sysctl_node;
6582 	child = SYSCTL_CHILDREN(node);
6583 
6584 	if (scctx->isc_ntxqsets > 100)
6585 		qfmt = "txq%03d";
6586 	else if (scctx->isc_ntxqsets > 10)
6587 		qfmt = "txq%02d";
6588 	else
6589 		qfmt = "txq%d";
6590 	for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6591 		snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6592 		queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6593 					     CTLFLAG_RD, NULL, "Queue Name");
6594 		queue_list = SYSCTL_CHILDREN(queue_node);
6595 #if MEMORY_LOGGING
6596 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6597 				CTLFLAG_RD,
6598 				&txq->ift_dequeued, "total mbufs freed");
6599 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6600 				CTLFLAG_RD,
6601 				&txq->ift_enqueued, "total mbufs enqueued");
6602 #endif
6603 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6604 				   CTLFLAG_RD,
6605 				   &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6606 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6607 				   CTLFLAG_RD,
6608 				   &txq->ift_pullups, "# of times m_pullup was called");
6609 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6610 				   CTLFLAG_RD,
6611 				   &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6612 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6613 				   CTLFLAG_RD,
6614 				   &txq->ift_no_desc_avail, "# of times no descriptors were available");
6615 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6616 				   CTLFLAG_RD,
6617 				   &txq->ift_map_failed, "# of times DMA map failed");
6618 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6619 				   CTLFLAG_RD,
6620 				   &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6621 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6622 				   CTLFLAG_RD,
6623 				   &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6624 		SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6625 				   CTLFLAG_RD,
6626 				   &txq->ift_pidx, 1, "Producer Index");
6627 		SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6628 				   CTLFLAG_RD,
6629 				   &txq->ift_cidx, 1, "Consumer Index");
6630 		SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6631 				   CTLFLAG_RD,
6632 				   &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6633 		SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6634 				   CTLFLAG_RD,
6635 				   &txq->ift_in_use, 1, "descriptors in use");
6636 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6637 				   CTLFLAG_RD,
6638 				   &txq->ift_processed, "descriptors procesed for clean");
6639 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6640 				   CTLFLAG_RD,
6641 				   &txq->ift_cleaned, "total cleaned");
6642 		SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6643 				CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state),
6644 				0, mp_ring_state_handler, "A", "soft ring state");
6645 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6646 				       CTLFLAG_RD, &txq->ift_br->enqueues,
6647 				       "# of enqueues to the mp_ring for this queue");
6648 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6649 				       CTLFLAG_RD, &txq->ift_br->drops,
6650 				       "# of drops in the mp_ring for this queue");
6651 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6652 				       CTLFLAG_RD, &txq->ift_br->starts,
6653 				       "# of normal consumer starts in the mp_ring for this queue");
6654 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6655 				       CTLFLAG_RD, &txq->ift_br->stalls,
6656 					       "# of consumer stalls in the mp_ring for this queue");
6657 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6658 			       CTLFLAG_RD, &txq->ift_br->restarts,
6659 				       "# of consumer restarts in the mp_ring for this queue");
6660 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6661 				       CTLFLAG_RD, &txq->ift_br->abdications,
6662 				       "# of consumer abdications in the mp_ring for this queue");
6663 	}
6664 
6665 	if (scctx->isc_nrxqsets > 100)
6666 		qfmt = "rxq%03d";
6667 	else if (scctx->isc_nrxqsets > 10)
6668 		qfmt = "rxq%02d";
6669 	else
6670 		qfmt = "rxq%d";
6671 	for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6672 		snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6673 		queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6674 					     CTLFLAG_RD, NULL, "Queue Name");
6675 		queue_list = SYSCTL_CHILDREN(queue_node);
6676 		if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6677 			SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6678 				       CTLFLAG_RD,
6679 				       &rxq->ifr_cq_cidx, 1, "Consumer Index");
6680 		}
6681 
6682 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6683 			snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6684 			fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6685 						     CTLFLAG_RD, NULL, "freelist Name");
6686 			fl_list = SYSCTL_CHILDREN(fl_node);
6687 			SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6688 				       CTLFLAG_RD,
6689 				       &fl->ifl_pidx, 1, "Producer Index");
6690 			SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6691 				       CTLFLAG_RD,
6692 				       &fl->ifl_cidx, 1, "Consumer Index");
6693 			SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6694 				       CTLFLAG_RD,
6695 				       &fl->ifl_credits, 1, "credits available");
6696 #if MEMORY_LOGGING
6697 			SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6698 					CTLFLAG_RD,
6699 					&fl->ifl_m_enqueued, "mbufs allocated");
6700 			SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6701 					CTLFLAG_RD,
6702 					&fl->ifl_m_dequeued, "mbufs freed");
6703 			SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6704 					CTLFLAG_RD,
6705 					&fl->ifl_cl_enqueued, "clusters allocated");
6706 			SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6707 					CTLFLAG_RD,
6708 					&fl->ifl_cl_dequeued, "clusters freed");
6709 #endif
6710 
6711 		}
6712 	}
6713 
6714 }
6715 
6716 void
6717 iflib_request_reset(if_ctx_t ctx)
6718 {
6719 
6720 	STATE_LOCK(ctx);
6721 	ctx->ifc_flags |= IFC_DO_RESET;
6722 	STATE_UNLOCK(ctx);
6723 }
6724 
6725 #ifndef __NO_STRICT_ALIGNMENT
6726 static struct mbuf *
6727 iflib_fixup_rx(struct mbuf *m)
6728 {
6729 	struct mbuf *n;
6730 
6731 	if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6732 		bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6733 		m->m_data += ETHER_HDR_LEN;
6734 		n = m;
6735 	} else {
6736 		MGETHDR(n, M_NOWAIT, MT_DATA);
6737 		if (n == NULL) {
6738 			m_freem(m);
6739 			return (NULL);
6740 		}
6741 		bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6742 		m->m_data += ETHER_HDR_LEN;
6743 		m->m_len -= ETHER_HDR_LEN;
6744 		n->m_len = ETHER_HDR_LEN;
6745 		M_MOVE_PKTHDR(n, m);
6746 		n->m_next = m;
6747 	}
6748 	return (n);
6749 }
6750 #endif
6751 
6752 #ifdef DEBUGNET
6753 static void
6754 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6755 {
6756 	if_ctx_t ctx;
6757 
6758 	ctx = if_getsoftc(ifp);
6759 	CTX_LOCK(ctx);
6760 	*nrxr = NRXQSETS(ctx);
6761 	*ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6762 	*clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6763 	CTX_UNLOCK(ctx);
6764 }
6765 
6766 static void
6767 iflib_debugnet_event(if_t ifp, enum debugnet_ev event)
6768 {
6769 	if_ctx_t ctx;
6770 	if_softc_ctx_t scctx;
6771 	iflib_fl_t fl;
6772 	iflib_rxq_t rxq;
6773 	int i, j;
6774 
6775 	ctx = if_getsoftc(ifp);
6776 	scctx = &ctx->ifc_softc_ctx;
6777 
6778 	switch (event) {
6779 	case DEBUGNET_START:
6780 		for (i = 0; i < scctx->isc_nrxqsets; i++) {
6781 			rxq = &ctx->ifc_rxqs[i];
6782 			for (j = 0; j < rxq->ifr_nfl; j++) {
6783 				fl = rxq->ifr_fl;
6784 				fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6785 			}
6786 		}
6787 		iflib_no_tx_batch = 1;
6788 		break;
6789 	default:
6790 		break;
6791 	}
6792 }
6793 
6794 static int
6795 iflib_debugnet_transmit(if_t ifp, struct mbuf *m)
6796 {
6797 	if_ctx_t ctx;
6798 	iflib_txq_t txq;
6799 	int error;
6800 
6801 	ctx = if_getsoftc(ifp);
6802 	if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6803 	    IFF_DRV_RUNNING)
6804 		return (EBUSY);
6805 
6806 	txq = &ctx->ifc_txqs[0];
6807 	error = iflib_encap(txq, &m);
6808 	if (error == 0)
6809 		(void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6810 	return (error);
6811 }
6812 
6813 static int
6814 iflib_debugnet_poll(if_t ifp, int count)
6815 {
6816 	struct epoch_tracker et;
6817 	if_ctx_t ctx;
6818 	if_softc_ctx_t scctx;
6819 	iflib_txq_t txq;
6820 	int i;
6821 
6822 	ctx = if_getsoftc(ifp);
6823 	scctx = &ctx->ifc_softc_ctx;
6824 
6825 	if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6826 	    IFF_DRV_RUNNING)
6827 		return (EBUSY);
6828 
6829 	txq = &ctx->ifc_txqs[0];
6830 	(void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6831 
6832 	NET_EPOCH_ENTER(et);
6833 	for (i = 0; i < scctx->isc_nrxqsets; i++)
6834 		(void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6835 	NET_EPOCH_EXIT(et);
6836 	return (0);
6837 }
6838 #endif /* DEBUGNET */
6839