1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include "opt_inet.h" 30 #include "opt_inet6.h" 31 #include "opt_acpi.h" 32 #include "opt_sched.h" 33 34 #include <sys/param.h> 35 #include <sys/types.h> 36 #include <sys/bus.h> 37 #include <sys/eventhandler.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/module.h> 42 #include <sys/kobj.h> 43 #include <sys/rman.h> 44 #include <sys/sbuf.h> 45 #include <sys/smp.h> 46 #include <sys/socket.h> 47 #include <sys/sockio.h> 48 #include <sys/sysctl.h> 49 #include <sys/syslog.h> 50 #include <sys/taskqueue.h> 51 #include <sys/limits.h> 52 53 #include <net/if.h> 54 #include <net/if_var.h> 55 #include <net/if_private.h> 56 #include <net/if_types.h> 57 #include <net/if_media.h> 58 #include <net/bpf.h> 59 #include <net/ethernet.h> 60 #include <net/mp_ring.h> 61 #include <net/debugnet.h> 62 #include <net/pfil.h> 63 #include <net/vnet.h> 64 65 #include <netinet/in.h> 66 #include <netinet/in_pcb.h> 67 #include <netinet/tcp_lro.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/if_ether.h> 70 #include <netinet/ip.h> 71 #include <netinet/ip6.h> 72 #include <netinet/tcp.h> 73 #include <netinet/udp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 90 #include "ifdi_if.h" 91 92 #ifdef PCI_IOV 93 #include <dev/pci/pci_iov.h> 94 #endif 95 96 #include <sys/bitstring.h> 97 /* 98 * enable accounting of every mbuf as it comes in to and goes out of 99 * iflib's software descriptor references 100 */ 101 #define MEMORY_LOGGING 0 102 /* 103 * Enable mbuf vectors for compressing long mbuf chains 104 */ 105 106 /* 107 * NB: 108 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 109 * we prefetch needs to be determined by the time spent in m_free vis a vis 110 * the cost of a prefetch. This will of course vary based on the workload: 111 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 112 * is quite expensive, thus suggesting very little prefetch. 113 * - small packet forwarding which is just returning a single mbuf to 114 * UMA will typically be very fast vis a vis the cost of a memory 115 * access. 116 */ 117 118 /* 119 * File organization: 120 * - private structures 121 * - iflib private utility functions 122 * - ifnet functions 123 * - vlan registry and other exported functions 124 * - iflib public core functions 125 * 126 * 127 */ 128 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 129 130 #define IFLIB_RXEOF_MORE (1U << 0) 131 #define IFLIB_RXEOF_EMPTY (2U << 0) 132 133 struct iflib_txq; 134 typedef struct iflib_txq *iflib_txq_t; 135 struct iflib_rxq; 136 typedef struct iflib_rxq *iflib_rxq_t; 137 struct iflib_fl; 138 typedef struct iflib_fl *iflib_fl_t; 139 140 struct iflib_ctx; 141 142 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 143 static void iflib_timer(void *arg); 144 static void iflib_tqg_detach(if_ctx_t ctx); 145 146 typedef struct iflib_filter_info { 147 driver_filter_t *ifi_filter; 148 void *ifi_filter_arg; 149 struct grouptask *ifi_task; 150 void *ifi_ctx; 151 } *iflib_filter_info_t; 152 153 struct iflib_ctx { 154 KOBJ_FIELDS; 155 /* 156 * Pointer to hardware driver's softc 157 */ 158 void *ifc_softc; 159 device_t ifc_dev; 160 if_t ifc_ifp; 161 162 cpuset_t ifc_cpus; 163 if_shared_ctx_t ifc_sctx; 164 struct if_softc_ctx ifc_softc_ctx; 165 166 struct sx ifc_ctx_sx; 167 struct mtx ifc_state_mtx; 168 169 iflib_txq_t ifc_txqs; 170 iflib_rxq_t ifc_rxqs; 171 uint32_t ifc_if_flags; 172 uint32_t ifc_flags; 173 uint32_t ifc_max_fl_buf_size; 174 uint32_t ifc_rx_mbuf_sz; 175 176 int ifc_link_state; 177 int ifc_watchdog_events; 178 struct cdev *ifc_led_dev; 179 struct resource *ifc_msix_mem; 180 181 struct if_irq ifc_legacy_irq; 182 struct task ifc_admin_task; 183 struct task ifc_vflr_task; 184 struct taskqueue *ifc_tq; 185 struct iflib_filter_info ifc_filter_info; 186 struct ifmedia ifc_media; 187 struct ifmedia *ifc_mediap; 188 189 struct sysctl_oid *ifc_sysctl_node; 190 uint16_t ifc_sysctl_ntxqs; 191 uint16_t ifc_sysctl_nrxqs; 192 uint16_t ifc_sysctl_qs_eq_override; 193 uint16_t ifc_sysctl_rx_budget; 194 uint16_t ifc_sysctl_tx_abdicate; 195 uint16_t ifc_sysctl_core_offset; 196 #define CORE_OFFSET_UNSPECIFIED 0xffff 197 uint8_t ifc_sysctl_separate_txrx; 198 uint8_t ifc_sysctl_use_logical_cores; 199 uint16_t ifc_sysctl_extra_msix_vectors; 200 bool ifc_cpus_are_physical_cores; 201 202 qidx_t ifc_sysctl_ntxds[8]; 203 qidx_t ifc_sysctl_nrxds[8]; 204 struct if_txrx ifc_txrx; 205 #define isc_txd_encap ifc_txrx.ift_txd_encap 206 #define isc_txd_flush ifc_txrx.ift_txd_flush 207 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 208 #define isc_rxd_available ifc_txrx.ift_rxd_available 209 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 210 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 211 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 212 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 213 #define isc_txq_select ifc_txrx.ift_txq_select 214 #define isc_txq_select_v2 ifc_txrx.ift_txq_select_v2 215 216 eventhandler_tag ifc_vlan_attach_event; 217 eventhandler_tag ifc_vlan_detach_event; 218 struct ether_addr ifc_mac; 219 }; 220 221 void * 222 iflib_get_softc(if_ctx_t ctx) 223 { 224 225 return (ctx->ifc_softc); 226 } 227 228 device_t 229 iflib_get_dev(if_ctx_t ctx) 230 { 231 232 return (ctx->ifc_dev); 233 } 234 235 if_t 236 iflib_get_ifp(if_ctx_t ctx) 237 { 238 239 return (ctx->ifc_ifp); 240 } 241 242 struct ifmedia * 243 iflib_get_media(if_ctx_t ctx) 244 { 245 246 return (ctx->ifc_mediap); 247 } 248 249 void 250 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 251 { 252 253 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 254 } 255 256 if_softc_ctx_t 257 iflib_get_softc_ctx(if_ctx_t ctx) 258 { 259 260 return (&ctx->ifc_softc_ctx); 261 } 262 263 if_shared_ctx_t 264 iflib_get_sctx(if_ctx_t ctx) 265 { 266 267 return (ctx->ifc_sctx); 268 } 269 270 uint16_t 271 iflib_get_extra_msix_vectors_sysctl(if_ctx_t ctx) 272 { 273 274 return (ctx->ifc_sysctl_extra_msix_vectors); 275 } 276 277 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 278 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE / sizeof(void *)) 279 #define CACHE_PTR_NEXT(ptr) ((void *)(roundup2(ptr, CACHE_LINE_SIZE))) 280 281 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 282 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 283 284 typedef struct iflib_sw_rx_desc_array { 285 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 286 struct mbuf **ifsd_m; /* pkthdr mbufs */ 287 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 288 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 289 } iflib_rxsd_array_t; 290 291 typedef struct iflib_sw_tx_desc_array { 292 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 293 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 294 struct mbuf **ifsd_m; /* pkthdr mbufs */ 295 } if_txsd_vec_t; 296 297 /* magic number that should be high enough for any hardware */ 298 #define IFLIB_MAX_TX_SEGS 128 299 #define IFLIB_RX_COPY_THRESH 128 300 #define IFLIB_MAX_RX_REFRESH 32 301 /* The minimum descriptors per second before we start coalescing */ 302 #define IFLIB_MIN_DESC_SEC 16384 303 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 304 #define IFLIB_QUEUE_IDLE 0 305 #define IFLIB_QUEUE_HUNG 1 306 #define IFLIB_QUEUE_WORKING 2 307 /* maximum number of txqs that can share an rx interrupt */ 308 #define IFLIB_MAX_TX_SHARED_INTR 4 309 310 /* this should really scale with ring size - this is a fairly arbitrary value */ 311 #define TX_BATCH_SIZE 32 312 313 #define IFLIB_RESTART_BUDGET 8 314 315 #define IFC_LEGACY 0x001 316 #define IFC_QFLUSH 0x002 317 #define IFC_MULTISEG 0x004 318 #define IFC_SPARE1 0x008 319 #define IFC_SC_ALLOCATED 0x010 320 #define IFC_INIT_DONE 0x020 321 #define IFC_PREFETCH 0x040 322 #define IFC_DO_RESET 0x080 323 #define IFC_DO_WATCHDOG 0x100 324 #define IFC_SPARE0 0x200 325 #define IFC_SPARE2 0x400 326 #define IFC_IN_DETACH 0x800 327 328 #define IFC_NETMAP_TX_IRQ 0x80000000 329 330 #define CSUM_OFFLOAD (CSUM_IP_TSO | CSUM_IP6_TSO | CSUM_IP | \ 331 CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_SCTP | \ 332 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_SCTP) 333 334 struct iflib_txq { 335 qidx_t ift_in_use; 336 qidx_t ift_cidx; 337 qidx_t ift_cidx_processed; 338 qidx_t ift_pidx; 339 uint8_t ift_gen; 340 uint8_t ift_br_offset; 341 uint16_t ift_npending; 342 uint16_t ift_db_pending; 343 uint16_t ift_rs_pending; 344 /* implicit pad */ 345 uint8_t ift_txd_size[8]; 346 uint64_t ift_processed; 347 uint64_t ift_cleaned; 348 uint64_t ift_cleaned_prev; 349 #if MEMORY_LOGGING 350 uint64_t ift_enqueued; 351 uint64_t ift_dequeued; 352 #endif 353 uint64_t ift_no_tx_dma_setup; 354 uint64_t ift_no_desc_avail; 355 uint64_t ift_mbuf_defrag_failed; 356 uint64_t ift_mbuf_defrag; 357 uint64_t ift_map_failed; 358 uint64_t ift_txd_encap_efbig; 359 uint64_t ift_pullups; 360 uint64_t ift_last_timer_tick; 361 362 struct mtx ift_mtx; 363 struct mtx ift_db_mtx; 364 365 /* constant values */ 366 if_ctx_t ift_ctx; 367 struct ifmp_ring *ift_br; 368 struct grouptask ift_task; 369 qidx_t ift_size; 370 uint16_t ift_id; 371 struct callout ift_timer; 372 #ifdef DEV_NETMAP 373 struct callout ift_netmap_timer; 374 #endif /* DEV_NETMAP */ 375 376 if_txsd_vec_t ift_sds; 377 uint8_t ift_qstatus; 378 uint8_t ift_closed; 379 uint8_t ift_update_freq; 380 struct iflib_filter_info ift_filter_info; 381 bus_dma_tag_t ift_buf_tag; 382 bus_dma_tag_t ift_tso_buf_tag; 383 iflib_dma_info_t ift_ifdi; 384 #define MTX_NAME_LEN 32 385 char ift_mtx_name[MTX_NAME_LEN]; 386 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 387 #ifdef IFLIB_DIAGNOSTICS 388 uint64_t ift_cpu_exec_count[256]; 389 #endif 390 } __aligned(CACHE_LINE_SIZE); 391 392 struct iflib_fl { 393 qidx_t ifl_cidx; 394 qidx_t ifl_pidx; 395 qidx_t ifl_credits; 396 uint8_t ifl_gen; 397 uint8_t ifl_rxd_size; 398 #if MEMORY_LOGGING 399 uint64_t ifl_m_enqueued; 400 uint64_t ifl_m_dequeued; 401 uint64_t ifl_cl_enqueued; 402 uint64_t ifl_cl_dequeued; 403 #endif 404 /* implicit pad */ 405 bitstr_t *ifl_rx_bitmap; 406 qidx_t ifl_fragidx; 407 /* constant */ 408 qidx_t ifl_size; 409 uint16_t ifl_buf_size; 410 uint16_t ifl_cltype; 411 uma_zone_t ifl_zone; 412 iflib_rxsd_array_t ifl_sds; 413 iflib_rxq_t ifl_rxq; 414 uint8_t ifl_id; 415 bus_dma_tag_t ifl_buf_tag; 416 iflib_dma_info_t ifl_ifdi; 417 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 418 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 419 } __aligned(CACHE_LINE_SIZE); 420 421 static inline qidx_t 422 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 423 { 424 qidx_t used; 425 426 if (pidx > cidx) 427 used = pidx - cidx; 428 else if (pidx < cidx) 429 used = size - cidx + pidx; 430 else if (gen == 0 && pidx == cidx) 431 used = 0; 432 else if (gen == 1 && pidx == cidx) 433 used = size; 434 else 435 panic("bad state"); 436 437 return (used); 438 } 439 440 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 441 442 #define IDXDIFF(head, tail, wrap) \ 443 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 444 445 struct iflib_rxq { 446 if_ctx_t ifr_ctx; 447 iflib_fl_t ifr_fl; 448 uint64_t ifr_rx_irq; 449 struct pfil_head *pfil; 450 /* 451 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 452 * the completion queue consumer index. Otherwise it's unused. 453 */ 454 qidx_t ifr_cq_cidx; 455 uint16_t ifr_id; 456 uint8_t ifr_nfl; 457 uint8_t ifr_ntxqirq; 458 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 459 uint8_t ifr_fl_offset; 460 struct lro_ctrl ifr_lc; 461 struct grouptask ifr_task; 462 struct callout ifr_watchdog; 463 struct iflib_filter_info ifr_filter_info; 464 iflib_dma_info_t ifr_ifdi; 465 466 /* dynamically allocate if any drivers need a value substantially larger than this */ 467 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 468 #ifdef IFLIB_DIAGNOSTICS 469 uint64_t ifr_cpu_exec_count[256]; 470 #endif 471 } __aligned(CACHE_LINE_SIZE); 472 473 typedef struct if_rxsd { 474 caddr_t *ifsd_cl; 475 iflib_fl_t ifsd_fl; 476 } *if_rxsd_t; 477 478 /* multiple of word size */ 479 #ifdef __LP64__ 480 #define PKT_INFO_SIZE 6 481 #define RXD_INFO_SIZE 5 482 #define PKT_TYPE uint64_t 483 #else 484 #define PKT_INFO_SIZE 11 485 #define RXD_INFO_SIZE 8 486 #define PKT_TYPE uint32_t 487 #endif 488 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE / 3) * 3) 489 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE / 4) * 4) 490 491 typedef struct if_pkt_info_pad { 492 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 493 } *if_pkt_info_pad_t; 494 typedef struct if_rxd_info_pad { 495 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 496 } *if_rxd_info_pad_t; 497 498 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 499 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 500 501 static inline void 502 pkt_info_zero(if_pkt_info_t pi) 503 { 504 if_pkt_info_pad_t pi_pad; 505 506 pi_pad = (if_pkt_info_pad_t)pi; 507 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 508 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 509 #ifndef __LP64__ 510 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 511 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 512 #endif 513 } 514 515 static inline void 516 rxd_info_zero(if_rxd_info_t ri) 517 { 518 if_rxd_info_pad_t ri_pad; 519 int i; 520 521 ri_pad = (if_rxd_info_pad_t)ri; 522 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 523 ri_pad->rxd_val[i] = 0; 524 ri_pad->rxd_val[i + 1] = 0; 525 ri_pad->rxd_val[i + 2] = 0; 526 ri_pad->rxd_val[i + 3] = 0; 527 } 528 #ifdef __LP64__ 529 ri_pad->rxd_val[RXD_INFO_SIZE - 1] = 0; 530 #endif 531 } 532 533 /* 534 * Only allow a single packet to take up most 1/nth of the tx ring 535 */ 536 #define MAX_SINGLE_PACKET_FRACTION 12 537 #define IF_BAD_DMA ((bus_addr_t)-1) 538 539 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 540 541 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 542 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 543 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 544 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 545 546 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 547 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 548 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 549 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 550 551 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 552 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 553 554 /* Our boot-time initialization hook */ 555 static int iflib_module_event_handler(module_t, int, void *); 556 557 static moduledata_t iflib_moduledata = { 558 "iflib", 559 iflib_module_event_handler, 560 NULL 561 }; 562 563 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 564 MODULE_VERSION(iflib, 1); 565 566 MODULE_DEPEND(iflib, pci, 1, 1, 1); 567 MODULE_DEPEND(iflib, ether, 1, 1, 1); 568 569 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 570 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 571 572 #ifndef IFLIB_DEBUG_COUNTERS 573 #ifdef INVARIANTS 574 #define IFLIB_DEBUG_COUNTERS 1 575 #else 576 #define IFLIB_DEBUG_COUNTERS 0 577 #endif /* !INVARIANTS */ 578 #endif 579 580 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 581 "iflib driver parameters"); 582 583 /* 584 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 585 */ 586 static int iflib_min_tx_latency = 0; 587 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 588 &iflib_min_tx_latency, 0, 589 "minimize transmit latency at the possible expense of throughput"); 590 static int iflib_no_tx_batch = 0; 591 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 592 &iflib_no_tx_batch, 0, 593 "minimize transmit latency at the possible expense of throughput"); 594 static int iflib_timer_default = 1000; 595 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW, 596 &iflib_timer_default, 0, "number of ticks between iflib_timer calls"); 597 598 599 #if IFLIB_DEBUG_COUNTERS 600 601 static int iflib_tx_seen; 602 static int iflib_tx_sent; 603 static int iflib_tx_encap; 604 static int iflib_rx_allocs; 605 static int iflib_fl_refills; 606 static int iflib_fl_refills_large; 607 static int iflib_tx_frees; 608 609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, &iflib_tx_seen, 0, 610 "# TX mbufs seen"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, &iflib_tx_sent, 0, 612 "# TX mbufs sent"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, &iflib_tx_encap, 0, 614 "# TX mbufs encapped"); 615 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, &iflib_tx_frees, 0, 616 "# TX frees"); 617 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, &iflib_rx_allocs, 0, 618 "# RX allocations"); 619 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, &iflib_fl_refills, 0, 620 "# refills"); 621 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 622 &iflib_fl_refills_large, 0, "# large refills"); 623 624 static int iflib_txq_drain_flushing; 625 static int iflib_txq_drain_oactive; 626 static int iflib_txq_drain_notready; 627 628 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 629 &iflib_txq_drain_flushing, 0, "# drain flushes"); 630 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 631 &iflib_txq_drain_oactive, 0, "# drain oactives"); 632 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 633 &iflib_txq_drain_notready, 0, "# drain notready"); 634 635 static int iflib_encap_load_mbuf_fail; 636 static int iflib_encap_pad_mbuf_fail; 637 static int iflib_encap_txq_avail_fail; 638 static int iflib_encap_txd_encap_fail; 639 640 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 641 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 642 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 643 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 644 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 645 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 646 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 647 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 648 649 static int iflib_task_fn_rxs; 650 static int iflib_rx_intr_enables; 651 static int iflib_fast_intrs; 652 static int iflib_rx_unavail; 653 static int iflib_rx_ctx_inactive; 654 static int iflib_rx_if_input; 655 static int iflib_rxd_flush; 656 657 static int iflib_verbose_debug; 658 659 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, &iflib_task_fn_rxs, 0, 660 "# task_fn_rx calls"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 662 &iflib_rx_intr_enables, 0, "# RX intr enables"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, &iflib_fast_intrs, 0, 664 "# fast_intr calls"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, &iflib_rx_unavail, 0, 666 "# times rxeof called with no available data"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 668 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 669 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, &iflib_rx_if_input, 670 0, "# times rxeof called if_input"); 671 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, &iflib_rxd_flush, 0, 672 "# times rxd_flush called"); 673 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 674 &iflib_verbose_debug, 0, "enable verbose debugging"); 675 676 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 677 static void 678 iflib_debug_reset(void) 679 { 680 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 681 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 682 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 683 iflib_txq_drain_notready = 684 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 685 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 686 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 687 iflib_rx_unavail = 688 iflib_rx_ctx_inactive = iflib_rx_if_input = 689 iflib_rxd_flush = 0; 690 } 691 692 #else 693 #define DBG_COUNTER_INC(name) 694 static void iflib_debug_reset(void) {} 695 #endif 696 697 #define IFLIB_DEBUG 0 698 699 static void iflib_tx_structures_free(if_ctx_t ctx); 700 static void iflib_rx_structures_free(if_ctx_t ctx); 701 static int iflib_queues_alloc(if_ctx_t ctx); 702 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 703 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 704 static int iflib_qset_structures_setup(if_ctx_t ctx); 705 static int iflib_msix_init(if_ctx_t ctx); 706 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 707 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 708 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 709 #ifdef ALTQ 710 static void iflib_altq_if_start(if_t ifp); 711 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 712 #endif 713 static int iflib_register(if_ctx_t); 714 static void iflib_deregister(if_ctx_t); 715 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 716 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 717 static void iflib_init_locked(if_ctx_t ctx); 718 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 719 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 720 static void iflib_ifmp_purge(iflib_txq_t txq); 721 static void _iflib_pre_assert(if_softc_ctx_t scctx); 722 static void iflib_stop(if_ctx_t ctx); 723 static void iflib_if_init_locked(if_ctx_t ctx); 724 static void iflib_free_intr_mem(if_ctx_t ctx); 725 #ifndef __NO_STRICT_ALIGNMENT 726 static struct mbuf *iflib_fixup_rx(struct mbuf *m); 727 #endif 728 729 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 730 SLIST_HEAD_INITIALIZER(cpu_offsets); 731 struct cpu_offset { 732 SLIST_ENTRY(cpu_offset) entries; 733 cpuset_t set; 734 unsigned int refcount; 735 uint16_t next_cpuid; 736 }; 737 static struct mtx cpu_offset_mtx; 738 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 739 MTX_DEF); 740 741 DEBUGNET_DEFINE(iflib); 742 743 static int 744 iflib_num_rx_descs(if_ctx_t ctx) 745 { 746 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 747 if_shared_ctx_t sctx = ctx->ifc_sctx; 748 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 749 750 return (scctx->isc_nrxd[first_rxq]); 751 } 752 753 static int 754 iflib_num_tx_descs(if_ctx_t ctx) 755 { 756 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 757 if_shared_ctx_t sctx = ctx->ifc_sctx; 758 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 759 760 return (scctx->isc_ntxd[first_txq]); 761 } 762 763 #ifdef DEV_NETMAP 764 #include <sys/selinfo.h> 765 #include <net/netmap.h> 766 #include <dev/netmap/netmap_kern.h> 767 768 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 769 770 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 771 static void iflib_netmap_timer(void *arg); 772 773 /* 774 * device-specific sysctl variables: 775 * 776 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 777 * During regular operations the CRC is stripped, but on some 778 * hardware reception of frames not multiple of 64 is slower, 779 * so using crcstrip=0 helps in benchmarks. 780 * 781 * iflib_rx_miss, iflib_rx_miss_bufs: 782 * count packets that might be missed due to lost interrupts. 783 */ 784 SYSCTL_DECL(_dev_netmap); 785 /* 786 * The xl driver by default strips CRCs and we do not override it. 787 */ 788 789 int iflib_crcstrip = 1; 790 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 791 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 792 793 int iflib_rx_miss, iflib_rx_miss_bufs; 794 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 795 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 796 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 797 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 798 799 /* 800 * Register/unregister. We are already under netmap lock. 801 * Only called on the first register or the last unregister. 802 */ 803 static int 804 iflib_netmap_register(struct netmap_adapter *na, int onoff) 805 { 806 if_t ifp = na->ifp; 807 if_ctx_t ctx = if_getsoftc(ifp); 808 int status; 809 810 CTX_LOCK(ctx); 811 if (!CTX_IS_VF(ctx)) 812 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 813 814 iflib_stop(ctx); 815 816 /* 817 * Enable (or disable) netmap flags, and intercept (or restore) 818 * ifp->if_transmit. This is done once the device has been stopped 819 * to prevent race conditions. Also, this must be done after 820 * calling netmap_disable_all_rings() and before calling 821 * netmap_enable_all_rings(), so that these two functions see the 822 * updated state of the NAF_NETMAP_ON bit. 823 */ 824 if (onoff) { 825 nm_set_native_flags(na); 826 } else { 827 nm_clear_native_flags(na); 828 } 829 830 iflib_init_locked(ctx); 831 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 832 status = if_getdrvflags(ifp) & IFF_DRV_RUNNING ? 0 : 1; 833 if (status) 834 nm_clear_native_flags(na); 835 CTX_UNLOCK(ctx); 836 return (status); 837 } 838 839 static int 840 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info) 841 { 842 if_t ifp = na->ifp; 843 if_ctx_t ctx = if_getsoftc(ifp); 844 iflib_rxq_t rxq = &ctx->ifc_rxqs[0]; 845 iflib_fl_t fl = &rxq->ifr_fl[0]; 846 847 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 848 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 849 info->num_tx_descs = iflib_num_tx_descs(ctx); 850 info->num_rx_descs = iflib_num_rx_descs(ctx); 851 info->rx_buf_maxsize = fl->ifl_buf_size; 852 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u", 853 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs, 854 info->num_rx_descs, info->rx_buf_maxsize); 855 856 return (0); 857 } 858 859 static int 860 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 861 { 862 struct netmap_adapter *na = kring->na; 863 u_int const lim = kring->nkr_num_slots - 1; 864 struct netmap_ring *ring = kring->ring; 865 bus_dmamap_t *map; 866 struct if_rxd_update iru; 867 if_ctx_t ctx = rxq->ifr_ctx; 868 iflib_fl_t fl = &rxq->ifr_fl[0]; 869 u_int nic_i_first, nic_i; 870 u_int nm_i; 871 int i, n; 872 #if IFLIB_DEBUG_COUNTERS 873 int rf_count = 0; 874 #endif 875 876 /* 877 * This function is used both at initialization and in rxsync. 878 * At initialization we need to prepare (with isc_rxd_refill()) 879 * all the netmap buffers currently owned by the kernel, in 880 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync 881 * (except for kring->nkr_hwofs). These may be less than 882 * kring->nkr_num_slots if netmap_reset() was called while 883 * an application using the kring that still owned some 884 * buffers. 885 * At rxsync time, both indexes point to the next buffer to be 886 * refilled. 887 * In any case we publish (with isc_rxd_flush()) up to 888 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 889 * pointer to overrun the head/cons pointer, although this is 890 * not necessary for some NICs (e.g. vmx). 891 */ 892 if (__predict_false(init)) { 893 n = kring->nkr_num_slots - nm_kr_rxspace(kring); 894 } else { 895 n = kring->rhead - kring->nr_hwcur; 896 if (n == 0) 897 return (0); /* Nothing to do. */ 898 if (n < 0) 899 n += kring->nkr_num_slots; 900 } 901 902 iru_init(&iru, rxq, 0 /* flid */); 903 map = fl->ifl_sds.ifsd_map; 904 nic_i = fl->ifl_pidx; 905 nm_i = netmap_idx_n2k(kring, nic_i); 906 if (__predict_false(init)) { 907 /* 908 * On init/reset, nic_i must be 0, and we must 909 * start to refill from hwtail (see netmap_reset()). 910 */ 911 MPASS(nic_i == 0); 912 MPASS(nm_i == kring->nr_hwtail); 913 } else 914 MPASS(nm_i == kring->nr_hwcur); 915 DBG_COUNTER_INC(fl_refills); 916 while (n > 0) { 917 #if IFLIB_DEBUG_COUNTERS 918 if (++rf_count == 9) 919 DBG_COUNTER_INC(fl_refills_large); 920 #endif 921 nic_i_first = nic_i; 922 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 923 struct netmap_slot *slot = &ring->slot[nm_i]; 924 uint64_t paddr; 925 void *addr = PNMB(na, slot, &paddr); 926 927 MPASS(i < IFLIB_MAX_RX_REFRESH); 928 929 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 930 return (netmap_ring_reinit(kring)); 931 932 fl->ifl_bus_addrs[i] = paddr + 933 nm_get_offset(kring, slot); 934 fl->ifl_rxd_idxs[i] = nic_i; 935 936 if (__predict_false(init)) { 937 netmap_load_map(na, fl->ifl_buf_tag, 938 map[nic_i], addr); 939 } else if (slot->flags & NS_BUF_CHANGED) { 940 /* buffer has changed, reload map */ 941 netmap_reload_map(na, fl->ifl_buf_tag, 942 map[nic_i], addr); 943 } 944 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 945 BUS_DMASYNC_PREREAD); 946 slot->flags &= ~NS_BUF_CHANGED; 947 948 nm_i = nm_next(nm_i, lim); 949 nic_i = nm_next(nic_i, lim); 950 } 951 952 iru.iru_pidx = nic_i_first; 953 iru.iru_count = i; 954 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 955 } 956 fl->ifl_pidx = nic_i; 957 /* 958 * At the end of the loop we must have refilled everything 959 * we could possibly refill. 960 */ 961 MPASS(nm_i == kring->rhead); 962 kring->nr_hwcur = nm_i; 963 964 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 965 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 966 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 967 nm_prev(nic_i, lim)); 968 DBG_COUNTER_INC(rxd_flush); 969 970 return (0); 971 } 972 973 #define NETMAP_TX_TIMER_US 90 974 975 /* 976 * Reconcile kernel and user view of the transmit ring. 977 * 978 * All information is in the kring. 979 * Userspace wants to send packets up to the one before kring->rhead, 980 * kernel knows kring->nr_hwcur is the first unsent packet. 981 * 982 * Here we push packets out (as many as possible), and possibly 983 * reclaim buffers from previously completed transmission. 984 * 985 * The caller (netmap) guarantees that there is only one instance 986 * running at any time. Any interference with other driver 987 * methods should be handled by the individual drivers. 988 */ 989 static int 990 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 991 { 992 struct netmap_adapter *na = kring->na; 993 if_t ifp = na->ifp; 994 struct netmap_ring *ring = kring->ring; 995 u_int nm_i; /* index into the netmap kring */ 996 u_int nic_i; /* index into the NIC ring */ 997 u_int const lim = kring->nkr_num_slots - 1; 998 u_int const head = kring->rhead; 999 struct if_pkt_info pi; 1000 int tx_pkts = 0, tx_bytes = 0; 1001 1002 /* 1003 * interrupts on every tx packet are expensive so request 1004 * them every half ring, or where NS_REPORT is set 1005 */ 1006 u_int report_frequency = kring->nkr_num_slots >> 1; 1007 /* device-specific */ 1008 if_ctx_t ctx = if_getsoftc(ifp); 1009 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 1010 1011 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1012 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1013 1014 /* 1015 * First part: process new packets to send. 1016 * nm_i is the current index in the netmap kring, 1017 * nic_i is the corresponding index in the NIC ring. 1018 * 1019 * If we have packets to send (nm_i != head) 1020 * iterate over the netmap ring, fetch length and update 1021 * the corresponding slot in the NIC ring. Some drivers also 1022 * need to update the buffer's physical address in the NIC slot 1023 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 1024 * 1025 * The netmap_reload_map() calls is especially expensive, 1026 * even when (as in this case) the tag is 0, so do only 1027 * when the buffer has actually changed. 1028 * 1029 * If possible do not set the report/intr bit on all slots, 1030 * but only a few times per ring or when NS_REPORT is set. 1031 * 1032 * Finally, on 10G and faster drivers, it might be useful 1033 * to prefetch the next slot and txr entry. 1034 */ 1035 1036 nm_i = kring->nr_hwcur; 1037 if (nm_i != head) { /* we have new packets to send */ 1038 uint32_t pkt_len = 0, seg_idx = 0; 1039 int nic_i_start = -1, flags = 0; 1040 pkt_info_zero(&pi); 1041 pi.ipi_segs = txq->ift_segs; 1042 pi.ipi_qsidx = kring->ring_id; 1043 nic_i = netmap_idx_k2n(kring, nm_i); 1044 1045 __builtin_prefetch(&ring->slot[nm_i]); 1046 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 1047 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 1048 1049 while (nm_i != head) { 1050 struct netmap_slot *slot = &ring->slot[nm_i]; 1051 uint64_t offset = nm_get_offset(kring, slot); 1052 u_int len = slot->len; 1053 uint64_t paddr; 1054 void *addr = PNMB(na, slot, &paddr); 1055 1056 flags |= (slot->flags & NS_REPORT || 1057 nic_i == 0 || nic_i == report_frequency) ? 1058 IPI_TX_INTR : 0; 1059 1060 /* 1061 * If this is the first packet fragment, save the 1062 * index of the first NIC slot for later. 1063 */ 1064 if (nic_i_start < 0) 1065 nic_i_start = nic_i; 1066 1067 pi.ipi_segs[seg_idx].ds_addr = paddr + offset; 1068 pi.ipi_segs[seg_idx].ds_len = len; 1069 if (len) { 1070 pkt_len += len; 1071 seg_idx++; 1072 } 1073 1074 if (!(slot->flags & NS_MOREFRAG)) { 1075 pi.ipi_len = pkt_len; 1076 pi.ipi_nsegs = seg_idx; 1077 pi.ipi_pidx = nic_i_start; 1078 pi.ipi_ndescs = 0; 1079 pi.ipi_flags = flags; 1080 1081 /* Prepare the NIC TX ring. */ 1082 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1083 DBG_COUNTER_INC(tx_encap); 1084 1085 /* Update transmit counters */ 1086 tx_bytes += pi.ipi_len; 1087 tx_pkts++; 1088 1089 /* Reinit per-packet info for the next one. */ 1090 flags = seg_idx = pkt_len = 0; 1091 nic_i_start = -1; 1092 } 1093 1094 /* prefetch for next round */ 1095 __builtin_prefetch(&ring->slot[nm_i + 1]); 1096 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1097 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1098 1099 NM_CHECK_ADDR_LEN_OFF(na, len, offset); 1100 1101 if (slot->flags & NS_BUF_CHANGED) { 1102 /* buffer has changed, reload map */ 1103 netmap_reload_map(na, txq->ift_buf_tag, 1104 txq->ift_sds.ifsd_map[nic_i], addr); 1105 } 1106 /* make sure changes to the buffer are synced */ 1107 bus_dmamap_sync(txq->ift_buf_tag, 1108 txq->ift_sds.ifsd_map[nic_i], 1109 BUS_DMASYNC_PREWRITE); 1110 1111 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG); 1112 nm_i = nm_next(nm_i, lim); 1113 nic_i = nm_next(nic_i, lim); 1114 } 1115 kring->nr_hwcur = nm_i; 1116 1117 /* synchronize the NIC ring */ 1118 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1119 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1120 1121 /* (re)start the tx unit up to slot nic_i (excluded) */ 1122 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1123 } 1124 1125 /* 1126 * Second part: reclaim buffers for completed transmissions. 1127 * 1128 * If there are unclaimed buffers, attempt to reclaim them. 1129 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1130 * trigger a per-tx-queue timer to try again later. 1131 */ 1132 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1133 if (iflib_tx_credits_update(ctx, txq)) { 1134 /* some tx completed, increment avail */ 1135 nic_i = txq->ift_cidx_processed; 1136 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1137 } 1138 } 1139 1140 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1141 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1142 callout_reset_sbt_on(&txq->ift_netmap_timer, 1143 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1144 iflib_netmap_timer, txq, 1145 txq->ift_netmap_timer.c_cpu, 0); 1146 } 1147 1148 if_inc_counter(ifp, IFCOUNTER_OBYTES, tx_bytes); 1149 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tx_pkts); 1150 1151 return (0); 1152 } 1153 1154 /* 1155 * Reconcile kernel and user view of the receive ring. 1156 * Same as for the txsync, this routine must be efficient. 1157 * The caller guarantees a single invocations, but races against 1158 * the rest of the driver should be handled here. 1159 * 1160 * On call, kring->rhead is the first packet that userspace wants 1161 * to keep, and kring->rcur is the wakeup point. 1162 * The kernel has previously reported packets up to kring->rtail. 1163 * 1164 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1165 * of whether or not we received an interrupt. 1166 */ 1167 static int 1168 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1169 { 1170 struct netmap_adapter *na = kring->na; 1171 struct netmap_ring *ring = kring->ring; 1172 if_t ifp = na->ifp; 1173 uint32_t nm_i; /* index into the netmap ring */ 1174 uint32_t nic_i; /* index into the NIC ring */ 1175 u_int n; 1176 u_int const lim = kring->nkr_num_slots - 1; 1177 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1178 int i = 0, rx_bytes = 0, rx_pkts = 0; 1179 1180 if_ctx_t ctx = if_getsoftc(ifp); 1181 if_shared_ctx_t sctx = ctx->ifc_sctx; 1182 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1183 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1184 iflib_fl_t fl = &rxq->ifr_fl[0]; 1185 struct if_rxd_info ri; 1186 qidx_t *cidxp; 1187 1188 /* 1189 * netmap only uses free list 0, to avoid out of order consumption 1190 * of receive buffers 1191 */ 1192 1193 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1194 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1195 1196 /* 1197 * First part: import newly received packets. 1198 * 1199 * nm_i is the index of the next free slot in the netmap ring, 1200 * nic_i is the index of the next received packet in the NIC ring 1201 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1202 * differ in case if_init() has been called while 1203 * in netmap mode. For the receive ring we have 1204 * 1205 * nic_i = fl->ifl_cidx; 1206 * nm_i = kring->nr_hwtail (previous) 1207 * and 1208 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1209 * 1210 * fl->ifl_cidx is set to 0 on a ring reinit 1211 */ 1212 if (netmap_no_pendintr || force_update) { 1213 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1214 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1215 int crclen = iflib_crcstrip ? 0 : 4; 1216 int error, avail; 1217 1218 /* 1219 * For the free list consumer index, we use the same 1220 * logic as in iflib_rxeof(). 1221 */ 1222 if (have_rxcq) 1223 cidxp = &rxq->ifr_cq_cidx; 1224 else 1225 cidxp = &fl->ifl_cidx; 1226 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1227 rxq->ifr_id, *cidxp, USHRT_MAX); 1228 1229 nic_i = fl->ifl_cidx; 1230 nm_i = netmap_idx_n2k(kring, nic_i); 1231 MPASS(nm_i == kring->nr_hwtail); 1232 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1233 rxd_info_zero(&ri); 1234 ri.iri_frags = rxq->ifr_frags; 1235 ri.iri_qsidx = kring->ring_id; 1236 ri.iri_ifp = ctx->ifc_ifp; 1237 ri.iri_cidx = *cidxp; 1238 1239 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1240 for (i = 0; i < ri.iri_nfrags; i++) { 1241 if (error) { 1242 ring->slot[nm_i].len = 0; 1243 ring->slot[nm_i].flags = 0; 1244 } else { 1245 ring->slot[nm_i].len = ri.iri_frags[i].irf_len; 1246 if (i == (ri.iri_nfrags - 1)) { 1247 ring->slot[nm_i].len -= crclen; 1248 ring->slot[nm_i].flags = 0; 1249 1250 /* Update receive counters */ 1251 rx_bytes += ri.iri_len; 1252 rx_pkts++; 1253 } else 1254 ring->slot[nm_i].flags = NS_MOREFRAG; 1255 } 1256 1257 bus_dmamap_sync(fl->ifl_buf_tag, 1258 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1259 nm_i = nm_next(nm_i, lim); 1260 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1261 } 1262 1263 if (have_rxcq) { 1264 *cidxp = ri.iri_cidx; 1265 while (*cidxp >= scctx->isc_nrxd[0]) 1266 *cidxp -= scctx->isc_nrxd[0]; 1267 } 1268 1269 } 1270 if (n) { /* update the state variables */ 1271 if (netmap_no_pendintr && !force_update) { 1272 /* diagnostics */ 1273 iflib_rx_miss++; 1274 iflib_rx_miss_bufs += n; 1275 } 1276 kring->nr_hwtail = nm_i; 1277 } 1278 kring->nr_kflags &= ~NKR_PENDINTR; 1279 } 1280 /* 1281 * Second part: skip past packets that userspace has released. 1282 * (kring->nr_hwcur to head excluded), 1283 * and make the buffers available for reception. 1284 * As usual nm_i is the index in the netmap ring, 1285 * nic_i is the index in the NIC ring, and 1286 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1287 */ 1288 netmap_fl_refill(rxq, kring, false); 1289 1290 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 1291 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 1292 1293 return (0); 1294 } 1295 1296 static void 1297 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1298 { 1299 if_ctx_t ctx = if_getsoftc(na->ifp); 1300 1301 CTX_LOCK(ctx); 1302 if (onoff) { 1303 IFDI_INTR_ENABLE(ctx); 1304 } else { 1305 IFDI_INTR_DISABLE(ctx); 1306 } 1307 CTX_UNLOCK(ctx); 1308 } 1309 1310 static int 1311 iflib_netmap_attach(if_ctx_t ctx) 1312 { 1313 struct netmap_adapter na; 1314 1315 bzero(&na, sizeof(na)); 1316 1317 na.ifp = ctx->ifc_ifp; 1318 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS; 1319 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1320 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1321 1322 na.num_tx_desc = iflib_num_tx_descs(ctx); 1323 na.num_rx_desc = iflib_num_rx_descs(ctx); 1324 na.nm_txsync = iflib_netmap_txsync; 1325 na.nm_rxsync = iflib_netmap_rxsync; 1326 na.nm_register = iflib_netmap_register; 1327 na.nm_intr = iflib_netmap_intr; 1328 na.nm_config = iflib_netmap_config; 1329 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1330 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1331 return (netmap_attach(&na)); 1332 } 1333 1334 static int 1335 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1336 { 1337 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1338 struct netmap_slot *slot; 1339 1340 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1341 if (slot == NULL) 1342 return (0); 1343 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1344 /* 1345 * In netmap mode, set the map for the packet buffer. 1346 * NOTE: Some drivers (not this one) also need to set 1347 * the physical buffer address in the NIC ring. 1348 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1349 * netmap slot index, si 1350 */ 1351 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1352 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1353 NMB(na, slot + si)); 1354 } 1355 return (1); 1356 } 1357 1358 static int 1359 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1360 { 1361 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1362 struct netmap_kring *kring; 1363 struct netmap_slot *slot; 1364 1365 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1366 if (slot == NULL) 1367 return (0); 1368 kring = na->rx_rings[rxq->ifr_id]; 1369 netmap_fl_refill(rxq, kring, true); 1370 return (1); 1371 } 1372 1373 static void 1374 iflib_netmap_timer(void *arg) 1375 { 1376 iflib_txq_t txq = arg; 1377 if_ctx_t ctx = txq->ift_ctx; 1378 1379 /* 1380 * Wake up the netmap application, to give it a chance to 1381 * call txsync and reclaim more completed TX buffers. 1382 */ 1383 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1384 } 1385 1386 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1387 1388 #else 1389 #define iflib_netmap_txq_init(ctx, txq) (0) 1390 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1391 #define iflib_netmap_detach(ifp) 1392 #define netmap_enable_all_rings(ifp) 1393 #define netmap_disable_all_rings(ifp) 1394 1395 #define iflib_netmap_attach(ctx) (0) 1396 #define netmap_rx_irq(ifp, qid, budget) (0) 1397 #endif 1398 1399 #if defined(__i386__) || defined(__amd64__) 1400 static __inline void 1401 prefetch(void *x) 1402 { 1403 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1404 } 1405 1406 static __inline void 1407 prefetch2cachelines(void *x) 1408 { 1409 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1410 #if (CACHE_LINE_SIZE < 128) 1411 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x) + CACHE_LINE_SIZE / (sizeof(unsigned long))))); 1412 #endif 1413 } 1414 #else 1415 static __inline void 1416 prefetch(void *x) 1417 { 1418 } 1419 1420 static __inline void 1421 prefetch2cachelines(void *x) 1422 { 1423 } 1424 #endif 1425 1426 static void 1427 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1428 { 1429 iflib_fl_t fl; 1430 1431 fl = &rxq->ifr_fl[flid]; 1432 iru->iru_paddrs = fl->ifl_bus_addrs; 1433 iru->iru_idxs = fl->ifl_rxd_idxs; 1434 iru->iru_qsidx = rxq->ifr_id; 1435 iru->iru_buf_size = fl->ifl_buf_size; 1436 iru->iru_flidx = fl->ifl_id; 1437 } 1438 1439 static void 1440 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1441 { 1442 if (err) 1443 return; 1444 *(bus_addr_t *) arg = segs[0].ds_addr; 1445 } 1446 1447 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \ 1448 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \ 1449 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL) 1450 1451 int 1452 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1453 { 1454 int err; 1455 device_t dev = ctx->ifc_dev; 1456 bus_addr_t lowaddr; 1457 1458 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width); 1459 1460 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1461 align, 0, /* alignment, bounds */ 1462 lowaddr, /* lowaddr */ 1463 BUS_SPACE_MAXADDR, /* highaddr */ 1464 NULL, NULL, /* filter, filterarg */ 1465 size, /* maxsize */ 1466 1, /* nsegments */ 1467 size, /* maxsegsize */ 1468 BUS_DMA_ALLOCNOW, /* flags */ 1469 NULL, /* lockfunc */ 1470 NULL, /* lockarg */ 1471 &dma->idi_tag); 1472 if (err) { 1473 device_printf(dev, 1474 "%s: bus_dma_tag_create failed: %d (size=%d, align=%d)\n", 1475 __func__, err, size, align); 1476 goto fail_0; 1477 } 1478 1479 err = bus_dmamem_alloc(dma->idi_tag, (void **)&dma->idi_vaddr, 1480 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1481 if (err) { 1482 device_printf(dev, 1483 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1484 __func__, (uintmax_t)size, err); 1485 goto fail_1; 1486 } 1487 1488 dma->idi_paddr = IF_BAD_DMA; 1489 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1490 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1491 if (err || dma->idi_paddr == IF_BAD_DMA) { 1492 device_printf(dev, 1493 "%s: bus_dmamap_load failed: %d\n", 1494 __func__, err); 1495 goto fail_2; 1496 } 1497 1498 dma->idi_size = size; 1499 return (0); 1500 1501 fail_2: 1502 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1503 fail_1: 1504 bus_dma_tag_destroy(dma->idi_tag); 1505 fail_0: 1506 dma->idi_tag = NULL; 1507 1508 return (err); 1509 } 1510 1511 int 1512 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1513 { 1514 if_shared_ctx_t sctx = ctx->ifc_sctx; 1515 1516 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1517 1518 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1519 } 1520 1521 int 1522 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1523 { 1524 int i, err; 1525 iflib_dma_info_t *dmaiter; 1526 1527 dmaiter = dmalist; 1528 for (i = 0; i < count; i++, dmaiter++) { 1529 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1530 break; 1531 } 1532 if (err) 1533 iflib_dma_free_multi(dmalist, i); 1534 return (err); 1535 } 1536 1537 void 1538 iflib_dma_free(iflib_dma_info_t dma) 1539 { 1540 if (dma->idi_tag == NULL) 1541 return; 1542 if (dma->idi_paddr != IF_BAD_DMA) { 1543 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1544 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1545 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1546 dma->idi_paddr = IF_BAD_DMA; 1547 } 1548 if (dma->idi_vaddr != NULL) { 1549 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1550 dma->idi_vaddr = NULL; 1551 } 1552 bus_dma_tag_destroy(dma->idi_tag); 1553 dma->idi_tag = NULL; 1554 } 1555 1556 void 1557 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1558 { 1559 int i; 1560 iflib_dma_info_t *dmaiter = dmalist; 1561 1562 for (i = 0; i < count; i++, dmaiter++) 1563 iflib_dma_free(*dmaiter); 1564 } 1565 1566 static int 1567 iflib_fast_intr(void *arg) 1568 { 1569 iflib_filter_info_t info = arg; 1570 struct grouptask *gtask = info->ifi_task; 1571 int result; 1572 1573 DBG_COUNTER_INC(fast_intrs); 1574 if (info->ifi_filter != NULL) { 1575 result = info->ifi_filter(info->ifi_filter_arg); 1576 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1577 return (result); 1578 } 1579 1580 GROUPTASK_ENQUEUE(gtask); 1581 return (FILTER_HANDLED); 1582 } 1583 1584 static int 1585 iflib_fast_intr_rxtx(void *arg) 1586 { 1587 iflib_filter_info_t info = arg; 1588 struct grouptask *gtask = info->ifi_task; 1589 if_ctx_t ctx; 1590 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1591 iflib_txq_t txq; 1592 void *sc; 1593 int i, cidx, result; 1594 qidx_t txqid; 1595 bool intr_enable, intr_legacy; 1596 1597 DBG_COUNTER_INC(fast_intrs); 1598 if (info->ifi_filter != NULL) { 1599 result = info->ifi_filter(info->ifi_filter_arg); 1600 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1601 return (result); 1602 } 1603 1604 ctx = rxq->ifr_ctx; 1605 sc = ctx->ifc_softc; 1606 intr_enable = false; 1607 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1608 MPASS(rxq->ifr_ntxqirq); 1609 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1610 txqid = rxq->ifr_txqid[i]; 1611 txq = &ctx->ifc_txqs[txqid]; 1612 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1613 BUS_DMASYNC_POSTREAD); 1614 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1615 if (intr_legacy) 1616 intr_enable = true; 1617 else 1618 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1619 continue; 1620 } 1621 GROUPTASK_ENQUEUE(&txq->ift_task); 1622 } 1623 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1624 cidx = rxq->ifr_cq_cidx; 1625 else 1626 cidx = rxq->ifr_fl[0].ifl_cidx; 1627 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1628 GROUPTASK_ENQUEUE(gtask); 1629 else { 1630 if (intr_legacy) 1631 intr_enable = true; 1632 else 1633 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1634 DBG_COUNTER_INC(rx_intr_enables); 1635 } 1636 if (intr_enable) 1637 IFDI_INTR_ENABLE(ctx); 1638 return (FILTER_HANDLED); 1639 } 1640 1641 static int 1642 iflib_fast_intr_ctx(void *arg) 1643 { 1644 iflib_filter_info_t info = arg; 1645 if_ctx_t ctx = info->ifi_ctx; 1646 int result; 1647 1648 DBG_COUNTER_INC(fast_intrs); 1649 if (info->ifi_filter != NULL) { 1650 result = info->ifi_filter(info->ifi_filter_arg); 1651 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1652 return (result); 1653 } 1654 1655 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_admin_task); 1656 return (FILTER_HANDLED); 1657 } 1658 1659 static int 1660 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1661 driver_filter_t filter, driver_intr_t handler, void *arg, 1662 const char *name) 1663 { 1664 struct resource *res; 1665 void *tag = NULL; 1666 device_t dev = ctx->ifc_dev; 1667 int flags, i, rc; 1668 1669 flags = RF_ACTIVE; 1670 if (ctx->ifc_flags & IFC_LEGACY) 1671 flags |= RF_SHAREABLE; 1672 MPASS(rid < 512); 1673 i = rid; 1674 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1675 if (res == NULL) { 1676 device_printf(dev, 1677 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1678 return (ENOMEM); 1679 } 1680 irq->ii_res = res; 1681 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1682 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1683 filter, handler, arg, &tag); 1684 if (rc != 0) { 1685 device_printf(dev, 1686 "failed to setup interrupt for rid %d, name %s: %d\n", 1687 rid, name ? name : "unknown", rc); 1688 return (rc); 1689 } else if (name) 1690 bus_describe_intr(dev, res, tag, "%s", name); 1691 1692 irq->ii_tag = tag; 1693 return (0); 1694 } 1695 1696 /********************************************************************* 1697 * 1698 * Allocate DMA resources for TX buffers as well as memory for the TX 1699 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1700 * iflib_sw_tx_desc_array structure, storing all the information that 1701 * is needed to transmit a packet on the wire. This is called only 1702 * once at attach, setup is done every reset. 1703 * 1704 **********************************************************************/ 1705 static int 1706 iflib_txsd_alloc(iflib_txq_t txq) 1707 { 1708 if_ctx_t ctx = txq->ift_ctx; 1709 if_shared_ctx_t sctx = ctx->ifc_sctx; 1710 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1711 device_t dev = ctx->ifc_dev; 1712 bus_size_t tsomaxsize; 1713 bus_addr_t lowaddr; 1714 int err, nsegments, ntsosegments; 1715 bool tso; 1716 1717 nsegments = scctx->isc_tx_nsegments; 1718 ntsosegments = scctx->isc_tx_tso_segments_max; 1719 tsomaxsize = scctx->isc_tx_tso_size_max; 1720 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1721 tsomaxsize += sizeof(struct ether_vlan_header); 1722 MPASS(scctx->isc_ntxd[0] > 0); 1723 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1724 MPASS(nsegments > 0); 1725 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1726 MPASS(ntsosegments > 0); 1727 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1728 } 1729 1730 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1731 1732 /* 1733 * Set up DMA tags for TX buffers. 1734 */ 1735 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1736 1, 0, /* alignment, bounds */ 1737 lowaddr, /* lowaddr */ 1738 BUS_SPACE_MAXADDR, /* highaddr */ 1739 NULL, NULL, /* filter, filterarg */ 1740 sctx->isc_tx_maxsize, /* maxsize */ 1741 nsegments, /* nsegments */ 1742 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1743 0, /* flags */ 1744 NULL, /* lockfunc */ 1745 NULL, /* lockfuncarg */ 1746 &txq->ift_buf_tag))) { 1747 device_printf(dev, "Unable to allocate TX DMA tag: %d\n", err); 1748 device_printf(dev, "maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1749 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1750 goto fail; 1751 } 1752 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1753 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1754 1, 0, /* alignment, bounds */ 1755 lowaddr, /* lowaddr */ 1756 BUS_SPACE_MAXADDR, /* highaddr */ 1757 NULL, NULL, /* filter, filterarg */ 1758 tsomaxsize, /* maxsize */ 1759 ntsosegments, /* nsegments */ 1760 sctx->isc_tso_maxsegsize, /* maxsegsize */ 1761 0, /* flags */ 1762 NULL, /* lockfunc */ 1763 NULL, /* lockfuncarg */ 1764 &txq->ift_tso_buf_tag))) { 1765 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1766 err); 1767 goto fail; 1768 } 1769 1770 /* Allocate memory for the TX mbuf map. */ 1771 if (!(txq->ift_sds.ifsd_m = 1772 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1773 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1774 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1775 err = ENOMEM; 1776 goto fail; 1777 } 1778 1779 /* 1780 * Create the DMA maps for TX buffers. 1781 */ 1782 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1783 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1784 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1785 device_printf(dev, 1786 "Unable to allocate TX buffer DMA map memory\n"); 1787 err = ENOMEM; 1788 goto fail; 1789 } 1790 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1791 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1792 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1793 device_printf(dev, 1794 "Unable to allocate TSO TX buffer map memory\n"); 1795 err = ENOMEM; 1796 goto fail; 1797 } 1798 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1799 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1800 &txq->ift_sds.ifsd_map[i]); 1801 if (err != 0) { 1802 device_printf(dev, "Unable to create TX DMA map\n"); 1803 goto fail; 1804 } 1805 if (!tso) 1806 continue; 1807 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1808 &txq->ift_sds.ifsd_tso_map[i]); 1809 if (err != 0) { 1810 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1811 goto fail; 1812 } 1813 } 1814 return (0); 1815 fail: 1816 /* We free all, it handles case where we are in the middle */ 1817 iflib_tx_structures_free(ctx); 1818 return (err); 1819 } 1820 1821 static void 1822 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1823 { 1824 bus_dmamap_t map; 1825 1826 if (txq->ift_sds.ifsd_map != NULL) { 1827 map = txq->ift_sds.ifsd_map[i]; 1828 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1829 bus_dmamap_unload(txq->ift_buf_tag, map); 1830 bus_dmamap_destroy(txq->ift_buf_tag, map); 1831 txq->ift_sds.ifsd_map[i] = NULL; 1832 } 1833 1834 if (txq->ift_sds.ifsd_tso_map != NULL) { 1835 map = txq->ift_sds.ifsd_tso_map[i]; 1836 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1837 BUS_DMASYNC_POSTWRITE); 1838 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1839 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1840 txq->ift_sds.ifsd_tso_map[i] = NULL; 1841 } 1842 } 1843 1844 static void 1845 iflib_txq_destroy(iflib_txq_t txq) 1846 { 1847 if_ctx_t ctx = txq->ift_ctx; 1848 1849 for (int i = 0; i < txq->ift_size; i++) 1850 iflib_txsd_destroy(ctx, txq, i); 1851 1852 if (txq->ift_br != NULL) { 1853 ifmp_ring_free(txq->ift_br); 1854 txq->ift_br = NULL; 1855 } 1856 1857 mtx_destroy(&txq->ift_mtx); 1858 1859 if (txq->ift_sds.ifsd_map != NULL) { 1860 free(txq->ift_sds.ifsd_map, M_IFLIB); 1861 txq->ift_sds.ifsd_map = NULL; 1862 } 1863 if (txq->ift_sds.ifsd_tso_map != NULL) { 1864 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1865 txq->ift_sds.ifsd_tso_map = NULL; 1866 } 1867 if (txq->ift_sds.ifsd_m != NULL) { 1868 free(txq->ift_sds.ifsd_m, M_IFLIB); 1869 txq->ift_sds.ifsd_m = NULL; 1870 } 1871 if (txq->ift_buf_tag != NULL) { 1872 bus_dma_tag_destroy(txq->ift_buf_tag); 1873 txq->ift_buf_tag = NULL; 1874 } 1875 if (txq->ift_tso_buf_tag != NULL) { 1876 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1877 txq->ift_tso_buf_tag = NULL; 1878 } 1879 if (txq->ift_ifdi != NULL) { 1880 free(txq->ift_ifdi, M_IFLIB); 1881 } 1882 } 1883 1884 static void 1885 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1886 { 1887 struct mbuf **mp; 1888 1889 mp = &txq->ift_sds.ifsd_m[i]; 1890 if (*mp == NULL) 1891 return; 1892 1893 if (txq->ift_sds.ifsd_map != NULL) { 1894 bus_dmamap_sync(txq->ift_buf_tag, 1895 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1896 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1897 } 1898 if (txq->ift_sds.ifsd_tso_map != NULL) { 1899 bus_dmamap_sync(txq->ift_tso_buf_tag, 1900 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1901 bus_dmamap_unload(txq->ift_tso_buf_tag, 1902 txq->ift_sds.ifsd_tso_map[i]); 1903 } 1904 m_freem(*mp); 1905 DBG_COUNTER_INC(tx_frees); 1906 *mp = NULL; 1907 } 1908 1909 static int 1910 iflib_txq_setup(iflib_txq_t txq) 1911 { 1912 if_ctx_t ctx = txq->ift_ctx; 1913 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1914 if_shared_ctx_t sctx = ctx->ifc_sctx; 1915 iflib_dma_info_t di; 1916 int i; 1917 1918 /* Set number of descriptors available */ 1919 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1920 /* XXX make configurable */ 1921 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1922 1923 /* Reset indices */ 1924 txq->ift_cidx_processed = 0; 1925 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1926 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1927 1928 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1929 bzero((void *)di->idi_vaddr, di->idi_size); 1930 1931 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1932 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1933 bus_dmamap_sync(di->idi_tag, di->idi_map, 1934 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1935 return (0); 1936 } 1937 1938 /********************************************************************* 1939 * 1940 * Allocate DMA resources for RX buffers as well as memory for the RX 1941 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1942 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1943 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1944 * Since we use use one entry in iflib_sw_rx_desc_array per received 1945 * packet, the maximum number of entries we'll need is equal to the 1946 * number of hardware receive descriptors that we've allocated. 1947 * 1948 **********************************************************************/ 1949 static int 1950 iflib_rxsd_alloc(iflib_rxq_t rxq) 1951 { 1952 if_ctx_t ctx = rxq->ifr_ctx; 1953 if_shared_ctx_t sctx = ctx->ifc_sctx; 1954 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1955 device_t dev = ctx->ifc_dev; 1956 iflib_fl_t fl; 1957 bus_addr_t lowaddr; 1958 int err; 1959 1960 MPASS(scctx->isc_nrxd[0] > 0); 1961 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1962 1963 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1964 1965 fl = rxq->ifr_fl; 1966 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1967 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1968 /* Set up DMA tag for RX buffers. */ 1969 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1970 1, 0, /* alignment, bounds */ 1971 lowaddr, /* lowaddr */ 1972 BUS_SPACE_MAXADDR, /* highaddr */ 1973 NULL, NULL, /* filter, filterarg */ 1974 sctx->isc_rx_maxsize, /* maxsize */ 1975 sctx->isc_rx_nsegments, /* nsegments */ 1976 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1977 0, /* flags */ 1978 NULL, /* lockfunc */ 1979 NULL, /* lockarg */ 1980 &fl->ifl_buf_tag); 1981 if (err) { 1982 device_printf(dev, 1983 "Unable to allocate RX DMA tag: %d\n", err); 1984 goto fail; 1985 } 1986 1987 /* Allocate memory for the RX mbuf map. */ 1988 if (!(fl->ifl_sds.ifsd_m = 1989 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1990 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1991 device_printf(dev, 1992 "Unable to allocate RX mbuf map memory\n"); 1993 err = ENOMEM; 1994 goto fail; 1995 } 1996 1997 /* Allocate memory for the direct RX cluster pointer map. */ 1998 if (!(fl->ifl_sds.ifsd_cl = 1999 (caddr_t *) malloc(sizeof(caddr_t) * 2000 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2001 device_printf(dev, 2002 "Unable to allocate RX cluster map memory\n"); 2003 err = ENOMEM; 2004 goto fail; 2005 } 2006 2007 /* Allocate memory for the RX cluster bus address map. */ 2008 if (!(fl->ifl_sds.ifsd_ba = 2009 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 2010 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2011 device_printf(dev, 2012 "Unable to allocate RX bus address map memory\n"); 2013 err = ENOMEM; 2014 goto fail; 2015 } 2016 2017 /* 2018 * Create the DMA maps for RX buffers. 2019 */ 2020 if (!(fl->ifl_sds.ifsd_map = 2021 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2022 device_printf(dev, 2023 "Unable to allocate RX buffer DMA map memory\n"); 2024 err = ENOMEM; 2025 goto fail; 2026 } 2027 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 2028 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 2029 &fl->ifl_sds.ifsd_map[i]); 2030 if (err != 0) { 2031 device_printf(dev, "Unable to create RX buffer DMA map\n"); 2032 goto fail; 2033 } 2034 } 2035 } 2036 return (0); 2037 2038 fail: 2039 iflib_rx_structures_free(ctx); 2040 return (err); 2041 } 2042 2043 /* 2044 * Internal service routines 2045 */ 2046 2047 struct rxq_refill_cb_arg { 2048 int error; 2049 bus_dma_segment_t seg; 2050 int nseg; 2051 }; 2052 2053 static void 2054 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2055 { 2056 struct rxq_refill_cb_arg *cb_arg = arg; 2057 2058 cb_arg->error = error; 2059 cb_arg->seg = segs[0]; 2060 cb_arg->nseg = nseg; 2061 } 2062 2063 /** 2064 * iflib_fl_refill - refill an rxq free-buffer list 2065 * @ctx: the iflib context 2066 * @fl: the free list to refill 2067 * @count: the number of new buffers to allocate 2068 * 2069 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 2070 * The caller must assure that @count does not exceed the queue's capacity 2071 * minus one (since we always leave a descriptor unavailable). 2072 */ 2073 static uint8_t 2074 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 2075 { 2076 struct if_rxd_update iru; 2077 struct rxq_refill_cb_arg cb_arg; 2078 struct mbuf *m; 2079 caddr_t cl, *sd_cl; 2080 struct mbuf **sd_m; 2081 bus_dmamap_t *sd_map; 2082 bus_addr_t bus_addr, *sd_ba; 2083 int err, frag_idx, i, idx, n, pidx; 2084 qidx_t credits; 2085 2086 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 2087 2088 sd_m = fl->ifl_sds.ifsd_m; 2089 sd_map = fl->ifl_sds.ifsd_map; 2090 sd_cl = fl->ifl_sds.ifsd_cl; 2091 sd_ba = fl->ifl_sds.ifsd_ba; 2092 pidx = fl->ifl_pidx; 2093 idx = pidx; 2094 frag_idx = fl->ifl_fragidx; 2095 credits = fl->ifl_credits; 2096 2097 i = 0; 2098 n = count; 2099 MPASS(n > 0); 2100 MPASS(credits + n <= fl->ifl_size); 2101 2102 if (pidx < fl->ifl_cidx) 2103 MPASS(pidx + n <= fl->ifl_cidx); 2104 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 2105 MPASS(fl->ifl_gen == 0); 2106 if (pidx > fl->ifl_cidx) 2107 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 2108 2109 DBG_COUNTER_INC(fl_refills); 2110 if (n > 8) 2111 DBG_COUNTER_INC(fl_refills_large); 2112 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 2113 while (n-- > 0) { 2114 /* 2115 * We allocate an uninitialized mbuf + cluster, mbuf is 2116 * initialized after rx. 2117 * 2118 * If the cluster is still set then we know a minimum sized 2119 * packet was received 2120 */ 2121 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2122 &frag_idx); 2123 if (frag_idx < 0) 2124 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2125 MPASS(frag_idx >= 0); 2126 if ((cl = sd_cl[frag_idx]) == NULL) { 2127 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2128 if (__predict_false(cl == NULL)) 2129 break; 2130 2131 cb_arg.error = 0; 2132 MPASS(sd_map != NULL); 2133 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2134 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2135 BUS_DMA_NOWAIT); 2136 if (__predict_false(err != 0 || cb_arg.error)) { 2137 uma_zfree(fl->ifl_zone, cl); 2138 break; 2139 } 2140 2141 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2142 sd_cl[frag_idx] = cl; 2143 #if MEMORY_LOGGING 2144 fl->ifl_cl_enqueued++; 2145 #endif 2146 } else { 2147 bus_addr = sd_ba[frag_idx]; 2148 } 2149 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2150 BUS_DMASYNC_PREREAD); 2151 2152 if (sd_m[frag_idx] == NULL) { 2153 m = m_gethdr_raw(M_NOWAIT, 0); 2154 if (__predict_false(m == NULL)) 2155 break; 2156 sd_m[frag_idx] = m; 2157 } 2158 bit_set(fl->ifl_rx_bitmap, frag_idx); 2159 #if MEMORY_LOGGING 2160 fl->ifl_m_enqueued++; 2161 #endif 2162 2163 DBG_COUNTER_INC(rx_allocs); 2164 fl->ifl_rxd_idxs[i] = frag_idx; 2165 fl->ifl_bus_addrs[i] = bus_addr; 2166 credits++; 2167 i++; 2168 MPASS(credits <= fl->ifl_size); 2169 if (++idx == fl->ifl_size) { 2170 #ifdef INVARIANTS 2171 fl->ifl_gen = 1; 2172 #endif 2173 idx = 0; 2174 } 2175 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2176 iru.iru_pidx = pidx; 2177 iru.iru_count = i; 2178 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2179 fl->ifl_pidx = idx; 2180 fl->ifl_credits = credits; 2181 pidx = idx; 2182 i = 0; 2183 } 2184 } 2185 2186 if (n < count - 1) { 2187 if (i != 0) { 2188 iru.iru_pidx = pidx; 2189 iru.iru_count = i; 2190 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2191 fl->ifl_pidx = idx; 2192 fl->ifl_credits = credits; 2193 } 2194 DBG_COUNTER_INC(rxd_flush); 2195 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2196 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2197 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2198 fl->ifl_id, fl->ifl_pidx); 2199 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2200 fl->ifl_fragidx = frag_idx + 1; 2201 if (fl->ifl_fragidx == fl->ifl_size) 2202 fl->ifl_fragidx = 0; 2203 } else { 2204 fl->ifl_fragidx = frag_idx; 2205 } 2206 } 2207 2208 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2209 } 2210 2211 static inline uint8_t 2212 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2213 { 2214 /* 2215 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2216 * This is important as it confuses most NICs. For instance, 2217 * Intel NICs have (per receive ring) RDH and RDT registers, where 2218 * RDH points to the next receive descriptor to be used by the NIC, 2219 * and RDT for the next receive descriptor to be published by the 2220 * driver to the NIC (RDT - 1 is thus the last valid one). 2221 * The condition RDH == RDT means no descriptors are available to 2222 * the NIC, and thus it would be ambiguous if it also meant that 2223 * all the descriptors are available to the NIC. 2224 */ 2225 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2226 #ifdef INVARIANTS 2227 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2228 #endif 2229 2230 MPASS(fl->ifl_credits <= fl->ifl_size); 2231 MPASS(reclaimable == delta); 2232 2233 if (reclaimable > 0) 2234 return (iflib_fl_refill(ctx, fl, reclaimable)); 2235 return (0); 2236 } 2237 2238 uint8_t 2239 iflib_in_detach(if_ctx_t ctx) 2240 { 2241 bool in_detach; 2242 2243 STATE_LOCK(ctx); 2244 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2245 STATE_UNLOCK(ctx); 2246 return (in_detach); 2247 } 2248 2249 static void 2250 iflib_fl_bufs_free(iflib_fl_t fl) 2251 { 2252 iflib_dma_info_t idi = fl->ifl_ifdi; 2253 bus_dmamap_t sd_map; 2254 uint32_t i; 2255 2256 for (i = 0; i < fl->ifl_size; i++) { 2257 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2258 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2259 2260 if (*sd_cl != NULL) { 2261 sd_map = fl->ifl_sds.ifsd_map[i]; 2262 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2263 BUS_DMASYNC_POSTREAD); 2264 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2265 uma_zfree(fl->ifl_zone, *sd_cl); 2266 *sd_cl = NULL; 2267 if (*sd_m != NULL) { 2268 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2269 m_free_raw(*sd_m); 2270 *sd_m = NULL; 2271 } 2272 } else { 2273 MPASS(*sd_m == NULL); 2274 } 2275 #if MEMORY_LOGGING 2276 fl->ifl_m_dequeued++; 2277 fl->ifl_cl_dequeued++; 2278 #endif 2279 } 2280 #ifdef INVARIANTS 2281 for (i = 0; i < fl->ifl_size; i++) { 2282 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2283 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2284 } 2285 #endif 2286 /* 2287 * Reset free list values 2288 */ 2289 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2290 bzero(idi->idi_vaddr, idi->idi_size); 2291 } 2292 2293 /********************************************************************* 2294 * 2295 * Initialize a free list and its buffers. 2296 * 2297 **********************************************************************/ 2298 static int 2299 iflib_fl_setup(iflib_fl_t fl) 2300 { 2301 iflib_rxq_t rxq = fl->ifl_rxq; 2302 if_ctx_t ctx = rxq->ifr_ctx; 2303 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2304 int qidx; 2305 2306 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2307 /* 2308 * Free current RX buffer structs and their mbufs 2309 */ 2310 iflib_fl_bufs_free(fl); 2311 /* Now replenish the mbufs */ 2312 MPASS(fl->ifl_credits == 0); 2313 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2314 if (scctx->isc_rxd_buf_size[qidx] != 0) 2315 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2316 else 2317 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2318 /* 2319 * ifl_buf_size may be a driver-supplied value, so pull it up 2320 * to the selected mbuf size. 2321 */ 2322 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2323 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2324 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2325 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2326 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2327 2328 /* 2329 * Avoid pre-allocating zillions of clusters to an idle card 2330 * potentially speeding up attach. In any case make sure 2331 * to leave a descriptor unavailable. See the comment in 2332 * iflib_fl_refill_all(). 2333 */ 2334 MPASS(fl->ifl_size > 0); 2335 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2336 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2337 return (ENOBUFS); 2338 /* 2339 * handle failure 2340 */ 2341 MPASS(rxq != NULL); 2342 MPASS(fl->ifl_ifdi != NULL); 2343 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2344 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2345 return (0); 2346 } 2347 2348 /********************************************************************* 2349 * 2350 * Free receive ring data structures 2351 * 2352 **********************************************************************/ 2353 static void 2354 iflib_rx_sds_free(iflib_rxq_t rxq) 2355 { 2356 iflib_fl_t fl; 2357 int i, j; 2358 2359 if (rxq->ifr_fl != NULL) { 2360 for (i = 0; i < rxq->ifr_nfl; i++) { 2361 fl = &rxq->ifr_fl[i]; 2362 if (fl->ifl_buf_tag != NULL) { 2363 if (fl->ifl_sds.ifsd_map != NULL) { 2364 for (j = 0; j < fl->ifl_size; j++) { 2365 bus_dmamap_sync( 2366 fl->ifl_buf_tag, 2367 fl->ifl_sds.ifsd_map[j], 2368 BUS_DMASYNC_POSTREAD); 2369 bus_dmamap_unload( 2370 fl->ifl_buf_tag, 2371 fl->ifl_sds.ifsd_map[j]); 2372 bus_dmamap_destroy( 2373 fl->ifl_buf_tag, 2374 fl->ifl_sds.ifsd_map[j]); 2375 } 2376 } 2377 bus_dma_tag_destroy(fl->ifl_buf_tag); 2378 fl->ifl_buf_tag = NULL; 2379 } 2380 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2381 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2382 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2383 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2384 free(fl->ifl_rx_bitmap, M_IFLIB); 2385 fl->ifl_sds.ifsd_m = NULL; 2386 fl->ifl_sds.ifsd_cl = NULL; 2387 fl->ifl_sds.ifsd_ba = NULL; 2388 fl->ifl_sds.ifsd_map = NULL; 2389 fl->ifl_rx_bitmap = NULL; 2390 } 2391 free(rxq->ifr_fl, M_IFLIB); 2392 rxq->ifr_fl = NULL; 2393 free(rxq->ifr_ifdi, M_IFLIB); 2394 rxq->ifr_ifdi = NULL; 2395 rxq->ifr_cq_cidx = 0; 2396 } 2397 } 2398 2399 /* 2400 * Timer routine 2401 */ 2402 static void 2403 iflib_timer(void *arg) 2404 { 2405 iflib_txq_t txq = arg; 2406 if_ctx_t ctx = txq->ift_ctx; 2407 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2408 uint64_t this_tick = ticks; 2409 2410 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2411 return; 2412 2413 /* 2414 ** Check on the state of the TX queue(s), this 2415 ** can be done without the lock because its RO 2416 ** and the HUNG state will be static if set. 2417 */ 2418 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) { 2419 txq->ift_last_timer_tick = this_tick; 2420 IFDI_TIMER(ctx, txq->ift_id); 2421 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2422 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2423 (sctx->isc_pause_frames == 0))) 2424 goto hung; 2425 2426 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2427 ifmp_ring_is_stalled(txq->ift_br)) { 2428 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, 2429 ("queue can't be marked as hung if interface is down")); 2430 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2431 } 2432 txq->ift_cleaned_prev = txq->ift_cleaned; 2433 } 2434 /* handle any laggards */ 2435 if (txq->ift_db_pending) 2436 GROUPTASK_ENQUEUE(&txq->ift_task); 2437 2438 sctx->isc_pause_frames = 0; 2439 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2440 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, 2441 txq, txq->ift_timer.c_cpu); 2442 return; 2443 2444 hung: 2445 device_printf(ctx->ifc_dev, 2446 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2447 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2448 STATE_LOCK(ctx); 2449 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2450 ctx->ifc_flags |= (IFC_DO_WATCHDOG | IFC_DO_RESET); 2451 iflib_admin_intr_deferred(ctx); 2452 STATE_UNLOCK(ctx); 2453 } 2454 2455 static uint16_t 2456 iflib_get_mbuf_size_for(unsigned int size) 2457 { 2458 2459 if (size <= MCLBYTES) 2460 return (MCLBYTES); 2461 else 2462 return (MJUMPAGESIZE); 2463 } 2464 2465 static void 2466 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2467 { 2468 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2469 2470 /* 2471 * XXX don't set the max_frame_size to larger 2472 * than the hardware can handle 2473 */ 2474 ctx->ifc_rx_mbuf_sz = 2475 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2476 } 2477 2478 uint32_t 2479 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2480 { 2481 2482 return (ctx->ifc_rx_mbuf_sz); 2483 } 2484 2485 static void 2486 iflib_init_locked(if_ctx_t ctx) 2487 { 2488 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2489 if_t ifp = ctx->ifc_ifp; 2490 iflib_fl_t fl; 2491 iflib_txq_t txq; 2492 iflib_rxq_t rxq; 2493 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2494 2495 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2496 IFDI_INTR_DISABLE(ctx); 2497 2498 /* 2499 * See iflib_stop(). Useful in case iflib_init_locked() is 2500 * called without first calling iflib_stop(). 2501 */ 2502 netmap_disable_all_rings(ifp); 2503 2504 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2505 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2506 /* Set hardware offload abilities */ 2507 if_clearhwassist(ifp); 2508 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2509 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2510 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2511 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2512 if (if_getcapenable(ifp) & IFCAP_TSO4) 2513 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2514 if (if_getcapenable(ifp) & IFCAP_TSO6) 2515 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2516 2517 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 2518 CALLOUT_LOCK(txq); 2519 callout_stop(&txq->ift_timer); 2520 #ifdef DEV_NETMAP 2521 callout_stop(&txq->ift_netmap_timer); 2522 #endif /* DEV_NETMAP */ 2523 CALLOUT_UNLOCK(txq); 2524 (void)iflib_netmap_txq_init(ctx, txq); 2525 } 2526 2527 /* 2528 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2529 * that drivers can use the value when setting up the hardware receive 2530 * buffers. 2531 */ 2532 iflib_calc_rx_mbuf_sz(ctx); 2533 2534 #ifdef INVARIANTS 2535 i = if_getdrvflags(ifp); 2536 #endif 2537 IFDI_INIT(ctx); 2538 MPASS(if_getdrvflags(ifp) == i); 2539 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 2540 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2541 /* This rxq is in netmap mode. Skip normal init. */ 2542 continue; 2543 } 2544 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2545 if (iflib_fl_setup(fl)) { 2546 device_printf(ctx->ifc_dev, 2547 "setting up free list %d failed - " 2548 "check cluster settings\n", j); 2549 goto done; 2550 } 2551 } 2552 } 2553 done: 2554 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2555 IFDI_INTR_ENABLE(ctx); 2556 txq = ctx->ifc_txqs; 2557 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) 2558 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 2559 txq->ift_timer.c_cpu); 2560 2561 /* Re-enable txsync/rxsync. */ 2562 netmap_enable_all_rings(ifp); 2563 } 2564 2565 static int 2566 iflib_media_change(if_t ifp) 2567 { 2568 if_ctx_t ctx = if_getsoftc(ifp); 2569 int err; 2570 2571 CTX_LOCK(ctx); 2572 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2573 iflib_if_init_locked(ctx); 2574 CTX_UNLOCK(ctx); 2575 return (err); 2576 } 2577 2578 static void 2579 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2580 { 2581 if_ctx_t ctx = if_getsoftc(ifp); 2582 2583 CTX_LOCK(ctx); 2584 IFDI_UPDATE_ADMIN_STATUS(ctx); 2585 IFDI_MEDIA_STATUS(ctx, ifmr); 2586 CTX_UNLOCK(ctx); 2587 } 2588 2589 static void 2590 iflib_stop(if_ctx_t ctx) 2591 { 2592 iflib_txq_t txq = ctx->ifc_txqs; 2593 iflib_rxq_t rxq = ctx->ifc_rxqs; 2594 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2595 if_shared_ctx_t sctx = ctx->ifc_sctx; 2596 iflib_dma_info_t di; 2597 iflib_fl_t fl; 2598 int i, j; 2599 2600 /* Tell the stack that the interface is no longer active */ 2601 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2602 2603 IFDI_INTR_DISABLE(ctx); 2604 DELAY(1000); 2605 IFDI_STOP(ctx); 2606 DELAY(1000); 2607 2608 /* 2609 * Stop any pending txsync/rxsync and prevent new ones 2610 * form starting. Processes blocked in poll() will get 2611 * POLLERR. 2612 */ 2613 netmap_disable_all_rings(ctx->ifc_ifp); 2614 2615 iflib_debug_reset(); 2616 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2617 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2618 /* make sure all transmitters have completed before proceeding XXX */ 2619 2620 CALLOUT_LOCK(txq); 2621 callout_stop(&txq->ift_timer); 2622 #ifdef DEV_NETMAP 2623 callout_stop(&txq->ift_netmap_timer); 2624 #endif /* DEV_NETMAP */ 2625 CALLOUT_UNLOCK(txq); 2626 2627 /* clean any enqueued buffers */ 2628 iflib_ifmp_purge(txq); 2629 /* Free any existing tx buffers. */ 2630 for (j = 0; j < txq->ift_size; j++) { 2631 iflib_txsd_free(ctx, txq, j); 2632 } 2633 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2634 txq->ift_in_use = txq->ift_gen = txq->ift_no_desc_avail = 0; 2635 if (sctx->isc_flags & IFLIB_PRESERVE_TX_INDICES) 2636 txq->ift_cidx = txq->ift_pidx; 2637 else 2638 txq->ift_cidx = txq->ift_pidx = 0; 2639 2640 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2641 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2642 txq->ift_pullups = 0; 2643 ifmp_ring_reset_stats(txq->ift_br); 2644 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2645 bzero((void *)di->idi_vaddr, di->idi_size); 2646 } 2647 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2648 if (rxq->ifr_task.gt_taskqueue != NULL) 2649 gtaskqueue_drain(rxq->ifr_task.gt_taskqueue, 2650 &rxq->ifr_task.gt_task); 2651 2652 rxq->ifr_cq_cidx = 0; 2653 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2654 bzero((void *)di->idi_vaddr, di->idi_size); 2655 /* also resets the free lists pidx/cidx */ 2656 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2657 iflib_fl_bufs_free(fl); 2658 } 2659 } 2660 2661 static inline caddr_t 2662 calc_next_rxd(iflib_fl_t fl, int cidx) 2663 { 2664 qidx_t size; 2665 int nrxd; 2666 caddr_t start, end, cur, next; 2667 2668 nrxd = fl->ifl_size; 2669 size = fl->ifl_rxd_size; 2670 start = fl->ifl_ifdi->idi_vaddr; 2671 2672 if (__predict_false(size == 0)) 2673 return (start); 2674 cur = start + size * cidx; 2675 end = start + size * nrxd; 2676 next = CACHE_PTR_NEXT(cur); 2677 return (next < end ? next : start); 2678 } 2679 2680 static inline void 2681 prefetch_pkts(iflib_fl_t fl, int cidx) 2682 { 2683 int nextptr; 2684 int nrxd = fl->ifl_size; 2685 caddr_t next_rxd; 2686 2687 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd - 1); 2688 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2689 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2690 next_rxd = calc_next_rxd(fl, cidx); 2691 prefetch(next_rxd); 2692 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd - 1)]); 2693 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd - 1)]); 2694 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd - 1)]); 2695 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd - 1)]); 2696 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd - 1)]); 2697 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd - 1)]); 2698 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd - 1)]); 2699 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd - 1)]); 2700 } 2701 2702 static struct mbuf * 2703 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2704 int *pf_rv, if_rxd_info_t ri) 2705 { 2706 bus_dmamap_t map; 2707 iflib_fl_t fl; 2708 caddr_t payload; 2709 struct mbuf *m; 2710 int flid, cidx, len, next; 2711 2712 map = NULL; 2713 flid = irf->irf_flid; 2714 cidx = irf->irf_idx; 2715 fl = &rxq->ifr_fl[flid]; 2716 sd->ifsd_fl = fl; 2717 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2718 fl->ifl_credits--; 2719 #if MEMORY_LOGGING 2720 fl->ifl_m_dequeued++; 2721 #endif 2722 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2723 prefetch_pkts(fl, cidx); 2724 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size - 1); 2725 prefetch(&fl->ifl_sds.ifsd_map[next]); 2726 map = fl->ifl_sds.ifsd_map[cidx]; 2727 2728 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2729 2730 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2731 irf->irf_len != 0) { 2732 payload = *sd->ifsd_cl; 2733 payload += ri->iri_pad; 2734 len = ri->iri_len - ri->iri_pad; 2735 *pf_rv = pfil_mem_in(rxq->pfil, payload, len, ri->iri_ifp, &m); 2736 switch (*pf_rv) { 2737 case PFIL_DROPPED: 2738 case PFIL_CONSUMED: 2739 /* 2740 * The filter ate it. Everything is recycled. 2741 */ 2742 m = NULL; 2743 unload = 0; 2744 break; 2745 case PFIL_REALLOCED: 2746 /* 2747 * The filter copied it. Everything is recycled. 2748 * 'm' points at new mbuf. 2749 */ 2750 unload = 0; 2751 break; 2752 case PFIL_PASS: 2753 /* 2754 * Filter said it was OK, so receive like 2755 * normal 2756 */ 2757 m = fl->ifl_sds.ifsd_m[cidx]; 2758 fl->ifl_sds.ifsd_m[cidx] = NULL; 2759 break; 2760 default: 2761 MPASS(0); 2762 } 2763 } else { 2764 m = fl->ifl_sds.ifsd_m[cidx]; 2765 fl->ifl_sds.ifsd_m[cidx] = NULL; 2766 if (pf_rv != NULL) 2767 *pf_rv = PFIL_PASS; 2768 } 2769 2770 if (unload && irf->irf_len != 0) 2771 bus_dmamap_unload(fl->ifl_buf_tag, map); 2772 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size - 1); 2773 if (__predict_false(fl->ifl_cidx == 0)) 2774 fl->ifl_gen = 0; 2775 bit_clear(fl->ifl_rx_bitmap, cidx); 2776 return (m); 2777 } 2778 2779 static struct mbuf * 2780 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2781 { 2782 struct mbuf *m, *mh, *mt; 2783 caddr_t cl; 2784 int *pf_rv_ptr, flags, i, padlen; 2785 bool consumed; 2786 2787 i = 0; 2788 mh = NULL; 2789 consumed = false; 2790 *pf_rv = PFIL_PASS; 2791 pf_rv_ptr = pf_rv; 2792 do { 2793 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2794 pf_rv_ptr, ri); 2795 2796 MPASS(*sd->ifsd_cl != NULL); 2797 2798 /* 2799 * Exclude zero-length frags & frags from 2800 * packets the filter has consumed or dropped 2801 */ 2802 if (ri->iri_frags[i].irf_len == 0 || consumed || 2803 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2804 if (mh == NULL) { 2805 /* everything saved here */ 2806 consumed = true; 2807 pf_rv_ptr = NULL; 2808 continue; 2809 } 2810 /* XXX we can save the cluster here, but not the mbuf */ 2811 m_init(m, M_NOWAIT, MT_DATA, 0); 2812 m_free(m); 2813 continue; 2814 } 2815 if (mh == NULL) { 2816 flags = M_PKTHDR | M_EXT; 2817 mh = mt = m; 2818 padlen = ri->iri_pad; 2819 } else { 2820 flags = M_EXT; 2821 mt->m_next = m; 2822 mt = m; 2823 /* assuming padding is only on the first fragment */ 2824 padlen = 0; 2825 } 2826 cl = *sd->ifsd_cl; 2827 *sd->ifsd_cl = NULL; 2828 2829 /* Can these two be made one ? */ 2830 m_init(m, M_NOWAIT, MT_DATA, flags); 2831 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2832 /* 2833 * These must follow m_init and m_cljset 2834 */ 2835 m->m_data += padlen; 2836 ri->iri_len -= padlen; 2837 m->m_len = ri->iri_frags[i].irf_len; 2838 } while (++i < ri->iri_nfrags); 2839 2840 return (mh); 2841 } 2842 2843 /* 2844 * Process one software descriptor 2845 */ 2846 static struct mbuf * 2847 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2848 { 2849 struct if_rxsd sd; 2850 struct mbuf *m; 2851 int pf_rv; 2852 2853 /* should I merge this back in now that the two paths are basically duplicated? */ 2854 if (ri->iri_nfrags == 1 && 2855 ri->iri_frags[0].irf_len != 0 && 2856 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2857 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2858 &pf_rv, ri); 2859 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2860 return (m); 2861 if (pf_rv == PFIL_PASS) { 2862 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2863 #ifndef __NO_STRICT_ALIGNMENT 2864 if (!IP_ALIGNED(m) && ri->iri_pad == 0) 2865 m->m_data += 2; 2866 #endif 2867 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2868 m->m_len = ri->iri_frags[0].irf_len; 2869 m->m_data += ri->iri_pad; 2870 ri->iri_len -= ri->iri_pad; 2871 } 2872 } else { 2873 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2874 if (m == NULL) 2875 return (NULL); 2876 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2877 return (m); 2878 } 2879 m->m_pkthdr.len = ri->iri_len; 2880 m->m_pkthdr.rcvif = ri->iri_ifp; 2881 m->m_flags |= ri->iri_flags; 2882 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2883 m->m_pkthdr.flowid = ri->iri_flowid; 2884 #ifdef NUMA 2885 m->m_pkthdr.numa_domain = if_getnumadomain(ri->iri_ifp); 2886 #endif 2887 M_HASHTYPE_SET(m, ri->iri_rsstype); 2888 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2889 m->m_pkthdr.csum_data = ri->iri_csum_data; 2890 return (m); 2891 } 2892 2893 static void 2894 _task_fn_rx_watchdog(void *context) 2895 { 2896 iflib_rxq_t rxq = context; 2897 2898 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2899 } 2900 2901 static uint8_t 2902 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2903 { 2904 if_t ifp; 2905 if_ctx_t ctx = rxq->ifr_ctx; 2906 if_shared_ctx_t sctx = ctx->ifc_sctx; 2907 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2908 int avail, i; 2909 qidx_t *cidxp; 2910 struct if_rxd_info ri; 2911 int err, budget_left, rx_bytes, rx_pkts; 2912 iflib_fl_t fl; 2913 #if defined(INET6) || defined(INET) 2914 int lro_enabled; 2915 #endif 2916 uint8_t retval = 0; 2917 2918 /* 2919 * XXX early demux data packets so that if_input processing only handles 2920 * acks in interrupt context 2921 */ 2922 struct mbuf *m, *mh, *mt; 2923 2924 NET_EPOCH_ASSERT(); 2925 2926 ifp = ctx->ifc_ifp; 2927 mh = mt = NULL; 2928 MPASS(budget > 0); 2929 rx_pkts = rx_bytes = 0; 2930 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2931 cidxp = &rxq->ifr_cq_cidx; 2932 else 2933 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2934 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2935 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2936 retval |= iflib_fl_refill_all(ctx, fl); 2937 DBG_COUNTER_INC(rx_unavail); 2938 return (retval); 2939 } 2940 2941 #if defined(INET6) || defined(INET) 2942 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2943 #endif 2944 2945 /* pfil needs the vnet to be set */ 2946 CURVNET_SET_QUIET(if_getvnet(ifp)); 2947 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2948 if (__predict_false(!CTX_ACTIVE(ctx))) { 2949 DBG_COUNTER_INC(rx_ctx_inactive); 2950 break; 2951 } 2952 /* 2953 * Reset client set fields to their default values 2954 */ 2955 rxd_info_zero(&ri); 2956 ri.iri_qsidx = rxq->ifr_id; 2957 ri.iri_cidx = *cidxp; 2958 ri.iri_ifp = ifp; 2959 ri.iri_frags = rxq->ifr_frags; 2960 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2961 2962 if (err) 2963 goto err; 2964 rx_pkts += 1; 2965 rx_bytes += ri.iri_len; 2966 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2967 *cidxp = ri.iri_cidx; 2968 /* Update our consumer index */ 2969 /* XXX NB: shurd - check if this is still safe */ 2970 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2971 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2972 /* was this only a completion queue message? */ 2973 if (__predict_false(ri.iri_nfrags == 0)) 2974 continue; 2975 } 2976 MPASS(ri.iri_nfrags != 0); 2977 MPASS(ri.iri_len != 0); 2978 2979 /* will advance the cidx on the corresponding free lists */ 2980 m = iflib_rxd_pkt_get(rxq, &ri); 2981 avail--; 2982 budget_left--; 2983 if (avail == 0 && budget_left) 2984 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2985 2986 if (__predict_false(m == NULL)) 2987 continue; 2988 2989 #ifndef __NO_STRICT_ALIGNMENT 2990 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2991 continue; 2992 #endif 2993 #if defined(INET6) || defined(INET) 2994 if (lro_enabled) { 2995 tcp_lro_queue_mbuf(&rxq->ifr_lc, m); 2996 continue; 2997 } 2998 #endif 2999 3000 if (mh == NULL) 3001 mh = mt = m; 3002 else { 3003 mt->m_nextpkt = m; 3004 mt = m; 3005 } 3006 } 3007 CURVNET_RESTORE(); 3008 /* make sure that we can refill faster than drain */ 3009 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3010 retval |= iflib_fl_refill_all(ctx, fl); 3011 3012 if (mh != NULL) { 3013 if_input(ifp, mh); 3014 DBG_COUNTER_INC(rx_if_input); 3015 } 3016 3017 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 3018 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 3019 3020 /* 3021 * Flush any outstanding LRO work 3022 */ 3023 #if defined(INET6) || defined(INET) 3024 tcp_lro_flush_all(&rxq->ifr_lc); 3025 #endif 3026 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 3027 retval |= IFLIB_RXEOF_MORE; 3028 return (retval); 3029 err: 3030 STATE_LOCK(ctx); 3031 ctx->ifc_flags |= IFC_DO_RESET; 3032 iflib_admin_intr_deferred(ctx); 3033 STATE_UNLOCK(ctx); 3034 return (0); 3035 } 3036 3037 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq) - 1) 3038 static inline qidx_t 3039 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 3040 { 3041 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3042 qidx_t minthresh = txq->ift_size / 8; 3043 if (in_use > 4 * minthresh) 3044 return (notify_count); 3045 if (in_use > 2 * minthresh) 3046 return (notify_count >> 1); 3047 if (in_use > minthresh) 3048 return (notify_count >> 3); 3049 return (0); 3050 } 3051 3052 static inline qidx_t 3053 txq_max_rs_deferred(iflib_txq_t txq) 3054 { 3055 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3056 qidx_t minthresh = txq->ift_size / 8; 3057 if (txq->ift_in_use > 4 * minthresh) 3058 return (notify_count); 3059 if (txq->ift_in_use > 2 * minthresh) 3060 return (notify_count >> 1); 3061 if (txq->ift_in_use > minthresh) 3062 return (notify_count >> 2); 3063 return (2); 3064 } 3065 3066 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 3067 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 3068 3069 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 3070 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 3071 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 3072 3073 /* forward compatibility for cxgb */ 3074 #define FIRST_QSET(ctx) 0 3075 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3076 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3077 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3078 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3079 3080 /* XXX we should be setting this to something other than zero */ 3081 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 3082 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3083 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3084 3085 static inline bool 3086 iflib_txd_db_check(iflib_txq_t txq, int ring) 3087 { 3088 if_ctx_t ctx = txq->ift_ctx; 3089 qidx_t dbval, max; 3090 3091 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use); 3092 3093 /* force || threshold exceeded || at the edge of the ring */ 3094 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2)) { 3095 3096 /* 3097 * 'npending' is used if the card's doorbell is in terms of the number of descriptors 3098 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the 3099 * producer index explicitly (INTC). 3100 */ 3101 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3102 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3103 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3104 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3105 3106 /* 3107 * Absent bugs there are zero packets pending so reset pending counts to zero. 3108 */ 3109 txq->ift_db_pending = txq->ift_npending = 0; 3110 return (true); 3111 } 3112 return (false); 3113 } 3114 3115 #ifdef PKT_DEBUG 3116 static void 3117 print_pkt(if_pkt_info_t pi) 3118 { 3119 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3120 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3121 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3122 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3123 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3124 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3125 } 3126 #endif 3127 3128 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3129 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3130 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3131 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3132 3133 /** 3134 * Parses out ethernet header information in the given mbuf. 3135 * Returns in pi: ipi_etype (EtherType) and ipi_ehdrlen (Ethernet header length) 3136 * 3137 * This will account for the VLAN header if present. 3138 * 3139 * XXX: This doesn't handle QinQ, which could prevent TX offloads for those 3140 * types of packets. 3141 */ 3142 static int 3143 iflib_parse_ether_header(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3144 { 3145 struct ether_vlan_header *eh; 3146 struct mbuf *m; 3147 3148 m = *mp; 3149 if (__predict_false(m->m_len < sizeof(*eh))) { 3150 (*pullups)++; 3151 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3152 return (ENOMEM); 3153 } 3154 eh = mtod(m, struct ether_vlan_header *); 3155 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3156 pi->ipi_etype = ntohs(eh->evl_proto); 3157 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3158 } else { 3159 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3160 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3161 } 3162 *mp = m; 3163 3164 return (0); 3165 } 3166 3167 /** 3168 * Parse up to the L3 header and extract IPv4/IPv6 header information into pi. 3169 * Currently this information includes: IP ToS value, IP header version/presence 3170 * 3171 * This is missing some checks and doesn't edit the packet content as it goes, 3172 * unlike iflib_parse_header(), in order to keep the amount of code here minimal. 3173 */ 3174 static int 3175 iflib_parse_header_partial(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3176 { 3177 struct mbuf *m; 3178 int err; 3179 3180 *pullups = 0; 3181 m = *mp; 3182 if (!M_WRITABLE(m)) { 3183 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3184 return (ENOMEM); 3185 } else { 3186 m_freem(*mp); 3187 DBG_COUNTER_INC(tx_frees); 3188 *mp = m; 3189 } 3190 } 3191 3192 /* Fills out pi->ipi_etype */ 3193 err = iflib_parse_ether_header(pi, mp, pullups); 3194 if (err) 3195 return (err); 3196 m = *mp; 3197 3198 switch (pi->ipi_etype) { 3199 #ifdef INET 3200 case ETHERTYPE_IP: 3201 { 3202 struct mbuf *n; 3203 struct ip *ip = NULL; 3204 int miniplen; 3205 3206 miniplen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip)); 3207 if (__predict_false(m->m_len < miniplen)) { 3208 /* 3209 * Check for common case where the first mbuf only contains 3210 * the Ethernet header 3211 */ 3212 if (m->m_len == pi->ipi_ehdrlen) { 3213 n = m->m_next; 3214 MPASS(n); 3215 /* If next mbuf contains at least the minimal IP header, then stop */ 3216 if (n->m_len >= sizeof(*ip)) { 3217 ip = (struct ip *)n->m_data; 3218 } else { 3219 (*pullups)++; 3220 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3221 return (ENOMEM); 3222 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3223 } 3224 } else { 3225 (*pullups)++; 3226 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3227 return (ENOMEM); 3228 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3229 } 3230 } else { 3231 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3232 } 3233 3234 /* Have the IPv4 header w/ no options here */ 3235 pi->ipi_ip_hlen = ip->ip_hl << 2; 3236 pi->ipi_ipproto = ip->ip_p; 3237 pi->ipi_ip_tos = ip->ip_tos; 3238 pi->ipi_flags |= IPI_TX_IPV4; 3239 3240 break; 3241 } 3242 #endif 3243 #ifdef INET6 3244 case ETHERTYPE_IPV6: 3245 { 3246 struct ip6_hdr *ip6; 3247 3248 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3249 (*pullups)++; 3250 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3251 return (ENOMEM); 3252 } 3253 ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3254 3255 /* Have the IPv6 fixed header here */ 3256 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3257 pi->ipi_ipproto = ip6->ip6_nxt; 3258 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3259 pi->ipi_flags |= IPI_TX_IPV6; 3260 3261 break; 3262 } 3263 #endif 3264 default: 3265 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3266 pi->ipi_ip_hlen = 0; 3267 break; 3268 } 3269 *mp = m; 3270 3271 return (0); 3272 3273 } 3274 3275 static int 3276 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3277 { 3278 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3279 struct mbuf *m; 3280 int err; 3281 3282 m = *mp; 3283 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3284 M_WRITABLE(m) == 0) { 3285 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3286 return (ENOMEM); 3287 } else { 3288 m_freem(*mp); 3289 DBG_COUNTER_INC(tx_frees); 3290 *mp = m; 3291 } 3292 } 3293 3294 /* Fills out pi->ipi_etype */ 3295 err = iflib_parse_ether_header(pi, mp, &txq->ift_pullups); 3296 if (__predict_false(err)) 3297 return (err); 3298 m = *mp; 3299 3300 switch (pi->ipi_etype) { 3301 #ifdef INET 3302 case ETHERTYPE_IP: 3303 { 3304 struct ip *ip; 3305 struct tcphdr *th; 3306 uint8_t hlen; 3307 3308 hlen = pi->ipi_ehdrlen + sizeof(*ip); 3309 if (__predict_false(m->m_len < hlen)) { 3310 txq->ift_pullups++; 3311 if (__predict_false((m = m_pullup(m, hlen)) == NULL)) 3312 return (ENOMEM); 3313 } 3314 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3315 hlen = pi->ipi_ehdrlen + (ip->ip_hl << 2); 3316 if (ip->ip_p == IPPROTO_TCP) { 3317 hlen += sizeof(*th); 3318 th = (struct tcphdr *)((char *)ip + (ip->ip_hl << 2)); 3319 } else if (ip->ip_p == IPPROTO_UDP) { 3320 hlen += sizeof(struct udphdr); 3321 } 3322 if (__predict_false(m->m_len < hlen)) { 3323 txq->ift_pullups++; 3324 if ((m = m_pullup(m, hlen)) == NULL) 3325 return (ENOMEM); 3326 } 3327 pi->ipi_ip_hlen = ip->ip_hl << 2; 3328 pi->ipi_ipproto = ip->ip_p; 3329 pi->ipi_ip_tos = ip->ip_tos; 3330 pi->ipi_flags |= IPI_TX_IPV4; 3331 3332 /* TCP checksum offload may require TCP header length */ 3333 if (IS_TX_OFFLOAD4(pi)) { 3334 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3335 pi->ipi_tcp_hflags = tcp_get_flags(th); 3336 pi->ipi_tcp_hlen = th->th_off << 2; 3337 pi->ipi_tcp_seq = th->th_seq; 3338 } 3339 if (IS_TSO4(pi)) { 3340 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3341 return (ENXIO); 3342 /* 3343 * TSO always requires hardware checksum offload. 3344 */ 3345 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3346 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3347 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3348 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3349 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3350 ip->ip_sum = 0; 3351 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3352 } 3353 } 3354 } 3355 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3356 ip->ip_sum = 0; 3357 3358 break; 3359 } 3360 #endif 3361 #ifdef INET6 3362 case ETHERTYPE_IPV6: 3363 { 3364 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3365 struct tcphdr *th; 3366 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3367 3368 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3369 txq->ift_pullups++; 3370 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3371 return (ENOMEM); 3372 } 3373 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3374 3375 /* XXX-BZ this will go badly in case of ext hdrs. */ 3376 pi->ipi_ipproto = ip6->ip6_nxt; 3377 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3378 pi->ipi_flags |= IPI_TX_IPV6; 3379 3380 /* TCP checksum offload may require TCP header length */ 3381 if (IS_TX_OFFLOAD6(pi)) { 3382 if (pi->ipi_ipproto == IPPROTO_TCP) { 3383 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3384 txq->ift_pullups++; 3385 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3386 return (ENOMEM); 3387 } 3388 pi->ipi_tcp_hflags = tcp_get_flags(th); 3389 pi->ipi_tcp_hlen = th->th_off << 2; 3390 pi->ipi_tcp_seq = th->th_seq; 3391 } 3392 if (IS_TSO6(pi)) { 3393 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3394 return (ENXIO); 3395 /* 3396 * TSO always requires hardware checksum offload. 3397 */ 3398 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3399 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3400 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3401 } 3402 } 3403 break; 3404 } 3405 #endif 3406 default: 3407 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3408 pi->ipi_ip_hlen = 0; 3409 break; 3410 } 3411 *mp = m; 3412 3413 return (0); 3414 } 3415 3416 /* 3417 * If dodgy hardware rejects the scatter gather chain we've handed it 3418 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3419 * m_defrag'd mbufs 3420 */ 3421 static __noinline struct mbuf * 3422 iflib_remove_mbuf(iflib_txq_t txq) 3423 { 3424 int ntxd, pidx; 3425 struct mbuf *m, **ifsd_m; 3426 3427 ifsd_m = txq->ift_sds.ifsd_m; 3428 ntxd = txq->ift_size; 3429 pidx = txq->ift_pidx & (ntxd - 1); 3430 ifsd_m = txq->ift_sds.ifsd_m; 3431 m = ifsd_m[pidx]; 3432 ifsd_m[pidx] = NULL; 3433 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3434 if (txq->ift_sds.ifsd_tso_map != NULL) 3435 bus_dmamap_unload(txq->ift_tso_buf_tag, 3436 txq->ift_sds.ifsd_tso_map[pidx]); 3437 #if MEMORY_LOGGING 3438 txq->ift_dequeued++; 3439 #endif 3440 return (m); 3441 } 3442 3443 static inline caddr_t 3444 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3445 { 3446 qidx_t size; 3447 int ntxd; 3448 caddr_t start, end, cur, next; 3449 3450 ntxd = txq->ift_size; 3451 size = txq->ift_txd_size[qid]; 3452 start = txq->ift_ifdi[qid].idi_vaddr; 3453 3454 if (__predict_false(size == 0)) 3455 return (start); 3456 cur = start + size * cidx; 3457 end = start + size * ntxd; 3458 next = CACHE_PTR_NEXT(cur); 3459 return (next < end ? next : start); 3460 } 3461 3462 /* 3463 * Pad an mbuf to ensure a minimum ethernet frame size. 3464 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3465 */ 3466 static __noinline int 3467 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3468 { 3469 /* 3470 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3471 * and ARP message is the smallest common payload I can think of 3472 */ 3473 static char pad[18]; /* just zeros */ 3474 int n; 3475 struct mbuf *new_head; 3476 3477 if (!M_WRITABLE(*m_head)) { 3478 new_head = m_dup(*m_head, M_NOWAIT); 3479 if (new_head == NULL) { 3480 m_freem(*m_head); 3481 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3482 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3483 DBG_COUNTER_INC(tx_frees); 3484 return (ENOMEM); 3485 } 3486 m_freem(*m_head); 3487 *m_head = new_head; 3488 } 3489 3490 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3491 n > 0; n -= sizeof(pad)) 3492 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3493 break; 3494 3495 if (n > 0) { 3496 m_freem(*m_head); 3497 device_printf(dev, "cannot pad short frame\n"); 3498 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3499 DBG_COUNTER_INC(tx_frees); 3500 return (ENOBUFS); 3501 } 3502 3503 return (0); 3504 } 3505 3506 static int 3507 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3508 { 3509 if_ctx_t ctx; 3510 if_shared_ctx_t sctx; 3511 if_softc_ctx_t scctx; 3512 bus_dma_tag_t buf_tag; 3513 bus_dma_segment_t *segs; 3514 struct mbuf *m_head, **ifsd_m; 3515 void *next_txd; 3516 bus_dmamap_t map; 3517 struct if_pkt_info pi; 3518 int remap = 0; 3519 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3520 3521 ctx = txq->ift_ctx; 3522 sctx = ctx->ifc_sctx; 3523 scctx = &ctx->ifc_softc_ctx; 3524 segs = txq->ift_segs; 3525 ntxd = txq->ift_size; 3526 m_head = *m_headp; 3527 map = NULL; 3528 3529 /* 3530 * If we're doing TSO the next descriptor to clean may be quite far ahead 3531 */ 3532 cidx = txq->ift_cidx; 3533 pidx = txq->ift_pidx; 3534 if (ctx->ifc_flags & IFC_PREFETCH) { 3535 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd - 1); 3536 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3537 next_txd = calc_next_txd(txq, cidx, 0); 3538 prefetch(next_txd); 3539 } 3540 3541 /* prefetch the next cache line of mbuf pointers and flags */ 3542 prefetch(&txq->ift_sds.ifsd_m[next]); 3543 prefetch(&txq->ift_sds.ifsd_map[next]); 3544 next = (cidx + CACHE_LINE_SIZE) & (ntxd - 1); 3545 } 3546 map = txq->ift_sds.ifsd_map[pidx]; 3547 ifsd_m = txq->ift_sds.ifsd_m; 3548 3549 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3550 buf_tag = txq->ift_tso_buf_tag; 3551 max_segs = scctx->isc_tx_tso_segments_max; 3552 map = txq->ift_sds.ifsd_tso_map[pidx]; 3553 MPASS(buf_tag != NULL); 3554 MPASS(max_segs > 0); 3555 } else { 3556 buf_tag = txq->ift_buf_tag; 3557 max_segs = scctx->isc_tx_nsegments; 3558 map = txq->ift_sds.ifsd_map[pidx]; 3559 } 3560 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3561 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3562 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3563 if (err) { 3564 DBG_COUNTER_INC(encap_txd_encap_fail); 3565 return (err); 3566 } 3567 } 3568 m_head = *m_headp; 3569 3570 pkt_info_zero(&pi); 3571 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG | M_BCAST | M_MCAST)); 3572 pi.ipi_pidx = pidx; 3573 pi.ipi_qsidx = txq->ift_id; 3574 pi.ipi_len = m_head->m_pkthdr.len; 3575 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3576 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3577 3578 /* deliberate bitwise OR to make one condition */ 3579 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3580 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3581 DBG_COUNTER_INC(encap_txd_encap_fail); 3582 return (err); 3583 } 3584 m_head = *m_headp; 3585 } 3586 3587 retry: 3588 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3589 BUS_DMA_NOWAIT); 3590 defrag: 3591 if (__predict_false(err)) { 3592 switch (err) { 3593 case EFBIG: 3594 /* try collapse once and defrag once */ 3595 if (remap == 0) { 3596 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3597 /* try defrag if collapsing fails */ 3598 if (m_head == NULL) 3599 remap++; 3600 } 3601 if (remap == 1) { 3602 txq->ift_mbuf_defrag++; 3603 m_head = m_defrag(*m_headp, M_NOWAIT); 3604 } 3605 /* 3606 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3607 * failed to map an mbuf that was run through m_defrag 3608 */ 3609 MPASS(remap <= 1); 3610 if (__predict_false(m_head == NULL || remap > 1)) 3611 goto defrag_failed; 3612 remap++; 3613 *m_headp = m_head; 3614 goto retry; 3615 break; 3616 case ENOMEM: 3617 txq->ift_no_tx_dma_setup++; 3618 break; 3619 default: 3620 txq->ift_no_tx_dma_setup++; 3621 m_freem(*m_headp); 3622 DBG_COUNTER_INC(tx_frees); 3623 *m_headp = NULL; 3624 break; 3625 } 3626 txq->ift_map_failed++; 3627 DBG_COUNTER_INC(encap_load_mbuf_fail); 3628 DBG_COUNTER_INC(encap_txd_encap_fail); 3629 return (err); 3630 } 3631 ifsd_m[pidx] = m_head; 3632 /* 3633 * XXX assumes a 1 to 1 relationship between segments and 3634 * descriptors - this does not hold true on all drivers, e.g. 3635 * cxgb 3636 */ 3637 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3638 txq->ift_no_desc_avail++; 3639 bus_dmamap_unload(buf_tag, map); 3640 DBG_COUNTER_INC(encap_txq_avail_fail); 3641 DBG_COUNTER_INC(encap_txd_encap_fail); 3642 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3643 GROUPTASK_ENQUEUE(&txq->ift_task); 3644 return (ENOBUFS); 3645 } 3646 /* 3647 * On Intel cards we can greatly reduce the number of TX interrupts 3648 * we see by only setting report status on every Nth descriptor. 3649 * However, this also means that the driver will need to keep track 3650 * of the descriptors that RS was set on to check them for the DD bit. 3651 */ 3652 txq->ift_rs_pending += nsegs + 1; 3653 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3654 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3655 pi.ipi_flags |= IPI_TX_INTR; 3656 txq->ift_rs_pending = 0; 3657 } 3658 3659 pi.ipi_segs = segs; 3660 pi.ipi_nsegs = nsegs; 3661 3662 MPASS(pidx >= 0 && pidx < txq->ift_size); 3663 #ifdef PKT_DEBUG 3664 print_pkt(&pi); 3665 #endif 3666 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3667 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3668 DBG_COUNTER_INC(tx_encap); 3669 MPASS(pi.ipi_new_pidx < txq->ift_size); 3670 3671 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3672 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3673 ndesc += txq->ift_size; 3674 txq->ift_gen = 1; 3675 } 3676 /* 3677 * drivers can need as many as 3678 * two sentinels 3679 */ 3680 MPASS(ndesc <= pi.ipi_nsegs + 2); 3681 MPASS(pi.ipi_new_pidx != pidx); 3682 MPASS(ndesc > 0); 3683 txq->ift_in_use += ndesc; 3684 txq->ift_db_pending += ndesc; 3685 3686 /* 3687 * We update the last software descriptor again here because there may 3688 * be a sentinel and/or there may be more mbufs than segments 3689 */ 3690 txq->ift_pidx = pi.ipi_new_pidx; 3691 txq->ift_npending += pi.ipi_ndescs; 3692 } else { 3693 *m_headp = m_head = iflib_remove_mbuf(txq); 3694 if (err == EFBIG) { 3695 txq->ift_txd_encap_efbig++; 3696 if (remap < 2) { 3697 remap = 1; 3698 goto defrag; 3699 } 3700 } 3701 goto defrag_failed; 3702 } 3703 /* 3704 * err can't possibly be non-zero here, so we don't neet to test it 3705 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3706 */ 3707 return (err); 3708 3709 defrag_failed: 3710 txq->ift_mbuf_defrag_failed++; 3711 txq->ift_map_failed++; 3712 m_freem(*m_headp); 3713 DBG_COUNTER_INC(tx_frees); 3714 *m_headp = NULL; 3715 DBG_COUNTER_INC(encap_txd_encap_fail); 3716 return (ENOMEM); 3717 } 3718 3719 static void 3720 iflib_tx_desc_free(iflib_txq_t txq, int n) 3721 { 3722 uint32_t qsize, cidx, mask, gen; 3723 struct mbuf *m, **ifsd_m; 3724 bool do_prefetch; 3725 3726 cidx = txq->ift_cidx; 3727 gen = txq->ift_gen; 3728 qsize = txq->ift_size; 3729 mask = qsize - 1; 3730 ifsd_m = txq->ift_sds.ifsd_m; 3731 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3732 3733 while (n-- > 0) { 3734 if (do_prefetch) { 3735 prefetch(ifsd_m[(cidx + 3) & mask]); 3736 prefetch(ifsd_m[(cidx + 4) & mask]); 3737 } 3738 if ((m = ifsd_m[cidx]) != NULL) { 3739 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3740 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3741 bus_dmamap_sync(txq->ift_tso_buf_tag, 3742 txq->ift_sds.ifsd_tso_map[cidx], 3743 BUS_DMASYNC_POSTWRITE); 3744 bus_dmamap_unload(txq->ift_tso_buf_tag, 3745 txq->ift_sds.ifsd_tso_map[cidx]); 3746 } else { 3747 bus_dmamap_sync(txq->ift_buf_tag, 3748 txq->ift_sds.ifsd_map[cidx], 3749 BUS_DMASYNC_POSTWRITE); 3750 bus_dmamap_unload(txq->ift_buf_tag, 3751 txq->ift_sds.ifsd_map[cidx]); 3752 } 3753 /* XXX we don't support any drivers that batch packets yet */ 3754 MPASS(m->m_nextpkt == NULL); 3755 m_freem(m); 3756 ifsd_m[cidx] = NULL; 3757 #if MEMORY_LOGGING 3758 txq->ift_dequeued++; 3759 #endif 3760 DBG_COUNTER_INC(tx_frees); 3761 } 3762 if (__predict_false(++cidx == qsize)) { 3763 cidx = 0; 3764 gen = 0; 3765 } 3766 } 3767 txq->ift_cidx = cidx; 3768 txq->ift_gen = gen; 3769 } 3770 3771 static __inline int 3772 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3773 { 3774 int reclaim; 3775 if_ctx_t ctx = txq->ift_ctx; 3776 3777 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3778 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3779 3780 /* 3781 * Need a rate-limiting check so that this isn't called every time 3782 */ 3783 iflib_tx_credits_update(ctx, txq); 3784 reclaim = DESC_RECLAIMABLE(txq); 3785 3786 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3787 #ifdef INVARIANTS 3788 if (iflib_verbose_debug) { 3789 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __func__, 3790 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3791 reclaim, thresh); 3792 } 3793 #endif 3794 return (0); 3795 } 3796 iflib_tx_desc_free(txq, reclaim); 3797 txq->ift_cleaned += reclaim; 3798 txq->ift_in_use -= reclaim; 3799 3800 return (reclaim); 3801 } 3802 3803 static struct mbuf ** 3804 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3805 { 3806 int next, size; 3807 struct mbuf **items; 3808 3809 size = r->size; 3810 next = (cidx + CACHE_PTR_INCREMENT) & (size - 1); 3811 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3812 3813 prefetch(items[(cidx + offset) & (size - 1)]); 3814 if (remaining > 1) { 3815 prefetch2cachelines(&items[next]); 3816 prefetch2cachelines(items[(cidx + offset + 1) & (size - 1)]); 3817 prefetch2cachelines(items[(cidx + offset + 2) & (size - 1)]); 3818 prefetch2cachelines(items[(cidx + offset + 3) & (size - 1)]); 3819 } 3820 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size - 1)])); 3821 } 3822 3823 static void 3824 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3825 { 3826 3827 ifmp_ring_check_drainage(txq->ift_br, budget); 3828 } 3829 3830 static uint32_t 3831 iflib_txq_can_drain(struct ifmp_ring *r) 3832 { 3833 iflib_txq_t txq = r->cookie; 3834 if_ctx_t ctx = txq->ift_ctx; 3835 3836 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3837 return (1); 3838 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3839 BUS_DMASYNC_POSTREAD); 3840 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3841 false)); 3842 } 3843 3844 static uint32_t 3845 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3846 { 3847 iflib_txq_t txq = r->cookie; 3848 if_ctx_t ctx = txq->ift_ctx; 3849 if_t ifp = ctx->ifc_ifp; 3850 struct mbuf *m, **mp; 3851 int avail, bytes_sent, skipped, count, err, i; 3852 int mcast_sent, pkt_sent, reclaimed; 3853 bool do_prefetch, rang, ring; 3854 3855 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3856 !LINK_ACTIVE(ctx))) { 3857 DBG_COUNTER_INC(txq_drain_notready); 3858 return (0); 3859 } 3860 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3861 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending); 3862 avail = IDXDIFF(pidx, cidx, r->size); 3863 3864 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3865 /* 3866 * The driver is unloading so we need to free all pending packets. 3867 */ 3868 DBG_COUNTER_INC(txq_drain_flushing); 3869 for (i = 0; i < avail; i++) { 3870 if (__predict_true(r->items[(cidx + i) & (r->size - 1)] != (void *)txq)) 3871 m_freem(r->items[(cidx + i) & (r->size - 1)]); 3872 r->items[(cidx + i) & (r->size - 1)] = NULL; 3873 } 3874 return (avail); 3875 } 3876 3877 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3878 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3879 CALLOUT_LOCK(txq); 3880 callout_stop(&txq->ift_timer); 3881 CALLOUT_UNLOCK(txq); 3882 DBG_COUNTER_INC(txq_drain_oactive); 3883 return (0); 3884 } 3885 3886 /* 3887 * If we've reclaimed any packets this queue cannot be hung. 3888 */ 3889 if (reclaimed) 3890 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3891 skipped = mcast_sent = bytes_sent = pkt_sent = 0; 3892 count = MIN(avail, TX_BATCH_SIZE); 3893 #ifdef INVARIANTS 3894 if (iflib_verbose_debug) 3895 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __func__, 3896 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3897 #endif 3898 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3899 err = 0; 3900 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx) + 2; i++) { 3901 int rem = do_prefetch ? count - i : 0; 3902 3903 mp = _ring_peek_one(r, cidx, i, rem); 3904 MPASS(mp != NULL && *mp != NULL); 3905 3906 /* 3907 * Completion interrupts will use the address of the txq 3908 * as a sentinel to enqueue _something_ in order to acquire 3909 * the lock on the mp_ring (there's no direct lock call). 3910 * We obviously whave to check for these sentinel cases 3911 * and skip them. 3912 */ 3913 if (__predict_false(*mp == (struct mbuf *)txq)) { 3914 skipped++; 3915 continue; 3916 } 3917 err = iflib_encap(txq, mp); 3918 if (__predict_false(err)) { 3919 /* no room - bail out */ 3920 if (err == ENOBUFS) 3921 break; 3922 skipped++; 3923 /* we can't send this packet - skip it */ 3924 continue; 3925 } 3926 pkt_sent++; 3927 m = *mp; 3928 DBG_COUNTER_INC(tx_sent); 3929 bytes_sent += m->m_pkthdr.len; 3930 mcast_sent += !!(m->m_flags & M_MCAST); 3931 3932 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))) 3933 break; 3934 ETHER_BPF_MTAP(ifp, m); 3935 rang = iflib_txd_db_check(txq, false); 3936 } 3937 3938 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3939 ring = rang ? false : (iflib_min_tx_latency | err); 3940 iflib_txd_db_check(txq, ring); 3941 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3942 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3943 if (mcast_sent) 3944 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3945 #ifdef INVARIANTS 3946 if (iflib_verbose_debug) 3947 printf("consumed=%d\n", skipped + pkt_sent); 3948 #endif 3949 return (skipped + pkt_sent); 3950 } 3951 3952 static uint32_t 3953 iflib_txq_drain_always(struct ifmp_ring *r) 3954 { 3955 return (1); 3956 } 3957 3958 static uint32_t 3959 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3960 { 3961 int i, avail; 3962 struct mbuf **mp; 3963 iflib_txq_t txq; 3964 3965 txq = r->cookie; 3966 3967 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3968 CALLOUT_LOCK(txq); 3969 callout_stop(&txq->ift_timer); 3970 CALLOUT_UNLOCK(txq); 3971 3972 avail = IDXDIFF(pidx, cidx, r->size); 3973 for (i = 0; i < avail; i++) { 3974 mp = _ring_peek_one(r, cidx, i, avail - i); 3975 if (__predict_false(*mp == (struct mbuf *)txq)) 3976 continue; 3977 m_freem(*mp); 3978 DBG_COUNTER_INC(tx_frees); 3979 } 3980 MPASS(ifmp_ring_is_stalled(r) == 0); 3981 return (avail); 3982 } 3983 3984 static void 3985 iflib_ifmp_purge(iflib_txq_t txq) 3986 { 3987 struct ifmp_ring *r; 3988 3989 r = txq->ift_br; 3990 r->drain = iflib_txq_drain_free; 3991 r->can_drain = iflib_txq_drain_always; 3992 3993 ifmp_ring_check_drainage(r, r->size); 3994 3995 r->drain = iflib_txq_drain; 3996 r->can_drain = iflib_txq_can_drain; 3997 } 3998 3999 static void 4000 _task_fn_tx(void *context) 4001 { 4002 iflib_txq_t txq = context; 4003 if_ctx_t ctx = txq->ift_ctx; 4004 if_t ifp = ctx->ifc_ifp; 4005 int abdicate = ctx->ifc_sysctl_tx_abdicate; 4006 4007 #ifdef IFLIB_DIAGNOSTICS 4008 txq->ift_cpu_exec_count[curcpu]++; 4009 #endif 4010 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4011 return; 4012 #ifdef DEV_NETMAP 4013 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 4014 netmap_tx_irq(ifp, txq->ift_id)) 4015 goto skip_ifmp; 4016 #endif 4017 #ifdef ALTQ 4018 if (if_altq_is_enabled(ifp)) 4019 iflib_altq_if_start(ifp); 4020 #endif 4021 if (txq->ift_db_pending) 4022 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 4023 else if (!abdicate) 4024 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4025 /* 4026 * When abdicating, we always need to check drainage, not just when we don't enqueue 4027 */ 4028 if (abdicate) 4029 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4030 #ifdef DEV_NETMAP 4031 skip_ifmp: 4032 #endif 4033 if (ctx->ifc_flags & IFC_LEGACY) 4034 IFDI_INTR_ENABLE(ctx); 4035 else 4036 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 4037 } 4038 4039 static void 4040 _task_fn_rx(void *context) 4041 { 4042 iflib_rxq_t rxq = context; 4043 if_ctx_t ctx = rxq->ifr_ctx; 4044 uint8_t more; 4045 uint16_t budget; 4046 #ifdef DEV_NETMAP 4047 u_int work = 0; 4048 int nmirq; 4049 #endif 4050 4051 #ifdef IFLIB_DIAGNOSTICS 4052 rxq->ifr_cpu_exec_count[curcpu]++; 4053 #endif 4054 DBG_COUNTER_INC(task_fn_rxs); 4055 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4056 return; 4057 #ifdef DEV_NETMAP 4058 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 4059 if (nmirq != NM_IRQ_PASS) { 4060 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 4061 goto skip_rxeof; 4062 } 4063 #endif 4064 budget = ctx->ifc_sysctl_rx_budget; 4065 if (budget == 0) 4066 budget = 16; /* XXX */ 4067 more = iflib_rxeof(rxq, budget); 4068 #ifdef DEV_NETMAP 4069 skip_rxeof: 4070 #endif 4071 if ((more & IFLIB_RXEOF_MORE) == 0) { 4072 if (ctx->ifc_flags & IFC_LEGACY) 4073 IFDI_INTR_ENABLE(ctx); 4074 else 4075 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 4076 DBG_COUNTER_INC(rx_intr_enables); 4077 } 4078 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4079 return; 4080 4081 if (more & IFLIB_RXEOF_MORE) 4082 GROUPTASK_ENQUEUE(&rxq->ifr_task); 4083 else if (more & IFLIB_RXEOF_EMPTY) 4084 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 4085 } 4086 4087 static void 4088 _task_fn_admin(void *context, int pending) 4089 { 4090 if_ctx_t ctx = context; 4091 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 4092 iflib_txq_t txq; 4093 int i; 4094 bool oactive, running, do_reset, do_watchdog, in_detach; 4095 4096 STATE_LOCK(ctx); 4097 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 4098 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 4099 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 4100 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 4101 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 4102 ctx->ifc_flags &= ~(IFC_DO_RESET | IFC_DO_WATCHDOG); 4103 STATE_UNLOCK(ctx); 4104 4105 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4106 return; 4107 if (in_detach) 4108 return; 4109 4110 CTX_LOCK(ctx); 4111 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4112 CALLOUT_LOCK(txq); 4113 callout_stop(&txq->ift_timer); 4114 CALLOUT_UNLOCK(txq); 4115 } 4116 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ) 4117 IFDI_ADMIN_COMPLETION_HANDLE(ctx); 4118 if (do_watchdog) { 4119 ctx->ifc_watchdog_events++; 4120 IFDI_WATCHDOG_RESET(ctx); 4121 } 4122 IFDI_UPDATE_ADMIN_STATUS(ctx); 4123 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4124 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 4125 txq->ift_timer.c_cpu); 4126 } 4127 IFDI_LINK_INTR_ENABLE(ctx); 4128 if (do_reset) 4129 iflib_if_init_locked(ctx); 4130 CTX_UNLOCK(ctx); 4131 4132 if (LINK_ACTIVE(ctx) == 0) 4133 return; 4134 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 4135 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4136 } 4137 4138 static void 4139 _task_fn_iov(void *context, int pending) 4140 { 4141 if_ctx_t ctx = context; 4142 4143 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 4144 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4145 return; 4146 4147 CTX_LOCK(ctx); 4148 IFDI_VFLR_HANDLE(ctx); 4149 CTX_UNLOCK(ctx); 4150 } 4151 4152 static int 4153 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4154 { 4155 int err; 4156 if_int_delay_info_t info; 4157 if_ctx_t ctx; 4158 4159 info = (if_int_delay_info_t)arg1; 4160 ctx = info->iidi_ctx; 4161 info->iidi_req = req; 4162 info->iidi_oidp = oidp; 4163 CTX_LOCK(ctx); 4164 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 4165 CTX_UNLOCK(ctx); 4166 return (err); 4167 } 4168 4169 /********************************************************************* 4170 * 4171 * IFNET FUNCTIONS 4172 * 4173 **********************************************************************/ 4174 4175 static void 4176 iflib_if_init_locked(if_ctx_t ctx) 4177 { 4178 iflib_stop(ctx); 4179 iflib_init_locked(ctx); 4180 } 4181 4182 static void 4183 iflib_if_init(void *arg) 4184 { 4185 if_ctx_t ctx = arg; 4186 4187 CTX_LOCK(ctx); 4188 iflib_if_init_locked(ctx); 4189 CTX_UNLOCK(ctx); 4190 } 4191 4192 static int 4193 iflib_if_transmit(if_t ifp, struct mbuf *m) 4194 { 4195 if_ctx_t ctx = if_getsoftc(ifp); 4196 iflib_txq_t txq; 4197 int err, qidx; 4198 int abdicate; 4199 4200 if (__predict_false((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 4201 DBG_COUNTER_INC(tx_frees); 4202 m_freem(m); 4203 return (ENETDOWN); 4204 } 4205 4206 MPASS(m->m_nextpkt == NULL); 4207 /* ALTQ-enabled interfaces always use queue 0. */ 4208 qidx = 0; 4209 /* Use driver-supplied queue selection method if it exists */ 4210 if (ctx->isc_txq_select_v2) { 4211 struct if_pkt_info pi; 4212 uint64_t early_pullups = 0; 4213 pkt_info_zero(&pi); 4214 4215 err = iflib_parse_header_partial(&pi, &m, &early_pullups); 4216 if (__predict_false(err != 0)) { 4217 /* Assign pullups for bad pkts to default queue */ 4218 ctx->ifc_txqs[0].ift_pullups += early_pullups; 4219 DBG_COUNTER_INC(encap_txd_encap_fail); 4220 return (err); 4221 } 4222 /* Let driver make queueing decision */ 4223 qidx = ctx->isc_txq_select_v2(ctx->ifc_softc, m, &pi); 4224 ctx->ifc_txqs[qidx].ift_pullups += early_pullups; 4225 } 4226 /* Backwards compatibility w/ simpler queue select */ 4227 else if (ctx->isc_txq_select) 4228 qidx = ctx->isc_txq_select(ctx->ifc_softc, m); 4229 /* If not, use iflib's standard method */ 4230 else if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !if_altq_is_enabled(ifp)) 4231 qidx = QIDX(ctx, m); 4232 4233 /* Set TX queue */ 4234 txq = &ctx->ifc_txqs[qidx]; 4235 4236 #ifdef DRIVER_BACKPRESSURE 4237 if (txq->ift_closed) { 4238 while (m != NULL) { 4239 next = m->m_nextpkt; 4240 m->m_nextpkt = NULL; 4241 m_freem(m); 4242 DBG_COUNTER_INC(tx_frees); 4243 m = next; 4244 } 4245 return (ENOBUFS); 4246 } 4247 #endif 4248 #ifdef notyet 4249 qidx = count = 0; 4250 mp = marr; 4251 next = m; 4252 do { 4253 count++; 4254 next = next->m_nextpkt; 4255 } while (next != NULL); 4256 4257 if (count > nitems(marr)) 4258 if ((mp = malloc(count * sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4259 /* XXX check nextpkt */ 4260 m_freem(m); 4261 /* XXX simplify for now */ 4262 DBG_COUNTER_INC(tx_frees); 4263 return (ENOBUFS); 4264 } 4265 for (next = m, i = 0; next != NULL; i++) { 4266 mp[i] = next; 4267 next = next->m_nextpkt; 4268 mp[i]->m_nextpkt = NULL; 4269 } 4270 #endif 4271 DBG_COUNTER_INC(tx_seen); 4272 abdicate = ctx->ifc_sysctl_tx_abdicate; 4273 4274 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4275 4276 if (abdicate) 4277 GROUPTASK_ENQUEUE(&txq->ift_task); 4278 if (err) { 4279 if (!abdicate) 4280 GROUPTASK_ENQUEUE(&txq->ift_task); 4281 /* support forthcoming later */ 4282 #ifdef DRIVER_BACKPRESSURE 4283 txq->ift_closed = TRUE; 4284 #endif 4285 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4286 m_freem(m); 4287 DBG_COUNTER_INC(tx_frees); 4288 } 4289 4290 return (err); 4291 } 4292 4293 #ifdef ALTQ 4294 /* 4295 * The overall approach to integrating iflib with ALTQ is to continue to use 4296 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4297 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4298 * is redundant/unnecessary, but doing so minimizes the amount of 4299 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4300 * redundantly queueing to an intermediate mp_ring is swamped by the 4301 * performance limitations inherent in using ALTQ. 4302 * 4303 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4304 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4305 * given interface. If ALTQ is enabled for an interface, then all 4306 * transmitted packets for that interface will be submitted to the ALTQ 4307 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4308 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4309 * update stats that the iflib machinery handles, and which is sensitve to 4310 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4311 * will be installed as the start routine for use by ALTQ facilities that 4312 * need to trigger queue drains on a scheduled basis. 4313 * 4314 */ 4315 static void 4316 iflib_altq_if_start(if_t ifp) 4317 { 4318 struct ifaltq *ifq = &ifp->if_snd; /* XXX - DRVAPI */ 4319 struct mbuf *m; 4320 4321 IFQ_LOCK(ifq); 4322 IFQ_DEQUEUE_NOLOCK(ifq, m); 4323 while (m != NULL) { 4324 iflib_if_transmit(ifp, m); 4325 IFQ_DEQUEUE_NOLOCK(ifq, m); 4326 } 4327 IFQ_UNLOCK(ifq); 4328 } 4329 4330 static int 4331 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4332 { 4333 int err; 4334 4335 if (if_altq_is_enabled(ifp)) { 4336 IFQ_ENQUEUE(&ifp->if_snd, m, err); /* XXX - DRVAPI */ 4337 if (err == 0) 4338 iflib_altq_if_start(ifp); 4339 } else 4340 err = iflib_if_transmit(ifp, m); 4341 4342 return (err); 4343 } 4344 #endif /* ALTQ */ 4345 4346 static void 4347 iflib_if_qflush(if_t ifp) 4348 { 4349 if_ctx_t ctx = if_getsoftc(ifp); 4350 iflib_txq_t txq = ctx->ifc_txqs; 4351 int i; 4352 4353 STATE_LOCK(ctx); 4354 ctx->ifc_flags |= IFC_QFLUSH; 4355 STATE_UNLOCK(ctx); 4356 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4357 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4358 iflib_txq_check_drain(txq, 0); 4359 STATE_LOCK(ctx); 4360 ctx->ifc_flags &= ~IFC_QFLUSH; 4361 STATE_UNLOCK(ctx); 4362 4363 /* 4364 * When ALTQ is enabled, this will also take care of purging the 4365 * ALTQ queue(s). 4366 */ 4367 if_qflush(ifp); 4368 } 4369 4370 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4371 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4372 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4373 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG) 4374 4375 static int 4376 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4377 { 4378 if_ctx_t ctx = if_getsoftc(ifp); 4379 struct ifreq *ifr = (struct ifreq *)data; 4380 #if defined(INET) || defined(INET6) 4381 struct ifaddr *ifa = (struct ifaddr *)data; 4382 #endif 4383 bool avoid_reset = false; 4384 int err = 0, reinit = 0, bits; 4385 4386 switch (command) { 4387 case SIOCSIFADDR: 4388 #ifdef INET 4389 if (ifa->ifa_addr->sa_family == AF_INET) 4390 avoid_reset = true; 4391 #endif 4392 #ifdef INET6 4393 if (ifa->ifa_addr->sa_family == AF_INET6) 4394 avoid_reset = true; 4395 #endif 4396 /* 4397 * Calling init results in link renegotiation, 4398 * so we avoid doing it when possible. 4399 */ 4400 if (avoid_reset) { 4401 if_setflagbits(ifp, IFF_UP, 0); 4402 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4403 reinit = 1; 4404 #ifdef INET 4405 if (!(if_getflags(ifp) & IFF_NOARP)) 4406 arp_ifinit(ifp, ifa); 4407 #endif 4408 } else 4409 err = ether_ioctl(ifp, command, data); 4410 break; 4411 case SIOCSIFMTU: 4412 CTX_LOCK(ctx); 4413 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4414 CTX_UNLOCK(ctx); 4415 break; 4416 } 4417 bits = if_getdrvflags(ifp); 4418 /* stop the driver and free any clusters before proceeding */ 4419 iflib_stop(ctx); 4420 4421 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4422 STATE_LOCK(ctx); 4423 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4424 ctx->ifc_flags |= IFC_MULTISEG; 4425 else 4426 ctx->ifc_flags &= ~IFC_MULTISEG; 4427 STATE_UNLOCK(ctx); 4428 err = if_setmtu(ifp, ifr->ifr_mtu); 4429 } 4430 iflib_init_locked(ctx); 4431 STATE_LOCK(ctx); 4432 if_setdrvflags(ifp, bits); 4433 STATE_UNLOCK(ctx); 4434 CTX_UNLOCK(ctx); 4435 break; 4436 case SIOCSIFFLAGS: 4437 CTX_LOCK(ctx); 4438 if (if_getflags(ifp) & IFF_UP) { 4439 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4440 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4441 (IFF_PROMISC | IFF_ALLMULTI)) { 4442 CTX_UNLOCK(ctx); 4443 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4444 CTX_LOCK(ctx); 4445 } 4446 } else 4447 reinit = 1; 4448 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4449 iflib_stop(ctx); 4450 } 4451 ctx->ifc_if_flags = if_getflags(ifp); 4452 CTX_UNLOCK(ctx); 4453 break; 4454 case SIOCADDMULTI: 4455 case SIOCDELMULTI: 4456 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4457 CTX_LOCK(ctx); 4458 IFDI_INTR_DISABLE(ctx); 4459 IFDI_MULTI_SET(ctx); 4460 IFDI_INTR_ENABLE(ctx); 4461 CTX_UNLOCK(ctx); 4462 } 4463 break; 4464 case SIOCSIFMEDIA: 4465 CTX_LOCK(ctx); 4466 IFDI_MEDIA_SET(ctx); 4467 CTX_UNLOCK(ctx); 4468 /* FALLTHROUGH */ 4469 case SIOCGIFMEDIA: 4470 case SIOCGIFXMEDIA: 4471 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4472 break; 4473 case SIOCGI2C: 4474 { 4475 struct ifi2creq i2c; 4476 4477 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4478 if (err != 0) 4479 break; 4480 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4481 err = EINVAL; 4482 break; 4483 } 4484 if (i2c.len > sizeof(i2c.data)) { 4485 err = EINVAL; 4486 break; 4487 } 4488 4489 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4490 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4491 sizeof(i2c)); 4492 break; 4493 } 4494 case SIOCSIFCAP: 4495 { 4496 int mask, setmask, oldmask; 4497 4498 oldmask = if_getcapenable(ifp); 4499 mask = ifr->ifr_reqcap ^ oldmask; 4500 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG; 4501 setmask = 0; 4502 #ifdef TCP_OFFLOAD 4503 setmask |= mask & (IFCAP_TOE4 | IFCAP_TOE6); 4504 #endif 4505 setmask |= (mask & IFCAP_FLAGS); 4506 setmask |= (mask & IFCAP_WOL); 4507 4508 /* 4509 * If any RX csum has changed, change all the ones that 4510 * are supported by the driver. 4511 */ 4512 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4513 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4514 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4515 } 4516 4517 /* 4518 * want to ensure that traffic has stopped before we change any of the flags 4519 */ 4520 if (setmask) { 4521 CTX_LOCK(ctx); 4522 bits = if_getdrvflags(ifp); 4523 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4524 iflib_stop(ctx); 4525 STATE_LOCK(ctx); 4526 if_togglecapenable(ifp, setmask); 4527 ctx->ifc_softc_ctx.isc_capenable ^= setmask; 4528 STATE_UNLOCK(ctx); 4529 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4530 iflib_init_locked(ctx); 4531 STATE_LOCK(ctx); 4532 if_setdrvflags(ifp, bits); 4533 STATE_UNLOCK(ctx); 4534 CTX_UNLOCK(ctx); 4535 } 4536 if_vlancap(ifp); 4537 break; 4538 } 4539 case SIOCGPRIVATE_0: 4540 case SIOCSDRVSPEC: 4541 case SIOCGDRVSPEC: 4542 CTX_LOCK(ctx); 4543 err = IFDI_PRIV_IOCTL(ctx, command, data); 4544 CTX_UNLOCK(ctx); 4545 break; 4546 default: 4547 err = ether_ioctl(ifp, command, data); 4548 break; 4549 } 4550 if (reinit) 4551 iflib_if_init(ctx); 4552 return (err); 4553 } 4554 4555 static uint64_t 4556 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4557 { 4558 if_ctx_t ctx = if_getsoftc(ifp); 4559 4560 return (IFDI_GET_COUNTER(ctx, cnt)); 4561 } 4562 4563 /********************************************************************* 4564 * 4565 * OTHER FUNCTIONS EXPORTED TO THE STACK 4566 * 4567 **********************************************************************/ 4568 4569 static void 4570 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4571 { 4572 if_ctx_t ctx = if_getsoftc(ifp); 4573 4574 if ((void *)ctx != arg) 4575 return; 4576 4577 if ((vtag == 0) || (vtag > 4095)) 4578 return; 4579 4580 if (iflib_in_detach(ctx)) 4581 return; 4582 4583 CTX_LOCK(ctx); 4584 /* Driver may need all untagged packets to be flushed */ 4585 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4586 iflib_stop(ctx); 4587 IFDI_VLAN_REGISTER(ctx, vtag); 4588 /* Re-init to load the changes, if required */ 4589 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4590 iflib_init_locked(ctx); 4591 CTX_UNLOCK(ctx); 4592 } 4593 4594 static void 4595 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4596 { 4597 if_ctx_t ctx = if_getsoftc(ifp); 4598 4599 if ((void *)ctx != arg) 4600 return; 4601 4602 if ((vtag == 0) || (vtag > 4095)) 4603 return; 4604 4605 CTX_LOCK(ctx); 4606 /* Driver may need all tagged packets to be flushed */ 4607 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4608 iflib_stop(ctx); 4609 IFDI_VLAN_UNREGISTER(ctx, vtag); 4610 /* Re-init to load the changes, if required */ 4611 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4612 iflib_init_locked(ctx); 4613 CTX_UNLOCK(ctx); 4614 } 4615 4616 static void 4617 iflib_led_func(void *arg, int onoff) 4618 { 4619 if_ctx_t ctx = arg; 4620 4621 CTX_LOCK(ctx); 4622 IFDI_LED_FUNC(ctx, onoff); 4623 CTX_UNLOCK(ctx); 4624 } 4625 4626 /********************************************************************* 4627 * 4628 * BUS FUNCTION DEFINITIONS 4629 * 4630 **********************************************************************/ 4631 4632 int 4633 iflib_device_probe(device_t dev) 4634 { 4635 const pci_vendor_info_t *ent; 4636 if_shared_ctx_t sctx; 4637 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4638 uint16_t pci_vendor_id; 4639 4640 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4641 return (ENOTSUP); 4642 4643 pci_vendor_id = pci_get_vendor(dev); 4644 pci_device_id = pci_get_device(dev); 4645 pci_subvendor_id = pci_get_subvendor(dev); 4646 pci_subdevice_id = pci_get_subdevice(dev); 4647 pci_rev_id = pci_get_revid(dev); 4648 if (sctx->isc_parse_devinfo != NULL) 4649 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4650 4651 ent = sctx->isc_vendor_info; 4652 while (ent->pvi_vendor_id != 0) { 4653 if (pci_vendor_id != ent->pvi_vendor_id) { 4654 ent++; 4655 continue; 4656 } 4657 if ((pci_device_id == ent->pvi_device_id) && 4658 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4659 (ent->pvi_subvendor_id == 0)) && 4660 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4661 (ent->pvi_subdevice_id == 0)) && 4662 ((pci_rev_id == ent->pvi_rev_id) || 4663 (ent->pvi_rev_id == 0))) { 4664 device_set_desc_copy(dev, ent->pvi_name); 4665 /* this needs to be changed to zero if the bus probing code 4666 * ever stops re-probing on best match because the sctx 4667 * may have its values over written by register calls 4668 * in subsequent probes 4669 */ 4670 return (BUS_PROBE_DEFAULT); 4671 } 4672 ent++; 4673 } 4674 return (ENXIO); 4675 } 4676 4677 int 4678 iflib_device_probe_vendor(device_t dev) 4679 { 4680 int probe; 4681 4682 probe = iflib_device_probe(dev); 4683 if (probe == BUS_PROBE_DEFAULT) 4684 return (BUS_PROBE_VENDOR); 4685 else 4686 return (probe); 4687 } 4688 4689 static void 4690 iflib_reset_qvalues(if_ctx_t ctx) 4691 { 4692 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4693 if_shared_ctx_t sctx = ctx->ifc_sctx; 4694 device_t dev = ctx->ifc_dev; 4695 int i; 4696 4697 if (ctx->ifc_sysctl_ntxqs != 0) 4698 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4699 if (ctx->ifc_sysctl_nrxqs != 0) 4700 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4701 4702 for (i = 0; i < sctx->isc_ntxqs; i++) { 4703 if (ctx->ifc_sysctl_ntxds[i] != 0) 4704 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4705 else 4706 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4707 } 4708 4709 for (i = 0; i < sctx->isc_nrxqs; i++) { 4710 if (ctx->ifc_sysctl_nrxds[i] != 0) 4711 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4712 else 4713 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4714 } 4715 4716 for (i = 0; i < sctx->isc_nrxqs; i++) { 4717 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4718 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4719 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4720 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4721 } 4722 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4723 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4724 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4725 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4726 } 4727 if (!powerof2(scctx->isc_nrxd[i])) { 4728 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4729 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4730 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4731 } 4732 } 4733 4734 for (i = 0; i < sctx->isc_ntxqs; i++) { 4735 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4736 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4737 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4738 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4739 } 4740 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4741 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4742 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4743 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4744 } 4745 if (!powerof2(scctx->isc_ntxd[i])) { 4746 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4747 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4748 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4749 } 4750 } 4751 } 4752 4753 static void 4754 iflib_add_pfil(if_ctx_t ctx) 4755 { 4756 struct pfil_head *pfil; 4757 struct pfil_head_args pa; 4758 iflib_rxq_t rxq; 4759 int i; 4760 4761 pa.pa_version = PFIL_VERSION; 4762 pa.pa_flags = PFIL_IN; 4763 pa.pa_type = PFIL_TYPE_ETHERNET; 4764 pa.pa_headname = if_name(ctx->ifc_ifp); 4765 pfil = pfil_head_register(&pa); 4766 4767 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4768 rxq->pfil = pfil; 4769 } 4770 } 4771 4772 static void 4773 iflib_rem_pfil(if_ctx_t ctx) 4774 { 4775 struct pfil_head *pfil; 4776 iflib_rxq_t rxq; 4777 int i; 4778 4779 rxq = ctx->ifc_rxqs; 4780 pfil = rxq->pfil; 4781 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4782 rxq->pfil = NULL; 4783 } 4784 pfil_head_unregister(pfil); 4785 } 4786 4787 4788 /* 4789 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from 4790 * cpuid and wrapping as necessary. 4791 */ 4792 static unsigned int 4793 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n) 4794 { 4795 unsigned int first_valid; 4796 unsigned int last_valid; 4797 4798 /* cpuid should always be in the valid set */ 4799 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4800 4801 /* valid set should never be empty */ 4802 MPASS(!CPU_EMPTY(&ctx->ifc_cpus)); 4803 4804 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4805 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4806 n = n % CPU_COUNT(&ctx->ifc_cpus); 4807 while (n > 0) { 4808 do { 4809 cpuid++; 4810 if (cpuid > last_valid) 4811 cpuid = first_valid; 4812 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4813 n--; 4814 } 4815 4816 return (cpuid); 4817 } 4818 4819 #if defined(SMP) && defined(SCHED_ULE) 4820 extern struct cpu_group *cpu_top; /* CPU topology */ 4821 4822 static int 4823 find_child_with_core(int cpu, struct cpu_group *grp) 4824 { 4825 int i; 4826 4827 if (grp->cg_children == 0) 4828 return (-1); 4829 4830 MPASS(grp->cg_child); 4831 for (i = 0; i < grp->cg_children; i++) { 4832 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 4833 return (i); 4834 } 4835 4836 return (-1); 4837 } 4838 4839 4840 /* 4841 * Find an L2 neighbor of the given CPU or return -1 if none found. This 4842 * does not distinguish among multiple L2 neighbors if the given CPU has 4843 * more than one (it will always return the same result in that case). 4844 */ 4845 static int 4846 find_l2_neighbor(int cpu) 4847 { 4848 struct cpu_group *grp; 4849 int i; 4850 4851 grp = cpu_top; 4852 if (grp == NULL) 4853 return (-1); 4854 4855 /* 4856 * Find the smallest CPU group that contains the given core. 4857 */ 4858 i = 0; 4859 while ((i = find_child_with_core(cpu, grp)) != -1) { 4860 /* 4861 * If the smallest group containing the given CPU has less 4862 * than two members, we conclude the given CPU has no 4863 * L2 neighbor. 4864 */ 4865 if (grp->cg_child[i].cg_count <= 1) 4866 return (-1); 4867 grp = &grp->cg_child[i]; 4868 } 4869 4870 /* Must share L2. */ 4871 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 4872 return (-1); 4873 4874 /* 4875 * Select the first member of the set that isn't the reference 4876 * CPU, which at this point is guaranteed to exist. 4877 */ 4878 for (i = 0; i < CPU_SETSIZE; i++) { 4879 if (CPU_ISSET(i, &grp->cg_mask) && i != cpu) 4880 return (i); 4881 } 4882 4883 /* Should never be reached */ 4884 return (-1); 4885 } 4886 4887 #else 4888 static int 4889 find_l2_neighbor(int cpu) 4890 { 4891 4892 return (-1); 4893 } 4894 #endif 4895 4896 /* 4897 * CPU mapping behaviors 4898 * --------------------- 4899 * 'separate txrx' refers to the separate_txrx sysctl 4900 * 'use logical' refers to the use_logical_cores sysctl 4901 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded 4902 * 4903 * separate use INTR 4904 * txrx logical CPUS result 4905 * ---------- --------- ------ ------------------------------------------------ 4906 * - - X RX and TX queues mapped to consecutive physical 4907 * cores with RX/TX pairs on same core and excess 4908 * of either following 4909 * - X X RX and TX queues mapped to consecutive cores 4910 * of any type with RX/TX pairs on same core and 4911 * excess of either following 4912 * X - X RX and TX queues mapped to consecutive physical 4913 * cores; all RX then all TX 4914 * X X X RX queues mapped to consecutive physical cores 4915 * first, then TX queues mapped to L2 neighbor of 4916 * the corresponding RX queue if one exists, 4917 * otherwise to consecutive physical cores 4918 * - n/a - RX and TX queues mapped to consecutive cores of 4919 * any type with RX/TX pairs on same core and excess 4920 * of either following 4921 * X n/a - RX and TX queues mapped to consecutive cores of 4922 * any type; all RX then all TX 4923 */ 4924 static unsigned int 4925 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid, 4926 bool is_tx) 4927 { 4928 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4929 unsigned int core_index; 4930 4931 if (ctx->ifc_sysctl_separate_txrx) { 4932 /* 4933 * When using separate CPUs for TX and RX, the assignment 4934 * will always be of a consecutive CPU out of the set of 4935 * context CPUs, except for the specific case where the 4936 * context CPUs are phsyical cores, the use of logical cores 4937 * has been enabled, the assignment is for TX, the TX qid 4938 * corresponds to an RX qid, and the CPU assigned to the 4939 * corresponding RX queue has an L2 neighbor. 4940 */ 4941 if (ctx->ifc_sysctl_use_logical_cores && 4942 ctx->ifc_cpus_are_physical_cores && 4943 is_tx && qid < scctx->isc_nrxqsets) { 4944 int l2_neighbor; 4945 unsigned int rx_cpuid; 4946 4947 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid); 4948 l2_neighbor = find_l2_neighbor(rx_cpuid); 4949 if (l2_neighbor != -1) { 4950 return (l2_neighbor); 4951 } 4952 /* 4953 * ... else fall through to the normal 4954 * consecutive-after-RX assignment scheme. 4955 * 4956 * Note that we are assuming that all RX queue CPUs 4957 * have an L2 neighbor, or all do not. If a mixed 4958 * scenario is possible, we will have to keep track 4959 * separately of how many queues prior to this one 4960 * were not able to be assigned to an L2 neighbor. 4961 */ 4962 } 4963 if (is_tx) 4964 core_index = scctx->isc_nrxqsets + qid; 4965 else 4966 core_index = qid; 4967 } else { 4968 core_index = qid; 4969 } 4970 4971 return (cpuid_advance(ctx, base_cpuid, core_index)); 4972 } 4973 4974 static uint16_t 4975 get_ctx_core_offset(if_ctx_t ctx) 4976 { 4977 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4978 struct cpu_offset *op; 4979 cpuset_t assigned_cpus; 4980 unsigned int cores_consumed; 4981 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset; 4982 unsigned int first_valid; 4983 unsigned int last_valid; 4984 unsigned int i; 4985 4986 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4987 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4988 4989 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) { 4990 /* 4991 * Align the user-chosen base CPU ID to the next valid CPU 4992 * for this device. If the chosen base CPU ID is smaller 4993 * than the first valid CPU or larger than the last valid 4994 * CPU, we assume the user does not know what the valid 4995 * range is for this device and is thinking in terms of a 4996 * zero-based reference frame, and so we shift the given 4997 * value into the valid range (and wrap accordingly) so the 4998 * intent is translated to the proper frame of reference. 4999 * If the base CPU ID is within the valid first/last, but 5000 * does not correspond to a valid CPU, it is advanced to the 5001 * next valid CPU (wrapping if necessary). 5002 */ 5003 if (base_cpuid < first_valid || base_cpuid > last_valid) { 5004 /* shift from zero-based to first_valid-based */ 5005 base_cpuid += first_valid; 5006 /* wrap to range [first_valid, last_valid] */ 5007 base_cpuid = (base_cpuid - first_valid) % 5008 (last_valid - first_valid + 1); 5009 } 5010 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) { 5011 /* 5012 * base_cpuid is in [first_valid, last_valid], but 5013 * not a member of the valid set. In this case, 5014 * there will always be a member of the valid set 5015 * with a CPU ID that is greater than base_cpuid, 5016 * and we simply advance to it. 5017 */ 5018 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) 5019 base_cpuid++; 5020 } 5021 return (base_cpuid); 5022 } 5023 5024 /* 5025 * Determine how many cores will be consumed by performing the CPU 5026 * assignments and counting how many of the assigned CPUs correspond 5027 * to CPUs in the set of context CPUs. This is done using the CPU 5028 * ID first_valid as the base CPU ID, as the base CPU must be within 5029 * the set of context CPUs. 5030 * 5031 * Note not all assigned CPUs will be in the set of context CPUs 5032 * when separate CPUs are being allocated to TX and RX queues, 5033 * assignment to logical cores has been enabled, the set of context 5034 * CPUs contains only physical CPUs, and TX queues are mapped to L2 5035 * neighbors of CPUs that RX queues have been mapped to - in this 5036 * case we do only want to count how many CPUs in the set of context 5037 * CPUs have been consumed, as that determines the next CPU in that 5038 * set to start allocating at for the next device for which 5039 * core_offset is not set. 5040 */ 5041 CPU_ZERO(&assigned_cpus); 5042 for (i = 0; i < scctx->isc_ntxqsets; i++) 5043 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true), 5044 &assigned_cpus); 5045 for (i = 0; i < scctx->isc_nrxqsets; i++) 5046 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false), 5047 &assigned_cpus); 5048 CPU_AND(&assigned_cpus, &assigned_cpus, &ctx->ifc_cpus); 5049 cores_consumed = CPU_COUNT(&assigned_cpus); 5050 5051 mtx_lock(&cpu_offset_mtx); 5052 SLIST_FOREACH(op, &cpu_offsets, entries) { 5053 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5054 base_cpuid = op->next_cpuid; 5055 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid, 5056 cores_consumed); 5057 MPASS(op->refcount < UINT_MAX); 5058 op->refcount++; 5059 break; 5060 } 5061 } 5062 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) { 5063 base_cpuid = first_valid; 5064 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 5065 M_NOWAIT | M_ZERO); 5066 if (op == NULL) { 5067 device_printf(ctx->ifc_dev, 5068 "allocation for cpu offset failed.\n"); 5069 } else { 5070 op->next_cpuid = cpuid_advance(ctx, base_cpuid, 5071 cores_consumed); 5072 op->refcount = 1; 5073 CPU_COPY(&ctx->ifc_cpus, &op->set); 5074 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 5075 } 5076 } 5077 mtx_unlock(&cpu_offset_mtx); 5078 5079 return (base_cpuid); 5080 } 5081 5082 static void 5083 unref_ctx_core_offset(if_ctx_t ctx) 5084 { 5085 struct cpu_offset *op, *top; 5086 5087 mtx_lock(&cpu_offset_mtx); 5088 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 5089 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5090 MPASS(op->refcount > 0); 5091 op->refcount--; 5092 if (op->refcount == 0) { 5093 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 5094 free(op, M_IFLIB); 5095 } 5096 break; 5097 } 5098 } 5099 mtx_unlock(&cpu_offset_mtx); 5100 } 5101 5102 int 5103 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 5104 { 5105 if_ctx_t ctx; 5106 if_t ifp; 5107 if_softc_ctx_t scctx; 5108 kobjop_desc_t kobj_desc; 5109 kobj_method_t *kobj_method; 5110 int err, msix, rid; 5111 int num_txd, num_rxd; 5112 char namebuf[TASKQUEUE_NAMELEN]; 5113 5114 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK | M_ZERO); 5115 5116 if (sc == NULL) { 5117 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK | M_ZERO); 5118 device_set_softc(dev, ctx); 5119 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5120 } 5121 5122 ctx->ifc_sctx = sctx; 5123 ctx->ifc_dev = dev; 5124 ctx->ifc_softc = sc; 5125 5126 if ((err = iflib_register(ctx)) != 0) { 5127 device_printf(dev, "iflib_register failed %d\n", err); 5128 goto fail_ctx_free; 5129 } 5130 iflib_add_device_sysctl_pre(ctx); 5131 5132 scctx = &ctx->ifc_softc_ctx; 5133 ifp = ctx->ifc_ifp; 5134 5135 iflib_reset_qvalues(ctx); 5136 IFNET_WLOCK(); 5137 CTX_LOCK(ctx); 5138 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5139 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5140 goto fail_unlock; 5141 } 5142 _iflib_pre_assert(scctx); 5143 ctx->ifc_txrx = *scctx->isc_txrx; 5144 5145 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR)); 5146 5147 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 5148 ctx->ifc_mediap = scctx->isc_media; 5149 5150 #ifdef INVARIANTS 5151 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5152 MPASS(scctx->isc_tx_csum_flags); 5153 #endif 5154 5155 if_setcapabilities(ifp, 5156 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG); 5157 if_setcapenable(ifp, 5158 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG); 5159 5160 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5161 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5162 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5163 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5164 5165 num_txd = iflib_num_tx_descs(ctx); 5166 num_rxd = iflib_num_rx_descs(ctx); 5167 5168 /* XXX change for per-queue sizes */ 5169 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5170 num_txd, num_rxd); 5171 5172 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5173 scctx->isc_tx_nsegments = max(1, num_txd / 5174 MAX_SINGLE_PACKET_FRACTION); 5175 if (scctx->isc_tx_tso_segments_max > num_txd / 5176 MAX_SINGLE_PACKET_FRACTION) 5177 scctx->isc_tx_tso_segments_max = max(1, 5178 num_txd / MAX_SINGLE_PACKET_FRACTION); 5179 5180 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5181 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5182 /* 5183 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5184 * but some MACs do. 5185 */ 5186 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5187 IP_MAXPACKET)); 5188 /* 5189 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5190 * into account. In the worst case, each of these calls will 5191 * add another mbuf and, thus, the requirement for another DMA 5192 * segment. So for best performance, it doesn't make sense to 5193 * advertize a maximum of TSO segments that typically will 5194 * require defragmentation in iflib_encap(). 5195 */ 5196 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5197 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5198 } 5199 if (scctx->isc_rss_table_size == 0) 5200 scctx->isc_rss_table_size = 64; 5201 scctx->isc_rss_table_mask = scctx->isc_rss_table_size - 1; 5202 5203 /* Create and start admin taskqueue */ 5204 snprintf(namebuf, TASKQUEUE_NAMELEN, "if_%s_tq", device_get_nameunit(dev)); 5205 ctx->ifc_tq = taskqueue_create_fast(namebuf, M_NOWAIT, 5206 taskqueue_thread_enqueue, &ctx->ifc_tq); 5207 if (ctx->ifc_tq == NULL) { 5208 device_printf(dev, "Unable to create admin taskqueue\n"); 5209 return (ENOMEM); 5210 } 5211 5212 err = taskqueue_start_threads(&ctx->ifc_tq, 1, PI_NET, "%s", namebuf); 5213 if (err) { 5214 device_printf(dev, 5215 "Unable to start admin taskqueue threads error: %d\n", 5216 err); 5217 taskqueue_free(ctx->ifc_tq); 5218 return (err); 5219 } 5220 5221 TASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5222 5223 /* Set up cpu set. If it fails, use the set of all CPUs. */ 5224 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 5225 device_printf(dev, "Unable to fetch CPU list\n"); 5226 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 5227 ctx->ifc_cpus_are_physical_cores = false; 5228 } else 5229 ctx->ifc_cpus_are_physical_cores = true; 5230 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 5231 5232 /* 5233 * Now set up MSI or MSI-X, should return us the number of supported 5234 * vectors (will be 1 for a legacy interrupt and MSI). 5235 */ 5236 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 5237 msix = scctx->isc_vectors; 5238 } else if (scctx->isc_msix_bar != 0) 5239 /* 5240 * The simple fact that isc_msix_bar is not 0 does not mean we 5241 * we have a good value there that is known to work. 5242 */ 5243 msix = iflib_msix_init(ctx); 5244 else { 5245 scctx->isc_vectors = 1; 5246 scctx->isc_ntxqsets = 1; 5247 scctx->isc_nrxqsets = 1; 5248 scctx->isc_intr = IFLIB_INTR_LEGACY; 5249 msix = 0; 5250 } 5251 /* Get memory for the station queues */ 5252 if ((err = iflib_queues_alloc(ctx))) { 5253 device_printf(dev, "Unable to allocate queue memory\n"); 5254 goto fail_intr_free; 5255 } 5256 5257 if ((err = iflib_qset_structures_setup(ctx))) 5258 goto fail_queues; 5259 5260 /* 5261 * Now that we know how many queues there are, get the core offset. 5262 */ 5263 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 5264 5265 if (msix > 1) { 5266 /* 5267 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 5268 * aren't the default NULL implementation. 5269 */ 5270 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 5271 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5272 kobj_desc); 5273 if (kobj_method == &kobj_desc->deflt) { 5274 device_printf(dev, 5275 "MSI-X requires ifdi_rx_queue_intr_enable method"); 5276 err = EOPNOTSUPP; 5277 goto fail_queues; 5278 } 5279 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 5280 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5281 kobj_desc); 5282 if (kobj_method == &kobj_desc->deflt) { 5283 device_printf(dev, 5284 "MSI-X requires ifdi_tx_queue_intr_enable method"); 5285 err = EOPNOTSUPP; 5286 goto fail_queues; 5287 } 5288 5289 /* 5290 * Assign the MSI-X vectors. 5291 * Note that the default NULL ifdi_msix_intr_assign method will 5292 * fail here, too. 5293 */ 5294 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 5295 if (err != 0) { 5296 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 5297 err); 5298 goto fail_queues; 5299 } 5300 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 5301 rid = 0; 5302 if (scctx->isc_intr == IFLIB_INTR_MSI) { 5303 MPASS(msix == 1); 5304 rid = 1; 5305 } 5306 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 5307 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 5308 goto fail_queues; 5309 } 5310 } else { 5311 device_printf(dev, 5312 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 5313 err = ENODEV; 5314 goto fail_queues; 5315 } 5316 5317 /* 5318 * It prevents a double-locking panic with iflib_media_status when 5319 * the driver loads. 5320 */ 5321 CTX_UNLOCK(ctx); 5322 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5323 CTX_LOCK(ctx); 5324 5325 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5326 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5327 goto fail_detach; 5328 } 5329 5330 /* 5331 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5332 * This must appear after the call to ether_ifattach() because 5333 * ether_ifattach() sets if_hdrlen to the default value. 5334 */ 5335 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5336 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5337 5338 if ((err = iflib_netmap_attach(ctx))) { 5339 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 5340 goto fail_detach; 5341 } 5342 *ctxp = ctx; 5343 5344 DEBUGNET_SET(ctx->ifc_ifp, iflib); 5345 5346 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5347 iflib_add_device_sysctl_post(ctx); 5348 iflib_add_pfil(ctx); 5349 ctx->ifc_flags |= IFC_INIT_DONE; 5350 CTX_UNLOCK(ctx); 5351 IFNET_WUNLOCK(); 5352 5353 return (0); 5354 5355 fail_detach: 5356 ether_ifdetach(ctx->ifc_ifp); 5357 fail_queues: 5358 taskqueue_free(ctx->ifc_tq); 5359 iflib_tqg_detach(ctx); 5360 iflib_tx_structures_free(ctx); 5361 iflib_rx_structures_free(ctx); 5362 IFDI_DETACH(ctx); 5363 IFDI_QUEUES_FREE(ctx); 5364 fail_intr_free: 5365 iflib_free_intr_mem(ctx); 5366 fail_unlock: 5367 CTX_UNLOCK(ctx); 5368 IFNET_WUNLOCK(); 5369 iflib_deregister(ctx); 5370 fail_ctx_free: 5371 device_set_softc(ctx->ifc_dev, NULL); 5372 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5373 free(ctx->ifc_softc, M_IFLIB); 5374 free(ctx, M_IFLIB); 5375 return (err); 5376 } 5377 5378 int 5379 iflib_device_attach(device_t dev) 5380 { 5381 if_ctx_t ctx; 5382 if_shared_ctx_t sctx; 5383 5384 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5385 return (ENOTSUP); 5386 5387 pci_enable_busmaster(dev); 5388 5389 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5390 } 5391 5392 int 5393 iflib_device_deregister(if_ctx_t ctx) 5394 { 5395 if_t ifp = ctx->ifc_ifp; 5396 device_t dev = ctx->ifc_dev; 5397 5398 /* Make sure VLANS are not using driver */ 5399 if (if_vlantrunkinuse(ifp)) { 5400 device_printf(dev, "Vlan in use, detach first\n"); 5401 return (EBUSY); 5402 } 5403 #ifdef PCI_IOV 5404 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5405 device_printf(dev, "SR-IOV in use; detach first.\n"); 5406 return (EBUSY); 5407 } 5408 #endif 5409 5410 STATE_LOCK(ctx); 5411 ctx->ifc_flags |= IFC_IN_DETACH; 5412 STATE_UNLOCK(ctx); 5413 5414 /* Unregister VLAN handlers before calling iflib_stop() */ 5415 iflib_unregister_vlan_handlers(ctx); 5416 5417 iflib_netmap_detach(ifp); 5418 ether_ifdetach(ifp); 5419 5420 CTX_LOCK(ctx); 5421 iflib_stop(ctx); 5422 CTX_UNLOCK(ctx); 5423 5424 iflib_rem_pfil(ctx); 5425 if (ctx->ifc_led_dev != NULL) 5426 led_destroy(ctx->ifc_led_dev); 5427 5428 iflib_tqg_detach(ctx); 5429 iflib_tx_structures_free(ctx); 5430 iflib_rx_structures_free(ctx); 5431 5432 CTX_LOCK(ctx); 5433 IFDI_DETACH(ctx); 5434 IFDI_QUEUES_FREE(ctx); 5435 CTX_UNLOCK(ctx); 5436 5437 taskqueue_free(ctx->ifc_tq); 5438 ctx->ifc_tq = NULL; 5439 5440 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5441 iflib_free_intr_mem(ctx); 5442 5443 bus_generic_detach(dev); 5444 5445 iflib_deregister(ctx); 5446 5447 device_set_softc(ctx->ifc_dev, NULL); 5448 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5449 free(ctx->ifc_softc, M_IFLIB); 5450 unref_ctx_core_offset(ctx); 5451 free(ctx, M_IFLIB); 5452 return (0); 5453 } 5454 5455 static void 5456 iflib_tqg_detach(if_ctx_t ctx) 5457 { 5458 iflib_txq_t txq; 5459 iflib_rxq_t rxq; 5460 int i; 5461 struct taskqgroup *tqg; 5462 5463 /* XXX drain any dependent tasks */ 5464 tqg = qgroup_if_io_tqg; 5465 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5466 callout_drain(&txq->ift_timer); 5467 #ifdef DEV_NETMAP 5468 callout_drain(&txq->ift_netmap_timer); 5469 #endif /* DEV_NETMAP */ 5470 if (txq->ift_task.gt_uniq != NULL) 5471 taskqgroup_detach(tqg, &txq->ift_task); 5472 } 5473 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5474 if (rxq->ifr_task.gt_uniq != NULL) 5475 taskqgroup_detach(tqg, &rxq->ifr_task); 5476 } 5477 } 5478 5479 static void 5480 iflib_free_intr_mem(if_ctx_t ctx) 5481 { 5482 5483 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5484 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5485 } 5486 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5487 pci_release_msi(ctx->ifc_dev); 5488 } 5489 if (ctx->ifc_msix_mem != NULL) { 5490 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5491 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5492 ctx->ifc_msix_mem = NULL; 5493 } 5494 } 5495 5496 int 5497 iflib_device_detach(device_t dev) 5498 { 5499 if_ctx_t ctx = device_get_softc(dev); 5500 5501 return (iflib_device_deregister(ctx)); 5502 } 5503 5504 int 5505 iflib_device_suspend(device_t dev) 5506 { 5507 if_ctx_t ctx = device_get_softc(dev); 5508 5509 CTX_LOCK(ctx); 5510 IFDI_SUSPEND(ctx); 5511 CTX_UNLOCK(ctx); 5512 5513 return (bus_generic_suspend(dev)); 5514 } 5515 int 5516 iflib_device_shutdown(device_t dev) 5517 { 5518 if_ctx_t ctx = device_get_softc(dev); 5519 5520 CTX_LOCK(ctx); 5521 IFDI_SHUTDOWN(ctx); 5522 CTX_UNLOCK(ctx); 5523 5524 return (bus_generic_suspend(dev)); 5525 } 5526 5527 int 5528 iflib_device_resume(device_t dev) 5529 { 5530 if_ctx_t ctx = device_get_softc(dev); 5531 iflib_txq_t txq = ctx->ifc_txqs; 5532 5533 CTX_LOCK(ctx); 5534 IFDI_RESUME(ctx); 5535 iflib_if_init_locked(ctx); 5536 CTX_UNLOCK(ctx); 5537 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5538 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5539 5540 return (bus_generic_resume(dev)); 5541 } 5542 5543 int 5544 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5545 { 5546 int error; 5547 if_ctx_t ctx = device_get_softc(dev); 5548 5549 CTX_LOCK(ctx); 5550 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5551 CTX_UNLOCK(ctx); 5552 5553 return (error); 5554 } 5555 5556 void 5557 iflib_device_iov_uninit(device_t dev) 5558 { 5559 if_ctx_t ctx = device_get_softc(dev); 5560 5561 CTX_LOCK(ctx); 5562 IFDI_IOV_UNINIT(ctx); 5563 CTX_UNLOCK(ctx); 5564 } 5565 5566 int 5567 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5568 { 5569 int error; 5570 if_ctx_t ctx = device_get_softc(dev); 5571 5572 CTX_LOCK(ctx); 5573 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5574 CTX_UNLOCK(ctx); 5575 5576 return (error); 5577 } 5578 5579 /********************************************************************* 5580 * 5581 * MODULE FUNCTION DEFINITIONS 5582 * 5583 **********************************************************************/ 5584 5585 /* 5586 * - Start a fast taskqueue thread for each core 5587 * - Start a taskqueue for control operations 5588 */ 5589 static int 5590 iflib_module_init(void) 5591 { 5592 iflib_timer_default = hz / 2; 5593 return (0); 5594 } 5595 5596 static int 5597 iflib_module_event_handler(module_t mod, int what, void *arg) 5598 { 5599 int err; 5600 5601 switch (what) { 5602 case MOD_LOAD: 5603 if ((err = iflib_module_init()) != 0) 5604 return (err); 5605 break; 5606 case MOD_UNLOAD: 5607 return (EBUSY); 5608 default: 5609 return (EOPNOTSUPP); 5610 } 5611 5612 return (0); 5613 } 5614 5615 /********************************************************************* 5616 * 5617 * PUBLIC FUNCTION DEFINITIONS 5618 * ordered as in iflib.h 5619 * 5620 **********************************************************************/ 5621 5622 static void 5623 _iflib_assert(if_shared_ctx_t sctx) 5624 { 5625 int i; 5626 5627 MPASS(sctx->isc_tx_maxsize); 5628 MPASS(sctx->isc_tx_maxsegsize); 5629 5630 MPASS(sctx->isc_rx_maxsize); 5631 MPASS(sctx->isc_rx_nsegments); 5632 MPASS(sctx->isc_rx_maxsegsize); 5633 5634 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5635 for (i = 0; i < sctx->isc_nrxqs; i++) { 5636 MPASS(sctx->isc_nrxd_min[i]); 5637 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5638 MPASS(sctx->isc_nrxd_max[i]); 5639 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5640 MPASS(sctx->isc_nrxd_default[i]); 5641 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5642 } 5643 5644 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5645 for (i = 0; i < sctx->isc_ntxqs; i++) { 5646 MPASS(sctx->isc_ntxd_min[i]); 5647 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5648 MPASS(sctx->isc_ntxd_max[i]); 5649 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5650 MPASS(sctx->isc_ntxd_default[i]); 5651 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5652 } 5653 } 5654 5655 static void 5656 _iflib_pre_assert(if_softc_ctx_t scctx) 5657 { 5658 5659 MPASS(scctx->isc_txrx->ift_txd_encap); 5660 MPASS(scctx->isc_txrx->ift_txd_flush); 5661 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5662 MPASS(scctx->isc_txrx->ift_rxd_available); 5663 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5664 MPASS(scctx->isc_txrx->ift_rxd_refill); 5665 MPASS(scctx->isc_txrx->ift_rxd_flush); 5666 } 5667 5668 static int 5669 iflib_register(if_ctx_t ctx) 5670 { 5671 if_shared_ctx_t sctx = ctx->ifc_sctx; 5672 driver_t *driver = sctx->isc_driver; 5673 device_t dev = ctx->ifc_dev; 5674 if_t ifp; 5675 5676 _iflib_assert(sctx); 5677 5678 CTX_LOCK_INIT(ctx); 5679 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5680 ifp = ctx->ifc_ifp = if_alloc_dev(IFT_ETHER, dev); 5681 5682 /* 5683 * Initialize our context's device specific methods 5684 */ 5685 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5686 kobj_class_compile((kobj_class_t) driver); 5687 5688 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5689 if_setsoftc(ifp, ctx); 5690 if_setdev(ifp, dev); 5691 if_setinitfn(ifp, iflib_if_init); 5692 if_setioctlfn(ifp, iflib_if_ioctl); 5693 #ifdef ALTQ 5694 if_setstartfn(ifp, iflib_altq_if_start); 5695 if_settransmitfn(ifp, iflib_altq_if_transmit); 5696 if_setsendqready(ifp); 5697 #else 5698 if_settransmitfn(ifp, iflib_if_transmit); 5699 #endif 5700 if_setqflushfn(ifp, iflib_if_qflush); 5701 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5702 ctx->ifc_vlan_attach_event = 5703 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5704 EVENTHANDLER_PRI_FIRST); 5705 ctx->ifc_vlan_detach_event = 5706 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5707 EVENTHANDLER_PRI_FIRST); 5708 5709 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5710 ctx->ifc_mediap = &ctx->ifc_media; 5711 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5712 iflib_media_change, iflib_media_status); 5713 } 5714 return (0); 5715 } 5716 5717 static void 5718 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5719 { 5720 /* Unregister VLAN events */ 5721 if (ctx->ifc_vlan_attach_event != NULL) { 5722 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5723 ctx->ifc_vlan_attach_event = NULL; 5724 } 5725 if (ctx->ifc_vlan_detach_event != NULL) { 5726 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5727 ctx->ifc_vlan_detach_event = NULL; 5728 } 5729 5730 } 5731 5732 static void 5733 iflib_deregister(if_ctx_t ctx) 5734 { 5735 if_t ifp = ctx->ifc_ifp; 5736 5737 /* Remove all media */ 5738 ifmedia_removeall(&ctx->ifc_media); 5739 5740 /* Ensure that VLAN event handlers are unregistered */ 5741 iflib_unregister_vlan_handlers(ctx); 5742 5743 /* Release kobject reference */ 5744 kobj_delete((kobj_t) ctx, NULL); 5745 5746 /* Free the ifnet structure */ 5747 if_free(ifp); 5748 5749 STATE_LOCK_DESTROY(ctx); 5750 5751 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5752 CTX_LOCK_DESTROY(ctx); 5753 } 5754 5755 static int 5756 iflib_queues_alloc(if_ctx_t ctx) 5757 { 5758 if_shared_ctx_t sctx = ctx->ifc_sctx; 5759 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5760 device_t dev = ctx->ifc_dev; 5761 int nrxqsets = scctx->isc_nrxqsets; 5762 int ntxqsets = scctx->isc_ntxqsets; 5763 iflib_txq_t txq; 5764 iflib_rxq_t rxq; 5765 iflib_fl_t fl = NULL; 5766 int i, j, cpu, err, txconf, rxconf; 5767 iflib_dma_info_t ifdip; 5768 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5769 uint32_t *txqsizes = scctx->isc_txqsizes; 5770 uint8_t nrxqs = sctx->isc_nrxqs; 5771 uint8_t ntxqs = sctx->isc_ntxqs; 5772 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5773 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0); 5774 caddr_t *vaddrs; 5775 uint64_t *paddrs; 5776 5777 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5778 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5779 KASSERT(nrxqs >= fl_offset + nfree_lists, 5780 ("there must be at least a rxq for each free list")); 5781 5782 /* Allocate the TX ring struct memory */ 5783 if (!(ctx->ifc_txqs = 5784 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5785 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5786 device_printf(dev, "Unable to allocate TX ring memory\n"); 5787 err = ENOMEM; 5788 goto fail; 5789 } 5790 5791 /* Now allocate the RX */ 5792 if (!(ctx->ifc_rxqs = 5793 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5794 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5795 device_printf(dev, "Unable to allocate RX ring memory\n"); 5796 err = ENOMEM; 5797 goto rx_fail; 5798 } 5799 5800 txq = ctx->ifc_txqs; 5801 rxq = ctx->ifc_rxqs; 5802 5803 /* 5804 * XXX handle allocation failure 5805 */ 5806 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5807 /* Set up some basics */ 5808 5809 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5810 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5811 device_printf(dev, 5812 "Unable to allocate TX DMA info memory\n"); 5813 err = ENOMEM; 5814 goto err_tx_desc; 5815 } 5816 txq->ift_ifdi = ifdip; 5817 for (j = 0; j < ntxqs; j++, ifdip++) { 5818 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5819 device_printf(dev, 5820 "Unable to allocate TX descriptors\n"); 5821 err = ENOMEM; 5822 goto err_tx_desc; 5823 } 5824 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5825 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5826 } 5827 txq->ift_ctx = ctx; 5828 txq->ift_id = i; 5829 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5830 txq->ift_br_offset = 1; 5831 } else { 5832 txq->ift_br_offset = 0; 5833 } 5834 5835 if (iflib_txsd_alloc(txq)) { 5836 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5837 err = ENOMEM; 5838 goto err_tx_desc; 5839 } 5840 5841 /* Initialize the TX lock */ 5842 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5843 device_get_nameunit(dev), txq->ift_id); 5844 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5845 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5846 txq->ift_timer.c_cpu = cpu; 5847 #ifdef DEV_NETMAP 5848 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 5849 txq->ift_netmap_timer.c_cpu = cpu; 5850 #endif /* DEV_NETMAP */ 5851 5852 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5853 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5854 if (err) { 5855 /* XXX free any allocated rings */ 5856 device_printf(dev, "Unable to allocate buf_ring\n"); 5857 goto err_tx_desc; 5858 } 5859 } 5860 5861 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5862 /* Set up some basics */ 5863 callout_init(&rxq->ifr_watchdog, 1); 5864 5865 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5866 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5867 device_printf(dev, 5868 "Unable to allocate RX DMA info memory\n"); 5869 err = ENOMEM; 5870 goto err_tx_desc; 5871 } 5872 5873 rxq->ifr_ifdi = ifdip; 5874 /* XXX this needs to be changed if #rx queues != #tx queues */ 5875 rxq->ifr_ntxqirq = 1; 5876 rxq->ifr_txqid[0] = i; 5877 for (j = 0; j < nrxqs; j++, ifdip++) { 5878 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5879 device_printf(dev, 5880 "Unable to allocate RX descriptors\n"); 5881 err = ENOMEM; 5882 goto err_tx_desc; 5883 } 5884 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5885 } 5886 rxq->ifr_ctx = ctx; 5887 rxq->ifr_id = i; 5888 rxq->ifr_fl_offset = fl_offset; 5889 rxq->ifr_nfl = nfree_lists; 5890 if (!(fl = 5891 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5892 device_printf(dev, "Unable to allocate free list memory\n"); 5893 err = ENOMEM; 5894 goto err_tx_desc; 5895 } 5896 rxq->ifr_fl = fl; 5897 for (j = 0; j < nfree_lists; j++) { 5898 fl[j].ifl_rxq = rxq; 5899 fl[j].ifl_id = j; 5900 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5901 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5902 } 5903 /* Allocate receive buffers for the ring */ 5904 if (iflib_rxsd_alloc(rxq)) { 5905 device_printf(dev, 5906 "Critical Failure setting up receive buffers\n"); 5907 err = ENOMEM; 5908 goto err_rx_desc; 5909 } 5910 5911 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5912 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5913 M_WAITOK); 5914 } 5915 5916 /* TXQs */ 5917 vaddrs = malloc(sizeof(caddr_t) * ntxqsets * ntxqs, M_IFLIB, M_WAITOK); 5918 paddrs = malloc(sizeof(uint64_t) * ntxqsets * ntxqs, M_IFLIB, M_WAITOK); 5919 for (i = 0; i < ntxqsets; i++) { 5920 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5921 5922 for (j = 0; j < ntxqs; j++, di++) { 5923 vaddrs[i * ntxqs + j] = di->idi_vaddr; 5924 paddrs[i * ntxqs + j] = di->idi_paddr; 5925 } 5926 } 5927 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5928 device_printf(ctx->ifc_dev, 5929 "Unable to allocate device TX queue\n"); 5930 iflib_tx_structures_free(ctx); 5931 free(vaddrs, M_IFLIB); 5932 free(paddrs, M_IFLIB); 5933 goto err_rx_desc; 5934 } 5935 free(vaddrs, M_IFLIB); 5936 free(paddrs, M_IFLIB); 5937 5938 /* RXQs */ 5939 vaddrs = malloc(sizeof(caddr_t) * nrxqsets * nrxqs, M_IFLIB, M_WAITOK); 5940 paddrs = malloc(sizeof(uint64_t) * nrxqsets * nrxqs, M_IFLIB, M_WAITOK); 5941 for (i = 0; i < nrxqsets; i++) { 5942 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5943 5944 for (j = 0; j < nrxqs; j++, di++) { 5945 vaddrs[i * nrxqs + j] = di->idi_vaddr; 5946 paddrs[i * nrxqs + j] = di->idi_paddr; 5947 } 5948 } 5949 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5950 device_printf(ctx->ifc_dev, 5951 "Unable to allocate device RX queue\n"); 5952 iflib_tx_structures_free(ctx); 5953 free(vaddrs, M_IFLIB); 5954 free(paddrs, M_IFLIB); 5955 goto err_rx_desc; 5956 } 5957 free(vaddrs, M_IFLIB); 5958 free(paddrs, M_IFLIB); 5959 5960 return (0); 5961 5962 /* XXX handle allocation failure changes */ 5963 err_rx_desc: 5964 err_tx_desc: 5965 rx_fail: 5966 if (ctx->ifc_rxqs != NULL) 5967 free(ctx->ifc_rxqs, M_IFLIB); 5968 ctx->ifc_rxqs = NULL; 5969 if (ctx->ifc_txqs != NULL) 5970 free(ctx->ifc_txqs, M_IFLIB); 5971 ctx->ifc_txqs = NULL; 5972 fail: 5973 return (err); 5974 } 5975 5976 static int 5977 iflib_tx_structures_setup(if_ctx_t ctx) 5978 { 5979 iflib_txq_t txq = ctx->ifc_txqs; 5980 int i; 5981 5982 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5983 iflib_txq_setup(txq); 5984 5985 return (0); 5986 } 5987 5988 static void 5989 iflib_tx_structures_free(if_ctx_t ctx) 5990 { 5991 iflib_txq_t txq = ctx->ifc_txqs; 5992 if_shared_ctx_t sctx = ctx->ifc_sctx; 5993 int i, j; 5994 5995 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5996 for (j = 0; j < sctx->isc_ntxqs; j++) 5997 iflib_dma_free(&txq->ift_ifdi[j]); 5998 iflib_txq_destroy(txq); 5999 } 6000 free(ctx->ifc_txqs, M_IFLIB); 6001 ctx->ifc_txqs = NULL; 6002 } 6003 6004 /********************************************************************* 6005 * 6006 * Initialize all receive rings. 6007 * 6008 **********************************************************************/ 6009 static int 6010 iflib_rx_structures_setup(if_ctx_t ctx) 6011 { 6012 iflib_rxq_t rxq = ctx->ifc_rxqs; 6013 int q; 6014 #if defined(INET6) || defined(INET) 6015 int err, i; 6016 #endif 6017 6018 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 6019 #if defined(INET6) || defined(INET) 6020 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 6021 TCP_LRO_ENTRIES, min(1024, 6022 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 6023 if (err != 0) { 6024 device_printf(ctx->ifc_dev, 6025 "LRO Initialization failed!\n"); 6026 goto fail; 6027 } 6028 #endif 6029 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 6030 } 6031 return (0); 6032 #if defined(INET6) || defined(INET) 6033 fail: 6034 /* 6035 * Free LRO resources allocated so far, we will only handle 6036 * the rings that completed, the failing case will have 6037 * cleaned up for itself. 'q' failed, so its the terminus. 6038 */ 6039 rxq = ctx->ifc_rxqs; 6040 for (i = 0; i < q; ++i, rxq++) { 6041 tcp_lro_free(&rxq->ifr_lc); 6042 } 6043 return (err); 6044 #endif 6045 } 6046 6047 /********************************************************************* 6048 * 6049 * Free all receive rings. 6050 * 6051 **********************************************************************/ 6052 static void 6053 iflib_rx_structures_free(if_ctx_t ctx) 6054 { 6055 iflib_rxq_t rxq = ctx->ifc_rxqs; 6056 if_shared_ctx_t sctx = ctx->ifc_sctx; 6057 int i, j; 6058 6059 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 6060 for (j = 0; j < sctx->isc_nrxqs; j++) 6061 iflib_dma_free(&rxq->ifr_ifdi[j]); 6062 iflib_rx_sds_free(rxq); 6063 #if defined(INET6) || defined(INET) 6064 tcp_lro_free(&rxq->ifr_lc); 6065 #endif 6066 } 6067 free(ctx->ifc_rxqs, M_IFLIB); 6068 ctx->ifc_rxqs = NULL; 6069 } 6070 6071 static int 6072 iflib_qset_structures_setup(if_ctx_t ctx) 6073 { 6074 int err; 6075 6076 /* 6077 * It is expected that the caller takes care of freeing queues if this 6078 * fails. 6079 */ 6080 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 6081 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 6082 return (err); 6083 } 6084 6085 if ((err = iflib_rx_structures_setup(ctx)) != 0) 6086 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 6087 6088 return (err); 6089 } 6090 6091 int 6092 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 6093 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 6094 { 6095 6096 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 6097 } 6098 6099 /* Just to avoid copy/paste */ 6100 static inline int 6101 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6102 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 6103 const char *name) 6104 { 6105 device_t dev; 6106 unsigned int base_cpuid, cpuid; 6107 int err; 6108 6109 dev = ctx->ifc_dev; 6110 base_cpuid = ctx->ifc_sysctl_core_offset; 6111 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX); 6112 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, 6113 irq ? irq->ii_res : NULL, name); 6114 if (err) { 6115 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6116 return (err); 6117 } 6118 #ifdef notyet 6119 if (cpuid > ctx->ifc_cpuid_highest) 6120 ctx->ifc_cpuid_highest = cpuid; 6121 #endif 6122 return (0); 6123 } 6124 6125 /* 6126 * Allocate a hardware interrupt for subctx using the parent (ctx)'s hardware 6127 * resources. 6128 * 6129 * Similar to iflib_irq_alloc_generic(), but for interrupt type IFLIB_INTR_RXTX 6130 * only. 6131 * 6132 * XXX: Could be removed if subctx's dev has its intr resource allocation 6133 * methods replaced with custom ones? 6134 */ 6135 int 6136 iflib_irq_alloc_generic_subctx(if_ctx_t ctx, if_ctx_t subctx, if_irq_t irq, 6137 int rid, iflib_intr_type_t type, 6138 driver_filter_t *filter, void *filter_arg, 6139 int qid, const char *name) 6140 { 6141 device_t dev, subdev; 6142 struct grouptask *gtask; 6143 struct taskqgroup *tqg; 6144 iflib_filter_info_t info; 6145 gtask_fn_t *fn; 6146 int tqrid, err; 6147 driver_filter_t *intr_fast; 6148 void *q; 6149 6150 MPASS(ctx != NULL); 6151 MPASS(subctx != NULL); 6152 6153 tqrid = rid; 6154 dev = ctx->ifc_dev; 6155 subdev = subctx->ifc_dev; 6156 6157 switch (type) { 6158 case IFLIB_INTR_RXTX: 6159 q = &subctx->ifc_rxqs[qid]; 6160 info = &subctx->ifc_rxqs[qid].ifr_filter_info; 6161 gtask = &subctx->ifc_rxqs[qid].ifr_task; 6162 tqg = qgroup_if_io_tqg; 6163 fn = _task_fn_rx; 6164 intr_fast = iflib_fast_intr_rxtx; 6165 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6166 break; 6167 default: 6168 device_printf(dev, "%s: unknown net intr type for subctx %s (%d)\n", 6169 __func__, device_get_nameunit(subdev), type); 6170 return (EINVAL); 6171 } 6172 6173 info->ifi_filter = filter; 6174 info->ifi_filter_arg = filter_arg; 6175 info->ifi_task = gtask; 6176 info->ifi_ctx = q; 6177 6178 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6179 6180 /* Allocate interrupts from hardware using parent context */ 6181 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6182 if (err != 0) { 6183 device_printf(dev, "_iflib_irq_alloc failed for subctx %s: %d\n", 6184 device_get_nameunit(subdev), err); 6185 return (err); 6186 } 6187 6188 if (tqrid != -1) { 6189 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6190 name); 6191 if (err) 6192 return (err); 6193 } else { 6194 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6195 } 6196 6197 return (0); 6198 } 6199 6200 int 6201 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6202 iflib_intr_type_t type, driver_filter_t *filter, 6203 void *filter_arg, int qid, const char *name) 6204 { 6205 device_t dev; 6206 struct grouptask *gtask; 6207 struct taskqgroup *tqg; 6208 iflib_filter_info_t info; 6209 gtask_fn_t *fn; 6210 int tqrid, err; 6211 driver_filter_t *intr_fast; 6212 void *q; 6213 6214 info = &ctx->ifc_filter_info; 6215 tqrid = rid; 6216 6217 switch (type) { 6218 /* XXX merge tx/rx for netmap? */ 6219 case IFLIB_INTR_TX: 6220 q = &ctx->ifc_txqs[qid]; 6221 info = &ctx->ifc_txqs[qid].ift_filter_info; 6222 gtask = &ctx->ifc_txqs[qid].ift_task; 6223 tqg = qgroup_if_io_tqg; 6224 fn = _task_fn_tx; 6225 intr_fast = iflib_fast_intr; 6226 GROUPTASK_INIT(gtask, 0, fn, q); 6227 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6228 break; 6229 case IFLIB_INTR_RX: 6230 q = &ctx->ifc_rxqs[qid]; 6231 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6232 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6233 tqg = qgroup_if_io_tqg; 6234 fn = _task_fn_rx; 6235 intr_fast = iflib_fast_intr; 6236 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6237 break; 6238 case IFLIB_INTR_RXTX: 6239 q = &ctx->ifc_rxqs[qid]; 6240 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6241 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6242 tqg = qgroup_if_io_tqg; 6243 fn = _task_fn_rx; 6244 intr_fast = iflib_fast_intr_rxtx; 6245 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6246 break; 6247 case IFLIB_INTR_ADMIN: 6248 q = ctx; 6249 tqrid = -1; 6250 info = &ctx->ifc_filter_info; 6251 gtask = NULL; 6252 intr_fast = iflib_fast_intr_ctx; 6253 break; 6254 default: 6255 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6256 __func__); 6257 return (EINVAL); 6258 } 6259 6260 info->ifi_filter = filter; 6261 info->ifi_filter_arg = filter_arg; 6262 info->ifi_task = gtask; 6263 info->ifi_ctx = q; 6264 6265 dev = ctx->ifc_dev; 6266 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6267 if (err != 0) { 6268 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6269 return (err); 6270 } 6271 if (type == IFLIB_INTR_ADMIN) 6272 return (0); 6273 6274 if (tqrid != -1) { 6275 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6276 name); 6277 if (err) 6278 return (err); 6279 } else { 6280 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6281 } 6282 6283 return (0); 6284 } 6285 6286 void 6287 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6288 void *arg, int qid, const char *name) 6289 { 6290 device_t dev; 6291 struct grouptask *gtask; 6292 struct taskqgroup *tqg; 6293 gtask_fn_t *fn; 6294 void *q; 6295 int err; 6296 6297 switch (type) { 6298 case IFLIB_INTR_TX: 6299 q = &ctx->ifc_txqs[qid]; 6300 gtask = &ctx->ifc_txqs[qid].ift_task; 6301 tqg = qgroup_if_io_tqg; 6302 fn = _task_fn_tx; 6303 GROUPTASK_INIT(gtask, 0, fn, q); 6304 break; 6305 case IFLIB_INTR_RX: 6306 q = &ctx->ifc_rxqs[qid]; 6307 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6308 tqg = qgroup_if_io_tqg; 6309 fn = _task_fn_rx; 6310 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6311 break; 6312 case IFLIB_INTR_IOV: 6313 TASK_INIT(&ctx->ifc_vflr_task, 0, _task_fn_iov, ctx); 6314 return; 6315 default: 6316 panic("unknown net intr type"); 6317 } 6318 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name); 6319 if (err) { 6320 dev = ctx->ifc_dev; 6321 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL, 6322 name); 6323 } 6324 } 6325 6326 void 6327 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6328 { 6329 6330 if (irq->ii_tag) 6331 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6332 6333 if (irq->ii_res) 6334 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6335 rman_get_rid(irq->ii_res), irq->ii_res); 6336 } 6337 6338 static int 6339 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6340 { 6341 iflib_txq_t txq = ctx->ifc_txqs; 6342 iflib_rxq_t rxq = ctx->ifc_rxqs; 6343 if_irq_t irq = &ctx->ifc_legacy_irq; 6344 iflib_filter_info_t info; 6345 device_t dev; 6346 struct grouptask *gtask; 6347 struct resource *res; 6348 int err, tqrid; 6349 bool rx_only; 6350 6351 info = &rxq->ifr_filter_info; 6352 gtask = &rxq->ifr_task; 6353 tqrid = *rid; 6354 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6355 6356 ctx->ifc_flags |= IFC_LEGACY; 6357 info->ifi_filter = filter; 6358 info->ifi_filter_arg = filter_arg; 6359 info->ifi_task = gtask; 6360 info->ifi_ctx = rxq; 6361 6362 dev = ctx->ifc_dev; 6363 /* We allocate a single interrupt resource */ 6364 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr : 6365 iflib_fast_intr_rxtx, NULL, info, name); 6366 if (err != 0) 6367 return (err); 6368 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, rxq); 6369 res = irq->ii_res; 6370 taskqgroup_attach(qgroup_if_io_tqg, gtask, rxq, dev, res, name); 6371 6372 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6373 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6374 "tx"); 6375 return (0); 6376 } 6377 6378 void 6379 iflib_led_create(if_ctx_t ctx) 6380 { 6381 6382 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6383 device_get_nameunit(ctx->ifc_dev)); 6384 } 6385 6386 void 6387 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6388 { 6389 6390 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6391 } 6392 6393 void 6394 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6395 { 6396 6397 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6398 } 6399 6400 void 6401 iflib_admin_intr_deferred(if_ctx_t ctx) 6402 { 6403 6404 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_admin_task); 6405 } 6406 6407 void 6408 iflib_iov_intr_deferred(if_ctx_t ctx) 6409 { 6410 6411 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_vflr_task); 6412 } 6413 6414 void 6415 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6416 { 6417 6418 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6419 name); 6420 } 6421 6422 void 6423 iflib_config_task_init(if_ctx_t ctx, struct task *config_task, task_fn_t *fn) 6424 { 6425 TASK_INIT(config_task, 0, fn, ctx); 6426 } 6427 6428 void 6429 iflib_config_task_enqueue(if_ctx_t ctx, struct task *config_task) 6430 { 6431 taskqueue_enqueue(ctx->ifc_tq, config_task); 6432 } 6433 6434 void 6435 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6436 { 6437 if_t ifp = ctx->ifc_ifp; 6438 iflib_txq_t txq = ctx->ifc_txqs; 6439 6440 if_setbaudrate(ifp, baudrate); 6441 if (baudrate >= IF_Gbps(10)) { 6442 STATE_LOCK(ctx); 6443 ctx->ifc_flags |= IFC_PREFETCH; 6444 STATE_UNLOCK(ctx); 6445 } 6446 /* If link down, disable watchdog */ 6447 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6448 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6449 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6450 } 6451 ctx->ifc_link_state = link_state; 6452 if_link_state_change(ifp, link_state); 6453 } 6454 6455 static int 6456 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6457 { 6458 int credits; 6459 #ifdef INVARIANTS 6460 int credits_pre = txq->ift_cidx_processed; 6461 #endif 6462 6463 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6464 BUS_DMASYNC_POSTREAD); 6465 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6466 return (0); 6467 6468 txq->ift_processed += credits; 6469 txq->ift_cidx_processed += credits; 6470 6471 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6472 if (txq->ift_cidx_processed >= txq->ift_size) 6473 txq->ift_cidx_processed -= txq->ift_size; 6474 return (credits); 6475 } 6476 6477 static int 6478 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6479 { 6480 iflib_fl_t fl; 6481 u_int i; 6482 6483 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6484 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6485 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6486 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6487 budget)); 6488 } 6489 6490 void 6491 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6492 const char *description, if_int_delay_info_t info, 6493 int offset, int value) 6494 { 6495 info->iidi_ctx = ctx; 6496 info->iidi_offset = offset; 6497 info->iidi_value = value; 6498 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6499 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6500 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6501 info, 0, iflib_sysctl_int_delay, "I", description); 6502 } 6503 6504 struct sx * 6505 iflib_ctx_lock_get(if_ctx_t ctx) 6506 { 6507 6508 return (&ctx->ifc_ctx_sx); 6509 } 6510 6511 static int 6512 iflib_msix_init(if_ctx_t ctx) 6513 { 6514 device_t dev = ctx->ifc_dev; 6515 if_shared_ctx_t sctx = ctx->ifc_sctx; 6516 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6517 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6518 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6519 6520 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6521 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6522 6523 if (bootverbose) 6524 device_printf(dev, "msix_init qsets capped at %d\n", 6525 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6526 6527 /* Override by tuneable */ 6528 if (scctx->isc_disable_msix) 6529 goto msi; 6530 6531 /* First try MSI-X */ 6532 if ((msgs = pci_msix_count(dev)) == 0) { 6533 if (bootverbose) 6534 device_printf(dev, "MSI-X not supported or disabled\n"); 6535 goto msi; 6536 } 6537 6538 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6539 /* 6540 * bar == -1 => "trust me I know what I'm doing" 6541 * Some drivers are for hardware that is so shoddily 6542 * documented that no one knows which bars are which 6543 * so the developer has to map all bars. This hack 6544 * allows shoddy garbage to use MSI-X in this framework. 6545 */ 6546 if (bar != -1) { 6547 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6548 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6549 if (ctx->ifc_msix_mem == NULL) { 6550 device_printf(dev, "Unable to map MSI-X table\n"); 6551 goto msi; 6552 } 6553 } 6554 6555 admincnt = sctx->isc_admin_intrcnt; 6556 #if IFLIB_DEBUG 6557 /* use only 1 qset in debug mode */ 6558 queuemsgs = min(msgs - admincnt, 1); 6559 #else 6560 queuemsgs = msgs - admincnt; 6561 #endif 6562 #ifdef RSS 6563 queues = imin(queuemsgs, rss_getnumbuckets()); 6564 #else 6565 queues = queuemsgs; 6566 #endif 6567 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6568 if (bootverbose) 6569 device_printf(dev, 6570 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6571 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6572 #ifdef RSS 6573 /* If we're doing RSS, clamp at the number of RSS buckets */ 6574 if (queues > rss_getnumbuckets()) 6575 queues = rss_getnumbuckets(); 6576 #endif 6577 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6578 rx_queues = iflib_num_rx_queues; 6579 else 6580 rx_queues = queues; 6581 6582 if (rx_queues > scctx->isc_nrxqsets) 6583 rx_queues = scctx->isc_nrxqsets; 6584 6585 /* 6586 * We want this to be all logical CPUs by default 6587 */ 6588 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6589 tx_queues = iflib_num_tx_queues; 6590 else 6591 tx_queues = mp_ncpus; 6592 6593 if (tx_queues > scctx->isc_ntxqsets) 6594 tx_queues = scctx->isc_ntxqsets; 6595 6596 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6597 #ifdef INVARIANTS 6598 if (tx_queues != rx_queues) 6599 device_printf(dev, 6600 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6601 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6602 #endif 6603 tx_queues = min(rx_queues, tx_queues); 6604 rx_queues = min(rx_queues, tx_queues); 6605 } 6606 6607 vectors = rx_queues + admincnt; 6608 if (msgs < vectors) { 6609 device_printf(dev, 6610 "insufficient number of MSI-X vectors " 6611 "(supported %d, need %d)\n", msgs, vectors); 6612 goto msi; 6613 } 6614 6615 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6616 tx_queues); 6617 msgs = vectors; 6618 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6619 if (vectors != msgs) { 6620 device_printf(dev, 6621 "Unable to allocate sufficient MSI-X vectors " 6622 "(got %d, need %d)\n", vectors, msgs); 6623 pci_release_msi(dev); 6624 if (bar != -1) { 6625 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6626 ctx->ifc_msix_mem); 6627 ctx->ifc_msix_mem = NULL; 6628 } 6629 goto msi; 6630 } 6631 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6632 vectors); 6633 scctx->isc_vectors = vectors; 6634 scctx->isc_nrxqsets = rx_queues; 6635 scctx->isc_ntxqsets = tx_queues; 6636 scctx->isc_intr = IFLIB_INTR_MSIX; 6637 6638 return (vectors); 6639 } else { 6640 device_printf(dev, 6641 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6642 err); 6643 if (bar != -1) { 6644 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6645 ctx->ifc_msix_mem); 6646 ctx->ifc_msix_mem = NULL; 6647 } 6648 } 6649 6650 msi: 6651 vectors = pci_msi_count(dev); 6652 scctx->isc_nrxqsets = 1; 6653 scctx->isc_ntxqsets = 1; 6654 scctx->isc_vectors = vectors; 6655 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6656 device_printf(dev, "Using an MSI interrupt\n"); 6657 scctx->isc_intr = IFLIB_INTR_MSI; 6658 } else { 6659 scctx->isc_vectors = 1; 6660 device_printf(dev, "Using a Legacy interrupt\n"); 6661 scctx->isc_intr = IFLIB_INTR_LEGACY; 6662 } 6663 6664 return (vectors); 6665 } 6666 6667 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6668 6669 static int 6670 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6671 { 6672 int rc; 6673 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6674 struct sbuf *sb; 6675 const char *ring_state = "UNKNOWN"; 6676 6677 /* XXX needed ? */ 6678 rc = sysctl_wire_old_buffer(req, 0); 6679 MPASS(rc == 0); 6680 if (rc != 0) 6681 return (rc); 6682 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6683 MPASS(sb != NULL); 6684 if (sb == NULL) 6685 return (ENOMEM); 6686 if (state[3] <= 3) 6687 ring_state = ring_states[state[3]]; 6688 6689 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6690 state[0], state[1], state[2], ring_state); 6691 rc = sbuf_finish(sb); 6692 sbuf_delete(sb); 6693 return (rc); 6694 } 6695 6696 enum iflib_ndesc_handler { 6697 IFLIB_NTXD_HANDLER, 6698 IFLIB_NRXD_HANDLER, 6699 }; 6700 6701 static int 6702 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6703 { 6704 if_ctx_t ctx = (void *)arg1; 6705 enum iflib_ndesc_handler type = arg2; 6706 char buf[256] = {0}; 6707 qidx_t *ndesc; 6708 char *p, *next; 6709 int nqs, rc, i; 6710 6711 nqs = 8; 6712 switch (type) { 6713 case IFLIB_NTXD_HANDLER: 6714 ndesc = ctx->ifc_sysctl_ntxds; 6715 if (ctx->ifc_sctx) 6716 nqs = ctx->ifc_sctx->isc_ntxqs; 6717 break; 6718 case IFLIB_NRXD_HANDLER: 6719 ndesc = ctx->ifc_sysctl_nrxds; 6720 if (ctx->ifc_sctx) 6721 nqs = ctx->ifc_sctx->isc_nrxqs; 6722 break; 6723 default: 6724 printf("%s: unhandled type\n", __func__); 6725 return (EINVAL); 6726 } 6727 if (nqs == 0) 6728 nqs = 8; 6729 6730 for (i = 0; i < 8; i++) { 6731 if (i >= nqs) 6732 break; 6733 if (i) 6734 strcat(buf, ","); 6735 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6736 } 6737 6738 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6739 if (rc || req->newptr == NULL) 6740 return (rc); 6741 6742 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6743 i++, p = strsep(&next, " ,")) { 6744 ndesc[i] = strtoul(p, NULL, 10); 6745 } 6746 6747 return (rc); 6748 } 6749 6750 #define NAME_BUFLEN 32 6751 static void 6752 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6753 { 6754 device_t dev = iflib_get_dev(ctx); 6755 struct sysctl_oid_list *child, *oid_list; 6756 struct sysctl_ctx_list *ctx_list; 6757 struct sysctl_oid *node; 6758 6759 ctx_list = device_get_sysctl_ctx(dev); 6760 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6761 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, 6762 OID_AUTO, "iflib", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 6763 "IFLIB fields"); 6764 oid_list = SYSCTL_CHILDREN(node); 6765 6766 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6767 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, "driver version"); 6768 6769 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6770 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6771 "# of txqs to use, 0 => use default #"); 6772 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6773 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6774 "# of rxqs to use, 0 => use default #"); 6775 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6776 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6777 "permit #txq != #rxq"); 6778 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6779 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6780 "disable MSI-X (default 0)"); 6781 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6782 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, "set the RX budget"); 6783 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6784 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6785 "cause TX to abdicate instead of running to completion"); 6786 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6787 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6788 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6789 "offset to start using cores at"); 6790 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6791 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6792 "use separate cores for TX and RX"); 6793 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "use_logical_cores", 6794 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0, 6795 "try to make use of logical cores for TX and RX"); 6796 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "use_extra_msix_vectors", 6797 CTLFLAG_RDTUN, &ctx->ifc_sysctl_extra_msix_vectors, 0, 6798 "attempt to reserve the given number of extra MSI-X vectors during driver load for the creation of additional interfaces later"); 6799 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "allocated_msix_vectors", 6800 CTLFLAG_RDTUN, &ctx->ifc_softc_ctx.isc_vectors, 0, 6801 "total # of MSI-X vectors allocated by driver"); 6802 6803 /* XXX change for per-queue sizes */ 6804 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6805 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6806 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6807 "list of # of TX descriptors to use, 0 = use default #"); 6808 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6809 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6810 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6811 "list of # of RX descriptors to use, 0 = use default #"); 6812 } 6813 6814 static void 6815 iflib_add_device_sysctl_post(if_ctx_t ctx) 6816 { 6817 if_shared_ctx_t sctx = ctx->ifc_sctx; 6818 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6819 device_t dev = iflib_get_dev(ctx); 6820 struct sysctl_oid_list *child; 6821 struct sysctl_ctx_list *ctx_list; 6822 iflib_fl_t fl; 6823 iflib_txq_t txq; 6824 iflib_rxq_t rxq; 6825 int i, j; 6826 char namebuf[NAME_BUFLEN]; 6827 char *qfmt; 6828 struct sysctl_oid *queue_node, *fl_node, *node; 6829 struct sysctl_oid_list *queue_list, *fl_list; 6830 ctx_list = device_get_sysctl_ctx(dev); 6831 6832 node = ctx->ifc_sysctl_node; 6833 child = SYSCTL_CHILDREN(node); 6834 6835 if (scctx->isc_ntxqsets > 100) 6836 qfmt = "txq%03d"; 6837 else if (scctx->isc_ntxqsets > 10) 6838 qfmt = "txq%02d"; 6839 else 6840 qfmt = "txq%d"; 6841 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6842 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6843 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6844 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6845 queue_list = SYSCTL_CHILDREN(queue_node); 6846 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 6847 CTLFLAG_RD, &txq->ift_task.gt_cpu, 0, 6848 "cpu this queue is bound to"); 6849 #if MEMORY_LOGGING 6850 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6851 CTLFLAG_RD, &txq->ift_dequeued, "total mbufs freed"); 6852 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6853 CTLFLAG_RD, &txq->ift_enqueued, "total mbufs enqueued"); 6854 #endif 6855 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6856 CTLFLAG_RD, &txq->ift_mbuf_defrag, 6857 "# of times m_defrag was called"); 6858 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6859 CTLFLAG_RD, &txq->ift_pullups, 6860 "# of times m_pullup was called"); 6861 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 6862 "mbuf_defrag_failed", CTLFLAG_RD, 6863 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6864 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 6865 "no_desc_avail", CTLFLAG_RD, &txq->ift_no_desc_avail, 6866 "# of times no descriptors were available"); 6867 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 6868 "tx_map_failed", CTLFLAG_RD, &txq->ift_map_failed, 6869 "# of times DMA map failed"); 6870 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 6871 "txd_encap_efbig", CTLFLAG_RD, &txq->ift_txd_encap_efbig, 6872 "# of times txd_encap returned EFBIG"); 6873 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 6874 "no_tx_dma_setup", CTLFLAG_RD, &txq->ift_no_tx_dma_setup, 6875 "# of times map failed for other than EFBIG"); 6876 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6877 CTLFLAG_RD, &txq->ift_pidx, 1, "Producer Index"); 6878 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6879 CTLFLAG_RD, &txq->ift_cidx, 1, "Consumer Index"); 6880 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, 6881 "txq_cidx_processed", CTLFLAG_RD, &txq->ift_cidx_processed, 6882 1, "Consumer Index seen by credit update"); 6883 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6884 CTLFLAG_RD, &txq->ift_in_use, 1, "descriptors in use"); 6885 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 6886 "txq_processed", CTLFLAG_RD, &txq->ift_processed, 6887 "descriptors procesed for clean"); 6888 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6889 CTLFLAG_RD, &txq->ift_cleaned, "total cleaned"); 6890 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6891 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6892 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6893 mp_ring_state_handler, "A", "soft ring state"); 6894 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 6895 "r_enqueues", CTLFLAG_RD, &txq->ift_br->enqueues, 6896 "# of enqueues to the mp_ring for this queue"); 6897 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 6898 "r_drops", CTLFLAG_RD, &txq->ift_br->drops, 6899 "# of drops in the mp_ring for this queue"); 6900 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 6901 "r_starts", CTLFLAG_RD, &txq->ift_br->starts, 6902 "# of normal consumer starts in mp_ring for this queue"); 6903 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 6904 "r_stalls", CTLFLAG_RD, &txq->ift_br->stalls, 6905 "# of consumer stalls in the mp_ring for this queue"); 6906 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 6907 "r_restarts", CTLFLAG_RD, &txq->ift_br->restarts, 6908 "# of consumer restarts in the mp_ring for this queue"); 6909 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 6910 "r_abdications", CTLFLAG_RD, &txq->ift_br->abdications, 6911 "# of consumer abdications in the mp_ring for this queue"); 6912 } 6913 6914 if (scctx->isc_nrxqsets > 100) 6915 qfmt = "rxq%03d"; 6916 else if (scctx->isc_nrxqsets > 10) 6917 qfmt = "rxq%02d"; 6918 else 6919 qfmt = "rxq%d"; 6920 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6921 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6922 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6923 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6924 queue_list = SYSCTL_CHILDREN(queue_node); 6925 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 6926 CTLFLAG_RD, &rxq->ifr_task.gt_cpu, 0, 6927 "cpu this queue is bound to"); 6928 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6929 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, 6930 "rxq_cq_cidx", CTLFLAG_RD, &rxq->ifr_cq_cidx, 1, 6931 "Consumer Index"); 6932 } 6933 6934 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6935 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6936 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, 6937 OID_AUTO, namebuf, CTLFLAG_RD | CTLFLAG_MPSAFE, 6938 NULL, "freelist Name"); 6939 fl_list = SYSCTL_CHILDREN(fl_node); 6940 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6941 CTLFLAG_RD, &fl->ifl_pidx, 1, "Producer Index"); 6942 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6943 CTLFLAG_RD, &fl->ifl_cidx, 1, "Consumer Index"); 6944 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6945 CTLFLAG_RD, &fl->ifl_credits, 1, 6946 "credits available"); 6947 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 6948 CTLFLAG_RD, &fl->ifl_buf_size, 1, "buffer size"); 6949 #if MEMORY_LOGGING 6950 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 6951 "fl_m_enqueued", CTLFLAG_RD, &fl->ifl_m_enqueued, 6952 "mbufs allocated"); 6953 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 6954 "fl_m_dequeued", CTLFLAG_RD, &fl->ifl_m_dequeued, 6955 "mbufs freed"); 6956 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 6957 "fl_cl_enqueued", CTLFLAG_RD, &fl->ifl_cl_enqueued, 6958 "clusters allocated"); 6959 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 6960 "fl_cl_dequeued", CTLFLAG_RD, &fl->ifl_cl_dequeued, 6961 "clusters freed"); 6962 #endif 6963 } 6964 } 6965 6966 } 6967 6968 void 6969 iflib_request_reset(if_ctx_t ctx) 6970 { 6971 6972 STATE_LOCK(ctx); 6973 ctx->ifc_flags |= IFC_DO_RESET; 6974 STATE_UNLOCK(ctx); 6975 } 6976 6977 #ifndef __NO_STRICT_ALIGNMENT 6978 static struct mbuf * 6979 iflib_fixup_rx(struct mbuf *m) 6980 { 6981 struct mbuf *n; 6982 6983 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6984 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6985 m->m_data += ETHER_HDR_LEN; 6986 n = m; 6987 } else { 6988 MGETHDR(n, M_NOWAIT, MT_DATA); 6989 if (n == NULL) { 6990 m_freem(m); 6991 return (NULL); 6992 } 6993 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6994 m->m_data += ETHER_HDR_LEN; 6995 m->m_len -= ETHER_HDR_LEN; 6996 n->m_len = ETHER_HDR_LEN; 6997 M_MOVE_PKTHDR(n, m); 6998 n->m_next = m; 6999 } 7000 return (n); 7001 } 7002 #endif 7003 7004 #ifdef DEBUGNET 7005 static void 7006 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 7007 { 7008 if_ctx_t ctx; 7009 7010 ctx = if_getsoftc(ifp); 7011 CTX_LOCK(ctx); 7012 *nrxr = NRXQSETS(ctx); 7013 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 7014 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 7015 CTX_UNLOCK(ctx); 7016 } 7017 7018 static void 7019 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 7020 { 7021 if_ctx_t ctx; 7022 if_softc_ctx_t scctx; 7023 iflib_fl_t fl; 7024 iflib_rxq_t rxq; 7025 int i, j; 7026 7027 ctx = if_getsoftc(ifp); 7028 scctx = &ctx->ifc_softc_ctx; 7029 7030 switch (event) { 7031 case DEBUGNET_START: 7032 for (i = 0; i < scctx->isc_nrxqsets; i++) { 7033 rxq = &ctx->ifc_rxqs[i]; 7034 for (j = 0; j < rxq->ifr_nfl; j++) { 7035 fl = rxq->ifr_fl; 7036 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 7037 } 7038 } 7039 iflib_no_tx_batch = 1; 7040 break; 7041 default: 7042 break; 7043 } 7044 } 7045 7046 static int 7047 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 7048 { 7049 if_ctx_t ctx; 7050 iflib_txq_t txq; 7051 int error; 7052 7053 ctx = if_getsoftc(ifp); 7054 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7055 IFF_DRV_RUNNING) 7056 return (EBUSY); 7057 7058 txq = &ctx->ifc_txqs[0]; 7059 error = iflib_encap(txq, &m); 7060 if (error == 0) 7061 (void)iflib_txd_db_check(txq, true); 7062 return (error); 7063 } 7064 7065 static int 7066 iflib_debugnet_poll(if_t ifp, int count) 7067 { 7068 struct epoch_tracker et; 7069 if_ctx_t ctx; 7070 if_softc_ctx_t scctx; 7071 iflib_txq_t txq; 7072 int i; 7073 7074 ctx = if_getsoftc(ifp); 7075 scctx = &ctx->ifc_softc_ctx; 7076 7077 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7078 IFF_DRV_RUNNING) 7079 return (EBUSY); 7080 7081 txq = &ctx->ifc_txqs[0]; 7082 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 7083 7084 NET_EPOCH_ENTER(et); 7085 for (i = 0; i < scctx->isc_nrxqsets; i++) 7086 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 7087 NET_EPOCH_EXIT(et); 7088 return (0); 7089 } 7090 #endif /* DEBUGNET */ 7091