1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include "opt_inet.h" 30 #include "opt_inet6.h" 31 #include "opt_acpi.h" 32 #include "opt_sched.h" 33 34 #include <sys/param.h> 35 #include <sys/types.h> 36 #include <sys/bus.h> 37 #include <sys/eventhandler.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/module.h> 42 #include <sys/kobj.h> 43 #include <sys/rman.h> 44 #include <sys/sbuf.h> 45 #include <sys/smp.h> 46 #include <sys/socket.h> 47 #include <sys/sockio.h> 48 #include <sys/sysctl.h> 49 #include <sys/syslog.h> 50 #include <sys/taskqueue.h> 51 #include <sys/limits.h> 52 53 #include <net/if.h> 54 #include <net/if_var.h> 55 #include <net/if_private.h> 56 #include <net/if_types.h> 57 #include <net/if_media.h> 58 #include <net/bpf.h> 59 #include <net/ethernet.h> 60 #include <net/mp_ring.h> 61 #include <net/debugnet.h> 62 #include <net/pfil.h> 63 #include <net/vnet.h> 64 65 #include <netinet/in.h> 66 #include <netinet/in_pcb.h> 67 #include <netinet/tcp_lro.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/if_ether.h> 70 #include <netinet/ip.h> 71 #include <netinet/ip6.h> 72 #include <netinet/tcp.h> 73 #include <netinet/ip_var.h> 74 #include <netinet6/ip6_var.h> 75 76 #include <machine/bus.h> 77 #include <machine/in_cksum.h> 78 79 #include <vm/vm.h> 80 #include <vm/pmap.h> 81 82 #include <dev/led/led.h> 83 #include <dev/pci/pcireg.h> 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pci_private.h> 86 87 #include <net/iflib.h> 88 89 #include "ifdi_if.h" 90 91 #ifdef PCI_IOV 92 #include <dev/pci/pci_iov.h> 93 #endif 94 95 #include <sys/bitstring.h> 96 /* 97 * enable accounting of every mbuf as it comes in to and goes out of 98 * iflib's software descriptor references 99 */ 100 #define MEMORY_LOGGING 0 101 /* 102 * Enable mbuf vectors for compressing long mbuf chains 103 */ 104 105 /* 106 * NB: 107 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 108 * we prefetch needs to be determined by the time spent in m_free vis a vis 109 * the cost of a prefetch. This will of course vary based on the workload: 110 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 111 * is quite expensive, thus suggesting very little prefetch. 112 * - small packet forwarding which is just returning a single mbuf to 113 * UMA will typically be very fast vis a vis the cost of a memory 114 * access. 115 */ 116 117 /* 118 * File organization: 119 * - private structures 120 * - iflib private utility functions 121 * - ifnet functions 122 * - vlan registry and other exported functions 123 * - iflib public core functions 124 * 125 * 126 */ 127 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 128 129 #define IFLIB_RXEOF_MORE (1U << 0) 130 #define IFLIB_RXEOF_EMPTY (2U << 0) 131 132 struct iflib_txq; 133 typedef struct iflib_txq *iflib_txq_t; 134 struct iflib_rxq; 135 typedef struct iflib_rxq *iflib_rxq_t; 136 struct iflib_fl; 137 typedef struct iflib_fl *iflib_fl_t; 138 139 struct iflib_ctx; 140 141 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 142 static void iflib_timer(void *arg); 143 static void iflib_tqg_detach(if_ctx_t ctx); 144 145 typedef struct iflib_filter_info { 146 driver_filter_t *ifi_filter; 147 void *ifi_filter_arg; 148 struct grouptask *ifi_task; 149 void *ifi_ctx; 150 } *iflib_filter_info_t; 151 152 struct iflib_ctx { 153 KOBJ_FIELDS; 154 /* 155 * Pointer to hardware driver's softc 156 */ 157 void *ifc_softc; 158 device_t ifc_dev; 159 if_t ifc_ifp; 160 161 cpuset_t ifc_cpus; 162 if_shared_ctx_t ifc_sctx; 163 struct if_softc_ctx ifc_softc_ctx; 164 165 struct sx ifc_ctx_sx; 166 struct mtx ifc_state_mtx; 167 168 iflib_txq_t ifc_txqs; 169 iflib_rxq_t ifc_rxqs; 170 uint32_t ifc_if_flags; 171 uint32_t ifc_flags; 172 uint32_t ifc_max_fl_buf_size; 173 uint32_t ifc_rx_mbuf_sz; 174 175 int ifc_link_state; 176 int ifc_watchdog_events; 177 struct cdev *ifc_led_dev; 178 struct resource *ifc_msix_mem; 179 180 struct if_irq ifc_legacy_irq; 181 struct grouptask ifc_admin_task; 182 struct grouptask ifc_vflr_task; 183 struct iflib_filter_info ifc_filter_info; 184 struct ifmedia ifc_media; 185 struct ifmedia *ifc_mediap; 186 187 struct sysctl_oid *ifc_sysctl_node; 188 uint16_t ifc_sysctl_ntxqs; 189 uint16_t ifc_sysctl_nrxqs; 190 uint16_t ifc_sysctl_qs_eq_override; 191 uint16_t ifc_sysctl_rx_budget; 192 uint16_t ifc_sysctl_tx_abdicate; 193 uint16_t ifc_sysctl_core_offset; 194 #define CORE_OFFSET_UNSPECIFIED 0xffff 195 uint8_t ifc_sysctl_separate_txrx; 196 uint8_t ifc_sysctl_use_logical_cores; 197 bool ifc_cpus_are_physical_cores; 198 199 qidx_t ifc_sysctl_ntxds[8]; 200 qidx_t ifc_sysctl_nrxds[8]; 201 struct if_txrx ifc_txrx; 202 #define isc_txd_encap ifc_txrx.ift_txd_encap 203 #define isc_txd_flush ifc_txrx.ift_txd_flush 204 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 205 #define isc_rxd_available ifc_txrx.ift_rxd_available 206 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 209 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 210 #define isc_txq_select ifc_txrx.ift_txq_select 211 #define isc_txq_select_v2 ifc_txrx.ift_txq_select_v2 212 213 eventhandler_tag ifc_vlan_attach_event; 214 eventhandler_tag ifc_vlan_detach_event; 215 struct ether_addr ifc_mac; 216 }; 217 218 void * 219 iflib_get_softc(if_ctx_t ctx) 220 { 221 222 return (ctx->ifc_softc); 223 } 224 225 device_t 226 iflib_get_dev(if_ctx_t ctx) 227 { 228 229 return (ctx->ifc_dev); 230 } 231 232 if_t 233 iflib_get_ifp(if_ctx_t ctx) 234 { 235 236 return (ctx->ifc_ifp); 237 } 238 239 struct ifmedia * 240 iflib_get_media(if_ctx_t ctx) 241 { 242 243 return (ctx->ifc_mediap); 244 } 245 246 void 247 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 248 { 249 250 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 251 } 252 253 if_softc_ctx_t 254 iflib_get_softc_ctx(if_ctx_t ctx) 255 { 256 257 return (&ctx->ifc_softc_ctx); 258 } 259 260 if_shared_ctx_t 261 iflib_get_sctx(if_ctx_t ctx) 262 { 263 264 return (ctx->ifc_sctx); 265 } 266 267 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 268 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 269 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 270 271 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 272 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 273 274 typedef struct iflib_sw_rx_desc_array { 275 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 276 struct mbuf **ifsd_m; /* pkthdr mbufs */ 277 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 278 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 279 } iflib_rxsd_array_t; 280 281 typedef struct iflib_sw_tx_desc_array { 282 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 283 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 284 struct mbuf **ifsd_m; /* pkthdr mbufs */ 285 } if_txsd_vec_t; 286 287 /* magic number that should be high enough for any hardware */ 288 #define IFLIB_MAX_TX_SEGS 128 289 #define IFLIB_RX_COPY_THRESH 128 290 #define IFLIB_MAX_RX_REFRESH 32 291 /* The minimum descriptors per second before we start coalescing */ 292 #define IFLIB_MIN_DESC_SEC 16384 293 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 294 #define IFLIB_QUEUE_IDLE 0 295 #define IFLIB_QUEUE_HUNG 1 296 #define IFLIB_QUEUE_WORKING 2 297 /* maximum number of txqs that can share an rx interrupt */ 298 #define IFLIB_MAX_TX_SHARED_INTR 4 299 300 /* this should really scale with ring size - this is a fairly arbitrary value */ 301 #define TX_BATCH_SIZE 32 302 303 #define IFLIB_RESTART_BUDGET 8 304 305 #define IFC_LEGACY 0x001 306 #define IFC_QFLUSH 0x002 307 #define IFC_MULTISEG 0x004 308 #define IFC_SPARE1 0x008 309 #define IFC_SC_ALLOCATED 0x010 310 #define IFC_INIT_DONE 0x020 311 #define IFC_PREFETCH 0x040 312 #define IFC_DO_RESET 0x080 313 #define IFC_DO_WATCHDOG 0x100 314 #define IFC_SPARE0 0x200 315 #define IFC_SPARE2 0x400 316 #define IFC_IN_DETACH 0x800 317 318 #define IFC_NETMAP_TX_IRQ 0x80000000 319 320 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 321 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 322 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 323 324 struct iflib_txq { 325 qidx_t ift_in_use; 326 qidx_t ift_cidx; 327 qidx_t ift_cidx_processed; 328 qidx_t ift_pidx; 329 uint8_t ift_gen; 330 uint8_t ift_br_offset; 331 uint16_t ift_npending; 332 uint16_t ift_db_pending; 333 uint16_t ift_rs_pending; 334 /* implicit pad */ 335 uint8_t ift_txd_size[8]; 336 uint64_t ift_processed; 337 uint64_t ift_cleaned; 338 uint64_t ift_cleaned_prev; 339 #if MEMORY_LOGGING 340 uint64_t ift_enqueued; 341 uint64_t ift_dequeued; 342 #endif 343 uint64_t ift_no_tx_dma_setup; 344 uint64_t ift_no_desc_avail; 345 uint64_t ift_mbuf_defrag_failed; 346 uint64_t ift_mbuf_defrag; 347 uint64_t ift_map_failed; 348 uint64_t ift_txd_encap_efbig; 349 uint64_t ift_pullups; 350 uint64_t ift_last_timer_tick; 351 352 struct mtx ift_mtx; 353 struct mtx ift_db_mtx; 354 355 /* constant values */ 356 if_ctx_t ift_ctx; 357 struct ifmp_ring *ift_br; 358 struct grouptask ift_task; 359 qidx_t ift_size; 360 uint16_t ift_id; 361 struct callout ift_timer; 362 #ifdef DEV_NETMAP 363 struct callout ift_netmap_timer; 364 #endif /* DEV_NETMAP */ 365 366 if_txsd_vec_t ift_sds; 367 uint8_t ift_qstatus; 368 uint8_t ift_closed; 369 uint8_t ift_update_freq; 370 struct iflib_filter_info ift_filter_info; 371 bus_dma_tag_t ift_buf_tag; 372 bus_dma_tag_t ift_tso_buf_tag; 373 iflib_dma_info_t ift_ifdi; 374 #define MTX_NAME_LEN 32 375 char ift_mtx_name[MTX_NAME_LEN]; 376 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 377 #ifdef IFLIB_DIAGNOSTICS 378 uint64_t ift_cpu_exec_count[256]; 379 #endif 380 } __aligned(CACHE_LINE_SIZE); 381 382 struct iflib_fl { 383 qidx_t ifl_cidx; 384 qidx_t ifl_pidx; 385 qidx_t ifl_credits; 386 uint8_t ifl_gen; 387 uint8_t ifl_rxd_size; 388 #if MEMORY_LOGGING 389 uint64_t ifl_m_enqueued; 390 uint64_t ifl_m_dequeued; 391 uint64_t ifl_cl_enqueued; 392 uint64_t ifl_cl_dequeued; 393 #endif 394 /* implicit pad */ 395 bitstr_t *ifl_rx_bitmap; 396 qidx_t ifl_fragidx; 397 /* constant */ 398 qidx_t ifl_size; 399 uint16_t ifl_buf_size; 400 uint16_t ifl_cltype; 401 uma_zone_t ifl_zone; 402 iflib_rxsd_array_t ifl_sds; 403 iflib_rxq_t ifl_rxq; 404 uint8_t ifl_id; 405 bus_dma_tag_t ifl_buf_tag; 406 iflib_dma_info_t ifl_ifdi; 407 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 408 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 409 } __aligned(CACHE_LINE_SIZE); 410 411 static inline qidx_t 412 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 413 { 414 qidx_t used; 415 416 if (pidx > cidx) 417 used = pidx - cidx; 418 else if (pidx < cidx) 419 used = size - cidx + pidx; 420 else if (gen == 0 && pidx == cidx) 421 used = 0; 422 else if (gen == 1 && pidx == cidx) 423 used = size; 424 else 425 panic("bad state"); 426 427 return (used); 428 } 429 430 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 431 432 #define IDXDIFF(head, tail, wrap) \ 433 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 434 435 struct iflib_rxq { 436 if_ctx_t ifr_ctx; 437 iflib_fl_t ifr_fl; 438 uint64_t ifr_rx_irq; 439 struct pfil_head *pfil; 440 /* 441 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 442 * the completion queue consumer index. Otherwise it's unused. 443 */ 444 qidx_t ifr_cq_cidx; 445 uint16_t ifr_id; 446 uint8_t ifr_nfl; 447 uint8_t ifr_ntxqirq; 448 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 449 uint8_t ifr_fl_offset; 450 struct lro_ctrl ifr_lc; 451 struct grouptask ifr_task; 452 struct callout ifr_watchdog; 453 struct iflib_filter_info ifr_filter_info; 454 iflib_dma_info_t ifr_ifdi; 455 456 /* dynamically allocate if any drivers need a value substantially larger than this */ 457 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 458 #ifdef IFLIB_DIAGNOSTICS 459 uint64_t ifr_cpu_exec_count[256]; 460 #endif 461 } __aligned(CACHE_LINE_SIZE); 462 463 typedef struct if_rxsd { 464 caddr_t *ifsd_cl; 465 iflib_fl_t ifsd_fl; 466 } *if_rxsd_t; 467 468 /* multiple of word size */ 469 #ifdef __LP64__ 470 #define PKT_INFO_SIZE 6 471 #define RXD_INFO_SIZE 5 472 #define PKT_TYPE uint64_t 473 #else 474 #define PKT_INFO_SIZE 11 475 #define RXD_INFO_SIZE 8 476 #define PKT_TYPE uint32_t 477 #endif 478 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 479 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 480 481 typedef struct if_pkt_info_pad { 482 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 483 } *if_pkt_info_pad_t; 484 typedef struct if_rxd_info_pad { 485 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 486 } *if_rxd_info_pad_t; 487 488 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 489 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 490 491 static inline void 492 pkt_info_zero(if_pkt_info_t pi) 493 { 494 if_pkt_info_pad_t pi_pad; 495 496 pi_pad = (if_pkt_info_pad_t)pi; 497 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 498 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 499 #ifndef __LP64__ 500 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 501 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 502 #endif 503 } 504 505 static inline void 506 rxd_info_zero(if_rxd_info_t ri) 507 { 508 if_rxd_info_pad_t ri_pad; 509 int i; 510 511 ri_pad = (if_rxd_info_pad_t)ri; 512 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 513 ri_pad->rxd_val[i] = 0; 514 ri_pad->rxd_val[i+1] = 0; 515 ri_pad->rxd_val[i+2] = 0; 516 ri_pad->rxd_val[i+3] = 0; 517 } 518 #ifdef __LP64__ 519 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 520 #endif 521 } 522 523 /* 524 * Only allow a single packet to take up most 1/nth of the tx ring 525 */ 526 #define MAX_SINGLE_PACKET_FRACTION 12 527 #define IF_BAD_DMA (bus_addr_t)-1 528 529 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 530 531 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 532 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 533 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 534 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 535 536 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 537 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 538 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 539 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 540 541 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 542 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 543 544 /* Our boot-time initialization hook */ 545 static int iflib_module_event_handler(module_t, int, void *); 546 547 static moduledata_t iflib_moduledata = { 548 "iflib", 549 iflib_module_event_handler, 550 NULL 551 }; 552 553 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 554 MODULE_VERSION(iflib, 1); 555 556 MODULE_DEPEND(iflib, pci, 1, 1, 1); 557 MODULE_DEPEND(iflib, ether, 1, 1, 1); 558 559 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 560 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 561 562 #ifndef IFLIB_DEBUG_COUNTERS 563 #ifdef INVARIANTS 564 #define IFLIB_DEBUG_COUNTERS 1 565 #else 566 #define IFLIB_DEBUG_COUNTERS 0 567 #endif /* !INVARIANTS */ 568 #endif 569 570 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 571 "iflib driver parameters"); 572 573 /* 574 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 575 */ 576 static int iflib_min_tx_latency = 0; 577 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 578 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 579 static int iflib_no_tx_batch = 0; 580 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 581 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 582 static int iflib_timer_default = 1000; 583 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW, 584 &iflib_timer_default, 0, "number of ticks between iflib_timer calls"); 585 586 587 #if IFLIB_DEBUG_COUNTERS 588 589 static int iflib_tx_seen; 590 static int iflib_tx_sent; 591 static int iflib_tx_encap; 592 static int iflib_rx_allocs; 593 static int iflib_fl_refills; 594 static int iflib_fl_refills_large; 595 static int iflib_tx_frees; 596 597 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 598 &iflib_tx_seen, 0, "# TX mbufs seen"); 599 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 600 &iflib_tx_sent, 0, "# TX mbufs sent"); 601 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 602 &iflib_tx_encap, 0, "# TX mbufs encapped"); 603 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 604 &iflib_tx_frees, 0, "# TX frees"); 605 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 606 &iflib_rx_allocs, 0, "# RX allocations"); 607 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 608 &iflib_fl_refills, 0, "# refills"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 610 &iflib_fl_refills_large, 0, "# large refills"); 611 612 static int iflib_txq_drain_flushing; 613 static int iflib_txq_drain_oactive; 614 static int iflib_txq_drain_notready; 615 616 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 617 &iflib_txq_drain_flushing, 0, "# drain flushes"); 618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 619 &iflib_txq_drain_oactive, 0, "# drain oactives"); 620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 621 &iflib_txq_drain_notready, 0, "# drain notready"); 622 623 static int iflib_encap_load_mbuf_fail; 624 static int iflib_encap_pad_mbuf_fail; 625 static int iflib_encap_txq_avail_fail; 626 static int iflib_encap_txd_encap_fail; 627 628 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 629 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 630 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 631 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 632 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 633 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 634 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 635 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 636 637 static int iflib_task_fn_rxs; 638 static int iflib_rx_intr_enables; 639 static int iflib_fast_intrs; 640 static int iflib_rx_unavail; 641 static int iflib_rx_ctx_inactive; 642 static int iflib_rx_if_input; 643 static int iflib_rxd_flush; 644 645 static int iflib_verbose_debug; 646 647 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 648 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 649 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 650 &iflib_rx_intr_enables, 0, "# RX intr enables"); 651 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 652 &iflib_fast_intrs, 0, "# fast_intr calls"); 653 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 654 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 655 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 656 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 657 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 658 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 660 &iflib_rxd_flush, 0, "# times rxd_flush called"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 662 &iflib_verbose_debug, 0, "enable verbose debugging"); 663 664 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 665 static void 666 iflib_debug_reset(void) 667 { 668 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 669 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 670 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 671 iflib_txq_drain_notready = 672 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 673 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 674 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 675 iflib_rx_unavail = 676 iflib_rx_ctx_inactive = iflib_rx_if_input = 677 iflib_rxd_flush = 0; 678 } 679 680 #else 681 #define DBG_COUNTER_INC(name) 682 static void iflib_debug_reset(void) {} 683 #endif 684 685 #define IFLIB_DEBUG 0 686 687 static void iflib_tx_structures_free(if_ctx_t ctx); 688 static void iflib_rx_structures_free(if_ctx_t ctx); 689 static int iflib_queues_alloc(if_ctx_t ctx); 690 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 691 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 692 static int iflib_qset_structures_setup(if_ctx_t ctx); 693 static int iflib_msix_init(if_ctx_t ctx); 694 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 695 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 696 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 697 #ifdef ALTQ 698 static void iflib_altq_if_start(if_t ifp); 699 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 700 #endif 701 static int iflib_register(if_ctx_t); 702 static void iflib_deregister(if_ctx_t); 703 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 704 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 705 static void iflib_init_locked(if_ctx_t ctx); 706 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 707 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 708 static void iflib_ifmp_purge(iflib_txq_t txq); 709 static void _iflib_pre_assert(if_softc_ctx_t scctx); 710 static void iflib_stop(if_ctx_t ctx); 711 static void iflib_if_init_locked(if_ctx_t ctx); 712 static void iflib_free_intr_mem(if_ctx_t ctx); 713 #ifndef __NO_STRICT_ALIGNMENT 714 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 715 #endif 716 717 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 718 SLIST_HEAD_INITIALIZER(cpu_offsets); 719 struct cpu_offset { 720 SLIST_ENTRY(cpu_offset) entries; 721 cpuset_t set; 722 unsigned int refcount; 723 uint16_t next_cpuid; 724 }; 725 static struct mtx cpu_offset_mtx; 726 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 727 MTX_DEF); 728 729 DEBUGNET_DEFINE(iflib); 730 731 static int 732 iflib_num_rx_descs(if_ctx_t ctx) 733 { 734 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 735 if_shared_ctx_t sctx = ctx->ifc_sctx; 736 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 737 738 return scctx->isc_nrxd[first_rxq]; 739 } 740 741 static int 742 iflib_num_tx_descs(if_ctx_t ctx) 743 { 744 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 745 if_shared_ctx_t sctx = ctx->ifc_sctx; 746 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 747 748 return scctx->isc_ntxd[first_txq]; 749 } 750 751 #ifdef DEV_NETMAP 752 #include <sys/selinfo.h> 753 #include <net/netmap.h> 754 #include <dev/netmap/netmap_kern.h> 755 756 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 757 758 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 759 static void iflib_netmap_timer(void *arg); 760 761 /* 762 * device-specific sysctl variables: 763 * 764 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 765 * During regular operations the CRC is stripped, but on some 766 * hardware reception of frames not multiple of 64 is slower, 767 * so using crcstrip=0 helps in benchmarks. 768 * 769 * iflib_rx_miss, iflib_rx_miss_bufs: 770 * count packets that might be missed due to lost interrupts. 771 */ 772 SYSCTL_DECL(_dev_netmap); 773 /* 774 * The xl driver by default strips CRCs and we do not override it. 775 */ 776 777 int iflib_crcstrip = 1; 778 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 779 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 780 781 int iflib_rx_miss, iflib_rx_miss_bufs; 782 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 783 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 784 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 785 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 786 787 /* 788 * Register/unregister. We are already under netmap lock. 789 * Only called on the first register or the last unregister. 790 */ 791 static int 792 iflib_netmap_register(struct netmap_adapter *na, int onoff) 793 { 794 if_t ifp = na->ifp; 795 if_ctx_t ctx = if_getsoftc(ifp); 796 int status; 797 798 CTX_LOCK(ctx); 799 if (!CTX_IS_VF(ctx)) 800 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 801 802 iflib_stop(ctx); 803 804 /* 805 * Enable (or disable) netmap flags, and intercept (or restore) 806 * ifp->if_transmit. This is done once the device has been stopped 807 * to prevent race conditions. Also, this must be done after 808 * calling netmap_disable_all_rings() and before calling 809 * netmap_enable_all_rings(), so that these two functions see the 810 * updated state of the NAF_NETMAP_ON bit. 811 */ 812 if (onoff) { 813 nm_set_native_flags(na); 814 } else { 815 nm_clear_native_flags(na); 816 } 817 818 iflib_init_locked(ctx); 819 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 820 status = if_getdrvflags(ifp) & IFF_DRV_RUNNING ? 0 : 1; 821 if (status) 822 nm_clear_native_flags(na); 823 CTX_UNLOCK(ctx); 824 return (status); 825 } 826 827 static int 828 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info) 829 { 830 if_t ifp = na->ifp; 831 if_ctx_t ctx = if_getsoftc(ifp); 832 iflib_rxq_t rxq = &ctx->ifc_rxqs[0]; 833 iflib_fl_t fl = &rxq->ifr_fl[0]; 834 835 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 836 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 837 info->num_tx_descs = iflib_num_tx_descs(ctx); 838 info->num_rx_descs = iflib_num_rx_descs(ctx); 839 info->rx_buf_maxsize = fl->ifl_buf_size; 840 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u", 841 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs, 842 info->num_rx_descs, info->rx_buf_maxsize); 843 844 return 0; 845 } 846 847 static int 848 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 849 { 850 struct netmap_adapter *na = kring->na; 851 u_int const lim = kring->nkr_num_slots - 1; 852 struct netmap_ring *ring = kring->ring; 853 bus_dmamap_t *map; 854 struct if_rxd_update iru; 855 if_ctx_t ctx = rxq->ifr_ctx; 856 iflib_fl_t fl = &rxq->ifr_fl[0]; 857 u_int nic_i_first, nic_i; 858 u_int nm_i; 859 int i, n; 860 #if IFLIB_DEBUG_COUNTERS 861 int rf_count = 0; 862 #endif 863 864 /* 865 * This function is used both at initialization and in rxsync. 866 * At initialization we need to prepare (with isc_rxd_refill()) 867 * all the netmap buffers currently owned by the kernel, in 868 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync 869 * (except for kring->nkr_hwofs). These may be less than 870 * kring->nkr_num_slots if netmap_reset() was called while 871 * an application using the kring that still owned some 872 * buffers. 873 * At rxsync time, both indexes point to the next buffer to be 874 * refilled. 875 * In any case we publish (with isc_rxd_flush()) up to 876 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 877 * pointer to overrun the head/cons pointer, although this is 878 * not necessary for some NICs (e.g. vmx). 879 */ 880 if (__predict_false(init)) { 881 n = kring->nkr_num_slots - nm_kr_rxspace(kring); 882 } else { 883 n = kring->rhead - kring->nr_hwcur; 884 if (n == 0) 885 return (0); /* Nothing to do. */ 886 if (n < 0) 887 n += kring->nkr_num_slots; 888 } 889 890 iru_init(&iru, rxq, 0 /* flid */); 891 map = fl->ifl_sds.ifsd_map; 892 nic_i = fl->ifl_pidx; 893 nm_i = netmap_idx_n2k(kring, nic_i); 894 if (__predict_false(init)) { 895 /* 896 * On init/reset, nic_i must be 0, and we must 897 * start to refill from hwtail (see netmap_reset()). 898 */ 899 MPASS(nic_i == 0); 900 MPASS(nm_i == kring->nr_hwtail); 901 } else 902 MPASS(nm_i == kring->nr_hwcur); 903 DBG_COUNTER_INC(fl_refills); 904 while (n > 0) { 905 #if IFLIB_DEBUG_COUNTERS 906 if (++rf_count == 9) 907 DBG_COUNTER_INC(fl_refills_large); 908 #endif 909 nic_i_first = nic_i; 910 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 911 struct netmap_slot *slot = &ring->slot[nm_i]; 912 uint64_t paddr; 913 void *addr = PNMB(na, slot, &paddr); 914 915 MPASS(i < IFLIB_MAX_RX_REFRESH); 916 917 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 918 return netmap_ring_reinit(kring); 919 920 fl->ifl_bus_addrs[i] = paddr + 921 nm_get_offset(kring, slot); 922 fl->ifl_rxd_idxs[i] = nic_i; 923 924 if (__predict_false(init)) { 925 netmap_load_map(na, fl->ifl_buf_tag, 926 map[nic_i], addr); 927 } else if (slot->flags & NS_BUF_CHANGED) { 928 /* buffer has changed, reload map */ 929 netmap_reload_map(na, fl->ifl_buf_tag, 930 map[nic_i], addr); 931 } 932 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 933 BUS_DMASYNC_PREREAD); 934 slot->flags &= ~NS_BUF_CHANGED; 935 936 nm_i = nm_next(nm_i, lim); 937 nic_i = nm_next(nic_i, lim); 938 } 939 940 iru.iru_pidx = nic_i_first; 941 iru.iru_count = i; 942 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 943 } 944 fl->ifl_pidx = nic_i; 945 /* 946 * At the end of the loop we must have refilled everything 947 * we could possibly refill. 948 */ 949 MPASS(nm_i == kring->rhead); 950 kring->nr_hwcur = nm_i; 951 952 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 953 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 954 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 955 nm_prev(nic_i, lim)); 956 DBG_COUNTER_INC(rxd_flush); 957 958 return (0); 959 } 960 961 #define NETMAP_TX_TIMER_US 90 962 963 /* 964 * Reconcile kernel and user view of the transmit ring. 965 * 966 * All information is in the kring. 967 * Userspace wants to send packets up to the one before kring->rhead, 968 * kernel knows kring->nr_hwcur is the first unsent packet. 969 * 970 * Here we push packets out (as many as possible), and possibly 971 * reclaim buffers from previously completed transmission. 972 * 973 * The caller (netmap) guarantees that there is only one instance 974 * running at any time. Any interference with other driver 975 * methods should be handled by the individual drivers. 976 */ 977 static int 978 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 979 { 980 struct netmap_adapter *na = kring->na; 981 if_t ifp = na->ifp; 982 struct netmap_ring *ring = kring->ring; 983 u_int nm_i; /* index into the netmap kring */ 984 u_int nic_i; /* index into the NIC ring */ 985 u_int const lim = kring->nkr_num_slots - 1; 986 u_int const head = kring->rhead; 987 struct if_pkt_info pi; 988 int tx_pkts = 0, tx_bytes = 0; 989 990 /* 991 * interrupts on every tx packet are expensive so request 992 * them every half ring, or where NS_REPORT is set 993 */ 994 u_int report_frequency = kring->nkr_num_slots >> 1; 995 /* device-specific */ 996 if_ctx_t ctx = if_getsoftc(ifp); 997 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 998 999 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1000 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1001 1002 /* 1003 * First part: process new packets to send. 1004 * nm_i is the current index in the netmap kring, 1005 * nic_i is the corresponding index in the NIC ring. 1006 * 1007 * If we have packets to send (nm_i != head) 1008 * iterate over the netmap ring, fetch length and update 1009 * the corresponding slot in the NIC ring. Some drivers also 1010 * need to update the buffer's physical address in the NIC slot 1011 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 1012 * 1013 * The netmap_reload_map() calls is especially expensive, 1014 * even when (as in this case) the tag is 0, so do only 1015 * when the buffer has actually changed. 1016 * 1017 * If possible do not set the report/intr bit on all slots, 1018 * but only a few times per ring or when NS_REPORT is set. 1019 * 1020 * Finally, on 10G and faster drivers, it might be useful 1021 * to prefetch the next slot and txr entry. 1022 */ 1023 1024 nm_i = kring->nr_hwcur; 1025 if (nm_i != head) { /* we have new packets to send */ 1026 uint32_t pkt_len = 0, seg_idx = 0; 1027 int nic_i_start = -1, flags = 0; 1028 pkt_info_zero(&pi); 1029 pi.ipi_segs = txq->ift_segs; 1030 pi.ipi_qsidx = kring->ring_id; 1031 nic_i = netmap_idx_k2n(kring, nm_i); 1032 1033 __builtin_prefetch(&ring->slot[nm_i]); 1034 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 1035 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 1036 1037 while (nm_i != head) { 1038 struct netmap_slot *slot = &ring->slot[nm_i]; 1039 uint64_t offset = nm_get_offset(kring, slot); 1040 u_int len = slot->len; 1041 uint64_t paddr; 1042 void *addr = PNMB(na, slot, &paddr); 1043 1044 flags |= (slot->flags & NS_REPORT || 1045 nic_i == 0 || nic_i == report_frequency) ? 1046 IPI_TX_INTR : 0; 1047 1048 /* 1049 * If this is the first packet fragment, save the 1050 * index of the first NIC slot for later. 1051 */ 1052 if (nic_i_start < 0) 1053 nic_i_start = nic_i; 1054 1055 pi.ipi_segs[seg_idx].ds_addr = paddr + offset; 1056 pi.ipi_segs[seg_idx].ds_len = len; 1057 if (len) { 1058 pkt_len += len; 1059 seg_idx++; 1060 } 1061 1062 if (!(slot->flags & NS_MOREFRAG)) { 1063 pi.ipi_len = pkt_len; 1064 pi.ipi_nsegs = seg_idx; 1065 pi.ipi_pidx = nic_i_start; 1066 pi.ipi_ndescs = 0; 1067 pi.ipi_flags = flags; 1068 1069 /* Prepare the NIC TX ring. */ 1070 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1071 DBG_COUNTER_INC(tx_encap); 1072 1073 /* Update transmit counters */ 1074 tx_bytes += pi.ipi_len; 1075 tx_pkts++; 1076 1077 /* Reinit per-packet info for the next one. */ 1078 flags = seg_idx = pkt_len = 0; 1079 nic_i_start = -1; 1080 } 1081 1082 /* prefetch for next round */ 1083 __builtin_prefetch(&ring->slot[nm_i + 1]); 1084 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1085 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1086 1087 NM_CHECK_ADDR_LEN_OFF(na, len, offset); 1088 1089 if (slot->flags & NS_BUF_CHANGED) { 1090 /* buffer has changed, reload map */ 1091 netmap_reload_map(na, txq->ift_buf_tag, 1092 txq->ift_sds.ifsd_map[nic_i], addr); 1093 } 1094 /* make sure changes to the buffer are synced */ 1095 bus_dmamap_sync(txq->ift_buf_tag, 1096 txq->ift_sds.ifsd_map[nic_i], 1097 BUS_DMASYNC_PREWRITE); 1098 1099 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG); 1100 nm_i = nm_next(nm_i, lim); 1101 nic_i = nm_next(nic_i, lim); 1102 } 1103 kring->nr_hwcur = nm_i; 1104 1105 /* synchronize the NIC ring */ 1106 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1107 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1108 1109 /* (re)start the tx unit up to slot nic_i (excluded) */ 1110 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1111 } 1112 1113 /* 1114 * Second part: reclaim buffers for completed transmissions. 1115 * 1116 * If there are unclaimed buffers, attempt to reclaim them. 1117 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1118 * trigger a per-tx-queue timer to try again later. 1119 */ 1120 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1121 if (iflib_tx_credits_update(ctx, txq)) { 1122 /* some tx completed, increment avail */ 1123 nic_i = txq->ift_cidx_processed; 1124 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1125 } 1126 } 1127 1128 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1129 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1130 callout_reset_sbt_on(&txq->ift_netmap_timer, 1131 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1132 iflib_netmap_timer, txq, 1133 txq->ift_netmap_timer.c_cpu, 0); 1134 } 1135 1136 if_inc_counter(ifp, IFCOUNTER_OBYTES, tx_bytes); 1137 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tx_pkts); 1138 1139 return (0); 1140 } 1141 1142 /* 1143 * Reconcile kernel and user view of the receive ring. 1144 * Same as for the txsync, this routine must be efficient. 1145 * The caller guarantees a single invocations, but races against 1146 * the rest of the driver should be handled here. 1147 * 1148 * On call, kring->rhead is the first packet that userspace wants 1149 * to keep, and kring->rcur is the wakeup point. 1150 * The kernel has previously reported packets up to kring->rtail. 1151 * 1152 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1153 * of whether or not we received an interrupt. 1154 */ 1155 static int 1156 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1157 { 1158 struct netmap_adapter *na = kring->na; 1159 struct netmap_ring *ring = kring->ring; 1160 if_t ifp = na->ifp; 1161 uint32_t nm_i; /* index into the netmap ring */ 1162 uint32_t nic_i; /* index into the NIC ring */ 1163 u_int n; 1164 u_int const lim = kring->nkr_num_slots - 1; 1165 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1166 int i = 0, rx_bytes = 0, rx_pkts = 0; 1167 1168 if_ctx_t ctx = if_getsoftc(ifp); 1169 if_shared_ctx_t sctx = ctx->ifc_sctx; 1170 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1171 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1172 iflib_fl_t fl = &rxq->ifr_fl[0]; 1173 struct if_rxd_info ri; 1174 qidx_t *cidxp; 1175 1176 /* 1177 * netmap only uses free list 0, to avoid out of order consumption 1178 * of receive buffers 1179 */ 1180 1181 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1182 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1183 1184 /* 1185 * First part: import newly received packets. 1186 * 1187 * nm_i is the index of the next free slot in the netmap ring, 1188 * nic_i is the index of the next received packet in the NIC ring 1189 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1190 * differ in case if_init() has been called while 1191 * in netmap mode. For the receive ring we have 1192 * 1193 * nic_i = fl->ifl_cidx; 1194 * nm_i = kring->nr_hwtail (previous) 1195 * and 1196 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1197 * 1198 * fl->ifl_cidx is set to 0 on a ring reinit 1199 */ 1200 if (netmap_no_pendintr || force_update) { 1201 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1202 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1203 int crclen = iflib_crcstrip ? 0 : 4; 1204 int error, avail; 1205 1206 /* 1207 * For the free list consumer index, we use the same 1208 * logic as in iflib_rxeof(). 1209 */ 1210 if (have_rxcq) 1211 cidxp = &rxq->ifr_cq_cidx; 1212 else 1213 cidxp = &fl->ifl_cidx; 1214 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1215 rxq->ifr_id, *cidxp, USHRT_MAX); 1216 1217 nic_i = fl->ifl_cidx; 1218 nm_i = netmap_idx_n2k(kring, nic_i); 1219 MPASS(nm_i == kring->nr_hwtail); 1220 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1221 rxd_info_zero(&ri); 1222 ri.iri_frags = rxq->ifr_frags; 1223 ri.iri_qsidx = kring->ring_id; 1224 ri.iri_ifp = ctx->ifc_ifp; 1225 ri.iri_cidx = *cidxp; 1226 1227 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1228 for (i = 0; i < ri.iri_nfrags; i++) { 1229 if (error) { 1230 ring->slot[nm_i].len = 0; 1231 ring->slot[nm_i].flags = 0; 1232 } else { 1233 ring->slot[nm_i].len = ri.iri_frags[i].irf_len; 1234 if (i == (ri.iri_nfrags - 1)) { 1235 ring->slot[nm_i].len -= crclen; 1236 ring->slot[nm_i].flags = 0; 1237 1238 /* Update receive counters */ 1239 rx_bytes += ri.iri_len; 1240 rx_pkts++; 1241 } else 1242 ring->slot[nm_i].flags = NS_MOREFRAG; 1243 } 1244 1245 bus_dmamap_sync(fl->ifl_buf_tag, 1246 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1247 nm_i = nm_next(nm_i, lim); 1248 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1249 } 1250 1251 if (have_rxcq) { 1252 *cidxp = ri.iri_cidx; 1253 while (*cidxp >= scctx->isc_nrxd[0]) 1254 *cidxp -= scctx->isc_nrxd[0]; 1255 } 1256 1257 } 1258 if (n) { /* update the state variables */ 1259 if (netmap_no_pendintr && !force_update) { 1260 /* diagnostics */ 1261 iflib_rx_miss ++; 1262 iflib_rx_miss_bufs += n; 1263 } 1264 kring->nr_hwtail = nm_i; 1265 } 1266 kring->nr_kflags &= ~NKR_PENDINTR; 1267 } 1268 /* 1269 * Second part: skip past packets that userspace has released. 1270 * (kring->nr_hwcur to head excluded), 1271 * and make the buffers available for reception. 1272 * As usual nm_i is the index in the netmap ring, 1273 * nic_i is the index in the NIC ring, and 1274 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1275 */ 1276 netmap_fl_refill(rxq, kring, false); 1277 1278 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 1279 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 1280 1281 return (0); 1282 } 1283 1284 static void 1285 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1286 { 1287 if_ctx_t ctx = if_getsoftc(na->ifp); 1288 1289 CTX_LOCK(ctx); 1290 if (onoff) { 1291 IFDI_INTR_ENABLE(ctx); 1292 } else { 1293 IFDI_INTR_DISABLE(ctx); 1294 } 1295 CTX_UNLOCK(ctx); 1296 } 1297 1298 static int 1299 iflib_netmap_attach(if_ctx_t ctx) 1300 { 1301 struct netmap_adapter na; 1302 1303 bzero(&na, sizeof(na)); 1304 1305 na.ifp = ctx->ifc_ifp; 1306 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS; 1307 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1308 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1309 1310 na.num_tx_desc = iflib_num_tx_descs(ctx); 1311 na.num_rx_desc = iflib_num_rx_descs(ctx); 1312 na.nm_txsync = iflib_netmap_txsync; 1313 na.nm_rxsync = iflib_netmap_rxsync; 1314 na.nm_register = iflib_netmap_register; 1315 na.nm_intr = iflib_netmap_intr; 1316 na.nm_config = iflib_netmap_config; 1317 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1318 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1319 return (netmap_attach(&na)); 1320 } 1321 1322 static int 1323 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1324 { 1325 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1326 struct netmap_slot *slot; 1327 1328 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1329 if (slot == NULL) 1330 return (0); 1331 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1332 /* 1333 * In netmap mode, set the map for the packet buffer. 1334 * NOTE: Some drivers (not this one) also need to set 1335 * the physical buffer address in the NIC ring. 1336 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1337 * netmap slot index, si 1338 */ 1339 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1340 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1341 NMB(na, slot + si)); 1342 } 1343 return (1); 1344 } 1345 1346 static int 1347 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1348 { 1349 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1350 struct netmap_kring *kring; 1351 struct netmap_slot *slot; 1352 1353 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1354 if (slot == NULL) 1355 return (0); 1356 kring = na->rx_rings[rxq->ifr_id]; 1357 netmap_fl_refill(rxq, kring, true); 1358 return (1); 1359 } 1360 1361 static void 1362 iflib_netmap_timer(void *arg) 1363 { 1364 iflib_txq_t txq = arg; 1365 if_ctx_t ctx = txq->ift_ctx; 1366 1367 /* 1368 * Wake up the netmap application, to give it a chance to 1369 * call txsync and reclaim more completed TX buffers. 1370 */ 1371 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1372 } 1373 1374 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1375 1376 #else 1377 #define iflib_netmap_txq_init(ctx, txq) (0) 1378 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1379 #define iflib_netmap_detach(ifp) 1380 #define netmap_enable_all_rings(ifp) 1381 #define netmap_disable_all_rings(ifp) 1382 1383 #define iflib_netmap_attach(ctx) (0) 1384 #define netmap_rx_irq(ifp, qid, budget) (0) 1385 #endif 1386 1387 #if defined(__i386__) || defined(__amd64__) 1388 static __inline void 1389 prefetch(void *x) 1390 { 1391 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1392 } 1393 1394 static __inline void 1395 prefetch2cachelines(void *x) 1396 { 1397 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1398 #if (CACHE_LINE_SIZE < 128) 1399 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1400 #endif 1401 } 1402 #else 1403 static __inline void 1404 prefetch(void *x) 1405 { 1406 } 1407 1408 static __inline void 1409 prefetch2cachelines(void *x) 1410 { 1411 } 1412 #endif 1413 1414 static void 1415 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1416 { 1417 iflib_fl_t fl; 1418 1419 fl = &rxq->ifr_fl[flid]; 1420 iru->iru_paddrs = fl->ifl_bus_addrs; 1421 iru->iru_idxs = fl->ifl_rxd_idxs; 1422 iru->iru_qsidx = rxq->ifr_id; 1423 iru->iru_buf_size = fl->ifl_buf_size; 1424 iru->iru_flidx = fl->ifl_id; 1425 } 1426 1427 static void 1428 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1429 { 1430 if (err) 1431 return; 1432 *(bus_addr_t *) arg = segs[0].ds_addr; 1433 } 1434 1435 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \ 1436 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \ 1437 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL) 1438 1439 int 1440 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1441 { 1442 int err; 1443 device_t dev = ctx->ifc_dev; 1444 bus_addr_t lowaddr; 1445 1446 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width); 1447 1448 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1449 align, 0, /* alignment, bounds */ 1450 lowaddr, /* lowaddr */ 1451 BUS_SPACE_MAXADDR, /* highaddr */ 1452 NULL, NULL, /* filter, filterarg */ 1453 size, /* maxsize */ 1454 1, /* nsegments */ 1455 size, /* maxsegsize */ 1456 BUS_DMA_ALLOCNOW, /* flags */ 1457 NULL, /* lockfunc */ 1458 NULL, /* lockarg */ 1459 &dma->idi_tag); 1460 if (err) { 1461 device_printf(dev, 1462 "%s: bus_dma_tag_create failed: %d\n", 1463 __func__, err); 1464 goto fail_0; 1465 } 1466 1467 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1468 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1469 if (err) { 1470 device_printf(dev, 1471 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1472 __func__, (uintmax_t)size, err); 1473 goto fail_1; 1474 } 1475 1476 dma->idi_paddr = IF_BAD_DMA; 1477 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1478 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1479 if (err || dma->idi_paddr == IF_BAD_DMA) { 1480 device_printf(dev, 1481 "%s: bus_dmamap_load failed: %d\n", 1482 __func__, err); 1483 goto fail_2; 1484 } 1485 1486 dma->idi_size = size; 1487 return (0); 1488 1489 fail_2: 1490 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1491 fail_1: 1492 bus_dma_tag_destroy(dma->idi_tag); 1493 fail_0: 1494 dma->idi_tag = NULL; 1495 1496 return (err); 1497 } 1498 1499 int 1500 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1501 { 1502 if_shared_ctx_t sctx = ctx->ifc_sctx; 1503 1504 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1505 1506 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1507 } 1508 1509 int 1510 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1511 { 1512 int i, err; 1513 iflib_dma_info_t *dmaiter; 1514 1515 dmaiter = dmalist; 1516 for (i = 0; i < count; i++, dmaiter++) { 1517 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1518 break; 1519 } 1520 if (err) 1521 iflib_dma_free_multi(dmalist, i); 1522 return (err); 1523 } 1524 1525 void 1526 iflib_dma_free(iflib_dma_info_t dma) 1527 { 1528 if (dma->idi_tag == NULL) 1529 return; 1530 if (dma->idi_paddr != IF_BAD_DMA) { 1531 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1532 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1533 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1534 dma->idi_paddr = IF_BAD_DMA; 1535 } 1536 if (dma->idi_vaddr != NULL) { 1537 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1538 dma->idi_vaddr = NULL; 1539 } 1540 bus_dma_tag_destroy(dma->idi_tag); 1541 dma->idi_tag = NULL; 1542 } 1543 1544 void 1545 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1546 { 1547 int i; 1548 iflib_dma_info_t *dmaiter = dmalist; 1549 1550 for (i = 0; i < count; i++, dmaiter++) 1551 iflib_dma_free(*dmaiter); 1552 } 1553 1554 static int 1555 iflib_fast_intr(void *arg) 1556 { 1557 iflib_filter_info_t info = arg; 1558 struct grouptask *gtask = info->ifi_task; 1559 int result; 1560 1561 DBG_COUNTER_INC(fast_intrs); 1562 if (info->ifi_filter != NULL) { 1563 result = info->ifi_filter(info->ifi_filter_arg); 1564 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1565 return (result); 1566 } 1567 1568 GROUPTASK_ENQUEUE(gtask); 1569 return (FILTER_HANDLED); 1570 } 1571 1572 static int 1573 iflib_fast_intr_rxtx(void *arg) 1574 { 1575 iflib_filter_info_t info = arg; 1576 struct grouptask *gtask = info->ifi_task; 1577 if_ctx_t ctx; 1578 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1579 iflib_txq_t txq; 1580 void *sc; 1581 int i, cidx, result; 1582 qidx_t txqid; 1583 bool intr_enable, intr_legacy; 1584 1585 DBG_COUNTER_INC(fast_intrs); 1586 if (info->ifi_filter != NULL) { 1587 result = info->ifi_filter(info->ifi_filter_arg); 1588 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1589 return (result); 1590 } 1591 1592 ctx = rxq->ifr_ctx; 1593 sc = ctx->ifc_softc; 1594 intr_enable = false; 1595 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1596 MPASS(rxq->ifr_ntxqirq); 1597 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1598 txqid = rxq->ifr_txqid[i]; 1599 txq = &ctx->ifc_txqs[txqid]; 1600 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1601 BUS_DMASYNC_POSTREAD); 1602 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1603 if (intr_legacy) 1604 intr_enable = true; 1605 else 1606 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1607 continue; 1608 } 1609 GROUPTASK_ENQUEUE(&txq->ift_task); 1610 } 1611 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1612 cidx = rxq->ifr_cq_cidx; 1613 else 1614 cidx = rxq->ifr_fl[0].ifl_cidx; 1615 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1616 GROUPTASK_ENQUEUE(gtask); 1617 else { 1618 if (intr_legacy) 1619 intr_enable = true; 1620 else 1621 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1622 DBG_COUNTER_INC(rx_intr_enables); 1623 } 1624 if (intr_enable) 1625 IFDI_INTR_ENABLE(ctx); 1626 return (FILTER_HANDLED); 1627 } 1628 1629 static int 1630 iflib_fast_intr_ctx(void *arg) 1631 { 1632 iflib_filter_info_t info = arg; 1633 struct grouptask *gtask = info->ifi_task; 1634 int result; 1635 1636 DBG_COUNTER_INC(fast_intrs); 1637 if (info->ifi_filter != NULL) { 1638 result = info->ifi_filter(info->ifi_filter_arg); 1639 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1640 return (result); 1641 } 1642 1643 if (gtask->gt_taskqueue != NULL) 1644 GROUPTASK_ENQUEUE(gtask); 1645 return (FILTER_HANDLED); 1646 } 1647 1648 static int 1649 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1650 driver_filter_t filter, driver_intr_t handler, void *arg, 1651 const char *name) 1652 { 1653 struct resource *res; 1654 void *tag = NULL; 1655 device_t dev = ctx->ifc_dev; 1656 int flags, i, rc; 1657 1658 flags = RF_ACTIVE; 1659 if (ctx->ifc_flags & IFC_LEGACY) 1660 flags |= RF_SHAREABLE; 1661 MPASS(rid < 512); 1662 i = rid; 1663 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1664 if (res == NULL) { 1665 device_printf(dev, 1666 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1667 return (ENOMEM); 1668 } 1669 irq->ii_res = res; 1670 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1671 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1672 filter, handler, arg, &tag); 1673 if (rc != 0) { 1674 device_printf(dev, 1675 "failed to setup interrupt for rid %d, name %s: %d\n", 1676 rid, name ? name : "unknown", rc); 1677 return (rc); 1678 } else if (name) 1679 bus_describe_intr(dev, res, tag, "%s", name); 1680 1681 irq->ii_tag = tag; 1682 return (0); 1683 } 1684 1685 /********************************************************************* 1686 * 1687 * Allocate DMA resources for TX buffers as well as memory for the TX 1688 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1689 * iflib_sw_tx_desc_array structure, storing all the information that 1690 * is needed to transmit a packet on the wire. This is called only 1691 * once at attach, setup is done every reset. 1692 * 1693 **********************************************************************/ 1694 static int 1695 iflib_txsd_alloc(iflib_txq_t txq) 1696 { 1697 if_ctx_t ctx = txq->ift_ctx; 1698 if_shared_ctx_t sctx = ctx->ifc_sctx; 1699 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1700 device_t dev = ctx->ifc_dev; 1701 bus_size_t tsomaxsize; 1702 bus_addr_t lowaddr; 1703 int err, nsegments, ntsosegments; 1704 bool tso; 1705 1706 nsegments = scctx->isc_tx_nsegments; 1707 ntsosegments = scctx->isc_tx_tso_segments_max; 1708 tsomaxsize = scctx->isc_tx_tso_size_max; 1709 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1710 tsomaxsize += sizeof(struct ether_vlan_header); 1711 MPASS(scctx->isc_ntxd[0] > 0); 1712 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1713 MPASS(nsegments > 0); 1714 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1715 MPASS(ntsosegments > 0); 1716 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1717 } 1718 1719 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1720 1721 /* 1722 * Set up DMA tags for TX buffers. 1723 */ 1724 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1725 1, 0, /* alignment, bounds */ 1726 lowaddr, /* lowaddr */ 1727 BUS_SPACE_MAXADDR, /* highaddr */ 1728 NULL, NULL, /* filter, filterarg */ 1729 sctx->isc_tx_maxsize, /* maxsize */ 1730 nsegments, /* nsegments */ 1731 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1732 0, /* flags */ 1733 NULL, /* lockfunc */ 1734 NULL, /* lockfuncarg */ 1735 &txq->ift_buf_tag))) { 1736 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1737 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1738 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1739 goto fail; 1740 } 1741 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1742 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1743 1, 0, /* alignment, bounds */ 1744 lowaddr, /* lowaddr */ 1745 BUS_SPACE_MAXADDR, /* highaddr */ 1746 NULL, NULL, /* filter, filterarg */ 1747 tsomaxsize, /* maxsize */ 1748 ntsosegments, /* nsegments */ 1749 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1750 0, /* flags */ 1751 NULL, /* lockfunc */ 1752 NULL, /* lockfuncarg */ 1753 &txq->ift_tso_buf_tag))) { 1754 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1755 err); 1756 goto fail; 1757 } 1758 1759 /* Allocate memory for the TX mbuf map. */ 1760 if (!(txq->ift_sds.ifsd_m = 1761 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1762 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1763 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1764 err = ENOMEM; 1765 goto fail; 1766 } 1767 1768 /* 1769 * Create the DMA maps for TX buffers. 1770 */ 1771 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1772 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1773 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1774 device_printf(dev, 1775 "Unable to allocate TX buffer DMA map memory\n"); 1776 err = ENOMEM; 1777 goto fail; 1778 } 1779 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1780 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1781 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1782 device_printf(dev, 1783 "Unable to allocate TSO TX buffer map memory\n"); 1784 err = ENOMEM; 1785 goto fail; 1786 } 1787 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1788 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1789 &txq->ift_sds.ifsd_map[i]); 1790 if (err != 0) { 1791 device_printf(dev, "Unable to create TX DMA map\n"); 1792 goto fail; 1793 } 1794 if (!tso) 1795 continue; 1796 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1797 &txq->ift_sds.ifsd_tso_map[i]); 1798 if (err != 0) { 1799 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1800 goto fail; 1801 } 1802 } 1803 return (0); 1804 fail: 1805 /* We free all, it handles case where we are in the middle */ 1806 iflib_tx_structures_free(ctx); 1807 return (err); 1808 } 1809 1810 static void 1811 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1812 { 1813 bus_dmamap_t map; 1814 1815 if (txq->ift_sds.ifsd_map != NULL) { 1816 map = txq->ift_sds.ifsd_map[i]; 1817 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1818 bus_dmamap_unload(txq->ift_buf_tag, map); 1819 bus_dmamap_destroy(txq->ift_buf_tag, map); 1820 txq->ift_sds.ifsd_map[i] = NULL; 1821 } 1822 1823 if (txq->ift_sds.ifsd_tso_map != NULL) { 1824 map = txq->ift_sds.ifsd_tso_map[i]; 1825 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1826 BUS_DMASYNC_POSTWRITE); 1827 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1828 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1829 txq->ift_sds.ifsd_tso_map[i] = NULL; 1830 } 1831 } 1832 1833 static void 1834 iflib_txq_destroy(iflib_txq_t txq) 1835 { 1836 if_ctx_t ctx = txq->ift_ctx; 1837 1838 for (int i = 0; i < txq->ift_size; i++) 1839 iflib_txsd_destroy(ctx, txq, i); 1840 1841 if (txq->ift_br != NULL) { 1842 ifmp_ring_free(txq->ift_br); 1843 txq->ift_br = NULL; 1844 } 1845 1846 mtx_destroy(&txq->ift_mtx); 1847 1848 if (txq->ift_sds.ifsd_map != NULL) { 1849 free(txq->ift_sds.ifsd_map, M_IFLIB); 1850 txq->ift_sds.ifsd_map = NULL; 1851 } 1852 if (txq->ift_sds.ifsd_tso_map != NULL) { 1853 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1854 txq->ift_sds.ifsd_tso_map = NULL; 1855 } 1856 if (txq->ift_sds.ifsd_m != NULL) { 1857 free(txq->ift_sds.ifsd_m, M_IFLIB); 1858 txq->ift_sds.ifsd_m = NULL; 1859 } 1860 if (txq->ift_buf_tag != NULL) { 1861 bus_dma_tag_destroy(txq->ift_buf_tag); 1862 txq->ift_buf_tag = NULL; 1863 } 1864 if (txq->ift_tso_buf_tag != NULL) { 1865 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1866 txq->ift_tso_buf_tag = NULL; 1867 } 1868 if (txq->ift_ifdi != NULL) { 1869 free(txq->ift_ifdi, M_IFLIB); 1870 } 1871 } 1872 1873 static void 1874 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1875 { 1876 struct mbuf **mp; 1877 1878 mp = &txq->ift_sds.ifsd_m[i]; 1879 if (*mp == NULL) 1880 return; 1881 1882 if (txq->ift_sds.ifsd_map != NULL) { 1883 bus_dmamap_sync(txq->ift_buf_tag, 1884 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1885 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1886 } 1887 if (txq->ift_sds.ifsd_tso_map != NULL) { 1888 bus_dmamap_sync(txq->ift_tso_buf_tag, 1889 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1890 bus_dmamap_unload(txq->ift_tso_buf_tag, 1891 txq->ift_sds.ifsd_tso_map[i]); 1892 } 1893 m_freem(*mp); 1894 DBG_COUNTER_INC(tx_frees); 1895 *mp = NULL; 1896 } 1897 1898 static int 1899 iflib_txq_setup(iflib_txq_t txq) 1900 { 1901 if_ctx_t ctx = txq->ift_ctx; 1902 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1903 if_shared_ctx_t sctx = ctx->ifc_sctx; 1904 iflib_dma_info_t di; 1905 int i; 1906 1907 /* Set number of descriptors available */ 1908 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1909 /* XXX make configurable */ 1910 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1911 1912 /* Reset indices */ 1913 txq->ift_cidx_processed = 0; 1914 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1915 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1916 1917 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1918 bzero((void *)di->idi_vaddr, di->idi_size); 1919 1920 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1921 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1922 bus_dmamap_sync(di->idi_tag, di->idi_map, 1923 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1924 return (0); 1925 } 1926 1927 /********************************************************************* 1928 * 1929 * Allocate DMA resources for RX buffers as well as memory for the RX 1930 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1931 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1932 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1933 * Since we use use one entry in iflib_sw_rx_desc_array per received 1934 * packet, the maximum number of entries we'll need is equal to the 1935 * number of hardware receive descriptors that we've allocated. 1936 * 1937 **********************************************************************/ 1938 static int 1939 iflib_rxsd_alloc(iflib_rxq_t rxq) 1940 { 1941 if_ctx_t ctx = rxq->ifr_ctx; 1942 if_shared_ctx_t sctx = ctx->ifc_sctx; 1943 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1944 device_t dev = ctx->ifc_dev; 1945 iflib_fl_t fl; 1946 bus_addr_t lowaddr; 1947 int err; 1948 1949 MPASS(scctx->isc_nrxd[0] > 0); 1950 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1951 1952 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1953 1954 fl = rxq->ifr_fl; 1955 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1956 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1957 /* Set up DMA tag for RX buffers. */ 1958 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1959 1, 0, /* alignment, bounds */ 1960 lowaddr, /* lowaddr */ 1961 BUS_SPACE_MAXADDR, /* highaddr */ 1962 NULL, NULL, /* filter, filterarg */ 1963 sctx->isc_rx_maxsize, /* maxsize */ 1964 sctx->isc_rx_nsegments, /* nsegments */ 1965 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1966 0, /* flags */ 1967 NULL, /* lockfunc */ 1968 NULL, /* lockarg */ 1969 &fl->ifl_buf_tag); 1970 if (err) { 1971 device_printf(dev, 1972 "Unable to allocate RX DMA tag: %d\n", err); 1973 goto fail; 1974 } 1975 1976 /* Allocate memory for the RX mbuf map. */ 1977 if (!(fl->ifl_sds.ifsd_m = 1978 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1979 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1980 device_printf(dev, 1981 "Unable to allocate RX mbuf map memory\n"); 1982 err = ENOMEM; 1983 goto fail; 1984 } 1985 1986 /* Allocate memory for the direct RX cluster pointer map. */ 1987 if (!(fl->ifl_sds.ifsd_cl = 1988 (caddr_t *) malloc(sizeof(caddr_t) * 1989 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1990 device_printf(dev, 1991 "Unable to allocate RX cluster map memory\n"); 1992 err = ENOMEM; 1993 goto fail; 1994 } 1995 1996 /* Allocate memory for the RX cluster bus address map. */ 1997 if (!(fl->ifl_sds.ifsd_ba = 1998 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1999 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2000 device_printf(dev, 2001 "Unable to allocate RX bus address map memory\n"); 2002 err = ENOMEM; 2003 goto fail; 2004 } 2005 2006 /* 2007 * Create the DMA maps for RX buffers. 2008 */ 2009 if (!(fl->ifl_sds.ifsd_map = 2010 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2011 device_printf(dev, 2012 "Unable to allocate RX buffer DMA map memory\n"); 2013 err = ENOMEM; 2014 goto fail; 2015 } 2016 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 2017 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 2018 &fl->ifl_sds.ifsd_map[i]); 2019 if (err != 0) { 2020 device_printf(dev, "Unable to create RX buffer DMA map\n"); 2021 goto fail; 2022 } 2023 } 2024 } 2025 return (0); 2026 2027 fail: 2028 iflib_rx_structures_free(ctx); 2029 return (err); 2030 } 2031 2032 /* 2033 * Internal service routines 2034 */ 2035 2036 struct rxq_refill_cb_arg { 2037 int error; 2038 bus_dma_segment_t seg; 2039 int nseg; 2040 }; 2041 2042 static void 2043 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2044 { 2045 struct rxq_refill_cb_arg *cb_arg = arg; 2046 2047 cb_arg->error = error; 2048 cb_arg->seg = segs[0]; 2049 cb_arg->nseg = nseg; 2050 } 2051 2052 /** 2053 * iflib_fl_refill - refill an rxq free-buffer list 2054 * @ctx: the iflib context 2055 * @fl: the free list to refill 2056 * @count: the number of new buffers to allocate 2057 * 2058 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 2059 * The caller must assure that @count does not exceed the queue's capacity 2060 * minus one (since we always leave a descriptor unavailable). 2061 */ 2062 static uint8_t 2063 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 2064 { 2065 struct if_rxd_update iru; 2066 struct rxq_refill_cb_arg cb_arg; 2067 struct mbuf *m; 2068 caddr_t cl, *sd_cl; 2069 struct mbuf **sd_m; 2070 bus_dmamap_t *sd_map; 2071 bus_addr_t bus_addr, *sd_ba; 2072 int err, frag_idx, i, idx, n, pidx; 2073 qidx_t credits; 2074 2075 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 2076 2077 sd_m = fl->ifl_sds.ifsd_m; 2078 sd_map = fl->ifl_sds.ifsd_map; 2079 sd_cl = fl->ifl_sds.ifsd_cl; 2080 sd_ba = fl->ifl_sds.ifsd_ba; 2081 pidx = fl->ifl_pidx; 2082 idx = pidx; 2083 frag_idx = fl->ifl_fragidx; 2084 credits = fl->ifl_credits; 2085 2086 i = 0; 2087 n = count; 2088 MPASS(n > 0); 2089 MPASS(credits + n <= fl->ifl_size); 2090 2091 if (pidx < fl->ifl_cidx) 2092 MPASS(pidx + n <= fl->ifl_cidx); 2093 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 2094 MPASS(fl->ifl_gen == 0); 2095 if (pidx > fl->ifl_cidx) 2096 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 2097 2098 DBG_COUNTER_INC(fl_refills); 2099 if (n > 8) 2100 DBG_COUNTER_INC(fl_refills_large); 2101 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 2102 while (n-- > 0) { 2103 /* 2104 * We allocate an uninitialized mbuf + cluster, mbuf is 2105 * initialized after rx. 2106 * 2107 * If the cluster is still set then we know a minimum sized 2108 * packet was received 2109 */ 2110 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2111 &frag_idx); 2112 if (frag_idx < 0) 2113 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2114 MPASS(frag_idx >= 0); 2115 if ((cl = sd_cl[frag_idx]) == NULL) { 2116 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2117 if (__predict_false(cl == NULL)) 2118 break; 2119 2120 cb_arg.error = 0; 2121 MPASS(sd_map != NULL); 2122 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2123 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2124 BUS_DMA_NOWAIT); 2125 if (__predict_false(err != 0 || cb_arg.error)) { 2126 uma_zfree(fl->ifl_zone, cl); 2127 break; 2128 } 2129 2130 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2131 sd_cl[frag_idx] = cl; 2132 #if MEMORY_LOGGING 2133 fl->ifl_cl_enqueued++; 2134 #endif 2135 } else { 2136 bus_addr = sd_ba[frag_idx]; 2137 } 2138 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2139 BUS_DMASYNC_PREREAD); 2140 2141 if (sd_m[frag_idx] == NULL) { 2142 m = m_gethdr_raw(M_NOWAIT, 0); 2143 if (__predict_false(m == NULL)) 2144 break; 2145 sd_m[frag_idx] = m; 2146 } 2147 bit_set(fl->ifl_rx_bitmap, frag_idx); 2148 #if MEMORY_LOGGING 2149 fl->ifl_m_enqueued++; 2150 #endif 2151 2152 DBG_COUNTER_INC(rx_allocs); 2153 fl->ifl_rxd_idxs[i] = frag_idx; 2154 fl->ifl_bus_addrs[i] = bus_addr; 2155 credits++; 2156 i++; 2157 MPASS(credits <= fl->ifl_size); 2158 if (++idx == fl->ifl_size) { 2159 #ifdef INVARIANTS 2160 fl->ifl_gen = 1; 2161 #endif 2162 idx = 0; 2163 } 2164 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2165 iru.iru_pidx = pidx; 2166 iru.iru_count = i; 2167 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2168 fl->ifl_pidx = idx; 2169 fl->ifl_credits = credits; 2170 pidx = idx; 2171 i = 0; 2172 } 2173 } 2174 2175 if (n < count - 1) { 2176 if (i != 0) { 2177 iru.iru_pidx = pidx; 2178 iru.iru_count = i; 2179 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2180 fl->ifl_pidx = idx; 2181 fl->ifl_credits = credits; 2182 } 2183 DBG_COUNTER_INC(rxd_flush); 2184 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2185 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2186 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2187 fl->ifl_id, fl->ifl_pidx); 2188 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2189 fl->ifl_fragidx = frag_idx + 1; 2190 if (fl->ifl_fragidx == fl->ifl_size) 2191 fl->ifl_fragidx = 0; 2192 } else { 2193 fl->ifl_fragidx = frag_idx; 2194 } 2195 } 2196 2197 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2198 } 2199 2200 static inline uint8_t 2201 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2202 { 2203 /* 2204 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2205 * This is important as it confuses most NICs. For instance, 2206 * Intel NICs have (per receive ring) RDH and RDT registers, where 2207 * RDH points to the next receive descriptor to be used by the NIC, 2208 * and RDT for the next receive descriptor to be published by the 2209 * driver to the NIC (RDT - 1 is thus the last valid one). 2210 * The condition RDH == RDT means no descriptors are available to 2211 * the NIC, and thus it would be ambiguous if it also meant that 2212 * all the descriptors are available to the NIC. 2213 */ 2214 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2215 #ifdef INVARIANTS 2216 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2217 #endif 2218 2219 MPASS(fl->ifl_credits <= fl->ifl_size); 2220 MPASS(reclaimable == delta); 2221 2222 if (reclaimable > 0) 2223 return (iflib_fl_refill(ctx, fl, reclaimable)); 2224 return (0); 2225 } 2226 2227 uint8_t 2228 iflib_in_detach(if_ctx_t ctx) 2229 { 2230 bool in_detach; 2231 2232 STATE_LOCK(ctx); 2233 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2234 STATE_UNLOCK(ctx); 2235 return (in_detach); 2236 } 2237 2238 static void 2239 iflib_fl_bufs_free(iflib_fl_t fl) 2240 { 2241 iflib_dma_info_t idi = fl->ifl_ifdi; 2242 bus_dmamap_t sd_map; 2243 uint32_t i; 2244 2245 for (i = 0; i < fl->ifl_size; i++) { 2246 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2247 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2248 2249 if (*sd_cl != NULL) { 2250 sd_map = fl->ifl_sds.ifsd_map[i]; 2251 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2252 BUS_DMASYNC_POSTREAD); 2253 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2254 uma_zfree(fl->ifl_zone, *sd_cl); 2255 *sd_cl = NULL; 2256 if (*sd_m != NULL) { 2257 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2258 m_free_raw(*sd_m); 2259 *sd_m = NULL; 2260 } 2261 } else { 2262 MPASS(*sd_m == NULL); 2263 } 2264 #if MEMORY_LOGGING 2265 fl->ifl_m_dequeued++; 2266 fl->ifl_cl_dequeued++; 2267 #endif 2268 } 2269 #ifdef INVARIANTS 2270 for (i = 0; i < fl->ifl_size; i++) { 2271 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2272 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2273 } 2274 #endif 2275 /* 2276 * Reset free list values 2277 */ 2278 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2279 bzero(idi->idi_vaddr, idi->idi_size); 2280 } 2281 2282 /********************************************************************* 2283 * 2284 * Initialize a free list and its buffers. 2285 * 2286 **********************************************************************/ 2287 static int 2288 iflib_fl_setup(iflib_fl_t fl) 2289 { 2290 iflib_rxq_t rxq = fl->ifl_rxq; 2291 if_ctx_t ctx = rxq->ifr_ctx; 2292 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2293 int qidx; 2294 2295 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2296 /* 2297 ** Free current RX buffer structs and their mbufs 2298 */ 2299 iflib_fl_bufs_free(fl); 2300 /* Now replenish the mbufs */ 2301 MPASS(fl->ifl_credits == 0); 2302 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2303 if (scctx->isc_rxd_buf_size[qidx] != 0) 2304 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2305 else 2306 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2307 /* 2308 * ifl_buf_size may be a driver-supplied value, so pull it up 2309 * to the selected mbuf size. 2310 */ 2311 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2312 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2313 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2314 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2315 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2316 2317 /* 2318 * Avoid pre-allocating zillions of clusters to an idle card 2319 * potentially speeding up attach. In any case make sure 2320 * to leave a descriptor unavailable. See the comment in 2321 * iflib_fl_refill_all(). 2322 */ 2323 MPASS(fl->ifl_size > 0); 2324 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2325 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2326 return (ENOBUFS); 2327 /* 2328 * handle failure 2329 */ 2330 MPASS(rxq != NULL); 2331 MPASS(fl->ifl_ifdi != NULL); 2332 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2333 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2334 return (0); 2335 } 2336 2337 /********************************************************************* 2338 * 2339 * Free receive ring data structures 2340 * 2341 **********************************************************************/ 2342 static void 2343 iflib_rx_sds_free(iflib_rxq_t rxq) 2344 { 2345 iflib_fl_t fl; 2346 int i, j; 2347 2348 if (rxq->ifr_fl != NULL) { 2349 for (i = 0; i < rxq->ifr_nfl; i++) { 2350 fl = &rxq->ifr_fl[i]; 2351 if (fl->ifl_buf_tag != NULL) { 2352 if (fl->ifl_sds.ifsd_map != NULL) { 2353 for (j = 0; j < fl->ifl_size; j++) { 2354 bus_dmamap_sync( 2355 fl->ifl_buf_tag, 2356 fl->ifl_sds.ifsd_map[j], 2357 BUS_DMASYNC_POSTREAD); 2358 bus_dmamap_unload( 2359 fl->ifl_buf_tag, 2360 fl->ifl_sds.ifsd_map[j]); 2361 bus_dmamap_destroy( 2362 fl->ifl_buf_tag, 2363 fl->ifl_sds.ifsd_map[j]); 2364 } 2365 } 2366 bus_dma_tag_destroy(fl->ifl_buf_tag); 2367 fl->ifl_buf_tag = NULL; 2368 } 2369 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2370 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2371 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2372 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2373 free(fl->ifl_rx_bitmap, M_IFLIB); 2374 fl->ifl_sds.ifsd_m = NULL; 2375 fl->ifl_sds.ifsd_cl = NULL; 2376 fl->ifl_sds.ifsd_ba = NULL; 2377 fl->ifl_sds.ifsd_map = NULL; 2378 fl->ifl_rx_bitmap = NULL; 2379 } 2380 free(rxq->ifr_fl, M_IFLIB); 2381 rxq->ifr_fl = NULL; 2382 free(rxq->ifr_ifdi, M_IFLIB); 2383 rxq->ifr_ifdi = NULL; 2384 rxq->ifr_cq_cidx = 0; 2385 } 2386 } 2387 2388 /* 2389 * Timer routine 2390 */ 2391 static void 2392 iflib_timer(void *arg) 2393 { 2394 iflib_txq_t txq = arg; 2395 if_ctx_t ctx = txq->ift_ctx; 2396 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2397 uint64_t this_tick = ticks; 2398 2399 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2400 return; 2401 2402 /* 2403 ** Check on the state of the TX queue(s), this 2404 ** can be done without the lock because its RO 2405 ** and the HUNG state will be static if set. 2406 */ 2407 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) { 2408 txq->ift_last_timer_tick = this_tick; 2409 IFDI_TIMER(ctx, txq->ift_id); 2410 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2411 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2412 (sctx->isc_pause_frames == 0))) 2413 goto hung; 2414 2415 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2416 ifmp_ring_is_stalled(txq->ift_br)) { 2417 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, 2418 ("queue can't be marked as hung if interface is down")); 2419 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2420 } 2421 txq->ift_cleaned_prev = txq->ift_cleaned; 2422 } 2423 /* handle any laggards */ 2424 if (txq->ift_db_pending) 2425 GROUPTASK_ENQUEUE(&txq->ift_task); 2426 2427 sctx->isc_pause_frames = 0; 2428 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2429 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, 2430 txq, txq->ift_timer.c_cpu); 2431 return; 2432 2433 hung: 2434 device_printf(ctx->ifc_dev, 2435 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2436 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2437 STATE_LOCK(ctx); 2438 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2439 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2440 iflib_admin_intr_deferred(ctx); 2441 STATE_UNLOCK(ctx); 2442 } 2443 2444 static uint16_t 2445 iflib_get_mbuf_size_for(unsigned int size) 2446 { 2447 2448 if (size <= MCLBYTES) 2449 return (MCLBYTES); 2450 else 2451 return (MJUMPAGESIZE); 2452 } 2453 2454 static void 2455 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2456 { 2457 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2458 2459 /* 2460 * XXX don't set the max_frame_size to larger 2461 * than the hardware can handle 2462 */ 2463 ctx->ifc_rx_mbuf_sz = 2464 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2465 } 2466 2467 uint32_t 2468 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2469 { 2470 2471 return (ctx->ifc_rx_mbuf_sz); 2472 } 2473 2474 static void 2475 iflib_init_locked(if_ctx_t ctx) 2476 { 2477 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2478 if_t ifp = ctx->ifc_ifp; 2479 iflib_fl_t fl; 2480 iflib_txq_t txq; 2481 iflib_rxq_t rxq; 2482 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2483 2484 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2485 IFDI_INTR_DISABLE(ctx); 2486 2487 /* 2488 * See iflib_stop(). Useful in case iflib_init_locked() is 2489 * called without first calling iflib_stop(). 2490 */ 2491 netmap_disable_all_rings(ifp); 2492 2493 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2494 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2495 /* Set hardware offload abilities */ 2496 if_clearhwassist(ifp); 2497 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2498 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2499 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2500 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2501 if (if_getcapenable(ifp) & IFCAP_TSO4) 2502 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2503 if (if_getcapenable(ifp) & IFCAP_TSO6) 2504 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2505 2506 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 2507 CALLOUT_LOCK(txq); 2508 callout_stop(&txq->ift_timer); 2509 #ifdef DEV_NETMAP 2510 callout_stop(&txq->ift_netmap_timer); 2511 #endif /* DEV_NETMAP */ 2512 CALLOUT_UNLOCK(txq); 2513 (void)iflib_netmap_txq_init(ctx, txq); 2514 } 2515 2516 /* 2517 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2518 * that drivers can use the value when setting up the hardware receive 2519 * buffers. 2520 */ 2521 iflib_calc_rx_mbuf_sz(ctx); 2522 2523 #ifdef INVARIANTS 2524 i = if_getdrvflags(ifp); 2525 #endif 2526 IFDI_INIT(ctx); 2527 MPASS(if_getdrvflags(ifp) == i); 2528 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 2529 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2530 /* This rxq is in netmap mode. Skip normal init. */ 2531 continue; 2532 } 2533 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2534 if (iflib_fl_setup(fl)) { 2535 device_printf(ctx->ifc_dev, 2536 "setting up free list %d failed - " 2537 "check cluster settings\n", j); 2538 goto done; 2539 } 2540 } 2541 } 2542 done: 2543 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2544 IFDI_INTR_ENABLE(ctx); 2545 txq = ctx->ifc_txqs; 2546 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) 2547 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 2548 txq->ift_timer.c_cpu); 2549 2550 /* Re-enable txsync/rxsync. */ 2551 netmap_enable_all_rings(ifp); 2552 } 2553 2554 static int 2555 iflib_media_change(if_t ifp) 2556 { 2557 if_ctx_t ctx = if_getsoftc(ifp); 2558 int err; 2559 2560 CTX_LOCK(ctx); 2561 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2562 iflib_if_init_locked(ctx); 2563 CTX_UNLOCK(ctx); 2564 return (err); 2565 } 2566 2567 static void 2568 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2569 { 2570 if_ctx_t ctx = if_getsoftc(ifp); 2571 2572 CTX_LOCK(ctx); 2573 IFDI_UPDATE_ADMIN_STATUS(ctx); 2574 IFDI_MEDIA_STATUS(ctx, ifmr); 2575 CTX_UNLOCK(ctx); 2576 } 2577 2578 void 2579 iflib_stop(if_ctx_t ctx) 2580 { 2581 iflib_txq_t txq = ctx->ifc_txqs; 2582 iflib_rxq_t rxq = ctx->ifc_rxqs; 2583 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2584 if_shared_ctx_t sctx = ctx->ifc_sctx; 2585 iflib_dma_info_t di; 2586 iflib_fl_t fl; 2587 int i, j; 2588 2589 /* Tell the stack that the interface is no longer active */ 2590 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2591 2592 IFDI_INTR_DISABLE(ctx); 2593 DELAY(1000); 2594 IFDI_STOP(ctx); 2595 DELAY(1000); 2596 2597 /* 2598 * Stop any pending txsync/rxsync and prevent new ones 2599 * form starting. Processes blocked in poll() will get 2600 * POLLERR. 2601 */ 2602 netmap_disable_all_rings(ctx->ifc_ifp); 2603 2604 iflib_debug_reset(); 2605 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2606 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2607 /* make sure all transmitters have completed before proceeding XXX */ 2608 2609 CALLOUT_LOCK(txq); 2610 callout_stop(&txq->ift_timer); 2611 #ifdef DEV_NETMAP 2612 callout_stop(&txq->ift_netmap_timer); 2613 #endif /* DEV_NETMAP */ 2614 CALLOUT_UNLOCK(txq); 2615 2616 /* clean any enqueued buffers */ 2617 iflib_ifmp_purge(txq); 2618 /* Free any existing tx buffers. */ 2619 for (j = 0; j < txq->ift_size; j++) { 2620 iflib_txsd_free(ctx, txq, j); 2621 } 2622 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2623 txq->ift_in_use = txq->ift_gen = txq->ift_no_desc_avail = 0; 2624 if (sctx->isc_flags & IFLIB_PRESERVE_TX_INDICES) 2625 txq->ift_cidx = txq->ift_pidx; 2626 else 2627 txq->ift_cidx = txq->ift_pidx = 0; 2628 2629 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2630 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2631 txq->ift_pullups = 0; 2632 ifmp_ring_reset_stats(txq->ift_br); 2633 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2634 bzero((void *)di->idi_vaddr, di->idi_size); 2635 } 2636 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2637 if (rxq->ifr_task.gt_taskqueue != NULL) 2638 gtaskqueue_drain(rxq->ifr_task.gt_taskqueue, 2639 &rxq->ifr_task.gt_task); 2640 2641 rxq->ifr_cq_cidx = 0; 2642 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2643 bzero((void *)di->idi_vaddr, di->idi_size); 2644 /* also resets the free lists pidx/cidx */ 2645 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2646 iflib_fl_bufs_free(fl); 2647 } 2648 } 2649 2650 static inline caddr_t 2651 calc_next_rxd(iflib_fl_t fl, int cidx) 2652 { 2653 qidx_t size; 2654 int nrxd; 2655 caddr_t start, end, cur, next; 2656 2657 nrxd = fl->ifl_size; 2658 size = fl->ifl_rxd_size; 2659 start = fl->ifl_ifdi->idi_vaddr; 2660 2661 if (__predict_false(size == 0)) 2662 return (start); 2663 cur = start + size*cidx; 2664 end = start + size*nrxd; 2665 next = CACHE_PTR_NEXT(cur); 2666 return (next < end ? next : start); 2667 } 2668 2669 static inline void 2670 prefetch_pkts(iflib_fl_t fl, int cidx) 2671 { 2672 int nextptr; 2673 int nrxd = fl->ifl_size; 2674 caddr_t next_rxd; 2675 2676 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2677 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2678 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2679 next_rxd = calc_next_rxd(fl, cidx); 2680 prefetch(next_rxd); 2681 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2682 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2683 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2684 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2685 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2686 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2687 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2688 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2689 } 2690 2691 static struct mbuf * 2692 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2693 int *pf_rv, if_rxd_info_t ri) 2694 { 2695 bus_dmamap_t map; 2696 iflib_fl_t fl; 2697 caddr_t payload; 2698 struct mbuf *m; 2699 int flid, cidx, len, next; 2700 2701 map = NULL; 2702 flid = irf->irf_flid; 2703 cidx = irf->irf_idx; 2704 fl = &rxq->ifr_fl[flid]; 2705 sd->ifsd_fl = fl; 2706 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2707 fl->ifl_credits--; 2708 #if MEMORY_LOGGING 2709 fl->ifl_m_dequeued++; 2710 #endif 2711 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2712 prefetch_pkts(fl, cidx); 2713 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2714 prefetch(&fl->ifl_sds.ifsd_map[next]); 2715 map = fl->ifl_sds.ifsd_map[cidx]; 2716 2717 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2718 2719 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2720 irf->irf_len != 0) { 2721 payload = *sd->ifsd_cl; 2722 payload += ri->iri_pad; 2723 len = ri->iri_len - ri->iri_pad; 2724 *pf_rv = pfil_mem_in(rxq->pfil, payload, len, ri->iri_ifp, &m); 2725 switch (*pf_rv) { 2726 case PFIL_DROPPED: 2727 case PFIL_CONSUMED: 2728 /* 2729 * The filter ate it. Everything is recycled. 2730 */ 2731 m = NULL; 2732 unload = 0; 2733 break; 2734 case PFIL_REALLOCED: 2735 /* 2736 * The filter copied it. Everything is recycled. 2737 * 'm' points at new mbuf. 2738 */ 2739 unload = 0; 2740 break; 2741 case PFIL_PASS: 2742 /* 2743 * Filter said it was OK, so receive like 2744 * normal 2745 */ 2746 m = fl->ifl_sds.ifsd_m[cidx]; 2747 fl->ifl_sds.ifsd_m[cidx] = NULL; 2748 break; 2749 default: 2750 MPASS(0); 2751 } 2752 } else { 2753 m = fl->ifl_sds.ifsd_m[cidx]; 2754 fl->ifl_sds.ifsd_m[cidx] = NULL; 2755 if (pf_rv != NULL) 2756 *pf_rv = PFIL_PASS; 2757 } 2758 2759 if (unload && irf->irf_len != 0) 2760 bus_dmamap_unload(fl->ifl_buf_tag, map); 2761 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2762 if (__predict_false(fl->ifl_cidx == 0)) 2763 fl->ifl_gen = 0; 2764 bit_clear(fl->ifl_rx_bitmap, cidx); 2765 return (m); 2766 } 2767 2768 static struct mbuf * 2769 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2770 { 2771 struct mbuf *m, *mh, *mt; 2772 caddr_t cl; 2773 int *pf_rv_ptr, flags, i, padlen; 2774 bool consumed; 2775 2776 i = 0; 2777 mh = NULL; 2778 consumed = false; 2779 *pf_rv = PFIL_PASS; 2780 pf_rv_ptr = pf_rv; 2781 do { 2782 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2783 pf_rv_ptr, ri); 2784 2785 MPASS(*sd->ifsd_cl != NULL); 2786 2787 /* 2788 * Exclude zero-length frags & frags from 2789 * packets the filter has consumed or dropped 2790 */ 2791 if (ri->iri_frags[i].irf_len == 0 || consumed || 2792 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2793 if (mh == NULL) { 2794 /* everything saved here */ 2795 consumed = true; 2796 pf_rv_ptr = NULL; 2797 continue; 2798 } 2799 /* XXX we can save the cluster here, but not the mbuf */ 2800 m_init(m, M_NOWAIT, MT_DATA, 0); 2801 m_free(m); 2802 continue; 2803 } 2804 if (mh == NULL) { 2805 flags = M_PKTHDR|M_EXT; 2806 mh = mt = m; 2807 padlen = ri->iri_pad; 2808 } else { 2809 flags = M_EXT; 2810 mt->m_next = m; 2811 mt = m; 2812 /* assuming padding is only on the first fragment */ 2813 padlen = 0; 2814 } 2815 cl = *sd->ifsd_cl; 2816 *sd->ifsd_cl = NULL; 2817 2818 /* Can these two be made one ? */ 2819 m_init(m, M_NOWAIT, MT_DATA, flags); 2820 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2821 /* 2822 * These must follow m_init and m_cljset 2823 */ 2824 m->m_data += padlen; 2825 ri->iri_len -= padlen; 2826 m->m_len = ri->iri_frags[i].irf_len; 2827 } while (++i < ri->iri_nfrags); 2828 2829 return (mh); 2830 } 2831 2832 /* 2833 * Process one software descriptor 2834 */ 2835 static struct mbuf * 2836 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2837 { 2838 struct if_rxsd sd; 2839 struct mbuf *m; 2840 int pf_rv; 2841 2842 /* should I merge this back in now that the two paths are basically duplicated? */ 2843 if (ri->iri_nfrags == 1 && 2844 ri->iri_frags[0].irf_len != 0 && 2845 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2846 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2847 &pf_rv, ri); 2848 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2849 return (m); 2850 if (pf_rv == PFIL_PASS) { 2851 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2852 #ifndef __NO_STRICT_ALIGNMENT 2853 if (!IP_ALIGNED(m) && ri->iri_pad == 0) 2854 m->m_data += 2; 2855 #endif 2856 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2857 m->m_len = ri->iri_frags[0].irf_len; 2858 m->m_data += ri->iri_pad; 2859 ri->iri_len -= ri->iri_pad; 2860 } 2861 } else { 2862 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2863 if (m == NULL) 2864 return (NULL); 2865 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2866 return (m); 2867 } 2868 m->m_pkthdr.len = ri->iri_len; 2869 m->m_pkthdr.rcvif = ri->iri_ifp; 2870 m->m_flags |= ri->iri_flags; 2871 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2872 m->m_pkthdr.flowid = ri->iri_flowid; 2873 M_HASHTYPE_SET(m, ri->iri_rsstype); 2874 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2875 m->m_pkthdr.csum_data = ri->iri_csum_data; 2876 return (m); 2877 } 2878 2879 #if defined(INET6) || defined(INET) 2880 static void 2881 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2882 { 2883 CURVNET_SET(if_getvnet(lc->ifp)); 2884 #if defined(INET6) 2885 *v6 = V_ip6_forwarding; 2886 #endif 2887 #if defined(INET) 2888 *v4 = V_ipforwarding; 2889 #endif 2890 CURVNET_RESTORE(); 2891 } 2892 2893 /* 2894 * Returns true if it's possible this packet could be LROed. 2895 * if it returns false, it is guaranteed that tcp_lro_rx() 2896 * would not return zero. 2897 */ 2898 static bool 2899 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2900 { 2901 struct ether_header *eh; 2902 2903 eh = mtod(m, struct ether_header *); 2904 switch (eh->ether_type) { 2905 #if defined(INET6) 2906 case htons(ETHERTYPE_IPV6): 2907 return (!v6_forwarding); 2908 #endif 2909 #if defined (INET) 2910 case htons(ETHERTYPE_IP): 2911 return (!v4_forwarding); 2912 #endif 2913 } 2914 2915 return false; 2916 } 2917 #else 2918 static void 2919 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2920 { 2921 } 2922 #endif 2923 2924 static void 2925 _task_fn_rx_watchdog(void *context) 2926 { 2927 iflib_rxq_t rxq = context; 2928 2929 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2930 } 2931 2932 static uint8_t 2933 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2934 { 2935 if_t ifp; 2936 if_ctx_t ctx = rxq->ifr_ctx; 2937 if_shared_ctx_t sctx = ctx->ifc_sctx; 2938 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2939 int avail, i; 2940 qidx_t *cidxp; 2941 struct if_rxd_info ri; 2942 int err, budget_left, rx_bytes, rx_pkts; 2943 iflib_fl_t fl; 2944 int lro_enabled; 2945 bool v4_forwarding, v6_forwarding, lro_possible; 2946 uint8_t retval = 0; 2947 2948 /* 2949 * XXX early demux data packets so that if_input processing only handles 2950 * acks in interrupt context 2951 */ 2952 struct mbuf *m, *mh, *mt, *mf; 2953 2954 NET_EPOCH_ASSERT(); 2955 2956 lro_possible = v4_forwarding = v6_forwarding = false; 2957 ifp = ctx->ifc_ifp; 2958 mh = mt = NULL; 2959 MPASS(budget > 0); 2960 rx_pkts = rx_bytes = 0; 2961 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2962 cidxp = &rxq->ifr_cq_cidx; 2963 else 2964 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2965 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2966 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2967 retval |= iflib_fl_refill_all(ctx, fl); 2968 DBG_COUNTER_INC(rx_unavail); 2969 return (retval); 2970 } 2971 2972 /* pfil needs the vnet to be set */ 2973 CURVNET_SET_QUIET(if_getvnet(ifp)); 2974 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2975 if (__predict_false(!CTX_ACTIVE(ctx))) { 2976 DBG_COUNTER_INC(rx_ctx_inactive); 2977 break; 2978 } 2979 /* 2980 * Reset client set fields to their default values 2981 */ 2982 rxd_info_zero(&ri); 2983 ri.iri_qsidx = rxq->ifr_id; 2984 ri.iri_cidx = *cidxp; 2985 ri.iri_ifp = ifp; 2986 ri.iri_frags = rxq->ifr_frags; 2987 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2988 2989 if (err) 2990 goto err; 2991 rx_pkts += 1; 2992 rx_bytes += ri.iri_len; 2993 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2994 *cidxp = ri.iri_cidx; 2995 /* Update our consumer index */ 2996 /* XXX NB: shurd - check if this is still safe */ 2997 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2998 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2999 /* was this only a completion queue message? */ 3000 if (__predict_false(ri.iri_nfrags == 0)) 3001 continue; 3002 } 3003 MPASS(ri.iri_nfrags != 0); 3004 MPASS(ri.iri_len != 0); 3005 3006 /* will advance the cidx on the corresponding free lists */ 3007 m = iflib_rxd_pkt_get(rxq, &ri); 3008 avail--; 3009 budget_left--; 3010 if (avail == 0 && budget_left) 3011 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 3012 3013 if (__predict_false(m == NULL)) 3014 continue; 3015 3016 /* imm_pkt: -- cxgb */ 3017 if (mh == NULL) 3018 mh = mt = m; 3019 else { 3020 mt->m_nextpkt = m; 3021 mt = m; 3022 } 3023 } 3024 CURVNET_RESTORE(); 3025 /* make sure that we can refill faster than drain */ 3026 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3027 retval |= iflib_fl_refill_all(ctx, fl); 3028 3029 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 3030 if (lro_enabled) 3031 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 3032 mt = mf = NULL; 3033 while (mh != NULL) { 3034 m = mh; 3035 mh = mh->m_nextpkt; 3036 m->m_nextpkt = NULL; 3037 #ifndef __NO_STRICT_ALIGNMENT 3038 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 3039 continue; 3040 #endif 3041 #if defined(INET6) || defined(INET) 3042 if (lro_enabled) { 3043 if (!lro_possible) { 3044 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 3045 if (lro_possible && mf != NULL) { 3046 if_input(ifp, mf); 3047 DBG_COUNTER_INC(rx_if_input); 3048 mt = mf = NULL; 3049 } 3050 } 3051 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 3052 (CSUM_L4_CALC|CSUM_L4_VALID)) { 3053 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 3054 continue; 3055 } 3056 } 3057 #endif 3058 if (lro_possible) { 3059 if_input(ifp, m); 3060 DBG_COUNTER_INC(rx_if_input); 3061 continue; 3062 } 3063 3064 if (mf == NULL) 3065 mf = m; 3066 if (mt != NULL) 3067 mt->m_nextpkt = m; 3068 mt = m; 3069 } 3070 if (mf != NULL) { 3071 if_input(ifp, mf); 3072 DBG_COUNTER_INC(rx_if_input); 3073 } 3074 3075 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 3076 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 3077 3078 /* 3079 * Flush any outstanding LRO work 3080 */ 3081 #if defined(INET6) || defined(INET) 3082 tcp_lro_flush_all(&rxq->ifr_lc); 3083 #endif 3084 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 3085 retval |= IFLIB_RXEOF_MORE; 3086 return (retval); 3087 err: 3088 STATE_LOCK(ctx); 3089 ctx->ifc_flags |= IFC_DO_RESET; 3090 iflib_admin_intr_deferred(ctx); 3091 STATE_UNLOCK(ctx); 3092 return (0); 3093 } 3094 3095 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 3096 static inline qidx_t 3097 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 3098 { 3099 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3100 qidx_t minthresh = txq->ift_size / 8; 3101 if (in_use > 4*minthresh) 3102 return (notify_count); 3103 if (in_use > 2*minthresh) 3104 return (notify_count >> 1); 3105 if (in_use > minthresh) 3106 return (notify_count >> 3); 3107 return (0); 3108 } 3109 3110 static inline qidx_t 3111 txq_max_rs_deferred(iflib_txq_t txq) 3112 { 3113 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3114 qidx_t minthresh = txq->ift_size / 8; 3115 if (txq->ift_in_use > 4*minthresh) 3116 return (notify_count); 3117 if (txq->ift_in_use > 2*minthresh) 3118 return (notify_count >> 1); 3119 if (txq->ift_in_use > minthresh) 3120 return (notify_count >> 2); 3121 return (2); 3122 } 3123 3124 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 3125 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 3126 3127 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 3128 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 3129 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 3130 3131 /* forward compatibility for cxgb */ 3132 #define FIRST_QSET(ctx) 0 3133 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3134 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3135 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3136 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3137 3138 /* XXX we should be setting this to something other than zero */ 3139 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 3140 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3141 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3142 3143 static inline bool 3144 iflib_txd_db_check(iflib_txq_t txq, int ring) 3145 { 3146 if_ctx_t ctx = txq->ift_ctx; 3147 qidx_t dbval, max; 3148 3149 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use); 3150 3151 /* force || threshold exceeded || at the edge of the ring */ 3152 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2)) { 3153 3154 /* 3155 * 'npending' is used if the card's doorbell is in terms of the number of descriptors 3156 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the 3157 * producer index explicitly (INTC). 3158 */ 3159 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3160 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3161 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3162 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3163 3164 /* 3165 * Absent bugs there are zero packets pending so reset pending counts to zero. 3166 */ 3167 txq->ift_db_pending = txq->ift_npending = 0; 3168 return (true); 3169 } 3170 return (false); 3171 } 3172 3173 #ifdef PKT_DEBUG 3174 static void 3175 print_pkt(if_pkt_info_t pi) 3176 { 3177 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3178 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3179 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3180 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3181 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3182 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3183 } 3184 #endif 3185 3186 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3187 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3188 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3189 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3190 3191 /** 3192 * Parses out ethernet header information in the given mbuf. 3193 * Returns in pi: ipi_etype (EtherType) and ipi_ehdrlen (Ethernet header length) 3194 * 3195 * This will account for the VLAN header if present. 3196 * 3197 * XXX: This doesn't handle QinQ, which could prevent TX offloads for those 3198 * types of packets. 3199 */ 3200 static int 3201 iflib_parse_ether_header(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3202 { 3203 struct ether_vlan_header *eh; 3204 struct mbuf *m; 3205 3206 m = *mp; 3207 if (__predict_false(m->m_len < sizeof(*eh))) { 3208 (*pullups)++; 3209 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3210 return (ENOMEM); 3211 } 3212 eh = mtod(m, struct ether_vlan_header *); 3213 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3214 pi->ipi_etype = ntohs(eh->evl_proto); 3215 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3216 } else { 3217 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3218 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3219 } 3220 *mp = m; 3221 3222 return (0); 3223 } 3224 3225 /** 3226 * Parse up to the L3 header and extract IPv4/IPv6 header information into pi. 3227 * Currently this information includes: IP ToS value, IP header version/presence 3228 * 3229 * This is missing some checks and doesn't edit the packet content as it goes, 3230 * unlike iflib_parse_header(), in order to keep the amount of code here minimal. 3231 */ 3232 static int 3233 iflib_parse_header_partial(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3234 { 3235 struct mbuf *m; 3236 int err; 3237 3238 *pullups = 0; 3239 m = *mp; 3240 if (!M_WRITABLE(m)) { 3241 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3242 return (ENOMEM); 3243 } else { 3244 m_freem(*mp); 3245 DBG_COUNTER_INC(tx_frees); 3246 *mp = m; 3247 } 3248 } 3249 3250 /* Fills out pi->ipi_etype */ 3251 err = iflib_parse_ether_header(pi, mp, pullups); 3252 if (err) 3253 return (err); 3254 m = *mp; 3255 3256 switch (pi->ipi_etype) { 3257 #ifdef INET 3258 case ETHERTYPE_IP: 3259 { 3260 struct mbuf *n; 3261 struct ip *ip = NULL; 3262 int miniplen; 3263 3264 miniplen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip)); 3265 if (__predict_false(m->m_len < miniplen)) { 3266 /* 3267 * Check for common case where the first mbuf only contains 3268 * the Ethernet header 3269 */ 3270 if (m->m_len == pi->ipi_ehdrlen) { 3271 n = m->m_next; 3272 MPASS(n); 3273 /* If next mbuf contains at least the minimal IP header, then stop */ 3274 if (n->m_len >= sizeof(*ip)) { 3275 ip = (struct ip *)n->m_data; 3276 } else { 3277 (*pullups)++; 3278 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3279 return (ENOMEM); 3280 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3281 } 3282 } else { 3283 (*pullups)++; 3284 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3285 return (ENOMEM); 3286 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3287 } 3288 } else { 3289 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3290 } 3291 3292 /* Have the IPv4 header w/ no options here */ 3293 pi->ipi_ip_hlen = ip->ip_hl << 2; 3294 pi->ipi_ipproto = ip->ip_p; 3295 pi->ipi_ip_tos = ip->ip_tos; 3296 pi->ipi_flags |= IPI_TX_IPV4; 3297 3298 break; 3299 } 3300 #endif 3301 #ifdef INET6 3302 case ETHERTYPE_IPV6: 3303 { 3304 struct ip6_hdr *ip6; 3305 3306 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3307 (*pullups)++; 3308 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3309 return (ENOMEM); 3310 } 3311 ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3312 3313 /* Have the IPv6 fixed header here */ 3314 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3315 pi->ipi_ipproto = ip6->ip6_nxt; 3316 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3317 pi->ipi_flags |= IPI_TX_IPV6; 3318 3319 break; 3320 } 3321 #endif 3322 default: 3323 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3324 pi->ipi_ip_hlen = 0; 3325 break; 3326 } 3327 *mp = m; 3328 3329 return (0); 3330 3331 } 3332 3333 static int 3334 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3335 { 3336 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3337 struct mbuf *m; 3338 int err; 3339 3340 m = *mp; 3341 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3342 M_WRITABLE(m) == 0) { 3343 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3344 return (ENOMEM); 3345 } else { 3346 m_freem(*mp); 3347 DBG_COUNTER_INC(tx_frees); 3348 *mp = m; 3349 } 3350 } 3351 3352 /* Fills out pi->ipi_etype */ 3353 err = iflib_parse_ether_header(pi, mp, &txq->ift_pullups); 3354 if (__predict_false(err)) 3355 return (err); 3356 m = *mp; 3357 3358 switch (pi->ipi_etype) { 3359 #ifdef INET 3360 case ETHERTYPE_IP: 3361 { 3362 struct mbuf *n; 3363 struct ip *ip = NULL; 3364 struct tcphdr *th = NULL; 3365 int minthlen; 3366 3367 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3368 if (__predict_false(m->m_len < minthlen)) { 3369 /* 3370 * if this code bloat is causing too much of a hit 3371 * move it to a separate function and mark it noinline 3372 */ 3373 if (m->m_len == pi->ipi_ehdrlen) { 3374 n = m->m_next; 3375 MPASS(n); 3376 if (n->m_len >= sizeof(*ip)) { 3377 ip = (struct ip *)n->m_data; 3378 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3379 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3380 } else { 3381 txq->ift_pullups++; 3382 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3383 return (ENOMEM); 3384 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3385 } 3386 } else { 3387 txq->ift_pullups++; 3388 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3389 return (ENOMEM); 3390 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3391 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3392 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3393 } 3394 } else { 3395 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3396 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3397 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3398 } 3399 pi->ipi_ip_hlen = ip->ip_hl << 2; 3400 pi->ipi_ipproto = ip->ip_p; 3401 pi->ipi_ip_tos = ip->ip_tos; 3402 pi->ipi_flags |= IPI_TX_IPV4; 3403 3404 /* TCP checksum offload may require TCP header length */ 3405 if (IS_TX_OFFLOAD4(pi)) { 3406 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3407 if (__predict_false(th == NULL)) { 3408 txq->ift_pullups++; 3409 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3410 return (ENOMEM); 3411 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3412 } 3413 pi->ipi_tcp_hflags = th->th_flags; 3414 pi->ipi_tcp_hlen = th->th_off << 2; 3415 pi->ipi_tcp_seq = th->th_seq; 3416 } 3417 if (IS_TSO4(pi)) { 3418 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3419 return (ENXIO); 3420 /* 3421 * TSO always requires hardware checksum offload. 3422 */ 3423 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3424 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3425 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3426 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3427 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3428 ip->ip_sum = 0; 3429 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3430 } 3431 } 3432 } 3433 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3434 ip->ip_sum = 0; 3435 3436 break; 3437 } 3438 #endif 3439 #ifdef INET6 3440 case ETHERTYPE_IPV6: 3441 { 3442 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3443 struct tcphdr *th; 3444 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3445 3446 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3447 txq->ift_pullups++; 3448 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3449 return (ENOMEM); 3450 } 3451 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3452 3453 /* XXX-BZ this will go badly in case of ext hdrs. */ 3454 pi->ipi_ipproto = ip6->ip6_nxt; 3455 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3456 pi->ipi_flags |= IPI_TX_IPV6; 3457 3458 /* TCP checksum offload may require TCP header length */ 3459 if (IS_TX_OFFLOAD6(pi)) { 3460 if (pi->ipi_ipproto == IPPROTO_TCP) { 3461 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3462 txq->ift_pullups++; 3463 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3464 return (ENOMEM); 3465 } 3466 pi->ipi_tcp_hflags = th->th_flags; 3467 pi->ipi_tcp_hlen = th->th_off << 2; 3468 pi->ipi_tcp_seq = th->th_seq; 3469 } 3470 if (IS_TSO6(pi)) { 3471 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3472 return (ENXIO); 3473 /* 3474 * TSO always requires hardware checksum offload. 3475 */ 3476 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3477 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3478 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3479 } 3480 } 3481 break; 3482 } 3483 #endif 3484 default: 3485 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3486 pi->ipi_ip_hlen = 0; 3487 break; 3488 } 3489 *mp = m; 3490 3491 return (0); 3492 } 3493 3494 /* 3495 * If dodgy hardware rejects the scatter gather chain we've handed it 3496 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3497 * m_defrag'd mbufs 3498 */ 3499 static __noinline struct mbuf * 3500 iflib_remove_mbuf(iflib_txq_t txq) 3501 { 3502 int ntxd, pidx; 3503 struct mbuf *m, **ifsd_m; 3504 3505 ifsd_m = txq->ift_sds.ifsd_m; 3506 ntxd = txq->ift_size; 3507 pidx = txq->ift_pidx & (ntxd - 1); 3508 ifsd_m = txq->ift_sds.ifsd_m; 3509 m = ifsd_m[pidx]; 3510 ifsd_m[pidx] = NULL; 3511 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3512 if (txq->ift_sds.ifsd_tso_map != NULL) 3513 bus_dmamap_unload(txq->ift_tso_buf_tag, 3514 txq->ift_sds.ifsd_tso_map[pidx]); 3515 #if MEMORY_LOGGING 3516 txq->ift_dequeued++; 3517 #endif 3518 return (m); 3519 } 3520 3521 static inline caddr_t 3522 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3523 { 3524 qidx_t size; 3525 int ntxd; 3526 caddr_t start, end, cur, next; 3527 3528 ntxd = txq->ift_size; 3529 size = txq->ift_txd_size[qid]; 3530 start = txq->ift_ifdi[qid].idi_vaddr; 3531 3532 if (__predict_false(size == 0)) 3533 return (start); 3534 cur = start + size*cidx; 3535 end = start + size*ntxd; 3536 next = CACHE_PTR_NEXT(cur); 3537 return (next < end ? next : start); 3538 } 3539 3540 /* 3541 * Pad an mbuf to ensure a minimum ethernet frame size. 3542 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3543 */ 3544 static __noinline int 3545 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3546 { 3547 /* 3548 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3549 * and ARP message is the smallest common payload I can think of 3550 */ 3551 static char pad[18]; /* just zeros */ 3552 int n; 3553 struct mbuf *new_head; 3554 3555 if (!M_WRITABLE(*m_head)) { 3556 new_head = m_dup(*m_head, M_NOWAIT); 3557 if (new_head == NULL) { 3558 m_freem(*m_head); 3559 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3560 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3561 DBG_COUNTER_INC(tx_frees); 3562 return ENOMEM; 3563 } 3564 m_freem(*m_head); 3565 *m_head = new_head; 3566 } 3567 3568 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3569 n > 0; n -= sizeof(pad)) 3570 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3571 break; 3572 3573 if (n > 0) { 3574 m_freem(*m_head); 3575 device_printf(dev, "cannot pad short frame\n"); 3576 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3577 DBG_COUNTER_INC(tx_frees); 3578 return (ENOBUFS); 3579 } 3580 3581 return 0; 3582 } 3583 3584 static int 3585 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3586 { 3587 if_ctx_t ctx; 3588 if_shared_ctx_t sctx; 3589 if_softc_ctx_t scctx; 3590 bus_dma_tag_t buf_tag; 3591 bus_dma_segment_t *segs; 3592 struct mbuf *m_head, **ifsd_m; 3593 void *next_txd; 3594 bus_dmamap_t map; 3595 struct if_pkt_info pi; 3596 int remap = 0; 3597 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3598 3599 ctx = txq->ift_ctx; 3600 sctx = ctx->ifc_sctx; 3601 scctx = &ctx->ifc_softc_ctx; 3602 segs = txq->ift_segs; 3603 ntxd = txq->ift_size; 3604 m_head = *m_headp; 3605 map = NULL; 3606 3607 /* 3608 * If we're doing TSO the next descriptor to clean may be quite far ahead 3609 */ 3610 cidx = txq->ift_cidx; 3611 pidx = txq->ift_pidx; 3612 if (ctx->ifc_flags & IFC_PREFETCH) { 3613 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3614 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3615 next_txd = calc_next_txd(txq, cidx, 0); 3616 prefetch(next_txd); 3617 } 3618 3619 /* prefetch the next cache line of mbuf pointers and flags */ 3620 prefetch(&txq->ift_sds.ifsd_m[next]); 3621 prefetch(&txq->ift_sds.ifsd_map[next]); 3622 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3623 } 3624 map = txq->ift_sds.ifsd_map[pidx]; 3625 ifsd_m = txq->ift_sds.ifsd_m; 3626 3627 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3628 buf_tag = txq->ift_tso_buf_tag; 3629 max_segs = scctx->isc_tx_tso_segments_max; 3630 map = txq->ift_sds.ifsd_tso_map[pidx]; 3631 MPASS(buf_tag != NULL); 3632 MPASS(max_segs > 0); 3633 } else { 3634 buf_tag = txq->ift_buf_tag; 3635 max_segs = scctx->isc_tx_nsegments; 3636 map = txq->ift_sds.ifsd_map[pidx]; 3637 } 3638 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3639 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3640 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3641 if (err) { 3642 DBG_COUNTER_INC(encap_txd_encap_fail); 3643 return err; 3644 } 3645 } 3646 m_head = *m_headp; 3647 3648 pkt_info_zero(&pi); 3649 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3650 pi.ipi_pidx = pidx; 3651 pi.ipi_qsidx = txq->ift_id; 3652 pi.ipi_len = m_head->m_pkthdr.len; 3653 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3654 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3655 3656 /* deliberate bitwise OR to make one condition */ 3657 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3658 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3659 DBG_COUNTER_INC(encap_txd_encap_fail); 3660 return (err); 3661 } 3662 m_head = *m_headp; 3663 } 3664 3665 retry: 3666 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3667 BUS_DMA_NOWAIT); 3668 defrag: 3669 if (__predict_false(err)) { 3670 switch (err) { 3671 case EFBIG: 3672 /* try collapse once and defrag once */ 3673 if (remap == 0) { 3674 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3675 /* try defrag if collapsing fails */ 3676 if (m_head == NULL) 3677 remap++; 3678 } 3679 if (remap == 1) { 3680 txq->ift_mbuf_defrag++; 3681 m_head = m_defrag(*m_headp, M_NOWAIT); 3682 } 3683 /* 3684 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3685 * failed to map an mbuf that was run through m_defrag 3686 */ 3687 MPASS(remap <= 1); 3688 if (__predict_false(m_head == NULL || remap > 1)) 3689 goto defrag_failed; 3690 remap++; 3691 *m_headp = m_head; 3692 goto retry; 3693 break; 3694 case ENOMEM: 3695 txq->ift_no_tx_dma_setup++; 3696 break; 3697 default: 3698 txq->ift_no_tx_dma_setup++; 3699 m_freem(*m_headp); 3700 DBG_COUNTER_INC(tx_frees); 3701 *m_headp = NULL; 3702 break; 3703 } 3704 txq->ift_map_failed++; 3705 DBG_COUNTER_INC(encap_load_mbuf_fail); 3706 DBG_COUNTER_INC(encap_txd_encap_fail); 3707 return (err); 3708 } 3709 ifsd_m[pidx] = m_head; 3710 /* 3711 * XXX assumes a 1 to 1 relationship between segments and 3712 * descriptors - this does not hold true on all drivers, e.g. 3713 * cxgb 3714 */ 3715 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3716 txq->ift_no_desc_avail++; 3717 bus_dmamap_unload(buf_tag, map); 3718 DBG_COUNTER_INC(encap_txq_avail_fail); 3719 DBG_COUNTER_INC(encap_txd_encap_fail); 3720 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3721 GROUPTASK_ENQUEUE(&txq->ift_task); 3722 return (ENOBUFS); 3723 } 3724 /* 3725 * On Intel cards we can greatly reduce the number of TX interrupts 3726 * we see by only setting report status on every Nth descriptor. 3727 * However, this also means that the driver will need to keep track 3728 * of the descriptors that RS was set on to check them for the DD bit. 3729 */ 3730 txq->ift_rs_pending += nsegs + 1; 3731 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3732 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3733 pi.ipi_flags |= IPI_TX_INTR; 3734 txq->ift_rs_pending = 0; 3735 } 3736 3737 pi.ipi_segs = segs; 3738 pi.ipi_nsegs = nsegs; 3739 3740 MPASS(pidx >= 0 && pidx < txq->ift_size); 3741 #ifdef PKT_DEBUG 3742 print_pkt(&pi); 3743 #endif 3744 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3745 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3746 DBG_COUNTER_INC(tx_encap); 3747 MPASS(pi.ipi_new_pidx < txq->ift_size); 3748 3749 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3750 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3751 ndesc += txq->ift_size; 3752 txq->ift_gen = 1; 3753 } 3754 /* 3755 * drivers can need as many as 3756 * two sentinels 3757 */ 3758 MPASS(ndesc <= pi.ipi_nsegs + 2); 3759 MPASS(pi.ipi_new_pidx != pidx); 3760 MPASS(ndesc > 0); 3761 txq->ift_in_use += ndesc; 3762 txq->ift_db_pending += ndesc; 3763 3764 /* 3765 * We update the last software descriptor again here because there may 3766 * be a sentinel and/or there may be more mbufs than segments 3767 */ 3768 txq->ift_pidx = pi.ipi_new_pidx; 3769 txq->ift_npending += pi.ipi_ndescs; 3770 } else { 3771 *m_headp = m_head = iflib_remove_mbuf(txq); 3772 if (err == EFBIG) { 3773 txq->ift_txd_encap_efbig++; 3774 if (remap < 2) { 3775 remap = 1; 3776 goto defrag; 3777 } 3778 } 3779 goto defrag_failed; 3780 } 3781 /* 3782 * err can't possibly be non-zero here, so we don't neet to test it 3783 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3784 */ 3785 return (err); 3786 3787 defrag_failed: 3788 txq->ift_mbuf_defrag_failed++; 3789 txq->ift_map_failed++; 3790 m_freem(*m_headp); 3791 DBG_COUNTER_INC(tx_frees); 3792 *m_headp = NULL; 3793 DBG_COUNTER_INC(encap_txd_encap_fail); 3794 return (ENOMEM); 3795 } 3796 3797 static void 3798 iflib_tx_desc_free(iflib_txq_t txq, int n) 3799 { 3800 uint32_t qsize, cidx, mask, gen; 3801 struct mbuf *m, **ifsd_m; 3802 bool do_prefetch; 3803 3804 cidx = txq->ift_cidx; 3805 gen = txq->ift_gen; 3806 qsize = txq->ift_size; 3807 mask = qsize-1; 3808 ifsd_m = txq->ift_sds.ifsd_m; 3809 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3810 3811 while (n-- > 0) { 3812 if (do_prefetch) { 3813 prefetch(ifsd_m[(cidx + 3) & mask]); 3814 prefetch(ifsd_m[(cidx + 4) & mask]); 3815 } 3816 if ((m = ifsd_m[cidx]) != NULL) { 3817 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3818 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3819 bus_dmamap_sync(txq->ift_tso_buf_tag, 3820 txq->ift_sds.ifsd_tso_map[cidx], 3821 BUS_DMASYNC_POSTWRITE); 3822 bus_dmamap_unload(txq->ift_tso_buf_tag, 3823 txq->ift_sds.ifsd_tso_map[cidx]); 3824 } else { 3825 bus_dmamap_sync(txq->ift_buf_tag, 3826 txq->ift_sds.ifsd_map[cidx], 3827 BUS_DMASYNC_POSTWRITE); 3828 bus_dmamap_unload(txq->ift_buf_tag, 3829 txq->ift_sds.ifsd_map[cidx]); 3830 } 3831 /* XXX we don't support any drivers that batch packets yet */ 3832 MPASS(m->m_nextpkt == NULL); 3833 m_freem(m); 3834 ifsd_m[cidx] = NULL; 3835 #if MEMORY_LOGGING 3836 txq->ift_dequeued++; 3837 #endif 3838 DBG_COUNTER_INC(tx_frees); 3839 } 3840 if (__predict_false(++cidx == qsize)) { 3841 cidx = 0; 3842 gen = 0; 3843 } 3844 } 3845 txq->ift_cidx = cidx; 3846 txq->ift_gen = gen; 3847 } 3848 3849 static __inline int 3850 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3851 { 3852 int reclaim; 3853 if_ctx_t ctx = txq->ift_ctx; 3854 3855 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3856 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3857 3858 /* 3859 * Need a rate-limiting check so that this isn't called every time 3860 */ 3861 iflib_tx_credits_update(ctx, txq); 3862 reclaim = DESC_RECLAIMABLE(txq); 3863 3864 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3865 #ifdef INVARIANTS 3866 if (iflib_verbose_debug) { 3867 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3868 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3869 reclaim, thresh); 3870 } 3871 #endif 3872 return (0); 3873 } 3874 iflib_tx_desc_free(txq, reclaim); 3875 txq->ift_cleaned += reclaim; 3876 txq->ift_in_use -= reclaim; 3877 3878 return (reclaim); 3879 } 3880 3881 static struct mbuf ** 3882 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3883 { 3884 int next, size; 3885 struct mbuf **items; 3886 3887 size = r->size; 3888 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3889 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3890 3891 prefetch(items[(cidx + offset) & (size-1)]); 3892 if (remaining > 1) { 3893 prefetch2cachelines(&items[next]); 3894 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3895 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3896 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3897 } 3898 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3899 } 3900 3901 static void 3902 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3903 { 3904 3905 ifmp_ring_check_drainage(txq->ift_br, budget); 3906 } 3907 3908 static uint32_t 3909 iflib_txq_can_drain(struct ifmp_ring *r) 3910 { 3911 iflib_txq_t txq = r->cookie; 3912 if_ctx_t ctx = txq->ift_ctx; 3913 3914 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3915 return (1); 3916 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3917 BUS_DMASYNC_POSTREAD); 3918 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3919 false)); 3920 } 3921 3922 static uint32_t 3923 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3924 { 3925 iflib_txq_t txq = r->cookie; 3926 if_ctx_t ctx = txq->ift_ctx; 3927 if_t ifp = ctx->ifc_ifp; 3928 struct mbuf *m, **mp; 3929 int avail, bytes_sent, skipped, count, err, i; 3930 int mcast_sent, pkt_sent, reclaimed; 3931 bool do_prefetch, rang, ring; 3932 3933 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3934 !LINK_ACTIVE(ctx))) { 3935 DBG_COUNTER_INC(txq_drain_notready); 3936 return (0); 3937 } 3938 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3939 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending); 3940 avail = IDXDIFF(pidx, cidx, r->size); 3941 3942 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3943 /* 3944 * The driver is unloading so we need to free all pending packets. 3945 */ 3946 DBG_COUNTER_INC(txq_drain_flushing); 3947 for (i = 0; i < avail; i++) { 3948 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3949 m_freem(r->items[(cidx + i) & (r->size-1)]); 3950 r->items[(cidx + i) & (r->size-1)] = NULL; 3951 } 3952 return (avail); 3953 } 3954 3955 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3956 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3957 CALLOUT_LOCK(txq); 3958 callout_stop(&txq->ift_timer); 3959 CALLOUT_UNLOCK(txq); 3960 DBG_COUNTER_INC(txq_drain_oactive); 3961 return (0); 3962 } 3963 3964 /* 3965 * If we've reclaimed any packets this queue cannot be hung. 3966 */ 3967 if (reclaimed) 3968 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3969 skipped = mcast_sent = bytes_sent = pkt_sent = 0; 3970 count = MIN(avail, TX_BATCH_SIZE); 3971 #ifdef INVARIANTS 3972 if (iflib_verbose_debug) 3973 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3974 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3975 #endif 3976 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3977 err = 0; 3978 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx) + 2; i++) { 3979 int rem = do_prefetch ? count - i : 0; 3980 3981 mp = _ring_peek_one(r, cidx, i, rem); 3982 MPASS(mp != NULL && *mp != NULL); 3983 3984 /* 3985 * Completion interrupts will use the address of the txq 3986 * as a sentinel to enqueue _something_ in order to acquire 3987 * the lock on the mp_ring (there's no direct lock call). 3988 * We obviously whave to check for these sentinel cases 3989 * and skip them. 3990 */ 3991 if (__predict_false(*mp == (struct mbuf *)txq)) { 3992 skipped++; 3993 continue; 3994 } 3995 err = iflib_encap(txq, mp); 3996 if (__predict_false(err)) { 3997 /* no room - bail out */ 3998 if (err == ENOBUFS) 3999 break; 4000 skipped++; 4001 /* we can't send this packet - skip it */ 4002 continue; 4003 } 4004 pkt_sent++; 4005 m = *mp; 4006 DBG_COUNTER_INC(tx_sent); 4007 bytes_sent += m->m_pkthdr.len; 4008 mcast_sent += !!(m->m_flags & M_MCAST); 4009 4010 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))) 4011 break; 4012 ETHER_BPF_MTAP(ifp, m); 4013 rang = iflib_txd_db_check(txq, false); 4014 } 4015 4016 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 4017 ring = rang ? false : (iflib_min_tx_latency | err); 4018 iflib_txd_db_check(txq, ring); 4019 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 4020 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 4021 if (mcast_sent) 4022 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 4023 #ifdef INVARIANTS 4024 if (iflib_verbose_debug) 4025 printf("consumed=%d\n", skipped + pkt_sent); 4026 #endif 4027 return (skipped + pkt_sent); 4028 } 4029 4030 static uint32_t 4031 iflib_txq_drain_always(struct ifmp_ring *r) 4032 { 4033 return (1); 4034 } 4035 4036 static uint32_t 4037 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 4038 { 4039 int i, avail; 4040 struct mbuf **mp; 4041 iflib_txq_t txq; 4042 4043 txq = r->cookie; 4044 4045 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 4046 CALLOUT_LOCK(txq); 4047 callout_stop(&txq->ift_timer); 4048 CALLOUT_UNLOCK(txq); 4049 4050 avail = IDXDIFF(pidx, cidx, r->size); 4051 for (i = 0; i < avail; i++) { 4052 mp = _ring_peek_one(r, cidx, i, avail - i); 4053 if (__predict_false(*mp == (struct mbuf *)txq)) 4054 continue; 4055 m_freem(*mp); 4056 DBG_COUNTER_INC(tx_frees); 4057 } 4058 MPASS(ifmp_ring_is_stalled(r) == 0); 4059 return (avail); 4060 } 4061 4062 static void 4063 iflib_ifmp_purge(iflib_txq_t txq) 4064 { 4065 struct ifmp_ring *r; 4066 4067 r = txq->ift_br; 4068 r->drain = iflib_txq_drain_free; 4069 r->can_drain = iflib_txq_drain_always; 4070 4071 ifmp_ring_check_drainage(r, r->size); 4072 4073 r->drain = iflib_txq_drain; 4074 r->can_drain = iflib_txq_can_drain; 4075 } 4076 4077 static void 4078 _task_fn_tx(void *context) 4079 { 4080 iflib_txq_t txq = context; 4081 if_ctx_t ctx = txq->ift_ctx; 4082 if_t ifp = ctx->ifc_ifp; 4083 int abdicate = ctx->ifc_sysctl_tx_abdicate; 4084 4085 #ifdef IFLIB_DIAGNOSTICS 4086 txq->ift_cpu_exec_count[curcpu]++; 4087 #endif 4088 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4089 return; 4090 #ifdef DEV_NETMAP 4091 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 4092 netmap_tx_irq(ifp, txq->ift_id)) 4093 goto skip_ifmp; 4094 #endif 4095 #ifdef ALTQ 4096 if (if_altq_is_enabled(ifp)) 4097 iflib_altq_if_start(ifp); 4098 #endif 4099 if (txq->ift_db_pending) 4100 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 4101 else if (!abdicate) 4102 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4103 /* 4104 * When abdicating, we always need to check drainage, not just when we don't enqueue 4105 */ 4106 if (abdicate) 4107 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4108 #ifdef DEV_NETMAP 4109 skip_ifmp: 4110 #endif 4111 if (ctx->ifc_flags & IFC_LEGACY) 4112 IFDI_INTR_ENABLE(ctx); 4113 else 4114 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 4115 } 4116 4117 static void 4118 _task_fn_rx(void *context) 4119 { 4120 iflib_rxq_t rxq = context; 4121 if_ctx_t ctx = rxq->ifr_ctx; 4122 uint8_t more; 4123 uint16_t budget; 4124 #ifdef DEV_NETMAP 4125 u_int work = 0; 4126 int nmirq; 4127 #endif 4128 4129 #ifdef IFLIB_DIAGNOSTICS 4130 rxq->ifr_cpu_exec_count[curcpu]++; 4131 #endif 4132 DBG_COUNTER_INC(task_fn_rxs); 4133 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4134 return; 4135 #ifdef DEV_NETMAP 4136 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 4137 if (nmirq != NM_IRQ_PASS) { 4138 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 4139 goto skip_rxeof; 4140 } 4141 #endif 4142 budget = ctx->ifc_sysctl_rx_budget; 4143 if (budget == 0) 4144 budget = 16; /* XXX */ 4145 more = iflib_rxeof(rxq, budget); 4146 #ifdef DEV_NETMAP 4147 skip_rxeof: 4148 #endif 4149 if ((more & IFLIB_RXEOF_MORE) == 0) { 4150 if (ctx->ifc_flags & IFC_LEGACY) 4151 IFDI_INTR_ENABLE(ctx); 4152 else 4153 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 4154 DBG_COUNTER_INC(rx_intr_enables); 4155 } 4156 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4157 return; 4158 4159 if (more & IFLIB_RXEOF_MORE) 4160 GROUPTASK_ENQUEUE(&rxq->ifr_task); 4161 else if (more & IFLIB_RXEOF_EMPTY) 4162 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 4163 } 4164 4165 static void 4166 _task_fn_admin(void *context) 4167 { 4168 if_ctx_t ctx = context; 4169 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 4170 iflib_txq_t txq; 4171 int i; 4172 bool oactive, running, do_reset, do_watchdog, in_detach; 4173 4174 STATE_LOCK(ctx); 4175 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 4176 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 4177 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 4178 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 4179 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 4180 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 4181 STATE_UNLOCK(ctx); 4182 4183 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4184 return; 4185 if (in_detach) 4186 return; 4187 4188 CTX_LOCK(ctx); 4189 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4190 CALLOUT_LOCK(txq); 4191 callout_stop(&txq->ift_timer); 4192 CALLOUT_UNLOCK(txq); 4193 } 4194 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ) 4195 IFDI_ADMIN_COMPLETION_HANDLE(ctx); 4196 if (do_watchdog) { 4197 ctx->ifc_watchdog_events++; 4198 IFDI_WATCHDOG_RESET(ctx); 4199 } 4200 IFDI_UPDATE_ADMIN_STATUS(ctx); 4201 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4202 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 4203 txq->ift_timer.c_cpu); 4204 } 4205 IFDI_LINK_INTR_ENABLE(ctx); 4206 if (do_reset) 4207 iflib_if_init_locked(ctx); 4208 CTX_UNLOCK(ctx); 4209 4210 if (LINK_ACTIVE(ctx) == 0) 4211 return; 4212 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 4213 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4214 } 4215 4216 static void 4217 _task_fn_iov(void *context) 4218 { 4219 if_ctx_t ctx = context; 4220 4221 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 4222 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4223 return; 4224 4225 CTX_LOCK(ctx); 4226 IFDI_VFLR_HANDLE(ctx); 4227 CTX_UNLOCK(ctx); 4228 } 4229 4230 static int 4231 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4232 { 4233 int err; 4234 if_int_delay_info_t info; 4235 if_ctx_t ctx; 4236 4237 info = (if_int_delay_info_t)arg1; 4238 ctx = info->iidi_ctx; 4239 info->iidi_req = req; 4240 info->iidi_oidp = oidp; 4241 CTX_LOCK(ctx); 4242 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 4243 CTX_UNLOCK(ctx); 4244 return (err); 4245 } 4246 4247 /********************************************************************* 4248 * 4249 * IFNET FUNCTIONS 4250 * 4251 **********************************************************************/ 4252 4253 static void 4254 iflib_if_init_locked(if_ctx_t ctx) 4255 { 4256 iflib_stop(ctx); 4257 iflib_init_locked(ctx); 4258 } 4259 4260 static void 4261 iflib_if_init(void *arg) 4262 { 4263 if_ctx_t ctx = arg; 4264 4265 CTX_LOCK(ctx); 4266 iflib_if_init_locked(ctx); 4267 CTX_UNLOCK(ctx); 4268 } 4269 4270 static int 4271 iflib_if_transmit(if_t ifp, struct mbuf *m) 4272 { 4273 if_ctx_t ctx = if_getsoftc(ifp); 4274 iflib_txq_t txq; 4275 int err, qidx; 4276 int abdicate; 4277 4278 if (__predict_false((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 4279 DBG_COUNTER_INC(tx_frees); 4280 m_freem(m); 4281 return (ENETDOWN); 4282 } 4283 4284 MPASS(m->m_nextpkt == NULL); 4285 /* ALTQ-enabled interfaces always use queue 0. */ 4286 qidx = 0; 4287 /* Use driver-supplied queue selection method if it exists */ 4288 if (ctx->isc_txq_select_v2) { 4289 struct if_pkt_info pi; 4290 uint64_t early_pullups = 0; 4291 pkt_info_zero(&pi); 4292 4293 err = iflib_parse_header_partial(&pi, &m, &early_pullups); 4294 if (__predict_false(err != 0)) { 4295 /* Assign pullups for bad pkts to default queue */ 4296 ctx->ifc_txqs[0].ift_pullups += early_pullups; 4297 DBG_COUNTER_INC(encap_txd_encap_fail); 4298 return (err); 4299 } 4300 /* Let driver make queueing decision */ 4301 qidx = ctx->isc_txq_select_v2(ctx->ifc_softc, m, &pi); 4302 ctx->ifc_txqs[qidx].ift_pullups += early_pullups; 4303 } 4304 /* Backwards compatibility w/ simpler queue select */ 4305 else if (ctx->isc_txq_select) 4306 qidx = ctx->isc_txq_select(ctx->ifc_softc, m); 4307 /* If not, use iflib's standard method */ 4308 else if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !if_altq_is_enabled(ifp)) 4309 qidx = QIDX(ctx, m); 4310 4311 /* Set TX queue */ 4312 txq = &ctx->ifc_txqs[qidx]; 4313 4314 #ifdef DRIVER_BACKPRESSURE 4315 if (txq->ift_closed) { 4316 while (m != NULL) { 4317 next = m->m_nextpkt; 4318 m->m_nextpkt = NULL; 4319 m_freem(m); 4320 DBG_COUNTER_INC(tx_frees); 4321 m = next; 4322 } 4323 return (ENOBUFS); 4324 } 4325 #endif 4326 #ifdef notyet 4327 qidx = count = 0; 4328 mp = marr; 4329 next = m; 4330 do { 4331 count++; 4332 next = next->m_nextpkt; 4333 } while (next != NULL); 4334 4335 if (count > nitems(marr)) 4336 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4337 /* XXX check nextpkt */ 4338 m_freem(m); 4339 /* XXX simplify for now */ 4340 DBG_COUNTER_INC(tx_frees); 4341 return (ENOBUFS); 4342 } 4343 for (next = m, i = 0; next != NULL; i++) { 4344 mp[i] = next; 4345 next = next->m_nextpkt; 4346 mp[i]->m_nextpkt = NULL; 4347 } 4348 #endif 4349 DBG_COUNTER_INC(tx_seen); 4350 abdicate = ctx->ifc_sysctl_tx_abdicate; 4351 4352 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4353 4354 if (abdicate) 4355 GROUPTASK_ENQUEUE(&txq->ift_task); 4356 if (err) { 4357 if (!abdicate) 4358 GROUPTASK_ENQUEUE(&txq->ift_task); 4359 /* support forthcoming later */ 4360 #ifdef DRIVER_BACKPRESSURE 4361 txq->ift_closed = TRUE; 4362 #endif 4363 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4364 m_freem(m); 4365 DBG_COUNTER_INC(tx_frees); 4366 } 4367 4368 return (err); 4369 } 4370 4371 #ifdef ALTQ 4372 /* 4373 * The overall approach to integrating iflib with ALTQ is to continue to use 4374 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4375 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4376 * is redundant/unnecessary, but doing so minimizes the amount of 4377 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4378 * redundantly queueing to an intermediate mp_ring is swamped by the 4379 * performance limitations inherent in using ALTQ. 4380 * 4381 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4382 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4383 * given interface. If ALTQ is enabled for an interface, then all 4384 * transmitted packets for that interface will be submitted to the ALTQ 4385 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4386 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4387 * update stats that the iflib machinery handles, and which is sensitve to 4388 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4389 * will be installed as the start routine for use by ALTQ facilities that 4390 * need to trigger queue drains on a scheduled basis. 4391 * 4392 */ 4393 static void 4394 iflib_altq_if_start(if_t ifp) 4395 { 4396 struct ifaltq *ifq = &ifp->if_snd; /* XXX - DRVAPI */ 4397 struct mbuf *m; 4398 4399 IFQ_LOCK(ifq); 4400 IFQ_DEQUEUE_NOLOCK(ifq, m); 4401 while (m != NULL) { 4402 iflib_if_transmit(ifp, m); 4403 IFQ_DEQUEUE_NOLOCK(ifq, m); 4404 } 4405 IFQ_UNLOCK(ifq); 4406 } 4407 4408 static int 4409 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4410 { 4411 int err; 4412 4413 if (if_altq_is_enabled(ifp)) { 4414 IFQ_ENQUEUE(&ifp->if_snd, m, err); /* XXX - DRVAPI */ 4415 if (err == 0) 4416 iflib_altq_if_start(ifp); 4417 } else 4418 err = iflib_if_transmit(ifp, m); 4419 4420 return (err); 4421 } 4422 #endif /* ALTQ */ 4423 4424 static void 4425 iflib_if_qflush(if_t ifp) 4426 { 4427 if_ctx_t ctx = if_getsoftc(ifp); 4428 iflib_txq_t txq = ctx->ifc_txqs; 4429 int i; 4430 4431 STATE_LOCK(ctx); 4432 ctx->ifc_flags |= IFC_QFLUSH; 4433 STATE_UNLOCK(ctx); 4434 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4435 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4436 iflib_txq_check_drain(txq, 0); 4437 STATE_LOCK(ctx); 4438 ctx->ifc_flags &= ~IFC_QFLUSH; 4439 STATE_UNLOCK(ctx); 4440 4441 /* 4442 * When ALTQ is enabled, this will also take care of purging the 4443 * ALTQ queue(s). 4444 */ 4445 if_qflush(ifp); 4446 } 4447 4448 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4449 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4450 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4451 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG) 4452 4453 static int 4454 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4455 { 4456 if_ctx_t ctx = if_getsoftc(ifp); 4457 struct ifreq *ifr = (struct ifreq *)data; 4458 #if defined(INET) || defined(INET6) 4459 struct ifaddr *ifa = (struct ifaddr *)data; 4460 #endif 4461 bool avoid_reset = false; 4462 int err = 0, reinit = 0, bits; 4463 4464 switch (command) { 4465 case SIOCSIFADDR: 4466 #ifdef INET 4467 if (ifa->ifa_addr->sa_family == AF_INET) 4468 avoid_reset = true; 4469 #endif 4470 #ifdef INET6 4471 if (ifa->ifa_addr->sa_family == AF_INET6) 4472 avoid_reset = true; 4473 #endif 4474 /* 4475 ** Calling init results in link renegotiation, 4476 ** so we avoid doing it when possible. 4477 */ 4478 if (avoid_reset) { 4479 if_setflagbits(ifp, IFF_UP,0); 4480 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4481 reinit = 1; 4482 #ifdef INET 4483 if (!(if_getflags(ifp) & IFF_NOARP)) 4484 arp_ifinit(ifp, ifa); 4485 #endif 4486 } else 4487 err = ether_ioctl(ifp, command, data); 4488 break; 4489 case SIOCSIFMTU: 4490 CTX_LOCK(ctx); 4491 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4492 CTX_UNLOCK(ctx); 4493 break; 4494 } 4495 bits = if_getdrvflags(ifp); 4496 /* stop the driver and free any clusters before proceeding */ 4497 iflib_stop(ctx); 4498 4499 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4500 STATE_LOCK(ctx); 4501 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4502 ctx->ifc_flags |= IFC_MULTISEG; 4503 else 4504 ctx->ifc_flags &= ~IFC_MULTISEG; 4505 STATE_UNLOCK(ctx); 4506 err = if_setmtu(ifp, ifr->ifr_mtu); 4507 } 4508 iflib_init_locked(ctx); 4509 STATE_LOCK(ctx); 4510 if_setdrvflags(ifp, bits); 4511 STATE_UNLOCK(ctx); 4512 CTX_UNLOCK(ctx); 4513 break; 4514 case SIOCSIFFLAGS: 4515 CTX_LOCK(ctx); 4516 if (if_getflags(ifp) & IFF_UP) { 4517 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4518 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4519 (IFF_PROMISC | IFF_ALLMULTI)) { 4520 CTX_UNLOCK(ctx); 4521 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4522 CTX_LOCK(ctx); 4523 } 4524 } else 4525 reinit = 1; 4526 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4527 iflib_stop(ctx); 4528 } 4529 ctx->ifc_if_flags = if_getflags(ifp); 4530 CTX_UNLOCK(ctx); 4531 break; 4532 case SIOCADDMULTI: 4533 case SIOCDELMULTI: 4534 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4535 CTX_LOCK(ctx); 4536 IFDI_INTR_DISABLE(ctx); 4537 IFDI_MULTI_SET(ctx); 4538 IFDI_INTR_ENABLE(ctx); 4539 CTX_UNLOCK(ctx); 4540 } 4541 break; 4542 case SIOCSIFMEDIA: 4543 CTX_LOCK(ctx); 4544 IFDI_MEDIA_SET(ctx); 4545 CTX_UNLOCK(ctx); 4546 /* FALLTHROUGH */ 4547 case SIOCGIFMEDIA: 4548 case SIOCGIFXMEDIA: 4549 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4550 break; 4551 case SIOCGI2C: 4552 { 4553 struct ifi2creq i2c; 4554 4555 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4556 if (err != 0) 4557 break; 4558 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4559 err = EINVAL; 4560 break; 4561 } 4562 if (i2c.len > sizeof(i2c.data)) { 4563 err = EINVAL; 4564 break; 4565 } 4566 4567 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4568 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4569 sizeof(i2c)); 4570 break; 4571 } 4572 case SIOCSIFCAP: 4573 { 4574 int mask, setmask, oldmask; 4575 4576 oldmask = if_getcapenable(ifp); 4577 mask = ifr->ifr_reqcap ^ oldmask; 4578 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG; 4579 setmask = 0; 4580 #ifdef TCP_OFFLOAD 4581 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4582 #endif 4583 setmask |= (mask & IFCAP_FLAGS); 4584 setmask |= (mask & IFCAP_WOL); 4585 4586 /* 4587 * If any RX csum has changed, change all the ones that 4588 * are supported by the driver. 4589 */ 4590 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4591 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4592 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4593 } 4594 4595 /* 4596 * want to ensure that traffic has stopped before we change any of the flags 4597 */ 4598 if (setmask) { 4599 CTX_LOCK(ctx); 4600 bits = if_getdrvflags(ifp); 4601 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4602 iflib_stop(ctx); 4603 STATE_LOCK(ctx); 4604 if_togglecapenable(ifp, setmask); 4605 ctx->ifc_softc_ctx.isc_capenable ^= setmask; 4606 STATE_UNLOCK(ctx); 4607 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4608 iflib_init_locked(ctx); 4609 STATE_LOCK(ctx); 4610 if_setdrvflags(ifp, bits); 4611 STATE_UNLOCK(ctx); 4612 CTX_UNLOCK(ctx); 4613 } 4614 if_vlancap(ifp); 4615 break; 4616 } 4617 case SIOCGPRIVATE_0: 4618 case SIOCSDRVSPEC: 4619 case SIOCGDRVSPEC: 4620 CTX_LOCK(ctx); 4621 err = IFDI_PRIV_IOCTL(ctx, command, data); 4622 CTX_UNLOCK(ctx); 4623 break; 4624 default: 4625 err = ether_ioctl(ifp, command, data); 4626 break; 4627 } 4628 if (reinit) 4629 iflib_if_init(ctx); 4630 return (err); 4631 } 4632 4633 static uint64_t 4634 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4635 { 4636 if_ctx_t ctx = if_getsoftc(ifp); 4637 4638 return (IFDI_GET_COUNTER(ctx, cnt)); 4639 } 4640 4641 /********************************************************************* 4642 * 4643 * OTHER FUNCTIONS EXPORTED TO THE STACK 4644 * 4645 **********************************************************************/ 4646 4647 static void 4648 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4649 { 4650 if_ctx_t ctx = if_getsoftc(ifp); 4651 4652 if ((void *)ctx != arg) 4653 return; 4654 4655 if ((vtag == 0) || (vtag > 4095)) 4656 return; 4657 4658 if (iflib_in_detach(ctx)) 4659 return; 4660 4661 CTX_LOCK(ctx); 4662 /* Driver may need all untagged packets to be flushed */ 4663 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4664 iflib_stop(ctx); 4665 IFDI_VLAN_REGISTER(ctx, vtag); 4666 /* Re-init to load the changes, if required */ 4667 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4668 iflib_init_locked(ctx); 4669 CTX_UNLOCK(ctx); 4670 } 4671 4672 static void 4673 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4674 { 4675 if_ctx_t ctx = if_getsoftc(ifp); 4676 4677 if ((void *)ctx != arg) 4678 return; 4679 4680 if ((vtag == 0) || (vtag > 4095)) 4681 return; 4682 4683 CTX_LOCK(ctx); 4684 /* Driver may need all tagged packets to be flushed */ 4685 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4686 iflib_stop(ctx); 4687 IFDI_VLAN_UNREGISTER(ctx, vtag); 4688 /* Re-init to load the changes, if required */ 4689 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4690 iflib_init_locked(ctx); 4691 CTX_UNLOCK(ctx); 4692 } 4693 4694 static void 4695 iflib_led_func(void *arg, int onoff) 4696 { 4697 if_ctx_t ctx = arg; 4698 4699 CTX_LOCK(ctx); 4700 IFDI_LED_FUNC(ctx, onoff); 4701 CTX_UNLOCK(ctx); 4702 } 4703 4704 /********************************************************************* 4705 * 4706 * BUS FUNCTION DEFINITIONS 4707 * 4708 **********************************************************************/ 4709 4710 int 4711 iflib_device_probe(device_t dev) 4712 { 4713 const pci_vendor_info_t *ent; 4714 if_shared_ctx_t sctx; 4715 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4716 uint16_t pci_vendor_id; 4717 4718 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4719 return (ENOTSUP); 4720 4721 pci_vendor_id = pci_get_vendor(dev); 4722 pci_device_id = pci_get_device(dev); 4723 pci_subvendor_id = pci_get_subvendor(dev); 4724 pci_subdevice_id = pci_get_subdevice(dev); 4725 pci_rev_id = pci_get_revid(dev); 4726 if (sctx->isc_parse_devinfo != NULL) 4727 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4728 4729 ent = sctx->isc_vendor_info; 4730 while (ent->pvi_vendor_id != 0) { 4731 if (pci_vendor_id != ent->pvi_vendor_id) { 4732 ent++; 4733 continue; 4734 } 4735 if ((pci_device_id == ent->pvi_device_id) && 4736 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4737 (ent->pvi_subvendor_id == 0)) && 4738 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4739 (ent->pvi_subdevice_id == 0)) && 4740 ((pci_rev_id == ent->pvi_rev_id) || 4741 (ent->pvi_rev_id == 0))) { 4742 device_set_desc_copy(dev, ent->pvi_name); 4743 /* this needs to be changed to zero if the bus probing code 4744 * ever stops re-probing on best match because the sctx 4745 * may have its values over written by register calls 4746 * in subsequent probes 4747 */ 4748 return (BUS_PROBE_DEFAULT); 4749 } 4750 ent++; 4751 } 4752 return (ENXIO); 4753 } 4754 4755 int 4756 iflib_device_probe_vendor(device_t dev) 4757 { 4758 int probe; 4759 4760 probe = iflib_device_probe(dev); 4761 if (probe == BUS_PROBE_DEFAULT) 4762 return (BUS_PROBE_VENDOR); 4763 else 4764 return (probe); 4765 } 4766 4767 static void 4768 iflib_reset_qvalues(if_ctx_t ctx) 4769 { 4770 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4771 if_shared_ctx_t sctx = ctx->ifc_sctx; 4772 device_t dev = ctx->ifc_dev; 4773 int i; 4774 4775 if (ctx->ifc_sysctl_ntxqs != 0) 4776 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4777 if (ctx->ifc_sysctl_nrxqs != 0) 4778 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4779 4780 for (i = 0; i < sctx->isc_ntxqs; i++) { 4781 if (ctx->ifc_sysctl_ntxds[i] != 0) 4782 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4783 else 4784 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4785 } 4786 4787 for (i = 0; i < sctx->isc_nrxqs; i++) { 4788 if (ctx->ifc_sysctl_nrxds[i] != 0) 4789 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4790 else 4791 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4792 } 4793 4794 for (i = 0; i < sctx->isc_nrxqs; i++) { 4795 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4796 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4797 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4798 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4799 } 4800 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4801 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4802 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4803 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4804 } 4805 if (!powerof2(scctx->isc_nrxd[i])) { 4806 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4807 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4808 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4809 } 4810 } 4811 4812 for (i = 0; i < sctx->isc_ntxqs; i++) { 4813 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4814 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4815 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4816 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4817 } 4818 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4819 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4820 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4821 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4822 } 4823 if (!powerof2(scctx->isc_ntxd[i])) { 4824 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4825 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4826 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4827 } 4828 } 4829 } 4830 4831 static void 4832 iflib_add_pfil(if_ctx_t ctx) 4833 { 4834 struct pfil_head *pfil; 4835 struct pfil_head_args pa; 4836 iflib_rxq_t rxq; 4837 int i; 4838 4839 pa.pa_version = PFIL_VERSION; 4840 pa.pa_flags = PFIL_IN; 4841 pa.pa_type = PFIL_TYPE_ETHERNET; 4842 pa.pa_headname = if_name(ctx->ifc_ifp); 4843 pfil = pfil_head_register(&pa); 4844 4845 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4846 rxq->pfil = pfil; 4847 } 4848 } 4849 4850 static void 4851 iflib_rem_pfil(if_ctx_t ctx) 4852 { 4853 struct pfil_head *pfil; 4854 iflib_rxq_t rxq; 4855 int i; 4856 4857 rxq = ctx->ifc_rxqs; 4858 pfil = rxq->pfil; 4859 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4860 rxq->pfil = NULL; 4861 } 4862 pfil_head_unregister(pfil); 4863 } 4864 4865 4866 /* 4867 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from 4868 * cpuid and wrapping as necessary. 4869 */ 4870 static unsigned int 4871 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n) 4872 { 4873 unsigned int first_valid; 4874 unsigned int last_valid; 4875 4876 /* cpuid should always be in the valid set */ 4877 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4878 4879 /* valid set should never be empty */ 4880 MPASS(!CPU_EMPTY(&ctx->ifc_cpus)); 4881 4882 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4883 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4884 n = n % CPU_COUNT(&ctx->ifc_cpus); 4885 while (n > 0) { 4886 do { 4887 cpuid++; 4888 if (cpuid > last_valid) 4889 cpuid = first_valid; 4890 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4891 n--; 4892 } 4893 4894 return (cpuid); 4895 } 4896 4897 #if defined(SMP) && defined(SCHED_ULE) 4898 extern struct cpu_group *cpu_top; /* CPU topology */ 4899 4900 static int 4901 find_child_with_core(int cpu, struct cpu_group *grp) 4902 { 4903 int i; 4904 4905 if (grp->cg_children == 0) 4906 return -1; 4907 4908 MPASS(grp->cg_child); 4909 for (i = 0; i < grp->cg_children; i++) { 4910 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 4911 return i; 4912 } 4913 4914 return -1; 4915 } 4916 4917 4918 /* 4919 * Find an L2 neighbor of the given CPU or return -1 if none found. This 4920 * does not distinguish among multiple L2 neighbors if the given CPU has 4921 * more than one (it will always return the same result in that case). 4922 */ 4923 static int 4924 find_l2_neighbor(int cpu) 4925 { 4926 struct cpu_group *grp; 4927 int i; 4928 4929 grp = cpu_top; 4930 if (grp == NULL) 4931 return -1; 4932 4933 /* 4934 * Find the smallest CPU group that contains the given core. 4935 */ 4936 i = 0; 4937 while ((i = find_child_with_core(cpu, grp)) != -1) { 4938 /* 4939 * If the smallest group containing the given CPU has less 4940 * than two members, we conclude the given CPU has no 4941 * L2 neighbor. 4942 */ 4943 if (grp->cg_child[i].cg_count <= 1) 4944 return (-1); 4945 grp = &grp->cg_child[i]; 4946 } 4947 4948 /* Must share L2. */ 4949 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 4950 return -1; 4951 4952 /* 4953 * Select the first member of the set that isn't the reference 4954 * CPU, which at this point is guaranteed to exist. 4955 */ 4956 for (i = 0; i < CPU_SETSIZE; i++) { 4957 if (CPU_ISSET(i, &grp->cg_mask) && i != cpu) 4958 return (i); 4959 } 4960 4961 /* Should never be reached */ 4962 return (-1); 4963 } 4964 4965 #else 4966 static int 4967 find_l2_neighbor(int cpu) 4968 { 4969 4970 return (-1); 4971 } 4972 #endif 4973 4974 /* 4975 * CPU mapping behaviors 4976 * --------------------- 4977 * 'separate txrx' refers to the separate_txrx sysctl 4978 * 'use logical' refers to the use_logical_cores sysctl 4979 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded 4980 * 4981 * separate use INTR 4982 * txrx logical CPUS result 4983 * ---------- --------- ------ ------------------------------------------------ 4984 * - - X RX and TX queues mapped to consecutive physical 4985 * cores with RX/TX pairs on same core and excess 4986 * of either following 4987 * - X X RX and TX queues mapped to consecutive cores 4988 * of any type with RX/TX pairs on same core and 4989 * excess of either following 4990 * X - X RX and TX queues mapped to consecutive physical 4991 * cores; all RX then all TX 4992 * X X X RX queues mapped to consecutive physical cores 4993 * first, then TX queues mapped to L2 neighbor of 4994 * the corresponding RX queue if one exists, 4995 * otherwise to consecutive physical cores 4996 * - n/a - RX and TX queues mapped to consecutive cores of 4997 * any type with RX/TX pairs on same core and excess 4998 * of either following 4999 * X n/a - RX and TX queues mapped to consecutive cores of 5000 * any type; all RX then all TX 5001 */ 5002 static unsigned int 5003 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid, 5004 bool is_tx) 5005 { 5006 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5007 unsigned int core_index; 5008 5009 if (ctx->ifc_sysctl_separate_txrx) { 5010 /* 5011 * When using separate CPUs for TX and RX, the assignment 5012 * will always be of a consecutive CPU out of the set of 5013 * context CPUs, except for the specific case where the 5014 * context CPUs are phsyical cores, the use of logical cores 5015 * has been enabled, the assignment is for TX, the TX qid 5016 * corresponds to an RX qid, and the CPU assigned to the 5017 * corresponding RX queue has an L2 neighbor. 5018 */ 5019 if (ctx->ifc_sysctl_use_logical_cores && 5020 ctx->ifc_cpus_are_physical_cores && 5021 is_tx && qid < scctx->isc_nrxqsets) { 5022 int l2_neighbor; 5023 unsigned int rx_cpuid; 5024 5025 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid); 5026 l2_neighbor = find_l2_neighbor(rx_cpuid); 5027 if (l2_neighbor != -1) { 5028 return (l2_neighbor); 5029 } 5030 /* 5031 * ... else fall through to the normal 5032 * consecutive-after-RX assignment scheme. 5033 * 5034 * Note that we are assuming that all RX queue CPUs 5035 * have an L2 neighbor, or all do not. If a mixed 5036 * scenario is possible, we will have to keep track 5037 * separately of how many queues prior to this one 5038 * were not able to be assigned to an L2 neighbor. 5039 */ 5040 } 5041 if (is_tx) 5042 core_index = scctx->isc_nrxqsets + qid; 5043 else 5044 core_index = qid; 5045 } else { 5046 core_index = qid; 5047 } 5048 5049 return (cpuid_advance(ctx, base_cpuid, core_index)); 5050 } 5051 5052 static uint16_t 5053 get_ctx_core_offset(if_ctx_t ctx) 5054 { 5055 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5056 struct cpu_offset *op; 5057 cpuset_t assigned_cpus; 5058 unsigned int cores_consumed; 5059 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset; 5060 unsigned int first_valid; 5061 unsigned int last_valid; 5062 unsigned int i; 5063 5064 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 5065 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 5066 5067 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) { 5068 /* 5069 * Align the user-chosen base CPU ID to the next valid CPU 5070 * for this device. If the chosen base CPU ID is smaller 5071 * than the first valid CPU or larger than the last valid 5072 * CPU, we assume the user does not know what the valid 5073 * range is for this device and is thinking in terms of a 5074 * zero-based reference frame, and so we shift the given 5075 * value into the valid range (and wrap accordingly) so the 5076 * intent is translated to the proper frame of reference. 5077 * If the base CPU ID is within the valid first/last, but 5078 * does not correspond to a valid CPU, it is advanced to the 5079 * next valid CPU (wrapping if necessary). 5080 */ 5081 if (base_cpuid < first_valid || base_cpuid > last_valid) { 5082 /* shift from zero-based to first_valid-based */ 5083 base_cpuid += first_valid; 5084 /* wrap to range [first_valid, last_valid] */ 5085 base_cpuid = (base_cpuid - first_valid) % 5086 (last_valid - first_valid + 1); 5087 } 5088 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) { 5089 /* 5090 * base_cpuid is in [first_valid, last_valid], but 5091 * not a member of the valid set. In this case, 5092 * there will always be a member of the valid set 5093 * with a CPU ID that is greater than base_cpuid, 5094 * and we simply advance to it. 5095 */ 5096 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) 5097 base_cpuid++; 5098 } 5099 return (base_cpuid); 5100 } 5101 5102 /* 5103 * Determine how many cores will be consumed by performing the CPU 5104 * assignments and counting how many of the assigned CPUs correspond 5105 * to CPUs in the set of context CPUs. This is done using the CPU 5106 * ID first_valid as the base CPU ID, as the base CPU must be within 5107 * the set of context CPUs. 5108 * 5109 * Note not all assigned CPUs will be in the set of context CPUs 5110 * when separate CPUs are being allocated to TX and RX queues, 5111 * assignment to logical cores has been enabled, the set of context 5112 * CPUs contains only physical CPUs, and TX queues are mapped to L2 5113 * neighbors of CPUs that RX queues have been mapped to - in this 5114 * case we do only want to count how many CPUs in the set of context 5115 * CPUs have been consumed, as that determines the next CPU in that 5116 * set to start allocating at for the next device for which 5117 * core_offset is not set. 5118 */ 5119 CPU_ZERO(&assigned_cpus); 5120 for (i = 0; i < scctx->isc_ntxqsets; i++) 5121 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true), 5122 &assigned_cpus); 5123 for (i = 0; i < scctx->isc_nrxqsets; i++) 5124 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false), 5125 &assigned_cpus); 5126 CPU_AND(&assigned_cpus, &assigned_cpus, &ctx->ifc_cpus); 5127 cores_consumed = CPU_COUNT(&assigned_cpus); 5128 5129 mtx_lock(&cpu_offset_mtx); 5130 SLIST_FOREACH(op, &cpu_offsets, entries) { 5131 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5132 base_cpuid = op->next_cpuid; 5133 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid, 5134 cores_consumed); 5135 MPASS(op->refcount < UINT_MAX); 5136 op->refcount++; 5137 break; 5138 } 5139 } 5140 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) { 5141 base_cpuid = first_valid; 5142 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 5143 M_NOWAIT | M_ZERO); 5144 if (op == NULL) { 5145 device_printf(ctx->ifc_dev, 5146 "allocation for cpu offset failed.\n"); 5147 } else { 5148 op->next_cpuid = cpuid_advance(ctx, base_cpuid, 5149 cores_consumed); 5150 op->refcount = 1; 5151 CPU_COPY(&ctx->ifc_cpus, &op->set); 5152 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 5153 } 5154 } 5155 mtx_unlock(&cpu_offset_mtx); 5156 5157 return (base_cpuid); 5158 } 5159 5160 static void 5161 unref_ctx_core_offset(if_ctx_t ctx) 5162 { 5163 struct cpu_offset *op, *top; 5164 5165 mtx_lock(&cpu_offset_mtx); 5166 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 5167 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5168 MPASS(op->refcount > 0); 5169 op->refcount--; 5170 if (op->refcount == 0) { 5171 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 5172 free(op, M_IFLIB); 5173 } 5174 break; 5175 } 5176 } 5177 mtx_unlock(&cpu_offset_mtx); 5178 } 5179 5180 int 5181 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 5182 { 5183 if_ctx_t ctx; 5184 if_t ifp; 5185 if_softc_ctx_t scctx; 5186 kobjop_desc_t kobj_desc; 5187 kobj_method_t *kobj_method; 5188 int err, msix, rid; 5189 int num_txd, num_rxd; 5190 5191 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 5192 5193 if (sc == NULL) { 5194 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 5195 device_set_softc(dev, ctx); 5196 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5197 } 5198 5199 ctx->ifc_sctx = sctx; 5200 ctx->ifc_dev = dev; 5201 ctx->ifc_softc = sc; 5202 5203 if ((err = iflib_register(ctx)) != 0) { 5204 device_printf(dev, "iflib_register failed %d\n", err); 5205 goto fail_ctx_free; 5206 } 5207 iflib_add_device_sysctl_pre(ctx); 5208 5209 scctx = &ctx->ifc_softc_ctx; 5210 ifp = ctx->ifc_ifp; 5211 5212 iflib_reset_qvalues(ctx); 5213 IFNET_WLOCK(); 5214 CTX_LOCK(ctx); 5215 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5216 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5217 goto fail_unlock; 5218 } 5219 _iflib_pre_assert(scctx); 5220 ctx->ifc_txrx = *scctx->isc_txrx; 5221 5222 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR)); 5223 5224 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 5225 ctx->ifc_mediap = scctx->isc_media; 5226 5227 #ifdef INVARIANTS 5228 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5229 MPASS(scctx->isc_tx_csum_flags); 5230 #endif 5231 5232 if_setcapabilities(ifp, 5233 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG); 5234 if_setcapenable(ifp, 5235 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG); 5236 5237 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5238 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5239 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5240 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5241 5242 num_txd = iflib_num_tx_descs(ctx); 5243 num_rxd = iflib_num_rx_descs(ctx); 5244 5245 /* XXX change for per-queue sizes */ 5246 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5247 num_txd, num_rxd); 5248 5249 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5250 scctx->isc_tx_nsegments = max(1, num_txd / 5251 MAX_SINGLE_PACKET_FRACTION); 5252 if (scctx->isc_tx_tso_segments_max > num_txd / 5253 MAX_SINGLE_PACKET_FRACTION) 5254 scctx->isc_tx_tso_segments_max = max(1, 5255 num_txd / MAX_SINGLE_PACKET_FRACTION); 5256 5257 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5258 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5259 /* 5260 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5261 * but some MACs do. 5262 */ 5263 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5264 IP_MAXPACKET)); 5265 /* 5266 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5267 * into account. In the worst case, each of these calls will 5268 * add another mbuf and, thus, the requirement for another DMA 5269 * segment. So for best performance, it doesn't make sense to 5270 * advertize a maximum of TSO segments that typically will 5271 * require defragmentation in iflib_encap(). 5272 */ 5273 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5274 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5275 } 5276 if (scctx->isc_rss_table_size == 0) 5277 scctx->isc_rss_table_size = 64; 5278 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5279 5280 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5281 /* XXX format name */ 5282 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5283 NULL, NULL, "admin"); 5284 5285 /* Set up cpu set. If it fails, use the set of all CPUs. */ 5286 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 5287 device_printf(dev, "Unable to fetch CPU list\n"); 5288 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 5289 ctx->ifc_cpus_are_physical_cores = false; 5290 } else 5291 ctx->ifc_cpus_are_physical_cores = true; 5292 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 5293 5294 /* 5295 ** Now set up MSI or MSI-X, should return us the number of supported 5296 ** vectors (will be 1 for a legacy interrupt and MSI). 5297 */ 5298 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 5299 msix = scctx->isc_vectors; 5300 } else if (scctx->isc_msix_bar != 0) 5301 /* 5302 * The simple fact that isc_msix_bar is not 0 does not mean we 5303 * we have a good value there that is known to work. 5304 */ 5305 msix = iflib_msix_init(ctx); 5306 else { 5307 scctx->isc_vectors = 1; 5308 scctx->isc_ntxqsets = 1; 5309 scctx->isc_nrxqsets = 1; 5310 scctx->isc_intr = IFLIB_INTR_LEGACY; 5311 msix = 0; 5312 } 5313 /* Get memory for the station queues */ 5314 if ((err = iflib_queues_alloc(ctx))) { 5315 device_printf(dev, "Unable to allocate queue memory\n"); 5316 goto fail_intr_free; 5317 } 5318 5319 if ((err = iflib_qset_structures_setup(ctx))) 5320 goto fail_queues; 5321 5322 /* 5323 * Now that we know how many queues there are, get the core offset. 5324 */ 5325 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 5326 5327 if (msix > 1) { 5328 /* 5329 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 5330 * aren't the default NULL implementation. 5331 */ 5332 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 5333 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5334 kobj_desc); 5335 if (kobj_method == &kobj_desc->deflt) { 5336 device_printf(dev, 5337 "MSI-X requires ifdi_rx_queue_intr_enable method"); 5338 err = EOPNOTSUPP; 5339 goto fail_queues; 5340 } 5341 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 5342 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5343 kobj_desc); 5344 if (kobj_method == &kobj_desc->deflt) { 5345 device_printf(dev, 5346 "MSI-X requires ifdi_tx_queue_intr_enable method"); 5347 err = EOPNOTSUPP; 5348 goto fail_queues; 5349 } 5350 5351 /* 5352 * Assign the MSI-X vectors. 5353 * Note that the default NULL ifdi_msix_intr_assign method will 5354 * fail here, too. 5355 */ 5356 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 5357 if (err != 0) { 5358 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 5359 err); 5360 goto fail_queues; 5361 } 5362 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 5363 rid = 0; 5364 if (scctx->isc_intr == IFLIB_INTR_MSI) { 5365 MPASS(msix == 1); 5366 rid = 1; 5367 } 5368 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 5369 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 5370 goto fail_queues; 5371 } 5372 } else { 5373 device_printf(dev, 5374 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 5375 err = ENODEV; 5376 goto fail_queues; 5377 } 5378 5379 /* 5380 * It prevents a double-locking panic with iflib_media_status when 5381 * the driver loads. 5382 */ 5383 CTX_UNLOCK(ctx); 5384 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5385 CTX_LOCK(ctx); 5386 5387 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5388 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5389 goto fail_detach; 5390 } 5391 5392 /* 5393 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5394 * This must appear after the call to ether_ifattach() because 5395 * ether_ifattach() sets if_hdrlen to the default value. 5396 */ 5397 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5398 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5399 5400 if ((err = iflib_netmap_attach(ctx))) { 5401 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 5402 goto fail_detach; 5403 } 5404 *ctxp = ctx; 5405 5406 DEBUGNET_SET(ctx->ifc_ifp, iflib); 5407 5408 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5409 iflib_add_device_sysctl_post(ctx); 5410 iflib_add_pfil(ctx); 5411 ctx->ifc_flags |= IFC_INIT_DONE; 5412 CTX_UNLOCK(ctx); 5413 IFNET_WUNLOCK(); 5414 5415 return (0); 5416 5417 fail_detach: 5418 ether_ifdetach(ctx->ifc_ifp); 5419 fail_queues: 5420 iflib_tqg_detach(ctx); 5421 iflib_tx_structures_free(ctx); 5422 iflib_rx_structures_free(ctx); 5423 IFDI_DETACH(ctx); 5424 IFDI_QUEUES_FREE(ctx); 5425 fail_intr_free: 5426 iflib_free_intr_mem(ctx); 5427 fail_unlock: 5428 CTX_UNLOCK(ctx); 5429 IFNET_WUNLOCK(); 5430 iflib_deregister(ctx); 5431 fail_ctx_free: 5432 device_set_softc(ctx->ifc_dev, NULL); 5433 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5434 free(ctx->ifc_softc, M_IFLIB); 5435 free(ctx, M_IFLIB); 5436 return (err); 5437 } 5438 5439 int 5440 iflib_device_attach(device_t dev) 5441 { 5442 if_ctx_t ctx; 5443 if_shared_ctx_t sctx; 5444 5445 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5446 return (ENOTSUP); 5447 5448 pci_enable_busmaster(dev); 5449 5450 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5451 } 5452 5453 int 5454 iflib_device_deregister(if_ctx_t ctx) 5455 { 5456 if_t ifp = ctx->ifc_ifp; 5457 device_t dev = ctx->ifc_dev; 5458 5459 /* Make sure VLANS are not using driver */ 5460 if (if_vlantrunkinuse(ifp)) { 5461 device_printf(dev, "Vlan in use, detach first\n"); 5462 return (EBUSY); 5463 } 5464 #ifdef PCI_IOV 5465 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5466 device_printf(dev, "SR-IOV in use; detach first.\n"); 5467 return (EBUSY); 5468 } 5469 #endif 5470 5471 STATE_LOCK(ctx); 5472 ctx->ifc_flags |= IFC_IN_DETACH; 5473 STATE_UNLOCK(ctx); 5474 5475 /* Unregister VLAN handlers before calling iflib_stop() */ 5476 iflib_unregister_vlan_handlers(ctx); 5477 5478 iflib_netmap_detach(ifp); 5479 ether_ifdetach(ifp); 5480 5481 CTX_LOCK(ctx); 5482 iflib_stop(ctx); 5483 CTX_UNLOCK(ctx); 5484 5485 iflib_rem_pfil(ctx); 5486 if (ctx->ifc_led_dev != NULL) 5487 led_destroy(ctx->ifc_led_dev); 5488 5489 iflib_tqg_detach(ctx); 5490 iflib_tx_structures_free(ctx); 5491 iflib_rx_structures_free(ctx); 5492 5493 CTX_LOCK(ctx); 5494 IFDI_DETACH(ctx); 5495 IFDI_QUEUES_FREE(ctx); 5496 CTX_UNLOCK(ctx); 5497 5498 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5499 iflib_free_intr_mem(ctx); 5500 5501 bus_generic_detach(dev); 5502 5503 iflib_deregister(ctx); 5504 5505 device_set_softc(ctx->ifc_dev, NULL); 5506 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5507 free(ctx->ifc_softc, M_IFLIB); 5508 unref_ctx_core_offset(ctx); 5509 free(ctx, M_IFLIB); 5510 return (0); 5511 } 5512 5513 static void 5514 iflib_tqg_detach(if_ctx_t ctx) 5515 { 5516 iflib_txq_t txq; 5517 iflib_rxq_t rxq; 5518 int i; 5519 struct taskqgroup *tqg; 5520 5521 /* XXX drain any dependent tasks */ 5522 tqg = qgroup_if_io_tqg; 5523 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5524 callout_drain(&txq->ift_timer); 5525 #ifdef DEV_NETMAP 5526 callout_drain(&txq->ift_netmap_timer); 5527 #endif /* DEV_NETMAP */ 5528 if (txq->ift_task.gt_uniq != NULL) 5529 taskqgroup_detach(tqg, &txq->ift_task); 5530 } 5531 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5532 if (rxq->ifr_task.gt_uniq != NULL) 5533 taskqgroup_detach(tqg, &rxq->ifr_task); 5534 } 5535 tqg = qgroup_if_config_tqg; 5536 if (ctx->ifc_admin_task.gt_uniq != NULL) 5537 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5538 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5539 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5540 } 5541 5542 static void 5543 iflib_free_intr_mem(if_ctx_t ctx) 5544 { 5545 5546 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5547 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5548 } 5549 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5550 pci_release_msi(ctx->ifc_dev); 5551 } 5552 if (ctx->ifc_msix_mem != NULL) { 5553 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5554 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5555 ctx->ifc_msix_mem = NULL; 5556 } 5557 } 5558 5559 int 5560 iflib_device_detach(device_t dev) 5561 { 5562 if_ctx_t ctx = device_get_softc(dev); 5563 5564 return (iflib_device_deregister(ctx)); 5565 } 5566 5567 int 5568 iflib_device_suspend(device_t dev) 5569 { 5570 if_ctx_t ctx = device_get_softc(dev); 5571 5572 CTX_LOCK(ctx); 5573 IFDI_SUSPEND(ctx); 5574 CTX_UNLOCK(ctx); 5575 5576 return bus_generic_suspend(dev); 5577 } 5578 int 5579 iflib_device_shutdown(device_t dev) 5580 { 5581 if_ctx_t ctx = device_get_softc(dev); 5582 5583 CTX_LOCK(ctx); 5584 IFDI_SHUTDOWN(ctx); 5585 CTX_UNLOCK(ctx); 5586 5587 return bus_generic_suspend(dev); 5588 } 5589 5590 int 5591 iflib_device_resume(device_t dev) 5592 { 5593 if_ctx_t ctx = device_get_softc(dev); 5594 iflib_txq_t txq = ctx->ifc_txqs; 5595 5596 CTX_LOCK(ctx); 5597 IFDI_RESUME(ctx); 5598 iflib_if_init_locked(ctx); 5599 CTX_UNLOCK(ctx); 5600 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5601 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5602 5603 return (bus_generic_resume(dev)); 5604 } 5605 5606 int 5607 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5608 { 5609 int error; 5610 if_ctx_t ctx = device_get_softc(dev); 5611 5612 CTX_LOCK(ctx); 5613 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5614 CTX_UNLOCK(ctx); 5615 5616 return (error); 5617 } 5618 5619 void 5620 iflib_device_iov_uninit(device_t dev) 5621 { 5622 if_ctx_t ctx = device_get_softc(dev); 5623 5624 CTX_LOCK(ctx); 5625 IFDI_IOV_UNINIT(ctx); 5626 CTX_UNLOCK(ctx); 5627 } 5628 5629 int 5630 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5631 { 5632 int error; 5633 if_ctx_t ctx = device_get_softc(dev); 5634 5635 CTX_LOCK(ctx); 5636 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5637 CTX_UNLOCK(ctx); 5638 5639 return (error); 5640 } 5641 5642 /********************************************************************* 5643 * 5644 * MODULE FUNCTION DEFINITIONS 5645 * 5646 **********************************************************************/ 5647 5648 /* 5649 * - Start a fast taskqueue thread for each core 5650 * - Start a taskqueue for control operations 5651 */ 5652 static int 5653 iflib_module_init(void) 5654 { 5655 iflib_timer_default = hz / 2; 5656 return (0); 5657 } 5658 5659 static int 5660 iflib_module_event_handler(module_t mod, int what, void *arg) 5661 { 5662 int err; 5663 5664 switch (what) { 5665 case MOD_LOAD: 5666 if ((err = iflib_module_init()) != 0) 5667 return (err); 5668 break; 5669 case MOD_UNLOAD: 5670 return (EBUSY); 5671 default: 5672 return (EOPNOTSUPP); 5673 } 5674 5675 return (0); 5676 } 5677 5678 /********************************************************************* 5679 * 5680 * PUBLIC FUNCTION DEFINITIONS 5681 * ordered as in iflib.h 5682 * 5683 **********************************************************************/ 5684 5685 static void 5686 _iflib_assert(if_shared_ctx_t sctx) 5687 { 5688 int i; 5689 5690 MPASS(sctx->isc_tx_maxsize); 5691 MPASS(sctx->isc_tx_maxsegsize); 5692 5693 MPASS(sctx->isc_rx_maxsize); 5694 MPASS(sctx->isc_rx_nsegments); 5695 MPASS(sctx->isc_rx_maxsegsize); 5696 5697 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5698 for (i = 0; i < sctx->isc_nrxqs; i++) { 5699 MPASS(sctx->isc_nrxd_min[i]); 5700 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5701 MPASS(sctx->isc_nrxd_max[i]); 5702 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5703 MPASS(sctx->isc_nrxd_default[i]); 5704 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5705 } 5706 5707 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5708 for (i = 0; i < sctx->isc_ntxqs; i++) { 5709 MPASS(sctx->isc_ntxd_min[i]); 5710 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5711 MPASS(sctx->isc_ntxd_max[i]); 5712 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5713 MPASS(sctx->isc_ntxd_default[i]); 5714 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5715 } 5716 } 5717 5718 static void 5719 _iflib_pre_assert(if_softc_ctx_t scctx) 5720 { 5721 5722 MPASS(scctx->isc_txrx->ift_txd_encap); 5723 MPASS(scctx->isc_txrx->ift_txd_flush); 5724 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5725 MPASS(scctx->isc_txrx->ift_rxd_available); 5726 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5727 MPASS(scctx->isc_txrx->ift_rxd_refill); 5728 MPASS(scctx->isc_txrx->ift_rxd_flush); 5729 } 5730 5731 static int 5732 iflib_register(if_ctx_t ctx) 5733 { 5734 if_shared_ctx_t sctx = ctx->ifc_sctx; 5735 driver_t *driver = sctx->isc_driver; 5736 device_t dev = ctx->ifc_dev; 5737 if_t ifp; 5738 5739 _iflib_assert(sctx); 5740 5741 CTX_LOCK_INIT(ctx); 5742 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5743 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5744 if (ifp == NULL) { 5745 device_printf(dev, "can not allocate ifnet structure\n"); 5746 return (ENOMEM); 5747 } 5748 5749 /* 5750 * Initialize our context's device specific methods 5751 */ 5752 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5753 kobj_class_compile((kobj_class_t) driver); 5754 5755 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5756 if_setsoftc(ifp, ctx); 5757 if_setdev(ifp, dev); 5758 if_setinitfn(ifp, iflib_if_init); 5759 if_setioctlfn(ifp, iflib_if_ioctl); 5760 #ifdef ALTQ 5761 if_setstartfn(ifp, iflib_altq_if_start); 5762 if_settransmitfn(ifp, iflib_altq_if_transmit); 5763 if_setsendqready(ifp); 5764 #else 5765 if_settransmitfn(ifp, iflib_if_transmit); 5766 #endif 5767 if_setqflushfn(ifp, iflib_if_qflush); 5768 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5769 ctx->ifc_vlan_attach_event = 5770 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5771 EVENTHANDLER_PRI_FIRST); 5772 ctx->ifc_vlan_detach_event = 5773 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5774 EVENTHANDLER_PRI_FIRST); 5775 5776 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5777 ctx->ifc_mediap = &ctx->ifc_media; 5778 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5779 iflib_media_change, iflib_media_status); 5780 } 5781 return (0); 5782 } 5783 5784 static void 5785 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5786 { 5787 /* Unregister VLAN events */ 5788 if (ctx->ifc_vlan_attach_event != NULL) { 5789 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5790 ctx->ifc_vlan_attach_event = NULL; 5791 } 5792 if (ctx->ifc_vlan_detach_event != NULL) { 5793 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5794 ctx->ifc_vlan_detach_event = NULL; 5795 } 5796 5797 } 5798 5799 static void 5800 iflib_deregister(if_ctx_t ctx) 5801 { 5802 if_t ifp = ctx->ifc_ifp; 5803 5804 /* Remove all media */ 5805 ifmedia_removeall(&ctx->ifc_media); 5806 5807 /* Ensure that VLAN event handlers are unregistered */ 5808 iflib_unregister_vlan_handlers(ctx); 5809 5810 /* Release kobject reference */ 5811 kobj_delete((kobj_t) ctx, NULL); 5812 5813 /* Free the ifnet structure */ 5814 if_free(ifp); 5815 5816 STATE_LOCK_DESTROY(ctx); 5817 5818 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5819 CTX_LOCK_DESTROY(ctx); 5820 } 5821 5822 static int 5823 iflib_queues_alloc(if_ctx_t ctx) 5824 { 5825 if_shared_ctx_t sctx = ctx->ifc_sctx; 5826 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5827 device_t dev = ctx->ifc_dev; 5828 int nrxqsets = scctx->isc_nrxqsets; 5829 int ntxqsets = scctx->isc_ntxqsets; 5830 iflib_txq_t txq; 5831 iflib_rxq_t rxq; 5832 iflib_fl_t fl = NULL; 5833 int i, j, cpu, err, txconf, rxconf; 5834 iflib_dma_info_t ifdip; 5835 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5836 uint32_t *txqsizes = scctx->isc_txqsizes; 5837 uint8_t nrxqs = sctx->isc_nrxqs; 5838 uint8_t ntxqs = sctx->isc_ntxqs; 5839 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5840 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0); 5841 caddr_t *vaddrs; 5842 uint64_t *paddrs; 5843 5844 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5845 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5846 KASSERT(nrxqs >= fl_offset + nfree_lists, 5847 ("there must be at least a rxq for each free list")); 5848 5849 /* Allocate the TX ring struct memory */ 5850 if (!(ctx->ifc_txqs = 5851 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5852 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5853 device_printf(dev, "Unable to allocate TX ring memory\n"); 5854 err = ENOMEM; 5855 goto fail; 5856 } 5857 5858 /* Now allocate the RX */ 5859 if (!(ctx->ifc_rxqs = 5860 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5861 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5862 device_printf(dev, "Unable to allocate RX ring memory\n"); 5863 err = ENOMEM; 5864 goto rx_fail; 5865 } 5866 5867 txq = ctx->ifc_txqs; 5868 rxq = ctx->ifc_rxqs; 5869 5870 /* 5871 * XXX handle allocation failure 5872 */ 5873 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5874 /* Set up some basics */ 5875 5876 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5877 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5878 device_printf(dev, 5879 "Unable to allocate TX DMA info memory\n"); 5880 err = ENOMEM; 5881 goto err_tx_desc; 5882 } 5883 txq->ift_ifdi = ifdip; 5884 for (j = 0; j < ntxqs; j++, ifdip++) { 5885 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5886 device_printf(dev, 5887 "Unable to allocate TX descriptors\n"); 5888 err = ENOMEM; 5889 goto err_tx_desc; 5890 } 5891 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5892 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5893 } 5894 txq->ift_ctx = ctx; 5895 txq->ift_id = i; 5896 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5897 txq->ift_br_offset = 1; 5898 } else { 5899 txq->ift_br_offset = 0; 5900 } 5901 5902 if (iflib_txsd_alloc(txq)) { 5903 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5904 err = ENOMEM; 5905 goto err_tx_desc; 5906 } 5907 5908 /* Initialize the TX lock */ 5909 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5910 device_get_nameunit(dev), txq->ift_id); 5911 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5912 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5913 txq->ift_timer.c_cpu = cpu; 5914 #ifdef DEV_NETMAP 5915 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 5916 txq->ift_netmap_timer.c_cpu = cpu; 5917 #endif /* DEV_NETMAP */ 5918 5919 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5920 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5921 if (err) { 5922 /* XXX free any allocated rings */ 5923 device_printf(dev, "Unable to allocate buf_ring\n"); 5924 goto err_tx_desc; 5925 } 5926 } 5927 5928 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5929 /* Set up some basics */ 5930 callout_init(&rxq->ifr_watchdog, 1); 5931 5932 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5933 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5934 device_printf(dev, 5935 "Unable to allocate RX DMA info memory\n"); 5936 err = ENOMEM; 5937 goto err_tx_desc; 5938 } 5939 5940 rxq->ifr_ifdi = ifdip; 5941 /* XXX this needs to be changed if #rx queues != #tx queues */ 5942 rxq->ifr_ntxqirq = 1; 5943 rxq->ifr_txqid[0] = i; 5944 for (j = 0; j < nrxqs; j++, ifdip++) { 5945 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5946 device_printf(dev, 5947 "Unable to allocate RX descriptors\n"); 5948 err = ENOMEM; 5949 goto err_tx_desc; 5950 } 5951 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5952 } 5953 rxq->ifr_ctx = ctx; 5954 rxq->ifr_id = i; 5955 rxq->ifr_fl_offset = fl_offset; 5956 rxq->ifr_nfl = nfree_lists; 5957 if (!(fl = 5958 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5959 device_printf(dev, "Unable to allocate free list memory\n"); 5960 err = ENOMEM; 5961 goto err_tx_desc; 5962 } 5963 rxq->ifr_fl = fl; 5964 for (j = 0; j < nfree_lists; j++) { 5965 fl[j].ifl_rxq = rxq; 5966 fl[j].ifl_id = j; 5967 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5968 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5969 } 5970 /* Allocate receive buffers for the ring */ 5971 if (iflib_rxsd_alloc(rxq)) { 5972 device_printf(dev, 5973 "Critical Failure setting up receive buffers\n"); 5974 err = ENOMEM; 5975 goto err_rx_desc; 5976 } 5977 5978 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5979 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5980 M_WAITOK); 5981 } 5982 5983 /* TXQs */ 5984 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5985 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5986 for (i = 0; i < ntxqsets; i++) { 5987 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5988 5989 for (j = 0; j < ntxqs; j++, di++) { 5990 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5991 paddrs[i*ntxqs + j] = di->idi_paddr; 5992 } 5993 } 5994 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5995 device_printf(ctx->ifc_dev, 5996 "Unable to allocate device TX queue\n"); 5997 iflib_tx_structures_free(ctx); 5998 free(vaddrs, M_IFLIB); 5999 free(paddrs, M_IFLIB); 6000 goto err_rx_desc; 6001 } 6002 free(vaddrs, M_IFLIB); 6003 free(paddrs, M_IFLIB); 6004 6005 /* RXQs */ 6006 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6007 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6008 for (i = 0; i < nrxqsets; i++) { 6009 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 6010 6011 for (j = 0; j < nrxqs; j++, di++) { 6012 vaddrs[i*nrxqs + j] = di->idi_vaddr; 6013 paddrs[i*nrxqs + j] = di->idi_paddr; 6014 } 6015 } 6016 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 6017 device_printf(ctx->ifc_dev, 6018 "Unable to allocate device RX queue\n"); 6019 iflib_tx_structures_free(ctx); 6020 free(vaddrs, M_IFLIB); 6021 free(paddrs, M_IFLIB); 6022 goto err_rx_desc; 6023 } 6024 free(vaddrs, M_IFLIB); 6025 free(paddrs, M_IFLIB); 6026 6027 return (0); 6028 6029 /* XXX handle allocation failure changes */ 6030 err_rx_desc: 6031 err_tx_desc: 6032 rx_fail: 6033 if (ctx->ifc_rxqs != NULL) 6034 free(ctx->ifc_rxqs, M_IFLIB); 6035 ctx->ifc_rxqs = NULL; 6036 if (ctx->ifc_txqs != NULL) 6037 free(ctx->ifc_txqs, M_IFLIB); 6038 ctx->ifc_txqs = NULL; 6039 fail: 6040 return (err); 6041 } 6042 6043 static int 6044 iflib_tx_structures_setup(if_ctx_t ctx) 6045 { 6046 iflib_txq_t txq = ctx->ifc_txqs; 6047 int i; 6048 6049 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 6050 iflib_txq_setup(txq); 6051 6052 return (0); 6053 } 6054 6055 static void 6056 iflib_tx_structures_free(if_ctx_t ctx) 6057 { 6058 iflib_txq_t txq = ctx->ifc_txqs; 6059 if_shared_ctx_t sctx = ctx->ifc_sctx; 6060 int i, j; 6061 6062 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6063 for (j = 0; j < sctx->isc_ntxqs; j++) 6064 iflib_dma_free(&txq->ift_ifdi[j]); 6065 iflib_txq_destroy(txq); 6066 } 6067 free(ctx->ifc_txqs, M_IFLIB); 6068 ctx->ifc_txqs = NULL; 6069 } 6070 6071 /********************************************************************* 6072 * 6073 * Initialize all receive rings. 6074 * 6075 **********************************************************************/ 6076 static int 6077 iflib_rx_structures_setup(if_ctx_t ctx) 6078 { 6079 iflib_rxq_t rxq = ctx->ifc_rxqs; 6080 int q; 6081 #if defined(INET6) || defined(INET) 6082 int err, i; 6083 #endif 6084 6085 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 6086 #if defined(INET6) || defined(INET) 6087 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 6088 TCP_LRO_ENTRIES, min(1024, 6089 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 6090 if (err != 0) { 6091 device_printf(ctx->ifc_dev, 6092 "LRO Initialization failed!\n"); 6093 goto fail; 6094 } 6095 #endif 6096 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 6097 } 6098 return (0); 6099 #if defined(INET6) || defined(INET) 6100 fail: 6101 /* 6102 * Free LRO resources allocated so far, we will only handle 6103 * the rings that completed, the failing case will have 6104 * cleaned up for itself. 'q' failed, so its the terminus. 6105 */ 6106 rxq = ctx->ifc_rxqs; 6107 for (i = 0; i < q; ++i, rxq++) { 6108 tcp_lro_free(&rxq->ifr_lc); 6109 } 6110 return (err); 6111 #endif 6112 } 6113 6114 /********************************************************************* 6115 * 6116 * Free all receive rings. 6117 * 6118 **********************************************************************/ 6119 static void 6120 iflib_rx_structures_free(if_ctx_t ctx) 6121 { 6122 iflib_rxq_t rxq = ctx->ifc_rxqs; 6123 if_shared_ctx_t sctx = ctx->ifc_sctx; 6124 int i, j; 6125 6126 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 6127 for (j = 0; j < sctx->isc_nrxqs; j++) 6128 iflib_dma_free(&rxq->ifr_ifdi[j]); 6129 iflib_rx_sds_free(rxq); 6130 #if defined(INET6) || defined(INET) 6131 tcp_lro_free(&rxq->ifr_lc); 6132 #endif 6133 } 6134 free(ctx->ifc_rxqs, M_IFLIB); 6135 ctx->ifc_rxqs = NULL; 6136 } 6137 6138 static int 6139 iflib_qset_structures_setup(if_ctx_t ctx) 6140 { 6141 int err; 6142 6143 /* 6144 * It is expected that the caller takes care of freeing queues if this 6145 * fails. 6146 */ 6147 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 6148 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 6149 return (err); 6150 } 6151 6152 if ((err = iflib_rx_structures_setup(ctx)) != 0) 6153 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 6154 6155 return (err); 6156 } 6157 6158 int 6159 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 6160 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 6161 { 6162 6163 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 6164 } 6165 6166 /* Just to avoid copy/paste */ 6167 static inline int 6168 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6169 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 6170 const char *name) 6171 { 6172 device_t dev; 6173 unsigned int base_cpuid, cpuid; 6174 int err; 6175 6176 dev = ctx->ifc_dev; 6177 base_cpuid = ctx->ifc_sysctl_core_offset; 6178 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX); 6179 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, 6180 irq ? irq->ii_res : NULL, name); 6181 if (err) { 6182 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6183 return (err); 6184 } 6185 #ifdef notyet 6186 if (cpuid > ctx->ifc_cpuid_highest) 6187 ctx->ifc_cpuid_highest = cpuid; 6188 #endif 6189 return (0); 6190 } 6191 6192 int 6193 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6194 iflib_intr_type_t type, driver_filter_t *filter, 6195 void *filter_arg, int qid, const char *name) 6196 { 6197 device_t dev; 6198 struct grouptask *gtask; 6199 struct taskqgroup *tqg; 6200 iflib_filter_info_t info; 6201 gtask_fn_t *fn; 6202 int tqrid, err; 6203 driver_filter_t *intr_fast; 6204 void *q; 6205 6206 info = &ctx->ifc_filter_info; 6207 tqrid = rid; 6208 6209 switch (type) { 6210 /* XXX merge tx/rx for netmap? */ 6211 case IFLIB_INTR_TX: 6212 q = &ctx->ifc_txqs[qid]; 6213 info = &ctx->ifc_txqs[qid].ift_filter_info; 6214 gtask = &ctx->ifc_txqs[qid].ift_task; 6215 tqg = qgroup_if_io_tqg; 6216 fn = _task_fn_tx; 6217 intr_fast = iflib_fast_intr; 6218 GROUPTASK_INIT(gtask, 0, fn, q); 6219 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6220 break; 6221 case IFLIB_INTR_RX: 6222 q = &ctx->ifc_rxqs[qid]; 6223 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6224 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6225 tqg = qgroup_if_io_tqg; 6226 fn = _task_fn_rx; 6227 intr_fast = iflib_fast_intr; 6228 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6229 break; 6230 case IFLIB_INTR_RXTX: 6231 q = &ctx->ifc_rxqs[qid]; 6232 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6233 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6234 tqg = qgroup_if_io_tqg; 6235 fn = _task_fn_rx; 6236 intr_fast = iflib_fast_intr_rxtx; 6237 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6238 break; 6239 case IFLIB_INTR_ADMIN: 6240 q = ctx; 6241 tqrid = -1; 6242 info = &ctx->ifc_filter_info; 6243 gtask = &ctx->ifc_admin_task; 6244 tqg = qgroup_if_config_tqg; 6245 fn = _task_fn_admin; 6246 intr_fast = iflib_fast_intr_ctx; 6247 break; 6248 default: 6249 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6250 __func__); 6251 return (EINVAL); 6252 } 6253 6254 info->ifi_filter = filter; 6255 info->ifi_filter_arg = filter_arg; 6256 info->ifi_task = gtask; 6257 info->ifi_ctx = q; 6258 6259 dev = ctx->ifc_dev; 6260 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6261 if (err != 0) { 6262 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6263 return (err); 6264 } 6265 if (type == IFLIB_INTR_ADMIN) 6266 return (0); 6267 6268 if (tqrid != -1) { 6269 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6270 name); 6271 if (err) 6272 return (err); 6273 } else { 6274 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6275 } 6276 6277 return (0); 6278 } 6279 6280 void 6281 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6282 void *arg, int qid, const char *name) 6283 { 6284 device_t dev; 6285 struct grouptask *gtask; 6286 struct taskqgroup *tqg; 6287 gtask_fn_t *fn; 6288 void *q; 6289 int err; 6290 6291 switch (type) { 6292 case IFLIB_INTR_TX: 6293 q = &ctx->ifc_txqs[qid]; 6294 gtask = &ctx->ifc_txqs[qid].ift_task; 6295 tqg = qgroup_if_io_tqg; 6296 fn = _task_fn_tx; 6297 GROUPTASK_INIT(gtask, 0, fn, q); 6298 break; 6299 case IFLIB_INTR_RX: 6300 q = &ctx->ifc_rxqs[qid]; 6301 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6302 tqg = qgroup_if_io_tqg; 6303 fn = _task_fn_rx; 6304 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6305 break; 6306 case IFLIB_INTR_IOV: 6307 q = ctx; 6308 gtask = &ctx->ifc_vflr_task; 6309 tqg = qgroup_if_config_tqg; 6310 fn = _task_fn_iov; 6311 GROUPTASK_INIT(gtask, 0, fn, q); 6312 break; 6313 default: 6314 panic("unknown net intr type"); 6315 } 6316 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name); 6317 if (err) { 6318 dev = ctx->ifc_dev; 6319 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL, 6320 name); 6321 } 6322 } 6323 6324 void 6325 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6326 { 6327 6328 if (irq->ii_tag) 6329 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6330 6331 if (irq->ii_res) 6332 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6333 rman_get_rid(irq->ii_res), irq->ii_res); 6334 } 6335 6336 static int 6337 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6338 { 6339 iflib_txq_t txq = ctx->ifc_txqs; 6340 iflib_rxq_t rxq = ctx->ifc_rxqs; 6341 if_irq_t irq = &ctx->ifc_legacy_irq; 6342 iflib_filter_info_t info; 6343 device_t dev; 6344 struct grouptask *gtask; 6345 struct resource *res; 6346 struct taskqgroup *tqg; 6347 void *q; 6348 int err, tqrid; 6349 bool rx_only; 6350 6351 q = &ctx->ifc_rxqs[0]; 6352 info = &rxq[0].ifr_filter_info; 6353 gtask = &rxq[0].ifr_task; 6354 tqg = qgroup_if_io_tqg; 6355 tqrid = *rid; 6356 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6357 6358 ctx->ifc_flags |= IFC_LEGACY; 6359 info->ifi_filter = filter; 6360 info->ifi_filter_arg = filter_arg; 6361 info->ifi_task = gtask; 6362 info->ifi_ctx = rx_only ? ctx : q; 6363 6364 dev = ctx->ifc_dev; 6365 /* We allocate a single interrupt resource */ 6366 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6367 iflib_fast_intr_rxtx, NULL, info, name); 6368 if (err != 0) 6369 return (err); 6370 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6371 res = irq->ii_res; 6372 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6373 6374 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6375 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6376 "tx"); 6377 return (0); 6378 } 6379 6380 void 6381 iflib_led_create(if_ctx_t ctx) 6382 { 6383 6384 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6385 device_get_nameunit(ctx->ifc_dev)); 6386 } 6387 6388 void 6389 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6390 { 6391 6392 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6393 } 6394 6395 void 6396 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6397 { 6398 6399 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6400 } 6401 6402 void 6403 iflib_admin_intr_deferred(if_ctx_t ctx) 6404 { 6405 6406 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6407 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6408 } 6409 6410 void 6411 iflib_iov_intr_deferred(if_ctx_t ctx) 6412 { 6413 6414 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6415 } 6416 6417 void 6418 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6419 { 6420 6421 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6422 name); 6423 } 6424 6425 void 6426 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6427 const char *name) 6428 { 6429 6430 GROUPTASK_INIT(gtask, 0, fn, ctx); 6431 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6432 name); 6433 } 6434 6435 void 6436 iflib_config_gtask_deinit(struct grouptask *gtask) 6437 { 6438 6439 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6440 } 6441 6442 void 6443 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6444 { 6445 if_t ifp = ctx->ifc_ifp; 6446 iflib_txq_t txq = ctx->ifc_txqs; 6447 6448 if_setbaudrate(ifp, baudrate); 6449 if (baudrate >= IF_Gbps(10)) { 6450 STATE_LOCK(ctx); 6451 ctx->ifc_flags |= IFC_PREFETCH; 6452 STATE_UNLOCK(ctx); 6453 } 6454 /* If link down, disable watchdog */ 6455 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6456 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6457 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6458 } 6459 ctx->ifc_link_state = link_state; 6460 if_link_state_change(ifp, link_state); 6461 } 6462 6463 static int 6464 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6465 { 6466 int credits; 6467 #ifdef INVARIANTS 6468 int credits_pre = txq->ift_cidx_processed; 6469 #endif 6470 6471 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6472 BUS_DMASYNC_POSTREAD); 6473 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6474 return (0); 6475 6476 txq->ift_processed += credits; 6477 txq->ift_cidx_processed += credits; 6478 6479 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6480 if (txq->ift_cidx_processed >= txq->ift_size) 6481 txq->ift_cidx_processed -= txq->ift_size; 6482 return (credits); 6483 } 6484 6485 static int 6486 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6487 { 6488 iflib_fl_t fl; 6489 u_int i; 6490 6491 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6492 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6493 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6494 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6495 budget)); 6496 } 6497 6498 void 6499 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6500 const char *description, if_int_delay_info_t info, 6501 int offset, int value) 6502 { 6503 info->iidi_ctx = ctx; 6504 info->iidi_offset = offset; 6505 info->iidi_value = value; 6506 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6507 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6508 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6509 info, 0, iflib_sysctl_int_delay, "I", description); 6510 } 6511 6512 struct sx * 6513 iflib_ctx_lock_get(if_ctx_t ctx) 6514 { 6515 6516 return (&ctx->ifc_ctx_sx); 6517 } 6518 6519 static int 6520 iflib_msix_init(if_ctx_t ctx) 6521 { 6522 device_t dev = ctx->ifc_dev; 6523 if_shared_ctx_t sctx = ctx->ifc_sctx; 6524 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6525 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6526 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6527 6528 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6529 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6530 6531 if (bootverbose) 6532 device_printf(dev, "msix_init qsets capped at %d\n", 6533 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6534 6535 /* Override by tuneable */ 6536 if (scctx->isc_disable_msix) 6537 goto msi; 6538 6539 /* First try MSI-X */ 6540 if ((msgs = pci_msix_count(dev)) == 0) { 6541 if (bootverbose) 6542 device_printf(dev, "MSI-X not supported or disabled\n"); 6543 goto msi; 6544 } 6545 6546 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6547 /* 6548 * bar == -1 => "trust me I know what I'm doing" 6549 * Some drivers are for hardware that is so shoddily 6550 * documented that no one knows which bars are which 6551 * so the developer has to map all bars. This hack 6552 * allows shoddy garbage to use MSI-X in this framework. 6553 */ 6554 if (bar != -1) { 6555 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6556 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6557 if (ctx->ifc_msix_mem == NULL) { 6558 device_printf(dev, "Unable to map MSI-X table\n"); 6559 goto msi; 6560 } 6561 } 6562 6563 admincnt = sctx->isc_admin_intrcnt; 6564 #if IFLIB_DEBUG 6565 /* use only 1 qset in debug mode */ 6566 queuemsgs = min(msgs - admincnt, 1); 6567 #else 6568 queuemsgs = msgs - admincnt; 6569 #endif 6570 #ifdef RSS 6571 queues = imin(queuemsgs, rss_getnumbuckets()); 6572 #else 6573 queues = queuemsgs; 6574 #endif 6575 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6576 if (bootverbose) 6577 device_printf(dev, 6578 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6579 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6580 #ifdef RSS 6581 /* If we're doing RSS, clamp at the number of RSS buckets */ 6582 if (queues > rss_getnumbuckets()) 6583 queues = rss_getnumbuckets(); 6584 #endif 6585 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6586 rx_queues = iflib_num_rx_queues; 6587 else 6588 rx_queues = queues; 6589 6590 if (rx_queues > scctx->isc_nrxqsets) 6591 rx_queues = scctx->isc_nrxqsets; 6592 6593 /* 6594 * We want this to be all logical CPUs by default 6595 */ 6596 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6597 tx_queues = iflib_num_tx_queues; 6598 else 6599 tx_queues = mp_ncpus; 6600 6601 if (tx_queues > scctx->isc_ntxqsets) 6602 tx_queues = scctx->isc_ntxqsets; 6603 6604 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6605 #ifdef INVARIANTS 6606 if (tx_queues != rx_queues) 6607 device_printf(dev, 6608 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6609 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6610 #endif 6611 tx_queues = min(rx_queues, tx_queues); 6612 rx_queues = min(rx_queues, tx_queues); 6613 } 6614 6615 vectors = rx_queues + admincnt; 6616 if (msgs < vectors) { 6617 device_printf(dev, 6618 "insufficient number of MSI-X vectors " 6619 "(supported %d, need %d)\n", msgs, vectors); 6620 goto msi; 6621 } 6622 6623 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6624 tx_queues); 6625 msgs = vectors; 6626 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6627 if (vectors != msgs) { 6628 device_printf(dev, 6629 "Unable to allocate sufficient MSI-X vectors " 6630 "(got %d, need %d)\n", vectors, msgs); 6631 pci_release_msi(dev); 6632 if (bar != -1) { 6633 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6634 ctx->ifc_msix_mem); 6635 ctx->ifc_msix_mem = NULL; 6636 } 6637 goto msi; 6638 } 6639 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6640 vectors); 6641 scctx->isc_vectors = vectors; 6642 scctx->isc_nrxqsets = rx_queues; 6643 scctx->isc_ntxqsets = tx_queues; 6644 scctx->isc_intr = IFLIB_INTR_MSIX; 6645 6646 return (vectors); 6647 } else { 6648 device_printf(dev, 6649 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6650 err); 6651 if (bar != -1) { 6652 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6653 ctx->ifc_msix_mem); 6654 ctx->ifc_msix_mem = NULL; 6655 } 6656 } 6657 6658 msi: 6659 vectors = pci_msi_count(dev); 6660 scctx->isc_nrxqsets = 1; 6661 scctx->isc_ntxqsets = 1; 6662 scctx->isc_vectors = vectors; 6663 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6664 device_printf(dev,"Using an MSI interrupt\n"); 6665 scctx->isc_intr = IFLIB_INTR_MSI; 6666 } else { 6667 scctx->isc_vectors = 1; 6668 device_printf(dev,"Using a Legacy interrupt\n"); 6669 scctx->isc_intr = IFLIB_INTR_LEGACY; 6670 } 6671 6672 return (vectors); 6673 } 6674 6675 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6676 6677 static int 6678 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6679 { 6680 int rc; 6681 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6682 struct sbuf *sb; 6683 const char *ring_state = "UNKNOWN"; 6684 6685 /* XXX needed ? */ 6686 rc = sysctl_wire_old_buffer(req, 0); 6687 MPASS(rc == 0); 6688 if (rc != 0) 6689 return (rc); 6690 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6691 MPASS(sb != NULL); 6692 if (sb == NULL) 6693 return (ENOMEM); 6694 if (state[3] <= 3) 6695 ring_state = ring_states[state[3]]; 6696 6697 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6698 state[0], state[1], state[2], ring_state); 6699 rc = sbuf_finish(sb); 6700 sbuf_delete(sb); 6701 return(rc); 6702 } 6703 6704 enum iflib_ndesc_handler { 6705 IFLIB_NTXD_HANDLER, 6706 IFLIB_NRXD_HANDLER, 6707 }; 6708 6709 static int 6710 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6711 { 6712 if_ctx_t ctx = (void *)arg1; 6713 enum iflib_ndesc_handler type = arg2; 6714 char buf[256] = {0}; 6715 qidx_t *ndesc; 6716 char *p, *next; 6717 int nqs, rc, i; 6718 6719 nqs = 8; 6720 switch(type) { 6721 case IFLIB_NTXD_HANDLER: 6722 ndesc = ctx->ifc_sysctl_ntxds; 6723 if (ctx->ifc_sctx) 6724 nqs = ctx->ifc_sctx->isc_ntxqs; 6725 break; 6726 case IFLIB_NRXD_HANDLER: 6727 ndesc = ctx->ifc_sysctl_nrxds; 6728 if (ctx->ifc_sctx) 6729 nqs = ctx->ifc_sctx->isc_nrxqs; 6730 break; 6731 default: 6732 printf("%s: unhandled type\n", __func__); 6733 return (EINVAL); 6734 } 6735 if (nqs == 0) 6736 nqs = 8; 6737 6738 for (i=0; i<8; i++) { 6739 if (i >= nqs) 6740 break; 6741 if (i) 6742 strcat(buf, ","); 6743 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6744 } 6745 6746 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6747 if (rc || req->newptr == NULL) 6748 return rc; 6749 6750 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6751 i++, p = strsep(&next, " ,")) { 6752 ndesc[i] = strtoul(p, NULL, 10); 6753 } 6754 6755 return(rc); 6756 } 6757 6758 #define NAME_BUFLEN 32 6759 static void 6760 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6761 { 6762 device_t dev = iflib_get_dev(ctx); 6763 struct sysctl_oid_list *child, *oid_list; 6764 struct sysctl_ctx_list *ctx_list; 6765 struct sysctl_oid *node; 6766 6767 ctx_list = device_get_sysctl_ctx(dev); 6768 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6769 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6770 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 6771 oid_list = SYSCTL_CHILDREN(node); 6772 6773 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6774 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6775 "driver version"); 6776 6777 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6778 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6779 "# of txqs to use, 0 => use default #"); 6780 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6781 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6782 "# of rxqs to use, 0 => use default #"); 6783 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6784 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6785 "permit #txq != #rxq"); 6786 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6787 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6788 "disable MSI-X (default 0)"); 6789 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6790 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6791 "set the RX budget"); 6792 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6793 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6794 "cause TX to abdicate instead of running to completion"); 6795 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6796 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6797 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6798 "offset to start using cores at"); 6799 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6800 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6801 "use separate cores for TX and RX"); 6802 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "use_logical_cores", 6803 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0, 6804 "try to make use of logical cores for TX and RX"); 6805 6806 /* XXX change for per-queue sizes */ 6807 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6808 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6809 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6810 "list of # of TX descriptors to use, 0 = use default #"); 6811 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6812 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6813 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6814 "list of # of RX descriptors to use, 0 = use default #"); 6815 } 6816 6817 static void 6818 iflib_add_device_sysctl_post(if_ctx_t ctx) 6819 { 6820 if_shared_ctx_t sctx = ctx->ifc_sctx; 6821 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6822 device_t dev = iflib_get_dev(ctx); 6823 struct sysctl_oid_list *child; 6824 struct sysctl_ctx_list *ctx_list; 6825 iflib_fl_t fl; 6826 iflib_txq_t txq; 6827 iflib_rxq_t rxq; 6828 int i, j; 6829 char namebuf[NAME_BUFLEN]; 6830 char *qfmt; 6831 struct sysctl_oid *queue_node, *fl_node, *node; 6832 struct sysctl_oid_list *queue_list, *fl_list; 6833 ctx_list = device_get_sysctl_ctx(dev); 6834 6835 node = ctx->ifc_sysctl_node; 6836 child = SYSCTL_CHILDREN(node); 6837 6838 if (scctx->isc_ntxqsets > 100) 6839 qfmt = "txq%03d"; 6840 else if (scctx->isc_ntxqsets > 10) 6841 qfmt = "txq%02d"; 6842 else 6843 qfmt = "txq%d"; 6844 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6845 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6846 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6847 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6848 queue_list = SYSCTL_CHILDREN(queue_node); 6849 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 6850 CTLFLAG_RD, 6851 &txq->ift_task.gt_cpu, 0, "cpu this queue is bound to"); 6852 #if MEMORY_LOGGING 6853 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6854 CTLFLAG_RD, 6855 &txq->ift_dequeued, "total mbufs freed"); 6856 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6857 CTLFLAG_RD, 6858 &txq->ift_enqueued, "total mbufs enqueued"); 6859 #endif 6860 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6861 CTLFLAG_RD, 6862 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6863 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6864 CTLFLAG_RD, 6865 &txq->ift_pullups, "# of times m_pullup was called"); 6866 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6867 CTLFLAG_RD, 6868 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6869 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6870 CTLFLAG_RD, 6871 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6872 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6873 CTLFLAG_RD, 6874 &txq->ift_map_failed, "# of times DMA map failed"); 6875 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6876 CTLFLAG_RD, 6877 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6878 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6879 CTLFLAG_RD, 6880 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6881 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6882 CTLFLAG_RD, 6883 &txq->ift_pidx, 1, "Producer Index"); 6884 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6885 CTLFLAG_RD, 6886 &txq->ift_cidx, 1, "Consumer Index"); 6887 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6888 CTLFLAG_RD, 6889 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6890 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6891 CTLFLAG_RD, 6892 &txq->ift_in_use, 1, "descriptors in use"); 6893 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6894 CTLFLAG_RD, 6895 &txq->ift_processed, "descriptors procesed for clean"); 6896 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6897 CTLFLAG_RD, 6898 &txq->ift_cleaned, "total cleaned"); 6899 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6900 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6901 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6902 mp_ring_state_handler, "A", "soft ring state"); 6903 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6904 CTLFLAG_RD, &txq->ift_br->enqueues, 6905 "# of enqueues to the mp_ring for this queue"); 6906 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6907 CTLFLAG_RD, &txq->ift_br->drops, 6908 "# of drops in the mp_ring for this queue"); 6909 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6910 CTLFLAG_RD, &txq->ift_br->starts, 6911 "# of normal consumer starts in the mp_ring for this queue"); 6912 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6913 CTLFLAG_RD, &txq->ift_br->stalls, 6914 "# of consumer stalls in the mp_ring for this queue"); 6915 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6916 CTLFLAG_RD, &txq->ift_br->restarts, 6917 "# of consumer restarts in the mp_ring for this queue"); 6918 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6919 CTLFLAG_RD, &txq->ift_br->abdications, 6920 "# of consumer abdications in the mp_ring for this queue"); 6921 } 6922 6923 if (scctx->isc_nrxqsets > 100) 6924 qfmt = "rxq%03d"; 6925 else if (scctx->isc_nrxqsets > 10) 6926 qfmt = "rxq%02d"; 6927 else 6928 qfmt = "rxq%d"; 6929 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6930 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6931 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6932 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6933 queue_list = SYSCTL_CHILDREN(queue_node); 6934 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 6935 CTLFLAG_RD, 6936 &rxq->ifr_task.gt_cpu, 0, "cpu this queue is bound to"); 6937 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6938 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6939 CTLFLAG_RD, 6940 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6941 } 6942 6943 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6944 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6945 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6946 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 6947 fl_list = SYSCTL_CHILDREN(fl_node); 6948 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6949 CTLFLAG_RD, 6950 &fl->ifl_pidx, 1, "Producer Index"); 6951 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6952 CTLFLAG_RD, 6953 &fl->ifl_cidx, 1, "Consumer Index"); 6954 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6955 CTLFLAG_RD, 6956 &fl->ifl_credits, 1, "credits available"); 6957 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 6958 CTLFLAG_RD, 6959 &fl->ifl_buf_size, 1, "buffer size"); 6960 #if MEMORY_LOGGING 6961 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6962 CTLFLAG_RD, 6963 &fl->ifl_m_enqueued, "mbufs allocated"); 6964 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6965 CTLFLAG_RD, 6966 &fl->ifl_m_dequeued, "mbufs freed"); 6967 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6968 CTLFLAG_RD, 6969 &fl->ifl_cl_enqueued, "clusters allocated"); 6970 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6971 CTLFLAG_RD, 6972 &fl->ifl_cl_dequeued, "clusters freed"); 6973 #endif 6974 } 6975 } 6976 6977 } 6978 6979 void 6980 iflib_request_reset(if_ctx_t ctx) 6981 { 6982 6983 STATE_LOCK(ctx); 6984 ctx->ifc_flags |= IFC_DO_RESET; 6985 STATE_UNLOCK(ctx); 6986 } 6987 6988 #ifndef __NO_STRICT_ALIGNMENT 6989 static struct mbuf * 6990 iflib_fixup_rx(struct mbuf *m) 6991 { 6992 struct mbuf *n; 6993 6994 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6995 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6996 m->m_data += ETHER_HDR_LEN; 6997 n = m; 6998 } else { 6999 MGETHDR(n, M_NOWAIT, MT_DATA); 7000 if (n == NULL) { 7001 m_freem(m); 7002 return (NULL); 7003 } 7004 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 7005 m->m_data += ETHER_HDR_LEN; 7006 m->m_len -= ETHER_HDR_LEN; 7007 n->m_len = ETHER_HDR_LEN; 7008 M_MOVE_PKTHDR(n, m); 7009 n->m_next = m; 7010 } 7011 return (n); 7012 } 7013 #endif 7014 7015 #ifdef DEBUGNET 7016 static void 7017 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 7018 { 7019 if_ctx_t ctx; 7020 7021 ctx = if_getsoftc(ifp); 7022 CTX_LOCK(ctx); 7023 *nrxr = NRXQSETS(ctx); 7024 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 7025 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 7026 CTX_UNLOCK(ctx); 7027 } 7028 7029 static void 7030 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 7031 { 7032 if_ctx_t ctx; 7033 if_softc_ctx_t scctx; 7034 iflib_fl_t fl; 7035 iflib_rxq_t rxq; 7036 int i, j; 7037 7038 ctx = if_getsoftc(ifp); 7039 scctx = &ctx->ifc_softc_ctx; 7040 7041 switch (event) { 7042 case DEBUGNET_START: 7043 for (i = 0; i < scctx->isc_nrxqsets; i++) { 7044 rxq = &ctx->ifc_rxqs[i]; 7045 for (j = 0; j < rxq->ifr_nfl; j++) { 7046 fl = rxq->ifr_fl; 7047 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 7048 } 7049 } 7050 iflib_no_tx_batch = 1; 7051 break; 7052 default: 7053 break; 7054 } 7055 } 7056 7057 static int 7058 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 7059 { 7060 if_ctx_t ctx; 7061 iflib_txq_t txq; 7062 int error; 7063 7064 ctx = if_getsoftc(ifp); 7065 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7066 IFF_DRV_RUNNING) 7067 return (EBUSY); 7068 7069 txq = &ctx->ifc_txqs[0]; 7070 error = iflib_encap(txq, &m); 7071 if (error == 0) 7072 (void)iflib_txd_db_check(txq, true); 7073 return (error); 7074 } 7075 7076 static int 7077 iflib_debugnet_poll(if_t ifp, int count) 7078 { 7079 struct epoch_tracker et; 7080 if_ctx_t ctx; 7081 if_softc_ctx_t scctx; 7082 iflib_txq_t txq; 7083 int i; 7084 7085 ctx = if_getsoftc(ifp); 7086 scctx = &ctx->ifc_softc_ctx; 7087 7088 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7089 IFF_DRV_RUNNING) 7090 return (EBUSY); 7091 7092 txq = &ctx->ifc_txqs[0]; 7093 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 7094 7095 NET_EPOCH_ENTER(et); 7096 for (i = 0; i < scctx->isc_nrxqsets; i++) 7097 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 7098 NET_EPOCH_EXIT(et); 7099 return (0); 7100 } 7101 #endif /* DEBUGNET */ 7102