1 /*- 2 * Copyright (c) 2014-2017, Matthew Macy <mmacy@nextbsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 35 #include <sys/param.h> 36 #include <sys/types.h> 37 #include <sys/bus.h> 38 #include <sys/eventhandler.h> 39 #include <sys/sockio.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sysctl.h> 50 #include <sys/syslog.h> 51 #include <sys/taskqueue.h> 52 #include <sys/limits.h> 53 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 63 #include <netinet/in.h> 64 #include <netinet/in_pcb.h> 65 #include <netinet/tcp_lro.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/if_ether.h> 68 #include <netinet/ip.h> 69 #include <netinet/ip6.h> 70 #include <netinet/tcp.h> 71 72 #include <machine/bus.h> 73 #include <machine/in_cksum.h> 74 75 #include <vm/vm.h> 76 #include <vm/pmap.h> 77 78 #include <dev/led/led.h> 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pci_private.h> 82 83 #include <net/iflib.h> 84 85 #include "ifdi_if.h" 86 87 #if defined(__i386__) || defined(__amd64__) 88 #include <sys/memdesc.h> 89 #include <machine/bus.h> 90 #include <machine/md_var.h> 91 #include <machine/specialreg.h> 92 #include <x86/include/busdma_impl.h> 93 #include <x86/iommu/busdma_dmar.h> 94 #endif 95 96 /* 97 * enable accounting of every mbuf as it comes in to and goes out of iflib's software descriptor references 98 */ 99 #define MEMORY_LOGGING 0 100 /* 101 * Enable mbuf vectors for compressing long mbuf chains 102 */ 103 104 /* 105 * NB: 106 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 107 * we prefetch needs to be determined by the time spent in m_free vis a vis 108 * the cost of a prefetch. This will of course vary based on the workload: 109 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 110 * is quite expensive, thus suggesting very little prefetch. 111 * - small packet forwarding which is just returning a single mbuf to 112 * UMA will typically be very fast vis a vis the cost of a memory 113 * access. 114 */ 115 116 117 /* 118 * File organization: 119 * - private structures 120 * - iflib private utility functions 121 * - ifnet functions 122 * - vlan registry and other exported functions 123 * - iflib public core functions 124 * 125 * 126 */ 127 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 128 129 struct iflib_txq; 130 typedef struct iflib_txq *iflib_txq_t; 131 struct iflib_rxq; 132 typedef struct iflib_rxq *iflib_rxq_t; 133 struct iflib_fl; 134 typedef struct iflib_fl *iflib_fl_t; 135 136 struct iflib_ctx; 137 138 typedef struct iflib_filter_info { 139 driver_filter_t *ifi_filter; 140 void *ifi_filter_arg; 141 struct grouptask *ifi_task; 142 struct iflib_ctx *ifi_ctx; 143 } *iflib_filter_info_t; 144 145 struct iflib_ctx { 146 KOBJ_FIELDS; 147 /* 148 * Pointer to hardware driver's softc 149 */ 150 void *ifc_softc; 151 device_t ifc_dev; 152 if_t ifc_ifp; 153 154 cpuset_t ifc_cpus; 155 if_shared_ctx_t ifc_sctx; 156 struct if_softc_ctx ifc_softc_ctx; 157 158 struct mtx ifc_mtx; 159 160 uint16_t ifc_nhwtxqs; 161 uint16_t ifc_nhwrxqs; 162 163 iflib_txq_t ifc_txqs; 164 iflib_rxq_t ifc_rxqs; 165 uint32_t ifc_if_flags; 166 uint32_t ifc_flags; 167 uint32_t ifc_max_fl_buf_size; 168 int ifc_in_detach; 169 170 int ifc_link_state; 171 int ifc_link_irq; 172 int ifc_pause_frames; 173 int ifc_watchdog_events; 174 struct cdev *ifc_led_dev; 175 struct resource *ifc_msix_mem; 176 177 struct if_irq ifc_legacy_irq; 178 struct grouptask ifc_admin_task; 179 struct grouptask ifc_vflr_task; 180 struct iflib_filter_info ifc_filter_info; 181 struct ifmedia ifc_media; 182 183 struct sysctl_oid *ifc_sysctl_node; 184 uint16_t ifc_sysctl_ntxqs; 185 uint16_t ifc_sysctl_nrxqs; 186 uint16_t ifc_sysctl_qs_eq_override; 187 188 uint16_t ifc_sysctl_ntxds[8]; 189 uint16_t ifc_sysctl_nrxds[8]; 190 struct if_txrx ifc_txrx; 191 #define isc_txd_encap ifc_txrx.ift_txd_encap 192 #define isc_txd_flush ifc_txrx.ift_txd_flush 193 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 194 #define isc_rxd_available ifc_txrx.ift_rxd_available 195 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 196 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 197 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 198 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 199 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 200 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 201 eventhandler_tag ifc_vlan_attach_event; 202 eventhandler_tag ifc_vlan_detach_event; 203 uint8_t ifc_mac[ETHER_ADDR_LEN]; 204 char ifc_mtx_name[16]; 205 }; 206 207 208 void * 209 iflib_get_softc(if_ctx_t ctx) 210 { 211 212 return (ctx->ifc_softc); 213 } 214 215 device_t 216 iflib_get_dev(if_ctx_t ctx) 217 { 218 219 return (ctx->ifc_dev); 220 } 221 222 if_t 223 iflib_get_ifp(if_ctx_t ctx) 224 { 225 226 return (ctx->ifc_ifp); 227 } 228 229 struct ifmedia * 230 iflib_get_media(if_ctx_t ctx) 231 { 232 233 return (&ctx->ifc_media); 234 } 235 236 void 237 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 238 { 239 240 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 241 } 242 243 if_softc_ctx_t 244 iflib_get_softc_ctx(if_ctx_t ctx) 245 { 246 247 return (&ctx->ifc_softc_ctx); 248 } 249 250 if_shared_ctx_t 251 iflib_get_sctx(if_ctx_t ctx) 252 { 253 254 return (ctx->ifc_sctx); 255 } 256 257 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 258 259 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 260 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 261 262 #define RX_SW_DESC_MAP_CREATED (1 << 0) 263 #define TX_SW_DESC_MAP_CREATED (1 << 1) 264 #define RX_SW_DESC_INUSE (1 << 3) 265 #define TX_SW_DESC_MAPPED (1 << 4) 266 267 typedef struct iflib_sw_rx_desc_array { 268 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 269 struct mbuf **ifsd_m; /* pkthdr mbufs */ 270 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 271 uint8_t *ifsd_flags; 272 } iflib_rxsd_array_t; 273 274 typedef struct iflib_sw_tx_desc_array { 275 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 276 struct mbuf **ifsd_m; /* pkthdr mbufs */ 277 uint8_t *ifsd_flags; 278 } iflib_txsd_array_t; 279 280 281 /* magic number that should be high enough for any hardware */ 282 #define IFLIB_MAX_TX_SEGS 128 283 #define IFLIB_MAX_RX_SEGS 32 284 #define IFLIB_RX_COPY_THRESH 63 285 #define IFLIB_MAX_RX_REFRESH 32 286 #define IFLIB_QUEUE_IDLE 0 287 #define IFLIB_QUEUE_HUNG 1 288 #define IFLIB_QUEUE_WORKING 2 289 290 /* this should really scale with ring size - 32 is a fairly arbitrary value for this */ 291 #define TX_BATCH_SIZE 16 292 293 #define IFLIB_RESTART_BUDGET 8 294 295 #define IFC_LEGACY 0x01 296 #define IFC_QFLUSH 0x02 297 #define IFC_MULTISEG 0x04 298 #define IFC_DMAR 0x08 299 #define IFC_SC_ALLOCATED 0x10 300 #define IFC_INIT_DONE 0x20 301 302 303 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 304 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 305 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 306 struct iflib_txq { 307 uint16_t ift_in_use; 308 uint16_t ift_cidx; 309 uint16_t ift_cidx_processed; 310 uint16_t ift_pidx; 311 uint8_t ift_gen; 312 uint8_t ift_db_pending; 313 uint8_t ift_db_pending_queued; 314 uint8_t ift_npending; 315 uint8_t ift_br_offset; 316 /* implicit pad */ 317 uint64_t ift_processed; 318 uint64_t ift_cleaned; 319 #if MEMORY_LOGGING 320 uint64_t ift_enqueued; 321 uint64_t ift_dequeued; 322 #endif 323 uint64_t ift_no_tx_dma_setup; 324 uint64_t ift_no_desc_avail; 325 uint64_t ift_mbuf_defrag_failed; 326 uint64_t ift_mbuf_defrag; 327 uint64_t ift_map_failed; 328 uint64_t ift_txd_encap_efbig; 329 uint64_t ift_pullups; 330 331 struct mtx ift_mtx; 332 struct mtx ift_db_mtx; 333 334 /* constant values */ 335 if_ctx_t ift_ctx; 336 struct ifmp_ring **ift_br; 337 struct grouptask ift_task; 338 uint16_t ift_size; 339 uint16_t ift_id; 340 struct callout ift_timer; 341 struct callout ift_db_check; 342 343 iflib_txsd_array_t ift_sds; 344 uint8_t ift_nbr; 345 uint8_t ift_qstatus; 346 uint8_t ift_active; 347 uint8_t ift_closed; 348 int ift_watchdog_time; 349 struct iflib_filter_info ift_filter_info; 350 bus_dma_tag_t ift_desc_tag; 351 bus_dma_tag_t ift_tso_desc_tag; 352 iflib_dma_info_t ift_ifdi; 353 #define MTX_NAME_LEN 16 354 char ift_mtx_name[MTX_NAME_LEN]; 355 char ift_db_mtx_name[MTX_NAME_LEN]; 356 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 357 #ifdef IFLIB_DIAGNOSTICS 358 uint64_t ift_cpu_exec_count[256]; 359 #endif 360 } __aligned(CACHE_LINE_SIZE); 361 362 struct iflib_fl { 363 uint16_t ifl_cidx; 364 uint16_t ifl_pidx; 365 uint16_t ifl_credits; 366 uint8_t ifl_gen; 367 #if MEMORY_LOGGING 368 uint64_t ifl_m_enqueued; 369 uint64_t ifl_m_dequeued; 370 uint64_t ifl_cl_enqueued; 371 uint64_t ifl_cl_dequeued; 372 #endif 373 /* implicit pad */ 374 375 /* constant */ 376 uint16_t ifl_size; 377 uint16_t ifl_buf_size; 378 uint16_t ifl_cltype; 379 uma_zone_t ifl_zone; 380 iflib_rxsd_array_t ifl_sds; 381 iflib_rxq_t ifl_rxq; 382 uint8_t ifl_id; 383 bus_dma_tag_t ifl_desc_tag; 384 iflib_dma_info_t ifl_ifdi; 385 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 386 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 387 } __aligned(CACHE_LINE_SIZE); 388 389 static inline int 390 get_inuse(int size, int cidx, int pidx, int gen) 391 { 392 int used; 393 394 if (pidx > cidx) 395 used = pidx - cidx; 396 else if (pidx < cidx) 397 used = size - cidx + pidx; 398 else if (gen == 0 && pidx == cidx) 399 used = 0; 400 else if (gen == 1 && pidx == cidx) 401 used = size; 402 else 403 panic("bad state"); 404 405 return (used); 406 } 407 408 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 409 410 #define IDXDIFF(head, tail, wrap) \ 411 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 412 413 struct iflib_rxq { 414 /* If there is a separate completion queue - 415 * these are the cq cidx and pidx. Otherwise 416 * these are unused. 417 */ 418 uint16_t ifr_size; 419 uint16_t ifr_cq_cidx; 420 uint16_t ifr_cq_pidx; 421 uint8_t ifr_cq_gen; 422 uint8_t ifr_fl_offset; 423 424 if_ctx_t ifr_ctx; 425 iflib_fl_t ifr_fl; 426 uint64_t ifr_rx_irq; 427 uint16_t ifr_id; 428 uint8_t ifr_lro_enabled; 429 uint8_t ifr_nfl; 430 struct lro_ctrl ifr_lc; 431 struct grouptask ifr_task; 432 struct iflib_filter_info ifr_filter_info; 433 iflib_dma_info_t ifr_ifdi; 434 /* dynamically allocate if any drivers need a value substantially larger than this */ 435 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 436 #ifdef IFLIB_DIAGNOSTICS 437 uint64_t ifr_cpu_exec_count[256]; 438 #endif 439 } __aligned(CACHE_LINE_SIZE); 440 441 /* 442 * Only allow a single packet to take up most 1/nth of the tx ring 443 */ 444 #define MAX_SINGLE_PACKET_FRACTION 12 445 #define IF_BAD_DMA (bus_addr_t)-1 446 447 static int enable_msix = 1; 448 449 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 450 451 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF) 452 453 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx) 454 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx) 455 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx) 456 457 458 #define TXDB_LOCK_INIT(txq) mtx_init(&(txq)->ift_db_mtx, (txq)->ift_db_mtx_name, NULL, MTX_DEF) 459 #define TXDB_TRYLOCK(txq) mtx_trylock(&(txq)->ift_db_mtx) 460 #define TXDB_LOCK(txq) mtx_lock(&(txq)->ift_db_mtx) 461 #define TXDB_UNLOCK(txq) mtx_unlock(&(txq)->ift_db_mtx) 462 #define TXDB_LOCK_DESTROY(txq) mtx_destroy(&(txq)->ift_db_mtx) 463 464 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 465 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 466 467 468 /* Our boot-time initialization hook */ 469 static int iflib_module_event_handler(module_t, int, void *); 470 471 static moduledata_t iflib_moduledata = { 472 "iflib", 473 iflib_module_event_handler, 474 NULL 475 }; 476 477 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 478 MODULE_VERSION(iflib, 1); 479 480 MODULE_DEPEND(iflib, pci, 1, 1, 1); 481 MODULE_DEPEND(iflib, ether, 1, 1, 1); 482 483 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 484 485 #ifndef IFLIB_DEBUG_COUNTERS 486 #ifdef INVARIANTS 487 #define IFLIB_DEBUG_COUNTERS 1 488 #else 489 #define IFLIB_DEBUG_COUNTERS 0 490 #endif /* !INVARIANTS */ 491 #endif 492 493 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 494 "iflib driver parameters"); 495 496 /* 497 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 498 */ 499 static int iflib_min_tx_latency = 0; 500 501 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 502 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 503 504 505 #if IFLIB_DEBUG_COUNTERS 506 507 static int iflib_tx_seen; 508 static int iflib_tx_sent; 509 static int iflib_tx_encap; 510 static int iflib_rx_allocs; 511 static int iflib_fl_refills; 512 static int iflib_fl_refills_large; 513 static int iflib_tx_frees; 514 515 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 516 &iflib_tx_seen, 0, "# tx mbufs seen"); 517 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 518 &iflib_tx_sent, 0, "# tx mbufs sent"); 519 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 520 &iflib_tx_encap, 0, "# tx mbufs encapped"); 521 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 522 &iflib_tx_frees, 0, "# tx frees"); 523 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 524 &iflib_rx_allocs, 0, "# rx allocations"); 525 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 526 &iflib_fl_refills, 0, "# refills"); 527 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 528 &iflib_fl_refills_large, 0, "# large refills"); 529 530 531 static int iflib_txq_drain_flushing; 532 static int iflib_txq_drain_oactive; 533 static int iflib_txq_drain_notready; 534 static int iflib_txq_drain_encapfail; 535 536 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 537 &iflib_txq_drain_flushing, 0, "# drain flushes"); 538 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 539 &iflib_txq_drain_oactive, 0, "# drain oactives"); 540 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 541 &iflib_txq_drain_notready, 0, "# drain notready"); 542 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 543 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 544 545 546 static int iflib_encap_load_mbuf_fail; 547 static int iflib_encap_txq_avail_fail; 548 static int iflib_encap_txd_encap_fail; 549 550 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 551 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 552 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 553 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 554 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 555 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 556 557 static int iflib_task_fn_rxs; 558 static int iflib_rx_intr_enables; 559 static int iflib_fast_intrs; 560 static int iflib_intr_link; 561 static int iflib_intr_msix; 562 static int iflib_rx_unavail; 563 static int iflib_rx_ctx_inactive; 564 static int iflib_rx_zero_len; 565 static int iflib_rx_if_input; 566 static int iflib_rx_mbuf_null; 567 static int iflib_rxd_flush; 568 569 static int iflib_verbose_debug; 570 571 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 572 &iflib_intr_link, 0, "# intr link calls"); 573 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 574 &iflib_intr_msix, 0, "# intr msix calls"); 575 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 576 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 577 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 578 &iflib_rx_intr_enables, 0, "# rx intr enables"); 579 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 580 &iflib_fast_intrs, 0, "# fast_intr calls"); 581 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 582 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 583 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 584 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 585 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 586 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 587 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 588 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 589 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 590 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 591 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 592 &iflib_rxd_flush, 0, "# times rxd_flush called"); 593 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 594 &iflib_verbose_debug, 0, "enable verbose debugging"); 595 596 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 597 static void 598 iflib_debug_reset(void) 599 { 600 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 601 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 602 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 603 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 604 iflib_encap_load_mbuf_fail = iflib_encap_txq_avail_fail = 605 iflib_encap_txd_encap_fail = iflib_task_fn_rxs = iflib_rx_intr_enables = 606 iflib_fast_intrs = iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 607 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 608 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 609 } 610 611 #else 612 #define DBG_COUNTER_INC(name) 613 static void iflib_debug_reset(void) {} 614 #endif 615 616 617 618 #define IFLIB_DEBUG 0 619 620 static void iflib_tx_structures_free(if_ctx_t ctx); 621 static void iflib_rx_structures_free(if_ctx_t ctx); 622 static int iflib_queues_alloc(if_ctx_t ctx); 623 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 624 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, int cidx, int budget); 625 static int iflib_qset_structures_setup(if_ctx_t ctx); 626 static int iflib_msix_init(if_ctx_t ctx); 627 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str); 628 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 629 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 630 static int iflib_register(if_ctx_t); 631 static void iflib_init_locked(if_ctx_t ctx); 632 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 633 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 634 static void iflib_ifmp_purge(iflib_txq_t txq); 635 static void _iflib_pre_assert(if_softc_ctx_t scctx); 636 637 #ifdef DEV_NETMAP 638 #include <sys/selinfo.h> 639 #include <net/netmap.h> 640 #include <dev/netmap/netmap_kern.h> 641 642 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 643 644 /* 645 * device-specific sysctl variables: 646 * 647 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 648 * During regular operations the CRC is stripped, but on some 649 * hardware reception of frames not multiple of 64 is slower, 650 * so using crcstrip=0 helps in benchmarks. 651 * 652 * iflib_rx_miss, iflib_rx_miss_bufs: 653 * count packets that might be missed due to lost interrupts. 654 */ 655 SYSCTL_DECL(_dev_netmap); 656 /* 657 * The xl driver by default strips CRCs and we do not override it. 658 */ 659 660 int iflib_crcstrip = 1; 661 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 662 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 663 664 int iflib_rx_miss, iflib_rx_miss_bufs; 665 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 666 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 667 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 668 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 669 670 /* 671 * Register/unregister. We are already under netmap lock. 672 * Only called on the first register or the last unregister. 673 */ 674 static int 675 iflib_netmap_register(struct netmap_adapter *na, int onoff) 676 { 677 struct ifnet *ifp = na->ifp; 678 if_ctx_t ctx = ifp->if_softc; 679 680 CTX_LOCK(ctx); 681 IFDI_INTR_DISABLE(ctx); 682 683 /* Tell the stack that the interface is no longer active */ 684 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 685 686 if (!CTX_IS_VF(ctx)) 687 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 688 689 /* enable or disable flags and callbacks in na and ifp */ 690 if (onoff) { 691 nm_set_native_flags(na); 692 } else { 693 nm_clear_native_flags(na); 694 } 695 IFDI_INIT(ctx); 696 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 697 CTX_UNLOCK(ctx); 698 return (ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1); 699 } 700 701 /* 702 * Reconcile kernel and user view of the transmit ring. 703 * 704 * All information is in the kring. 705 * Userspace wants to send packets up to the one before kring->rhead, 706 * kernel knows kring->nr_hwcur is the first unsent packet. 707 * 708 * Here we push packets out (as many as possible), and possibly 709 * reclaim buffers from previously completed transmission. 710 * 711 * The caller (netmap) guarantees that there is only one instance 712 * running at any time. Any interference with other driver 713 * methods should be handled by the individual drivers. 714 */ 715 static int 716 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 717 { 718 struct netmap_adapter *na = kring->na; 719 struct ifnet *ifp = na->ifp; 720 struct netmap_ring *ring = kring->ring; 721 u_int nm_i; /* index into the netmap ring */ 722 u_int nic_i; /* index into the NIC ring */ 723 u_int n; 724 u_int const lim = kring->nkr_num_slots - 1; 725 u_int const head = kring->rhead; 726 struct if_pkt_info pi; 727 728 /* 729 * interrupts on every tx packet are expensive so request 730 * them every half ring, or where NS_REPORT is set 731 */ 732 u_int report_frequency = kring->nkr_num_slots >> 1; 733 /* device-specific */ 734 if_ctx_t ctx = ifp->if_softc; 735 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 736 737 pi.ipi_segs = txq->ift_segs; 738 pi.ipi_qsidx = kring->ring_id; 739 pi.ipi_ndescs = 0; 740 741 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 742 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 743 744 745 /* 746 * First part: process new packets to send. 747 * nm_i is the current index in the netmap ring, 748 * nic_i is the corresponding index in the NIC ring. 749 * 750 * If we have packets to send (nm_i != head) 751 * iterate over the netmap ring, fetch length and update 752 * the corresponding slot in the NIC ring. Some drivers also 753 * need to update the buffer's physical address in the NIC slot 754 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 755 * 756 * The netmap_reload_map() calls is especially expensive, 757 * even when (as in this case) the tag is 0, so do only 758 * when the buffer has actually changed. 759 * 760 * If possible do not set the report/intr bit on all slots, 761 * but only a few times per ring or when NS_REPORT is set. 762 * 763 * Finally, on 10G and faster drivers, it might be useful 764 * to prefetch the next slot and txr entry. 765 */ 766 767 nm_i = kring->nr_hwcur; 768 if (nm_i != head) { /* we have new packets to send */ 769 nic_i = netmap_idx_k2n(kring, nm_i); 770 771 __builtin_prefetch(&ring->slot[nm_i]); 772 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 773 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 774 775 for (n = 0; nm_i != head; n++) { 776 struct netmap_slot *slot = &ring->slot[nm_i]; 777 u_int len = slot->len; 778 uint64_t paddr; 779 void *addr = PNMB(na, slot, &paddr); 780 int flags = (slot->flags & NS_REPORT || 781 nic_i == 0 || nic_i == report_frequency) ? 782 IPI_TX_INTR : 0; 783 784 /* device-specific */ 785 pi.ipi_pidx = nic_i; 786 pi.ipi_flags = flags; 787 788 /* Fill the slot in the NIC ring. */ 789 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 790 791 /* prefetch for next round */ 792 __builtin_prefetch(&ring->slot[nm_i + 1]); 793 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 794 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 795 796 NM_CHECK_ADDR_LEN(na, addr, len); 797 798 if (slot->flags & NS_BUF_CHANGED) { 799 /* buffer has changed, reload map */ 800 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 801 } 802 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 803 804 /* make sure changes to the buffer are synced */ 805 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 806 BUS_DMASYNC_PREWRITE); 807 808 nm_i = nm_next(nm_i, lim); 809 nic_i = nm_next(nic_i, lim); 810 } 811 kring->nr_hwcur = head; 812 813 /* synchronize the NIC ring */ 814 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 815 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 816 817 /* (re)start the tx unit up to slot nic_i (excluded) */ 818 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 819 } 820 821 /* 822 * Second part: reclaim buffers for completed transmissions. 823 */ 824 if (iflib_tx_credits_update(ctx, txq)) { 825 /* some tx completed, increment avail */ 826 nic_i = txq->ift_cidx_processed; 827 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 828 } 829 return (0); 830 } 831 832 /* 833 * Reconcile kernel and user view of the receive ring. 834 * Same as for the txsync, this routine must be efficient. 835 * The caller guarantees a single invocations, but races against 836 * the rest of the driver should be handled here. 837 * 838 * On call, kring->rhead is the first packet that userspace wants 839 * to keep, and kring->rcur is the wakeup point. 840 * The kernel has previously reported packets up to kring->rtail. 841 * 842 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 843 * of whether or not we received an interrupt. 844 */ 845 static int 846 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 847 { 848 struct netmap_adapter *na = kring->na; 849 struct ifnet *ifp = na->ifp; 850 struct netmap_ring *ring = kring->ring; 851 u_int nm_i; /* index into the netmap ring */ 852 u_int nic_i; /* index into the NIC ring */ 853 u_int i, n; 854 u_int const lim = kring->nkr_num_slots - 1; 855 u_int const head = kring->rhead; 856 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 857 struct if_rxd_info ri; 858 /* device-specific */ 859 if_ctx_t ctx = ifp->if_softc; 860 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 861 iflib_fl_t fl = rxq->ifr_fl; 862 if (head > lim) 863 return netmap_ring_reinit(kring); 864 865 bzero(&ri, sizeof(ri)); 866 ri.iri_qsidx = kring->ring_id; 867 ri.iri_ifp = ctx->ifc_ifp; 868 /* XXX check sync modes */ 869 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) 870 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 871 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 872 873 /* 874 * First part: import newly received packets. 875 * 876 * nm_i is the index of the next free slot in the netmap ring, 877 * nic_i is the index of the next received packet in the NIC ring, 878 * and they may differ in case if_init() has been called while 879 * in netmap mode. For the receive ring we have 880 * 881 * nic_i = rxr->next_check; 882 * nm_i = kring->nr_hwtail (previous) 883 * and 884 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 885 * 886 * rxr->next_check is set to 0 on a ring reinit 887 */ 888 if (netmap_no_pendintr || force_update) { 889 int crclen = iflib_crcstrip ? 0 : 4; 890 int error, avail; 891 uint16_t slot_flags = kring->nkr_slot_flags; 892 893 for (fl = rxq->ifr_fl, i = 0; i < rxq->ifr_nfl; i++, fl++) { 894 nic_i = fl->ifl_cidx; 895 nm_i = netmap_idx_n2k(kring, nic_i); 896 avail = ctx->isc_rxd_available(ctx->ifc_softc, kring->ring_id, nic_i, INT_MAX); 897 for (n = 0; avail > 0; n++, avail--) { 898 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 899 if (error) 900 ring->slot[nm_i].len = 0; 901 else 902 ring->slot[nm_i].len = ri.iri_len - crclen; 903 ring->slot[nm_i].flags = slot_flags; 904 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 905 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 906 nm_i = nm_next(nm_i, lim); 907 nic_i = nm_next(nic_i, lim); 908 } 909 if (n) { /* update the state variables */ 910 if (netmap_no_pendintr && !force_update) { 911 /* diagnostics */ 912 iflib_rx_miss ++; 913 iflib_rx_miss_bufs += n; 914 } 915 fl->ifl_cidx = nic_i; 916 kring->nr_hwtail = nm_i; 917 } 918 kring->nr_kflags &= ~NKR_PENDINTR; 919 } 920 } 921 /* 922 * Second part: skip past packets that userspace has released. 923 * (kring->nr_hwcur to head excluded), 924 * and make the buffers available for reception. 925 * As usual nm_i is the index in the netmap ring, 926 * nic_i is the index in the NIC ring, and 927 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 928 */ 929 /* XXX not sure how this will work with multiple free lists */ 930 nm_i = kring->nr_hwcur; 931 if (nm_i != head) { 932 nic_i = netmap_idx_k2n(kring, nm_i); 933 for (n = 0; nm_i != head; n++) { 934 struct netmap_slot *slot = &ring->slot[nm_i]; 935 uint64_t paddr; 936 caddr_t vaddr; 937 void *addr = PNMB(na, slot, &paddr); 938 939 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 940 goto ring_reset; 941 942 vaddr = addr; 943 if (slot->flags & NS_BUF_CHANGED) { 944 /* buffer has changed, reload map */ 945 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i], addr); 946 slot->flags &= ~NS_BUF_CHANGED; 947 } 948 /* 949 * XXX we should be batching this operation - TODO 950 */ 951 ctx->isc_rxd_refill(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i, &paddr, &vaddr, 1, fl->ifl_buf_size); 952 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i], 953 BUS_DMASYNC_PREREAD); 954 nm_i = nm_next(nm_i, lim); 955 nic_i = nm_next(nic_i, lim); 956 } 957 kring->nr_hwcur = head; 958 959 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 960 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 961 /* 962 * IMPORTANT: we must leave one free slot in the ring, 963 * so move nic_i back by one unit 964 */ 965 nic_i = nm_prev(nic_i, lim); 966 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 967 } 968 969 return 0; 970 971 ring_reset: 972 return netmap_ring_reinit(kring); 973 } 974 975 static int 976 iflib_netmap_attach(if_ctx_t ctx) 977 { 978 struct netmap_adapter na; 979 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 980 981 bzero(&na, sizeof(na)); 982 983 na.ifp = ctx->ifc_ifp; 984 na.na_flags = NAF_BDG_MAYSLEEP; 985 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 986 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 987 988 na.num_tx_desc = scctx->isc_ntxd[0]; 989 na.num_rx_desc = scctx->isc_nrxd[0]; 990 na.nm_txsync = iflib_netmap_txsync; 991 na.nm_rxsync = iflib_netmap_rxsync; 992 na.nm_register = iflib_netmap_register; 993 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 994 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 995 return (netmap_attach(&na)); 996 } 997 998 static void 999 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1000 { 1001 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1002 struct netmap_slot *slot; 1003 1004 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1005 if (slot == NULL) 1006 return; 1007 1008 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1009 1010 /* 1011 * In netmap mode, set the map for the packet buffer. 1012 * NOTE: Some drivers (not this one) also need to set 1013 * the physical buffer address in the NIC ring. 1014 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1015 * netmap slot index, si 1016 */ 1017 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i); 1018 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1019 } 1020 } 1021 static void 1022 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1023 { 1024 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1025 struct netmap_slot *slot; 1026 bus_dmamap_t *map; 1027 int nrxd; 1028 1029 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1030 if (slot == NULL) 1031 return; 1032 map = rxq->ifr_fl[0].ifl_sds.ifsd_map; 1033 nrxd = ctx->ifc_softc_ctx.isc_nrxd[0]; 1034 for (int i = 0; i < nrxd; i++, map++) { 1035 int sj = netmap_idx_n2k(&na->rx_rings[rxq->ifr_id], i); 1036 uint64_t paddr; 1037 void *addr; 1038 caddr_t vaddr; 1039 1040 vaddr = addr = PNMB(na, slot + sj, &paddr); 1041 netmap_load_map(na, rxq->ifr_fl[0].ifl_ifdi->idi_tag, *map, addr); 1042 /* Update descriptor and the cached value */ 1043 ctx->isc_rxd_refill(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, i, &paddr, &vaddr, 1, rxq->ifr_fl[0].ifl_buf_size); 1044 } 1045 /* preserve queue */ 1046 if (ctx->ifc_ifp->if_capenable & IFCAP_NETMAP) { 1047 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id]; 1048 int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring); 1049 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, t); 1050 } else 1051 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, nrxd-1); 1052 } 1053 1054 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1055 1056 #else 1057 #define iflib_netmap_txq_init(ctx, txq) 1058 #define iflib_netmap_rxq_init(ctx, rxq) 1059 #define iflib_netmap_detach(ifp) 1060 1061 #define iflib_netmap_attach(ctx) (0) 1062 #define netmap_rx_irq(ifp, qid, budget) (0) 1063 1064 #endif 1065 1066 #if defined(__i386__) || defined(__amd64__) 1067 static __inline void 1068 prefetch(void *x) 1069 { 1070 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1071 } 1072 #else 1073 #define prefetch(x) 1074 #endif 1075 1076 static void 1077 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1078 { 1079 if (err) 1080 return; 1081 *(bus_addr_t *) arg = segs[0].ds_addr; 1082 } 1083 1084 int 1085 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1086 { 1087 int err; 1088 if_shared_ctx_t sctx = ctx->ifc_sctx; 1089 device_t dev = ctx->ifc_dev; 1090 1091 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1092 1093 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1094 sctx->isc_q_align, 0, /* alignment, bounds */ 1095 BUS_SPACE_MAXADDR, /* lowaddr */ 1096 BUS_SPACE_MAXADDR, /* highaddr */ 1097 NULL, NULL, /* filter, filterarg */ 1098 size, /* maxsize */ 1099 1, /* nsegments */ 1100 size, /* maxsegsize */ 1101 BUS_DMA_ALLOCNOW, /* flags */ 1102 NULL, /* lockfunc */ 1103 NULL, /* lockarg */ 1104 &dma->idi_tag); 1105 if (err) { 1106 device_printf(dev, 1107 "%s: bus_dma_tag_create failed: %d\n", 1108 __func__, err); 1109 goto fail_0; 1110 } 1111 1112 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1113 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1114 if (err) { 1115 device_printf(dev, 1116 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1117 __func__, (uintmax_t)size, err); 1118 goto fail_1; 1119 } 1120 1121 dma->idi_paddr = IF_BAD_DMA; 1122 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1123 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1124 if (err || dma->idi_paddr == IF_BAD_DMA) { 1125 device_printf(dev, 1126 "%s: bus_dmamap_load failed: %d\n", 1127 __func__, err); 1128 goto fail_2; 1129 } 1130 1131 dma->idi_size = size; 1132 return (0); 1133 1134 fail_2: 1135 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1136 fail_1: 1137 bus_dma_tag_destroy(dma->idi_tag); 1138 fail_0: 1139 dma->idi_tag = NULL; 1140 1141 return (err); 1142 } 1143 1144 int 1145 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1146 { 1147 int i, err; 1148 iflib_dma_info_t *dmaiter; 1149 1150 dmaiter = dmalist; 1151 for (i = 0; i < count; i++, dmaiter++) { 1152 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1153 break; 1154 } 1155 if (err) 1156 iflib_dma_free_multi(dmalist, i); 1157 return (err); 1158 } 1159 1160 void 1161 iflib_dma_free(iflib_dma_info_t dma) 1162 { 1163 if (dma->idi_tag == NULL) 1164 return; 1165 if (dma->idi_paddr != IF_BAD_DMA) { 1166 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1167 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1168 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1169 dma->idi_paddr = IF_BAD_DMA; 1170 } 1171 if (dma->idi_vaddr != NULL) { 1172 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1173 dma->idi_vaddr = NULL; 1174 } 1175 bus_dma_tag_destroy(dma->idi_tag); 1176 dma->idi_tag = NULL; 1177 } 1178 1179 void 1180 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1181 { 1182 int i; 1183 iflib_dma_info_t *dmaiter = dmalist; 1184 1185 for (i = 0; i < count; i++, dmaiter++) 1186 iflib_dma_free(*dmaiter); 1187 } 1188 1189 #ifdef EARLY_AP_STARTUP 1190 static const int iflib_started = 1; 1191 #else 1192 /* 1193 * We used to abuse the smp_started flag to decide if the queues have been 1194 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1195 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1196 * is set. Run a SYSINIT() strictly after that to just set a usable 1197 * completion flag. 1198 */ 1199 1200 static int iflib_started; 1201 1202 static void 1203 iflib_record_started(void *arg) 1204 { 1205 iflib_started = 1; 1206 } 1207 1208 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1209 iflib_record_started, NULL); 1210 #endif 1211 1212 static int 1213 iflib_fast_intr(void *arg) 1214 { 1215 iflib_filter_info_t info = arg; 1216 struct grouptask *gtask = info->ifi_task; 1217 1218 if (!iflib_started) 1219 return (FILTER_HANDLED); 1220 1221 DBG_COUNTER_INC(fast_intrs); 1222 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1223 return (FILTER_HANDLED); 1224 1225 GROUPTASK_ENQUEUE(gtask); 1226 return (FILTER_HANDLED); 1227 } 1228 1229 static int 1230 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1231 driver_filter_t filter, driver_intr_t handler, void *arg, 1232 char *name) 1233 { 1234 int rc; 1235 struct resource *res; 1236 void *tag; 1237 device_t dev = ctx->ifc_dev; 1238 1239 MPASS(rid < 512); 1240 irq->ii_rid = rid; 1241 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, 1242 RF_SHAREABLE | RF_ACTIVE); 1243 if (res == NULL) { 1244 device_printf(dev, 1245 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1246 return (ENOMEM); 1247 } 1248 irq->ii_res = res; 1249 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1250 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1251 filter, handler, arg, &tag); 1252 if (rc != 0) { 1253 device_printf(dev, 1254 "failed to setup interrupt for rid %d, name %s: %d\n", 1255 rid, name ? name : "unknown", rc); 1256 return (rc); 1257 } else if (name) 1258 bus_describe_intr(dev, res, tag, "%s", name); 1259 1260 irq->ii_tag = tag; 1261 return (0); 1262 } 1263 1264 1265 /********************************************************************* 1266 * 1267 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1268 * the information needed to transmit a packet on the wire. This is 1269 * called only once at attach, setup is done every reset. 1270 * 1271 **********************************************************************/ 1272 1273 static int 1274 iflib_txsd_alloc(iflib_txq_t txq) 1275 { 1276 if_ctx_t ctx = txq->ift_ctx; 1277 if_shared_ctx_t sctx = ctx->ifc_sctx; 1278 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1279 device_t dev = ctx->ifc_dev; 1280 int err, nsegments, ntsosegments; 1281 1282 nsegments = scctx->isc_tx_nsegments; 1283 ntsosegments = scctx->isc_tx_tso_segments_max; 1284 MPASS(scctx->isc_ntxd[0] > 0); 1285 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1286 MPASS(nsegments > 0); 1287 MPASS(ntsosegments > 0); 1288 /* 1289 * Setup DMA descriptor areas. 1290 */ 1291 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1292 1, 0, /* alignment, bounds */ 1293 BUS_SPACE_MAXADDR, /* lowaddr */ 1294 BUS_SPACE_MAXADDR, /* highaddr */ 1295 NULL, NULL, /* filter, filterarg */ 1296 sctx->isc_tx_maxsize, /* maxsize */ 1297 nsegments, /* nsegments */ 1298 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1299 0, /* flags */ 1300 NULL, /* lockfunc */ 1301 NULL, /* lockfuncarg */ 1302 &txq->ift_desc_tag))) { 1303 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1304 device_printf(dev,"maxsize: %zd nsegments: %d maxsegsize: %zd\n", 1305 sctx->isc_tx_maxsize, nsegments, sctx->isc_tx_maxsegsize); 1306 goto fail; 1307 } 1308 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1309 1, 0, /* alignment, bounds */ 1310 BUS_SPACE_MAXADDR, /* lowaddr */ 1311 BUS_SPACE_MAXADDR, /* highaddr */ 1312 NULL, NULL, /* filter, filterarg */ 1313 scctx->isc_tx_tso_size_max, /* maxsize */ 1314 ntsosegments, /* nsegments */ 1315 scctx->isc_tx_tso_segsize_max, /* maxsegsize */ 1316 0, /* flags */ 1317 NULL, /* lockfunc */ 1318 NULL, /* lockfuncarg */ 1319 &txq->ift_tso_desc_tag))) { 1320 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1321 1322 goto fail; 1323 } 1324 if (!(txq->ift_sds.ifsd_flags = 1325 (uint8_t *) malloc(sizeof(uint8_t) * 1326 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1327 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1328 err = ENOMEM; 1329 goto fail; 1330 } 1331 if (!(txq->ift_sds.ifsd_m = 1332 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1333 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1334 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1335 err = ENOMEM; 1336 goto fail; 1337 } 1338 1339 /* Create the descriptor buffer dma maps */ 1340 #if defined(ACPI_DMAR) || (!(defined(__i386__) && !defined(__amd64__))) 1341 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1342 return (0); 1343 1344 if (!(txq->ift_sds.ifsd_map = 1345 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1346 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1347 err = ENOMEM; 1348 goto fail; 1349 } 1350 1351 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1352 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1353 if (err != 0) { 1354 device_printf(dev, "Unable to create TX DMA map\n"); 1355 goto fail; 1356 } 1357 } 1358 #endif 1359 return (0); 1360 fail: 1361 /* We free all, it handles case where we are in the middle */ 1362 iflib_tx_structures_free(ctx); 1363 return (err); 1364 } 1365 1366 static void 1367 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1368 { 1369 bus_dmamap_t map; 1370 1371 map = NULL; 1372 if (txq->ift_sds.ifsd_map != NULL) 1373 map = txq->ift_sds.ifsd_map[i]; 1374 if (map != NULL) { 1375 bus_dmamap_unload(txq->ift_desc_tag, map); 1376 bus_dmamap_destroy(txq->ift_desc_tag, map); 1377 txq->ift_sds.ifsd_map[i] = NULL; 1378 } 1379 } 1380 1381 static void 1382 iflib_txq_destroy(iflib_txq_t txq) 1383 { 1384 if_ctx_t ctx = txq->ift_ctx; 1385 1386 for (int i = 0; i < txq->ift_size; i++) 1387 iflib_txsd_destroy(ctx, txq, i); 1388 if (txq->ift_sds.ifsd_map != NULL) { 1389 free(txq->ift_sds.ifsd_map, M_IFLIB); 1390 txq->ift_sds.ifsd_map = NULL; 1391 } 1392 if (txq->ift_sds.ifsd_m != NULL) { 1393 free(txq->ift_sds.ifsd_m, M_IFLIB); 1394 txq->ift_sds.ifsd_m = NULL; 1395 } 1396 if (txq->ift_sds.ifsd_flags != NULL) { 1397 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1398 txq->ift_sds.ifsd_flags = NULL; 1399 } 1400 if (txq->ift_desc_tag != NULL) { 1401 bus_dma_tag_destroy(txq->ift_desc_tag); 1402 txq->ift_desc_tag = NULL; 1403 } 1404 if (txq->ift_tso_desc_tag != NULL) { 1405 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1406 txq->ift_tso_desc_tag = NULL; 1407 } 1408 } 1409 1410 static void 1411 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1412 { 1413 struct mbuf **mp; 1414 1415 mp = &txq->ift_sds.ifsd_m[i]; 1416 if (*mp == NULL) 1417 return; 1418 1419 if (txq->ift_sds.ifsd_map != NULL) { 1420 bus_dmamap_sync(txq->ift_desc_tag, 1421 txq->ift_sds.ifsd_map[i], 1422 BUS_DMASYNC_POSTWRITE); 1423 bus_dmamap_unload(txq->ift_desc_tag, 1424 txq->ift_sds.ifsd_map[i]); 1425 } 1426 m_free(*mp); 1427 DBG_COUNTER_INC(tx_frees); 1428 *mp = NULL; 1429 } 1430 1431 static int 1432 iflib_txq_setup(iflib_txq_t txq) 1433 { 1434 if_ctx_t ctx = txq->ift_ctx; 1435 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1436 iflib_dma_info_t di; 1437 int i; 1438 1439 /* Set number of descriptors available */ 1440 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1441 1442 /* Reset indices */ 1443 txq->ift_cidx_processed = txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1444 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1445 1446 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1447 bzero((void *)di->idi_vaddr, di->idi_size); 1448 1449 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1450 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1451 bus_dmamap_sync(di->idi_tag, di->idi_map, 1452 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1453 return (0); 1454 } 1455 1456 /********************************************************************* 1457 * 1458 * Allocate memory for rx_buffer structures. Since we use one 1459 * rx_buffer per received packet, the maximum number of rx_buffer's 1460 * that we'll need is equal to the number of receive descriptors 1461 * that we've allocated. 1462 * 1463 **********************************************************************/ 1464 static int 1465 iflib_rxsd_alloc(iflib_rxq_t rxq) 1466 { 1467 if_ctx_t ctx = rxq->ifr_ctx; 1468 if_shared_ctx_t sctx = ctx->ifc_sctx; 1469 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1470 device_t dev = ctx->ifc_dev; 1471 iflib_fl_t fl; 1472 int err; 1473 1474 MPASS(scctx->isc_nrxd[0] > 0); 1475 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1476 1477 fl = rxq->ifr_fl; 1478 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1479 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1480 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1481 1, 0, /* alignment, bounds */ 1482 BUS_SPACE_MAXADDR, /* lowaddr */ 1483 BUS_SPACE_MAXADDR, /* highaddr */ 1484 NULL, NULL, /* filter, filterarg */ 1485 sctx->isc_rx_maxsize, /* maxsize */ 1486 sctx->isc_rx_nsegments, /* nsegments */ 1487 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1488 0, /* flags */ 1489 NULL, /* lockfunc */ 1490 NULL, /* lockarg */ 1491 &fl->ifl_desc_tag); 1492 if (err) { 1493 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1494 __func__, err); 1495 goto fail; 1496 } 1497 if (!(fl->ifl_sds.ifsd_flags = 1498 (uint8_t *) malloc(sizeof(uint8_t) * 1499 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1500 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1501 err = ENOMEM; 1502 goto fail; 1503 } 1504 if (!(fl->ifl_sds.ifsd_m = 1505 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1506 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1507 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1508 err = ENOMEM; 1509 goto fail; 1510 } 1511 if (!(fl->ifl_sds.ifsd_cl = 1512 (caddr_t *) malloc(sizeof(caddr_t) * 1513 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1514 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1515 err = ENOMEM; 1516 goto fail; 1517 } 1518 1519 /* Create the descriptor buffer dma maps */ 1520 #if defined(ACPI_DMAR) || (!(defined(__i386__) && !defined(__amd64__))) 1521 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1522 continue; 1523 1524 if (!(fl->ifl_sds.ifsd_map = 1525 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1526 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1527 err = ENOMEM; 1528 goto fail; 1529 } 1530 1531 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1532 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1533 if (err != 0) { 1534 device_printf(dev, "Unable to create TX DMA map\n"); 1535 goto fail; 1536 } 1537 } 1538 #endif 1539 } 1540 return (0); 1541 1542 fail: 1543 iflib_rx_structures_free(ctx); 1544 return (err); 1545 } 1546 1547 1548 /* 1549 * Internal service routines 1550 */ 1551 1552 struct rxq_refill_cb_arg { 1553 int error; 1554 bus_dma_segment_t seg; 1555 int nseg; 1556 }; 1557 1558 static void 1559 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1560 { 1561 struct rxq_refill_cb_arg *cb_arg = arg; 1562 1563 cb_arg->error = error; 1564 cb_arg->seg = segs[0]; 1565 cb_arg->nseg = nseg; 1566 } 1567 1568 1569 #ifdef ACPI_DMAR 1570 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1571 #else 1572 #define IS_DMAR(ctx) (0) 1573 #endif 1574 1575 /** 1576 * rxq_refill - refill an rxq free-buffer list 1577 * @ctx: the iflib context 1578 * @rxq: the free-list to refill 1579 * @n: the number of new buffers to allocate 1580 * 1581 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1582 * The caller must assure that @n does not exceed the queue's capacity. 1583 */ 1584 static void 1585 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1586 { 1587 struct mbuf *m; 1588 int idx, pidx = fl->ifl_pidx; 1589 caddr_t cl, *sd_cl; 1590 struct mbuf **sd_m; 1591 uint8_t *sd_flags; 1592 bus_dmamap_t *sd_map; 1593 int n, i = 0; 1594 uint64_t bus_addr; 1595 int err; 1596 1597 sd_m = fl->ifl_sds.ifsd_m; 1598 sd_map = fl->ifl_sds.ifsd_map; 1599 sd_cl = fl->ifl_sds.ifsd_cl; 1600 sd_flags = fl->ifl_sds.ifsd_flags; 1601 idx = pidx; 1602 1603 n = count; 1604 MPASS(n > 0); 1605 MPASS(fl->ifl_credits + n <= fl->ifl_size); 1606 1607 if (pidx < fl->ifl_cidx) 1608 MPASS(pidx + n <= fl->ifl_cidx); 1609 if (pidx == fl->ifl_cidx && (fl->ifl_credits < fl->ifl_size)) 1610 MPASS(fl->ifl_gen == 0); 1611 if (pidx > fl->ifl_cidx) 1612 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1613 1614 DBG_COUNTER_INC(fl_refills); 1615 if (n > 8) 1616 DBG_COUNTER_INC(fl_refills_large); 1617 1618 while (n--) { 1619 /* 1620 * We allocate an uninitialized mbuf + cluster, mbuf is 1621 * initialized after rx. 1622 * 1623 * If the cluster is still set then we know a minimum sized packet was received 1624 */ 1625 if ((cl = sd_cl[idx]) == NULL) { 1626 if ((cl = sd_cl[idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1627 break; 1628 #if MEMORY_LOGGING 1629 fl->ifl_cl_enqueued++; 1630 #endif 1631 } 1632 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1633 break; 1634 } 1635 #if MEMORY_LOGGING 1636 fl->ifl_m_enqueued++; 1637 #endif 1638 1639 DBG_COUNTER_INC(rx_allocs); 1640 #ifdef notyet 1641 if ((sd_flags[pidx] & RX_SW_DESC_MAP_CREATED) == 0) { 1642 int err; 1643 1644 if ((err = bus_dmamap_create(fl->ifl_ifdi->idi_tag, 0, &sd_map[idx]))) { 1645 log(LOG_WARNING, "bus_dmamap_create failed %d\n", err); 1646 uma_zfree(fl->ifl_zone, cl); 1647 n = 0; 1648 goto done; 1649 } 1650 sd_flags[idx] |= RX_SW_DESC_MAP_CREATED; 1651 } 1652 #endif 1653 #if defined(__i386__) || defined(__amd64__) 1654 if (!IS_DMAR(ctx)) { 1655 bus_addr = pmap_kextract((vm_offset_t)cl); 1656 } else 1657 #endif 1658 { 1659 struct rxq_refill_cb_arg cb_arg; 1660 iflib_rxq_t q; 1661 1662 cb_arg.error = 0; 1663 q = fl->ifl_rxq; 1664 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[idx], 1665 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1666 1667 if (err != 0 || cb_arg.error) { 1668 /* 1669 * !zone_pack ? 1670 */ 1671 if (fl->ifl_zone == zone_pack) 1672 uma_zfree(fl->ifl_zone, cl); 1673 m_free(m); 1674 n = 0; 1675 goto done; 1676 } 1677 bus_addr = cb_arg.seg.ds_addr; 1678 } 1679 sd_flags[idx] |= RX_SW_DESC_INUSE; 1680 1681 MPASS(sd_m[idx] == NULL); 1682 sd_cl[idx] = cl; 1683 sd_m[idx] = m; 1684 fl->ifl_bus_addrs[i] = bus_addr; 1685 fl->ifl_vm_addrs[i] = cl; 1686 fl->ifl_credits++; 1687 i++; 1688 MPASS(fl->ifl_credits <= fl->ifl_size); 1689 if (++idx == fl->ifl_size) { 1690 fl->ifl_gen = 1; 1691 idx = 0; 1692 } 1693 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 1694 ctx->isc_rxd_refill(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx, 1695 fl->ifl_bus_addrs, fl->ifl_vm_addrs, i, fl->ifl_buf_size); 1696 i = 0; 1697 pidx = idx; 1698 } 1699 fl->ifl_pidx = idx; 1700 1701 } 1702 done: 1703 DBG_COUNTER_INC(rxd_flush); 1704 if (fl->ifl_pidx == 0) 1705 pidx = fl->ifl_size - 1; 1706 else 1707 pidx = fl->ifl_pidx - 1; 1708 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 1709 } 1710 1711 static __inline void 1712 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 1713 { 1714 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 1715 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 1716 #ifdef INVARIANTS 1717 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 1718 #endif 1719 1720 MPASS(fl->ifl_credits <= fl->ifl_size); 1721 MPASS(reclaimable == delta); 1722 1723 if (reclaimable > 0) 1724 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 1725 } 1726 1727 static void 1728 iflib_fl_bufs_free(iflib_fl_t fl) 1729 { 1730 iflib_dma_info_t idi = fl->ifl_ifdi; 1731 uint32_t i; 1732 1733 for (i = 0; i < fl->ifl_size; i++) { 1734 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 1735 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 1736 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 1737 1738 if (*sd_flags & RX_SW_DESC_INUSE) { 1739 if (fl->ifl_sds.ifsd_map != NULL) { 1740 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 1741 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 1742 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 1743 } 1744 if (*sd_m != NULL) { 1745 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 1746 uma_zfree(zone_mbuf, *sd_m); 1747 } 1748 if (*sd_cl != NULL) 1749 uma_zfree(fl->ifl_zone, *sd_cl); 1750 *sd_flags = 0; 1751 } else { 1752 MPASS(*sd_cl == NULL); 1753 MPASS(*sd_m == NULL); 1754 } 1755 #if MEMORY_LOGGING 1756 fl->ifl_m_dequeued++; 1757 fl->ifl_cl_dequeued++; 1758 #endif 1759 *sd_cl = NULL; 1760 *sd_m = NULL; 1761 } 1762 /* 1763 * Reset free list values 1764 */ 1765 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = 0;; 1766 bzero(idi->idi_vaddr, idi->idi_size); 1767 } 1768 1769 /********************************************************************* 1770 * 1771 * Initialize a receive ring and its buffers. 1772 * 1773 **********************************************************************/ 1774 static int 1775 iflib_fl_setup(iflib_fl_t fl) 1776 { 1777 iflib_rxq_t rxq = fl->ifl_rxq; 1778 if_ctx_t ctx = rxq->ifr_ctx; 1779 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 1780 1781 /* 1782 ** Free current RX buffer structs and their mbufs 1783 */ 1784 iflib_fl_bufs_free(fl); 1785 /* Now replenish the mbufs */ 1786 MPASS(fl->ifl_credits == 0); 1787 /* 1788 * XXX don't set the max_frame_size to larger 1789 * than the hardware can handle 1790 */ 1791 if (sctx->isc_max_frame_size <= 2048) 1792 fl->ifl_buf_size = MCLBYTES; 1793 else if (sctx->isc_max_frame_size <= 4096) 1794 fl->ifl_buf_size = MJUMPAGESIZE; 1795 else if (sctx->isc_max_frame_size <= 9216) 1796 fl->ifl_buf_size = MJUM9BYTES; 1797 else 1798 fl->ifl_buf_size = MJUM16BYTES; 1799 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 1800 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 1801 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 1802 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 1803 1804 1805 /* avoid pre-allocating zillions of clusters to an idle card 1806 * potentially speeding up attach 1807 */ 1808 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 1809 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 1810 if (min(128, fl->ifl_size) != fl->ifl_credits) 1811 return (ENOBUFS); 1812 /* 1813 * handle failure 1814 */ 1815 MPASS(rxq != NULL); 1816 MPASS(fl->ifl_ifdi != NULL); 1817 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1818 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1819 return (0); 1820 } 1821 1822 /********************************************************************* 1823 * 1824 * Free receive ring data structures 1825 * 1826 **********************************************************************/ 1827 static void 1828 iflib_rx_sds_free(iflib_rxq_t rxq) 1829 { 1830 iflib_fl_t fl; 1831 int i; 1832 1833 if (rxq->ifr_fl != NULL) { 1834 for (i = 0; i < rxq->ifr_nfl; i++) { 1835 fl = &rxq->ifr_fl[i]; 1836 if (fl->ifl_desc_tag != NULL) { 1837 bus_dma_tag_destroy(fl->ifl_desc_tag); 1838 fl->ifl_desc_tag = NULL; 1839 } 1840 free(fl->ifl_sds.ifsd_m, M_IFLIB); 1841 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 1842 /* XXX destroy maps first */ 1843 free(fl->ifl_sds.ifsd_map, M_IFLIB); 1844 fl->ifl_sds.ifsd_m = NULL; 1845 fl->ifl_sds.ifsd_cl = NULL; 1846 fl->ifl_sds.ifsd_map = NULL; 1847 } 1848 free(rxq->ifr_fl, M_IFLIB); 1849 rxq->ifr_fl = NULL; 1850 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 1851 } 1852 } 1853 1854 /* 1855 * MI independent logic 1856 * 1857 */ 1858 static void 1859 iflib_timer(void *arg) 1860 { 1861 iflib_txq_t txq = arg; 1862 if_ctx_t ctx = txq->ift_ctx; 1863 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1864 1865 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 1866 return; 1867 /* 1868 ** Check on the state of the TX queue(s), this 1869 ** can be done without the lock because its RO 1870 ** and the HUNG state will be static if set. 1871 */ 1872 IFDI_TIMER(ctx, txq->ift_id); 1873 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 1874 (ctx->ifc_pause_frames == 0)) 1875 goto hung; 1876 1877 if (TXQ_AVAIL(txq) <= 2*scctx->isc_tx_nsegments || 1878 ifmp_ring_is_stalled(txq->ift_br[0])) 1879 GROUPTASK_ENQUEUE(&txq->ift_task); 1880 1881 ctx->ifc_pause_frames = 0; 1882 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 1883 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 1884 return; 1885 hung: 1886 CTX_LOCK(ctx); 1887 if_setdrvflagbits(ctx->ifc_ifp, 0, IFF_DRV_RUNNING); 1888 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 1889 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 1890 1891 IFDI_WATCHDOG_RESET(ctx); 1892 ctx->ifc_watchdog_events++; 1893 ctx->ifc_pause_frames = 0; 1894 1895 iflib_init_locked(ctx); 1896 CTX_UNLOCK(ctx); 1897 } 1898 1899 static void 1900 iflib_init_locked(if_ctx_t ctx) 1901 { 1902 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 1903 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1904 if_t ifp = ctx->ifc_ifp; 1905 iflib_fl_t fl; 1906 iflib_txq_t txq; 1907 iflib_rxq_t rxq; 1908 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 1909 1910 1911 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 1912 IFDI_INTR_DISABLE(ctx); 1913 1914 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 1915 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 1916 /* Set hardware offload abilities */ 1917 if_clearhwassist(ifp); 1918 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 1919 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 1920 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 1921 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 1922 if (if_getcapenable(ifp) & IFCAP_TSO4) 1923 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 1924 if (if_getcapenable(ifp) & IFCAP_TSO6) 1925 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 1926 1927 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 1928 CALLOUT_LOCK(txq); 1929 callout_stop(&txq->ift_timer); 1930 callout_stop(&txq->ift_db_check); 1931 CALLOUT_UNLOCK(txq); 1932 iflib_netmap_txq_init(ctx, txq); 1933 } 1934 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 1935 iflib_netmap_rxq_init(ctx, rxq); 1936 } 1937 #ifdef INVARIANTS 1938 i = if_getdrvflags(ifp); 1939 #endif 1940 IFDI_INIT(ctx); 1941 MPASS(if_getdrvflags(ifp) == i); 1942 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 1943 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 1944 if (iflib_fl_setup(fl)) { 1945 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 1946 goto done; 1947 } 1948 } 1949 } 1950 done: 1951 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 1952 IFDI_INTR_ENABLE(ctx); 1953 txq = ctx->ifc_txqs; 1954 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 1955 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 1956 txq->ift_timer.c_cpu); 1957 } 1958 1959 static int 1960 iflib_media_change(if_t ifp) 1961 { 1962 if_ctx_t ctx = if_getsoftc(ifp); 1963 int err; 1964 1965 CTX_LOCK(ctx); 1966 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 1967 iflib_init_locked(ctx); 1968 CTX_UNLOCK(ctx); 1969 return (err); 1970 } 1971 1972 static void 1973 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 1974 { 1975 if_ctx_t ctx = if_getsoftc(ifp); 1976 1977 CTX_LOCK(ctx); 1978 IFDI_UPDATE_ADMIN_STATUS(ctx); 1979 IFDI_MEDIA_STATUS(ctx, ifmr); 1980 CTX_UNLOCK(ctx); 1981 } 1982 1983 static void 1984 iflib_stop(if_ctx_t ctx) 1985 { 1986 iflib_txq_t txq = ctx->ifc_txqs; 1987 iflib_rxq_t rxq = ctx->ifc_rxqs; 1988 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1989 iflib_dma_info_t di; 1990 iflib_fl_t fl; 1991 int i, j; 1992 1993 /* Tell the stack that the interface is no longer active */ 1994 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 1995 1996 IFDI_INTR_DISABLE(ctx); 1997 DELAY(100000); 1998 IFDI_STOP(ctx); 1999 DELAY(100000); 2000 2001 iflib_debug_reset(); 2002 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2003 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2004 /* make sure all transmitters have completed before proceeding XXX */ 2005 2006 /* clean any enqueued buffers */ 2007 iflib_ifmp_purge(txq); 2008 /* Free any existing tx buffers. */ 2009 for (j = 0; j < txq->ift_size; j++) { 2010 iflib_txsd_free(ctx, txq, j); 2011 } 2012 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2013 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2014 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2015 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2016 txq->ift_pullups = 0; 2017 ifmp_ring_reset_stats(txq->ift_br[0]); 2018 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2019 bzero((void *)di->idi_vaddr, di->idi_size); 2020 } 2021 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2022 /* make sure all transmitters have completed before proceeding XXX */ 2023 2024 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++) 2025 bzero((void *)di->idi_vaddr, di->idi_size); 2026 /* also resets the free lists pidx/cidx */ 2027 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2028 iflib_fl_bufs_free(fl); 2029 } 2030 } 2031 2032 static inline void 2033 prefetch_pkts(iflib_fl_t fl, int cidx) 2034 { 2035 int nextptr; 2036 int nrxd = fl->ifl_size; 2037 2038 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2039 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2040 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2041 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2042 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2043 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2044 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2045 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2046 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2047 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2048 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2049 } 2050 2051 static void 2052 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int *cltype, int unload, iflib_fl_t *pfl, int *pcidx) 2053 { 2054 int flid, cidx; 2055 bus_dmamap_t map; 2056 iflib_fl_t fl; 2057 iflib_dma_info_t di; 2058 int next; 2059 2060 flid = irf->irf_flid; 2061 cidx = irf->irf_idx; 2062 fl = &rxq->ifr_fl[flid]; 2063 fl->ifl_credits--; 2064 #if MEMORY_LOGGING 2065 fl->ifl_m_dequeued++; 2066 if (cltype) 2067 fl->ifl_cl_dequeued++; 2068 #endif 2069 prefetch_pkts(fl, cidx); 2070 if (fl->ifl_sds.ifsd_map != NULL) { 2071 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2072 prefetch(&fl->ifl_sds.ifsd_map[next]); 2073 map = fl->ifl_sds.ifsd_map[cidx]; 2074 di = fl->ifl_ifdi; 2075 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2076 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2077 bus_dmamap_sync(di->idi_tag, di->idi_map, 2078 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2079 2080 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2081 MPASS(fl->ifl_cidx == cidx); 2082 if (unload) 2083 bus_dmamap_unload(fl->ifl_desc_tag, map); 2084 } 2085 if (__predict_false(++fl->ifl_cidx == fl->ifl_size)) { 2086 fl->ifl_cidx = 0; 2087 fl->ifl_gen = 0; 2088 } 2089 /* YES ick */ 2090 if (cltype) 2091 *cltype = fl->ifl_cltype; 2092 *pfl = fl; 2093 *pcidx = cidx; 2094 } 2095 2096 static struct mbuf * 2097 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri) 2098 { 2099 int i, padlen , flags, cltype; 2100 struct mbuf *m, *mh, *mt, *sd_m; 2101 iflib_fl_t fl; 2102 int cidx; 2103 caddr_t cl, sd_cl; 2104 2105 i = 0; 2106 mh = NULL; 2107 do { 2108 rxd_frag_to_sd(rxq, &ri->iri_frags[i], &cltype, TRUE, &fl, &cidx); 2109 sd_m = fl->ifl_sds.ifsd_m[cidx]; 2110 sd_cl = fl->ifl_sds.ifsd_cl[cidx]; 2111 2112 MPASS(sd_cl != NULL); 2113 MPASS(sd_m != NULL); 2114 2115 /* Don't include zero-length frags */ 2116 if (ri->iri_frags[i].irf_len == 0) { 2117 /* XXX we can save the cluster here, but not the mbuf */ 2118 m_init(sd_m, M_NOWAIT, MT_DATA, 0); 2119 m_free(sd_m); 2120 fl->ifl_sds.ifsd_m[cidx] = NULL; 2121 continue; 2122 } 2123 m = sd_m; 2124 if (mh == NULL) { 2125 flags = M_PKTHDR|M_EXT; 2126 mh = mt = m; 2127 padlen = ri->iri_pad; 2128 } else { 2129 flags = M_EXT; 2130 mt->m_next = m; 2131 mt = m; 2132 /* assuming padding is only on the first fragment */ 2133 padlen = 0; 2134 } 2135 fl->ifl_sds.ifsd_m[cidx] = NULL; 2136 cl = fl->ifl_sds.ifsd_cl[cidx]; 2137 fl->ifl_sds.ifsd_cl[cidx] = NULL; 2138 2139 /* Can these two be made one ? */ 2140 m_init(m, M_NOWAIT, MT_DATA, flags); 2141 m_cljset(m, cl, cltype); 2142 /* 2143 * These must follow m_init and m_cljset 2144 */ 2145 m->m_data += padlen; 2146 ri->iri_len -= padlen; 2147 m->m_len = ri->iri_frags[i].irf_len; 2148 } while (++i < ri->iri_nfrags); 2149 2150 return (mh); 2151 } 2152 2153 /* 2154 * Process one software descriptor 2155 */ 2156 static struct mbuf * 2157 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2158 { 2159 struct mbuf *m; 2160 iflib_fl_t fl; 2161 caddr_t sd_cl; 2162 int cidx; 2163 2164 /* should I merge this back in now that the two paths are basically duplicated? */ 2165 if (ri->iri_nfrags == 1 && 2166 ri->iri_frags[0].irf_len <= IFLIB_RX_COPY_THRESH) { 2167 rxd_frag_to_sd(rxq, &ri->iri_frags[0], NULL, FALSE, &fl, &cidx); 2168 m = fl->ifl_sds.ifsd_m[cidx]; 2169 fl->ifl_sds.ifsd_m[cidx] = NULL; 2170 sd_cl = fl->ifl_sds.ifsd_cl[cidx]; 2171 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2172 memcpy(m->m_data, sd_cl, ri->iri_len); 2173 m->m_len = ri->iri_frags[0].irf_len; 2174 } else { 2175 m = assemble_segments(rxq, ri); 2176 } 2177 m->m_pkthdr.len = ri->iri_len; 2178 m->m_pkthdr.rcvif = ri->iri_ifp; 2179 m->m_flags |= ri->iri_flags; 2180 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2181 m->m_pkthdr.flowid = ri->iri_flowid; 2182 M_HASHTYPE_SET(m, ri->iri_rsstype); 2183 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2184 m->m_pkthdr.csum_data = ri->iri_csum_data; 2185 return (m); 2186 } 2187 2188 static bool 2189 iflib_rxeof(iflib_rxq_t rxq, int budget) 2190 { 2191 if_ctx_t ctx = rxq->ifr_ctx; 2192 if_shared_ctx_t sctx = ctx->ifc_sctx; 2193 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2194 int avail, i; 2195 uint16_t *cidxp; 2196 struct if_rxd_info ri; 2197 int err, budget_left, rx_bytes, rx_pkts; 2198 iflib_fl_t fl; 2199 struct ifnet *ifp; 2200 int lro_enabled; 2201 /* 2202 * XXX early demux data packets so that if_input processing only handles 2203 * acks in interrupt context 2204 */ 2205 struct mbuf *m, *mh, *mt; 2206 2207 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &budget)) { 2208 return (FALSE); 2209 } 2210 2211 mh = mt = NULL; 2212 MPASS(budget > 0); 2213 rx_pkts = rx_bytes = 0; 2214 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2215 cidxp = &rxq->ifr_cq_cidx; 2216 else 2217 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2218 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2219 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2220 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2221 DBG_COUNTER_INC(rx_unavail); 2222 return (false); 2223 } 2224 2225 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2226 if (__predict_false(!CTX_ACTIVE(ctx))) { 2227 DBG_COUNTER_INC(rx_ctx_inactive); 2228 break; 2229 } 2230 /* 2231 * Reset client set fields to their default values 2232 */ 2233 bzero(&ri, sizeof(ri)); 2234 ri.iri_qsidx = rxq->ifr_id; 2235 ri.iri_cidx = *cidxp; 2236 ri.iri_ifp = ctx->ifc_ifp; 2237 ri.iri_frags = rxq->ifr_frags; 2238 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2239 2240 /* in lieu of handling correctly - make sure it isn't being unhandled */ 2241 MPASS(err == 0); 2242 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2243 *cidxp = ri.iri_cidx; 2244 /* Update our consumer index */ 2245 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2246 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2247 rxq->ifr_cq_gen = 0; 2248 } 2249 /* was this only a completion queue message? */ 2250 if (__predict_false(ri.iri_nfrags == 0)) 2251 continue; 2252 } 2253 MPASS(ri.iri_nfrags != 0); 2254 MPASS(ri.iri_len != 0); 2255 2256 /* will advance the cidx on the corresponding free lists */ 2257 m = iflib_rxd_pkt_get(rxq, &ri); 2258 if (avail == 0 && budget_left) 2259 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2260 2261 if (__predict_false(m == NULL)) { 2262 DBG_COUNTER_INC(rx_mbuf_null); 2263 continue; 2264 } 2265 /* imm_pkt: -- cxgb */ 2266 if (mh == NULL) 2267 mh = mt = m; 2268 else { 2269 mt->m_nextpkt = m; 2270 mt = m; 2271 } 2272 } 2273 /* make sure that we can refill faster than drain */ 2274 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2275 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2276 2277 ifp = ctx->ifc_ifp; 2278 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2279 while (mh != NULL) { 2280 m = mh; 2281 mh = mh->m_nextpkt; 2282 m->m_nextpkt = NULL; 2283 rx_bytes += m->m_pkthdr.len; 2284 rx_pkts++; 2285 #if defined(INET6) || defined(INET) 2286 if (lro_enabled && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2287 continue; 2288 #endif 2289 DBG_COUNTER_INC(rx_if_input); 2290 ifp->if_input(ifp, m); 2291 } 2292 2293 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2294 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2295 2296 /* 2297 * Flush any outstanding LRO work 2298 */ 2299 #if defined(INET6) || defined(INET) 2300 tcp_lro_flush_all(&rxq->ifr_lc); 2301 #endif 2302 if (avail) 2303 return true; 2304 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2305 } 2306 2307 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2308 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2309 #define TXQ_MAX_DB_DEFERRED(size) (size >> 5) 2310 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2311 2312 static __inline void 2313 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring) 2314 { 2315 uint32_t dbval; 2316 2317 if (ring || txq->ift_db_pending >= 2318 TXQ_MAX_DB_DEFERRED(txq->ift_size)) { 2319 2320 /* the lock will only ever be contended in the !min_latency case */ 2321 if (!TXDB_TRYLOCK(txq)) 2322 return; 2323 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2324 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2325 txq->ift_db_pending = txq->ift_npending = 0; 2326 TXDB_UNLOCK(txq); 2327 } 2328 } 2329 2330 static void 2331 iflib_txd_deferred_db_check(void * arg) 2332 { 2333 iflib_txq_t txq = arg; 2334 2335 /* simple non-zero boolean so use bitwise OR */ 2336 if ((txq->ift_db_pending | txq->ift_npending) && 2337 txq->ift_db_pending >= txq->ift_db_pending_queued) 2338 iflib_txd_db_check(txq->ift_ctx, txq, TRUE); 2339 txq->ift_db_pending_queued = 0; 2340 if (ifmp_ring_is_stalled(txq->ift_br[0])) 2341 iflib_txq_check_drain(txq, 4); 2342 } 2343 2344 #ifdef PKT_DEBUG 2345 static void 2346 print_pkt(if_pkt_info_t pi) 2347 { 2348 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2349 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2350 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2351 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2352 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2353 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2354 } 2355 #endif 2356 2357 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2358 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2359 2360 static int 2361 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2362 { 2363 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2364 struct ether_vlan_header *eh; 2365 struct mbuf *m, *n; 2366 2367 n = m = *mp; 2368 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2369 M_WRITABLE(m) == 0) { 2370 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2371 return (ENOMEM); 2372 } else { 2373 m_freem(*mp); 2374 n = *mp = m; 2375 } 2376 } 2377 2378 /* 2379 * Determine where frame payload starts. 2380 * Jump over vlan headers if already present, 2381 * helpful for QinQ too. 2382 */ 2383 if (__predict_false(m->m_len < sizeof(*eh))) { 2384 txq->ift_pullups++; 2385 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2386 return (ENOMEM); 2387 } 2388 eh = mtod(m, struct ether_vlan_header *); 2389 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2390 pi->ipi_etype = ntohs(eh->evl_proto); 2391 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2392 } else { 2393 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2394 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2395 } 2396 2397 switch (pi->ipi_etype) { 2398 #ifdef INET 2399 case ETHERTYPE_IP: 2400 { 2401 struct ip *ip = NULL; 2402 struct tcphdr *th = NULL; 2403 int minthlen; 2404 2405 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2406 if (__predict_false(m->m_len < minthlen)) { 2407 /* 2408 * if this code bloat is causing too much of a hit 2409 * move it to a separate function and mark it noinline 2410 */ 2411 if (m->m_len == pi->ipi_ehdrlen) { 2412 n = m->m_next; 2413 MPASS(n); 2414 if (n->m_len >= sizeof(*ip)) { 2415 ip = (struct ip *)n->m_data; 2416 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2417 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2418 } else { 2419 txq->ift_pullups++; 2420 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2421 return (ENOMEM); 2422 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2423 } 2424 } else { 2425 txq->ift_pullups++; 2426 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2427 return (ENOMEM); 2428 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2429 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2430 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2431 } 2432 } else { 2433 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2434 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2435 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2436 } 2437 pi->ipi_ip_hlen = ip->ip_hl << 2; 2438 pi->ipi_ipproto = ip->ip_p; 2439 pi->ipi_flags |= IPI_TX_IPV4; 2440 2441 if (pi->ipi_csum_flags & CSUM_IP) 2442 ip->ip_sum = 0; 2443 2444 if (pi->ipi_ipproto == IPPROTO_TCP) { 2445 if (__predict_false(th == NULL)) { 2446 txq->ift_pullups++; 2447 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2448 return (ENOMEM); 2449 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2450 } 2451 pi->ipi_tcp_hflags = th->th_flags; 2452 pi->ipi_tcp_hlen = th->th_off << 2; 2453 pi->ipi_tcp_seq = th->th_seq; 2454 } 2455 if (IS_TSO4(pi)) { 2456 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2457 return (ENXIO); 2458 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2459 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2460 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2461 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2462 ip->ip_sum = 0; 2463 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2464 } 2465 } 2466 break; 2467 } 2468 #endif 2469 #ifdef INET6 2470 case ETHERTYPE_IPV6: 2471 { 2472 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2473 struct tcphdr *th; 2474 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2475 2476 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2477 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2478 return (ENOMEM); 2479 } 2480 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2481 2482 /* XXX-BZ this will go badly in case of ext hdrs. */ 2483 pi->ipi_ipproto = ip6->ip6_nxt; 2484 pi->ipi_flags |= IPI_TX_IPV6; 2485 2486 if (pi->ipi_ipproto == IPPROTO_TCP) { 2487 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2488 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2489 return (ENOMEM); 2490 } 2491 pi->ipi_tcp_hflags = th->th_flags; 2492 pi->ipi_tcp_hlen = th->th_off << 2; 2493 } 2494 if (IS_TSO6(pi)) { 2495 2496 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2497 return (ENXIO); 2498 /* 2499 * The corresponding flag is set by the stack in the IPv4 2500 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 2501 * So, set it here because the rest of the flow requires it. 2502 */ 2503 pi->ipi_csum_flags |= CSUM_TCP_IPV6; 2504 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2505 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2506 } 2507 break; 2508 } 2509 #endif 2510 default: 2511 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2512 pi->ipi_ip_hlen = 0; 2513 break; 2514 } 2515 *mp = m; 2516 2517 return (0); 2518 } 2519 2520 static __noinline struct mbuf * 2521 collapse_pkthdr(struct mbuf *m0) 2522 { 2523 struct mbuf *m, *m_next, *tmp; 2524 2525 m = m0; 2526 m_next = m->m_next; 2527 while (m_next != NULL && m_next->m_len == 0) { 2528 m = m_next; 2529 m->m_next = NULL; 2530 m_free(m); 2531 m_next = m_next->m_next; 2532 } 2533 m = m0; 2534 m->m_next = m_next; 2535 if ((m_next->m_flags & M_EXT) == 0) { 2536 m = m_defrag(m, M_NOWAIT); 2537 } else { 2538 tmp = m_next->m_next; 2539 memcpy(m_next, m, MPKTHSIZE); 2540 m = m_next; 2541 m->m_next = tmp; 2542 } 2543 return (m); 2544 } 2545 2546 /* 2547 * If dodgy hardware rejects the scatter gather chain we've handed it 2548 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 2549 * m_defrag'd mbufs 2550 */ 2551 static __noinline struct mbuf * 2552 iflib_remove_mbuf(iflib_txq_t txq) 2553 { 2554 int ntxd, i, pidx; 2555 struct mbuf *m, *mh, **ifsd_m; 2556 2557 pidx = txq->ift_pidx; 2558 ifsd_m = txq->ift_sds.ifsd_m; 2559 ntxd = txq->ift_size; 2560 mh = m = ifsd_m[pidx]; 2561 ifsd_m[pidx] = NULL; 2562 #if MEMORY_LOGGING 2563 txq->ift_dequeued++; 2564 #endif 2565 i = 1; 2566 2567 while (m) { 2568 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 2569 #if MEMORY_LOGGING 2570 txq->ift_dequeued++; 2571 #endif 2572 m = m->m_next; 2573 i++; 2574 } 2575 return (mh); 2576 } 2577 2578 static int 2579 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 2580 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 2581 int max_segs, int flags) 2582 { 2583 if_ctx_t ctx; 2584 if_shared_ctx_t sctx; 2585 if_softc_ctx_t scctx; 2586 int i, next, pidx, mask, err, maxsegsz, ntxd, count; 2587 struct mbuf *m, *tmp, **ifsd_m, **mp; 2588 2589 m = *m0; 2590 2591 /* 2592 * Please don't ever do this 2593 */ 2594 if (__predict_false(m->m_len == 0)) 2595 *m0 = m = collapse_pkthdr(m); 2596 2597 ctx = txq->ift_ctx; 2598 sctx = ctx->ifc_sctx; 2599 scctx = &ctx->ifc_softc_ctx; 2600 ifsd_m = txq->ift_sds.ifsd_m; 2601 ntxd = txq->ift_size; 2602 pidx = txq->ift_pidx; 2603 if (map != NULL) { 2604 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 2605 2606 err = bus_dmamap_load_mbuf_sg(tag, map, 2607 *m0, segs, nsegs, BUS_DMA_NOWAIT); 2608 if (err) 2609 return (err); 2610 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 2611 i = 0; 2612 next = pidx; 2613 mask = (txq->ift_size-1); 2614 m = *m0; 2615 do { 2616 mp = &ifsd_m[next]; 2617 *mp = m; 2618 m = m->m_next; 2619 if (__predict_false((*mp)->m_len == 0)) { 2620 m_free(*mp); 2621 *mp = NULL; 2622 } else 2623 next = (pidx + i) & (ntxd-1); 2624 } while (m != NULL); 2625 } else { 2626 int buflen, sgsize, max_sgsize; 2627 vm_offset_t vaddr; 2628 vm_paddr_t curaddr; 2629 2630 count = i = 0; 2631 maxsegsz = sctx->isc_tx_maxsize; 2632 m = *m0; 2633 do { 2634 if (__predict_false(m->m_len <= 0)) { 2635 tmp = m; 2636 m = m->m_next; 2637 tmp->m_next = NULL; 2638 m_free(tmp); 2639 continue; 2640 } 2641 buflen = m->m_len; 2642 vaddr = (vm_offset_t)m->m_data; 2643 /* 2644 * see if we can't be smarter about physically 2645 * contiguous mappings 2646 */ 2647 next = (pidx + count) & (ntxd-1); 2648 MPASS(ifsd_m[next] == NULL); 2649 #if MEMORY_LOGGING 2650 txq->ift_enqueued++; 2651 #endif 2652 ifsd_m[next] = m; 2653 while (buflen > 0) { 2654 max_sgsize = MIN(buflen, maxsegsz); 2655 curaddr = pmap_kextract(vaddr); 2656 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 2657 sgsize = MIN(sgsize, max_sgsize); 2658 segs[i].ds_addr = curaddr; 2659 segs[i].ds_len = sgsize; 2660 vaddr += sgsize; 2661 buflen -= sgsize; 2662 i++; 2663 if (i >= max_segs) 2664 goto err; 2665 } 2666 count++; 2667 tmp = m; 2668 m = m->m_next; 2669 } while (m != NULL); 2670 *nsegs = i; 2671 } 2672 return (0); 2673 err: 2674 *m0 = iflib_remove_mbuf(txq); 2675 return (EFBIG); 2676 } 2677 2678 static int 2679 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 2680 { 2681 if_ctx_t ctx; 2682 if_shared_ctx_t sctx; 2683 if_softc_ctx_t scctx; 2684 bus_dma_segment_t *segs; 2685 struct mbuf *m_head; 2686 bus_dmamap_t map; 2687 struct if_pkt_info pi; 2688 int remap = 0; 2689 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 2690 bus_dma_tag_t desc_tag; 2691 2692 segs = txq->ift_segs; 2693 ctx = txq->ift_ctx; 2694 sctx = ctx->ifc_sctx; 2695 scctx = &ctx->ifc_softc_ctx; 2696 segs = txq->ift_segs; 2697 ntxd = txq->ift_size; 2698 m_head = *m_headp; 2699 map = NULL; 2700 2701 /* 2702 * If we're doing TSO the next descriptor to clean may be quite far ahead 2703 */ 2704 cidx = txq->ift_cidx; 2705 pidx = txq->ift_pidx; 2706 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 2707 2708 /* prefetch the next cache line of mbuf pointers and flags */ 2709 prefetch(&txq->ift_sds.ifsd_m[next]); 2710 if (txq->ift_sds.ifsd_map != NULL) { 2711 prefetch(&txq->ift_sds.ifsd_map[next]); 2712 map = txq->ift_sds.ifsd_map[pidx]; 2713 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 2714 prefetch(&txq->ift_sds.ifsd_flags[next]); 2715 } 2716 2717 2718 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 2719 desc_tag = txq->ift_tso_desc_tag; 2720 max_segs = scctx->isc_tx_tso_segments_max; 2721 } else { 2722 desc_tag = txq->ift_desc_tag; 2723 max_segs = scctx->isc_tx_nsegments; 2724 } 2725 m_head = *m_headp; 2726 bzero(&pi, sizeof(pi)); 2727 pi.ipi_len = m_head->m_pkthdr.len; 2728 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 2729 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 2730 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 2731 pi.ipi_pidx = pidx; 2732 pi.ipi_qsidx = txq->ift_id; 2733 2734 /* deliberate bitwise OR to make one condition */ 2735 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 2736 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 2737 return (err); 2738 m_head = *m_headp; 2739 } 2740 2741 retry: 2742 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 2743 defrag: 2744 if (__predict_false(err)) { 2745 switch (err) { 2746 case EFBIG: 2747 /* try collapse once and defrag once */ 2748 if (remap == 0) 2749 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 2750 if (remap == 1) 2751 m_head = m_defrag(*m_headp, M_NOWAIT); 2752 remap++; 2753 if (__predict_false(m_head == NULL)) 2754 goto defrag_failed; 2755 txq->ift_mbuf_defrag++; 2756 *m_headp = m_head; 2757 goto retry; 2758 break; 2759 case ENOMEM: 2760 txq->ift_no_tx_dma_setup++; 2761 break; 2762 default: 2763 txq->ift_no_tx_dma_setup++; 2764 m_freem(*m_headp); 2765 DBG_COUNTER_INC(tx_frees); 2766 *m_headp = NULL; 2767 break; 2768 } 2769 txq->ift_map_failed++; 2770 DBG_COUNTER_INC(encap_load_mbuf_fail); 2771 return (err); 2772 } 2773 2774 /* 2775 * XXX assumes a 1 to 1 relationship between segments and 2776 * descriptors - this does not hold true on all drivers, e.g. 2777 * cxgb 2778 */ 2779 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 2780 txq->ift_no_desc_avail++; 2781 if (map != NULL) 2782 bus_dmamap_unload(desc_tag, map); 2783 DBG_COUNTER_INC(encap_txq_avail_fail); 2784 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 2785 GROUPTASK_ENQUEUE(&txq->ift_task); 2786 return (ENOBUFS); 2787 } 2788 pi.ipi_segs = segs; 2789 pi.ipi_nsegs = nsegs; 2790 2791 MPASS(pidx >= 0 && pidx < txq->ift_size); 2792 #ifdef PKT_DEBUG 2793 print_pkt(&pi); 2794 #endif 2795 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 2796 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 2797 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2798 2799 DBG_COUNTER_INC(tx_encap); 2800 MPASS(pi.ipi_new_pidx >= 0 && 2801 pi.ipi_new_pidx < txq->ift_size); 2802 2803 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 2804 if (pi.ipi_new_pidx < pi.ipi_pidx) { 2805 ndesc += txq->ift_size; 2806 txq->ift_gen = 1; 2807 } 2808 /* 2809 * drivers can need as many as 2810 * two sentinels 2811 */ 2812 MPASS(ndesc <= pi.ipi_nsegs + 2); 2813 MPASS(pi.ipi_new_pidx != pidx); 2814 MPASS(ndesc > 0); 2815 txq->ift_in_use += ndesc; 2816 /* 2817 * We update the last software descriptor again here because there may 2818 * be a sentinel and/or there may be more mbufs than segments 2819 */ 2820 txq->ift_pidx = pi.ipi_new_pidx; 2821 txq->ift_npending += pi.ipi_ndescs; 2822 } else if (__predict_false(err == EFBIG && remap < 2)) { 2823 *m_headp = m_head = iflib_remove_mbuf(txq); 2824 remap = 1; 2825 txq->ift_txd_encap_efbig++; 2826 goto defrag; 2827 } else 2828 DBG_COUNTER_INC(encap_txd_encap_fail); 2829 return (err); 2830 2831 defrag_failed: 2832 txq->ift_mbuf_defrag_failed++; 2833 txq->ift_map_failed++; 2834 m_freem(*m_headp); 2835 DBG_COUNTER_INC(tx_frees); 2836 *m_headp = NULL; 2837 return (ENOMEM); 2838 } 2839 2840 /* forward compatibility for cxgb */ 2841 #define FIRST_QSET(ctx) 0 2842 2843 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2844 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2845 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2846 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2847 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2848 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2849 2850 2851 2852 /* if there are more than TXQ_MIN_OCCUPANCY packets pending we consider deferring 2853 * doorbell writes 2854 * 2855 * ORing with 2 assures that min occupancy is never less than 2 without any conditional logic 2856 */ 2857 #define TXQ_MIN_OCCUPANCY(size) ((size >> 6)| 0x2) 2858 2859 static inline int 2860 iflib_txq_min_occupancy(iflib_txq_t txq) 2861 { 2862 if_ctx_t ctx; 2863 2864 ctx = txq->ift_ctx; 2865 return (get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, 2866 txq->ift_gen) < TXQ_MIN_OCCUPANCY(txq->ift_size) + 2867 MAX_TX_DESC(ctx)); 2868 } 2869 2870 static void 2871 iflib_tx_desc_free(iflib_txq_t txq, int n) 2872 { 2873 int hasmap; 2874 uint32_t qsize, cidx, mask, gen; 2875 struct mbuf *m, **ifsd_m; 2876 uint8_t *ifsd_flags; 2877 bus_dmamap_t *ifsd_map; 2878 2879 cidx = txq->ift_cidx; 2880 gen = txq->ift_gen; 2881 qsize = txq->ift_size; 2882 mask = qsize-1; 2883 hasmap = txq->ift_sds.ifsd_map != NULL; 2884 ifsd_flags = txq->ift_sds.ifsd_flags; 2885 ifsd_m = txq->ift_sds.ifsd_m; 2886 ifsd_map = txq->ift_sds.ifsd_map; 2887 2888 while (n--) { 2889 prefetch(ifsd_m[(cidx + 3) & mask]); 2890 prefetch(ifsd_m[(cidx + 4) & mask]); 2891 2892 if (ifsd_m[cidx] != NULL) { 2893 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 2894 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 2895 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 2896 /* 2897 * does it matter if it's not the TSO tag? If so we'll 2898 * have to add the type to flags 2899 */ 2900 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 2901 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 2902 } 2903 if ((m = ifsd_m[cidx]) != NULL) { 2904 /* XXX we don't support any drivers that batch packets yet */ 2905 MPASS(m->m_nextpkt == NULL); 2906 2907 m_free(m); 2908 ifsd_m[cidx] = NULL; 2909 #if MEMORY_LOGGING 2910 txq->ift_dequeued++; 2911 #endif 2912 DBG_COUNTER_INC(tx_frees); 2913 } 2914 } 2915 if (__predict_false(++cidx == qsize)) { 2916 cidx = 0; 2917 gen = 0; 2918 } 2919 } 2920 txq->ift_cidx = cidx; 2921 txq->ift_gen = gen; 2922 } 2923 2924 static __inline int 2925 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 2926 { 2927 int reclaim; 2928 if_ctx_t ctx = txq->ift_ctx; 2929 2930 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 2931 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 2932 2933 /* 2934 * Need a rate-limiting check so that this isn't called every time 2935 */ 2936 iflib_tx_credits_update(ctx, txq); 2937 reclaim = DESC_RECLAIMABLE(txq); 2938 2939 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 2940 #ifdef INVARIANTS 2941 if (iflib_verbose_debug) { 2942 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 2943 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 2944 reclaim, thresh); 2945 2946 } 2947 #endif 2948 return (0); 2949 } 2950 iflib_tx_desc_free(txq, reclaim); 2951 txq->ift_cleaned += reclaim; 2952 txq->ift_in_use -= reclaim; 2953 2954 if (txq->ift_active == FALSE) 2955 txq->ift_active = TRUE; 2956 2957 return (reclaim); 2958 } 2959 2960 static struct mbuf ** 2961 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset) 2962 { 2963 2964 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (r->size-1)])); 2965 } 2966 2967 static void 2968 iflib_txq_check_drain(iflib_txq_t txq, int budget) 2969 { 2970 2971 ifmp_ring_check_drainage(txq->ift_br[0], budget); 2972 } 2973 2974 static uint32_t 2975 iflib_txq_can_drain(struct ifmp_ring *r) 2976 { 2977 iflib_txq_t txq = r->cookie; 2978 if_ctx_t ctx = txq->ift_ctx; 2979 2980 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 2981 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, txq->ift_cidx_processed, false)); 2982 } 2983 2984 static uint32_t 2985 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 2986 { 2987 iflib_txq_t txq = r->cookie; 2988 if_ctx_t ctx = txq->ift_ctx; 2989 if_t ifp = ctx->ifc_ifp; 2990 struct mbuf **mp, *m; 2991 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail, err, in_use_prev, desc_used; 2992 2993 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 2994 !LINK_ACTIVE(ctx))) { 2995 DBG_COUNTER_INC(txq_drain_notready); 2996 return (0); 2997 } 2998 2999 avail = IDXDIFF(pidx, cidx, r->size); 3000 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3001 DBG_COUNTER_INC(txq_drain_flushing); 3002 for (i = 0; i < avail; i++) { 3003 m_free(r->items[(cidx + i) & (r->size-1)]); 3004 r->items[(cidx + i) & (r->size-1)] = NULL; 3005 } 3006 return (avail); 3007 } 3008 iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3009 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3010 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3011 CALLOUT_LOCK(txq); 3012 callout_stop(&txq->ift_timer); 3013 callout_stop(&txq->ift_db_check); 3014 CALLOUT_UNLOCK(txq); 3015 DBG_COUNTER_INC(txq_drain_oactive); 3016 return (0); 3017 } 3018 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3019 count = MIN(avail, TX_BATCH_SIZE); 3020 #ifdef INVARIANTS 3021 if (iflib_verbose_debug) 3022 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3023 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3024 #endif 3025 3026 for (desc_used = i = 0; i < count && TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2; i++) { 3027 mp = _ring_peek_one(r, cidx, i); 3028 MPASS(mp != NULL && *mp != NULL); 3029 in_use_prev = txq->ift_in_use; 3030 if ((err = iflib_encap(txq, mp)) == ENOBUFS) { 3031 DBG_COUNTER_INC(txq_drain_encapfail); 3032 /* no room - bail out */ 3033 break; 3034 } 3035 consumed++; 3036 if (err) { 3037 DBG_COUNTER_INC(txq_drain_encapfail); 3038 /* we can't send this packet - skip it */ 3039 continue; 3040 } 3041 pkt_sent++; 3042 m = *mp; 3043 DBG_COUNTER_INC(tx_sent); 3044 bytes_sent += m->m_pkthdr.len; 3045 if (m->m_flags & M_MCAST) 3046 mcast_sent++; 3047 3048 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3049 desc_used += (txq->ift_in_use - in_use_prev); 3050 iflib_txd_db_check(ctx, txq, FALSE); 3051 ETHER_BPF_MTAP(ifp, m); 3052 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3053 break; 3054 3055 if (desc_used >= TXQ_MAX_DB_CONSUMED(txq->ift_size)) 3056 break; 3057 } 3058 3059 if ((iflib_min_tx_latency || iflib_txq_min_occupancy(txq)) && txq->ift_db_pending) 3060 iflib_txd_db_check(ctx, txq, TRUE); 3061 else if ((txq->ift_db_pending || TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2) && 3062 (callout_pending(&txq->ift_db_check) == 0)) { 3063 txq->ift_db_pending_queued = txq->ift_db_pending; 3064 callout_reset_on(&txq->ift_db_check, 1, iflib_txd_deferred_db_check, 3065 txq, txq->ift_db_check.c_cpu); 3066 } 3067 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3068 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3069 if (mcast_sent) 3070 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3071 #ifdef INVARIANTS 3072 if (iflib_verbose_debug) 3073 printf("consumed=%d\n", consumed); 3074 #endif 3075 return (consumed); 3076 } 3077 3078 static uint32_t 3079 iflib_txq_drain_always(struct ifmp_ring *r) 3080 { 3081 return (1); 3082 } 3083 3084 static uint32_t 3085 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3086 { 3087 int i, avail; 3088 struct mbuf **mp; 3089 iflib_txq_t txq; 3090 3091 txq = r->cookie; 3092 3093 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3094 CALLOUT_LOCK(txq); 3095 callout_stop(&txq->ift_timer); 3096 callout_stop(&txq->ift_db_check); 3097 CALLOUT_UNLOCK(txq); 3098 3099 avail = IDXDIFF(pidx, cidx, r->size); 3100 for (i = 0; i < avail; i++) { 3101 mp = _ring_peek_one(r, cidx, i); 3102 m_freem(*mp); 3103 } 3104 MPASS(ifmp_ring_is_stalled(r) == 0); 3105 return (avail); 3106 } 3107 3108 static void 3109 iflib_ifmp_purge(iflib_txq_t txq) 3110 { 3111 struct ifmp_ring *r; 3112 3113 r = txq->ift_br[0]; 3114 r->drain = iflib_txq_drain_free; 3115 r->can_drain = iflib_txq_drain_always; 3116 3117 ifmp_ring_check_drainage(r, r->size); 3118 3119 r->drain = iflib_txq_drain; 3120 r->can_drain = iflib_txq_can_drain; 3121 } 3122 3123 static void 3124 _task_fn_tx(void *context) 3125 { 3126 iflib_txq_t txq = context; 3127 if_ctx_t ctx = txq->ift_ctx; 3128 3129 #ifdef IFLIB_DIAGNOSTICS 3130 txq->ift_cpu_exec_count[curcpu]++; 3131 #endif 3132 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3133 return; 3134 ifmp_ring_check_drainage(txq->ift_br[0], TX_BATCH_SIZE); 3135 } 3136 3137 static void 3138 _task_fn_rx(void *context) 3139 { 3140 iflib_rxq_t rxq = context; 3141 if_ctx_t ctx = rxq->ifr_ctx; 3142 bool more; 3143 int rc; 3144 3145 #ifdef IFLIB_DIAGNOSTICS 3146 rxq->ifr_cpu_exec_count[curcpu]++; 3147 #endif 3148 DBG_COUNTER_INC(task_fn_rxs); 3149 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3150 return; 3151 3152 if ((more = iflib_rxeof(rxq, 16 /* XXX */)) == false) { 3153 if (ctx->ifc_flags & IFC_LEGACY) 3154 IFDI_INTR_ENABLE(ctx); 3155 else { 3156 DBG_COUNTER_INC(rx_intr_enables); 3157 rc = IFDI_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3158 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3159 } 3160 } 3161 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3162 return; 3163 if (more) 3164 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3165 } 3166 3167 static void 3168 _task_fn_admin(void *context) 3169 { 3170 if_ctx_t ctx = context; 3171 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3172 iflib_txq_t txq; 3173 int i; 3174 3175 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3176 return; 3177 3178 CTX_LOCK(ctx); 3179 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3180 CALLOUT_LOCK(txq); 3181 callout_stop(&txq->ift_timer); 3182 CALLOUT_UNLOCK(txq); 3183 } 3184 IFDI_UPDATE_ADMIN_STATUS(ctx); 3185 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3186 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 3187 IFDI_LINK_INTR_ENABLE(ctx); 3188 CTX_UNLOCK(ctx); 3189 3190 if (LINK_ACTIVE(ctx) == 0) 3191 return; 3192 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3193 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3194 } 3195 3196 3197 static void 3198 _task_fn_iov(void *context) 3199 { 3200 if_ctx_t ctx = context; 3201 3202 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3203 return; 3204 3205 CTX_LOCK(ctx); 3206 IFDI_VFLR_HANDLE(ctx); 3207 CTX_UNLOCK(ctx); 3208 } 3209 3210 static int 3211 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3212 { 3213 int err; 3214 if_int_delay_info_t info; 3215 if_ctx_t ctx; 3216 3217 info = (if_int_delay_info_t)arg1; 3218 ctx = info->iidi_ctx; 3219 info->iidi_req = req; 3220 info->iidi_oidp = oidp; 3221 CTX_LOCK(ctx); 3222 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3223 CTX_UNLOCK(ctx); 3224 return (err); 3225 } 3226 3227 /********************************************************************* 3228 * 3229 * IFNET FUNCTIONS 3230 * 3231 **********************************************************************/ 3232 3233 static void 3234 iflib_if_init_locked(if_ctx_t ctx) 3235 { 3236 iflib_stop(ctx); 3237 iflib_init_locked(ctx); 3238 } 3239 3240 3241 static void 3242 iflib_if_init(void *arg) 3243 { 3244 if_ctx_t ctx = arg; 3245 3246 CTX_LOCK(ctx); 3247 iflib_if_init_locked(ctx); 3248 CTX_UNLOCK(ctx); 3249 } 3250 3251 static int 3252 iflib_if_transmit(if_t ifp, struct mbuf *m) 3253 { 3254 if_ctx_t ctx = if_getsoftc(ifp); 3255 3256 iflib_txq_t txq; 3257 int err, qidx; 3258 3259 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3260 DBG_COUNTER_INC(tx_frees); 3261 m_freem(m); 3262 return (ENOBUFS); 3263 } 3264 3265 MPASS(m->m_nextpkt == NULL); 3266 qidx = 0; 3267 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3268 qidx = QIDX(ctx, m); 3269 /* 3270 * XXX calculate buf_ring based on flowid (divvy up bits?) 3271 */ 3272 txq = &ctx->ifc_txqs[qidx]; 3273 3274 #ifdef DRIVER_BACKPRESSURE 3275 if (txq->ift_closed) { 3276 while (m != NULL) { 3277 next = m->m_nextpkt; 3278 m->m_nextpkt = NULL; 3279 m_freem(m); 3280 m = next; 3281 } 3282 return (ENOBUFS); 3283 } 3284 #endif 3285 #ifdef notyet 3286 qidx = count = 0; 3287 mp = marr; 3288 next = m; 3289 do { 3290 count++; 3291 next = next->m_nextpkt; 3292 } while (next != NULL); 3293 3294 if (count > nitems(marr)) 3295 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3296 /* XXX check nextpkt */ 3297 m_freem(m); 3298 /* XXX simplify for now */ 3299 DBG_COUNTER_INC(tx_frees); 3300 return (ENOBUFS); 3301 } 3302 for (next = m, i = 0; next != NULL; i++) { 3303 mp[i] = next; 3304 next = next->m_nextpkt; 3305 mp[i]->m_nextpkt = NULL; 3306 } 3307 #endif 3308 DBG_COUNTER_INC(tx_seen); 3309 err = ifmp_ring_enqueue(txq->ift_br[0], (void **)&m, 1, TX_BATCH_SIZE); 3310 3311 if (err) { 3312 GROUPTASK_ENQUEUE(&txq->ift_task); 3313 /* support forthcoming later */ 3314 #ifdef DRIVER_BACKPRESSURE 3315 txq->ift_closed = TRUE; 3316 #endif 3317 ifmp_ring_check_drainage(txq->ift_br[0], TX_BATCH_SIZE); 3318 m_freem(m); 3319 } else if (TXQ_AVAIL(txq) < (txq->ift_size >> 1)) { 3320 GROUPTASK_ENQUEUE(&txq->ift_task); 3321 } 3322 3323 return (err); 3324 } 3325 3326 static void 3327 iflib_if_qflush(if_t ifp) 3328 { 3329 if_ctx_t ctx = if_getsoftc(ifp); 3330 iflib_txq_t txq = ctx->ifc_txqs; 3331 int i; 3332 3333 CTX_LOCK(ctx); 3334 ctx->ifc_flags |= IFC_QFLUSH; 3335 CTX_UNLOCK(ctx); 3336 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3337 while (!(ifmp_ring_is_idle(txq->ift_br[0]) || ifmp_ring_is_stalled(txq->ift_br[0]))) 3338 iflib_txq_check_drain(txq, 0); 3339 CTX_LOCK(ctx); 3340 ctx->ifc_flags &= ~IFC_QFLUSH; 3341 CTX_UNLOCK(ctx); 3342 3343 if_qflush(ifp); 3344 } 3345 3346 3347 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3348 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | \ 3349 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 3350 3351 static int 3352 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 3353 { 3354 if_ctx_t ctx = if_getsoftc(ifp); 3355 struct ifreq *ifr = (struct ifreq *)data; 3356 #if defined(INET) || defined(INET6) 3357 struct ifaddr *ifa = (struct ifaddr *)data; 3358 #endif 3359 bool avoid_reset = FALSE; 3360 int err = 0, reinit = 0, bits; 3361 3362 switch (command) { 3363 case SIOCSIFADDR: 3364 #ifdef INET 3365 if (ifa->ifa_addr->sa_family == AF_INET) 3366 avoid_reset = TRUE; 3367 #endif 3368 #ifdef INET6 3369 if (ifa->ifa_addr->sa_family == AF_INET6) 3370 avoid_reset = TRUE; 3371 #endif 3372 /* 3373 ** Calling init results in link renegotiation, 3374 ** so we avoid doing it when possible. 3375 */ 3376 if (avoid_reset) { 3377 if_setflagbits(ifp, IFF_UP,0); 3378 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING)) 3379 reinit = 1; 3380 #ifdef INET 3381 if (!(if_getflags(ifp) & IFF_NOARP)) 3382 arp_ifinit(ifp, ifa); 3383 #endif 3384 } else 3385 err = ether_ioctl(ifp, command, data); 3386 break; 3387 case SIOCSIFMTU: 3388 CTX_LOCK(ctx); 3389 if (ifr->ifr_mtu == if_getmtu(ifp)) { 3390 CTX_UNLOCK(ctx); 3391 break; 3392 } 3393 bits = if_getdrvflags(ifp); 3394 /* stop the driver and free any clusters before proceeding */ 3395 iflib_stop(ctx); 3396 3397 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 3398 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 3399 ctx->ifc_flags |= IFC_MULTISEG; 3400 else 3401 ctx->ifc_flags &= ~IFC_MULTISEG; 3402 err = if_setmtu(ifp, ifr->ifr_mtu); 3403 } 3404 iflib_init_locked(ctx); 3405 if_setdrvflags(ifp, bits); 3406 CTX_UNLOCK(ctx); 3407 break; 3408 case SIOCSIFFLAGS: 3409 CTX_LOCK(ctx); 3410 if (if_getflags(ifp) & IFF_UP) { 3411 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3412 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 3413 (IFF_PROMISC | IFF_ALLMULTI)) { 3414 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 3415 } 3416 } else 3417 reinit = 1; 3418 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3419 iflib_stop(ctx); 3420 } 3421 ctx->ifc_if_flags = if_getflags(ifp); 3422 CTX_UNLOCK(ctx); 3423 break; 3424 case SIOCADDMULTI: 3425 case SIOCDELMULTI: 3426 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3427 CTX_LOCK(ctx); 3428 IFDI_INTR_DISABLE(ctx); 3429 IFDI_MULTI_SET(ctx); 3430 IFDI_INTR_ENABLE(ctx); 3431 CTX_UNLOCK(ctx); 3432 } 3433 break; 3434 case SIOCSIFMEDIA: 3435 CTX_LOCK(ctx); 3436 IFDI_MEDIA_SET(ctx); 3437 CTX_UNLOCK(ctx); 3438 /* falls thru */ 3439 case SIOCGIFMEDIA: 3440 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 3441 break; 3442 case SIOCGI2C: 3443 { 3444 struct ifi2creq i2c; 3445 3446 err = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); 3447 if (err != 0) 3448 break; 3449 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 3450 err = EINVAL; 3451 break; 3452 } 3453 if (i2c.len > sizeof(i2c.data)) { 3454 err = EINVAL; 3455 break; 3456 } 3457 3458 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 3459 err = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); 3460 break; 3461 } 3462 case SIOCSIFCAP: 3463 { 3464 int mask, setmask; 3465 3466 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3467 setmask = 0; 3468 #ifdef TCP_OFFLOAD 3469 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 3470 #endif 3471 setmask |= (mask & IFCAP_FLAGS); 3472 3473 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 3474 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 3475 if ((mask & IFCAP_WOL) && 3476 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 3477 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 3478 if_vlancap(ifp); 3479 /* 3480 * want to ensure that traffic has stopped before we change any of the flags 3481 */ 3482 if (setmask) { 3483 CTX_LOCK(ctx); 3484 bits = if_getdrvflags(ifp); 3485 if (bits & IFF_DRV_RUNNING) 3486 iflib_stop(ctx); 3487 if_togglecapenable(ifp, setmask); 3488 if (bits & IFF_DRV_RUNNING) 3489 iflib_init_locked(ctx); 3490 if_setdrvflags(ifp, bits); 3491 CTX_UNLOCK(ctx); 3492 } 3493 break; 3494 } 3495 case SIOCGPRIVATE_0: 3496 case SIOCSDRVSPEC: 3497 case SIOCGDRVSPEC: 3498 CTX_LOCK(ctx); 3499 err = IFDI_PRIV_IOCTL(ctx, command, data); 3500 CTX_UNLOCK(ctx); 3501 break; 3502 default: 3503 err = ether_ioctl(ifp, command, data); 3504 break; 3505 } 3506 if (reinit) 3507 iflib_if_init(ctx); 3508 return (err); 3509 } 3510 3511 static uint64_t 3512 iflib_if_get_counter(if_t ifp, ift_counter cnt) 3513 { 3514 if_ctx_t ctx = if_getsoftc(ifp); 3515 3516 return (IFDI_GET_COUNTER(ctx, cnt)); 3517 } 3518 3519 /********************************************************************* 3520 * 3521 * OTHER FUNCTIONS EXPORTED TO THE STACK 3522 * 3523 **********************************************************************/ 3524 3525 static void 3526 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 3527 { 3528 if_ctx_t ctx = if_getsoftc(ifp); 3529 3530 if ((void *)ctx != arg) 3531 return; 3532 3533 if ((vtag == 0) || (vtag > 4095)) 3534 return; 3535 3536 CTX_LOCK(ctx); 3537 IFDI_VLAN_REGISTER(ctx, vtag); 3538 /* Re-init to load the changes */ 3539 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 3540 iflib_init_locked(ctx); 3541 CTX_UNLOCK(ctx); 3542 } 3543 3544 static void 3545 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 3546 { 3547 if_ctx_t ctx = if_getsoftc(ifp); 3548 3549 if ((void *)ctx != arg) 3550 return; 3551 3552 if ((vtag == 0) || (vtag > 4095)) 3553 return; 3554 3555 CTX_LOCK(ctx); 3556 IFDI_VLAN_UNREGISTER(ctx, vtag); 3557 /* Re-init to load the changes */ 3558 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 3559 iflib_init_locked(ctx); 3560 CTX_UNLOCK(ctx); 3561 } 3562 3563 static void 3564 iflib_led_func(void *arg, int onoff) 3565 { 3566 if_ctx_t ctx = arg; 3567 3568 CTX_LOCK(ctx); 3569 IFDI_LED_FUNC(ctx, onoff); 3570 CTX_UNLOCK(ctx); 3571 } 3572 3573 /********************************************************************* 3574 * 3575 * BUS FUNCTION DEFINITIONS 3576 * 3577 **********************************************************************/ 3578 3579 int 3580 iflib_device_probe(device_t dev) 3581 { 3582 pci_vendor_info_t *ent; 3583 3584 uint16_t pci_vendor_id, pci_device_id; 3585 uint16_t pci_subvendor_id, pci_subdevice_id; 3586 uint16_t pci_rev_id; 3587 if_shared_ctx_t sctx; 3588 3589 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 3590 return (ENOTSUP); 3591 3592 pci_vendor_id = pci_get_vendor(dev); 3593 pci_device_id = pci_get_device(dev); 3594 pci_subvendor_id = pci_get_subvendor(dev); 3595 pci_subdevice_id = pci_get_subdevice(dev); 3596 pci_rev_id = pci_get_revid(dev); 3597 if (sctx->isc_parse_devinfo != NULL) 3598 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 3599 3600 ent = sctx->isc_vendor_info; 3601 while (ent->pvi_vendor_id != 0) { 3602 if (pci_vendor_id != ent->pvi_vendor_id) { 3603 ent++; 3604 continue; 3605 } 3606 if ((pci_device_id == ent->pvi_device_id) && 3607 ((pci_subvendor_id == ent->pvi_subvendor_id) || 3608 (ent->pvi_subvendor_id == 0)) && 3609 ((pci_subdevice_id == ent->pvi_subdevice_id) || 3610 (ent->pvi_subdevice_id == 0)) && 3611 ((pci_rev_id == ent->pvi_rev_id) || 3612 (ent->pvi_rev_id == 0))) { 3613 3614 device_set_desc_copy(dev, ent->pvi_name); 3615 /* this needs to be changed to zero if the bus probing code 3616 * ever stops re-probing on best match because the sctx 3617 * may have its values over written by register calls 3618 * in subsequent probes 3619 */ 3620 return (BUS_PROBE_DEFAULT); 3621 } 3622 ent++; 3623 } 3624 return (ENXIO); 3625 } 3626 3627 int 3628 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 3629 { 3630 int err, rid, msix, msix_bar; 3631 if_ctx_t ctx; 3632 if_t ifp; 3633 if_softc_ctx_t scctx; 3634 int i; 3635 uint16_t main_txq; 3636 uint16_t main_rxq; 3637 3638 3639 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 3640 3641 if (sc == NULL) { 3642 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 3643 device_set_softc(dev, ctx); 3644 ctx->ifc_flags |= IFC_SC_ALLOCATED; 3645 } 3646 3647 ctx->ifc_sctx = sctx; 3648 ctx->ifc_dev = dev; 3649 ctx->ifc_softc = sc; 3650 3651 if ((err = iflib_register(ctx)) != 0) { 3652 device_printf(dev, "iflib_register failed %d\n", err); 3653 return (err); 3654 } 3655 iflib_add_device_sysctl_pre(ctx); 3656 3657 scctx = &ctx->ifc_softc_ctx; 3658 ifp = ctx->ifc_ifp; 3659 3660 /* 3661 * XXX sanity check that ntxd & nrxd are a power of 2 3662 */ 3663 if (ctx->ifc_sysctl_ntxqs != 0) 3664 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 3665 if (ctx->ifc_sysctl_nrxqs != 0) 3666 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 3667 3668 for (i = 0; i < sctx->isc_ntxqs; i++) { 3669 if (ctx->ifc_sysctl_ntxds[i] != 0) 3670 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 3671 else 3672 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 3673 } 3674 3675 for (i = 0; i < sctx->isc_nrxqs; i++) { 3676 if (ctx->ifc_sysctl_nrxds[i] != 0) 3677 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 3678 else 3679 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 3680 } 3681 3682 for (i = 0; i < sctx->isc_nrxqs; i++) { 3683 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 3684 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 3685 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 3686 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 3687 } 3688 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 3689 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 3690 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 3691 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 3692 } 3693 } 3694 3695 for (i = 0; i < sctx->isc_ntxqs; i++) { 3696 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 3697 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 3698 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 3699 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 3700 } 3701 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 3702 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 3703 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 3704 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 3705 } 3706 } 3707 3708 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 3709 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 3710 return (err); 3711 } 3712 _iflib_pre_assert(scctx); 3713 ctx->ifc_txrx = *scctx->isc_txrx; 3714 3715 #ifdef INVARIANTS 3716 MPASS(scctx->isc_capenable); 3717 if (scctx->isc_capenable & IFCAP_TXCSUM) 3718 MPASS(scctx->isc_tx_csum_flags); 3719 #endif 3720 3721 if_setcapabilities(ifp, scctx->isc_capenable); 3722 if_setcapenable(ifp, scctx->isc_capenable); 3723 3724 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 3725 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 3726 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 3727 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 3728 3729 #ifdef ACPI_DMAR 3730 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 3731 ctx->ifc_flags |= IFC_DMAR; 3732 #endif 3733 3734 msix_bar = scctx->isc_msix_bar; 3735 3736 if(sctx->isc_flags & IFLIB_HAS_TXCQ) 3737 main_txq = 1; 3738 else 3739 main_txq = 0; 3740 3741 if(sctx->isc_flags & IFLIB_HAS_RXCQ) 3742 main_rxq = 1; 3743 else 3744 main_rxq = 0; 3745 3746 /* XXX change for per-queue sizes */ 3747 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 3748 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 3749 for (i = 0; i < sctx->isc_nrxqs; i++) { 3750 if (!powerof2(scctx->isc_nrxd[i])) { 3751 /* round down instead? */ 3752 device_printf(dev, "# rx descriptors must be a power of 2\n"); 3753 err = EINVAL; 3754 goto fail; 3755 } 3756 } 3757 for (i = 0; i < sctx->isc_ntxqs; i++) { 3758 if (!powerof2(scctx->isc_ntxd[i])) { 3759 device_printf(dev, 3760 "# tx descriptors must be a power of 2"); 3761 err = EINVAL; 3762 goto fail; 3763 } 3764 } 3765 3766 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 3767 MAX_SINGLE_PACKET_FRACTION) 3768 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 3769 MAX_SINGLE_PACKET_FRACTION); 3770 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 3771 MAX_SINGLE_PACKET_FRACTION) 3772 scctx->isc_tx_tso_segments_max = max(1, 3773 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 3774 3775 /* 3776 * Protect the stack against modern hardware 3777 */ 3778 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 3779 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 3780 3781 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 3782 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 3783 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 3784 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 3785 if (scctx->isc_rss_table_size == 0) 3786 scctx->isc_rss_table_size = 64; 3787 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 3788 3789 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 3790 /* XXX format name */ 3791 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 3792 /* 3793 ** Now setup MSI or MSI/X, should 3794 ** return us the number of supported 3795 ** vectors. (Will be 1 for MSI) 3796 */ 3797 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 3798 msix = scctx->isc_vectors; 3799 } else if (scctx->isc_msix_bar != 0) 3800 /* 3801 * The simple fact that isc_msix_bar is not 0 does not mean we 3802 * we have a good value there that is known to work. 3803 */ 3804 msix = iflib_msix_init(ctx); 3805 else { 3806 scctx->isc_vectors = 1; 3807 scctx->isc_ntxqsets = 1; 3808 scctx->isc_nrxqsets = 1; 3809 scctx->isc_intr = IFLIB_INTR_LEGACY; 3810 msix = 0; 3811 } 3812 /* Get memory for the station queues */ 3813 if ((err = iflib_queues_alloc(ctx))) { 3814 device_printf(dev, "Unable to allocate queue memory\n"); 3815 goto fail; 3816 } 3817 3818 if ((err = iflib_qset_structures_setup(ctx))) { 3819 device_printf(dev, "qset structure setup failed %d\n", err); 3820 goto fail_queues; 3821 } 3822 3823 /* 3824 * Group taskqueues aren't properly set up until SMP is started, 3825 * so we disable interrupts until we can handle them post 3826 * SI_SUB_SMP. 3827 * 3828 * XXX: disabling interrupts doesn't actually work, at least for 3829 * the non-MSI case. When they occur before SI_SUB_SMP completes, 3830 * we do null handling and depend on this not causing too large an 3831 * interrupt storm. 3832 */ 3833 IFDI_INTR_DISABLE(ctx); 3834 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 3835 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 3836 goto fail_intr_free; 3837 } 3838 if (msix <= 1) { 3839 rid = 0; 3840 if (scctx->isc_intr == IFLIB_INTR_MSI) { 3841 MPASS(msix == 1); 3842 rid = 1; 3843 } 3844 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 3845 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 3846 goto fail_intr_free; 3847 } 3848 } 3849 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 3850 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 3851 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 3852 goto fail_detach; 3853 } 3854 if ((err = iflib_netmap_attach(ctx))) { 3855 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 3856 goto fail_detach; 3857 } 3858 *ctxp = ctx; 3859 3860 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 3861 iflib_add_device_sysctl_post(ctx); 3862 ctx->ifc_flags |= IFC_INIT_DONE; 3863 return (0); 3864 fail_detach: 3865 ether_ifdetach(ctx->ifc_ifp); 3866 fail_intr_free: 3867 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 3868 pci_release_msi(ctx->ifc_dev); 3869 fail_queues: 3870 /* XXX free queues */ 3871 fail: 3872 IFDI_DETACH(ctx); 3873 return (err); 3874 } 3875 3876 int 3877 iflib_device_attach(device_t dev) 3878 { 3879 if_ctx_t ctx; 3880 if_shared_ctx_t sctx; 3881 3882 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 3883 return (ENOTSUP); 3884 3885 pci_enable_busmaster(dev); 3886 3887 return (iflib_device_register(dev, NULL, sctx, &ctx)); 3888 } 3889 3890 int 3891 iflib_device_deregister(if_ctx_t ctx) 3892 { 3893 if_t ifp = ctx->ifc_ifp; 3894 iflib_txq_t txq; 3895 iflib_rxq_t rxq; 3896 device_t dev = ctx->ifc_dev; 3897 int i; 3898 struct taskqgroup *tqg; 3899 3900 /* Make sure VLANS are not using driver */ 3901 if (if_vlantrunkinuse(ifp)) { 3902 device_printf(dev,"Vlan in use, detach first\n"); 3903 return (EBUSY); 3904 } 3905 3906 CTX_LOCK(ctx); 3907 ctx->ifc_in_detach = 1; 3908 iflib_stop(ctx); 3909 CTX_UNLOCK(ctx); 3910 3911 /* Unregister VLAN events */ 3912 if (ctx->ifc_vlan_attach_event != NULL) 3913 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 3914 if (ctx->ifc_vlan_detach_event != NULL) 3915 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 3916 3917 iflib_netmap_detach(ifp); 3918 ether_ifdetach(ifp); 3919 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 3920 CTX_LOCK_DESTROY(ctx); 3921 if (ctx->ifc_led_dev != NULL) 3922 led_destroy(ctx->ifc_led_dev); 3923 /* XXX drain any dependent tasks */ 3924 tqg = qgroup_softirq; 3925 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 3926 callout_drain(&txq->ift_timer); 3927 callout_drain(&txq->ift_db_check); 3928 if (txq->ift_task.gt_uniq != NULL) 3929 taskqgroup_detach(tqg, &txq->ift_task); 3930 } 3931 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 3932 if (rxq->ifr_task.gt_uniq != NULL) 3933 taskqgroup_detach(tqg, &rxq->ifr_task); 3934 } 3935 tqg = qgroup_if_config_tqg; 3936 if (ctx->ifc_admin_task.gt_uniq != NULL) 3937 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 3938 if (ctx->ifc_vflr_task.gt_uniq != NULL) 3939 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 3940 3941 IFDI_DETACH(ctx); 3942 device_set_softc(ctx->ifc_dev, NULL); 3943 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 3944 pci_release_msi(dev); 3945 } 3946 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 3947 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 3948 } 3949 if (ctx->ifc_msix_mem != NULL) { 3950 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 3951 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 3952 ctx->ifc_msix_mem = NULL; 3953 } 3954 3955 bus_generic_detach(dev); 3956 if_free(ifp); 3957 3958 iflib_tx_structures_free(ctx); 3959 iflib_rx_structures_free(ctx); 3960 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 3961 free(ctx->ifc_softc, M_IFLIB); 3962 free(ctx, M_IFLIB); 3963 return (0); 3964 } 3965 3966 3967 int 3968 iflib_device_detach(device_t dev) 3969 { 3970 if_ctx_t ctx = device_get_softc(dev); 3971 3972 return (iflib_device_deregister(ctx)); 3973 } 3974 3975 int 3976 iflib_device_suspend(device_t dev) 3977 { 3978 if_ctx_t ctx = device_get_softc(dev); 3979 3980 CTX_LOCK(ctx); 3981 IFDI_SUSPEND(ctx); 3982 CTX_UNLOCK(ctx); 3983 3984 return bus_generic_suspend(dev); 3985 } 3986 int 3987 iflib_device_shutdown(device_t dev) 3988 { 3989 if_ctx_t ctx = device_get_softc(dev); 3990 3991 CTX_LOCK(ctx); 3992 IFDI_SHUTDOWN(ctx); 3993 CTX_UNLOCK(ctx); 3994 3995 return bus_generic_suspend(dev); 3996 } 3997 3998 3999 int 4000 iflib_device_resume(device_t dev) 4001 { 4002 if_ctx_t ctx = device_get_softc(dev); 4003 iflib_txq_t txq = ctx->ifc_txqs; 4004 4005 CTX_LOCK(ctx); 4006 IFDI_RESUME(ctx); 4007 iflib_init_locked(ctx); 4008 CTX_UNLOCK(ctx); 4009 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4010 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4011 4012 return (bus_generic_resume(dev)); 4013 } 4014 4015 int 4016 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4017 { 4018 int error; 4019 if_ctx_t ctx = device_get_softc(dev); 4020 4021 CTX_LOCK(ctx); 4022 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4023 CTX_UNLOCK(ctx); 4024 4025 return (error); 4026 } 4027 4028 void 4029 iflib_device_iov_uninit(device_t dev) 4030 { 4031 if_ctx_t ctx = device_get_softc(dev); 4032 4033 CTX_LOCK(ctx); 4034 IFDI_IOV_UNINIT(ctx); 4035 CTX_UNLOCK(ctx); 4036 } 4037 4038 int 4039 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 4040 { 4041 int error; 4042 if_ctx_t ctx = device_get_softc(dev); 4043 4044 CTX_LOCK(ctx); 4045 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 4046 CTX_UNLOCK(ctx); 4047 4048 return (error); 4049 } 4050 4051 /********************************************************************* 4052 * 4053 * MODULE FUNCTION DEFINITIONS 4054 * 4055 **********************************************************************/ 4056 4057 /* 4058 * - Start a fast taskqueue thread for each core 4059 * - Start a taskqueue for control operations 4060 */ 4061 static int 4062 iflib_module_init(void) 4063 { 4064 return (0); 4065 } 4066 4067 static int 4068 iflib_module_event_handler(module_t mod, int what, void *arg) 4069 { 4070 int err; 4071 4072 switch (what) { 4073 case MOD_LOAD: 4074 if ((err = iflib_module_init()) != 0) 4075 return (err); 4076 break; 4077 case MOD_UNLOAD: 4078 return (EBUSY); 4079 default: 4080 return (EOPNOTSUPP); 4081 } 4082 4083 return (0); 4084 } 4085 4086 /********************************************************************* 4087 * 4088 * PUBLIC FUNCTION DEFINITIONS 4089 * ordered as in iflib.h 4090 * 4091 **********************************************************************/ 4092 4093 4094 static void 4095 _iflib_assert(if_shared_ctx_t sctx) 4096 { 4097 MPASS(sctx->isc_tx_maxsize); 4098 MPASS(sctx->isc_tx_maxsegsize); 4099 4100 MPASS(sctx->isc_rx_maxsize); 4101 MPASS(sctx->isc_rx_nsegments); 4102 MPASS(sctx->isc_rx_maxsegsize); 4103 4104 MPASS(sctx->isc_nrxd_min[0]); 4105 MPASS(sctx->isc_nrxd_max[0]); 4106 MPASS(sctx->isc_nrxd_default[0]); 4107 MPASS(sctx->isc_ntxd_min[0]); 4108 MPASS(sctx->isc_ntxd_max[0]); 4109 MPASS(sctx->isc_ntxd_default[0]); 4110 } 4111 4112 static void 4113 _iflib_pre_assert(if_softc_ctx_t scctx) 4114 { 4115 4116 MPASS(scctx->isc_txrx->ift_txd_encap); 4117 MPASS(scctx->isc_txrx->ift_txd_flush); 4118 MPASS(scctx->isc_txrx->ift_txd_credits_update); 4119 MPASS(scctx->isc_txrx->ift_rxd_available); 4120 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 4121 MPASS(scctx->isc_txrx->ift_rxd_refill); 4122 MPASS(scctx->isc_txrx->ift_rxd_flush); 4123 } 4124 4125 static int 4126 iflib_register(if_ctx_t ctx) 4127 { 4128 if_shared_ctx_t sctx = ctx->ifc_sctx; 4129 driver_t *driver = sctx->isc_driver; 4130 device_t dev = ctx->ifc_dev; 4131 if_t ifp; 4132 4133 _iflib_assert(sctx); 4134 4135 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 4136 4137 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 4138 if (ifp == NULL) { 4139 device_printf(dev, "can not allocate ifnet structure\n"); 4140 return (ENOMEM); 4141 } 4142 4143 /* 4144 * Initialize our context's device specific methods 4145 */ 4146 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 4147 kobj_class_compile((kobj_class_t) driver); 4148 driver->refs++; 4149 4150 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 4151 if_setsoftc(ifp, ctx); 4152 if_setdev(ifp, dev); 4153 if_setinitfn(ifp, iflib_if_init); 4154 if_setioctlfn(ifp, iflib_if_ioctl); 4155 if_settransmitfn(ifp, iflib_if_transmit); 4156 if_setqflushfn(ifp, iflib_if_qflush); 4157 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 4158 4159 ctx->ifc_vlan_attach_event = 4160 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 4161 EVENTHANDLER_PRI_FIRST); 4162 ctx->ifc_vlan_detach_event = 4163 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 4164 EVENTHANDLER_PRI_FIRST); 4165 4166 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 4167 iflib_media_change, iflib_media_status); 4168 4169 return (0); 4170 } 4171 4172 4173 static int 4174 iflib_queues_alloc(if_ctx_t ctx) 4175 { 4176 if_shared_ctx_t sctx = ctx->ifc_sctx; 4177 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4178 device_t dev = ctx->ifc_dev; 4179 int nrxqsets = scctx->isc_nrxqsets; 4180 int ntxqsets = scctx->isc_ntxqsets; 4181 iflib_txq_t txq; 4182 iflib_rxq_t rxq; 4183 iflib_fl_t fl = NULL; 4184 int i, j, cpu, err, txconf, rxconf; 4185 iflib_dma_info_t ifdip; 4186 uint32_t *rxqsizes = scctx->isc_rxqsizes; 4187 uint32_t *txqsizes = scctx->isc_txqsizes; 4188 uint8_t nrxqs = sctx->isc_nrxqs; 4189 uint8_t ntxqs = sctx->isc_ntxqs; 4190 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 4191 caddr_t *vaddrs; 4192 uint64_t *paddrs; 4193 struct ifmp_ring **brscp; 4194 int nbuf_rings = 1; /* XXX determine dynamically */ 4195 4196 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 4197 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 4198 4199 brscp = NULL; 4200 txq = NULL; 4201 rxq = NULL; 4202 4203 /* Allocate the TX ring struct memory */ 4204 if (!(txq = 4205 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 4206 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4207 device_printf(dev, "Unable to allocate TX ring memory\n"); 4208 err = ENOMEM; 4209 goto fail; 4210 } 4211 4212 /* Now allocate the RX */ 4213 if (!(rxq = 4214 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 4215 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4216 device_printf(dev, "Unable to allocate RX ring memory\n"); 4217 err = ENOMEM; 4218 goto rx_fail; 4219 } 4220 if (!(brscp = malloc(sizeof(void *) * nbuf_rings * nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4221 device_printf(dev, "Unable to buf_ring_sc * memory\n"); 4222 err = ENOMEM; 4223 goto rx_fail; 4224 } 4225 4226 ctx->ifc_txqs = txq; 4227 ctx->ifc_rxqs = rxq; 4228 4229 /* 4230 * XXX handle allocation failure 4231 */ 4232 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 4233 /* Set up some basics */ 4234 4235 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4236 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4237 err = ENOMEM; 4238 goto err_tx_desc; 4239 } 4240 txq->ift_ifdi = ifdip; 4241 for (j = 0; j < ntxqs; j++, ifdip++) { 4242 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4243 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4244 err = ENOMEM; 4245 goto err_tx_desc; 4246 } 4247 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 4248 } 4249 txq->ift_ctx = ctx; 4250 txq->ift_id = i; 4251 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 4252 txq->ift_br_offset = 1; 4253 } else { 4254 txq->ift_br_offset = 0; 4255 } 4256 /* XXX fix this */ 4257 txq->ift_timer.c_cpu = cpu; 4258 txq->ift_db_check.c_cpu = cpu; 4259 txq->ift_nbr = nbuf_rings; 4260 4261 if (iflib_txsd_alloc(txq)) { 4262 device_printf(dev, "Critical Failure setting up TX buffers\n"); 4263 err = ENOMEM; 4264 goto err_tx_desc; 4265 } 4266 4267 /* Initialize the TX lock */ 4268 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 4269 device_get_nameunit(dev), txq->ift_id); 4270 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 4271 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 4272 callout_init_mtx(&txq->ift_db_check, &txq->ift_mtx, 0); 4273 4274 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 4275 device_get_nameunit(dev), txq->ift_id); 4276 TXDB_LOCK_INIT(txq); 4277 4278 txq->ift_br = brscp + i*nbuf_rings; 4279 for (j = 0; j < nbuf_rings; j++) { 4280 err = ifmp_ring_alloc(&txq->ift_br[j], 2048, txq, iflib_txq_drain, 4281 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 4282 if (err) { 4283 /* XXX free any allocated rings */ 4284 device_printf(dev, "Unable to allocate buf_ring\n"); 4285 goto err_tx_desc; 4286 } 4287 } 4288 } 4289 4290 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 4291 /* Set up some basics */ 4292 4293 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4294 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4295 err = ENOMEM; 4296 goto err_tx_desc; 4297 } 4298 4299 rxq->ifr_ifdi = ifdip; 4300 for (j = 0; j < nrxqs; j++, ifdip++) { 4301 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4302 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4303 err = ENOMEM; 4304 goto err_tx_desc; 4305 } 4306 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 4307 } 4308 rxq->ifr_ctx = ctx; 4309 rxq->ifr_id = i; 4310 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 4311 rxq->ifr_fl_offset = 1; 4312 } else { 4313 rxq->ifr_fl_offset = 0; 4314 } 4315 rxq->ifr_nfl = nfree_lists; 4316 if (!(fl = 4317 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 4318 device_printf(dev, "Unable to allocate free list memory\n"); 4319 err = ENOMEM; 4320 goto err_tx_desc; 4321 } 4322 rxq->ifr_fl = fl; 4323 for (j = 0; j < nfree_lists; j++) { 4324 rxq->ifr_fl[j].ifl_rxq = rxq; 4325 rxq->ifr_fl[j].ifl_id = j; 4326 rxq->ifr_fl[j].ifl_ifdi = 4327 &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 4328 } 4329 /* Allocate receive buffers for the ring*/ 4330 if (iflib_rxsd_alloc(rxq)) { 4331 device_printf(dev, 4332 "Critical Failure setting up receive buffers\n"); 4333 err = ENOMEM; 4334 goto err_rx_desc; 4335 } 4336 } 4337 4338 /* TXQs */ 4339 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4340 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4341 for (i = 0; i < ntxqsets; i++) { 4342 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 4343 4344 for (j = 0; j < ntxqs; j++, di++) { 4345 vaddrs[i*ntxqs + j] = di->idi_vaddr; 4346 paddrs[i*ntxqs + j] = di->idi_paddr; 4347 } 4348 } 4349 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 4350 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4351 iflib_tx_structures_free(ctx); 4352 free(vaddrs, M_IFLIB); 4353 free(paddrs, M_IFLIB); 4354 goto err_rx_desc; 4355 } 4356 free(vaddrs, M_IFLIB); 4357 free(paddrs, M_IFLIB); 4358 4359 /* RXQs */ 4360 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4361 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4362 for (i = 0; i < nrxqsets; i++) { 4363 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 4364 4365 for (j = 0; j < nrxqs; j++, di++) { 4366 vaddrs[i*nrxqs + j] = di->idi_vaddr; 4367 paddrs[i*nrxqs + j] = di->idi_paddr; 4368 } 4369 } 4370 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 4371 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4372 iflib_tx_structures_free(ctx); 4373 free(vaddrs, M_IFLIB); 4374 free(paddrs, M_IFLIB); 4375 goto err_rx_desc; 4376 } 4377 free(vaddrs, M_IFLIB); 4378 free(paddrs, M_IFLIB); 4379 4380 return (0); 4381 4382 /* XXX handle allocation failure changes */ 4383 err_rx_desc: 4384 err_tx_desc: 4385 if (ctx->ifc_rxqs != NULL) 4386 free(ctx->ifc_rxqs, M_IFLIB); 4387 ctx->ifc_rxqs = NULL; 4388 if (ctx->ifc_txqs != NULL) 4389 free(ctx->ifc_txqs, M_IFLIB); 4390 ctx->ifc_txqs = NULL; 4391 rx_fail: 4392 if (brscp != NULL) 4393 free(brscp, M_IFLIB); 4394 if (rxq != NULL) 4395 free(rxq, M_IFLIB); 4396 if (txq != NULL) 4397 free(txq, M_IFLIB); 4398 fail: 4399 return (err); 4400 } 4401 4402 static int 4403 iflib_tx_structures_setup(if_ctx_t ctx) 4404 { 4405 iflib_txq_t txq = ctx->ifc_txqs; 4406 int i; 4407 4408 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4409 iflib_txq_setup(txq); 4410 4411 return (0); 4412 } 4413 4414 static void 4415 iflib_tx_structures_free(if_ctx_t ctx) 4416 { 4417 iflib_txq_t txq = ctx->ifc_txqs; 4418 int i, j; 4419 4420 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 4421 iflib_txq_destroy(txq); 4422 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 4423 iflib_dma_free(&txq->ift_ifdi[j]); 4424 } 4425 free(ctx->ifc_txqs, M_IFLIB); 4426 ctx->ifc_txqs = NULL; 4427 IFDI_QUEUES_FREE(ctx); 4428 } 4429 4430 /********************************************************************* 4431 * 4432 * Initialize all receive rings. 4433 * 4434 **********************************************************************/ 4435 static int 4436 iflib_rx_structures_setup(if_ctx_t ctx) 4437 { 4438 iflib_rxq_t rxq = ctx->ifc_rxqs; 4439 int q; 4440 #if defined(INET6) || defined(INET) 4441 int i, err; 4442 #endif 4443 4444 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 4445 #if defined(INET6) || defined(INET) 4446 tcp_lro_free(&rxq->ifr_lc); 4447 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 4448 TCP_LRO_ENTRIES, min(1024, 4449 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 4450 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 4451 goto fail; 4452 } 4453 rxq->ifr_lro_enabled = TRUE; 4454 #endif 4455 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 4456 } 4457 return (0); 4458 #if defined(INET6) || defined(INET) 4459 fail: 4460 /* 4461 * Free RX software descriptors allocated so far, we will only handle 4462 * the rings that completed, the failing case will have 4463 * cleaned up for itself. 'q' failed, so its the terminus. 4464 */ 4465 rxq = ctx->ifc_rxqs; 4466 for (i = 0; i < q; ++i, rxq++) { 4467 iflib_rx_sds_free(rxq); 4468 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 4469 } 4470 return (err); 4471 #endif 4472 } 4473 4474 /********************************************************************* 4475 * 4476 * Free all receive rings. 4477 * 4478 **********************************************************************/ 4479 static void 4480 iflib_rx_structures_free(if_ctx_t ctx) 4481 { 4482 iflib_rxq_t rxq = ctx->ifc_rxqs; 4483 4484 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 4485 iflib_rx_sds_free(rxq); 4486 } 4487 } 4488 4489 static int 4490 iflib_qset_structures_setup(if_ctx_t ctx) 4491 { 4492 int err; 4493 4494 if ((err = iflib_tx_structures_setup(ctx)) != 0) 4495 return (err); 4496 4497 if ((err = iflib_rx_structures_setup(ctx)) != 0) { 4498 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 4499 iflib_tx_structures_free(ctx); 4500 iflib_rx_structures_free(ctx); 4501 } 4502 return (err); 4503 } 4504 4505 int 4506 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 4507 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name) 4508 { 4509 4510 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 4511 } 4512 4513 static int 4514 find_nth(if_ctx_t ctx, cpuset_t *cpus, int qid) 4515 { 4516 int i, cpuid, eqid, count; 4517 4518 CPU_COPY(&ctx->ifc_cpus, cpus); 4519 count = CPU_COUNT(&ctx->ifc_cpus); 4520 eqid = qid % count; 4521 /* clear up to the qid'th bit */ 4522 for (i = 0; i < eqid; i++) { 4523 cpuid = CPU_FFS(cpus); 4524 MPASS(cpuid != 0); 4525 CPU_CLR(cpuid-1, cpus); 4526 } 4527 cpuid = CPU_FFS(cpus); 4528 MPASS(cpuid != 0); 4529 return (cpuid-1); 4530 } 4531 4532 int 4533 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 4534 iflib_intr_type_t type, driver_filter_t *filter, 4535 void *filter_arg, int qid, char *name) 4536 { 4537 struct grouptask *gtask; 4538 struct taskqgroup *tqg; 4539 iflib_filter_info_t info; 4540 cpuset_t cpus; 4541 gtask_fn_t *fn; 4542 int tqrid, err, cpuid; 4543 void *q; 4544 4545 info = &ctx->ifc_filter_info; 4546 tqrid = rid; 4547 4548 switch (type) { 4549 /* XXX merge tx/rx for netmap? */ 4550 case IFLIB_INTR_TX: 4551 q = &ctx->ifc_txqs[qid]; 4552 info = &ctx->ifc_txqs[qid].ift_filter_info; 4553 gtask = &ctx->ifc_txqs[qid].ift_task; 4554 tqg = qgroup_softirq; 4555 fn = _task_fn_tx; 4556 GROUPTASK_INIT(gtask, 0, fn, q); 4557 break; 4558 case IFLIB_INTR_RX: 4559 q = &ctx->ifc_rxqs[qid]; 4560 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 4561 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4562 tqg = qgroup_softirq; 4563 fn = _task_fn_rx; 4564 GROUPTASK_INIT(gtask, 0, fn, q); 4565 break; 4566 case IFLIB_INTR_ADMIN: 4567 q = ctx; 4568 tqrid = -1; 4569 info = &ctx->ifc_filter_info; 4570 gtask = &ctx->ifc_admin_task; 4571 tqg = qgroup_if_config_tqg; 4572 fn = _task_fn_admin; 4573 break; 4574 default: 4575 panic("unknown net intr type"); 4576 } 4577 4578 info->ifi_filter = filter; 4579 info->ifi_filter_arg = filter_arg; 4580 info->ifi_task = gtask; 4581 info->ifi_ctx = ctx; 4582 4583 err = _iflib_irq_alloc(ctx, irq, rid, iflib_fast_intr, NULL, info, name); 4584 if (err != 0) { 4585 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 4586 return (err); 4587 } 4588 if (type == IFLIB_INTR_ADMIN) 4589 return (0); 4590 4591 if (tqrid != -1) { 4592 cpuid = find_nth(ctx, &cpus, qid); 4593 taskqgroup_attach_cpu(tqg, gtask, q, cpuid, irq->ii_rid, name); 4594 } else { 4595 taskqgroup_attach(tqg, gtask, q, tqrid, name); 4596 } 4597 4598 return (0); 4599 } 4600 4601 void 4602 iflib_softirq_alloc_generic(if_ctx_t ctx, int rid, iflib_intr_type_t type, void *arg, int qid, char *name) 4603 { 4604 struct grouptask *gtask; 4605 struct taskqgroup *tqg; 4606 gtask_fn_t *fn; 4607 void *q; 4608 4609 switch (type) { 4610 case IFLIB_INTR_TX: 4611 q = &ctx->ifc_txqs[qid]; 4612 gtask = &ctx->ifc_txqs[qid].ift_task; 4613 tqg = qgroup_softirq; 4614 fn = _task_fn_tx; 4615 break; 4616 case IFLIB_INTR_RX: 4617 q = &ctx->ifc_rxqs[qid]; 4618 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4619 tqg = qgroup_softirq; 4620 fn = _task_fn_rx; 4621 break; 4622 case IFLIB_INTR_IOV: 4623 q = ctx; 4624 gtask = &ctx->ifc_vflr_task; 4625 tqg = qgroup_if_config_tqg; 4626 rid = -1; 4627 fn = _task_fn_iov; 4628 break; 4629 default: 4630 panic("unknown net intr type"); 4631 } 4632 GROUPTASK_INIT(gtask, 0, fn, q); 4633 taskqgroup_attach(tqg, gtask, q, rid, name); 4634 } 4635 4636 void 4637 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 4638 { 4639 if (irq->ii_tag) 4640 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 4641 4642 if (irq->ii_res) 4643 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 4644 } 4645 4646 static int 4647 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name) 4648 { 4649 iflib_txq_t txq = ctx->ifc_txqs; 4650 iflib_rxq_t rxq = ctx->ifc_rxqs; 4651 if_irq_t irq = &ctx->ifc_legacy_irq; 4652 iflib_filter_info_t info; 4653 struct grouptask *gtask; 4654 struct taskqgroup *tqg; 4655 gtask_fn_t *fn; 4656 int tqrid; 4657 void *q; 4658 int err; 4659 4660 q = &ctx->ifc_rxqs[0]; 4661 info = &rxq[0].ifr_filter_info; 4662 gtask = &rxq[0].ifr_task; 4663 tqg = qgroup_softirq; 4664 tqrid = irq->ii_rid = *rid; 4665 fn = _task_fn_rx; 4666 4667 ctx->ifc_flags |= IFC_LEGACY; 4668 info->ifi_filter = filter; 4669 info->ifi_filter_arg = filter_arg; 4670 info->ifi_task = gtask; 4671 info->ifi_ctx = ctx; 4672 4673 /* We allocate a single interrupt resource */ 4674 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr, NULL, info, name)) != 0) 4675 return (err); 4676 GROUPTASK_INIT(gtask, 0, fn, q); 4677 taskqgroup_attach(tqg, gtask, q, tqrid, name); 4678 4679 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 4680 taskqgroup_attach(qgroup_softirq, &txq->ift_task, txq, tqrid, "tx"); 4681 return (0); 4682 } 4683 4684 void 4685 iflib_led_create(if_ctx_t ctx) 4686 { 4687 4688 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 4689 device_get_nameunit(ctx->ifc_dev)); 4690 } 4691 4692 void 4693 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 4694 { 4695 4696 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 4697 } 4698 4699 void 4700 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 4701 { 4702 4703 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 4704 } 4705 4706 void 4707 iflib_admin_intr_deferred(if_ctx_t ctx) 4708 { 4709 #ifdef INVARIANTS 4710 struct grouptask *gtask; 4711 4712 gtask = &ctx->ifc_admin_task; 4713 MPASS(gtask->gt_taskqueue != NULL); 4714 #endif 4715 4716 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 4717 } 4718 4719 void 4720 iflib_iov_intr_deferred(if_ctx_t ctx) 4721 { 4722 4723 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 4724 } 4725 4726 void 4727 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 4728 { 4729 4730 taskqgroup_attach_cpu(qgroup_softirq, gt, uniq, cpu, -1, name); 4731 } 4732 4733 void 4734 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn, 4735 char *name) 4736 { 4737 4738 GROUPTASK_INIT(gtask, 0, fn, ctx); 4739 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 4740 } 4741 4742 void 4743 iflib_config_gtask_deinit(struct grouptask *gtask) 4744 { 4745 4746 taskqgroup_detach(qgroup_if_config_tqg, gtask); 4747 } 4748 4749 void 4750 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 4751 { 4752 if_t ifp = ctx->ifc_ifp; 4753 iflib_txq_t txq = ctx->ifc_txqs; 4754 4755 if_setbaudrate(ifp, baudrate); 4756 4757 /* If link down, disable watchdog */ 4758 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 4759 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 4760 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 4761 } 4762 ctx->ifc_link_state = link_state; 4763 if_link_state_change(ifp, link_state); 4764 } 4765 4766 static int 4767 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 4768 { 4769 int credits; 4770 #ifdef INVARIANTS 4771 int credits_pre = txq->ift_cidx_processed; 4772 #endif 4773 4774 if (ctx->isc_txd_credits_update == NULL) 4775 return (0); 4776 4777 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, txq->ift_cidx_processed, true)) == 0) 4778 return (0); 4779 4780 txq->ift_processed += credits; 4781 txq->ift_cidx_processed += credits; 4782 4783 MPASS(credits_pre + credits == txq->ift_cidx_processed); 4784 if (txq->ift_cidx_processed >= txq->ift_size) 4785 txq->ift_cidx_processed -= txq->ift_size; 4786 return (credits); 4787 } 4788 4789 static int 4790 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, int cidx, int budget) 4791 { 4792 4793 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 4794 budget)); 4795 } 4796 4797 void 4798 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 4799 const char *description, if_int_delay_info_t info, 4800 int offset, int value) 4801 { 4802 info->iidi_ctx = ctx; 4803 info->iidi_offset = offset; 4804 info->iidi_value = value; 4805 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 4806 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 4807 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 4808 info, 0, iflib_sysctl_int_delay, "I", description); 4809 } 4810 4811 struct mtx * 4812 iflib_ctx_lock_get(if_ctx_t ctx) 4813 { 4814 4815 return (&ctx->ifc_mtx); 4816 } 4817 4818 static int 4819 iflib_msix_init(if_ctx_t ctx) 4820 { 4821 device_t dev = ctx->ifc_dev; 4822 if_shared_ctx_t sctx = ctx->ifc_sctx; 4823 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4824 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 4825 int iflib_num_tx_queues, iflib_num_rx_queues; 4826 int err, admincnt, bar; 4827 4828 iflib_num_tx_queues = scctx->isc_ntxqsets; 4829 iflib_num_rx_queues = scctx->isc_nrxqsets; 4830 4831 device_printf(dev, "msix_init qsets capped at %d\n", iflib_num_tx_queues); 4832 4833 bar = ctx->ifc_softc_ctx.isc_msix_bar; 4834 admincnt = sctx->isc_admin_intrcnt; 4835 /* Override by tuneable */ 4836 if (enable_msix == 0) 4837 goto msi; 4838 4839 /* 4840 ** When used in a virtualized environment 4841 ** PCI BUSMASTER capability may not be set 4842 ** so explicity set it here and rewrite 4843 ** the ENABLE in the MSIX control register 4844 ** at this point to cause the host to 4845 ** successfully initialize us. 4846 */ 4847 { 4848 int msix_ctrl, rid; 4849 4850 pci_enable_busmaster(dev); 4851 rid = 0; 4852 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) { 4853 rid += PCIR_MSIX_CTRL; 4854 msix_ctrl = pci_read_config(dev, rid, 2); 4855 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 4856 pci_write_config(dev, rid, msix_ctrl, 2); 4857 } else { 4858 device_printf(dev, "PCIY_MSIX capability not found; " 4859 "or rid %d == 0.\n", rid); 4860 goto msi; 4861 } 4862 } 4863 4864 /* 4865 * bar == -1 => "trust me I know what I'm doing" 4866 * https://www.youtube.com/watch?v=nnwWKkNau4I 4867 * Some drivers are for hardware that is so shoddily 4868 * documented that no one knows which bars are which 4869 * so the developer has to map all bars. This hack 4870 * allows shoddy garbage to use msix in this framework. 4871 */ 4872 if (bar != -1) { 4873 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 4874 SYS_RES_MEMORY, &bar, RF_ACTIVE); 4875 if (ctx->ifc_msix_mem == NULL) { 4876 /* May not be enabled */ 4877 device_printf(dev, "Unable to map MSIX table \n"); 4878 goto msi; 4879 } 4880 } 4881 /* First try MSI/X */ 4882 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 4883 device_printf(dev, "System has MSIX disabled \n"); 4884 bus_release_resource(dev, SYS_RES_MEMORY, 4885 bar, ctx->ifc_msix_mem); 4886 ctx->ifc_msix_mem = NULL; 4887 goto msi; 4888 } 4889 #if IFLIB_DEBUG 4890 /* use only 1 qset in debug mode */ 4891 queuemsgs = min(msgs - admincnt, 1); 4892 #else 4893 queuemsgs = msgs - admincnt; 4894 #endif 4895 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) == 0) { 4896 #ifdef RSS 4897 queues = imin(queuemsgs, rss_getnumbuckets()); 4898 #else 4899 queues = queuemsgs; 4900 #endif 4901 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 4902 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 4903 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 4904 } else { 4905 device_printf(dev, "Unable to fetch CPU list\n"); 4906 /* Figure out a reasonable auto config value */ 4907 queues = min(queuemsgs, mp_ncpus); 4908 } 4909 #ifdef RSS 4910 /* If we're doing RSS, clamp at the number of RSS buckets */ 4911 if (queues > rss_getnumbuckets()) 4912 queues = rss_getnumbuckets(); 4913 #endif 4914 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 4915 rx_queues = iflib_num_rx_queues; 4916 else 4917 rx_queues = queues; 4918 /* 4919 * We want this to be all logical CPUs by default 4920 */ 4921 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 4922 tx_queues = iflib_num_tx_queues; 4923 else 4924 tx_queues = mp_ncpus; 4925 4926 if (ctx->ifc_sysctl_qs_eq_override == 0) { 4927 #ifdef INVARIANTS 4928 if (tx_queues != rx_queues) 4929 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 4930 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 4931 #endif 4932 tx_queues = min(rx_queues, tx_queues); 4933 rx_queues = min(rx_queues, tx_queues); 4934 } 4935 4936 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 4937 4938 vectors = rx_queues + admincnt; 4939 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 4940 device_printf(dev, 4941 "Using MSIX interrupts with %d vectors\n", vectors); 4942 scctx->isc_vectors = vectors; 4943 scctx->isc_nrxqsets = rx_queues; 4944 scctx->isc_ntxqsets = tx_queues; 4945 scctx->isc_intr = IFLIB_INTR_MSIX; 4946 4947 return (vectors); 4948 } else { 4949 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 4950 } 4951 msi: 4952 vectors = pci_msi_count(dev); 4953 scctx->isc_nrxqsets = 1; 4954 scctx->isc_ntxqsets = 1; 4955 scctx->isc_vectors = vectors; 4956 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 4957 device_printf(dev,"Using an MSI interrupt\n"); 4958 scctx->isc_intr = IFLIB_INTR_MSI; 4959 } else { 4960 device_printf(dev,"Using a Legacy interrupt\n"); 4961 scctx->isc_intr = IFLIB_INTR_LEGACY; 4962 } 4963 4964 return (vectors); 4965 } 4966 4967 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 4968 4969 static int 4970 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 4971 { 4972 int rc; 4973 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 4974 struct sbuf *sb; 4975 char *ring_state = "UNKNOWN"; 4976 4977 /* XXX needed ? */ 4978 rc = sysctl_wire_old_buffer(req, 0); 4979 MPASS(rc == 0); 4980 if (rc != 0) 4981 return (rc); 4982 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 4983 MPASS(sb != NULL); 4984 if (sb == NULL) 4985 return (ENOMEM); 4986 if (state[3] <= 3) 4987 ring_state = ring_states[state[3]]; 4988 4989 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 4990 state[0], state[1], state[2], ring_state); 4991 rc = sbuf_finish(sb); 4992 sbuf_delete(sb); 4993 return(rc); 4994 } 4995 4996 enum iflib_ndesc_handler { 4997 IFLIB_NTXD_HANDLER, 4998 IFLIB_NRXD_HANDLER, 4999 }; 5000 5001 static int 5002 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 5003 { 5004 if_ctx_t ctx = (void *)arg1; 5005 enum iflib_ndesc_handler type = arg2; 5006 char buf[256] = {0}; 5007 uint16_t *ndesc; 5008 char *p, *next; 5009 int nqs, rc, i; 5010 5011 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 5012 5013 nqs = 8; 5014 switch(type) { 5015 case IFLIB_NTXD_HANDLER: 5016 ndesc = ctx->ifc_sysctl_ntxds; 5017 if (ctx->ifc_sctx) 5018 nqs = ctx->ifc_sctx->isc_ntxqs; 5019 break; 5020 case IFLIB_NRXD_HANDLER: 5021 ndesc = ctx->ifc_sysctl_nrxds; 5022 if (ctx->ifc_sctx) 5023 nqs = ctx->ifc_sctx->isc_nrxqs; 5024 break; 5025 } 5026 if (nqs == 0) 5027 nqs = 8; 5028 5029 for (i=0; i<8; i++) { 5030 if (i >= nqs) 5031 break; 5032 if (i) 5033 strcat(buf, ","); 5034 sprintf(strchr(buf, 0), "%d", ndesc[i]); 5035 } 5036 5037 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 5038 if (rc || req->newptr == NULL) 5039 return rc; 5040 5041 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 5042 i++, p = strsep(&next, " ,")) { 5043 ndesc[i] = strtoul(p, NULL, 10); 5044 } 5045 5046 return(rc); 5047 } 5048 5049 #define NAME_BUFLEN 32 5050 static void 5051 iflib_add_device_sysctl_pre(if_ctx_t ctx) 5052 { 5053 device_t dev = iflib_get_dev(ctx); 5054 struct sysctl_oid_list *child, *oid_list; 5055 struct sysctl_ctx_list *ctx_list; 5056 struct sysctl_oid *node; 5057 5058 ctx_list = device_get_sysctl_ctx(dev); 5059 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 5060 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 5061 CTLFLAG_RD, NULL, "IFLIB fields"); 5062 oid_list = SYSCTL_CHILDREN(node); 5063 5064 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 5065 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 5066 "driver version"); 5067 5068 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 5069 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 5070 "# of txqs to use, 0 => use default #"); 5071 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 5072 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 5073 "# of rxqs to use, 0 => use default #"); 5074 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 5075 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 5076 "permit #txq != #rxq"); 5077 5078 /* XXX change for per-queue sizes */ 5079 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 5080 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 5081 mp_ndesc_handler, "A", 5082 "list of # of tx descriptors to use, 0 = use default #"); 5083 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 5084 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 5085 mp_ndesc_handler, "A", 5086 "list of # of rx descriptors to use, 0 = use default #"); 5087 } 5088 5089 static void 5090 iflib_add_device_sysctl_post(if_ctx_t ctx) 5091 { 5092 if_shared_ctx_t sctx = ctx->ifc_sctx; 5093 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5094 device_t dev = iflib_get_dev(ctx); 5095 struct sysctl_oid_list *child; 5096 struct sysctl_ctx_list *ctx_list; 5097 iflib_fl_t fl; 5098 iflib_txq_t txq; 5099 iflib_rxq_t rxq; 5100 int i, j; 5101 char namebuf[NAME_BUFLEN]; 5102 char *qfmt; 5103 struct sysctl_oid *queue_node, *fl_node, *node; 5104 struct sysctl_oid_list *queue_list, *fl_list; 5105 ctx_list = device_get_sysctl_ctx(dev); 5106 5107 node = ctx->ifc_sysctl_node; 5108 child = SYSCTL_CHILDREN(node); 5109 5110 if (scctx->isc_ntxqsets > 100) 5111 qfmt = "txq%03d"; 5112 else if (scctx->isc_ntxqsets > 10) 5113 qfmt = "txq%02d"; 5114 else 5115 qfmt = "txq%d"; 5116 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 5117 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5118 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5119 CTLFLAG_RD, NULL, "Queue Name"); 5120 queue_list = SYSCTL_CHILDREN(queue_node); 5121 #if MEMORY_LOGGING 5122 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 5123 CTLFLAG_RD, 5124 &txq->ift_dequeued, "total mbufs freed"); 5125 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 5126 CTLFLAG_RD, 5127 &txq->ift_enqueued, "total mbufs enqueued"); 5128 #endif 5129 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 5130 CTLFLAG_RD, 5131 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 5132 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 5133 CTLFLAG_RD, 5134 &txq->ift_pullups, "# of times m_pullup was called"); 5135 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 5136 CTLFLAG_RD, 5137 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 5138 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 5139 CTLFLAG_RD, 5140 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 5141 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 5142 CTLFLAG_RD, 5143 &txq->ift_map_failed, "# of times dma map failed"); 5144 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 5145 CTLFLAG_RD, 5146 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 5147 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 5148 CTLFLAG_RD, 5149 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 5150 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 5151 CTLFLAG_RD, 5152 &txq->ift_pidx, 1, "Producer Index"); 5153 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 5154 CTLFLAG_RD, 5155 &txq->ift_cidx, 1, "Consumer Index"); 5156 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 5157 CTLFLAG_RD, 5158 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 5159 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 5160 CTLFLAG_RD, 5161 &txq->ift_in_use, 1, "descriptors in use"); 5162 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 5163 CTLFLAG_RD, 5164 &txq->ift_processed, "descriptors procesed for clean"); 5165 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 5166 CTLFLAG_RD, 5167 &txq->ift_cleaned, "total cleaned"); 5168 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 5169 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br[0]->state), 5170 0, mp_ring_state_handler, "A", "soft ring state"); 5171 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 5172 CTLFLAG_RD, &txq->ift_br[0]->enqueues, 5173 "# of enqueues to the mp_ring for this queue"); 5174 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 5175 CTLFLAG_RD, &txq->ift_br[0]->drops, 5176 "# of drops in the mp_ring for this queue"); 5177 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 5178 CTLFLAG_RD, &txq->ift_br[0]->starts, 5179 "# of normal consumer starts in the mp_ring for this queue"); 5180 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 5181 CTLFLAG_RD, &txq->ift_br[0]->stalls, 5182 "# of consumer stalls in the mp_ring for this queue"); 5183 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 5184 CTLFLAG_RD, &txq->ift_br[0]->restarts, 5185 "# of consumer restarts in the mp_ring for this queue"); 5186 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 5187 CTLFLAG_RD, &txq->ift_br[0]->abdications, 5188 "# of consumer abdications in the mp_ring for this queue"); 5189 } 5190 5191 if (scctx->isc_nrxqsets > 100) 5192 qfmt = "rxq%03d"; 5193 else if (scctx->isc_nrxqsets > 10) 5194 qfmt = "rxq%02d"; 5195 else 5196 qfmt = "rxq%d"; 5197 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 5198 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5199 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5200 CTLFLAG_RD, NULL, "Queue Name"); 5201 queue_list = SYSCTL_CHILDREN(queue_node); 5202 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5203 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 5204 CTLFLAG_RD, 5205 &rxq->ifr_cq_pidx, 1, "Producer Index"); 5206 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 5207 CTLFLAG_RD, 5208 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 5209 } 5210 5211 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 5212 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 5213 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 5214 CTLFLAG_RD, NULL, "freelist Name"); 5215 fl_list = SYSCTL_CHILDREN(fl_node); 5216 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 5217 CTLFLAG_RD, 5218 &fl->ifl_pidx, 1, "Producer Index"); 5219 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 5220 CTLFLAG_RD, 5221 &fl->ifl_cidx, 1, "Consumer Index"); 5222 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 5223 CTLFLAG_RD, 5224 &fl->ifl_credits, 1, "credits available"); 5225 #if MEMORY_LOGGING 5226 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 5227 CTLFLAG_RD, 5228 &fl->ifl_m_enqueued, "mbufs allocated"); 5229 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 5230 CTLFLAG_RD, 5231 &fl->ifl_m_dequeued, "mbufs freed"); 5232 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 5233 CTLFLAG_RD, 5234 &fl->ifl_cl_enqueued, "clusters allocated"); 5235 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 5236 CTLFLAG_RD, 5237 &fl->ifl_cl_dequeued, "clusters freed"); 5238 #endif 5239 5240 } 5241 } 5242 5243 } 5244