1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include "opt_inet.h" 30 #include "opt_inet6.h" 31 #include "opt_acpi.h" 32 33 #include <sys/param.h> 34 #include <sys/types.h> 35 #include <sys/bus.h> 36 #include <sys/eventhandler.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/module.h> 41 #include <sys/kobj.h> 42 #include <sys/proc.h> 43 #include <sys/rman.h> 44 #include <sys/sbuf.h> 45 #include <sys/sched.h> 46 #include <sys/smp.h> 47 #include <sys/socket.h> 48 #include <sys/sockio.h> 49 #include <sys/sysctl.h> 50 #include <sys/syslog.h> 51 #include <sys/taskqueue.h> 52 #include <sys/limits.h> 53 54 #include <net/if.h> 55 #include <net/if_var.h> 56 #include <net/if_private.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/udp.h> 75 #include <netinet/ip_var.h> 76 #include <netinet6/ip6_var.h> 77 78 #include <machine/bus.h> 79 #include <machine/in_cksum.h> 80 81 #include <vm/vm.h> 82 #include <vm/pmap.h> 83 84 #include <dev/led/led.h> 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pci_private.h> 88 89 #include <net/iflib.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 /* 120 * File organization: 121 * - private structures 122 * - iflib private utility functions 123 * - ifnet functions 124 * - vlan registry and other exported functions 125 * - iflib public core functions 126 * 127 * 128 */ 129 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 130 131 #define IFLIB_RXEOF_MORE (1U << 0) 132 #define IFLIB_RXEOF_EMPTY (2U << 0) 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 static void iflib_tqg_detach(if_ctx_t ctx); 146 #ifndef ALTQ 147 static int iflib_simple_transmit(if_t ifp, struct mbuf *m); 148 #endif 149 150 typedef struct iflib_filter_info { 151 driver_filter_t *ifi_filter; 152 void *ifi_filter_arg; 153 struct grouptask *ifi_task; 154 void *ifi_ctx; 155 } *iflib_filter_info_t; 156 157 struct iflib_ctx { 158 KOBJ_FIELDS; 159 /* 160 * Pointer to hardware driver's softc 161 */ 162 void *ifc_softc; 163 device_t ifc_dev; 164 if_t ifc_ifp; 165 166 cpuset_t ifc_cpus; 167 if_shared_ctx_t ifc_sctx; 168 struct if_softc_ctx ifc_softc_ctx; 169 170 struct sx ifc_ctx_sx; 171 struct mtx ifc_state_mtx; 172 173 iflib_txq_t ifc_txqs; 174 iflib_rxq_t ifc_rxqs; 175 uint32_t ifc_if_flags; 176 uint32_t ifc_flags; 177 uint32_t ifc_max_fl_buf_size; 178 uint32_t ifc_rx_mbuf_sz; 179 180 int ifc_link_state; 181 int ifc_watchdog_events; 182 struct cdev *ifc_led_dev; 183 struct resource *ifc_msix_mem; 184 185 struct if_irq ifc_legacy_irq; 186 struct task ifc_admin_task; 187 struct task ifc_vflr_task; 188 struct taskqueue *ifc_tq; 189 struct iflib_filter_info ifc_filter_info; 190 struct ifmedia ifc_media; 191 struct ifmedia *ifc_mediap; 192 193 struct sysctl_ctx_list ifc_sysctl_ctx; 194 struct sysctl_oid *ifc_sysctl_node; 195 uint16_t ifc_sysctl_ntxqs; 196 uint16_t ifc_sysctl_nrxqs; 197 uint16_t ifc_sysctl_qs_eq_override; 198 uint16_t ifc_sysctl_rx_budget; 199 uint16_t ifc_sysctl_tx_abdicate; 200 uint16_t ifc_sysctl_core_offset; 201 #define CORE_OFFSET_UNSPECIFIED 0xffff 202 uint8_t ifc_sysctl_separate_txrx; 203 uint8_t ifc_sysctl_use_logical_cores; 204 uint16_t ifc_sysctl_extra_msix_vectors; 205 bool ifc_cpus_are_physical_cores; 206 bool ifc_sysctl_simple_tx; 207 bool ifc_sysctl_tx_defer_mfree; 208 uint16_t ifc_sysctl_tx_reclaim_thresh; 209 uint16_t ifc_sysctl_tx_reclaim_ticks; 210 211 qidx_t ifc_sysctl_ntxds[8]; 212 qidx_t ifc_sysctl_nrxds[8]; 213 struct if_txrx ifc_txrx; 214 #define isc_txd_encap ifc_txrx.ift_txd_encap 215 #define isc_txd_flush ifc_txrx.ift_txd_flush 216 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 217 #define isc_rxd_available ifc_txrx.ift_rxd_available 218 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 219 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 220 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 221 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 222 #define isc_txq_select ifc_txrx.ift_txq_select 223 #define isc_txq_select_v2 ifc_txrx.ift_txq_select_v2 224 225 eventhandler_tag ifc_vlan_attach_event; 226 eventhandler_tag ifc_vlan_detach_event; 227 struct ether_addr ifc_mac; 228 }; 229 230 void * 231 iflib_get_softc(if_ctx_t ctx) 232 { 233 234 return (ctx->ifc_softc); 235 } 236 237 device_t 238 iflib_get_dev(if_ctx_t ctx) 239 { 240 241 return (ctx->ifc_dev); 242 } 243 244 if_t 245 iflib_get_ifp(if_ctx_t ctx) 246 { 247 248 return (ctx->ifc_ifp); 249 } 250 251 struct ifmedia * 252 iflib_get_media(if_ctx_t ctx) 253 { 254 255 return (ctx->ifc_mediap); 256 } 257 258 void 259 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 260 { 261 262 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 263 } 264 265 if_softc_ctx_t 266 iflib_get_softc_ctx(if_ctx_t ctx) 267 { 268 269 return (&ctx->ifc_softc_ctx); 270 } 271 272 if_shared_ctx_t 273 iflib_get_sctx(if_ctx_t ctx) 274 { 275 276 return (ctx->ifc_sctx); 277 } 278 279 uint16_t 280 iflib_get_extra_msix_vectors_sysctl(if_ctx_t ctx) 281 { 282 283 return (ctx->ifc_sysctl_extra_msix_vectors); 284 } 285 286 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 287 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE / sizeof(void *)) 288 #define CACHE_PTR_NEXT(ptr) ((void *)(roundup2(ptr, CACHE_LINE_SIZE))) 289 290 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 291 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 292 293 typedef struct iflib_sw_rx_desc_array { 294 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 295 struct mbuf **ifsd_m; /* pkthdr mbufs */ 296 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 297 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 298 } iflib_rxsd_array_t; 299 300 typedef struct iflib_sw_tx_desc_array { 301 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 302 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 303 struct mbuf **ifsd_m; /* pkthdr mbufs */ 304 struct mbuf **ifsd_m_defer; /* deferred mbuf ptr */ 305 struct mbuf **ifsd_m_deferb;/* deferred mbuf backing ptr */ 306 } if_txsd_vec_t; 307 308 /* magic number that should be high enough for any hardware */ 309 #define IFLIB_MAX_TX_SEGS 128 310 #define IFLIB_RX_COPY_THRESH 128 311 #define IFLIB_MAX_RX_REFRESH 32 312 /* The minimum descriptors per second before we start coalescing */ 313 #define IFLIB_MIN_DESC_SEC 16384 314 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 315 /* maximum number of txqs that can share an rx interrupt */ 316 #define IFLIB_MAX_TX_SHARED_INTR 4 317 318 /* this should really scale with ring size - this is a fairly arbitrary value */ 319 #define TX_BATCH_SIZE 32 320 321 #define IFLIB_RESTART_BUDGET 8 322 323 324 /* 325 * Encode TSO or !TSO in the low bits of the tx ifsd_m pointer so as 326 * to avoid defref'ing the mbuf to determine the correct busdma resources 327 * to release 328 */ 329 #define IFLIB_TSO (1ULL << 0) 330 #define IFLIB_NO_TSO (2ULL << 0) 331 #define IFLIB_FLAGS_MASK (0x3ULL) 332 #define IFLIB_SAVE_MBUF(mbuf, flags) ((void *)(((uintptr_t)mbuf) | flags)) 333 #define IFLIB_GET_FLAGS(a) ((uintptr_t)a & IFLIB_FLAGS_MASK) 334 #define IFLIB_GET_MBUF(a) ((struct mbuf *)((uintptr_t)a & ~IFLIB_FLAGS_MASK)) 335 336 337 #define IFC_LEGACY 0x001 338 #define IFC_QFLUSH 0x002 339 #define IFC_MULTISEG 0x004 340 #define IFC_SPARE1 0x008 341 #define IFC_SC_ALLOCATED 0x010 342 #define IFC_INIT_DONE 0x020 343 #define IFC_PREFETCH 0x040 344 #define IFC_DO_RESET 0x080 345 #define IFC_DO_WATCHDOG 0x100 346 #define IFC_SPARE0 0x200 347 #define IFC_SPARE2 0x400 348 #define IFC_IN_DETACH 0x800 349 350 #define IFC_NETMAP_TX_IRQ 0x80000000 351 352 #define CSUM_OFFLOAD (CSUM_IP_TSO | CSUM_IP6_TSO | CSUM_IP | \ 353 CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_SCTP | \ 354 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_SCTP) 355 356 struct iflib_txq { 357 qidx_t ift_in_use; 358 qidx_t ift_cidx; 359 qidx_t ift_cidx_processed; 360 qidx_t ift_pidx; 361 uint8_t ift_gen; 362 uint8_t ift_br_offset:1, 363 ift_defer_mfree:1, 364 ift_spare_bits0:6; 365 uint16_t ift_npending; 366 uint16_t ift_db_pending; 367 uint16_t ift_rs_pending; 368 uint32_t ift_last_reclaim; 369 uint16_t ift_reclaim_thresh; 370 uint16_t ift_reclaim_ticks; 371 uint8_t ift_txd_size[8]; 372 uint64_t ift_processed; 373 uint64_t ift_cleaned; 374 uint64_t ift_processed_prev; 375 #if MEMORY_LOGGING 376 uint64_t ift_enqueued; 377 uint64_t ift_dequeued; 378 #endif 379 uint64_t ift_no_tx_dma_setup; 380 uint64_t ift_no_desc_avail; 381 uint64_t ift_mbuf_defrag_failed; 382 uint64_t ift_mbuf_defrag; 383 uint64_t ift_map_failed; 384 uint64_t ift_txd_encap_efbig; 385 uint64_t ift_pullups; 386 uint64_t ift_last_timer_tick; 387 388 struct mtx ift_mtx; 389 struct mtx ift_db_mtx; 390 391 /* constant values */ 392 if_ctx_t ift_ctx; 393 struct ifmp_ring *ift_br; 394 struct grouptask ift_task; 395 qidx_t ift_size; 396 qidx_t ift_pad; 397 uint16_t ift_id; 398 struct callout ift_timer; 399 #ifdef DEV_NETMAP 400 struct callout ift_netmap_timer; 401 #endif /* DEV_NETMAP */ 402 403 if_txsd_vec_t ift_sds; 404 /* 405 * TX watchdog state, updated once per iflib_timer period. The 406 * period count saturates instead of wrapping, and is 16 bits 407 * wide so that it still reaches any value 408 * net.iflib.tx_watchdog_periods is plausibly set to; an 8-bit 409 * counter would silently disable the check for a threshold 410 * above 255. 411 */ 412 qidx_t ift_outstanding_prev; 413 uint16_t ift_wdog_armed; 414 uint8_t ift_closed; 415 uint8_t ift_update_freq; 416 uint8_t ift_spare0[2]; /* pad to the next pointer boundary */ 417 struct iflib_filter_info ift_filter_info; 418 bus_dma_tag_t ift_buf_tag; 419 bus_dma_tag_t ift_tso_buf_tag; 420 iflib_dma_info_t ift_ifdi; 421 #define MTX_NAME_LEN 32 422 char ift_mtx_name[MTX_NAME_LEN]; 423 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 424 #ifdef IFLIB_DIAGNOSTICS 425 uint64_t ift_cpu_exec_count[256]; 426 #endif 427 } __aligned(CACHE_LINE_SIZE); 428 429 struct iflib_fl { 430 qidx_t ifl_cidx; 431 qidx_t ifl_pidx; 432 qidx_t ifl_credits; 433 uint8_t ifl_gen; 434 uint8_t ifl_rxd_size; 435 #if MEMORY_LOGGING 436 uint64_t ifl_m_enqueued; 437 uint64_t ifl_m_dequeued; 438 uint64_t ifl_cl_enqueued; 439 uint64_t ifl_cl_dequeued; 440 #endif 441 /* implicit pad */ 442 bitstr_t *ifl_rx_bitmap; 443 qidx_t ifl_fragidx; 444 /* constant */ 445 qidx_t ifl_size; 446 uint16_t ifl_buf_size; 447 uint16_t ifl_cltype; 448 uma_zone_t ifl_zone; 449 iflib_rxsd_array_t ifl_sds; 450 iflib_rxq_t ifl_rxq; 451 uint8_t ifl_id; 452 bus_dma_tag_t ifl_buf_tag; 453 iflib_dma_info_t ifl_ifdi; 454 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 455 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 456 } __aligned(CACHE_LINE_SIZE); 457 458 static inline qidx_t 459 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 460 { 461 qidx_t used; 462 463 if (pidx > cidx) 464 used = pidx - cidx; 465 else if (pidx < cidx) 466 used = size - cidx + pidx; 467 else if (gen == 0 && pidx == cidx) 468 used = 0; 469 else if (gen == 1 && pidx == cidx) 470 used = size; 471 else 472 panic("bad state"); 473 474 return (used); 475 } 476 477 #define TXQ_AVAIL(txq) ((txq->ift_size - txq->ift_pad) -\ 478 get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 479 480 #define IDXDIFF(head, tail, wrap) \ 481 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 482 483 struct iflib_rxq { 484 if_ctx_t ifr_ctx; 485 iflib_fl_t ifr_fl; 486 struct pfil_head *pfil; 487 /* 488 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 489 * the completion queue consumer index. Otherwise it's unused. 490 */ 491 qidx_t ifr_cq_cidx; 492 uint16_t ifr_id; 493 uint8_t ifr_nfl; 494 uint8_t ifr_ntxqirq; 495 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 496 uint8_t ifr_fl_offset; 497 struct lro_ctrl ifr_lc; 498 struct grouptask ifr_task; 499 struct callout ifr_watchdog; 500 struct iflib_filter_info ifr_filter_info; 501 iflib_dma_info_t ifr_ifdi; 502 503 /* dynamically allocate if any drivers need a value substantially larger than this */ 504 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 505 #ifdef IFLIB_DIAGNOSTICS 506 uint64_t ifr_cpu_exec_count[256]; 507 #endif 508 } __aligned(CACHE_LINE_SIZE); 509 510 typedef struct if_rxsd { 511 caddr_t *ifsd_cl; 512 iflib_fl_t ifsd_fl; 513 } *if_rxsd_t; 514 515 /* 516 * Only allow a single packet to take up most 1/nth of the tx ring 517 */ 518 #define MAX_SINGLE_PACKET_FRACTION 12 519 #define IF_BAD_DMA ((bus_addr_t)-1) 520 521 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 522 523 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 524 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 525 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 526 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 527 528 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 529 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 530 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 531 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 532 533 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 534 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 535 536 /* Our boot-time initialization hook */ 537 static int iflib_module_event_handler(module_t, int, void *); 538 539 static moduledata_t iflib_moduledata = { 540 "iflib", 541 iflib_module_event_handler, 542 NULL 543 }; 544 545 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 546 MODULE_VERSION(iflib, 1); 547 548 MODULE_DEPEND(iflib, pci, 1, 1, 1); 549 MODULE_DEPEND(iflib, ether, 1, 1, 1); 550 551 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 552 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 553 554 #ifndef IFLIB_DEBUG_COUNTERS 555 #ifdef INVARIANTS 556 #define IFLIB_DEBUG_COUNTERS 1 557 #else 558 #define IFLIB_DEBUG_COUNTERS 0 559 #endif /* !INVARIANTS */ 560 #endif 561 562 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 563 "iflib driver parameters"); 564 565 /* 566 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 567 */ 568 static int iflib_min_tx_latency = 0; 569 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 570 &iflib_min_tx_latency, 0, 571 "minimize transmit latency at the possible expense of throughput"); 572 static int iflib_no_tx_batch = 0; 573 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 574 &iflib_no_tx_batch, 0, 575 "minimize transmit latency at the possible expense of throughput"); 576 static int iflib_timer_default = 1000; 577 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW, 578 &iflib_timer_default, 0, "number of ticks between iflib_timer calls"); 579 /* 580 * Consecutive timer periods a TX queue must stay frozen - see 581 * iflib_timer(), which defines that state - before the hardware is 582 * asked whether it has completions pending. Four periods is roughly 583 * two seconds with the default timer interval: a healthy queue on 584 * hardware that coalesces completion reports (e.g. 8254x, 585 * TXDCTL.WTHRESH) stays frozen for at most two (measured on 82541PI), 586 * a wedged one until it is reset. 587 */ 588 static int iflib_tx_watchdog_periods = 4; 589 SYSCTL_INT(_net_iflib, OID_AUTO, tx_watchdog_periods, CTLFLAG_RWTUN, 590 &iflib_tx_watchdog_periods, 0, 591 "consecutive frozen timer periods before a TX queue is checked for " 592 "a hang (0 disables the check)"); 593 594 595 #if IFLIB_DEBUG_COUNTERS 596 597 static int iflib_tx_seen; 598 static int iflib_tx_sent; 599 static int iflib_tx_encap; 600 static int iflib_rx_allocs; 601 static int iflib_fl_refills; 602 static int iflib_fl_refills_large; 603 static int iflib_tx_frees; 604 605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, &iflib_tx_seen, 0, 606 "# TX mbufs seen"); 607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, &iflib_tx_sent, 0, 608 "# TX mbufs sent"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, &iflib_tx_encap, 0, 610 "# TX mbufs encapped"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, &iflib_tx_frees, 0, 612 "# TX frees"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, &iflib_rx_allocs, 0, 614 "# RX allocations"); 615 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, &iflib_fl_refills, 0, 616 "# refills"); 617 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 618 &iflib_fl_refills_large, 0, "# large refills"); 619 620 static int iflib_txq_drain_flushing; 621 static int iflib_txq_drain_oactive; 622 static int iflib_txq_drain_notready; 623 624 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 625 &iflib_txq_drain_flushing, 0, "# drain flushes"); 626 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 627 &iflib_txq_drain_oactive, 0, "# drain oactives"); 628 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 629 &iflib_txq_drain_notready, 0, "# drain notready"); 630 631 static int iflib_encap_load_mbuf_fail; 632 static int iflib_encap_pad_mbuf_fail; 633 static int iflib_encap_txq_avail_fail; 634 static int iflib_encap_txd_encap_fail; 635 636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 637 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 638 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 639 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 640 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 641 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 642 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 643 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 644 645 static int iflib_task_fn_rxs; 646 static int iflib_rx_intr_enables; 647 static int iflib_fast_intrs; 648 static int iflib_rx_unavail; 649 static int iflib_rx_ctx_inactive; 650 static int iflib_rx_if_input; 651 static int iflib_rxd_flush; 652 653 static int iflib_verbose_debug; 654 655 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, &iflib_task_fn_rxs, 0, 656 "# task_fn_rx calls"); 657 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 658 &iflib_rx_intr_enables, 0, "# RX intr enables"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, &iflib_fast_intrs, 0, 660 "# fast_intr calls"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, &iflib_rx_unavail, 0, 662 "# times rxeof called with no available data"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 664 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, &iflib_rx_if_input, 666 0, "# times rxeof called if_input"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, &iflib_rxd_flush, 0, 668 "# times rxd_flush called"); 669 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 670 &iflib_verbose_debug, 0, "enable verbose debugging"); 671 672 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 673 static void 674 iflib_debug_reset(void) 675 { 676 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 677 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 678 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 679 iflib_txq_drain_notready = 680 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 681 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 682 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 683 iflib_rx_unavail = 684 iflib_rx_ctx_inactive = iflib_rx_if_input = 685 iflib_rxd_flush = 0; 686 } 687 688 #else 689 #define DBG_COUNTER_INC(name) 690 static void iflib_debug_reset(void) {} 691 #endif 692 693 #define IFLIB_DEBUG 0 694 695 static void iflib_tx_structures_free(if_ctx_t ctx); 696 static void iflib_rx_structures_free(if_ctx_t ctx); 697 static int iflib_queues_alloc(if_ctx_t ctx); 698 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 699 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 700 static int iflib_qset_structures_setup(if_ctx_t ctx); 701 static int iflib_msix_init(if_ctx_t ctx); 702 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 703 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 704 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 705 #ifdef ALTQ 706 static void iflib_altq_if_start(if_t ifp); 707 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 708 #endif 709 static void iflib_register(if_ctx_t); 710 static void iflib_deregister(if_ctx_t); 711 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 712 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 713 static void iflib_init_locked(if_ctx_t ctx); 714 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 715 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 716 static void iflib_ifmp_purge(iflib_txq_t txq); 717 static void _iflib_pre_assert(if_softc_ctx_t scctx); 718 static void iflib_stop(if_ctx_t ctx); 719 static void iflib_if_init_locked(if_ctx_t ctx); 720 static void iflib_free_intr_mem(if_ctx_t ctx); 721 #ifndef __NO_STRICT_ALIGNMENT 722 static struct mbuf *iflib_fixup_rx(struct mbuf *m); 723 #endif 724 static __inline int iflib_completed_tx_reclaim(iflib_txq_t txq, 725 struct mbuf **m_defer); 726 static __inline void iflib_completed_tx_reclaim_force(iflib_txq_t txq); 727 728 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 729 SLIST_HEAD_INITIALIZER(cpu_offsets); 730 struct cpu_offset { 731 SLIST_ENTRY(cpu_offset) entries; 732 cpuset_t set; 733 unsigned int refcount; 734 uint16_t next_cpuid; 735 }; 736 static struct mtx cpu_offset_mtx; 737 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 738 MTX_DEF); 739 740 DEBUGNET_DEFINE(iflib); 741 742 static int 743 iflib_num_rx_descs(if_ctx_t ctx) 744 { 745 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 746 if_shared_ctx_t sctx = ctx->ifc_sctx; 747 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 748 749 return (scctx->isc_nrxd[first_rxq]); 750 } 751 752 static int 753 iflib_num_tx_descs(if_ctx_t ctx) 754 { 755 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 756 if_shared_ctx_t sctx = ctx->ifc_sctx; 757 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 758 759 return (scctx->isc_ntxd[first_txq]); 760 } 761 762 #ifdef DEV_NETMAP 763 #include <sys/selinfo.h> 764 #include <net/netmap.h> 765 #include <dev/netmap/netmap_kern.h> 766 767 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 768 769 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 770 static void iflib_netmap_timer(void *arg); 771 772 /* 773 * device-specific sysctl variables: 774 * 775 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 776 * During regular operations the CRC is stripped, but on some 777 * hardware reception of frames not multiple of 64 is slower, 778 * so using crcstrip=0 helps in benchmarks. 779 * 780 * iflib_rx_miss, iflib_rx_miss_bufs: 781 * count packets that might be missed due to lost interrupts. 782 */ 783 SYSCTL_DECL(_dev_netmap); 784 /* 785 * The xl driver by default strips CRCs and we do not override it. 786 */ 787 788 int iflib_crcstrip = 1; 789 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 790 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 791 792 int iflib_rx_miss, iflib_rx_miss_bufs; 793 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 794 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 795 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 796 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 797 798 /* 799 * Register/unregister. We are already under netmap lock. 800 * Only called on the first register or the last unregister. 801 */ 802 static int 803 iflib_netmap_register(struct netmap_adapter *na, int onoff) 804 { 805 if_t ifp = na->ifp; 806 if_ctx_t ctx = if_getsoftc(ifp); 807 int status; 808 809 CTX_LOCK(ctx); 810 if (!CTX_IS_VF(ctx)) 811 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 812 813 iflib_stop(ctx); 814 815 /* 816 * Enable (or disable) netmap flags, and intercept (or restore) 817 * ifp->if_transmit. This is done once the device has been stopped 818 * to prevent race conditions. Also, this must be done after 819 * calling netmap_disable_all_rings() and before calling 820 * netmap_enable_all_rings(), so that these two functions see the 821 * updated state of the NAF_NETMAP_ON bit. 822 */ 823 if (onoff) { 824 nm_set_native_flags(na); 825 } else { 826 nm_clear_native_flags(na); 827 } 828 829 iflib_init_locked(ctx); 830 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 831 status = if_getdrvflags(ifp) & IFF_DRV_RUNNING ? 0 : 1; 832 if (status) 833 nm_clear_native_flags(na); 834 CTX_UNLOCK(ctx); 835 return (status); 836 } 837 838 static int 839 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info) 840 { 841 if_t ifp = na->ifp; 842 if_ctx_t ctx = if_getsoftc(ifp); 843 iflib_rxq_t rxq = &ctx->ifc_rxqs[0]; 844 iflib_fl_t fl = &rxq->ifr_fl[0]; 845 846 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 847 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 848 info->num_tx_descs = iflib_num_tx_descs(ctx); 849 info->num_rx_descs = iflib_num_rx_descs(ctx); 850 info->rx_buf_maxsize = fl->ifl_buf_size; 851 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u", 852 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs, 853 info->num_rx_descs, info->rx_buf_maxsize); 854 855 return (0); 856 } 857 858 static int 859 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 860 { 861 struct netmap_adapter *na = kring->na; 862 u_int const lim = kring->nkr_num_slots - 1; 863 struct netmap_ring *ring = kring->ring; 864 bus_dmamap_t *map; 865 struct if_rxd_update iru; 866 if_ctx_t ctx = rxq->ifr_ctx; 867 iflib_fl_t fl = &rxq->ifr_fl[0]; 868 u_int nic_i_first, nic_i; 869 u_int nm_i; 870 int i, n; 871 #if IFLIB_DEBUG_COUNTERS 872 int rf_count = 0; 873 #endif 874 875 /* 876 * This function is used both at initialization and in rxsync. 877 * At initialization we need to prepare (with isc_rxd_refill()) 878 * all the netmap buffers currently owned by the kernel, in 879 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync 880 * (except for kring->nkr_hwofs). These may be less than 881 * kring->nkr_num_slots if netmap_reset() was called while 882 * an application using the kring that still owned some 883 * buffers. 884 * At rxsync time, both indexes point to the next buffer to be 885 * refilled. 886 * In any case we publish (with isc_rxd_flush()) up to 887 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 888 * pointer to overrun the head/cons pointer, although this is 889 * not necessary for some NICs (e.g. vmx). 890 */ 891 if (__predict_false(init)) { 892 n = kring->nkr_num_slots - nm_kr_rxspace(kring); 893 } else { 894 n = kring->rhead - kring->nr_hwcur; 895 if (n == 0) 896 return (0); /* Nothing to do. */ 897 if (n < 0) 898 n += kring->nkr_num_slots; 899 } 900 901 iru_init(&iru, rxq, 0 /* flid */); 902 map = fl->ifl_sds.ifsd_map; 903 nic_i = fl->ifl_pidx; 904 nm_i = netmap_idx_n2k(kring, nic_i); 905 if (__predict_false(init)) { 906 /* 907 * On init/reset, nic_i must be 0, and we must 908 * start to refill from hwtail (see netmap_reset()). 909 */ 910 MPASS(nic_i == 0); 911 MPASS(nm_i == kring->nr_hwtail); 912 } else 913 MPASS(nm_i == kring->nr_hwcur); 914 DBG_COUNTER_INC(fl_refills); 915 while (n > 0) { 916 #if IFLIB_DEBUG_COUNTERS 917 if (++rf_count == 9) 918 DBG_COUNTER_INC(fl_refills_large); 919 #endif 920 nic_i_first = nic_i; 921 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 922 struct netmap_slot *slot = &ring->slot[nm_i]; 923 uint64_t paddr; 924 void *addr = PNMB(na, slot, &paddr); 925 926 MPASS(i < IFLIB_MAX_RX_REFRESH); 927 928 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 929 return (netmap_ring_reinit(kring)); 930 931 fl->ifl_bus_addrs[i] = paddr + 932 nm_get_offset(kring, slot); 933 fl->ifl_rxd_idxs[i] = nic_i; 934 935 if (__predict_false(init)) { 936 netmap_load_map(na, fl->ifl_buf_tag, 937 map[nic_i], addr); 938 } else if (slot->flags & NS_BUF_CHANGED) { 939 /* buffer has changed, reload map */ 940 netmap_reload_map(na, fl->ifl_buf_tag, 941 map[nic_i], addr); 942 } 943 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 944 BUS_DMASYNC_PREREAD); 945 slot->flags &= ~NS_BUF_CHANGED; 946 947 nm_i = nm_next(nm_i, lim); 948 nic_i = nm_next(nic_i, lim); 949 } 950 951 iru.iru_pidx = nic_i_first; 952 iru.iru_count = i; 953 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 954 } 955 fl->ifl_pidx = nic_i; 956 /* 957 * At the end of the loop we must have refilled everything 958 * we could possibly refill. 959 */ 960 MPASS(nm_i == kring->rhead); 961 kring->nr_hwcur = nm_i; 962 963 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 964 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 965 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 966 nm_prev(nic_i, lim)); 967 DBG_COUNTER_INC(rxd_flush); 968 969 return (0); 970 } 971 972 #define NETMAP_TX_TIMER_US 90 973 974 /* 975 * Reconcile kernel and user view of the transmit ring. 976 * 977 * All information is in the kring. 978 * Userspace wants to send packets up to the one before kring->rhead, 979 * kernel knows kring->nr_hwcur is the first unsent packet. 980 * 981 * Here we push packets out (as many as possible), and possibly 982 * reclaim buffers from previously completed transmission. 983 * 984 * The caller (netmap) guarantees that there is only one instance 985 * running at any time. Any interference with other driver 986 * methods should be handled by the individual drivers. 987 */ 988 static int 989 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 990 { 991 struct netmap_adapter *na = kring->na; 992 if_t ifp = na->ifp; 993 struct netmap_ring *ring = kring->ring; 994 u_int nm_i; /* index into the netmap kring */ 995 u_int nic_i; /* index into the NIC ring */ 996 u_int const lim = kring->nkr_num_slots - 1; 997 u_int const head = kring->rhead; 998 struct if_pkt_info pi; 999 int tx_pkts = 0, tx_bytes = 0; 1000 1001 /* 1002 * interrupts on every tx packet are expensive so request 1003 * them every half ring, or where NS_REPORT is set 1004 */ 1005 u_int report_frequency = kring->nkr_num_slots >> 1; 1006 /* device-specific */ 1007 if_ctx_t ctx = if_getsoftc(ifp); 1008 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 1009 1010 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1011 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1012 1013 /* 1014 * First part: process new packets to send. 1015 * nm_i is the current index in the netmap kring, 1016 * nic_i is the corresponding index in the NIC ring. 1017 * 1018 * If we have packets to send (nm_i != head) 1019 * iterate over the netmap ring, fetch length and update 1020 * the corresponding slot in the NIC ring. Some drivers also 1021 * need to update the buffer's physical address in the NIC slot 1022 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 1023 * 1024 * The netmap_reload_map() calls is especially expensive, 1025 * even when (as in this case) the tag is 0, so do only 1026 * when the buffer has actually changed. 1027 * 1028 * If possible do not set the report/intr bit on all slots, 1029 * but only a few times per ring or when NS_REPORT is set. 1030 * 1031 * Finally, on 10G and faster drivers, it might be useful 1032 * to prefetch the next slot and txr entry. 1033 */ 1034 1035 nm_i = kring->nr_hwcur; 1036 if (nm_i != head) { /* we have new packets to send */ 1037 uint32_t pkt_len = 0, seg_idx = 0; 1038 int nic_i_start = -1, flags = 0; 1039 memset(&pi, 0, sizeof(pi)); 1040 pi.ipi_segs = txq->ift_segs; 1041 pi.ipi_qsidx = kring->ring_id; 1042 nic_i = netmap_idx_k2n(kring, nm_i); 1043 1044 __builtin_prefetch(&ring->slot[nm_i]); 1045 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 1046 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 1047 1048 while (nm_i != head) { 1049 struct netmap_slot *slot = &ring->slot[nm_i]; 1050 uint64_t offset = nm_get_offset(kring, slot); 1051 u_int len = slot->len; 1052 uint64_t paddr; 1053 void *addr = PNMB(na, slot, &paddr); 1054 1055 flags |= (slot->flags & NS_REPORT || 1056 nic_i == 0 || nic_i == report_frequency) ? 1057 IPI_TX_INTR : 0; 1058 1059 /* 1060 * If this is the first packet fragment, save the 1061 * index of the first NIC slot for later. 1062 */ 1063 if (nic_i_start < 0) 1064 nic_i_start = nic_i; 1065 1066 pi.ipi_segs[seg_idx].ds_addr = paddr + offset; 1067 pi.ipi_segs[seg_idx].ds_len = len; 1068 if (len) { 1069 pkt_len += len; 1070 seg_idx++; 1071 } 1072 1073 if (!(slot->flags & NS_MOREFRAG)) { 1074 pi.ipi_len = pkt_len; 1075 pi.ipi_nsegs = seg_idx; 1076 pi.ipi_pidx = nic_i_start; 1077 pi.ipi_ndescs = 0; 1078 pi.ipi_flags = flags; 1079 1080 /* Prepare the NIC TX ring. */ 1081 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1082 DBG_COUNTER_INC(tx_encap); 1083 1084 /* Update transmit counters */ 1085 tx_bytes += pi.ipi_len; 1086 tx_pkts++; 1087 1088 /* Reinit per-packet info for the next one. */ 1089 flags = seg_idx = pkt_len = 0; 1090 nic_i_start = -1; 1091 } 1092 1093 /* prefetch for next round */ 1094 __builtin_prefetch(&ring->slot[nm_i + 1]); 1095 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1096 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1097 1098 NM_CHECK_ADDR_LEN_OFF(na, len, offset); 1099 1100 if (slot->flags & NS_BUF_CHANGED) { 1101 /* buffer has changed, reload map */ 1102 netmap_reload_map(na, txq->ift_buf_tag, 1103 txq->ift_sds.ifsd_map[nic_i], addr); 1104 } 1105 /* make sure changes to the buffer are synced */ 1106 bus_dmamap_sync(txq->ift_buf_tag, 1107 txq->ift_sds.ifsd_map[nic_i], 1108 BUS_DMASYNC_PREWRITE); 1109 1110 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG); 1111 nm_i = nm_next(nm_i, lim); 1112 nic_i = nm_next(nic_i, lim); 1113 } 1114 kring->nr_hwcur = nm_i; 1115 1116 /* synchronize the NIC ring */ 1117 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1118 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1119 1120 /* (re)start the tx unit up to slot nic_i (excluded) */ 1121 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1122 } 1123 1124 /* 1125 * Second part: reclaim buffers for completed transmissions. 1126 * 1127 * If there are unclaimed buffers, attempt to reclaim them. 1128 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1129 * trigger a per-tx-queue timer to try again later. 1130 */ 1131 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1132 if (iflib_tx_credits_update(ctx, txq)) { 1133 /* some tx completed, increment avail */ 1134 nic_i = txq->ift_cidx_processed; 1135 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1136 } 1137 } 1138 1139 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1140 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1141 callout_reset_sbt_on(&txq->ift_netmap_timer, 1142 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1143 iflib_netmap_timer, txq, 1144 txq->ift_netmap_timer.c_cpu, 0); 1145 } 1146 1147 if_inc_counter(ifp, IFCOUNTER_OBYTES, tx_bytes); 1148 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tx_pkts); 1149 1150 return (0); 1151 } 1152 1153 /* 1154 * Reconcile kernel and user view of the receive ring. 1155 * Same as for the txsync, this routine must be efficient. 1156 * The caller guarantees a single invocations, but races against 1157 * the rest of the driver should be handled here. 1158 * 1159 * On call, kring->rhead is the first packet that userspace wants 1160 * to keep, and kring->rcur is the wakeup point. 1161 * The kernel has previously reported packets up to kring->rtail. 1162 * 1163 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1164 * of whether or not we received an interrupt. 1165 */ 1166 static int 1167 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1168 { 1169 struct netmap_adapter *na = kring->na; 1170 struct netmap_ring *ring = kring->ring; 1171 if_t ifp = na->ifp; 1172 uint32_t nm_i; /* index into the netmap ring */ 1173 uint32_t nic_i; /* index into the NIC ring */ 1174 u_int n; 1175 u_int const lim = kring->nkr_num_slots - 1; 1176 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1177 int i = 0, rx_bytes = 0, rx_pkts = 0; 1178 1179 if_ctx_t ctx = if_getsoftc(ifp); 1180 if_shared_ctx_t sctx = ctx->ifc_sctx; 1181 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1182 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1183 iflib_fl_t fl = &rxq->ifr_fl[0]; 1184 struct if_rxd_info ri; 1185 qidx_t *cidxp; 1186 1187 /* 1188 * netmap only uses free list 0, to avoid out of order consumption 1189 * of receive buffers 1190 */ 1191 1192 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1193 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1194 1195 /* 1196 * First part: import newly received packets. 1197 * 1198 * nm_i is the index of the next free slot in the netmap ring, 1199 * nic_i is the index of the next received packet in the NIC ring 1200 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1201 * differ in case if_init() has been called while 1202 * in netmap mode. For the receive ring we have 1203 * 1204 * nic_i = fl->ifl_cidx; 1205 * nm_i = kring->nr_hwtail (previous) 1206 * and 1207 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1208 * 1209 * fl->ifl_cidx is set to 0 on a ring reinit 1210 */ 1211 if (netmap_no_pendintr || force_update) { 1212 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1213 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1214 int crclen = iflib_crcstrip ? 0 : 4; 1215 int error, avail; 1216 1217 /* 1218 * For the free list consumer index, we use the same 1219 * logic as in iflib_rxeof(). 1220 */ 1221 if (have_rxcq) 1222 cidxp = &rxq->ifr_cq_cidx; 1223 else 1224 cidxp = &fl->ifl_cidx; 1225 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1226 rxq->ifr_id, *cidxp, USHRT_MAX); 1227 1228 nic_i = fl->ifl_cidx; 1229 nm_i = netmap_idx_n2k(kring, nic_i); 1230 MPASS(nm_i == kring->nr_hwtail); 1231 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1232 memset(&ri, 0, sizeof(ri)); 1233 ri.iri_frags = rxq->ifr_frags; 1234 ri.iri_qsidx = kring->ring_id; 1235 ri.iri_ifp = ctx->ifc_ifp; 1236 ri.iri_cidx = *cidxp; 1237 1238 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1239 for (i = 0; i < ri.iri_nfrags; i++) { 1240 if (error) { 1241 ring->slot[nm_i].len = 0; 1242 ring->slot[nm_i].flags = 0; 1243 } else { 1244 ring->slot[nm_i].len = ri.iri_frags[i].irf_len; 1245 if (i == (ri.iri_nfrags - 1)) { 1246 ring->slot[nm_i].len -= crclen; 1247 ring->slot[nm_i].flags = 0; 1248 1249 /* Update receive counters */ 1250 rx_bytes += ri.iri_len; 1251 rx_pkts++; 1252 } else 1253 ring->slot[nm_i].flags = NS_MOREFRAG; 1254 } 1255 1256 bus_dmamap_sync(fl->ifl_buf_tag, 1257 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1258 nm_i = nm_next(nm_i, lim); 1259 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1260 } 1261 1262 if (have_rxcq) { 1263 *cidxp = ri.iri_cidx; 1264 while (*cidxp >= scctx->isc_nrxd[0]) 1265 *cidxp -= scctx->isc_nrxd[0]; 1266 } 1267 1268 } 1269 if (n) { /* update the state variables */ 1270 if (netmap_no_pendintr && !force_update) { 1271 /* diagnostics */ 1272 iflib_rx_miss++; 1273 iflib_rx_miss_bufs += n; 1274 } 1275 kring->nr_hwtail = nm_i; 1276 } 1277 kring->nr_kflags &= ~NKR_PENDINTR; 1278 } 1279 /* 1280 * Second part: skip past packets that userspace has released. 1281 * (kring->nr_hwcur to head excluded), 1282 * and make the buffers available for reception. 1283 * As usual nm_i is the index in the netmap ring, 1284 * nic_i is the index in the NIC ring, and 1285 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1286 */ 1287 netmap_fl_refill(rxq, kring, false); 1288 1289 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 1290 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 1291 1292 return (0); 1293 } 1294 1295 static void 1296 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1297 { 1298 if_ctx_t ctx = if_getsoftc(na->ifp); 1299 1300 CTX_LOCK(ctx); 1301 if (onoff) { 1302 IFDI_INTR_ENABLE(ctx); 1303 } else { 1304 IFDI_INTR_DISABLE(ctx); 1305 } 1306 CTX_UNLOCK(ctx); 1307 } 1308 1309 static int 1310 iflib_netmap_attach(if_ctx_t ctx) 1311 { 1312 struct netmap_adapter na; 1313 1314 bzero(&na, sizeof(na)); 1315 1316 na.ifp = ctx->ifc_ifp; 1317 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS; 1318 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1319 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1320 1321 na.num_tx_desc = iflib_num_tx_descs(ctx); 1322 na.num_rx_desc = iflib_num_rx_descs(ctx); 1323 na.nm_txsync = iflib_netmap_txsync; 1324 na.nm_rxsync = iflib_netmap_rxsync; 1325 na.nm_register = iflib_netmap_register; 1326 na.nm_intr = iflib_netmap_intr; 1327 na.nm_config = iflib_netmap_config; 1328 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1329 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1330 return (netmap_attach(&na)); 1331 } 1332 1333 static int 1334 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1335 { 1336 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1337 struct netmap_slot *slot; 1338 1339 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1340 if (slot == NULL) 1341 return (0); 1342 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1343 /* 1344 * In netmap mode, set the map for the packet buffer. 1345 * NOTE: Some drivers (not this one) also need to set 1346 * the physical buffer address in the NIC ring. 1347 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1348 * netmap slot index, si 1349 */ 1350 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1351 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1352 NMB(na, slot + si)); 1353 } 1354 return (1); 1355 } 1356 1357 static int 1358 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1359 { 1360 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1361 struct netmap_kring *kring; 1362 struct netmap_slot *slot; 1363 1364 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1365 if (slot == NULL) 1366 return (0); 1367 kring = na->rx_rings[rxq->ifr_id]; 1368 netmap_fl_refill(rxq, kring, true); 1369 return (1); 1370 } 1371 1372 static void 1373 iflib_netmap_timer(void *arg) 1374 { 1375 iflib_txq_t txq = arg; 1376 if_ctx_t ctx = txq->ift_ctx; 1377 1378 /* 1379 * Wake up the netmap application, to give it a chance to 1380 * call txsync and reclaim more completed TX buffers. 1381 */ 1382 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1383 } 1384 1385 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1386 1387 #else 1388 #define iflib_netmap_txq_init(ctx, txq) (0) 1389 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1390 #define iflib_netmap_detach(ifp) 1391 #define netmap_enable_all_rings(ifp) 1392 #define netmap_disable_all_rings(ifp) 1393 1394 #define iflib_netmap_attach(ctx) (0) 1395 #define netmap_rx_irq(ifp, qid, budget) (0) 1396 #endif 1397 1398 #if defined(__i386__) || defined(__amd64__) 1399 static __inline void 1400 prefetch(void *x) 1401 { 1402 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1403 } 1404 1405 static __inline void 1406 prefetch2cachelines(void *x) 1407 { 1408 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1409 #if (CACHE_LINE_SIZE < 128) 1410 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x) + CACHE_LINE_SIZE / (sizeof(unsigned long))))); 1411 #endif 1412 } 1413 #else 1414 static __inline void 1415 prefetch(void *x) 1416 { 1417 } 1418 1419 static __inline void 1420 prefetch2cachelines(void *x) 1421 { 1422 } 1423 #endif 1424 1425 static void 1426 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1427 { 1428 iflib_fl_t fl; 1429 1430 fl = &rxq->ifr_fl[flid]; 1431 iru->iru_paddrs = fl->ifl_bus_addrs; 1432 iru->iru_idxs = fl->ifl_rxd_idxs; 1433 iru->iru_qsidx = rxq->ifr_id; 1434 iru->iru_buf_size = fl->ifl_buf_size; 1435 iru->iru_flidx = fl->ifl_id; 1436 } 1437 1438 static void 1439 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1440 { 1441 if (err) 1442 return; 1443 *(bus_addr_t *) arg = segs[0].ds_addr; 1444 } 1445 1446 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \ 1447 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \ 1448 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL) 1449 1450 int 1451 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1452 { 1453 int err; 1454 device_t dev = ctx->ifc_dev; 1455 bus_addr_t lowaddr; 1456 1457 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width); 1458 1459 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1460 align, 0, /* alignment, bounds */ 1461 lowaddr, /* lowaddr */ 1462 BUS_SPACE_MAXADDR, /* highaddr */ 1463 NULL, NULL, /* filter, filterarg */ 1464 size, /* maxsize */ 1465 1, /* nsegments */ 1466 size, /* maxsegsize */ 1467 BUS_DMA_ALLOCNOW, /* flags */ 1468 NULL, /* lockfunc */ 1469 NULL, /* lockarg */ 1470 &dma->idi_tag); 1471 if (err) { 1472 device_printf(dev, 1473 "%s: bus_dma_tag_create failed: %d (size=%d, align=%d)\n", 1474 __func__, err, size, align); 1475 goto fail_0; 1476 } 1477 1478 err = bus_dmamem_alloc(dma->idi_tag, (void **)&dma->idi_vaddr, 1479 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1480 if (err) { 1481 device_printf(dev, 1482 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1483 __func__, (uintmax_t)size, err); 1484 goto fail_1; 1485 } 1486 1487 dma->idi_paddr = IF_BAD_DMA; 1488 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1489 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1490 if (err || dma->idi_paddr == IF_BAD_DMA) { 1491 device_printf(dev, 1492 "%s: bus_dmamap_load failed: %d\n", 1493 __func__, err); 1494 goto fail_2; 1495 } 1496 1497 dma->idi_size = size; 1498 return (0); 1499 1500 fail_2: 1501 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1502 fail_1: 1503 bus_dma_tag_destroy(dma->idi_tag); 1504 fail_0: 1505 dma->idi_tag = NULL; 1506 1507 return (err); 1508 } 1509 1510 int 1511 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1512 { 1513 if_shared_ctx_t sctx = ctx->ifc_sctx; 1514 1515 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1516 1517 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1518 } 1519 1520 int 1521 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1522 { 1523 int i, err; 1524 iflib_dma_info_t *dmaiter; 1525 1526 dmaiter = dmalist; 1527 for (i = 0; i < count; i++, dmaiter++) { 1528 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1529 break; 1530 } 1531 if (err) 1532 iflib_dma_free_multi(dmalist, i); 1533 return (err); 1534 } 1535 1536 void 1537 iflib_dma_free(iflib_dma_info_t dma) 1538 { 1539 if (dma->idi_tag == NULL) 1540 return; 1541 if (dma->idi_paddr != IF_BAD_DMA) { 1542 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1543 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1544 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1545 dma->idi_paddr = IF_BAD_DMA; 1546 } 1547 if (dma->idi_vaddr != NULL) { 1548 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1549 dma->idi_vaddr = NULL; 1550 } 1551 bus_dma_tag_destroy(dma->idi_tag); 1552 dma->idi_tag = NULL; 1553 } 1554 1555 void 1556 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1557 { 1558 int i; 1559 iflib_dma_info_t *dmaiter = dmalist; 1560 1561 for (i = 0; i < count; i++, dmaiter++) 1562 iflib_dma_free(*dmaiter); 1563 } 1564 1565 static int 1566 iflib_fast_intr(void *arg) 1567 { 1568 iflib_filter_info_t info = arg; 1569 struct grouptask *gtask = info->ifi_task; 1570 int result; 1571 1572 DBG_COUNTER_INC(fast_intrs); 1573 if (info->ifi_filter != NULL) { 1574 result = info->ifi_filter(info->ifi_filter_arg); 1575 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1576 return (result); 1577 } 1578 1579 GROUPTASK_ENQUEUE(gtask); 1580 return (FILTER_HANDLED); 1581 } 1582 1583 static int 1584 iflib_fast_intr_rxtx(void *arg) 1585 { 1586 iflib_filter_info_t info = arg; 1587 struct grouptask *gtask = info->ifi_task; 1588 if_ctx_t ctx; 1589 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1590 iflib_txq_t txq; 1591 void *sc; 1592 int i, cidx, result; 1593 qidx_t txqid; 1594 bool intr_enable, intr_legacy; 1595 1596 DBG_COUNTER_INC(fast_intrs); 1597 if (info->ifi_filter != NULL) { 1598 result = info->ifi_filter(info->ifi_filter_arg); 1599 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1600 return (result); 1601 } 1602 1603 ctx = rxq->ifr_ctx; 1604 sc = ctx->ifc_softc; 1605 intr_enable = false; 1606 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1607 MPASS(rxq->ifr_ntxqirq); 1608 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1609 txqid = rxq->ifr_txqid[i]; 1610 txq = &ctx->ifc_txqs[txqid]; 1611 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1612 BUS_DMASYNC_POSTREAD); 1613 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1614 if (intr_legacy) 1615 intr_enable = true; 1616 else 1617 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1618 continue; 1619 } 1620 GROUPTASK_ENQUEUE(&txq->ift_task); 1621 } 1622 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1623 cidx = rxq->ifr_cq_cidx; 1624 else 1625 cidx = rxq->ifr_fl[0].ifl_cidx; 1626 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1627 GROUPTASK_ENQUEUE(gtask); 1628 else { 1629 if (intr_legacy) 1630 intr_enable = true; 1631 else 1632 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1633 DBG_COUNTER_INC(rx_intr_enables); 1634 } 1635 if (intr_enable) 1636 IFDI_INTR_ENABLE(ctx); 1637 return (FILTER_HANDLED); 1638 } 1639 1640 static int 1641 iflib_fast_intr_ctx(void *arg) 1642 { 1643 iflib_filter_info_t info = arg; 1644 if_ctx_t ctx = info->ifi_ctx; 1645 int result; 1646 1647 DBG_COUNTER_INC(fast_intrs); 1648 if (info->ifi_filter != NULL) { 1649 result = info->ifi_filter(info->ifi_filter_arg); 1650 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1651 return (result); 1652 } 1653 1654 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_admin_task); 1655 return (FILTER_HANDLED); 1656 } 1657 1658 static int 1659 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1660 driver_filter_t filter, driver_intr_t handler, void *arg, 1661 const char *name) 1662 { 1663 struct resource *res; 1664 void *tag = NULL; 1665 device_t dev = ctx->ifc_dev; 1666 int flags, i, rc; 1667 1668 flags = RF_ACTIVE; 1669 if (ctx->ifc_flags & IFC_LEGACY) 1670 flags |= RF_SHAREABLE; 1671 MPASS(rid < 512); 1672 i = rid; 1673 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1674 if (res == NULL) { 1675 device_printf(dev, 1676 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1677 return (ENOMEM); 1678 } 1679 irq->ii_res = res; 1680 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1681 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1682 filter, handler, arg, &tag); 1683 if (rc != 0) { 1684 device_printf(dev, 1685 "failed to setup interrupt for rid %d, name %s: %d\n", 1686 rid, name ? name : "unknown", rc); 1687 return (rc); 1688 } else if (name) 1689 bus_describe_intr(dev, res, tag, "%s", name); 1690 1691 irq->ii_tag = tag; 1692 return (0); 1693 } 1694 1695 /********************************************************************* 1696 * 1697 * Allocate DMA resources for TX buffers as well as memory for the TX 1698 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1699 * iflib_sw_tx_desc_array structure, storing all the information that 1700 * is needed to transmit a packet on the wire. This is called only 1701 * once at attach, setup is done every reset. 1702 * 1703 **********************************************************************/ 1704 static int 1705 iflib_txsd_alloc(iflib_txq_t txq) 1706 { 1707 if_ctx_t ctx = txq->ift_ctx; 1708 if_shared_ctx_t sctx = ctx->ifc_sctx; 1709 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1710 device_t dev = ctx->ifc_dev; 1711 bus_size_t tsomaxsize; 1712 bus_addr_t lowaddr; 1713 int err, nsegments, ntsosegments; 1714 bool tso; 1715 1716 nsegments = scctx->isc_tx_nsegments; 1717 ntsosegments = scctx->isc_tx_tso_segments_max; 1718 tsomaxsize = scctx->isc_tx_tso_size_max; 1719 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1720 tsomaxsize += sizeof(struct ether_vlan_header); 1721 MPASS(scctx->isc_ntxd[0] > 0); 1722 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1723 MPASS(nsegments > 0); 1724 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1725 MPASS(ntsosegments > 0); 1726 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1727 } 1728 1729 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1730 1731 /* 1732 * Set up DMA tags for TX buffers. 1733 */ 1734 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1735 1, 0, /* alignment, bounds */ 1736 lowaddr, /* lowaddr */ 1737 BUS_SPACE_MAXADDR, /* highaddr */ 1738 NULL, NULL, /* filter, filterarg */ 1739 sctx->isc_tx_maxsize, /* maxsize */ 1740 nsegments, /* nsegments */ 1741 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1742 0, /* flags */ 1743 NULL, /* lockfunc */ 1744 NULL, /* lockfuncarg */ 1745 &txq->ift_buf_tag))) { 1746 device_printf(dev, "Unable to allocate TX DMA tag: %d\n", err); 1747 device_printf(dev, "maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1748 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1749 goto fail; 1750 } 1751 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1752 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1753 1, 0, /* alignment, bounds */ 1754 lowaddr, /* lowaddr */ 1755 BUS_SPACE_MAXADDR, /* highaddr */ 1756 NULL, NULL, /* filter, filterarg */ 1757 tsomaxsize, /* maxsize */ 1758 ntsosegments, /* nsegments */ 1759 sctx->isc_tso_maxsegsize, /* maxsegsize */ 1760 0, /* flags */ 1761 NULL, /* lockfunc */ 1762 NULL, /* lockfuncarg */ 1763 &txq->ift_tso_buf_tag))) { 1764 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1765 err); 1766 goto fail; 1767 } 1768 1769 /* Allocate memory for the TX mbuf map. */ 1770 if (!(txq->ift_sds.ifsd_m = 1771 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1772 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1773 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1774 err = ENOMEM; 1775 goto fail; 1776 } 1777 if (ctx->ifc_sysctl_simple_tx) { 1778 if (!(txq->ift_sds.ifsd_m_defer = 1779 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1780 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1781 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1782 err = ENOMEM; 1783 goto fail; 1784 } 1785 } 1786 txq->ift_sds.ifsd_m_deferb = txq->ift_sds.ifsd_m_defer; 1787 /* 1788 * Create the DMA maps for TX buffers. 1789 */ 1790 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1791 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1792 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1793 device_printf(dev, 1794 "Unable to allocate TX buffer DMA map memory\n"); 1795 err = ENOMEM; 1796 goto fail; 1797 } 1798 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1799 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1800 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1801 device_printf(dev, 1802 "Unable to allocate TSO TX buffer map memory\n"); 1803 err = ENOMEM; 1804 goto fail; 1805 } 1806 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1807 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1808 &txq->ift_sds.ifsd_map[i]); 1809 if (err != 0) { 1810 device_printf(dev, "Unable to create TX DMA map\n"); 1811 goto fail; 1812 } 1813 if (!tso) 1814 continue; 1815 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1816 &txq->ift_sds.ifsd_tso_map[i]); 1817 if (err != 0) { 1818 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1819 goto fail; 1820 } 1821 } 1822 return (0); 1823 fail: 1824 /* We free all, it handles case where we are in the middle */ 1825 iflib_tx_structures_free(ctx); 1826 return (err); 1827 } 1828 1829 static void 1830 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1831 { 1832 bus_dmamap_t map; 1833 1834 if (txq->ift_sds.ifsd_map != NULL) { 1835 map = txq->ift_sds.ifsd_map[i]; 1836 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1837 bus_dmamap_unload(txq->ift_buf_tag, map); 1838 bus_dmamap_destroy(txq->ift_buf_tag, map); 1839 txq->ift_sds.ifsd_map[i] = NULL; 1840 } 1841 1842 if (txq->ift_sds.ifsd_tso_map != NULL) { 1843 map = txq->ift_sds.ifsd_tso_map[i]; 1844 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1845 BUS_DMASYNC_POSTWRITE); 1846 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1847 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1848 txq->ift_sds.ifsd_tso_map[i] = NULL; 1849 } 1850 } 1851 1852 static void 1853 iflib_txq_destroy(iflib_txq_t txq) 1854 { 1855 if_ctx_t ctx = txq->ift_ctx; 1856 1857 for (int i = 0; i < txq->ift_size; i++) 1858 iflib_txsd_destroy(ctx, txq, i); 1859 1860 if (txq->ift_br != NULL) { 1861 ifmp_ring_free(txq->ift_br); 1862 txq->ift_br = NULL; 1863 } 1864 1865 mtx_destroy(&txq->ift_mtx); 1866 1867 if (txq->ift_sds.ifsd_map != NULL) { 1868 free(txq->ift_sds.ifsd_map, M_IFLIB); 1869 txq->ift_sds.ifsd_map = NULL; 1870 } 1871 if (txq->ift_sds.ifsd_tso_map != NULL) { 1872 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1873 txq->ift_sds.ifsd_tso_map = NULL; 1874 } 1875 if (txq->ift_sds.ifsd_m != NULL) { 1876 free(txq->ift_sds.ifsd_m, M_IFLIB); 1877 txq->ift_sds.ifsd_m = NULL; 1878 } 1879 if (txq->ift_sds.ifsd_m_defer != NULL) { 1880 free(txq->ift_sds.ifsd_m_defer, M_IFLIB); 1881 txq->ift_sds.ifsd_m_defer = NULL; 1882 } 1883 if (txq->ift_buf_tag != NULL) { 1884 bus_dma_tag_destroy(txq->ift_buf_tag); 1885 txq->ift_buf_tag = NULL; 1886 } 1887 if (txq->ift_tso_buf_tag != NULL) { 1888 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1889 txq->ift_tso_buf_tag = NULL; 1890 } 1891 if (txq->ift_ifdi != NULL) { 1892 free(txq->ift_ifdi, M_IFLIB); 1893 } 1894 } 1895 1896 static void 1897 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1898 { 1899 struct mbuf *m; 1900 1901 m = IFLIB_GET_MBUF(txq->ift_sds.ifsd_m[i]); 1902 if (m == NULL) 1903 return; 1904 1905 if (txq->ift_sds.ifsd_map != NULL) { 1906 bus_dmamap_sync(txq->ift_buf_tag, 1907 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1908 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1909 } 1910 if (txq->ift_sds.ifsd_tso_map != NULL) { 1911 bus_dmamap_sync(txq->ift_tso_buf_tag, 1912 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1913 bus_dmamap_unload(txq->ift_tso_buf_tag, 1914 txq->ift_sds.ifsd_tso_map[i]); 1915 } 1916 txq->ift_sds.ifsd_m[i] = NULL; 1917 m_freem(m); 1918 DBG_COUNTER_INC(tx_frees); 1919 } 1920 1921 static int 1922 iflib_txq_setup(iflib_txq_t txq) 1923 { 1924 if_ctx_t ctx = txq->ift_ctx; 1925 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1926 if_shared_ctx_t sctx = ctx->ifc_sctx; 1927 iflib_dma_info_t di; 1928 int i; 1929 1930 /* XXX make configurable */ 1931 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1932 1933 /* Reset indices */ 1934 txq->ift_cidx_processed = 0; 1935 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1936 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1937 txq->ift_pad = scctx->isc_tx_pad; 1938 1939 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1940 bzero((void *)di->idi_vaddr, di->idi_size); 1941 1942 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1943 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1944 bus_dmamap_sync(di->idi_tag, di->idi_map, 1945 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1946 return (0); 1947 } 1948 1949 /********************************************************************* 1950 * 1951 * Allocate DMA resources for RX buffers as well as memory for the RX 1952 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1953 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1954 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1955 * Since we use use one entry in iflib_sw_rx_desc_array per received 1956 * packet, the maximum number of entries we'll need is equal to the 1957 * number of hardware receive descriptors that we've allocated. 1958 * 1959 **********************************************************************/ 1960 static int 1961 iflib_rxsd_alloc(iflib_rxq_t rxq) 1962 { 1963 if_ctx_t ctx = rxq->ifr_ctx; 1964 if_shared_ctx_t sctx = ctx->ifc_sctx; 1965 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1966 device_t dev = ctx->ifc_dev; 1967 iflib_fl_t fl; 1968 bus_addr_t lowaddr; 1969 int err; 1970 1971 MPASS(scctx->isc_nrxd[0] > 0); 1972 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1973 1974 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1975 1976 fl = rxq->ifr_fl; 1977 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1978 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1979 /* Set up DMA tag for RX buffers. */ 1980 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1981 1, 0, /* alignment, bounds */ 1982 lowaddr, /* lowaddr */ 1983 BUS_SPACE_MAXADDR, /* highaddr */ 1984 NULL, NULL, /* filter, filterarg */ 1985 sctx->isc_rx_maxsize, /* maxsize */ 1986 sctx->isc_rx_nsegments, /* nsegments */ 1987 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1988 0, /* flags */ 1989 NULL, /* lockfunc */ 1990 NULL, /* lockarg */ 1991 &fl->ifl_buf_tag); 1992 if (err) { 1993 device_printf(dev, 1994 "Unable to allocate RX DMA tag: %d\n", err); 1995 goto fail; 1996 } 1997 1998 /* Allocate memory for the RX mbuf map. */ 1999 if (!(fl->ifl_sds.ifsd_m = 2000 (struct mbuf **) malloc(sizeof(struct mbuf *) * 2001 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2002 device_printf(dev, 2003 "Unable to allocate RX mbuf map memory\n"); 2004 err = ENOMEM; 2005 goto fail; 2006 } 2007 2008 /* Allocate memory for the direct RX cluster pointer map. */ 2009 if (!(fl->ifl_sds.ifsd_cl = 2010 (caddr_t *) malloc(sizeof(caddr_t) * 2011 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2012 device_printf(dev, 2013 "Unable to allocate RX cluster map memory\n"); 2014 err = ENOMEM; 2015 goto fail; 2016 } 2017 2018 /* Allocate memory for the RX cluster bus address map. */ 2019 if (!(fl->ifl_sds.ifsd_ba = 2020 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 2021 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2022 device_printf(dev, 2023 "Unable to allocate RX bus address map memory\n"); 2024 err = ENOMEM; 2025 goto fail; 2026 } 2027 2028 /* 2029 * Create the DMA maps for RX buffers. 2030 */ 2031 if (!(fl->ifl_sds.ifsd_map = 2032 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2033 device_printf(dev, 2034 "Unable to allocate RX buffer DMA map memory\n"); 2035 err = ENOMEM; 2036 goto fail; 2037 } 2038 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 2039 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 2040 &fl->ifl_sds.ifsd_map[i]); 2041 if (err != 0) { 2042 device_printf(dev, "Unable to create RX buffer DMA map\n"); 2043 goto fail; 2044 } 2045 } 2046 } 2047 return (0); 2048 2049 fail: 2050 iflib_rx_structures_free(ctx); 2051 return (err); 2052 } 2053 2054 /* 2055 * Internal service routines 2056 */ 2057 2058 struct rxq_refill_cb_arg { 2059 int error; 2060 bus_dma_segment_t seg; 2061 int nseg; 2062 }; 2063 2064 static void 2065 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2066 { 2067 struct rxq_refill_cb_arg *cb_arg = arg; 2068 2069 cb_arg->error = error; 2070 cb_arg->seg = segs[0]; 2071 cb_arg->nseg = nseg; 2072 } 2073 2074 /** 2075 * iflib_fl_refill - refill an rxq free-buffer list 2076 * @ctx: the iflib context 2077 * @fl: the free list to refill 2078 * @count: the number of new buffers to allocate 2079 * 2080 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 2081 * The caller must assure that @count does not exceed the queue's capacity 2082 * minus one (since we always leave a descriptor unavailable). 2083 */ 2084 static uint8_t 2085 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 2086 { 2087 struct if_rxd_update iru; 2088 struct rxq_refill_cb_arg cb_arg; 2089 struct mbuf *m; 2090 caddr_t cl, *sd_cl; 2091 struct mbuf **sd_m; 2092 bus_dmamap_t *sd_map; 2093 bus_addr_t bus_addr, *sd_ba; 2094 int err, frag_idx, i, idx, n, pidx; 2095 qidx_t credits; 2096 2097 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 2098 2099 sd_m = fl->ifl_sds.ifsd_m; 2100 sd_map = fl->ifl_sds.ifsd_map; 2101 sd_cl = fl->ifl_sds.ifsd_cl; 2102 sd_ba = fl->ifl_sds.ifsd_ba; 2103 pidx = fl->ifl_pidx; 2104 idx = pidx; 2105 frag_idx = fl->ifl_fragidx; 2106 credits = fl->ifl_credits; 2107 2108 i = 0; 2109 n = count; 2110 MPASS(n > 0); 2111 MPASS(credits + n <= fl->ifl_size); 2112 2113 if (pidx < fl->ifl_cidx) 2114 MPASS(pidx + n <= fl->ifl_cidx); 2115 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 2116 MPASS(fl->ifl_gen == 0); 2117 if (pidx > fl->ifl_cidx) 2118 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 2119 2120 DBG_COUNTER_INC(fl_refills); 2121 if (n > 8) 2122 DBG_COUNTER_INC(fl_refills_large); 2123 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 2124 while (n-- > 0) { 2125 /* 2126 * We allocate an uninitialized mbuf + cluster, mbuf is 2127 * initialized after rx. 2128 * 2129 * If the cluster is still set then we know a minimum sized 2130 * packet was received 2131 */ 2132 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2133 &frag_idx); 2134 if (frag_idx < 0) 2135 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2136 MPASS(frag_idx >= 0); 2137 if ((cl = sd_cl[frag_idx]) == NULL) { 2138 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2139 if (__predict_false(cl == NULL)) 2140 break; 2141 2142 cb_arg.error = 0; 2143 MPASS(sd_map != NULL); 2144 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2145 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2146 BUS_DMA_NOWAIT); 2147 if (__predict_false(err != 0 || cb_arg.error)) { 2148 uma_zfree(fl->ifl_zone, cl); 2149 break; 2150 } 2151 2152 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2153 sd_cl[frag_idx] = cl; 2154 #if MEMORY_LOGGING 2155 fl->ifl_cl_enqueued++; 2156 #endif 2157 } else { 2158 bus_addr = sd_ba[frag_idx]; 2159 } 2160 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2161 BUS_DMASYNC_PREREAD); 2162 2163 if (sd_m[frag_idx] == NULL) { 2164 m = m_gethdr_raw(M_NOWAIT, 0); 2165 if (__predict_false(m == NULL)) 2166 break; 2167 sd_m[frag_idx] = m; 2168 } 2169 bit_set(fl->ifl_rx_bitmap, frag_idx); 2170 #if MEMORY_LOGGING 2171 fl->ifl_m_enqueued++; 2172 #endif 2173 2174 DBG_COUNTER_INC(rx_allocs); 2175 fl->ifl_rxd_idxs[i] = frag_idx; 2176 fl->ifl_bus_addrs[i] = bus_addr; 2177 credits++; 2178 i++; 2179 MPASS(credits <= fl->ifl_size); 2180 if (++idx == fl->ifl_size) { 2181 #ifdef INVARIANTS 2182 fl->ifl_gen = 1; 2183 #endif 2184 idx = 0; 2185 } 2186 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2187 iru.iru_pidx = pidx; 2188 iru.iru_count = i; 2189 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2190 fl->ifl_pidx = idx; 2191 fl->ifl_credits = credits; 2192 pidx = idx; 2193 i = 0; 2194 } 2195 } 2196 2197 if (n < count - 1) { 2198 if (i != 0) { 2199 iru.iru_pidx = pidx; 2200 iru.iru_count = i; 2201 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2202 fl->ifl_pidx = idx; 2203 fl->ifl_credits = credits; 2204 } 2205 DBG_COUNTER_INC(rxd_flush); 2206 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2207 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2208 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2209 fl->ifl_id, fl->ifl_pidx); 2210 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2211 fl->ifl_fragidx = frag_idx + 1; 2212 if (fl->ifl_fragidx == fl->ifl_size) 2213 fl->ifl_fragidx = 0; 2214 } else { 2215 fl->ifl_fragidx = frag_idx; 2216 } 2217 } 2218 2219 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2220 } 2221 2222 static inline uint8_t 2223 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2224 { 2225 /* 2226 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2227 * This is important as it confuses most NICs. For instance, 2228 * Intel NICs have (per receive ring) RDH and RDT registers, where 2229 * RDH points to the next receive descriptor to be used by the NIC, 2230 * and RDT for the next receive descriptor to be published by the 2231 * driver to the NIC (RDT - 1 is thus the last valid one). 2232 * The condition RDH == RDT means no descriptors are available to 2233 * the NIC, and thus it would be ambiguous if it also meant that 2234 * all the descriptors are available to the NIC. 2235 */ 2236 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2237 #ifdef INVARIANTS 2238 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2239 #endif 2240 2241 MPASS(fl->ifl_credits <= fl->ifl_size); 2242 MPASS(reclaimable == delta); 2243 2244 if (reclaimable > 0) 2245 return (iflib_fl_refill(ctx, fl, reclaimable)); 2246 return (0); 2247 } 2248 2249 uint8_t 2250 iflib_in_detach(if_ctx_t ctx) 2251 { 2252 bool in_detach; 2253 2254 STATE_LOCK(ctx); 2255 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2256 STATE_UNLOCK(ctx); 2257 return (in_detach); 2258 } 2259 2260 static void 2261 iflib_fl_bufs_free(iflib_fl_t fl) 2262 { 2263 iflib_dma_info_t idi = fl->ifl_ifdi; 2264 bus_dmamap_t sd_map; 2265 uint32_t i; 2266 2267 for (i = 0; i < fl->ifl_size; i++) { 2268 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2269 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2270 2271 if (*sd_cl != NULL) { 2272 sd_map = fl->ifl_sds.ifsd_map[i]; 2273 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2274 BUS_DMASYNC_POSTREAD); 2275 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2276 uma_zfree(fl->ifl_zone, *sd_cl); 2277 *sd_cl = NULL; 2278 if (*sd_m != NULL) { 2279 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2280 m_free_raw(*sd_m); 2281 *sd_m = NULL; 2282 } 2283 } else { 2284 MPASS(*sd_m == NULL); 2285 } 2286 #if MEMORY_LOGGING 2287 fl->ifl_m_dequeued++; 2288 fl->ifl_cl_dequeued++; 2289 #endif 2290 } 2291 #ifdef INVARIANTS 2292 for (i = 0; i < fl->ifl_size; i++) { 2293 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2294 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2295 } 2296 #endif 2297 /* 2298 * Reset free list values 2299 */ 2300 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2301 bzero(idi->idi_vaddr, idi->idi_size); 2302 } 2303 2304 /********************************************************************* 2305 * 2306 * Initialize a free list and its buffers. 2307 * 2308 **********************************************************************/ 2309 static int 2310 iflib_fl_setup(iflib_fl_t fl) 2311 { 2312 iflib_rxq_t rxq = fl->ifl_rxq; 2313 if_ctx_t ctx = rxq->ifr_ctx; 2314 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2315 int qidx; 2316 2317 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2318 /* 2319 * Free current RX buffer structs and their mbufs 2320 */ 2321 iflib_fl_bufs_free(fl); 2322 /* Now replenish the mbufs */ 2323 MPASS(fl->ifl_credits == 0); 2324 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2325 if (scctx->isc_rxd_buf_size[qidx] != 0) 2326 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2327 else 2328 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2329 /* 2330 * ifl_buf_size may be a driver-supplied value, so pull it up 2331 * to the selected mbuf size. 2332 */ 2333 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2334 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2335 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2336 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2337 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2338 2339 /* 2340 * Avoid pre-allocating zillions of clusters to an idle card 2341 * potentially speeding up attach. In any case make sure 2342 * to leave a descriptor unavailable. See the comment in 2343 * iflib_fl_refill_all(). 2344 */ 2345 MPASS(fl->ifl_size > 0); 2346 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2347 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2348 return (ENOBUFS); 2349 /* 2350 * handle failure 2351 */ 2352 MPASS(rxq != NULL); 2353 MPASS(fl->ifl_ifdi != NULL); 2354 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2355 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2356 return (0); 2357 } 2358 2359 /********************************************************************* 2360 * 2361 * Free receive ring data structures 2362 * 2363 **********************************************************************/ 2364 static void 2365 iflib_rx_sds_free(iflib_rxq_t rxq) 2366 { 2367 iflib_fl_t fl; 2368 int i, j; 2369 2370 if (rxq->ifr_fl != NULL) { 2371 for (i = 0; i < rxq->ifr_nfl; i++) { 2372 fl = &rxq->ifr_fl[i]; 2373 if (fl->ifl_buf_tag != NULL) { 2374 if (fl->ifl_sds.ifsd_map != NULL) { 2375 for (j = 0; j < fl->ifl_size; j++) { 2376 bus_dmamap_sync( 2377 fl->ifl_buf_tag, 2378 fl->ifl_sds.ifsd_map[j], 2379 BUS_DMASYNC_POSTREAD); 2380 bus_dmamap_unload( 2381 fl->ifl_buf_tag, 2382 fl->ifl_sds.ifsd_map[j]); 2383 bus_dmamap_destroy( 2384 fl->ifl_buf_tag, 2385 fl->ifl_sds.ifsd_map[j]); 2386 } 2387 } 2388 bus_dma_tag_destroy(fl->ifl_buf_tag); 2389 fl->ifl_buf_tag = NULL; 2390 } 2391 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2392 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2393 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2394 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2395 free(fl->ifl_rx_bitmap, M_IFLIB); 2396 fl->ifl_sds.ifsd_m = NULL; 2397 fl->ifl_sds.ifsd_cl = NULL; 2398 fl->ifl_sds.ifsd_ba = NULL; 2399 fl->ifl_sds.ifsd_map = NULL; 2400 fl->ifl_rx_bitmap = NULL; 2401 } 2402 free(rxq->ifr_fl, M_IFLIB); 2403 rxq->ifr_fl = NULL; 2404 free(rxq->ifr_ifdi, M_IFLIB); 2405 rxq->ifr_ifdi = NULL; 2406 rxq->ifr_cq_cidx = 0; 2407 } 2408 } 2409 2410 /* 2411 * Timer routine 2412 */ 2413 static void 2414 iflib_timer(void *arg) 2415 { 2416 iflib_txq_t txq = arg; 2417 if_ctx_t ctx = txq->ift_ctx; 2418 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2419 uint64_t this_tick = ticks; 2420 2421 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2422 return; 2423 2424 /* 2425 * Check on the state of the TX queue(s); this can be done 2426 * without the lock: the counters the check reads are only 2427 * advanced by the queue's tx task and a stale read just 2428 * delays the verdict by one timer period. 2429 */ 2430 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) { 2431 qidx_t outstanding; 2432 bool frozen; 2433 2434 txq->ift_last_timer_tick = this_tick; 2435 IFDI_TIMER(ctx, txq->ift_id); 2436 2437 /* 2438 * Descriptors the hardware has not reported as 2439 * completed: neither harvested as credits 2440 * (ift_processed) nor reclaimed (ift_cleaned accounts 2441 * the difference to ift_in_use). The tail whose 2442 * report-status request is still deferred is never 2443 * reported and must not count (ift_rs_pending 2444 * over-counts it by one per packet). 2445 */ 2446 outstanding = txq->ift_in_use - 2447 (qidx_t)(txq->ift_processed - txq->ift_cleaned); 2448 2449 /* 2450 * The queue is frozen while it has descriptors the 2451 * hardware has not reported as completed and none 2452 * were reclaimed over the period; the link must be 2453 * up, with no pause frames and no pending doorbell 2454 * (the laggard check below rings it). 2455 * 2456 * Being frozen is not a fault - the hardware may 2457 * defer marking descriptors as completed 2458 * indefinitely, and 8254x hardware does so for a 2459 * quiet queue - therefore the check arms only when a 2460 * frozen queue also takes on new work, and acts only 2461 * once it has stayed frozen for 2462 * net.iflib.tx_watchdog_periods consecutive periods. 2463 */ 2464 frozen = outstanding > txq->ift_rs_pending && 2465 txq->ift_processed == txq->ift_processed_prev && 2466 txq->ift_db_pending == 0 && 2467 sctx->isc_pause_frames == 0 && 2468 ctx->ifc_link_state == LINK_STATE_UP; 2469 if (!frozen) 2470 txq->ift_wdog_armed = 0; 2471 else if (txq->ift_wdog_armed > 0 || 2472 outstanding > txq->ift_outstanding_prev) { 2473 if (txq->ift_wdog_armed < UINT16_MAX) 2474 txq->ift_wdog_armed++; 2475 } 2476 2477 /* 2478 * Frozen long enough: ask the hardware. Completions 2479 * ready but unharvested for this long mean the 2480 * completion interrupt went missing - kick the 2481 * queue's task. Nothing ready, although the queue 2482 * kept taking on work, means it is hung. 2483 */ 2484 if (iflib_tx_watchdog_periods > 0 && 2485 txq->ift_wdog_armed >= iflib_tx_watchdog_periods) { 2486 bus_dmamap_sync(txq->ift_ifdi->idi_tag, 2487 txq->ift_ifdi->idi_map, BUS_DMASYNC_POSTREAD); 2488 if (ctx->isc_txd_credits_update(ctx->ifc_softc, 2489 txq->ift_id, false) == 0) { 2490 device_printf(ctx->ifc_dev, 2491 "Watchdog timeout (TX: %d desc " 2492 "avail: %d pidx: %d) -- resetting\n", 2493 txq->ift_id, TXQ_AVAIL(txq), 2494 txq->ift_pidx); 2495 STATE_LOCK(ctx); 2496 if_setdrvflagbits(ctx->ifc_ifp, 2497 IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2498 ctx->ifc_flags |= 2499 (IFC_DO_WATCHDOG | IFC_DO_RESET); 2500 iflib_admin_intr_deferred(ctx); 2501 STATE_UNLOCK(ctx); 2502 return; 2503 } 2504 GROUPTASK_ENQUEUE(&txq->ift_task); 2505 } 2506 txq->ift_outstanding_prev = outstanding; 2507 txq->ift_processed_prev = txq->ift_processed; 2508 } 2509 /* handle any laggards */ 2510 if (txq->ift_db_pending) 2511 GROUPTASK_ENQUEUE(&txq->ift_task); 2512 2513 sctx->isc_pause_frames = 0; 2514 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2515 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, 2516 txq, txq->ift_timer.c_cpu); 2517 } 2518 2519 static uint16_t 2520 iflib_get_mbuf_size_for(unsigned int size) 2521 { 2522 2523 if (size <= MCLBYTES) 2524 return (MCLBYTES); 2525 else 2526 return (MJUMPAGESIZE); 2527 } 2528 2529 static void 2530 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2531 { 2532 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2533 2534 /* 2535 * XXX don't set the max_frame_size to larger 2536 * than the hardware can handle 2537 */ 2538 ctx->ifc_rx_mbuf_sz = 2539 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2540 } 2541 2542 uint32_t 2543 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2544 { 2545 2546 return (ctx->ifc_rx_mbuf_sz); 2547 } 2548 2549 static void 2550 iflib_init_locked(if_ctx_t ctx) 2551 { 2552 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2553 if_t ifp = ctx->ifc_ifp; 2554 iflib_fl_t fl; 2555 iflib_txq_t txq; 2556 iflib_rxq_t rxq; 2557 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2558 2559 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2560 IFDI_INTR_DISABLE(ctx); 2561 2562 /* 2563 * See iflib_stop(). Useful in case iflib_init_locked() is 2564 * called without first calling iflib_stop(). 2565 */ 2566 netmap_disable_all_rings(ifp); 2567 2568 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2569 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2570 /* Set hardware offload abilities */ 2571 if_clearhwassist(ifp); 2572 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2573 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2574 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2575 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2576 if (if_getcapenable(ifp) & IFCAP_TSO4) 2577 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2578 if (if_getcapenable(ifp) & IFCAP_TSO6) 2579 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2580 2581 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 2582 CALLOUT_LOCK(txq); 2583 callout_stop(&txq->ift_timer); 2584 #ifdef DEV_NETMAP 2585 callout_stop(&txq->ift_netmap_timer); 2586 #endif /* DEV_NETMAP */ 2587 CALLOUT_UNLOCK(txq); 2588 (void)iflib_netmap_txq_init(ctx, txq); 2589 } 2590 2591 /* 2592 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2593 * that drivers can use the value when setting up the hardware receive 2594 * buffers. 2595 */ 2596 iflib_calc_rx_mbuf_sz(ctx); 2597 2598 #ifdef INVARIANTS 2599 i = if_getdrvflags(ifp); 2600 #endif 2601 IFDI_INIT(ctx); 2602 MPASS(if_getdrvflags(ifp) == i); 2603 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 2604 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2605 /* This rxq is in netmap mode. Skip normal init. */ 2606 continue; 2607 } 2608 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2609 if (iflib_fl_setup(fl)) { 2610 device_printf(ctx->ifc_dev, 2611 "setting up free list %d failed - " 2612 "check cluster settings\n", j); 2613 goto done; 2614 } 2615 } 2616 } 2617 done: 2618 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2619 IFDI_INTR_ENABLE(ctx); 2620 txq = ctx->ifc_txqs; 2621 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) 2622 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 2623 txq->ift_timer.c_cpu); 2624 2625 /* Re-enable txsync/rxsync. */ 2626 netmap_enable_all_rings(ifp); 2627 } 2628 2629 static int 2630 iflib_media_change(if_t ifp) 2631 { 2632 if_ctx_t ctx = if_getsoftc(ifp); 2633 int err; 2634 2635 CTX_LOCK(ctx); 2636 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2637 iflib_if_init_locked(ctx); 2638 CTX_UNLOCK(ctx); 2639 return (err); 2640 } 2641 2642 static void 2643 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2644 { 2645 if_ctx_t ctx = if_getsoftc(ifp); 2646 2647 CTX_LOCK(ctx); 2648 IFDI_UPDATE_ADMIN_STATUS(ctx); 2649 IFDI_MEDIA_STATUS(ctx, ifmr); 2650 CTX_UNLOCK(ctx); 2651 } 2652 2653 static void 2654 iflib_stop(if_ctx_t ctx) 2655 { 2656 iflib_txq_t txq = ctx->ifc_txqs; 2657 iflib_rxq_t rxq = ctx->ifc_rxqs; 2658 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2659 if_shared_ctx_t sctx = ctx->ifc_sctx; 2660 iflib_dma_info_t di; 2661 iflib_fl_t fl; 2662 int i, j; 2663 2664 /* Tell the stack that the interface is no longer active */ 2665 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2666 2667 IFDI_INTR_DISABLE(ctx); 2668 DELAY(1000); 2669 IFDI_STOP(ctx); 2670 DELAY(1000); 2671 2672 /* 2673 * Stop any pending txsync/rxsync and prevent new ones 2674 * form starting. Processes blocked in poll() will get 2675 * POLLERR. 2676 */ 2677 netmap_disable_all_rings(ctx->ifc_ifp); 2678 2679 iflib_debug_reset(); 2680 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2681 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2682 /* make sure all transmitters have completed before proceeding XXX */ 2683 2684 CALLOUT_LOCK(txq); 2685 callout_stop(&txq->ift_timer); 2686 #ifdef DEV_NETMAP 2687 callout_stop(&txq->ift_netmap_timer); 2688 #endif /* DEV_NETMAP */ 2689 CALLOUT_UNLOCK(txq); 2690 2691 if (!ctx->ifc_sysctl_simple_tx) { 2692 /* clean any enqueued buffers */ 2693 iflib_ifmp_purge(txq); 2694 } 2695 /* Free any existing tx buffers. */ 2696 for (j = 0; j < txq->ift_size; j++) { 2697 iflib_txsd_free(ctx, txq, j); 2698 } 2699 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2700 txq->ift_processed_prev = 0; 2701 txq->ift_outstanding_prev = 0; 2702 txq->ift_wdog_armed = 0; 2703 txq->ift_in_use = txq->ift_gen = txq->ift_no_desc_avail = 0; 2704 txq->ift_npending = txq->ift_db_pending = 0; 2705 txq->ift_rs_pending = 0; 2706 if (sctx->isc_flags & IFLIB_PRESERVE_TX_INDICES) 2707 txq->ift_cidx = txq->ift_pidx; 2708 else 2709 txq->ift_cidx = txq->ift_pidx = 0; 2710 2711 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2712 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2713 txq->ift_pullups = 0; 2714 ifmp_ring_reset_stats(txq->ift_br); 2715 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2716 bzero((void *)di->idi_vaddr, di->idi_size); 2717 } 2718 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2719 if (rxq->ifr_task.gt_taskqueue != NULL) 2720 gtaskqueue_drain(rxq->ifr_task.gt_taskqueue, 2721 &rxq->ifr_task.gt_task); 2722 2723 rxq->ifr_cq_cidx = 0; 2724 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2725 bzero((void *)di->idi_vaddr, di->idi_size); 2726 /* also resets the free lists pidx/cidx */ 2727 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2728 iflib_fl_bufs_free(fl); 2729 } 2730 } 2731 2732 static inline caddr_t 2733 calc_next_rxd(iflib_fl_t fl, int cidx) 2734 { 2735 qidx_t size; 2736 int nrxd; 2737 caddr_t start, end, cur, next; 2738 2739 nrxd = fl->ifl_size; 2740 size = fl->ifl_rxd_size; 2741 start = fl->ifl_ifdi->idi_vaddr; 2742 2743 if (__predict_false(size == 0)) 2744 return (start); 2745 cur = start + size * cidx; 2746 end = start + size * nrxd; 2747 next = CACHE_PTR_NEXT(cur); 2748 return (next < end ? next : start); 2749 } 2750 2751 static inline void 2752 prefetch_pkts(iflib_fl_t fl, int cidx) 2753 { 2754 int nextptr; 2755 int nrxd = fl->ifl_size; 2756 caddr_t next_rxd; 2757 2758 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd - 1); 2759 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2760 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2761 next_rxd = calc_next_rxd(fl, cidx); 2762 prefetch(next_rxd); 2763 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd - 1)]); 2764 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd - 1)]); 2765 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd - 1)]); 2766 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd - 1)]); 2767 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd - 1)]); 2768 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd - 1)]); 2769 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd - 1)]); 2770 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd - 1)]); 2771 } 2772 2773 static struct mbuf * 2774 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2775 int *pf_rv, if_rxd_info_t ri) 2776 { 2777 bus_dmamap_t map; 2778 iflib_fl_t fl; 2779 caddr_t payload; 2780 struct mbuf *m; 2781 int flid, cidx, len, next; 2782 2783 map = NULL; 2784 flid = irf->irf_flid; 2785 cidx = irf->irf_idx; 2786 fl = &rxq->ifr_fl[flid]; 2787 sd->ifsd_fl = fl; 2788 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2789 fl->ifl_credits--; 2790 #if MEMORY_LOGGING 2791 fl->ifl_m_dequeued++; 2792 #endif 2793 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2794 prefetch_pkts(fl, cidx); 2795 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size - 1); 2796 prefetch(&fl->ifl_sds.ifsd_map[next]); 2797 map = fl->ifl_sds.ifsd_map[cidx]; 2798 2799 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2800 2801 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2802 irf->irf_len != 0) { 2803 payload = *sd->ifsd_cl; 2804 payload += ri->iri_pad; 2805 len = ri->iri_len - ri->iri_pad; 2806 *pf_rv = pfil_mem_in(rxq->pfil, payload, len, ri->iri_ifp, &m); 2807 switch (*pf_rv) { 2808 case PFIL_DROPPED: 2809 case PFIL_CONSUMED: 2810 /* 2811 * The filter ate it. Everything is recycled. 2812 */ 2813 m = NULL; 2814 unload = 0; 2815 break; 2816 case PFIL_REALLOCED: 2817 /* 2818 * The filter copied it. Everything is recycled. 2819 * 'm' points at new mbuf. 2820 */ 2821 unload = 0; 2822 break; 2823 case PFIL_PASS: 2824 /* 2825 * Filter said it was OK, so receive like 2826 * normal 2827 */ 2828 m = fl->ifl_sds.ifsd_m[cidx]; 2829 fl->ifl_sds.ifsd_m[cidx] = NULL; 2830 break; 2831 default: 2832 MPASS(0); 2833 } 2834 } else { 2835 m = fl->ifl_sds.ifsd_m[cidx]; 2836 fl->ifl_sds.ifsd_m[cidx] = NULL; 2837 if (pf_rv != NULL) 2838 *pf_rv = PFIL_PASS; 2839 } 2840 2841 if (unload && irf->irf_len != 0) 2842 bus_dmamap_unload(fl->ifl_buf_tag, map); 2843 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size - 1); 2844 if (__predict_false(fl->ifl_cidx == 0)) 2845 fl->ifl_gen = 0; 2846 bit_clear(fl->ifl_rx_bitmap, cidx); 2847 return (m); 2848 } 2849 2850 static struct mbuf * 2851 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2852 { 2853 struct mbuf *m, *mh, *mt; 2854 caddr_t cl; 2855 int *pf_rv_ptr, flags, i, padlen; 2856 bool consumed; 2857 2858 i = 0; 2859 mh = NULL; 2860 consumed = false; 2861 *pf_rv = PFIL_PASS; 2862 pf_rv_ptr = pf_rv; 2863 do { 2864 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2865 pf_rv_ptr, ri); 2866 2867 MPASS(*sd->ifsd_cl != NULL); 2868 2869 /* 2870 * Exclude zero-length frags & frags from 2871 * packets the filter has consumed or dropped 2872 */ 2873 if (ri->iri_frags[i].irf_len == 0 || consumed || 2874 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2875 if (mh == NULL) { 2876 consumed = true; 2877 pf_rv_ptr = NULL; 2878 } 2879 /* XXX we can save the cluster here, but not the mbuf */ 2880 if (m != NULL) { 2881 m_init(m, M_NOWAIT, MT_DATA, 0); 2882 m_free(m); 2883 } 2884 continue; 2885 } 2886 if (mh == NULL) { 2887 flags = M_PKTHDR | M_EXT; 2888 mh = mt = m; 2889 padlen = ri->iri_pad; 2890 } else { 2891 flags = M_EXT; 2892 mt->m_next = m; 2893 mt = m; 2894 /* assuming padding is only on the first fragment */ 2895 padlen = 0; 2896 } 2897 cl = *sd->ifsd_cl; 2898 *sd->ifsd_cl = NULL; 2899 2900 /* Can these two be made one ? */ 2901 m_init(m, M_NOWAIT, MT_DATA, flags); 2902 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2903 /* 2904 * These must follow m_init and m_cljset 2905 */ 2906 m->m_data += padlen; 2907 ri->iri_len -= padlen; 2908 m->m_len = ri->iri_frags[i].irf_len; 2909 } while (++i < ri->iri_nfrags); 2910 2911 return (mh); 2912 } 2913 2914 /* 2915 * Process one software descriptor 2916 */ 2917 static struct mbuf * 2918 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2919 { 2920 struct if_rxsd sd; 2921 struct mbuf *m; 2922 int pf_rv; 2923 2924 /* should I merge this back in now that the two paths are basically duplicated? */ 2925 if (ri->iri_nfrags == 1 && 2926 ri->iri_frags[0].irf_len != 0 && 2927 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2928 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2929 &pf_rv, ri); 2930 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2931 return (m); 2932 if (pf_rv == PFIL_PASS) { 2933 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2934 #ifndef __NO_STRICT_ALIGNMENT 2935 if (!IP_ALIGNED(m) && ri->iri_pad == 0) 2936 m->m_data += 2; 2937 #endif 2938 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2939 m->m_len = ri->iri_frags[0].irf_len; 2940 m->m_data += ri->iri_pad; 2941 ri->iri_len -= ri->iri_pad; 2942 } 2943 } else { 2944 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2945 if (m == NULL) 2946 return (NULL); 2947 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2948 return (m); 2949 } 2950 m->m_pkthdr.len = ri->iri_len; 2951 m->m_pkthdr.rcvif = ri->iri_ifp; 2952 m->m_flags |= ri->iri_flags; 2953 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2954 m->m_pkthdr.flowid = ri->iri_flowid; 2955 #ifdef NUMA 2956 m->m_pkthdr.numa_domain = if_getnumadomain(ri->iri_ifp); 2957 #endif 2958 M_HASHTYPE_SET(m, ri->iri_rsstype); 2959 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2960 m->m_pkthdr.csum_data = ri->iri_csum_data; 2961 return (m); 2962 } 2963 2964 static void 2965 _task_fn_rx_watchdog(void *context) 2966 { 2967 iflib_rxq_t rxq = context; 2968 2969 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2970 } 2971 2972 static uint8_t 2973 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2974 { 2975 if_t ifp; 2976 if_ctx_t ctx = rxq->ifr_ctx; 2977 if_shared_ctx_t sctx = ctx->ifc_sctx; 2978 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2979 int avail, i; 2980 qidx_t *cidxp; 2981 struct if_rxd_info ri; 2982 int err, budget_left, rx_bytes, rx_pkts; 2983 iflib_fl_t fl; 2984 #if defined(INET6) || defined(INET) 2985 int lro_enabled; 2986 #endif 2987 uint8_t retval = 0; 2988 2989 /* 2990 * XXX early demux data packets so that if_input processing only handles 2991 * acks in interrupt context 2992 */ 2993 struct mbuf *m, *mh, *mt; 2994 2995 NET_EPOCH_ASSERT(); 2996 2997 ifp = ctx->ifc_ifp; 2998 mh = mt = NULL; 2999 MPASS(budget > 0); 3000 rx_pkts = rx_bytes = 0; 3001 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 3002 cidxp = &rxq->ifr_cq_cidx; 3003 else 3004 cidxp = &rxq->ifr_fl[0].ifl_cidx; 3005 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 3006 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3007 retval |= iflib_fl_refill_all(ctx, fl); 3008 DBG_COUNTER_INC(rx_unavail); 3009 return (retval); 3010 } 3011 3012 #if defined(INET6) || defined(INET) 3013 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 3014 #endif 3015 3016 /* pfil needs the vnet to be set */ 3017 CURVNET_SET_QUIET(if_getvnet(ifp)); 3018 for (budget_left = budget; budget_left > 0 && avail > 0;) { 3019 if (__predict_false(!CTX_ACTIVE(ctx))) { 3020 DBG_COUNTER_INC(rx_ctx_inactive); 3021 break; 3022 } 3023 /* 3024 * Reset client set fields to their default values 3025 */ 3026 memset(&ri, 0, sizeof(ri)); 3027 ri.iri_qsidx = rxq->ifr_id; 3028 ri.iri_cidx = *cidxp; 3029 ri.iri_ifp = ifp; 3030 ri.iri_frags = rxq->ifr_frags; 3031 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 3032 3033 if (err) { 3034 CURVNET_RESTORE(); 3035 goto err; 3036 } 3037 rx_pkts += 1; 3038 rx_bytes += ri.iri_len; 3039 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 3040 *cidxp = ri.iri_cidx; 3041 /* Update our consumer index */ 3042 /* XXX NB: shurd - check if this is still safe */ 3043 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 3044 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 3045 /* was this only a completion queue message? */ 3046 if (__predict_false(ri.iri_nfrags == 0)) 3047 continue; 3048 } 3049 MPASS(ri.iri_nfrags != 0); 3050 MPASS(ri.iri_len != 0); 3051 3052 /* will advance the cidx on the corresponding free lists */ 3053 m = iflib_rxd_pkt_get(rxq, &ri); 3054 avail--; 3055 budget_left--; 3056 if (avail == 0 && budget_left) 3057 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 3058 3059 if (__predict_false(m == NULL)) 3060 continue; 3061 3062 #ifndef __NO_STRICT_ALIGNMENT 3063 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 3064 continue; 3065 #endif 3066 #if defined(INET6) || defined(INET) 3067 if (lro_enabled) { 3068 tcp_lro_queue_mbuf(&rxq->ifr_lc, m); 3069 continue; 3070 } 3071 #endif 3072 3073 if (mh == NULL) 3074 mh = mt = m; 3075 else { 3076 mt->m_nextpkt = m; 3077 mt = m; 3078 } 3079 } 3080 CURVNET_RESTORE(); 3081 /* make sure that we can refill faster than drain */ 3082 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3083 retval |= iflib_fl_refill_all(ctx, fl); 3084 3085 if (mh != NULL) { 3086 if_input(ifp, mh); 3087 DBG_COUNTER_INC(rx_if_input); 3088 } 3089 3090 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 3091 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 3092 3093 /* 3094 * Flush any outstanding LRO work 3095 */ 3096 #if defined(INET6) || defined(INET) 3097 tcp_lro_flush_all(&rxq->ifr_lc); 3098 #endif 3099 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 3100 retval |= IFLIB_RXEOF_MORE; 3101 return (retval); 3102 err: 3103 STATE_LOCK(ctx); 3104 ctx->ifc_flags |= IFC_DO_RESET; 3105 iflib_admin_intr_deferred(ctx); 3106 STATE_UNLOCK(ctx); 3107 return (0); 3108 } 3109 3110 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq) - 1) 3111 static inline qidx_t 3112 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 3113 { 3114 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3115 qidx_t minthresh = txq->ift_size / 8; 3116 if (in_use > 4 * minthresh) 3117 return (notify_count); 3118 if (in_use > 2 * minthresh) 3119 return (notify_count >> 1); 3120 if (in_use > minthresh) 3121 return (notify_count >> 3); 3122 return (0); 3123 } 3124 3125 static inline qidx_t 3126 txq_max_rs_deferred(iflib_txq_t txq) 3127 { 3128 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3129 qidx_t minthresh = txq->ift_size / 8; 3130 if (txq->ift_in_use > 4 * minthresh) 3131 return (notify_count); 3132 if (txq->ift_in_use > 2 * minthresh) 3133 return (notify_count >> 1); 3134 if (txq->ift_in_use > minthresh) 3135 return (notify_count >> 2); 3136 return (2); 3137 } 3138 3139 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 3140 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 3141 3142 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 3143 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 3144 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 3145 3146 /* forward compatibility for cxgb */ 3147 #define FIRST_QSET(ctx) 0 3148 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3149 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3150 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3151 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3152 3153 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3154 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3155 3156 static inline bool 3157 iflib_txd_db_check(iflib_txq_t txq, int ring) 3158 { 3159 if_ctx_t ctx = txq->ift_ctx; 3160 qidx_t dbval, max; 3161 3162 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use); 3163 3164 /* force || threshold exceeded || at the edge of the ring */ 3165 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx))) { 3166 3167 /* 3168 * 'npending' is used if the card's doorbell is in terms of the number of descriptors 3169 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the 3170 * producer index explicitly (INTC). 3171 */ 3172 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3173 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3174 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3175 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3176 3177 /* 3178 * Absent bugs there are zero packets pending so reset pending counts to zero. 3179 */ 3180 txq->ift_db_pending = txq->ift_npending = 0; 3181 return (true); 3182 } 3183 return (false); 3184 } 3185 3186 #ifdef PKT_DEBUG 3187 static void 3188 print_pkt(if_pkt_info_t pi) 3189 { 3190 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3191 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3192 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3193 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3194 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3195 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3196 } 3197 #endif 3198 3199 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3200 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3201 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3202 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3203 3204 /** 3205 * Parses out ethernet header information in the given mbuf. 3206 * Returns in pi: ipi_etype (EtherType) and ipi_ehdrlen (Ethernet header length) 3207 * 3208 * This will account for the VLAN header if present. 3209 * 3210 * XXX: This doesn't handle QinQ, which could prevent TX offloads for those 3211 * types of packets. 3212 */ 3213 static int 3214 iflib_parse_ether_header(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3215 { 3216 struct ether_vlan_header *eh; 3217 struct mbuf *m; 3218 3219 m = *mp; 3220 if (__predict_false(m->m_len < sizeof(*eh))) { 3221 (*pullups)++; 3222 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3223 return (ENOMEM); 3224 } 3225 eh = mtod(m, struct ether_vlan_header *); 3226 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3227 pi->ipi_etype = ntohs(eh->evl_proto); 3228 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3229 } else { 3230 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3231 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3232 } 3233 *mp = m; 3234 3235 return (0); 3236 } 3237 3238 /** 3239 * Parse up to the L3 header and extract IPv4/IPv6 header information into pi. 3240 * Currently this information includes: IP ToS value, IP header version/presence 3241 * 3242 * This is missing some checks and doesn't edit the packet content as it goes, 3243 * unlike iflib_parse_header(), in order to keep the amount of code here minimal. 3244 */ 3245 static int 3246 iflib_parse_header_partial(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3247 { 3248 struct mbuf *m; 3249 int err; 3250 3251 *pullups = 0; 3252 m = *mp; 3253 if (!M_WRITABLE(m)) { 3254 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3255 return (ENOMEM); 3256 } else { 3257 m_freem(*mp); 3258 DBG_COUNTER_INC(tx_frees); 3259 *mp = m; 3260 } 3261 } 3262 3263 /* Fills out pi->ipi_etype */ 3264 err = iflib_parse_ether_header(pi, mp, pullups); 3265 if (err) 3266 return (err); 3267 m = *mp; 3268 3269 switch (pi->ipi_etype) { 3270 #ifdef INET 3271 case ETHERTYPE_IP: 3272 { 3273 struct mbuf *n; 3274 struct ip *ip = NULL; 3275 int miniplen; 3276 3277 miniplen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip)); 3278 if (__predict_false(m->m_len < miniplen)) { 3279 /* 3280 * Check for common case where the first mbuf only contains 3281 * the Ethernet header 3282 */ 3283 if (m->m_len == pi->ipi_ehdrlen) { 3284 n = m->m_next; 3285 MPASS(n); 3286 /* If next mbuf contains at least the minimal IP header, then stop */ 3287 if (n->m_len >= sizeof(*ip)) { 3288 ip = (struct ip *)n->m_data; 3289 } else { 3290 (*pullups)++; 3291 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3292 return (ENOMEM); 3293 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3294 } 3295 } else { 3296 (*pullups)++; 3297 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3298 return (ENOMEM); 3299 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3300 } 3301 } else { 3302 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3303 } 3304 3305 /* Have the IPv4 header w/ no options here */ 3306 pi->ipi_ip_hlen = ip->ip_hl << 2; 3307 pi->ipi_ipproto = ip->ip_p; 3308 pi->ipi_ip_tos = ip->ip_tos; 3309 pi->ipi_flags |= IPI_TX_IPV4; 3310 3311 break; 3312 } 3313 #endif 3314 #ifdef INET6 3315 case ETHERTYPE_IPV6: 3316 { 3317 struct ip6_hdr *ip6; 3318 3319 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3320 (*pullups)++; 3321 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3322 return (ENOMEM); 3323 } 3324 ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3325 3326 /* Have the IPv6 fixed header here */ 3327 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3328 pi->ipi_ipproto = ip6->ip6_nxt; 3329 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3330 pi->ipi_flags |= IPI_TX_IPV6; 3331 3332 break; 3333 } 3334 #endif 3335 default: 3336 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3337 pi->ipi_ip_hlen = 0; 3338 break; 3339 } 3340 *mp = m; 3341 3342 return (0); 3343 3344 } 3345 3346 static int 3347 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3348 { 3349 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3350 struct mbuf *m; 3351 int err; 3352 3353 m = *mp; 3354 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3355 M_WRITABLE(m) == 0) { 3356 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3357 return (ENOMEM); 3358 } else { 3359 m_freem(*mp); 3360 DBG_COUNTER_INC(tx_frees); 3361 *mp = m; 3362 } 3363 } 3364 3365 /* Fills out pi->ipi_etype */ 3366 err = iflib_parse_ether_header(pi, mp, &txq->ift_pullups); 3367 if (__predict_false(err)) 3368 return (err); 3369 m = *mp; 3370 3371 switch (pi->ipi_etype) { 3372 #ifdef INET 3373 case ETHERTYPE_IP: 3374 { 3375 struct ip *ip; 3376 struct tcphdr *th; 3377 uint8_t hlen; 3378 3379 hlen = pi->ipi_ehdrlen + sizeof(*ip); 3380 if (__predict_false(m->m_len < hlen)) { 3381 txq->ift_pullups++; 3382 if (__predict_false((m = m_pullup(m, hlen)) == NULL)) 3383 return (ENOMEM); 3384 } 3385 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3386 hlen = pi->ipi_ehdrlen + (ip->ip_hl << 2); 3387 if (ip->ip_p == IPPROTO_TCP) { 3388 hlen += sizeof(*th); 3389 th = (struct tcphdr *)((char *)ip + (ip->ip_hl << 2)); 3390 } else if (ip->ip_p == IPPROTO_UDP) { 3391 hlen += sizeof(struct udphdr); 3392 } 3393 if (__predict_false(m->m_len < hlen)) { 3394 txq->ift_pullups++; 3395 if ((m = m_pullup(m, hlen)) == NULL) 3396 return (ENOMEM); 3397 } 3398 pi->ipi_ip_hlen = ip->ip_hl << 2; 3399 pi->ipi_ipproto = ip->ip_p; 3400 pi->ipi_ip_tos = ip->ip_tos; 3401 pi->ipi_flags |= IPI_TX_IPV4; 3402 3403 /* TCP checksum offload may require TCP header length */ 3404 if (IS_TX_OFFLOAD4(pi)) { 3405 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3406 pi->ipi_tcp_hflags = tcp_get_flags(th); 3407 pi->ipi_tcp_hlen = th->th_off << 2; 3408 pi->ipi_tcp_seq = th->th_seq; 3409 } 3410 if (IS_TSO4(pi)) { 3411 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3412 return (ENXIO); 3413 /* 3414 * TSO always requires hardware checksum offload. 3415 */ 3416 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3417 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3418 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3419 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3420 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3421 ip->ip_sum = 0; 3422 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3423 } 3424 } 3425 } 3426 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3427 ip->ip_sum = 0; 3428 3429 break; 3430 } 3431 #endif 3432 #ifdef INET6 3433 case ETHERTYPE_IPV6: 3434 { 3435 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3436 struct tcphdr *th; 3437 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3438 3439 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3440 txq->ift_pullups++; 3441 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3442 return (ENOMEM); 3443 } 3444 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3445 3446 /* XXX-BZ this will go badly in case of ext hdrs. */ 3447 pi->ipi_ipproto = ip6->ip6_nxt; 3448 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3449 pi->ipi_flags |= IPI_TX_IPV6; 3450 3451 /* TCP checksum offload may require TCP header length */ 3452 if (IS_TX_OFFLOAD6(pi)) { 3453 if (pi->ipi_ipproto == IPPROTO_TCP) { 3454 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3455 txq->ift_pullups++; 3456 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3457 return (ENOMEM); 3458 } 3459 pi->ipi_tcp_hflags = tcp_get_flags(th); 3460 pi->ipi_tcp_hlen = th->th_off << 2; 3461 pi->ipi_tcp_seq = th->th_seq; 3462 } 3463 if (IS_TSO6(pi)) { 3464 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3465 return (ENXIO); 3466 /* 3467 * TSO always requires hardware checksum offload. 3468 */ 3469 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3470 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3471 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3472 } 3473 } 3474 break; 3475 } 3476 #endif 3477 default: 3478 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3479 pi->ipi_ip_hlen = 0; 3480 break; 3481 } 3482 *mp = m; 3483 3484 return (0); 3485 } 3486 3487 /* 3488 * If dodgy hardware rejects the scatter gather chain we've handed it 3489 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3490 * m_defrag'd mbufs 3491 */ 3492 static __noinline struct mbuf * 3493 iflib_remove_mbuf(iflib_txq_t txq) 3494 { 3495 int ntxd, pidx; 3496 struct mbuf *m, **ifsd_m; 3497 3498 ifsd_m = txq->ift_sds.ifsd_m; 3499 ntxd = txq->ift_size; 3500 pidx = txq->ift_pidx & (ntxd - 1); 3501 ifsd_m = txq->ift_sds.ifsd_m; 3502 m = IFLIB_GET_MBUF(ifsd_m[pidx]); 3503 ifsd_m[pidx] = NULL; 3504 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3505 if (txq->ift_sds.ifsd_tso_map != NULL) 3506 bus_dmamap_unload(txq->ift_tso_buf_tag, 3507 txq->ift_sds.ifsd_tso_map[pidx]); 3508 #if MEMORY_LOGGING 3509 txq->ift_dequeued++; 3510 #endif 3511 return (m); 3512 } 3513 3514 /* 3515 * Pad an mbuf to ensure a minimum ethernet frame size. 3516 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3517 */ 3518 static __noinline int 3519 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3520 { 3521 /* 3522 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3523 * and ARP message is the smallest common payload I can think of 3524 */ 3525 static char pad[18]; /* just zeros */ 3526 int n; 3527 struct mbuf *new_head; 3528 3529 if (!M_WRITABLE(*m_head)) { 3530 new_head = m_dup(*m_head, M_NOWAIT); 3531 if (new_head == NULL) { 3532 m_freem(*m_head); 3533 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3534 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3535 DBG_COUNTER_INC(tx_frees); 3536 return (ENOMEM); 3537 } 3538 m_freem(*m_head); 3539 *m_head = new_head; 3540 } 3541 3542 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3543 n > 0; n -= sizeof(pad)) 3544 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3545 break; 3546 3547 if (n > 0) { 3548 m_freem(*m_head); 3549 device_printf(dev, "cannot pad short frame\n"); 3550 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3551 DBG_COUNTER_INC(tx_frees); 3552 return (ENOBUFS); 3553 } 3554 3555 return (0); 3556 } 3557 3558 static int 3559 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp, int *obytes, int *opkts) 3560 { 3561 if_ctx_t ctx; 3562 if_shared_ctx_t sctx; 3563 if_softc_ctx_t scctx; 3564 bus_dma_tag_t buf_tag; 3565 bus_dma_segment_t *segs; 3566 struct mbuf *m_head, **ifsd_m; 3567 bus_dmamap_t map; 3568 struct if_pkt_info pi; 3569 uintptr_t flags; 3570 int remap = 0; 3571 int err, nsegs, ndesc, max_segs, pidx; 3572 3573 ctx = txq->ift_ctx; 3574 sctx = ctx->ifc_sctx; 3575 scctx = &ctx->ifc_softc_ctx; 3576 segs = txq->ift_segs; 3577 m_head = *m_headp; 3578 map = NULL; 3579 3580 /* 3581 * If we're doing TSO the next descriptor to clean may be quite far ahead 3582 */ 3583 pidx = txq->ift_pidx; 3584 map = txq->ift_sds.ifsd_map[pidx]; 3585 ifsd_m = txq->ift_sds.ifsd_m; 3586 3587 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3588 buf_tag = txq->ift_tso_buf_tag; 3589 max_segs = scctx->isc_tx_tso_segments_max; 3590 map = txq->ift_sds.ifsd_tso_map[pidx]; 3591 MPASS(buf_tag != NULL); 3592 MPASS(max_segs > 0); 3593 flags = IFLIB_TSO; 3594 } else { 3595 buf_tag = txq->ift_buf_tag; 3596 max_segs = scctx->isc_tx_nsegments; 3597 map = txq->ift_sds.ifsd_map[pidx]; 3598 flags = IFLIB_NO_TSO; 3599 } 3600 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3601 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3602 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3603 if (err) { 3604 DBG_COUNTER_INC(encap_txd_encap_fail); 3605 return (err); 3606 } 3607 } 3608 m_head = *m_headp; 3609 3610 memset(&pi, 0, sizeof(pi)); 3611 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG | M_BCAST | M_MCAST)); 3612 pi.ipi_pidx = pidx; 3613 pi.ipi_qsidx = txq->ift_id; 3614 pi.ipi_len = m_head->m_pkthdr.len; 3615 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3616 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3617 3618 /* deliberate bitwise OR to make one condition */ 3619 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3620 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3621 DBG_COUNTER_INC(encap_txd_encap_fail); 3622 return (err); 3623 } 3624 m_head = *m_headp; 3625 } 3626 3627 retry: 3628 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3629 BUS_DMA_NOWAIT); 3630 defrag: 3631 if (__predict_false(err)) { 3632 switch (err) { 3633 case EFBIG: 3634 /* try collapse once and defrag once */ 3635 if (remap == 0) { 3636 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3637 /* try defrag if collapsing fails */ 3638 if (m_head == NULL) 3639 remap++; 3640 } 3641 if (remap == 1) { 3642 txq->ift_mbuf_defrag++; 3643 m_head = m_defrag(*m_headp, M_NOWAIT); 3644 } 3645 /* 3646 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3647 * failed to map an mbuf that was run through m_defrag 3648 */ 3649 MPASS(remap <= 1); 3650 if (__predict_false(m_head == NULL || remap > 1)) 3651 goto defrag_failed; 3652 remap++; 3653 *m_headp = m_head; 3654 goto retry; 3655 break; 3656 case ENOMEM: 3657 txq->ift_no_tx_dma_setup++; 3658 break; 3659 default: 3660 txq->ift_no_tx_dma_setup++; 3661 m_freem(*m_headp); 3662 DBG_COUNTER_INC(tx_frees); 3663 *m_headp = NULL; 3664 break; 3665 } 3666 txq->ift_map_failed++; 3667 DBG_COUNTER_INC(encap_load_mbuf_fail); 3668 DBG_COUNTER_INC(encap_txd_encap_fail); 3669 return (err); 3670 } 3671 ifsd_m[pidx] = IFLIB_SAVE_MBUF(m_head, flags); 3672 if (m_head->m_pkthdr.csum_flags & CSUM_SND_TAG) 3673 pi.ipi_mbuf = m_head; 3674 else 3675 pi.ipi_mbuf = NULL; 3676 /* 3677 * XXX assumes a 1 to 1 relationship between segments and 3678 * descriptors - this does not hold true on all drivers, e.g. 3679 * cxgb 3680 */ 3681 if (__predict_false(nsegs > TXQ_AVAIL(txq))) { 3682 iflib_completed_tx_reclaim_force(txq); 3683 if (__predict_false(nsegs > TXQ_AVAIL(txq))) { 3684 txq->ift_no_desc_avail++; 3685 bus_dmamap_unload(buf_tag, map); 3686 DBG_COUNTER_INC(encap_txq_avail_fail); 3687 DBG_COUNTER_INC(encap_txd_encap_fail); 3688 if (ctx->ifc_sysctl_simple_tx) { 3689 *m_headp = m_head = iflib_remove_mbuf(txq); 3690 m_freem(*m_headp); 3691 DBG_COUNTER_INC(tx_frees); 3692 *m_headp = NULL; 3693 } 3694 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3695 GROUPTASK_ENQUEUE(&txq->ift_task); 3696 return (ENOBUFS); 3697 } 3698 } 3699 /* 3700 * On Intel cards we can greatly reduce the number of TX interrupts 3701 * we see by only setting report status on every Nth descriptor. 3702 * However, this also means that the driver will need to keep track 3703 * of the descriptors that RS was set on to check them for the DD bit. 3704 */ 3705 txq->ift_rs_pending += nsegs + 1; 3706 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3707 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx)) { 3708 pi.ipi_flags |= IPI_TX_INTR; 3709 txq->ift_rs_pending = 0; 3710 } 3711 3712 pi.ipi_segs = segs; 3713 pi.ipi_nsegs = nsegs; 3714 3715 MPASS(pidx >= 0 && pidx < txq->ift_size); 3716 #ifdef PKT_DEBUG 3717 print_pkt(&pi); 3718 #endif 3719 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3720 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3721 DBG_COUNTER_INC(tx_encap); 3722 MPASS(pi.ipi_new_pidx < txq->ift_size); 3723 3724 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3725 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3726 ndesc += txq->ift_size; 3727 txq->ift_gen = 1; 3728 } 3729 /* 3730 * drivers can need up to ift_pad sentinels 3731 */ 3732 MPASS(ndesc <= pi.ipi_nsegs + txq->ift_pad); 3733 MPASS(pi.ipi_new_pidx != pidx); 3734 MPASS(ndesc > 0); 3735 txq->ift_in_use += ndesc; 3736 txq->ift_db_pending += ndesc; 3737 3738 /* 3739 * We update the last software descriptor again here because there may 3740 * be a sentinel and/or there may be more mbufs than segments 3741 */ 3742 txq->ift_pidx = pi.ipi_new_pidx; 3743 txq->ift_npending += pi.ipi_ndescs; 3744 3745 /* 3746 * Update packets / bytes sent 3747 */ 3748 if (flags & IFLIB_TSO) { 3749 int hlen = pi.ipi_ehdrlen + pi.ipi_ip_hlen + pi.ipi_tcp_hlen; 3750 int tsolen = pi.ipi_len - hlen; 3751 int nsegs = (tsolen + pi.ipi_tso_segsz - 1) / pi.ipi_tso_segsz; 3752 *obytes += tsolen + nsegs * hlen; 3753 *opkts += nsegs; 3754 } else { 3755 *obytes += pi.ipi_len; 3756 *opkts += 1; 3757 } 3758 } else { 3759 *m_headp = m_head = iflib_remove_mbuf(txq); 3760 if (err == EFBIG) { 3761 txq->ift_txd_encap_efbig++; 3762 if (remap < 2) { 3763 remap = 1; 3764 goto defrag; 3765 } 3766 goto defrag_failed; 3767 } 3768 goto out_with_error; 3769 } 3770 /* 3771 * err can't possibly be non-zero here, so we don't neet to test it 3772 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3773 */ 3774 return (err); 3775 3776 defrag_failed: 3777 err = ENOMEM; 3778 txq->ift_mbuf_defrag_failed++; 3779 out_with_error: 3780 txq->ift_map_failed++; 3781 m_freem(*m_headp); 3782 DBG_COUNTER_INC(tx_frees); 3783 *m_headp = NULL; 3784 DBG_COUNTER_INC(encap_txd_encap_fail); 3785 return (err); 3786 } 3787 3788 static void 3789 iflib_tx_desc_free(iflib_txq_t txq, int n, struct mbuf **m_defer) 3790 { 3791 uint32_t qsize, cidx, gen; 3792 struct mbuf *m, **ifsd_m; 3793 uintptr_t flags; 3794 3795 cidx = txq->ift_cidx; 3796 gen = txq->ift_gen; 3797 qsize = txq->ift_size; 3798 ifsd_m =txq->ift_sds.ifsd_m; 3799 3800 while (n-- > 0) { 3801 if ((m = IFLIB_GET_MBUF(ifsd_m[cidx])) != NULL) { 3802 flags = IFLIB_GET_FLAGS(ifsd_m[cidx]); 3803 MPASS(flags != 0); 3804 if (flags & IFLIB_TSO) { 3805 bus_dmamap_sync(txq->ift_tso_buf_tag, 3806 txq->ift_sds.ifsd_tso_map[cidx], 3807 BUS_DMASYNC_POSTWRITE); 3808 bus_dmamap_unload(txq->ift_tso_buf_tag, 3809 txq->ift_sds.ifsd_tso_map[cidx]); 3810 } else { 3811 bus_dmamap_sync(txq->ift_buf_tag, 3812 txq->ift_sds.ifsd_map[cidx], 3813 BUS_DMASYNC_POSTWRITE); 3814 bus_dmamap_unload(txq->ift_buf_tag, 3815 txq->ift_sds.ifsd_map[cidx]); 3816 } 3817 /* XXX we don't support any drivers that batch packets yet */ 3818 MPASS(m->m_nextpkt == NULL); 3819 if (m_defer == NULL) { 3820 m_freem(m); 3821 } else if (m != NULL) { 3822 *m_defer = m; 3823 m_defer++; 3824 } 3825 ifsd_m[cidx] = NULL; 3826 #if MEMORY_LOGGING 3827 txq->ift_dequeued++; 3828 #endif 3829 DBG_COUNTER_INC(tx_frees); 3830 } 3831 if (__predict_false(++cidx == qsize)) { 3832 cidx = 0; 3833 gen = 0; 3834 } 3835 } 3836 txq->ift_cidx = cidx; 3837 txq->ift_gen = gen; 3838 } 3839 3840 static __inline int 3841 iflib_txq_can_reclaim(iflib_txq_t txq) 3842 { 3843 int reclaim, thresh; 3844 3845 thresh = txq->ift_reclaim_thresh; 3846 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3847 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3848 3849 if (ticks <= (txq->ift_last_reclaim + txq->ift_reclaim_ticks) && 3850 txq->ift_in_use < thresh) 3851 return (false); 3852 iflib_tx_credits_update(txq->ift_ctx, txq); 3853 reclaim = DESC_RECLAIMABLE(txq); 3854 if (reclaim <= thresh) { 3855 #ifdef INVARIANTS 3856 if (iflib_verbose_debug) { 3857 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __func__, 3858 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3859 reclaim, thresh); 3860 } 3861 #endif 3862 return (0); 3863 } 3864 return (reclaim); 3865 } 3866 3867 static __inline void 3868 _iflib_completed_tx_reclaim(iflib_txq_t txq, struct mbuf **m_defer, int reclaim) 3869 { 3870 txq->ift_last_reclaim = ticks; 3871 iflib_tx_desc_free(txq, reclaim, m_defer); 3872 txq->ift_cleaned += reclaim; 3873 txq->ift_in_use -= reclaim; 3874 } 3875 3876 static __inline int 3877 iflib_completed_tx_reclaim(iflib_txq_t txq, struct mbuf **m_defer) 3878 { 3879 int reclaim; 3880 3881 reclaim = iflib_txq_can_reclaim(txq); 3882 if (reclaim == 0) 3883 return (0); 3884 _iflib_completed_tx_reclaim(txq, m_defer, reclaim); 3885 return (reclaim); 3886 } 3887 3888 /* 3889 * Reclaim any transmit descriptors possible, ignoring coalescing 3890 */ 3891 static __inline void 3892 iflib_completed_tx_reclaim_force(iflib_txq_t txq) 3893 { 3894 int reclaim; 3895 3896 iflib_tx_credits_update(txq->ift_ctx, txq); 3897 reclaim = DESC_RECLAIMABLE(txq); 3898 if (reclaim != 0) 3899 _iflib_completed_tx_reclaim(txq, NULL, reclaim); 3900 } 3901 3902 static struct mbuf ** 3903 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3904 { 3905 int next, size; 3906 struct mbuf **items; 3907 3908 size = r->size; 3909 next = (cidx + CACHE_PTR_INCREMENT) & (size - 1); 3910 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3911 3912 prefetch(items[(cidx + offset) & (size - 1)]); 3913 if (remaining > 1) { 3914 prefetch2cachelines(&items[next]); 3915 prefetch2cachelines(items[(cidx + offset + 1) & (size - 1)]); 3916 prefetch2cachelines(items[(cidx + offset + 2) & (size - 1)]); 3917 prefetch2cachelines(items[(cidx + offset + 3) & (size - 1)]); 3918 } 3919 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size - 1)])); 3920 } 3921 3922 static void 3923 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3924 { 3925 3926 ifmp_ring_check_drainage(txq->ift_br, budget); 3927 } 3928 3929 static uint32_t 3930 iflib_txq_can_drain(struct ifmp_ring *r) 3931 { 3932 iflib_txq_t txq = r->cookie; 3933 if_ctx_t ctx = txq->ift_ctx; 3934 3935 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx)) 3936 return (1); 3937 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3938 BUS_DMASYNC_POSTREAD); 3939 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3940 false)); 3941 } 3942 3943 static uint32_t 3944 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3945 { 3946 iflib_txq_t txq = r->cookie; 3947 if_ctx_t ctx = txq->ift_ctx; 3948 if_t ifp = ctx->ifc_ifp; 3949 struct mbuf *m, **mp; 3950 int avail, bytes_sent, consumed, count, err, i; 3951 int mcast_sent, pkt_sent, reclaimed; 3952 bool do_prefetch, rang, ring; 3953 3954 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3955 !LINK_ACTIVE(ctx))) { 3956 DBG_COUNTER_INC(txq_drain_notready); 3957 return (0); 3958 } 3959 reclaimed = iflib_completed_tx_reclaim(txq, NULL); 3960 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending); 3961 avail = IDXDIFF(pidx, cidx, r->size); 3962 3963 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3964 /* 3965 * The driver is unloading so we need to free all pending packets. 3966 */ 3967 DBG_COUNTER_INC(txq_drain_flushing); 3968 for (i = 0; i < avail; i++) { 3969 if (__predict_true(r->items[(cidx + i) & (r->size - 1)] != (void *)txq)) 3970 m_freem(r->items[(cidx + i) & (r->size - 1)]); 3971 r->items[(cidx + i) & (r->size - 1)] = NULL; 3972 } 3973 return (avail); 3974 } 3975 3976 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3977 CALLOUT_LOCK(txq); 3978 callout_stop(&txq->ift_timer); 3979 CALLOUT_UNLOCK(txq); 3980 DBG_COUNTER_INC(txq_drain_oactive); 3981 return (0); 3982 } 3983 3984 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3985 count = MIN(avail, TX_BATCH_SIZE); 3986 #ifdef INVARIANTS 3987 if (iflib_verbose_debug) 3988 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __func__, 3989 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3990 #endif 3991 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3992 err = 0; 3993 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx); i++) { 3994 int rem = do_prefetch ? count - i : 0; 3995 3996 mp = _ring_peek_one(r, cidx, i, rem); 3997 MPASS(mp != NULL && *mp != NULL); 3998 3999 /* 4000 * Completion interrupts will use the address of the txq 4001 * as a sentinel to enqueue _something_ in order to acquire 4002 * the lock on the mp_ring (there's no direct lock call). 4003 * We obviously whave to check for these sentinel cases 4004 * and skip them. 4005 */ 4006 if (__predict_false(*mp == (struct mbuf *)txq)) { 4007 consumed++; 4008 continue; 4009 } 4010 err = iflib_encap(txq, mp, &bytes_sent, &pkt_sent); 4011 if (__predict_false(err)) { 4012 /* no room - bail out */ 4013 if (err == ENOBUFS) 4014 break; 4015 consumed++; 4016 /* we can't send this packet - skip it */ 4017 continue; 4018 } 4019 consumed++; 4020 m = *mp; 4021 DBG_COUNTER_INC(tx_sent); 4022 mcast_sent += !!(m->m_flags & M_MCAST); 4023 4024 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))) 4025 break; 4026 ETHER_BPF_MTAP(ifp, m); 4027 rang = iflib_txd_db_check(txq, false); 4028 } 4029 4030 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 4031 ring = rang ? false : (iflib_min_tx_latency | err | (!!txq->ift_reclaim_thresh)); 4032 iflib_txd_db_check(txq, ring); 4033 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 4034 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 4035 if (mcast_sent) 4036 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 4037 #ifdef INVARIANTS 4038 if (iflib_verbose_debug) 4039 printf("consumed=%d\n", consumed); 4040 #endif 4041 return (consumed); 4042 } 4043 4044 static uint32_t 4045 iflib_txq_drain_always(struct ifmp_ring *r) 4046 { 4047 return (1); 4048 } 4049 4050 static uint32_t 4051 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 4052 { 4053 int i, avail; 4054 struct mbuf **mp; 4055 iflib_txq_t txq; 4056 4057 txq = r->cookie; 4058 4059 CALLOUT_LOCK(txq); 4060 callout_stop(&txq->ift_timer); 4061 CALLOUT_UNLOCK(txq); 4062 4063 avail = IDXDIFF(pidx, cidx, r->size); 4064 for (i = 0; i < avail; i++) { 4065 mp = _ring_peek_one(r, cidx, i, avail - i); 4066 if (__predict_false(*mp == (struct mbuf *)txq)) 4067 continue; 4068 m_freem(*mp); 4069 DBG_COUNTER_INC(tx_frees); 4070 } 4071 MPASS(ifmp_ring_is_stalled(r) == 0); 4072 return (avail); 4073 } 4074 4075 static void 4076 iflib_ifmp_purge(iflib_txq_t txq) 4077 { 4078 struct ifmp_ring *r; 4079 4080 r = txq->ift_br; 4081 r->drain = iflib_txq_drain_free; 4082 r->can_drain = iflib_txq_drain_always; 4083 4084 ifmp_ring_check_drainage(r, r->size); 4085 4086 r->drain = iflib_txq_drain; 4087 r->can_drain = iflib_txq_can_drain; 4088 } 4089 4090 static void 4091 _task_fn_tx(void *context) 4092 { 4093 iflib_txq_t txq = context; 4094 if_ctx_t ctx = txq->ift_ctx; 4095 if_t ifp = ctx->ifc_ifp; 4096 int abdicate = ctx->ifc_sysctl_tx_abdicate; 4097 4098 #ifdef IFLIB_DIAGNOSTICS 4099 txq->ift_cpu_exec_count[curcpu]++; 4100 #endif 4101 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4102 return; 4103 #ifdef DEV_NETMAP 4104 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 4105 netmap_tx_irq(ifp, txq->ift_id)) 4106 goto skip_ifmp; 4107 #endif 4108 if (ctx->ifc_sysctl_simple_tx) { 4109 mtx_lock(&txq->ift_mtx); 4110 (void)iflib_completed_tx_reclaim(txq, NULL); 4111 mtx_unlock(&txq->ift_mtx); 4112 goto skip_ifmp; 4113 } 4114 #ifdef ALTQ 4115 if (if_altq_is_enabled(ifp)) 4116 iflib_altq_if_start(ifp); 4117 #endif 4118 if (txq->ift_db_pending) 4119 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 4120 else if (!abdicate) 4121 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4122 /* 4123 * When abdicating, we always need to check drainage, not just when we don't enqueue 4124 */ 4125 if (abdicate) 4126 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4127 4128 skip_ifmp: 4129 if (ctx->ifc_flags & IFC_LEGACY) 4130 IFDI_INTR_ENABLE(ctx); 4131 else 4132 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 4133 } 4134 4135 static void 4136 _task_fn_rx(void *context) 4137 { 4138 iflib_rxq_t rxq = context; 4139 if_ctx_t ctx = rxq->ifr_ctx; 4140 uint8_t more; 4141 uint16_t budget; 4142 #ifdef DEV_NETMAP 4143 u_int work = 0; 4144 int nmirq; 4145 #endif 4146 4147 #ifdef IFLIB_DIAGNOSTICS 4148 rxq->ifr_cpu_exec_count[curcpu]++; 4149 #endif 4150 DBG_COUNTER_INC(task_fn_rxs); 4151 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4152 return; 4153 #ifdef DEV_NETMAP 4154 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 4155 if (nmirq != NM_IRQ_PASS) { 4156 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 4157 goto skip_rxeof; 4158 } 4159 #endif 4160 budget = ctx->ifc_sysctl_rx_budget; 4161 if (budget == 0) 4162 budget = 16; /* XXX */ 4163 more = iflib_rxeof(rxq, budget); 4164 #ifdef DEV_NETMAP 4165 skip_rxeof: 4166 #endif 4167 if ((more & IFLIB_RXEOF_MORE) == 0) { 4168 if (ctx->ifc_flags & IFC_LEGACY) 4169 IFDI_INTR_ENABLE(ctx); 4170 else 4171 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 4172 DBG_COUNTER_INC(rx_intr_enables); 4173 } 4174 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4175 return; 4176 4177 if (more & IFLIB_RXEOF_MORE) 4178 GROUPTASK_ENQUEUE(&rxq->ifr_task); 4179 else if (more & IFLIB_RXEOF_EMPTY) 4180 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 4181 } 4182 4183 static void 4184 _task_fn_admin(void *context, int pending) 4185 { 4186 if_ctx_t ctx = context; 4187 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 4188 iflib_txq_t txq; 4189 int i; 4190 bool oactive, running, do_reset, do_watchdog, in_detach; 4191 4192 STATE_LOCK(ctx); 4193 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 4194 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 4195 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 4196 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 4197 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 4198 ctx->ifc_flags &= ~(IFC_DO_RESET | IFC_DO_WATCHDOG); 4199 STATE_UNLOCK(ctx); 4200 4201 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4202 return; 4203 if (in_detach) 4204 return; 4205 4206 CTX_LOCK(ctx); 4207 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4208 CALLOUT_LOCK(txq); 4209 callout_stop(&txq->ift_timer); 4210 CALLOUT_UNLOCK(txq); 4211 } 4212 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ) 4213 IFDI_ADMIN_COMPLETION_HANDLE(ctx); 4214 if (do_watchdog) { 4215 ctx->ifc_watchdog_events++; 4216 IFDI_WATCHDOG_RESET(ctx); 4217 } 4218 IFDI_UPDATE_ADMIN_STATUS(ctx); 4219 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4220 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 4221 txq->ift_timer.c_cpu); 4222 } 4223 IFDI_LINK_INTR_ENABLE(ctx); 4224 if (do_reset) 4225 iflib_if_init_locked(ctx); 4226 CTX_UNLOCK(ctx); 4227 4228 if (LINK_ACTIVE(ctx) == 0) 4229 return; 4230 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 4231 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4232 } 4233 4234 static void 4235 _task_fn_iov(void *context, int pending) 4236 { 4237 if_ctx_t ctx = context; 4238 4239 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 4240 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4241 return; 4242 4243 CTX_LOCK(ctx); 4244 IFDI_VFLR_HANDLE(ctx); 4245 CTX_UNLOCK(ctx); 4246 } 4247 4248 static int 4249 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4250 { 4251 int err; 4252 if_int_delay_info_t info; 4253 if_ctx_t ctx; 4254 4255 info = (if_int_delay_info_t)arg1; 4256 ctx = info->iidi_ctx; 4257 info->iidi_req = req; 4258 info->iidi_oidp = oidp; 4259 CTX_LOCK(ctx); 4260 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 4261 CTX_UNLOCK(ctx); 4262 return (err); 4263 } 4264 4265 /********************************************************************* 4266 * 4267 * IFNET FUNCTIONS 4268 * 4269 **********************************************************************/ 4270 4271 static void 4272 iflib_if_init_locked(if_ctx_t ctx) 4273 { 4274 iflib_stop(ctx); 4275 iflib_init_locked(ctx); 4276 } 4277 4278 static void 4279 iflib_if_init(void *arg) 4280 { 4281 if_ctx_t ctx = arg; 4282 4283 CTX_LOCK(ctx); 4284 iflib_if_init_locked(ctx); 4285 CTX_UNLOCK(ctx); 4286 } 4287 4288 static int 4289 iflib_if_transmit(if_t ifp, struct mbuf *m) 4290 { 4291 if_ctx_t ctx = if_getsoftc(ifp); 4292 iflib_txq_t txq; 4293 int err, qidx; 4294 int abdicate; 4295 4296 if (__predict_false((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 4297 DBG_COUNTER_INC(tx_frees); 4298 m_freem(m); 4299 return (ENETDOWN); 4300 } 4301 4302 MPASS(m->m_nextpkt == NULL); 4303 /* ALTQ-enabled interfaces always use queue 0. */ 4304 qidx = 0; 4305 /* Use driver-supplied queue selection method if it exists */ 4306 if (ctx->isc_txq_select_v2) { 4307 struct if_pkt_info pi; 4308 uint64_t early_pullups = 0; 4309 memset(&pi, 0, sizeof(pi)); 4310 4311 err = iflib_parse_header_partial(&pi, &m, &early_pullups); 4312 if (__predict_false(err != 0)) { 4313 /* Assign pullups for bad pkts to default queue */ 4314 ctx->ifc_txqs[0].ift_pullups += early_pullups; 4315 DBG_COUNTER_INC(encap_txd_encap_fail); 4316 return (err); 4317 } 4318 /* Let driver make queueing decision */ 4319 qidx = ctx->isc_txq_select_v2(ctx->ifc_softc, m, &pi); 4320 ctx->ifc_txqs[qidx].ift_pullups += early_pullups; 4321 } 4322 /* Backwards compatibility w/ simpler queue select */ 4323 else if (ctx->isc_txq_select) 4324 qidx = ctx->isc_txq_select(ctx->ifc_softc, m); 4325 /* If not, use iflib's standard method */ 4326 else if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !if_altq_is_enabled(ifp)) 4327 qidx = QIDX(ctx, m); 4328 4329 /* Set TX queue */ 4330 txq = &ctx->ifc_txqs[qidx]; 4331 4332 #ifdef DRIVER_BACKPRESSURE 4333 if (txq->ift_closed) { 4334 while (m != NULL) { 4335 next = m->m_nextpkt; 4336 m->m_nextpkt = NULL; 4337 m_freem(m); 4338 DBG_COUNTER_INC(tx_frees); 4339 m = next; 4340 } 4341 return (ENOBUFS); 4342 } 4343 #endif 4344 #ifdef notyet 4345 qidx = count = 0; 4346 mp = marr; 4347 next = m; 4348 do { 4349 count++; 4350 next = next->m_nextpkt; 4351 } while (next != NULL); 4352 4353 if (count > nitems(marr)) 4354 if ((mp = malloc(count * sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4355 /* XXX check nextpkt */ 4356 m_freem(m); 4357 /* XXX simplify for now */ 4358 DBG_COUNTER_INC(tx_frees); 4359 return (ENOBUFS); 4360 } 4361 for (next = m, i = 0; next != NULL; i++) { 4362 mp[i] = next; 4363 next = next->m_nextpkt; 4364 mp[i]->m_nextpkt = NULL; 4365 } 4366 #endif 4367 DBG_COUNTER_INC(tx_seen); 4368 abdicate = ctx->ifc_sysctl_tx_abdicate; 4369 4370 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4371 4372 if (abdicate) 4373 GROUPTASK_ENQUEUE(&txq->ift_task); 4374 if (err) { 4375 if (!abdicate) 4376 GROUPTASK_ENQUEUE(&txq->ift_task); 4377 /* support forthcoming later */ 4378 #ifdef DRIVER_BACKPRESSURE 4379 txq->ift_closed = TRUE; 4380 #endif 4381 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4382 m_freem(m); 4383 DBG_COUNTER_INC(tx_frees); 4384 if (err == ENOBUFS) 4385 if_inc_counter(ifp, IFCOUNTER_OQDROPS, 1); 4386 else 4387 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 4388 } 4389 4390 return (err); 4391 } 4392 4393 #ifdef ALTQ 4394 /* 4395 * The overall approach to integrating iflib with ALTQ is to continue to use 4396 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4397 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4398 * is redundant/unnecessary, but doing so minimizes the amount of 4399 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4400 * redundantly queueing to an intermediate mp_ring is swamped by the 4401 * performance limitations inherent in using ALTQ. 4402 * 4403 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4404 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4405 * given interface. If ALTQ is enabled for an interface, then all 4406 * transmitted packets for that interface will be submitted to the ALTQ 4407 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4408 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4409 * update stats that the iflib machinery handles, and which is sensitve to 4410 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4411 * will be installed as the start routine for use by ALTQ facilities that 4412 * need to trigger queue drains on a scheduled basis. 4413 * 4414 */ 4415 static void 4416 iflib_altq_if_start(if_t ifp) 4417 { 4418 struct ifaltq *ifq = &ifp->if_snd; /* XXX - DRVAPI */ 4419 struct mbuf *m; 4420 4421 IFQ_LOCK(ifq); 4422 IFQ_DEQUEUE_NOLOCK(ifq, m); 4423 while (m != NULL) { 4424 iflib_if_transmit(ifp, m); 4425 IFQ_DEQUEUE_NOLOCK(ifq, m); 4426 } 4427 IFQ_UNLOCK(ifq); 4428 } 4429 4430 static int 4431 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4432 { 4433 int err; 4434 4435 if (if_altq_is_enabled(ifp)) { 4436 IFQ_ENQUEUE(&ifp->if_snd, m, err); /* XXX - DRVAPI */ 4437 if (err == 0) 4438 iflib_altq_if_start(ifp); 4439 } else 4440 err = iflib_if_transmit(ifp, m); 4441 4442 return (err); 4443 } 4444 #endif /* ALTQ */ 4445 4446 static void 4447 iflib_if_qflush(if_t ifp) 4448 { 4449 if_ctx_t ctx = if_getsoftc(ifp); 4450 iflib_txq_t txq = ctx->ifc_txqs; 4451 int i; 4452 4453 STATE_LOCK(ctx); 4454 ctx->ifc_flags |= IFC_QFLUSH; 4455 STATE_UNLOCK(ctx); 4456 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4457 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4458 iflib_txq_check_drain(txq, 0); 4459 STATE_LOCK(ctx); 4460 ctx->ifc_flags &= ~IFC_QFLUSH; 4461 STATE_UNLOCK(ctx); 4462 4463 /* 4464 * When ALTQ is enabled, this will also take care of purging the 4465 * ALTQ queue(s). 4466 */ 4467 if_qflush(ifp); 4468 } 4469 4470 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4471 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4472 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4473 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG) 4474 4475 static int 4476 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4477 { 4478 if_ctx_t ctx = if_getsoftc(ifp); 4479 struct ifreq *ifr = (struct ifreq *)data; 4480 #if defined(INET) || defined(INET6) 4481 struct ifaddr *ifa = (struct ifaddr *)data; 4482 #endif 4483 bool avoid_reset = false; 4484 int err = 0, reinit = 0, bits; 4485 4486 switch (command) { 4487 case SIOCSIFADDR: 4488 #ifdef INET 4489 if (ifa->ifa_addr->sa_family == AF_INET) 4490 avoid_reset = true; 4491 #endif 4492 #ifdef INET6 4493 if (ifa->ifa_addr->sa_family == AF_INET6) 4494 avoid_reset = true; 4495 #endif 4496 /* 4497 * Calling init results in link renegotiation, 4498 * so we avoid doing it when possible. 4499 */ 4500 if (avoid_reset) { 4501 if_setflagbits(ifp, IFF_UP, 0); 4502 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4503 reinit = 1; 4504 #ifdef INET 4505 if (!(if_getflags(ifp) & IFF_NOARP)) 4506 arp_ifinit(ifp, ifa); 4507 #endif 4508 } else 4509 err = ether_ioctl(ifp, command, data); 4510 break; 4511 case SIOCSIFMTU: 4512 CTX_LOCK(ctx); 4513 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4514 CTX_UNLOCK(ctx); 4515 break; 4516 } 4517 bits = if_getdrvflags(ifp); 4518 /* stop the driver and free any clusters before proceeding */ 4519 iflib_stop(ctx); 4520 4521 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4522 STATE_LOCK(ctx); 4523 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4524 ctx->ifc_flags |= IFC_MULTISEG; 4525 else 4526 ctx->ifc_flags &= ~IFC_MULTISEG; 4527 STATE_UNLOCK(ctx); 4528 err = if_setmtu(ifp, ifr->ifr_mtu); 4529 } 4530 iflib_init_locked(ctx); 4531 STATE_LOCK(ctx); 4532 if_setdrvflags(ifp, bits); 4533 STATE_UNLOCK(ctx); 4534 CTX_UNLOCK(ctx); 4535 break; 4536 case SIOCSIFFLAGS: 4537 CTX_LOCK(ctx); 4538 if (if_getflags(ifp) & IFF_UP) { 4539 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4540 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4541 (IFF_PROMISC | IFF_ALLMULTI)) { 4542 CTX_UNLOCK(ctx); 4543 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4544 CTX_LOCK(ctx); 4545 } 4546 } else 4547 reinit = 1; 4548 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4549 iflib_stop(ctx); 4550 } 4551 ctx->ifc_if_flags = if_getflags(ifp); 4552 CTX_UNLOCK(ctx); 4553 break; 4554 case SIOCADDMULTI: 4555 case SIOCDELMULTI: 4556 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4557 CTX_LOCK(ctx); 4558 IFDI_INTR_DISABLE(ctx); 4559 IFDI_MULTI_SET(ctx); 4560 IFDI_INTR_ENABLE(ctx); 4561 CTX_UNLOCK(ctx); 4562 } 4563 break; 4564 case SIOCSIFMEDIA: 4565 CTX_LOCK(ctx); 4566 IFDI_MEDIA_SET(ctx); 4567 CTX_UNLOCK(ctx); 4568 /* FALLTHROUGH */ 4569 case SIOCGIFMEDIA: 4570 case SIOCGIFXMEDIA: 4571 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4572 break; 4573 case SIOCGI2C: 4574 /* FALLTHROUGH */ 4575 case SIOCGI2CPB: 4576 { 4577 struct ifi2creq i2c; 4578 if_shared_ctx_t sctx = ctx->ifc_sctx; 4579 4580 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4581 if (err != 0) 4582 break; 4583 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4584 err = EINVAL; 4585 break; 4586 } 4587 if (i2c.len > sizeof(i2c.data)) { 4588 err = EINVAL; 4589 break; 4590 } 4591 if (command == SIOCGI2C) { 4592 i2c.page = i2c.bank = 0; 4593 } else if ((sctx->isc_flags & IFLIB_I2C_PAGE_BANK) == 0) { 4594 err = EINVAL; 4595 break; 4596 } 4597 4598 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4599 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4600 sizeof(i2c)); 4601 break; 4602 } 4603 case SIOCSIFCAP: 4604 { 4605 int mask, setmask, oldmask; 4606 4607 oldmask = if_getcapenable(ifp); 4608 mask = ifr->ifr_reqcap ^ oldmask; 4609 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG; 4610 setmask = 0; 4611 #ifdef TCP_OFFLOAD 4612 setmask |= mask & (IFCAP_TOE4 | IFCAP_TOE6); 4613 #endif 4614 setmask |= (mask & IFCAP_FLAGS); 4615 setmask |= (mask & IFCAP_WOL); 4616 4617 /* 4618 * If any RX csum has changed, change all the ones that 4619 * are supported by the driver. 4620 */ 4621 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4622 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4623 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4624 } 4625 4626 /* 4627 * want to ensure that traffic has stopped before we change any of the flags 4628 */ 4629 if (setmask) { 4630 CTX_LOCK(ctx); 4631 bits = if_getdrvflags(ifp); 4632 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4633 iflib_stop(ctx); 4634 STATE_LOCK(ctx); 4635 if_togglecapenable(ifp, setmask); 4636 ctx->ifc_softc_ctx.isc_capenable ^= setmask; 4637 STATE_UNLOCK(ctx); 4638 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4639 iflib_init_locked(ctx); 4640 STATE_LOCK(ctx); 4641 if_setdrvflags(ifp, bits); 4642 STATE_UNLOCK(ctx); 4643 CTX_UNLOCK(ctx); 4644 } 4645 if_vlancap(ifp); 4646 break; 4647 } 4648 case SIOCGPRIVATE_0: 4649 case SIOCSDRVSPEC: 4650 case SIOCGDRVSPEC: 4651 CTX_LOCK(ctx); 4652 err = IFDI_PRIV_IOCTL(ctx, command, data); 4653 CTX_UNLOCK(ctx); 4654 break; 4655 case SIOCGIFDOWNREASON: 4656 CTX_LOCK(ctx); 4657 err = IFDI_GET_DOWNREASON(ctx, (struct ifdownreason *)data); 4658 CTX_UNLOCK(ctx); 4659 break; 4660 default: 4661 err = ether_ioctl(ifp, command, data); 4662 break; 4663 } 4664 if (reinit) 4665 iflib_if_init(ctx); 4666 return (err); 4667 } 4668 4669 static uint64_t 4670 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4671 { 4672 if_ctx_t ctx = if_getsoftc(ifp); 4673 4674 return (IFDI_GET_COUNTER(ctx, cnt)); 4675 } 4676 4677 /********************************************************************* 4678 * 4679 * OTHER FUNCTIONS EXPORTED TO THE STACK 4680 * 4681 **********************************************************************/ 4682 4683 static void 4684 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4685 { 4686 if_ctx_t ctx = if_getsoftc(ifp); 4687 4688 if ((void *)ctx != arg) 4689 return; 4690 4691 if ((vtag == 0) || (vtag > 4095)) 4692 return; 4693 4694 if (iflib_in_detach(ctx)) 4695 return; 4696 4697 CTX_LOCK(ctx); 4698 /* Driver may need all untagged packets to be flushed */ 4699 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4700 iflib_stop(ctx); 4701 IFDI_VLAN_REGISTER(ctx, vtag); 4702 /* Re-init to load the changes, if required */ 4703 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4704 iflib_init_locked(ctx); 4705 CTX_UNLOCK(ctx); 4706 } 4707 4708 static void 4709 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4710 { 4711 if_ctx_t ctx = if_getsoftc(ifp); 4712 4713 if ((void *)ctx != arg) 4714 return; 4715 4716 if ((vtag == 0) || (vtag > 4095)) 4717 return; 4718 4719 CTX_LOCK(ctx); 4720 /* Driver may need all tagged packets to be flushed */ 4721 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4722 iflib_stop(ctx); 4723 IFDI_VLAN_UNREGISTER(ctx, vtag); 4724 /* Re-init to load the changes, if required */ 4725 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4726 iflib_init_locked(ctx); 4727 CTX_UNLOCK(ctx); 4728 } 4729 4730 static void 4731 iflib_led_func(void *arg, int onoff) 4732 { 4733 if_ctx_t ctx = arg; 4734 4735 CTX_LOCK(ctx); 4736 IFDI_LED_FUNC(ctx, onoff); 4737 CTX_UNLOCK(ctx); 4738 } 4739 4740 /********************************************************************* 4741 * 4742 * BUS FUNCTION DEFINITIONS 4743 * 4744 **********************************************************************/ 4745 4746 int 4747 iflib_device_probe(device_t dev) 4748 { 4749 const pci_vendor_info_t *ent; 4750 if_shared_ctx_t sctx; 4751 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4752 uint16_t pci_vendor_id; 4753 4754 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4755 return (ENOTSUP); 4756 4757 pci_vendor_id = pci_get_vendor(dev); 4758 pci_device_id = pci_get_device(dev); 4759 pci_subvendor_id = pci_get_subvendor(dev); 4760 pci_subdevice_id = pci_get_subdevice(dev); 4761 pci_rev_id = pci_get_revid(dev); 4762 if (sctx->isc_parse_devinfo != NULL) 4763 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4764 4765 ent = sctx->isc_vendor_info; 4766 while (ent->pvi_vendor_id != 0) { 4767 if (pci_vendor_id != ent->pvi_vendor_id) { 4768 ent++; 4769 continue; 4770 } 4771 if ((pci_device_id == ent->pvi_device_id) && 4772 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4773 (ent->pvi_subvendor_id == 0)) && 4774 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4775 (ent->pvi_subdevice_id == 0)) && 4776 ((pci_rev_id == ent->pvi_rev_id) || 4777 (ent->pvi_rev_id == 0))) { 4778 device_set_desc_copy(dev, ent->pvi_name); 4779 /* this needs to be changed to zero if the bus probing code 4780 * ever stops re-probing on best match because the sctx 4781 * may have its values over written by register calls 4782 * in subsequent probes 4783 */ 4784 return (BUS_PROBE_DEFAULT); 4785 } 4786 ent++; 4787 } 4788 return (ENXIO); 4789 } 4790 4791 int 4792 iflib_device_probe_vendor(device_t dev) 4793 { 4794 int probe; 4795 4796 probe = iflib_device_probe(dev); 4797 if (probe == BUS_PROBE_DEFAULT) 4798 return (BUS_PROBE_VENDOR); 4799 else 4800 return (probe); 4801 } 4802 4803 static void 4804 iflib_reset_qvalues(if_ctx_t ctx) 4805 { 4806 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4807 if_shared_ctx_t sctx = ctx->ifc_sctx; 4808 device_t dev = ctx->ifc_dev; 4809 int i; 4810 4811 if (ctx->ifc_sysctl_ntxqs != 0) 4812 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4813 if (ctx->ifc_sysctl_nrxqs != 0) 4814 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4815 4816 for (i = 0; i < sctx->isc_ntxqs; i++) { 4817 if (ctx->ifc_sysctl_ntxds[i] != 0) 4818 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4819 else 4820 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4821 } 4822 4823 for (i = 0; i < sctx->isc_nrxqs; i++) { 4824 if (ctx->ifc_sysctl_nrxds[i] != 0) 4825 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4826 else 4827 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4828 } 4829 4830 for (i = 0; i < sctx->isc_nrxqs; i++) { 4831 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4832 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4833 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4834 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4835 } 4836 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4837 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4838 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4839 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4840 } 4841 if (!powerof2(scctx->isc_nrxd[i])) { 4842 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4843 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4844 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4845 } 4846 } 4847 4848 for (i = 0; i < sctx->isc_ntxqs; i++) { 4849 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4850 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4851 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4852 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4853 } 4854 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4855 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4856 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4857 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4858 } 4859 if (!powerof2(scctx->isc_ntxd[i])) { 4860 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4861 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4862 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4863 } 4864 } 4865 scctx->isc_tx_pad = 2; 4866 } 4867 4868 static void 4869 iflib_add_pfil(if_ctx_t ctx) 4870 { 4871 struct pfil_head *pfil; 4872 struct pfil_head_args pa; 4873 iflib_rxq_t rxq; 4874 int i; 4875 4876 pa.pa_version = PFIL_VERSION; 4877 pa.pa_flags = PFIL_IN; 4878 pa.pa_type = PFIL_TYPE_ETHERNET; 4879 pa.pa_headname = if_name(ctx->ifc_ifp); 4880 pfil = pfil_head_register(&pa); 4881 4882 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4883 rxq->pfil = pfil; 4884 } 4885 } 4886 4887 static void 4888 iflib_rem_pfil(if_ctx_t ctx) 4889 { 4890 struct pfil_head *pfil; 4891 iflib_rxq_t rxq; 4892 int i; 4893 4894 rxq = ctx->ifc_rxqs; 4895 pfil = rxq->pfil; 4896 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4897 rxq->pfil = NULL; 4898 } 4899 pfil_head_unregister(pfil); 4900 } 4901 4902 4903 /* 4904 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from 4905 * cpuid and wrapping as necessary. 4906 */ 4907 static unsigned int 4908 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n) 4909 { 4910 unsigned int first_valid; 4911 unsigned int last_valid; 4912 4913 /* cpuid should always be in the valid set */ 4914 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4915 4916 /* valid set should never be empty */ 4917 MPASS(!CPU_EMPTY(&ctx->ifc_cpus)); 4918 4919 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4920 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4921 n = n % CPU_COUNT(&ctx->ifc_cpus); 4922 while (n > 0) { 4923 do { 4924 cpuid++; 4925 if (cpuid > last_valid) 4926 cpuid = first_valid; 4927 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4928 n--; 4929 } 4930 4931 return (cpuid); 4932 } 4933 4934 /* 4935 * CPU mapping behaviors 4936 * --------------------- 4937 * 'separate txrx' refers to the separate_txrx sysctl 4938 * 'use logical' refers to the use_logical_cores sysctl 4939 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded 4940 * 4941 * separate use INTR 4942 * txrx logical CPUS result 4943 * ---------- --------- ------ ------------------------------------------------ 4944 * - - X RX and TX queues mapped to consecutive physical 4945 * cores with RX/TX pairs on same core and excess 4946 * of either following 4947 * - X X RX and TX queues mapped to consecutive cores 4948 * of any type with RX/TX pairs on same core and 4949 * excess of either following 4950 * X - X RX and TX queues mapped to consecutive physical 4951 * cores; all RX then all TX 4952 * X X X RX queues mapped to consecutive physical cores 4953 * first, then TX queues mapped to L2 neighbor of 4954 * the corresponding RX queue if one exists, 4955 * otherwise to consecutive physical cores 4956 * - n/a - RX and TX queues mapped to consecutive cores of 4957 * any type with RX/TX pairs on same core and excess 4958 * of either following 4959 * X n/a - RX and TX queues mapped to consecutive cores of 4960 * any type; all RX then all TX 4961 */ 4962 static unsigned int 4963 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid, 4964 bool is_tx) 4965 { 4966 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4967 unsigned int core_index; 4968 4969 if (ctx->ifc_sysctl_separate_txrx) { 4970 /* 4971 * When using separate CPUs for TX and RX, the assignment 4972 * will always be of a consecutive CPU out of the set of 4973 * context CPUs, except for the specific case where the 4974 * context CPUs are phsyical cores, the use of logical cores 4975 * has been enabled, the assignment is for TX, the TX qid 4976 * corresponds to an RX qid, and the CPU assigned to the 4977 * corresponding RX queue has an L2 neighbor. 4978 */ 4979 if (ctx->ifc_sysctl_use_logical_cores && 4980 ctx->ifc_cpus_are_physical_cores && 4981 is_tx && qid < scctx->isc_nrxqsets) { 4982 int l2_neighbor; 4983 unsigned int rx_cpuid; 4984 4985 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid); 4986 l2_neighbor = sched_find_l2_neighbor(rx_cpuid); 4987 if (l2_neighbor != -1) { 4988 return (l2_neighbor); 4989 } 4990 /* 4991 * ... else fall through to the normal 4992 * consecutive-after-RX assignment scheme. 4993 * 4994 * Note that we are assuming that all RX queue CPUs 4995 * have an L2 neighbor, or all do not. If a mixed 4996 * scenario is possible, we will have to keep track 4997 * separately of how many queues prior to this one 4998 * were not able to be assigned to an L2 neighbor. 4999 */ 5000 } 5001 if (is_tx) 5002 core_index = scctx->isc_nrxqsets + qid; 5003 else 5004 core_index = qid; 5005 } else { 5006 core_index = qid; 5007 } 5008 5009 return (cpuid_advance(ctx, base_cpuid, core_index)); 5010 } 5011 5012 static uint16_t 5013 get_ctx_core_offset(if_ctx_t ctx) 5014 { 5015 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5016 struct cpu_offset *op; 5017 cpuset_t assigned_cpus; 5018 unsigned int cores_consumed; 5019 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset; 5020 unsigned int first_valid; 5021 unsigned int last_valid; 5022 unsigned int i; 5023 5024 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 5025 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 5026 5027 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) { 5028 /* 5029 * Align the user-chosen base CPU ID to the next valid CPU 5030 * for this device. If the chosen base CPU ID is smaller 5031 * than the first valid CPU or larger than the last valid 5032 * CPU, we assume the user does not know what the valid 5033 * range is for this device and is thinking in terms of a 5034 * zero-based reference frame, and so we shift the given 5035 * value into the valid range (and wrap accordingly) so the 5036 * intent is translated to the proper frame of reference. 5037 * If the base CPU ID is within the valid first/last, but 5038 * does not correspond to a valid CPU, it is advanced to the 5039 * next valid CPU (wrapping if necessary). 5040 */ 5041 if (base_cpuid < first_valid || base_cpuid > last_valid) { 5042 /* shift from zero-based to first_valid-based */ 5043 base_cpuid += first_valid; 5044 /* wrap to range [first_valid, last_valid] */ 5045 base_cpuid = (base_cpuid - first_valid) % 5046 (last_valid - first_valid + 1); 5047 } 5048 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) { 5049 /* 5050 * base_cpuid is in [first_valid, last_valid], but 5051 * not a member of the valid set. In this case, 5052 * there will always be a member of the valid set 5053 * with a CPU ID that is greater than base_cpuid, 5054 * and we simply advance to it. 5055 */ 5056 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) 5057 base_cpuid++; 5058 } 5059 return (base_cpuid); 5060 } 5061 5062 /* 5063 * Determine how many cores will be consumed by performing the CPU 5064 * assignments and counting how many of the assigned CPUs correspond 5065 * to CPUs in the set of context CPUs. This is done using the CPU 5066 * ID first_valid as the base CPU ID, as the base CPU must be within 5067 * the set of context CPUs. 5068 * 5069 * Note not all assigned CPUs will be in the set of context CPUs 5070 * when separate CPUs are being allocated to TX and RX queues, 5071 * assignment to logical cores has been enabled, the set of context 5072 * CPUs contains only physical CPUs, and TX queues are mapped to L2 5073 * neighbors of CPUs that RX queues have been mapped to - in this 5074 * case we do only want to count how many CPUs in the set of context 5075 * CPUs have been consumed, as that determines the next CPU in that 5076 * set to start allocating at for the next device for which 5077 * core_offset is not set. 5078 */ 5079 CPU_ZERO(&assigned_cpus); 5080 for (i = 0; i < scctx->isc_ntxqsets; i++) 5081 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true), 5082 &assigned_cpus); 5083 for (i = 0; i < scctx->isc_nrxqsets; i++) 5084 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false), 5085 &assigned_cpus); 5086 CPU_AND(&assigned_cpus, &assigned_cpus, &ctx->ifc_cpus); 5087 cores_consumed = CPU_COUNT(&assigned_cpus); 5088 5089 mtx_lock(&cpu_offset_mtx); 5090 SLIST_FOREACH(op, &cpu_offsets, entries) { 5091 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5092 base_cpuid = op->next_cpuid; 5093 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid, 5094 cores_consumed); 5095 MPASS(op->refcount < UINT_MAX); 5096 op->refcount++; 5097 break; 5098 } 5099 } 5100 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) { 5101 base_cpuid = first_valid; 5102 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 5103 M_NOWAIT | M_ZERO); 5104 if (op == NULL) { 5105 device_printf(ctx->ifc_dev, 5106 "allocation for cpu offset failed.\n"); 5107 } else { 5108 op->next_cpuid = cpuid_advance(ctx, base_cpuid, 5109 cores_consumed); 5110 op->refcount = 1; 5111 CPU_COPY(&ctx->ifc_cpus, &op->set); 5112 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 5113 } 5114 } 5115 mtx_unlock(&cpu_offset_mtx); 5116 5117 return (base_cpuid); 5118 } 5119 5120 static void 5121 unref_ctx_core_offset(if_ctx_t ctx) 5122 { 5123 struct cpu_offset *op, *top; 5124 5125 mtx_lock(&cpu_offset_mtx); 5126 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 5127 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5128 MPASS(op->refcount > 0); 5129 op->refcount--; 5130 if (op->refcount == 0) { 5131 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 5132 free(op, M_IFLIB); 5133 } 5134 break; 5135 } 5136 } 5137 mtx_unlock(&cpu_offset_mtx); 5138 } 5139 5140 int 5141 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 5142 { 5143 if_ctx_t ctx; 5144 if_t ifp; 5145 if_softc_ctx_t scctx; 5146 kobjop_desc_t kobj_desc; 5147 kobj_method_t *kobj_method; 5148 int err, msix, rid; 5149 int num_txd, num_rxd; 5150 char namebuf[TASKQUEUE_NAMELEN]; 5151 5152 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK | M_ZERO); 5153 5154 if (sc == NULL) { 5155 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK | M_ZERO); 5156 device_set_softc(dev, ctx); 5157 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5158 } 5159 5160 ctx->ifc_sctx = sctx; 5161 ctx->ifc_dev = dev; 5162 ctx->ifc_softc = sc; 5163 5164 iflib_register(ctx); 5165 iflib_add_device_sysctl_pre(ctx); 5166 5167 scctx = &ctx->ifc_softc_ctx; 5168 ifp = ctx->ifc_ifp; 5169 if (ctx->ifc_sysctl_simple_tx) { 5170 #ifndef ALTQ 5171 if_settransmitfn(ifp, iflib_simple_transmit); 5172 device_printf(dev, "using simple if_transmit\n"); 5173 #else 5174 device_printf(dev, "ALTQ prevents using simple if_transmit\n"); 5175 #endif 5176 } 5177 iflib_reset_qvalues(ctx); 5178 IFNET_WLOCK(); 5179 CTX_LOCK(ctx); 5180 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5181 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5182 goto fail_unlock; 5183 } 5184 _iflib_pre_assert(scctx); 5185 ctx->ifc_txrx = *scctx->isc_txrx; 5186 5187 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR)); 5188 5189 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 5190 ctx->ifc_mediap = scctx->isc_media; 5191 5192 #ifdef INVARIANTS 5193 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5194 MPASS(scctx->isc_tx_csum_flags); 5195 #endif 5196 5197 if_setcapabilities(ifp, 5198 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG); 5199 if_setcapenable(ifp, 5200 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG); 5201 5202 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5203 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5204 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5205 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5206 5207 num_txd = iflib_num_tx_descs(ctx); 5208 num_rxd = iflib_num_rx_descs(ctx); 5209 5210 /* XXX change for per-queue sizes */ 5211 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5212 num_txd, num_rxd); 5213 5214 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5215 scctx->isc_tx_nsegments = max(1, num_txd / 5216 MAX_SINGLE_PACKET_FRACTION); 5217 if (scctx->isc_tx_tso_segments_max > num_txd / 5218 MAX_SINGLE_PACKET_FRACTION) 5219 scctx->isc_tx_tso_segments_max = max(1, 5220 num_txd / MAX_SINGLE_PACKET_FRACTION); 5221 5222 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5223 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5224 /* 5225 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5226 * but some MACs do. 5227 */ 5228 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5229 IP_MAXPACKET)); 5230 /* 5231 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5232 * into account. In the worst case, each of these calls will 5233 * add another mbuf and, thus, the requirement for another DMA 5234 * segment. So for best performance, it doesn't make sense to 5235 * advertize a maximum of TSO segments that typically will 5236 * require defragmentation in iflib_encap(). 5237 */ 5238 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5239 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5240 } 5241 if (scctx->isc_rss_table_size == 0) 5242 scctx->isc_rss_table_size = 64; 5243 scctx->isc_rss_table_mask = scctx->isc_rss_table_size - 1; 5244 5245 /* Create and start admin taskqueue */ 5246 snprintf(namebuf, TASKQUEUE_NAMELEN, "if_%s_tq", device_get_nameunit(dev)); 5247 ctx->ifc_tq = taskqueue_create_fast(namebuf, M_NOWAIT, 5248 taskqueue_thread_enqueue, &ctx->ifc_tq); 5249 if (ctx->ifc_tq == NULL) { 5250 device_printf(dev, "Unable to create admin taskqueue\n"); 5251 return (ENOMEM); 5252 } 5253 5254 err = taskqueue_start_threads(&ctx->ifc_tq, 1, PI_NET, "%s", namebuf); 5255 if (err) { 5256 device_printf(dev, 5257 "Unable to start admin taskqueue threads error: %d\n", 5258 err); 5259 taskqueue_free(ctx->ifc_tq); 5260 return (err); 5261 } 5262 5263 TASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5264 5265 /* Set up cpu set. If it fails, use the set of all CPUs. */ 5266 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 5267 device_printf(dev, "Unable to fetch CPU list\n"); 5268 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 5269 ctx->ifc_cpus_are_physical_cores = false; 5270 } else 5271 ctx->ifc_cpus_are_physical_cores = true; 5272 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 5273 5274 /* 5275 * Now set up MSI or MSI-X, should return us the number of supported 5276 * vectors (will be 1 for a legacy interrupt and MSI). 5277 */ 5278 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 5279 msix = scctx->isc_vectors; 5280 } else if (scctx->isc_msix_bar != 0) 5281 /* 5282 * The simple fact that isc_msix_bar is not 0 does not mean we 5283 * we have a good value there that is known to work. 5284 */ 5285 msix = iflib_msix_init(ctx); 5286 else { 5287 scctx->isc_vectors = 1; 5288 scctx->isc_ntxqsets = 1; 5289 scctx->isc_nrxqsets = 1; 5290 scctx->isc_intr = IFLIB_INTR_LEGACY; 5291 msix = 0; 5292 } 5293 /* Get memory for the station queues */ 5294 if ((err = iflib_queues_alloc(ctx))) { 5295 device_printf(dev, "Unable to allocate queue memory\n"); 5296 goto fail_intr_free; 5297 } 5298 5299 if ((err = iflib_qset_structures_setup(ctx))) 5300 goto fail_queues; 5301 5302 /* 5303 * Now that we know how many queues there are, get the core offset. 5304 */ 5305 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 5306 5307 if (msix > 1) { 5308 /* 5309 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 5310 * aren't the default NULL implementation. 5311 */ 5312 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 5313 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5314 kobj_desc); 5315 if (kobj_method == &kobj_desc->deflt) { 5316 device_printf(dev, 5317 "MSI-X requires ifdi_rx_queue_intr_enable method"); 5318 err = EOPNOTSUPP; 5319 goto fail_queues; 5320 } 5321 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 5322 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5323 kobj_desc); 5324 if (kobj_method == &kobj_desc->deflt) { 5325 device_printf(dev, 5326 "MSI-X requires ifdi_tx_queue_intr_enable method"); 5327 err = EOPNOTSUPP; 5328 goto fail_queues; 5329 } 5330 5331 /* 5332 * Assign the MSI-X vectors. 5333 * Note that the default NULL ifdi_msix_intr_assign method will 5334 * fail here, too. 5335 */ 5336 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 5337 if (err != 0) { 5338 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 5339 err); 5340 goto fail_queues; 5341 } 5342 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 5343 rid = 0; 5344 if (scctx->isc_intr == IFLIB_INTR_MSI) { 5345 MPASS(msix == 1); 5346 rid = 1; 5347 } 5348 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 5349 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 5350 goto fail_queues; 5351 } 5352 } else { 5353 device_printf(dev, 5354 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 5355 err = ENODEV; 5356 goto fail_queues; 5357 } 5358 5359 /* 5360 * It prevents a double-locking panic with iflib_media_status when 5361 * the driver loads. 5362 */ 5363 CTX_UNLOCK(ctx); 5364 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5365 CTX_LOCK(ctx); 5366 5367 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5368 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5369 goto fail_detach; 5370 } 5371 5372 /* 5373 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5374 * This must appear after the call to ether_ifattach() because 5375 * ether_ifattach() sets if_hdrlen to the default value. 5376 */ 5377 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5378 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5379 5380 if ((err = iflib_netmap_attach(ctx))) { 5381 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 5382 goto fail_detach; 5383 } 5384 *ctxp = ctx; 5385 5386 DEBUGNET_SET(ctx->ifc_ifp, iflib); 5387 5388 iflib_add_device_sysctl_post(ctx); 5389 iflib_add_pfil(ctx); 5390 ctx->ifc_flags |= IFC_INIT_DONE; 5391 CTX_UNLOCK(ctx); 5392 IFNET_WUNLOCK(); 5393 5394 return (0); 5395 5396 fail_detach: 5397 CTX_UNLOCK(ctx); 5398 taskqueue_drain(ctx->ifc_tq, &ctx->ifc_admin_task); 5399 ether_ifdetach(ctx->ifc_ifp); 5400 CTX_LOCK(ctx); 5401 fail_queues: 5402 sysctl_ctx_free(&ctx->ifc_sysctl_ctx); 5403 ctx->ifc_sysctl_node = NULL; 5404 /* 5405 * Drain without holding CTX_LOCK so _task_fn_admin can run to 5406 * completion if it needs the context lock. On fail_detach we already 5407 * drained above; a second drain is a no-op when the queue is empty. 5408 */ 5409 CTX_UNLOCK(ctx); 5410 taskqueue_drain(ctx->ifc_tq, &ctx->ifc_admin_task); 5411 CTX_LOCK(ctx); 5412 iflib_tqg_detach(ctx); 5413 iflib_tx_structures_free(ctx); 5414 iflib_rx_structures_free(ctx); 5415 /* 5416 * Match iflib_device_deregister: IFDI_DETACH before taskqueue_free. 5417 * Avoid IFNET_WLOCK across driver detach (LinuxKPI workqueue drain). 5418 */ 5419 IFNET_WUNLOCK(); 5420 IFDI_DETACH(ctx); 5421 IFDI_QUEUES_FREE(ctx); 5422 IFNET_WLOCK(); 5423 taskqueue_free(ctx->ifc_tq); 5424 fail_intr_free: 5425 iflib_free_intr_mem(ctx); 5426 fail_unlock: 5427 CTX_UNLOCK(ctx); 5428 IFNET_WUNLOCK(); 5429 iflib_deregister(ctx); 5430 device_set_softc(ctx->ifc_dev, NULL); 5431 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5432 free(ctx->ifc_softc, M_IFLIB); 5433 free(ctx, M_IFLIB); 5434 return (err); 5435 } 5436 5437 int 5438 iflib_device_attach(device_t dev) 5439 { 5440 if_ctx_t ctx; 5441 if_shared_ctx_t sctx; 5442 5443 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5444 return (ENOTSUP); 5445 5446 pci_enable_busmaster(dev); 5447 5448 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5449 } 5450 5451 int 5452 iflib_device_deregister(if_ctx_t ctx) 5453 { 5454 if_t ifp = ctx->ifc_ifp; 5455 device_t dev = ctx->ifc_dev; 5456 5457 sysctl_ctx_free(&ctx->ifc_sysctl_ctx); 5458 ctx->ifc_sysctl_node = NULL; 5459 5460 /* Make sure VLANS are not using driver */ 5461 if (if_vlantrunkinuse(ifp)) { 5462 device_printf(dev, "Vlan in use, detach first\n"); 5463 return (EBUSY); 5464 } 5465 #ifdef PCI_IOV 5466 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5467 device_printf(dev, "SR-IOV in use; detach first.\n"); 5468 return (EBUSY); 5469 } 5470 #endif 5471 5472 STATE_LOCK(ctx); 5473 ctx->ifc_flags |= IFC_IN_DETACH; 5474 STATE_UNLOCK(ctx); 5475 5476 /* Unregister VLAN handlers before calling iflib_stop() */ 5477 iflib_unregister_vlan_handlers(ctx); 5478 5479 iflib_netmap_detach(ifp); 5480 ether_ifdetach(ifp); 5481 5482 CTX_LOCK(ctx); 5483 iflib_stop(ctx); 5484 CTX_UNLOCK(ctx); 5485 5486 iflib_rem_pfil(ctx); 5487 if (ctx->ifc_led_dev != NULL) 5488 led_destroy(ctx->ifc_led_dev); 5489 5490 iflib_tqg_detach(ctx); 5491 iflib_tx_structures_free(ctx); 5492 iflib_rx_structures_free(ctx); 5493 5494 CTX_LOCK(ctx); 5495 IFDI_DETACH(ctx); 5496 IFDI_QUEUES_FREE(ctx); 5497 CTX_UNLOCK(ctx); 5498 5499 taskqueue_free(ctx->ifc_tq); 5500 ctx->ifc_tq = NULL; 5501 5502 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5503 iflib_free_intr_mem(ctx); 5504 5505 bus_generic_detach(dev); 5506 5507 iflib_deregister(ctx); 5508 5509 device_set_softc(ctx->ifc_dev, NULL); 5510 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5511 free(ctx->ifc_softc, M_IFLIB); 5512 unref_ctx_core_offset(ctx); 5513 free(ctx, M_IFLIB); 5514 return (0); 5515 } 5516 5517 static void 5518 iflib_tqg_detach(if_ctx_t ctx) 5519 { 5520 iflib_txq_t txq; 5521 iflib_rxq_t rxq; 5522 int i; 5523 struct taskqgroup *tqg; 5524 5525 /* XXX drain any dependent tasks */ 5526 tqg = qgroup_if_io_tqg; 5527 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5528 callout_drain(&txq->ift_timer); 5529 #ifdef DEV_NETMAP 5530 callout_drain(&txq->ift_netmap_timer); 5531 #endif /* DEV_NETMAP */ 5532 if (txq->ift_task.gt_uniq != NULL) 5533 taskqgroup_detach(tqg, &txq->ift_task); 5534 } 5535 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5536 if (rxq->ifr_task.gt_uniq != NULL) 5537 taskqgroup_detach(tqg, &rxq->ifr_task); 5538 } 5539 } 5540 5541 static void 5542 iflib_free_intr_mem(if_ctx_t ctx) 5543 { 5544 5545 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5546 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5547 } 5548 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5549 pci_release_msi(ctx->ifc_dev); 5550 } 5551 if (ctx->ifc_msix_mem != NULL) { 5552 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5553 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5554 ctx->ifc_msix_mem = NULL; 5555 } 5556 } 5557 5558 int 5559 iflib_device_detach(device_t dev) 5560 { 5561 if_ctx_t ctx = device_get_softc(dev); 5562 5563 return (iflib_device_deregister(ctx)); 5564 } 5565 5566 int 5567 iflib_device_suspend(device_t dev) 5568 { 5569 if_ctx_t ctx = device_get_softc(dev); 5570 5571 CTX_LOCK(ctx); 5572 IFDI_SUSPEND(ctx); 5573 CTX_UNLOCK(ctx); 5574 5575 return (bus_generic_suspend(dev)); 5576 } 5577 int 5578 iflib_device_shutdown(device_t dev) 5579 { 5580 if_ctx_t ctx = device_get_softc(dev); 5581 5582 CTX_LOCK(ctx); 5583 IFDI_SHUTDOWN(ctx); 5584 CTX_UNLOCK(ctx); 5585 5586 return (bus_generic_suspend(dev)); 5587 } 5588 5589 int 5590 iflib_device_resume(device_t dev) 5591 { 5592 if_ctx_t ctx = device_get_softc(dev); 5593 iflib_txq_t txq = ctx->ifc_txqs; 5594 5595 CTX_LOCK(ctx); 5596 IFDI_RESUME(ctx); 5597 iflib_if_init_locked(ctx); 5598 CTX_UNLOCK(ctx); 5599 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5600 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5601 5602 return (bus_generic_resume(dev)); 5603 } 5604 5605 int 5606 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5607 { 5608 int error; 5609 if_ctx_t ctx = device_get_softc(dev); 5610 5611 CTX_LOCK(ctx); 5612 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5613 CTX_UNLOCK(ctx); 5614 5615 return (error); 5616 } 5617 5618 int 5619 iflib_device_iov_init_restart(device_t dev, uint16_t num_vfs, 5620 const nvlist_t *params) 5621 { 5622 if_ctx_t ctx; 5623 if_t ifp; 5624 bool restart, running; 5625 int error; 5626 5627 ctx = device_get_softc(dev); 5628 ifp = ctx->ifc_ifp; 5629 5630 CTX_LOCK(ctx); 5631 /* 5632 * Drivers which change the PF queue layout need the complete iflib 5633 * stop/init sequence around their IOV callback when the interface is 5634 * active. An administratively-down interface has no live queues to 5635 * quiesce, and must remain down after the new layout is installed. 5636 * Keep the transition within one context-lock critical section. 5637 */ 5638 restart = (if_getflags(ifp) & IFF_UP) != 0; 5639 running = (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0; 5640 if (restart || running) 5641 iflib_stop(ctx); 5642 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5643 if (restart) 5644 iflib_init_locked(ctx); 5645 CTX_UNLOCK(ctx); 5646 return (error); 5647 } 5648 5649 void 5650 iflib_device_iov_uninit(device_t dev) 5651 { 5652 if_ctx_t ctx = device_get_softc(dev); 5653 5654 CTX_LOCK(ctx); 5655 IFDI_IOV_UNINIT(ctx); 5656 CTX_UNLOCK(ctx); 5657 } 5658 5659 void 5660 iflib_device_iov_uninit_restart(device_t dev) 5661 { 5662 if_ctx_t ctx; 5663 bool restart; 5664 5665 ctx = device_get_softc(dev); 5666 5667 CTX_LOCK(ctx); 5668 /* 5669 * RUNNING can be clear while a watchdog reset is pending but the 5670 * hardware is still live. Always stop before the driver changes its 5671 * queue layout, and use IFF_UP only to preserve administrative state. 5672 */ 5673 restart = (if_getflags(ctx->ifc_ifp) & IFF_UP) != 0; 5674 iflib_stop(ctx); 5675 IFDI_IOV_UNINIT(ctx); 5676 if (restart) 5677 iflib_init_locked(ctx); 5678 CTX_UNLOCK(ctx); 5679 } 5680 5681 int 5682 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5683 { 5684 int error; 5685 if_ctx_t ctx = device_get_softc(dev); 5686 5687 CTX_LOCK(ctx); 5688 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5689 CTX_UNLOCK(ctx); 5690 5691 return (error); 5692 } 5693 5694 /********************************************************************* 5695 * 5696 * MODULE FUNCTION DEFINITIONS 5697 * 5698 **********************************************************************/ 5699 5700 /* 5701 * - Start a fast taskqueue thread for each core 5702 * - Start a taskqueue for control operations 5703 */ 5704 static int 5705 iflib_module_init(void) 5706 { 5707 iflib_timer_default = hz / 2; 5708 return (0); 5709 } 5710 5711 static int 5712 iflib_module_event_handler(module_t mod, int what, void *arg) 5713 { 5714 int err; 5715 5716 switch (what) { 5717 case MOD_LOAD: 5718 if ((err = iflib_module_init()) != 0) 5719 return (err); 5720 break; 5721 case MOD_UNLOAD: 5722 return (EBUSY); 5723 default: 5724 return (EOPNOTSUPP); 5725 } 5726 5727 return (0); 5728 } 5729 5730 /********************************************************************* 5731 * 5732 * PUBLIC FUNCTION DEFINITIONS 5733 * ordered as in iflib.h 5734 * 5735 **********************************************************************/ 5736 5737 static void 5738 _iflib_assert(if_shared_ctx_t sctx) 5739 { 5740 int i; 5741 5742 MPASS(sctx->isc_tx_maxsize); 5743 MPASS(sctx->isc_tx_maxsegsize); 5744 5745 MPASS(sctx->isc_rx_maxsize); 5746 MPASS(sctx->isc_rx_nsegments); 5747 MPASS(sctx->isc_rx_maxsegsize); 5748 5749 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5750 for (i = 0; i < sctx->isc_nrxqs; i++) { 5751 MPASS(sctx->isc_nrxd_min[i]); 5752 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5753 MPASS(sctx->isc_nrxd_max[i]); 5754 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5755 MPASS(sctx->isc_nrxd_default[i]); 5756 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5757 } 5758 5759 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5760 for (i = 0; i < sctx->isc_ntxqs; i++) { 5761 MPASS(sctx->isc_ntxd_min[i]); 5762 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5763 MPASS(sctx->isc_ntxd_max[i]); 5764 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5765 MPASS(sctx->isc_ntxd_default[i]); 5766 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5767 } 5768 } 5769 5770 static void 5771 _iflib_pre_assert(if_softc_ctx_t scctx) 5772 { 5773 5774 MPASS(scctx->isc_txrx->ift_txd_encap); 5775 MPASS(scctx->isc_txrx->ift_txd_flush); 5776 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5777 MPASS(scctx->isc_txrx->ift_rxd_available); 5778 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5779 MPASS(scctx->isc_txrx->ift_rxd_refill); 5780 MPASS(scctx->isc_txrx->ift_rxd_flush); 5781 } 5782 5783 static void 5784 iflib_register(if_ctx_t ctx) 5785 { 5786 if_shared_ctx_t sctx = ctx->ifc_sctx; 5787 driver_t *driver = sctx->isc_driver; 5788 device_t dev = ctx->ifc_dev; 5789 if_t ifp; 5790 5791 _iflib_assert(sctx); 5792 5793 CTX_LOCK_INIT(ctx); 5794 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5795 ifp = ctx->ifc_ifp = if_alloc_dev(IFT_ETHER, dev); 5796 5797 /* 5798 * Initialize our context's device specific methods 5799 */ 5800 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5801 kobj_class_compile((kobj_class_t) driver); 5802 5803 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5804 if_setsoftc(ifp, ctx); 5805 if_setdev(ifp, dev); 5806 if_setinitfn(ifp, iflib_if_init); 5807 if_setioctlfn(ifp, iflib_if_ioctl); 5808 #ifdef ALTQ 5809 if_setstartfn(ifp, iflib_altq_if_start); 5810 if_settransmitfn(ifp, iflib_altq_if_transmit); 5811 if_setsendqready(ifp); 5812 #else 5813 if_settransmitfn(ifp, iflib_if_transmit); 5814 #endif 5815 if_setqflushfn(ifp, iflib_if_qflush); 5816 if_setgetcounterfn(ifp, iflib_if_get_counter); 5817 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5818 ctx->ifc_vlan_attach_event = 5819 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5820 EVENTHANDLER_PRI_FIRST); 5821 ctx->ifc_vlan_detach_event = 5822 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5823 EVENTHANDLER_PRI_FIRST); 5824 5825 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5826 ctx->ifc_mediap = &ctx->ifc_media; 5827 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5828 iflib_media_change, iflib_media_status); 5829 } 5830 } 5831 5832 static void 5833 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5834 { 5835 /* Unregister VLAN events */ 5836 if (ctx->ifc_vlan_attach_event != NULL) { 5837 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5838 ctx->ifc_vlan_attach_event = NULL; 5839 } 5840 if (ctx->ifc_vlan_detach_event != NULL) { 5841 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5842 ctx->ifc_vlan_detach_event = NULL; 5843 } 5844 5845 } 5846 5847 static void 5848 iflib_deregister(if_ctx_t ctx) 5849 { 5850 if_t ifp = ctx->ifc_ifp; 5851 5852 /* Remove all media */ 5853 ifmedia_removeall(&ctx->ifc_media); 5854 5855 /* Ensure that VLAN event handlers are unregistered */ 5856 iflib_unregister_vlan_handlers(ctx); 5857 5858 /* Release kobject reference */ 5859 kobj_delete((kobj_t) ctx, NULL); 5860 5861 /* Free the ifnet structure */ 5862 if_free(ifp); 5863 5864 STATE_LOCK_DESTROY(ctx); 5865 5866 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5867 CTX_LOCK_DESTROY(ctx); 5868 } 5869 5870 static int 5871 iflib_queues_alloc(if_ctx_t ctx) 5872 { 5873 if_shared_ctx_t sctx = ctx->ifc_sctx; 5874 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5875 device_t dev = ctx->ifc_dev; 5876 int nrxqsets = scctx->isc_nrxqsets; 5877 int ntxqsets = scctx->isc_ntxqsets; 5878 iflib_txq_t txq; 5879 iflib_rxq_t rxq; 5880 iflib_fl_t fl = NULL; 5881 int i, j, cpu, err, txconf, rxconf; 5882 iflib_dma_info_t ifdip; 5883 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5884 uint32_t *txqsizes = scctx->isc_txqsizes; 5885 uint8_t nrxqs = sctx->isc_nrxqs; 5886 uint8_t ntxqs = sctx->isc_ntxqs; 5887 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5888 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0); 5889 caddr_t *vaddrs; 5890 uint64_t *paddrs; 5891 5892 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5893 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5894 KASSERT(nrxqs >= fl_offset + nfree_lists, 5895 ("there must be at least a rxq for each free list")); 5896 5897 /* Allocate the TX ring struct memory */ 5898 if (!(ctx->ifc_txqs = 5899 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5900 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5901 device_printf(dev, "Unable to allocate TX ring memory\n"); 5902 err = ENOMEM; 5903 goto fail; 5904 } 5905 5906 /* Now allocate the RX */ 5907 if (!(ctx->ifc_rxqs = 5908 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5909 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5910 device_printf(dev, "Unable to allocate RX ring memory\n"); 5911 err = ENOMEM; 5912 goto rx_fail; 5913 } 5914 5915 txq = ctx->ifc_txqs; 5916 rxq = ctx->ifc_rxqs; 5917 5918 /* 5919 * XXX handle allocation failure 5920 */ 5921 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5922 /* Set up some basics */ 5923 5924 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5925 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5926 device_printf(dev, 5927 "Unable to allocate TX DMA info memory\n"); 5928 err = ENOMEM; 5929 goto err_tx_desc; 5930 } 5931 txq->ift_ifdi = ifdip; 5932 for (j = 0; j < ntxqs; j++, ifdip++) { 5933 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5934 device_printf(dev, 5935 "Unable to allocate TX descriptors\n"); 5936 err = ENOMEM; 5937 goto err_tx_desc; 5938 } 5939 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5940 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5941 } 5942 txq->ift_ctx = ctx; 5943 txq->ift_id = i; 5944 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5945 txq->ift_br_offset = 1; 5946 } else { 5947 txq->ift_br_offset = 0; 5948 } 5949 5950 if (iflib_txsd_alloc(txq)) { 5951 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5952 err = ENOMEM; 5953 goto err_tx_desc; 5954 } 5955 5956 /* Initialize the TX lock */ 5957 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5958 device_get_nameunit(dev), txq->ift_id); 5959 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5960 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5961 txq->ift_timer.c_cpu = cpu; 5962 #ifdef DEV_NETMAP 5963 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 5964 txq->ift_netmap_timer.c_cpu = cpu; 5965 #endif /* DEV_NETMAP */ 5966 5967 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5968 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5969 if (err) { 5970 /* XXX free any allocated rings */ 5971 device_printf(dev, "Unable to allocate buf_ring\n"); 5972 goto err_tx_desc; 5973 } 5974 txq->ift_reclaim_thresh = ctx->ifc_sysctl_tx_reclaim_thresh; 5975 } 5976 5977 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5978 /* Set up some basics */ 5979 callout_init(&rxq->ifr_watchdog, 1); 5980 5981 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5982 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5983 device_printf(dev, 5984 "Unable to allocate RX DMA info memory\n"); 5985 err = ENOMEM; 5986 goto err_tx_desc; 5987 } 5988 5989 rxq->ifr_ifdi = ifdip; 5990 /* XXX this needs to be changed if #rx queues != #tx queues */ 5991 rxq->ifr_ntxqirq = 1; 5992 rxq->ifr_txqid[0] = i; 5993 for (j = 0; j < nrxqs; j++, ifdip++) { 5994 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5995 device_printf(dev, 5996 "Unable to allocate RX descriptors\n"); 5997 err = ENOMEM; 5998 goto err_tx_desc; 5999 } 6000 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 6001 } 6002 rxq->ifr_ctx = ctx; 6003 rxq->ifr_id = i; 6004 rxq->ifr_fl_offset = fl_offset; 6005 rxq->ifr_nfl = nfree_lists; 6006 if (!(fl = 6007 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 6008 device_printf(dev, "Unable to allocate free list memory\n"); 6009 err = ENOMEM; 6010 goto err_tx_desc; 6011 } 6012 rxq->ifr_fl = fl; 6013 for (j = 0; j < nfree_lists; j++) { 6014 fl[j].ifl_rxq = rxq; 6015 fl[j].ifl_id = j; 6016 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 6017 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 6018 } 6019 /* Allocate receive buffers for the ring */ 6020 if (iflib_rxsd_alloc(rxq)) { 6021 device_printf(dev, 6022 "Critical Failure setting up receive buffers\n"); 6023 err = ENOMEM; 6024 goto err_rx_desc; 6025 } 6026 6027 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 6028 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 6029 M_WAITOK); 6030 } 6031 6032 /* TXQs */ 6033 vaddrs = malloc(sizeof(caddr_t) * ntxqsets * ntxqs, M_IFLIB, M_WAITOK); 6034 paddrs = malloc(sizeof(uint64_t) * ntxqsets * ntxqs, M_IFLIB, M_WAITOK); 6035 for (i = 0; i < ntxqsets; i++) { 6036 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 6037 6038 for (j = 0; j < ntxqs; j++, di++) { 6039 vaddrs[i * ntxqs + j] = di->idi_vaddr; 6040 paddrs[i * ntxqs + j] = di->idi_paddr; 6041 } 6042 } 6043 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 6044 device_printf(ctx->ifc_dev, 6045 "Unable to allocate device TX queue\n"); 6046 iflib_tx_structures_free(ctx); 6047 free(vaddrs, M_IFLIB); 6048 free(paddrs, M_IFLIB); 6049 goto err_rx_desc; 6050 } 6051 free(vaddrs, M_IFLIB); 6052 free(paddrs, M_IFLIB); 6053 6054 /* RXQs */ 6055 vaddrs = malloc(sizeof(caddr_t) * nrxqsets * nrxqs, M_IFLIB, M_WAITOK); 6056 paddrs = malloc(sizeof(uint64_t) * nrxqsets * nrxqs, M_IFLIB, M_WAITOK); 6057 for (i = 0; i < nrxqsets; i++) { 6058 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 6059 6060 for (j = 0; j < nrxqs; j++, di++) { 6061 vaddrs[i * nrxqs + j] = di->idi_vaddr; 6062 paddrs[i * nrxqs + j] = di->idi_paddr; 6063 } 6064 } 6065 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 6066 device_printf(ctx->ifc_dev, 6067 "Unable to allocate device RX queue\n"); 6068 iflib_tx_structures_free(ctx); 6069 free(vaddrs, M_IFLIB); 6070 free(paddrs, M_IFLIB); 6071 goto err_rx_desc; 6072 } 6073 free(vaddrs, M_IFLIB); 6074 free(paddrs, M_IFLIB); 6075 6076 return (0); 6077 6078 /* XXX handle allocation failure changes */ 6079 err_rx_desc: 6080 err_tx_desc: 6081 rx_fail: 6082 if (ctx->ifc_rxqs != NULL) 6083 free(ctx->ifc_rxqs, M_IFLIB); 6084 ctx->ifc_rxqs = NULL; 6085 if (ctx->ifc_txqs != NULL) 6086 free(ctx->ifc_txqs, M_IFLIB); 6087 ctx->ifc_txqs = NULL; 6088 fail: 6089 return (err); 6090 } 6091 6092 static int 6093 iflib_tx_structures_setup(if_ctx_t ctx) 6094 { 6095 iflib_txq_t txq = ctx->ifc_txqs; 6096 int i; 6097 6098 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 6099 iflib_txq_setup(txq); 6100 6101 return (0); 6102 } 6103 6104 static void 6105 iflib_tx_structures_free(if_ctx_t ctx) 6106 { 6107 iflib_txq_t txq = ctx->ifc_txqs; 6108 if_shared_ctx_t sctx = ctx->ifc_sctx; 6109 int i, j; 6110 6111 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6112 for (j = 0; j < sctx->isc_ntxqs; j++) 6113 iflib_dma_free(&txq->ift_ifdi[j]); 6114 iflib_txq_destroy(txq); 6115 } 6116 free(ctx->ifc_txqs, M_IFLIB); 6117 ctx->ifc_txqs = NULL; 6118 } 6119 6120 /********************************************************************* 6121 * 6122 * Initialize all receive rings. 6123 * 6124 **********************************************************************/ 6125 static int 6126 iflib_rx_structures_setup(if_ctx_t ctx) 6127 { 6128 iflib_rxq_t rxq = ctx->ifc_rxqs; 6129 int q; 6130 #if defined(INET6) || defined(INET) 6131 int err, i; 6132 #endif 6133 6134 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 6135 #if defined(INET6) || defined(INET) 6136 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 6137 TCP_LRO_ENTRIES, min(1024, 6138 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 6139 if (err != 0) { 6140 device_printf(ctx->ifc_dev, 6141 "LRO Initialization failed!\n"); 6142 goto fail; 6143 } 6144 #endif 6145 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 6146 } 6147 return (0); 6148 #if defined(INET6) || defined(INET) 6149 fail: 6150 /* 6151 * Free LRO resources allocated so far, we will only handle 6152 * the rings that completed, the failing case will have 6153 * cleaned up for itself. 'q' failed, so its the terminus. 6154 */ 6155 rxq = ctx->ifc_rxqs; 6156 for (i = 0; i < q; ++i, rxq++) { 6157 tcp_lro_free(&rxq->ifr_lc); 6158 } 6159 return (err); 6160 #endif 6161 } 6162 6163 /********************************************************************* 6164 * 6165 * Free all receive rings. 6166 * 6167 **********************************************************************/ 6168 static void 6169 iflib_rx_structures_free(if_ctx_t ctx) 6170 { 6171 iflib_rxq_t rxq = ctx->ifc_rxqs; 6172 if_shared_ctx_t sctx = ctx->ifc_sctx; 6173 int i, j; 6174 6175 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 6176 for (j = 0; j < sctx->isc_nrxqs; j++) 6177 iflib_dma_free(&rxq->ifr_ifdi[j]); 6178 iflib_rx_sds_free(rxq); 6179 #if defined(INET6) || defined(INET) 6180 tcp_lro_free(&rxq->ifr_lc); 6181 #endif 6182 } 6183 free(ctx->ifc_rxqs, M_IFLIB); 6184 ctx->ifc_rxqs = NULL; 6185 } 6186 6187 static int 6188 iflib_qset_structures_setup(if_ctx_t ctx) 6189 { 6190 int err; 6191 6192 /* 6193 * It is expected that the caller takes care of freeing queues if this 6194 * fails. 6195 */ 6196 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 6197 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 6198 return (err); 6199 } 6200 6201 if ((err = iflib_rx_structures_setup(ctx)) != 0) 6202 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 6203 6204 return (err); 6205 } 6206 6207 int 6208 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 6209 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 6210 { 6211 6212 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 6213 } 6214 6215 /* Just to avoid copy/paste */ 6216 static inline int 6217 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6218 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 6219 const char *name) 6220 { 6221 device_t dev; 6222 unsigned int base_cpuid, cpuid; 6223 int err; 6224 6225 dev = ctx->ifc_dev; 6226 base_cpuid = ctx->ifc_sysctl_core_offset; 6227 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX); 6228 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, 6229 irq ? irq->ii_res : NULL, name); 6230 if (err) { 6231 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6232 return (err); 6233 } 6234 #ifdef notyet 6235 if (cpuid > ctx->ifc_cpuid_highest) 6236 ctx->ifc_cpuid_highest = cpuid; 6237 #endif 6238 return (0); 6239 } 6240 6241 /* 6242 * Allocate a hardware interrupt for subctx using the parent (ctx)'s hardware 6243 * resources. 6244 * 6245 * Similar to iflib_irq_alloc_generic(), but for interrupt type IFLIB_INTR_RXTX 6246 * only. 6247 * 6248 * XXX: Could be removed if subctx's dev has its intr resource allocation 6249 * methods replaced with custom ones? 6250 */ 6251 int 6252 iflib_irq_alloc_generic_subctx(if_ctx_t ctx, if_ctx_t subctx, if_irq_t irq, 6253 int rid, iflib_intr_type_t type, 6254 driver_filter_t *filter, void *filter_arg, 6255 int qid, const char *name) 6256 { 6257 device_t dev, subdev; 6258 struct grouptask *gtask; 6259 struct taskqgroup *tqg; 6260 iflib_filter_info_t info; 6261 gtask_fn_t *fn; 6262 int tqrid, err; 6263 driver_filter_t *intr_fast; 6264 void *q; 6265 6266 MPASS(ctx != NULL); 6267 MPASS(subctx != NULL); 6268 6269 tqrid = rid; 6270 dev = ctx->ifc_dev; 6271 subdev = subctx->ifc_dev; 6272 6273 switch (type) { 6274 case IFLIB_INTR_RXTX: 6275 q = &subctx->ifc_rxqs[qid]; 6276 info = &subctx->ifc_rxqs[qid].ifr_filter_info; 6277 gtask = &subctx->ifc_rxqs[qid].ifr_task; 6278 tqg = qgroup_if_io_tqg; 6279 fn = _task_fn_rx; 6280 intr_fast = iflib_fast_intr_rxtx; 6281 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6282 break; 6283 default: 6284 device_printf(dev, "%s: unknown net intr type for subctx %s (%d)\n", 6285 __func__, device_get_nameunit(subdev), type); 6286 return (EINVAL); 6287 } 6288 6289 info->ifi_filter = filter; 6290 info->ifi_filter_arg = filter_arg; 6291 info->ifi_task = gtask; 6292 info->ifi_ctx = q; 6293 6294 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6295 6296 /* Allocate interrupts from hardware using parent context */ 6297 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6298 if (err != 0) { 6299 device_printf(dev, "_iflib_irq_alloc failed for subctx %s: %d\n", 6300 device_get_nameunit(subdev), err); 6301 return (err); 6302 } 6303 6304 if (tqrid != -1) { 6305 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6306 name); 6307 if (err) 6308 return (err); 6309 } else { 6310 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6311 } 6312 6313 return (0); 6314 } 6315 6316 int 6317 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6318 iflib_intr_type_t type, driver_filter_t *filter, 6319 void *filter_arg, int qid, const char *name) 6320 { 6321 device_t dev; 6322 struct grouptask *gtask; 6323 struct taskqgroup *tqg; 6324 iflib_filter_info_t info; 6325 gtask_fn_t *fn; 6326 int tqrid, err; 6327 driver_filter_t *intr_fast; 6328 void *q; 6329 6330 info = &ctx->ifc_filter_info; 6331 tqrid = rid; 6332 6333 switch (type) { 6334 /* XXX merge tx/rx for netmap? */ 6335 case IFLIB_INTR_TX: 6336 q = &ctx->ifc_txqs[qid]; 6337 info = &ctx->ifc_txqs[qid].ift_filter_info; 6338 gtask = &ctx->ifc_txqs[qid].ift_task; 6339 tqg = qgroup_if_io_tqg; 6340 fn = _task_fn_tx; 6341 intr_fast = iflib_fast_intr; 6342 GROUPTASK_INIT(gtask, 0, fn, q); 6343 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6344 break; 6345 case IFLIB_INTR_RX: 6346 q = &ctx->ifc_rxqs[qid]; 6347 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6348 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6349 tqg = qgroup_if_io_tqg; 6350 fn = _task_fn_rx; 6351 intr_fast = iflib_fast_intr; 6352 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6353 break; 6354 case IFLIB_INTR_RXTX: 6355 q = &ctx->ifc_rxqs[qid]; 6356 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6357 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6358 tqg = qgroup_if_io_tqg; 6359 fn = _task_fn_rx; 6360 intr_fast = iflib_fast_intr_rxtx; 6361 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6362 break; 6363 case IFLIB_INTR_ADMIN: 6364 q = ctx; 6365 tqrid = -1; 6366 info = &ctx->ifc_filter_info; 6367 gtask = NULL; 6368 intr_fast = iflib_fast_intr_ctx; 6369 break; 6370 default: 6371 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6372 __func__); 6373 return (EINVAL); 6374 } 6375 6376 info->ifi_filter = filter; 6377 info->ifi_filter_arg = filter_arg; 6378 info->ifi_task = gtask; 6379 info->ifi_ctx = q; 6380 6381 dev = ctx->ifc_dev; 6382 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6383 if (err != 0) { 6384 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6385 return (err); 6386 } 6387 if (type == IFLIB_INTR_ADMIN) 6388 return (0); 6389 6390 if (tqrid != -1) { 6391 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6392 name); 6393 if (err) 6394 return (err); 6395 } else { 6396 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6397 } 6398 6399 return (0); 6400 } 6401 6402 void 6403 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6404 void *arg, int qid, const char *name) 6405 { 6406 device_t dev; 6407 struct grouptask *gtask; 6408 struct taskqgroup *tqg; 6409 gtask_fn_t *fn; 6410 void *q; 6411 int err; 6412 6413 switch (type) { 6414 case IFLIB_INTR_TX: 6415 q = &ctx->ifc_txqs[qid]; 6416 gtask = &ctx->ifc_txqs[qid].ift_task; 6417 tqg = qgroup_if_io_tqg; 6418 fn = _task_fn_tx; 6419 GROUPTASK_INIT(gtask, 0, fn, q); 6420 break; 6421 case IFLIB_INTR_RX: 6422 q = &ctx->ifc_rxqs[qid]; 6423 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6424 tqg = qgroup_if_io_tqg; 6425 fn = _task_fn_rx; 6426 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6427 break; 6428 case IFLIB_INTR_IOV: 6429 TASK_INIT(&ctx->ifc_vflr_task, 0, _task_fn_iov, ctx); 6430 return; 6431 default: 6432 panic("unknown net intr type"); 6433 } 6434 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name); 6435 if (err) { 6436 dev = ctx->ifc_dev; 6437 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL, 6438 name); 6439 } 6440 } 6441 6442 void 6443 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6444 { 6445 6446 if (irq->ii_tag) 6447 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6448 6449 if (irq->ii_res) 6450 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6451 rman_get_rid(irq->ii_res), irq->ii_res); 6452 } 6453 6454 static int 6455 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6456 { 6457 iflib_txq_t txq = ctx->ifc_txqs; 6458 iflib_rxq_t rxq = ctx->ifc_rxqs; 6459 if_irq_t irq = &ctx->ifc_legacy_irq; 6460 iflib_filter_info_t info; 6461 device_t dev; 6462 struct grouptask *gtask; 6463 struct resource *res; 6464 int err, tqrid; 6465 bool rx_only; 6466 6467 info = &rxq->ifr_filter_info; 6468 gtask = &rxq->ifr_task; 6469 tqrid = *rid; 6470 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6471 6472 ctx->ifc_flags |= IFC_LEGACY; 6473 info->ifi_filter = filter; 6474 info->ifi_filter_arg = filter_arg; 6475 info->ifi_task = gtask; 6476 info->ifi_ctx = rxq; 6477 6478 dev = ctx->ifc_dev; 6479 /* We allocate a single interrupt resource */ 6480 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr : 6481 iflib_fast_intr_rxtx, NULL, info, name); 6482 if (err != 0) 6483 return (err); 6484 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, rxq); 6485 res = irq->ii_res; 6486 taskqgroup_attach(qgroup_if_io_tqg, gtask, rxq, dev, res, name); 6487 6488 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6489 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6490 "tx"); 6491 return (0); 6492 } 6493 6494 void 6495 iflib_led_create(if_ctx_t ctx) 6496 { 6497 6498 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6499 device_get_nameunit(ctx->ifc_dev)); 6500 } 6501 6502 void 6503 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6504 { 6505 6506 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6507 } 6508 6509 void 6510 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6511 { 6512 6513 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6514 } 6515 6516 void 6517 iflib_admin_intr_deferred(if_ctx_t ctx) 6518 { 6519 6520 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_admin_task); 6521 } 6522 6523 void 6524 iflib_iov_intr_deferred(if_ctx_t ctx) 6525 { 6526 6527 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_vflr_task); 6528 } 6529 6530 void 6531 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6532 { 6533 6534 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6535 name); 6536 } 6537 6538 void 6539 iflib_config_task_init(if_ctx_t ctx, struct task *config_task, task_fn_t *fn) 6540 { 6541 TASK_INIT(config_task, 0, fn, ctx); 6542 } 6543 6544 void 6545 iflib_config_task_enqueue(if_ctx_t ctx, struct task *config_task) 6546 { 6547 taskqueue_enqueue(ctx->ifc_tq, config_task); 6548 } 6549 6550 void 6551 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6552 { 6553 if_t ifp = ctx->ifc_ifp; 6554 6555 if_setbaudrate(ifp, baudrate); 6556 if (baudrate >= IF_Gbps(10)) { 6557 STATE_LOCK(ctx); 6558 ctx->ifc_flags |= IFC_PREFETCH; 6559 STATE_UNLOCK(ctx); 6560 } 6561 ctx->ifc_link_state = link_state; 6562 if_link_state_change(ifp, link_state); 6563 } 6564 6565 static int 6566 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6567 { 6568 int credits; 6569 #ifdef INVARIANTS 6570 int credits_pre = txq->ift_cidx_processed; 6571 #endif 6572 6573 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6574 BUS_DMASYNC_POSTREAD); 6575 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6576 return (0); 6577 6578 txq->ift_processed += credits; 6579 txq->ift_cidx_processed += credits; 6580 6581 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6582 if (txq->ift_cidx_processed >= txq->ift_size) 6583 txq->ift_cidx_processed -= txq->ift_size; 6584 return (credits); 6585 } 6586 6587 static int 6588 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6589 { 6590 iflib_fl_t fl; 6591 u_int i; 6592 6593 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6594 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6595 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6596 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6597 budget)); 6598 } 6599 6600 void 6601 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6602 const char *description, if_int_delay_info_t info, 6603 int offset, int value) 6604 { 6605 info->iidi_ctx = ctx; 6606 info->iidi_offset = offset; 6607 info->iidi_value = value; 6608 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6609 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6610 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6611 info, 0, iflib_sysctl_int_delay, "I", description); 6612 } 6613 6614 struct sx * 6615 iflib_ctx_lock_get(if_ctx_t ctx) 6616 { 6617 6618 return (&ctx->ifc_ctx_sx); 6619 } 6620 6621 static int 6622 iflib_msix_init(if_ctx_t ctx) 6623 { 6624 device_t dev = ctx->ifc_dev; 6625 if_shared_ctx_t sctx = ctx->ifc_sctx; 6626 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6627 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6628 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6629 6630 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6631 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6632 6633 if (bootverbose) 6634 device_printf(dev, "msix_init qsets capped at %d\n", 6635 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6636 6637 /* Override by tuneable */ 6638 if (scctx->isc_disable_msix) 6639 goto msi; 6640 6641 /* First try MSI-X */ 6642 if ((msgs = pci_msix_count(dev)) == 0) { 6643 if (bootverbose) 6644 device_printf(dev, "MSI-X not supported or disabled\n"); 6645 goto msi; 6646 } 6647 6648 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6649 /* 6650 * bar == -1 => "trust me I know what I'm doing" 6651 * Some drivers are for hardware that is so shoddily 6652 * documented that no one knows which bars are which 6653 * so the developer has to map all bars. This hack 6654 * allows shoddy garbage to use MSI-X in this framework. 6655 */ 6656 if (bar != -1) { 6657 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6658 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6659 if (ctx->ifc_msix_mem == NULL) { 6660 device_printf(dev, "Unable to map MSI-X table\n"); 6661 goto msi; 6662 } 6663 } 6664 6665 admincnt = sctx->isc_admin_intrcnt; 6666 #if IFLIB_DEBUG 6667 /* use only 1 qset in debug mode */ 6668 queuemsgs = min(msgs - admincnt, 1); 6669 #else 6670 queuemsgs = msgs - admincnt; 6671 #endif 6672 #ifdef RSS 6673 queues = imin(queuemsgs, rss_getnumbuckets()); 6674 #else 6675 queues = queuemsgs; 6676 #endif 6677 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6678 if (bootverbose) 6679 device_printf(dev, 6680 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6681 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6682 #ifdef RSS 6683 /* If we're doing RSS, clamp at the number of RSS buckets */ 6684 if (queues > rss_getnumbuckets()) 6685 queues = rss_getnumbuckets(); 6686 #endif 6687 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6688 rx_queues = iflib_num_rx_queues; 6689 else 6690 rx_queues = queues; 6691 6692 if (rx_queues > scctx->isc_nrxqsets) 6693 rx_queues = scctx->isc_nrxqsets; 6694 6695 /* 6696 * We want this to be all logical CPUs by default 6697 */ 6698 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6699 tx_queues = iflib_num_tx_queues; 6700 else 6701 tx_queues = mp_ncpus; 6702 6703 if (tx_queues > scctx->isc_ntxqsets) 6704 tx_queues = scctx->isc_ntxqsets; 6705 6706 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6707 #ifdef INVARIANTS 6708 if (tx_queues != rx_queues) 6709 device_printf(dev, 6710 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6711 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6712 #endif 6713 tx_queues = min(rx_queues, tx_queues); 6714 rx_queues = min(rx_queues, tx_queues); 6715 } 6716 6717 vectors = rx_queues + admincnt; 6718 if (msgs < vectors) { 6719 device_printf(dev, 6720 "insufficient number of MSI-X vectors " 6721 "(supported %d, need %d)\n", msgs, vectors); 6722 goto msi; 6723 } 6724 6725 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6726 tx_queues); 6727 msgs = vectors; 6728 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6729 if (vectors != msgs) { 6730 device_printf(dev, 6731 "Unable to allocate sufficient MSI-X vectors " 6732 "(got %d, need %d)\n", vectors, msgs); 6733 pci_release_msi(dev); 6734 if (bar != -1) { 6735 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6736 ctx->ifc_msix_mem); 6737 ctx->ifc_msix_mem = NULL; 6738 } 6739 goto msi; 6740 } 6741 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6742 vectors); 6743 scctx->isc_vectors = vectors; 6744 scctx->isc_nrxqsets = rx_queues; 6745 scctx->isc_ntxqsets = tx_queues; 6746 scctx->isc_intr = IFLIB_INTR_MSIX; 6747 6748 return (vectors); 6749 } else { 6750 device_printf(dev, 6751 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6752 err); 6753 if (bar != -1) { 6754 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6755 ctx->ifc_msix_mem); 6756 ctx->ifc_msix_mem = NULL; 6757 } 6758 } 6759 6760 msi: 6761 vectors = pci_msi_count(dev); 6762 scctx->isc_nrxqsets = 1; 6763 scctx->isc_ntxqsets = 1; 6764 scctx->isc_vectors = vectors; 6765 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6766 device_printf(dev, "Using an MSI interrupt\n"); 6767 scctx->isc_intr = IFLIB_INTR_MSI; 6768 } else { 6769 scctx->isc_vectors = 1; 6770 device_printf(dev, "Using a Legacy interrupt\n"); 6771 scctx->isc_intr = IFLIB_INTR_LEGACY; 6772 } 6773 6774 return (vectors); 6775 } 6776 6777 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6778 6779 static int 6780 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6781 { 6782 int rc; 6783 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6784 struct sbuf *sb; 6785 const char *ring_state = "UNKNOWN"; 6786 6787 /* XXX needed ? */ 6788 rc = sysctl_wire_old_buffer(req, 0); 6789 MPASS(rc == 0); 6790 if (rc != 0) 6791 return (rc); 6792 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6793 MPASS(sb != NULL); 6794 if (sb == NULL) 6795 return (ENOMEM); 6796 if (state[3] <= 3) 6797 ring_state = ring_states[state[3]]; 6798 6799 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6800 state[0], state[1], state[2], ring_state); 6801 rc = sbuf_finish(sb); 6802 sbuf_delete(sb); 6803 return (rc); 6804 } 6805 6806 enum iflib_ndesc_handler { 6807 IFLIB_NTXD_HANDLER, 6808 IFLIB_NRXD_HANDLER, 6809 }; 6810 6811 static int 6812 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6813 { 6814 if_ctx_t ctx = (void *)arg1; 6815 enum iflib_ndesc_handler type = arg2; 6816 char buf[256] = {0}; 6817 qidx_t *ndesc; 6818 char *p, *next; 6819 int nqs, rc, i; 6820 6821 nqs = 8; 6822 switch (type) { 6823 case IFLIB_NTXD_HANDLER: 6824 ndesc = ctx->ifc_sysctl_ntxds; 6825 if (ctx->ifc_sctx) 6826 nqs = ctx->ifc_sctx->isc_ntxqs; 6827 break; 6828 case IFLIB_NRXD_HANDLER: 6829 ndesc = ctx->ifc_sysctl_nrxds; 6830 if (ctx->ifc_sctx) 6831 nqs = ctx->ifc_sctx->isc_nrxqs; 6832 break; 6833 default: 6834 printf("%s: unhandled type\n", __func__); 6835 return (EINVAL); 6836 } 6837 if (nqs == 0) 6838 nqs = 8; 6839 6840 for (i = 0; i < 8; i++) { 6841 if (i >= nqs) 6842 break; 6843 if (i) 6844 strcat(buf, ","); 6845 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6846 } 6847 6848 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6849 if (rc || req->newptr == NULL) 6850 return (rc); 6851 6852 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6853 i++, p = strsep(&next, " ,")) { 6854 ndesc[i] = strtoul(p, NULL, 10); 6855 } 6856 6857 return (rc); 6858 } 6859 6860 static int 6861 iflib_handle_tx_reclaim_thresh(SYSCTL_HANDLER_ARGS) 6862 { 6863 if_ctx_t ctx = (void *)arg1; 6864 iflib_txq_t txq; 6865 int i, err; 6866 int thresh; 6867 6868 thresh = ctx->ifc_sysctl_tx_reclaim_thresh; 6869 err = sysctl_handle_int(oidp, &thresh, arg2, req); 6870 if (err != 0) { 6871 return err; 6872 } 6873 6874 if (thresh == ctx->ifc_sysctl_tx_reclaim_thresh) 6875 return 0; 6876 6877 if (thresh > ctx->ifc_softc_ctx.isc_ntxd[0] / 2) { 6878 device_printf(ctx->ifc_dev, "TX Reclaim thresh must be <= %d\n", 6879 ctx->ifc_softc_ctx.isc_ntxd[0] / 2); 6880 return (EINVAL); 6881 } 6882 6883 ctx->ifc_sysctl_tx_reclaim_thresh = thresh; 6884 if (ctx->ifc_txqs == NULL) 6885 return (err); 6886 6887 txq = &ctx->ifc_txqs[0]; 6888 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6889 txq->ift_reclaim_thresh = thresh; 6890 } 6891 return (err); 6892 } 6893 6894 static int 6895 iflib_handle_tx_reclaim_ticks(SYSCTL_HANDLER_ARGS) 6896 { 6897 if_ctx_t ctx = (void *)arg1; 6898 iflib_txq_t txq; 6899 int i, err; 6900 int ticks; 6901 6902 ticks = ctx->ifc_sysctl_tx_reclaim_ticks; 6903 err = sysctl_handle_int(oidp, &ticks, arg2, req); 6904 if (err != 0) { 6905 return err; 6906 } 6907 6908 if (ticks == ctx->ifc_sysctl_tx_reclaim_ticks) 6909 return 0; 6910 6911 if (ticks > hz) { 6912 device_printf(ctx->ifc_dev, 6913 "TX Reclaim ticks must be <= hz (%d)\n", hz); 6914 return (EINVAL); 6915 } 6916 6917 ctx->ifc_sysctl_tx_reclaim_ticks = ticks; 6918 if (ctx->ifc_txqs == NULL) 6919 return (err); 6920 6921 txq = &ctx->ifc_txqs[0]; 6922 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6923 txq->ift_reclaim_ticks = ticks; 6924 } 6925 return (err); 6926 } 6927 6928 static int 6929 iflib_handle_tx_defer_mfree(SYSCTL_HANDLER_ARGS) 6930 { 6931 if_ctx_t ctx = (void *)arg1; 6932 iflib_txq_t txq; 6933 int i, err; 6934 int defer; 6935 6936 defer = ctx->ifc_sysctl_tx_defer_mfree; 6937 err = sysctl_handle_int(oidp, &defer, arg2, req); 6938 if (err != 0) { 6939 return err; 6940 } 6941 6942 if (defer == ctx->ifc_sysctl_tx_defer_mfree) 6943 return 0; 6944 6945 ctx->ifc_sysctl_tx_defer_mfree = defer; 6946 if (ctx->ifc_txqs == NULL) 6947 return (err); 6948 6949 txq = &ctx->ifc_txqs[0]; 6950 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6951 txq->ift_defer_mfree = defer; 6952 } 6953 return (err); 6954 } 6955 6956 #define NAME_BUFLEN 32 6957 static void 6958 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6959 { 6960 device_t dev = iflib_get_dev(ctx); 6961 struct sysctl_oid_list *child, *oid_list; 6962 struct sysctl_oid *node; 6963 6964 sysctl_ctx_init(&ctx->ifc_sysctl_ctx); 6965 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6966 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(&ctx->ifc_sysctl_ctx, child, 6967 OID_AUTO, "iflib", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 6968 "IFLIB fields"); 6969 oid_list = SYSCTL_CHILDREN(node); 6970 6971 SYSCTL_ADD_CONST_STRING(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "driver_version", 6972 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, "driver version"); 6973 6974 SYSCTL_ADD_BOOL(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "simple_tx", 6975 CTLFLAG_RDTUN, &ctx->ifc_sysctl_simple_tx, 0, 6976 "use simple tx ring"); 6977 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_ntxqs", 6978 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6979 "# of txqs to use, 0 => use default #"); 6980 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_nrxqs", 6981 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6982 "# of rxqs to use, 0 => use default #"); 6983 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_qs_enable", 6984 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6985 "permit #txq != #rxq"); 6986 SYSCTL_ADD_INT(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "disable_msix", 6987 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6988 "disable MSI-X (default 0)"); 6989 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "rx_budget", 6990 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, "set the RX budget"); 6991 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "tx_abdicate", 6992 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6993 "cause TX to abdicate instead of running to completion"); 6994 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6995 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "core_offset", 6996 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6997 "offset to start using cores at"); 6998 SYSCTL_ADD_U8(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "separate_txrx", 6999 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 7000 "use separate cores for TX and RX"); 7001 SYSCTL_ADD_U8(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "use_logical_cores", 7002 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0, 7003 "try to make use of logical cores for TX and RX"); 7004 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "use_extra_msix_vectors", 7005 CTLFLAG_RDTUN, &ctx->ifc_sysctl_extra_msix_vectors, 0, 7006 "attempt to reserve the given number of extra MSI-X vectors during driver load for the creation of additional interfaces later"); 7007 SYSCTL_ADD_INT(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "allocated_msix_vectors", 7008 CTLFLAG_RDTUN, &ctx->ifc_softc_ctx.isc_vectors, 0, 7009 "total # of MSI-X vectors allocated by driver"); 7010 7011 /* XXX change for per-queue sizes */ 7012 SYSCTL_ADD_PROC(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_ntxds", 7013 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 7014 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 7015 "list of # of TX descriptors to use, 0 = use default #"); 7016 SYSCTL_ADD_PROC(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_nrxds", 7017 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 7018 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 7019 "list of # of RX descriptors to use, 0 = use default #"); 7020 } 7021 7022 static void 7023 iflib_add_device_sysctl_post(if_ctx_t ctx) 7024 { 7025 if_shared_ctx_t sctx = ctx->ifc_sctx; 7026 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 7027 struct sysctl_oid_list *child; 7028 struct sysctl_ctx_list *ctx_list = &ctx->ifc_sysctl_ctx; 7029 iflib_fl_t fl; 7030 iflib_txq_t txq; 7031 iflib_rxq_t rxq; 7032 int i, j; 7033 char namebuf[NAME_BUFLEN]; 7034 char *qfmt; 7035 struct sysctl_oid *queue_node, *fl_node, *node; 7036 struct sysctl_oid_list *queue_list, *fl_list; 7037 7038 node = ctx->ifc_sysctl_node; 7039 child = SYSCTL_CHILDREN(node); 7040 7041 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_reclaim_thresh", 7042 CTLTYPE_INT | CTLFLAG_RWTUN, ctx, 7043 0, iflib_handle_tx_reclaim_thresh, "I", 7044 "Number of TX descs outstanding before reclaim is called"); 7045 7046 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_reclaim_ticks", 7047 CTLTYPE_INT | CTLFLAG_RWTUN, ctx, 7048 0, iflib_handle_tx_reclaim_ticks, "I", 7049 "Number of ticks before a TX reclaim is forced"); 7050 7051 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_defer_mfree", 7052 CTLTYPE_INT | CTLFLAG_RWTUN, ctx, 7053 0, iflib_handle_tx_defer_mfree, "I", 7054 "Free completed transmits outside of TX ring lock"); 7055 7056 if (scctx->isc_ntxqsets > 100) 7057 qfmt = "txq%03d"; 7058 else if (scctx->isc_ntxqsets > 10) 7059 qfmt = "txq%02d"; 7060 else 7061 qfmt = "txq%d"; 7062 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 7063 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 7064 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 7065 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 7066 queue_list = SYSCTL_CHILDREN(queue_node); 7067 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 7068 CTLFLAG_RD, &txq->ift_task.gt_cpu, 0, 7069 "cpu this queue is bound to"); 7070 #if MEMORY_LOGGING 7071 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 7072 CTLFLAG_RD, &txq->ift_dequeued, "total mbufs freed"); 7073 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 7074 CTLFLAG_RD, &txq->ift_enqueued, "total mbufs enqueued"); 7075 #endif 7076 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 7077 CTLFLAG_RD, &txq->ift_mbuf_defrag, 7078 "# of times m_defrag was called"); 7079 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 7080 CTLFLAG_RD, &txq->ift_pullups, 7081 "# of times m_pullup was called"); 7082 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7083 "mbuf_defrag_failed", CTLFLAG_RD, 7084 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 7085 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7086 "no_desc_avail", CTLFLAG_RD, &txq->ift_no_desc_avail, 7087 "# of times no descriptors were available"); 7088 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7089 "tx_map_failed", CTLFLAG_RD, &txq->ift_map_failed, 7090 "# of times DMA map failed"); 7091 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7092 "txd_encap_efbig", CTLFLAG_RD, &txq->ift_txd_encap_efbig, 7093 "# of times txd_encap returned EFBIG"); 7094 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7095 "no_tx_dma_setup", CTLFLAG_RD, &txq->ift_no_tx_dma_setup, 7096 "# of times map failed for other than EFBIG"); 7097 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 7098 CTLFLAG_RD, &txq->ift_pidx, 1, "Producer Index"); 7099 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 7100 CTLFLAG_RD, &txq->ift_cidx, 1, "Consumer Index"); 7101 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, 7102 "txq_cidx_processed", CTLFLAG_RD, &txq->ift_cidx_processed, 7103 1, "Consumer Index seen by credit update"); 7104 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 7105 CTLFLAG_RD, &txq->ift_in_use, 1, "descriptors in use"); 7106 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7107 "txq_processed", CTLFLAG_RD, &txq->ift_processed, 7108 "descriptors procesed for clean"); 7109 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 7110 CTLFLAG_RD, &txq->ift_cleaned, "total cleaned"); 7111 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 7112 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 7113 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 7114 mp_ring_state_handler, "A", "soft ring state"); 7115 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7116 "r_enqueues", CTLFLAG_RD, &txq->ift_br->enqueues, 7117 "# of enqueues to the mp_ring for this queue"); 7118 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7119 "r_drops", CTLFLAG_RD, &txq->ift_br->drops, 7120 "# of drops in the mp_ring for this queue"); 7121 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7122 "r_starts", CTLFLAG_RD, &txq->ift_br->starts, 7123 "# of normal consumer starts in mp_ring for this queue"); 7124 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7125 "r_stalls", CTLFLAG_RD, &txq->ift_br->stalls, 7126 "# of consumer stalls in the mp_ring for this queue"); 7127 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7128 "r_restarts", CTLFLAG_RD, &txq->ift_br->restarts, 7129 "# of consumer restarts in the mp_ring for this queue"); 7130 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7131 "r_abdications", CTLFLAG_RD, &txq->ift_br->abdications, 7132 "# of consumer abdications in the mp_ring for this queue"); 7133 } 7134 7135 if (scctx->isc_nrxqsets > 100) 7136 qfmt = "rxq%03d"; 7137 else if (scctx->isc_nrxqsets > 10) 7138 qfmt = "rxq%02d"; 7139 else 7140 qfmt = "rxq%d"; 7141 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 7142 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 7143 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 7144 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 7145 queue_list = SYSCTL_CHILDREN(queue_node); 7146 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 7147 CTLFLAG_RD, &rxq->ifr_task.gt_cpu, 0, 7148 "cpu this queue is bound to"); 7149 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 7150 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, 7151 "rxq_cq_cidx", CTLFLAG_RD, &rxq->ifr_cq_cidx, 1, 7152 "Consumer Index"); 7153 } 7154 7155 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 7156 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 7157 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, 7158 OID_AUTO, namebuf, CTLFLAG_RD | CTLFLAG_MPSAFE, 7159 NULL, "freelist Name"); 7160 fl_list = SYSCTL_CHILDREN(fl_node); 7161 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 7162 CTLFLAG_RD, &fl->ifl_pidx, 1, "Producer Index"); 7163 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 7164 CTLFLAG_RD, &fl->ifl_cidx, 1, "Consumer Index"); 7165 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 7166 CTLFLAG_RD, &fl->ifl_credits, 1, 7167 "credits available"); 7168 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 7169 CTLFLAG_RD, &fl->ifl_buf_size, 1, "buffer size"); 7170 #if MEMORY_LOGGING 7171 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7172 "fl_m_enqueued", CTLFLAG_RD, &fl->ifl_m_enqueued, 7173 "mbufs allocated"); 7174 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7175 "fl_m_dequeued", CTLFLAG_RD, &fl->ifl_m_dequeued, 7176 "mbufs freed"); 7177 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7178 "fl_cl_enqueued", CTLFLAG_RD, &fl->ifl_cl_enqueued, 7179 "clusters allocated"); 7180 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7181 "fl_cl_dequeued", CTLFLAG_RD, &fl->ifl_cl_dequeued, 7182 "clusters freed"); 7183 #endif 7184 } 7185 } 7186 7187 } 7188 7189 void 7190 iflib_request_reset(if_ctx_t ctx) 7191 { 7192 7193 STATE_LOCK(ctx); 7194 ctx->ifc_flags |= IFC_DO_RESET; 7195 STATE_UNLOCK(ctx); 7196 } 7197 7198 #ifndef __NO_STRICT_ALIGNMENT 7199 static struct mbuf * 7200 iflib_fixup_rx(struct mbuf *m) 7201 { 7202 struct mbuf *n; 7203 7204 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 7205 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 7206 m->m_data += ETHER_HDR_LEN; 7207 n = m; 7208 } else { 7209 MGETHDR(n, M_NOWAIT, MT_DATA); 7210 if (n == NULL) { 7211 m_freem(m); 7212 return (NULL); 7213 } 7214 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 7215 m->m_data += ETHER_HDR_LEN; 7216 m->m_len -= ETHER_HDR_LEN; 7217 n->m_len = ETHER_HDR_LEN; 7218 M_MOVE_PKTHDR(n, m); 7219 n->m_next = m; 7220 } 7221 return (n); 7222 } 7223 #endif 7224 7225 #ifdef DEBUGNET 7226 static void 7227 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 7228 { 7229 if_ctx_t ctx; 7230 7231 ctx = if_getsoftc(ifp); 7232 CTX_LOCK(ctx); 7233 *nrxr = NRXQSETS(ctx); 7234 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 7235 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 7236 CTX_UNLOCK(ctx); 7237 } 7238 7239 static void 7240 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 7241 { 7242 if_ctx_t ctx; 7243 if_softc_ctx_t scctx; 7244 iflib_fl_t fl; 7245 iflib_rxq_t rxq; 7246 int i, j; 7247 7248 ctx = if_getsoftc(ifp); 7249 scctx = &ctx->ifc_softc_ctx; 7250 7251 switch (event) { 7252 case DEBUGNET_START: 7253 for (i = 0; i < scctx->isc_nrxqsets; i++) { 7254 rxq = &ctx->ifc_rxqs[i]; 7255 for (j = 0; j < rxq->ifr_nfl; j++) { 7256 fl = rxq->ifr_fl; 7257 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 7258 } 7259 } 7260 iflib_no_tx_batch = 1; 7261 break; 7262 default: 7263 break; 7264 } 7265 } 7266 7267 static int 7268 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 7269 { 7270 if_ctx_t ctx; 7271 iflib_txq_t txq; 7272 int error; 7273 int bytes_sent = 0; 7274 int pkt_sent = 0; 7275 7276 ctx = if_getsoftc(ifp); 7277 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7278 IFF_DRV_RUNNING) 7279 return (EBUSY); 7280 7281 txq = &ctx->ifc_txqs[0]; 7282 error = iflib_encap(txq, &m, &bytes_sent, &pkt_sent); 7283 if (error == 0) 7284 (void)iflib_txd_db_check(txq, true); 7285 return (error); 7286 } 7287 7288 static int 7289 iflib_debugnet_poll(if_t ifp, int count) 7290 { 7291 struct epoch_tracker et; 7292 if_ctx_t ctx; 7293 if_softc_ctx_t scctx; 7294 iflib_txq_t txq; 7295 int i; 7296 7297 ctx = if_getsoftc(ifp); 7298 scctx = &ctx->ifc_softc_ctx; 7299 7300 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7301 IFF_DRV_RUNNING) 7302 return (EBUSY); 7303 7304 txq = &ctx->ifc_txqs[0]; 7305 (void)iflib_completed_tx_reclaim(txq, NULL); 7306 7307 NET_EPOCH_ENTER(et); 7308 for (i = 0; i < scctx->isc_nrxqsets; i++) 7309 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 7310 NET_EPOCH_EXIT(et); 7311 return (0); 7312 } 7313 #endif /* DEBUGNET */ 7314 7315 #ifndef ALTQ 7316 static inline iflib_txq_t 7317 iflib_simple_select_queue(if_ctx_t ctx, struct mbuf *m) 7318 { 7319 int qidx; 7320 7321 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 7322 qidx = QIDX(ctx, m); 7323 else 7324 qidx = NTXQSETS(ctx) + FIRST_QSET(ctx) - 1; 7325 return (&ctx->ifc_txqs[qidx]); 7326 } 7327 7328 static int 7329 iflib_simple_transmit(if_t ifp, struct mbuf *m) 7330 { 7331 if_ctx_t ctx; 7332 iflib_txq_t txq; 7333 struct mbuf **m_defer; 7334 int error, i, reclaimable; 7335 int bytes_sent = 0, pkt_sent = 0, mcast_sent = 0; 7336 7337 7338 ctx = if_getsoftc(ifp); 7339 if (__predict_false((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 7340 || !LINK_ACTIVE(ctx))) { 7341 DBG_COUNTER_INC(tx_frees); 7342 m_freem(m); 7343 return (ENETDOWN); 7344 } 7345 7346 txq = iflib_simple_select_queue(ctx, m); 7347 mtx_lock(&txq->ift_mtx); 7348 error = iflib_encap(txq, &m, &bytes_sent, &pkt_sent); 7349 if (error == 0) { 7350 mcast_sent += !!(m->m_flags & M_MCAST); 7351 (void)iflib_txd_db_check(txq, true); 7352 } else { 7353 if (error == ENOBUFS) 7354 if_inc_counter(ifp, IFCOUNTER_OQDROPS, 1); 7355 else 7356 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 7357 } 7358 m_defer = NULL; 7359 reclaimable = iflib_txq_can_reclaim(txq); 7360 if (reclaimable != 0) { 7361 /* 7362 * Try to set m_defer to the deferred mbuf reclaim array. If 7363 * we can, the frees will happen outside the tx lock. If we 7364 * can't, it means another thread is still proccessing frees. 7365 */ 7366 if (txq->ift_defer_mfree && 7367 atomic_cmpset_acq_ptr((uintptr_t *)&txq->ift_sds.ifsd_m_defer, 7368 (uintptr_t )txq->ift_sds.ifsd_m_deferb, 0)) { 7369 m_defer = txq->ift_sds.ifsd_m_deferb; 7370 } 7371 _iflib_completed_tx_reclaim(txq, m_defer, reclaimable); 7372 } 7373 mtx_unlock(&txq->ift_mtx); 7374 7375 /* 7376 * Process mbuf frees outside the tx lock 7377 */ 7378 if (m_defer != NULL) { 7379 for (i = 0; m_defer[i] != NULL; i++) { 7380 m_freem(m_defer[i]); 7381 m_defer[i] = NULL; 7382 } 7383 atomic_store_rel_ptr((uintptr_t *)&txq->ift_sds.ifsd_m_defer, 7384 (uintptr_t)m_defer); 7385 } 7386 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 7387 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 7388 if (mcast_sent) 7389 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 7390 7391 return (error); 7392 } 7393 #endif 7394