1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/jail.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/md5.h> 44 #include <sys/mutex.h> 45 #include <sys/module.h> 46 #include <sys/kobj.h> 47 #include <sys/rman.h> 48 #include <sys/proc.h> 49 #include <sys/sbuf.h> 50 #include <sys/smp.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/syslog.h> 55 #include <sys/taskqueue.h> 56 #include <sys/limits.h> 57 58 #include <net/if.h> 59 #include <net/if_var.h> 60 #include <net/if_types.h> 61 #include <net/if_media.h> 62 #include <net/bpf.h> 63 #include <net/ethernet.h> 64 #include <net/mp_ring.h> 65 #include <net/vnet.h> 66 67 #include <netinet/in.h> 68 #include <netinet/in_pcb.h> 69 #include <netinet/tcp_lro.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/if_ether.h> 72 #include <netinet/ip.h> 73 #include <netinet/ip6.h> 74 #include <netinet/tcp.h> 75 #include <netinet/ip_var.h> 76 #include <netinet/netdump/netdump.h> 77 #include <netinet6/ip6_var.h> 78 79 #include <machine/bus.h> 80 #include <machine/in_cksum.h> 81 82 #include <vm/vm.h> 83 #include <vm/pmap.h> 84 85 #include <dev/led/led.h> 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pci_private.h> 89 90 #include <net/iflib.h> 91 #include <net/iflib_private.h> 92 93 #include "ifdi_if.h" 94 95 #if defined(__i386__) || defined(__amd64__) 96 #include <sys/memdesc.h> 97 #include <machine/bus.h> 98 #include <machine/md_var.h> 99 #include <machine/specialreg.h> 100 #include <x86/include/busdma_impl.h> 101 #include <x86/iommu/busdma_dmar.h> 102 #endif 103 104 #include <sys/bitstring.h> 105 /* 106 * enable accounting of every mbuf as it comes in to and goes out of 107 * iflib's software descriptor references 108 */ 109 #define MEMORY_LOGGING 0 110 /* 111 * Enable mbuf vectors for compressing long mbuf chains 112 */ 113 114 /* 115 * NB: 116 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 117 * we prefetch needs to be determined by the time spent in m_free vis a vis 118 * the cost of a prefetch. This will of course vary based on the workload: 119 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 120 * is quite expensive, thus suggesting very little prefetch. 121 * - small packet forwarding which is just returning a single mbuf to 122 * UMA will typically be very fast vis a vis the cost of a memory 123 * access. 124 */ 125 126 127 /* 128 * File organization: 129 * - private structures 130 * - iflib private utility functions 131 * - ifnet functions 132 * - vlan registry and other exported functions 133 * - iflib public core functions 134 * 135 * 136 */ 137 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 138 139 struct iflib_txq; 140 typedef struct iflib_txq *iflib_txq_t; 141 struct iflib_rxq; 142 typedef struct iflib_rxq *iflib_rxq_t; 143 struct iflib_fl; 144 typedef struct iflib_fl *iflib_fl_t; 145 146 struct iflib_ctx; 147 148 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 149 static void iflib_timer(void *arg); 150 151 typedef struct iflib_filter_info { 152 driver_filter_t *ifi_filter; 153 void *ifi_filter_arg; 154 struct grouptask *ifi_task; 155 void *ifi_ctx; 156 } *iflib_filter_info_t; 157 158 struct iflib_ctx { 159 KOBJ_FIELDS; 160 /* 161 * Pointer to hardware driver's softc 162 */ 163 void *ifc_softc; 164 device_t ifc_dev; 165 if_t ifc_ifp; 166 167 cpuset_t ifc_cpus; 168 if_shared_ctx_t ifc_sctx; 169 struct if_softc_ctx ifc_softc_ctx; 170 171 struct sx ifc_ctx_sx; 172 struct mtx ifc_state_mtx; 173 174 uint16_t ifc_nhwtxqs; 175 176 iflib_txq_t ifc_txqs; 177 iflib_rxq_t ifc_rxqs; 178 uint32_t ifc_if_flags; 179 uint32_t ifc_flags; 180 uint32_t ifc_max_fl_buf_size; 181 int ifc_in_detach; 182 183 int ifc_link_state; 184 int ifc_link_irq; 185 int ifc_watchdog_events; 186 struct cdev *ifc_led_dev; 187 struct resource *ifc_msix_mem; 188 189 struct if_irq ifc_legacy_irq; 190 struct grouptask ifc_admin_task; 191 struct grouptask ifc_vflr_task; 192 struct iflib_filter_info ifc_filter_info; 193 struct ifmedia ifc_media; 194 195 struct sysctl_oid *ifc_sysctl_node; 196 uint16_t ifc_sysctl_ntxqs; 197 uint16_t ifc_sysctl_nrxqs; 198 uint16_t ifc_sysctl_qs_eq_override; 199 uint16_t ifc_sysctl_rx_budget; 200 uint16_t ifc_sysctl_tx_abdicate; 201 202 qidx_t ifc_sysctl_ntxds[8]; 203 qidx_t ifc_sysctl_nrxds[8]; 204 struct if_txrx ifc_txrx; 205 #define isc_txd_encap ifc_txrx.ift_txd_encap 206 #define isc_txd_flush ifc_txrx.ift_txd_flush 207 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 208 #define isc_rxd_available ifc_txrx.ift_rxd_available 209 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 210 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 211 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 212 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 213 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 214 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 215 eventhandler_tag ifc_vlan_attach_event; 216 eventhandler_tag ifc_vlan_detach_event; 217 uint8_t ifc_mac[ETHER_ADDR_LEN]; 218 char ifc_mtx_name[16]; 219 }; 220 221 222 void * 223 iflib_get_softc(if_ctx_t ctx) 224 { 225 226 return (ctx->ifc_softc); 227 } 228 229 device_t 230 iflib_get_dev(if_ctx_t ctx) 231 { 232 233 return (ctx->ifc_dev); 234 } 235 236 if_t 237 iflib_get_ifp(if_ctx_t ctx) 238 { 239 240 return (ctx->ifc_ifp); 241 } 242 243 struct ifmedia * 244 iflib_get_media(if_ctx_t ctx) 245 { 246 247 return (&ctx->ifc_media); 248 } 249 250 uint32_t 251 iflib_get_flags(if_ctx_t ctx) 252 { 253 return (ctx->ifc_flags); 254 } 255 256 void 257 iflib_set_detach(if_ctx_t ctx) 258 { 259 ctx->ifc_in_detach = 1; 260 } 261 262 void 263 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 264 { 265 266 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 267 } 268 269 if_softc_ctx_t 270 iflib_get_softc_ctx(if_ctx_t ctx) 271 { 272 273 return (&ctx->ifc_softc_ctx); 274 } 275 276 if_shared_ctx_t 277 iflib_get_sctx(if_ctx_t ctx) 278 { 279 280 return (ctx->ifc_sctx); 281 } 282 283 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 284 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 285 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 286 287 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 288 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 289 290 #define RX_SW_DESC_MAP_CREATED (1 << 0) 291 #define TX_SW_DESC_MAP_CREATED (1 << 1) 292 #define RX_SW_DESC_INUSE (1 << 3) 293 #define TX_SW_DESC_MAPPED (1 << 4) 294 295 #define M_TOOBIG M_PROTO1 296 297 typedef struct iflib_sw_rx_desc_array { 298 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 299 struct mbuf **ifsd_m; /* pkthdr mbufs */ 300 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 301 uint8_t *ifsd_flags; 302 } iflib_rxsd_array_t; 303 304 typedef struct iflib_sw_tx_desc_array { 305 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 306 struct mbuf **ifsd_m; /* pkthdr mbufs */ 307 uint8_t *ifsd_flags; 308 } if_txsd_vec_t; 309 310 311 /* magic number that should be high enough for any hardware */ 312 #define IFLIB_MAX_TX_SEGS 128 313 /* bnxt supports 64 with hardware LRO enabled */ 314 #define IFLIB_MAX_RX_SEGS 64 315 #define IFLIB_RX_COPY_THRESH 128 316 #define IFLIB_MAX_RX_REFRESH 32 317 /* The minimum descriptors per second before we start coalescing */ 318 #define IFLIB_MIN_DESC_SEC 16384 319 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 320 #define IFLIB_QUEUE_IDLE 0 321 #define IFLIB_QUEUE_HUNG 1 322 #define IFLIB_QUEUE_WORKING 2 323 /* maximum number of txqs that can share an rx interrupt */ 324 #define IFLIB_MAX_TX_SHARED_INTR 4 325 326 /* this should really scale with ring size - this is a fairly arbitrary value */ 327 #define TX_BATCH_SIZE 32 328 329 #define IFLIB_RESTART_BUDGET 8 330 331 332 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 333 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 334 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 335 struct iflib_txq { 336 qidx_t ift_in_use; 337 qidx_t ift_cidx; 338 qidx_t ift_cidx_processed; 339 qidx_t ift_pidx; 340 uint8_t ift_gen; 341 uint8_t ift_br_offset; 342 uint16_t ift_npending; 343 uint16_t ift_db_pending; 344 uint16_t ift_rs_pending; 345 /* implicit pad */ 346 uint8_t ift_txd_size[8]; 347 uint64_t ift_processed; 348 uint64_t ift_cleaned; 349 uint64_t ift_cleaned_prev; 350 #if MEMORY_LOGGING 351 uint64_t ift_enqueued; 352 uint64_t ift_dequeued; 353 #endif 354 uint64_t ift_no_tx_dma_setup; 355 uint64_t ift_no_desc_avail; 356 uint64_t ift_mbuf_defrag_failed; 357 uint64_t ift_mbuf_defrag; 358 uint64_t ift_map_failed; 359 uint64_t ift_txd_encap_efbig; 360 uint64_t ift_pullups; 361 uint64_t ift_last_timer_tick; 362 363 struct mtx ift_mtx; 364 struct mtx ift_db_mtx; 365 366 /* constant values */ 367 if_ctx_t ift_ctx; 368 struct ifmp_ring *ift_br; 369 struct grouptask ift_task; 370 qidx_t ift_size; 371 uint16_t ift_id; 372 struct callout ift_timer; 373 374 if_txsd_vec_t ift_sds; 375 uint8_t ift_qstatus; 376 uint8_t ift_closed; 377 uint8_t ift_update_freq; 378 struct iflib_filter_info ift_filter_info; 379 bus_dma_tag_t ift_desc_tag; 380 bus_dma_tag_t ift_tso_desc_tag; 381 iflib_dma_info_t ift_ifdi; 382 #define MTX_NAME_LEN 16 383 char ift_mtx_name[MTX_NAME_LEN]; 384 char ift_db_mtx_name[MTX_NAME_LEN]; 385 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 386 #ifdef IFLIB_DIAGNOSTICS 387 uint64_t ift_cpu_exec_count[256]; 388 #endif 389 } __aligned(CACHE_LINE_SIZE); 390 391 struct iflib_fl { 392 qidx_t ifl_cidx; 393 qidx_t ifl_pidx; 394 qidx_t ifl_credits; 395 uint8_t ifl_gen; 396 uint8_t ifl_rxd_size; 397 #if MEMORY_LOGGING 398 uint64_t ifl_m_enqueued; 399 uint64_t ifl_m_dequeued; 400 uint64_t ifl_cl_enqueued; 401 uint64_t ifl_cl_dequeued; 402 #endif 403 /* implicit pad */ 404 405 bitstr_t *ifl_rx_bitmap; 406 qidx_t ifl_fragidx; 407 /* constant */ 408 qidx_t ifl_size; 409 uint16_t ifl_buf_size; 410 uint16_t ifl_cltype; 411 uma_zone_t ifl_zone; 412 iflib_rxsd_array_t ifl_sds; 413 iflib_rxq_t ifl_rxq; 414 uint8_t ifl_id; 415 bus_dma_tag_t ifl_desc_tag; 416 iflib_dma_info_t ifl_ifdi; 417 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 418 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 419 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 420 } __aligned(CACHE_LINE_SIZE); 421 422 static inline qidx_t 423 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 424 { 425 qidx_t used; 426 427 if (pidx > cidx) 428 used = pidx - cidx; 429 else if (pidx < cidx) 430 used = size - cidx + pidx; 431 else if (gen == 0 && pidx == cidx) 432 used = 0; 433 else if (gen == 1 && pidx == cidx) 434 used = size; 435 else 436 panic("bad state"); 437 438 return (used); 439 } 440 441 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 442 443 #define IDXDIFF(head, tail, wrap) \ 444 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 445 446 struct iflib_rxq { 447 /* If there is a separate completion queue - 448 * these are the cq cidx and pidx. Otherwise 449 * these are unused. 450 */ 451 qidx_t ifr_size; 452 qidx_t ifr_cq_cidx; 453 qidx_t ifr_cq_pidx; 454 uint8_t ifr_cq_gen; 455 uint8_t ifr_fl_offset; 456 457 if_ctx_t ifr_ctx; 458 iflib_fl_t ifr_fl; 459 uint64_t ifr_rx_irq; 460 uint16_t ifr_id; 461 uint8_t ifr_lro_enabled; 462 uint8_t ifr_nfl; 463 uint8_t ifr_ntxqirq; 464 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 465 struct lro_ctrl ifr_lc; 466 struct grouptask ifr_task; 467 struct iflib_filter_info ifr_filter_info; 468 iflib_dma_info_t ifr_ifdi; 469 470 /* dynamically allocate if any drivers need a value substantially larger than this */ 471 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 472 #ifdef IFLIB_DIAGNOSTICS 473 uint64_t ifr_cpu_exec_count[256]; 474 #endif 475 } __aligned(CACHE_LINE_SIZE); 476 477 typedef struct if_rxsd { 478 caddr_t *ifsd_cl; 479 struct mbuf **ifsd_m; 480 iflib_fl_t ifsd_fl; 481 qidx_t ifsd_cidx; 482 } *if_rxsd_t; 483 484 /* multiple of word size */ 485 #ifdef __LP64__ 486 #define PKT_INFO_SIZE 6 487 #define RXD_INFO_SIZE 5 488 #define PKT_TYPE uint64_t 489 #else 490 #define PKT_INFO_SIZE 11 491 #define RXD_INFO_SIZE 8 492 #define PKT_TYPE uint32_t 493 #endif 494 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 495 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 496 497 typedef struct if_pkt_info_pad { 498 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 499 } *if_pkt_info_pad_t; 500 typedef struct if_rxd_info_pad { 501 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 502 } *if_rxd_info_pad_t; 503 504 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 505 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 506 507 508 static inline void 509 pkt_info_zero(if_pkt_info_t pi) 510 { 511 if_pkt_info_pad_t pi_pad; 512 513 pi_pad = (if_pkt_info_pad_t)pi; 514 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 515 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 516 #ifndef __LP64__ 517 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 518 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 519 #endif 520 } 521 522 static device_method_t iflib_pseudo_methods[] = { 523 DEVMETHOD(device_attach, noop_attach), 524 DEVMETHOD(device_detach, iflib_pseudo_detach), 525 DEVMETHOD_END 526 }; 527 528 driver_t iflib_pseudodriver = { 529 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 530 }; 531 532 static inline void 533 rxd_info_zero(if_rxd_info_t ri) 534 { 535 if_rxd_info_pad_t ri_pad; 536 int i; 537 538 ri_pad = (if_rxd_info_pad_t)ri; 539 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 540 ri_pad->rxd_val[i] = 0; 541 ri_pad->rxd_val[i+1] = 0; 542 ri_pad->rxd_val[i+2] = 0; 543 ri_pad->rxd_val[i+3] = 0; 544 } 545 #ifdef __LP64__ 546 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 547 #endif 548 } 549 550 /* 551 * Only allow a single packet to take up most 1/nth of the tx ring 552 */ 553 #define MAX_SINGLE_PACKET_FRACTION 12 554 #define IF_BAD_DMA (bus_addr_t)-1 555 556 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 557 558 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 559 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 560 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 561 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 562 563 564 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 565 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 566 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 567 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 568 569 570 571 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 572 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 573 574 575 /* Our boot-time initialization hook */ 576 static int iflib_module_event_handler(module_t, int, void *); 577 578 static moduledata_t iflib_moduledata = { 579 "iflib", 580 iflib_module_event_handler, 581 NULL 582 }; 583 584 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 585 MODULE_VERSION(iflib, 1); 586 587 MODULE_DEPEND(iflib, pci, 1, 1, 1); 588 MODULE_DEPEND(iflib, ether, 1, 1, 1); 589 590 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 591 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 592 593 #ifndef IFLIB_DEBUG_COUNTERS 594 #ifdef INVARIANTS 595 #define IFLIB_DEBUG_COUNTERS 1 596 #else 597 #define IFLIB_DEBUG_COUNTERS 0 598 #endif /* !INVARIANTS */ 599 #endif 600 601 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 602 "iflib driver parameters"); 603 604 /* 605 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 606 */ 607 static int iflib_min_tx_latency = 0; 608 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 609 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 610 static int iflib_no_tx_batch = 0; 611 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 612 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 613 614 615 #if IFLIB_DEBUG_COUNTERS 616 617 static int iflib_tx_seen; 618 static int iflib_tx_sent; 619 static int iflib_tx_encap; 620 static int iflib_rx_allocs; 621 static int iflib_fl_refills; 622 static int iflib_fl_refills_large; 623 static int iflib_tx_frees; 624 625 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 626 &iflib_tx_seen, 0, "# tx mbufs seen"); 627 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 628 &iflib_tx_sent, 0, "# tx mbufs sent"); 629 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 630 &iflib_tx_encap, 0, "# tx mbufs encapped"); 631 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 632 &iflib_tx_frees, 0, "# tx frees"); 633 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 634 &iflib_rx_allocs, 0, "# rx allocations"); 635 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 636 &iflib_fl_refills, 0, "# refills"); 637 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 638 &iflib_fl_refills_large, 0, "# large refills"); 639 640 641 static int iflib_txq_drain_flushing; 642 static int iflib_txq_drain_oactive; 643 static int iflib_txq_drain_notready; 644 static int iflib_txq_drain_encapfail; 645 646 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 647 &iflib_txq_drain_flushing, 0, "# drain flushes"); 648 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 649 &iflib_txq_drain_oactive, 0, "# drain oactives"); 650 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 651 &iflib_txq_drain_notready, 0, "# drain notready"); 652 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 653 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 654 655 656 static int iflib_encap_load_mbuf_fail; 657 static int iflib_encap_pad_mbuf_fail; 658 static int iflib_encap_txq_avail_fail; 659 static int iflib_encap_txd_encap_fail; 660 661 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 662 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 664 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 666 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 668 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 669 670 static int iflib_task_fn_rxs; 671 static int iflib_rx_intr_enables; 672 static int iflib_fast_intrs; 673 static int iflib_intr_link; 674 static int iflib_intr_msix; 675 static int iflib_rx_unavail; 676 static int iflib_rx_ctx_inactive; 677 static int iflib_rx_zero_len; 678 static int iflib_rx_if_input; 679 static int iflib_rx_mbuf_null; 680 static int iflib_rxd_flush; 681 682 static int iflib_verbose_debug; 683 684 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 685 &iflib_intr_link, 0, "# intr link calls"); 686 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 687 &iflib_intr_msix, 0, "# intr msix calls"); 688 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 689 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 690 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 691 &iflib_rx_intr_enables, 0, "# rx intr enables"); 692 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 693 &iflib_fast_intrs, 0, "# fast_intr calls"); 694 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 695 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 696 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 697 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 698 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 699 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 700 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 701 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 702 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 703 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 704 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 705 &iflib_rxd_flush, 0, "# times rxd_flush called"); 706 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 707 &iflib_verbose_debug, 0, "enable verbose debugging"); 708 709 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 710 static void 711 iflib_debug_reset(void) 712 { 713 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 714 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 715 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 716 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 717 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 718 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 719 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 720 iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 721 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 722 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 723 } 724 725 #else 726 #define DBG_COUNTER_INC(name) 727 static void iflib_debug_reset(void) {} 728 #endif 729 730 #define IFLIB_DEBUG 0 731 732 static void iflib_tx_structures_free(if_ctx_t ctx); 733 static void iflib_rx_structures_free(if_ctx_t ctx); 734 static int iflib_queues_alloc(if_ctx_t ctx); 735 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 736 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 737 static int iflib_qset_structures_setup(if_ctx_t ctx); 738 static int iflib_msix_init(if_ctx_t ctx); 739 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 740 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 741 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 742 static int iflib_register(if_ctx_t); 743 static void iflib_init_locked(if_ctx_t ctx); 744 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 745 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 746 static void iflib_ifmp_purge(iflib_txq_t txq); 747 static void _iflib_pre_assert(if_softc_ctx_t scctx); 748 static void iflib_if_init_locked(if_ctx_t ctx); 749 #ifndef __NO_STRICT_ALIGNMENT 750 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 751 #endif 752 753 NETDUMP_DEFINE(iflib); 754 755 #ifdef DEV_NETMAP 756 #include <sys/selinfo.h> 757 #include <net/netmap.h> 758 #include <dev/netmap/netmap_kern.h> 759 760 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 761 762 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 763 764 /* 765 * device-specific sysctl variables: 766 * 767 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 768 * During regular operations the CRC is stripped, but on some 769 * hardware reception of frames not multiple of 64 is slower, 770 * so using crcstrip=0 helps in benchmarks. 771 * 772 * iflib_rx_miss, iflib_rx_miss_bufs: 773 * count packets that might be missed due to lost interrupts. 774 */ 775 SYSCTL_DECL(_dev_netmap); 776 /* 777 * The xl driver by default strips CRCs and we do not override it. 778 */ 779 780 int iflib_crcstrip = 1; 781 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 782 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 783 784 int iflib_rx_miss, iflib_rx_miss_bufs; 785 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 786 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 787 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 788 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 789 790 /* 791 * Register/unregister. We are already under netmap lock. 792 * Only called on the first register or the last unregister. 793 */ 794 static int 795 iflib_netmap_register(struct netmap_adapter *na, int onoff) 796 { 797 struct ifnet *ifp = na->ifp; 798 if_ctx_t ctx = ifp->if_softc; 799 int status; 800 801 CTX_LOCK(ctx); 802 IFDI_INTR_DISABLE(ctx); 803 804 /* Tell the stack that the interface is no longer active */ 805 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 806 807 if (!CTX_IS_VF(ctx)) 808 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 809 810 /* enable or disable flags and callbacks in na and ifp */ 811 if (onoff) { 812 nm_set_native_flags(na); 813 } else { 814 nm_clear_native_flags(na); 815 } 816 iflib_stop(ctx); 817 iflib_init_locked(ctx); 818 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 819 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 820 if (status) 821 nm_clear_native_flags(na); 822 CTX_UNLOCK(ctx); 823 return (status); 824 } 825 826 static int 827 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 828 { 829 struct netmap_adapter *na = kring->na; 830 u_int const lim = kring->nkr_num_slots - 1; 831 u_int head = kring->rhead; 832 struct netmap_ring *ring = kring->ring; 833 bus_dmamap_t *map; 834 struct if_rxd_update iru; 835 if_ctx_t ctx = rxq->ifr_ctx; 836 iflib_fl_t fl = &rxq->ifr_fl[0]; 837 uint32_t refill_pidx, nic_i; 838 839 if (nm_i == head && __predict_true(!init)) 840 return 0; 841 iru_init(&iru, rxq, 0 /* flid */); 842 map = fl->ifl_sds.ifsd_map; 843 refill_pidx = netmap_idx_k2n(kring, nm_i); 844 /* 845 * IMPORTANT: we must leave one free slot in the ring, 846 * so move head back by one unit 847 */ 848 head = nm_prev(head, lim); 849 nic_i = UINT_MAX; 850 while (nm_i != head) { 851 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 852 struct netmap_slot *slot = &ring->slot[nm_i]; 853 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 854 uint32_t nic_i_dma = refill_pidx; 855 nic_i = netmap_idx_k2n(kring, nm_i); 856 857 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 858 859 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 860 return netmap_ring_reinit(kring); 861 862 fl->ifl_vm_addrs[tmp_pidx] = addr; 863 if (__predict_false(init) && map) { 864 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 865 } else if (map && (slot->flags & NS_BUF_CHANGED)) { 866 /* buffer has changed, reload map */ 867 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 868 } 869 slot->flags &= ~NS_BUF_CHANGED; 870 871 nm_i = nm_next(nm_i, lim); 872 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 873 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 874 continue; 875 876 iru.iru_pidx = refill_pidx; 877 iru.iru_count = tmp_pidx+1; 878 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 879 880 refill_pidx = nic_i; 881 if (map == NULL) 882 continue; 883 884 for (int n = 0; n < iru.iru_count; n++) { 885 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma], 886 BUS_DMASYNC_PREREAD); 887 /* XXX - change this to not use the netmap func*/ 888 nic_i_dma = nm_next(nic_i_dma, lim); 889 } 890 } 891 } 892 kring->nr_hwcur = head; 893 894 if (map) 895 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 896 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 897 if (__predict_true(nic_i != UINT_MAX)) 898 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 899 return (0); 900 } 901 902 /* 903 * Reconcile kernel and user view of the transmit ring. 904 * 905 * All information is in the kring. 906 * Userspace wants to send packets up to the one before kring->rhead, 907 * kernel knows kring->nr_hwcur is the first unsent packet. 908 * 909 * Here we push packets out (as many as possible), and possibly 910 * reclaim buffers from previously completed transmission. 911 * 912 * The caller (netmap) guarantees that there is only one instance 913 * running at any time. Any interference with other driver 914 * methods should be handled by the individual drivers. 915 */ 916 static int 917 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 918 { 919 struct netmap_adapter *na = kring->na; 920 struct ifnet *ifp = na->ifp; 921 struct netmap_ring *ring = kring->ring; 922 u_int nm_i; /* index into the netmap kring */ 923 u_int nic_i; /* index into the NIC ring */ 924 u_int n; 925 u_int const lim = kring->nkr_num_slots - 1; 926 u_int const head = kring->rhead; 927 struct if_pkt_info pi; 928 929 /* 930 * interrupts on every tx packet are expensive so request 931 * them every half ring, or where NS_REPORT is set 932 */ 933 u_int report_frequency = kring->nkr_num_slots >> 1; 934 /* device-specific */ 935 if_ctx_t ctx = ifp->if_softc; 936 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 937 938 if (txq->ift_sds.ifsd_map) 939 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 940 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 941 942 943 /* 944 * First part: process new packets to send. 945 * nm_i is the current index in the netmap kring, 946 * nic_i is the corresponding index in the NIC ring. 947 * 948 * If we have packets to send (nm_i != head) 949 * iterate over the netmap ring, fetch length and update 950 * the corresponding slot in the NIC ring. Some drivers also 951 * need to update the buffer's physical address in the NIC slot 952 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 953 * 954 * The netmap_reload_map() calls is especially expensive, 955 * even when (as in this case) the tag is 0, so do only 956 * when the buffer has actually changed. 957 * 958 * If possible do not set the report/intr bit on all slots, 959 * but only a few times per ring or when NS_REPORT is set. 960 * 961 * Finally, on 10G and faster drivers, it might be useful 962 * to prefetch the next slot and txr entry. 963 */ 964 965 nm_i = kring->nr_hwcur; 966 if (nm_i != head) { /* we have new packets to send */ 967 pkt_info_zero(&pi); 968 pi.ipi_segs = txq->ift_segs; 969 pi.ipi_qsidx = kring->ring_id; 970 nic_i = netmap_idx_k2n(kring, nm_i); 971 972 __builtin_prefetch(&ring->slot[nm_i]); 973 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 974 if (txq->ift_sds.ifsd_map) 975 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 976 977 for (n = 0; nm_i != head; n++) { 978 struct netmap_slot *slot = &ring->slot[nm_i]; 979 u_int len = slot->len; 980 uint64_t paddr; 981 void *addr = PNMB(na, slot, &paddr); 982 int flags = (slot->flags & NS_REPORT || 983 nic_i == 0 || nic_i == report_frequency) ? 984 IPI_TX_INTR : 0; 985 986 /* device-specific */ 987 pi.ipi_len = len; 988 pi.ipi_segs[0].ds_addr = paddr; 989 pi.ipi_segs[0].ds_len = len; 990 pi.ipi_nsegs = 1; 991 pi.ipi_ndescs = 0; 992 pi.ipi_pidx = nic_i; 993 pi.ipi_flags = flags; 994 995 /* Fill the slot in the NIC ring. */ 996 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 997 998 /* prefetch for next round */ 999 __builtin_prefetch(&ring->slot[nm_i + 1]); 1000 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1001 if (txq->ift_sds.ifsd_map) { 1002 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1003 1004 NM_CHECK_ADDR_LEN(na, addr, len); 1005 1006 if (slot->flags & NS_BUF_CHANGED) { 1007 /* buffer has changed, reload map */ 1008 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 1009 } 1010 /* make sure changes to the buffer are synced */ 1011 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 1012 BUS_DMASYNC_PREWRITE); 1013 } 1014 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1015 nm_i = nm_next(nm_i, lim); 1016 nic_i = nm_next(nic_i, lim); 1017 } 1018 kring->nr_hwcur = nm_i; 1019 1020 /* synchronize the NIC ring */ 1021 if (txq->ift_sds.ifsd_map) 1022 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 1023 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1024 1025 /* (re)start the tx unit up to slot nic_i (excluded) */ 1026 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1027 } 1028 1029 /* 1030 * Second part: reclaim buffers for completed transmissions. 1031 * 1032 * If there are unclaimed buffers, attempt to reclaim them. 1033 * If none are reclaimed, and TX IRQs are not in use, do an initial 1034 * minimal delay, then trigger the tx handler which will spin in the 1035 * group task queue. 1036 */ 1037 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1038 if (iflib_tx_credits_update(ctx, txq)) { 1039 /* some tx completed, increment avail */ 1040 nic_i = txq->ift_cidx_processed; 1041 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1042 } 1043 } 1044 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1045 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1046 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1047 iflib_timer, txq, txq->ift_timer.c_cpu); 1048 } 1049 return (0); 1050 } 1051 1052 /* 1053 * Reconcile kernel and user view of the receive ring. 1054 * Same as for the txsync, this routine must be efficient. 1055 * The caller guarantees a single invocations, but races against 1056 * the rest of the driver should be handled here. 1057 * 1058 * On call, kring->rhead is the first packet that userspace wants 1059 * to keep, and kring->rcur is the wakeup point. 1060 * The kernel has previously reported packets up to kring->rtail. 1061 * 1062 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1063 * of whether or not we received an interrupt. 1064 */ 1065 static int 1066 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1067 { 1068 struct netmap_adapter *na = kring->na; 1069 struct netmap_ring *ring = kring->ring; 1070 uint32_t nm_i; /* index into the netmap ring */ 1071 uint32_t nic_i; /* index into the NIC ring */ 1072 u_int i, n; 1073 u_int const lim = kring->nkr_num_slots - 1; 1074 u_int const head = kring->rhead; 1075 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1076 struct if_rxd_info ri; 1077 1078 struct ifnet *ifp = na->ifp; 1079 if_ctx_t ctx = ifp->if_softc; 1080 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1081 iflib_fl_t fl = rxq->ifr_fl; 1082 if (head > lim) 1083 return netmap_ring_reinit(kring); 1084 1085 /* XXX check sync modes */ 1086 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1087 if (fl->ifl_sds.ifsd_map == NULL) 1088 continue; 1089 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 1090 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1091 } 1092 /* 1093 * First part: import newly received packets. 1094 * 1095 * nm_i is the index of the next free slot in the netmap ring, 1096 * nic_i is the index of the next received packet in the NIC ring, 1097 * and they may differ in case if_init() has been called while 1098 * in netmap mode. For the receive ring we have 1099 * 1100 * nic_i = rxr->next_check; 1101 * nm_i = kring->nr_hwtail (previous) 1102 * and 1103 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1104 * 1105 * rxr->next_check is set to 0 on a ring reinit 1106 */ 1107 if (netmap_no_pendintr || force_update) { 1108 int crclen = iflib_crcstrip ? 0 : 4; 1109 int error, avail; 1110 1111 for (i = 0; i < rxq->ifr_nfl; i++) { 1112 fl = &rxq->ifr_fl[i]; 1113 nic_i = fl->ifl_cidx; 1114 nm_i = netmap_idx_n2k(kring, nic_i); 1115 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 1116 for (n = 0; avail > 0; n++, avail--) { 1117 rxd_info_zero(&ri); 1118 ri.iri_frags = rxq->ifr_frags; 1119 ri.iri_qsidx = kring->ring_id; 1120 ri.iri_ifp = ctx->ifc_ifp; 1121 ri.iri_cidx = nic_i; 1122 1123 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1124 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1125 ring->slot[nm_i].flags = 0; 1126 if (fl->ifl_sds.ifsd_map) 1127 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1128 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1129 nm_i = nm_next(nm_i, lim); 1130 nic_i = nm_next(nic_i, lim); 1131 } 1132 if (n) { /* update the state variables */ 1133 if (netmap_no_pendintr && !force_update) { 1134 /* diagnostics */ 1135 iflib_rx_miss ++; 1136 iflib_rx_miss_bufs += n; 1137 } 1138 fl->ifl_cidx = nic_i; 1139 kring->nr_hwtail = nm_i; 1140 } 1141 kring->nr_kflags &= ~NKR_PENDINTR; 1142 } 1143 } 1144 /* 1145 * Second part: skip past packets that userspace has released. 1146 * (kring->nr_hwcur to head excluded), 1147 * and make the buffers available for reception. 1148 * As usual nm_i is the index in the netmap ring, 1149 * nic_i is the index in the NIC ring, and 1150 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1151 */ 1152 /* XXX not sure how this will work with multiple free lists */ 1153 nm_i = kring->nr_hwcur; 1154 1155 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1156 } 1157 1158 static void 1159 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1160 { 1161 struct ifnet *ifp = na->ifp; 1162 if_ctx_t ctx = ifp->if_softc; 1163 1164 CTX_LOCK(ctx); 1165 if (onoff) { 1166 IFDI_INTR_ENABLE(ctx); 1167 } else { 1168 IFDI_INTR_DISABLE(ctx); 1169 } 1170 CTX_UNLOCK(ctx); 1171 } 1172 1173 1174 static int 1175 iflib_netmap_attach(if_ctx_t ctx) 1176 { 1177 struct netmap_adapter na; 1178 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1179 1180 bzero(&na, sizeof(na)); 1181 1182 na.ifp = ctx->ifc_ifp; 1183 na.na_flags = NAF_BDG_MAYSLEEP; 1184 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1185 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1186 1187 na.num_tx_desc = scctx->isc_ntxd[0]; 1188 na.num_rx_desc = scctx->isc_nrxd[0]; 1189 na.nm_txsync = iflib_netmap_txsync; 1190 na.nm_rxsync = iflib_netmap_rxsync; 1191 na.nm_register = iflib_netmap_register; 1192 na.nm_intr = iflib_netmap_intr; 1193 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1194 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1195 return (netmap_attach(&na)); 1196 } 1197 1198 static void 1199 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1200 { 1201 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1202 struct netmap_slot *slot; 1203 1204 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1205 if (slot == NULL) 1206 return; 1207 if (txq->ift_sds.ifsd_map == NULL) 1208 return; 1209 1210 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1211 1212 /* 1213 * In netmap mode, set the map for the packet buffer. 1214 * NOTE: Some drivers (not this one) also need to set 1215 * the physical buffer address in the NIC ring. 1216 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1217 * netmap slot index, si 1218 */ 1219 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1220 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1221 } 1222 } 1223 1224 static void 1225 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1226 { 1227 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1228 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1229 struct netmap_slot *slot; 1230 uint32_t nm_i; 1231 1232 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1233 if (slot == NULL) 1234 return; 1235 nm_i = netmap_idx_n2k(kring, 0); 1236 netmap_fl_refill(rxq, kring, nm_i, true); 1237 } 1238 1239 static void 1240 iflib_netmap_timer_adjust(if_ctx_t ctx, uint16_t txqid, uint32_t *reset_on) 1241 { 1242 struct netmap_kring *kring; 1243 1244 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1245 1246 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1247 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1248 netmap_tx_irq(ctx->ifc_ifp, txqid); 1249 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1250 if (hz < 2000) 1251 *reset_on = 1; 1252 else 1253 *reset_on = hz / 1000; 1254 } 1255 } 1256 } 1257 1258 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1259 1260 #else 1261 #define iflib_netmap_txq_init(ctx, txq) 1262 #define iflib_netmap_rxq_init(ctx, rxq) 1263 #define iflib_netmap_detach(ifp) 1264 1265 #define iflib_netmap_attach(ctx) (0) 1266 #define netmap_rx_irq(ifp, qid, budget) (0) 1267 #define netmap_tx_irq(ifp, qid) do {} while (0) 1268 #define iflib_netmap_timer_adjust(ctx, txqid, reset_on) 1269 1270 #endif 1271 1272 #if defined(__i386__) || defined(__amd64__) 1273 static __inline void 1274 prefetch(void *x) 1275 { 1276 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1277 } 1278 static __inline void 1279 prefetch2cachelines(void *x) 1280 { 1281 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1282 #if (CACHE_LINE_SIZE < 128) 1283 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1284 #endif 1285 } 1286 #else 1287 #define prefetch(x) 1288 #define prefetch2cachelines(x) 1289 #endif 1290 1291 static void 1292 iflib_gen_mac(if_ctx_t ctx) 1293 { 1294 struct thread *td; 1295 MD5_CTX mdctx; 1296 char uuid[HOSTUUIDLEN+1]; 1297 char buf[HOSTUUIDLEN+16]; 1298 uint8_t *mac; 1299 unsigned char digest[16]; 1300 1301 td = curthread; 1302 mac = ctx->ifc_mac; 1303 uuid[HOSTUUIDLEN] = 0; 1304 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN); 1305 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev)); 1306 /* 1307 * Generate a pseudo-random, deterministic MAC 1308 * address based on the UUID and unit number. 1309 * The FreeBSD Foundation OUI of 58-9C-FC is used. 1310 */ 1311 MD5Init(&mdctx); 1312 MD5Update(&mdctx, buf, strlen(buf)); 1313 MD5Final(digest, &mdctx); 1314 1315 mac[0] = 0x58; 1316 mac[1] = 0x9C; 1317 mac[2] = 0xFC; 1318 mac[3] = digest[0]; 1319 mac[4] = digest[1]; 1320 mac[5] = digest[2]; 1321 } 1322 1323 static void 1324 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1325 { 1326 iflib_fl_t fl; 1327 1328 fl = &rxq->ifr_fl[flid]; 1329 iru->iru_paddrs = fl->ifl_bus_addrs; 1330 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1331 iru->iru_idxs = fl->ifl_rxd_idxs; 1332 iru->iru_qsidx = rxq->ifr_id; 1333 iru->iru_buf_size = fl->ifl_buf_size; 1334 iru->iru_flidx = fl->ifl_id; 1335 } 1336 1337 static void 1338 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1339 { 1340 if (err) 1341 return; 1342 *(bus_addr_t *) arg = segs[0].ds_addr; 1343 } 1344 1345 int 1346 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1347 { 1348 int err; 1349 if_shared_ctx_t sctx = ctx->ifc_sctx; 1350 device_t dev = ctx->ifc_dev; 1351 1352 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1353 1354 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1355 sctx->isc_q_align, 0, /* alignment, bounds */ 1356 BUS_SPACE_MAXADDR, /* lowaddr */ 1357 BUS_SPACE_MAXADDR, /* highaddr */ 1358 NULL, NULL, /* filter, filterarg */ 1359 size, /* maxsize */ 1360 1, /* nsegments */ 1361 size, /* maxsegsize */ 1362 BUS_DMA_ALLOCNOW, /* flags */ 1363 NULL, /* lockfunc */ 1364 NULL, /* lockarg */ 1365 &dma->idi_tag); 1366 if (err) { 1367 device_printf(dev, 1368 "%s: bus_dma_tag_create failed: %d\n", 1369 __func__, err); 1370 goto fail_0; 1371 } 1372 1373 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1374 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1375 if (err) { 1376 device_printf(dev, 1377 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1378 __func__, (uintmax_t)size, err); 1379 goto fail_1; 1380 } 1381 1382 dma->idi_paddr = IF_BAD_DMA; 1383 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1384 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1385 if (err || dma->idi_paddr == IF_BAD_DMA) { 1386 device_printf(dev, 1387 "%s: bus_dmamap_load failed: %d\n", 1388 __func__, err); 1389 goto fail_2; 1390 } 1391 1392 dma->idi_size = size; 1393 return (0); 1394 1395 fail_2: 1396 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1397 fail_1: 1398 bus_dma_tag_destroy(dma->idi_tag); 1399 fail_0: 1400 dma->idi_tag = NULL; 1401 1402 return (err); 1403 } 1404 1405 int 1406 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1407 { 1408 int i, err; 1409 iflib_dma_info_t *dmaiter; 1410 1411 dmaiter = dmalist; 1412 for (i = 0; i < count; i++, dmaiter++) { 1413 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1414 break; 1415 } 1416 if (err) 1417 iflib_dma_free_multi(dmalist, i); 1418 return (err); 1419 } 1420 1421 void 1422 iflib_dma_free(iflib_dma_info_t dma) 1423 { 1424 if (dma->idi_tag == NULL) 1425 return; 1426 if (dma->idi_paddr != IF_BAD_DMA) { 1427 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1428 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1429 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1430 dma->idi_paddr = IF_BAD_DMA; 1431 } 1432 if (dma->idi_vaddr != NULL) { 1433 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1434 dma->idi_vaddr = NULL; 1435 } 1436 bus_dma_tag_destroy(dma->idi_tag); 1437 dma->idi_tag = NULL; 1438 } 1439 1440 void 1441 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1442 { 1443 int i; 1444 iflib_dma_info_t *dmaiter = dmalist; 1445 1446 for (i = 0; i < count; i++, dmaiter++) 1447 iflib_dma_free(*dmaiter); 1448 } 1449 1450 #ifdef EARLY_AP_STARTUP 1451 static const int iflib_started = 1; 1452 #else 1453 /* 1454 * We used to abuse the smp_started flag to decide if the queues have been 1455 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1456 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1457 * is set. Run a SYSINIT() strictly after that to just set a usable 1458 * completion flag. 1459 */ 1460 1461 static int iflib_started; 1462 1463 static void 1464 iflib_record_started(void *arg) 1465 { 1466 iflib_started = 1; 1467 } 1468 1469 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1470 iflib_record_started, NULL); 1471 #endif 1472 1473 static int 1474 iflib_fast_intr(void *arg) 1475 { 1476 iflib_filter_info_t info = arg; 1477 struct grouptask *gtask = info->ifi_task; 1478 if (!iflib_started) 1479 return (FILTER_HANDLED); 1480 1481 DBG_COUNTER_INC(fast_intrs); 1482 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1483 return (FILTER_HANDLED); 1484 1485 GROUPTASK_ENQUEUE(gtask); 1486 return (FILTER_HANDLED); 1487 } 1488 1489 static int 1490 iflib_fast_intr_rxtx(void *arg) 1491 { 1492 iflib_filter_info_t info = arg; 1493 struct grouptask *gtask = info->ifi_task; 1494 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1495 if_ctx_t ctx = NULL;; 1496 int i, cidx; 1497 1498 if (!iflib_started) 1499 return (FILTER_HANDLED); 1500 1501 DBG_COUNTER_INC(fast_intrs); 1502 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1503 return (FILTER_HANDLED); 1504 1505 MPASS(rxq->ifr_ntxqirq); 1506 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1507 qidx_t txqid = rxq->ifr_txqid[i]; 1508 1509 ctx = rxq->ifr_ctx; 1510 1511 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1512 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1513 continue; 1514 } 1515 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1516 } 1517 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1518 cidx = rxq->ifr_cq_cidx; 1519 else 1520 cidx = rxq->ifr_fl[0].ifl_cidx; 1521 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1522 GROUPTASK_ENQUEUE(gtask); 1523 else 1524 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1525 return (FILTER_HANDLED); 1526 } 1527 1528 1529 static int 1530 iflib_fast_intr_ctx(void *arg) 1531 { 1532 iflib_filter_info_t info = arg; 1533 struct grouptask *gtask = info->ifi_task; 1534 1535 if (!iflib_started) 1536 return (FILTER_HANDLED); 1537 1538 DBG_COUNTER_INC(fast_intrs); 1539 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1540 return (FILTER_HANDLED); 1541 1542 GROUPTASK_ENQUEUE(gtask); 1543 return (FILTER_HANDLED); 1544 } 1545 1546 static int 1547 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1548 driver_filter_t filter, driver_intr_t handler, void *arg, 1549 const char *name) 1550 { 1551 int rc, flags; 1552 struct resource *res; 1553 void *tag = NULL; 1554 device_t dev = ctx->ifc_dev; 1555 1556 flags = RF_ACTIVE; 1557 if (ctx->ifc_flags & IFC_LEGACY) 1558 flags |= RF_SHAREABLE; 1559 MPASS(rid < 512); 1560 irq->ii_rid = rid; 1561 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1562 if (res == NULL) { 1563 device_printf(dev, 1564 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1565 return (ENOMEM); 1566 } 1567 irq->ii_res = res; 1568 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1569 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1570 filter, handler, arg, &tag); 1571 if (rc != 0) { 1572 device_printf(dev, 1573 "failed to setup interrupt for rid %d, name %s: %d\n", 1574 rid, name ? name : "unknown", rc); 1575 return (rc); 1576 } else if (name) 1577 bus_describe_intr(dev, res, tag, "%s", name); 1578 1579 irq->ii_tag = tag; 1580 return (0); 1581 } 1582 1583 1584 /********************************************************************* 1585 * 1586 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1587 * the information needed to transmit a packet on the wire. This is 1588 * called only once at attach, setup is done every reset. 1589 * 1590 **********************************************************************/ 1591 1592 static int 1593 iflib_txsd_alloc(iflib_txq_t txq) 1594 { 1595 if_ctx_t ctx = txq->ift_ctx; 1596 if_shared_ctx_t sctx = ctx->ifc_sctx; 1597 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1598 device_t dev = ctx->ifc_dev; 1599 bus_size_t tsomaxsize; 1600 int err, nsegments, ntsosegments; 1601 1602 nsegments = scctx->isc_tx_nsegments; 1603 ntsosegments = scctx->isc_tx_tso_segments_max; 1604 tsomaxsize = scctx->isc_tx_tso_size_max; 1605 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1606 tsomaxsize += sizeof(struct ether_vlan_header); 1607 MPASS(scctx->isc_ntxd[0] > 0); 1608 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1609 MPASS(nsegments > 0); 1610 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1611 MPASS(ntsosegments > 0); 1612 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1613 } 1614 1615 /* 1616 * Setup DMA descriptor areas. 1617 */ 1618 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1619 1, 0, /* alignment, bounds */ 1620 BUS_SPACE_MAXADDR, /* lowaddr */ 1621 BUS_SPACE_MAXADDR, /* highaddr */ 1622 NULL, NULL, /* filter, filterarg */ 1623 sctx->isc_tx_maxsize, /* maxsize */ 1624 nsegments, /* nsegments */ 1625 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1626 0, /* flags */ 1627 NULL, /* lockfunc */ 1628 NULL, /* lockfuncarg */ 1629 &txq->ift_desc_tag))) { 1630 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1631 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1632 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1633 goto fail; 1634 } 1635 if ((if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) & 1636 (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1637 1, 0, /* alignment, bounds */ 1638 BUS_SPACE_MAXADDR, /* lowaddr */ 1639 BUS_SPACE_MAXADDR, /* highaddr */ 1640 NULL, NULL, /* filter, filterarg */ 1641 tsomaxsize, /* maxsize */ 1642 ntsosegments, /* nsegments */ 1643 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1644 0, /* flags */ 1645 NULL, /* lockfunc */ 1646 NULL, /* lockfuncarg */ 1647 &txq->ift_tso_desc_tag))) { 1648 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1649 1650 goto fail; 1651 } 1652 if (!(txq->ift_sds.ifsd_flags = 1653 (uint8_t *) malloc(sizeof(uint8_t) * 1654 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1655 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1656 err = ENOMEM; 1657 goto fail; 1658 } 1659 if (!(txq->ift_sds.ifsd_m = 1660 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1661 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1662 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1663 err = ENOMEM; 1664 goto fail; 1665 } 1666 1667 /* Create the descriptor buffer dma maps */ 1668 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1669 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1670 return (0); 1671 1672 if (!(txq->ift_sds.ifsd_map = 1673 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1674 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1675 err = ENOMEM; 1676 goto fail; 1677 } 1678 1679 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1680 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1681 if (err != 0) { 1682 device_printf(dev, "Unable to create TX DMA map\n"); 1683 goto fail; 1684 } 1685 } 1686 #endif 1687 return (0); 1688 fail: 1689 /* We free all, it handles case where we are in the middle */ 1690 iflib_tx_structures_free(ctx); 1691 return (err); 1692 } 1693 1694 static void 1695 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1696 { 1697 bus_dmamap_t map; 1698 1699 map = NULL; 1700 if (txq->ift_sds.ifsd_map != NULL) 1701 map = txq->ift_sds.ifsd_map[i]; 1702 if (map != NULL) { 1703 bus_dmamap_unload(txq->ift_desc_tag, map); 1704 bus_dmamap_destroy(txq->ift_desc_tag, map); 1705 txq->ift_sds.ifsd_map[i] = NULL; 1706 } 1707 } 1708 1709 static void 1710 iflib_txq_destroy(iflib_txq_t txq) 1711 { 1712 if_ctx_t ctx = txq->ift_ctx; 1713 1714 for (int i = 0; i < txq->ift_size; i++) 1715 iflib_txsd_destroy(ctx, txq, i); 1716 if (txq->ift_sds.ifsd_map != NULL) { 1717 free(txq->ift_sds.ifsd_map, M_IFLIB); 1718 txq->ift_sds.ifsd_map = NULL; 1719 } 1720 if (txq->ift_sds.ifsd_m != NULL) { 1721 free(txq->ift_sds.ifsd_m, M_IFLIB); 1722 txq->ift_sds.ifsd_m = NULL; 1723 } 1724 if (txq->ift_sds.ifsd_flags != NULL) { 1725 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1726 txq->ift_sds.ifsd_flags = NULL; 1727 } 1728 if (txq->ift_desc_tag != NULL) { 1729 bus_dma_tag_destroy(txq->ift_desc_tag); 1730 txq->ift_desc_tag = NULL; 1731 } 1732 if (txq->ift_tso_desc_tag != NULL) { 1733 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1734 txq->ift_tso_desc_tag = NULL; 1735 } 1736 } 1737 1738 static void 1739 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1740 { 1741 struct mbuf **mp; 1742 1743 mp = &txq->ift_sds.ifsd_m[i]; 1744 if (*mp == NULL) 1745 return; 1746 1747 if (txq->ift_sds.ifsd_map != NULL) { 1748 bus_dmamap_sync(txq->ift_desc_tag, 1749 txq->ift_sds.ifsd_map[i], 1750 BUS_DMASYNC_POSTWRITE); 1751 bus_dmamap_unload(txq->ift_desc_tag, 1752 txq->ift_sds.ifsd_map[i]); 1753 } 1754 m_free(*mp); 1755 DBG_COUNTER_INC(tx_frees); 1756 *mp = NULL; 1757 } 1758 1759 static int 1760 iflib_txq_setup(iflib_txq_t txq) 1761 { 1762 if_ctx_t ctx = txq->ift_ctx; 1763 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1764 iflib_dma_info_t di; 1765 int i; 1766 1767 /* Set number of descriptors available */ 1768 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1769 /* XXX make configurable */ 1770 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1771 1772 /* Reset indices */ 1773 txq->ift_cidx_processed = 0; 1774 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1775 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1776 1777 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1778 bzero((void *)di->idi_vaddr, di->idi_size); 1779 1780 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1781 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1782 bus_dmamap_sync(di->idi_tag, di->idi_map, 1783 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1784 return (0); 1785 } 1786 1787 /********************************************************************* 1788 * 1789 * Allocate memory for rx_buffer structures. Since we use one 1790 * rx_buffer per received packet, the maximum number of rx_buffer's 1791 * that we'll need is equal to the number of receive descriptors 1792 * that we've allocated. 1793 * 1794 **********************************************************************/ 1795 static int 1796 iflib_rxsd_alloc(iflib_rxq_t rxq) 1797 { 1798 if_ctx_t ctx = rxq->ifr_ctx; 1799 if_shared_ctx_t sctx = ctx->ifc_sctx; 1800 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1801 device_t dev = ctx->ifc_dev; 1802 iflib_fl_t fl; 1803 int err; 1804 1805 MPASS(scctx->isc_nrxd[0] > 0); 1806 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1807 1808 fl = rxq->ifr_fl; 1809 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1810 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1811 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1812 1, 0, /* alignment, bounds */ 1813 BUS_SPACE_MAXADDR, /* lowaddr */ 1814 BUS_SPACE_MAXADDR, /* highaddr */ 1815 NULL, NULL, /* filter, filterarg */ 1816 sctx->isc_rx_maxsize, /* maxsize */ 1817 sctx->isc_rx_nsegments, /* nsegments */ 1818 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1819 0, /* flags */ 1820 NULL, /* lockfunc */ 1821 NULL, /* lockarg */ 1822 &fl->ifl_desc_tag); 1823 if (err) { 1824 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1825 __func__, err); 1826 goto fail; 1827 } 1828 if (!(fl->ifl_sds.ifsd_flags = 1829 (uint8_t *) malloc(sizeof(uint8_t) * 1830 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1831 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1832 err = ENOMEM; 1833 goto fail; 1834 } 1835 if (!(fl->ifl_sds.ifsd_m = 1836 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1837 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1838 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1839 err = ENOMEM; 1840 goto fail; 1841 } 1842 if (!(fl->ifl_sds.ifsd_cl = 1843 (caddr_t *) malloc(sizeof(caddr_t) * 1844 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1845 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1846 err = ENOMEM; 1847 goto fail; 1848 } 1849 1850 /* Create the descriptor buffer dma maps */ 1851 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1852 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1853 continue; 1854 1855 if (!(fl->ifl_sds.ifsd_map = 1856 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1857 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1858 err = ENOMEM; 1859 goto fail; 1860 } 1861 1862 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1863 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1864 if (err != 0) { 1865 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1866 goto fail; 1867 } 1868 } 1869 #endif 1870 } 1871 return (0); 1872 1873 fail: 1874 iflib_rx_structures_free(ctx); 1875 return (err); 1876 } 1877 1878 1879 /* 1880 * Internal service routines 1881 */ 1882 1883 struct rxq_refill_cb_arg { 1884 int error; 1885 bus_dma_segment_t seg; 1886 int nseg; 1887 }; 1888 1889 static void 1890 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1891 { 1892 struct rxq_refill_cb_arg *cb_arg = arg; 1893 1894 cb_arg->error = error; 1895 cb_arg->seg = segs[0]; 1896 cb_arg->nseg = nseg; 1897 } 1898 1899 1900 #ifdef ACPI_DMAR 1901 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1902 #else 1903 #define IS_DMAR(ctx) (0) 1904 #endif 1905 1906 /** 1907 * rxq_refill - refill an rxq free-buffer list 1908 * @ctx: the iflib context 1909 * @rxq: the free-list to refill 1910 * @n: the number of new buffers to allocate 1911 * 1912 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1913 * The caller must assure that @n does not exceed the queue's capacity. 1914 */ 1915 static void 1916 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1917 { 1918 struct mbuf *m; 1919 int idx, frag_idx = fl->ifl_fragidx; 1920 int pidx = fl->ifl_pidx; 1921 caddr_t cl, *sd_cl; 1922 struct mbuf **sd_m; 1923 uint8_t *sd_flags; 1924 struct if_rxd_update iru; 1925 bus_dmamap_t *sd_map; 1926 int n, i = 0; 1927 uint64_t bus_addr; 1928 int err; 1929 qidx_t credits; 1930 1931 sd_m = fl->ifl_sds.ifsd_m; 1932 sd_map = fl->ifl_sds.ifsd_map; 1933 sd_cl = fl->ifl_sds.ifsd_cl; 1934 sd_flags = fl->ifl_sds.ifsd_flags; 1935 idx = pidx; 1936 credits = fl->ifl_credits; 1937 1938 n = count; 1939 MPASS(n > 0); 1940 MPASS(credits + n <= fl->ifl_size); 1941 1942 if (pidx < fl->ifl_cidx) 1943 MPASS(pidx + n <= fl->ifl_cidx); 1944 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1945 MPASS(fl->ifl_gen == 0); 1946 if (pidx > fl->ifl_cidx) 1947 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1948 1949 DBG_COUNTER_INC(fl_refills); 1950 if (n > 8) 1951 DBG_COUNTER_INC(fl_refills_large); 1952 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1953 while (n--) { 1954 /* 1955 * We allocate an uninitialized mbuf + cluster, mbuf is 1956 * initialized after rx. 1957 * 1958 * If the cluster is still set then we know a minimum sized packet was received 1959 */ 1960 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1961 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1962 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1963 if ((cl = sd_cl[frag_idx]) == NULL) { 1964 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1965 break; 1966 #if MEMORY_LOGGING 1967 fl->ifl_cl_enqueued++; 1968 #endif 1969 } 1970 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1971 break; 1972 } 1973 #if MEMORY_LOGGING 1974 fl->ifl_m_enqueued++; 1975 #endif 1976 1977 DBG_COUNTER_INC(rx_allocs); 1978 #if defined(__i386__) || defined(__amd64__) 1979 if (!IS_DMAR(ctx)) { 1980 bus_addr = pmap_kextract((vm_offset_t)cl); 1981 } else 1982 #endif 1983 { 1984 struct rxq_refill_cb_arg cb_arg; 1985 1986 cb_arg.error = 0; 1987 MPASS(sd_map != NULL); 1988 MPASS(sd_map[frag_idx] != NULL); 1989 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1990 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1991 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 1992 BUS_DMASYNC_PREREAD); 1993 1994 if (err != 0 || cb_arg.error) { 1995 /* 1996 * !zone_pack ? 1997 */ 1998 if (fl->ifl_zone == zone_pack) 1999 uma_zfree(fl->ifl_zone, cl); 2000 m_free(m); 2001 n = 0; 2002 goto done; 2003 } 2004 bus_addr = cb_arg.seg.ds_addr; 2005 } 2006 bit_set(fl->ifl_rx_bitmap, frag_idx); 2007 sd_flags[frag_idx] |= RX_SW_DESC_INUSE; 2008 2009 MPASS(sd_m[frag_idx] == NULL); 2010 sd_cl[frag_idx] = cl; 2011 sd_m[frag_idx] = m; 2012 fl->ifl_rxd_idxs[i] = frag_idx; 2013 fl->ifl_bus_addrs[i] = bus_addr; 2014 fl->ifl_vm_addrs[i] = cl; 2015 credits++; 2016 i++; 2017 MPASS(credits <= fl->ifl_size); 2018 if (++idx == fl->ifl_size) { 2019 fl->ifl_gen = 1; 2020 idx = 0; 2021 } 2022 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2023 iru.iru_pidx = pidx; 2024 iru.iru_count = i; 2025 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2026 i = 0; 2027 pidx = idx; 2028 fl->ifl_pidx = idx; 2029 fl->ifl_credits = credits; 2030 } 2031 2032 } 2033 done: 2034 if (i) { 2035 iru.iru_pidx = pidx; 2036 iru.iru_count = i; 2037 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2038 fl->ifl_pidx = idx; 2039 fl->ifl_credits = credits; 2040 } 2041 DBG_COUNTER_INC(rxd_flush); 2042 if (fl->ifl_pidx == 0) 2043 pidx = fl->ifl_size - 1; 2044 else 2045 pidx = fl->ifl_pidx - 1; 2046 2047 if (sd_map) 2048 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2049 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2050 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2051 fl->ifl_fragidx = frag_idx; 2052 } 2053 2054 static __inline void 2055 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2056 { 2057 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2058 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2059 #ifdef INVARIANTS 2060 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2061 #endif 2062 2063 MPASS(fl->ifl_credits <= fl->ifl_size); 2064 MPASS(reclaimable == delta); 2065 2066 if (reclaimable > 0) 2067 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2068 } 2069 2070 static void 2071 iflib_fl_bufs_free(iflib_fl_t fl) 2072 { 2073 iflib_dma_info_t idi = fl->ifl_ifdi; 2074 uint32_t i; 2075 2076 for (i = 0; i < fl->ifl_size; i++) { 2077 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2078 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 2079 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2080 2081 if (*sd_flags & RX_SW_DESC_INUSE) { 2082 if (fl->ifl_sds.ifsd_map != NULL) { 2083 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 2084 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 2085 if (fl->ifl_rxq->ifr_ctx->ifc_in_detach) 2086 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 2087 } 2088 if (*sd_m != NULL) { 2089 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2090 uma_zfree(zone_mbuf, *sd_m); 2091 } 2092 if (*sd_cl != NULL) 2093 uma_zfree(fl->ifl_zone, *sd_cl); 2094 *sd_flags = 0; 2095 } else { 2096 MPASS(*sd_cl == NULL); 2097 MPASS(*sd_m == NULL); 2098 } 2099 #if MEMORY_LOGGING 2100 fl->ifl_m_dequeued++; 2101 fl->ifl_cl_dequeued++; 2102 #endif 2103 *sd_cl = NULL; 2104 *sd_m = NULL; 2105 } 2106 #ifdef INVARIANTS 2107 for (i = 0; i < fl->ifl_size; i++) { 2108 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 2109 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2110 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2111 } 2112 #endif 2113 /* 2114 * Reset free list values 2115 */ 2116 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2117 bzero(idi->idi_vaddr, idi->idi_size); 2118 } 2119 2120 /********************************************************************* 2121 * 2122 * Initialize a receive ring and its buffers. 2123 * 2124 **********************************************************************/ 2125 static int 2126 iflib_fl_setup(iflib_fl_t fl) 2127 { 2128 iflib_rxq_t rxq = fl->ifl_rxq; 2129 if_ctx_t ctx = rxq->ifr_ctx; 2130 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2131 2132 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2133 /* 2134 ** Free current RX buffer structs and their mbufs 2135 */ 2136 iflib_fl_bufs_free(fl); 2137 /* Now replenish the mbufs */ 2138 MPASS(fl->ifl_credits == 0); 2139 /* 2140 * XXX don't set the max_frame_size to larger 2141 * than the hardware can handle 2142 */ 2143 if (sctx->isc_max_frame_size <= 2048) 2144 fl->ifl_buf_size = MCLBYTES; 2145 #ifndef CONTIGMALLOC_WORKS 2146 else 2147 fl->ifl_buf_size = MJUMPAGESIZE; 2148 #else 2149 else if (sctx->isc_max_frame_size <= 4096) 2150 fl->ifl_buf_size = MJUMPAGESIZE; 2151 else if (sctx->isc_max_frame_size <= 9216) 2152 fl->ifl_buf_size = MJUM9BYTES; 2153 else 2154 fl->ifl_buf_size = MJUM16BYTES; 2155 #endif 2156 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2157 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2158 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2159 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2160 2161 2162 /* avoid pre-allocating zillions of clusters to an idle card 2163 * potentially speeding up attach 2164 */ 2165 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2166 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2167 if (min(128, fl->ifl_size) != fl->ifl_credits) 2168 return (ENOBUFS); 2169 /* 2170 * handle failure 2171 */ 2172 MPASS(rxq != NULL); 2173 MPASS(fl->ifl_ifdi != NULL); 2174 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2175 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2176 return (0); 2177 } 2178 2179 /********************************************************************* 2180 * 2181 * Free receive ring data structures 2182 * 2183 **********************************************************************/ 2184 static void 2185 iflib_rx_sds_free(iflib_rxq_t rxq) 2186 { 2187 iflib_fl_t fl; 2188 int i; 2189 2190 if (rxq->ifr_fl != NULL) { 2191 for (i = 0; i < rxq->ifr_nfl; i++) { 2192 fl = &rxq->ifr_fl[i]; 2193 if (fl->ifl_desc_tag != NULL) { 2194 bus_dma_tag_destroy(fl->ifl_desc_tag); 2195 fl->ifl_desc_tag = NULL; 2196 } 2197 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2198 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2199 /* XXX destroy maps first */ 2200 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2201 fl->ifl_sds.ifsd_m = NULL; 2202 fl->ifl_sds.ifsd_cl = NULL; 2203 fl->ifl_sds.ifsd_map = NULL; 2204 } 2205 free(rxq->ifr_fl, M_IFLIB); 2206 rxq->ifr_fl = NULL; 2207 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2208 } 2209 } 2210 2211 /* 2212 * MI independent logic 2213 * 2214 */ 2215 static void 2216 iflib_timer(void *arg) 2217 { 2218 iflib_txq_t txq = arg; 2219 if_ctx_t ctx = txq->ift_ctx; 2220 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2221 uint64_t this_tick = ticks; 2222 uint32_t reset_on = hz / 2; 2223 2224 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2225 return; 2226 /* 2227 ** Check on the state of the TX queue(s), this 2228 ** can be done without the lock because its RO 2229 ** and the HUNG state will be static if set. 2230 */ 2231 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2232 txq->ift_last_timer_tick = this_tick; 2233 IFDI_TIMER(ctx, txq->ift_id); 2234 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2235 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2236 (sctx->isc_pause_frames == 0))) 2237 goto hung; 2238 2239 if (ifmp_ring_is_stalled(txq->ift_br)) 2240 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2241 txq->ift_cleaned_prev = txq->ift_cleaned; 2242 } 2243 #ifdef DEV_NETMAP 2244 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2245 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on); 2246 #endif 2247 /* handle any laggards */ 2248 if (txq->ift_db_pending) 2249 GROUPTASK_ENQUEUE(&txq->ift_task); 2250 2251 sctx->isc_pause_frames = 0; 2252 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2253 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2254 return; 2255 hung: 2256 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2257 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2258 STATE_LOCK(ctx); 2259 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2260 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2261 iflib_admin_intr_deferred(ctx); 2262 STATE_UNLOCK(ctx); 2263 } 2264 2265 static void 2266 iflib_init_locked(if_ctx_t ctx) 2267 { 2268 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2269 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2270 if_t ifp = ctx->ifc_ifp; 2271 iflib_fl_t fl; 2272 iflib_txq_t txq; 2273 iflib_rxq_t rxq; 2274 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2275 2276 2277 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2278 IFDI_INTR_DISABLE(ctx); 2279 2280 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2281 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2282 /* Set hardware offload abilities */ 2283 if_clearhwassist(ifp); 2284 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2285 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2286 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2287 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2288 if (if_getcapenable(ifp) & IFCAP_TSO4) 2289 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2290 if (if_getcapenable(ifp) & IFCAP_TSO6) 2291 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2292 2293 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2294 CALLOUT_LOCK(txq); 2295 callout_stop(&txq->ift_timer); 2296 CALLOUT_UNLOCK(txq); 2297 iflib_netmap_txq_init(ctx, txq); 2298 } 2299 #ifdef INVARIANTS 2300 i = if_getdrvflags(ifp); 2301 #endif 2302 IFDI_INIT(ctx); 2303 MPASS(if_getdrvflags(ifp) == i); 2304 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2305 /* XXX this should really be done on a per-queue basis */ 2306 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2307 MPASS(rxq->ifr_id == i); 2308 iflib_netmap_rxq_init(ctx, rxq); 2309 continue; 2310 } 2311 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2312 if (iflib_fl_setup(fl)) { 2313 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2314 goto done; 2315 } 2316 } 2317 } 2318 done: 2319 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2320 IFDI_INTR_ENABLE(ctx); 2321 txq = ctx->ifc_txqs; 2322 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2323 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2324 txq->ift_timer.c_cpu); 2325 } 2326 2327 static int 2328 iflib_media_change(if_t ifp) 2329 { 2330 if_ctx_t ctx = if_getsoftc(ifp); 2331 int err; 2332 2333 CTX_LOCK(ctx); 2334 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2335 iflib_init_locked(ctx); 2336 CTX_UNLOCK(ctx); 2337 return (err); 2338 } 2339 2340 static void 2341 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2342 { 2343 if_ctx_t ctx = if_getsoftc(ifp); 2344 2345 CTX_LOCK(ctx); 2346 IFDI_UPDATE_ADMIN_STATUS(ctx); 2347 IFDI_MEDIA_STATUS(ctx, ifmr); 2348 CTX_UNLOCK(ctx); 2349 } 2350 2351 void 2352 iflib_stop(if_ctx_t ctx) 2353 { 2354 iflib_txq_t txq = ctx->ifc_txqs; 2355 iflib_rxq_t rxq = ctx->ifc_rxqs; 2356 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2357 iflib_dma_info_t di; 2358 iflib_fl_t fl; 2359 int i, j; 2360 2361 /* Tell the stack that the interface is no longer active */ 2362 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2363 2364 IFDI_INTR_DISABLE(ctx); 2365 DELAY(1000); 2366 IFDI_STOP(ctx); 2367 DELAY(1000); 2368 2369 iflib_debug_reset(); 2370 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2371 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2372 /* make sure all transmitters have completed before proceeding XXX */ 2373 2374 CALLOUT_LOCK(txq); 2375 callout_stop(&txq->ift_timer); 2376 CALLOUT_UNLOCK(txq); 2377 2378 /* clean any enqueued buffers */ 2379 iflib_ifmp_purge(txq); 2380 /* Free any existing tx buffers. */ 2381 for (j = 0; j < txq->ift_size; j++) { 2382 iflib_txsd_free(ctx, txq, j); 2383 } 2384 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2385 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2386 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2387 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2388 txq->ift_pullups = 0; 2389 ifmp_ring_reset_stats(txq->ift_br); 2390 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2391 bzero((void *)di->idi_vaddr, di->idi_size); 2392 } 2393 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2394 /* make sure all transmitters have completed before proceeding XXX */ 2395 2396 for (j = 0, di = rxq->ifr_ifdi; j < rxq->ifr_nfl; j++, di++) 2397 bzero((void *)di->idi_vaddr, di->idi_size); 2398 /* also resets the free lists pidx/cidx */ 2399 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2400 iflib_fl_bufs_free(fl); 2401 } 2402 } 2403 2404 static inline caddr_t 2405 calc_next_rxd(iflib_fl_t fl, int cidx) 2406 { 2407 qidx_t size; 2408 int nrxd; 2409 caddr_t start, end, cur, next; 2410 2411 nrxd = fl->ifl_size; 2412 size = fl->ifl_rxd_size; 2413 start = fl->ifl_ifdi->idi_vaddr; 2414 2415 if (__predict_false(size == 0)) 2416 return (start); 2417 cur = start + size*cidx; 2418 end = start + size*nrxd; 2419 next = CACHE_PTR_NEXT(cur); 2420 return (next < end ? next : start); 2421 } 2422 2423 static inline void 2424 prefetch_pkts(iflib_fl_t fl, int cidx) 2425 { 2426 int nextptr; 2427 int nrxd = fl->ifl_size; 2428 caddr_t next_rxd; 2429 2430 2431 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2432 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2433 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2434 next_rxd = calc_next_rxd(fl, cidx); 2435 prefetch(next_rxd); 2436 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2437 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2438 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2439 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2440 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2441 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2442 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2443 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2444 } 2445 2446 static void 2447 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2448 { 2449 int flid, cidx; 2450 bus_dmamap_t map; 2451 iflib_fl_t fl; 2452 iflib_dma_info_t di; 2453 int next; 2454 2455 map = NULL; 2456 flid = irf->irf_flid; 2457 cidx = irf->irf_idx; 2458 fl = &rxq->ifr_fl[flid]; 2459 sd->ifsd_fl = fl; 2460 sd->ifsd_cidx = cidx; 2461 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2462 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2463 fl->ifl_credits--; 2464 #if MEMORY_LOGGING 2465 fl->ifl_m_dequeued++; 2466 #endif 2467 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2468 prefetch_pkts(fl, cidx); 2469 if (fl->ifl_sds.ifsd_map != NULL) { 2470 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2471 prefetch(&fl->ifl_sds.ifsd_map[next]); 2472 map = fl->ifl_sds.ifsd_map[cidx]; 2473 di = fl->ifl_ifdi; 2474 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2475 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2476 bus_dmamap_sync(di->idi_tag, di->idi_map, 2477 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2478 2479 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2480 MPASS(fl->ifl_cidx == cidx); 2481 if (unload) 2482 bus_dmamap_unload(fl->ifl_desc_tag, map); 2483 } 2484 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2485 if (__predict_false(fl->ifl_cidx == 0)) 2486 fl->ifl_gen = 0; 2487 if (map != NULL) 2488 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2489 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2490 bit_clear(fl->ifl_rx_bitmap, cidx); 2491 } 2492 2493 static struct mbuf * 2494 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2495 { 2496 int i, padlen , flags; 2497 struct mbuf *m, *mh, *mt; 2498 caddr_t cl; 2499 2500 i = 0; 2501 mh = NULL; 2502 do { 2503 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2504 2505 MPASS(*sd->ifsd_cl != NULL); 2506 MPASS(*sd->ifsd_m != NULL); 2507 2508 /* Don't include zero-length frags */ 2509 if (ri->iri_frags[i].irf_len == 0) { 2510 /* XXX we can save the cluster here, but not the mbuf */ 2511 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2512 m_free(*sd->ifsd_m); 2513 *sd->ifsd_m = NULL; 2514 continue; 2515 } 2516 m = *sd->ifsd_m; 2517 *sd->ifsd_m = NULL; 2518 if (mh == NULL) { 2519 flags = M_PKTHDR|M_EXT; 2520 mh = mt = m; 2521 padlen = ri->iri_pad; 2522 } else { 2523 flags = M_EXT; 2524 mt->m_next = m; 2525 mt = m; 2526 /* assuming padding is only on the first fragment */ 2527 padlen = 0; 2528 } 2529 cl = *sd->ifsd_cl; 2530 *sd->ifsd_cl = NULL; 2531 2532 /* Can these two be made one ? */ 2533 m_init(m, M_NOWAIT, MT_DATA, flags); 2534 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2535 /* 2536 * These must follow m_init and m_cljset 2537 */ 2538 m->m_data += padlen; 2539 ri->iri_len -= padlen; 2540 m->m_len = ri->iri_frags[i].irf_len; 2541 } while (++i < ri->iri_nfrags); 2542 2543 return (mh); 2544 } 2545 2546 /* 2547 * Process one software descriptor 2548 */ 2549 static struct mbuf * 2550 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2551 { 2552 struct if_rxsd sd; 2553 struct mbuf *m; 2554 2555 /* should I merge this back in now that the two paths are basically duplicated? */ 2556 if (ri->iri_nfrags == 1 && 2557 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2558 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2559 m = *sd.ifsd_m; 2560 *sd.ifsd_m = NULL; 2561 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2562 #ifndef __NO_STRICT_ALIGNMENT 2563 if (!IP_ALIGNED(m)) 2564 m->m_data += 2; 2565 #endif 2566 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2567 m->m_len = ri->iri_frags[0].irf_len; 2568 } else { 2569 m = assemble_segments(rxq, ri, &sd); 2570 } 2571 m->m_pkthdr.len = ri->iri_len; 2572 m->m_pkthdr.rcvif = ri->iri_ifp; 2573 m->m_flags |= ri->iri_flags; 2574 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2575 m->m_pkthdr.flowid = ri->iri_flowid; 2576 M_HASHTYPE_SET(m, ri->iri_rsstype); 2577 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2578 m->m_pkthdr.csum_data = ri->iri_csum_data; 2579 return (m); 2580 } 2581 2582 #if defined(INET6) || defined(INET) 2583 static void 2584 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2585 { 2586 CURVNET_SET(lc->ifp->if_vnet); 2587 #if defined(INET6) 2588 *v6 = VNET(ip6_forwarding); 2589 #endif 2590 #if defined(INET) 2591 *v4 = VNET(ipforwarding); 2592 #endif 2593 CURVNET_RESTORE(); 2594 } 2595 2596 /* 2597 * Returns true if it's possible this packet could be LROed. 2598 * if it returns false, it is guaranteed that tcp_lro_rx() 2599 * would not return zero. 2600 */ 2601 static bool 2602 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2603 { 2604 struct ether_header *eh; 2605 uint16_t eh_type; 2606 2607 eh = mtod(m, struct ether_header *); 2608 eh_type = ntohs(eh->ether_type); 2609 switch (eh_type) { 2610 #if defined(INET6) 2611 case ETHERTYPE_IPV6: 2612 return !v6_forwarding; 2613 #endif 2614 #if defined (INET) 2615 case ETHERTYPE_IP: 2616 return !v4_forwarding; 2617 #endif 2618 } 2619 2620 return false; 2621 } 2622 #else 2623 static void 2624 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2625 { 2626 } 2627 #endif 2628 2629 static bool 2630 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2631 { 2632 if_ctx_t ctx = rxq->ifr_ctx; 2633 if_shared_ctx_t sctx = ctx->ifc_sctx; 2634 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2635 int avail, i; 2636 qidx_t *cidxp; 2637 struct if_rxd_info ri; 2638 int err, budget_left, rx_bytes, rx_pkts; 2639 iflib_fl_t fl; 2640 struct ifnet *ifp; 2641 int lro_enabled; 2642 bool v4_forwarding, v6_forwarding, lro_possible; 2643 2644 /* 2645 * XXX early demux data packets so that if_input processing only handles 2646 * acks in interrupt context 2647 */ 2648 struct mbuf *m, *mh, *mt, *mf; 2649 2650 lro_possible = v4_forwarding = v6_forwarding = false; 2651 ifp = ctx->ifc_ifp; 2652 mh = mt = NULL; 2653 MPASS(budget > 0); 2654 rx_pkts = rx_bytes = 0; 2655 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2656 cidxp = &rxq->ifr_cq_cidx; 2657 else 2658 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2659 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2660 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2661 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2662 DBG_COUNTER_INC(rx_unavail); 2663 return (false); 2664 } 2665 2666 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2667 if (__predict_false(!CTX_ACTIVE(ctx))) { 2668 DBG_COUNTER_INC(rx_ctx_inactive); 2669 break; 2670 } 2671 /* 2672 * Reset client set fields to their default values 2673 */ 2674 rxd_info_zero(&ri); 2675 ri.iri_qsidx = rxq->ifr_id; 2676 ri.iri_cidx = *cidxp; 2677 ri.iri_ifp = ifp; 2678 ri.iri_frags = rxq->ifr_frags; 2679 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2680 2681 if (err) 2682 goto err; 2683 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2684 *cidxp = ri.iri_cidx; 2685 /* Update our consumer index */ 2686 /* XXX NB: shurd - check if this is still safe */ 2687 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2688 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2689 rxq->ifr_cq_gen = 0; 2690 } 2691 /* was this only a completion queue message? */ 2692 if (__predict_false(ri.iri_nfrags == 0)) 2693 continue; 2694 } 2695 MPASS(ri.iri_nfrags != 0); 2696 MPASS(ri.iri_len != 0); 2697 2698 /* will advance the cidx on the corresponding free lists */ 2699 m = iflib_rxd_pkt_get(rxq, &ri); 2700 avail--; 2701 budget_left--; 2702 if (avail == 0 && budget_left) 2703 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2704 2705 if (__predict_false(m == NULL)) { 2706 DBG_COUNTER_INC(rx_mbuf_null); 2707 continue; 2708 } 2709 /* imm_pkt: -- cxgb */ 2710 if (mh == NULL) 2711 mh = mt = m; 2712 else { 2713 mt->m_nextpkt = m; 2714 mt = m; 2715 } 2716 } 2717 /* make sure that we can refill faster than drain */ 2718 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2719 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2720 2721 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2722 if (lro_enabled) 2723 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2724 mt = mf = NULL; 2725 while (mh != NULL) { 2726 m = mh; 2727 mh = mh->m_nextpkt; 2728 m->m_nextpkt = NULL; 2729 #ifndef __NO_STRICT_ALIGNMENT 2730 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2731 continue; 2732 #endif 2733 rx_bytes += m->m_pkthdr.len; 2734 rx_pkts++; 2735 #if defined(INET6) || defined(INET) 2736 if (lro_enabled) { 2737 if (!lro_possible) { 2738 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2739 if (lro_possible && mf != NULL) { 2740 ifp->if_input(ifp, mf); 2741 DBG_COUNTER_INC(rx_if_input); 2742 mt = mf = NULL; 2743 } 2744 } 2745 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2746 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2747 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2748 continue; 2749 } 2750 } 2751 #endif 2752 if (lro_possible) { 2753 ifp->if_input(ifp, m); 2754 DBG_COUNTER_INC(rx_if_input); 2755 continue; 2756 } 2757 2758 if (mf == NULL) 2759 mf = m; 2760 if (mt != NULL) 2761 mt->m_nextpkt = m; 2762 mt = m; 2763 } 2764 if (mf != NULL) { 2765 ifp->if_input(ifp, mf); 2766 DBG_COUNTER_INC(rx_if_input); 2767 } 2768 2769 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2770 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2771 2772 /* 2773 * Flush any outstanding LRO work 2774 */ 2775 #if defined(INET6) || defined(INET) 2776 tcp_lro_flush_all(&rxq->ifr_lc); 2777 #endif 2778 if (avail) 2779 return true; 2780 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2781 err: 2782 STATE_LOCK(ctx); 2783 ctx->ifc_flags |= IFC_DO_RESET; 2784 iflib_admin_intr_deferred(ctx); 2785 STATE_UNLOCK(ctx); 2786 return (false); 2787 } 2788 2789 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2790 static inline qidx_t 2791 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2792 { 2793 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2794 qidx_t minthresh = txq->ift_size / 8; 2795 if (in_use > 4*minthresh) 2796 return (notify_count); 2797 if (in_use > 2*minthresh) 2798 return (notify_count >> 1); 2799 if (in_use > minthresh) 2800 return (notify_count >> 3); 2801 return (0); 2802 } 2803 2804 static inline qidx_t 2805 txq_max_rs_deferred(iflib_txq_t txq) 2806 { 2807 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2808 qidx_t minthresh = txq->ift_size / 8; 2809 if (txq->ift_in_use > 4*minthresh) 2810 return (notify_count); 2811 if (txq->ift_in_use > 2*minthresh) 2812 return (notify_count >> 1); 2813 if (txq->ift_in_use > minthresh) 2814 return (notify_count >> 2); 2815 return (2); 2816 } 2817 2818 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2819 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2820 2821 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2822 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2823 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2824 2825 /* forward compatibility for cxgb */ 2826 #define FIRST_QSET(ctx) 0 2827 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2828 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2829 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2830 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2831 2832 /* XXX we should be setting this to something other than zero */ 2833 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2834 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2835 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2836 2837 static inline bool 2838 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2839 { 2840 qidx_t dbval, max; 2841 bool rang; 2842 2843 rang = false; 2844 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2845 if (ring || txq->ift_db_pending >= max) { 2846 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2847 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2848 txq->ift_db_pending = txq->ift_npending = 0; 2849 rang = true; 2850 } 2851 return (rang); 2852 } 2853 2854 #ifdef PKT_DEBUG 2855 static void 2856 print_pkt(if_pkt_info_t pi) 2857 { 2858 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2859 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2860 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2861 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2862 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2863 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2864 } 2865 #endif 2866 2867 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2868 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2869 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2870 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2871 2872 static int 2873 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2874 { 2875 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2876 struct ether_vlan_header *eh; 2877 struct mbuf *m; 2878 2879 m = *mp; 2880 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2881 M_WRITABLE(m) == 0) { 2882 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2883 return (ENOMEM); 2884 } else { 2885 m_freem(*mp); 2886 *mp = m; 2887 } 2888 } 2889 2890 /* 2891 * Determine where frame payload starts. 2892 * Jump over vlan headers if already present, 2893 * helpful for QinQ too. 2894 */ 2895 if (__predict_false(m->m_len < sizeof(*eh))) { 2896 txq->ift_pullups++; 2897 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2898 return (ENOMEM); 2899 } 2900 eh = mtod(m, struct ether_vlan_header *); 2901 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2902 pi->ipi_etype = ntohs(eh->evl_proto); 2903 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2904 } else { 2905 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2906 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2907 } 2908 2909 switch (pi->ipi_etype) { 2910 #ifdef INET 2911 case ETHERTYPE_IP: 2912 { 2913 struct mbuf *n; 2914 struct ip *ip = NULL; 2915 struct tcphdr *th = NULL; 2916 int minthlen; 2917 2918 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2919 if (__predict_false(m->m_len < minthlen)) { 2920 /* 2921 * if this code bloat is causing too much of a hit 2922 * move it to a separate function and mark it noinline 2923 */ 2924 if (m->m_len == pi->ipi_ehdrlen) { 2925 n = m->m_next; 2926 MPASS(n); 2927 if (n->m_len >= sizeof(*ip)) { 2928 ip = (struct ip *)n->m_data; 2929 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2930 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2931 } else { 2932 txq->ift_pullups++; 2933 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2934 return (ENOMEM); 2935 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2936 } 2937 } else { 2938 txq->ift_pullups++; 2939 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2940 return (ENOMEM); 2941 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2942 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2943 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2944 } 2945 } else { 2946 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2947 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2948 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2949 } 2950 pi->ipi_ip_hlen = ip->ip_hl << 2; 2951 pi->ipi_ipproto = ip->ip_p; 2952 pi->ipi_flags |= IPI_TX_IPV4; 2953 2954 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 2955 ip->ip_sum = 0; 2956 2957 /* TCP checksum offload may require TCP header length */ 2958 if (IS_TX_OFFLOAD4(pi)) { 2959 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 2960 if (__predict_false(th == NULL)) { 2961 txq->ift_pullups++; 2962 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2963 return (ENOMEM); 2964 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2965 } 2966 pi->ipi_tcp_hflags = th->th_flags; 2967 pi->ipi_tcp_hlen = th->th_off << 2; 2968 pi->ipi_tcp_seq = th->th_seq; 2969 } 2970 if (IS_TSO4(pi)) { 2971 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2972 return (ENXIO); 2973 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2974 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2975 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2976 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2977 ip->ip_sum = 0; 2978 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2979 } 2980 } 2981 } 2982 break; 2983 } 2984 #endif 2985 #ifdef INET6 2986 case ETHERTYPE_IPV6: 2987 { 2988 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2989 struct tcphdr *th; 2990 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2991 2992 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2993 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2994 return (ENOMEM); 2995 } 2996 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2997 2998 /* XXX-BZ this will go badly in case of ext hdrs. */ 2999 pi->ipi_ipproto = ip6->ip6_nxt; 3000 pi->ipi_flags |= IPI_TX_IPV6; 3001 3002 /* TCP checksum offload may require TCP header length */ 3003 if (IS_TX_OFFLOAD6(pi)) { 3004 if (pi->ipi_ipproto == IPPROTO_TCP) { 3005 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3006 txq->ift_pullups++; 3007 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3008 return (ENOMEM); 3009 } 3010 pi->ipi_tcp_hflags = th->th_flags; 3011 pi->ipi_tcp_hlen = th->th_off << 2; 3012 pi->ipi_tcp_seq = th->th_seq; 3013 } 3014 if (IS_TSO6(pi)) { 3015 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3016 return (ENXIO); 3017 /* 3018 * The corresponding flag is set by the stack in the IPv4 3019 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 3020 * So, set it here because the rest of the flow requires it. 3021 */ 3022 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3023 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3024 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3025 } 3026 } 3027 break; 3028 } 3029 #endif 3030 default: 3031 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3032 pi->ipi_ip_hlen = 0; 3033 break; 3034 } 3035 *mp = m; 3036 3037 return (0); 3038 } 3039 3040 static __noinline struct mbuf * 3041 collapse_pkthdr(struct mbuf *m0) 3042 { 3043 struct mbuf *m, *m_next, *tmp; 3044 3045 m = m0; 3046 m_next = m->m_next; 3047 while (m_next != NULL && m_next->m_len == 0) { 3048 m = m_next; 3049 m->m_next = NULL; 3050 m_free(m); 3051 m_next = m_next->m_next; 3052 } 3053 m = m0; 3054 m->m_next = m_next; 3055 if (m_next == NULL) 3056 return (m); 3057 if ((m_next->m_flags & M_EXT) == 0) { 3058 m = m_defrag(m, M_NOWAIT); 3059 } else { 3060 tmp = m_next->m_next; 3061 memcpy(m_next, m, MPKTHSIZE); 3062 m = m_next; 3063 m->m_next = tmp; 3064 } 3065 return (m); 3066 } 3067 3068 /* 3069 * If dodgy hardware rejects the scatter gather chain we've handed it 3070 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3071 * m_defrag'd mbufs 3072 */ 3073 static __noinline struct mbuf * 3074 iflib_remove_mbuf(iflib_txq_t txq) 3075 { 3076 int ntxd, i, pidx; 3077 struct mbuf *m, *mh, **ifsd_m; 3078 3079 pidx = txq->ift_pidx; 3080 ifsd_m = txq->ift_sds.ifsd_m; 3081 ntxd = txq->ift_size; 3082 mh = m = ifsd_m[pidx]; 3083 ifsd_m[pidx] = NULL; 3084 #if MEMORY_LOGGING 3085 txq->ift_dequeued++; 3086 #endif 3087 i = 1; 3088 3089 while (m) { 3090 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 3091 #if MEMORY_LOGGING 3092 txq->ift_dequeued++; 3093 #endif 3094 m = m->m_next; 3095 i++; 3096 } 3097 return (mh); 3098 } 3099 3100 static int 3101 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 3102 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 3103 int max_segs, int flags) 3104 { 3105 if_ctx_t ctx; 3106 if_shared_ctx_t sctx; 3107 if_softc_ctx_t scctx; 3108 int i, next, pidx, err, ntxd, count; 3109 struct mbuf *m, *tmp, **ifsd_m; 3110 3111 m = *m0; 3112 3113 /* 3114 * Please don't ever do this 3115 */ 3116 if (__predict_false(m->m_len == 0)) 3117 *m0 = collapse_pkthdr(m); 3118 3119 ctx = txq->ift_ctx; 3120 sctx = ctx->ifc_sctx; 3121 scctx = &ctx->ifc_softc_ctx; 3122 ifsd_m = txq->ift_sds.ifsd_m; 3123 ntxd = txq->ift_size; 3124 pidx = txq->ift_pidx; 3125 if (map != NULL) { 3126 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 3127 3128 err = bus_dmamap_load_mbuf_sg(tag, map, 3129 *m0, segs, nsegs, BUS_DMA_NOWAIT); 3130 if (err) 3131 return (err); 3132 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 3133 count = 0; 3134 m = *m0; 3135 do { 3136 if (__predict_false(m->m_len <= 0)) { 3137 tmp = m; 3138 m = m->m_next; 3139 tmp->m_next = NULL; 3140 m_free(tmp); 3141 continue; 3142 } 3143 m = m->m_next; 3144 count++; 3145 } while (m != NULL); 3146 if (count > *nsegs) { 3147 ifsd_m[pidx] = *m0; 3148 ifsd_m[pidx]->m_flags |= M_TOOBIG; 3149 return (0); 3150 } 3151 m = *m0; 3152 count = 0; 3153 do { 3154 next = (pidx + count) & (ntxd-1); 3155 MPASS(ifsd_m[next] == NULL); 3156 ifsd_m[next] = m; 3157 count++; 3158 tmp = m; 3159 m = m->m_next; 3160 } while (m != NULL); 3161 } else { 3162 int buflen, sgsize, maxsegsz, max_sgsize; 3163 vm_offset_t vaddr; 3164 vm_paddr_t curaddr; 3165 3166 count = i = 0; 3167 m = *m0; 3168 if (m->m_pkthdr.csum_flags & CSUM_TSO) 3169 maxsegsz = scctx->isc_tx_tso_segsize_max; 3170 else 3171 maxsegsz = sctx->isc_tx_maxsegsize; 3172 3173 do { 3174 if (__predict_false(m->m_len <= 0)) { 3175 tmp = m; 3176 m = m->m_next; 3177 tmp->m_next = NULL; 3178 m_free(tmp); 3179 continue; 3180 } 3181 buflen = m->m_len; 3182 vaddr = (vm_offset_t)m->m_data; 3183 /* 3184 * see if we can't be smarter about physically 3185 * contiguous mappings 3186 */ 3187 next = (pidx + count) & (ntxd-1); 3188 MPASS(ifsd_m[next] == NULL); 3189 #if MEMORY_LOGGING 3190 txq->ift_enqueued++; 3191 #endif 3192 ifsd_m[next] = m; 3193 while (buflen > 0) { 3194 if (i >= max_segs) 3195 goto err; 3196 max_sgsize = MIN(buflen, maxsegsz); 3197 curaddr = pmap_kextract(vaddr); 3198 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 3199 sgsize = MIN(sgsize, max_sgsize); 3200 segs[i].ds_addr = curaddr; 3201 segs[i].ds_len = sgsize; 3202 vaddr += sgsize; 3203 buflen -= sgsize; 3204 i++; 3205 } 3206 count++; 3207 tmp = m; 3208 m = m->m_next; 3209 } while (m != NULL); 3210 *nsegs = i; 3211 } 3212 return (0); 3213 err: 3214 *m0 = iflib_remove_mbuf(txq); 3215 return (EFBIG); 3216 } 3217 3218 static inline caddr_t 3219 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3220 { 3221 qidx_t size; 3222 int ntxd; 3223 caddr_t start, end, cur, next; 3224 3225 ntxd = txq->ift_size; 3226 size = txq->ift_txd_size[qid]; 3227 start = txq->ift_ifdi[qid].idi_vaddr; 3228 3229 if (__predict_false(size == 0)) 3230 return (start); 3231 cur = start + size*cidx; 3232 end = start + size*ntxd; 3233 next = CACHE_PTR_NEXT(cur); 3234 return (next < end ? next : start); 3235 } 3236 3237 /* 3238 * Pad an mbuf to ensure a minimum ethernet frame size. 3239 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3240 */ 3241 static __noinline int 3242 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3243 { 3244 /* 3245 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3246 * and ARP message is the smallest common payload I can think of 3247 */ 3248 static char pad[18]; /* just zeros */ 3249 int n; 3250 struct mbuf *new_head; 3251 3252 if (!M_WRITABLE(*m_head)) { 3253 new_head = m_dup(*m_head, M_NOWAIT); 3254 if (new_head == NULL) { 3255 m_freem(*m_head); 3256 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3257 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3258 return ENOMEM; 3259 } 3260 m_freem(*m_head); 3261 *m_head = new_head; 3262 } 3263 3264 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3265 n > 0; n -= sizeof(pad)) 3266 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3267 break; 3268 3269 if (n > 0) { 3270 m_freem(*m_head); 3271 device_printf(dev, "cannot pad short frame\n"); 3272 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3273 return (ENOBUFS); 3274 } 3275 3276 return 0; 3277 } 3278 3279 static int 3280 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3281 { 3282 if_ctx_t ctx; 3283 if_shared_ctx_t sctx; 3284 if_softc_ctx_t scctx; 3285 bus_dma_segment_t *segs; 3286 struct mbuf *m_head; 3287 void *next_txd; 3288 bus_dmamap_t map; 3289 struct if_pkt_info pi; 3290 int remap = 0; 3291 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3292 bus_dma_tag_t desc_tag; 3293 3294 ctx = txq->ift_ctx; 3295 sctx = ctx->ifc_sctx; 3296 scctx = &ctx->ifc_softc_ctx; 3297 segs = txq->ift_segs; 3298 ntxd = txq->ift_size; 3299 m_head = *m_headp; 3300 map = NULL; 3301 3302 /* 3303 * If we're doing TSO the next descriptor to clean may be quite far ahead 3304 */ 3305 cidx = txq->ift_cidx; 3306 pidx = txq->ift_pidx; 3307 if (ctx->ifc_flags & IFC_PREFETCH) { 3308 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3309 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3310 next_txd = calc_next_txd(txq, cidx, 0); 3311 prefetch(next_txd); 3312 } 3313 3314 /* prefetch the next cache line of mbuf pointers and flags */ 3315 prefetch(&txq->ift_sds.ifsd_m[next]); 3316 if (txq->ift_sds.ifsd_map != NULL) { 3317 prefetch(&txq->ift_sds.ifsd_map[next]); 3318 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3319 prefetch(&txq->ift_sds.ifsd_flags[next]); 3320 } 3321 } else if (txq->ift_sds.ifsd_map != NULL) 3322 map = txq->ift_sds.ifsd_map[pidx]; 3323 3324 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3325 desc_tag = txq->ift_tso_desc_tag; 3326 max_segs = scctx->isc_tx_tso_segments_max; 3327 MPASS(desc_tag != NULL); 3328 MPASS(max_segs > 0); 3329 } else { 3330 desc_tag = txq->ift_desc_tag; 3331 max_segs = scctx->isc_tx_nsegments; 3332 } 3333 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3334 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3335 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3336 if (err) 3337 return err; 3338 } 3339 m_head = *m_headp; 3340 3341 pkt_info_zero(&pi); 3342 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3343 pi.ipi_pidx = pidx; 3344 pi.ipi_qsidx = txq->ift_id; 3345 pi.ipi_len = m_head->m_pkthdr.len; 3346 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3347 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3348 3349 /* deliberate bitwise OR to make one condition */ 3350 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3351 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3352 return (err); 3353 m_head = *m_headp; 3354 } 3355 3356 retry: 3357 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3358 defrag: 3359 if (__predict_false(err)) { 3360 switch (err) { 3361 case EFBIG: 3362 /* try collapse once and defrag once */ 3363 if (remap == 0) { 3364 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3365 /* try defrag if collapsing fails */ 3366 if (m_head == NULL) 3367 remap++; 3368 } 3369 if (remap == 1) 3370 m_head = m_defrag(*m_headp, M_NOWAIT); 3371 remap++; 3372 if (__predict_false(m_head == NULL)) 3373 goto defrag_failed; 3374 txq->ift_mbuf_defrag++; 3375 *m_headp = m_head; 3376 goto retry; 3377 break; 3378 case ENOMEM: 3379 txq->ift_no_tx_dma_setup++; 3380 break; 3381 default: 3382 txq->ift_no_tx_dma_setup++; 3383 m_freem(*m_headp); 3384 DBG_COUNTER_INC(tx_frees); 3385 *m_headp = NULL; 3386 break; 3387 } 3388 txq->ift_map_failed++; 3389 DBG_COUNTER_INC(encap_load_mbuf_fail); 3390 return (err); 3391 } 3392 3393 /* 3394 * XXX assumes a 1 to 1 relationship between segments and 3395 * descriptors - this does not hold true on all drivers, e.g. 3396 * cxgb 3397 */ 3398 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3399 txq->ift_no_desc_avail++; 3400 if (map != NULL) 3401 bus_dmamap_unload(desc_tag, map); 3402 DBG_COUNTER_INC(encap_txq_avail_fail); 3403 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3404 GROUPTASK_ENQUEUE(&txq->ift_task); 3405 return (ENOBUFS); 3406 } 3407 /* 3408 * On Intel cards we can greatly reduce the number of TX interrupts 3409 * we see by only setting report status on every Nth descriptor. 3410 * However, this also means that the driver will need to keep track 3411 * of the descriptors that RS was set on to check them for the DD bit. 3412 */ 3413 txq->ift_rs_pending += nsegs + 1; 3414 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3415 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3416 pi.ipi_flags |= IPI_TX_INTR; 3417 txq->ift_rs_pending = 0; 3418 } 3419 3420 pi.ipi_segs = segs; 3421 pi.ipi_nsegs = nsegs; 3422 3423 MPASS(pidx >= 0 && pidx < txq->ift_size); 3424 #ifdef PKT_DEBUG 3425 print_pkt(&pi); 3426 #endif 3427 if (map != NULL) 3428 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3429 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3430 if (map != NULL) 3431 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3432 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3433 DBG_COUNTER_INC(tx_encap); 3434 MPASS(pi.ipi_new_pidx < txq->ift_size); 3435 3436 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3437 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3438 ndesc += txq->ift_size; 3439 txq->ift_gen = 1; 3440 } 3441 /* 3442 * drivers can need as many as 3443 * two sentinels 3444 */ 3445 MPASS(ndesc <= pi.ipi_nsegs + 2); 3446 MPASS(pi.ipi_new_pidx != pidx); 3447 MPASS(ndesc > 0); 3448 txq->ift_in_use += ndesc; 3449 3450 /* 3451 * We update the last software descriptor again here because there may 3452 * be a sentinel and/or there may be more mbufs than segments 3453 */ 3454 txq->ift_pidx = pi.ipi_new_pidx; 3455 txq->ift_npending += pi.ipi_ndescs; 3456 } else { 3457 *m_headp = m_head = iflib_remove_mbuf(txq); 3458 if (err == EFBIG) { 3459 txq->ift_txd_encap_efbig++; 3460 if (remap < 2) { 3461 remap = 1; 3462 goto defrag; 3463 } 3464 } 3465 DBG_COUNTER_INC(encap_txd_encap_fail); 3466 goto defrag_failed; 3467 } 3468 return (err); 3469 3470 defrag_failed: 3471 txq->ift_mbuf_defrag_failed++; 3472 txq->ift_map_failed++; 3473 m_freem(*m_headp); 3474 DBG_COUNTER_INC(tx_frees); 3475 *m_headp = NULL; 3476 return (ENOMEM); 3477 } 3478 3479 static void 3480 iflib_tx_desc_free(iflib_txq_t txq, int n) 3481 { 3482 int hasmap; 3483 uint32_t qsize, cidx, mask, gen; 3484 struct mbuf *m, **ifsd_m; 3485 uint8_t *ifsd_flags; 3486 bus_dmamap_t *ifsd_map; 3487 bool do_prefetch; 3488 3489 cidx = txq->ift_cidx; 3490 gen = txq->ift_gen; 3491 qsize = txq->ift_size; 3492 mask = qsize-1; 3493 hasmap = txq->ift_sds.ifsd_map != NULL; 3494 ifsd_flags = txq->ift_sds.ifsd_flags; 3495 ifsd_m = txq->ift_sds.ifsd_m; 3496 ifsd_map = txq->ift_sds.ifsd_map; 3497 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3498 3499 while (n-- > 0) { 3500 if (do_prefetch) { 3501 prefetch(ifsd_m[(cidx + 3) & mask]); 3502 prefetch(ifsd_m[(cidx + 4) & mask]); 3503 } 3504 if (ifsd_m[cidx] != NULL) { 3505 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3506 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3507 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3508 /* 3509 * does it matter if it's not the TSO tag? If so we'll 3510 * have to add the type to flags 3511 */ 3512 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3513 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3514 } 3515 if ((m = ifsd_m[cidx]) != NULL) { 3516 /* XXX we don't support any drivers that batch packets yet */ 3517 MPASS(m->m_nextpkt == NULL); 3518 /* if the number of clusters exceeds the number of segments 3519 * there won't be space on the ring to save a pointer to each 3520 * cluster so we simply free the list here 3521 */ 3522 if (m->m_flags & M_TOOBIG) { 3523 m_freem(m); 3524 } else { 3525 m_free(m); 3526 } 3527 ifsd_m[cidx] = NULL; 3528 #if MEMORY_LOGGING 3529 txq->ift_dequeued++; 3530 #endif 3531 DBG_COUNTER_INC(tx_frees); 3532 } 3533 } 3534 if (__predict_false(++cidx == qsize)) { 3535 cidx = 0; 3536 gen = 0; 3537 } 3538 } 3539 txq->ift_cidx = cidx; 3540 txq->ift_gen = gen; 3541 } 3542 3543 static __inline int 3544 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3545 { 3546 int reclaim; 3547 if_ctx_t ctx = txq->ift_ctx; 3548 3549 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3550 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3551 3552 /* 3553 * Need a rate-limiting check so that this isn't called every time 3554 */ 3555 iflib_tx_credits_update(ctx, txq); 3556 reclaim = DESC_RECLAIMABLE(txq); 3557 3558 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3559 #ifdef INVARIANTS 3560 if (iflib_verbose_debug) { 3561 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3562 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3563 reclaim, thresh); 3564 3565 } 3566 #endif 3567 return (0); 3568 } 3569 iflib_tx_desc_free(txq, reclaim); 3570 txq->ift_cleaned += reclaim; 3571 txq->ift_in_use -= reclaim; 3572 3573 return (reclaim); 3574 } 3575 3576 static struct mbuf ** 3577 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3578 { 3579 int next, size; 3580 struct mbuf **items; 3581 3582 size = r->size; 3583 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3584 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3585 3586 prefetch(items[(cidx + offset) & (size-1)]); 3587 if (remaining > 1) { 3588 prefetch2cachelines(&items[next]); 3589 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3590 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3591 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3592 } 3593 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3594 } 3595 3596 static void 3597 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3598 { 3599 3600 ifmp_ring_check_drainage(txq->ift_br, budget); 3601 } 3602 3603 static uint32_t 3604 iflib_txq_can_drain(struct ifmp_ring *r) 3605 { 3606 iflib_txq_t txq = r->cookie; 3607 if_ctx_t ctx = txq->ift_ctx; 3608 3609 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3610 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3611 } 3612 3613 static uint32_t 3614 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3615 { 3616 iflib_txq_t txq = r->cookie; 3617 if_ctx_t ctx = txq->ift_ctx; 3618 struct ifnet *ifp = ctx->ifc_ifp; 3619 struct mbuf **mp, *m; 3620 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3621 int reclaimed, err, in_use_prev, desc_used; 3622 bool do_prefetch, ring, rang; 3623 3624 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3625 !LINK_ACTIVE(ctx))) { 3626 DBG_COUNTER_INC(txq_drain_notready); 3627 return (0); 3628 } 3629 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3630 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3631 avail = IDXDIFF(pidx, cidx, r->size); 3632 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3633 DBG_COUNTER_INC(txq_drain_flushing); 3634 for (i = 0; i < avail; i++) { 3635 m_free(r->items[(cidx + i) & (r->size-1)]); 3636 r->items[(cidx + i) & (r->size-1)] = NULL; 3637 } 3638 return (avail); 3639 } 3640 3641 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3642 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3643 CALLOUT_LOCK(txq); 3644 callout_stop(&txq->ift_timer); 3645 CALLOUT_UNLOCK(txq); 3646 DBG_COUNTER_INC(txq_drain_oactive); 3647 return (0); 3648 } 3649 if (reclaimed) 3650 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3651 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3652 count = MIN(avail, TX_BATCH_SIZE); 3653 #ifdef INVARIANTS 3654 if (iflib_verbose_debug) 3655 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3656 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3657 #endif 3658 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3659 avail = TXQ_AVAIL(txq); 3660 err = 0; 3661 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3662 int rem = do_prefetch ? count - i : 0; 3663 3664 mp = _ring_peek_one(r, cidx, i, rem); 3665 MPASS(mp != NULL && *mp != NULL); 3666 if (__predict_false(*mp == (struct mbuf *)txq)) { 3667 consumed++; 3668 reclaimed++; 3669 continue; 3670 } 3671 in_use_prev = txq->ift_in_use; 3672 err = iflib_encap(txq, mp); 3673 if (__predict_false(err)) { 3674 DBG_COUNTER_INC(txq_drain_encapfail); 3675 /* no room - bail out */ 3676 if (err == ENOBUFS) 3677 break; 3678 consumed++; 3679 DBG_COUNTER_INC(txq_drain_encapfail); 3680 /* we can't send this packet - skip it */ 3681 continue; 3682 } 3683 consumed++; 3684 pkt_sent++; 3685 m = *mp; 3686 DBG_COUNTER_INC(tx_sent); 3687 bytes_sent += m->m_pkthdr.len; 3688 mcast_sent += !!(m->m_flags & M_MCAST); 3689 avail = TXQ_AVAIL(txq); 3690 3691 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3692 desc_used += (txq->ift_in_use - in_use_prev); 3693 ETHER_BPF_MTAP(ifp, m); 3694 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3695 break; 3696 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3697 } 3698 3699 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3700 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3701 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3702 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3703 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3704 if (mcast_sent) 3705 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3706 #ifdef INVARIANTS 3707 if (iflib_verbose_debug) 3708 printf("consumed=%d\n", consumed); 3709 #endif 3710 return (consumed); 3711 } 3712 3713 static uint32_t 3714 iflib_txq_drain_always(struct ifmp_ring *r) 3715 { 3716 return (1); 3717 } 3718 3719 static uint32_t 3720 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3721 { 3722 int i, avail; 3723 struct mbuf **mp; 3724 iflib_txq_t txq; 3725 3726 txq = r->cookie; 3727 3728 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3729 CALLOUT_LOCK(txq); 3730 callout_stop(&txq->ift_timer); 3731 CALLOUT_UNLOCK(txq); 3732 3733 avail = IDXDIFF(pidx, cidx, r->size); 3734 for (i = 0; i < avail; i++) { 3735 mp = _ring_peek_one(r, cidx, i, avail - i); 3736 if (__predict_false(*mp == (struct mbuf *)txq)) 3737 continue; 3738 m_freem(*mp); 3739 } 3740 MPASS(ifmp_ring_is_stalled(r) == 0); 3741 return (avail); 3742 } 3743 3744 static void 3745 iflib_ifmp_purge(iflib_txq_t txq) 3746 { 3747 struct ifmp_ring *r; 3748 3749 r = txq->ift_br; 3750 r->drain = iflib_txq_drain_free; 3751 r->can_drain = iflib_txq_drain_always; 3752 3753 ifmp_ring_check_drainage(r, r->size); 3754 3755 r->drain = iflib_txq_drain; 3756 r->can_drain = iflib_txq_can_drain; 3757 } 3758 3759 static void 3760 _task_fn_tx(void *context) 3761 { 3762 iflib_txq_t txq = context; 3763 if_ctx_t ctx = txq->ift_ctx; 3764 struct ifnet *ifp = ctx->ifc_ifp; 3765 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3766 3767 #ifdef IFLIB_DIAGNOSTICS 3768 txq->ift_cpu_exec_count[curcpu]++; 3769 #endif 3770 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3771 return; 3772 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3773 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3774 netmap_tx_irq(ifp, txq->ift_id); 3775 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3776 return; 3777 } 3778 if (txq->ift_db_pending) 3779 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3780 else if (!abdicate) 3781 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3782 /* 3783 * When abdicating, we always need to check drainage, not just when we don't enqueue 3784 */ 3785 if (abdicate) 3786 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3787 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3788 if (ctx->ifc_flags & IFC_LEGACY) 3789 IFDI_INTR_ENABLE(ctx); 3790 else { 3791 #ifdef INVARIANTS 3792 int rc = 3793 #endif 3794 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3795 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3796 } 3797 } 3798 3799 static void 3800 _task_fn_rx(void *context) 3801 { 3802 iflib_rxq_t rxq = context; 3803 if_ctx_t ctx = rxq->ifr_ctx; 3804 bool more; 3805 uint16_t budget; 3806 3807 #ifdef IFLIB_DIAGNOSTICS 3808 rxq->ifr_cpu_exec_count[curcpu]++; 3809 #endif 3810 DBG_COUNTER_INC(task_fn_rxs); 3811 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3812 return; 3813 more = true; 3814 #ifdef DEV_NETMAP 3815 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3816 u_int work = 0; 3817 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3818 more = false; 3819 } 3820 } 3821 #endif 3822 budget = ctx->ifc_sysctl_rx_budget; 3823 if (budget == 0) 3824 budget = 16; /* XXX */ 3825 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3826 if (ctx->ifc_flags & IFC_LEGACY) 3827 IFDI_INTR_ENABLE(ctx); 3828 else { 3829 #ifdef INVARIANTS 3830 int rc = 3831 #endif 3832 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3833 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3834 DBG_COUNTER_INC(rx_intr_enables); 3835 } 3836 } 3837 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3838 return; 3839 if (more) 3840 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3841 } 3842 3843 static void 3844 _task_fn_admin(void *context) 3845 { 3846 if_ctx_t ctx = context; 3847 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3848 iflib_txq_t txq; 3849 int i; 3850 bool oactive, running, do_reset, do_watchdog; 3851 uint32_t reset_on = hz / 2; 3852 3853 STATE_LOCK(ctx); 3854 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3855 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3856 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3857 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3858 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3859 STATE_UNLOCK(ctx); 3860 3861 if ((!running & !oactive) && 3862 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3863 return; 3864 3865 CTX_LOCK(ctx); 3866 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3867 CALLOUT_LOCK(txq); 3868 callout_stop(&txq->ift_timer); 3869 CALLOUT_UNLOCK(txq); 3870 } 3871 if (do_watchdog) { 3872 ctx->ifc_watchdog_events++; 3873 IFDI_WATCHDOG_RESET(ctx); 3874 } 3875 IFDI_UPDATE_ADMIN_STATUS(ctx); 3876 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3877 #ifdef DEV_NETMAP 3878 reset_on = hz / 2; 3879 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3880 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on); 3881 #endif 3882 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3883 } 3884 IFDI_LINK_INTR_ENABLE(ctx); 3885 if (do_reset) 3886 iflib_if_init_locked(ctx); 3887 CTX_UNLOCK(ctx); 3888 3889 if (LINK_ACTIVE(ctx) == 0) 3890 return; 3891 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3892 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3893 } 3894 3895 3896 static void 3897 _task_fn_iov(void *context) 3898 { 3899 if_ctx_t ctx = context; 3900 3901 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3902 return; 3903 3904 CTX_LOCK(ctx); 3905 IFDI_VFLR_HANDLE(ctx); 3906 CTX_UNLOCK(ctx); 3907 } 3908 3909 static int 3910 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3911 { 3912 int err; 3913 if_int_delay_info_t info; 3914 if_ctx_t ctx; 3915 3916 info = (if_int_delay_info_t)arg1; 3917 ctx = info->iidi_ctx; 3918 info->iidi_req = req; 3919 info->iidi_oidp = oidp; 3920 CTX_LOCK(ctx); 3921 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3922 CTX_UNLOCK(ctx); 3923 return (err); 3924 } 3925 3926 /********************************************************************* 3927 * 3928 * IFNET FUNCTIONS 3929 * 3930 **********************************************************************/ 3931 3932 static void 3933 iflib_if_init_locked(if_ctx_t ctx) 3934 { 3935 iflib_stop(ctx); 3936 iflib_init_locked(ctx); 3937 } 3938 3939 3940 static void 3941 iflib_if_init(void *arg) 3942 { 3943 if_ctx_t ctx = arg; 3944 3945 CTX_LOCK(ctx); 3946 iflib_if_init_locked(ctx); 3947 CTX_UNLOCK(ctx); 3948 } 3949 3950 static int 3951 iflib_if_transmit(if_t ifp, struct mbuf *m) 3952 { 3953 if_ctx_t ctx = if_getsoftc(ifp); 3954 3955 iflib_txq_t txq; 3956 int err, qidx; 3957 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3958 3959 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3960 DBG_COUNTER_INC(tx_frees); 3961 m_freem(m); 3962 return (ENOBUFS); 3963 } 3964 3965 MPASS(m->m_nextpkt == NULL); 3966 qidx = 0; 3967 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3968 qidx = QIDX(ctx, m); 3969 /* 3970 * XXX calculate buf_ring based on flowid (divvy up bits?) 3971 */ 3972 txq = &ctx->ifc_txqs[qidx]; 3973 3974 #ifdef DRIVER_BACKPRESSURE 3975 if (txq->ift_closed) { 3976 while (m != NULL) { 3977 next = m->m_nextpkt; 3978 m->m_nextpkt = NULL; 3979 m_freem(m); 3980 m = next; 3981 } 3982 return (ENOBUFS); 3983 } 3984 #endif 3985 #ifdef notyet 3986 qidx = count = 0; 3987 mp = marr; 3988 next = m; 3989 do { 3990 count++; 3991 next = next->m_nextpkt; 3992 } while (next != NULL); 3993 3994 if (count > nitems(marr)) 3995 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3996 /* XXX check nextpkt */ 3997 m_freem(m); 3998 /* XXX simplify for now */ 3999 DBG_COUNTER_INC(tx_frees); 4000 return (ENOBUFS); 4001 } 4002 for (next = m, i = 0; next != NULL; i++) { 4003 mp[i] = next; 4004 next = next->m_nextpkt; 4005 mp[i]->m_nextpkt = NULL; 4006 } 4007 #endif 4008 DBG_COUNTER_INC(tx_seen); 4009 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4010 4011 if (abdicate) 4012 GROUPTASK_ENQUEUE(&txq->ift_task); 4013 if (err) { 4014 if (!abdicate) 4015 GROUPTASK_ENQUEUE(&txq->ift_task); 4016 /* support forthcoming later */ 4017 #ifdef DRIVER_BACKPRESSURE 4018 txq->ift_closed = TRUE; 4019 #endif 4020 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4021 m_freem(m); 4022 } 4023 4024 return (err); 4025 } 4026 4027 static void 4028 iflib_if_qflush(if_t ifp) 4029 { 4030 if_ctx_t ctx = if_getsoftc(ifp); 4031 iflib_txq_t txq = ctx->ifc_txqs; 4032 int i; 4033 4034 STATE_LOCK(ctx); 4035 ctx->ifc_flags |= IFC_QFLUSH; 4036 STATE_UNLOCK(ctx); 4037 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4038 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4039 iflib_txq_check_drain(txq, 0); 4040 STATE_LOCK(ctx); 4041 ctx->ifc_flags &= ~IFC_QFLUSH; 4042 STATE_UNLOCK(ctx); 4043 4044 if_qflush(ifp); 4045 } 4046 4047 4048 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4049 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4050 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 4051 4052 static int 4053 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4054 { 4055 if_ctx_t ctx = if_getsoftc(ifp); 4056 struct ifreq *ifr = (struct ifreq *)data; 4057 #if defined(INET) || defined(INET6) 4058 struct ifaddr *ifa = (struct ifaddr *)data; 4059 #endif 4060 bool avoid_reset = FALSE; 4061 int err = 0, reinit = 0, bits; 4062 4063 switch (command) { 4064 case SIOCSIFADDR: 4065 #ifdef INET 4066 if (ifa->ifa_addr->sa_family == AF_INET) 4067 avoid_reset = TRUE; 4068 #endif 4069 #ifdef INET6 4070 if (ifa->ifa_addr->sa_family == AF_INET6) 4071 avoid_reset = TRUE; 4072 #endif 4073 /* 4074 ** Calling init results in link renegotiation, 4075 ** so we avoid doing it when possible. 4076 */ 4077 if (avoid_reset) { 4078 if_setflagbits(ifp, IFF_UP,0); 4079 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4080 reinit = 1; 4081 #ifdef INET 4082 if (!(if_getflags(ifp) & IFF_NOARP)) 4083 arp_ifinit(ifp, ifa); 4084 #endif 4085 } else 4086 err = ether_ioctl(ifp, command, data); 4087 break; 4088 case SIOCSIFMTU: 4089 CTX_LOCK(ctx); 4090 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4091 CTX_UNLOCK(ctx); 4092 break; 4093 } 4094 bits = if_getdrvflags(ifp); 4095 /* stop the driver and free any clusters before proceeding */ 4096 iflib_stop(ctx); 4097 4098 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4099 STATE_LOCK(ctx); 4100 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4101 ctx->ifc_flags |= IFC_MULTISEG; 4102 else 4103 ctx->ifc_flags &= ~IFC_MULTISEG; 4104 STATE_UNLOCK(ctx); 4105 err = if_setmtu(ifp, ifr->ifr_mtu); 4106 } 4107 iflib_init_locked(ctx); 4108 STATE_LOCK(ctx); 4109 if_setdrvflags(ifp, bits); 4110 STATE_UNLOCK(ctx); 4111 CTX_UNLOCK(ctx); 4112 break; 4113 case SIOCSIFFLAGS: 4114 CTX_LOCK(ctx); 4115 if (if_getflags(ifp) & IFF_UP) { 4116 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4117 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4118 (IFF_PROMISC | IFF_ALLMULTI)) { 4119 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4120 } 4121 } else 4122 reinit = 1; 4123 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4124 iflib_stop(ctx); 4125 } 4126 ctx->ifc_if_flags = if_getflags(ifp); 4127 CTX_UNLOCK(ctx); 4128 break; 4129 case SIOCADDMULTI: 4130 case SIOCDELMULTI: 4131 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4132 CTX_LOCK(ctx); 4133 IFDI_INTR_DISABLE(ctx); 4134 IFDI_MULTI_SET(ctx); 4135 IFDI_INTR_ENABLE(ctx); 4136 CTX_UNLOCK(ctx); 4137 } 4138 break; 4139 case SIOCSIFMEDIA: 4140 CTX_LOCK(ctx); 4141 IFDI_MEDIA_SET(ctx); 4142 CTX_UNLOCK(ctx); 4143 /* falls thru */ 4144 case SIOCGIFMEDIA: 4145 case SIOCGIFXMEDIA: 4146 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 4147 break; 4148 case SIOCGI2C: 4149 { 4150 struct ifi2creq i2c; 4151 4152 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4153 if (err != 0) 4154 break; 4155 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4156 err = EINVAL; 4157 break; 4158 } 4159 if (i2c.len > sizeof(i2c.data)) { 4160 err = EINVAL; 4161 break; 4162 } 4163 4164 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4165 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4166 sizeof(i2c)); 4167 break; 4168 } 4169 case SIOCSIFCAP: 4170 { 4171 int mask, setmask; 4172 4173 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 4174 setmask = 0; 4175 #ifdef TCP_OFFLOAD 4176 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4177 #endif 4178 setmask |= (mask & IFCAP_FLAGS); 4179 4180 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 4181 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4182 if ((mask & IFCAP_WOL) && 4183 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 4184 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 4185 if_vlancap(ifp); 4186 /* 4187 * want to ensure that traffic has stopped before we change any of the flags 4188 */ 4189 if (setmask) { 4190 CTX_LOCK(ctx); 4191 bits = if_getdrvflags(ifp); 4192 if (bits & IFF_DRV_RUNNING) 4193 iflib_stop(ctx); 4194 STATE_LOCK(ctx); 4195 if_togglecapenable(ifp, setmask); 4196 STATE_UNLOCK(ctx); 4197 if (bits & IFF_DRV_RUNNING) 4198 iflib_init_locked(ctx); 4199 STATE_LOCK(ctx); 4200 if_setdrvflags(ifp, bits); 4201 STATE_UNLOCK(ctx); 4202 CTX_UNLOCK(ctx); 4203 } 4204 break; 4205 } 4206 case SIOCGPRIVATE_0: 4207 case SIOCSDRVSPEC: 4208 case SIOCGDRVSPEC: 4209 CTX_LOCK(ctx); 4210 err = IFDI_PRIV_IOCTL(ctx, command, data); 4211 CTX_UNLOCK(ctx); 4212 break; 4213 default: 4214 err = ether_ioctl(ifp, command, data); 4215 break; 4216 } 4217 if (reinit) 4218 iflib_if_init(ctx); 4219 return (err); 4220 } 4221 4222 static uint64_t 4223 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4224 { 4225 if_ctx_t ctx = if_getsoftc(ifp); 4226 4227 return (IFDI_GET_COUNTER(ctx, cnt)); 4228 } 4229 4230 /********************************************************************* 4231 * 4232 * OTHER FUNCTIONS EXPORTED TO THE STACK 4233 * 4234 **********************************************************************/ 4235 4236 static void 4237 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4238 { 4239 if_ctx_t ctx = if_getsoftc(ifp); 4240 4241 if ((void *)ctx != arg) 4242 return; 4243 4244 if ((vtag == 0) || (vtag > 4095)) 4245 return; 4246 4247 CTX_LOCK(ctx); 4248 IFDI_VLAN_REGISTER(ctx, vtag); 4249 /* Re-init to load the changes */ 4250 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4251 iflib_if_init_locked(ctx); 4252 CTX_UNLOCK(ctx); 4253 } 4254 4255 static void 4256 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4257 { 4258 if_ctx_t ctx = if_getsoftc(ifp); 4259 4260 if ((void *)ctx != arg) 4261 return; 4262 4263 if ((vtag == 0) || (vtag > 4095)) 4264 return; 4265 4266 CTX_LOCK(ctx); 4267 IFDI_VLAN_UNREGISTER(ctx, vtag); 4268 /* Re-init to load the changes */ 4269 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4270 iflib_if_init_locked(ctx); 4271 CTX_UNLOCK(ctx); 4272 } 4273 4274 static void 4275 iflib_led_func(void *arg, int onoff) 4276 { 4277 if_ctx_t ctx = arg; 4278 4279 CTX_LOCK(ctx); 4280 IFDI_LED_FUNC(ctx, onoff); 4281 CTX_UNLOCK(ctx); 4282 } 4283 4284 /********************************************************************* 4285 * 4286 * BUS FUNCTION DEFINITIONS 4287 * 4288 **********************************************************************/ 4289 4290 int 4291 iflib_device_probe(device_t dev) 4292 { 4293 pci_vendor_info_t *ent; 4294 4295 uint16_t pci_vendor_id, pci_device_id; 4296 uint16_t pci_subvendor_id, pci_subdevice_id; 4297 uint16_t pci_rev_id; 4298 if_shared_ctx_t sctx; 4299 4300 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4301 return (ENOTSUP); 4302 4303 pci_vendor_id = pci_get_vendor(dev); 4304 pci_device_id = pci_get_device(dev); 4305 pci_subvendor_id = pci_get_subvendor(dev); 4306 pci_subdevice_id = pci_get_subdevice(dev); 4307 pci_rev_id = pci_get_revid(dev); 4308 if (sctx->isc_parse_devinfo != NULL) 4309 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4310 4311 ent = sctx->isc_vendor_info; 4312 while (ent->pvi_vendor_id != 0) { 4313 if (pci_vendor_id != ent->pvi_vendor_id) { 4314 ent++; 4315 continue; 4316 } 4317 if ((pci_device_id == ent->pvi_device_id) && 4318 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4319 (ent->pvi_subvendor_id == 0)) && 4320 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4321 (ent->pvi_subdevice_id == 0)) && 4322 ((pci_rev_id == ent->pvi_rev_id) || 4323 (ent->pvi_rev_id == 0))) { 4324 4325 device_set_desc_copy(dev, ent->pvi_name); 4326 /* this needs to be changed to zero if the bus probing code 4327 * ever stops re-probing on best match because the sctx 4328 * may have its values over written by register calls 4329 * in subsequent probes 4330 */ 4331 return (BUS_PROBE_DEFAULT); 4332 } 4333 ent++; 4334 } 4335 return (ENXIO); 4336 } 4337 4338 static void 4339 iflib_reset_qvalues(if_ctx_t ctx) 4340 { 4341 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4342 if_shared_ctx_t sctx = ctx->ifc_sctx; 4343 device_t dev = ctx->ifc_dev; 4344 int i; 4345 4346 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES; 4347 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH; 4348 /* 4349 * XXX sanity check that ntxd & nrxd are a power of 2 4350 */ 4351 if (ctx->ifc_sysctl_ntxqs != 0) 4352 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4353 if (ctx->ifc_sysctl_nrxqs != 0) 4354 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4355 4356 for (i = 0; i < sctx->isc_ntxqs; i++) { 4357 if (ctx->ifc_sysctl_ntxds[i] != 0) 4358 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4359 else 4360 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4361 } 4362 4363 for (i = 0; i < sctx->isc_nrxqs; i++) { 4364 if (ctx->ifc_sysctl_nrxds[i] != 0) 4365 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4366 else 4367 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4368 } 4369 4370 for (i = 0; i < sctx->isc_nrxqs; i++) { 4371 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4372 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4373 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4374 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4375 } 4376 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4377 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4378 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4379 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4380 } 4381 } 4382 4383 for (i = 0; i < sctx->isc_ntxqs; i++) { 4384 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4385 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4386 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4387 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4388 } 4389 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4390 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4391 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4392 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4393 } 4394 } 4395 } 4396 4397 int 4398 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4399 { 4400 int err, rid, msix; 4401 if_ctx_t ctx; 4402 if_t ifp; 4403 if_softc_ctx_t scctx; 4404 int i; 4405 uint16_t main_txq; 4406 uint16_t main_rxq; 4407 4408 4409 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4410 4411 if (sc == NULL) { 4412 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4413 device_set_softc(dev, ctx); 4414 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4415 } 4416 4417 ctx->ifc_sctx = sctx; 4418 ctx->ifc_dev = dev; 4419 ctx->ifc_softc = sc; 4420 4421 if ((err = iflib_register(ctx)) != 0) { 4422 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4423 free(sc, M_IFLIB); 4424 free(ctx, M_IFLIB); 4425 device_printf(dev, "iflib_register failed %d\n", err); 4426 return (err); 4427 } 4428 iflib_add_device_sysctl_pre(ctx); 4429 4430 scctx = &ctx->ifc_softc_ctx; 4431 ifp = ctx->ifc_ifp; 4432 4433 iflib_reset_qvalues(ctx); 4434 CTX_LOCK(ctx); 4435 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4436 CTX_UNLOCK(ctx); 4437 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4438 return (err); 4439 } 4440 _iflib_pre_assert(scctx); 4441 ctx->ifc_txrx = *scctx->isc_txrx; 4442 4443 #ifdef INVARIANTS 4444 MPASS(scctx->isc_capabilities); 4445 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4446 MPASS(scctx->isc_tx_csum_flags); 4447 #endif 4448 4449 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS); 4450 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4451 4452 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4453 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4454 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4455 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4456 4457 #ifdef ACPI_DMAR 4458 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4459 ctx->ifc_flags |= IFC_DMAR; 4460 #elif !(defined(__i386__) || defined(__amd64__)) 4461 /* set unconditionally for !x86 */ 4462 ctx->ifc_flags |= IFC_DMAR; 4463 #endif 4464 4465 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4466 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4467 4468 /* XXX change for per-queue sizes */ 4469 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4470 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4471 for (i = 0; i < sctx->isc_nrxqs; i++) { 4472 if (!powerof2(scctx->isc_nrxd[i])) { 4473 /* round down instead? */ 4474 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4475 err = EINVAL; 4476 goto fail; 4477 } 4478 } 4479 for (i = 0; i < sctx->isc_ntxqs; i++) { 4480 if (!powerof2(scctx->isc_ntxd[i])) { 4481 device_printf(dev, 4482 "# tx descriptors must be a power of 2"); 4483 err = EINVAL; 4484 goto fail; 4485 } 4486 } 4487 4488 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4489 MAX_SINGLE_PACKET_FRACTION) 4490 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4491 MAX_SINGLE_PACKET_FRACTION); 4492 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4493 MAX_SINGLE_PACKET_FRACTION) 4494 scctx->isc_tx_tso_segments_max = max(1, 4495 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4496 4497 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4498 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4499 /* 4500 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4501 * but some MACs do. 4502 */ 4503 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4504 IP_MAXPACKET)); 4505 /* 4506 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4507 * into account. In the worst case, each of these calls will 4508 * add another mbuf and, thus, the requirement for another DMA 4509 * segment. So for best performance, it doesn't make sense to 4510 * advertize a maximum of TSO segments that typically will 4511 * require defragmentation in iflib_encap(). 4512 */ 4513 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4514 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4515 } 4516 if (scctx->isc_rss_table_size == 0) 4517 scctx->isc_rss_table_size = 64; 4518 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4519 4520 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4521 /* XXX format name */ 4522 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4523 4524 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4525 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4526 device_printf(dev, "Unable to fetch CPU list\n"); 4527 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4528 } 4529 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4530 4531 /* 4532 ** Now setup MSI or MSI/X, should 4533 ** return us the number of supported 4534 ** vectors. (Will be 1 for MSI) 4535 */ 4536 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4537 msix = scctx->isc_vectors; 4538 } else if (scctx->isc_msix_bar != 0) 4539 /* 4540 * The simple fact that isc_msix_bar is not 0 does not mean we 4541 * we have a good value there that is known to work. 4542 */ 4543 msix = iflib_msix_init(ctx); 4544 else { 4545 scctx->isc_vectors = 1; 4546 scctx->isc_ntxqsets = 1; 4547 scctx->isc_nrxqsets = 1; 4548 scctx->isc_intr = IFLIB_INTR_LEGACY; 4549 msix = 0; 4550 } 4551 /* Get memory for the station queues */ 4552 if ((err = iflib_queues_alloc(ctx))) { 4553 device_printf(dev, "Unable to allocate queue memory\n"); 4554 goto fail; 4555 } 4556 4557 if ((err = iflib_qset_structures_setup(ctx))) 4558 goto fail_queues; 4559 4560 /* 4561 * Group taskqueues aren't properly set up until SMP is started, 4562 * so we disable interrupts until we can handle them post 4563 * SI_SUB_SMP. 4564 * 4565 * XXX: disabling interrupts doesn't actually work, at least for 4566 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4567 * we do null handling and depend on this not causing too large an 4568 * interrupt storm. 4569 */ 4570 IFDI_INTR_DISABLE(ctx); 4571 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4572 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4573 goto fail_intr_free; 4574 } 4575 if (msix <= 1) { 4576 rid = 0; 4577 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4578 MPASS(msix == 1); 4579 rid = 1; 4580 } 4581 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4582 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4583 goto fail_intr_free; 4584 } 4585 } 4586 4587 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4588 4589 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4590 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4591 goto fail_detach; 4592 } 4593 4594 /* 4595 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4596 * This must appear after the call to ether_ifattach() because 4597 * ether_ifattach() sets if_hdrlen to the default value. 4598 */ 4599 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4600 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4601 4602 if ((err = iflib_netmap_attach(ctx))) { 4603 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4604 goto fail_detach; 4605 } 4606 *ctxp = ctx; 4607 4608 NETDUMP_SET(ctx->ifc_ifp, iflib); 4609 4610 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4611 iflib_add_device_sysctl_post(ctx); 4612 ctx->ifc_flags |= IFC_INIT_DONE; 4613 CTX_UNLOCK(ctx); 4614 return (0); 4615 fail_detach: 4616 ether_ifdetach(ctx->ifc_ifp); 4617 fail_intr_free: 4618 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4619 pci_release_msi(ctx->ifc_dev); 4620 fail_queues: 4621 iflib_tx_structures_free(ctx); 4622 iflib_rx_structures_free(ctx); 4623 fail: 4624 IFDI_DETACH(ctx); 4625 CTX_UNLOCK(ctx); 4626 return (err); 4627 } 4628 4629 int 4630 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4631 struct iflib_cloneattach_ctx *clctx) 4632 { 4633 int err; 4634 if_ctx_t ctx; 4635 if_t ifp; 4636 if_softc_ctx_t scctx; 4637 int i; 4638 void *sc; 4639 uint16_t main_txq; 4640 uint16_t main_rxq; 4641 4642 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4643 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4644 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4645 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4646 ctx->ifc_flags |= IFC_PSEUDO; 4647 4648 ctx->ifc_sctx = sctx; 4649 ctx->ifc_softc = sc; 4650 ctx->ifc_dev = dev; 4651 4652 if ((err = iflib_register(ctx)) != 0) { 4653 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4654 free(sc, M_IFLIB); 4655 free(ctx, M_IFLIB); 4656 return (err); 4657 } 4658 iflib_add_device_sysctl_pre(ctx); 4659 4660 scctx = &ctx->ifc_softc_ctx; 4661 ifp = ctx->ifc_ifp; 4662 4663 /* 4664 * XXX sanity check that ntxd & nrxd are a power of 2 4665 */ 4666 iflib_reset_qvalues(ctx); 4667 4668 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4669 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4670 return (err); 4671 } 4672 if (sctx->isc_flags & IFLIB_GEN_MAC) 4673 iflib_gen_mac(ctx); 4674 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4675 clctx->cc_params)) != 0) { 4676 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4677 return (err); 4678 } 4679 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4680 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 4681 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO); 4682 4683 #ifdef INVARIANTS 4684 MPASS(scctx->isc_capabilities); 4685 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4686 MPASS(scctx->isc_tx_csum_flags); 4687 #endif 4688 4689 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4690 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4691 4692 ifp->if_flags |= IFF_NOGROUP; 4693 if (sctx->isc_flags & IFLIB_PSEUDO) { 4694 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4695 4696 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4697 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4698 goto fail_detach; 4699 } 4700 *ctxp = ctx; 4701 4702 /* 4703 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4704 * This must appear after the call to ether_ifattach() because 4705 * ether_ifattach() sets if_hdrlen to the default value. 4706 */ 4707 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4708 if_setifheaderlen(ifp, 4709 sizeof(struct ether_vlan_header)); 4710 4711 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4712 iflib_add_device_sysctl_post(ctx); 4713 ctx->ifc_flags |= IFC_INIT_DONE; 4714 return (0); 4715 } 4716 _iflib_pre_assert(scctx); 4717 ctx->ifc_txrx = *scctx->isc_txrx; 4718 4719 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4720 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4721 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4722 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4723 4724 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4725 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4726 4727 /* XXX change for per-queue sizes */ 4728 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4729 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4730 for (i = 0; i < sctx->isc_nrxqs; i++) { 4731 if (!powerof2(scctx->isc_nrxd[i])) { 4732 /* round down instead? */ 4733 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4734 err = EINVAL; 4735 goto fail; 4736 } 4737 } 4738 for (i = 0; i < sctx->isc_ntxqs; i++) { 4739 if (!powerof2(scctx->isc_ntxd[i])) { 4740 device_printf(dev, 4741 "# tx descriptors must be a power of 2"); 4742 err = EINVAL; 4743 goto fail; 4744 } 4745 } 4746 4747 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4748 MAX_SINGLE_PACKET_FRACTION) 4749 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4750 MAX_SINGLE_PACKET_FRACTION); 4751 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4752 MAX_SINGLE_PACKET_FRACTION) 4753 scctx->isc_tx_tso_segments_max = max(1, 4754 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4755 4756 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4757 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4758 /* 4759 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4760 * but some MACs do. 4761 */ 4762 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4763 IP_MAXPACKET)); 4764 /* 4765 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4766 * into account. In the worst case, each of these calls will 4767 * add another mbuf and, thus, the requirement for another DMA 4768 * segment. So for best performance, it doesn't make sense to 4769 * advertize a maximum of TSO segments that typically will 4770 * require defragmentation in iflib_encap(). 4771 */ 4772 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4773 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4774 } 4775 if (scctx->isc_rss_table_size == 0) 4776 scctx->isc_rss_table_size = 64; 4777 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4778 4779 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4780 /* XXX format name */ 4781 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4782 4783 /* XXX --- can support > 1 -- but keep it simple for now */ 4784 scctx->isc_intr = IFLIB_INTR_LEGACY; 4785 4786 /* Get memory for the station queues */ 4787 if ((err = iflib_queues_alloc(ctx))) { 4788 device_printf(dev, "Unable to allocate queue memory\n"); 4789 goto fail; 4790 } 4791 4792 if ((err = iflib_qset_structures_setup(ctx))) { 4793 device_printf(dev, "qset structure setup failed %d\n", err); 4794 goto fail_queues; 4795 } 4796 4797 /* 4798 * XXX What if anything do we want to do about interrupts? 4799 */ 4800 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4801 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4802 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4803 goto fail_detach; 4804 } 4805 4806 /* 4807 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4808 * This must appear after the call to ether_ifattach() because 4809 * ether_ifattach() sets if_hdrlen to the default value. 4810 */ 4811 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4812 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4813 4814 /* XXX handle more than one queue */ 4815 for (i = 0; i < scctx->isc_nrxqsets; i++) 4816 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4817 4818 *ctxp = ctx; 4819 4820 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4821 iflib_add_device_sysctl_post(ctx); 4822 ctx->ifc_flags |= IFC_INIT_DONE; 4823 return (0); 4824 fail_detach: 4825 ether_ifdetach(ctx->ifc_ifp); 4826 fail_queues: 4827 iflib_tx_structures_free(ctx); 4828 iflib_rx_structures_free(ctx); 4829 fail: 4830 IFDI_DETACH(ctx); 4831 return (err); 4832 } 4833 4834 int 4835 iflib_pseudo_deregister(if_ctx_t ctx) 4836 { 4837 if_t ifp = ctx->ifc_ifp; 4838 iflib_txq_t txq; 4839 iflib_rxq_t rxq; 4840 int i, j; 4841 struct taskqgroup *tqg; 4842 iflib_fl_t fl; 4843 4844 /* Unregister VLAN events */ 4845 if (ctx->ifc_vlan_attach_event != NULL) 4846 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4847 if (ctx->ifc_vlan_detach_event != NULL) 4848 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4849 4850 ether_ifdetach(ifp); 4851 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4852 CTX_LOCK_DESTROY(ctx); 4853 /* XXX drain any dependent tasks */ 4854 tqg = qgroup_if_io_tqg; 4855 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4856 callout_drain(&txq->ift_timer); 4857 if (txq->ift_task.gt_uniq != NULL) 4858 taskqgroup_detach(tqg, &txq->ift_task); 4859 } 4860 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4861 if (rxq->ifr_task.gt_uniq != NULL) 4862 taskqgroup_detach(tqg, &rxq->ifr_task); 4863 4864 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4865 free(fl->ifl_rx_bitmap, M_IFLIB); 4866 } 4867 tqg = qgroup_if_config_tqg; 4868 if (ctx->ifc_admin_task.gt_uniq != NULL) 4869 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4870 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4871 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4872 4873 if_free(ifp); 4874 4875 iflib_tx_structures_free(ctx); 4876 iflib_rx_structures_free(ctx); 4877 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4878 free(ctx->ifc_softc, M_IFLIB); 4879 free(ctx, M_IFLIB); 4880 return (0); 4881 } 4882 4883 int 4884 iflib_device_attach(device_t dev) 4885 { 4886 if_ctx_t ctx; 4887 if_shared_ctx_t sctx; 4888 4889 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4890 return (ENOTSUP); 4891 4892 pci_enable_busmaster(dev); 4893 4894 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4895 } 4896 4897 int 4898 iflib_device_deregister(if_ctx_t ctx) 4899 { 4900 if_t ifp = ctx->ifc_ifp; 4901 iflib_txq_t txq; 4902 iflib_rxq_t rxq; 4903 device_t dev = ctx->ifc_dev; 4904 int i, j; 4905 struct taskqgroup *tqg; 4906 iflib_fl_t fl; 4907 4908 /* Make sure VLANS are not using driver */ 4909 if (if_vlantrunkinuse(ifp)) { 4910 device_printf(dev,"Vlan in use, detach first\n"); 4911 return (EBUSY); 4912 } 4913 4914 CTX_LOCK(ctx); 4915 ctx->ifc_in_detach = 1; 4916 iflib_stop(ctx); 4917 CTX_UNLOCK(ctx); 4918 4919 /* Unregister VLAN events */ 4920 if (ctx->ifc_vlan_attach_event != NULL) 4921 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4922 if (ctx->ifc_vlan_detach_event != NULL) 4923 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4924 4925 iflib_netmap_detach(ifp); 4926 ether_ifdetach(ifp); 4927 if (ctx->ifc_led_dev != NULL) 4928 led_destroy(ctx->ifc_led_dev); 4929 /* XXX drain any dependent tasks */ 4930 tqg = qgroup_if_io_tqg; 4931 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4932 callout_drain(&txq->ift_timer); 4933 if (txq->ift_task.gt_uniq != NULL) 4934 taskqgroup_detach(tqg, &txq->ift_task); 4935 } 4936 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4937 if (rxq->ifr_task.gt_uniq != NULL) 4938 taskqgroup_detach(tqg, &rxq->ifr_task); 4939 4940 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4941 free(fl->ifl_rx_bitmap, M_IFLIB); 4942 4943 } 4944 tqg = qgroup_if_config_tqg; 4945 if (ctx->ifc_admin_task.gt_uniq != NULL) 4946 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4947 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4948 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4949 CTX_LOCK(ctx); 4950 IFDI_DETACH(ctx); 4951 CTX_UNLOCK(ctx); 4952 4953 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4954 CTX_LOCK_DESTROY(ctx); 4955 device_set_softc(ctx->ifc_dev, NULL); 4956 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4957 pci_release_msi(dev); 4958 } 4959 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4960 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4961 } 4962 if (ctx->ifc_msix_mem != NULL) { 4963 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4964 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4965 ctx->ifc_msix_mem = NULL; 4966 } 4967 4968 bus_generic_detach(dev); 4969 if_free(ifp); 4970 4971 iflib_tx_structures_free(ctx); 4972 iflib_rx_structures_free(ctx); 4973 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4974 free(ctx->ifc_softc, M_IFLIB); 4975 free(ctx, M_IFLIB); 4976 return (0); 4977 } 4978 4979 4980 int 4981 iflib_device_detach(device_t dev) 4982 { 4983 if_ctx_t ctx = device_get_softc(dev); 4984 4985 return (iflib_device_deregister(ctx)); 4986 } 4987 4988 int 4989 iflib_device_suspend(device_t dev) 4990 { 4991 if_ctx_t ctx = device_get_softc(dev); 4992 4993 CTX_LOCK(ctx); 4994 IFDI_SUSPEND(ctx); 4995 CTX_UNLOCK(ctx); 4996 4997 return bus_generic_suspend(dev); 4998 } 4999 int 5000 iflib_device_shutdown(device_t dev) 5001 { 5002 if_ctx_t ctx = device_get_softc(dev); 5003 5004 CTX_LOCK(ctx); 5005 IFDI_SHUTDOWN(ctx); 5006 CTX_UNLOCK(ctx); 5007 5008 return bus_generic_suspend(dev); 5009 } 5010 5011 5012 int 5013 iflib_device_resume(device_t dev) 5014 { 5015 if_ctx_t ctx = device_get_softc(dev); 5016 iflib_txq_t txq = ctx->ifc_txqs; 5017 5018 CTX_LOCK(ctx); 5019 IFDI_RESUME(ctx); 5020 iflib_init_locked(ctx); 5021 CTX_UNLOCK(ctx); 5022 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5023 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5024 5025 return (bus_generic_resume(dev)); 5026 } 5027 5028 int 5029 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5030 { 5031 int error; 5032 if_ctx_t ctx = device_get_softc(dev); 5033 5034 CTX_LOCK(ctx); 5035 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5036 CTX_UNLOCK(ctx); 5037 5038 return (error); 5039 } 5040 5041 void 5042 iflib_device_iov_uninit(device_t dev) 5043 { 5044 if_ctx_t ctx = device_get_softc(dev); 5045 5046 CTX_LOCK(ctx); 5047 IFDI_IOV_UNINIT(ctx); 5048 CTX_UNLOCK(ctx); 5049 } 5050 5051 int 5052 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5053 { 5054 int error; 5055 if_ctx_t ctx = device_get_softc(dev); 5056 5057 CTX_LOCK(ctx); 5058 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5059 CTX_UNLOCK(ctx); 5060 5061 return (error); 5062 } 5063 5064 /********************************************************************* 5065 * 5066 * MODULE FUNCTION DEFINITIONS 5067 * 5068 **********************************************************************/ 5069 5070 /* 5071 * - Start a fast taskqueue thread for each core 5072 * - Start a taskqueue for control operations 5073 */ 5074 static int 5075 iflib_module_init(void) 5076 { 5077 return (0); 5078 } 5079 5080 static int 5081 iflib_module_event_handler(module_t mod, int what, void *arg) 5082 { 5083 int err; 5084 5085 switch (what) { 5086 case MOD_LOAD: 5087 if ((err = iflib_module_init()) != 0) 5088 return (err); 5089 break; 5090 case MOD_UNLOAD: 5091 return (EBUSY); 5092 default: 5093 return (EOPNOTSUPP); 5094 } 5095 5096 return (0); 5097 } 5098 5099 /********************************************************************* 5100 * 5101 * PUBLIC FUNCTION DEFINITIONS 5102 * ordered as in iflib.h 5103 * 5104 **********************************************************************/ 5105 5106 5107 static void 5108 _iflib_assert(if_shared_ctx_t sctx) 5109 { 5110 MPASS(sctx->isc_tx_maxsize); 5111 MPASS(sctx->isc_tx_maxsegsize); 5112 5113 MPASS(sctx->isc_rx_maxsize); 5114 MPASS(sctx->isc_rx_nsegments); 5115 MPASS(sctx->isc_rx_maxsegsize); 5116 5117 MPASS(sctx->isc_nrxd_min[0]); 5118 MPASS(sctx->isc_nrxd_max[0]); 5119 MPASS(sctx->isc_nrxd_default[0]); 5120 MPASS(sctx->isc_ntxd_min[0]); 5121 MPASS(sctx->isc_ntxd_max[0]); 5122 MPASS(sctx->isc_ntxd_default[0]); 5123 } 5124 5125 static void 5126 _iflib_pre_assert(if_softc_ctx_t scctx) 5127 { 5128 5129 MPASS(scctx->isc_txrx->ift_txd_encap); 5130 MPASS(scctx->isc_txrx->ift_txd_flush); 5131 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5132 MPASS(scctx->isc_txrx->ift_rxd_available); 5133 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5134 MPASS(scctx->isc_txrx->ift_rxd_refill); 5135 MPASS(scctx->isc_txrx->ift_rxd_flush); 5136 } 5137 5138 static int 5139 iflib_register(if_ctx_t ctx) 5140 { 5141 if_shared_ctx_t sctx = ctx->ifc_sctx; 5142 driver_t *driver = sctx->isc_driver; 5143 device_t dev = ctx->ifc_dev; 5144 if_t ifp; 5145 5146 _iflib_assert(sctx); 5147 5148 CTX_LOCK_INIT(ctx); 5149 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5150 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 5151 if (ifp == NULL) { 5152 device_printf(dev, "can not allocate ifnet structure\n"); 5153 return (ENOMEM); 5154 } 5155 5156 /* 5157 * Initialize our context's device specific methods 5158 */ 5159 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5160 kobj_class_compile((kobj_class_t) driver); 5161 driver->refs++; 5162 5163 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5164 if_setsoftc(ifp, ctx); 5165 if_setdev(ifp, dev); 5166 if_setinitfn(ifp, iflib_if_init); 5167 if_setioctlfn(ifp, iflib_if_ioctl); 5168 if_settransmitfn(ifp, iflib_if_transmit); 5169 if_setqflushfn(ifp, iflib_if_qflush); 5170 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5171 5172 ctx->ifc_vlan_attach_event = 5173 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5174 EVENTHANDLER_PRI_FIRST); 5175 ctx->ifc_vlan_detach_event = 5176 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5177 EVENTHANDLER_PRI_FIRST); 5178 5179 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 5180 iflib_media_change, iflib_media_status); 5181 5182 return (0); 5183 } 5184 5185 5186 static int 5187 iflib_queues_alloc(if_ctx_t ctx) 5188 { 5189 if_shared_ctx_t sctx = ctx->ifc_sctx; 5190 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5191 device_t dev = ctx->ifc_dev; 5192 int nrxqsets = scctx->isc_nrxqsets; 5193 int ntxqsets = scctx->isc_ntxqsets; 5194 iflib_txq_t txq; 5195 iflib_rxq_t rxq; 5196 iflib_fl_t fl = NULL; 5197 int i, j, cpu, err, txconf, rxconf; 5198 iflib_dma_info_t ifdip; 5199 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5200 uint32_t *txqsizes = scctx->isc_txqsizes; 5201 uint8_t nrxqs = sctx->isc_nrxqs; 5202 uint8_t ntxqs = sctx->isc_ntxqs; 5203 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5204 caddr_t *vaddrs; 5205 uint64_t *paddrs; 5206 5207 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5208 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5209 5210 /* Allocate the TX ring struct memory */ 5211 if (!(ctx->ifc_txqs = 5212 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5213 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5214 device_printf(dev, "Unable to allocate TX ring memory\n"); 5215 err = ENOMEM; 5216 goto fail; 5217 } 5218 5219 /* Now allocate the RX */ 5220 if (!(ctx->ifc_rxqs = 5221 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5222 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5223 device_printf(dev, "Unable to allocate RX ring memory\n"); 5224 err = ENOMEM; 5225 goto rx_fail; 5226 } 5227 5228 txq = ctx->ifc_txqs; 5229 rxq = ctx->ifc_rxqs; 5230 5231 /* 5232 * XXX handle allocation failure 5233 */ 5234 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5235 /* Set up some basics */ 5236 5237 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 5238 device_printf(dev, "failed to allocate iflib_dma_info\n"); 5239 err = ENOMEM; 5240 goto err_tx_desc; 5241 } 5242 txq->ift_ifdi = ifdip; 5243 for (j = 0; j < ntxqs; j++, ifdip++) { 5244 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 5245 device_printf(dev, "Unable to allocate Descriptor memory\n"); 5246 err = ENOMEM; 5247 goto err_tx_desc; 5248 } 5249 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5250 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5251 } 5252 txq->ift_ctx = ctx; 5253 txq->ift_id = i; 5254 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5255 txq->ift_br_offset = 1; 5256 } else { 5257 txq->ift_br_offset = 0; 5258 } 5259 /* XXX fix this */ 5260 txq->ift_timer.c_cpu = cpu; 5261 5262 if (iflib_txsd_alloc(txq)) { 5263 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5264 err = ENOMEM; 5265 goto err_tx_desc; 5266 } 5267 5268 /* Initialize the TX lock */ 5269 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 5270 device_get_nameunit(dev), txq->ift_id); 5271 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5272 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5273 5274 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 5275 device_get_nameunit(dev), txq->ift_id); 5276 5277 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5278 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5279 if (err) { 5280 /* XXX free any allocated rings */ 5281 device_printf(dev, "Unable to allocate buf_ring\n"); 5282 goto err_tx_desc; 5283 } 5284 } 5285 5286 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5287 /* Set up some basics */ 5288 5289 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 5290 device_printf(dev, "failed to allocate iflib_dma_info\n"); 5291 err = ENOMEM; 5292 goto err_tx_desc; 5293 } 5294 5295 rxq->ifr_ifdi = ifdip; 5296 /* XXX this needs to be changed if #rx queues != #tx queues */ 5297 rxq->ifr_ntxqirq = 1; 5298 rxq->ifr_txqid[0] = i; 5299 for (j = 0; j < nrxqs; j++, ifdip++) { 5300 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 5301 device_printf(dev, "Unable to allocate Descriptor memory\n"); 5302 err = ENOMEM; 5303 goto err_tx_desc; 5304 } 5305 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5306 } 5307 rxq->ifr_ctx = ctx; 5308 rxq->ifr_id = i; 5309 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5310 rxq->ifr_fl_offset = 1; 5311 } else { 5312 rxq->ifr_fl_offset = 0; 5313 } 5314 rxq->ifr_nfl = nfree_lists; 5315 if (!(fl = 5316 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5317 device_printf(dev, "Unable to allocate free list memory\n"); 5318 err = ENOMEM; 5319 goto err_tx_desc; 5320 } 5321 rxq->ifr_fl = fl; 5322 for (j = 0; j < nfree_lists; j++) { 5323 fl[j].ifl_rxq = rxq; 5324 fl[j].ifl_id = j; 5325 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5326 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5327 } 5328 /* Allocate receive buffers for the ring*/ 5329 if (iflib_rxsd_alloc(rxq)) { 5330 device_printf(dev, 5331 "Critical Failure setting up receive buffers\n"); 5332 err = ENOMEM; 5333 goto err_rx_desc; 5334 } 5335 5336 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5337 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 5338 } 5339 5340 /* TXQs */ 5341 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5342 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5343 for (i = 0; i < ntxqsets; i++) { 5344 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5345 5346 for (j = 0; j < ntxqs; j++, di++) { 5347 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5348 paddrs[i*ntxqs + j] = di->idi_paddr; 5349 } 5350 } 5351 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5352 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 5353 iflib_tx_structures_free(ctx); 5354 free(vaddrs, M_IFLIB); 5355 free(paddrs, M_IFLIB); 5356 goto err_rx_desc; 5357 } 5358 free(vaddrs, M_IFLIB); 5359 free(paddrs, M_IFLIB); 5360 5361 /* RXQs */ 5362 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5363 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5364 for (i = 0; i < nrxqsets; i++) { 5365 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5366 5367 for (j = 0; j < nrxqs; j++, di++) { 5368 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5369 paddrs[i*nrxqs + j] = di->idi_paddr; 5370 } 5371 } 5372 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5373 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 5374 iflib_tx_structures_free(ctx); 5375 free(vaddrs, M_IFLIB); 5376 free(paddrs, M_IFLIB); 5377 goto err_rx_desc; 5378 } 5379 free(vaddrs, M_IFLIB); 5380 free(paddrs, M_IFLIB); 5381 5382 return (0); 5383 5384 /* XXX handle allocation failure changes */ 5385 err_rx_desc: 5386 err_tx_desc: 5387 rx_fail: 5388 if (ctx->ifc_rxqs != NULL) 5389 free(ctx->ifc_rxqs, M_IFLIB); 5390 ctx->ifc_rxqs = NULL; 5391 if (ctx->ifc_txqs != NULL) 5392 free(ctx->ifc_txqs, M_IFLIB); 5393 ctx->ifc_txqs = NULL; 5394 fail: 5395 return (err); 5396 } 5397 5398 static int 5399 iflib_tx_structures_setup(if_ctx_t ctx) 5400 { 5401 iflib_txq_t txq = ctx->ifc_txqs; 5402 int i; 5403 5404 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5405 iflib_txq_setup(txq); 5406 5407 return (0); 5408 } 5409 5410 static void 5411 iflib_tx_structures_free(if_ctx_t ctx) 5412 { 5413 iflib_txq_t txq = ctx->ifc_txqs; 5414 int i, j; 5415 5416 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5417 iflib_txq_destroy(txq); 5418 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 5419 iflib_dma_free(&txq->ift_ifdi[j]); 5420 } 5421 free(ctx->ifc_txqs, M_IFLIB); 5422 ctx->ifc_txqs = NULL; 5423 IFDI_QUEUES_FREE(ctx); 5424 } 5425 5426 /********************************************************************* 5427 * 5428 * Initialize all receive rings. 5429 * 5430 **********************************************************************/ 5431 static int 5432 iflib_rx_structures_setup(if_ctx_t ctx) 5433 { 5434 iflib_rxq_t rxq = ctx->ifc_rxqs; 5435 int q; 5436 #if defined(INET6) || defined(INET) 5437 int i, err; 5438 #endif 5439 5440 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5441 #if defined(INET6) || defined(INET) 5442 tcp_lro_free(&rxq->ifr_lc); 5443 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5444 TCP_LRO_ENTRIES, min(1024, 5445 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 5446 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 5447 goto fail; 5448 } 5449 rxq->ifr_lro_enabled = TRUE; 5450 #endif 5451 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5452 } 5453 return (0); 5454 #if defined(INET6) || defined(INET) 5455 fail: 5456 /* 5457 * Free RX software descriptors allocated so far, we will only handle 5458 * the rings that completed, the failing case will have 5459 * cleaned up for itself. 'q' failed, so its the terminus. 5460 */ 5461 rxq = ctx->ifc_rxqs; 5462 for (i = 0; i < q; ++i, rxq++) { 5463 iflib_rx_sds_free(rxq); 5464 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5465 } 5466 return (err); 5467 #endif 5468 } 5469 5470 /********************************************************************* 5471 * 5472 * Free all receive rings. 5473 * 5474 **********************************************************************/ 5475 static void 5476 iflib_rx_structures_free(if_ctx_t ctx) 5477 { 5478 iflib_rxq_t rxq = ctx->ifc_rxqs; 5479 5480 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5481 iflib_rx_sds_free(rxq); 5482 } 5483 } 5484 5485 static int 5486 iflib_qset_structures_setup(if_ctx_t ctx) 5487 { 5488 int err; 5489 5490 /* 5491 * It is expected that the caller takes care of freeing queues if this 5492 * fails. 5493 */ 5494 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5495 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5496 return (err); 5497 } 5498 5499 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5500 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5501 5502 return (err); 5503 } 5504 5505 int 5506 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5507 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5508 { 5509 5510 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5511 } 5512 5513 #ifdef SMP 5514 static int 5515 find_nth(if_ctx_t ctx, int qid) 5516 { 5517 cpuset_t cpus; 5518 int i, cpuid, eqid, count; 5519 5520 CPU_COPY(&ctx->ifc_cpus, &cpus); 5521 count = CPU_COUNT(&cpus); 5522 eqid = qid % count; 5523 /* clear up to the qid'th bit */ 5524 for (i = 0; i < eqid; i++) { 5525 cpuid = CPU_FFS(&cpus); 5526 MPASS(cpuid != 0); 5527 CPU_CLR(cpuid-1, &cpus); 5528 } 5529 cpuid = CPU_FFS(&cpus); 5530 MPASS(cpuid != 0); 5531 return (cpuid-1); 5532 } 5533 5534 #ifdef SCHED_ULE 5535 extern struct cpu_group *cpu_top; /* CPU topology */ 5536 5537 static int 5538 find_child_with_core(int cpu, struct cpu_group *grp) 5539 { 5540 int i; 5541 5542 if (grp->cg_children == 0) 5543 return -1; 5544 5545 MPASS(grp->cg_child); 5546 for (i = 0; i < grp->cg_children; i++) { 5547 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5548 return i; 5549 } 5550 5551 return -1; 5552 } 5553 5554 /* 5555 * Find the nth "close" core to the specified core 5556 * "close" is defined as the deepest level that shares 5557 * at least an L2 cache. With threads, this will be 5558 * threads on the same core. If the sahred cache is L3 5559 * or higher, simply returns the same core. 5560 */ 5561 static int 5562 find_close_core(int cpu, int core_offset) 5563 { 5564 struct cpu_group *grp; 5565 int i; 5566 int fcpu; 5567 cpuset_t cs; 5568 5569 grp = cpu_top; 5570 if (grp == NULL) 5571 return cpu; 5572 i = 0; 5573 while ((i = find_child_with_core(cpu, grp)) != -1) { 5574 /* If the child only has one cpu, don't descend */ 5575 if (grp->cg_child[i].cg_count <= 1) 5576 break; 5577 grp = &grp->cg_child[i]; 5578 } 5579 5580 /* If they don't share at least an L2 cache, use the same CPU */ 5581 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5582 return cpu; 5583 5584 /* Now pick one */ 5585 CPU_COPY(&grp->cg_mask, &cs); 5586 5587 /* Add the selected CPU offset to core offset. */ 5588 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5589 if (fcpu - 1 == cpu) 5590 break; 5591 CPU_CLR(fcpu - 1, &cs); 5592 } 5593 MPASS(fcpu); 5594 5595 core_offset += i; 5596 5597 CPU_COPY(&grp->cg_mask, &cs); 5598 for (i = core_offset % grp->cg_count; i > 0; i--) { 5599 MPASS(CPU_FFS(&cs)); 5600 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5601 } 5602 MPASS(CPU_FFS(&cs)); 5603 return CPU_FFS(&cs) - 1; 5604 } 5605 #else 5606 static int 5607 find_close_core(int cpu, int core_offset __unused) 5608 { 5609 return cpu; 5610 } 5611 #endif 5612 5613 static int 5614 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5615 { 5616 switch (type) { 5617 case IFLIB_INTR_TX: 5618 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5619 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5620 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5621 case IFLIB_INTR_RX: 5622 case IFLIB_INTR_RXTX: 5623 /* RX queues get the specified core */ 5624 return qid / CPU_COUNT(&ctx->ifc_cpus); 5625 default: 5626 return -1; 5627 } 5628 } 5629 #else 5630 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5631 #define find_close_core(cpuid, tid) CPU_FIRST() 5632 #define find_nth(ctx, gid) CPU_FIRST() 5633 #endif 5634 5635 /* Just to avoid copy/paste */ 5636 static inline int 5637 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid, 5638 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, const char *name) 5639 { 5640 int cpuid; 5641 int err, tid; 5642 5643 cpuid = find_nth(ctx, qid); 5644 tid = get_core_offset(ctx, type, qid); 5645 MPASS(tid >= 0); 5646 cpuid = find_close_core(cpuid, tid); 5647 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name); 5648 if (err) { 5649 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err); 5650 return (err); 5651 } 5652 #ifdef notyet 5653 if (cpuid > ctx->ifc_cpuid_highest) 5654 ctx->ifc_cpuid_highest = cpuid; 5655 #endif 5656 return 0; 5657 } 5658 5659 int 5660 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5661 iflib_intr_type_t type, driver_filter_t *filter, 5662 void *filter_arg, int qid, const char *name) 5663 { 5664 struct grouptask *gtask; 5665 struct taskqgroup *tqg; 5666 iflib_filter_info_t info; 5667 gtask_fn_t *fn; 5668 int tqrid, err; 5669 driver_filter_t *intr_fast; 5670 void *q; 5671 5672 info = &ctx->ifc_filter_info; 5673 tqrid = rid; 5674 5675 switch (type) { 5676 /* XXX merge tx/rx for netmap? */ 5677 case IFLIB_INTR_TX: 5678 q = &ctx->ifc_txqs[qid]; 5679 info = &ctx->ifc_txqs[qid].ift_filter_info; 5680 gtask = &ctx->ifc_txqs[qid].ift_task; 5681 tqg = qgroup_if_io_tqg; 5682 fn = _task_fn_tx; 5683 intr_fast = iflib_fast_intr; 5684 GROUPTASK_INIT(gtask, 0, fn, q); 5685 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5686 break; 5687 case IFLIB_INTR_RX: 5688 q = &ctx->ifc_rxqs[qid]; 5689 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5690 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5691 tqg = qgroup_if_io_tqg; 5692 fn = _task_fn_rx; 5693 intr_fast = iflib_fast_intr; 5694 GROUPTASK_INIT(gtask, 0, fn, q); 5695 break; 5696 case IFLIB_INTR_RXTX: 5697 q = &ctx->ifc_rxqs[qid]; 5698 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5699 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5700 tqg = qgroup_if_io_tqg; 5701 fn = _task_fn_rx; 5702 intr_fast = iflib_fast_intr_rxtx; 5703 GROUPTASK_INIT(gtask, 0, fn, q); 5704 break; 5705 case IFLIB_INTR_ADMIN: 5706 q = ctx; 5707 tqrid = -1; 5708 info = &ctx->ifc_filter_info; 5709 gtask = &ctx->ifc_admin_task; 5710 tqg = qgroup_if_config_tqg; 5711 fn = _task_fn_admin; 5712 intr_fast = iflib_fast_intr_ctx; 5713 break; 5714 default: 5715 panic("unknown net intr type"); 5716 } 5717 5718 info->ifi_filter = filter; 5719 info->ifi_filter_arg = filter_arg; 5720 info->ifi_task = gtask; 5721 info->ifi_ctx = q; 5722 5723 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5724 if (err != 0) { 5725 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 5726 return (err); 5727 } 5728 if (type == IFLIB_INTR_ADMIN) 5729 return (0); 5730 5731 if (tqrid != -1) { 5732 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name); 5733 if (err) 5734 return (err); 5735 } else { 5736 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5737 } 5738 5739 return (0); 5740 } 5741 5742 void 5743 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 5744 { 5745 struct grouptask *gtask; 5746 struct taskqgroup *tqg; 5747 gtask_fn_t *fn; 5748 void *q; 5749 int irq_num = -1; 5750 int err; 5751 5752 switch (type) { 5753 case IFLIB_INTR_TX: 5754 q = &ctx->ifc_txqs[qid]; 5755 gtask = &ctx->ifc_txqs[qid].ift_task; 5756 tqg = qgroup_if_io_tqg; 5757 fn = _task_fn_tx; 5758 if (irq != NULL) 5759 irq_num = rman_get_start(irq->ii_res); 5760 break; 5761 case IFLIB_INTR_RX: 5762 q = &ctx->ifc_rxqs[qid]; 5763 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5764 tqg = qgroup_if_io_tqg; 5765 fn = _task_fn_rx; 5766 if (irq != NULL) 5767 irq_num = rman_get_start(irq->ii_res); 5768 break; 5769 case IFLIB_INTR_IOV: 5770 q = ctx; 5771 gtask = &ctx->ifc_vflr_task; 5772 tqg = qgroup_if_config_tqg; 5773 fn = _task_fn_iov; 5774 break; 5775 default: 5776 panic("unknown net intr type"); 5777 } 5778 GROUPTASK_INIT(gtask, 0, fn, q); 5779 if (irq_num != -1) { 5780 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name); 5781 if (err) 5782 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5783 } 5784 else { 5785 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5786 } 5787 } 5788 5789 void 5790 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5791 { 5792 if (irq->ii_tag) 5793 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5794 5795 if (irq->ii_res) 5796 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5797 } 5798 5799 static int 5800 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 5801 { 5802 iflib_txq_t txq = ctx->ifc_txqs; 5803 iflib_rxq_t rxq = ctx->ifc_rxqs; 5804 if_irq_t irq = &ctx->ifc_legacy_irq; 5805 iflib_filter_info_t info; 5806 struct grouptask *gtask; 5807 struct taskqgroup *tqg; 5808 gtask_fn_t *fn; 5809 int tqrid; 5810 void *q; 5811 int err; 5812 5813 q = &ctx->ifc_rxqs[0]; 5814 info = &rxq[0].ifr_filter_info; 5815 gtask = &rxq[0].ifr_task; 5816 tqg = qgroup_if_io_tqg; 5817 tqrid = irq->ii_rid = *rid; 5818 fn = _task_fn_rx; 5819 5820 ctx->ifc_flags |= IFC_LEGACY; 5821 info->ifi_filter = filter; 5822 info->ifi_filter_arg = filter_arg; 5823 info->ifi_task = gtask; 5824 info->ifi_ctx = ctx; 5825 5826 /* We allocate a single interrupt resource */ 5827 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5828 return (err); 5829 GROUPTASK_INIT(gtask, 0, fn, q); 5830 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5831 5832 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5833 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx"); 5834 return (0); 5835 } 5836 5837 void 5838 iflib_led_create(if_ctx_t ctx) 5839 { 5840 5841 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5842 device_get_nameunit(ctx->ifc_dev)); 5843 } 5844 5845 void 5846 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5847 { 5848 5849 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5850 } 5851 5852 void 5853 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5854 { 5855 5856 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5857 } 5858 5859 void 5860 iflib_admin_intr_deferred(if_ctx_t ctx) 5861 { 5862 #ifdef INVARIANTS 5863 struct grouptask *gtask; 5864 5865 gtask = &ctx->ifc_admin_task; 5866 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5867 #endif 5868 5869 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5870 } 5871 5872 void 5873 iflib_iov_intr_deferred(if_ctx_t ctx) 5874 { 5875 5876 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5877 } 5878 5879 void 5880 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5881 { 5882 5883 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5884 } 5885 5886 void 5887 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 5888 const char *name) 5889 { 5890 5891 GROUPTASK_INIT(gtask, 0, fn, ctx); 5892 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5893 } 5894 5895 void 5896 iflib_config_gtask_deinit(struct grouptask *gtask) 5897 { 5898 5899 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5900 } 5901 5902 void 5903 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5904 { 5905 if_t ifp = ctx->ifc_ifp; 5906 iflib_txq_t txq = ctx->ifc_txqs; 5907 5908 if_setbaudrate(ifp, baudrate); 5909 if (baudrate >= IF_Gbps(10)) { 5910 STATE_LOCK(ctx); 5911 ctx->ifc_flags |= IFC_PREFETCH; 5912 STATE_UNLOCK(ctx); 5913 } 5914 /* If link down, disable watchdog */ 5915 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5916 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5917 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5918 } 5919 ctx->ifc_link_state = link_state; 5920 if_link_state_change(ifp, link_state); 5921 } 5922 5923 static int 5924 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5925 { 5926 int credits; 5927 #ifdef INVARIANTS 5928 int credits_pre = txq->ift_cidx_processed; 5929 #endif 5930 5931 if (ctx->isc_txd_credits_update == NULL) 5932 return (0); 5933 5934 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5935 return (0); 5936 5937 txq->ift_processed += credits; 5938 txq->ift_cidx_processed += credits; 5939 5940 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5941 if (txq->ift_cidx_processed >= txq->ift_size) 5942 txq->ift_cidx_processed -= txq->ift_size; 5943 return (credits); 5944 } 5945 5946 static int 5947 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5948 { 5949 5950 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5951 budget)); 5952 } 5953 5954 void 5955 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5956 const char *description, if_int_delay_info_t info, 5957 int offset, int value) 5958 { 5959 info->iidi_ctx = ctx; 5960 info->iidi_offset = offset; 5961 info->iidi_value = value; 5962 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5963 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5964 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5965 info, 0, iflib_sysctl_int_delay, "I", description); 5966 } 5967 5968 struct sx * 5969 iflib_ctx_lock_get(if_ctx_t ctx) 5970 { 5971 5972 return (&ctx->ifc_ctx_sx); 5973 } 5974 5975 static int 5976 iflib_msix_init(if_ctx_t ctx) 5977 { 5978 device_t dev = ctx->ifc_dev; 5979 if_shared_ctx_t sctx = ctx->ifc_sctx; 5980 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5981 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5982 int iflib_num_tx_queues, iflib_num_rx_queues; 5983 int err, admincnt, bar; 5984 5985 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 5986 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 5987 5988 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 5989 5990 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5991 admincnt = sctx->isc_admin_intrcnt; 5992 /* Override by tuneable */ 5993 if (scctx->isc_disable_msix) 5994 goto msi; 5995 5996 /* 5997 * bar == -1 => "trust me I know what I'm doing" 5998 * Some drivers are for hardware that is so shoddily 5999 * documented that no one knows which bars are which 6000 * so the developer has to map all bars. This hack 6001 * allows shoddy garbage to use msix in this framework. 6002 */ 6003 if (bar != -1) { 6004 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6005 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6006 if (ctx->ifc_msix_mem == NULL) { 6007 /* May not be enabled */ 6008 device_printf(dev, "Unable to map MSIX table \n"); 6009 goto msi; 6010 } 6011 } 6012 /* First try MSI/X */ 6013 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 6014 device_printf(dev, "System has MSIX disabled \n"); 6015 bus_release_resource(dev, SYS_RES_MEMORY, 6016 bar, ctx->ifc_msix_mem); 6017 ctx->ifc_msix_mem = NULL; 6018 goto msi; 6019 } 6020 #if IFLIB_DEBUG 6021 /* use only 1 qset in debug mode */ 6022 queuemsgs = min(msgs - admincnt, 1); 6023 #else 6024 queuemsgs = msgs - admincnt; 6025 #endif 6026 #ifdef RSS 6027 queues = imin(queuemsgs, rss_getnumbuckets()); 6028 #else 6029 queues = queuemsgs; 6030 #endif 6031 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6032 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 6033 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6034 #ifdef RSS 6035 /* If we're doing RSS, clamp at the number of RSS buckets */ 6036 if (queues > rss_getnumbuckets()) 6037 queues = rss_getnumbuckets(); 6038 #endif 6039 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6040 rx_queues = iflib_num_rx_queues; 6041 else 6042 rx_queues = queues; 6043 6044 if (rx_queues > scctx->isc_nrxqsets) 6045 rx_queues = scctx->isc_nrxqsets; 6046 6047 /* 6048 * We want this to be all logical CPUs by default 6049 */ 6050 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6051 tx_queues = iflib_num_tx_queues; 6052 else 6053 tx_queues = mp_ncpus; 6054 6055 if (tx_queues > scctx->isc_ntxqsets) 6056 tx_queues = scctx->isc_ntxqsets; 6057 6058 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6059 #ifdef INVARIANTS 6060 if (tx_queues != rx_queues) 6061 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6062 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6063 #endif 6064 tx_queues = min(rx_queues, tx_queues); 6065 rx_queues = min(rx_queues, tx_queues); 6066 } 6067 6068 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 6069 6070 vectors = rx_queues + admincnt; 6071 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6072 device_printf(dev, 6073 "Using MSIX interrupts with %d vectors\n", vectors); 6074 scctx->isc_vectors = vectors; 6075 scctx->isc_nrxqsets = rx_queues; 6076 scctx->isc_ntxqsets = tx_queues; 6077 scctx->isc_intr = IFLIB_INTR_MSIX; 6078 6079 return (vectors); 6080 } else { 6081 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 6082 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6083 ctx->ifc_msix_mem); 6084 ctx->ifc_msix_mem = NULL; 6085 } 6086 msi: 6087 vectors = pci_msi_count(dev); 6088 scctx->isc_nrxqsets = 1; 6089 scctx->isc_ntxqsets = 1; 6090 scctx->isc_vectors = vectors; 6091 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6092 device_printf(dev,"Using an MSI interrupt\n"); 6093 scctx->isc_intr = IFLIB_INTR_MSI; 6094 } else { 6095 scctx->isc_vectors = 1; 6096 device_printf(dev,"Using a Legacy interrupt\n"); 6097 scctx->isc_intr = IFLIB_INTR_LEGACY; 6098 } 6099 6100 return (vectors); 6101 } 6102 6103 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6104 6105 static int 6106 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6107 { 6108 int rc; 6109 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6110 struct sbuf *sb; 6111 const char *ring_state = "UNKNOWN"; 6112 6113 /* XXX needed ? */ 6114 rc = sysctl_wire_old_buffer(req, 0); 6115 MPASS(rc == 0); 6116 if (rc != 0) 6117 return (rc); 6118 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6119 MPASS(sb != NULL); 6120 if (sb == NULL) 6121 return (ENOMEM); 6122 if (state[3] <= 3) 6123 ring_state = ring_states[state[3]]; 6124 6125 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6126 state[0], state[1], state[2], ring_state); 6127 rc = sbuf_finish(sb); 6128 sbuf_delete(sb); 6129 return(rc); 6130 } 6131 6132 enum iflib_ndesc_handler { 6133 IFLIB_NTXD_HANDLER, 6134 IFLIB_NRXD_HANDLER, 6135 }; 6136 6137 static int 6138 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6139 { 6140 if_ctx_t ctx = (void *)arg1; 6141 enum iflib_ndesc_handler type = arg2; 6142 char buf[256] = {0}; 6143 qidx_t *ndesc; 6144 char *p, *next; 6145 int nqs, rc, i; 6146 6147 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 6148 6149 nqs = 8; 6150 switch(type) { 6151 case IFLIB_NTXD_HANDLER: 6152 ndesc = ctx->ifc_sysctl_ntxds; 6153 if (ctx->ifc_sctx) 6154 nqs = ctx->ifc_sctx->isc_ntxqs; 6155 break; 6156 case IFLIB_NRXD_HANDLER: 6157 ndesc = ctx->ifc_sysctl_nrxds; 6158 if (ctx->ifc_sctx) 6159 nqs = ctx->ifc_sctx->isc_nrxqs; 6160 break; 6161 default: 6162 panic("unhandled type"); 6163 } 6164 if (nqs == 0) 6165 nqs = 8; 6166 6167 for (i=0; i<8; i++) { 6168 if (i >= nqs) 6169 break; 6170 if (i) 6171 strcat(buf, ","); 6172 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6173 } 6174 6175 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6176 if (rc || req->newptr == NULL) 6177 return rc; 6178 6179 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6180 i++, p = strsep(&next, " ,")) { 6181 ndesc[i] = strtoul(p, NULL, 10); 6182 } 6183 6184 return(rc); 6185 } 6186 6187 #define NAME_BUFLEN 32 6188 static void 6189 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6190 { 6191 device_t dev = iflib_get_dev(ctx); 6192 struct sysctl_oid_list *child, *oid_list; 6193 struct sysctl_ctx_list *ctx_list; 6194 struct sysctl_oid *node; 6195 6196 ctx_list = device_get_sysctl_ctx(dev); 6197 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6198 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6199 CTLFLAG_RD, NULL, "IFLIB fields"); 6200 oid_list = SYSCTL_CHILDREN(node); 6201 6202 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6203 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 6204 "driver version"); 6205 6206 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6207 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6208 "# of txqs to use, 0 => use default #"); 6209 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6210 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6211 "# of rxqs to use, 0 => use default #"); 6212 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6213 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6214 "permit #txq != #rxq"); 6215 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6216 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6217 "disable MSIX (default 0)"); 6218 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6219 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6220 "set the rx budget"); 6221 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6222 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6223 "cause tx to abdicate instead of running to completion"); 6224 6225 /* XXX change for per-queue sizes */ 6226 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6227 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6228 mp_ndesc_handler, "A", 6229 "list of # of tx descriptors to use, 0 = use default #"); 6230 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6231 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6232 mp_ndesc_handler, "A", 6233 "list of # of rx descriptors to use, 0 = use default #"); 6234 } 6235 6236 static void 6237 iflib_add_device_sysctl_post(if_ctx_t ctx) 6238 { 6239 if_shared_ctx_t sctx = ctx->ifc_sctx; 6240 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6241 device_t dev = iflib_get_dev(ctx); 6242 struct sysctl_oid_list *child; 6243 struct sysctl_ctx_list *ctx_list; 6244 iflib_fl_t fl; 6245 iflib_txq_t txq; 6246 iflib_rxq_t rxq; 6247 int i, j; 6248 char namebuf[NAME_BUFLEN]; 6249 char *qfmt; 6250 struct sysctl_oid *queue_node, *fl_node, *node; 6251 struct sysctl_oid_list *queue_list, *fl_list; 6252 ctx_list = device_get_sysctl_ctx(dev); 6253 6254 node = ctx->ifc_sysctl_node; 6255 child = SYSCTL_CHILDREN(node); 6256 6257 if (scctx->isc_ntxqsets > 100) 6258 qfmt = "txq%03d"; 6259 else if (scctx->isc_ntxqsets > 10) 6260 qfmt = "txq%02d"; 6261 else 6262 qfmt = "txq%d"; 6263 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6264 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6265 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6266 CTLFLAG_RD, NULL, "Queue Name"); 6267 queue_list = SYSCTL_CHILDREN(queue_node); 6268 #if MEMORY_LOGGING 6269 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6270 CTLFLAG_RD, 6271 &txq->ift_dequeued, "total mbufs freed"); 6272 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6273 CTLFLAG_RD, 6274 &txq->ift_enqueued, "total mbufs enqueued"); 6275 #endif 6276 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6277 CTLFLAG_RD, 6278 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6279 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6280 CTLFLAG_RD, 6281 &txq->ift_pullups, "# of times m_pullup was called"); 6282 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6283 CTLFLAG_RD, 6284 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6285 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6286 CTLFLAG_RD, 6287 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6288 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6289 CTLFLAG_RD, 6290 &txq->ift_map_failed, "# of times dma map failed"); 6291 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6292 CTLFLAG_RD, 6293 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6294 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6295 CTLFLAG_RD, 6296 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6297 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6298 CTLFLAG_RD, 6299 &txq->ift_pidx, 1, "Producer Index"); 6300 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6301 CTLFLAG_RD, 6302 &txq->ift_cidx, 1, "Consumer Index"); 6303 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6304 CTLFLAG_RD, 6305 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6306 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6307 CTLFLAG_RD, 6308 &txq->ift_in_use, 1, "descriptors in use"); 6309 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6310 CTLFLAG_RD, 6311 &txq->ift_processed, "descriptors procesed for clean"); 6312 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6313 CTLFLAG_RD, 6314 &txq->ift_cleaned, "total cleaned"); 6315 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6316 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6317 0, mp_ring_state_handler, "A", "soft ring state"); 6318 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6319 CTLFLAG_RD, &txq->ift_br->enqueues, 6320 "# of enqueues to the mp_ring for this queue"); 6321 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6322 CTLFLAG_RD, &txq->ift_br->drops, 6323 "# of drops in the mp_ring for this queue"); 6324 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6325 CTLFLAG_RD, &txq->ift_br->starts, 6326 "# of normal consumer starts in the mp_ring for this queue"); 6327 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6328 CTLFLAG_RD, &txq->ift_br->stalls, 6329 "# of consumer stalls in the mp_ring for this queue"); 6330 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6331 CTLFLAG_RD, &txq->ift_br->restarts, 6332 "# of consumer restarts in the mp_ring for this queue"); 6333 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6334 CTLFLAG_RD, &txq->ift_br->abdications, 6335 "# of consumer abdications in the mp_ring for this queue"); 6336 } 6337 6338 if (scctx->isc_nrxqsets > 100) 6339 qfmt = "rxq%03d"; 6340 else if (scctx->isc_nrxqsets > 10) 6341 qfmt = "rxq%02d"; 6342 else 6343 qfmt = "rxq%d"; 6344 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6345 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6346 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6347 CTLFLAG_RD, NULL, "Queue Name"); 6348 queue_list = SYSCTL_CHILDREN(queue_node); 6349 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6350 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 6351 CTLFLAG_RD, 6352 &rxq->ifr_cq_pidx, 1, "Producer Index"); 6353 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6354 CTLFLAG_RD, 6355 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6356 } 6357 6358 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6359 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6360 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6361 CTLFLAG_RD, NULL, "freelist Name"); 6362 fl_list = SYSCTL_CHILDREN(fl_node); 6363 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6364 CTLFLAG_RD, 6365 &fl->ifl_pidx, 1, "Producer Index"); 6366 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6367 CTLFLAG_RD, 6368 &fl->ifl_cidx, 1, "Consumer Index"); 6369 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6370 CTLFLAG_RD, 6371 &fl->ifl_credits, 1, "credits available"); 6372 #if MEMORY_LOGGING 6373 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6374 CTLFLAG_RD, 6375 &fl->ifl_m_enqueued, "mbufs allocated"); 6376 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6377 CTLFLAG_RD, 6378 &fl->ifl_m_dequeued, "mbufs freed"); 6379 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6380 CTLFLAG_RD, 6381 &fl->ifl_cl_enqueued, "clusters allocated"); 6382 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6383 CTLFLAG_RD, 6384 &fl->ifl_cl_dequeued, "clusters freed"); 6385 #endif 6386 6387 } 6388 } 6389 6390 } 6391 6392 #ifndef __NO_STRICT_ALIGNMENT 6393 static struct mbuf * 6394 iflib_fixup_rx(struct mbuf *m) 6395 { 6396 struct mbuf *n; 6397 6398 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6399 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6400 m->m_data += ETHER_HDR_LEN; 6401 n = m; 6402 } else { 6403 MGETHDR(n, M_NOWAIT, MT_DATA); 6404 if (n == NULL) { 6405 m_freem(m); 6406 return (NULL); 6407 } 6408 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6409 m->m_data += ETHER_HDR_LEN; 6410 m->m_len -= ETHER_HDR_LEN; 6411 n->m_len = ETHER_HDR_LEN; 6412 M_MOVE_PKTHDR(n, m); 6413 n->m_next = m; 6414 } 6415 return (n); 6416 } 6417 #endif 6418 6419 #ifdef NETDUMP 6420 static void 6421 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 6422 { 6423 if_ctx_t ctx; 6424 6425 ctx = if_getsoftc(ifp); 6426 CTX_LOCK(ctx); 6427 *nrxr = NRXQSETS(ctx); 6428 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6429 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6430 CTX_UNLOCK(ctx); 6431 } 6432 6433 static void 6434 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event) 6435 { 6436 if_ctx_t ctx; 6437 if_softc_ctx_t scctx; 6438 iflib_fl_t fl; 6439 iflib_rxq_t rxq; 6440 int i, j; 6441 6442 ctx = if_getsoftc(ifp); 6443 scctx = &ctx->ifc_softc_ctx; 6444 6445 switch (event) { 6446 case NETDUMP_START: 6447 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6448 rxq = &ctx->ifc_rxqs[i]; 6449 for (j = 0; j < rxq->ifr_nfl; j++) { 6450 fl = rxq->ifr_fl; 6451 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6452 } 6453 } 6454 iflib_no_tx_batch = 1; 6455 break; 6456 default: 6457 break; 6458 } 6459 } 6460 6461 static int 6462 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m) 6463 { 6464 if_ctx_t ctx; 6465 iflib_txq_t txq; 6466 int error; 6467 6468 ctx = if_getsoftc(ifp); 6469 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6470 IFF_DRV_RUNNING) 6471 return (EBUSY); 6472 6473 txq = &ctx->ifc_txqs[0]; 6474 error = iflib_encap(txq, &m); 6475 if (error == 0) 6476 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6477 return (error); 6478 } 6479 6480 static int 6481 iflib_netdump_poll(struct ifnet *ifp, int count) 6482 { 6483 if_ctx_t ctx; 6484 if_softc_ctx_t scctx; 6485 iflib_txq_t txq; 6486 int i; 6487 6488 ctx = if_getsoftc(ifp); 6489 scctx = &ctx->ifc_softc_ctx; 6490 6491 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6492 IFF_DRV_RUNNING) 6493 return (EBUSY); 6494 6495 txq = &ctx->ifc_txqs[0]; 6496 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6497 6498 for (i = 0; i < scctx->isc_nrxqsets; i++) 6499 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6500 return (0); 6501 } 6502 #endif /* NETDUMP */ 6503