xref: /freebsd/sys/net/iflib.c (revision c697fb7f7cc9bedc5beee44d35b771c4e87b335a)
1 /*-
2  * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  *  1. Redistributions of source code must retain the above copyright notice,
9  *     this list of conditions and the following disclaimer.
10  *
11  *  2. Neither the name of Matthew Macy nor the names of its
12  *     contributors may be used to endorse or promote products derived from
13  *     this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25  * POSSIBILITY OF SUCH DAMAGE.
26  */
27 
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30 
31 #include "opt_inet.h"
32 #include "opt_inet6.h"
33 #include "opt_acpi.h"
34 #include "opt_sched.h"
35 
36 #include <sys/param.h>
37 #include <sys/types.h>
38 #include <sys/bus.h>
39 #include <sys/eventhandler.h>
40 #include <sys/kernel.h>
41 #include <sys/lock.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
44 #include <sys/kobj.h>
45 #include <sys/rman.h>
46 #include <sys/sbuf.h>
47 #include <sys/smp.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
54 
55 #include <net/if.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
59 #include <net/bpf.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
62 #include <net/debugnet.h>
63 #include <net/pfil.h>
64 #include <net/vnet.h>
65 
66 #include <netinet/in.h>
67 #include <netinet/in_pcb.h>
68 #include <netinet/tcp_lro.h>
69 #include <netinet/in_systm.h>
70 #include <netinet/if_ether.h>
71 #include <netinet/ip.h>
72 #include <netinet/ip6.h>
73 #include <netinet/tcp.h>
74 #include <netinet/ip_var.h>
75 #include <netinet6/ip6_var.h>
76 
77 #include <machine/bus.h>
78 #include <machine/in_cksum.h>
79 
80 #include <vm/vm.h>
81 #include <vm/pmap.h>
82 
83 #include <dev/led/led.h>
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
86 #include <dev/pci/pci_private.h>
87 
88 #include <net/iflib.h>
89 #include <net/iflib_private.h>
90 
91 #include "ifdi_if.h"
92 
93 #ifdef PCI_IOV
94 #include <dev/pci/pci_iov.h>
95 #endif
96 
97 #include <sys/bitstring.h>
98 /*
99  * enable accounting of every mbuf as it comes in to and goes out of
100  * iflib's software descriptor references
101  */
102 #define MEMORY_LOGGING 0
103 /*
104  * Enable mbuf vectors for compressing long mbuf chains
105  */
106 
107 /*
108  * NB:
109  * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110  *   we prefetch needs to be determined by the time spent in m_free vis a vis
111  *   the cost of a prefetch. This will of course vary based on the workload:
112  *      - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
113  *        is quite expensive, thus suggesting very little prefetch.
114  *      - small packet forwarding which is just returning a single mbuf to
115  *        UMA will typically be very fast vis a vis the cost of a memory
116  *        access.
117  */
118 
119 
120 /*
121  * File organization:
122  *  - private structures
123  *  - iflib private utility functions
124  *  - ifnet functions
125  *  - vlan registry and other exported functions
126  *  - iflib public core functions
127  *
128  *
129  */
130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
131 
132 #define	IFLIB_RXEOF_MORE (1U << 0)
133 #define	IFLIB_RXEOF_EMPTY (2U << 0)
134 
135 struct iflib_txq;
136 typedef struct iflib_txq *iflib_txq_t;
137 struct iflib_rxq;
138 typedef struct iflib_rxq *iflib_rxq_t;
139 struct iflib_fl;
140 typedef struct iflib_fl *iflib_fl_t;
141 
142 struct iflib_ctx;
143 
144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
145 static void iflib_timer(void *arg);
146 
147 typedef struct iflib_filter_info {
148 	driver_filter_t *ifi_filter;
149 	void *ifi_filter_arg;
150 	struct grouptask *ifi_task;
151 	void *ifi_ctx;
152 } *iflib_filter_info_t;
153 
154 struct iflib_ctx {
155 	KOBJ_FIELDS;
156 	/*
157 	 * Pointer to hardware driver's softc
158 	 */
159 	void *ifc_softc;
160 	device_t ifc_dev;
161 	if_t ifc_ifp;
162 
163 	cpuset_t ifc_cpus;
164 	if_shared_ctx_t ifc_sctx;
165 	struct if_softc_ctx ifc_softc_ctx;
166 
167 	struct sx ifc_ctx_sx;
168 	struct mtx ifc_state_mtx;
169 
170 	iflib_txq_t ifc_txqs;
171 	iflib_rxq_t ifc_rxqs;
172 	uint32_t ifc_if_flags;
173 	uint32_t ifc_flags;
174 	uint32_t ifc_max_fl_buf_size;
175 	uint32_t ifc_rx_mbuf_sz;
176 
177 	int ifc_link_state;
178 	int ifc_watchdog_events;
179 	struct cdev *ifc_led_dev;
180 	struct resource *ifc_msix_mem;
181 
182 	struct if_irq ifc_legacy_irq;
183 	struct grouptask ifc_admin_task;
184 	struct grouptask ifc_vflr_task;
185 	struct iflib_filter_info ifc_filter_info;
186 	struct ifmedia	ifc_media;
187 	struct ifmedia	*ifc_mediap;
188 
189 	struct sysctl_oid *ifc_sysctl_node;
190 	uint16_t ifc_sysctl_ntxqs;
191 	uint16_t ifc_sysctl_nrxqs;
192 	uint16_t ifc_sysctl_qs_eq_override;
193 	uint16_t ifc_sysctl_rx_budget;
194 	uint16_t ifc_sysctl_tx_abdicate;
195 	uint16_t ifc_sysctl_core_offset;
196 #define	CORE_OFFSET_UNSPECIFIED	0xffff
197 	uint8_t  ifc_sysctl_separate_txrx;
198 
199 	qidx_t ifc_sysctl_ntxds[8];
200 	qidx_t ifc_sysctl_nrxds[8];
201 	struct if_txrx ifc_txrx;
202 #define isc_txd_encap  ifc_txrx.ift_txd_encap
203 #define isc_txd_flush  ifc_txrx.ift_txd_flush
204 #define isc_txd_credits_update  ifc_txrx.ift_txd_credits_update
205 #define isc_rxd_available ifc_txrx.ift_rxd_available
206 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
208 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
209 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
210 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
211 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
212 	eventhandler_tag ifc_vlan_attach_event;
213 	eventhandler_tag ifc_vlan_detach_event;
214 	struct ether_addr ifc_mac;
215 };
216 
217 void *
218 iflib_get_softc(if_ctx_t ctx)
219 {
220 
221 	return (ctx->ifc_softc);
222 }
223 
224 device_t
225 iflib_get_dev(if_ctx_t ctx)
226 {
227 
228 	return (ctx->ifc_dev);
229 }
230 
231 if_t
232 iflib_get_ifp(if_ctx_t ctx)
233 {
234 
235 	return (ctx->ifc_ifp);
236 }
237 
238 struct ifmedia *
239 iflib_get_media(if_ctx_t ctx)
240 {
241 
242 	return (ctx->ifc_mediap);
243 }
244 
245 uint32_t
246 iflib_get_flags(if_ctx_t ctx)
247 {
248 	return (ctx->ifc_flags);
249 }
250 
251 void
252 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
253 {
254 
255 	bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
256 }
257 
258 if_softc_ctx_t
259 iflib_get_softc_ctx(if_ctx_t ctx)
260 {
261 
262 	return (&ctx->ifc_softc_ctx);
263 }
264 
265 if_shared_ctx_t
266 iflib_get_sctx(if_ctx_t ctx)
267 {
268 
269 	return (ctx->ifc_sctx);
270 }
271 
272 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
273 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
274 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
275 
276 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
277 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
278 
279 typedef struct iflib_sw_rx_desc_array {
280 	bus_dmamap_t	*ifsd_map;         /* bus_dma maps for packet */
281 	struct mbuf	**ifsd_m;           /* pkthdr mbufs */
282 	caddr_t		*ifsd_cl;          /* direct cluster pointer for rx */
283 	bus_addr_t	*ifsd_ba;          /* bus addr of cluster for rx */
284 } iflib_rxsd_array_t;
285 
286 typedef struct iflib_sw_tx_desc_array {
287 	bus_dmamap_t    *ifsd_map;         /* bus_dma maps for packet */
288 	bus_dmamap_t	*ifsd_tso_map;     /* bus_dma maps for TSO packet */
289 	struct mbuf    **ifsd_m;           /* pkthdr mbufs */
290 } if_txsd_vec_t;
291 
292 /* magic number that should be high enough for any hardware */
293 #define IFLIB_MAX_TX_SEGS		128
294 #define IFLIB_RX_COPY_THRESH		128
295 #define IFLIB_MAX_RX_REFRESH		32
296 /* The minimum descriptors per second before we start coalescing */
297 #define IFLIB_MIN_DESC_SEC		16384
298 #define IFLIB_DEFAULT_TX_UPDATE_FREQ	16
299 #define IFLIB_QUEUE_IDLE		0
300 #define IFLIB_QUEUE_HUNG		1
301 #define IFLIB_QUEUE_WORKING		2
302 /* maximum number of txqs that can share an rx interrupt */
303 #define IFLIB_MAX_TX_SHARED_INTR	4
304 
305 /* this should really scale with ring size - this is a fairly arbitrary value */
306 #define TX_BATCH_SIZE			32
307 
308 #define IFLIB_RESTART_BUDGET		8
309 
310 #define CSUM_OFFLOAD		(CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
311 				 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
312 				 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
313 
314 struct iflib_txq {
315 	qidx_t		ift_in_use;
316 	qidx_t		ift_cidx;
317 	qidx_t		ift_cidx_processed;
318 	qidx_t		ift_pidx;
319 	uint8_t		ift_gen;
320 	uint8_t		ift_br_offset;
321 	uint16_t	ift_npending;
322 	uint16_t	ift_db_pending;
323 	uint16_t	ift_rs_pending;
324 	/* implicit pad */
325 	uint8_t		ift_txd_size[8];
326 	uint64_t	ift_processed;
327 	uint64_t	ift_cleaned;
328 	uint64_t	ift_cleaned_prev;
329 #if MEMORY_LOGGING
330 	uint64_t	ift_enqueued;
331 	uint64_t	ift_dequeued;
332 #endif
333 	uint64_t	ift_no_tx_dma_setup;
334 	uint64_t	ift_no_desc_avail;
335 	uint64_t	ift_mbuf_defrag_failed;
336 	uint64_t	ift_mbuf_defrag;
337 	uint64_t	ift_map_failed;
338 	uint64_t	ift_txd_encap_efbig;
339 	uint64_t	ift_pullups;
340 	uint64_t	ift_last_timer_tick;
341 
342 	struct mtx	ift_mtx;
343 	struct mtx	ift_db_mtx;
344 
345 	/* constant values */
346 	if_ctx_t	ift_ctx;
347 	struct ifmp_ring        *ift_br;
348 	struct grouptask	ift_task;
349 	qidx_t		ift_size;
350 	uint16_t	ift_id;
351 	struct callout	ift_timer;
352 
353 	if_txsd_vec_t	ift_sds;
354 	uint8_t		ift_qstatus;
355 	uint8_t		ift_closed;
356 	uint8_t		ift_update_freq;
357 	struct iflib_filter_info ift_filter_info;
358 	bus_dma_tag_t	ift_buf_tag;
359 	bus_dma_tag_t	ift_tso_buf_tag;
360 	iflib_dma_info_t	ift_ifdi;
361 #define MTX_NAME_LEN 16
362 	char                    ift_mtx_name[MTX_NAME_LEN];
363 	bus_dma_segment_t	ift_segs[IFLIB_MAX_TX_SEGS]  __aligned(CACHE_LINE_SIZE);
364 #ifdef IFLIB_DIAGNOSTICS
365 	uint64_t ift_cpu_exec_count[256];
366 #endif
367 } __aligned(CACHE_LINE_SIZE);
368 
369 struct iflib_fl {
370 	qidx_t		ifl_cidx;
371 	qidx_t		ifl_pidx;
372 	qidx_t		ifl_credits;
373 	uint8_t		ifl_gen;
374 	uint8_t		ifl_rxd_size;
375 #if MEMORY_LOGGING
376 	uint64_t	ifl_m_enqueued;
377 	uint64_t	ifl_m_dequeued;
378 	uint64_t	ifl_cl_enqueued;
379 	uint64_t	ifl_cl_dequeued;
380 #endif
381 	/* implicit pad */
382 	bitstr_t 	*ifl_rx_bitmap;
383 	qidx_t		ifl_fragidx;
384 	/* constant */
385 	qidx_t		ifl_size;
386 	uint16_t	ifl_buf_size;
387 	uint16_t	ifl_cltype;
388 	uma_zone_t	ifl_zone;
389 	iflib_rxsd_array_t	ifl_sds;
390 	iflib_rxq_t	ifl_rxq;
391 	uint8_t		ifl_id;
392 	bus_dma_tag_t	ifl_buf_tag;
393 	iflib_dma_info_t	ifl_ifdi;
394 	uint64_t	ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
395 	caddr_t		ifl_vm_addrs[IFLIB_MAX_RX_REFRESH];
396 	qidx_t	ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
397 }  __aligned(CACHE_LINE_SIZE);
398 
399 static inline qidx_t
400 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
401 {
402 	qidx_t used;
403 
404 	if (pidx > cidx)
405 		used = pidx - cidx;
406 	else if (pidx < cidx)
407 		used = size - cidx + pidx;
408 	else if (gen == 0 && pidx == cidx)
409 		used = 0;
410 	else if (gen == 1 && pidx == cidx)
411 		used = size;
412 	else
413 		panic("bad state");
414 
415 	return (used);
416 }
417 
418 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
419 
420 #define IDXDIFF(head, tail, wrap) \
421 	((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
422 
423 struct iflib_rxq {
424 	if_ctx_t	ifr_ctx;
425 	iflib_fl_t	ifr_fl;
426 	uint64_t	ifr_rx_irq;
427 	struct pfil_head	*pfil;
428 	/*
429 	 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
430 	 * the command queue consumer index.  Otherwise it's unused.
431 	 */
432 	qidx_t		ifr_cq_cidx;
433 	uint16_t	ifr_id;
434 	uint8_t		ifr_nfl;
435 	uint8_t		ifr_ntxqirq;
436 	uint8_t		ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
437 	uint8_t		ifr_fl_offset;
438 	struct lro_ctrl			ifr_lc;
439 	struct grouptask        ifr_task;
440 	struct callout		ifr_watchdog;
441 	struct iflib_filter_info ifr_filter_info;
442 	iflib_dma_info_t		ifr_ifdi;
443 
444 	/* dynamically allocate if any drivers need a value substantially larger than this */
445 	struct if_rxd_frag	ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
446 #ifdef IFLIB_DIAGNOSTICS
447 	uint64_t ifr_cpu_exec_count[256];
448 #endif
449 }  __aligned(CACHE_LINE_SIZE);
450 
451 typedef struct if_rxsd {
452 	caddr_t *ifsd_cl;
453 	iflib_fl_t ifsd_fl;
454 } *if_rxsd_t;
455 
456 /* multiple of word size */
457 #ifdef __LP64__
458 #define PKT_INFO_SIZE	6
459 #define RXD_INFO_SIZE	5
460 #define PKT_TYPE uint64_t
461 #else
462 #define PKT_INFO_SIZE	11
463 #define RXD_INFO_SIZE	8
464 #define PKT_TYPE uint32_t
465 #endif
466 #define PKT_LOOP_BOUND  ((PKT_INFO_SIZE/3)*3)
467 #define RXD_LOOP_BOUND  ((RXD_INFO_SIZE/4)*4)
468 
469 typedef struct if_pkt_info_pad {
470 	PKT_TYPE pkt_val[PKT_INFO_SIZE];
471 } *if_pkt_info_pad_t;
472 typedef struct if_rxd_info_pad {
473 	PKT_TYPE rxd_val[RXD_INFO_SIZE];
474 } *if_rxd_info_pad_t;
475 
476 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
477 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
478 
479 
480 static inline void
481 pkt_info_zero(if_pkt_info_t pi)
482 {
483 	if_pkt_info_pad_t pi_pad;
484 
485 	pi_pad = (if_pkt_info_pad_t)pi;
486 	pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
487 	pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
488 #ifndef __LP64__
489 	pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
490 	pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
491 #endif
492 }
493 
494 static device_method_t iflib_pseudo_methods[] = {
495 	DEVMETHOD(device_attach, noop_attach),
496 	DEVMETHOD(device_detach, iflib_pseudo_detach),
497 	DEVMETHOD_END
498 };
499 
500 driver_t iflib_pseudodriver = {
501 	"iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
502 };
503 
504 static inline void
505 rxd_info_zero(if_rxd_info_t ri)
506 {
507 	if_rxd_info_pad_t ri_pad;
508 	int i;
509 
510 	ri_pad = (if_rxd_info_pad_t)ri;
511 	for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
512 		ri_pad->rxd_val[i] = 0;
513 		ri_pad->rxd_val[i+1] = 0;
514 		ri_pad->rxd_val[i+2] = 0;
515 		ri_pad->rxd_val[i+3] = 0;
516 	}
517 #ifdef __LP64__
518 	ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
519 #endif
520 }
521 
522 /*
523  * Only allow a single packet to take up most 1/nth of the tx ring
524  */
525 #define MAX_SINGLE_PACKET_FRACTION 12
526 #define IF_BAD_DMA (bus_addr_t)-1
527 
528 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
529 
530 #define CTX_LOCK_INIT(_sc)  sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
531 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
532 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
533 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
534 
535 #define STATE_LOCK_INIT(_sc, _name)  mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
536 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
537 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
538 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
539 
540 #define CALLOUT_LOCK(txq)	mtx_lock(&txq->ift_mtx)
541 #define CALLOUT_UNLOCK(txq) 	mtx_unlock(&txq->ift_mtx)
542 
543 void
544 iflib_set_detach(if_ctx_t ctx)
545 {
546 	STATE_LOCK(ctx);
547 	ctx->ifc_flags |= IFC_IN_DETACH;
548 	STATE_UNLOCK(ctx);
549 }
550 
551 /* Our boot-time initialization hook */
552 static int	iflib_module_event_handler(module_t, int, void *);
553 
554 static moduledata_t iflib_moduledata = {
555 	"iflib",
556 	iflib_module_event_handler,
557 	NULL
558 };
559 
560 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
561 MODULE_VERSION(iflib, 1);
562 
563 MODULE_DEPEND(iflib, pci, 1, 1, 1);
564 MODULE_DEPEND(iflib, ether, 1, 1, 1);
565 
566 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
567 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
568 
569 #ifndef IFLIB_DEBUG_COUNTERS
570 #ifdef INVARIANTS
571 #define IFLIB_DEBUG_COUNTERS 1
572 #else
573 #define IFLIB_DEBUG_COUNTERS 0
574 #endif /* !INVARIANTS */
575 #endif
576 
577 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
578     "iflib driver parameters");
579 
580 /*
581  * XXX need to ensure that this can't accidentally cause the head to be moved backwards
582  */
583 static int iflib_min_tx_latency = 0;
584 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
585 		   &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
586 static int iflib_no_tx_batch = 0;
587 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
588 		   &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
589 
590 
591 #if IFLIB_DEBUG_COUNTERS
592 
593 static int iflib_tx_seen;
594 static int iflib_tx_sent;
595 static int iflib_tx_encap;
596 static int iflib_rx_allocs;
597 static int iflib_fl_refills;
598 static int iflib_fl_refills_large;
599 static int iflib_tx_frees;
600 
601 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
602 		   &iflib_tx_seen, 0, "# TX mbufs seen");
603 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
604 		   &iflib_tx_sent, 0, "# TX mbufs sent");
605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
606 		   &iflib_tx_encap, 0, "# TX mbufs encapped");
607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
608 		   &iflib_tx_frees, 0, "# TX frees");
609 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
610 		   &iflib_rx_allocs, 0, "# RX allocations");
611 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
612 		   &iflib_fl_refills, 0, "# refills");
613 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
614 		   &iflib_fl_refills_large, 0, "# large refills");
615 
616 
617 static int iflib_txq_drain_flushing;
618 static int iflib_txq_drain_oactive;
619 static int iflib_txq_drain_notready;
620 
621 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
622 		   &iflib_txq_drain_flushing, 0, "# drain flushes");
623 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
624 		   &iflib_txq_drain_oactive, 0, "# drain oactives");
625 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
626 		   &iflib_txq_drain_notready, 0, "# drain notready");
627 
628 
629 static int iflib_encap_load_mbuf_fail;
630 static int iflib_encap_pad_mbuf_fail;
631 static int iflib_encap_txq_avail_fail;
632 static int iflib_encap_txd_encap_fail;
633 
634 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
635 		   &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
637 		   &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
638 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
639 		   &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
640 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
641 		   &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
642 
643 static int iflib_task_fn_rxs;
644 static int iflib_rx_intr_enables;
645 static int iflib_fast_intrs;
646 static int iflib_rx_unavail;
647 static int iflib_rx_ctx_inactive;
648 static int iflib_rx_if_input;
649 static int iflib_rxd_flush;
650 
651 static int iflib_verbose_debug;
652 
653 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
654 		   &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
655 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
656 		   &iflib_rx_intr_enables, 0, "# RX intr enables");
657 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
658 		   &iflib_fast_intrs, 0, "# fast_intr calls");
659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
660 		   &iflib_rx_unavail, 0, "# times rxeof called with no available data");
661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
662 		   &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
664 		   &iflib_rx_if_input, 0, "# times rxeof called if_input");
665 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
666 	         &iflib_rxd_flush, 0, "# times rxd_flush called");
667 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
668 		   &iflib_verbose_debug, 0, "enable verbose debugging");
669 
670 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
671 static void
672 iflib_debug_reset(void)
673 {
674 	iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
675 		iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
676 		iflib_txq_drain_flushing = iflib_txq_drain_oactive =
677 		iflib_txq_drain_notready =
678 		iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
679 		iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
680 		iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
681 		iflib_rx_unavail =
682 		iflib_rx_ctx_inactive = iflib_rx_if_input =
683 		iflib_rxd_flush = 0;
684 }
685 
686 #else
687 #define DBG_COUNTER_INC(name)
688 static void iflib_debug_reset(void) {}
689 #endif
690 
691 #define IFLIB_DEBUG 0
692 
693 static void iflib_tx_structures_free(if_ctx_t ctx);
694 static void iflib_rx_structures_free(if_ctx_t ctx);
695 static int iflib_queues_alloc(if_ctx_t ctx);
696 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
697 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
698 static int iflib_qset_structures_setup(if_ctx_t ctx);
699 static int iflib_msix_init(if_ctx_t ctx);
700 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
701 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
702 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
703 #ifdef ALTQ
704 static void iflib_altq_if_start(if_t ifp);
705 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
706 #endif
707 static int iflib_register(if_ctx_t);
708 static void iflib_deregister(if_ctx_t);
709 static void iflib_unregister_vlan_handlers(if_ctx_t ctx);
710 static uint16_t iflib_get_mbuf_size_for(unsigned int size);
711 static void iflib_init_locked(if_ctx_t ctx);
712 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
713 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
714 static void iflib_ifmp_purge(iflib_txq_t txq);
715 static void _iflib_pre_assert(if_softc_ctx_t scctx);
716 static void iflib_if_init_locked(if_ctx_t ctx);
717 static void iflib_free_intr_mem(if_ctx_t ctx);
718 #ifndef __NO_STRICT_ALIGNMENT
719 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
720 #endif
721 
722 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
723     SLIST_HEAD_INITIALIZER(cpu_offsets);
724 struct cpu_offset {
725 	SLIST_ENTRY(cpu_offset) entries;
726 	cpuset_t	set;
727 	unsigned int	refcount;
728 	uint16_t	offset;
729 };
730 static struct mtx cpu_offset_mtx;
731 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
732     MTX_DEF);
733 
734 DEBUGNET_DEFINE(iflib);
735 
736 #ifdef DEV_NETMAP
737 #include <sys/selinfo.h>
738 #include <net/netmap.h>
739 #include <dev/netmap/netmap_kern.h>
740 
741 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
742 
743 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
744 
745 /*
746  * device-specific sysctl variables:
747  *
748  * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
749  *	During regular operations the CRC is stripped, but on some
750  *	hardware reception of frames not multiple of 64 is slower,
751  *	so using crcstrip=0 helps in benchmarks.
752  *
753  * iflib_rx_miss, iflib_rx_miss_bufs:
754  *	count packets that might be missed due to lost interrupts.
755  */
756 SYSCTL_DECL(_dev_netmap);
757 /*
758  * The xl driver by default strips CRCs and we do not override it.
759  */
760 
761 int iflib_crcstrip = 1;
762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
763     CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
764 
765 int iflib_rx_miss, iflib_rx_miss_bufs;
766 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
767     CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
768 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
769     CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
770 
771 /*
772  * Register/unregister. We are already under netmap lock.
773  * Only called on the first register or the last unregister.
774  */
775 static int
776 iflib_netmap_register(struct netmap_adapter *na, int onoff)
777 {
778 	if_t ifp = na->ifp;
779 	if_ctx_t ctx = ifp->if_softc;
780 	int status;
781 
782 	CTX_LOCK(ctx);
783 	IFDI_INTR_DISABLE(ctx);
784 
785 	/* Tell the stack that the interface is no longer active */
786 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
787 
788 	if (!CTX_IS_VF(ctx))
789 		IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
790 
791 	/* enable or disable flags and callbacks in na and ifp */
792 	if (onoff) {
793 		nm_set_native_flags(na);
794 	} else {
795 		nm_clear_native_flags(na);
796 	}
797 	iflib_stop(ctx);
798 	iflib_init_locked(ctx);
799 	IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
800 	status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
801 	if (status)
802 		nm_clear_native_flags(na);
803 	CTX_UNLOCK(ctx);
804 	return (status);
805 }
806 
807 static int
808 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
809 {
810 	struct netmap_adapter *na = kring->na;
811 	u_int const lim = kring->nkr_num_slots - 1;
812 	u_int head = kring->rhead;
813 	struct netmap_ring *ring = kring->ring;
814 	bus_dmamap_t *map;
815 	struct if_rxd_update iru;
816 	if_ctx_t ctx = rxq->ifr_ctx;
817 	iflib_fl_t fl = &rxq->ifr_fl[0];
818 	uint32_t refill_pidx, nic_i;
819 #if IFLIB_DEBUG_COUNTERS
820 	int rf_count = 0;
821 #endif
822 
823 	if (nm_i == head && __predict_true(!init))
824 		return 0;
825 	iru_init(&iru, rxq, 0 /* flid */);
826 	map = fl->ifl_sds.ifsd_map;
827 	refill_pidx = netmap_idx_k2n(kring, nm_i);
828 	/*
829 	 * IMPORTANT: we must leave one free slot in the ring,
830 	 * so move head back by one unit
831 	 */
832 	head = nm_prev(head, lim);
833 	nic_i = UINT_MAX;
834 	DBG_COUNTER_INC(fl_refills);
835 	while (nm_i != head) {
836 #if IFLIB_DEBUG_COUNTERS
837 		if (++rf_count == 9)
838 			DBG_COUNTER_INC(fl_refills_large);
839 #endif
840 		for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
841 			struct netmap_slot *slot = &ring->slot[nm_i];
842 			void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
843 			uint32_t nic_i_dma = refill_pidx;
844 			nic_i = netmap_idx_k2n(kring, nm_i);
845 
846 			MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
847 
848 			if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
849 			        return netmap_ring_reinit(kring);
850 
851 			fl->ifl_vm_addrs[tmp_pidx] = addr;
852 			if (__predict_false(init)) {
853 				netmap_load_map(na, fl->ifl_buf_tag,
854 				    map[nic_i], addr);
855 			} else if (slot->flags & NS_BUF_CHANGED) {
856 				/* buffer has changed, reload map */
857 				netmap_reload_map(na, fl->ifl_buf_tag,
858 				    map[nic_i], addr);
859 			}
860 			slot->flags &= ~NS_BUF_CHANGED;
861 
862 			nm_i = nm_next(nm_i, lim);
863 			fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
864 			if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
865 				continue;
866 
867 			iru.iru_pidx = refill_pidx;
868 			iru.iru_count = tmp_pidx+1;
869 			ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
870 			refill_pidx = nic_i;
871 			for (int n = 0; n < iru.iru_count; n++) {
872 				bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma],
873 						BUS_DMASYNC_PREREAD);
874 				/* XXX - change this to not use the netmap func*/
875 				nic_i_dma = nm_next(nic_i_dma, lim);
876 			}
877 		}
878 	}
879 	kring->nr_hwcur = head;
880 
881 	bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
882 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
883 	if (__predict_true(nic_i != UINT_MAX)) {
884 		ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
885 		DBG_COUNTER_INC(rxd_flush);
886 	}
887 	return (0);
888 }
889 
890 /*
891  * Reconcile kernel and user view of the transmit ring.
892  *
893  * All information is in the kring.
894  * Userspace wants to send packets up to the one before kring->rhead,
895  * kernel knows kring->nr_hwcur is the first unsent packet.
896  *
897  * Here we push packets out (as many as possible), and possibly
898  * reclaim buffers from previously completed transmission.
899  *
900  * The caller (netmap) guarantees that there is only one instance
901  * running at any time. Any interference with other driver
902  * methods should be handled by the individual drivers.
903  */
904 static int
905 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
906 {
907 	struct netmap_adapter *na = kring->na;
908 	if_t ifp = na->ifp;
909 	struct netmap_ring *ring = kring->ring;
910 	u_int nm_i;	/* index into the netmap kring */
911 	u_int nic_i;	/* index into the NIC ring */
912 	u_int n;
913 	u_int const lim = kring->nkr_num_slots - 1;
914 	u_int const head = kring->rhead;
915 	struct if_pkt_info pi;
916 
917 	/*
918 	 * interrupts on every tx packet are expensive so request
919 	 * them every half ring, or where NS_REPORT is set
920 	 */
921 	u_int report_frequency = kring->nkr_num_slots >> 1;
922 	/* device-specific */
923 	if_ctx_t ctx = ifp->if_softc;
924 	iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
925 
926 	bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
927 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
928 
929 	/*
930 	 * First part: process new packets to send.
931 	 * nm_i is the current index in the netmap kring,
932 	 * nic_i is the corresponding index in the NIC ring.
933 	 *
934 	 * If we have packets to send (nm_i != head)
935 	 * iterate over the netmap ring, fetch length and update
936 	 * the corresponding slot in the NIC ring. Some drivers also
937 	 * need to update the buffer's physical address in the NIC slot
938 	 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
939 	 *
940 	 * The netmap_reload_map() calls is especially expensive,
941 	 * even when (as in this case) the tag is 0, so do only
942 	 * when the buffer has actually changed.
943 	 *
944 	 * If possible do not set the report/intr bit on all slots,
945 	 * but only a few times per ring or when NS_REPORT is set.
946 	 *
947 	 * Finally, on 10G and faster drivers, it might be useful
948 	 * to prefetch the next slot and txr entry.
949 	 */
950 
951 	nm_i = kring->nr_hwcur;
952 	if (nm_i != head) {	/* we have new packets to send */
953 		pkt_info_zero(&pi);
954 		pi.ipi_segs = txq->ift_segs;
955 		pi.ipi_qsidx = kring->ring_id;
956 		nic_i = netmap_idx_k2n(kring, nm_i);
957 
958 		__builtin_prefetch(&ring->slot[nm_i]);
959 		__builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
960 		__builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
961 
962 		for (n = 0; nm_i != head; n++) {
963 			struct netmap_slot *slot = &ring->slot[nm_i];
964 			u_int len = slot->len;
965 			uint64_t paddr;
966 			void *addr = PNMB(na, slot, &paddr);
967 			int flags = (slot->flags & NS_REPORT ||
968 				nic_i == 0 || nic_i == report_frequency) ?
969 				IPI_TX_INTR : 0;
970 
971 			/* device-specific */
972 			pi.ipi_len = len;
973 			pi.ipi_segs[0].ds_addr = paddr;
974 			pi.ipi_segs[0].ds_len = len;
975 			pi.ipi_nsegs = 1;
976 			pi.ipi_ndescs = 0;
977 			pi.ipi_pidx = nic_i;
978 			pi.ipi_flags = flags;
979 
980 			/* Fill the slot in the NIC ring. */
981 			ctx->isc_txd_encap(ctx->ifc_softc, &pi);
982 			DBG_COUNTER_INC(tx_encap);
983 
984 			/* prefetch for next round */
985 			__builtin_prefetch(&ring->slot[nm_i + 1]);
986 			__builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
987 			__builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
988 
989 			NM_CHECK_ADDR_LEN(na, addr, len);
990 
991 			if (slot->flags & NS_BUF_CHANGED) {
992 				/* buffer has changed, reload map */
993 				netmap_reload_map(na, txq->ift_buf_tag,
994 				    txq->ift_sds.ifsd_map[nic_i], addr);
995 			}
996 			/* make sure changes to the buffer are synced */
997 			bus_dmamap_sync(txq->ift_buf_tag,
998 			    txq->ift_sds.ifsd_map[nic_i],
999 			    BUS_DMASYNC_PREWRITE);
1000 
1001 			slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1002 			nm_i = nm_next(nm_i, lim);
1003 			nic_i = nm_next(nic_i, lim);
1004 		}
1005 		kring->nr_hwcur = nm_i;
1006 
1007 		/* synchronize the NIC ring */
1008 		bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1009 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1010 
1011 		/* (re)start the tx unit up to slot nic_i (excluded) */
1012 		ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1013 	}
1014 
1015 	/*
1016 	 * Second part: reclaim buffers for completed transmissions.
1017 	 *
1018 	 * If there are unclaimed buffers, attempt to reclaim them.
1019 	 * If none are reclaimed, and TX IRQs are not in use, do an initial
1020 	 * minimal delay, then trigger the tx handler which will spin in the
1021 	 * group task queue.
1022 	 */
1023 	if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1024 		if (iflib_tx_credits_update(ctx, txq)) {
1025 			/* some tx completed, increment avail */
1026 			nic_i = txq->ift_cidx_processed;
1027 			kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1028 		}
1029 	}
1030 	if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1031 		if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1032 			callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1033 			    iflib_timer, txq, txq->ift_timer.c_cpu);
1034 	}
1035 	return (0);
1036 }
1037 
1038 /*
1039  * Reconcile kernel and user view of the receive ring.
1040  * Same as for the txsync, this routine must be efficient.
1041  * The caller guarantees a single invocations, but races against
1042  * the rest of the driver should be handled here.
1043  *
1044  * On call, kring->rhead is the first packet that userspace wants
1045  * to keep, and kring->rcur is the wakeup point.
1046  * The kernel has previously reported packets up to kring->rtail.
1047  *
1048  * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1049  * of whether or not we received an interrupt.
1050  */
1051 static int
1052 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1053 {
1054 	struct netmap_adapter *na = kring->na;
1055 	struct netmap_ring *ring = kring->ring;
1056 	if_t ifp = na->ifp;
1057 	iflib_fl_t fl;
1058 	uint32_t nm_i;	/* index into the netmap ring */
1059 	uint32_t nic_i;	/* index into the NIC ring */
1060 	u_int i, n;
1061 	u_int const lim = kring->nkr_num_slots - 1;
1062 	u_int const head = kring->rhead;
1063 	int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1064 	struct if_rxd_info ri;
1065 
1066 	if_ctx_t ctx = ifp->if_softc;
1067 	iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1068 	if (head > lim)
1069 		return netmap_ring_reinit(kring);
1070 
1071 	/*
1072 	 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far.
1073 	 */
1074 
1075 	for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) {
1076 		bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1077 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1078 	}
1079 
1080 	/*
1081 	 * First part: import newly received packets.
1082 	 *
1083 	 * nm_i is the index of the next free slot in the netmap ring,
1084 	 * nic_i is the index of the next received packet in the NIC ring,
1085 	 * and they may differ in case if_init() has been called while
1086 	 * in netmap mode. For the receive ring we have
1087 	 *
1088 	 *	nic_i = rxr->next_check;
1089 	 *	nm_i = kring->nr_hwtail (previous)
1090 	 * and
1091 	 *	nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1092 	 *
1093 	 * rxr->next_check is set to 0 on a ring reinit
1094 	 */
1095 	if (netmap_no_pendintr || force_update) {
1096 		int crclen = iflib_crcstrip ? 0 : 4;
1097 		int error, avail;
1098 
1099 		for (i = 0; i < rxq->ifr_nfl; i++) {
1100 			fl = &rxq->ifr_fl[i];
1101 			nic_i = fl->ifl_cidx;
1102 			nm_i = netmap_idx_n2k(kring, nic_i);
1103 			avail = ctx->isc_rxd_available(ctx->ifc_softc,
1104 			    rxq->ifr_id, nic_i, USHRT_MAX);
1105 			for (n = 0; avail > 0; n++, avail--) {
1106 				rxd_info_zero(&ri);
1107 				ri.iri_frags = rxq->ifr_frags;
1108 				ri.iri_qsidx = kring->ring_id;
1109 				ri.iri_ifp = ctx->ifc_ifp;
1110 				ri.iri_cidx = nic_i;
1111 
1112 				error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1113 				ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1114 				ring->slot[nm_i].flags = 0;
1115 				bus_dmamap_sync(fl->ifl_buf_tag,
1116 				    fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1117 				nm_i = nm_next(nm_i, lim);
1118 				nic_i = nm_next(nic_i, lim);
1119 			}
1120 			if (n) { /* update the state variables */
1121 				if (netmap_no_pendintr && !force_update) {
1122 					/* diagnostics */
1123 					iflib_rx_miss ++;
1124 					iflib_rx_miss_bufs += n;
1125 				}
1126 				fl->ifl_cidx = nic_i;
1127 				kring->nr_hwtail = nm_i;
1128 			}
1129 			kring->nr_kflags &= ~NKR_PENDINTR;
1130 		}
1131 	}
1132 	/*
1133 	 * Second part: skip past packets that userspace has released.
1134 	 * (kring->nr_hwcur to head excluded),
1135 	 * and make the buffers available for reception.
1136 	 * As usual nm_i is the index in the netmap ring,
1137 	 * nic_i is the index in the NIC ring, and
1138 	 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1139 	 */
1140 	/* XXX not sure how this will work with multiple free lists */
1141 	nm_i = kring->nr_hwcur;
1142 
1143 	return (netmap_fl_refill(rxq, kring, nm_i, false));
1144 }
1145 
1146 static void
1147 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1148 {
1149 	if_ctx_t ctx = na->ifp->if_softc;
1150 
1151 	CTX_LOCK(ctx);
1152 	if (onoff) {
1153 		IFDI_INTR_ENABLE(ctx);
1154 	} else {
1155 		IFDI_INTR_DISABLE(ctx);
1156 	}
1157 	CTX_UNLOCK(ctx);
1158 }
1159 
1160 
1161 static int
1162 iflib_netmap_attach(if_ctx_t ctx)
1163 {
1164 	struct netmap_adapter na;
1165 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1166 
1167 	bzero(&na, sizeof(na));
1168 
1169 	na.ifp = ctx->ifc_ifp;
1170 	na.na_flags = NAF_BDG_MAYSLEEP;
1171 	MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1172 	MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1173 
1174 	na.num_tx_desc = scctx->isc_ntxd[0];
1175 	na.num_rx_desc = scctx->isc_nrxd[0];
1176 	na.nm_txsync = iflib_netmap_txsync;
1177 	na.nm_rxsync = iflib_netmap_rxsync;
1178 	na.nm_register = iflib_netmap_register;
1179 	na.nm_intr = iflib_netmap_intr;
1180 	na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1181 	na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1182 	return (netmap_attach(&na));
1183 }
1184 
1185 static void
1186 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1187 {
1188 	struct netmap_adapter *na = NA(ctx->ifc_ifp);
1189 	struct netmap_slot *slot;
1190 
1191 	slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1192 	if (slot == NULL)
1193 		return;
1194 	for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1195 
1196 		/*
1197 		 * In netmap mode, set the map for the packet buffer.
1198 		 * NOTE: Some drivers (not this one) also need to set
1199 		 * the physical buffer address in the NIC ring.
1200 		 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1201 		 * netmap slot index, si
1202 		 */
1203 		int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1204 		netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1205 		    NMB(na, slot + si));
1206 	}
1207 }
1208 
1209 static void
1210 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1211 {
1212 	struct netmap_adapter *na = NA(ctx->ifc_ifp);
1213 	struct netmap_kring *kring = na->rx_rings[rxq->ifr_id];
1214 	struct netmap_slot *slot;
1215 	uint32_t nm_i;
1216 
1217 	slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1218 	if (slot == NULL)
1219 		return;
1220 	nm_i = netmap_idx_n2k(kring, 0);
1221 	netmap_fl_refill(rxq, kring, nm_i, true);
1222 }
1223 
1224 static void
1225 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on)
1226 {
1227 	struct netmap_kring *kring;
1228 	uint16_t txqid;
1229 
1230 	txqid = txq->ift_id;
1231 	kring = NA(ctx->ifc_ifp)->tx_rings[txqid];
1232 
1233 	if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1234 		bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1235 		    BUS_DMASYNC_POSTREAD);
1236 		if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1237 			netmap_tx_irq(ctx->ifc_ifp, txqid);
1238 		if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1239 			if (hz < 2000)
1240 				*reset_on = 1;
1241 			else
1242 				*reset_on = hz / 1000;
1243 		}
1244 	}
1245 }
1246 
1247 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1248 
1249 #else
1250 #define iflib_netmap_txq_init(ctx, txq)
1251 #define iflib_netmap_rxq_init(ctx, rxq)
1252 #define iflib_netmap_detach(ifp)
1253 
1254 #define iflib_netmap_attach(ctx) (0)
1255 #define netmap_rx_irq(ifp, qid, budget) (0)
1256 #define netmap_tx_irq(ifp, qid) do {} while (0)
1257 #define iflib_netmap_timer_adjust(ctx, txq, reset_on)
1258 #endif
1259 
1260 #if defined(__i386__) || defined(__amd64__)
1261 static __inline void
1262 prefetch(void *x)
1263 {
1264 	__asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1265 }
1266 static __inline void
1267 prefetch2cachelines(void *x)
1268 {
1269 	__asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1270 #if (CACHE_LINE_SIZE < 128)
1271 	__asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1272 #endif
1273 }
1274 #else
1275 #define prefetch(x)
1276 #define prefetch2cachelines(x)
1277 #endif
1278 
1279 static void
1280 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1281 {
1282 	iflib_fl_t fl;
1283 
1284 	fl = &rxq->ifr_fl[flid];
1285 	iru->iru_paddrs = fl->ifl_bus_addrs;
1286 	iru->iru_vaddrs = &fl->ifl_vm_addrs[0];
1287 	iru->iru_idxs = fl->ifl_rxd_idxs;
1288 	iru->iru_qsidx = rxq->ifr_id;
1289 	iru->iru_buf_size = fl->ifl_buf_size;
1290 	iru->iru_flidx = fl->ifl_id;
1291 }
1292 
1293 static void
1294 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1295 {
1296 	if (err)
1297 		return;
1298 	*(bus_addr_t *) arg = segs[0].ds_addr;
1299 }
1300 
1301 int
1302 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1303 {
1304 	int err;
1305 	device_t dev = ctx->ifc_dev;
1306 
1307 	err = bus_dma_tag_create(bus_get_dma_tag(dev),	/* parent */
1308 				align, 0,		/* alignment, bounds */
1309 				BUS_SPACE_MAXADDR,	/* lowaddr */
1310 				BUS_SPACE_MAXADDR,	/* highaddr */
1311 				NULL, NULL,		/* filter, filterarg */
1312 				size,			/* maxsize */
1313 				1,			/* nsegments */
1314 				size,			/* maxsegsize */
1315 				BUS_DMA_ALLOCNOW,	/* flags */
1316 				NULL,			/* lockfunc */
1317 				NULL,			/* lockarg */
1318 				&dma->idi_tag);
1319 	if (err) {
1320 		device_printf(dev,
1321 		    "%s: bus_dma_tag_create failed: %d\n",
1322 		    __func__, err);
1323 		goto fail_0;
1324 	}
1325 
1326 	err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1327 	    BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1328 	if (err) {
1329 		device_printf(dev,
1330 		    "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1331 		    __func__, (uintmax_t)size, err);
1332 		goto fail_1;
1333 	}
1334 
1335 	dma->idi_paddr = IF_BAD_DMA;
1336 	err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1337 	    size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1338 	if (err || dma->idi_paddr == IF_BAD_DMA) {
1339 		device_printf(dev,
1340 		    "%s: bus_dmamap_load failed: %d\n",
1341 		    __func__, err);
1342 		goto fail_2;
1343 	}
1344 
1345 	dma->idi_size = size;
1346 	return (0);
1347 
1348 fail_2:
1349 	bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1350 fail_1:
1351 	bus_dma_tag_destroy(dma->idi_tag);
1352 fail_0:
1353 	dma->idi_tag = NULL;
1354 
1355 	return (err);
1356 }
1357 
1358 int
1359 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1360 {
1361 	if_shared_ctx_t sctx = ctx->ifc_sctx;
1362 
1363 	KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1364 
1365 	return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1366 }
1367 
1368 int
1369 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1370 {
1371 	int i, err;
1372 	iflib_dma_info_t *dmaiter;
1373 
1374 	dmaiter = dmalist;
1375 	for (i = 0; i < count; i++, dmaiter++) {
1376 		if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1377 			break;
1378 	}
1379 	if (err)
1380 		iflib_dma_free_multi(dmalist, i);
1381 	return (err);
1382 }
1383 
1384 void
1385 iflib_dma_free(iflib_dma_info_t dma)
1386 {
1387 	if (dma->idi_tag == NULL)
1388 		return;
1389 	if (dma->idi_paddr != IF_BAD_DMA) {
1390 		bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1391 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1392 		bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1393 		dma->idi_paddr = IF_BAD_DMA;
1394 	}
1395 	if (dma->idi_vaddr != NULL) {
1396 		bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1397 		dma->idi_vaddr = NULL;
1398 	}
1399 	bus_dma_tag_destroy(dma->idi_tag);
1400 	dma->idi_tag = NULL;
1401 }
1402 
1403 void
1404 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1405 {
1406 	int i;
1407 	iflib_dma_info_t *dmaiter = dmalist;
1408 
1409 	for (i = 0; i < count; i++, dmaiter++)
1410 		iflib_dma_free(*dmaiter);
1411 }
1412 
1413 #ifdef EARLY_AP_STARTUP
1414 static const int iflib_started = 1;
1415 #else
1416 /*
1417  * We used to abuse the smp_started flag to decide if the queues have been
1418  * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()).
1419  * That gave bad races, since the SYSINIT() runs strictly after smp_started
1420  * is set.  Run a SYSINIT() strictly after that to just set a usable
1421  * completion flag.
1422  */
1423 
1424 static int iflib_started;
1425 
1426 static void
1427 iflib_record_started(void *arg)
1428 {
1429 	iflib_started = 1;
1430 }
1431 
1432 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST,
1433 	iflib_record_started, NULL);
1434 #endif
1435 
1436 static int
1437 iflib_fast_intr(void *arg)
1438 {
1439 	iflib_filter_info_t info = arg;
1440 	struct grouptask *gtask = info->ifi_task;
1441 	int result;
1442 
1443 	if (!iflib_started)
1444 		return (FILTER_STRAY);
1445 
1446 	DBG_COUNTER_INC(fast_intrs);
1447 	if (info->ifi_filter != NULL) {
1448 		result = info->ifi_filter(info->ifi_filter_arg);
1449 		if ((result & FILTER_SCHEDULE_THREAD) == 0)
1450 			return (result);
1451 	}
1452 
1453 	GROUPTASK_ENQUEUE(gtask);
1454 	return (FILTER_HANDLED);
1455 }
1456 
1457 static int
1458 iflib_fast_intr_rxtx(void *arg)
1459 {
1460 	iflib_filter_info_t info = arg;
1461 	struct grouptask *gtask = info->ifi_task;
1462 	if_ctx_t ctx;
1463 	iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1464 	iflib_txq_t txq;
1465 	void *sc;
1466 	int i, cidx, result;
1467 	qidx_t txqid;
1468 	bool intr_enable, intr_legacy;
1469 
1470 	if (!iflib_started)
1471 		return (FILTER_STRAY);
1472 
1473 	DBG_COUNTER_INC(fast_intrs);
1474 	if (info->ifi_filter != NULL) {
1475 		result = info->ifi_filter(info->ifi_filter_arg);
1476 		if ((result & FILTER_SCHEDULE_THREAD) == 0)
1477 			return (result);
1478 	}
1479 
1480 	ctx = rxq->ifr_ctx;
1481 	sc = ctx->ifc_softc;
1482 	intr_enable = false;
1483 	intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1484 	MPASS(rxq->ifr_ntxqirq);
1485 	for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1486 		txqid = rxq->ifr_txqid[i];
1487 		txq = &ctx->ifc_txqs[txqid];
1488 		bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1489 		    BUS_DMASYNC_POSTREAD);
1490 		if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1491 			if (intr_legacy)
1492 				intr_enable = true;
1493 			else
1494 				IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1495 			continue;
1496 		}
1497 		GROUPTASK_ENQUEUE(&txq->ift_task);
1498 	}
1499 	if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1500 		cidx = rxq->ifr_cq_cidx;
1501 	else
1502 		cidx = rxq->ifr_fl[0].ifl_cidx;
1503 	if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1504 		GROUPTASK_ENQUEUE(gtask);
1505 	else {
1506 		if (intr_legacy)
1507 			intr_enable = true;
1508 		else
1509 			IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1510 		DBG_COUNTER_INC(rx_intr_enables);
1511 	}
1512 	if (intr_enable)
1513 		IFDI_INTR_ENABLE(ctx);
1514 	return (FILTER_HANDLED);
1515 }
1516 
1517 
1518 static int
1519 iflib_fast_intr_ctx(void *arg)
1520 {
1521 	iflib_filter_info_t info = arg;
1522 	struct grouptask *gtask = info->ifi_task;
1523 	int result;
1524 
1525 	if (!iflib_started)
1526 		return (FILTER_STRAY);
1527 
1528 	DBG_COUNTER_INC(fast_intrs);
1529 	if (info->ifi_filter != NULL) {
1530 		result = info->ifi_filter(info->ifi_filter_arg);
1531 		if ((result & FILTER_SCHEDULE_THREAD) == 0)
1532 			return (result);
1533 	}
1534 
1535 	GROUPTASK_ENQUEUE(gtask);
1536 	return (FILTER_HANDLED);
1537 }
1538 
1539 static int
1540 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1541 		 driver_filter_t filter, driver_intr_t handler, void *arg,
1542 		 const char *name)
1543 {
1544 	struct resource *res;
1545 	void *tag = NULL;
1546 	device_t dev = ctx->ifc_dev;
1547 	int flags, i, rc;
1548 
1549 	flags = RF_ACTIVE;
1550 	if (ctx->ifc_flags & IFC_LEGACY)
1551 		flags |= RF_SHAREABLE;
1552 	MPASS(rid < 512);
1553 	i = rid;
1554 	res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags);
1555 	if (res == NULL) {
1556 		device_printf(dev,
1557 		    "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1558 		return (ENOMEM);
1559 	}
1560 	irq->ii_res = res;
1561 	KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1562 	rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1563 						filter, handler, arg, &tag);
1564 	if (rc != 0) {
1565 		device_printf(dev,
1566 		    "failed to setup interrupt for rid %d, name %s: %d\n",
1567 					  rid, name ? name : "unknown", rc);
1568 		return (rc);
1569 	} else if (name)
1570 		bus_describe_intr(dev, res, tag, "%s", name);
1571 
1572 	irq->ii_tag = tag;
1573 	return (0);
1574 }
1575 
1576 /*********************************************************************
1577  *
1578  *  Allocate DMA resources for TX buffers as well as memory for the TX
1579  *  mbuf map.  TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1580  *  iflib_sw_tx_desc_array structure, storing all the information that
1581  *  is needed to transmit a packet on the wire.  This is called only
1582  *  once at attach, setup is done every reset.
1583  *
1584  **********************************************************************/
1585 static int
1586 iflib_txsd_alloc(iflib_txq_t txq)
1587 {
1588 	if_ctx_t ctx = txq->ift_ctx;
1589 	if_shared_ctx_t sctx = ctx->ifc_sctx;
1590 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1591 	device_t dev = ctx->ifc_dev;
1592 	bus_size_t tsomaxsize;
1593 	int err, nsegments, ntsosegments;
1594 	bool tso;
1595 
1596 	nsegments = scctx->isc_tx_nsegments;
1597 	ntsosegments = scctx->isc_tx_tso_segments_max;
1598 	tsomaxsize = scctx->isc_tx_tso_size_max;
1599 	if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1600 		tsomaxsize += sizeof(struct ether_vlan_header);
1601 	MPASS(scctx->isc_ntxd[0] > 0);
1602 	MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1603 	MPASS(nsegments > 0);
1604 	if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1605 		MPASS(ntsosegments > 0);
1606 		MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1607 	}
1608 
1609 	/*
1610 	 * Set up DMA tags for TX buffers.
1611 	 */
1612 	if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1613 			       1, 0,			/* alignment, bounds */
1614 			       BUS_SPACE_MAXADDR,	/* lowaddr */
1615 			       BUS_SPACE_MAXADDR,	/* highaddr */
1616 			       NULL, NULL,		/* filter, filterarg */
1617 			       sctx->isc_tx_maxsize,		/* maxsize */
1618 			       nsegments,	/* nsegments */
1619 			       sctx->isc_tx_maxsegsize,	/* maxsegsize */
1620 			       0,			/* flags */
1621 			       NULL,			/* lockfunc */
1622 			       NULL,			/* lockfuncarg */
1623 			       &txq->ift_buf_tag))) {
1624 		device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1625 		device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1626 		    (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1627 		goto fail;
1628 	}
1629 	tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1630 	if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1631 			       1, 0,			/* alignment, bounds */
1632 			       BUS_SPACE_MAXADDR,	/* lowaddr */
1633 			       BUS_SPACE_MAXADDR,	/* highaddr */
1634 			       NULL, NULL,		/* filter, filterarg */
1635 			       tsomaxsize,		/* maxsize */
1636 			       ntsosegments,	/* nsegments */
1637 			       sctx->isc_tso_maxsegsize,/* maxsegsize */
1638 			       0,			/* flags */
1639 			       NULL,			/* lockfunc */
1640 			       NULL,			/* lockfuncarg */
1641 			       &txq->ift_tso_buf_tag))) {
1642 		device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1643 		    err);
1644 		goto fail;
1645 	}
1646 
1647 	/* Allocate memory for the TX mbuf map. */
1648 	if (!(txq->ift_sds.ifsd_m =
1649 	    (struct mbuf **) malloc(sizeof(struct mbuf *) *
1650 	    scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1651 		device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1652 		err = ENOMEM;
1653 		goto fail;
1654 	}
1655 
1656 	/*
1657 	 * Create the DMA maps for TX buffers.
1658 	 */
1659 	if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1660 	    sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1661 	    M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1662 		device_printf(dev,
1663 		    "Unable to allocate TX buffer DMA map memory\n");
1664 		err = ENOMEM;
1665 		goto fail;
1666 	}
1667 	if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1668 	    sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1669 	    M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1670 		device_printf(dev,
1671 		    "Unable to allocate TSO TX buffer map memory\n");
1672 		err = ENOMEM;
1673 		goto fail;
1674 	}
1675 	for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1676 		err = bus_dmamap_create(txq->ift_buf_tag, 0,
1677 		    &txq->ift_sds.ifsd_map[i]);
1678 		if (err != 0) {
1679 			device_printf(dev, "Unable to create TX DMA map\n");
1680 			goto fail;
1681 		}
1682 		if (!tso)
1683 			continue;
1684 		err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1685 		    &txq->ift_sds.ifsd_tso_map[i]);
1686 		if (err != 0) {
1687 			device_printf(dev, "Unable to create TSO TX DMA map\n");
1688 			goto fail;
1689 		}
1690 	}
1691 	return (0);
1692 fail:
1693 	/* We free all, it handles case where we are in the middle */
1694 	iflib_tx_structures_free(ctx);
1695 	return (err);
1696 }
1697 
1698 static void
1699 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1700 {
1701 	bus_dmamap_t map;
1702 
1703 	if (txq->ift_sds.ifsd_map != NULL) {
1704 		map = txq->ift_sds.ifsd_map[i];
1705 		bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1706 		bus_dmamap_unload(txq->ift_buf_tag, map);
1707 		bus_dmamap_destroy(txq->ift_buf_tag, map);
1708 		txq->ift_sds.ifsd_map[i] = NULL;
1709 	}
1710 
1711 	if (txq->ift_sds.ifsd_tso_map != NULL) {
1712 		map = txq->ift_sds.ifsd_tso_map[i];
1713 		bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1714 		    BUS_DMASYNC_POSTWRITE);
1715 		bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1716 		bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1717 		txq->ift_sds.ifsd_tso_map[i] = NULL;
1718 	}
1719 }
1720 
1721 static void
1722 iflib_txq_destroy(iflib_txq_t txq)
1723 {
1724 	if_ctx_t ctx = txq->ift_ctx;
1725 
1726 	for (int i = 0; i < txq->ift_size; i++)
1727 		iflib_txsd_destroy(ctx, txq, i);
1728 
1729 	if (txq->ift_br != NULL) {
1730 		ifmp_ring_free(txq->ift_br);
1731 		txq->ift_br = NULL;
1732 	}
1733 
1734 	mtx_destroy(&txq->ift_mtx);
1735 
1736 	if (txq->ift_sds.ifsd_map != NULL) {
1737 		free(txq->ift_sds.ifsd_map, M_IFLIB);
1738 		txq->ift_sds.ifsd_map = NULL;
1739 	}
1740 	if (txq->ift_sds.ifsd_tso_map != NULL) {
1741 		free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1742 		txq->ift_sds.ifsd_tso_map = NULL;
1743 	}
1744 	if (txq->ift_sds.ifsd_m != NULL) {
1745 		free(txq->ift_sds.ifsd_m, M_IFLIB);
1746 		txq->ift_sds.ifsd_m = NULL;
1747 	}
1748 	if (txq->ift_buf_tag != NULL) {
1749 		bus_dma_tag_destroy(txq->ift_buf_tag);
1750 		txq->ift_buf_tag = NULL;
1751 	}
1752 	if (txq->ift_tso_buf_tag != NULL) {
1753 		bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1754 		txq->ift_tso_buf_tag = NULL;
1755 	}
1756 	if (txq->ift_ifdi != NULL) {
1757 		free(txq->ift_ifdi, M_IFLIB);
1758 	}
1759 }
1760 
1761 static void
1762 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1763 {
1764 	struct mbuf **mp;
1765 
1766 	mp = &txq->ift_sds.ifsd_m[i];
1767 	if (*mp == NULL)
1768 		return;
1769 
1770 	if (txq->ift_sds.ifsd_map != NULL) {
1771 		bus_dmamap_sync(txq->ift_buf_tag,
1772 		    txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1773 		bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1774 	}
1775 	if (txq->ift_sds.ifsd_tso_map != NULL) {
1776 		bus_dmamap_sync(txq->ift_tso_buf_tag,
1777 		    txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1778 		bus_dmamap_unload(txq->ift_tso_buf_tag,
1779 		    txq->ift_sds.ifsd_tso_map[i]);
1780 	}
1781 	m_free(*mp);
1782 	DBG_COUNTER_INC(tx_frees);
1783 	*mp = NULL;
1784 }
1785 
1786 static int
1787 iflib_txq_setup(iflib_txq_t txq)
1788 {
1789 	if_ctx_t ctx = txq->ift_ctx;
1790 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1791 	if_shared_ctx_t sctx = ctx->ifc_sctx;
1792 	iflib_dma_info_t di;
1793 	int i;
1794 
1795 	/* Set number of descriptors available */
1796 	txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1797 	/* XXX make configurable */
1798 	txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1799 
1800 	/* Reset indices */
1801 	txq->ift_cidx_processed = 0;
1802 	txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1803 	txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1804 
1805 	for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1806 		bzero((void *)di->idi_vaddr, di->idi_size);
1807 
1808 	IFDI_TXQ_SETUP(ctx, txq->ift_id);
1809 	for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1810 		bus_dmamap_sync(di->idi_tag, di->idi_map,
1811 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1812 	return (0);
1813 }
1814 
1815 /*********************************************************************
1816  *
1817  *  Allocate DMA resources for RX buffers as well as memory for the RX
1818  *  mbuf map, direct RX cluster pointer map and RX cluster bus address
1819  *  map.  RX DMA map, RX mbuf map, direct RX cluster pointer map and
1820  *  RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1821  *  Since we use use one entry in iflib_sw_rx_desc_array per received
1822  *  packet, the maximum number of entries we'll need is equal to the
1823  *  number of hardware receive descriptors that we've allocated.
1824  *
1825  **********************************************************************/
1826 static int
1827 iflib_rxsd_alloc(iflib_rxq_t rxq)
1828 {
1829 	if_ctx_t ctx = rxq->ifr_ctx;
1830 	if_shared_ctx_t sctx = ctx->ifc_sctx;
1831 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1832 	device_t dev = ctx->ifc_dev;
1833 	iflib_fl_t fl;
1834 	int			err;
1835 
1836 	MPASS(scctx->isc_nrxd[0] > 0);
1837 	MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1838 
1839 	fl = rxq->ifr_fl;
1840 	for (int i = 0; i <  rxq->ifr_nfl; i++, fl++) {
1841 		fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1842 		/* Set up DMA tag for RX buffers. */
1843 		err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1844 					 1, 0,			/* alignment, bounds */
1845 					 BUS_SPACE_MAXADDR,	/* lowaddr */
1846 					 BUS_SPACE_MAXADDR,	/* highaddr */
1847 					 NULL, NULL,		/* filter, filterarg */
1848 					 sctx->isc_rx_maxsize,	/* maxsize */
1849 					 sctx->isc_rx_nsegments,	/* nsegments */
1850 					 sctx->isc_rx_maxsegsize,	/* maxsegsize */
1851 					 0,			/* flags */
1852 					 NULL,			/* lockfunc */
1853 					 NULL,			/* lockarg */
1854 					 &fl->ifl_buf_tag);
1855 		if (err) {
1856 			device_printf(dev,
1857 			    "Unable to allocate RX DMA tag: %d\n", err);
1858 			goto fail;
1859 		}
1860 
1861 		/* Allocate memory for the RX mbuf map. */
1862 		if (!(fl->ifl_sds.ifsd_m =
1863 		      (struct mbuf **) malloc(sizeof(struct mbuf *) *
1864 					      scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1865 			device_printf(dev,
1866 			    "Unable to allocate RX mbuf map memory\n");
1867 			err = ENOMEM;
1868 			goto fail;
1869 		}
1870 
1871 		/* Allocate memory for the direct RX cluster pointer map. */
1872 		if (!(fl->ifl_sds.ifsd_cl =
1873 		      (caddr_t *) malloc(sizeof(caddr_t) *
1874 					      scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1875 			device_printf(dev,
1876 			    "Unable to allocate RX cluster map memory\n");
1877 			err = ENOMEM;
1878 			goto fail;
1879 		}
1880 
1881 		/* Allocate memory for the RX cluster bus address map. */
1882 		if (!(fl->ifl_sds.ifsd_ba =
1883 		      (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1884 					      scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1885 			device_printf(dev,
1886 			    "Unable to allocate RX bus address map memory\n");
1887 			err = ENOMEM;
1888 			goto fail;
1889 		}
1890 
1891 		/*
1892 		 * Create the DMA maps for RX buffers.
1893 		 */
1894 		if (!(fl->ifl_sds.ifsd_map =
1895 		      (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1896 			device_printf(dev,
1897 			    "Unable to allocate RX buffer DMA map memory\n");
1898 			err = ENOMEM;
1899 			goto fail;
1900 		}
1901 		for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1902 			err = bus_dmamap_create(fl->ifl_buf_tag, 0,
1903 			    &fl->ifl_sds.ifsd_map[i]);
1904 			if (err != 0) {
1905 				device_printf(dev, "Unable to create RX buffer DMA map\n");
1906 				goto fail;
1907 			}
1908 		}
1909 	}
1910 	return (0);
1911 
1912 fail:
1913 	iflib_rx_structures_free(ctx);
1914 	return (err);
1915 }
1916 
1917 
1918 /*
1919  * Internal service routines
1920  */
1921 
1922 struct rxq_refill_cb_arg {
1923 	int               error;
1924 	bus_dma_segment_t seg;
1925 	int               nseg;
1926 };
1927 
1928 static void
1929 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1930 {
1931 	struct rxq_refill_cb_arg *cb_arg = arg;
1932 
1933 	cb_arg->error = error;
1934 	cb_arg->seg = segs[0];
1935 	cb_arg->nseg = nseg;
1936 }
1937 
1938 /**
1939  * _iflib_fl_refill - refill an rxq free-buffer list
1940  * @ctx: the iflib context
1941  * @fl: the free list to refill
1942  * @count: the number of new buffers to allocate
1943  *
1944  * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
1945  * The caller must assure that @count does not exceed the queue's capacity.
1946  */
1947 static uint8_t
1948 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1949 {
1950 	struct if_rxd_update iru;
1951 	struct rxq_refill_cb_arg cb_arg;
1952 	struct mbuf *m;
1953 	caddr_t cl, *sd_cl;
1954 	struct mbuf **sd_m;
1955 	bus_dmamap_t *sd_map;
1956 	bus_addr_t bus_addr, *sd_ba;
1957 	int err, frag_idx, i, idx, n, pidx;
1958 	qidx_t credits;
1959 
1960 	sd_m = fl->ifl_sds.ifsd_m;
1961 	sd_map = fl->ifl_sds.ifsd_map;
1962 	sd_cl = fl->ifl_sds.ifsd_cl;
1963 	sd_ba = fl->ifl_sds.ifsd_ba;
1964 	pidx = fl->ifl_pidx;
1965 	idx = pidx;
1966 	frag_idx = fl->ifl_fragidx;
1967 	credits = fl->ifl_credits;
1968 
1969 	i = 0;
1970 	n = count;
1971 	MPASS(n > 0);
1972 	MPASS(credits + n <= fl->ifl_size);
1973 
1974 	if (pidx < fl->ifl_cidx)
1975 		MPASS(pidx + n <= fl->ifl_cidx);
1976 	if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1977 		MPASS(fl->ifl_gen == 0);
1978 	if (pidx > fl->ifl_cidx)
1979 		MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1980 
1981 	DBG_COUNTER_INC(fl_refills);
1982 	if (n > 8)
1983 		DBG_COUNTER_INC(fl_refills_large);
1984 	iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1985 	while (n--) {
1986 		/*
1987 		 * We allocate an uninitialized mbuf + cluster, mbuf is
1988 		 * initialized after rx.
1989 		 *
1990 		 * If the cluster is still set then we know a minimum sized packet was received
1991 		 */
1992 		bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
1993 		    &frag_idx);
1994 		if (frag_idx < 0)
1995 			bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1996 		MPASS(frag_idx >= 0);
1997 		if ((cl = sd_cl[frag_idx]) == NULL) {
1998 			if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL)
1999 				break;
2000 
2001 			cb_arg.error = 0;
2002 			MPASS(sd_map != NULL);
2003 			err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
2004 			    cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
2005 			    BUS_DMA_NOWAIT);
2006 			if (err != 0 || cb_arg.error) {
2007 				/*
2008 				 * !zone_pack ?
2009 				 */
2010 				if (fl->ifl_zone == zone_pack)
2011 					uma_zfree(fl->ifl_zone, cl);
2012 				break;
2013 			}
2014 
2015 			sd_ba[frag_idx] =  bus_addr = cb_arg.seg.ds_addr;
2016 			sd_cl[frag_idx] = cl;
2017 #if MEMORY_LOGGING
2018 			fl->ifl_cl_enqueued++;
2019 #endif
2020 		} else {
2021 			bus_addr = sd_ba[frag_idx];
2022 		}
2023 		bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2024 		    BUS_DMASYNC_PREREAD);
2025 
2026 		if (sd_m[frag_idx] == NULL) {
2027 			if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) {
2028 				break;
2029 			}
2030 			sd_m[frag_idx] = m;
2031 		}
2032 		bit_set(fl->ifl_rx_bitmap, frag_idx);
2033 #if MEMORY_LOGGING
2034 		fl->ifl_m_enqueued++;
2035 #endif
2036 
2037 		DBG_COUNTER_INC(rx_allocs);
2038 		fl->ifl_rxd_idxs[i] = frag_idx;
2039 		fl->ifl_bus_addrs[i] = bus_addr;
2040 		fl->ifl_vm_addrs[i] = cl;
2041 		credits++;
2042 		i++;
2043 		MPASS(credits <= fl->ifl_size);
2044 		if (++idx == fl->ifl_size) {
2045 			fl->ifl_gen = 1;
2046 			idx = 0;
2047 		}
2048 		if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2049 			iru.iru_pidx = pidx;
2050 			iru.iru_count = i;
2051 			ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2052 			i = 0;
2053 			pidx = idx;
2054 			fl->ifl_pidx = idx;
2055 			fl->ifl_credits = credits;
2056 		}
2057 	}
2058 
2059 	if (i) {
2060 		iru.iru_pidx = pidx;
2061 		iru.iru_count = i;
2062 		ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2063 		fl->ifl_pidx = idx;
2064 		fl->ifl_credits = credits;
2065 	}
2066 	DBG_COUNTER_INC(rxd_flush);
2067 	if (fl->ifl_pidx == 0)
2068 		pidx = fl->ifl_size - 1;
2069 	else
2070 		pidx = fl->ifl_pidx - 1;
2071 
2072 	bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2073 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2074 	ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx);
2075 	fl->ifl_fragidx = frag_idx + 1;
2076 	if (fl->ifl_fragidx == fl->ifl_size)
2077 		fl->ifl_fragidx = 0;
2078 
2079 	return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY);
2080 }
2081 
2082 static __inline uint8_t
2083 __iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl)
2084 {
2085 	/* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2086 	int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2087 #ifdef INVARIANTS
2088 	int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2089 #endif
2090 
2091 	MPASS(fl->ifl_credits <= fl->ifl_size);
2092 	MPASS(reclaimable == delta);
2093 
2094 	if (reclaimable > 0)
2095 		return (_iflib_fl_refill(ctx, fl, reclaimable));
2096 	return (0);
2097 }
2098 
2099 uint8_t
2100 iflib_in_detach(if_ctx_t ctx)
2101 {
2102 	bool in_detach;
2103 
2104 	STATE_LOCK(ctx);
2105 	in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2106 	STATE_UNLOCK(ctx);
2107 	return (in_detach);
2108 }
2109 
2110 static void
2111 iflib_fl_bufs_free(iflib_fl_t fl)
2112 {
2113 	iflib_dma_info_t idi = fl->ifl_ifdi;
2114 	bus_dmamap_t sd_map;
2115 	uint32_t i;
2116 
2117 	for (i = 0; i < fl->ifl_size; i++) {
2118 		struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2119 		caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2120 
2121 		if (*sd_cl != NULL) {
2122 			sd_map = fl->ifl_sds.ifsd_map[i];
2123 			bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2124 			    BUS_DMASYNC_POSTREAD);
2125 			bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2126 			if (*sd_cl != NULL)
2127 				uma_zfree(fl->ifl_zone, *sd_cl);
2128 			if (*sd_m != NULL) {
2129 				m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2130 				uma_zfree(zone_mbuf, *sd_m);
2131 			}
2132 		} else {
2133 			MPASS(*sd_cl == NULL);
2134 			MPASS(*sd_m == NULL);
2135 		}
2136 #if MEMORY_LOGGING
2137 		fl->ifl_m_dequeued++;
2138 		fl->ifl_cl_dequeued++;
2139 #endif
2140 		*sd_cl = NULL;
2141 		*sd_m = NULL;
2142 	}
2143 #ifdef INVARIANTS
2144 	for (i = 0; i < fl->ifl_size; i++) {
2145 		MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2146 		MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2147 	}
2148 #endif
2149 	/*
2150 	 * Reset free list values
2151 	 */
2152 	fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2153 	bzero(idi->idi_vaddr, idi->idi_size);
2154 }
2155 
2156 /*********************************************************************
2157  *
2158  *  Initialize a free list and its buffers.
2159  *
2160  **********************************************************************/
2161 static int
2162 iflib_fl_setup(iflib_fl_t fl)
2163 {
2164 	iflib_rxq_t rxq = fl->ifl_rxq;
2165 	if_ctx_t ctx = rxq->ifr_ctx;
2166 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2167 	int qidx;
2168 
2169 	bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2170 	/*
2171 	** Free current RX buffer structs and their mbufs
2172 	*/
2173 	iflib_fl_bufs_free(fl);
2174 	/* Now replenish the mbufs */
2175 	MPASS(fl->ifl_credits == 0);
2176 	qidx = rxq->ifr_fl_offset + fl->ifl_id;
2177 	if (scctx->isc_rxd_buf_size[qidx] != 0)
2178 		fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx];
2179 	else
2180 		fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2181 	/*
2182 	 * ifl_buf_size may be a driver-supplied value, so pull it up
2183 	 * to the selected mbuf size.
2184 	 */
2185 	fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size);
2186 	if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2187 		ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2188 	fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2189 	fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2190 
2191 
2192 	/* avoid pre-allocating zillions of clusters to an idle card
2193 	 * potentially speeding up attach
2194 	 */
2195 	(void) _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2196 	MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2197 	if (min(128, fl->ifl_size) != fl->ifl_credits)
2198 		return (ENOBUFS);
2199 	/*
2200 	 * handle failure
2201 	 */
2202 	MPASS(rxq != NULL);
2203 	MPASS(fl->ifl_ifdi != NULL);
2204 	bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2205 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2206 	return (0);
2207 }
2208 
2209 /*********************************************************************
2210  *
2211  *  Free receive ring data structures
2212  *
2213  **********************************************************************/
2214 static void
2215 iflib_rx_sds_free(iflib_rxq_t rxq)
2216 {
2217 	iflib_fl_t fl;
2218 	int i, j;
2219 
2220 	if (rxq->ifr_fl != NULL) {
2221 		for (i = 0; i < rxq->ifr_nfl; i++) {
2222 			fl = &rxq->ifr_fl[i];
2223 			if (fl->ifl_buf_tag != NULL) {
2224 				if (fl->ifl_sds.ifsd_map != NULL) {
2225 					for (j = 0; j < fl->ifl_size; j++) {
2226 						bus_dmamap_sync(
2227 						    fl->ifl_buf_tag,
2228 						    fl->ifl_sds.ifsd_map[j],
2229 						    BUS_DMASYNC_POSTREAD);
2230 						bus_dmamap_unload(
2231 						    fl->ifl_buf_tag,
2232 						    fl->ifl_sds.ifsd_map[j]);
2233 						bus_dmamap_destroy(
2234 						    fl->ifl_buf_tag,
2235 						    fl->ifl_sds.ifsd_map[j]);
2236 					}
2237 				}
2238 				bus_dma_tag_destroy(fl->ifl_buf_tag);
2239 				fl->ifl_buf_tag = NULL;
2240 			}
2241 			free(fl->ifl_sds.ifsd_m, M_IFLIB);
2242 			free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2243 			free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2244 			free(fl->ifl_sds.ifsd_map, M_IFLIB);
2245 			fl->ifl_sds.ifsd_m = NULL;
2246 			fl->ifl_sds.ifsd_cl = NULL;
2247 			fl->ifl_sds.ifsd_ba = NULL;
2248 			fl->ifl_sds.ifsd_map = NULL;
2249 		}
2250 		free(rxq->ifr_fl, M_IFLIB);
2251 		rxq->ifr_fl = NULL;
2252 		free(rxq->ifr_ifdi, M_IFLIB);
2253 		rxq->ifr_ifdi = NULL;
2254 		rxq->ifr_cq_cidx = 0;
2255 	}
2256 }
2257 
2258 /*
2259  * Timer routine
2260  */
2261 static void
2262 iflib_timer(void *arg)
2263 {
2264 	iflib_txq_t txq = arg;
2265 	if_ctx_t ctx = txq->ift_ctx;
2266 	if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2267 	uint64_t this_tick = ticks;
2268 	uint32_t reset_on = hz / 2;
2269 
2270 	if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2271 		return;
2272 
2273 	/*
2274 	** Check on the state of the TX queue(s), this
2275 	** can be done without the lock because its RO
2276 	** and the HUNG state will be static if set.
2277 	*/
2278 	if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2279 		txq->ift_last_timer_tick = this_tick;
2280 		IFDI_TIMER(ctx, txq->ift_id);
2281 		if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2282 		    ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2283 		     (sctx->isc_pause_frames == 0)))
2284 			goto hung;
2285 
2286 		if (txq->ift_qstatus != IFLIB_QUEUE_IDLE &&
2287 		    ifmp_ring_is_stalled(txq->ift_br)) {
2288 			KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down"));
2289 			txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2290 		}
2291 		txq->ift_cleaned_prev = txq->ift_cleaned;
2292 	}
2293 #ifdef DEV_NETMAP
2294 	if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2295 		iflib_netmap_timer_adjust(ctx, txq, &reset_on);
2296 #endif
2297 	/* handle any laggards */
2298 	if (txq->ift_db_pending)
2299 		GROUPTASK_ENQUEUE(&txq->ift_task);
2300 
2301 	sctx->isc_pause_frames = 0;
2302 	if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2303 		callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2304 	return;
2305 
2306  hung:
2307 	device_printf(ctx->ifc_dev,
2308 	    "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2309 	    txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2310 	STATE_LOCK(ctx);
2311 	if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2312 	ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2313 	iflib_admin_intr_deferred(ctx);
2314 	STATE_UNLOCK(ctx);
2315 }
2316 
2317 static uint16_t
2318 iflib_get_mbuf_size_for(unsigned int size)
2319 {
2320 
2321 	if (size <= MCLBYTES)
2322 		return (MCLBYTES);
2323 	else
2324 		return (MJUMPAGESIZE);
2325 }
2326 
2327 static void
2328 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2329 {
2330 	if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2331 
2332 	/*
2333 	 * XXX don't set the max_frame_size to larger
2334 	 * than the hardware can handle
2335 	 */
2336 	ctx->ifc_rx_mbuf_sz =
2337 	    iflib_get_mbuf_size_for(sctx->isc_max_frame_size);
2338 }
2339 
2340 uint32_t
2341 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2342 {
2343 
2344 	return (ctx->ifc_rx_mbuf_sz);
2345 }
2346 
2347 static void
2348 iflib_init_locked(if_ctx_t ctx)
2349 {
2350 	if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2351 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2352 	if_t ifp = ctx->ifc_ifp;
2353 	iflib_fl_t fl;
2354 	iflib_txq_t txq;
2355 	iflib_rxq_t rxq;
2356 	int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2357 
2358 	if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2359 	IFDI_INTR_DISABLE(ctx);
2360 
2361 	tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2362 	tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2363 	/* Set hardware offload abilities */
2364 	if_clearhwassist(ifp);
2365 	if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2366 		if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2367 	if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2368 		if_sethwassistbits(ifp,  tx_ip6_csum_flags, 0);
2369 	if (if_getcapenable(ifp) & IFCAP_TSO4)
2370 		if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2371 	if (if_getcapenable(ifp) & IFCAP_TSO6)
2372 		if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2373 
2374 	for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2375 		CALLOUT_LOCK(txq);
2376 		callout_stop(&txq->ift_timer);
2377 		CALLOUT_UNLOCK(txq);
2378 		iflib_netmap_txq_init(ctx, txq);
2379 	}
2380 
2381 	/*
2382 	 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2383 	 * that drivers can use the value when setting up the hardware receive
2384 	 * buffers.
2385 	 */
2386 	iflib_calc_rx_mbuf_sz(ctx);
2387 
2388 #ifdef INVARIANTS
2389 	i = if_getdrvflags(ifp);
2390 #endif
2391 	IFDI_INIT(ctx);
2392 	MPASS(if_getdrvflags(ifp) == i);
2393 	for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2394 		/* XXX this should really be done on a per-queue basis */
2395 		if (if_getcapenable(ifp) & IFCAP_NETMAP) {
2396 			MPASS(rxq->ifr_id == i);
2397 			iflib_netmap_rxq_init(ctx, rxq);
2398 			continue;
2399 		}
2400 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2401 			if (iflib_fl_setup(fl)) {
2402 				device_printf(ctx->ifc_dev,
2403 				    "setting up free list %d failed - "
2404 				    "check cluster settings\n", j);
2405 				goto done;
2406 			}
2407 		}
2408 	}
2409 done:
2410 	if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2411 	IFDI_INTR_ENABLE(ctx);
2412 	txq = ctx->ifc_txqs;
2413 	for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2414 		callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2415 			txq->ift_timer.c_cpu);
2416 }
2417 
2418 static int
2419 iflib_media_change(if_t ifp)
2420 {
2421 	if_ctx_t ctx = if_getsoftc(ifp);
2422 	int err;
2423 
2424 	CTX_LOCK(ctx);
2425 	if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2426 		iflib_init_locked(ctx);
2427 	CTX_UNLOCK(ctx);
2428 	return (err);
2429 }
2430 
2431 static void
2432 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2433 {
2434 	if_ctx_t ctx = if_getsoftc(ifp);
2435 
2436 	CTX_LOCK(ctx);
2437 	IFDI_UPDATE_ADMIN_STATUS(ctx);
2438 	IFDI_MEDIA_STATUS(ctx, ifmr);
2439 	CTX_UNLOCK(ctx);
2440 }
2441 
2442 void
2443 iflib_stop(if_ctx_t ctx)
2444 {
2445 	iflib_txq_t txq = ctx->ifc_txqs;
2446 	iflib_rxq_t rxq = ctx->ifc_rxqs;
2447 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2448 	if_shared_ctx_t sctx = ctx->ifc_sctx;
2449 	iflib_dma_info_t di;
2450 	iflib_fl_t fl;
2451 	int i, j;
2452 
2453 	/* Tell the stack that the interface is no longer active */
2454 	if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2455 
2456 	IFDI_INTR_DISABLE(ctx);
2457 	DELAY(1000);
2458 	IFDI_STOP(ctx);
2459 	DELAY(1000);
2460 
2461 	iflib_debug_reset();
2462 	/* Wait for current tx queue users to exit to disarm watchdog timer. */
2463 	for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2464 		/* make sure all transmitters have completed before proceeding XXX */
2465 
2466 		CALLOUT_LOCK(txq);
2467 		callout_stop(&txq->ift_timer);
2468 		CALLOUT_UNLOCK(txq);
2469 
2470 		/* clean any enqueued buffers */
2471 		iflib_ifmp_purge(txq);
2472 		/* Free any existing tx buffers. */
2473 		for (j = 0; j < txq->ift_size; j++) {
2474 			iflib_txsd_free(ctx, txq, j);
2475 		}
2476 		txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2477 		txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2478 		txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2479 		txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2480 		txq->ift_pullups = 0;
2481 		ifmp_ring_reset_stats(txq->ift_br);
2482 		for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2483 			bzero((void *)di->idi_vaddr, di->idi_size);
2484 	}
2485 	for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2486 		/* make sure all transmitters have completed before proceeding XXX */
2487 
2488 		rxq->ifr_cq_cidx = 0;
2489 		for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2490 			bzero((void *)di->idi_vaddr, di->idi_size);
2491 		/* also resets the free lists pidx/cidx */
2492 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2493 			iflib_fl_bufs_free(fl);
2494 	}
2495 }
2496 
2497 static inline caddr_t
2498 calc_next_rxd(iflib_fl_t fl, int cidx)
2499 {
2500 	qidx_t size;
2501 	int nrxd;
2502 	caddr_t start, end, cur, next;
2503 
2504 	nrxd = fl->ifl_size;
2505 	size = fl->ifl_rxd_size;
2506 	start = fl->ifl_ifdi->idi_vaddr;
2507 
2508 	if (__predict_false(size == 0))
2509 		return (start);
2510 	cur = start + size*cidx;
2511 	end = start + size*nrxd;
2512 	next = CACHE_PTR_NEXT(cur);
2513 	return (next < end ? next : start);
2514 }
2515 
2516 static inline void
2517 prefetch_pkts(iflib_fl_t fl, int cidx)
2518 {
2519 	int nextptr;
2520 	int nrxd = fl->ifl_size;
2521 	caddr_t next_rxd;
2522 
2523 
2524 	nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2525 	prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2526 	prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2527 	next_rxd = calc_next_rxd(fl, cidx);
2528 	prefetch(next_rxd);
2529 	prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2530 	prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2531 	prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2532 	prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2533 	prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2534 	prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2535 	prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2536 	prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2537 }
2538 
2539 static struct mbuf *
2540 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2541     int *pf_rv, if_rxd_info_t ri)
2542 {
2543 	bus_dmamap_t map;
2544 	iflib_fl_t fl;
2545 	caddr_t payload;
2546 	struct mbuf *m;
2547 	int flid, cidx, len, next;
2548 
2549 	map = NULL;
2550 	flid = irf->irf_flid;
2551 	cidx = irf->irf_idx;
2552 	fl = &rxq->ifr_fl[flid];
2553 	sd->ifsd_fl = fl;
2554 	m = fl->ifl_sds.ifsd_m[cidx];
2555 	sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2556 	fl->ifl_credits--;
2557 #if MEMORY_LOGGING
2558 	fl->ifl_m_dequeued++;
2559 #endif
2560 	if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2561 		prefetch_pkts(fl, cidx);
2562 	next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2563 	prefetch(&fl->ifl_sds.ifsd_map[next]);
2564 	map = fl->ifl_sds.ifsd_map[cidx];
2565 
2566 	bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2567 
2568 	if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL &&
2569 	    irf->irf_len != 0) {
2570 		payload  = *sd->ifsd_cl;
2571 		payload +=  ri->iri_pad;
2572 		len = ri->iri_len - ri->iri_pad;
2573 		*pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp,
2574 		    len | PFIL_MEMPTR | PFIL_IN, NULL);
2575 		switch (*pf_rv) {
2576 		case PFIL_DROPPED:
2577 		case PFIL_CONSUMED:
2578 			/*
2579 			 * The filter ate it.  Everything is recycled.
2580 			 */
2581 			m = NULL;
2582 			unload = 0;
2583 			break;
2584 		case PFIL_REALLOCED:
2585 			/*
2586 			 * The filter copied it.  Everything is recycled.
2587 			 */
2588 			m = pfil_mem2mbuf(payload);
2589 			unload = 0;
2590 			break;
2591 		case PFIL_PASS:
2592 			/*
2593 			 * Filter said it was OK, so receive like
2594 			 * normal
2595 			 */
2596 			fl->ifl_sds.ifsd_m[cidx] = NULL;
2597 			break;
2598 		default:
2599 			MPASS(0);
2600 		}
2601 	} else {
2602 		fl->ifl_sds.ifsd_m[cidx] = NULL;
2603 		*pf_rv = PFIL_PASS;
2604 	}
2605 
2606 	if (unload && irf->irf_len != 0)
2607 		bus_dmamap_unload(fl->ifl_buf_tag, map);
2608 	fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2609 	if (__predict_false(fl->ifl_cidx == 0))
2610 		fl->ifl_gen = 0;
2611 	bit_clear(fl->ifl_rx_bitmap, cidx);
2612 	return (m);
2613 }
2614 
2615 static struct mbuf *
2616 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2617 {
2618 	struct mbuf *m, *mh, *mt;
2619 	caddr_t cl;
2620 	int  *pf_rv_ptr, flags, i, padlen;
2621 	bool consumed;
2622 
2623 	i = 0;
2624 	mh = NULL;
2625 	consumed = false;
2626 	*pf_rv = PFIL_PASS;
2627 	pf_rv_ptr = pf_rv;
2628 	do {
2629 		m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2630 		    pf_rv_ptr, ri);
2631 
2632 		MPASS(*sd->ifsd_cl != NULL);
2633 
2634 		/*
2635 		 * Exclude zero-length frags & frags from
2636 		 * packets the filter has consumed or dropped
2637 		 */
2638 		if (ri->iri_frags[i].irf_len == 0 || consumed ||
2639 		    *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2640 			if (mh == NULL) {
2641 				/* everything saved here */
2642 				consumed = true;
2643 				pf_rv_ptr = NULL;
2644 				continue;
2645 			}
2646 			/* XXX we can save the cluster here, but not the mbuf */
2647 			m_init(m, M_NOWAIT, MT_DATA, 0);
2648 			m_free(m);
2649 			continue;
2650 		}
2651 		if (mh == NULL) {
2652 			flags = M_PKTHDR|M_EXT;
2653 			mh = mt = m;
2654 			padlen = ri->iri_pad;
2655 		} else {
2656 			flags = M_EXT;
2657 			mt->m_next = m;
2658 			mt = m;
2659 			/* assuming padding is only on the first fragment */
2660 			padlen = 0;
2661 		}
2662 		cl = *sd->ifsd_cl;
2663 		*sd->ifsd_cl = NULL;
2664 
2665 		/* Can these two be made one ? */
2666 		m_init(m, M_NOWAIT, MT_DATA, flags);
2667 		m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2668 		/*
2669 		 * These must follow m_init and m_cljset
2670 		 */
2671 		m->m_data += padlen;
2672 		ri->iri_len -= padlen;
2673 		m->m_len = ri->iri_frags[i].irf_len;
2674 	} while (++i < ri->iri_nfrags);
2675 
2676 	return (mh);
2677 }
2678 
2679 /*
2680  * Process one software descriptor
2681  */
2682 static struct mbuf *
2683 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2684 {
2685 	struct if_rxsd sd;
2686 	struct mbuf *m;
2687 	int pf_rv;
2688 
2689 	/* should I merge this back in now that the two paths are basically duplicated? */
2690 	if (ri->iri_nfrags == 1 &&
2691 	    ri->iri_frags[0].irf_len != 0 &&
2692 	    ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2693 		m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2694 		    &pf_rv, ri);
2695 		if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2696 			return (m);
2697 		if (pf_rv == PFIL_PASS) {
2698 			m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2699 #ifndef __NO_STRICT_ALIGNMENT
2700 			if (!IP_ALIGNED(m))
2701 				m->m_data += 2;
2702 #endif
2703 			memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2704 			m->m_len = ri->iri_frags[0].irf_len;
2705 		}
2706 	} else {
2707 		m = assemble_segments(rxq, ri, &sd, &pf_rv);
2708 		if (m == NULL)
2709 			return (NULL);
2710 		if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2711 			return (m);
2712 	}
2713 	m->m_pkthdr.len = ri->iri_len;
2714 	m->m_pkthdr.rcvif = ri->iri_ifp;
2715 	m->m_flags |= ri->iri_flags;
2716 	m->m_pkthdr.ether_vtag = ri->iri_vtag;
2717 	m->m_pkthdr.flowid = ri->iri_flowid;
2718 	M_HASHTYPE_SET(m, ri->iri_rsstype);
2719 	m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2720 	m->m_pkthdr.csum_data = ri->iri_csum_data;
2721 	return (m);
2722 }
2723 
2724 #if defined(INET6) || defined(INET)
2725 static void
2726 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2727 {
2728 	CURVNET_SET(lc->ifp->if_vnet);
2729 #if defined(INET6)
2730 	*v6 = V_ip6_forwarding;
2731 #endif
2732 #if defined(INET)
2733 	*v4 = V_ipforwarding;
2734 #endif
2735 	CURVNET_RESTORE();
2736 }
2737 
2738 /*
2739  * Returns true if it's possible this packet could be LROed.
2740  * if it returns false, it is guaranteed that tcp_lro_rx()
2741  * would not return zero.
2742  */
2743 static bool
2744 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2745 {
2746 	struct ether_header *eh;
2747 
2748 	eh = mtod(m, struct ether_header *);
2749 	switch (eh->ether_type) {
2750 #if defined(INET6)
2751 		case htons(ETHERTYPE_IPV6):
2752 			return (!v6_forwarding);
2753 #endif
2754 #if defined (INET)
2755 		case htons(ETHERTYPE_IP):
2756 			return (!v4_forwarding);
2757 #endif
2758 	}
2759 
2760 	return false;
2761 }
2762 #else
2763 static void
2764 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2765 {
2766 }
2767 #endif
2768 
2769 static void
2770 _task_fn_rx_watchdog(void *context)
2771 {
2772 	iflib_rxq_t rxq = context;
2773 
2774 	GROUPTASK_ENQUEUE(&rxq->ifr_task);
2775 }
2776 
2777 static uint8_t
2778 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2779 {
2780 	if_t ifp;
2781 	if_ctx_t ctx = rxq->ifr_ctx;
2782 	if_shared_ctx_t sctx = ctx->ifc_sctx;
2783 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2784 	int avail, i;
2785 	qidx_t *cidxp;
2786 	struct if_rxd_info ri;
2787 	int err, budget_left, rx_bytes, rx_pkts;
2788 	iflib_fl_t fl;
2789 	int lro_enabled;
2790 	bool v4_forwarding, v6_forwarding, lro_possible;
2791 	uint8_t retval = 0;
2792 
2793 	/*
2794 	 * XXX early demux data packets so that if_input processing only handles
2795 	 * acks in interrupt context
2796 	 */
2797 	struct mbuf *m, *mh, *mt, *mf;
2798 
2799 	NET_EPOCH_ASSERT();
2800 
2801 	lro_possible = v4_forwarding = v6_forwarding = false;
2802 	ifp = ctx->ifc_ifp;
2803 	mh = mt = NULL;
2804 	MPASS(budget > 0);
2805 	rx_pkts	= rx_bytes = 0;
2806 	if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2807 		cidxp = &rxq->ifr_cq_cidx;
2808 	else
2809 		cidxp = &rxq->ifr_fl[0].ifl_cidx;
2810 	if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2811 		for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2812 			retval |= __iflib_fl_refill_all(ctx, fl);
2813 		DBG_COUNTER_INC(rx_unavail);
2814 		return (retval);
2815 	}
2816 
2817 	/* pfil needs the vnet to be set */
2818 	CURVNET_SET_QUIET(ifp->if_vnet);
2819 	for (budget_left = budget; budget_left > 0 && avail > 0;) {
2820 		if (__predict_false(!CTX_ACTIVE(ctx))) {
2821 			DBG_COUNTER_INC(rx_ctx_inactive);
2822 			break;
2823 		}
2824 		/*
2825 		 * Reset client set fields to their default values
2826 		 */
2827 		rxd_info_zero(&ri);
2828 		ri.iri_qsidx = rxq->ifr_id;
2829 		ri.iri_cidx = *cidxp;
2830 		ri.iri_ifp = ifp;
2831 		ri.iri_frags = rxq->ifr_frags;
2832 		err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2833 
2834 		if (err)
2835 			goto err;
2836 		rx_pkts += 1;
2837 		rx_bytes += ri.iri_len;
2838 		if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2839 			*cidxp = ri.iri_cidx;
2840 			/* Update our consumer index */
2841 			/* XXX NB: shurd - check if this is still safe */
2842 			while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
2843 				rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2844 			/* was this only a completion queue message? */
2845 			if (__predict_false(ri.iri_nfrags == 0))
2846 				continue;
2847 		}
2848 		MPASS(ri.iri_nfrags != 0);
2849 		MPASS(ri.iri_len != 0);
2850 
2851 		/* will advance the cidx on the corresponding free lists */
2852 		m = iflib_rxd_pkt_get(rxq, &ri);
2853 		avail--;
2854 		budget_left--;
2855 		if (avail == 0 && budget_left)
2856 			avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2857 
2858 		if (__predict_false(m == NULL))
2859 			continue;
2860 
2861 		/* imm_pkt: -- cxgb */
2862 		if (mh == NULL)
2863 			mh = mt = m;
2864 		else {
2865 			mt->m_nextpkt = m;
2866 			mt = m;
2867 		}
2868 	}
2869 	CURVNET_RESTORE();
2870 	/* make sure that we can refill faster than drain */
2871 	for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2872 		retval |= __iflib_fl_refill_all(ctx, fl);
2873 
2874 	lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2875 	if (lro_enabled)
2876 		iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2877 	mt = mf = NULL;
2878 	while (mh != NULL) {
2879 		m = mh;
2880 		mh = mh->m_nextpkt;
2881 		m->m_nextpkt = NULL;
2882 #ifndef __NO_STRICT_ALIGNMENT
2883 		if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2884 			continue;
2885 #endif
2886 		rx_bytes += m->m_pkthdr.len;
2887 		rx_pkts++;
2888 #if defined(INET6) || defined(INET)
2889 		if (lro_enabled) {
2890 			if (!lro_possible) {
2891 				lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2892 				if (lro_possible && mf != NULL) {
2893 					ifp->if_input(ifp, mf);
2894 					DBG_COUNTER_INC(rx_if_input);
2895 					mt = mf = NULL;
2896 				}
2897 			}
2898 			if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2899 			    (CSUM_L4_CALC|CSUM_L4_VALID)) {
2900 				if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2901 					continue;
2902 			}
2903 		}
2904 #endif
2905 		if (lro_possible) {
2906 			ifp->if_input(ifp, m);
2907 			DBG_COUNTER_INC(rx_if_input);
2908 			continue;
2909 		}
2910 
2911 		if (mf == NULL)
2912 			mf = m;
2913 		if (mt != NULL)
2914 			mt->m_nextpkt = m;
2915 		mt = m;
2916 	}
2917 	if (mf != NULL) {
2918 		ifp->if_input(ifp, mf);
2919 		DBG_COUNTER_INC(rx_if_input);
2920 	}
2921 
2922 	if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2923 	if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2924 
2925 	/*
2926 	 * Flush any outstanding LRO work
2927 	 */
2928 #if defined(INET6) || defined(INET)
2929 	tcp_lro_flush_all(&rxq->ifr_lc);
2930 #endif
2931 	if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0)
2932 		retval |= IFLIB_RXEOF_MORE;
2933 	return (retval);
2934 err:
2935 	STATE_LOCK(ctx);
2936 	ctx->ifc_flags |= IFC_DO_RESET;
2937 	iflib_admin_intr_deferred(ctx);
2938 	STATE_UNLOCK(ctx);
2939 	return (0);
2940 }
2941 
2942 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2943 static inline qidx_t
2944 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2945 {
2946 	qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2947 	qidx_t minthresh = txq->ift_size / 8;
2948 	if (in_use > 4*minthresh)
2949 		return (notify_count);
2950 	if (in_use > 2*minthresh)
2951 		return (notify_count >> 1);
2952 	if (in_use > minthresh)
2953 		return (notify_count >> 3);
2954 	return (0);
2955 }
2956 
2957 static inline qidx_t
2958 txq_max_rs_deferred(iflib_txq_t txq)
2959 {
2960 	qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2961 	qidx_t minthresh = txq->ift_size / 8;
2962 	if (txq->ift_in_use > 4*minthresh)
2963 		return (notify_count);
2964 	if (txq->ift_in_use > 2*minthresh)
2965 		return (notify_count >> 1);
2966 	if (txq->ift_in_use > minthresh)
2967 		return (notify_count >> 2);
2968 	return (2);
2969 }
2970 
2971 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2972 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2973 
2974 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2975 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2976 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2977 
2978 /* forward compatibility for cxgb */
2979 #define FIRST_QSET(ctx) 0
2980 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2981 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2982 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2983 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2984 
2985 /* XXX we should be setting this to something other than zero */
2986 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2987 #define	MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2988     (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2989 
2990 static inline bool
2991 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2992 {
2993 	qidx_t dbval, max;
2994 	bool rang;
2995 
2996 	rang = false;
2997 	max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2998 	if (ring || txq->ift_db_pending >= max) {
2999 		dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
3000 		bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3001 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3002 		ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
3003 		txq->ift_db_pending = txq->ift_npending = 0;
3004 		rang = true;
3005 	}
3006 	return (rang);
3007 }
3008 
3009 #ifdef PKT_DEBUG
3010 static void
3011 print_pkt(if_pkt_info_t pi)
3012 {
3013 	printf("pi len:  %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
3014 	       pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
3015 	printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
3016 	       pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
3017 	printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
3018 	       pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
3019 }
3020 #endif
3021 
3022 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
3023 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
3024 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
3025 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
3026 
3027 static int
3028 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
3029 {
3030 	if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
3031 	struct ether_vlan_header *eh;
3032 	struct mbuf *m;
3033 
3034 	m = *mp;
3035 	if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
3036 	    M_WRITABLE(m) == 0) {
3037 		if ((m = m_dup(m, M_NOWAIT)) == NULL) {
3038 			return (ENOMEM);
3039 		} else {
3040 			m_freem(*mp);
3041 			DBG_COUNTER_INC(tx_frees);
3042 			*mp = m;
3043 		}
3044 	}
3045 
3046 	/*
3047 	 * Determine where frame payload starts.
3048 	 * Jump over vlan headers if already present,
3049 	 * helpful for QinQ too.
3050 	 */
3051 	if (__predict_false(m->m_len < sizeof(*eh))) {
3052 		txq->ift_pullups++;
3053 		if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3054 			return (ENOMEM);
3055 	}
3056 	eh = mtod(m, struct ether_vlan_header *);
3057 	if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3058 		pi->ipi_etype = ntohs(eh->evl_proto);
3059 		pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3060 	} else {
3061 		pi->ipi_etype = ntohs(eh->evl_encap_proto);
3062 		pi->ipi_ehdrlen = ETHER_HDR_LEN;
3063 	}
3064 
3065 	switch (pi->ipi_etype) {
3066 #ifdef INET
3067 	case ETHERTYPE_IP:
3068 	{
3069 		struct mbuf *n;
3070 		struct ip *ip = NULL;
3071 		struct tcphdr *th = NULL;
3072 		int minthlen;
3073 
3074 		minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3075 		if (__predict_false(m->m_len < minthlen)) {
3076 			/*
3077 			 * if this code bloat is causing too much of a hit
3078 			 * move it to a separate function and mark it noinline
3079 			 */
3080 			if (m->m_len == pi->ipi_ehdrlen) {
3081 				n = m->m_next;
3082 				MPASS(n);
3083 				if (n->m_len >= sizeof(*ip))  {
3084 					ip = (struct ip *)n->m_data;
3085 					if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3086 						th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3087 				} else {
3088 					txq->ift_pullups++;
3089 					if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3090 						return (ENOMEM);
3091 					ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3092 				}
3093 			} else {
3094 				txq->ift_pullups++;
3095 				if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3096 					return (ENOMEM);
3097 				ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3098 				if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3099 					th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3100 			}
3101 		} else {
3102 			ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3103 			if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3104 				th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3105 		}
3106 		pi->ipi_ip_hlen = ip->ip_hl << 2;
3107 		pi->ipi_ipproto = ip->ip_p;
3108 		pi->ipi_flags |= IPI_TX_IPV4;
3109 
3110 		/* TCP checksum offload may require TCP header length */
3111 		if (IS_TX_OFFLOAD4(pi)) {
3112 			if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3113 				if (__predict_false(th == NULL)) {
3114 					txq->ift_pullups++;
3115 					if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3116 						return (ENOMEM);
3117 					th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3118 				}
3119 				pi->ipi_tcp_hflags = th->th_flags;
3120 				pi->ipi_tcp_hlen = th->th_off << 2;
3121 				pi->ipi_tcp_seq = th->th_seq;
3122 			}
3123 			if (IS_TSO4(pi)) {
3124 				if (__predict_false(ip->ip_p != IPPROTO_TCP))
3125 					return (ENXIO);
3126 				/*
3127 				 * TSO always requires hardware checksum offload.
3128 				 */
3129 				pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3130 				th->th_sum = in_pseudo(ip->ip_src.s_addr,
3131 						       ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3132 				pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3133 				if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3134 					ip->ip_sum = 0;
3135 					ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3136 				}
3137 			}
3138 		}
3139 		if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3140                        ip->ip_sum = 0;
3141 
3142 		break;
3143 	}
3144 #endif
3145 #ifdef INET6
3146 	case ETHERTYPE_IPV6:
3147 	{
3148 		struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3149 		struct tcphdr *th;
3150 		pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3151 
3152 		if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3153 			txq->ift_pullups++;
3154 			if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3155 				return (ENOMEM);
3156 		}
3157 		th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3158 
3159 		/* XXX-BZ this will go badly in case of ext hdrs. */
3160 		pi->ipi_ipproto = ip6->ip6_nxt;
3161 		pi->ipi_flags |= IPI_TX_IPV6;
3162 
3163 		/* TCP checksum offload may require TCP header length */
3164 		if (IS_TX_OFFLOAD6(pi)) {
3165 			if (pi->ipi_ipproto == IPPROTO_TCP) {
3166 				if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3167 					txq->ift_pullups++;
3168 					if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3169 						return (ENOMEM);
3170 				}
3171 				pi->ipi_tcp_hflags = th->th_flags;
3172 				pi->ipi_tcp_hlen = th->th_off << 2;
3173 				pi->ipi_tcp_seq = th->th_seq;
3174 			}
3175 			if (IS_TSO6(pi)) {
3176 				if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3177 					return (ENXIO);
3178 				/*
3179 				 * TSO always requires hardware checksum offload.
3180 				 */
3181 				pi->ipi_csum_flags |= CSUM_IP6_TCP;
3182 				th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3183 				pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3184 			}
3185 		}
3186 		break;
3187 	}
3188 #endif
3189 	default:
3190 		pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3191 		pi->ipi_ip_hlen = 0;
3192 		break;
3193 	}
3194 	*mp = m;
3195 
3196 	return (0);
3197 }
3198 
3199 /*
3200  * If dodgy hardware rejects the scatter gather chain we've handed it
3201  * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3202  * m_defrag'd mbufs
3203  */
3204 static __noinline struct mbuf *
3205 iflib_remove_mbuf(iflib_txq_t txq)
3206 {
3207 	int ntxd, pidx;
3208 	struct mbuf *m, **ifsd_m;
3209 
3210 	ifsd_m = txq->ift_sds.ifsd_m;
3211 	ntxd = txq->ift_size;
3212 	pidx = txq->ift_pidx & (ntxd - 1);
3213 	ifsd_m = txq->ift_sds.ifsd_m;
3214 	m = ifsd_m[pidx];
3215 	ifsd_m[pidx] = NULL;
3216 	bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3217 	if (txq->ift_sds.ifsd_tso_map != NULL)
3218 		bus_dmamap_unload(txq->ift_tso_buf_tag,
3219 		    txq->ift_sds.ifsd_tso_map[pidx]);
3220 #if MEMORY_LOGGING
3221 	txq->ift_dequeued++;
3222 #endif
3223 	return (m);
3224 }
3225 
3226 static inline caddr_t
3227 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3228 {
3229 	qidx_t size;
3230 	int ntxd;
3231 	caddr_t start, end, cur, next;
3232 
3233 	ntxd = txq->ift_size;
3234 	size = txq->ift_txd_size[qid];
3235 	start = txq->ift_ifdi[qid].idi_vaddr;
3236 
3237 	if (__predict_false(size == 0))
3238 		return (start);
3239 	cur = start + size*cidx;
3240 	end = start + size*ntxd;
3241 	next = CACHE_PTR_NEXT(cur);
3242 	return (next < end ? next : start);
3243 }
3244 
3245 /*
3246  * Pad an mbuf to ensure a minimum ethernet frame size.
3247  * min_frame_size is the frame size (less CRC) to pad the mbuf to
3248  */
3249 static __noinline int
3250 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3251 {
3252 	/*
3253 	 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3254 	 * and ARP message is the smallest common payload I can think of
3255 	 */
3256 	static char pad[18];	/* just zeros */
3257 	int n;
3258 	struct mbuf *new_head;
3259 
3260 	if (!M_WRITABLE(*m_head)) {
3261 		new_head = m_dup(*m_head, M_NOWAIT);
3262 		if (new_head == NULL) {
3263 			m_freem(*m_head);
3264 			device_printf(dev, "cannot pad short frame, m_dup() failed");
3265 			DBG_COUNTER_INC(encap_pad_mbuf_fail);
3266 			DBG_COUNTER_INC(tx_frees);
3267 			return ENOMEM;
3268 		}
3269 		m_freem(*m_head);
3270 		*m_head = new_head;
3271 	}
3272 
3273 	for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3274 	     n > 0; n -= sizeof(pad))
3275 		if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3276 			break;
3277 
3278 	if (n > 0) {
3279 		m_freem(*m_head);
3280 		device_printf(dev, "cannot pad short frame\n");
3281 		DBG_COUNTER_INC(encap_pad_mbuf_fail);
3282 		DBG_COUNTER_INC(tx_frees);
3283 		return (ENOBUFS);
3284 	}
3285 
3286 	return 0;
3287 }
3288 
3289 static int
3290 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3291 {
3292 	if_ctx_t		ctx;
3293 	if_shared_ctx_t		sctx;
3294 	if_softc_ctx_t		scctx;
3295 	bus_dma_tag_t		buf_tag;
3296 	bus_dma_segment_t	*segs;
3297 	struct mbuf		*m_head, **ifsd_m;
3298 	void			*next_txd;
3299 	bus_dmamap_t		map;
3300 	struct if_pkt_info	pi;
3301 	int remap = 0;
3302 	int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3303 
3304 	ctx = txq->ift_ctx;
3305 	sctx = ctx->ifc_sctx;
3306 	scctx = &ctx->ifc_softc_ctx;
3307 	segs = txq->ift_segs;
3308 	ntxd = txq->ift_size;
3309 	m_head = *m_headp;
3310 	map = NULL;
3311 
3312 	/*
3313 	 * If we're doing TSO the next descriptor to clean may be quite far ahead
3314 	 */
3315 	cidx = txq->ift_cidx;
3316 	pidx = txq->ift_pidx;
3317 	if (ctx->ifc_flags & IFC_PREFETCH) {
3318 		next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3319 		if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3320 			next_txd = calc_next_txd(txq, cidx, 0);
3321 			prefetch(next_txd);
3322 		}
3323 
3324 		/* prefetch the next cache line of mbuf pointers and flags */
3325 		prefetch(&txq->ift_sds.ifsd_m[next]);
3326 		prefetch(&txq->ift_sds.ifsd_map[next]);
3327 		next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3328 	}
3329 	map = txq->ift_sds.ifsd_map[pidx];
3330 	ifsd_m = txq->ift_sds.ifsd_m;
3331 
3332 	if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3333 		buf_tag = txq->ift_tso_buf_tag;
3334 		max_segs = scctx->isc_tx_tso_segments_max;
3335 		map = txq->ift_sds.ifsd_tso_map[pidx];
3336 		MPASS(buf_tag != NULL);
3337 		MPASS(max_segs > 0);
3338 	} else {
3339 		buf_tag = txq->ift_buf_tag;
3340 		max_segs = scctx->isc_tx_nsegments;
3341 		map = txq->ift_sds.ifsd_map[pidx];
3342 	}
3343 	if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3344 	    __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3345 		err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3346 		if (err) {
3347 			DBG_COUNTER_INC(encap_txd_encap_fail);
3348 			return err;
3349 		}
3350 	}
3351 	m_head = *m_headp;
3352 
3353 	pkt_info_zero(&pi);
3354 	pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3355 	pi.ipi_pidx = pidx;
3356 	pi.ipi_qsidx = txq->ift_id;
3357 	pi.ipi_len = m_head->m_pkthdr.len;
3358 	pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3359 	pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3360 
3361 	/* deliberate bitwise OR to make one condition */
3362 	if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3363 		if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3364 			DBG_COUNTER_INC(encap_txd_encap_fail);
3365 			return (err);
3366 		}
3367 		m_head = *m_headp;
3368 	}
3369 
3370 retry:
3371 	err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3372 	    BUS_DMA_NOWAIT);
3373 defrag:
3374 	if (__predict_false(err)) {
3375 		switch (err) {
3376 		case EFBIG:
3377 			/* try collapse once and defrag once */
3378 			if (remap == 0) {
3379 				m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3380 				/* try defrag if collapsing fails */
3381 				if (m_head == NULL)
3382 					remap++;
3383 			}
3384 			if (remap == 1) {
3385 				txq->ift_mbuf_defrag++;
3386 				m_head = m_defrag(*m_headp, M_NOWAIT);
3387 			}
3388 			/*
3389 			 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3390 			 * failed to map an mbuf that was run through m_defrag
3391 			 */
3392 			MPASS(remap <= 1);
3393 			if (__predict_false(m_head == NULL || remap > 1))
3394 				goto defrag_failed;
3395 			remap++;
3396 			*m_headp = m_head;
3397 			goto retry;
3398 			break;
3399 		case ENOMEM:
3400 			txq->ift_no_tx_dma_setup++;
3401 			break;
3402 		default:
3403 			txq->ift_no_tx_dma_setup++;
3404 			m_freem(*m_headp);
3405 			DBG_COUNTER_INC(tx_frees);
3406 			*m_headp = NULL;
3407 			break;
3408 		}
3409 		txq->ift_map_failed++;
3410 		DBG_COUNTER_INC(encap_load_mbuf_fail);
3411 		DBG_COUNTER_INC(encap_txd_encap_fail);
3412 		return (err);
3413 	}
3414 	ifsd_m[pidx] = m_head;
3415 	/*
3416 	 * XXX assumes a 1 to 1 relationship between segments and
3417 	 *        descriptors - this does not hold true on all drivers, e.g.
3418 	 *        cxgb
3419 	 */
3420 	if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3421 		txq->ift_no_desc_avail++;
3422 		bus_dmamap_unload(buf_tag, map);
3423 		DBG_COUNTER_INC(encap_txq_avail_fail);
3424 		DBG_COUNTER_INC(encap_txd_encap_fail);
3425 		if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3426 			GROUPTASK_ENQUEUE(&txq->ift_task);
3427 		return (ENOBUFS);
3428 	}
3429 	/*
3430 	 * On Intel cards we can greatly reduce the number of TX interrupts
3431 	 * we see by only setting report status on every Nth descriptor.
3432 	 * However, this also means that the driver will need to keep track
3433 	 * of the descriptors that RS was set on to check them for the DD bit.
3434 	 */
3435 	txq->ift_rs_pending += nsegs + 1;
3436 	if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3437 	     iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3438 		pi.ipi_flags |= IPI_TX_INTR;
3439 		txq->ift_rs_pending = 0;
3440 	}
3441 
3442 	pi.ipi_segs = segs;
3443 	pi.ipi_nsegs = nsegs;
3444 
3445 	MPASS(pidx >= 0 && pidx < txq->ift_size);
3446 #ifdef PKT_DEBUG
3447 	print_pkt(&pi);
3448 #endif
3449 	if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3450 		bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3451 		DBG_COUNTER_INC(tx_encap);
3452 		MPASS(pi.ipi_new_pidx < txq->ift_size);
3453 
3454 		ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3455 		if (pi.ipi_new_pidx < pi.ipi_pidx) {
3456 			ndesc += txq->ift_size;
3457 			txq->ift_gen = 1;
3458 		}
3459 		/*
3460 		 * drivers can need as many as
3461 		 * two sentinels
3462 		 */
3463 		MPASS(ndesc <= pi.ipi_nsegs + 2);
3464 		MPASS(pi.ipi_new_pidx != pidx);
3465 		MPASS(ndesc > 0);
3466 		txq->ift_in_use += ndesc;
3467 
3468 		/*
3469 		 * We update the last software descriptor again here because there may
3470 		 * be a sentinel and/or there may be more mbufs than segments
3471 		 */
3472 		txq->ift_pidx = pi.ipi_new_pidx;
3473 		txq->ift_npending += pi.ipi_ndescs;
3474 	} else {
3475 		*m_headp = m_head = iflib_remove_mbuf(txq);
3476 		if (err == EFBIG) {
3477 			txq->ift_txd_encap_efbig++;
3478 			if (remap < 2) {
3479 				remap = 1;
3480 				goto defrag;
3481 			}
3482 		}
3483 		goto defrag_failed;
3484 	}
3485 	/*
3486 	 * err can't possibly be non-zero here, so we don't neet to test it
3487 	 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3488 	 */
3489 	return (err);
3490 
3491 defrag_failed:
3492 	txq->ift_mbuf_defrag_failed++;
3493 	txq->ift_map_failed++;
3494 	m_freem(*m_headp);
3495 	DBG_COUNTER_INC(tx_frees);
3496 	*m_headp = NULL;
3497 	DBG_COUNTER_INC(encap_txd_encap_fail);
3498 	return (ENOMEM);
3499 }
3500 
3501 static void
3502 iflib_tx_desc_free(iflib_txq_t txq, int n)
3503 {
3504 	uint32_t qsize, cidx, mask, gen;
3505 	struct mbuf *m, **ifsd_m;
3506 	bool do_prefetch;
3507 
3508 	cidx = txq->ift_cidx;
3509 	gen = txq->ift_gen;
3510 	qsize = txq->ift_size;
3511 	mask = qsize-1;
3512 	ifsd_m = txq->ift_sds.ifsd_m;
3513 	do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3514 
3515 	while (n-- > 0) {
3516 		if (do_prefetch) {
3517 			prefetch(ifsd_m[(cidx + 3) & mask]);
3518 			prefetch(ifsd_m[(cidx + 4) & mask]);
3519 		}
3520 		if ((m = ifsd_m[cidx]) != NULL) {
3521 			prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3522 			if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3523 				bus_dmamap_sync(txq->ift_tso_buf_tag,
3524 				    txq->ift_sds.ifsd_tso_map[cidx],
3525 				    BUS_DMASYNC_POSTWRITE);
3526 				bus_dmamap_unload(txq->ift_tso_buf_tag,
3527 				    txq->ift_sds.ifsd_tso_map[cidx]);
3528 			} else {
3529 				bus_dmamap_sync(txq->ift_buf_tag,
3530 				    txq->ift_sds.ifsd_map[cidx],
3531 				    BUS_DMASYNC_POSTWRITE);
3532 				bus_dmamap_unload(txq->ift_buf_tag,
3533 				    txq->ift_sds.ifsd_map[cidx]);
3534 			}
3535 			/* XXX we don't support any drivers that batch packets yet */
3536 			MPASS(m->m_nextpkt == NULL);
3537 			m_freem(m);
3538 			ifsd_m[cidx] = NULL;
3539 #if MEMORY_LOGGING
3540 			txq->ift_dequeued++;
3541 #endif
3542 			DBG_COUNTER_INC(tx_frees);
3543 		}
3544 		if (__predict_false(++cidx == qsize)) {
3545 			cidx = 0;
3546 			gen = 0;
3547 		}
3548 	}
3549 	txq->ift_cidx = cidx;
3550 	txq->ift_gen = gen;
3551 }
3552 
3553 static __inline int
3554 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3555 {
3556 	int reclaim;
3557 	if_ctx_t ctx = txq->ift_ctx;
3558 
3559 	KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3560 	MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3561 
3562 	/*
3563 	 * Need a rate-limiting check so that this isn't called every time
3564 	 */
3565 	iflib_tx_credits_update(ctx, txq);
3566 	reclaim = DESC_RECLAIMABLE(txq);
3567 
3568 	if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3569 #ifdef INVARIANTS
3570 		if (iflib_verbose_debug) {
3571 			printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3572 			       txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3573 			       reclaim, thresh);
3574 
3575 		}
3576 #endif
3577 		return (0);
3578 	}
3579 	iflib_tx_desc_free(txq, reclaim);
3580 	txq->ift_cleaned += reclaim;
3581 	txq->ift_in_use -= reclaim;
3582 
3583 	return (reclaim);
3584 }
3585 
3586 static struct mbuf **
3587 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3588 {
3589 	int next, size;
3590 	struct mbuf **items;
3591 
3592 	size = r->size;
3593 	next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3594 	items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3595 
3596 	prefetch(items[(cidx + offset) & (size-1)]);
3597 	if (remaining > 1) {
3598 		prefetch2cachelines(&items[next]);
3599 		prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3600 		prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3601 		prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3602 	}
3603 	return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3604 }
3605 
3606 static void
3607 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3608 {
3609 
3610 	ifmp_ring_check_drainage(txq->ift_br, budget);
3611 }
3612 
3613 static uint32_t
3614 iflib_txq_can_drain(struct ifmp_ring *r)
3615 {
3616 	iflib_txq_t txq = r->cookie;
3617 	if_ctx_t ctx = txq->ift_ctx;
3618 
3619 	if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3620 		return (1);
3621 	bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3622 	    BUS_DMASYNC_POSTREAD);
3623 	return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3624 	    false));
3625 }
3626 
3627 static uint32_t
3628 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3629 {
3630 	iflib_txq_t txq = r->cookie;
3631 	if_ctx_t ctx = txq->ift_ctx;
3632 	if_t ifp = ctx->ifc_ifp;
3633 	struct mbuf *m, **mp;
3634 	int avail, bytes_sent, consumed, count, err, i, in_use_prev;
3635 	int mcast_sent, pkt_sent, reclaimed, txq_avail;
3636 	bool do_prefetch, rang, ring;
3637 
3638 	if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3639 			    !LINK_ACTIVE(ctx))) {
3640 		DBG_COUNTER_INC(txq_drain_notready);
3641 		return (0);
3642 	}
3643 	reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3644 	rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3645 	avail = IDXDIFF(pidx, cidx, r->size);
3646 	if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3647 		DBG_COUNTER_INC(txq_drain_flushing);
3648 		for (i = 0; i < avail; i++) {
3649 			if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3650 				m_free(r->items[(cidx + i) & (r->size-1)]);
3651 			r->items[(cidx + i) & (r->size-1)] = NULL;
3652 		}
3653 		return (avail);
3654 	}
3655 
3656 	if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3657 		txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3658 		CALLOUT_LOCK(txq);
3659 		callout_stop(&txq->ift_timer);
3660 		CALLOUT_UNLOCK(txq);
3661 		DBG_COUNTER_INC(txq_drain_oactive);
3662 		return (0);
3663 	}
3664 	if (reclaimed)
3665 		txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3666 	consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3667 	count = MIN(avail, TX_BATCH_SIZE);
3668 #ifdef INVARIANTS
3669 	if (iflib_verbose_debug)
3670 		printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3671 		       avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3672 #endif
3673 	do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3674 	txq_avail = TXQ_AVAIL(txq);
3675 	err = 0;
3676 	for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) {
3677 		int rem = do_prefetch ? count - i : 0;
3678 
3679 		mp = _ring_peek_one(r, cidx, i, rem);
3680 		MPASS(mp != NULL && *mp != NULL);
3681 		if (__predict_false(*mp == (struct mbuf *)txq)) {
3682 			consumed++;
3683 			continue;
3684 		}
3685 		in_use_prev = txq->ift_in_use;
3686 		err = iflib_encap(txq, mp);
3687 		if (__predict_false(err)) {
3688 			/* no room - bail out */
3689 			if (err == ENOBUFS)
3690 				break;
3691 			consumed++;
3692 			/* we can't send this packet - skip it */
3693 			continue;
3694 		}
3695 		consumed++;
3696 		pkt_sent++;
3697 		m = *mp;
3698 		DBG_COUNTER_INC(tx_sent);
3699 		bytes_sent += m->m_pkthdr.len;
3700 		mcast_sent += !!(m->m_flags & M_MCAST);
3701 		txq_avail = TXQ_AVAIL(txq);
3702 
3703 		txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3704 		ETHER_BPF_MTAP(ifp, m);
3705 		if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3706 			break;
3707 		rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3708 	}
3709 
3710 	/* deliberate use of bitwise or to avoid gratuitous short-circuit */
3711 	ring = rang ? false  : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3712 	iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3713 	if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3714 	if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3715 	if (mcast_sent)
3716 		if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3717 #ifdef INVARIANTS
3718 	if (iflib_verbose_debug)
3719 		printf("consumed=%d\n", consumed);
3720 #endif
3721 	return (consumed);
3722 }
3723 
3724 static uint32_t
3725 iflib_txq_drain_always(struct ifmp_ring *r)
3726 {
3727 	return (1);
3728 }
3729 
3730 static uint32_t
3731 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3732 {
3733 	int i, avail;
3734 	struct mbuf **mp;
3735 	iflib_txq_t txq;
3736 
3737 	txq = r->cookie;
3738 
3739 	txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3740 	CALLOUT_LOCK(txq);
3741 	callout_stop(&txq->ift_timer);
3742 	CALLOUT_UNLOCK(txq);
3743 
3744 	avail = IDXDIFF(pidx, cidx, r->size);
3745 	for (i = 0; i < avail; i++) {
3746 		mp = _ring_peek_one(r, cidx, i, avail - i);
3747 		if (__predict_false(*mp == (struct mbuf *)txq))
3748 			continue;
3749 		m_freem(*mp);
3750 		DBG_COUNTER_INC(tx_frees);
3751 	}
3752 	MPASS(ifmp_ring_is_stalled(r) == 0);
3753 	return (avail);
3754 }
3755 
3756 static void
3757 iflib_ifmp_purge(iflib_txq_t txq)
3758 {
3759 	struct ifmp_ring *r;
3760 
3761 	r = txq->ift_br;
3762 	r->drain = iflib_txq_drain_free;
3763 	r->can_drain = iflib_txq_drain_always;
3764 
3765 	ifmp_ring_check_drainage(r, r->size);
3766 
3767 	r->drain = iflib_txq_drain;
3768 	r->can_drain = iflib_txq_can_drain;
3769 }
3770 
3771 static void
3772 _task_fn_tx(void *context)
3773 {
3774 	iflib_txq_t txq = context;
3775 	if_ctx_t ctx = txq->ift_ctx;
3776 #if defined(ALTQ) || defined(DEV_NETMAP)
3777 	if_t ifp = ctx->ifc_ifp;
3778 #endif
3779 	int abdicate = ctx->ifc_sysctl_tx_abdicate;
3780 
3781 #ifdef IFLIB_DIAGNOSTICS
3782 	txq->ift_cpu_exec_count[curcpu]++;
3783 #endif
3784 	if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
3785 		return;
3786 #ifdef DEV_NETMAP
3787 	if (if_getcapenable(ifp) & IFCAP_NETMAP) {
3788 		bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3789 		    BUS_DMASYNC_POSTREAD);
3790 		if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false))
3791 			netmap_tx_irq(ifp, txq->ift_id);
3792 		if (ctx->ifc_flags & IFC_LEGACY)
3793 			IFDI_INTR_ENABLE(ctx);
3794 		else
3795 			IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3796 		return;
3797 	}
3798 #endif
3799 #ifdef ALTQ
3800 	if (ALTQ_IS_ENABLED(&ifp->if_snd))
3801 		iflib_altq_if_start(ifp);
3802 #endif
3803 	if (txq->ift_db_pending)
3804 		ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3805 	else if (!abdicate)
3806 		ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3807 	/*
3808 	 * When abdicating, we always need to check drainage, not just when we don't enqueue
3809 	 */
3810 	if (abdicate)
3811 		ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3812 	if (ctx->ifc_flags & IFC_LEGACY)
3813 		IFDI_INTR_ENABLE(ctx);
3814 	else
3815 		IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3816 }
3817 
3818 static void
3819 _task_fn_rx(void *context)
3820 {
3821 	iflib_rxq_t rxq = context;
3822 	if_ctx_t ctx = rxq->ifr_ctx;
3823 	uint8_t more;
3824 	uint16_t budget;
3825 
3826 #ifdef IFLIB_DIAGNOSTICS
3827 	rxq->ifr_cpu_exec_count[curcpu]++;
3828 #endif
3829 	DBG_COUNTER_INC(task_fn_rxs);
3830 	if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3831 		return;
3832 #ifdef DEV_NETMAP
3833 	if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) {
3834 		u_int work = 0;
3835 		if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) {
3836 			more = 0;
3837 			goto skip_rxeof;
3838 		}
3839 	}
3840 #endif
3841 	budget = ctx->ifc_sysctl_rx_budget;
3842 	if (budget == 0)
3843 		budget = 16;	/* XXX */
3844 	more = iflib_rxeof(rxq, budget);
3845 #ifdef DEV_NETMAP
3846 skip_rxeof:
3847 #endif
3848 	if ((more & IFLIB_RXEOF_MORE) == 0) {
3849 		if (ctx->ifc_flags & IFC_LEGACY)
3850 			IFDI_INTR_ENABLE(ctx);
3851 		else
3852 			IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3853 		DBG_COUNTER_INC(rx_intr_enables);
3854 	}
3855 	if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3856 		return;
3857 
3858 	if (more & IFLIB_RXEOF_MORE)
3859 		GROUPTASK_ENQUEUE(&rxq->ifr_task);
3860 	else if (more & IFLIB_RXEOF_EMPTY)
3861 		callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq);
3862 }
3863 
3864 static void
3865 _task_fn_admin(void *context)
3866 {
3867 	if_ctx_t ctx = context;
3868 	if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3869 	iflib_txq_t txq;
3870 	int i;
3871 	bool oactive, running, do_reset, do_watchdog, in_detach;
3872 	uint32_t reset_on = hz / 2;
3873 
3874 	STATE_LOCK(ctx);
3875 	running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3876 	oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3877 	do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3878 	do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3879 	in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3880 	ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3881 	STATE_UNLOCK(ctx);
3882 
3883 	if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3884 		return;
3885 	if (in_detach)
3886 		return;
3887 
3888 	CTX_LOCK(ctx);
3889 	for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3890 		CALLOUT_LOCK(txq);
3891 		callout_stop(&txq->ift_timer);
3892 		CALLOUT_UNLOCK(txq);
3893 	}
3894 	if (do_watchdog) {
3895 		ctx->ifc_watchdog_events++;
3896 		IFDI_WATCHDOG_RESET(ctx);
3897 	}
3898 	IFDI_UPDATE_ADMIN_STATUS(ctx);
3899 	for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3900 #ifdef DEV_NETMAP
3901 		reset_on = hz / 2;
3902 		if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3903 			iflib_netmap_timer_adjust(ctx, txq, &reset_on);
3904 #endif
3905 		callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3906 	}
3907 	IFDI_LINK_INTR_ENABLE(ctx);
3908 	if (do_reset)
3909 		iflib_if_init_locked(ctx);
3910 	CTX_UNLOCK(ctx);
3911 
3912 	if (LINK_ACTIVE(ctx) == 0)
3913 		return;
3914 	for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3915 		iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3916 }
3917 
3918 
3919 static void
3920 _task_fn_iov(void *context)
3921 {
3922 	if_ctx_t ctx = context;
3923 
3924 	if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3925 	    !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3926 		return;
3927 
3928 	CTX_LOCK(ctx);
3929 	IFDI_VFLR_HANDLE(ctx);
3930 	CTX_UNLOCK(ctx);
3931 }
3932 
3933 static int
3934 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3935 {
3936 	int err;
3937 	if_int_delay_info_t info;
3938 	if_ctx_t ctx;
3939 
3940 	info = (if_int_delay_info_t)arg1;
3941 	ctx = info->iidi_ctx;
3942 	info->iidi_req = req;
3943 	info->iidi_oidp = oidp;
3944 	CTX_LOCK(ctx);
3945 	err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3946 	CTX_UNLOCK(ctx);
3947 	return (err);
3948 }
3949 
3950 /*********************************************************************
3951  *
3952  *  IFNET FUNCTIONS
3953  *
3954  **********************************************************************/
3955 
3956 static void
3957 iflib_if_init_locked(if_ctx_t ctx)
3958 {
3959 	iflib_stop(ctx);
3960 	iflib_init_locked(ctx);
3961 }
3962 
3963 
3964 static void
3965 iflib_if_init(void *arg)
3966 {
3967 	if_ctx_t ctx = arg;
3968 
3969 	CTX_LOCK(ctx);
3970 	iflib_if_init_locked(ctx);
3971 	CTX_UNLOCK(ctx);
3972 }
3973 
3974 static int
3975 iflib_if_transmit(if_t ifp, struct mbuf *m)
3976 {
3977 	if_ctx_t	ctx = if_getsoftc(ifp);
3978 
3979 	iflib_txq_t txq;
3980 	int err, qidx;
3981 	int abdicate = ctx->ifc_sysctl_tx_abdicate;
3982 
3983 	if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3984 		DBG_COUNTER_INC(tx_frees);
3985 		m_freem(m);
3986 		return (ENETDOWN);
3987 	}
3988 
3989 	MPASS(m->m_nextpkt == NULL);
3990 	/* ALTQ-enabled interfaces always use queue 0. */
3991 	qidx = 0;
3992 	if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3993 		qidx = QIDX(ctx, m);
3994 	/*
3995 	 * XXX calculate buf_ring based on flowid (divvy up bits?)
3996 	 */
3997 	txq = &ctx->ifc_txqs[qidx];
3998 
3999 #ifdef DRIVER_BACKPRESSURE
4000 	if (txq->ift_closed) {
4001 		while (m != NULL) {
4002 			next = m->m_nextpkt;
4003 			m->m_nextpkt = NULL;
4004 			m_freem(m);
4005 			DBG_COUNTER_INC(tx_frees);
4006 			m = next;
4007 		}
4008 		return (ENOBUFS);
4009 	}
4010 #endif
4011 #ifdef notyet
4012 	qidx = count = 0;
4013 	mp = marr;
4014 	next = m;
4015 	do {
4016 		count++;
4017 		next = next->m_nextpkt;
4018 	} while (next != NULL);
4019 
4020 	if (count > nitems(marr))
4021 		if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
4022 			/* XXX check nextpkt */
4023 			m_freem(m);
4024 			/* XXX simplify for now */
4025 			DBG_COUNTER_INC(tx_frees);
4026 			return (ENOBUFS);
4027 		}
4028 	for (next = m, i = 0; next != NULL; i++) {
4029 		mp[i] = next;
4030 		next = next->m_nextpkt;
4031 		mp[i]->m_nextpkt = NULL;
4032 	}
4033 #endif
4034 	DBG_COUNTER_INC(tx_seen);
4035 	err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
4036 
4037 	if (abdicate)
4038 		GROUPTASK_ENQUEUE(&txq->ift_task);
4039  	if (err) {
4040 		if (!abdicate)
4041 			GROUPTASK_ENQUEUE(&txq->ift_task);
4042 		/* support forthcoming later */
4043 #ifdef DRIVER_BACKPRESSURE
4044 		txq->ift_closed = TRUE;
4045 #endif
4046 		ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4047 		m_freem(m);
4048 		DBG_COUNTER_INC(tx_frees);
4049 	}
4050 
4051 	return (err);
4052 }
4053 
4054 #ifdef ALTQ
4055 /*
4056  * The overall approach to integrating iflib with ALTQ is to continue to use
4057  * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4058  * ring.  Technically, when using ALTQ, queueing to an intermediate mp_ring
4059  * is redundant/unnecessary, but doing so minimizes the amount of
4060  * ALTQ-specific code required in iflib.  It is assumed that the overhead of
4061  * redundantly queueing to an intermediate mp_ring is swamped by the
4062  * performance limitations inherent in using ALTQ.
4063  *
4064  * When ALTQ support is compiled in, all iflib drivers will use a transmit
4065  * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4066  * given interface.  If ALTQ is enabled for an interface, then all
4067  * transmitted packets for that interface will be submitted to the ALTQ
4068  * subsystem via IFQ_ENQUEUE().  We don't use the legacy if_transmit()
4069  * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4070  * update stats that the iflib machinery handles, and which is sensitve to
4071  * the disused IFF_DRV_OACTIVE flag.  Additionally, iflib_altq_if_start()
4072  * will be installed as the start routine for use by ALTQ facilities that
4073  * need to trigger queue drains on a scheduled basis.
4074  *
4075  */
4076 static void
4077 iflib_altq_if_start(if_t ifp)
4078 {
4079 	struct ifaltq *ifq = &ifp->if_snd;
4080 	struct mbuf *m;
4081 
4082 	IFQ_LOCK(ifq);
4083 	IFQ_DEQUEUE_NOLOCK(ifq, m);
4084 	while (m != NULL) {
4085 		iflib_if_transmit(ifp, m);
4086 		IFQ_DEQUEUE_NOLOCK(ifq, m);
4087 	}
4088 	IFQ_UNLOCK(ifq);
4089 }
4090 
4091 static int
4092 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4093 {
4094 	int err;
4095 
4096 	if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4097 		IFQ_ENQUEUE(&ifp->if_snd, m, err);
4098 		if (err == 0)
4099 			iflib_altq_if_start(ifp);
4100 	} else
4101 		err = iflib_if_transmit(ifp, m);
4102 
4103 	return (err);
4104 }
4105 #endif /* ALTQ */
4106 
4107 static void
4108 iflib_if_qflush(if_t ifp)
4109 {
4110 	if_ctx_t ctx = if_getsoftc(ifp);
4111 	iflib_txq_t txq = ctx->ifc_txqs;
4112 	int i;
4113 
4114 	STATE_LOCK(ctx);
4115 	ctx->ifc_flags |= IFC_QFLUSH;
4116 	STATE_UNLOCK(ctx);
4117 	for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4118 		while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4119 			iflib_txq_check_drain(txq, 0);
4120 	STATE_LOCK(ctx);
4121 	ctx->ifc_flags &= ~IFC_QFLUSH;
4122 	STATE_UNLOCK(ctx);
4123 
4124 	/*
4125 	 * When ALTQ is enabled, this will also take care of purging the
4126 	 * ALTQ queue(s).
4127 	 */
4128 	if_qflush(ifp);
4129 }
4130 
4131 
4132 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4133 		     IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4134 		     IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4135 		     IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP)
4136 
4137 static int
4138 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4139 {
4140 	if_ctx_t ctx = if_getsoftc(ifp);
4141 	struct ifreq	*ifr = (struct ifreq *)data;
4142 #if defined(INET) || defined(INET6)
4143 	struct ifaddr	*ifa = (struct ifaddr *)data;
4144 #endif
4145 	bool		avoid_reset = false;
4146 	int		err = 0, reinit = 0, bits;
4147 
4148 	switch (command) {
4149 	case SIOCSIFADDR:
4150 #ifdef INET
4151 		if (ifa->ifa_addr->sa_family == AF_INET)
4152 			avoid_reset = true;
4153 #endif
4154 #ifdef INET6
4155 		if (ifa->ifa_addr->sa_family == AF_INET6)
4156 			avoid_reset = true;
4157 #endif
4158 		/*
4159 		** Calling init results in link renegotiation,
4160 		** so we avoid doing it when possible.
4161 		*/
4162 		if (avoid_reset) {
4163 			if_setflagbits(ifp, IFF_UP,0);
4164 			if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4165 				reinit = 1;
4166 #ifdef INET
4167 			if (!(if_getflags(ifp) & IFF_NOARP))
4168 				arp_ifinit(ifp, ifa);
4169 #endif
4170 		} else
4171 			err = ether_ioctl(ifp, command, data);
4172 		break;
4173 	case SIOCSIFMTU:
4174 		CTX_LOCK(ctx);
4175 		if (ifr->ifr_mtu == if_getmtu(ifp)) {
4176 			CTX_UNLOCK(ctx);
4177 			break;
4178 		}
4179 		bits = if_getdrvflags(ifp);
4180 		/* stop the driver and free any clusters before proceeding */
4181 		iflib_stop(ctx);
4182 
4183 		if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4184 			STATE_LOCK(ctx);
4185 			if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4186 				ctx->ifc_flags |= IFC_MULTISEG;
4187 			else
4188 				ctx->ifc_flags &= ~IFC_MULTISEG;
4189 			STATE_UNLOCK(ctx);
4190 			err = if_setmtu(ifp, ifr->ifr_mtu);
4191 		}
4192 		iflib_init_locked(ctx);
4193 		STATE_LOCK(ctx);
4194 		if_setdrvflags(ifp, bits);
4195 		STATE_UNLOCK(ctx);
4196 		CTX_UNLOCK(ctx);
4197 		break;
4198 	case SIOCSIFFLAGS:
4199 		CTX_LOCK(ctx);
4200 		if (if_getflags(ifp) & IFF_UP) {
4201 			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4202 				if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4203 				    (IFF_PROMISC | IFF_ALLMULTI)) {
4204 					err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4205 				}
4206 			} else
4207 				reinit = 1;
4208 		} else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4209 			iflib_stop(ctx);
4210 		}
4211 		ctx->ifc_if_flags = if_getflags(ifp);
4212 		CTX_UNLOCK(ctx);
4213 		break;
4214 	case SIOCADDMULTI:
4215 	case SIOCDELMULTI:
4216 		if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4217 			CTX_LOCK(ctx);
4218 			IFDI_INTR_DISABLE(ctx);
4219 			IFDI_MULTI_SET(ctx);
4220 			IFDI_INTR_ENABLE(ctx);
4221 			CTX_UNLOCK(ctx);
4222 		}
4223 		break;
4224 	case SIOCSIFMEDIA:
4225 		CTX_LOCK(ctx);
4226 		IFDI_MEDIA_SET(ctx);
4227 		CTX_UNLOCK(ctx);
4228 		/* FALLTHROUGH */
4229 	case SIOCGIFMEDIA:
4230 	case SIOCGIFXMEDIA:
4231 		err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4232 		break;
4233 	case SIOCGI2C:
4234 	{
4235 		struct ifi2creq i2c;
4236 
4237 		err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4238 		if (err != 0)
4239 			break;
4240 		if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4241 			err = EINVAL;
4242 			break;
4243 		}
4244 		if (i2c.len > sizeof(i2c.data)) {
4245 			err = EINVAL;
4246 			break;
4247 		}
4248 
4249 		if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4250 			err = copyout(&i2c, ifr_data_get_ptr(ifr),
4251 			    sizeof(i2c));
4252 		break;
4253 	}
4254 	case SIOCSIFCAP:
4255 	{
4256 		int mask, setmask, oldmask;
4257 
4258 		oldmask = if_getcapenable(ifp);
4259 		mask = ifr->ifr_reqcap ^ oldmask;
4260 		mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP;
4261 		setmask = 0;
4262 #ifdef TCP_OFFLOAD
4263 		setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4264 #endif
4265 		setmask |= (mask & IFCAP_FLAGS);
4266 		setmask |= (mask & IFCAP_WOL);
4267 
4268 		/*
4269 		 * If any RX csum has changed, change all the ones that
4270 		 * are supported by the driver.
4271 		 */
4272 		if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4273 			setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4274 			    (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4275 		}
4276 
4277 		/*
4278 		 * want to ensure that traffic has stopped before we change any of the flags
4279 		 */
4280 		if (setmask) {
4281 			CTX_LOCK(ctx);
4282 			bits = if_getdrvflags(ifp);
4283 			if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4284 				iflib_stop(ctx);
4285 			STATE_LOCK(ctx);
4286 			if_togglecapenable(ifp, setmask);
4287 			STATE_UNLOCK(ctx);
4288 			if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4289 				iflib_init_locked(ctx);
4290 			STATE_LOCK(ctx);
4291 			if_setdrvflags(ifp, bits);
4292 			STATE_UNLOCK(ctx);
4293 			CTX_UNLOCK(ctx);
4294 		}
4295 		if_vlancap(ifp);
4296 		break;
4297 	}
4298 	case SIOCGPRIVATE_0:
4299 	case SIOCSDRVSPEC:
4300 	case SIOCGDRVSPEC:
4301 		CTX_LOCK(ctx);
4302 		err = IFDI_PRIV_IOCTL(ctx, command, data);
4303 		CTX_UNLOCK(ctx);
4304 		break;
4305 	default:
4306 		err = ether_ioctl(ifp, command, data);
4307 		break;
4308 	}
4309 	if (reinit)
4310 		iflib_if_init(ctx);
4311 	return (err);
4312 }
4313 
4314 static uint64_t
4315 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4316 {
4317 	if_ctx_t ctx = if_getsoftc(ifp);
4318 
4319 	return (IFDI_GET_COUNTER(ctx, cnt));
4320 }
4321 
4322 /*********************************************************************
4323  *
4324  *  OTHER FUNCTIONS EXPORTED TO THE STACK
4325  *
4326  **********************************************************************/
4327 
4328 static void
4329 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4330 {
4331 	if_ctx_t ctx = if_getsoftc(ifp);
4332 
4333 	if ((void *)ctx != arg)
4334 		return;
4335 
4336 	if ((vtag == 0) || (vtag > 4095))
4337 		return;
4338 
4339 	if (iflib_in_detach(ctx))
4340 		return;
4341 
4342 	CTX_LOCK(ctx);
4343 	IFDI_VLAN_REGISTER(ctx, vtag);
4344 	/* Re-init to load the changes */
4345 	if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4346 		iflib_if_init_locked(ctx);
4347 	CTX_UNLOCK(ctx);
4348 }
4349 
4350 static void
4351 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4352 {
4353 	if_ctx_t ctx = if_getsoftc(ifp);
4354 
4355 	if ((void *)ctx != arg)
4356 		return;
4357 
4358 	if ((vtag == 0) || (vtag > 4095))
4359 		return;
4360 
4361 	CTX_LOCK(ctx);
4362 	IFDI_VLAN_UNREGISTER(ctx, vtag);
4363 	/* Re-init to load the changes */
4364 	if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
4365 		iflib_if_init_locked(ctx);
4366 	CTX_UNLOCK(ctx);
4367 }
4368 
4369 static void
4370 iflib_led_func(void *arg, int onoff)
4371 {
4372 	if_ctx_t ctx = arg;
4373 
4374 	CTX_LOCK(ctx);
4375 	IFDI_LED_FUNC(ctx, onoff);
4376 	CTX_UNLOCK(ctx);
4377 }
4378 
4379 /*********************************************************************
4380  *
4381  *  BUS FUNCTION DEFINITIONS
4382  *
4383  **********************************************************************/
4384 
4385 int
4386 iflib_device_probe(device_t dev)
4387 {
4388 	const pci_vendor_info_t *ent;
4389 	if_shared_ctx_t sctx;
4390 	uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id;
4391 	uint16_t pci_vendor_id;
4392 
4393 	if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4394 		return (ENOTSUP);
4395 
4396 	pci_vendor_id = pci_get_vendor(dev);
4397 	pci_device_id = pci_get_device(dev);
4398 	pci_subvendor_id = pci_get_subvendor(dev);
4399 	pci_subdevice_id = pci_get_subdevice(dev);
4400 	pci_rev_id = pci_get_revid(dev);
4401 	if (sctx->isc_parse_devinfo != NULL)
4402 		sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4403 
4404 	ent = sctx->isc_vendor_info;
4405 	while (ent->pvi_vendor_id != 0) {
4406 		if (pci_vendor_id != ent->pvi_vendor_id) {
4407 			ent++;
4408 			continue;
4409 		}
4410 		if ((pci_device_id == ent->pvi_device_id) &&
4411 		    ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4412 		     (ent->pvi_subvendor_id == 0)) &&
4413 		    ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4414 		     (ent->pvi_subdevice_id == 0)) &&
4415 		    ((pci_rev_id == ent->pvi_rev_id) ||
4416 		     (ent->pvi_rev_id == 0))) {
4417 
4418 			device_set_desc_copy(dev, ent->pvi_name);
4419 			/* this needs to be changed to zero if the bus probing code
4420 			 * ever stops re-probing on best match because the sctx
4421 			 * may have its values over written by register calls
4422 			 * in subsequent probes
4423 			 */
4424 			return (BUS_PROBE_DEFAULT);
4425 		}
4426 		ent++;
4427 	}
4428 	return (ENXIO);
4429 }
4430 
4431 int
4432 iflib_device_probe_vendor(device_t dev)
4433 {
4434 	int probe;
4435 
4436 	probe = iflib_device_probe(dev);
4437 	if (probe == BUS_PROBE_DEFAULT)
4438 		return (BUS_PROBE_VENDOR);
4439 	else
4440 		return (probe);
4441 }
4442 
4443 static void
4444 iflib_reset_qvalues(if_ctx_t ctx)
4445 {
4446 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4447 	if_shared_ctx_t sctx = ctx->ifc_sctx;
4448 	device_t dev = ctx->ifc_dev;
4449 	int i;
4450 
4451 	if (ctx->ifc_sysctl_ntxqs != 0)
4452 		scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4453 	if (ctx->ifc_sysctl_nrxqs != 0)
4454 		scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4455 
4456 	for (i = 0; i < sctx->isc_ntxqs; i++) {
4457 		if (ctx->ifc_sysctl_ntxds[i] != 0)
4458 			scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4459 		else
4460 			scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4461 	}
4462 
4463 	for (i = 0; i < sctx->isc_nrxqs; i++) {
4464 		if (ctx->ifc_sysctl_nrxds[i] != 0)
4465 			scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4466 		else
4467 			scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4468 	}
4469 
4470 	for (i = 0; i < sctx->isc_nrxqs; i++) {
4471 		if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4472 			device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4473 				      i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4474 			scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4475 		}
4476 		if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4477 			device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4478 				      i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4479 			scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4480 		}
4481 		if (!powerof2(scctx->isc_nrxd[i])) {
4482 			device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4483 				      i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4484 			scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4485 		}
4486 	}
4487 
4488 	for (i = 0; i < sctx->isc_ntxqs; i++) {
4489 		if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4490 			device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4491 				      i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4492 			scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4493 		}
4494 		if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4495 			device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4496 				      i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4497 			scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4498 		}
4499 		if (!powerof2(scctx->isc_ntxd[i])) {
4500 			device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4501 				      i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4502 			scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4503 		}
4504 	}
4505 }
4506 
4507 static void
4508 iflib_add_pfil(if_ctx_t ctx)
4509 {
4510 	struct pfil_head *pfil;
4511 	struct pfil_head_args pa;
4512 	iflib_rxq_t rxq;
4513 	int i;
4514 
4515 	pa.pa_version = PFIL_VERSION;
4516 	pa.pa_flags = PFIL_IN;
4517 	pa.pa_type = PFIL_TYPE_ETHERNET;
4518 	pa.pa_headname = ctx->ifc_ifp->if_xname;
4519 	pfil = pfil_head_register(&pa);
4520 
4521 	for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4522 		rxq->pfil = pfil;
4523 	}
4524 }
4525 
4526 static void
4527 iflib_rem_pfil(if_ctx_t ctx)
4528 {
4529 	struct pfil_head *pfil;
4530 	iflib_rxq_t rxq;
4531 	int i;
4532 
4533 	rxq = ctx->ifc_rxqs;
4534 	pfil = rxq->pfil;
4535 	for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4536 		rxq->pfil = NULL;
4537 	}
4538 	pfil_head_unregister(pfil);
4539 }
4540 
4541 static uint16_t
4542 get_ctx_core_offset(if_ctx_t ctx)
4543 {
4544 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4545 	struct cpu_offset *op;
4546 	uint16_t qc;
4547 	uint16_t ret = ctx->ifc_sysctl_core_offset;
4548 
4549 	if (ret != CORE_OFFSET_UNSPECIFIED)
4550 		return (ret);
4551 
4552 	if (ctx->ifc_sysctl_separate_txrx)
4553 		qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets;
4554 	else
4555 		qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets);
4556 
4557 	mtx_lock(&cpu_offset_mtx);
4558 	SLIST_FOREACH(op, &cpu_offsets, entries) {
4559 		if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4560 			ret = op->offset;
4561 			op->offset += qc;
4562 			MPASS(op->refcount < UINT_MAX);
4563 			op->refcount++;
4564 			break;
4565 		}
4566 	}
4567 	if (ret == CORE_OFFSET_UNSPECIFIED) {
4568 		ret = 0;
4569 		op = malloc(sizeof(struct cpu_offset), M_IFLIB,
4570 		    M_NOWAIT | M_ZERO);
4571 		if (op == NULL) {
4572 			device_printf(ctx->ifc_dev,
4573 			    "allocation for cpu offset failed.\n");
4574 		} else {
4575 			op->offset = qc;
4576 			op->refcount = 1;
4577 			CPU_COPY(&ctx->ifc_cpus, &op->set);
4578 			SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
4579 		}
4580 	}
4581 	mtx_unlock(&cpu_offset_mtx);
4582 
4583 	return (ret);
4584 }
4585 
4586 static void
4587 unref_ctx_core_offset(if_ctx_t ctx)
4588 {
4589 	struct cpu_offset *op, *top;
4590 
4591 	mtx_lock(&cpu_offset_mtx);
4592 	SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
4593 		if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4594 			MPASS(op->refcount > 0);
4595 			op->refcount--;
4596 			if (op->refcount == 0) {
4597 				SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
4598 				free(op, M_IFLIB);
4599 			}
4600 			break;
4601 		}
4602 	}
4603 	mtx_unlock(&cpu_offset_mtx);
4604 }
4605 
4606 int
4607 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4608 {
4609 	if_ctx_t ctx;
4610 	if_t ifp;
4611 	if_softc_ctx_t scctx;
4612 	kobjop_desc_t kobj_desc;
4613 	kobj_method_t *kobj_method;
4614 	int err, msix, rid;
4615 	uint16_t main_rxq, main_txq;
4616 
4617 	ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4618 
4619 	if (sc == NULL) {
4620 		sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4621 		device_set_softc(dev, ctx);
4622 		ctx->ifc_flags |= IFC_SC_ALLOCATED;
4623 	}
4624 
4625 	ctx->ifc_sctx = sctx;
4626 	ctx->ifc_dev = dev;
4627 	ctx->ifc_softc = sc;
4628 
4629 	if ((err = iflib_register(ctx)) != 0) {
4630 		device_printf(dev, "iflib_register failed %d\n", err);
4631 		goto fail_ctx_free;
4632 	}
4633 	iflib_add_device_sysctl_pre(ctx);
4634 
4635 	scctx = &ctx->ifc_softc_ctx;
4636 	ifp = ctx->ifc_ifp;
4637 
4638 	iflib_reset_qvalues(ctx);
4639 	CTX_LOCK(ctx);
4640 	if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4641 		device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4642 		goto fail_unlock;
4643 	}
4644 	_iflib_pre_assert(scctx);
4645 	ctx->ifc_txrx = *scctx->isc_txrx;
4646 
4647 	if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
4648 		ctx->ifc_mediap = scctx->isc_media;
4649 
4650 #ifdef INVARIANTS
4651 	if (scctx->isc_capabilities & IFCAP_TXCSUM)
4652 		MPASS(scctx->isc_tx_csum_flags);
4653 #endif
4654 
4655 	if_setcapabilities(ifp,
4656 	    scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP);
4657 	if_setcapenable(ifp,
4658 	    scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP);
4659 
4660 	if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4661 		scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4662 	if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4663 		scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4664 
4665 	main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4666 	main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4667 
4668 	/* XXX change for per-queue sizes */
4669 	device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4670 	    scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4671 
4672 	if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4673 	    MAX_SINGLE_PACKET_FRACTION)
4674 		scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4675 		    MAX_SINGLE_PACKET_FRACTION);
4676 	if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4677 	    MAX_SINGLE_PACKET_FRACTION)
4678 		scctx->isc_tx_tso_segments_max = max(1,
4679 		    scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4680 
4681 	/* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4682 	if (if_getcapabilities(ifp) & IFCAP_TSO) {
4683 		/*
4684 		 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4685 		 * but some MACs do.
4686 		 */
4687 		if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4688 		    IP_MAXPACKET));
4689 		/*
4690 		 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4691 		 * into account.  In the worst case, each of these calls will
4692 		 * add another mbuf and, thus, the requirement for another DMA
4693 		 * segment.  So for best performance, it doesn't make sense to
4694 		 * advertize a maximum of TSO segments that typically will
4695 		 * require defragmentation in iflib_encap().
4696 		 */
4697 		if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4698 		if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4699 	}
4700 	if (scctx->isc_rss_table_size == 0)
4701 		scctx->isc_rss_table_size = 64;
4702 	scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4703 
4704 	GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4705 	/* XXX format name */
4706 	taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4707 	    NULL, NULL, "admin");
4708 
4709 	/* Set up cpu set.  If it fails, use the set of all CPUs. */
4710 	if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4711 		device_printf(dev, "Unable to fetch CPU list\n");
4712 		CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4713 	}
4714 	MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4715 
4716 	/*
4717 	** Now set up MSI or MSI-X, should return us the number of supported
4718 	** vectors (will be 1 for a legacy interrupt and MSI).
4719 	*/
4720 	if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4721 		msix = scctx->isc_vectors;
4722 	} else if (scctx->isc_msix_bar != 0)
4723 	       /*
4724 		* The simple fact that isc_msix_bar is not 0 does not mean we
4725 		* we have a good value there that is known to work.
4726 		*/
4727 		msix = iflib_msix_init(ctx);
4728 	else {
4729 		scctx->isc_vectors = 1;
4730 		scctx->isc_ntxqsets = 1;
4731 		scctx->isc_nrxqsets = 1;
4732 		scctx->isc_intr = IFLIB_INTR_LEGACY;
4733 		msix = 0;
4734 	}
4735 	/* Get memory for the station queues */
4736 	if ((err = iflib_queues_alloc(ctx))) {
4737 		device_printf(dev, "Unable to allocate queue memory\n");
4738 		goto fail_intr_free;
4739 	}
4740 
4741 	if ((err = iflib_qset_structures_setup(ctx)))
4742 		goto fail_queues;
4743 
4744 	/*
4745 	 * Now that we know how many queues there are, get the core offset.
4746 	 */
4747 	ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
4748 
4749 	/*
4750 	 * Group taskqueues aren't properly set up until SMP is started,
4751 	 * so we disable interrupts until we can handle them post
4752 	 * SI_SUB_SMP.
4753 	 *
4754 	 * XXX: disabling interrupts doesn't actually work, at least for
4755 	 * the non-MSI case.  When they occur before SI_SUB_SMP completes,
4756 	 * we do null handling and depend on this not causing too large an
4757 	 * interrupt storm.
4758 	 */
4759 	IFDI_INTR_DISABLE(ctx);
4760 
4761 	if (msix > 1) {
4762 		/*
4763 		 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
4764 		 * aren't the default NULL implementation.
4765 		 */
4766 		kobj_desc = &ifdi_rx_queue_intr_enable_desc;
4767 		kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4768 		    kobj_desc);
4769 		if (kobj_method == &kobj_desc->deflt) {
4770 			device_printf(dev,
4771 			    "MSI-X requires ifdi_rx_queue_intr_enable method");
4772 			err = EOPNOTSUPP;
4773 			goto fail_queues;
4774 		}
4775 		kobj_desc = &ifdi_tx_queue_intr_enable_desc;
4776 		kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4777 		    kobj_desc);
4778 		if (kobj_method == &kobj_desc->deflt) {
4779 			device_printf(dev,
4780 			    "MSI-X requires ifdi_tx_queue_intr_enable method");
4781 			err = EOPNOTSUPP;
4782 			goto fail_queues;
4783 		}
4784 
4785 		/*
4786 		 * Assign the MSI-X vectors.
4787 		 * Note that the default NULL ifdi_msix_intr_assign method will
4788 		 * fail here, too.
4789 		 */
4790 		err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
4791 		if (err != 0) {
4792 			device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
4793 			    err);
4794 			goto fail_queues;
4795 		}
4796 	} else if (scctx->isc_intr != IFLIB_INTR_MSIX) {
4797 		rid = 0;
4798 		if (scctx->isc_intr == IFLIB_INTR_MSI) {
4799 			MPASS(msix == 1);
4800 			rid = 1;
4801 		}
4802 		if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4803 			device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4804 			goto fail_queues;
4805 		}
4806 	} else {
4807 		device_printf(dev,
4808 		    "Cannot use iflib with only 1 MSI-X interrupt!\n");
4809 		err = ENODEV;
4810 		goto fail_intr_free;
4811 	}
4812 
4813 	ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4814 
4815 	if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4816 		device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4817 		goto fail_detach;
4818 	}
4819 
4820 	/*
4821 	 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4822 	 * This must appear after the call to ether_ifattach() because
4823 	 * ether_ifattach() sets if_hdrlen to the default value.
4824 	 */
4825 	if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4826 		if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4827 
4828 	if ((err = iflib_netmap_attach(ctx))) {
4829 		device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4830 		goto fail_detach;
4831 	}
4832 	*ctxp = ctx;
4833 
4834 	DEBUGNET_SET(ctx->ifc_ifp, iflib);
4835 
4836 	if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4837 	iflib_add_device_sysctl_post(ctx);
4838 	iflib_add_pfil(ctx);
4839 	ctx->ifc_flags |= IFC_INIT_DONE;
4840 	CTX_UNLOCK(ctx);
4841 
4842 	return (0);
4843 
4844 fail_detach:
4845 	ether_ifdetach(ctx->ifc_ifp);
4846 fail_intr_free:
4847 	iflib_free_intr_mem(ctx);
4848 fail_queues:
4849 	iflib_tx_structures_free(ctx);
4850 	iflib_rx_structures_free(ctx);
4851 	taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task);
4852 	IFDI_DETACH(ctx);
4853 fail_unlock:
4854 	CTX_UNLOCK(ctx);
4855 	iflib_deregister(ctx);
4856 fail_ctx_free:
4857 	device_set_softc(ctx->ifc_dev, NULL);
4858         if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4859                 free(ctx->ifc_softc, M_IFLIB);
4860         free(ctx, M_IFLIB);
4861 	return (err);
4862 }
4863 
4864 int
4865 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4866 					  struct iflib_cloneattach_ctx *clctx)
4867 {
4868 	int err;
4869 	if_ctx_t ctx;
4870 	if_t ifp;
4871 	if_softc_ctx_t scctx;
4872 	int i;
4873 	void *sc;
4874 	uint16_t main_txq;
4875 	uint16_t main_rxq;
4876 
4877 	ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4878 	sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4879 	ctx->ifc_flags |= IFC_SC_ALLOCATED;
4880 	if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4881 		ctx->ifc_flags |= IFC_PSEUDO;
4882 
4883 	ctx->ifc_sctx = sctx;
4884 	ctx->ifc_softc = sc;
4885 	ctx->ifc_dev = dev;
4886 
4887 	if ((err = iflib_register(ctx)) != 0) {
4888 		device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4889 		goto fail_ctx_free;
4890 	}
4891 	iflib_add_device_sysctl_pre(ctx);
4892 
4893 	scctx = &ctx->ifc_softc_ctx;
4894 	ifp = ctx->ifc_ifp;
4895 
4896 	iflib_reset_qvalues(ctx);
4897 	CTX_LOCK(ctx);
4898 	if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4899 		device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4900 		goto fail_unlock;
4901 	}
4902 	if (sctx->isc_flags & IFLIB_GEN_MAC)
4903 		ether_gen_addr(ifp, &ctx->ifc_mac);
4904 	if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4905 								clctx->cc_params)) != 0) {
4906 		device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4907 		goto fail_ctx_free;
4908 	}
4909 	ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4910 	ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4911 	ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4912 
4913 #ifdef INVARIANTS
4914 	if (scctx->isc_capabilities & IFCAP_TXCSUM)
4915 		MPASS(scctx->isc_tx_csum_flags);
4916 #endif
4917 
4918 	if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4919 	if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4920 
4921 	ifp->if_flags |= IFF_NOGROUP;
4922 	if (sctx->isc_flags & IFLIB_PSEUDO) {
4923 		ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4924 
4925 		if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4926 			device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4927 			goto fail_detach;
4928 		}
4929 		*ctxp = ctx;
4930 
4931 		/*
4932 		 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4933 		 * This must appear after the call to ether_ifattach() because
4934 		 * ether_ifattach() sets if_hdrlen to the default value.
4935 		 */
4936 		if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4937 			if_setifheaderlen(ifp,
4938 			    sizeof(struct ether_vlan_header));
4939 
4940 		if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4941 		iflib_add_device_sysctl_post(ctx);
4942 		ctx->ifc_flags |= IFC_INIT_DONE;
4943 		return (0);
4944 	}
4945 	_iflib_pre_assert(scctx);
4946 	ctx->ifc_txrx = *scctx->isc_txrx;
4947 
4948 	if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4949 		scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4950 	if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4951 		scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4952 
4953 	main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
4954 	main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
4955 
4956 	/* XXX change for per-queue sizes */
4957 	device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4958 	    scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]);
4959 
4960 	if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] /
4961 	    MAX_SINGLE_PACKET_FRACTION)
4962 		scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] /
4963 		    MAX_SINGLE_PACKET_FRACTION);
4964 	if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] /
4965 	    MAX_SINGLE_PACKET_FRACTION)
4966 		scctx->isc_tx_tso_segments_max = max(1,
4967 		    scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION);
4968 
4969 	/* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4970 	if (if_getcapabilities(ifp) & IFCAP_TSO) {
4971 		/*
4972 		 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4973 		 * but some MACs do.
4974 		 */
4975 		if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4976 		    IP_MAXPACKET));
4977 		/*
4978 		 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4979 		 * into account.  In the worst case, each of these calls will
4980 		 * add another mbuf and, thus, the requirement for another DMA
4981 		 * segment.  So for best performance, it doesn't make sense to
4982 		 * advertize a maximum of TSO segments that typically will
4983 		 * require defragmentation in iflib_encap().
4984 		 */
4985 		if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4986 		if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4987 	}
4988 	if (scctx->isc_rss_table_size == 0)
4989 		scctx->isc_rss_table_size = 64;
4990 	scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4991 
4992 	GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4993 	/* XXX format name */
4994 	taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4995 	    NULL, NULL, "admin");
4996 
4997 	/* XXX --- can support > 1 -- but keep it simple for now */
4998 	scctx->isc_intr = IFLIB_INTR_LEGACY;
4999 
5000 	/* Get memory for the station queues */
5001 	if ((err = iflib_queues_alloc(ctx))) {
5002 		device_printf(dev, "Unable to allocate queue memory\n");
5003 		goto fail_iflib_detach;
5004 	}
5005 
5006 	if ((err = iflib_qset_structures_setup(ctx))) {
5007 		device_printf(dev, "qset structure setup failed %d\n", err);
5008 		goto fail_queues;
5009 	}
5010 
5011 	/*
5012 	 * XXX What if anything do we want to do about interrupts?
5013 	 */
5014 	ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
5015 	if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
5016 		device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
5017 		goto fail_detach;
5018 	}
5019 
5020 	/*
5021 	 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5022 	 * This must appear after the call to ether_ifattach() because
5023 	 * ether_ifattach() sets if_hdrlen to the default value.
5024 	 */
5025 	if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5026 		if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
5027 
5028 	/* XXX handle more than one queue */
5029 	for (i = 0; i < scctx->isc_nrxqsets; i++)
5030 		IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
5031 
5032 	*ctxp = ctx;
5033 
5034 	if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
5035 	iflib_add_device_sysctl_post(ctx);
5036 	ctx->ifc_flags |= IFC_INIT_DONE;
5037 	CTX_UNLOCK(ctx);
5038 
5039 	return (0);
5040 fail_detach:
5041 	ether_ifdetach(ctx->ifc_ifp);
5042 fail_queues:
5043 	iflib_tx_structures_free(ctx);
5044 	iflib_rx_structures_free(ctx);
5045 fail_iflib_detach:
5046 	IFDI_DETACH(ctx);
5047 fail_unlock:
5048 	CTX_UNLOCK(ctx);
5049 	iflib_deregister(ctx);
5050 fail_ctx_free:
5051 	free(ctx->ifc_softc, M_IFLIB);
5052 	free(ctx, M_IFLIB);
5053 	return (err);
5054 }
5055 
5056 int
5057 iflib_pseudo_deregister(if_ctx_t ctx)
5058 {
5059 	if_t ifp = ctx->ifc_ifp;
5060 	iflib_txq_t txq;
5061 	iflib_rxq_t rxq;
5062 	int i, j;
5063 	struct taskqgroup *tqg;
5064 	iflib_fl_t fl;
5065 
5066 	/* Unregister VLAN event handlers early */
5067 	iflib_unregister_vlan_handlers(ctx);
5068 
5069 	ether_ifdetach(ifp);
5070 	/* XXX drain any dependent tasks */
5071 	tqg = qgroup_if_io_tqg;
5072 	for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5073 		callout_drain(&txq->ift_timer);
5074 		if (txq->ift_task.gt_uniq != NULL)
5075 			taskqgroup_detach(tqg, &txq->ift_task);
5076 	}
5077 	for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5078 		callout_drain(&rxq->ifr_watchdog);
5079 		if (rxq->ifr_task.gt_uniq != NULL)
5080 			taskqgroup_detach(tqg, &rxq->ifr_task);
5081 
5082 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5083 			free(fl->ifl_rx_bitmap, M_IFLIB);
5084 	}
5085 	tqg = qgroup_if_config_tqg;
5086 	if (ctx->ifc_admin_task.gt_uniq != NULL)
5087 		taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5088 	if (ctx->ifc_vflr_task.gt_uniq != NULL)
5089 		taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5090 
5091 	iflib_tx_structures_free(ctx);
5092 	iflib_rx_structures_free(ctx);
5093 
5094 	iflib_deregister(ctx);
5095 
5096 	if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5097 		free(ctx->ifc_softc, M_IFLIB);
5098 	free(ctx, M_IFLIB);
5099 	return (0);
5100 }
5101 
5102 int
5103 iflib_device_attach(device_t dev)
5104 {
5105 	if_ctx_t ctx;
5106 	if_shared_ctx_t sctx;
5107 
5108 	if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5109 		return (ENOTSUP);
5110 
5111 	pci_enable_busmaster(dev);
5112 
5113 	return (iflib_device_register(dev, NULL, sctx, &ctx));
5114 }
5115 
5116 int
5117 iflib_device_deregister(if_ctx_t ctx)
5118 {
5119 	if_t ifp = ctx->ifc_ifp;
5120 	iflib_txq_t txq;
5121 	iflib_rxq_t rxq;
5122 	device_t dev = ctx->ifc_dev;
5123 	int i, j;
5124 	struct taskqgroup *tqg;
5125 	iflib_fl_t fl;
5126 
5127 	/* Make sure VLANS are not using driver */
5128 	if (if_vlantrunkinuse(ifp)) {
5129 		device_printf(dev, "Vlan in use, detach first\n");
5130 		return (EBUSY);
5131 	}
5132 #ifdef PCI_IOV
5133 	if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5134 		device_printf(dev, "SR-IOV in use; detach first.\n");
5135 		return (EBUSY);
5136 	}
5137 #endif
5138 
5139 	STATE_LOCK(ctx);
5140 	ctx->ifc_flags |= IFC_IN_DETACH;
5141 	STATE_UNLOCK(ctx);
5142 
5143 	/* Unregister VLAN handlers before calling iflib_stop() */
5144 	iflib_unregister_vlan_handlers(ctx);
5145 
5146 	iflib_netmap_detach(ifp);
5147 	ether_ifdetach(ifp);
5148 
5149 	CTX_LOCK(ctx);
5150 	iflib_stop(ctx);
5151 	CTX_UNLOCK(ctx);
5152 
5153 	iflib_rem_pfil(ctx);
5154 	if (ctx->ifc_led_dev != NULL)
5155 		led_destroy(ctx->ifc_led_dev);
5156 	/* XXX drain any dependent tasks */
5157 	tqg = qgroup_if_io_tqg;
5158 	for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5159 		callout_drain(&txq->ift_timer);
5160 		if (txq->ift_task.gt_uniq != NULL)
5161 			taskqgroup_detach(tqg, &txq->ift_task);
5162 	}
5163 	for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5164 		if (rxq->ifr_task.gt_uniq != NULL)
5165 			taskqgroup_detach(tqg, &rxq->ifr_task);
5166 
5167 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5168 			free(fl->ifl_rx_bitmap, M_IFLIB);
5169 	}
5170 	tqg = qgroup_if_config_tqg;
5171 	if (ctx->ifc_admin_task.gt_uniq != NULL)
5172 		taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5173 	if (ctx->ifc_vflr_task.gt_uniq != NULL)
5174 		taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5175 	CTX_LOCK(ctx);
5176 	IFDI_DETACH(ctx);
5177 	CTX_UNLOCK(ctx);
5178 
5179 	/* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5180 	iflib_free_intr_mem(ctx);
5181 
5182 	bus_generic_detach(dev);
5183 
5184 	iflib_tx_structures_free(ctx);
5185 	iflib_rx_structures_free(ctx);
5186 
5187 	iflib_deregister(ctx);
5188 
5189 	device_set_softc(ctx->ifc_dev, NULL);
5190 	if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5191 		free(ctx->ifc_softc, M_IFLIB);
5192 	unref_ctx_core_offset(ctx);
5193 	free(ctx, M_IFLIB);
5194 	return (0);
5195 }
5196 
5197 static void
5198 iflib_free_intr_mem(if_ctx_t ctx)
5199 {
5200 
5201 	if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5202 		iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5203 	}
5204 	if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5205 		pci_release_msi(ctx->ifc_dev);
5206 	}
5207 	if (ctx->ifc_msix_mem != NULL) {
5208 		bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5209 		    rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5210 		ctx->ifc_msix_mem = NULL;
5211 	}
5212 }
5213 
5214 int
5215 iflib_device_detach(device_t dev)
5216 {
5217 	if_ctx_t ctx = device_get_softc(dev);
5218 
5219 	return (iflib_device_deregister(ctx));
5220 }
5221 
5222 int
5223 iflib_device_suspend(device_t dev)
5224 {
5225 	if_ctx_t ctx = device_get_softc(dev);
5226 
5227 	CTX_LOCK(ctx);
5228 	IFDI_SUSPEND(ctx);
5229 	CTX_UNLOCK(ctx);
5230 
5231 	return bus_generic_suspend(dev);
5232 }
5233 int
5234 iflib_device_shutdown(device_t dev)
5235 {
5236 	if_ctx_t ctx = device_get_softc(dev);
5237 
5238 	CTX_LOCK(ctx);
5239 	IFDI_SHUTDOWN(ctx);
5240 	CTX_UNLOCK(ctx);
5241 
5242 	return bus_generic_suspend(dev);
5243 }
5244 
5245 
5246 int
5247 iflib_device_resume(device_t dev)
5248 {
5249 	if_ctx_t ctx = device_get_softc(dev);
5250 	iflib_txq_t txq = ctx->ifc_txqs;
5251 
5252 	CTX_LOCK(ctx);
5253 	IFDI_RESUME(ctx);
5254 	iflib_if_init_locked(ctx);
5255 	CTX_UNLOCK(ctx);
5256 	for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5257 		iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5258 
5259 	return (bus_generic_resume(dev));
5260 }
5261 
5262 int
5263 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5264 {
5265 	int error;
5266 	if_ctx_t ctx = device_get_softc(dev);
5267 
5268 	CTX_LOCK(ctx);
5269 	error = IFDI_IOV_INIT(ctx, num_vfs, params);
5270 	CTX_UNLOCK(ctx);
5271 
5272 	return (error);
5273 }
5274 
5275 void
5276 iflib_device_iov_uninit(device_t dev)
5277 {
5278 	if_ctx_t ctx = device_get_softc(dev);
5279 
5280 	CTX_LOCK(ctx);
5281 	IFDI_IOV_UNINIT(ctx);
5282 	CTX_UNLOCK(ctx);
5283 }
5284 
5285 int
5286 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5287 {
5288 	int error;
5289 	if_ctx_t ctx = device_get_softc(dev);
5290 
5291 	CTX_LOCK(ctx);
5292 	error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5293 	CTX_UNLOCK(ctx);
5294 
5295 	return (error);
5296 }
5297 
5298 /*********************************************************************
5299  *
5300  *  MODULE FUNCTION DEFINITIONS
5301  *
5302  **********************************************************************/
5303 
5304 /*
5305  * - Start a fast taskqueue thread for each core
5306  * - Start a taskqueue for control operations
5307  */
5308 static int
5309 iflib_module_init(void)
5310 {
5311 	return (0);
5312 }
5313 
5314 static int
5315 iflib_module_event_handler(module_t mod, int what, void *arg)
5316 {
5317 	int err;
5318 
5319 	switch (what) {
5320 	case MOD_LOAD:
5321 		if ((err = iflib_module_init()) != 0)
5322 			return (err);
5323 		break;
5324 	case MOD_UNLOAD:
5325 		return (EBUSY);
5326 	default:
5327 		return (EOPNOTSUPP);
5328 	}
5329 
5330 	return (0);
5331 }
5332 
5333 /*********************************************************************
5334  *
5335  *  PUBLIC FUNCTION DEFINITIONS
5336  *     ordered as in iflib.h
5337  *
5338  **********************************************************************/
5339 
5340 
5341 static void
5342 _iflib_assert(if_shared_ctx_t sctx)
5343 {
5344 	int i;
5345 
5346 	MPASS(sctx->isc_tx_maxsize);
5347 	MPASS(sctx->isc_tx_maxsegsize);
5348 
5349 	MPASS(sctx->isc_rx_maxsize);
5350 	MPASS(sctx->isc_rx_nsegments);
5351 	MPASS(sctx->isc_rx_maxsegsize);
5352 
5353 	MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5354 	for (i = 0; i < sctx->isc_nrxqs; i++) {
5355 		MPASS(sctx->isc_nrxd_min[i]);
5356 		MPASS(powerof2(sctx->isc_nrxd_min[i]));
5357 		MPASS(sctx->isc_nrxd_max[i]);
5358 		MPASS(powerof2(sctx->isc_nrxd_max[i]));
5359 		MPASS(sctx->isc_nrxd_default[i]);
5360 		MPASS(powerof2(sctx->isc_nrxd_default[i]));
5361 	}
5362 
5363 	MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5364 	for (i = 0; i < sctx->isc_ntxqs; i++) {
5365 		MPASS(sctx->isc_ntxd_min[i]);
5366 		MPASS(powerof2(sctx->isc_ntxd_min[i]));
5367 		MPASS(sctx->isc_ntxd_max[i]);
5368 		MPASS(powerof2(sctx->isc_ntxd_max[i]));
5369 		MPASS(sctx->isc_ntxd_default[i]);
5370 		MPASS(powerof2(sctx->isc_ntxd_default[i]));
5371 	}
5372 }
5373 
5374 static void
5375 _iflib_pre_assert(if_softc_ctx_t scctx)
5376 {
5377 
5378 	MPASS(scctx->isc_txrx->ift_txd_encap);
5379 	MPASS(scctx->isc_txrx->ift_txd_flush);
5380 	MPASS(scctx->isc_txrx->ift_txd_credits_update);
5381 	MPASS(scctx->isc_txrx->ift_rxd_available);
5382 	MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5383 	MPASS(scctx->isc_txrx->ift_rxd_refill);
5384 	MPASS(scctx->isc_txrx->ift_rxd_flush);
5385 }
5386 
5387 static int
5388 iflib_register(if_ctx_t ctx)
5389 {
5390 	if_shared_ctx_t sctx = ctx->ifc_sctx;
5391 	driver_t *driver = sctx->isc_driver;
5392 	device_t dev = ctx->ifc_dev;
5393 	if_t ifp;
5394 
5395 	_iflib_assert(sctx);
5396 
5397 	CTX_LOCK_INIT(ctx);
5398 	STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5399 	ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER);
5400 	if (ifp == NULL) {
5401 		device_printf(dev, "can not allocate ifnet structure\n");
5402 		return (ENOMEM);
5403 	}
5404 
5405 	/*
5406 	 * Initialize our context's device specific methods
5407 	 */
5408 	kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5409 	kobj_class_compile((kobj_class_t) driver);
5410 
5411 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5412 	if_setsoftc(ifp, ctx);
5413 	if_setdev(ifp, dev);
5414 	if_setinitfn(ifp, iflib_if_init);
5415 	if_setioctlfn(ifp, iflib_if_ioctl);
5416 #ifdef ALTQ
5417 	if_setstartfn(ifp, iflib_altq_if_start);
5418 	if_settransmitfn(ifp, iflib_altq_if_transmit);
5419 	if_setsendqready(ifp);
5420 #else
5421 	if_settransmitfn(ifp, iflib_if_transmit);
5422 #endif
5423 	if_setqflushfn(ifp, iflib_if_qflush);
5424 	if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST |
5425 	    IFF_KNOWSEPOCH);
5426 
5427 	ctx->ifc_vlan_attach_event =
5428 		EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5429 							  EVENTHANDLER_PRI_FIRST);
5430 	ctx->ifc_vlan_detach_event =
5431 		EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5432 							  EVENTHANDLER_PRI_FIRST);
5433 
5434 	if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
5435 		ctx->ifc_mediap = &ctx->ifc_media;
5436 		ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
5437 		    iflib_media_change, iflib_media_status);
5438 	}
5439 	return (0);
5440 }
5441 
5442 static void
5443 iflib_unregister_vlan_handlers(if_ctx_t ctx)
5444 {
5445 	/* Unregister VLAN events */
5446 	if (ctx->ifc_vlan_attach_event != NULL) {
5447 		EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5448 		ctx->ifc_vlan_attach_event = NULL;
5449 	}
5450 	if (ctx->ifc_vlan_detach_event != NULL) {
5451 		EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5452 		ctx->ifc_vlan_detach_event = NULL;
5453 	}
5454 
5455 }
5456 
5457 static void
5458 iflib_deregister(if_ctx_t ctx)
5459 {
5460 	if_t ifp = ctx->ifc_ifp;
5461 
5462 	/* Remove all media */
5463 	ifmedia_removeall(&ctx->ifc_media);
5464 
5465 	/* Ensure that VLAN event handlers are unregistered */
5466 	iflib_unregister_vlan_handlers(ctx);
5467 
5468 	/* Release kobject reference */
5469 	kobj_delete((kobj_t) ctx, NULL);
5470 
5471 	/* Free the ifnet structure */
5472 	if_free(ifp);
5473 
5474 	STATE_LOCK_DESTROY(ctx);
5475 
5476 	/* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5477 	CTX_LOCK_DESTROY(ctx);
5478 }
5479 
5480 static int
5481 iflib_queues_alloc(if_ctx_t ctx)
5482 {
5483 	if_shared_ctx_t sctx = ctx->ifc_sctx;
5484 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5485 	device_t dev = ctx->ifc_dev;
5486 	int nrxqsets = scctx->isc_nrxqsets;
5487 	int ntxqsets = scctx->isc_ntxqsets;
5488 	iflib_txq_t txq;
5489 	iflib_rxq_t rxq;
5490 	iflib_fl_t fl = NULL;
5491 	int i, j, cpu, err, txconf, rxconf;
5492 	iflib_dma_info_t ifdip;
5493 	uint32_t *rxqsizes = scctx->isc_rxqsizes;
5494 	uint32_t *txqsizes = scctx->isc_txqsizes;
5495 	uint8_t nrxqs = sctx->isc_nrxqs;
5496 	uint8_t ntxqs = sctx->isc_ntxqs;
5497 	int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5498 	caddr_t *vaddrs;
5499 	uint64_t *paddrs;
5500 
5501 	KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5502 	KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5503 
5504 	/* Allocate the TX ring struct memory */
5505 	if (!(ctx->ifc_txqs =
5506 	    (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5507 	    ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5508 		device_printf(dev, "Unable to allocate TX ring memory\n");
5509 		err = ENOMEM;
5510 		goto fail;
5511 	}
5512 
5513 	/* Now allocate the RX */
5514 	if (!(ctx->ifc_rxqs =
5515 	    (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5516 	    nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5517 		device_printf(dev, "Unable to allocate RX ring memory\n");
5518 		err = ENOMEM;
5519 		goto rx_fail;
5520 	}
5521 
5522 	txq = ctx->ifc_txqs;
5523 	rxq = ctx->ifc_rxqs;
5524 
5525 	/*
5526 	 * XXX handle allocation failure
5527 	 */
5528 	for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5529 		/* Set up some basics */
5530 
5531 		if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5532 		    M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5533 			device_printf(dev,
5534 			    "Unable to allocate TX DMA info memory\n");
5535 			err = ENOMEM;
5536 			goto err_tx_desc;
5537 		}
5538 		txq->ift_ifdi = ifdip;
5539 		for (j = 0; j < ntxqs; j++, ifdip++) {
5540 			if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5541 				device_printf(dev,
5542 				    "Unable to allocate TX descriptors\n");
5543 				err = ENOMEM;
5544 				goto err_tx_desc;
5545 			}
5546 			txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5547 			bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5548 		}
5549 		txq->ift_ctx = ctx;
5550 		txq->ift_id = i;
5551 		if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5552 			txq->ift_br_offset = 1;
5553 		} else {
5554 			txq->ift_br_offset = 0;
5555 		}
5556 		/* XXX fix this */
5557 		txq->ift_timer.c_cpu = cpu;
5558 
5559 		if (iflib_txsd_alloc(txq)) {
5560 			device_printf(dev, "Critical Failure setting up TX buffers\n");
5561 			err = ENOMEM;
5562 			goto err_tx_desc;
5563 		}
5564 
5565 		/* Initialize the TX lock */
5566 		snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
5567 		    device_get_nameunit(dev), txq->ift_id);
5568 		mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5569 		callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5570 
5571 		err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5572 				      iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5573 		if (err) {
5574 			/* XXX free any allocated rings */
5575 			device_printf(dev, "Unable to allocate buf_ring\n");
5576 			goto err_tx_desc;
5577 		}
5578 	}
5579 
5580 	for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5581 		/* Set up some basics */
5582 		callout_init(&rxq->ifr_watchdog, 1);
5583 
5584 		if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5585 		   M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5586 			device_printf(dev,
5587 			    "Unable to allocate RX DMA info memory\n");
5588 			err = ENOMEM;
5589 			goto err_tx_desc;
5590 		}
5591 
5592 		rxq->ifr_ifdi = ifdip;
5593 		/* XXX this needs to be changed if #rx queues != #tx queues */
5594 		rxq->ifr_ntxqirq = 1;
5595 		rxq->ifr_txqid[0] = i;
5596 		for (j = 0; j < nrxqs; j++, ifdip++) {
5597 			if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5598 				device_printf(dev,
5599 				    "Unable to allocate RX descriptors\n");
5600 				err = ENOMEM;
5601 				goto err_tx_desc;
5602 			}
5603 			bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5604 		}
5605 		rxq->ifr_ctx = ctx;
5606 		rxq->ifr_id = i;
5607 		if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5608 			rxq->ifr_fl_offset = 1;
5609 		} else {
5610 			rxq->ifr_fl_offset = 0;
5611 		}
5612 		rxq->ifr_nfl = nfree_lists;
5613 		if (!(fl =
5614 			  (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5615 			device_printf(dev, "Unable to allocate free list memory\n");
5616 			err = ENOMEM;
5617 			goto err_tx_desc;
5618 		}
5619 		rxq->ifr_fl = fl;
5620 		for (j = 0; j < nfree_lists; j++) {
5621 			fl[j].ifl_rxq = rxq;
5622 			fl[j].ifl_id = j;
5623 			fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5624 			fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5625 		}
5626 		/* Allocate receive buffers for the ring */
5627 		if (iflib_rxsd_alloc(rxq)) {
5628 			device_printf(dev,
5629 			    "Critical Failure setting up receive buffers\n");
5630 			err = ENOMEM;
5631 			goto err_rx_desc;
5632 		}
5633 
5634 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5635 			fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5636 			    M_WAITOK);
5637 	}
5638 
5639 	/* TXQs */
5640 	vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5641 	paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5642 	for (i = 0; i < ntxqsets; i++) {
5643 		iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5644 
5645 		for (j = 0; j < ntxqs; j++, di++) {
5646 			vaddrs[i*ntxqs + j] = di->idi_vaddr;
5647 			paddrs[i*ntxqs + j] = di->idi_paddr;
5648 		}
5649 	}
5650 	if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5651 		device_printf(ctx->ifc_dev,
5652 		    "Unable to allocate device TX queue\n");
5653 		iflib_tx_structures_free(ctx);
5654 		free(vaddrs, M_IFLIB);
5655 		free(paddrs, M_IFLIB);
5656 		goto err_rx_desc;
5657 	}
5658 	free(vaddrs, M_IFLIB);
5659 	free(paddrs, M_IFLIB);
5660 
5661 	/* RXQs */
5662 	vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5663 	paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5664 	for (i = 0; i < nrxqsets; i++) {
5665 		iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5666 
5667 		for (j = 0; j < nrxqs; j++, di++) {
5668 			vaddrs[i*nrxqs + j] = di->idi_vaddr;
5669 			paddrs[i*nrxqs + j] = di->idi_paddr;
5670 		}
5671 	}
5672 	if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5673 		device_printf(ctx->ifc_dev,
5674 		    "Unable to allocate device RX queue\n");
5675 		iflib_tx_structures_free(ctx);
5676 		free(vaddrs, M_IFLIB);
5677 		free(paddrs, M_IFLIB);
5678 		goto err_rx_desc;
5679 	}
5680 	free(vaddrs, M_IFLIB);
5681 	free(paddrs, M_IFLIB);
5682 
5683 	return (0);
5684 
5685 /* XXX handle allocation failure changes */
5686 err_rx_desc:
5687 err_tx_desc:
5688 rx_fail:
5689 	if (ctx->ifc_rxqs != NULL)
5690 		free(ctx->ifc_rxqs, M_IFLIB);
5691 	ctx->ifc_rxqs = NULL;
5692 	if (ctx->ifc_txqs != NULL)
5693 		free(ctx->ifc_txqs, M_IFLIB);
5694 	ctx->ifc_txqs = NULL;
5695 fail:
5696 	return (err);
5697 }
5698 
5699 static int
5700 iflib_tx_structures_setup(if_ctx_t ctx)
5701 {
5702 	iflib_txq_t txq = ctx->ifc_txqs;
5703 	int i;
5704 
5705 	for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5706 		iflib_txq_setup(txq);
5707 
5708 	return (0);
5709 }
5710 
5711 static void
5712 iflib_tx_structures_free(if_ctx_t ctx)
5713 {
5714 	iflib_txq_t txq = ctx->ifc_txqs;
5715 	if_shared_ctx_t sctx = ctx->ifc_sctx;
5716 	int i, j;
5717 
5718 	for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5719 		for (j = 0; j < sctx->isc_ntxqs; j++)
5720 			iflib_dma_free(&txq->ift_ifdi[j]);
5721 		iflib_txq_destroy(txq);
5722 	}
5723 	free(ctx->ifc_txqs, M_IFLIB);
5724 	ctx->ifc_txqs = NULL;
5725 	IFDI_QUEUES_FREE(ctx);
5726 }
5727 
5728 /*********************************************************************
5729  *
5730  *  Initialize all receive rings.
5731  *
5732  **********************************************************************/
5733 static int
5734 iflib_rx_structures_setup(if_ctx_t ctx)
5735 {
5736 	iflib_rxq_t rxq = ctx->ifc_rxqs;
5737 	int q;
5738 #if defined(INET6) || defined(INET)
5739 	int err, i;
5740 #endif
5741 
5742 	for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5743 #if defined(INET6) || defined(INET)
5744 		if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) {
5745 			err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5746 			    TCP_LRO_ENTRIES, min(1024,
5747 			    ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
5748 			if (err != 0) {
5749 				device_printf(ctx->ifc_dev,
5750 				    "LRO Initialization failed!\n");
5751 				goto fail;
5752 			}
5753 		}
5754 #endif
5755 		IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5756 	}
5757 	return (0);
5758 #if defined(INET6) || defined(INET)
5759 fail:
5760 	/*
5761 	 * Free LRO resources allocated so far, we will only handle
5762 	 * the rings that completed, the failing case will have
5763 	 * cleaned up for itself.  'q' failed, so its the terminus.
5764 	 */
5765 	rxq = ctx->ifc_rxqs;
5766 	for (i = 0; i < q; ++i, rxq++) {
5767 		if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5768 			tcp_lro_free(&rxq->ifr_lc);
5769 	}
5770 	return (err);
5771 #endif
5772 }
5773 
5774 /*********************************************************************
5775  *
5776  *  Free all receive rings.
5777  *
5778  **********************************************************************/
5779 static void
5780 iflib_rx_structures_free(if_ctx_t ctx)
5781 {
5782 	iflib_rxq_t rxq = ctx->ifc_rxqs;
5783 	if_shared_ctx_t sctx = ctx->ifc_sctx;
5784 	int i, j;
5785 
5786 	for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5787 		for (j = 0; j < sctx->isc_nrxqs; j++)
5788 			iflib_dma_free(&rxq->ifr_ifdi[j]);
5789 		iflib_rx_sds_free(rxq);
5790 #if defined(INET6) || defined(INET)
5791 		if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5792 			tcp_lro_free(&rxq->ifr_lc);
5793 #endif
5794 	}
5795 	free(ctx->ifc_rxqs, M_IFLIB);
5796 	ctx->ifc_rxqs = NULL;
5797 }
5798 
5799 static int
5800 iflib_qset_structures_setup(if_ctx_t ctx)
5801 {
5802 	int err;
5803 
5804 	/*
5805 	 * It is expected that the caller takes care of freeing queues if this
5806 	 * fails.
5807 	 */
5808 	if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5809 		device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5810 		return (err);
5811 	}
5812 
5813 	if ((err = iflib_rx_structures_setup(ctx)) != 0)
5814 		device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5815 
5816 	return (err);
5817 }
5818 
5819 int
5820 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5821 		driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5822 {
5823 
5824 	return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5825 }
5826 
5827 #ifdef SMP
5828 static int
5829 find_nth(if_ctx_t ctx, int qid)
5830 {
5831 	cpuset_t cpus;
5832 	int i, cpuid, eqid, count;
5833 
5834 	CPU_COPY(&ctx->ifc_cpus, &cpus);
5835 	count = CPU_COUNT(&cpus);
5836 	eqid = qid % count;
5837 	/* clear up to the qid'th bit */
5838 	for (i = 0; i < eqid; i++) {
5839 		cpuid = CPU_FFS(&cpus);
5840 		MPASS(cpuid != 0);
5841 		CPU_CLR(cpuid-1, &cpus);
5842 	}
5843 	cpuid = CPU_FFS(&cpus);
5844 	MPASS(cpuid != 0);
5845 	return (cpuid-1);
5846 }
5847 
5848 #ifdef SCHED_ULE
5849 extern struct cpu_group *cpu_top;              /* CPU topology */
5850 
5851 static int
5852 find_child_with_core(int cpu, struct cpu_group *grp)
5853 {
5854 	int i;
5855 
5856 	if (grp->cg_children == 0)
5857 		return -1;
5858 
5859 	MPASS(grp->cg_child);
5860 	for (i = 0; i < grp->cg_children; i++) {
5861 		if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5862 			return i;
5863 	}
5864 
5865 	return -1;
5866 }
5867 
5868 /*
5869  * Find the nth "close" core to the specified core
5870  * "close" is defined as the deepest level that shares
5871  * at least an L2 cache.  With threads, this will be
5872  * threads on the same core.  If the shared cache is L3
5873  * or higher, simply returns the same core.
5874  */
5875 static int
5876 find_close_core(int cpu, int core_offset)
5877 {
5878 	struct cpu_group *grp;
5879 	int i;
5880 	int fcpu;
5881 	cpuset_t cs;
5882 
5883 	grp = cpu_top;
5884 	if (grp == NULL)
5885 		return cpu;
5886 	i = 0;
5887 	while ((i = find_child_with_core(cpu, grp)) != -1) {
5888 		/* If the child only has one cpu, don't descend */
5889 		if (grp->cg_child[i].cg_count <= 1)
5890 			break;
5891 		grp = &grp->cg_child[i];
5892 	}
5893 
5894 	/* If they don't share at least an L2 cache, use the same CPU */
5895 	if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5896 		return cpu;
5897 
5898 	/* Now pick one */
5899 	CPU_COPY(&grp->cg_mask, &cs);
5900 
5901 	/* Add the selected CPU offset to core offset. */
5902 	for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5903 		if (fcpu - 1 == cpu)
5904 			break;
5905 		CPU_CLR(fcpu - 1, &cs);
5906 	}
5907 	MPASS(fcpu);
5908 
5909 	core_offset += i;
5910 
5911 	CPU_COPY(&grp->cg_mask, &cs);
5912 	for (i = core_offset % grp->cg_count; i > 0; i--) {
5913 		MPASS(CPU_FFS(&cs));
5914 		CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5915 	}
5916 	MPASS(CPU_FFS(&cs));
5917 	return CPU_FFS(&cs) - 1;
5918 }
5919 #else
5920 static int
5921 find_close_core(int cpu, int core_offset __unused)
5922 {
5923 	return cpu;
5924 }
5925 #endif
5926 
5927 static int
5928 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5929 {
5930 	switch (type) {
5931 	case IFLIB_INTR_TX:
5932 		/* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5933 		/* XXX handle multiple RX threads per core and more than two core per L2 group */
5934 		return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5935 	case IFLIB_INTR_RX:
5936 	case IFLIB_INTR_RXTX:
5937 		/* RX queues get the specified core */
5938 		return qid / CPU_COUNT(&ctx->ifc_cpus);
5939 	default:
5940 		return -1;
5941 	}
5942 }
5943 #else
5944 #define get_core_offset(ctx, type, qid)	CPU_FIRST()
5945 #define find_close_core(cpuid, tid)	CPU_FIRST()
5946 #define find_nth(ctx, gid)		CPU_FIRST()
5947 #endif
5948 
5949 /* Just to avoid copy/paste */
5950 static inline int
5951 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
5952     int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
5953     const char *name)
5954 {
5955 	device_t dev;
5956 	int co, cpuid, err, tid;
5957 
5958 	dev = ctx->ifc_dev;
5959 	co = ctx->ifc_sysctl_core_offset;
5960 	if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX)
5961 		co += ctx->ifc_softc_ctx.isc_nrxqsets;
5962 	cpuid = find_nth(ctx, qid + co);
5963 	tid = get_core_offset(ctx, type, qid);
5964 	if (tid < 0) {
5965 		device_printf(dev, "get_core_offset failed\n");
5966 		return (EOPNOTSUPP);
5967 	}
5968 	cpuid = find_close_core(cpuid, tid);
5969 	err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res,
5970 	    name);
5971 	if (err) {
5972 		device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
5973 		return (err);
5974 	}
5975 #ifdef notyet
5976 	if (cpuid > ctx->ifc_cpuid_highest)
5977 		ctx->ifc_cpuid_highest = cpuid;
5978 #endif
5979 	return (0);
5980 }
5981 
5982 int
5983 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5984 			iflib_intr_type_t type, driver_filter_t *filter,
5985 			void *filter_arg, int qid, const char *name)
5986 {
5987 	device_t dev;
5988 	struct grouptask *gtask;
5989 	struct taskqgroup *tqg;
5990 	iflib_filter_info_t info;
5991 	gtask_fn_t *fn;
5992 	int tqrid, err;
5993 	driver_filter_t *intr_fast;
5994 	void *q;
5995 
5996 	info = &ctx->ifc_filter_info;
5997 	tqrid = rid;
5998 
5999 	switch (type) {
6000 	/* XXX merge tx/rx for netmap? */
6001 	case IFLIB_INTR_TX:
6002 		q = &ctx->ifc_txqs[qid];
6003 		info = &ctx->ifc_txqs[qid].ift_filter_info;
6004 		gtask = &ctx->ifc_txqs[qid].ift_task;
6005 		tqg = qgroup_if_io_tqg;
6006 		fn = _task_fn_tx;
6007 		intr_fast = iflib_fast_intr;
6008 		GROUPTASK_INIT(gtask, 0, fn, q);
6009 		ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
6010 		break;
6011 	case IFLIB_INTR_RX:
6012 		q = &ctx->ifc_rxqs[qid];
6013 		info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6014 		gtask = &ctx->ifc_rxqs[qid].ifr_task;
6015 		tqg = qgroup_if_io_tqg;
6016 		fn = _task_fn_rx;
6017 		intr_fast = iflib_fast_intr;
6018 		NET_GROUPTASK_INIT(gtask, 0, fn, q);
6019 		break;
6020 	case IFLIB_INTR_RXTX:
6021 		q = &ctx->ifc_rxqs[qid];
6022 		info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6023 		gtask = &ctx->ifc_rxqs[qid].ifr_task;
6024 		tqg = qgroup_if_io_tqg;
6025 		fn = _task_fn_rx;
6026 		intr_fast = iflib_fast_intr_rxtx;
6027 		NET_GROUPTASK_INIT(gtask, 0, fn, q);
6028 		break;
6029 	case IFLIB_INTR_ADMIN:
6030 		q = ctx;
6031 		tqrid = -1;
6032 		info = &ctx->ifc_filter_info;
6033 		gtask = &ctx->ifc_admin_task;
6034 		tqg = qgroup_if_config_tqg;
6035 		fn = _task_fn_admin;
6036 		intr_fast = iflib_fast_intr_ctx;
6037 		break;
6038 	default:
6039 		device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
6040 		    __func__);
6041 		return (EINVAL);
6042 	}
6043 
6044 	info->ifi_filter = filter;
6045 	info->ifi_filter_arg = filter_arg;
6046 	info->ifi_task = gtask;
6047 	info->ifi_ctx = q;
6048 
6049 	dev = ctx->ifc_dev;
6050 	err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info,  name);
6051 	if (err != 0) {
6052 		device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
6053 		return (err);
6054 	}
6055 	if (type == IFLIB_INTR_ADMIN)
6056 		return (0);
6057 
6058 	if (tqrid != -1) {
6059 		err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6060 		    q, name);
6061 		if (err)
6062 			return (err);
6063 	} else {
6064 		taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
6065 	}
6066 
6067 	return (0);
6068 }
6069 
6070 void
6071 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
6072 {
6073 	struct grouptask *gtask;
6074 	struct taskqgroup *tqg;
6075 	gtask_fn_t *fn;
6076 	void *q;
6077 	int err;
6078 
6079 	switch (type) {
6080 	case IFLIB_INTR_TX:
6081 		q = &ctx->ifc_txqs[qid];
6082 		gtask = &ctx->ifc_txqs[qid].ift_task;
6083 		tqg = qgroup_if_io_tqg;
6084 		fn = _task_fn_tx;
6085 		GROUPTASK_INIT(gtask, 0, fn, q);
6086 		break;
6087 	case IFLIB_INTR_RX:
6088 		q = &ctx->ifc_rxqs[qid];
6089 		gtask = &ctx->ifc_rxqs[qid].ifr_task;
6090 		tqg = qgroup_if_io_tqg;
6091 		fn = _task_fn_rx;
6092 		NET_GROUPTASK_INIT(gtask, 0, fn, q);
6093 		break;
6094 	case IFLIB_INTR_IOV:
6095 		q = ctx;
6096 		gtask = &ctx->ifc_vflr_task;
6097 		tqg = qgroup_if_config_tqg;
6098 		fn = _task_fn_iov;
6099 		GROUPTASK_INIT(gtask, 0, fn, q);
6100 		break;
6101 	default:
6102 		panic("unknown net intr type");
6103 	}
6104 	if (irq != NULL) {
6105 		err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6106 		    q, name);
6107 		if (err)
6108 			taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev,
6109 			    irq->ii_res, name);
6110 	} else {
6111 		taskqgroup_attach(tqg, gtask, q, NULL, NULL, name);
6112 	}
6113 }
6114 
6115 void
6116 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6117 {
6118 
6119 	if (irq->ii_tag)
6120 		bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6121 
6122 	if (irq->ii_res)
6123 		bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6124 		    rman_get_rid(irq->ii_res), irq->ii_res);
6125 }
6126 
6127 static int
6128 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6129 {
6130 	iflib_txq_t txq = ctx->ifc_txqs;
6131 	iflib_rxq_t rxq = ctx->ifc_rxqs;
6132 	if_irq_t irq = &ctx->ifc_legacy_irq;
6133 	iflib_filter_info_t info;
6134 	device_t dev;
6135 	struct grouptask *gtask;
6136 	struct resource *res;
6137 	struct taskqgroup *tqg;
6138 	void *q;
6139 	int err, tqrid;
6140 	bool rx_only;
6141 
6142 	q = &ctx->ifc_rxqs[0];
6143 	info = &rxq[0].ifr_filter_info;
6144 	gtask = &rxq[0].ifr_task;
6145 	tqg = qgroup_if_io_tqg;
6146 	tqrid = *rid;
6147 	rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0;
6148 
6149 	ctx->ifc_flags |= IFC_LEGACY;
6150 	info->ifi_filter = filter;
6151 	info->ifi_filter_arg = filter_arg;
6152 	info->ifi_task = gtask;
6153 	info->ifi_ctx = rx_only ? ctx : q;
6154 
6155 	dev = ctx->ifc_dev;
6156 	/* We allocate a single interrupt resource */
6157 	err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx :
6158 	    iflib_fast_intr_rxtx, NULL, info, name);
6159 	if (err != 0)
6160 		return (err);
6161 	NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q);
6162 	res = irq->ii_res;
6163 	taskqgroup_attach(tqg, gtask, q, dev, res, name);
6164 
6165 	GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6166 	taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6167 	    "tx");
6168 	return (0);
6169 }
6170 
6171 void
6172 iflib_led_create(if_ctx_t ctx)
6173 {
6174 
6175 	ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6176 	    device_get_nameunit(ctx->ifc_dev));
6177 }
6178 
6179 void
6180 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6181 {
6182 
6183 	GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6184 }
6185 
6186 void
6187 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6188 {
6189 
6190 	GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6191 }
6192 
6193 void
6194 iflib_admin_intr_deferred(if_ctx_t ctx)
6195 {
6196 #ifdef INVARIANTS
6197 	struct grouptask *gtask;
6198 
6199 	gtask = &ctx->ifc_admin_task;
6200 	MPASS(gtask != NULL && gtask->gt_taskqueue != NULL);
6201 #endif
6202 
6203 	GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
6204 }
6205 
6206 void
6207 iflib_iov_intr_deferred(if_ctx_t ctx)
6208 {
6209 
6210 	GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6211 }
6212 
6213 void
6214 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name)
6215 {
6216 
6217 	taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6218 	    name);
6219 }
6220 
6221 void
6222 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6223 	const char *name)
6224 {
6225 
6226 	GROUPTASK_INIT(gtask, 0, fn, ctx);
6227 	taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
6228 	    name);
6229 }
6230 
6231 void
6232 iflib_config_gtask_deinit(struct grouptask *gtask)
6233 {
6234 
6235 	taskqgroup_detach(qgroup_if_config_tqg, gtask);
6236 }
6237 
6238 void
6239 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6240 {
6241 	if_t ifp = ctx->ifc_ifp;
6242 	iflib_txq_t txq = ctx->ifc_txqs;
6243 
6244 	if_setbaudrate(ifp, baudrate);
6245 	if (baudrate >= IF_Gbps(10)) {
6246 		STATE_LOCK(ctx);
6247 		ctx->ifc_flags |= IFC_PREFETCH;
6248 		STATE_UNLOCK(ctx);
6249 	}
6250 	/* If link down, disable watchdog */
6251 	if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6252 		for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6253 			txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6254 	}
6255 	ctx->ifc_link_state = link_state;
6256 	if_link_state_change(ifp, link_state);
6257 }
6258 
6259 static int
6260 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6261 {
6262 	int credits;
6263 #ifdef INVARIANTS
6264 	int credits_pre = txq->ift_cidx_processed;
6265 #endif
6266 
6267 	bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6268 	    BUS_DMASYNC_POSTREAD);
6269 	if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6270 		return (0);
6271 
6272 	txq->ift_processed += credits;
6273 	txq->ift_cidx_processed += credits;
6274 
6275 	MPASS(credits_pre + credits == txq->ift_cidx_processed);
6276 	if (txq->ift_cidx_processed >= txq->ift_size)
6277 		txq->ift_cidx_processed -= txq->ift_size;
6278 	return (credits);
6279 }
6280 
6281 static int
6282 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6283 {
6284 	iflib_fl_t fl;
6285 	u_int i;
6286 
6287 	for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6288 		bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6289 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6290 	return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6291 	    budget));
6292 }
6293 
6294 void
6295 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6296 	const char *description, if_int_delay_info_t info,
6297 	int offset, int value)
6298 {
6299 	info->iidi_ctx = ctx;
6300 	info->iidi_offset = offset;
6301 	info->iidi_value = value;
6302 	SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6303 	    SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6304 	    OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
6305 	    info, 0, iflib_sysctl_int_delay, "I", description);
6306 }
6307 
6308 struct sx *
6309 iflib_ctx_lock_get(if_ctx_t ctx)
6310 {
6311 
6312 	return (&ctx->ifc_ctx_sx);
6313 }
6314 
6315 static int
6316 iflib_msix_init(if_ctx_t ctx)
6317 {
6318 	device_t dev = ctx->ifc_dev;
6319 	if_shared_ctx_t sctx = ctx->ifc_sctx;
6320 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6321 	int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6322 	int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6323 
6324 	iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6325 	iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6326 
6327 	if (bootverbose)
6328 		device_printf(dev, "msix_init qsets capped at %d\n",
6329 		    imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6330 
6331 	/* Override by tuneable */
6332 	if (scctx->isc_disable_msix)
6333 		goto msi;
6334 
6335 	/* First try MSI-X */
6336 	if ((msgs = pci_msix_count(dev)) == 0) {
6337 		if (bootverbose)
6338 			device_printf(dev, "MSI-X not supported or disabled\n");
6339 		goto msi;
6340 	}
6341 
6342 	bar = ctx->ifc_softc_ctx.isc_msix_bar;
6343 	/*
6344 	 * bar == -1 => "trust me I know what I'm doing"
6345 	 * Some drivers are for hardware that is so shoddily
6346 	 * documented that no one knows which bars are which
6347 	 * so the developer has to map all bars. This hack
6348 	 * allows shoddy garbage to use MSI-X in this framework.
6349 	 */
6350 	if (bar != -1) {
6351 		ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6352 	            SYS_RES_MEMORY, &bar, RF_ACTIVE);
6353 		if (ctx->ifc_msix_mem == NULL) {
6354 			device_printf(dev, "Unable to map MSI-X table\n");
6355 			goto msi;
6356 		}
6357 	}
6358 
6359 	admincnt = sctx->isc_admin_intrcnt;
6360 #if IFLIB_DEBUG
6361 	/* use only 1 qset in debug mode */
6362 	queuemsgs = min(msgs - admincnt, 1);
6363 #else
6364 	queuemsgs = msgs - admincnt;
6365 #endif
6366 #ifdef RSS
6367 	queues = imin(queuemsgs, rss_getnumbuckets());
6368 #else
6369 	queues = queuemsgs;
6370 #endif
6371 	queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6372 	if (bootverbose)
6373 		device_printf(dev,
6374 		    "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6375 		    CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6376 #ifdef  RSS
6377 	/* If we're doing RSS, clamp at the number of RSS buckets */
6378 	if (queues > rss_getnumbuckets())
6379 		queues = rss_getnumbuckets();
6380 #endif
6381 	if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6382 		rx_queues = iflib_num_rx_queues;
6383 	else
6384 		rx_queues = queues;
6385 
6386 	if (rx_queues > scctx->isc_nrxqsets)
6387 		rx_queues = scctx->isc_nrxqsets;
6388 
6389 	/*
6390 	 * We want this to be all logical CPUs by default
6391 	 */
6392 	if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6393 		tx_queues = iflib_num_tx_queues;
6394 	else
6395 		tx_queues = mp_ncpus;
6396 
6397 	if (tx_queues > scctx->isc_ntxqsets)
6398 		tx_queues = scctx->isc_ntxqsets;
6399 
6400 	if (ctx->ifc_sysctl_qs_eq_override == 0) {
6401 #ifdef INVARIANTS
6402 		if (tx_queues != rx_queues)
6403 			device_printf(dev,
6404 			    "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6405 			    min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6406 #endif
6407 		tx_queues = min(rx_queues, tx_queues);
6408 		rx_queues = min(rx_queues, tx_queues);
6409 	}
6410 
6411 	vectors = rx_queues + admincnt;
6412 	if (msgs < vectors) {
6413 		device_printf(dev,
6414 		    "insufficient number of MSI-X vectors "
6415 		    "(supported %d, need %d)\n", msgs, vectors);
6416 		goto msi;
6417 	}
6418 
6419 	device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6420 	    tx_queues);
6421 	msgs = vectors;
6422 	if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6423 		if (vectors != msgs) {
6424 			device_printf(dev,
6425 			    "Unable to allocate sufficient MSI-X vectors "
6426 			    "(got %d, need %d)\n", vectors, msgs);
6427 			pci_release_msi(dev);
6428 			if (bar != -1) {
6429 				bus_release_resource(dev, SYS_RES_MEMORY, bar,
6430 				    ctx->ifc_msix_mem);
6431 				ctx->ifc_msix_mem = NULL;
6432 			}
6433 			goto msi;
6434 		}
6435 		device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6436 		    vectors);
6437 		scctx->isc_vectors = vectors;
6438 		scctx->isc_nrxqsets = rx_queues;
6439 		scctx->isc_ntxqsets = tx_queues;
6440 		scctx->isc_intr = IFLIB_INTR_MSIX;
6441 
6442 		return (vectors);
6443 	} else {
6444 		device_printf(dev,
6445 		    "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6446 		    err);
6447 		if (bar != -1) {
6448 			bus_release_resource(dev, SYS_RES_MEMORY, bar,
6449 			    ctx->ifc_msix_mem);
6450 			ctx->ifc_msix_mem = NULL;
6451 		}
6452 	}
6453 
6454 msi:
6455 	vectors = pci_msi_count(dev);
6456 	scctx->isc_nrxqsets = 1;
6457 	scctx->isc_ntxqsets = 1;
6458 	scctx->isc_vectors = vectors;
6459 	if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6460 		device_printf(dev,"Using an MSI interrupt\n");
6461 		scctx->isc_intr = IFLIB_INTR_MSI;
6462 	} else {
6463 		scctx->isc_vectors = 1;
6464 		device_printf(dev,"Using a Legacy interrupt\n");
6465 		scctx->isc_intr = IFLIB_INTR_LEGACY;
6466 	}
6467 
6468 	return (vectors);
6469 }
6470 
6471 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6472 
6473 static int
6474 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6475 {
6476 	int rc;
6477 	uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6478 	struct sbuf *sb;
6479 	const char *ring_state = "UNKNOWN";
6480 
6481 	/* XXX needed ? */
6482 	rc = sysctl_wire_old_buffer(req, 0);
6483 	MPASS(rc == 0);
6484 	if (rc != 0)
6485 		return (rc);
6486 	sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6487 	MPASS(sb != NULL);
6488 	if (sb == NULL)
6489 		return (ENOMEM);
6490 	if (state[3] <= 3)
6491 		ring_state = ring_states[state[3]];
6492 
6493 	sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6494 		    state[0], state[1], state[2], ring_state);
6495 	rc = sbuf_finish(sb);
6496 	sbuf_delete(sb);
6497         return(rc);
6498 }
6499 
6500 enum iflib_ndesc_handler {
6501 	IFLIB_NTXD_HANDLER,
6502 	IFLIB_NRXD_HANDLER,
6503 };
6504 
6505 static int
6506 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6507 {
6508 	if_ctx_t ctx = (void *)arg1;
6509 	enum iflib_ndesc_handler type = arg2;
6510 	char buf[256] = {0};
6511 	qidx_t *ndesc;
6512 	char *p, *next;
6513 	int nqs, rc, i;
6514 
6515 	nqs = 8;
6516 	switch(type) {
6517 	case IFLIB_NTXD_HANDLER:
6518 		ndesc = ctx->ifc_sysctl_ntxds;
6519 		if (ctx->ifc_sctx)
6520 			nqs = ctx->ifc_sctx->isc_ntxqs;
6521 		break;
6522 	case IFLIB_NRXD_HANDLER:
6523 		ndesc = ctx->ifc_sysctl_nrxds;
6524 		if (ctx->ifc_sctx)
6525 			nqs = ctx->ifc_sctx->isc_nrxqs;
6526 		break;
6527 	default:
6528 		printf("%s: unhandled type\n", __func__);
6529 		return (EINVAL);
6530 	}
6531 	if (nqs == 0)
6532 		nqs = 8;
6533 
6534 	for (i=0; i<8; i++) {
6535 		if (i >= nqs)
6536 			break;
6537 		if (i)
6538 			strcat(buf, ",");
6539 		sprintf(strchr(buf, 0), "%d", ndesc[i]);
6540 	}
6541 
6542 	rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6543 	if (rc || req->newptr == NULL)
6544 		return rc;
6545 
6546 	for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6547 	    i++, p = strsep(&next, " ,")) {
6548 		ndesc[i] = strtoul(p, NULL, 10);
6549 	}
6550 
6551 	return(rc);
6552 }
6553 
6554 #define NAME_BUFLEN 32
6555 static void
6556 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6557 {
6558         device_t dev = iflib_get_dev(ctx);
6559 	struct sysctl_oid_list *child, *oid_list;
6560 	struct sysctl_ctx_list *ctx_list;
6561 	struct sysctl_oid *node;
6562 
6563 	ctx_list = device_get_sysctl_ctx(dev);
6564 	child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6565 	ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6566 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields");
6567 	oid_list = SYSCTL_CHILDREN(node);
6568 
6569 	SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6570 		       CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
6571 		       "driver version");
6572 
6573 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6574 		       CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6575 			"# of txqs to use, 0 => use default #");
6576 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6577 		       CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6578 			"# of rxqs to use, 0 => use default #");
6579 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6580 		       CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6581                        "permit #txq != #rxq");
6582 	SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6583                       CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6584                       "disable MSI-X (default 0)");
6585 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6586 		       CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6587 		       "set the RX budget");
6588 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6589 		       CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6590 		       "cause TX to abdicate instead of running to completion");
6591 	ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6592 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6593 		       CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6594 		       "offset to start using cores at");
6595 	SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6596 		       CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6597 		       "use separate cores for TX and RX");
6598 
6599 	/* XXX change for per-queue sizes */
6600 	SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6601 	    CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6602 	    IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A",
6603 	    "list of # of TX descriptors to use, 0 = use default #");
6604 	SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6605 	    CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6606 	    IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A",
6607 	    "list of # of RX descriptors to use, 0 = use default #");
6608 }
6609 
6610 static void
6611 iflib_add_device_sysctl_post(if_ctx_t ctx)
6612 {
6613 	if_shared_ctx_t sctx = ctx->ifc_sctx;
6614 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6615         device_t dev = iflib_get_dev(ctx);
6616 	struct sysctl_oid_list *child;
6617 	struct sysctl_ctx_list *ctx_list;
6618 	iflib_fl_t fl;
6619 	iflib_txq_t txq;
6620 	iflib_rxq_t rxq;
6621 	int i, j;
6622 	char namebuf[NAME_BUFLEN];
6623 	char *qfmt;
6624 	struct sysctl_oid *queue_node, *fl_node, *node;
6625 	struct sysctl_oid_list *queue_list, *fl_list;
6626 	ctx_list = device_get_sysctl_ctx(dev);
6627 
6628 	node = ctx->ifc_sysctl_node;
6629 	child = SYSCTL_CHILDREN(node);
6630 
6631 	if (scctx->isc_ntxqsets > 100)
6632 		qfmt = "txq%03d";
6633 	else if (scctx->isc_ntxqsets > 10)
6634 		qfmt = "txq%02d";
6635 	else
6636 		qfmt = "txq%d";
6637 	for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6638 		snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6639 		queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6640 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6641 		queue_list = SYSCTL_CHILDREN(queue_node);
6642 #if MEMORY_LOGGING
6643 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6644 				CTLFLAG_RD,
6645 				&txq->ift_dequeued, "total mbufs freed");
6646 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6647 				CTLFLAG_RD,
6648 				&txq->ift_enqueued, "total mbufs enqueued");
6649 #endif
6650 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6651 				   CTLFLAG_RD,
6652 				   &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6653 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6654 				   CTLFLAG_RD,
6655 				   &txq->ift_pullups, "# of times m_pullup was called");
6656 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6657 				   CTLFLAG_RD,
6658 				   &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6659 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6660 				   CTLFLAG_RD,
6661 				   &txq->ift_no_desc_avail, "# of times no descriptors were available");
6662 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6663 				   CTLFLAG_RD,
6664 				   &txq->ift_map_failed, "# of times DMA map failed");
6665 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6666 				   CTLFLAG_RD,
6667 				   &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6668 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6669 				   CTLFLAG_RD,
6670 				   &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6671 		SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6672 				   CTLFLAG_RD,
6673 				   &txq->ift_pidx, 1, "Producer Index");
6674 		SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6675 				   CTLFLAG_RD,
6676 				   &txq->ift_cidx, 1, "Consumer Index");
6677 		SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6678 				   CTLFLAG_RD,
6679 				   &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6680 		SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6681 				   CTLFLAG_RD,
6682 				   &txq->ift_in_use, 1, "descriptors in use");
6683 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6684 				   CTLFLAG_RD,
6685 				   &txq->ift_processed, "descriptors procesed for clean");
6686 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6687 				   CTLFLAG_RD,
6688 				   &txq->ift_cleaned, "total cleaned");
6689 		SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6690 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
6691 		    __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0,
6692 		    mp_ring_state_handler, "A", "soft ring state");
6693 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6694 				       CTLFLAG_RD, &txq->ift_br->enqueues,
6695 				       "# of enqueues to the mp_ring for this queue");
6696 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6697 				       CTLFLAG_RD, &txq->ift_br->drops,
6698 				       "# of drops in the mp_ring for this queue");
6699 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6700 				       CTLFLAG_RD, &txq->ift_br->starts,
6701 				       "# of normal consumer starts in the mp_ring for this queue");
6702 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6703 				       CTLFLAG_RD, &txq->ift_br->stalls,
6704 					       "# of consumer stalls in the mp_ring for this queue");
6705 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6706 			       CTLFLAG_RD, &txq->ift_br->restarts,
6707 				       "# of consumer restarts in the mp_ring for this queue");
6708 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6709 				       CTLFLAG_RD, &txq->ift_br->abdications,
6710 				       "# of consumer abdications in the mp_ring for this queue");
6711 	}
6712 
6713 	if (scctx->isc_nrxqsets > 100)
6714 		qfmt = "rxq%03d";
6715 	else if (scctx->isc_nrxqsets > 10)
6716 		qfmt = "rxq%02d";
6717 	else
6718 		qfmt = "rxq%d";
6719 	for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6720 		snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6721 		queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6722 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6723 		queue_list = SYSCTL_CHILDREN(queue_node);
6724 		if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6725 			SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6726 				       CTLFLAG_RD,
6727 				       &rxq->ifr_cq_cidx, 1, "Consumer Index");
6728 		}
6729 
6730 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6731 			snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6732 			fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6733 			    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name");
6734 			fl_list = SYSCTL_CHILDREN(fl_node);
6735 			SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6736 				       CTLFLAG_RD,
6737 				       &fl->ifl_pidx, 1, "Producer Index");
6738 			SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6739 				       CTLFLAG_RD,
6740 				       &fl->ifl_cidx, 1, "Consumer Index");
6741 			SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6742 				       CTLFLAG_RD,
6743 				       &fl->ifl_credits, 1, "credits available");
6744 			SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size",
6745 				       CTLFLAG_RD,
6746 				       &fl->ifl_buf_size, 1, "buffer size");
6747 #if MEMORY_LOGGING
6748 			SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6749 					CTLFLAG_RD,
6750 					&fl->ifl_m_enqueued, "mbufs allocated");
6751 			SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6752 					CTLFLAG_RD,
6753 					&fl->ifl_m_dequeued, "mbufs freed");
6754 			SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6755 					CTLFLAG_RD,
6756 					&fl->ifl_cl_enqueued, "clusters allocated");
6757 			SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6758 					CTLFLAG_RD,
6759 					&fl->ifl_cl_dequeued, "clusters freed");
6760 #endif
6761 
6762 		}
6763 	}
6764 
6765 }
6766 
6767 void
6768 iflib_request_reset(if_ctx_t ctx)
6769 {
6770 
6771 	STATE_LOCK(ctx);
6772 	ctx->ifc_flags |= IFC_DO_RESET;
6773 	STATE_UNLOCK(ctx);
6774 }
6775 
6776 #ifndef __NO_STRICT_ALIGNMENT
6777 static struct mbuf *
6778 iflib_fixup_rx(struct mbuf *m)
6779 {
6780 	struct mbuf *n;
6781 
6782 	if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6783 		bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6784 		m->m_data += ETHER_HDR_LEN;
6785 		n = m;
6786 	} else {
6787 		MGETHDR(n, M_NOWAIT, MT_DATA);
6788 		if (n == NULL) {
6789 			m_freem(m);
6790 			return (NULL);
6791 		}
6792 		bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6793 		m->m_data += ETHER_HDR_LEN;
6794 		m->m_len -= ETHER_HDR_LEN;
6795 		n->m_len = ETHER_HDR_LEN;
6796 		M_MOVE_PKTHDR(n, m);
6797 		n->m_next = m;
6798 	}
6799 	return (n);
6800 }
6801 #endif
6802 
6803 #ifdef DEBUGNET
6804 static void
6805 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6806 {
6807 	if_ctx_t ctx;
6808 
6809 	ctx = if_getsoftc(ifp);
6810 	CTX_LOCK(ctx);
6811 	*nrxr = NRXQSETS(ctx);
6812 	*ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6813 	*clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6814 	CTX_UNLOCK(ctx);
6815 }
6816 
6817 static void
6818 iflib_debugnet_event(if_t ifp, enum debugnet_ev event)
6819 {
6820 	if_ctx_t ctx;
6821 	if_softc_ctx_t scctx;
6822 	iflib_fl_t fl;
6823 	iflib_rxq_t rxq;
6824 	int i, j;
6825 
6826 	ctx = if_getsoftc(ifp);
6827 	scctx = &ctx->ifc_softc_ctx;
6828 
6829 	switch (event) {
6830 	case DEBUGNET_START:
6831 		for (i = 0; i < scctx->isc_nrxqsets; i++) {
6832 			rxq = &ctx->ifc_rxqs[i];
6833 			for (j = 0; j < rxq->ifr_nfl; j++) {
6834 				fl = rxq->ifr_fl;
6835 				fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6836 			}
6837 		}
6838 		iflib_no_tx_batch = 1;
6839 		break;
6840 	default:
6841 		break;
6842 	}
6843 }
6844 
6845 static int
6846 iflib_debugnet_transmit(if_t ifp, struct mbuf *m)
6847 {
6848 	if_ctx_t ctx;
6849 	iflib_txq_t txq;
6850 	int error;
6851 
6852 	ctx = if_getsoftc(ifp);
6853 	if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6854 	    IFF_DRV_RUNNING)
6855 		return (EBUSY);
6856 
6857 	txq = &ctx->ifc_txqs[0];
6858 	error = iflib_encap(txq, &m);
6859 	if (error == 0)
6860 		(void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6861 	return (error);
6862 }
6863 
6864 static int
6865 iflib_debugnet_poll(if_t ifp, int count)
6866 {
6867 	struct epoch_tracker et;
6868 	if_ctx_t ctx;
6869 	if_softc_ctx_t scctx;
6870 	iflib_txq_t txq;
6871 	int i;
6872 
6873 	ctx = if_getsoftc(ifp);
6874 	scctx = &ctx->ifc_softc_ctx;
6875 
6876 	if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6877 	    IFF_DRV_RUNNING)
6878 		return (EBUSY);
6879 
6880 	txq = &ctx->ifc_txqs[0];
6881 	(void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6882 
6883 	NET_EPOCH_ENTER(et);
6884 	for (i = 0; i < scctx->isc_nrxqsets; i++)
6885 		(void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6886 	NET_EPOCH_EXIT(et);
6887 	return (0);
6888 }
6889 #endif /* DEBUGNET */
6890