1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 120 /* 121 * File organization: 122 * - private structures 123 * - iflib private utility functions 124 * - ifnet functions 125 * - vlan registry and other exported functions 126 * - iflib public core functions 127 * 128 * 129 */ 130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 131 132 struct iflib_txq; 133 typedef struct iflib_txq *iflib_txq_t; 134 struct iflib_rxq; 135 typedef struct iflib_rxq *iflib_rxq_t; 136 struct iflib_fl; 137 typedef struct iflib_fl *iflib_fl_t; 138 139 struct iflib_ctx; 140 141 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 142 static void iflib_timer(void *arg); 143 144 typedef struct iflib_filter_info { 145 driver_filter_t *ifi_filter; 146 void *ifi_filter_arg; 147 struct grouptask *ifi_task; 148 void *ifi_ctx; 149 } *iflib_filter_info_t; 150 151 struct iflib_ctx { 152 KOBJ_FIELDS; 153 /* 154 * Pointer to hardware driver's softc 155 */ 156 void *ifc_softc; 157 device_t ifc_dev; 158 if_t ifc_ifp; 159 160 cpuset_t ifc_cpus; 161 if_shared_ctx_t ifc_sctx; 162 struct if_softc_ctx ifc_softc_ctx; 163 164 struct sx ifc_ctx_sx; 165 struct mtx ifc_state_mtx; 166 167 iflib_txq_t ifc_txqs; 168 iflib_rxq_t ifc_rxqs; 169 uint32_t ifc_if_flags; 170 uint32_t ifc_flags; 171 uint32_t ifc_max_fl_buf_size; 172 uint32_t ifc_rx_mbuf_sz; 173 174 int ifc_link_state; 175 int ifc_watchdog_events; 176 struct cdev *ifc_led_dev; 177 struct resource *ifc_msix_mem; 178 179 struct if_irq ifc_legacy_irq; 180 struct grouptask ifc_admin_task; 181 struct grouptask ifc_vflr_task; 182 struct iflib_filter_info ifc_filter_info; 183 struct ifmedia ifc_media; 184 struct ifmedia *ifc_mediap; 185 186 struct sysctl_oid *ifc_sysctl_node; 187 uint16_t ifc_sysctl_ntxqs; 188 uint16_t ifc_sysctl_nrxqs; 189 uint16_t ifc_sysctl_qs_eq_override; 190 uint16_t ifc_sysctl_rx_budget; 191 uint16_t ifc_sysctl_tx_abdicate; 192 uint16_t ifc_sysctl_core_offset; 193 #define CORE_OFFSET_UNSPECIFIED 0xffff 194 uint8_t ifc_sysctl_separate_txrx; 195 196 qidx_t ifc_sysctl_ntxds[8]; 197 qidx_t ifc_sysctl_nrxds[8]; 198 struct if_txrx ifc_txrx; 199 #define isc_txd_encap ifc_txrx.ift_txd_encap 200 #define isc_txd_flush ifc_txrx.ift_txd_flush 201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 202 #define isc_rxd_available ifc_txrx.ift_rxd_available 203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 209 eventhandler_tag ifc_vlan_attach_event; 210 eventhandler_tag ifc_vlan_detach_event; 211 struct ether_addr ifc_mac; 212 }; 213 214 void * 215 iflib_get_softc(if_ctx_t ctx) 216 { 217 218 return (ctx->ifc_softc); 219 } 220 221 device_t 222 iflib_get_dev(if_ctx_t ctx) 223 { 224 225 return (ctx->ifc_dev); 226 } 227 228 if_t 229 iflib_get_ifp(if_ctx_t ctx) 230 { 231 232 return (ctx->ifc_ifp); 233 } 234 235 struct ifmedia * 236 iflib_get_media(if_ctx_t ctx) 237 { 238 239 return (ctx->ifc_mediap); 240 } 241 242 uint32_t 243 iflib_get_flags(if_ctx_t ctx) 244 { 245 return (ctx->ifc_flags); 246 } 247 248 void 249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 250 { 251 252 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 253 } 254 255 if_softc_ctx_t 256 iflib_get_softc_ctx(if_ctx_t ctx) 257 { 258 259 return (&ctx->ifc_softc_ctx); 260 } 261 262 if_shared_ctx_t 263 iflib_get_sctx(if_ctx_t ctx) 264 { 265 266 return (ctx->ifc_sctx); 267 } 268 269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 272 273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 275 276 typedef struct iflib_sw_rx_desc_array { 277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 278 struct mbuf **ifsd_m; /* pkthdr mbufs */ 279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 281 } iflib_rxsd_array_t; 282 283 typedef struct iflib_sw_tx_desc_array { 284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 286 struct mbuf **ifsd_m; /* pkthdr mbufs */ 287 } if_txsd_vec_t; 288 289 /* magic number that should be high enough for any hardware */ 290 #define IFLIB_MAX_TX_SEGS 128 291 #define IFLIB_RX_COPY_THRESH 128 292 #define IFLIB_MAX_RX_REFRESH 32 293 /* The minimum descriptors per second before we start coalescing */ 294 #define IFLIB_MIN_DESC_SEC 16384 295 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 296 #define IFLIB_QUEUE_IDLE 0 297 #define IFLIB_QUEUE_HUNG 1 298 #define IFLIB_QUEUE_WORKING 2 299 /* maximum number of txqs that can share an rx interrupt */ 300 #define IFLIB_MAX_TX_SHARED_INTR 4 301 302 /* this should really scale with ring size - this is a fairly arbitrary value */ 303 #define TX_BATCH_SIZE 32 304 305 #define IFLIB_RESTART_BUDGET 8 306 307 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 308 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 309 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 310 311 struct iflib_txq { 312 qidx_t ift_in_use; 313 qidx_t ift_cidx; 314 qidx_t ift_cidx_processed; 315 qidx_t ift_pidx; 316 uint8_t ift_gen; 317 uint8_t ift_br_offset; 318 uint16_t ift_npending; 319 uint16_t ift_db_pending; 320 uint16_t ift_rs_pending; 321 /* implicit pad */ 322 uint8_t ift_txd_size[8]; 323 uint64_t ift_processed; 324 uint64_t ift_cleaned; 325 uint64_t ift_cleaned_prev; 326 #if MEMORY_LOGGING 327 uint64_t ift_enqueued; 328 uint64_t ift_dequeued; 329 #endif 330 uint64_t ift_no_tx_dma_setup; 331 uint64_t ift_no_desc_avail; 332 uint64_t ift_mbuf_defrag_failed; 333 uint64_t ift_mbuf_defrag; 334 uint64_t ift_map_failed; 335 uint64_t ift_txd_encap_efbig; 336 uint64_t ift_pullups; 337 uint64_t ift_last_timer_tick; 338 339 struct mtx ift_mtx; 340 struct mtx ift_db_mtx; 341 342 /* constant values */ 343 if_ctx_t ift_ctx; 344 struct ifmp_ring *ift_br; 345 struct grouptask ift_task; 346 qidx_t ift_size; 347 uint16_t ift_id; 348 struct callout ift_timer; 349 350 if_txsd_vec_t ift_sds; 351 uint8_t ift_qstatus; 352 uint8_t ift_closed; 353 uint8_t ift_update_freq; 354 struct iflib_filter_info ift_filter_info; 355 bus_dma_tag_t ift_buf_tag; 356 bus_dma_tag_t ift_tso_buf_tag; 357 iflib_dma_info_t ift_ifdi; 358 #define MTX_NAME_LEN 16 359 char ift_mtx_name[MTX_NAME_LEN]; 360 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 361 #ifdef IFLIB_DIAGNOSTICS 362 uint64_t ift_cpu_exec_count[256]; 363 #endif 364 } __aligned(CACHE_LINE_SIZE); 365 366 struct iflib_fl { 367 qidx_t ifl_cidx; 368 qidx_t ifl_pidx; 369 qidx_t ifl_credits; 370 uint8_t ifl_gen; 371 uint8_t ifl_rxd_size; 372 #if MEMORY_LOGGING 373 uint64_t ifl_m_enqueued; 374 uint64_t ifl_m_dequeued; 375 uint64_t ifl_cl_enqueued; 376 uint64_t ifl_cl_dequeued; 377 #endif 378 /* implicit pad */ 379 bitstr_t *ifl_rx_bitmap; 380 qidx_t ifl_fragidx; 381 /* constant */ 382 qidx_t ifl_size; 383 uint16_t ifl_buf_size; 384 uint16_t ifl_cltype; 385 uma_zone_t ifl_zone; 386 iflib_rxsd_array_t ifl_sds; 387 iflib_rxq_t ifl_rxq; 388 uint8_t ifl_id; 389 bus_dma_tag_t ifl_buf_tag; 390 iflib_dma_info_t ifl_ifdi; 391 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 392 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 393 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 394 } __aligned(CACHE_LINE_SIZE); 395 396 static inline qidx_t 397 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 398 { 399 qidx_t used; 400 401 if (pidx > cidx) 402 used = pidx - cidx; 403 else if (pidx < cidx) 404 used = size - cidx + pidx; 405 else if (gen == 0 && pidx == cidx) 406 used = 0; 407 else if (gen == 1 && pidx == cidx) 408 used = size; 409 else 410 panic("bad state"); 411 412 return (used); 413 } 414 415 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 416 417 #define IDXDIFF(head, tail, wrap) \ 418 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 419 420 struct iflib_rxq { 421 if_ctx_t ifr_ctx; 422 iflib_fl_t ifr_fl; 423 uint64_t ifr_rx_irq; 424 struct pfil_head *pfil; 425 /* 426 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 427 * the command queue consumer index. Otherwise it's unused. 428 */ 429 qidx_t ifr_cq_cidx; 430 uint16_t ifr_id; 431 uint8_t ifr_nfl; 432 uint8_t ifr_ntxqirq; 433 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 434 uint8_t ifr_fl_offset; 435 struct lro_ctrl ifr_lc; 436 struct grouptask ifr_task; 437 struct iflib_filter_info ifr_filter_info; 438 iflib_dma_info_t ifr_ifdi; 439 440 /* dynamically allocate if any drivers need a value substantially larger than this */ 441 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 442 #ifdef IFLIB_DIAGNOSTICS 443 uint64_t ifr_cpu_exec_count[256]; 444 #endif 445 } __aligned(CACHE_LINE_SIZE); 446 447 typedef struct if_rxsd { 448 caddr_t *ifsd_cl; 449 iflib_fl_t ifsd_fl; 450 qidx_t ifsd_cidx; 451 } *if_rxsd_t; 452 453 /* multiple of word size */ 454 #ifdef __LP64__ 455 #define PKT_INFO_SIZE 6 456 #define RXD_INFO_SIZE 5 457 #define PKT_TYPE uint64_t 458 #else 459 #define PKT_INFO_SIZE 11 460 #define RXD_INFO_SIZE 8 461 #define PKT_TYPE uint32_t 462 #endif 463 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 464 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 465 466 typedef struct if_pkt_info_pad { 467 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 468 } *if_pkt_info_pad_t; 469 typedef struct if_rxd_info_pad { 470 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 471 } *if_rxd_info_pad_t; 472 473 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 474 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 475 476 477 static inline void 478 pkt_info_zero(if_pkt_info_t pi) 479 { 480 if_pkt_info_pad_t pi_pad; 481 482 pi_pad = (if_pkt_info_pad_t)pi; 483 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 484 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 485 #ifndef __LP64__ 486 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 487 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 488 #endif 489 } 490 491 static device_method_t iflib_pseudo_methods[] = { 492 DEVMETHOD(device_attach, noop_attach), 493 DEVMETHOD(device_detach, iflib_pseudo_detach), 494 DEVMETHOD_END 495 }; 496 497 driver_t iflib_pseudodriver = { 498 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 499 }; 500 501 static inline void 502 rxd_info_zero(if_rxd_info_t ri) 503 { 504 if_rxd_info_pad_t ri_pad; 505 int i; 506 507 ri_pad = (if_rxd_info_pad_t)ri; 508 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 509 ri_pad->rxd_val[i] = 0; 510 ri_pad->rxd_val[i+1] = 0; 511 ri_pad->rxd_val[i+2] = 0; 512 ri_pad->rxd_val[i+3] = 0; 513 } 514 #ifdef __LP64__ 515 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 516 #endif 517 } 518 519 /* 520 * Only allow a single packet to take up most 1/nth of the tx ring 521 */ 522 #define MAX_SINGLE_PACKET_FRACTION 12 523 #define IF_BAD_DMA (bus_addr_t)-1 524 525 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 526 527 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 528 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 529 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 530 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 531 532 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 533 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 534 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 535 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 536 537 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 538 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 539 540 void 541 iflib_set_detach(if_ctx_t ctx) 542 { 543 STATE_LOCK(ctx); 544 ctx->ifc_flags |= IFC_IN_DETACH; 545 STATE_UNLOCK(ctx); 546 } 547 548 /* Our boot-time initialization hook */ 549 static int iflib_module_event_handler(module_t, int, void *); 550 551 static moduledata_t iflib_moduledata = { 552 "iflib", 553 iflib_module_event_handler, 554 NULL 555 }; 556 557 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 558 MODULE_VERSION(iflib, 1); 559 560 MODULE_DEPEND(iflib, pci, 1, 1, 1); 561 MODULE_DEPEND(iflib, ether, 1, 1, 1); 562 563 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 564 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 565 566 #ifndef IFLIB_DEBUG_COUNTERS 567 #ifdef INVARIANTS 568 #define IFLIB_DEBUG_COUNTERS 1 569 #else 570 #define IFLIB_DEBUG_COUNTERS 0 571 #endif /* !INVARIANTS */ 572 #endif 573 574 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 575 "iflib driver parameters"); 576 577 /* 578 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 579 */ 580 static int iflib_min_tx_latency = 0; 581 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 582 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 583 static int iflib_no_tx_batch = 0; 584 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 585 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 586 587 588 #if IFLIB_DEBUG_COUNTERS 589 590 static int iflib_tx_seen; 591 static int iflib_tx_sent; 592 static int iflib_tx_encap; 593 static int iflib_rx_allocs; 594 static int iflib_fl_refills; 595 static int iflib_fl_refills_large; 596 static int iflib_tx_frees; 597 598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 599 &iflib_tx_seen, 0, "# TX mbufs seen"); 600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 601 &iflib_tx_sent, 0, "# TX mbufs sent"); 602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 603 &iflib_tx_encap, 0, "# TX mbufs encapped"); 604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 605 &iflib_tx_frees, 0, "# TX frees"); 606 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 607 &iflib_rx_allocs, 0, "# RX allocations"); 608 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 609 &iflib_fl_refills, 0, "# refills"); 610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 611 &iflib_fl_refills_large, 0, "# large refills"); 612 613 614 static int iflib_txq_drain_flushing; 615 static int iflib_txq_drain_oactive; 616 static int iflib_txq_drain_notready; 617 618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 619 &iflib_txq_drain_flushing, 0, "# drain flushes"); 620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 621 &iflib_txq_drain_oactive, 0, "# drain oactives"); 622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 623 &iflib_txq_drain_notready, 0, "# drain notready"); 624 625 626 static int iflib_encap_load_mbuf_fail; 627 static int iflib_encap_pad_mbuf_fail; 628 static int iflib_encap_txq_avail_fail; 629 static int iflib_encap_txd_encap_fail; 630 631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 632 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 634 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 636 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 638 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 639 640 static int iflib_task_fn_rxs; 641 static int iflib_rx_intr_enables; 642 static int iflib_fast_intrs; 643 static int iflib_rx_unavail; 644 static int iflib_rx_ctx_inactive; 645 static int iflib_rx_if_input; 646 static int iflib_rxd_flush; 647 648 static int iflib_verbose_debug; 649 650 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 651 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 652 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 653 &iflib_rx_intr_enables, 0, "# RX intr enables"); 654 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 655 &iflib_fast_intrs, 0, "# fast_intr calls"); 656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 657 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 659 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 661 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 663 &iflib_rxd_flush, 0, "# times rxd_flush called"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 665 &iflib_verbose_debug, 0, "enable verbose debugging"); 666 667 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 668 static void 669 iflib_debug_reset(void) 670 { 671 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 672 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 673 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 674 iflib_txq_drain_notready = 675 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 676 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 677 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 678 iflib_rx_unavail = 679 iflib_rx_ctx_inactive = iflib_rx_if_input = 680 iflib_rxd_flush = 0; 681 } 682 683 #else 684 #define DBG_COUNTER_INC(name) 685 static void iflib_debug_reset(void) {} 686 #endif 687 688 #define IFLIB_DEBUG 0 689 690 static void iflib_tx_structures_free(if_ctx_t ctx); 691 static void iflib_rx_structures_free(if_ctx_t ctx); 692 static int iflib_queues_alloc(if_ctx_t ctx); 693 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 694 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 695 static int iflib_qset_structures_setup(if_ctx_t ctx); 696 static int iflib_msix_init(if_ctx_t ctx); 697 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 698 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 699 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 700 #ifdef ALTQ 701 static void iflib_altq_if_start(if_t ifp); 702 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 703 #endif 704 static int iflib_register(if_ctx_t); 705 static void iflib_deregister(if_ctx_t); 706 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 707 static void iflib_init_locked(if_ctx_t ctx); 708 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 709 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 710 static void iflib_ifmp_purge(iflib_txq_t txq); 711 static void _iflib_pre_assert(if_softc_ctx_t scctx); 712 static void iflib_if_init_locked(if_ctx_t ctx); 713 static void iflib_free_intr_mem(if_ctx_t ctx); 714 #ifndef __NO_STRICT_ALIGNMENT 715 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 716 #endif 717 718 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 719 SLIST_HEAD_INITIALIZER(cpu_offsets); 720 struct cpu_offset { 721 SLIST_ENTRY(cpu_offset) entries; 722 cpuset_t set; 723 unsigned int refcount; 724 uint16_t offset; 725 }; 726 static struct mtx cpu_offset_mtx; 727 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 728 MTX_DEF); 729 730 DEBUGNET_DEFINE(iflib); 731 732 #ifdef DEV_NETMAP 733 #include <sys/selinfo.h> 734 #include <net/netmap.h> 735 #include <dev/netmap/netmap_kern.h> 736 737 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 738 739 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 740 741 /* 742 * device-specific sysctl variables: 743 * 744 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 745 * During regular operations the CRC is stripped, but on some 746 * hardware reception of frames not multiple of 64 is slower, 747 * so using crcstrip=0 helps in benchmarks. 748 * 749 * iflib_rx_miss, iflib_rx_miss_bufs: 750 * count packets that might be missed due to lost interrupts. 751 */ 752 SYSCTL_DECL(_dev_netmap); 753 /* 754 * The xl driver by default strips CRCs and we do not override it. 755 */ 756 757 int iflib_crcstrip = 1; 758 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 759 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 760 761 int iflib_rx_miss, iflib_rx_miss_bufs; 762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 763 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 764 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 765 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 766 767 /* 768 * Register/unregister. We are already under netmap lock. 769 * Only called on the first register or the last unregister. 770 */ 771 static int 772 iflib_netmap_register(struct netmap_adapter *na, int onoff) 773 { 774 if_t ifp = na->ifp; 775 if_ctx_t ctx = ifp->if_softc; 776 int status; 777 778 CTX_LOCK(ctx); 779 IFDI_INTR_DISABLE(ctx); 780 781 /* Tell the stack that the interface is no longer active */ 782 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 783 784 if (!CTX_IS_VF(ctx)) 785 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 786 787 /* enable or disable flags and callbacks in na and ifp */ 788 if (onoff) { 789 nm_set_native_flags(na); 790 } else { 791 nm_clear_native_flags(na); 792 } 793 iflib_stop(ctx); 794 iflib_init_locked(ctx); 795 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 796 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 797 if (status) 798 nm_clear_native_flags(na); 799 CTX_UNLOCK(ctx); 800 return (status); 801 } 802 803 static int 804 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 805 { 806 struct netmap_adapter *na = kring->na; 807 u_int const lim = kring->nkr_num_slots - 1; 808 u_int head = kring->rhead; 809 struct netmap_ring *ring = kring->ring; 810 bus_dmamap_t *map; 811 struct if_rxd_update iru; 812 if_ctx_t ctx = rxq->ifr_ctx; 813 iflib_fl_t fl = &rxq->ifr_fl[0]; 814 uint32_t refill_pidx, nic_i; 815 #if IFLIB_DEBUG_COUNTERS 816 int rf_count = 0; 817 #endif 818 819 if (nm_i == head && __predict_true(!init)) 820 return 0; 821 iru_init(&iru, rxq, 0 /* flid */); 822 map = fl->ifl_sds.ifsd_map; 823 refill_pidx = netmap_idx_k2n(kring, nm_i); 824 /* 825 * IMPORTANT: we must leave one free slot in the ring, 826 * so move head back by one unit 827 */ 828 head = nm_prev(head, lim); 829 nic_i = UINT_MAX; 830 DBG_COUNTER_INC(fl_refills); 831 while (nm_i != head) { 832 #if IFLIB_DEBUG_COUNTERS 833 if (++rf_count == 9) 834 DBG_COUNTER_INC(fl_refills_large); 835 #endif 836 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 837 struct netmap_slot *slot = &ring->slot[nm_i]; 838 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 839 uint32_t nic_i_dma = refill_pidx; 840 nic_i = netmap_idx_k2n(kring, nm_i); 841 842 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 843 844 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 845 return netmap_ring_reinit(kring); 846 847 fl->ifl_vm_addrs[tmp_pidx] = addr; 848 if (__predict_false(init)) { 849 netmap_load_map(na, fl->ifl_buf_tag, 850 map[nic_i], addr); 851 } else if (slot->flags & NS_BUF_CHANGED) { 852 /* buffer has changed, reload map */ 853 netmap_reload_map(na, fl->ifl_buf_tag, 854 map[nic_i], addr); 855 } 856 slot->flags &= ~NS_BUF_CHANGED; 857 858 nm_i = nm_next(nm_i, lim); 859 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 860 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 861 continue; 862 863 iru.iru_pidx = refill_pidx; 864 iru.iru_count = tmp_pidx+1; 865 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 866 refill_pidx = nic_i; 867 for (int n = 0; n < iru.iru_count; n++) { 868 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma], 869 BUS_DMASYNC_PREREAD); 870 /* XXX - change this to not use the netmap func*/ 871 nic_i_dma = nm_next(nic_i_dma, lim); 872 } 873 } 874 } 875 kring->nr_hwcur = head; 876 877 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 878 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 879 if (__predict_true(nic_i != UINT_MAX)) { 880 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 881 DBG_COUNTER_INC(rxd_flush); 882 } 883 return (0); 884 } 885 886 /* 887 * Reconcile kernel and user view of the transmit ring. 888 * 889 * All information is in the kring. 890 * Userspace wants to send packets up to the one before kring->rhead, 891 * kernel knows kring->nr_hwcur is the first unsent packet. 892 * 893 * Here we push packets out (as many as possible), and possibly 894 * reclaim buffers from previously completed transmission. 895 * 896 * The caller (netmap) guarantees that there is only one instance 897 * running at any time. Any interference with other driver 898 * methods should be handled by the individual drivers. 899 */ 900 static int 901 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 902 { 903 struct netmap_adapter *na = kring->na; 904 if_t ifp = na->ifp; 905 struct netmap_ring *ring = kring->ring; 906 u_int nm_i; /* index into the netmap kring */ 907 u_int nic_i; /* index into the NIC ring */ 908 u_int n; 909 u_int const lim = kring->nkr_num_slots - 1; 910 u_int const head = kring->rhead; 911 struct if_pkt_info pi; 912 913 /* 914 * interrupts on every tx packet are expensive so request 915 * them every half ring, or where NS_REPORT is set 916 */ 917 u_int report_frequency = kring->nkr_num_slots >> 1; 918 /* device-specific */ 919 if_ctx_t ctx = ifp->if_softc; 920 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 921 922 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 923 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 924 925 /* 926 * First part: process new packets to send. 927 * nm_i is the current index in the netmap kring, 928 * nic_i is the corresponding index in the NIC ring. 929 * 930 * If we have packets to send (nm_i != head) 931 * iterate over the netmap ring, fetch length and update 932 * the corresponding slot in the NIC ring. Some drivers also 933 * need to update the buffer's physical address in the NIC slot 934 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 935 * 936 * The netmap_reload_map() calls is especially expensive, 937 * even when (as in this case) the tag is 0, so do only 938 * when the buffer has actually changed. 939 * 940 * If possible do not set the report/intr bit on all slots, 941 * but only a few times per ring or when NS_REPORT is set. 942 * 943 * Finally, on 10G and faster drivers, it might be useful 944 * to prefetch the next slot and txr entry. 945 */ 946 947 nm_i = kring->nr_hwcur; 948 if (nm_i != head) { /* we have new packets to send */ 949 pkt_info_zero(&pi); 950 pi.ipi_segs = txq->ift_segs; 951 pi.ipi_qsidx = kring->ring_id; 952 nic_i = netmap_idx_k2n(kring, nm_i); 953 954 __builtin_prefetch(&ring->slot[nm_i]); 955 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 956 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 957 958 for (n = 0; nm_i != head; n++) { 959 struct netmap_slot *slot = &ring->slot[nm_i]; 960 u_int len = slot->len; 961 uint64_t paddr; 962 void *addr = PNMB(na, slot, &paddr); 963 int flags = (slot->flags & NS_REPORT || 964 nic_i == 0 || nic_i == report_frequency) ? 965 IPI_TX_INTR : 0; 966 967 /* device-specific */ 968 pi.ipi_len = len; 969 pi.ipi_segs[0].ds_addr = paddr; 970 pi.ipi_segs[0].ds_len = len; 971 pi.ipi_nsegs = 1; 972 pi.ipi_ndescs = 0; 973 pi.ipi_pidx = nic_i; 974 pi.ipi_flags = flags; 975 976 /* Fill the slot in the NIC ring. */ 977 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 978 DBG_COUNTER_INC(tx_encap); 979 980 /* prefetch for next round */ 981 __builtin_prefetch(&ring->slot[nm_i + 1]); 982 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 983 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 984 985 NM_CHECK_ADDR_LEN(na, addr, len); 986 987 if (slot->flags & NS_BUF_CHANGED) { 988 /* buffer has changed, reload map */ 989 netmap_reload_map(na, txq->ift_buf_tag, 990 txq->ift_sds.ifsd_map[nic_i], addr); 991 } 992 /* make sure changes to the buffer are synced */ 993 bus_dmamap_sync(txq->ift_buf_tag, 994 txq->ift_sds.ifsd_map[nic_i], 995 BUS_DMASYNC_PREWRITE); 996 997 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 998 nm_i = nm_next(nm_i, lim); 999 nic_i = nm_next(nic_i, lim); 1000 } 1001 kring->nr_hwcur = nm_i; 1002 1003 /* synchronize the NIC ring */ 1004 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1005 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1006 1007 /* (re)start the tx unit up to slot nic_i (excluded) */ 1008 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1009 } 1010 1011 /* 1012 * Second part: reclaim buffers for completed transmissions. 1013 * 1014 * If there are unclaimed buffers, attempt to reclaim them. 1015 * If none are reclaimed, and TX IRQs are not in use, do an initial 1016 * minimal delay, then trigger the tx handler which will spin in the 1017 * group task queue. 1018 */ 1019 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1020 if (iflib_tx_credits_update(ctx, txq)) { 1021 /* some tx completed, increment avail */ 1022 nic_i = txq->ift_cidx_processed; 1023 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1024 } 1025 } 1026 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1027 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1028 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1029 iflib_timer, txq, txq->ift_timer.c_cpu); 1030 } 1031 return (0); 1032 } 1033 1034 /* 1035 * Reconcile kernel and user view of the receive ring. 1036 * Same as for the txsync, this routine must be efficient. 1037 * The caller guarantees a single invocations, but races against 1038 * the rest of the driver should be handled here. 1039 * 1040 * On call, kring->rhead is the first packet that userspace wants 1041 * to keep, and kring->rcur is the wakeup point. 1042 * The kernel has previously reported packets up to kring->rtail. 1043 * 1044 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1045 * of whether or not we received an interrupt. 1046 */ 1047 static int 1048 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1049 { 1050 struct netmap_adapter *na = kring->na; 1051 struct netmap_ring *ring = kring->ring; 1052 if_t ifp = na->ifp; 1053 iflib_fl_t fl; 1054 uint32_t nm_i; /* index into the netmap ring */ 1055 uint32_t nic_i; /* index into the NIC ring */ 1056 u_int i, n; 1057 u_int const lim = kring->nkr_num_slots - 1; 1058 u_int const head = kring->rhead; 1059 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1060 struct if_rxd_info ri; 1061 1062 if_ctx_t ctx = ifp->if_softc; 1063 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1064 if (head > lim) 1065 return netmap_ring_reinit(kring); 1066 1067 /* 1068 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far. 1069 */ 1070 1071 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1072 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1073 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1074 } 1075 1076 /* 1077 * First part: import newly received packets. 1078 * 1079 * nm_i is the index of the next free slot in the netmap ring, 1080 * nic_i is the index of the next received packet in the NIC ring, 1081 * and they may differ in case if_init() has been called while 1082 * in netmap mode. For the receive ring we have 1083 * 1084 * nic_i = rxr->next_check; 1085 * nm_i = kring->nr_hwtail (previous) 1086 * and 1087 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1088 * 1089 * rxr->next_check is set to 0 on a ring reinit 1090 */ 1091 if (netmap_no_pendintr || force_update) { 1092 int crclen = iflib_crcstrip ? 0 : 4; 1093 int error, avail; 1094 1095 for (i = 0; i < rxq->ifr_nfl; i++) { 1096 fl = &rxq->ifr_fl[i]; 1097 nic_i = fl->ifl_cidx; 1098 nm_i = netmap_idx_n2k(kring, nic_i); 1099 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1100 rxq->ifr_id, nic_i, USHRT_MAX); 1101 for (n = 0; avail > 0; n++, avail--) { 1102 rxd_info_zero(&ri); 1103 ri.iri_frags = rxq->ifr_frags; 1104 ri.iri_qsidx = kring->ring_id; 1105 ri.iri_ifp = ctx->ifc_ifp; 1106 ri.iri_cidx = nic_i; 1107 1108 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1109 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1110 ring->slot[nm_i].flags = 0; 1111 bus_dmamap_sync(fl->ifl_buf_tag, 1112 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1113 nm_i = nm_next(nm_i, lim); 1114 nic_i = nm_next(nic_i, lim); 1115 } 1116 if (n) { /* update the state variables */ 1117 if (netmap_no_pendintr && !force_update) { 1118 /* diagnostics */ 1119 iflib_rx_miss ++; 1120 iflib_rx_miss_bufs += n; 1121 } 1122 fl->ifl_cidx = nic_i; 1123 kring->nr_hwtail = nm_i; 1124 } 1125 kring->nr_kflags &= ~NKR_PENDINTR; 1126 } 1127 } 1128 /* 1129 * Second part: skip past packets that userspace has released. 1130 * (kring->nr_hwcur to head excluded), 1131 * and make the buffers available for reception. 1132 * As usual nm_i is the index in the netmap ring, 1133 * nic_i is the index in the NIC ring, and 1134 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1135 */ 1136 /* XXX not sure how this will work with multiple free lists */ 1137 nm_i = kring->nr_hwcur; 1138 1139 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1140 } 1141 1142 static void 1143 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1144 { 1145 if_ctx_t ctx = na->ifp->if_softc; 1146 1147 CTX_LOCK(ctx); 1148 if (onoff) { 1149 IFDI_INTR_ENABLE(ctx); 1150 } else { 1151 IFDI_INTR_DISABLE(ctx); 1152 } 1153 CTX_UNLOCK(ctx); 1154 } 1155 1156 1157 static int 1158 iflib_netmap_attach(if_ctx_t ctx) 1159 { 1160 struct netmap_adapter na; 1161 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1162 1163 bzero(&na, sizeof(na)); 1164 1165 na.ifp = ctx->ifc_ifp; 1166 na.na_flags = NAF_BDG_MAYSLEEP; 1167 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1168 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1169 1170 na.num_tx_desc = scctx->isc_ntxd[0]; 1171 na.num_rx_desc = scctx->isc_nrxd[0]; 1172 na.nm_txsync = iflib_netmap_txsync; 1173 na.nm_rxsync = iflib_netmap_rxsync; 1174 na.nm_register = iflib_netmap_register; 1175 na.nm_intr = iflib_netmap_intr; 1176 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1177 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1178 return (netmap_attach(&na)); 1179 } 1180 1181 static void 1182 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1183 { 1184 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1185 struct netmap_slot *slot; 1186 1187 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1188 if (slot == NULL) 1189 return; 1190 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1191 1192 /* 1193 * In netmap mode, set the map for the packet buffer. 1194 * NOTE: Some drivers (not this one) also need to set 1195 * the physical buffer address in the NIC ring. 1196 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1197 * netmap slot index, si 1198 */ 1199 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1200 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1201 NMB(na, slot + si)); 1202 } 1203 } 1204 1205 static void 1206 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1207 { 1208 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1209 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1210 struct netmap_slot *slot; 1211 uint32_t nm_i; 1212 1213 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1214 if (slot == NULL) 1215 return; 1216 nm_i = netmap_idx_n2k(kring, 0); 1217 netmap_fl_refill(rxq, kring, nm_i, true); 1218 } 1219 1220 static void 1221 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on) 1222 { 1223 struct netmap_kring *kring; 1224 uint16_t txqid; 1225 1226 txqid = txq->ift_id; 1227 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1228 1229 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1230 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1231 BUS_DMASYNC_POSTREAD); 1232 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1233 netmap_tx_irq(ctx->ifc_ifp, txqid); 1234 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1235 if (hz < 2000) 1236 *reset_on = 1; 1237 else 1238 *reset_on = hz / 1000; 1239 } 1240 } 1241 } 1242 1243 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1244 1245 #else 1246 #define iflib_netmap_txq_init(ctx, txq) 1247 #define iflib_netmap_rxq_init(ctx, rxq) 1248 #define iflib_netmap_detach(ifp) 1249 1250 #define iflib_netmap_attach(ctx) (0) 1251 #define netmap_rx_irq(ifp, qid, budget) (0) 1252 #define netmap_tx_irq(ifp, qid) do {} while (0) 1253 #define iflib_netmap_timer_adjust(ctx, txq, reset_on) 1254 #endif 1255 1256 #if defined(__i386__) || defined(__amd64__) 1257 static __inline void 1258 prefetch(void *x) 1259 { 1260 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1261 } 1262 static __inline void 1263 prefetch2cachelines(void *x) 1264 { 1265 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1266 #if (CACHE_LINE_SIZE < 128) 1267 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1268 #endif 1269 } 1270 #else 1271 #define prefetch(x) 1272 #define prefetch2cachelines(x) 1273 #endif 1274 1275 static void 1276 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1277 { 1278 iflib_fl_t fl; 1279 1280 fl = &rxq->ifr_fl[flid]; 1281 iru->iru_paddrs = fl->ifl_bus_addrs; 1282 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1283 iru->iru_idxs = fl->ifl_rxd_idxs; 1284 iru->iru_qsidx = rxq->ifr_id; 1285 iru->iru_buf_size = fl->ifl_buf_size; 1286 iru->iru_flidx = fl->ifl_id; 1287 } 1288 1289 static void 1290 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1291 { 1292 if (err) 1293 return; 1294 *(bus_addr_t *) arg = segs[0].ds_addr; 1295 } 1296 1297 int 1298 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1299 { 1300 int err; 1301 device_t dev = ctx->ifc_dev; 1302 1303 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1304 align, 0, /* alignment, bounds */ 1305 BUS_SPACE_MAXADDR, /* lowaddr */ 1306 BUS_SPACE_MAXADDR, /* highaddr */ 1307 NULL, NULL, /* filter, filterarg */ 1308 size, /* maxsize */ 1309 1, /* nsegments */ 1310 size, /* maxsegsize */ 1311 BUS_DMA_ALLOCNOW, /* flags */ 1312 NULL, /* lockfunc */ 1313 NULL, /* lockarg */ 1314 &dma->idi_tag); 1315 if (err) { 1316 device_printf(dev, 1317 "%s: bus_dma_tag_create failed: %d\n", 1318 __func__, err); 1319 goto fail_0; 1320 } 1321 1322 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1323 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1324 if (err) { 1325 device_printf(dev, 1326 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1327 __func__, (uintmax_t)size, err); 1328 goto fail_1; 1329 } 1330 1331 dma->idi_paddr = IF_BAD_DMA; 1332 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1333 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1334 if (err || dma->idi_paddr == IF_BAD_DMA) { 1335 device_printf(dev, 1336 "%s: bus_dmamap_load failed: %d\n", 1337 __func__, err); 1338 goto fail_2; 1339 } 1340 1341 dma->idi_size = size; 1342 return (0); 1343 1344 fail_2: 1345 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1346 fail_1: 1347 bus_dma_tag_destroy(dma->idi_tag); 1348 fail_0: 1349 dma->idi_tag = NULL; 1350 1351 return (err); 1352 } 1353 1354 int 1355 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1356 { 1357 if_shared_ctx_t sctx = ctx->ifc_sctx; 1358 1359 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1360 1361 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1362 } 1363 1364 int 1365 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1366 { 1367 int i, err; 1368 iflib_dma_info_t *dmaiter; 1369 1370 dmaiter = dmalist; 1371 for (i = 0; i < count; i++, dmaiter++) { 1372 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1373 break; 1374 } 1375 if (err) 1376 iflib_dma_free_multi(dmalist, i); 1377 return (err); 1378 } 1379 1380 void 1381 iflib_dma_free(iflib_dma_info_t dma) 1382 { 1383 if (dma->idi_tag == NULL) 1384 return; 1385 if (dma->idi_paddr != IF_BAD_DMA) { 1386 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1387 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1388 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1389 dma->idi_paddr = IF_BAD_DMA; 1390 } 1391 if (dma->idi_vaddr != NULL) { 1392 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1393 dma->idi_vaddr = NULL; 1394 } 1395 bus_dma_tag_destroy(dma->idi_tag); 1396 dma->idi_tag = NULL; 1397 } 1398 1399 void 1400 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1401 { 1402 int i; 1403 iflib_dma_info_t *dmaiter = dmalist; 1404 1405 for (i = 0; i < count; i++, dmaiter++) 1406 iflib_dma_free(*dmaiter); 1407 } 1408 1409 #ifdef EARLY_AP_STARTUP 1410 static const int iflib_started = 1; 1411 #else 1412 /* 1413 * We used to abuse the smp_started flag to decide if the queues have been 1414 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1415 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1416 * is set. Run a SYSINIT() strictly after that to just set a usable 1417 * completion flag. 1418 */ 1419 1420 static int iflib_started; 1421 1422 static void 1423 iflib_record_started(void *arg) 1424 { 1425 iflib_started = 1; 1426 } 1427 1428 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1429 iflib_record_started, NULL); 1430 #endif 1431 1432 static int 1433 iflib_fast_intr(void *arg) 1434 { 1435 iflib_filter_info_t info = arg; 1436 struct grouptask *gtask = info->ifi_task; 1437 int result; 1438 1439 if (!iflib_started) 1440 return (FILTER_STRAY); 1441 1442 DBG_COUNTER_INC(fast_intrs); 1443 if (info->ifi_filter != NULL) { 1444 result = info->ifi_filter(info->ifi_filter_arg); 1445 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1446 return (result); 1447 } 1448 1449 GROUPTASK_ENQUEUE(gtask); 1450 return (FILTER_HANDLED); 1451 } 1452 1453 static int 1454 iflib_fast_intr_rxtx(void *arg) 1455 { 1456 iflib_filter_info_t info = arg; 1457 struct grouptask *gtask = info->ifi_task; 1458 if_ctx_t ctx; 1459 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1460 iflib_txq_t txq; 1461 void *sc; 1462 int i, cidx, result; 1463 qidx_t txqid; 1464 bool intr_enable, intr_legacy; 1465 1466 if (!iflib_started) 1467 return (FILTER_STRAY); 1468 1469 DBG_COUNTER_INC(fast_intrs); 1470 if (info->ifi_filter != NULL) { 1471 result = info->ifi_filter(info->ifi_filter_arg); 1472 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1473 return (result); 1474 } 1475 1476 ctx = rxq->ifr_ctx; 1477 sc = ctx->ifc_softc; 1478 intr_enable = false; 1479 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1480 MPASS(rxq->ifr_ntxqirq); 1481 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1482 txqid = rxq->ifr_txqid[i]; 1483 txq = &ctx->ifc_txqs[txqid]; 1484 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1485 BUS_DMASYNC_POSTREAD); 1486 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1487 if (intr_legacy) 1488 intr_enable = true; 1489 else 1490 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1491 continue; 1492 } 1493 GROUPTASK_ENQUEUE(&txq->ift_task); 1494 } 1495 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1496 cidx = rxq->ifr_cq_cidx; 1497 else 1498 cidx = rxq->ifr_fl[0].ifl_cidx; 1499 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1500 GROUPTASK_ENQUEUE(gtask); 1501 else { 1502 if (intr_legacy) 1503 intr_enable = true; 1504 else 1505 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1506 DBG_COUNTER_INC(rx_intr_enables); 1507 } 1508 if (intr_enable) 1509 IFDI_INTR_ENABLE(ctx); 1510 return (FILTER_HANDLED); 1511 } 1512 1513 1514 static int 1515 iflib_fast_intr_ctx(void *arg) 1516 { 1517 iflib_filter_info_t info = arg; 1518 struct grouptask *gtask = info->ifi_task; 1519 int result; 1520 1521 if (!iflib_started) 1522 return (FILTER_STRAY); 1523 1524 DBG_COUNTER_INC(fast_intrs); 1525 if (info->ifi_filter != NULL) { 1526 result = info->ifi_filter(info->ifi_filter_arg); 1527 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1528 return (result); 1529 } 1530 1531 GROUPTASK_ENQUEUE(gtask); 1532 return (FILTER_HANDLED); 1533 } 1534 1535 static int 1536 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1537 driver_filter_t filter, driver_intr_t handler, void *arg, 1538 const char *name) 1539 { 1540 struct resource *res; 1541 void *tag = NULL; 1542 device_t dev = ctx->ifc_dev; 1543 int flags, i, rc; 1544 1545 flags = RF_ACTIVE; 1546 if (ctx->ifc_flags & IFC_LEGACY) 1547 flags |= RF_SHAREABLE; 1548 MPASS(rid < 512); 1549 i = rid; 1550 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1551 if (res == NULL) { 1552 device_printf(dev, 1553 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1554 return (ENOMEM); 1555 } 1556 irq->ii_res = res; 1557 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1558 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1559 filter, handler, arg, &tag); 1560 if (rc != 0) { 1561 device_printf(dev, 1562 "failed to setup interrupt for rid %d, name %s: %d\n", 1563 rid, name ? name : "unknown", rc); 1564 return (rc); 1565 } else if (name) 1566 bus_describe_intr(dev, res, tag, "%s", name); 1567 1568 irq->ii_tag = tag; 1569 return (0); 1570 } 1571 1572 /********************************************************************* 1573 * 1574 * Allocate DMA resources for TX buffers as well as memory for the TX 1575 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1576 * iflib_sw_tx_desc_array structure, storing all the information that 1577 * is needed to transmit a packet on the wire. This is called only 1578 * once at attach, setup is done every reset. 1579 * 1580 **********************************************************************/ 1581 static int 1582 iflib_txsd_alloc(iflib_txq_t txq) 1583 { 1584 if_ctx_t ctx = txq->ift_ctx; 1585 if_shared_ctx_t sctx = ctx->ifc_sctx; 1586 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1587 device_t dev = ctx->ifc_dev; 1588 bus_size_t tsomaxsize; 1589 int err, nsegments, ntsosegments; 1590 bool tso; 1591 1592 nsegments = scctx->isc_tx_nsegments; 1593 ntsosegments = scctx->isc_tx_tso_segments_max; 1594 tsomaxsize = scctx->isc_tx_tso_size_max; 1595 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1596 tsomaxsize += sizeof(struct ether_vlan_header); 1597 MPASS(scctx->isc_ntxd[0] > 0); 1598 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1599 MPASS(nsegments > 0); 1600 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1601 MPASS(ntsosegments > 0); 1602 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1603 } 1604 1605 /* 1606 * Set up DMA tags for TX buffers. 1607 */ 1608 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1609 1, 0, /* alignment, bounds */ 1610 BUS_SPACE_MAXADDR, /* lowaddr */ 1611 BUS_SPACE_MAXADDR, /* highaddr */ 1612 NULL, NULL, /* filter, filterarg */ 1613 sctx->isc_tx_maxsize, /* maxsize */ 1614 nsegments, /* nsegments */ 1615 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1616 0, /* flags */ 1617 NULL, /* lockfunc */ 1618 NULL, /* lockfuncarg */ 1619 &txq->ift_buf_tag))) { 1620 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1621 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1622 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1623 goto fail; 1624 } 1625 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1626 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1627 1, 0, /* alignment, bounds */ 1628 BUS_SPACE_MAXADDR, /* lowaddr */ 1629 BUS_SPACE_MAXADDR, /* highaddr */ 1630 NULL, NULL, /* filter, filterarg */ 1631 tsomaxsize, /* maxsize */ 1632 ntsosegments, /* nsegments */ 1633 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1634 0, /* flags */ 1635 NULL, /* lockfunc */ 1636 NULL, /* lockfuncarg */ 1637 &txq->ift_tso_buf_tag))) { 1638 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1639 err); 1640 goto fail; 1641 } 1642 1643 /* Allocate memory for the TX mbuf map. */ 1644 if (!(txq->ift_sds.ifsd_m = 1645 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1646 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1647 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1648 err = ENOMEM; 1649 goto fail; 1650 } 1651 1652 /* 1653 * Create the DMA maps for TX buffers. 1654 */ 1655 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1656 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1657 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1658 device_printf(dev, 1659 "Unable to allocate TX buffer DMA map memory\n"); 1660 err = ENOMEM; 1661 goto fail; 1662 } 1663 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1664 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1665 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1666 device_printf(dev, 1667 "Unable to allocate TSO TX buffer map memory\n"); 1668 err = ENOMEM; 1669 goto fail; 1670 } 1671 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1672 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1673 &txq->ift_sds.ifsd_map[i]); 1674 if (err != 0) { 1675 device_printf(dev, "Unable to create TX DMA map\n"); 1676 goto fail; 1677 } 1678 if (!tso) 1679 continue; 1680 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1681 &txq->ift_sds.ifsd_tso_map[i]); 1682 if (err != 0) { 1683 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1684 goto fail; 1685 } 1686 } 1687 return (0); 1688 fail: 1689 /* We free all, it handles case where we are in the middle */ 1690 iflib_tx_structures_free(ctx); 1691 return (err); 1692 } 1693 1694 static void 1695 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1696 { 1697 bus_dmamap_t map; 1698 1699 map = NULL; 1700 if (txq->ift_sds.ifsd_map != NULL) 1701 map = txq->ift_sds.ifsd_map[i]; 1702 if (map != NULL) { 1703 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1704 bus_dmamap_unload(txq->ift_buf_tag, map); 1705 bus_dmamap_destroy(txq->ift_buf_tag, map); 1706 txq->ift_sds.ifsd_map[i] = NULL; 1707 } 1708 1709 map = NULL; 1710 if (txq->ift_sds.ifsd_tso_map != NULL) 1711 map = txq->ift_sds.ifsd_tso_map[i]; 1712 if (map != NULL) { 1713 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1714 BUS_DMASYNC_POSTWRITE); 1715 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1716 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1717 txq->ift_sds.ifsd_tso_map[i] = NULL; 1718 } 1719 } 1720 1721 static void 1722 iflib_txq_destroy(iflib_txq_t txq) 1723 { 1724 if_ctx_t ctx = txq->ift_ctx; 1725 1726 for (int i = 0; i < txq->ift_size; i++) 1727 iflib_txsd_destroy(ctx, txq, i); 1728 1729 if (txq->ift_br != NULL) { 1730 ifmp_ring_free(txq->ift_br); 1731 txq->ift_br = NULL; 1732 } 1733 1734 mtx_destroy(&txq->ift_mtx); 1735 1736 if (txq->ift_sds.ifsd_map != NULL) { 1737 free(txq->ift_sds.ifsd_map, M_IFLIB); 1738 txq->ift_sds.ifsd_map = NULL; 1739 } 1740 if (txq->ift_sds.ifsd_tso_map != NULL) { 1741 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1742 txq->ift_sds.ifsd_tso_map = NULL; 1743 } 1744 if (txq->ift_sds.ifsd_m != NULL) { 1745 free(txq->ift_sds.ifsd_m, M_IFLIB); 1746 txq->ift_sds.ifsd_m = NULL; 1747 } 1748 if (txq->ift_buf_tag != NULL) { 1749 bus_dma_tag_destroy(txq->ift_buf_tag); 1750 txq->ift_buf_tag = NULL; 1751 } 1752 if (txq->ift_tso_buf_tag != NULL) { 1753 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1754 txq->ift_tso_buf_tag = NULL; 1755 } 1756 if (txq->ift_ifdi != NULL) { 1757 free(txq->ift_ifdi, M_IFLIB); 1758 } 1759 } 1760 1761 static void 1762 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1763 { 1764 struct mbuf **mp; 1765 1766 mp = &txq->ift_sds.ifsd_m[i]; 1767 if (*mp == NULL) 1768 return; 1769 1770 if (txq->ift_sds.ifsd_map != NULL) { 1771 bus_dmamap_sync(txq->ift_buf_tag, 1772 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1773 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1774 } 1775 if (txq->ift_sds.ifsd_tso_map != NULL) { 1776 bus_dmamap_sync(txq->ift_tso_buf_tag, 1777 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1778 bus_dmamap_unload(txq->ift_tso_buf_tag, 1779 txq->ift_sds.ifsd_tso_map[i]); 1780 } 1781 m_free(*mp); 1782 DBG_COUNTER_INC(tx_frees); 1783 *mp = NULL; 1784 } 1785 1786 static int 1787 iflib_txq_setup(iflib_txq_t txq) 1788 { 1789 if_ctx_t ctx = txq->ift_ctx; 1790 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1791 if_shared_ctx_t sctx = ctx->ifc_sctx; 1792 iflib_dma_info_t di; 1793 int i; 1794 1795 /* Set number of descriptors available */ 1796 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1797 /* XXX make configurable */ 1798 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1799 1800 /* Reset indices */ 1801 txq->ift_cidx_processed = 0; 1802 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1803 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1804 1805 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1806 bzero((void *)di->idi_vaddr, di->idi_size); 1807 1808 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1809 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1810 bus_dmamap_sync(di->idi_tag, di->idi_map, 1811 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1812 return (0); 1813 } 1814 1815 /********************************************************************* 1816 * 1817 * Allocate DMA resources for RX buffers as well as memory for the RX 1818 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1819 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1820 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1821 * Since we use use one entry in iflib_sw_rx_desc_array per received 1822 * packet, the maximum number of entries we'll need is equal to the 1823 * number of hardware receive descriptors that we've allocated. 1824 * 1825 **********************************************************************/ 1826 static int 1827 iflib_rxsd_alloc(iflib_rxq_t rxq) 1828 { 1829 if_ctx_t ctx = rxq->ifr_ctx; 1830 if_shared_ctx_t sctx = ctx->ifc_sctx; 1831 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1832 device_t dev = ctx->ifc_dev; 1833 iflib_fl_t fl; 1834 int err; 1835 1836 MPASS(scctx->isc_nrxd[0] > 0); 1837 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1838 1839 fl = rxq->ifr_fl; 1840 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1841 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1842 /* Set up DMA tag for RX buffers. */ 1843 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1844 1, 0, /* alignment, bounds */ 1845 BUS_SPACE_MAXADDR, /* lowaddr */ 1846 BUS_SPACE_MAXADDR, /* highaddr */ 1847 NULL, NULL, /* filter, filterarg */ 1848 sctx->isc_rx_maxsize, /* maxsize */ 1849 sctx->isc_rx_nsegments, /* nsegments */ 1850 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1851 0, /* flags */ 1852 NULL, /* lockfunc */ 1853 NULL, /* lockarg */ 1854 &fl->ifl_buf_tag); 1855 if (err) { 1856 device_printf(dev, 1857 "Unable to allocate RX DMA tag: %d\n", err); 1858 goto fail; 1859 } 1860 1861 /* Allocate memory for the RX mbuf map. */ 1862 if (!(fl->ifl_sds.ifsd_m = 1863 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1864 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1865 device_printf(dev, 1866 "Unable to allocate RX mbuf map memory\n"); 1867 err = ENOMEM; 1868 goto fail; 1869 } 1870 1871 /* Allocate memory for the direct RX cluster pointer map. */ 1872 if (!(fl->ifl_sds.ifsd_cl = 1873 (caddr_t *) malloc(sizeof(caddr_t) * 1874 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1875 device_printf(dev, 1876 "Unable to allocate RX cluster map memory\n"); 1877 err = ENOMEM; 1878 goto fail; 1879 } 1880 1881 /* Allocate memory for the RX cluster bus address map. */ 1882 if (!(fl->ifl_sds.ifsd_ba = 1883 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1884 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1885 device_printf(dev, 1886 "Unable to allocate RX bus address map memory\n"); 1887 err = ENOMEM; 1888 goto fail; 1889 } 1890 1891 /* 1892 * Create the DMA maps for RX buffers. 1893 */ 1894 if (!(fl->ifl_sds.ifsd_map = 1895 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1896 device_printf(dev, 1897 "Unable to allocate RX buffer DMA map memory\n"); 1898 err = ENOMEM; 1899 goto fail; 1900 } 1901 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1902 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1903 &fl->ifl_sds.ifsd_map[i]); 1904 if (err != 0) { 1905 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1906 goto fail; 1907 } 1908 } 1909 } 1910 return (0); 1911 1912 fail: 1913 iflib_rx_structures_free(ctx); 1914 return (err); 1915 } 1916 1917 1918 /* 1919 * Internal service routines 1920 */ 1921 1922 struct rxq_refill_cb_arg { 1923 int error; 1924 bus_dma_segment_t seg; 1925 int nseg; 1926 }; 1927 1928 static void 1929 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1930 { 1931 struct rxq_refill_cb_arg *cb_arg = arg; 1932 1933 cb_arg->error = error; 1934 cb_arg->seg = segs[0]; 1935 cb_arg->nseg = nseg; 1936 } 1937 1938 /** 1939 * _iflib_fl_refill - refill an rxq free-buffer list 1940 * @ctx: the iflib context 1941 * @fl: the free list to refill 1942 * @count: the number of new buffers to allocate 1943 * 1944 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 1945 * The caller must assure that @count does not exceed the queue's capacity. 1946 */ 1947 static void 1948 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1949 { 1950 struct if_rxd_update iru; 1951 struct rxq_refill_cb_arg cb_arg; 1952 struct mbuf *m; 1953 caddr_t cl, *sd_cl; 1954 struct mbuf **sd_m; 1955 bus_dmamap_t *sd_map; 1956 bus_addr_t bus_addr, *sd_ba; 1957 int err, frag_idx, i, idx, n, pidx; 1958 qidx_t credits; 1959 1960 sd_m = fl->ifl_sds.ifsd_m; 1961 sd_map = fl->ifl_sds.ifsd_map; 1962 sd_cl = fl->ifl_sds.ifsd_cl; 1963 sd_ba = fl->ifl_sds.ifsd_ba; 1964 pidx = fl->ifl_pidx; 1965 idx = pidx; 1966 frag_idx = fl->ifl_fragidx; 1967 credits = fl->ifl_credits; 1968 1969 i = 0; 1970 n = count; 1971 MPASS(n > 0); 1972 MPASS(credits + n <= fl->ifl_size); 1973 1974 if (pidx < fl->ifl_cidx) 1975 MPASS(pidx + n <= fl->ifl_cidx); 1976 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1977 MPASS(fl->ifl_gen == 0); 1978 if (pidx > fl->ifl_cidx) 1979 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1980 1981 DBG_COUNTER_INC(fl_refills); 1982 if (n > 8) 1983 DBG_COUNTER_INC(fl_refills_large); 1984 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1985 while (n--) { 1986 /* 1987 * We allocate an uninitialized mbuf + cluster, mbuf is 1988 * initialized after rx. 1989 * 1990 * If the cluster is still set then we know a minimum sized packet was received 1991 */ 1992 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 1993 &frag_idx); 1994 if (frag_idx < 0) 1995 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1996 MPASS(frag_idx >= 0); 1997 if ((cl = sd_cl[frag_idx]) == NULL) { 1998 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1999 break; 2000 2001 cb_arg.error = 0; 2002 MPASS(sd_map != NULL); 2003 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2004 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2005 BUS_DMA_NOWAIT); 2006 if (err != 0 || cb_arg.error) { 2007 /* 2008 * !zone_pack ? 2009 */ 2010 if (fl->ifl_zone == zone_pack) 2011 uma_zfree(fl->ifl_zone, cl); 2012 break; 2013 } 2014 2015 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2016 sd_cl[frag_idx] = cl; 2017 #if MEMORY_LOGGING 2018 fl->ifl_cl_enqueued++; 2019 #endif 2020 } else { 2021 bus_addr = sd_ba[frag_idx]; 2022 } 2023 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2024 BUS_DMASYNC_PREREAD); 2025 2026 if (sd_m[frag_idx] == NULL) { 2027 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 2028 break; 2029 } 2030 sd_m[frag_idx] = m; 2031 } 2032 bit_set(fl->ifl_rx_bitmap, frag_idx); 2033 #if MEMORY_LOGGING 2034 fl->ifl_m_enqueued++; 2035 #endif 2036 2037 DBG_COUNTER_INC(rx_allocs); 2038 fl->ifl_rxd_idxs[i] = frag_idx; 2039 fl->ifl_bus_addrs[i] = bus_addr; 2040 fl->ifl_vm_addrs[i] = cl; 2041 credits++; 2042 i++; 2043 MPASS(credits <= fl->ifl_size); 2044 if (++idx == fl->ifl_size) { 2045 fl->ifl_gen = 1; 2046 idx = 0; 2047 } 2048 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2049 iru.iru_pidx = pidx; 2050 iru.iru_count = i; 2051 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2052 i = 0; 2053 pidx = idx; 2054 fl->ifl_pidx = idx; 2055 fl->ifl_credits = credits; 2056 } 2057 } 2058 2059 if (i) { 2060 iru.iru_pidx = pidx; 2061 iru.iru_count = i; 2062 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2063 fl->ifl_pidx = idx; 2064 fl->ifl_credits = credits; 2065 } 2066 DBG_COUNTER_INC(rxd_flush); 2067 if (fl->ifl_pidx == 0) 2068 pidx = fl->ifl_size - 1; 2069 else 2070 pidx = fl->ifl_pidx - 1; 2071 2072 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2073 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2074 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2075 fl->ifl_fragidx = frag_idx; 2076 } 2077 2078 static __inline void 2079 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2080 { 2081 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2082 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2083 #ifdef INVARIANTS 2084 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2085 #endif 2086 2087 MPASS(fl->ifl_credits <= fl->ifl_size); 2088 MPASS(reclaimable == delta); 2089 2090 if (reclaimable > 0) 2091 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2092 } 2093 2094 uint8_t 2095 iflib_in_detach(if_ctx_t ctx) 2096 { 2097 bool in_detach; 2098 2099 STATE_LOCK(ctx); 2100 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2101 STATE_UNLOCK(ctx); 2102 return (in_detach); 2103 } 2104 2105 static void 2106 iflib_fl_bufs_free(iflib_fl_t fl) 2107 { 2108 iflib_dma_info_t idi = fl->ifl_ifdi; 2109 bus_dmamap_t sd_map; 2110 uint32_t i; 2111 2112 for (i = 0; i < fl->ifl_size; i++) { 2113 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2114 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2115 2116 if (*sd_cl != NULL) { 2117 sd_map = fl->ifl_sds.ifsd_map[i]; 2118 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2119 BUS_DMASYNC_POSTREAD); 2120 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2121 if (*sd_cl != NULL) 2122 uma_zfree(fl->ifl_zone, *sd_cl); 2123 // XXX: Should this get moved out? 2124 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx)) 2125 bus_dmamap_destroy(fl->ifl_buf_tag, sd_map); 2126 if (*sd_m != NULL) { 2127 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2128 uma_zfree(zone_mbuf, *sd_m); 2129 } 2130 } else { 2131 MPASS(*sd_cl == NULL); 2132 MPASS(*sd_m == NULL); 2133 } 2134 #if MEMORY_LOGGING 2135 fl->ifl_m_dequeued++; 2136 fl->ifl_cl_dequeued++; 2137 #endif 2138 *sd_cl = NULL; 2139 *sd_m = NULL; 2140 } 2141 #ifdef INVARIANTS 2142 for (i = 0; i < fl->ifl_size; i++) { 2143 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2144 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2145 } 2146 #endif 2147 /* 2148 * Reset free list values 2149 */ 2150 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2151 bzero(idi->idi_vaddr, idi->idi_size); 2152 } 2153 2154 /********************************************************************* 2155 * 2156 * Initialize a free list and its buffers. 2157 * 2158 **********************************************************************/ 2159 static int 2160 iflib_fl_setup(iflib_fl_t fl) 2161 { 2162 iflib_rxq_t rxq = fl->ifl_rxq; 2163 if_ctx_t ctx = rxq->ifr_ctx; 2164 2165 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2166 /* 2167 ** Free current RX buffer structs and their mbufs 2168 */ 2169 iflib_fl_bufs_free(fl); 2170 /* Now replenish the mbufs */ 2171 MPASS(fl->ifl_credits == 0); 2172 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2173 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2174 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2175 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2176 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2177 2178 2179 /* avoid pre-allocating zillions of clusters to an idle card 2180 * potentially speeding up attach 2181 */ 2182 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2183 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2184 if (min(128, fl->ifl_size) != fl->ifl_credits) 2185 return (ENOBUFS); 2186 /* 2187 * handle failure 2188 */ 2189 MPASS(rxq != NULL); 2190 MPASS(fl->ifl_ifdi != NULL); 2191 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2192 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2193 return (0); 2194 } 2195 2196 /********************************************************************* 2197 * 2198 * Free receive ring data structures 2199 * 2200 **********************************************************************/ 2201 static void 2202 iflib_rx_sds_free(iflib_rxq_t rxq) 2203 { 2204 iflib_fl_t fl; 2205 int i, j; 2206 2207 if (rxq->ifr_fl != NULL) { 2208 for (i = 0; i < rxq->ifr_nfl; i++) { 2209 fl = &rxq->ifr_fl[i]; 2210 if (fl->ifl_buf_tag != NULL) { 2211 if (fl->ifl_sds.ifsd_map != NULL) { 2212 for (j = 0; j < fl->ifl_size; j++) { 2213 if (fl->ifl_sds.ifsd_map[j] == 2214 NULL) 2215 continue; 2216 bus_dmamap_sync( 2217 fl->ifl_buf_tag, 2218 fl->ifl_sds.ifsd_map[j], 2219 BUS_DMASYNC_POSTREAD); 2220 bus_dmamap_unload( 2221 fl->ifl_buf_tag, 2222 fl->ifl_sds.ifsd_map[j]); 2223 } 2224 } 2225 bus_dma_tag_destroy(fl->ifl_buf_tag); 2226 fl->ifl_buf_tag = NULL; 2227 } 2228 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2229 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2230 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2231 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2232 fl->ifl_sds.ifsd_m = NULL; 2233 fl->ifl_sds.ifsd_cl = NULL; 2234 fl->ifl_sds.ifsd_ba = NULL; 2235 fl->ifl_sds.ifsd_map = NULL; 2236 } 2237 free(rxq->ifr_fl, M_IFLIB); 2238 rxq->ifr_fl = NULL; 2239 free(rxq->ifr_ifdi, M_IFLIB); 2240 rxq->ifr_ifdi = NULL; 2241 rxq->ifr_cq_cidx = 0; 2242 } 2243 } 2244 2245 /* 2246 * Timer routine 2247 */ 2248 static void 2249 iflib_timer(void *arg) 2250 { 2251 iflib_txq_t txq = arg; 2252 if_ctx_t ctx = txq->ift_ctx; 2253 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2254 uint64_t this_tick = ticks; 2255 uint32_t reset_on = hz / 2; 2256 2257 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2258 return; 2259 2260 /* 2261 ** Check on the state of the TX queue(s), this 2262 ** can be done without the lock because its RO 2263 ** and the HUNG state will be static if set. 2264 */ 2265 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2266 txq->ift_last_timer_tick = this_tick; 2267 IFDI_TIMER(ctx, txq->ift_id); 2268 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2269 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2270 (sctx->isc_pause_frames == 0))) 2271 goto hung; 2272 2273 if (ifmp_ring_is_stalled(txq->ift_br)) 2274 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2275 txq->ift_cleaned_prev = txq->ift_cleaned; 2276 } 2277 #ifdef DEV_NETMAP 2278 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2279 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 2280 #endif 2281 /* handle any laggards */ 2282 if (txq->ift_db_pending) 2283 GROUPTASK_ENQUEUE(&txq->ift_task); 2284 2285 sctx->isc_pause_frames = 0; 2286 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2287 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2288 return; 2289 2290 hung: 2291 device_printf(ctx->ifc_dev, 2292 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2293 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2294 STATE_LOCK(ctx); 2295 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2296 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2297 iflib_admin_intr_deferred(ctx); 2298 STATE_UNLOCK(ctx); 2299 } 2300 2301 static void 2302 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2303 { 2304 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2305 2306 /* 2307 * XXX don't set the max_frame_size to larger 2308 * than the hardware can handle 2309 */ 2310 if (sctx->isc_max_frame_size <= MCLBYTES) 2311 ctx->ifc_rx_mbuf_sz = MCLBYTES; 2312 else 2313 ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE; 2314 } 2315 2316 uint32_t 2317 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2318 { 2319 2320 return (ctx->ifc_rx_mbuf_sz); 2321 } 2322 2323 static void 2324 iflib_init_locked(if_ctx_t ctx) 2325 { 2326 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2327 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2328 if_t ifp = ctx->ifc_ifp; 2329 iflib_fl_t fl; 2330 iflib_txq_t txq; 2331 iflib_rxq_t rxq; 2332 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2333 2334 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2335 IFDI_INTR_DISABLE(ctx); 2336 2337 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2338 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2339 /* Set hardware offload abilities */ 2340 if_clearhwassist(ifp); 2341 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2342 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2343 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2344 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2345 if (if_getcapenable(ifp) & IFCAP_TSO4) 2346 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2347 if (if_getcapenable(ifp) & IFCAP_TSO6) 2348 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2349 2350 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2351 CALLOUT_LOCK(txq); 2352 callout_stop(&txq->ift_timer); 2353 CALLOUT_UNLOCK(txq); 2354 iflib_netmap_txq_init(ctx, txq); 2355 } 2356 2357 /* 2358 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2359 * that drivers can use the value when setting up the hardware receive 2360 * buffers. 2361 */ 2362 iflib_calc_rx_mbuf_sz(ctx); 2363 2364 #ifdef INVARIANTS 2365 i = if_getdrvflags(ifp); 2366 #endif 2367 IFDI_INIT(ctx); 2368 MPASS(if_getdrvflags(ifp) == i); 2369 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2370 /* XXX this should really be done on a per-queue basis */ 2371 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2372 MPASS(rxq->ifr_id == i); 2373 iflib_netmap_rxq_init(ctx, rxq); 2374 continue; 2375 } 2376 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2377 if (iflib_fl_setup(fl)) { 2378 device_printf(ctx->ifc_dev, 2379 "setting up free list %d failed - " 2380 "check cluster settings\n", j); 2381 goto done; 2382 } 2383 } 2384 } 2385 done: 2386 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2387 IFDI_INTR_ENABLE(ctx); 2388 txq = ctx->ifc_txqs; 2389 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2390 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2391 txq->ift_timer.c_cpu); 2392 } 2393 2394 static int 2395 iflib_media_change(if_t ifp) 2396 { 2397 if_ctx_t ctx = if_getsoftc(ifp); 2398 int err; 2399 2400 CTX_LOCK(ctx); 2401 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2402 iflib_init_locked(ctx); 2403 CTX_UNLOCK(ctx); 2404 return (err); 2405 } 2406 2407 static void 2408 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2409 { 2410 if_ctx_t ctx = if_getsoftc(ifp); 2411 2412 CTX_LOCK(ctx); 2413 IFDI_UPDATE_ADMIN_STATUS(ctx); 2414 IFDI_MEDIA_STATUS(ctx, ifmr); 2415 CTX_UNLOCK(ctx); 2416 } 2417 2418 void 2419 iflib_stop(if_ctx_t ctx) 2420 { 2421 iflib_txq_t txq = ctx->ifc_txqs; 2422 iflib_rxq_t rxq = ctx->ifc_rxqs; 2423 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2424 if_shared_ctx_t sctx = ctx->ifc_sctx; 2425 iflib_dma_info_t di; 2426 iflib_fl_t fl; 2427 int i, j; 2428 2429 /* Tell the stack that the interface is no longer active */ 2430 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2431 2432 IFDI_INTR_DISABLE(ctx); 2433 DELAY(1000); 2434 IFDI_STOP(ctx); 2435 DELAY(1000); 2436 2437 iflib_debug_reset(); 2438 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2439 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2440 /* make sure all transmitters have completed before proceeding XXX */ 2441 2442 CALLOUT_LOCK(txq); 2443 callout_stop(&txq->ift_timer); 2444 CALLOUT_UNLOCK(txq); 2445 2446 /* clean any enqueued buffers */ 2447 iflib_ifmp_purge(txq); 2448 /* Free any existing tx buffers. */ 2449 for (j = 0; j < txq->ift_size; j++) { 2450 iflib_txsd_free(ctx, txq, j); 2451 } 2452 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2453 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2454 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2455 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2456 txq->ift_pullups = 0; 2457 ifmp_ring_reset_stats(txq->ift_br); 2458 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2459 bzero((void *)di->idi_vaddr, di->idi_size); 2460 } 2461 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2462 /* make sure all transmitters have completed before proceeding XXX */ 2463 2464 rxq->ifr_cq_cidx = 0; 2465 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2466 bzero((void *)di->idi_vaddr, di->idi_size); 2467 /* also resets the free lists pidx/cidx */ 2468 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2469 iflib_fl_bufs_free(fl); 2470 } 2471 } 2472 2473 static inline caddr_t 2474 calc_next_rxd(iflib_fl_t fl, int cidx) 2475 { 2476 qidx_t size; 2477 int nrxd; 2478 caddr_t start, end, cur, next; 2479 2480 nrxd = fl->ifl_size; 2481 size = fl->ifl_rxd_size; 2482 start = fl->ifl_ifdi->idi_vaddr; 2483 2484 if (__predict_false(size == 0)) 2485 return (start); 2486 cur = start + size*cidx; 2487 end = start + size*nrxd; 2488 next = CACHE_PTR_NEXT(cur); 2489 return (next < end ? next : start); 2490 } 2491 2492 static inline void 2493 prefetch_pkts(iflib_fl_t fl, int cidx) 2494 { 2495 int nextptr; 2496 int nrxd = fl->ifl_size; 2497 caddr_t next_rxd; 2498 2499 2500 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2501 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2502 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2503 next_rxd = calc_next_rxd(fl, cidx); 2504 prefetch(next_rxd); 2505 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2506 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2507 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2508 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2509 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2510 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2511 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2512 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2513 } 2514 2515 static struct mbuf * 2516 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2517 int *pf_rv, if_rxd_info_t ri) 2518 { 2519 bus_dmamap_t map; 2520 iflib_fl_t fl; 2521 caddr_t payload; 2522 struct mbuf *m; 2523 int flid, cidx, len, next; 2524 2525 map = NULL; 2526 flid = irf->irf_flid; 2527 cidx = irf->irf_idx; 2528 fl = &rxq->ifr_fl[flid]; 2529 sd->ifsd_fl = fl; 2530 sd->ifsd_cidx = cidx; 2531 m = fl->ifl_sds.ifsd_m[cidx]; 2532 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2533 fl->ifl_credits--; 2534 #if MEMORY_LOGGING 2535 fl->ifl_m_dequeued++; 2536 #endif 2537 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2538 prefetch_pkts(fl, cidx); 2539 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2540 prefetch(&fl->ifl_sds.ifsd_map[next]); 2541 map = fl->ifl_sds.ifsd_map[cidx]; 2542 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2543 2544 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2545 MPASS(fl->ifl_cidx == cidx); 2546 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2547 2548 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL) { 2549 payload = *sd->ifsd_cl; 2550 payload += ri->iri_pad; 2551 len = ri->iri_len - ri->iri_pad; 2552 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2553 len | PFIL_MEMPTR | PFIL_IN, NULL); 2554 switch (*pf_rv) { 2555 case PFIL_DROPPED: 2556 case PFIL_CONSUMED: 2557 /* 2558 * The filter ate it. Everything is recycled. 2559 */ 2560 m = NULL; 2561 unload = 0; 2562 break; 2563 case PFIL_REALLOCED: 2564 /* 2565 * The filter copied it. Everything is recycled. 2566 */ 2567 m = pfil_mem2mbuf(payload); 2568 unload = 0; 2569 break; 2570 case PFIL_PASS: 2571 /* 2572 * Filter said it was OK, so receive like 2573 * normal 2574 */ 2575 fl->ifl_sds.ifsd_m[cidx] = NULL; 2576 break; 2577 default: 2578 MPASS(0); 2579 } 2580 } else { 2581 fl->ifl_sds.ifsd_m[cidx] = NULL; 2582 *pf_rv = PFIL_PASS; 2583 } 2584 2585 if (unload) 2586 bus_dmamap_unload(fl->ifl_buf_tag, map); 2587 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2588 if (__predict_false(fl->ifl_cidx == 0)) 2589 fl->ifl_gen = 0; 2590 bit_clear(fl->ifl_rx_bitmap, cidx); 2591 return (m); 2592 } 2593 2594 static struct mbuf * 2595 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2596 { 2597 struct mbuf *m, *mh, *mt; 2598 caddr_t cl; 2599 int *pf_rv_ptr, flags, i, padlen; 2600 bool consumed; 2601 2602 i = 0; 2603 mh = NULL; 2604 consumed = false; 2605 *pf_rv = PFIL_PASS; 2606 pf_rv_ptr = pf_rv; 2607 do { 2608 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2609 pf_rv_ptr, ri); 2610 2611 MPASS(*sd->ifsd_cl != NULL); 2612 2613 /* 2614 * Exclude zero-length frags & frags from 2615 * packets the filter has consumed or dropped 2616 */ 2617 if (ri->iri_frags[i].irf_len == 0 || consumed || 2618 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2619 if (mh == NULL) { 2620 /* everything saved here */ 2621 consumed = true; 2622 pf_rv_ptr = NULL; 2623 continue; 2624 } 2625 /* XXX we can save the cluster here, but not the mbuf */ 2626 m_init(m, M_NOWAIT, MT_DATA, 0); 2627 m_free(m); 2628 continue; 2629 } 2630 if (mh == NULL) { 2631 flags = M_PKTHDR|M_EXT; 2632 mh = mt = m; 2633 padlen = ri->iri_pad; 2634 } else { 2635 flags = M_EXT; 2636 mt->m_next = m; 2637 mt = m; 2638 /* assuming padding is only on the first fragment */ 2639 padlen = 0; 2640 } 2641 cl = *sd->ifsd_cl; 2642 *sd->ifsd_cl = NULL; 2643 2644 /* Can these two be made one ? */ 2645 m_init(m, M_NOWAIT, MT_DATA, flags); 2646 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2647 /* 2648 * These must follow m_init and m_cljset 2649 */ 2650 m->m_data += padlen; 2651 ri->iri_len -= padlen; 2652 m->m_len = ri->iri_frags[i].irf_len; 2653 } while (++i < ri->iri_nfrags); 2654 2655 return (mh); 2656 } 2657 2658 /* 2659 * Process one software descriptor 2660 */ 2661 static struct mbuf * 2662 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2663 { 2664 struct if_rxsd sd; 2665 struct mbuf *m; 2666 int pf_rv; 2667 2668 /* should I merge this back in now that the two paths are basically duplicated? */ 2669 if (ri->iri_nfrags == 1 && 2670 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2671 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2672 &pf_rv, ri); 2673 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2674 return (m); 2675 if (pf_rv == PFIL_PASS) { 2676 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2677 #ifndef __NO_STRICT_ALIGNMENT 2678 if (!IP_ALIGNED(m)) 2679 m->m_data += 2; 2680 #endif 2681 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2682 m->m_len = ri->iri_frags[0].irf_len; 2683 } 2684 } else { 2685 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2686 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2687 return (m); 2688 } 2689 m->m_pkthdr.len = ri->iri_len; 2690 m->m_pkthdr.rcvif = ri->iri_ifp; 2691 m->m_flags |= ri->iri_flags; 2692 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2693 m->m_pkthdr.flowid = ri->iri_flowid; 2694 M_HASHTYPE_SET(m, ri->iri_rsstype); 2695 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2696 m->m_pkthdr.csum_data = ri->iri_csum_data; 2697 return (m); 2698 } 2699 2700 #if defined(INET6) || defined(INET) 2701 static void 2702 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2703 { 2704 CURVNET_SET(lc->ifp->if_vnet); 2705 #if defined(INET6) 2706 *v6 = V_ip6_forwarding; 2707 #endif 2708 #if defined(INET) 2709 *v4 = V_ipforwarding; 2710 #endif 2711 CURVNET_RESTORE(); 2712 } 2713 2714 /* 2715 * Returns true if it's possible this packet could be LROed. 2716 * if it returns false, it is guaranteed that tcp_lro_rx() 2717 * would not return zero. 2718 */ 2719 static bool 2720 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2721 { 2722 struct ether_header *eh; 2723 2724 eh = mtod(m, struct ether_header *); 2725 switch (eh->ether_type) { 2726 #if defined(INET6) 2727 case htons(ETHERTYPE_IPV6): 2728 return (!v6_forwarding); 2729 #endif 2730 #if defined (INET) 2731 case htons(ETHERTYPE_IP): 2732 return (!v4_forwarding); 2733 #endif 2734 } 2735 2736 return false; 2737 } 2738 #else 2739 static void 2740 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2741 { 2742 } 2743 #endif 2744 2745 static bool 2746 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2747 { 2748 if_t ifp; 2749 if_ctx_t ctx = rxq->ifr_ctx; 2750 if_shared_ctx_t sctx = ctx->ifc_sctx; 2751 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2752 int avail, i; 2753 qidx_t *cidxp; 2754 struct if_rxd_info ri; 2755 int err, budget_left, rx_bytes, rx_pkts; 2756 iflib_fl_t fl; 2757 int lro_enabled; 2758 bool v4_forwarding, v6_forwarding, lro_possible; 2759 2760 /* 2761 * XXX early demux data packets so that if_input processing only handles 2762 * acks in interrupt context 2763 */ 2764 struct mbuf *m, *mh, *mt, *mf; 2765 2766 lro_possible = v4_forwarding = v6_forwarding = false; 2767 ifp = ctx->ifc_ifp; 2768 mh = mt = NULL; 2769 MPASS(budget > 0); 2770 rx_pkts = rx_bytes = 0; 2771 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2772 cidxp = &rxq->ifr_cq_cidx; 2773 else 2774 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2775 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2776 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2777 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2778 DBG_COUNTER_INC(rx_unavail); 2779 return (false); 2780 } 2781 2782 /* pfil needs the vnet to be set */ 2783 CURVNET_SET_QUIET(ifp->if_vnet); 2784 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2785 if (__predict_false(!CTX_ACTIVE(ctx))) { 2786 DBG_COUNTER_INC(rx_ctx_inactive); 2787 break; 2788 } 2789 /* 2790 * Reset client set fields to their default values 2791 */ 2792 rxd_info_zero(&ri); 2793 ri.iri_qsidx = rxq->ifr_id; 2794 ri.iri_cidx = *cidxp; 2795 ri.iri_ifp = ifp; 2796 ri.iri_frags = rxq->ifr_frags; 2797 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2798 2799 if (err) 2800 goto err; 2801 rx_pkts += 1; 2802 rx_bytes += ri.iri_len; 2803 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2804 *cidxp = ri.iri_cidx; 2805 /* Update our consumer index */ 2806 /* XXX NB: shurd - check if this is still safe */ 2807 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2808 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2809 /* was this only a completion queue message? */ 2810 if (__predict_false(ri.iri_nfrags == 0)) 2811 continue; 2812 } 2813 MPASS(ri.iri_nfrags != 0); 2814 MPASS(ri.iri_len != 0); 2815 2816 /* will advance the cidx on the corresponding free lists */ 2817 m = iflib_rxd_pkt_get(rxq, &ri); 2818 avail--; 2819 budget_left--; 2820 if (avail == 0 && budget_left) 2821 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2822 2823 if (__predict_false(m == NULL)) 2824 continue; 2825 2826 /* imm_pkt: -- cxgb */ 2827 if (mh == NULL) 2828 mh = mt = m; 2829 else { 2830 mt->m_nextpkt = m; 2831 mt = m; 2832 } 2833 } 2834 CURVNET_RESTORE(); 2835 /* make sure that we can refill faster than drain */ 2836 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2837 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2838 2839 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2840 if (lro_enabled) 2841 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2842 mt = mf = NULL; 2843 while (mh != NULL) { 2844 m = mh; 2845 mh = mh->m_nextpkt; 2846 m->m_nextpkt = NULL; 2847 #ifndef __NO_STRICT_ALIGNMENT 2848 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2849 continue; 2850 #endif 2851 rx_bytes += m->m_pkthdr.len; 2852 rx_pkts++; 2853 #if defined(INET6) || defined(INET) 2854 if (lro_enabled) { 2855 if (!lro_possible) { 2856 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2857 if (lro_possible && mf != NULL) { 2858 ifp->if_input(ifp, mf); 2859 DBG_COUNTER_INC(rx_if_input); 2860 mt = mf = NULL; 2861 } 2862 } 2863 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2864 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2865 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2866 continue; 2867 } 2868 } 2869 #endif 2870 if (lro_possible) { 2871 ifp->if_input(ifp, m); 2872 DBG_COUNTER_INC(rx_if_input); 2873 continue; 2874 } 2875 2876 if (mf == NULL) 2877 mf = m; 2878 if (mt != NULL) 2879 mt->m_nextpkt = m; 2880 mt = m; 2881 } 2882 if (mf != NULL) { 2883 ifp->if_input(ifp, mf); 2884 DBG_COUNTER_INC(rx_if_input); 2885 } 2886 2887 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2888 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2889 2890 /* 2891 * Flush any outstanding LRO work 2892 */ 2893 #if defined(INET6) || defined(INET) 2894 tcp_lro_flush_all(&rxq->ifr_lc); 2895 #endif 2896 if (avail) 2897 return true; 2898 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2899 err: 2900 STATE_LOCK(ctx); 2901 ctx->ifc_flags |= IFC_DO_RESET; 2902 iflib_admin_intr_deferred(ctx); 2903 STATE_UNLOCK(ctx); 2904 return (false); 2905 } 2906 2907 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2908 static inline qidx_t 2909 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2910 { 2911 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2912 qidx_t minthresh = txq->ift_size / 8; 2913 if (in_use > 4*minthresh) 2914 return (notify_count); 2915 if (in_use > 2*minthresh) 2916 return (notify_count >> 1); 2917 if (in_use > minthresh) 2918 return (notify_count >> 3); 2919 return (0); 2920 } 2921 2922 static inline qidx_t 2923 txq_max_rs_deferred(iflib_txq_t txq) 2924 { 2925 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2926 qidx_t minthresh = txq->ift_size / 8; 2927 if (txq->ift_in_use > 4*minthresh) 2928 return (notify_count); 2929 if (txq->ift_in_use > 2*minthresh) 2930 return (notify_count >> 1); 2931 if (txq->ift_in_use > minthresh) 2932 return (notify_count >> 2); 2933 return (2); 2934 } 2935 2936 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2937 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2938 2939 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2940 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2941 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2942 2943 /* forward compatibility for cxgb */ 2944 #define FIRST_QSET(ctx) 0 2945 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2946 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2947 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2948 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2949 2950 /* XXX we should be setting this to something other than zero */ 2951 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2952 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2953 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2954 2955 static inline bool 2956 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2957 { 2958 qidx_t dbval, max; 2959 bool rang; 2960 2961 rang = false; 2962 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2963 if (ring || txq->ift_db_pending >= max) { 2964 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2965 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 2966 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2967 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2968 txq->ift_db_pending = txq->ift_npending = 0; 2969 rang = true; 2970 } 2971 return (rang); 2972 } 2973 2974 #ifdef PKT_DEBUG 2975 static void 2976 print_pkt(if_pkt_info_t pi) 2977 { 2978 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2979 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2980 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2981 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2982 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2983 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2984 } 2985 #endif 2986 2987 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2988 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2989 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2990 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2991 2992 static int 2993 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2994 { 2995 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2996 struct ether_vlan_header *eh; 2997 struct mbuf *m; 2998 2999 m = *mp; 3000 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3001 M_WRITABLE(m) == 0) { 3002 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3003 return (ENOMEM); 3004 } else { 3005 m_freem(*mp); 3006 DBG_COUNTER_INC(tx_frees); 3007 *mp = m; 3008 } 3009 } 3010 3011 /* 3012 * Determine where frame payload starts. 3013 * Jump over vlan headers if already present, 3014 * helpful for QinQ too. 3015 */ 3016 if (__predict_false(m->m_len < sizeof(*eh))) { 3017 txq->ift_pullups++; 3018 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3019 return (ENOMEM); 3020 } 3021 eh = mtod(m, struct ether_vlan_header *); 3022 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3023 pi->ipi_etype = ntohs(eh->evl_proto); 3024 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3025 } else { 3026 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3027 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3028 } 3029 3030 switch (pi->ipi_etype) { 3031 #ifdef INET 3032 case ETHERTYPE_IP: 3033 { 3034 struct mbuf *n; 3035 struct ip *ip = NULL; 3036 struct tcphdr *th = NULL; 3037 int minthlen; 3038 3039 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3040 if (__predict_false(m->m_len < minthlen)) { 3041 /* 3042 * if this code bloat is causing too much of a hit 3043 * move it to a separate function and mark it noinline 3044 */ 3045 if (m->m_len == pi->ipi_ehdrlen) { 3046 n = m->m_next; 3047 MPASS(n); 3048 if (n->m_len >= sizeof(*ip)) { 3049 ip = (struct ip *)n->m_data; 3050 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3051 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3052 } else { 3053 txq->ift_pullups++; 3054 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3055 return (ENOMEM); 3056 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3057 } 3058 } else { 3059 txq->ift_pullups++; 3060 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3061 return (ENOMEM); 3062 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3063 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3064 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3065 } 3066 } else { 3067 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3068 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3069 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3070 } 3071 pi->ipi_ip_hlen = ip->ip_hl << 2; 3072 pi->ipi_ipproto = ip->ip_p; 3073 pi->ipi_flags |= IPI_TX_IPV4; 3074 3075 /* TCP checksum offload may require TCP header length */ 3076 if (IS_TX_OFFLOAD4(pi)) { 3077 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3078 if (__predict_false(th == NULL)) { 3079 txq->ift_pullups++; 3080 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3081 return (ENOMEM); 3082 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3083 } 3084 pi->ipi_tcp_hflags = th->th_flags; 3085 pi->ipi_tcp_hlen = th->th_off << 2; 3086 pi->ipi_tcp_seq = th->th_seq; 3087 } 3088 if (IS_TSO4(pi)) { 3089 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3090 return (ENXIO); 3091 /* 3092 * TSO always requires hardware checksum offload. 3093 */ 3094 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3095 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3096 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3097 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3098 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3099 ip->ip_sum = 0; 3100 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3101 } 3102 } 3103 } 3104 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3105 ip->ip_sum = 0; 3106 3107 break; 3108 } 3109 #endif 3110 #ifdef INET6 3111 case ETHERTYPE_IPV6: 3112 { 3113 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3114 struct tcphdr *th; 3115 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3116 3117 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3118 txq->ift_pullups++; 3119 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3120 return (ENOMEM); 3121 } 3122 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3123 3124 /* XXX-BZ this will go badly in case of ext hdrs. */ 3125 pi->ipi_ipproto = ip6->ip6_nxt; 3126 pi->ipi_flags |= IPI_TX_IPV6; 3127 3128 /* TCP checksum offload may require TCP header length */ 3129 if (IS_TX_OFFLOAD6(pi)) { 3130 if (pi->ipi_ipproto == IPPROTO_TCP) { 3131 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3132 txq->ift_pullups++; 3133 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3134 return (ENOMEM); 3135 } 3136 pi->ipi_tcp_hflags = th->th_flags; 3137 pi->ipi_tcp_hlen = th->th_off << 2; 3138 pi->ipi_tcp_seq = th->th_seq; 3139 } 3140 if (IS_TSO6(pi)) { 3141 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3142 return (ENXIO); 3143 /* 3144 * TSO always requires hardware checksum offload. 3145 */ 3146 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3147 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3148 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3149 } 3150 } 3151 break; 3152 } 3153 #endif 3154 default: 3155 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3156 pi->ipi_ip_hlen = 0; 3157 break; 3158 } 3159 *mp = m; 3160 3161 return (0); 3162 } 3163 3164 /* 3165 * If dodgy hardware rejects the scatter gather chain we've handed it 3166 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3167 * m_defrag'd mbufs 3168 */ 3169 static __noinline struct mbuf * 3170 iflib_remove_mbuf(iflib_txq_t txq) 3171 { 3172 int ntxd, pidx; 3173 struct mbuf *m, **ifsd_m; 3174 3175 ifsd_m = txq->ift_sds.ifsd_m; 3176 ntxd = txq->ift_size; 3177 pidx = txq->ift_pidx & (ntxd - 1); 3178 ifsd_m = txq->ift_sds.ifsd_m; 3179 m = ifsd_m[pidx]; 3180 ifsd_m[pidx] = NULL; 3181 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3182 if (txq->ift_sds.ifsd_tso_map != NULL) 3183 bus_dmamap_unload(txq->ift_tso_buf_tag, 3184 txq->ift_sds.ifsd_tso_map[pidx]); 3185 #if MEMORY_LOGGING 3186 txq->ift_dequeued++; 3187 #endif 3188 return (m); 3189 } 3190 3191 static inline caddr_t 3192 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3193 { 3194 qidx_t size; 3195 int ntxd; 3196 caddr_t start, end, cur, next; 3197 3198 ntxd = txq->ift_size; 3199 size = txq->ift_txd_size[qid]; 3200 start = txq->ift_ifdi[qid].idi_vaddr; 3201 3202 if (__predict_false(size == 0)) 3203 return (start); 3204 cur = start + size*cidx; 3205 end = start + size*ntxd; 3206 next = CACHE_PTR_NEXT(cur); 3207 return (next < end ? next : start); 3208 } 3209 3210 /* 3211 * Pad an mbuf to ensure a minimum ethernet frame size. 3212 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3213 */ 3214 static __noinline int 3215 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3216 { 3217 /* 3218 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3219 * and ARP message is the smallest common payload I can think of 3220 */ 3221 static char pad[18]; /* just zeros */ 3222 int n; 3223 struct mbuf *new_head; 3224 3225 if (!M_WRITABLE(*m_head)) { 3226 new_head = m_dup(*m_head, M_NOWAIT); 3227 if (new_head == NULL) { 3228 m_freem(*m_head); 3229 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3230 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3231 DBG_COUNTER_INC(tx_frees); 3232 return ENOMEM; 3233 } 3234 m_freem(*m_head); 3235 *m_head = new_head; 3236 } 3237 3238 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3239 n > 0; n -= sizeof(pad)) 3240 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3241 break; 3242 3243 if (n > 0) { 3244 m_freem(*m_head); 3245 device_printf(dev, "cannot pad short frame\n"); 3246 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3247 DBG_COUNTER_INC(tx_frees); 3248 return (ENOBUFS); 3249 } 3250 3251 return 0; 3252 } 3253 3254 static int 3255 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3256 { 3257 if_ctx_t ctx; 3258 if_shared_ctx_t sctx; 3259 if_softc_ctx_t scctx; 3260 bus_dma_tag_t buf_tag; 3261 bus_dma_segment_t *segs; 3262 struct mbuf *m_head, **ifsd_m; 3263 void *next_txd; 3264 bus_dmamap_t map; 3265 struct if_pkt_info pi; 3266 int remap = 0; 3267 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3268 3269 ctx = txq->ift_ctx; 3270 sctx = ctx->ifc_sctx; 3271 scctx = &ctx->ifc_softc_ctx; 3272 segs = txq->ift_segs; 3273 ntxd = txq->ift_size; 3274 m_head = *m_headp; 3275 map = NULL; 3276 3277 /* 3278 * If we're doing TSO the next descriptor to clean may be quite far ahead 3279 */ 3280 cidx = txq->ift_cidx; 3281 pidx = txq->ift_pidx; 3282 if (ctx->ifc_flags & IFC_PREFETCH) { 3283 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3284 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3285 next_txd = calc_next_txd(txq, cidx, 0); 3286 prefetch(next_txd); 3287 } 3288 3289 /* prefetch the next cache line of mbuf pointers and flags */ 3290 prefetch(&txq->ift_sds.ifsd_m[next]); 3291 prefetch(&txq->ift_sds.ifsd_map[next]); 3292 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3293 } 3294 map = txq->ift_sds.ifsd_map[pidx]; 3295 ifsd_m = txq->ift_sds.ifsd_m; 3296 3297 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3298 buf_tag = txq->ift_tso_buf_tag; 3299 max_segs = scctx->isc_tx_tso_segments_max; 3300 map = txq->ift_sds.ifsd_tso_map[pidx]; 3301 MPASS(buf_tag != NULL); 3302 MPASS(max_segs > 0); 3303 } else { 3304 buf_tag = txq->ift_buf_tag; 3305 max_segs = scctx->isc_tx_nsegments; 3306 map = txq->ift_sds.ifsd_map[pidx]; 3307 } 3308 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3309 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3310 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3311 if (err) { 3312 DBG_COUNTER_INC(encap_txd_encap_fail); 3313 return err; 3314 } 3315 } 3316 m_head = *m_headp; 3317 3318 pkt_info_zero(&pi); 3319 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3320 pi.ipi_pidx = pidx; 3321 pi.ipi_qsidx = txq->ift_id; 3322 pi.ipi_len = m_head->m_pkthdr.len; 3323 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3324 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3325 3326 /* deliberate bitwise OR to make one condition */ 3327 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3328 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3329 DBG_COUNTER_INC(encap_txd_encap_fail); 3330 return (err); 3331 } 3332 m_head = *m_headp; 3333 } 3334 3335 retry: 3336 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3337 BUS_DMA_NOWAIT); 3338 defrag: 3339 if (__predict_false(err)) { 3340 switch (err) { 3341 case EFBIG: 3342 /* try collapse once and defrag once */ 3343 if (remap == 0) { 3344 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3345 /* try defrag if collapsing fails */ 3346 if (m_head == NULL) 3347 remap++; 3348 } 3349 if (remap == 1) { 3350 txq->ift_mbuf_defrag++; 3351 m_head = m_defrag(*m_headp, M_NOWAIT); 3352 } 3353 /* 3354 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3355 * failed to map an mbuf that was run through m_defrag 3356 */ 3357 MPASS(remap <= 1); 3358 if (__predict_false(m_head == NULL || remap > 1)) 3359 goto defrag_failed; 3360 remap++; 3361 *m_headp = m_head; 3362 goto retry; 3363 break; 3364 case ENOMEM: 3365 txq->ift_no_tx_dma_setup++; 3366 break; 3367 default: 3368 txq->ift_no_tx_dma_setup++; 3369 m_freem(*m_headp); 3370 DBG_COUNTER_INC(tx_frees); 3371 *m_headp = NULL; 3372 break; 3373 } 3374 txq->ift_map_failed++; 3375 DBG_COUNTER_INC(encap_load_mbuf_fail); 3376 DBG_COUNTER_INC(encap_txd_encap_fail); 3377 return (err); 3378 } 3379 ifsd_m[pidx] = m_head; 3380 /* 3381 * XXX assumes a 1 to 1 relationship between segments and 3382 * descriptors - this does not hold true on all drivers, e.g. 3383 * cxgb 3384 */ 3385 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3386 txq->ift_no_desc_avail++; 3387 bus_dmamap_unload(buf_tag, map); 3388 DBG_COUNTER_INC(encap_txq_avail_fail); 3389 DBG_COUNTER_INC(encap_txd_encap_fail); 3390 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3391 GROUPTASK_ENQUEUE(&txq->ift_task); 3392 return (ENOBUFS); 3393 } 3394 /* 3395 * On Intel cards we can greatly reduce the number of TX interrupts 3396 * we see by only setting report status on every Nth descriptor. 3397 * However, this also means that the driver will need to keep track 3398 * of the descriptors that RS was set on to check them for the DD bit. 3399 */ 3400 txq->ift_rs_pending += nsegs + 1; 3401 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3402 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3403 pi.ipi_flags |= IPI_TX_INTR; 3404 txq->ift_rs_pending = 0; 3405 } 3406 3407 pi.ipi_segs = segs; 3408 pi.ipi_nsegs = nsegs; 3409 3410 MPASS(pidx >= 0 && pidx < txq->ift_size); 3411 #ifdef PKT_DEBUG 3412 print_pkt(&pi); 3413 #endif 3414 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3415 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3416 DBG_COUNTER_INC(tx_encap); 3417 MPASS(pi.ipi_new_pidx < txq->ift_size); 3418 3419 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3420 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3421 ndesc += txq->ift_size; 3422 txq->ift_gen = 1; 3423 } 3424 /* 3425 * drivers can need as many as 3426 * two sentinels 3427 */ 3428 MPASS(ndesc <= pi.ipi_nsegs + 2); 3429 MPASS(pi.ipi_new_pidx != pidx); 3430 MPASS(ndesc > 0); 3431 txq->ift_in_use += ndesc; 3432 3433 /* 3434 * We update the last software descriptor again here because there may 3435 * be a sentinel and/or there may be more mbufs than segments 3436 */ 3437 txq->ift_pidx = pi.ipi_new_pidx; 3438 txq->ift_npending += pi.ipi_ndescs; 3439 } else { 3440 *m_headp = m_head = iflib_remove_mbuf(txq); 3441 if (err == EFBIG) { 3442 txq->ift_txd_encap_efbig++; 3443 if (remap < 2) { 3444 remap = 1; 3445 goto defrag; 3446 } 3447 } 3448 goto defrag_failed; 3449 } 3450 /* 3451 * err can't possibly be non-zero here, so we don't neet to test it 3452 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3453 */ 3454 return (err); 3455 3456 defrag_failed: 3457 txq->ift_mbuf_defrag_failed++; 3458 txq->ift_map_failed++; 3459 m_freem(*m_headp); 3460 DBG_COUNTER_INC(tx_frees); 3461 *m_headp = NULL; 3462 DBG_COUNTER_INC(encap_txd_encap_fail); 3463 return (ENOMEM); 3464 } 3465 3466 static void 3467 iflib_tx_desc_free(iflib_txq_t txq, int n) 3468 { 3469 uint32_t qsize, cidx, mask, gen; 3470 struct mbuf *m, **ifsd_m; 3471 bool do_prefetch; 3472 3473 cidx = txq->ift_cidx; 3474 gen = txq->ift_gen; 3475 qsize = txq->ift_size; 3476 mask = qsize-1; 3477 ifsd_m = txq->ift_sds.ifsd_m; 3478 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3479 3480 while (n-- > 0) { 3481 if (do_prefetch) { 3482 prefetch(ifsd_m[(cidx + 3) & mask]); 3483 prefetch(ifsd_m[(cidx + 4) & mask]); 3484 } 3485 if ((m = ifsd_m[cidx]) != NULL) { 3486 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3487 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3488 bus_dmamap_sync(txq->ift_tso_buf_tag, 3489 txq->ift_sds.ifsd_tso_map[cidx], 3490 BUS_DMASYNC_POSTWRITE); 3491 bus_dmamap_unload(txq->ift_tso_buf_tag, 3492 txq->ift_sds.ifsd_tso_map[cidx]); 3493 } else { 3494 bus_dmamap_sync(txq->ift_buf_tag, 3495 txq->ift_sds.ifsd_map[cidx], 3496 BUS_DMASYNC_POSTWRITE); 3497 bus_dmamap_unload(txq->ift_buf_tag, 3498 txq->ift_sds.ifsd_map[cidx]); 3499 } 3500 /* XXX we don't support any drivers that batch packets yet */ 3501 MPASS(m->m_nextpkt == NULL); 3502 m_freem(m); 3503 ifsd_m[cidx] = NULL; 3504 #if MEMORY_LOGGING 3505 txq->ift_dequeued++; 3506 #endif 3507 DBG_COUNTER_INC(tx_frees); 3508 } 3509 if (__predict_false(++cidx == qsize)) { 3510 cidx = 0; 3511 gen = 0; 3512 } 3513 } 3514 txq->ift_cidx = cidx; 3515 txq->ift_gen = gen; 3516 } 3517 3518 static __inline int 3519 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3520 { 3521 int reclaim; 3522 if_ctx_t ctx = txq->ift_ctx; 3523 3524 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3525 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3526 3527 /* 3528 * Need a rate-limiting check so that this isn't called every time 3529 */ 3530 iflib_tx_credits_update(ctx, txq); 3531 reclaim = DESC_RECLAIMABLE(txq); 3532 3533 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3534 #ifdef INVARIANTS 3535 if (iflib_verbose_debug) { 3536 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3537 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3538 reclaim, thresh); 3539 3540 } 3541 #endif 3542 return (0); 3543 } 3544 iflib_tx_desc_free(txq, reclaim); 3545 txq->ift_cleaned += reclaim; 3546 txq->ift_in_use -= reclaim; 3547 3548 return (reclaim); 3549 } 3550 3551 static struct mbuf ** 3552 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3553 { 3554 int next, size; 3555 struct mbuf **items; 3556 3557 size = r->size; 3558 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3559 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3560 3561 prefetch(items[(cidx + offset) & (size-1)]); 3562 if (remaining > 1) { 3563 prefetch2cachelines(&items[next]); 3564 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3565 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3566 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3567 } 3568 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3569 } 3570 3571 static void 3572 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3573 { 3574 3575 ifmp_ring_check_drainage(txq->ift_br, budget); 3576 } 3577 3578 static uint32_t 3579 iflib_txq_can_drain(struct ifmp_ring *r) 3580 { 3581 iflib_txq_t txq = r->cookie; 3582 if_ctx_t ctx = txq->ift_ctx; 3583 3584 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3585 return (1); 3586 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3587 BUS_DMASYNC_POSTREAD); 3588 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3589 false)); 3590 } 3591 3592 static uint32_t 3593 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3594 { 3595 iflib_txq_t txq = r->cookie; 3596 if_ctx_t ctx = txq->ift_ctx; 3597 if_t ifp = ctx->ifc_ifp; 3598 struct mbuf *m, **mp; 3599 int avail, bytes_sent, consumed, count, err, i, in_use_prev; 3600 int mcast_sent, pkt_sent, reclaimed, txq_avail; 3601 bool do_prefetch, rang, ring; 3602 3603 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3604 !LINK_ACTIVE(ctx))) { 3605 DBG_COUNTER_INC(txq_drain_notready); 3606 return (0); 3607 } 3608 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3609 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3610 avail = IDXDIFF(pidx, cidx, r->size); 3611 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3612 DBG_COUNTER_INC(txq_drain_flushing); 3613 for (i = 0; i < avail; i++) { 3614 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3615 m_free(r->items[(cidx + i) & (r->size-1)]); 3616 r->items[(cidx + i) & (r->size-1)] = NULL; 3617 } 3618 return (avail); 3619 } 3620 3621 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3622 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3623 CALLOUT_LOCK(txq); 3624 callout_stop(&txq->ift_timer); 3625 CALLOUT_UNLOCK(txq); 3626 DBG_COUNTER_INC(txq_drain_oactive); 3627 return (0); 3628 } 3629 if (reclaimed) 3630 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3631 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3632 count = MIN(avail, TX_BATCH_SIZE); 3633 #ifdef INVARIANTS 3634 if (iflib_verbose_debug) 3635 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3636 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3637 #endif 3638 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3639 txq_avail = TXQ_AVAIL(txq); 3640 err = 0; 3641 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) { 3642 int rem = do_prefetch ? count - i : 0; 3643 3644 mp = _ring_peek_one(r, cidx, i, rem); 3645 MPASS(mp != NULL && *mp != NULL); 3646 if (__predict_false(*mp == (struct mbuf *)txq)) { 3647 consumed++; 3648 continue; 3649 } 3650 in_use_prev = txq->ift_in_use; 3651 err = iflib_encap(txq, mp); 3652 if (__predict_false(err)) { 3653 /* no room - bail out */ 3654 if (err == ENOBUFS) 3655 break; 3656 consumed++; 3657 /* we can't send this packet - skip it */ 3658 continue; 3659 } 3660 consumed++; 3661 pkt_sent++; 3662 m = *mp; 3663 DBG_COUNTER_INC(tx_sent); 3664 bytes_sent += m->m_pkthdr.len; 3665 mcast_sent += !!(m->m_flags & M_MCAST); 3666 txq_avail = TXQ_AVAIL(txq); 3667 3668 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3669 ETHER_BPF_MTAP(ifp, m); 3670 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3671 break; 3672 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3673 } 3674 3675 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3676 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3677 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3678 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3679 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3680 if (mcast_sent) 3681 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3682 #ifdef INVARIANTS 3683 if (iflib_verbose_debug) 3684 printf("consumed=%d\n", consumed); 3685 #endif 3686 return (consumed); 3687 } 3688 3689 static uint32_t 3690 iflib_txq_drain_always(struct ifmp_ring *r) 3691 { 3692 return (1); 3693 } 3694 3695 static uint32_t 3696 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3697 { 3698 int i, avail; 3699 struct mbuf **mp; 3700 iflib_txq_t txq; 3701 3702 txq = r->cookie; 3703 3704 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3705 CALLOUT_LOCK(txq); 3706 callout_stop(&txq->ift_timer); 3707 CALLOUT_UNLOCK(txq); 3708 3709 avail = IDXDIFF(pidx, cidx, r->size); 3710 for (i = 0; i < avail; i++) { 3711 mp = _ring_peek_one(r, cidx, i, avail - i); 3712 if (__predict_false(*mp == (struct mbuf *)txq)) 3713 continue; 3714 m_freem(*mp); 3715 DBG_COUNTER_INC(tx_frees); 3716 } 3717 MPASS(ifmp_ring_is_stalled(r) == 0); 3718 return (avail); 3719 } 3720 3721 static void 3722 iflib_ifmp_purge(iflib_txq_t txq) 3723 { 3724 struct ifmp_ring *r; 3725 3726 r = txq->ift_br; 3727 r->drain = iflib_txq_drain_free; 3728 r->can_drain = iflib_txq_drain_always; 3729 3730 ifmp_ring_check_drainage(r, r->size); 3731 3732 r->drain = iflib_txq_drain; 3733 r->can_drain = iflib_txq_can_drain; 3734 } 3735 3736 static void 3737 _task_fn_tx(void *context) 3738 { 3739 iflib_txq_t txq = context; 3740 if_ctx_t ctx = txq->ift_ctx; 3741 #if defined(ALTQ) || defined(DEV_NETMAP) 3742 if_t ifp = ctx->ifc_ifp; 3743 #endif 3744 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3745 3746 #ifdef IFLIB_DIAGNOSTICS 3747 txq->ift_cpu_exec_count[curcpu]++; 3748 #endif 3749 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3750 return; 3751 #ifdef DEV_NETMAP 3752 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3753 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3754 BUS_DMASYNC_POSTREAD); 3755 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3756 netmap_tx_irq(ifp, txq->ift_id); 3757 if (ctx->ifc_flags & IFC_LEGACY) 3758 IFDI_INTR_ENABLE(ctx); 3759 else 3760 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3761 return; 3762 } 3763 #endif 3764 #ifdef ALTQ 3765 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3766 iflib_altq_if_start(ifp); 3767 #endif 3768 if (txq->ift_db_pending) 3769 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3770 else if (!abdicate) 3771 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3772 /* 3773 * When abdicating, we always need to check drainage, not just when we don't enqueue 3774 */ 3775 if (abdicate) 3776 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3777 if (ctx->ifc_flags & IFC_LEGACY) 3778 IFDI_INTR_ENABLE(ctx); 3779 else 3780 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3781 } 3782 3783 static void 3784 _task_fn_rx(void *context) 3785 { 3786 iflib_rxq_t rxq = context; 3787 if_ctx_t ctx = rxq->ifr_ctx; 3788 bool more; 3789 uint16_t budget; 3790 3791 #ifdef IFLIB_DIAGNOSTICS 3792 rxq->ifr_cpu_exec_count[curcpu]++; 3793 #endif 3794 DBG_COUNTER_INC(task_fn_rxs); 3795 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3796 return; 3797 more = true; 3798 #ifdef DEV_NETMAP 3799 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3800 u_int work = 0; 3801 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3802 more = false; 3803 } 3804 } 3805 #endif 3806 budget = ctx->ifc_sysctl_rx_budget; 3807 if (budget == 0) 3808 budget = 16; /* XXX */ 3809 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3810 if (ctx->ifc_flags & IFC_LEGACY) 3811 IFDI_INTR_ENABLE(ctx); 3812 else 3813 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3814 DBG_COUNTER_INC(rx_intr_enables); 3815 } 3816 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3817 return; 3818 if (more) 3819 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3820 } 3821 3822 static void 3823 _task_fn_admin(void *context) 3824 { 3825 if_ctx_t ctx = context; 3826 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3827 iflib_txq_t txq; 3828 int i; 3829 bool oactive, running, do_reset, do_watchdog, in_detach; 3830 uint32_t reset_on = hz / 2; 3831 3832 STATE_LOCK(ctx); 3833 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3834 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3835 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3836 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3837 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3838 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3839 STATE_UNLOCK(ctx); 3840 3841 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3842 return; 3843 if (in_detach) 3844 return; 3845 3846 CTX_LOCK(ctx); 3847 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3848 CALLOUT_LOCK(txq); 3849 callout_stop(&txq->ift_timer); 3850 CALLOUT_UNLOCK(txq); 3851 } 3852 if (do_watchdog) { 3853 ctx->ifc_watchdog_events++; 3854 IFDI_WATCHDOG_RESET(ctx); 3855 } 3856 IFDI_UPDATE_ADMIN_STATUS(ctx); 3857 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3858 #ifdef DEV_NETMAP 3859 reset_on = hz / 2; 3860 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3861 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 3862 #endif 3863 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3864 } 3865 IFDI_LINK_INTR_ENABLE(ctx); 3866 if (do_reset) 3867 iflib_if_init_locked(ctx); 3868 CTX_UNLOCK(ctx); 3869 3870 if (LINK_ACTIVE(ctx) == 0) 3871 return; 3872 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3873 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3874 } 3875 3876 3877 static void 3878 _task_fn_iov(void *context) 3879 { 3880 if_ctx_t ctx = context; 3881 3882 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3883 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3884 return; 3885 3886 CTX_LOCK(ctx); 3887 IFDI_VFLR_HANDLE(ctx); 3888 CTX_UNLOCK(ctx); 3889 } 3890 3891 static int 3892 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3893 { 3894 int err; 3895 if_int_delay_info_t info; 3896 if_ctx_t ctx; 3897 3898 info = (if_int_delay_info_t)arg1; 3899 ctx = info->iidi_ctx; 3900 info->iidi_req = req; 3901 info->iidi_oidp = oidp; 3902 CTX_LOCK(ctx); 3903 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3904 CTX_UNLOCK(ctx); 3905 return (err); 3906 } 3907 3908 /********************************************************************* 3909 * 3910 * IFNET FUNCTIONS 3911 * 3912 **********************************************************************/ 3913 3914 static void 3915 iflib_if_init_locked(if_ctx_t ctx) 3916 { 3917 iflib_stop(ctx); 3918 iflib_init_locked(ctx); 3919 } 3920 3921 3922 static void 3923 iflib_if_init(void *arg) 3924 { 3925 if_ctx_t ctx = arg; 3926 3927 CTX_LOCK(ctx); 3928 iflib_if_init_locked(ctx); 3929 CTX_UNLOCK(ctx); 3930 } 3931 3932 static int 3933 iflib_if_transmit(if_t ifp, struct mbuf *m) 3934 { 3935 if_ctx_t ctx = if_getsoftc(ifp); 3936 3937 iflib_txq_t txq; 3938 int err, qidx; 3939 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3940 3941 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3942 DBG_COUNTER_INC(tx_frees); 3943 m_freem(m); 3944 return (ENETDOWN); 3945 } 3946 3947 MPASS(m->m_nextpkt == NULL); 3948 /* ALTQ-enabled interfaces always use queue 0. */ 3949 qidx = 0; 3950 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3951 qidx = QIDX(ctx, m); 3952 /* 3953 * XXX calculate buf_ring based on flowid (divvy up bits?) 3954 */ 3955 txq = &ctx->ifc_txqs[qidx]; 3956 3957 #ifdef DRIVER_BACKPRESSURE 3958 if (txq->ift_closed) { 3959 while (m != NULL) { 3960 next = m->m_nextpkt; 3961 m->m_nextpkt = NULL; 3962 m_freem(m); 3963 DBG_COUNTER_INC(tx_frees); 3964 m = next; 3965 } 3966 return (ENOBUFS); 3967 } 3968 #endif 3969 #ifdef notyet 3970 qidx = count = 0; 3971 mp = marr; 3972 next = m; 3973 do { 3974 count++; 3975 next = next->m_nextpkt; 3976 } while (next != NULL); 3977 3978 if (count > nitems(marr)) 3979 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3980 /* XXX check nextpkt */ 3981 m_freem(m); 3982 /* XXX simplify for now */ 3983 DBG_COUNTER_INC(tx_frees); 3984 return (ENOBUFS); 3985 } 3986 for (next = m, i = 0; next != NULL; i++) { 3987 mp[i] = next; 3988 next = next->m_nextpkt; 3989 mp[i]->m_nextpkt = NULL; 3990 } 3991 #endif 3992 DBG_COUNTER_INC(tx_seen); 3993 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 3994 3995 if (abdicate) 3996 GROUPTASK_ENQUEUE(&txq->ift_task); 3997 if (err) { 3998 if (!abdicate) 3999 GROUPTASK_ENQUEUE(&txq->ift_task); 4000 /* support forthcoming later */ 4001 #ifdef DRIVER_BACKPRESSURE 4002 txq->ift_closed = TRUE; 4003 #endif 4004 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4005 m_freem(m); 4006 DBG_COUNTER_INC(tx_frees); 4007 } 4008 4009 return (err); 4010 } 4011 4012 #ifdef ALTQ 4013 /* 4014 * The overall approach to integrating iflib with ALTQ is to continue to use 4015 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4016 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4017 * is redundant/unnecessary, but doing so minimizes the amount of 4018 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4019 * redundantly queueing to an intermediate mp_ring is swamped by the 4020 * performance limitations inherent in using ALTQ. 4021 * 4022 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4023 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4024 * given interface. If ALTQ is enabled for an interface, then all 4025 * transmitted packets for that interface will be submitted to the ALTQ 4026 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4027 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4028 * update stats that the iflib machinery handles, and which is sensitve to 4029 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4030 * will be installed as the start routine for use by ALTQ facilities that 4031 * need to trigger queue drains on a scheduled basis. 4032 * 4033 */ 4034 static void 4035 iflib_altq_if_start(if_t ifp) 4036 { 4037 struct ifaltq *ifq = &ifp->if_snd; 4038 struct mbuf *m; 4039 4040 IFQ_LOCK(ifq); 4041 IFQ_DEQUEUE_NOLOCK(ifq, m); 4042 while (m != NULL) { 4043 iflib_if_transmit(ifp, m); 4044 IFQ_DEQUEUE_NOLOCK(ifq, m); 4045 } 4046 IFQ_UNLOCK(ifq); 4047 } 4048 4049 static int 4050 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4051 { 4052 int err; 4053 4054 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4055 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4056 if (err == 0) 4057 iflib_altq_if_start(ifp); 4058 } else 4059 err = iflib_if_transmit(ifp, m); 4060 4061 return (err); 4062 } 4063 #endif /* ALTQ */ 4064 4065 static void 4066 iflib_if_qflush(if_t ifp) 4067 { 4068 if_ctx_t ctx = if_getsoftc(ifp); 4069 iflib_txq_t txq = ctx->ifc_txqs; 4070 int i; 4071 4072 STATE_LOCK(ctx); 4073 ctx->ifc_flags |= IFC_QFLUSH; 4074 STATE_UNLOCK(ctx); 4075 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4076 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4077 iflib_txq_check_drain(txq, 0); 4078 STATE_LOCK(ctx); 4079 ctx->ifc_flags &= ~IFC_QFLUSH; 4080 STATE_UNLOCK(ctx); 4081 4082 /* 4083 * When ALTQ is enabled, this will also take care of purging the 4084 * ALTQ queue(s). 4085 */ 4086 if_qflush(ifp); 4087 } 4088 4089 4090 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4091 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4092 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4093 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP) 4094 4095 static int 4096 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4097 { 4098 if_ctx_t ctx = if_getsoftc(ifp); 4099 struct ifreq *ifr = (struct ifreq *)data; 4100 #if defined(INET) || defined(INET6) 4101 struct ifaddr *ifa = (struct ifaddr *)data; 4102 #endif 4103 bool avoid_reset = false; 4104 int err = 0, reinit = 0, bits; 4105 4106 switch (command) { 4107 case SIOCSIFADDR: 4108 #ifdef INET 4109 if (ifa->ifa_addr->sa_family == AF_INET) 4110 avoid_reset = true; 4111 #endif 4112 #ifdef INET6 4113 if (ifa->ifa_addr->sa_family == AF_INET6) 4114 avoid_reset = true; 4115 #endif 4116 /* 4117 ** Calling init results in link renegotiation, 4118 ** so we avoid doing it when possible. 4119 */ 4120 if (avoid_reset) { 4121 if_setflagbits(ifp, IFF_UP,0); 4122 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4123 reinit = 1; 4124 #ifdef INET 4125 if (!(if_getflags(ifp) & IFF_NOARP)) 4126 arp_ifinit(ifp, ifa); 4127 #endif 4128 } else 4129 err = ether_ioctl(ifp, command, data); 4130 break; 4131 case SIOCSIFMTU: 4132 CTX_LOCK(ctx); 4133 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4134 CTX_UNLOCK(ctx); 4135 break; 4136 } 4137 bits = if_getdrvflags(ifp); 4138 /* stop the driver and free any clusters before proceeding */ 4139 iflib_stop(ctx); 4140 4141 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4142 STATE_LOCK(ctx); 4143 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4144 ctx->ifc_flags |= IFC_MULTISEG; 4145 else 4146 ctx->ifc_flags &= ~IFC_MULTISEG; 4147 STATE_UNLOCK(ctx); 4148 err = if_setmtu(ifp, ifr->ifr_mtu); 4149 } 4150 iflib_init_locked(ctx); 4151 STATE_LOCK(ctx); 4152 if_setdrvflags(ifp, bits); 4153 STATE_UNLOCK(ctx); 4154 CTX_UNLOCK(ctx); 4155 break; 4156 case SIOCSIFFLAGS: 4157 CTX_LOCK(ctx); 4158 if (if_getflags(ifp) & IFF_UP) { 4159 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4160 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4161 (IFF_PROMISC | IFF_ALLMULTI)) { 4162 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4163 } 4164 } else 4165 reinit = 1; 4166 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4167 iflib_stop(ctx); 4168 } 4169 ctx->ifc_if_flags = if_getflags(ifp); 4170 CTX_UNLOCK(ctx); 4171 break; 4172 case SIOCADDMULTI: 4173 case SIOCDELMULTI: 4174 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4175 CTX_LOCK(ctx); 4176 IFDI_INTR_DISABLE(ctx); 4177 IFDI_MULTI_SET(ctx); 4178 IFDI_INTR_ENABLE(ctx); 4179 CTX_UNLOCK(ctx); 4180 } 4181 break; 4182 case SIOCSIFMEDIA: 4183 CTX_LOCK(ctx); 4184 IFDI_MEDIA_SET(ctx); 4185 CTX_UNLOCK(ctx); 4186 /* FALLTHROUGH */ 4187 case SIOCGIFMEDIA: 4188 case SIOCGIFXMEDIA: 4189 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4190 break; 4191 case SIOCGI2C: 4192 { 4193 struct ifi2creq i2c; 4194 4195 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4196 if (err != 0) 4197 break; 4198 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4199 err = EINVAL; 4200 break; 4201 } 4202 if (i2c.len > sizeof(i2c.data)) { 4203 err = EINVAL; 4204 break; 4205 } 4206 4207 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4208 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4209 sizeof(i2c)); 4210 break; 4211 } 4212 case SIOCSIFCAP: 4213 { 4214 int mask, setmask, oldmask; 4215 4216 oldmask = if_getcapenable(ifp); 4217 mask = ifr->ifr_reqcap ^ oldmask; 4218 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP; 4219 setmask = 0; 4220 #ifdef TCP_OFFLOAD 4221 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4222 #endif 4223 setmask |= (mask & IFCAP_FLAGS); 4224 setmask |= (mask & IFCAP_WOL); 4225 4226 /* 4227 * If any RX csum has changed, change all the ones that 4228 * are supported by the driver. 4229 */ 4230 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4231 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4232 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4233 } 4234 4235 /* 4236 * want to ensure that traffic has stopped before we change any of the flags 4237 */ 4238 if (setmask) { 4239 CTX_LOCK(ctx); 4240 bits = if_getdrvflags(ifp); 4241 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4242 iflib_stop(ctx); 4243 STATE_LOCK(ctx); 4244 if_togglecapenable(ifp, setmask); 4245 STATE_UNLOCK(ctx); 4246 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4247 iflib_init_locked(ctx); 4248 STATE_LOCK(ctx); 4249 if_setdrvflags(ifp, bits); 4250 STATE_UNLOCK(ctx); 4251 CTX_UNLOCK(ctx); 4252 } 4253 if_vlancap(ifp); 4254 break; 4255 } 4256 case SIOCGPRIVATE_0: 4257 case SIOCSDRVSPEC: 4258 case SIOCGDRVSPEC: 4259 CTX_LOCK(ctx); 4260 err = IFDI_PRIV_IOCTL(ctx, command, data); 4261 CTX_UNLOCK(ctx); 4262 break; 4263 default: 4264 err = ether_ioctl(ifp, command, data); 4265 break; 4266 } 4267 if (reinit) 4268 iflib_if_init(ctx); 4269 return (err); 4270 } 4271 4272 static uint64_t 4273 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4274 { 4275 if_ctx_t ctx = if_getsoftc(ifp); 4276 4277 return (IFDI_GET_COUNTER(ctx, cnt)); 4278 } 4279 4280 /********************************************************************* 4281 * 4282 * OTHER FUNCTIONS EXPORTED TO THE STACK 4283 * 4284 **********************************************************************/ 4285 4286 static void 4287 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4288 { 4289 if_ctx_t ctx = if_getsoftc(ifp); 4290 4291 if ((void *)ctx != arg) 4292 return; 4293 4294 if ((vtag == 0) || (vtag > 4095)) 4295 return; 4296 4297 if (iflib_in_detach(ctx)) 4298 return; 4299 4300 CTX_LOCK(ctx); 4301 IFDI_VLAN_REGISTER(ctx, vtag); 4302 /* Re-init to load the changes */ 4303 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4304 iflib_if_init_locked(ctx); 4305 CTX_UNLOCK(ctx); 4306 } 4307 4308 static void 4309 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4310 { 4311 if_ctx_t ctx = if_getsoftc(ifp); 4312 4313 if ((void *)ctx != arg) 4314 return; 4315 4316 if ((vtag == 0) || (vtag > 4095)) 4317 return; 4318 4319 CTX_LOCK(ctx); 4320 IFDI_VLAN_UNREGISTER(ctx, vtag); 4321 /* Re-init to load the changes */ 4322 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4323 iflib_if_init_locked(ctx); 4324 CTX_UNLOCK(ctx); 4325 } 4326 4327 static void 4328 iflib_led_func(void *arg, int onoff) 4329 { 4330 if_ctx_t ctx = arg; 4331 4332 CTX_LOCK(ctx); 4333 IFDI_LED_FUNC(ctx, onoff); 4334 CTX_UNLOCK(ctx); 4335 } 4336 4337 /********************************************************************* 4338 * 4339 * BUS FUNCTION DEFINITIONS 4340 * 4341 **********************************************************************/ 4342 4343 int 4344 iflib_device_probe(device_t dev) 4345 { 4346 const pci_vendor_info_t *ent; 4347 if_shared_ctx_t sctx; 4348 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4349 uint16_t pci_vendor_id; 4350 4351 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4352 return (ENOTSUP); 4353 4354 pci_vendor_id = pci_get_vendor(dev); 4355 pci_device_id = pci_get_device(dev); 4356 pci_subvendor_id = pci_get_subvendor(dev); 4357 pci_subdevice_id = pci_get_subdevice(dev); 4358 pci_rev_id = pci_get_revid(dev); 4359 if (sctx->isc_parse_devinfo != NULL) 4360 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4361 4362 ent = sctx->isc_vendor_info; 4363 while (ent->pvi_vendor_id != 0) { 4364 if (pci_vendor_id != ent->pvi_vendor_id) { 4365 ent++; 4366 continue; 4367 } 4368 if ((pci_device_id == ent->pvi_device_id) && 4369 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4370 (ent->pvi_subvendor_id == 0)) && 4371 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4372 (ent->pvi_subdevice_id == 0)) && 4373 ((pci_rev_id == ent->pvi_rev_id) || 4374 (ent->pvi_rev_id == 0))) { 4375 4376 device_set_desc_copy(dev, ent->pvi_name); 4377 /* this needs to be changed to zero if the bus probing code 4378 * ever stops re-probing on best match because the sctx 4379 * may have its values over written by register calls 4380 * in subsequent probes 4381 */ 4382 return (BUS_PROBE_DEFAULT); 4383 } 4384 ent++; 4385 } 4386 return (ENXIO); 4387 } 4388 4389 int 4390 iflib_device_probe_vendor(device_t dev) 4391 { 4392 int probe; 4393 4394 probe = iflib_device_probe(dev); 4395 if (probe == BUS_PROBE_DEFAULT) 4396 return (BUS_PROBE_VENDOR); 4397 else 4398 return (probe); 4399 } 4400 4401 static void 4402 iflib_reset_qvalues(if_ctx_t ctx) 4403 { 4404 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4405 if_shared_ctx_t sctx = ctx->ifc_sctx; 4406 device_t dev = ctx->ifc_dev; 4407 int i; 4408 4409 if (ctx->ifc_sysctl_ntxqs != 0) 4410 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4411 if (ctx->ifc_sysctl_nrxqs != 0) 4412 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4413 4414 for (i = 0; i < sctx->isc_ntxqs; i++) { 4415 if (ctx->ifc_sysctl_ntxds[i] != 0) 4416 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4417 else 4418 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4419 } 4420 4421 for (i = 0; i < sctx->isc_nrxqs; i++) { 4422 if (ctx->ifc_sysctl_nrxds[i] != 0) 4423 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4424 else 4425 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4426 } 4427 4428 for (i = 0; i < sctx->isc_nrxqs; i++) { 4429 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4430 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4431 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4432 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4433 } 4434 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4435 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4436 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4437 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4438 } 4439 if (!powerof2(scctx->isc_nrxd[i])) { 4440 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4441 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4442 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4443 } 4444 } 4445 4446 for (i = 0; i < sctx->isc_ntxqs; i++) { 4447 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4448 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4449 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4450 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4451 } 4452 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4453 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4454 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4455 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4456 } 4457 if (!powerof2(scctx->isc_ntxd[i])) { 4458 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4459 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4460 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4461 } 4462 } 4463 } 4464 4465 static void 4466 iflib_add_pfil(if_ctx_t ctx) 4467 { 4468 struct pfil_head *pfil; 4469 struct pfil_head_args pa; 4470 iflib_rxq_t rxq; 4471 int i; 4472 4473 pa.pa_version = PFIL_VERSION; 4474 pa.pa_flags = PFIL_IN; 4475 pa.pa_type = PFIL_TYPE_ETHERNET; 4476 pa.pa_headname = ctx->ifc_ifp->if_xname; 4477 pfil = pfil_head_register(&pa); 4478 4479 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4480 rxq->pfil = pfil; 4481 } 4482 } 4483 4484 static void 4485 iflib_rem_pfil(if_ctx_t ctx) 4486 { 4487 struct pfil_head *pfil; 4488 iflib_rxq_t rxq; 4489 int i; 4490 4491 rxq = ctx->ifc_rxqs; 4492 pfil = rxq->pfil; 4493 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4494 rxq->pfil = NULL; 4495 } 4496 pfil_head_unregister(pfil); 4497 } 4498 4499 static uint16_t 4500 get_ctx_core_offset(if_ctx_t ctx) 4501 { 4502 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4503 struct cpu_offset *op; 4504 uint16_t qc; 4505 uint16_t ret = ctx->ifc_sysctl_core_offset; 4506 4507 if (ret != CORE_OFFSET_UNSPECIFIED) 4508 return (ret); 4509 4510 if (ctx->ifc_sysctl_separate_txrx) 4511 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets; 4512 else 4513 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets); 4514 4515 mtx_lock(&cpu_offset_mtx); 4516 SLIST_FOREACH(op, &cpu_offsets, entries) { 4517 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4518 ret = op->offset; 4519 op->offset += qc; 4520 MPASS(op->refcount < UINT_MAX); 4521 op->refcount++; 4522 break; 4523 } 4524 } 4525 if (ret == CORE_OFFSET_UNSPECIFIED) { 4526 ret = 0; 4527 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4528 M_NOWAIT | M_ZERO); 4529 if (op == NULL) { 4530 device_printf(ctx->ifc_dev, 4531 "allocation for cpu offset failed.\n"); 4532 } else { 4533 op->offset = qc; 4534 op->refcount = 1; 4535 CPU_COPY(&ctx->ifc_cpus, &op->set); 4536 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4537 } 4538 } 4539 mtx_unlock(&cpu_offset_mtx); 4540 4541 return (ret); 4542 } 4543 4544 static void 4545 unref_ctx_core_offset(if_ctx_t ctx) 4546 { 4547 struct cpu_offset *op, *top; 4548 4549 mtx_lock(&cpu_offset_mtx); 4550 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4551 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4552 MPASS(op->refcount > 0); 4553 op->refcount--; 4554 if (op->refcount == 0) { 4555 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4556 free(op, M_IFLIB); 4557 } 4558 break; 4559 } 4560 } 4561 mtx_unlock(&cpu_offset_mtx); 4562 } 4563 4564 int 4565 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4566 { 4567 if_ctx_t ctx; 4568 if_t ifp; 4569 if_softc_ctx_t scctx; 4570 kobjop_desc_t kobj_desc; 4571 kobj_method_t *kobj_method; 4572 int err, msix, rid; 4573 uint16_t main_rxq, main_txq; 4574 4575 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4576 4577 if (sc == NULL) { 4578 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4579 device_set_softc(dev, ctx); 4580 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4581 } 4582 4583 ctx->ifc_sctx = sctx; 4584 ctx->ifc_dev = dev; 4585 ctx->ifc_softc = sc; 4586 4587 if ((err = iflib_register(ctx)) != 0) { 4588 device_printf(dev, "iflib_register failed %d\n", err); 4589 goto fail_ctx_free; 4590 } 4591 iflib_add_device_sysctl_pre(ctx); 4592 4593 scctx = &ctx->ifc_softc_ctx; 4594 ifp = ctx->ifc_ifp; 4595 4596 iflib_reset_qvalues(ctx); 4597 CTX_LOCK(ctx); 4598 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4599 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4600 goto fail_unlock; 4601 } 4602 _iflib_pre_assert(scctx); 4603 ctx->ifc_txrx = *scctx->isc_txrx; 4604 4605 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 4606 ctx->ifc_mediap = scctx->isc_media; 4607 4608 #ifdef INVARIANTS 4609 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4610 MPASS(scctx->isc_tx_csum_flags); 4611 #endif 4612 4613 if_setcapabilities(ifp, 4614 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP); 4615 if_setcapenable(ifp, 4616 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP); 4617 4618 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4619 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4620 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4621 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4622 4623 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4624 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4625 4626 /* XXX change for per-queue sizes */ 4627 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4628 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4629 4630 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4631 MAX_SINGLE_PACKET_FRACTION) 4632 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4633 MAX_SINGLE_PACKET_FRACTION); 4634 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4635 MAX_SINGLE_PACKET_FRACTION) 4636 scctx->isc_tx_tso_segments_max = max(1, 4637 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4638 4639 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4640 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4641 /* 4642 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4643 * but some MACs do. 4644 */ 4645 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4646 IP_MAXPACKET)); 4647 /* 4648 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4649 * into account. In the worst case, each of these calls will 4650 * add another mbuf and, thus, the requirement for another DMA 4651 * segment. So for best performance, it doesn't make sense to 4652 * advertize a maximum of TSO segments that typically will 4653 * require defragmentation in iflib_encap(). 4654 */ 4655 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4656 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4657 } 4658 if (scctx->isc_rss_table_size == 0) 4659 scctx->isc_rss_table_size = 64; 4660 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4661 4662 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4663 /* XXX format name */ 4664 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4665 NULL, NULL, "admin"); 4666 4667 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4668 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4669 device_printf(dev, "Unable to fetch CPU list\n"); 4670 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4671 } 4672 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4673 4674 /* 4675 ** Now set up MSI or MSI-X, should return us the number of supported 4676 ** vectors (will be 1 for a legacy interrupt and MSI). 4677 */ 4678 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4679 msix = scctx->isc_vectors; 4680 } else if (scctx->isc_msix_bar != 0) 4681 /* 4682 * The simple fact that isc_msix_bar is not 0 does not mean we 4683 * we have a good value there that is known to work. 4684 */ 4685 msix = iflib_msix_init(ctx); 4686 else { 4687 scctx->isc_vectors = 1; 4688 scctx->isc_ntxqsets = 1; 4689 scctx->isc_nrxqsets = 1; 4690 scctx->isc_intr = IFLIB_INTR_LEGACY; 4691 msix = 0; 4692 } 4693 /* Get memory for the station queues */ 4694 if ((err = iflib_queues_alloc(ctx))) { 4695 device_printf(dev, "Unable to allocate queue memory\n"); 4696 goto fail_intr_free; 4697 } 4698 4699 if ((err = iflib_qset_structures_setup(ctx))) 4700 goto fail_queues; 4701 4702 /* 4703 * Now that we know how many queues there are, get the core offset. 4704 */ 4705 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 4706 4707 /* 4708 * Group taskqueues aren't properly set up until SMP is started, 4709 * so we disable interrupts until we can handle them post 4710 * SI_SUB_SMP. 4711 * 4712 * XXX: disabling interrupts doesn't actually work, at least for 4713 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4714 * we do null handling and depend on this not causing too large an 4715 * interrupt storm. 4716 */ 4717 IFDI_INTR_DISABLE(ctx); 4718 4719 if (msix > 1) { 4720 /* 4721 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 4722 * aren't the default NULL implementation. 4723 */ 4724 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 4725 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4726 kobj_desc); 4727 if (kobj_method == &kobj_desc->deflt) { 4728 device_printf(dev, 4729 "MSI-X requires ifdi_rx_queue_intr_enable method"); 4730 err = EOPNOTSUPP; 4731 goto fail_queues; 4732 } 4733 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 4734 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4735 kobj_desc); 4736 if (kobj_method == &kobj_desc->deflt) { 4737 device_printf(dev, 4738 "MSI-X requires ifdi_tx_queue_intr_enable method"); 4739 err = EOPNOTSUPP; 4740 goto fail_queues; 4741 } 4742 4743 /* 4744 * Assign the MSI-X vectors. 4745 * Note that the default NULL ifdi_msix_intr_assign method will 4746 * fail here, too. 4747 */ 4748 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 4749 if (err != 0) { 4750 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 4751 err); 4752 goto fail_queues; 4753 } 4754 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 4755 rid = 0; 4756 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4757 MPASS(msix == 1); 4758 rid = 1; 4759 } 4760 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4761 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4762 goto fail_queues; 4763 } 4764 } else { 4765 device_printf(dev, 4766 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 4767 err = ENODEV; 4768 goto fail_intr_free; 4769 } 4770 4771 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4772 4773 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4774 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4775 goto fail_detach; 4776 } 4777 4778 /* 4779 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4780 * This must appear after the call to ether_ifattach() because 4781 * ether_ifattach() sets if_hdrlen to the default value. 4782 */ 4783 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4784 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4785 4786 if ((err = iflib_netmap_attach(ctx))) { 4787 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4788 goto fail_detach; 4789 } 4790 *ctxp = ctx; 4791 4792 DEBUGNET_SET(ctx->ifc_ifp, iflib); 4793 4794 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4795 iflib_add_device_sysctl_post(ctx); 4796 iflib_add_pfil(ctx); 4797 ctx->ifc_flags |= IFC_INIT_DONE; 4798 CTX_UNLOCK(ctx); 4799 4800 return (0); 4801 4802 fail_detach: 4803 ether_ifdetach(ctx->ifc_ifp); 4804 fail_intr_free: 4805 iflib_free_intr_mem(ctx); 4806 fail_queues: 4807 iflib_tx_structures_free(ctx); 4808 iflib_rx_structures_free(ctx); 4809 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task); 4810 IFDI_DETACH(ctx); 4811 fail_unlock: 4812 CTX_UNLOCK(ctx); 4813 iflib_deregister(ctx); 4814 fail_ctx_free: 4815 device_set_softc(ctx->ifc_dev, NULL); 4816 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4817 free(ctx->ifc_softc, M_IFLIB); 4818 free(ctx, M_IFLIB); 4819 return (err); 4820 } 4821 4822 int 4823 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4824 struct iflib_cloneattach_ctx *clctx) 4825 { 4826 int err; 4827 if_ctx_t ctx; 4828 if_t ifp; 4829 if_softc_ctx_t scctx; 4830 int i; 4831 void *sc; 4832 uint16_t main_txq; 4833 uint16_t main_rxq; 4834 4835 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4836 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4837 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4838 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4839 ctx->ifc_flags |= IFC_PSEUDO; 4840 4841 ctx->ifc_sctx = sctx; 4842 ctx->ifc_softc = sc; 4843 ctx->ifc_dev = dev; 4844 4845 if ((err = iflib_register(ctx)) != 0) { 4846 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4847 goto fail_ctx_free; 4848 } 4849 iflib_add_device_sysctl_pre(ctx); 4850 4851 scctx = &ctx->ifc_softc_ctx; 4852 ifp = ctx->ifc_ifp; 4853 4854 iflib_reset_qvalues(ctx); 4855 CTX_LOCK(ctx); 4856 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4857 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4858 goto fail_unlock; 4859 } 4860 if (sctx->isc_flags & IFLIB_GEN_MAC) 4861 ether_gen_addr(ifp, &ctx->ifc_mac); 4862 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4863 clctx->cc_params)) != 0) { 4864 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4865 goto fail_ctx_free; 4866 } 4867 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4868 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4869 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4870 4871 #ifdef INVARIANTS 4872 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4873 MPASS(scctx->isc_tx_csum_flags); 4874 #endif 4875 4876 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4877 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4878 4879 ifp->if_flags |= IFF_NOGROUP; 4880 if (sctx->isc_flags & IFLIB_PSEUDO) { 4881 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4882 4883 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4884 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4885 goto fail_detach; 4886 } 4887 *ctxp = ctx; 4888 4889 /* 4890 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4891 * This must appear after the call to ether_ifattach() because 4892 * ether_ifattach() sets if_hdrlen to the default value. 4893 */ 4894 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4895 if_setifheaderlen(ifp, 4896 sizeof(struct ether_vlan_header)); 4897 4898 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4899 iflib_add_device_sysctl_post(ctx); 4900 ctx->ifc_flags |= IFC_INIT_DONE; 4901 return (0); 4902 } 4903 _iflib_pre_assert(scctx); 4904 ctx->ifc_txrx = *scctx->isc_txrx; 4905 4906 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4907 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4908 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4909 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4910 4911 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4912 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4913 4914 /* XXX change for per-queue sizes */ 4915 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4916 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4917 4918 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4919 MAX_SINGLE_PACKET_FRACTION) 4920 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4921 MAX_SINGLE_PACKET_FRACTION); 4922 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4923 MAX_SINGLE_PACKET_FRACTION) 4924 scctx->isc_tx_tso_segments_max = max(1, 4925 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4926 4927 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4928 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4929 /* 4930 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4931 * but some MACs do. 4932 */ 4933 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4934 IP_MAXPACKET)); 4935 /* 4936 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4937 * into account. In the worst case, each of these calls will 4938 * add another mbuf and, thus, the requirement for another DMA 4939 * segment. So for best performance, it doesn't make sense to 4940 * advertize a maximum of TSO segments that typically will 4941 * require defragmentation in iflib_encap(). 4942 */ 4943 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4944 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4945 } 4946 if (scctx->isc_rss_table_size == 0) 4947 scctx->isc_rss_table_size = 64; 4948 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4949 4950 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4951 /* XXX format name */ 4952 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4953 NULL, NULL, "admin"); 4954 4955 /* XXX --- can support > 1 -- but keep it simple for now */ 4956 scctx->isc_intr = IFLIB_INTR_LEGACY; 4957 4958 /* Get memory for the station queues */ 4959 if ((err = iflib_queues_alloc(ctx))) { 4960 device_printf(dev, "Unable to allocate queue memory\n"); 4961 goto fail_iflib_detach; 4962 } 4963 4964 if ((err = iflib_qset_structures_setup(ctx))) { 4965 device_printf(dev, "qset structure setup failed %d\n", err); 4966 goto fail_queues; 4967 } 4968 4969 /* 4970 * XXX What if anything do we want to do about interrupts? 4971 */ 4972 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4973 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4974 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4975 goto fail_detach; 4976 } 4977 4978 /* 4979 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4980 * This must appear after the call to ether_ifattach() because 4981 * ether_ifattach() sets if_hdrlen to the default value. 4982 */ 4983 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4984 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4985 4986 /* XXX handle more than one queue */ 4987 for (i = 0; i < scctx->isc_nrxqsets; i++) 4988 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4989 4990 *ctxp = ctx; 4991 4992 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4993 iflib_add_device_sysctl_post(ctx); 4994 ctx->ifc_flags |= IFC_INIT_DONE; 4995 CTX_UNLOCK(ctx); 4996 4997 return (0); 4998 fail_detach: 4999 ether_ifdetach(ctx->ifc_ifp); 5000 fail_queues: 5001 iflib_tx_structures_free(ctx); 5002 iflib_rx_structures_free(ctx); 5003 fail_iflib_detach: 5004 IFDI_DETACH(ctx); 5005 fail_unlock: 5006 CTX_UNLOCK(ctx); 5007 iflib_deregister(ctx); 5008 fail_ctx_free: 5009 free(ctx->ifc_softc, M_IFLIB); 5010 free(ctx, M_IFLIB); 5011 return (err); 5012 } 5013 5014 int 5015 iflib_pseudo_deregister(if_ctx_t ctx) 5016 { 5017 if_t ifp = ctx->ifc_ifp; 5018 iflib_txq_t txq; 5019 iflib_rxq_t rxq; 5020 int i, j; 5021 struct taskqgroup *tqg; 5022 iflib_fl_t fl; 5023 5024 /* Unregister VLAN event handlers early */ 5025 iflib_unregister_vlan_handlers(ctx); 5026 5027 ether_ifdetach(ifp); 5028 /* XXX drain any dependent tasks */ 5029 tqg = qgroup_if_io_tqg; 5030 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5031 callout_drain(&txq->ift_timer); 5032 if (txq->ift_task.gt_uniq != NULL) 5033 taskqgroup_detach(tqg, &txq->ift_task); 5034 } 5035 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5036 if (rxq->ifr_task.gt_uniq != NULL) 5037 taskqgroup_detach(tqg, &rxq->ifr_task); 5038 5039 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5040 free(fl->ifl_rx_bitmap, M_IFLIB); 5041 } 5042 tqg = qgroup_if_config_tqg; 5043 if (ctx->ifc_admin_task.gt_uniq != NULL) 5044 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5045 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5046 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5047 5048 iflib_tx_structures_free(ctx); 5049 iflib_rx_structures_free(ctx); 5050 5051 iflib_deregister(ctx); 5052 5053 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5054 free(ctx->ifc_softc, M_IFLIB); 5055 free(ctx, M_IFLIB); 5056 return (0); 5057 } 5058 5059 int 5060 iflib_device_attach(device_t dev) 5061 { 5062 if_ctx_t ctx; 5063 if_shared_ctx_t sctx; 5064 5065 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5066 return (ENOTSUP); 5067 5068 pci_enable_busmaster(dev); 5069 5070 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5071 } 5072 5073 int 5074 iflib_device_deregister(if_ctx_t ctx) 5075 { 5076 if_t ifp = ctx->ifc_ifp; 5077 iflib_txq_t txq; 5078 iflib_rxq_t rxq; 5079 device_t dev = ctx->ifc_dev; 5080 int i, j; 5081 struct taskqgroup *tqg; 5082 iflib_fl_t fl; 5083 5084 /* Make sure VLANS are not using driver */ 5085 if (if_vlantrunkinuse(ifp)) { 5086 device_printf(dev, "Vlan in use, detach first\n"); 5087 return (EBUSY); 5088 } 5089 #ifdef PCI_IOV 5090 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5091 device_printf(dev, "SR-IOV in use; detach first.\n"); 5092 return (EBUSY); 5093 } 5094 #endif 5095 5096 STATE_LOCK(ctx); 5097 ctx->ifc_flags |= IFC_IN_DETACH; 5098 STATE_UNLOCK(ctx); 5099 5100 /* Unregister VLAN handlers before calling iflib_stop() */ 5101 iflib_unregister_vlan_handlers(ctx); 5102 5103 iflib_netmap_detach(ifp); 5104 ether_ifdetach(ifp); 5105 5106 CTX_LOCK(ctx); 5107 iflib_stop(ctx); 5108 CTX_UNLOCK(ctx); 5109 5110 iflib_rem_pfil(ctx); 5111 if (ctx->ifc_led_dev != NULL) 5112 led_destroy(ctx->ifc_led_dev); 5113 /* XXX drain any dependent tasks */ 5114 tqg = qgroup_if_io_tqg; 5115 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5116 callout_drain(&txq->ift_timer); 5117 if (txq->ift_task.gt_uniq != NULL) 5118 taskqgroup_detach(tqg, &txq->ift_task); 5119 } 5120 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5121 if (rxq->ifr_task.gt_uniq != NULL) 5122 taskqgroup_detach(tqg, &rxq->ifr_task); 5123 5124 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5125 free(fl->ifl_rx_bitmap, M_IFLIB); 5126 } 5127 tqg = qgroup_if_config_tqg; 5128 if (ctx->ifc_admin_task.gt_uniq != NULL) 5129 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5130 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5131 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5132 CTX_LOCK(ctx); 5133 IFDI_DETACH(ctx); 5134 CTX_UNLOCK(ctx); 5135 5136 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5137 iflib_free_intr_mem(ctx); 5138 5139 bus_generic_detach(dev); 5140 5141 iflib_tx_structures_free(ctx); 5142 iflib_rx_structures_free(ctx); 5143 5144 iflib_deregister(ctx); 5145 5146 device_set_softc(ctx->ifc_dev, NULL); 5147 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5148 free(ctx->ifc_softc, M_IFLIB); 5149 unref_ctx_core_offset(ctx); 5150 free(ctx, M_IFLIB); 5151 return (0); 5152 } 5153 5154 static void 5155 iflib_free_intr_mem(if_ctx_t ctx) 5156 { 5157 5158 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5159 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5160 } 5161 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5162 pci_release_msi(ctx->ifc_dev); 5163 } 5164 if (ctx->ifc_msix_mem != NULL) { 5165 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5166 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5167 ctx->ifc_msix_mem = NULL; 5168 } 5169 } 5170 5171 int 5172 iflib_device_detach(device_t dev) 5173 { 5174 if_ctx_t ctx = device_get_softc(dev); 5175 5176 return (iflib_device_deregister(ctx)); 5177 } 5178 5179 int 5180 iflib_device_suspend(device_t dev) 5181 { 5182 if_ctx_t ctx = device_get_softc(dev); 5183 5184 CTX_LOCK(ctx); 5185 IFDI_SUSPEND(ctx); 5186 CTX_UNLOCK(ctx); 5187 5188 return bus_generic_suspend(dev); 5189 } 5190 int 5191 iflib_device_shutdown(device_t dev) 5192 { 5193 if_ctx_t ctx = device_get_softc(dev); 5194 5195 CTX_LOCK(ctx); 5196 IFDI_SHUTDOWN(ctx); 5197 CTX_UNLOCK(ctx); 5198 5199 return bus_generic_suspend(dev); 5200 } 5201 5202 5203 int 5204 iflib_device_resume(device_t dev) 5205 { 5206 if_ctx_t ctx = device_get_softc(dev); 5207 iflib_txq_t txq = ctx->ifc_txqs; 5208 5209 CTX_LOCK(ctx); 5210 IFDI_RESUME(ctx); 5211 iflib_if_init_locked(ctx); 5212 CTX_UNLOCK(ctx); 5213 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5214 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5215 5216 return (bus_generic_resume(dev)); 5217 } 5218 5219 int 5220 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5221 { 5222 int error; 5223 if_ctx_t ctx = device_get_softc(dev); 5224 5225 CTX_LOCK(ctx); 5226 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5227 CTX_UNLOCK(ctx); 5228 5229 return (error); 5230 } 5231 5232 void 5233 iflib_device_iov_uninit(device_t dev) 5234 { 5235 if_ctx_t ctx = device_get_softc(dev); 5236 5237 CTX_LOCK(ctx); 5238 IFDI_IOV_UNINIT(ctx); 5239 CTX_UNLOCK(ctx); 5240 } 5241 5242 int 5243 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5244 { 5245 int error; 5246 if_ctx_t ctx = device_get_softc(dev); 5247 5248 CTX_LOCK(ctx); 5249 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5250 CTX_UNLOCK(ctx); 5251 5252 return (error); 5253 } 5254 5255 /********************************************************************* 5256 * 5257 * MODULE FUNCTION DEFINITIONS 5258 * 5259 **********************************************************************/ 5260 5261 /* 5262 * - Start a fast taskqueue thread for each core 5263 * - Start a taskqueue for control operations 5264 */ 5265 static int 5266 iflib_module_init(void) 5267 { 5268 return (0); 5269 } 5270 5271 static int 5272 iflib_module_event_handler(module_t mod, int what, void *arg) 5273 { 5274 int err; 5275 5276 switch (what) { 5277 case MOD_LOAD: 5278 if ((err = iflib_module_init()) != 0) 5279 return (err); 5280 break; 5281 case MOD_UNLOAD: 5282 return (EBUSY); 5283 default: 5284 return (EOPNOTSUPP); 5285 } 5286 5287 return (0); 5288 } 5289 5290 /********************************************************************* 5291 * 5292 * PUBLIC FUNCTION DEFINITIONS 5293 * ordered as in iflib.h 5294 * 5295 **********************************************************************/ 5296 5297 5298 static void 5299 _iflib_assert(if_shared_ctx_t sctx) 5300 { 5301 int i; 5302 5303 MPASS(sctx->isc_tx_maxsize); 5304 MPASS(sctx->isc_tx_maxsegsize); 5305 5306 MPASS(sctx->isc_rx_maxsize); 5307 MPASS(sctx->isc_rx_nsegments); 5308 MPASS(sctx->isc_rx_maxsegsize); 5309 5310 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5311 for (i = 0; i < sctx->isc_nrxqs; i++) { 5312 MPASS(sctx->isc_nrxd_min[i]); 5313 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5314 MPASS(sctx->isc_nrxd_max[i]); 5315 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5316 MPASS(sctx->isc_nrxd_default[i]); 5317 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5318 } 5319 5320 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5321 for (i = 0; i < sctx->isc_ntxqs; i++) { 5322 MPASS(sctx->isc_ntxd_min[i]); 5323 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5324 MPASS(sctx->isc_ntxd_max[i]); 5325 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5326 MPASS(sctx->isc_ntxd_default[i]); 5327 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5328 } 5329 } 5330 5331 static void 5332 _iflib_pre_assert(if_softc_ctx_t scctx) 5333 { 5334 5335 MPASS(scctx->isc_txrx->ift_txd_encap); 5336 MPASS(scctx->isc_txrx->ift_txd_flush); 5337 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5338 MPASS(scctx->isc_txrx->ift_rxd_available); 5339 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5340 MPASS(scctx->isc_txrx->ift_rxd_refill); 5341 MPASS(scctx->isc_txrx->ift_rxd_flush); 5342 } 5343 5344 static int 5345 iflib_register(if_ctx_t ctx) 5346 { 5347 if_shared_ctx_t sctx = ctx->ifc_sctx; 5348 driver_t *driver = sctx->isc_driver; 5349 device_t dev = ctx->ifc_dev; 5350 if_t ifp; 5351 5352 _iflib_assert(sctx); 5353 5354 CTX_LOCK_INIT(ctx); 5355 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5356 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5357 if (ifp == NULL) { 5358 device_printf(dev, "can not allocate ifnet structure\n"); 5359 return (ENOMEM); 5360 } 5361 5362 /* 5363 * Initialize our context's device specific methods 5364 */ 5365 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5366 kobj_class_compile((kobj_class_t) driver); 5367 5368 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5369 if_setsoftc(ifp, ctx); 5370 if_setdev(ifp, dev); 5371 if_setinitfn(ifp, iflib_if_init); 5372 if_setioctlfn(ifp, iflib_if_ioctl); 5373 #ifdef ALTQ 5374 if_setstartfn(ifp, iflib_altq_if_start); 5375 if_settransmitfn(ifp, iflib_altq_if_transmit); 5376 if_setsendqready(ifp); 5377 #else 5378 if_settransmitfn(ifp, iflib_if_transmit); 5379 #endif 5380 if_setqflushfn(ifp, iflib_if_qflush); 5381 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5382 5383 ctx->ifc_vlan_attach_event = 5384 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5385 EVENTHANDLER_PRI_FIRST); 5386 ctx->ifc_vlan_detach_event = 5387 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5388 EVENTHANDLER_PRI_FIRST); 5389 5390 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5391 ctx->ifc_mediap = &ctx->ifc_media; 5392 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5393 iflib_media_change, iflib_media_status); 5394 } 5395 return (0); 5396 } 5397 5398 static void 5399 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5400 { 5401 /* Unregister VLAN events */ 5402 if (ctx->ifc_vlan_attach_event != NULL) { 5403 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5404 ctx->ifc_vlan_attach_event = NULL; 5405 } 5406 if (ctx->ifc_vlan_detach_event != NULL) { 5407 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5408 ctx->ifc_vlan_detach_event = NULL; 5409 } 5410 5411 } 5412 5413 static void 5414 iflib_deregister(if_ctx_t ctx) 5415 { 5416 if_t ifp = ctx->ifc_ifp; 5417 5418 /* Remove all media */ 5419 ifmedia_removeall(&ctx->ifc_media); 5420 5421 /* Ensure that VLAN event handlers are unregistered */ 5422 iflib_unregister_vlan_handlers(ctx); 5423 5424 /* Release kobject reference */ 5425 kobj_delete((kobj_t) ctx, NULL); 5426 5427 /* Free the ifnet structure */ 5428 if_free(ifp); 5429 5430 STATE_LOCK_DESTROY(ctx); 5431 5432 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5433 CTX_LOCK_DESTROY(ctx); 5434 } 5435 5436 static int 5437 iflib_queues_alloc(if_ctx_t ctx) 5438 { 5439 if_shared_ctx_t sctx = ctx->ifc_sctx; 5440 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5441 device_t dev = ctx->ifc_dev; 5442 int nrxqsets = scctx->isc_nrxqsets; 5443 int ntxqsets = scctx->isc_ntxqsets; 5444 iflib_txq_t txq; 5445 iflib_rxq_t rxq; 5446 iflib_fl_t fl = NULL; 5447 int i, j, cpu, err, txconf, rxconf; 5448 iflib_dma_info_t ifdip; 5449 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5450 uint32_t *txqsizes = scctx->isc_txqsizes; 5451 uint8_t nrxqs = sctx->isc_nrxqs; 5452 uint8_t ntxqs = sctx->isc_ntxqs; 5453 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5454 caddr_t *vaddrs; 5455 uint64_t *paddrs; 5456 5457 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5458 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5459 5460 /* Allocate the TX ring struct memory */ 5461 if (!(ctx->ifc_txqs = 5462 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5463 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5464 device_printf(dev, "Unable to allocate TX ring memory\n"); 5465 err = ENOMEM; 5466 goto fail; 5467 } 5468 5469 /* Now allocate the RX */ 5470 if (!(ctx->ifc_rxqs = 5471 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5472 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5473 device_printf(dev, "Unable to allocate RX ring memory\n"); 5474 err = ENOMEM; 5475 goto rx_fail; 5476 } 5477 5478 txq = ctx->ifc_txqs; 5479 rxq = ctx->ifc_rxqs; 5480 5481 /* 5482 * XXX handle allocation failure 5483 */ 5484 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5485 /* Set up some basics */ 5486 5487 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5488 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5489 device_printf(dev, 5490 "Unable to allocate TX DMA info memory\n"); 5491 err = ENOMEM; 5492 goto err_tx_desc; 5493 } 5494 txq->ift_ifdi = ifdip; 5495 for (j = 0; j < ntxqs; j++, ifdip++) { 5496 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5497 device_printf(dev, 5498 "Unable to allocate TX descriptors\n"); 5499 err = ENOMEM; 5500 goto err_tx_desc; 5501 } 5502 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5503 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5504 } 5505 txq->ift_ctx = ctx; 5506 txq->ift_id = i; 5507 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5508 txq->ift_br_offset = 1; 5509 } else { 5510 txq->ift_br_offset = 0; 5511 } 5512 /* XXX fix this */ 5513 txq->ift_timer.c_cpu = cpu; 5514 5515 if (iflib_txsd_alloc(txq)) { 5516 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5517 err = ENOMEM; 5518 goto err_tx_desc; 5519 } 5520 5521 /* Initialize the TX lock */ 5522 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5523 device_get_nameunit(dev), txq->ift_id); 5524 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5525 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5526 5527 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5528 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5529 if (err) { 5530 /* XXX free any allocated rings */ 5531 device_printf(dev, "Unable to allocate buf_ring\n"); 5532 goto err_tx_desc; 5533 } 5534 } 5535 5536 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5537 /* Set up some basics */ 5538 5539 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5540 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5541 device_printf(dev, 5542 "Unable to allocate RX DMA info memory\n"); 5543 err = ENOMEM; 5544 goto err_tx_desc; 5545 } 5546 5547 rxq->ifr_ifdi = ifdip; 5548 /* XXX this needs to be changed if #rx queues != #tx queues */ 5549 rxq->ifr_ntxqirq = 1; 5550 rxq->ifr_txqid[0] = i; 5551 for (j = 0; j < nrxqs; j++, ifdip++) { 5552 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5553 device_printf(dev, 5554 "Unable to allocate RX descriptors\n"); 5555 err = ENOMEM; 5556 goto err_tx_desc; 5557 } 5558 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5559 } 5560 rxq->ifr_ctx = ctx; 5561 rxq->ifr_id = i; 5562 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5563 rxq->ifr_fl_offset = 1; 5564 } else { 5565 rxq->ifr_fl_offset = 0; 5566 } 5567 rxq->ifr_nfl = nfree_lists; 5568 if (!(fl = 5569 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5570 device_printf(dev, "Unable to allocate free list memory\n"); 5571 err = ENOMEM; 5572 goto err_tx_desc; 5573 } 5574 rxq->ifr_fl = fl; 5575 for (j = 0; j < nfree_lists; j++) { 5576 fl[j].ifl_rxq = rxq; 5577 fl[j].ifl_id = j; 5578 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5579 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5580 } 5581 /* Allocate receive buffers for the ring */ 5582 if (iflib_rxsd_alloc(rxq)) { 5583 device_printf(dev, 5584 "Critical Failure setting up receive buffers\n"); 5585 err = ENOMEM; 5586 goto err_rx_desc; 5587 } 5588 5589 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5590 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5591 M_WAITOK); 5592 } 5593 5594 /* TXQs */ 5595 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5596 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5597 for (i = 0; i < ntxqsets; i++) { 5598 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5599 5600 for (j = 0; j < ntxqs; j++, di++) { 5601 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5602 paddrs[i*ntxqs + j] = di->idi_paddr; 5603 } 5604 } 5605 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5606 device_printf(ctx->ifc_dev, 5607 "Unable to allocate device TX queue\n"); 5608 iflib_tx_structures_free(ctx); 5609 free(vaddrs, M_IFLIB); 5610 free(paddrs, M_IFLIB); 5611 goto err_rx_desc; 5612 } 5613 free(vaddrs, M_IFLIB); 5614 free(paddrs, M_IFLIB); 5615 5616 /* RXQs */ 5617 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5618 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5619 for (i = 0; i < nrxqsets; i++) { 5620 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5621 5622 for (j = 0; j < nrxqs; j++, di++) { 5623 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5624 paddrs[i*nrxqs + j] = di->idi_paddr; 5625 } 5626 } 5627 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5628 device_printf(ctx->ifc_dev, 5629 "Unable to allocate device RX queue\n"); 5630 iflib_tx_structures_free(ctx); 5631 free(vaddrs, M_IFLIB); 5632 free(paddrs, M_IFLIB); 5633 goto err_rx_desc; 5634 } 5635 free(vaddrs, M_IFLIB); 5636 free(paddrs, M_IFLIB); 5637 5638 return (0); 5639 5640 /* XXX handle allocation failure changes */ 5641 err_rx_desc: 5642 err_tx_desc: 5643 rx_fail: 5644 if (ctx->ifc_rxqs != NULL) 5645 free(ctx->ifc_rxqs, M_IFLIB); 5646 ctx->ifc_rxqs = NULL; 5647 if (ctx->ifc_txqs != NULL) 5648 free(ctx->ifc_txqs, M_IFLIB); 5649 ctx->ifc_txqs = NULL; 5650 fail: 5651 return (err); 5652 } 5653 5654 static int 5655 iflib_tx_structures_setup(if_ctx_t ctx) 5656 { 5657 iflib_txq_t txq = ctx->ifc_txqs; 5658 int i; 5659 5660 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5661 iflib_txq_setup(txq); 5662 5663 return (0); 5664 } 5665 5666 static void 5667 iflib_tx_structures_free(if_ctx_t ctx) 5668 { 5669 iflib_txq_t txq = ctx->ifc_txqs; 5670 if_shared_ctx_t sctx = ctx->ifc_sctx; 5671 int i, j; 5672 5673 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5674 for (j = 0; j < sctx->isc_ntxqs; j++) 5675 iflib_dma_free(&txq->ift_ifdi[j]); 5676 iflib_txq_destroy(txq); 5677 } 5678 free(ctx->ifc_txqs, M_IFLIB); 5679 ctx->ifc_txqs = NULL; 5680 IFDI_QUEUES_FREE(ctx); 5681 } 5682 5683 /********************************************************************* 5684 * 5685 * Initialize all receive rings. 5686 * 5687 **********************************************************************/ 5688 static int 5689 iflib_rx_structures_setup(if_ctx_t ctx) 5690 { 5691 iflib_rxq_t rxq = ctx->ifc_rxqs; 5692 int q; 5693 #if defined(INET6) || defined(INET) 5694 int err, i; 5695 #endif 5696 5697 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5698 #if defined(INET6) || defined(INET) 5699 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) { 5700 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5701 TCP_LRO_ENTRIES, min(1024, 5702 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 5703 if (err != 0) { 5704 device_printf(ctx->ifc_dev, 5705 "LRO Initialization failed!\n"); 5706 goto fail; 5707 } 5708 } 5709 #endif 5710 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5711 } 5712 return (0); 5713 #if defined(INET6) || defined(INET) 5714 fail: 5715 /* 5716 * Free LRO resources allocated so far, we will only handle 5717 * the rings that completed, the failing case will have 5718 * cleaned up for itself. 'q' failed, so its the terminus. 5719 */ 5720 rxq = ctx->ifc_rxqs; 5721 for (i = 0; i < q; ++i, rxq++) { 5722 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5723 tcp_lro_free(&rxq->ifr_lc); 5724 } 5725 return (err); 5726 #endif 5727 } 5728 5729 /********************************************************************* 5730 * 5731 * Free all receive rings. 5732 * 5733 **********************************************************************/ 5734 static void 5735 iflib_rx_structures_free(if_ctx_t ctx) 5736 { 5737 iflib_rxq_t rxq = ctx->ifc_rxqs; 5738 int i; 5739 5740 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5741 iflib_rx_sds_free(rxq); 5742 #if defined(INET6) || defined(INET) 5743 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5744 tcp_lro_free(&rxq->ifr_lc); 5745 #endif 5746 } 5747 free(ctx->ifc_rxqs, M_IFLIB); 5748 ctx->ifc_rxqs = NULL; 5749 } 5750 5751 static int 5752 iflib_qset_structures_setup(if_ctx_t ctx) 5753 { 5754 int err; 5755 5756 /* 5757 * It is expected that the caller takes care of freeing queues if this 5758 * fails. 5759 */ 5760 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5761 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5762 return (err); 5763 } 5764 5765 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5766 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5767 5768 return (err); 5769 } 5770 5771 int 5772 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5773 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5774 { 5775 5776 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5777 } 5778 5779 #ifdef SMP 5780 static int 5781 find_nth(if_ctx_t ctx, int qid) 5782 { 5783 cpuset_t cpus; 5784 int i, cpuid, eqid, count; 5785 5786 CPU_COPY(&ctx->ifc_cpus, &cpus); 5787 count = CPU_COUNT(&cpus); 5788 eqid = qid % count; 5789 /* clear up to the qid'th bit */ 5790 for (i = 0; i < eqid; i++) { 5791 cpuid = CPU_FFS(&cpus); 5792 MPASS(cpuid != 0); 5793 CPU_CLR(cpuid-1, &cpus); 5794 } 5795 cpuid = CPU_FFS(&cpus); 5796 MPASS(cpuid != 0); 5797 return (cpuid-1); 5798 } 5799 5800 #ifdef SCHED_ULE 5801 extern struct cpu_group *cpu_top; /* CPU topology */ 5802 5803 static int 5804 find_child_with_core(int cpu, struct cpu_group *grp) 5805 { 5806 int i; 5807 5808 if (grp->cg_children == 0) 5809 return -1; 5810 5811 MPASS(grp->cg_child); 5812 for (i = 0; i < grp->cg_children; i++) { 5813 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5814 return i; 5815 } 5816 5817 return -1; 5818 } 5819 5820 /* 5821 * Find the nth "close" core to the specified core 5822 * "close" is defined as the deepest level that shares 5823 * at least an L2 cache. With threads, this will be 5824 * threads on the same core. If the shared cache is L3 5825 * or higher, simply returns the same core. 5826 */ 5827 static int 5828 find_close_core(int cpu, int core_offset) 5829 { 5830 struct cpu_group *grp; 5831 int i; 5832 int fcpu; 5833 cpuset_t cs; 5834 5835 grp = cpu_top; 5836 if (grp == NULL) 5837 return cpu; 5838 i = 0; 5839 while ((i = find_child_with_core(cpu, grp)) != -1) { 5840 /* If the child only has one cpu, don't descend */ 5841 if (grp->cg_child[i].cg_count <= 1) 5842 break; 5843 grp = &grp->cg_child[i]; 5844 } 5845 5846 /* If they don't share at least an L2 cache, use the same CPU */ 5847 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5848 return cpu; 5849 5850 /* Now pick one */ 5851 CPU_COPY(&grp->cg_mask, &cs); 5852 5853 /* Add the selected CPU offset to core offset. */ 5854 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5855 if (fcpu - 1 == cpu) 5856 break; 5857 CPU_CLR(fcpu - 1, &cs); 5858 } 5859 MPASS(fcpu); 5860 5861 core_offset += i; 5862 5863 CPU_COPY(&grp->cg_mask, &cs); 5864 for (i = core_offset % grp->cg_count; i > 0; i--) { 5865 MPASS(CPU_FFS(&cs)); 5866 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5867 } 5868 MPASS(CPU_FFS(&cs)); 5869 return CPU_FFS(&cs) - 1; 5870 } 5871 #else 5872 static int 5873 find_close_core(int cpu, int core_offset __unused) 5874 { 5875 return cpu; 5876 } 5877 #endif 5878 5879 static int 5880 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5881 { 5882 switch (type) { 5883 case IFLIB_INTR_TX: 5884 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5885 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5886 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5887 case IFLIB_INTR_RX: 5888 case IFLIB_INTR_RXTX: 5889 /* RX queues get the specified core */ 5890 return qid / CPU_COUNT(&ctx->ifc_cpus); 5891 default: 5892 return -1; 5893 } 5894 } 5895 #else 5896 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5897 #define find_close_core(cpuid, tid) CPU_FIRST() 5898 #define find_nth(ctx, gid) CPU_FIRST() 5899 #endif 5900 5901 /* Just to avoid copy/paste */ 5902 static inline int 5903 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5904 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5905 const char *name) 5906 { 5907 device_t dev; 5908 int co, cpuid, err, tid; 5909 5910 dev = ctx->ifc_dev; 5911 co = ctx->ifc_sysctl_core_offset; 5912 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX) 5913 co += ctx->ifc_softc_ctx.isc_nrxqsets; 5914 cpuid = find_nth(ctx, qid + co); 5915 tid = get_core_offset(ctx, type, qid); 5916 if (tid < 0) { 5917 device_printf(dev, "get_core_offset failed\n"); 5918 return (EOPNOTSUPP); 5919 } 5920 cpuid = find_close_core(cpuid, tid); 5921 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 5922 name); 5923 if (err) { 5924 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 5925 return (err); 5926 } 5927 #ifdef notyet 5928 if (cpuid > ctx->ifc_cpuid_highest) 5929 ctx->ifc_cpuid_highest = cpuid; 5930 #endif 5931 return (0); 5932 } 5933 5934 int 5935 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5936 iflib_intr_type_t type, driver_filter_t *filter, 5937 void *filter_arg, int qid, const char *name) 5938 { 5939 device_t dev; 5940 struct grouptask *gtask; 5941 struct taskqgroup *tqg; 5942 iflib_filter_info_t info; 5943 gtask_fn_t *fn; 5944 int tqrid, err; 5945 driver_filter_t *intr_fast; 5946 void *q; 5947 5948 info = &ctx->ifc_filter_info; 5949 tqrid = rid; 5950 5951 switch (type) { 5952 /* XXX merge tx/rx for netmap? */ 5953 case IFLIB_INTR_TX: 5954 q = &ctx->ifc_txqs[qid]; 5955 info = &ctx->ifc_txqs[qid].ift_filter_info; 5956 gtask = &ctx->ifc_txqs[qid].ift_task; 5957 tqg = qgroup_if_io_tqg; 5958 fn = _task_fn_tx; 5959 intr_fast = iflib_fast_intr; 5960 GROUPTASK_INIT(gtask, 0, fn, q); 5961 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5962 break; 5963 case IFLIB_INTR_RX: 5964 q = &ctx->ifc_rxqs[qid]; 5965 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5966 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5967 tqg = qgroup_if_io_tqg; 5968 fn = _task_fn_rx; 5969 intr_fast = iflib_fast_intr; 5970 GROUPTASK_INIT(gtask, 0, fn, q); 5971 break; 5972 case IFLIB_INTR_RXTX: 5973 q = &ctx->ifc_rxqs[qid]; 5974 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5975 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5976 tqg = qgroup_if_io_tqg; 5977 fn = _task_fn_rx; 5978 intr_fast = iflib_fast_intr_rxtx; 5979 GROUPTASK_INIT(gtask, 0, fn, q); 5980 break; 5981 case IFLIB_INTR_ADMIN: 5982 q = ctx; 5983 tqrid = -1; 5984 info = &ctx->ifc_filter_info; 5985 gtask = &ctx->ifc_admin_task; 5986 tqg = qgroup_if_config_tqg; 5987 fn = _task_fn_admin; 5988 intr_fast = iflib_fast_intr_ctx; 5989 break; 5990 default: 5991 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 5992 __func__); 5993 return (EINVAL); 5994 } 5995 5996 info->ifi_filter = filter; 5997 info->ifi_filter_arg = filter_arg; 5998 info->ifi_task = gtask; 5999 info->ifi_ctx = q; 6000 6001 dev = ctx->ifc_dev; 6002 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6003 if (err != 0) { 6004 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6005 return (err); 6006 } 6007 if (type == IFLIB_INTR_ADMIN) 6008 return (0); 6009 6010 if (tqrid != -1) { 6011 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6012 q, name); 6013 if (err) 6014 return (err); 6015 } else { 6016 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6017 } 6018 6019 return (0); 6020 } 6021 6022 void 6023 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6024 { 6025 struct grouptask *gtask; 6026 struct taskqgroup *tqg; 6027 gtask_fn_t *fn; 6028 void *q; 6029 int err; 6030 6031 switch (type) { 6032 case IFLIB_INTR_TX: 6033 q = &ctx->ifc_txqs[qid]; 6034 gtask = &ctx->ifc_txqs[qid].ift_task; 6035 tqg = qgroup_if_io_tqg; 6036 fn = _task_fn_tx; 6037 break; 6038 case IFLIB_INTR_RX: 6039 q = &ctx->ifc_rxqs[qid]; 6040 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6041 tqg = qgroup_if_io_tqg; 6042 fn = _task_fn_rx; 6043 break; 6044 case IFLIB_INTR_IOV: 6045 q = ctx; 6046 gtask = &ctx->ifc_vflr_task; 6047 tqg = qgroup_if_config_tqg; 6048 fn = _task_fn_iov; 6049 break; 6050 default: 6051 panic("unknown net intr type"); 6052 } 6053 GROUPTASK_INIT(gtask, 0, fn, q); 6054 if (irq != NULL) { 6055 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6056 q, name); 6057 if (err) 6058 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 6059 irq->ii_res, name); 6060 } else { 6061 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 6062 } 6063 } 6064 6065 void 6066 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6067 { 6068 6069 if (irq->ii_tag) 6070 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6071 6072 if (irq->ii_res) 6073 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6074 rman_get_rid(irq->ii_res), irq->ii_res); 6075 } 6076 6077 static int 6078 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6079 { 6080 iflib_txq_t txq = ctx->ifc_txqs; 6081 iflib_rxq_t rxq = ctx->ifc_rxqs; 6082 if_irq_t irq = &ctx->ifc_legacy_irq; 6083 iflib_filter_info_t info; 6084 device_t dev; 6085 struct grouptask *gtask; 6086 struct resource *res; 6087 struct taskqgroup *tqg; 6088 gtask_fn_t *fn; 6089 void *q; 6090 int err, tqrid; 6091 bool rx_only; 6092 6093 q = &ctx->ifc_rxqs[0]; 6094 info = &rxq[0].ifr_filter_info; 6095 gtask = &rxq[0].ifr_task; 6096 tqg = qgroup_if_io_tqg; 6097 tqrid = *rid; 6098 fn = _task_fn_rx; 6099 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6100 6101 ctx->ifc_flags |= IFC_LEGACY; 6102 info->ifi_filter = filter; 6103 info->ifi_filter_arg = filter_arg; 6104 info->ifi_task = gtask; 6105 info->ifi_ctx = rx_only ? ctx : q; 6106 6107 dev = ctx->ifc_dev; 6108 /* We allocate a single interrupt resource */ 6109 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6110 iflib_fast_intr_rxtx, NULL, info, name); 6111 if (err != 0) 6112 return (err); 6113 GROUPTASK_INIT(gtask, 0, fn, q); 6114 res = irq->ii_res; 6115 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6116 6117 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6118 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6119 "tx"); 6120 return (0); 6121 } 6122 6123 void 6124 iflib_led_create(if_ctx_t ctx) 6125 { 6126 6127 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6128 device_get_nameunit(ctx->ifc_dev)); 6129 } 6130 6131 void 6132 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6133 { 6134 6135 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6136 } 6137 6138 void 6139 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6140 { 6141 6142 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6143 } 6144 6145 void 6146 iflib_admin_intr_deferred(if_ctx_t ctx) 6147 { 6148 #ifdef INVARIANTS 6149 struct grouptask *gtask; 6150 6151 gtask = &ctx->ifc_admin_task; 6152 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 6153 #endif 6154 6155 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6156 } 6157 6158 void 6159 iflib_iov_intr_deferred(if_ctx_t ctx) 6160 { 6161 6162 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6163 } 6164 6165 void 6166 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6167 { 6168 6169 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6170 name); 6171 } 6172 6173 void 6174 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6175 const char *name) 6176 { 6177 6178 GROUPTASK_INIT(gtask, 0, fn, ctx); 6179 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6180 name); 6181 } 6182 6183 void 6184 iflib_config_gtask_deinit(struct grouptask *gtask) 6185 { 6186 6187 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6188 } 6189 6190 void 6191 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6192 { 6193 if_t ifp = ctx->ifc_ifp; 6194 iflib_txq_t txq = ctx->ifc_txqs; 6195 6196 if_setbaudrate(ifp, baudrate); 6197 if (baudrate >= IF_Gbps(10)) { 6198 STATE_LOCK(ctx); 6199 ctx->ifc_flags |= IFC_PREFETCH; 6200 STATE_UNLOCK(ctx); 6201 } 6202 /* If link down, disable watchdog */ 6203 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6204 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6205 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6206 } 6207 ctx->ifc_link_state = link_state; 6208 if_link_state_change(ifp, link_state); 6209 } 6210 6211 static int 6212 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6213 { 6214 int credits; 6215 #ifdef INVARIANTS 6216 int credits_pre = txq->ift_cidx_processed; 6217 #endif 6218 6219 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6220 BUS_DMASYNC_POSTREAD); 6221 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6222 return (0); 6223 6224 txq->ift_processed += credits; 6225 txq->ift_cidx_processed += credits; 6226 6227 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6228 if (txq->ift_cidx_processed >= txq->ift_size) 6229 txq->ift_cidx_processed -= txq->ift_size; 6230 return (credits); 6231 } 6232 6233 static int 6234 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6235 { 6236 iflib_fl_t fl; 6237 u_int i; 6238 6239 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6240 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6241 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6242 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6243 budget)); 6244 } 6245 6246 void 6247 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6248 const char *description, if_int_delay_info_t info, 6249 int offset, int value) 6250 { 6251 info->iidi_ctx = ctx; 6252 info->iidi_offset = offset; 6253 info->iidi_value = value; 6254 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6255 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6256 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 6257 info, 0, iflib_sysctl_int_delay, "I", description); 6258 } 6259 6260 struct sx * 6261 iflib_ctx_lock_get(if_ctx_t ctx) 6262 { 6263 6264 return (&ctx->ifc_ctx_sx); 6265 } 6266 6267 static int 6268 iflib_msix_init(if_ctx_t ctx) 6269 { 6270 device_t dev = ctx->ifc_dev; 6271 if_shared_ctx_t sctx = ctx->ifc_sctx; 6272 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6273 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6274 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6275 6276 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6277 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6278 6279 if (bootverbose) 6280 device_printf(dev, "msix_init qsets capped at %d\n", 6281 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6282 6283 /* Override by tuneable */ 6284 if (scctx->isc_disable_msix) 6285 goto msi; 6286 6287 /* First try MSI-X */ 6288 if ((msgs = pci_msix_count(dev)) == 0) { 6289 if (bootverbose) 6290 device_printf(dev, "MSI-X not supported or disabled\n"); 6291 goto msi; 6292 } 6293 6294 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6295 /* 6296 * bar == -1 => "trust me I know what I'm doing" 6297 * Some drivers are for hardware that is so shoddily 6298 * documented that no one knows which bars are which 6299 * so the developer has to map all bars. This hack 6300 * allows shoddy garbage to use MSI-X in this framework. 6301 */ 6302 if (bar != -1) { 6303 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6304 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6305 if (ctx->ifc_msix_mem == NULL) { 6306 device_printf(dev, "Unable to map MSI-X table\n"); 6307 goto msi; 6308 } 6309 } 6310 6311 admincnt = sctx->isc_admin_intrcnt; 6312 #if IFLIB_DEBUG 6313 /* use only 1 qset in debug mode */ 6314 queuemsgs = min(msgs - admincnt, 1); 6315 #else 6316 queuemsgs = msgs - admincnt; 6317 #endif 6318 #ifdef RSS 6319 queues = imin(queuemsgs, rss_getnumbuckets()); 6320 #else 6321 queues = queuemsgs; 6322 #endif 6323 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6324 if (bootverbose) 6325 device_printf(dev, 6326 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6327 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6328 #ifdef RSS 6329 /* If we're doing RSS, clamp at the number of RSS buckets */ 6330 if (queues > rss_getnumbuckets()) 6331 queues = rss_getnumbuckets(); 6332 #endif 6333 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6334 rx_queues = iflib_num_rx_queues; 6335 else 6336 rx_queues = queues; 6337 6338 if (rx_queues > scctx->isc_nrxqsets) 6339 rx_queues = scctx->isc_nrxqsets; 6340 6341 /* 6342 * We want this to be all logical CPUs by default 6343 */ 6344 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6345 tx_queues = iflib_num_tx_queues; 6346 else 6347 tx_queues = mp_ncpus; 6348 6349 if (tx_queues > scctx->isc_ntxqsets) 6350 tx_queues = scctx->isc_ntxqsets; 6351 6352 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6353 #ifdef INVARIANTS 6354 if (tx_queues != rx_queues) 6355 device_printf(dev, 6356 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6357 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6358 #endif 6359 tx_queues = min(rx_queues, tx_queues); 6360 rx_queues = min(rx_queues, tx_queues); 6361 } 6362 6363 vectors = rx_queues + admincnt; 6364 if (msgs < vectors) { 6365 device_printf(dev, 6366 "insufficient number of MSI-X vectors " 6367 "(supported %d, need %d)\n", msgs, vectors); 6368 goto msi; 6369 } 6370 6371 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6372 tx_queues); 6373 msgs = vectors; 6374 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6375 if (vectors != msgs) { 6376 device_printf(dev, 6377 "Unable to allocate sufficient MSI-X vectors " 6378 "(got %d, need %d)\n", vectors, msgs); 6379 pci_release_msi(dev); 6380 if (bar != -1) { 6381 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6382 ctx->ifc_msix_mem); 6383 ctx->ifc_msix_mem = NULL; 6384 } 6385 goto msi; 6386 } 6387 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6388 vectors); 6389 scctx->isc_vectors = vectors; 6390 scctx->isc_nrxqsets = rx_queues; 6391 scctx->isc_ntxqsets = tx_queues; 6392 scctx->isc_intr = IFLIB_INTR_MSIX; 6393 6394 return (vectors); 6395 } else { 6396 device_printf(dev, 6397 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6398 err); 6399 if (bar != -1) { 6400 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6401 ctx->ifc_msix_mem); 6402 ctx->ifc_msix_mem = NULL; 6403 } 6404 } 6405 6406 msi: 6407 vectors = pci_msi_count(dev); 6408 scctx->isc_nrxqsets = 1; 6409 scctx->isc_ntxqsets = 1; 6410 scctx->isc_vectors = vectors; 6411 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6412 device_printf(dev,"Using an MSI interrupt\n"); 6413 scctx->isc_intr = IFLIB_INTR_MSI; 6414 } else { 6415 scctx->isc_vectors = 1; 6416 device_printf(dev,"Using a Legacy interrupt\n"); 6417 scctx->isc_intr = IFLIB_INTR_LEGACY; 6418 } 6419 6420 return (vectors); 6421 } 6422 6423 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6424 6425 static int 6426 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6427 { 6428 int rc; 6429 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6430 struct sbuf *sb; 6431 const char *ring_state = "UNKNOWN"; 6432 6433 /* XXX needed ? */ 6434 rc = sysctl_wire_old_buffer(req, 0); 6435 MPASS(rc == 0); 6436 if (rc != 0) 6437 return (rc); 6438 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6439 MPASS(sb != NULL); 6440 if (sb == NULL) 6441 return (ENOMEM); 6442 if (state[3] <= 3) 6443 ring_state = ring_states[state[3]]; 6444 6445 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6446 state[0], state[1], state[2], ring_state); 6447 rc = sbuf_finish(sb); 6448 sbuf_delete(sb); 6449 return(rc); 6450 } 6451 6452 enum iflib_ndesc_handler { 6453 IFLIB_NTXD_HANDLER, 6454 IFLIB_NRXD_HANDLER, 6455 }; 6456 6457 static int 6458 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6459 { 6460 if_ctx_t ctx = (void *)arg1; 6461 enum iflib_ndesc_handler type = arg2; 6462 char buf[256] = {0}; 6463 qidx_t *ndesc; 6464 char *p, *next; 6465 int nqs, rc, i; 6466 6467 nqs = 8; 6468 switch(type) { 6469 case IFLIB_NTXD_HANDLER: 6470 ndesc = ctx->ifc_sysctl_ntxds; 6471 if (ctx->ifc_sctx) 6472 nqs = ctx->ifc_sctx->isc_ntxqs; 6473 break; 6474 case IFLIB_NRXD_HANDLER: 6475 ndesc = ctx->ifc_sysctl_nrxds; 6476 if (ctx->ifc_sctx) 6477 nqs = ctx->ifc_sctx->isc_nrxqs; 6478 break; 6479 default: 6480 printf("%s: unhandled type\n", __func__); 6481 return (EINVAL); 6482 } 6483 if (nqs == 0) 6484 nqs = 8; 6485 6486 for (i=0; i<8; i++) { 6487 if (i >= nqs) 6488 break; 6489 if (i) 6490 strcat(buf, ","); 6491 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6492 } 6493 6494 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6495 if (rc || req->newptr == NULL) 6496 return rc; 6497 6498 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6499 i++, p = strsep(&next, " ,")) { 6500 ndesc[i] = strtoul(p, NULL, 10); 6501 } 6502 6503 return(rc); 6504 } 6505 6506 #define NAME_BUFLEN 32 6507 static void 6508 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6509 { 6510 device_t dev = iflib_get_dev(ctx); 6511 struct sysctl_oid_list *child, *oid_list; 6512 struct sysctl_ctx_list *ctx_list; 6513 struct sysctl_oid *node; 6514 6515 ctx_list = device_get_sysctl_ctx(dev); 6516 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6517 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6518 CTLFLAG_RD, NULL, "IFLIB fields"); 6519 oid_list = SYSCTL_CHILDREN(node); 6520 6521 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6522 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6523 "driver version"); 6524 6525 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6526 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6527 "# of txqs to use, 0 => use default #"); 6528 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6529 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6530 "# of rxqs to use, 0 => use default #"); 6531 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6532 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6533 "permit #txq != #rxq"); 6534 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6535 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6536 "disable MSI-X (default 0)"); 6537 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6538 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6539 "set the RX budget"); 6540 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6541 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6542 "cause TX to abdicate instead of running to completion"); 6543 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6544 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6545 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6546 "offset to start using cores at"); 6547 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6548 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6549 "use separate cores for TX and RX"); 6550 6551 /* XXX change for per-queue sizes */ 6552 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6553 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6554 mp_ndesc_handler, "A", 6555 "list of # of TX descriptors to use, 0 = use default #"); 6556 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6557 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6558 mp_ndesc_handler, "A", 6559 "list of # of RX descriptors to use, 0 = use default #"); 6560 } 6561 6562 static void 6563 iflib_add_device_sysctl_post(if_ctx_t ctx) 6564 { 6565 if_shared_ctx_t sctx = ctx->ifc_sctx; 6566 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6567 device_t dev = iflib_get_dev(ctx); 6568 struct sysctl_oid_list *child; 6569 struct sysctl_ctx_list *ctx_list; 6570 iflib_fl_t fl; 6571 iflib_txq_t txq; 6572 iflib_rxq_t rxq; 6573 int i, j; 6574 char namebuf[NAME_BUFLEN]; 6575 char *qfmt; 6576 struct sysctl_oid *queue_node, *fl_node, *node; 6577 struct sysctl_oid_list *queue_list, *fl_list; 6578 ctx_list = device_get_sysctl_ctx(dev); 6579 6580 node = ctx->ifc_sysctl_node; 6581 child = SYSCTL_CHILDREN(node); 6582 6583 if (scctx->isc_ntxqsets > 100) 6584 qfmt = "txq%03d"; 6585 else if (scctx->isc_ntxqsets > 10) 6586 qfmt = "txq%02d"; 6587 else 6588 qfmt = "txq%d"; 6589 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6590 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6591 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6592 CTLFLAG_RD, NULL, "Queue Name"); 6593 queue_list = SYSCTL_CHILDREN(queue_node); 6594 #if MEMORY_LOGGING 6595 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6596 CTLFLAG_RD, 6597 &txq->ift_dequeued, "total mbufs freed"); 6598 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6599 CTLFLAG_RD, 6600 &txq->ift_enqueued, "total mbufs enqueued"); 6601 #endif 6602 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6603 CTLFLAG_RD, 6604 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6605 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6606 CTLFLAG_RD, 6607 &txq->ift_pullups, "# of times m_pullup was called"); 6608 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6609 CTLFLAG_RD, 6610 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6611 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6612 CTLFLAG_RD, 6613 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6614 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6615 CTLFLAG_RD, 6616 &txq->ift_map_failed, "# of times DMA map failed"); 6617 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6618 CTLFLAG_RD, 6619 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6620 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6621 CTLFLAG_RD, 6622 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6623 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6624 CTLFLAG_RD, 6625 &txq->ift_pidx, 1, "Producer Index"); 6626 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6627 CTLFLAG_RD, 6628 &txq->ift_cidx, 1, "Consumer Index"); 6629 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6630 CTLFLAG_RD, 6631 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6632 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6633 CTLFLAG_RD, 6634 &txq->ift_in_use, 1, "descriptors in use"); 6635 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6636 CTLFLAG_RD, 6637 &txq->ift_processed, "descriptors procesed for clean"); 6638 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6639 CTLFLAG_RD, 6640 &txq->ift_cleaned, "total cleaned"); 6641 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6642 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6643 0, mp_ring_state_handler, "A", "soft ring state"); 6644 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6645 CTLFLAG_RD, &txq->ift_br->enqueues, 6646 "# of enqueues to the mp_ring for this queue"); 6647 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6648 CTLFLAG_RD, &txq->ift_br->drops, 6649 "# of drops in the mp_ring for this queue"); 6650 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6651 CTLFLAG_RD, &txq->ift_br->starts, 6652 "# of normal consumer starts in the mp_ring for this queue"); 6653 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6654 CTLFLAG_RD, &txq->ift_br->stalls, 6655 "# of consumer stalls in the mp_ring for this queue"); 6656 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6657 CTLFLAG_RD, &txq->ift_br->restarts, 6658 "# of consumer restarts in the mp_ring for this queue"); 6659 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6660 CTLFLAG_RD, &txq->ift_br->abdications, 6661 "# of consumer abdications in the mp_ring for this queue"); 6662 } 6663 6664 if (scctx->isc_nrxqsets > 100) 6665 qfmt = "rxq%03d"; 6666 else if (scctx->isc_nrxqsets > 10) 6667 qfmt = "rxq%02d"; 6668 else 6669 qfmt = "rxq%d"; 6670 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6671 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6672 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6673 CTLFLAG_RD, NULL, "Queue Name"); 6674 queue_list = SYSCTL_CHILDREN(queue_node); 6675 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6676 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6677 CTLFLAG_RD, 6678 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6679 } 6680 6681 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6682 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6683 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6684 CTLFLAG_RD, NULL, "freelist Name"); 6685 fl_list = SYSCTL_CHILDREN(fl_node); 6686 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6687 CTLFLAG_RD, 6688 &fl->ifl_pidx, 1, "Producer Index"); 6689 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6690 CTLFLAG_RD, 6691 &fl->ifl_cidx, 1, "Consumer Index"); 6692 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6693 CTLFLAG_RD, 6694 &fl->ifl_credits, 1, "credits available"); 6695 #if MEMORY_LOGGING 6696 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6697 CTLFLAG_RD, 6698 &fl->ifl_m_enqueued, "mbufs allocated"); 6699 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6700 CTLFLAG_RD, 6701 &fl->ifl_m_dequeued, "mbufs freed"); 6702 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6703 CTLFLAG_RD, 6704 &fl->ifl_cl_enqueued, "clusters allocated"); 6705 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6706 CTLFLAG_RD, 6707 &fl->ifl_cl_dequeued, "clusters freed"); 6708 #endif 6709 6710 } 6711 } 6712 6713 } 6714 6715 void 6716 iflib_request_reset(if_ctx_t ctx) 6717 { 6718 6719 STATE_LOCK(ctx); 6720 ctx->ifc_flags |= IFC_DO_RESET; 6721 STATE_UNLOCK(ctx); 6722 } 6723 6724 #ifndef __NO_STRICT_ALIGNMENT 6725 static struct mbuf * 6726 iflib_fixup_rx(struct mbuf *m) 6727 { 6728 struct mbuf *n; 6729 6730 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6731 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6732 m->m_data += ETHER_HDR_LEN; 6733 n = m; 6734 } else { 6735 MGETHDR(n, M_NOWAIT, MT_DATA); 6736 if (n == NULL) { 6737 m_freem(m); 6738 return (NULL); 6739 } 6740 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6741 m->m_data += ETHER_HDR_LEN; 6742 m->m_len -= ETHER_HDR_LEN; 6743 n->m_len = ETHER_HDR_LEN; 6744 M_MOVE_PKTHDR(n, m); 6745 n->m_next = m; 6746 } 6747 return (n); 6748 } 6749 #endif 6750 6751 #ifdef DEBUGNET 6752 static void 6753 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6754 { 6755 if_ctx_t ctx; 6756 6757 ctx = if_getsoftc(ifp); 6758 CTX_LOCK(ctx); 6759 *nrxr = NRXQSETS(ctx); 6760 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6761 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6762 CTX_UNLOCK(ctx); 6763 } 6764 6765 static void 6766 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 6767 { 6768 if_ctx_t ctx; 6769 if_softc_ctx_t scctx; 6770 iflib_fl_t fl; 6771 iflib_rxq_t rxq; 6772 int i, j; 6773 6774 ctx = if_getsoftc(ifp); 6775 scctx = &ctx->ifc_softc_ctx; 6776 6777 switch (event) { 6778 case DEBUGNET_START: 6779 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6780 rxq = &ctx->ifc_rxqs[i]; 6781 for (j = 0; j < rxq->ifr_nfl; j++) { 6782 fl = rxq->ifr_fl; 6783 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6784 } 6785 } 6786 iflib_no_tx_batch = 1; 6787 break; 6788 default: 6789 break; 6790 } 6791 } 6792 6793 static int 6794 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 6795 { 6796 if_ctx_t ctx; 6797 iflib_txq_t txq; 6798 int error; 6799 6800 ctx = if_getsoftc(ifp); 6801 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6802 IFF_DRV_RUNNING) 6803 return (EBUSY); 6804 6805 txq = &ctx->ifc_txqs[0]; 6806 error = iflib_encap(txq, &m); 6807 if (error == 0) 6808 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6809 return (error); 6810 } 6811 6812 static int 6813 iflib_debugnet_poll(if_t ifp, int count) 6814 { 6815 if_ctx_t ctx; 6816 if_softc_ctx_t scctx; 6817 iflib_txq_t txq; 6818 int i; 6819 6820 ctx = if_getsoftc(ifp); 6821 scctx = &ctx->ifc_softc_ctx; 6822 6823 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6824 IFF_DRV_RUNNING) 6825 return (EBUSY); 6826 6827 txq = &ctx->ifc_txqs[0]; 6828 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6829 6830 for (i = 0; i < scctx->isc_nrxqsets; i++) 6831 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6832 return (0); 6833 } 6834 #endif /* DEBUGNET */ 6835