1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 /* 120 * File organization: 121 * - private structures 122 * - iflib private utility functions 123 * - ifnet functions 124 * - vlan registry and other exported functions 125 * - iflib public core functions 126 * 127 * 128 */ 129 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 130 131 #define IFLIB_RXEOF_MORE (1U << 0) 132 #define IFLIB_RXEOF_EMPTY (2U << 0) 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 146 typedef struct iflib_filter_info { 147 driver_filter_t *ifi_filter; 148 void *ifi_filter_arg; 149 struct grouptask *ifi_task; 150 void *ifi_ctx; 151 } *iflib_filter_info_t; 152 153 struct iflib_ctx { 154 KOBJ_FIELDS; 155 /* 156 * Pointer to hardware driver's softc 157 */ 158 void *ifc_softc; 159 device_t ifc_dev; 160 if_t ifc_ifp; 161 162 cpuset_t ifc_cpus; 163 if_shared_ctx_t ifc_sctx; 164 struct if_softc_ctx ifc_softc_ctx; 165 166 struct sx ifc_ctx_sx; 167 struct mtx ifc_state_mtx; 168 169 iflib_txq_t ifc_txqs; 170 iflib_rxq_t ifc_rxqs; 171 uint32_t ifc_if_flags; 172 uint32_t ifc_flags; 173 uint32_t ifc_max_fl_buf_size; 174 uint32_t ifc_rx_mbuf_sz; 175 176 int ifc_link_state; 177 int ifc_watchdog_events; 178 struct cdev *ifc_led_dev; 179 struct resource *ifc_msix_mem; 180 181 struct if_irq ifc_legacy_irq; 182 struct grouptask ifc_admin_task; 183 struct grouptask ifc_vflr_task; 184 struct iflib_filter_info ifc_filter_info; 185 struct ifmedia ifc_media; 186 struct ifmedia *ifc_mediap; 187 188 struct sysctl_oid *ifc_sysctl_node; 189 uint16_t ifc_sysctl_ntxqs; 190 uint16_t ifc_sysctl_nrxqs; 191 uint16_t ifc_sysctl_qs_eq_override; 192 uint16_t ifc_sysctl_rx_budget; 193 uint16_t ifc_sysctl_tx_abdicate; 194 uint16_t ifc_sysctl_core_offset; 195 #define CORE_OFFSET_UNSPECIFIED 0xffff 196 uint8_t ifc_sysctl_separate_txrx; 197 198 qidx_t ifc_sysctl_ntxds[8]; 199 qidx_t ifc_sysctl_nrxds[8]; 200 struct if_txrx ifc_txrx; 201 #define isc_txd_encap ifc_txrx.ift_txd_encap 202 #define isc_txd_flush ifc_txrx.ift_txd_flush 203 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 204 #define isc_rxd_available ifc_txrx.ift_rxd_available 205 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 207 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 209 eventhandler_tag ifc_vlan_attach_event; 210 eventhandler_tag ifc_vlan_detach_event; 211 struct ether_addr ifc_mac; 212 }; 213 214 void * 215 iflib_get_softc(if_ctx_t ctx) 216 { 217 218 return (ctx->ifc_softc); 219 } 220 221 device_t 222 iflib_get_dev(if_ctx_t ctx) 223 { 224 225 return (ctx->ifc_dev); 226 } 227 228 if_t 229 iflib_get_ifp(if_ctx_t ctx) 230 { 231 232 return (ctx->ifc_ifp); 233 } 234 235 struct ifmedia * 236 iflib_get_media(if_ctx_t ctx) 237 { 238 239 return (ctx->ifc_mediap); 240 } 241 242 uint32_t 243 iflib_get_flags(if_ctx_t ctx) 244 { 245 return (ctx->ifc_flags); 246 } 247 248 void 249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 250 { 251 252 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 253 } 254 255 if_softc_ctx_t 256 iflib_get_softc_ctx(if_ctx_t ctx) 257 { 258 259 return (&ctx->ifc_softc_ctx); 260 } 261 262 if_shared_ctx_t 263 iflib_get_sctx(if_ctx_t ctx) 264 { 265 266 return (ctx->ifc_sctx); 267 } 268 269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 272 273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 275 276 typedef struct iflib_sw_rx_desc_array { 277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 278 struct mbuf **ifsd_m; /* pkthdr mbufs */ 279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 281 } iflib_rxsd_array_t; 282 283 typedef struct iflib_sw_tx_desc_array { 284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 286 struct mbuf **ifsd_m; /* pkthdr mbufs */ 287 } if_txsd_vec_t; 288 289 /* magic number that should be high enough for any hardware */ 290 #define IFLIB_MAX_TX_SEGS 128 291 #define IFLIB_RX_COPY_THRESH 128 292 #define IFLIB_MAX_RX_REFRESH 32 293 /* The minimum descriptors per second before we start coalescing */ 294 #define IFLIB_MIN_DESC_SEC 16384 295 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 296 #define IFLIB_QUEUE_IDLE 0 297 #define IFLIB_QUEUE_HUNG 1 298 #define IFLIB_QUEUE_WORKING 2 299 /* maximum number of txqs that can share an rx interrupt */ 300 #define IFLIB_MAX_TX_SHARED_INTR 4 301 302 /* this should really scale with ring size - this is a fairly arbitrary value */ 303 #define TX_BATCH_SIZE 32 304 305 #define IFLIB_RESTART_BUDGET 8 306 307 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 308 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 309 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 310 311 struct iflib_txq { 312 qidx_t ift_in_use; 313 qidx_t ift_cidx; 314 qidx_t ift_cidx_processed; 315 qidx_t ift_pidx; 316 uint8_t ift_gen; 317 uint8_t ift_br_offset; 318 uint16_t ift_npending; 319 uint16_t ift_db_pending; 320 uint16_t ift_rs_pending; 321 /* implicit pad */ 322 uint8_t ift_txd_size[8]; 323 uint64_t ift_processed; 324 uint64_t ift_cleaned; 325 uint64_t ift_cleaned_prev; 326 #if MEMORY_LOGGING 327 uint64_t ift_enqueued; 328 uint64_t ift_dequeued; 329 #endif 330 uint64_t ift_no_tx_dma_setup; 331 uint64_t ift_no_desc_avail; 332 uint64_t ift_mbuf_defrag_failed; 333 uint64_t ift_mbuf_defrag; 334 uint64_t ift_map_failed; 335 uint64_t ift_txd_encap_efbig; 336 uint64_t ift_pullups; 337 uint64_t ift_last_timer_tick; 338 339 struct mtx ift_mtx; 340 struct mtx ift_db_mtx; 341 342 /* constant values */ 343 if_ctx_t ift_ctx; 344 struct ifmp_ring *ift_br; 345 struct grouptask ift_task; 346 qidx_t ift_size; 347 uint16_t ift_id; 348 struct callout ift_timer; 349 #ifdef DEV_NETMAP 350 struct callout ift_netmap_timer; 351 #endif /* DEV_NETMAP */ 352 353 if_txsd_vec_t ift_sds; 354 uint8_t ift_qstatus; 355 uint8_t ift_closed; 356 uint8_t ift_update_freq; 357 struct iflib_filter_info ift_filter_info; 358 bus_dma_tag_t ift_buf_tag; 359 bus_dma_tag_t ift_tso_buf_tag; 360 iflib_dma_info_t ift_ifdi; 361 #define MTX_NAME_LEN 32 362 char ift_mtx_name[MTX_NAME_LEN]; 363 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 364 #ifdef IFLIB_DIAGNOSTICS 365 uint64_t ift_cpu_exec_count[256]; 366 #endif 367 } __aligned(CACHE_LINE_SIZE); 368 369 struct iflib_fl { 370 qidx_t ifl_cidx; 371 qidx_t ifl_pidx; 372 qidx_t ifl_credits; 373 uint8_t ifl_gen; 374 uint8_t ifl_rxd_size; 375 #if MEMORY_LOGGING 376 uint64_t ifl_m_enqueued; 377 uint64_t ifl_m_dequeued; 378 uint64_t ifl_cl_enqueued; 379 uint64_t ifl_cl_dequeued; 380 #endif 381 /* implicit pad */ 382 bitstr_t *ifl_rx_bitmap; 383 qidx_t ifl_fragidx; 384 /* constant */ 385 qidx_t ifl_size; 386 uint16_t ifl_buf_size; 387 uint16_t ifl_cltype; 388 uma_zone_t ifl_zone; 389 iflib_rxsd_array_t ifl_sds; 390 iflib_rxq_t ifl_rxq; 391 uint8_t ifl_id; 392 bus_dma_tag_t ifl_buf_tag; 393 iflib_dma_info_t ifl_ifdi; 394 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 395 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 396 } __aligned(CACHE_LINE_SIZE); 397 398 static inline qidx_t 399 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 400 { 401 qidx_t used; 402 403 if (pidx > cidx) 404 used = pidx - cidx; 405 else if (pidx < cidx) 406 used = size - cidx + pidx; 407 else if (gen == 0 && pidx == cidx) 408 used = 0; 409 else if (gen == 1 && pidx == cidx) 410 used = size; 411 else 412 panic("bad state"); 413 414 return (used); 415 } 416 417 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 418 419 #define IDXDIFF(head, tail, wrap) \ 420 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 421 422 struct iflib_rxq { 423 if_ctx_t ifr_ctx; 424 iflib_fl_t ifr_fl; 425 uint64_t ifr_rx_irq; 426 struct pfil_head *pfil; 427 /* 428 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 429 * the completion queue consumer index. Otherwise it's unused. 430 */ 431 qidx_t ifr_cq_cidx; 432 uint16_t ifr_id; 433 uint8_t ifr_nfl; 434 uint8_t ifr_ntxqirq; 435 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 436 uint8_t ifr_fl_offset; 437 struct lro_ctrl ifr_lc; 438 struct grouptask ifr_task; 439 struct callout ifr_watchdog; 440 struct iflib_filter_info ifr_filter_info; 441 iflib_dma_info_t ifr_ifdi; 442 443 /* dynamically allocate if any drivers need a value substantially larger than this */ 444 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 445 #ifdef IFLIB_DIAGNOSTICS 446 uint64_t ifr_cpu_exec_count[256]; 447 #endif 448 } __aligned(CACHE_LINE_SIZE); 449 450 typedef struct if_rxsd { 451 caddr_t *ifsd_cl; 452 iflib_fl_t ifsd_fl; 453 } *if_rxsd_t; 454 455 /* multiple of word size */ 456 #ifdef __LP64__ 457 #define PKT_INFO_SIZE 6 458 #define RXD_INFO_SIZE 5 459 #define PKT_TYPE uint64_t 460 #else 461 #define PKT_INFO_SIZE 11 462 #define RXD_INFO_SIZE 8 463 #define PKT_TYPE uint32_t 464 #endif 465 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 466 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 467 468 typedef struct if_pkt_info_pad { 469 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 470 } *if_pkt_info_pad_t; 471 typedef struct if_rxd_info_pad { 472 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 473 } *if_rxd_info_pad_t; 474 475 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 476 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 477 478 static inline void 479 pkt_info_zero(if_pkt_info_t pi) 480 { 481 if_pkt_info_pad_t pi_pad; 482 483 pi_pad = (if_pkt_info_pad_t)pi; 484 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 485 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 486 #ifndef __LP64__ 487 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 488 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 489 #endif 490 } 491 492 static device_method_t iflib_pseudo_methods[] = { 493 DEVMETHOD(device_attach, noop_attach), 494 DEVMETHOD(device_detach, iflib_pseudo_detach), 495 DEVMETHOD_END 496 }; 497 498 driver_t iflib_pseudodriver = { 499 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 500 }; 501 502 static inline void 503 rxd_info_zero(if_rxd_info_t ri) 504 { 505 if_rxd_info_pad_t ri_pad; 506 int i; 507 508 ri_pad = (if_rxd_info_pad_t)ri; 509 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 510 ri_pad->rxd_val[i] = 0; 511 ri_pad->rxd_val[i+1] = 0; 512 ri_pad->rxd_val[i+2] = 0; 513 ri_pad->rxd_val[i+3] = 0; 514 } 515 #ifdef __LP64__ 516 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 517 #endif 518 } 519 520 /* 521 * Only allow a single packet to take up most 1/nth of the tx ring 522 */ 523 #define MAX_SINGLE_PACKET_FRACTION 12 524 #define IF_BAD_DMA (bus_addr_t)-1 525 526 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 527 528 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 529 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 530 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 531 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 532 533 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 534 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 535 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 536 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 537 538 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 539 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 540 541 void 542 iflib_set_detach(if_ctx_t ctx) 543 { 544 STATE_LOCK(ctx); 545 ctx->ifc_flags |= IFC_IN_DETACH; 546 STATE_UNLOCK(ctx); 547 } 548 549 /* Our boot-time initialization hook */ 550 static int iflib_module_event_handler(module_t, int, void *); 551 552 static moduledata_t iflib_moduledata = { 553 "iflib", 554 iflib_module_event_handler, 555 NULL 556 }; 557 558 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 559 MODULE_VERSION(iflib, 1); 560 561 MODULE_DEPEND(iflib, pci, 1, 1, 1); 562 MODULE_DEPEND(iflib, ether, 1, 1, 1); 563 564 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 565 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 566 567 #ifndef IFLIB_DEBUG_COUNTERS 568 #ifdef INVARIANTS 569 #define IFLIB_DEBUG_COUNTERS 1 570 #else 571 #define IFLIB_DEBUG_COUNTERS 0 572 #endif /* !INVARIANTS */ 573 #endif 574 575 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 576 "iflib driver parameters"); 577 578 /* 579 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 580 */ 581 static int iflib_min_tx_latency = 0; 582 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 583 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 584 static int iflib_no_tx_batch = 0; 585 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 586 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 587 588 #if IFLIB_DEBUG_COUNTERS 589 590 static int iflib_tx_seen; 591 static int iflib_tx_sent; 592 static int iflib_tx_encap; 593 static int iflib_rx_allocs; 594 static int iflib_fl_refills; 595 static int iflib_fl_refills_large; 596 static int iflib_tx_frees; 597 598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 599 &iflib_tx_seen, 0, "# TX mbufs seen"); 600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 601 &iflib_tx_sent, 0, "# TX mbufs sent"); 602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 603 &iflib_tx_encap, 0, "# TX mbufs encapped"); 604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 605 &iflib_tx_frees, 0, "# TX frees"); 606 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 607 &iflib_rx_allocs, 0, "# RX allocations"); 608 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 609 &iflib_fl_refills, 0, "# refills"); 610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 611 &iflib_fl_refills_large, 0, "# large refills"); 612 613 static int iflib_txq_drain_flushing; 614 static int iflib_txq_drain_oactive; 615 static int iflib_txq_drain_notready; 616 617 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 618 &iflib_txq_drain_flushing, 0, "# drain flushes"); 619 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 620 &iflib_txq_drain_oactive, 0, "# drain oactives"); 621 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 622 &iflib_txq_drain_notready, 0, "# drain notready"); 623 624 static int iflib_encap_load_mbuf_fail; 625 static int iflib_encap_pad_mbuf_fail; 626 static int iflib_encap_txq_avail_fail; 627 static int iflib_encap_txd_encap_fail; 628 629 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 630 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 632 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 634 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 636 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 637 638 static int iflib_task_fn_rxs; 639 static int iflib_rx_intr_enables; 640 static int iflib_fast_intrs; 641 static int iflib_rx_unavail; 642 static int iflib_rx_ctx_inactive; 643 static int iflib_rx_if_input; 644 static int iflib_rxd_flush; 645 646 static int iflib_verbose_debug; 647 648 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 649 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 650 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 651 &iflib_rx_intr_enables, 0, "# RX intr enables"); 652 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 653 &iflib_fast_intrs, 0, "# fast_intr calls"); 654 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 655 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 657 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 659 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 661 &iflib_rxd_flush, 0, "# times rxd_flush called"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 663 &iflib_verbose_debug, 0, "enable verbose debugging"); 664 665 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 666 static void 667 iflib_debug_reset(void) 668 { 669 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 670 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 671 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 672 iflib_txq_drain_notready = 673 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 674 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 675 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 676 iflib_rx_unavail = 677 iflib_rx_ctx_inactive = iflib_rx_if_input = 678 iflib_rxd_flush = 0; 679 } 680 681 #else 682 #define DBG_COUNTER_INC(name) 683 static void iflib_debug_reset(void) {} 684 #endif 685 686 #define IFLIB_DEBUG 0 687 688 static void iflib_tx_structures_free(if_ctx_t ctx); 689 static void iflib_rx_structures_free(if_ctx_t ctx); 690 static int iflib_queues_alloc(if_ctx_t ctx); 691 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 692 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 693 static int iflib_qset_structures_setup(if_ctx_t ctx); 694 static int iflib_msix_init(if_ctx_t ctx); 695 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 696 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 697 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 698 #ifdef ALTQ 699 static void iflib_altq_if_start(if_t ifp); 700 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 701 #endif 702 static int iflib_register(if_ctx_t); 703 static void iflib_deregister(if_ctx_t); 704 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 705 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 706 static void iflib_init_locked(if_ctx_t ctx); 707 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 708 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 709 static void iflib_ifmp_purge(iflib_txq_t txq); 710 static void _iflib_pre_assert(if_softc_ctx_t scctx); 711 static void iflib_if_init_locked(if_ctx_t ctx); 712 static void iflib_free_intr_mem(if_ctx_t ctx); 713 #ifndef __NO_STRICT_ALIGNMENT 714 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 715 #endif 716 717 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 718 SLIST_HEAD_INITIALIZER(cpu_offsets); 719 struct cpu_offset { 720 SLIST_ENTRY(cpu_offset) entries; 721 cpuset_t set; 722 unsigned int refcount; 723 uint16_t offset; 724 }; 725 static struct mtx cpu_offset_mtx; 726 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 727 MTX_DEF); 728 729 DEBUGNET_DEFINE(iflib); 730 731 static int 732 iflib_num_rx_descs(if_ctx_t ctx) 733 { 734 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 735 if_shared_ctx_t sctx = ctx->ifc_sctx; 736 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 737 738 return scctx->isc_nrxd[first_rxq]; 739 } 740 741 static int 742 iflib_num_tx_descs(if_ctx_t ctx) 743 { 744 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 745 if_shared_ctx_t sctx = ctx->ifc_sctx; 746 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 747 748 return scctx->isc_ntxd[first_txq]; 749 } 750 751 #ifdef DEV_NETMAP 752 #include <sys/selinfo.h> 753 #include <net/netmap.h> 754 #include <dev/netmap/netmap_kern.h> 755 756 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 757 758 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 759 static void iflib_netmap_timer(void *arg); 760 761 /* 762 * device-specific sysctl variables: 763 * 764 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 765 * During regular operations the CRC is stripped, but on some 766 * hardware reception of frames not multiple of 64 is slower, 767 * so using crcstrip=0 helps in benchmarks. 768 * 769 * iflib_rx_miss, iflib_rx_miss_bufs: 770 * count packets that might be missed due to lost interrupts. 771 */ 772 SYSCTL_DECL(_dev_netmap); 773 /* 774 * The xl driver by default strips CRCs and we do not override it. 775 */ 776 777 int iflib_crcstrip = 1; 778 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 779 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 780 781 int iflib_rx_miss, iflib_rx_miss_bufs; 782 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 783 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 784 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 785 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 786 787 /* 788 * Register/unregister. We are already under netmap lock. 789 * Only called on the first register or the last unregister. 790 */ 791 static int 792 iflib_netmap_register(struct netmap_adapter *na, int onoff) 793 { 794 if_t ifp = na->ifp; 795 if_ctx_t ctx = ifp->if_softc; 796 int status; 797 798 CTX_LOCK(ctx); 799 IFDI_INTR_DISABLE(ctx); 800 801 /* Tell the stack that the interface is no longer active */ 802 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 803 804 if (!CTX_IS_VF(ctx)) 805 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 806 807 iflib_stop(ctx); 808 809 /* 810 * Enable (or disable) netmap flags, and intercept (or restore) 811 * ifp->if_transmit. This is done once the device has been stopped 812 * to prevent race conditions. 813 */ 814 if (onoff) { 815 nm_set_native_flags(na); 816 } else { 817 nm_clear_native_flags(na); 818 } 819 820 iflib_init_locked(ctx); 821 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 822 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 823 if (status) 824 nm_clear_native_flags(na); 825 CTX_UNLOCK(ctx); 826 return (status); 827 } 828 829 static int 830 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 831 { 832 struct netmap_adapter *na = kring->na; 833 u_int const lim = kring->nkr_num_slots - 1; 834 u_int nm_i = kring->nr_hwcur; 835 struct netmap_ring *ring = kring->ring; 836 bus_dmamap_t *map; 837 struct if_rxd_update iru; 838 if_ctx_t ctx = rxq->ifr_ctx; 839 iflib_fl_t fl = &rxq->ifr_fl[0]; 840 u_int nic_i_first, nic_i; 841 int i, n; 842 #if IFLIB_DEBUG_COUNTERS 843 int rf_count = 0; 844 #endif 845 846 /* 847 * This function is used both at initialization and in rxsync. 848 * At initialization we need to prepare (with isc_rxd_refill()) 849 * all the (N) netmap buffers in the ring, in such a way to keep 850 * fl->ifl_pidx and kring->nr_hwcur in sync (except for 851 * kring->nkr_hwofs); at rxsync time, both indexes point to the 852 * next buffer to be refilled. 853 * In any case we publish (with isc_rxd_flush()) up to 854 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 855 * pointer to overrun the head/cons pointer, although this is 856 * not necessary for some NICs (e.g. vmx). 857 */ 858 if (__predict_false(init)) 859 n = kring->nkr_num_slots; 860 else { 861 n = kring->rhead - nm_i; 862 if (n == 0) 863 return (0); /* Nothing to do. */ 864 if (n < 0) 865 n += kring->nkr_num_slots; 866 } 867 868 /* Start to refill from nr_hwcur, publishing n buffers. */ 869 iru_init(&iru, rxq, 0 /* flid */); 870 map = fl->ifl_sds.ifsd_map; 871 nic_i = fl->ifl_pidx; 872 MPASS(nic_i == netmap_idx_k2n(kring, nm_i)); 873 DBG_COUNTER_INC(fl_refills); 874 while (n > 0) { 875 #if IFLIB_DEBUG_COUNTERS 876 if (++rf_count == 9) 877 DBG_COUNTER_INC(fl_refills_large); 878 #endif 879 nic_i_first = nic_i; 880 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 881 struct netmap_slot *slot = &ring->slot[nm_i]; 882 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]); 883 884 MPASS(i < IFLIB_MAX_RX_REFRESH); 885 886 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 887 return netmap_ring_reinit(kring); 888 889 fl->ifl_rxd_idxs[i] = nic_i; 890 891 if (__predict_false(init)) { 892 netmap_load_map(na, fl->ifl_buf_tag, 893 map[nic_i], addr); 894 } else if (slot->flags & NS_BUF_CHANGED) { 895 /* buffer has changed, reload map */ 896 netmap_reload_map(na, fl->ifl_buf_tag, 897 map[nic_i], addr); 898 } 899 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 900 BUS_DMASYNC_PREREAD); 901 slot->flags &= ~NS_BUF_CHANGED; 902 903 nm_i = nm_next(nm_i, lim); 904 nic_i = nm_next(nic_i, lim); 905 } 906 907 iru.iru_pidx = nic_i_first; 908 iru.iru_count = i; 909 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 910 } 911 fl->ifl_pidx = nic_i; 912 MPASS(!init || nm_i == 0); 913 MPASS(nm_i == kring->rhead); 914 kring->nr_hwcur = nm_i; 915 916 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 917 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 918 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 919 nm_prev(nic_i, lim)); 920 DBG_COUNTER_INC(rxd_flush); 921 922 return (0); 923 } 924 925 #define NETMAP_TX_TIMER_US 90 926 927 /* 928 * Reconcile kernel and user view of the transmit ring. 929 * 930 * All information is in the kring. 931 * Userspace wants to send packets up to the one before kring->rhead, 932 * kernel knows kring->nr_hwcur is the first unsent packet. 933 * 934 * Here we push packets out (as many as possible), and possibly 935 * reclaim buffers from previously completed transmission. 936 * 937 * The caller (netmap) guarantees that there is only one instance 938 * running at any time. Any interference with other driver 939 * methods should be handled by the individual drivers. 940 */ 941 static int 942 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 943 { 944 struct netmap_adapter *na = kring->na; 945 if_t ifp = na->ifp; 946 struct netmap_ring *ring = kring->ring; 947 u_int nm_i; /* index into the netmap kring */ 948 u_int nic_i; /* index into the NIC ring */ 949 u_int n; 950 u_int const lim = kring->nkr_num_slots - 1; 951 u_int const head = kring->rhead; 952 struct if_pkt_info pi; 953 954 /* 955 * interrupts on every tx packet are expensive so request 956 * them every half ring, or where NS_REPORT is set 957 */ 958 u_int report_frequency = kring->nkr_num_slots >> 1; 959 /* device-specific */ 960 if_ctx_t ctx = ifp->if_softc; 961 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 962 963 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 964 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 965 966 /* 967 * First part: process new packets to send. 968 * nm_i is the current index in the netmap kring, 969 * nic_i is the corresponding index in the NIC ring. 970 * 971 * If we have packets to send (nm_i != head) 972 * iterate over the netmap ring, fetch length and update 973 * the corresponding slot in the NIC ring. Some drivers also 974 * need to update the buffer's physical address in the NIC slot 975 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 976 * 977 * The netmap_reload_map() calls is especially expensive, 978 * even when (as in this case) the tag is 0, so do only 979 * when the buffer has actually changed. 980 * 981 * If possible do not set the report/intr bit on all slots, 982 * but only a few times per ring or when NS_REPORT is set. 983 * 984 * Finally, on 10G and faster drivers, it might be useful 985 * to prefetch the next slot and txr entry. 986 */ 987 988 nm_i = kring->nr_hwcur; 989 if (nm_i != head) { /* we have new packets to send */ 990 pkt_info_zero(&pi); 991 pi.ipi_segs = txq->ift_segs; 992 pi.ipi_qsidx = kring->ring_id; 993 nic_i = netmap_idx_k2n(kring, nm_i); 994 995 __builtin_prefetch(&ring->slot[nm_i]); 996 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 997 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 998 999 for (n = 0; nm_i != head; n++) { 1000 struct netmap_slot *slot = &ring->slot[nm_i]; 1001 u_int len = slot->len; 1002 uint64_t paddr; 1003 void *addr = PNMB(na, slot, &paddr); 1004 int flags = (slot->flags & NS_REPORT || 1005 nic_i == 0 || nic_i == report_frequency) ? 1006 IPI_TX_INTR : 0; 1007 1008 /* device-specific */ 1009 pi.ipi_len = len; 1010 pi.ipi_segs[0].ds_addr = paddr; 1011 pi.ipi_segs[0].ds_len = len; 1012 pi.ipi_nsegs = 1; 1013 pi.ipi_ndescs = 0; 1014 pi.ipi_pidx = nic_i; 1015 pi.ipi_flags = flags; 1016 1017 /* Fill the slot in the NIC ring. */ 1018 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1019 DBG_COUNTER_INC(tx_encap); 1020 1021 /* prefetch for next round */ 1022 __builtin_prefetch(&ring->slot[nm_i + 1]); 1023 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1024 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1025 1026 NM_CHECK_ADDR_LEN(na, addr, len); 1027 1028 if (slot->flags & NS_BUF_CHANGED) { 1029 /* buffer has changed, reload map */ 1030 netmap_reload_map(na, txq->ift_buf_tag, 1031 txq->ift_sds.ifsd_map[nic_i], addr); 1032 } 1033 /* make sure changes to the buffer are synced */ 1034 bus_dmamap_sync(txq->ift_buf_tag, 1035 txq->ift_sds.ifsd_map[nic_i], 1036 BUS_DMASYNC_PREWRITE); 1037 1038 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1039 nm_i = nm_next(nm_i, lim); 1040 nic_i = nm_next(nic_i, lim); 1041 } 1042 kring->nr_hwcur = nm_i; 1043 1044 /* synchronize the NIC ring */ 1045 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1046 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1047 1048 /* (re)start the tx unit up to slot nic_i (excluded) */ 1049 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1050 } 1051 1052 /* 1053 * Second part: reclaim buffers for completed transmissions. 1054 * 1055 * If there are unclaimed buffers, attempt to reclaim them. 1056 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1057 * trigger a per-tx-queue timer to try again later. 1058 */ 1059 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1060 if (iflib_tx_credits_update(ctx, txq)) { 1061 /* some tx completed, increment avail */ 1062 nic_i = txq->ift_cidx_processed; 1063 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1064 } 1065 } 1066 1067 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1068 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1069 callout_reset_sbt(&txq->ift_netmap_timer, 1070 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1071 iflib_netmap_timer, txq, txq->ift_netmap_timer.c_cpu); 1072 } 1073 return (0); 1074 } 1075 1076 /* 1077 * Reconcile kernel and user view of the receive ring. 1078 * Same as for the txsync, this routine must be efficient. 1079 * The caller guarantees a single invocations, but races against 1080 * the rest of the driver should be handled here. 1081 * 1082 * On call, kring->rhead is the first packet that userspace wants 1083 * to keep, and kring->rcur is the wakeup point. 1084 * The kernel has previously reported packets up to kring->rtail. 1085 * 1086 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1087 * of whether or not we received an interrupt. 1088 */ 1089 static int 1090 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1091 { 1092 struct netmap_adapter *na = kring->na; 1093 struct netmap_ring *ring = kring->ring; 1094 if_t ifp = na->ifp; 1095 uint32_t nm_i; /* index into the netmap ring */ 1096 uint32_t nic_i; /* index into the NIC ring */ 1097 u_int n; 1098 u_int const lim = kring->nkr_num_slots - 1; 1099 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1100 1101 if_ctx_t ctx = ifp->if_softc; 1102 if_shared_ctx_t sctx = ctx->ifc_sctx; 1103 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1104 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1105 iflib_fl_t fl = &rxq->ifr_fl[0]; 1106 struct if_rxd_info ri; 1107 qidx_t *cidxp; 1108 1109 /* 1110 * netmap only uses free list 0, to avoid out of order consumption 1111 * of receive buffers 1112 */ 1113 1114 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1115 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1116 1117 /* 1118 * First part: import newly received packets. 1119 * 1120 * nm_i is the index of the next free slot in the netmap ring, 1121 * nic_i is the index of the next received packet in the NIC ring 1122 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1123 * differ in case if_init() has been called while 1124 * in netmap mode. For the receive ring we have 1125 * 1126 * nic_i = fl->ifl_cidx; 1127 * nm_i = kring->nr_hwtail (previous) 1128 * and 1129 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1130 * 1131 * fl->ifl_cidx is set to 0 on a ring reinit 1132 */ 1133 if (netmap_no_pendintr || force_update) { 1134 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1135 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1136 int crclen = iflib_crcstrip ? 0 : 4; 1137 int error, avail; 1138 1139 /* 1140 * For the free list consumer index, we use the same 1141 * logic as in iflib_rxeof(). 1142 */ 1143 if (have_rxcq) 1144 cidxp = &rxq->ifr_cq_cidx; 1145 else 1146 cidxp = &fl->ifl_cidx; 1147 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1148 rxq->ifr_id, *cidxp, USHRT_MAX); 1149 1150 nic_i = fl->ifl_cidx; 1151 nm_i = netmap_idx_n2k(kring, nic_i); 1152 MPASS(nm_i == kring->nr_hwtail); 1153 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1154 rxd_info_zero(&ri); 1155 ri.iri_frags = rxq->ifr_frags; 1156 ri.iri_qsidx = kring->ring_id; 1157 ri.iri_ifp = ctx->ifc_ifp; 1158 ri.iri_cidx = *cidxp; 1159 1160 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1161 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1162 ring->slot[nm_i].flags = 0; 1163 if (have_rxcq) { 1164 *cidxp = ri.iri_cidx; 1165 while (*cidxp >= scctx->isc_nrxd[0]) 1166 *cidxp -= scctx->isc_nrxd[0]; 1167 } 1168 bus_dmamap_sync(fl->ifl_buf_tag, 1169 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1170 nm_i = nm_next(nm_i, lim); 1171 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1172 } 1173 if (n) { /* update the state variables */ 1174 if (netmap_no_pendintr && !force_update) { 1175 /* diagnostics */ 1176 iflib_rx_miss ++; 1177 iflib_rx_miss_bufs += n; 1178 } 1179 kring->nr_hwtail = nm_i; 1180 } 1181 kring->nr_kflags &= ~NKR_PENDINTR; 1182 } 1183 /* 1184 * Second part: skip past packets that userspace has released. 1185 * (kring->nr_hwcur to head excluded), 1186 * and make the buffers available for reception. 1187 * As usual nm_i is the index in the netmap ring, 1188 * nic_i is the index in the NIC ring, and 1189 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1190 */ 1191 netmap_fl_refill(rxq, kring, false); 1192 1193 return (0); 1194 } 1195 1196 static void 1197 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1198 { 1199 if_ctx_t ctx = na->ifp->if_softc; 1200 1201 CTX_LOCK(ctx); 1202 if (onoff) { 1203 IFDI_INTR_ENABLE(ctx); 1204 } else { 1205 IFDI_INTR_DISABLE(ctx); 1206 } 1207 CTX_UNLOCK(ctx); 1208 } 1209 1210 static int 1211 iflib_netmap_attach(if_ctx_t ctx) 1212 { 1213 struct netmap_adapter na; 1214 1215 bzero(&na, sizeof(na)); 1216 1217 na.ifp = ctx->ifc_ifp; 1218 na.na_flags = NAF_BDG_MAYSLEEP; 1219 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1220 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1221 1222 na.num_tx_desc = iflib_num_tx_descs(ctx); 1223 na.num_rx_desc = iflib_num_rx_descs(ctx); 1224 na.nm_txsync = iflib_netmap_txsync; 1225 na.nm_rxsync = iflib_netmap_rxsync; 1226 na.nm_register = iflib_netmap_register; 1227 na.nm_intr = iflib_netmap_intr; 1228 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1229 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1230 return (netmap_attach(&na)); 1231 } 1232 1233 static int 1234 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1235 { 1236 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1237 struct netmap_slot *slot; 1238 1239 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1240 if (slot == NULL) 1241 return (0); 1242 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1243 /* 1244 * In netmap mode, set the map for the packet buffer. 1245 * NOTE: Some drivers (not this one) also need to set 1246 * the physical buffer address in the NIC ring. 1247 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1248 * netmap slot index, si 1249 */ 1250 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1251 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1252 NMB(na, slot + si)); 1253 } 1254 return (1); 1255 } 1256 1257 static int 1258 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1259 { 1260 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1261 struct netmap_kring *kring; 1262 struct netmap_slot *slot; 1263 1264 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1265 if (slot == NULL) 1266 return (0); 1267 kring = na->rx_rings[rxq->ifr_id]; 1268 netmap_fl_refill(rxq, kring, true); 1269 return (1); 1270 } 1271 1272 static void 1273 iflib_netmap_timer(void *arg) 1274 { 1275 iflib_txq_t txq = arg; 1276 if_ctx_t ctx = txq->ift_ctx; 1277 1278 /* 1279 * Wake up the netmap application, to give it a chance to 1280 * call txsync and reclaim more completed TX buffers. 1281 */ 1282 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1283 } 1284 1285 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1286 1287 #else 1288 #define iflib_netmap_txq_init(ctx, txq) (0) 1289 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1290 #define iflib_netmap_detach(ifp) 1291 1292 #define iflib_netmap_attach(ctx) (0) 1293 #define netmap_rx_irq(ifp, qid, budget) (0) 1294 #endif 1295 1296 #if defined(__i386__) || defined(__amd64__) 1297 static __inline void 1298 prefetch(void *x) 1299 { 1300 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1301 } 1302 static __inline void 1303 prefetch2cachelines(void *x) 1304 { 1305 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1306 #if (CACHE_LINE_SIZE < 128) 1307 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1308 #endif 1309 } 1310 #else 1311 #define prefetch(x) 1312 #define prefetch2cachelines(x) 1313 #endif 1314 1315 static void 1316 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1317 { 1318 iflib_fl_t fl; 1319 1320 fl = &rxq->ifr_fl[flid]; 1321 iru->iru_paddrs = fl->ifl_bus_addrs; 1322 iru->iru_idxs = fl->ifl_rxd_idxs; 1323 iru->iru_qsidx = rxq->ifr_id; 1324 iru->iru_buf_size = fl->ifl_buf_size; 1325 iru->iru_flidx = fl->ifl_id; 1326 } 1327 1328 static void 1329 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1330 { 1331 if (err) 1332 return; 1333 *(bus_addr_t *) arg = segs[0].ds_addr; 1334 } 1335 1336 int 1337 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1338 { 1339 int err; 1340 device_t dev = ctx->ifc_dev; 1341 1342 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1343 align, 0, /* alignment, bounds */ 1344 BUS_SPACE_MAXADDR, /* lowaddr */ 1345 BUS_SPACE_MAXADDR, /* highaddr */ 1346 NULL, NULL, /* filter, filterarg */ 1347 size, /* maxsize */ 1348 1, /* nsegments */ 1349 size, /* maxsegsize */ 1350 BUS_DMA_ALLOCNOW, /* flags */ 1351 NULL, /* lockfunc */ 1352 NULL, /* lockarg */ 1353 &dma->idi_tag); 1354 if (err) { 1355 device_printf(dev, 1356 "%s: bus_dma_tag_create failed: %d\n", 1357 __func__, err); 1358 goto fail_0; 1359 } 1360 1361 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1362 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1363 if (err) { 1364 device_printf(dev, 1365 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1366 __func__, (uintmax_t)size, err); 1367 goto fail_1; 1368 } 1369 1370 dma->idi_paddr = IF_BAD_DMA; 1371 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1372 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1373 if (err || dma->idi_paddr == IF_BAD_DMA) { 1374 device_printf(dev, 1375 "%s: bus_dmamap_load failed: %d\n", 1376 __func__, err); 1377 goto fail_2; 1378 } 1379 1380 dma->idi_size = size; 1381 return (0); 1382 1383 fail_2: 1384 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1385 fail_1: 1386 bus_dma_tag_destroy(dma->idi_tag); 1387 fail_0: 1388 dma->idi_tag = NULL; 1389 1390 return (err); 1391 } 1392 1393 int 1394 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1395 { 1396 if_shared_ctx_t sctx = ctx->ifc_sctx; 1397 1398 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1399 1400 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1401 } 1402 1403 int 1404 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1405 { 1406 int i, err; 1407 iflib_dma_info_t *dmaiter; 1408 1409 dmaiter = dmalist; 1410 for (i = 0; i < count; i++, dmaiter++) { 1411 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1412 break; 1413 } 1414 if (err) 1415 iflib_dma_free_multi(dmalist, i); 1416 return (err); 1417 } 1418 1419 void 1420 iflib_dma_free(iflib_dma_info_t dma) 1421 { 1422 if (dma->idi_tag == NULL) 1423 return; 1424 if (dma->idi_paddr != IF_BAD_DMA) { 1425 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1426 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1427 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1428 dma->idi_paddr = IF_BAD_DMA; 1429 } 1430 if (dma->idi_vaddr != NULL) { 1431 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1432 dma->idi_vaddr = NULL; 1433 } 1434 bus_dma_tag_destroy(dma->idi_tag); 1435 dma->idi_tag = NULL; 1436 } 1437 1438 void 1439 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1440 { 1441 int i; 1442 iflib_dma_info_t *dmaiter = dmalist; 1443 1444 for (i = 0; i < count; i++, dmaiter++) 1445 iflib_dma_free(*dmaiter); 1446 } 1447 1448 static int 1449 iflib_fast_intr(void *arg) 1450 { 1451 iflib_filter_info_t info = arg; 1452 struct grouptask *gtask = info->ifi_task; 1453 int result; 1454 1455 DBG_COUNTER_INC(fast_intrs); 1456 if (info->ifi_filter != NULL) { 1457 result = info->ifi_filter(info->ifi_filter_arg); 1458 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1459 return (result); 1460 } 1461 1462 GROUPTASK_ENQUEUE(gtask); 1463 return (FILTER_HANDLED); 1464 } 1465 1466 static int 1467 iflib_fast_intr_rxtx(void *arg) 1468 { 1469 iflib_filter_info_t info = arg; 1470 struct grouptask *gtask = info->ifi_task; 1471 if_ctx_t ctx; 1472 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1473 iflib_txq_t txq; 1474 void *sc; 1475 int i, cidx, result; 1476 qidx_t txqid; 1477 bool intr_enable, intr_legacy; 1478 1479 DBG_COUNTER_INC(fast_intrs); 1480 if (info->ifi_filter != NULL) { 1481 result = info->ifi_filter(info->ifi_filter_arg); 1482 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1483 return (result); 1484 } 1485 1486 ctx = rxq->ifr_ctx; 1487 sc = ctx->ifc_softc; 1488 intr_enable = false; 1489 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1490 MPASS(rxq->ifr_ntxqirq); 1491 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1492 txqid = rxq->ifr_txqid[i]; 1493 txq = &ctx->ifc_txqs[txqid]; 1494 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1495 BUS_DMASYNC_POSTREAD); 1496 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1497 if (intr_legacy) 1498 intr_enable = true; 1499 else 1500 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1501 continue; 1502 } 1503 GROUPTASK_ENQUEUE(&txq->ift_task); 1504 } 1505 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1506 cidx = rxq->ifr_cq_cidx; 1507 else 1508 cidx = rxq->ifr_fl[0].ifl_cidx; 1509 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1510 GROUPTASK_ENQUEUE(gtask); 1511 else { 1512 if (intr_legacy) 1513 intr_enable = true; 1514 else 1515 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1516 DBG_COUNTER_INC(rx_intr_enables); 1517 } 1518 if (intr_enable) 1519 IFDI_INTR_ENABLE(ctx); 1520 return (FILTER_HANDLED); 1521 } 1522 1523 static int 1524 iflib_fast_intr_ctx(void *arg) 1525 { 1526 iflib_filter_info_t info = arg; 1527 struct grouptask *gtask = info->ifi_task; 1528 int result; 1529 1530 DBG_COUNTER_INC(fast_intrs); 1531 if (info->ifi_filter != NULL) { 1532 result = info->ifi_filter(info->ifi_filter_arg); 1533 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1534 return (result); 1535 } 1536 1537 GROUPTASK_ENQUEUE(gtask); 1538 return (FILTER_HANDLED); 1539 } 1540 1541 static int 1542 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1543 driver_filter_t filter, driver_intr_t handler, void *arg, 1544 const char *name) 1545 { 1546 struct resource *res; 1547 void *tag = NULL; 1548 device_t dev = ctx->ifc_dev; 1549 int flags, i, rc; 1550 1551 flags = RF_ACTIVE; 1552 if (ctx->ifc_flags & IFC_LEGACY) 1553 flags |= RF_SHAREABLE; 1554 MPASS(rid < 512); 1555 i = rid; 1556 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1557 if (res == NULL) { 1558 device_printf(dev, 1559 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1560 return (ENOMEM); 1561 } 1562 irq->ii_res = res; 1563 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1564 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1565 filter, handler, arg, &tag); 1566 if (rc != 0) { 1567 device_printf(dev, 1568 "failed to setup interrupt for rid %d, name %s: %d\n", 1569 rid, name ? name : "unknown", rc); 1570 return (rc); 1571 } else if (name) 1572 bus_describe_intr(dev, res, tag, "%s", name); 1573 1574 irq->ii_tag = tag; 1575 return (0); 1576 } 1577 1578 /********************************************************************* 1579 * 1580 * Allocate DMA resources for TX buffers as well as memory for the TX 1581 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1582 * iflib_sw_tx_desc_array structure, storing all the information that 1583 * is needed to transmit a packet on the wire. This is called only 1584 * once at attach, setup is done every reset. 1585 * 1586 **********************************************************************/ 1587 static int 1588 iflib_txsd_alloc(iflib_txq_t txq) 1589 { 1590 if_ctx_t ctx = txq->ift_ctx; 1591 if_shared_ctx_t sctx = ctx->ifc_sctx; 1592 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1593 device_t dev = ctx->ifc_dev; 1594 bus_size_t tsomaxsize; 1595 int err, nsegments, ntsosegments; 1596 bool tso; 1597 1598 nsegments = scctx->isc_tx_nsegments; 1599 ntsosegments = scctx->isc_tx_tso_segments_max; 1600 tsomaxsize = scctx->isc_tx_tso_size_max; 1601 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1602 tsomaxsize += sizeof(struct ether_vlan_header); 1603 MPASS(scctx->isc_ntxd[0] > 0); 1604 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1605 MPASS(nsegments > 0); 1606 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1607 MPASS(ntsosegments > 0); 1608 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1609 } 1610 1611 /* 1612 * Set up DMA tags for TX buffers. 1613 */ 1614 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1615 1, 0, /* alignment, bounds */ 1616 BUS_SPACE_MAXADDR, /* lowaddr */ 1617 BUS_SPACE_MAXADDR, /* highaddr */ 1618 NULL, NULL, /* filter, filterarg */ 1619 sctx->isc_tx_maxsize, /* maxsize */ 1620 nsegments, /* nsegments */ 1621 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1622 0, /* flags */ 1623 NULL, /* lockfunc */ 1624 NULL, /* lockfuncarg */ 1625 &txq->ift_buf_tag))) { 1626 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1627 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1628 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1629 goto fail; 1630 } 1631 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1632 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1633 1, 0, /* alignment, bounds */ 1634 BUS_SPACE_MAXADDR, /* lowaddr */ 1635 BUS_SPACE_MAXADDR, /* highaddr */ 1636 NULL, NULL, /* filter, filterarg */ 1637 tsomaxsize, /* maxsize */ 1638 ntsosegments, /* nsegments */ 1639 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1640 0, /* flags */ 1641 NULL, /* lockfunc */ 1642 NULL, /* lockfuncarg */ 1643 &txq->ift_tso_buf_tag))) { 1644 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1645 err); 1646 goto fail; 1647 } 1648 1649 /* Allocate memory for the TX mbuf map. */ 1650 if (!(txq->ift_sds.ifsd_m = 1651 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1652 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1653 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1654 err = ENOMEM; 1655 goto fail; 1656 } 1657 1658 /* 1659 * Create the DMA maps for TX buffers. 1660 */ 1661 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1662 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1663 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1664 device_printf(dev, 1665 "Unable to allocate TX buffer DMA map memory\n"); 1666 err = ENOMEM; 1667 goto fail; 1668 } 1669 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1670 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1671 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1672 device_printf(dev, 1673 "Unable to allocate TSO TX buffer map memory\n"); 1674 err = ENOMEM; 1675 goto fail; 1676 } 1677 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1678 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1679 &txq->ift_sds.ifsd_map[i]); 1680 if (err != 0) { 1681 device_printf(dev, "Unable to create TX DMA map\n"); 1682 goto fail; 1683 } 1684 if (!tso) 1685 continue; 1686 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1687 &txq->ift_sds.ifsd_tso_map[i]); 1688 if (err != 0) { 1689 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1690 goto fail; 1691 } 1692 } 1693 return (0); 1694 fail: 1695 /* We free all, it handles case where we are in the middle */ 1696 iflib_tx_structures_free(ctx); 1697 return (err); 1698 } 1699 1700 static void 1701 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1702 { 1703 bus_dmamap_t map; 1704 1705 if (txq->ift_sds.ifsd_map != NULL) { 1706 map = txq->ift_sds.ifsd_map[i]; 1707 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1708 bus_dmamap_unload(txq->ift_buf_tag, map); 1709 bus_dmamap_destroy(txq->ift_buf_tag, map); 1710 txq->ift_sds.ifsd_map[i] = NULL; 1711 } 1712 1713 if (txq->ift_sds.ifsd_tso_map != NULL) { 1714 map = txq->ift_sds.ifsd_tso_map[i]; 1715 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1716 BUS_DMASYNC_POSTWRITE); 1717 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1718 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1719 txq->ift_sds.ifsd_tso_map[i] = NULL; 1720 } 1721 } 1722 1723 static void 1724 iflib_txq_destroy(iflib_txq_t txq) 1725 { 1726 if_ctx_t ctx = txq->ift_ctx; 1727 1728 for (int i = 0; i < txq->ift_size; i++) 1729 iflib_txsd_destroy(ctx, txq, i); 1730 1731 if (txq->ift_br != NULL) { 1732 ifmp_ring_free(txq->ift_br); 1733 txq->ift_br = NULL; 1734 } 1735 1736 mtx_destroy(&txq->ift_mtx); 1737 1738 if (txq->ift_sds.ifsd_map != NULL) { 1739 free(txq->ift_sds.ifsd_map, M_IFLIB); 1740 txq->ift_sds.ifsd_map = NULL; 1741 } 1742 if (txq->ift_sds.ifsd_tso_map != NULL) { 1743 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1744 txq->ift_sds.ifsd_tso_map = NULL; 1745 } 1746 if (txq->ift_sds.ifsd_m != NULL) { 1747 free(txq->ift_sds.ifsd_m, M_IFLIB); 1748 txq->ift_sds.ifsd_m = NULL; 1749 } 1750 if (txq->ift_buf_tag != NULL) { 1751 bus_dma_tag_destroy(txq->ift_buf_tag); 1752 txq->ift_buf_tag = NULL; 1753 } 1754 if (txq->ift_tso_buf_tag != NULL) { 1755 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1756 txq->ift_tso_buf_tag = NULL; 1757 } 1758 if (txq->ift_ifdi != NULL) { 1759 free(txq->ift_ifdi, M_IFLIB); 1760 } 1761 } 1762 1763 static void 1764 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1765 { 1766 struct mbuf **mp; 1767 1768 mp = &txq->ift_sds.ifsd_m[i]; 1769 if (*mp == NULL) 1770 return; 1771 1772 if (txq->ift_sds.ifsd_map != NULL) { 1773 bus_dmamap_sync(txq->ift_buf_tag, 1774 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1775 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1776 } 1777 if (txq->ift_sds.ifsd_tso_map != NULL) { 1778 bus_dmamap_sync(txq->ift_tso_buf_tag, 1779 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1780 bus_dmamap_unload(txq->ift_tso_buf_tag, 1781 txq->ift_sds.ifsd_tso_map[i]); 1782 } 1783 m_free(*mp); 1784 DBG_COUNTER_INC(tx_frees); 1785 *mp = NULL; 1786 } 1787 1788 static int 1789 iflib_txq_setup(iflib_txq_t txq) 1790 { 1791 if_ctx_t ctx = txq->ift_ctx; 1792 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1793 if_shared_ctx_t sctx = ctx->ifc_sctx; 1794 iflib_dma_info_t di; 1795 int i; 1796 1797 /* Set number of descriptors available */ 1798 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1799 /* XXX make configurable */ 1800 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1801 1802 /* Reset indices */ 1803 txq->ift_cidx_processed = 0; 1804 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1805 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1806 1807 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1808 bzero((void *)di->idi_vaddr, di->idi_size); 1809 1810 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1811 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1812 bus_dmamap_sync(di->idi_tag, di->idi_map, 1813 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1814 return (0); 1815 } 1816 1817 /********************************************************************* 1818 * 1819 * Allocate DMA resources for RX buffers as well as memory for the RX 1820 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1821 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1822 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1823 * Since we use use one entry in iflib_sw_rx_desc_array per received 1824 * packet, the maximum number of entries we'll need is equal to the 1825 * number of hardware receive descriptors that we've allocated. 1826 * 1827 **********************************************************************/ 1828 static int 1829 iflib_rxsd_alloc(iflib_rxq_t rxq) 1830 { 1831 if_ctx_t ctx = rxq->ifr_ctx; 1832 if_shared_ctx_t sctx = ctx->ifc_sctx; 1833 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1834 device_t dev = ctx->ifc_dev; 1835 iflib_fl_t fl; 1836 int err; 1837 1838 MPASS(scctx->isc_nrxd[0] > 0); 1839 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1840 1841 fl = rxq->ifr_fl; 1842 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1843 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1844 /* Set up DMA tag for RX buffers. */ 1845 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1846 1, 0, /* alignment, bounds */ 1847 BUS_SPACE_MAXADDR, /* lowaddr */ 1848 BUS_SPACE_MAXADDR, /* highaddr */ 1849 NULL, NULL, /* filter, filterarg */ 1850 sctx->isc_rx_maxsize, /* maxsize */ 1851 sctx->isc_rx_nsegments, /* nsegments */ 1852 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1853 0, /* flags */ 1854 NULL, /* lockfunc */ 1855 NULL, /* lockarg */ 1856 &fl->ifl_buf_tag); 1857 if (err) { 1858 device_printf(dev, 1859 "Unable to allocate RX DMA tag: %d\n", err); 1860 goto fail; 1861 } 1862 1863 /* Allocate memory for the RX mbuf map. */ 1864 if (!(fl->ifl_sds.ifsd_m = 1865 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1866 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1867 device_printf(dev, 1868 "Unable to allocate RX mbuf map memory\n"); 1869 err = ENOMEM; 1870 goto fail; 1871 } 1872 1873 /* Allocate memory for the direct RX cluster pointer map. */ 1874 if (!(fl->ifl_sds.ifsd_cl = 1875 (caddr_t *) malloc(sizeof(caddr_t) * 1876 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1877 device_printf(dev, 1878 "Unable to allocate RX cluster map memory\n"); 1879 err = ENOMEM; 1880 goto fail; 1881 } 1882 1883 /* Allocate memory for the RX cluster bus address map. */ 1884 if (!(fl->ifl_sds.ifsd_ba = 1885 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1886 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1887 device_printf(dev, 1888 "Unable to allocate RX bus address map memory\n"); 1889 err = ENOMEM; 1890 goto fail; 1891 } 1892 1893 /* 1894 * Create the DMA maps for RX buffers. 1895 */ 1896 if (!(fl->ifl_sds.ifsd_map = 1897 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1898 device_printf(dev, 1899 "Unable to allocate RX buffer DMA map memory\n"); 1900 err = ENOMEM; 1901 goto fail; 1902 } 1903 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1904 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1905 &fl->ifl_sds.ifsd_map[i]); 1906 if (err != 0) { 1907 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1908 goto fail; 1909 } 1910 } 1911 } 1912 return (0); 1913 1914 fail: 1915 iflib_rx_structures_free(ctx); 1916 return (err); 1917 } 1918 1919 /* 1920 * Internal service routines 1921 */ 1922 1923 struct rxq_refill_cb_arg { 1924 int error; 1925 bus_dma_segment_t seg; 1926 int nseg; 1927 }; 1928 1929 static void 1930 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1931 { 1932 struct rxq_refill_cb_arg *cb_arg = arg; 1933 1934 cb_arg->error = error; 1935 cb_arg->seg = segs[0]; 1936 cb_arg->nseg = nseg; 1937 } 1938 1939 /** 1940 * iflib_fl_refill - refill an rxq free-buffer list 1941 * @ctx: the iflib context 1942 * @fl: the free list to refill 1943 * @count: the number of new buffers to allocate 1944 * 1945 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 1946 * The caller must assure that @count does not exceed the queue's capacity 1947 * minus one (since we always leave a descriptor unavailable). 1948 */ 1949 static uint8_t 1950 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1951 { 1952 struct if_rxd_update iru; 1953 struct rxq_refill_cb_arg cb_arg; 1954 struct mbuf *m; 1955 caddr_t cl, *sd_cl; 1956 struct mbuf **sd_m; 1957 bus_dmamap_t *sd_map; 1958 bus_addr_t bus_addr, *sd_ba; 1959 int err, frag_idx, i, idx, n, pidx; 1960 qidx_t credits; 1961 1962 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 1963 1964 sd_m = fl->ifl_sds.ifsd_m; 1965 sd_map = fl->ifl_sds.ifsd_map; 1966 sd_cl = fl->ifl_sds.ifsd_cl; 1967 sd_ba = fl->ifl_sds.ifsd_ba; 1968 pidx = fl->ifl_pidx; 1969 idx = pidx; 1970 frag_idx = fl->ifl_fragidx; 1971 credits = fl->ifl_credits; 1972 1973 i = 0; 1974 n = count; 1975 MPASS(n > 0); 1976 MPASS(credits + n <= fl->ifl_size); 1977 1978 if (pidx < fl->ifl_cidx) 1979 MPASS(pidx + n <= fl->ifl_cidx); 1980 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1981 MPASS(fl->ifl_gen == 0); 1982 if (pidx > fl->ifl_cidx) 1983 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1984 1985 DBG_COUNTER_INC(fl_refills); 1986 if (n > 8) 1987 DBG_COUNTER_INC(fl_refills_large); 1988 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1989 while (n-- > 0) { 1990 /* 1991 * We allocate an uninitialized mbuf + cluster, mbuf is 1992 * initialized after rx. 1993 * 1994 * If the cluster is still set then we know a minimum sized 1995 * packet was received 1996 */ 1997 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 1998 &frag_idx); 1999 if (frag_idx < 0) 2000 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2001 MPASS(frag_idx >= 0); 2002 if ((cl = sd_cl[frag_idx]) == NULL) { 2003 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2004 if (__predict_false(cl == NULL)) 2005 break; 2006 2007 cb_arg.error = 0; 2008 MPASS(sd_map != NULL); 2009 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2010 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2011 BUS_DMA_NOWAIT); 2012 if (__predict_false(err != 0 || cb_arg.error)) { 2013 uma_zfree(fl->ifl_zone, cl); 2014 break; 2015 } 2016 2017 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2018 sd_cl[frag_idx] = cl; 2019 #if MEMORY_LOGGING 2020 fl->ifl_cl_enqueued++; 2021 #endif 2022 } else { 2023 bus_addr = sd_ba[frag_idx]; 2024 } 2025 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2026 BUS_DMASYNC_PREREAD); 2027 2028 if (sd_m[frag_idx] == NULL) { 2029 m = m_gethdr(M_NOWAIT, MT_NOINIT); 2030 if (__predict_false(m == NULL)) 2031 break; 2032 sd_m[frag_idx] = m; 2033 } 2034 bit_set(fl->ifl_rx_bitmap, frag_idx); 2035 #if MEMORY_LOGGING 2036 fl->ifl_m_enqueued++; 2037 #endif 2038 2039 DBG_COUNTER_INC(rx_allocs); 2040 fl->ifl_rxd_idxs[i] = frag_idx; 2041 fl->ifl_bus_addrs[i] = bus_addr; 2042 credits++; 2043 i++; 2044 MPASS(credits <= fl->ifl_size); 2045 if (++idx == fl->ifl_size) { 2046 #ifdef INVARIANTS 2047 fl->ifl_gen = 1; 2048 #endif 2049 idx = 0; 2050 } 2051 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2052 iru.iru_pidx = pidx; 2053 iru.iru_count = i; 2054 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2055 fl->ifl_pidx = idx; 2056 fl->ifl_credits = credits; 2057 pidx = idx; 2058 i = 0; 2059 } 2060 } 2061 2062 if (n < count - 1) { 2063 if (i != 0) { 2064 iru.iru_pidx = pidx; 2065 iru.iru_count = i; 2066 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2067 fl->ifl_pidx = idx; 2068 fl->ifl_credits = credits; 2069 } 2070 DBG_COUNTER_INC(rxd_flush); 2071 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2072 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2073 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2074 fl->ifl_id, fl->ifl_pidx); 2075 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2076 fl->ifl_fragidx = frag_idx + 1; 2077 if (fl->ifl_fragidx == fl->ifl_size) 2078 fl->ifl_fragidx = 0; 2079 } else { 2080 fl->ifl_fragidx = frag_idx; 2081 } 2082 } 2083 2084 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2085 } 2086 2087 static inline uint8_t 2088 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2089 { 2090 /* 2091 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2092 * This is important as it confuses most NICs. For instance, 2093 * Intel NICs have (per receive ring) RDH and RDT registers, where 2094 * RDH points to the next receive descriptor to be used by the NIC, 2095 * and RDT for the next receive descriptor to be published by the 2096 * driver to the NIC (RDT - 1 is thus the last valid one). 2097 * The condition RDH == RDT means no descriptors are available to 2098 * the NIC, and thus it would be ambiguous if it also meant that 2099 * all the descriptors are available to the NIC. 2100 */ 2101 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2102 #ifdef INVARIANTS 2103 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2104 #endif 2105 2106 MPASS(fl->ifl_credits <= fl->ifl_size); 2107 MPASS(reclaimable == delta); 2108 2109 if (reclaimable > 0) 2110 return (iflib_fl_refill(ctx, fl, reclaimable)); 2111 return (0); 2112 } 2113 2114 uint8_t 2115 iflib_in_detach(if_ctx_t ctx) 2116 { 2117 bool in_detach; 2118 2119 STATE_LOCK(ctx); 2120 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2121 STATE_UNLOCK(ctx); 2122 return (in_detach); 2123 } 2124 2125 static void 2126 iflib_fl_bufs_free(iflib_fl_t fl) 2127 { 2128 iflib_dma_info_t idi = fl->ifl_ifdi; 2129 bus_dmamap_t sd_map; 2130 uint32_t i; 2131 2132 for (i = 0; i < fl->ifl_size; i++) { 2133 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2134 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2135 2136 if (*sd_cl != NULL) { 2137 sd_map = fl->ifl_sds.ifsd_map[i]; 2138 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2139 BUS_DMASYNC_POSTREAD); 2140 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2141 uma_zfree(fl->ifl_zone, *sd_cl); 2142 *sd_cl = NULL; 2143 if (*sd_m != NULL) { 2144 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2145 uma_zfree(zone_mbuf, *sd_m); 2146 *sd_m = NULL; 2147 } 2148 } else { 2149 MPASS(*sd_m == NULL); 2150 } 2151 #if MEMORY_LOGGING 2152 fl->ifl_m_dequeued++; 2153 fl->ifl_cl_dequeued++; 2154 #endif 2155 } 2156 #ifdef INVARIANTS 2157 for (i = 0; i < fl->ifl_size; i++) { 2158 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2159 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2160 } 2161 #endif 2162 /* 2163 * Reset free list values 2164 */ 2165 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2166 bzero(idi->idi_vaddr, idi->idi_size); 2167 } 2168 2169 /********************************************************************* 2170 * 2171 * Initialize a free list and its buffers. 2172 * 2173 **********************************************************************/ 2174 static int 2175 iflib_fl_setup(iflib_fl_t fl) 2176 { 2177 iflib_rxq_t rxq = fl->ifl_rxq; 2178 if_ctx_t ctx = rxq->ifr_ctx; 2179 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2180 int qidx; 2181 2182 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2183 /* 2184 ** Free current RX buffer structs and their mbufs 2185 */ 2186 iflib_fl_bufs_free(fl); 2187 /* Now replenish the mbufs */ 2188 MPASS(fl->ifl_credits == 0); 2189 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2190 if (scctx->isc_rxd_buf_size[qidx] != 0) 2191 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2192 else 2193 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2194 /* 2195 * ifl_buf_size may be a driver-supplied value, so pull it up 2196 * to the selected mbuf size. 2197 */ 2198 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2199 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2200 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2201 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2202 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2203 2204 /* 2205 * Avoid pre-allocating zillions of clusters to an idle card 2206 * potentially speeding up attach. In any case make sure 2207 * to leave a descriptor unavailable. See the comment in 2208 * iflib_fl_refill_all(). 2209 */ 2210 MPASS(fl->ifl_size > 0); 2211 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2212 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2213 return (ENOBUFS); 2214 /* 2215 * handle failure 2216 */ 2217 MPASS(rxq != NULL); 2218 MPASS(fl->ifl_ifdi != NULL); 2219 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2220 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2221 return (0); 2222 } 2223 2224 /********************************************************************* 2225 * 2226 * Free receive ring data structures 2227 * 2228 **********************************************************************/ 2229 static void 2230 iflib_rx_sds_free(iflib_rxq_t rxq) 2231 { 2232 iflib_fl_t fl; 2233 int i, j; 2234 2235 if (rxq->ifr_fl != NULL) { 2236 for (i = 0; i < rxq->ifr_nfl; i++) { 2237 fl = &rxq->ifr_fl[i]; 2238 if (fl->ifl_buf_tag != NULL) { 2239 if (fl->ifl_sds.ifsd_map != NULL) { 2240 for (j = 0; j < fl->ifl_size; j++) { 2241 bus_dmamap_sync( 2242 fl->ifl_buf_tag, 2243 fl->ifl_sds.ifsd_map[j], 2244 BUS_DMASYNC_POSTREAD); 2245 bus_dmamap_unload( 2246 fl->ifl_buf_tag, 2247 fl->ifl_sds.ifsd_map[j]); 2248 bus_dmamap_destroy( 2249 fl->ifl_buf_tag, 2250 fl->ifl_sds.ifsd_map[j]); 2251 } 2252 } 2253 bus_dma_tag_destroy(fl->ifl_buf_tag); 2254 fl->ifl_buf_tag = NULL; 2255 } 2256 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2257 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2258 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2259 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2260 fl->ifl_sds.ifsd_m = NULL; 2261 fl->ifl_sds.ifsd_cl = NULL; 2262 fl->ifl_sds.ifsd_ba = NULL; 2263 fl->ifl_sds.ifsd_map = NULL; 2264 } 2265 free(rxq->ifr_fl, M_IFLIB); 2266 rxq->ifr_fl = NULL; 2267 free(rxq->ifr_ifdi, M_IFLIB); 2268 rxq->ifr_ifdi = NULL; 2269 rxq->ifr_cq_cidx = 0; 2270 } 2271 } 2272 2273 /* 2274 * Timer routine 2275 */ 2276 static void 2277 iflib_timer(void *arg) 2278 { 2279 iflib_txq_t txq = arg; 2280 if_ctx_t ctx = txq->ift_ctx; 2281 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2282 uint64_t this_tick = ticks; 2283 2284 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2285 return; 2286 2287 /* 2288 ** Check on the state of the TX queue(s), this 2289 ** can be done without the lock because its RO 2290 ** and the HUNG state will be static if set. 2291 */ 2292 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2293 txq->ift_last_timer_tick = this_tick; 2294 IFDI_TIMER(ctx, txq->ift_id); 2295 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2296 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2297 (sctx->isc_pause_frames == 0))) 2298 goto hung; 2299 2300 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2301 ifmp_ring_is_stalled(txq->ift_br)) { 2302 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down")); 2303 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2304 } 2305 txq->ift_cleaned_prev = txq->ift_cleaned; 2306 } 2307 /* handle any laggards */ 2308 if (txq->ift_db_pending) 2309 GROUPTASK_ENQUEUE(&txq->ift_task); 2310 2311 sctx->isc_pause_frames = 0; 2312 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2313 callout_reset_on(&txq->ift_timer, hz / 2, iflib_timer, txq, txq->ift_timer.c_cpu); 2314 return; 2315 2316 hung: 2317 device_printf(ctx->ifc_dev, 2318 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2319 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2320 STATE_LOCK(ctx); 2321 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2322 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2323 iflib_admin_intr_deferred(ctx); 2324 STATE_UNLOCK(ctx); 2325 } 2326 2327 static uint16_t 2328 iflib_get_mbuf_size_for(unsigned int size) 2329 { 2330 2331 if (size <= MCLBYTES) 2332 return (MCLBYTES); 2333 else 2334 return (MJUMPAGESIZE); 2335 } 2336 2337 static void 2338 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2339 { 2340 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2341 2342 /* 2343 * XXX don't set the max_frame_size to larger 2344 * than the hardware can handle 2345 */ 2346 ctx->ifc_rx_mbuf_sz = 2347 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2348 } 2349 2350 uint32_t 2351 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2352 { 2353 2354 return (ctx->ifc_rx_mbuf_sz); 2355 } 2356 2357 static void 2358 iflib_init_locked(if_ctx_t ctx) 2359 { 2360 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2361 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2362 if_t ifp = ctx->ifc_ifp; 2363 iflib_fl_t fl; 2364 iflib_txq_t txq; 2365 iflib_rxq_t rxq; 2366 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2367 2368 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2369 IFDI_INTR_DISABLE(ctx); 2370 2371 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2372 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2373 /* Set hardware offload abilities */ 2374 if_clearhwassist(ifp); 2375 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2376 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2377 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2378 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2379 if (if_getcapenable(ifp) & IFCAP_TSO4) 2380 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2381 if (if_getcapenable(ifp) & IFCAP_TSO6) 2382 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2383 2384 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2385 CALLOUT_LOCK(txq); 2386 callout_stop(&txq->ift_timer); 2387 #ifdef DEV_NETMAP 2388 callout_stop(&txq->ift_netmap_timer); 2389 #endif /* DEV_NETMAP */ 2390 CALLOUT_UNLOCK(txq); 2391 iflib_netmap_txq_init(ctx, txq); 2392 } 2393 2394 /* 2395 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2396 * that drivers can use the value when setting up the hardware receive 2397 * buffers. 2398 */ 2399 iflib_calc_rx_mbuf_sz(ctx); 2400 2401 #ifdef INVARIANTS 2402 i = if_getdrvflags(ifp); 2403 #endif 2404 IFDI_INIT(ctx); 2405 MPASS(if_getdrvflags(ifp) == i); 2406 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2407 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2408 /* This rxq is in netmap mode. Skip normal init. */ 2409 continue; 2410 } 2411 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2412 if (iflib_fl_setup(fl)) { 2413 device_printf(ctx->ifc_dev, 2414 "setting up free list %d failed - " 2415 "check cluster settings\n", j); 2416 goto done; 2417 } 2418 } 2419 } 2420 done: 2421 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2422 IFDI_INTR_ENABLE(ctx); 2423 txq = ctx->ifc_txqs; 2424 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2425 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2426 txq->ift_timer.c_cpu); 2427 } 2428 2429 static int 2430 iflib_media_change(if_t ifp) 2431 { 2432 if_ctx_t ctx = if_getsoftc(ifp); 2433 int err; 2434 2435 CTX_LOCK(ctx); 2436 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2437 iflib_init_locked(ctx); 2438 CTX_UNLOCK(ctx); 2439 return (err); 2440 } 2441 2442 static void 2443 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2444 { 2445 if_ctx_t ctx = if_getsoftc(ifp); 2446 2447 CTX_LOCK(ctx); 2448 IFDI_UPDATE_ADMIN_STATUS(ctx); 2449 IFDI_MEDIA_STATUS(ctx, ifmr); 2450 CTX_UNLOCK(ctx); 2451 } 2452 2453 void 2454 iflib_stop(if_ctx_t ctx) 2455 { 2456 iflib_txq_t txq = ctx->ifc_txqs; 2457 iflib_rxq_t rxq = ctx->ifc_rxqs; 2458 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2459 if_shared_ctx_t sctx = ctx->ifc_sctx; 2460 iflib_dma_info_t di; 2461 iflib_fl_t fl; 2462 int i, j; 2463 2464 /* Tell the stack that the interface is no longer active */ 2465 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2466 2467 IFDI_INTR_DISABLE(ctx); 2468 DELAY(1000); 2469 IFDI_STOP(ctx); 2470 DELAY(1000); 2471 2472 iflib_debug_reset(); 2473 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2474 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2475 /* make sure all transmitters have completed before proceeding XXX */ 2476 2477 CALLOUT_LOCK(txq); 2478 callout_stop(&txq->ift_timer); 2479 #ifdef DEV_NETMAP 2480 callout_stop(&txq->ift_netmap_timer); 2481 #endif /* DEV_NETMAP */ 2482 CALLOUT_UNLOCK(txq); 2483 2484 /* clean any enqueued buffers */ 2485 iflib_ifmp_purge(txq); 2486 /* Free any existing tx buffers. */ 2487 for (j = 0; j < txq->ift_size; j++) { 2488 iflib_txsd_free(ctx, txq, j); 2489 } 2490 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2491 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2492 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2493 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2494 txq->ift_pullups = 0; 2495 ifmp_ring_reset_stats(txq->ift_br); 2496 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2497 bzero((void *)di->idi_vaddr, di->idi_size); 2498 } 2499 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2500 /* make sure all transmitters have completed before proceeding XXX */ 2501 2502 rxq->ifr_cq_cidx = 0; 2503 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2504 bzero((void *)di->idi_vaddr, di->idi_size); 2505 /* also resets the free lists pidx/cidx */ 2506 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2507 iflib_fl_bufs_free(fl); 2508 } 2509 } 2510 2511 static inline caddr_t 2512 calc_next_rxd(iflib_fl_t fl, int cidx) 2513 { 2514 qidx_t size; 2515 int nrxd; 2516 caddr_t start, end, cur, next; 2517 2518 nrxd = fl->ifl_size; 2519 size = fl->ifl_rxd_size; 2520 start = fl->ifl_ifdi->idi_vaddr; 2521 2522 if (__predict_false(size == 0)) 2523 return (start); 2524 cur = start + size*cidx; 2525 end = start + size*nrxd; 2526 next = CACHE_PTR_NEXT(cur); 2527 return (next < end ? next : start); 2528 } 2529 2530 static inline void 2531 prefetch_pkts(iflib_fl_t fl, int cidx) 2532 { 2533 int nextptr; 2534 int nrxd = fl->ifl_size; 2535 caddr_t next_rxd; 2536 2537 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2538 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2539 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2540 next_rxd = calc_next_rxd(fl, cidx); 2541 prefetch(next_rxd); 2542 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2543 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2544 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2545 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2546 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2547 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2548 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2549 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2550 } 2551 2552 static struct mbuf * 2553 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2554 int *pf_rv, if_rxd_info_t ri) 2555 { 2556 bus_dmamap_t map; 2557 iflib_fl_t fl; 2558 caddr_t payload; 2559 struct mbuf *m; 2560 int flid, cidx, len, next; 2561 2562 map = NULL; 2563 flid = irf->irf_flid; 2564 cidx = irf->irf_idx; 2565 fl = &rxq->ifr_fl[flid]; 2566 sd->ifsd_fl = fl; 2567 m = fl->ifl_sds.ifsd_m[cidx]; 2568 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2569 fl->ifl_credits--; 2570 #if MEMORY_LOGGING 2571 fl->ifl_m_dequeued++; 2572 #endif 2573 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2574 prefetch_pkts(fl, cidx); 2575 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2576 prefetch(&fl->ifl_sds.ifsd_map[next]); 2577 map = fl->ifl_sds.ifsd_map[cidx]; 2578 2579 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2580 2581 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2582 irf->irf_len != 0) { 2583 payload = *sd->ifsd_cl; 2584 payload += ri->iri_pad; 2585 len = ri->iri_len - ri->iri_pad; 2586 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2587 len | PFIL_MEMPTR | PFIL_IN, NULL); 2588 switch (*pf_rv) { 2589 case PFIL_DROPPED: 2590 case PFIL_CONSUMED: 2591 /* 2592 * The filter ate it. Everything is recycled. 2593 */ 2594 m = NULL; 2595 unload = 0; 2596 break; 2597 case PFIL_REALLOCED: 2598 /* 2599 * The filter copied it. Everything is recycled. 2600 */ 2601 m = pfil_mem2mbuf(payload); 2602 unload = 0; 2603 break; 2604 case PFIL_PASS: 2605 /* 2606 * Filter said it was OK, so receive like 2607 * normal 2608 */ 2609 fl->ifl_sds.ifsd_m[cidx] = NULL; 2610 break; 2611 default: 2612 MPASS(0); 2613 } 2614 } else { 2615 fl->ifl_sds.ifsd_m[cidx] = NULL; 2616 *pf_rv = PFIL_PASS; 2617 } 2618 2619 if (unload && irf->irf_len != 0) 2620 bus_dmamap_unload(fl->ifl_buf_tag, map); 2621 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2622 if (__predict_false(fl->ifl_cidx == 0)) 2623 fl->ifl_gen = 0; 2624 bit_clear(fl->ifl_rx_bitmap, cidx); 2625 return (m); 2626 } 2627 2628 static struct mbuf * 2629 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2630 { 2631 struct mbuf *m, *mh, *mt; 2632 caddr_t cl; 2633 int *pf_rv_ptr, flags, i, padlen; 2634 bool consumed; 2635 2636 i = 0; 2637 mh = NULL; 2638 consumed = false; 2639 *pf_rv = PFIL_PASS; 2640 pf_rv_ptr = pf_rv; 2641 do { 2642 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2643 pf_rv_ptr, ri); 2644 2645 MPASS(*sd->ifsd_cl != NULL); 2646 2647 /* 2648 * Exclude zero-length frags & frags from 2649 * packets the filter has consumed or dropped 2650 */ 2651 if (ri->iri_frags[i].irf_len == 0 || consumed || 2652 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2653 if (mh == NULL) { 2654 /* everything saved here */ 2655 consumed = true; 2656 pf_rv_ptr = NULL; 2657 continue; 2658 } 2659 /* XXX we can save the cluster here, but not the mbuf */ 2660 m_init(m, M_NOWAIT, MT_DATA, 0); 2661 m_free(m); 2662 continue; 2663 } 2664 if (mh == NULL) { 2665 flags = M_PKTHDR|M_EXT; 2666 mh = mt = m; 2667 padlen = ri->iri_pad; 2668 } else { 2669 flags = M_EXT; 2670 mt->m_next = m; 2671 mt = m; 2672 /* assuming padding is only on the first fragment */ 2673 padlen = 0; 2674 } 2675 cl = *sd->ifsd_cl; 2676 *sd->ifsd_cl = NULL; 2677 2678 /* Can these two be made one ? */ 2679 m_init(m, M_NOWAIT, MT_DATA, flags); 2680 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2681 /* 2682 * These must follow m_init and m_cljset 2683 */ 2684 m->m_data += padlen; 2685 ri->iri_len -= padlen; 2686 m->m_len = ri->iri_frags[i].irf_len; 2687 } while (++i < ri->iri_nfrags); 2688 2689 return (mh); 2690 } 2691 2692 /* 2693 * Process one software descriptor 2694 */ 2695 static struct mbuf * 2696 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2697 { 2698 struct if_rxsd sd; 2699 struct mbuf *m; 2700 int pf_rv; 2701 2702 /* should I merge this back in now that the two paths are basically duplicated? */ 2703 if (ri->iri_nfrags == 1 && 2704 ri->iri_frags[0].irf_len != 0 && 2705 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2706 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2707 &pf_rv, ri); 2708 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2709 return (m); 2710 if (pf_rv == PFIL_PASS) { 2711 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2712 #ifndef __NO_STRICT_ALIGNMENT 2713 if (!IP_ALIGNED(m)) 2714 m->m_data += 2; 2715 #endif 2716 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2717 m->m_len = ri->iri_frags[0].irf_len; 2718 } 2719 } else { 2720 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2721 if (m == NULL) 2722 return (NULL); 2723 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2724 return (m); 2725 } 2726 m->m_pkthdr.len = ri->iri_len; 2727 m->m_pkthdr.rcvif = ri->iri_ifp; 2728 m->m_flags |= ri->iri_flags; 2729 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2730 m->m_pkthdr.flowid = ri->iri_flowid; 2731 M_HASHTYPE_SET(m, ri->iri_rsstype); 2732 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2733 m->m_pkthdr.csum_data = ri->iri_csum_data; 2734 return (m); 2735 } 2736 2737 #if defined(INET6) || defined(INET) 2738 static void 2739 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2740 { 2741 CURVNET_SET(lc->ifp->if_vnet); 2742 #if defined(INET6) 2743 *v6 = V_ip6_forwarding; 2744 #endif 2745 #if defined(INET) 2746 *v4 = V_ipforwarding; 2747 #endif 2748 CURVNET_RESTORE(); 2749 } 2750 2751 /* 2752 * Returns true if it's possible this packet could be LROed. 2753 * if it returns false, it is guaranteed that tcp_lro_rx() 2754 * would not return zero. 2755 */ 2756 static bool 2757 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2758 { 2759 struct ether_header *eh; 2760 2761 eh = mtod(m, struct ether_header *); 2762 switch (eh->ether_type) { 2763 #if defined(INET6) 2764 case htons(ETHERTYPE_IPV6): 2765 return (!v6_forwarding); 2766 #endif 2767 #if defined (INET) 2768 case htons(ETHERTYPE_IP): 2769 return (!v4_forwarding); 2770 #endif 2771 } 2772 2773 return false; 2774 } 2775 #else 2776 static void 2777 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2778 { 2779 } 2780 #endif 2781 2782 static void 2783 _task_fn_rx_watchdog(void *context) 2784 { 2785 iflib_rxq_t rxq = context; 2786 2787 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2788 } 2789 2790 static uint8_t 2791 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2792 { 2793 if_t ifp; 2794 if_ctx_t ctx = rxq->ifr_ctx; 2795 if_shared_ctx_t sctx = ctx->ifc_sctx; 2796 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2797 int avail, i; 2798 qidx_t *cidxp; 2799 struct if_rxd_info ri; 2800 int err, budget_left, rx_bytes, rx_pkts; 2801 iflib_fl_t fl; 2802 int lro_enabled; 2803 bool v4_forwarding, v6_forwarding, lro_possible; 2804 uint8_t retval = 0; 2805 2806 /* 2807 * XXX early demux data packets so that if_input processing only handles 2808 * acks in interrupt context 2809 */ 2810 struct mbuf *m, *mh, *mt, *mf; 2811 2812 NET_EPOCH_ASSERT(); 2813 2814 lro_possible = v4_forwarding = v6_forwarding = false; 2815 ifp = ctx->ifc_ifp; 2816 mh = mt = NULL; 2817 MPASS(budget > 0); 2818 rx_pkts = rx_bytes = 0; 2819 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2820 cidxp = &rxq->ifr_cq_cidx; 2821 else 2822 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2823 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2824 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2825 retval |= iflib_fl_refill_all(ctx, fl); 2826 DBG_COUNTER_INC(rx_unavail); 2827 return (retval); 2828 } 2829 2830 /* pfil needs the vnet to be set */ 2831 CURVNET_SET_QUIET(ifp->if_vnet); 2832 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2833 if (__predict_false(!CTX_ACTIVE(ctx))) { 2834 DBG_COUNTER_INC(rx_ctx_inactive); 2835 break; 2836 } 2837 /* 2838 * Reset client set fields to their default values 2839 */ 2840 rxd_info_zero(&ri); 2841 ri.iri_qsidx = rxq->ifr_id; 2842 ri.iri_cidx = *cidxp; 2843 ri.iri_ifp = ifp; 2844 ri.iri_frags = rxq->ifr_frags; 2845 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2846 2847 if (err) 2848 goto err; 2849 rx_pkts += 1; 2850 rx_bytes += ri.iri_len; 2851 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2852 *cidxp = ri.iri_cidx; 2853 /* Update our consumer index */ 2854 /* XXX NB: shurd - check if this is still safe */ 2855 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2856 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2857 /* was this only a completion queue message? */ 2858 if (__predict_false(ri.iri_nfrags == 0)) 2859 continue; 2860 } 2861 MPASS(ri.iri_nfrags != 0); 2862 MPASS(ri.iri_len != 0); 2863 2864 /* will advance the cidx on the corresponding free lists */ 2865 m = iflib_rxd_pkt_get(rxq, &ri); 2866 avail--; 2867 budget_left--; 2868 if (avail == 0 && budget_left) 2869 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2870 2871 if (__predict_false(m == NULL)) 2872 continue; 2873 2874 /* imm_pkt: -- cxgb */ 2875 if (mh == NULL) 2876 mh = mt = m; 2877 else { 2878 mt->m_nextpkt = m; 2879 mt = m; 2880 } 2881 } 2882 CURVNET_RESTORE(); 2883 /* make sure that we can refill faster than drain */ 2884 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2885 retval |= iflib_fl_refill_all(ctx, fl); 2886 2887 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2888 if (lro_enabled) 2889 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2890 mt = mf = NULL; 2891 while (mh != NULL) { 2892 m = mh; 2893 mh = mh->m_nextpkt; 2894 m->m_nextpkt = NULL; 2895 #ifndef __NO_STRICT_ALIGNMENT 2896 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2897 continue; 2898 #endif 2899 rx_bytes += m->m_pkthdr.len; 2900 rx_pkts++; 2901 #if defined(INET6) || defined(INET) 2902 if (lro_enabled) { 2903 if (!lro_possible) { 2904 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2905 if (lro_possible && mf != NULL) { 2906 ifp->if_input(ifp, mf); 2907 DBG_COUNTER_INC(rx_if_input); 2908 mt = mf = NULL; 2909 } 2910 } 2911 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2912 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2913 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2914 continue; 2915 } 2916 } 2917 #endif 2918 if (lro_possible) { 2919 ifp->if_input(ifp, m); 2920 DBG_COUNTER_INC(rx_if_input); 2921 continue; 2922 } 2923 2924 if (mf == NULL) 2925 mf = m; 2926 if (mt != NULL) 2927 mt->m_nextpkt = m; 2928 mt = m; 2929 } 2930 if (mf != NULL) { 2931 ifp->if_input(ifp, mf); 2932 DBG_COUNTER_INC(rx_if_input); 2933 } 2934 2935 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2936 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2937 2938 /* 2939 * Flush any outstanding LRO work 2940 */ 2941 #if defined(INET6) || defined(INET) 2942 tcp_lro_flush_all(&rxq->ifr_lc); 2943 #endif 2944 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 2945 retval |= IFLIB_RXEOF_MORE; 2946 return (retval); 2947 err: 2948 STATE_LOCK(ctx); 2949 ctx->ifc_flags |= IFC_DO_RESET; 2950 iflib_admin_intr_deferred(ctx); 2951 STATE_UNLOCK(ctx); 2952 return (0); 2953 } 2954 2955 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2956 static inline qidx_t 2957 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2958 { 2959 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2960 qidx_t minthresh = txq->ift_size / 8; 2961 if (in_use > 4*minthresh) 2962 return (notify_count); 2963 if (in_use > 2*minthresh) 2964 return (notify_count >> 1); 2965 if (in_use > minthresh) 2966 return (notify_count >> 3); 2967 return (0); 2968 } 2969 2970 static inline qidx_t 2971 txq_max_rs_deferred(iflib_txq_t txq) 2972 { 2973 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2974 qidx_t minthresh = txq->ift_size / 8; 2975 if (txq->ift_in_use > 4*minthresh) 2976 return (notify_count); 2977 if (txq->ift_in_use > 2*minthresh) 2978 return (notify_count >> 1); 2979 if (txq->ift_in_use > minthresh) 2980 return (notify_count >> 2); 2981 return (2); 2982 } 2983 2984 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2985 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2986 2987 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2988 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2989 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2990 2991 /* forward compatibility for cxgb */ 2992 #define FIRST_QSET(ctx) 0 2993 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2994 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2995 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2996 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2997 2998 /* XXX we should be setting this to something other than zero */ 2999 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 3000 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3001 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3002 3003 static inline bool 3004 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 3005 { 3006 qidx_t dbval, max; 3007 bool rang; 3008 3009 rang = false; 3010 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 3011 if (ring || txq->ift_db_pending >= max) { 3012 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3013 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3014 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3015 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3016 txq->ift_db_pending = txq->ift_npending = 0; 3017 rang = true; 3018 } 3019 return (rang); 3020 } 3021 3022 #ifdef PKT_DEBUG 3023 static void 3024 print_pkt(if_pkt_info_t pi) 3025 { 3026 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3027 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3028 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3029 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3030 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3031 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3032 } 3033 #endif 3034 3035 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3036 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3037 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3038 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3039 3040 static int 3041 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3042 { 3043 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3044 struct ether_vlan_header *eh; 3045 struct mbuf *m; 3046 3047 m = *mp; 3048 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3049 M_WRITABLE(m) == 0) { 3050 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3051 return (ENOMEM); 3052 } else { 3053 m_freem(*mp); 3054 DBG_COUNTER_INC(tx_frees); 3055 *mp = m; 3056 } 3057 } 3058 3059 /* 3060 * Determine where frame payload starts. 3061 * Jump over vlan headers if already present, 3062 * helpful for QinQ too. 3063 */ 3064 if (__predict_false(m->m_len < sizeof(*eh))) { 3065 txq->ift_pullups++; 3066 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3067 return (ENOMEM); 3068 } 3069 eh = mtod(m, struct ether_vlan_header *); 3070 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3071 pi->ipi_etype = ntohs(eh->evl_proto); 3072 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3073 } else { 3074 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3075 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3076 } 3077 3078 switch (pi->ipi_etype) { 3079 #ifdef INET 3080 case ETHERTYPE_IP: 3081 { 3082 struct mbuf *n; 3083 struct ip *ip = NULL; 3084 struct tcphdr *th = NULL; 3085 int minthlen; 3086 3087 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3088 if (__predict_false(m->m_len < minthlen)) { 3089 /* 3090 * if this code bloat is causing too much of a hit 3091 * move it to a separate function and mark it noinline 3092 */ 3093 if (m->m_len == pi->ipi_ehdrlen) { 3094 n = m->m_next; 3095 MPASS(n); 3096 if (n->m_len >= sizeof(*ip)) { 3097 ip = (struct ip *)n->m_data; 3098 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3099 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3100 } else { 3101 txq->ift_pullups++; 3102 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3103 return (ENOMEM); 3104 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3105 } 3106 } else { 3107 txq->ift_pullups++; 3108 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3109 return (ENOMEM); 3110 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3111 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3112 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3113 } 3114 } else { 3115 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3116 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3117 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3118 } 3119 pi->ipi_ip_hlen = ip->ip_hl << 2; 3120 pi->ipi_ipproto = ip->ip_p; 3121 pi->ipi_flags |= IPI_TX_IPV4; 3122 3123 /* TCP checksum offload may require TCP header length */ 3124 if (IS_TX_OFFLOAD4(pi)) { 3125 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3126 if (__predict_false(th == NULL)) { 3127 txq->ift_pullups++; 3128 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3129 return (ENOMEM); 3130 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3131 } 3132 pi->ipi_tcp_hflags = th->th_flags; 3133 pi->ipi_tcp_hlen = th->th_off << 2; 3134 pi->ipi_tcp_seq = th->th_seq; 3135 } 3136 if (IS_TSO4(pi)) { 3137 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3138 return (ENXIO); 3139 /* 3140 * TSO always requires hardware checksum offload. 3141 */ 3142 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3143 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3144 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3145 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3146 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3147 ip->ip_sum = 0; 3148 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3149 } 3150 } 3151 } 3152 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3153 ip->ip_sum = 0; 3154 3155 break; 3156 } 3157 #endif 3158 #ifdef INET6 3159 case ETHERTYPE_IPV6: 3160 { 3161 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3162 struct tcphdr *th; 3163 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3164 3165 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3166 txq->ift_pullups++; 3167 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3168 return (ENOMEM); 3169 } 3170 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3171 3172 /* XXX-BZ this will go badly in case of ext hdrs. */ 3173 pi->ipi_ipproto = ip6->ip6_nxt; 3174 pi->ipi_flags |= IPI_TX_IPV6; 3175 3176 /* TCP checksum offload may require TCP header length */ 3177 if (IS_TX_OFFLOAD6(pi)) { 3178 if (pi->ipi_ipproto == IPPROTO_TCP) { 3179 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3180 txq->ift_pullups++; 3181 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3182 return (ENOMEM); 3183 } 3184 pi->ipi_tcp_hflags = th->th_flags; 3185 pi->ipi_tcp_hlen = th->th_off << 2; 3186 pi->ipi_tcp_seq = th->th_seq; 3187 } 3188 if (IS_TSO6(pi)) { 3189 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3190 return (ENXIO); 3191 /* 3192 * TSO always requires hardware checksum offload. 3193 */ 3194 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3195 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3196 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3197 } 3198 } 3199 break; 3200 } 3201 #endif 3202 default: 3203 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3204 pi->ipi_ip_hlen = 0; 3205 break; 3206 } 3207 *mp = m; 3208 3209 return (0); 3210 } 3211 3212 /* 3213 * If dodgy hardware rejects the scatter gather chain we've handed it 3214 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3215 * m_defrag'd mbufs 3216 */ 3217 static __noinline struct mbuf * 3218 iflib_remove_mbuf(iflib_txq_t txq) 3219 { 3220 int ntxd, pidx; 3221 struct mbuf *m, **ifsd_m; 3222 3223 ifsd_m = txq->ift_sds.ifsd_m; 3224 ntxd = txq->ift_size; 3225 pidx = txq->ift_pidx & (ntxd - 1); 3226 ifsd_m = txq->ift_sds.ifsd_m; 3227 m = ifsd_m[pidx]; 3228 ifsd_m[pidx] = NULL; 3229 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3230 if (txq->ift_sds.ifsd_tso_map != NULL) 3231 bus_dmamap_unload(txq->ift_tso_buf_tag, 3232 txq->ift_sds.ifsd_tso_map[pidx]); 3233 #if MEMORY_LOGGING 3234 txq->ift_dequeued++; 3235 #endif 3236 return (m); 3237 } 3238 3239 static inline caddr_t 3240 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3241 { 3242 qidx_t size; 3243 int ntxd; 3244 caddr_t start, end, cur, next; 3245 3246 ntxd = txq->ift_size; 3247 size = txq->ift_txd_size[qid]; 3248 start = txq->ift_ifdi[qid].idi_vaddr; 3249 3250 if (__predict_false(size == 0)) 3251 return (start); 3252 cur = start + size*cidx; 3253 end = start + size*ntxd; 3254 next = CACHE_PTR_NEXT(cur); 3255 return (next < end ? next : start); 3256 } 3257 3258 /* 3259 * Pad an mbuf to ensure a minimum ethernet frame size. 3260 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3261 */ 3262 static __noinline int 3263 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3264 { 3265 /* 3266 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3267 * and ARP message is the smallest common payload I can think of 3268 */ 3269 static char pad[18]; /* just zeros */ 3270 int n; 3271 struct mbuf *new_head; 3272 3273 if (!M_WRITABLE(*m_head)) { 3274 new_head = m_dup(*m_head, M_NOWAIT); 3275 if (new_head == NULL) { 3276 m_freem(*m_head); 3277 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3278 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3279 DBG_COUNTER_INC(tx_frees); 3280 return ENOMEM; 3281 } 3282 m_freem(*m_head); 3283 *m_head = new_head; 3284 } 3285 3286 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3287 n > 0; n -= sizeof(pad)) 3288 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3289 break; 3290 3291 if (n > 0) { 3292 m_freem(*m_head); 3293 device_printf(dev, "cannot pad short frame\n"); 3294 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3295 DBG_COUNTER_INC(tx_frees); 3296 return (ENOBUFS); 3297 } 3298 3299 return 0; 3300 } 3301 3302 static int 3303 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3304 { 3305 if_ctx_t ctx; 3306 if_shared_ctx_t sctx; 3307 if_softc_ctx_t scctx; 3308 bus_dma_tag_t buf_tag; 3309 bus_dma_segment_t *segs; 3310 struct mbuf *m_head, **ifsd_m; 3311 void *next_txd; 3312 bus_dmamap_t map; 3313 struct if_pkt_info pi; 3314 int remap = 0; 3315 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3316 3317 ctx = txq->ift_ctx; 3318 sctx = ctx->ifc_sctx; 3319 scctx = &ctx->ifc_softc_ctx; 3320 segs = txq->ift_segs; 3321 ntxd = txq->ift_size; 3322 m_head = *m_headp; 3323 map = NULL; 3324 3325 /* 3326 * If we're doing TSO the next descriptor to clean may be quite far ahead 3327 */ 3328 cidx = txq->ift_cidx; 3329 pidx = txq->ift_pidx; 3330 if (ctx->ifc_flags & IFC_PREFETCH) { 3331 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3332 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3333 next_txd = calc_next_txd(txq, cidx, 0); 3334 prefetch(next_txd); 3335 } 3336 3337 /* prefetch the next cache line of mbuf pointers and flags */ 3338 prefetch(&txq->ift_sds.ifsd_m[next]); 3339 prefetch(&txq->ift_sds.ifsd_map[next]); 3340 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3341 } 3342 map = txq->ift_sds.ifsd_map[pidx]; 3343 ifsd_m = txq->ift_sds.ifsd_m; 3344 3345 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3346 buf_tag = txq->ift_tso_buf_tag; 3347 max_segs = scctx->isc_tx_tso_segments_max; 3348 map = txq->ift_sds.ifsd_tso_map[pidx]; 3349 MPASS(buf_tag != NULL); 3350 MPASS(max_segs > 0); 3351 } else { 3352 buf_tag = txq->ift_buf_tag; 3353 max_segs = scctx->isc_tx_nsegments; 3354 map = txq->ift_sds.ifsd_map[pidx]; 3355 } 3356 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3357 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3358 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3359 if (err) { 3360 DBG_COUNTER_INC(encap_txd_encap_fail); 3361 return err; 3362 } 3363 } 3364 m_head = *m_headp; 3365 3366 pkt_info_zero(&pi); 3367 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3368 pi.ipi_pidx = pidx; 3369 pi.ipi_qsidx = txq->ift_id; 3370 pi.ipi_len = m_head->m_pkthdr.len; 3371 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3372 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3373 3374 /* deliberate bitwise OR to make one condition */ 3375 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3376 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3377 DBG_COUNTER_INC(encap_txd_encap_fail); 3378 return (err); 3379 } 3380 m_head = *m_headp; 3381 } 3382 3383 retry: 3384 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3385 BUS_DMA_NOWAIT); 3386 defrag: 3387 if (__predict_false(err)) { 3388 switch (err) { 3389 case EFBIG: 3390 /* try collapse once and defrag once */ 3391 if (remap == 0) { 3392 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3393 /* try defrag if collapsing fails */ 3394 if (m_head == NULL) 3395 remap++; 3396 } 3397 if (remap == 1) { 3398 txq->ift_mbuf_defrag++; 3399 m_head = m_defrag(*m_headp, M_NOWAIT); 3400 } 3401 /* 3402 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3403 * failed to map an mbuf that was run through m_defrag 3404 */ 3405 MPASS(remap <= 1); 3406 if (__predict_false(m_head == NULL || remap > 1)) 3407 goto defrag_failed; 3408 remap++; 3409 *m_headp = m_head; 3410 goto retry; 3411 break; 3412 case ENOMEM: 3413 txq->ift_no_tx_dma_setup++; 3414 break; 3415 default: 3416 txq->ift_no_tx_dma_setup++; 3417 m_freem(*m_headp); 3418 DBG_COUNTER_INC(tx_frees); 3419 *m_headp = NULL; 3420 break; 3421 } 3422 txq->ift_map_failed++; 3423 DBG_COUNTER_INC(encap_load_mbuf_fail); 3424 DBG_COUNTER_INC(encap_txd_encap_fail); 3425 return (err); 3426 } 3427 ifsd_m[pidx] = m_head; 3428 /* 3429 * XXX assumes a 1 to 1 relationship between segments and 3430 * descriptors - this does not hold true on all drivers, e.g. 3431 * cxgb 3432 */ 3433 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3434 txq->ift_no_desc_avail++; 3435 bus_dmamap_unload(buf_tag, map); 3436 DBG_COUNTER_INC(encap_txq_avail_fail); 3437 DBG_COUNTER_INC(encap_txd_encap_fail); 3438 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3439 GROUPTASK_ENQUEUE(&txq->ift_task); 3440 return (ENOBUFS); 3441 } 3442 /* 3443 * On Intel cards we can greatly reduce the number of TX interrupts 3444 * we see by only setting report status on every Nth descriptor. 3445 * However, this also means that the driver will need to keep track 3446 * of the descriptors that RS was set on to check them for the DD bit. 3447 */ 3448 txq->ift_rs_pending += nsegs + 1; 3449 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3450 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3451 pi.ipi_flags |= IPI_TX_INTR; 3452 txq->ift_rs_pending = 0; 3453 } 3454 3455 pi.ipi_segs = segs; 3456 pi.ipi_nsegs = nsegs; 3457 3458 MPASS(pidx >= 0 && pidx < txq->ift_size); 3459 #ifdef PKT_DEBUG 3460 print_pkt(&pi); 3461 #endif 3462 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3463 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3464 DBG_COUNTER_INC(tx_encap); 3465 MPASS(pi.ipi_new_pidx < txq->ift_size); 3466 3467 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3468 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3469 ndesc += txq->ift_size; 3470 txq->ift_gen = 1; 3471 } 3472 /* 3473 * drivers can need as many as 3474 * two sentinels 3475 */ 3476 MPASS(ndesc <= pi.ipi_nsegs + 2); 3477 MPASS(pi.ipi_new_pidx != pidx); 3478 MPASS(ndesc > 0); 3479 txq->ift_in_use += ndesc; 3480 3481 /* 3482 * We update the last software descriptor again here because there may 3483 * be a sentinel and/or there may be more mbufs than segments 3484 */ 3485 txq->ift_pidx = pi.ipi_new_pidx; 3486 txq->ift_npending += pi.ipi_ndescs; 3487 } else { 3488 *m_headp = m_head = iflib_remove_mbuf(txq); 3489 if (err == EFBIG) { 3490 txq->ift_txd_encap_efbig++; 3491 if (remap < 2) { 3492 remap = 1; 3493 goto defrag; 3494 } 3495 } 3496 goto defrag_failed; 3497 } 3498 /* 3499 * err can't possibly be non-zero here, so we don't neet to test it 3500 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3501 */ 3502 return (err); 3503 3504 defrag_failed: 3505 txq->ift_mbuf_defrag_failed++; 3506 txq->ift_map_failed++; 3507 m_freem(*m_headp); 3508 DBG_COUNTER_INC(tx_frees); 3509 *m_headp = NULL; 3510 DBG_COUNTER_INC(encap_txd_encap_fail); 3511 return (ENOMEM); 3512 } 3513 3514 static void 3515 iflib_tx_desc_free(iflib_txq_t txq, int n) 3516 { 3517 uint32_t qsize, cidx, mask, gen; 3518 struct mbuf *m, **ifsd_m; 3519 bool do_prefetch; 3520 3521 cidx = txq->ift_cidx; 3522 gen = txq->ift_gen; 3523 qsize = txq->ift_size; 3524 mask = qsize-1; 3525 ifsd_m = txq->ift_sds.ifsd_m; 3526 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3527 3528 while (n-- > 0) { 3529 if (do_prefetch) { 3530 prefetch(ifsd_m[(cidx + 3) & mask]); 3531 prefetch(ifsd_m[(cidx + 4) & mask]); 3532 } 3533 if ((m = ifsd_m[cidx]) != NULL) { 3534 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3535 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3536 bus_dmamap_sync(txq->ift_tso_buf_tag, 3537 txq->ift_sds.ifsd_tso_map[cidx], 3538 BUS_DMASYNC_POSTWRITE); 3539 bus_dmamap_unload(txq->ift_tso_buf_tag, 3540 txq->ift_sds.ifsd_tso_map[cidx]); 3541 } else { 3542 bus_dmamap_sync(txq->ift_buf_tag, 3543 txq->ift_sds.ifsd_map[cidx], 3544 BUS_DMASYNC_POSTWRITE); 3545 bus_dmamap_unload(txq->ift_buf_tag, 3546 txq->ift_sds.ifsd_map[cidx]); 3547 } 3548 /* XXX we don't support any drivers that batch packets yet */ 3549 MPASS(m->m_nextpkt == NULL); 3550 m_freem(m); 3551 ifsd_m[cidx] = NULL; 3552 #if MEMORY_LOGGING 3553 txq->ift_dequeued++; 3554 #endif 3555 DBG_COUNTER_INC(tx_frees); 3556 } 3557 if (__predict_false(++cidx == qsize)) { 3558 cidx = 0; 3559 gen = 0; 3560 } 3561 } 3562 txq->ift_cidx = cidx; 3563 txq->ift_gen = gen; 3564 } 3565 3566 static __inline int 3567 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3568 { 3569 int reclaim; 3570 if_ctx_t ctx = txq->ift_ctx; 3571 3572 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3573 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3574 3575 /* 3576 * Need a rate-limiting check so that this isn't called every time 3577 */ 3578 iflib_tx_credits_update(ctx, txq); 3579 reclaim = DESC_RECLAIMABLE(txq); 3580 3581 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3582 #ifdef INVARIANTS 3583 if (iflib_verbose_debug) { 3584 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3585 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3586 reclaim, thresh); 3587 } 3588 #endif 3589 return (0); 3590 } 3591 iflib_tx_desc_free(txq, reclaim); 3592 txq->ift_cleaned += reclaim; 3593 txq->ift_in_use -= reclaim; 3594 3595 return (reclaim); 3596 } 3597 3598 static struct mbuf ** 3599 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3600 { 3601 int next, size; 3602 struct mbuf **items; 3603 3604 size = r->size; 3605 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3606 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3607 3608 prefetch(items[(cidx + offset) & (size-1)]); 3609 if (remaining > 1) { 3610 prefetch2cachelines(&items[next]); 3611 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3612 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3613 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3614 } 3615 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3616 } 3617 3618 static void 3619 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3620 { 3621 3622 ifmp_ring_check_drainage(txq->ift_br, budget); 3623 } 3624 3625 static uint32_t 3626 iflib_txq_can_drain(struct ifmp_ring *r) 3627 { 3628 iflib_txq_t txq = r->cookie; 3629 if_ctx_t ctx = txq->ift_ctx; 3630 3631 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3632 return (1); 3633 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3634 BUS_DMASYNC_POSTREAD); 3635 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3636 false)); 3637 } 3638 3639 static uint32_t 3640 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3641 { 3642 iflib_txq_t txq = r->cookie; 3643 if_ctx_t ctx = txq->ift_ctx; 3644 if_t ifp = ctx->ifc_ifp; 3645 struct mbuf *m, **mp; 3646 int avail, bytes_sent, consumed, count, err, i, in_use_prev; 3647 int mcast_sent, pkt_sent, reclaimed, txq_avail; 3648 bool do_prefetch, rang, ring; 3649 3650 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3651 !LINK_ACTIVE(ctx))) { 3652 DBG_COUNTER_INC(txq_drain_notready); 3653 return (0); 3654 } 3655 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3656 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3657 avail = IDXDIFF(pidx, cidx, r->size); 3658 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3659 DBG_COUNTER_INC(txq_drain_flushing); 3660 for (i = 0; i < avail; i++) { 3661 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3662 m_free(r->items[(cidx + i) & (r->size-1)]); 3663 r->items[(cidx + i) & (r->size-1)] = NULL; 3664 } 3665 return (avail); 3666 } 3667 3668 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3669 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3670 CALLOUT_LOCK(txq); 3671 callout_stop(&txq->ift_timer); 3672 CALLOUT_UNLOCK(txq); 3673 DBG_COUNTER_INC(txq_drain_oactive); 3674 return (0); 3675 } 3676 if (reclaimed) 3677 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3678 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3679 count = MIN(avail, TX_BATCH_SIZE); 3680 #ifdef INVARIANTS 3681 if (iflib_verbose_debug) 3682 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3683 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3684 #endif 3685 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3686 txq_avail = TXQ_AVAIL(txq); 3687 err = 0; 3688 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) { 3689 int rem = do_prefetch ? count - i : 0; 3690 3691 mp = _ring_peek_one(r, cidx, i, rem); 3692 MPASS(mp != NULL && *mp != NULL); 3693 if (__predict_false(*mp == (struct mbuf *)txq)) { 3694 consumed++; 3695 continue; 3696 } 3697 in_use_prev = txq->ift_in_use; 3698 err = iflib_encap(txq, mp); 3699 if (__predict_false(err)) { 3700 /* no room - bail out */ 3701 if (err == ENOBUFS) 3702 break; 3703 consumed++; 3704 /* we can't send this packet - skip it */ 3705 continue; 3706 } 3707 consumed++; 3708 pkt_sent++; 3709 m = *mp; 3710 DBG_COUNTER_INC(tx_sent); 3711 bytes_sent += m->m_pkthdr.len; 3712 mcast_sent += !!(m->m_flags & M_MCAST); 3713 txq_avail = TXQ_AVAIL(txq); 3714 3715 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3716 ETHER_BPF_MTAP(ifp, m); 3717 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3718 break; 3719 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3720 } 3721 3722 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3723 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3724 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3725 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3726 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3727 if (mcast_sent) 3728 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3729 #ifdef INVARIANTS 3730 if (iflib_verbose_debug) 3731 printf("consumed=%d\n", consumed); 3732 #endif 3733 return (consumed); 3734 } 3735 3736 static uint32_t 3737 iflib_txq_drain_always(struct ifmp_ring *r) 3738 { 3739 return (1); 3740 } 3741 3742 static uint32_t 3743 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3744 { 3745 int i, avail; 3746 struct mbuf **mp; 3747 iflib_txq_t txq; 3748 3749 txq = r->cookie; 3750 3751 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3752 CALLOUT_LOCK(txq); 3753 callout_stop(&txq->ift_timer); 3754 CALLOUT_UNLOCK(txq); 3755 3756 avail = IDXDIFF(pidx, cidx, r->size); 3757 for (i = 0; i < avail; i++) { 3758 mp = _ring_peek_one(r, cidx, i, avail - i); 3759 if (__predict_false(*mp == (struct mbuf *)txq)) 3760 continue; 3761 m_freem(*mp); 3762 DBG_COUNTER_INC(tx_frees); 3763 } 3764 MPASS(ifmp_ring_is_stalled(r) == 0); 3765 return (avail); 3766 } 3767 3768 static void 3769 iflib_ifmp_purge(iflib_txq_t txq) 3770 { 3771 struct ifmp_ring *r; 3772 3773 r = txq->ift_br; 3774 r->drain = iflib_txq_drain_free; 3775 r->can_drain = iflib_txq_drain_always; 3776 3777 ifmp_ring_check_drainage(r, r->size); 3778 3779 r->drain = iflib_txq_drain; 3780 r->can_drain = iflib_txq_can_drain; 3781 } 3782 3783 static void 3784 _task_fn_tx(void *context) 3785 { 3786 iflib_txq_t txq = context; 3787 if_ctx_t ctx = txq->ift_ctx; 3788 if_t ifp = ctx->ifc_ifp; 3789 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3790 3791 #ifdef IFLIB_DIAGNOSTICS 3792 txq->ift_cpu_exec_count[curcpu]++; 3793 #endif 3794 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 3795 return; 3796 #ifdef DEV_NETMAP 3797 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 3798 netmap_tx_irq(ifp, txq->ift_id)) 3799 goto skip_ifmp; 3800 #endif 3801 #ifdef ALTQ 3802 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3803 iflib_altq_if_start(ifp); 3804 #endif 3805 if (txq->ift_db_pending) 3806 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3807 else if (!abdicate) 3808 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3809 /* 3810 * When abdicating, we always need to check drainage, not just when we don't enqueue 3811 */ 3812 if (abdicate) 3813 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3814 #ifdef DEV_NETMAP 3815 skip_ifmp: 3816 #endif 3817 if (ctx->ifc_flags & IFC_LEGACY) 3818 IFDI_INTR_ENABLE(ctx); 3819 else 3820 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3821 } 3822 3823 static void 3824 _task_fn_rx(void *context) 3825 { 3826 iflib_rxq_t rxq = context; 3827 if_ctx_t ctx = rxq->ifr_ctx; 3828 uint8_t more; 3829 uint16_t budget; 3830 #ifdef DEV_NETMAP 3831 u_int work = 0; 3832 int nmirq; 3833 #endif 3834 3835 #ifdef IFLIB_DIAGNOSTICS 3836 rxq->ifr_cpu_exec_count[curcpu]++; 3837 #endif 3838 DBG_COUNTER_INC(task_fn_rxs); 3839 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3840 return; 3841 #ifdef DEV_NETMAP 3842 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 3843 if (nmirq != NM_IRQ_PASS) { 3844 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 3845 goto skip_rxeof; 3846 } 3847 #endif 3848 budget = ctx->ifc_sysctl_rx_budget; 3849 if (budget == 0) 3850 budget = 16; /* XXX */ 3851 more = iflib_rxeof(rxq, budget); 3852 #ifdef DEV_NETMAP 3853 skip_rxeof: 3854 #endif 3855 if ((more & IFLIB_RXEOF_MORE) == 0) { 3856 if (ctx->ifc_flags & IFC_LEGACY) 3857 IFDI_INTR_ENABLE(ctx); 3858 else 3859 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3860 DBG_COUNTER_INC(rx_intr_enables); 3861 } 3862 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3863 return; 3864 3865 if (more & IFLIB_RXEOF_MORE) 3866 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3867 else if (more & IFLIB_RXEOF_EMPTY) 3868 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 3869 } 3870 3871 static void 3872 _task_fn_admin(void *context) 3873 { 3874 if_ctx_t ctx = context; 3875 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3876 iflib_txq_t txq; 3877 int i; 3878 bool oactive, running, do_reset, do_watchdog, in_detach; 3879 3880 STATE_LOCK(ctx); 3881 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3882 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3883 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3884 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3885 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3886 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3887 STATE_UNLOCK(ctx); 3888 3889 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3890 return; 3891 if (in_detach) 3892 return; 3893 3894 CTX_LOCK(ctx); 3895 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3896 CALLOUT_LOCK(txq); 3897 callout_stop(&txq->ift_timer); 3898 CALLOUT_UNLOCK(txq); 3899 } 3900 if (do_watchdog) { 3901 ctx->ifc_watchdog_events++; 3902 IFDI_WATCHDOG_RESET(ctx); 3903 } 3904 IFDI_UPDATE_ADMIN_STATUS(ctx); 3905 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3906 callout_reset_on(&txq->ift_timer, hz / 2, iflib_timer, txq, 3907 txq->ift_timer.c_cpu); 3908 } 3909 IFDI_LINK_INTR_ENABLE(ctx); 3910 if (do_reset) 3911 iflib_if_init_locked(ctx); 3912 CTX_UNLOCK(ctx); 3913 3914 if (LINK_ACTIVE(ctx) == 0) 3915 return; 3916 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3917 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3918 } 3919 3920 static void 3921 _task_fn_iov(void *context) 3922 { 3923 if_ctx_t ctx = context; 3924 3925 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3926 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3927 return; 3928 3929 CTX_LOCK(ctx); 3930 IFDI_VFLR_HANDLE(ctx); 3931 CTX_UNLOCK(ctx); 3932 } 3933 3934 static int 3935 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3936 { 3937 int err; 3938 if_int_delay_info_t info; 3939 if_ctx_t ctx; 3940 3941 info = (if_int_delay_info_t)arg1; 3942 ctx = info->iidi_ctx; 3943 info->iidi_req = req; 3944 info->iidi_oidp = oidp; 3945 CTX_LOCK(ctx); 3946 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3947 CTX_UNLOCK(ctx); 3948 return (err); 3949 } 3950 3951 /********************************************************************* 3952 * 3953 * IFNET FUNCTIONS 3954 * 3955 **********************************************************************/ 3956 3957 static void 3958 iflib_if_init_locked(if_ctx_t ctx) 3959 { 3960 iflib_stop(ctx); 3961 iflib_init_locked(ctx); 3962 } 3963 3964 static void 3965 iflib_if_init(void *arg) 3966 { 3967 if_ctx_t ctx = arg; 3968 3969 CTX_LOCK(ctx); 3970 iflib_if_init_locked(ctx); 3971 CTX_UNLOCK(ctx); 3972 } 3973 3974 static int 3975 iflib_if_transmit(if_t ifp, struct mbuf *m) 3976 { 3977 if_ctx_t ctx = if_getsoftc(ifp); 3978 3979 iflib_txq_t txq; 3980 int err, qidx; 3981 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3982 3983 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3984 DBG_COUNTER_INC(tx_frees); 3985 m_freem(m); 3986 return (ENETDOWN); 3987 } 3988 3989 MPASS(m->m_nextpkt == NULL); 3990 /* ALTQ-enabled interfaces always use queue 0. */ 3991 qidx = 0; 3992 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3993 qidx = QIDX(ctx, m); 3994 /* 3995 * XXX calculate buf_ring based on flowid (divvy up bits?) 3996 */ 3997 txq = &ctx->ifc_txqs[qidx]; 3998 3999 #ifdef DRIVER_BACKPRESSURE 4000 if (txq->ift_closed) { 4001 while (m != NULL) { 4002 next = m->m_nextpkt; 4003 m->m_nextpkt = NULL; 4004 m_freem(m); 4005 DBG_COUNTER_INC(tx_frees); 4006 m = next; 4007 } 4008 return (ENOBUFS); 4009 } 4010 #endif 4011 #ifdef notyet 4012 qidx = count = 0; 4013 mp = marr; 4014 next = m; 4015 do { 4016 count++; 4017 next = next->m_nextpkt; 4018 } while (next != NULL); 4019 4020 if (count > nitems(marr)) 4021 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4022 /* XXX check nextpkt */ 4023 m_freem(m); 4024 /* XXX simplify for now */ 4025 DBG_COUNTER_INC(tx_frees); 4026 return (ENOBUFS); 4027 } 4028 for (next = m, i = 0; next != NULL; i++) { 4029 mp[i] = next; 4030 next = next->m_nextpkt; 4031 mp[i]->m_nextpkt = NULL; 4032 } 4033 #endif 4034 DBG_COUNTER_INC(tx_seen); 4035 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4036 4037 if (abdicate) 4038 GROUPTASK_ENQUEUE(&txq->ift_task); 4039 if (err) { 4040 if (!abdicate) 4041 GROUPTASK_ENQUEUE(&txq->ift_task); 4042 /* support forthcoming later */ 4043 #ifdef DRIVER_BACKPRESSURE 4044 txq->ift_closed = TRUE; 4045 #endif 4046 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4047 m_freem(m); 4048 DBG_COUNTER_INC(tx_frees); 4049 } 4050 4051 return (err); 4052 } 4053 4054 #ifdef ALTQ 4055 /* 4056 * The overall approach to integrating iflib with ALTQ is to continue to use 4057 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4058 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4059 * is redundant/unnecessary, but doing so minimizes the amount of 4060 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4061 * redundantly queueing to an intermediate mp_ring is swamped by the 4062 * performance limitations inherent in using ALTQ. 4063 * 4064 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4065 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4066 * given interface. If ALTQ is enabled for an interface, then all 4067 * transmitted packets for that interface will be submitted to the ALTQ 4068 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4069 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4070 * update stats that the iflib machinery handles, and which is sensitve to 4071 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4072 * will be installed as the start routine for use by ALTQ facilities that 4073 * need to trigger queue drains on a scheduled basis. 4074 * 4075 */ 4076 static void 4077 iflib_altq_if_start(if_t ifp) 4078 { 4079 struct ifaltq *ifq = &ifp->if_snd; 4080 struct mbuf *m; 4081 4082 IFQ_LOCK(ifq); 4083 IFQ_DEQUEUE_NOLOCK(ifq, m); 4084 while (m != NULL) { 4085 iflib_if_transmit(ifp, m); 4086 IFQ_DEQUEUE_NOLOCK(ifq, m); 4087 } 4088 IFQ_UNLOCK(ifq); 4089 } 4090 4091 static int 4092 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4093 { 4094 int err; 4095 4096 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4097 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4098 if (err == 0) 4099 iflib_altq_if_start(ifp); 4100 } else 4101 err = iflib_if_transmit(ifp, m); 4102 4103 return (err); 4104 } 4105 #endif /* ALTQ */ 4106 4107 static void 4108 iflib_if_qflush(if_t ifp) 4109 { 4110 if_ctx_t ctx = if_getsoftc(ifp); 4111 iflib_txq_t txq = ctx->ifc_txqs; 4112 int i; 4113 4114 STATE_LOCK(ctx); 4115 ctx->ifc_flags |= IFC_QFLUSH; 4116 STATE_UNLOCK(ctx); 4117 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4118 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4119 iflib_txq_check_drain(txq, 0); 4120 STATE_LOCK(ctx); 4121 ctx->ifc_flags &= ~IFC_QFLUSH; 4122 STATE_UNLOCK(ctx); 4123 4124 /* 4125 * When ALTQ is enabled, this will also take care of purging the 4126 * ALTQ queue(s). 4127 */ 4128 if_qflush(ifp); 4129 } 4130 4131 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4132 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4133 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4134 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP) 4135 4136 static int 4137 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4138 { 4139 if_ctx_t ctx = if_getsoftc(ifp); 4140 struct ifreq *ifr = (struct ifreq *)data; 4141 #if defined(INET) || defined(INET6) 4142 struct ifaddr *ifa = (struct ifaddr *)data; 4143 #endif 4144 bool avoid_reset = false; 4145 int err = 0, reinit = 0, bits; 4146 4147 switch (command) { 4148 case SIOCSIFADDR: 4149 #ifdef INET 4150 if (ifa->ifa_addr->sa_family == AF_INET) 4151 avoid_reset = true; 4152 #endif 4153 #ifdef INET6 4154 if (ifa->ifa_addr->sa_family == AF_INET6) 4155 avoid_reset = true; 4156 #endif 4157 /* 4158 ** Calling init results in link renegotiation, 4159 ** so we avoid doing it when possible. 4160 */ 4161 if (avoid_reset) { 4162 if_setflagbits(ifp, IFF_UP,0); 4163 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4164 reinit = 1; 4165 #ifdef INET 4166 if (!(if_getflags(ifp) & IFF_NOARP)) 4167 arp_ifinit(ifp, ifa); 4168 #endif 4169 } else 4170 err = ether_ioctl(ifp, command, data); 4171 break; 4172 case SIOCSIFMTU: 4173 CTX_LOCK(ctx); 4174 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4175 CTX_UNLOCK(ctx); 4176 break; 4177 } 4178 bits = if_getdrvflags(ifp); 4179 /* stop the driver and free any clusters before proceeding */ 4180 iflib_stop(ctx); 4181 4182 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4183 STATE_LOCK(ctx); 4184 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4185 ctx->ifc_flags |= IFC_MULTISEG; 4186 else 4187 ctx->ifc_flags &= ~IFC_MULTISEG; 4188 STATE_UNLOCK(ctx); 4189 err = if_setmtu(ifp, ifr->ifr_mtu); 4190 } 4191 iflib_init_locked(ctx); 4192 STATE_LOCK(ctx); 4193 if_setdrvflags(ifp, bits); 4194 STATE_UNLOCK(ctx); 4195 CTX_UNLOCK(ctx); 4196 break; 4197 case SIOCSIFFLAGS: 4198 CTX_LOCK(ctx); 4199 if (if_getflags(ifp) & IFF_UP) { 4200 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4201 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4202 (IFF_PROMISC | IFF_ALLMULTI)) { 4203 CTX_UNLOCK(ctx); 4204 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4205 CTX_LOCK(ctx); 4206 } 4207 } else 4208 reinit = 1; 4209 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4210 iflib_stop(ctx); 4211 } 4212 ctx->ifc_if_flags = if_getflags(ifp); 4213 CTX_UNLOCK(ctx); 4214 break; 4215 case SIOCADDMULTI: 4216 case SIOCDELMULTI: 4217 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4218 CTX_LOCK(ctx); 4219 IFDI_INTR_DISABLE(ctx); 4220 IFDI_MULTI_SET(ctx); 4221 IFDI_INTR_ENABLE(ctx); 4222 CTX_UNLOCK(ctx); 4223 } 4224 break; 4225 case SIOCSIFMEDIA: 4226 CTX_LOCK(ctx); 4227 IFDI_MEDIA_SET(ctx); 4228 CTX_UNLOCK(ctx); 4229 /* FALLTHROUGH */ 4230 case SIOCGIFMEDIA: 4231 case SIOCGIFXMEDIA: 4232 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4233 break; 4234 case SIOCGI2C: 4235 { 4236 struct ifi2creq i2c; 4237 4238 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4239 if (err != 0) 4240 break; 4241 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4242 err = EINVAL; 4243 break; 4244 } 4245 if (i2c.len > sizeof(i2c.data)) { 4246 err = EINVAL; 4247 break; 4248 } 4249 4250 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4251 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4252 sizeof(i2c)); 4253 break; 4254 } 4255 case SIOCSIFCAP: 4256 { 4257 int mask, setmask, oldmask; 4258 4259 oldmask = if_getcapenable(ifp); 4260 mask = ifr->ifr_reqcap ^ oldmask; 4261 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP; 4262 setmask = 0; 4263 #ifdef TCP_OFFLOAD 4264 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4265 #endif 4266 setmask |= (mask & IFCAP_FLAGS); 4267 setmask |= (mask & IFCAP_WOL); 4268 4269 /* 4270 * If any RX csum has changed, change all the ones that 4271 * are supported by the driver. 4272 */ 4273 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4274 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4275 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4276 } 4277 4278 /* 4279 * want to ensure that traffic has stopped before we change any of the flags 4280 */ 4281 if (setmask) { 4282 CTX_LOCK(ctx); 4283 bits = if_getdrvflags(ifp); 4284 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4285 iflib_stop(ctx); 4286 STATE_LOCK(ctx); 4287 if_togglecapenable(ifp, setmask); 4288 STATE_UNLOCK(ctx); 4289 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4290 iflib_init_locked(ctx); 4291 STATE_LOCK(ctx); 4292 if_setdrvflags(ifp, bits); 4293 STATE_UNLOCK(ctx); 4294 CTX_UNLOCK(ctx); 4295 } 4296 if_vlancap(ifp); 4297 break; 4298 } 4299 case SIOCGPRIVATE_0: 4300 case SIOCSDRVSPEC: 4301 case SIOCGDRVSPEC: 4302 CTX_LOCK(ctx); 4303 err = IFDI_PRIV_IOCTL(ctx, command, data); 4304 CTX_UNLOCK(ctx); 4305 break; 4306 default: 4307 err = ether_ioctl(ifp, command, data); 4308 break; 4309 } 4310 if (reinit) 4311 iflib_if_init(ctx); 4312 return (err); 4313 } 4314 4315 static uint64_t 4316 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4317 { 4318 if_ctx_t ctx = if_getsoftc(ifp); 4319 4320 return (IFDI_GET_COUNTER(ctx, cnt)); 4321 } 4322 4323 /********************************************************************* 4324 * 4325 * OTHER FUNCTIONS EXPORTED TO THE STACK 4326 * 4327 **********************************************************************/ 4328 4329 static void 4330 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4331 { 4332 if_ctx_t ctx = if_getsoftc(ifp); 4333 4334 if ((void *)ctx != arg) 4335 return; 4336 4337 if ((vtag == 0) || (vtag > 4095)) 4338 return; 4339 4340 if (iflib_in_detach(ctx)) 4341 return; 4342 4343 CTX_LOCK(ctx); 4344 /* Driver may need all untagged packets to be flushed */ 4345 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4346 iflib_stop(ctx); 4347 IFDI_VLAN_REGISTER(ctx, vtag); 4348 /* Re-init to load the changes, if required */ 4349 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4350 iflib_init_locked(ctx); 4351 CTX_UNLOCK(ctx); 4352 } 4353 4354 static void 4355 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4356 { 4357 if_ctx_t ctx = if_getsoftc(ifp); 4358 4359 if ((void *)ctx != arg) 4360 return; 4361 4362 if ((vtag == 0) || (vtag > 4095)) 4363 return; 4364 4365 CTX_LOCK(ctx); 4366 /* Driver may need all tagged packets to be flushed */ 4367 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4368 iflib_stop(ctx); 4369 IFDI_VLAN_UNREGISTER(ctx, vtag); 4370 /* Re-init to load the changes, if required */ 4371 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4372 iflib_init_locked(ctx); 4373 CTX_UNLOCK(ctx); 4374 } 4375 4376 static void 4377 iflib_led_func(void *arg, int onoff) 4378 { 4379 if_ctx_t ctx = arg; 4380 4381 CTX_LOCK(ctx); 4382 IFDI_LED_FUNC(ctx, onoff); 4383 CTX_UNLOCK(ctx); 4384 } 4385 4386 /********************************************************************* 4387 * 4388 * BUS FUNCTION DEFINITIONS 4389 * 4390 **********************************************************************/ 4391 4392 int 4393 iflib_device_probe(device_t dev) 4394 { 4395 const pci_vendor_info_t *ent; 4396 if_shared_ctx_t sctx; 4397 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4398 uint16_t pci_vendor_id; 4399 4400 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4401 return (ENOTSUP); 4402 4403 pci_vendor_id = pci_get_vendor(dev); 4404 pci_device_id = pci_get_device(dev); 4405 pci_subvendor_id = pci_get_subvendor(dev); 4406 pci_subdevice_id = pci_get_subdevice(dev); 4407 pci_rev_id = pci_get_revid(dev); 4408 if (sctx->isc_parse_devinfo != NULL) 4409 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4410 4411 ent = sctx->isc_vendor_info; 4412 while (ent->pvi_vendor_id != 0) { 4413 if (pci_vendor_id != ent->pvi_vendor_id) { 4414 ent++; 4415 continue; 4416 } 4417 if ((pci_device_id == ent->pvi_device_id) && 4418 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4419 (ent->pvi_subvendor_id == 0)) && 4420 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4421 (ent->pvi_subdevice_id == 0)) && 4422 ((pci_rev_id == ent->pvi_rev_id) || 4423 (ent->pvi_rev_id == 0))) { 4424 device_set_desc_copy(dev, ent->pvi_name); 4425 /* this needs to be changed to zero if the bus probing code 4426 * ever stops re-probing on best match because the sctx 4427 * may have its values over written by register calls 4428 * in subsequent probes 4429 */ 4430 return (BUS_PROBE_DEFAULT); 4431 } 4432 ent++; 4433 } 4434 return (ENXIO); 4435 } 4436 4437 int 4438 iflib_device_probe_vendor(device_t dev) 4439 { 4440 int probe; 4441 4442 probe = iflib_device_probe(dev); 4443 if (probe == BUS_PROBE_DEFAULT) 4444 return (BUS_PROBE_VENDOR); 4445 else 4446 return (probe); 4447 } 4448 4449 static void 4450 iflib_reset_qvalues(if_ctx_t ctx) 4451 { 4452 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4453 if_shared_ctx_t sctx = ctx->ifc_sctx; 4454 device_t dev = ctx->ifc_dev; 4455 int i; 4456 4457 if (ctx->ifc_sysctl_ntxqs != 0) 4458 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4459 if (ctx->ifc_sysctl_nrxqs != 0) 4460 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4461 4462 for (i = 0; i < sctx->isc_ntxqs; i++) { 4463 if (ctx->ifc_sysctl_ntxds[i] != 0) 4464 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4465 else 4466 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4467 } 4468 4469 for (i = 0; i < sctx->isc_nrxqs; i++) { 4470 if (ctx->ifc_sysctl_nrxds[i] != 0) 4471 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4472 else 4473 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4474 } 4475 4476 for (i = 0; i < sctx->isc_nrxqs; i++) { 4477 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4478 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4479 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4480 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4481 } 4482 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4483 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4484 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4485 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4486 } 4487 if (!powerof2(scctx->isc_nrxd[i])) { 4488 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4489 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4490 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4491 } 4492 } 4493 4494 for (i = 0; i < sctx->isc_ntxqs; i++) { 4495 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4496 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4497 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4498 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4499 } 4500 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4501 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4502 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4503 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4504 } 4505 if (!powerof2(scctx->isc_ntxd[i])) { 4506 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4507 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4508 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4509 } 4510 } 4511 } 4512 4513 static void 4514 iflib_add_pfil(if_ctx_t ctx) 4515 { 4516 struct pfil_head *pfil; 4517 struct pfil_head_args pa; 4518 iflib_rxq_t rxq; 4519 int i; 4520 4521 pa.pa_version = PFIL_VERSION; 4522 pa.pa_flags = PFIL_IN; 4523 pa.pa_type = PFIL_TYPE_ETHERNET; 4524 pa.pa_headname = ctx->ifc_ifp->if_xname; 4525 pfil = pfil_head_register(&pa); 4526 4527 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4528 rxq->pfil = pfil; 4529 } 4530 } 4531 4532 static void 4533 iflib_rem_pfil(if_ctx_t ctx) 4534 { 4535 struct pfil_head *pfil; 4536 iflib_rxq_t rxq; 4537 int i; 4538 4539 rxq = ctx->ifc_rxqs; 4540 pfil = rxq->pfil; 4541 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4542 rxq->pfil = NULL; 4543 } 4544 pfil_head_unregister(pfil); 4545 } 4546 4547 static uint16_t 4548 get_ctx_core_offset(if_ctx_t ctx) 4549 { 4550 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4551 struct cpu_offset *op; 4552 uint16_t qc; 4553 uint16_t ret = ctx->ifc_sysctl_core_offset; 4554 4555 if (ret != CORE_OFFSET_UNSPECIFIED) 4556 return (ret); 4557 4558 if (ctx->ifc_sysctl_separate_txrx) 4559 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets; 4560 else 4561 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets); 4562 4563 mtx_lock(&cpu_offset_mtx); 4564 SLIST_FOREACH(op, &cpu_offsets, entries) { 4565 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4566 ret = op->offset; 4567 op->offset += qc; 4568 MPASS(op->refcount < UINT_MAX); 4569 op->refcount++; 4570 break; 4571 } 4572 } 4573 if (ret == CORE_OFFSET_UNSPECIFIED) { 4574 ret = 0; 4575 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4576 M_NOWAIT | M_ZERO); 4577 if (op == NULL) { 4578 device_printf(ctx->ifc_dev, 4579 "allocation for cpu offset failed.\n"); 4580 } else { 4581 op->offset = qc; 4582 op->refcount = 1; 4583 CPU_COPY(&ctx->ifc_cpus, &op->set); 4584 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4585 } 4586 } 4587 mtx_unlock(&cpu_offset_mtx); 4588 4589 return (ret); 4590 } 4591 4592 static void 4593 unref_ctx_core_offset(if_ctx_t ctx) 4594 { 4595 struct cpu_offset *op, *top; 4596 4597 mtx_lock(&cpu_offset_mtx); 4598 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4599 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4600 MPASS(op->refcount > 0); 4601 op->refcount--; 4602 if (op->refcount == 0) { 4603 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4604 free(op, M_IFLIB); 4605 } 4606 break; 4607 } 4608 } 4609 mtx_unlock(&cpu_offset_mtx); 4610 } 4611 4612 int 4613 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4614 { 4615 if_ctx_t ctx; 4616 if_t ifp; 4617 if_softc_ctx_t scctx; 4618 kobjop_desc_t kobj_desc; 4619 kobj_method_t *kobj_method; 4620 int err, msix, rid; 4621 int num_txd, num_rxd; 4622 4623 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4624 4625 if (sc == NULL) { 4626 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4627 device_set_softc(dev, ctx); 4628 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4629 } 4630 4631 ctx->ifc_sctx = sctx; 4632 ctx->ifc_dev = dev; 4633 ctx->ifc_softc = sc; 4634 4635 if ((err = iflib_register(ctx)) != 0) { 4636 device_printf(dev, "iflib_register failed %d\n", err); 4637 goto fail_ctx_free; 4638 } 4639 iflib_add_device_sysctl_pre(ctx); 4640 4641 scctx = &ctx->ifc_softc_ctx; 4642 ifp = ctx->ifc_ifp; 4643 4644 iflib_reset_qvalues(ctx); 4645 CTX_LOCK(ctx); 4646 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4647 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4648 goto fail_unlock; 4649 } 4650 _iflib_pre_assert(scctx); 4651 ctx->ifc_txrx = *scctx->isc_txrx; 4652 4653 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 4654 ctx->ifc_mediap = scctx->isc_media; 4655 4656 #ifdef INVARIANTS 4657 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4658 MPASS(scctx->isc_tx_csum_flags); 4659 #endif 4660 4661 if_setcapabilities(ifp, 4662 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP); 4663 if_setcapenable(ifp, 4664 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP); 4665 4666 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4667 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4668 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4669 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4670 4671 num_txd = iflib_num_tx_descs(ctx); 4672 num_rxd = iflib_num_rx_descs(ctx); 4673 4674 /* XXX change for per-queue sizes */ 4675 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4676 num_txd, num_rxd); 4677 4678 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 4679 scctx->isc_tx_nsegments = max(1, num_txd / 4680 MAX_SINGLE_PACKET_FRACTION); 4681 if (scctx->isc_tx_tso_segments_max > num_txd / 4682 MAX_SINGLE_PACKET_FRACTION) 4683 scctx->isc_tx_tso_segments_max = max(1, 4684 num_txd / MAX_SINGLE_PACKET_FRACTION); 4685 4686 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4687 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4688 /* 4689 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4690 * but some MACs do. 4691 */ 4692 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4693 IP_MAXPACKET)); 4694 /* 4695 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4696 * into account. In the worst case, each of these calls will 4697 * add another mbuf and, thus, the requirement for another DMA 4698 * segment. So for best performance, it doesn't make sense to 4699 * advertize a maximum of TSO segments that typically will 4700 * require defragmentation in iflib_encap(). 4701 */ 4702 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4703 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4704 } 4705 if (scctx->isc_rss_table_size == 0) 4706 scctx->isc_rss_table_size = 64; 4707 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4708 4709 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4710 /* XXX format name */ 4711 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4712 NULL, NULL, "admin"); 4713 4714 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4715 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4716 device_printf(dev, "Unable to fetch CPU list\n"); 4717 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4718 } 4719 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4720 4721 /* 4722 ** Now set up MSI or MSI-X, should return us the number of supported 4723 ** vectors (will be 1 for a legacy interrupt and MSI). 4724 */ 4725 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4726 msix = scctx->isc_vectors; 4727 } else if (scctx->isc_msix_bar != 0) 4728 /* 4729 * The simple fact that isc_msix_bar is not 0 does not mean we 4730 * we have a good value there that is known to work. 4731 */ 4732 msix = iflib_msix_init(ctx); 4733 else { 4734 scctx->isc_vectors = 1; 4735 scctx->isc_ntxqsets = 1; 4736 scctx->isc_nrxqsets = 1; 4737 scctx->isc_intr = IFLIB_INTR_LEGACY; 4738 msix = 0; 4739 } 4740 /* Get memory for the station queues */ 4741 if ((err = iflib_queues_alloc(ctx))) { 4742 device_printf(dev, "Unable to allocate queue memory\n"); 4743 goto fail_intr_free; 4744 } 4745 4746 if ((err = iflib_qset_structures_setup(ctx))) 4747 goto fail_queues; 4748 4749 /* 4750 * Now that we know how many queues there are, get the core offset. 4751 */ 4752 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 4753 4754 if (msix > 1) { 4755 /* 4756 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 4757 * aren't the default NULL implementation. 4758 */ 4759 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 4760 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4761 kobj_desc); 4762 if (kobj_method == &kobj_desc->deflt) { 4763 device_printf(dev, 4764 "MSI-X requires ifdi_rx_queue_intr_enable method"); 4765 err = EOPNOTSUPP; 4766 goto fail_queues; 4767 } 4768 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 4769 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4770 kobj_desc); 4771 if (kobj_method == &kobj_desc->deflt) { 4772 device_printf(dev, 4773 "MSI-X requires ifdi_tx_queue_intr_enable method"); 4774 err = EOPNOTSUPP; 4775 goto fail_queues; 4776 } 4777 4778 /* 4779 * Assign the MSI-X vectors. 4780 * Note that the default NULL ifdi_msix_intr_assign method will 4781 * fail here, too. 4782 */ 4783 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 4784 if (err != 0) { 4785 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 4786 err); 4787 goto fail_queues; 4788 } 4789 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 4790 rid = 0; 4791 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4792 MPASS(msix == 1); 4793 rid = 1; 4794 } 4795 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4796 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4797 goto fail_queues; 4798 } 4799 } else { 4800 device_printf(dev, 4801 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 4802 err = ENODEV; 4803 goto fail_intr_free; 4804 } 4805 4806 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4807 4808 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4809 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4810 goto fail_detach; 4811 } 4812 4813 /* 4814 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4815 * This must appear after the call to ether_ifattach() because 4816 * ether_ifattach() sets if_hdrlen to the default value. 4817 */ 4818 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4819 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4820 4821 if ((err = iflib_netmap_attach(ctx))) { 4822 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4823 goto fail_detach; 4824 } 4825 *ctxp = ctx; 4826 4827 DEBUGNET_SET(ctx->ifc_ifp, iflib); 4828 4829 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4830 iflib_add_device_sysctl_post(ctx); 4831 iflib_add_pfil(ctx); 4832 ctx->ifc_flags |= IFC_INIT_DONE; 4833 CTX_UNLOCK(ctx); 4834 4835 return (0); 4836 4837 fail_detach: 4838 ether_ifdetach(ctx->ifc_ifp); 4839 fail_intr_free: 4840 iflib_free_intr_mem(ctx); 4841 fail_queues: 4842 iflib_tx_structures_free(ctx); 4843 iflib_rx_structures_free(ctx); 4844 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task); 4845 IFDI_DETACH(ctx); 4846 fail_unlock: 4847 CTX_UNLOCK(ctx); 4848 iflib_deregister(ctx); 4849 fail_ctx_free: 4850 device_set_softc(ctx->ifc_dev, NULL); 4851 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4852 free(ctx->ifc_softc, M_IFLIB); 4853 free(ctx, M_IFLIB); 4854 return (err); 4855 } 4856 4857 int 4858 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4859 struct iflib_cloneattach_ctx *clctx) 4860 { 4861 int num_txd, num_rxd; 4862 int err; 4863 if_ctx_t ctx; 4864 if_t ifp; 4865 if_softc_ctx_t scctx; 4866 int i; 4867 void *sc; 4868 4869 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4870 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4871 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4872 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4873 ctx->ifc_flags |= IFC_PSEUDO; 4874 4875 ctx->ifc_sctx = sctx; 4876 ctx->ifc_softc = sc; 4877 ctx->ifc_dev = dev; 4878 4879 if ((err = iflib_register(ctx)) != 0) { 4880 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4881 goto fail_ctx_free; 4882 } 4883 iflib_add_device_sysctl_pre(ctx); 4884 4885 scctx = &ctx->ifc_softc_ctx; 4886 ifp = ctx->ifc_ifp; 4887 4888 iflib_reset_qvalues(ctx); 4889 CTX_LOCK(ctx); 4890 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4891 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4892 goto fail_unlock; 4893 } 4894 if (sctx->isc_flags & IFLIB_GEN_MAC) 4895 ether_gen_addr(ifp, &ctx->ifc_mac); 4896 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4897 clctx->cc_params)) != 0) { 4898 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4899 goto fail_unlock; 4900 } 4901 #ifdef INVARIANTS 4902 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4903 MPASS(scctx->isc_tx_csum_flags); 4904 #endif 4905 4906 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4907 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4908 4909 ifp->if_flags |= IFF_NOGROUP; 4910 if (sctx->isc_flags & IFLIB_PSEUDO) { 4911 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4912 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4913 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) { 4914 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4915 } else { 4916 if_attach(ctx->ifc_ifp); 4917 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t)); 4918 } 4919 4920 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4921 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4922 goto fail_detach; 4923 } 4924 *ctxp = ctx; 4925 4926 /* 4927 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4928 * This must appear after the call to ether_ifattach() because 4929 * ether_ifattach() sets if_hdrlen to the default value. 4930 */ 4931 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4932 if_setifheaderlen(ifp, 4933 sizeof(struct ether_vlan_header)); 4934 4935 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4936 iflib_add_device_sysctl_post(ctx); 4937 ctx->ifc_flags |= IFC_INIT_DONE; 4938 CTX_UNLOCK(ctx); 4939 return (0); 4940 } 4941 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4942 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4943 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4944 4945 _iflib_pre_assert(scctx); 4946 ctx->ifc_txrx = *scctx->isc_txrx; 4947 4948 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4949 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4950 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4951 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4952 4953 num_txd = iflib_num_tx_descs(ctx); 4954 num_rxd = iflib_num_rx_descs(ctx); 4955 4956 /* XXX change for per-queue sizes */ 4957 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4958 num_txd, num_rxd); 4959 4960 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 4961 scctx->isc_tx_nsegments = max(1, num_txd / 4962 MAX_SINGLE_PACKET_FRACTION); 4963 if (scctx->isc_tx_tso_segments_max > num_txd / 4964 MAX_SINGLE_PACKET_FRACTION) 4965 scctx->isc_tx_tso_segments_max = max(1, 4966 num_txd / MAX_SINGLE_PACKET_FRACTION); 4967 4968 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4969 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4970 /* 4971 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4972 * but some MACs do. 4973 */ 4974 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4975 IP_MAXPACKET)); 4976 /* 4977 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4978 * into account. In the worst case, each of these calls will 4979 * add another mbuf and, thus, the requirement for another DMA 4980 * segment. So for best performance, it doesn't make sense to 4981 * advertize a maximum of TSO segments that typically will 4982 * require defragmentation in iflib_encap(). 4983 */ 4984 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4985 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4986 } 4987 if (scctx->isc_rss_table_size == 0) 4988 scctx->isc_rss_table_size = 64; 4989 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4990 4991 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4992 /* XXX format name */ 4993 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4994 NULL, NULL, "admin"); 4995 4996 /* XXX --- can support > 1 -- but keep it simple for now */ 4997 scctx->isc_intr = IFLIB_INTR_LEGACY; 4998 4999 /* Get memory for the station queues */ 5000 if ((err = iflib_queues_alloc(ctx))) { 5001 device_printf(dev, "Unable to allocate queue memory\n"); 5002 goto fail_iflib_detach; 5003 } 5004 5005 if ((err = iflib_qset_structures_setup(ctx))) { 5006 device_printf(dev, "qset structure setup failed %d\n", err); 5007 goto fail_queues; 5008 } 5009 5010 /* 5011 * XXX What if anything do we want to do about interrupts? 5012 */ 5013 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5014 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5015 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5016 goto fail_detach; 5017 } 5018 5019 /* 5020 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5021 * This must appear after the call to ether_ifattach() because 5022 * ether_ifattach() sets if_hdrlen to the default value. 5023 */ 5024 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5025 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5026 5027 /* XXX handle more than one queue */ 5028 for (i = 0; i < scctx->isc_nrxqsets; i++) 5029 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 5030 5031 *ctxp = ctx; 5032 5033 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5034 iflib_add_device_sysctl_post(ctx); 5035 ctx->ifc_flags |= IFC_INIT_DONE; 5036 CTX_UNLOCK(ctx); 5037 5038 return (0); 5039 fail_detach: 5040 ether_ifdetach(ctx->ifc_ifp); 5041 fail_queues: 5042 iflib_tx_structures_free(ctx); 5043 iflib_rx_structures_free(ctx); 5044 fail_iflib_detach: 5045 IFDI_DETACH(ctx); 5046 fail_unlock: 5047 CTX_UNLOCK(ctx); 5048 iflib_deregister(ctx); 5049 fail_ctx_free: 5050 free(ctx->ifc_softc, M_IFLIB); 5051 free(ctx, M_IFLIB); 5052 return (err); 5053 } 5054 5055 int 5056 iflib_pseudo_deregister(if_ctx_t ctx) 5057 { 5058 if_t ifp = ctx->ifc_ifp; 5059 if_shared_ctx_t sctx = ctx->ifc_sctx; 5060 iflib_txq_t txq; 5061 iflib_rxq_t rxq; 5062 int i, j; 5063 struct taskqgroup *tqg; 5064 iflib_fl_t fl; 5065 5066 /* Unregister VLAN event handlers early */ 5067 iflib_unregister_vlan_handlers(ctx); 5068 5069 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5070 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) { 5071 bpfdetach(ifp); 5072 if_detach(ifp); 5073 } else { 5074 ether_ifdetach(ifp); 5075 } 5076 /* XXX drain any dependent tasks */ 5077 tqg = qgroup_if_io_tqg; 5078 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5079 callout_drain(&txq->ift_timer); 5080 #ifdef DEV_NETMAP 5081 callout_drain(&txq->ift_netmap_timer); 5082 #endif /* DEV_NETMAP */ 5083 if (txq->ift_task.gt_uniq != NULL) 5084 taskqgroup_detach(tqg, &txq->ift_task); 5085 } 5086 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5087 callout_drain(&rxq->ifr_watchdog); 5088 if (rxq->ifr_task.gt_uniq != NULL) 5089 taskqgroup_detach(tqg, &rxq->ifr_task); 5090 5091 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5092 free(fl->ifl_rx_bitmap, M_IFLIB); 5093 } 5094 tqg = qgroup_if_config_tqg; 5095 if (ctx->ifc_admin_task.gt_uniq != NULL) 5096 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5097 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5098 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5099 5100 iflib_tx_structures_free(ctx); 5101 iflib_rx_structures_free(ctx); 5102 5103 iflib_deregister(ctx); 5104 5105 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5106 free(ctx->ifc_softc, M_IFLIB); 5107 free(ctx, M_IFLIB); 5108 return (0); 5109 } 5110 5111 int 5112 iflib_device_attach(device_t dev) 5113 { 5114 if_ctx_t ctx; 5115 if_shared_ctx_t sctx; 5116 5117 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5118 return (ENOTSUP); 5119 5120 pci_enable_busmaster(dev); 5121 5122 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5123 } 5124 5125 int 5126 iflib_device_deregister(if_ctx_t ctx) 5127 { 5128 if_t ifp = ctx->ifc_ifp; 5129 iflib_txq_t txq; 5130 iflib_rxq_t rxq; 5131 device_t dev = ctx->ifc_dev; 5132 int i, j; 5133 struct taskqgroup *tqg; 5134 iflib_fl_t fl; 5135 5136 /* Make sure VLANS are not using driver */ 5137 if (if_vlantrunkinuse(ifp)) { 5138 device_printf(dev, "Vlan in use, detach first\n"); 5139 return (EBUSY); 5140 } 5141 #ifdef PCI_IOV 5142 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5143 device_printf(dev, "SR-IOV in use; detach first.\n"); 5144 return (EBUSY); 5145 } 5146 #endif 5147 5148 STATE_LOCK(ctx); 5149 ctx->ifc_flags |= IFC_IN_DETACH; 5150 STATE_UNLOCK(ctx); 5151 5152 /* Unregister VLAN handlers before calling iflib_stop() */ 5153 iflib_unregister_vlan_handlers(ctx); 5154 5155 iflib_netmap_detach(ifp); 5156 ether_ifdetach(ifp); 5157 5158 CTX_LOCK(ctx); 5159 iflib_stop(ctx); 5160 CTX_UNLOCK(ctx); 5161 5162 iflib_rem_pfil(ctx); 5163 if (ctx->ifc_led_dev != NULL) 5164 led_destroy(ctx->ifc_led_dev); 5165 /* XXX drain any dependent tasks */ 5166 tqg = qgroup_if_io_tqg; 5167 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5168 callout_drain(&txq->ift_timer); 5169 #ifdef DEV_NETMAP 5170 callout_drain(&txq->ift_netmap_timer); 5171 #endif /* DEV_NETMAP */ 5172 if (txq->ift_task.gt_uniq != NULL) 5173 taskqgroup_detach(tqg, &txq->ift_task); 5174 } 5175 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5176 if (rxq->ifr_task.gt_uniq != NULL) 5177 taskqgroup_detach(tqg, &rxq->ifr_task); 5178 5179 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5180 free(fl->ifl_rx_bitmap, M_IFLIB); 5181 } 5182 tqg = qgroup_if_config_tqg; 5183 if (ctx->ifc_admin_task.gt_uniq != NULL) 5184 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5185 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5186 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5187 CTX_LOCK(ctx); 5188 IFDI_DETACH(ctx); 5189 CTX_UNLOCK(ctx); 5190 5191 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5192 iflib_free_intr_mem(ctx); 5193 5194 bus_generic_detach(dev); 5195 5196 iflib_tx_structures_free(ctx); 5197 iflib_rx_structures_free(ctx); 5198 5199 iflib_deregister(ctx); 5200 5201 device_set_softc(ctx->ifc_dev, NULL); 5202 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5203 free(ctx->ifc_softc, M_IFLIB); 5204 unref_ctx_core_offset(ctx); 5205 free(ctx, M_IFLIB); 5206 return (0); 5207 } 5208 5209 static void 5210 iflib_free_intr_mem(if_ctx_t ctx) 5211 { 5212 5213 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5214 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5215 } 5216 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5217 pci_release_msi(ctx->ifc_dev); 5218 } 5219 if (ctx->ifc_msix_mem != NULL) { 5220 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5221 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5222 ctx->ifc_msix_mem = NULL; 5223 } 5224 } 5225 5226 int 5227 iflib_device_detach(device_t dev) 5228 { 5229 if_ctx_t ctx = device_get_softc(dev); 5230 5231 return (iflib_device_deregister(ctx)); 5232 } 5233 5234 int 5235 iflib_device_suspend(device_t dev) 5236 { 5237 if_ctx_t ctx = device_get_softc(dev); 5238 5239 CTX_LOCK(ctx); 5240 IFDI_SUSPEND(ctx); 5241 CTX_UNLOCK(ctx); 5242 5243 return bus_generic_suspend(dev); 5244 } 5245 int 5246 iflib_device_shutdown(device_t dev) 5247 { 5248 if_ctx_t ctx = device_get_softc(dev); 5249 5250 CTX_LOCK(ctx); 5251 IFDI_SHUTDOWN(ctx); 5252 CTX_UNLOCK(ctx); 5253 5254 return bus_generic_suspend(dev); 5255 } 5256 5257 int 5258 iflib_device_resume(device_t dev) 5259 { 5260 if_ctx_t ctx = device_get_softc(dev); 5261 iflib_txq_t txq = ctx->ifc_txqs; 5262 5263 CTX_LOCK(ctx); 5264 IFDI_RESUME(ctx); 5265 iflib_if_init_locked(ctx); 5266 CTX_UNLOCK(ctx); 5267 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5268 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5269 5270 return (bus_generic_resume(dev)); 5271 } 5272 5273 int 5274 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5275 { 5276 int error; 5277 if_ctx_t ctx = device_get_softc(dev); 5278 5279 CTX_LOCK(ctx); 5280 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5281 CTX_UNLOCK(ctx); 5282 5283 return (error); 5284 } 5285 5286 void 5287 iflib_device_iov_uninit(device_t dev) 5288 { 5289 if_ctx_t ctx = device_get_softc(dev); 5290 5291 CTX_LOCK(ctx); 5292 IFDI_IOV_UNINIT(ctx); 5293 CTX_UNLOCK(ctx); 5294 } 5295 5296 int 5297 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5298 { 5299 int error; 5300 if_ctx_t ctx = device_get_softc(dev); 5301 5302 CTX_LOCK(ctx); 5303 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5304 CTX_UNLOCK(ctx); 5305 5306 return (error); 5307 } 5308 5309 /********************************************************************* 5310 * 5311 * MODULE FUNCTION DEFINITIONS 5312 * 5313 **********************************************************************/ 5314 5315 /* 5316 * - Start a fast taskqueue thread for each core 5317 * - Start a taskqueue for control operations 5318 */ 5319 static int 5320 iflib_module_init(void) 5321 { 5322 return (0); 5323 } 5324 5325 static int 5326 iflib_module_event_handler(module_t mod, int what, void *arg) 5327 { 5328 int err; 5329 5330 switch (what) { 5331 case MOD_LOAD: 5332 if ((err = iflib_module_init()) != 0) 5333 return (err); 5334 break; 5335 case MOD_UNLOAD: 5336 return (EBUSY); 5337 default: 5338 return (EOPNOTSUPP); 5339 } 5340 5341 return (0); 5342 } 5343 5344 /********************************************************************* 5345 * 5346 * PUBLIC FUNCTION DEFINITIONS 5347 * ordered as in iflib.h 5348 * 5349 **********************************************************************/ 5350 5351 static void 5352 _iflib_assert(if_shared_ctx_t sctx) 5353 { 5354 int i; 5355 5356 MPASS(sctx->isc_tx_maxsize); 5357 MPASS(sctx->isc_tx_maxsegsize); 5358 5359 MPASS(sctx->isc_rx_maxsize); 5360 MPASS(sctx->isc_rx_nsegments); 5361 MPASS(sctx->isc_rx_maxsegsize); 5362 5363 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5364 for (i = 0; i < sctx->isc_nrxqs; i++) { 5365 MPASS(sctx->isc_nrxd_min[i]); 5366 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5367 MPASS(sctx->isc_nrxd_max[i]); 5368 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5369 MPASS(sctx->isc_nrxd_default[i]); 5370 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5371 } 5372 5373 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5374 for (i = 0; i < sctx->isc_ntxqs; i++) { 5375 MPASS(sctx->isc_ntxd_min[i]); 5376 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5377 MPASS(sctx->isc_ntxd_max[i]); 5378 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5379 MPASS(sctx->isc_ntxd_default[i]); 5380 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5381 } 5382 } 5383 5384 static void 5385 _iflib_pre_assert(if_softc_ctx_t scctx) 5386 { 5387 5388 MPASS(scctx->isc_txrx->ift_txd_encap); 5389 MPASS(scctx->isc_txrx->ift_txd_flush); 5390 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5391 MPASS(scctx->isc_txrx->ift_rxd_available); 5392 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5393 MPASS(scctx->isc_txrx->ift_rxd_refill); 5394 MPASS(scctx->isc_txrx->ift_rxd_flush); 5395 } 5396 5397 static int 5398 iflib_register(if_ctx_t ctx) 5399 { 5400 if_shared_ctx_t sctx = ctx->ifc_sctx; 5401 driver_t *driver = sctx->isc_driver; 5402 device_t dev = ctx->ifc_dev; 5403 if_t ifp; 5404 u_char type; 5405 int iflags; 5406 5407 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0) 5408 _iflib_assert(sctx); 5409 5410 CTX_LOCK_INIT(ctx); 5411 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5412 if (sctx->isc_flags & IFLIB_PSEUDO) { 5413 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) 5414 type = IFT_ETHER; 5415 else 5416 type = IFT_PPP; 5417 } else 5418 type = IFT_ETHER; 5419 ifp = ctx->ifc_ifp = if_alloc(type); 5420 if (ifp == NULL) { 5421 device_printf(dev, "can not allocate ifnet structure\n"); 5422 return (ENOMEM); 5423 } 5424 5425 /* 5426 * Initialize our context's device specific methods 5427 */ 5428 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5429 kobj_class_compile((kobj_class_t) driver); 5430 5431 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5432 if_setsoftc(ifp, ctx); 5433 if_setdev(ifp, dev); 5434 if_setinitfn(ifp, iflib_if_init); 5435 if_setioctlfn(ifp, iflib_if_ioctl); 5436 #ifdef ALTQ 5437 if_setstartfn(ifp, iflib_altq_if_start); 5438 if_settransmitfn(ifp, iflib_altq_if_transmit); 5439 if_setsendqready(ifp); 5440 #else 5441 if_settransmitfn(ifp, iflib_if_transmit); 5442 #endif 5443 if_setqflushfn(ifp, iflib_if_qflush); 5444 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH; 5445 5446 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5447 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) 5448 iflags |= IFF_POINTOPOINT; 5449 else 5450 iflags |= IFF_BROADCAST | IFF_SIMPLEX; 5451 if_setflags(ifp, iflags); 5452 ctx->ifc_vlan_attach_event = 5453 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5454 EVENTHANDLER_PRI_FIRST); 5455 ctx->ifc_vlan_detach_event = 5456 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5457 EVENTHANDLER_PRI_FIRST); 5458 5459 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5460 ctx->ifc_mediap = &ctx->ifc_media; 5461 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5462 iflib_media_change, iflib_media_status); 5463 } 5464 return (0); 5465 } 5466 5467 static void 5468 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5469 { 5470 /* Unregister VLAN events */ 5471 if (ctx->ifc_vlan_attach_event != NULL) { 5472 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5473 ctx->ifc_vlan_attach_event = NULL; 5474 } 5475 if (ctx->ifc_vlan_detach_event != NULL) { 5476 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5477 ctx->ifc_vlan_detach_event = NULL; 5478 } 5479 5480 } 5481 5482 static void 5483 iflib_deregister(if_ctx_t ctx) 5484 { 5485 if_t ifp = ctx->ifc_ifp; 5486 5487 /* Remove all media */ 5488 ifmedia_removeall(&ctx->ifc_media); 5489 5490 /* Ensure that VLAN event handlers are unregistered */ 5491 iflib_unregister_vlan_handlers(ctx); 5492 5493 /* Release kobject reference */ 5494 kobj_delete((kobj_t) ctx, NULL); 5495 5496 /* Free the ifnet structure */ 5497 if_free(ifp); 5498 5499 STATE_LOCK_DESTROY(ctx); 5500 5501 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5502 CTX_LOCK_DESTROY(ctx); 5503 } 5504 5505 static int 5506 iflib_queues_alloc(if_ctx_t ctx) 5507 { 5508 if_shared_ctx_t sctx = ctx->ifc_sctx; 5509 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5510 device_t dev = ctx->ifc_dev; 5511 int nrxqsets = scctx->isc_nrxqsets; 5512 int ntxqsets = scctx->isc_ntxqsets; 5513 iflib_txq_t txq; 5514 iflib_rxq_t rxq; 5515 iflib_fl_t fl = NULL; 5516 int i, j, cpu, err, txconf, rxconf; 5517 iflib_dma_info_t ifdip; 5518 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5519 uint32_t *txqsizes = scctx->isc_txqsizes; 5520 uint8_t nrxqs = sctx->isc_nrxqs; 5521 uint8_t ntxqs = sctx->isc_ntxqs; 5522 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5523 caddr_t *vaddrs; 5524 uint64_t *paddrs; 5525 5526 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5527 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5528 5529 /* Allocate the TX ring struct memory */ 5530 if (!(ctx->ifc_txqs = 5531 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5532 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5533 device_printf(dev, "Unable to allocate TX ring memory\n"); 5534 err = ENOMEM; 5535 goto fail; 5536 } 5537 5538 /* Now allocate the RX */ 5539 if (!(ctx->ifc_rxqs = 5540 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5541 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5542 device_printf(dev, "Unable to allocate RX ring memory\n"); 5543 err = ENOMEM; 5544 goto rx_fail; 5545 } 5546 5547 txq = ctx->ifc_txqs; 5548 rxq = ctx->ifc_rxqs; 5549 5550 /* 5551 * XXX handle allocation failure 5552 */ 5553 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5554 /* Set up some basics */ 5555 5556 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5557 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5558 device_printf(dev, 5559 "Unable to allocate TX DMA info memory\n"); 5560 err = ENOMEM; 5561 goto err_tx_desc; 5562 } 5563 txq->ift_ifdi = ifdip; 5564 for (j = 0; j < ntxqs; j++, ifdip++) { 5565 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5566 device_printf(dev, 5567 "Unable to allocate TX descriptors\n"); 5568 err = ENOMEM; 5569 goto err_tx_desc; 5570 } 5571 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5572 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5573 } 5574 txq->ift_ctx = ctx; 5575 txq->ift_id = i; 5576 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5577 txq->ift_br_offset = 1; 5578 } else { 5579 txq->ift_br_offset = 0; 5580 } 5581 5582 if (iflib_txsd_alloc(txq)) { 5583 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5584 err = ENOMEM; 5585 goto err_tx_desc; 5586 } 5587 5588 /* Initialize the TX lock */ 5589 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5590 device_get_nameunit(dev), txq->ift_id); 5591 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5592 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5593 txq->ift_timer.c_cpu = cpu; 5594 #ifdef DEV_NETMAP 5595 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 5596 txq->ift_netmap_timer.c_cpu = cpu; 5597 #endif /* DEV_NETMAP */ 5598 5599 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5600 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5601 if (err) { 5602 /* XXX free any allocated rings */ 5603 device_printf(dev, "Unable to allocate buf_ring\n"); 5604 goto err_tx_desc; 5605 } 5606 } 5607 5608 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5609 /* Set up some basics */ 5610 callout_init(&rxq->ifr_watchdog, 1); 5611 5612 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5613 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5614 device_printf(dev, 5615 "Unable to allocate RX DMA info memory\n"); 5616 err = ENOMEM; 5617 goto err_tx_desc; 5618 } 5619 5620 rxq->ifr_ifdi = ifdip; 5621 /* XXX this needs to be changed if #rx queues != #tx queues */ 5622 rxq->ifr_ntxqirq = 1; 5623 rxq->ifr_txqid[0] = i; 5624 for (j = 0; j < nrxqs; j++, ifdip++) { 5625 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5626 device_printf(dev, 5627 "Unable to allocate RX descriptors\n"); 5628 err = ENOMEM; 5629 goto err_tx_desc; 5630 } 5631 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5632 } 5633 rxq->ifr_ctx = ctx; 5634 rxq->ifr_id = i; 5635 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5636 rxq->ifr_fl_offset = 1; 5637 } else { 5638 rxq->ifr_fl_offset = 0; 5639 } 5640 rxq->ifr_nfl = nfree_lists; 5641 if (!(fl = 5642 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5643 device_printf(dev, "Unable to allocate free list memory\n"); 5644 err = ENOMEM; 5645 goto err_tx_desc; 5646 } 5647 rxq->ifr_fl = fl; 5648 for (j = 0; j < nfree_lists; j++) { 5649 fl[j].ifl_rxq = rxq; 5650 fl[j].ifl_id = j; 5651 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5652 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5653 } 5654 /* Allocate receive buffers for the ring */ 5655 if (iflib_rxsd_alloc(rxq)) { 5656 device_printf(dev, 5657 "Critical Failure setting up receive buffers\n"); 5658 err = ENOMEM; 5659 goto err_rx_desc; 5660 } 5661 5662 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5663 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5664 M_WAITOK); 5665 } 5666 5667 /* TXQs */ 5668 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5669 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5670 for (i = 0; i < ntxqsets; i++) { 5671 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5672 5673 for (j = 0; j < ntxqs; j++, di++) { 5674 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5675 paddrs[i*ntxqs + j] = di->idi_paddr; 5676 } 5677 } 5678 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5679 device_printf(ctx->ifc_dev, 5680 "Unable to allocate device TX queue\n"); 5681 iflib_tx_structures_free(ctx); 5682 free(vaddrs, M_IFLIB); 5683 free(paddrs, M_IFLIB); 5684 goto err_rx_desc; 5685 } 5686 free(vaddrs, M_IFLIB); 5687 free(paddrs, M_IFLIB); 5688 5689 /* RXQs */ 5690 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5691 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5692 for (i = 0; i < nrxqsets; i++) { 5693 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5694 5695 for (j = 0; j < nrxqs; j++, di++) { 5696 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5697 paddrs[i*nrxqs + j] = di->idi_paddr; 5698 } 5699 } 5700 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5701 device_printf(ctx->ifc_dev, 5702 "Unable to allocate device RX queue\n"); 5703 iflib_tx_structures_free(ctx); 5704 free(vaddrs, M_IFLIB); 5705 free(paddrs, M_IFLIB); 5706 goto err_rx_desc; 5707 } 5708 free(vaddrs, M_IFLIB); 5709 free(paddrs, M_IFLIB); 5710 5711 return (0); 5712 5713 /* XXX handle allocation failure changes */ 5714 err_rx_desc: 5715 err_tx_desc: 5716 rx_fail: 5717 if (ctx->ifc_rxqs != NULL) 5718 free(ctx->ifc_rxqs, M_IFLIB); 5719 ctx->ifc_rxqs = NULL; 5720 if (ctx->ifc_txqs != NULL) 5721 free(ctx->ifc_txqs, M_IFLIB); 5722 ctx->ifc_txqs = NULL; 5723 fail: 5724 return (err); 5725 } 5726 5727 static int 5728 iflib_tx_structures_setup(if_ctx_t ctx) 5729 { 5730 iflib_txq_t txq = ctx->ifc_txqs; 5731 int i; 5732 5733 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5734 iflib_txq_setup(txq); 5735 5736 return (0); 5737 } 5738 5739 static void 5740 iflib_tx_structures_free(if_ctx_t ctx) 5741 { 5742 iflib_txq_t txq = ctx->ifc_txqs; 5743 if_shared_ctx_t sctx = ctx->ifc_sctx; 5744 int i, j; 5745 5746 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5747 for (j = 0; j < sctx->isc_ntxqs; j++) 5748 iflib_dma_free(&txq->ift_ifdi[j]); 5749 iflib_txq_destroy(txq); 5750 } 5751 free(ctx->ifc_txqs, M_IFLIB); 5752 ctx->ifc_txqs = NULL; 5753 IFDI_QUEUES_FREE(ctx); 5754 } 5755 5756 /********************************************************************* 5757 * 5758 * Initialize all receive rings. 5759 * 5760 **********************************************************************/ 5761 static int 5762 iflib_rx_structures_setup(if_ctx_t ctx) 5763 { 5764 iflib_rxq_t rxq = ctx->ifc_rxqs; 5765 int q; 5766 #if defined(INET6) || defined(INET) 5767 int err, i; 5768 #endif 5769 5770 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5771 #if defined(INET6) || defined(INET) 5772 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) { 5773 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5774 TCP_LRO_ENTRIES, min(1024, 5775 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 5776 if (err != 0) { 5777 device_printf(ctx->ifc_dev, 5778 "LRO Initialization failed!\n"); 5779 goto fail; 5780 } 5781 } 5782 #endif 5783 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5784 } 5785 return (0); 5786 #if defined(INET6) || defined(INET) 5787 fail: 5788 /* 5789 * Free LRO resources allocated so far, we will only handle 5790 * the rings that completed, the failing case will have 5791 * cleaned up for itself. 'q' failed, so its the terminus. 5792 */ 5793 rxq = ctx->ifc_rxqs; 5794 for (i = 0; i < q; ++i, rxq++) { 5795 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5796 tcp_lro_free(&rxq->ifr_lc); 5797 } 5798 return (err); 5799 #endif 5800 } 5801 5802 /********************************************************************* 5803 * 5804 * Free all receive rings. 5805 * 5806 **********************************************************************/ 5807 static void 5808 iflib_rx_structures_free(if_ctx_t ctx) 5809 { 5810 iflib_rxq_t rxq = ctx->ifc_rxqs; 5811 if_shared_ctx_t sctx = ctx->ifc_sctx; 5812 int i, j; 5813 5814 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5815 for (j = 0; j < sctx->isc_nrxqs; j++) 5816 iflib_dma_free(&rxq->ifr_ifdi[j]); 5817 iflib_rx_sds_free(rxq); 5818 #if defined(INET6) || defined(INET) 5819 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5820 tcp_lro_free(&rxq->ifr_lc); 5821 #endif 5822 } 5823 free(ctx->ifc_rxqs, M_IFLIB); 5824 ctx->ifc_rxqs = NULL; 5825 } 5826 5827 static int 5828 iflib_qset_structures_setup(if_ctx_t ctx) 5829 { 5830 int err; 5831 5832 /* 5833 * It is expected that the caller takes care of freeing queues if this 5834 * fails. 5835 */ 5836 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5837 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5838 return (err); 5839 } 5840 5841 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5842 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5843 5844 return (err); 5845 } 5846 5847 int 5848 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5849 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5850 { 5851 5852 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5853 } 5854 5855 #ifdef SMP 5856 static int 5857 find_nth(if_ctx_t ctx, int qid) 5858 { 5859 cpuset_t cpus; 5860 int i, cpuid, eqid, count; 5861 5862 CPU_COPY(&ctx->ifc_cpus, &cpus); 5863 count = CPU_COUNT(&cpus); 5864 eqid = qid % count; 5865 /* clear up to the qid'th bit */ 5866 for (i = 0; i < eqid; i++) { 5867 cpuid = CPU_FFS(&cpus); 5868 MPASS(cpuid != 0); 5869 CPU_CLR(cpuid-1, &cpus); 5870 } 5871 cpuid = CPU_FFS(&cpus); 5872 MPASS(cpuid != 0); 5873 return (cpuid-1); 5874 } 5875 5876 #ifdef SCHED_ULE 5877 extern struct cpu_group *cpu_top; /* CPU topology */ 5878 5879 static int 5880 find_child_with_core(int cpu, struct cpu_group *grp) 5881 { 5882 int i; 5883 5884 if (grp->cg_children == 0) 5885 return -1; 5886 5887 MPASS(grp->cg_child); 5888 for (i = 0; i < grp->cg_children; i++) { 5889 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5890 return i; 5891 } 5892 5893 return -1; 5894 } 5895 5896 /* 5897 * Find the nth "close" core to the specified core 5898 * "close" is defined as the deepest level that shares 5899 * at least an L2 cache. With threads, this will be 5900 * threads on the same core. If the shared cache is L3 5901 * or higher, simply returns the same core. 5902 */ 5903 static int 5904 find_close_core(int cpu, int core_offset) 5905 { 5906 struct cpu_group *grp; 5907 int i; 5908 int fcpu; 5909 cpuset_t cs; 5910 5911 grp = cpu_top; 5912 if (grp == NULL) 5913 return cpu; 5914 i = 0; 5915 while ((i = find_child_with_core(cpu, grp)) != -1) { 5916 /* If the child only has one cpu, don't descend */ 5917 if (grp->cg_child[i].cg_count <= 1) 5918 break; 5919 grp = &grp->cg_child[i]; 5920 } 5921 5922 /* If they don't share at least an L2 cache, use the same CPU */ 5923 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5924 return cpu; 5925 5926 /* Now pick one */ 5927 CPU_COPY(&grp->cg_mask, &cs); 5928 5929 /* Add the selected CPU offset to core offset. */ 5930 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5931 if (fcpu - 1 == cpu) 5932 break; 5933 CPU_CLR(fcpu - 1, &cs); 5934 } 5935 MPASS(fcpu); 5936 5937 core_offset += i; 5938 5939 CPU_COPY(&grp->cg_mask, &cs); 5940 for (i = core_offset % grp->cg_count; i > 0; i--) { 5941 MPASS(CPU_FFS(&cs)); 5942 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5943 } 5944 MPASS(CPU_FFS(&cs)); 5945 return CPU_FFS(&cs) - 1; 5946 } 5947 #else 5948 static int 5949 find_close_core(int cpu, int core_offset __unused) 5950 { 5951 return cpu; 5952 } 5953 #endif 5954 5955 static int 5956 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5957 { 5958 switch (type) { 5959 case IFLIB_INTR_TX: 5960 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5961 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5962 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5963 case IFLIB_INTR_RX: 5964 case IFLIB_INTR_RXTX: 5965 /* RX queues get the specified core */ 5966 return qid / CPU_COUNT(&ctx->ifc_cpus); 5967 default: 5968 return -1; 5969 } 5970 } 5971 #else 5972 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5973 #define find_close_core(cpuid, tid) CPU_FIRST() 5974 #define find_nth(ctx, gid) CPU_FIRST() 5975 #endif 5976 5977 /* Just to avoid copy/paste */ 5978 static inline int 5979 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5980 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5981 const char *name) 5982 { 5983 device_t dev; 5984 int co, cpuid, err, tid; 5985 5986 dev = ctx->ifc_dev; 5987 co = ctx->ifc_sysctl_core_offset; 5988 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX) 5989 co += ctx->ifc_softc_ctx.isc_nrxqsets; 5990 cpuid = find_nth(ctx, qid + co); 5991 tid = get_core_offset(ctx, type, qid); 5992 if (tid < 0) { 5993 device_printf(dev, "get_core_offset failed\n"); 5994 return (EOPNOTSUPP); 5995 } 5996 cpuid = find_close_core(cpuid, tid); 5997 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 5998 name); 5999 if (err) { 6000 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6001 return (err); 6002 } 6003 #ifdef notyet 6004 if (cpuid > ctx->ifc_cpuid_highest) 6005 ctx->ifc_cpuid_highest = cpuid; 6006 #endif 6007 return (0); 6008 } 6009 6010 int 6011 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6012 iflib_intr_type_t type, driver_filter_t *filter, 6013 void *filter_arg, int qid, const char *name) 6014 { 6015 device_t dev; 6016 struct grouptask *gtask; 6017 struct taskqgroup *tqg; 6018 iflib_filter_info_t info; 6019 gtask_fn_t *fn; 6020 int tqrid, err; 6021 driver_filter_t *intr_fast; 6022 void *q; 6023 6024 info = &ctx->ifc_filter_info; 6025 tqrid = rid; 6026 6027 switch (type) { 6028 /* XXX merge tx/rx for netmap? */ 6029 case IFLIB_INTR_TX: 6030 q = &ctx->ifc_txqs[qid]; 6031 info = &ctx->ifc_txqs[qid].ift_filter_info; 6032 gtask = &ctx->ifc_txqs[qid].ift_task; 6033 tqg = qgroup_if_io_tqg; 6034 fn = _task_fn_tx; 6035 intr_fast = iflib_fast_intr; 6036 GROUPTASK_INIT(gtask, 0, fn, q); 6037 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6038 break; 6039 case IFLIB_INTR_RX: 6040 q = &ctx->ifc_rxqs[qid]; 6041 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6042 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6043 tqg = qgroup_if_io_tqg; 6044 fn = _task_fn_rx; 6045 intr_fast = iflib_fast_intr; 6046 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6047 break; 6048 case IFLIB_INTR_RXTX: 6049 q = &ctx->ifc_rxqs[qid]; 6050 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6051 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6052 tqg = qgroup_if_io_tqg; 6053 fn = _task_fn_rx; 6054 intr_fast = iflib_fast_intr_rxtx; 6055 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6056 break; 6057 case IFLIB_INTR_ADMIN: 6058 q = ctx; 6059 tqrid = -1; 6060 info = &ctx->ifc_filter_info; 6061 gtask = &ctx->ifc_admin_task; 6062 tqg = qgroup_if_config_tqg; 6063 fn = _task_fn_admin; 6064 intr_fast = iflib_fast_intr_ctx; 6065 break; 6066 default: 6067 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6068 __func__); 6069 return (EINVAL); 6070 } 6071 6072 info->ifi_filter = filter; 6073 info->ifi_filter_arg = filter_arg; 6074 info->ifi_task = gtask; 6075 info->ifi_ctx = q; 6076 6077 dev = ctx->ifc_dev; 6078 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6079 if (err != 0) { 6080 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6081 return (err); 6082 } 6083 if (type == IFLIB_INTR_ADMIN) 6084 return (0); 6085 6086 if (tqrid != -1) { 6087 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6088 q, name); 6089 if (err) 6090 return (err); 6091 } else { 6092 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6093 } 6094 6095 return (0); 6096 } 6097 6098 void 6099 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6100 { 6101 struct grouptask *gtask; 6102 struct taskqgroup *tqg; 6103 gtask_fn_t *fn; 6104 void *q; 6105 int err; 6106 6107 switch (type) { 6108 case IFLIB_INTR_TX: 6109 q = &ctx->ifc_txqs[qid]; 6110 gtask = &ctx->ifc_txqs[qid].ift_task; 6111 tqg = qgroup_if_io_tqg; 6112 fn = _task_fn_tx; 6113 GROUPTASK_INIT(gtask, 0, fn, q); 6114 break; 6115 case IFLIB_INTR_RX: 6116 q = &ctx->ifc_rxqs[qid]; 6117 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6118 tqg = qgroup_if_io_tqg; 6119 fn = _task_fn_rx; 6120 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6121 break; 6122 case IFLIB_INTR_IOV: 6123 q = ctx; 6124 gtask = &ctx->ifc_vflr_task; 6125 tqg = qgroup_if_config_tqg; 6126 fn = _task_fn_iov; 6127 GROUPTASK_INIT(gtask, 0, fn, q); 6128 break; 6129 default: 6130 panic("unknown net intr type"); 6131 } 6132 if (irq != NULL) { 6133 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6134 q, name); 6135 if (err) 6136 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 6137 irq->ii_res, name); 6138 } else { 6139 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 6140 } 6141 } 6142 6143 void 6144 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6145 { 6146 6147 if (irq->ii_tag) 6148 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6149 6150 if (irq->ii_res) 6151 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6152 rman_get_rid(irq->ii_res), irq->ii_res); 6153 } 6154 6155 static int 6156 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6157 { 6158 iflib_txq_t txq = ctx->ifc_txqs; 6159 iflib_rxq_t rxq = ctx->ifc_rxqs; 6160 if_irq_t irq = &ctx->ifc_legacy_irq; 6161 iflib_filter_info_t info; 6162 device_t dev; 6163 struct grouptask *gtask; 6164 struct resource *res; 6165 struct taskqgroup *tqg; 6166 void *q; 6167 int err, tqrid; 6168 bool rx_only; 6169 6170 q = &ctx->ifc_rxqs[0]; 6171 info = &rxq[0].ifr_filter_info; 6172 gtask = &rxq[0].ifr_task; 6173 tqg = qgroup_if_io_tqg; 6174 tqrid = *rid; 6175 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6176 6177 ctx->ifc_flags |= IFC_LEGACY; 6178 info->ifi_filter = filter; 6179 info->ifi_filter_arg = filter_arg; 6180 info->ifi_task = gtask; 6181 info->ifi_ctx = rx_only ? ctx : q; 6182 6183 dev = ctx->ifc_dev; 6184 /* We allocate a single interrupt resource */ 6185 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6186 iflib_fast_intr_rxtx, NULL, info, name); 6187 if (err != 0) 6188 return (err); 6189 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6190 res = irq->ii_res; 6191 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6192 6193 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6194 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6195 "tx"); 6196 return (0); 6197 } 6198 6199 void 6200 iflib_led_create(if_ctx_t ctx) 6201 { 6202 6203 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6204 device_get_nameunit(ctx->ifc_dev)); 6205 } 6206 6207 void 6208 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6209 { 6210 6211 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6212 } 6213 6214 void 6215 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6216 { 6217 6218 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6219 } 6220 6221 void 6222 iflib_admin_intr_deferred(if_ctx_t ctx) 6223 { 6224 6225 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6226 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6227 } 6228 6229 void 6230 iflib_iov_intr_deferred(if_ctx_t ctx) 6231 { 6232 6233 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6234 } 6235 6236 void 6237 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6238 { 6239 6240 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6241 name); 6242 } 6243 6244 void 6245 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6246 const char *name) 6247 { 6248 6249 GROUPTASK_INIT(gtask, 0, fn, ctx); 6250 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6251 name); 6252 } 6253 6254 void 6255 iflib_config_gtask_deinit(struct grouptask *gtask) 6256 { 6257 6258 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6259 } 6260 6261 void 6262 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6263 { 6264 if_t ifp = ctx->ifc_ifp; 6265 iflib_txq_t txq = ctx->ifc_txqs; 6266 6267 if_setbaudrate(ifp, baudrate); 6268 if (baudrate >= IF_Gbps(10)) { 6269 STATE_LOCK(ctx); 6270 ctx->ifc_flags |= IFC_PREFETCH; 6271 STATE_UNLOCK(ctx); 6272 } 6273 /* If link down, disable watchdog */ 6274 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6275 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6276 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6277 } 6278 ctx->ifc_link_state = link_state; 6279 if_link_state_change(ifp, link_state); 6280 } 6281 6282 static int 6283 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6284 { 6285 int credits; 6286 #ifdef INVARIANTS 6287 int credits_pre = txq->ift_cidx_processed; 6288 #endif 6289 6290 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6291 BUS_DMASYNC_POSTREAD); 6292 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6293 return (0); 6294 6295 txq->ift_processed += credits; 6296 txq->ift_cidx_processed += credits; 6297 6298 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6299 if (txq->ift_cidx_processed >= txq->ift_size) 6300 txq->ift_cidx_processed -= txq->ift_size; 6301 return (credits); 6302 } 6303 6304 static int 6305 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6306 { 6307 iflib_fl_t fl; 6308 u_int i; 6309 6310 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6311 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6312 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6313 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6314 budget)); 6315 } 6316 6317 void 6318 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6319 const char *description, if_int_delay_info_t info, 6320 int offset, int value) 6321 { 6322 info->iidi_ctx = ctx; 6323 info->iidi_offset = offset; 6324 info->iidi_value = value; 6325 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6326 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6327 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6328 info, 0, iflib_sysctl_int_delay, "I", description); 6329 } 6330 6331 struct sx * 6332 iflib_ctx_lock_get(if_ctx_t ctx) 6333 { 6334 6335 return (&ctx->ifc_ctx_sx); 6336 } 6337 6338 static int 6339 iflib_msix_init(if_ctx_t ctx) 6340 { 6341 device_t dev = ctx->ifc_dev; 6342 if_shared_ctx_t sctx = ctx->ifc_sctx; 6343 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6344 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6345 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6346 6347 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6348 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6349 6350 if (bootverbose) 6351 device_printf(dev, "msix_init qsets capped at %d\n", 6352 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6353 6354 /* Override by tuneable */ 6355 if (scctx->isc_disable_msix) 6356 goto msi; 6357 6358 /* First try MSI-X */ 6359 if ((msgs = pci_msix_count(dev)) == 0) { 6360 if (bootverbose) 6361 device_printf(dev, "MSI-X not supported or disabled\n"); 6362 goto msi; 6363 } 6364 6365 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6366 /* 6367 * bar == -1 => "trust me I know what I'm doing" 6368 * Some drivers are for hardware that is so shoddily 6369 * documented that no one knows which bars are which 6370 * so the developer has to map all bars. This hack 6371 * allows shoddy garbage to use MSI-X in this framework. 6372 */ 6373 if (bar != -1) { 6374 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6375 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6376 if (ctx->ifc_msix_mem == NULL) { 6377 device_printf(dev, "Unable to map MSI-X table\n"); 6378 goto msi; 6379 } 6380 } 6381 6382 admincnt = sctx->isc_admin_intrcnt; 6383 #if IFLIB_DEBUG 6384 /* use only 1 qset in debug mode */ 6385 queuemsgs = min(msgs - admincnt, 1); 6386 #else 6387 queuemsgs = msgs - admincnt; 6388 #endif 6389 #ifdef RSS 6390 queues = imin(queuemsgs, rss_getnumbuckets()); 6391 #else 6392 queues = queuemsgs; 6393 #endif 6394 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6395 if (bootverbose) 6396 device_printf(dev, 6397 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6398 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6399 #ifdef RSS 6400 /* If we're doing RSS, clamp at the number of RSS buckets */ 6401 if (queues > rss_getnumbuckets()) 6402 queues = rss_getnumbuckets(); 6403 #endif 6404 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6405 rx_queues = iflib_num_rx_queues; 6406 else 6407 rx_queues = queues; 6408 6409 if (rx_queues > scctx->isc_nrxqsets) 6410 rx_queues = scctx->isc_nrxqsets; 6411 6412 /* 6413 * We want this to be all logical CPUs by default 6414 */ 6415 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6416 tx_queues = iflib_num_tx_queues; 6417 else 6418 tx_queues = mp_ncpus; 6419 6420 if (tx_queues > scctx->isc_ntxqsets) 6421 tx_queues = scctx->isc_ntxqsets; 6422 6423 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6424 #ifdef INVARIANTS 6425 if (tx_queues != rx_queues) 6426 device_printf(dev, 6427 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6428 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6429 #endif 6430 tx_queues = min(rx_queues, tx_queues); 6431 rx_queues = min(rx_queues, tx_queues); 6432 } 6433 6434 vectors = rx_queues + admincnt; 6435 if (msgs < vectors) { 6436 device_printf(dev, 6437 "insufficient number of MSI-X vectors " 6438 "(supported %d, need %d)\n", msgs, vectors); 6439 goto msi; 6440 } 6441 6442 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6443 tx_queues); 6444 msgs = vectors; 6445 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6446 if (vectors != msgs) { 6447 device_printf(dev, 6448 "Unable to allocate sufficient MSI-X vectors " 6449 "(got %d, need %d)\n", vectors, msgs); 6450 pci_release_msi(dev); 6451 if (bar != -1) { 6452 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6453 ctx->ifc_msix_mem); 6454 ctx->ifc_msix_mem = NULL; 6455 } 6456 goto msi; 6457 } 6458 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6459 vectors); 6460 scctx->isc_vectors = vectors; 6461 scctx->isc_nrxqsets = rx_queues; 6462 scctx->isc_ntxqsets = tx_queues; 6463 scctx->isc_intr = IFLIB_INTR_MSIX; 6464 6465 return (vectors); 6466 } else { 6467 device_printf(dev, 6468 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6469 err); 6470 if (bar != -1) { 6471 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6472 ctx->ifc_msix_mem); 6473 ctx->ifc_msix_mem = NULL; 6474 } 6475 } 6476 6477 msi: 6478 vectors = pci_msi_count(dev); 6479 scctx->isc_nrxqsets = 1; 6480 scctx->isc_ntxqsets = 1; 6481 scctx->isc_vectors = vectors; 6482 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6483 device_printf(dev,"Using an MSI interrupt\n"); 6484 scctx->isc_intr = IFLIB_INTR_MSI; 6485 } else { 6486 scctx->isc_vectors = 1; 6487 device_printf(dev,"Using a Legacy interrupt\n"); 6488 scctx->isc_intr = IFLIB_INTR_LEGACY; 6489 } 6490 6491 return (vectors); 6492 } 6493 6494 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6495 6496 static int 6497 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6498 { 6499 int rc; 6500 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6501 struct sbuf *sb; 6502 const char *ring_state = "UNKNOWN"; 6503 6504 /* XXX needed ? */ 6505 rc = sysctl_wire_old_buffer(req, 0); 6506 MPASS(rc == 0); 6507 if (rc != 0) 6508 return (rc); 6509 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6510 MPASS(sb != NULL); 6511 if (sb == NULL) 6512 return (ENOMEM); 6513 if (state[3] <= 3) 6514 ring_state = ring_states[state[3]]; 6515 6516 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6517 state[0], state[1], state[2], ring_state); 6518 rc = sbuf_finish(sb); 6519 sbuf_delete(sb); 6520 return(rc); 6521 } 6522 6523 enum iflib_ndesc_handler { 6524 IFLIB_NTXD_HANDLER, 6525 IFLIB_NRXD_HANDLER, 6526 }; 6527 6528 static int 6529 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6530 { 6531 if_ctx_t ctx = (void *)arg1; 6532 enum iflib_ndesc_handler type = arg2; 6533 char buf[256] = {0}; 6534 qidx_t *ndesc; 6535 char *p, *next; 6536 int nqs, rc, i; 6537 6538 nqs = 8; 6539 switch(type) { 6540 case IFLIB_NTXD_HANDLER: 6541 ndesc = ctx->ifc_sysctl_ntxds; 6542 if (ctx->ifc_sctx) 6543 nqs = ctx->ifc_sctx->isc_ntxqs; 6544 break; 6545 case IFLIB_NRXD_HANDLER: 6546 ndesc = ctx->ifc_sysctl_nrxds; 6547 if (ctx->ifc_sctx) 6548 nqs = ctx->ifc_sctx->isc_nrxqs; 6549 break; 6550 default: 6551 printf("%s: unhandled type\n", __func__); 6552 return (EINVAL); 6553 } 6554 if (nqs == 0) 6555 nqs = 8; 6556 6557 for (i=0; i<8; i++) { 6558 if (i >= nqs) 6559 break; 6560 if (i) 6561 strcat(buf, ","); 6562 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6563 } 6564 6565 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6566 if (rc || req->newptr == NULL) 6567 return rc; 6568 6569 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6570 i++, p = strsep(&next, " ,")) { 6571 ndesc[i] = strtoul(p, NULL, 10); 6572 } 6573 6574 return(rc); 6575 } 6576 6577 #define NAME_BUFLEN 32 6578 static void 6579 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6580 { 6581 device_t dev = iflib_get_dev(ctx); 6582 struct sysctl_oid_list *child, *oid_list; 6583 struct sysctl_ctx_list *ctx_list; 6584 struct sysctl_oid *node; 6585 6586 ctx_list = device_get_sysctl_ctx(dev); 6587 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6588 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6589 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 6590 oid_list = SYSCTL_CHILDREN(node); 6591 6592 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6593 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6594 "driver version"); 6595 6596 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6597 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6598 "# of txqs to use, 0 => use default #"); 6599 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6600 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6601 "# of rxqs to use, 0 => use default #"); 6602 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6603 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6604 "permit #txq != #rxq"); 6605 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6606 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6607 "disable MSI-X (default 0)"); 6608 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6609 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6610 "set the RX budget"); 6611 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6612 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6613 "cause TX to abdicate instead of running to completion"); 6614 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6615 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6616 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6617 "offset to start using cores at"); 6618 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6619 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6620 "use separate cores for TX and RX"); 6621 6622 /* XXX change for per-queue sizes */ 6623 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6624 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6625 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6626 "list of # of TX descriptors to use, 0 = use default #"); 6627 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6628 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6629 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6630 "list of # of RX descriptors to use, 0 = use default #"); 6631 } 6632 6633 static void 6634 iflib_add_device_sysctl_post(if_ctx_t ctx) 6635 { 6636 if_shared_ctx_t sctx = ctx->ifc_sctx; 6637 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6638 device_t dev = iflib_get_dev(ctx); 6639 struct sysctl_oid_list *child; 6640 struct sysctl_ctx_list *ctx_list; 6641 iflib_fl_t fl; 6642 iflib_txq_t txq; 6643 iflib_rxq_t rxq; 6644 int i, j; 6645 char namebuf[NAME_BUFLEN]; 6646 char *qfmt; 6647 struct sysctl_oid *queue_node, *fl_node, *node; 6648 struct sysctl_oid_list *queue_list, *fl_list; 6649 ctx_list = device_get_sysctl_ctx(dev); 6650 6651 node = ctx->ifc_sysctl_node; 6652 child = SYSCTL_CHILDREN(node); 6653 6654 if (scctx->isc_ntxqsets > 100) 6655 qfmt = "txq%03d"; 6656 else if (scctx->isc_ntxqsets > 10) 6657 qfmt = "txq%02d"; 6658 else 6659 qfmt = "txq%d"; 6660 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6661 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6662 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6663 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6664 queue_list = SYSCTL_CHILDREN(queue_node); 6665 #if MEMORY_LOGGING 6666 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6667 CTLFLAG_RD, 6668 &txq->ift_dequeued, "total mbufs freed"); 6669 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6670 CTLFLAG_RD, 6671 &txq->ift_enqueued, "total mbufs enqueued"); 6672 #endif 6673 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6674 CTLFLAG_RD, 6675 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6676 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6677 CTLFLAG_RD, 6678 &txq->ift_pullups, "# of times m_pullup was called"); 6679 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6680 CTLFLAG_RD, 6681 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6682 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6683 CTLFLAG_RD, 6684 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6685 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6686 CTLFLAG_RD, 6687 &txq->ift_map_failed, "# of times DMA map failed"); 6688 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6689 CTLFLAG_RD, 6690 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6691 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6692 CTLFLAG_RD, 6693 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6694 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6695 CTLFLAG_RD, 6696 &txq->ift_pidx, 1, "Producer Index"); 6697 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6698 CTLFLAG_RD, 6699 &txq->ift_cidx, 1, "Consumer Index"); 6700 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6701 CTLFLAG_RD, 6702 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6703 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6704 CTLFLAG_RD, 6705 &txq->ift_in_use, 1, "descriptors in use"); 6706 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6707 CTLFLAG_RD, 6708 &txq->ift_processed, "descriptors procesed for clean"); 6709 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6710 CTLFLAG_RD, 6711 &txq->ift_cleaned, "total cleaned"); 6712 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6713 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6714 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6715 mp_ring_state_handler, "A", "soft ring state"); 6716 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6717 CTLFLAG_RD, &txq->ift_br->enqueues, 6718 "# of enqueues to the mp_ring for this queue"); 6719 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6720 CTLFLAG_RD, &txq->ift_br->drops, 6721 "# of drops in the mp_ring for this queue"); 6722 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6723 CTLFLAG_RD, &txq->ift_br->starts, 6724 "# of normal consumer starts in the mp_ring for this queue"); 6725 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6726 CTLFLAG_RD, &txq->ift_br->stalls, 6727 "# of consumer stalls in the mp_ring for this queue"); 6728 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6729 CTLFLAG_RD, &txq->ift_br->restarts, 6730 "# of consumer restarts in the mp_ring for this queue"); 6731 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6732 CTLFLAG_RD, &txq->ift_br->abdications, 6733 "# of consumer abdications in the mp_ring for this queue"); 6734 } 6735 6736 if (scctx->isc_nrxqsets > 100) 6737 qfmt = "rxq%03d"; 6738 else if (scctx->isc_nrxqsets > 10) 6739 qfmt = "rxq%02d"; 6740 else 6741 qfmt = "rxq%d"; 6742 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6743 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6744 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6745 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6746 queue_list = SYSCTL_CHILDREN(queue_node); 6747 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6748 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6749 CTLFLAG_RD, 6750 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6751 } 6752 6753 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6754 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6755 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6756 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 6757 fl_list = SYSCTL_CHILDREN(fl_node); 6758 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6759 CTLFLAG_RD, 6760 &fl->ifl_pidx, 1, "Producer Index"); 6761 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6762 CTLFLAG_RD, 6763 &fl->ifl_cidx, 1, "Consumer Index"); 6764 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6765 CTLFLAG_RD, 6766 &fl->ifl_credits, 1, "credits available"); 6767 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 6768 CTLFLAG_RD, 6769 &fl->ifl_buf_size, 1, "buffer size"); 6770 #if MEMORY_LOGGING 6771 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6772 CTLFLAG_RD, 6773 &fl->ifl_m_enqueued, "mbufs allocated"); 6774 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6775 CTLFLAG_RD, 6776 &fl->ifl_m_dequeued, "mbufs freed"); 6777 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6778 CTLFLAG_RD, 6779 &fl->ifl_cl_enqueued, "clusters allocated"); 6780 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6781 CTLFLAG_RD, 6782 &fl->ifl_cl_dequeued, "clusters freed"); 6783 #endif 6784 } 6785 } 6786 6787 } 6788 6789 void 6790 iflib_request_reset(if_ctx_t ctx) 6791 { 6792 6793 STATE_LOCK(ctx); 6794 ctx->ifc_flags |= IFC_DO_RESET; 6795 STATE_UNLOCK(ctx); 6796 } 6797 6798 #ifndef __NO_STRICT_ALIGNMENT 6799 static struct mbuf * 6800 iflib_fixup_rx(struct mbuf *m) 6801 { 6802 struct mbuf *n; 6803 6804 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6805 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6806 m->m_data += ETHER_HDR_LEN; 6807 n = m; 6808 } else { 6809 MGETHDR(n, M_NOWAIT, MT_DATA); 6810 if (n == NULL) { 6811 m_freem(m); 6812 return (NULL); 6813 } 6814 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6815 m->m_data += ETHER_HDR_LEN; 6816 m->m_len -= ETHER_HDR_LEN; 6817 n->m_len = ETHER_HDR_LEN; 6818 M_MOVE_PKTHDR(n, m); 6819 n->m_next = m; 6820 } 6821 return (n); 6822 } 6823 #endif 6824 6825 #ifdef DEBUGNET 6826 static void 6827 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6828 { 6829 if_ctx_t ctx; 6830 6831 ctx = if_getsoftc(ifp); 6832 CTX_LOCK(ctx); 6833 *nrxr = NRXQSETS(ctx); 6834 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6835 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6836 CTX_UNLOCK(ctx); 6837 } 6838 6839 static void 6840 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 6841 { 6842 if_ctx_t ctx; 6843 if_softc_ctx_t scctx; 6844 iflib_fl_t fl; 6845 iflib_rxq_t rxq; 6846 int i, j; 6847 6848 ctx = if_getsoftc(ifp); 6849 scctx = &ctx->ifc_softc_ctx; 6850 6851 switch (event) { 6852 case DEBUGNET_START: 6853 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6854 rxq = &ctx->ifc_rxqs[i]; 6855 for (j = 0; j < rxq->ifr_nfl; j++) { 6856 fl = rxq->ifr_fl; 6857 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6858 } 6859 } 6860 iflib_no_tx_batch = 1; 6861 break; 6862 default: 6863 break; 6864 } 6865 } 6866 6867 static int 6868 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 6869 { 6870 if_ctx_t ctx; 6871 iflib_txq_t txq; 6872 int error; 6873 6874 ctx = if_getsoftc(ifp); 6875 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6876 IFF_DRV_RUNNING) 6877 return (EBUSY); 6878 6879 txq = &ctx->ifc_txqs[0]; 6880 error = iflib_encap(txq, &m); 6881 if (error == 0) 6882 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6883 return (error); 6884 } 6885 6886 static int 6887 iflib_debugnet_poll(if_t ifp, int count) 6888 { 6889 struct epoch_tracker et; 6890 if_ctx_t ctx; 6891 if_softc_ctx_t scctx; 6892 iflib_txq_t txq; 6893 int i; 6894 6895 ctx = if_getsoftc(ifp); 6896 scctx = &ctx->ifc_softc_ctx; 6897 6898 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6899 IFF_DRV_RUNNING) 6900 return (EBUSY); 6901 6902 txq = &ctx->ifc_txqs[0]; 6903 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6904 6905 NET_EPOCH_ENTER(et); 6906 for (i = 0; i < scctx->isc_nrxqsets; i++) 6907 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6908 NET_EPOCH_EXIT(et); 6909 return (0); 6910 } 6911 #endif /* DEBUGNET */ 6912