1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/sockio.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/mutex.h> 44 #include <sys/module.h> 45 #include <sys/kobj.h> 46 #include <sys/rman.h> 47 #include <sys/sbuf.h> 48 #include <sys/smp.h> 49 #include <sys/socket.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 56 #include <net/if.h> 57 #include <net/if_var.h> 58 #include <net/if_types.h> 59 #include <net/if_media.h> 60 #include <net/bpf.h> 61 #include <net/ethernet.h> 62 #include <net/mp_ring.h> 63 #include <net/vnet.h> 64 65 #include <netinet/in.h> 66 #include <netinet/in_pcb.h> 67 #include <netinet/tcp_lro.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/if_ether.h> 70 #include <netinet/ip.h> 71 #include <netinet/ip6.h> 72 #include <netinet/tcp.h> 73 #include <netinet/ip_var.h> 74 #include <netinet6/ip6_var.h> 75 76 #include <machine/bus.h> 77 #include <machine/in_cksum.h> 78 79 #include <vm/vm.h> 80 #include <vm/pmap.h> 81 82 #include <dev/led/led.h> 83 #include <dev/pci/pcireg.h> 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pci_private.h> 86 87 #include <net/iflib.h> 88 89 #include "ifdi_if.h" 90 91 #if defined(__i386__) || defined(__amd64__) 92 #include <sys/memdesc.h> 93 #include <machine/bus.h> 94 #include <machine/md_var.h> 95 #include <machine/specialreg.h> 96 #include <x86/include/busdma_impl.h> 97 #include <x86/iommu/busdma_dmar.h> 98 #endif 99 100 #include <sys/bitstring.h> 101 /* 102 * enable accounting of every mbuf as it comes in to and goes out of 103 * iflib's software descriptor references 104 */ 105 #define MEMORY_LOGGING 0 106 /* 107 * Enable mbuf vectors for compressing long mbuf chains 108 */ 109 110 /* 111 * NB: 112 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 113 * we prefetch needs to be determined by the time spent in m_free vis a vis 114 * the cost of a prefetch. This will of course vary based on the workload: 115 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 116 * is quite expensive, thus suggesting very little prefetch. 117 * - small packet forwarding which is just returning a single mbuf to 118 * UMA will typically be very fast vis a vis the cost of a memory 119 * access. 120 */ 121 122 123 /* 124 * File organization: 125 * - private structures 126 * - iflib private utility functions 127 * - ifnet functions 128 * - vlan registry and other exported functions 129 * - iflib public core functions 130 * 131 * 132 */ 133 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 134 135 struct iflib_txq; 136 typedef struct iflib_txq *iflib_txq_t; 137 struct iflib_rxq; 138 typedef struct iflib_rxq *iflib_rxq_t; 139 struct iflib_fl; 140 typedef struct iflib_fl *iflib_fl_t; 141 142 struct iflib_ctx; 143 144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 145 146 typedef struct iflib_filter_info { 147 driver_filter_t *ifi_filter; 148 void *ifi_filter_arg; 149 struct grouptask *ifi_task; 150 void *ifi_ctx; 151 } *iflib_filter_info_t; 152 153 struct iflib_ctx { 154 KOBJ_FIELDS; 155 /* 156 * Pointer to hardware driver's softc 157 */ 158 void *ifc_softc; 159 device_t ifc_dev; 160 if_t ifc_ifp; 161 162 cpuset_t ifc_cpus; 163 if_shared_ctx_t ifc_sctx; 164 struct if_softc_ctx ifc_softc_ctx; 165 166 struct mtx ifc_ctx_mtx; 167 struct mtx ifc_state_mtx; 168 169 uint16_t ifc_nhwtxqs; 170 171 iflib_txq_t ifc_txqs; 172 iflib_rxq_t ifc_rxqs; 173 uint32_t ifc_if_flags; 174 uint32_t ifc_flags; 175 uint32_t ifc_max_fl_buf_size; 176 int ifc_in_detach; 177 178 int ifc_link_state; 179 int ifc_link_irq; 180 int ifc_watchdog_events; 181 struct cdev *ifc_led_dev; 182 struct resource *ifc_msix_mem; 183 184 struct if_irq ifc_legacy_irq; 185 struct grouptask ifc_admin_task; 186 struct grouptask ifc_vflr_task; 187 struct iflib_filter_info ifc_filter_info; 188 struct ifmedia ifc_media; 189 190 struct sysctl_oid *ifc_sysctl_node; 191 uint16_t ifc_sysctl_ntxqs; 192 uint16_t ifc_sysctl_nrxqs; 193 uint16_t ifc_sysctl_qs_eq_override; 194 uint16_t ifc_sysctl_rx_budget; 195 196 qidx_t ifc_sysctl_ntxds[8]; 197 qidx_t ifc_sysctl_nrxds[8]; 198 struct if_txrx ifc_txrx; 199 #define isc_txd_encap ifc_txrx.ift_txd_encap 200 #define isc_txd_flush ifc_txrx.ift_txd_flush 201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 202 #define isc_rxd_available ifc_txrx.ift_rxd_available 203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 209 eventhandler_tag ifc_vlan_attach_event; 210 eventhandler_tag ifc_vlan_detach_event; 211 uint8_t ifc_mac[ETHER_ADDR_LEN]; 212 char ifc_mtx_name[16]; 213 }; 214 215 216 void * 217 iflib_get_softc(if_ctx_t ctx) 218 { 219 220 return (ctx->ifc_softc); 221 } 222 223 device_t 224 iflib_get_dev(if_ctx_t ctx) 225 { 226 227 return (ctx->ifc_dev); 228 } 229 230 if_t 231 iflib_get_ifp(if_ctx_t ctx) 232 { 233 234 return (ctx->ifc_ifp); 235 } 236 237 struct ifmedia * 238 iflib_get_media(if_ctx_t ctx) 239 { 240 241 return (&ctx->ifc_media); 242 } 243 244 void 245 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 246 { 247 248 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 249 } 250 251 if_softc_ctx_t 252 iflib_get_softc_ctx(if_ctx_t ctx) 253 { 254 255 return (&ctx->ifc_softc_ctx); 256 } 257 258 if_shared_ctx_t 259 iflib_get_sctx(if_ctx_t ctx) 260 { 261 262 return (ctx->ifc_sctx); 263 } 264 265 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 266 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 267 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 268 269 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 270 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 271 272 #define RX_SW_DESC_MAP_CREATED (1 << 0) 273 #define TX_SW_DESC_MAP_CREATED (1 << 1) 274 #define RX_SW_DESC_INUSE (1 << 3) 275 #define TX_SW_DESC_MAPPED (1 << 4) 276 277 #define M_TOOBIG M_PROTO1 278 279 typedef struct iflib_sw_rx_desc_array { 280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 281 struct mbuf **ifsd_m; /* pkthdr mbufs */ 282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 283 uint8_t *ifsd_flags; 284 } iflib_rxsd_array_t; 285 286 typedef struct iflib_sw_tx_desc_array { 287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 288 struct mbuf **ifsd_m; /* pkthdr mbufs */ 289 uint8_t *ifsd_flags; 290 } if_txsd_vec_t; 291 292 293 /* magic number that should be high enough for any hardware */ 294 #define IFLIB_MAX_TX_SEGS 128 295 /* bnxt supports 64 with hardware LRO enabled */ 296 #define IFLIB_MAX_RX_SEGS 64 297 #define IFLIB_RX_COPY_THRESH 128 298 #define IFLIB_MAX_RX_REFRESH 32 299 /* The minimum descriptors per second before we start coalescing */ 300 #define IFLIB_MIN_DESC_SEC 16384 301 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 302 #define IFLIB_QUEUE_IDLE 0 303 #define IFLIB_QUEUE_HUNG 1 304 #define IFLIB_QUEUE_WORKING 2 305 /* maximum number of txqs that can share an rx interrupt */ 306 #define IFLIB_MAX_TX_SHARED_INTR 4 307 308 /* this should really scale with ring size - this is a fairly arbitrary value */ 309 #define TX_BATCH_SIZE 32 310 311 #define IFLIB_RESTART_BUDGET 8 312 313 #define IFC_LEGACY 0x001 314 #define IFC_QFLUSH 0x002 315 #define IFC_MULTISEG 0x004 316 #define IFC_DMAR 0x008 317 #define IFC_SC_ALLOCATED 0x010 318 #define IFC_INIT_DONE 0x020 319 #define IFC_PREFETCH 0x040 320 #define IFC_DO_RESET 0x080 321 #define IFC_DO_WATCHDOG 0x100 322 #define IFC_CHECK_HUNG 0x200 323 324 325 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 326 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 327 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 328 struct iflib_txq { 329 qidx_t ift_in_use; 330 qidx_t ift_cidx; 331 qidx_t ift_cidx_processed; 332 qidx_t ift_pidx; 333 uint8_t ift_gen; 334 uint8_t ift_br_offset; 335 uint16_t ift_npending; 336 uint16_t ift_db_pending; 337 uint16_t ift_rs_pending; 338 /* implicit pad */ 339 uint8_t ift_txd_size[8]; 340 uint64_t ift_processed; 341 uint64_t ift_cleaned; 342 uint64_t ift_cleaned_prev; 343 #if MEMORY_LOGGING 344 uint64_t ift_enqueued; 345 uint64_t ift_dequeued; 346 #endif 347 uint64_t ift_no_tx_dma_setup; 348 uint64_t ift_no_desc_avail; 349 uint64_t ift_mbuf_defrag_failed; 350 uint64_t ift_mbuf_defrag; 351 uint64_t ift_map_failed; 352 uint64_t ift_txd_encap_efbig; 353 uint64_t ift_pullups; 354 355 struct mtx ift_mtx; 356 struct mtx ift_db_mtx; 357 358 /* constant values */ 359 if_ctx_t ift_ctx; 360 struct ifmp_ring *ift_br; 361 struct grouptask ift_task; 362 qidx_t ift_size; 363 uint16_t ift_id; 364 struct callout ift_timer; 365 366 if_txsd_vec_t ift_sds; 367 uint8_t ift_qstatus; 368 uint8_t ift_closed; 369 uint8_t ift_update_freq; 370 struct iflib_filter_info ift_filter_info; 371 bus_dma_tag_t ift_desc_tag; 372 bus_dma_tag_t ift_tso_desc_tag; 373 iflib_dma_info_t ift_ifdi; 374 #define MTX_NAME_LEN 16 375 char ift_mtx_name[MTX_NAME_LEN]; 376 char ift_db_mtx_name[MTX_NAME_LEN]; 377 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 378 #ifdef IFLIB_DIAGNOSTICS 379 uint64_t ift_cpu_exec_count[256]; 380 #endif 381 } __aligned(CACHE_LINE_SIZE); 382 383 struct iflib_fl { 384 qidx_t ifl_cidx; 385 qidx_t ifl_pidx; 386 qidx_t ifl_credits; 387 uint8_t ifl_gen; 388 uint8_t ifl_rxd_size; 389 #if MEMORY_LOGGING 390 uint64_t ifl_m_enqueued; 391 uint64_t ifl_m_dequeued; 392 uint64_t ifl_cl_enqueued; 393 uint64_t ifl_cl_dequeued; 394 #endif 395 /* implicit pad */ 396 397 bitstr_t *ifl_rx_bitmap; 398 qidx_t ifl_fragidx; 399 /* constant */ 400 qidx_t ifl_size; 401 uint16_t ifl_buf_size; 402 uint16_t ifl_cltype; 403 uma_zone_t ifl_zone; 404 iflib_rxsd_array_t ifl_sds; 405 iflib_rxq_t ifl_rxq; 406 uint8_t ifl_id; 407 bus_dma_tag_t ifl_desc_tag; 408 iflib_dma_info_t ifl_ifdi; 409 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 410 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 411 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 412 } __aligned(CACHE_LINE_SIZE); 413 414 static inline qidx_t 415 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 416 { 417 qidx_t used; 418 419 if (pidx > cidx) 420 used = pidx - cidx; 421 else if (pidx < cidx) 422 used = size - cidx + pidx; 423 else if (gen == 0 && pidx == cidx) 424 used = 0; 425 else if (gen == 1 && pidx == cidx) 426 used = size; 427 else 428 panic("bad state"); 429 430 return (used); 431 } 432 433 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 434 435 #define IDXDIFF(head, tail, wrap) \ 436 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 437 438 struct iflib_rxq { 439 /* If there is a separate completion queue - 440 * these are the cq cidx and pidx. Otherwise 441 * these are unused. 442 */ 443 qidx_t ifr_size; 444 qidx_t ifr_cq_cidx; 445 qidx_t ifr_cq_pidx; 446 uint8_t ifr_cq_gen; 447 uint8_t ifr_fl_offset; 448 449 if_ctx_t ifr_ctx; 450 iflib_fl_t ifr_fl; 451 uint64_t ifr_rx_irq; 452 uint16_t ifr_id; 453 uint8_t ifr_lro_enabled; 454 uint8_t ifr_nfl; 455 uint8_t ifr_ntxqirq; 456 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 457 struct lro_ctrl ifr_lc; 458 struct grouptask ifr_task; 459 struct iflib_filter_info ifr_filter_info; 460 iflib_dma_info_t ifr_ifdi; 461 462 /* dynamically allocate if any drivers need a value substantially larger than this */ 463 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 464 #ifdef IFLIB_DIAGNOSTICS 465 uint64_t ifr_cpu_exec_count[256]; 466 #endif 467 } __aligned(CACHE_LINE_SIZE); 468 469 typedef struct if_rxsd { 470 caddr_t *ifsd_cl; 471 struct mbuf **ifsd_m; 472 iflib_fl_t ifsd_fl; 473 qidx_t ifsd_cidx; 474 } *if_rxsd_t; 475 476 /* multiple of word size */ 477 #ifdef __LP64__ 478 #define PKT_INFO_SIZE 6 479 #define RXD_INFO_SIZE 5 480 #define PKT_TYPE uint64_t 481 #else 482 #define PKT_INFO_SIZE 11 483 #define RXD_INFO_SIZE 8 484 #define PKT_TYPE uint32_t 485 #endif 486 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 487 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 488 489 typedef struct if_pkt_info_pad { 490 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 491 } *if_pkt_info_pad_t; 492 typedef struct if_rxd_info_pad { 493 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 494 } *if_rxd_info_pad_t; 495 496 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 497 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 498 499 500 static inline void 501 pkt_info_zero(if_pkt_info_t pi) 502 { 503 if_pkt_info_pad_t pi_pad; 504 505 pi_pad = (if_pkt_info_pad_t)pi; 506 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 507 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 508 #ifndef __LP64__ 509 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 510 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 511 #endif 512 } 513 514 static inline void 515 rxd_info_zero(if_rxd_info_t ri) 516 { 517 if_rxd_info_pad_t ri_pad; 518 int i; 519 520 ri_pad = (if_rxd_info_pad_t)ri; 521 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 522 ri_pad->rxd_val[i] = 0; 523 ri_pad->rxd_val[i+1] = 0; 524 ri_pad->rxd_val[i+2] = 0; 525 ri_pad->rxd_val[i+3] = 0; 526 } 527 #ifdef __LP64__ 528 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 529 #endif 530 } 531 532 /* 533 * Only allow a single packet to take up most 1/nth of the tx ring 534 */ 535 #define MAX_SINGLE_PACKET_FRACTION 12 536 #define IF_BAD_DMA (bus_addr_t)-1 537 538 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 539 540 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_ctx_mtx, _name, "iflib ctx lock", MTX_DEF) 541 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_ctx_mtx) 542 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_ctx_mtx) 543 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_ctx_mtx) 544 545 546 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 547 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 548 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 549 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 550 551 552 553 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 554 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 555 556 557 /* Our boot-time initialization hook */ 558 static int iflib_module_event_handler(module_t, int, void *); 559 560 static moduledata_t iflib_moduledata = { 561 "iflib", 562 iflib_module_event_handler, 563 NULL 564 }; 565 566 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 567 MODULE_VERSION(iflib, 1); 568 569 MODULE_DEPEND(iflib, pci, 1, 1, 1); 570 MODULE_DEPEND(iflib, ether, 1, 1, 1); 571 572 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 573 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 574 575 #ifndef IFLIB_DEBUG_COUNTERS 576 #ifdef INVARIANTS 577 #define IFLIB_DEBUG_COUNTERS 1 578 #else 579 #define IFLIB_DEBUG_COUNTERS 0 580 #endif /* !INVARIANTS */ 581 #endif 582 583 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 584 "iflib driver parameters"); 585 586 /* 587 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 588 */ 589 static int iflib_min_tx_latency = 0; 590 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 591 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 592 static int iflib_no_tx_batch = 0; 593 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 594 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 595 596 597 #if IFLIB_DEBUG_COUNTERS 598 599 static int iflib_tx_seen; 600 static int iflib_tx_sent; 601 static int iflib_tx_encap; 602 static int iflib_rx_allocs; 603 static int iflib_fl_refills; 604 static int iflib_fl_refills_large; 605 static int iflib_tx_frees; 606 607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 608 &iflib_tx_seen, 0, "# tx mbufs seen"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 610 &iflib_tx_sent, 0, "# tx mbufs sent"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 612 &iflib_tx_encap, 0, "# tx mbufs encapped"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 614 &iflib_tx_frees, 0, "# tx frees"); 615 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 616 &iflib_rx_allocs, 0, "# rx allocations"); 617 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 618 &iflib_fl_refills, 0, "# refills"); 619 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 620 &iflib_fl_refills_large, 0, "# large refills"); 621 622 623 static int iflib_txq_drain_flushing; 624 static int iflib_txq_drain_oactive; 625 static int iflib_txq_drain_notready; 626 static int iflib_txq_drain_encapfail; 627 628 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 629 &iflib_txq_drain_flushing, 0, "# drain flushes"); 630 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 631 &iflib_txq_drain_oactive, 0, "# drain oactives"); 632 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 633 &iflib_txq_drain_notready, 0, "# drain notready"); 634 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 635 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 636 637 638 static int iflib_encap_load_mbuf_fail; 639 static int iflib_encap_pad_mbuf_fail; 640 static int iflib_encap_txq_avail_fail; 641 static int iflib_encap_txd_encap_fail; 642 643 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 644 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 645 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 646 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 647 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 648 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 649 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 650 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 651 652 static int iflib_task_fn_rxs; 653 static int iflib_rx_intr_enables; 654 static int iflib_fast_intrs; 655 static int iflib_intr_link; 656 static int iflib_intr_msix; 657 static int iflib_rx_unavail; 658 static int iflib_rx_ctx_inactive; 659 static int iflib_rx_zero_len; 660 static int iflib_rx_if_input; 661 static int iflib_rx_mbuf_null; 662 static int iflib_rxd_flush; 663 664 static int iflib_verbose_debug; 665 666 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 667 &iflib_intr_link, 0, "# intr link calls"); 668 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 669 &iflib_intr_msix, 0, "# intr msix calls"); 670 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 671 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 672 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 673 &iflib_rx_intr_enables, 0, "# rx intr enables"); 674 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 675 &iflib_fast_intrs, 0, "# fast_intr calls"); 676 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 677 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 678 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 679 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 680 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 681 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 682 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 683 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 684 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 685 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 686 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 687 &iflib_rxd_flush, 0, "# times rxd_flush called"); 688 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 689 &iflib_verbose_debug, 0, "enable verbose debugging"); 690 691 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 692 static void 693 iflib_debug_reset(void) 694 { 695 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 696 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 697 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 698 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 699 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 700 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 701 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 702 iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 703 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 704 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 705 } 706 707 #else 708 #define DBG_COUNTER_INC(name) 709 static void iflib_debug_reset(void) {} 710 #endif 711 712 713 714 #define IFLIB_DEBUG 0 715 716 static void iflib_tx_structures_free(if_ctx_t ctx); 717 static void iflib_rx_structures_free(if_ctx_t ctx); 718 static int iflib_queues_alloc(if_ctx_t ctx); 719 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 720 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 721 static int iflib_qset_structures_setup(if_ctx_t ctx); 722 static int iflib_msix_init(if_ctx_t ctx); 723 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str); 724 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 725 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 726 static int iflib_register(if_ctx_t); 727 static void iflib_init_locked(if_ctx_t ctx); 728 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 729 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 730 static void iflib_ifmp_purge(iflib_txq_t txq); 731 static void _iflib_pre_assert(if_softc_ctx_t scctx); 732 static void iflib_stop(if_ctx_t ctx); 733 static void iflib_if_init_locked(if_ctx_t ctx); 734 #ifndef __NO_STRICT_ALIGNMENT 735 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 736 #endif 737 738 #ifdef DEV_NETMAP 739 #include <sys/selinfo.h> 740 #include <net/netmap.h> 741 #include <dev/netmap/netmap_kern.h> 742 743 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 744 745 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 746 747 /* 748 * device-specific sysctl variables: 749 * 750 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 751 * During regular operations the CRC is stripped, but on some 752 * hardware reception of frames not multiple of 64 is slower, 753 * so using crcstrip=0 helps in benchmarks. 754 * 755 * iflib_rx_miss, iflib_rx_miss_bufs: 756 * count packets that might be missed due to lost interrupts. 757 */ 758 SYSCTL_DECL(_dev_netmap); 759 /* 760 * The xl driver by default strips CRCs and we do not override it. 761 */ 762 763 int iflib_crcstrip = 1; 764 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 765 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 766 767 int iflib_rx_miss, iflib_rx_miss_bufs; 768 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 769 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 770 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 771 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 772 773 /* 774 * Register/unregister. We are already under netmap lock. 775 * Only called on the first register or the last unregister. 776 */ 777 static int 778 iflib_netmap_register(struct netmap_adapter *na, int onoff) 779 { 780 struct ifnet *ifp = na->ifp; 781 if_ctx_t ctx = ifp->if_softc; 782 int status; 783 784 CTX_LOCK(ctx); 785 IFDI_INTR_DISABLE(ctx); 786 787 /* Tell the stack that the interface is no longer active */ 788 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 789 790 if (!CTX_IS_VF(ctx)) 791 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 792 793 /* enable or disable flags and callbacks in na and ifp */ 794 if (onoff) { 795 nm_set_native_flags(na); 796 } else { 797 nm_clear_native_flags(na); 798 } 799 iflib_stop(ctx); 800 iflib_init_locked(ctx); 801 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 802 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 803 if (status) 804 nm_clear_native_flags(na); 805 CTX_UNLOCK(ctx); 806 return (status); 807 } 808 809 static int 810 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 811 { 812 struct netmap_adapter *na = kring->na; 813 u_int const lim = kring->nkr_num_slots - 1; 814 u_int head = kring->rhead; 815 struct netmap_ring *ring = kring->ring; 816 bus_dmamap_t *map; 817 struct if_rxd_update iru; 818 if_ctx_t ctx = rxq->ifr_ctx; 819 iflib_fl_t fl = &rxq->ifr_fl[0]; 820 uint32_t refill_pidx, nic_i; 821 822 if (nm_i == head && __predict_true(!init)) 823 return 0; 824 iru_init(&iru, rxq, 0 /* flid */); 825 map = fl->ifl_sds.ifsd_map; 826 refill_pidx = netmap_idx_k2n(kring, nm_i); 827 /* 828 * IMPORTANT: we must leave one free slot in the ring, 829 * so move head back by one unit 830 */ 831 head = nm_prev(head, lim); 832 while (nm_i != head) { 833 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 834 struct netmap_slot *slot = &ring->slot[nm_i]; 835 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 836 uint32_t nic_i_dma = refill_pidx; 837 nic_i = netmap_idx_k2n(kring, nm_i); 838 839 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 840 841 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 842 return netmap_ring_reinit(kring); 843 844 fl->ifl_vm_addrs[tmp_pidx] = addr; 845 if (__predict_false(init) && map) { 846 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 847 } else if (map && (slot->flags & NS_BUF_CHANGED)) { 848 /* buffer has changed, reload map */ 849 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 850 } 851 slot->flags &= ~NS_BUF_CHANGED; 852 853 nm_i = nm_next(nm_i, lim); 854 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 855 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 856 continue; 857 858 iru.iru_pidx = refill_pidx; 859 iru.iru_count = tmp_pidx+1; 860 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 861 862 refill_pidx = nic_i; 863 if (map == NULL) 864 continue; 865 866 for (int n = 0; n < iru.iru_count; n++) { 867 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma], 868 BUS_DMASYNC_PREREAD); 869 /* XXX - change this to not use the netmap func*/ 870 nic_i_dma = nm_next(nic_i_dma, lim); 871 } 872 } 873 } 874 kring->nr_hwcur = head; 875 876 if (map) 877 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 878 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 879 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 880 return (0); 881 } 882 883 /* 884 * Reconcile kernel and user view of the transmit ring. 885 * 886 * All information is in the kring. 887 * Userspace wants to send packets up to the one before kring->rhead, 888 * kernel knows kring->nr_hwcur is the first unsent packet. 889 * 890 * Here we push packets out (as many as possible), and possibly 891 * reclaim buffers from previously completed transmission. 892 * 893 * The caller (netmap) guarantees that there is only one instance 894 * running at any time. Any interference with other driver 895 * methods should be handled by the individual drivers. 896 */ 897 static int 898 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 899 { 900 struct netmap_adapter *na = kring->na; 901 struct ifnet *ifp = na->ifp; 902 struct netmap_ring *ring = kring->ring; 903 u_int nm_i; /* index into the netmap ring */ 904 u_int nic_i; /* index into the NIC ring */ 905 u_int n; 906 u_int const lim = kring->nkr_num_slots - 1; 907 u_int const head = kring->rhead; 908 struct if_pkt_info pi; 909 910 /* 911 * interrupts on every tx packet are expensive so request 912 * them every half ring, or where NS_REPORT is set 913 */ 914 u_int report_frequency = kring->nkr_num_slots >> 1; 915 /* device-specific */ 916 if_ctx_t ctx = ifp->if_softc; 917 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 918 919 if (txq->ift_sds.ifsd_map) 920 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 921 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 922 923 924 /* 925 * First part: process new packets to send. 926 * nm_i is the current index in the netmap ring, 927 * nic_i is the corresponding index in the NIC ring. 928 * 929 * If we have packets to send (nm_i != head) 930 * iterate over the netmap ring, fetch length and update 931 * the corresponding slot in the NIC ring. Some drivers also 932 * need to update the buffer's physical address in the NIC slot 933 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 934 * 935 * The netmap_reload_map() calls is especially expensive, 936 * even when (as in this case) the tag is 0, so do only 937 * when the buffer has actually changed. 938 * 939 * If possible do not set the report/intr bit on all slots, 940 * but only a few times per ring or when NS_REPORT is set. 941 * 942 * Finally, on 10G and faster drivers, it might be useful 943 * to prefetch the next slot and txr entry. 944 */ 945 946 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 947 pkt_info_zero(&pi); 948 pi.ipi_segs = txq->ift_segs; 949 pi.ipi_qsidx = kring->ring_id; 950 if (nm_i != head) { /* we have new packets to send */ 951 nic_i = netmap_idx_k2n(kring, nm_i); 952 953 __builtin_prefetch(&ring->slot[nm_i]); 954 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 955 if (txq->ift_sds.ifsd_map) 956 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 957 958 for (n = 0; nm_i != head; n++) { 959 struct netmap_slot *slot = &ring->slot[nm_i]; 960 u_int len = slot->len; 961 uint64_t paddr; 962 void *addr = PNMB(na, slot, &paddr); 963 int flags = (slot->flags & NS_REPORT || 964 nic_i == 0 || nic_i == report_frequency) ? 965 IPI_TX_INTR : 0; 966 967 /* device-specific */ 968 pi.ipi_len = len; 969 pi.ipi_segs[0].ds_addr = paddr; 970 pi.ipi_segs[0].ds_len = len; 971 pi.ipi_nsegs = 1; 972 pi.ipi_ndescs = 0; 973 pi.ipi_pidx = nic_i; 974 pi.ipi_flags = flags; 975 976 /* Fill the slot in the NIC ring. */ 977 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 978 979 /* prefetch for next round */ 980 __builtin_prefetch(&ring->slot[nm_i + 1]); 981 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 982 if (txq->ift_sds.ifsd_map) { 983 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 984 985 NM_CHECK_ADDR_LEN(na, addr, len); 986 987 if (slot->flags & NS_BUF_CHANGED) { 988 /* buffer has changed, reload map */ 989 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 990 } 991 /* make sure changes to the buffer are synced */ 992 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 993 BUS_DMASYNC_PREWRITE); 994 } 995 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 996 nm_i = nm_next(nm_i, lim); 997 nic_i = nm_next(nic_i, lim); 998 } 999 kring->nr_hwcur = head; 1000 1001 /* synchronize the NIC ring */ 1002 if (txq->ift_sds.ifsd_map) 1003 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 1004 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1005 1006 /* (re)start the tx unit up to slot nic_i (excluded) */ 1007 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1008 } 1009 1010 /* 1011 * Second part: reclaim buffers for completed transmissions. 1012 */ 1013 if (iflib_tx_credits_update(ctx, txq)) { 1014 /* some tx completed, increment avail */ 1015 nic_i = txq->ift_cidx_processed; 1016 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1017 } 1018 return (0); 1019 } 1020 1021 /* 1022 * Reconcile kernel and user view of the receive ring. 1023 * Same as for the txsync, this routine must be efficient. 1024 * The caller guarantees a single invocations, but races against 1025 * the rest of the driver should be handled here. 1026 * 1027 * On call, kring->rhead is the first packet that userspace wants 1028 * to keep, and kring->rcur is the wakeup point. 1029 * The kernel has previously reported packets up to kring->rtail. 1030 * 1031 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1032 * of whether or not we received an interrupt. 1033 */ 1034 static int 1035 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1036 { 1037 struct netmap_adapter *na = kring->na; 1038 struct netmap_ring *ring = kring->ring; 1039 uint32_t nm_i; /* index into the netmap ring */ 1040 uint32_t nic_i; /* index into the NIC ring */ 1041 u_int i, n; 1042 u_int const lim = kring->nkr_num_slots - 1; 1043 u_int const head = netmap_idx_n2k(kring, kring->rhead); 1044 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1045 struct if_rxd_info ri; 1046 1047 struct ifnet *ifp = na->ifp; 1048 if_ctx_t ctx = ifp->if_softc; 1049 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1050 iflib_fl_t fl = rxq->ifr_fl; 1051 if (head > lim) 1052 return netmap_ring_reinit(kring); 1053 1054 /* XXX check sync modes */ 1055 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1056 if (fl->ifl_sds.ifsd_map == NULL) 1057 continue; 1058 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 1059 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1060 } 1061 /* 1062 * First part: import newly received packets. 1063 * 1064 * nm_i is the index of the next free slot in the netmap ring, 1065 * nic_i is the index of the next received packet in the NIC ring, 1066 * and they may differ in case if_init() has been called while 1067 * in netmap mode. For the receive ring we have 1068 * 1069 * nic_i = rxr->next_check; 1070 * nm_i = kring->nr_hwtail (previous) 1071 * and 1072 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1073 * 1074 * rxr->next_check is set to 0 on a ring reinit 1075 */ 1076 if (netmap_no_pendintr || force_update) { 1077 int crclen = iflib_crcstrip ? 0 : 4; 1078 int error, avail; 1079 1080 for (i = 0; i < rxq->ifr_nfl; i++) { 1081 fl = &rxq->ifr_fl[i]; 1082 nic_i = fl->ifl_cidx; 1083 nm_i = netmap_idx_n2k(kring, nic_i); 1084 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 1085 for (n = 0; avail > 0; n++, avail--) { 1086 rxd_info_zero(&ri); 1087 ri.iri_frags = rxq->ifr_frags; 1088 ri.iri_qsidx = kring->ring_id; 1089 ri.iri_ifp = ctx->ifc_ifp; 1090 ri.iri_cidx = nic_i; 1091 1092 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1093 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1094 ring->slot[nm_i].flags = 0; 1095 if (fl->ifl_sds.ifsd_map) 1096 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1097 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1098 nm_i = nm_next(nm_i, lim); 1099 nic_i = nm_next(nic_i, lim); 1100 } 1101 if (n) { /* update the state variables */ 1102 if (netmap_no_pendintr && !force_update) { 1103 /* diagnostics */ 1104 iflib_rx_miss ++; 1105 iflib_rx_miss_bufs += n; 1106 } 1107 fl->ifl_cidx = nic_i; 1108 kring->nr_hwtail = netmap_idx_k2n(kring, nm_i); 1109 } 1110 kring->nr_kflags &= ~NKR_PENDINTR; 1111 } 1112 } 1113 /* 1114 * Second part: skip past packets that userspace has released. 1115 * (kring->nr_hwcur to head excluded), 1116 * and make the buffers available for reception. 1117 * As usual nm_i is the index in the netmap ring, 1118 * nic_i is the index in the NIC ring, and 1119 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1120 */ 1121 /* XXX not sure how this will work with multiple free lists */ 1122 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 1123 1124 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1125 } 1126 1127 static void 1128 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1129 { 1130 struct ifnet *ifp = na->ifp; 1131 if_ctx_t ctx = ifp->if_softc; 1132 1133 CTX_LOCK(ctx); 1134 if (onoff) { 1135 IFDI_INTR_ENABLE(ctx); 1136 } else { 1137 IFDI_INTR_DISABLE(ctx); 1138 } 1139 CTX_UNLOCK(ctx); 1140 } 1141 1142 1143 static int 1144 iflib_netmap_attach(if_ctx_t ctx) 1145 { 1146 struct netmap_adapter na; 1147 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1148 1149 bzero(&na, sizeof(na)); 1150 1151 na.ifp = ctx->ifc_ifp; 1152 na.na_flags = NAF_BDG_MAYSLEEP; 1153 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1154 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1155 1156 na.num_tx_desc = scctx->isc_ntxd[0]; 1157 na.num_rx_desc = scctx->isc_nrxd[0]; 1158 na.nm_txsync = iflib_netmap_txsync; 1159 na.nm_rxsync = iflib_netmap_rxsync; 1160 na.nm_register = iflib_netmap_register; 1161 na.nm_intr = iflib_netmap_intr; 1162 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1163 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1164 return (netmap_attach(&na)); 1165 } 1166 1167 static void 1168 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1169 { 1170 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1171 struct netmap_slot *slot; 1172 1173 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1174 if (slot == NULL) 1175 return; 1176 if (txq->ift_sds.ifsd_map == NULL) 1177 return; 1178 1179 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1180 1181 /* 1182 * In netmap mode, set the map for the packet buffer. 1183 * NOTE: Some drivers (not this one) also need to set 1184 * the physical buffer address in the NIC ring. 1185 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1186 * netmap slot index, si 1187 */ 1188 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1189 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1190 } 1191 } 1192 1193 static void 1194 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1195 { 1196 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1197 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1198 struct netmap_slot *slot; 1199 uint32_t nm_i; 1200 1201 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1202 if (slot == NULL) 1203 return; 1204 nm_i = netmap_idx_n2k(kring, 0); 1205 netmap_fl_refill(rxq, kring, nm_i, true); 1206 } 1207 1208 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1209 1210 #else 1211 #define iflib_netmap_txq_init(ctx, txq) 1212 #define iflib_netmap_rxq_init(ctx, rxq) 1213 #define iflib_netmap_detach(ifp) 1214 1215 #define iflib_netmap_attach(ctx) (0) 1216 #define netmap_rx_irq(ifp, qid, budget) (0) 1217 #define netmap_tx_irq(ifp, qid) do {} while (0) 1218 1219 #endif 1220 1221 #if defined(__i386__) || defined(__amd64__) 1222 static __inline void 1223 prefetch(void *x) 1224 { 1225 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1226 } 1227 static __inline void 1228 prefetch2cachelines(void *x) 1229 { 1230 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1231 #if (CACHE_LINE_SIZE < 128) 1232 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1233 #endif 1234 } 1235 #else 1236 #define prefetch(x) 1237 #define prefetch2cachelines(x) 1238 #endif 1239 1240 static void 1241 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1242 { 1243 iflib_fl_t fl; 1244 1245 fl = &rxq->ifr_fl[flid]; 1246 iru->iru_paddrs = fl->ifl_bus_addrs; 1247 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1248 iru->iru_idxs = fl->ifl_rxd_idxs; 1249 iru->iru_qsidx = rxq->ifr_id; 1250 iru->iru_buf_size = fl->ifl_buf_size; 1251 iru->iru_flidx = fl->ifl_id; 1252 } 1253 1254 static void 1255 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1256 { 1257 if (err) 1258 return; 1259 *(bus_addr_t *) arg = segs[0].ds_addr; 1260 } 1261 1262 int 1263 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1264 { 1265 int err; 1266 if_shared_ctx_t sctx = ctx->ifc_sctx; 1267 device_t dev = ctx->ifc_dev; 1268 1269 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1270 1271 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1272 sctx->isc_q_align, 0, /* alignment, bounds */ 1273 BUS_SPACE_MAXADDR, /* lowaddr */ 1274 BUS_SPACE_MAXADDR, /* highaddr */ 1275 NULL, NULL, /* filter, filterarg */ 1276 size, /* maxsize */ 1277 1, /* nsegments */ 1278 size, /* maxsegsize */ 1279 BUS_DMA_ALLOCNOW, /* flags */ 1280 NULL, /* lockfunc */ 1281 NULL, /* lockarg */ 1282 &dma->idi_tag); 1283 if (err) { 1284 device_printf(dev, 1285 "%s: bus_dma_tag_create failed: %d\n", 1286 __func__, err); 1287 goto fail_0; 1288 } 1289 1290 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1291 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1292 if (err) { 1293 device_printf(dev, 1294 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1295 __func__, (uintmax_t)size, err); 1296 goto fail_1; 1297 } 1298 1299 dma->idi_paddr = IF_BAD_DMA; 1300 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1301 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1302 if (err || dma->idi_paddr == IF_BAD_DMA) { 1303 device_printf(dev, 1304 "%s: bus_dmamap_load failed: %d\n", 1305 __func__, err); 1306 goto fail_2; 1307 } 1308 1309 dma->idi_size = size; 1310 return (0); 1311 1312 fail_2: 1313 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1314 fail_1: 1315 bus_dma_tag_destroy(dma->idi_tag); 1316 fail_0: 1317 dma->idi_tag = NULL; 1318 1319 return (err); 1320 } 1321 1322 int 1323 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1324 { 1325 int i, err; 1326 iflib_dma_info_t *dmaiter; 1327 1328 dmaiter = dmalist; 1329 for (i = 0; i < count; i++, dmaiter++) { 1330 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1331 break; 1332 } 1333 if (err) 1334 iflib_dma_free_multi(dmalist, i); 1335 return (err); 1336 } 1337 1338 void 1339 iflib_dma_free(iflib_dma_info_t dma) 1340 { 1341 if (dma->idi_tag == NULL) 1342 return; 1343 if (dma->idi_paddr != IF_BAD_DMA) { 1344 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1345 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1346 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1347 dma->idi_paddr = IF_BAD_DMA; 1348 } 1349 if (dma->idi_vaddr != NULL) { 1350 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1351 dma->idi_vaddr = NULL; 1352 } 1353 bus_dma_tag_destroy(dma->idi_tag); 1354 dma->idi_tag = NULL; 1355 } 1356 1357 void 1358 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1359 { 1360 int i; 1361 iflib_dma_info_t *dmaiter = dmalist; 1362 1363 for (i = 0; i < count; i++, dmaiter++) 1364 iflib_dma_free(*dmaiter); 1365 } 1366 1367 #ifdef EARLY_AP_STARTUP 1368 static const int iflib_started = 1; 1369 #else 1370 /* 1371 * We used to abuse the smp_started flag to decide if the queues have been 1372 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1373 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1374 * is set. Run a SYSINIT() strictly after that to just set a usable 1375 * completion flag. 1376 */ 1377 1378 static int iflib_started; 1379 1380 static void 1381 iflib_record_started(void *arg) 1382 { 1383 iflib_started = 1; 1384 } 1385 1386 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1387 iflib_record_started, NULL); 1388 #endif 1389 1390 static int 1391 iflib_fast_intr(void *arg) 1392 { 1393 iflib_filter_info_t info = arg; 1394 struct grouptask *gtask = info->ifi_task; 1395 if (!iflib_started) 1396 return (FILTER_HANDLED); 1397 1398 DBG_COUNTER_INC(fast_intrs); 1399 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1400 return (FILTER_HANDLED); 1401 1402 GROUPTASK_ENQUEUE(gtask); 1403 return (FILTER_HANDLED); 1404 } 1405 1406 static int 1407 iflib_fast_intr_rxtx(void *arg) 1408 { 1409 iflib_filter_info_t info = arg; 1410 struct grouptask *gtask = info->ifi_task; 1411 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1412 if_ctx_t ctx; 1413 int i, cidx; 1414 1415 if (!iflib_started) 1416 return (FILTER_HANDLED); 1417 1418 DBG_COUNTER_INC(fast_intrs); 1419 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1420 return (FILTER_HANDLED); 1421 1422 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1423 qidx_t txqid = rxq->ifr_txqid[i]; 1424 1425 ctx = rxq->ifr_ctx; 1426 1427 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1428 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1429 continue; 1430 } 1431 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1432 } 1433 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1434 cidx = rxq->ifr_cq_cidx; 1435 else 1436 cidx = rxq->ifr_fl[0].ifl_cidx; 1437 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1438 GROUPTASK_ENQUEUE(gtask); 1439 else 1440 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1441 return (FILTER_HANDLED); 1442 } 1443 1444 1445 static int 1446 iflib_fast_intr_ctx(void *arg) 1447 { 1448 iflib_filter_info_t info = arg; 1449 struct grouptask *gtask = info->ifi_task; 1450 1451 if (!iflib_started) 1452 return (FILTER_HANDLED); 1453 1454 DBG_COUNTER_INC(fast_intrs); 1455 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1456 return (FILTER_HANDLED); 1457 1458 GROUPTASK_ENQUEUE(gtask); 1459 return (FILTER_HANDLED); 1460 } 1461 1462 static int 1463 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1464 driver_filter_t filter, driver_intr_t handler, void *arg, 1465 char *name) 1466 { 1467 int rc, flags; 1468 struct resource *res; 1469 void *tag = NULL; 1470 device_t dev = ctx->ifc_dev; 1471 1472 flags = RF_ACTIVE; 1473 if (ctx->ifc_flags & IFC_LEGACY) 1474 flags |= RF_SHAREABLE; 1475 MPASS(rid < 512); 1476 irq->ii_rid = rid; 1477 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1478 if (res == NULL) { 1479 device_printf(dev, 1480 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1481 return (ENOMEM); 1482 } 1483 irq->ii_res = res; 1484 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1485 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1486 filter, handler, arg, &tag); 1487 if (rc != 0) { 1488 device_printf(dev, 1489 "failed to setup interrupt for rid %d, name %s: %d\n", 1490 rid, name ? name : "unknown", rc); 1491 return (rc); 1492 } else if (name) 1493 bus_describe_intr(dev, res, tag, "%s", name); 1494 1495 irq->ii_tag = tag; 1496 return (0); 1497 } 1498 1499 1500 /********************************************************************* 1501 * 1502 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1503 * the information needed to transmit a packet on the wire. This is 1504 * called only once at attach, setup is done every reset. 1505 * 1506 **********************************************************************/ 1507 1508 static int 1509 iflib_txsd_alloc(iflib_txq_t txq) 1510 { 1511 if_ctx_t ctx = txq->ift_ctx; 1512 if_shared_ctx_t sctx = ctx->ifc_sctx; 1513 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1514 device_t dev = ctx->ifc_dev; 1515 int err, nsegments, ntsosegments; 1516 1517 nsegments = scctx->isc_tx_nsegments; 1518 ntsosegments = scctx->isc_tx_tso_segments_max; 1519 MPASS(scctx->isc_ntxd[0] > 0); 1520 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1521 MPASS(nsegments > 0); 1522 MPASS(ntsosegments > 0); 1523 /* 1524 * Setup DMA descriptor areas. 1525 */ 1526 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1527 1, 0, /* alignment, bounds */ 1528 BUS_SPACE_MAXADDR, /* lowaddr */ 1529 BUS_SPACE_MAXADDR, /* highaddr */ 1530 NULL, NULL, /* filter, filterarg */ 1531 sctx->isc_tx_maxsize, /* maxsize */ 1532 nsegments, /* nsegments */ 1533 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1534 0, /* flags */ 1535 NULL, /* lockfunc */ 1536 NULL, /* lockfuncarg */ 1537 &txq->ift_desc_tag))) { 1538 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1539 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1540 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1541 goto fail; 1542 } 1543 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1544 1, 0, /* alignment, bounds */ 1545 BUS_SPACE_MAXADDR, /* lowaddr */ 1546 BUS_SPACE_MAXADDR, /* highaddr */ 1547 NULL, NULL, /* filter, filterarg */ 1548 scctx->isc_tx_tso_size_max, /* maxsize */ 1549 ntsosegments, /* nsegments */ 1550 scctx->isc_tx_tso_segsize_max, /* maxsegsize */ 1551 0, /* flags */ 1552 NULL, /* lockfunc */ 1553 NULL, /* lockfuncarg */ 1554 &txq->ift_tso_desc_tag))) { 1555 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1556 1557 goto fail; 1558 } 1559 if (!(txq->ift_sds.ifsd_flags = 1560 (uint8_t *) malloc(sizeof(uint8_t) * 1561 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1562 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1563 err = ENOMEM; 1564 goto fail; 1565 } 1566 if (!(txq->ift_sds.ifsd_m = 1567 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1568 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1569 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1570 err = ENOMEM; 1571 goto fail; 1572 } 1573 1574 /* Create the descriptor buffer dma maps */ 1575 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1576 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1577 return (0); 1578 1579 if (!(txq->ift_sds.ifsd_map = 1580 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1581 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1582 err = ENOMEM; 1583 goto fail; 1584 } 1585 1586 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1587 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1588 if (err != 0) { 1589 device_printf(dev, "Unable to create TX DMA map\n"); 1590 goto fail; 1591 } 1592 } 1593 #endif 1594 return (0); 1595 fail: 1596 /* We free all, it handles case where we are in the middle */ 1597 iflib_tx_structures_free(ctx); 1598 return (err); 1599 } 1600 1601 static void 1602 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1603 { 1604 bus_dmamap_t map; 1605 1606 map = NULL; 1607 if (txq->ift_sds.ifsd_map != NULL) 1608 map = txq->ift_sds.ifsd_map[i]; 1609 if (map != NULL) { 1610 bus_dmamap_unload(txq->ift_desc_tag, map); 1611 bus_dmamap_destroy(txq->ift_desc_tag, map); 1612 txq->ift_sds.ifsd_map[i] = NULL; 1613 } 1614 } 1615 1616 static void 1617 iflib_txq_destroy(iflib_txq_t txq) 1618 { 1619 if_ctx_t ctx = txq->ift_ctx; 1620 1621 for (int i = 0; i < txq->ift_size; i++) 1622 iflib_txsd_destroy(ctx, txq, i); 1623 if (txq->ift_sds.ifsd_map != NULL) { 1624 free(txq->ift_sds.ifsd_map, M_IFLIB); 1625 txq->ift_sds.ifsd_map = NULL; 1626 } 1627 if (txq->ift_sds.ifsd_m != NULL) { 1628 free(txq->ift_sds.ifsd_m, M_IFLIB); 1629 txq->ift_sds.ifsd_m = NULL; 1630 } 1631 if (txq->ift_sds.ifsd_flags != NULL) { 1632 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1633 txq->ift_sds.ifsd_flags = NULL; 1634 } 1635 if (txq->ift_desc_tag != NULL) { 1636 bus_dma_tag_destroy(txq->ift_desc_tag); 1637 txq->ift_desc_tag = NULL; 1638 } 1639 if (txq->ift_tso_desc_tag != NULL) { 1640 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1641 txq->ift_tso_desc_tag = NULL; 1642 } 1643 } 1644 1645 static void 1646 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1647 { 1648 struct mbuf **mp; 1649 1650 mp = &txq->ift_sds.ifsd_m[i]; 1651 if (*mp == NULL) 1652 return; 1653 1654 if (txq->ift_sds.ifsd_map != NULL) { 1655 bus_dmamap_sync(txq->ift_desc_tag, 1656 txq->ift_sds.ifsd_map[i], 1657 BUS_DMASYNC_POSTWRITE); 1658 bus_dmamap_unload(txq->ift_desc_tag, 1659 txq->ift_sds.ifsd_map[i]); 1660 } 1661 m_free(*mp); 1662 DBG_COUNTER_INC(tx_frees); 1663 *mp = NULL; 1664 } 1665 1666 static int 1667 iflib_txq_setup(iflib_txq_t txq) 1668 { 1669 if_ctx_t ctx = txq->ift_ctx; 1670 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1671 iflib_dma_info_t di; 1672 int i; 1673 1674 /* Set number of descriptors available */ 1675 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1676 /* XXX make configurable */ 1677 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1678 1679 /* Reset indices */ 1680 txq->ift_cidx_processed = 0; 1681 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1682 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1683 1684 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1685 bzero((void *)di->idi_vaddr, di->idi_size); 1686 1687 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1688 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1689 bus_dmamap_sync(di->idi_tag, di->idi_map, 1690 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1691 return (0); 1692 } 1693 1694 /********************************************************************* 1695 * 1696 * Allocate memory for rx_buffer structures. Since we use one 1697 * rx_buffer per received packet, the maximum number of rx_buffer's 1698 * that we'll need is equal to the number of receive descriptors 1699 * that we've allocated. 1700 * 1701 **********************************************************************/ 1702 static int 1703 iflib_rxsd_alloc(iflib_rxq_t rxq) 1704 { 1705 if_ctx_t ctx = rxq->ifr_ctx; 1706 if_shared_ctx_t sctx = ctx->ifc_sctx; 1707 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1708 device_t dev = ctx->ifc_dev; 1709 iflib_fl_t fl; 1710 int err; 1711 1712 MPASS(scctx->isc_nrxd[0] > 0); 1713 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1714 1715 fl = rxq->ifr_fl; 1716 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1717 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1718 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1719 1, 0, /* alignment, bounds */ 1720 BUS_SPACE_MAXADDR, /* lowaddr */ 1721 BUS_SPACE_MAXADDR, /* highaddr */ 1722 NULL, NULL, /* filter, filterarg */ 1723 sctx->isc_rx_maxsize, /* maxsize */ 1724 sctx->isc_rx_nsegments, /* nsegments */ 1725 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1726 0, /* flags */ 1727 NULL, /* lockfunc */ 1728 NULL, /* lockarg */ 1729 &fl->ifl_desc_tag); 1730 if (err) { 1731 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1732 __func__, err); 1733 goto fail; 1734 } 1735 if (!(fl->ifl_sds.ifsd_flags = 1736 (uint8_t *) malloc(sizeof(uint8_t) * 1737 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1738 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1739 err = ENOMEM; 1740 goto fail; 1741 } 1742 if (!(fl->ifl_sds.ifsd_m = 1743 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1744 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1745 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1746 err = ENOMEM; 1747 goto fail; 1748 } 1749 if (!(fl->ifl_sds.ifsd_cl = 1750 (caddr_t *) malloc(sizeof(caddr_t) * 1751 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1752 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1753 err = ENOMEM; 1754 goto fail; 1755 } 1756 1757 /* Create the descriptor buffer dma maps */ 1758 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1759 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1760 continue; 1761 1762 if (!(fl->ifl_sds.ifsd_map = 1763 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1764 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1765 err = ENOMEM; 1766 goto fail; 1767 } 1768 1769 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1770 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1771 if (err != 0) { 1772 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1773 goto fail; 1774 } 1775 } 1776 #endif 1777 } 1778 return (0); 1779 1780 fail: 1781 iflib_rx_structures_free(ctx); 1782 return (err); 1783 } 1784 1785 1786 /* 1787 * Internal service routines 1788 */ 1789 1790 struct rxq_refill_cb_arg { 1791 int error; 1792 bus_dma_segment_t seg; 1793 int nseg; 1794 }; 1795 1796 static void 1797 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1798 { 1799 struct rxq_refill_cb_arg *cb_arg = arg; 1800 1801 cb_arg->error = error; 1802 cb_arg->seg = segs[0]; 1803 cb_arg->nseg = nseg; 1804 } 1805 1806 1807 #ifdef ACPI_DMAR 1808 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1809 #else 1810 #define IS_DMAR(ctx) (0) 1811 #endif 1812 1813 /** 1814 * rxq_refill - refill an rxq free-buffer list 1815 * @ctx: the iflib context 1816 * @rxq: the free-list to refill 1817 * @n: the number of new buffers to allocate 1818 * 1819 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1820 * The caller must assure that @n does not exceed the queue's capacity. 1821 */ 1822 static void 1823 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1824 { 1825 struct mbuf *m; 1826 int idx, frag_idx = fl->ifl_fragidx; 1827 int pidx = fl->ifl_pidx; 1828 caddr_t cl, *sd_cl; 1829 struct mbuf **sd_m; 1830 uint8_t *sd_flags; 1831 struct if_rxd_update iru; 1832 bus_dmamap_t *sd_map; 1833 int n, i = 0; 1834 uint64_t bus_addr; 1835 int err; 1836 qidx_t credits; 1837 1838 sd_m = fl->ifl_sds.ifsd_m; 1839 sd_map = fl->ifl_sds.ifsd_map; 1840 sd_cl = fl->ifl_sds.ifsd_cl; 1841 sd_flags = fl->ifl_sds.ifsd_flags; 1842 idx = pidx; 1843 credits = fl->ifl_credits; 1844 1845 n = count; 1846 MPASS(n > 0); 1847 MPASS(credits + n <= fl->ifl_size); 1848 1849 if (pidx < fl->ifl_cidx) 1850 MPASS(pidx + n <= fl->ifl_cidx); 1851 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1852 MPASS(fl->ifl_gen == 0); 1853 if (pidx > fl->ifl_cidx) 1854 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1855 1856 DBG_COUNTER_INC(fl_refills); 1857 if (n > 8) 1858 DBG_COUNTER_INC(fl_refills_large); 1859 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1860 while (n--) { 1861 /* 1862 * We allocate an uninitialized mbuf + cluster, mbuf is 1863 * initialized after rx. 1864 * 1865 * If the cluster is still set then we know a minimum sized packet was received 1866 */ 1867 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1868 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1869 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1870 if ((cl = sd_cl[frag_idx]) == NULL) { 1871 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1872 break; 1873 #if MEMORY_LOGGING 1874 fl->ifl_cl_enqueued++; 1875 #endif 1876 } 1877 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1878 break; 1879 } 1880 #if MEMORY_LOGGING 1881 fl->ifl_m_enqueued++; 1882 #endif 1883 1884 DBG_COUNTER_INC(rx_allocs); 1885 #if defined(__i386__) || defined(__amd64__) 1886 if (!IS_DMAR(ctx)) { 1887 bus_addr = pmap_kextract((vm_offset_t)cl); 1888 } else 1889 #endif 1890 { 1891 struct rxq_refill_cb_arg cb_arg; 1892 iflib_rxq_t q; 1893 1894 cb_arg.error = 0; 1895 q = fl->ifl_rxq; 1896 MPASS(sd_map != NULL); 1897 MPASS(sd_map[frag_idx] != NULL); 1898 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1899 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1900 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 1901 BUS_DMASYNC_PREREAD); 1902 1903 if (err != 0 || cb_arg.error) { 1904 /* 1905 * !zone_pack ? 1906 */ 1907 if (fl->ifl_zone == zone_pack) 1908 uma_zfree(fl->ifl_zone, cl); 1909 m_free(m); 1910 n = 0; 1911 goto done; 1912 } 1913 bus_addr = cb_arg.seg.ds_addr; 1914 } 1915 bit_set(fl->ifl_rx_bitmap, frag_idx); 1916 sd_flags[frag_idx] |= RX_SW_DESC_INUSE; 1917 1918 MPASS(sd_m[frag_idx] == NULL); 1919 sd_cl[frag_idx] = cl; 1920 sd_m[frag_idx] = m; 1921 fl->ifl_rxd_idxs[i] = frag_idx; 1922 fl->ifl_bus_addrs[i] = bus_addr; 1923 fl->ifl_vm_addrs[i] = cl; 1924 credits++; 1925 i++; 1926 MPASS(credits <= fl->ifl_size); 1927 if (++idx == fl->ifl_size) { 1928 fl->ifl_gen = 1; 1929 idx = 0; 1930 } 1931 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 1932 iru.iru_pidx = pidx; 1933 iru.iru_count = i; 1934 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1935 i = 0; 1936 pidx = idx; 1937 fl->ifl_pidx = idx; 1938 fl->ifl_credits = credits; 1939 } 1940 1941 } 1942 done: 1943 if (i) { 1944 iru.iru_pidx = pidx; 1945 iru.iru_count = i; 1946 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1947 fl->ifl_pidx = idx; 1948 fl->ifl_credits = credits; 1949 } 1950 DBG_COUNTER_INC(rxd_flush); 1951 if (fl->ifl_pidx == 0) 1952 pidx = fl->ifl_size - 1; 1953 else 1954 pidx = fl->ifl_pidx - 1; 1955 1956 if (sd_map) 1957 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1958 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1959 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 1960 fl->ifl_fragidx = frag_idx; 1961 } 1962 1963 static __inline void 1964 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 1965 { 1966 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 1967 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 1968 #ifdef INVARIANTS 1969 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 1970 #endif 1971 1972 MPASS(fl->ifl_credits <= fl->ifl_size); 1973 MPASS(reclaimable == delta); 1974 1975 if (reclaimable > 0) 1976 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 1977 } 1978 1979 static void 1980 iflib_fl_bufs_free(iflib_fl_t fl) 1981 { 1982 iflib_dma_info_t idi = fl->ifl_ifdi; 1983 uint32_t i; 1984 1985 for (i = 0; i < fl->ifl_size; i++) { 1986 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 1987 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 1988 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 1989 1990 if (*sd_flags & RX_SW_DESC_INUSE) { 1991 if (fl->ifl_sds.ifsd_map != NULL) { 1992 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 1993 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 1994 if (fl->ifl_rxq->ifr_ctx->ifc_in_detach) 1995 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 1996 } 1997 if (*sd_m != NULL) { 1998 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 1999 uma_zfree(zone_mbuf, *sd_m); 2000 } 2001 if (*sd_cl != NULL) 2002 uma_zfree(fl->ifl_zone, *sd_cl); 2003 *sd_flags = 0; 2004 } else { 2005 MPASS(*sd_cl == NULL); 2006 MPASS(*sd_m == NULL); 2007 } 2008 #if MEMORY_LOGGING 2009 fl->ifl_m_dequeued++; 2010 fl->ifl_cl_dequeued++; 2011 #endif 2012 *sd_cl = NULL; 2013 *sd_m = NULL; 2014 } 2015 #ifdef INVARIANTS 2016 for (i = 0; i < fl->ifl_size; i++) { 2017 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 2018 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2019 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2020 } 2021 #endif 2022 /* 2023 * Reset free list values 2024 */ 2025 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2026 bzero(idi->idi_vaddr, idi->idi_size); 2027 } 2028 2029 /********************************************************************* 2030 * 2031 * Initialize a receive ring and its buffers. 2032 * 2033 **********************************************************************/ 2034 static int 2035 iflib_fl_setup(iflib_fl_t fl) 2036 { 2037 iflib_rxq_t rxq = fl->ifl_rxq; 2038 if_ctx_t ctx = rxq->ifr_ctx; 2039 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2040 2041 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2042 /* 2043 ** Free current RX buffer structs and their mbufs 2044 */ 2045 iflib_fl_bufs_free(fl); 2046 /* Now replenish the mbufs */ 2047 MPASS(fl->ifl_credits == 0); 2048 /* 2049 * XXX don't set the max_frame_size to larger 2050 * than the hardware can handle 2051 */ 2052 if (sctx->isc_max_frame_size <= 2048) 2053 fl->ifl_buf_size = MCLBYTES; 2054 #ifndef CONTIGMALLOC_WORKS 2055 else 2056 fl->ifl_buf_size = MJUMPAGESIZE; 2057 #else 2058 else if (sctx->isc_max_frame_size <= 4096) 2059 fl->ifl_buf_size = MJUMPAGESIZE; 2060 else if (sctx->isc_max_frame_size <= 9216) 2061 fl->ifl_buf_size = MJUM9BYTES; 2062 else 2063 fl->ifl_buf_size = MJUM16BYTES; 2064 #endif 2065 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2066 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2067 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2068 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2069 2070 2071 /* avoid pre-allocating zillions of clusters to an idle card 2072 * potentially speeding up attach 2073 */ 2074 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2075 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2076 if (min(128, fl->ifl_size) != fl->ifl_credits) 2077 return (ENOBUFS); 2078 /* 2079 * handle failure 2080 */ 2081 MPASS(rxq != NULL); 2082 MPASS(fl->ifl_ifdi != NULL); 2083 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2084 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2085 return (0); 2086 } 2087 2088 /********************************************************************* 2089 * 2090 * Free receive ring data structures 2091 * 2092 **********************************************************************/ 2093 static void 2094 iflib_rx_sds_free(iflib_rxq_t rxq) 2095 { 2096 iflib_fl_t fl; 2097 int i; 2098 2099 if (rxq->ifr_fl != NULL) { 2100 for (i = 0; i < rxq->ifr_nfl; i++) { 2101 fl = &rxq->ifr_fl[i]; 2102 if (fl->ifl_desc_tag != NULL) { 2103 bus_dma_tag_destroy(fl->ifl_desc_tag); 2104 fl->ifl_desc_tag = NULL; 2105 } 2106 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2107 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2108 /* XXX destroy maps first */ 2109 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2110 fl->ifl_sds.ifsd_m = NULL; 2111 fl->ifl_sds.ifsd_cl = NULL; 2112 fl->ifl_sds.ifsd_map = NULL; 2113 } 2114 free(rxq->ifr_fl, M_IFLIB); 2115 rxq->ifr_fl = NULL; 2116 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2117 } 2118 } 2119 2120 /* 2121 * MI independent logic 2122 * 2123 */ 2124 static void 2125 iflib_timer(void *arg) 2126 { 2127 iflib_txq_t txq = arg; 2128 if_ctx_t ctx = txq->ift_ctx; 2129 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2130 2131 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2132 return; 2133 /* 2134 ** Check on the state of the TX queue(s), this 2135 ** can be done without the lock because its RO 2136 ** and the HUNG state will be static if set. 2137 */ 2138 IFDI_TIMER(ctx, txq->ift_id); 2139 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2140 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2141 (sctx->isc_pause_frames == 0))) 2142 goto hung; 2143 2144 if (ifmp_ring_is_stalled(txq->ift_br)) 2145 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2146 txq->ift_cleaned_prev = txq->ift_cleaned; 2147 /* handle any laggards */ 2148 if (txq->ift_db_pending) 2149 GROUPTASK_ENQUEUE(&txq->ift_task); 2150 2151 sctx->isc_pause_frames = 0; 2152 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2153 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 2154 return; 2155 hung: 2156 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2157 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2158 STATE_LOCK(ctx); 2159 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2160 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2161 iflib_admin_intr_deferred(ctx); 2162 STATE_UNLOCK(ctx); 2163 } 2164 2165 static void 2166 iflib_init_locked(if_ctx_t ctx) 2167 { 2168 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2169 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2170 if_t ifp = ctx->ifc_ifp; 2171 iflib_fl_t fl; 2172 iflib_txq_t txq; 2173 iflib_rxq_t rxq; 2174 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2175 2176 2177 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2178 IFDI_INTR_DISABLE(ctx); 2179 2180 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2181 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2182 /* Set hardware offload abilities */ 2183 if_clearhwassist(ifp); 2184 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2185 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2186 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2187 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2188 if (if_getcapenable(ifp) & IFCAP_TSO4) 2189 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2190 if (if_getcapenable(ifp) & IFCAP_TSO6) 2191 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2192 2193 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2194 CALLOUT_LOCK(txq); 2195 callout_stop(&txq->ift_timer); 2196 CALLOUT_UNLOCK(txq); 2197 iflib_netmap_txq_init(ctx, txq); 2198 } 2199 #ifdef INVARIANTS 2200 i = if_getdrvflags(ifp); 2201 #endif 2202 IFDI_INIT(ctx); 2203 MPASS(if_getdrvflags(ifp) == i); 2204 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2205 /* XXX this should really be done on a per-queue basis */ 2206 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2207 MPASS(rxq->ifr_id == i); 2208 iflib_netmap_rxq_init(ctx, rxq); 2209 continue; 2210 } 2211 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2212 if (iflib_fl_setup(fl)) { 2213 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2214 goto done; 2215 } 2216 } 2217 } 2218 done: 2219 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2220 IFDI_INTR_ENABLE(ctx); 2221 txq = ctx->ifc_txqs; 2222 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2223 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2224 txq->ift_timer.c_cpu); 2225 } 2226 2227 static int 2228 iflib_media_change(if_t ifp) 2229 { 2230 if_ctx_t ctx = if_getsoftc(ifp); 2231 int err; 2232 2233 CTX_LOCK(ctx); 2234 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2235 iflib_init_locked(ctx); 2236 CTX_UNLOCK(ctx); 2237 return (err); 2238 } 2239 2240 static void 2241 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2242 { 2243 if_ctx_t ctx = if_getsoftc(ifp); 2244 2245 CTX_LOCK(ctx); 2246 IFDI_UPDATE_ADMIN_STATUS(ctx); 2247 IFDI_MEDIA_STATUS(ctx, ifmr); 2248 CTX_UNLOCK(ctx); 2249 } 2250 2251 static void 2252 iflib_stop(if_ctx_t ctx) 2253 { 2254 iflib_txq_t txq = ctx->ifc_txqs; 2255 iflib_rxq_t rxq = ctx->ifc_rxqs; 2256 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2257 iflib_dma_info_t di; 2258 iflib_fl_t fl; 2259 int i, j; 2260 2261 /* Tell the stack that the interface is no longer active */ 2262 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2263 2264 IFDI_INTR_DISABLE(ctx); 2265 DELAY(1000); 2266 IFDI_STOP(ctx); 2267 DELAY(1000); 2268 2269 iflib_debug_reset(); 2270 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2271 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2272 /* make sure all transmitters have completed before proceeding XXX */ 2273 2274 CALLOUT_LOCK(txq); 2275 callout_stop(&txq->ift_timer); 2276 CALLOUT_UNLOCK(txq); 2277 2278 /* clean any enqueued buffers */ 2279 iflib_ifmp_purge(txq); 2280 /* Free any existing tx buffers. */ 2281 for (j = 0; j < txq->ift_size; j++) { 2282 iflib_txsd_free(ctx, txq, j); 2283 } 2284 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2285 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2286 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2287 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2288 txq->ift_pullups = 0; 2289 ifmp_ring_reset_stats(txq->ift_br); 2290 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2291 bzero((void *)di->idi_vaddr, di->idi_size); 2292 } 2293 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2294 /* make sure all transmitters have completed before proceeding XXX */ 2295 2296 for (j = 0, di = rxq->ifr_ifdi; j < rxq->ifr_nfl; j++, di++) 2297 bzero((void *)di->idi_vaddr, di->idi_size); 2298 /* also resets the free lists pidx/cidx */ 2299 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2300 iflib_fl_bufs_free(fl); 2301 } 2302 } 2303 2304 static inline caddr_t 2305 calc_next_rxd(iflib_fl_t fl, int cidx) 2306 { 2307 qidx_t size; 2308 int nrxd; 2309 caddr_t start, end, cur, next; 2310 2311 nrxd = fl->ifl_size; 2312 size = fl->ifl_rxd_size; 2313 start = fl->ifl_ifdi->idi_vaddr; 2314 2315 if (__predict_false(size == 0)) 2316 return (start); 2317 cur = start + size*cidx; 2318 end = start + size*nrxd; 2319 next = CACHE_PTR_NEXT(cur); 2320 return (next < end ? next : start); 2321 } 2322 2323 static inline void 2324 prefetch_pkts(iflib_fl_t fl, int cidx) 2325 { 2326 int nextptr; 2327 int nrxd = fl->ifl_size; 2328 caddr_t next_rxd; 2329 2330 2331 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2332 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2333 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2334 next_rxd = calc_next_rxd(fl, cidx); 2335 prefetch(next_rxd); 2336 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2337 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2338 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2339 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2340 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2341 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2342 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2343 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2344 } 2345 2346 static void 2347 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2348 { 2349 int flid, cidx; 2350 bus_dmamap_t map; 2351 iflib_fl_t fl; 2352 iflib_dma_info_t di; 2353 int next; 2354 2355 map = NULL; 2356 flid = irf->irf_flid; 2357 cidx = irf->irf_idx; 2358 fl = &rxq->ifr_fl[flid]; 2359 sd->ifsd_fl = fl; 2360 sd->ifsd_cidx = cidx; 2361 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2362 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2363 fl->ifl_credits--; 2364 #if MEMORY_LOGGING 2365 fl->ifl_m_dequeued++; 2366 #endif 2367 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2368 prefetch_pkts(fl, cidx); 2369 if (fl->ifl_sds.ifsd_map != NULL) { 2370 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2371 prefetch(&fl->ifl_sds.ifsd_map[next]); 2372 map = fl->ifl_sds.ifsd_map[cidx]; 2373 di = fl->ifl_ifdi; 2374 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2375 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2376 bus_dmamap_sync(di->idi_tag, di->idi_map, 2377 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2378 2379 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2380 MPASS(fl->ifl_cidx == cidx); 2381 if (unload) 2382 bus_dmamap_unload(fl->ifl_desc_tag, map); 2383 } 2384 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2385 if (__predict_false(fl->ifl_cidx == 0)) 2386 fl->ifl_gen = 0; 2387 if (map != NULL) 2388 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2389 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2390 bit_clear(fl->ifl_rx_bitmap, cidx); 2391 } 2392 2393 static struct mbuf * 2394 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2395 { 2396 int i, padlen , flags; 2397 struct mbuf *m, *mh, *mt; 2398 caddr_t cl; 2399 2400 i = 0; 2401 mh = NULL; 2402 do { 2403 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2404 2405 MPASS(*sd->ifsd_cl != NULL); 2406 MPASS(*sd->ifsd_m != NULL); 2407 2408 /* Don't include zero-length frags */ 2409 if (ri->iri_frags[i].irf_len == 0) { 2410 /* XXX we can save the cluster here, but not the mbuf */ 2411 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2412 m_free(*sd->ifsd_m); 2413 *sd->ifsd_m = NULL; 2414 continue; 2415 } 2416 m = *sd->ifsd_m; 2417 *sd->ifsd_m = NULL; 2418 if (mh == NULL) { 2419 flags = M_PKTHDR|M_EXT; 2420 mh = mt = m; 2421 padlen = ri->iri_pad; 2422 } else { 2423 flags = M_EXT; 2424 mt->m_next = m; 2425 mt = m; 2426 /* assuming padding is only on the first fragment */ 2427 padlen = 0; 2428 } 2429 cl = *sd->ifsd_cl; 2430 *sd->ifsd_cl = NULL; 2431 2432 /* Can these two be made one ? */ 2433 m_init(m, M_NOWAIT, MT_DATA, flags); 2434 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2435 /* 2436 * These must follow m_init and m_cljset 2437 */ 2438 m->m_data += padlen; 2439 ri->iri_len -= padlen; 2440 m->m_len = ri->iri_frags[i].irf_len; 2441 } while (++i < ri->iri_nfrags); 2442 2443 return (mh); 2444 } 2445 2446 /* 2447 * Process one software descriptor 2448 */ 2449 static struct mbuf * 2450 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2451 { 2452 struct if_rxsd sd; 2453 struct mbuf *m; 2454 2455 /* should I merge this back in now that the two paths are basically duplicated? */ 2456 if (ri->iri_nfrags == 1 && 2457 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2458 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2459 m = *sd.ifsd_m; 2460 *sd.ifsd_m = NULL; 2461 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2462 #ifndef __NO_STRICT_ALIGNMENT 2463 if (!IP_ALIGNED(m)) 2464 m->m_data += 2; 2465 #endif 2466 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2467 m->m_len = ri->iri_frags[0].irf_len; 2468 } else { 2469 m = assemble_segments(rxq, ri, &sd); 2470 } 2471 m->m_pkthdr.len = ri->iri_len; 2472 m->m_pkthdr.rcvif = ri->iri_ifp; 2473 m->m_flags |= ri->iri_flags; 2474 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2475 m->m_pkthdr.flowid = ri->iri_flowid; 2476 M_HASHTYPE_SET(m, ri->iri_rsstype); 2477 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2478 m->m_pkthdr.csum_data = ri->iri_csum_data; 2479 return (m); 2480 } 2481 2482 #if defined(INET6) || defined(INET) 2483 static void 2484 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2485 { 2486 CURVNET_SET(lc->ifp->if_vnet); 2487 #if defined(INET6) 2488 *v6 = VNET(ip6_forwarding); 2489 #endif 2490 #if defined(INET) 2491 *v4 = VNET(ipforwarding); 2492 #endif 2493 CURVNET_RESTORE(); 2494 } 2495 2496 /* 2497 * Returns true if it's possible this packet could be LROed. 2498 * if it returns false, it is guaranteed that tcp_lro_rx() 2499 * would not return zero. 2500 */ 2501 static bool 2502 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2503 { 2504 struct ether_header *eh; 2505 uint16_t eh_type; 2506 2507 eh = mtod(m, struct ether_header *); 2508 eh_type = ntohs(eh->ether_type); 2509 switch (eh_type) { 2510 #if defined(INET6) 2511 case ETHERTYPE_IPV6: 2512 return !v6_forwarding; 2513 #endif 2514 #if defined (INET) 2515 case ETHERTYPE_IP: 2516 return !v4_forwarding; 2517 #endif 2518 } 2519 2520 return false; 2521 } 2522 #else 2523 static void 2524 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2525 { 2526 } 2527 #endif 2528 2529 static bool 2530 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2531 { 2532 if_ctx_t ctx = rxq->ifr_ctx; 2533 if_shared_ctx_t sctx = ctx->ifc_sctx; 2534 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2535 int avail, i; 2536 qidx_t *cidxp; 2537 struct if_rxd_info ri; 2538 int err, budget_left, rx_bytes, rx_pkts; 2539 iflib_fl_t fl; 2540 struct ifnet *ifp; 2541 int lro_enabled; 2542 bool lro_possible = false; 2543 bool v4_forwarding, v6_forwarding; 2544 2545 /* 2546 * XXX early demux data packets so that if_input processing only handles 2547 * acks in interrupt context 2548 */ 2549 struct mbuf *m, *mh, *mt, *mf; 2550 2551 ifp = ctx->ifc_ifp; 2552 mh = mt = NULL; 2553 MPASS(budget > 0); 2554 rx_pkts = rx_bytes = 0; 2555 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2556 cidxp = &rxq->ifr_cq_cidx; 2557 else 2558 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2559 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2560 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2561 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2562 DBG_COUNTER_INC(rx_unavail); 2563 return (false); 2564 } 2565 2566 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2567 if (__predict_false(!CTX_ACTIVE(ctx))) { 2568 DBG_COUNTER_INC(rx_ctx_inactive); 2569 break; 2570 } 2571 /* 2572 * Reset client set fields to their default values 2573 */ 2574 rxd_info_zero(&ri); 2575 ri.iri_qsidx = rxq->ifr_id; 2576 ri.iri_cidx = *cidxp; 2577 ri.iri_ifp = ifp; 2578 ri.iri_frags = rxq->ifr_frags; 2579 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2580 2581 if (err) 2582 goto err; 2583 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2584 *cidxp = ri.iri_cidx; 2585 /* Update our consumer index */ 2586 /* XXX NB: shurd - check if this is still safe */ 2587 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2588 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2589 rxq->ifr_cq_gen = 0; 2590 } 2591 /* was this only a completion queue message? */ 2592 if (__predict_false(ri.iri_nfrags == 0)) 2593 continue; 2594 } 2595 MPASS(ri.iri_nfrags != 0); 2596 MPASS(ri.iri_len != 0); 2597 2598 /* will advance the cidx on the corresponding free lists */ 2599 m = iflib_rxd_pkt_get(rxq, &ri); 2600 if (avail == 0 && budget_left) 2601 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2602 2603 if (__predict_false(m == NULL)) { 2604 DBG_COUNTER_INC(rx_mbuf_null); 2605 continue; 2606 } 2607 /* imm_pkt: -- cxgb */ 2608 if (mh == NULL) 2609 mh = mt = m; 2610 else { 2611 mt->m_nextpkt = m; 2612 mt = m; 2613 } 2614 } 2615 /* make sure that we can refill faster than drain */ 2616 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2617 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2618 2619 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2620 if (lro_enabled) 2621 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2622 mt = mf = NULL; 2623 while (mh != NULL) { 2624 m = mh; 2625 mh = mh->m_nextpkt; 2626 m->m_nextpkt = NULL; 2627 #ifndef __NO_STRICT_ALIGNMENT 2628 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2629 continue; 2630 #endif 2631 rx_bytes += m->m_pkthdr.len; 2632 rx_pkts++; 2633 #if defined(INET6) || defined(INET) 2634 if (lro_enabled) { 2635 if (!lro_possible) { 2636 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2637 if (lro_possible && mf != NULL) { 2638 ifp->if_input(ifp, mf); 2639 DBG_COUNTER_INC(rx_if_input); 2640 mt = mf = NULL; 2641 } 2642 } 2643 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2644 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2645 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2646 continue; 2647 } 2648 } 2649 #endif 2650 if (lro_possible) { 2651 ifp->if_input(ifp, m); 2652 DBG_COUNTER_INC(rx_if_input); 2653 continue; 2654 } 2655 2656 if (mf == NULL) 2657 mf = m; 2658 if (mt != NULL) 2659 mt->m_nextpkt = m; 2660 mt = m; 2661 } 2662 if (mf != NULL) { 2663 ifp->if_input(ifp, mf); 2664 DBG_COUNTER_INC(rx_if_input); 2665 } 2666 2667 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2668 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2669 2670 /* 2671 * Flush any outstanding LRO work 2672 */ 2673 #if defined(INET6) || defined(INET) 2674 tcp_lro_flush_all(&rxq->ifr_lc); 2675 #endif 2676 if (avail) 2677 return true; 2678 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2679 err: 2680 STATE_LOCK(ctx); 2681 ctx->ifc_flags |= IFC_DO_RESET; 2682 iflib_admin_intr_deferred(ctx); 2683 STATE_UNLOCK(ctx); 2684 return (false); 2685 } 2686 2687 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2688 static inline qidx_t 2689 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2690 { 2691 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2692 qidx_t minthresh = txq->ift_size / 8; 2693 if (in_use > 4*minthresh) 2694 return (notify_count); 2695 if (in_use > 2*minthresh) 2696 return (notify_count >> 1); 2697 if (in_use > minthresh) 2698 return (notify_count >> 3); 2699 return (0); 2700 } 2701 2702 static inline qidx_t 2703 txq_max_rs_deferred(iflib_txq_t txq) 2704 { 2705 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2706 qidx_t minthresh = txq->ift_size / 8; 2707 if (txq->ift_in_use > 4*minthresh) 2708 return (notify_count); 2709 if (txq->ift_in_use > 2*minthresh) 2710 return (notify_count >> 1); 2711 if (txq->ift_in_use > minthresh) 2712 return (notify_count >> 2); 2713 return (2); 2714 } 2715 2716 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2717 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2718 2719 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2720 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2721 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2722 2723 /* forward compatibility for cxgb */ 2724 #define FIRST_QSET(ctx) 0 2725 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2726 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2727 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2728 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2729 2730 /* XXX we should be setting this to something other than zero */ 2731 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2732 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2733 2734 static inline bool 2735 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2736 { 2737 qidx_t dbval, max; 2738 bool rang; 2739 2740 rang = false; 2741 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2742 if (ring || txq->ift_db_pending >= max) { 2743 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2744 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2745 txq->ift_db_pending = txq->ift_npending = 0; 2746 rang = true; 2747 } 2748 return (rang); 2749 } 2750 2751 #ifdef PKT_DEBUG 2752 static void 2753 print_pkt(if_pkt_info_t pi) 2754 { 2755 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2756 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2757 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2758 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2759 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2760 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2761 } 2762 #endif 2763 2764 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2765 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2766 2767 static int 2768 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2769 { 2770 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2771 struct ether_vlan_header *eh; 2772 struct mbuf *m, *n; 2773 2774 n = m = *mp; 2775 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2776 M_WRITABLE(m) == 0) { 2777 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2778 return (ENOMEM); 2779 } else { 2780 m_freem(*mp); 2781 n = *mp = m; 2782 } 2783 } 2784 2785 /* 2786 * Determine where frame payload starts. 2787 * Jump over vlan headers if already present, 2788 * helpful for QinQ too. 2789 */ 2790 if (__predict_false(m->m_len < sizeof(*eh))) { 2791 txq->ift_pullups++; 2792 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2793 return (ENOMEM); 2794 } 2795 eh = mtod(m, struct ether_vlan_header *); 2796 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2797 pi->ipi_etype = ntohs(eh->evl_proto); 2798 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2799 } else { 2800 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2801 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2802 } 2803 2804 switch (pi->ipi_etype) { 2805 #ifdef INET 2806 case ETHERTYPE_IP: 2807 { 2808 struct ip *ip = NULL; 2809 struct tcphdr *th = NULL; 2810 int minthlen; 2811 2812 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2813 if (__predict_false(m->m_len < minthlen)) { 2814 /* 2815 * if this code bloat is causing too much of a hit 2816 * move it to a separate function and mark it noinline 2817 */ 2818 if (m->m_len == pi->ipi_ehdrlen) { 2819 n = m->m_next; 2820 MPASS(n); 2821 if (n->m_len >= sizeof(*ip)) { 2822 ip = (struct ip *)n->m_data; 2823 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2824 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2825 } else { 2826 txq->ift_pullups++; 2827 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2828 return (ENOMEM); 2829 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2830 } 2831 } else { 2832 txq->ift_pullups++; 2833 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2834 return (ENOMEM); 2835 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2836 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2837 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2838 } 2839 } else { 2840 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2841 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2842 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2843 } 2844 pi->ipi_ip_hlen = ip->ip_hl << 2; 2845 pi->ipi_ipproto = ip->ip_p; 2846 pi->ipi_flags |= IPI_TX_IPV4; 2847 2848 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 2849 ip->ip_sum = 0; 2850 2851 if (IS_TSO4(pi)) { 2852 if (pi->ipi_ipproto == IPPROTO_TCP) { 2853 if (__predict_false(th == NULL)) { 2854 txq->ift_pullups++; 2855 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2856 return (ENOMEM); 2857 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2858 } 2859 pi->ipi_tcp_hflags = th->th_flags; 2860 pi->ipi_tcp_hlen = th->th_off << 2; 2861 pi->ipi_tcp_seq = th->th_seq; 2862 } 2863 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2864 return (ENXIO); 2865 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2866 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2867 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2868 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2869 ip->ip_sum = 0; 2870 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2871 } 2872 } 2873 break; 2874 } 2875 #endif 2876 #ifdef INET6 2877 case ETHERTYPE_IPV6: 2878 { 2879 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2880 struct tcphdr *th; 2881 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2882 2883 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2884 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2885 return (ENOMEM); 2886 } 2887 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2888 2889 /* XXX-BZ this will go badly in case of ext hdrs. */ 2890 pi->ipi_ipproto = ip6->ip6_nxt; 2891 pi->ipi_flags |= IPI_TX_IPV6; 2892 2893 if (IS_TSO6(pi)) { 2894 if (pi->ipi_ipproto == IPPROTO_TCP) { 2895 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2896 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2897 return (ENOMEM); 2898 } 2899 pi->ipi_tcp_hflags = th->th_flags; 2900 pi->ipi_tcp_hlen = th->th_off << 2; 2901 } 2902 2903 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2904 return (ENXIO); 2905 /* 2906 * The corresponding flag is set by the stack in the IPv4 2907 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 2908 * So, set it here because the rest of the flow requires it. 2909 */ 2910 pi->ipi_csum_flags |= CSUM_TCP_IPV6; 2911 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2912 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2913 } 2914 break; 2915 } 2916 #endif 2917 default: 2918 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2919 pi->ipi_ip_hlen = 0; 2920 break; 2921 } 2922 *mp = m; 2923 2924 return (0); 2925 } 2926 2927 static __noinline struct mbuf * 2928 collapse_pkthdr(struct mbuf *m0) 2929 { 2930 struct mbuf *m, *m_next, *tmp; 2931 2932 m = m0; 2933 m_next = m->m_next; 2934 while (m_next != NULL && m_next->m_len == 0) { 2935 m = m_next; 2936 m->m_next = NULL; 2937 m_free(m); 2938 m_next = m_next->m_next; 2939 } 2940 m = m0; 2941 m->m_next = m_next; 2942 if ((m_next->m_flags & M_EXT) == 0) { 2943 m = m_defrag(m, M_NOWAIT); 2944 } else { 2945 tmp = m_next->m_next; 2946 memcpy(m_next, m, MPKTHSIZE); 2947 m = m_next; 2948 m->m_next = tmp; 2949 } 2950 return (m); 2951 } 2952 2953 /* 2954 * If dodgy hardware rejects the scatter gather chain we've handed it 2955 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 2956 * m_defrag'd mbufs 2957 */ 2958 static __noinline struct mbuf * 2959 iflib_remove_mbuf(iflib_txq_t txq) 2960 { 2961 int ntxd, i, pidx; 2962 struct mbuf *m, *mh, **ifsd_m; 2963 2964 pidx = txq->ift_pidx; 2965 ifsd_m = txq->ift_sds.ifsd_m; 2966 ntxd = txq->ift_size; 2967 mh = m = ifsd_m[pidx]; 2968 ifsd_m[pidx] = NULL; 2969 #if MEMORY_LOGGING 2970 txq->ift_dequeued++; 2971 #endif 2972 i = 1; 2973 2974 while (m) { 2975 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 2976 #if MEMORY_LOGGING 2977 txq->ift_dequeued++; 2978 #endif 2979 m = m->m_next; 2980 i++; 2981 } 2982 return (mh); 2983 } 2984 2985 static int 2986 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 2987 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 2988 int max_segs, int flags) 2989 { 2990 if_ctx_t ctx; 2991 if_shared_ctx_t sctx; 2992 if_softc_ctx_t scctx; 2993 int i, next, pidx, err, ntxd, count; 2994 struct mbuf *m, *tmp, **ifsd_m; 2995 2996 m = *m0; 2997 2998 /* 2999 * Please don't ever do this 3000 */ 3001 if (__predict_false(m->m_len == 0)) 3002 *m0 = m = collapse_pkthdr(m); 3003 3004 ctx = txq->ift_ctx; 3005 sctx = ctx->ifc_sctx; 3006 scctx = &ctx->ifc_softc_ctx; 3007 ifsd_m = txq->ift_sds.ifsd_m; 3008 ntxd = txq->ift_size; 3009 pidx = txq->ift_pidx; 3010 if (map != NULL) { 3011 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 3012 3013 err = bus_dmamap_load_mbuf_sg(tag, map, 3014 *m0, segs, nsegs, BUS_DMA_NOWAIT); 3015 if (err) 3016 return (err); 3017 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 3018 count = 0; 3019 m = *m0; 3020 do { 3021 if (__predict_false(m->m_len <= 0)) { 3022 tmp = m; 3023 m = m->m_next; 3024 tmp->m_next = NULL; 3025 m_free(tmp); 3026 continue; 3027 } 3028 m = m->m_next; 3029 count++; 3030 } while (m != NULL); 3031 if (count > *nsegs) { 3032 ifsd_m[pidx] = *m0; 3033 ifsd_m[pidx]->m_flags |= M_TOOBIG; 3034 return (0); 3035 } 3036 m = *m0; 3037 count = 0; 3038 do { 3039 next = (pidx + count) & (ntxd-1); 3040 MPASS(ifsd_m[next] == NULL); 3041 ifsd_m[next] = m; 3042 count++; 3043 tmp = m; 3044 m = m->m_next; 3045 } while (m != NULL); 3046 } else { 3047 int buflen, sgsize, maxsegsz, max_sgsize; 3048 vm_offset_t vaddr; 3049 vm_paddr_t curaddr; 3050 3051 count = i = 0; 3052 m = *m0; 3053 if (m->m_pkthdr.csum_flags & CSUM_TSO) 3054 maxsegsz = scctx->isc_tx_tso_segsize_max; 3055 else 3056 maxsegsz = sctx->isc_tx_maxsegsize; 3057 3058 do { 3059 if (__predict_false(m->m_len <= 0)) { 3060 tmp = m; 3061 m = m->m_next; 3062 tmp->m_next = NULL; 3063 m_free(tmp); 3064 continue; 3065 } 3066 buflen = m->m_len; 3067 vaddr = (vm_offset_t)m->m_data; 3068 /* 3069 * see if we can't be smarter about physically 3070 * contiguous mappings 3071 */ 3072 next = (pidx + count) & (ntxd-1); 3073 MPASS(ifsd_m[next] == NULL); 3074 #if MEMORY_LOGGING 3075 txq->ift_enqueued++; 3076 #endif 3077 ifsd_m[next] = m; 3078 while (buflen > 0) { 3079 if (i >= max_segs) 3080 goto err; 3081 max_sgsize = MIN(buflen, maxsegsz); 3082 curaddr = pmap_kextract(vaddr); 3083 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 3084 sgsize = MIN(sgsize, max_sgsize); 3085 segs[i].ds_addr = curaddr; 3086 segs[i].ds_len = sgsize; 3087 vaddr += sgsize; 3088 buflen -= sgsize; 3089 i++; 3090 } 3091 count++; 3092 tmp = m; 3093 m = m->m_next; 3094 } while (m != NULL); 3095 *nsegs = i; 3096 } 3097 return (0); 3098 err: 3099 *m0 = iflib_remove_mbuf(txq); 3100 return (EFBIG); 3101 } 3102 3103 static inline caddr_t 3104 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3105 { 3106 qidx_t size; 3107 int ntxd; 3108 caddr_t start, end, cur, next; 3109 3110 ntxd = txq->ift_size; 3111 size = txq->ift_txd_size[qid]; 3112 start = txq->ift_ifdi[qid].idi_vaddr; 3113 3114 if (__predict_false(size == 0)) 3115 return (start); 3116 cur = start + size*cidx; 3117 end = start + size*ntxd; 3118 next = CACHE_PTR_NEXT(cur); 3119 return (next < end ? next : start); 3120 } 3121 3122 /* 3123 * Pad an mbuf to ensure a minimum ethernet frame size. 3124 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3125 */ 3126 static __noinline int 3127 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3128 { 3129 /* 3130 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3131 * and ARP message is the smallest common payload I can think of 3132 */ 3133 static char pad[18]; /* just zeros */ 3134 int n; 3135 struct mbuf *new_head; 3136 3137 if (!M_WRITABLE(*m_head)) { 3138 new_head = m_dup(*m_head, M_NOWAIT); 3139 if (new_head == NULL) { 3140 m_freem(*m_head); 3141 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3142 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3143 return ENOMEM; 3144 } 3145 m_freem(*m_head); 3146 *m_head = new_head; 3147 } 3148 3149 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3150 n > 0; n -= sizeof(pad)) 3151 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3152 break; 3153 3154 if (n > 0) { 3155 m_freem(*m_head); 3156 device_printf(dev, "cannot pad short frame\n"); 3157 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3158 return (ENOBUFS); 3159 } 3160 3161 return 0; 3162 } 3163 3164 static int 3165 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3166 { 3167 if_ctx_t ctx; 3168 if_shared_ctx_t sctx; 3169 if_softc_ctx_t scctx; 3170 bus_dma_segment_t *segs; 3171 struct mbuf *m_head; 3172 void *next_txd; 3173 bus_dmamap_t map; 3174 struct if_pkt_info pi; 3175 int remap = 0; 3176 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3177 bus_dma_tag_t desc_tag; 3178 3179 segs = txq->ift_segs; 3180 ctx = txq->ift_ctx; 3181 sctx = ctx->ifc_sctx; 3182 scctx = &ctx->ifc_softc_ctx; 3183 segs = txq->ift_segs; 3184 ntxd = txq->ift_size; 3185 m_head = *m_headp; 3186 map = NULL; 3187 3188 /* 3189 * If we're doing TSO the next descriptor to clean may be quite far ahead 3190 */ 3191 cidx = txq->ift_cidx; 3192 pidx = txq->ift_pidx; 3193 if (ctx->ifc_flags & IFC_PREFETCH) { 3194 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3195 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3196 next_txd = calc_next_txd(txq, cidx, 0); 3197 prefetch(next_txd); 3198 } 3199 3200 /* prefetch the next cache line of mbuf pointers and flags */ 3201 prefetch(&txq->ift_sds.ifsd_m[next]); 3202 if (txq->ift_sds.ifsd_map != NULL) { 3203 prefetch(&txq->ift_sds.ifsd_map[next]); 3204 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3205 prefetch(&txq->ift_sds.ifsd_flags[next]); 3206 } 3207 } else if (txq->ift_sds.ifsd_map != NULL) 3208 map = txq->ift_sds.ifsd_map[pidx]; 3209 3210 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3211 desc_tag = txq->ift_tso_desc_tag; 3212 max_segs = scctx->isc_tx_tso_segments_max; 3213 } else { 3214 desc_tag = txq->ift_desc_tag; 3215 max_segs = scctx->isc_tx_nsegments; 3216 } 3217 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3218 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3219 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3220 if (err) 3221 return err; 3222 } 3223 m_head = *m_headp; 3224 3225 pkt_info_zero(&pi); 3226 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3227 pi.ipi_pidx = pidx; 3228 pi.ipi_qsidx = txq->ift_id; 3229 pi.ipi_len = m_head->m_pkthdr.len; 3230 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3231 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3232 3233 /* deliberate bitwise OR to make one condition */ 3234 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3235 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3236 return (err); 3237 m_head = *m_headp; 3238 } 3239 3240 retry: 3241 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3242 defrag: 3243 if (__predict_false(err)) { 3244 switch (err) { 3245 case EFBIG: 3246 /* try collapse once and defrag once */ 3247 if (remap == 0) 3248 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3249 if (remap == 1) 3250 m_head = m_defrag(*m_headp, M_NOWAIT); 3251 remap++; 3252 if (__predict_false(m_head == NULL)) 3253 goto defrag_failed; 3254 txq->ift_mbuf_defrag++; 3255 *m_headp = m_head; 3256 goto retry; 3257 break; 3258 case ENOMEM: 3259 txq->ift_no_tx_dma_setup++; 3260 break; 3261 default: 3262 txq->ift_no_tx_dma_setup++; 3263 m_freem(*m_headp); 3264 DBG_COUNTER_INC(tx_frees); 3265 *m_headp = NULL; 3266 break; 3267 } 3268 txq->ift_map_failed++; 3269 DBG_COUNTER_INC(encap_load_mbuf_fail); 3270 return (err); 3271 } 3272 3273 /* 3274 * XXX assumes a 1 to 1 relationship between segments and 3275 * descriptors - this does not hold true on all drivers, e.g. 3276 * cxgb 3277 */ 3278 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3279 txq->ift_no_desc_avail++; 3280 if (map != NULL) 3281 bus_dmamap_unload(desc_tag, map); 3282 DBG_COUNTER_INC(encap_txq_avail_fail); 3283 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3284 GROUPTASK_ENQUEUE(&txq->ift_task); 3285 return (ENOBUFS); 3286 } 3287 /* 3288 * On Intel cards we can greatly reduce the number of TX interrupts 3289 * we see by only setting report status on every Nth descriptor. 3290 * However, this also means that the driver will need to keep track 3291 * of the descriptors that RS was set on to check them for the DD bit. 3292 */ 3293 txq->ift_rs_pending += nsegs + 1; 3294 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3295 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) { 3296 pi.ipi_flags |= IPI_TX_INTR; 3297 txq->ift_rs_pending = 0; 3298 } 3299 3300 pi.ipi_segs = segs; 3301 pi.ipi_nsegs = nsegs; 3302 3303 MPASS(pidx >= 0 && pidx < txq->ift_size); 3304 #ifdef PKT_DEBUG 3305 print_pkt(&pi); 3306 #endif 3307 if (map != NULL) 3308 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3309 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3310 if (map != NULL) 3311 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3312 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3313 DBG_COUNTER_INC(tx_encap); 3314 MPASS(pi.ipi_new_pidx < txq->ift_size); 3315 3316 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3317 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3318 ndesc += txq->ift_size; 3319 txq->ift_gen = 1; 3320 } 3321 /* 3322 * drivers can need as many as 3323 * two sentinels 3324 */ 3325 MPASS(ndesc <= pi.ipi_nsegs + 2); 3326 MPASS(pi.ipi_new_pidx != pidx); 3327 MPASS(ndesc > 0); 3328 txq->ift_in_use += ndesc; 3329 3330 /* 3331 * We update the last software descriptor again here because there may 3332 * be a sentinel and/or there may be more mbufs than segments 3333 */ 3334 txq->ift_pidx = pi.ipi_new_pidx; 3335 txq->ift_npending += pi.ipi_ndescs; 3336 } else if (__predict_false(err == EFBIG && remap < 2)) { 3337 *m_headp = m_head = iflib_remove_mbuf(txq); 3338 remap = 1; 3339 txq->ift_txd_encap_efbig++; 3340 goto defrag; 3341 } else 3342 DBG_COUNTER_INC(encap_txd_encap_fail); 3343 return (err); 3344 3345 defrag_failed: 3346 txq->ift_mbuf_defrag_failed++; 3347 txq->ift_map_failed++; 3348 m_freem(*m_headp); 3349 DBG_COUNTER_INC(tx_frees); 3350 *m_headp = NULL; 3351 return (ENOMEM); 3352 } 3353 3354 static void 3355 iflib_tx_desc_free(iflib_txq_t txq, int n) 3356 { 3357 int hasmap; 3358 uint32_t qsize, cidx, mask, gen; 3359 struct mbuf *m, **ifsd_m; 3360 uint8_t *ifsd_flags; 3361 bus_dmamap_t *ifsd_map; 3362 bool do_prefetch; 3363 3364 cidx = txq->ift_cidx; 3365 gen = txq->ift_gen; 3366 qsize = txq->ift_size; 3367 mask = qsize-1; 3368 hasmap = txq->ift_sds.ifsd_map != NULL; 3369 ifsd_flags = txq->ift_sds.ifsd_flags; 3370 ifsd_m = txq->ift_sds.ifsd_m; 3371 ifsd_map = txq->ift_sds.ifsd_map; 3372 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3373 3374 while (n--) { 3375 if (do_prefetch) { 3376 prefetch(ifsd_m[(cidx + 3) & mask]); 3377 prefetch(ifsd_m[(cidx + 4) & mask]); 3378 } 3379 if (ifsd_m[cidx] != NULL) { 3380 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3381 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3382 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3383 /* 3384 * does it matter if it's not the TSO tag? If so we'll 3385 * have to add the type to flags 3386 */ 3387 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3388 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3389 } 3390 if ((m = ifsd_m[cidx]) != NULL) { 3391 /* XXX we don't support any drivers that batch packets yet */ 3392 MPASS(m->m_nextpkt == NULL); 3393 /* if the number of clusters exceeds the number of segments 3394 * there won't be space on the ring to save a pointer to each 3395 * cluster so we simply free the list here 3396 */ 3397 if (m->m_flags & M_TOOBIG) { 3398 m_freem(m); 3399 } else { 3400 m_free(m); 3401 } 3402 ifsd_m[cidx] = NULL; 3403 #if MEMORY_LOGGING 3404 txq->ift_dequeued++; 3405 #endif 3406 DBG_COUNTER_INC(tx_frees); 3407 } 3408 } 3409 if (__predict_false(++cidx == qsize)) { 3410 cidx = 0; 3411 gen = 0; 3412 } 3413 } 3414 txq->ift_cidx = cidx; 3415 txq->ift_gen = gen; 3416 } 3417 3418 static __inline int 3419 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3420 { 3421 int reclaim; 3422 if_ctx_t ctx = txq->ift_ctx; 3423 3424 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3425 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3426 3427 /* 3428 * Need a rate-limiting check so that this isn't called every time 3429 */ 3430 iflib_tx_credits_update(ctx, txq); 3431 reclaim = DESC_RECLAIMABLE(txq); 3432 3433 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3434 #ifdef INVARIANTS 3435 if (iflib_verbose_debug) { 3436 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3437 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3438 reclaim, thresh); 3439 3440 } 3441 #endif 3442 return (0); 3443 } 3444 iflib_tx_desc_free(txq, reclaim); 3445 txq->ift_cleaned += reclaim; 3446 txq->ift_in_use -= reclaim; 3447 3448 return (reclaim); 3449 } 3450 3451 static struct mbuf ** 3452 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3453 { 3454 int next, size; 3455 struct mbuf **items; 3456 3457 size = r->size; 3458 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3459 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3460 3461 prefetch(items[(cidx + offset) & (size-1)]); 3462 if (remaining > 1) { 3463 prefetch2cachelines(&items[next]); 3464 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3465 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3466 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3467 } 3468 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3469 } 3470 3471 static void 3472 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3473 { 3474 3475 ifmp_ring_check_drainage(txq->ift_br, budget); 3476 } 3477 3478 static uint32_t 3479 iflib_txq_can_drain(struct ifmp_ring *r) 3480 { 3481 iflib_txq_t txq = r->cookie; 3482 if_ctx_t ctx = txq->ift_ctx; 3483 3484 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3485 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3486 } 3487 3488 static uint32_t 3489 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3490 { 3491 iflib_txq_t txq = r->cookie; 3492 if_ctx_t ctx = txq->ift_ctx; 3493 struct ifnet *ifp = ctx->ifc_ifp; 3494 struct mbuf **mp, *m; 3495 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3496 int reclaimed, err, in_use_prev, desc_used; 3497 bool do_prefetch, ring, rang; 3498 3499 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3500 !LINK_ACTIVE(ctx))) { 3501 DBG_COUNTER_INC(txq_drain_notready); 3502 return (0); 3503 } 3504 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3505 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3506 avail = IDXDIFF(pidx, cidx, r->size); 3507 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3508 DBG_COUNTER_INC(txq_drain_flushing); 3509 for (i = 0; i < avail; i++) { 3510 m_free(r->items[(cidx + i) & (r->size-1)]); 3511 r->items[(cidx + i) & (r->size-1)] = NULL; 3512 } 3513 return (avail); 3514 } 3515 3516 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3517 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3518 CALLOUT_LOCK(txq); 3519 callout_stop(&txq->ift_timer); 3520 CALLOUT_UNLOCK(txq); 3521 DBG_COUNTER_INC(txq_drain_oactive); 3522 return (0); 3523 } 3524 if (reclaimed) 3525 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3526 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3527 count = MIN(avail, TX_BATCH_SIZE); 3528 #ifdef INVARIANTS 3529 if (iflib_verbose_debug) 3530 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3531 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3532 #endif 3533 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3534 avail = TXQ_AVAIL(txq); 3535 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3536 int pidx_prev, rem = do_prefetch ? count - i : 0; 3537 3538 mp = _ring_peek_one(r, cidx, i, rem); 3539 MPASS(mp != NULL && *mp != NULL); 3540 if (__predict_false(*mp == (struct mbuf *)txq)) { 3541 consumed++; 3542 reclaimed++; 3543 continue; 3544 } 3545 in_use_prev = txq->ift_in_use; 3546 pidx_prev = txq->ift_pidx; 3547 err = iflib_encap(txq, mp); 3548 if (__predict_false(err)) { 3549 DBG_COUNTER_INC(txq_drain_encapfail); 3550 /* no room - bail out */ 3551 if (err == ENOBUFS) 3552 break; 3553 consumed++; 3554 DBG_COUNTER_INC(txq_drain_encapfail); 3555 /* we can't send this packet - skip it */ 3556 continue; 3557 } 3558 consumed++; 3559 pkt_sent++; 3560 m = *mp; 3561 DBG_COUNTER_INC(tx_sent); 3562 bytes_sent += m->m_pkthdr.len; 3563 mcast_sent += !!(m->m_flags & M_MCAST); 3564 avail = TXQ_AVAIL(txq); 3565 3566 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3567 desc_used += (txq->ift_in_use - in_use_prev); 3568 ETHER_BPF_MTAP(ifp, m); 3569 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3570 break; 3571 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3572 } 3573 3574 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3575 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3576 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3577 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3578 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3579 if (mcast_sent) 3580 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3581 #ifdef INVARIANTS 3582 if (iflib_verbose_debug) 3583 printf("consumed=%d\n", consumed); 3584 #endif 3585 return (consumed); 3586 } 3587 3588 static uint32_t 3589 iflib_txq_drain_always(struct ifmp_ring *r) 3590 { 3591 return (1); 3592 } 3593 3594 static uint32_t 3595 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3596 { 3597 int i, avail; 3598 struct mbuf **mp; 3599 iflib_txq_t txq; 3600 3601 txq = r->cookie; 3602 3603 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3604 CALLOUT_LOCK(txq); 3605 callout_stop(&txq->ift_timer); 3606 CALLOUT_UNLOCK(txq); 3607 3608 avail = IDXDIFF(pidx, cidx, r->size); 3609 for (i = 0; i < avail; i++) { 3610 mp = _ring_peek_one(r, cidx, i, avail - i); 3611 if (__predict_false(*mp == (struct mbuf *)txq)) 3612 continue; 3613 m_freem(*mp); 3614 } 3615 MPASS(ifmp_ring_is_stalled(r) == 0); 3616 return (avail); 3617 } 3618 3619 static void 3620 iflib_ifmp_purge(iflib_txq_t txq) 3621 { 3622 struct ifmp_ring *r; 3623 3624 r = txq->ift_br; 3625 r->drain = iflib_txq_drain_free; 3626 r->can_drain = iflib_txq_drain_always; 3627 3628 ifmp_ring_check_drainage(r, r->size); 3629 3630 r->drain = iflib_txq_drain; 3631 r->can_drain = iflib_txq_can_drain; 3632 } 3633 3634 static void 3635 _task_fn_tx(void *context) 3636 { 3637 iflib_txq_t txq = context; 3638 if_ctx_t ctx = txq->ift_ctx; 3639 struct ifnet *ifp = ctx->ifc_ifp; 3640 int rc; 3641 3642 #ifdef IFLIB_DIAGNOSTICS 3643 txq->ift_cpu_exec_count[curcpu]++; 3644 #endif 3645 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3646 return; 3647 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3648 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3649 netmap_tx_irq(ifp, txq->ift_id); 3650 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3651 return; 3652 } 3653 if (txq->ift_db_pending) 3654 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); 3655 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3656 if (ctx->ifc_flags & IFC_LEGACY) 3657 IFDI_INTR_ENABLE(ctx); 3658 else { 3659 rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3660 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3661 } 3662 } 3663 3664 static void 3665 _task_fn_rx(void *context) 3666 { 3667 iflib_rxq_t rxq = context; 3668 if_ctx_t ctx = rxq->ifr_ctx; 3669 bool more; 3670 int rc; 3671 uint16_t budget; 3672 3673 #ifdef IFLIB_DIAGNOSTICS 3674 rxq->ifr_cpu_exec_count[curcpu]++; 3675 #endif 3676 DBG_COUNTER_INC(task_fn_rxs); 3677 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3678 return; 3679 more = true; 3680 #ifdef DEV_NETMAP 3681 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3682 u_int work = 0; 3683 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3684 more = false; 3685 } 3686 } 3687 #endif 3688 budget = ctx->ifc_sysctl_rx_budget; 3689 if (budget == 0) 3690 budget = 16; /* XXX */ 3691 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3692 if (ctx->ifc_flags & IFC_LEGACY) 3693 IFDI_INTR_ENABLE(ctx); 3694 else { 3695 DBG_COUNTER_INC(rx_intr_enables); 3696 rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3697 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3698 } 3699 } 3700 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3701 return; 3702 if (more) 3703 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3704 } 3705 3706 static void 3707 _task_fn_admin(void *context) 3708 { 3709 if_ctx_t ctx = context; 3710 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3711 iflib_txq_t txq; 3712 int i; 3713 bool oactive, running, do_reset, do_watchdog; 3714 3715 STATE_LOCK(ctx); 3716 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3717 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3718 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3719 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3720 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3721 STATE_UNLOCK(ctx); 3722 3723 if (!running & !oactive) 3724 return; 3725 3726 CTX_LOCK(ctx); 3727 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3728 CALLOUT_LOCK(txq); 3729 callout_stop(&txq->ift_timer); 3730 CALLOUT_UNLOCK(txq); 3731 } 3732 if (do_watchdog) { 3733 ctx->ifc_watchdog_events++; 3734 IFDI_WATCHDOG_RESET(ctx); 3735 } 3736 IFDI_UPDATE_ADMIN_STATUS(ctx); 3737 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3738 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 3739 IFDI_LINK_INTR_ENABLE(ctx); 3740 if (do_reset) 3741 iflib_if_init_locked(ctx); 3742 CTX_UNLOCK(ctx); 3743 3744 if (LINK_ACTIVE(ctx) == 0) 3745 return; 3746 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3747 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3748 } 3749 3750 3751 static void 3752 _task_fn_iov(void *context) 3753 { 3754 if_ctx_t ctx = context; 3755 3756 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3757 return; 3758 3759 CTX_LOCK(ctx); 3760 IFDI_VFLR_HANDLE(ctx); 3761 CTX_UNLOCK(ctx); 3762 } 3763 3764 static int 3765 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3766 { 3767 int err; 3768 if_int_delay_info_t info; 3769 if_ctx_t ctx; 3770 3771 info = (if_int_delay_info_t)arg1; 3772 ctx = info->iidi_ctx; 3773 info->iidi_req = req; 3774 info->iidi_oidp = oidp; 3775 CTX_LOCK(ctx); 3776 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3777 CTX_UNLOCK(ctx); 3778 return (err); 3779 } 3780 3781 /********************************************************************* 3782 * 3783 * IFNET FUNCTIONS 3784 * 3785 **********************************************************************/ 3786 3787 static void 3788 iflib_if_init_locked(if_ctx_t ctx) 3789 { 3790 iflib_stop(ctx); 3791 iflib_init_locked(ctx); 3792 } 3793 3794 3795 static void 3796 iflib_if_init(void *arg) 3797 { 3798 if_ctx_t ctx = arg; 3799 3800 CTX_LOCK(ctx); 3801 iflib_if_init_locked(ctx); 3802 CTX_UNLOCK(ctx); 3803 } 3804 3805 static int 3806 iflib_if_transmit(if_t ifp, struct mbuf *m) 3807 { 3808 if_ctx_t ctx = if_getsoftc(ifp); 3809 3810 iflib_txq_t txq; 3811 int err, qidx; 3812 3813 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3814 DBG_COUNTER_INC(tx_frees); 3815 m_freem(m); 3816 return (ENOBUFS); 3817 } 3818 3819 MPASS(m->m_nextpkt == NULL); 3820 qidx = 0; 3821 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3822 qidx = QIDX(ctx, m); 3823 /* 3824 * XXX calculate buf_ring based on flowid (divvy up bits?) 3825 */ 3826 txq = &ctx->ifc_txqs[qidx]; 3827 3828 #ifdef DRIVER_BACKPRESSURE 3829 if (txq->ift_closed) { 3830 while (m != NULL) { 3831 next = m->m_nextpkt; 3832 m->m_nextpkt = NULL; 3833 m_freem(m); 3834 m = next; 3835 } 3836 return (ENOBUFS); 3837 } 3838 #endif 3839 #ifdef notyet 3840 qidx = count = 0; 3841 mp = marr; 3842 next = m; 3843 do { 3844 count++; 3845 next = next->m_nextpkt; 3846 } while (next != NULL); 3847 3848 if (count > nitems(marr)) 3849 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3850 /* XXX check nextpkt */ 3851 m_freem(m); 3852 /* XXX simplify for now */ 3853 DBG_COUNTER_INC(tx_frees); 3854 return (ENOBUFS); 3855 } 3856 for (next = m, i = 0; next != NULL; i++) { 3857 mp[i] = next; 3858 next = next->m_nextpkt; 3859 mp[i]->m_nextpkt = NULL; 3860 } 3861 #endif 3862 DBG_COUNTER_INC(tx_seen); 3863 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); 3864 3865 GROUPTASK_ENQUEUE(&txq->ift_task); 3866 if (err) { 3867 /* support forthcoming later */ 3868 #ifdef DRIVER_BACKPRESSURE 3869 txq->ift_closed = TRUE; 3870 #endif 3871 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3872 m_freem(m); 3873 } 3874 3875 return (err); 3876 } 3877 3878 static void 3879 iflib_if_qflush(if_t ifp) 3880 { 3881 if_ctx_t ctx = if_getsoftc(ifp); 3882 iflib_txq_t txq = ctx->ifc_txqs; 3883 int i; 3884 3885 STATE_LOCK(ctx); 3886 ctx->ifc_flags |= IFC_QFLUSH; 3887 STATE_UNLOCK(ctx); 3888 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3889 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3890 iflib_txq_check_drain(txq, 0); 3891 STATE_LOCK(ctx); 3892 ctx->ifc_flags &= ~IFC_QFLUSH; 3893 STATE_UNLOCK(ctx); 3894 3895 if_qflush(ifp); 3896 } 3897 3898 3899 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3900 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 3901 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 3902 3903 static int 3904 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 3905 { 3906 if_ctx_t ctx = if_getsoftc(ifp); 3907 struct ifreq *ifr = (struct ifreq *)data; 3908 #if defined(INET) || defined(INET6) 3909 struct ifaddr *ifa = (struct ifaddr *)data; 3910 #endif 3911 bool avoid_reset = FALSE; 3912 int err = 0, reinit = 0, bits; 3913 3914 switch (command) { 3915 case SIOCSIFADDR: 3916 #ifdef INET 3917 if (ifa->ifa_addr->sa_family == AF_INET) 3918 avoid_reset = TRUE; 3919 #endif 3920 #ifdef INET6 3921 if (ifa->ifa_addr->sa_family == AF_INET6) 3922 avoid_reset = TRUE; 3923 #endif 3924 /* 3925 ** Calling init results in link renegotiation, 3926 ** so we avoid doing it when possible. 3927 */ 3928 if (avoid_reset) { 3929 if_setflagbits(ifp, IFF_UP,0); 3930 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING)) 3931 reinit = 1; 3932 #ifdef INET 3933 if (!(if_getflags(ifp) & IFF_NOARP)) 3934 arp_ifinit(ifp, ifa); 3935 #endif 3936 } else 3937 err = ether_ioctl(ifp, command, data); 3938 break; 3939 case SIOCSIFMTU: 3940 CTX_LOCK(ctx); 3941 if (ifr->ifr_mtu == if_getmtu(ifp)) { 3942 CTX_UNLOCK(ctx); 3943 break; 3944 } 3945 bits = if_getdrvflags(ifp); 3946 /* stop the driver and free any clusters before proceeding */ 3947 iflib_stop(ctx); 3948 3949 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 3950 STATE_LOCK(ctx); 3951 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 3952 ctx->ifc_flags |= IFC_MULTISEG; 3953 else 3954 ctx->ifc_flags &= ~IFC_MULTISEG; 3955 STATE_UNLOCK(ctx); 3956 err = if_setmtu(ifp, ifr->ifr_mtu); 3957 } 3958 iflib_init_locked(ctx); 3959 STATE_LOCK(ctx); 3960 if_setdrvflags(ifp, bits); 3961 STATE_UNLOCK(ctx); 3962 CTX_UNLOCK(ctx); 3963 break; 3964 case SIOCSIFFLAGS: 3965 CTX_LOCK(ctx); 3966 if (if_getflags(ifp) & IFF_UP) { 3967 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3968 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 3969 (IFF_PROMISC | IFF_ALLMULTI)) { 3970 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 3971 } 3972 } else 3973 reinit = 1; 3974 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3975 iflib_stop(ctx); 3976 } 3977 ctx->ifc_if_flags = if_getflags(ifp); 3978 CTX_UNLOCK(ctx); 3979 break; 3980 case SIOCADDMULTI: 3981 case SIOCDELMULTI: 3982 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3983 CTX_LOCK(ctx); 3984 IFDI_INTR_DISABLE(ctx); 3985 IFDI_MULTI_SET(ctx); 3986 IFDI_INTR_ENABLE(ctx); 3987 CTX_UNLOCK(ctx); 3988 } 3989 break; 3990 case SIOCSIFMEDIA: 3991 CTX_LOCK(ctx); 3992 IFDI_MEDIA_SET(ctx); 3993 CTX_UNLOCK(ctx); 3994 /* falls thru */ 3995 case SIOCGIFMEDIA: 3996 case SIOCGIFXMEDIA: 3997 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 3998 break; 3999 case SIOCGI2C: 4000 { 4001 struct ifi2creq i2c; 4002 4003 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4004 if (err != 0) 4005 break; 4006 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4007 err = EINVAL; 4008 break; 4009 } 4010 if (i2c.len > sizeof(i2c.data)) { 4011 err = EINVAL; 4012 break; 4013 } 4014 4015 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4016 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4017 sizeof(i2c)); 4018 break; 4019 } 4020 case SIOCSIFCAP: 4021 { 4022 int mask, setmask; 4023 4024 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 4025 setmask = 0; 4026 #ifdef TCP_OFFLOAD 4027 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4028 #endif 4029 setmask |= (mask & IFCAP_FLAGS); 4030 4031 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 4032 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4033 if ((mask & IFCAP_WOL) && 4034 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 4035 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 4036 if_vlancap(ifp); 4037 /* 4038 * want to ensure that traffic has stopped before we change any of the flags 4039 */ 4040 if (setmask) { 4041 CTX_LOCK(ctx); 4042 bits = if_getdrvflags(ifp); 4043 if (bits & IFF_DRV_RUNNING) 4044 iflib_stop(ctx); 4045 STATE_LOCK(ctx); 4046 if_togglecapenable(ifp, setmask); 4047 STATE_UNLOCK(ctx); 4048 if (bits & IFF_DRV_RUNNING) 4049 iflib_init_locked(ctx); 4050 STATE_LOCK(ctx); 4051 if_setdrvflags(ifp, bits); 4052 STATE_UNLOCK(ctx); 4053 CTX_UNLOCK(ctx); 4054 } 4055 break; 4056 } 4057 case SIOCGPRIVATE_0: 4058 case SIOCSDRVSPEC: 4059 case SIOCGDRVSPEC: 4060 CTX_LOCK(ctx); 4061 err = IFDI_PRIV_IOCTL(ctx, command, data); 4062 CTX_UNLOCK(ctx); 4063 break; 4064 default: 4065 err = ether_ioctl(ifp, command, data); 4066 break; 4067 } 4068 if (reinit) 4069 iflib_if_init(ctx); 4070 return (err); 4071 } 4072 4073 static uint64_t 4074 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4075 { 4076 if_ctx_t ctx = if_getsoftc(ifp); 4077 4078 return (IFDI_GET_COUNTER(ctx, cnt)); 4079 } 4080 4081 /********************************************************************* 4082 * 4083 * OTHER FUNCTIONS EXPORTED TO THE STACK 4084 * 4085 **********************************************************************/ 4086 4087 static void 4088 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4089 { 4090 if_ctx_t ctx = if_getsoftc(ifp); 4091 4092 if ((void *)ctx != arg) 4093 return; 4094 4095 if ((vtag == 0) || (vtag > 4095)) 4096 return; 4097 4098 CTX_LOCK(ctx); 4099 IFDI_VLAN_REGISTER(ctx, vtag); 4100 /* Re-init to load the changes */ 4101 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4102 iflib_if_init_locked(ctx); 4103 CTX_UNLOCK(ctx); 4104 } 4105 4106 static void 4107 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4108 { 4109 if_ctx_t ctx = if_getsoftc(ifp); 4110 4111 if ((void *)ctx != arg) 4112 return; 4113 4114 if ((vtag == 0) || (vtag > 4095)) 4115 return; 4116 4117 CTX_LOCK(ctx); 4118 IFDI_VLAN_UNREGISTER(ctx, vtag); 4119 /* Re-init to load the changes */ 4120 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4121 iflib_if_init_locked(ctx); 4122 CTX_UNLOCK(ctx); 4123 } 4124 4125 static void 4126 iflib_led_func(void *arg, int onoff) 4127 { 4128 if_ctx_t ctx = arg; 4129 4130 CTX_LOCK(ctx); 4131 IFDI_LED_FUNC(ctx, onoff); 4132 CTX_UNLOCK(ctx); 4133 } 4134 4135 /********************************************************************* 4136 * 4137 * BUS FUNCTION DEFINITIONS 4138 * 4139 **********************************************************************/ 4140 4141 int 4142 iflib_device_probe(device_t dev) 4143 { 4144 pci_vendor_info_t *ent; 4145 4146 uint16_t pci_vendor_id, pci_device_id; 4147 uint16_t pci_subvendor_id, pci_subdevice_id; 4148 uint16_t pci_rev_id; 4149 if_shared_ctx_t sctx; 4150 4151 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4152 return (ENOTSUP); 4153 4154 pci_vendor_id = pci_get_vendor(dev); 4155 pci_device_id = pci_get_device(dev); 4156 pci_subvendor_id = pci_get_subvendor(dev); 4157 pci_subdevice_id = pci_get_subdevice(dev); 4158 pci_rev_id = pci_get_revid(dev); 4159 if (sctx->isc_parse_devinfo != NULL) 4160 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4161 4162 ent = sctx->isc_vendor_info; 4163 while (ent->pvi_vendor_id != 0) { 4164 if (pci_vendor_id != ent->pvi_vendor_id) { 4165 ent++; 4166 continue; 4167 } 4168 if ((pci_device_id == ent->pvi_device_id) && 4169 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4170 (ent->pvi_subvendor_id == 0)) && 4171 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4172 (ent->pvi_subdevice_id == 0)) && 4173 ((pci_rev_id == ent->pvi_rev_id) || 4174 (ent->pvi_rev_id == 0))) { 4175 4176 device_set_desc_copy(dev, ent->pvi_name); 4177 /* this needs to be changed to zero if the bus probing code 4178 * ever stops re-probing on best match because the sctx 4179 * may have its values over written by register calls 4180 * in subsequent probes 4181 */ 4182 return (BUS_PROBE_DEFAULT); 4183 } 4184 ent++; 4185 } 4186 return (ENXIO); 4187 } 4188 4189 int 4190 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4191 { 4192 int err, rid, msix, msix_bar; 4193 if_ctx_t ctx; 4194 if_t ifp; 4195 if_softc_ctx_t scctx; 4196 int i; 4197 uint16_t main_txq; 4198 uint16_t main_rxq; 4199 4200 4201 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4202 4203 if (sc == NULL) { 4204 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4205 device_set_softc(dev, ctx); 4206 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4207 } 4208 4209 ctx->ifc_sctx = sctx; 4210 ctx->ifc_dev = dev; 4211 ctx->ifc_softc = sc; 4212 4213 if ((err = iflib_register(ctx)) != 0) { 4214 device_printf(dev, "iflib_register failed %d\n", err); 4215 return (err); 4216 } 4217 iflib_add_device_sysctl_pre(ctx); 4218 4219 scctx = &ctx->ifc_softc_ctx; 4220 ifp = ctx->ifc_ifp; 4221 ctx->ifc_nhwtxqs = sctx->isc_ntxqs; 4222 4223 /* 4224 * XXX sanity check that ntxd & nrxd are a power of 2 4225 */ 4226 if (ctx->ifc_sysctl_ntxqs != 0) 4227 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4228 if (ctx->ifc_sysctl_nrxqs != 0) 4229 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4230 4231 for (i = 0; i < sctx->isc_ntxqs; i++) { 4232 if (ctx->ifc_sysctl_ntxds[i] != 0) 4233 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4234 else 4235 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4236 } 4237 4238 for (i = 0; i < sctx->isc_nrxqs; i++) { 4239 if (ctx->ifc_sysctl_nrxds[i] != 0) 4240 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4241 else 4242 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4243 } 4244 4245 for (i = 0; i < sctx->isc_nrxqs; i++) { 4246 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4247 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4248 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4249 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4250 } 4251 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4252 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4253 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4254 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4255 } 4256 } 4257 4258 for (i = 0; i < sctx->isc_ntxqs; i++) { 4259 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4260 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4261 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4262 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4263 } 4264 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4265 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4266 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4267 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4268 } 4269 } 4270 4271 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4272 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4273 return (err); 4274 } 4275 _iflib_pre_assert(scctx); 4276 ctx->ifc_txrx = *scctx->isc_txrx; 4277 4278 #ifdef INVARIANTS 4279 MPASS(scctx->isc_capenable); 4280 if (scctx->isc_capenable & IFCAP_TXCSUM) 4281 MPASS(scctx->isc_tx_csum_flags); 4282 #endif 4283 4284 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4285 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4286 4287 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4288 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4289 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4290 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4291 4292 #ifdef ACPI_DMAR 4293 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4294 ctx->ifc_flags |= IFC_DMAR; 4295 #elif !(defined(__i386__) || defined(__amd64__)) 4296 /* set unconditionally for !x86 */ 4297 ctx->ifc_flags |= IFC_DMAR; 4298 #endif 4299 4300 msix_bar = scctx->isc_msix_bar; 4301 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4302 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4303 4304 /* XXX change for per-queue sizes */ 4305 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4306 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4307 for (i = 0; i < sctx->isc_nrxqs; i++) { 4308 if (!powerof2(scctx->isc_nrxd[i])) { 4309 /* round down instead? */ 4310 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4311 err = EINVAL; 4312 goto fail; 4313 } 4314 } 4315 for (i = 0; i < sctx->isc_ntxqs; i++) { 4316 if (!powerof2(scctx->isc_ntxd[i])) { 4317 device_printf(dev, 4318 "# tx descriptors must be a power of 2"); 4319 err = EINVAL; 4320 goto fail; 4321 } 4322 } 4323 4324 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4325 MAX_SINGLE_PACKET_FRACTION) 4326 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4327 MAX_SINGLE_PACKET_FRACTION); 4328 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4329 MAX_SINGLE_PACKET_FRACTION) 4330 scctx->isc_tx_tso_segments_max = max(1, 4331 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4332 4333 /* 4334 * Protect the stack against modern hardware 4335 */ 4336 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4337 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4338 4339 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4340 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4341 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4342 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4343 if (scctx->isc_rss_table_size == 0) 4344 scctx->isc_rss_table_size = 64; 4345 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4346 4347 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4348 /* XXX format name */ 4349 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4350 4351 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4352 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4353 device_printf(dev, "Unable to fetch CPU list\n"); 4354 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4355 } 4356 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4357 4358 /* 4359 ** Now setup MSI or MSI/X, should 4360 ** return us the number of supported 4361 ** vectors. (Will be 1 for MSI) 4362 */ 4363 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4364 msix = scctx->isc_vectors; 4365 } else if (scctx->isc_msix_bar != 0) 4366 /* 4367 * The simple fact that isc_msix_bar is not 0 does not mean we 4368 * we have a good value there that is known to work. 4369 */ 4370 msix = iflib_msix_init(ctx); 4371 else { 4372 scctx->isc_vectors = 1; 4373 scctx->isc_ntxqsets = 1; 4374 scctx->isc_nrxqsets = 1; 4375 scctx->isc_intr = IFLIB_INTR_LEGACY; 4376 msix = 0; 4377 } 4378 /* Get memory for the station queues */ 4379 if ((err = iflib_queues_alloc(ctx))) { 4380 device_printf(dev, "Unable to allocate queue memory\n"); 4381 goto fail; 4382 } 4383 4384 if ((err = iflib_qset_structures_setup(ctx))) { 4385 device_printf(dev, "qset structure setup failed %d\n", err); 4386 goto fail_queues; 4387 } 4388 4389 /* 4390 * Group taskqueues aren't properly set up until SMP is started, 4391 * so we disable interrupts until we can handle them post 4392 * SI_SUB_SMP. 4393 * 4394 * XXX: disabling interrupts doesn't actually work, at least for 4395 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4396 * we do null handling and depend on this not causing too large an 4397 * interrupt storm. 4398 */ 4399 IFDI_INTR_DISABLE(ctx); 4400 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4401 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4402 goto fail_intr_free; 4403 } 4404 if (msix <= 1) { 4405 rid = 0; 4406 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4407 MPASS(msix == 1); 4408 rid = 1; 4409 } 4410 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4411 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4412 goto fail_intr_free; 4413 } 4414 } 4415 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4416 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4417 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4418 goto fail_detach; 4419 } 4420 if ((err = iflib_netmap_attach(ctx))) { 4421 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4422 goto fail_detach; 4423 } 4424 *ctxp = ctx; 4425 4426 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4427 iflib_add_device_sysctl_post(ctx); 4428 ctx->ifc_flags |= IFC_INIT_DONE; 4429 return (0); 4430 fail_detach: 4431 ether_ifdetach(ctx->ifc_ifp); 4432 fail_intr_free: 4433 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4434 pci_release_msi(ctx->ifc_dev); 4435 fail_queues: 4436 /* XXX free queues */ 4437 fail: 4438 IFDI_DETACH(ctx); 4439 return (err); 4440 } 4441 4442 int 4443 iflib_device_attach(device_t dev) 4444 { 4445 if_ctx_t ctx; 4446 if_shared_ctx_t sctx; 4447 4448 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4449 return (ENOTSUP); 4450 4451 pci_enable_busmaster(dev); 4452 4453 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4454 } 4455 4456 int 4457 iflib_device_deregister(if_ctx_t ctx) 4458 { 4459 if_t ifp = ctx->ifc_ifp; 4460 iflib_txq_t txq; 4461 iflib_rxq_t rxq; 4462 device_t dev = ctx->ifc_dev; 4463 int i, j; 4464 struct taskqgroup *tqg; 4465 iflib_fl_t fl; 4466 4467 /* Make sure VLANS are not using driver */ 4468 if (if_vlantrunkinuse(ifp)) { 4469 device_printf(dev,"Vlan in use, detach first\n"); 4470 return (EBUSY); 4471 } 4472 4473 CTX_LOCK(ctx); 4474 ctx->ifc_in_detach = 1; 4475 iflib_stop(ctx); 4476 CTX_UNLOCK(ctx); 4477 4478 /* Unregister VLAN events */ 4479 if (ctx->ifc_vlan_attach_event != NULL) 4480 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4481 if (ctx->ifc_vlan_detach_event != NULL) 4482 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4483 4484 iflib_netmap_detach(ifp); 4485 ether_ifdetach(ifp); 4486 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4487 CTX_LOCK_DESTROY(ctx); 4488 if (ctx->ifc_led_dev != NULL) 4489 led_destroy(ctx->ifc_led_dev); 4490 /* XXX drain any dependent tasks */ 4491 tqg = qgroup_if_io_tqg; 4492 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4493 callout_drain(&txq->ift_timer); 4494 if (txq->ift_task.gt_uniq != NULL) 4495 taskqgroup_detach(tqg, &txq->ift_task); 4496 } 4497 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4498 if (rxq->ifr_task.gt_uniq != NULL) 4499 taskqgroup_detach(tqg, &rxq->ifr_task); 4500 4501 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4502 free(fl->ifl_rx_bitmap, M_IFLIB); 4503 4504 } 4505 tqg = qgroup_if_config_tqg; 4506 if (ctx->ifc_admin_task.gt_uniq != NULL) 4507 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4508 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4509 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4510 4511 IFDI_DETACH(ctx); 4512 device_set_softc(ctx->ifc_dev, NULL); 4513 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4514 pci_release_msi(dev); 4515 } 4516 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4517 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4518 } 4519 if (ctx->ifc_msix_mem != NULL) { 4520 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4521 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4522 ctx->ifc_msix_mem = NULL; 4523 } 4524 4525 bus_generic_detach(dev); 4526 if_free(ifp); 4527 4528 iflib_tx_structures_free(ctx); 4529 iflib_rx_structures_free(ctx); 4530 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4531 free(ctx->ifc_softc, M_IFLIB); 4532 free(ctx, M_IFLIB); 4533 return (0); 4534 } 4535 4536 4537 int 4538 iflib_device_detach(device_t dev) 4539 { 4540 if_ctx_t ctx = device_get_softc(dev); 4541 4542 return (iflib_device_deregister(ctx)); 4543 } 4544 4545 int 4546 iflib_device_suspend(device_t dev) 4547 { 4548 if_ctx_t ctx = device_get_softc(dev); 4549 4550 CTX_LOCK(ctx); 4551 IFDI_SUSPEND(ctx); 4552 CTX_UNLOCK(ctx); 4553 4554 return bus_generic_suspend(dev); 4555 } 4556 int 4557 iflib_device_shutdown(device_t dev) 4558 { 4559 if_ctx_t ctx = device_get_softc(dev); 4560 4561 CTX_LOCK(ctx); 4562 IFDI_SHUTDOWN(ctx); 4563 CTX_UNLOCK(ctx); 4564 4565 return bus_generic_suspend(dev); 4566 } 4567 4568 4569 int 4570 iflib_device_resume(device_t dev) 4571 { 4572 if_ctx_t ctx = device_get_softc(dev); 4573 iflib_txq_t txq = ctx->ifc_txqs; 4574 4575 CTX_LOCK(ctx); 4576 IFDI_RESUME(ctx); 4577 iflib_init_locked(ctx); 4578 CTX_UNLOCK(ctx); 4579 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4580 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4581 4582 return (bus_generic_resume(dev)); 4583 } 4584 4585 int 4586 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4587 { 4588 int error; 4589 if_ctx_t ctx = device_get_softc(dev); 4590 4591 CTX_LOCK(ctx); 4592 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4593 CTX_UNLOCK(ctx); 4594 4595 return (error); 4596 } 4597 4598 void 4599 iflib_device_iov_uninit(device_t dev) 4600 { 4601 if_ctx_t ctx = device_get_softc(dev); 4602 4603 CTX_LOCK(ctx); 4604 IFDI_IOV_UNINIT(ctx); 4605 CTX_UNLOCK(ctx); 4606 } 4607 4608 int 4609 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 4610 { 4611 int error; 4612 if_ctx_t ctx = device_get_softc(dev); 4613 4614 CTX_LOCK(ctx); 4615 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 4616 CTX_UNLOCK(ctx); 4617 4618 return (error); 4619 } 4620 4621 /********************************************************************* 4622 * 4623 * MODULE FUNCTION DEFINITIONS 4624 * 4625 **********************************************************************/ 4626 4627 /* 4628 * - Start a fast taskqueue thread for each core 4629 * - Start a taskqueue for control operations 4630 */ 4631 static int 4632 iflib_module_init(void) 4633 { 4634 return (0); 4635 } 4636 4637 static int 4638 iflib_module_event_handler(module_t mod, int what, void *arg) 4639 { 4640 int err; 4641 4642 switch (what) { 4643 case MOD_LOAD: 4644 if ((err = iflib_module_init()) != 0) 4645 return (err); 4646 break; 4647 case MOD_UNLOAD: 4648 return (EBUSY); 4649 default: 4650 return (EOPNOTSUPP); 4651 } 4652 4653 return (0); 4654 } 4655 4656 /********************************************************************* 4657 * 4658 * PUBLIC FUNCTION DEFINITIONS 4659 * ordered as in iflib.h 4660 * 4661 **********************************************************************/ 4662 4663 4664 static void 4665 _iflib_assert(if_shared_ctx_t sctx) 4666 { 4667 MPASS(sctx->isc_tx_maxsize); 4668 MPASS(sctx->isc_tx_maxsegsize); 4669 4670 MPASS(sctx->isc_rx_maxsize); 4671 MPASS(sctx->isc_rx_nsegments); 4672 MPASS(sctx->isc_rx_maxsegsize); 4673 4674 MPASS(sctx->isc_nrxd_min[0]); 4675 MPASS(sctx->isc_nrxd_max[0]); 4676 MPASS(sctx->isc_nrxd_default[0]); 4677 MPASS(sctx->isc_ntxd_min[0]); 4678 MPASS(sctx->isc_ntxd_max[0]); 4679 MPASS(sctx->isc_ntxd_default[0]); 4680 } 4681 4682 static void 4683 _iflib_pre_assert(if_softc_ctx_t scctx) 4684 { 4685 4686 MPASS(scctx->isc_txrx->ift_txd_encap); 4687 MPASS(scctx->isc_txrx->ift_txd_flush); 4688 MPASS(scctx->isc_txrx->ift_txd_credits_update); 4689 MPASS(scctx->isc_txrx->ift_rxd_available); 4690 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 4691 MPASS(scctx->isc_txrx->ift_rxd_refill); 4692 MPASS(scctx->isc_txrx->ift_rxd_flush); 4693 } 4694 4695 static int 4696 iflib_register(if_ctx_t ctx) 4697 { 4698 if_shared_ctx_t sctx = ctx->ifc_sctx; 4699 driver_t *driver = sctx->isc_driver; 4700 device_t dev = ctx->ifc_dev; 4701 if_t ifp; 4702 4703 _iflib_assert(sctx); 4704 4705 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 4706 4707 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 4708 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 4709 if (ifp == NULL) { 4710 device_printf(dev, "can not allocate ifnet structure\n"); 4711 return (ENOMEM); 4712 } 4713 4714 /* 4715 * Initialize our context's device specific methods 4716 */ 4717 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 4718 kobj_class_compile((kobj_class_t) driver); 4719 driver->refs++; 4720 4721 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 4722 if_setsoftc(ifp, ctx); 4723 if_setdev(ifp, dev); 4724 if_setinitfn(ifp, iflib_if_init); 4725 if_setioctlfn(ifp, iflib_if_ioctl); 4726 if_settransmitfn(ifp, iflib_if_transmit); 4727 if_setqflushfn(ifp, iflib_if_qflush); 4728 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 4729 4730 ctx->ifc_vlan_attach_event = 4731 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 4732 EVENTHANDLER_PRI_FIRST); 4733 ctx->ifc_vlan_detach_event = 4734 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 4735 EVENTHANDLER_PRI_FIRST); 4736 4737 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 4738 iflib_media_change, iflib_media_status); 4739 4740 return (0); 4741 } 4742 4743 4744 static int 4745 iflib_queues_alloc(if_ctx_t ctx) 4746 { 4747 if_shared_ctx_t sctx = ctx->ifc_sctx; 4748 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4749 device_t dev = ctx->ifc_dev; 4750 int nrxqsets = scctx->isc_nrxqsets; 4751 int ntxqsets = scctx->isc_ntxqsets; 4752 iflib_txq_t txq; 4753 iflib_rxq_t rxq; 4754 iflib_fl_t fl = NULL; 4755 int i, j, cpu, err, txconf, rxconf; 4756 iflib_dma_info_t ifdip; 4757 uint32_t *rxqsizes = scctx->isc_rxqsizes; 4758 uint32_t *txqsizes = scctx->isc_txqsizes; 4759 uint8_t nrxqs = sctx->isc_nrxqs; 4760 uint8_t ntxqs = sctx->isc_ntxqs; 4761 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 4762 caddr_t *vaddrs; 4763 uint64_t *paddrs; 4764 struct ifmp_ring **brscp; 4765 4766 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 4767 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 4768 4769 brscp = NULL; 4770 txq = NULL; 4771 rxq = NULL; 4772 4773 /* Allocate the TX ring struct memory */ 4774 if (!(txq = 4775 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 4776 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4777 device_printf(dev, "Unable to allocate TX ring memory\n"); 4778 err = ENOMEM; 4779 goto fail; 4780 } 4781 4782 /* Now allocate the RX */ 4783 if (!(rxq = 4784 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 4785 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4786 device_printf(dev, "Unable to allocate RX ring memory\n"); 4787 err = ENOMEM; 4788 goto rx_fail; 4789 } 4790 4791 ctx->ifc_txqs = txq; 4792 ctx->ifc_rxqs = rxq; 4793 4794 /* 4795 * XXX handle allocation failure 4796 */ 4797 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 4798 /* Set up some basics */ 4799 4800 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4801 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4802 err = ENOMEM; 4803 goto err_tx_desc; 4804 } 4805 txq->ift_ifdi = ifdip; 4806 for (j = 0; j < ntxqs; j++, ifdip++) { 4807 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4808 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4809 err = ENOMEM; 4810 goto err_tx_desc; 4811 } 4812 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 4813 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 4814 } 4815 txq->ift_ctx = ctx; 4816 txq->ift_id = i; 4817 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 4818 txq->ift_br_offset = 1; 4819 } else { 4820 txq->ift_br_offset = 0; 4821 } 4822 /* XXX fix this */ 4823 txq->ift_timer.c_cpu = cpu; 4824 4825 if (iflib_txsd_alloc(txq)) { 4826 device_printf(dev, "Critical Failure setting up TX buffers\n"); 4827 err = ENOMEM; 4828 goto err_tx_desc; 4829 } 4830 4831 /* Initialize the TX lock */ 4832 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 4833 device_get_nameunit(dev), txq->ift_id); 4834 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 4835 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 4836 4837 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 4838 device_get_nameunit(dev), txq->ift_id); 4839 4840 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 4841 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 4842 if (err) { 4843 /* XXX free any allocated rings */ 4844 device_printf(dev, "Unable to allocate buf_ring\n"); 4845 goto err_tx_desc; 4846 } 4847 } 4848 4849 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 4850 /* Set up some basics */ 4851 4852 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4853 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4854 err = ENOMEM; 4855 goto err_tx_desc; 4856 } 4857 4858 rxq->ifr_ifdi = ifdip; 4859 /* XXX this needs to be changed if #rx queues != #tx queues */ 4860 rxq->ifr_ntxqirq = 1; 4861 rxq->ifr_txqid[0] = i; 4862 for (j = 0; j < nrxqs; j++, ifdip++) { 4863 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4864 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4865 err = ENOMEM; 4866 goto err_tx_desc; 4867 } 4868 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 4869 } 4870 rxq->ifr_ctx = ctx; 4871 rxq->ifr_id = i; 4872 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 4873 rxq->ifr_fl_offset = 1; 4874 } else { 4875 rxq->ifr_fl_offset = 0; 4876 } 4877 rxq->ifr_nfl = nfree_lists; 4878 if (!(fl = 4879 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 4880 device_printf(dev, "Unable to allocate free list memory\n"); 4881 err = ENOMEM; 4882 goto err_tx_desc; 4883 } 4884 rxq->ifr_fl = fl; 4885 for (j = 0; j < nfree_lists; j++) { 4886 fl[j].ifl_rxq = rxq; 4887 fl[j].ifl_id = j; 4888 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 4889 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 4890 } 4891 /* Allocate receive buffers for the ring*/ 4892 if (iflib_rxsd_alloc(rxq)) { 4893 device_printf(dev, 4894 "Critical Failure setting up receive buffers\n"); 4895 err = ENOMEM; 4896 goto err_rx_desc; 4897 } 4898 4899 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4900 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 4901 } 4902 4903 /* TXQs */ 4904 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4905 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4906 for (i = 0; i < ntxqsets; i++) { 4907 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 4908 4909 for (j = 0; j < ntxqs; j++, di++) { 4910 vaddrs[i*ntxqs + j] = di->idi_vaddr; 4911 paddrs[i*ntxqs + j] = di->idi_paddr; 4912 } 4913 } 4914 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 4915 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4916 iflib_tx_structures_free(ctx); 4917 free(vaddrs, M_IFLIB); 4918 free(paddrs, M_IFLIB); 4919 goto err_rx_desc; 4920 } 4921 free(vaddrs, M_IFLIB); 4922 free(paddrs, M_IFLIB); 4923 4924 /* RXQs */ 4925 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4926 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4927 for (i = 0; i < nrxqsets; i++) { 4928 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 4929 4930 for (j = 0; j < nrxqs; j++, di++) { 4931 vaddrs[i*nrxqs + j] = di->idi_vaddr; 4932 paddrs[i*nrxqs + j] = di->idi_paddr; 4933 } 4934 } 4935 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 4936 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4937 iflib_tx_structures_free(ctx); 4938 free(vaddrs, M_IFLIB); 4939 free(paddrs, M_IFLIB); 4940 goto err_rx_desc; 4941 } 4942 free(vaddrs, M_IFLIB); 4943 free(paddrs, M_IFLIB); 4944 4945 return (0); 4946 4947 /* XXX handle allocation failure changes */ 4948 err_rx_desc: 4949 err_tx_desc: 4950 if (ctx->ifc_rxqs != NULL) 4951 free(ctx->ifc_rxqs, M_IFLIB); 4952 ctx->ifc_rxqs = NULL; 4953 if (ctx->ifc_txqs != NULL) 4954 free(ctx->ifc_txqs, M_IFLIB); 4955 ctx->ifc_txqs = NULL; 4956 rx_fail: 4957 if (brscp != NULL) 4958 free(brscp, M_IFLIB); 4959 if (rxq != NULL) 4960 free(rxq, M_IFLIB); 4961 if (txq != NULL) 4962 free(txq, M_IFLIB); 4963 fail: 4964 return (err); 4965 } 4966 4967 static int 4968 iflib_tx_structures_setup(if_ctx_t ctx) 4969 { 4970 iflib_txq_t txq = ctx->ifc_txqs; 4971 int i; 4972 4973 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4974 iflib_txq_setup(txq); 4975 4976 return (0); 4977 } 4978 4979 static void 4980 iflib_tx_structures_free(if_ctx_t ctx) 4981 { 4982 iflib_txq_t txq = ctx->ifc_txqs; 4983 int i, j; 4984 4985 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 4986 iflib_txq_destroy(txq); 4987 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 4988 iflib_dma_free(&txq->ift_ifdi[j]); 4989 } 4990 free(ctx->ifc_txqs, M_IFLIB); 4991 ctx->ifc_txqs = NULL; 4992 IFDI_QUEUES_FREE(ctx); 4993 } 4994 4995 /********************************************************************* 4996 * 4997 * Initialize all receive rings. 4998 * 4999 **********************************************************************/ 5000 static int 5001 iflib_rx_structures_setup(if_ctx_t ctx) 5002 { 5003 iflib_rxq_t rxq = ctx->ifc_rxqs; 5004 int q; 5005 #if defined(INET6) || defined(INET) 5006 int i, err; 5007 #endif 5008 5009 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5010 #if defined(INET6) || defined(INET) 5011 tcp_lro_free(&rxq->ifr_lc); 5012 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5013 TCP_LRO_ENTRIES, min(1024, 5014 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 5015 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 5016 goto fail; 5017 } 5018 rxq->ifr_lro_enabled = TRUE; 5019 #endif 5020 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5021 } 5022 return (0); 5023 #if defined(INET6) || defined(INET) 5024 fail: 5025 /* 5026 * Free RX software descriptors allocated so far, we will only handle 5027 * the rings that completed, the failing case will have 5028 * cleaned up for itself. 'q' failed, so its the terminus. 5029 */ 5030 rxq = ctx->ifc_rxqs; 5031 for (i = 0; i < q; ++i, rxq++) { 5032 iflib_rx_sds_free(rxq); 5033 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5034 } 5035 return (err); 5036 #endif 5037 } 5038 5039 /********************************************************************* 5040 * 5041 * Free all receive rings. 5042 * 5043 **********************************************************************/ 5044 static void 5045 iflib_rx_structures_free(if_ctx_t ctx) 5046 { 5047 iflib_rxq_t rxq = ctx->ifc_rxqs; 5048 5049 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5050 iflib_rx_sds_free(rxq); 5051 } 5052 } 5053 5054 static int 5055 iflib_qset_structures_setup(if_ctx_t ctx) 5056 { 5057 int err; 5058 5059 if ((err = iflib_tx_structures_setup(ctx)) != 0) 5060 return (err); 5061 5062 if ((err = iflib_rx_structures_setup(ctx)) != 0) { 5063 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5064 iflib_tx_structures_free(ctx); 5065 iflib_rx_structures_free(ctx); 5066 } 5067 return (err); 5068 } 5069 5070 int 5071 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5072 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name) 5073 { 5074 5075 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5076 } 5077 5078 #ifdef SMP 5079 static int 5080 find_nth(if_ctx_t ctx, int qid) 5081 { 5082 cpuset_t cpus; 5083 int i, cpuid, eqid, count; 5084 5085 CPU_COPY(&ctx->ifc_cpus, &cpus); 5086 count = CPU_COUNT(&cpus); 5087 eqid = qid % count; 5088 /* clear up to the qid'th bit */ 5089 for (i = 0; i < eqid; i++) { 5090 cpuid = CPU_FFS(&cpus); 5091 MPASS(cpuid != 0); 5092 CPU_CLR(cpuid-1, &cpus); 5093 } 5094 cpuid = CPU_FFS(&cpus); 5095 MPASS(cpuid != 0); 5096 return (cpuid-1); 5097 } 5098 5099 #ifdef SCHED_ULE 5100 extern struct cpu_group *cpu_top; /* CPU topology */ 5101 5102 static int 5103 find_child_with_core(int cpu, struct cpu_group *grp) 5104 { 5105 int i; 5106 5107 if (grp->cg_children == 0) 5108 return -1; 5109 5110 MPASS(grp->cg_child); 5111 for (i = 0; i < grp->cg_children; i++) { 5112 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5113 return i; 5114 } 5115 5116 return -1; 5117 } 5118 5119 /* 5120 * Find the nth "close" core to the specified core 5121 * "close" is defined as the deepest level that shares 5122 * at least an L2 cache. With threads, this will be 5123 * threads on the same core. If the sahred cache is L3 5124 * or higher, simply returns the same core. 5125 */ 5126 static int 5127 find_close_core(int cpu, int core_offset) 5128 { 5129 struct cpu_group *grp; 5130 int i; 5131 int fcpu; 5132 cpuset_t cs; 5133 5134 grp = cpu_top; 5135 if (grp == NULL) 5136 return cpu; 5137 i = 0; 5138 while ((i = find_child_with_core(cpu, grp)) != -1) { 5139 /* If the child only has one cpu, don't descend */ 5140 if (grp->cg_child[i].cg_count <= 1) 5141 break; 5142 grp = &grp->cg_child[i]; 5143 } 5144 5145 /* If they don't share at least an L2 cache, use the same CPU */ 5146 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5147 return cpu; 5148 5149 /* Now pick one */ 5150 CPU_COPY(&grp->cg_mask, &cs); 5151 5152 /* Add the selected CPU offset to core offset. */ 5153 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5154 if (fcpu - 1 == cpu) 5155 break; 5156 CPU_CLR(fcpu - 1, &cs); 5157 } 5158 MPASS(fcpu); 5159 5160 core_offset += i; 5161 5162 CPU_COPY(&grp->cg_mask, &cs); 5163 for (i = core_offset % grp->cg_count; i > 0; i--) { 5164 MPASS(CPU_FFS(&cs)); 5165 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5166 } 5167 MPASS(CPU_FFS(&cs)); 5168 return CPU_FFS(&cs) - 1; 5169 } 5170 #else 5171 static int 5172 find_close_core(int cpu, int core_offset __unused) 5173 { 5174 return cpu; 5175 } 5176 #endif 5177 5178 static int 5179 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5180 { 5181 switch (type) { 5182 case IFLIB_INTR_TX: 5183 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5184 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5185 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5186 case IFLIB_INTR_RX: 5187 case IFLIB_INTR_RXTX: 5188 /* RX queues get the specified core */ 5189 return qid / CPU_COUNT(&ctx->ifc_cpus); 5190 default: 5191 return -1; 5192 } 5193 } 5194 #else 5195 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5196 #define find_close_core(cpuid, tid) CPU_FIRST() 5197 #define find_nth(ctx, gid) CPU_FIRST() 5198 #endif 5199 5200 /* Just to avoid copy/paste */ 5201 static inline int 5202 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid, 5203 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, char *name) 5204 { 5205 int cpuid; 5206 int err, tid; 5207 5208 cpuid = find_nth(ctx, qid); 5209 tid = get_core_offset(ctx, type, qid); 5210 MPASS(tid >= 0); 5211 cpuid = find_close_core(cpuid, tid); 5212 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name); 5213 if (err) { 5214 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err); 5215 return (err); 5216 } 5217 #ifdef notyet 5218 if (cpuid > ctx->ifc_cpuid_highest) 5219 ctx->ifc_cpuid_highest = cpuid; 5220 #endif 5221 return 0; 5222 } 5223 5224 int 5225 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5226 iflib_intr_type_t type, driver_filter_t *filter, 5227 void *filter_arg, int qid, char *name) 5228 { 5229 struct grouptask *gtask; 5230 struct taskqgroup *tqg; 5231 iflib_filter_info_t info; 5232 gtask_fn_t *fn; 5233 int tqrid, err; 5234 driver_filter_t *intr_fast; 5235 void *q; 5236 5237 info = &ctx->ifc_filter_info; 5238 tqrid = rid; 5239 5240 switch (type) { 5241 /* XXX merge tx/rx for netmap? */ 5242 case IFLIB_INTR_TX: 5243 q = &ctx->ifc_txqs[qid]; 5244 info = &ctx->ifc_txqs[qid].ift_filter_info; 5245 gtask = &ctx->ifc_txqs[qid].ift_task; 5246 tqg = qgroup_if_io_tqg; 5247 fn = _task_fn_tx; 5248 intr_fast = iflib_fast_intr; 5249 GROUPTASK_INIT(gtask, 0, fn, q); 5250 break; 5251 case IFLIB_INTR_RX: 5252 q = &ctx->ifc_rxqs[qid]; 5253 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5254 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5255 tqg = qgroup_if_io_tqg; 5256 fn = _task_fn_rx; 5257 intr_fast = iflib_fast_intr; 5258 GROUPTASK_INIT(gtask, 0, fn, q); 5259 break; 5260 case IFLIB_INTR_RXTX: 5261 q = &ctx->ifc_rxqs[qid]; 5262 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5263 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5264 tqg = qgroup_if_io_tqg; 5265 fn = _task_fn_rx; 5266 intr_fast = iflib_fast_intr_rxtx; 5267 GROUPTASK_INIT(gtask, 0, fn, q); 5268 break; 5269 case IFLIB_INTR_ADMIN: 5270 q = ctx; 5271 tqrid = -1; 5272 info = &ctx->ifc_filter_info; 5273 gtask = &ctx->ifc_admin_task; 5274 tqg = qgroup_if_config_tqg; 5275 fn = _task_fn_admin; 5276 intr_fast = iflib_fast_intr_ctx; 5277 break; 5278 default: 5279 panic("unknown net intr type"); 5280 } 5281 5282 info->ifi_filter = filter; 5283 info->ifi_filter_arg = filter_arg; 5284 info->ifi_task = gtask; 5285 info->ifi_ctx = q; 5286 5287 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5288 if (err != 0) { 5289 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 5290 return (err); 5291 } 5292 if (type == IFLIB_INTR_ADMIN) 5293 return (0); 5294 5295 if (tqrid != -1) { 5296 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name); 5297 if (err) 5298 return (err); 5299 } else { 5300 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5301 } 5302 5303 return (0); 5304 } 5305 5306 void 5307 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, char *name) 5308 { 5309 struct grouptask *gtask; 5310 struct taskqgroup *tqg; 5311 gtask_fn_t *fn; 5312 void *q; 5313 int irq_num = -1; 5314 int err; 5315 5316 switch (type) { 5317 case IFLIB_INTR_TX: 5318 q = &ctx->ifc_txqs[qid]; 5319 gtask = &ctx->ifc_txqs[qid].ift_task; 5320 tqg = qgroup_if_io_tqg; 5321 fn = _task_fn_tx; 5322 if (irq != NULL) 5323 irq_num = rman_get_start(irq->ii_res); 5324 break; 5325 case IFLIB_INTR_RX: 5326 q = &ctx->ifc_rxqs[qid]; 5327 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5328 tqg = qgroup_if_io_tqg; 5329 fn = _task_fn_rx; 5330 if (irq != NULL) 5331 irq_num = rman_get_start(irq->ii_res); 5332 break; 5333 case IFLIB_INTR_IOV: 5334 q = ctx; 5335 gtask = &ctx->ifc_vflr_task; 5336 tqg = qgroup_if_config_tqg; 5337 fn = _task_fn_iov; 5338 break; 5339 default: 5340 panic("unknown net intr type"); 5341 } 5342 GROUPTASK_INIT(gtask, 0, fn, q); 5343 if (irq_num != -1) { 5344 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name); 5345 if (err) 5346 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5347 } 5348 else { 5349 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5350 } 5351 } 5352 5353 void 5354 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5355 { 5356 if (irq->ii_tag) 5357 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5358 5359 if (irq->ii_res) 5360 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5361 } 5362 5363 static int 5364 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name) 5365 { 5366 iflib_txq_t txq = ctx->ifc_txqs; 5367 iflib_rxq_t rxq = ctx->ifc_rxqs; 5368 if_irq_t irq = &ctx->ifc_legacy_irq; 5369 iflib_filter_info_t info; 5370 struct grouptask *gtask; 5371 struct taskqgroup *tqg; 5372 gtask_fn_t *fn; 5373 int tqrid; 5374 void *q; 5375 int err; 5376 5377 q = &ctx->ifc_rxqs[0]; 5378 info = &rxq[0].ifr_filter_info; 5379 gtask = &rxq[0].ifr_task; 5380 tqg = qgroup_if_io_tqg; 5381 tqrid = irq->ii_rid = *rid; 5382 fn = _task_fn_rx; 5383 5384 ctx->ifc_flags |= IFC_LEGACY; 5385 info->ifi_filter = filter; 5386 info->ifi_filter_arg = filter_arg; 5387 info->ifi_task = gtask; 5388 info->ifi_ctx = ctx; 5389 5390 /* We allocate a single interrupt resource */ 5391 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5392 return (err); 5393 GROUPTASK_INIT(gtask, 0, fn, q); 5394 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5395 5396 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5397 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx"); 5398 return (0); 5399 } 5400 5401 void 5402 iflib_led_create(if_ctx_t ctx) 5403 { 5404 5405 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5406 device_get_nameunit(ctx->ifc_dev)); 5407 } 5408 5409 void 5410 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5411 { 5412 5413 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5414 } 5415 5416 void 5417 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5418 { 5419 5420 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5421 } 5422 5423 void 5424 iflib_admin_intr_deferred(if_ctx_t ctx) 5425 { 5426 #ifdef INVARIANTS 5427 struct grouptask *gtask; 5428 5429 gtask = &ctx->ifc_admin_task; 5430 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5431 #endif 5432 5433 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5434 } 5435 5436 void 5437 iflib_iov_intr_deferred(if_ctx_t ctx) 5438 { 5439 5440 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5441 } 5442 5443 void 5444 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5445 { 5446 5447 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5448 } 5449 5450 void 5451 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn, 5452 char *name) 5453 { 5454 5455 GROUPTASK_INIT(gtask, 0, fn, ctx); 5456 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5457 } 5458 5459 void 5460 iflib_config_gtask_deinit(struct grouptask *gtask) 5461 { 5462 5463 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5464 } 5465 5466 void 5467 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5468 { 5469 if_t ifp = ctx->ifc_ifp; 5470 iflib_txq_t txq = ctx->ifc_txqs; 5471 5472 if_setbaudrate(ifp, baudrate); 5473 if (baudrate >= IF_Gbps(10)) { 5474 STATE_LOCK(ctx); 5475 ctx->ifc_flags |= IFC_PREFETCH; 5476 STATE_UNLOCK(ctx); 5477 } 5478 /* If link down, disable watchdog */ 5479 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5480 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5481 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5482 } 5483 ctx->ifc_link_state = link_state; 5484 if_link_state_change(ifp, link_state); 5485 } 5486 5487 static int 5488 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5489 { 5490 int credits; 5491 #ifdef INVARIANTS 5492 int credits_pre = txq->ift_cidx_processed; 5493 #endif 5494 5495 if (ctx->isc_txd_credits_update == NULL) 5496 return (0); 5497 5498 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5499 return (0); 5500 5501 txq->ift_processed += credits; 5502 txq->ift_cidx_processed += credits; 5503 5504 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5505 if (txq->ift_cidx_processed >= txq->ift_size) 5506 txq->ift_cidx_processed -= txq->ift_size; 5507 return (credits); 5508 } 5509 5510 static int 5511 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5512 { 5513 5514 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5515 budget)); 5516 } 5517 5518 void 5519 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5520 const char *description, if_int_delay_info_t info, 5521 int offset, int value) 5522 { 5523 info->iidi_ctx = ctx; 5524 info->iidi_offset = offset; 5525 info->iidi_value = value; 5526 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5527 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5528 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5529 info, 0, iflib_sysctl_int_delay, "I", description); 5530 } 5531 5532 struct mtx * 5533 iflib_ctx_lock_get(if_ctx_t ctx) 5534 { 5535 5536 return (&ctx->ifc_ctx_mtx); 5537 } 5538 5539 static int 5540 iflib_msix_init(if_ctx_t ctx) 5541 { 5542 device_t dev = ctx->ifc_dev; 5543 if_shared_ctx_t sctx = ctx->ifc_sctx; 5544 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5545 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5546 int iflib_num_tx_queues, iflib_num_rx_queues; 5547 int err, admincnt, bar; 5548 5549 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 5550 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 5551 5552 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 5553 5554 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5555 admincnt = sctx->isc_admin_intrcnt; 5556 /* Override by global tuneable */ 5557 { 5558 int i; 5559 size_t len = sizeof(i); 5560 err = kernel_sysctlbyname(curthread, "hw.pci.enable_msix", &i, &len, NULL, 0, NULL, 0); 5561 if (err == 0) { 5562 if (i == 0) 5563 goto msi; 5564 } 5565 else { 5566 device_printf(dev, "unable to read hw.pci.enable_msix."); 5567 } 5568 } 5569 /* Override by tuneable */ 5570 if (scctx->isc_disable_msix) 5571 goto msi; 5572 5573 /* 5574 ** When used in a virtualized environment 5575 ** PCI BUSMASTER capability may not be set 5576 ** so explicity set it here and rewrite 5577 ** the ENABLE in the MSIX control register 5578 ** at this point to cause the host to 5579 ** successfully initialize us. 5580 */ 5581 { 5582 int msix_ctrl, rid; 5583 5584 pci_enable_busmaster(dev); 5585 rid = 0; 5586 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) { 5587 rid += PCIR_MSIX_CTRL; 5588 msix_ctrl = pci_read_config(dev, rid, 2); 5589 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 5590 pci_write_config(dev, rid, msix_ctrl, 2); 5591 } else { 5592 device_printf(dev, "PCIY_MSIX capability not found; " 5593 "or rid %d == 0.\n", rid); 5594 goto msi; 5595 } 5596 } 5597 5598 /* 5599 * bar == -1 => "trust me I know what I'm doing" 5600 * Some drivers are for hardware that is so shoddily 5601 * documented that no one knows which bars are which 5602 * so the developer has to map all bars. This hack 5603 * allows shoddy garbage to use msix in this framework. 5604 */ 5605 if (bar != -1) { 5606 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5607 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5608 if (ctx->ifc_msix_mem == NULL) { 5609 /* May not be enabled */ 5610 device_printf(dev, "Unable to map MSIX table \n"); 5611 goto msi; 5612 } 5613 } 5614 /* First try MSI/X */ 5615 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5616 device_printf(dev, "System has MSIX disabled \n"); 5617 bus_release_resource(dev, SYS_RES_MEMORY, 5618 bar, ctx->ifc_msix_mem); 5619 ctx->ifc_msix_mem = NULL; 5620 goto msi; 5621 } 5622 #if IFLIB_DEBUG 5623 /* use only 1 qset in debug mode */ 5624 queuemsgs = min(msgs - admincnt, 1); 5625 #else 5626 queuemsgs = msgs - admincnt; 5627 #endif 5628 #ifdef RSS 5629 queues = imin(queuemsgs, rss_getnumbuckets()); 5630 #else 5631 queues = queuemsgs; 5632 #endif 5633 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 5634 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 5635 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 5636 #ifdef RSS 5637 /* If we're doing RSS, clamp at the number of RSS buckets */ 5638 if (queues > rss_getnumbuckets()) 5639 queues = rss_getnumbuckets(); 5640 #endif 5641 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 5642 rx_queues = iflib_num_rx_queues; 5643 else 5644 rx_queues = queues; 5645 5646 if (rx_queues > scctx->isc_nrxqsets) 5647 rx_queues = scctx->isc_nrxqsets; 5648 5649 /* 5650 * We want this to be all logical CPUs by default 5651 */ 5652 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 5653 tx_queues = iflib_num_tx_queues; 5654 else 5655 tx_queues = mp_ncpus; 5656 5657 if (tx_queues > scctx->isc_ntxqsets) 5658 tx_queues = scctx->isc_ntxqsets; 5659 5660 if (ctx->ifc_sysctl_qs_eq_override == 0) { 5661 #ifdef INVARIANTS 5662 if (tx_queues != rx_queues) 5663 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 5664 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 5665 #endif 5666 tx_queues = min(rx_queues, tx_queues); 5667 rx_queues = min(rx_queues, tx_queues); 5668 } 5669 5670 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 5671 5672 vectors = rx_queues + admincnt; 5673 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 5674 device_printf(dev, 5675 "Using MSIX interrupts with %d vectors\n", vectors); 5676 scctx->isc_vectors = vectors; 5677 scctx->isc_nrxqsets = rx_queues; 5678 scctx->isc_ntxqsets = tx_queues; 5679 scctx->isc_intr = IFLIB_INTR_MSIX; 5680 5681 return (vectors); 5682 } else { 5683 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 5684 } 5685 msi: 5686 vectors = pci_msi_count(dev); 5687 scctx->isc_nrxqsets = 1; 5688 scctx->isc_ntxqsets = 1; 5689 scctx->isc_vectors = vectors; 5690 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 5691 device_printf(dev,"Using an MSI interrupt\n"); 5692 scctx->isc_intr = IFLIB_INTR_MSI; 5693 } else { 5694 device_printf(dev,"Using a Legacy interrupt\n"); 5695 scctx->isc_intr = IFLIB_INTR_LEGACY; 5696 } 5697 5698 return (vectors); 5699 } 5700 5701 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 5702 5703 static int 5704 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 5705 { 5706 int rc; 5707 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 5708 struct sbuf *sb; 5709 char *ring_state = "UNKNOWN"; 5710 5711 /* XXX needed ? */ 5712 rc = sysctl_wire_old_buffer(req, 0); 5713 MPASS(rc == 0); 5714 if (rc != 0) 5715 return (rc); 5716 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 5717 MPASS(sb != NULL); 5718 if (sb == NULL) 5719 return (ENOMEM); 5720 if (state[3] <= 3) 5721 ring_state = ring_states[state[3]]; 5722 5723 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 5724 state[0], state[1], state[2], ring_state); 5725 rc = sbuf_finish(sb); 5726 sbuf_delete(sb); 5727 return(rc); 5728 } 5729 5730 enum iflib_ndesc_handler { 5731 IFLIB_NTXD_HANDLER, 5732 IFLIB_NRXD_HANDLER, 5733 }; 5734 5735 static int 5736 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 5737 { 5738 if_ctx_t ctx = (void *)arg1; 5739 enum iflib_ndesc_handler type = arg2; 5740 char buf[256] = {0}; 5741 qidx_t *ndesc; 5742 char *p, *next; 5743 int nqs, rc, i; 5744 5745 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 5746 5747 nqs = 8; 5748 switch(type) { 5749 case IFLIB_NTXD_HANDLER: 5750 ndesc = ctx->ifc_sysctl_ntxds; 5751 if (ctx->ifc_sctx) 5752 nqs = ctx->ifc_sctx->isc_ntxqs; 5753 break; 5754 case IFLIB_NRXD_HANDLER: 5755 ndesc = ctx->ifc_sysctl_nrxds; 5756 if (ctx->ifc_sctx) 5757 nqs = ctx->ifc_sctx->isc_nrxqs; 5758 break; 5759 } 5760 if (nqs == 0) 5761 nqs = 8; 5762 5763 for (i=0; i<8; i++) { 5764 if (i >= nqs) 5765 break; 5766 if (i) 5767 strcat(buf, ","); 5768 sprintf(strchr(buf, 0), "%d", ndesc[i]); 5769 } 5770 5771 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 5772 if (rc || req->newptr == NULL) 5773 return rc; 5774 5775 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 5776 i++, p = strsep(&next, " ,")) { 5777 ndesc[i] = strtoul(p, NULL, 10); 5778 } 5779 5780 return(rc); 5781 } 5782 5783 #define NAME_BUFLEN 32 5784 static void 5785 iflib_add_device_sysctl_pre(if_ctx_t ctx) 5786 { 5787 device_t dev = iflib_get_dev(ctx); 5788 struct sysctl_oid_list *child, *oid_list; 5789 struct sysctl_ctx_list *ctx_list; 5790 struct sysctl_oid *node; 5791 5792 ctx_list = device_get_sysctl_ctx(dev); 5793 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 5794 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 5795 CTLFLAG_RD, NULL, "IFLIB fields"); 5796 oid_list = SYSCTL_CHILDREN(node); 5797 5798 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 5799 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 5800 "driver version"); 5801 5802 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 5803 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 5804 "# of txqs to use, 0 => use default #"); 5805 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 5806 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 5807 "# of rxqs to use, 0 => use default #"); 5808 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 5809 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 5810 "permit #txq != #rxq"); 5811 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 5812 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 5813 "disable MSIX (default 0)"); 5814 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 5815 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 5816 "set the rx budget"); 5817 5818 /* XXX change for per-queue sizes */ 5819 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 5820 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 5821 mp_ndesc_handler, "A", 5822 "list of # of tx descriptors to use, 0 = use default #"); 5823 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 5824 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 5825 mp_ndesc_handler, "A", 5826 "list of # of rx descriptors to use, 0 = use default #"); 5827 } 5828 5829 static void 5830 iflib_add_device_sysctl_post(if_ctx_t ctx) 5831 { 5832 if_shared_ctx_t sctx = ctx->ifc_sctx; 5833 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5834 device_t dev = iflib_get_dev(ctx); 5835 struct sysctl_oid_list *child; 5836 struct sysctl_ctx_list *ctx_list; 5837 iflib_fl_t fl; 5838 iflib_txq_t txq; 5839 iflib_rxq_t rxq; 5840 int i, j; 5841 char namebuf[NAME_BUFLEN]; 5842 char *qfmt; 5843 struct sysctl_oid *queue_node, *fl_node, *node; 5844 struct sysctl_oid_list *queue_list, *fl_list; 5845 ctx_list = device_get_sysctl_ctx(dev); 5846 5847 node = ctx->ifc_sysctl_node; 5848 child = SYSCTL_CHILDREN(node); 5849 5850 if (scctx->isc_ntxqsets > 100) 5851 qfmt = "txq%03d"; 5852 else if (scctx->isc_ntxqsets > 10) 5853 qfmt = "txq%02d"; 5854 else 5855 qfmt = "txq%d"; 5856 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 5857 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5858 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5859 CTLFLAG_RD, NULL, "Queue Name"); 5860 queue_list = SYSCTL_CHILDREN(queue_node); 5861 #if MEMORY_LOGGING 5862 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 5863 CTLFLAG_RD, 5864 &txq->ift_dequeued, "total mbufs freed"); 5865 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 5866 CTLFLAG_RD, 5867 &txq->ift_enqueued, "total mbufs enqueued"); 5868 #endif 5869 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 5870 CTLFLAG_RD, 5871 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 5872 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 5873 CTLFLAG_RD, 5874 &txq->ift_pullups, "# of times m_pullup was called"); 5875 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 5876 CTLFLAG_RD, 5877 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 5878 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 5879 CTLFLAG_RD, 5880 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 5881 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 5882 CTLFLAG_RD, 5883 &txq->ift_map_failed, "# of times dma map failed"); 5884 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 5885 CTLFLAG_RD, 5886 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 5887 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 5888 CTLFLAG_RD, 5889 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 5890 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 5891 CTLFLAG_RD, 5892 &txq->ift_pidx, 1, "Producer Index"); 5893 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 5894 CTLFLAG_RD, 5895 &txq->ift_cidx, 1, "Consumer Index"); 5896 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 5897 CTLFLAG_RD, 5898 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 5899 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 5900 CTLFLAG_RD, 5901 &txq->ift_in_use, 1, "descriptors in use"); 5902 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 5903 CTLFLAG_RD, 5904 &txq->ift_processed, "descriptors procesed for clean"); 5905 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 5906 CTLFLAG_RD, 5907 &txq->ift_cleaned, "total cleaned"); 5908 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 5909 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 5910 0, mp_ring_state_handler, "A", "soft ring state"); 5911 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 5912 CTLFLAG_RD, &txq->ift_br->enqueues, 5913 "# of enqueues to the mp_ring for this queue"); 5914 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 5915 CTLFLAG_RD, &txq->ift_br->drops, 5916 "# of drops in the mp_ring for this queue"); 5917 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 5918 CTLFLAG_RD, &txq->ift_br->starts, 5919 "# of normal consumer starts in the mp_ring for this queue"); 5920 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 5921 CTLFLAG_RD, &txq->ift_br->stalls, 5922 "# of consumer stalls in the mp_ring for this queue"); 5923 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 5924 CTLFLAG_RD, &txq->ift_br->restarts, 5925 "# of consumer restarts in the mp_ring for this queue"); 5926 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 5927 CTLFLAG_RD, &txq->ift_br->abdications, 5928 "# of consumer abdications in the mp_ring for this queue"); 5929 } 5930 5931 if (scctx->isc_nrxqsets > 100) 5932 qfmt = "rxq%03d"; 5933 else if (scctx->isc_nrxqsets > 10) 5934 qfmt = "rxq%02d"; 5935 else 5936 qfmt = "rxq%d"; 5937 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 5938 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5939 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5940 CTLFLAG_RD, NULL, "Queue Name"); 5941 queue_list = SYSCTL_CHILDREN(queue_node); 5942 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5943 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 5944 CTLFLAG_RD, 5945 &rxq->ifr_cq_pidx, 1, "Producer Index"); 5946 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 5947 CTLFLAG_RD, 5948 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 5949 } 5950 5951 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 5952 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 5953 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 5954 CTLFLAG_RD, NULL, "freelist Name"); 5955 fl_list = SYSCTL_CHILDREN(fl_node); 5956 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 5957 CTLFLAG_RD, 5958 &fl->ifl_pidx, 1, "Producer Index"); 5959 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 5960 CTLFLAG_RD, 5961 &fl->ifl_cidx, 1, "Consumer Index"); 5962 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 5963 CTLFLAG_RD, 5964 &fl->ifl_credits, 1, "credits available"); 5965 #if MEMORY_LOGGING 5966 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 5967 CTLFLAG_RD, 5968 &fl->ifl_m_enqueued, "mbufs allocated"); 5969 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 5970 CTLFLAG_RD, 5971 &fl->ifl_m_dequeued, "mbufs freed"); 5972 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 5973 CTLFLAG_RD, 5974 &fl->ifl_cl_enqueued, "clusters allocated"); 5975 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 5976 CTLFLAG_RD, 5977 &fl->ifl_cl_dequeued, "clusters freed"); 5978 #endif 5979 5980 } 5981 } 5982 5983 } 5984 5985 #ifndef __NO_STRICT_ALIGNMENT 5986 static struct mbuf * 5987 iflib_fixup_rx(struct mbuf *m) 5988 { 5989 struct mbuf *n; 5990 5991 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 5992 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 5993 m->m_data += ETHER_HDR_LEN; 5994 n = m; 5995 } else { 5996 MGETHDR(n, M_NOWAIT, MT_DATA); 5997 if (n == NULL) { 5998 m_freem(m); 5999 return (NULL); 6000 } 6001 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6002 m->m_data += ETHER_HDR_LEN; 6003 m->m_len -= ETHER_HDR_LEN; 6004 n->m_len = ETHER_HDR_LEN; 6005 M_MOVE_PKTHDR(n, m); 6006 n->m_next = m; 6007 } 6008 return (n); 6009 } 6010 #endif 6011