1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/pfil.h> 63 #include <net/vnet.h> 64 65 #include <netinet/in.h> 66 #include <netinet/in_pcb.h> 67 #include <netinet/tcp_lro.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/if_ether.h> 70 #include <netinet/ip.h> 71 #include <netinet/ip6.h> 72 #include <netinet/tcp.h> 73 #include <netinet/ip_var.h> 74 #include <netinet/netdump/netdump.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 120 /* 121 * File organization: 122 * - private structures 123 * - iflib private utility functions 124 * - ifnet functions 125 * - vlan registry and other exported functions 126 * - iflib public core functions 127 * 128 * 129 */ 130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 131 132 struct iflib_txq; 133 typedef struct iflib_txq *iflib_txq_t; 134 struct iflib_rxq; 135 typedef struct iflib_rxq *iflib_rxq_t; 136 struct iflib_fl; 137 typedef struct iflib_fl *iflib_fl_t; 138 139 struct iflib_ctx; 140 141 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 142 static void iflib_timer(void *arg); 143 144 typedef struct iflib_filter_info { 145 driver_filter_t *ifi_filter; 146 void *ifi_filter_arg; 147 struct grouptask *ifi_task; 148 void *ifi_ctx; 149 } *iflib_filter_info_t; 150 151 struct iflib_ctx { 152 KOBJ_FIELDS; 153 /* 154 * Pointer to hardware driver's softc 155 */ 156 void *ifc_softc; 157 device_t ifc_dev; 158 if_t ifc_ifp; 159 160 cpuset_t ifc_cpus; 161 if_shared_ctx_t ifc_sctx; 162 struct if_softc_ctx ifc_softc_ctx; 163 164 struct sx ifc_ctx_sx; 165 struct mtx ifc_state_mtx; 166 167 iflib_txq_t ifc_txqs; 168 iflib_rxq_t ifc_rxqs; 169 uint32_t ifc_if_flags; 170 uint32_t ifc_flags; 171 uint32_t ifc_max_fl_buf_size; 172 uint32_t ifc_rx_mbuf_sz; 173 174 int ifc_link_state; 175 int ifc_watchdog_events; 176 struct cdev *ifc_led_dev; 177 struct resource *ifc_msix_mem; 178 179 struct if_irq ifc_legacy_irq; 180 struct grouptask ifc_admin_task; 181 struct grouptask ifc_vflr_task; 182 struct iflib_filter_info ifc_filter_info; 183 struct ifmedia ifc_media; 184 struct ifmedia *ifc_mediap; 185 186 struct sysctl_oid *ifc_sysctl_node; 187 uint16_t ifc_sysctl_ntxqs; 188 uint16_t ifc_sysctl_nrxqs; 189 uint16_t ifc_sysctl_qs_eq_override; 190 uint16_t ifc_sysctl_rx_budget; 191 uint16_t ifc_sysctl_tx_abdicate; 192 uint16_t ifc_sysctl_core_offset; 193 #define CORE_OFFSET_UNSPECIFIED 0xffff 194 uint8_t ifc_sysctl_separate_txrx; 195 196 qidx_t ifc_sysctl_ntxds[8]; 197 qidx_t ifc_sysctl_nrxds[8]; 198 struct if_txrx ifc_txrx; 199 #define isc_txd_encap ifc_txrx.ift_txd_encap 200 #define isc_txd_flush ifc_txrx.ift_txd_flush 201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 202 #define isc_rxd_available ifc_txrx.ift_rxd_available 203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 209 eventhandler_tag ifc_vlan_attach_event; 210 eventhandler_tag ifc_vlan_detach_event; 211 struct ether_addr ifc_mac; 212 }; 213 214 void * 215 iflib_get_softc(if_ctx_t ctx) 216 { 217 218 return (ctx->ifc_softc); 219 } 220 221 device_t 222 iflib_get_dev(if_ctx_t ctx) 223 { 224 225 return (ctx->ifc_dev); 226 } 227 228 if_t 229 iflib_get_ifp(if_ctx_t ctx) 230 { 231 232 return (ctx->ifc_ifp); 233 } 234 235 struct ifmedia * 236 iflib_get_media(if_ctx_t ctx) 237 { 238 239 return (ctx->ifc_mediap); 240 } 241 242 uint32_t 243 iflib_get_flags(if_ctx_t ctx) 244 { 245 return (ctx->ifc_flags); 246 } 247 248 void 249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 250 { 251 252 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 253 } 254 255 if_softc_ctx_t 256 iflib_get_softc_ctx(if_ctx_t ctx) 257 { 258 259 return (&ctx->ifc_softc_ctx); 260 } 261 262 if_shared_ctx_t 263 iflib_get_sctx(if_ctx_t ctx) 264 { 265 266 return (ctx->ifc_sctx); 267 } 268 269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 272 273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 275 276 typedef struct iflib_sw_rx_desc_array { 277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 278 struct mbuf **ifsd_m; /* pkthdr mbufs */ 279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 281 } iflib_rxsd_array_t; 282 283 typedef struct iflib_sw_tx_desc_array { 284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 286 struct mbuf **ifsd_m; /* pkthdr mbufs */ 287 } if_txsd_vec_t; 288 289 /* magic number that should be high enough for any hardware */ 290 #define IFLIB_MAX_TX_SEGS 128 291 #define IFLIB_RX_COPY_THRESH 128 292 #define IFLIB_MAX_RX_REFRESH 32 293 /* The minimum descriptors per second before we start coalescing */ 294 #define IFLIB_MIN_DESC_SEC 16384 295 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 296 #define IFLIB_QUEUE_IDLE 0 297 #define IFLIB_QUEUE_HUNG 1 298 #define IFLIB_QUEUE_WORKING 2 299 /* maximum number of txqs that can share an rx interrupt */ 300 #define IFLIB_MAX_TX_SHARED_INTR 4 301 302 /* this should really scale with ring size - this is a fairly arbitrary value */ 303 #define TX_BATCH_SIZE 32 304 305 #define IFLIB_RESTART_BUDGET 8 306 307 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 308 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 309 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 310 311 struct iflib_txq { 312 qidx_t ift_in_use; 313 qidx_t ift_cidx; 314 qidx_t ift_cidx_processed; 315 qidx_t ift_pidx; 316 uint8_t ift_gen; 317 uint8_t ift_br_offset; 318 uint16_t ift_npending; 319 uint16_t ift_db_pending; 320 uint16_t ift_rs_pending; 321 /* implicit pad */ 322 uint8_t ift_txd_size[8]; 323 uint64_t ift_processed; 324 uint64_t ift_cleaned; 325 uint64_t ift_cleaned_prev; 326 #if MEMORY_LOGGING 327 uint64_t ift_enqueued; 328 uint64_t ift_dequeued; 329 #endif 330 uint64_t ift_no_tx_dma_setup; 331 uint64_t ift_no_desc_avail; 332 uint64_t ift_mbuf_defrag_failed; 333 uint64_t ift_mbuf_defrag; 334 uint64_t ift_map_failed; 335 uint64_t ift_txd_encap_efbig; 336 uint64_t ift_pullups; 337 uint64_t ift_last_timer_tick; 338 339 struct mtx ift_mtx; 340 struct mtx ift_db_mtx; 341 342 /* constant values */ 343 if_ctx_t ift_ctx; 344 struct ifmp_ring *ift_br; 345 struct grouptask ift_task; 346 qidx_t ift_size; 347 uint16_t ift_id; 348 struct callout ift_timer; 349 350 if_txsd_vec_t ift_sds; 351 uint8_t ift_qstatus; 352 uint8_t ift_closed; 353 uint8_t ift_update_freq; 354 struct iflib_filter_info ift_filter_info; 355 bus_dma_tag_t ift_buf_tag; 356 bus_dma_tag_t ift_tso_buf_tag; 357 iflib_dma_info_t ift_ifdi; 358 #define MTX_NAME_LEN 16 359 char ift_mtx_name[MTX_NAME_LEN]; 360 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 361 #ifdef IFLIB_DIAGNOSTICS 362 uint64_t ift_cpu_exec_count[256]; 363 #endif 364 } __aligned(CACHE_LINE_SIZE); 365 366 struct iflib_fl { 367 qidx_t ifl_cidx; 368 qidx_t ifl_pidx; 369 qidx_t ifl_credits; 370 uint8_t ifl_gen; 371 uint8_t ifl_rxd_size; 372 #if MEMORY_LOGGING 373 uint64_t ifl_m_enqueued; 374 uint64_t ifl_m_dequeued; 375 uint64_t ifl_cl_enqueued; 376 uint64_t ifl_cl_dequeued; 377 #endif 378 /* implicit pad */ 379 bitstr_t *ifl_rx_bitmap; 380 qidx_t ifl_fragidx; 381 /* constant */ 382 qidx_t ifl_size; 383 uint16_t ifl_buf_size; 384 uint16_t ifl_cltype; 385 uma_zone_t ifl_zone; 386 iflib_rxsd_array_t ifl_sds; 387 iflib_rxq_t ifl_rxq; 388 uint8_t ifl_id; 389 bus_dma_tag_t ifl_buf_tag; 390 iflib_dma_info_t ifl_ifdi; 391 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 392 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 393 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 394 } __aligned(CACHE_LINE_SIZE); 395 396 static inline qidx_t 397 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 398 { 399 qidx_t used; 400 401 if (pidx > cidx) 402 used = pidx - cidx; 403 else if (pidx < cidx) 404 used = size - cidx + pidx; 405 else if (gen == 0 && pidx == cidx) 406 used = 0; 407 else if (gen == 1 && pidx == cidx) 408 used = size; 409 else 410 panic("bad state"); 411 412 return (used); 413 } 414 415 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 416 417 #define IDXDIFF(head, tail, wrap) \ 418 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 419 420 struct iflib_rxq { 421 if_ctx_t ifr_ctx; 422 iflib_fl_t ifr_fl; 423 uint64_t ifr_rx_irq; 424 struct pfil_head *pfil; 425 /* 426 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 427 * the command queue consumer index. Otherwise it's unused. 428 */ 429 qidx_t ifr_cq_cidx; 430 uint16_t ifr_id; 431 uint8_t ifr_nfl; 432 uint8_t ifr_ntxqirq; 433 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 434 uint8_t ifr_fl_offset; 435 struct lro_ctrl ifr_lc; 436 struct grouptask ifr_task; 437 struct iflib_filter_info ifr_filter_info; 438 iflib_dma_info_t ifr_ifdi; 439 440 /* dynamically allocate if any drivers need a value substantially larger than this */ 441 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 442 #ifdef IFLIB_DIAGNOSTICS 443 uint64_t ifr_cpu_exec_count[256]; 444 #endif 445 } __aligned(CACHE_LINE_SIZE); 446 447 typedef struct if_rxsd { 448 caddr_t *ifsd_cl; 449 iflib_fl_t ifsd_fl; 450 qidx_t ifsd_cidx; 451 } *if_rxsd_t; 452 453 /* multiple of word size */ 454 #ifdef __LP64__ 455 #define PKT_INFO_SIZE 6 456 #define RXD_INFO_SIZE 5 457 #define PKT_TYPE uint64_t 458 #else 459 #define PKT_INFO_SIZE 11 460 #define RXD_INFO_SIZE 8 461 #define PKT_TYPE uint32_t 462 #endif 463 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 464 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 465 466 typedef struct if_pkt_info_pad { 467 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 468 } *if_pkt_info_pad_t; 469 typedef struct if_rxd_info_pad { 470 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 471 } *if_rxd_info_pad_t; 472 473 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 474 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 475 476 477 static inline void 478 pkt_info_zero(if_pkt_info_t pi) 479 { 480 if_pkt_info_pad_t pi_pad; 481 482 pi_pad = (if_pkt_info_pad_t)pi; 483 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 484 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 485 #ifndef __LP64__ 486 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 487 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 488 #endif 489 } 490 491 static device_method_t iflib_pseudo_methods[] = { 492 DEVMETHOD(device_attach, noop_attach), 493 DEVMETHOD(device_detach, iflib_pseudo_detach), 494 DEVMETHOD_END 495 }; 496 497 driver_t iflib_pseudodriver = { 498 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 499 }; 500 501 static inline void 502 rxd_info_zero(if_rxd_info_t ri) 503 { 504 if_rxd_info_pad_t ri_pad; 505 int i; 506 507 ri_pad = (if_rxd_info_pad_t)ri; 508 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 509 ri_pad->rxd_val[i] = 0; 510 ri_pad->rxd_val[i+1] = 0; 511 ri_pad->rxd_val[i+2] = 0; 512 ri_pad->rxd_val[i+3] = 0; 513 } 514 #ifdef __LP64__ 515 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 516 #endif 517 } 518 519 /* 520 * Only allow a single packet to take up most 1/nth of the tx ring 521 */ 522 #define MAX_SINGLE_PACKET_FRACTION 12 523 #define IF_BAD_DMA (bus_addr_t)-1 524 525 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 526 527 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 528 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 529 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 530 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 531 532 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 533 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 534 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 535 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 536 537 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 538 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 539 540 void 541 iflib_set_detach(if_ctx_t ctx) 542 { 543 STATE_LOCK(ctx); 544 ctx->ifc_flags |= IFC_IN_DETACH; 545 STATE_UNLOCK(ctx); 546 } 547 548 /* Our boot-time initialization hook */ 549 static int iflib_module_event_handler(module_t, int, void *); 550 551 static moduledata_t iflib_moduledata = { 552 "iflib", 553 iflib_module_event_handler, 554 NULL 555 }; 556 557 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 558 MODULE_VERSION(iflib, 1); 559 560 MODULE_DEPEND(iflib, pci, 1, 1, 1); 561 MODULE_DEPEND(iflib, ether, 1, 1, 1); 562 563 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 564 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 565 566 #ifndef IFLIB_DEBUG_COUNTERS 567 #ifdef INVARIANTS 568 #define IFLIB_DEBUG_COUNTERS 1 569 #else 570 #define IFLIB_DEBUG_COUNTERS 0 571 #endif /* !INVARIANTS */ 572 #endif 573 574 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 575 "iflib driver parameters"); 576 577 /* 578 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 579 */ 580 static int iflib_min_tx_latency = 0; 581 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 582 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 583 static int iflib_no_tx_batch = 0; 584 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 585 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 586 587 588 #if IFLIB_DEBUG_COUNTERS 589 590 static int iflib_tx_seen; 591 static int iflib_tx_sent; 592 static int iflib_tx_encap; 593 static int iflib_rx_allocs; 594 static int iflib_fl_refills; 595 static int iflib_fl_refills_large; 596 static int iflib_tx_frees; 597 598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 599 &iflib_tx_seen, 0, "# TX mbufs seen"); 600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 601 &iflib_tx_sent, 0, "# TX mbufs sent"); 602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 603 &iflib_tx_encap, 0, "# TX mbufs encapped"); 604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 605 &iflib_tx_frees, 0, "# TX frees"); 606 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 607 &iflib_rx_allocs, 0, "# RX allocations"); 608 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 609 &iflib_fl_refills, 0, "# refills"); 610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 611 &iflib_fl_refills_large, 0, "# large refills"); 612 613 614 static int iflib_txq_drain_flushing; 615 static int iflib_txq_drain_oactive; 616 static int iflib_txq_drain_notready; 617 618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 619 &iflib_txq_drain_flushing, 0, "# drain flushes"); 620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 621 &iflib_txq_drain_oactive, 0, "# drain oactives"); 622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 623 &iflib_txq_drain_notready, 0, "# drain notready"); 624 625 626 static int iflib_encap_load_mbuf_fail; 627 static int iflib_encap_pad_mbuf_fail; 628 static int iflib_encap_txq_avail_fail; 629 static int iflib_encap_txd_encap_fail; 630 631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 632 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 634 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 636 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 638 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 639 640 static int iflib_task_fn_rxs; 641 static int iflib_rx_intr_enables; 642 static int iflib_fast_intrs; 643 static int iflib_rx_unavail; 644 static int iflib_rx_ctx_inactive; 645 static int iflib_rx_if_input; 646 static int iflib_rxd_flush; 647 648 static int iflib_verbose_debug; 649 650 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 651 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 652 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 653 &iflib_rx_intr_enables, 0, "# RX intr enables"); 654 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 655 &iflib_fast_intrs, 0, "# fast_intr calls"); 656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 657 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 659 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 661 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 663 &iflib_rxd_flush, 0, "# times rxd_flush called"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 665 &iflib_verbose_debug, 0, "enable verbose debugging"); 666 667 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 668 static void 669 iflib_debug_reset(void) 670 { 671 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 672 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 673 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 674 iflib_txq_drain_notready = 675 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 676 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 677 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 678 iflib_rx_unavail = 679 iflib_rx_ctx_inactive = iflib_rx_if_input = 680 iflib_rxd_flush = 0; 681 } 682 683 #else 684 #define DBG_COUNTER_INC(name) 685 static void iflib_debug_reset(void) {} 686 #endif 687 688 #define IFLIB_DEBUG 0 689 690 static void iflib_tx_structures_free(if_ctx_t ctx); 691 static void iflib_rx_structures_free(if_ctx_t ctx); 692 static int iflib_queues_alloc(if_ctx_t ctx); 693 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 694 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 695 static int iflib_qset_structures_setup(if_ctx_t ctx); 696 static int iflib_msix_init(if_ctx_t ctx); 697 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 698 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 699 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 700 #ifdef ALTQ 701 static void iflib_altq_if_start(if_t ifp); 702 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 703 #endif 704 static int iflib_register(if_ctx_t); 705 static void iflib_init_locked(if_ctx_t ctx); 706 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 707 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 708 static void iflib_ifmp_purge(iflib_txq_t txq); 709 static void _iflib_pre_assert(if_softc_ctx_t scctx); 710 static void iflib_if_init_locked(if_ctx_t ctx); 711 static void iflib_free_intr_mem(if_ctx_t ctx); 712 #ifndef __NO_STRICT_ALIGNMENT 713 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 714 #endif 715 716 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 717 SLIST_HEAD_INITIALIZER(cpu_offsets); 718 struct cpu_offset { 719 SLIST_ENTRY(cpu_offset) entries; 720 cpuset_t set; 721 unsigned int refcount; 722 uint16_t offset; 723 }; 724 static struct mtx cpu_offset_mtx; 725 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 726 MTX_DEF); 727 728 NETDUMP_DEFINE(iflib); 729 730 #ifdef DEV_NETMAP 731 #include <sys/selinfo.h> 732 #include <net/netmap.h> 733 #include <dev/netmap/netmap_kern.h> 734 735 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 736 737 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 738 739 /* 740 * device-specific sysctl variables: 741 * 742 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 743 * During regular operations the CRC is stripped, but on some 744 * hardware reception of frames not multiple of 64 is slower, 745 * so using crcstrip=0 helps in benchmarks. 746 * 747 * iflib_rx_miss, iflib_rx_miss_bufs: 748 * count packets that might be missed due to lost interrupts. 749 */ 750 SYSCTL_DECL(_dev_netmap); 751 /* 752 * The xl driver by default strips CRCs and we do not override it. 753 */ 754 755 int iflib_crcstrip = 1; 756 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 757 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 758 759 int iflib_rx_miss, iflib_rx_miss_bufs; 760 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 761 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 763 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 764 765 /* 766 * Register/unregister. We are already under netmap lock. 767 * Only called on the first register or the last unregister. 768 */ 769 static int 770 iflib_netmap_register(struct netmap_adapter *na, int onoff) 771 { 772 if_t ifp = na->ifp; 773 if_ctx_t ctx = ifp->if_softc; 774 int status; 775 776 CTX_LOCK(ctx); 777 IFDI_INTR_DISABLE(ctx); 778 779 /* Tell the stack that the interface is no longer active */ 780 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 781 782 if (!CTX_IS_VF(ctx)) 783 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 784 785 /* enable or disable flags and callbacks in na and ifp */ 786 if (onoff) { 787 nm_set_native_flags(na); 788 } else { 789 nm_clear_native_flags(na); 790 } 791 iflib_stop(ctx); 792 iflib_init_locked(ctx); 793 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 794 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 795 if (status) 796 nm_clear_native_flags(na); 797 CTX_UNLOCK(ctx); 798 return (status); 799 } 800 801 static int 802 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 803 { 804 struct netmap_adapter *na = kring->na; 805 u_int const lim = kring->nkr_num_slots - 1; 806 u_int head = kring->rhead; 807 struct netmap_ring *ring = kring->ring; 808 bus_dmamap_t *map; 809 struct if_rxd_update iru; 810 if_ctx_t ctx = rxq->ifr_ctx; 811 iflib_fl_t fl = &rxq->ifr_fl[0]; 812 uint32_t refill_pidx, nic_i; 813 #if IFLIB_DEBUG_COUNTERS 814 int rf_count = 0; 815 #endif 816 817 if (nm_i == head && __predict_true(!init)) 818 return 0; 819 iru_init(&iru, rxq, 0 /* flid */); 820 map = fl->ifl_sds.ifsd_map; 821 refill_pidx = netmap_idx_k2n(kring, nm_i); 822 /* 823 * IMPORTANT: we must leave one free slot in the ring, 824 * so move head back by one unit 825 */ 826 head = nm_prev(head, lim); 827 nic_i = UINT_MAX; 828 DBG_COUNTER_INC(fl_refills); 829 while (nm_i != head) { 830 #if IFLIB_DEBUG_COUNTERS 831 if (++rf_count == 9) 832 DBG_COUNTER_INC(fl_refills_large); 833 #endif 834 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 835 struct netmap_slot *slot = &ring->slot[nm_i]; 836 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 837 uint32_t nic_i_dma = refill_pidx; 838 nic_i = netmap_idx_k2n(kring, nm_i); 839 840 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 841 842 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 843 return netmap_ring_reinit(kring); 844 845 fl->ifl_vm_addrs[tmp_pidx] = addr; 846 if (__predict_false(init)) { 847 netmap_load_map(na, fl->ifl_buf_tag, 848 map[nic_i], addr); 849 } else if (slot->flags & NS_BUF_CHANGED) { 850 /* buffer has changed, reload map */ 851 netmap_reload_map(na, fl->ifl_buf_tag, 852 map[nic_i], addr); 853 } 854 slot->flags &= ~NS_BUF_CHANGED; 855 856 nm_i = nm_next(nm_i, lim); 857 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 858 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 859 continue; 860 861 iru.iru_pidx = refill_pidx; 862 iru.iru_count = tmp_pidx+1; 863 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 864 refill_pidx = nic_i; 865 for (int n = 0; n < iru.iru_count; n++) { 866 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma], 867 BUS_DMASYNC_PREREAD); 868 /* XXX - change this to not use the netmap func*/ 869 nic_i_dma = nm_next(nic_i_dma, lim); 870 } 871 } 872 } 873 kring->nr_hwcur = head; 874 875 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 876 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 877 if (__predict_true(nic_i != UINT_MAX)) { 878 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 879 DBG_COUNTER_INC(rxd_flush); 880 } 881 return (0); 882 } 883 884 /* 885 * Reconcile kernel and user view of the transmit ring. 886 * 887 * All information is in the kring. 888 * Userspace wants to send packets up to the one before kring->rhead, 889 * kernel knows kring->nr_hwcur is the first unsent packet. 890 * 891 * Here we push packets out (as many as possible), and possibly 892 * reclaim buffers from previously completed transmission. 893 * 894 * The caller (netmap) guarantees that there is only one instance 895 * running at any time. Any interference with other driver 896 * methods should be handled by the individual drivers. 897 */ 898 static int 899 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 900 { 901 struct netmap_adapter *na = kring->na; 902 if_t ifp = na->ifp; 903 struct netmap_ring *ring = kring->ring; 904 u_int nm_i; /* index into the netmap kring */ 905 u_int nic_i; /* index into the NIC ring */ 906 u_int n; 907 u_int const lim = kring->nkr_num_slots - 1; 908 u_int const head = kring->rhead; 909 struct if_pkt_info pi; 910 911 /* 912 * interrupts on every tx packet are expensive so request 913 * them every half ring, or where NS_REPORT is set 914 */ 915 u_int report_frequency = kring->nkr_num_slots >> 1; 916 /* device-specific */ 917 if_ctx_t ctx = ifp->if_softc; 918 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 919 920 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 921 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 922 923 /* 924 * First part: process new packets to send. 925 * nm_i is the current index in the netmap kring, 926 * nic_i is the corresponding index in the NIC ring. 927 * 928 * If we have packets to send (nm_i != head) 929 * iterate over the netmap ring, fetch length and update 930 * the corresponding slot in the NIC ring. Some drivers also 931 * need to update the buffer's physical address in the NIC slot 932 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 933 * 934 * The netmap_reload_map() calls is especially expensive, 935 * even when (as in this case) the tag is 0, so do only 936 * when the buffer has actually changed. 937 * 938 * If possible do not set the report/intr bit on all slots, 939 * but only a few times per ring or when NS_REPORT is set. 940 * 941 * Finally, on 10G and faster drivers, it might be useful 942 * to prefetch the next slot and txr entry. 943 */ 944 945 nm_i = kring->nr_hwcur; 946 if (nm_i != head) { /* we have new packets to send */ 947 pkt_info_zero(&pi); 948 pi.ipi_segs = txq->ift_segs; 949 pi.ipi_qsidx = kring->ring_id; 950 nic_i = netmap_idx_k2n(kring, nm_i); 951 952 __builtin_prefetch(&ring->slot[nm_i]); 953 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 954 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 955 956 for (n = 0; nm_i != head; n++) { 957 struct netmap_slot *slot = &ring->slot[nm_i]; 958 u_int len = slot->len; 959 uint64_t paddr; 960 void *addr = PNMB(na, slot, &paddr); 961 int flags = (slot->flags & NS_REPORT || 962 nic_i == 0 || nic_i == report_frequency) ? 963 IPI_TX_INTR : 0; 964 965 /* device-specific */ 966 pi.ipi_len = len; 967 pi.ipi_segs[0].ds_addr = paddr; 968 pi.ipi_segs[0].ds_len = len; 969 pi.ipi_nsegs = 1; 970 pi.ipi_ndescs = 0; 971 pi.ipi_pidx = nic_i; 972 pi.ipi_flags = flags; 973 974 /* Fill the slot in the NIC ring. */ 975 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 976 DBG_COUNTER_INC(tx_encap); 977 978 /* prefetch for next round */ 979 __builtin_prefetch(&ring->slot[nm_i + 1]); 980 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 981 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 982 983 NM_CHECK_ADDR_LEN(na, addr, len); 984 985 if (slot->flags & NS_BUF_CHANGED) { 986 /* buffer has changed, reload map */ 987 netmap_reload_map(na, txq->ift_buf_tag, 988 txq->ift_sds.ifsd_map[nic_i], addr); 989 } 990 /* make sure changes to the buffer are synced */ 991 bus_dmamap_sync(txq->ift_buf_tag, 992 txq->ift_sds.ifsd_map[nic_i], 993 BUS_DMASYNC_PREWRITE); 994 995 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 996 nm_i = nm_next(nm_i, lim); 997 nic_i = nm_next(nic_i, lim); 998 } 999 kring->nr_hwcur = nm_i; 1000 1001 /* synchronize the NIC ring */ 1002 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1003 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1004 1005 /* (re)start the tx unit up to slot nic_i (excluded) */ 1006 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1007 } 1008 1009 /* 1010 * Second part: reclaim buffers for completed transmissions. 1011 * 1012 * If there are unclaimed buffers, attempt to reclaim them. 1013 * If none are reclaimed, and TX IRQs are not in use, do an initial 1014 * minimal delay, then trigger the tx handler which will spin in the 1015 * group task queue. 1016 */ 1017 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1018 if (iflib_tx_credits_update(ctx, txq)) { 1019 /* some tx completed, increment avail */ 1020 nic_i = txq->ift_cidx_processed; 1021 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1022 } 1023 } 1024 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1025 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1026 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1027 iflib_timer, txq, txq->ift_timer.c_cpu); 1028 } 1029 return (0); 1030 } 1031 1032 /* 1033 * Reconcile kernel and user view of the receive ring. 1034 * Same as for the txsync, this routine must be efficient. 1035 * The caller guarantees a single invocations, but races against 1036 * the rest of the driver should be handled here. 1037 * 1038 * On call, kring->rhead is the first packet that userspace wants 1039 * to keep, and kring->rcur is the wakeup point. 1040 * The kernel has previously reported packets up to kring->rtail. 1041 * 1042 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1043 * of whether or not we received an interrupt. 1044 */ 1045 static int 1046 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1047 { 1048 struct netmap_adapter *na = kring->na; 1049 struct netmap_ring *ring = kring->ring; 1050 if_t ifp = na->ifp; 1051 iflib_fl_t fl; 1052 uint32_t nm_i; /* index into the netmap ring */ 1053 uint32_t nic_i; /* index into the NIC ring */ 1054 u_int i, n; 1055 u_int const lim = kring->nkr_num_slots - 1; 1056 u_int const head = kring->rhead; 1057 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1058 struct if_rxd_info ri; 1059 1060 if_ctx_t ctx = ifp->if_softc; 1061 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1062 if (head > lim) 1063 return netmap_ring_reinit(kring); 1064 1065 /* 1066 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far. 1067 */ 1068 1069 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1070 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1071 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1072 } 1073 1074 /* 1075 * First part: import newly received packets. 1076 * 1077 * nm_i is the index of the next free slot in the netmap ring, 1078 * nic_i is the index of the next received packet in the NIC ring, 1079 * and they may differ in case if_init() has been called while 1080 * in netmap mode. For the receive ring we have 1081 * 1082 * nic_i = rxr->next_check; 1083 * nm_i = kring->nr_hwtail (previous) 1084 * and 1085 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1086 * 1087 * rxr->next_check is set to 0 on a ring reinit 1088 */ 1089 if (netmap_no_pendintr || force_update) { 1090 int crclen = iflib_crcstrip ? 0 : 4; 1091 int error, avail; 1092 1093 for (i = 0; i < rxq->ifr_nfl; i++) { 1094 fl = &rxq->ifr_fl[i]; 1095 nic_i = fl->ifl_cidx; 1096 nm_i = netmap_idx_n2k(kring, nic_i); 1097 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1098 rxq->ifr_id, nic_i, USHRT_MAX); 1099 for (n = 0; avail > 0; n++, avail--) { 1100 rxd_info_zero(&ri); 1101 ri.iri_frags = rxq->ifr_frags; 1102 ri.iri_qsidx = kring->ring_id; 1103 ri.iri_ifp = ctx->ifc_ifp; 1104 ri.iri_cidx = nic_i; 1105 1106 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1107 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1108 ring->slot[nm_i].flags = 0; 1109 bus_dmamap_sync(fl->ifl_buf_tag, 1110 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1111 nm_i = nm_next(nm_i, lim); 1112 nic_i = nm_next(nic_i, lim); 1113 } 1114 if (n) { /* update the state variables */ 1115 if (netmap_no_pendintr && !force_update) { 1116 /* diagnostics */ 1117 iflib_rx_miss ++; 1118 iflib_rx_miss_bufs += n; 1119 } 1120 fl->ifl_cidx = nic_i; 1121 kring->nr_hwtail = nm_i; 1122 } 1123 kring->nr_kflags &= ~NKR_PENDINTR; 1124 } 1125 } 1126 /* 1127 * Second part: skip past packets that userspace has released. 1128 * (kring->nr_hwcur to head excluded), 1129 * and make the buffers available for reception. 1130 * As usual nm_i is the index in the netmap ring, 1131 * nic_i is the index in the NIC ring, and 1132 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1133 */ 1134 /* XXX not sure how this will work with multiple free lists */ 1135 nm_i = kring->nr_hwcur; 1136 1137 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1138 } 1139 1140 static void 1141 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1142 { 1143 if_ctx_t ctx = na->ifp->if_softc; 1144 1145 CTX_LOCK(ctx); 1146 if (onoff) { 1147 IFDI_INTR_ENABLE(ctx); 1148 } else { 1149 IFDI_INTR_DISABLE(ctx); 1150 } 1151 CTX_UNLOCK(ctx); 1152 } 1153 1154 1155 static int 1156 iflib_netmap_attach(if_ctx_t ctx) 1157 { 1158 struct netmap_adapter na; 1159 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1160 1161 bzero(&na, sizeof(na)); 1162 1163 na.ifp = ctx->ifc_ifp; 1164 na.na_flags = NAF_BDG_MAYSLEEP; 1165 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1166 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1167 1168 na.num_tx_desc = scctx->isc_ntxd[0]; 1169 na.num_rx_desc = scctx->isc_nrxd[0]; 1170 na.nm_txsync = iflib_netmap_txsync; 1171 na.nm_rxsync = iflib_netmap_rxsync; 1172 na.nm_register = iflib_netmap_register; 1173 na.nm_intr = iflib_netmap_intr; 1174 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1175 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1176 return (netmap_attach(&na)); 1177 } 1178 1179 static void 1180 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1181 { 1182 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1183 struct netmap_slot *slot; 1184 1185 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1186 if (slot == NULL) 1187 return; 1188 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1189 1190 /* 1191 * In netmap mode, set the map for the packet buffer. 1192 * NOTE: Some drivers (not this one) also need to set 1193 * the physical buffer address in the NIC ring. 1194 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1195 * netmap slot index, si 1196 */ 1197 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1198 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1199 NMB(na, slot + si)); 1200 } 1201 } 1202 1203 static void 1204 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1205 { 1206 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1207 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1208 struct netmap_slot *slot; 1209 uint32_t nm_i; 1210 1211 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1212 if (slot == NULL) 1213 return; 1214 nm_i = netmap_idx_n2k(kring, 0); 1215 netmap_fl_refill(rxq, kring, nm_i, true); 1216 } 1217 1218 static void 1219 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on) 1220 { 1221 struct netmap_kring *kring; 1222 uint16_t txqid; 1223 1224 txqid = txq->ift_id; 1225 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1226 1227 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1228 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1229 BUS_DMASYNC_POSTREAD); 1230 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1231 netmap_tx_irq(ctx->ifc_ifp, txqid); 1232 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1233 if (hz < 2000) 1234 *reset_on = 1; 1235 else 1236 *reset_on = hz / 1000; 1237 } 1238 } 1239 } 1240 1241 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1242 1243 #else 1244 #define iflib_netmap_txq_init(ctx, txq) 1245 #define iflib_netmap_rxq_init(ctx, rxq) 1246 #define iflib_netmap_detach(ifp) 1247 1248 #define iflib_netmap_attach(ctx) (0) 1249 #define netmap_rx_irq(ifp, qid, budget) (0) 1250 #define netmap_tx_irq(ifp, qid) do {} while (0) 1251 #define iflib_netmap_timer_adjust(ctx, txq, reset_on) 1252 #endif 1253 1254 #if defined(__i386__) || defined(__amd64__) 1255 static __inline void 1256 prefetch(void *x) 1257 { 1258 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1259 } 1260 static __inline void 1261 prefetch2cachelines(void *x) 1262 { 1263 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1264 #if (CACHE_LINE_SIZE < 128) 1265 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1266 #endif 1267 } 1268 #else 1269 #define prefetch(x) 1270 #define prefetch2cachelines(x) 1271 #endif 1272 1273 static void 1274 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1275 { 1276 iflib_fl_t fl; 1277 1278 fl = &rxq->ifr_fl[flid]; 1279 iru->iru_paddrs = fl->ifl_bus_addrs; 1280 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1281 iru->iru_idxs = fl->ifl_rxd_idxs; 1282 iru->iru_qsidx = rxq->ifr_id; 1283 iru->iru_buf_size = fl->ifl_buf_size; 1284 iru->iru_flidx = fl->ifl_id; 1285 } 1286 1287 static void 1288 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1289 { 1290 if (err) 1291 return; 1292 *(bus_addr_t *) arg = segs[0].ds_addr; 1293 } 1294 1295 int 1296 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1297 { 1298 int err; 1299 device_t dev = ctx->ifc_dev; 1300 1301 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1302 align, 0, /* alignment, bounds */ 1303 BUS_SPACE_MAXADDR, /* lowaddr */ 1304 BUS_SPACE_MAXADDR, /* highaddr */ 1305 NULL, NULL, /* filter, filterarg */ 1306 size, /* maxsize */ 1307 1, /* nsegments */ 1308 size, /* maxsegsize */ 1309 BUS_DMA_ALLOCNOW, /* flags */ 1310 NULL, /* lockfunc */ 1311 NULL, /* lockarg */ 1312 &dma->idi_tag); 1313 if (err) { 1314 device_printf(dev, 1315 "%s: bus_dma_tag_create failed: %d\n", 1316 __func__, err); 1317 goto fail_0; 1318 } 1319 1320 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1321 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1322 if (err) { 1323 device_printf(dev, 1324 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1325 __func__, (uintmax_t)size, err); 1326 goto fail_1; 1327 } 1328 1329 dma->idi_paddr = IF_BAD_DMA; 1330 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1331 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1332 if (err || dma->idi_paddr == IF_BAD_DMA) { 1333 device_printf(dev, 1334 "%s: bus_dmamap_load failed: %d\n", 1335 __func__, err); 1336 goto fail_2; 1337 } 1338 1339 dma->idi_size = size; 1340 return (0); 1341 1342 fail_2: 1343 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1344 fail_1: 1345 bus_dma_tag_destroy(dma->idi_tag); 1346 fail_0: 1347 dma->idi_tag = NULL; 1348 1349 return (err); 1350 } 1351 1352 int 1353 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1354 { 1355 if_shared_ctx_t sctx = ctx->ifc_sctx; 1356 1357 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1358 1359 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1360 } 1361 1362 int 1363 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1364 { 1365 int i, err; 1366 iflib_dma_info_t *dmaiter; 1367 1368 dmaiter = dmalist; 1369 for (i = 0; i < count; i++, dmaiter++) { 1370 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1371 break; 1372 } 1373 if (err) 1374 iflib_dma_free_multi(dmalist, i); 1375 return (err); 1376 } 1377 1378 void 1379 iflib_dma_free(iflib_dma_info_t dma) 1380 { 1381 if (dma->idi_tag == NULL) 1382 return; 1383 if (dma->idi_paddr != IF_BAD_DMA) { 1384 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1385 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1386 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1387 dma->idi_paddr = IF_BAD_DMA; 1388 } 1389 if (dma->idi_vaddr != NULL) { 1390 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1391 dma->idi_vaddr = NULL; 1392 } 1393 bus_dma_tag_destroy(dma->idi_tag); 1394 dma->idi_tag = NULL; 1395 } 1396 1397 void 1398 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1399 { 1400 int i; 1401 iflib_dma_info_t *dmaiter = dmalist; 1402 1403 for (i = 0; i < count; i++, dmaiter++) 1404 iflib_dma_free(*dmaiter); 1405 } 1406 1407 #ifdef EARLY_AP_STARTUP 1408 static const int iflib_started = 1; 1409 #else 1410 /* 1411 * We used to abuse the smp_started flag to decide if the queues have been 1412 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1413 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1414 * is set. Run a SYSINIT() strictly after that to just set a usable 1415 * completion flag. 1416 */ 1417 1418 static int iflib_started; 1419 1420 static void 1421 iflib_record_started(void *arg) 1422 { 1423 iflib_started = 1; 1424 } 1425 1426 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1427 iflib_record_started, NULL); 1428 #endif 1429 1430 static int 1431 iflib_fast_intr(void *arg) 1432 { 1433 iflib_filter_info_t info = arg; 1434 struct grouptask *gtask = info->ifi_task; 1435 int result; 1436 1437 if (!iflib_started) 1438 return (FILTER_STRAY); 1439 1440 DBG_COUNTER_INC(fast_intrs); 1441 if (info->ifi_filter != NULL) { 1442 result = info->ifi_filter(info->ifi_filter_arg); 1443 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1444 return (result); 1445 } 1446 1447 GROUPTASK_ENQUEUE(gtask); 1448 return (FILTER_HANDLED); 1449 } 1450 1451 static int 1452 iflib_fast_intr_rxtx(void *arg) 1453 { 1454 iflib_filter_info_t info = arg; 1455 struct grouptask *gtask = info->ifi_task; 1456 if_ctx_t ctx; 1457 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1458 iflib_txq_t txq; 1459 void *sc; 1460 int i, cidx, result; 1461 qidx_t txqid; 1462 bool intr_enable, intr_legacy; 1463 1464 if (!iflib_started) 1465 return (FILTER_STRAY); 1466 1467 DBG_COUNTER_INC(fast_intrs); 1468 if (info->ifi_filter != NULL) { 1469 result = info->ifi_filter(info->ifi_filter_arg); 1470 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1471 return (result); 1472 } 1473 1474 ctx = rxq->ifr_ctx; 1475 sc = ctx->ifc_softc; 1476 intr_enable = false; 1477 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1478 MPASS(rxq->ifr_ntxqirq); 1479 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1480 txqid = rxq->ifr_txqid[i]; 1481 txq = &ctx->ifc_txqs[txqid]; 1482 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1483 BUS_DMASYNC_POSTREAD); 1484 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1485 if (intr_legacy) 1486 intr_enable = true; 1487 else 1488 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1489 continue; 1490 } 1491 GROUPTASK_ENQUEUE(&txq->ift_task); 1492 } 1493 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1494 cidx = rxq->ifr_cq_cidx; 1495 else 1496 cidx = rxq->ifr_fl[0].ifl_cidx; 1497 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1498 GROUPTASK_ENQUEUE(gtask); 1499 else { 1500 if (intr_legacy) 1501 intr_enable = true; 1502 else 1503 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1504 DBG_COUNTER_INC(rx_intr_enables); 1505 } 1506 if (intr_enable) 1507 IFDI_INTR_ENABLE(ctx); 1508 return (FILTER_HANDLED); 1509 } 1510 1511 1512 static int 1513 iflib_fast_intr_ctx(void *arg) 1514 { 1515 iflib_filter_info_t info = arg; 1516 struct grouptask *gtask = info->ifi_task; 1517 int result; 1518 1519 if (!iflib_started) 1520 return (FILTER_STRAY); 1521 1522 DBG_COUNTER_INC(fast_intrs); 1523 if (info->ifi_filter != NULL) { 1524 result = info->ifi_filter(info->ifi_filter_arg); 1525 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1526 return (result); 1527 } 1528 1529 GROUPTASK_ENQUEUE(gtask); 1530 return (FILTER_HANDLED); 1531 } 1532 1533 static int 1534 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1535 driver_filter_t filter, driver_intr_t handler, void *arg, 1536 const char *name) 1537 { 1538 struct resource *res; 1539 void *tag = NULL; 1540 device_t dev = ctx->ifc_dev; 1541 int flags, i, rc; 1542 1543 flags = RF_ACTIVE; 1544 if (ctx->ifc_flags & IFC_LEGACY) 1545 flags |= RF_SHAREABLE; 1546 MPASS(rid < 512); 1547 i = rid; 1548 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1549 if (res == NULL) { 1550 device_printf(dev, 1551 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1552 return (ENOMEM); 1553 } 1554 irq->ii_res = res; 1555 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1556 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1557 filter, handler, arg, &tag); 1558 if (rc != 0) { 1559 device_printf(dev, 1560 "failed to setup interrupt for rid %d, name %s: %d\n", 1561 rid, name ? name : "unknown", rc); 1562 return (rc); 1563 } else if (name) 1564 bus_describe_intr(dev, res, tag, "%s", name); 1565 1566 irq->ii_tag = tag; 1567 return (0); 1568 } 1569 1570 /********************************************************************* 1571 * 1572 * Allocate DMA resources for TX buffers as well as memory for the TX 1573 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1574 * iflib_sw_tx_desc_array structure, storing all the information that 1575 * is needed to transmit a packet on the wire. This is called only 1576 * once at attach, setup is done every reset. 1577 * 1578 **********************************************************************/ 1579 static int 1580 iflib_txsd_alloc(iflib_txq_t txq) 1581 { 1582 if_ctx_t ctx = txq->ift_ctx; 1583 if_shared_ctx_t sctx = ctx->ifc_sctx; 1584 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1585 device_t dev = ctx->ifc_dev; 1586 bus_size_t tsomaxsize; 1587 int err, nsegments, ntsosegments; 1588 bool tso; 1589 1590 nsegments = scctx->isc_tx_nsegments; 1591 ntsosegments = scctx->isc_tx_tso_segments_max; 1592 tsomaxsize = scctx->isc_tx_tso_size_max; 1593 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1594 tsomaxsize += sizeof(struct ether_vlan_header); 1595 MPASS(scctx->isc_ntxd[0] > 0); 1596 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1597 MPASS(nsegments > 0); 1598 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1599 MPASS(ntsosegments > 0); 1600 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1601 } 1602 1603 /* 1604 * Set up DMA tags for TX buffers. 1605 */ 1606 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1607 1, 0, /* alignment, bounds */ 1608 BUS_SPACE_MAXADDR, /* lowaddr */ 1609 BUS_SPACE_MAXADDR, /* highaddr */ 1610 NULL, NULL, /* filter, filterarg */ 1611 sctx->isc_tx_maxsize, /* maxsize */ 1612 nsegments, /* nsegments */ 1613 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1614 0, /* flags */ 1615 NULL, /* lockfunc */ 1616 NULL, /* lockfuncarg */ 1617 &txq->ift_buf_tag))) { 1618 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1619 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1620 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1621 goto fail; 1622 } 1623 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1624 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1625 1, 0, /* alignment, bounds */ 1626 BUS_SPACE_MAXADDR, /* lowaddr */ 1627 BUS_SPACE_MAXADDR, /* highaddr */ 1628 NULL, NULL, /* filter, filterarg */ 1629 tsomaxsize, /* maxsize */ 1630 ntsosegments, /* nsegments */ 1631 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1632 0, /* flags */ 1633 NULL, /* lockfunc */ 1634 NULL, /* lockfuncarg */ 1635 &txq->ift_tso_buf_tag))) { 1636 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1637 err); 1638 goto fail; 1639 } 1640 1641 /* Allocate memory for the TX mbuf map. */ 1642 if (!(txq->ift_sds.ifsd_m = 1643 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1644 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1645 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1646 err = ENOMEM; 1647 goto fail; 1648 } 1649 1650 /* 1651 * Create the DMA maps for TX buffers. 1652 */ 1653 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1654 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1655 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1656 device_printf(dev, 1657 "Unable to allocate TX buffer DMA map memory\n"); 1658 err = ENOMEM; 1659 goto fail; 1660 } 1661 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1662 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1663 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1664 device_printf(dev, 1665 "Unable to allocate TSO TX buffer map memory\n"); 1666 err = ENOMEM; 1667 goto fail; 1668 } 1669 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1670 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1671 &txq->ift_sds.ifsd_map[i]); 1672 if (err != 0) { 1673 device_printf(dev, "Unable to create TX DMA map\n"); 1674 goto fail; 1675 } 1676 if (!tso) 1677 continue; 1678 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1679 &txq->ift_sds.ifsd_tso_map[i]); 1680 if (err != 0) { 1681 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1682 goto fail; 1683 } 1684 } 1685 return (0); 1686 fail: 1687 /* We free all, it handles case where we are in the middle */ 1688 iflib_tx_structures_free(ctx); 1689 return (err); 1690 } 1691 1692 static void 1693 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1694 { 1695 bus_dmamap_t map; 1696 1697 map = NULL; 1698 if (txq->ift_sds.ifsd_map != NULL) 1699 map = txq->ift_sds.ifsd_map[i]; 1700 if (map != NULL) { 1701 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1702 bus_dmamap_unload(txq->ift_buf_tag, map); 1703 bus_dmamap_destroy(txq->ift_buf_tag, map); 1704 txq->ift_sds.ifsd_map[i] = NULL; 1705 } 1706 1707 map = NULL; 1708 if (txq->ift_sds.ifsd_tso_map != NULL) 1709 map = txq->ift_sds.ifsd_tso_map[i]; 1710 if (map != NULL) { 1711 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1712 BUS_DMASYNC_POSTWRITE); 1713 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1714 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1715 txq->ift_sds.ifsd_tso_map[i] = NULL; 1716 } 1717 } 1718 1719 static void 1720 iflib_txq_destroy(iflib_txq_t txq) 1721 { 1722 if_ctx_t ctx = txq->ift_ctx; 1723 1724 for (int i = 0; i < txq->ift_size; i++) 1725 iflib_txsd_destroy(ctx, txq, i); 1726 if (txq->ift_sds.ifsd_map != NULL) { 1727 free(txq->ift_sds.ifsd_map, M_IFLIB); 1728 txq->ift_sds.ifsd_map = NULL; 1729 } 1730 if (txq->ift_sds.ifsd_tso_map != NULL) { 1731 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1732 txq->ift_sds.ifsd_tso_map = NULL; 1733 } 1734 if (txq->ift_sds.ifsd_m != NULL) { 1735 free(txq->ift_sds.ifsd_m, M_IFLIB); 1736 txq->ift_sds.ifsd_m = NULL; 1737 } 1738 if (txq->ift_buf_tag != NULL) { 1739 bus_dma_tag_destroy(txq->ift_buf_tag); 1740 txq->ift_buf_tag = NULL; 1741 } 1742 if (txq->ift_tso_buf_tag != NULL) { 1743 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1744 txq->ift_tso_buf_tag = NULL; 1745 } 1746 } 1747 1748 static void 1749 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1750 { 1751 struct mbuf **mp; 1752 1753 mp = &txq->ift_sds.ifsd_m[i]; 1754 if (*mp == NULL) 1755 return; 1756 1757 if (txq->ift_sds.ifsd_map != NULL) { 1758 bus_dmamap_sync(txq->ift_buf_tag, 1759 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1760 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1761 } 1762 if (txq->ift_sds.ifsd_tso_map != NULL) { 1763 bus_dmamap_sync(txq->ift_tso_buf_tag, 1764 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1765 bus_dmamap_unload(txq->ift_tso_buf_tag, 1766 txq->ift_sds.ifsd_tso_map[i]); 1767 } 1768 m_free(*mp); 1769 DBG_COUNTER_INC(tx_frees); 1770 *mp = NULL; 1771 } 1772 1773 static int 1774 iflib_txq_setup(iflib_txq_t txq) 1775 { 1776 if_ctx_t ctx = txq->ift_ctx; 1777 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1778 if_shared_ctx_t sctx = ctx->ifc_sctx; 1779 iflib_dma_info_t di; 1780 int i; 1781 1782 /* Set number of descriptors available */ 1783 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1784 /* XXX make configurable */ 1785 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1786 1787 /* Reset indices */ 1788 txq->ift_cidx_processed = 0; 1789 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1790 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1791 1792 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1793 bzero((void *)di->idi_vaddr, di->idi_size); 1794 1795 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1796 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1797 bus_dmamap_sync(di->idi_tag, di->idi_map, 1798 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1799 return (0); 1800 } 1801 1802 /********************************************************************* 1803 * 1804 * Allocate DMA resources for RX buffers as well as memory for the RX 1805 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1806 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1807 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1808 * Since we use use one entry in iflib_sw_rx_desc_array per received 1809 * packet, the maximum number of entries we'll need is equal to the 1810 * number of hardware receive descriptors that we've allocated. 1811 * 1812 **********************************************************************/ 1813 static int 1814 iflib_rxsd_alloc(iflib_rxq_t rxq) 1815 { 1816 if_ctx_t ctx = rxq->ifr_ctx; 1817 if_shared_ctx_t sctx = ctx->ifc_sctx; 1818 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1819 device_t dev = ctx->ifc_dev; 1820 iflib_fl_t fl; 1821 int err; 1822 1823 MPASS(scctx->isc_nrxd[0] > 0); 1824 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1825 1826 fl = rxq->ifr_fl; 1827 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1828 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1829 /* Set up DMA tag for RX buffers. */ 1830 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1831 1, 0, /* alignment, bounds */ 1832 BUS_SPACE_MAXADDR, /* lowaddr */ 1833 BUS_SPACE_MAXADDR, /* highaddr */ 1834 NULL, NULL, /* filter, filterarg */ 1835 sctx->isc_rx_maxsize, /* maxsize */ 1836 sctx->isc_rx_nsegments, /* nsegments */ 1837 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1838 0, /* flags */ 1839 NULL, /* lockfunc */ 1840 NULL, /* lockarg */ 1841 &fl->ifl_buf_tag); 1842 if (err) { 1843 device_printf(dev, 1844 "Unable to allocate RX DMA tag: %d\n", err); 1845 goto fail; 1846 } 1847 1848 /* Allocate memory for the RX mbuf map. */ 1849 if (!(fl->ifl_sds.ifsd_m = 1850 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1851 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1852 device_printf(dev, 1853 "Unable to allocate RX mbuf map memory\n"); 1854 err = ENOMEM; 1855 goto fail; 1856 } 1857 1858 /* Allocate memory for the direct RX cluster pointer map. */ 1859 if (!(fl->ifl_sds.ifsd_cl = 1860 (caddr_t *) malloc(sizeof(caddr_t) * 1861 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1862 device_printf(dev, 1863 "Unable to allocate RX cluster map memory\n"); 1864 err = ENOMEM; 1865 goto fail; 1866 } 1867 1868 /* Allocate memory for the RX cluster bus address map. */ 1869 if (!(fl->ifl_sds.ifsd_ba = 1870 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1871 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1872 device_printf(dev, 1873 "Unable to allocate RX bus address map memory\n"); 1874 err = ENOMEM; 1875 goto fail; 1876 } 1877 1878 /* 1879 * Create the DMA maps for RX buffers. 1880 */ 1881 if (!(fl->ifl_sds.ifsd_map = 1882 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1883 device_printf(dev, 1884 "Unable to allocate RX buffer DMA map memory\n"); 1885 err = ENOMEM; 1886 goto fail; 1887 } 1888 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1889 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1890 &fl->ifl_sds.ifsd_map[i]); 1891 if (err != 0) { 1892 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1893 goto fail; 1894 } 1895 } 1896 } 1897 return (0); 1898 1899 fail: 1900 iflib_rx_structures_free(ctx); 1901 return (err); 1902 } 1903 1904 1905 /* 1906 * Internal service routines 1907 */ 1908 1909 struct rxq_refill_cb_arg { 1910 int error; 1911 bus_dma_segment_t seg; 1912 int nseg; 1913 }; 1914 1915 static void 1916 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1917 { 1918 struct rxq_refill_cb_arg *cb_arg = arg; 1919 1920 cb_arg->error = error; 1921 cb_arg->seg = segs[0]; 1922 cb_arg->nseg = nseg; 1923 } 1924 1925 /** 1926 * _iflib_fl_refill - refill an rxq free-buffer list 1927 * @ctx: the iflib context 1928 * @fl: the free list to refill 1929 * @count: the number of new buffers to allocate 1930 * 1931 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 1932 * The caller must assure that @count does not exceed the queue's capacity. 1933 */ 1934 static void 1935 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1936 { 1937 struct if_rxd_update iru; 1938 struct rxq_refill_cb_arg cb_arg; 1939 struct mbuf *m; 1940 caddr_t cl, *sd_cl; 1941 struct mbuf **sd_m; 1942 bus_dmamap_t *sd_map; 1943 bus_addr_t bus_addr, *sd_ba; 1944 int err, frag_idx, i, idx, n, pidx; 1945 qidx_t credits; 1946 1947 sd_m = fl->ifl_sds.ifsd_m; 1948 sd_map = fl->ifl_sds.ifsd_map; 1949 sd_cl = fl->ifl_sds.ifsd_cl; 1950 sd_ba = fl->ifl_sds.ifsd_ba; 1951 pidx = fl->ifl_pidx; 1952 idx = pidx; 1953 frag_idx = fl->ifl_fragidx; 1954 credits = fl->ifl_credits; 1955 1956 i = 0; 1957 n = count; 1958 MPASS(n > 0); 1959 MPASS(credits + n <= fl->ifl_size); 1960 1961 if (pidx < fl->ifl_cidx) 1962 MPASS(pidx + n <= fl->ifl_cidx); 1963 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1964 MPASS(fl->ifl_gen == 0); 1965 if (pidx > fl->ifl_cidx) 1966 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1967 1968 DBG_COUNTER_INC(fl_refills); 1969 if (n > 8) 1970 DBG_COUNTER_INC(fl_refills_large); 1971 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1972 while (n--) { 1973 /* 1974 * We allocate an uninitialized mbuf + cluster, mbuf is 1975 * initialized after rx. 1976 * 1977 * If the cluster is still set then we know a minimum sized packet was received 1978 */ 1979 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 1980 &frag_idx); 1981 if (frag_idx < 0) 1982 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1983 MPASS(frag_idx >= 0); 1984 if ((cl = sd_cl[frag_idx]) == NULL) { 1985 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1986 break; 1987 1988 cb_arg.error = 0; 1989 MPASS(sd_map != NULL); 1990 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 1991 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 1992 BUS_DMA_NOWAIT); 1993 if (err != 0 || cb_arg.error) { 1994 /* 1995 * !zone_pack ? 1996 */ 1997 if (fl->ifl_zone == zone_pack) 1998 uma_zfree(fl->ifl_zone, cl); 1999 break; 2000 } 2001 2002 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2003 sd_cl[frag_idx] = cl; 2004 #if MEMORY_LOGGING 2005 fl->ifl_cl_enqueued++; 2006 #endif 2007 } else { 2008 bus_addr = sd_ba[frag_idx]; 2009 } 2010 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2011 BUS_DMASYNC_PREREAD); 2012 2013 if (sd_m[frag_idx] == NULL) { 2014 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 2015 break; 2016 } 2017 sd_m[frag_idx] = m; 2018 } 2019 bit_set(fl->ifl_rx_bitmap, frag_idx); 2020 #if MEMORY_LOGGING 2021 fl->ifl_m_enqueued++; 2022 #endif 2023 2024 DBG_COUNTER_INC(rx_allocs); 2025 fl->ifl_rxd_idxs[i] = frag_idx; 2026 fl->ifl_bus_addrs[i] = bus_addr; 2027 fl->ifl_vm_addrs[i] = cl; 2028 credits++; 2029 i++; 2030 MPASS(credits <= fl->ifl_size); 2031 if (++idx == fl->ifl_size) { 2032 fl->ifl_gen = 1; 2033 idx = 0; 2034 } 2035 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2036 iru.iru_pidx = pidx; 2037 iru.iru_count = i; 2038 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2039 i = 0; 2040 pidx = idx; 2041 fl->ifl_pidx = idx; 2042 fl->ifl_credits = credits; 2043 } 2044 } 2045 2046 if (i) { 2047 iru.iru_pidx = pidx; 2048 iru.iru_count = i; 2049 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2050 fl->ifl_pidx = idx; 2051 fl->ifl_credits = credits; 2052 } 2053 DBG_COUNTER_INC(rxd_flush); 2054 if (fl->ifl_pidx == 0) 2055 pidx = fl->ifl_size - 1; 2056 else 2057 pidx = fl->ifl_pidx - 1; 2058 2059 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2060 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2061 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2062 fl->ifl_fragidx = frag_idx; 2063 } 2064 2065 static __inline void 2066 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2067 { 2068 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2069 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2070 #ifdef INVARIANTS 2071 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2072 #endif 2073 2074 MPASS(fl->ifl_credits <= fl->ifl_size); 2075 MPASS(reclaimable == delta); 2076 2077 if (reclaimable > 0) 2078 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2079 } 2080 2081 uint8_t 2082 iflib_in_detach(if_ctx_t ctx) 2083 { 2084 bool in_detach; 2085 2086 STATE_LOCK(ctx); 2087 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2088 STATE_UNLOCK(ctx); 2089 return (in_detach); 2090 } 2091 2092 static void 2093 iflib_fl_bufs_free(iflib_fl_t fl) 2094 { 2095 iflib_dma_info_t idi = fl->ifl_ifdi; 2096 bus_dmamap_t sd_map; 2097 uint32_t i; 2098 2099 for (i = 0; i < fl->ifl_size; i++) { 2100 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2101 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2102 2103 if (*sd_cl != NULL) { 2104 sd_map = fl->ifl_sds.ifsd_map[i]; 2105 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2106 BUS_DMASYNC_POSTREAD); 2107 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2108 if (*sd_cl != NULL) 2109 uma_zfree(fl->ifl_zone, *sd_cl); 2110 // XXX: Should this get moved out? 2111 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx)) 2112 bus_dmamap_destroy(fl->ifl_buf_tag, sd_map); 2113 if (*sd_m != NULL) { 2114 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2115 uma_zfree(zone_mbuf, *sd_m); 2116 } 2117 } else { 2118 MPASS(*sd_cl == NULL); 2119 MPASS(*sd_m == NULL); 2120 } 2121 #if MEMORY_LOGGING 2122 fl->ifl_m_dequeued++; 2123 fl->ifl_cl_dequeued++; 2124 #endif 2125 *sd_cl = NULL; 2126 *sd_m = NULL; 2127 } 2128 #ifdef INVARIANTS 2129 for (i = 0; i < fl->ifl_size; i++) { 2130 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2131 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2132 } 2133 #endif 2134 /* 2135 * Reset free list values 2136 */ 2137 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2138 bzero(idi->idi_vaddr, idi->idi_size); 2139 } 2140 2141 /********************************************************************* 2142 * 2143 * Initialize a free list and its buffers. 2144 * 2145 **********************************************************************/ 2146 static int 2147 iflib_fl_setup(iflib_fl_t fl) 2148 { 2149 iflib_rxq_t rxq = fl->ifl_rxq; 2150 if_ctx_t ctx = rxq->ifr_ctx; 2151 2152 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2153 /* 2154 ** Free current RX buffer structs and their mbufs 2155 */ 2156 iflib_fl_bufs_free(fl); 2157 /* Now replenish the mbufs */ 2158 MPASS(fl->ifl_credits == 0); 2159 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2160 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2161 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2162 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2163 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2164 2165 2166 /* avoid pre-allocating zillions of clusters to an idle card 2167 * potentially speeding up attach 2168 */ 2169 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2170 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2171 if (min(128, fl->ifl_size) != fl->ifl_credits) 2172 return (ENOBUFS); 2173 /* 2174 * handle failure 2175 */ 2176 MPASS(rxq != NULL); 2177 MPASS(fl->ifl_ifdi != NULL); 2178 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2179 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2180 return (0); 2181 } 2182 2183 /********************************************************************* 2184 * 2185 * Free receive ring data structures 2186 * 2187 **********************************************************************/ 2188 static void 2189 iflib_rx_sds_free(iflib_rxq_t rxq) 2190 { 2191 iflib_fl_t fl; 2192 int i, j; 2193 2194 if (rxq->ifr_fl != NULL) { 2195 for (i = 0; i < rxq->ifr_nfl; i++) { 2196 fl = &rxq->ifr_fl[i]; 2197 if (fl->ifl_buf_tag != NULL) { 2198 if (fl->ifl_sds.ifsd_map != NULL) { 2199 for (j = 0; j < fl->ifl_size; j++) { 2200 if (fl->ifl_sds.ifsd_map[j] == 2201 NULL) 2202 continue; 2203 bus_dmamap_sync( 2204 fl->ifl_buf_tag, 2205 fl->ifl_sds.ifsd_map[j], 2206 BUS_DMASYNC_POSTREAD); 2207 bus_dmamap_unload( 2208 fl->ifl_buf_tag, 2209 fl->ifl_sds.ifsd_map[j]); 2210 } 2211 } 2212 bus_dma_tag_destroy(fl->ifl_buf_tag); 2213 fl->ifl_buf_tag = NULL; 2214 } 2215 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2216 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2217 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2218 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2219 fl->ifl_sds.ifsd_m = NULL; 2220 fl->ifl_sds.ifsd_cl = NULL; 2221 fl->ifl_sds.ifsd_ba = NULL; 2222 fl->ifl_sds.ifsd_map = NULL; 2223 } 2224 free(rxq->ifr_fl, M_IFLIB); 2225 rxq->ifr_fl = NULL; 2226 rxq->ifr_cq_cidx = 0; 2227 } 2228 } 2229 2230 /* 2231 * Timer routine 2232 */ 2233 static void 2234 iflib_timer(void *arg) 2235 { 2236 iflib_txq_t txq = arg; 2237 if_ctx_t ctx = txq->ift_ctx; 2238 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2239 uint64_t this_tick = ticks; 2240 uint32_t reset_on = hz / 2; 2241 2242 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2243 return; 2244 2245 /* 2246 ** Check on the state of the TX queue(s), this 2247 ** can be done without the lock because its RO 2248 ** and the HUNG state will be static if set. 2249 */ 2250 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2251 txq->ift_last_timer_tick = this_tick; 2252 IFDI_TIMER(ctx, txq->ift_id); 2253 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2254 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2255 (sctx->isc_pause_frames == 0))) 2256 goto hung; 2257 2258 if (ifmp_ring_is_stalled(txq->ift_br)) 2259 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2260 txq->ift_cleaned_prev = txq->ift_cleaned; 2261 } 2262 #ifdef DEV_NETMAP 2263 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2264 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 2265 #endif 2266 /* handle any laggards */ 2267 if (txq->ift_db_pending) 2268 GROUPTASK_ENQUEUE(&txq->ift_task); 2269 2270 sctx->isc_pause_frames = 0; 2271 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2272 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2273 return; 2274 2275 hung: 2276 device_printf(ctx->ifc_dev, 2277 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2278 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2279 STATE_LOCK(ctx); 2280 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2281 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2282 iflib_admin_intr_deferred(ctx); 2283 STATE_UNLOCK(ctx); 2284 } 2285 2286 static void 2287 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2288 { 2289 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2290 2291 /* 2292 * XXX don't set the max_frame_size to larger 2293 * than the hardware can handle 2294 */ 2295 if (sctx->isc_max_frame_size <= MCLBYTES) 2296 ctx->ifc_rx_mbuf_sz = MCLBYTES; 2297 else 2298 ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE; 2299 } 2300 2301 uint32_t 2302 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2303 { 2304 2305 return (ctx->ifc_rx_mbuf_sz); 2306 } 2307 2308 static void 2309 iflib_init_locked(if_ctx_t ctx) 2310 { 2311 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2312 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2313 if_t ifp = ctx->ifc_ifp; 2314 iflib_fl_t fl; 2315 iflib_txq_t txq; 2316 iflib_rxq_t rxq; 2317 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2318 2319 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2320 IFDI_INTR_DISABLE(ctx); 2321 2322 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2323 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2324 /* Set hardware offload abilities */ 2325 if_clearhwassist(ifp); 2326 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2327 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2328 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2329 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2330 if (if_getcapenable(ifp) & IFCAP_TSO4) 2331 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2332 if (if_getcapenable(ifp) & IFCAP_TSO6) 2333 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2334 2335 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2336 CALLOUT_LOCK(txq); 2337 callout_stop(&txq->ift_timer); 2338 CALLOUT_UNLOCK(txq); 2339 iflib_netmap_txq_init(ctx, txq); 2340 } 2341 2342 /* 2343 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2344 * that drivers can use the value when setting up the hardware receive 2345 * buffers. 2346 */ 2347 iflib_calc_rx_mbuf_sz(ctx); 2348 2349 #ifdef INVARIANTS 2350 i = if_getdrvflags(ifp); 2351 #endif 2352 IFDI_INIT(ctx); 2353 MPASS(if_getdrvflags(ifp) == i); 2354 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2355 /* XXX this should really be done on a per-queue basis */ 2356 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2357 MPASS(rxq->ifr_id == i); 2358 iflib_netmap_rxq_init(ctx, rxq); 2359 continue; 2360 } 2361 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2362 if (iflib_fl_setup(fl)) { 2363 device_printf(ctx->ifc_dev, 2364 "setting up free list %d failed - " 2365 "check cluster settings\n", j); 2366 goto done; 2367 } 2368 } 2369 } 2370 done: 2371 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2372 IFDI_INTR_ENABLE(ctx); 2373 txq = ctx->ifc_txqs; 2374 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2375 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2376 txq->ift_timer.c_cpu); 2377 } 2378 2379 static int 2380 iflib_media_change(if_t ifp) 2381 { 2382 if_ctx_t ctx = if_getsoftc(ifp); 2383 int err; 2384 2385 CTX_LOCK(ctx); 2386 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2387 iflib_init_locked(ctx); 2388 CTX_UNLOCK(ctx); 2389 return (err); 2390 } 2391 2392 static void 2393 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2394 { 2395 if_ctx_t ctx = if_getsoftc(ifp); 2396 2397 CTX_LOCK(ctx); 2398 IFDI_UPDATE_ADMIN_STATUS(ctx); 2399 IFDI_MEDIA_STATUS(ctx, ifmr); 2400 CTX_UNLOCK(ctx); 2401 } 2402 2403 void 2404 iflib_stop(if_ctx_t ctx) 2405 { 2406 iflib_txq_t txq = ctx->ifc_txqs; 2407 iflib_rxq_t rxq = ctx->ifc_rxqs; 2408 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2409 if_shared_ctx_t sctx = ctx->ifc_sctx; 2410 iflib_dma_info_t di; 2411 iflib_fl_t fl; 2412 int i, j; 2413 2414 /* Tell the stack that the interface is no longer active */ 2415 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2416 2417 IFDI_INTR_DISABLE(ctx); 2418 DELAY(1000); 2419 IFDI_STOP(ctx); 2420 DELAY(1000); 2421 2422 iflib_debug_reset(); 2423 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2424 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2425 /* make sure all transmitters have completed before proceeding XXX */ 2426 2427 CALLOUT_LOCK(txq); 2428 callout_stop(&txq->ift_timer); 2429 CALLOUT_UNLOCK(txq); 2430 2431 /* clean any enqueued buffers */ 2432 iflib_ifmp_purge(txq); 2433 /* Free any existing tx buffers. */ 2434 for (j = 0; j < txq->ift_size; j++) { 2435 iflib_txsd_free(ctx, txq, j); 2436 } 2437 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2438 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2439 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2440 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2441 txq->ift_pullups = 0; 2442 ifmp_ring_reset_stats(txq->ift_br); 2443 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2444 bzero((void *)di->idi_vaddr, di->idi_size); 2445 } 2446 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2447 /* make sure all transmitters have completed before proceeding XXX */ 2448 2449 rxq->ifr_cq_cidx = 0; 2450 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2451 bzero((void *)di->idi_vaddr, di->idi_size); 2452 /* also resets the free lists pidx/cidx */ 2453 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2454 iflib_fl_bufs_free(fl); 2455 } 2456 } 2457 2458 static inline caddr_t 2459 calc_next_rxd(iflib_fl_t fl, int cidx) 2460 { 2461 qidx_t size; 2462 int nrxd; 2463 caddr_t start, end, cur, next; 2464 2465 nrxd = fl->ifl_size; 2466 size = fl->ifl_rxd_size; 2467 start = fl->ifl_ifdi->idi_vaddr; 2468 2469 if (__predict_false(size == 0)) 2470 return (start); 2471 cur = start + size*cidx; 2472 end = start + size*nrxd; 2473 next = CACHE_PTR_NEXT(cur); 2474 return (next < end ? next : start); 2475 } 2476 2477 static inline void 2478 prefetch_pkts(iflib_fl_t fl, int cidx) 2479 { 2480 int nextptr; 2481 int nrxd = fl->ifl_size; 2482 caddr_t next_rxd; 2483 2484 2485 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2486 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2487 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2488 next_rxd = calc_next_rxd(fl, cidx); 2489 prefetch(next_rxd); 2490 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2491 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2492 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2493 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2494 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2495 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2496 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2497 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2498 } 2499 2500 static struct mbuf * 2501 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2502 int *pf_rv, if_rxd_info_t ri) 2503 { 2504 bus_dmamap_t map; 2505 iflib_fl_t fl; 2506 caddr_t payload; 2507 struct mbuf *m; 2508 int flid, cidx, len, next; 2509 2510 map = NULL; 2511 flid = irf->irf_flid; 2512 cidx = irf->irf_idx; 2513 fl = &rxq->ifr_fl[flid]; 2514 sd->ifsd_fl = fl; 2515 sd->ifsd_cidx = cidx; 2516 m = fl->ifl_sds.ifsd_m[cidx]; 2517 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2518 fl->ifl_credits--; 2519 #if MEMORY_LOGGING 2520 fl->ifl_m_dequeued++; 2521 #endif 2522 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2523 prefetch_pkts(fl, cidx); 2524 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2525 prefetch(&fl->ifl_sds.ifsd_map[next]); 2526 map = fl->ifl_sds.ifsd_map[cidx]; 2527 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2528 2529 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2530 MPASS(fl->ifl_cidx == cidx); 2531 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2532 2533 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL) { 2534 payload = *sd->ifsd_cl; 2535 payload += ri->iri_pad; 2536 len = ri->iri_len - ri->iri_pad; 2537 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2538 len | PFIL_MEMPTR | PFIL_IN, NULL); 2539 switch (*pf_rv) { 2540 case PFIL_DROPPED: 2541 case PFIL_CONSUMED: 2542 /* 2543 * The filter ate it. Everything is recycled. 2544 */ 2545 m = NULL; 2546 unload = 0; 2547 break; 2548 case PFIL_REALLOCED: 2549 /* 2550 * The filter copied it. Everything is recycled. 2551 */ 2552 m = pfil_mem2mbuf(payload); 2553 unload = 0; 2554 break; 2555 case PFIL_PASS: 2556 /* 2557 * Filter said it was OK, so receive like 2558 * normal 2559 */ 2560 fl->ifl_sds.ifsd_m[cidx] = NULL; 2561 break; 2562 default: 2563 MPASS(0); 2564 } 2565 } else { 2566 fl->ifl_sds.ifsd_m[cidx] = NULL; 2567 *pf_rv = PFIL_PASS; 2568 } 2569 2570 if (unload) 2571 bus_dmamap_unload(fl->ifl_buf_tag, map); 2572 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2573 if (__predict_false(fl->ifl_cidx == 0)) 2574 fl->ifl_gen = 0; 2575 bit_clear(fl->ifl_rx_bitmap, cidx); 2576 return (m); 2577 } 2578 2579 static struct mbuf * 2580 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2581 { 2582 struct mbuf *m, *mh, *mt; 2583 caddr_t cl; 2584 int *pf_rv_ptr, flags, i, padlen; 2585 bool consumed; 2586 2587 i = 0; 2588 mh = NULL; 2589 consumed = false; 2590 *pf_rv = PFIL_PASS; 2591 pf_rv_ptr = pf_rv; 2592 do { 2593 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2594 pf_rv_ptr, ri); 2595 2596 MPASS(*sd->ifsd_cl != NULL); 2597 2598 /* 2599 * Exclude zero-length frags & frags from 2600 * packets the filter has consumed or dropped 2601 */ 2602 if (ri->iri_frags[i].irf_len == 0 || consumed || 2603 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2604 if (mh == NULL) { 2605 /* everything saved here */ 2606 consumed = true; 2607 pf_rv_ptr = NULL; 2608 continue; 2609 } 2610 /* XXX we can save the cluster here, but not the mbuf */ 2611 m_init(m, M_NOWAIT, MT_DATA, 0); 2612 m_free(m); 2613 continue; 2614 } 2615 if (mh == NULL) { 2616 flags = M_PKTHDR|M_EXT; 2617 mh = mt = m; 2618 padlen = ri->iri_pad; 2619 } else { 2620 flags = M_EXT; 2621 mt->m_next = m; 2622 mt = m; 2623 /* assuming padding is only on the first fragment */ 2624 padlen = 0; 2625 } 2626 cl = *sd->ifsd_cl; 2627 *sd->ifsd_cl = NULL; 2628 2629 /* Can these two be made one ? */ 2630 m_init(m, M_NOWAIT, MT_DATA, flags); 2631 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2632 /* 2633 * These must follow m_init and m_cljset 2634 */ 2635 m->m_data += padlen; 2636 ri->iri_len -= padlen; 2637 m->m_len = ri->iri_frags[i].irf_len; 2638 } while (++i < ri->iri_nfrags); 2639 2640 return (mh); 2641 } 2642 2643 /* 2644 * Process one software descriptor 2645 */ 2646 static struct mbuf * 2647 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2648 { 2649 struct if_rxsd sd; 2650 struct mbuf *m; 2651 int pf_rv; 2652 2653 /* should I merge this back in now that the two paths are basically duplicated? */ 2654 if (ri->iri_nfrags == 1 && 2655 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2656 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2657 &pf_rv, ri); 2658 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2659 return (m); 2660 if (pf_rv == PFIL_PASS) { 2661 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2662 #ifndef __NO_STRICT_ALIGNMENT 2663 if (!IP_ALIGNED(m)) 2664 m->m_data += 2; 2665 #endif 2666 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2667 m->m_len = ri->iri_frags[0].irf_len; 2668 } 2669 } else { 2670 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2671 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2672 return (m); 2673 } 2674 m->m_pkthdr.len = ri->iri_len; 2675 m->m_pkthdr.rcvif = ri->iri_ifp; 2676 m->m_flags |= ri->iri_flags; 2677 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2678 m->m_pkthdr.flowid = ri->iri_flowid; 2679 M_HASHTYPE_SET(m, ri->iri_rsstype); 2680 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2681 m->m_pkthdr.csum_data = ri->iri_csum_data; 2682 return (m); 2683 } 2684 2685 #if defined(INET6) || defined(INET) 2686 static void 2687 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2688 { 2689 CURVNET_SET(lc->ifp->if_vnet); 2690 #if defined(INET6) 2691 *v6 = VNET(ip6_forwarding); 2692 #endif 2693 #if defined(INET) 2694 *v4 = VNET(ipforwarding); 2695 #endif 2696 CURVNET_RESTORE(); 2697 } 2698 2699 /* 2700 * Returns true if it's possible this packet could be LROed. 2701 * if it returns false, it is guaranteed that tcp_lro_rx() 2702 * would not return zero. 2703 */ 2704 static bool 2705 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2706 { 2707 struct ether_header *eh; 2708 uint16_t eh_type; 2709 2710 eh = mtod(m, struct ether_header *); 2711 eh_type = ntohs(eh->ether_type); 2712 switch (eh_type) { 2713 #if defined(INET6) 2714 case ETHERTYPE_IPV6: 2715 return !v6_forwarding; 2716 #endif 2717 #if defined (INET) 2718 case ETHERTYPE_IP: 2719 return !v4_forwarding; 2720 #endif 2721 } 2722 2723 return false; 2724 } 2725 #else 2726 static void 2727 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2728 { 2729 } 2730 #endif 2731 2732 static bool 2733 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2734 { 2735 if_t ifp; 2736 if_ctx_t ctx = rxq->ifr_ctx; 2737 if_shared_ctx_t sctx = ctx->ifc_sctx; 2738 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2739 int avail, i; 2740 qidx_t *cidxp; 2741 struct if_rxd_info ri; 2742 int err, budget_left, rx_bytes, rx_pkts; 2743 iflib_fl_t fl; 2744 int lro_enabled; 2745 bool v4_forwarding, v6_forwarding, lro_possible; 2746 2747 /* 2748 * XXX early demux data packets so that if_input processing only handles 2749 * acks in interrupt context 2750 */ 2751 struct mbuf *m, *mh, *mt, *mf; 2752 2753 lro_possible = v4_forwarding = v6_forwarding = false; 2754 ifp = ctx->ifc_ifp; 2755 mh = mt = NULL; 2756 MPASS(budget > 0); 2757 rx_pkts = rx_bytes = 0; 2758 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2759 cidxp = &rxq->ifr_cq_cidx; 2760 else 2761 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2762 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2763 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2764 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2765 DBG_COUNTER_INC(rx_unavail); 2766 return (false); 2767 } 2768 2769 /* pfil needs the vnet to be set */ 2770 CURVNET_SET_QUIET(ifp->if_vnet); 2771 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2772 if (__predict_false(!CTX_ACTIVE(ctx))) { 2773 DBG_COUNTER_INC(rx_ctx_inactive); 2774 break; 2775 } 2776 /* 2777 * Reset client set fields to their default values 2778 */ 2779 rxd_info_zero(&ri); 2780 ri.iri_qsidx = rxq->ifr_id; 2781 ri.iri_cidx = *cidxp; 2782 ri.iri_ifp = ifp; 2783 ri.iri_frags = rxq->ifr_frags; 2784 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2785 2786 if (err) 2787 goto err; 2788 rx_pkts += 1; 2789 rx_bytes += ri.iri_len; 2790 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2791 *cidxp = ri.iri_cidx; 2792 /* Update our consumer index */ 2793 /* XXX NB: shurd - check if this is still safe */ 2794 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2795 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2796 /* was this only a completion queue message? */ 2797 if (__predict_false(ri.iri_nfrags == 0)) 2798 continue; 2799 } 2800 MPASS(ri.iri_nfrags != 0); 2801 MPASS(ri.iri_len != 0); 2802 2803 /* will advance the cidx on the corresponding free lists */ 2804 m = iflib_rxd_pkt_get(rxq, &ri); 2805 avail--; 2806 budget_left--; 2807 if (avail == 0 && budget_left) 2808 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2809 2810 if (__predict_false(m == NULL)) 2811 continue; 2812 2813 /* imm_pkt: -- cxgb */ 2814 if (mh == NULL) 2815 mh = mt = m; 2816 else { 2817 mt->m_nextpkt = m; 2818 mt = m; 2819 } 2820 } 2821 CURVNET_RESTORE(); 2822 /* make sure that we can refill faster than drain */ 2823 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2824 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2825 2826 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2827 if (lro_enabled) 2828 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2829 mt = mf = NULL; 2830 while (mh != NULL) { 2831 m = mh; 2832 mh = mh->m_nextpkt; 2833 m->m_nextpkt = NULL; 2834 #ifndef __NO_STRICT_ALIGNMENT 2835 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2836 continue; 2837 #endif 2838 rx_bytes += m->m_pkthdr.len; 2839 rx_pkts++; 2840 #if defined(INET6) || defined(INET) 2841 if (lro_enabled) { 2842 if (!lro_possible) { 2843 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2844 if (lro_possible && mf != NULL) { 2845 ifp->if_input(ifp, mf); 2846 DBG_COUNTER_INC(rx_if_input); 2847 mt = mf = NULL; 2848 } 2849 } 2850 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2851 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2852 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2853 continue; 2854 } 2855 } 2856 #endif 2857 if (lro_possible) { 2858 ifp->if_input(ifp, m); 2859 DBG_COUNTER_INC(rx_if_input); 2860 continue; 2861 } 2862 2863 if (mf == NULL) 2864 mf = m; 2865 if (mt != NULL) 2866 mt->m_nextpkt = m; 2867 mt = m; 2868 } 2869 if (mf != NULL) { 2870 ifp->if_input(ifp, mf); 2871 DBG_COUNTER_INC(rx_if_input); 2872 } 2873 2874 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2875 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2876 2877 /* 2878 * Flush any outstanding LRO work 2879 */ 2880 #if defined(INET6) || defined(INET) 2881 tcp_lro_flush_all(&rxq->ifr_lc); 2882 #endif 2883 if (avail) 2884 return true; 2885 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2886 err: 2887 STATE_LOCK(ctx); 2888 ctx->ifc_flags |= IFC_DO_RESET; 2889 iflib_admin_intr_deferred(ctx); 2890 STATE_UNLOCK(ctx); 2891 return (false); 2892 } 2893 2894 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2895 static inline qidx_t 2896 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2897 { 2898 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2899 qidx_t minthresh = txq->ift_size / 8; 2900 if (in_use > 4*minthresh) 2901 return (notify_count); 2902 if (in_use > 2*minthresh) 2903 return (notify_count >> 1); 2904 if (in_use > minthresh) 2905 return (notify_count >> 3); 2906 return (0); 2907 } 2908 2909 static inline qidx_t 2910 txq_max_rs_deferred(iflib_txq_t txq) 2911 { 2912 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2913 qidx_t minthresh = txq->ift_size / 8; 2914 if (txq->ift_in_use > 4*minthresh) 2915 return (notify_count); 2916 if (txq->ift_in_use > 2*minthresh) 2917 return (notify_count >> 1); 2918 if (txq->ift_in_use > minthresh) 2919 return (notify_count >> 2); 2920 return (2); 2921 } 2922 2923 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2924 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2925 2926 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2927 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2928 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2929 2930 /* forward compatibility for cxgb */ 2931 #define FIRST_QSET(ctx) 0 2932 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2933 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2934 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2935 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2936 2937 /* XXX we should be setting this to something other than zero */ 2938 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2939 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2940 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2941 2942 static inline bool 2943 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2944 { 2945 qidx_t dbval, max; 2946 bool rang; 2947 2948 rang = false; 2949 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2950 if (ring || txq->ift_db_pending >= max) { 2951 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2952 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 2953 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2954 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2955 txq->ift_db_pending = txq->ift_npending = 0; 2956 rang = true; 2957 } 2958 return (rang); 2959 } 2960 2961 #ifdef PKT_DEBUG 2962 static void 2963 print_pkt(if_pkt_info_t pi) 2964 { 2965 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2966 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2967 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2968 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2969 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2970 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2971 } 2972 #endif 2973 2974 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2975 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2976 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2977 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2978 2979 static int 2980 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2981 { 2982 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2983 struct ether_vlan_header *eh; 2984 struct mbuf *m; 2985 2986 m = *mp; 2987 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2988 M_WRITABLE(m) == 0) { 2989 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2990 return (ENOMEM); 2991 } else { 2992 m_freem(*mp); 2993 DBG_COUNTER_INC(tx_frees); 2994 *mp = m; 2995 } 2996 } 2997 2998 /* 2999 * Determine where frame payload starts. 3000 * Jump over vlan headers if already present, 3001 * helpful for QinQ too. 3002 */ 3003 if (__predict_false(m->m_len < sizeof(*eh))) { 3004 txq->ift_pullups++; 3005 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3006 return (ENOMEM); 3007 } 3008 eh = mtod(m, struct ether_vlan_header *); 3009 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3010 pi->ipi_etype = ntohs(eh->evl_proto); 3011 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3012 } else { 3013 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3014 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3015 } 3016 3017 switch (pi->ipi_etype) { 3018 #ifdef INET 3019 case ETHERTYPE_IP: 3020 { 3021 struct mbuf *n; 3022 struct ip *ip = NULL; 3023 struct tcphdr *th = NULL; 3024 int minthlen; 3025 3026 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3027 if (__predict_false(m->m_len < minthlen)) { 3028 /* 3029 * if this code bloat is causing too much of a hit 3030 * move it to a separate function and mark it noinline 3031 */ 3032 if (m->m_len == pi->ipi_ehdrlen) { 3033 n = m->m_next; 3034 MPASS(n); 3035 if (n->m_len >= sizeof(*ip)) { 3036 ip = (struct ip *)n->m_data; 3037 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3038 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3039 } else { 3040 txq->ift_pullups++; 3041 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3042 return (ENOMEM); 3043 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3044 } 3045 } else { 3046 txq->ift_pullups++; 3047 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3048 return (ENOMEM); 3049 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3050 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3051 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3052 } 3053 } else { 3054 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3055 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3056 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3057 } 3058 pi->ipi_ip_hlen = ip->ip_hl << 2; 3059 pi->ipi_ipproto = ip->ip_p; 3060 pi->ipi_flags |= IPI_TX_IPV4; 3061 3062 /* TCP checksum offload may require TCP header length */ 3063 if (IS_TX_OFFLOAD4(pi)) { 3064 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3065 if (__predict_false(th == NULL)) { 3066 txq->ift_pullups++; 3067 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3068 return (ENOMEM); 3069 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3070 } 3071 pi->ipi_tcp_hflags = th->th_flags; 3072 pi->ipi_tcp_hlen = th->th_off << 2; 3073 pi->ipi_tcp_seq = th->th_seq; 3074 } 3075 if (IS_TSO4(pi)) { 3076 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3077 return (ENXIO); 3078 /* 3079 * TSO always requires hardware checksum offload. 3080 */ 3081 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3082 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3083 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3084 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3085 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3086 ip->ip_sum = 0; 3087 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3088 } 3089 } 3090 } 3091 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3092 ip->ip_sum = 0; 3093 3094 break; 3095 } 3096 #endif 3097 #ifdef INET6 3098 case ETHERTYPE_IPV6: 3099 { 3100 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3101 struct tcphdr *th; 3102 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3103 3104 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3105 txq->ift_pullups++; 3106 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3107 return (ENOMEM); 3108 } 3109 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3110 3111 /* XXX-BZ this will go badly in case of ext hdrs. */ 3112 pi->ipi_ipproto = ip6->ip6_nxt; 3113 pi->ipi_flags |= IPI_TX_IPV6; 3114 3115 /* TCP checksum offload may require TCP header length */ 3116 if (IS_TX_OFFLOAD6(pi)) { 3117 if (pi->ipi_ipproto == IPPROTO_TCP) { 3118 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3119 txq->ift_pullups++; 3120 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3121 return (ENOMEM); 3122 } 3123 pi->ipi_tcp_hflags = th->th_flags; 3124 pi->ipi_tcp_hlen = th->th_off << 2; 3125 pi->ipi_tcp_seq = th->th_seq; 3126 } 3127 if (IS_TSO6(pi)) { 3128 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3129 return (ENXIO); 3130 /* 3131 * TSO always requires hardware checksum offload. 3132 */ 3133 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3134 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3135 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3136 } 3137 } 3138 break; 3139 } 3140 #endif 3141 default: 3142 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3143 pi->ipi_ip_hlen = 0; 3144 break; 3145 } 3146 *mp = m; 3147 3148 return (0); 3149 } 3150 3151 /* 3152 * If dodgy hardware rejects the scatter gather chain we've handed it 3153 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3154 * m_defrag'd mbufs 3155 */ 3156 static __noinline struct mbuf * 3157 iflib_remove_mbuf(iflib_txq_t txq) 3158 { 3159 int ntxd, pidx; 3160 struct mbuf *m, **ifsd_m; 3161 3162 ifsd_m = txq->ift_sds.ifsd_m; 3163 ntxd = txq->ift_size; 3164 pidx = txq->ift_pidx & (ntxd - 1); 3165 ifsd_m = txq->ift_sds.ifsd_m; 3166 m = ifsd_m[pidx]; 3167 ifsd_m[pidx] = NULL; 3168 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3169 if (txq->ift_sds.ifsd_tso_map != NULL) 3170 bus_dmamap_unload(txq->ift_tso_buf_tag, 3171 txq->ift_sds.ifsd_tso_map[pidx]); 3172 #if MEMORY_LOGGING 3173 txq->ift_dequeued++; 3174 #endif 3175 return (m); 3176 } 3177 3178 static inline caddr_t 3179 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3180 { 3181 qidx_t size; 3182 int ntxd; 3183 caddr_t start, end, cur, next; 3184 3185 ntxd = txq->ift_size; 3186 size = txq->ift_txd_size[qid]; 3187 start = txq->ift_ifdi[qid].idi_vaddr; 3188 3189 if (__predict_false(size == 0)) 3190 return (start); 3191 cur = start + size*cidx; 3192 end = start + size*ntxd; 3193 next = CACHE_PTR_NEXT(cur); 3194 return (next < end ? next : start); 3195 } 3196 3197 /* 3198 * Pad an mbuf to ensure a minimum ethernet frame size. 3199 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3200 */ 3201 static __noinline int 3202 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3203 { 3204 /* 3205 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3206 * and ARP message is the smallest common payload I can think of 3207 */ 3208 static char pad[18]; /* just zeros */ 3209 int n; 3210 struct mbuf *new_head; 3211 3212 if (!M_WRITABLE(*m_head)) { 3213 new_head = m_dup(*m_head, M_NOWAIT); 3214 if (new_head == NULL) { 3215 m_freem(*m_head); 3216 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3217 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3218 DBG_COUNTER_INC(tx_frees); 3219 return ENOMEM; 3220 } 3221 m_freem(*m_head); 3222 *m_head = new_head; 3223 } 3224 3225 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3226 n > 0; n -= sizeof(pad)) 3227 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3228 break; 3229 3230 if (n > 0) { 3231 m_freem(*m_head); 3232 device_printf(dev, "cannot pad short frame\n"); 3233 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3234 DBG_COUNTER_INC(tx_frees); 3235 return (ENOBUFS); 3236 } 3237 3238 return 0; 3239 } 3240 3241 static int 3242 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3243 { 3244 if_ctx_t ctx; 3245 if_shared_ctx_t sctx; 3246 if_softc_ctx_t scctx; 3247 bus_dma_tag_t buf_tag; 3248 bus_dma_segment_t *segs; 3249 struct mbuf *m_head, **ifsd_m; 3250 void *next_txd; 3251 bus_dmamap_t map; 3252 struct if_pkt_info pi; 3253 int remap = 0; 3254 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3255 3256 ctx = txq->ift_ctx; 3257 sctx = ctx->ifc_sctx; 3258 scctx = &ctx->ifc_softc_ctx; 3259 segs = txq->ift_segs; 3260 ntxd = txq->ift_size; 3261 m_head = *m_headp; 3262 map = NULL; 3263 3264 /* 3265 * If we're doing TSO the next descriptor to clean may be quite far ahead 3266 */ 3267 cidx = txq->ift_cidx; 3268 pidx = txq->ift_pidx; 3269 if (ctx->ifc_flags & IFC_PREFETCH) { 3270 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3271 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3272 next_txd = calc_next_txd(txq, cidx, 0); 3273 prefetch(next_txd); 3274 } 3275 3276 /* prefetch the next cache line of mbuf pointers and flags */ 3277 prefetch(&txq->ift_sds.ifsd_m[next]); 3278 prefetch(&txq->ift_sds.ifsd_map[next]); 3279 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3280 } 3281 map = txq->ift_sds.ifsd_map[pidx]; 3282 ifsd_m = txq->ift_sds.ifsd_m; 3283 3284 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3285 buf_tag = txq->ift_tso_buf_tag; 3286 max_segs = scctx->isc_tx_tso_segments_max; 3287 map = txq->ift_sds.ifsd_tso_map[pidx]; 3288 MPASS(buf_tag != NULL); 3289 MPASS(max_segs > 0); 3290 } else { 3291 buf_tag = txq->ift_buf_tag; 3292 max_segs = scctx->isc_tx_nsegments; 3293 map = txq->ift_sds.ifsd_map[pidx]; 3294 } 3295 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3296 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3297 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3298 if (err) { 3299 DBG_COUNTER_INC(encap_txd_encap_fail); 3300 return err; 3301 } 3302 } 3303 m_head = *m_headp; 3304 3305 pkt_info_zero(&pi); 3306 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3307 pi.ipi_pidx = pidx; 3308 pi.ipi_qsidx = txq->ift_id; 3309 pi.ipi_len = m_head->m_pkthdr.len; 3310 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3311 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3312 3313 /* deliberate bitwise OR to make one condition */ 3314 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3315 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3316 DBG_COUNTER_INC(encap_txd_encap_fail); 3317 return (err); 3318 } 3319 m_head = *m_headp; 3320 } 3321 3322 retry: 3323 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3324 BUS_DMA_NOWAIT); 3325 defrag: 3326 if (__predict_false(err)) { 3327 switch (err) { 3328 case EFBIG: 3329 /* try collapse once and defrag once */ 3330 if (remap == 0) { 3331 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3332 /* try defrag if collapsing fails */ 3333 if (m_head == NULL) 3334 remap++; 3335 } 3336 if (remap == 1) { 3337 txq->ift_mbuf_defrag++; 3338 m_head = m_defrag(*m_headp, M_NOWAIT); 3339 } 3340 /* 3341 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3342 * failed to map an mbuf that was run through m_defrag 3343 */ 3344 MPASS(remap <= 1); 3345 if (__predict_false(m_head == NULL || remap > 1)) 3346 goto defrag_failed; 3347 remap++; 3348 *m_headp = m_head; 3349 goto retry; 3350 break; 3351 case ENOMEM: 3352 txq->ift_no_tx_dma_setup++; 3353 break; 3354 default: 3355 txq->ift_no_tx_dma_setup++; 3356 m_freem(*m_headp); 3357 DBG_COUNTER_INC(tx_frees); 3358 *m_headp = NULL; 3359 break; 3360 } 3361 txq->ift_map_failed++; 3362 DBG_COUNTER_INC(encap_load_mbuf_fail); 3363 DBG_COUNTER_INC(encap_txd_encap_fail); 3364 return (err); 3365 } 3366 ifsd_m[pidx] = m_head; 3367 /* 3368 * XXX assumes a 1 to 1 relationship between segments and 3369 * descriptors - this does not hold true on all drivers, e.g. 3370 * cxgb 3371 */ 3372 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3373 txq->ift_no_desc_avail++; 3374 bus_dmamap_unload(buf_tag, map); 3375 DBG_COUNTER_INC(encap_txq_avail_fail); 3376 DBG_COUNTER_INC(encap_txd_encap_fail); 3377 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3378 GROUPTASK_ENQUEUE(&txq->ift_task); 3379 return (ENOBUFS); 3380 } 3381 /* 3382 * On Intel cards we can greatly reduce the number of TX interrupts 3383 * we see by only setting report status on every Nth descriptor. 3384 * However, this also means that the driver will need to keep track 3385 * of the descriptors that RS was set on to check them for the DD bit. 3386 */ 3387 txq->ift_rs_pending += nsegs + 1; 3388 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3389 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3390 pi.ipi_flags |= IPI_TX_INTR; 3391 txq->ift_rs_pending = 0; 3392 } 3393 3394 pi.ipi_segs = segs; 3395 pi.ipi_nsegs = nsegs; 3396 3397 MPASS(pidx >= 0 && pidx < txq->ift_size); 3398 #ifdef PKT_DEBUG 3399 print_pkt(&pi); 3400 #endif 3401 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3402 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3403 DBG_COUNTER_INC(tx_encap); 3404 MPASS(pi.ipi_new_pidx < txq->ift_size); 3405 3406 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3407 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3408 ndesc += txq->ift_size; 3409 txq->ift_gen = 1; 3410 } 3411 /* 3412 * drivers can need as many as 3413 * two sentinels 3414 */ 3415 MPASS(ndesc <= pi.ipi_nsegs + 2); 3416 MPASS(pi.ipi_new_pidx != pidx); 3417 MPASS(ndesc > 0); 3418 txq->ift_in_use += ndesc; 3419 3420 /* 3421 * We update the last software descriptor again here because there may 3422 * be a sentinel and/or there may be more mbufs than segments 3423 */ 3424 txq->ift_pidx = pi.ipi_new_pidx; 3425 txq->ift_npending += pi.ipi_ndescs; 3426 } else { 3427 *m_headp = m_head = iflib_remove_mbuf(txq); 3428 if (err == EFBIG) { 3429 txq->ift_txd_encap_efbig++; 3430 if (remap < 2) { 3431 remap = 1; 3432 goto defrag; 3433 } 3434 } 3435 goto defrag_failed; 3436 } 3437 /* 3438 * err can't possibly be non-zero here, so we don't neet to test it 3439 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3440 */ 3441 return (err); 3442 3443 defrag_failed: 3444 txq->ift_mbuf_defrag_failed++; 3445 txq->ift_map_failed++; 3446 m_freem(*m_headp); 3447 DBG_COUNTER_INC(tx_frees); 3448 *m_headp = NULL; 3449 DBG_COUNTER_INC(encap_txd_encap_fail); 3450 return (ENOMEM); 3451 } 3452 3453 static void 3454 iflib_tx_desc_free(iflib_txq_t txq, int n) 3455 { 3456 uint32_t qsize, cidx, mask, gen; 3457 struct mbuf *m, **ifsd_m; 3458 bool do_prefetch; 3459 3460 cidx = txq->ift_cidx; 3461 gen = txq->ift_gen; 3462 qsize = txq->ift_size; 3463 mask = qsize-1; 3464 ifsd_m = txq->ift_sds.ifsd_m; 3465 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3466 3467 while (n-- > 0) { 3468 if (do_prefetch) { 3469 prefetch(ifsd_m[(cidx + 3) & mask]); 3470 prefetch(ifsd_m[(cidx + 4) & mask]); 3471 } 3472 if ((m = ifsd_m[cidx]) != NULL) { 3473 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3474 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3475 bus_dmamap_sync(txq->ift_tso_buf_tag, 3476 txq->ift_sds.ifsd_tso_map[cidx], 3477 BUS_DMASYNC_POSTWRITE); 3478 bus_dmamap_unload(txq->ift_tso_buf_tag, 3479 txq->ift_sds.ifsd_tso_map[cidx]); 3480 } else { 3481 bus_dmamap_sync(txq->ift_buf_tag, 3482 txq->ift_sds.ifsd_map[cidx], 3483 BUS_DMASYNC_POSTWRITE); 3484 bus_dmamap_unload(txq->ift_buf_tag, 3485 txq->ift_sds.ifsd_map[cidx]); 3486 } 3487 /* XXX we don't support any drivers that batch packets yet */ 3488 MPASS(m->m_nextpkt == NULL); 3489 m_freem(m); 3490 ifsd_m[cidx] = NULL; 3491 #if MEMORY_LOGGING 3492 txq->ift_dequeued++; 3493 #endif 3494 DBG_COUNTER_INC(tx_frees); 3495 } 3496 if (__predict_false(++cidx == qsize)) { 3497 cidx = 0; 3498 gen = 0; 3499 } 3500 } 3501 txq->ift_cidx = cidx; 3502 txq->ift_gen = gen; 3503 } 3504 3505 static __inline int 3506 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3507 { 3508 int reclaim; 3509 if_ctx_t ctx = txq->ift_ctx; 3510 3511 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3512 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3513 3514 /* 3515 * Need a rate-limiting check so that this isn't called every time 3516 */ 3517 iflib_tx_credits_update(ctx, txq); 3518 reclaim = DESC_RECLAIMABLE(txq); 3519 3520 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3521 #ifdef INVARIANTS 3522 if (iflib_verbose_debug) { 3523 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3524 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3525 reclaim, thresh); 3526 3527 } 3528 #endif 3529 return (0); 3530 } 3531 iflib_tx_desc_free(txq, reclaim); 3532 txq->ift_cleaned += reclaim; 3533 txq->ift_in_use -= reclaim; 3534 3535 return (reclaim); 3536 } 3537 3538 static struct mbuf ** 3539 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3540 { 3541 int next, size; 3542 struct mbuf **items; 3543 3544 size = r->size; 3545 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3546 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3547 3548 prefetch(items[(cidx + offset) & (size-1)]); 3549 if (remaining > 1) { 3550 prefetch2cachelines(&items[next]); 3551 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3552 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3553 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3554 } 3555 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3556 } 3557 3558 static void 3559 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3560 { 3561 3562 ifmp_ring_check_drainage(txq->ift_br, budget); 3563 } 3564 3565 static uint32_t 3566 iflib_txq_can_drain(struct ifmp_ring *r) 3567 { 3568 iflib_txq_t txq = r->cookie; 3569 if_ctx_t ctx = txq->ift_ctx; 3570 3571 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3572 return (1); 3573 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3574 BUS_DMASYNC_POSTREAD); 3575 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3576 false)); 3577 } 3578 3579 static uint32_t 3580 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3581 { 3582 iflib_txq_t txq = r->cookie; 3583 if_ctx_t ctx = txq->ift_ctx; 3584 if_t ifp = ctx->ifc_ifp; 3585 struct mbuf **mp, *m; 3586 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3587 int reclaimed, err, in_use_prev, desc_used; 3588 bool do_prefetch, ring, rang; 3589 3590 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3591 !LINK_ACTIVE(ctx))) { 3592 DBG_COUNTER_INC(txq_drain_notready); 3593 return (0); 3594 } 3595 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3596 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3597 avail = IDXDIFF(pidx, cidx, r->size); 3598 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3599 DBG_COUNTER_INC(txq_drain_flushing); 3600 for (i = 0; i < avail; i++) { 3601 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3602 m_free(r->items[(cidx + i) & (r->size-1)]); 3603 r->items[(cidx + i) & (r->size-1)] = NULL; 3604 } 3605 return (avail); 3606 } 3607 3608 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3609 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3610 CALLOUT_LOCK(txq); 3611 callout_stop(&txq->ift_timer); 3612 CALLOUT_UNLOCK(txq); 3613 DBG_COUNTER_INC(txq_drain_oactive); 3614 return (0); 3615 } 3616 if (reclaimed) 3617 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3618 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3619 count = MIN(avail, TX_BATCH_SIZE); 3620 #ifdef INVARIANTS 3621 if (iflib_verbose_debug) 3622 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3623 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3624 #endif 3625 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3626 avail = TXQ_AVAIL(txq); 3627 err = 0; 3628 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3629 int rem = do_prefetch ? count - i : 0; 3630 3631 mp = _ring_peek_one(r, cidx, i, rem); 3632 MPASS(mp != NULL && *mp != NULL); 3633 if (__predict_false(*mp == (struct mbuf *)txq)) { 3634 consumed++; 3635 reclaimed++; 3636 continue; 3637 } 3638 in_use_prev = txq->ift_in_use; 3639 err = iflib_encap(txq, mp); 3640 if (__predict_false(err)) { 3641 /* no room - bail out */ 3642 if (err == ENOBUFS) 3643 break; 3644 consumed++; 3645 /* we can't send this packet - skip it */ 3646 continue; 3647 } 3648 consumed++; 3649 pkt_sent++; 3650 m = *mp; 3651 DBG_COUNTER_INC(tx_sent); 3652 bytes_sent += m->m_pkthdr.len; 3653 mcast_sent += !!(m->m_flags & M_MCAST); 3654 avail = TXQ_AVAIL(txq); 3655 3656 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3657 desc_used += (txq->ift_in_use - in_use_prev); 3658 ETHER_BPF_MTAP(ifp, m); 3659 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3660 break; 3661 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3662 } 3663 3664 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3665 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3666 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3667 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3668 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3669 if (mcast_sent) 3670 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3671 #ifdef INVARIANTS 3672 if (iflib_verbose_debug) 3673 printf("consumed=%d\n", consumed); 3674 #endif 3675 return (consumed); 3676 } 3677 3678 static uint32_t 3679 iflib_txq_drain_always(struct ifmp_ring *r) 3680 { 3681 return (1); 3682 } 3683 3684 static uint32_t 3685 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3686 { 3687 int i, avail; 3688 struct mbuf **mp; 3689 iflib_txq_t txq; 3690 3691 txq = r->cookie; 3692 3693 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3694 CALLOUT_LOCK(txq); 3695 callout_stop(&txq->ift_timer); 3696 CALLOUT_UNLOCK(txq); 3697 3698 avail = IDXDIFF(pidx, cidx, r->size); 3699 for (i = 0; i < avail; i++) { 3700 mp = _ring_peek_one(r, cidx, i, avail - i); 3701 if (__predict_false(*mp == (struct mbuf *)txq)) 3702 continue; 3703 m_freem(*mp); 3704 DBG_COUNTER_INC(tx_frees); 3705 } 3706 MPASS(ifmp_ring_is_stalled(r) == 0); 3707 return (avail); 3708 } 3709 3710 static void 3711 iflib_ifmp_purge(iflib_txq_t txq) 3712 { 3713 struct ifmp_ring *r; 3714 3715 r = txq->ift_br; 3716 r->drain = iflib_txq_drain_free; 3717 r->can_drain = iflib_txq_drain_always; 3718 3719 ifmp_ring_check_drainage(r, r->size); 3720 3721 r->drain = iflib_txq_drain; 3722 r->can_drain = iflib_txq_can_drain; 3723 } 3724 3725 static void 3726 _task_fn_tx(void *context) 3727 { 3728 iflib_txq_t txq = context; 3729 if_ctx_t ctx = txq->ift_ctx; 3730 #if defined(ALTQ) || defined(DEV_NETMAP) 3731 if_t ifp = ctx->ifc_ifp; 3732 #endif 3733 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3734 3735 #ifdef IFLIB_DIAGNOSTICS 3736 txq->ift_cpu_exec_count[curcpu]++; 3737 #endif 3738 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3739 return; 3740 #ifdef DEV_NETMAP 3741 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3742 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3743 BUS_DMASYNC_POSTREAD); 3744 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3745 netmap_tx_irq(ifp, txq->ift_id); 3746 if (ctx->ifc_flags & IFC_LEGACY) 3747 IFDI_INTR_ENABLE(ctx); 3748 else 3749 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3750 return; 3751 } 3752 #endif 3753 #ifdef ALTQ 3754 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3755 iflib_altq_if_start(ifp); 3756 #endif 3757 if (txq->ift_db_pending) 3758 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3759 else if (!abdicate) 3760 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3761 /* 3762 * When abdicating, we always need to check drainage, not just when we don't enqueue 3763 */ 3764 if (abdicate) 3765 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3766 if (ctx->ifc_flags & IFC_LEGACY) 3767 IFDI_INTR_ENABLE(ctx); 3768 else 3769 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3770 } 3771 3772 static void 3773 _task_fn_rx(void *context) 3774 { 3775 iflib_rxq_t rxq = context; 3776 if_ctx_t ctx = rxq->ifr_ctx; 3777 bool more; 3778 uint16_t budget; 3779 3780 #ifdef IFLIB_DIAGNOSTICS 3781 rxq->ifr_cpu_exec_count[curcpu]++; 3782 #endif 3783 DBG_COUNTER_INC(task_fn_rxs); 3784 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3785 return; 3786 more = true; 3787 #ifdef DEV_NETMAP 3788 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3789 u_int work = 0; 3790 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3791 more = false; 3792 } 3793 } 3794 #endif 3795 budget = ctx->ifc_sysctl_rx_budget; 3796 if (budget == 0) 3797 budget = 16; /* XXX */ 3798 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3799 if (ctx->ifc_flags & IFC_LEGACY) 3800 IFDI_INTR_ENABLE(ctx); 3801 else 3802 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3803 DBG_COUNTER_INC(rx_intr_enables); 3804 } 3805 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3806 return; 3807 if (more) 3808 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3809 } 3810 3811 static void 3812 _task_fn_admin(void *context) 3813 { 3814 if_ctx_t ctx = context; 3815 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3816 iflib_txq_t txq; 3817 int i; 3818 bool oactive, running, do_reset, do_watchdog, in_detach; 3819 uint32_t reset_on = hz / 2; 3820 3821 STATE_LOCK(ctx); 3822 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3823 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3824 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3825 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3826 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3827 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3828 STATE_UNLOCK(ctx); 3829 3830 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3831 return; 3832 if (in_detach) 3833 return; 3834 3835 CTX_LOCK(ctx); 3836 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3837 CALLOUT_LOCK(txq); 3838 callout_stop(&txq->ift_timer); 3839 CALLOUT_UNLOCK(txq); 3840 } 3841 if (do_watchdog) { 3842 ctx->ifc_watchdog_events++; 3843 IFDI_WATCHDOG_RESET(ctx); 3844 } 3845 IFDI_UPDATE_ADMIN_STATUS(ctx); 3846 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3847 #ifdef DEV_NETMAP 3848 reset_on = hz / 2; 3849 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3850 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 3851 #endif 3852 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3853 } 3854 IFDI_LINK_INTR_ENABLE(ctx); 3855 if (do_reset) 3856 iflib_if_init_locked(ctx); 3857 CTX_UNLOCK(ctx); 3858 3859 if (LINK_ACTIVE(ctx) == 0) 3860 return; 3861 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3862 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3863 } 3864 3865 3866 static void 3867 _task_fn_iov(void *context) 3868 { 3869 if_ctx_t ctx = context; 3870 3871 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3872 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3873 return; 3874 3875 CTX_LOCK(ctx); 3876 IFDI_VFLR_HANDLE(ctx); 3877 CTX_UNLOCK(ctx); 3878 } 3879 3880 static int 3881 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3882 { 3883 int err; 3884 if_int_delay_info_t info; 3885 if_ctx_t ctx; 3886 3887 info = (if_int_delay_info_t)arg1; 3888 ctx = info->iidi_ctx; 3889 info->iidi_req = req; 3890 info->iidi_oidp = oidp; 3891 CTX_LOCK(ctx); 3892 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3893 CTX_UNLOCK(ctx); 3894 return (err); 3895 } 3896 3897 /********************************************************************* 3898 * 3899 * IFNET FUNCTIONS 3900 * 3901 **********************************************************************/ 3902 3903 static void 3904 iflib_if_init_locked(if_ctx_t ctx) 3905 { 3906 iflib_stop(ctx); 3907 iflib_init_locked(ctx); 3908 } 3909 3910 3911 static void 3912 iflib_if_init(void *arg) 3913 { 3914 if_ctx_t ctx = arg; 3915 3916 CTX_LOCK(ctx); 3917 iflib_if_init_locked(ctx); 3918 CTX_UNLOCK(ctx); 3919 } 3920 3921 static int 3922 iflib_if_transmit(if_t ifp, struct mbuf *m) 3923 { 3924 if_ctx_t ctx = if_getsoftc(ifp); 3925 3926 iflib_txq_t txq; 3927 int err, qidx; 3928 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3929 3930 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3931 DBG_COUNTER_INC(tx_frees); 3932 m_freem(m); 3933 return (ENETDOWN); 3934 } 3935 3936 MPASS(m->m_nextpkt == NULL); 3937 /* ALTQ-enabled interfaces always use queue 0. */ 3938 qidx = 0; 3939 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3940 qidx = QIDX(ctx, m); 3941 /* 3942 * XXX calculate buf_ring based on flowid (divvy up bits?) 3943 */ 3944 txq = &ctx->ifc_txqs[qidx]; 3945 3946 #ifdef DRIVER_BACKPRESSURE 3947 if (txq->ift_closed) { 3948 while (m != NULL) { 3949 next = m->m_nextpkt; 3950 m->m_nextpkt = NULL; 3951 m_freem(m); 3952 DBG_COUNTER_INC(tx_frees); 3953 m = next; 3954 } 3955 return (ENOBUFS); 3956 } 3957 #endif 3958 #ifdef notyet 3959 qidx = count = 0; 3960 mp = marr; 3961 next = m; 3962 do { 3963 count++; 3964 next = next->m_nextpkt; 3965 } while (next != NULL); 3966 3967 if (count > nitems(marr)) 3968 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3969 /* XXX check nextpkt */ 3970 m_freem(m); 3971 /* XXX simplify for now */ 3972 DBG_COUNTER_INC(tx_frees); 3973 return (ENOBUFS); 3974 } 3975 for (next = m, i = 0; next != NULL; i++) { 3976 mp[i] = next; 3977 next = next->m_nextpkt; 3978 mp[i]->m_nextpkt = NULL; 3979 } 3980 #endif 3981 DBG_COUNTER_INC(tx_seen); 3982 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 3983 3984 if (abdicate) 3985 GROUPTASK_ENQUEUE(&txq->ift_task); 3986 if (err) { 3987 if (!abdicate) 3988 GROUPTASK_ENQUEUE(&txq->ift_task); 3989 /* support forthcoming later */ 3990 #ifdef DRIVER_BACKPRESSURE 3991 txq->ift_closed = TRUE; 3992 #endif 3993 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3994 m_freem(m); 3995 DBG_COUNTER_INC(tx_frees); 3996 } 3997 3998 return (err); 3999 } 4000 4001 #ifdef ALTQ 4002 /* 4003 * The overall approach to integrating iflib with ALTQ is to continue to use 4004 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4005 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4006 * is redundant/unnecessary, but doing so minimizes the amount of 4007 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4008 * redundantly queueing to an intermediate mp_ring is swamped by the 4009 * performance limitations inherent in using ALTQ. 4010 * 4011 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4012 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4013 * given interface. If ALTQ is enabled for an interface, then all 4014 * transmitted packets for that interface will be submitted to the ALTQ 4015 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4016 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4017 * update stats that the iflib machinery handles, and which is sensitve to 4018 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4019 * will be installed as the start routine for use by ALTQ facilities that 4020 * need to trigger queue drains on a scheduled basis. 4021 * 4022 */ 4023 static void 4024 iflib_altq_if_start(if_t ifp) 4025 { 4026 struct ifaltq *ifq = &ifp->if_snd; 4027 struct mbuf *m; 4028 4029 IFQ_LOCK(ifq); 4030 IFQ_DEQUEUE_NOLOCK(ifq, m); 4031 while (m != NULL) { 4032 iflib_if_transmit(ifp, m); 4033 IFQ_DEQUEUE_NOLOCK(ifq, m); 4034 } 4035 IFQ_UNLOCK(ifq); 4036 } 4037 4038 static int 4039 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4040 { 4041 int err; 4042 4043 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4044 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4045 if (err == 0) 4046 iflib_altq_if_start(ifp); 4047 } else 4048 err = iflib_if_transmit(ifp, m); 4049 4050 return (err); 4051 } 4052 #endif /* ALTQ */ 4053 4054 static void 4055 iflib_if_qflush(if_t ifp) 4056 { 4057 if_ctx_t ctx = if_getsoftc(ifp); 4058 iflib_txq_t txq = ctx->ifc_txqs; 4059 int i; 4060 4061 STATE_LOCK(ctx); 4062 ctx->ifc_flags |= IFC_QFLUSH; 4063 STATE_UNLOCK(ctx); 4064 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4065 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4066 iflib_txq_check_drain(txq, 0); 4067 STATE_LOCK(ctx); 4068 ctx->ifc_flags &= ~IFC_QFLUSH; 4069 STATE_UNLOCK(ctx); 4070 4071 /* 4072 * When ALTQ is enabled, this will also take care of purging the 4073 * ALTQ queue(s). 4074 */ 4075 if_qflush(ifp); 4076 } 4077 4078 4079 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4080 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4081 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4082 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM) 4083 4084 static int 4085 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4086 { 4087 if_ctx_t ctx = if_getsoftc(ifp); 4088 struct ifreq *ifr = (struct ifreq *)data; 4089 #if defined(INET) || defined(INET6) 4090 struct ifaddr *ifa = (struct ifaddr *)data; 4091 #endif 4092 bool avoid_reset = false; 4093 int err = 0, reinit = 0, bits; 4094 4095 switch (command) { 4096 case SIOCSIFADDR: 4097 #ifdef INET 4098 if (ifa->ifa_addr->sa_family == AF_INET) 4099 avoid_reset = true; 4100 #endif 4101 #ifdef INET6 4102 if (ifa->ifa_addr->sa_family == AF_INET6) 4103 avoid_reset = true; 4104 #endif 4105 /* 4106 ** Calling init results in link renegotiation, 4107 ** so we avoid doing it when possible. 4108 */ 4109 if (avoid_reset) { 4110 if_setflagbits(ifp, IFF_UP,0); 4111 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4112 reinit = 1; 4113 #ifdef INET 4114 if (!(if_getflags(ifp) & IFF_NOARP)) 4115 arp_ifinit(ifp, ifa); 4116 #endif 4117 } else 4118 err = ether_ioctl(ifp, command, data); 4119 break; 4120 case SIOCSIFMTU: 4121 CTX_LOCK(ctx); 4122 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4123 CTX_UNLOCK(ctx); 4124 break; 4125 } 4126 bits = if_getdrvflags(ifp); 4127 /* stop the driver and free any clusters before proceeding */ 4128 iflib_stop(ctx); 4129 4130 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4131 STATE_LOCK(ctx); 4132 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4133 ctx->ifc_flags |= IFC_MULTISEG; 4134 else 4135 ctx->ifc_flags &= ~IFC_MULTISEG; 4136 STATE_UNLOCK(ctx); 4137 err = if_setmtu(ifp, ifr->ifr_mtu); 4138 } 4139 iflib_init_locked(ctx); 4140 STATE_LOCK(ctx); 4141 if_setdrvflags(ifp, bits); 4142 STATE_UNLOCK(ctx); 4143 CTX_UNLOCK(ctx); 4144 break; 4145 case SIOCSIFFLAGS: 4146 CTX_LOCK(ctx); 4147 if (if_getflags(ifp) & IFF_UP) { 4148 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4149 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4150 (IFF_PROMISC | IFF_ALLMULTI)) { 4151 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4152 } 4153 } else 4154 reinit = 1; 4155 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4156 iflib_stop(ctx); 4157 } 4158 ctx->ifc_if_flags = if_getflags(ifp); 4159 CTX_UNLOCK(ctx); 4160 break; 4161 case SIOCADDMULTI: 4162 case SIOCDELMULTI: 4163 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4164 CTX_LOCK(ctx); 4165 IFDI_INTR_DISABLE(ctx); 4166 IFDI_MULTI_SET(ctx); 4167 IFDI_INTR_ENABLE(ctx); 4168 CTX_UNLOCK(ctx); 4169 } 4170 break; 4171 case SIOCSIFMEDIA: 4172 CTX_LOCK(ctx); 4173 IFDI_MEDIA_SET(ctx); 4174 CTX_UNLOCK(ctx); 4175 /* FALLTHROUGH */ 4176 case SIOCGIFMEDIA: 4177 case SIOCGIFXMEDIA: 4178 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4179 break; 4180 case SIOCGI2C: 4181 { 4182 struct ifi2creq i2c; 4183 4184 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4185 if (err != 0) 4186 break; 4187 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4188 err = EINVAL; 4189 break; 4190 } 4191 if (i2c.len > sizeof(i2c.data)) { 4192 err = EINVAL; 4193 break; 4194 } 4195 4196 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4197 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4198 sizeof(i2c)); 4199 break; 4200 } 4201 case SIOCSIFCAP: 4202 { 4203 int mask, setmask, oldmask; 4204 4205 oldmask = if_getcapenable(ifp); 4206 mask = ifr->ifr_reqcap ^ oldmask; 4207 mask &= ctx->ifc_softc_ctx.isc_capabilities; 4208 setmask = 0; 4209 #ifdef TCP_OFFLOAD 4210 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4211 #endif 4212 setmask |= (mask & IFCAP_FLAGS); 4213 setmask |= (mask & IFCAP_WOL); 4214 4215 /* 4216 * If any RX csum has changed, change all the ones that 4217 * are supported by the driver. 4218 */ 4219 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4220 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4221 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4222 } 4223 4224 /* 4225 * want to ensure that traffic has stopped before we change any of the flags 4226 */ 4227 if (setmask) { 4228 CTX_LOCK(ctx); 4229 bits = if_getdrvflags(ifp); 4230 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4231 iflib_stop(ctx); 4232 STATE_LOCK(ctx); 4233 if_togglecapenable(ifp, setmask); 4234 STATE_UNLOCK(ctx); 4235 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4236 iflib_init_locked(ctx); 4237 STATE_LOCK(ctx); 4238 if_setdrvflags(ifp, bits); 4239 STATE_UNLOCK(ctx); 4240 CTX_UNLOCK(ctx); 4241 } 4242 if_vlancap(ifp); 4243 break; 4244 } 4245 case SIOCGPRIVATE_0: 4246 case SIOCSDRVSPEC: 4247 case SIOCGDRVSPEC: 4248 CTX_LOCK(ctx); 4249 err = IFDI_PRIV_IOCTL(ctx, command, data); 4250 CTX_UNLOCK(ctx); 4251 break; 4252 default: 4253 err = ether_ioctl(ifp, command, data); 4254 break; 4255 } 4256 if (reinit) 4257 iflib_if_init(ctx); 4258 return (err); 4259 } 4260 4261 static uint64_t 4262 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4263 { 4264 if_ctx_t ctx = if_getsoftc(ifp); 4265 4266 return (IFDI_GET_COUNTER(ctx, cnt)); 4267 } 4268 4269 /********************************************************************* 4270 * 4271 * OTHER FUNCTIONS EXPORTED TO THE STACK 4272 * 4273 **********************************************************************/ 4274 4275 static void 4276 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4277 { 4278 if_ctx_t ctx = if_getsoftc(ifp); 4279 4280 if ((void *)ctx != arg) 4281 return; 4282 4283 if ((vtag == 0) || (vtag > 4095)) 4284 return; 4285 4286 CTX_LOCK(ctx); 4287 IFDI_VLAN_REGISTER(ctx, vtag); 4288 /* Re-init to load the changes */ 4289 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4290 iflib_if_init_locked(ctx); 4291 CTX_UNLOCK(ctx); 4292 } 4293 4294 static void 4295 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4296 { 4297 if_ctx_t ctx = if_getsoftc(ifp); 4298 4299 if ((void *)ctx != arg) 4300 return; 4301 4302 if ((vtag == 0) || (vtag > 4095)) 4303 return; 4304 4305 CTX_LOCK(ctx); 4306 IFDI_VLAN_UNREGISTER(ctx, vtag); 4307 /* Re-init to load the changes */ 4308 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4309 iflib_if_init_locked(ctx); 4310 CTX_UNLOCK(ctx); 4311 } 4312 4313 static void 4314 iflib_led_func(void *arg, int onoff) 4315 { 4316 if_ctx_t ctx = arg; 4317 4318 CTX_LOCK(ctx); 4319 IFDI_LED_FUNC(ctx, onoff); 4320 CTX_UNLOCK(ctx); 4321 } 4322 4323 /********************************************************************* 4324 * 4325 * BUS FUNCTION DEFINITIONS 4326 * 4327 **********************************************************************/ 4328 4329 int 4330 iflib_device_probe(device_t dev) 4331 { 4332 const pci_vendor_info_t *ent; 4333 if_shared_ctx_t sctx; 4334 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4335 uint16_t pci_vendor_id; 4336 4337 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4338 return (ENOTSUP); 4339 4340 pci_vendor_id = pci_get_vendor(dev); 4341 pci_device_id = pci_get_device(dev); 4342 pci_subvendor_id = pci_get_subvendor(dev); 4343 pci_subdevice_id = pci_get_subdevice(dev); 4344 pci_rev_id = pci_get_revid(dev); 4345 if (sctx->isc_parse_devinfo != NULL) 4346 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4347 4348 ent = sctx->isc_vendor_info; 4349 while (ent->pvi_vendor_id != 0) { 4350 if (pci_vendor_id != ent->pvi_vendor_id) { 4351 ent++; 4352 continue; 4353 } 4354 if ((pci_device_id == ent->pvi_device_id) && 4355 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4356 (ent->pvi_subvendor_id == 0)) && 4357 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4358 (ent->pvi_subdevice_id == 0)) && 4359 ((pci_rev_id == ent->pvi_rev_id) || 4360 (ent->pvi_rev_id == 0))) { 4361 4362 device_set_desc_copy(dev, ent->pvi_name); 4363 /* this needs to be changed to zero if the bus probing code 4364 * ever stops re-probing on best match because the sctx 4365 * may have its values over written by register calls 4366 * in subsequent probes 4367 */ 4368 return (BUS_PROBE_DEFAULT); 4369 } 4370 ent++; 4371 } 4372 return (ENXIO); 4373 } 4374 4375 int 4376 iflib_device_probe_vendor(device_t dev) 4377 { 4378 int probe; 4379 4380 probe = iflib_device_probe(dev); 4381 if (probe == BUS_PROBE_DEFAULT) 4382 return (BUS_PROBE_VENDOR); 4383 else 4384 return (probe); 4385 } 4386 4387 static void 4388 iflib_reset_qvalues(if_ctx_t ctx) 4389 { 4390 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4391 if_shared_ctx_t sctx = ctx->ifc_sctx; 4392 device_t dev = ctx->ifc_dev; 4393 int i; 4394 4395 if (ctx->ifc_sysctl_ntxqs != 0) 4396 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4397 if (ctx->ifc_sysctl_nrxqs != 0) 4398 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4399 4400 for (i = 0; i < sctx->isc_ntxqs; i++) { 4401 if (ctx->ifc_sysctl_ntxds[i] != 0) 4402 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4403 else 4404 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4405 } 4406 4407 for (i = 0; i < sctx->isc_nrxqs; i++) { 4408 if (ctx->ifc_sysctl_nrxds[i] != 0) 4409 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4410 else 4411 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4412 } 4413 4414 for (i = 0; i < sctx->isc_nrxqs; i++) { 4415 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4416 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4417 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4418 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4419 } 4420 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4421 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4422 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4423 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4424 } 4425 if (!powerof2(scctx->isc_nrxd[i])) { 4426 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4427 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4428 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4429 } 4430 } 4431 4432 for (i = 0; i < sctx->isc_ntxqs; i++) { 4433 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4434 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4435 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4436 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4437 } 4438 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4439 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4440 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4441 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4442 } 4443 if (!powerof2(scctx->isc_ntxd[i])) { 4444 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4445 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4446 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4447 } 4448 } 4449 } 4450 4451 static void 4452 iflib_add_pfil(if_ctx_t ctx) 4453 { 4454 struct pfil_head *pfil; 4455 struct pfil_head_args pa; 4456 iflib_rxq_t rxq; 4457 int i; 4458 4459 pa.pa_version = PFIL_VERSION; 4460 pa.pa_flags = PFIL_IN; 4461 pa.pa_type = PFIL_TYPE_ETHERNET; 4462 pa.pa_headname = ctx->ifc_ifp->if_xname; 4463 pfil = pfil_head_register(&pa); 4464 4465 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4466 rxq->pfil = pfil; 4467 } 4468 } 4469 4470 static void 4471 iflib_rem_pfil(if_ctx_t ctx) 4472 { 4473 struct pfil_head *pfil; 4474 iflib_rxq_t rxq; 4475 int i; 4476 4477 rxq = ctx->ifc_rxqs; 4478 pfil = rxq->pfil; 4479 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4480 rxq->pfil = NULL; 4481 } 4482 pfil_head_unregister(pfil); 4483 } 4484 4485 static uint16_t 4486 get_ctx_core_offset(if_ctx_t ctx) 4487 { 4488 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4489 struct cpu_offset *op; 4490 uint16_t qc; 4491 uint16_t ret = ctx->ifc_sysctl_core_offset; 4492 4493 if (ret != CORE_OFFSET_UNSPECIFIED) 4494 return (ret); 4495 4496 if (ctx->ifc_sysctl_separate_txrx) 4497 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets; 4498 else 4499 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets); 4500 4501 mtx_lock(&cpu_offset_mtx); 4502 SLIST_FOREACH(op, &cpu_offsets, entries) { 4503 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4504 ret = op->offset; 4505 op->offset += qc; 4506 MPASS(op->refcount < UINT_MAX); 4507 op->refcount++; 4508 break; 4509 } 4510 } 4511 if (ret == CORE_OFFSET_UNSPECIFIED) { 4512 ret = 0; 4513 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4514 M_NOWAIT | M_ZERO); 4515 if (op == NULL) { 4516 device_printf(ctx->ifc_dev, 4517 "allocation for cpu offset failed.\n"); 4518 } else { 4519 op->offset = qc; 4520 op->refcount = 1; 4521 CPU_COPY(&ctx->ifc_cpus, &op->set); 4522 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4523 } 4524 } 4525 mtx_unlock(&cpu_offset_mtx); 4526 4527 return (ret); 4528 } 4529 4530 static void 4531 unref_ctx_core_offset(if_ctx_t ctx) 4532 { 4533 struct cpu_offset *op, *top; 4534 4535 mtx_lock(&cpu_offset_mtx); 4536 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4537 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4538 MPASS(op->refcount > 0); 4539 op->refcount--; 4540 if (op->refcount == 0) { 4541 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4542 free(op, M_IFLIB); 4543 } 4544 break; 4545 } 4546 } 4547 mtx_unlock(&cpu_offset_mtx); 4548 } 4549 4550 int 4551 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4552 { 4553 if_ctx_t ctx; 4554 if_t ifp; 4555 if_softc_ctx_t scctx; 4556 kobjop_desc_t kobj_desc; 4557 kobj_method_t *kobj_method; 4558 int err, msix, rid; 4559 uint16_t main_rxq, main_txq; 4560 4561 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4562 4563 if (sc == NULL) { 4564 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4565 device_set_softc(dev, ctx); 4566 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4567 } 4568 4569 ctx->ifc_sctx = sctx; 4570 ctx->ifc_dev = dev; 4571 ctx->ifc_softc = sc; 4572 4573 if ((err = iflib_register(ctx)) != 0) { 4574 device_printf(dev, "iflib_register failed %d\n", err); 4575 goto fail_ctx_free; 4576 } 4577 iflib_add_device_sysctl_pre(ctx); 4578 4579 scctx = &ctx->ifc_softc_ctx; 4580 ifp = ctx->ifc_ifp; 4581 4582 iflib_reset_qvalues(ctx); 4583 CTX_LOCK(ctx); 4584 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4585 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4586 goto fail_unlock; 4587 } 4588 _iflib_pre_assert(scctx); 4589 ctx->ifc_txrx = *scctx->isc_txrx; 4590 4591 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 4592 ctx->ifc_mediap = scctx->isc_media; 4593 4594 #ifdef INVARIANTS 4595 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4596 MPASS(scctx->isc_tx_csum_flags); 4597 #endif 4598 4599 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS); 4600 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4601 4602 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4603 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4604 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4605 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4606 4607 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4608 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4609 4610 /* XXX change for per-queue sizes */ 4611 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4612 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4613 4614 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4615 MAX_SINGLE_PACKET_FRACTION) 4616 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4617 MAX_SINGLE_PACKET_FRACTION); 4618 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4619 MAX_SINGLE_PACKET_FRACTION) 4620 scctx->isc_tx_tso_segments_max = max(1, 4621 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4622 4623 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4624 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4625 /* 4626 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4627 * but some MACs do. 4628 */ 4629 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4630 IP_MAXPACKET)); 4631 /* 4632 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4633 * into account. In the worst case, each of these calls will 4634 * add another mbuf and, thus, the requirement for another DMA 4635 * segment. So for best performance, it doesn't make sense to 4636 * advertize a maximum of TSO segments that typically will 4637 * require defragmentation in iflib_encap(). 4638 */ 4639 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4640 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4641 } 4642 if (scctx->isc_rss_table_size == 0) 4643 scctx->isc_rss_table_size = 64; 4644 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4645 4646 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4647 /* XXX format name */ 4648 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4649 NULL, NULL, "admin"); 4650 4651 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4652 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4653 device_printf(dev, "Unable to fetch CPU list\n"); 4654 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4655 } 4656 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4657 4658 /* 4659 ** Now set up MSI or MSI-X, should return us the number of supported 4660 ** vectors (will be 1 for a legacy interrupt and MSI). 4661 */ 4662 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4663 msix = scctx->isc_vectors; 4664 } else if (scctx->isc_msix_bar != 0) 4665 /* 4666 * The simple fact that isc_msix_bar is not 0 does not mean we 4667 * we have a good value there that is known to work. 4668 */ 4669 msix = iflib_msix_init(ctx); 4670 else { 4671 scctx->isc_vectors = 1; 4672 scctx->isc_ntxqsets = 1; 4673 scctx->isc_nrxqsets = 1; 4674 scctx->isc_intr = IFLIB_INTR_LEGACY; 4675 msix = 0; 4676 } 4677 /* Get memory for the station queues */ 4678 if ((err = iflib_queues_alloc(ctx))) { 4679 device_printf(dev, "Unable to allocate queue memory\n"); 4680 goto fail_intr_free; 4681 } 4682 4683 if ((err = iflib_qset_structures_setup(ctx))) 4684 goto fail_queues; 4685 4686 /* 4687 * Now that we know how many queues there are, get the core offset. 4688 */ 4689 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 4690 4691 /* 4692 * Group taskqueues aren't properly set up until SMP is started, 4693 * so we disable interrupts until we can handle them post 4694 * SI_SUB_SMP. 4695 * 4696 * XXX: disabling interrupts doesn't actually work, at least for 4697 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4698 * we do null handling and depend on this not causing too large an 4699 * interrupt storm. 4700 */ 4701 IFDI_INTR_DISABLE(ctx); 4702 4703 if (msix > 1) { 4704 /* 4705 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 4706 * aren't the default NULL implementation. 4707 */ 4708 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 4709 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4710 kobj_desc); 4711 if (kobj_method == &kobj_desc->deflt) { 4712 device_printf(dev, 4713 "MSI-X requires ifdi_rx_queue_intr_enable method"); 4714 err = EOPNOTSUPP; 4715 goto fail_queues; 4716 } 4717 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 4718 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4719 kobj_desc); 4720 if (kobj_method == &kobj_desc->deflt) { 4721 device_printf(dev, 4722 "MSI-X requires ifdi_tx_queue_intr_enable method"); 4723 err = EOPNOTSUPP; 4724 goto fail_queues; 4725 } 4726 4727 /* 4728 * Assign the MSI-X vectors. 4729 * Note that the default NULL ifdi_msix_intr_assign method will 4730 * fail here, too. 4731 */ 4732 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 4733 if (err != 0) { 4734 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 4735 err); 4736 goto fail_queues; 4737 } 4738 } else { 4739 rid = 0; 4740 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4741 MPASS(msix == 1); 4742 rid = 1; 4743 } 4744 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4745 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4746 goto fail_queues; 4747 } 4748 } 4749 4750 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4751 4752 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4753 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4754 goto fail_detach; 4755 } 4756 4757 /* 4758 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4759 * This must appear after the call to ether_ifattach() because 4760 * ether_ifattach() sets if_hdrlen to the default value. 4761 */ 4762 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4763 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4764 4765 if ((err = iflib_netmap_attach(ctx))) { 4766 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4767 goto fail_detach; 4768 } 4769 *ctxp = ctx; 4770 4771 NETDUMP_SET(ctx->ifc_ifp, iflib); 4772 4773 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4774 iflib_add_device_sysctl_post(ctx); 4775 iflib_add_pfil(ctx); 4776 ctx->ifc_flags |= IFC_INIT_DONE; 4777 CTX_UNLOCK(ctx); 4778 4779 return (0); 4780 4781 fail_detach: 4782 ether_ifdetach(ctx->ifc_ifp); 4783 fail_intr_free: 4784 iflib_free_intr_mem(ctx); 4785 fail_queues: 4786 iflib_tx_structures_free(ctx); 4787 iflib_rx_structures_free(ctx); 4788 IFDI_DETACH(ctx); 4789 fail_unlock: 4790 CTX_UNLOCK(ctx); 4791 fail_ctx_free: 4792 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4793 free(ctx->ifc_softc, M_IFLIB); 4794 free(ctx, M_IFLIB); 4795 return (err); 4796 } 4797 4798 int 4799 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4800 struct iflib_cloneattach_ctx *clctx) 4801 { 4802 int err; 4803 if_ctx_t ctx; 4804 if_t ifp; 4805 if_softc_ctx_t scctx; 4806 int i; 4807 void *sc; 4808 uint16_t main_txq; 4809 uint16_t main_rxq; 4810 4811 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4812 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4813 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4814 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4815 ctx->ifc_flags |= IFC_PSEUDO; 4816 4817 ctx->ifc_sctx = sctx; 4818 ctx->ifc_softc = sc; 4819 ctx->ifc_dev = dev; 4820 4821 if ((err = iflib_register(ctx)) != 0) { 4822 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4823 goto fail_ctx_free; 4824 } 4825 iflib_add_device_sysctl_pre(ctx); 4826 4827 scctx = &ctx->ifc_softc_ctx; 4828 ifp = ctx->ifc_ifp; 4829 4830 iflib_reset_qvalues(ctx); 4831 CTX_LOCK(ctx); 4832 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4833 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4834 goto fail_unlock; 4835 } 4836 if (sctx->isc_flags & IFLIB_GEN_MAC) 4837 ether_gen_addr(ifp, &ctx->ifc_mac); 4838 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4839 clctx->cc_params)) != 0) { 4840 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4841 goto fail_ctx_free; 4842 } 4843 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4844 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4845 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4846 4847 #ifdef INVARIANTS 4848 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4849 MPASS(scctx->isc_tx_csum_flags); 4850 #endif 4851 4852 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4853 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4854 4855 ifp->if_flags |= IFF_NOGROUP; 4856 if (sctx->isc_flags & IFLIB_PSEUDO) { 4857 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4858 4859 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4860 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4861 goto fail_detach; 4862 } 4863 *ctxp = ctx; 4864 4865 /* 4866 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4867 * This must appear after the call to ether_ifattach() because 4868 * ether_ifattach() sets if_hdrlen to the default value. 4869 */ 4870 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4871 if_setifheaderlen(ifp, 4872 sizeof(struct ether_vlan_header)); 4873 4874 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4875 iflib_add_device_sysctl_post(ctx); 4876 ctx->ifc_flags |= IFC_INIT_DONE; 4877 return (0); 4878 } 4879 _iflib_pre_assert(scctx); 4880 ctx->ifc_txrx = *scctx->isc_txrx; 4881 4882 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4883 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4884 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4885 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4886 4887 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4888 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4889 4890 /* XXX change for per-queue sizes */ 4891 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4892 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4893 4894 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4895 MAX_SINGLE_PACKET_FRACTION) 4896 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4897 MAX_SINGLE_PACKET_FRACTION); 4898 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4899 MAX_SINGLE_PACKET_FRACTION) 4900 scctx->isc_tx_tso_segments_max = max(1, 4901 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4902 4903 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4904 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4905 /* 4906 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4907 * but some MACs do. 4908 */ 4909 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4910 IP_MAXPACKET)); 4911 /* 4912 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4913 * into account. In the worst case, each of these calls will 4914 * add another mbuf and, thus, the requirement for another DMA 4915 * segment. So for best performance, it doesn't make sense to 4916 * advertize a maximum of TSO segments that typically will 4917 * require defragmentation in iflib_encap(). 4918 */ 4919 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4920 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4921 } 4922 if (scctx->isc_rss_table_size == 0) 4923 scctx->isc_rss_table_size = 64; 4924 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4925 4926 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4927 /* XXX format name */ 4928 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4929 NULL, NULL, "admin"); 4930 4931 /* XXX --- can support > 1 -- but keep it simple for now */ 4932 scctx->isc_intr = IFLIB_INTR_LEGACY; 4933 4934 /* Get memory for the station queues */ 4935 if ((err = iflib_queues_alloc(ctx))) { 4936 device_printf(dev, "Unable to allocate queue memory\n"); 4937 goto fail_iflib_detach; 4938 } 4939 4940 if ((err = iflib_qset_structures_setup(ctx))) { 4941 device_printf(dev, "qset structure setup failed %d\n", err); 4942 goto fail_queues; 4943 } 4944 4945 /* 4946 * XXX What if anything do we want to do about interrupts? 4947 */ 4948 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4949 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4950 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4951 goto fail_detach; 4952 } 4953 4954 /* 4955 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4956 * This must appear after the call to ether_ifattach() because 4957 * ether_ifattach() sets if_hdrlen to the default value. 4958 */ 4959 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4960 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4961 4962 /* XXX handle more than one queue */ 4963 for (i = 0; i < scctx->isc_nrxqsets; i++) 4964 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4965 4966 *ctxp = ctx; 4967 4968 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4969 iflib_add_device_sysctl_post(ctx); 4970 ctx->ifc_flags |= IFC_INIT_DONE; 4971 CTX_UNLOCK(ctx); 4972 4973 return (0); 4974 fail_detach: 4975 ether_ifdetach(ctx->ifc_ifp); 4976 fail_queues: 4977 iflib_tx_structures_free(ctx); 4978 iflib_rx_structures_free(ctx); 4979 fail_iflib_detach: 4980 IFDI_DETACH(ctx); 4981 fail_unlock: 4982 CTX_UNLOCK(ctx); 4983 fail_ctx_free: 4984 free(ctx->ifc_softc, M_IFLIB); 4985 free(ctx, M_IFLIB); 4986 return (err); 4987 } 4988 4989 int 4990 iflib_pseudo_deregister(if_ctx_t ctx) 4991 { 4992 if_t ifp = ctx->ifc_ifp; 4993 iflib_txq_t txq; 4994 iflib_rxq_t rxq; 4995 int i, j; 4996 struct taskqgroup *tqg; 4997 iflib_fl_t fl; 4998 4999 /* Unregister VLAN events */ 5000 if (ctx->ifc_vlan_attach_event != NULL) 5001 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5002 if (ctx->ifc_vlan_detach_event != NULL) 5003 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5004 5005 ether_ifdetach(ifp); 5006 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5007 CTX_LOCK_DESTROY(ctx); 5008 /* XXX drain any dependent tasks */ 5009 tqg = qgroup_if_io_tqg; 5010 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5011 callout_drain(&txq->ift_timer); 5012 if (txq->ift_task.gt_uniq != NULL) 5013 taskqgroup_detach(tqg, &txq->ift_task); 5014 } 5015 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5016 if (rxq->ifr_task.gt_uniq != NULL) 5017 taskqgroup_detach(tqg, &rxq->ifr_task); 5018 5019 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5020 free(fl->ifl_rx_bitmap, M_IFLIB); 5021 } 5022 tqg = qgroup_if_config_tqg; 5023 if (ctx->ifc_admin_task.gt_uniq != NULL) 5024 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5025 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5026 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5027 5028 if_free(ifp); 5029 5030 iflib_tx_structures_free(ctx); 5031 iflib_rx_structures_free(ctx); 5032 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5033 free(ctx->ifc_softc, M_IFLIB); 5034 free(ctx, M_IFLIB); 5035 return (0); 5036 } 5037 5038 int 5039 iflib_device_attach(device_t dev) 5040 { 5041 if_ctx_t ctx; 5042 if_shared_ctx_t sctx; 5043 5044 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5045 return (ENOTSUP); 5046 5047 pci_enable_busmaster(dev); 5048 5049 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5050 } 5051 5052 int 5053 iflib_device_deregister(if_ctx_t ctx) 5054 { 5055 if_t ifp = ctx->ifc_ifp; 5056 iflib_txq_t txq; 5057 iflib_rxq_t rxq; 5058 device_t dev = ctx->ifc_dev; 5059 int i, j; 5060 struct taskqgroup *tqg; 5061 iflib_fl_t fl; 5062 5063 /* Make sure VLANS are not using driver */ 5064 if (if_vlantrunkinuse(ifp)) { 5065 device_printf(dev, "Vlan in use, detach first\n"); 5066 return (EBUSY); 5067 } 5068 #ifdef PCI_IOV 5069 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5070 device_printf(dev, "SR-IOV in use; detach first.\n"); 5071 return (EBUSY); 5072 } 5073 #endif 5074 5075 STATE_LOCK(ctx); 5076 ctx->ifc_flags |= IFC_IN_DETACH; 5077 STATE_UNLOCK(ctx); 5078 5079 CTX_LOCK(ctx); 5080 iflib_stop(ctx); 5081 CTX_UNLOCK(ctx); 5082 5083 /* Unregister VLAN events */ 5084 if (ctx->ifc_vlan_attach_event != NULL) 5085 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5086 if (ctx->ifc_vlan_detach_event != NULL) 5087 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5088 5089 iflib_netmap_detach(ifp); 5090 ether_ifdetach(ifp); 5091 iflib_rem_pfil(ctx); 5092 if (ctx->ifc_led_dev != NULL) 5093 led_destroy(ctx->ifc_led_dev); 5094 /* XXX drain any dependent tasks */ 5095 tqg = qgroup_if_io_tqg; 5096 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5097 callout_drain(&txq->ift_timer); 5098 if (txq->ift_task.gt_uniq != NULL) 5099 taskqgroup_detach(tqg, &txq->ift_task); 5100 } 5101 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5102 if (rxq->ifr_task.gt_uniq != NULL) 5103 taskqgroup_detach(tqg, &rxq->ifr_task); 5104 5105 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5106 free(fl->ifl_rx_bitmap, M_IFLIB); 5107 } 5108 tqg = qgroup_if_config_tqg; 5109 if (ctx->ifc_admin_task.gt_uniq != NULL) 5110 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5111 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5112 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5113 CTX_LOCK(ctx); 5114 IFDI_DETACH(ctx); 5115 CTX_UNLOCK(ctx); 5116 5117 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5118 CTX_LOCK_DESTROY(ctx); 5119 device_set_softc(ctx->ifc_dev, NULL); 5120 iflib_free_intr_mem(ctx); 5121 5122 bus_generic_detach(dev); 5123 if_free(ifp); 5124 5125 iflib_tx_structures_free(ctx); 5126 iflib_rx_structures_free(ctx); 5127 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5128 free(ctx->ifc_softc, M_IFLIB); 5129 unref_ctx_core_offset(ctx); 5130 STATE_LOCK_DESTROY(ctx); 5131 free(ctx, M_IFLIB); 5132 return (0); 5133 } 5134 5135 static void 5136 iflib_free_intr_mem(if_ctx_t ctx) 5137 { 5138 5139 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5140 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5141 } 5142 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5143 pci_release_msi(ctx->ifc_dev); 5144 } 5145 if (ctx->ifc_msix_mem != NULL) { 5146 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5147 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5148 ctx->ifc_msix_mem = NULL; 5149 } 5150 } 5151 5152 int 5153 iflib_device_detach(device_t dev) 5154 { 5155 if_ctx_t ctx = device_get_softc(dev); 5156 5157 return (iflib_device_deregister(ctx)); 5158 } 5159 5160 int 5161 iflib_device_suspend(device_t dev) 5162 { 5163 if_ctx_t ctx = device_get_softc(dev); 5164 5165 CTX_LOCK(ctx); 5166 IFDI_SUSPEND(ctx); 5167 CTX_UNLOCK(ctx); 5168 5169 return bus_generic_suspend(dev); 5170 } 5171 int 5172 iflib_device_shutdown(device_t dev) 5173 { 5174 if_ctx_t ctx = device_get_softc(dev); 5175 5176 CTX_LOCK(ctx); 5177 IFDI_SHUTDOWN(ctx); 5178 CTX_UNLOCK(ctx); 5179 5180 return bus_generic_suspend(dev); 5181 } 5182 5183 5184 int 5185 iflib_device_resume(device_t dev) 5186 { 5187 if_ctx_t ctx = device_get_softc(dev); 5188 iflib_txq_t txq = ctx->ifc_txqs; 5189 5190 CTX_LOCK(ctx); 5191 IFDI_RESUME(ctx); 5192 iflib_if_init_locked(ctx); 5193 CTX_UNLOCK(ctx); 5194 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5195 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5196 5197 return (bus_generic_resume(dev)); 5198 } 5199 5200 int 5201 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5202 { 5203 int error; 5204 if_ctx_t ctx = device_get_softc(dev); 5205 5206 CTX_LOCK(ctx); 5207 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5208 CTX_UNLOCK(ctx); 5209 5210 return (error); 5211 } 5212 5213 void 5214 iflib_device_iov_uninit(device_t dev) 5215 { 5216 if_ctx_t ctx = device_get_softc(dev); 5217 5218 CTX_LOCK(ctx); 5219 IFDI_IOV_UNINIT(ctx); 5220 CTX_UNLOCK(ctx); 5221 } 5222 5223 int 5224 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5225 { 5226 int error; 5227 if_ctx_t ctx = device_get_softc(dev); 5228 5229 CTX_LOCK(ctx); 5230 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5231 CTX_UNLOCK(ctx); 5232 5233 return (error); 5234 } 5235 5236 /********************************************************************* 5237 * 5238 * MODULE FUNCTION DEFINITIONS 5239 * 5240 **********************************************************************/ 5241 5242 /* 5243 * - Start a fast taskqueue thread for each core 5244 * - Start a taskqueue for control operations 5245 */ 5246 static int 5247 iflib_module_init(void) 5248 { 5249 return (0); 5250 } 5251 5252 static int 5253 iflib_module_event_handler(module_t mod, int what, void *arg) 5254 { 5255 int err; 5256 5257 switch (what) { 5258 case MOD_LOAD: 5259 if ((err = iflib_module_init()) != 0) 5260 return (err); 5261 break; 5262 case MOD_UNLOAD: 5263 return (EBUSY); 5264 default: 5265 return (EOPNOTSUPP); 5266 } 5267 5268 return (0); 5269 } 5270 5271 /********************************************************************* 5272 * 5273 * PUBLIC FUNCTION DEFINITIONS 5274 * ordered as in iflib.h 5275 * 5276 **********************************************************************/ 5277 5278 5279 static void 5280 _iflib_assert(if_shared_ctx_t sctx) 5281 { 5282 int i; 5283 5284 MPASS(sctx->isc_tx_maxsize); 5285 MPASS(sctx->isc_tx_maxsegsize); 5286 5287 MPASS(sctx->isc_rx_maxsize); 5288 MPASS(sctx->isc_rx_nsegments); 5289 MPASS(sctx->isc_rx_maxsegsize); 5290 5291 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5292 for (i = 0; i < sctx->isc_nrxqs; i++) { 5293 MPASS(sctx->isc_nrxd_min[i]); 5294 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5295 MPASS(sctx->isc_nrxd_max[i]); 5296 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5297 MPASS(sctx->isc_nrxd_default[i]); 5298 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5299 } 5300 5301 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5302 for (i = 0; i < sctx->isc_ntxqs; i++) { 5303 MPASS(sctx->isc_ntxd_min[i]); 5304 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5305 MPASS(sctx->isc_ntxd_max[i]); 5306 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5307 MPASS(sctx->isc_ntxd_default[i]); 5308 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5309 } 5310 } 5311 5312 static void 5313 _iflib_pre_assert(if_softc_ctx_t scctx) 5314 { 5315 5316 MPASS(scctx->isc_txrx->ift_txd_encap); 5317 MPASS(scctx->isc_txrx->ift_txd_flush); 5318 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5319 MPASS(scctx->isc_txrx->ift_rxd_available); 5320 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5321 MPASS(scctx->isc_txrx->ift_rxd_refill); 5322 MPASS(scctx->isc_txrx->ift_rxd_flush); 5323 } 5324 5325 static int 5326 iflib_register(if_ctx_t ctx) 5327 { 5328 if_shared_ctx_t sctx = ctx->ifc_sctx; 5329 driver_t *driver = sctx->isc_driver; 5330 device_t dev = ctx->ifc_dev; 5331 if_t ifp; 5332 5333 _iflib_assert(sctx); 5334 5335 CTX_LOCK_INIT(ctx); 5336 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5337 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5338 if (ifp == NULL) { 5339 device_printf(dev, "can not allocate ifnet structure\n"); 5340 return (ENOMEM); 5341 } 5342 5343 /* 5344 * Initialize our context's device specific methods 5345 */ 5346 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5347 kobj_class_compile((kobj_class_t) driver); 5348 driver->refs++; 5349 5350 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5351 if_setsoftc(ifp, ctx); 5352 if_setdev(ifp, dev); 5353 if_setinitfn(ifp, iflib_if_init); 5354 if_setioctlfn(ifp, iflib_if_ioctl); 5355 #ifdef ALTQ 5356 if_setstartfn(ifp, iflib_altq_if_start); 5357 if_settransmitfn(ifp, iflib_altq_if_transmit); 5358 if_setsendqready(ifp); 5359 #else 5360 if_settransmitfn(ifp, iflib_if_transmit); 5361 #endif 5362 if_setqflushfn(ifp, iflib_if_qflush); 5363 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5364 5365 ctx->ifc_vlan_attach_event = 5366 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5367 EVENTHANDLER_PRI_FIRST); 5368 ctx->ifc_vlan_detach_event = 5369 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5370 EVENTHANDLER_PRI_FIRST); 5371 5372 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5373 ctx->ifc_mediap = &ctx->ifc_media; 5374 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5375 iflib_media_change, iflib_media_status); 5376 } 5377 return (0); 5378 } 5379 5380 static int 5381 iflib_queues_alloc(if_ctx_t ctx) 5382 { 5383 if_shared_ctx_t sctx = ctx->ifc_sctx; 5384 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5385 device_t dev = ctx->ifc_dev; 5386 int nrxqsets = scctx->isc_nrxqsets; 5387 int ntxqsets = scctx->isc_ntxqsets; 5388 iflib_txq_t txq; 5389 iflib_rxq_t rxq; 5390 iflib_fl_t fl = NULL; 5391 int i, j, cpu, err, txconf, rxconf; 5392 iflib_dma_info_t ifdip; 5393 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5394 uint32_t *txqsizes = scctx->isc_txqsizes; 5395 uint8_t nrxqs = sctx->isc_nrxqs; 5396 uint8_t ntxqs = sctx->isc_ntxqs; 5397 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5398 caddr_t *vaddrs; 5399 uint64_t *paddrs; 5400 5401 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5402 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5403 5404 /* Allocate the TX ring struct memory */ 5405 if (!(ctx->ifc_txqs = 5406 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5407 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5408 device_printf(dev, "Unable to allocate TX ring memory\n"); 5409 err = ENOMEM; 5410 goto fail; 5411 } 5412 5413 /* Now allocate the RX */ 5414 if (!(ctx->ifc_rxqs = 5415 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5416 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5417 device_printf(dev, "Unable to allocate RX ring memory\n"); 5418 err = ENOMEM; 5419 goto rx_fail; 5420 } 5421 5422 txq = ctx->ifc_txqs; 5423 rxq = ctx->ifc_rxqs; 5424 5425 /* 5426 * XXX handle allocation failure 5427 */ 5428 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5429 /* Set up some basics */ 5430 5431 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5432 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5433 device_printf(dev, 5434 "Unable to allocate TX DMA info memory\n"); 5435 err = ENOMEM; 5436 goto err_tx_desc; 5437 } 5438 txq->ift_ifdi = ifdip; 5439 for (j = 0; j < ntxqs; j++, ifdip++) { 5440 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5441 device_printf(dev, 5442 "Unable to allocate TX descriptors\n"); 5443 err = ENOMEM; 5444 goto err_tx_desc; 5445 } 5446 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5447 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5448 } 5449 txq->ift_ctx = ctx; 5450 txq->ift_id = i; 5451 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5452 txq->ift_br_offset = 1; 5453 } else { 5454 txq->ift_br_offset = 0; 5455 } 5456 /* XXX fix this */ 5457 txq->ift_timer.c_cpu = cpu; 5458 5459 if (iflib_txsd_alloc(txq)) { 5460 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5461 err = ENOMEM; 5462 goto err_tx_desc; 5463 } 5464 5465 /* Initialize the TX lock */ 5466 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5467 device_get_nameunit(dev), txq->ift_id); 5468 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5469 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5470 5471 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5472 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5473 if (err) { 5474 /* XXX free any allocated rings */ 5475 device_printf(dev, "Unable to allocate buf_ring\n"); 5476 goto err_tx_desc; 5477 } 5478 } 5479 5480 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5481 /* Set up some basics */ 5482 5483 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5484 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5485 device_printf(dev, 5486 "Unable to allocate RX DMA info memory\n"); 5487 err = ENOMEM; 5488 goto err_tx_desc; 5489 } 5490 5491 rxq->ifr_ifdi = ifdip; 5492 /* XXX this needs to be changed if #rx queues != #tx queues */ 5493 rxq->ifr_ntxqirq = 1; 5494 rxq->ifr_txqid[0] = i; 5495 for (j = 0; j < nrxqs; j++, ifdip++) { 5496 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5497 device_printf(dev, 5498 "Unable to allocate RX descriptors\n"); 5499 err = ENOMEM; 5500 goto err_tx_desc; 5501 } 5502 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5503 } 5504 rxq->ifr_ctx = ctx; 5505 rxq->ifr_id = i; 5506 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5507 rxq->ifr_fl_offset = 1; 5508 } else { 5509 rxq->ifr_fl_offset = 0; 5510 } 5511 rxq->ifr_nfl = nfree_lists; 5512 if (!(fl = 5513 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5514 device_printf(dev, "Unable to allocate free list memory\n"); 5515 err = ENOMEM; 5516 goto err_tx_desc; 5517 } 5518 rxq->ifr_fl = fl; 5519 for (j = 0; j < nfree_lists; j++) { 5520 fl[j].ifl_rxq = rxq; 5521 fl[j].ifl_id = j; 5522 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5523 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5524 } 5525 /* Allocate receive buffers for the ring */ 5526 if (iflib_rxsd_alloc(rxq)) { 5527 device_printf(dev, 5528 "Critical Failure setting up receive buffers\n"); 5529 err = ENOMEM; 5530 goto err_rx_desc; 5531 } 5532 5533 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5534 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5535 M_WAITOK); 5536 } 5537 5538 /* TXQs */ 5539 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5540 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5541 for (i = 0; i < ntxqsets; i++) { 5542 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5543 5544 for (j = 0; j < ntxqs; j++, di++) { 5545 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5546 paddrs[i*ntxqs + j] = di->idi_paddr; 5547 } 5548 } 5549 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5550 device_printf(ctx->ifc_dev, 5551 "Unable to allocate device TX queue\n"); 5552 iflib_tx_structures_free(ctx); 5553 free(vaddrs, M_IFLIB); 5554 free(paddrs, M_IFLIB); 5555 goto err_rx_desc; 5556 } 5557 free(vaddrs, M_IFLIB); 5558 free(paddrs, M_IFLIB); 5559 5560 /* RXQs */ 5561 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5562 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5563 for (i = 0; i < nrxqsets; i++) { 5564 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5565 5566 for (j = 0; j < nrxqs; j++, di++) { 5567 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5568 paddrs[i*nrxqs + j] = di->idi_paddr; 5569 } 5570 } 5571 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5572 device_printf(ctx->ifc_dev, 5573 "Unable to allocate device RX queue\n"); 5574 iflib_tx_structures_free(ctx); 5575 free(vaddrs, M_IFLIB); 5576 free(paddrs, M_IFLIB); 5577 goto err_rx_desc; 5578 } 5579 free(vaddrs, M_IFLIB); 5580 free(paddrs, M_IFLIB); 5581 5582 return (0); 5583 5584 /* XXX handle allocation failure changes */ 5585 err_rx_desc: 5586 err_tx_desc: 5587 rx_fail: 5588 if (ctx->ifc_rxqs != NULL) 5589 free(ctx->ifc_rxqs, M_IFLIB); 5590 ctx->ifc_rxqs = NULL; 5591 if (ctx->ifc_txqs != NULL) 5592 free(ctx->ifc_txqs, M_IFLIB); 5593 ctx->ifc_txqs = NULL; 5594 fail: 5595 return (err); 5596 } 5597 5598 static int 5599 iflib_tx_structures_setup(if_ctx_t ctx) 5600 { 5601 iflib_txq_t txq = ctx->ifc_txqs; 5602 int i; 5603 5604 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5605 iflib_txq_setup(txq); 5606 5607 return (0); 5608 } 5609 5610 static void 5611 iflib_tx_structures_free(if_ctx_t ctx) 5612 { 5613 iflib_txq_t txq = ctx->ifc_txqs; 5614 if_shared_ctx_t sctx = ctx->ifc_sctx; 5615 int i, j; 5616 5617 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5618 iflib_txq_destroy(txq); 5619 for (j = 0; j < sctx->isc_ntxqs; j++) 5620 iflib_dma_free(&txq->ift_ifdi[j]); 5621 } 5622 free(ctx->ifc_txqs, M_IFLIB); 5623 ctx->ifc_txqs = NULL; 5624 IFDI_QUEUES_FREE(ctx); 5625 } 5626 5627 /********************************************************************* 5628 * 5629 * Initialize all receive rings. 5630 * 5631 **********************************************************************/ 5632 static int 5633 iflib_rx_structures_setup(if_ctx_t ctx) 5634 { 5635 iflib_rxq_t rxq = ctx->ifc_rxqs; 5636 int q; 5637 #if defined(INET6) || defined(INET) 5638 int err, i; 5639 #endif 5640 5641 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5642 #if defined(INET6) || defined(INET) 5643 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) { 5644 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5645 TCP_LRO_ENTRIES, min(1024, 5646 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 5647 if (err != 0) { 5648 device_printf(ctx->ifc_dev, 5649 "LRO Initialization failed!\n"); 5650 goto fail; 5651 } 5652 } 5653 #endif 5654 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5655 } 5656 return (0); 5657 #if defined(INET6) || defined(INET) 5658 fail: 5659 /* 5660 * Free LRO resources allocated so far, we will only handle 5661 * the rings that completed, the failing case will have 5662 * cleaned up for itself. 'q' failed, so its the terminus. 5663 */ 5664 rxq = ctx->ifc_rxqs; 5665 for (i = 0; i < q; ++i, rxq++) { 5666 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5667 tcp_lro_free(&rxq->ifr_lc); 5668 } 5669 return (err); 5670 #endif 5671 } 5672 5673 /********************************************************************* 5674 * 5675 * Free all receive rings. 5676 * 5677 **********************************************************************/ 5678 static void 5679 iflib_rx_structures_free(if_ctx_t ctx) 5680 { 5681 iflib_rxq_t rxq = ctx->ifc_rxqs; 5682 int i; 5683 5684 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5685 iflib_rx_sds_free(rxq); 5686 #if defined(INET6) || defined(INET) 5687 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5688 tcp_lro_free(&rxq->ifr_lc); 5689 #endif 5690 } 5691 free(ctx->ifc_rxqs, M_IFLIB); 5692 ctx->ifc_rxqs = NULL; 5693 } 5694 5695 static int 5696 iflib_qset_structures_setup(if_ctx_t ctx) 5697 { 5698 int err; 5699 5700 /* 5701 * It is expected that the caller takes care of freeing queues if this 5702 * fails. 5703 */ 5704 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5705 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5706 return (err); 5707 } 5708 5709 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5710 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5711 5712 return (err); 5713 } 5714 5715 int 5716 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5717 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5718 { 5719 5720 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5721 } 5722 5723 #ifdef SMP 5724 static int 5725 find_nth(if_ctx_t ctx, int qid) 5726 { 5727 cpuset_t cpus; 5728 int i, cpuid, eqid, count; 5729 5730 CPU_COPY(&ctx->ifc_cpus, &cpus); 5731 count = CPU_COUNT(&cpus); 5732 eqid = qid % count; 5733 /* clear up to the qid'th bit */ 5734 for (i = 0; i < eqid; i++) { 5735 cpuid = CPU_FFS(&cpus); 5736 MPASS(cpuid != 0); 5737 CPU_CLR(cpuid-1, &cpus); 5738 } 5739 cpuid = CPU_FFS(&cpus); 5740 MPASS(cpuid != 0); 5741 return (cpuid-1); 5742 } 5743 5744 #ifdef SCHED_ULE 5745 extern struct cpu_group *cpu_top; /* CPU topology */ 5746 5747 static int 5748 find_child_with_core(int cpu, struct cpu_group *grp) 5749 { 5750 int i; 5751 5752 if (grp->cg_children == 0) 5753 return -1; 5754 5755 MPASS(grp->cg_child); 5756 for (i = 0; i < grp->cg_children; i++) { 5757 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5758 return i; 5759 } 5760 5761 return -1; 5762 } 5763 5764 /* 5765 * Find the nth "close" core to the specified core 5766 * "close" is defined as the deepest level that shares 5767 * at least an L2 cache. With threads, this will be 5768 * threads on the same core. If the shared cache is L3 5769 * or higher, simply returns the same core. 5770 */ 5771 static int 5772 find_close_core(int cpu, int core_offset) 5773 { 5774 struct cpu_group *grp; 5775 int i; 5776 int fcpu; 5777 cpuset_t cs; 5778 5779 grp = cpu_top; 5780 if (grp == NULL) 5781 return cpu; 5782 i = 0; 5783 while ((i = find_child_with_core(cpu, grp)) != -1) { 5784 /* If the child only has one cpu, don't descend */ 5785 if (grp->cg_child[i].cg_count <= 1) 5786 break; 5787 grp = &grp->cg_child[i]; 5788 } 5789 5790 /* If they don't share at least an L2 cache, use the same CPU */ 5791 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5792 return cpu; 5793 5794 /* Now pick one */ 5795 CPU_COPY(&grp->cg_mask, &cs); 5796 5797 /* Add the selected CPU offset to core offset. */ 5798 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5799 if (fcpu - 1 == cpu) 5800 break; 5801 CPU_CLR(fcpu - 1, &cs); 5802 } 5803 MPASS(fcpu); 5804 5805 core_offset += i; 5806 5807 CPU_COPY(&grp->cg_mask, &cs); 5808 for (i = core_offset % grp->cg_count; i > 0; i--) { 5809 MPASS(CPU_FFS(&cs)); 5810 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5811 } 5812 MPASS(CPU_FFS(&cs)); 5813 return CPU_FFS(&cs) - 1; 5814 } 5815 #else 5816 static int 5817 find_close_core(int cpu, int core_offset __unused) 5818 { 5819 return cpu; 5820 } 5821 #endif 5822 5823 static int 5824 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5825 { 5826 switch (type) { 5827 case IFLIB_INTR_TX: 5828 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5829 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5830 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5831 case IFLIB_INTR_RX: 5832 case IFLIB_INTR_RXTX: 5833 /* RX queues get the specified core */ 5834 return qid / CPU_COUNT(&ctx->ifc_cpus); 5835 default: 5836 return -1; 5837 } 5838 } 5839 #else 5840 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5841 #define find_close_core(cpuid, tid) CPU_FIRST() 5842 #define find_nth(ctx, gid) CPU_FIRST() 5843 #endif 5844 5845 /* Just to avoid copy/paste */ 5846 static inline int 5847 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5848 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5849 const char *name) 5850 { 5851 device_t dev; 5852 int co, cpuid, err, tid; 5853 5854 dev = ctx->ifc_dev; 5855 co = ctx->ifc_sysctl_core_offset; 5856 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX) 5857 co += ctx->ifc_softc_ctx.isc_nrxqsets; 5858 cpuid = find_nth(ctx, qid + co); 5859 tid = get_core_offset(ctx, type, qid); 5860 if (tid < 0) { 5861 device_printf(dev, "get_core_offset failed\n"); 5862 return (EOPNOTSUPP); 5863 } 5864 cpuid = find_close_core(cpuid, tid); 5865 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 5866 name); 5867 if (err) { 5868 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 5869 return (err); 5870 } 5871 #ifdef notyet 5872 if (cpuid > ctx->ifc_cpuid_highest) 5873 ctx->ifc_cpuid_highest = cpuid; 5874 #endif 5875 return (0); 5876 } 5877 5878 int 5879 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5880 iflib_intr_type_t type, driver_filter_t *filter, 5881 void *filter_arg, int qid, const char *name) 5882 { 5883 device_t dev; 5884 struct grouptask *gtask; 5885 struct taskqgroup *tqg; 5886 iflib_filter_info_t info; 5887 gtask_fn_t *fn; 5888 int tqrid, err; 5889 driver_filter_t *intr_fast; 5890 void *q; 5891 5892 info = &ctx->ifc_filter_info; 5893 tqrid = rid; 5894 5895 switch (type) { 5896 /* XXX merge tx/rx for netmap? */ 5897 case IFLIB_INTR_TX: 5898 q = &ctx->ifc_txqs[qid]; 5899 info = &ctx->ifc_txqs[qid].ift_filter_info; 5900 gtask = &ctx->ifc_txqs[qid].ift_task; 5901 tqg = qgroup_if_io_tqg; 5902 fn = _task_fn_tx; 5903 intr_fast = iflib_fast_intr; 5904 GROUPTASK_INIT(gtask, 0, fn, q); 5905 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5906 break; 5907 case IFLIB_INTR_RX: 5908 q = &ctx->ifc_rxqs[qid]; 5909 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5910 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5911 tqg = qgroup_if_io_tqg; 5912 fn = _task_fn_rx; 5913 intr_fast = iflib_fast_intr; 5914 GROUPTASK_INIT(gtask, 0, fn, q); 5915 break; 5916 case IFLIB_INTR_RXTX: 5917 q = &ctx->ifc_rxqs[qid]; 5918 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5919 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5920 tqg = qgroup_if_io_tqg; 5921 fn = _task_fn_rx; 5922 intr_fast = iflib_fast_intr_rxtx; 5923 GROUPTASK_INIT(gtask, 0, fn, q); 5924 break; 5925 case IFLIB_INTR_ADMIN: 5926 q = ctx; 5927 tqrid = -1; 5928 info = &ctx->ifc_filter_info; 5929 gtask = &ctx->ifc_admin_task; 5930 tqg = qgroup_if_config_tqg; 5931 fn = _task_fn_admin; 5932 intr_fast = iflib_fast_intr_ctx; 5933 break; 5934 default: 5935 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 5936 __func__); 5937 return (EINVAL); 5938 } 5939 5940 info->ifi_filter = filter; 5941 info->ifi_filter_arg = filter_arg; 5942 info->ifi_task = gtask; 5943 info->ifi_ctx = q; 5944 5945 dev = ctx->ifc_dev; 5946 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5947 if (err != 0) { 5948 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 5949 return (err); 5950 } 5951 if (type == IFLIB_INTR_ADMIN) 5952 return (0); 5953 5954 if (tqrid != -1) { 5955 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 5956 q, name); 5957 if (err) 5958 return (err); 5959 } else { 5960 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 5961 } 5962 5963 return (0); 5964 } 5965 5966 void 5967 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 5968 { 5969 struct grouptask *gtask; 5970 struct taskqgroup *tqg; 5971 gtask_fn_t *fn; 5972 void *q; 5973 int err; 5974 5975 switch (type) { 5976 case IFLIB_INTR_TX: 5977 q = &ctx->ifc_txqs[qid]; 5978 gtask = &ctx->ifc_txqs[qid].ift_task; 5979 tqg = qgroup_if_io_tqg; 5980 fn = _task_fn_tx; 5981 break; 5982 case IFLIB_INTR_RX: 5983 q = &ctx->ifc_rxqs[qid]; 5984 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5985 tqg = qgroup_if_io_tqg; 5986 fn = _task_fn_rx; 5987 break; 5988 case IFLIB_INTR_IOV: 5989 q = ctx; 5990 gtask = &ctx->ifc_vflr_task; 5991 tqg = qgroup_if_config_tqg; 5992 fn = _task_fn_iov; 5993 break; 5994 default: 5995 panic("unknown net intr type"); 5996 } 5997 GROUPTASK_INIT(gtask, 0, fn, q); 5998 if (irq != NULL) { 5999 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6000 q, name); 6001 if (err) 6002 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 6003 irq->ii_res, name); 6004 } else { 6005 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 6006 } 6007 } 6008 6009 void 6010 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6011 { 6012 6013 if (irq->ii_tag) 6014 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6015 6016 if (irq->ii_res) 6017 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6018 rman_get_rid(irq->ii_res), irq->ii_res); 6019 } 6020 6021 static int 6022 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6023 { 6024 iflib_txq_t txq = ctx->ifc_txqs; 6025 iflib_rxq_t rxq = ctx->ifc_rxqs; 6026 if_irq_t irq = &ctx->ifc_legacy_irq; 6027 iflib_filter_info_t info; 6028 device_t dev; 6029 struct grouptask *gtask; 6030 struct resource *res; 6031 struct taskqgroup *tqg; 6032 gtask_fn_t *fn; 6033 void *q; 6034 int err, tqrid; 6035 6036 q = &ctx->ifc_rxqs[0]; 6037 info = &rxq[0].ifr_filter_info; 6038 gtask = &rxq[0].ifr_task; 6039 tqg = qgroup_if_io_tqg; 6040 tqrid = *rid; 6041 fn = _task_fn_rx; 6042 6043 ctx->ifc_flags |= IFC_LEGACY; 6044 info->ifi_filter = filter; 6045 info->ifi_filter_arg = filter_arg; 6046 info->ifi_task = gtask; 6047 info->ifi_ctx = q; 6048 6049 dev = ctx->ifc_dev; 6050 /* We allocate a single interrupt resource */ 6051 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_rxtx, 6052 NULL, info, name)) != 0) 6053 return (err); 6054 GROUPTASK_INIT(gtask, 0, fn, q); 6055 res = irq->ii_res; 6056 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6057 6058 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6059 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6060 "tx"); 6061 return (0); 6062 } 6063 6064 void 6065 iflib_led_create(if_ctx_t ctx) 6066 { 6067 6068 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6069 device_get_nameunit(ctx->ifc_dev)); 6070 } 6071 6072 void 6073 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6074 { 6075 6076 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6077 } 6078 6079 void 6080 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6081 { 6082 6083 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6084 } 6085 6086 void 6087 iflib_admin_intr_deferred(if_ctx_t ctx) 6088 { 6089 #ifdef INVARIANTS 6090 struct grouptask *gtask; 6091 6092 gtask = &ctx->ifc_admin_task; 6093 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 6094 #endif 6095 6096 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6097 } 6098 6099 void 6100 iflib_iov_intr_deferred(if_ctx_t ctx) 6101 { 6102 6103 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6104 } 6105 6106 void 6107 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6108 { 6109 6110 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6111 name); 6112 } 6113 6114 void 6115 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6116 const char *name) 6117 { 6118 6119 GROUPTASK_INIT(gtask, 0, fn, ctx); 6120 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6121 name); 6122 } 6123 6124 void 6125 iflib_config_gtask_deinit(struct grouptask *gtask) 6126 { 6127 6128 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6129 } 6130 6131 void 6132 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6133 { 6134 if_t ifp = ctx->ifc_ifp; 6135 iflib_txq_t txq = ctx->ifc_txqs; 6136 6137 if_setbaudrate(ifp, baudrate); 6138 if (baudrate >= IF_Gbps(10)) { 6139 STATE_LOCK(ctx); 6140 ctx->ifc_flags |= IFC_PREFETCH; 6141 STATE_UNLOCK(ctx); 6142 } 6143 /* If link down, disable watchdog */ 6144 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6145 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6146 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6147 } 6148 ctx->ifc_link_state = link_state; 6149 if_link_state_change(ifp, link_state); 6150 } 6151 6152 static int 6153 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6154 { 6155 int credits; 6156 #ifdef INVARIANTS 6157 int credits_pre = txq->ift_cidx_processed; 6158 #endif 6159 6160 if (ctx->isc_txd_credits_update == NULL) 6161 return (0); 6162 6163 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6164 BUS_DMASYNC_POSTREAD); 6165 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6166 return (0); 6167 6168 txq->ift_processed += credits; 6169 txq->ift_cidx_processed += credits; 6170 6171 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6172 if (txq->ift_cidx_processed >= txq->ift_size) 6173 txq->ift_cidx_processed -= txq->ift_size; 6174 return (credits); 6175 } 6176 6177 static int 6178 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6179 { 6180 iflib_fl_t fl; 6181 u_int i; 6182 6183 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6184 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6185 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6186 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6187 budget)); 6188 } 6189 6190 void 6191 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6192 const char *description, if_int_delay_info_t info, 6193 int offset, int value) 6194 { 6195 info->iidi_ctx = ctx; 6196 info->iidi_offset = offset; 6197 info->iidi_value = value; 6198 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6199 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6200 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 6201 info, 0, iflib_sysctl_int_delay, "I", description); 6202 } 6203 6204 struct sx * 6205 iflib_ctx_lock_get(if_ctx_t ctx) 6206 { 6207 6208 return (&ctx->ifc_ctx_sx); 6209 } 6210 6211 static int 6212 iflib_msix_init(if_ctx_t ctx) 6213 { 6214 device_t dev = ctx->ifc_dev; 6215 if_shared_ctx_t sctx = ctx->ifc_sctx; 6216 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6217 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6218 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6219 6220 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6221 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6222 6223 if (bootverbose) 6224 device_printf(dev, "msix_init qsets capped at %d\n", 6225 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6226 6227 /* Override by tuneable */ 6228 if (scctx->isc_disable_msix) 6229 goto msi; 6230 6231 /* First try MSI-X */ 6232 if ((msgs = pci_msix_count(dev)) == 0) { 6233 if (bootverbose) 6234 device_printf(dev, "MSI-X not supported or disabled\n"); 6235 goto msi; 6236 } 6237 6238 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6239 /* 6240 * bar == -1 => "trust me I know what I'm doing" 6241 * Some drivers are for hardware that is so shoddily 6242 * documented that no one knows which bars are which 6243 * so the developer has to map all bars. This hack 6244 * allows shoddy garbage to use MSI-X in this framework. 6245 */ 6246 if (bar != -1) { 6247 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6248 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6249 if (ctx->ifc_msix_mem == NULL) { 6250 device_printf(dev, "Unable to map MSI-X table\n"); 6251 goto msi; 6252 } 6253 } 6254 6255 admincnt = sctx->isc_admin_intrcnt; 6256 #if IFLIB_DEBUG 6257 /* use only 1 qset in debug mode */ 6258 queuemsgs = min(msgs - admincnt, 1); 6259 #else 6260 queuemsgs = msgs - admincnt; 6261 #endif 6262 #ifdef RSS 6263 queues = imin(queuemsgs, rss_getnumbuckets()); 6264 #else 6265 queues = queuemsgs; 6266 #endif 6267 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6268 if (bootverbose) 6269 device_printf(dev, 6270 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6271 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6272 #ifdef RSS 6273 /* If we're doing RSS, clamp at the number of RSS buckets */ 6274 if (queues > rss_getnumbuckets()) 6275 queues = rss_getnumbuckets(); 6276 #endif 6277 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6278 rx_queues = iflib_num_rx_queues; 6279 else 6280 rx_queues = queues; 6281 6282 if (rx_queues > scctx->isc_nrxqsets) 6283 rx_queues = scctx->isc_nrxqsets; 6284 6285 /* 6286 * We want this to be all logical CPUs by default 6287 */ 6288 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6289 tx_queues = iflib_num_tx_queues; 6290 else 6291 tx_queues = mp_ncpus; 6292 6293 if (tx_queues > scctx->isc_ntxqsets) 6294 tx_queues = scctx->isc_ntxqsets; 6295 6296 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6297 #ifdef INVARIANTS 6298 if (tx_queues != rx_queues) 6299 device_printf(dev, 6300 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6301 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6302 #endif 6303 tx_queues = min(rx_queues, tx_queues); 6304 rx_queues = min(rx_queues, tx_queues); 6305 } 6306 6307 vectors = rx_queues + admincnt; 6308 if (msgs < vectors) { 6309 device_printf(dev, 6310 "insufficient number of MSI-X vectors " 6311 "(supported %d, need %d)\n", msgs, vectors); 6312 goto msi; 6313 } 6314 6315 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6316 tx_queues); 6317 msgs = vectors; 6318 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6319 if (vectors != msgs) { 6320 device_printf(dev, 6321 "Unable to allocate sufficient MSI-X vectors " 6322 "(got %d, need %d)\n", vectors, msgs); 6323 pci_release_msi(dev); 6324 if (bar != -1) { 6325 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6326 ctx->ifc_msix_mem); 6327 ctx->ifc_msix_mem = NULL; 6328 } 6329 goto msi; 6330 } 6331 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6332 vectors); 6333 scctx->isc_vectors = vectors; 6334 scctx->isc_nrxqsets = rx_queues; 6335 scctx->isc_ntxqsets = tx_queues; 6336 scctx->isc_intr = IFLIB_INTR_MSIX; 6337 6338 return (vectors); 6339 } else { 6340 device_printf(dev, 6341 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6342 err); 6343 if (bar != -1) { 6344 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6345 ctx->ifc_msix_mem); 6346 ctx->ifc_msix_mem = NULL; 6347 } 6348 } 6349 6350 msi: 6351 vectors = pci_msi_count(dev); 6352 scctx->isc_nrxqsets = 1; 6353 scctx->isc_ntxqsets = 1; 6354 scctx->isc_vectors = vectors; 6355 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6356 device_printf(dev,"Using an MSI interrupt\n"); 6357 scctx->isc_intr = IFLIB_INTR_MSI; 6358 } else { 6359 scctx->isc_vectors = 1; 6360 device_printf(dev,"Using a Legacy interrupt\n"); 6361 scctx->isc_intr = IFLIB_INTR_LEGACY; 6362 } 6363 6364 return (vectors); 6365 } 6366 6367 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6368 6369 static int 6370 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6371 { 6372 int rc; 6373 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6374 struct sbuf *sb; 6375 const char *ring_state = "UNKNOWN"; 6376 6377 /* XXX needed ? */ 6378 rc = sysctl_wire_old_buffer(req, 0); 6379 MPASS(rc == 0); 6380 if (rc != 0) 6381 return (rc); 6382 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6383 MPASS(sb != NULL); 6384 if (sb == NULL) 6385 return (ENOMEM); 6386 if (state[3] <= 3) 6387 ring_state = ring_states[state[3]]; 6388 6389 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6390 state[0], state[1], state[2], ring_state); 6391 rc = sbuf_finish(sb); 6392 sbuf_delete(sb); 6393 return(rc); 6394 } 6395 6396 enum iflib_ndesc_handler { 6397 IFLIB_NTXD_HANDLER, 6398 IFLIB_NRXD_HANDLER, 6399 }; 6400 6401 static int 6402 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6403 { 6404 if_ctx_t ctx = (void *)arg1; 6405 enum iflib_ndesc_handler type = arg2; 6406 char buf[256] = {0}; 6407 qidx_t *ndesc; 6408 char *p, *next; 6409 int nqs, rc, i; 6410 6411 nqs = 8; 6412 switch(type) { 6413 case IFLIB_NTXD_HANDLER: 6414 ndesc = ctx->ifc_sysctl_ntxds; 6415 if (ctx->ifc_sctx) 6416 nqs = ctx->ifc_sctx->isc_ntxqs; 6417 break; 6418 case IFLIB_NRXD_HANDLER: 6419 ndesc = ctx->ifc_sysctl_nrxds; 6420 if (ctx->ifc_sctx) 6421 nqs = ctx->ifc_sctx->isc_nrxqs; 6422 break; 6423 default: 6424 printf("%s: unhandled type\n", __func__); 6425 return (EINVAL); 6426 } 6427 if (nqs == 0) 6428 nqs = 8; 6429 6430 for (i=0; i<8; i++) { 6431 if (i >= nqs) 6432 break; 6433 if (i) 6434 strcat(buf, ","); 6435 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6436 } 6437 6438 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6439 if (rc || req->newptr == NULL) 6440 return rc; 6441 6442 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6443 i++, p = strsep(&next, " ,")) { 6444 ndesc[i] = strtoul(p, NULL, 10); 6445 } 6446 6447 return(rc); 6448 } 6449 6450 #define NAME_BUFLEN 32 6451 static void 6452 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6453 { 6454 device_t dev = iflib_get_dev(ctx); 6455 struct sysctl_oid_list *child, *oid_list; 6456 struct sysctl_ctx_list *ctx_list; 6457 struct sysctl_oid *node; 6458 6459 ctx_list = device_get_sysctl_ctx(dev); 6460 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6461 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6462 CTLFLAG_RD, NULL, "IFLIB fields"); 6463 oid_list = SYSCTL_CHILDREN(node); 6464 6465 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6466 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6467 "driver version"); 6468 6469 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6470 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6471 "# of txqs to use, 0 => use default #"); 6472 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6473 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6474 "# of rxqs to use, 0 => use default #"); 6475 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6476 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6477 "permit #txq != #rxq"); 6478 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6479 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6480 "disable MSI-X (default 0)"); 6481 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6482 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6483 "set the RX budget"); 6484 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6485 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6486 "cause TX to abdicate instead of running to completion"); 6487 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6488 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6489 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6490 "offset to start using cores at"); 6491 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6492 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6493 "use separate cores for TX and RX"); 6494 6495 /* XXX change for per-queue sizes */ 6496 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6497 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6498 mp_ndesc_handler, "A", 6499 "list of # of TX descriptors to use, 0 = use default #"); 6500 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6501 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6502 mp_ndesc_handler, "A", 6503 "list of # of RX descriptors to use, 0 = use default #"); 6504 } 6505 6506 static void 6507 iflib_add_device_sysctl_post(if_ctx_t ctx) 6508 { 6509 if_shared_ctx_t sctx = ctx->ifc_sctx; 6510 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6511 device_t dev = iflib_get_dev(ctx); 6512 struct sysctl_oid_list *child; 6513 struct sysctl_ctx_list *ctx_list; 6514 iflib_fl_t fl; 6515 iflib_txq_t txq; 6516 iflib_rxq_t rxq; 6517 int i, j; 6518 char namebuf[NAME_BUFLEN]; 6519 char *qfmt; 6520 struct sysctl_oid *queue_node, *fl_node, *node; 6521 struct sysctl_oid_list *queue_list, *fl_list; 6522 ctx_list = device_get_sysctl_ctx(dev); 6523 6524 node = ctx->ifc_sysctl_node; 6525 child = SYSCTL_CHILDREN(node); 6526 6527 if (scctx->isc_ntxqsets > 100) 6528 qfmt = "txq%03d"; 6529 else if (scctx->isc_ntxqsets > 10) 6530 qfmt = "txq%02d"; 6531 else 6532 qfmt = "txq%d"; 6533 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6534 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6535 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6536 CTLFLAG_RD, NULL, "Queue Name"); 6537 queue_list = SYSCTL_CHILDREN(queue_node); 6538 #if MEMORY_LOGGING 6539 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6540 CTLFLAG_RD, 6541 &txq->ift_dequeued, "total mbufs freed"); 6542 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6543 CTLFLAG_RD, 6544 &txq->ift_enqueued, "total mbufs enqueued"); 6545 #endif 6546 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6547 CTLFLAG_RD, 6548 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6549 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6550 CTLFLAG_RD, 6551 &txq->ift_pullups, "# of times m_pullup was called"); 6552 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6553 CTLFLAG_RD, 6554 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6555 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6556 CTLFLAG_RD, 6557 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6558 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6559 CTLFLAG_RD, 6560 &txq->ift_map_failed, "# of times DMA map failed"); 6561 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6562 CTLFLAG_RD, 6563 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6564 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6565 CTLFLAG_RD, 6566 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6567 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6568 CTLFLAG_RD, 6569 &txq->ift_pidx, 1, "Producer Index"); 6570 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6571 CTLFLAG_RD, 6572 &txq->ift_cidx, 1, "Consumer Index"); 6573 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6574 CTLFLAG_RD, 6575 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6576 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6577 CTLFLAG_RD, 6578 &txq->ift_in_use, 1, "descriptors in use"); 6579 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6580 CTLFLAG_RD, 6581 &txq->ift_processed, "descriptors procesed for clean"); 6582 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6583 CTLFLAG_RD, 6584 &txq->ift_cleaned, "total cleaned"); 6585 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6586 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6587 0, mp_ring_state_handler, "A", "soft ring state"); 6588 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6589 CTLFLAG_RD, &txq->ift_br->enqueues, 6590 "# of enqueues to the mp_ring for this queue"); 6591 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6592 CTLFLAG_RD, &txq->ift_br->drops, 6593 "# of drops in the mp_ring for this queue"); 6594 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6595 CTLFLAG_RD, &txq->ift_br->starts, 6596 "# of normal consumer starts in the mp_ring for this queue"); 6597 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6598 CTLFLAG_RD, &txq->ift_br->stalls, 6599 "# of consumer stalls in the mp_ring for this queue"); 6600 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6601 CTLFLAG_RD, &txq->ift_br->restarts, 6602 "# of consumer restarts in the mp_ring for this queue"); 6603 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6604 CTLFLAG_RD, &txq->ift_br->abdications, 6605 "# of consumer abdications in the mp_ring for this queue"); 6606 } 6607 6608 if (scctx->isc_nrxqsets > 100) 6609 qfmt = "rxq%03d"; 6610 else if (scctx->isc_nrxqsets > 10) 6611 qfmt = "rxq%02d"; 6612 else 6613 qfmt = "rxq%d"; 6614 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6615 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6616 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6617 CTLFLAG_RD, NULL, "Queue Name"); 6618 queue_list = SYSCTL_CHILDREN(queue_node); 6619 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6620 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6621 CTLFLAG_RD, 6622 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6623 } 6624 6625 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6626 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6627 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6628 CTLFLAG_RD, NULL, "freelist Name"); 6629 fl_list = SYSCTL_CHILDREN(fl_node); 6630 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6631 CTLFLAG_RD, 6632 &fl->ifl_pidx, 1, "Producer Index"); 6633 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6634 CTLFLAG_RD, 6635 &fl->ifl_cidx, 1, "Consumer Index"); 6636 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6637 CTLFLAG_RD, 6638 &fl->ifl_credits, 1, "credits available"); 6639 #if MEMORY_LOGGING 6640 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6641 CTLFLAG_RD, 6642 &fl->ifl_m_enqueued, "mbufs allocated"); 6643 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6644 CTLFLAG_RD, 6645 &fl->ifl_m_dequeued, "mbufs freed"); 6646 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6647 CTLFLAG_RD, 6648 &fl->ifl_cl_enqueued, "clusters allocated"); 6649 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6650 CTLFLAG_RD, 6651 &fl->ifl_cl_dequeued, "clusters freed"); 6652 #endif 6653 6654 } 6655 } 6656 6657 } 6658 6659 void 6660 iflib_request_reset(if_ctx_t ctx) 6661 { 6662 6663 STATE_LOCK(ctx); 6664 ctx->ifc_flags |= IFC_DO_RESET; 6665 STATE_UNLOCK(ctx); 6666 } 6667 6668 #ifndef __NO_STRICT_ALIGNMENT 6669 static struct mbuf * 6670 iflib_fixup_rx(struct mbuf *m) 6671 { 6672 struct mbuf *n; 6673 6674 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6675 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6676 m->m_data += ETHER_HDR_LEN; 6677 n = m; 6678 } else { 6679 MGETHDR(n, M_NOWAIT, MT_DATA); 6680 if (n == NULL) { 6681 m_freem(m); 6682 return (NULL); 6683 } 6684 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6685 m->m_data += ETHER_HDR_LEN; 6686 m->m_len -= ETHER_HDR_LEN; 6687 n->m_len = ETHER_HDR_LEN; 6688 M_MOVE_PKTHDR(n, m); 6689 n->m_next = m; 6690 } 6691 return (n); 6692 } 6693 #endif 6694 6695 #ifdef NETDUMP 6696 static void 6697 iflib_netdump_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6698 { 6699 if_ctx_t ctx; 6700 6701 ctx = if_getsoftc(ifp); 6702 CTX_LOCK(ctx); 6703 *nrxr = NRXQSETS(ctx); 6704 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6705 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6706 CTX_UNLOCK(ctx); 6707 } 6708 6709 static void 6710 iflib_netdump_event(if_t ifp, enum netdump_ev event) 6711 { 6712 if_ctx_t ctx; 6713 if_softc_ctx_t scctx; 6714 iflib_fl_t fl; 6715 iflib_rxq_t rxq; 6716 int i, j; 6717 6718 ctx = if_getsoftc(ifp); 6719 scctx = &ctx->ifc_softc_ctx; 6720 6721 switch (event) { 6722 case NETDUMP_START: 6723 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6724 rxq = &ctx->ifc_rxqs[i]; 6725 for (j = 0; j < rxq->ifr_nfl; j++) { 6726 fl = rxq->ifr_fl; 6727 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6728 } 6729 } 6730 iflib_no_tx_batch = 1; 6731 break; 6732 default: 6733 break; 6734 } 6735 } 6736 6737 static int 6738 iflib_netdump_transmit(if_t ifp, struct mbuf *m) 6739 { 6740 if_ctx_t ctx; 6741 iflib_txq_t txq; 6742 int error; 6743 6744 ctx = if_getsoftc(ifp); 6745 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6746 IFF_DRV_RUNNING) 6747 return (EBUSY); 6748 6749 txq = &ctx->ifc_txqs[0]; 6750 error = iflib_encap(txq, &m); 6751 if (error == 0) 6752 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6753 return (error); 6754 } 6755 6756 static int 6757 iflib_netdump_poll(if_t ifp, int count) 6758 { 6759 if_ctx_t ctx; 6760 if_softc_ctx_t scctx; 6761 iflib_txq_t txq; 6762 int i; 6763 6764 ctx = if_getsoftc(ifp); 6765 scctx = &ctx->ifc_softc_ctx; 6766 6767 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6768 IFF_DRV_RUNNING) 6769 return (EBUSY); 6770 6771 txq = &ctx->ifc_txqs[0]; 6772 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6773 6774 for (i = 0; i < scctx->isc_nrxqsets; i++) 6775 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6776 return (0); 6777 } 6778 #endif /* NETDUMP */ 6779