1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/jail.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/md5.h> 44 #include <sys/mutex.h> 45 #include <sys/module.h> 46 #include <sys/kobj.h> 47 #include <sys/rman.h> 48 #include <sys/proc.h> 49 #include <sys/sbuf.h> 50 #include <sys/smp.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/syslog.h> 55 #include <sys/taskqueue.h> 56 #include <sys/limits.h> 57 58 #include <net/if.h> 59 #include <net/if_var.h> 60 #include <net/if_types.h> 61 #include <net/if_media.h> 62 #include <net/bpf.h> 63 #include <net/ethernet.h> 64 #include <net/mp_ring.h> 65 #include <net/vnet.h> 66 67 #include <netinet/in.h> 68 #include <netinet/in_pcb.h> 69 #include <netinet/tcp_lro.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/if_ether.h> 72 #include <netinet/ip.h> 73 #include <netinet/ip6.h> 74 #include <netinet/tcp.h> 75 #include <netinet/ip_var.h> 76 #include <netinet/netdump/netdump.h> 77 #include <netinet6/ip6_var.h> 78 79 #include <machine/bus.h> 80 #include <machine/in_cksum.h> 81 82 #include <vm/vm.h> 83 #include <vm/pmap.h> 84 85 #include <dev/led/led.h> 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pci_private.h> 89 90 #include <net/iflib.h> 91 #include <net/iflib_private.h> 92 93 #include "ifdi_if.h" 94 95 #ifdef PCI_IOV 96 #include <dev/pci/pci_iov.h> 97 #endif 98 99 #include <sys/bitstring.h> 100 /* 101 * enable accounting of every mbuf as it comes in to and goes out of 102 * iflib's software descriptor references 103 */ 104 #define MEMORY_LOGGING 0 105 /* 106 * Enable mbuf vectors for compressing long mbuf chains 107 */ 108 109 /* 110 * NB: 111 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 112 * we prefetch needs to be determined by the time spent in m_free vis a vis 113 * the cost of a prefetch. This will of course vary based on the workload: 114 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 115 * is quite expensive, thus suggesting very little prefetch. 116 * - small packet forwarding which is just returning a single mbuf to 117 * UMA will typically be very fast vis a vis the cost of a memory 118 * access. 119 */ 120 121 122 /* 123 * File organization: 124 * - private structures 125 * - iflib private utility functions 126 * - ifnet functions 127 * - vlan registry and other exported functions 128 * - iflib public core functions 129 * 130 * 131 */ 132 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 146 typedef struct iflib_filter_info { 147 driver_filter_t *ifi_filter; 148 void *ifi_filter_arg; 149 struct grouptask *ifi_task; 150 void *ifi_ctx; 151 } *iflib_filter_info_t; 152 153 struct iflib_ctx { 154 KOBJ_FIELDS; 155 /* 156 * Pointer to hardware driver's softc 157 */ 158 void *ifc_softc; 159 device_t ifc_dev; 160 if_t ifc_ifp; 161 162 cpuset_t ifc_cpus; 163 if_shared_ctx_t ifc_sctx; 164 struct if_softc_ctx ifc_softc_ctx; 165 166 struct sx ifc_ctx_sx; 167 struct mtx ifc_state_mtx; 168 169 iflib_txq_t ifc_txqs; 170 iflib_rxq_t ifc_rxqs; 171 uint32_t ifc_if_flags; 172 uint32_t ifc_flags; 173 uint32_t ifc_max_fl_buf_size; 174 175 int ifc_link_state; 176 int ifc_link_irq; 177 int ifc_watchdog_events; 178 struct cdev *ifc_led_dev; 179 struct resource *ifc_msix_mem; 180 181 struct if_irq ifc_legacy_irq; 182 struct grouptask ifc_admin_task; 183 struct grouptask ifc_vflr_task; 184 struct iflib_filter_info ifc_filter_info; 185 struct ifmedia ifc_media; 186 187 struct sysctl_oid *ifc_sysctl_node; 188 uint16_t ifc_sysctl_ntxqs; 189 uint16_t ifc_sysctl_nrxqs; 190 uint16_t ifc_sysctl_qs_eq_override; 191 uint16_t ifc_sysctl_rx_budget; 192 uint16_t ifc_sysctl_tx_abdicate; 193 194 qidx_t ifc_sysctl_ntxds[8]; 195 qidx_t ifc_sysctl_nrxds[8]; 196 struct if_txrx ifc_txrx; 197 #define isc_txd_encap ifc_txrx.ift_txd_encap 198 #define isc_txd_flush ifc_txrx.ift_txd_flush 199 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 200 #define isc_rxd_available ifc_txrx.ift_rxd_available 201 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 202 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 203 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 205 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 206 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 207 eventhandler_tag ifc_vlan_attach_event; 208 eventhandler_tag ifc_vlan_detach_event; 209 uint8_t ifc_mac[ETHER_ADDR_LEN]; 210 char ifc_mtx_name[16]; 211 }; 212 213 214 void * 215 iflib_get_softc(if_ctx_t ctx) 216 { 217 218 return (ctx->ifc_softc); 219 } 220 221 device_t 222 iflib_get_dev(if_ctx_t ctx) 223 { 224 225 return (ctx->ifc_dev); 226 } 227 228 if_t 229 iflib_get_ifp(if_ctx_t ctx) 230 { 231 232 return (ctx->ifc_ifp); 233 } 234 235 struct ifmedia * 236 iflib_get_media(if_ctx_t ctx) 237 { 238 239 return (&ctx->ifc_media); 240 } 241 242 uint32_t 243 iflib_get_flags(if_ctx_t ctx) 244 { 245 return (ctx->ifc_flags); 246 } 247 248 void 249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 250 { 251 252 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 253 } 254 255 if_softc_ctx_t 256 iflib_get_softc_ctx(if_ctx_t ctx) 257 { 258 259 return (&ctx->ifc_softc_ctx); 260 } 261 262 if_shared_ctx_t 263 iflib_get_sctx(if_ctx_t ctx) 264 { 265 266 return (ctx->ifc_sctx); 267 } 268 269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 272 273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 275 276 typedef struct iflib_sw_rx_desc_array { 277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 278 struct mbuf **ifsd_m; /* pkthdr mbufs */ 279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 281 } iflib_rxsd_array_t; 282 283 typedef struct iflib_sw_tx_desc_array { 284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 286 struct mbuf **ifsd_m; /* pkthdr mbufs */ 287 } if_txsd_vec_t; 288 289 290 /* magic number that should be high enough for any hardware */ 291 #define IFLIB_MAX_TX_SEGS 128 292 #define IFLIB_RX_COPY_THRESH 128 293 #define IFLIB_MAX_RX_REFRESH 32 294 /* The minimum descriptors per second before we start coalescing */ 295 #define IFLIB_MIN_DESC_SEC 16384 296 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 297 #define IFLIB_QUEUE_IDLE 0 298 #define IFLIB_QUEUE_HUNG 1 299 #define IFLIB_QUEUE_WORKING 2 300 /* maximum number of txqs that can share an rx interrupt */ 301 #define IFLIB_MAX_TX_SHARED_INTR 4 302 303 /* this should really scale with ring size - this is a fairly arbitrary value */ 304 #define TX_BATCH_SIZE 32 305 306 #define IFLIB_RESTART_BUDGET 8 307 308 309 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 310 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 311 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 312 struct iflib_txq { 313 qidx_t ift_in_use; 314 qidx_t ift_cidx; 315 qidx_t ift_cidx_processed; 316 qidx_t ift_pidx; 317 uint8_t ift_gen; 318 uint8_t ift_br_offset; 319 uint16_t ift_npending; 320 uint16_t ift_db_pending; 321 uint16_t ift_rs_pending; 322 /* implicit pad */ 323 uint8_t ift_txd_size[8]; 324 uint64_t ift_processed; 325 uint64_t ift_cleaned; 326 uint64_t ift_cleaned_prev; 327 #if MEMORY_LOGGING 328 uint64_t ift_enqueued; 329 uint64_t ift_dequeued; 330 #endif 331 uint64_t ift_no_tx_dma_setup; 332 uint64_t ift_no_desc_avail; 333 uint64_t ift_mbuf_defrag_failed; 334 uint64_t ift_mbuf_defrag; 335 uint64_t ift_map_failed; 336 uint64_t ift_txd_encap_efbig; 337 uint64_t ift_pullups; 338 uint64_t ift_last_timer_tick; 339 340 struct mtx ift_mtx; 341 struct mtx ift_db_mtx; 342 343 /* constant values */ 344 if_ctx_t ift_ctx; 345 struct ifmp_ring *ift_br; 346 struct grouptask ift_task; 347 qidx_t ift_size; 348 uint16_t ift_id; 349 struct callout ift_timer; 350 351 if_txsd_vec_t ift_sds; 352 uint8_t ift_qstatus; 353 uint8_t ift_closed; 354 uint8_t ift_update_freq; 355 struct iflib_filter_info ift_filter_info; 356 bus_dma_tag_t ift_buf_tag; 357 bus_dma_tag_t ift_tso_buf_tag; 358 iflib_dma_info_t ift_ifdi; 359 #define MTX_NAME_LEN 16 360 char ift_mtx_name[MTX_NAME_LEN]; 361 char ift_db_mtx_name[MTX_NAME_LEN]; 362 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 363 #ifdef IFLIB_DIAGNOSTICS 364 uint64_t ift_cpu_exec_count[256]; 365 #endif 366 } __aligned(CACHE_LINE_SIZE); 367 368 struct iflib_fl { 369 qidx_t ifl_cidx; 370 qidx_t ifl_pidx; 371 qidx_t ifl_credits; 372 uint8_t ifl_gen; 373 uint8_t ifl_rxd_size; 374 #if MEMORY_LOGGING 375 uint64_t ifl_m_enqueued; 376 uint64_t ifl_m_dequeued; 377 uint64_t ifl_cl_enqueued; 378 uint64_t ifl_cl_dequeued; 379 #endif 380 /* implicit pad */ 381 382 bitstr_t *ifl_rx_bitmap; 383 qidx_t ifl_fragidx; 384 /* constant */ 385 qidx_t ifl_size; 386 uint16_t ifl_buf_size; 387 uint16_t ifl_cltype; 388 uma_zone_t ifl_zone; 389 iflib_rxsd_array_t ifl_sds; 390 iflib_rxq_t ifl_rxq; 391 uint8_t ifl_id; 392 bus_dma_tag_t ifl_buf_tag; 393 iflib_dma_info_t ifl_ifdi; 394 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 395 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 396 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 397 } __aligned(CACHE_LINE_SIZE); 398 399 static inline qidx_t 400 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 401 { 402 qidx_t used; 403 404 if (pidx > cidx) 405 used = pidx - cidx; 406 else if (pidx < cidx) 407 used = size - cidx + pidx; 408 else if (gen == 0 && pidx == cidx) 409 used = 0; 410 else if (gen == 1 && pidx == cidx) 411 used = size; 412 else 413 panic("bad state"); 414 415 return (used); 416 } 417 418 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 419 420 #define IDXDIFF(head, tail, wrap) \ 421 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 422 423 struct iflib_rxq { 424 /* If there is a separate completion queue - 425 * these are the cq cidx and pidx. Otherwise 426 * these are unused. 427 */ 428 qidx_t ifr_size; 429 qidx_t ifr_cq_cidx; 430 qidx_t ifr_cq_pidx; 431 uint8_t ifr_cq_gen; 432 uint8_t ifr_fl_offset; 433 434 if_ctx_t ifr_ctx; 435 iflib_fl_t ifr_fl; 436 uint64_t ifr_rx_irq; 437 uint16_t ifr_id; 438 uint8_t ifr_lro_enabled; 439 uint8_t ifr_nfl; 440 uint8_t ifr_ntxqirq; 441 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 442 struct lro_ctrl ifr_lc; 443 struct grouptask ifr_task; 444 struct iflib_filter_info ifr_filter_info; 445 iflib_dma_info_t ifr_ifdi; 446 447 /* dynamically allocate if any drivers need a value substantially larger than this */ 448 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 449 #ifdef IFLIB_DIAGNOSTICS 450 uint64_t ifr_cpu_exec_count[256]; 451 #endif 452 } __aligned(CACHE_LINE_SIZE); 453 454 typedef struct if_rxsd { 455 caddr_t *ifsd_cl; 456 struct mbuf **ifsd_m; 457 iflib_fl_t ifsd_fl; 458 qidx_t ifsd_cidx; 459 } *if_rxsd_t; 460 461 /* multiple of word size */ 462 #ifdef __LP64__ 463 #define PKT_INFO_SIZE 6 464 #define RXD_INFO_SIZE 5 465 #define PKT_TYPE uint64_t 466 #else 467 #define PKT_INFO_SIZE 11 468 #define RXD_INFO_SIZE 8 469 #define PKT_TYPE uint32_t 470 #endif 471 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 472 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 473 474 typedef struct if_pkt_info_pad { 475 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 476 } *if_pkt_info_pad_t; 477 typedef struct if_rxd_info_pad { 478 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 479 } *if_rxd_info_pad_t; 480 481 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 482 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 483 484 485 static inline void 486 pkt_info_zero(if_pkt_info_t pi) 487 { 488 if_pkt_info_pad_t pi_pad; 489 490 pi_pad = (if_pkt_info_pad_t)pi; 491 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 492 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 493 #ifndef __LP64__ 494 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 495 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 496 #endif 497 } 498 499 static device_method_t iflib_pseudo_methods[] = { 500 DEVMETHOD(device_attach, noop_attach), 501 DEVMETHOD(device_detach, iflib_pseudo_detach), 502 DEVMETHOD_END 503 }; 504 505 driver_t iflib_pseudodriver = { 506 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 507 }; 508 509 static inline void 510 rxd_info_zero(if_rxd_info_t ri) 511 { 512 if_rxd_info_pad_t ri_pad; 513 int i; 514 515 ri_pad = (if_rxd_info_pad_t)ri; 516 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 517 ri_pad->rxd_val[i] = 0; 518 ri_pad->rxd_val[i+1] = 0; 519 ri_pad->rxd_val[i+2] = 0; 520 ri_pad->rxd_val[i+3] = 0; 521 } 522 #ifdef __LP64__ 523 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 524 #endif 525 } 526 527 /* 528 * Only allow a single packet to take up most 1/nth of the tx ring 529 */ 530 #define MAX_SINGLE_PACKET_FRACTION 12 531 #define IF_BAD_DMA (bus_addr_t)-1 532 533 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 534 535 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 536 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 537 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 538 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 539 540 541 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 542 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 543 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 544 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 545 546 547 548 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 549 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 550 551 void 552 iflib_set_detach(if_ctx_t ctx) 553 { 554 STATE_LOCK(ctx); 555 ctx->ifc_flags |= IFC_IN_DETACH; 556 STATE_UNLOCK(ctx); 557 } 558 559 /* Our boot-time initialization hook */ 560 static int iflib_module_event_handler(module_t, int, void *); 561 562 static moduledata_t iflib_moduledata = { 563 "iflib", 564 iflib_module_event_handler, 565 NULL 566 }; 567 568 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 569 MODULE_VERSION(iflib, 1); 570 571 MODULE_DEPEND(iflib, pci, 1, 1, 1); 572 MODULE_DEPEND(iflib, ether, 1, 1, 1); 573 574 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 575 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 576 577 #ifndef IFLIB_DEBUG_COUNTERS 578 #ifdef INVARIANTS 579 #define IFLIB_DEBUG_COUNTERS 1 580 #else 581 #define IFLIB_DEBUG_COUNTERS 0 582 #endif /* !INVARIANTS */ 583 #endif 584 585 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 586 "iflib driver parameters"); 587 588 /* 589 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 590 */ 591 static int iflib_min_tx_latency = 0; 592 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 593 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 594 static int iflib_no_tx_batch = 0; 595 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 596 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 597 598 599 #if IFLIB_DEBUG_COUNTERS 600 601 static int iflib_tx_seen; 602 static int iflib_tx_sent; 603 static int iflib_tx_encap; 604 static int iflib_rx_allocs; 605 static int iflib_fl_refills; 606 static int iflib_fl_refills_large; 607 static int iflib_tx_frees; 608 609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 610 &iflib_tx_seen, 0, "# tx mbufs seen"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 612 &iflib_tx_sent, 0, "# tx mbufs sent"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 614 &iflib_tx_encap, 0, "# tx mbufs encapped"); 615 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 616 &iflib_tx_frees, 0, "# tx frees"); 617 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 618 &iflib_rx_allocs, 0, "# rx allocations"); 619 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 620 &iflib_fl_refills, 0, "# refills"); 621 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 622 &iflib_fl_refills_large, 0, "# large refills"); 623 624 625 static int iflib_txq_drain_flushing; 626 static int iflib_txq_drain_oactive; 627 static int iflib_txq_drain_notready; 628 629 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 630 &iflib_txq_drain_flushing, 0, "# drain flushes"); 631 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 632 &iflib_txq_drain_oactive, 0, "# drain oactives"); 633 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 634 &iflib_txq_drain_notready, 0, "# drain notready"); 635 636 637 static int iflib_encap_load_mbuf_fail; 638 static int iflib_encap_pad_mbuf_fail; 639 static int iflib_encap_txq_avail_fail; 640 static int iflib_encap_txd_encap_fail; 641 642 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 643 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 644 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 645 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 646 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 647 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 648 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 649 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 650 651 static int iflib_task_fn_rxs; 652 static int iflib_rx_intr_enables; 653 static int iflib_fast_intrs; 654 static int iflib_rx_unavail; 655 static int iflib_rx_ctx_inactive; 656 static int iflib_rx_if_input; 657 static int iflib_rx_mbuf_null; 658 static int iflib_rxd_flush; 659 660 static int iflib_verbose_debug; 661 662 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 663 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 665 &iflib_rx_intr_enables, 0, "# rx intr enables"); 666 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 667 &iflib_fast_intrs, 0, "# fast_intr calls"); 668 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 669 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 670 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 671 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 672 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 673 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 674 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 675 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 676 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 677 &iflib_rxd_flush, 0, "# times rxd_flush called"); 678 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 679 &iflib_verbose_debug, 0, "enable verbose debugging"); 680 681 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 682 static void 683 iflib_debug_reset(void) 684 { 685 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 686 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 687 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 688 iflib_txq_drain_notready = 689 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 690 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 691 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 692 iflib_rx_unavail = 693 iflib_rx_ctx_inactive = iflib_rx_if_input = 694 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 695 } 696 697 #else 698 #define DBG_COUNTER_INC(name) 699 static void iflib_debug_reset(void) {} 700 #endif 701 702 #define IFLIB_DEBUG 0 703 704 static void iflib_tx_structures_free(if_ctx_t ctx); 705 static void iflib_rx_structures_free(if_ctx_t ctx); 706 static int iflib_queues_alloc(if_ctx_t ctx); 707 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 708 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 709 static int iflib_qset_structures_setup(if_ctx_t ctx); 710 static int iflib_msix_init(if_ctx_t ctx); 711 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 712 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 713 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 714 #ifdef ALTQ 715 static void iflib_altq_if_start(if_t ifp); 716 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 717 #endif 718 static int iflib_register(if_ctx_t); 719 static void iflib_init_locked(if_ctx_t ctx); 720 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 721 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 722 static void iflib_ifmp_purge(iflib_txq_t txq); 723 static void _iflib_pre_assert(if_softc_ctx_t scctx); 724 static void iflib_if_init_locked(if_ctx_t ctx); 725 static void iflib_free_intr_mem(if_ctx_t ctx); 726 #ifndef __NO_STRICT_ALIGNMENT 727 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 728 #endif 729 730 NETDUMP_DEFINE(iflib); 731 732 #ifdef DEV_NETMAP 733 #include <sys/selinfo.h> 734 #include <net/netmap.h> 735 #include <dev/netmap/netmap_kern.h> 736 737 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 738 739 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 740 741 /* 742 * device-specific sysctl variables: 743 * 744 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 745 * During regular operations the CRC is stripped, but on some 746 * hardware reception of frames not multiple of 64 is slower, 747 * so using crcstrip=0 helps in benchmarks. 748 * 749 * iflib_rx_miss, iflib_rx_miss_bufs: 750 * count packets that might be missed due to lost interrupts. 751 */ 752 SYSCTL_DECL(_dev_netmap); 753 /* 754 * The xl driver by default strips CRCs and we do not override it. 755 */ 756 757 int iflib_crcstrip = 1; 758 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 759 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 760 761 int iflib_rx_miss, iflib_rx_miss_bufs; 762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 763 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 764 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 765 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 766 767 /* 768 * Register/unregister. We are already under netmap lock. 769 * Only called on the first register or the last unregister. 770 */ 771 static int 772 iflib_netmap_register(struct netmap_adapter *na, int onoff) 773 { 774 struct ifnet *ifp = na->ifp; 775 if_ctx_t ctx = ifp->if_softc; 776 int status; 777 778 CTX_LOCK(ctx); 779 IFDI_INTR_DISABLE(ctx); 780 781 /* Tell the stack that the interface is no longer active */ 782 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 783 784 if (!CTX_IS_VF(ctx)) 785 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 786 787 /* enable or disable flags and callbacks in na and ifp */ 788 if (onoff) { 789 nm_set_native_flags(na); 790 } else { 791 nm_clear_native_flags(na); 792 } 793 iflib_stop(ctx); 794 iflib_init_locked(ctx); 795 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 796 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 797 if (status) 798 nm_clear_native_flags(na); 799 CTX_UNLOCK(ctx); 800 return (status); 801 } 802 803 static int 804 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 805 { 806 struct netmap_adapter *na = kring->na; 807 u_int const lim = kring->nkr_num_slots - 1; 808 u_int head = kring->rhead; 809 struct netmap_ring *ring = kring->ring; 810 bus_dmamap_t *map; 811 struct if_rxd_update iru; 812 if_ctx_t ctx = rxq->ifr_ctx; 813 iflib_fl_t fl = &rxq->ifr_fl[0]; 814 uint32_t refill_pidx, nic_i; 815 #if IFLIB_DEBUG_COUNTERS 816 int rf_count = 0; 817 #endif 818 819 if (nm_i == head && __predict_true(!init)) 820 return 0; 821 iru_init(&iru, rxq, 0 /* flid */); 822 map = fl->ifl_sds.ifsd_map; 823 refill_pidx = netmap_idx_k2n(kring, nm_i); 824 /* 825 * IMPORTANT: we must leave one free slot in the ring, 826 * so move head back by one unit 827 */ 828 head = nm_prev(head, lim); 829 nic_i = UINT_MAX; 830 DBG_COUNTER_INC(fl_refills); 831 while (nm_i != head) { 832 #if IFLIB_DEBUG_COUNTERS 833 if (++rf_count == 9) 834 DBG_COUNTER_INC(fl_refills_large); 835 #endif 836 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 837 struct netmap_slot *slot = &ring->slot[nm_i]; 838 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 839 uint32_t nic_i_dma = refill_pidx; 840 nic_i = netmap_idx_k2n(kring, nm_i); 841 842 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 843 844 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 845 return netmap_ring_reinit(kring); 846 847 fl->ifl_vm_addrs[tmp_pidx] = addr; 848 if (__predict_false(init)) { 849 netmap_load_map(na, fl->ifl_buf_tag, 850 map[nic_i], addr); 851 } else if (slot->flags & NS_BUF_CHANGED) { 852 /* buffer has changed, reload map */ 853 netmap_reload_map(na, fl->ifl_buf_tag, 854 map[nic_i], addr); 855 } 856 slot->flags &= ~NS_BUF_CHANGED; 857 858 nm_i = nm_next(nm_i, lim); 859 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 860 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 861 continue; 862 863 iru.iru_pidx = refill_pidx; 864 iru.iru_count = tmp_pidx+1; 865 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 866 refill_pidx = nic_i; 867 for (int n = 0; n < iru.iru_count; n++) { 868 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma], 869 BUS_DMASYNC_PREREAD); 870 /* XXX - change this to not use the netmap func*/ 871 nic_i_dma = nm_next(nic_i_dma, lim); 872 } 873 } 874 } 875 kring->nr_hwcur = head; 876 877 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 878 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 879 if (__predict_true(nic_i != UINT_MAX)) { 880 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 881 DBG_COUNTER_INC(rxd_flush); 882 } 883 return (0); 884 } 885 886 /* 887 * Reconcile kernel and user view of the transmit ring. 888 * 889 * All information is in the kring. 890 * Userspace wants to send packets up to the one before kring->rhead, 891 * kernel knows kring->nr_hwcur is the first unsent packet. 892 * 893 * Here we push packets out (as many as possible), and possibly 894 * reclaim buffers from previously completed transmission. 895 * 896 * The caller (netmap) guarantees that there is only one instance 897 * running at any time. Any interference with other driver 898 * methods should be handled by the individual drivers. 899 */ 900 static int 901 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 902 { 903 struct netmap_adapter *na = kring->na; 904 struct ifnet *ifp = na->ifp; 905 struct netmap_ring *ring = kring->ring; 906 u_int nm_i; /* index into the netmap kring */ 907 u_int nic_i; /* index into the NIC ring */ 908 u_int n; 909 u_int const lim = kring->nkr_num_slots - 1; 910 u_int const head = kring->rhead; 911 struct if_pkt_info pi; 912 913 /* 914 * interrupts on every tx packet are expensive so request 915 * them every half ring, or where NS_REPORT is set 916 */ 917 u_int report_frequency = kring->nkr_num_slots >> 1; 918 /* device-specific */ 919 if_ctx_t ctx = ifp->if_softc; 920 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 921 922 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 923 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 924 925 /* 926 * First part: process new packets to send. 927 * nm_i is the current index in the netmap kring, 928 * nic_i is the corresponding index in the NIC ring. 929 * 930 * If we have packets to send (nm_i != head) 931 * iterate over the netmap ring, fetch length and update 932 * the corresponding slot in the NIC ring. Some drivers also 933 * need to update the buffer's physical address in the NIC slot 934 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 935 * 936 * The netmap_reload_map() calls is especially expensive, 937 * even when (as in this case) the tag is 0, so do only 938 * when the buffer has actually changed. 939 * 940 * If possible do not set the report/intr bit on all slots, 941 * but only a few times per ring or when NS_REPORT is set. 942 * 943 * Finally, on 10G and faster drivers, it might be useful 944 * to prefetch the next slot and txr entry. 945 */ 946 947 nm_i = kring->nr_hwcur; 948 if (nm_i != head) { /* we have new packets to send */ 949 pkt_info_zero(&pi); 950 pi.ipi_segs = txq->ift_segs; 951 pi.ipi_qsidx = kring->ring_id; 952 nic_i = netmap_idx_k2n(kring, nm_i); 953 954 __builtin_prefetch(&ring->slot[nm_i]); 955 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 956 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 957 958 for (n = 0; nm_i != head; n++) { 959 struct netmap_slot *slot = &ring->slot[nm_i]; 960 u_int len = slot->len; 961 uint64_t paddr; 962 void *addr = PNMB(na, slot, &paddr); 963 int flags = (slot->flags & NS_REPORT || 964 nic_i == 0 || nic_i == report_frequency) ? 965 IPI_TX_INTR : 0; 966 967 /* device-specific */ 968 pi.ipi_len = len; 969 pi.ipi_segs[0].ds_addr = paddr; 970 pi.ipi_segs[0].ds_len = len; 971 pi.ipi_nsegs = 1; 972 pi.ipi_ndescs = 0; 973 pi.ipi_pidx = nic_i; 974 pi.ipi_flags = flags; 975 976 /* Fill the slot in the NIC ring. */ 977 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 978 DBG_COUNTER_INC(tx_encap); 979 980 /* prefetch for next round */ 981 __builtin_prefetch(&ring->slot[nm_i + 1]); 982 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 983 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 984 985 NM_CHECK_ADDR_LEN(na, addr, len); 986 987 if (slot->flags & NS_BUF_CHANGED) { 988 /* buffer has changed, reload map */ 989 netmap_reload_map(na, txq->ift_buf_tag, 990 txq->ift_sds.ifsd_map[nic_i], addr); 991 } 992 /* make sure changes to the buffer are synced */ 993 bus_dmamap_sync(txq->ift_buf_tag, 994 txq->ift_sds.ifsd_map[nic_i], 995 BUS_DMASYNC_PREWRITE); 996 997 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 998 nm_i = nm_next(nm_i, lim); 999 nic_i = nm_next(nic_i, lim); 1000 } 1001 kring->nr_hwcur = nm_i; 1002 1003 /* synchronize the NIC ring */ 1004 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1005 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1006 1007 /* (re)start the tx unit up to slot nic_i (excluded) */ 1008 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1009 } 1010 1011 /* 1012 * Second part: reclaim buffers for completed transmissions. 1013 * 1014 * If there are unclaimed buffers, attempt to reclaim them. 1015 * If none are reclaimed, and TX IRQs are not in use, do an initial 1016 * minimal delay, then trigger the tx handler which will spin in the 1017 * group task queue. 1018 */ 1019 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1020 if (iflib_tx_credits_update(ctx, txq)) { 1021 /* some tx completed, increment avail */ 1022 nic_i = txq->ift_cidx_processed; 1023 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1024 } 1025 } 1026 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1027 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1028 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1029 iflib_timer, txq, txq->ift_timer.c_cpu); 1030 } 1031 return (0); 1032 } 1033 1034 /* 1035 * Reconcile kernel and user view of the receive ring. 1036 * Same as for the txsync, this routine must be efficient. 1037 * The caller guarantees a single invocations, but races against 1038 * the rest of the driver should be handled here. 1039 * 1040 * On call, kring->rhead is the first packet that userspace wants 1041 * to keep, and kring->rcur is the wakeup point. 1042 * The kernel has previously reported packets up to kring->rtail. 1043 * 1044 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1045 * of whether or not we received an interrupt. 1046 */ 1047 static int 1048 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1049 { 1050 struct netmap_adapter *na = kring->na; 1051 struct netmap_ring *ring = kring->ring; 1052 iflib_fl_t fl; 1053 uint32_t nm_i; /* index into the netmap ring */ 1054 uint32_t nic_i; /* index into the NIC ring */ 1055 u_int i, n; 1056 u_int const lim = kring->nkr_num_slots - 1; 1057 u_int const head = kring->rhead; 1058 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1059 struct if_rxd_info ri; 1060 1061 struct ifnet *ifp = na->ifp; 1062 if_ctx_t ctx = ifp->if_softc; 1063 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1064 if (head > lim) 1065 return netmap_ring_reinit(kring); 1066 1067 /* 1068 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far. 1069 */ 1070 1071 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1072 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1073 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1074 } 1075 1076 /* 1077 * First part: import newly received packets. 1078 * 1079 * nm_i is the index of the next free slot in the netmap ring, 1080 * nic_i is the index of the next received packet in the NIC ring, 1081 * and they may differ in case if_init() has been called while 1082 * in netmap mode. For the receive ring we have 1083 * 1084 * nic_i = rxr->next_check; 1085 * nm_i = kring->nr_hwtail (previous) 1086 * and 1087 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1088 * 1089 * rxr->next_check is set to 0 on a ring reinit 1090 */ 1091 if (netmap_no_pendintr || force_update) { 1092 int crclen = iflib_crcstrip ? 0 : 4; 1093 int error, avail; 1094 1095 for (i = 0; i < rxq->ifr_nfl; i++) { 1096 fl = &rxq->ifr_fl[i]; 1097 nic_i = fl->ifl_cidx; 1098 nm_i = netmap_idx_n2k(kring, nic_i); 1099 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1100 rxq->ifr_id, nic_i, USHRT_MAX); 1101 for (n = 0; avail > 0; n++, avail--) { 1102 rxd_info_zero(&ri); 1103 ri.iri_frags = rxq->ifr_frags; 1104 ri.iri_qsidx = kring->ring_id; 1105 ri.iri_ifp = ctx->ifc_ifp; 1106 ri.iri_cidx = nic_i; 1107 1108 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1109 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1110 ring->slot[nm_i].flags = 0; 1111 bus_dmamap_sync(fl->ifl_buf_tag, 1112 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1113 nm_i = nm_next(nm_i, lim); 1114 nic_i = nm_next(nic_i, lim); 1115 } 1116 if (n) { /* update the state variables */ 1117 if (netmap_no_pendintr && !force_update) { 1118 /* diagnostics */ 1119 iflib_rx_miss ++; 1120 iflib_rx_miss_bufs += n; 1121 } 1122 fl->ifl_cidx = nic_i; 1123 kring->nr_hwtail = nm_i; 1124 } 1125 kring->nr_kflags &= ~NKR_PENDINTR; 1126 } 1127 } 1128 /* 1129 * Second part: skip past packets that userspace has released. 1130 * (kring->nr_hwcur to head excluded), 1131 * and make the buffers available for reception. 1132 * As usual nm_i is the index in the netmap ring, 1133 * nic_i is the index in the NIC ring, and 1134 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1135 */ 1136 /* XXX not sure how this will work with multiple free lists */ 1137 nm_i = kring->nr_hwcur; 1138 1139 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1140 } 1141 1142 static void 1143 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1144 { 1145 struct ifnet *ifp = na->ifp; 1146 if_ctx_t ctx = ifp->if_softc; 1147 1148 CTX_LOCK(ctx); 1149 if (onoff) { 1150 IFDI_INTR_ENABLE(ctx); 1151 } else { 1152 IFDI_INTR_DISABLE(ctx); 1153 } 1154 CTX_UNLOCK(ctx); 1155 } 1156 1157 1158 static int 1159 iflib_netmap_attach(if_ctx_t ctx) 1160 { 1161 struct netmap_adapter na; 1162 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1163 1164 bzero(&na, sizeof(na)); 1165 1166 na.ifp = ctx->ifc_ifp; 1167 na.na_flags = NAF_BDG_MAYSLEEP; 1168 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1169 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1170 1171 na.num_tx_desc = scctx->isc_ntxd[0]; 1172 na.num_rx_desc = scctx->isc_nrxd[0]; 1173 na.nm_txsync = iflib_netmap_txsync; 1174 na.nm_rxsync = iflib_netmap_rxsync; 1175 na.nm_register = iflib_netmap_register; 1176 na.nm_intr = iflib_netmap_intr; 1177 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1178 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1179 return (netmap_attach(&na)); 1180 } 1181 1182 static void 1183 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1184 { 1185 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1186 struct netmap_slot *slot; 1187 1188 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1189 if (slot == NULL) 1190 return; 1191 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1192 1193 /* 1194 * In netmap mode, set the map for the packet buffer. 1195 * NOTE: Some drivers (not this one) also need to set 1196 * the physical buffer address in the NIC ring. 1197 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1198 * netmap slot index, si 1199 */ 1200 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1201 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1202 NMB(na, slot + si)); 1203 } 1204 } 1205 1206 static void 1207 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1208 { 1209 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1210 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1211 struct netmap_slot *slot; 1212 uint32_t nm_i; 1213 1214 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1215 if (slot == NULL) 1216 return; 1217 nm_i = netmap_idx_n2k(kring, 0); 1218 netmap_fl_refill(rxq, kring, nm_i, true); 1219 } 1220 1221 static void 1222 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on) 1223 { 1224 struct netmap_kring *kring; 1225 uint16_t txqid; 1226 1227 txqid = txq->ift_id; 1228 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1229 1230 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1231 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1232 BUS_DMASYNC_POSTREAD); 1233 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1234 netmap_tx_irq(ctx->ifc_ifp, txqid); 1235 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1236 if (hz < 2000) 1237 *reset_on = 1; 1238 else 1239 *reset_on = hz / 1000; 1240 } 1241 } 1242 } 1243 1244 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1245 1246 #else 1247 #define iflib_netmap_txq_init(ctx, txq) 1248 #define iflib_netmap_rxq_init(ctx, rxq) 1249 #define iflib_netmap_detach(ifp) 1250 1251 #define iflib_netmap_attach(ctx) (0) 1252 #define netmap_rx_irq(ifp, qid, budget) (0) 1253 #define netmap_tx_irq(ifp, qid) do {} while (0) 1254 #define iflib_netmap_timer_adjust(ctx, txq, reset_on) 1255 1256 #endif 1257 1258 #if defined(__i386__) || defined(__amd64__) 1259 static __inline void 1260 prefetch(void *x) 1261 { 1262 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1263 } 1264 static __inline void 1265 prefetch2cachelines(void *x) 1266 { 1267 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1268 #if (CACHE_LINE_SIZE < 128) 1269 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1270 #endif 1271 } 1272 #else 1273 #define prefetch(x) 1274 #define prefetch2cachelines(x) 1275 #endif 1276 1277 static void 1278 iflib_gen_mac(if_ctx_t ctx) 1279 { 1280 struct thread *td; 1281 MD5_CTX mdctx; 1282 char uuid[HOSTUUIDLEN+1]; 1283 char buf[HOSTUUIDLEN+16]; 1284 uint8_t *mac; 1285 unsigned char digest[16]; 1286 1287 td = curthread; 1288 mac = ctx->ifc_mac; 1289 uuid[HOSTUUIDLEN] = 0; 1290 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN); 1291 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev)); 1292 /* 1293 * Generate a pseudo-random, deterministic MAC 1294 * address based on the UUID and unit number. 1295 * The FreeBSD Foundation OUI of 58-9C-FC is used. 1296 */ 1297 MD5Init(&mdctx); 1298 MD5Update(&mdctx, buf, strlen(buf)); 1299 MD5Final(digest, &mdctx); 1300 1301 mac[0] = 0x58; 1302 mac[1] = 0x9C; 1303 mac[2] = 0xFC; 1304 mac[3] = digest[0]; 1305 mac[4] = digest[1]; 1306 mac[5] = digest[2]; 1307 } 1308 1309 static void 1310 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1311 { 1312 iflib_fl_t fl; 1313 1314 fl = &rxq->ifr_fl[flid]; 1315 iru->iru_paddrs = fl->ifl_bus_addrs; 1316 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1317 iru->iru_idxs = fl->ifl_rxd_idxs; 1318 iru->iru_qsidx = rxq->ifr_id; 1319 iru->iru_buf_size = fl->ifl_buf_size; 1320 iru->iru_flidx = fl->ifl_id; 1321 } 1322 1323 static void 1324 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1325 { 1326 if (err) 1327 return; 1328 *(bus_addr_t *) arg = segs[0].ds_addr; 1329 } 1330 1331 int 1332 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1333 { 1334 int err; 1335 device_t dev = ctx->ifc_dev; 1336 1337 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1338 align, 0, /* alignment, bounds */ 1339 BUS_SPACE_MAXADDR, /* lowaddr */ 1340 BUS_SPACE_MAXADDR, /* highaddr */ 1341 NULL, NULL, /* filter, filterarg */ 1342 size, /* maxsize */ 1343 1, /* nsegments */ 1344 size, /* maxsegsize */ 1345 BUS_DMA_ALLOCNOW, /* flags */ 1346 NULL, /* lockfunc */ 1347 NULL, /* lockarg */ 1348 &dma->idi_tag); 1349 if (err) { 1350 device_printf(dev, 1351 "%s: bus_dma_tag_create failed: %d\n", 1352 __func__, err); 1353 goto fail_0; 1354 } 1355 1356 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1357 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1358 if (err) { 1359 device_printf(dev, 1360 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1361 __func__, (uintmax_t)size, err); 1362 goto fail_1; 1363 } 1364 1365 dma->idi_paddr = IF_BAD_DMA; 1366 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1367 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1368 if (err || dma->idi_paddr == IF_BAD_DMA) { 1369 device_printf(dev, 1370 "%s: bus_dmamap_load failed: %d\n", 1371 __func__, err); 1372 goto fail_2; 1373 } 1374 1375 dma->idi_size = size; 1376 return (0); 1377 1378 fail_2: 1379 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1380 fail_1: 1381 bus_dma_tag_destroy(dma->idi_tag); 1382 fail_0: 1383 dma->idi_tag = NULL; 1384 1385 return (err); 1386 } 1387 1388 int 1389 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1390 { 1391 if_shared_ctx_t sctx = ctx->ifc_sctx; 1392 1393 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1394 1395 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1396 } 1397 1398 int 1399 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1400 { 1401 int i, err; 1402 iflib_dma_info_t *dmaiter; 1403 1404 dmaiter = dmalist; 1405 for (i = 0; i < count; i++, dmaiter++) { 1406 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1407 break; 1408 } 1409 if (err) 1410 iflib_dma_free_multi(dmalist, i); 1411 return (err); 1412 } 1413 1414 void 1415 iflib_dma_free(iflib_dma_info_t dma) 1416 { 1417 if (dma->idi_tag == NULL) 1418 return; 1419 if (dma->idi_paddr != IF_BAD_DMA) { 1420 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1421 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1422 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1423 dma->idi_paddr = IF_BAD_DMA; 1424 } 1425 if (dma->idi_vaddr != NULL) { 1426 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1427 dma->idi_vaddr = NULL; 1428 } 1429 bus_dma_tag_destroy(dma->idi_tag); 1430 dma->idi_tag = NULL; 1431 } 1432 1433 void 1434 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1435 { 1436 int i; 1437 iflib_dma_info_t *dmaiter = dmalist; 1438 1439 for (i = 0; i < count; i++, dmaiter++) 1440 iflib_dma_free(*dmaiter); 1441 } 1442 1443 #ifdef EARLY_AP_STARTUP 1444 static const int iflib_started = 1; 1445 #else 1446 /* 1447 * We used to abuse the smp_started flag to decide if the queues have been 1448 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1449 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1450 * is set. Run a SYSINIT() strictly after that to just set a usable 1451 * completion flag. 1452 */ 1453 1454 static int iflib_started; 1455 1456 static void 1457 iflib_record_started(void *arg) 1458 { 1459 iflib_started = 1; 1460 } 1461 1462 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1463 iflib_record_started, NULL); 1464 #endif 1465 1466 static int 1467 iflib_fast_intr(void *arg) 1468 { 1469 iflib_filter_info_t info = arg; 1470 struct grouptask *gtask = info->ifi_task; 1471 if (!iflib_started) 1472 return (FILTER_HANDLED); 1473 1474 DBG_COUNTER_INC(fast_intrs); 1475 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1476 return (FILTER_HANDLED); 1477 1478 GROUPTASK_ENQUEUE(gtask); 1479 return (FILTER_HANDLED); 1480 } 1481 1482 static int 1483 iflib_fast_intr_rxtx(void *arg) 1484 { 1485 iflib_filter_info_t info = arg; 1486 struct grouptask *gtask = info->ifi_task; 1487 if_ctx_t ctx; 1488 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1489 iflib_txq_t txq; 1490 void *sc; 1491 int i, cidx; 1492 qidx_t txqid; 1493 1494 if (!iflib_started) 1495 return (FILTER_HANDLED); 1496 1497 DBG_COUNTER_INC(fast_intrs); 1498 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1499 return (FILTER_HANDLED); 1500 1501 ctx = rxq->ifr_ctx; 1502 sc = ctx->ifc_softc; 1503 MPASS(rxq->ifr_ntxqirq); 1504 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1505 txqid = rxq->ifr_txqid[i]; 1506 txq = &ctx->ifc_txqs[txqid]; 1507 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1508 BUS_DMASYNC_POSTREAD); 1509 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1510 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1511 continue; 1512 } 1513 GROUPTASK_ENQUEUE(&txq->ift_task); 1514 } 1515 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1516 cidx = rxq->ifr_cq_cidx; 1517 else 1518 cidx = rxq->ifr_fl[0].ifl_cidx; 1519 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1520 GROUPTASK_ENQUEUE(gtask); 1521 else { 1522 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1523 DBG_COUNTER_INC(rx_intr_enables); 1524 } 1525 return (FILTER_HANDLED); 1526 } 1527 1528 1529 static int 1530 iflib_fast_intr_ctx(void *arg) 1531 { 1532 iflib_filter_info_t info = arg; 1533 struct grouptask *gtask = info->ifi_task; 1534 1535 if (!iflib_started) 1536 return (FILTER_HANDLED); 1537 1538 DBG_COUNTER_INC(fast_intrs); 1539 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1540 return (FILTER_HANDLED); 1541 1542 GROUPTASK_ENQUEUE(gtask); 1543 return (FILTER_HANDLED); 1544 } 1545 1546 static int 1547 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1548 driver_filter_t filter, driver_intr_t handler, void *arg, 1549 const char *name) 1550 { 1551 int rc, flags; 1552 struct resource *res; 1553 void *tag = NULL; 1554 device_t dev = ctx->ifc_dev; 1555 1556 flags = RF_ACTIVE; 1557 if (ctx->ifc_flags & IFC_LEGACY) 1558 flags |= RF_SHAREABLE; 1559 MPASS(rid < 512); 1560 irq->ii_rid = rid; 1561 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1562 if (res == NULL) { 1563 device_printf(dev, 1564 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1565 return (ENOMEM); 1566 } 1567 irq->ii_res = res; 1568 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1569 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1570 filter, handler, arg, &tag); 1571 if (rc != 0) { 1572 device_printf(dev, 1573 "failed to setup interrupt for rid %d, name %s: %d\n", 1574 rid, name ? name : "unknown", rc); 1575 return (rc); 1576 } else if (name) 1577 bus_describe_intr(dev, res, tag, "%s", name); 1578 1579 irq->ii_tag = tag; 1580 return (0); 1581 } 1582 1583 1584 /********************************************************************* 1585 * 1586 * Allocate DMA resources for TX buffers as well as memory for the TX 1587 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1588 * iflib_sw_tx_desc_array structure, storing all the information that 1589 * is needed to transmit a packet on the wire. This is called only 1590 * once at attach, setup is done every reset. 1591 * 1592 **********************************************************************/ 1593 static int 1594 iflib_txsd_alloc(iflib_txq_t txq) 1595 { 1596 if_ctx_t ctx = txq->ift_ctx; 1597 if_shared_ctx_t sctx = ctx->ifc_sctx; 1598 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1599 device_t dev = ctx->ifc_dev; 1600 bus_size_t tsomaxsize; 1601 int err, nsegments, ntsosegments; 1602 bool tso; 1603 1604 nsegments = scctx->isc_tx_nsegments; 1605 ntsosegments = scctx->isc_tx_tso_segments_max; 1606 tsomaxsize = scctx->isc_tx_tso_size_max; 1607 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1608 tsomaxsize += sizeof(struct ether_vlan_header); 1609 MPASS(scctx->isc_ntxd[0] > 0); 1610 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1611 MPASS(nsegments > 0); 1612 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1613 MPASS(ntsosegments > 0); 1614 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1615 } 1616 1617 /* 1618 * Set up DMA tags for TX buffers. 1619 */ 1620 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1621 1, 0, /* alignment, bounds */ 1622 BUS_SPACE_MAXADDR, /* lowaddr */ 1623 BUS_SPACE_MAXADDR, /* highaddr */ 1624 NULL, NULL, /* filter, filterarg */ 1625 sctx->isc_tx_maxsize, /* maxsize */ 1626 nsegments, /* nsegments */ 1627 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1628 0, /* flags */ 1629 NULL, /* lockfunc */ 1630 NULL, /* lockfuncarg */ 1631 &txq->ift_buf_tag))) { 1632 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1633 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1634 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1635 goto fail; 1636 } 1637 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1638 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1639 1, 0, /* alignment, bounds */ 1640 BUS_SPACE_MAXADDR, /* lowaddr */ 1641 BUS_SPACE_MAXADDR, /* highaddr */ 1642 NULL, NULL, /* filter, filterarg */ 1643 tsomaxsize, /* maxsize */ 1644 ntsosegments, /* nsegments */ 1645 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1646 0, /* flags */ 1647 NULL, /* lockfunc */ 1648 NULL, /* lockfuncarg */ 1649 &txq->ift_tso_buf_tag))) { 1650 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1651 err); 1652 goto fail; 1653 } 1654 1655 /* Allocate memory for the TX mbuf map. */ 1656 if (!(txq->ift_sds.ifsd_m = 1657 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1658 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1659 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1660 err = ENOMEM; 1661 goto fail; 1662 } 1663 1664 /* 1665 * Create the DMA maps for TX buffers. 1666 */ 1667 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1668 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1669 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1670 device_printf(dev, 1671 "Unable to allocate TX buffer DMA map memory\n"); 1672 err = ENOMEM; 1673 goto fail; 1674 } 1675 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1676 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1677 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1678 device_printf(dev, 1679 "Unable to allocate TSO TX buffer map memory\n"); 1680 err = ENOMEM; 1681 goto fail; 1682 } 1683 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1684 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1685 &txq->ift_sds.ifsd_map[i]); 1686 if (err != 0) { 1687 device_printf(dev, "Unable to create TX DMA map\n"); 1688 goto fail; 1689 } 1690 if (!tso) 1691 continue; 1692 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1693 &txq->ift_sds.ifsd_tso_map[i]); 1694 if (err != 0) { 1695 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1696 goto fail; 1697 } 1698 } 1699 return (0); 1700 fail: 1701 /* We free all, it handles case where we are in the middle */ 1702 iflib_tx_structures_free(ctx); 1703 return (err); 1704 } 1705 1706 static void 1707 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1708 { 1709 bus_dmamap_t map; 1710 1711 map = NULL; 1712 if (txq->ift_sds.ifsd_map != NULL) 1713 map = txq->ift_sds.ifsd_map[i]; 1714 if (map != NULL) { 1715 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1716 bus_dmamap_unload(txq->ift_buf_tag, map); 1717 bus_dmamap_destroy(txq->ift_buf_tag, map); 1718 txq->ift_sds.ifsd_map[i] = NULL; 1719 } 1720 1721 map = NULL; 1722 if (txq->ift_sds.ifsd_tso_map != NULL) 1723 map = txq->ift_sds.ifsd_tso_map[i]; 1724 if (map != NULL) { 1725 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1726 BUS_DMASYNC_POSTWRITE); 1727 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1728 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1729 txq->ift_sds.ifsd_tso_map[i] = NULL; 1730 } 1731 } 1732 1733 static void 1734 iflib_txq_destroy(iflib_txq_t txq) 1735 { 1736 if_ctx_t ctx = txq->ift_ctx; 1737 1738 for (int i = 0; i < txq->ift_size; i++) 1739 iflib_txsd_destroy(ctx, txq, i); 1740 if (txq->ift_sds.ifsd_map != NULL) { 1741 free(txq->ift_sds.ifsd_map, M_IFLIB); 1742 txq->ift_sds.ifsd_map = NULL; 1743 } 1744 if (txq->ift_sds.ifsd_tso_map != NULL) { 1745 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1746 txq->ift_sds.ifsd_tso_map = NULL; 1747 } 1748 if (txq->ift_sds.ifsd_m != NULL) { 1749 free(txq->ift_sds.ifsd_m, M_IFLIB); 1750 txq->ift_sds.ifsd_m = NULL; 1751 } 1752 if (txq->ift_buf_tag != NULL) { 1753 bus_dma_tag_destroy(txq->ift_buf_tag); 1754 txq->ift_buf_tag = NULL; 1755 } 1756 if (txq->ift_tso_buf_tag != NULL) { 1757 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1758 txq->ift_tso_buf_tag = NULL; 1759 } 1760 } 1761 1762 static void 1763 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1764 { 1765 struct mbuf **mp; 1766 1767 mp = &txq->ift_sds.ifsd_m[i]; 1768 if (*mp == NULL) 1769 return; 1770 1771 if (txq->ift_sds.ifsd_map != NULL) { 1772 bus_dmamap_sync(txq->ift_buf_tag, 1773 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1774 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1775 } 1776 if (txq->ift_sds.ifsd_tso_map != NULL) { 1777 bus_dmamap_sync(txq->ift_tso_buf_tag, 1778 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1779 bus_dmamap_unload(txq->ift_tso_buf_tag, 1780 txq->ift_sds.ifsd_tso_map[i]); 1781 } 1782 m_free(*mp); 1783 DBG_COUNTER_INC(tx_frees); 1784 *mp = NULL; 1785 } 1786 1787 static int 1788 iflib_txq_setup(iflib_txq_t txq) 1789 { 1790 if_ctx_t ctx = txq->ift_ctx; 1791 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1792 if_shared_ctx_t sctx = ctx->ifc_sctx; 1793 iflib_dma_info_t di; 1794 int i; 1795 1796 /* Set number of descriptors available */ 1797 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1798 /* XXX make configurable */ 1799 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1800 1801 /* Reset indices */ 1802 txq->ift_cidx_processed = 0; 1803 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1804 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1805 1806 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1807 bzero((void *)di->idi_vaddr, di->idi_size); 1808 1809 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1810 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1811 bus_dmamap_sync(di->idi_tag, di->idi_map, 1812 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1813 return (0); 1814 } 1815 1816 /********************************************************************* 1817 * 1818 * Allocate DMA resources for RX buffers as well as memory for the RX 1819 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1820 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1821 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1822 * Since we use use one entry in iflib_sw_rx_desc_array per received 1823 * packet, the maximum number of entries we'll need is equal to the 1824 * number of hardware receive descriptors that we've allocated. 1825 * 1826 **********************************************************************/ 1827 static int 1828 iflib_rxsd_alloc(iflib_rxq_t rxq) 1829 { 1830 if_ctx_t ctx = rxq->ifr_ctx; 1831 if_shared_ctx_t sctx = ctx->ifc_sctx; 1832 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1833 device_t dev = ctx->ifc_dev; 1834 iflib_fl_t fl; 1835 int err; 1836 1837 MPASS(scctx->isc_nrxd[0] > 0); 1838 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1839 1840 fl = rxq->ifr_fl; 1841 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1842 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1843 /* Set up DMA tag for RX buffers. */ 1844 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1845 1, 0, /* alignment, bounds */ 1846 BUS_SPACE_MAXADDR, /* lowaddr */ 1847 BUS_SPACE_MAXADDR, /* highaddr */ 1848 NULL, NULL, /* filter, filterarg */ 1849 sctx->isc_rx_maxsize, /* maxsize */ 1850 sctx->isc_rx_nsegments, /* nsegments */ 1851 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1852 0, /* flags */ 1853 NULL, /* lockfunc */ 1854 NULL, /* lockarg */ 1855 &fl->ifl_buf_tag); 1856 if (err) { 1857 device_printf(dev, 1858 "Unable to allocate RX DMA tag: %d\n", err); 1859 goto fail; 1860 } 1861 1862 /* Allocate memory for the RX mbuf map. */ 1863 if (!(fl->ifl_sds.ifsd_m = 1864 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1865 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1866 device_printf(dev, 1867 "Unable to allocate RX mbuf map memory\n"); 1868 err = ENOMEM; 1869 goto fail; 1870 } 1871 1872 /* Allocate memory for the direct RX cluster pointer map. */ 1873 if (!(fl->ifl_sds.ifsd_cl = 1874 (caddr_t *) malloc(sizeof(caddr_t) * 1875 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1876 device_printf(dev, 1877 "Unable to allocate RX cluster map memory\n"); 1878 err = ENOMEM; 1879 goto fail; 1880 } 1881 1882 /* Allocate memory for the RX cluster bus address map. */ 1883 if (!(fl->ifl_sds.ifsd_ba = 1884 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1885 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1886 device_printf(dev, 1887 "Unable to allocate RX bus address map memory\n"); 1888 err = ENOMEM; 1889 goto fail; 1890 } 1891 1892 /* 1893 * Create the DMA maps for RX buffers. 1894 */ 1895 if (!(fl->ifl_sds.ifsd_map = 1896 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1897 device_printf(dev, 1898 "Unable to allocate RX buffer DMA map memory\n"); 1899 err = ENOMEM; 1900 goto fail; 1901 } 1902 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1903 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1904 &fl->ifl_sds.ifsd_map[i]); 1905 if (err != 0) { 1906 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1907 goto fail; 1908 } 1909 } 1910 } 1911 return (0); 1912 1913 fail: 1914 iflib_rx_structures_free(ctx); 1915 return (err); 1916 } 1917 1918 1919 /* 1920 * Internal service routines 1921 */ 1922 1923 struct rxq_refill_cb_arg { 1924 int error; 1925 bus_dma_segment_t seg; 1926 int nseg; 1927 }; 1928 1929 static void 1930 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1931 { 1932 struct rxq_refill_cb_arg *cb_arg = arg; 1933 1934 cb_arg->error = error; 1935 cb_arg->seg = segs[0]; 1936 cb_arg->nseg = nseg; 1937 } 1938 1939 /** 1940 * rxq_refill - refill an rxq free-buffer list 1941 * @ctx: the iflib context 1942 * @rxq: the free-list to refill 1943 * @n: the number of new buffers to allocate 1944 * 1945 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1946 * The caller must assure that @n does not exceed the queue's capacity. 1947 */ 1948 static void 1949 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1950 { 1951 struct if_rxd_update iru; 1952 struct rxq_refill_cb_arg cb_arg; 1953 struct mbuf *m; 1954 caddr_t cl, *sd_cl; 1955 struct mbuf **sd_m; 1956 bus_dmamap_t *sd_map; 1957 bus_addr_t bus_addr, *sd_ba; 1958 int err, frag_idx, i, idx, n, pidx; 1959 qidx_t credits; 1960 1961 sd_m = fl->ifl_sds.ifsd_m; 1962 sd_map = fl->ifl_sds.ifsd_map; 1963 sd_cl = fl->ifl_sds.ifsd_cl; 1964 sd_ba = fl->ifl_sds.ifsd_ba; 1965 pidx = fl->ifl_pidx; 1966 idx = pidx; 1967 frag_idx = fl->ifl_fragidx; 1968 credits = fl->ifl_credits; 1969 1970 i = 0; 1971 n = count; 1972 MPASS(n > 0); 1973 MPASS(credits + n <= fl->ifl_size); 1974 1975 if (pidx < fl->ifl_cidx) 1976 MPASS(pidx + n <= fl->ifl_cidx); 1977 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1978 MPASS(fl->ifl_gen == 0); 1979 if (pidx > fl->ifl_cidx) 1980 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1981 1982 DBG_COUNTER_INC(fl_refills); 1983 if (n > 8) 1984 DBG_COUNTER_INC(fl_refills_large); 1985 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1986 while (n--) { 1987 /* 1988 * We allocate an uninitialized mbuf + cluster, mbuf is 1989 * initialized after rx. 1990 * 1991 * If the cluster is still set then we know a minimum sized packet was received 1992 */ 1993 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 1994 &frag_idx); 1995 if (frag_idx < 0) 1996 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1997 MPASS(frag_idx >= 0); 1998 if ((cl = sd_cl[frag_idx]) == NULL) { 1999 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 2000 break; 2001 2002 cb_arg.error = 0; 2003 MPASS(sd_map != NULL); 2004 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2005 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2006 BUS_DMA_NOWAIT); 2007 if (err != 0 || cb_arg.error) { 2008 /* 2009 * !zone_pack ? 2010 */ 2011 if (fl->ifl_zone == zone_pack) 2012 uma_zfree(fl->ifl_zone, cl); 2013 break; 2014 } 2015 2016 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2017 sd_cl[frag_idx] = cl; 2018 #if MEMORY_LOGGING 2019 fl->ifl_cl_enqueued++; 2020 #endif 2021 } else { 2022 bus_addr = sd_ba[frag_idx]; 2023 } 2024 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2025 BUS_DMASYNC_PREREAD); 2026 2027 MPASS(sd_m[frag_idx] == NULL); 2028 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 2029 break; 2030 } 2031 sd_m[frag_idx] = m; 2032 bit_set(fl->ifl_rx_bitmap, frag_idx); 2033 #if MEMORY_LOGGING 2034 fl->ifl_m_enqueued++; 2035 #endif 2036 2037 DBG_COUNTER_INC(rx_allocs); 2038 fl->ifl_rxd_idxs[i] = frag_idx; 2039 fl->ifl_bus_addrs[i] = bus_addr; 2040 fl->ifl_vm_addrs[i] = cl; 2041 credits++; 2042 i++; 2043 MPASS(credits <= fl->ifl_size); 2044 if (++idx == fl->ifl_size) { 2045 fl->ifl_gen = 1; 2046 idx = 0; 2047 } 2048 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2049 iru.iru_pidx = pidx; 2050 iru.iru_count = i; 2051 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2052 i = 0; 2053 pidx = idx; 2054 fl->ifl_pidx = idx; 2055 fl->ifl_credits = credits; 2056 } 2057 } 2058 2059 if (i) { 2060 iru.iru_pidx = pidx; 2061 iru.iru_count = i; 2062 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2063 fl->ifl_pidx = idx; 2064 fl->ifl_credits = credits; 2065 } 2066 DBG_COUNTER_INC(rxd_flush); 2067 if (fl->ifl_pidx == 0) 2068 pidx = fl->ifl_size - 1; 2069 else 2070 pidx = fl->ifl_pidx - 1; 2071 2072 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2073 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2074 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2075 fl->ifl_fragidx = frag_idx; 2076 } 2077 2078 static __inline void 2079 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2080 { 2081 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2082 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2083 #ifdef INVARIANTS 2084 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2085 #endif 2086 2087 MPASS(fl->ifl_credits <= fl->ifl_size); 2088 MPASS(reclaimable == delta); 2089 2090 if (reclaimable > 0) 2091 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2092 } 2093 2094 uint8_t 2095 iflib_in_detach(if_ctx_t ctx) 2096 { 2097 bool in_detach; 2098 STATE_LOCK(ctx); 2099 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2100 STATE_UNLOCK(ctx); 2101 return (in_detach); 2102 } 2103 2104 static void 2105 iflib_fl_bufs_free(iflib_fl_t fl) 2106 { 2107 iflib_dma_info_t idi = fl->ifl_ifdi; 2108 bus_dmamap_t sd_map; 2109 uint32_t i; 2110 2111 for (i = 0; i < fl->ifl_size; i++) { 2112 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2113 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2114 2115 if (*sd_cl != NULL) { 2116 sd_map = fl->ifl_sds.ifsd_map[i]; 2117 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2118 BUS_DMASYNC_POSTREAD); 2119 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2120 if (*sd_cl != NULL) 2121 uma_zfree(fl->ifl_zone, *sd_cl); 2122 // XXX: Should this get moved out? 2123 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx)) 2124 bus_dmamap_destroy(fl->ifl_buf_tag, sd_map); 2125 if (*sd_m != NULL) { 2126 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2127 uma_zfree(zone_mbuf, *sd_m); 2128 } 2129 } else { 2130 MPASS(*sd_cl == NULL); 2131 MPASS(*sd_m == NULL); 2132 } 2133 #if MEMORY_LOGGING 2134 fl->ifl_m_dequeued++; 2135 fl->ifl_cl_dequeued++; 2136 #endif 2137 *sd_cl = NULL; 2138 *sd_m = NULL; 2139 } 2140 #ifdef INVARIANTS 2141 for (i = 0; i < fl->ifl_size; i++) { 2142 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2143 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2144 } 2145 #endif 2146 /* 2147 * Reset free list values 2148 */ 2149 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2150 bzero(idi->idi_vaddr, idi->idi_size); 2151 } 2152 2153 /********************************************************************* 2154 * 2155 * Initialize a receive ring and its buffers. 2156 * 2157 **********************************************************************/ 2158 static int 2159 iflib_fl_setup(iflib_fl_t fl) 2160 { 2161 iflib_rxq_t rxq = fl->ifl_rxq; 2162 if_ctx_t ctx = rxq->ifr_ctx; 2163 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2164 2165 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2166 /* 2167 ** Free current RX buffer structs and their mbufs 2168 */ 2169 iflib_fl_bufs_free(fl); 2170 /* Now replenish the mbufs */ 2171 MPASS(fl->ifl_credits == 0); 2172 /* 2173 * XXX don't set the max_frame_size to larger 2174 * than the hardware can handle 2175 */ 2176 if (sctx->isc_max_frame_size <= 2048) 2177 fl->ifl_buf_size = MCLBYTES; 2178 #ifndef CONTIGMALLOC_WORKS 2179 else 2180 fl->ifl_buf_size = MJUMPAGESIZE; 2181 #else 2182 else if (sctx->isc_max_frame_size <= 4096) 2183 fl->ifl_buf_size = MJUMPAGESIZE; 2184 else if (sctx->isc_max_frame_size <= 9216) 2185 fl->ifl_buf_size = MJUM9BYTES; 2186 else 2187 fl->ifl_buf_size = MJUM16BYTES; 2188 #endif 2189 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2190 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2191 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2192 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2193 2194 2195 /* avoid pre-allocating zillions of clusters to an idle card 2196 * potentially speeding up attach 2197 */ 2198 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2199 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2200 if (min(128, fl->ifl_size) != fl->ifl_credits) 2201 return (ENOBUFS); 2202 /* 2203 * handle failure 2204 */ 2205 MPASS(rxq != NULL); 2206 MPASS(fl->ifl_ifdi != NULL); 2207 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2208 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2209 return (0); 2210 } 2211 2212 /********************************************************************* 2213 * 2214 * Free receive ring data structures 2215 * 2216 **********************************************************************/ 2217 static void 2218 iflib_rx_sds_free(iflib_rxq_t rxq) 2219 { 2220 iflib_fl_t fl; 2221 int i, j; 2222 2223 if (rxq->ifr_fl != NULL) { 2224 for (i = 0; i < rxq->ifr_nfl; i++) { 2225 fl = &rxq->ifr_fl[i]; 2226 if (fl->ifl_buf_tag != NULL) { 2227 if (fl->ifl_sds.ifsd_map != NULL) { 2228 for (j = 0; j < fl->ifl_size; j++) { 2229 if (fl->ifl_sds.ifsd_map[j] == 2230 NULL) 2231 continue; 2232 bus_dmamap_sync( 2233 fl->ifl_buf_tag, 2234 fl->ifl_sds.ifsd_map[j], 2235 BUS_DMASYNC_POSTREAD); 2236 bus_dmamap_unload( 2237 fl->ifl_buf_tag, 2238 fl->ifl_sds.ifsd_map[j]); 2239 } 2240 } 2241 bus_dma_tag_destroy(fl->ifl_buf_tag); 2242 fl->ifl_buf_tag = NULL; 2243 } 2244 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2245 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2246 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2247 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2248 fl->ifl_sds.ifsd_m = NULL; 2249 fl->ifl_sds.ifsd_cl = NULL; 2250 fl->ifl_sds.ifsd_ba = NULL; 2251 fl->ifl_sds.ifsd_map = NULL; 2252 } 2253 free(rxq->ifr_fl, M_IFLIB); 2254 rxq->ifr_fl = NULL; 2255 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2256 } 2257 } 2258 2259 /* 2260 * MI independent logic 2261 * 2262 */ 2263 static void 2264 iflib_timer(void *arg) 2265 { 2266 iflib_txq_t txq = arg; 2267 if_ctx_t ctx = txq->ift_ctx; 2268 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2269 uint64_t this_tick = ticks; 2270 uint32_t reset_on = hz / 2; 2271 2272 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2273 return; 2274 /* 2275 ** Check on the state of the TX queue(s), this 2276 ** can be done without the lock because its RO 2277 ** and the HUNG state will be static if set. 2278 */ 2279 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2280 txq->ift_last_timer_tick = this_tick; 2281 IFDI_TIMER(ctx, txq->ift_id); 2282 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2283 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2284 (sctx->isc_pause_frames == 0))) 2285 goto hung; 2286 2287 if (ifmp_ring_is_stalled(txq->ift_br)) 2288 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2289 txq->ift_cleaned_prev = txq->ift_cleaned; 2290 } 2291 #ifdef DEV_NETMAP 2292 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2293 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 2294 #endif 2295 /* handle any laggards */ 2296 if (txq->ift_db_pending) 2297 GROUPTASK_ENQUEUE(&txq->ift_task); 2298 2299 sctx->isc_pause_frames = 0; 2300 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2301 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2302 return; 2303 hung: 2304 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2305 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2306 STATE_LOCK(ctx); 2307 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2308 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2309 iflib_admin_intr_deferred(ctx); 2310 STATE_UNLOCK(ctx); 2311 } 2312 2313 static void 2314 iflib_init_locked(if_ctx_t ctx) 2315 { 2316 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2317 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2318 if_t ifp = ctx->ifc_ifp; 2319 iflib_fl_t fl; 2320 iflib_txq_t txq; 2321 iflib_rxq_t rxq; 2322 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2323 2324 2325 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2326 IFDI_INTR_DISABLE(ctx); 2327 2328 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2329 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2330 /* Set hardware offload abilities */ 2331 if_clearhwassist(ifp); 2332 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2333 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2334 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2335 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2336 if (if_getcapenable(ifp) & IFCAP_TSO4) 2337 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2338 if (if_getcapenable(ifp) & IFCAP_TSO6) 2339 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2340 2341 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2342 CALLOUT_LOCK(txq); 2343 callout_stop(&txq->ift_timer); 2344 CALLOUT_UNLOCK(txq); 2345 iflib_netmap_txq_init(ctx, txq); 2346 } 2347 #ifdef INVARIANTS 2348 i = if_getdrvflags(ifp); 2349 #endif 2350 IFDI_INIT(ctx); 2351 MPASS(if_getdrvflags(ifp) == i); 2352 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2353 /* XXX this should really be done on a per-queue basis */ 2354 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2355 MPASS(rxq->ifr_id == i); 2356 iflib_netmap_rxq_init(ctx, rxq); 2357 continue; 2358 } 2359 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2360 if (iflib_fl_setup(fl)) { 2361 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2362 goto done; 2363 } 2364 } 2365 } 2366 done: 2367 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2368 IFDI_INTR_ENABLE(ctx); 2369 txq = ctx->ifc_txqs; 2370 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2371 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2372 txq->ift_timer.c_cpu); 2373 } 2374 2375 static int 2376 iflib_media_change(if_t ifp) 2377 { 2378 if_ctx_t ctx = if_getsoftc(ifp); 2379 int err; 2380 2381 CTX_LOCK(ctx); 2382 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2383 iflib_init_locked(ctx); 2384 CTX_UNLOCK(ctx); 2385 return (err); 2386 } 2387 2388 static void 2389 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2390 { 2391 if_ctx_t ctx = if_getsoftc(ifp); 2392 2393 CTX_LOCK(ctx); 2394 IFDI_UPDATE_ADMIN_STATUS(ctx); 2395 IFDI_MEDIA_STATUS(ctx, ifmr); 2396 CTX_UNLOCK(ctx); 2397 } 2398 2399 void 2400 iflib_stop(if_ctx_t ctx) 2401 { 2402 iflib_txq_t txq = ctx->ifc_txqs; 2403 iflib_rxq_t rxq = ctx->ifc_rxqs; 2404 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2405 if_shared_ctx_t sctx = ctx->ifc_sctx; 2406 iflib_dma_info_t di; 2407 iflib_fl_t fl; 2408 int i, j; 2409 2410 /* Tell the stack that the interface is no longer active */ 2411 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2412 2413 IFDI_INTR_DISABLE(ctx); 2414 DELAY(1000); 2415 IFDI_STOP(ctx); 2416 DELAY(1000); 2417 2418 iflib_debug_reset(); 2419 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2420 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2421 /* make sure all transmitters have completed before proceeding XXX */ 2422 2423 CALLOUT_LOCK(txq); 2424 callout_stop(&txq->ift_timer); 2425 CALLOUT_UNLOCK(txq); 2426 2427 /* clean any enqueued buffers */ 2428 iflib_ifmp_purge(txq); 2429 /* Free any existing tx buffers. */ 2430 for (j = 0; j < txq->ift_size; j++) { 2431 iflib_txsd_free(ctx, txq, j); 2432 } 2433 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2434 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2435 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2436 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2437 txq->ift_pullups = 0; 2438 ifmp_ring_reset_stats(txq->ift_br); 2439 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2440 bzero((void *)di->idi_vaddr, di->idi_size); 2441 } 2442 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2443 /* make sure all transmitters have completed before proceeding XXX */ 2444 2445 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2446 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2447 bzero((void *)di->idi_vaddr, di->idi_size); 2448 /* also resets the free lists pidx/cidx */ 2449 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2450 iflib_fl_bufs_free(fl); 2451 } 2452 } 2453 2454 static inline caddr_t 2455 calc_next_rxd(iflib_fl_t fl, int cidx) 2456 { 2457 qidx_t size; 2458 int nrxd; 2459 caddr_t start, end, cur, next; 2460 2461 nrxd = fl->ifl_size; 2462 size = fl->ifl_rxd_size; 2463 start = fl->ifl_ifdi->idi_vaddr; 2464 2465 if (__predict_false(size == 0)) 2466 return (start); 2467 cur = start + size*cidx; 2468 end = start + size*nrxd; 2469 next = CACHE_PTR_NEXT(cur); 2470 return (next < end ? next : start); 2471 } 2472 2473 static inline void 2474 prefetch_pkts(iflib_fl_t fl, int cidx) 2475 { 2476 int nextptr; 2477 int nrxd = fl->ifl_size; 2478 caddr_t next_rxd; 2479 2480 2481 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2482 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2483 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2484 next_rxd = calc_next_rxd(fl, cidx); 2485 prefetch(next_rxd); 2486 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2487 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2488 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2489 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2490 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2491 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2492 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2493 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2494 } 2495 2496 static void 2497 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2498 { 2499 int flid, cidx; 2500 bus_dmamap_t map; 2501 iflib_fl_t fl; 2502 int next; 2503 2504 map = NULL; 2505 flid = irf->irf_flid; 2506 cidx = irf->irf_idx; 2507 fl = &rxq->ifr_fl[flid]; 2508 sd->ifsd_fl = fl; 2509 sd->ifsd_cidx = cidx; 2510 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2511 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2512 fl->ifl_credits--; 2513 #if MEMORY_LOGGING 2514 fl->ifl_m_dequeued++; 2515 #endif 2516 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2517 prefetch_pkts(fl, cidx); 2518 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2519 prefetch(&fl->ifl_sds.ifsd_map[next]); 2520 map = fl->ifl_sds.ifsd_map[cidx]; 2521 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2522 2523 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2524 MPASS(fl->ifl_cidx == cidx); 2525 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2526 if (unload) 2527 bus_dmamap_unload(fl->ifl_buf_tag, map); 2528 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2529 if (__predict_false(fl->ifl_cidx == 0)) 2530 fl->ifl_gen = 0; 2531 bit_clear(fl->ifl_rx_bitmap, cidx); 2532 } 2533 2534 static struct mbuf * 2535 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2536 { 2537 int i, padlen , flags; 2538 struct mbuf *m, *mh, *mt; 2539 caddr_t cl; 2540 2541 i = 0; 2542 mh = NULL; 2543 do { 2544 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2545 2546 MPASS(*sd->ifsd_cl != NULL); 2547 MPASS(*sd->ifsd_m != NULL); 2548 2549 /* Don't include zero-length frags */ 2550 if (ri->iri_frags[i].irf_len == 0) { 2551 /* XXX we can save the cluster here, but not the mbuf */ 2552 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2553 m_free(*sd->ifsd_m); 2554 *sd->ifsd_m = NULL; 2555 continue; 2556 } 2557 m = *sd->ifsd_m; 2558 *sd->ifsd_m = NULL; 2559 if (mh == NULL) { 2560 flags = M_PKTHDR|M_EXT; 2561 mh = mt = m; 2562 padlen = ri->iri_pad; 2563 } else { 2564 flags = M_EXT; 2565 mt->m_next = m; 2566 mt = m; 2567 /* assuming padding is only on the first fragment */ 2568 padlen = 0; 2569 } 2570 cl = *sd->ifsd_cl; 2571 *sd->ifsd_cl = NULL; 2572 2573 /* Can these two be made one ? */ 2574 m_init(m, M_NOWAIT, MT_DATA, flags); 2575 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2576 /* 2577 * These must follow m_init and m_cljset 2578 */ 2579 m->m_data += padlen; 2580 ri->iri_len -= padlen; 2581 m->m_len = ri->iri_frags[i].irf_len; 2582 } while (++i < ri->iri_nfrags); 2583 2584 return (mh); 2585 } 2586 2587 /* 2588 * Process one software descriptor 2589 */ 2590 static struct mbuf * 2591 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2592 { 2593 struct if_rxsd sd; 2594 struct mbuf *m; 2595 2596 /* should I merge this back in now that the two paths are basically duplicated? */ 2597 if (ri->iri_nfrags == 1 && 2598 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2599 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2600 m = *sd.ifsd_m; 2601 *sd.ifsd_m = NULL; 2602 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2603 #ifndef __NO_STRICT_ALIGNMENT 2604 if (!IP_ALIGNED(m)) 2605 m->m_data += 2; 2606 #endif 2607 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2608 m->m_len = ri->iri_frags[0].irf_len; 2609 } else { 2610 m = assemble_segments(rxq, ri, &sd); 2611 } 2612 m->m_pkthdr.len = ri->iri_len; 2613 m->m_pkthdr.rcvif = ri->iri_ifp; 2614 m->m_flags |= ri->iri_flags; 2615 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2616 m->m_pkthdr.flowid = ri->iri_flowid; 2617 M_HASHTYPE_SET(m, ri->iri_rsstype); 2618 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2619 m->m_pkthdr.csum_data = ri->iri_csum_data; 2620 return (m); 2621 } 2622 2623 #if defined(INET6) || defined(INET) 2624 static void 2625 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2626 { 2627 CURVNET_SET(lc->ifp->if_vnet); 2628 #if defined(INET6) 2629 *v6 = VNET(ip6_forwarding); 2630 #endif 2631 #if defined(INET) 2632 *v4 = VNET(ipforwarding); 2633 #endif 2634 CURVNET_RESTORE(); 2635 } 2636 2637 /* 2638 * Returns true if it's possible this packet could be LROed. 2639 * if it returns false, it is guaranteed that tcp_lro_rx() 2640 * would not return zero. 2641 */ 2642 static bool 2643 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2644 { 2645 struct ether_header *eh; 2646 uint16_t eh_type; 2647 2648 eh = mtod(m, struct ether_header *); 2649 eh_type = ntohs(eh->ether_type); 2650 switch (eh_type) { 2651 #if defined(INET6) 2652 case ETHERTYPE_IPV6: 2653 return !v6_forwarding; 2654 #endif 2655 #if defined (INET) 2656 case ETHERTYPE_IP: 2657 return !v4_forwarding; 2658 #endif 2659 } 2660 2661 return false; 2662 } 2663 #else 2664 static void 2665 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2666 { 2667 } 2668 #endif 2669 2670 static bool 2671 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2672 { 2673 if_ctx_t ctx = rxq->ifr_ctx; 2674 if_shared_ctx_t sctx = ctx->ifc_sctx; 2675 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2676 int avail, i; 2677 qidx_t *cidxp; 2678 struct if_rxd_info ri; 2679 int err, budget_left, rx_bytes, rx_pkts; 2680 iflib_fl_t fl; 2681 struct ifnet *ifp; 2682 int lro_enabled; 2683 bool v4_forwarding, v6_forwarding, lro_possible; 2684 2685 /* 2686 * XXX early demux data packets so that if_input processing only handles 2687 * acks in interrupt context 2688 */ 2689 struct mbuf *m, *mh, *mt, *mf; 2690 2691 lro_possible = v4_forwarding = v6_forwarding = false; 2692 ifp = ctx->ifc_ifp; 2693 mh = mt = NULL; 2694 MPASS(budget > 0); 2695 rx_pkts = rx_bytes = 0; 2696 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2697 cidxp = &rxq->ifr_cq_cidx; 2698 else 2699 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2700 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2701 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2702 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2703 DBG_COUNTER_INC(rx_unavail); 2704 return (false); 2705 } 2706 2707 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2708 if (__predict_false(!CTX_ACTIVE(ctx))) { 2709 DBG_COUNTER_INC(rx_ctx_inactive); 2710 break; 2711 } 2712 /* 2713 * Reset client set fields to their default values 2714 */ 2715 rxd_info_zero(&ri); 2716 ri.iri_qsidx = rxq->ifr_id; 2717 ri.iri_cidx = *cidxp; 2718 ri.iri_ifp = ifp; 2719 ri.iri_frags = rxq->ifr_frags; 2720 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2721 2722 if (err) 2723 goto err; 2724 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2725 *cidxp = ri.iri_cidx; 2726 /* Update our consumer index */ 2727 /* XXX NB: shurd - check if this is still safe */ 2728 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2729 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2730 rxq->ifr_cq_gen = 0; 2731 } 2732 /* was this only a completion queue message? */ 2733 if (__predict_false(ri.iri_nfrags == 0)) 2734 continue; 2735 } 2736 MPASS(ri.iri_nfrags != 0); 2737 MPASS(ri.iri_len != 0); 2738 2739 /* will advance the cidx on the corresponding free lists */ 2740 m = iflib_rxd_pkt_get(rxq, &ri); 2741 avail--; 2742 budget_left--; 2743 if (avail == 0 && budget_left) 2744 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2745 2746 if (__predict_false(m == NULL)) { 2747 DBG_COUNTER_INC(rx_mbuf_null); 2748 continue; 2749 } 2750 /* imm_pkt: -- cxgb */ 2751 if (mh == NULL) 2752 mh = mt = m; 2753 else { 2754 mt->m_nextpkt = m; 2755 mt = m; 2756 } 2757 } 2758 /* make sure that we can refill faster than drain */ 2759 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2760 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2761 2762 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2763 if (lro_enabled) 2764 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2765 mt = mf = NULL; 2766 while (mh != NULL) { 2767 m = mh; 2768 mh = mh->m_nextpkt; 2769 m->m_nextpkt = NULL; 2770 #ifndef __NO_STRICT_ALIGNMENT 2771 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2772 continue; 2773 #endif 2774 rx_bytes += m->m_pkthdr.len; 2775 rx_pkts++; 2776 #if defined(INET6) || defined(INET) 2777 if (lro_enabled) { 2778 if (!lro_possible) { 2779 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2780 if (lro_possible && mf != NULL) { 2781 ifp->if_input(ifp, mf); 2782 DBG_COUNTER_INC(rx_if_input); 2783 mt = mf = NULL; 2784 } 2785 } 2786 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2787 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2788 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2789 continue; 2790 } 2791 } 2792 #endif 2793 if (lro_possible) { 2794 ifp->if_input(ifp, m); 2795 DBG_COUNTER_INC(rx_if_input); 2796 continue; 2797 } 2798 2799 if (mf == NULL) 2800 mf = m; 2801 if (mt != NULL) 2802 mt->m_nextpkt = m; 2803 mt = m; 2804 } 2805 if (mf != NULL) { 2806 ifp->if_input(ifp, mf); 2807 DBG_COUNTER_INC(rx_if_input); 2808 } 2809 2810 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2811 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2812 2813 /* 2814 * Flush any outstanding LRO work 2815 */ 2816 #if defined(INET6) || defined(INET) 2817 tcp_lro_flush_all(&rxq->ifr_lc); 2818 #endif 2819 if (avail) 2820 return true; 2821 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2822 err: 2823 STATE_LOCK(ctx); 2824 ctx->ifc_flags |= IFC_DO_RESET; 2825 iflib_admin_intr_deferred(ctx); 2826 STATE_UNLOCK(ctx); 2827 return (false); 2828 } 2829 2830 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2831 static inline qidx_t 2832 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2833 { 2834 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2835 qidx_t minthresh = txq->ift_size / 8; 2836 if (in_use > 4*minthresh) 2837 return (notify_count); 2838 if (in_use > 2*minthresh) 2839 return (notify_count >> 1); 2840 if (in_use > minthresh) 2841 return (notify_count >> 3); 2842 return (0); 2843 } 2844 2845 static inline qidx_t 2846 txq_max_rs_deferred(iflib_txq_t txq) 2847 { 2848 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2849 qidx_t minthresh = txq->ift_size / 8; 2850 if (txq->ift_in_use > 4*minthresh) 2851 return (notify_count); 2852 if (txq->ift_in_use > 2*minthresh) 2853 return (notify_count >> 1); 2854 if (txq->ift_in_use > minthresh) 2855 return (notify_count >> 2); 2856 return (2); 2857 } 2858 2859 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2860 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2861 2862 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2863 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2864 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2865 2866 /* forward compatibility for cxgb */ 2867 #define FIRST_QSET(ctx) 0 2868 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2869 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2870 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2871 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2872 2873 /* XXX we should be setting this to something other than zero */ 2874 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2875 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2876 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2877 2878 static inline bool 2879 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2880 { 2881 qidx_t dbval, max; 2882 bool rang; 2883 2884 rang = false; 2885 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2886 if (ring || txq->ift_db_pending >= max) { 2887 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2888 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 2889 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2890 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2891 txq->ift_db_pending = txq->ift_npending = 0; 2892 rang = true; 2893 } 2894 return (rang); 2895 } 2896 2897 #ifdef PKT_DEBUG 2898 static void 2899 print_pkt(if_pkt_info_t pi) 2900 { 2901 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2902 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2903 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2904 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2905 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2906 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2907 } 2908 #endif 2909 2910 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2911 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2912 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2913 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2914 2915 static int 2916 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2917 { 2918 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2919 struct ether_vlan_header *eh; 2920 struct mbuf *m; 2921 2922 m = *mp; 2923 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2924 M_WRITABLE(m) == 0) { 2925 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2926 return (ENOMEM); 2927 } else { 2928 m_freem(*mp); 2929 DBG_COUNTER_INC(tx_frees); 2930 *mp = m; 2931 } 2932 } 2933 2934 /* 2935 * Determine where frame payload starts. 2936 * Jump over vlan headers if already present, 2937 * helpful for QinQ too. 2938 */ 2939 if (__predict_false(m->m_len < sizeof(*eh))) { 2940 txq->ift_pullups++; 2941 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2942 return (ENOMEM); 2943 } 2944 eh = mtod(m, struct ether_vlan_header *); 2945 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2946 pi->ipi_etype = ntohs(eh->evl_proto); 2947 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2948 } else { 2949 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2950 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2951 } 2952 2953 switch (pi->ipi_etype) { 2954 #ifdef INET 2955 case ETHERTYPE_IP: 2956 { 2957 struct mbuf *n; 2958 struct ip *ip = NULL; 2959 struct tcphdr *th = NULL; 2960 int minthlen; 2961 2962 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2963 if (__predict_false(m->m_len < minthlen)) { 2964 /* 2965 * if this code bloat is causing too much of a hit 2966 * move it to a separate function and mark it noinline 2967 */ 2968 if (m->m_len == pi->ipi_ehdrlen) { 2969 n = m->m_next; 2970 MPASS(n); 2971 if (n->m_len >= sizeof(*ip)) { 2972 ip = (struct ip *)n->m_data; 2973 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2974 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2975 } else { 2976 txq->ift_pullups++; 2977 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2978 return (ENOMEM); 2979 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2980 } 2981 } else { 2982 txq->ift_pullups++; 2983 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2984 return (ENOMEM); 2985 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2986 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2987 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2988 } 2989 } else { 2990 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2991 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2992 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2993 } 2994 pi->ipi_ip_hlen = ip->ip_hl << 2; 2995 pi->ipi_ipproto = ip->ip_p; 2996 pi->ipi_flags |= IPI_TX_IPV4; 2997 2998 /* TCP checksum offload may require TCP header length */ 2999 if (IS_TX_OFFLOAD4(pi)) { 3000 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3001 if (__predict_false(th == NULL)) { 3002 txq->ift_pullups++; 3003 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3004 return (ENOMEM); 3005 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3006 } 3007 pi->ipi_tcp_hflags = th->th_flags; 3008 pi->ipi_tcp_hlen = th->th_off << 2; 3009 pi->ipi_tcp_seq = th->th_seq; 3010 } 3011 if (IS_TSO4(pi)) { 3012 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3013 return (ENXIO); 3014 /* 3015 * TSO always requires hardware checksum offload. 3016 */ 3017 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3018 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3019 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3020 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3021 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3022 ip->ip_sum = 0; 3023 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3024 } 3025 } 3026 } 3027 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3028 ip->ip_sum = 0; 3029 3030 break; 3031 } 3032 #endif 3033 #ifdef INET6 3034 case ETHERTYPE_IPV6: 3035 { 3036 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3037 struct tcphdr *th; 3038 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3039 3040 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3041 txq->ift_pullups++; 3042 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3043 return (ENOMEM); 3044 } 3045 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3046 3047 /* XXX-BZ this will go badly in case of ext hdrs. */ 3048 pi->ipi_ipproto = ip6->ip6_nxt; 3049 pi->ipi_flags |= IPI_TX_IPV6; 3050 3051 /* TCP checksum offload may require TCP header length */ 3052 if (IS_TX_OFFLOAD6(pi)) { 3053 if (pi->ipi_ipproto == IPPROTO_TCP) { 3054 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3055 txq->ift_pullups++; 3056 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3057 return (ENOMEM); 3058 } 3059 pi->ipi_tcp_hflags = th->th_flags; 3060 pi->ipi_tcp_hlen = th->th_off << 2; 3061 pi->ipi_tcp_seq = th->th_seq; 3062 } 3063 if (IS_TSO6(pi)) { 3064 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3065 return (ENXIO); 3066 /* 3067 * TSO always requires hardware checksum offload. 3068 */ 3069 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3070 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3071 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3072 } 3073 } 3074 break; 3075 } 3076 #endif 3077 default: 3078 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3079 pi->ipi_ip_hlen = 0; 3080 break; 3081 } 3082 *mp = m; 3083 3084 return (0); 3085 } 3086 3087 /* 3088 * If dodgy hardware rejects the scatter gather chain we've handed it 3089 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3090 * m_defrag'd mbufs 3091 */ 3092 static __noinline struct mbuf * 3093 iflib_remove_mbuf(iflib_txq_t txq) 3094 { 3095 int ntxd, pidx; 3096 struct mbuf *m, **ifsd_m; 3097 3098 ifsd_m = txq->ift_sds.ifsd_m; 3099 ntxd = txq->ift_size; 3100 pidx = txq->ift_pidx & (ntxd - 1); 3101 ifsd_m = txq->ift_sds.ifsd_m; 3102 m = ifsd_m[pidx]; 3103 ifsd_m[pidx] = NULL; 3104 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3105 if (txq->ift_sds.ifsd_tso_map != NULL) 3106 bus_dmamap_unload(txq->ift_tso_buf_tag, 3107 txq->ift_sds.ifsd_tso_map[pidx]); 3108 #if MEMORY_LOGGING 3109 txq->ift_dequeued++; 3110 #endif 3111 return (m); 3112 } 3113 3114 static inline caddr_t 3115 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3116 { 3117 qidx_t size; 3118 int ntxd; 3119 caddr_t start, end, cur, next; 3120 3121 ntxd = txq->ift_size; 3122 size = txq->ift_txd_size[qid]; 3123 start = txq->ift_ifdi[qid].idi_vaddr; 3124 3125 if (__predict_false(size == 0)) 3126 return (start); 3127 cur = start + size*cidx; 3128 end = start + size*ntxd; 3129 next = CACHE_PTR_NEXT(cur); 3130 return (next < end ? next : start); 3131 } 3132 3133 /* 3134 * Pad an mbuf to ensure a minimum ethernet frame size. 3135 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3136 */ 3137 static __noinline int 3138 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3139 { 3140 /* 3141 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3142 * and ARP message is the smallest common payload I can think of 3143 */ 3144 static char pad[18]; /* just zeros */ 3145 int n; 3146 struct mbuf *new_head; 3147 3148 if (!M_WRITABLE(*m_head)) { 3149 new_head = m_dup(*m_head, M_NOWAIT); 3150 if (new_head == NULL) { 3151 m_freem(*m_head); 3152 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3153 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3154 DBG_COUNTER_INC(tx_frees); 3155 return ENOMEM; 3156 } 3157 m_freem(*m_head); 3158 *m_head = new_head; 3159 } 3160 3161 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3162 n > 0; n -= sizeof(pad)) 3163 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3164 break; 3165 3166 if (n > 0) { 3167 m_freem(*m_head); 3168 device_printf(dev, "cannot pad short frame\n"); 3169 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3170 DBG_COUNTER_INC(tx_frees); 3171 return (ENOBUFS); 3172 } 3173 3174 return 0; 3175 } 3176 3177 static int 3178 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3179 { 3180 if_ctx_t ctx; 3181 if_shared_ctx_t sctx; 3182 if_softc_ctx_t scctx; 3183 bus_dma_tag_t buf_tag; 3184 bus_dma_segment_t *segs; 3185 struct mbuf *m_head, **ifsd_m; 3186 void *next_txd; 3187 bus_dmamap_t map; 3188 struct if_pkt_info pi; 3189 int remap = 0; 3190 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3191 3192 ctx = txq->ift_ctx; 3193 sctx = ctx->ifc_sctx; 3194 scctx = &ctx->ifc_softc_ctx; 3195 segs = txq->ift_segs; 3196 ntxd = txq->ift_size; 3197 m_head = *m_headp; 3198 map = NULL; 3199 3200 /* 3201 * If we're doing TSO the next descriptor to clean may be quite far ahead 3202 */ 3203 cidx = txq->ift_cidx; 3204 pidx = txq->ift_pidx; 3205 if (ctx->ifc_flags & IFC_PREFETCH) { 3206 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3207 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3208 next_txd = calc_next_txd(txq, cidx, 0); 3209 prefetch(next_txd); 3210 } 3211 3212 /* prefetch the next cache line of mbuf pointers and flags */ 3213 prefetch(&txq->ift_sds.ifsd_m[next]); 3214 prefetch(&txq->ift_sds.ifsd_map[next]); 3215 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3216 } 3217 map = txq->ift_sds.ifsd_map[pidx]; 3218 ifsd_m = txq->ift_sds.ifsd_m; 3219 3220 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3221 buf_tag = txq->ift_tso_buf_tag; 3222 max_segs = scctx->isc_tx_tso_segments_max; 3223 map = txq->ift_sds.ifsd_tso_map[pidx]; 3224 MPASS(buf_tag != NULL); 3225 MPASS(max_segs > 0); 3226 } else { 3227 buf_tag = txq->ift_buf_tag; 3228 max_segs = scctx->isc_tx_nsegments; 3229 map = txq->ift_sds.ifsd_map[pidx]; 3230 } 3231 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3232 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3233 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3234 if (err) { 3235 DBG_COUNTER_INC(encap_txd_encap_fail); 3236 return err; 3237 } 3238 } 3239 m_head = *m_headp; 3240 3241 pkt_info_zero(&pi); 3242 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3243 pi.ipi_pidx = pidx; 3244 pi.ipi_qsidx = txq->ift_id; 3245 pi.ipi_len = m_head->m_pkthdr.len; 3246 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3247 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3248 3249 /* deliberate bitwise OR to make one condition */ 3250 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3251 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3252 DBG_COUNTER_INC(encap_txd_encap_fail); 3253 return (err); 3254 } 3255 m_head = *m_headp; 3256 } 3257 3258 retry: 3259 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3260 BUS_DMA_NOWAIT); 3261 defrag: 3262 if (__predict_false(err)) { 3263 switch (err) { 3264 case EFBIG: 3265 /* try collapse once and defrag once */ 3266 if (remap == 0) { 3267 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3268 /* try defrag if collapsing fails */ 3269 if (m_head == NULL) 3270 remap++; 3271 } 3272 if (remap == 1) { 3273 txq->ift_mbuf_defrag++; 3274 m_head = m_defrag(*m_headp, M_NOWAIT); 3275 } 3276 remap++; 3277 if (__predict_false(m_head == NULL)) 3278 goto defrag_failed; 3279 *m_headp = m_head; 3280 goto retry; 3281 break; 3282 case ENOMEM: 3283 txq->ift_no_tx_dma_setup++; 3284 break; 3285 default: 3286 txq->ift_no_tx_dma_setup++; 3287 m_freem(*m_headp); 3288 DBG_COUNTER_INC(tx_frees); 3289 *m_headp = NULL; 3290 break; 3291 } 3292 txq->ift_map_failed++; 3293 DBG_COUNTER_INC(encap_load_mbuf_fail); 3294 DBG_COUNTER_INC(encap_txd_encap_fail); 3295 return (err); 3296 } 3297 ifsd_m[pidx] = m_head; 3298 /* 3299 * XXX assumes a 1 to 1 relationship between segments and 3300 * descriptors - this does not hold true on all drivers, e.g. 3301 * cxgb 3302 */ 3303 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3304 txq->ift_no_desc_avail++; 3305 bus_dmamap_unload(buf_tag, map); 3306 DBG_COUNTER_INC(encap_txq_avail_fail); 3307 DBG_COUNTER_INC(encap_txd_encap_fail); 3308 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3309 GROUPTASK_ENQUEUE(&txq->ift_task); 3310 return (ENOBUFS); 3311 } 3312 /* 3313 * On Intel cards we can greatly reduce the number of TX interrupts 3314 * we see by only setting report status on every Nth descriptor. 3315 * However, this also means that the driver will need to keep track 3316 * of the descriptors that RS was set on to check them for the DD bit. 3317 */ 3318 txq->ift_rs_pending += nsegs + 1; 3319 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3320 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3321 pi.ipi_flags |= IPI_TX_INTR; 3322 txq->ift_rs_pending = 0; 3323 } 3324 3325 pi.ipi_segs = segs; 3326 pi.ipi_nsegs = nsegs; 3327 3328 MPASS(pidx >= 0 && pidx < txq->ift_size); 3329 #ifdef PKT_DEBUG 3330 print_pkt(&pi); 3331 #endif 3332 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3333 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3334 DBG_COUNTER_INC(tx_encap); 3335 MPASS(pi.ipi_new_pidx < txq->ift_size); 3336 3337 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3338 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3339 ndesc += txq->ift_size; 3340 txq->ift_gen = 1; 3341 } 3342 /* 3343 * drivers can need as many as 3344 * two sentinels 3345 */ 3346 MPASS(ndesc <= pi.ipi_nsegs + 2); 3347 MPASS(pi.ipi_new_pidx != pidx); 3348 MPASS(ndesc > 0); 3349 txq->ift_in_use += ndesc; 3350 3351 /* 3352 * We update the last software descriptor again here because there may 3353 * be a sentinel and/or there may be more mbufs than segments 3354 */ 3355 txq->ift_pidx = pi.ipi_new_pidx; 3356 txq->ift_npending += pi.ipi_ndescs; 3357 } else { 3358 *m_headp = m_head = iflib_remove_mbuf(txq); 3359 if (err == EFBIG) { 3360 txq->ift_txd_encap_efbig++; 3361 if (remap < 2) { 3362 remap = 1; 3363 goto defrag; 3364 } 3365 } 3366 goto defrag_failed; 3367 } 3368 /* 3369 * err can't possibly be non-zero here, so we don't neet to test it 3370 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3371 */ 3372 return (err); 3373 3374 defrag_failed: 3375 txq->ift_mbuf_defrag_failed++; 3376 txq->ift_map_failed++; 3377 m_freem(*m_headp); 3378 DBG_COUNTER_INC(tx_frees); 3379 *m_headp = NULL; 3380 DBG_COUNTER_INC(encap_txd_encap_fail); 3381 return (ENOMEM); 3382 } 3383 3384 static void 3385 iflib_tx_desc_free(iflib_txq_t txq, int n) 3386 { 3387 uint32_t qsize, cidx, mask, gen; 3388 struct mbuf *m, **ifsd_m; 3389 bool do_prefetch; 3390 3391 cidx = txq->ift_cidx; 3392 gen = txq->ift_gen; 3393 qsize = txq->ift_size; 3394 mask = qsize-1; 3395 ifsd_m = txq->ift_sds.ifsd_m; 3396 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3397 3398 while (n-- > 0) { 3399 if (do_prefetch) { 3400 prefetch(ifsd_m[(cidx + 3) & mask]); 3401 prefetch(ifsd_m[(cidx + 4) & mask]); 3402 } 3403 if ((m = ifsd_m[cidx]) != NULL) { 3404 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3405 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3406 bus_dmamap_sync(txq->ift_tso_buf_tag, 3407 txq->ift_sds.ifsd_tso_map[cidx], 3408 BUS_DMASYNC_POSTWRITE); 3409 bus_dmamap_unload(txq->ift_tso_buf_tag, 3410 txq->ift_sds.ifsd_tso_map[cidx]); 3411 } else { 3412 bus_dmamap_sync(txq->ift_buf_tag, 3413 txq->ift_sds.ifsd_map[cidx], 3414 BUS_DMASYNC_POSTWRITE); 3415 bus_dmamap_unload(txq->ift_buf_tag, 3416 txq->ift_sds.ifsd_map[cidx]); 3417 } 3418 /* XXX we don't support any drivers that batch packets yet */ 3419 MPASS(m->m_nextpkt == NULL); 3420 m_freem(m); 3421 ifsd_m[cidx] = NULL; 3422 #if MEMORY_LOGGING 3423 txq->ift_dequeued++; 3424 #endif 3425 DBG_COUNTER_INC(tx_frees); 3426 } 3427 if (__predict_false(++cidx == qsize)) { 3428 cidx = 0; 3429 gen = 0; 3430 } 3431 } 3432 txq->ift_cidx = cidx; 3433 txq->ift_gen = gen; 3434 } 3435 3436 static __inline int 3437 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3438 { 3439 int reclaim; 3440 if_ctx_t ctx = txq->ift_ctx; 3441 3442 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3443 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3444 3445 /* 3446 * Need a rate-limiting check so that this isn't called every time 3447 */ 3448 iflib_tx_credits_update(ctx, txq); 3449 reclaim = DESC_RECLAIMABLE(txq); 3450 3451 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3452 #ifdef INVARIANTS 3453 if (iflib_verbose_debug) { 3454 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3455 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3456 reclaim, thresh); 3457 3458 } 3459 #endif 3460 return (0); 3461 } 3462 iflib_tx_desc_free(txq, reclaim); 3463 txq->ift_cleaned += reclaim; 3464 txq->ift_in_use -= reclaim; 3465 3466 return (reclaim); 3467 } 3468 3469 static struct mbuf ** 3470 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3471 { 3472 int next, size; 3473 struct mbuf **items; 3474 3475 size = r->size; 3476 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3477 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3478 3479 prefetch(items[(cidx + offset) & (size-1)]); 3480 if (remaining > 1) { 3481 prefetch2cachelines(&items[next]); 3482 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3483 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3484 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3485 } 3486 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3487 } 3488 3489 static void 3490 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3491 { 3492 3493 ifmp_ring_check_drainage(txq->ift_br, budget); 3494 } 3495 3496 static uint32_t 3497 iflib_txq_can_drain(struct ifmp_ring *r) 3498 { 3499 iflib_txq_t txq = r->cookie; 3500 if_ctx_t ctx = txq->ift_ctx; 3501 3502 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3503 return (1); 3504 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3505 BUS_DMASYNC_POSTREAD); 3506 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3507 false)); 3508 } 3509 3510 static uint32_t 3511 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3512 { 3513 iflib_txq_t txq = r->cookie; 3514 if_ctx_t ctx = txq->ift_ctx; 3515 struct ifnet *ifp = ctx->ifc_ifp; 3516 struct mbuf **mp, *m; 3517 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3518 int reclaimed, err, in_use_prev, desc_used; 3519 bool do_prefetch, ring, rang; 3520 3521 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3522 !LINK_ACTIVE(ctx))) { 3523 DBG_COUNTER_INC(txq_drain_notready); 3524 return (0); 3525 } 3526 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3527 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3528 avail = IDXDIFF(pidx, cidx, r->size); 3529 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3530 DBG_COUNTER_INC(txq_drain_flushing); 3531 for (i = 0; i < avail; i++) { 3532 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3533 m_free(r->items[(cidx + i) & (r->size-1)]); 3534 r->items[(cidx + i) & (r->size-1)] = NULL; 3535 } 3536 return (avail); 3537 } 3538 3539 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3540 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3541 CALLOUT_LOCK(txq); 3542 callout_stop(&txq->ift_timer); 3543 CALLOUT_UNLOCK(txq); 3544 DBG_COUNTER_INC(txq_drain_oactive); 3545 return (0); 3546 } 3547 if (reclaimed) 3548 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3549 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3550 count = MIN(avail, TX_BATCH_SIZE); 3551 #ifdef INVARIANTS 3552 if (iflib_verbose_debug) 3553 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3554 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3555 #endif 3556 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3557 avail = TXQ_AVAIL(txq); 3558 err = 0; 3559 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3560 int rem = do_prefetch ? count - i : 0; 3561 3562 mp = _ring_peek_one(r, cidx, i, rem); 3563 MPASS(mp != NULL && *mp != NULL); 3564 if (__predict_false(*mp == (struct mbuf *)txq)) { 3565 consumed++; 3566 reclaimed++; 3567 continue; 3568 } 3569 in_use_prev = txq->ift_in_use; 3570 err = iflib_encap(txq, mp); 3571 if (__predict_false(err)) { 3572 /* no room - bail out */ 3573 if (err == ENOBUFS) 3574 break; 3575 consumed++; 3576 /* we can't send this packet - skip it */ 3577 continue; 3578 } 3579 consumed++; 3580 pkt_sent++; 3581 m = *mp; 3582 DBG_COUNTER_INC(tx_sent); 3583 bytes_sent += m->m_pkthdr.len; 3584 mcast_sent += !!(m->m_flags & M_MCAST); 3585 avail = TXQ_AVAIL(txq); 3586 3587 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3588 desc_used += (txq->ift_in_use - in_use_prev); 3589 ETHER_BPF_MTAP(ifp, m); 3590 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3591 break; 3592 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3593 } 3594 3595 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3596 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3597 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3598 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3599 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3600 if (mcast_sent) 3601 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3602 #ifdef INVARIANTS 3603 if (iflib_verbose_debug) 3604 printf("consumed=%d\n", consumed); 3605 #endif 3606 return (consumed); 3607 } 3608 3609 static uint32_t 3610 iflib_txq_drain_always(struct ifmp_ring *r) 3611 { 3612 return (1); 3613 } 3614 3615 static uint32_t 3616 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3617 { 3618 int i, avail; 3619 struct mbuf **mp; 3620 iflib_txq_t txq; 3621 3622 txq = r->cookie; 3623 3624 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3625 CALLOUT_LOCK(txq); 3626 callout_stop(&txq->ift_timer); 3627 CALLOUT_UNLOCK(txq); 3628 3629 avail = IDXDIFF(pidx, cidx, r->size); 3630 for (i = 0; i < avail; i++) { 3631 mp = _ring_peek_one(r, cidx, i, avail - i); 3632 if (__predict_false(*mp == (struct mbuf *)txq)) 3633 continue; 3634 m_freem(*mp); 3635 DBG_COUNTER_INC(tx_frees); 3636 } 3637 MPASS(ifmp_ring_is_stalled(r) == 0); 3638 return (avail); 3639 } 3640 3641 static void 3642 iflib_ifmp_purge(iflib_txq_t txq) 3643 { 3644 struct ifmp_ring *r; 3645 3646 r = txq->ift_br; 3647 r->drain = iflib_txq_drain_free; 3648 r->can_drain = iflib_txq_drain_always; 3649 3650 ifmp_ring_check_drainage(r, r->size); 3651 3652 r->drain = iflib_txq_drain; 3653 r->can_drain = iflib_txq_can_drain; 3654 } 3655 3656 static void 3657 _task_fn_tx(void *context) 3658 { 3659 iflib_txq_t txq = context; 3660 if_ctx_t ctx = txq->ift_ctx; 3661 #if defined(ALTQ) || defined(DEV_NETMAP) 3662 if_t ifp = ctx->ifc_ifp; 3663 #endif 3664 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3665 3666 #ifdef IFLIB_DIAGNOSTICS 3667 txq->ift_cpu_exec_count[curcpu]++; 3668 #endif 3669 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3670 return; 3671 #ifdef DEV_NETMAP 3672 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3673 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3674 BUS_DMASYNC_POSTREAD); 3675 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3676 netmap_tx_irq(ifp, txq->ift_id); 3677 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3678 return; 3679 } 3680 #endif 3681 #ifdef ALTQ 3682 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3683 iflib_altq_if_start(ifp); 3684 #endif 3685 if (txq->ift_db_pending) 3686 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3687 else if (!abdicate) 3688 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3689 /* 3690 * When abdicating, we always need to check drainage, not just when we don't enqueue 3691 */ 3692 if (abdicate) 3693 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3694 if (ctx->ifc_flags & IFC_LEGACY) 3695 IFDI_INTR_ENABLE(ctx); 3696 else { 3697 #ifdef INVARIANTS 3698 int rc = 3699 #endif 3700 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3701 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3702 } 3703 } 3704 3705 static void 3706 _task_fn_rx(void *context) 3707 { 3708 iflib_rxq_t rxq = context; 3709 if_ctx_t ctx = rxq->ifr_ctx; 3710 bool more; 3711 uint16_t budget; 3712 3713 #ifdef IFLIB_DIAGNOSTICS 3714 rxq->ifr_cpu_exec_count[curcpu]++; 3715 #endif 3716 DBG_COUNTER_INC(task_fn_rxs); 3717 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3718 return; 3719 more = true; 3720 #ifdef DEV_NETMAP 3721 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3722 u_int work = 0; 3723 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3724 more = false; 3725 } 3726 } 3727 #endif 3728 budget = ctx->ifc_sysctl_rx_budget; 3729 if (budget == 0) 3730 budget = 16; /* XXX */ 3731 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3732 if (ctx->ifc_flags & IFC_LEGACY) 3733 IFDI_INTR_ENABLE(ctx); 3734 else { 3735 #ifdef INVARIANTS 3736 int rc = 3737 #endif 3738 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3739 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3740 DBG_COUNTER_INC(rx_intr_enables); 3741 } 3742 } 3743 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3744 return; 3745 if (more) 3746 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3747 } 3748 3749 static void 3750 _task_fn_admin(void *context) 3751 { 3752 if_ctx_t ctx = context; 3753 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3754 iflib_txq_t txq; 3755 int i; 3756 bool oactive, running, do_reset, do_watchdog, in_detach; 3757 uint32_t reset_on = hz / 2; 3758 3759 STATE_LOCK(ctx); 3760 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3761 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3762 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3763 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3764 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3765 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3766 STATE_UNLOCK(ctx); 3767 3768 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3769 return; 3770 if (in_detach) 3771 return; 3772 3773 CTX_LOCK(ctx); 3774 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3775 CALLOUT_LOCK(txq); 3776 callout_stop(&txq->ift_timer); 3777 CALLOUT_UNLOCK(txq); 3778 } 3779 if (do_watchdog) { 3780 ctx->ifc_watchdog_events++; 3781 IFDI_WATCHDOG_RESET(ctx); 3782 } 3783 IFDI_UPDATE_ADMIN_STATUS(ctx); 3784 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3785 #ifdef DEV_NETMAP 3786 reset_on = hz / 2; 3787 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3788 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 3789 #endif 3790 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3791 } 3792 IFDI_LINK_INTR_ENABLE(ctx); 3793 if (do_reset) 3794 iflib_if_init_locked(ctx); 3795 CTX_UNLOCK(ctx); 3796 3797 if (LINK_ACTIVE(ctx) == 0) 3798 return; 3799 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3800 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3801 } 3802 3803 3804 static void 3805 _task_fn_iov(void *context) 3806 { 3807 if_ctx_t ctx = context; 3808 3809 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3810 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3811 return; 3812 3813 CTX_LOCK(ctx); 3814 IFDI_VFLR_HANDLE(ctx); 3815 CTX_UNLOCK(ctx); 3816 } 3817 3818 static int 3819 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3820 { 3821 int err; 3822 if_int_delay_info_t info; 3823 if_ctx_t ctx; 3824 3825 info = (if_int_delay_info_t)arg1; 3826 ctx = info->iidi_ctx; 3827 info->iidi_req = req; 3828 info->iidi_oidp = oidp; 3829 CTX_LOCK(ctx); 3830 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3831 CTX_UNLOCK(ctx); 3832 return (err); 3833 } 3834 3835 /********************************************************************* 3836 * 3837 * IFNET FUNCTIONS 3838 * 3839 **********************************************************************/ 3840 3841 static void 3842 iflib_if_init_locked(if_ctx_t ctx) 3843 { 3844 iflib_stop(ctx); 3845 iflib_init_locked(ctx); 3846 } 3847 3848 3849 static void 3850 iflib_if_init(void *arg) 3851 { 3852 if_ctx_t ctx = arg; 3853 3854 CTX_LOCK(ctx); 3855 iflib_if_init_locked(ctx); 3856 CTX_UNLOCK(ctx); 3857 } 3858 3859 static int 3860 iflib_if_transmit(if_t ifp, struct mbuf *m) 3861 { 3862 if_ctx_t ctx = if_getsoftc(ifp); 3863 3864 iflib_txq_t txq; 3865 int err, qidx; 3866 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3867 3868 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3869 DBG_COUNTER_INC(tx_frees); 3870 m_freem(m); 3871 return (ENOBUFS); 3872 } 3873 3874 MPASS(m->m_nextpkt == NULL); 3875 /* ALTQ-enabled interfaces always use queue 0. */ 3876 qidx = 0; 3877 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3878 qidx = QIDX(ctx, m); 3879 /* 3880 * XXX calculate buf_ring based on flowid (divvy up bits?) 3881 */ 3882 txq = &ctx->ifc_txqs[qidx]; 3883 3884 #ifdef DRIVER_BACKPRESSURE 3885 if (txq->ift_closed) { 3886 while (m != NULL) { 3887 next = m->m_nextpkt; 3888 m->m_nextpkt = NULL; 3889 m_freem(m); 3890 DBG_COUNTER_INC(tx_frees); 3891 m = next; 3892 } 3893 return (ENOBUFS); 3894 } 3895 #endif 3896 #ifdef notyet 3897 qidx = count = 0; 3898 mp = marr; 3899 next = m; 3900 do { 3901 count++; 3902 next = next->m_nextpkt; 3903 } while (next != NULL); 3904 3905 if (count > nitems(marr)) 3906 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3907 /* XXX check nextpkt */ 3908 m_freem(m); 3909 /* XXX simplify for now */ 3910 DBG_COUNTER_INC(tx_frees); 3911 return (ENOBUFS); 3912 } 3913 for (next = m, i = 0; next != NULL; i++) { 3914 mp[i] = next; 3915 next = next->m_nextpkt; 3916 mp[i]->m_nextpkt = NULL; 3917 } 3918 #endif 3919 DBG_COUNTER_INC(tx_seen); 3920 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 3921 3922 if (abdicate) 3923 GROUPTASK_ENQUEUE(&txq->ift_task); 3924 if (err) { 3925 if (!abdicate) 3926 GROUPTASK_ENQUEUE(&txq->ift_task); 3927 /* support forthcoming later */ 3928 #ifdef DRIVER_BACKPRESSURE 3929 txq->ift_closed = TRUE; 3930 #endif 3931 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3932 m_freem(m); 3933 DBG_COUNTER_INC(tx_frees); 3934 } 3935 3936 return (err); 3937 } 3938 3939 #ifdef ALTQ 3940 /* 3941 * The overall approach to integrating iflib with ALTQ is to continue to use 3942 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 3943 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 3944 * is redundant/unnecessary, but doing so minimizes the amount of 3945 * ALTQ-specific code required in iflib. It is assumed that the overhead of 3946 * redundantly queueing to an intermediate mp_ring is swamped by the 3947 * performance limitations inherent in using ALTQ. 3948 * 3949 * When ALTQ support is compiled in, all iflib drivers will use a transmit 3950 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 3951 * given interface. If ALTQ is enabled for an interface, then all 3952 * transmitted packets for that interface will be submitted to the ALTQ 3953 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 3954 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 3955 * update stats that the iflib machinery handles, and which is sensitve to 3956 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 3957 * will be installed as the start routine for use by ALTQ facilities that 3958 * need to trigger queue drains on a scheduled basis. 3959 * 3960 */ 3961 static void 3962 iflib_altq_if_start(if_t ifp) 3963 { 3964 struct ifaltq *ifq = &ifp->if_snd; 3965 struct mbuf *m; 3966 3967 IFQ_LOCK(ifq); 3968 IFQ_DEQUEUE_NOLOCK(ifq, m); 3969 while (m != NULL) { 3970 iflib_if_transmit(ifp, m); 3971 IFQ_DEQUEUE_NOLOCK(ifq, m); 3972 } 3973 IFQ_UNLOCK(ifq); 3974 } 3975 3976 static int 3977 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 3978 { 3979 int err; 3980 3981 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 3982 IFQ_ENQUEUE(&ifp->if_snd, m, err); 3983 if (err == 0) 3984 iflib_altq_if_start(ifp); 3985 } else 3986 err = iflib_if_transmit(ifp, m); 3987 3988 return (err); 3989 } 3990 #endif /* ALTQ */ 3991 3992 static void 3993 iflib_if_qflush(if_t ifp) 3994 { 3995 if_ctx_t ctx = if_getsoftc(ifp); 3996 iflib_txq_t txq = ctx->ifc_txqs; 3997 int i; 3998 3999 STATE_LOCK(ctx); 4000 ctx->ifc_flags |= IFC_QFLUSH; 4001 STATE_UNLOCK(ctx); 4002 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4003 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4004 iflib_txq_check_drain(txq, 0); 4005 STATE_LOCK(ctx); 4006 ctx->ifc_flags &= ~IFC_QFLUSH; 4007 STATE_UNLOCK(ctx); 4008 4009 /* 4010 * When ALTQ is enabled, this will also take care of purging the 4011 * ALTQ queue(s). 4012 */ 4013 if_qflush(ifp); 4014 } 4015 4016 4017 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4018 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4019 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4020 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM) 4021 4022 static int 4023 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4024 { 4025 if_ctx_t ctx = if_getsoftc(ifp); 4026 struct ifreq *ifr = (struct ifreq *)data; 4027 #if defined(INET) || defined(INET6) 4028 struct ifaddr *ifa = (struct ifaddr *)data; 4029 #endif 4030 bool avoid_reset = FALSE; 4031 int err = 0, reinit = 0, bits; 4032 4033 switch (command) { 4034 case SIOCSIFADDR: 4035 #ifdef INET 4036 if (ifa->ifa_addr->sa_family == AF_INET) 4037 avoid_reset = TRUE; 4038 #endif 4039 #ifdef INET6 4040 if (ifa->ifa_addr->sa_family == AF_INET6) 4041 avoid_reset = TRUE; 4042 #endif 4043 /* 4044 ** Calling init results in link renegotiation, 4045 ** so we avoid doing it when possible. 4046 */ 4047 if (avoid_reset) { 4048 if_setflagbits(ifp, IFF_UP,0); 4049 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4050 reinit = 1; 4051 #ifdef INET 4052 if (!(if_getflags(ifp) & IFF_NOARP)) 4053 arp_ifinit(ifp, ifa); 4054 #endif 4055 } else 4056 err = ether_ioctl(ifp, command, data); 4057 break; 4058 case SIOCSIFMTU: 4059 CTX_LOCK(ctx); 4060 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4061 CTX_UNLOCK(ctx); 4062 break; 4063 } 4064 bits = if_getdrvflags(ifp); 4065 /* stop the driver and free any clusters before proceeding */ 4066 iflib_stop(ctx); 4067 4068 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4069 STATE_LOCK(ctx); 4070 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4071 ctx->ifc_flags |= IFC_MULTISEG; 4072 else 4073 ctx->ifc_flags &= ~IFC_MULTISEG; 4074 STATE_UNLOCK(ctx); 4075 err = if_setmtu(ifp, ifr->ifr_mtu); 4076 } 4077 iflib_init_locked(ctx); 4078 STATE_LOCK(ctx); 4079 if_setdrvflags(ifp, bits); 4080 STATE_UNLOCK(ctx); 4081 CTX_UNLOCK(ctx); 4082 break; 4083 case SIOCSIFFLAGS: 4084 CTX_LOCK(ctx); 4085 if (if_getflags(ifp) & IFF_UP) { 4086 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4087 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4088 (IFF_PROMISC | IFF_ALLMULTI)) { 4089 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4090 } 4091 } else 4092 reinit = 1; 4093 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4094 iflib_stop(ctx); 4095 } 4096 ctx->ifc_if_flags = if_getflags(ifp); 4097 CTX_UNLOCK(ctx); 4098 break; 4099 case SIOCADDMULTI: 4100 case SIOCDELMULTI: 4101 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4102 CTX_LOCK(ctx); 4103 IFDI_INTR_DISABLE(ctx); 4104 IFDI_MULTI_SET(ctx); 4105 IFDI_INTR_ENABLE(ctx); 4106 CTX_UNLOCK(ctx); 4107 } 4108 break; 4109 case SIOCSIFMEDIA: 4110 CTX_LOCK(ctx); 4111 IFDI_MEDIA_SET(ctx); 4112 CTX_UNLOCK(ctx); 4113 /* falls thru */ 4114 case SIOCGIFMEDIA: 4115 case SIOCGIFXMEDIA: 4116 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 4117 break; 4118 case SIOCGI2C: 4119 { 4120 struct ifi2creq i2c; 4121 4122 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4123 if (err != 0) 4124 break; 4125 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4126 err = EINVAL; 4127 break; 4128 } 4129 if (i2c.len > sizeof(i2c.data)) { 4130 err = EINVAL; 4131 break; 4132 } 4133 4134 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4135 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4136 sizeof(i2c)); 4137 break; 4138 } 4139 case SIOCSIFCAP: 4140 { 4141 int mask, setmask, oldmask; 4142 4143 oldmask = if_getcapenable(ifp); 4144 mask = ifr->ifr_reqcap ^ oldmask; 4145 mask &= ctx->ifc_softc_ctx.isc_capabilities; 4146 setmask = 0; 4147 #ifdef TCP_OFFLOAD 4148 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4149 #endif 4150 setmask |= (mask & IFCAP_FLAGS); 4151 setmask |= (mask & IFCAP_WOL); 4152 4153 /* 4154 * If any RX csum has changed, change all the ones that 4155 * are supported by the driver. 4156 */ 4157 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4158 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4159 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4160 } 4161 4162 /* 4163 * want to ensure that traffic has stopped before we change any of the flags 4164 */ 4165 if (setmask) { 4166 CTX_LOCK(ctx); 4167 bits = if_getdrvflags(ifp); 4168 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4169 iflib_stop(ctx); 4170 STATE_LOCK(ctx); 4171 if_togglecapenable(ifp, setmask); 4172 STATE_UNLOCK(ctx); 4173 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4174 iflib_init_locked(ctx); 4175 STATE_LOCK(ctx); 4176 if_setdrvflags(ifp, bits); 4177 STATE_UNLOCK(ctx); 4178 CTX_UNLOCK(ctx); 4179 } 4180 if_vlancap(ifp); 4181 break; 4182 } 4183 case SIOCGPRIVATE_0: 4184 case SIOCSDRVSPEC: 4185 case SIOCGDRVSPEC: 4186 CTX_LOCK(ctx); 4187 err = IFDI_PRIV_IOCTL(ctx, command, data); 4188 CTX_UNLOCK(ctx); 4189 break; 4190 default: 4191 err = ether_ioctl(ifp, command, data); 4192 break; 4193 } 4194 if (reinit) 4195 iflib_if_init(ctx); 4196 return (err); 4197 } 4198 4199 static uint64_t 4200 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4201 { 4202 if_ctx_t ctx = if_getsoftc(ifp); 4203 4204 return (IFDI_GET_COUNTER(ctx, cnt)); 4205 } 4206 4207 /********************************************************************* 4208 * 4209 * OTHER FUNCTIONS EXPORTED TO THE STACK 4210 * 4211 **********************************************************************/ 4212 4213 static void 4214 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4215 { 4216 if_ctx_t ctx = if_getsoftc(ifp); 4217 4218 if ((void *)ctx != arg) 4219 return; 4220 4221 if ((vtag == 0) || (vtag > 4095)) 4222 return; 4223 4224 CTX_LOCK(ctx); 4225 IFDI_VLAN_REGISTER(ctx, vtag); 4226 /* Re-init to load the changes */ 4227 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4228 iflib_if_init_locked(ctx); 4229 CTX_UNLOCK(ctx); 4230 } 4231 4232 static void 4233 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4234 { 4235 if_ctx_t ctx = if_getsoftc(ifp); 4236 4237 if ((void *)ctx != arg) 4238 return; 4239 4240 if ((vtag == 0) || (vtag > 4095)) 4241 return; 4242 4243 CTX_LOCK(ctx); 4244 IFDI_VLAN_UNREGISTER(ctx, vtag); 4245 /* Re-init to load the changes */ 4246 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4247 iflib_if_init_locked(ctx); 4248 CTX_UNLOCK(ctx); 4249 } 4250 4251 static void 4252 iflib_led_func(void *arg, int onoff) 4253 { 4254 if_ctx_t ctx = arg; 4255 4256 CTX_LOCK(ctx); 4257 IFDI_LED_FUNC(ctx, onoff); 4258 CTX_UNLOCK(ctx); 4259 } 4260 4261 /********************************************************************* 4262 * 4263 * BUS FUNCTION DEFINITIONS 4264 * 4265 **********************************************************************/ 4266 4267 int 4268 iflib_device_probe(device_t dev) 4269 { 4270 pci_vendor_info_t *ent; 4271 4272 uint16_t pci_vendor_id, pci_device_id; 4273 uint16_t pci_subvendor_id, pci_subdevice_id; 4274 uint16_t pci_rev_id; 4275 if_shared_ctx_t sctx; 4276 4277 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4278 return (ENOTSUP); 4279 4280 pci_vendor_id = pci_get_vendor(dev); 4281 pci_device_id = pci_get_device(dev); 4282 pci_subvendor_id = pci_get_subvendor(dev); 4283 pci_subdevice_id = pci_get_subdevice(dev); 4284 pci_rev_id = pci_get_revid(dev); 4285 if (sctx->isc_parse_devinfo != NULL) 4286 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4287 4288 ent = sctx->isc_vendor_info; 4289 while (ent->pvi_vendor_id != 0) { 4290 if (pci_vendor_id != ent->pvi_vendor_id) { 4291 ent++; 4292 continue; 4293 } 4294 if ((pci_device_id == ent->pvi_device_id) && 4295 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4296 (ent->pvi_subvendor_id == 0)) && 4297 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4298 (ent->pvi_subdevice_id == 0)) && 4299 ((pci_rev_id == ent->pvi_rev_id) || 4300 (ent->pvi_rev_id == 0))) { 4301 4302 device_set_desc_copy(dev, ent->pvi_name); 4303 /* this needs to be changed to zero if the bus probing code 4304 * ever stops re-probing on best match because the sctx 4305 * may have its values over written by register calls 4306 * in subsequent probes 4307 */ 4308 return (BUS_PROBE_DEFAULT); 4309 } 4310 ent++; 4311 } 4312 return (ENXIO); 4313 } 4314 4315 static void 4316 iflib_reset_qvalues(if_ctx_t ctx) 4317 { 4318 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4319 if_shared_ctx_t sctx = ctx->ifc_sctx; 4320 device_t dev = ctx->ifc_dev; 4321 int i; 4322 4323 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES; 4324 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH; 4325 /* 4326 * XXX sanity check that ntxd & nrxd are a power of 2 4327 */ 4328 if (ctx->ifc_sysctl_ntxqs != 0) 4329 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4330 if (ctx->ifc_sysctl_nrxqs != 0) 4331 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4332 4333 for (i = 0; i < sctx->isc_ntxqs; i++) { 4334 if (ctx->ifc_sysctl_ntxds[i] != 0) 4335 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4336 else 4337 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4338 } 4339 4340 for (i = 0; i < sctx->isc_nrxqs; i++) { 4341 if (ctx->ifc_sysctl_nrxds[i] != 0) 4342 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4343 else 4344 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4345 } 4346 4347 for (i = 0; i < sctx->isc_nrxqs; i++) { 4348 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4349 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4350 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4351 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4352 } 4353 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4354 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4355 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4356 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4357 } 4358 } 4359 4360 for (i = 0; i < sctx->isc_ntxqs; i++) { 4361 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4362 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4363 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4364 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4365 } 4366 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4367 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4368 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4369 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4370 } 4371 } 4372 } 4373 4374 int 4375 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4376 { 4377 int err, rid, msix; 4378 if_ctx_t ctx; 4379 if_t ifp; 4380 if_softc_ctx_t scctx; 4381 int i; 4382 uint16_t main_txq; 4383 uint16_t main_rxq; 4384 4385 4386 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4387 4388 if (sc == NULL) { 4389 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4390 device_set_softc(dev, ctx); 4391 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4392 } 4393 4394 ctx->ifc_sctx = sctx; 4395 ctx->ifc_dev = dev; 4396 ctx->ifc_softc = sc; 4397 4398 if ((err = iflib_register(ctx)) != 0) { 4399 device_printf(dev, "iflib_register failed %d\n", err); 4400 goto fail_ctx_free; 4401 } 4402 iflib_add_device_sysctl_pre(ctx); 4403 4404 scctx = &ctx->ifc_softc_ctx; 4405 ifp = ctx->ifc_ifp; 4406 4407 iflib_reset_qvalues(ctx); 4408 CTX_LOCK(ctx); 4409 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4410 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4411 goto fail_unlock; 4412 } 4413 _iflib_pre_assert(scctx); 4414 ctx->ifc_txrx = *scctx->isc_txrx; 4415 4416 #ifdef INVARIANTS 4417 MPASS(scctx->isc_capabilities); 4418 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4419 MPASS(scctx->isc_tx_csum_flags); 4420 #endif 4421 4422 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS); 4423 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4424 4425 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4426 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4427 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4428 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4429 4430 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4431 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4432 4433 /* XXX change for per-queue sizes */ 4434 device_printf(dev, "Using %d tx descriptors and %d rx descriptors\n", 4435 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4436 for (i = 0; i < sctx->isc_nrxqs; i++) { 4437 if (!powerof2(scctx->isc_nrxd[i])) { 4438 /* round down instead? */ 4439 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4440 err = EINVAL; 4441 goto fail_iflib_detach; 4442 } 4443 } 4444 for (i = 0; i < sctx->isc_ntxqs; i++) { 4445 if (!powerof2(scctx->isc_ntxd[i])) { 4446 device_printf(dev, 4447 "# tx descriptors must be a power of 2"); 4448 err = EINVAL; 4449 goto fail_iflib_detach; 4450 } 4451 } 4452 4453 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4454 MAX_SINGLE_PACKET_FRACTION) 4455 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4456 MAX_SINGLE_PACKET_FRACTION); 4457 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4458 MAX_SINGLE_PACKET_FRACTION) 4459 scctx->isc_tx_tso_segments_max = max(1, 4460 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4461 4462 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4463 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4464 /* 4465 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4466 * but some MACs do. 4467 */ 4468 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4469 IP_MAXPACKET)); 4470 /* 4471 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4472 * into account. In the worst case, each of these calls will 4473 * add another mbuf and, thus, the requirement for another DMA 4474 * segment. So for best performance, it doesn't make sense to 4475 * advertize a maximum of TSO segments that typically will 4476 * require defragmentation in iflib_encap(). 4477 */ 4478 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4479 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4480 } 4481 if (scctx->isc_rss_table_size == 0) 4482 scctx->isc_rss_table_size = 64; 4483 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4484 4485 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4486 /* XXX format name */ 4487 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4488 NULL, NULL, "admin"); 4489 4490 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4491 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4492 device_printf(dev, "Unable to fetch CPU list\n"); 4493 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4494 } 4495 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4496 4497 /* 4498 ** Now set up MSI or MSI-X, should return us the number of supported 4499 ** vectors (will be 1 for a legacy interrupt and MSI). 4500 */ 4501 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4502 msix = scctx->isc_vectors; 4503 } else if (scctx->isc_msix_bar != 0) 4504 /* 4505 * The simple fact that isc_msix_bar is not 0 does not mean we 4506 * we have a good value there that is known to work. 4507 */ 4508 msix = iflib_msix_init(ctx); 4509 else { 4510 scctx->isc_vectors = 1; 4511 scctx->isc_ntxqsets = 1; 4512 scctx->isc_nrxqsets = 1; 4513 scctx->isc_intr = IFLIB_INTR_LEGACY; 4514 msix = 0; 4515 } 4516 /* Get memory for the station queues */ 4517 if ((err = iflib_queues_alloc(ctx))) { 4518 device_printf(dev, "Unable to allocate queue memory\n"); 4519 goto fail_intr_free; 4520 } 4521 4522 if ((err = iflib_qset_structures_setup(ctx))) 4523 goto fail_queues; 4524 4525 /* 4526 * Group taskqueues aren't properly set up until SMP is started, 4527 * so we disable interrupts until we can handle them post 4528 * SI_SUB_SMP. 4529 * 4530 * XXX: disabling interrupts doesn't actually work, at least for 4531 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4532 * we do null handling and depend on this not causing too large an 4533 * interrupt storm. 4534 */ 4535 IFDI_INTR_DISABLE(ctx); 4536 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4537 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4538 goto fail_queues; 4539 } 4540 if (msix <= 1) { 4541 rid = 0; 4542 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4543 MPASS(msix == 1); 4544 rid = 1; 4545 } 4546 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4547 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4548 goto fail_queues; 4549 } 4550 } 4551 4552 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4553 4554 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4555 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4556 goto fail_detach; 4557 } 4558 4559 /* 4560 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4561 * This must appear after the call to ether_ifattach() because 4562 * ether_ifattach() sets if_hdrlen to the default value. 4563 */ 4564 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4565 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4566 4567 if ((err = iflib_netmap_attach(ctx))) { 4568 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4569 goto fail_detach; 4570 } 4571 *ctxp = ctx; 4572 4573 NETDUMP_SET(ctx->ifc_ifp, iflib); 4574 4575 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4576 iflib_add_device_sysctl_post(ctx); 4577 ctx->ifc_flags |= IFC_INIT_DONE; 4578 CTX_UNLOCK(ctx); 4579 return (0); 4580 4581 fail_detach: 4582 ether_ifdetach(ctx->ifc_ifp); 4583 fail_intr_free: 4584 iflib_free_intr_mem(ctx); 4585 fail_queues: 4586 iflib_tx_structures_free(ctx); 4587 iflib_rx_structures_free(ctx); 4588 fail_iflib_detach: 4589 IFDI_DETACH(ctx); 4590 fail_unlock: 4591 CTX_UNLOCK(ctx); 4592 fail_ctx_free: 4593 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4594 free(ctx->ifc_softc, M_IFLIB); 4595 free(ctx, M_IFLIB); 4596 return (err); 4597 } 4598 4599 int 4600 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4601 struct iflib_cloneattach_ctx *clctx) 4602 { 4603 int err; 4604 if_ctx_t ctx; 4605 if_t ifp; 4606 if_softc_ctx_t scctx; 4607 int i; 4608 void *sc; 4609 uint16_t main_txq; 4610 uint16_t main_rxq; 4611 4612 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4613 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4614 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4615 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4616 ctx->ifc_flags |= IFC_PSEUDO; 4617 4618 ctx->ifc_sctx = sctx; 4619 ctx->ifc_softc = sc; 4620 ctx->ifc_dev = dev; 4621 4622 if ((err = iflib_register(ctx)) != 0) { 4623 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4624 goto fail_ctx_free; 4625 } 4626 iflib_add_device_sysctl_pre(ctx); 4627 4628 scctx = &ctx->ifc_softc_ctx; 4629 ifp = ctx->ifc_ifp; 4630 4631 /* 4632 * XXX sanity check that ntxd & nrxd are a power of 2 4633 */ 4634 iflib_reset_qvalues(ctx); 4635 4636 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4637 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4638 goto fail_ctx_free; 4639 } 4640 if (sctx->isc_flags & IFLIB_GEN_MAC) 4641 iflib_gen_mac(ctx); 4642 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4643 clctx->cc_params)) != 0) { 4644 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4645 goto fail_ctx_free; 4646 } 4647 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4648 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 4649 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO); 4650 4651 #ifdef INVARIANTS 4652 MPASS(scctx->isc_capabilities); 4653 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4654 MPASS(scctx->isc_tx_csum_flags); 4655 #endif 4656 4657 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4658 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4659 4660 ifp->if_flags |= IFF_NOGROUP; 4661 if (sctx->isc_flags & IFLIB_PSEUDO) { 4662 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4663 4664 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4665 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4666 goto fail_detach; 4667 } 4668 *ctxp = ctx; 4669 4670 /* 4671 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4672 * This must appear after the call to ether_ifattach() because 4673 * ether_ifattach() sets if_hdrlen to the default value. 4674 */ 4675 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4676 if_setifheaderlen(ifp, 4677 sizeof(struct ether_vlan_header)); 4678 4679 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4680 iflib_add_device_sysctl_post(ctx); 4681 ctx->ifc_flags |= IFC_INIT_DONE; 4682 return (0); 4683 } 4684 _iflib_pre_assert(scctx); 4685 ctx->ifc_txrx = *scctx->isc_txrx; 4686 4687 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4688 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4689 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4690 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4691 4692 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4693 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4694 4695 /* XXX change for per-queue sizes */ 4696 device_printf(dev, "Using %d tx descriptors and %d rx descriptors\n", 4697 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4698 for (i = 0; i < sctx->isc_nrxqs; i++) { 4699 if (!powerof2(scctx->isc_nrxd[i])) { 4700 /* round down instead? */ 4701 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4702 err = EINVAL; 4703 goto fail_iflib_detach; 4704 } 4705 } 4706 for (i = 0; i < sctx->isc_ntxqs; i++) { 4707 if (!powerof2(scctx->isc_ntxd[i])) { 4708 device_printf(dev, 4709 "# tx descriptors must be a power of 2"); 4710 err = EINVAL; 4711 goto fail_iflib_detach; 4712 } 4713 } 4714 4715 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4716 MAX_SINGLE_PACKET_FRACTION) 4717 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4718 MAX_SINGLE_PACKET_FRACTION); 4719 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4720 MAX_SINGLE_PACKET_FRACTION) 4721 scctx->isc_tx_tso_segments_max = max(1, 4722 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4723 4724 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4725 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4726 /* 4727 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4728 * but some MACs do. 4729 */ 4730 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4731 IP_MAXPACKET)); 4732 /* 4733 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4734 * into account. In the worst case, each of these calls will 4735 * add another mbuf and, thus, the requirement for another DMA 4736 * segment. So for best performance, it doesn't make sense to 4737 * advertize a maximum of TSO segments that typically will 4738 * require defragmentation in iflib_encap(). 4739 */ 4740 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4741 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4742 } 4743 if (scctx->isc_rss_table_size == 0) 4744 scctx->isc_rss_table_size = 64; 4745 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4746 4747 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4748 /* XXX format name */ 4749 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4750 NULL, NULL, "admin"); 4751 4752 /* XXX --- can support > 1 -- but keep it simple for now */ 4753 scctx->isc_intr = IFLIB_INTR_LEGACY; 4754 4755 /* Get memory for the station queues */ 4756 if ((err = iflib_queues_alloc(ctx))) { 4757 device_printf(dev, "Unable to allocate queue memory\n"); 4758 goto fail_iflib_detach; 4759 } 4760 4761 if ((err = iflib_qset_structures_setup(ctx))) { 4762 device_printf(dev, "qset structure setup failed %d\n", err); 4763 goto fail_queues; 4764 } 4765 4766 /* 4767 * XXX What if anything do we want to do about interrupts? 4768 */ 4769 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4770 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4771 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4772 goto fail_detach; 4773 } 4774 4775 /* 4776 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4777 * This must appear after the call to ether_ifattach() because 4778 * ether_ifattach() sets if_hdrlen to the default value. 4779 */ 4780 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4781 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4782 4783 /* XXX handle more than one queue */ 4784 for (i = 0; i < scctx->isc_nrxqsets; i++) 4785 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4786 4787 *ctxp = ctx; 4788 4789 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4790 iflib_add_device_sysctl_post(ctx); 4791 ctx->ifc_flags |= IFC_INIT_DONE; 4792 return (0); 4793 fail_detach: 4794 ether_ifdetach(ctx->ifc_ifp); 4795 fail_queues: 4796 iflib_tx_structures_free(ctx); 4797 iflib_rx_structures_free(ctx); 4798 fail_iflib_detach: 4799 IFDI_DETACH(ctx); 4800 fail_ctx_free: 4801 free(ctx->ifc_softc, M_IFLIB); 4802 free(ctx, M_IFLIB); 4803 return (err); 4804 } 4805 4806 int 4807 iflib_pseudo_deregister(if_ctx_t ctx) 4808 { 4809 if_t ifp = ctx->ifc_ifp; 4810 iflib_txq_t txq; 4811 iflib_rxq_t rxq; 4812 int i, j; 4813 struct taskqgroup *tqg; 4814 iflib_fl_t fl; 4815 4816 /* Unregister VLAN events */ 4817 if (ctx->ifc_vlan_attach_event != NULL) 4818 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4819 if (ctx->ifc_vlan_detach_event != NULL) 4820 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4821 4822 ether_ifdetach(ifp); 4823 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4824 CTX_LOCK_DESTROY(ctx); 4825 /* XXX drain any dependent tasks */ 4826 tqg = qgroup_if_io_tqg; 4827 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4828 callout_drain(&txq->ift_timer); 4829 if (txq->ift_task.gt_uniq != NULL) 4830 taskqgroup_detach(tqg, &txq->ift_task); 4831 } 4832 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4833 if (rxq->ifr_task.gt_uniq != NULL) 4834 taskqgroup_detach(tqg, &rxq->ifr_task); 4835 4836 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4837 free(fl->ifl_rx_bitmap, M_IFLIB); 4838 } 4839 tqg = qgroup_if_config_tqg; 4840 if (ctx->ifc_admin_task.gt_uniq != NULL) 4841 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4842 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4843 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4844 4845 if_free(ifp); 4846 4847 iflib_tx_structures_free(ctx); 4848 iflib_rx_structures_free(ctx); 4849 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4850 free(ctx->ifc_softc, M_IFLIB); 4851 free(ctx, M_IFLIB); 4852 return (0); 4853 } 4854 4855 int 4856 iflib_device_attach(device_t dev) 4857 { 4858 if_ctx_t ctx; 4859 if_shared_ctx_t sctx; 4860 4861 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4862 return (ENOTSUP); 4863 4864 pci_enable_busmaster(dev); 4865 4866 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4867 } 4868 4869 int 4870 iflib_device_deregister(if_ctx_t ctx) 4871 { 4872 if_t ifp = ctx->ifc_ifp; 4873 iflib_txq_t txq; 4874 iflib_rxq_t rxq; 4875 device_t dev = ctx->ifc_dev; 4876 int i, j; 4877 struct taskqgroup *tqg; 4878 iflib_fl_t fl; 4879 4880 /* Make sure VLANS are not using driver */ 4881 if (if_vlantrunkinuse(ifp)) { 4882 device_printf(dev, "Vlan in use, detach first\n"); 4883 return (EBUSY); 4884 } 4885 #ifdef PCI_IOV 4886 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 4887 device_printf(dev, "SR-IOV in use; detach first.\n"); 4888 return (EBUSY); 4889 } 4890 #endif 4891 4892 STATE_LOCK(ctx); 4893 ctx->ifc_flags |= IFC_IN_DETACH; 4894 STATE_UNLOCK(ctx); 4895 4896 CTX_LOCK(ctx); 4897 iflib_stop(ctx); 4898 CTX_UNLOCK(ctx); 4899 4900 /* Unregister VLAN events */ 4901 if (ctx->ifc_vlan_attach_event != NULL) 4902 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4903 if (ctx->ifc_vlan_detach_event != NULL) 4904 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4905 4906 iflib_netmap_detach(ifp); 4907 ether_ifdetach(ifp); 4908 if (ctx->ifc_led_dev != NULL) 4909 led_destroy(ctx->ifc_led_dev); 4910 /* XXX drain any dependent tasks */ 4911 tqg = qgroup_if_io_tqg; 4912 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4913 callout_drain(&txq->ift_timer); 4914 if (txq->ift_task.gt_uniq != NULL) 4915 taskqgroup_detach(tqg, &txq->ift_task); 4916 } 4917 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4918 if (rxq->ifr_task.gt_uniq != NULL) 4919 taskqgroup_detach(tqg, &rxq->ifr_task); 4920 4921 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4922 free(fl->ifl_rx_bitmap, M_IFLIB); 4923 } 4924 tqg = qgroup_if_config_tqg; 4925 if (ctx->ifc_admin_task.gt_uniq != NULL) 4926 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4927 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4928 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4929 CTX_LOCK(ctx); 4930 IFDI_DETACH(ctx); 4931 CTX_UNLOCK(ctx); 4932 4933 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4934 CTX_LOCK_DESTROY(ctx); 4935 device_set_softc(ctx->ifc_dev, NULL); 4936 iflib_free_intr_mem(ctx); 4937 4938 bus_generic_detach(dev); 4939 if_free(ifp); 4940 4941 iflib_tx_structures_free(ctx); 4942 iflib_rx_structures_free(ctx); 4943 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4944 free(ctx->ifc_softc, M_IFLIB); 4945 STATE_LOCK_DESTROY(ctx); 4946 free(ctx, M_IFLIB); 4947 return (0); 4948 } 4949 4950 static void 4951 iflib_free_intr_mem(if_ctx_t ctx) 4952 { 4953 4954 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4955 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4956 } 4957 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4958 pci_release_msi(ctx->ifc_dev); 4959 } 4960 if (ctx->ifc_msix_mem != NULL) { 4961 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4962 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 4963 ctx->ifc_msix_mem = NULL; 4964 } 4965 } 4966 4967 int 4968 iflib_device_detach(device_t dev) 4969 { 4970 if_ctx_t ctx = device_get_softc(dev); 4971 4972 return (iflib_device_deregister(ctx)); 4973 } 4974 4975 int 4976 iflib_device_suspend(device_t dev) 4977 { 4978 if_ctx_t ctx = device_get_softc(dev); 4979 4980 CTX_LOCK(ctx); 4981 IFDI_SUSPEND(ctx); 4982 CTX_UNLOCK(ctx); 4983 4984 return bus_generic_suspend(dev); 4985 } 4986 int 4987 iflib_device_shutdown(device_t dev) 4988 { 4989 if_ctx_t ctx = device_get_softc(dev); 4990 4991 CTX_LOCK(ctx); 4992 IFDI_SHUTDOWN(ctx); 4993 CTX_UNLOCK(ctx); 4994 4995 return bus_generic_suspend(dev); 4996 } 4997 4998 4999 int 5000 iflib_device_resume(device_t dev) 5001 { 5002 if_ctx_t ctx = device_get_softc(dev); 5003 iflib_txq_t txq = ctx->ifc_txqs; 5004 5005 CTX_LOCK(ctx); 5006 IFDI_RESUME(ctx); 5007 iflib_if_init_locked(ctx); 5008 CTX_UNLOCK(ctx); 5009 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5010 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5011 5012 return (bus_generic_resume(dev)); 5013 } 5014 5015 int 5016 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5017 { 5018 int error; 5019 if_ctx_t ctx = device_get_softc(dev); 5020 5021 CTX_LOCK(ctx); 5022 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5023 CTX_UNLOCK(ctx); 5024 5025 return (error); 5026 } 5027 5028 void 5029 iflib_device_iov_uninit(device_t dev) 5030 { 5031 if_ctx_t ctx = device_get_softc(dev); 5032 5033 CTX_LOCK(ctx); 5034 IFDI_IOV_UNINIT(ctx); 5035 CTX_UNLOCK(ctx); 5036 } 5037 5038 int 5039 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5040 { 5041 int error; 5042 if_ctx_t ctx = device_get_softc(dev); 5043 5044 CTX_LOCK(ctx); 5045 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5046 CTX_UNLOCK(ctx); 5047 5048 return (error); 5049 } 5050 5051 /********************************************************************* 5052 * 5053 * MODULE FUNCTION DEFINITIONS 5054 * 5055 **********************************************************************/ 5056 5057 /* 5058 * - Start a fast taskqueue thread for each core 5059 * - Start a taskqueue for control operations 5060 */ 5061 static int 5062 iflib_module_init(void) 5063 { 5064 return (0); 5065 } 5066 5067 static int 5068 iflib_module_event_handler(module_t mod, int what, void *arg) 5069 { 5070 int err; 5071 5072 switch (what) { 5073 case MOD_LOAD: 5074 if ((err = iflib_module_init()) != 0) 5075 return (err); 5076 break; 5077 case MOD_UNLOAD: 5078 return (EBUSY); 5079 default: 5080 return (EOPNOTSUPP); 5081 } 5082 5083 return (0); 5084 } 5085 5086 /********************************************************************* 5087 * 5088 * PUBLIC FUNCTION DEFINITIONS 5089 * ordered as in iflib.h 5090 * 5091 **********************************************************************/ 5092 5093 5094 static void 5095 _iflib_assert(if_shared_ctx_t sctx) 5096 { 5097 MPASS(sctx->isc_tx_maxsize); 5098 MPASS(sctx->isc_tx_maxsegsize); 5099 5100 MPASS(sctx->isc_rx_maxsize); 5101 MPASS(sctx->isc_rx_nsegments); 5102 MPASS(sctx->isc_rx_maxsegsize); 5103 5104 MPASS(sctx->isc_nrxd_min[0]); 5105 MPASS(sctx->isc_nrxd_max[0]); 5106 MPASS(sctx->isc_nrxd_default[0]); 5107 MPASS(sctx->isc_ntxd_min[0]); 5108 MPASS(sctx->isc_ntxd_max[0]); 5109 MPASS(sctx->isc_ntxd_default[0]); 5110 } 5111 5112 static void 5113 _iflib_pre_assert(if_softc_ctx_t scctx) 5114 { 5115 5116 MPASS(scctx->isc_txrx->ift_txd_encap); 5117 MPASS(scctx->isc_txrx->ift_txd_flush); 5118 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5119 MPASS(scctx->isc_txrx->ift_rxd_available); 5120 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5121 MPASS(scctx->isc_txrx->ift_rxd_refill); 5122 MPASS(scctx->isc_txrx->ift_rxd_flush); 5123 } 5124 5125 static int 5126 iflib_register(if_ctx_t ctx) 5127 { 5128 if_shared_ctx_t sctx = ctx->ifc_sctx; 5129 driver_t *driver = sctx->isc_driver; 5130 device_t dev = ctx->ifc_dev; 5131 if_t ifp; 5132 5133 _iflib_assert(sctx); 5134 5135 CTX_LOCK_INIT(ctx); 5136 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5137 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5138 if (ifp == NULL) { 5139 device_printf(dev, "can not allocate ifnet structure\n"); 5140 return (ENOMEM); 5141 } 5142 5143 /* 5144 * Initialize our context's device specific methods 5145 */ 5146 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5147 kobj_class_compile((kobj_class_t) driver); 5148 driver->refs++; 5149 5150 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5151 if_setsoftc(ifp, ctx); 5152 if_setdev(ifp, dev); 5153 if_setinitfn(ifp, iflib_if_init); 5154 if_setioctlfn(ifp, iflib_if_ioctl); 5155 #ifdef ALTQ 5156 if_setstartfn(ifp, iflib_altq_if_start); 5157 if_settransmitfn(ifp, iflib_altq_if_transmit); 5158 if_setsendqready(ifp); 5159 #else 5160 if_settransmitfn(ifp, iflib_if_transmit); 5161 #endif 5162 if_setqflushfn(ifp, iflib_if_qflush); 5163 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5164 5165 ctx->ifc_vlan_attach_event = 5166 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5167 EVENTHANDLER_PRI_FIRST); 5168 ctx->ifc_vlan_detach_event = 5169 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5170 EVENTHANDLER_PRI_FIRST); 5171 5172 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 5173 iflib_media_change, iflib_media_status); 5174 5175 return (0); 5176 } 5177 5178 5179 static int 5180 iflib_queues_alloc(if_ctx_t ctx) 5181 { 5182 if_shared_ctx_t sctx = ctx->ifc_sctx; 5183 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5184 device_t dev = ctx->ifc_dev; 5185 int nrxqsets = scctx->isc_nrxqsets; 5186 int ntxqsets = scctx->isc_ntxqsets; 5187 iflib_txq_t txq; 5188 iflib_rxq_t rxq; 5189 iflib_fl_t fl = NULL; 5190 int i, j, cpu, err, txconf, rxconf; 5191 iflib_dma_info_t ifdip; 5192 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5193 uint32_t *txqsizes = scctx->isc_txqsizes; 5194 uint8_t nrxqs = sctx->isc_nrxqs; 5195 uint8_t ntxqs = sctx->isc_ntxqs; 5196 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5197 caddr_t *vaddrs; 5198 uint64_t *paddrs; 5199 5200 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5201 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5202 5203 /* Allocate the TX ring struct memory */ 5204 if (!(ctx->ifc_txqs = 5205 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5206 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5207 device_printf(dev, "Unable to allocate TX ring memory\n"); 5208 err = ENOMEM; 5209 goto fail; 5210 } 5211 5212 /* Now allocate the RX */ 5213 if (!(ctx->ifc_rxqs = 5214 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5215 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5216 device_printf(dev, "Unable to allocate RX ring memory\n"); 5217 err = ENOMEM; 5218 goto rx_fail; 5219 } 5220 5221 txq = ctx->ifc_txqs; 5222 rxq = ctx->ifc_rxqs; 5223 5224 /* 5225 * XXX handle allocation failure 5226 */ 5227 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5228 /* Set up some basics */ 5229 5230 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5231 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5232 device_printf(dev, 5233 "Unable to allocate TX DMA info memory\n"); 5234 err = ENOMEM; 5235 goto err_tx_desc; 5236 } 5237 txq->ift_ifdi = ifdip; 5238 for (j = 0; j < ntxqs; j++, ifdip++) { 5239 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5240 device_printf(dev, 5241 "Unable to allocate TX descriptors\n"); 5242 err = ENOMEM; 5243 goto err_tx_desc; 5244 } 5245 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5246 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5247 } 5248 txq->ift_ctx = ctx; 5249 txq->ift_id = i; 5250 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5251 txq->ift_br_offset = 1; 5252 } else { 5253 txq->ift_br_offset = 0; 5254 } 5255 /* XXX fix this */ 5256 txq->ift_timer.c_cpu = cpu; 5257 5258 if (iflib_txsd_alloc(txq)) { 5259 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5260 err = ENOMEM; 5261 goto err_tx_desc; 5262 } 5263 5264 /* Initialize the TX lock */ 5265 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 5266 device_get_nameunit(dev), txq->ift_id); 5267 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5268 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5269 5270 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 5271 device_get_nameunit(dev), txq->ift_id); 5272 5273 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5274 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5275 if (err) { 5276 /* XXX free any allocated rings */ 5277 device_printf(dev, "Unable to allocate buf_ring\n"); 5278 goto err_tx_desc; 5279 } 5280 } 5281 5282 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5283 /* Set up some basics */ 5284 5285 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5286 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5287 device_printf(dev, 5288 "Unable to allocate RX DMA info memory\n"); 5289 err = ENOMEM; 5290 goto err_tx_desc; 5291 } 5292 5293 rxq->ifr_ifdi = ifdip; 5294 /* XXX this needs to be changed if #rx queues != #tx queues */ 5295 rxq->ifr_ntxqirq = 1; 5296 rxq->ifr_txqid[0] = i; 5297 for (j = 0; j < nrxqs; j++, ifdip++) { 5298 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5299 device_printf(dev, 5300 "Unable to allocate RX descriptors\n"); 5301 err = ENOMEM; 5302 goto err_tx_desc; 5303 } 5304 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5305 } 5306 rxq->ifr_ctx = ctx; 5307 rxq->ifr_id = i; 5308 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5309 rxq->ifr_fl_offset = 1; 5310 } else { 5311 rxq->ifr_fl_offset = 0; 5312 } 5313 rxq->ifr_nfl = nfree_lists; 5314 if (!(fl = 5315 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5316 device_printf(dev, "Unable to allocate free list memory\n"); 5317 err = ENOMEM; 5318 goto err_tx_desc; 5319 } 5320 rxq->ifr_fl = fl; 5321 for (j = 0; j < nfree_lists; j++) { 5322 fl[j].ifl_rxq = rxq; 5323 fl[j].ifl_id = j; 5324 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5325 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5326 } 5327 /* Allocate receive buffers for the ring */ 5328 if (iflib_rxsd_alloc(rxq)) { 5329 device_printf(dev, 5330 "Critical Failure setting up receive buffers\n"); 5331 err = ENOMEM; 5332 goto err_rx_desc; 5333 } 5334 5335 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5336 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5337 M_WAITOK); 5338 } 5339 5340 /* TXQs */ 5341 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5342 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5343 for (i = 0; i < ntxqsets; i++) { 5344 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5345 5346 for (j = 0; j < ntxqs; j++, di++) { 5347 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5348 paddrs[i*ntxqs + j] = di->idi_paddr; 5349 } 5350 } 5351 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5352 device_printf(ctx->ifc_dev, 5353 "Unable to allocate device TX queue\n"); 5354 iflib_tx_structures_free(ctx); 5355 free(vaddrs, M_IFLIB); 5356 free(paddrs, M_IFLIB); 5357 goto err_rx_desc; 5358 } 5359 free(vaddrs, M_IFLIB); 5360 free(paddrs, M_IFLIB); 5361 5362 /* RXQs */ 5363 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5364 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5365 for (i = 0; i < nrxqsets; i++) { 5366 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5367 5368 for (j = 0; j < nrxqs; j++, di++) { 5369 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5370 paddrs[i*nrxqs + j] = di->idi_paddr; 5371 } 5372 } 5373 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5374 device_printf(ctx->ifc_dev, 5375 "Unable to allocate device RX queue\n"); 5376 iflib_tx_structures_free(ctx); 5377 free(vaddrs, M_IFLIB); 5378 free(paddrs, M_IFLIB); 5379 goto err_rx_desc; 5380 } 5381 free(vaddrs, M_IFLIB); 5382 free(paddrs, M_IFLIB); 5383 5384 return (0); 5385 5386 /* XXX handle allocation failure changes */ 5387 err_rx_desc: 5388 err_tx_desc: 5389 rx_fail: 5390 if (ctx->ifc_rxqs != NULL) 5391 free(ctx->ifc_rxqs, M_IFLIB); 5392 ctx->ifc_rxqs = NULL; 5393 if (ctx->ifc_txqs != NULL) 5394 free(ctx->ifc_txqs, M_IFLIB); 5395 ctx->ifc_txqs = NULL; 5396 fail: 5397 return (err); 5398 } 5399 5400 static int 5401 iflib_tx_structures_setup(if_ctx_t ctx) 5402 { 5403 iflib_txq_t txq = ctx->ifc_txqs; 5404 int i; 5405 5406 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5407 iflib_txq_setup(txq); 5408 5409 return (0); 5410 } 5411 5412 static void 5413 iflib_tx_structures_free(if_ctx_t ctx) 5414 { 5415 iflib_txq_t txq = ctx->ifc_txqs; 5416 if_shared_ctx_t sctx = ctx->ifc_sctx; 5417 int i, j; 5418 5419 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5420 iflib_txq_destroy(txq); 5421 for (j = 0; j < sctx->isc_ntxqs; j++) 5422 iflib_dma_free(&txq->ift_ifdi[j]); 5423 } 5424 free(ctx->ifc_txqs, M_IFLIB); 5425 ctx->ifc_txqs = NULL; 5426 IFDI_QUEUES_FREE(ctx); 5427 } 5428 5429 /********************************************************************* 5430 * 5431 * Initialize all receive rings. 5432 * 5433 **********************************************************************/ 5434 static int 5435 iflib_rx_structures_setup(if_ctx_t ctx) 5436 { 5437 iflib_rxq_t rxq = ctx->ifc_rxqs; 5438 int q; 5439 #if defined(INET6) || defined(INET) 5440 int i, err; 5441 #endif 5442 5443 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5444 #if defined(INET6) || defined(INET) 5445 tcp_lro_free(&rxq->ifr_lc); 5446 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5447 TCP_LRO_ENTRIES, min(1024, 5448 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 5449 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 5450 goto fail; 5451 } 5452 rxq->ifr_lro_enabled = TRUE; 5453 #endif 5454 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5455 } 5456 return (0); 5457 #if defined(INET6) || defined(INET) 5458 fail: 5459 /* 5460 * Free RX software descriptors allocated so far, we will only handle 5461 * the rings that completed, the failing case will have 5462 * cleaned up for itself. 'q' failed, so its the terminus. 5463 */ 5464 rxq = ctx->ifc_rxqs; 5465 for (i = 0; i < q; ++i, rxq++) { 5466 iflib_rx_sds_free(rxq); 5467 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5468 } 5469 return (err); 5470 #endif 5471 } 5472 5473 /********************************************************************* 5474 * 5475 * Free all receive rings. 5476 * 5477 **********************************************************************/ 5478 static void 5479 iflib_rx_structures_free(if_ctx_t ctx) 5480 { 5481 iflib_rxq_t rxq = ctx->ifc_rxqs; 5482 5483 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5484 iflib_rx_sds_free(rxq); 5485 } 5486 free(ctx->ifc_rxqs, M_IFLIB); 5487 ctx->ifc_rxqs = NULL; 5488 } 5489 5490 static int 5491 iflib_qset_structures_setup(if_ctx_t ctx) 5492 { 5493 int err; 5494 5495 /* 5496 * It is expected that the caller takes care of freeing queues if this 5497 * fails. 5498 */ 5499 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5500 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5501 return (err); 5502 } 5503 5504 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5505 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5506 5507 return (err); 5508 } 5509 5510 int 5511 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5512 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5513 { 5514 5515 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5516 } 5517 5518 #ifdef SMP 5519 static int 5520 find_nth(if_ctx_t ctx, int qid) 5521 { 5522 cpuset_t cpus; 5523 int i, cpuid, eqid, count; 5524 5525 CPU_COPY(&ctx->ifc_cpus, &cpus); 5526 count = CPU_COUNT(&cpus); 5527 eqid = qid % count; 5528 /* clear up to the qid'th bit */ 5529 for (i = 0; i < eqid; i++) { 5530 cpuid = CPU_FFS(&cpus); 5531 MPASS(cpuid != 0); 5532 CPU_CLR(cpuid-1, &cpus); 5533 } 5534 cpuid = CPU_FFS(&cpus); 5535 MPASS(cpuid != 0); 5536 return (cpuid-1); 5537 } 5538 5539 #ifdef SCHED_ULE 5540 extern struct cpu_group *cpu_top; /* CPU topology */ 5541 5542 static int 5543 find_child_with_core(int cpu, struct cpu_group *grp) 5544 { 5545 int i; 5546 5547 if (grp->cg_children == 0) 5548 return -1; 5549 5550 MPASS(grp->cg_child); 5551 for (i = 0; i < grp->cg_children; i++) { 5552 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5553 return i; 5554 } 5555 5556 return -1; 5557 } 5558 5559 /* 5560 * Find the nth "close" core to the specified core 5561 * "close" is defined as the deepest level that shares 5562 * at least an L2 cache. With threads, this will be 5563 * threads on the same core. If the sahred cache is L3 5564 * or higher, simply returns the same core. 5565 */ 5566 static int 5567 find_close_core(int cpu, int core_offset) 5568 { 5569 struct cpu_group *grp; 5570 int i; 5571 int fcpu; 5572 cpuset_t cs; 5573 5574 grp = cpu_top; 5575 if (grp == NULL) 5576 return cpu; 5577 i = 0; 5578 while ((i = find_child_with_core(cpu, grp)) != -1) { 5579 /* If the child only has one cpu, don't descend */ 5580 if (grp->cg_child[i].cg_count <= 1) 5581 break; 5582 grp = &grp->cg_child[i]; 5583 } 5584 5585 /* If they don't share at least an L2 cache, use the same CPU */ 5586 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5587 return cpu; 5588 5589 /* Now pick one */ 5590 CPU_COPY(&grp->cg_mask, &cs); 5591 5592 /* Add the selected CPU offset to core offset. */ 5593 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5594 if (fcpu - 1 == cpu) 5595 break; 5596 CPU_CLR(fcpu - 1, &cs); 5597 } 5598 MPASS(fcpu); 5599 5600 core_offset += i; 5601 5602 CPU_COPY(&grp->cg_mask, &cs); 5603 for (i = core_offset % grp->cg_count; i > 0; i--) { 5604 MPASS(CPU_FFS(&cs)); 5605 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5606 } 5607 MPASS(CPU_FFS(&cs)); 5608 return CPU_FFS(&cs) - 1; 5609 } 5610 #else 5611 static int 5612 find_close_core(int cpu, int core_offset __unused) 5613 { 5614 return cpu; 5615 } 5616 #endif 5617 5618 static int 5619 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5620 { 5621 switch (type) { 5622 case IFLIB_INTR_TX: 5623 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5624 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5625 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5626 case IFLIB_INTR_RX: 5627 case IFLIB_INTR_RXTX: 5628 /* RX queues get the specified core */ 5629 return qid / CPU_COUNT(&ctx->ifc_cpus); 5630 default: 5631 return -1; 5632 } 5633 } 5634 #else 5635 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5636 #define find_close_core(cpuid, tid) CPU_FIRST() 5637 #define find_nth(ctx, gid) CPU_FIRST() 5638 #endif 5639 5640 /* Just to avoid copy/paste */ 5641 static inline int 5642 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5643 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5644 const char *name) 5645 { 5646 device_t dev; 5647 int err, cpuid, tid; 5648 5649 dev = ctx->ifc_dev; 5650 cpuid = find_nth(ctx, qid); 5651 tid = get_core_offset(ctx, type, qid); 5652 MPASS(tid >= 0); 5653 cpuid = find_close_core(cpuid, tid); 5654 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 5655 name); 5656 if (err) { 5657 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 5658 return (err); 5659 } 5660 #ifdef notyet 5661 if (cpuid > ctx->ifc_cpuid_highest) 5662 ctx->ifc_cpuid_highest = cpuid; 5663 #endif 5664 return 0; 5665 } 5666 5667 int 5668 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5669 iflib_intr_type_t type, driver_filter_t *filter, 5670 void *filter_arg, int qid, const char *name) 5671 { 5672 device_t dev; 5673 struct grouptask *gtask; 5674 struct taskqgroup *tqg; 5675 iflib_filter_info_t info; 5676 gtask_fn_t *fn; 5677 int tqrid, err; 5678 driver_filter_t *intr_fast; 5679 void *q; 5680 5681 info = &ctx->ifc_filter_info; 5682 tqrid = rid; 5683 5684 switch (type) { 5685 /* XXX merge tx/rx for netmap? */ 5686 case IFLIB_INTR_TX: 5687 q = &ctx->ifc_txqs[qid]; 5688 info = &ctx->ifc_txqs[qid].ift_filter_info; 5689 gtask = &ctx->ifc_txqs[qid].ift_task; 5690 tqg = qgroup_if_io_tqg; 5691 fn = _task_fn_tx; 5692 intr_fast = iflib_fast_intr; 5693 GROUPTASK_INIT(gtask, 0, fn, q); 5694 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5695 break; 5696 case IFLIB_INTR_RX: 5697 q = &ctx->ifc_rxqs[qid]; 5698 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5699 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5700 tqg = qgroup_if_io_tqg; 5701 fn = _task_fn_rx; 5702 intr_fast = iflib_fast_intr; 5703 GROUPTASK_INIT(gtask, 0, fn, q); 5704 break; 5705 case IFLIB_INTR_RXTX: 5706 q = &ctx->ifc_rxqs[qid]; 5707 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5708 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5709 tqg = qgroup_if_io_tqg; 5710 fn = _task_fn_rx; 5711 intr_fast = iflib_fast_intr_rxtx; 5712 GROUPTASK_INIT(gtask, 0, fn, q); 5713 break; 5714 case IFLIB_INTR_ADMIN: 5715 q = ctx; 5716 tqrid = -1; 5717 info = &ctx->ifc_filter_info; 5718 gtask = &ctx->ifc_admin_task; 5719 tqg = qgroup_if_config_tqg; 5720 fn = _task_fn_admin; 5721 intr_fast = iflib_fast_intr_ctx; 5722 break; 5723 default: 5724 panic("unknown net intr type"); 5725 } 5726 5727 info->ifi_filter = filter; 5728 info->ifi_filter_arg = filter_arg; 5729 info->ifi_task = gtask; 5730 info->ifi_ctx = q; 5731 5732 dev = ctx->ifc_dev; 5733 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5734 if (err != 0) { 5735 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 5736 return (err); 5737 } 5738 if (type == IFLIB_INTR_ADMIN) 5739 return (0); 5740 5741 if (tqrid != -1) { 5742 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 5743 q, name); 5744 if (err) 5745 return (err); 5746 } else { 5747 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 5748 } 5749 5750 return (0); 5751 } 5752 5753 void 5754 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 5755 { 5756 struct grouptask *gtask; 5757 struct taskqgroup *tqg; 5758 gtask_fn_t *fn; 5759 void *q; 5760 int err; 5761 5762 switch (type) { 5763 case IFLIB_INTR_TX: 5764 q = &ctx->ifc_txqs[qid]; 5765 gtask = &ctx->ifc_txqs[qid].ift_task; 5766 tqg = qgroup_if_io_tqg; 5767 fn = _task_fn_tx; 5768 break; 5769 case IFLIB_INTR_RX: 5770 q = &ctx->ifc_rxqs[qid]; 5771 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5772 tqg = qgroup_if_io_tqg; 5773 fn = _task_fn_rx; 5774 break; 5775 case IFLIB_INTR_IOV: 5776 q = ctx; 5777 gtask = &ctx->ifc_vflr_task; 5778 tqg = qgroup_if_config_tqg; 5779 fn = _task_fn_iov; 5780 break; 5781 default: 5782 panic("unknown net intr type"); 5783 } 5784 GROUPTASK_INIT(gtask, 0, fn, q); 5785 if (irq != NULL) { 5786 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 5787 q, name); 5788 if (err) 5789 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 5790 irq->ii_res, name); 5791 } else { 5792 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 5793 } 5794 } 5795 5796 void 5797 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5798 { 5799 5800 if (irq->ii_tag) 5801 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5802 5803 if (irq->ii_res) 5804 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 5805 rman_get_rid(irq->ii_res), irq->ii_res); 5806 } 5807 5808 static int 5809 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 5810 { 5811 iflib_txq_t txq = ctx->ifc_txqs; 5812 iflib_rxq_t rxq = ctx->ifc_rxqs; 5813 if_irq_t irq = &ctx->ifc_legacy_irq; 5814 iflib_filter_info_t info; 5815 device_t dev; 5816 struct grouptask *gtask; 5817 struct resource *res; 5818 struct taskqgroup *tqg; 5819 gtask_fn_t *fn; 5820 int tqrid; 5821 void *q; 5822 int err; 5823 5824 q = &ctx->ifc_rxqs[0]; 5825 info = &rxq[0].ifr_filter_info; 5826 gtask = &rxq[0].ifr_task; 5827 tqg = qgroup_if_io_tqg; 5828 tqrid = irq->ii_rid = *rid; 5829 fn = _task_fn_rx; 5830 5831 ctx->ifc_flags |= IFC_LEGACY; 5832 info->ifi_filter = filter; 5833 info->ifi_filter_arg = filter_arg; 5834 info->ifi_task = gtask; 5835 info->ifi_ctx = ctx; 5836 5837 dev = ctx->ifc_dev; 5838 /* We allocate a single interrupt resource */ 5839 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5840 return (err); 5841 GROUPTASK_INIT(gtask, 0, fn, q); 5842 res = irq->ii_res; 5843 taskqgroup_attach(tqg, gtask, q, dev, res, name); 5844 5845 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5846 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 5847 "tx"); 5848 return (0); 5849 } 5850 5851 void 5852 iflib_led_create(if_ctx_t ctx) 5853 { 5854 5855 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5856 device_get_nameunit(ctx->ifc_dev)); 5857 } 5858 5859 void 5860 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5861 { 5862 5863 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5864 } 5865 5866 void 5867 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5868 { 5869 5870 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5871 } 5872 5873 void 5874 iflib_admin_intr_deferred(if_ctx_t ctx) 5875 { 5876 #ifdef INVARIANTS 5877 struct grouptask *gtask; 5878 5879 gtask = &ctx->ifc_admin_task; 5880 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5881 #endif 5882 5883 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5884 } 5885 5886 void 5887 iflib_iov_intr_deferred(if_ctx_t ctx) 5888 { 5889 5890 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5891 } 5892 5893 void 5894 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5895 { 5896 5897 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 5898 name); 5899 } 5900 5901 void 5902 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 5903 const char *name) 5904 { 5905 5906 GROUPTASK_INIT(gtask, 0, fn, ctx); 5907 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 5908 name); 5909 } 5910 5911 void 5912 iflib_config_gtask_deinit(struct grouptask *gtask) 5913 { 5914 5915 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5916 } 5917 5918 void 5919 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5920 { 5921 if_t ifp = ctx->ifc_ifp; 5922 iflib_txq_t txq = ctx->ifc_txqs; 5923 5924 if_setbaudrate(ifp, baudrate); 5925 if (baudrate >= IF_Gbps(10)) { 5926 STATE_LOCK(ctx); 5927 ctx->ifc_flags |= IFC_PREFETCH; 5928 STATE_UNLOCK(ctx); 5929 } 5930 /* If link down, disable watchdog */ 5931 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5932 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5933 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5934 } 5935 ctx->ifc_link_state = link_state; 5936 if_link_state_change(ifp, link_state); 5937 } 5938 5939 static int 5940 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5941 { 5942 int credits; 5943 #ifdef INVARIANTS 5944 int credits_pre = txq->ift_cidx_processed; 5945 #endif 5946 5947 if (ctx->isc_txd_credits_update == NULL) 5948 return (0); 5949 5950 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 5951 BUS_DMASYNC_POSTREAD); 5952 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5953 return (0); 5954 5955 txq->ift_processed += credits; 5956 txq->ift_cidx_processed += credits; 5957 5958 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5959 if (txq->ift_cidx_processed >= txq->ift_size) 5960 txq->ift_cidx_processed -= txq->ift_size; 5961 return (credits); 5962 } 5963 5964 static int 5965 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5966 { 5967 iflib_fl_t fl; 5968 u_int i; 5969 5970 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 5971 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 5972 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 5973 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5974 budget)); 5975 } 5976 5977 void 5978 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5979 const char *description, if_int_delay_info_t info, 5980 int offset, int value) 5981 { 5982 info->iidi_ctx = ctx; 5983 info->iidi_offset = offset; 5984 info->iidi_value = value; 5985 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5986 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5987 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5988 info, 0, iflib_sysctl_int_delay, "I", description); 5989 } 5990 5991 struct sx * 5992 iflib_ctx_lock_get(if_ctx_t ctx) 5993 { 5994 5995 return (&ctx->ifc_ctx_sx); 5996 } 5997 5998 static int 5999 iflib_msix_init(if_ctx_t ctx) 6000 { 6001 device_t dev = ctx->ifc_dev; 6002 if_shared_ctx_t sctx = ctx->ifc_sctx; 6003 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6004 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 6005 int iflib_num_tx_queues, iflib_num_rx_queues; 6006 int err, admincnt, bar; 6007 6008 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6009 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6010 6011 if (bootverbose) 6012 device_printf(dev, "msix_init qsets capped at %d\n", 6013 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6014 6015 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6016 admincnt = sctx->isc_admin_intrcnt; 6017 /* Override by tuneable */ 6018 if (scctx->isc_disable_msix) 6019 goto msi; 6020 6021 /* First try MSI-X */ 6022 if ((msgs = pci_msix_count(dev)) == 0) { 6023 if (bootverbose) 6024 device_printf(dev, "MSI-X not supported or disabled\n"); 6025 goto msi; 6026 } 6027 /* 6028 * bar == -1 => "trust me I know what I'm doing" 6029 * Some drivers are for hardware that is so shoddily 6030 * documented that no one knows which bars are which 6031 * so the developer has to map all bars. This hack 6032 * allows shoddy garbage to use MSI-X in this framework. 6033 */ 6034 if (bar != -1) { 6035 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6036 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6037 if (ctx->ifc_msix_mem == NULL) { 6038 device_printf(dev, "Unable to map MSI-X table\n"); 6039 goto msi; 6040 } 6041 } 6042 #if IFLIB_DEBUG 6043 /* use only 1 qset in debug mode */ 6044 queuemsgs = min(msgs - admincnt, 1); 6045 #else 6046 queuemsgs = msgs - admincnt; 6047 #endif 6048 #ifdef RSS 6049 queues = imin(queuemsgs, rss_getnumbuckets()); 6050 #else 6051 queues = queuemsgs; 6052 #endif 6053 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6054 if (bootverbose) 6055 device_printf(dev, 6056 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6057 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6058 #ifdef RSS 6059 /* If we're doing RSS, clamp at the number of RSS buckets */ 6060 if (queues > rss_getnumbuckets()) 6061 queues = rss_getnumbuckets(); 6062 #endif 6063 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6064 rx_queues = iflib_num_rx_queues; 6065 else 6066 rx_queues = queues; 6067 6068 if (rx_queues > scctx->isc_nrxqsets) 6069 rx_queues = scctx->isc_nrxqsets; 6070 6071 /* 6072 * We want this to be all logical CPUs by default 6073 */ 6074 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6075 tx_queues = iflib_num_tx_queues; 6076 else 6077 tx_queues = mp_ncpus; 6078 6079 if (tx_queues > scctx->isc_ntxqsets) 6080 tx_queues = scctx->isc_ntxqsets; 6081 6082 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6083 #ifdef INVARIANTS 6084 if (tx_queues != rx_queues) 6085 device_printf(dev, 6086 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6087 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6088 #endif 6089 tx_queues = min(rx_queues, tx_queues); 6090 rx_queues = min(rx_queues, tx_queues); 6091 } 6092 6093 device_printf(dev, "Using %d rx queues %d tx queues\n", 6094 rx_queues, tx_queues); 6095 6096 vectors = rx_queues + admincnt; 6097 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6098 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6099 vectors); 6100 scctx->isc_vectors = vectors; 6101 scctx->isc_nrxqsets = rx_queues; 6102 scctx->isc_ntxqsets = tx_queues; 6103 scctx->isc_intr = IFLIB_INTR_MSIX; 6104 6105 return (vectors); 6106 } else { 6107 device_printf(dev, 6108 "failed to allocate %d MSI-X vectors, err: %d - using MSI\n", 6109 vectors, err); 6110 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6111 ctx->ifc_msix_mem); 6112 ctx->ifc_msix_mem = NULL; 6113 } 6114 msi: 6115 vectors = pci_msi_count(dev); 6116 scctx->isc_nrxqsets = 1; 6117 scctx->isc_ntxqsets = 1; 6118 scctx->isc_vectors = vectors; 6119 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6120 device_printf(dev,"Using an MSI interrupt\n"); 6121 scctx->isc_intr = IFLIB_INTR_MSI; 6122 } else { 6123 scctx->isc_vectors = 1; 6124 device_printf(dev,"Using a Legacy interrupt\n"); 6125 scctx->isc_intr = IFLIB_INTR_LEGACY; 6126 } 6127 6128 return (vectors); 6129 } 6130 6131 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6132 6133 static int 6134 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6135 { 6136 int rc; 6137 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6138 struct sbuf *sb; 6139 const char *ring_state = "UNKNOWN"; 6140 6141 /* XXX needed ? */ 6142 rc = sysctl_wire_old_buffer(req, 0); 6143 MPASS(rc == 0); 6144 if (rc != 0) 6145 return (rc); 6146 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6147 MPASS(sb != NULL); 6148 if (sb == NULL) 6149 return (ENOMEM); 6150 if (state[3] <= 3) 6151 ring_state = ring_states[state[3]]; 6152 6153 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6154 state[0], state[1], state[2], ring_state); 6155 rc = sbuf_finish(sb); 6156 sbuf_delete(sb); 6157 return(rc); 6158 } 6159 6160 enum iflib_ndesc_handler { 6161 IFLIB_NTXD_HANDLER, 6162 IFLIB_NRXD_HANDLER, 6163 }; 6164 6165 static int 6166 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6167 { 6168 if_ctx_t ctx = (void *)arg1; 6169 enum iflib_ndesc_handler type = arg2; 6170 char buf[256] = {0}; 6171 qidx_t *ndesc; 6172 char *p, *next; 6173 int nqs, rc, i; 6174 6175 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 6176 6177 nqs = 8; 6178 switch(type) { 6179 case IFLIB_NTXD_HANDLER: 6180 ndesc = ctx->ifc_sysctl_ntxds; 6181 if (ctx->ifc_sctx) 6182 nqs = ctx->ifc_sctx->isc_ntxqs; 6183 break; 6184 case IFLIB_NRXD_HANDLER: 6185 ndesc = ctx->ifc_sysctl_nrxds; 6186 if (ctx->ifc_sctx) 6187 nqs = ctx->ifc_sctx->isc_nrxqs; 6188 break; 6189 default: 6190 panic("unhandled type"); 6191 } 6192 if (nqs == 0) 6193 nqs = 8; 6194 6195 for (i=0; i<8; i++) { 6196 if (i >= nqs) 6197 break; 6198 if (i) 6199 strcat(buf, ","); 6200 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6201 } 6202 6203 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6204 if (rc || req->newptr == NULL) 6205 return rc; 6206 6207 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6208 i++, p = strsep(&next, " ,")) { 6209 ndesc[i] = strtoul(p, NULL, 10); 6210 } 6211 6212 return(rc); 6213 } 6214 6215 #define NAME_BUFLEN 32 6216 static void 6217 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6218 { 6219 device_t dev = iflib_get_dev(ctx); 6220 struct sysctl_oid_list *child, *oid_list; 6221 struct sysctl_ctx_list *ctx_list; 6222 struct sysctl_oid *node; 6223 6224 ctx_list = device_get_sysctl_ctx(dev); 6225 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6226 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6227 CTLFLAG_RD, NULL, "IFLIB fields"); 6228 oid_list = SYSCTL_CHILDREN(node); 6229 6230 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6231 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 6232 "driver version"); 6233 6234 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6235 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6236 "# of txqs to use, 0 => use default #"); 6237 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6238 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6239 "# of rxqs to use, 0 => use default #"); 6240 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6241 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6242 "permit #txq != #rxq"); 6243 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6244 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6245 "disable MSI-X (default 0)"); 6246 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6247 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6248 "set the rx budget"); 6249 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6250 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6251 "cause tx to abdicate instead of running to completion"); 6252 6253 /* XXX change for per-queue sizes */ 6254 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6255 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6256 mp_ndesc_handler, "A", 6257 "list of # of tx descriptors to use, 0 = use default #"); 6258 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6259 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6260 mp_ndesc_handler, "A", 6261 "list of # of rx descriptors to use, 0 = use default #"); 6262 } 6263 6264 static void 6265 iflib_add_device_sysctl_post(if_ctx_t ctx) 6266 { 6267 if_shared_ctx_t sctx = ctx->ifc_sctx; 6268 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6269 device_t dev = iflib_get_dev(ctx); 6270 struct sysctl_oid_list *child; 6271 struct sysctl_ctx_list *ctx_list; 6272 iflib_fl_t fl; 6273 iflib_txq_t txq; 6274 iflib_rxq_t rxq; 6275 int i, j; 6276 char namebuf[NAME_BUFLEN]; 6277 char *qfmt; 6278 struct sysctl_oid *queue_node, *fl_node, *node; 6279 struct sysctl_oid_list *queue_list, *fl_list; 6280 ctx_list = device_get_sysctl_ctx(dev); 6281 6282 node = ctx->ifc_sysctl_node; 6283 child = SYSCTL_CHILDREN(node); 6284 6285 if (scctx->isc_ntxqsets > 100) 6286 qfmt = "txq%03d"; 6287 else if (scctx->isc_ntxqsets > 10) 6288 qfmt = "txq%02d"; 6289 else 6290 qfmt = "txq%d"; 6291 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6292 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6293 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6294 CTLFLAG_RD, NULL, "Queue Name"); 6295 queue_list = SYSCTL_CHILDREN(queue_node); 6296 #if MEMORY_LOGGING 6297 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6298 CTLFLAG_RD, 6299 &txq->ift_dequeued, "total mbufs freed"); 6300 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6301 CTLFLAG_RD, 6302 &txq->ift_enqueued, "total mbufs enqueued"); 6303 #endif 6304 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6305 CTLFLAG_RD, 6306 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6307 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6308 CTLFLAG_RD, 6309 &txq->ift_pullups, "# of times m_pullup was called"); 6310 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6311 CTLFLAG_RD, 6312 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6313 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6314 CTLFLAG_RD, 6315 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6316 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6317 CTLFLAG_RD, 6318 &txq->ift_map_failed, "# of times dma map failed"); 6319 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6320 CTLFLAG_RD, 6321 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6322 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6323 CTLFLAG_RD, 6324 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6325 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6326 CTLFLAG_RD, 6327 &txq->ift_pidx, 1, "Producer Index"); 6328 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6329 CTLFLAG_RD, 6330 &txq->ift_cidx, 1, "Consumer Index"); 6331 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6332 CTLFLAG_RD, 6333 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6334 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6335 CTLFLAG_RD, 6336 &txq->ift_in_use, 1, "descriptors in use"); 6337 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6338 CTLFLAG_RD, 6339 &txq->ift_processed, "descriptors procesed for clean"); 6340 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6341 CTLFLAG_RD, 6342 &txq->ift_cleaned, "total cleaned"); 6343 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6344 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6345 0, mp_ring_state_handler, "A", "soft ring state"); 6346 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6347 CTLFLAG_RD, &txq->ift_br->enqueues, 6348 "# of enqueues to the mp_ring for this queue"); 6349 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6350 CTLFLAG_RD, &txq->ift_br->drops, 6351 "# of drops in the mp_ring for this queue"); 6352 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6353 CTLFLAG_RD, &txq->ift_br->starts, 6354 "# of normal consumer starts in the mp_ring for this queue"); 6355 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6356 CTLFLAG_RD, &txq->ift_br->stalls, 6357 "# of consumer stalls in the mp_ring for this queue"); 6358 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6359 CTLFLAG_RD, &txq->ift_br->restarts, 6360 "# of consumer restarts in the mp_ring for this queue"); 6361 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6362 CTLFLAG_RD, &txq->ift_br->abdications, 6363 "# of consumer abdications in the mp_ring for this queue"); 6364 } 6365 6366 if (scctx->isc_nrxqsets > 100) 6367 qfmt = "rxq%03d"; 6368 else if (scctx->isc_nrxqsets > 10) 6369 qfmt = "rxq%02d"; 6370 else 6371 qfmt = "rxq%d"; 6372 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6373 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6374 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6375 CTLFLAG_RD, NULL, "Queue Name"); 6376 queue_list = SYSCTL_CHILDREN(queue_node); 6377 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6378 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 6379 CTLFLAG_RD, 6380 &rxq->ifr_cq_pidx, 1, "Producer Index"); 6381 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6382 CTLFLAG_RD, 6383 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6384 } 6385 6386 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6387 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6388 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6389 CTLFLAG_RD, NULL, "freelist Name"); 6390 fl_list = SYSCTL_CHILDREN(fl_node); 6391 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6392 CTLFLAG_RD, 6393 &fl->ifl_pidx, 1, "Producer Index"); 6394 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6395 CTLFLAG_RD, 6396 &fl->ifl_cidx, 1, "Consumer Index"); 6397 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6398 CTLFLAG_RD, 6399 &fl->ifl_credits, 1, "credits available"); 6400 #if MEMORY_LOGGING 6401 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6402 CTLFLAG_RD, 6403 &fl->ifl_m_enqueued, "mbufs allocated"); 6404 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6405 CTLFLAG_RD, 6406 &fl->ifl_m_dequeued, "mbufs freed"); 6407 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6408 CTLFLAG_RD, 6409 &fl->ifl_cl_enqueued, "clusters allocated"); 6410 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6411 CTLFLAG_RD, 6412 &fl->ifl_cl_dequeued, "clusters freed"); 6413 #endif 6414 6415 } 6416 } 6417 6418 } 6419 6420 void 6421 iflib_request_reset(if_ctx_t ctx) 6422 { 6423 6424 STATE_LOCK(ctx); 6425 ctx->ifc_flags |= IFC_DO_RESET; 6426 STATE_UNLOCK(ctx); 6427 } 6428 6429 #ifndef __NO_STRICT_ALIGNMENT 6430 static struct mbuf * 6431 iflib_fixup_rx(struct mbuf *m) 6432 { 6433 struct mbuf *n; 6434 6435 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6436 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6437 m->m_data += ETHER_HDR_LEN; 6438 n = m; 6439 } else { 6440 MGETHDR(n, M_NOWAIT, MT_DATA); 6441 if (n == NULL) { 6442 m_freem(m); 6443 return (NULL); 6444 } 6445 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6446 m->m_data += ETHER_HDR_LEN; 6447 m->m_len -= ETHER_HDR_LEN; 6448 n->m_len = ETHER_HDR_LEN; 6449 M_MOVE_PKTHDR(n, m); 6450 n->m_next = m; 6451 } 6452 return (n); 6453 } 6454 #endif 6455 6456 #ifdef NETDUMP 6457 static void 6458 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 6459 { 6460 if_ctx_t ctx; 6461 6462 ctx = if_getsoftc(ifp); 6463 CTX_LOCK(ctx); 6464 *nrxr = NRXQSETS(ctx); 6465 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6466 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6467 CTX_UNLOCK(ctx); 6468 } 6469 6470 static void 6471 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event) 6472 { 6473 if_ctx_t ctx; 6474 if_softc_ctx_t scctx; 6475 iflib_fl_t fl; 6476 iflib_rxq_t rxq; 6477 int i, j; 6478 6479 ctx = if_getsoftc(ifp); 6480 scctx = &ctx->ifc_softc_ctx; 6481 6482 switch (event) { 6483 case NETDUMP_START: 6484 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6485 rxq = &ctx->ifc_rxqs[i]; 6486 for (j = 0; j < rxq->ifr_nfl; j++) { 6487 fl = rxq->ifr_fl; 6488 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6489 } 6490 } 6491 iflib_no_tx_batch = 1; 6492 break; 6493 default: 6494 break; 6495 } 6496 } 6497 6498 static int 6499 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m) 6500 { 6501 if_ctx_t ctx; 6502 iflib_txq_t txq; 6503 int error; 6504 6505 ctx = if_getsoftc(ifp); 6506 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6507 IFF_DRV_RUNNING) 6508 return (EBUSY); 6509 6510 txq = &ctx->ifc_txqs[0]; 6511 error = iflib_encap(txq, &m); 6512 if (error == 0) 6513 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6514 return (error); 6515 } 6516 6517 static int 6518 iflib_netdump_poll(struct ifnet *ifp, int count) 6519 { 6520 if_ctx_t ctx; 6521 if_softc_ctx_t scctx; 6522 iflib_txq_t txq; 6523 int i; 6524 6525 ctx = if_getsoftc(ifp); 6526 scctx = &ctx->ifc_softc_ctx; 6527 6528 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6529 IFF_DRV_RUNNING) 6530 return (EBUSY); 6531 6532 txq = &ctx->ifc_txqs[0]; 6533 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6534 6535 for (i = 0; i < scctx->isc_nrxqsets; i++) 6536 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6537 return (0); 6538 } 6539 #endif /* NETDUMP */ 6540