1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include "opt_inet.h" 30 #include "opt_inet6.h" 31 #include "opt_acpi.h" 32 33 #include <sys/param.h> 34 #include <sys/types.h> 35 #include <sys/bus.h> 36 #include <sys/eventhandler.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/module.h> 41 #include <sys/kobj.h> 42 #include <sys/proc.h> 43 #include <sys/rman.h> 44 #include <sys/sbuf.h> 45 #include <sys/sched.h> 46 #include <sys/smp.h> 47 #include <sys/socket.h> 48 #include <sys/sockio.h> 49 #include <sys/sysctl.h> 50 #include <sys/syslog.h> 51 #include <sys/taskqueue.h> 52 #include <sys/limits.h> 53 54 #include <net/if.h> 55 #include <net/if_var.h> 56 #include <net/if_private.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/udp.h> 75 #include <netinet/ip_var.h> 76 #include <netinet6/ip6_var.h> 77 78 #include <machine/bus.h> 79 #include <machine/in_cksum.h> 80 81 #include <vm/vm.h> 82 #include <vm/pmap.h> 83 84 #include <dev/led/led.h> 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pci_private.h> 88 89 #include <net/iflib.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 /* 120 * File organization: 121 * - private structures 122 * - iflib private utility functions 123 * - ifnet functions 124 * - vlan registry and other exported functions 125 * - iflib public core functions 126 * 127 * 128 */ 129 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 130 131 #define IFLIB_RXEOF_MORE (1U << 0) 132 #define IFLIB_RXEOF_EMPTY (2U << 0) 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 static void iflib_tqg_detach(if_ctx_t ctx); 146 #ifndef ALTQ 147 static int iflib_simple_transmit(if_t ifp, struct mbuf *m); 148 #endif 149 150 typedef struct iflib_filter_info { 151 driver_filter_t *ifi_filter; 152 void *ifi_filter_arg; 153 struct grouptask *ifi_task; 154 void *ifi_ctx; 155 } *iflib_filter_info_t; 156 157 struct iflib_ctx { 158 KOBJ_FIELDS; 159 /* 160 * Pointer to hardware driver's softc 161 */ 162 void *ifc_softc; 163 device_t ifc_dev; 164 if_t ifc_ifp; 165 166 cpuset_t ifc_cpus; 167 if_shared_ctx_t ifc_sctx; 168 struct if_softc_ctx ifc_softc_ctx; 169 170 struct sx ifc_ctx_sx; 171 struct mtx ifc_state_mtx; 172 173 iflib_txq_t ifc_txqs; 174 iflib_rxq_t ifc_rxqs; 175 uint32_t ifc_if_flags; 176 uint32_t ifc_flags; 177 uint32_t ifc_max_fl_buf_size; 178 uint32_t ifc_rx_mbuf_sz; 179 180 int ifc_link_state; 181 uint32_t ifc_tx_watchdog_events; 182 struct cdev *ifc_led_dev; 183 int ifc_led_state; 184 struct resource *ifc_msix_mem; 185 186 struct if_irq ifc_legacy_irq; 187 struct task ifc_admin_task; 188 struct task ifc_led_task; 189 struct task ifc_vflr_task; 190 struct taskqueue *ifc_tq; 191 struct iflib_filter_info ifc_filter_info; 192 struct ifmedia ifc_media; 193 struct ifmedia *ifc_mediap; 194 195 struct sysctl_ctx_list ifc_sysctl_ctx; 196 struct sysctl_oid *ifc_sysctl_node; 197 uint16_t ifc_sysctl_ntxqs; 198 uint16_t ifc_sysctl_nrxqs; 199 uint16_t ifc_sysctl_qs_eq_override; 200 uint16_t ifc_sysctl_rx_budget; 201 uint16_t ifc_sysctl_tx_abdicate; 202 uint16_t ifc_sysctl_core_offset; 203 #define CORE_OFFSET_UNSPECIFIED 0xffff 204 uint8_t ifc_sysctl_separate_txrx; 205 uint8_t ifc_sysctl_use_logical_cores; 206 uint16_t ifc_sysctl_extra_msix_vectors; 207 bool ifc_cpus_are_physical_cores; 208 bool ifc_sysctl_simple_tx; 209 bool ifc_sysctl_tx_defer_mfree; 210 uint16_t ifc_sysctl_tx_reclaim_thresh; 211 uint16_t ifc_sysctl_tx_reclaim_ticks; 212 213 qidx_t ifc_sysctl_ntxds[8]; 214 qidx_t ifc_sysctl_nrxds[8]; 215 struct if_txrx ifc_txrx; 216 #define isc_txd_encap ifc_txrx.ift_txd_encap 217 #define isc_txd_flush ifc_txrx.ift_txd_flush 218 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 219 #define isc_rxd_available ifc_txrx.ift_rxd_available 220 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 221 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 222 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 223 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 224 #define isc_txq_select ifc_txrx.ift_txq_select 225 #define isc_txq_select_v2 ifc_txrx.ift_txq_select_v2 226 227 eventhandler_tag ifc_vlan_attach_event; 228 eventhandler_tag ifc_vlan_detach_event; 229 struct ether_addr ifc_mac; 230 }; 231 232 void * 233 iflib_get_softc(if_ctx_t ctx) 234 { 235 236 return (ctx->ifc_softc); 237 } 238 239 device_t 240 iflib_get_dev(if_ctx_t ctx) 241 { 242 243 return (ctx->ifc_dev); 244 } 245 246 if_t 247 iflib_get_ifp(if_ctx_t ctx) 248 { 249 250 return (ctx->ifc_ifp); 251 } 252 253 struct ifmedia * 254 iflib_get_media(if_ctx_t ctx) 255 { 256 257 return (ctx->ifc_mediap); 258 } 259 260 void 261 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 262 { 263 264 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 265 } 266 267 if_softc_ctx_t 268 iflib_get_softc_ctx(if_ctx_t ctx) 269 { 270 271 return (&ctx->ifc_softc_ctx); 272 } 273 274 if_shared_ctx_t 275 iflib_get_sctx(if_ctx_t ctx) 276 { 277 278 return (ctx->ifc_sctx); 279 } 280 281 uint16_t 282 iflib_get_extra_msix_vectors_sysctl(if_ctx_t ctx) 283 { 284 285 return (ctx->ifc_sysctl_extra_msix_vectors); 286 } 287 288 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 289 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE / sizeof(void *)) 290 #define CACHE_PTR_NEXT(ptr) ((void *)(roundup2(ptr, CACHE_LINE_SIZE))) 291 292 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 293 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 294 295 typedef struct iflib_sw_rx_desc_array { 296 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 297 struct mbuf **ifsd_m; /* pkthdr mbufs */ 298 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 299 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 300 } iflib_rxsd_array_t; 301 302 typedef struct iflib_sw_tx_desc_array { 303 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 304 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 305 struct mbuf **ifsd_m; /* pkthdr mbufs */ 306 struct mbuf **ifsd_m_defer; /* deferred mbuf ptr */ 307 struct mbuf **ifsd_m_deferb;/* deferred mbuf backing ptr */ 308 } if_txsd_vec_t; 309 310 /* magic number that should be high enough for any hardware */ 311 #define IFLIB_MAX_TX_SEGS 128 312 #define IFLIB_RX_COPY_THRESH 128 313 #define IFLIB_MAX_RX_REFRESH 32 314 /* The minimum descriptors per second before we start coalescing */ 315 #define IFLIB_MIN_DESC_SEC 16384 316 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 317 /* maximum number of txqs that can share an rx interrupt */ 318 #define IFLIB_MAX_TX_SHARED_INTR 4 319 320 /* this should really scale with ring size - this is a fairly arbitrary value */ 321 #define TX_BATCH_SIZE 32 322 323 #define IFLIB_RESTART_BUDGET 8 324 325 326 /* 327 * Encode TSO or !TSO in the low bits of the tx ifsd_m pointer so as 328 * to avoid defref'ing the mbuf to determine the correct busdma resources 329 * to release 330 */ 331 #define IFLIB_TSO (1ULL << 0) 332 #define IFLIB_NO_TSO (2ULL << 0) 333 #define IFLIB_FLAGS_MASK (0x3ULL) 334 #define IFLIB_SAVE_MBUF(mbuf, flags) ((void *)(((uintptr_t)mbuf) | flags)) 335 #define IFLIB_GET_FLAGS(a) ((uintptr_t)a & IFLIB_FLAGS_MASK) 336 #define IFLIB_GET_MBUF(a) ((struct mbuf *)((uintptr_t)a & ~IFLIB_FLAGS_MASK)) 337 338 339 #define IFC_LEGACY 0x001 340 #define IFC_QFLUSH 0x002 341 #define IFC_MULTISEG 0x004 342 #define IFC_INIT_FAILED 0x008 343 #define IFC_SC_ALLOCATED 0x010 344 #define IFC_INIT_DONE 0x020 345 #define IFC_PREFETCH 0x040 346 #define IFC_DO_RESET 0x080 347 #define IFC_DO_WATCHDOG 0x100 348 #define IFC_DO_RESET_IF_UP 0x200 349 #define IFC_SPARE2 0x400 350 #define IFC_IN_DETACH 0x800 351 352 #define IFC_NETMAP_TX_IRQ 0x80000000 353 354 #define CSUM_OFFLOAD (CSUM_IP_TSO | CSUM_IP6_TSO | CSUM_IP | \ 355 CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_SCTP | \ 356 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_SCTP) 357 358 struct iflib_txq { 359 qidx_t ift_in_use; 360 qidx_t ift_cidx; 361 qidx_t ift_cidx_processed; 362 qidx_t ift_pidx; 363 uint8_t ift_gen; 364 uint8_t ift_br_offset:1, 365 ift_defer_mfree:1, 366 ift_spare_bits0:6; 367 uint16_t ift_npending; 368 uint16_t ift_db_pending; 369 uint16_t ift_rs_pending; 370 uint32_t ift_last_reclaim; 371 uint16_t ift_reclaim_thresh; 372 uint16_t ift_reclaim_ticks; 373 uint8_t ift_txd_size[8]; 374 uint64_t ift_processed; 375 uint64_t ift_cleaned; 376 uint64_t ift_processed_prev; 377 #if MEMORY_LOGGING 378 uint64_t ift_enqueued; 379 uint64_t ift_dequeued; 380 #endif 381 uint64_t ift_no_tx_dma_setup; 382 uint64_t ift_no_desc_avail; 383 uint64_t ift_mbuf_defrag_failed; 384 uint64_t ift_mbuf_defrag; 385 uint64_t ift_map_failed; 386 uint64_t ift_txd_encap_efbig; 387 uint64_t ift_pullups; 388 uint64_t ift_last_timer_tick; 389 390 struct mtx ift_mtx; 391 struct mtx ift_db_mtx; 392 393 /* constant values */ 394 if_ctx_t ift_ctx; 395 struct ifmp_ring *ift_br; 396 struct grouptask ift_task; 397 qidx_t ift_size; 398 qidx_t ift_pad; 399 uint16_t ift_id; 400 struct callout ift_timer; 401 #ifdef DEV_NETMAP 402 struct callout ift_netmap_timer; 403 #endif /* DEV_NETMAP */ 404 405 if_txsd_vec_t ift_sds; 406 /* 407 * TX watchdog state, updated once per iflib_timer period. The 408 * period count saturates instead of wrapping, and is 16 bits 409 * wide so that it still reaches any value 410 * net.iflib.tx_watchdog_periods is plausibly set to; an 8-bit 411 * counter would silently disable the check for a threshold 412 * above 255. 413 */ 414 qidx_t ift_outstanding_prev; 415 uint16_t ift_wdog_armed; 416 uint8_t ift_closed; 417 uint8_t ift_update_freq; 418 uint8_t ift_spare0[2]; /* pad to the next pointer boundary */ 419 struct iflib_filter_info ift_filter_info; 420 bus_dma_tag_t ift_buf_tag; 421 bus_dma_tag_t ift_tso_buf_tag; 422 iflib_dma_info_t ift_ifdi; 423 #define MTX_NAME_LEN 32 424 char ift_mtx_name[MTX_NAME_LEN]; 425 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 426 #ifdef IFLIB_DIAGNOSTICS 427 uint64_t ift_cpu_exec_count[256]; 428 #endif 429 } __aligned(CACHE_LINE_SIZE); 430 431 struct iflib_fl { 432 qidx_t ifl_cidx; 433 qidx_t ifl_pidx; 434 qidx_t ifl_credits; 435 uint8_t ifl_gen; 436 uint8_t ifl_rxd_size; 437 #if MEMORY_LOGGING 438 uint64_t ifl_m_enqueued; 439 uint64_t ifl_m_dequeued; 440 uint64_t ifl_cl_enqueued; 441 uint64_t ifl_cl_dequeued; 442 #endif 443 /* implicit pad */ 444 bitstr_t *ifl_rx_bitmap; 445 qidx_t ifl_fragidx; 446 /* constant */ 447 qidx_t ifl_size; 448 uint16_t ifl_buf_size; 449 uint16_t ifl_cltype; 450 uma_zone_t ifl_zone; 451 iflib_rxsd_array_t ifl_sds; 452 iflib_rxq_t ifl_rxq; 453 uint8_t ifl_id; 454 bus_dma_tag_t ifl_buf_tag; 455 iflib_dma_info_t ifl_ifdi; 456 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 457 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 458 } __aligned(CACHE_LINE_SIZE); 459 460 static inline qidx_t 461 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 462 { 463 qidx_t used; 464 465 if (pidx > cidx) 466 used = pidx - cidx; 467 else if (pidx < cidx) 468 used = size - cidx + pidx; 469 else if (gen == 0 && pidx == cidx) 470 used = 0; 471 else if (gen == 1 && pidx == cidx) 472 used = size; 473 else 474 panic("bad state"); 475 476 return (used); 477 } 478 479 #define TXQ_AVAIL(txq) ((txq->ift_size - txq->ift_pad) -\ 480 get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 481 482 #define IDXDIFF(head, tail, wrap) \ 483 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 484 485 struct iflib_rxq { 486 if_ctx_t ifr_ctx; 487 iflib_fl_t ifr_fl; 488 struct pfil_head *pfil; 489 /* 490 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 491 * the completion queue consumer index. Otherwise it's unused. 492 */ 493 qidx_t ifr_cq_cidx; 494 uint16_t ifr_id; 495 uint8_t ifr_nfl; 496 uint8_t ifr_ntxqirq; 497 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 498 uint8_t ifr_fl_offset; 499 struct lro_ctrl ifr_lc; 500 struct grouptask ifr_task; 501 struct callout ifr_watchdog; 502 struct iflib_filter_info ifr_filter_info; 503 iflib_dma_info_t ifr_ifdi; 504 505 /* dynamically allocate if any drivers need a value substantially larger than this */ 506 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 507 #ifdef IFLIB_DIAGNOSTICS 508 uint64_t ifr_cpu_exec_count[256]; 509 #endif 510 } __aligned(CACHE_LINE_SIZE); 511 512 typedef struct if_rxsd { 513 caddr_t *ifsd_cl; 514 iflib_fl_t ifsd_fl; 515 } *if_rxsd_t; 516 517 /* 518 * Only allow a single packet to take up most 1/nth of the tx ring 519 */ 520 #define MAX_SINGLE_PACKET_FRACTION 12 521 #define IF_BAD_DMA ((bus_addr_t)-1) 522 523 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 524 525 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 526 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 527 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 528 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 529 530 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 531 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 532 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 533 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 534 535 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 536 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 537 538 /* Our boot-time initialization hook */ 539 static int iflib_module_event_handler(module_t, int, void *); 540 541 static moduledata_t iflib_moduledata = { 542 "iflib", 543 iflib_module_event_handler, 544 NULL 545 }; 546 547 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 548 MODULE_VERSION(iflib, 1); 549 550 MODULE_DEPEND(iflib, pci, 1, 1, 1); 551 MODULE_DEPEND(iflib, ether, 1, 1, 1); 552 553 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 554 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 555 556 #ifndef IFLIB_DEBUG_COUNTERS 557 #ifdef INVARIANTS 558 #define IFLIB_DEBUG_COUNTERS 1 559 #else 560 #define IFLIB_DEBUG_COUNTERS 0 561 #endif /* !INVARIANTS */ 562 #endif 563 564 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 565 "iflib driver parameters"); 566 567 /* 568 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 569 */ 570 static int iflib_min_tx_latency = 0; 571 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 572 &iflib_min_tx_latency, 0, 573 "minimize transmit latency at the possible expense of throughput"); 574 static int iflib_no_tx_batch = 0; 575 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 576 &iflib_no_tx_batch, 0, 577 "minimize transmit latency at the possible expense of throughput"); 578 static int iflib_timer_default = 1000; 579 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW, 580 &iflib_timer_default, 0, "number of ticks between iflib_timer calls"); 581 /* 582 * Consecutive timer periods a TX queue must stay frozen - see 583 * iflib_timer(), which defines that state - before the hardware is 584 * asked whether it has completions pending. Four periods is roughly 585 * two seconds with the default timer interval: a healthy queue on 586 * hardware that coalesces completion reports (e.g. 8254x, 587 * TXDCTL.WTHRESH) stays frozen for at most two (measured on 82541PI), 588 * a wedged one until it is reset. 589 */ 590 static int iflib_tx_watchdog_periods = 4; 591 SYSCTL_INT(_net_iflib, OID_AUTO, tx_watchdog_periods, CTLFLAG_RWTUN, 592 &iflib_tx_watchdog_periods, 0, 593 "consecutive frozen timer periods before a TX queue is checked for " 594 "a hang (0 disables the check)"); 595 596 597 #if IFLIB_DEBUG_COUNTERS 598 599 static int iflib_tx_seen; 600 static int iflib_tx_sent; 601 static int iflib_tx_encap; 602 static int iflib_rx_allocs; 603 static int iflib_fl_refills; 604 static int iflib_fl_refills_large; 605 static int iflib_tx_frees; 606 607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, &iflib_tx_seen, 0, 608 "# TX mbufs seen"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, &iflib_tx_sent, 0, 610 "# TX mbufs sent"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, &iflib_tx_encap, 0, 612 "# TX mbufs encapped"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, &iflib_tx_frees, 0, 614 "# TX frees"); 615 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, &iflib_rx_allocs, 0, 616 "# RX allocations"); 617 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, &iflib_fl_refills, 0, 618 "# refills"); 619 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 620 &iflib_fl_refills_large, 0, "# large refills"); 621 622 static int iflib_txq_drain_flushing; 623 static int iflib_txq_drain_oactive; 624 static int iflib_txq_drain_notready; 625 626 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 627 &iflib_txq_drain_flushing, 0, "# drain flushes"); 628 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 629 &iflib_txq_drain_oactive, 0, "# drain oactives"); 630 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 631 &iflib_txq_drain_notready, 0, "# drain notready"); 632 633 static int iflib_encap_load_mbuf_fail; 634 static int iflib_encap_pad_mbuf_fail; 635 static int iflib_encap_txq_avail_fail; 636 static int iflib_encap_txd_encap_fail; 637 638 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 639 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 640 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 641 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 642 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 643 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 644 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 645 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 646 647 static int iflib_task_fn_rxs; 648 static int iflib_rx_intr_enables; 649 static int iflib_fast_intrs; 650 static int iflib_rx_unavail; 651 static int iflib_rx_ctx_inactive; 652 static int iflib_rx_if_input; 653 static int iflib_rxd_flush; 654 655 static int iflib_verbose_debug; 656 657 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, &iflib_task_fn_rxs, 0, 658 "# task_fn_rx calls"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 660 &iflib_rx_intr_enables, 0, "# RX intr enables"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, &iflib_fast_intrs, 0, 662 "# fast_intr calls"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, &iflib_rx_unavail, 0, 664 "# times rxeof called with no available data"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 666 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, &iflib_rx_if_input, 668 0, "# times rxeof called if_input"); 669 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, &iflib_rxd_flush, 0, 670 "# times rxd_flush called"); 671 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 672 &iflib_verbose_debug, 0, "enable verbose debugging"); 673 674 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 675 static void 676 iflib_debug_reset(void) 677 { 678 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 679 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 680 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 681 iflib_txq_drain_notready = 682 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 683 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 684 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 685 iflib_rx_unavail = 686 iflib_rx_ctx_inactive = iflib_rx_if_input = 687 iflib_rxd_flush = 0; 688 } 689 690 #else 691 #define DBG_COUNTER_INC(name) 692 static void iflib_debug_reset(void) {} 693 #endif 694 695 #define IFLIB_DEBUG 0 696 697 static void iflib_tx_structures_free(if_ctx_t ctx); 698 static void iflib_rx_structures_free(if_ctx_t ctx); 699 static int iflib_queues_alloc(if_ctx_t ctx); 700 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 701 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 702 static int iflib_qset_structures_setup(if_ctx_t ctx); 703 static int iflib_msix_init(if_ctx_t ctx); 704 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 705 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 706 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 707 #ifdef ALTQ 708 static void iflib_altq_if_start(if_t ifp); 709 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 710 #endif 711 static void iflib_register(if_ctx_t); 712 static void iflib_deregister(if_ctx_t); 713 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 714 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 715 static void iflib_init_locked(if_ctx_t ctx); 716 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 717 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 718 static void iflib_ifmp_purge(iflib_txq_t txq); 719 static void _iflib_pre_assert(if_softc_ctx_t scctx); 720 static void iflib_stop(if_ctx_t ctx); 721 static void iflib_if_init_locked(if_ctx_t ctx); 722 static void iflib_free_intr_mem(if_ctx_t ctx); 723 #ifndef __NO_STRICT_ALIGNMENT 724 static struct mbuf *iflib_fixup_rx(struct mbuf *m); 725 #endif 726 static __inline int iflib_completed_tx_reclaim(iflib_txq_t txq, 727 struct mbuf **m_defer); 728 static __inline void iflib_completed_tx_reclaim_force(iflib_txq_t txq); 729 730 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 731 SLIST_HEAD_INITIALIZER(cpu_offsets); 732 struct cpu_offset { 733 SLIST_ENTRY(cpu_offset) entries; 734 cpuset_t set; 735 unsigned int refcount; 736 uint16_t next_cpuid; 737 }; 738 static struct mtx cpu_offset_mtx; 739 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 740 MTX_DEF); 741 742 DEBUGNET_DEFINE(iflib); 743 744 static int 745 iflib_num_rx_descs(if_ctx_t ctx) 746 { 747 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 748 if_shared_ctx_t sctx = ctx->ifc_sctx; 749 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 750 751 return (scctx->isc_nrxd[first_rxq]); 752 } 753 754 static int 755 iflib_num_tx_descs(if_ctx_t ctx) 756 { 757 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 758 if_shared_ctx_t sctx = ctx->ifc_sctx; 759 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 760 761 return (scctx->isc_ntxd[first_txq]); 762 } 763 764 #ifdef DEV_NETMAP 765 #include <sys/selinfo.h> 766 #include <net/netmap.h> 767 #include <dev/netmap/netmap_kern.h> 768 769 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 770 771 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 772 static void iflib_netmap_timer(void *arg); 773 774 /* 775 * device-specific sysctl variables: 776 * 777 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 778 * During regular operations the CRC is stripped, but on some 779 * hardware reception of frames not multiple of 64 is slower, 780 * so using crcstrip=0 helps in benchmarks. 781 * 782 * iflib_rx_miss, iflib_rx_miss_bufs: 783 * count packets that might be missed due to lost interrupts. 784 */ 785 SYSCTL_DECL(_dev_netmap); 786 /* 787 * The xl driver by default strips CRCs and we do not override it. 788 */ 789 790 int iflib_crcstrip = 1; 791 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 792 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 793 794 int iflib_rx_miss, iflib_rx_miss_bufs; 795 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 796 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 797 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 798 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 799 800 /* 801 * Register/unregister. We are already under netmap lock. 802 * Only called on the first register or the last unregister. 803 */ 804 static int 805 iflib_netmap_register(struct netmap_adapter *na, int onoff) 806 { 807 if_t ifp = na->ifp; 808 if_ctx_t ctx = if_getsoftc(ifp); 809 int status; 810 811 CTX_LOCK(ctx); 812 if (!CTX_IS_VF(ctx)) 813 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 814 815 iflib_stop(ctx); 816 817 /* 818 * Enable (or disable) netmap flags, and intercept (or restore) 819 * ifp->if_transmit. This is done once the device has been stopped 820 * to prevent race conditions. Also, this must be done after 821 * calling netmap_disable_all_rings() and before calling 822 * netmap_enable_all_rings(), so that these two functions see the 823 * updated state of the NAF_NETMAP_ON bit. 824 */ 825 if (onoff) { 826 nm_set_native_flags(na); 827 } else { 828 nm_clear_native_flags(na); 829 } 830 831 iflib_init_locked(ctx); 832 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 833 status = if_getdrvflags(ifp) & IFF_DRV_RUNNING ? 0 : 1; 834 if (status) 835 nm_clear_native_flags(na); 836 CTX_UNLOCK(ctx); 837 return (status); 838 } 839 840 static int 841 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info) 842 { 843 if_t ifp = na->ifp; 844 if_ctx_t ctx = if_getsoftc(ifp); 845 iflib_rxq_t rxq = &ctx->ifc_rxqs[0]; 846 iflib_fl_t fl = &rxq->ifr_fl[0]; 847 848 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 849 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 850 info->num_tx_descs = iflib_num_tx_descs(ctx); 851 info->num_rx_descs = iflib_num_rx_descs(ctx); 852 info->rx_buf_maxsize = fl->ifl_buf_size; 853 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u", 854 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs, 855 info->num_rx_descs, info->rx_buf_maxsize); 856 857 return (0); 858 } 859 860 static int 861 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 862 { 863 struct netmap_adapter *na = kring->na; 864 u_int const lim = kring->nkr_num_slots - 1; 865 struct netmap_ring *ring = kring->ring; 866 bus_dmamap_t *map; 867 struct if_rxd_update iru; 868 if_ctx_t ctx = rxq->ifr_ctx; 869 iflib_fl_t fl = &rxq->ifr_fl[0]; 870 u_int nic_i_first, nic_i; 871 u_int nm_i; 872 int i, n; 873 #if IFLIB_DEBUG_COUNTERS 874 int rf_count = 0; 875 #endif 876 877 /* 878 * This function is used both at initialization and in rxsync. 879 * At initialization we need to prepare (with isc_rxd_refill()) 880 * all the netmap buffers currently owned by the kernel, in 881 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync 882 * (except for kring->nkr_hwofs). These may be less than 883 * kring->nkr_num_slots if netmap_reset() was called while 884 * an application using the kring that still owned some 885 * buffers. 886 * At rxsync time, both indexes point to the next buffer to be 887 * refilled. 888 * In any case we publish (with isc_rxd_flush()) up to 889 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 890 * pointer to overrun the head/cons pointer, although this is 891 * not necessary for some NICs (e.g. vmx). 892 */ 893 if (__predict_false(init)) { 894 n = kring->nkr_num_slots - nm_kr_rxspace(kring); 895 } else { 896 n = kring->rhead - kring->nr_hwcur; 897 if (n == 0) 898 return (0); /* Nothing to do. */ 899 if (n < 0) 900 n += kring->nkr_num_slots; 901 } 902 903 iru_init(&iru, rxq, 0 /* flid */); 904 map = fl->ifl_sds.ifsd_map; 905 nic_i = fl->ifl_pidx; 906 nm_i = netmap_idx_n2k(kring, nic_i); 907 if (__predict_false(init)) { 908 /* 909 * On init/reset, nic_i must be 0, and we must 910 * start to refill from hwtail (see netmap_reset()). 911 */ 912 MPASS(nic_i == 0); 913 MPASS(nm_i == kring->nr_hwtail); 914 } else 915 MPASS(nm_i == kring->nr_hwcur); 916 DBG_COUNTER_INC(fl_refills); 917 while (n > 0) { 918 #if IFLIB_DEBUG_COUNTERS 919 if (++rf_count == 9) 920 DBG_COUNTER_INC(fl_refills_large); 921 #endif 922 nic_i_first = nic_i; 923 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 924 struct netmap_slot *slot = &ring->slot[nm_i]; 925 uint64_t paddr; 926 void *addr = PNMB(na, slot, &paddr); 927 928 MPASS(i < IFLIB_MAX_RX_REFRESH); 929 930 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 931 return (netmap_ring_reinit(kring)); 932 933 fl->ifl_bus_addrs[i] = paddr + 934 nm_get_offset(kring, slot); 935 fl->ifl_rxd_idxs[i] = nic_i; 936 937 if (__predict_false(init)) { 938 netmap_load_map(na, fl->ifl_buf_tag, 939 map[nic_i], addr); 940 } else if (slot->flags & NS_BUF_CHANGED) { 941 /* buffer has changed, reload map */ 942 netmap_reload_map(na, fl->ifl_buf_tag, 943 map[nic_i], addr); 944 } 945 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 946 BUS_DMASYNC_PREREAD); 947 slot->flags &= ~NS_BUF_CHANGED; 948 949 nm_i = nm_next(nm_i, lim); 950 nic_i = nm_next(nic_i, lim); 951 } 952 953 iru.iru_pidx = nic_i_first; 954 iru.iru_count = i; 955 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 956 } 957 fl->ifl_pidx = nic_i; 958 /* 959 * At the end of the loop we must have refilled everything 960 * we could possibly refill. 961 */ 962 MPASS(nm_i == kring->rhead); 963 kring->nr_hwcur = nm_i; 964 965 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 966 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 967 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 968 nm_prev(nic_i, lim)); 969 DBG_COUNTER_INC(rxd_flush); 970 971 return (0); 972 } 973 974 #define NETMAP_TX_TIMER_US 90 975 976 /* 977 * Reconcile kernel and user view of the transmit ring. 978 * 979 * All information is in the kring. 980 * Userspace wants to send packets up to the one before kring->rhead, 981 * kernel knows kring->nr_hwcur is the first unsent packet. 982 * 983 * Here we push packets out (as many as possible), and possibly 984 * reclaim buffers from previously completed transmission. 985 * 986 * The caller (netmap) guarantees that there is only one instance 987 * running at any time. Any interference with other driver 988 * methods should be handled by the individual drivers. 989 */ 990 static int 991 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 992 { 993 struct netmap_adapter *na = kring->na; 994 if_t ifp = na->ifp; 995 struct netmap_ring *ring = kring->ring; 996 u_int nm_i; /* index into the netmap kring */ 997 u_int nic_i; /* index into the NIC ring */ 998 u_int const lim = kring->nkr_num_slots - 1; 999 u_int const head = kring->rhead; 1000 struct if_pkt_info pi; 1001 int tx_pkts = 0, tx_bytes = 0; 1002 1003 /* 1004 * interrupts on every tx packet are expensive so request 1005 * them every half ring, or where NS_REPORT is set 1006 */ 1007 u_int report_frequency = kring->nkr_num_slots >> 1; 1008 /* device-specific */ 1009 if_ctx_t ctx = if_getsoftc(ifp); 1010 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 1011 1012 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1013 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1014 1015 /* 1016 * First part: process new packets to send. 1017 * nm_i is the current index in the netmap kring, 1018 * nic_i is the corresponding index in the NIC ring. 1019 * 1020 * If we have packets to send (nm_i != head) 1021 * iterate over the netmap ring, fetch length and update 1022 * the corresponding slot in the NIC ring. Some drivers also 1023 * need to update the buffer's physical address in the NIC slot 1024 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 1025 * 1026 * The netmap_reload_map() calls is especially expensive, 1027 * even when (as in this case) the tag is 0, so do only 1028 * when the buffer has actually changed. 1029 * 1030 * If possible do not set the report/intr bit on all slots, 1031 * but only a few times per ring or when NS_REPORT is set. 1032 * 1033 * Finally, on 10G and faster drivers, it might be useful 1034 * to prefetch the next slot and txr entry. 1035 */ 1036 1037 nm_i = kring->nr_hwcur; 1038 if (nm_i != head) { /* we have new packets to send */ 1039 uint32_t pkt_len = 0, seg_idx = 0; 1040 int nic_i_start = -1, flags = 0; 1041 memset(&pi, 0, sizeof(pi)); 1042 pi.ipi_segs = txq->ift_segs; 1043 pi.ipi_qsidx = kring->ring_id; 1044 nic_i = netmap_idx_k2n(kring, nm_i); 1045 1046 __builtin_prefetch(&ring->slot[nm_i]); 1047 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 1048 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 1049 1050 while (nm_i != head) { 1051 struct netmap_slot *slot = &ring->slot[nm_i]; 1052 uint64_t offset = nm_get_offset(kring, slot); 1053 u_int len = slot->len; 1054 uint64_t paddr; 1055 void *addr = PNMB(na, slot, &paddr); 1056 1057 flags |= (slot->flags & NS_REPORT || 1058 nic_i == 0 || nic_i == report_frequency) ? 1059 IPI_TX_INTR : 0; 1060 1061 /* 1062 * If this is the first packet fragment, save the 1063 * index of the first NIC slot for later. 1064 */ 1065 if (nic_i_start < 0) 1066 nic_i_start = nic_i; 1067 1068 pi.ipi_segs[seg_idx].ds_addr = paddr + offset; 1069 pi.ipi_segs[seg_idx].ds_len = len; 1070 if (len) { 1071 pkt_len += len; 1072 seg_idx++; 1073 } 1074 1075 if (!(slot->flags & NS_MOREFRAG)) { 1076 pi.ipi_len = pkt_len; 1077 pi.ipi_nsegs = seg_idx; 1078 pi.ipi_pidx = nic_i_start; 1079 pi.ipi_ndescs = 0; 1080 pi.ipi_flags = flags; 1081 1082 /* Prepare the NIC TX ring. */ 1083 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1084 DBG_COUNTER_INC(tx_encap); 1085 1086 /* Update transmit counters */ 1087 tx_bytes += pi.ipi_len; 1088 tx_pkts++; 1089 1090 /* Reinit per-packet info for the next one. */ 1091 flags = seg_idx = pkt_len = 0; 1092 nic_i_start = -1; 1093 } 1094 1095 /* prefetch for next round */ 1096 __builtin_prefetch(&ring->slot[nm_i + 1]); 1097 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1098 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1099 1100 NM_CHECK_ADDR_LEN_OFF(na, len, offset); 1101 1102 if (slot->flags & NS_BUF_CHANGED) { 1103 /* buffer has changed, reload map */ 1104 netmap_reload_map(na, txq->ift_buf_tag, 1105 txq->ift_sds.ifsd_map[nic_i], addr); 1106 } 1107 /* make sure changes to the buffer are synced */ 1108 bus_dmamap_sync(txq->ift_buf_tag, 1109 txq->ift_sds.ifsd_map[nic_i], 1110 BUS_DMASYNC_PREWRITE); 1111 1112 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG); 1113 nm_i = nm_next(nm_i, lim); 1114 nic_i = nm_next(nic_i, lim); 1115 } 1116 kring->nr_hwcur = nm_i; 1117 1118 /* synchronize the NIC ring */ 1119 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1120 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1121 1122 /* (re)start the tx unit up to slot nic_i (excluded) */ 1123 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1124 } 1125 1126 /* 1127 * Second part: reclaim buffers for completed transmissions. 1128 * 1129 * If there are unclaimed buffers, attempt to reclaim them. 1130 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1131 * trigger a per-tx-queue timer to try again later. 1132 */ 1133 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1134 if (iflib_tx_credits_update(ctx, txq)) { 1135 /* some tx completed, increment avail */ 1136 nic_i = txq->ift_cidx_processed; 1137 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1138 } 1139 } 1140 1141 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1142 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1143 callout_reset_sbt_on(&txq->ift_netmap_timer, 1144 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1145 iflib_netmap_timer, txq, 1146 txq->ift_netmap_timer.c_cpu, 0); 1147 } 1148 1149 if_inc_counter(ifp, IFCOUNTER_OBYTES, tx_bytes); 1150 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tx_pkts); 1151 1152 return (0); 1153 } 1154 1155 /* 1156 * Reconcile kernel and user view of the receive ring. 1157 * Same as for the txsync, this routine must be efficient. 1158 * The caller guarantees a single invocations, but races against 1159 * the rest of the driver should be handled here. 1160 * 1161 * On call, kring->rhead is the first packet that userspace wants 1162 * to keep, and kring->rcur is the wakeup point. 1163 * The kernel has previously reported packets up to kring->rtail. 1164 * 1165 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1166 * of whether or not we received an interrupt. 1167 */ 1168 static int 1169 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1170 { 1171 struct netmap_adapter *na = kring->na; 1172 struct netmap_ring *ring = kring->ring; 1173 if_t ifp = na->ifp; 1174 uint32_t nm_i; /* index into the netmap ring */ 1175 uint32_t nic_i; /* index into the NIC ring */ 1176 u_int n; 1177 u_int const lim = kring->nkr_num_slots - 1; 1178 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1179 int i = 0, rx_bytes = 0, rx_pkts = 0; 1180 1181 if_ctx_t ctx = if_getsoftc(ifp); 1182 if_shared_ctx_t sctx = ctx->ifc_sctx; 1183 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1184 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1185 iflib_fl_t fl = &rxq->ifr_fl[0]; 1186 struct if_rxd_info ri; 1187 qidx_t *cidxp; 1188 1189 /* 1190 * netmap only uses free list 0, to avoid out of order consumption 1191 * of receive buffers 1192 */ 1193 1194 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1195 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1196 1197 /* 1198 * First part: import newly received packets. 1199 * 1200 * nm_i is the index of the next free slot in the netmap ring, 1201 * nic_i is the index of the next received packet in the NIC ring 1202 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1203 * differ in case if_init() has been called while 1204 * in netmap mode. For the receive ring we have 1205 * 1206 * nic_i = fl->ifl_cidx; 1207 * nm_i = kring->nr_hwtail (previous) 1208 * and 1209 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1210 * 1211 * fl->ifl_cidx is set to 0 on a ring reinit 1212 */ 1213 if (netmap_no_pendintr || force_update) { 1214 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1215 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1216 int crclen = iflib_crcstrip ? 0 : 4; 1217 int error, avail; 1218 1219 /* 1220 * For the free list consumer index, we use the same 1221 * logic as in iflib_rxeof(). 1222 */ 1223 if (have_rxcq) 1224 cidxp = &rxq->ifr_cq_cidx; 1225 else 1226 cidxp = &fl->ifl_cidx; 1227 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1228 rxq->ifr_id, *cidxp, USHRT_MAX); 1229 1230 nic_i = fl->ifl_cidx; 1231 nm_i = netmap_idx_n2k(kring, nic_i); 1232 MPASS(nm_i == kring->nr_hwtail); 1233 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1234 memset(&ri, 0, sizeof(ri)); 1235 ri.iri_frags = rxq->ifr_frags; 1236 ri.iri_qsidx = kring->ring_id; 1237 ri.iri_ifp = ctx->ifc_ifp; 1238 ri.iri_cidx = *cidxp; 1239 1240 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1241 for (i = 0; i < ri.iri_nfrags; i++) { 1242 if (error) { 1243 ring->slot[nm_i].len = 0; 1244 ring->slot[nm_i].flags = 0; 1245 } else { 1246 ring->slot[nm_i].len = ri.iri_frags[i].irf_len; 1247 if (i == (ri.iri_nfrags - 1)) { 1248 ring->slot[nm_i].len -= crclen; 1249 ring->slot[nm_i].flags = 0; 1250 1251 /* Update receive counters */ 1252 rx_bytes += ri.iri_len; 1253 rx_pkts++; 1254 } else 1255 ring->slot[nm_i].flags = NS_MOREFRAG; 1256 } 1257 1258 bus_dmamap_sync(fl->ifl_buf_tag, 1259 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1260 nm_i = nm_next(nm_i, lim); 1261 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1262 } 1263 1264 if (have_rxcq) { 1265 *cidxp = ri.iri_cidx; 1266 while (*cidxp >= scctx->isc_nrxd[0]) 1267 *cidxp -= scctx->isc_nrxd[0]; 1268 } 1269 1270 } 1271 if (n) { /* update the state variables */ 1272 if (netmap_no_pendintr && !force_update) { 1273 /* diagnostics */ 1274 iflib_rx_miss++; 1275 iflib_rx_miss_bufs += n; 1276 } 1277 kring->nr_hwtail = nm_i; 1278 } 1279 kring->nr_kflags &= ~NKR_PENDINTR; 1280 } 1281 /* 1282 * Second part: skip past packets that userspace has released. 1283 * (kring->nr_hwcur to head excluded), 1284 * and make the buffers available for reception. 1285 * As usual nm_i is the index in the netmap ring, 1286 * nic_i is the index in the NIC ring, and 1287 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1288 */ 1289 netmap_fl_refill(rxq, kring, false); 1290 1291 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 1292 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 1293 1294 return (0); 1295 } 1296 1297 static void 1298 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1299 { 1300 if_ctx_t ctx = if_getsoftc(na->ifp); 1301 1302 CTX_LOCK(ctx); 1303 if (onoff) { 1304 IFDI_INTR_ENABLE(ctx); 1305 } else { 1306 IFDI_INTR_DISABLE(ctx); 1307 } 1308 CTX_UNLOCK(ctx); 1309 } 1310 1311 static int 1312 iflib_netmap_attach(if_ctx_t ctx) 1313 { 1314 struct netmap_adapter na; 1315 1316 bzero(&na, sizeof(na)); 1317 1318 na.ifp = ctx->ifc_ifp; 1319 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS; 1320 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1321 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1322 1323 na.num_tx_desc = iflib_num_tx_descs(ctx); 1324 na.num_rx_desc = iflib_num_rx_descs(ctx); 1325 na.nm_txsync = iflib_netmap_txsync; 1326 na.nm_rxsync = iflib_netmap_rxsync; 1327 na.nm_register = iflib_netmap_register; 1328 na.nm_intr = iflib_netmap_intr; 1329 na.nm_config = iflib_netmap_config; 1330 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1331 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1332 return (netmap_attach(&na)); 1333 } 1334 1335 static int 1336 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1337 { 1338 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1339 struct netmap_slot *slot; 1340 1341 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1342 if (slot == NULL) 1343 return (0); 1344 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1345 /* 1346 * In netmap mode, set the map for the packet buffer. 1347 * NOTE: Some drivers (not this one) also need to set 1348 * the physical buffer address in the NIC ring. 1349 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1350 * netmap slot index, si 1351 */ 1352 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1353 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1354 NMB(na, slot + si)); 1355 } 1356 return (1); 1357 } 1358 1359 static int 1360 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1361 { 1362 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1363 struct netmap_kring *kring; 1364 struct netmap_slot *slot; 1365 1366 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1367 if (slot == NULL) 1368 return (0); 1369 kring = na->rx_rings[rxq->ifr_id]; 1370 netmap_fl_refill(rxq, kring, true); 1371 return (1); 1372 } 1373 1374 static void 1375 iflib_netmap_timer(void *arg) 1376 { 1377 iflib_txq_t txq = arg; 1378 if_ctx_t ctx = txq->ift_ctx; 1379 1380 /* 1381 * Wake up the netmap application, to give it a chance to 1382 * call txsync and reclaim more completed TX buffers. 1383 */ 1384 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1385 } 1386 1387 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1388 1389 #else 1390 #define iflib_netmap_txq_init(ctx, txq) (0) 1391 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1392 #define iflib_netmap_detach(ifp) 1393 #define netmap_enable_all_rings(ifp) 1394 #define netmap_disable_all_rings(ifp) 1395 1396 #define iflib_netmap_attach(ctx) (0) 1397 #define netmap_rx_irq(ifp, qid, budget) (0) 1398 #endif 1399 1400 #if defined(__i386__) || defined(__amd64__) 1401 static __inline void 1402 prefetch(void *x) 1403 { 1404 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1405 } 1406 1407 static __inline void 1408 prefetch2cachelines(void *x) 1409 { 1410 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1411 #if (CACHE_LINE_SIZE < 128) 1412 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x) + CACHE_LINE_SIZE / (sizeof(unsigned long))))); 1413 #endif 1414 } 1415 #else 1416 static __inline void 1417 prefetch(void *x) 1418 { 1419 } 1420 1421 static __inline void 1422 prefetch2cachelines(void *x) 1423 { 1424 } 1425 #endif 1426 1427 static void 1428 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1429 { 1430 iflib_fl_t fl; 1431 1432 fl = &rxq->ifr_fl[flid]; 1433 iru->iru_paddrs = fl->ifl_bus_addrs; 1434 iru->iru_idxs = fl->ifl_rxd_idxs; 1435 iru->iru_qsidx = rxq->ifr_id; 1436 iru->iru_buf_size = fl->ifl_buf_size; 1437 iru->iru_flidx = fl->ifl_id; 1438 } 1439 1440 static void 1441 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1442 { 1443 if (err) 1444 return; 1445 *(bus_addr_t *) arg = segs[0].ds_addr; 1446 } 1447 1448 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \ 1449 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \ 1450 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL) 1451 1452 int 1453 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1454 { 1455 int err; 1456 device_t dev = ctx->ifc_dev; 1457 bus_addr_t lowaddr; 1458 1459 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width); 1460 1461 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1462 align, 0, /* alignment, bounds */ 1463 lowaddr, /* lowaddr */ 1464 BUS_SPACE_MAXADDR, /* highaddr */ 1465 NULL, NULL, /* filter, filterarg */ 1466 size, /* maxsize */ 1467 1, /* nsegments */ 1468 size, /* maxsegsize */ 1469 BUS_DMA_ALLOCNOW, /* flags */ 1470 NULL, /* lockfunc */ 1471 NULL, /* lockarg */ 1472 &dma->idi_tag); 1473 if (err) { 1474 device_printf(dev, 1475 "%s: bus_dma_tag_create failed: %d (size=%d, align=%d)\n", 1476 __func__, err, size, align); 1477 goto fail_0; 1478 } 1479 1480 err = bus_dmamem_alloc(dma->idi_tag, (void **)&dma->idi_vaddr, 1481 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1482 if (err) { 1483 device_printf(dev, 1484 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1485 __func__, (uintmax_t)size, err); 1486 goto fail_1; 1487 } 1488 1489 dma->idi_paddr = IF_BAD_DMA; 1490 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1491 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1492 if (err || dma->idi_paddr == IF_BAD_DMA) { 1493 device_printf(dev, 1494 "%s: bus_dmamap_load failed: %d\n", 1495 __func__, err); 1496 goto fail_2; 1497 } 1498 1499 dma->idi_size = size; 1500 return (0); 1501 1502 fail_2: 1503 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1504 fail_1: 1505 bus_dma_tag_destroy(dma->idi_tag); 1506 fail_0: 1507 dma->idi_tag = NULL; 1508 1509 return (err); 1510 } 1511 1512 int 1513 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1514 { 1515 if_shared_ctx_t sctx = ctx->ifc_sctx; 1516 1517 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1518 1519 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1520 } 1521 1522 int 1523 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1524 { 1525 int i, err; 1526 iflib_dma_info_t *dmaiter; 1527 1528 dmaiter = dmalist; 1529 for (i = 0; i < count; i++, dmaiter++) { 1530 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1531 break; 1532 } 1533 if (err) 1534 iflib_dma_free_multi(dmalist, i); 1535 return (err); 1536 } 1537 1538 void 1539 iflib_dma_free(iflib_dma_info_t dma) 1540 { 1541 if (dma->idi_tag == NULL) 1542 return; 1543 if (dma->idi_paddr != IF_BAD_DMA) { 1544 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1545 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1546 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1547 dma->idi_paddr = IF_BAD_DMA; 1548 } 1549 if (dma->idi_vaddr != NULL) { 1550 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1551 dma->idi_vaddr = NULL; 1552 } 1553 bus_dma_tag_destroy(dma->idi_tag); 1554 dma->idi_tag = NULL; 1555 } 1556 1557 void 1558 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1559 { 1560 int i; 1561 iflib_dma_info_t *dmaiter = dmalist; 1562 1563 for (i = 0; i < count; i++, dmaiter++) 1564 iflib_dma_free(*dmaiter); 1565 } 1566 1567 static int 1568 iflib_fast_intr(void *arg) 1569 { 1570 iflib_filter_info_t info = arg; 1571 struct grouptask *gtask = info->ifi_task; 1572 int result; 1573 1574 DBG_COUNTER_INC(fast_intrs); 1575 if (info->ifi_filter != NULL) { 1576 result = info->ifi_filter(info->ifi_filter_arg); 1577 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1578 return (result); 1579 } 1580 1581 GROUPTASK_ENQUEUE(gtask); 1582 return (FILTER_HANDLED); 1583 } 1584 1585 static int 1586 iflib_fast_intr_rxtx(void *arg) 1587 { 1588 iflib_filter_info_t info = arg; 1589 struct grouptask *gtask = info->ifi_task; 1590 if_ctx_t ctx; 1591 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1592 iflib_txq_t txq; 1593 void *sc; 1594 int i, cidx, result; 1595 qidx_t txqid; 1596 bool intr_enable, intr_legacy; 1597 1598 DBG_COUNTER_INC(fast_intrs); 1599 if (info->ifi_filter != NULL) { 1600 result = info->ifi_filter(info->ifi_filter_arg); 1601 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1602 return (result); 1603 } 1604 1605 ctx = rxq->ifr_ctx; 1606 sc = ctx->ifc_softc; 1607 intr_enable = false; 1608 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1609 MPASS(rxq->ifr_ntxqirq); 1610 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1611 txqid = rxq->ifr_txqid[i]; 1612 txq = &ctx->ifc_txqs[txqid]; 1613 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1614 BUS_DMASYNC_POSTREAD); 1615 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1616 if (intr_legacy) 1617 intr_enable = true; 1618 else 1619 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1620 continue; 1621 } 1622 GROUPTASK_ENQUEUE(&txq->ift_task); 1623 } 1624 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1625 cidx = rxq->ifr_cq_cidx; 1626 else 1627 cidx = rxq->ifr_fl[0].ifl_cidx; 1628 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1629 GROUPTASK_ENQUEUE(gtask); 1630 else { 1631 if (intr_legacy) 1632 intr_enable = true; 1633 else 1634 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1635 DBG_COUNTER_INC(rx_intr_enables); 1636 } 1637 if (intr_enable) 1638 IFDI_INTR_ENABLE(ctx); 1639 return (FILTER_HANDLED); 1640 } 1641 1642 static int 1643 iflib_fast_intr_ctx(void *arg) 1644 { 1645 iflib_filter_info_t info = arg; 1646 if_ctx_t ctx = info->ifi_ctx; 1647 int result; 1648 1649 DBG_COUNTER_INC(fast_intrs); 1650 if (info->ifi_filter != NULL) { 1651 result = info->ifi_filter(info->ifi_filter_arg); 1652 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1653 return (result); 1654 } 1655 1656 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_admin_task); 1657 return (FILTER_HANDLED); 1658 } 1659 1660 static int 1661 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1662 driver_filter_t filter, driver_intr_t handler, void *arg, 1663 const char *name) 1664 { 1665 struct resource *res; 1666 void *tag = NULL; 1667 device_t dev = ctx->ifc_dev; 1668 int flags, i, rc; 1669 1670 flags = RF_ACTIVE; 1671 if (ctx->ifc_flags & IFC_LEGACY) 1672 flags |= RF_SHAREABLE; 1673 MPASS(rid < 512); 1674 i = rid; 1675 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1676 if (res == NULL) { 1677 device_printf(dev, 1678 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1679 return (ENOMEM); 1680 } 1681 irq->ii_res = res; 1682 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1683 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1684 filter, handler, arg, &tag); 1685 if (rc != 0) { 1686 device_printf(dev, 1687 "failed to setup interrupt for rid %d, name %s: %d\n", 1688 rid, name ? name : "unknown", rc); 1689 return (rc); 1690 } else if (name) 1691 bus_describe_intr(dev, res, tag, "%s", name); 1692 1693 irq->ii_tag = tag; 1694 return (0); 1695 } 1696 1697 /********************************************************************* 1698 * 1699 * Allocate DMA resources for TX buffers as well as memory for the TX 1700 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1701 * iflib_sw_tx_desc_array structure, storing all the information that 1702 * is needed to transmit a packet on the wire. This is called only 1703 * once at attach, setup is done every reset. 1704 * 1705 **********************************************************************/ 1706 static int 1707 iflib_txsd_alloc(iflib_txq_t txq) 1708 { 1709 if_ctx_t ctx = txq->ift_ctx; 1710 if_shared_ctx_t sctx = ctx->ifc_sctx; 1711 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1712 device_t dev = ctx->ifc_dev; 1713 bus_size_t tsomaxsize; 1714 bus_addr_t lowaddr; 1715 int err, nsegments, ntsosegments; 1716 bool tso; 1717 1718 nsegments = scctx->isc_tx_nsegments; 1719 ntsosegments = scctx->isc_tx_tso_segments_max; 1720 tsomaxsize = scctx->isc_tx_tso_size_max; 1721 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1722 tsomaxsize += sizeof(struct ether_vlan_header); 1723 MPASS(scctx->isc_ntxd[0] > 0); 1724 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1725 MPASS(nsegments > 0); 1726 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1727 MPASS(ntsosegments > 0); 1728 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1729 } 1730 1731 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1732 1733 /* 1734 * Set up DMA tags for TX buffers. 1735 */ 1736 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1737 1, 0, /* alignment, bounds */ 1738 lowaddr, /* lowaddr */ 1739 BUS_SPACE_MAXADDR, /* highaddr */ 1740 NULL, NULL, /* filter, filterarg */ 1741 sctx->isc_tx_maxsize, /* maxsize */ 1742 nsegments, /* nsegments */ 1743 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1744 0, /* flags */ 1745 NULL, /* lockfunc */ 1746 NULL, /* lockfuncarg */ 1747 &txq->ift_buf_tag))) { 1748 device_printf(dev, "Unable to allocate TX DMA tag: %d\n", err); 1749 device_printf(dev, "maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1750 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1751 goto fail; 1752 } 1753 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1754 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1755 1, 0, /* alignment, bounds */ 1756 lowaddr, /* lowaddr */ 1757 BUS_SPACE_MAXADDR, /* highaddr */ 1758 NULL, NULL, /* filter, filterarg */ 1759 tsomaxsize, /* maxsize */ 1760 ntsosegments, /* nsegments */ 1761 sctx->isc_tso_maxsegsize, /* maxsegsize */ 1762 0, /* flags */ 1763 NULL, /* lockfunc */ 1764 NULL, /* lockfuncarg */ 1765 &txq->ift_tso_buf_tag))) { 1766 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1767 err); 1768 goto fail; 1769 } 1770 1771 /* Allocate memory for the TX mbuf map. */ 1772 if (!(txq->ift_sds.ifsd_m = 1773 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1774 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1775 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1776 err = ENOMEM; 1777 goto fail; 1778 } 1779 if (ctx->ifc_sysctl_simple_tx) { 1780 if (!(txq->ift_sds.ifsd_m_defer = 1781 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1782 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1783 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1784 err = ENOMEM; 1785 goto fail; 1786 } 1787 } 1788 txq->ift_sds.ifsd_m_deferb = txq->ift_sds.ifsd_m_defer; 1789 /* 1790 * Create the DMA maps for TX buffers. 1791 */ 1792 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1793 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1794 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1795 device_printf(dev, 1796 "Unable to allocate TX buffer DMA map memory\n"); 1797 err = ENOMEM; 1798 goto fail; 1799 } 1800 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1801 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1802 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1803 device_printf(dev, 1804 "Unable to allocate TSO TX buffer map memory\n"); 1805 err = ENOMEM; 1806 goto fail; 1807 } 1808 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1809 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1810 &txq->ift_sds.ifsd_map[i]); 1811 if (err != 0) { 1812 device_printf(dev, "Unable to create TX DMA map\n"); 1813 goto fail; 1814 } 1815 if (!tso) 1816 continue; 1817 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1818 &txq->ift_sds.ifsd_tso_map[i]); 1819 if (err != 0) { 1820 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1821 goto fail; 1822 } 1823 } 1824 return (0); 1825 fail: 1826 /* We free all, it handles case where we are in the middle */ 1827 iflib_tx_structures_free(ctx); 1828 return (err); 1829 } 1830 1831 static void 1832 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1833 { 1834 bus_dmamap_t map; 1835 1836 if (txq->ift_sds.ifsd_map != NULL) { 1837 map = txq->ift_sds.ifsd_map[i]; 1838 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1839 bus_dmamap_unload(txq->ift_buf_tag, map); 1840 bus_dmamap_destroy(txq->ift_buf_tag, map); 1841 txq->ift_sds.ifsd_map[i] = NULL; 1842 } 1843 1844 if (txq->ift_sds.ifsd_tso_map != NULL) { 1845 map = txq->ift_sds.ifsd_tso_map[i]; 1846 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1847 BUS_DMASYNC_POSTWRITE); 1848 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1849 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1850 txq->ift_sds.ifsd_tso_map[i] = NULL; 1851 } 1852 } 1853 1854 static void 1855 iflib_txq_destroy(iflib_txq_t txq) 1856 { 1857 if_ctx_t ctx = txq->ift_ctx; 1858 1859 for (int i = 0; i < txq->ift_size; i++) 1860 iflib_txsd_destroy(ctx, txq, i); 1861 1862 if (txq->ift_br != NULL) { 1863 ifmp_ring_free(txq->ift_br); 1864 txq->ift_br = NULL; 1865 } 1866 1867 mtx_destroy(&txq->ift_mtx); 1868 1869 if (txq->ift_sds.ifsd_map != NULL) { 1870 free(txq->ift_sds.ifsd_map, M_IFLIB); 1871 txq->ift_sds.ifsd_map = NULL; 1872 } 1873 if (txq->ift_sds.ifsd_tso_map != NULL) { 1874 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1875 txq->ift_sds.ifsd_tso_map = NULL; 1876 } 1877 if (txq->ift_sds.ifsd_m != NULL) { 1878 free(txq->ift_sds.ifsd_m, M_IFLIB); 1879 txq->ift_sds.ifsd_m = NULL; 1880 } 1881 if (txq->ift_sds.ifsd_m_defer != NULL) { 1882 free(txq->ift_sds.ifsd_m_defer, M_IFLIB); 1883 txq->ift_sds.ifsd_m_defer = NULL; 1884 } 1885 if (txq->ift_buf_tag != NULL) { 1886 bus_dma_tag_destroy(txq->ift_buf_tag); 1887 txq->ift_buf_tag = NULL; 1888 } 1889 if (txq->ift_tso_buf_tag != NULL) { 1890 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1891 txq->ift_tso_buf_tag = NULL; 1892 } 1893 if (txq->ift_ifdi != NULL) { 1894 free(txq->ift_ifdi, M_IFLIB); 1895 } 1896 } 1897 1898 static void 1899 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1900 { 1901 struct mbuf *m; 1902 1903 m = IFLIB_GET_MBUF(txq->ift_sds.ifsd_m[i]); 1904 if (m == NULL) 1905 return; 1906 1907 if (txq->ift_sds.ifsd_map != NULL) { 1908 bus_dmamap_sync(txq->ift_buf_tag, 1909 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1910 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1911 } 1912 if (txq->ift_sds.ifsd_tso_map != NULL) { 1913 bus_dmamap_sync(txq->ift_tso_buf_tag, 1914 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1915 bus_dmamap_unload(txq->ift_tso_buf_tag, 1916 txq->ift_sds.ifsd_tso_map[i]); 1917 } 1918 txq->ift_sds.ifsd_m[i] = NULL; 1919 m_freem(m); 1920 DBG_COUNTER_INC(tx_frees); 1921 } 1922 1923 static int 1924 iflib_txq_setup(iflib_txq_t txq) 1925 { 1926 if_ctx_t ctx = txq->ift_ctx; 1927 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1928 if_shared_ctx_t sctx = ctx->ifc_sctx; 1929 iflib_dma_info_t di; 1930 int i; 1931 1932 /* XXX make configurable */ 1933 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1934 1935 /* Reset indices */ 1936 txq->ift_cidx_processed = 0; 1937 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1938 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1939 txq->ift_pad = scctx->isc_tx_pad; 1940 1941 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1942 bzero((void *)di->idi_vaddr, di->idi_size); 1943 1944 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1945 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1946 bus_dmamap_sync(di->idi_tag, di->idi_map, 1947 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1948 return (0); 1949 } 1950 1951 /********************************************************************* 1952 * 1953 * Allocate DMA resources for RX buffers as well as memory for the RX 1954 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1955 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1956 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1957 * Since we use use one entry in iflib_sw_rx_desc_array per received 1958 * packet, the maximum number of entries we'll need is equal to the 1959 * number of hardware receive descriptors that we've allocated. 1960 * 1961 **********************************************************************/ 1962 static int 1963 iflib_rxsd_alloc(iflib_rxq_t rxq) 1964 { 1965 if_ctx_t ctx = rxq->ifr_ctx; 1966 if_shared_ctx_t sctx = ctx->ifc_sctx; 1967 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1968 device_t dev = ctx->ifc_dev; 1969 iflib_fl_t fl; 1970 bus_addr_t lowaddr; 1971 int err; 1972 1973 MPASS(scctx->isc_nrxd[0] > 0); 1974 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1975 1976 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1977 1978 fl = rxq->ifr_fl; 1979 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1980 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1981 /* Set up DMA tag for RX buffers. */ 1982 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1983 1, 0, /* alignment, bounds */ 1984 lowaddr, /* lowaddr */ 1985 BUS_SPACE_MAXADDR, /* highaddr */ 1986 NULL, NULL, /* filter, filterarg */ 1987 sctx->isc_rx_maxsize, /* maxsize */ 1988 sctx->isc_rx_nsegments, /* nsegments */ 1989 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1990 0, /* flags */ 1991 NULL, /* lockfunc */ 1992 NULL, /* lockarg */ 1993 &fl->ifl_buf_tag); 1994 if (err) { 1995 device_printf(dev, 1996 "Unable to allocate RX DMA tag: %d\n", err); 1997 goto fail; 1998 } 1999 2000 /* Allocate memory for the RX mbuf map. */ 2001 if (!(fl->ifl_sds.ifsd_m = 2002 (struct mbuf **) malloc(sizeof(struct mbuf *) * 2003 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2004 device_printf(dev, 2005 "Unable to allocate RX mbuf map memory\n"); 2006 err = ENOMEM; 2007 goto fail; 2008 } 2009 2010 /* Allocate memory for the direct RX cluster pointer map. */ 2011 if (!(fl->ifl_sds.ifsd_cl = 2012 (caddr_t *) malloc(sizeof(caddr_t) * 2013 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2014 device_printf(dev, 2015 "Unable to allocate RX cluster map memory\n"); 2016 err = ENOMEM; 2017 goto fail; 2018 } 2019 2020 /* Allocate memory for the RX cluster bus address map. */ 2021 if (!(fl->ifl_sds.ifsd_ba = 2022 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 2023 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2024 device_printf(dev, 2025 "Unable to allocate RX bus address map memory\n"); 2026 err = ENOMEM; 2027 goto fail; 2028 } 2029 2030 /* 2031 * Create the DMA maps for RX buffers. 2032 */ 2033 if (!(fl->ifl_sds.ifsd_map = 2034 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2035 device_printf(dev, 2036 "Unable to allocate RX buffer DMA map memory\n"); 2037 err = ENOMEM; 2038 goto fail; 2039 } 2040 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 2041 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 2042 &fl->ifl_sds.ifsd_map[i]); 2043 if (err != 0) { 2044 device_printf(dev, "Unable to create RX buffer DMA map\n"); 2045 goto fail; 2046 } 2047 } 2048 } 2049 return (0); 2050 2051 fail: 2052 iflib_rx_structures_free(ctx); 2053 return (err); 2054 } 2055 2056 /* 2057 * Internal service routines 2058 */ 2059 2060 struct rxq_refill_cb_arg { 2061 int error; 2062 bus_dma_segment_t seg; 2063 int nseg; 2064 }; 2065 2066 static void 2067 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2068 { 2069 struct rxq_refill_cb_arg *cb_arg = arg; 2070 2071 cb_arg->error = error; 2072 cb_arg->seg = segs[0]; 2073 cb_arg->nseg = nseg; 2074 } 2075 2076 /** 2077 * iflib_fl_refill - refill an rxq free-buffer list 2078 * @ctx: the iflib context 2079 * @fl: the free list to refill 2080 * @count: the number of new buffers to allocate 2081 * 2082 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 2083 * The caller must assure that @count does not exceed the queue's capacity 2084 * minus one (since we always leave a descriptor unavailable). 2085 */ 2086 static uint8_t 2087 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 2088 { 2089 struct if_rxd_update iru; 2090 struct rxq_refill_cb_arg cb_arg; 2091 struct mbuf *m; 2092 caddr_t cl, *sd_cl; 2093 struct mbuf **sd_m; 2094 bus_dmamap_t *sd_map; 2095 bus_addr_t bus_addr, *sd_ba; 2096 int err, frag_idx, i, idx, n, pidx; 2097 qidx_t credits; 2098 2099 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 2100 2101 sd_m = fl->ifl_sds.ifsd_m; 2102 sd_map = fl->ifl_sds.ifsd_map; 2103 sd_cl = fl->ifl_sds.ifsd_cl; 2104 sd_ba = fl->ifl_sds.ifsd_ba; 2105 pidx = fl->ifl_pidx; 2106 idx = pidx; 2107 frag_idx = fl->ifl_fragidx; 2108 credits = fl->ifl_credits; 2109 2110 i = 0; 2111 n = count; 2112 MPASS(n > 0); 2113 MPASS(credits + n <= fl->ifl_size); 2114 2115 if (pidx < fl->ifl_cidx) 2116 MPASS(pidx + n <= fl->ifl_cidx); 2117 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 2118 MPASS(fl->ifl_gen == 0); 2119 if (pidx > fl->ifl_cidx) 2120 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 2121 2122 DBG_COUNTER_INC(fl_refills); 2123 if (n > 8) 2124 DBG_COUNTER_INC(fl_refills_large); 2125 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 2126 while (n-- > 0) { 2127 /* 2128 * We allocate an uninitialized mbuf + cluster, mbuf is 2129 * initialized after rx. 2130 * 2131 * If the cluster is still set then we know a minimum sized 2132 * packet was received 2133 */ 2134 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2135 &frag_idx); 2136 if (frag_idx < 0) 2137 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2138 MPASS(frag_idx >= 0); 2139 if ((cl = sd_cl[frag_idx]) == NULL) { 2140 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2141 if (__predict_false(cl == NULL)) 2142 break; 2143 2144 cb_arg.error = 0; 2145 MPASS(sd_map != NULL); 2146 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2147 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2148 BUS_DMA_NOWAIT); 2149 if (__predict_false(err != 0 || cb_arg.error)) { 2150 uma_zfree(fl->ifl_zone, cl); 2151 break; 2152 } 2153 2154 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2155 sd_cl[frag_idx] = cl; 2156 #if MEMORY_LOGGING 2157 fl->ifl_cl_enqueued++; 2158 #endif 2159 } else { 2160 bus_addr = sd_ba[frag_idx]; 2161 } 2162 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2163 BUS_DMASYNC_PREREAD); 2164 2165 if (sd_m[frag_idx] == NULL) { 2166 m = m_gethdr_raw(M_NOWAIT, 0); 2167 if (__predict_false(m == NULL)) 2168 break; 2169 sd_m[frag_idx] = m; 2170 } 2171 bit_set(fl->ifl_rx_bitmap, frag_idx); 2172 #if MEMORY_LOGGING 2173 fl->ifl_m_enqueued++; 2174 #endif 2175 2176 DBG_COUNTER_INC(rx_allocs); 2177 fl->ifl_rxd_idxs[i] = frag_idx; 2178 fl->ifl_bus_addrs[i] = bus_addr; 2179 credits++; 2180 i++; 2181 MPASS(credits <= fl->ifl_size); 2182 if (++idx == fl->ifl_size) { 2183 #ifdef INVARIANTS 2184 fl->ifl_gen = 1; 2185 #endif 2186 idx = 0; 2187 } 2188 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2189 iru.iru_pidx = pidx; 2190 iru.iru_count = i; 2191 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2192 fl->ifl_pidx = idx; 2193 fl->ifl_credits = credits; 2194 pidx = idx; 2195 i = 0; 2196 } 2197 } 2198 2199 if (n < count - 1) { 2200 if (i != 0) { 2201 iru.iru_pidx = pidx; 2202 iru.iru_count = i; 2203 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2204 fl->ifl_pidx = idx; 2205 fl->ifl_credits = credits; 2206 } 2207 DBG_COUNTER_INC(rxd_flush); 2208 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2209 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2210 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2211 fl->ifl_id, fl->ifl_pidx); 2212 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2213 fl->ifl_fragidx = frag_idx + 1; 2214 if (fl->ifl_fragidx == fl->ifl_size) 2215 fl->ifl_fragidx = 0; 2216 } else { 2217 fl->ifl_fragidx = frag_idx; 2218 } 2219 } 2220 2221 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2222 } 2223 2224 static inline uint8_t 2225 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2226 { 2227 /* 2228 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2229 * This is important as it confuses most NICs. For instance, 2230 * Intel NICs have (per receive ring) RDH and RDT registers, where 2231 * RDH points to the next receive descriptor to be used by the NIC, 2232 * and RDT for the next receive descriptor to be published by the 2233 * driver to the NIC (RDT - 1 is thus the last valid one). 2234 * The condition RDH == RDT means no descriptors are available to 2235 * the NIC, and thus it would be ambiguous if it also meant that 2236 * all the descriptors are available to the NIC. 2237 */ 2238 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2239 #ifdef INVARIANTS 2240 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2241 #endif 2242 2243 MPASS(fl->ifl_credits <= fl->ifl_size); 2244 MPASS(reclaimable == delta); 2245 2246 if (reclaimable > 0) 2247 return (iflib_fl_refill(ctx, fl, reclaimable)); 2248 return (0); 2249 } 2250 2251 uint8_t 2252 iflib_in_detach(if_ctx_t ctx) 2253 { 2254 bool in_detach; 2255 2256 STATE_LOCK(ctx); 2257 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2258 STATE_UNLOCK(ctx); 2259 return (in_detach); 2260 } 2261 2262 static void 2263 iflib_fl_bufs_free(iflib_fl_t fl) 2264 { 2265 iflib_dma_info_t idi = fl->ifl_ifdi; 2266 bus_dmamap_t sd_map; 2267 uint32_t i; 2268 2269 for (i = 0; i < fl->ifl_size; i++) { 2270 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2271 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2272 2273 if (*sd_cl != NULL) { 2274 sd_map = fl->ifl_sds.ifsd_map[i]; 2275 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2276 BUS_DMASYNC_POSTREAD); 2277 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2278 uma_zfree(fl->ifl_zone, *sd_cl); 2279 *sd_cl = NULL; 2280 if (*sd_m != NULL) { 2281 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2282 m_free_raw(*sd_m); 2283 *sd_m = NULL; 2284 } 2285 } else { 2286 MPASS(*sd_m == NULL); 2287 } 2288 #if MEMORY_LOGGING 2289 fl->ifl_m_dequeued++; 2290 fl->ifl_cl_dequeued++; 2291 #endif 2292 } 2293 #ifdef INVARIANTS 2294 for (i = 0; i < fl->ifl_size; i++) { 2295 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2296 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2297 } 2298 #endif 2299 /* 2300 * Reset free list values 2301 */ 2302 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2303 bzero(idi->idi_vaddr, idi->idi_size); 2304 } 2305 2306 /********************************************************************* 2307 * 2308 * Initialize a free list and its buffers. 2309 * 2310 **********************************************************************/ 2311 static int 2312 iflib_fl_setup(iflib_fl_t fl) 2313 { 2314 iflib_rxq_t rxq = fl->ifl_rxq; 2315 if_ctx_t ctx = rxq->ifr_ctx; 2316 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2317 int qidx; 2318 2319 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2320 /* 2321 * Free current RX buffer structs and their mbufs 2322 */ 2323 iflib_fl_bufs_free(fl); 2324 /* Now replenish the mbufs */ 2325 MPASS(fl->ifl_credits == 0); 2326 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2327 if (scctx->isc_rxd_buf_size[qidx] != 0) 2328 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2329 else 2330 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2331 /* 2332 * ifl_buf_size may be a driver-supplied value, so pull it up 2333 * to the selected mbuf size. 2334 */ 2335 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2336 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2337 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2338 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2339 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2340 2341 /* 2342 * Avoid pre-allocating zillions of clusters to an idle card 2343 * potentially speeding up attach. In any case make sure 2344 * to leave a descriptor unavailable. See the comment in 2345 * iflib_fl_refill_all(). 2346 */ 2347 MPASS(fl->ifl_size > 0); 2348 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2349 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2350 return (ENOBUFS); 2351 /* 2352 * handle failure 2353 */ 2354 MPASS(rxq != NULL); 2355 MPASS(fl->ifl_ifdi != NULL); 2356 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2357 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2358 return (0); 2359 } 2360 2361 /********************************************************************* 2362 * 2363 * Free receive ring data structures 2364 * 2365 **********************************************************************/ 2366 static void 2367 iflib_rx_sds_free(iflib_rxq_t rxq) 2368 { 2369 iflib_fl_t fl; 2370 int i, j; 2371 2372 if (rxq->ifr_fl != NULL) { 2373 for (i = 0; i < rxq->ifr_nfl; i++) { 2374 fl = &rxq->ifr_fl[i]; 2375 if (fl->ifl_buf_tag != NULL) { 2376 if (fl->ifl_sds.ifsd_map != NULL) { 2377 for (j = 0; j < fl->ifl_size; j++) { 2378 bus_dmamap_sync( 2379 fl->ifl_buf_tag, 2380 fl->ifl_sds.ifsd_map[j], 2381 BUS_DMASYNC_POSTREAD); 2382 bus_dmamap_unload( 2383 fl->ifl_buf_tag, 2384 fl->ifl_sds.ifsd_map[j]); 2385 bus_dmamap_destroy( 2386 fl->ifl_buf_tag, 2387 fl->ifl_sds.ifsd_map[j]); 2388 } 2389 } 2390 bus_dma_tag_destroy(fl->ifl_buf_tag); 2391 fl->ifl_buf_tag = NULL; 2392 } 2393 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2394 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2395 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2396 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2397 free(fl->ifl_rx_bitmap, M_IFLIB); 2398 fl->ifl_sds.ifsd_m = NULL; 2399 fl->ifl_sds.ifsd_cl = NULL; 2400 fl->ifl_sds.ifsd_ba = NULL; 2401 fl->ifl_sds.ifsd_map = NULL; 2402 fl->ifl_rx_bitmap = NULL; 2403 } 2404 free(rxq->ifr_fl, M_IFLIB); 2405 rxq->ifr_fl = NULL; 2406 free(rxq->ifr_ifdi, M_IFLIB); 2407 rxq->ifr_ifdi = NULL; 2408 rxq->ifr_cq_cidx = 0; 2409 } 2410 } 2411 2412 /* 2413 * Timer routine 2414 */ 2415 static void 2416 iflib_timer(void *arg) 2417 { 2418 iflib_txq_t txq = arg; 2419 if_ctx_t ctx = txq->ift_ctx; 2420 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2421 uint64_t this_tick = ticks; 2422 2423 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2424 return; 2425 2426 /* 2427 * Check on the state of the TX queue(s); this can be done 2428 * without the lock: the counters the check reads are only 2429 * advanced by the queue's tx task and a stale read just 2430 * delays the verdict by one timer period. 2431 */ 2432 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) { 2433 qidx_t outstanding; 2434 bool frozen; 2435 2436 txq->ift_last_timer_tick = this_tick; 2437 IFDI_TIMER(ctx, txq->ift_id); 2438 2439 /* 2440 * Descriptors the hardware has not reported as 2441 * completed: neither harvested as credits 2442 * (ift_processed) nor reclaimed (ift_cleaned accounts 2443 * the difference to ift_in_use). The tail whose 2444 * report-status request is still deferred is never 2445 * reported and must not count (ift_rs_pending 2446 * over-counts it by one per packet). 2447 */ 2448 outstanding = txq->ift_in_use - 2449 (qidx_t)(txq->ift_processed - txq->ift_cleaned); 2450 2451 /* 2452 * The queue is frozen while it has descriptors the 2453 * hardware has not reported as completed and none 2454 * were reclaimed over the period; the link must be 2455 * up, with no pause frames and no pending doorbell 2456 * (the laggard check below rings it). 2457 * 2458 * Being frozen is not a fault - the hardware may 2459 * defer marking descriptors as completed 2460 * indefinitely, and 8254x hardware does so for a 2461 * quiet queue - therefore the check arms only when a 2462 * frozen queue also takes on new work, and acts only 2463 * once it has stayed frozen for 2464 * net.iflib.tx_watchdog_periods consecutive periods. 2465 */ 2466 frozen = outstanding > txq->ift_rs_pending && 2467 txq->ift_processed == txq->ift_processed_prev && 2468 txq->ift_db_pending == 0 && 2469 sctx->isc_pause_frames == 0 && 2470 ctx->ifc_link_state == LINK_STATE_UP; 2471 if (!frozen) 2472 txq->ift_wdog_armed = 0; 2473 else if (txq->ift_wdog_armed > 0 || 2474 outstanding > txq->ift_outstanding_prev) { 2475 if (txq->ift_wdog_armed < UINT16_MAX) 2476 txq->ift_wdog_armed++; 2477 } 2478 2479 /* 2480 * Frozen long enough: ask the hardware. Completions 2481 * ready but unharvested for this long mean the 2482 * completion interrupt went missing - kick the 2483 * queue's task. Nothing ready, although the queue 2484 * kept taking on work, means it is hung. 2485 */ 2486 if (iflib_tx_watchdog_periods > 0 && 2487 txq->ift_wdog_armed >= iflib_tx_watchdog_periods) { 2488 bus_dmamap_sync(txq->ift_ifdi->idi_tag, 2489 txq->ift_ifdi->idi_map, BUS_DMASYNC_POSTREAD); 2490 if (ctx->isc_txd_credits_update(ctx->ifc_softc, 2491 txq->ift_id, false) == 0) { 2492 device_printf(ctx->ifc_dev, 2493 "Watchdog timeout (TX: %d desc " 2494 "avail: %d pidx: %d) -- resetting\n", 2495 txq->ift_id, TXQ_AVAIL(txq), 2496 txq->ift_pidx); 2497 STATE_LOCK(ctx); 2498 if_setdrvflagbits(ctx->ifc_ifp, 2499 IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2500 ctx->ifc_flags |= 2501 (IFC_DO_WATCHDOG | IFC_DO_RESET); 2502 iflib_admin_intr_deferred(ctx); 2503 STATE_UNLOCK(ctx); 2504 return; 2505 } 2506 GROUPTASK_ENQUEUE(&txq->ift_task); 2507 } 2508 txq->ift_outstanding_prev = outstanding; 2509 txq->ift_processed_prev = txq->ift_processed; 2510 } 2511 /* handle any laggards */ 2512 if (txq->ift_db_pending) 2513 GROUPTASK_ENQUEUE(&txq->ift_task); 2514 2515 sctx->isc_pause_frames = 0; 2516 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2517 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, 2518 txq, txq->ift_timer.c_cpu); 2519 } 2520 2521 static uint16_t 2522 iflib_get_mbuf_size_for(unsigned int size) 2523 { 2524 2525 if (size <= MCLBYTES) 2526 return (MCLBYTES); 2527 else 2528 return (MJUMPAGESIZE); 2529 } 2530 2531 static void 2532 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2533 { 2534 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2535 2536 /* 2537 * XXX don't set the max_frame_size to larger 2538 * than the hardware can handle 2539 */ 2540 ctx->ifc_rx_mbuf_sz = 2541 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2542 } 2543 2544 uint32_t 2545 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2546 { 2547 2548 return (ctx->ifc_rx_mbuf_sz); 2549 } 2550 2551 static void 2552 iflib_init_locked(if_ctx_t ctx) 2553 { 2554 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2555 if_t ifp = ctx->ifc_ifp; 2556 iflib_fl_t fl; 2557 iflib_txq_t txq; 2558 iflib_rxq_t rxq; 2559 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2560 bool init_failed; 2561 2562 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2563 IFDI_INTR_DISABLE(ctx); 2564 2565 /* 2566 * See iflib_stop(). Useful in case iflib_init_locked() is 2567 * called without first calling iflib_stop(). 2568 */ 2569 netmap_disable_all_rings(ifp); 2570 2571 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2572 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2573 /* Set hardware offload abilities */ 2574 if_clearhwassist(ifp); 2575 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2576 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2577 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2578 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2579 if (if_getcapenable(ifp) & IFCAP_TSO4) 2580 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2581 if (if_getcapenable(ifp) & IFCAP_TSO6) 2582 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2583 2584 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 2585 CALLOUT_LOCK(txq); 2586 callout_stop(&txq->ift_timer); 2587 #ifdef DEV_NETMAP 2588 callout_stop(&txq->ift_netmap_timer); 2589 #endif /* DEV_NETMAP */ 2590 CALLOUT_UNLOCK(txq); 2591 (void)iflib_netmap_txq_init(ctx, txq); 2592 } 2593 2594 /* 2595 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2596 * that drivers can use the value when setting up the hardware receive 2597 * buffers. 2598 */ 2599 iflib_calc_rx_mbuf_sz(ctx); 2600 2601 #ifdef INVARIANTS 2602 i = if_getdrvflags(ifp); 2603 #endif 2604 STATE_LOCK(ctx); 2605 ctx->ifc_flags &= ~IFC_INIT_FAILED; 2606 STATE_UNLOCK(ctx); 2607 IFDI_INIT(ctx); 2608 MPASS(if_getdrvflags(ifp) == i); 2609 STATE_LOCK(ctx); 2610 init_failed = (ctx->ifc_flags & IFC_INIT_FAILED) != 0; 2611 STATE_UNLOCK(ctx); 2612 if (init_failed) 2613 return; 2614 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 2615 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2616 /* This rxq is in netmap mode. Skip normal init. */ 2617 continue; 2618 } 2619 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2620 if (iflib_fl_setup(fl)) { 2621 device_printf(ctx->ifc_dev, 2622 "setting up free list %d failed - " 2623 "check cluster settings\n", j); 2624 goto done; 2625 } 2626 } 2627 } 2628 done: 2629 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2630 IFDI_INTR_ENABLE(ctx); 2631 txq = ctx->ifc_txqs; 2632 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) 2633 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 2634 txq->ift_timer.c_cpu); 2635 2636 /* Re-enable txsync/rxsync. */ 2637 netmap_enable_all_rings(ifp); 2638 } 2639 2640 static int 2641 iflib_media_change(if_t ifp) 2642 { 2643 if_ctx_t ctx = if_getsoftc(ifp); 2644 int err; 2645 2646 CTX_LOCK(ctx); 2647 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2648 iflib_if_init_locked(ctx); 2649 CTX_UNLOCK(ctx); 2650 return (err); 2651 } 2652 2653 static void 2654 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2655 { 2656 if_ctx_t ctx = if_getsoftc(ifp); 2657 2658 CTX_LOCK(ctx); 2659 IFDI_UPDATE_ADMIN_STATUS(ctx); 2660 IFDI_MEDIA_STATUS(ctx, ifmr); 2661 CTX_UNLOCK(ctx); 2662 } 2663 2664 static void 2665 iflib_stop(if_ctx_t ctx) 2666 { 2667 iflib_txq_t txq = ctx->ifc_txqs; 2668 iflib_rxq_t rxq = ctx->ifc_rxqs; 2669 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2670 if_shared_ctx_t sctx = ctx->ifc_sctx; 2671 iflib_dma_info_t di; 2672 iflib_fl_t fl; 2673 int i, j; 2674 2675 /* Tell the stack that the interface is no longer active */ 2676 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2677 2678 IFDI_INTR_DISABLE(ctx); 2679 DELAY(1000); 2680 IFDI_STOP(ctx); 2681 DELAY(1000); 2682 2683 /* 2684 * Stop any pending txsync/rxsync and prevent new ones 2685 * form starting. Processes blocked in poll() will get 2686 * POLLERR. 2687 */ 2688 netmap_disable_all_rings(ctx->ifc_ifp); 2689 2690 iflib_debug_reset(); 2691 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2692 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2693 /* make sure all transmitters have completed before proceeding XXX */ 2694 2695 CALLOUT_LOCK(txq); 2696 callout_stop(&txq->ift_timer); 2697 #ifdef DEV_NETMAP 2698 callout_stop(&txq->ift_netmap_timer); 2699 #endif /* DEV_NETMAP */ 2700 CALLOUT_UNLOCK(txq); 2701 2702 if (!ctx->ifc_sysctl_simple_tx) { 2703 /* clean any enqueued buffers */ 2704 iflib_ifmp_purge(txq); 2705 } 2706 /* Free any existing tx buffers. */ 2707 for (j = 0; j < txq->ift_size; j++) { 2708 iflib_txsd_free(ctx, txq, j); 2709 } 2710 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2711 txq->ift_processed_prev = 0; 2712 txq->ift_outstanding_prev = 0; 2713 txq->ift_wdog_armed = 0; 2714 txq->ift_in_use = txq->ift_gen = txq->ift_no_desc_avail = 0; 2715 txq->ift_npending = txq->ift_db_pending = 0; 2716 txq->ift_rs_pending = 0; 2717 if (sctx->isc_flags & IFLIB_PRESERVE_TX_INDICES) 2718 txq->ift_cidx = txq->ift_pidx; 2719 else 2720 txq->ift_cidx = txq->ift_pidx = 0; 2721 2722 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2723 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2724 txq->ift_pullups = 0; 2725 ifmp_ring_reset_stats(txq->ift_br); 2726 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2727 bzero((void *)di->idi_vaddr, di->idi_size); 2728 } 2729 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2730 if (rxq->ifr_task.gt_taskqueue != NULL) 2731 gtaskqueue_drain(rxq->ifr_task.gt_taskqueue, 2732 &rxq->ifr_task.gt_task); 2733 2734 rxq->ifr_cq_cidx = 0; 2735 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2736 bzero((void *)di->idi_vaddr, di->idi_size); 2737 /* also resets the free lists pidx/cidx */ 2738 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2739 iflib_fl_bufs_free(fl); 2740 } 2741 } 2742 2743 static inline caddr_t 2744 calc_next_rxd(iflib_fl_t fl, int cidx) 2745 { 2746 qidx_t size; 2747 int nrxd; 2748 caddr_t start, end, cur, next; 2749 2750 nrxd = fl->ifl_size; 2751 size = fl->ifl_rxd_size; 2752 start = fl->ifl_ifdi->idi_vaddr; 2753 2754 if (__predict_false(size == 0)) 2755 return (start); 2756 cur = start + size * cidx; 2757 end = start + size * nrxd; 2758 next = CACHE_PTR_NEXT(cur); 2759 return (next < end ? next : start); 2760 } 2761 2762 static inline void 2763 prefetch_pkts(iflib_fl_t fl, int cidx) 2764 { 2765 int nextptr; 2766 int nrxd = fl->ifl_size; 2767 caddr_t next_rxd; 2768 2769 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd - 1); 2770 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2771 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2772 next_rxd = calc_next_rxd(fl, cidx); 2773 prefetch(next_rxd); 2774 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd - 1)]); 2775 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd - 1)]); 2776 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd - 1)]); 2777 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd - 1)]); 2778 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd - 1)]); 2779 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd - 1)]); 2780 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd - 1)]); 2781 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd - 1)]); 2782 } 2783 2784 static struct mbuf * 2785 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2786 int *pf_rv, if_rxd_info_t ri) 2787 { 2788 bus_dmamap_t map; 2789 iflib_fl_t fl; 2790 caddr_t payload; 2791 struct mbuf *m; 2792 int flid, cidx, len, next; 2793 2794 map = NULL; 2795 flid = irf->irf_flid; 2796 cidx = irf->irf_idx; 2797 fl = &rxq->ifr_fl[flid]; 2798 sd->ifsd_fl = fl; 2799 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2800 fl->ifl_credits--; 2801 #if MEMORY_LOGGING 2802 fl->ifl_m_dequeued++; 2803 #endif 2804 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2805 prefetch_pkts(fl, cidx); 2806 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size - 1); 2807 prefetch(&fl->ifl_sds.ifsd_map[next]); 2808 map = fl->ifl_sds.ifsd_map[cidx]; 2809 2810 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2811 2812 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2813 irf->irf_len != 0) { 2814 payload = *sd->ifsd_cl; 2815 payload += ri->iri_pad; 2816 len = ri->iri_len - ri->iri_pad; 2817 *pf_rv = pfil_mem_in(rxq->pfil, payload, len, ri->iri_ifp, &m); 2818 switch (*pf_rv) { 2819 case PFIL_DROPPED: 2820 case PFIL_CONSUMED: 2821 /* 2822 * The filter ate it. Everything is recycled. 2823 */ 2824 m = NULL; 2825 unload = 0; 2826 break; 2827 case PFIL_REALLOCED: 2828 /* 2829 * The filter copied it. Everything is recycled. 2830 * 'm' points at new mbuf. 2831 */ 2832 unload = 0; 2833 break; 2834 case PFIL_PASS: 2835 /* 2836 * Filter said it was OK, so receive like 2837 * normal 2838 */ 2839 m = fl->ifl_sds.ifsd_m[cidx]; 2840 fl->ifl_sds.ifsd_m[cidx] = NULL; 2841 break; 2842 default: 2843 MPASS(0); 2844 } 2845 } else { 2846 m = fl->ifl_sds.ifsd_m[cidx]; 2847 fl->ifl_sds.ifsd_m[cidx] = NULL; 2848 if (pf_rv != NULL) 2849 *pf_rv = PFIL_PASS; 2850 } 2851 2852 if (unload && irf->irf_len != 0) 2853 bus_dmamap_unload(fl->ifl_buf_tag, map); 2854 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size - 1); 2855 if (__predict_false(fl->ifl_cidx == 0)) 2856 fl->ifl_gen = 0; 2857 bit_clear(fl->ifl_rx_bitmap, cidx); 2858 return (m); 2859 } 2860 2861 static struct mbuf * 2862 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2863 { 2864 struct mbuf *m, *mh, *mt; 2865 caddr_t cl; 2866 int *pf_rv_ptr, flags, i, padlen; 2867 bool consumed; 2868 2869 i = 0; 2870 mh = NULL; 2871 consumed = false; 2872 *pf_rv = PFIL_PASS; 2873 pf_rv_ptr = pf_rv; 2874 do { 2875 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2876 pf_rv_ptr, ri); 2877 2878 MPASS(*sd->ifsd_cl != NULL); 2879 2880 /* 2881 * Exclude zero-length frags & frags from 2882 * packets the filter has consumed or dropped 2883 */ 2884 if (ri->iri_frags[i].irf_len == 0 || consumed || 2885 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2886 if (mh == NULL) { 2887 consumed = true; 2888 pf_rv_ptr = NULL; 2889 } 2890 /* XXX we can save the cluster here, but not the mbuf */ 2891 if (m != NULL) { 2892 m_init(m, M_NOWAIT, MT_DATA, 0); 2893 m_free(m); 2894 } 2895 continue; 2896 } 2897 if (mh == NULL) { 2898 flags = M_PKTHDR | M_EXT; 2899 mh = mt = m; 2900 padlen = ri->iri_pad; 2901 } else { 2902 flags = M_EXT; 2903 mt->m_next = m; 2904 mt = m; 2905 /* assuming padding is only on the first fragment */ 2906 padlen = 0; 2907 } 2908 cl = *sd->ifsd_cl; 2909 *sd->ifsd_cl = NULL; 2910 2911 /* Can these two be made one ? */ 2912 m_init(m, M_NOWAIT, MT_DATA, flags); 2913 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2914 /* 2915 * These must follow m_init and m_cljset 2916 */ 2917 m->m_data += padlen; 2918 ri->iri_len -= padlen; 2919 m->m_len = ri->iri_frags[i].irf_len; 2920 } while (++i < ri->iri_nfrags); 2921 2922 return (mh); 2923 } 2924 2925 /* 2926 * Process one software descriptor 2927 */ 2928 static struct mbuf * 2929 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2930 { 2931 struct if_rxsd sd; 2932 struct mbuf *m; 2933 int pf_rv; 2934 2935 /* should I merge this back in now that the two paths are basically duplicated? */ 2936 if (ri->iri_nfrags == 1 && 2937 ri->iri_frags[0].irf_len != 0 && 2938 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2939 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2940 &pf_rv, ri); 2941 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2942 return (m); 2943 if (pf_rv == PFIL_PASS) { 2944 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2945 #ifndef __NO_STRICT_ALIGNMENT 2946 if (!IP_ALIGNED(m) && ri->iri_pad == 0) 2947 m->m_data += 2; 2948 #endif 2949 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2950 m->m_len = ri->iri_frags[0].irf_len; 2951 m->m_data += ri->iri_pad; 2952 ri->iri_len -= ri->iri_pad; 2953 } 2954 } else { 2955 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2956 if (m == NULL) 2957 return (NULL); 2958 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2959 return (m); 2960 } 2961 m->m_pkthdr.len = ri->iri_len; 2962 m->m_pkthdr.rcvif = ri->iri_ifp; 2963 m->m_flags |= ri->iri_flags; 2964 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2965 m->m_pkthdr.flowid = ri->iri_flowid; 2966 #ifdef NUMA 2967 m->m_pkthdr.numa_domain = if_getnumadomain(ri->iri_ifp); 2968 #endif 2969 M_HASHTYPE_SET(m, ri->iri_rsstype); 2970 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2971 m->m_pkthdr.csum_data = ri->iri_csum_data; 2972 return (m); 2973 } 2974 2975 static void 2976 _task_fn_rx_watchdog(void *context) 2977 { 2978 iflib_rxq_t rxq = context; 2979 2980 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2981 } 2982 2983 static uint8_t 2984 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2985 { 2986 if_t ifp; 2987 if_ctx_t ctx = rxq->ifr_ctx; 2988 if_shared_ctx_t sctx = ctx->ifc_sctx; 2989 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2990 int avail, i; 2991 qidx_t *cidxp; 2992 struct if_rxd_info ri; 2993 int err, budget_left, rx_bytes, rx_pkts; 2994 iflib_fl_t fl; 2995 #if defined(INET6) || defined(INET) 2996 int lro_enabled; 2997 #endif 2998 uint8_t retval = 0; 2999 3000 /* 3001 * XXX early demux data packets so that if_input processing only handles 3002 * acks in interrupt context 3003 */ 3004 struct mbuf *m, *mh, *mt; 3005 3006 NET_EPOCH_ASSERT(); 3007 3008 ifp = ctx->ifc_ifp; 3009 mh = mt = NULL; 3010 MPASS(budget > 0); 3011 rx_pkts = rx_bytes = 0; 3012 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 3013 cidxp = &rxq->ifr_cq_cidx; 3014 else 3015 cidxp = &rxq->ifr_fl[0].ifl_cidx; 3016 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 3017 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3018 retval |= iflib_fl_refill_all(ctx, fl); 3019 DBG_COUNTER_INC(rx_unavail); 3020 return (retval); 3021 } 3022 3023 #if defined(INET6) || defined(INET) 3024 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 3025 #endif 3026 3027 /* pfil needs the vnet to be set */ 3028 CURVNET_SET_QUIET(if_getvnet(ifp)); 3029 for (budget_left = budget; budget_left > 0 && avail > 0;) { 3030 if (__predict_false(!CTX_ACTIVE(ctx))) { 3031 DBG_COUNTER_INC(rx_ctx_inactive); 3032 break; 3033 } 3034 /* 3035 * Reset client set fields to their default values 3036 */ 3037 memset(&ri, 0, sizeof(ri)); 3038 ri.iri_qsidx = rxq->ifr_id; 3039 ri.iri_cidx = *cidxp; 3040 ri.iri_ifp = ifp; 3041 ri.iri_frags = rxq->ifr_frags; 3042 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 3043 3044 if (err) { 3045 CURVNET_RESTORE(); 3046 goto err; 3047 } 3048 rx_pkts += 1; 3049 rx_bytes += ri.iri_len; 3050 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 3051 *cidxp = ri.iri_cidx; 3052 /* Update our consumer index */ 3053 /* XXX NB: shurd - check if this is still safe */ 3054 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 3055 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 3056 /* was this only a completion queue message? */ 3057 if (__predict_false(ri.iri_nfrags == 0)) 3058 continue; 3059 } 3060 MPASS(ri.iri_nfrags != 0); 3061 MPASS(ri.iri_len != 0); 3062 3063 /* will advance the cidx on the corresponding free lists */ 3064 m = iflib_rxd_pkt_get(rxq, &ri); 3065 avail--; 3066 budget_left--; 3067 if (avail == 0 && budget_left) 3068 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 3069 3070 if (__predict_false(m == NULL)) 3071 continue; 3072 3073 #ifndef __NO_STRICT_ALIGNMENT 3074 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 3075 continue; 3076 #endif 3077 #if defined(INET6) || defined(INET) 3078 if (lro_enabled) { 3079 tcp_lro_queue_mbuf(&rxq->ifr_lc, m); 3080 continue; 3081 } 3082 #endif 3083 3084 if (mh == NULL) 3085 mh = mt = m; 3086 else { 3087 mt->m_nextpkt = m; 3088 mt = m; 3089 } 3090 } 3091 CURVNET_RESTORE(); 3092 /* make sure that we can refill faster than drain */ 3093 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3094 retval |= iflib_fl_refill_all(ctx, fl); 3095 3096 if (mh != NULL) { 3097 if_input(ifp, mh); 3098 DBG_COUNTER_INC(rx_if_input); 3099 } 3100 3101 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 3102 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 3103 3104 /* 3105 * Flush any outstanding LRO work 3106 */ 3107 #if defined(INET6) || defined(INET) 3108 tcp_lro_flush_all(&rxq->ifr_lc); 3109 #endif 3110 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 3111 retval |= IFLIB_RXEOF_MORE; 3112 return (retval); 3113 err: 3114 STATE_LOCK(ctx); 3115 ctx->ifc_flags |= IFC_DO_RESET; 3116 iflib_admin_intr_deferred(ctx); 3117 STATE_UNLOCK(ctx); 3118 return (0); 3119 } 3120 3121 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq) - 1) 3122 static inline qidx_t 3123 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 3124 { 3125 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3126 qidx_t minthresh = txq->ift_size / 8; 3127 if (in_use > 4 * minthresh) 3128 return (notify_count); 3129 if (in_use > 2 * minthresh) 3130 return (notify_count >> 1); 3131 if (in_use > minthresh) 3132 return (notify_count >> 3); 3133 return (0); 3134 } 3135 3136 static inline qidx_t 3137 txq_max_rs_deferred(iflib_txq_t txq) 3138 { 3139 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3140 qidx_t minthresh = txq->ift_size / 8; 3141 if (txq->ift_in_use > 4 * minthresh) 3142 return (notify_count); 3143 if (txq->ift_in_use > 2 * minthresh) 3144 return (notify_count >> 1); 3145 if (txq->ift_in_use > minthresh) 3146 return (notify_count >> 2); 3147 return (2); 3148 } 3149 3150 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 3151 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 3152 3153 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 3154 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 3155 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 3156 3157 /* forward compatibility for cxgb */ 3158 #define FIRST_QSET(ctx) 0 3159 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3160 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3161 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3162 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3163 3164 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3165 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3166 3167 static inline bool 3168 iflib_txd_db_check(iflib_txq_t txq, int ring) 3169 { 3170 if_ctx_t ctx = txq->ift_ctx; 3171 qidx_t dbval, max; 3172 3173 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use); 3174 3175 /* force || threshold exceeded || at the edge of the ring */ 3176 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx))) { 3177 3178 /* 3179 * 'npending' is used if the card's doorbell is in terms of the number of descriptors 3180 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the 3181 * producer index explicitly (INTC). 3182 */ 3183 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3184 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3185 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3186 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3187 3188 /* 3189 * Absent bugs there are zero packets pending so reset pending counts to zero. 3190 */ 3191 txq->ift_db_pending = txq->ift_npending = 0; 3192 return (true); 3193 } 3194 return (false); 3195 } 3196 3197 #ifdef PKT_DEBUG 3198 static void 3199 print_pkt(if_pkt_info_t pi) 3200 { 3201 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3202 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3203 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3204 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3205 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3206 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3207 } 3208 #endif 3209 3210 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3211 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3212 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3213 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3214 3215 /** 3216 * Parses out ethernet header information in the given mbuf. 3217 * Returns in pi: ipi_etype (EtherType) and ipi_ehdrlen (Ethernet header length) 3218 * 3219 * This will account for the VLAN header if present. 3220 * 3221 * XXX: This doesn't handle QinQ, which could prevent TX offloads for those 3222 * types of packets. 3223 */ 3224 static int 3225 iflib_parse_ether_header(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3226 { 3227 struct ether_vlan_header *eh; 3228 struct mbuf *m; 3229 3230 m = *mp; 3231 if (__predict_false(m->m_len < sizeof(*eh))) { 3232 (*pullups)++; 3233 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3234 return (ENOMEM); 3235 } 3236 eh = mtod(m, struct ether_vlan_header *); 3237 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3238 pi->ipi_etype = ntohs(eh->evl_proto); 3239 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3240 } else { 3241 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3242 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3243 } 3244 *mp = m; 3245 3246 return (0); 3247 } 3248 3249 /** 3250 * Parse up to the L3 header and extract IPv4/IPv6 header information into pi. 3251 * Currently this information includes: IP ToS value, IP header version/presence 3252 * 3253 * This is missing some checks and doesn't edit the packet content as it goes, 3254 * unlike iflib_parse_header(), in order to keep the amount of code here minimal. 3255 */ 3256 static int 3257 iflib_parse_header_partial(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3258 { 3259 struct mbuf *m; 3260 int err; 3261 3262 *pullups = 0; 3263 m = *mp; 3264 if (!M_WRITABLE(m)) { 3265 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3266 return (ENOMEM); 3267 } else { 3268 m_freem(*mp); 3269 DBG_COUNTER_INC(tx_frees); 3270 *mp = m; 3271 } 3272 } 3273 3274 /* Fills out pi->ipi_etype */ 3275 err = iflib_parse_ether_header(pi, mp, pullups); 3276 if (err) 3277 return (err); 3278 m = *mp; 3279 3280 switch (pi->ipi_etype) { 3281 #ifdef INET 3282 case ETHERTYPE_IP: 3283 { 3284 struct mbuf *n; 3285 struct ip *ip = NULL; 3286 int miniplen; 3287 3288 miniplen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip)); 3289 if (__predict_false(m->m_len < miniplen)) { 3290 /* 3291 * Check for common case where the first mbuf only contains 3292 * the Ethernet header 3293 */ 3294 if (m->m_len == pi->ipi_ehdrlen) { 3295 n = m->m_next; 3296 MPASS(n); 3297 /* If next mbuf contains at least the minimal IP header, then stop */ 3298 if (n->m_len >= sizeof(*ip)) { 3299 ip = (struct ip *)n->m_data; 3300 } else { 3301 (*pullups)++; 3302 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3303 return (ENOMEM); 3304 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3305 } 3306 } else { 3307 (*pullups)++; 3308 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3309 return (ENOMEM); 3310 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3311 } 3312 } else { 3313 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3314 } 3315 3316 /* Have the IPv4 header w/ no options here */ 3317 pi->ipi_ip_hlen = ip->ip_hl << 2; 3318 pi->ipi_ipproto = ip->ip_p; 3319 pi->ipi_ip_tos = ip->ip_tos; 3320 pi->ipi_flags |= IPI_TX_IPV4; 3321 3322 break; 3323 } 3324 #endif 3325 #ifdef INET6 3326 case ETHERTYPE_IPV6: 3327 { 3328 struct ip6_hdr *ip6; 3329 3330 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3331 (*pullups)++; 3332 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3333 return (ENOMEM); 3334 } 3335 ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3336 3337 /* Have the IPv6 fixed header here */ 3338 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3339 pi->ipi_ipproto = ip6->ip6_nxt; 3340 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3341 pi->ipi_flags |= IPI_TX_IPV6; 3342 3343 break; 3344 } 3345 #endif 3346 default: 3347 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3348 pi->ipi_ip_hlen = 0; 3349 break; 3350 } 3351 *mp = m; 3352 3353 return (0); 3354 3355 } 3356 3357 static int 3358 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3359 { 3360 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3361 struct mbuf *m; 3362 int err; 3363 3364 m = *mp; 3365 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3366 M_WRITABLE(m) == 0) { 3367 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3368 return (ENOMEM); 3369 } else { 3370 m_freem(*mp); 3371 DBG_COUNTER_INC(tx_frees); 3372 *mp = m; 3373 } 3374 } 3375 3376 /* Fills out pi->ipi_etype */ 3377 err = iflib_parse_ether_header(pi, mp, &txq->ift_pullups); 3378 if (__predict_false(err)) 3379 return (err); 3380 m = *mp; 3381 3382 switch (pi->ipi_etype) { 3383 #ifdef INET 3384 case ETHERTYPE_IP: 3385 { 3386 struct ip *ip; 3387 struct tcphdr *th; 3388 uint8_t hlen; 3389 3390 hlen = pi->ipi_ehdrlen + sizeof(*ip); 3391 if (__predict_false(m->m_len < hlen)) { 3392 txq->ift_pullups++; 3393 if (__predict_false((m = m_pullup(m, hlen)) == NULL)) 3394 return (ENOMEM); 3395 } 3396 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3397 hlen = pi->ipi_ehdrlen + (ip->ip_hl << 2); 3398 if (ip->ip_p == IPPROTO_TCP) { 3399 hlen += sizeof(*th); 3400 th = (struct tcphdr *)((char *)ip + (ip->ip_hl << 2)); 3401 } else if (ip->ip_p == IPPROTO_UDP) { 3402 hlen += sizeof(struct udphdr); 3403 } 3404 if (__predict_false(m->m_len < hlen)) { 3405 txq->ift_pullups++; 3406 if ((m = m_pullup(m, hlen)) == NULL) 3407 return (ENOMEM); 3408 } 3409 pi->ipi_ip_hlen = ip->ip_hl << 2; 3410 pi->ipi_ipproto = ip->ip_p; 3411 pi->ipi_ip_tos = ip->ip_tos; 3412 pi->ipi_flags |= IPI_TX_IPV4; 3413 3414 /* TCP checksum offload may require TCP header length */ 3415 if (IS_TX_OFFLOAD4(pi)) { 3416 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3417 pi->ipi_tcp_hflags = tcp_get_flags(th); 3418 pi->ipi_tcp_hlen = th->th_off << 2; 3419 pi->ipi_tcp_seq = th->th_seq; 3420 } 3421 if (IS_TSO4(pi)) { 3422 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3423 return (ENXIO); 3424 /* 3425 * TSO always requires hardware checksum offload. 3426 */ 3427 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3428 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3429 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3430 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3431 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3432 ip->ip_sum = 0; 3433 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3434 } 3435 } 3436 } 3437 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3438 ip->ip_sum = 0; 3439 3440 break; 3441 } 3442 #endif 3443 #ifdef INET6 3444 case ETHERTYPE_IPV6: 3445 { 3446 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3447 struct tcphdr *th; 3448 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3449 3450 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3451 txq->ift_pullups++; 3452 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3453 return (ENOMEM); 3454 } 3455 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3456 3457 /* XXX-BZ this will go badly in case of ext hdrs. */ 3458 pi->ipi_ipproto = ip6->ip6_nxt; 3459 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3460 pi->ipi_flags |= IPI_TX_IPV6; 3461 3462 /* TCP checksum offload may require TCP header length */ 3463 if (IS_TX_OFFLOAD6(pi)) { 3464 if (pi->ipi_ipproto == IPPROTO_TCP) { 3465 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3466 txq->ift_pullups++; 3467 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3468 return (ENOMEM); 3469 } 3470 pi->ipi_tcp_hflags = tcp_get_flags(th); 3471 pi->ipi_tcp_hlen = th->th_off << 2; 3472 pi->ipi_tcp_seq = th->th_seq; 3473 } 3474 if (IS_TSO6(pi)) { 3475 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3476 return (ENXIO); 3477 /* 3478 * TSO always requires hardware checksum offload. 3479 */ 3480 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3481 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3482 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3483 } 3484 } 3485 break; 3486 } 3487 #endif 3488 default: 3489 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3490 pi->ipi_ip_hlen = 0; 3491 break; 3492 } 3493 *mp = m; 3494 3495 return (0); 3496 } 3497 3498 /* 3499 * If dodgy hardware rejects the scatter gather chain we've handed it 3500 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3501 * m_defrag'd mbufs 3502 */ 3503 static __noinline struct mbuf * 3504 iflib_remove_mbuf(iflib_txq_t txq) 3505 { 3506 int ntxd, pidx; 3507 struct mbuf *m, **ifsd_m; 3508 3509 ifsd_m = txq->ift_sds.ifsd_m; 3510 ntxd = txq->ift_size; 3511 pidx = txq->ift_pidx & (ntxd - 1); 3512 ifsd_m = txq->ift_sds.ifsd_m; 3513 m = IFLIB_GET_MBUF(ifsd_m[pidx]); 3514 ifsd_m[pidx] = NULL; 3515 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3516 if (txq->ift_sds.ifsd_tso_map != NULL) 3517 bus_dmamap_unload(txq->ift_tso_buf_tag, 3518 txq->ift_sds.ifsd_tso_map[pidx]); 3519 #if MEMORY_LOGGING 3520 txq->ift_dequeued++; 3521 #endif 3522 return (m); 3523 } 3524 3525 /* 3526 * Pad an mbuf to ensure a minimum ethernet frame size. 3527 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3528 */ 3529 static __noinline int 3530 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3531 { 3532 /* 3533 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3534 * and ARP message is the smallest common payload I can think of 3535 */ 3536 static char pad[18]; /* just zeros */ 3537 int n; 3538 struct mbuf *new_head; 3539 3540 if (!M_WRITABLE(*m_head)) { 3541 new_head = m_dup(*m_head, M_NOWAIT); 3542 if (new_head == NULL) { 3543 m_freem(*m_head); 3544 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3545 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3546 DBG_COUNTER_INC(tx_frees); 3547 return (ENOMEM); 3548 } 3549 m_freem(*m_head); 3550 *m_head = new_head; 3551 } 3552 3553 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3554 n > 0; n -= sizeof(pad)) 3555 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3556 break; 3557 3558 if (n > 0) { 3559 m_freem(*m_head); 3560 device_printf(dev, "cannot pad short frame\n"); 3561 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3562 DBG_COUNTER_INC(tx_frees); 3563 return (ENOBUFS); 3564 } 3565 3566 return (0); 3567 } 3568 3569 static int 3570 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp, int *obytes, int *opkts) 3571 { 3572 if_ctx_t ctx; 3573 if_shared_ctx_t sctx; 3574 if_softc_ctx_t scctx; 3575 bus_dma_tag_t buf_tag; 3576 bus_dma_segment_t *segs; 3577 struct mbuf *m_head, **ifsd_m; 3578 bus_dmamap_t map; 3579 struct if_pkt_info pi; 3580 uintptr_t flags; 3581 int remap = 0; 3582 int err, nsegs, ndesc, max_segs, pidx; 3583 3584 ctx = txq->ift_ctx; 3585 sctx = ctx->ifc_sctx; 3586 scctx = &ctx->ifc_softc_ctx; 3587 segs = txq->ift_segs; 3588 m_head = *m_headp; 3589 map = NULL; 3590 3591 /* 3592 * If we're doing TSO the next descriptor to clean may be quite far ahead 3593 */ 3594 pidx = txq->ift_pidx; 3595 map = txq->ift_sds.ifsd_map[pidx]; 3596 ifsd_m = txq->ift_sds.ifsd_m; 3597 3598 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3599 buf_tag = txq->ift_tso_buf_tag; 3600 max_segs = scctx->isc_tx_tso_segments_max; 3601 map = txq->ift_sds.ifsd_tso_map[pidx]; 3602 MPASS(buf_tag != NULL); 3603 MPASS(max_segs > 0); 3604 flags = IFLIB_TSO; 3605 } else { 3606 buf_tag = txq->ift_buf_tag; 3607 max_segs = scctx->isc_tx_nsegments; 3608 map = txq->ift_sds.ifsd_map[pidx]; 3609 flags = IFLIB_NO_TSO; 3610 } 3611 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3612 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3613 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3614 if (err) { 3615 DBG_COUNTER_INC(encap_txd_encap_fail); 3616 return (err); 3617 } 3618 } 3619 m_head = *m_headp; 3620 3621 memset(&pi, 0, sizeof(pi)); 3622 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG | M_BCAST | M_MCAST)); 3623 pi.ipi_pidx = pidx; 3624 pi.ipi_qsidx = txq->ift_id; 3625 pi.ipi_len = m_head->m_pkthdr.len; 3626 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3627 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3628 3629 /* deliberate bitwise OR to make one condition */ 3630 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3631 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3632 DBG_COUNTER_INC(encap_txd_encap_fail); 3633 return (err); 3634 } 3635 m_head = *m_headp; 3636 } 3637 3638 retry: 3639 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3640 BUS_DMA_NOWAIT); 3641 defrag: 3642 if (__predict_false(err)) { 3643 switch (err) { 3644 case EFBIG: 3645 /* try collapse once and defrag once */ 3646 if (remap == 0) { 3647 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3648 /* try defrag if collapsing fails */ 3649 if (m_head == NULL) 3650 remap++; 3651 } 3652 if (remap == 1) { 3653 txq->ift_mbuf_defrag++; 3654 m_head = m_defrag(*m_headp, M_NOWAIT); 3655 } 3656 /* 3657 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3658 * failed to map an mbuf that was run through m_defrag 3659 */ 3660 MPASS(remap <= 1); 3661 if (__predict_false(m_head == NULL || remap > 1)) 3662 goto defrag_failed; 3663 remap++; 3664 *m_headp = m_head; 3665 goto retry; 3666 break; 3667 case ENOMEM: 3668 txq->ift_no_tx_dma_setup++; 3669 break; 3670 default: 3671 txq->ift_no_tx_dma_setup++; 3672 m_freem(*m_headp); 3673 DBG_COUNTER_INC(tx_frees); 3674 *m_headp = NULL; 3675 break; 3676 } 3677 txq->ift_map_failed++; 3678 DBG_COUNTER_INC(encap_load_mbuf_fail); 3679 DBG_COUNTER_INC(encap_txd_encap_fail); 3680 return (err); 3681 } 3682 ifsd_m[pidx] = IFLIB_SAVE_MBUF(m_head, flags); 3683 if (m_head->m_pkthdr.csum_flags & CSUM_SND_TAG) 3684 pi.ipi_mbuf = m_head; 3685 else 3686 pi.ipi_mbuf = NULL; 3687 /* 3688 * XXX assumes a 1 to 1 relationship between segments and 3689 * descriptors - this does not hold true on all drivers, e.g. 3690 * cxgb 3691 */ 3692 if (__predict_false(nsegs > TXQ_AVAIL(txq))) { 3693 iflib_completed_tx_reclaim_force(txq); 3694 if (__predict_false(nsegs > TXQ_AVAIL(txq))) { 3695 txq->ift_no_desc_avail++; 3696 bus_dmamap_unload(buf_tag, map); 3697 DBG_COUNTER_INC(encap_txq_avail_fail); 3698 DBG_COUNTER_INC(encap_txd_encap_fail); 3699 if (ctx->ifc_sysctl_simple_tx) { 3700 *m_headp = m_head = iflib_remove_mbuf(txq); 3701 m_freem(*m_headp); 3702 DBG_COUNTER_INC(tx_frees); 3703 *m_headp = NULL; 3704 } 3705 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3706 GROUPTASK_ENQUEUE(&txq->ift_task); 3707 return (ENOBUFS); 3708 } 3709 } 3710 /* 3711 * On Intel cards we can greatly reduce the number of TX interrupts 3712 * we see by only setting report status on every Nth descriptor. 3713 * However, this also means that the driver will need to keep track 3714 * of the descriptors that RS was set on to check them for the DD bit. 3715 */ 3716 txq->ift_rs_pending += nsegs + 1; 3717 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3718 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx)) { 3719 pi.ipi_flags |= IPI_TX_INTR; 3720 txq->ift_rs_pending = 0; 3721 } 3722 3723 pi.ipi_segs = segs; 3724 pi.ipi_nsegs = nsegs; 3725 3726 MPASS(pidx >= 0 && pidx < txq->ift_size); 3727 #ifdef PKT_DEBUG 3728 print_pkt(&pi); 3729 #endif 3730 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3731 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3732 DBG_COUNTER_INC(tx_encap); 3733 MPASS(pi.ipi_new_pidx < txq->ift_size); 3734 3735 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3736 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3737 ndesc += txq->ift_size; 3738 txq->ift_gen = 1; 3739 } 3740 /* 3741 * drivers can need up to ift_pad sentinels 3742 */ 3743 MPASS(ndesc <= pi.ipi_nsegs + txq->ift_pad); 3744 MPASS(pi.ipi_new_pidx != pidx); 3745 MPASS(ndesc > 0); 3746 txq->ift_in_use += ndesc; 3747 txq->ift_db_pending += ndesc; 3748 3749 /* 3750 * We update the last software descriptor again here because there may 3751 * be a sentinel and/or there may be more mbufs than segments 3752 */ 3753 txq->ift_pidx = pi.ipi_new_pidx; 3754 txq->ift_npending += pi.ipi_ndescs; 3755 3756 /* 3757 * Update packets / bytes sent 3758 */ 3759 if (flags & IFLIB_TSO) { 3760 int hlen = pi.ipi_ehdrlen + pi.ipi_ip_hlen + pi.ipi_tcp_hlen; 3761 int tsolen = pi.ipi_len - hlen; 3762 int nsegs = (tsolen + pi.ipi_tso_segsz - 1) / pi.ipi_tso_segsz; 3763 *obytes += tsolen + nsegs * hlen; 3764 *opkts += nsegs; 3765 } else { 3766 *obytes += pi.ipi_len; 3767 *opkts += 1; 3768 } 3769 } else { 3770 *m_headp = m_head = iflib_remove_mbuf(txq); 3771 if (err == EFBIG) { 3772 txq->ift_txd_encap_efbig++; 3773 if (remap < 2) { 3774 remap = 1; 3775 goto defrag; 3776 } 3777 goto defrag_failed; 3778 } 3779 goto out_with_error; 3780 } 3781 /* 3782 * err can't possibly be non-zero here, so we don't neet to test it 3783 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3784 */ 3785 return (err); 3786 3787 defrag_failed: 3788 err = ENOMEM; 3789 txq->ift_mbuf_defrag_failed++; 3790 out_with_error: 3791 txq->ift_map_failed++; 3792 m_freem(*m_headp); 3793 DBG_COUNTER_INC(tx_frees); 3794 *m_headp = NULL; 3795 DBG_COUNTER_INC(encap_txd_encap_fail); 3796 return (err); 3797 } 3798 3799 static void 3800 iflib_tx_desc_free(iflib_txq_t txq, int n, struct mbuf **m_defer) 3801 { 3802 uint32_t qsize, cidx, gen; 3803 struct mbuf *m, **ifsd_m; 3804 uintptr_t flags; 3805 3806 cidx = txq->ift_cidx; 3807 gen = txq->ift_gen; 3808 qsize = txq->ift_size; 3809 ifsd_m =txq->ift_sds.ifsd_m; 3810 3811 while (n-- > 0) { 3812 if ((m = IFLIB_GET_MBUF(ifsd_m[cidx])) != NULL) { 3813 flags = IFLIB_GET_FLAGS(ifsd_m[cidx]); 3814 MPASS(flags != 0); 3815 if (flags & IFLIB_TSO) { 3816 bus_dmamap_sync(txq->ift_tso_buf_tag, 3817 txq->ift_sds.ifsd_tso_map[cidx], 3818 BUS_DMASYNC_POSTWRITE); 3819 bus_dmamap_unload(txq->ift_tso_buf_tag, 3820 txq->ift_sds.ifsd_tso_map[cidx]); 3821 } else { 3822 bus_dmamap_sync(txq->ift_buf_tag, 3823 txq->ift_sds.ifsd_map[cidx], 3824 BUS_DMASYNC_POSTWRITE); 3825 bus_dmamap_unload(txq->ift_buf_tag, 3826 txq->ift_sds.ifsd_map[cidx]); 3827 } 3828 /* XXX we don't support any drivers that batch packets yet */ 3829 MPASS(m->m_nextpkt == NULL); 3830 if (m_defer == NULL) { 3831 m_freem(m); 3832 } else if (m != NULL) { 3833 *m_defer = m; 3834 m_defer++; 3835 } 3836 ifsd_m[cidx] = NULL; 3837 #if MEMORY_LOGGING 3838 txq->ift_dequeued++; 3839 #endif 3840 DBG_COUNTER_INC(tx_frees); 3841 } 3842 if (__predict_false(++cidx == qsize)) { 3843 cidx = 0; 3844 gen = 0; 3845 } 3846 } 3847 txq->ift_cidx = cidx; 3848 txq->ift_gen = gen; 3849 } 3850 3851 static __inline int 3852 iflib_txq_can_reclaim(iflib_txq_t txq) 3853 { 3854 int reclaim, thresh; 3855 3856 thresh = txq->ift_reclaim_thresh; 3857 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3858 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3859 3860 if (ticks <= (txq->ift_last_reclaim + txq->ift_reclaim_ticks) && 3861 txq->ift_in_use < thresh) 3862 return (false); 3863 iflib_tx_credits_update(txq->ift_ctx, txq); 3864 reclaim = DESC_RECLAIMABLE(txq); 3865 if (reclaim <= thresh) { 3866 #ifdef INVARIANTS 3867 if (iflib_verbose_debug) { 3868 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __func__, 3869 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3870 reclaim, thresh); 3871 } 3872 #endif 3873 return (0); 3874 } 3875 return (reclaim); 3876 } 3877 3878 static __inline void 3879 _iflib_completed_tx_reclaim(iflib_txq_t txq, struct mbuf **m_defer, int reclaim) 3880 { 3881 txq->ift_last_reclaim = ticks; 3882 iflib_tx_desc_free(txq, reclaim, m_defer); 3883 txq->ift_cleaned += reclaim; 3884 txq->ift_in_use -= reclaim; 3885 } 3886 3887 static __inline int 3888 iflib_completed_tx_reclaim(iflib_txq_t txq, struct mbuf **m_defer) 3889 { 3890 int reclaim; 3891 3892 reclaim = iflib_txq_can_reclaim(txq); 3893 if (reclaim == 0) 3894 return (0); 3895 _iflib_completed_tx_reclaim(txq, m_defer, reclaim); 3896 return (reclaim); 3897 } 3898 3899 /* 3900 * Reclaim any transmit descriptors possible, ignoring coalescing 3901 */ 3902 static __inline void 3903 iflib_completed_tx_reclaim_force(iflib_txq_t txq) 3904 { 3905 int reclaim; 3906 3907 iflib_tx_credits_update(txq->ift_ctx, txq); 3908 reclaim = DESC_RECLAIMABLE(txq); 3909 if (reclaim != 0) 3910 _iflib_completed_tx_reclaim(txq, NULL, reclaim); 3911 } 3912 3913 static struct mbuf ** 3914 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3915 { 3916 int next, size; 3917 struct mbuf **items; 3918 3919 size = r->size; 3920 next = (cidx + CACHE_PTR_INCREMENT) & (size - 1); 3921 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3922 3923 prefetch(items[(cidx + offset) & (size - 1)]); 3924 if (remaining > 1) { 3925 prefetch2cachelines(&items[next]); 3926 prefetch2cachelines(items[(cidx + offset + 1) & (size - 1)]); 3927 prefetch2cachelines(items[(cidx + offset + 2) & (size - 1)]); 3928 prefetch2cachelines(items[(cidx + offset + 3) & (size - 1)]); 3929 } 3930 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size - 1)])); 3931 } 3932 3933 static void 3934 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3935 { 3936 3937 ifmp_ring_check_drainage(txq->ift_br, budget); 3938 } 3939 3940 static uint32_t 3941 iflib_txq_can_drain(struct ifmp_ring *r) 3942 { 3943 iflib_txq_t txq = r->cookie; 3944 if_ctx_t ctx = txq->ift_ctx; 3945 3946 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx)) 3947 return (1); 3948 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3949 BUS_DMASYNC_POSTREAD); 3950 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3951 false)); 3952 } 3953 3954 static uint32_t 3955 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3956 { 3957 iflib_txq_t txq = r->cookie; 3958 if_ctx_t ctx = txq->ift_ctx; 3959 if_t ifp = ctx->ifc_ifp; 3960 struct mbuf *m, **mp; 3961 int avail, bytes_sent, consumed, count, err, i; 3962 int mcast_sent, pkt_sent, reclaimed; 3963 bool do_prefetch, rang, ring; 3964 3965 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3966 !LINK_ACTIVE(ctx))) { 3967 DBG_COUNTER_INC(txq_drain_notready); 3968 return (0); 3969 } 3970 reclaimed = iflib_completed_tx_reclaim(txq, NULL); 3971 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending); 3972 avail = IDXDIFF(pidx, cidx, r->size); 3973 3974 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3975 /* 3976 * The driver is unloading so we need to free all pending packets. 3977 */ 3978 DBG_COUNTER_INC(txq_drain_flushing); 3979 for (i = 0; i < avail; i++) { 3980 if (__predict_true(r->items[(cidx + i) & (r->size - 1)] != (void *)txq)) 3981 m_freem(r->items[(cidx + i) & (r->size - 1)]); 3982 r->items[(cidx + i) & (r->size - 1)] = NULL; 3983 } 3984 return (avail); 3985 } 3986 3987 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3988 CALLOUT_LOCK(txq); 3989 callout_stop(&txq->ift_timer); 3990 CALLOUT_UNLOCK(txq); 3991 DBG_COUNTER_INC(txq_drain_oactive); 3992 return (0); 3993 } 3994 3995 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3996 count = MIN(avail, TX_BATCH_SIZE); 3997 #ifdef INVARIANTS 3998 if (iflib_verbose_debug) 3999 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __func__, 4000 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 4001 #endif 4002 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 4003 err = 0; 4004 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx); i++) { 4005 int rem = do_prefetch ? count - i : 0; 4006 4007 mp = _ring_peek_one(r, cidx, i, rem); 4008 MPASS(mp != NULL && *mp != NULL); 4009 4010 /* 4011 * Completion interrupts will use the address of the txq 4012 * as a sentinel to enqueue _something_ in order to acquire 4013 * the lock on the mp_ring (there's no direct lock call). 4014 * We obviously whave to check for these sentinel cases 4015 * and skip them. 4016 */ 4017 if (__predict_false(*mp == (struct mbuf *)txq)) { 4018 consumed++; 4019 continue; 4020 } 4021 err = iflib_encap(txq, mp, &bytes_sent, &pkt_sent); 4022 if (__predict_false(err)) { 4023 /* no room - bail out */ 4024 if (err == ENOBUFS) 4025 break; 4026 consumed++; 4027 /* we can't send this packet - skip it */ 4028 continue; 4029 } 4030 consumed++; 4031 m = *mp; 4032 DBG_COUNTER_INC(tx_sent); 4033 mcast_sent += !!(m->m_flags & M_MCAST); 4034 4035 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))) 4036 break; 4037 ETHER_BPF_MTAP(ifp, m); 4038 rang = iflib_txd_db_check(txq, false); 4039 } 4040 4041 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 4042 ring = rang ? false : (iflib_min_tx_latency | err | (!!txq->ift_reclaim_thresh)); 4043 iflib_txd_db_check(txq, ring); 4044 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 4045 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 4046 if (mcast_sent) 4047 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 4048 #ifdef INVARIANTS 4049 if (iflib_verbose_debug) 4050 printf("consumed=%d\n", consumed); 4051 #endif 4052 return (consumed); 4053 } 4054 4055 static uint32_t 4056 iflib_txq_drain_always(struct ifmp_ring *r) 4057 { 4058 return (1); 4059 } 4060 4061 static uint32_t 4062 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 4063 { 4064 int i, avail; 4065 struct mbuf **mp; 4066 iflib_txq_t txq; 4067 4068 txq = r->cookie; 4069 4070 CALLOUT_LOCK(txq); 4071 callout_stop(&txq->ift_timer); 4072 CALLOUT_UNLOCK(txq); 4073 4074 avail = IDXDIFF(pidx, cidx, r->size); 4075 for (i = 0; i < avail; i++) { 4076 mp = _ring_peek_one(r, cidx, i, avail - i); 4077 if (__predict_false(*mp == (struct mbuf *)txq)) 4078 continue; 4079 m_freem(*mp); 4080 DBG_COUNTER_INC(tx_frees); 4081 } 4082 MPASS(ifmp_ring_is_stalled(r) == 0); 4083 return (avail); 4084 } 4085 4086 static void 4087 iflib_ifmp_purge(iflib_txq_t txq) 4088 { 4089 struct ifmp_ring *r; 4090 4091 r = txq->ift_br; 4092 r->drain = iflib_txq_drain_free; 4093 r->can_drain = iflib_txq_drain_always; 4094 4095 ifmp_ring_check_drainage(r, r->size); 4096 4097 r->drain = iflib_txq_drain; 4098 r->can_drain = iflib_txq_can_drain; 4099 } 4100 4101 static void 4102 _task_fn_tx(void *context) 4103 { 4104 iflib_txq_t txq = context; 4105 if_ctx_t ctx = txq->ift_ctx; 4106 if_t ifp = ctx->ifc_ifp; 4107 int abdicate = ctx->ifc_sysctl_tx_abdicate; 4108 4109 #ifdef IFLIB_DIAGNOSTICS 4110 txq->ift_cpu_exec_count[curcpu]++; 4111 #endif 4112 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4113 return; 4114 #ifdef DEV_NETMAP 4115 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 4116 netmap_tx_irq(ifp, txq->ift_id)) 4117 goto skip_ifmp; 4118 #endif 4119 if (ctx->ifc_sysctl_simple_tx) { 4120 mtx_lock(&txq->ift_mtx); 4121 (void)iflib_completed_tx_reclaim(txq, NULL); 4122 mtx_unlock(&txq->ift_mtx); 4123 goto skip_ifmp; 4124 } 4125 #ifdef ALTQ 4126 if (if_altq_is_enabled(ifp)) 4127 iflib_altq_if_start(ifp); 4128 #endif 4129 if (txq->ift_db_pending) 4130 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 4131 else if (!abdicate) 4132 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4133 /* 4134 * When abdicating, we always need to check drainage, not just when we don't enqueue 4135 */ 4136 if (abdicate) 4137 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4138 4139 skip_ifmp: 4140 if (ctx->ifc_flags & IFC_LEGACY) 4141 IFDI_INTR_ENABLE(ctx); 4142 else 4143 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 4144 } 4145 4146 static void 4147 _task_fn_rx(void *context) 4148 { 4149 iflib_rxq_t rxq = context; 4150 if_ctx_t ctx = rxq->ifr_ctx; 4151 uint8_t more; 4152 uint16_t budget; 4153 #ifdef DEV_NETMAP 4154 u_int work = 0; 4155 int nmirq; 4156 #endif 4157 4158 #ifdef IFLIB_DIAGNOSTICS 4159 rxq->ifr_cpu_exec_count[curcpu]++; 4160 #endif 4161 DBG_COUNTER_INC(task_fn_rxs); 4162 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4163 return; 4164 #ifdef DEV_NETMAP 4165 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 4166 if (nmirq != NM_IRQ_PASS) { 4167 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 4168 goto skip_rxeof; 4169 } 4170 #endif 4171 budget = ctx->ifc_sysctl_rx_budget; 4172 if (budget == 0) 4173 budget = 16; /* XXX */ 4174 more = iflib_rxeof(rxq, budget); 4175 #ifdef DEV_NETMAP 4176 skip_rxeof: 4177 #endif 4178 if ((more & IFLIB_RXEOF_MORE) == 0) { 4179 if (ctx->ifc_flags & IFC_LEGACY) 4180 IFDI_INTR_ENABLE(ctx); 4181 else 4182 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 4183 DBG_COUNTER_INC(rx_intr_enables); 4184 } 4185 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4186 return; 4187 4188 if (more & IFLIB_RXEOF_MORE) 4189 GROUPTASK_ENQUEUE(&rxq->ifr_task); 4190 else if (more & IFLIB_RXEOF_EMPTY) 4191 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 4192 } 4193 4194 static void 4195 _task_fn_admin(void *context, int pending) 4196 { 4197 if_ctx_t ctx = context; 4198 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 4199 iflib_txq_t txq; 4200 int i; 4201 bool oactive, running, do_reset, do_reset_if_up, do_watchdog; 4202 bool in_detach; 4203 4204 STATE_LOCK(ctx); 4205 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 4206 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 4207 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 4208 do_reset_if_up = (ctx->ifc_flags & IFC_DO_RESET_IF_UP); 4209 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 4210 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 4211 ctx->ifc_flags &= ~(IFC_DO_RESET | IFC_DO_RESET_IF_UP | 4212 IFC_DO_WATCHDOG); 4213 STATE_UNLOCK(ctx); 4214 4215 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4216 return; 4217 if (in_detach) 4218 return; 4219 4220 CTX_LOCK(ctx); 4221 if (!do_reset && do_reset_if_up && 4222 (if_getflags(ctx->ifc_ifp) & IFF_UP) != 0) 4223 do_reset = true; 4224 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4225 CALLOUT_LOCK(txq); 4226 callout_stop(&txq->ift_timer); 4227 CALLOUT_UNLOCK(txq); 4228 } 4229 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ) 4230 IFDI_ADMIN_COMPLETION_HANDLE(ctx); 4231 if (do_watchdog) { 4232 ctx->ifc_tx_watchdog_events++; 4233 IFDI_WATCHDOG_RESET(ctx); 4234 } 4235 IFDI_UPDATE_ADMIN_STATUS(ctx); 4236 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4237 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 4238 txq->ift_timer.c_cpu); 4239 } 4240 IFDI_LINK_INTR_ENABLE(ctx); 4241 if (do_reset) 4242 iflib_if_init_locked(ctx); 4243 CTX_UNLOCK(ctx); 4244 4245 if (LINK_ACTIVE(ctx) == 0) 4246 return; 4247 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 4248 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4249 } 4250 4251 static void 4252 _task_fn_iov(void *context, int pending) 4253 { 4254 if_ctx_t ctx = context; 4255 4256 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 4257 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4258 return; 4259 4260 CTX_LOCK(ctx); 4261 IFDI_VFLR_HANDLE(ctx); 4262 CTX_UNLOCK(ctx); 4263 } 4264 4265 static int 4266 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4267 { 4268 int err; 4269 if_int_delay_info_t info; 4270 if_ctx_t ctx; 4271 4272 info = (if_int_delay_info_t)arg1; 4273 ctx = info->iidi_ctx; 4274 info->iidi_req = req; 4275 info->iidi_oidp = oidp; 4276 CTX_LOCK(ctx); 4277 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 4278 CTX_UNLOCK(ctx); 4279 return (err); 4280 } 4281 4282 /********************************************************************* 4283 * 4284 * IFNET FUNCTIONS 4285 * 4286 **********************************************************************/ 4287 4288 static void 4289 iflib_if_init_locked(if_ctx_t ctx) 4290 { 4291 iflib_stop(ctx); 4292 iflib_init_locked(ctx); 4293 } 4294 4295 static void 4296 iflib_if_init(void *arg) 4297 { 4298 if_ctx_t ctx = arg; 4299 4300 CTX_LOCK(ctx); 4301 iflib_if_init_locked(ctx); 4302 CTX_UNLOCK(ctx); 4303 } 4304 4305 static int 4306 iflib_if_transmit(if_t ifp, struct mbuf *m) 4307 { 4308 if_ctx_t ctx = if_getsoftc(ifp); 4309 iflib_txq_t txq; 4310 int err, qidx; 4311 int abdicate; 4312 4313 if (__predict_false((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 4314 DBG_COUNTER_INC(tx_frees); 4315 m_freem(m); 4316 return (ENETDOWN); 4317 } 4318 4319 MPASS(m->m_nextpkt == NULL); 4320 /* ALTQ-enabled interfaces always use queue 0. */ 4321 qidx = 0; 4322 /* Use driver-supplied queue selection method if it exists */ 4323 if (ctx->isc_txq_select_v2) { 4324 struct if_pkt_info pi; 4325 uint64_t early_pullups = 0; 4326 memset(&pi, 0, sizeof(pi)); 4327 4328 err = iflib_parse_header_partial(&pi, &m, &early_pullups); 4329 if (__predict_false(err != 0)) { 4330 /* Assign pullups for bad pkts to default queue */ 4331 ctx->ifc_txqs[0].ift_pullups += early_pullups; 4332 DBG_COUNTER_INC(encap_txd_encap_fail); 4333 return (err); 4334 } 4335 /* Let driver make queueing decision */ 4336 qidx = ctx->isc_txq_select_v2(ctx->ifc_softc, m, &pi); 4337 ctx->ifc_txqs[qidx].ift_pullups += early_pullups; 4338 } 4339 /* Backwards compatibility w/ simpler queue select */ 4340 else if (ctx->isc_txq_select) 4341 qidx = ctx->isc_txq_select(ctx->ifc_softc, m); 4342 /* If not, use iflib's standard method */ 4343 else if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !if_altq_is_enabled(ifp)) 4344 qidx = QIDX(ctx, m); 4345 4346 /* Set TX queue */ 4347 txq = &ctx->ifc_txqs[qidx]; 4348 4349 #ifdef DRIVER_BACKPRESSURE 4350 if (txq->ift_closed) { 4351 while (m != NULL) { 4352 next = m->m_nextpkt; 4353 m->m_nextpkt = NULL; 4354 m_freem(m); 4355 DBG_COUNTER_INC(tx_frees); 4356 m = next; 4357 } 4358 return (ENOBUFS); 4359 } 4360 #endif 4361 #ifdef notyet 4362 qidx = count = 0; 4363 mp = marr; 4364 next = m; 4365 do { 4366 count++; 4367 next = next->m_nextpkt; 4368 } while (next != NULL); 4369 4370 if (count > nitems(marr)) 4371 if ((mp = malloc(count * sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4372 /* XXX check nextpkt */ 4373 m_freem(m); 4374 /* XXX simplify for now */ 4375 DBG_COUNTER_INC(tx_frees); 4376 return (ENOBUFS); 4377 } 4378 for (next = m, i = 0; next != NULL; i++) { 4379 mp[i] = next; 4380 next = next->m_nextpkt; 4381 mp[i]->m_nextpkt = NULL; 4382 } 4383 #endif 4384 DBG_COUNTER_INC(tx_seen); 4385 abdicate = ctx->ifc_sysctl_tx_abdicate; 4386 4387 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4388 4389 if (abdicate) 4390 GROUPTASK_ENQUEUE(&txq->ift_task); 4391 if (err) { 4392 if (!abdicate) 4393 GROUPTASK_ENQUEUE(&txq->ift_task); 4394 /* support forthcoming later */ 4395 #ifdef DRIVER_BACKPRESSURE 4396 txq->ift_closed = TRUE; 4397 #endif 4398 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4399 m_freem(m); 4400 DBG_COUNTER_INC(tx_frees); 4401 if (err == ENOBUFS) 4402 if_inc_counter(ifp, IFCOUNTER_OQDROPS, 1); 4403 else 4404 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 4405 } 4406 4407 return (err); 4408 } 4409 4410 #ifdef ALTQ 4411 /* 4412 * The overall approach to integrating iflib with ALTQ is to continue to use 4413 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4414 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4415 * is redundant/unnecessary, but doing so minimizes the amount of 4416 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4417 * redundantly queueing to an intermediate mp_ring is swamped by the 4418 * performance limitations inherent in using ALTQ. 4419 * 4420 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4421 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4422 * given interface. If ALTQ is enabled for an interface, then all 4423 * transmitted packets for that interface will be submitted to the ALTQ 4424 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4425 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4426 * update stats that the iflib machinery handles, and which is sensitve to 4427 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4428 * will be installed as the start routine for use by ALTQ facilities that 4429 * need to trigger queue drains on a scheduled basis. 4430 * 4431 */ 4432 static void 4433 iflib_altq_if_start(if_t ifp) 4434 { 4435 struct ifaltq *ifq = &ifp->if_snd; /* XXX - DRVAPI */ 4436 struct mbuf *m; 4437 4438 IFQ_LOCK(ifq); 4439 IFQ_DEQUEUE_NOLOCK(ifq, m); 4440 while (m != NULL) { 4441 iflib_if_transmit(ifp, m); 4442 IFQ_DEQUEUE_NOLOCK(ifq, m); 4443 } 4444 IFQ_UNLOCK(ifq); 4445 } 4446 4447 static int 4448 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4449 { 4450 int err; 4451 4452 if (if_altq_is_enabled(ifp)) { 4453 IFQ_ENQUEUE(&ifp->if_snd, m, err); /* XXX - DRVAPI */ 4454 if (err == 0) 4455 iflib_altq_if_start(ifp); 4456 } else 4457 err = iflib_if_transmit(ifp, m); 4458 4459 return (err); 4460 } 4461 #endif /* ALTQ */ 4462 4463 static void 4464 iflib_if_qflush(if_t ifp) 4465 { 4466 if_ctx_t ctx = if_getsoftc(ifp); 4467 iflib_txq_t txq = ctx->ifc_txqs; 4468 int i; 4469 4470 STATE_LOCK(ctx); 4471 ctx->ifc_flags |= IFC_QFLUSH; 4472 STATE_UNLOCK(ctx); 4473 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4474 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4475 iflib_txq_check_drain(txq, 0); 4476 STATE_LOCK(ctx); 4477 ctx->ifc_flags &= ~IFC_QFLUSH; 4478 STATE_UNLOCK(ctx); 4479 4480 /* 4481 * When ALTQ is enabled, this will also take care of purging the 4482 * ALTQ queue(s). 4483 */ 4484 if_qflush(ifp); 4485 } 4486 4487 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4488 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4489 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4490 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG) 4491 4492 static int 4493 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4494 { 4495 if_ctx_t ctx = if_getsoftc(ifp); 4496 struct ifreq *ifr = (struct ifreq *)data; 4497 #if defined(INET) || defined(INET6) 4498 struct ifaddr *ifa = (struct ifaddr *)data; 4499 #endif 4500 bool avoid_reset = false; 4501 int err = 0, reinit = 0, bits; 4502 4503 switch (command) { 4504 case SIOCSIFADDR: 4505 #ifdef INET 4506 if (ifa->ifa_addr->sa_family == AF_INET) 4507 avoid_reset = true; 4508 #endif 4509 #ifdef INET6 4510 if (ifa->ifa_addr->sa_family == AF_INET6) 4511 avoid_reset = true; 4512 #endif 4513 /* 4514 * Calling init results in link renegotiation, 4515 * so we avoid doing it when possible. 4516 */ 4517 if (avoid_reset) { 4518 if_setflagbits(ifp, IFF_UP, 0); 4519 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4520 reinit = 1; 4521 #ifdef INET 4522 if (!(if_getflags(ifp) & IFF_NOARP)) 4523 arp_ifinit(ifp, ifa); 4524 #endif 4525 } else 4526 err = ether_ioctl(ifp, command, data); 4527 break; 4528 case SIOCSIFMTU: 4529 CTX_LOCK(ctx); 4530 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4531 CTX_UNLOCK(ctx); 4532 break; 4533 } 4534 bits = if_getdrvflags(ifp); 4535 /* stop the driver and free any clusters before proceeding */ 4536 iflib_stop(ctx); 4537 4538 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4539 STATE_LOCK(ctx); 4540 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4541 ctx->ifc_flags |= IFC_MULTISEG; 4542 else 4543 ctx->ifc_flags &= ~IFC_MULTISEG; 4544 STATE_UNLOCK(ctx); 4545 err = if_setmtu(ifp, ifr->ifr_mtu); 4546 } 4547 iflib_init_locked(ctx); 4548 STATE_LOCK(ctx); 4549 /* Preserve the stopped state reported by iflib_init_failed(). */ 4550 if ((ctx->ifc_flags & IFC_INIT_FAILED) == 0) 4551 if_setdrvflags(ifp, bits); 4552 STATE_UNLOCK(ctx); 4553 CTX_UNLOCK(ctx); 4554 break; 4555 case SIOCSIFFLAGS: 4556 CTX_LOCK(ctx); 4557 if (if_getflags(ifp) & IFF_UP) { 4558 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4559 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4560 (IFF_PROMISC | IFF_ALLMULTI)) { 4561 CTX_UNLOCK(ctx); 4562 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4563 CTX_LOCK(ctx); 4564 } 4565 } else 4566 reinit = 1; 4567 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4568 iflib_stop(ctx); 4569 } 4570 ctx->ifc_if_flags = if_getflags(ifp); 4571 CTX_UNLOCK(ctx); 4572 break; 4573 case SIOCADDMULTI: 4574 case SIOCDELMULTI: 4575 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4576 CTX_LOCK(ctx); 4577 IFDI_INTR_DISABLE(ctx); 4578 IFDI_MULTI_SET(ctx); 4579 IFDI_INTR_ENABLE(ctx); 4580 CTX_UNLOCK(ctx); 4581 } 4582 break; 4583 case SIOCSIFMEDIA: 4584 CTX_LOCK(ctx); 4585 IFDI_MEDIA_SET(ctx); 4586 CTX_UNLOCK(ctx); 4587 /* FALLTHROUGH */ 4588 case SIOCGIFMEDIA: 4589 case SIOCGIFXMEDIA: 4590 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4591 break; 4592 case SIOCGI2C: 4593 /* FALLTHROUGH */ 4594 case SIOCGI2CPB: 4595 { 4596 struct ifi2creq i2c; 4597 if_shared_ctx_t sctx = ctx->ifc_sctx; 4598 4599 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4600 if (err != 0) 4601 break; 4602 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4603 err = EINVAL; 4604 break; 4605 } 4606 if (i2c.len > sizeof(i2c.data)) { 4607 err = EINVAL; 4608 break; 4609 } 4610 if (command == SIOCGI2C) { 4611 i2c.page = i2c.bank = 0; 4612 } else if ((sctx->isc_flags & IFLIB_I2C_PAGE_BANK) == 0) { 4613 err = EINVAL; 4614 break; 4615 } 4616 4617 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4618 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4619 sizeof(i2c)); 4620 break; 4621 } 4622 case SIOCSIFCAP: 4623 { 4624 int mask, setmask, oldmask; 4625 4626 oldmask = if_getcapenable(ifp); 4627 mask = ifr->ifr_reqcap ^ oldmask; 4628 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG; 4629 setmask = 0; 4630 #ifdef TCP_OFFLOAD 4631 setmask |= mask & (IFCAP_TOE4 | IFCAP_TOE6); 4632 #endif 4633 setmask |= (mask & IFCAP_FLAGS); 4634 setmask |= (mask & IFCAP_WOL); 4635 4636 /* 4637 * If any RX csum has changed, change all the ones that 4638 * are supported by the driver. 4639 */ 4640 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4641 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4642 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4643 } 4644 4645 /* 4646 * want to ensure that traffic has stopped before we change any of the flags 4647 */ 4648 if (setmask) { 4649 CTX_LOCK(ctx); 4650 bits = if_getdrvflags(ifp); 4651 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4652 iflib_stop(ctx); 4653 STATE_LOCK(ctx); 4654 if_togglecapenable(ifp, setmask); 4655 ctx->ifc_softc_ctx.isc_capenable ^= setmask; 4656 STATE_UNLOCK(ctx); 4657 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4658 iflib_init_locked(ctx); 4659 STATE_LOCK(ctx); 4660 if ((ctx->ifc_flags & IFC_INIT_FAILED) == 0) 4661 if_setdrvflags(ifp, bits); 4662 STATE_UNLOCK(ctx); 4663 CTX_UNLOCK(ctx); 4664 } 4665 if_vlancap(ifp); 4666 break; 4667 } 4668 case SIOCGPRIVATE_0: 4669 case SIOCSDRVSPEC: 4670 case SIOCGDRVSPEC: 4671 CTX_LOCK(ctx); 4672 err = IFDI_PRIV_IOCTL(ctx, command, data); 4673 CTX_UNLOCK(ctx); 4674 break; 4675 case SIOCGIFDOWNREASON: 4676 CTX_LOCK(ctx); 4677 err = IFDI_GET_DOWNREASON(ctx, (struct ifdownreason *)data); 4678 CTX_UNLOCK(ctx); 4679 break; 4680 default: 4681 err = ether_ioctl(ifp, command, data); 4682 break; 4683 } 4684 if (reinit) 4685 iflib_if_init(ctx); 4686 return (err); 4687 } 4688 4689 static uint64_t 4690 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4691 { 4692 if_ctx_t ctx = if_getsoftc(ifp); 4693 4694 return (IFDI_GET_COUNTER(ctx, cnt)); 4695 } 4696 4697 /********************************************************************* 4698 * 4699 * OTHER FUNCTIONS EXPORTED TO THE STACK 4700 * 4701 **********************************************************************/ 4702 4703 static void 4704 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4705 { 4706 if_ctx_t ctx = if_getsoftc(ifp); 4707 4708 if ((void *)ctx != arg) 4709 return; 4710 4711 if ((vtag == 0) || (vtag > 4095)) 4712 return; 4713 4714 if (iflib_in_detach(ctx)) 4715 return; 4716 4717 CTX_LOCK(ctx); 4718 /* Driver may need all untagged packets to be flushed */ 4719 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4720 iflib_stop(ctx); 4721 IFDI_VLAN_REGISTER(ctx, vtag); 4722 /* Re-init to load the changes, if required */ 4723 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4724 iflib_init_locked(ctx); 4725 CTX_UNLOCK(ctx); 4726 } 4727 4728 static void 4729 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4730 { 4731 if_ctx_t ctx = if_getsoftc(ifp); 4732 4733 if ((void *)ctx != arg) 4734 return; 4735 4736 if ((vtag == 0) || (vtag > 4095)) 4737 return; 4738 4739 CTX_LOCK(ctx); 4740 /* Driver may need all tagged packets to be flushed */ 4741 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4742 iflib_stop(ctx); 4743 IFDI_VLAN_UNREGISTER(ctx, vtag); 4744 /* Re-init to load the changes, if required */ 4745 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4746 iflib_init_locked(ctx); 4747 CTX_UNLOCK(ctx); 4748 } 4749 4750 static void 4751 _task_fn_led(void *context, int pending __unused) 4752 { 4753 if_ctx_t ctx = context; 4754 bool in_detach; 4755 int onoff; 4756 4757 STATE_LOCK(ctx); 4758 in_detach = (ctx->ifc_flags & IFC_IN_DETACH) != 0; 4759 onoff = ctx->ifc_led_state; 4760 STATE_UNLOCK(ctx); 4761 if (in_detach) 4762 return; 4763 4764 CTX_LOCK(ctx); 4765 IFDI_LED_FUNC(ctx, onoff); 4766 CTX_UNLOCK(ctx); 4767 } 4768 4769 static void 4770 iflib_led_func(void *arg, int onoff) 4771 { 4772 if_ctx_t ctx = arg; 4773 bool in_detach; 4774 4775 /* led(4) may invoke this callback from a non-sleepable callout. */ 4776 STATE_LOCK(ctx); 4777 ctx->ifc_led_state = onoff; 4778 in_detach = (ctx->ifc_flags & IFC_IN_DETACH) != 0; 4779 STATE_UNLOCK(ctx); 4780 if (!in_detach) 4781 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_led_task); 4782 } 4783 4784 /********************************************************************* 4785 * 4786 * BUS FUNCTION DEFINITIONS 4787 * 4788 **********************************************************************/ 4789 4790 int 4791 iflib_device_probe(device_t dev) 4792 { 4793 const pci_vendor_info_t *ent; 4794 if_shared_ctx_t sctx; 4795 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4796 uint16_t pci_vendor_id; 4797 4798 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4799 return (ENOTSUP); 4800 4801 pci_vendor_id = pci_get_vendor(dev); 4802 pci_device_id = pci_get_device(dev); 4803 pci_subvendor_id = pci_get_subvendor(dev); 4804 pci_subdevice_id = pci_get_subdevice(dev); 4805 pci_rev_id = pci_get_revid(dev); 4806 if (sctx->isc_parse_devinfo != NULL) 4807 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4808 4809 ent = sctx->isc_vendor_info; 4810 while (ent->pvi_vendor_id != 0) { 4811 if (pci_vendor_id != ent->pvi_vendor_id) { 4812 ent++; 4813 continue; 4814 } 4815 if ((pci_device_id == ent->pvi_device_id) && 4816 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4817 (ent->pvi_subvendor_id == 0)) && 4818 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4819 (ent->pvi_subdevice_id == 0)) && 4820 ((pci_rev_id == ent->pvi_rev_id) || 4821 (ent->pvi_rev_id == 0))) { 4822 device_set_desc_copy(dev, ent->pvi_name); 4823 /* this needs to be changed to zero if the bus probing code 4824 * ever stops re-probing on best match because the sctx 4825 * may have its values over written by register calls 4826 * in subsequent probes 4827 */ 4828 return (BUS_PROBE_DEFAULT); 4829 } 4830 ent++; 4831 } 4832 return (ENXIO); 4833 } 4834 4835 int 4836 iflib_device_probe_vendor(device_t dev) 4837 { 4838 int probe; 4839 4840 probe = iflib_device_probe(dev); 4841 if (probe == BUS_PROBE_DEFAULT) 4842 return (BUS_PROBE_VENDOR); 4843 else 4844 return (probe); 4845 } 4846 4847 static void 4848 iflib_reset_qvalues(if_ctx_t ctx) 4849 { 4850 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4851 if_shared_ctx_t sctx = ctx->ifc_sctx; 4852 device_t dev = ctx->ifc_dev; 4853 int i; 4854 4855 if (ctx->ifc_sysctl_ntxqs != 0) 4856 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4857 if (ctx->ifc_sysctl_nrxqs != 0) 4858 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4859 4860 for (i = 0; i < sctx->isc_ntxqs; i++) { 4861 if (ctx->ifc_sysctl_ntxds[i] != 0) 4862 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4863 else 4864 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4865 } 4866 4867 for (i = 0; i < sctx->isc_nrxqs; i++) { 4868 if (ctx->ifc_sysctl_nrxds[i] != 0) 4869 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4870 else 4871 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4872 } 4873 4874 for (i = 0; i < sctx->isc_nrxqs; i++) { 4875 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4876 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4877 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4878 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4879 } 4880 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4881 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4882 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4883 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4884 } 4885 if (!powerof2(scctx->isc_nrxd[i])) { 4886 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4887 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4888 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4889 } 4890 } 4891 4892 for (i = 0; i < sctx->isc_ntxqs; i++) { 4893 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4894 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4895 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4896 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4897 } 4898 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4899 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4900 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4901 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4902 } 4903 if (!powerof2(scctx->isc_ntxd[i])) { 4904 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4905 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4906 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4907 } 4908 } 4909 scctx->isc_tx_pad = 2; 4910 } 4911 4912 static void 4913 iflib_add_pfil(if_ctx_t ctx) 4914 { 4915 struct pfil_head *pfil; 4916 struct pfil_head_args pa; 4917 iflib_rxq_t rxq; 4918 int i; 4919 4920 pa.pa_version = PFIL_VERSION; 4921 pa.pa_flags = PFIL_IN; 4922 pa.pa_type = PFIL_TYPE_ETHERNET; 4923 pa.pa_headname = if_name(ctx->ifc_ifp); 4924 pfil = pfil_head_register(&pa); 4925 4926 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4927 rxq->pfil = pfil; 4928 } 4929 } 4930 4931 static void 4932 iflib_rem_pfil(if_ctx_t ctx) 4933 { 4934 struct pfil_head *pfil; 4935 iflib_rxq_t rxq; 4936 int i; 4937 4938 rxq = ctx->ifc_rxqs; 4939 pfil = rxq->pfil; 4940 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4941 rxq->pfil = NULL; 4942 } 4943 pfil_head_unregister(pfil); 4944 } 4945 4946 4947 /* 4948 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from 4949 * cpuid and wrapping as necessary. 4950 */ 4951 static unsigned int 4952 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n) 4953 { 4954 unsigned int first_valid; 4955 unsigned int last_valid; 4956 4957 /* cpuid should always be in the valid set */ 4958 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4959 4960 /* valid set should never be empty */ 4961 MPASS(!CPU_EMPTY(&ctx->ifc_cpus)); 4962 4963 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4964 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4965 n = n % CPU_COUNT(&ctx->ifc_cpus); 4966 while (n > 0) { 4967 do { 4968 cpuid++; 4969 if (cpuid > last_valid) 4970 cpuid = first_valid; 4971 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4972 n--; 4973 } 4974 4975 return (cpuid); 4976 } 4977 4978 /* 4979 * CPU mapping behaviors 4980 * --------------------- 4981 * 'separate txrx' refers to the separate_txrx sysctl 4982 * 'use logical' refers to the use_logical_cores sysctl 4983 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded 4984 * 4985 * separate use INTR 4986 * txrx logical CPUS result 4987 * ---------- --------- ------ ------------------------------------------------ 4988 * - - X RX and TX queues mapped to consecutive physical 4989 * cores with RX/TX pairs on same core and excess 4990 * of either following 4991 * - X X RX and TX queues mapped to consecutive cores 4992 * of any type with RX/TX pairs on same core and 4993 * excess of either following 4994 * X - X RX and TX queues mapped to consecutive physical 4995 * cores; all RX then all TX 4996 * X X X RX queues mapped to consecutive physical cores 4997 * first, then TX queues mapped to L2 neighbor of 4998 * the corresponding RX queue if one exists, 4999 * otherwise to consecutive physical cores 5000 * - n/a - RX and TX queues mapped to consecutive cores of 5001 * any type with RX/TX pairs on same core and excess 5002 * of either following 5003 * X n/a - RX and TX queues mapped to consecutive cores of 5004 * any type; all RX then all TX 5005 */ 5006 static unsigned int 5007 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid, 5008 bool is_tx) 5009 { 5010 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5011 unsigned int core_index; 5012 5013 if (ctx->ifc_sysctl_separate_txrx) { 5014 /* 5015 * When using separate CPUs for TX and RX, the assignment 5016 * will always be of a consecutive CPU out of the set of 5017 * context CPUs, except for the specific case where the 5018 * context CPUs are phsyical cores, the use of logical cores 5019 * has been enabled, the assignment is for TX, the TX qid 5020 * corresponds to an RX qid, and the CPU assigned to the 5021 * corresponding RX queue has an L2 neighbor. 5022 */ 5023 if (ctx->ifc_sysctl_use_logical_cores && 5024 ctx->ifc_cpus_are_physical_cores && 5025 is_tx && qid < scctx->isc_nrxqsets) { 5026 int l2_neighbor; 5027 unsigned int rx_cpuid; 5028 5029 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid); 5030 l2_neighbor = sched_find_l2_neighbor(rx_cpuid); 5031 if (l2_neighbor != -1) { 5032 return (l2_neighbor); 5033 } 5034 /* 5035 * ... else fall through to the normal 5036 * consecutive-after-RX assignment scheme. 5037 * 5038 * Note that we are assuming that all RX queue CPUs 5039 * have an L2 neighbor, or all do not. If a mixed 5040 * scenario is possible, we will have to keep track 5041 * separately of how many queues prior to this one 5042 * were not able to be assigned to an L2 neighbor. 5043 */ 5044 } 5045 if (is_tx) 5046 core_index = scctx->isc_nrxqsets + qid; 5047 else 5048 core_index = qid; 5049 } else { 5050 core_index = qid; 5051 } 5052 5053 return (cpuid_advance(ctx, base_cpuid, core_index)); 5054 } 5055 5056 static uint16_t 5057 get_ctx_core_offset(if_ctx_t ctx) 5058 { 5059 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5060 struct cpu_offset *op; 5061 cpuset_t assigned_cpus; 5062 unsigned int cores_consumed; 5063 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset; 5064 unsigned int first_valid; 5065 unsigned int last_valid; 5066 unsigned int i; 5067 5068 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 5069 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 5070 5071 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) { 5072 /* 5073 * Align the user-chosen base CPU ID to the next valid CPU 5074 * for this device. If the chosen base CPU ID is smaller 5075 * than the first valid CPU or larger than the last valid 5076 * CPU, we assume the user does not know what the valid 5077 * range is for this device and is thinking in terms of a 5078 * zero-based reference frame, and so we shift the given 5079 * value into the valid range (and wrap accordingly) so the 5080 * intent is translated to the proper frame of reference. 5081 * If the base CPU ID is within the valid first/last, but 5082 * does not correspond to a valid CPU, it is advanced to the 5083 * next valid CPU (wrapping if necessary). 5084 */ 5085 if (base_cpuid < first_valid || base_cpuid > last_valid) { 5086 /* shift from zero-based to first_valid-based */ 5087 base_cpuid += first_valid; 5088 /* wrap to range [first_valid, last_valid] */ 5089 base_cpuid = (base_cpuid - first_valid) % 5090 (last_valid - first_valid + 1); 5091 } 5092 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) { 5093 /* 5094 * base_cpuid is in [first_valid, last_valid], but 5095 * not a member of the valid set. In this case, 5096 * there will always be a member of the valid set 5097 * with a CPU ID that is greater than base_cpuid, 5098 * and we simply advance to it. 5099 */ 5100 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) 5101 base_cpuid++; 5102 } 5103 return (base_cpuid); 5104 } 5105 5106 /* 5107 * Determine how many cores will be consumed by performing the CPU 5108 * assignments and counting how many of the assigned CPUs correspond 5109 * to CPUs in the set of context CPUs. This is done using the CPU 5110 * ID first_valid as the base CPU ID, as the base CPU must be within 5111 * the set of context CPUs. 5112 * 5113 * Note not all assigned CPUs will be in the set of context CPUs 5114 * when separate CPUs are being allocated to TX and RX queues, 5115 * assignment to logical cores has been enabled, the set of context 5116 * CPUs contains only physical CPUs, and TX queues are mapped to L2 5117 * neighbors of CPUs that RX queues have been mapped to - in this 5118 * case we do only want to count how many CPUs in the set of context 5119 * CPUs have been consumed, as that determines the next CPU in that 5120 * set to start allocating at for the next device for which 5121 * core_offset is not set. 5122 */ 5123 CPU_ZERO(&assigned_cpus); 5124 for (i = 0; i < scctx->isc_ntxqsets; i++) 5125 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true), 5126 &assigned_cpus); 5127 for (i = 0; i < scctx->isc_nrxqsets; i++) 5128 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false), 5129 &assigned_cpus); 5130 CPU_AND(&assigned_cpus, &assigned_cpus, &ctx->ifc_cpus); 5131 cores_consumed = CPU_COUNT(&assigned_cpus); 5132 5133 mtx_lock(&cpu_offset_mtx); 5134 SLIST_FOREACH(op, &cpu_offsets, entries) { 5135 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5136 base_cpuid = op->next_cpuid; 5137 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid, 5138 cores_consumed); 5139 MPASS(op->refcount < UINT_MAX); 5140 op->refcount++; 5141 break; 5142 } 5143 } 5144 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) { 5145 base_cpuid = first_valid; 5146 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 5147 M_NOWAIT | M_ZERO); 5148 if (op == NULL) { 5149 device_printf(ctx->ifc_dev, 5150 "allocation for cpu offset failed.\n"); 5151 } else { 5152 op->next_cpuid = cpuid_advance(ctx, base_cpuid, 5153 cores_consumed); 5154 op->refcount = 1; 5155 CPU_COPY(&ctx->ifc_cpus, &op->set); 5156 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 5157 } 5158 } 5159 mtx_unlock(&cpu_offset_mtx); 5160 5161 return (base_cpuid); 5162 } 5163 5164 static void 5165 unref_ctx_core_offset(if_ctx_t ctx) 5166 { 5167 struct cpu_offset *op, *top; 5168 5169 mtx_lock(&cpu_offset_mtx); 5170 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 5171 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5172 MPASS(op->refcount > 0); 5173 op->refcount--; 5174 if (op->refcount == 0) { 5175 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 5176 free(op, M_IFLIB); 5177 } 5178 break; 5179 } 5180 } 5181 mtx_unlock(&cpu_offset_mtx); 5182 } 5183 5184 int 5185 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 5186 { 5187 if_ctx_t ctx; 5188 if_t ifp; 5189 if_softc_ctx_t scctx; 5190 kobjop_desc_t kobj_desc; 5191 kobj_method_t *kobj_method; 5192 int err, msix, rid; 5193 int num_txd, num_rxd; 5194 char namebuf[TASKQUEUE_NAMELEN]; 5195 5196 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK | M_ZERO); 5197 5198 if (sc == NULL) { 5199 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK | M_ZERO); 5200 device_set_softc(dev, ctx); 5201 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5202 } 5203 5204 ctx->ifc_sctx = sctx; 5205 ctx->ifc_dev = dev; 5206 ctx->ifc_softc = sc; 5207 5208 iflib_register(ctx); 5209 iflib_add_device_sysctl_pre(ctx); 5210 5211 scctx = &ctx->ifc_softc_ctx; 5212 ifp = ctx->ifc_ifp; 5213 if (ctx->ifc_sysctl_simple_tx) { 5214 #ifndef ALTQ 5215 if_settransmitfn(ifp, iflib_simple_transmit); 5216 device_printf(dev, "using simple if_transmit\n"); 5217 #else 5218 device_printf(dev, "ALTQ prevents using simple if_transmit\n"); 5219 #endif 5220 } 5221 iflib_reset_qvalues(ctx); 5222 IFNET_WLOCK(); 5223 CTX_LOCK(ctx); 5224 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5225 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5226 goto fail_unlock; 5227 } 5228 _iflib_pre_assert(scctx); 5229 ctx->ifc_txrx = *scctx->isc_txrx; 5230 5231 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR)); 5232 5233 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 5234 ctx->ifc_mediap = scctx->isc_media; 5235 5236 #ifdef INVARIANTS 5237 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5238 MPASS(scctx->isc_tx_csum_flags); 5239 #endif 5240 5241 if_setcapabilities(ifp, 5242 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG); 5243 if_setcapenable(ifp, 5244 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG); 5245 5246 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5247 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5248 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5249 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5250 5251 num_txd = iflib_num_tx_descs(ctx); 5252 num_rxd = iflib_num_rx_descs(ctx); 5253 5254 /* XXX change for per-queue sizes */ 5255 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5256 num_txd, num_rxd); 5257 5258 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5259 scctx->isc_tx_nsegments = max(1, num_txd / 5260 MAX_SINGLE_PACKET_FRACTION); 5261 if (scctx->isc_tx_tso_segments_max > num_txd / 5262 MAX_SINGLE_PACKET_FRACTION) 5263 scctx->isc_tx_tso_segments_max = max(1, 5264 num_txd / MAX_SINGLE_PACKET_FRACTION); 5265 5266 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5267 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5268 /* 5269 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5270 * but some MACs do. 5271 */ 5272 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5273 IP_MAXPACKET)); 5274 /* 5275 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5276 * into account. In the worst case, each of these calls will 5277 * add another mbuf and, thus, the requirement for another DMA 5278 * segment. So for best performance, it doesn't make sense to 5279 * advertize a maximum of TSO segments that typically will 5280 * require defragmentation in iflib_encap(). 5281 */ 5282 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5283 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5284 } 5285 if (scctx->isc_rss_table_size == 0) 5286 scctx->isc_rss_table_size = 64; 5287 scctx->isc_rss_table_mask = scctx->isc_rss_table_size - 1; 5288 5289 /* Create and start admin taskqueue */ 5290 snprintf(namebuf, TASKQUEUE_NAMELEN, "if_%s_tq", device_get_nameunit(dev)); 5291 ctx->ifc_tq = taskqueue_create_fast(namebuf, M_NOWAIT, 5292 taskqueue_thread_enqueue, &ctx->ifc_tq); 5293 if (ctx->ifc_tq == NULL) { 5294 device_printf(dev, "Unable to create admin taskqueue\n"); 5295 return (ENOMEM); 5296 } 5297 5298 err = taskqueue_start_threads(&ctx->ifc_tq, 1, PI_NET, "%s", namebuf); 5299 if (err) { 5300 device_printf(dev, 5301 "Unable to start admin taskqueue threads error: %d\n", 5302 err); 5303 taskqueue_free(ctx->ifc_tq); 5304 return (err); 5305 } 5306 5307 TASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5308 TASK_INIT(&ctx->ifc_led_task, 0, _task_fn_led, ctx); 5309 5310 /* Set up cpu set. If it fails, use the set of all CPUs. */ 5311 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 5312 device_printf(dev, "Unable to fetch CPU list\n"); 5313 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 5314 ctx->ifc_cpus_are_physical_cores = false; 5315 } else 5316 ctx->ifc_cpus_are_physical_cores = true; 5317 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 5318 5319 /* 5320 * Now set up MSI or MSI-X, should return us the number of supported 5321 * vectors (will be 1 for a legacy interrupt and MSI). 5322 */ 5323 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 5324 msix = scctx->isc_vectors; 5325 } else if (scctx->isc_msix_bar != 0) 5326 /* 5327 * The simple fact that isc_msix_bar is not 0 does not mean we 5328 * we have a good value there that is known to work. 5329 */ 5330 msix = iflib_msix_init(ctx); 5331 else { 5332 scctx->isc_vectors = 1; 5333 scctx->isc_ntxqsets = 1; 5334 scctx->isc_nrxqsets = 1; 5335 scctx->isc_intr = IFLIB_INTR_LEGACY; 5336 msix = 0; 5337 } 5338 /* Get memory for the station queues */ 5339 if ((err = iflib_queues_alloc(ctx))) { 5340 device_printf(dev, "Unable to allocate queue memory\n"); 5341 goto fail_intr_free; 5342 } 5343 5344 if ((err = iflib_qset_structures_setup(ctx))) 5345 goto fail_queues; 5346 5347 /* 5348 * Now that we know how many queues there are, get the core offset. 5349 */ 5350 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 5351 5352 if (msix > 1) { 5353 /* 5354 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 5355 * aren't the default NULL implementation. 5356 */ 5357 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 5358 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5359 kobj_desc); 5360 if (kobj_method == &kobj_desc->deflt) { 5361 device_printf(dev, 5362 "MSI-X requires ifdi_rx_queue_intr_enable method"); 5363 err = EOPNOTSUPP; 5364 goto fail_queues; 5365 } 5366 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 5367 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5368 kobj_desc); 5369 if (kobj_method == &kobj_desc->deflt) { 5370 device_printf(dev, 5371 "MSI-X requires ifdi_tx_queue_intr_enable method"); 5372 err = EOPNOTSUPP; 5373 goto fail_queues; 5374 } 5375 5376 /* 5377 * Assign the MSI-X vectors. 5378 * Note that the default NULL ifdi_msix_intr_assign method will 5379 * fail here, too. 5380 */ 5381 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 5382 if (err != 0) { 5383 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 5384 err); 5385 goto fail_queues; 5386 } 5387 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 5388 rid = 0; 5389 if (scctx->isc_intr == IFLIB_INTR_MSI) { 5390 MPASS(msix == 1); 5391 rid = 1; 5392 } 5393 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 5394 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 5395 goto fail_queues; 5396 } 5397 } else { 5398 device_printf(dev, 5399 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 5400 err = ENODEV; 5401 goto fail_queues; 5402 } 5403 5404 /* 5405 * It prevents a double-locking panic with iflib_media_status when 5406 * the driver loads. 5407 */ 5408 CTX_UNLOCK(ctx); 5409 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5410 CTX_LOCK(ctx); 5411 5412 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5413 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5414 goto fail_detach; 5415 } 5416 5417 /* 5418 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5419 * This must appear after the call to ether_ifattach() because 5420 * ether_ifattach() sets if_hdrlen to the default value. 5421 */ 5422 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5423 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5424 5425 if ((err = iflib_netmap_attach(ctx))) { 5426 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 5427 goto fail_detach; 5428 } 5429 *ctxp = ctx; 5430 5431 DEBUGNET_SET(ctx->ifc_ifp, iflib); 5432 5433 iflib_add_device_sysctl_post(ctx); 5434 iflib_add_pfil(ctx); 5435 ctx->ifc_flags |= IFC_INIT_DONE; 5436 CTX_UNLOCK(ctx); 5437 IFNET_WUNLOCK(); 5438 5439 /* Create led(4) devices if the driver defined the method */ 5440 kobj_desc = &ifdi_led_func_desc; 5441 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5442 kobj_desc); 5443 if (kobj_method != &kobj_desc->deflt && IFDI_LED_SUPPORTED(ctx)) 5444 iflib_led_create(ctx); 5445 5446 return (0); 5447 5448 fail_detach: 5449 CTX_UNLOCK(ctx); 5450 taskqueue_drain(ctx->ifc_tq, &ctx->ifc_admin_task); 5451 ether_ifdetach(ctx->ifc_ifp); 5452 CTX_LOCK(ctx); 5453 fail_queues: 5454 sysctl_ctx_free(&ctx->ifc_sysctl_ctx); 5455 ctx->ifc_sysctl_node = NULL; 5456 /* 5457 * Drain without holding CTX_LOCK so _task_fn_admin can run to 5458 * completion if it needs the context lock. On fail_detach we already 5459 * drained above; a second drain is a no-op when the queue is empty. 5460 */ 5461 CTX_UNLOCK(ctx); 5462 taskqueue_drain(ctx->ifc_tq, &ctx->ifc_admin_task); 5463 CTX_LOCK(ctx); 5464 iflib_tqg_detach(ctx); 5465 iflib_tx_structures_free(ctx); 5466 iflib_rx_structures_free(ctx); 5467 /* 5468 * Match iflib_device_deregister: IFDI_DETACH before taskqueue_free. 5469 * Avoid IFNET_WLOCK across driver detach (LinuxKPI workqueue drain). 5470 */ 5471 IFNET_WUNLOCK(); 5472 IFDI_DETACH(ctx); 5473 IFDI_QUEUES_FREE(ctx); 5474 IFNET_WLOCK(); 5475 taskqueue_free(ctx->ifc_tq); 5476 fail_intr_free: 5477 iflib_free_intr_mem(ctx); 5478 fail_unlock: 5479 CTX_UNLOCK(ctx); 5480 IFNET_WUNLOCK(); 5481 iflib_deregister(ctx); 5482 device_set_softc(ctx->ifc_dev, NULL); 5483 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5484 free(ctx->ifc_softc, M_IFLIB); 5485 free(ctx, M_IFLIB); 5486 return (err); 5487 } 5488 5489 int 5490 iflib_device_attach(device_t dev) 5491 { 5492 if_ctx_t ctx; 5493 if_shared_ctx_t sctx; 5494 5495 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5496 return (ENOTSUP); 5497 5498 pci_enable_busmaster(dev); 5499 5500 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5501 } 5502 5503 int 5504 iflib_device_deregister(if_ctx_t ctx) 5505 { 5506 if_t ifp = ctx->ifc_ifp; 5507 device_t dev = ctx->ifc_dev; 5508 5509 sysctl_ctx_free(&ctx->ifc_sysctl_ctx); 5510 ctx->ifc_sysctl_node = NULL; 5511 5512 /* Make sure VLANS are not using driver */ 5513 if (if_vlantrunkinuse(ifp)) { 5514 device_printf(dev, "Vlan in use, detach first\n"); 5515 return (EBUSY); 5516 } 5517 #ifdef PCI_IOV 5518 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5519 device_printf(dev, "SR-IOV in use; detach first.\n"); 5520 return (EBUSY); 5521 } 5522 #endif 5523 5524 STATE_LOCK(ctx); 5525 ctx->ifc_flags |= IFC_IN_DETACH; 5526 STATE_UNLOCK(ctx); 5527 5528 /* Unregister VLAN handlers before calling iflib_stop() */ 5529 iflib_unregister_vlan_handlers(ctx); 5530 5531 iflib_netmap_detach(ifp); 5532 ether_ifdetach(ifp); 5533 5534 CTX_LOCK(ctx); 5535 iflib_stop(ctx); 5536 CTX_UNLOCK(ctx); 5537 5538 iflib_rem_pfil(ctx); 5539 if (ctx->ifc_led_dev != NULL) { 5540 led_destroy(ctx->ifc_led_dev); 5541 taskqueue_drain(ctx->ifc_tq, &ctx->ifc_led_task); 5542 } 5543 5544 iflib_tqg_detach(ctx); 5545 iflib_tx_structures_free(ctx); 5546 iflib_rx_structures_free(ctx); 5547 5548 CTX_LOCK(ctx); 5549 IFDI_DETACH(ctx); 5550 IFDI_QUEUES_FREE(ctx); 5551 CTX_UNLOCK(ctx); 5552 5553 taskqueue_free(ctx->ifc_tq); 5554 ctx->ifc_tq = NULL; 5555 5556 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5557 iflib_free_intr_mem(ctx); 5558 5559 bus_generic_detach(dev); 5560 5561 iflib_deregister(ctx); 5562 5563 device_set_softc(ctx->ifc_dev, NULL); 5564 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5565 free(ctx->ifc_softc, M_IFLIB); 5566 unref_ctx_core_offset(ctx); 5567 free(ctx, M_IFLIB); 5568 return (0); 5569 } 5570 5571 static void 5572 iflib_tqg_detach(if_ctx_t ctx) 5573 { 5574 iflib_txq_t txq; 5575 iflib_rxq_t rxq; 5576 int i; 5577 struct taskqgroup *tqg; 5578 5579 /* XXX drain any dependent tasks */ 5580 tqg = qgroup_if_io_tqg; 5581 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5582 callout_drain(&txq->ift_timer); 5583 #ifdef DEV_NETMAP 5584 callout_drain(&txq->ift_netmap_timer); 5585 #endif /* DEV_NETMAP */ 5586 if (txq->ift_task.gt_uniq != NULL) 5587 taskqgroup_detach(tqg, &txq->ift_task); 5588 } 5589 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5590 if (rxq->ifr_task.gt_uniq != NULL) 5591 taskqgroup_detach(tqg, &rxq->ifr_task); 5592 } 5593 } 5594 5595 static void 5596 iflib_free_intr_mem(if_ctx_t ctx) 5597 { 5598 5599 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5600 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5601 } 5602 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5603 pci_release_msi(ctx->ifc_dev); 5604 } 5605 if (ctx->ifc_msix_mem != NULL) { 5606 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5607 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5608 ctx->ifc_msix_mem = NULL; 5609 } 5610 } 5611 5612 int 5613 iflib_device_detach(device_t dev) 5614 { 5615 if_ctx_t ctx = device_get_softc(dev); 5616 5617 return (iflib_device_deregister(ctx)); 5618 } 5619 5620 int 5621 iflib_device_suspend(device_t dev) 5622 { 5623 if_ctx_t ctx = device_get_softc(dev); 5624 5625 CTX_LOCK(ctx); 5626 IFDI_SUSPEND(ctx); 5627 CTX_UNLOCK(ctx); 5628 5629 return (bus_generic_suspend(dev)); 5630 } 5631 int 5632 iflib_device_shutdown(device_t dev) 5633 { 5634 if_ctx_t ctx = device_get_softc(dev); 5635 5636 CTX_LOCK(ctx); 5637 IFDI_SHUTDOWN(ctx); 5638 CTX_UNLOCK(ctx); 5639 5640 return (bus_generic_suspend(dev)); 5641 } 5642 5643 int 5644 iflib_device_resume(device_t dev) 5645 { 5646 if_ctx_t ctx = device_get_softc(dev); 5647 iflib_txq_t txq = ctx->ifc_txqs; 5648 5649 CTX_LOCK(ctx); 5650 IFDI_RESUME(ctx); 5651 iflib_if_init_locked(ctx); 5652 CTX_UNLOCK(ctx); 5653 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5654 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5655 5656 return (bus_generic_resume(dev)); 5657 } 5658 5659 int 5660 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5661 { 5662 int error; 5663 if_ctx_t ctx = device_get_softc(dev); 5664 5665 CTX_LOCK(ctx); 5666 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5667 CTX_UNLOCK(ctx); 5668 5669 return (error); 5670 } 5671 5672 int 5673 iflib_device_iov_init_restart(device_t dev, uint16_t num_vfs, 5674 const nvlist_t *params) 5675 { 5676 if_ctx_t ctx; 5677 if_t ifp; 5678 bool restart, running; 5679 int error; 5680 5681 ctx = device_get_softc(dev); 5682 ifp = ctx->ifc_ifp; 5683 5684 CTX_LOCK(ctx); 5685 /* 5686 * Drivers which change the PF queue layout need the complete iflib 5687 * stop/init sequence around their IOV callback when the interface is 5688 * active. An administratively-down interface has no live queues to 5689 * quiesce, and must remain down after the new layout is installed. 5690 * Keep the transition within one context-lock critical section. 5691 */ 5692 restart = (if_getflags(ifp) & IFF_UP) != 0; 5693 running = (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0; 5694 if (restart || running) 5695 iflib_stop(ctx); 5696 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5697 if (restart) 5698 iflib_init_locked(ctx); 5699 CTX_UNLOCK(ctx); 5700 return (error); 5701 } 5702 5703 void 5704 iflib_device_iov_uninit(device_t dev) 5705 { 5706 if_ctx_t ctx = device_get_softc(dev); 5707 5708 CTX_LOCK(ctx); 5709 IFDI_IOV_UNINIT(ctx); 5710 CTX_UNLOCK(ctx); 5711 } 5712 5713 void 5714 iflib_device_iov_uninit_restart(device_t dev) 5715 { 5716 if_ctx_t ctx; 5717 bool restart; 5718 5719 ctx = device_get_softc(dev); 5720 5721 CTX_LOCK(ctx); 5722 /* 5723 * RUNNING can be clear while a watchdog reset is pending but the 5724 * hardware is still live. Always stop before the driver changes its 5725 * queue layout, and use IFF_UP only to preserve administrative state. 5726 */ 5727 restart = (if_getflags(ctx->ifc_ifp) & IFF_UP) != 0; 5728 iflib_stop(ctx); 5729 IFDI_IOV_UNINIT(ctx); 5730 if (restart) 5731 iflib_init_locked(ctx); 5732 CTX_UNLOCK(ctx); 5733 } 5734 5735 int 5736 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5737 { 5738 int error; 5739 if_ctx_t ctx = device_get_softc(dev); 5740 5741 CTX_LOCK(ctx); 5742 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5743 CTX_UNLOCK(ctx); 5744 5745 return (error); 5746 } 5747 5748 /********************************************************************* 5749 * 5750 * MODULE FUNCTION DEFINITIONS 5751 * 5752 **********************************************************************/ 5753 5754 /* 5755 * - Start a fast taskqueue thread for each core 5756 * - Start a taskqueue for control operations 5757 */ 5758 static int 5759 iflib_module_init(void) 5760 { 5761 iflib_timer_default = hz / 2; 5762 return (0); 5763 } 5764 5765 static int 5766 iflib_module_event_handler(module_t mod, int what, void *arg) 5767 { 5768 int err; 5769 5770 switch (what) { 5771 case MOD_LOAD: 5772 if ((err = iflib_module_init()) != 0) 5773 return (err); 5774 break; 5775 case MOD_UNLOAD: 5776 return (EBUSY); 5777 default: 5778 return (EOPNOTSUPP); 5779 } 5780 5781 return (0); 5782 } 5783 5784 /********************************************************************* 5785 * 5786 * PUBLIC FUNCTION DEFINITIONS 5787 * ordered as in iflib.h 5788 * 5789 **********************************************************************/ 5790 5791 static void 5792 _iflib_assert(if_shared_ctx_t sctx) 5793 { 5794 int i; 5795 5796 MPASS(sctx->isc_tx_maxsize); 5797 MPASS(sctx->isc_tx_maxsegsize); 5798 5799 MPASS(sctx->isc_rx_maxsize); 5800 MPASS(sctx->isc_rx_nsegments); 5801 MPASS(sctx->isc_rx_maxsegsize); 5802 5803 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5804 for (i = 0; i < sctx->isc_nrxqs; i++) { 5805 MPASS(sctx->isc_nrxd_min[i]); 5806 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5807 MPASS(sctx->isc_nrxd_max[i]); 5808 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5809 MPASS(sctx->isc_nrxd_default[i]); 5810 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5811 } 5812 5813 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5814 for (i = 0; i < sctx->isc_ntxqs; i++) { 5815 MPASS(sctx->isc_ntxd_min[i]); 5816 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5817 MPASS(sctx->isc_ntxd_max[i]); 5818 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5819 MPASS(sctx->isc_ntxd_default[i]); 5820 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5821 } 5822 } 5823 5824 static void 5825 _iflib_pre_assert(if_softc_ctx_t scctx) 5826 { 5827 5828 MPASS(scctx->isc_txrx->ift_txd_encap); 5829 MPASS(scctx->isc_txrx->ift_txd_flush); 5830 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5831 MPASS(scctx->isc_txrx->ift_rxd_available); 5832 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5833 MPASS(scctx->isc_txrx->ift_rxd_refill); 5834 MPASS(scctx->isc_txrx->ift_rxd_flush); 5835 } 5836 5837 static void 5838 iflib_register(if_ctx_t ctx) 5839 { 5840 if_shared_ctx_t sctx = ctx->ifc_sctx; 5841 driver_t *driver = sctx->isc_driver; 5842 device_t dev = ctx->ifc_dev; 5843 if_t ifp; 5844 5845 _iflib_assert(sctx); 5846 5847 CTX_LOCK_INIT(ctx); 5848 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5849 ifp = ctx->ifc_ifp = if_alloc_dev(IFT_ETHER, dev); 5850 5851 /* 5852 * Initialize our context's device specific methods 5853 */ 5854 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5855 kobj_class_compile((kobj_class_t) driver); 5856 5857 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5858 if_setsoftc(ifp, ctx); 5859 if_setdev(ifp, dev); 5860 if_setinitfn(ifp, iflib_if_init); 5861 if_setioctlfn(ifp, iflib_if_ioctl); 5862 #ifdef ALTQ 5863 if_setstartfn(ifp, iflib_altq_if_start); 5864 if_settransmitfn(ifp, iflib_altq_if_transmit); 5865 if_setsendqready(ifp); 5866 #else 5867 if_settransmitfn(ifp, iflib_if_transmit); 5868 #endif 5869 if_setqflushfn(ifp, iflib_if_qflush); 5870 if_setgetcounterfn(ifp, iflib_if_get_counter); 5871 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5872 ctx->ifc_vlan_attach_event = 5873 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5874 EVENTHANDLER_PRI_FIRST); 5875 ctx->ifc_vlan_detach_event = 5876 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5877 EVENTHANDLER_PRI_FIRST); 5878 5879 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5880 ctx->ifc_mediap = &ctx->ifc_media; 5881 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5882 iflib_media_change, iflib_media_status); 5883 } 5884 } 5885 5886 static void 5887 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5888 { 5889 /* Unregister VLAN events */ 5890 if (ctx->ifc_vlan_attach_event != NULL) { 5891 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5892 ctx->ifc_vlan_attach_event = NULL; 5893 } 5894 if (ctx->ifc_vlan_detach_event != NULL) { 5895 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5896 ctx->ifc_vlan_detach_event = NULL; 5897 } 5898 5899 } 5900 5901 static void 5902 iflib_deregister(if_ctx_t ctx) 5903 { 5904 if_t ifp = ctx->ifc_ifp; 5905 5906 /* Remove all media */ 5907 ifmedia_removeall(&ctx->ifc_media); 5908 5909 /* Ensure that VLAN event handlers are unregistered */ 5910 iflib_unregister_vlan_handlers(ctx); 5911 5912 /* Release kobject reference */ 5913 kobj_delete((kobj_t) ctx, NULL); 5914 5915 /* Free the ifnet structure */ 5916 if_free(ifp); 5917 5918 STATE_LOCK_DESTROY(ctx); 5919 5920 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5921 CTX_LOCK_DESTROY(ctx); 5922 } 5923 5924 static int 5925 iflib_queues_alloc(if_ctx_t ctx) 5926 { 5927 if_shared_ctx_t sctx = ctx->ifc_sctx; 5928 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5929 device_t dev = ctx->ifc_dev; 5930 int nrxqsets = scctx->isc_nrxqsets; 5931 int ntxqsets = scctx->isc_ntxqsets; 5932 iflib_txq_t txq; 5933 iflib_rxq_t rxq; 5934 iflib_fl_t fl = NULL; 5935 int i, j, cpu, err, txconf, rxconf; 5936 iflib_dma_info_t ifdip; 5937 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5938 uint32_t *txqsizes = scctx->isc_txqsizes; 5939 uint8_t nrxqs = sctx->isc_nrxqs; 5940 uint8_t ntxqs = sctx->isc_ntxqs; 5941 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5942 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0); 5943 caddr_t *vaddrs; 5944 uint64_t *paddrs; 5945 5946 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5947 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5948 KASSERT(nrxqs >= fl_offset + nfree_lists, 5949 ("there must be at least a rxq for each free list")); 5950 5951 /* Allocate the TX ring struct memory */ 5952 if (!(ctx->ifc_txqs = 5953 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5954 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5955 device_printf(dev, "Unable to allocate TX ring memory\n"); 5956 err = ENOMEM; 5957 goto fail; 5958 } 5959 5960 /* Now allocate the RX */ 5961 if (!(ctx->ifc_rxqs = 5962 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5963 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5964 device_printf(dev, "Unable to allocate RX ring memory\n"); 5965 err = ENOMEM; 5966 goto rx_fail; 5967 } 5968 5969 txq = ctx->ifc_txqs; 5970 rxq = ctx->ifc_rxqs; 5971 5972 /* 5973 * XXX handle allocation failure 5974 */ 5975 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5976 /* Set up some basics */ 5977 5978 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5979 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5980 device_printf(dev, 5981 "Unable to allocate TX DMA info memory\n"); 5982 err = ENOMEM; 5983 goto err_tx_desc; 5984 } 5985 txq->ift_ifdi = ifdip; 5986 for (j = 0; j < ntxqs; j++, ifdip++) { 5987 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5988 device_printf(dev, 5989 "Unable to allocate TX descriptors\n"); 5990 err = ENOMEM; 5991 goto err_tx_desc; 5992 } 5993 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5994 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5995 } 5996 txq->ift_ctx = ctx; 5997 txq->ift_id = i; 5998 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5999 txq->ift_br_offset = 1; 6000 } else { 6001 txq->ift_br_offset = 0; 6002 } 6003 6004 if (iflib_txsd_alloc(txq)) { 6005 device_printf(dev, "Critical Failure setting up TX buffers\n"); 6006 err = ENOMEM; 6007 goto err_tx_desc; 6008 } 6009 6010 /* Initialize the TX lock */ 6011 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 6012 device_get_nameunit(dev), txq->ift_id); 6013 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 6014 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 6015 txq->ift_timer.c_cpu = cpu; 6016 #ifdef DEV_NETMAP 6017 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 6018 txq->ift_netmap_timer.c_cpu = cpu; 6019 #endif /* DEV_NETMAP */ 6020 6021 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 6022 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 6023 if (err) { 6024 /* XXX free any allocated rings */ 6025 device_printf(dev, "Unable to allocate buf_ring\n"); 6026 goto err_tx_desc; 6027 } 6028 txq->ift_reclaim_thresh = ctx->ifc_sysctl_tx_reclaim_thresh; 6029 } 6030 6031 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 6032 /* Set up some basics */ 6033 callout_init(&rxq->ifr_watchdog, 1); 6034 6035 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 6036 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 6037 device_printf(dev, 6038 "Unable to allocate RX DMA info memory\n"); 6039 err = ENOMEM; 6040 goto err_tx_desc; 6041 } 6042 6043 rxq->ifr_ifdi = ifdip; 6044 /* XXX this needs to be changed if #rx queues != #tx queues */ 6045 rxq->ifr_ntxqirq = 1; 6046 rxq->ifr_txqid[0] = i; 6047 for (j = 0; j < nrxqs; j++, ifdip++) { 6048 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 6049 device_printf(dev, 6050 "Unable to allocate RX descriptors\n"); 6051 err = ENOMEM; 6052 goto err_tx_desc; 6053 } 6054 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 6055 } 6056 rxq->ifr_ctx = ctx; 6057 rxq->ifr_id = i; 6058 rxq->ifr_fl_offset = fl_offset; 6059 rxq->ifr_nfl = nfree_lists; 6060 if (!(fl = 6061 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 6062 device_printf(dev, "Unable to allocate free list memory\n"); 6063 err = ENOMEM; 6064 goto err_tx_desc; 6065 } 6066 rxq->ifr_fl = fl; 6067 for (j = 0; j < nfree_lists; j++) { 6068 fl[j].ifl_rxq = rxq; 6069 fl[j].ifl_id = j; 6070 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 6071 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 6072 } 6073 /* Allocate receive buffers for the ring */ 6074 if (iflib_rxsd_alloc(rxq)) { 6075 device_printf(dev, 6076 "Critical Failure setting up receive buffers\n"); 6077 err = ENOMEM; 6078 goto err_rx_desc; 6079 } 6080 6081 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 6082 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 6083 M_WAITOK); 6084 } 6085 6086 /* TXQs */ 6087 vaddrs = malloc(sizeof(caddr_t) * ntxqsets * ntxqs, M_IFLIB, M_WAITOK); 6088 paddrs = malloc(sizeof(uint64_t) * ntxqsets * ntxqs, M_IFLIB, M_WAITOK); 6089 for (i = 0; i < ntxqsets; i++) { 6090 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 6091 6092 for (j = 0; j < ntxqs; j++, di++) { 6093 vaddrs[i * ntxqs + j] = di->idi_vaddr; 6094 paddrs[i * ntxqs + j] = di->idi_paddr; 6095 } 6096 } 6097 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 6098 device_printf(ctx->ifc_dev, 6099 "Unable to allocate device TX queue\n"); 6100 iflib_tx_structures_free(ctx); 6101 free(vaddrs, M_IFLIB); 6102 free(paddrs, M_IFLIB); 6103 goto err_rx_desc; 6104 } 6105 free(vaddrs, M_IFLIB); 6106 free(paddrs, M_IFLIB); 6107 6108 /* RXQs */ 6109 vaddrs = malloc(sizeof(caddr_t) * nrxqsets * nrxqs, M_IFLIB, M_WAITOK); 6110 paddrs = malloc(sizeof(uint64_t) * nrxqsets * nrxqs, M_IFLIB, M_WAITOK); 6111 for (i = 0; i < nrxqsets; i++) { 6112 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 6113 6114 for (j = 0; j < nrxqs; j++, di++) { 6115 vaddrs[i * nrxqs + j] = di->idi_vaddr; 6116 paddrs[i * nrxqs + j] = di->idi_paddr; 6117 } 6118 } 6119 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 6120 device_printf(ctx->ifc_dev, 6121 "Unable to allocate device RX queue\n"); 6122 iflib_tx_structures_free(ctx); 6123 free(vaddrs, M_IFLIB); 6124 free(paddrs, M_IFLIB); 6125 goto err_rx_desc; 6126 } 6127 free(vaddrs, M_IFLIB); 6128 free(paddrs, M_IFLIB); 6129 6130 return (0); 6131 6132 /* XXX handle allocation failure changes */ 6133 err_rx_desc: 6134 err_tx_desc: 6135 rx_fail: 6136 if (ctx->ifc_rxqs != NULL) 6137 free(ctx->ifc_rxqs, M_IFLIB); 6138 ctx->ifc_rxqs = NULL; 6139 if (ctx->ifc_txqs != NULL) 6140 free(ctx->ifc_txqs, M_IFLIB); 6141 ctx->ifc_txqs = NULL; 6142 fail: 6143 return (err); 6144 } 6145 6146 static int 6147 iflib_tx_structures_setup(if_ctx_t ctx) 6148 { 6149 iflib_txq_t txq = ctx->ifc_txqs; 6150 int i; 6151 6152 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 6153 iflib_txq_setup(txq); 6154 6155 return (0); 6156 } 6157 6158 static void 6159 iflib_tx_structures_free(if_ctx_t ctx) 6160 { 6161 iflib_txq_t txq = ctx->ifc_txqs; 6162 if_shared_ctx_t sctx = ctx->ifc_sctx; 6163 int i, j; 6164 6165 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6166 for (j = 0; j < sctx->isc_ntxqs; j++) 6167 iflib_dma_free(&txq->ift_ifdi[j]); 6168 iflib_txq_destroy(txq); 6169 } 6170 free(ctx->ifc_txqs, M_IFLIB); 6171 ctx->ifc_txqs = NULL; 6172 } 6173 6174 /********************************************************************* 6175 * 6176 * Initialize all receive rings. 6177 * 6178 **********************************************************************/ 6179 static int 6180 iflib_rx_structures_setup(if_ctx_t ctx) 6181 { 6182 iflib_rxq_t rxq = ctx->ifc_rxqs; 6183 int q; 6184 #if defined(INET6) || defined(INET) 6185 int err, i; 6186 #endif 6187 6188 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 6189 #if defined(INET6) || defined(INET) 6190 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 6191 TCP_LRO_ENTRIES, min(1024, 6192 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 6193 if (err != 0) { 6194 device_printf(ctx->ifc_dev, 6195 "LRO Initialization failed!\n"); 6196 goto fail; 6197 } 6198 #endif 6199 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 6200 } 6201 return (0); 6202 #if defined(INET6) || defined(INET) 6203 fail: 6204 /* 6205 * Free LRO resources allocated so far, we will only handle 6206 * the rings that completed, the failing case will have 6207 * cleaned up for itself. 'q' failed, so its the terminus. 6208 */ 6209 rxq = ctx->ifc_rxqs; 6210 for (i = 0; i < q; ++i, rxq++) { 6211 tcp_lro_free(&rxq->ifr_lc); 6212 } 6213 return (err); 6214 #endif 6215 } 6216 6217 /********************************************************************* 6218 * 6219 * Free all receive rings. 6220 * 6221 **********************************************************************/ 6222 static void 6223 iflib_rx_structures_free(if_ctx_t ctx) 6224 { 6225 iflib_rxq_t rxq = ctx->ifc_rxqs; 6226 if_shared_ctx_t sctx = ctx->ifc_sctx; 6227 int i, j; 6228 6229 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 6230 for (j = 0; j < sctx->isc_nrxqs; j++) 6231 iflib_dma_free(&rxq->ifr_ifdi[j]); 6232 iflib_rx_sds_free(rxq); 6233 #if defined(INET6) || defined(INET) 6234 tcp_lro_free(&rxq->ifr_lc); 6235 #endif 6236 } 6237 free(ctx->ifc_rxqs, M_IFLIB); 6238 ctx->ifc_rxqs = NULL; 6239 } 6240 6241 static int 6242 iflib_qset_structures_setup(if_ctx_t ctx) 6243 { 6244 int err; 6245 6246 /* 6247 * It is expected that the caller takes care of freeing queues if this 6248 * fails. 6249 */ 6250 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 6251 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 6252 return (err); 6253 } 6254 6255 if ((err = iflib_rx_structures_setup(ctx)) != 0) 6256 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 6257 6258 return (err); 6259 } 6260 6261 int 6262 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 6263 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 6264 { 6265 6266 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 6267 } 6268 6269 /* Just to avoid copy/paste */ 6270 static inline int 6271 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6272 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 6273 const char *name) 6274 { 6275 device_t dev; 6276 unsigned int base_cpuid, cpuid; 6277 int err; 6278 6279 dev = ctx->ifc_dev; 6280 base_cpuid = ctx->ifc_sysctl_core_offset; 6281 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX); 6282 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, 6283 irq ? irq->ii_res : NULL, name); 6284 if (err) { 6285 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6286 return (err); 6287 } 6288 #ifdef notyet 6289 if (cpuid > ctx->ifc_cpuid_highest) 6290 ctx->ifc_cpuid_highest = cpuid; 6291 #endif 6292 return (0); 6293 } 6294 6295 /* 6296 * Allocate a hardware interrupt for subctx using the parent (ctx)'s hardware 6297 * resources. 6298 * 6299 * Similar to iflib_irq_alloc_generic(), but for interrupt type IFLIB_INTR_RXTX 6300 * only. 6301 * 6302 * XXX: Could be removed if subctx's dev has its intr resource allocation 6303 * methods replaced with custom ones? 6304 */ 6305 int 6306 iflib_irq_alloc_generic_subctx(if_ctx_t ctx, if_ctx_t subctx, if_irq_t irq, 6307 int rid, iflib_intr_type_t type, 6308 driver_filter_t *filter, void *filter_arg, 6309 int qid, const char *name) 6310 { 6311 device_t dev, subdev; 6312 struct grouptask *gtask; 6313 struct taskqgroup *tqg; 6314 iflib_filter_info_t info; 6315 gtask_fn_t *fn; 6316 int tqrid, err; 6317 driver_filter_t *intr_fast; 6318 void *q; 6319 6320 MPASS(ctx != NULL); 6321 MPASS(subctx != NULL); 6322 6323 tqrid = rid; 6324 dev = ctx->ifc_dev; 6325 subdev = subctx->ifc_dev; 6326 6327 switch (type) { 6328 case IFLIB_INTR_RXTX: 6329 q = &subctx->ifc_rxqs[qid]; 6330 info = &subctx->ifc_rxqs[qid].ifr_filter_info; 6331 gtask = &subctx->ifc_rxqs[qid].ifr_task; 6332 tqg = qgroup_if_io_tqg; 6333 fn = _task_fn_rx; 6334 intr_fast = iflib_fast_intr_rxtx; 6335 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6336 break; 6337 default: 6338 device_printf(dev, "%s: unknown net intr type for subctx %s (%d)\n", 6339 __func__, device_get_nameunit(subdev), type); 6340 return (EINVAL); 6341 } 6342 6343 info->ifi_filter = filter; 6344 info->ifi_filter_arg = filter_arg; 6345 info->ifi_task = gtask; 6346 info->ifi_ctx = q; 6347 6348 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6349 6350 /* Allocate interrupts from hardware using parent context */ 6351 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6352 if (err != 0) { 6353 device_printf(dev, "_iflib_irq_alloc failed for subctx %s: %d\n", 6354 device_get_nameunit(subdev), err); 6355 return (err); 6356 } 6357 6358 if (tqrid != -1) { 6359 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6360 name); 6361 if (err) 6362 return (err); 6363 } else { 6364 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6365 } 6366 6367 return (0); 6368 } 6369 6370 int 6371 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6372 iflib_intr_type_t type, driver_filter_t *filter, 6373 void *filter_arg, int qid, const char *name) 6374 { 6375 device_t dev; 6376 struct grouptask *gtask; 6377 struct taskqgroup *tqg; 6378 iflib_filter_info_t info; 6379 gtask_fn_t *fn; 6380 int tqrid, err; 6381 driver_filter_t *intr_fast; 6382 void *q; 6383 6384 info = &ctx->ifc_filter_info; 6385 tqrid = rid; 6386 6387 switch (type) { 6388 /* XXX merge tx/rx for netmap? */ 6389 case IFLIB_INTR_TX: 6390 q = &ctx->ifc_txqs[qid]; 6391 info = &ctx->ifc_txqs[qid].ift_filter_info; 6392 gtask = &ctx->ifc_txqs[qid].ift_task; 6393 tqg = qgroup_if_io_tqg; 6394 fn = _task_fn_tx; 6395 intr_fast = iflib_fast_intr; 6396 GROUPTASK_INIT(gtask, 0, fn, q); 6397 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6398 break; 6399 case IFLIB_INTR_RX: 6400 q = &ctx->ifc_rxqs[qid]; 6401 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6402 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6403 tqg = qgroup_if_io_tqg; 6404 fn = _task_fn_rx; 6405 intr_fast = iflib_fast_intr; 6406 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6407 break; 6408 case IFLIB_INTR_RXTX: 6409 q = &ctx->ifc_rxqs[qid]; 6410 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6411 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6412 tqg = qgroup_if_io_tqg; 6413 fn = _task_fn_rx; 6414 intr_fast = iflib_fast_intr_rxtx; 6415 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6416 break; 6417 case IFLIB_INTR_ADMIN: 6418 q = ctx; 6419 tqrid = -1; 6420 info = &ctx->ifc_filter_info; 6421 gtask = NULL; 6422 intr_fast = iflib_fast_intr_ctx; 6423 break; 6424 default: 6425 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6426 __func__); 6427 return (EINVAL); 6428 } 6429 6430 info->ifi_filter = filter; 6431 info->ifi_filter_arg = filter_arg; 6432 info->ifi_task = gtask; 6433 info->ifi_ctx = q; 6434 6435 dev = ctx->ifc_dev; 6436 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6437 if (err != 0) { 6438 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6439 return (err); 6440 } 6441 if (type == IFLIB_INTR_ADMIN) 6442 return (0); 6443 6444 if (tqrid != -1) { 6445 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6446 name); 6447 if (err) 6448 return (err); 6449 } else { 6450 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6451 } 6452 6453 return (0); 6454 } 6455 6456 void 6457 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6458 void *arg, int qid, const char *name) 6459 { 6460 device_t dev; 6461 struct grouptask *gtask; 6462 struct taskqgroup *tqg; 6463 gtask_fn_t *fn; 6464 void *q; 6465 int err; 6466 6467 switch (type) { 6468 case IFLIB_INTR_TX: 6469 q = &ctx->ifc_txqs[qid]; 6470 gtask = &ctx->ifc_txqs[qid].ift_task; 6471 tqg = qgroup_if_io_tqg; 6472 fn = _task_fn_tx; 6473 GROUPTASK_INIT(gtask, 0, fn, q); 6474 break; 6475 case IFLIB_INTR_RX: 6476 q = &ctx->ifc_rxqs[qid]; 6477 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6478 tqg = qgroup_if_io_tqg; 6479 fn = _task_fn_rx; 6480 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6481 break; 6482 case IFLIB_INTR_IOV: 6483 TASK_INIT(&ctx->ifc_vflr_task, 0, _task_fn_iov, ctx); 6484 return; 6485 default: 6486 panic("unknown net intr type"); 6487 } 6488 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name); 6489 if (err) { 6490 dev = ctx->ifc_dev; 6491 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL, 6492 name); 6493 } 6494 } 6495 6496 void 6497 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6498 { 6499 6500 if (irq->ii_tag) 6501 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6502 6503 if (irq->ii_res) 6504 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6505 rman_get_rid(irq->ii_res), irq->ii_res); 6506 } 6507 6508 static int 6509 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6510 { 6511 iflib_txq_t txq = ctx->ifc_txqs; 6512 iflib_rxq_t rxq = ctx->ifc_rxqs; 6513 if_irq_t irq = &ctx->ifc_legacy_irq; 6514 iflib_filter_info_t info; 6515 device_t dev; 6516 struct grouptask *gtask; 6517 struct resource *res; 6518 int err, tqrid; 6519 bool rx_only; 6520 6521 info = &rxq->ifr_filter_info; 6522 gtask = &rxq->ifr_task; 6523 tqrid = *rid; 6524 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6525 6526 ctx->ifc_flags |= IFC_LEGACY; 6527 info->ifi_filter = filter; 6528 info->ifi_filter_arg = filter_arg; 6529 info->ifi_task = gtask; 6530 info->ifi_ctx = rxq; 6531 6532 dev = ctx->ifc_dev; 6533 /* We allocate a single interrupt resource */ 6534 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr : 6535 iflib_fast_intr_rxtx, NULL, info, name); 6536 if (err != 0) 6537 return (err); 6538 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, rxq); 6539 res = irq->ii_res; 6540 taskqgroup_attach(qgroup_if_io_tqg, gtask, rxq, dev, res, name); 6541 6542 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6543 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6544 "tx"); 6545 return (0); 6546 } 6547 6548 void 6549 iflib_led_create(if_ctx_t ctx) 6550 { 6551 6552 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6553 device_get_nameunit(ctx->ifc_dev)); 6554 } 6555 6556 void 6557 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6558 { 6559 6560 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6561 } 6562 6563 void 6564 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6565 { 6566 6567 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6568 } 6569 6570 void 6571 iflib_admin_intr_deferred(if_ctx_t ctx) 6572 { 6573 6574 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_admin_task); 6575 } 6576 6577 void 6578 iflib_iov_intr_deferred(if_ctx_t ctx) 6579 { 6580 6581 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_vflr_task); 6582 } 6583 6584 void 6585 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6586 { 6587 6588 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6589 name); 6590 } 6591 6592 void 6593 iflib_config_task_init(if_ctx_t ctx, struct task *config_task, task_fn_t *fn) 6594 { 6595 TASK_INIT(config_task, 0, fn, ctx); 6596 } 6597 6598 void 6599 iflib_config_task_enqueue(if_ctx_t ctx, struct task *config_task) 6600 { 6601 taskqueue_enqueue(ctx->ifc_tq, config_task); 6602 } 6603 6604 void 6605 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6606 { 6607 if_t ifp = ctx->ifc_ifp; 6608 6609 if_setbaudrate(ifp, baudrate); 6610 if (baudrate >= IF_Gbps(10)) { 6611 STATE_LOCK(ctx); 6612 ctx->ifc_flags |= IFC_PREFETCH; 6613 STATE_UNLOCK(ctx); 6614 } 6615 ctx->ifc_link_state = link_state; 6616 if_link_state_change(ifp, link_state); 6617 } 6618 6619 static int 6620 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6621 { 6622 int credits; 6623 #ifdef INVARIANTS 6624 int credits_pre = txq->ift_cidx_processed; 6625 #endif 6626 6627 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6628 BUS_DMASYNC_POSTREAD); 6629 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6630 return (0); 6631 6632 txq->ift_processed += credits; 6633 txq->ift_cidx_processed += credits; 6634 6635 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6636 if (txq->ift_cidx_processed >= txq->ift_size) 6637 txq->ift_cidx_processed -= txq->ift_size; 6638 return (credits); 6639 } 6640 6641 static int 6642 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6643 { 6644 iflib_fl_t fl; 6645 u_int i; 6646 6647 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6648 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6649 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6650 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6651 budget)); 6652 } 6653 6654 void 6655 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6656 const char *description, if_int_delay_info_t info, 6657 int offset, int value) 6658 { 6659 info->iidi_ctx = ctx; 6660 info->iidi_offset = offset; 6661 info->iidi_value = value; 6662 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6663 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6664 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6665 info, 0, iflib_sysctl_int_delay, "I", description); 6666 } 6667 6668 struct sx * 6669 iflib_ctx_lock_get(if_ctx_t ctx) 6670 { 6671 6672 return (&ctx->ifc_ctx_sx); 6673 } 6674 6675 static int 6676 iflib_msix_init(if_ctx_t ctx) 6677 { 6678 device_t dev = ctx->ifc_dev; 6679 if_shared_ctx_t sctx = ctx->ifc_sctx; 6680 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6681 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6682 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6683 6684 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6685 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6686 6687 if (bootverbose) 6688 device_printf(dev, "msix_init qsets capped at %d\n", 6689 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6690 6691 /* Override by tuneable */ 6692 if (scctx->isc_disable_msix) 6693 goto msi; 6694 6695 /* First try MSI-X */ 6696 if ((msgs = pci_msix_count(dev)) == 0) { 6697 if (bootverbose) 6698 device_printf(dev, "MSI-X not supported or disabled\n"); 6699 goto msi; 6700 } 6701 6702 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6703 /* 6704 * bar == -1 => "trust me I know what I'm doing" 6705 * Some drivers are for hardware that is so shoddily 6706 * documented that no one knows which bars are which 6707 * so the developer has to map all bars. This hack 6708 * allows shoddy garbage to use MSI-X in this framework. 6709 */ 6710 if (bar != -1) { 6711 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6712 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6713 if (ctx->ifc_msix_mem == NULL) { 6714 device_printf(dev, "Unable to map MSI-X table\n"); 6715 goto msi; 6716 } 6717 } 6718 6719 admincnt = sctx->isc_admin_intrcnt; 6720 #if IFLIB_DEBUG 6721 /* use only 1 qset in debug mode */ 6722 queuemsgs = min(msgs - admincnt, 1); 6723 #else 6724 queuemsgs = msgs - admincnt; 6725 #endif 6726 #ifdef RSS 6727 queues = imin(queuemsgs, rss_getnumbuckets()); 6728 #else 6729 queues = queuemsgs; 6730 #endif 6731 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6732 if (bootverbose) 6733 device_printf(dev, 6734 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6735 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6736 #ifdef RSS 6737 /* If we're doing RSS, clamp at the number of RSS buckets */ 6738 if (queues > rss_getnumbuckets()) 6739 queues = rss_getnumbuckets(); 6740 #endif 6741 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6742 rx_queues = iflib_num_rx_queues; 6743 else 6744 rx_queues = queues; 6745 6746 if (rx_queues > scctx->isc_nrxqsets) 6747 rx_queues = scctx->isc_nrxqsets; 6748 6749 /* 6750 * We want this to be all logical CPUs by default 6751 */ 6752 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6753 tx_queues = iflib_num_tx_queues; 6754 else 6755 tx_queues = mp_ncpus; 6756 6757 if (tx_queues > scctx->isc_ntxqsets) 6758 tx_queues = scctx->isc_ntxqsets; 6759 6760 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6761 #ifdef INVARIANTS 6762 if (tx_queues != rx_queues) 6763 device_printf(dev, 6764 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6765 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6766 #endif 6767 tx_queues = min(rx_queues, tx_queues); 6768 rx_queues = min(rx_queues, tx_queues); 6769 } 6770 6771 vectors = rx_queues + admincnt; 6772 if (msgs < vectors) { 6773 device_printf(dev, 6774 "insufficient number of MSI-X vectors " 6775 "(supported %d, need %d)\n", msgs, vectors); 6776 goto msi; 6777 } 6778 6779 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6780 tx_queues); 6781 msgs = vectors; 6782 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6783 if (vectors != msgs) { 6784 device_printf(dev, 6785 "Unable to allocate sufficient MSI-X vectors " 6786 "(got %d, need %d)\n", vectors, msgs); 6787 pci_release_msi(dev); 6788 if (bar != -1) { 6789 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6790 ctx->ifc_msix_mem); 6791 ctx->ifc_msix_mem = NULL; 6792 } 6793 goto msi; 6794 } 6795 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6796 vectors); 6797 scctx->isc_vectors = vectors; 6798 scctx->isc_nrxqsets = rx_queues; 6799 scctx->isc_ntxqsets = tx_queues; 6800 scctx->isc_intr = IFLIB_INTR_MSIX; 6801 6802 return (vectors); 6803 } else { 6804 device_printf(dev, 6805 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6806 err); 6807 if (bar != -1) { 6808 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6809 ctx->ifc_msix_mem); 6810 ctx->ifc_msix_mem = NULL; 6811 } 6812 } 6813 6814 msi: 6815 vectors = pci_msi_count(dev); 6816 scctx->isc_nrxqsets = 1; 6817 scctx->isc_ntxqsets = 1; 6818 scctx->isc_vectors = vectors; 6819 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6820 device_printf(dev, "Using an MSI interrupt\n"); 6821 scctx->isc_intr = IFLIB_INTR_MSI; 6822 } else { 6823 scctx->isc_vectors = 1; 6824 device_printf(dev, "Using a Legacy interrupt\n"); 6825 scctx->isc_intr = IFLIB_INTR_LEGACY; 6826 } 6827 6828 return (vectors); 6829 } 6830 6831 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6832 6833 static int 6834 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6835 { 6836 int rc; 6837 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6838 struct sbuf *sb; 6839 const char *ring_state = "UNKNOWN"; 6840 6841 /* XXX needed ? */ 6842 rc = sysctl_wire_old_buffer(req, 0); 6843 MPASS(rc == 0); 6844 if (rc != 0) 6845 return (rc); 6846 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6847 MPASS(sb != NULL); 6848 if (sb == NULL) 6849 return (ENOMEM); 6850 if (state[3] <= 3) 6851 ring_state = ring_states[state[3]]; 6852 6853 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6854 state[0], state[1], state[2], ring_state); 6855 rc = sbuf_finish(sb); 6856 sbuf_delete(sb); 6857 return (rc); 6858 } 6859 6860 enum iflib_ndesc_handler { 6861 IFLIB_NTXD_HANDLER, 6862 IFLIB_NRXD_HANDLER, 6863 }; 6864 6865 static int 6866 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6867 { 6868 if_ctx_t ctx = (void *)arg1; 6869 enum iflib_ndesc_handler type = arg2; 6870 char buf[256] = {0}; 6871 qidx_t *ndesc; 6872 char *p, *next; 6873 int nqs, rc, i; 6874 6875 nqs = 8; 6876 switch (type) { 6877 case IFLIB_NTXD_HANDLER: 6878 ndesc = ctx->ifc_sysctl_ntxds; 6879 if (ctx->ifc_sctx) 6880 nqs = ctx->ifc_sctx->isc_ntxqs; 6881 break; 6882 case IFLIB_NRXD_HANDLER: 6883 ndesc = ctx->ifc_sysctl_nrxds; 6884 if (ctx->ifc_sctx) 6885 nqs = ctx->ifc_sctx->isc_nrxqs; 6886 break; 6887 default: 6888 printf("%s: unhandled type\n", __func__); 6889 return (EINVAL); 6890 } 6891 if (nqs == 0) 6892 nqs = 8; 6893 6894 for (i = 0; i < 8; i++) { 6895 if (i >= nqs) 6896 break; 6897 if (i) 6898 strcat(buf, ","); 6899 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6900 } 6901 6902 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6903 if (rc || req->newptr == NULL) 6904 return (rc); 6905 6906 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6907 i++, p = strsep(&next, " ,")) { 6908 ndesc[i] = strtoul(p, NULL, 10); 6909 } 6910 6911 return (rc); 6912 } 6913 6914 static int 6915 iflib_handle_tx_reclaim_thresh(SYSCTL_HANDLER_ARGS) 6916 { 6917 if_ctx_t ctx = (void *)arg1; 6918 iflib_txq_t txq; 6919 int i, err; 6920 int thresh; 6921 6922 thresh = ctx->ifc_sysctl_tx_reclaim_thresh; 6923 err = sysctl_handle_int(oidp, &thresh, arg2, req); 6924 if (err != 0) { 6925 return err; 6926 } 6927 6928 if (thresh == ctx->ifc_sysctl_tx_reclaim_thresh) 6929 return 0; 6930 6931 if (thresh > ctx->ifc_softc_ctx.isc_ntxd[0] / 2) { 6932 device_printf(ctx->ifc_dev, "TX Reclaim thresh must be <= %d\n", 6933 ctx->ifc_softc_ctx.isc_ntxd[0] / 2); 6934 return (EINVAL); 6935 } 6936 6937 ctx->ifc_sysctl_tx_reclaim_thresh = thresh; 6938 if (ctx->ifc_txqs == NULL) 6939 return (err); 6940 6941 txq = &ctx->ifc_txqs[0]; 6942 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6943 txq->ift_reclaim_thresh = thresh; 6944 } 6945 return (err); 6946 } 6947 6948 static int 6949 iflib_handle_tx_reclaim_ticks(SYSCTL_HANDLER_ARGS) 6950 { 6951 if_ctx_t ctx = (void *)arg1; 6952 iflib_txq_t txq; 6953 int i, err; 6954 int ticks; 6955 6956 ticks = ctx->ifc_sysctl_tx_reclaim_ticks; 6957 err = sysctl_handle_int(oidp, &ticks, arg2, req); 6958 if (err != 0) { 6959 return err; 6960 } 6961 6962 if (ticks == ctx->ifc_sysctl_tx_reclaim_ticks) 6963 return 0; 6964 6965 if (ticks > hz) { 6966 device_printf(ctx->ifc_dev, 6967 "TX Reclaim ticks must be <= hz (%d)\n", hz); 6968 return (EINVAL); 6969 } 6970 6971 ctx->ifc_sysctl_tx_reclaim_ticks = ticks; 6972 if (ctx->ifc_txqs == NULL) 6973 return (err); 6974 6975 txq = &ctx->ifc_txqs[0]; 6976 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6977 txq->ift_reclaim_ticks = ticks; 6978 } 6979 return (err); 6980 } 6981 6982 static int 6983 iflib_handle_tx_defer_mfree(SYSCTL_HANDLER_ARGS) 6984 { 6985 if_ctx_t ctx = (void *)arg1; 6986 iflib_txq_t txq; 6987 int i, err; 6988 int defer; 6989 6990 defer = ctx->ifc_sysctl_tx_defer_mfree; 6991 err = sysctl_handle_int(oidp, &defer, arg2, req); 6992 if (err != 0) { 6993 return err; 6994 } 6995 6996 if (defer == ctx->ifc_sysctl_tx_defer_mfree) 6997 return 0; 6998 6999 ctx->ifc_sysctl_tx_defer_mfree = defer; 7000 if (ctx->ifc_txqs == NULL) 7001 return (err); 7002 7003 txq = &ctx->ifc_txqs[0]; 7004 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 7005 txq->ift_defer_mfree = defer; 7006 } 7007 return (err); 7008 } 7009 7010 #define NAME_BUFLEN 32 7011 static void 7012 iflib_add_device_sysctl_pre(if_ctx_t ctx) 7013 { 7014 device_t dev = iflib_get_dev(ctx); 7015 struct sysctl_oid_list *child, *oid_list; 7016 struct sysctl_oid *node; 7017 7018 sysctl_ctx_init(&ctx->ifc_sysctl_ctx); 7019 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 7020 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(&ctx->ifc_sysctl_ctx, child, 7021 OID_AUTO, "iflib", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 7022 "IFLIB fields"); 7023 oid_list = SYSCTL_CHILDREN(node); 7024 7025 SYSCTL_ADD_CONST_STRING(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "driver_version", 7026 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, "driver version"); 7027 SYSCTL_ADD_U32(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, 7028 "tx_watchdog_events", CTLFLAG_RD, &ctx->ifc_tx_watchdog_events, 0, 7029 "TX watchdog resets initiated by iflib"); 7030 7031 SYSCTL_ADD_BOOL(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "simple_tx", 7032 CTLFLAG_RDTUN, &ctx->ifc_sysctl_simple_tx, 0, 7033 "use simple tx ring"); 7034 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_ntxqs", 7035 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 7036 "# of txqs to use, 0 => use default #"); 7037 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_nrxqs", 7038 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 7039 "# of rxqs to use, 0 => use default #"); 7040 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_qs_enable", 7041 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 7042 "permit #txq != #rxq"); 7043 SYSCTL_ADD_INT(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "disable_msix", 7044 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 7045 "disable MSI-X (default 0)"); 7046 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "rx_budget", 7047 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, "set the RX budget"); 7048 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "tx_abdicate", 7049 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 7050 "cause TX to abdicate instead of running to completion"); 7051 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 7052 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "core_offset", 7053 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 7054 "offset to start using cores at"); 7055 SYSCTL_ADD_U8(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "separate_txrx", 7056 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 7057 "use separate cores for TX and RX"); 7058 SYSCTL_ADD_U8(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "use_logical_cores", 7059 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0, 7060 "try to make use of logical cores for TX and RX"); 7061 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "use_extra_msix_vectors", 7062 CTLFLAG_RDTUN, &ctx->ifc_sysctl_extra_msix_vectors, 0, 7063 "attempt to reserve the given number of extra MSI-X vectors during driver load for the creation of additional interfaces later"); 7064 SYSCTL_ADD_INT(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "allocated_msix_vectors", 7065 CTLFLAG_RDTUN, &ctx->ifc_softc_ctx.isc_vectors, 0, 7066 "total # of MSI-X vectors allocated by driver"); 7067 7068 /* XXX change for per-queue sizes */ 7069 SYSCTL_ADD_PROC(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_ntxds", 7070 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 7071 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 7072 "list of # of TX descriptors to use, 0 = use default #"); 7073 SYSCTL_ADD_PROC(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_nrxds", 7074 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 7075 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 7076 "list of # of RX descriptors to use, 0 = use default #"); 7077 } 7078 7079 static void 7080 iflib_add_device_sysctl_post(if_ctx_t ctx) 7081 { 7082 if_shared_ctx_t sctx = ctx->ifc_sctx; 7083 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 7084 struct sysctl_oid_list *child; 7085 struct sysctl_ctx_list *ctx_list = &ctx->ifc_sysctl_ctx; 7086 iflib_fl_t fl; 7087 iflib_txq_t txq; 7088 iflib_rxq_t rxq; 7089 int i, j; 7090 char namebuf[NAME_BUFLEN]; 7091 char *qfmt; 7092 struct sysctl_oid *queue_node, *fl_node, *node; 7093 struct sysctl_oid_list *queue_list, *fl_list; 7094 7095 node = ctx->ifc_sysctl_node; 7096 child = SYSCTL_CHILDREN(node); 7097 7098 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_reclaim_thresh", 7099 CTLTYPE_INT | CTLFLAG_RWTUN, ctx, 7100 0, iflib_handle_tx_reclaim_thresh, "I", 7101 "Number of TX descs outstanding before reclaim is called"); 7102 7103 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_reclaim_ticks", 7104 CTLTYPE_INT | CTLFLAG_RWTUN, ctx, 7105 0, iflib_handle_tx_reclaim_ticks, "I", 7106 "Number of ticks before a TX reclaim is forced"); 7107 7108 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_defer_mfree", 7109 CTLTYPE_INT | CTLFLAG_RWTUN, ctx, 7110 0, iflib_handle_tx_defer_mfree, "I", 7111 "Free completed transmits outside of TX ring lock"); 7112 7113 if (scctx->isc_ntxqsets > 100) 7114 qfmt = "txq%03d"; 7115 else if (scctx->isc_ntxqsets > 10) 7116 qfmt = "txq%02d"; 7117 else 7118 qfmt = "txq%d"; 7119 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 7120 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 7121 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 7122 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 7123 queue_list = SYSCTL_CHILDREN(queue_node); 7124 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 7125 CTLFLAG_RD, &txq->ift_task.gt_cpu, 0, 7126 "cpu this queue is bound to"); 7127 #if MEMORY_LOGGING 7128 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 7129 CTLFLAG_RD, &txq->ift_dequeued, "total mbufs freed"); 7130 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 7131 CTLFLAG_RD, &txq->ift_enqueued, "total mbufs enqueued"); 7132 #endif 7133 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 7134 CTLFLAG_RD, &txq->ift_mbuf_defrag, 7135 "# of times m_defrag was called"); 7136 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 7137 CTLFLAG_RD, &txq->ift_pullups, 7138 "# of times m_pullup was called"); 7139 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7140 "mbuf_defrag_failed", CTLFLAG_RD, 7141 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 7142 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7143 "no_desc_avail", CTLFLAG_RD, &txq->ift_no_desc_avail, 7144 "# of times no descriptors were available"); 7145 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7146 "tx_map_failed", CTLFLAG_RD, &txq->ift_map_failed, 7147 "# of times DMA map failed"); 7148 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7149 "txd_encap_efbig", CTLFLAG_RD, &txq->ift_txd_encap_efbig, 7150 "# of times txd_encap returned EFBIG"); 7151 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7152 "no_tx_dma_setup", CTLFLAG_RD, &txq->ift_no_tx_dma_setup, 7153 "# of times map failed for other than EFBIG"); 7154 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 7155 CTLFLAG_RD, &txq->ift_pidx, 1, "Producer Index"); 7156 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 7157 CTLFLAG_RD, &txq->ift_cidx, 1, "Consumer Index"); 7158 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, 7159 "txq_cidx_processed", CTLFLAG_RD, &txq->ift_cidx_processed, 7160 1, "Consumer Index seen by credit update"); 7161 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 7162 CTLFLAG_RD, &txq->ift_in_use, 1, "descriptors in use"); 7163 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7164 "txq_processed", CTLFLAG_RD, &txq->ift_processed, 7165 "descriptors procesed for clean"); 7166 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 7167 CTLFLAG_RD, &txq->ift_cleaned, "total cleaned"); 7168 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 7169 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 7170 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 7171 mp_ring_state_handler, "A", "soft ring state"); 7172 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7173 "r_enqueues", CTLFLAG_RD, &txq->ift_br->enqueues, 7174 "# of enqueues to the mp_ring for this queue"); 7175 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7176 "r_drops", CTLFLAG_RD, &txq->ift_br->drops, 7177 "# of drops in the mp_ring for this queue"); 7178 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7179 "r_starts", CTLFLAG_RD, &txq->ift_br->starts, 7180 "# of normal consumer starts in mp_ring for this queue"); 7181 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7182 "r_stalls", CTLFLAG_RD, &txq->ift_br->stalls, 7183 "# of consumer stalls in the mp_ring for this queue"); 7184 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7185 "r_restarts", CTLFLAG_RD, &txq->ift_br->restarts, 7186 "# of consumer restarts in the mp_ring for this queue"); 7187 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7188 "r_abdications", CTLFLAG_RD, &txq->ift_br->abdications, 7189 "# of consumer abdications in the mp_ring for this queue"); 7190 } 7191 7192 if (scctx->isc_nrxqsets > 100) 7193 qfmt = "rxq%03d"; 7194 else if (scctx->isc_nrxqsets > 10) 7195 qfmt = "rxq%02d"; 7196 else 7197 qfmt = "rxq%d"; 7198 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 7199 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 7200 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 7201 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 7202 queue_list = SYSCTL_CHILDREN(queue_node); 7203 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 7204 CTLFLAG_RD, &rxq->ifr_task.gt_cpu, 0, 7205 "cpu this queue is bound to"); 7206 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 7207 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, 7208 "rxq_cq_cidx", CTLFLAG_RD, &rxq->ifr_cq_cidx, 1, 7209 "Consumer Index"); 7210 } 7211 7212 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 7213 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 7214 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, 7215 OID_AUTO, namebuf, CTLFLAG_RD | CTLFLAG_MPSAFE, 7216 NULL, "freelist Name"); 7217 fl_list = SYSCTL_CHILDREN(fl_node); 7218 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 7219 CTLFLAG_RD, &fl->ifl_pidx, 1, "Producer Index"); 7220 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 7221 CTLFLAG_RD, &fl->ifl_cidx, 1, "Consumer Index"); 7222 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 7223 CTLFLAG_RD, &fl->ifl_credits, 1, 7224 "credits available"); 7225 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 7226 CTLFLAG_RD, &fl->ifl_buf_size, 1, "buffer size"); 7227 #if MEMORY_LOGGING 7228 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7229 "fl_m_enqueued", CTLFLAG_RD, &fl->ifl_m_enqueued, 7230 "mbufs allocated"); 7231 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7232 "fl_m_dequeued", CTLFLAG_RD, &fl->ifl_m_dequeued, 7233 "mbufs freed"); 7234 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7235 "fl_cl_enqueued", CTLFLAG_RD, &fl->ifl_cl_enqueued, 7236 "clusters allocated"); 7237 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7238 "fl_cl_dequeued", CTLFLAG_RD, &fl->ifl_cl_dequeued, 7239 "clusters freed"); 7240 #endif 7241 } 7242 } 7243 7244 } 7245 7246 void 7247 iflib_request_reset(if_ctx_t ctx) 7248 { 7249 7250 STATE_LOCK(ctx); 7251 ctx->ifc_flags |= IFC_DO_RESET; 7252 STATE_UNLOCK(ctx); 7253 } 7254 7255 void 7256 iflib_request_reset_if_up(if_ctx_t ctx) 7257 { 7258 7259 STATE_LOCK(ctx); 7260 ctx->ifc_flags |= IFC_DO_RESET_IF_UP; 7261 STATE_UNLOCK(ctx); 7262 } 7263 7264 void 7265 iflib_init_failed(if_ctx_t ctx) 7266 { 7267 7268 sx_assert(&ctx->ifc_ctx_sx, SA_XLOCKED); 7269 STATE_LOCK(ctx); 7270 ctx->ifc_flags |= IFC_INIT_FAILED; 7271 STATE_UNLOCK(ctx); 7272 } 7273 7274 #ifndef __NO_STRICT_ALIGNMENT 7275 static struct mbuf * 7276 iflib_fixup_rx(struct mbuf *m) 7277 { 7278 struct mbuf *n; 7279 7280 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 7281 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 7282 m->m_data += ETHER_HDR_LEN; 7283 n = m; 7284 } else { 7285 MGETHDR(n, M_NOWAIT, MT_DATA); 7286 if (n == NULL) { 7287 m_freem(m); 7288 return (NULL); 7289 } 7290 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 7291 m->m_data += ETHER_HDR_LEN; 7292 m->m_len -= ETHER_HDR_LEN; 7293 n->m_len = ETHER_HDR_LEN; 7294 M_MOVE_PKTHDR(n, m); 7295 n->m_next = m; 7296 } 7297 return (n); 7298 } 7299 #endif 7300 7301 #ifdef DEBUGNET 7302 static void 7303 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 7304 { 7305 if_ctx_t ctx; 7306 7307 ctx = if_getsoftc(ifp); 7308 CTX_LOCK(ctx); 7309 *nrxr = NRXQSETS(ctx); 7310 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 7311 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 7312 CTX_UNLOCK(ctx); 7313 } 7314 7315 static void 7316 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 7317 { 7318 if_ctx_t ctx; 7319 if_softc_ctx_t scctx; 7320 iflib_fl_t fl; 7321 iflib_rxq_t rxq; 7322 int i, j; 7323 7324 ctx = if_getsoftc(ifp); 7325 scctx = &ctx->ifc_softc_ctx; 7326 7327 switch (event) { 7328 case DEBUGNET_START: 7329 for (i = 0; i < scctx->isc_nrxqsets; i++) { 7330 rxq = &ctx->ifc_rxqs[i]; 7331 for (j = 0; j < rxq->ifr_nfl; j++) { 7332 fl = rxq->ifr_fl; 7333 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 7334 } 7335 } 7336 iflib_no_tx_batch = 1; 7337 break; 7338 default: 7339 break; 7340 } 7341 } 7342 7343 static int 7344 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 7345 { 7346 if_ctx_t ctx; 7347 iflib_txq_t txq; 7348 int error; 7349 int bytes_sent = 0; 7350 int pkt_sent = 0; 7351 7352 ctx = if_getsoftc(ifp); 7353 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7354 IFF_DRV_RUNNING) 7355 return (EBUSY); 7356 7357 txq = &ctx->ifc_txqs[0]; 7358 error = iflib_encap(txq, &m, &bytes_sent, &pkt_sent); 7359 if (error == 0) 7360 (void)iflib_txd_db_check(txq, true); 7361 return (error); 7362 } 7363 7364 static int 7365 iflib_debugnet_poll(if_t ifp, int count) 7366 { 7367 struct epoch_tracker et; 7368 if_ctx_t ctx; 7369 if_softc_ctx_t scctx; 7370 iflib_txq_t txq; 7371 int i; 7372 7373 ctx = if_getsoftc(ifp); 7374 scctx = &ctx->ifc_softc_ctx; 7375 7376 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7377 IFF_DRV_RUNNING) 7378 return (EBUSY); 7379 7380 txq = &ctx->ifc_txqs[0]; 7381 (void)iflib_completed_tx_reclaim(txq, NULL); 7382 7383 NET_EPOCH_ENTER(et); 7384 for (i = 0; i < scctx->isc_nrxqsets; i++) 7385 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 7386 NET_EPOCH_EXIT(et); 7387 return (0); 7388 } 7389 #endif /* DEBUGNET */ 7390 7391 #ifndef ALTQ 7392 static inline iflib_txq_t 7393 iflib_simple_select_queue(if_ctx_t ctx, struct mbuf *m) 7394 { 7395 int qidx; 7396 7397 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 7398 qidx = QIDX(ctx, m); 7399 else 7400 qidx = NTXQSETS(ctx) + FIRST_QSET(ctx) - 1; 7401 return (&ctx->ifc_txqs[qidx]); 7402 } 7403 7404 static int 7405 iflib_simple_transmit(if_t ifp, struct mbuf *m) 7406 { 7407 if_ctx_t ctx; 7408 iflib_txq_t txq; 7409 struct mbuf **m_defer; 7410 int error, i, reclaimable; 7411 int bytes_sent = 0, pkt_sent = 0, mcast_sent = 0; 7412 7413 7414 ctx = if_getsoftc(ifp); 7415 if (__predict_false((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 7416 || !LINK_ACTIVE(ctx))) { 7417 DBG_COUNTER_INC(tx_frees); 7418 m_freem(m); 7419 return (ENETDOWN); 7420 } 7421 7422 txq = iflib_simple_select_queue(ctx, m); 7423 mtx_lock(&txq->ift_mtx); 7424 error = iflib_encap(txq, &m, &bytes_sent, &pkt_sent); 7425 if (error == 0) { 7426 mcast_sent += !!(m->m_flags & M_MCAST); 7427 (void)iflib_txd_db_check(txq, true); 7428 } else { 7429 if (error == ENOBUFS) 7430 if_inc_counter(ifp, IFCOUNTER_OQDROPS, 1); 7431 else 7432 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 7433 } 7434 m_defer = NULL; 7435 reclaimable = iflib_txq_can_reclaim(txq); 7436 if (reclaimable != 0) { 7437 /* 7438 * Try to set m_defer to the deferred mbuf reclaim array. If 7439 * we can, the frees will happen outside the tx lock. If we 7440 * can't, it means another thread is still proccessing frees. 7441 */ 7442 if (txq->ift_defer_mfree && 7443 atomic_cmpset_acq_ptr((uintptr_t *)&txq->ift_sds.ifsd_m_defer, 7444 (uintptr_t )txq->ift_sds.ifsd_m_deferb, 0)) { 7445 m_defer = txq->ift_sds.ifsd_m_deferb; 7446 } 7447 _iflib_completed_tx_reclaim(txq, m_defer, reclaimable); 7448 } 7449 mtx_unlock(&txq->ift_mtx); 7450 7451 /* 7452 * Process mbuf frees outside the tx lock 7453 */ 7454 if (m_defer != NULL) { 7455 for (i = 0; m_defer[i] != NULL; i++) { 7456 m_freem(m_defer[i]); 7457 m_defer[i] = NULL; 7458 } 7459 atomic_store_rel_ptr((uintptr_t *)&txq->ift_sds.ifsd_m_defer, 7460 (uintptr_t)m_defer); 7461 } 7462 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 7463 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 7464 if (mcast_sent) 7465 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 7466 7467 return (error); 7468 } 7469 #endif 7470