xref: /freebsd/sys/net/iflib.c (revision b4e38a41f584ad4391c04b8cfec81f46176b18b0)
1 /*-
2  * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  *  1. Redistributions of source code must retain the above copyright notice,
9  *     this list of conditions and the following disclaimer.
10  *
11  *  2. Neither the name of Matthew Macy nor the names of its
12  *     contributors may be used to endorse or promote products derived from
13  *     this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25  * POSSIBILITY OF SUCH DAMAGE.
26  */
27 
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30 
31 #include "opt_inet.h"
32 #include "opt_inet6.h"
33 #include "opt_acpi.h"
34 #include "opt_sched.h"
35 
36 #include <sys/param.h>
37 #include <sys/types.h>
38 #include <sys/bus.h>
39 #include <sys/eventhandler.h>
40 #include <sys/kernel.h>
41 #include <sys/lock.h>
42 #include <sys/mutex.h>
43 #include <sys/module.h>
44 #include <sys/kobj.h>
45 #include <sys/rman.h>
46 #include <sys/sbuf.h>
47 #include <sys/smp.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/syslog.h>
52 #include <sys/taskqueue.h>
53 #include <sys/limits.h>
54 
55 #include <net/if.h>
56 #include <net/if_var.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
59 #include <net/bpf.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
62 #include <net/debugnet.h>
63 #include <net/pfil.h>
64 #include <net/vnet.h>
65 
66 #include <netinet/in.h>
67 #include <netinet/in_pcb.h>
68 #include <netinet/tcp_lro.h>
69 #include <netinet/in_systm.h>
70 #include <netinet/if_ether.h>
71 #include <netinet/ip.h>
72 #include <netinet/ip6.h>
73 #include <netinet/tcp.h>
74 #include <netinet/ip_var.h>
75 #include <netinet6/ip6_var.h>
76 
77 #include <machine/bus.h>
78 #include <machine/in_cksum.h>
79 
80 #include <vm/vm.h>
81 #include <vm/pmap.h>
82 
83 #include <dev/led/led.h>
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
86 #include <dev/pci/pci_private.h>
87 
88 #include <net/iflib.h>
89 #include <net/iflib_private.h>
90 
91 #include "ifdi_if.h"
92 
93 #ifdef PCI_IOV
94 #include <dev/pci/pci_iov.h>
95 #endif
96 
97 #include <sys/bitstring.h>
98 /*
99  * enable accounting of every mbuf as it comes in to and goes out of
100  * iflib's software descriptor references
101  */
102 #define MEMORY_LOGGING 0
103 /*
104  * Enable mbuf vectors for compressing long mbuf chains
105  */
106 
107 /*
108  * NB:
109  * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110  *   we prefetch needs to be determined by the time spent in m_free vis a vis
111  *   the cost of a prefetch. This will of course vary based on the workload:
112  *      - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
113  *        is quite expensive, thus suggesting very little prefetch.
114  *      - small packet forwarding which is just returning a single mbuf to
115  *        UMA will typically be very fast vis a vis the cost of a memory
116  *        access.
117  */
118 
119 
120 /*
121  * File organization:
122  *  - private structures
123  *  - iflib private utility functions
124  *  - ifnet functions
125  *  - vlan registry and other exported functions
126  *  - iflib public core functions
127  *
128  *
129  */
130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
131 
132 #define	IFLIB_RXEOF_MORE (1U << 0)
133 #define	IFLIB_RXEOF_EMPTY (2U << 0)
134 
135 struct iflib_txq;
136 typedef struct iflib_txq *iflib_txq_t;
137 struct iflib_rxq;
138 typedef struct iflib_rxq *iflib_rxq_t;
139 struct iflib_fl;
140 typedef struct iflib_fl *iflib_fl_t;
141 
142 struct iflib_ctx;
143 
144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
145 static void iflib_timer(void *arg);
146 
147 typedef struct iflib_filter_info {
148 	driver_filter_t *ifi_filter;
149 	void *ifi_filter_arg;
150 	struct grouptask *ifi_task;
151 	void *ifi_ctx;
152 } *iflib_filter_info_t;
153 
154 struct iflib_ctx {
155 	KOBJ_FIELDS;
156 	/*
157 	 * Pointer to hardware driver's softc
158 	 */
159 	void *ifc_softc;
160 	device_t ifc_dev;
161 	if_t ifc_ifp;
162 
163 	cpuset_t ifc_cpus;
164 	if_shared_ctx_t ifc_sctx;
165 	struct if_softc_ctx ifc_softc_ctx;
166 
167 	struct sx ifc_ctx_sx;
168 	struct mtx ifc_state_mtx;
169 
170 	iflib_txq_t ifc_txqs;
171 	iflib_rxq_t ifc_rxqs;
172 	uint32_t ifc_if_flags;
173 	uint32_t ifc_flags;
174 	uint32_t ifc_max_fl_buf_size;
175 	uint32_t ifc_rx_mbuf_sz;
176 
177 	int ifc_link_state;
178 	int ifc_watchdog_events;
179 	struct cdev *ifc_led_dev;
180 	struct resource *ifc_msix_mem;
181 
182 	struct if_irq ifc_legacy_irq;
183 	struct grouptask ifc_admin_task;
184 	struct grouptask ifc_vflr_task;
185 	struct iflib_filter_info ifc_filter_info;
186 	struct ifmedia	ifc_media;
187 	struct ifmedia	*ifc_mediap;
188 
189 	struct sysctl_oid *ifc_sysctl_node;
190 	uint16_t ifc_sysctl_ntxqs;
191 	uint16_t ifc_sysctl_nrxqs;
192 	uint16_t ifc_sysctl_qs_eq_override;
193 	uint16_t ifc_sysctl_rx_budget;
194 	uint16_t ifc_sysctl_tx_abdicate;
195 	uint16_t ifc_sysctl_core_offset;
196 #define	CORE_OFFSET_UNSPECIFIED	0xffff
197 	uint8_t  ifc_sysctl_separate_txrx;
198 
199 	qidx_t ifc_sysctl_ntxds[8];
200 	qidx_t ifc_sysctl_nrxds[8];
201 	struct if_txrx ifc_txrx;
202 #define isc_txd_encap  ifc_txrx.ift_txd_encap
203 #define isc_txd_flush  ifc_txrx.ift_txd_flush
204 #define isc_txd_credits_update  ifc_txrx.ift_txd_credits_update
205 #define isc_rxd_available ifc_txrx.ift_rxd_available
206 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
208 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
209 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
210 	eventhandler_tag ifc_vlan_attach_event;
211 	eventhandler_tag ifc_vlan_detach_event;
212 	struct ether_addr ifc_mac;
213 };
214 
215 void *
216 iflib_get_softc(if_ctx_t ctx)
217 {
218 
219 	return (ctx->ifc_softc);
220 }
221 
222 device_t
223 iflib_get_dev(if_ctx_t ctx)
224 {
225 
226 	return (ctx->ifc_dev);
227 }
228 
229 if_t
230 iflib_get_ifp(if_ctx_t ctx)
231 {
232 
233 	return (ctx->ifc_ifp);
234 }
235 
236 struct ifmedia *
237 iflib_get_media(if_ctx_t ctx)
238 {
239 
240 	return (ctx->ifc_mediap);
241 }
242 
243 uint32_t
244 iflib_get_flags(if_ctx_t ctx)
245 {
246 	return (ctx->ifc_flags);
247 }
248 
249 void
250 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
251 {
252 
253 	bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
254 }
255 
256 if_softc_ctx_t
257 iflib_get_softc_ctx(if_ctx_t ctx)
258 {
259 
260 	return (&ctx->ifc_softc_ctx);
261 }
262 
263 if_shared_ctx_t
264 iflib_get_sctx(if_ctx_t ctx)
265 {
266 
267 	return (ctx->ifc_sctx);
268 }
269 
270 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
271 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*))
272 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1)))
273 
274 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
275 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
276 
277 typedef struct iflib_sw_rx_desc_array {
278 	bus_dmamap_t	*ifsd_map;         /* bus_dma maps for packet */
279 	struct mbuf	**ifsd_m;           /* pkthdr mbufs */
280 	caddr_t		*ifsd_cl;          /* direct cluster pointer for rx */
281 	bus_addr_t	*ifsd_ba;          /* bus addr of cluster for rx */
282 } iflib_rxsd_array_t;
283 
284 typedef struct iflib_sw_tx_desc_array {
285 	bus_dmamap_t    *ifsd_map;         /* bus_dma maps for packet */
286 	bus_dmamap_t	*ifsd_tso_map;     /* bus_dma maps for TSO packet */
287 	struct mbuf    **ifsd_m;           /* pkthdr mbufs */
288 } if_txsd_vec_t;
289 
290 /* magic number that should be high enough for any hardware */
291 #define IFLIB_MAX_TX_SEGS		128
292 #define IFLIB_RX_COPY_THRESH		128
293 #define IFLIB_MAX_RX_REFRESH		32
294 /* The minimum descriptors per second before we start coalescing */
295 #define IFLIB_MIN_DESC_SEC		16384
296 #define IFLIB_DEFAULT_TX_UPDATE_FREQ	16
297 #define IFLIB_QUEUE_IDLE		0
298 #define IFLIB_QUEUE_HUNG		1
299 #define IFLIB_QUEUE_WORKING		2
300 /* maximum number of txqs that can share an rx interrupt */
301 #define IFLIB_MAX_TX_SHARED_INTR	4
302 
303 /* this should really scale with ring size - this is a fairly arbitrary value */
304 #define TX_BATCH_SIZE			32
305 
306 #define IFLIB_RESTART_BUDGET		8
307 
308 #define CSUM_OFFLOAD		(CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
309 				 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
310 				 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
311 
312 struct iflib_txq {
313 	qidx_t		ift_in_use;
314 	qidx_t		ift_cidx;
315 	qidx_t		ift_cidx_processed;
316 	qidx_t		ift_pidx;
317 	uint8_t		ift_gen;
318 	uint8_t		ift_br_offset;
319 	uint16_t	ift_npending;
320 	uint16_t	ift_db_pending;
321 	uint16_t	ift_rs_pending;
322 	/* implicit pad */
323 	uint8_t		ift_txd_size[8];
324 	uint64_t	ift_processed;
325 	uint64_t	ift_cleaned;
326 	uint64_t	ift_cleaned_prev;
327 #if MEMORY_LOGGING
328 	uint64_t	ift_enqueued;
329 	uint64_t	ift_dequeued;
330 #endif
331 	uint64_t	ift_no_tx_dma_setup;
332 	uint64_t	ift_no_desc_avail;
333 	uint64_t	ift_mbuf_defrag_failed;
334 	uint64_t	ift_mbuf_defrag;
335 	uint64_t	ift_map_failed;
336 	uint64_t	ift_txd_encap_efbig;
337 	uint64_t	ift_pullups;
338 	uint64_t	ift_last_timer_tick;
339 
340 	struct mtx	ift_mtx;
341 	struct mtx	ift_db_mtx;
342 
343 	/* constant values */
344 	if_ctx_t	ift_ctx;
345 	struct ifmp_ring        *ift_br;
346 	struct grouptask	ift_task;
347 	qidx_t		ift_size;
348 	uint16_t	ift_id;
349 	struct callout	ift_timer;
350 
351 	if_txsd_vec_t	ift_sds;
352 	uint8_t		ift_qstatus;
353 	uint8_t		ift_closed;
354 	uint8_t		ift_update_freq;
355 	struct iflib_filter_info ift_filter_info;
356 	bus_dma_tag_t	ift_buf_tag;
357 	bus_dma_tag_t	ift_tso_buf_tag;
358 	iflib_dma_info_t	ift_ifdi;
359 #define	MTX_NAME_LEN	32
360 	char                    ift_mtx_name[MTX_NAME_LEN];
361 	bus_dma_segment_t	ift_segs[IFLIB_MAX_TX_SEGS]  __aligned(CACHE_LINE_SIZE);
362 #ifdef IFLIB_DIAGNOSTICS
363 	uint64_t ift_cpu_exec_count[256];
364 #endif
365 } __aligned(CACHE_LINE_SIZE);
366 
367 struct iflib_fl {
368 	qidx_t		ifl_cidx;
369 	qidx_t		ifl_pidx;
370 	qidx_t		ifl_credits;
371 	uint8_t		ifl_gen;
372 	uint8_t		ifl_rxd_size;
373 #if MEMORY_LOGGING
374 	uint64_t	ifl_m_enqueued;
375 	uint64_t	ifl_m_dequeued;
376 	uint64_t	ifl_cl_enqueued;
377 	uint64_t	ifl_cl_dequeued;
378 #endif
379 	/* implicit pad */
380 	bitstr_t 	*ifl_rx_bitmap;
381 	qidx_t		ifl_fragidx;
382 	/* constant */
383 	qidx_t		ifl_size;
384 	uint16_t	ifl_buf_size;
385 	uint16_t	ifl_cltype;
386 	uma_zone_t	ifl_zone;
387 	iflib_rxsd_array_t	ifl_sds;
388 	iflib_rxq_t	ifl_rxq;
389 	uint8_t		ifl_id;
390 	bus_dma_tag_t	ifl_buf_tag;
391 	iflib_dma_info_t	ifl_ifdi;
392 	uint64_t	ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
393 	qidx_t		ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
394 }  __aligned(CACHE_LINE_SIZE);
395 
396 static inline qidx_t
397 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
398 {
399 	qidx_t used;
400 
401 	if (pidx > cidx)
402 		used = pidx - cidx;
403 	else if (pidx < cidx)
404 		used = size - cidx + pidx;
405 	else if (gen == 0 && pidx == cidx)
406 		used = 0;
407 	else if (gen == 1 && pidx == cidx)
408 		used = size;
409 	else
410 		panic("bad state");
411 
412 	return (used);
413 }
414 
415 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
416 
417 #define IDXDIFF(head, tail, wrap) \
418 	((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
419 
420 struct iflib_rxq {
421 	if_ctx_t	ifr_ctx;
422 	iflib_fl_t	ifr_fl;
423 	uint64_t	ifr_rx_irq;
424 	struct pfil_head	*pfil;
425 	/*
426 	 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
427 	 * the command queue consumer index.  Otherwise it's unused.
428 	 */
429 	qidx_t		ifr_cq_cidx;
430 	uint16_t	ifr_id;
431 	uint8_t		ifr_nfl;
432 	uint8_t		ifr_ntxqirq;
433 	uint8_t		ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
434 	uint8_t		ifr_fl_offset;
435 	struct lro_ctrl			ifr_lc;
436 	struct grouptask        ifr_task;
437 	struct callout		ifr_watchdog;
438 	struct iflib_filter_info ifr_filter_info;
439 	iflib_dma_info_t		ifr_ifdi;
440 
441 	/* dynamically allocate if any drivers need a value substantially larger than this */
442 	struct if_rxd_frag	ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
443 #ifdef IFLIB_DIAGNOSTICS
444 	uint64_t ifr_cpu_exec_count[256];
445 #endif
446 }  __aligned(CACHE_LINE_SIZE);
447 
448 typedef struct if_rxsd {
449 	caddr_t *ifsd_cl;
450 	iflib_fl_t ifsd_fl;
451 } *if_rxsd_t;
452 
453 /* multiple of word size */
454 #ifdef __LP64__
455 #define PKT_INFO_SIZE	6
456 #define RXD_INFO_SIZE	5
457 #define PKT_TYPE uint64_t
458 #else
459 #define PKT_INFO_SIZE	11
460 #define RXD_INFO_SIZE	8
461 #define PKT_TYPE uint32_t
462 #endif
463 #define PKT_LOOP_BOUND  ((PKT_INFO_SIZE/3)*3)
464 #define RXD_LOOP_BOUND  ((RXD_INFO_SIZE/4)*4)
465 
466 typedef struct if_pkt_info_pad {
467 	PKT_TYPE pkt_val[PKT_INFO_SIZE];
468 } *if_pkt_info_pad_t;
469 typedef struct if_rxd_info_pad {
470 	PKT_TYPE rxd_val[RXD_INFO_SIZE];
471 } *if_rxd_info_pad_t;
472 
473 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info));
474 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info));
475 
476 
477 static inline void
478 pkt_info_zero(if_pkt_info_t pi)
479 {
480 	if_pkt_info_pad_t pi_pad;
481 
482 	pi_pad = (if_pkt_info_pad_t)pi;
483 	pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0;
484 	pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0;
485 #ifndef __LP64__
486 	pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0;
487 	pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0;
488 #endif
489 }
490 
491 static device_method_t iflib_pseudo_methods[] = {
492 	DEVMETHOD(device_attach, noop_attach),
493 	DEVMETHOD(device_detach, iflib_pseudo_detach),
494 	DEVMETHOD_END
495 };
496 
497 driver_t iflib_pseudodriver = {
498 	"iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx),
499 };
500 
501 static inline void
502 rxd_info_zero(if_rxd_info_t ri)
503 {
504 	if_rxd_info_pad_t ri_pad;
505 	int i;
506 
507 	ri_pad = (if_rxd_info_pad_t)ri;
508 	for (i = 0; i < RXD_LOOP_BOUND; i += 4) {
509 		ri_pad->rxd_val[i] = 0;
510 		ri_pad->rxd_val[i+1] = 0;
511 		ri_pad->rxd_val[i+2] = 0;
512 		ri_pad->rxd_val[i+3] = 0;
513 	}
514 #ifdef __LP64__
515 	ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0;
516 #endif
517 }
518 
519 /*
520  * Only allow a single packet to take up most 1/nth of the tx ring
521  */
522 #define MAX_SINGLE_PACKET_FRACTION 12
523 #define IF_BAD_DMA (bus_addr_t)-1
524 
525 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
526 
527 #define CTX_LOCK_INIT(_sc)  sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
528 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
529 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
530 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
531 
532 #define STATE_LOCK_INIT(_sc, _name)  mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
533 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
534 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
535 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
536 
537 #define CALLOUT_LOCK(txq)	mtx_lock(&txq->ift_mtx)
538 #define CALLOUT_UNLOCK(txq) 	mtx_unlock(&txq->ift_mtx)
539 
540 void
541 iflib_set_detach(if_ctx_t ctx)
542 {
543 	STATE_LOCK(ctx);
544 	ctx->ifc_flags |= IFC_IN_DETACH;
545 	STATE_UNLOCK(ctx);
546 }
547 
548 /* Our boot-time initialization hook */
549 static int	iflib_module_event_handler(module_t, int, void *);
550 
551 static moduledata_t iflib_moduledata = {
552 	"iflib",
553 	iflib_module_event_handler,
554 	NULL
555 };
556 
557 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
558 MODULE_VERSION(iflib, 1);
559 
560 MODULE_DEPEND(iflib, pci, 1, 1, 1);
561 MODULE_DEPEND(iflib, ether, 1, 1, 1);
562 
563 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
564 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
565 
566 #ifndef IFLIB_DEBUG_COUNTERS
567 #ifdef INVARIANTS
568 #define IFLIB_DEBUG_COUNTERS 1
569 #else
570 #define IFLIB_DEBUG_COUNTERS 0
571 #endif /* !INVARIANTS */
572 #endif
573 
574 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
575     "iflib driver parameters");
576 
577 /*
578  * XXX need to ensure that this can't accidentally cause the head to be moved backwards
579  */
580 static int iflib_min_tx_latency = 0;
581 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
582 		   &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput");
583 static int iflib_no_tx_batch = 0;
584 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
585 		   &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput");
586 
587 
588 #if IFLIB_DEBUG_COUNTERS
589 
590 static int iflib_tx_seen;
591 static int iflib_tx_sent;
592 static int iflib_tx_encap;
593 static int iflib_rx_allocs;
594 static int iflib_fl_refills;
595 static int iflib_fl_refills_large;
596 static int iflib_tx_frees;
597 
598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD,
599 		   &iflib_tx_seen, 0, "# TX mbufs seen");
600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD,
601 		   &iflib_tx_sent, 0, "# TX mbufs sent");
602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD,
603 		   &iflib_tx_encap, 0, "# TX mbufs encapped");
604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD,
605 		   &iflib_tx_frees, 0, "# TX frees");
606 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD,
607 		   &iflib_rx_allocs, 0, "# RX allocations");
608 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD,
609 		   &iflib_fl_refills, 0, "# refills");
610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
611 		   &iflib_fl_refills_large, 0, "# large refills");
612 
613 
614 static int iflib_txq_drain_flushing;
615 static int iflib_txq_drain_oactive;
616 static int iflib_txq_drain_notready;
617 
618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
619 		   &iflib_txq_drain_flushing, 0, "# drain flushes");
620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
621 		   &iflib_txq_drain_oactive, 0, "# drain oactives");
622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
623 		   &iflib_txq_drain_notready, 0, "# drain notready");
624 
625 
626 static int iflib_encap_load_mbuf_fail;
627 static int iflib_encap_pad_mbuf_fail;
628 static int iflib_encap_txq_avail_fail;
629 static int iflib_encap_txd_encap_fail;
630 
631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
632 		   &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
634 		   &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
636 		   &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
638 		   &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
639 
640 static int iflib_task_fn_rxs;
641 static int iflib_rx_intr_enables;
642 static int iflib_fast_intrs;
643 static int iflib_rx_unavail;
644 static int iflib_rx_ctx_inactive;
645 static int iflib_rx_if_input;
646 static int iflib_rxd_flush;
647 
648 static int iflib_verbose_debug;
649 
650 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD,
651 		   &iflib_task_fn_rxs, 0, "# task_fn_rx calls");
652 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
653 		   &iflib_rx_intr_enables, 0, "# RX intr enables");
654 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD,
655 		   &iflib_fast_intrs, 0, "# fast_intr calls");
656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD,
657 		   &iflib_rx_unavail, 0, "# times rxeof called with no available data");
658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
659 		   &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD,
661 		   &iflib_rx_if_input, 0, "# times rxeof called if_input");
662 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD,
663 	         &iflib_rxd_flush, 0, "# times rxd_flush called");
664 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
665 		   &iflib_verbose_debug, 0, "enable verbose debugging");
666 
667 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
668 static void
669 iflib_debug_reset(void)
670 {
671 	iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
672 		iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
673 		iflib_txq_drain_flushing = iflib_txq_drain_oactive =
674 		iflib_txq_drain_notready =
675 		iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
676 		iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
677 		iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
678 		iflib_rx_unavail =
679 		iflib_rx_ctx_inactive = iflib_rx_if_input =
680 		iflib_rxd_flush = 0;
681 }
682 
683 #else
684 #define DBG_COUNTER_INC(name)
685 static void iflib_debug_reset(void) {}
686 #endif
687 
688 #define IFLIB_DEBUG 0
689 
690 static void iflib_tx_structures_free(if_ctx_t ctx);
691 static void iflib_rx_structures_free(if_ctx_t ctx);
692 static int iflib_queues_alloc(if_ctx_t ctx);
693 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
694 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
695 static int iflib_qset_structures_setup(if_ctx_t ctx);
696 static int iflib_msix_init(if_ctx_t ctx);
697 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
698 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
699 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
700 #ifdef ALTQ
701 static void iflib_altq_if_start(if_t ifp);
702 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
703 #endif
704 static int iflib_register(if_ctx_t);
705 static void iflib_deregister(if_ctx_t);
706 static void iflib_unregister_vlan_handlers(if_ctx_t ctx);
707 static uint16_t iflib_get_mbuf_size_for(unsigned int size);
708 static void iflib_init_locked(if_ctx_t ctx);
709 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
710 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
711 static void iflib_ifmp_purge(iflib_txq_t txq);
712 static void _iflib_pre_assert(if_softc_ctx_t scctx);
713 static void iflib_if_init_locked(if_ctx_t ctx);
714 static void iflib_free_intr_mem(if_ctx_t ctx);
715 #ifndef __NO_STRICT_ALIGNMENT
716 static struct mbuf * iflib_fixup_rx(struct mbuf *m);
717 #endif
718 
719 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
720     SLIST_HEAD_INITIALIZER(cpu_offsets);
721 struct cpu_offset {
722 	SLIST_ENTRY(cpu_offset) entries;
723 	cpuset_t	set;
724 	unsigned int	refcount;
725 	uint16_t	offset;
726 };
727 static struct mtx cpu_offset_mtx;
728 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
729     MTX_DEF);
730 
731 DEBUGNET_DEFINE(iflib);
732 
733 static int
734 iflib_num_rx_descs(if_ctx_t ctx)
735 {
736 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
737 	if_shared_ctx_t sctx = ctx->ifc_sctx;
738 	uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
739 
740 	return scctx->isc_nrxd[first_rxq];
741 }
742 
743 static int
744 iflib_num_tx_descs(if_ctx_t ctx)
745 {
746 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
747 	if_shared_ctx_t sctx = ctx->ifc_sctx;
748 	uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
749 
750 	return scctx->isc_ntxd[first_txq];
751 }
752 
753 #ifdef DEV_NETMAP
754 #include <sys/selinfo.h>
755 #include <net/netmap.h>
756 #include <dev/netmap/netmap_kern.h>
757 
758 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
759 
760 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init);
761 
762 /*
763  * device-specific sysctl variables:
764  *
765  * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
766  *	During regular operations the CRC is stripped, but on some
767  *	hardware reception of frames not multiple of 64 is slower,
768  *	so using crcstrip=0 helps in benchmarks.
769  *
770  * iflib_rx_miss, iflib_rx_miss_bufs:
771  *	count packets that might be missed due to lost interrupts.
772  */
773 SYSCTL_DECL(_dev_netmap);
774 /*
775  * The xl driver by default strips CRCs and we do not override it.
776  */
777 
778 int iflib_crcstrip = 1;
779 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
780     CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
781 
782 int iflib_rx_miss, iflib_rx_miss_bufs;
783 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
784     CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
785 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
786     CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
787 
788 /*
789  * Register/unregister. We are already under netmap lock.
790  * Only called on the first register or the last unregister.
791  */
792 static int
793 iflib_netmap_register(struct netmap_adapter *na, int onoff)
794 {
795 	if_t ifp = na->ifp;
796 	if_ctx_t ctx = ifp->if_softc;
797 	int status;
798 
799 	CTX_LOCK(ctx);
800 	IFDI_INTR_DISABLE(ctx);
801 
802 	/* Tell the stack that the interface is no longer active */
803 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
804 
805 	if (!CTX_IS_VF(ctx))
806 		IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
807 
808 	iflib_stop(ctx);
809 
810 	/*
811 	 * Enable (or disable) netmap flags, and intercept (or restore)
812 	 * ifp->if_transmit. This is done once the device has been stopped
813 	 * to prevent race conditions.
814 	 */
815 	if (onoff) {
816 		nm_set_native_flags(na);
817 	} else {
818 		nm_clear_native_flags(na);
819 	}
820 
821 	iflib_init_locked(ctx);
822 	IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
823 	status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1;
824 	if (status)
825 		nm_clear_native_flags(na);
826 	CTX_UNLOCK(ctx);
827 	return (status);
828 }
829 
830 static int
831 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init)
832 {
833 	struct netmap_adapter *na = kring->na;
834 	u_int const lim = kring->nkr_num_slots - 1;
835 	u_int head = kring->rhead;
836 	struct netmap_ring *ring = kring->ring;
837 	bus_dmamap_t *map;
838 	struct if_rxd_update iru;
839 	if_ctx_t ctx = rxq->ifr_ctx;
840 	iflib_fl_t fl = &rxq->ifr_fl[0];
841 	uint32_t refill_pidx, nic_i;
842 #if IFLIB_DEBUG_COUNTERS
843 	int rf_count = 0;
844 #endif
845 
846 	if (nm_i == head && __predict_true(!init))
847 		return 0;
848 	iru_init(&iru, rxq, 0 /* flid */);
849 	map = fl->ifl_sds.ifsd_map;
850 	refill_pidx = netmap_idx_k2n(kring, nm_i);
851 	/*
852 	 * IMPORTANT: we must leave one free slot in the ring,
853 	 * so move head back by one unit
854 	 */
855 	head = nm_prev(head, lim);
856 	nic_i = UINT_MAX;
857 	DBG_COUNTER_INC(fl_refills);
858 	while (nm_i != head) {
859 #if IFLIB_DEBUG_COUNTERS
860 		if (++rf_count == 9)
861 			DBG_COUNTER_INC(fl_refills_large);
862 #endif
863 		for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) {
864 			struct netmap_slot *slot = &ring->slot[nm_i];
865 			void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]);
866 			uint32_t nic_i_dma = refill_pidx;
867 			nic_i = netmap_idx_k2n(kring, nm_i);
868 
869 			MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH);
870 
871 			if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
872 			        return netmap_ring_reinit(kring);
873 
874 			if (__predict_false(init)) {
875 				netmap_load_map(na, fl->ifl_buf_tag,
876 				    map[nic_i], addr);
877 			} else if (slot->flags & NS_BUF_CHANGED) {
878 				/* buffer has changed, reload map */
879 				netmap_reload_map(na, fl->ifl_buf_tag,
880 				    map[nic_i], addr);
881 			}
882 			slot->flags &= ~NS_BUF_CHANGED;
883 
884 			nm_i = nm_next(nm_i, lim);
885 			fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim);
886 			if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1)
887 				continue;
888 
889 			iru.iru_pidx = refill_pidx;
890 			iru.iru_count = tmp_pidx+1;
891 			ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
892 			refill_pidx = nic_i;
893 			for (int n = 0; n < iru.iru_count; n++) {
894 				bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma],
895 						BUS_DMASYNC_PREREAD);
896 				/* XXX - change this to not use the netmap func*/
897 				nic_i_dma = nm_next(nic_i_dma, lim);
898 			}
899 		}
900 	}
901 	kring->nr_hwcur = head;
902 
903 	bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
904 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
905 	if (__predict_true(nic_i != UINT_MAX)) {
906 		ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i);
907 		DBG_COUNTER_INC(rxd_flush);
908 	}
909 	return (0);
910 }
911 
912 /*
913  * Reconcile kernel and user view of the transmit ring.
914  *
915  * All information is in the kring.
916  * Userspace wants to send packets up to the one before kring->rhead,
917  * kernel knows kring->nr_hwcur is the first unsent packet.
918  *
919  * Here we push packets out (as many as possible), and possibly
920  * reclaim buffers from previously completed transmission.
921  *
922  * The caller (netmap) guarantees that there is only one instance
923  * running at any time. Any interference with other driver
924  * methods should be handled by the individual drivers.
925  */
926 static int
927 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
928 {
929 	struct netmap_adapter *na = kring->na;
930 	if_t ifp = na->ifp;
931 	struct netmap_ring *ring = kring->ring;
932 	u_int nm_i;	/* index into the netmap kring */
933 	u_int nic_i;	/* index into the NIC ring */
934 	u_int n;
935 	u_int const lim = kring->nkr_num_slots - 1;
936 	u_int const head = kring->rhead;
937 	struct if_pkt_info pi;
938 
939 	/*
940 	 * interrupts on every tx packet are expensive so request
941 	 * them every half ring, or where NS_REPORT is set
942 	 */
943 	u_int report_frequency = kring->nkr_num_slots >> 1;
944 	/* device-specific */
945 	if_ctx_t ctx = ifp->if_softc;
946 	iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
947 
948 	bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
949 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
950 
951 	/*
952 	 * First part: process new packets to send.
953 	 * nm_i is the current index in the netmap kring,
954 	 * nic_i is the corresponding index in the NIC ring.
955 	 *
956 	 * If we have packets to send (nm_i != head)
957 	 * iterate over the netmap ring, fetch length and update
958 	 * the corresponding slot in the NIC ring. Some drivers also
959 	 * need to update the buffer's physical address in the NIC slot
960 	 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
961 	 *
962 	 * The netmap_reload_map() calls is especially expensive,
963 	 * even when (as in this case) the tag is 0, so do only
964 	 * when the buffer has actually changed.
965 	 *
966 	 * If possible do not set the report/intr bit on all slots,
967 	 * but only a few times per ring or when NS_REPORT is set.
968 	 *
969 	 * Finally, on 10G and faster drivers, it might be useful
970 	 * to prefetch the next slot and txr entry.
971 	 */
972 
973 	nm_i = kring->nr_hwcur;
974 	if (nm_i != head) {	/* we have new packets to send */
975 		pkt_info_zero(&pi);
976 		pi.ipi_segs = txq->ift_segs;
977 		pi.ipi_qsidx = kring->ring_id;
978 		nic_i = netmap_idx_k2n(kring, nm_i);
979 
980 		__builtin_prefetch(&ring->slot[nm_i]);
981 		__builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
982 		__builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
983 
984 		for (n = 0; nm_i != head; n++) {
985 			struct netmap_slot *slot = &ring->slot[nm_i];
986 			u_int len = slot->len;
987 			uint64_t paddr;
988 			void *addr = PNMB(na, slot, &paddr);
989 			int flags = (slot->flags & NS_REPORT ||
990 				nic_i == 0 || nic_i == report_frequency) ?
991 				IPI_TX_INTR : 0;
992 
993 			/* device-specific */
994 			pi.ipi_len = len;
995 			pi.ipi_segs[0].ds_addr = paddr;
996 			pi.ipi_segs[0].ds_len = len;
997 			pi.ipi_nsegs = 1;
998 			pi.ipi_ndescs = 0;
999 			pi.ipi_pidx = nic_i;
1000 			pi.ipi_flags = flags;
1001 
1002 			/* Fill the slot in the NIC ring. */
1003 			ctx->isc_txd_encap(ctx->ifc_softc, &pi);
1004 			DBG_COUNTER_INC(tx_encap);
1005 
1006 			/* prefetch for next round */
1007 			__builtin_prefetch(&ring->slot[nm_i + 1]);
1008 			__builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
1009 			__builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
1010 
1011 			NM_CHECK_ADDR_LEN(na, addr, len);
1012 
1013 			if (slot->flags & NS_BUF_CHANGED) {
1014 				/* buffer has changed, reload map */
1015 				netmap_reload_map(na, txq->ift_buf_tag,
1016 				    txq->ift_sds.ifsd_map[nic_i], addr);
1017 			}
1018 			/* make sure changes to the buffer are synced */
1019 			bus_dmamap_sync(txq->ift_buf_tag,
1020 			    txq->ift_sds.ifsd_map[nic_i],
1021 			    BUS_DMASYNC_PREWRITE);
1022 
1023 			slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1024 			nm_i = nm_next(nm_i, lim);
1025 			nic_i = nm_next(nic_i, lim);
1026 		}
1027 		kring->nr_hwcur = nm_i;
1028 
1029 		/* synchronize the NIC ring */
1030 		bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1031 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1032 
1033 		/* (re)start the tx unit up to slot nic_i (excluded) */
1034 		ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1035 	}
1036 
1037 	/*
1038 	 * Second part: reclaim buffers for completed transmissions.
1039 	 *
1040 	 * If there are unclaimed buffers, attempt to reclaim them.
1041 	 * If none are reclaimed, and TX IRQs are not in use, do an initial
1042 	 * minimal delay, then trigger the tx handler which will spin in the
1043 	 * group task queue.
1044 	 */
1045 	if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1046 		if (iflib_tx_credits_update(ctx, txq)) {
1047 			/* some tx completed, increment avail */
1048 			nic_i = txq->ift_cidx_processed;
1049 			kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1050 		}
1051 	}
1052 	if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1053 		if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1054 			callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000,
1055 			    iflib_timer, txq, txq->ift_timer.c_cpu);
1056 	}
1057 	return (0);
1058 }
1059 
1060 /*
1061  * Reconcile kernel and user view of the receive ring.
1062  * Same as for the txsync, this routine must be efficient.
1063  * The caller guarantees a single invocations, but races against
1064  * the rest of the driver should be handled here.
1065  *
1066  * On call, kring->rhead is the first packet that userspace wants
1067  * to keep, and kring->rcur is the wakeup point.
1068  * The kernel has previously reported packets up to kring->rtail.
1069  *
1070  * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1071  * of whether or not we received an interrupt.
1072  */
1073 static int
1074 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1075 {
1076 	struct netmap_adapter *na = kring->na;
1077 	struct netmap_ring *ring = kring->ring;
1078 	if_t ifp = na->ifp;
1079 	uint32_t nm_i;	/* index into the netmap ring */
1080 	uint32_t nic_i;	/* index into the NIC ring */
1081 	u_int n;
1082 	u_int const lim = kring->nkr_num_slots - 1;
1083 	int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1084 
1085 	if_ctx_t ctx = ifp->if_softc;
1086 	iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1087 	iflib_fl_t fl = &rxq->ifr_fl[0];
1088 	struct if_rxd_info ri;
1089 
1090 	/*
1091 	 * netmap only uses free list 0, to avoid out of order consumption
1092 	 * of receive buffers
1093 	 */
1094 
1095 	bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1096 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1097 
1098 	/*
1099 	 * First part: import newly received packets.
1100 	 *
1101 	 * nm_i is the index of the next free slot in the netmap ring,
1102 	 * nic_i is the index of the next received packet in the NIC ring,
1103 	 * and they may differ in case if_init() has been called while
1104 	 * in netmap mode. For the receive ring we have
1105 	 *
1106 	 *	nic_i = rxr->next_check;
1107 	 *	nm_i = kring->nr_hwtail (previous)
1108 	 * and
1109 	 *	nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1110 	 *
1111 	 * rxr->next_check is set to 0 on a ring reinit
1112 	 */
1113 	if (netmap_no_pendintr || force_update) {
1114 		uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim);
1115 		int crclen = iflib_crcstrip ? 0 : 4;
1116 		int error, avail;
1117 
1118 		nic_i = fl->ifl_cidx;
1119 		nm_i = netmap_idx_n2k(kring, nic_i);
1120 		avail = ctx->isc_rxd_available(ctx->ifc_softc,
1121 		    rxq->ifr_id, nic_i, USHRT_MAX);
1122 		for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) {
1123 			rxd_info_zero(&ri);
1124 			ri.iri_frags = rxq->ifr_frags;
1125 			ri.iri_qsidx = kring->ring_id;
1126 			ri.iri_ifp = ctx->ifc_ifp;
1127 			ri.iri_cidx = nic_i;
1128 
1129 			error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1130 			ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen;
1131 			ring->slot[nm_i].flags = 0;
1132 			bus_dmamap_sync(fl->ifl_buf_tag,
1133 			    fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1134 			nm_i = nm_next(nm_i, lim);
1135 			nic_i = nm_next(nic_i, lim);
1136 		}
1137 		if (n) { /* update the state variables */
1138 			if (netmap_no_pendintr && !force_update) {
1139 				/* diagnostics */
1140 				iflib_rx_miss ++;
1141 				iflib_rx_miss_bufs += n;
1142 			}
1143 			fl->ifl_cidx = nic_i;
1144 			kring->nr_hwtail = nm_i;
1145 		}
1146 		kring->nr_kflags &= ~NKR_PENDINTR;
1147 	}
1148 	/*
1149 	 * Second part: skip past packets that userspace has released.
1150 	 * (kring->nr_hwcur to head excluded),
1151 	 * and make the buffers available for reception.
1152 	 * As usual nm_i is the index in the netmap ring,
1153 	 * nic_i is the index in the NIC ring, and
1154 	 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1155 	 */
1156 	nm_i = kring->nr_hwcur;
1157 
1158 	return (netmap_fl_refill(rxq, kring, nm_i, false));
1159 }
1160 
1161 static void
1162 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1163 {
1164 	if_ctx_t ctx = na->ifp->if_softc;
1165 
1166 	CTX_LOCK(ctx);
1167 	if (onoff) {
1168 		IFDI_INTR_ENABLE(ctx);
1169 	} else {
1170 		IFDI_INTR_DISABLE(ctx);
1171 	}
1172 	CTX_UNLOCK(ctx);
1173 }
1174 
1175 
1176 static int
1177 iflib_netmap_attach(if_ctx_t ctx)
1178 {
1179 	struct netmap_adapter na;
1180 
1181 	bzero(&na, sizeof(na));
1182 
1183 	na.ifp = ctx->ifc_ifp;
1184 	na.na_flags = NAF_BDG_MAYSLEEP;
1185 	MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1186 	MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1187 
1188 	na.num_tx_desc = iflib_num_tx_descs(ctx);
1189 	na.num_rx_desc = iflib_num_rx_descs(ctx);
1190 	na.nm_txsync = iflib_netmap_txsync;
1191 	na.nm_rxsync = iflib_netmap_rxsync;
1192 	na.nm_register = iflib_netmap_register;
1193 	na.nm_intr = iflib_netmap_intr;
1194 	na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1195 	na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1196 	return (netmap_attach(&na));
1197 }
1198 
1199 static int
1200 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1201 {
1202 	struct netmap_adapter *na = NA(ctx->ifc_ifp);
1203 	struct netmap_slot *slot;
1204 
1205 	slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1206 	if (slot == NULL)
1207 		return (0);
1208 	for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1209 
1210 		/*
1211 		 * In netmap mode, set the map for the packet buffer.
1212 		 * NOTE: Some drivers (not this one) also need to set
1213 		 * the physical buffer address in the NIC ring.
1214 		 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1215 		 * netmap slot index, si
1216 		 */
1217 		int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1218 		netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1219 		    NMB(na, slot + si));
1220 	}
1221 	return (1);
1222 }
1223 
1224 static int
1225 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1226 {
1227 	struct netmap_adapter *na = NA(ctx->ifc_ifp);
1228 	struct netmap_kring *kring;
1229 	struct netmap_slot *slot;
1230 	uint32_t nm_i;
1231 
1232 	slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1233 	if (slot == NULL)
1234 		return (0);
1235 	kring = na->rx_rings[rxq->ifr_id];
1236 	nm_i = netmap_idx_n2k(kring, 0);
1237 	netmap_fl_refill(rxq, kring, nm_i, true);
1238 	return (1);
1239 }
1240 
1241 static void
1242 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on)
1243 {
1244 	struct netmap_kring *kring;
1245 	uint16_t txqid;
1246 
1247 	txqid = txq->ift_id;
1248 	kring = netmap_kring_on(NA(ctx->ifc_ifp), txqid, NR_TX);
1249 	if (kring == NULL)
1250 		return;
1251 
1252 	if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) {
1253 		bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1254 		    BUS_DMASYNC_POSTREAD);
1255 		if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false))
1256 			netmap_tx_irq(ctx->ifc_ifp, txqid);
1257 		if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) {
1258 			if (hz < 2000)
1259 				*reset_on = 1;
1260 			else
1261 				*reset_on = hz / 1000;
1262 		}
1263 	}
1264 }
1265 
1266 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1267 
1268 #else
1269 #define iflib_netmap_txq_init(ctx, txq) (0)
1270 #define iflib_netmap_rxq_init(ctx, rxq) (0)
1271 #define iflib_netmap_detach(ifp)
1272 
1273 #define iflib_netmap_attach(ctx) (0)
1274 #define netmap_rx_irq(ifp, qid, budget) (0)
1275 #define netmap_tx_irq(ifp, qid) do {} while (0)
1276 #define iflib_netmap_timer_adjust(ctx, txq, reset_on)
1277 #endif
1278 
1279 #if defined(__i386__) || defined(__amd64__)
1280 static __inline void
1281 prefetch(void *x)
1282 {
1283 	__asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1284 }
1285 static __inline void
1286 prefetch2cachelines(void *x)
1287 {
1288 	__asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1289 #if (CACHE_LINE_SIZE < 128)
1290 	__asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long)))));
1291 #endif
1292 }
1293 #else
1294 #define prefetch(x)
1295 #define prefetch2cachelines(x)
1296 #endif
1297 
1298 static void
1299 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1300 {
1301 	iflib_fl_t fl;
1302 
1303 	fl = &rxq->ifr_fl[flid];
1304 	iru->iru_paddrs = fl->ifl_bus_addrs;
1305 	iru->iru_idxs = fl->ifl_rxd_idxs;
1306 	iru->iru_qsidx = rxq->ifr_id;
1307 	iru->iru_buf_size = fl->ifl_buf_size;
1308 	iru->iru_flidx = fl->ifl_id;
1309 }
1310 
1311 static void
1312 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1313 {
1314 	if (err)
1315 		return;
1316 	*(bus_addr_t *) arg = segs[0].ds_addr;
1317 }
1318 
1319 int
1320 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1321 {
1322 	int err;
1323 	device_t dev = ctx->ifc_dev;
1324 
1325 	err = bus_dma_tag_create(bus_get_dma_tag(dev),	/* parent */
1326 				align, 0,		/* alignment, bounds */
1327 				BUS_SPACE_MAXADDR,	/* lowaddr */
1328 				BUS_SPACE_MAXADDR,	/* highaddr */
1329 				NULL, NULL,		/* filter, filterarg */
1330 				size,			/* maxsize */
1331 				1,			/* nsegments */
1332 				size,			/* maxsegsize */
1333 				BUS_DMA_ALLOCNOW,	/* flags */
1334 				NULL,			/* lockfunc */
1335 				NULL,			/* lockarg */
1336 				&dma->idi_tag);
1337 	if (err) {
1338 		device_printf(dev,
1339 		    "%s: bus_dma_tag_create failed: %d\n",
1340 		    __func__, err);
1341 		goto fail_0;
1342 	}
1343 
1344 	err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr,
1345 	    BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1346 	if (err) {
1347 		device_printf(dev,
1348 		    "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1349 		    __func__, (uintmax_t)size, err);
1350 		goto fail_1;
1351 	}
1352 
1353 	dma->idi_paddr = IF_BAD_DMA;
1354 	err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1355 	    size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1356 	if (err || dma->idi_paddr == IF_BAD_DMA) {
1357 		device_printf(dev,
1358 		    "%s: bus_dmamap_load failed: %d\n",
1359 		    __func__, err);
1360 		goto fail_2;
1361 	}
1362 
1363 	dma->idi_size = size;
1364 	return (0);
1365 
1366 fail_2:
1367 	bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1368 fail_1:
1369 	bus_dma_tag_destroy(dma->idi_tag);
1370 fail_0:
1371 	dma->idi_tag = NULL;
1372 
1373 	return (err);
1374 }
1375 
1376 int
1377 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1378 {
1379 	if_shared_ctx_t sctx = ctx->ifc_sctx;
1380 
1381 	KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1382 
1383 	return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1384 }
1385 
1386 int
1387 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1388 {
1389 	int i, err;
1390 	iflib_dma_info_t *dmaiter;
1391 
1392 	dmaiter = dmalist;
1393 	for (i = 0; i < count; i++, dmaiter++) {
1394 		if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1395 			break;
1396 	}
1397 	if (err)
1398 		iflib_dma_free_multi(dmalist, i);
1399 	return (err);
1400 }
1401 
1402 void
1403 iflib_dma_free(iflib_dma_info_t dma)
1404 {
1405 	if (dma->idi_tag == NULL)
1406 		return;
1407 	if (dma->idi_paddr != IF_BAD_DMA) {
1408 		bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1409 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1410 		bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1411 		dma->idi_paddr = IF_BAD_DMA;
1412 	}
1413 	if (dma->idi_vaddr != NULL) {
1414 		bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1415 		dma->idi_vaddr = NULL;
1416 	}
1417 	bus_dma_tag_destroy(dma->idi_tag);
1418 	dma->idi_tag = NULL;
1419 }
1420 
1421 void
1422 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1423 {
1424 	int i;
1425 	iflib_dma_info_t *dmaiter = dmalist;
1426 
1427 	for (i = 0; i < count; i++, dmaiter++)
1428 		iflib_dma_free(*dmaiter);
1429 }
1430 
1431 static int
1432 iflib_fast_intr(void *arg)
1433 {
1434 	iflib_filter_info_t info = arg;
1435 	struct grouptask *gtask = info->ifi_task;
1436 	int result;
1437 
1438 	DBG_COUNTER_INC(fast_intrs);
1439 	if (info->ifi_filter != NULL) {
1440 		result = info->ifi_filter(info->ifi_filter_arg);
1441 		if ((result & FILTER_SCHEDULE_THREAD) == 0)
1442 			return (result);
1443 	}
1444 
1445 	GROUPTASK_ENQUEUE(gtask);
1446 	return (FILTER_HANDLED);
1447 }
1448 
1449 static int
1450 iflib_fast_intr_rxtx(void *arg)
1451 {
1452 	iflib_filter_info_t info = arg;
1453 	struct grouptask *gtask = info->ifi_task;
1454 	if_ctx_t ctx;
1455 	iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1456 	iflib_txq_t txq;
1457 	void *sc;
1458 	int i, cidx, result;
1459 	qidx_t txqid;
1460 	bool intr_enable, intr_legacy;
1461 
1462 	DBG_COUNTER_INC(fast_intrs);
1463 	if (info->ifi_filter != NULL) {
1464 		result = info->ifi_filter(info->ifi_filter_arg);
1465 		if ((result & FILTER_SCHEDULE_THREAD) == 0)
1466 			return (result);
1467 	}
1468 
1469 	ctx = rxq->ifr_ctx;
1470 	sc = ctx->ifc_softc;
1471 	intr_enable = false;
1472 	intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1473 	MPASS(rxq->ifr_ntxqirq);
1474 	for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1475 		txqid = rxq->ifr_txqid[i];
1476 		txq = &ctx->ifc_txqs[txqid];
1477 		bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1478 		    BUS_DMASYNC_POSTREAD);
1479 		if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1480 			if (intr_legacy)
1481 				intr_enable = true;
1482 			else
1483 				IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1484 			continue;
1485 		}
1486 		GROUPTASK_ENQUEUE(&txq->ift_task);
1487 	}
1488 	if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1489 		cidx = rxq->ifr_cq_cidx;
1490 	else
1491 		cidx = rxq->ifr_fl[0].ifl_cidx;
1492 	if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1493 		GROUPTASK_ENQUEUE(gtask);
1494 	else {
1495 		if (intr_legacy)
1496 			intr_enable = true;
1497 		else
1498 			IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1499 		DBG_COUNTER_INC(rx_intr_enables);
1500 	}
1501 	if (intr_enable)
1502 		IFDI_INTR_ENABLE(ctx);
1503 	return (FILTER_HANDLED);
1504 }
1505 
1506 
1507 static int
1508 iflib_fast_intr_ctx(void *arg)
1509 {
1510 	iflib_filter_info_t info = arg;
1511 	struct grouptask *gtask = info->ifi_task;
1512 	int result;
1513 
1514 	DBG_COUNTER_INC(fast_intrs);
1515 	if (info->ifi_filter != NULL) {
1516 		result = info->ifi_filter(info->ifi_filter_arg);
1517 		if ((result & FILTER_SCHEDULE_THREAD) == 0)
1518 			return (result);
1519 	}
1520 
1521 	GROUPTASK_ENQUEUE(gtask);
1522 	return (FILTER_HANDLED);
1523 }
1524 
1525 static int
1526 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1527 		 driver_filter_t filter, driver_intr_t handler, void *arg,
1528 		 const char *name)
1529 {
1530 	struct resource *res;
1531 	void *tag = NULL;
1532 	device_t dev = ctx->ifc_dev;
1533 	int flags, i, rc;
1534 
1535 	flags = RF_ACTIVE;
1536 	if (ctx->ifc_flags & IFC_LEGACY)
1537 		flags |= RF_SHAREABLE;
1538 	MPASS(rid < 512);
1539 	i = rid;
1540 	res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags);
1541 	if (res == NULL) {
1542 		device_printf(dev,
1543 		    "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1544 		return (ENOMEM);
1545 	}
1546 	irq->ii_res = res;
1547 	KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1548 	rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1549 						filter, handler, arg, &tag);
1550 	if (rc != 0) {
1551 		device_printf(dev,
1552 		    "failed to setup interrupt for rid %d, name %s: %d\n",
1553 					  rid, name ? name : "unknown", rc);
1554 		return (rc);
1555 	} else if (name)
1556 		bus_describe_intr(dev, res, tag, "%s", name);
1557 
1558 	irq->ii_tag = tag;
1559 	return (0);
1560 }
1561 
1562 /*********************************************************************
1563  *
1564  *  Allocate DMA resources for TX buffers as well as memory for the TX
1565  *  mbuf map.  TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1566  *  iflib_sw_tx_desc_array structure, storing all the information that
1567  *  is needed to transmit a packet on the wire.  This is called only
1568  *  once at attach, setup is done every reset.
1569  *
1570  **********************************************************************/
1571 static int
1572 iflib_txsd_alloc(iflib_txq_t txq)
1573 {
1574 	if_ctx_t ctx = txq->ift_ctx;
1575 	if_shared_ctx_t sctx = ctx->ifc_sctx;
1576 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1577 	device_t dev = ctx->ifc_dev;
1578 	bus_size_t tsomaxsize;
1579 	int err, nsegments, ntsosegments;
1580 	bool tso;
1581 
1582 	nsegments = scctx->isc_tx_nsegments;
1583 	ntsosegments = scctx->isc_tx_tso_segments_max;
1584 	tsomaxsize = scctx->isc_tx_tso_size_max;
1585 	if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1586 		tsomaxsize += sizeof(struct ether_vlan_header);
1587 	MPASS(scctx->isc_ntxd[0] > 0);
1588 	MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1589 	MPASS(nsegments > 0);
1590 	if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1591 		MPASS(ntsosegments > 0);
1592 		MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1593 	}
1594 
1595 	/*
1596 	 * Set up DMA tags for TX buffers.
1597 	 */
1598 	if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1599 			       1, 0,			/* alignment, bounds */
1600 			       BUS_SPACE_MAXADDR,	/* lowaddr */
1601 			       BUS_SPACE_MAXADDR,	/* highaddr */
1602 			       NULL, NULL,		/* filter, filterarg */
1603 			       sctx->isc_tx_maxsize,		/* maxsize */
1604 			       nsegments,	/* nsegments */
1605 			       sctx->isc_tx_maxsegsize,	/* maxsegsize */
1606 			       0,			/* flags */
1607 			       NULL,			/* lockfunc */
1608 			       NULL,			/* lockfuncarg */
1609 			       &txq->ift_buf_tag))) {
1610 		device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err);
1611 		device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1612 		    (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1613 		goto fail;
1614 	}
1615 	tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1616 	if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1617 			       1, 0,			/* alignment, bounds */
1618 			       BUS_SPACE_MAXADDR,	/* lowaddr */
1619 			       BUS_SPACE_MAXADDR,	/* highaddr */
1620 			       NULL, NULL,		/* filter, filterarg */
1621 			       tsomaxsize,		/* maxsize */
1622 			       ntsosegments,	/* nsegments */
1623 			       sctx->isc_tso_maxsegsize,/* maxsegsize */
1624 			       0,			/* flags */
1625 			       NULL,			/* lockfunc */
1626 			       NULL,			/* lockfuncarg */
1627 			       &txq->ift_tso_buf_tag))) {
1628 		device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1629 		    err);
1630 		goto fail;
1631 	}
1632 
1633 	/* Allocate memory for the TX mbuf map. */
1634 	if (!(txq->ift_sds.ifsd_m =
1635 	    (struct mbuf **) malloc(sizeof(struct mbuf *) *
1636 	    scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1637 		device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1638 		err = ENOMEM;
1639 		goto fail;
1640 	}
1641 
1642 	/*
1643 	 * Create the DMA maps for TX buffers.
1644 	 */
1645 	if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1646 	    sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1647 	    M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1648 		device_printf(dev,
1649 		    "Unable to allocate TX buffer DMA map memory\n");
1650 		err = ENOMEM;
1651 		goto fail;
1652 	}
1653 	if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1654 	    sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1655 	    M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1656 		device_printf(dev,
1657 		    "Unable to allocate TSO TX buffer map memory\n");
1658 		err = ENOMEM;
1659 		goto fail;
1660 	}
1661 	for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1662 		err = bus_dmamap_create(txq->ift_buf_tag, 0,
1663 		    &txq->ift_sds.ifsd_map[i]);
1664 		if (err != 0) {
1665 			device_printf(dev, "Unable to create TX DMA map\n");
1666 			goto fail;
1667 		}
1668 		if (!tso)
1669 			continue;
1670 		err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1671 		    &txq->ift_sds.ifsd_tso_map[i]);
1672 		if (err != 0) {
1673 			device_printf(dev, "Unable to create TSO TX DMA map\n");
1674 			goto fail;
1675 		}
1676 	}
1677 	return (0);
1678 fail:
1679 	/* We free all, it handles case where we are in the middle */
1680 	iflib_tx_structures_free(ctx);
1681 	return (err);
1682 }
1683 
1684 static void
1685 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1686 {
1687 	bus_dmamap_t map;
1688 
1689 	if (txq->ift_sds.ifsd_map != NULL) {
1690 		map = txq->ift_sds.ifsd_map[i];
1691 		bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1692 		bus_dmamap_unload(txq->ift_buf_tag, map);
1693 		bus_dmamap_destroy(txq->ift_buf_tag, map);
1694 		txq->ift_sds.ifsd_map[i] = NULL;
1695 	}
1696 
1697 	if (txq->ift_sds.ifsd_tso_map != NULL) {
1698 		map = txq->ift_sds.ifsd_tso_map[i];
1699 		bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1700 		    BUS_DMASYNC_POSTWRITE);
1701 		bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1702 		bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1703 		txq->ift_sds.ifsd_tso_map[i] = NULL;
1704 	}
1705 }
1706 
1707 static void
1708 iflib_txq_destroy(iflib_txq_t txq)
1709 {
1710 	if_ctx_t ctx = txq->ift_ctx;
1711 
1712 	for (int i = 0; i < txq->ift_size; i++)
1713 		iflib_txsd_destroy(ctx, txq, i);
1714 
1715 	if (txq->ift_br != NULL) {
1716 		ifmp_ring_free(txq->ift_br);
1717 		txq->ift_br = NULL;
1718 	}
1719 
1720 	mtx_destroy(&txq->ift_mtx);
1721 
1722 	if (txq->ift_sds.ifsd_map != NULL) {
1723 		free(txq->ift_sds.ifsd_map, M_IFLIB);
1724 		txq->ift_sds.ifsd_map = NULL;
1725 	}
1726 	if (txq->ift_sds.ifsd_tso_map != NULL) {
1727 		free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1728 		txq->ift_sds.ifsd_tso_map = NULL;
1729 	}
1730 	if (txq->ift_sds.ifsd_m != NULL) {
1731 		free(txq->ift_sds.ifsd_m, M_IFLIB);
1732 		txq->ift_sds.ifsd_m = NULL;
1733 	}
1734 	if (txq->ift_buf_tag != NULL) {
1735 		bus_dma_tag_destroy(txq->ift_buf_tag);
1736 		txq->ift_buf_tag = NULL;
1737 	}
1738 	if (txq->ift_tso_buf_tag != NULL) {
1739 		bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1740 		txq->ift_tso_buf_tag = NULL;
1741 	}
1742 	if (txq->ift_ifdi != NULL) {
1743 		free(txq->ift_ifdi, M_IFLIB);
1744 	}
1745 }
1746 
1747 static void
1748 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1749 {
1750 	struct mbuf **mp;
1751 
1752 	mp = &txq->ift_sds.ifsd_m[i];
1753 	if (*mp == NULL)
1754 		return;
1755 
1756 	if (txq->ift_sds.ifsd_map != NULL) {
1757 		bus_dmamap_sync(txq->ift_buf_tag,
1758 		    txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1759 		bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1760 	}
1761 	if (txq->ift_sds.ifsd_tso_map != NULL) {
1762 		bus_dmamap_sync(txq->ift_tso_buf_tag,
1763 		    txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1764 		bus_dmamap_unload(txq->ift_tso_buf_tag,
1765 		    txq->ift_sds.ifsd_tso_map[i]);
1766 	}
1767 	m_free(*mp);
1768 	DBG_COUNTER_INC(tx_frees);
1769 	*mp = NULL;
1770 }
1771 
1772 static int
1773 iflib_txq_setup(iflib_txq_t txq)
1774 {
1775 	if_ctx_t ctx = txq->ift_ctx;
1776 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1777 	if_shared_ctx_t sctx = ctx->ifc_sctx;
1778 	iflib_dma_info_t di;
1779 	int i;
1780 
1781 	/* Set number of descriptors available */
1782 	txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1783 	/* XXX make configurable */
1784 	txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1785 
1786 	/* Reset indices */
1787 	txq->ift_cidx_processed = 0;
1788 	txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1789 	txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1790 
1791 	for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1792 		bzero((void *)di->idi_vaddr, di->idi_size);
1793 
1794 	IFDI_TXQ_SETUP(ctx, txq->ift_id);
1795 	for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1796 		bus_dmamap_sync(di->idi_tag, di->idi_map,
1797 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1798 	return (0);
1799 }
1800 
1801 /*********************************************************************
1802  *
1803  *  Allocate DMA resources for RX buffers as well as memory for the RX
1804  *  mbuf map, direct RX cluster pointer map and RX cluster bus address
1805  *  map.  RX DMA map, RX mbuf map, direct RX cluster pointer map and
1806  *  RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1807  *  Since we use use one entry in iflib_sw_rx_desc_array per received
1808  *  packet, the maximum number of entries we'll need is equal to the
1809  *  number of hardware receive descriptors that we've allocated.
1810  *
1811  **********************************************************************/
1812 static int
1813 iflib_rxsd_alloc(iflib_rxq_t rxq)
1814 {
1815 	if_ctx_t ctx = rxq->ifr_ctx;
1816 	if_shared_ctx_t sctx = ctx->ifc_sctx;
1817 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1818 	device_t dev = ctx->ifc_dev;
1819 	iflib_fl_t fl;
1820 	int			err;
1821 
1822 	MPASS(scctx->isc_nrxd[0] > 0);
1823 	MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1824 
1825 	fl = rxq->ifr_fl;
1826 	for (int i = 0; i <  rxq->ifr_nfl; i++, fl++) {
1827 		fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1828 		/* Set up DMA tag for RX buffers. */
1829 		err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1830 					 1, 0,			/* alignment, bounds */
1831 					 BUS_SPACE_MAXADDR,	/* lowaddr */
1832 					 BUS_SPACE_MAXADDR,	/* highaddr */
1833 					 NULL, NULL,		/* filter, filterarg */
1834 					 sctx->isc_rx_maxsize,	/* maxsize */
1835 					 sctx->isc_rx_nsegments,	/* nsegments */
1836 					 sctx->isc_rx_maxsegsize,	/* maxsegsize */
1837 					 0,			/* flags */
1838 					 NULL,			/* lockfunc */
1839 					 NULL,			/* lockarg */
1840 					 &fl->ifl_buf_tag);
1841 		if (err) {
1842 			device_printf(dev,
1843 			    "Unable to allocate RX DMA tag: %d\n", err);
1844 			goto fail;
1845 		}
1846 
1847 		/* Allocate memory for the RX mbuf map. */
1848 		if (!(fl->ifl_sds.ifsd_m =
1849 		      (struct mbuf **) malloc(sizeof(struct mbuf *) *
1850 					      scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1851 			device_printf(dev,
1852 			    "Unable to allocate RX mbuf map memory\n");
1853 			err = ENOMEM;
1854 			goto fail;
1855 		}
1856 
1857 		/* Allocate memory for the direct RX cluster pointer map. */
1858 		if (!(fl->ifl_sds.ifsd_cl =
1859 		      (caddr_t *) malloc(sizeof(caddr_t) *
1860 					      scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1861 			device_printf(dev,
1862 			    "Unable to allocate RX cluster map memory\n");
1863 			err = ENOMEM;
1864 			goto fail;
1865 		}
1866 
1867 		/* Allocate memory for the RX cluster bus address map. */
1868 		if (!(fl->ifl_sds.ifsd_ba =
1869 		      (bus_addr_t *) malloc(sizeof(bus_addr_t) *
1870 					      scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1871 			device_printf(dev,
1872 			    "Unable to allocate RX bus address map memory\n");
1873 			err = ENOMEM;
1874 			goto fail;
1875 		}
1876 
1877 		/*
1878 		 * Create the DMA maps for RX buffers.
1879 		 */
1880 		if (!(fl->ifl_sds.ifsd_map =
1881 		      (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1882 			device_printf(dev,
1883 			    "Unable to allocate RX buffer DMA map memory\n");
1884 			err = ENOMEM;
1885 			goto fail;
1886 		}
1887 		for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
1888 			err = bus_dmamap_create(fl->ifl_buf_tag, 0,
1889 			    &fl->ifl_sds.ifsd_map[i]);
1890 			if (err != 0) {
1891 				device_printf(dev, "Unable to create RX buffer DMA map\n");
1892 				goto fail;
1893 			}
1894 		}
1895 	}
1896 	return (0);
1897 
1898 fail:
1899 	iflib_rx_structures_free(ctx);
1900 	return (err);
1901 }
1902 
1903 
1904 /*
1905  * Internal service routines
1906  */
1907 
1908 struct rxq_refill_cb_arg {
1909 	int               error;
1910 	bus_dma_segment_t seg;
1911 	int               nseg;
1912 };
1913 
1914 static void
1915 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1916 {
1917 	struct rxq_refill_cb_arg *cb_arg = arg;
1918 
1919 	cb_arg->error = error;
1920 	cb_arg->seg = segs[0];
1921 	cb_arg->nseg = nseg;
1922 }
1923 
1924 /**
1925  * iflib_fl_refill - refill an rxq free-buffer list
1926  * @ctx: the iflib context
1927  * @fl: the free list to refill
1928  * @count: the number of new buffers to allocate
1929  *
1930  * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
1931  * The caller must assure that @count does not exceed the queue's capacity.
1932  */
1933 static uint8_t
1934 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
1935 {
1936 	struct if_rxd_update iru;
1937 	struct rxq_refill_cb_arg cb_arg;
1938 	struct mbuf *m;
1939 	caddr_t cl, *sd_cl;
1940 	struct mbuf **sd_m;
1941 	bus_dmamap_t *sd_map;
1942 	bus_addr_t bus_addr, *sd_ba;
1943 	int err, frag_idx, i, idx, n, pidx;
1944 	qidx_t credits;
1945 
1946 	sd_m = fl->ifl_sds.ifsd_m;
1947 	sd_map = fl->ifl_sds.ifsd_map;
1948 	sd_cl = fl->ifl_sds.ifsd_cl;
1949 	sd_ba = fl->ifl_sds.ifsd_ba;
1950 	pidx = fl->ifl_pidx;
1951 	idx = pidx;
1952 	frag_idx = fl->ifl_fragidx;
1953 	credits = fl->ifl_credits;
1954 
1955 	i = 0;
1956 	n = count;
1957 	MPASS(n > 0);
1958 	MPASS(credits + n <= fl->ifl_size);
1959 
1960 	if (pidx < fl->ifl_cidx)
1961 		MPASS(pidx + n <= fl->ifl_cidx);
1962 	if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
1963 		MPASS(fl->ifl_gen == 0);
1964 	if (pidx > fl->ifl_cidx)
1965 		MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
1966 
1967 	DBG_COUNTER_INC(fl_refills);
1968 	if (n > 8)
1969 		DBG_COUNTER_INC(fl_refills_large);
1970 	iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
1971 	while (n-- > 0) {
1972 		/*
1973 		 * We allocate an uninitialized mbuf + cluster, mbuf is
1974 		 * initialized after rx.
1975 		 *
1976 		 * If the cluster is still set then we know a minimum sized
1977 		 * packet was received
1978 		 */
1979 		bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
1980 		    &frag_idx);
1981 		if (frag_idx < 0)
1982 			bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
1983 		MPASS(frag_idx >= 0);
1984 		if ((cl = sd_cl[frag_idx]) == NULL) {
1985 			cl = uma_zalloc(fl->ifl_zone, M_NOWAIT);
1986 			if (__predict_false(cl == NULL))
1987 				break;
1988 
1989 			cb_arg.error = 0;
1990 			MPASS(sd_map != NULL);
1991 			err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
1992 			    cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
1993 			    BUS_DMA_NOWAIT);
1994 			if (__predict_false(err != 0 || cb_arg.error)) {
1995 				uma_zfree(fl->ifl_zone, cl);
1996 				break;
1997 			}
1998 
1999 			sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
2000 			sd_cl[frag_idx] = cl;
2001 #if MEMORY_LOGGING
2002 			fl->ifl_cl_enqueued++;
2003 #endif
2004 		} else {
2005 			bus_addr = sd_ba[frag_idx];
2006 		}
2007 		bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2008 		    BUS_DMASYNC_PREREAD);
2009 
2010 		if (sd_m[frag_idx] == NULL) {
2011 			m = m_gethdr(M_NOWAIT, MT_NOINIT);
2012 			if (__predict_false(m == NULL))
2013 				break;
2014 			sd_m[frag_idx] = m;
2015 		}
2016 		bit_set(fl->ifl_rx_bitmap, frag_idx);
2017 #if MEMORY_LOGGING
2018 		fl->ifl_m_enqueued++;
2019 #endif
2020 
2021 		DBG_COUNTER_INC(rx_allocs);
2022 		fl->ifl_rxd_idxs[i] = frag_idx;
2023 		fl->ifl_bus_addrs[i] = bus_addr;
2024 		credits++;
2025 		i++;
2026 		MPASS(credits <= fl->ifl_size);
2027 		if (++idx == fl->ifl_size) {
2028 #ifdef INVARIANTS
2029 			fl->ifl_gen = 1;
2030 #endif
2031 			idx = 0;
2032 		}
2033 		if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2034 			iru.iru_pidx = pidx;
2035 			iru.iru_count = i;
2036 			ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2037 			fl->ifl_pidx = idx;
2038 			fl->ifl_credits = credits;
2039 			pidx = idx;
2040 			i = 0;
2041 		}
2042 	}
2043 
2044 	if (n < count - 1) {
2045 		if (i != 0) {
2046 			iru.iru_pidx = pidx;
2047 			iru.iru_count = i;
2048 			ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2049 			fl->ifl_pidx = idx;
2050 			fl->ifl_credits = credits;
2051 		}
2052 		DBG_COUNTER_INC(rxd_flush);
2053 		if (fl->ifl_pidx == 0)
2054 			pidx = fl->ifl_size - 1;
2055 		else
2056 			pidx = fl->ifl_pidx - 1;
2057 
2058 		bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2059 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2060 		ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id,
2061 		    fl->ifl_id, pidx);
2062 		if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) {
2063 			fl->ifl_fragidx = frag_idx + 1;
2064 			if (fl->ifl_fragidx == fl->ifl_size)
2065 				fl->ifl_fragidx = 0;
2066 		} else {
2067 			fl->ifl_fragidx = frag_idx;
2068 		}
2069 	}
2070 
2071 	return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY);
2072 }
2073 
2074 static inline uint8_t
2075 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl)
2076 {
2077 	/* we avoid allowing pidx to catch up with cidx as it confuses ixl */
2078 	int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2079 #ifdef INVARIANTS
2080 	int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2081 #endif
2082 
2083 	MPASS(fl->ifl_credits <= fl->ifl_size);
2084 	MPASS(reclaimable == delta);
2085 
2086 	if (reclaimable > 0)
2087 		return (iflib_fl_refill(ctx, fl, reclaimable));
2088 	return (0);
2089 }
2090 
2091 uint8_t
2092 iflib_in_detach(if_ctx_t ctx)
2093 {
2094 	bool in_detach;
2095 
2096 	STATE_LOCK(ctx);
2097 	in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2098 	STATE_UNLOCK(ctx);
2099 	return (in_detach);
2100 }
2101 
2102 static void
2103 iflib_fl_bufs_free(iflib_fl_t fl)
2104 {
2105 	iflib_dma_info_t idi = fl->ifl_ifdi;
2106 	bus_dmamap_t sd_map;
2107 	uint32_t i;
2108 
2109 	for (i = 0; i < fl->ifl_size; i++) {
2110 		struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2111 		caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2112 
2113 		if (*sd_cl != NULL) {
2114 			sd_map = fl->ifl_sds.ifsd_map[i];
2115 			bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2116 			    BUS_DMASYNC_POSTREAD);
2117 			bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2118 			uma_zfree(fl->ifl_zone, *sd_cl);
2119 			*sd_cl = NULL;
2120 			if (*sd_m != NULL) {
2121 				m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2122 				uma_zfree(zone_mbuf, *sd_m);
2123 				*sd_m = NULL;
2124 			}
2125 		} else {
2126 			MPASS(*sd_m == NULL);
2127 		}
2128 #if MEMORY_LOGGING
2129 		fl->ifl_m_dequeued++;
2130 		fl->ifl_cl_dequeued++;
2131 #endif
2132 	}
2133 #ifdef INVARIANTS
2134 	for (i = 0; i < fl->ifl_size; i++) {
2135 		MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2136 		MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2137 	}
2138 #endif
2139 	/*
2140 	 * Reset free list values
2141 	 */
2142 	fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2143 	bzero(idi->idi_vaddr, idi->idi_size);
2144 }
2145 
2146 /*********************************************************************
2147  *
2148  *  Initialize a free list and its buffers.
2149  *
2150  **********************************************************************/
2151 static int
2152 iflib_fl_setup(iflib_fl_t fl)
2153 {
2154 	iflib_rxq_t rxq = fl->ifl_rxq;
2155 	if_ctx_t ctx = rxq->ifr_ctx;
2156 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2157 	int qidx;
2158 
2159 	bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2160 	/*
2161 	** Free current RX buffer structs and their mbufs
2162 	*/
2163 	iflib_fl_bufs_free(fl);
2164 	/* Now replenish the mbufs */
2165 	MPASS(fl->ifl_credits == 0);
2166 	qidx = rxq->ifr_fl_offset + fl->ifl_id;
2167 	if (scctx->isc_rxd_buf_size[qidx] != 0)
2168 		fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx];
2169 	else
2170 		fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2171 	/*
2172 	 * ifl_buf_size may be a driver-supplied value, so pull it up
2173 	 * to the selected mbuf size.
2174 	 */
2175 	fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size);
2176 	if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2177 		ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2178 	fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2179 	fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2180 
2181 
2182 	/* avoid pre-allocating zillions of clusters to an idle card
2183 	 * potentially speeding up attach
2184 	 */
2185 	(void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size));
2186 	MPASS(min(128, fl->ifl_size) == fl->ifl_credits);
2187 	if (min(128, fl->ifl_size) != fl->ifl_credits)
2188 		return (ENOBUFS);
2189 	/*
2190 	 * handle failure
2191 	 */
2192 	MPASS(rxq != NULL);
2193 	MPASS(fl->ifl_ifdi != NULL);
2194 	bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2195 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2196 	return (0);
2197 }
2198 
2199 /*********************************************************************
2200  *
2201  *  Free receive ring data structures
2202  *
2203  **********************************************************************/
2204 static void
2205 iflib_rx_sds_free(iflib_rxq_t rxq)
2206 {
2207 	iflib_fl_t fl;
2208 	int i, j;
2209 
2210 	if (rxq->ifr_fl != NULL) {
2211 		for (i = 0; i < rxq->ifr_nfl; i++) {
2212 			fl = &rxq->ifr_fl[i];
2213 			if (fl->ifl_buf_tag != NULL) {
2214 				if (fl->ifl_sds.ifsd_map != NULL) {
2215 					for (j = 0; j < fl->ifl_size; j++) {
2216 						bus_dmamap_sync(
2217 						    fl->ifl_buf_tag,
2218 						    fl->ifl_sds.ifsd_map[j],
2219 						    BUS_DMASYNC_POSTREAD);
2220 						bus_dmamap_unload(
2221 						    fl->ifl_buf_tag,
2222 						    fl->ifl_sds.ifsd_map[j]);
2223 						bus_dmamap_destroy(
2224 						    fl->ifl_buf_tag,
2225 						    fl->ifl_sds.ifsd_map[j]);
2226 					}
2227 				}
2228 				bus_dma_tag_destroy(fl->ifl_buf_tag);
2229 				fl->ifl_buf_tag = NULL;
2230 			}
2231 			free(fl->ifl_sds.ifsd_m, M_IFLIB);
2232 			free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2233 			free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2234 			free(fl->ifl_sds.ifsd_map, M_IFLIB);
2235 			fl->ifl_sds.ifsd_m = NULL;
2236 			fl->ifl_sds.ifsd_cl = NULL;
2237 			fl->ifl_sds.ifsd_ba = NULL;
2238 			fl->ifl_sds.ifsd_map = NULL;
2239 		}
2240 		free(rxq->ifr_fl, M_IFLIB);
2241 		rxq->ifr_fl = NULL;
2242 		free(rxq->ifr_ifdi, M_IFLIB);
2243 		rxq->ifr_ifdi = NULL;
2244 		rxq->ifr_cq_cidx = 0;
2245 	}
2246 }
2247 
2248 /*
2249  * Timer routine
2250  */
2251 static void
2252 iflib_timer(void *arg)
2253 {
2254 	iflib_txq_t txq = arg;
2255 	if_ctx_t ctx = txq->ift_ctx;
2256 	if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2257 	uint64_t this_tick = ticks;
2258 	uint32_t reset_on = hz / 2;
2259 
2260 	if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2261 		return;
2262 
2263 	/*
2264 	** Check on the state of the TX queue(s), this
2265 	** can be done without the lock because its RO
2266 	** and the HUNG state will be static if set.
2267 	*/
2268 	if (this_tick - txq->ift_last_timer_tick >= hz / 2) {
2269 		txq->ift_last_timer_tick = this_tick;
2270 		IFDI_TIMER(ctx, txq->ift_id);
2271 		if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2272 		    ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2273 		     (sctx->isc_pause_frames == 0)))
2274 			goto hung;
2275 
2276 		if (txq->ift_qstatus != IFLIB_QUEUE_IDLE &&
2277 		    ifmp_ring_is_stalled(txq->ift_br)) {
2278 			KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down"));
2279 			txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2280 		}
2281 		txq->ift_cleaned_prev = txq->ift_cleaned;
2282 	}
2283 #ifdef DEV_NETMAP
2284 	if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
2285 		iflib_netmap_timer_adjust(ctx, txq, &reset_on);
2286 #endif
2287 	/* handle any laggards */
2288 	if (txq->ift_db_pending)
2289 		GROUPTASK_ENQUEUE(&txq->ift_task);
2290 
2291 	sctx->isc_pause_frames = 0;
2292 	if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2293 		callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
2294 	return;
2295 
2296  hung:
2297 	device_printf(ctx->ifc_dev,
2298 	    "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2299 	    txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2300 	STATE_LOCK(ctx);
2301 	if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2302 	ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET);
2303 	iflib_admin_intr_deferred(ctx);
2304 	STATE_UNLOCK(ctx);
2305 }
2306 
2307 static uint16_t
2308 iflib_get_mbuf_size_for(unsigned int size)
2309 {
2310 
2311 	if (size <= MCLBYTES)
2312 		return (MCLBYTES);
2313 	else
2314 		return (MJUMPAGESIZE);
2315 }
2316 
2317 static void
2318 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2319 {
2320 	if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2321 
2322 	/*
2323 	 * XXX don't set the max_frame_size to larger
2324 	 * than the hardware can handle
2325 	 */
2326 	ctx->ifc_rx_mbuf_sz =
2327 	    iflib_get_mbuf_size_for(sctx->isc_max_frame_size);
2328 }
2329 
2330 uint32_t
2331 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2332 {
2333 
2334 	return (ctx->ifc_rx_mbuf_sz);
2335 }
2336 
2337 static void
2338 iflib_init_locked(if_ctx_t ctx)
2339 {
2340 	if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2341 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2342 	if_t ifp = ctx->ifc_ifp;
2343 	iflib_fl_t fl;
2344 	iflib_txq_t txq;
2345 	iflib_rxq_t rxq;
2346 	int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2347 
2348 	if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2349 	IFDI_INTR_DISABLE(ctx);
2350 
2351 	tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2352 	tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2353 	/* Set hardware offload abilities */
2354 	if_clearhwassist(ifp);
2355 	if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2356 		if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2357 	if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2358 		if_sethwassistbits(ifp,  tx_ip6_csum_flags, 0);
2359 	if (if_getcapenable(ifp) & IFCAP_TSO4)
2360 		if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2361 	if (if_getcapenable(ifp) & IFCAP_TSO6)
2362 		if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2363 
2364 	for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) {
2365 		CALLOUT_LOCK(txq);
2366 		callout_stop(&txq->ift_timer);
2367 		CALLOUT_UNLOCK(txq);
2368 		iflib_netmap_txq_init(ctx, txq);
2369 	}
2370 
2371 	/*
2372 	 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2373 	 * that drivers can use the value when setting up the hardware receive
2374 	 * buffers.
2375 	 */
2376 	iflib_calc_rx_mbuf_sz(ctx);
2377 
2378 #ifdef INVARIANTS
2379 	i = if_getdrvflags(ifp);
2380 #endif
2381 	IFDI_INIT(ctx);
2382 	MPASS(if_getdrvflags(ifp) == i);
2383 	for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) {
2384 		if (iflib_netmap_rxq_init(ctx, rxq) > 0) {
2385 			/* This rxq is in netmap mode. Skip normal init. */
2386 			continue;
2387 		}
2388 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2389 			if (iflib_fl_setup(fl)) {
2390 				device_printf(ctx->ifc_dev,
2391 				    "setting up free list %d failed - "
2392 				    "check cluster settings\n", j);
2393 				goto done;
2394 			}
2395 		}
2396 	}
2397 done:
2398 	if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2399 	IFDI_INTR_ENABLE(ctx);
2400 	txq = ctx->ifc_txqs;
2401 	for (i = 0; i < sctx->isc_ntxqsets; i++, txq++)
2402 		callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq,
2403 			txq->ift_timer.c_cpu);
2404 }
2405 
2406 static int
2407 iflib_media_change(if_t ifp)
2408 {
2409 	if_ctx_t ctx = if_getsoftc(ifp);
2410 	int err;
2411 
2412 	CTX_LOCK(ctx);
2413 	if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2414 		iflib_init_locked(ctx);
2415 	CTX_UNLOCK(ctx);
2416 	return (err);
2417 }
2418 
2419 static void
2420 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2421 {
2422 	if_ctx_t ctx = if_getsoftc(ifp);
2423 
2424 	CTX_LOCK(ctx);
2425 	IFDI_UPDATE_ADMIN_STATUS(ctx);
2426 	IFDI_MEDIA_STATUS(ctx, ifmr);
2427 	CTX_UNLOCK(ctx);
2428 }
2429 
2430 void
2431 iflib_stop(if_ctx_t ctx)
2432 {
2433 	iflib_txq_t txq = ctx->ifc_txqs;
2434 	iflib_rxq_t rxq = ctx->ifc_rxqs;
2435 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2436 	if_shared_ctx_t sctx = ctx->ifc_sctx;
2437 	iflib_dma_info_t di;
2438 	iflib_fl_t fl;
2439 	int i, j;
2440 
2441 	/* Tell the stack that the interface is no longer active */
2442 	if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2443 
2444 	IFDI_INTR_DISABLE(ctx);
2445 	DELAY(1000);
2446 	IFDI_STOP(ctx);
2447 	DELAY(1000);
2448 
2449 	iflib_debug_reset();
2450 	/* Wait for current tx queue users to exit to disarm watchdog timer. */
2451 	for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2452 		/* make sure all transmitters have completed before proceeding XXX */
2453 
2454 		CALLOUT_LOCK(txq);
2455 		callout_stop(&txq->ift_timer);
2456 		CALLOUT_UNLOCK(txq);
2457 
2458 		/* clean any enqueued buffers */
2459 		iflib_ifmp_purge(txq);
2460 		/* Free any existing tx buffers. */
2461 		for (j = 0; j < txq->ift_size; j++) {
2462 			iflib_txsd_free(ctx, txq, j);
2463 		}
2464 		txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2465 		txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0;
2466 		txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2467 		txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2468 		txq->ift_pullups = 0;
2469 		ifmp_ring_reset_stats(txq->ift_br);
2470 		for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2471 			bzero((void *)di->idi_vaddr, di->idi_size);
2472 	}
2473 	for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2474 		/* make sure all transmitters have completed before proceeding XXX */
2475 
2476 		rxq->ifr_cq_cidx = 0;
2477 		for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2478 			bzero((void *)di->idi_vaddr, di->idi_size);
2479 		/* also resets the free lists pidx/cidx */
2480 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2481 			iflib_fl_bufs_free(fl);
2482 	}
2483 }
2484 
2485 static inline caddr_t
2486 calc_next_rxd(iflib_fl_t fl, int cidx)
2487 {
2488 	qidx_t size;
2489 	int nrxd;
2490 	caddr_t start, end, cur, next;
2491 
2492 	nrxd = fl->ifl_size;
2493 	size = fl->ifl_rxd_size;
2494 	start = fl->ifl_ifdi->idi_vaddr;
2495 
2496 	if (__predict_false(size == 0))
2497 		return (start);
2498 	cur = start + size*cidx;
2499 	end = start + size*nrxd;
2500 	next = CACHE_PTR_NEXT(cur);
2501 	return (next < end ? next : start);
2502 }
2503 
2504 static inline void
2505 prefetch_pkts(iflib_fl_t fl, int cidx)
2506 {
2507 	int nextptr;
2508 	int nrxd = fl->ifl_size;
2509 	caddr_t next_rxd;
2510 
2511 
2512 	nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1);
2513 	prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2514 	prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2515 	next_rxd = calc_next_rxd(fl, cidx);
2516 	prefetch(next_rxd);
2517 	prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]);
2518 	prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]);
2519 	prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]);
2520 	prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]);
2521 	prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]);
2522 	prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]);
2523 	prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]);
2524 	prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]);
2525 }
2526 
2527 static struct mbuf *
2528 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2529     int *pf_rv, if_rxd_info_t ri)
2530 {
2531 	bus_dmamap_t map;
2532 	iflib_fl_t fl;
2533 	caddr_t payload;
2534 	struct mbuf *m;
2535 	int flid, cidx, len, next;
2536 
2537 	map = NULL;
2538 	flid = irf->irf_flid;
2539 	cidx = irf->irf_idx;
2540 	fl = &rxq->ifr_fl[flid];
2541 	sd->ifsd_fl = fl;
2542 	m = fl->ifl_sds.ifsd_m[cidx];
2543 	sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2544 	fl->ifl_credits--;
2545 #if MEMORY_LOGGING
2546 	fl->ifl_m_dequeued++;
2547 #endif
2548 	if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2549 		prefetch_pkts(fl, cidx);
2550 	next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1);
2551 	prefetch(&fl->ifl_sds.ifsd_map[next]);
2552 	map = fl->ifl_sds.ifsd_map[cidx];
2553 
2554 	bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2555 
2556 	if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL &&
2557 	    irf->irf_len != 0) {
2558 		payload  = *sd->ifsd_cl;
2559 		payload +=  ri->iri_pad;
2560 		len = ri->iri_len - ri->iri_pad;
2561 		*pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp,
2562 		    len | PFIL_MEMPTR | PFIL_IN, NULL);
2563 		switch (*pf_rv) {
2564 		case PFIL_DROPPED:
2565 		case PFIL_CONSUMED:
2566 			/*
2567 			 * The filter ate it.  Everything is recycled.
2568 			 */
2569 			m = NULL;
2570 			unload = 0;
2571 			break;
2572 		case PFIL_REALLOCED:
2573 			/*
2574 			 * The filter copied it.  Everything is recycled.
2575 			 */
2576 			m = pfil_mem2mbuf(payload);
2577 			unload = 0;
2578 			break;
2579 		case PFIL_PASS:
2580 			/*
2581 			 * Filter said it was OK, so receive like
2582 			 * normal
2583 			 */
2584 			fl->ifl_sds.ifsd_m[cidx] = NULL;
2585 			break;
2586 		default:
2587 			MPASS(0);
2588 		}
2589 	} else {
2590 		fl->ifl_sds.ifsd_m[cidx] = NULL;
2591 		*pf_rv = PFIL_PASS;
2592 	}
2593 
2594 	if (unload && irf->irf_len != 0)
2595 		bus_dmamap_unload(fl->ifl_buf_tag, map);
2596 	fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1);
2597 	if (__predict_false(fl->ifl_cidx == 0))
2598 		fl->ifl_gen = 0;
2599 	bit_clear(fl->ifl_rx_bitmap, cidx);
2600 	return (m);
2601 }
2602 
2603 static struct mbuf *
2604 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2605 {
2606 	struct mbuf *m, *mh, *mt;
2607 	caddr_t cl;
2608 	int  *pf_rv_ptr, flags, i, padlen;
2609 	bool consumed;
2610 
2611 	i = 0;
2612 	mh = NULL;
2613 	consumed = false;
2614 	*pf_rv = PFIL_PASS;
2615 	pf_rv_ptr = pf_rv;
2616 	do {
2617 		m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2618 		    pf_rv_ptr, ri);
2619 
2620 		MPASS(*sd->ifsd_cl != NULL);
2621 
2622 		/*
2623 		 * Exclude zero-length frags & frags from
2624 		 * packets the filter has consumed or dropped
2625 		 */
2626 		if (ri->iri_frags[i].irf_len == 0 || consumed ||
2627 		    *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2628 			if (mh == NULL) {
2629 				/* everything saved here */
2630 				consumed = true;
2631 				pf_rv_ptr = NULL;
2632 				continue;
2633 			}
2634 			/* XXX we can save the cluster here, but not the mbuf */
2635 			m_init(m, M_NOWAIT, MT_DATA, 0);
2636 			m_free(m);
2637 			continue;
2638 		}
2639 		if (mh == NULL) {
2640 			flags = M_PKTHDR|M_EXT;
2641 			mh = mt = m;
2642 			padlen = ri->iri_pad;
2643 		} else {
2644 			flags = M_EXT;
2645 			mt->m_next = m;
2646 			mt = m;
2647 			/* assuming padding is only on the first fragment */
2648 			padlen = 0;
2649 		}
2650 		cl = *sd->ifsd_cl;
2651 		*sd->ifsd_cl = NULL;
2652 
2653 		/* Can these two be made one ? */
2654 		m_init(m, M_NOWAIT, MT_DATA, flags);
2655 		m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2656 		/*
2657 		 * These must follow m_init and m_cljset
2658 		 */
2659 		m->m_data += padlen;
2660 		ri->iri_len -= padlen;
2661 		m->m_len = ri->iri_frags[i].irf_len;
2662 	} while (++i < ri->iri_nfrags);
2663 
2664 	return (mh);
2665 }
2666 
2667 /*
2668  * Process one software descriptor
2669  */
2670 static struct mbuf *
2671 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2672 {
2673 	struct if_rxsd sd;
2674 	struct mbuf *m;
2675 	int pf_rv;
2676 
2677 	/* should I merge this back in now that the two paths are basically duplicated? */
2678 	if (ri->iri_nfrags == 1 &&
2679 	    ri->iri_frags[0].irf_len != 0 &&
2680 	    ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2681 		m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2682 		    &pf_rv, ri);
2683 		if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2684 			return (m);
2685 		if (pf_rv == PFIL_PASS) {
2686 			m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2687 #ifndef __NO_STRICT_ALIGNMENT
2688 			if (!IP_ALIGNED(m))
2689 				m->m_data += 2;
2690 #endif
2691 			memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2692 			m->m_len = ri->iri_frags[0].irf_len;
2693 		}
2694 	} else {
2695 		m = assemble_segments(rxq, ri, &sd, &pf_rv);
2696 		if (m == NULL)
2697 			return (NULL);
2698 		if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2699 			return (m);
2700 	}
2701 	m->m_pkthdr.len = ri->iri_len;
2702 	m->m_pkthdr.rcvif = ri->iri_ifp;
2703 	m->m_flags |= ri->iri_flags;
2704 	m->m_pkthdr.ether_vtag = ri->iri_vtag;
2705 	m->m_pkthdr.flowid = ri->iri_flowid;
2706 	M_HASHTYPE_SET(m, ri->iri_rsstype);
2707 	m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2708 	m->m_pkthdr.csum_data = ri->iri_csum_data;
2709 	return (m);
2710 }
2711 
2712 #if defined(INET6) || defined(INET)
2713 static void
2714 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6)
2715 {
2716 	CURVNET_SET(lc->ifp->if_vnet);
2717 #if defined(INET6)
2718 	*v6 = V_ip6_forwarding;
2719 #endif
2720 #if defined(INET)
2721 	*v4 = V_ipforwarding;
2722 #endif
2723 	CURVNET_RESTORE();
2724 }
2725 
2726 /*
2727  * Returns true if it's possible this packet could be LROed.
2728  * if it returns false, it is guaranteed that tcp_lro_rx()
2729  * would not return zero.
2730  */
2731 static bool
2732 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding)
2733 {
2734 	struct ether_header *eh;
2735 
2736 	eh = mtod(m, struct ether_header *);
2737 	switch (eh->ether_type) {
2738 #if defined(INET6)
2739 		case htons(ETHERTYPE_IPV6):
2740 			return (!v6_forwarding);
2741 #endif
2742 #if defined (INET)
2743 		case htons(ETHERTYPE_IP):
2744 			return (!v4_forwarding);
2745 #endif
2746 	}
2747 
2748 	return false;
2749 }
2750 #else
2751 static void
2752 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused)
2753 {
2754 }
2755 #endif
2756 
2757 static void
2758 _task_fn_rx_watchdog(void *context)
2759 {
2760 	iflib_rxq_t rxq = context;
2761 
2762 	GROUPTASK_ENQUEUE(&rxq->ifr_task);
2763 }
2764 
2765 static uint8_t
2766 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2767 {
2768 	if_t ifp;
2769 	if_ctx_t ctx = rxq->ifr_ctx;
2770 	if_shared_ctx_t sctx = ctx->ifc_sctx;
2771 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2772 	int avail, i;
2773 	qidx_t *cidxp;
2774 	struct if_rxd_info ri;
2775 	int err, budget_left, rx_bytes, rx_pkts;
2776 	iflib_fl_t fl;
2777 	int lro_enabled;
2778 	bool v4_forwarding, v6_forwarding, lro_possible;
2779 	uint8_t retval = 0;
2780 
2781 	/*
2782 	 * XXX early demux data packets so that if_input processing only handles
2783 	 * acks in interrupt context
2784 	 */
2785 	struct mbuf *m, *mh, *mt, *mf;
2786 
2787 	NET_EPOCH_ASSERT();
2788 
2789 	lro_possible = v4_forwarding = v6_forwarding = false;
2790 	ifp = ctx->ifc_ifp;
2791 	mh = mt = NULL;
2792 	MPASS(budget > 0);
2793 	rx_pkts	= rx_bytes = 0;
2794 	if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2795 		cidxp = &rxq->ifr_cq_cidx;
2796 	else
2797 		cidxp = &rxq->ifr_fl[0].ifl_cidx;
2798 	if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2799 		for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2800 			retval |= iflib_fl_refill_all(ctx, fl);
2801 		DBG_COUNTER_INC(rx_unavail);
2802 		return (retval);
2803 	}
2804 
2805 	/* pfil needs the vnet to be set */
2806 	CURVNET_SET_QUIET(ifp->if_vnet);
2807 	for (budget_left = budget; budget_left > 0 && avail > 0;) {
2808 		if (__predict_false(!CTX_ACTIVE(ctx))) {
2809 			DBG_COUNTER_INC(rx_ctx_inactive);
2810 			break;
2811 		}
2812 		/*
2813 		 * Reset client set fields to their default values
2814 		 */
2815 		rxd_info_zero(&ri);
2816 		ri.iri_qsidx = rxq->ifr_id;
2817 		ri.iri_cidx = *cidxp;
2818 		ri.iri_ifp = ifp;
2819 		ri.iri_frags = rxq->ifr_frags;
2820 		err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2821 
2822 		if (err)
2823 			goto err;
2824 		rx_pkts += 1;
2825 		rx_bytes += ri.iri_len;
2826 		if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2827 			*cidxp = ri.iri_cidx;
2828 			/* Update our consumer index */
2829 			/* XXX NB: shurd - check if this is still safe */
2830 			while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
2831 				rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2832 			/* was this only a completion queue message? */
2833 			if (__predict_false(ri.iri_nfrags == 0))
2834 				continue;
2835 		}
2836 		MPASS(ri.iri_nfrags != 0);
2837 		MPASS(ri.iri_len != 0);
2838 
2839 		/* will advance the cidx on the corresponding free lists */
2840 		m = iflib_rxd_pkt_get(rxq, &ri);
2841 		avail--;
2842 		budget_left--;
2843 		if (avail == 0 && budget_left)
2844 			avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2845 
2846 		if (__predict_false(m == NULL))
2847 			continue;
2848 
2849 		/* imm_pkt: -- cxgb */
2850 		if (mh == NULL)
2851 			mh = mt = m;
2852 		else {
2853 			mt->m_nextpkt = m;
2854 			mt = m;
2855 		}
2856 	}
2857 	CURVNET_RESTORE();
2858 	/* make sure that we can refill faster than drain */
2859 	for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2860 		retval |= iflib_fl_refill_all(ctx, fl);
2861 
2862 	lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2863 	if (lro_enabled)
2864 		iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding);
2865 	mt = mf = NULL;
2866 	while (mh != NULL) {
2867 		m = mh;
2868 		mh = mh->m_nextpkt;
2869 		m->m_nextpkt = NULL;
2870 #ifndef __NO_STRICT_ALIGNMENT
2871 		if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2872 			continue;
2873 #endif
2874 		rx_bytes += m->m_pkthdr.len;
2875 		rx_pkts++;
2876 #if defined(INET6) || defined(INET)
2877 		if (lro_enabled) {
2878 			if (!lro_possible) {
2879 				lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding);
2880 				if (lro_possible && mf != NULL) {
2881 					ifp->if_input(ifp, mf);
2882 					DBG_COUNTER_INC(rx_if_input);
2883 					mt = mf = NULL;
2884 				}
2885 			}
2886 			if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) ==
2887 			    (CSUM_L4_CALC|CSUM_L4_VALID)) {
2888 				if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0)
2889 					continue;
2890 			}
2891 		}
2892 #endif
2893 		if (lro_possible) {
2894 			ifp->if_input(ifp, m);
2895 			DBG_COUNTER_INC(rx_if_input);
2896 			continue;
2897 		}
2898 
2899 		if (mf == NULL)
2900 			mf = m;
2901 		if (mt != NULL)
2902 			mt->m_nextpkt = m;
2903 		mt = m;
2904 	}
2905 	if (mf != NULL) {
2906 		ifp->if_input(ifp, mf);
2907 		DBG_COUNTER_INC(rx_if_input);
2908 	}
2909 
2910 	if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
2911 	if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
2912 
2913 	/*
2914 	 * Flush any outstanding LRO work
2915 	 */
2916 #if defined(INET6) || defined(INET)
2917 	tcp_lro_flush_all(&rxq->ifr_lc);
2918 #endif
2919 	if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0)
2920 		retval |= IFLIB_RXEOF_MORE;
2921 	return (retval);
2922 err:
2923 	STATE_LOCK(ctx);
2924 	ctx->ifc_flags |= IFC_DO_RESET;
2925 	iflib_admin_intr_deferred(ctx);
2926 	STATE_UNLOCK(ctx);
2927 	return (0);
2928 }
2929 
2930 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1)
2931 static inline qidx_t
2932 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
2933 {
2934 	qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2935 	qidx_t minthresh = txq->ift_size / 8;
2936 	if (in_use > 4*minthresh)
2937 		return (notify_count);
2938 	if (in_use > 2*minthresh)
2939 		return (notify_count >> 1);
2940 	if (in_use > minthresh)
2941 		return (notify_count >> 3);
2942 	return (0);
2943 }
2944 
2945 static inline qidx_t
2946 txq_max_rs_deferred(iflib_txq_t txq)
2947 {
2948 	qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
2949 	qidx_t minthresh = txq->ift_size / 8;
2950 	if (txq->ift_in_use > 4*minthresh)
2951 		return (notify_count);
2952 	if (txq->ift_in_use > 2*minthresh)
2953 		return (notify_count >> 1);
2954 	if (txq->ift_in_use > minthresh)
2955 		return (notify_count >> 2);
2956 	return (2);
2957 }
2958 
2959 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
2960 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
2961 
2962 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
2963 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
2964 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
2965 
2966 /* forward compatibility for cxgb */
2967 #define FIRST_QSET(ctx) 0
2968 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
2969 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
2970 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
2971 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
2972 
2973 /* XXX we should be setting this to something other than zero */
2974 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh)
2975 #define	MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
2976     (ctx)->ifc_softc_ctx.isc_tx_nsegments)
2977 
2978 static inline bool
2979 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use)
2980 {
2981 	qidx_t dbval, max;
2982 	bool rang;
2983 
2984 	rang = false;
2985 	max = TXQ_MAX_DB_DEFERRED(txq, in_use);
2986 	if (ring || txq->ift_db_pending >= max) {
2987 		dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
2988 		bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
2989 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2990 		ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
2991 		txq->ift_db_pending = txq->ift_npending = 0;
2992 		rang = true;
2993 	}
2994 	return (rang);
2995 }
2996 
2997 #ifdef PKT_DEBUG
2998 static void
2999 print_pkt(if_pkt_info_t pi)
3000 {
3001 	printf("pi len:  %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
3002 	       pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
3003 	printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
3004 	       pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
3005 	printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
3006 	       pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
3007 }
3008 #endif
3009 
3010 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
3011 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
3012 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
3013 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
3014 
3015 static int
3016 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
3017 {
3018 	if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
3019 	struct ether_vlan_header *eh;
3020 	struct mbuf *m;
3021 
3022 	m = *mp;
3023 	if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
3024 	    M_WRITABLE(m) == 0) {
3025 		if ((m = m_dup(m, M_NOWAIT)) == NULL) {
3026 			return (ENOMEM);
3027 		} else {
3028 			m_freem(*mp);
3029 			DBG_COUNTER_INC(tx_frees);
3030 			*mp = m;
3031 		}
3032 	}
3033 
3034 	/*
3035 	 * Determine where frame payload starts.
3036 	 * Jump over vlan headers if already present,
3037 	 * helpful for QinQ too.
3038 	 */
3039 	if (__predict_false(m->m_len < sizeof(*eh))) {
3040 		txq->ift_pullups++;
3041 		if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3042 			return (ENOMEM);
3043 	}
3044 	eh = mtod(m, struct ether_vlan_header *);
3045 	if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3046 		pi->ipi_etype = ntohs(eh->evl_proto);
3047 		pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3048 	} else {
3049 		pi->ipi_etype = ntohs(eh->evl_encap_proto);
3050 		pi->ipi_ehdrlen = ETHER_HDR_LEN;
3051 	}
3052 
3053 	switch (pi->ipi_etype) {
3054 #ifdef INET
3055 	case ETHERTYPE_IP:
3056 	{
3057 		struct mbuf *n;
3058 		struct ip *ip = NULL;
3059 		struct tcphdr *th = NULL;
3060 		int minthlen;
3061 
3062 		minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th));
3063 		if (__predict_false(m->m_len < minthlen)) {
3064 			/*
3065 			 * if this code bloat is causing too much of a hit
3066 			 * move it to a separate function and mark it noinline
3067 			 */
3068 			if (m->m_len == pi->ipi_ehdrlen) {
3069 				n = m->m_next;
3070 				MPASS(n);
3071 				if (n->m_len >= sizeof(*ip))  {
3072 					ip = (struct ip *)n->m_data;
3073 					if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3074 						th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3075 				} else {
3076 					txq->ift_pullups++;
3077 					if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3078 						return (ENOMEM);
3079 					ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3080 				}
3081 			} else {
3082 				txq->ift_pullups++;
3083 				if (__predict_false((m = m_pullup(m, minthlen)) == NULL))
3084 					return (ENOMEM);
3085 				ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3086 				if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3087 					th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3088 			}
3089 		} else {
3090 			ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3091 			if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th))
3092 				th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
3093 		}
3094 		pi->ipi_ip_hlen = ip->ip_hl << 2;
3095 		pi->ipi_ipproto = ip->ip_p;
3096 		pi->ipi_flags |= IPI_TX_IPV4;
3097 
3098 		/* TCP checksum offload may require TCP header length */
3099 		if (IS_TX_OFFLOAD4(pi)) {
3100 			if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3101 				if (__predict_false(th == NULL)) {
3102 					txq->ift_pullups++;
3103 					if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL))
3104 						return (ENOMEM);
3105 					th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen);
3106 				}
3107 				pi->ipi_tcp_hflags = th->th_flags;
3108 				pi->ipi_tcp_hlen = th->th_off << 2;
3109 				pi->ipi_tcp_seq = th->th_seq;
3110 			}
3111 			if (IS_TSO4(pi)) {
3112 				if (__predict_false(ip->ip_p != IPPROTO_TCP))
3113 					return (ENXIO);
3114 				/*
3115 				 * TSO always requires hardware checksum offload.
3116 				 */
3117 				pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3118 				th->th_sum = in_pseudo(ip->ip_src.s_addr,
3119 						       ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3120 				pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3121 				if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3122 					ip->ip_sum = 0;
3123 					ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3124 				}
3125 			}
3126 		}
3127 		if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3128                        ip->ip_sum = 0;
3129 
3130 		break;
3131 	}
3132 #endif
3133 #ifdef INET6
3134 	case ETHERTYPE_IPV6:
3135 	{
3136 		struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3137 		struct tcphdr *th;
3138 		pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3139 
3140 		if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3141 			txq->ift_pullups++;
3142 			if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3143 				return (ENOMEM);
3144 		}
3145 		th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3146 
3147 		/* XXX-BZ this will go badly in case of ext hdrs. */
3148 		pi->ipi_ipproto = ip6->ip6_nxt;
3149 		pi->ipi_flags |= IPI_TX_IPV6;
3150 
3151 		/* TCP checksum offload may require TCP header length */
3152 		if (IS_TX_OFFLOAD6(pi)) {
3153 			if (pi->ipi_ipproto == IPPROTO_TCP) {
3154 				if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3155 					txq->ift_pullups++;
3156 					if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3157 						return (ENOMEM);
3158 				}
3159 				pi->ipi_tcp_hflags = th->th_flags;
3160 				pi->ipi_tcp_hlen = th->th_off << 2;
3161 				pi->ipi_tcp_seq = th->th_seq;
3162 			}
3163 			if (IS_TSO6(pi)) {
3164 				if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3165 					return (ENXIO);
3166 				/*
3167 				 * TSO always requires hardware checksum offload.
3168 				 */
3169 				pi->ipi_csum_flags |= CSUM_IP6_TCP;
3170 				th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3171 				pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3172 			}
3173 		}
3174 		break;
3175 	}
3176 #endif
3177 	default:
3178 		pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3179 		pi->ipi_ip_hlen = 0;
3180 		break;
3181 	}
3182 	*mp = m;
3183 
3184 	return (0);
3185 }
3186 
3187 /*
3188  * If dodgy hardware rejects the scatter gather chain we've handed it
3189  * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3190  * m_defrag'd mbufs
3191  */
3192 static __noinline struct mbuf *
3193 iflib_remove_mbuf(iflib_txq_t txq)
3194 {
3195 	int ntxd, pidx;
3196 	struct mbuf *m, **ifsd_m;
3197 
3198 	ifsd_m = txq->ift_sds.ifsd_m;
3199 	ntxd = txq->ift_size;
3200 	pidx = txq->ift_pidx & (ntxd - 1);
3201 	ifsd_m = txq->ift_sds.ifsd_m;
3202 	m = ifsd_m[pidx];
3203 	ifsd_m[pidx] = NULL;
3204 	bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3205 	if (txq->ift_sds.ifsd_tso_map != NULL)
3206 		bus_dmamap_unload(txq->ift_tso_buf_tag,
3207 		    txq->ift_sds.ifsd_tso_map[pidx]);
3208 #if MEMORY_LOGGING
3209 	txq->ift_dequeued++;
3210 #endif
3211 	return (m);
3212 }
3213 
3214 static inline caddr_t
3215 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid)
3216 {
3217 	qidx_t size;
3218 	int ntxd;
3219 	caddr_t start, end, cur, next;
3220 
3221 	ntxd = txq->ift_size;
3222 	size = txq->ift_txd_size[qid];
3223 	start = txq->ift_ifdi[qid].idi_vaddr;
3224 
3225 	if (__predict_false(size == 0))
3226 		return (start);
3227 	cur = start + size*cidx;
3228 	end = start + size*ntxd;
3229 	next = CACHE_PTR_NEXT(cur);
3230 	return (next < end ? next : start);
3231 }
3232 
3233 /*
3234  * Pad an mbuf to ensure a minimum ethernet frame size.
3235  * min_frame_size is the frame size (less CRC) to pad the mbuf to
3236  */
3237 static __noinline int
3238 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3239 {
3240 	/*
3241 	 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3242 	 * and ARP message is the smallest common payload I can think of
3243 	 */
3244 	static char pad[18];	/* just zeros */
3245 	int n;
3246 	struct mbuf *new_head;
3247 
3248 	if (!M_WRITABLE(*m_head)) {
3249 		new_head = m_dup(*m_head, M_NOWAIT);
3250 		if (new_head == NULL) {
3251 			m_freem(*m_head);
3252 			device_printf(dev, "cannot pad short frame, m_dup() failed");
3253 			DBG_COUNTER_INC(encap_pad_mbuf_fail);
3254 			DBG_COUNTER_INC(tx_frees);
3255 			return ENOMEM;
3256 		}
3257 		m_freem(*m_head);
3258 		*m_head = new_head;
3259 	}
3260 
3261 	for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3262 	     n > 0; n -= sizeof(pad))
3263 		if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3264 			break;
3265 
3266 	if (n > 0) {
3267 		m_freem(*m_head);
3268 		device_printf(dev, "cannot pad short frame\n");
3269 		DBG_COUNTER_INC(encap_pad_mbuf_fail);
3270 		DBG_COUNTER_INC(tx_frees);
3271 		return (ENOBUFS);
3272 	}
3273 
3274 	return 0;
3275 }
3276 
3277 static int
3278 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3279 {
3280 	if_ctx_t		ctx;
3281 	if_shared_ctx_t		sctx;
3282 	if_softc_ctx_t		scctx;
3283 	bus_dma_tag_t		buf_tag;
3284 	bus_dma_segment_t	*segs;
3285 	struct mbuf		*m_head, **ifsd_m;
3286 	void			*next_txd;
3287 	bus_dmamap_t		map;
3288 	struct if_pkt_info	pi;
3289 	int remap = 0;
3290 	int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd;
3291 
3292 	ctx = txq->ift_ctx;
3293 	sctx = ctx->ifc_sctx;
3294 	scctx = &ctx->ifc_softc_ctx;
3295 	segs = txq->ift_segs;
3296 	ntxd = txq->ift_size;
3297 	m_head = *m_headp;
3298 	map = NULL;
3299 
3300 	/*
3301 	 * If we're doing TSO the next descriptor to clean may be quite far ahead
3302 	 */
3303 	cidx = txq->ift_cidx;
3304 	pidx = txq->ift_pidx;
3305 	if (ctx->ifc_flags & IFC_PREFETCH) {
3306 		next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1);
3307 		if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) {
3308 			next_txd = calc_next_txd(txq, cidx, 0);
3309 			prefetch(next_txd);
3310 		}
3311 
3312 		/* prefetch the next cache line of mbuf pointers and flags */
3313 		prefetch(&txq->ift_sds.ifsd_m[next]);
3314 		prefetch(&txq->ift_sds.ifsd_map[next]);
3315 		next = (cidx + CACHE_LINE_SIZE) & (ntxd-1);
3316 	}
3317 	map = txq->ift_sds.ifsd_map[pidx];
3318 	ifsd_m = txq->ift_sds.ifsd_m;
3319 
3320 	if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3321 		buf_tag = txq->ift_tso_buf_tag;
3322 		max_segs = scctx->isc_tx_tso_segments_max;
3323 		map = txq->ift_sds.ifsd_tso_map[pidx];
3324 		MPASS(buf_tag != NULL);
3325 		MPASS(max_segs > 0);
3326 	} else {
3327 		buf_tag = txq->ift_buf_tag;
3328 		max_segs = scctx->isc_tx_nsegments;
3329 		map = txq->ift_sds.ifsd_map[pidx];
3330 	}
3331 	if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3332 	    __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3333 		err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3334 		if (err) {
3335 			DBG_COUNTER_INC(encap_txd_encap_fail);
3336 			return err;
3337 		}
3338 	}
3339 	m_head = *m_headp;
3340 
3341 	pkt_info_zero(&pi);
3342 	pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST));
3343 	pi.ipi_pidx = pidx;
3344 	pi.ipi_qsidx = txq->ift_id;
3345 	pi.ipi_len = m_head->m_pkthdr.len;
3346 	pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3347 	pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3348 
3349 	/* deliberate bitwise OR to make one condition */
3350 	if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3351 		if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3352 			DBG_COUNTER_INC(encap_txd_encap_fail);
3353 			return (err);
3354 		}
3355 		m_head = *m_headp;
3356 	}
3357 
3358 retry:
3359 	err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3360 	    BUS_DMA_NOWAIT);
3361 defrag:
3362 	if (__predict_false(err)) {
3363 		switch (err) {
3364 		case EFBIG:
3365 			/* try collapse once and defrag once */
3366 			if (remap == 0) {
3367 				m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3368 				/* try defrag if collapsing fails */
3369 				if (m_head == NULL)
3370 					remap++;
3371 			}
3372 			if (remap == 1) {
3373 				txq->ift_mbuf_defrag++;
3374 				m_head = m_defrag(*m_headp, M_NOWAIT);
3375 			}
3376 			/*
3377 			 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3378 			 * failed to map an mbuf that was run through m_defrag
3379 			 */
3380 			MPASS(remap <= 1);
3381 			if (__predict_false(m_head == NULL || remap > 1))
3382 				goto defrag_failed;
3383 			remap++;
3384 			*m_headp = m_head;
3385 			goto retry;
3386 			break;
3387 		case ENOMEM:
3388 			txq->ift_no_tx_dma_setup++;
3389 			break;
3390 		default:
3391 			txq->ift_no_tx_dma_setup++;
3392 			m_freem(*m_headp);
3393 			DBG_COUNTER_INC(tx_frees);
3394 			*m_headp = NULL;
3395 			break;
3396 		}
3397 		txq->ift_map_failed++;
3398 		DBG_COUNTER_INC(encap_load_mbuf_fail);
3399 		DBG_COUNTER_INC(encap_txd_encap_fail);
3400 		return (err);
3401 	}
3402 	ifsd_m[pidx] = m_head;
3403 	/*
3404 	 * XXX assumes a 1 to 1 relationship between segments and
3405 	 *        descriptors - this does not hold true on all drivers, e.g.
3406 	 *        cxgb
3407 	 */
3408 	if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) {
3409 		txq->ift_no_desc_avail++;
3410 		bus_dmamap_unload(buf_tag, map);
3411 		DBG_COUNTER_INC(encap_txq_avail_fail);
3412 		DBG_COUNTER_INC(encap_txd_encap_fail);
3413 		if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3414 			GROUPTASK_ENQUEUE(&txq->ift_task);
3415 		return (ENOBUFS);
3416 	}
3417 	/*
3418 	 * On Intel cards we can greatly reduce the number of TX interrupts
3419 	 * we see by only setting report status on every Nth descriptor.
3420 	 * However, this also means that the driver will need to keep track
3421 	 * of the descriptors that RS was set on to check them for the DD bit.
3422 	 */
3423 	txq->ift_rs_pending += nsegs + 1;
3424 	if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3425 	     iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) {
3426 		pi.ipi_flags |= IPI_TX_INTR;
3427 		txq->ift_rs_pending = 0;
3428 	}
3429 
3430 	pi.ipi_segs = segs;
3431 	pi.ipi_nsegs = nsegs;
3432 
3433 	MPASS(pidx >= 0 && pidx < txq->ift_size);
3434 #ifdef PKT_DEBUG
3435 	print_pkt(&pi);
3436 #endif
3437 	if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3438 		bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3439 		DBG_COUNTER_INC(tx_encap);
3440 		MPASS(pi.ipi_new_pidx < txq->ift_size);
3441 
3442 		ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3443 		if (pi.ipi_new_pidx < pi.ipi_pidx) {
3444 			ndesc += txq->ift_size;
3445 			txq->ift_gen = 1;
3446 		}
3447 		/*
3448 		 * drivers can need as many as
3449 		 * two sentinels
3450 		 */
3451 		MPASS(ndesc <= pi.ipi_nsegs + 2);
3452 		MPASS(pi.ipi_new_pidx != pidx);
3453 		MPASS(ndesc > 0);
3454 		txq->ift_in_use += ndesc;
3455 
3456 		/*
3457 		 * We update the last software descriptor again here because there may
3458 		 * be a sentinel and/or there may be more mbufs than segments
3459 		 */
3460 		txq->ift_pidx = pi.ipi_new_pidx;
3461 		txq->ift_npending += pi.ipi_ndescs;
3462 	} else {
3463 		*m_headp = m_head = iflib_remove_mbuf(txq);
3464 		if (err == EFBIG) {
3465 			txq->ift_txd_encap_efbig++;
3466 			if (remap < 2) {
3467 				remap = 1;
3468 				goto defrag;
3469 			}
3470 		}
3471 		goto defrag_failed;
3472 	}
3473 	/*
3474 	 * err can't possibly be non-zero here, so we don't neet to test it
3475 	 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3476 	 */
3477 	return (err);
3478 
3479 defrag_failed:
3480 	txq->ift_mbuf_defrag_failed++;
3481 	txq->ift_map_failed++;
3482 	m_freem(*m_headp);
3483 	DBG_COUNTER_INC(tx_frees);
3484 	*m_headp = NULL;
3485 	DBG_COUNTER_INC(encap_txd_encap_fail);
3486 	return (ENOMEM);
3487 }
3488 
3489 static void
3490 iflib_tx_desc_free(iflib_txq_t txq, int n)
3491 {
3492 	uint32_t qsize, cidx, mask, gen;
3493 	struct mbuf *m, **ifsd_m;
3494 	bool do_prefetch;
3495 
3496 	cidx = txq->ift_cidx;
3497 	gen = txq->ift_gen;
3498 	qsize = txq->ift_size;
3499 	mask = qsize-1;
3500 	ifsd_m = txq->ift_sds.ifsd_m;
3501 	do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH);
3502 
3503 	while (n-- > 0) {
3504 		if (do_prefetch) {
3505 			prefetch(ifsd_m[(cidx + 3) & mask]);
3506 			prefetch(ifsd_m[(cidx + 4) & mask]);
3507 		}
3508 		if ((m = ifsd_m[cidx]) != NULL) {
3509 			prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]);
3510 			if (m->m_pkthdr.csum_flags & CSUM_TSO) {
3511 				bus_dmamap_sync(txq->ift_tso_buf_tag,
3512 				    txq->ift_sds.ifsd_tso_map[cidx],
3513 				    BUS_DMASYNC_POSTWRITE);
3514 				bus_dmamap_unload(txq->ift_tso_buf_tag,
3515 				    txq->ift_sds.ifsd_tso_map[cidx]);
3516 			} else {
3517 				bus_dmamap_sync(txq->ift_buf_tag,
3518 				    txq->ift_sds.ifsd_map[cidx],
3519 				    BUS_DMASYNC_POSTWRITE);
3520 				bus_dmamap_unload(txq->ift_buf_tag,
3521 				    txq->ift_sds.ifsd_map[cidx]);
3522 			}
3523 			/* XXX we don't support any drivers that batch packets yet */
3524 			MPASS(m->m_nextpkt == NULL);
3525 			m_freem(m);
3526 			ifsd_m[cidx] = NULL;
3527 #if MEMORY_LOGGING
3528 			txq->ift_dequeued++;
3529 #endif
3530 			DBG_COUNTER_INC(tx_frees);
3531 		}
3532 		if (__predict_false(++cidx == qsize)) {
3533 			cidx = 0;
3534 			gen = 0;
3535 		}
3536 	}
3537 	txq->ift_cidx = cidx;
3538 	txq->ift_gen = gen;
3539 }
3540 
3541 static __inline int
3542 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh)
3543 {
3544 	int reclaim;
3545 	if_ctx_t ctx = txq->ift_ctx;
3546 
3547 	KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3548 	MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3549 
3550 	/*
3551 	 * Need a rate-limiting check so that this isn't called every time
3552 	 */
3553 	iflib_tx_credits_update(ctx, txq);
3554 	reclaim = DESC_RECLAIMABLE(txq);
3555 
3556 	if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) {
3557 #ifdef INVARIANTS
3558 		if (iflib_verbose_debug) {
3559 			printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__,
3560 			       txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3561 			       reclaim, thresh);
3562 
3563 		}
3564 #endif
3565 		return (0);
3566 	}
3567 	iflib_tx_desc_free(txq, reclaim);
3568 	txq->ift_cleaned += reclaim;
3569 	txq->ift_in_use -= reclaim;
3570 
3571 	return (reclaim);
3572 }
3573 
3574 static struct mbuf **
3575 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3576 {
3577 	int next, size;
3578 	struct mbuf **items;
3579 
3580 	size = r->size;
3581 	next = (cidx + CACHE_PTR_INCREMENT) & (size-1);
3582 	items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3583 
3584 	prefetch(items[(cidx + offset) & (size-1)]);
3585 	if (remaining > 1) {
3586 		prefetch2cachelines(&items[next]);
3587 		prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]);
3588 		prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]);
3589 		prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]);
3590 	}
3591 	return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)]));
3592 }
3593 
3594 static void
3595 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3596 {
3597 
3598 	ifmp_ring_check_drainage(txq->ift_br, budget);
3599 }
3600 
3601 static uint32_t
3602 iflib_txq_can_drain(struct ifmp_ring *r)
3603 {
3604 	iflib_txq_t txq = r->cookie;
3605 	if_ctx_t ctx = txq->ift_ctx;
3606 
3607 	if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2)
3608 		return (1);
3609 	bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3610 	    BUS_DMASYNC_POSTREAD);
3611 	return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3612 	    false));
3613 }
3614 
3615 static uint32_t
3616 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3617 {
3618 	iflib_txq_t txq = r->cookie;
3619 	if_ctx_t ctx = txq->ift_ctx;
3620 	if_t ifp = ctx->ifc_ifp;
3621 	struct mbuf *m, **mp;
3622 	int avail, bytes_sent, consumed, count, err, i, in_use_prev;
3623 	int mcast_sent, pkt_sent, reclaimed, txq_avail;
3624 	bool do_prefetch, rang, ring;
3625 
3626 	if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3627 			    !LINK_ACTIVE(ctx))) {
3628 		DBG_COUNTER_INC(txq_drain_notready);
3629 		return (0);
3630 	}
3631 	reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
3632 	rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use);
3633 	avail = IDXDIFF(pidx, cidx, r->size);
3634 	if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3635 		DBG_COUNTER_INC(txq_drain_flushing);
3636 		for (i = 0; i < avail; i++) {
3637 			if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq))
3638 				m_free(r->items[(cidx + i) & (r->size-1)]);
3639 			r->items[(cidx + i) & (r->size-1)] = NULL;
3640 		}
3641 		return (avail);
3642 	}
3643 
3644 	if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3645 		txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3646 		CALLOUT_LOCK(txq);
3647 		callout_stop(&txq->ift_timer);
3648 		CALLOUT_UNLOCK(txq);
3649 		DBG_COUNTER_INC(txq_drain_oactive);
3650 		return (0);
3651 	}
3652 	if (reclaimed)
3653 		txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3654 	consumed = mcast_sent = bytes_sent = pkt_sent = 0;
3655 	count = MIN(avail, TX_BATCH_SIZE);
3656 #ifdef INVARIANTS
3657 	if (iflib_verbose_debug)
3658 		printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__,
3659 		       avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3660 #endif
3661 	do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3662 	txq_avail = TXQ_AVAIL(txq);
3663 	err = 0;
3664 	for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) {
3665 		int rem = do_prefetch ? count - i : 0;
3666 
3667 		mp = _ring_peek_one(r, cidx, i, rem);
3668 		MPASS(mp != NULL && *mp != NULL);
3669 		if (__predict_false(*mp == (struct mbuf *)txq)) {
3670 			consumed++;
3671 			continue;
3672 		}
3673 		in_use_prev = txq->ift_in_use;
3674 		err = iflib_encap(txq, mp);
3675 		if (__predict_false(err)) {
3676 			/* no room - bail out */
3677 			if (err == ENOBUFS)
3678 				break;
3679 			consumed++;
3680 			/* we can't send this packet - skip it */
3681 			continue;
3682 		}
3683 		consumed++;
3684 		pkt_sent++;
3685 		m = *mp;
3686 		DBG_COUNTER_INC(tx_sent);
3687 		bytes_sent += m->m_pkthdr.len;
3688 		mcast_sent += !!(m->m_flags & M_MCAST);
3689 		txq_avail = TXQ_AVAIL(txq);
3690 
3691 		txq->ift_db_pending += (txq->ift_in_use - in_use_prev);
3692 		ETHER_BPF_MTAP(ifp, m);
3693 		if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING)))
3694 			break;
3695 		rang = iflib_txd_db_check(ctx, txq, false, in_use_prev);
3696 	}
3697 
3698 	/* deliberate use of bitwise or to avoid gratuitous short-circuit */
3699 	ring = rang ? false  : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx));
3700 	iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use);
3701 	if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3702 	if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3703 	if (mcast_sent)
3704 		if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3705 #ifdef INVARIANTS
3706 	if (iflib_verbose_debug)
3707 		printf("consumed=%d\n", consumed);
3708 #endif
3709 	return (consumed);
3710 }
3711 
3712 static uint32_t
3713 iflib_txq_drain_always(struct ifmp_ring *r)
3714 {
3715 	return (1);
3716 }
3717 
3718 static uint32_t
3719 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3720 {
3721 	int i, avail;
3722 	struct mbuf **mp;
3723 	iflib_txq_t txq;
3724 
3725 	txq = r->cookie;
3726 
3727 	txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3728 	CALLOUT_LOCK(txq);
3729 	callout_stop(&txq->ift_timer);
3730 	CALLOUT_UNLOCK(txq);
3731 
3732 	avail = IDXDIFF(pidx, cidx, r->size);
3733 	for (i = 0; i < avail; i++) {
3734 		mp = _ring_peek_one(r, cidx, i, avail - i);
3735 		if (__predict_false(*mp == (struct mbuf *)txq))
3736 			continue;
3737 		m_freem(*mp);
3738 		DBG_COUNTER_INC(tx_frees);
3739 	}
3740 	MPASS(ifmp_ring_is_stalled(r) == 0);
3741 	return (avail);
3742 }
3743 
3744 static void
3745 iflib_ifmp_purge(iflib_txq_t txq)
3746 {
3747 	struct ifmp_ring *r;
3748 
3749 	r = txq->ift_br;
3750 	r->drain = iflib_txq_drain_free;
3751 	r->can_drain = iflib_txq_drain_always;
3752 
3753 	ifmp_ring_check_drainage(r, r->size);
3754 
3755 	r->drain = iflib_txq_drain;
3756 	r->can_drain = iflib_txq_can_drain;
3757 }
3758 
3759 static void
3760 _task_fn_tx(void *context)
3761 {
3762 	iflib_txq_t txq = context;
3763 	if_ctx_t ctx = txq->ift_ctx;
3764 	if_t ifp = ctx->ifc_ifp;
3765 	int abdicate = ctx->ifc_sysctl_tx_abdicate;
3766 
3767 #ifdef IFLIB_DIAGNOSTICS
3768 	txq->ift_cpu_exec_count[curcpu]++;
3769 #endif
3770 	if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
3771 		return;
3772 #ifdef DEV_NETMAP
3773 	if ((if_getcapenable(ifp) & IFCAP_NETMAP) &&
3774 	    netmap_tx_irq(ifp, txq->ift_id))
3775 		goto skip_ifmp;
3776 #endif
3777 #ifdef ALTQ
3778 	if (ALTQ_IS_ENABLED(&ifp->if_snd))
3779 		iflib_altq_if_start(ifp);
3780 #endif
3781 	if (txq->ift_db_pending)
3782 		ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
3783 	else if (!abdicate)
3784 		ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3785 	/*
3786 	 * When abdicating, we always need to check drainage, not just when we don't enqueue
3787 	 */
3788 	if (abdicate)
3789 		ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
3790 #ifdef DEV_NETMAP
3791 skip_ifmp:
3792 #endif
3793 	if (ctx->ifc_flags & IFC_LEGACY)
3794 		IFDI_INTR_ENABLE(ctx);
3795 	else
3796 		IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
3797 }
3798 
3799 static void
3800 _task_fn_rx(void *context)
3801 {
3802 	iflib_rxq_t rxq = context;
3803 	if_ctx_t ctx = rxq->ifr_ctx;
3804 	uint8_t more;
3805 	uint16_t budget;
3806 #ifdef DEV_NETMAP
3807 	u_int work = 0;
3808 	int nmirq;
3809 #endif
3810 
3811 #ifdef IFLIB_DIAGNOSTICS
3812 	rxq->ifr_cpu_exec_count[curcpu]++;
3813 #endif
3814 	DBG_COUNTER_INC(task_fn_rxs);
3815 	if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3816 		return;
3817 #ifdef DEV_NETMAP
3818 	nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work);
3819 	if (nmirq != NM_IRQ_PASS) {
3820 		more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0;
3821 		goto skip_rxeof;
3822 	}
3823 #endif
3824 	budget = ctx->ifc_sysctl_rx_budget;
3825 	if (budget == 0)
3826 		budget = 16;	/* XXX */
3827 	more = iflib_rxeof(rxq, budget);
3828 #ifdef DEV_NETMAP
3829 skip_rxeof:
3830 #endif
3831 	if ((more & IFLIB_RXEOF_MORE) == 0) {
3832 		if (ctx->ifc_flags & IFC_LEGACY)
3833 			IFDI_INTR_ENABLE(ctx);
3834 		else
3835 			IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
3836 		DBG_COUNTER_INC(rx_intr_enables);
3837 	}
3838 	if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
3839 		return;
3840 
3841 	if (more & IFLIB_RXEOF_MORE)
3842 		GROUPTASK_ENQUEUE(&rxq->ifr_task);
3843 	else if (more & IFLIB_RXEOF_EMPTY)
3844 		callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq);
3845 }
3846 
3847 static void
3848 _task_fn_admin(void *context)
3849 {
3850 	if_ctx_t ctx = context;
3851 	if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
3852 	iflib_txq_t txq;
3853 	int i;
3854 	bool oactive, running, do_reset, do_watchdog, in_detach;
3855 	uint32_t reset_on = hz / 2;
3856 
3857 	STATE_LOCK(ctx);
3858 	running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
3859 	oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
3860 	do_reset = (ctx->ifc_flags & IFC_DO_RESET);
3861 	do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
3862 	in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
3863 	ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG);
3864 	STATE_UNLOCK(ctx);
3865 
3866 	if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3867 		return;
3868 	if (in_detach)
3869 		return;
3870 
3871 	CTX_LOCK(ctx);
3872 	for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3873 		CALLOUT_LOCK(txq);
3874 		callout_stop(&txq->ift_timer);
3875 		CALLOUT_UNLOCK(txq);
3876 	}
3877 	if (do_watchdog) {
3878 		ctx->ifc_watchdog_events++;
3879 		IFDI_WATCHDOG_RESET(ctx);
3880 	}
3881 	IFDI_UPDATE_ADMIN_STATUS(ctx);
3882 	for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
3883 #ifdef DEV_NETMAP
3884 		reset_on = hz / 2;
3885 		if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP)
3886 			iflib_netmap_timer_adjust(ctx, txq, &reset_on);
3887 #endif
3888 		callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu);
3889 	}
3890 	IFDI_LINK_INTR_ENABLE(ctx);
3891 	if (do_reset)
3892 		iflib_if_init_locked(ctx);
3893 	CTX_UNLOCK(ctx);
3894 
3895 	if (LINK_ACTIVE(ctx) == 0)
3896 		return;
3897 	for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
3898 		iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
3899 }
3900 
3901 
3902 static void
3903 _task_fn_iov(void *context)
3904 {
3905 	if_ctx_t ctx = context;
3906 
3907 	if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
3908 	    !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
3909 		return;
3910 
3911 	CTX_LOCK(ctx);
3912 	IFDI_VFLR_HANDLE(ctx);
3913 	CTX_UNLOCK(ctx);
3914 }
3915 
3916 static int
3917 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3918 {
3919 	int err;
3920 	if_int_delay_info_t info;
3921 	if_ctx_t ctx;
3922 
3923 	info = (if_int_delay_info_t)arg1;
3924 	ctx = info->iidi_ctx;
3925 	info->iidi_req = req;
3926 	info->iidi_oidp = oidp;
3927 	CTX_LOCK(ctx);
3928 	err = IFDI_SYSCTL_INT_DELAY(ctx, info);
3929 	CTX_UNLOCK(ctx);
3930 	return (err);
3931 }
3932 
3933 /*********************************************************************
3934  *
3935  *  IFNET FUNCTIONS
3936  *
3937  **********************************************************************/
3938 
3939 static void
3940 iflib_if_init_locked(if_ctx_t ctx)
3941 {
3942 	iflib_stop(ctx);
3943 	iflib_init_locked(ctx);
3944 }
3945 
3946 
3947 static void
3948 iflib_if_init(void *arg)
3949 {
3950 	if_ctx_t ctx = arg;
3951 
3952 	CTX_LOCK(ctx);
3953 	iflib_if_init_locked(ctx);
3954 	CTX_UNLOCK(ctx);
3955 }
3956 
3957 static int
3958 iflib_if_transmit(if_t ifp, struct mbuf *m)
3959 {
3960 	if_ctx_t	ctx = if_getsoftc(ifp);
3961 
3962 	iflib_txq_t txq;
3963 	int err, qidx;
3964 	int abdicate = ctx->ifc_sysctl_tx_abdicate;
3965 
3966 	if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
3967 		DBG_COUNTER_INC(tx_frees);
3968 		m_freem(m);
3969 		return (ENETDOWN);
3970 	}
3971 
3972 	MPASS(m->m_nextpkt == NULL);
3973 	/* ALTQ-enabled interfaces always use queue 0. */
3974 	qidx = 0;
3975 	if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd))
3976 		qidx = QIDX(ctx, m);
3977 	/*
3978 	 * XXX calculate buf_ring based on flowid (divvy up bits?)
3979 	 */
3980 	txq = &ctx->ifc_txqs[qidx];
3981 
3982 #ifdef DRIVER_BACKPRESSURE
3983 	if (txq->ift_closed) {
3984 		while (m != NULL) {
3985 			next = m->m_nextpkt;
3986 			m->m_nextpkt = NULL;
3987 			m_freem(m);
3988 			DBG_COUNTER_INC(tx_frees);
3989 			m = next;
3990 		}
3991 		return (ENOBUFS);
3992 	}
3993 #endif
3994 #ifdef notyet
3995 	qidx = count = 0;
3996 	mp = marr;
3997 	next = m;
3998 	do {
3999 		count++;
4000 		next = next->m_nextpkt;
4001 	} while (next != NULL);
4002 
4003 	if (count > nitems(marr))
4004 		if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
4005 			/* XXX check nextpkt */
4006 			m_freem(m);
4007 			/* XXX simplify for now */
4008 			DBG_COUNTER_INC(tx_frees);
4009 			return (ENOBUFS);
4010 		}
4011 	for (next = m, i = 0; next != NULL; i++) {
4012 		mp[i] = next;
4013 		next = next->m_nextpkt;
4014 		mp[i]->m_nextpkt = NULL;
4015 	}
4016 #endif
4017 	DBG_COUNTER_INC(tx_seen);
4018 	err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
4019 
4020 	if (abdicate)
4021 		GROUPTASK_ENQUEUE(&txq->ift_task);
4022  	if (err) {
4023 		if (!abdicate)
4024 			GROUPTASK_ENQUEUE(&txq->ift_task);
4025 		/* support forthcoming later */
4026 #ifdef DRIVER_BACKPRESSURE
4027 		txq->ift_closed = TRUE;
4028 #endif
4029 		ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4030 		m_freem(m);
4031 		DBG_COUNTER_INC(tx_frees);
4032 	}
4033 
4034 	return (err);
4035 }
4036 
4037 #ifdef ALTQ
4038 /*
4039  * The overall approach to integrating iflib with ALTQ is to continue to use
4040  * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4041  * ring.  Technically, when using ALTQ, queueing to an intermediate mp_ring
4042  * is redundant/unnecessary, but doing so minimizes the amount of
4043  * ALTQ-specific code required in iflib.  It is assumed that the overhead of
4044  * redundantly queueing to an intermediate mp_ring is swamped by the
4045  * performance limitations inherent in using ALTQ.
4046  *
4047  * When ALTQ support is compiled in, all iflib drivers will use a transmit
4048  * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4049  * given interface.  If ALTQ is enabled for an interface, then all
4050  * transmitted packets for that interface will be submitted to the ALTQ
4051  * subsystem via IFQ_ENQUEUE().  We don't use the legacy if_transmit()
4052  * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4053  * update stats that the iflib machinery handles, and which is sensitve to
4054  * the disused IFF_DRV_OACTIVE flag.  Additionally, iflib_altq_if_start()
4055  * will be installed as the start routine for use by ALTQ facilities that
4056  * need to trigger queue drains on a scheduled basis.
4057  *
4058  */
4059 static void
4060 iflib_altq_if_start(if_t ifp)
4061 {
4062 	struct ifaltq *ifq = &ifp->if_snd;
4063 	struct mbuf *m;
4064 
4065 	IFQ_LOCK(ifq);
4066 	IFQ_DEQUEUE_NOLOCK(ifq, m);
4067 	while (m != NULL) {
4068 		iflib_if_transmit(ifp, m);
4069 		IFQ_DEQUEUE_NOLOCK(ifq, m);
4070 	}
4071 	IFQ_UNLOCK(ifq);
4072 }
4073 
4074 static int
4075 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4076 {
4077 	int err;
4078 
4079 	if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
4080 		IFQ_ENQUEUE(&ifp->if_snd, m, err);
4081 		if (err == 0)
4082 			iflib_altq_if_start(ifp);
4083 	} else
4084 		err = iflib_if_transmit(ifp, m);
4085 
4086 	return (err);
4087 }
4088 #endif /* ALTQ */
4089 
4090 static void
4091 iflib_if_qflush(if_t ifp)
4092 {
4093 	if_ctx_t ctx = if_getsoftc(ifp);
4094 	iflib_txq_t txq = ctx->ifc_txqs;
4095 	int i;
4096 
4097 	STATE_LOCK(ctx);
4098 	ctx->ifc_flags |= IFC_QFLUSH;
4099 	STATE_UNLOCK(ctx);
4100 	for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4101 		while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4102 			iflib_txq_check_drain(txq, 0);
4103 	STATE_LOCK(ctx);
4104 	ctx->ifc_flags &= ~IFC_QFLUSH;
4105 	STATE_UNLOCK(ctx);
4106 
4107 	/*
4108 	 * When ALTQ is enabled, this will also take care of purging the
4109 	 * ALTQ queue(s).
4110 	 */
4111 	if_qflush(ifp);
4112 }
4113 
4114 
4115 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4116 		     IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4117 		     IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4118 		     IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP)
4119 
4120 static int
4121 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4122 {
4123 	if_ctx_t ctx = if_getsoftc(ifp);
4124 	struct ifreq	*ifr = (struct ifreq *)data;
4125 #if defined(INET) || defined(INET6)
4126 	struct ifaddr	*ifa = (struct ifaddr *)data;
4127 #endif
4128 	bool		avoid_reset = false;
4129 	int		err = 0, reinit = 0, bits;
4130 
4131 	switch (command) {
4132 	case SIOCSIFADDR:
4133 #ifdef INET
4134 		if (ifa->ifa_addr->sa_family == AF_INET)
4135 			avoid_reset = true;
4136 #endif
4137 #ifdef INET6
4138 		if (ifa->ifa_addr->sa_family == AF_INET6)
4139 			avoid_reset = true;
4140 #endif
4141 		/*
4142 		** Calling init results in link renegotiation,
4143 		** so we avoid doing it when possible.
4144 		*/
4145 		if (avoid_reset) {
4146 			if_setflagbits(ifp, IFF_UP,0);
4147 			if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4148 				reinit = 1;
4149 #ifdef INET
4150 			if (!(if_getflags(ifp) & IFF_NOARP))
4151 				arp_ifinit(ifp, ifa);
4152 #endif
4153 		} else
4154 			err = ether_ioctl(ifp, command, data);
4155 		break;
4156 	case SIOCSIFMTU:
4157 		CTX_LOCK(ctx);
4158 		if (ifr->ifr_mtu == if_getmtu(ifp)) {
4159 			CTX_UNLOCK(ctx);
4160 			break;
4161 		}
4162 		bits = if_getdrvflags(ifp);
4163 		/* stop the driver and free any clusters before proceeding */
4164 		iflib_stop(ctx);
4165 
4166 		if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4167 			STATE_LOCK(ctx);
4168 			if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4169 				ctx->ifc_flags |= IFC_MULTISEG;
4170 			else
4171 				ctx->ifc_flags &= ~IFC_MULTISEG;
4172 			STATE_UNLOCK(ctx);
4173 			err = if_setmtu(ifp, ifr->ifr_mtu);
4174 		}
4175 		iflib_init_locked(ctx);
4176 		STATE_LOCK(ctx);
4177 		if_setdrvflags(ifp, bits);
4178 		STATE_UNLOCK(ctx);
4179 		CTX_UNLOCK(ctx);
4180 		break;
4181 	case SIOCSIFFLAGS:
4182 		CTX_LOCK(ctx);
4183 		if (if_getflags(ifp) & IFF_UP) {
4184 			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4185 				if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4186 				    (IFF_PROMISC | IFF_ALLMULTI)) {
4187 					CTX_UNLOCK(ctx);
4188 					err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4189 					CTX_LOCK(ctx);
4190 				}
4191 			} else
4192 				reinit = 1;
4193 		} else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4194 			iflib_stop(ctx);
4195 		}
4196 		ctx->ifc_if_flags = if_getflags(ifp);
4197 		CTX_UNLOCK(ctx);
4198 		break;
4199 	case SIOCADDMULTI:
4200 	case SIOCDELMULTI:
4201 		if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4202 			CTX_LOCK(ctx);
4203 			IFDI_INTR_DISABLE(ctx);
4204 			IFDI_MULTI_SET(ctx);
4205 			IFDI_INTR_ENABLE(ctx);
4206 			CTX_UNLOCK(ctx);
4207 		}
4208 		break;
4209 	case SIOCSIFMEDIA:
4210 		CTX_LOCK(ctx);
4211 		IFDI_MEDIA_SET(ctx);
4212 		CTX_UNLOCK(ctx);
4213 		/* FALLTHROUGH */
4214 	case SIOCGIFMEDIA:
4215 	case SIOCGIFXMEDIA:
4216 		err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4217 		break;
4218 	case SIOCGI2C:
4219 	{
4220 		struct ifi2creq i2c;
4221 
4222 		err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4223 		if (err != 0)
4224 			break;
4225 		if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4226 			err = EINVAL;
4227 			break;
4228 		}
4229 		if (i2c.len > sizeof(i2c.data)) {
4230 			err = EINVAL;
4231 			break;
4232 		}
4233 
4234 		if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4235 			err = copyout(&i2c, ifr_data_get_ptr(ifr),
4236 			    sizeof(i2c));
4237 		break;
4238 	}
4239 	case SIOCSIFCAP:
4240 	{
4241 		int mask, setmask, oldmask;
4242 
4243 		oldmask = if_getcapenable(ifp);
4244 		mask = ifr->ifr_reqcap ^ oldmask;
4245 		mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP;
4246 		setmask = 0;
4247 #ifdef TCP_OFFLOAD
4248 		setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6);
4249 #endif
4250 		setmask |= (mask & IFCAP_FLAGS);
4251 		setmask |= (mask & IFCAP_WOL);
4252 
4253 		/*
4254 		 * If any RX csum has changed, change all the ones that
4255 		 * are supported by the driver.
4256 		 */
4257 		if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4258 			setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4259 			    (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4260 		}
4261 
4262 		/*
4263 		 * want to ensure that traffic has stopped before we change any of the flags
4264 		 */
4265 		if (setmask) {
4266 			CTX_LOCK(ctx);
4267 			bits = if_getdrvflags(ifp);
4268 			if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4269 				iflib_stop(ctx);
4270 			STATE_LOCK(ctx);
4271 			if_togglecapenable(ifp, setmask);
4272 			STATE_UNLOCK(ctx);
4273 			if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4274 				iflib_init_locked(ctx);
4275 			STATE_LOCK(ctx);
4276 			if_setdrvflags(ifp, bits);
4277 			STATE_UNLOCK(ctx);
4278 			CTX_UNLOCK(ctx);
4279 		}
4280 		if_vlancap(ifp);
4281 		break;
4282 	}
4283 	case SIOCGPRIVATE_0:
4284 	case SIOCSDRVSPEC:
4285 	case SIOCGDRVSPEC:
4286 		CTX_LOCK(ctx);
4287 		err = IFDI_PRIV_IOCTL(ctx, command, data);
4288 		CTX_UNLOCK(ctx);
4289 		break;
4290 	default:
4291 		err = ether_ioctl(ifp, command, data);
4292 		break;
4293 	}
4294 	if (reinit)
4295 		iflib_if_init(ctx);
4296 	return (err);
4297 }
4298 
4299 static uint64_t
4300 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4301 {
4302 	if_ctx_t ctx = if_getsoftc(ifp);
4303 
4304 	return (IFDI_GET_COUNTER(ctx, cnt));
4305 }
4306 
4307 /*********************************************************************
4308  *
4309  *  OTHER FUNCTIONS EXPORTED TO THE STACK
4310  *
4311  **********************************************************************/
4312 
4313 static void
4314 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4315 {
4316 	if_ctx_t ctx = if_getsoftc(ifp);
4317 
4318 	if ((void *)ctx != arg)
4319 		return;
4320 
4321 	if ((vtag == 0) || (vtag > 4095))
4322 		return;
4323 
4324 	if (iflib_in_detach(ctx))
4325 		return;
4326 
4327 	CTX_LOCK(ctx);
4328 	/* Driver may need all untagged packets to be flushed */
4329 	if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4330 		iflib_stop(ctx);
4331 	IFDI_VLAN_REGISTER(ctx, vtag);
4332 	/* Re-init to load the changes, if required */
4333 	if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4334 		iflib_init_locked(ctx);
4335 	CTX_UNLOCK(ctx);
4336 }
4337 
4338 static void
4339 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4340 {
4341 	if_ctx_t ctx = if_getsoftc(ifp);
4342 
4343 	if ((void *)ctx != arg)
4344 		return;
4345 
4346 	if ((vtag == 0) || (vtag > 4095))
4347 		return;
4348 
4349 	CTX_LOCK(ctx);
4350 	/* Driver may need all tagged packets to be flushed */
4351 	if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4352 		iflib_stop(ctx);
4353 	IFDI_VLAN_UNREGISTER(ctx, vtag);
4354 	/* Re-init to load the changes, if required */
4355 	if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4356 		iflib_init_locked(ctx);
4357 	CTX_UNLOCK(ctx);
4358 }
4359 
4360 static void
4361 iflib_led_func(void *arg, int onoff)
4362 {
4363 	if_ctx_t ctx = arg;
4364 
4365 	CTX_LOCK(ctx);
4366 	IFDI_LED_FUNC(ctx, onoff);
4367 	CTX_UNLOCK(ctx);
4368 }
4369 
4370 /*********************************************************************
4371  *
4372  *  BUS FUNCTION DEFINITIONS
4373  *
4374  **********************************************************************/
4375 
4376 int
4377 iflib_device_probe(device_t dev)
4378 {
4379 	const pci_vendor_info_t *ent;
4380 	if_shared_ctx_t sctx;
4381 	uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id;
4382 	uint16_t pci_vendor_id;
4383 
4384 	if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4385 		return (ENOTSUP);
4386 
4387 	pci_vendor_id = pci_get_vendor(dev);
4388 	pci_device_id = pci_get_device(dev);
4389 	pci_subvendor_id = pci_get_subvendor(dev);
4390 	pci_subdevice_id = pci_get_subdevice(dev);
4391 	pci_rev_id = pci_get_revid(dev);
4392 	if (sctx->isc_parse_devinfo != NULL)
4393 		sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4394 
4395 	ent = sctx->isc_vendor_info;
4396 	while (ent->pvi_vendor_id != 0) {
4397 		if (pci_vendor_id != ent->pvi_vendor_id) {
4398 			ent++;
4399 			continue;
4400 		}
4401 		if ((pci_device_id == ent->pvi_device_id) &&
4402 		    ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4403 		     (ent->pvi_subvendor_id == 0)) &&
4404 		    ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4405 		     (ent->pvi_subdevice_id == 0)) &&
4406 		    ((pci_rev_id == ent->pvi_rev_id) ||
4407 		     (ent->pvi_rev_id == 0))) {
4408 
4409 			device_set_desc_copy(dev, ent->pvi_name);
4410 			/* this needs to be changed to zero if the bus probing code
4411 			 * ever stops re-probing on best match because the sctx
4412 			 * may have its values over written by register calls
4413 			 * in subsequent probes
4414 			 */
4415 			return (BUS_PROBE_DEFAULT);
4416 		}
4417 		ent++;
4418 	}
4419 	return (ENXIO);
4420 }
4421 
4422 int
4423 iflib_device_probe_vendor(device_t dev)
4424 {
4425 	int probe;
4426 
4427 	probe = iflib_device_probe(dev);
4428 	if (probe == BUS_PROBE_DEFAULT)
4429 		return (BUS_PROBE_VENDOR);
4430 	else
4431 		return (probe);
4432 }
4433 
4434 static void
4435 iflib_reset_qvalues(if_ctx_t ctx)
4436 {
4437 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4438 	if_shared_ctx_t sctx = ctx->ifc_sctx;
4439 	device_t dev = ctx->ifc_dev;
4440 	int i;
4441 
4442 	if (ctx->ifc_sysctl_ntxqs != 0)
4443 		scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4444 	if (ctx->ifc_sysctl_nrxqs != 0)
4445 		scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4446 
4447 	for (i = 0; i < sctx->isc_ntxqs; i++) {
4448 		if (ctx->ifc_sysctl_ntxds[i] != 0)
4449 			scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4450 		else
4451 			scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4452 	}
4453 
4454 	for (i = 0; i < sctx->isc_nrxqs; i++) {
4455 		if (ctx->ifc_sysctl_nrxds[i] != 0)
4456 			scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4457 		else
4458 			scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4459 	}
4460 
4461 	for (i = 0; i < sctx->isc_nrxqs; i++) {
4462 		if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4463 			device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4464 				      i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4465 			scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4466 		}
4467 		if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4468 			device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4469 				      i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4470 			scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4471 		}
4472 		if (!powerof2(scctx->isc_nrxd[i])) {
4473 			device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4474 				      i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4475 			scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4476 		}
4477 	}
4478 
4479 	for (i = 0; i < sctx->isc_ntxqs; i++) {
4480 		if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4481 			device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4482 				      i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4483 			scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4484 		}
4485 		if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4486 			device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4487 				      i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4488 			scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4489 		}
4490 		if (!powerof2(scctx->isc_ntxd[i])) {
4491 			device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4492 				      i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4493 			scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4494 		}
4495 	}
4496 }
4497 
4498 static void
4499 iflib_add_pfil(if_ctx_t ctx)
4500 {
4501 	struct pfil_head *pfil;
4502 	struct pfil_head_args pa;
4503 	iflib_rxq_t rxq;
4504 	int i;
4505 
4506 	pa.pa_version = PFIL_VERSION;
4507 	pa.pa_flags = PFIL_IN;
4508 	pa.pa_type = PFIL_TYPE_ETHERNET;
4509 	pa.pa_headname = ctx->ifc_ifp->if_xname;
4510 	pfil = pfil_head_register(&pa);
4511 
4512 	for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4513 		rxq->pfil = pfil;
4514 	}
4515 }
4516 
4517 static void
4518 iflib_rem_pfil(if_ctx_t ctx)
4519 {
4520 	struct pfil_head *pfil;
4521 	iflib_rxq_t rxq;
4522 	int i;
4523 
4524 	rxq = ctx->ifc_rxqs;
4525 	pfil = rxq->pfil;
4526 	for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4527 		rxq->pfil = NULL;
4528 	}
4529 	pfil_head_unregister(pfil);
4530 }
4531 
4532 static uint16_t
4533 get_ctx_core_offset(if_ctx_t ctx)
4534 {
4535 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4536 	struct cpu_offset *op;
4537 	uint16_t qc;
4538 	uint16_t ret = ctx->ifc_sysctl_core_offset;
4539 
4540 	if (ret != CORE_OFFSET_UNSPECIFIED)
4541 		return (ret);
4542 
4543 	if (ctx->ifc_sysctl_separate_txrx)
4544 		qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets;
4545 	else
4546 		qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets);
4547 
4548 	mtx_lock(&cpu_offset_mtx);
4549 	SLIST_FOREACH(op, &cpu_offsets, entries) {
4550 		if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4551 			ret = op->offset;
4552 			op->offset += qc;
4553 			MPASS(op->refcount < UINT_MAX);
4554 			op->refcount++;
4555 			break;
4556 		}
4557 	}
4558 	if (ret == CORE_OFFSET_UNSPECIFIED) {
4559 		ret = 0;
4560 		op = malloc(sizeof(struct cpu_offset), M_IFLIB,
4561 		    M_NOWAIT | M_ZERO);
4562 		if (op == NULL) {
4563 			device_printf(ctx->ifc_dev,
4564 			    "allocation for cpu offset failed.\n");
4565 		} else {
4566 			op->offset = qc;
4567 			op->refcount = 1;
4568 			CPU_COPY(&ctx->ifc_cpus, &op->set);
4569 			SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
4570 		}
4571 	}
4572 	mtx_unlock(&cpu_offset_mtx);
4573 
4574 	return (ret);
4575 }
4576 
4577 static void
4578 unref_ctx_core_offset(if_ctx_t ctx)
4579 {
4580 	struct cpu_offset *op, *top;
4581 
4582 	mtx_lock(&cpu_offset_mtx);
4583 	SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
4584 		if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4585 			MPASS(op->refcount > 0);
4586 			op->refcount--;
4587 			if (op->refcount == 0) {
4588 				SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
4589 				free(op, M_IFLIB);
4590 			}
4591 			break;
4592 		}
4593 	}
4594 	mtx_unlock(&cpu_offset_mtx);
4595 }
4596 
4597 int
4598 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
4599 {
4600 	if_ctx_t ctx;
4601 	if_t ifp;
4602 	if_softc_ctx_t scctx;
4603 	kobjop_desc_t kobj_desc;
4604 	kobj_method_t *kobj_method;
4605 	int err, msix, rid;
4606 	int num_txd, num_rxd;
4607 
4608 	ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO);
4609 
4610 	if (sc == NULL) {
4611 		sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4612 		device_set_softc(dev, ctx);
4613 		ctx->ifc_flags |= IFC_SC_ALLOCATED;
4614 	}
4615 
4616 	ctx->ifc_sctx = sctx;
4617 	ctx->ifc_dev = dev;
4618 	ctx->ifc_softc = sc;
4619 
4620 	if ((err = iflib_register(ctx)) != 0) {
4621 		device_printf(dev, "iflib_register failed %d\n", err);
4622 		goto fail_ctx_free;
4623 	}
4624 	iflib_add_device_sysctl_pre(ctx);
4625 
4626 	scctx = &ctx->ifc_softc_ctx;
4627 	ifp = ctx->ifc_ifp;
4628 
4629 	iflib_reset_qvalues(ctx);
4630 	CTX_LOCK(ctx);
4631 	if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4632 		device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4633 		goto fail_unlock;
4634 	}
4635 	_iflib_pre_assert(scctx);
4636 	ctx->ifc_txrx = *scctx->isc_txrx;
4637 
4638 	if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
4639 		ctx->ifc_mediap = scctx->isc_media;
4640 
4641 #ifdef INVARIANTS
4642 	if (scctx->isc_capabilities & IFCAP_TXCSUM)
4643 		MPASS(scctx->isc_tx_csum_flags);
4644 #endif
4645 
4646 	if_setcapabilities(ifp,
4647 	    scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP);
4648 	if_setcapenable(ifp,
4649 	    scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP);
4650 
4651 	if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4652 		scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4653 	if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4654 		scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4655 
4656 	num_txd = iflib_num_tx_descs(ctx);
4657 	num_rxd = iflib_num_rx_descs(ctx);
4658 
4659 	/* XXX change for per-queue sizes */
4660 	device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4661 	    num_txd, num_rxd);
4662 
4663 	if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
4664 		scctx->isc_tx_nsegments = max(1, num_txd /
4665 		    MAX_SINGLE_PACKET_FRACTION);
4666 	if (scctx->isc_tx_tso_segments_max > num_txd /
4667 	    MAX_SINGLE_PACKET_FRACTION)
4668 		scctx->isc_tx_tso_segments_max = max(1,
4669 		    num_txd / MAX_SINGLE_PACKET_FRACTION);
4670 
4671 	/* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4672 	if (if_getcapabilities(ifp) & IFCAP_TSO) {
4673 		/*
4674 		 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4675 		 * but some MACs do.
4676 		 */
4677 		if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4678 		    IP_MAXPACKET));
4679 		/*
4680 		 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4681 		 * into account.  In the worst case, each of these calls will
4682 		 * add another mbuf and, thus, the requirement for another DMA
4683 		 * segment.  So for best performance, it doesn't make sense to
4684 		 * advertize a maximum of TSO segments that typically will
4685 		 * require defragmentation in iflib_encap().
4686 		 */
4687 		if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4688 		if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4689 	}
4690 	if (scctx->isc_rss_table_size == 0)
4691 		scctx->isc_rss_table_size = 64;
4692 	scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4693 
4694 	GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4695 	/* XXX format name */
4696 	taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4697 	    NULL, NULL, "admin");
4698 
4699 	/* Set up cpu set.  If it fails, use the set of all CPUs. */
4700 	if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
4701 		device_printf(dev, "Unable to fetch CPU list\n");
4702 		CPU_COPY(&all_cpus, &ctx->ifc_cpus);
4703 	}
4704 	MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
4705 
4706 	/*
4707 	** Now set up MSI or MSI-X, should return us the number of supported
4708 	** vectors (will be 1 for a legacy interrupt and MSI).
4709 	*/
4710 	if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
4711 		msix = scctx->isc_vectors;
4712 	} else if (scctx->isc_msix_bar != 0)
4713 	       /*
4714 		* The simple fact that isc_msix_bar is not 0 does not mean we
4715 		* we have a good value there that is known to work.
4716 		*/
4717 		msix = iflib_msix_init(ctx);
4718 	else {
4719 		scctx->isc_vectors = 1;
4720 		scctx->isc_ntxqsets = 1;
4721 		scctx->isc_nrxqsets = 1;
4722 		scctx->isc_intr = IFLIB_INTR_LEGACY;
4723 		msix = 0;
4724 	}
4725 	/* Get memory for the station queues */
4726 	if ((err = iflib_queues_alloc(ctx))) {
4727 		device_printf(dev, "Unable to allocate queue memory\n");
4728 		goto fail_intr_free;
4729 	}
4730 
4731 	if ((err = iflib_qset_structures_setup(ctx)))
4732 		goto fail_queues;
4733 
4734 	/*
4735 	 * Now that we know how many queues there are, get the core offset.
4736 	 */
4737 	ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
4738 
4739 	if (msix > 1) {
4740 		/*
4741 		 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
4742 		 * aren't the default NULL implementation.
4743 		 */
4744 		kobj_desc = &ifdi_rx_queue_intr_enable_desc;
4745 		kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4746 		    kobj_desc);
4747 		if (kobj_method == &kobj_desc->deflt) {
4748 			device_printf(dev,
4749 			    "MSI-X requires ifdi_rx_queue_intr_enable method");
4750 			err = EOPNOTSUPP;
4751 			goto fail_queues;
4752 		}
4753 		kobj_desc = &ifdi_tx_queue_intr_enable_desc;
4754 		kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
4755 		    kobj_desc);
4756 		if (kobj_method == &kobj_desc->deflt) {
4757 			device_printf(dev,
4758 			    "MSI-X requires ifdi_tx_queue_intr_enable method");
4759 			err = EOPNOTSUPP;
4760 			goto fail_queues;
4761 		}
4762 
4763 		/*
4764 		 * Assign the MSI-X vectors.
4765 		 * Note that the default NULL ifdi_msix_intr_assign method will
4766 		 * fail here, too.
4767 		 */
4768 		err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
4769 		if (err != 0) {
4770 			device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
4771 			    err);
4772 			goto fail_queues;
4773 		}
4774 	} else if (scctx->isc_intr != IFLIB_INTR_MSIX) {
4775 		rid = 0;
4776 		if (scctx->isc_intr == IFLIB_INTR_MSI) {
4777 			MPASS(msix == 1);
4778 			rid = 1;
4779 		}
4780 		if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
4781 			device_printf(dev, "iflib_legacy_setup failed %d\n", err);
4782 			goto fail_queues;
4783 		}
4784 	} else {
4785 		device_printf(dev,
4786 		    "Cannot use iflib with only 1 MSI-X interrupt!\n");
4787 		err = ENODEV;
4788 		goto fail_intr_free;
4789 	}
4790 
4791 	ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4792 
4793 	if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4794 		device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4795 		goto fail_detach;
4796 	}
4797 
4798 	/*
4799 	 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4800 	 * This must appear after the call to ether_ifattach() because
4801 	 * ether_ifattach() sets if_hdrlen to the default value.
4802 	 */
4803 	if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4804 		if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
4805 
4806 	if ((err = iflib_netmap_attach(ctx))) {
4807 		device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
4808 		goto fail_detach;
4809 	}
4810 	*ctxp = ctx;
4811 
4812 	DEBUGNET_SET(ctx->ifc_ifp, iflib);
4813 
4814 	if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4815 	iflib_add_device_sysctl_post(ctx);
4816 	iflib_add_pfil(ctx);
4817 	ctx->ifc_flags |= IFC_INIT_DONE;
4818 	CTX_UNLOCK(ctx);
4819 
4820 	return (0);
4821 
4822 fail_detach:
4823 	ether_ifdetach(ctx->ifc_ifp);
4824 fail_intr_free:
4825 	iflib_free_intr_mem(ctx);
4826 fail_queues:
4827 	iflib_tx_structures_free(ctx);
4828 	iflib_rx_structures_free(ctx);
4829 	taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task);
4830 	IFDI_DETACH(ctx);
4831 fail_unlock:
4832 	CTX_UNLOCK(ctx);
4833 	iflib_deregister(ctx);
4834 fail_ctx_free:
4835 	device_set_softc(ctx->ifc_dev, NULL);
4836         if (ctx->ifc_flags & IFC_SC_ALLOCATED)
4837                 free(ctx->ifc_softc, M_IFLIB);
4838         free(ctx, M_IFLIB);
4839 	return (err);
4840 }
4841 
4842 int
4843 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp,
4844 					  struct iflib_cloneattach_ctx *clctx)
4845 {
4846 	int num_txd, num_rxd;
4847 	int err;
4848 	if_ctx_t ctx;
4849 	if_t ifp;
4850 	if_softc_ctx_t scctx;
4851 	int i;
4852 	void *sc;
4853 
4854 	ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO);
4855 	sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO);
4856 	ctx->ifc_flags |= IFC_SC_ALLOCATED;
4857 	if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL))
4858 		ctx->ifc_flags |= IFC_PSEUDO;
4859 
4860 	ctx->ifc_sctx = sctx;
4861 	ctx->ifc_softc = sc;
4862 	ctx->ifc_dev = dev;
4863 
4864 	if ((err = iflib_register(ctx)) != 0) {
4865 		device_printf(dev, "%s: iflib_register failed %d\n", __func__, err);
4866 		goto fail_ctx_free;
4867 	}
4868 	iflib_add_device_sysctl_pre(ctx);
4869 
4870 	scctx = &ctx->ifc_softc_ctx;
4871 	ifp = ctx->ifc_ifp;
4872 
4873 	iflib_reset_qvalues(ctx);
4874 	CTX_LOCK(ctx);
4875 	if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
4876 		device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
4877 		goto fail_unlock;
4878 	}
4879 	if (sctx->isc_flags & IFLIB_GEN_MAC)
4880 		ether_gen_addr(ifp, &ctx->ifc_mac);
4881 	if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name,
4882 								clctx->cc_params)) != 0) {
4883 		device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err);
4884 		goto fail_unlock;
4885 	}
4886 #ifdef INVARIANTS
4887 	if (scctx->isc_capabilities & IFCAP_TXCSUM)
4888 		MPASS(scctx->isc_tx_csum_flags);
4889 #endif
4890 
4891 	if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4892 	if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE);
4893 
4894 	ifp->if_flags |= IFF_NOGROUP;
4895 	if (sctx->isc_flags & IFLIB_PSEUDO) {
4896 		ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4897 		ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4898 		if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) {
4899 			ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4900 		} else {
4901 			if_attach(ctx->ifc_ifp);
4902 			bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t));
4903 		}
4904 
4905 		if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
4906 			device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
4907 			goto fail_detach;
4908 		}
4909 		*ctxp = ctx;
4910 
4911 		/*
4912 		 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
4913 		 * This must appear after the call to ether_ifattach() because
4914 		 * ether_ifattach() sets if_hdrlen to the default value.
4915 		 */
4916 		if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
4917 			if_setifheaderlen(ifp,
4918 			    sizeof(struct ether_vlan_header));
4919 
4920 		if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
4921 		iflib_add_device_sysctl_post(ctx);
4922 		ctx->ifc_flags |= IFC_INIT_DONE;
4923 		CTX_UNLOCK(ctx);
4924 		return (0);
4925 	}
4926 	ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
4927 	ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL);
4928 	ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO);
4929 
4930 	_iflib_pre_assert(scctx);
4931 	ctx->ifc_txrx = *scctx->isc_txrx;
4932 
4933 	if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
4934 		scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
4935 	if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
4936 		scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
4937 
4938 	num_txd = iflib_num_tx_descs(ctx);
4939 	num_rxd = iflib_num_rx_descs(ctx);
4940 
4941 	/* XXX change for per-queue sizes */
4942 	device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
4943 	    num_txd, num_rxd);
4944 
4945 	if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
4946 		scctx->isc_tx_nsegments = max(1, num_txd /
4947 		    MAX_SINGLE_PACKET_FRACTION);
4948 	if (scctx->isc_tx_tso_segments_max > num_txd /
4949 	    MAX_SINGLE_PACKET_FRACTION)
4950 		scctx->isc_tx_tso_segments_max = max(1,
4951 		    num_txd / MAX_SINGLE_PACKET_FRACTION);
4952 
4953 	/* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
4954 	if (if_getcapabilities(ifp) & IFCAP_TSO) {
4955 		/*
4956 		 * The stack can't handle a TSO size larger than IP_MAXPACKET,
4957 		 * but some MACs do.
4958 		 */
4959 		if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
4960 		    IP_MAXPACKET));
4961 		/*
4962 		 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
4963 		 * into account.  In the worst case, each of these calls will
4964 		 * add another mbuf and, thus, the requirement for another DMA
4965 		 * segment.  So for best performance, it doesn't make sense to
4966 		 * advertize a maximum of TSO segments that typically will
4967 		 * require defragmentation in iflib_encap().
4968 		 */
4969 		if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
4970 		if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
4971 	}
4972 	if (scctx->isc_rss_table_size == 0)
4973 		scctx->isc_rss_table_size = 64;
4974 	scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;
4975 
4976 	GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
4977 	/* XXX format name */
4978 	taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx,
4979 	    NULL, NULL, "admin");
4980 
4981 	/* XXX --- can support > 1 -- but keep it simple for now */
4982 	scctx->isc_intr = IFLIB_INTR_LEGACY;
4983 
4984 	/* Get memory for the station queues */
4985 	if ((err = iflib_queues_alloc(ctx))) {
4986 		device_printf(dev, "Unable to allocate queue memory\n");
4987 		goto fail_iflib_detach;
4988 	}
4989 
4990 	if ((err = iflib_qset_structures_setup(ctx))) {
4991 		device_printf(dev, "qset structure setup failed %d\n", err);
4992 		goto fail_queues;
4993 	}
4994 
4995 	/*
4996 	 * XXX What if anything do we want to do about interrupts?
4997 	 */
4998 	ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
4999 	if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
5000 		device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
5001 		goto fail_detach;
5002 	}
5003 
5004 	/*
5005 	 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5006 	 * This must appear after the call to ether_ifattach() because
5007 	 * ether_ifattach() sets if_hdrlen to the default value.
5008 	 */
5009 	if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5010 		if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
5011 
5012 	/* XXX handle more than one queue */
5013 	for (i = 0; i < scctx->isc_nrxqsets; i++)
5014 		IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl);
5015 
5016 	*ctxp = ctx;
5017 
5018 	if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter);
5019 	iflib_add_device_sysctl_post(ctx);
5020 	ctx->ifc_flags |= IFC_INIT_DONE;
5021 	CTX_UNLOCK(ctx);
5022 
5023 	return (0);
5024 fail_detach:
5025 	ether_ifdetach(ctx->ifc_ifp);
5026 fail_queues:
5027 	iflib_tx_structures_free(ctx);
5028 	iflib_rx_structures_free(ctx);
5029 fail_iflib_detach:
5030 	IFDI_DETACH(ctx);
5031 fail_unlock:
5032 	CTX_UNLOCK(ctx);
5033 	iflib_deregister(ctx);
5034 fail_ctx_free:
5035 	free(ctx->ifc_softc, M_IFLIB);
5036 	free(ctx, M_IFLIB);
5037 	return (err);
5038 }
5039 
5040 int
5041 iflib_pseudo_deregister(if_ctx_t ctx)
5042 {
5043 	if_t ifp = ctx->ifc_ifp;
5044 	if_shared_ctx_t sctx = ctx->ifc_sctx;
5045 	iflib_txq_t txq;
5046 	iflib_rxq_t rxq;
5047 	int i, j;
5048 	struct taskqgroup *tqg;
5049 	iflib_fl_t fl;
5050 
5051 	/* Unregister VLAN event handlers early */
5052 	iflib_unregister_vlan_handlers(ctx);
5053 
5054 	if ((sctx->isc_flags & IFLIB_PSEUDO)  &&
5055 		(sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) {
5056 		bpfdetach(ifp);
5057 		if_detach(ifp);
5058 	} else {
5059 		ether_ifdetach(ifp);
5060 	}
5061 	/* XXX drain any dependent tasks */
5062 	tqg = qgroup_if_io_tqg;
5063 	for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5064 		callout_drain(&txq->ift_timer);
5065 		if (txq->ift_task.gt_uniq != NULL)
5066 			taskqgroup_detach(tqg, &txq->ift_task);
5067 	}
5068 	for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5069 		callout_drain(&rxq->ifr_watchdog);
5070 		if (rxq->ifr_task.gt_uniq != NULL)
5071 			taskqgroup_detach(tqg, &rxq->ifr_task);
5072 
5073 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5074 			free(fl->ifl_rx_bitmap, M_IFLIB);
5075 	}
5076 	tqg = qgroup_if_config_tqg;
5077 	if (ctx->ifc_admin_task.gt_uniq != NULL)
5078 		taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5079 	if (ctx->ifc_vflr_task.gt_uniq != NULL)
5080 		taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5081 
5082 	iflib_tx_structures_free(ctx);
5083 	iflib_rx_structures_free(ctx);
5084 
5085 	iflib_deregister(ctx);
5086 
5087 	if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5088 		free(ctx->ifc_softc, M_IFLIB);
5089 	free(ctx, M_IFLIB);
5090 	return (0);
5091 }
5092 
5093 int
5094 iflib_device_attach(device_t dev)
5095 {
5096 	if_ctx_t ctx;
5097 	if_shared_ctx_t sctx;
5098 
5099 	if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5100 		return (ENOTSUP);
5101 
5102 	pci_enable_busmaster(dev);
5103 
5104 	return (iflib_device_register(dev, NULL, sctx, &ctx));
5105 }
5106 
5107 int
5108 iflib_device_deregister(if_ctx_t ctx)
5109 {
5110 	if_t ifp = ctx->ifc_ifp;
5111 	iflib_txq_t txq;
5112 	iflib_rxq_t rxq;
5113 	device_t dev = ctx->ifc_dev;
5114 	int i, j;
5115 	struct taskqgroup *tqg;
5116 	iflib_fl_t fl;
5117 
5118 	/* Make sure VLANS are not using driver */
5119 	if (if_vlantrunkinuse(ifp)) {
5120 		device_printf(dev, "Vlan in use, detach first\n");
5121 		return (EBUSY);
5122 	}
5123 #ifdef PCI_IOV
5124 	if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5125 		device_printf(dev, "SR-IOV in use; detach first.\n");
5126 		return (EBUSY);
5127 	}
5128 #endif
5129 
5130 	STATE_LOCK(ctx);
5131 	ctx->ifc_flags |= IFC_IN_DETACH;
5132 	STATE_UNLOCK(ctx);
5133 
5134 	/* Unregister VLAN handlers before calling iflib_stop() */
5135 	iflib_unregister_vlan_handlers(ctx);
5136 
5137 	iflib_netmap_detach(ifp);
5138 	ether_ifdetach(ifp);
5139 
5140 	CTX_LOCK(ctx);
5141 	iflib_stop(ctx);
5142 	CTX_UNLOCK(ctx);
5143 
5144 	iflib_rem_pfil(ctx);
5145 	if (ctx->ifc_led_dev != NULL)
5146 		led_destroy(ctx->ifc_led_dev);
5147 	/* XXX drain any dependent tasks */
5148 	tqg = qgroup_if_io_tqg;
5149 	for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5150 		callout_drain(&txq->ift_timer);
5151 		if (txq->ift_task.gt_uniq != NULL)
5152 			taskqgroup_detach(tqg, &txq->ift_task);
5153 	}
5154 	for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5155 		if (rxq->ifr_task.gt_uniq != NULL)
5156 			taskqgroup_detach(tqg, &rxq->ifr_task);
5157 
5158 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5159 			free(fl->ifl_rx_bitmap, M_IFLIB);
5160 	}
5161 	tqg = qgroup_if_config_tqg;
5162 	if (ctx->ifc_admin_task.gt_uniq != NULL)
5163 		taskqgroup_detach(tqg, &ctx->ifc_admin_task);
5164 	if (ctx->ifc_vflr_task.gt_uniq != NULL)
5165 		taskqgroup_detach(tqg, &ctx->ifc_vflr_task);
5166 	CTX_LOCK(ctx);
5167 	IFDI_DETACH(ctx);
5168 	CTX_UNLOCK(ctx);
5169 
5170 	/* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5171 	iflib_free_intr_mem(ctx);
5172 
5173 	bus_generic_detach(dev);
5174 
5175 	iflib_tx_structures_free(ctx);
5176 	iflib_rx_structures_free(ctx);
5177 
5178 	iflib_deregister(ctx);
5179 
5180 	device_set_softc(ctx->ifc_dev, NULL);
5181 	if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5182 		free(ctx->ifc_softc, M_IFLIB);
5183 	unref_ctx_core_offset(ctx);
5184 	free(ctx, M_IFLIB);
5185 	return (0);
5186 }
5187 
5188 static void
5189 iflib_free_intr_mem(if_ctx_t ctx)
5190 {
5191 
5192 	if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5193 		iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5194 	}
5195 	if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5196 		pci_release_msi(ctx->ifc_dev);
5197 	}
5198 	if (ctx->ifc_msix_mem != NULL) {
5199 		bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5200 		    rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5201 		ctx->ifc_msix_mem = NULL;
5202 	}
5203 }
5204 
5205 int
5206 iflib_device_detach(device_t dev)
5207 {
5208 	if_ctx_t ctx = device_get_softc(dev);
5209 
5210 	return (iflib_device_deregister(ctx));
5211 }
5212 
5213 int
5214 iflib_device_suspend(device_t dev)
5215 {
5216 	if_ctx_t ctx = device_get_softc(dev);
5217 
5218 	CTX_LOCK(ctx);
5219 	IFDI_SUSPEND(ctx);
5220 	CTX_UNLOCK(ctx);
5221 
5222 	return bus_generic_suspend(dev);
5223 }
5224 int
5225 iflib_device_shutdown(device_t dev)
5226 {
5227 	if_ctx_t ctx = device_get_softc(dev);
5228 
5229 	CTX_LOCK(ctx);
5230 	IFDI_SHUTDOWN(ctx);
5231 	CTX_UNLOCK(ctx);
5232 
5233 	return bus_generic_suspend(dev);
5234 }
5235 
5236 
5237 int
5238 iflib_device_resume(device_t dev)
5239 {
5240 	if_ctx_t ctx = device_get_softc(dev);
5241 	iflib_txq_t txq = ctx->ifc_txqs;
5242 
5243 	CTX_LOCK(ctx);
5244 	IFDI_RESUME(ctx);
5245 	iflib_if_init_locked(ctx);
5246 	CTX_UNLOCK(ctx);
5247 	for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5248 		iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5249 
5250 	return (bus_generic_resume(dev));
5251 }
5252 
5253 int
5254 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5255 {
5256 	int error;
5257 	if_ctx_t ctx = device_get_softc(dev);
5258 
5259 	CTX_LOCK(ctx);
5260 	error = IFDI_IOV_INIT(ctx, num_vfs, params);
5261 	CTX_UNLOCK(ctx);
5262 
5263 	return (error);
5264 }
5265 
5266 void
5267 iflib_device_iov_uninit(device_t dev)
5268 {
5269 	if_ctx_t ctx = device_get_softc(dev);
5270 
5271 	CTX_LOCK(ctx);
5272 	IFDI_IOV_UNINIT(ctx);
5273 	CTX_UNLOCK(ctx);
5274 }
5275 
5276 int
5277 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5278 {
5279 	int error;
5280 	if_ctx_t ctx = device_get_softc(dev);
5281 
5282 	CTX_LOCK(ctx);
5283 	error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5284 	CTX_UNLOCK(ctx);
5285 
5286 	return (error);
5287 }
5288 
5289 /*********************************************************************
5290  *
5291  *  MODULE FUNCTION DEFINITIONS
5292  *
5293  **********************************************************************/
5294 
5295 /*
5296  * - Start a fast taskqueue thread for each core
5297  * - Start a taskqueue for control operations
5298  */
5299 static int
5300 iflib_module_init(void)
5301 {
5302 	return (0);
5303 }
5304 
5305 static int
5306 iflib_module_event_handler(module_t mod, int what, void *arg)
5307 {
5308 	int err;
5309 
5310 	switch (what) {
5311 	case MOD_LOAD:
5312 		if ((err = iflib_module_init()) != 0)
5313 			return (err);
5314 		break;
5315 	case MOD_UNLOAD:
5316 		return (EBUSY);
5317 	default:
5318 		return (EOPNOTSUPP);
5319 	}
5320 
5321 	return (0);
5322 }
5323 
5324 /*********************************************************************
5325  *
5326  *  PUBLIC FUNCTION DEFINITIONS
5327  *     ordered as in iflib.h
5328  *
5329  **********************************************************************/
5330 
5331 
5332 static void
5333 _iflib_assert(if_shared_ctx_t sctx)
5334 {
5335 	int i;
5336 
5337 	MPASS(sctx->isc_tx_maxsize);
5338 	MPASS(sctx->isc_tx_maxsegsize);
5339 
5340 	MPASS(sctx->isc_rx_maxsize);
5341 	MPASS(sctx->isc_rx_nsegments);
5342 	MPASS(sctx->isc_rx_maxsegsize);
5343 
5344 	MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5345 	for (i = 0; i < sctx->isc_nrxqs; i++) {
5346 		MPASS(sctx->isc_nrxd_min[i]);
5347 		MPASS(powerof2(sctx->isc_nrxd_min[i]));
5348 		MPASS(sctx->isc_nrxd_max[i]);
5349 		MPASS(powerof2(sctx->isc_nrxd_max[i]));
5350 		MPASS(sctx->isc_nrxd_default[i]);
5351 		MPASS(powerof2(sctx->isc_nrxd_default[i]));
5352 	}
5353 
5354 	MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5355 	for (i = 0; i < sctx->isc_ntxqs; i++) {
5356 		MPASS(sctx->isc_ntxd_min[i]);
5357 		MPASS(powerof2(sctx->isc_ntxd_min[i]));
5358 		MPASS(sctx->isc_ntxd_max[i]);
5359 		MPASS(powerof2(sctx->isc_ntxd_max[i]));
5360 		MPASS(sctx->isc_ntxd_default[i]);
5361 		MPASS(powerof2(sctx->isc_ntxd_default[i]));
5362 	}
5363 }
5364 
5365 static void
5366 _iflib_pre_assert(if_softc_ctx_t scctx)
5367 {
5368 
5369 	MPASS(scctx->isc_txrx->ift_txd_encap);
5370 	MPASS(scctx->isc_txrx->ift_txd_flush);
5371 	MPASS(scctx->isc_txrx->ift_txd_credits_update);
5372 	MPASS(scctx->isc_txrx->ift_rxd_available);
5373 	MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5374 	MPASS(scctx->isc_txrx->ift_rxd_refill);
5375 	MPASS(scctx->isc_txrx->ift_rxd_flush);
5376 }
5377 
5378 static int
5379 iflib_register(if_ctx_t ctx)
5380 {
5381 	if_shared_ctx_t sctx = ctx->ifc_sctx;
5382 	driver_t *driver = sctx->isc_driver;
5383 	device_t dev = ctx->ifc_dev;
5384 	if_t ifp;
5385 	u_char type;
5386 	int iflags;
5387 
5388 	if ((sctx->isc_flags & IFLIB_PSEUDO) == 0)
5389 		_iflib_assert(sctx);
5390 
5391 	CTX_LOCK_INIT(ctx);
5392 	STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5393 	if (sctx->isc_flags & IFLIB_PSEUDO) {
5394 		if (sctx->isc_flags & IFLIB_PSEUDO_ETHER)
5395 			type = IFT_ETHER;
5396 		else
5397 			type = IFT_PPP;
5398 	} else
5399 		type = IFT_ETHER;
5400 	ifp = ctx->ifc_ifp = if_alloc(type);
5401 	if (ifp == NULL) {
5402 		device_printf(dev, "can not allocate ifnet structure\n");
5403 		return (ENOMEM);
5404 	}
5405 
5406 	/*
5407 	 * Initialize our context's device specific methods
5408 	 */
5409 	kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5410 	kobj_class_compile((kobj_class_t) driver);
5411 
5412 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5413 	if_setsoftc(ifp, ctx);
5414 	if_setdev(ifp, dev);
5415 	if_setinitfn(ifp, iflib_if_init);
5416 	if_setioctlfn(ifp, iflib_if_ioctl);
5417 #ifdef ALTQ
5418 	if_setstartfn(ifp, iflib_altq_if_start);
5419 	if_settransmitfn(ifp, iflib_altq_if_transmit);
5420 	if_setsendqready(ifp);
5421 #else
5422 	if_settransmitfn(ifp, iflib_if_transmit);
5423 #endif
5424 	if_setqflushfn(ifp, iflib_if_qflush);
5425 	iflags = IFF_MULTICAST | IFF_KNOWSEPOCH;
5426 
5427 	if ((sctx->isc_flags & IFLIB_PSEUDO) &&
5428 		(sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0)
5429 		iflags |= IFF_POINTOPOINT;
5430 	else
5431 		iflags |= IFF_BROADCAST | IFF_SIMPLEX;
5432 	if_setflags(ifp, iflags);
5433 	ctx->ifc_vlan_attach_event =
5434 		EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5435 							  EVENTHANDLER_PRI_FIRST);
5436 	ctx->ifc_vlan_detach_event =
5437 		EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5438 							  EVENTHANDLER_PRI_FIRST);
5439 
5440 	if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
5441 		ctx->ifc_mediap = &ctx->ifc_media;
5442 		ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
5443 		    iflib_media_change, iflib_media_status);
5444 	}
5445 	return (0);
5446 }
5447 
5448 static void
5449 iflib_unregister_vlan_handlers(if_ctx_t ctx)
5450 {
5451 	/* Unregister VLAN events */
5452 	if (ctx->ifc_vlan_attach_event != NULL) {
5453 		EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5454 		ctx->ifc_vlan_attach_event = NULL;
5455 	}
5456 	if (ctx->ifc_vlan_detach_event != NULL) {
5457 		EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5458 		ctx->ifc_vlan_detach_event = NULL;
5459 	}
5460 
5461 }
5462 
5463 static void
5464 iflib_deregister(if_ctx_t ctx)
5465 {
5466 	if_t ifp = ctx->ifc_ifp;
5467 
5468 	/* Remove all media */
5469 	ifmedia_removeall(&ctx->ifc_media);
5470 
5471 	/* Ensure that VLAN event handlers are unregistered */
5472 	iflib_unregister_vlan_handlers(ctx);
5473 
5474 	/* Release kobject reference */
5475 	kobj_delete((kobj_t) ctx, NULL);
5476 
5477 	/* Free the ifnet structure */
5478 	if_free(ifp);
5479 
5480 	STATE_LOCK_DESTROY(ctx);
5481 
5482 	/* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5483 	CTX_LOCK_DESTROY(ctx);
5484 }
5485 
5486 static int
5487 iflib_queues_alloc(if_ctx_t ctx)
5488 {
5489 	if_shared_ctx_t sctx = ctx->ifc_sctx;
5490 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5491 	device_t dev = ctx->ifc_dev;
5492 	int nrxqsets = scctx->isc_nrxqsets;
5493 	int ntxqsets = scctx->isc_ntxqsets;
5494 	iflib_txq_t txq;
5495 	iflib_rxq_t rxq;
5496 	iflib_fl_t fl = NULL;
5497 	int i, j, cpu, err, txconf, rxconf;
5498 	iflib_dma_info_t ifdip;
5499 	uint32_t *rxqsizes = scctx->isc_rxqsizes;
5500 	uint32_t *txqsizes = scctx->isc_txqsizes;
5501 	uint8_t nrxqs = sctx->isc_nrxqs;
5502 	uint8_t ntxqs = sctx->isc_ntxqs;
5503 	int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5504 	caddr_t *vaddrs;
5505 	uint64_t *paddrs;
5506 
5507 	KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5508 	KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5509 
5510 	/* Allocate the TX ring struct memory */
5511 	if (!(ctx->ifc_txqs =
5512 	    (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5513 	    ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5514 		device_printf(dev, "Unable to allocate TX ring memory\n");
5515 		err = ENOMEM;
5516 		goto fail;
5517 	}
5518 
5519 	/* Now allocate the RX */
5520 	if (!(ctx->ifc_rxqs =
5521 	    (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5522 	    nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5523 		device_printf(dev, "Unable to allocate RX ring memory\n");
5524 		err = ENOMEM;
5525 		goto rx_fail;
5526 	}
5527 
5528 	txq = ctx->ifc_txqs;
5529 	rxq = ctx->ifc_rxqs;
5530 
5531 	/*
5532 	 * XXX handle allocation failure
5533 	 */
5534 	for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5535 		/* Set up some basics */
5536 
5537 		if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5538 		    M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5539 			device_printf(dev,
5540 			    "Unable to allocate TX DMA info memory\n");
5541 			err = ENOMEM;
5542 			goto err_tx_desc;
5543 		}
5544 		txq->ift_ifdi = ifdip;
5545 		for (j = 0; j < ntxqs; j++, ifdip++) {
5546 			if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5547 				device_printf(dev,
5548 				    "Unable to allocate TX descriptors\n");
5549 				err = ENOMEM;
5550 				goto err_tx_desc;
5551 			}
5552 			txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5553 			bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5554 		}
5555 		txq->ift_ctx = ctx;
5556 		txq->ift_id = i;
5557 		if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5558 			txq->ift_br_offset = 1;
5559 		} else {
5560 			txq->ift_br_offset = 0;
5561 		}
5562 		/* XXX fix this */
5563 		txq->ift_timer.c_cpu = cpu;
5564 
5565 		if (iflib_txsd_alloc(txq)) {
5566 			device_printf(dev, "Critical Failure setting up TX buffers\n");
5567 			err = ENOMEM;
5568 			goto err_tx_desc;
5569 		}
5570 
5571 		/* Initialize the TX lock */
5572 		snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
5573 		    device_get_nameunit(dev), txq->ift_id);
5574 		mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5575 		callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5576 
5577 		err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5578 				      iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5579 		if (err) {
5580 			/* XXX free any allocated rings */
5581 			device_printf(dev, "Unable to allocate buf_ring\n");
5582 			goto err_tx_desc;
5583 		}
5584 	}
5585 
5586 	for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5587 		/* Set up some basics */
5588 		callout_init(&rxq->ifr_watchdog, 1);
5589 
5590 		if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5591 		   M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5592 			device_printf(dev,
5593 			    "Unable to allocate RX DMA info memory\n");
5594 			err = ENOMEM;
5595 			goto err_tx_desc;
5596 		}
5597 
5598 		rxq->ifr_ifdi = ifdip;
5599 		/* XXX this needs to be changed if #rx queues != #tx queues */
5600 		rxq->ifr_ntxqirq = 1;
5601 		rxq->ifr_txqid[0] = i;
5602 		for (j = 0; j < nrxqs; j++, ifdip++) {
5603 			if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5604 				device_printf(dev,
5605 				    "Unable to allocate RX descriptors\n");
5606 				err = ENOMEM;
5607 				goto err_tx_desc;
5608 			}
5609 			bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5610 		}
5611 		rxq->ifr_ctx = ctx;
5612 		rxq->ifr_id = i;
5613 		if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
5614 			rxq->ifr_fl_offset = 1;
5615 		} else {
5616 			rxq->ifr_fl_offset = 0;
5617 		}
5618 		rxq->ifr_nfl = nfree_lists;
5619 		if (!(fl =
5620 			  (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5621 			device_printf(dev, "Unable to allocate free list memory\n");
5622 			err = ENOMEM;
5623 			goto err_tx_desc;
5624 		}
5625 		rxq->ifr_fl = fl;
5626 		for (j = 0; j < nfree_lists; j++) {
5627 			fl[j].ifl_rxq = rxq;
5628 			fl[j].ifl_id = j;
5629 			fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5630 			fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5631 		}
5632 		/* Allocate receive buffers for the ring */
5633 		if (iflib_rxsd_alloc(rxq)) {
5634 			device_printf(dev,
5635 			    "Critical Failure setting up receive buffers\n");
5636 			err = ENOMEM;
5637 			goto err_rx_desc;
5638 		}
5639 
5640 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5641 			fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5642 			    M_WAITOK);
5643 	}
5644 
5645 	/* TXQs */
5646 	vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5647 	paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK);
5648 	for (i = 0; i < ntxqsets; i++) {
5649 		iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5650 
5651 		for (j = 0; j < ntxqs; j++, di++) {
5652 			vaddrs[i*ntxqs + j] = di->idi_vaddr;
5653 			paddrs[i*ntxqs + j] = di->idi_paddr;
5654 		}
5655 	}
5656 	if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5657 		device_printf(ctx->ifc_dev,
5658 		    "Unable to allocate device TX queue\n");
5659 		iflib_tx_structures_free(ctx);
5660 		free(vaddrs, M_IFLIB);
5661 		free(paddrs, M_IFLIB);
5662 		goto err_rx_desc;
5663 	}
5664 	free(vaddrs, M_IFLIB);
5665 	free(paddrs, M_IFLIB);
5666 
5667 	/* RXQs */
5668 	vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5669 	paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK);
5670 	for (i = 0; i < nrxqsets; i++) {
5671 		iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5672 
5673 		for (j = 0; j < nrxqs; j++, di++) {
5674 			vaddrs[i*nrxqs + j] = di->idi_vaddr;
5675 			paddrs[i*nrxqs + j] = di->idi_paddr;
5676 		}
5677 	}
5678 	if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5679 		device_printf(ctx->ifc_dev,
5680 		    "Unable to allocate device RX queue\n");
5681 		iflib_tx_structures_free(ctx);
5682 		free(vaddrs, M_IFLIB);
5683 		free(paddrs, M_IFLIB);
5684 		goto err_rx_desc;
5685 	}
5686 	free(vaddrs, M_IFLIB);
5687 	free(paddrs, M_IFLIB);
5688 
5689 	return (0);
5690 
5691 /* XXX handle allocation failure changes */
5692 err_rx_desc:
5693 err_tx_desc:
5694 rx_fail:
5695 	if (ctx->ifc_rxqs != NULL)
5696 		free(ctx->ifc_rxqs, M_IFLIB);
5697 	ctx->ifc_rxqs = NULL;
5698 	if (ctx->ifc_txqs != NULL)
5699 		free(ctx->ifc_txqs, M_IFLIB);
5700 	ctx->ifc_txqs = NULL;
5701 fail:
5702 	return (err);
5703 }
5704 
5705 static int
5706 iflib_tx_structures_setup(if_ctx_t ctx)
5707 {
5708 	iflib_txq_t txq = ctx->ifc_txqs;
5709 	int i;
5710 
5711 	for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5712 		iflib_txq_setup(txq);
5713 
5714 	return (0);
5715 }
5716 
5717 static void
5718 iflib_tx_structures_free(if_ctx_t ctx)
5719 {
5720 	iflib_txq_t txq = ctx->ifc_txqs;
5721 	if_shared_ctx_t sctx = ctx->ifc_sctx;
5722 	int i, j;
5723 
5724 	for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5725 		for (j = 0; j < sctx->isc_ntxqs; j++)
5726 			iflib_dma_free(&txq->ift_ifdi[j]);
5727 		iflib_txq_destroy(txq);
5728 	}
5729 	free(ctx->ifc_txqs, M_IFLIB);
5730 	ctx->ifc_txqs = NULL;
5731 	IFDI_QUEUES_FREE(ctx);
5732 }
5733 
5734 /*********************************************************************
5735  *
5736  *  Initialize all receive rings.
5737  *
5738  **********************************************************************/
5739 static int
5740 iflib_rx_structures_setup(if_ctx_t ctx)
5741 {
5742 	iflib_rxq_t rxq = ctx->ifc_rxqs;
5743 	int q;
5744 #if defined(INET6) || defined(INET)
5745 	int err, i;
5746 #endif
5747 
5748 	for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5749 #if defined(INET6) || defined(INET)
5750 		if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) {
5751 			err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5752 			    TCP_LRO_ENTRIES, min(1024,
5753 			    ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
5754 			if (err != 0) {
5755 				device_printf(ctx->ifc_dev,
5756 				    "LRO Initialization failed!\n");
5757 				goto fail;
5758 			}
5759 		}
5760 #endif
5761 		IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5762 	}
5763 	return (0);
5764 #if defined(INET6) || defined(INET)
5765 fail:
5766 	/*
5767 	 * Free LRO resources allocated so far, we will only handle
5768 	 * the rings that completed, the failing case will have
5769 	 * cleaned up for itself.  'q' failed, so its the terminus.
5770 	 */
5771 	rxq = ctx->ifc_rxqs;
5772 	for (i = 0; i < q; ++i, rxq++) {
5773 		if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5774 			tcp_lro_free(&rxq->ifr_lc);
5775 	}
5776 	return (err);
5777 #endif
5778 }
5779 
5780 /*********************************************************************
5781  *
5782  *  Free all receive rings.
5783  *
5784  **********************************************************************/
5785 static void
5786 iflib_rx_structures_free(if_ctx_t ctx)
5787 {
5788 	iflib_rxq_t rxq = ctx->ifc_rxqs;
5789 	if_shared_ctx_t sctx = ctx->ifc_sctx;
5790 	int i, j;
5791 
5792 	for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5793 		for (j = 0; j < sctx->isc_nrxqs; j++)
5794 			iflib_dma_free(&rxq->ifr_ifdi[j]);
5795 		iflib_rx_sds_free(rxq);
5796 #if defined(INET6) || defined(INET)
5797 		if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO)
5798 			tcp_lro_free(&rxq->ifr_lc);
5799 #endif
5800 	}
5801 	free(ctx->ifc_rxqs, M_IFLIB);
5802 	ctx->ifc_rxqs = NULL;
5803 }
5804 
5805 static int
5806 iflib_qset_structures_setup(if_ctx_t ctx)
5807 {
5808 	int err;
5809 
5810 	/*
5811 	 * It is expected that the caller takes care of freeing queues if this
5812 	 * fails.
5813 	 */
5814 	if ((err = iflib_tx_structures_setup(ctx)) != 0) {
5815 		device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
5816 		return (err);
5817 	}
5818 
5819 	if ((err = iflib_rx_structures_setup(ctx)) != 0)
5820 		device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
5821 
5822 	return (err);
5823 }
5824 
5825 int
5826 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
5827 		driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
5828 {
5829 
5830 	return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
5831 }
5832 
5833 #ifdef SMP
5834 static int
5835 find_nth(if_ctx_t ctx, int qid)
5836 {
5837 	cpuset_t cpus;
5838 	int i, cpuid, eqid, count;
5839 
5840 	CPU_COPY(&ctx->ifc_cpus, &cpus);
5841 	count = CPU_COUNT(&cpus);
5842 	eqid = qid % count;
5843 	/* clear up to the qid'th bit */
5844 	for (i = 0; i < eqid; i++) {
5845 		cpuid = CPU_FFS(&cpus);
5846 		MPASS(cpuid != 0);
5847 		CPU_CLR(cpuid-1, &cpus);
5848 	}
5849 	cpuid = CPU_FFS(&cpus);
5850 	MPASS(cpuid != 0);
5851 	return (cpuid-1);
5852 }
5853 
5854 #ifdef SCHED_ULE
5855 extern struct cpu_group *cpu_top;              /* CPU topology */
5856 
5857 static int
5858 find_child_with_core(int cpu, struct cpu_group *grp)
5859 {
5860 	int i;
5861 
5862 	if (grp->cg_children == 0)
5863 		return -1;
5864 
5865 	MPASS(grp->cg_child);
5866 	for (i = 0; i < grp->cg_children; i++) {
5867 		if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask))
5868 			return i;
5869 	}
5870 
5871 	return -1;
5872 }
5873 
5874 /*
5875  * Find the nth "close" core to the specified core
5876  * "close" is defined as the deepest level that shares
5877  * at least an L2 cache.  With threads, this will be
5878  * threads on the same core.  If the shared cache is L3
5879  * or higher, simply returns the same core.
5880  */
5881 static int
5882 find_close_core(int cpu, int core_offset)
5883 {
5884 	struct cpu_group *grp;
5885 	int i;
5886 	int fcpu;
5887 	cpuset_t cs;
5888 
5889 	grp = cpu_top;
5890 	if (grp == NULL)
5891 		return cpu;
5892 	i = 0;
5893 	while ((i = find_child_with_core(cpu, grp)) != -1) {
5894 		/* If the child only has one cpu, don't descend */
5895 		if (grp->cg_child[i].cg_count <= 1)
5896 			break;
5897 		grp = &grp->cg_child[i];
5898 	}
5899 
5900 	/* If they don't share at least an L2 cache, use the same CPU */
5901 	if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE)
5902 		return cpu;
5903 
5904 	/* Now pick one */
5905 	CPU_COPY(&grp->cg_mask, &cs);
5906 
5907 	/* Add the selected CPU offset to core offset. */
5908 	for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) {
5909 		if (fcpu - 1 == cpu)
5910 			break;
5911 		CPU_CLR(fcpu - 1, &cs);
5912 	}
5913 	MPASS(fcpu);
5914 
5915 	core_offset += i;
5916 
5917 	CPU_COPY(&grp->cg_mask, &cs);
5918 	for (i = core_offset % grp->cg_count; i > 0; i--) {
5919 		MPASS(CPU_FFS(&cs));
5920 		CPU_CLR(CPU_FFS(&cs) - 1, &cs);
5921 	}
5922 	MPASS(CPU_FFS(&cs));
5923 	return CPU_FFS(&cs) - 1;
5924 }
5925 #else
5926 static int
5927 find_close_core(int cpu, int core_offset __unused)
5928 {
5929 	return cpu;
5930 }
5931 #endif
5932 
5933 static int
5934 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid)
5935 {
5936 	switch (type) {
5937 	case IFLIB_INTR_TX:
5938 		/* TX queues get cores which share at least an L2 cache with the corresponding RX queue */
5939 		/* XXX handle multiple RX threads per core and more than two core per L2 group */
5940 		return qid / CPU_COUNT(&ctx->ifc_cpus) + 1;
5941 	case IFLIB_INTR_RX:
5942 	case IFLIB_INTR_RXTX:
5943 		/* RX queues get the specified core */
5944 		return qid / CPU_COUNT(&ctx->ifc_cpus);
5945 	default:
5946 		return -1;
5947 	}
5948 }
5949 #else
5950 #define get_core_offset(ctx, type, qid)	CPU_FIRST()
5951 #define find_close_core(cpuid, tid)	CPU_FIRST()
5952 #define find_nth(ctx, gid)		CPU_FIRST()
5953 #endif
5954 
5955 /* Just to avoid copy/paste */
5956 static inline int
5957 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
5958     int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
5959     const char *name)
5960 {
5961 	device_t dev;
5962 	int co, cpuid, err, tid;
5963 
5964 	dev = ctx->ifc_dev;
5965 	co = ctx->ifc_sysctl_core_offset;
5966 	if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX)
5967 		co += ctx->ifc_softc_ctx.isc_nrxqsets;
5968 	cpuid = find_nth(ctx, qid + co);
5969 	tid = get_core_offset(ctx, type, qid);
5970 	if (tid < 0) {
5971 		device_printf(dev, "get_core_offset failed\n");
5972 		return (EOPNOTSUPP);
5973 	}
5974 	cpuid = find_close_core(cpuid, tid);
5975 	err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res,
5976 	    name);
5977 	if (err) {
5978 		device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
5979 		return (err);
5980 	}
5981 #ifdef notyet
5982 	if (cpuid > ctx->ifc_cpuid_highest)
5983 		ctx->ifc_cpuid_highest = cpuid;
5984 #endif
5985 	return (0);
5986 }
5987 
5988 int
5989 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
5990 			iflib_intr_type_t type, driver_filter_t *filter,
5991 			void *filter_arg, int qid, const char *name)
5992 {
5993 	device_t dev;
5994 	struct grouptask *gtask;
5995 	struct taskqgroup *tqg;
5996 	iflib_filter_info_t info;
5997 	gtask_fn_t *fn;
5998 	int tqrid, err;
5999 	driver_filter_t *intr_fast;
6000 	void *q;
6001 
6002 	info = &ctx->ifc_filter_info;
6003 	tqrid = rid;
6004 
6005 	switch (type) {
6006 	/* XXX merge tx/rx for netmap? */
6007 	case IFLIB_INTR_TX:
6008 		q = &ctx->ifc_txqs[qid];
6009 		info = &ctx->ifc_txqs[qid].ift_filter_info;
6010 		gtask = &ctx->ifc_txqs[qid].ift_task;
6011 		tqg = qgroup_if_io_tqg;
6012 		fn = _task_fn_tx;
6013 		intr_fast = iflib_fast_intr;
6014 		GROUPTASK_INIT(gtask, 0, fn, q);
6015 		ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
6016 		break;
6017 	case IFLIB_INTR_RX:
6018 		q = &ctx->ifc_rxqs[qid];
6019 		info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6020 		gtask = &ctx->ifc_rxqs[qid].ifr_task;
6021 		tqg = qgroup_if_io_tqg;
6022 		fn = _task_fn_rx;
6023 		intr_fast = iflib_fast_intr;
6024 		NET_GROUPTASK_INIT(gtask, 0, fn, q);
6025 		break;
6026 	case IFLIB_INTR_RXTX:
6027 		q = &ctx->ifc_rxqs[qid];
6028 		info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6029 		gtask = &ctx->ifc_rxqs[qid].ifr_task;
6030 		tqg = qgroup_if_io_tqg;
6031 		fn = _task_fn_rx;
6032 		intr_fast = iflib_fast_intr_rxtx;
6033 		NET_GROUPTASK_INIT(gtask, 0, fn, q);
6034 		break;
6035 	case IFLIB_INTR_ADMIN:
6036 		q = ctx;
6037 		tqrid = -1;
6038 		info = &ctx->ifc_filter_info;
6039 		gtask = &ctx->ifc_admin_task;
6040 		tqg = qgroup_if_config_tqg;
6041 		fn = _task_fn_admin;
6042 		intr_fast = iflib_fast_intr_ctx;
6043 		break;
6044 	default:
6045 		device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
6046 		    __func__);
6047 		return (EINVAL);
6048 	}
6049 
6050 	info->ifi_filter = filter;
6051 	info->ifi_filter_arg = filter_arg;
6052 	info->ifi_task = gtask;
6053 	info->ifi_ctx = q;
6054 
6055 	dev = ctx->ifc_dev;
6056 	err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info,  name);
6057 	if (err != 0) {
6058 		device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
6059 		return (err);
6060 	}
6061 	if (type == IFLIB_INTR_ADMIN)
6062 		return (0);
6063 
6064 	if (tqrid != -1) {
6065 		err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6066 		    q, name);
6067 		if (err)
6068 			return (err);
6069 	} else {
6070 		taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
6071 	}
6072 
6073 	return (0);
6074 }
6075 
6076 void
6077 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name)
6078 {
6079 	struct grouptask *gtask;
6080 	struct taskqgroup *tqg;
6081 	gtask_fn_t *fn;
6082 	void *q;
6083 	int err;
6084 
6085 	switch (type) {
6086 	case IFLIB_INTR_TX:
6087 		q = &ctx->ifc_txqs[qid];
6088 		gtask = &ctx->ifc_txqs[qid].ift_task;
6089 		tqg = qgroup_if_io_tqg;
6090 		fn = _task_fn_tx;
6091 		GROUPTASK_INIT(gtask, 0, fn, q);
6092 		break;
6093 	case IFLIB_INTR_RX:
6094 		q = &ctx->ifc_rxqs[qid];
6095 		gtask = &ctx->ifc_rxqs[qid].ifr_task;
6096 		tqg = qgroup_if_io_tqg;
6097 		fn = _task_fn_rx;
6098 		NET_GROUPTASK_INIT(gtask, 0, fn, q);
6099 		break;
6100 	case IFLIB_INTR_IOV:
6101 		q = ctx;
6102 		gtask = &ctx->ifc_vflr_task;
6103 		tqg = qgroup_if_config_tqg;
6104 		fn = _task_fn_iov;
6105 		GROUPTASK_INIT(gtask, 0, fn, q);
6106 		break;
6107 	default:
6108 		panic("unknown net intr type");
6109 	}
6110 	if (irq != NULL) {
6111 		err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg,
6112 		    q, name);
6113 		if (err)
6114 			taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev,
6115 			    irq->ii_res, name);
6116 	} else {
6117 		taskqgroup_attach(tqg, gtask, q, NULL, NULL, name);
6118 	}
6119 }
6120 
6121 void
6122 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6123 {
6124 
6125 	if (irq->ii_tag)
6126 		bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6127 
6128 	if (irq->ii_res)
6129 		bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6130 		    rman_get_rid(irq->ii_res), irq->ii_res);
6131 }
6132 
6133 static int
6134 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6135 {
6136 	iflib_txq_t txq = ctx->ifc_txqs;
6137 	iflib_rxq_t rxq = ctx->ifc_rxqs;
6138 	if_irq_t irq = &ctx->ifc_legacy_irq;
6139 	iflib_filter_info_t info;
6140 	device_t dev;
6141 	struct grouptask *gtask;
6142 	struct resource *res;
6143 	struct taskqgroup *tqg;
6144 	void *q;
6145 	int err, tqrid;
6146 	bool rx_only;
6147 
6148 	q = &ctx->ifc_rxqs[0];
6149 	info = &rxq[0].ifr_filter_info;
6150 	gtask = &rxq[0].ifr_task;
6151 	tqg = qgroup_if_io_tqg;
6152 	tqrid = *rid;
6153 	rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0;
6154 
6155 	ctx->ifc_flags |= IFC_LEGACY;
6156 	info->ifi_filter = filter;
6157 	info->ifi_filter_arg = filter_arg;
6158 	info->ifi_task = gtask;
6159 	info->ifi_ctx = rx_only ? ctx : q;
6160 
6161 	dev = ctx->ifc_dev;
6162 	/* We allocate a single interrupt resource */
6163 	err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx :
6164 	    iflib_fast_intr_rxtx, NULL, info, name);
6165 	if (err != 0)
6166 		return (err);
6167 	NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q);
6168 	res = irq->ii_res;
6169 	taskqgroup_attach(tqg, gtask, q, dev, res, name);
6170 
6171 	GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6172 	taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6173 	    "tx");
6174 	return (0);
6175 }
6176 
6177 void
6178 iflib_led_create(if_ctx_t ctx)
6179 {
6180 
6181 	ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6182 	    device_get_nameunit(ctx->ifc_dev));
6183 }
6184 
6185 void
6186 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6187 {
6188 
6189 	GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6190 }
6191 
6192 void
6193 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6194 {
6195 
6196 	GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6197 }
6198 
6199 void
6200 iflib_admin_intr_deferred(if_ctx_t ctx)
6201 {
6202 
6203 	MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL);
6204 	GROUPTASK_ENQUEUE(&ctx->ifc_admin_task);
6205 }
6206 
6207 void
6208 iflib_iov_intr_deferred(if_ctx_t ctx)
6209 {
6210 
6211 	GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task);
6212 }
6213 
6214 void
6215 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name)
6216 {
6217 
6218 	taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6219 	    name);
6220 }
6221 
6222 void
6223 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn,
6224 	const char *name)
6225 {
6226 
6227 	GROUPTASK_INIT(gtask, 0, fn, ctx);
6228 	taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL,
6229 	    name);
6230 }
6231 
6232 void
6233 iflib_config_gtask_deinit(struct grouptask *gtask)
6234 {
6235 
6236 	taskqgroup_detach(qgroup_if_config_tqg, gtask);
6237 }
6238 
6239 void
6240 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6241 {
6242 	if_t ifp = ctx->ifc_ifp;
6243 	iflib_txq_t txq = ctx->ifc_txqs;
6244 
6245 	if_setbaudrate(ifp, baudrate);
6246 	if (baudrate >= IF_Gbps(10)) {
6247 		STATE_LOCK(ctx);
6248 		ctx->ifc_flags |= IFC_PREFETCH;
6249 		STATE_UNLOCK(ctx);
6250 	}
6251 	/* If link down, disable watchdog */
6252 	if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6253 		for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6254 			txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6255 	}
6256 	ctx->ifc_link_state = link_state;
6257 	if_link_state_change(ifp, link_state);
6258 }
6259 
6260 static int
6261 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6262 {
6263 	int credits;
6264 #ifdef INVARIANTS
6265 	int credits_pre = txq->ift_cidx_processed;
6266 #endif
6267 
6268 	bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6269 	    BUS_DMASYNC_POSTREAD);
6270 	if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6271 		return (0);
6272 
6273 	txq->ift_processed += credits;
6274 	txq->ift_cidx_processed += credits;
6275 
6276 	MPASS(credits_pre + credits == txq->ift_cidx_processed);
6277 	if (txq->ift_cidx_processed >= txq->ift_size)
6278 		txq->ift_cidx_processed -= txq->ift_size;
6279 	return (credits);
6280 }
6281 
6282 static int
6283 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6284 {
6285 	iflib_fl_t fl;
6286 	u_int i;
6287 
6288 	for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6289 		bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6290 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6291 	return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6292 	    budget));
6293 }
6294 
6295 void
6296 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6297 	const char *description, if_int_delay_info_t info,
6298 	int offset, int value)
6299 {
6300 	info->iidi_ctx = ctx;
6301 	info->iidi_offset = offset;
6302 	info->iidi_value = value;
6303 	SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6304 	    SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6305 	    OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
6306 	    info, 0, iflib_sysctl_int_delay, "I", description);
6307 }
6308 
6309 struct sx *
6310 iflib_ctx_lock_get(if_ctx_t ctx)
6311 {
6312 
6313 	return (&ctx->ifc_ctx_sx);
6314 }
6315 
6316 static int
6317 iflib_msix_init(if_ctx_t ctx)
6318 {
6319 	device_t dev = ctx->ifc_dev;
6320 	if_shared_ctx_t sctx = ctx->ifc_sctx;
6321 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6322 	int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6323 	int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6324 
6325 	iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6326 	iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6327 
6328 	if (bootverbose)
6329 		device_printf(dev, "msix_init qsets capped at %d\n",
6330 		    imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6331 
6332 	/* Override by tuneable */
6333 	if (scctx->isc_disable_msix)
6334 		goto msi;
6335 
6336 	/* First try MSI-X */
6337 	if ((msgs = pci_msix_count(dev)) == 0) {
6338 		if (bootverbose)
6339 			device_printf(dev, "MSI-X not supported or disabled\n");
6340 		goto msi;
6341 	}
6342 
6343 	bar = ctx->ifc_softc_ctx.isc_msix_bar;
6344 	/*
6345 	 * bar == -1 => "trust me I know what I'm doing"
6346 	 * Some drivers are for hardware that is so shoddily
6347 	 * documented that no one knows which bars are which
6348 	 * so the developer has to map all bars. This hack
6349 	 * allows shoddy garbage to use MSI-X in this framework.
6350 	 */
6351 	if (bar != -1) {
6352 		ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6353 	            SYS_RES_MEMORY, &bar, RF_ACTIVE);
6354 		if (ctx->ifc_msix_mem == NULL) {
6355 			device_printf(dev, "Unable to map MSI-X table\n");
6356 			goto msi;
6357 		}
6358 	}
6359 
6360 	admincnt = sctx->isc_admin_intrcnt;
6361 #if IFLIB_DEBUG
6362 	/* use only 1 qset in debug mode */
6363 	queuemsgs = min(msgs - admincnt, 1);
6364 #else
6365 	queuemsgs = msgs - admincnt;
6366 #endif
6367 #ifdef RSS
6368 	queues = imin(queuemsgs, rss_getnumbuckets());
6369 #else
6370 	queues = queuemsgs;
6371 #endif
6372 	queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6373 	if (bootverbose)
6374 		device_printf(dev,
6375 		    "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6376 		    CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6377 #ifdef  RSS
6378 	/* If we're doing RSS, clamp at the number of RSS buckets */
6379 	if (queues > rss_getnumbuckets())
6380 		queues = rss_getnumbuckets();
6381 #endif
6382 	if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6383 		rx_queues = iflib_num_rx_queues;
6384 	else
6385 		rx_queues = queues;
6386 
6387 	if (rx_queues > scctx->isc_nrxqsets)
6388 		rx_queues = scctx->isc_nrxqsets;
6389 
6390 	/*
6391 	 * We want this to be all logical CPUs by default
6392 	 */
6393 	if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6394 		tx_queues = iflib_num_tx_queues;
6395 	else
6396 		tx_queues = mp_ncpus;
6397 
6398 	if (tx_queues > scctx->isc_ntxqsets)
6399 		tx_queues = scctx->isc_ntxqsets;
6400 
6401 	if (ctx->ifc_sysctl_qs_eq_override == 0) {
6402 #ifdef INVARIANTS
6403 		if (tx_queues != rx_queues)
6404 			device_printf(dev,
6405 			    "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6406 			    min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6407 #endif
6408 		tx_queues = min(rx_queues, tx_queues);
6409 		rx_queues = min(rx_queues, tx_queues);
6410 	}
6411 
6412 	vectors = rx_queues + admincnt;
6413 	if (msgs < vectors) {
6414 		device_printf(dev,
6415 		    "insufficient number of MSI-X vectors "
6416 		    "(supported %d, need %d)\n", msgs, vectors);
6417 		goto msi;
6418 	}
6419 
6420 	device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6421 	    tx_queues);
6422 	msgs = vectors;
6423 	if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6424 		if (vectors != msgs) {
6425 			device_printf(dev,
6426 			    "Unable to allocate sufficient MSI-X vectors "
6427 			    "(got %d, need %d)\n", vectors, msgs);
6428 			pci_release_msi(dev);
6429 			if (bar != -1) {
6430 				bus_release_resource(dev, SYS_RES_MEMORY, bar,
6431 				    ctx->ifc_msix_mem);
6432 				ctx->ifc_msix_mem = NULL;
6433 			}
6434 			goto msi;
6435 		}
6436 		device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6437 		    vectors);
6438 		scctx->isc_vectors = vectors;
6439 		scctx->isc_nrxqsets = rx_queues;
6440 		scctx->isc_ntxqsets = tx_queues;
6441 		scctx->isc_intr = IFLIB_INTR_MSIX;
6442 
6443 		return (vectors);
6444 	} else {
6445 		device_printf(dev,
6446 		    "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6447 		    err);
6448 		if (bar != -1) {
6449 			bus_release_resource(dev, SYS_RES_MEMORY, bar,
6450 			    ctx->ifc_msix_mem);
6451 			ctx->ifc_msix_mem = NULL;
6452 		}
6453 	}
6454 
6455 msi:
6456 	vectors = pci_msi_count(dev);
6457 	scctx->isc_nrxqsets = 1;
6458 	scctx->isc_ntxqsets = 1;
6459 	scctx->isc_vectors = vectors;
6460 	if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6461 		device_printf(dev,"Using an MSI interrupt\n");
6462 		scctx->isc_intr = IFLIB_INTR_MSI;
6463 	} else {
6464 		scctx->isc_vectors = 1;
6465 		device_printf(dev,"Using a Legacy interrupt\n");
6466 		scctx->isc_intr = IFLIB_INTR_LEGACY;
6467 	}
6468 
6469 	return (vectors);
6470 }
6471 
6472 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6473 
6474 static int
6475 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6476 {
6477 	int rc;
6478 	uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6479 	struct sbuf *sb;
6480 	const char *ring_state = "UNKNOWN";
6481 
6482 	/* XXX needed ? */
6483 	rc = sysctl_wire_old_buffer(req, 0);
6484 	MPASS(rc == 0);
6485 	if (rc != 0)
6486 		return (rc);
6487 	sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6488 	MPASS(sb != NULL);
6489 	if (sb == NULL)
6490 		return (ENOMEM);
6491 	if (state[3] <= 3)
6492 		ring_state = ring_states[state[3]];
6493 
6494 	sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6495 		    state[0], state[1], state[2], ring_state);
6496 	rc = sbuf_finish(sb);
6497 	sbuf_delete(sb);
6498         return(rc);
6499 }
6500 
6501 enum iflib_ndesc_handler {
6502 	IFLIB_NTXD_HANDLER,
6503 	IFLIB_NRXD_HANDLER,
6504 };
6505 
6506 static int
6507 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6508 {
6509 	if_ctx_t ctx = (void *)arg1;
6510 	enum iflib_ndesc_handler type = arg2;
6511 	char buf[256] = {0};
6512 	qidx_t *ndesc;
6513 	char *p, *next;
6514 	int nqs, rc, i;
6515 
6516 	nqs = 8;
6517 	switch(type) {
6518 	case IFLIB_NTXD_HANDLER:
6519 		ndesc = ctx->ifc_sysctl_ntxds;
6520 		if (ctx->ifc_sctx)
6521 			nqs = ctx->ifc_sctx->isc_ntxqs;
6522 		break;
6523 	case IFLIB_NRXD_HANDLER:
6524 		ndesc = ctx->ifc_sysctl_nrxds;
6525 		if (ctx->ifc_sctx)
6526 			nqs = ctx->ifc_sctx->isc_nrxqs;
6527 		break;
6528 	default:
6529 		printf("%s: unhandled type\n", __func__);
6530 		return (EINVAL);
6531 	}
6532 	if (nqs == 0)
6533 		nqs = 8;
6534 
6535 	for (i=0; i<8; i++) {
6536 		if (i >= nqs)
6537 			break;
6538 		if (i)
6539 			strcat(buf, ",");
6540 		sprintf(strchr(buf, 0), "%d", ndesc[i]);
6541 	}
6542 
6543 	rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6544 	if (rc || req->newptr == NULL)
6545 		return rc;
6546 
6547 	for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6548 	    i++, p = strsep(&next, " ,")) {
6549 		ndesc[i] = strtoul(p, NULL, 10);
6550 	}
6551 
6552 	return(rc);
6553 }
6554 
6555 #define NAME_BUFLEN 32
6556 static void
6557 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6558 {
6559         device_t dev = iflib_get_dev(ctx);
6560 	struct sysctl_oid_list *child, *oid_list;
6561 	struct sysctl_ctx_list *ctx_list;
6562 	struct sysctl_oid *node;
6563 
6564 	ctx_list = device_get_sysctl_ctx(dev);
6565 	child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6566 	ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib",
6567 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields");
6568 	oid_list = SYSCTL_CHILDREN(node);
6569 
6570 	SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6571 		       CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version,
6572 		       "driver version");
6573 
6574 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6575 		       CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6576 			"# of txqs to use, 0 => use default #");
6577 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6578 		       CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6579 			"# of rxqs to use, 0 => use default #");
6580 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6581 		       CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6582                        "permit #txq != #rxq");
6583 	SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6584                       CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6585                       "disable MSI-X (default 0)");
6586 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6587 		       CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0,
6588 		       "set the RX budget");
6589 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6590 		       CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6591 		       "cause TX to abdicate instead of running to completion");
6592 	ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6593 	SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6594 		       CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6595 		       "offset to start using cores at");
6596 	SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6597 		       CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6598 		       "use separate cores for TX and RX");
6599 
6600 	/* XXX change for per-queue sizes */
6601 	SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6602 	    CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6603 	    IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A",
6604 	    "list of # of TX descriptors to use, 0 = use default #");
6605 	SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6606 	    CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6607 	    IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A",
6608 	    "list of # of RX descriptors to use, 0 = use default #");
6609 }
6610 
6611 static void
6612 iflib_add_device_sysctl_post(if_ctx_t ctx)
6613 {
6614 	if_shared_ctx_t sctx = ctx->ifc_sctx;
6615 	if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6616         device_t dev = iflib_get_dev(ctx);
6617 	struct sysctl_oid_list *child;
6618 	struct sysctl_ctx_list *ctx_list;
6619 	iflib_fl_t fl;
6620 	iflib_txq_t txq;
6621 	iflib_rxq_t rxq;
6622 	int i, j;
6623 	char namebuf[NAME_BUFLEN];
6624 	char *qfmt;
6625 	struct sysctl_oid *queue_node, *fl_node, *node;
6626 	struct sysctl_oid_list *queue_list, *fl_list;
6627 	ctx_list = device_get_sysctl_ctx(dev);
6628 
6629 	node = ctx->ifc_sysctl_node;
6630 	child = SYSCTL_CHILDREN(node);
6631 
6632 	if (scctx->isc_ntxqsets > 100)
6633 		qfmt = "txq%03d";
6634 	else if (scctx->isc_ntxqsets > 10)
6635 		qfmt = "txq%02d";
6636 	else
6637 		qfmt = "txq%d";
6638 	for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6639 		snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6640 		queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6641 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6642 		queue_list = SYSCTL_CHILDREN(queue_node);
6643 #if MEMORY_LOGGING
6644 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6645 				CTLFLAG_RD,
6646 				&txq->ift_dequeued, "total mbufs freed");
6647 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6648 				CTLFLAG_RD,
6649 				&txq->ift_enqueued, "total mbufs enqueued");
6650 #endif
6651 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6652 				   CTLFLAG_RD,
6653 				   &txq->ift_mbuf_defrag, "# of times m_defrag was called");
6654 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6655 				   CTLFLAG_RD,
6656 				   &txq->ift_pullups, "# of times m_pullup was called");
6657 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed",
6658 				   CTLFLAG_RD,
6659 				   &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6660 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail",
6661 				   CTLFLAG_RD,
6662 				   &txq->ift_no_desc_avail, "# of times no descriptors were available");
6663 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed",
6664 				   CTLFLAG_RD,
6665 				   &txq->ift_map_failed, "# of times DMA map failed");
6666 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig",
6667 				   CTLFLAG_RD,
6668 				   &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG");
6669 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup",
6670 				   CTLFLAG_RD,
6671 				   &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG");
6672 		SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6673 				   CTLFLAG_RD,
6674 				   &txq->ift_pidx, 1, "Producer Index");
6675 		SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6676 				   CTLFLAG_RD,
6677 				   &txq->ift_cidx, 1, "Consumer Index");
6678 		SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed",
6679 				   CTLFLAG_RD,
6680 				   &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update");
6681 		SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6682 				   CTLFLAG_RD,
6683 				   &txq->ift_in_use, 1, "descriptors in use");
6684 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed",
6685 				   CTLFLAG_RD,
6686 				   &txq->ift_processed, "descriptors procesed for clean");
6687 		SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6688 				   CTLFLAG_RD,
6689 				   &txq->ift_cleaned, "total cleaned");
6690 		SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6691 		    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
6692 		    __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0,
6693 		    mp_ring_state_handler, "A", "soft ring state");
6694 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues",
6695 				       CTLFLAG_RD, &txq->ift_br->enqueues,
6696 				       "# of enqueues to the mp_ring for this queue");
6697 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops",
6698 				       CTLFLAG_RD, &txq->ift_br->drops,
6699 				       "# of drops in the mp_ring for this queue");
6700 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts",
6701 				       CTLFLAG_RD, &txq->ift_br->starts,
6702 				       "# of normal consumer starts in the mp_ring for this queue");
6703 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls",
6704 				       CTLFLAG_RD, &txq->ift_br->stalls,
6705 					       "# of consumer stalls in the mp_ring for this queue");
6706 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts",
6707 			       CTLFLAG_RD, &txq->ift_br->restarts,
6708 				       "# of consumer restarts in the mp_ring for this queue");
6709 		SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications",
6710 				       CTLFLAG_RD, &txq->ift_br->abdications,
6711 				       "# of consumer abdications in the mp_ring for this queue");
6712 	}
6713 
6714 	if (scctx->isc_nrxqsets > 100)
6715 		qfmt = "rxq%03d";
6716 	else if (scctx->isc_nrxqsets > 10)
6717 		qfmt = "rxq%02d";
6718 	else
6719 		qfmt = "rxq%d";
6720 	for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6721 		snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6722 		queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6723 		    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6724 		queue_list = SYSCTL_CHILDREN(queue_node);
6725 		if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6726 			SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx",
6727 				       CTLFLAG_RD,
6728 				       &rxq->ifr_cq_cidx, 1, "Consumer Index");
6729 		}
6730 
6731 		for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6732 			snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6733 			fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf,
6734 			    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name");
6735 			fl_list = SYSCTL_CHILDREN(fl_node);
6736 			SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6737 				       CTLFLAG_RD,
6738 				       &fl->ifl_pidx, 1, "Producer Index");
6739 			SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6740 				       CTLFLAG_RD,
6741 				       &fl->ifl_cidx, 1, "Consumer Index");
6742 			SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6743 				       CTLFLAG_RD,
6744 				       &fl->ifl_credits, 1, "credits available");
6745 			SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size",
6746 				       CTLFLAG_RD,
6747 				       &fl->ifl_buf_size, 1, "buffer size");
6748 #if MEMORY_LOGGING
6749 			SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued",
6750 					CTLFLAG_RD,
6751 					&fl->ifl_m_enqueued, "mbufs allocated");
6752 			SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued",
6753 					CTLFLAG_RD,
6754 					&fl->ifl_m_dequeued, "mbufs freed");
6755 			SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued",
6756 					CTLFLAG_RD,
6757 					&fl->ifl_cl_enqueued, "clusters allocated");
6758 			SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued",
6759 					CTLFLAG_RD,
6760 					&fl->ifl_cl_dequeued, "clusters freed");
6761 #endif
6762 
6763 		}
6764 	}
6765 
6766 }
6767 
6768 void
6769 iflib_request_reset(if_ctx_t ctx)
6770 {
6771 
6772 	STATE_LOCK(ctx);
6773 	ctx->ifc_flags |= IFC_DO_RESET;
6774 	STATE_UNLOCK(ctx);
6775 }
6776 
6777 #ifndef __NO_STRICT_ALIGNMENT
6778 static struct mbuf *
6779 iflib_fixup_rx(struct mbuf *m)
6780 {
6781 	struct mbuf *n;
6782 
6783 	if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
6784 		bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
6785 		m->m_data += ETHER_HDR_LEN;
6786 		n = m;
6787 	} else {
6788 		MGETHDR(n, M_NOWAIT, MT_DATA);
6789 		if (n == NULL) {
6790 			m_freem(m);
6791 			return (NULL);
6792 		}
6793 		bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
6794 		m->m_data += ETHER_HDR_LEN;
6795 		m->m_len -= ETHER_HDR_LEN;
6796 		n->m_len = ETHER_HDR_LEN;
6797 		M_MOVE_PKTHDR(n, m);
6798 		n->m_next = m;
6799 	}
6800 	return (n);
6801 }
6802 #endif
6803 
6804 #ifdef DEBUGNET
6805 static void
6806 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6807 {
6808 	if_ctx_t ctx;
6809 
6810 	ctx = if_getsoftc(ifp);
6811 	CTX_LOCK(ctx);
6812 	*nrxr = NRXQSETS(ctx);
6813 	*ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
6814 	*clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
6815 	CTX_UNLOCK(ctx);
6816 }
6817 
6818 static void
6819 iflib_debugnet_event(if_t ifp, enum debugnet_ev event)
6820 {
6821 	if_ctx_t ctx;
6822 	if_softc_ctx_t scctx;
6823 	iflib_fl_t fl;
6824 	iflib_rxq_t rxq;
6825 	int i, j;
6826 
6827 	ctx = if_getsoftc(ifp);
6828 	scctx = &ctx->ifc_softc_ctx;
6829 
6830 	switch (event) {
6831 	case DEBUGNET_START:
6832 		for (i = 0; i < scctx->isc_nrxqsets; i++) {
6833 			rxq = &ctx->ifc_rxqs[i];
6834 			for (j = 0; j < rxq->ifr_nfl; j++) {
6835 				fl = rxq->ifr_fl;
6836 				fl->ifl_zone = m_getzone(fl->ifl_buf_size);
6837 			}
6838 		}
6839 		iflib_no_tx_batch = 1;
6840 		break;
6841 	default:
6842 		break;
6843 	}
6844 }
6845 
6846 static int
6847 iflib_debugnet_transmit(if_t ifp, struct mbuf *m)
6848 {
6849 	if_ctx_t ctx;
6850 	iflib_txq_t txq;
6851 	int error;
6852 
6853 	ctx = if_getsoftc(ifp);
6854 	if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6855 	    IFF_DRV_RUNNING)
6856 		return (EBUSY);
6857 
6858 	txq = &ctx->ifc_txqs[0];
6859 	error = iflib_encap(txq, &m);
6860 	if (error == 0)
6861 		(void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use);
6862 	return (error);
6863 }
6864 
6865 static int
6866 iflib_debugnet_poll(if_t ifp, int count)
6867 {
6868 	struct epoch_tracker et;
6869 	if_ctx_t ctx;
6870 	if_softc_ctx_t scctx;
6871 	iflib_txq_t txq;
6872 	int i;
6873 
6874 	ctx = if_getsoftc(ifp);
6875 	scctx = &ctx->ifc_softc_ctx;
6876 
6877 	if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6878 	    IFF_DRV_RUNNING)
6879 		return (EBUSY);
6880 
6881 	txq = &ctx->ifc_txqs[0];
6882 	(void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx));
6883 
6884 	NET_EPOCH_ENTER(et);
6885 	for (i = 0; i < scctx->isc_nrxqsets; i++)
6886 		(void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
6887 	NET_EPOCH_EXIT(et);
6888 	return (0);
6889 }
6890 #endif /* DEBUGNET */
6891