1 /*- 2 * Copyright (c) 2014-2017, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/sockio.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/mutex.h> 44 #include <sys/module.h> 45 #include <sys/kobj.h> 46 #include <sys/rman.h> 47 #include <sys/sbuf.h> 48 #include <sys/smp.h> 49 #include <sys/socket.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 56 #include <net/if.h> 57 #include <net/if_var.h> 58 #include <net/if_types.h> 59 #include <net/if_media.h> 60 #include <net/bpf.h> 61 #include <net/ethernet.h> 62 #include <net/mp_ring.h> 63 #include <net/vnet.h> 64 65 #include <netinet/in.h> 66 #include <netinet/in_pcb.h> 67 #include <netinet/tcp_lro.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/if_ether.h> 70 #include <netinet/ip.h> 71 #include <netinet/ip6.h> 72 #include <netinet/tcp.h> 73 #include <netinet/ip_var.h> 74 #include <netinet6/ip6_var.h> 75 76 #include <machine/bus.h> 77 #include <machine/in_cksum.h> 78 79 #include <vm/vm.h> 80 #include <vm/pmap.h> 81 82 #include <dev/led/led.h> 83 #include <dev/pci/pcireg.h> 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pci_private.h> 86 87 #include <net/iflib.h> 88 89 #include "ifdi_if.h" 90 91 #if defined(__i386__) || defined(__amd64__) 92 #include <sys/memdesc.h> 93 #include <machine/bus.h> 94 #include <machine/md_var.h> 95 #include <machine/specialreg.h> 96 #include <x86/include/busdma_impl.h> 97 #include <x86/iommu/busdma_dmar.h> 98 #endif 99 100 #include <sys/bitstring.h> 101 /* 102 * enable accounting of every mbuf as it comes in to and goes out of 103 * iflib's software descriptor references 104 */ 105 #define MEMORY_LOGGING 0 106 /* 107 * Enable mbuf vectors for compressing long mbuf chains 108 */ 109 110 /* 111 * NB: 112 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 113 * we prefetch needs to be determined by the time spent in m_free vis a vis 114 * the cost of a prefetch. This will of course vary based on the workload: 115 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 116 * is quite expensive, thus suggesting very little prefetch. 117 * - small packet forwarding which is just returning a single mbuf to 118 * UMA will typically be very fast vis a vis the cost of a memory 119 * access. 120 */ 121 122 123 /* 124 * File organization: 125 * - private structures 126 * - iflib private utility functions 127 * - ifnet functions 128 * - vlan registry and other exported functions 129 * - iflib public core functions 130 * 131 * 132 */ 133 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 134 135 struct iflib_txq; 136 typedef struct iflib_txq *iflib_txq_t; 137 struct iflib_rxq; 138 typedef struct iflib_rxq *iflib_rxq_t; 139 struct iflib_fl; 140 typedef struct iflib_fl *iflib_fl_t; 141 142 struct iflib_ctx; 143 144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 145 146 typedef struct iflib_filter_info { 147 driver_filter_t *ifi_filter; 148 void *ifi_filter_arg; 149 struct grouptask *ifi_task; 150 void *ifi_ctx; 151 } *iflib_filter_info_t; 152 153 struct iflib_ctx { 154 KOBJ_FIELDS; 155 /* 156 * Pointer to hardware driver's softc 157 */ 158 void *ifc_softc; 159 device_t ifc_dev; 160 if_t ifc_ifp; 161 162 cpuset_t ifc_cpus; 163 if_shared_ctx_t ifc_sctx; 164 struct if_softc_ctx ifc_softc_ctx; 165 166 struct mtx ifc_mtx; 167 168 uint16_t ifc_nhwtxqs; 169 uint16_t ifc_nhwrxqs; 170 171 iflib_txq_t ifc_txqs; 172 iflib_rxq_t ifc_rxqs; 173 uint32_t ifc_if_flags; 174 uint32_t ifc_flags; 175 uint32_t ifc_max_fl_buf_size; 176 int ifc_in_detach; 177 178 int ifc_link_state; 179 int ifc_link_irq; 180 int ifc_watchdog_events; 181 struct cdev *ifc_led_dev; 182 struct resource *ifc_msix_mem; 183 184 struct if_irq ifc_legacy_irq; 185 struct grouptask ifc_admin_task; 186 struct grouptask ifc_vflr_task; 187 struct iflib_filter_info ifc_filter_info; 188 struct ifmedia ifc_media; 189 190 struct sysctl_oid *ifc_sysctl_node; 191 uint16_t ifc_sysctl_ntxqs; 192 uint16_t ifc_sysctl_nrxqs; 193 uint16_t ifc_sysctl_qs_eq_override; 194 uint16_t ifc_sysctl_rx_budget; 195 196 qidx_t ifc_sysctl_ntxds[8]; 197 qidx_t ifc_sysctl_nrxds[8]; 198 struct if_txrx ifc_txrx; 199 #define isc_txd_encap ifc_txrx.ift_txd_encap 200 #define isc_txd_flush ifc_txrx.ift_txd_flush 201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 202 #define isc_rxd_available ifc_txrx.ift_rxd_available 203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 209 eventhandler_tag ifc_vlan_attach_event; 210 eventhandler_tag ifc_vlan_detach_event; 211 uint8_t ifc_mac[ETHER_ADDR_LEN]; 212 char ifc_mtx_name[16]; 213 }; 214 215 216 void * 217 iflib_get_softc(if_ctx_t ctx) 218 { 219 220 return (ctx->ifc_softc); 221 } 222 223 device_t 224 iflib_get_dev(if_ctx_t ctx) 225 { 226 227 return (ctx->ifc_dev); 228 } 229 230 if_t 231 iflib_get_ifp(if_ctx_t ctx) 232 { 233 234 return (ctx->ifc_ifp); 235 } 236 237 struct ifmedia * 238 iflib_get_media(if_ctx_t ctx) 239 { 240 241 return (&ctx->ifc_media); 242 } 243 244 void 245 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 246 { 247 248 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 249 } 250 251 if_softc_ctx_t 252 iflib_get_softc_ctx(if_ctx_t ctx) 253 { 254 255 return (&ctx->ifc_softc_ctx); 256 } 257 258 if_shared_ctx_t 259 iflib_get_sctx(if_ctx_t ctx) 260 { 261 262 return (ctx->ifc_sctx); 263 } 264 265 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 266 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 267 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 268 269 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 270 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 271 272 #define RX_SW_DESC_MAP_CREATED (1 << 0) 273 #define TX_SW_DESC_MAP_CREATED (1 << 1) 274 #define RX_SW_DESC_INUSE (1 << 3) 275 #define TX_SW_DESC_MAPPED (1 << 4) 276 277 #define M_TOOBIG M_PROTO1 278 279 typedef struct iflib_sw_rx_desc_array { 280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 281 struct mbuf **ifsd_m; /* pkthdr mbufs */ 282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 283 uint8_t *ifsd_flags; 284 } iflib_rxsd_array_t; 285 286 typedef struct iflib_sw_tx_desc_array { 287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 288 struct mbuf **ifsd_m; /* pkthdr mbufs */ 289 uint8_t *ifsd_flags; 290 } if_txsd_vec_t; 291 292 293 /* magic number that should be high enough for any hardware */ 294 #define IFLIB_MAX_TX_SEGS 128 295 /* bnxt supports 64 with hardware LRO enabled */ 296 #define IFLIB_MAX_RX_SEGS 64 297 #define IFLIB_RX_COPY_THRESH 128 298 #define IFLIB_MAX_RX_REFRESH 32 299 /* The minimum descriptors per second before we start coalescing */ 300 #define IFLIB_MIN_DESC_SEC 16384 301 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 302 #define IFLIB_QUEUE_IDLE 0 303 #define IFLIB_QUEUE_HUNG 1 304 #define IFLIB_QUEUE_WORKING 2 305 /* maximum number of txqs that can share an rx interrupt */ 306 #define IFLIB_MAX_TX_SHARED_INTR 4 307 308 /* this should really scale with ring size - this is a fairly arbitrary value */ 309 #define TX_BATCH_SIZE 32 310 311 #define IFLIB_RESTART_BUDGET 8 312 313 #define IFC_LEGACY 0x001 314 #define IFC_QFLUSH 0x002 315 #define IFC_MULTISEG 0x004 316 #define IFC_DMAR 0x008 317 #define IFC_SC_ALLOCATED 0x010 318 #define IFC_INIT_DONE 0x020 319 #define IFC_PREFETCH 0x040 320 #define IFC_DO_RESET 0x080 321 #define IFC_CHECK_HUNG 0x100 322 323 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 324 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 325 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 326 struct iflib_txq { 327 qidx_t ift_in_use; 328 qidx_t ift_cidx; 329 qidx_t ift_cidx_processed; 330 qidx_t ift_pidx; 331 uint8_t ift_gen; 332 uint8_t ift_br_offset; 333 uint16_t ift_npending; 334 uint16_t ift_db_pending; 335 uint16_t ift_rs_pending; 336 /* implicit pad */ 337 uint8_t ift_txd_size[8]; 338 uint64_t ift_processed; 339 uint64_t ift_cleaned; 340 uint64_t ift_cleaned_prev; 341 #if MEMORY_LOGGING 342 uint64_t ift_enqueued; 343 uint64_t ift_dequeued; 344 #endif 345 uint64_t ift_no_tx_dma_setup; 346 uint64_t ift_no_desc_avail; 347 uint64_t ift_mbuf_defrag_failed; 348 uint64_t ift_mbuf_defrag; 349 uint64_t ift_map_failed; 350 uint64_t ift_txd_encap_efbig; 351 uint64_t ift_pullups; 352 353 struct mtx ift_mtx; 354 struct mtx ift_db_mtx; 355 356 /* constant values */ 357 if_ctx_t ift_ctx; 358 struct ifmp_ring *ift_br; 359 struct grouptask ift_task; 360 qidx_t ift_size; 361 uint16_t ift_id; 362 struct callout ift_timer; 363 364 if_txsd_vec_t ift_sds; 365 uint8_t ift_qstatus; 366 uint8_t ift_closed; 367 uint8_t ift_update_freq; 368 struct iflib_filter_info ift_filter_info; 369 bus_dma_tag_t ift_desc_tag; 370 bus_dma_tag_t ift_tso_desc_tag; 371 iflib_dma_info_t ift_ifdi; 372 #define MTX_NAME_LEN 16 373 char ift_mtx_name[MTX_NAME_LEN]; 374 char ift_db_mtx_name[MTX_NAME_LEN]; 375 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 376 #ifdef IFLIB_DIAGNOSTICS 377 uint64_t ift_cpu_exec_count[256]; 378 #endif 379 } __aligned(CACHE_LINE_SIZE); 380 381 struct iflib_fl { 382 qidx_t ifl_cidx; 383 qidx_t ifl_pidx; 384 qidx_t ifl_credits; 385 uint8_t ifl_gen; 386 uint8_t ifl_rxd_size; 387 #if MEMORY_LOGGING 388 uint64_t ifl_m_enqueued; 389 uint64_t ifl_m_dequeued; 390 uint64_t ifl_cl_enqueued; 391 uint64_t ifl_cl_dequeued; 392 #endif 393 /* implicit pad */ 394 395 bitstr_t *ifl_rx_bitmap; 396 qidx_t ifl_fragidx; 397 /* constant */ 398 qidx_t ifl_size; 399 uint16_t ifl_buf_size; 400 uint16_t ifl_cltype; 401 uma_zone_t ifl_zone; 402 iflib_rxsd_array_t ifl_sds; 403 iflib_rxq_t ifl_rxq; 404 uint8_t ifl_id; 405 bus_dma_tag_t ifl_desc_tag; 406 iflib_dma_info_t ifl_ifdi; 407 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 408 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 409 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 410 } __aligned(CACHE_LINE_SIZE); 411 412 static inline qidx_t 413 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 414 { 415 qidx_t used; 416 417 if (pidx > cidx) 418 used = pidx - cidx; 419 else if (pidx < cidx) 420 used = size - cidx + pidx; 421 else if (gen == 0 && pidx == cidx) 422 used = 0; 423 else if (gen == 1 && pidx == cidx) 424 used = size; 425 else 426 panic("bad state"); 427 428 return (used); 429 } 430 431 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 432 433 #define IDXDIFF(head, tail, wrap) \ 434 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 435 436 struct iflib_rxq { 437 /* If there is a separate completion queue - 438 * these are the cq cidx and pidx. Otherwise 439 * these are unused. 440 */ 441 qidx_t ifr_size; 442 qidx_t ifr_cq_cidx; 443 qidx_t ifr_cq_pidx; 444 uint8_t ifr_cq_gen; 445 uint8_t ifr_fl_offset; 446 447 if_ctx_t ifr_ctx; 448 iflib_fl_t ifr_fl; 449 uint64_t ifr_rx_irq; 450 uint16_t ifr_id; 451 uint8_t ifr_lro_enabled; 452 uint8_t ifr_nfl; 453 uint8_t ifr_ntxqirq; 454 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 455 struct lro_ctrl ifr_lc; 456 struct grouptask ifr_task; 457 struct iflib_filter_info ifr_filter_info; 458 iflib_dma_info_t ifr_ifdi; 459 460 /* dynamically allocate if any drivers need a value substantially larger than this */ 461 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 462 #ifdef IFLIB_DIAGNOSTICS 463 uint64_t ifr_cpu_exec_count[256]; 464 #endif 465 } __aligned(CACHE_LINE_SIZE); 466 467 typedef struct if_rxsd { 468 caddr_t *ifsd_cl; 469 struct mbuf **ifsd_m; 470 iflib_fl_t ifsd_fl; 471 qidx_t ifsd_cidx; 472 } *if_rxsd_t; 473 474 /* multiple of word size */ 475 #ifdef __LP64__ 476 #define PKT_INFO_SIZE 6 477 #define RXD_INFO_SIZE 5 478 #define PKT_TYPE uint64_t 479 #else 480 #define PKT_INFO_SIZE 11 481 #define RXD_INFO_SIZE 8 482 #define PKT_TYPE uint32_t 483 #endif 484 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 485 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 486 487 typedef struct if_pkt_info_pad { 488 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 489 } *if_pkt_info_pad_t; 490 typedef struct if_rxd_info_pad { 491 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 492 } *if_rxd_info_pad_t; 493 494 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 495 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 496 497 498 static inline void 499 pkt_info_zero(if_pkt_info_t pi) 500 { 501 if_pkt_info_pad_t pi_pad; 502 503 pi_pad = (if_pkt_info_pad_t)pi; 504 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 505 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 506 #ifndef __LP64__ 507 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 508 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 509 #endif 510 } 511 512 static inline void 513 rxd_info_zero(if_rxd_info_t ri) 514 { 515 if_rxd_info_pad_t ri_pad; 516 int i; 517 518 ri_pad = (if_rxd_info_pad_t)ri; 519 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 520 ri_pad->rxd_val[i] = 0; 521 ri_pad->rxd_val[i+1] = 0; 522 ri_pad->rxd_val[i+2] = 0; 523 ri_pad->rxd_val[i+3] = 0; 524 } 525 #ifdef __LP64__ 526 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 527 #endif 528 } 529 530 /* 531 * Only allow a single packet to take up most 1/nth of the tx ring 532 */ 533 #define MAX_SINGLE_PACKET_FRACTION 12 534 #define IF_BAD_DMA (bus_addr_t)-1 535 536 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 537 538 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF) 539 540 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx) 541 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx) 542 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx) 543 544 545 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 546 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 547 548 549 /* Our boot-time initialization hook */ 550 static int iflib_module_event_handler(module_t, int, void *); 551 552 static moduledata_t iflib_moduledata = { 553 "iflib", 554 iflib_module_event_handler, 555 NULL 556 }; 557 558 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 559 MODULE_VERSION(iflib, 1); 560 561 MODULE_DEPEND(iflib, pci, 1, 1, 1); 562 MODULE_DEPEND(iflib, ether, 1, 1, 1); 563 564 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 565 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 566 567 #ifndef IFLIB_DEBUG_COUNTERS 568 #ifdef INVARIANTS 569 #define IFLIB_DEBUG_COUNTERS 1 570 #else 571 #define IFLIB_DEBUG_COUNTERS 0 572 #endif /* !INVARIANTS */ 573 #endif 574 575 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 576 "iflib driver parameters"); 577 578 /* 579 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 580 */ 581 static int iflib_min_tx_latency = 0; 582 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 583 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 584 static int iflib_no_tx_batch = 0; 585 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 586 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 587 588 589 #if IFLIB_DEBUG_COUNTERS 590 591 static int iflib_tx_seen; 592 static int iflib_tx_sent; 593 static int iflib_tx_encap; 594 static int iflib_rx_allocs; 595 static int iflib_fl_refills; 596 static int iflib_fl_refills_large; 597 static int iflib_tx_frees; 598 599 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 600 &iflib_tx_seen, 0, "# tx mbufs seen"); 601 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 602 &iflib_tx_sent, 0, "# tx mbufs sent"); 603 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 604 &iflib_tx_encap, 0, "# tx mbufs encapped"); 605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 606 &iflib_tx_frees, 0, "# tx frees"); 607 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 608 &iflib_rx_allocs, 0, "# rx allocations"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 610 &iflib_fl_refills, 0, "# refills"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 612 &iflib_fl_refills_large, 0, "# large refills"); 613 614 615 static int iflib_txq_drain_flushing; 616 static int iflib_txq_drain_oactive; 617 static int iflib_txq_drain_notready; 618 static int iflib_txq_drain_encapfail; 619 620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 621 &iflib_txq_drain_flushing, 0, "# drain flushes"); 622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 623 &iflib_txq_drain_oactive, 0, "# drain oactives"); 624 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 625 &iflib_txq_drain_notready, 0, "# drain notready"); 626 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 627 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 628 629 630 static int iflib_encap_load_mbuf_fail; 631 static int iflib_encap_pad_mbuf_fail; 632 static int iflib_encap_txq_avail_fail; 633 static int iflib_encap_txd_encap_fail; 634 635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 636 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 638 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 639 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 640 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 641 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 642 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 643 644 static int iflib_task_fn_rxs; 645 static int iflib_rx_intr_enables; 646 static int iflib_fast_intrs; 647 static int iflib_intr_link; 648 static int iflib_intr_msix; 649 static int iflib_rx_unavail; 650 static int iflib_rx_ctx_inactive; 651 static int iflib_rx_zero_len; 652 static int iflib_rx_if_input; 653 static int iflib_rx_mbuf_null; 654 static int iflib_rxd_flush; 655 656 static int iflib_verbose_debug; 657 658 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 659 &iflib_intr_link, 0, "# intr link calls"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 661 &iflib_intr_msix, 0, "# intr msix calls"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 663 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 665 &iflib_rx_intr_enables, 0, "# rx intr enables"); 666 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 667 &iflib_fast_intrs, 0, "# fast_intr calls"); 668 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 669 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 670 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 671 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 672 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 673 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 674 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 675 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 676 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 677 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 678 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 679 &iflib_rxd_flush, 0, "# times rxd_flush called"); 680 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 681 &iflib_verbose_debug, 0, "enable verbose debugging"); 682 683 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 684 static void 685 iflib_debug_reset(void) 686 { 687 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 688 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 689 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 690 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 691 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 692 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 693 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 694 iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 695 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 696 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 697 } 698 699 #else 700 #define DBG_COUNTER_INC(name) 701 static void iflib_debug_reset(void) {} 702 #endif 703 704 705 706 #define IFLIB_DEBUG 0 707 708 static void iflib_tx_structures_free(if_ctx_t ctx); 709 static void iflib_rx_structures_free(if_ctx_t ctx); 710 static int iflib_queues_alloc(if_ctx_t ctx); 711 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 712 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 713 static int iflib_qset_structures_setup(if_ctx_t ctx); 714 static int iflib_msix_init(if_ctx_t ctx); 715 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str); 716 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 717 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 718 static int iflib_register(if_ctx_t); 719 static void iflib_init_locked(if_ctx_t ctx); 720 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 721 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 722 static void iflib_ifmp_purge(iflib_txq_t txq); 723 static void _iflib_pre_assert(if_softc_ctx_t scctx); 724 static void iflib_stop(if_ctx_t ctx); 725 static void iflib_if_init_locked(if_ctx_t ctx); 726 #ifndef __NO_STRICT_ALIGNMENT 727 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 728 #endif 729 730 #ifdef DEV_NETMAP 731 #include <sys/selinfo.h> 732 #include <net/netmap.h> 733 #include <dev/netmap/netmap_kern.h> 734 735 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 736 737 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 738 739 /* 740 * device-specific sysctl variables: 741 * 742 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 743 * During regular operations the CRC is stripped, but on some 744 * hardware reception of frames not multiple of 64 is slower, 745 * so using crcstrip=0 helps in benchmarks. 746 * 747 * iflib_rx_miss, iflib_rx_miss_bufs: 748 * count packets that might be missed due to lost interrupts. 749 */ 750 SYSCTL_DECL(_dev_netmap); 751 /* 752 * The xl driver by default strips CRCs and we do not override it. 753 */ 754 755 int iflib_crcstrip = 1; 756 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 757 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 758 759 int iflib_rx_miss, iflib_rx_miss_bufs; 760 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 761 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 763 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 764 765 /* 766 * Register/unregister. We are already under netmap lock. 767 * Only called on the first register or the last unregister. 768 */ 769 static int 770 iflib_netmap_register(struct netmap_adapter *na, int onoff) 771 { 772 struct ifnet *ifp = na->ifp; 773 if_ctx_t ctx = ifp->if_softc; 774 int status; 775 776 CTX_LOCK(ctx); 777 IFDI_INTR_DISABLE(ctx); 778 779 /* Tell the stack that the interface is no longer active */ 780 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 781 782 if (!CTX_IS_VF(ctx)) 783 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 784 785 /* enable or disable flags and callbacks in na and ifp */ 786 if (onoff) { 787 nm_set_native_flags(na); 788 } else { 789 nm_clear_native_flags(na); 790 } 791 iflib_stop(ctx); 792 iflib_init_locked(ctx); 793 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 794 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 795 if (status) 796 nm_clear_native_flags(na); 797 CTX_UNLOCK(ctx); 798 return (status); 799 } 800 801 static int 802 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 803 { 804 struct netmap_adapter *na = kring->na; 805 u_int const lim = kring->nkr_num_slots - 1; 806 u_int head = kring->rhead; 807 struct netmap_ring *ring = kring->ring; 808 bus_dmamap_t *map; 809 struct if_rxd_update iru; 810 if_ctx_t ctx = rxq->ifr_ctx; 811 iflib_fl_t fl = &rxq->ifr_fl[0]; 812 uint32_t refill_pidx, nic_i; 813 814 if (nm_i == head && __predict_true(!init)) 815 return 0; 816 iru_init(&iru, rxq, 0 /* flid */); 817 map = fl->ifl_sds.ifsd_map; 818 refill_pidx = netmap_idx_k2n(kring, nm_i); 819 /* 820 * IMPORTANT: we must leave one free slot in the ring, 821 * so move head back by one unit 822 */ 823 head = nm_prev(head, lim); 824 while (nm_i != head) { 825 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 826 struct netmap_slot *slot = &ring->slot[nm_i]; 827 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 828 uint32_t nic_i_dma = refill_pidx; 829 nic_i = netmap_idx_k2n(kring, nm_i); 830 831 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 832 833 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 834 return netmap_ring_reinit(kring); 835 836 fl->ifl_vm_addrs[tmp_pidx] = addr; 837 if (__predict_false(init) && map) { 838 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 839 } else if (map && (slot->flags & NS_BUF_CHANGED)) { 840 /* buffer has changed, reload map */ 841 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 842 } 843 slot->flags &= ~NS_BUF_CHANGED; 844 845 nm_i = nm_next(nm_i, lim); 846 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 847 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 848 continue; 849 850 iru.iru_pidx = refill_pidx; 851 iru.iru_count = tmp_pidx+1; 852 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 853 854 refill_pidx = nic_i; 855 if (map == NULL) 856 continue; 857 858 for (int n = 0; n < iru.iru_count; n++) { 859 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma], 860 BUS_DMASYNC_PREREAD); 861 /* XXX - change this to not use the netmap func*/ 862 nic_i_dma = nm_next(nic_i_dma, lim); 863 } 864 } 865 } 866 kring->nr_hwcur = head; 867 868 if (map) 869 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 870 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 871 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 872 return (0); 873 } 874 875 /* 876 * Reconcile kernel and user view of the transmit ring. 877 * 878 * All information is in the kring. 879 * Userspace wants to send packets up to the one before kring->rhead, 880 * kernel knows kring->nr_hwcur is the first unsent packet. 881 * 882 * Here we push packets out (as many as possible), and possibly 883 * reclaim buffers from previously completed transmission. 884 * 885 * The caller (netmap) guarantees that there is only one instance 886 * running at any time. Any interference with other driver 887 * methods should be handled by the individual drivers. 888 */ 889 static int 890 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 891 { 892 struct netmap_adapter *na = kring->na; 893 struct ifnet *ifp = na->ifp; 894 struct netmap_ring *ring = kring->ring; 895 u_int nm_i; /* index into the netmap ring */ 896 u_int nic_i; /* index into the NIC ring */ 897 u_int n; 898 u_int const lim = kring->nkr_num_slots - 1; 899 u_int const head = kring->rhead; 900 struct if_pkt_info pi; 901 902 /* 903 * interrupts on every tx packet are expensive so request 904 * them every half ring, or where NS_REPORT is set 905 */ 906 u_int report_frequency = kring->nkr_num_slots >> 1; 907 /* device-specific */ 908 if_ctx_t ctx = ifp->if_softc; 909 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 910 911 if (txq->ift_sds.ifsd_map) 912 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 913 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 914 915 916 /* 917 * First part: process new packets to send. 918 * nm_i is the current index in the netmap ring, 919 * nic_i is the corresponding index in the NIC ring. 920 * 921 * If we have packets to send (nm_i != head) 922 * iterate over the netmap ring, fetch length and update 923 * the corresponding slot in the NIC ring. Some drivers also 924 * need to update the buffer's physical address in the NIC slot 925 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 926 * 927 * The netmap_reload_map() calls is especially expensive, 928 * even when (as in this case) the tag is 0, so do only 929 * when the buffer has actually changed. 930 * 931 * If possible do not set the report/intr bit on all slots, 932 * but only a few times per ring or when NS_REPORT is set. 933 * 934 * Finally, on 10G and faster drivers, it might be useful 935 * to prefetch the next slot and txr entry. 936 */ 937 938 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 939 pkt_info_zero(&pi); 940 pi.ipi_segs = txq->ift_segs; 941 pi.ipi_qsidx = kring->ring_id; 942 if (nm_i != head) { /* we have new packets to send */ 943 nic_i = netmap_idx_k2n(kring, nm_i); 944 945 __builtin_prefetch(&ring->slot[nm_i]); 946 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 947 if (txq->ift_sds.ifsd_map) 948 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 949 950 for (n = 0; nm_i != head; n++) { 951 struct netmap_slot *slot = &ring->slot[nm_i]; 952 u_int len = slot->len; 953 uint64_t paddr; 954 void *addr = PNMB(na, slot, &paddr); 955 int flags = (slot->flags & NS_REPORT || 956 nic_i == 0 || nic_i == report_frequency) ? 957 IPI_TX_INTR : 0; 958 959 /* device-specific */ 960 pi.ipi_len = len; 961 pi.ipi_segs[0].ds_addr = paddr; 962 pi.ipi_segs[0].ds_len = len; 963 pi.ipi_nsegs = 1; 964 pi.ipi_ndescs = 0; 965 pi.ipi_pidx = nic_i; 966 pi.ipi_flags = flags; 967 968 /* Fill the slot in the NIC ring. */ 969 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 970 971 /* prefetch for next round */ 972 __builtin_prefetch(&ring->slot[nm_i + 1]); 973 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 974 if (txq->ift_sds.ifsd_map) { 975 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 976 977 NM_CHECK_ADDR_LEN(na, addr, len); 978 979 if (slot->flags & NS_BUF_CHANGED) { 980 /* buffer has changed, reload map */ 981 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 982 } 983 /* make sure changes to the buffer are synced */ 984 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 985 BUS_DMASYNC_PREWRITE); 986 } 987 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 988 nm_i = nm_next(nm_i, lim); 989 nic_i = nm_next(nic_i, lim); 990 } 991 kring->nr_hwcur = head; 992 993 /* synchronize the NIC ring */ 994 if (txq->ift_sds.ifsd_map) 995 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 996 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 997 998 /* (re)start the tx unit up to slot nic_i (excluded) */ 999 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1000 } 1001 1002 /* 1003 * Second part: reclaim buffers for completed transmissions. 1004 */ 1005 if (iflib_tx_credits_update(ctx, txq)) { 1006 /* some tx completed, increment avail */ 1007 nic_i = txq->ift_cidx_processed; 1008 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1009 } 1010 return (0); 1011 } 1012 1013 /* 1014 * Reconcile kernel and user view of the receive ring. 1015 * Same as for the txsync, this routine must be efficient. 1016 * The caller guarantees a single invocations, but races against 1017 * the rest of the driver should be handled here. 1018 * 1019 * On call, kring->rhead is the first packet that userspace wants 1020 * to keep, and kring->rcur is the wakeup point. 1021 * The kernel has previously reported packets up to kring->rtail. 1022 * 1023 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1024 * of whether or not we received an interrupt. 1025 */ 1026 static int 1027 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1028 { 1029 struct netmap_adapter *na = kring->na; 1030 struct netmap_ring *ring = kring->ring; 1031 uint32_t nm_i; /* index into the netmap ring */ 1032 uint32_t nic_i; /* index into the NIC ring */ 1033 u_int i, n; 1034 u_int const lim = kring->nkr_num_slots - 1; 1035 u_int const head = netmap_idx_n2k(kring, kring->rhead); 1036 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1037 struct if_rxd_info ri; 1038 1039 struct ifnet *ifp = na->ifp; 1040 if_ctx_t ctx = ifp->if_softc; 1041 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1042 iflib_fl_t fl = rxq->ifr_fl; 1043 if (head > lim) 1044 return netmap_ring_reinit(kring); 1045 1046 /* XXX check sync modes */ 1047 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1048 if (fl->ifl_sds.ifsd_map == NULL) 1049 continue; 1050 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 1051 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1052 } 1053 /* 1054 * First part: import newly received packets. 1055 * 1056 * nm_i is the index of the next free slot in the netmap ring, 1057 * nic_i is the index of the next received packet in the NIC ring, 1058 * and they may differ in case if_init() has been called while 1059 * in netmap mode. For the receive ring we have 1060 * 1061 * nic_i = rxr->next_check; 1062 * nm_i = kring->nr_hwtail (previous) 1063 * and 1064 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1065 * 1066 * rxr->next_check is set to 0 on a ring reinit 1067 */ 1068 if (netmap_no_pendintr || force_update) { 1069 int crclen = iflib_crcstrip ? 0 : 4; 1070 int error, avail; 1071 uint16_t slot_flags = kring->nkr_slot_flags; 1072 1073 for (i = 0; i < rxq->ifr_nfl; i++) { 1074 fl = &rxq->ifr_fl[i]; 1075 nic_i = fl->ifl_cidx; 1076 nm_i = netmap_idx_n2k(kring, nic_i); 1077 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 1078 for (n = 0; avail > 0; n++, avail--) { 1079 rxd_info_zero(&ri); 1080 ri.iri_frags = rxq->ifr_frags; 1081 ri.iri_qsidx = kring->ring_id; 1082 ri.iri_ifp = ctx->ifc_ifp; 1083 ri.iri_cidx = nic_i; 1084 1085 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1086 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1087 ring->slot[nm_i].flags = slot_flags; 1088 if (fl->ifl_sds.ifsd_map) 1089 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1090 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1091 nm_i = nm_next(nm_i, lim); 1092 nic_i = nm_next(nic_i, lim); 1093 } 1094 if (n) { /* update the state variables */ 1095 if (netmap_no_pendintr && !force_update) { 1096 /* diagnostics */ 1097 iflib_rx_miss ++; 1098 iflib_rx_miss_bufs += n; 1099 } 1100 fl->ifl_cidx = nic_i; 1101 kring->nr_hwtail = netmap_idx_k2n(kring, nm_i); 1102 } 1103 kring->nr_kflags &= ~NKR_PENDINTR; 1104 } 1105 } 1106 /* 1107 * Second part: skip past packets that userspace has released. 1108 * (kring->nr_hwcur to head excluded), 1109 * and make the buffers available for reception. 1110 * As usual nm_i is the index in the netmap ring, 1111 * nic_i is the index in the NIC ring, and 1112 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1113 */ 1114 /* XXX not sure how this will work with multiple free lists */ 1115 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 1116 1117 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1118 } 1119 1120 static void 1121 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1122 { 1123 struct ifnet *ifp = na->ifp; 1124 if_ctx_t ctx = ifp->if_softc; 1125 1126 CTX_LOCK(ctx); 1127 if (onoff) { 1128 IFDI_INTR_ENABLE(ctx); 1129 } else { 1130 IFDI_INTR_DISABLE(ctx); 1131 } 1132 CTX_UNLOCK(ctx); 1133 } 1134 1135 1136 static int 1137 iflib_netmap_attach(if_ctx_t ctx) 1138 { 1139 struct netmap_adapter na; 1140 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1141 1142 bzero(&na, sizeof(na)); 1143 1144 na.ifp = ctx->ifc_ifp; 1145 na.na_flags = NAF_BDG_MAYSLEEP; 1146 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1147 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1148 1149 na.num_tx_desc = scctx->isc_ntxd[0]; 1150 na.num_rx_desc = scctx->isc_nrxd[0]; 1151 na.nm_txsync = iflib_netmap_txsync; 1152 na.nm_rxsync = iflib_netmap_rxsync; 1153 na.nm_register = iflib_netmap_register; 1154 na.nm_intr = iflib_netmap_intr; 1155 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1156 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1157 return (netmap_attach(&na)); 1158 } 1159 1160 static void 1161 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1162 { 1163 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1164 struct netmap_slot *slot; 1165 1166 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1167 if (slot == NULL) 1168 return; 1169 if (txq->ift_sds.ifsd_map == NULL) 1170 return; 1171 1172 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1173 1174 /* 1175 * In netmap mode, set the map for the packet buffer. 1176 * NOTE: Some drivers (not this one) also need to set 1177 * the physical buffer address in the NIC ring. 1178 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1179 * netmap slot index, si 1180 */ 1181 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i); 1182 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1183 } 1184 } 1185 1186 static void 1187 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1188 { 1189 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1190 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id]; 1191 struct netmap_slot *slot; 1192 uint32_t nm_i; 1193 1194 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1195 if (slot == NULL) 1196 return; 1197 nm_i = netmap_idx_n2k(kring, 0); 1198 netmap_fl_refill(rxq, kring, nm_i, true); 1199 } 1200 1201 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1202 1203 #else 1204 #define iflib_netmap_txq_init(ctx, txq) 1205 #define iflib_netmap_rxq_init(ctx, rxq) 1206 #define iflib_netmap_detach(ifp) 1207 1208 #define iflib_netmap_attach(ctx) (0) 1209 #define netmap_rx_irq(ifp, qid, budget) (0) 1210 #define netmap_tx_irq(ifp, qid) do {} while (0) 1211 1212 #endif 1213 1214 #if defined(__i386__) || defined(__amd64__) 1215 static __inline void 1216 prefetch(void *x) 1217 { 1218 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1219 } 1220 static __inline void 1221 prefetch2cachelines(void *x) 1222 { 1223 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1224 #if (CACHE_LINE_SIZE < 128) 1225 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1226 #endif 1227 } 1228 #else 1229 #define prefetch(x) 1230 #define prefetch2cachelines(x) 1231 #endif 1232 1233 static void 1234 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1235 { 1236 iflib_fl_t fl; 1237 1238 fl = &rxq->ifr_fl[flid]; 1239 iru->iru_paddrs = fl->ifl_bus_addrs; 1240 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1241 iru->iru_idxs = fl->ifl_rxd_idxs; 1242 iru->iru_qsidx = rxq->ifr_id; 1243 iru->iru_buf_size = fl->ifl_buf_size; 1244 iru->iru_flidx = fl->ifl_id; 1245 } 1246 1247 static void 1248 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1249 { 1250 if (err) 1251 return; 1252 *(bus_addr_t *) arg = segs[0].ds_addr; 1253 } 1254 1255 int 1256 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1257 { 1258 int err; 1259 if_shared_ctx_t sctx = ctx->ifc_sctx; 1260 device_t dev = ctx->ifc_dev; 1261 1262 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1263 1264 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1265 sctx->isc_q_align, 0, /* alignment, bounds */ 1266 BUS_SPACE_MAXADDR, /* lowaddr */ 1267 BUS_SPACE_MAXADDR, /* highaddr */ 1268 NULL, NULL, /* filter, filterarg */ 1269 size, /* maxsize */ 1270 1, /* nsegments */ 1271 size, /* maxsegsize */ 1272 BUS_DMA_ALLOCNOW, /* flags */ 1273 NULL, /* lockfunc */ 1274 NULL, /* lockarg */ 1275 &dma->idi_tag); 1276 if (err) { 1277 device_printf(dev, 1278 "%s: bus_dma_tag_create failed: %d\n", 1279 __func__, err); 1280 goto fail_0; 1281 } 1282 1283 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1284 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1285 if (err) { 1286 device_printf(dev, 1287 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1288 __func__, (uintmax_t)size, err); 1289 goto fail_1; 1290 } 1291 1292 dma->idi_paddr = IF_BAD_DMA; 1293 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1294 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1295 if (err || dma->idi_paddr == IF_BAD_DMA) { 1296 device_printf(dev, 1297 "%s: bus_dmamap_load failed: %d\n", 1298 __func__, err); 1299 goto fail_2; 1300 } 1301 1302 dma->idi_size = size; 1303 return (0); 1304 1305 fail_2: 1306 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1307 fail_1: 1308 bus_dma_tag_destroy(dma->idi_tag); 1309 fail_0: 1310 dma->idi_tag = NULL; 1311 1312 return (err); 1313 } 1314 1315 int 1316 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1317 { 1318 int i, err; 1319 iflib_dma_info_t *dmaiter; 1320 1321 dmaiter = dmalist; 1322 for (i = 0; i < count; i++, dmaiter++) { 1323 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1324 break; 1325 } 1326 if (err) 1327 iflib_dma_free_multi(dmalist, i); 1328 return (err); 1329 } 1330 1331 void 1332 iflib_dma_free(iflib_dma_info_t dma) 1333 { 1334 if (dma->idi_tag == NULL) 1335 return; 1336 if (dma->idi_paddr != IF_BAD_DMA) { 1337 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1338 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1339 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1340 dma->idi_paddr = IF_BAD_DMA; 1341 } 1342 if (dma->idi_vaddr != NULL) { 1343 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1344 dma->idi_vaddr = NULL; 1345 } 1346 bus_dma_tag_destroy(dma->idi_tag); 1347 dma->idi_tag = NULL; 1348 } 1349 1350 void 1351 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1352 { 1353 int i; 1354 iflib_dma_info_t *dmaiter = dmalist; 1355 1356 for (i = 0; i < count; i++, dmaiter++) 1357 iflib_dma_free(*dmaiter); 1358 } 1359 1360 #ifdef EARLY_AP_STARTUP 1361 static const int iflib_started = 1; 1362 #else 1363 /* 1364 * We used to abuse the smp_started flag to decide if the queues have been 1365 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1366 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1367 * is set. Run a SYSINIT() strictly after that to just set a usable 1368 * completion flag. 1369 */ 1370 1371 static int iflib_started; 1372 1373 static void 1374 iflib_record_started(void *arg) 1375 { 1376 iflib_started = 1; 1377 } 1378 1379 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1380 iflib_record_started, NULL); 1381 #endif 1382 1383 static int 1384 iflib_fast_intr(void *arg) 1385 { 1386 iflib_filter_info_t info = arg; 1387 struct grouptask *gtask = info->ifi_task; 1388 if (!iflib_started) 1389 return (FILTER_HANDLED); 1390 1391 DBG_COUNTER_INC(fast_intrs); 1392 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1393 return (FILTER_HANDLED); 1394 1395 GROUPTASK_ENQUEUE(gtask); 1396 return (FILTER_HANDLED); 1397 } 1398 1399 static int 1400 iflib_fast_intr_rxtx(void *arg) 1401 { 1402 iflib_filter_info_t info = arg; 1403 struct grouptask *gtask = info->ifi_task; 1404 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1405 if_ctx_t ctx; 1406 int i, cidx; 1407 1408 if (!iflib_started) 1409 return (FILTER_HANDLED); 1410 1411 DBG_COUNTER_INC(fast_intrs); 1412 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1413 return (FILTER_HANDLED); 1414 1415 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1416 qidx_t txqid = rxq->ifr_txqid[i]; 1417 1418 ctx = rxq->ifr_ctx; 1419 1420 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1421 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1422 continue; 1423 } 1424 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1425 } 1426 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1427 cidx = rxq->ifr_cq_cidx; 1428 else 1429 cidx = rxq->ifr_fl[0].ifl_cidx; 1430 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1431 GROUPTASK_ENQUEUE(gtask); 1432 else 1433 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1434 return (FILTER_HANDLED); 1435 } 1436 1437 1438 static int 1439 iflib_fast_intr_ctx(void *arg) 1440 { 1441 iflib_filter_info_t info = arg; 1442 struct grouptask *gtask = info->ifi_task; 1443 1444 if (!iflib_started) 1445 return (FILTER_HANDLED); 1446 1447 DBG_COUNTER_INC(fast_intrs); 1448 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1449 return (FILTER_HANDLED); 1450 1451 GROUPTASK_ENQUEUE(gtask); 1452 return (FILTER_HANDLED); 1453 } 1454 1455 static int 1456 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1457 driver_filter_t filter, driver_intr_t handler, void *arg, 1458 char *name) 1459 { 1460 int rc, flags; 1461 struct resource *res; 1462 void *tag = NULL; 1463 device_t dev = ctx->ifc_dev; 1464 1465 flags = RF_ACTIVE; 1466 if (ctx->ifc_flags & IFC_LEGACY) 1467 flags |= RF_SHAREABLE; 1468 MPASS(rid < 512); 1469 irq->ii_rid = rid; 1470 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1471 if (res == NULL) { 1472 device_printf(dev, 1473 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1474 return (ENOMEM); 1475 } 1476 irq->ii_res = res; 1477 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1478 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1479 filter, handler, arg, &tag); 1480 if (rc != 0) { 1481 device_printf(dev, 1482 "failed to setup interrupt for rid %d, name %s: %d\n", 1483 rid, name ? name : "unknown", rc); 1484 return (rc); 1485 } else if (name) 1486 bus_describe_intr(dev, res, tag, "%s", name); 1487 1488 irq->ii_tag = tag; 1489 return (0); 1490 } 1491 1492 1493 /********************************************************************* 1494 * 1495 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1496 * the information needed to transmit a packet on the wire. This is 1497 * called only once at attach, setup is done every reset. 1498 * 1499 **********************************************************************/ 1500 1501 static int 1502 iflib_txsd_alloc(iflib_txq_t txq) 1503 { 1504 if_ctx_t ctx = txq->ift_ctx; 1505 if_shared_ctx_t sctx = ctx->ifc_sctx; 1506 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1507 device_t dev = ctx->ifc_dev; 1508 int err, nsegments, ntsosegments; 1509 1510 nsegments = scctx->isc_tx_nsegments; 1511 ntsosegments = scctx->isc_tx_tso_segments_max; 1512 MPASS(scctx->isc_ntxd[0] > 0); 1513 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1514 MPASS(nsegments > 0); 1515 MPASS(ntsosegments > 0); 1516 /* 1517 * Setup DMA descriptor areas. 1518 */ 1519 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1520 1, 0, /* alignment, bounds */ 1521 BUS_SPACE_MAXADDR, /* lowaddr */ 1522 BUS_SPACE_MAXADDR, /* highaddr */ 1523 NULL, NULL, /* filter, filterarg */ 1524 sctx->isc_tx_maxsize, /* maxsize */ 1525 nsegments, /* nsegments */ 1526 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1527 0, /* flags */ 1528 NULL, /* lockfunc */ 1529 NULL, /* lockfuncarg */ 1530 &txq->ift_desc_tag))) { 1531 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1532 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1533 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1534 goto fail; 1535 } 1536 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1537 1, 0, /* alignment, bounds */ 1538 BUS_SPACE_MAXADDR, /* lowaddr */ 1539 BUS_SPACE_MAXADDR, /* highaddr */ 1540 NULL, NULL, /* filter, filterarg */ 1541 scctx->isc_tx_tso_size_max, /* maxsize */ 1542 ntsosegments, /* nsegments */ 1543 scctx->isc_tx_tso_segsize_max, /* maxsegsize */ 1544 0, /* flags */ 1545 NULL, /* lockfunc */ 1546 NULL, /* lockfuncarg */ 1547 &txq->ift_tso_desc_tag))) { 1548 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1549 1550 goto fail; 1551 } 1552 if (!(txq->ift_sds.ifsd_flags = 1553 (uint8_t *) malloc(sizeof(uint8_t) * 1554 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1555 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1556 err = ENOMEM; 1557 goto fail; 1558 } 1559 if (!(txq->ift_sds.ifsd_m = 1560 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1561 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1562 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1563 err = ENOMEM; 1564 goto fail; 1565 } 1566 1567 /* Create the descriptor buffer dma maps */ 1568 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1569 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1570 return (0); 1571 1572 if (!(txq->ift_sds.ifsd_map = 1573 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1574 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1575 err = ENOMEM; 1576 goto fail; 1577 } 1578 1579 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1580 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1581 if (err != 0) { 1582 device_printf(dev, "Unable to create TX DMA map\n"); 1583 goto fail; 1584 } 1585 } 1586 #endif 1587 return (0); 1588 fail: 1589 /* We free all, it handles case where we are in the middle */ 1590 iflib_tx_structures_free(ctx); 1591 return (err); 1592 } 1593 1594 static void 1595 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1596 { 1597 bus_dmamap_t map; 1598 1599 map = NULL; 1600 if (txq->ift_sds.ifsd_map != NULL) 1601 map = txq->ift_sds.ifsd_map[i]; 1602 if (map != NULL) { 1603 bus_dmamap_unload(txq->ift_desc_tag, map); 1604 bus_dmamap_destroy(txq->ift_desc_tag, map); 1605 txq->ift_sds.ifsd_map[i] = NULL; 1606 } 1607 } 1608 1609 static void 1610 iflib_txq_destroy(iflib_txq_t txq) 1611 { 1612 if_ctx_t ctx = txq->ift_ctx; 1613 1614 for (int i = 0; i < txq->ift_size; i++) 1615 iflib_txsd_destroy(ctx, txq, i); 1616 if (txq->ift_sds.ifsd_map != NULL) { 1617 free(txq->ift_sds.ifsd_map, M_IFLIB); 1618 txq->ift_sds.ifsd_map = NULL; 1619 } 1620 if (txq->ift_sds.ifsd_m != NULL) { 1621 free(txq->ift_sds.ifsd_m, M_IFLIB); 1622 txq->ift_sds.ifsd_m = NULL; 1623 } 1624 if (txq->ift_sds.ifsd_flags != NULL) { 1625 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1626 txq->ift_sds.ifsd_flags = NULL; 1627 } 1628 if (txq->ift_desc_tag != NULL) { 1629 bus_dma_tag_destroy(txq->ift_desc_tag); 1630 txq->ift_desc_tag = NULL; 1631 } 1632 if (txq->ift_tso_desc_tag != NULL) { 1633 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1634 txq->ift_tso_desc_tag = NULL; 1635 } 1636 } 1637 1638 static void 1639 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1640 { 1641 struct mbuf **mp; 1642 1643 mp = &txq->ift_sds.ifsd_m[i]; 1644 if (*mp == NULL) 1645 return; 1646 1647 if (txq->ift_sds.ifsd_map != NULL) { 1648 bus_dmamap_sync(txq->ift_desc_tag, 1649 txq->ift_sds.ifsd_map[i], 1650 BUS_DMASYNC_POSTWRITE); 1651 bus_dmamap_unload(txq->ift_desc_tag, 1652 txq->ift_sds.ifsd_map[i]); 1653 } 1654 m_free(*mp); 1655 DBG_COUNTER_INC(tx_frees); 1656 *mp = NULL; 1657 } 1658 1659 static int 1660 iflib_txq_setup(iflib_txq_t txq) 1661 { 1662 if_ctx_t ctx = txq->ift_ctx; 1663 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1664 iflib_dma_info_t di; 1665 int i; 1666 1667 /* Set number of descriptors available */ 1668 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1669 /* XXX make configurable */ 1670 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1671 1672 /* Reset indices */ 1673 txq->ift_cidx_processed = 0; 1674 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1675 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1676 1677 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1678 bzero((void *)di->idi_vaddr, di->idi_size); 1679 1680 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1681 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1682 bus_dmamap_sync(di->idi_tag, di->idi_map, 1683 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1684 return (0); 1685 } 1686 1687 /********************************************************************* 1688 * 1689 * Allocate memory for rx_buffer structures. Since we use one 1690 * rx_buffer per received packet, the maximum number of rx_buffer's 1691 * that we'll need is equal to the number of receive descriptors 1692 * that we've allocated. 1693 * 1694 **********************************************************************/ 1695 static int 1696 iflib_rxsd_alloc(iflib_rxq_t rxq) 1697 { 1698 if_ctx_t ctx = rxq->ifr_ctx; 1699 if_shared_ctx_t sctx = ctx->ifc_sctx; 1700 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1701 device_t dev = ctx->ifc_dev; 1702 iflib_fl_t fl; 1703 int err; 1704 1705 MPASS(scctx->isc_nrxd[0] > 0); 1706 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1707 1708 fl = rxq->ifr_fl; 1709 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1710 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1711 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1712 1, 0, /* alignment, bounds */ 1713 BUS_SPACE_MAXADDR, /* lowaddr */ 1714 BUS_SPACE_MAXADDR, /* highaddr */ 1715 NULL, NULL, /* filter, filterarg */ 1716 sctx->isc_rx_maxsize, /* maxsize */ 1717 sctx->isc_rx_nsegments, /* nsegments */ 1718 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1719 0, /* flags */ 1720 NULL, /* lockfunc */ 1721 NULL, /* lockarg */ 1722 &fl->ifl_desc_tag); 1723 if (err) { 1724 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1725 __func__, err); 1726 goto fail; 1727 } 1728 if (!(fl->ifl_sds.ifsd_flags = 1729 (uint8_t *) malloc(sizeof(uint8_t) * 1730 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1731 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1732 err = ENOMEM; 1733 goto fail; 1734 } 1735 if (!(fl->ifl_sds.ifsd_m = 1736 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1737 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1738 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1739 err = ENOMEM; 1740 goto fail; 1741 } 1742 if (!(fl->ifl_sds.ifsd_cl = 1743 (caddr_t *) malloc(sizeof(caddr_t) * 1744 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1745 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1746 err = ENOMEM; 1747 goto fail; 1748 } 1749 1750 /* Create the descriptor buffer dma maps */ 1751 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1752 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1753 continue; 1754 1755 if (!(fl->ifl_sds.ifsd_map = 1756 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1757 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1758 err = ENOMEM; 1759 goto fail; 1760 } 1761 1762 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1763 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1764 if (err != 0) { 1765 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1766 goto fail; 1767 } 1768 } 1769 #endif 1770 } 1771 return (0); 1772 1773 fail: 1774 iflib_rx_structures_free(ctx); 1775 return (err); 1776 } 1777 1778 1779 /* 1780 * Internal service routines 1781 */ 1782 1783 struct rxq_refill_cb_arg { 1784 int error; 1785 bus_dma_segment_t seg; 1786 int nseg; 1787 }; 1788 1789 static void 1790 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1791 { 1792 struct rxq_refill_cb_arg *cb_arg = arg; 1793 1794 cb_arg->error = error; 1795 cb_arg->seg = segs[0]; 1796 cb_arg->nseg = nseg; 1797 } 1798 1799 1800 #ifdef ACPI_DMAR 1801 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1802 #else 1803 #define IS_DMAR(ctx) (0) 1804 #endif 1805 1806 /** 1807 * rxq_refill - refill an rxq free-buffer list 1808 * @ctx: the iflib context 1809 * @rxq: the free-list to refill 1810 * @n: the number of new buffers to allocate 1811 * 1812 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1813 * The caller must assure that @n does not exceed the queue's capacity. 1814 */ 1815 static void 1816 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1817 { 1818 struct mbuf *m; 1819 int idx, frag_idx = fl->ifl_fragidx; 1820 int pidx = fl->ifl_pidx; 1821 caddr_t cl, *sd_cl; 1822 struct mbuf **sd_m; 1823 uint8_t *sd_flags; 1824 struct if_rxd_update iru; 1825 bus_dmamap_t *sd_map; 1826 int n, i = 0; 1827 uint64_t bus_addr; 1828 int err; 1829 qidx_t credits; 1830 1831 sd_m = fl->ifl_sds.ifsd_m; 1832 sd_map = fl->ifl_sds.ifsd_map; 1833 sd_cl = fl->ifl_sds.ifsd_cl; 1834 sd_flags = fl->ifl_sds.ifsd_flags; 1835 idx = pidx; 1836 credits = fl->ifl_credits; 1837 1838 n = count; 1839 MPASS(n > 0); 1840 MPASS(credits + n <= fl->ifl_size); 1841 1842 if (pidx < fl->ifl_cidx) 1843 MPASS(pidx + n <= fl->ifl_cidx); 1844 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1845 MPASS(fl->ifl_gen == 0); 1846 if (pidx > fl->ifl_cidx) 1847 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1848 1849 DBG_COUNTER_INC(fl_refills); 1850 if (n > 8) 1851 DBG_COUNTER_INC(fl_refills_large); 1852 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1853 while (n--) { 1854 /* 1855 * We allocate an uninitialized mbuf + cluster, mbuf is 1856 * initialized after rx. 1857 * 1858 * If the cluster is still set then we know a minimum sized packet was received 1859 */ 1860 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1861 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1862 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1863 if ((cl = sd_cl[frag_idx]) == NULL) { 1864 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1865 break; 1866 #if MEMORY_LOGGING 1867 fl->ifl_cl_enqueued++; 1868 #endif 1869 } 1870 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1871 break; 1872 } 1873 #if MEMORY_LOGGING 1874 fl->ifl_m_enqueued++; 1875 #endif 1876 1877 DBG_COUNTER_INC(rx_allocs); 1878 #if defined(__i386__) || defined(__amd64__) 1879 if (!IS_DMAR(ctx)) { 1880 bus_addr = pmap_kextract((vm_offset_t)cl); 1881 } else 1882 #endif 1883 { 1884 struct rxq_refill_cb_arg cb_arg; 1885 iflib_rxq_t q; 1886 1887 cb_arg.error = 0; 1888 q = fl->ifl_rxq; 1889 MPASS(sd_map != NULL); 1890 MPASS(sd_map[frag_idx] != NULL); 1891 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1892 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1893 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 1894 BUS_DMASYNC_PREREAD); 1895 1896 if (err != 0 || cb_arg.error) { 1897 /* 1898 * !zone_pack ? 1899 */ 1900 if (fl->ifl_zone == zone_pack) 1901 uma_zfree(fl->ifl_zone, cl); 1902 m_free(m); 1903 n = 0; 1904 goto done; 1905 } 1906 bus_addr = cb_arg.seg.ds_addr; 1907 } 1908 bit_set(fl->ifl_rx_bitmap, frag_idx); 1909 sd_flags[frag_idx] |= RX_SW_DESC_INUSE; 1910 1911 MPASS(sd_m[frag_idx] == NULL); 1912 sd_cl[frag_idx] = cl; 1913 sd_m[frag_idx] = m; 1914 fl->ifl_rxd_idxs[i] = frag_idx; 1915 fl->ifl_bus_addrs[i] = bus_addr; 1916 fl->ifl_vm_addrs[i] = cl; 1917 credits++; 1918 i++; 1919 MPASS(credits <= fl->ifl_size); 1920 if (++idx == fl->ifl_size) { 1921 fl->ifl_gen = 1; 1922 idx = 0; 1923 } 1924 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 1925 iru.iru_pidx = pidx; 1926 iru.iru_count = i; 1927 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1928 i = 0; 1929 pidx = idx; 1930 fl->ifl_pidx = idx; 1931 fl->ifl_credits = credits; 1932 } 1933 1934 } 1935 done: 1936 if (i) { 1937 iru.iru_pidx = pidx; 1938 iru.iru_count = i; 1939 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1940 fl->ifl_pidx = idx; 1941 fl->ifl_credits = credits; 1942 } 1943 DBG_COUNTER_INC(rxd_flush); 1944 if (fl->ifl_pidx == 0) 1945 pidx = fl->ifl_size - 1; 1946 else 1947 pidx = fl->ifl_pidx - 1; 1948 1949 if (sd_map) 1950 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1951 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1952 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 1953 fl->ifl_fragidx = frag_idx; 1954 } 1955 1956 static __inline void 1957 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 1958 { 1959 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 1960 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 1961 #ifdef INVARIANTS 1962 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 1963 #endif 1964 1965 MPASS(fl->ifl_credits <= fl->ifl_size); 1966 MPASS(reclaimable == delta); 1967 1968 if (reclaimable > 0) 1969 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 1970 } 1971 1972 static void 1973 iflib_fl_bufs_free(iflib_fl_t fl) 1974 { 1975 iflib_dma_info_t idi = fl->ifl_ifdi; 1976 uint32_t i; 1977 1978 for (i = 0; i < fl->ifl_size; i++) { 1979 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 1980 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 1981 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 1982 1983 if (*sd_flags & RX_SW_DESC_INUSE) { 1984 if (fl->ifl_sds.ifsd_map != NULL) { 1985 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 1986 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 1987 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 1988 } 1989 if (*sd_m != NULL) { 1990 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 1991 uma_zfree(zone_mbuf, *sd_m); 1992 } 1993 if (*sd_cl != NULL) 1994 uma_zfree(fl->ifl_zone, *sd_cl); 1995 *sd_flags = 0; 1996 } else { 1997 MPASS(*sd_cl == NULL); 1998 MPASS(*sd_m == NULL); 1999 } 2000 #if MEMORY_LOGGING 2001 fl->ifl_m_dequeued++; 2002 fl->ifl_cl_dequeued++; 2003 #endif 2004 *sd_cl = NULL; 2005 *sd_m = NULL; 2006 } 2007 #ifdef INVARIANTS 2008 for (i = 0; i < fl->ifl_size; i++) { 2009 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 2010 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2011 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2012 } 2013 #endif 2014 /* 2015 * Reset free list values 2016 */ 2017 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2018 bzero(idi->idi_vaddr, idi->idi_size); 2019 } 2020 2021 /********************************************************************* 2022 * 2023 * Initialize a receive ring and its buffers. 2024 * 2025 **********************************************************************/ 2026 static int 2027 iflib_fl_setup(iflib_fl_t fl) 2028 { 2029 iflib_rxq_t rxq = fl->ifl_rxq; 2030 if_ctx_t ctx = rxq->ifr_ctx; 2031 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2032 2033 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2034 /* 2035 ** Free current RX buffer structs and their mbufs 2036 */ 2037 iflib_fl_bufs_free(fl); 2038 /* Now replenish the mbufs */ 2039 MPASS(fl->ifl_credits == 0); 2040 /* 2041 * XXX don't set the max_frame_size to larger 2042 * than the hardware can handle 2043 */ 2044 if (sctx->isc_max_frame_size <= 2048) 2045 fl->ifl_buf_size = MCLBYTES; 2046 #ifndef CONTIGMALLOC_WORKS 2047 else 2048 fl->ifl_buf_size = MJUMPAGESIZE; 2049 #else 2050 else if (sctx->isc_max_frame_size <= 4096) 2051 fl->ifl_buf_size = MJUMPAGESIZE; 2052 else if (sctx->isc_max_frame_size <= 9216) 2053 fl->ifl_buf_size = MJUM9BYTES; 2054 else 2055 fl->ifl_buf_size = MJUM16BYTES; 2056 #endif 2057 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2058 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2059 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2060 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2061 2062 2063 /* avoid pre-allocating zillions of clusters to an idle card 2064 * potentially speeding up attach 2065 */ 2066 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2067 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2068 if (min(128, fl->ifl_size) != fl->ifl_credits) 2069 return (ENOBUFS); 2070 /* 2071 * handle failure 2072 */ 2073 MPASS(rxq != NULL); 2074 MPASS(fl->ifl_ifdi != NULL); 2075 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2076 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2077 return (0); 2078 } 2079 2080 /********************************************************************* 2081 * 2082 * Free receive ring data structures 2083 * 2084 **********************************************************************/ 2085 static void 2086 iflib_rx_sds_free(iflib_rxq_t rxq) 2087 { 2088 iflib_fl_t fl; 2089 int i; 2090 2091 if (rxq->ifr_fl != NULL) { 2092 for (i = 0; i < rxq->ifr_nfl; i++) { 2093 fl = &rxq->ifr_fl[i]; 2094 if (fl->ifl_desc_tag != NULL) { 2095 bus_dma_tag_destroy(fl->ifl_desc_tag); 2096 fl->ifl_desc_tag = NULL; 2097 } 2098 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2099 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2100 /* XXX destroy maps first */ 2101 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2102 fl->ifl_sds.ifsd_m = NULL; 2103 fl->ifl_sds.ifsd_cl = NULL; 2104 fl->ifl_sds.ifsd_map = NULL; 2105 } 2106 free(rxq->ifr_fl, M_IFLIB); 2107 rxq->ifr_fl = NULL; 2108 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2109 } 2110 } 2111 2112 /* 2113 * MI independent logic 2114 * 2115 */ 2116 static void 2117 iflib_timer(void *arg) 2118 { 2119 iflib_txq_t txq = arg; 2120 if_ctx_t ctx = txq->ift_ctx; 2121 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2122 2123 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2124 return; 2125 /* 2126 ** Check on the state of the TX queue(s), this 2127 ** can be done without the lock because its RO 2128 ** and the HUNG state will be static if set. 2129 */ 2130 IFDI_TIMER(ctx, txq->ift_id); 2131 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2132 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2133 (sctx->isc_pause_frames == 0))) 2134 goto hung; 2135 2136 if (ifmp_ring_is_stalled(txq->ift_br)) 2137 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2138 txq->ift_cleaned_prev = txq->ift_cleaned; 2139 /* handle any laggards */ 2140 if (txq->ift_db_pending) 2141 GROUPTASK_ENQUEUE(&txq->ift_task); 2142 2143 sctx->isc_pause_frames = 0; 2144 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2145 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 2146 return; 2147 hung: 2148 CTX_LOCK(ctx); 2149 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2150 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2151 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2152 2153 IFDI_WATCHDOG_RESET(ctx); 2154 ctx->ifc_watchdog_events++; 2155 2156 ctx->ifc_flags |= IFC_DO_RESET; 2157 iflib_admin_intr_deferred(ctx); 2158 CTX_UNLOCK(ctx); 2159 } 2160 2161 static void 2162 iflib_init_locked(if_ctx_t ctx) 2163 { 2164 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2165 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2166 if_t ifp = ctx->ifc_ifp; 2167 iflib_fl_t fl; 2168 iflib_txq_t txq; 2169 iflib_rxq_t rxq; 2170 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2171 2172 2173 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2174 IFDI_INTR_DISABLE(ctx); 2175 2176 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2177 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2178 /* Set hardware offload abilities */ 2179 if_clearhwassist(ifp); 2180 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2181 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2182 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2183 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2184 if (if_getcapenable(ifp) & IFCAP_TSO4) 2185 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2186 if (if_getcapenable(ifp) & IFCAP_TSO6) 2187 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2188 2189 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2190 CALLOUT_LOCK(txq); 2191 callout_stop(&txq->ift_timer); 2192 CALLOUT_UNLOCK(txq); 2193 iflib_netmap_txq_init(ctx, txq); 2194 } 2195 #ifdef INVARIANTS 2196 i = if_getdrvflags(ifp); 2197 #endif 2198 IFDI_INIT(ctx); 2199 MPASS(if_getdrvflags(ifp) == i); 2200 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2201 /* XXX this should really be done on a per-queue basis */ 2202 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2203 MPASS(rxq->ifr_id == i); 2204 iflib_netmap_rxq_init(ctx, rxq); 2205 continue; 2206 } 2207 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2208 if (iflib_fl_setup(fl)) { 2209 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2210 goto done; 2211 } 2212 } 2213 } 2214 done: 2215 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2216 IFDI_INTR_ENABLE(ctx); 2217 txq = ctx->ifc_txqs; 2218 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2219 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2220 txq->ift_timer.c_cpu); 2221 } 2222 2223 static int 2224 iflib_media_change(if_t ifp) 2225 { 2226 if_ctx_t ctx = if_getsoftc(ifp); 2227 int err; 2228 2229 CTX_LOCK(ctx); 2230 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2231 iflib_init_locked(ctx); 2232 CTX_UNLOCK(ctx); 2233 return (err); 2234 } 2235 2236 static void 2237 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2238 { 2239 if_ctx_t ctx = if_getsoftc(ifp); 2240 2241 CTX_LOCK(ctx); 2242 IFDI_UPDATE_ADMIN_STATUS(ctx); 2243 IFDI_MEDIA_STATUS(ctx, ifmr); 2244 CTX_UNLOCK(ctx); 2245 } 2246 2247 static void 2248 iflib_stop(if_ctx_t ctx) 2249 { 2250 iflib_txq_t txq = ctx->ifc_txqs; 2251 iflib_rxq_t rxq = ctx->ifc_rxqs; 2252 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2253 iflib_dma_info_t di; 2254 iflib_fl_t fl; 2255 int i, j; 2256 2257 /* Tell the stack that the interface is no longer active */ 2258 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2259 2260 IFDI_INTR_DISABLE(ctx); 2261 DELAY(1000); 2262 IFDI_STOP(ctx); 2263 DELAY(1000); 2264 2265 iflib_debug_reset(); 2266 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2267 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2268 /* make sure all transmitters have completed before proceeding XXX */ 2269 2270 /* clean any enqueued buffers */ 2271 iflib_ifmp_purge(txq); 2272 /* Free any existing tx buffers. */ 2273 for (j = 0; j < txq->ift_size; j++) { 2274 iflib_txsd_free(ctx, txq, j); 2275 } 2276 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2277 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2278 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2279 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2280 txq->ift_pullups = 0; 2281 ifmp_ring_reset_stats(txq->ift_br); 2282 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2283 bzero((void *)di->idi_vaddr, di->idi_size); 2284 } 2285 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2286 /* make sure all transmitters have completed before proceeding XXX */ 2287 2288 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++) 2289 bzero((void *)di->idi_vaddr, di->idi_size); 2290 /* also resets the free lists pidx/cidx */ 2291 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2292 iflib_fl_bufs_free(fl); 2293 } 2294 } 2295 2296 static inline caddr_t 2297 calc_next_rxd(iflib_fl_t fl, int cidx) 2298 { 2299 qidx_t size; 2300 int nrxd; 2301 caddr_t start, end, cur, next; 2302 2303 nrxd = fl->ifl_size; 2304 size = fl->ifl_rxd_size; 2305 start = fl->ifl_ifdi->idi_vaddr; 2306 2307 if (__predict_false(size == 0)) 2308 return (start); 2309 cur = start + size*cidx; 2310 end = start + size*nrxd; 2311 next = CACHE_PTR_NEXT(cur); 2312 return (next < end ? next : start); 2313 } 2314 2315 static inline void 2316 prefetch_pkts(iflib_fl_t fl, int cidx) 2317 { 2318 int nextptr; 2319 int nrxd = fl->ifl_size; 2320 caddr_t next_rxd; 2321 2322 2323 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2324 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2325 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2326 next_rxd = calc_next_rxd(fl, cidx); 2327 prefetch(next_rxd); 2328 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2329 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2330 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2331 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2332 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2333 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2334 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2335 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2336 } 2337 2338 static void 2339 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2340 { 2341 int flid, cidx; 2342 bus_dmamap_t map; 2343 iflib_fl_t fl; 2344 iflib_dma_info_t di; 2345 int next; 2346 2347 map = NULL; 2348 flid = irf->irf_flid; 2349 cidx = irf->irf_idx; 2350 fl = &rxq->ifr_fl[flid]; 2351 sd->ifsd_fl = fl; 2352 sd->ifsd_cidx = cidx; 2353 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2354 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2355 fl->ifl_credits--; 2356 #if MEMORY_LOGGING 2357 fl->ifl_m_dequeued++; 2358 #endif 2359 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2360 prefetch_pkts(fl, cidx); 2361 if (fl->ifl_sds.ifsd_map != NULL) { 2362 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2363 prefetch(&fl->ifl_sds.ifsd_map[next]); 2364 map = fl->ifl_sds.ifsd_map[cidx]; 2365 di = fl->ifl_ifdi; 2366 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2367 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2368 bus_dmamap_sync(di->idi_tag, di->idi_map, 2369 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2370 2371 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2372 MPASS(fl->ifl_cidx == cidx); 2373 if (unload) 2374 bus_dmamap_unload(fl->ifl_desc_tag, map); 2375 } 2376 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2377 if (__predict_false(fl->ifl_cidx == 0)) 2378 fl->ifl_gen = 0; 2379 if (map != NULL) 2380 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2381 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2382 bit_clear(fl->ifl_rx_bitmap, cidx); 2383 } 2384 2385 static struct mbuf * 2386 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2387 { 2388 int i, padlen , flags; 2389 struct mbuf *m, *mh, *mt; 2390 caddr_t cl; 2391 2392 i = 0; 2393 mh = NULL; 2394 do { 2395 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2396 2397 MPASS(*sd->ifsd_cl != NULL); 2398 MPASS(*sd->ifsd_m != NULL); 2399 2400 /* Don't include zero-length frags */ 2401 if (ri->iri_frags[i].irf_len == 0) { 2402 /* XXX we can save the cluster here, but not the mbuf */ 2403 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2404 m_free(*sd->ifsd_m); 2405 *sd->ifsd_m = NULL; 2406 continue; 2407 } 2408 m = *sd->ifsd_m; 2409 *sd->ifsd_m = NULL; 2410 if (mh == NULL) { 2411 flags = M_PKTHDR|M_EXT; 2412 mh = mt = m; 2413 padlen = ri->iri_pad; 2414 } else { 2415 flags = M_EXT; 2416 mt->m_next = m; 2417 mt = m; 2418 /* assuming padding is only on the first fragment */ 2419 padlen = 0; 2420 } 2421 cl = *sd->ifsd_cl; 2422 *sd->ifsd_cl = NULL; 2423 2424 /* Can these two be made one ? */ 2425 m_init(m, M_NOWAIT, MT_DATA, flags); 2426 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2427 /* 2428 * These must follow m_init and m_cljset 2429 */ 2430 m->m_data += padlen; 2431 ri->iri_len -= padlen; 2432 m->m_len = ri->iri_frags[i].irf_len; 2433 } while (++i < ri->iri_nfrags); 2434 2435 return (mh); 2436 } 2437 2438 /* 2439 * Process one software descriptor 2440 */ 2441 static struct mbuf * 2442 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2443 { 2444 struct if_rxsd sd; 2445 struct mbuf *m; 2446 2447 /* should I merge this back in now that the two paths are basically duplicated? */ 2448 if (ri->iri_nfrags == 1 && 2449 ri->iri_frags[0].irf_len <= IFLIB_RX_COPY_THRESH) { 2450 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2451 m = *sd.ifsd_m; 2452 *sd.ifsd_m = NULL; 2453 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2454 #ifndef __NO_STRICT_ALIGNMENT 2455 if (!IP_ALIGNED(m)) 2456 m->m_data += 2; 2457 #endif 2458 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2459 m->m_len = ri->iri_frags[0].irf_len; 2460 } else { 2461 m = assemble_segments(rxq, ri, &sd); 2462 } 2463 m->m_pkthdr.len = ri->iri_len; 2464 m->m_pkthdr.rcvif = ri->iri_ifp; 2465 m->m_flags |= ri->iri_flags; 2466 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2467 m->m_pkthdr.flowid = ri->iri_flowid; 2468 M_HASHTYPE_SET(m, ri->iri_rsstype); 2469 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2470 m->m_pkthdr.csum_data = ri->iri_csum_data; 2471 return (m); 2472 } 2473 2474 #if defined(INET6) || defined(INET) 2475 static void 2476 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2477 { 2478 CURVNET_SET(lc->ifp->if_vnet); 2479 #if defined(INET6) 2480 *v6 = VNET(ip6_forwarding); 2481 #endif 2482 #if defined(INET) 2483 *v4 = VNET(ipforwarding); 2484 #endif 2485 CURVNET_RESTORE(); 2486 } 2487 2488 /* 2489 * Returns true if it's possible this packet could be LROed. 2490 * if it returns false, it is guaranteed that tcp_lro_rx() 2491 * would not return zero. 2492 */ 2493 static bool 2494 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2495 { 2496 struct ether_header *eh; 2497 uint16_t eh_type; 2498 2499 eh = mtod(m, struct ether_header *); 2500 eh_type = ntohs(eh->ether_type); 2501 switch (eh_type) { 2502 #if defined(INET6) 2503 case ETHERTYPE_IPV6: 2504 return !v6_forwarding; 2505 #endif 2506 #if defined (INET) 2507 case ETHERTYPE_IP: 2508 return !v4_forwarding; 2509 #endif 2510 } 2511 2512 return false; 2513 } 2514 #else 2515 static void 2516 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2517 { 2518 } 2519 #endif 2520 2521 static bool 2522 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2523 { 2524 if_ctx_t ctx = rxq->ifr_ctx; 2525 if_shared_ctx_t sctx = ctx->ifc_sctx; 2526 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2527 int avail, i; 2528 qidx_t *cidxp; 2529 struct if_rxd_info ri; 2530 int err, budget_left, rx_bytes, rx_pkts; 2531 iflib_fl_t fl; 2532 struct ifnet *ifp; 2533 int lro_enabled; 2534 bool lro_possible = false; 2535 bool v4_forwarding, v6_forwarding; 2536 2537 /* 2538 * XXX early demux data packets so that if_input processing only handles 2539 * acks in interrupt context 2540 */ 2541 struct mbuf *m, *mh, *mt, *mf; 2542 2543 ifp = ctx->ifc_ifp; 2544 mh = mt = NULL; 2545 MPASS(budget > 0); 2546 rx_pkts = rx_bytes = 0; 2547 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2548 cidxp = &rxq->ifr_cq_cidx; 2549 else 2550 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2551 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2552 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2553 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2554 DBG_COUNTER_INC(rx_unavail); 2555 return (false); 2556 } 2557 2558 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2559 if (__predict_false(!CTX_ACTIVE(ctx))) { 2560 DBG_COUNTER_INC(rx_ctx_inactive); 2561 break; 2562 } 2563 /* 2564 * Reset client set fields to their default values 2565 */ 2566 rxd_info_zero(&ri); 2567 ri.iri_qsidx = rxq->ifr_id; 2568 ri.iri_cidx = *cidxp; 2569 ri.iri_ifp = ifp; 2570 ri.iri_frags = rxq->ifr_frags; 2571 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2572 2573 if (err) 2574 goto err; 2575 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2576 *cidxp = ri.iri_cidx; 2577 /* Update our consumer index */ 2578 /* XXX NB: shurd - check if this is still safe */ 2579 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2580 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2581 rxq->ifr_cq_gen = 0; 2582 } 2583 /* was this only a completion queue message? */ 2584 if (__predict_false(ri.iri_nfrags == 0)) 2585 continue; 2586 } 2587 MPASS(ri.iri_nfrags != 0); 2588 MPASS(ri.iri_len != 0); 2589 2590 /* will advance the cidx on the corresponding free lists */ 2591 m = iflib_rxd_pkt_get(rxq, &ri); 2592 if (avail == 0 && budget_left) 2593 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2594 2595 if (__predict_false(m == NULL)) { 2596 DBG_COUNTER_INC(rx_mbuf_null); 2597 continue; 2598 } 2599 /* imm_pkt: -- cxgb */ 2600 if (mh == NULL) 2601 mh = mt = m; 2602 else { 2603 mt->m_nextpkt = m; 2604 mt = m; 2605 } 2606 } 2607 /* make sure that we can refill faster than drain */ 2608 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2609 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2610 2611 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2612 if (lro_enabled) 2613 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2614 mt = mf = NULL; 2615 while (mh != NULL) { 2616 m = mh; 2617 mh = mh->m_nextpkt; 2618 m->m_nextpkt = NULL; 2619 #ifndef __NO_STRICT_ALIGNMENT 2620 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2621 continue; 2622 #endif 2623 rx_bytes += m->m_pkthdr.len; 2624 rx_pkts++; 2625 #if defined(INET6) || defined(INET) 2626 if (lro_enabled) { 2627 if (!lro_possible) { 2628 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2629 if (lro_possible && mf != NULL) { 2630 ifp->if_input(ifp, mf); 2631 DBG_COUNTER_INC(rx_if_input); 2632 mt = mf = NULL; 2633 } 2634 } 2635 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2636 continue; 2637 } 2638 #endif 2639 if (lro_possible) { 2640 ifp->if_input(ifp, m); 2641 DBG_COUNTER_INC(rx_if_input); 2642 continue; 2643 } 2644 2645 if (mf == NULL) 2646 mf = m; 2647 if (mt != NULL) 2648 mt->m_nextpkt = m; 2649 mt = m; 2650 } 2651 if (mf != NULL) { 2652 ifp->if_input(ifp, mf); 2653 DBG_COUNTER_INC(rx_if_input); 2654 } 2655 2656 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2657 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2658 2659 /* 2660 * Flush any outstanding LRO work 2661 */ 2662 #if defined(INET6) || defined(INET) 2663 tcp_lro_flush_all(&rxq->ifr_lc); 2664 #endif 2665 if (avail) 2666 return true; 2667 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2668 err: 2669 CTX_LOCK(ctx); 2670 ctx->ifc_flags |= IFC_DO_RESET; 2671 iflib_admin_intr_deferred(ctx); 2672 CTX_UNLOCK(ctx); 2673 return (false); 2674 } 2675 2676 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2677 static inline qidx_t 2678 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2679 { 2680 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2681 qidx_t minthresh = txq->ift_size / 8; 2682 if (in_use > 4*minthresh) 2683 return (notify_count); 2684 if (in_use > 2*minthresh) 2685 return (notify_count >> 1); 2686 if (in_use > minthresh) 2687 return (notify_count >> 3); 2688 return (0); 2689 } 2690 2691 static inline qidx_t 2692 txq_max_rs_deferred(iflib_txq_t txq) 2693 { 2694 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2695 qidx_t minthresh = txq->ift_size / 8; 2696 if (txq->ift_in_use > 4*minthresh) 2697 return (notify_count); 2698 if (txq->ift_in_use > 2*minthresh) 2699 return (notify_count >> 1); 2700 if (txq->ift_in_use > minthresh) 2701 return (notify_count >> 2); 2702 return (2); 2703 } 2704 2705 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2706 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2707 2708 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2709 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2710 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2711 2712 /* forward compatibility for cxgb */ 2713 #define FIRST_QSET(ctx) 0 2714 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2715 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2716 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2717 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2718 2719 /* XXX we should be setting this to something other than zero */ 2720 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2721 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2722 2723 static inline bool 2724 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2725 { 2726 qidx_t dbval, max; 2727 bool rang; 2728 2729 rang = false; 2730 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2731 if (ring || txq->ift_db_pending >= max) { 2732 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2733 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2734 txq->ift_db_pending = txq->ift_npending = 0; 2735 rang = true; 2736 } 2737 return (rang); 2738 } 2739 2740 #ifdef PKT_DEBUG 2741 static void 2742 print_pkt(if_pkt_info_t pi) 2743 { 2744 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2745 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2746 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2747 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2748 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2749 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2750 } 2751 #endif 2752 2753 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2754 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2755 2756 static int 2757 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2758 { 2759 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2760 struct ether_vlan_header *eh; 2761 struct mbuf *m, *n; 2762 2763 n = m = *mp; 2764 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2765 M_WRITABLE(m) == 0) { 2766 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2767 return (ENOMEM); 2768 } else { 2769 m_freem(*mp); 2770 n = *mp = m; 2771 } 2772 } 2773 2774 /* 2775 * Determine where frame payload starts. 2776 * Jump over vlan headers if already present, 2777 * helpful for QinQ too. 2778 */ 2779 if (__predict_false(m->m_len < sizeof(*eh))) { 2780 txq->ift_pullups++; 2781 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2782 return (ENOMEM); 2783 } 2784 eh = mtod(m, struct ether_vlan_header *); 2785 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2786 pi->ipi_etype = ntohs(eh->evl_proto); 2787 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2788 } else { 2789 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2790 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2791 } 2792 2793 switch (pi->ipi_etype) { 2794 #ifdef INET 2795 case ETHERTYPE_IP: 2796 { 2797 struct ip *ip = NULL; 2798 struct tcphdr *th = NULL; 2799 int minthlen; 2800 2801 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2802 if (__predict_false(m->m_len < minthlen)) { 2803 /* 2804 * if this code bloat is causing too much of a hit 2805 * move it to a separate function and mark it noinline 2806 */ 2807 if (m->m_len == pi->ipi_ehdrlen) { 2808 n = m->m_next; 2809 MPASS(n); 2810 if (n->m_len >= sizeof(*ip)) { 2811 ip = (struct ip *)n->m_data; 2812 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2813 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2814 } else { 2815 txq->ift_pullups++; 2816 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2817 return (ENOMEM); 2818 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2819 } 2820 } else { 2821 txq->ift_pullups++; 2822 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2823 return (ENOMEM); 2824 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2825 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2826 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2827 } 2828 } else { 2829 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2830 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2831 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2832 } 2833 pi->ipi_ip_hlen = ip->ip_hl << 2; 2834 pi->ipi_ipproto = ip->ip_p; 2835 pi->ipi_flags |= IPI_TX_IPV4; 2836 2837 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 2838 ip->ip_sum = 0; 2839 2840 if (IS_TSO4(pi)) { 2841 if (pi->ipi_ipproto == IPPROTO_TCP) { 2842 if (__predict_false(th == NULL)) { 2843 txq->ift_pullups++; 2844 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2845 return (ENOMEM); 2846 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2847 } 2848 pi->ipi_tcp_hflags = th->th_flags; 2849 pi->ipi_tcp_hlen = th->th_off << 2; 2850 pi->ipi_tcp_seq = th->th_seq; 2851 } 2852 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2853 return (ENXIO); 2854 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2855 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2856 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2857 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2858 ip->ip_sum = 0; 2859 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2860 } 2861 } 2862 break; 2863 } 2864 #endif 2865 #ifdef INET6 2866 case ETHERTYPE_IPV6: 2867 { 2868 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2869 struct tcphdr *th; 2870 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2871 2872 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2873 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2874 return (ENOMEM); 2875 } 2876 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2877 2878 /* XXX-BZ this will go badly in case of ext hdrs. */ 2879 pi->ipi_ipproto = ip6->ip6_nxt; 2880 pi->ipi_flags |= IPI_TX_IPV6; 2881 2882 if (IS_TSO6(pi)) { 2883 if (pi->ipi_ipproto == IPPROTO_TCP) { 2884 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2885 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2886 return (ENOMEM); 2887 } 2888 pi->ipi_tcp_hflags = th->th_flags; 2889 pi->ipi_tcp_hlen = th->th_off << 2; 2890 } 2891 2892 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2893 return (ENXIO); 2894 /* 2895 * The corresponding flag is set by the stack in the IPv4 2896 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 2897 * So, set it here because the rest of the flow requires it. 2898 */ 2899 pi->ipi_csum_flags |= CSUM_TCP_IPV6; 2900 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2901 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2902 } 2903 break; 2904 } 2905 #endif 2906 default: 2907 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2908 pi->ipi_ip_hlen = 0; 2909 break; 2910 } 2911 *mp = m; 2912 2913 return (0); 2914 } 2915 2916 static __noinline struct mbuf * 2917 collapse_pkthdr(struct mbuf *m0) 2918 { 2919 struct mbuf *m, *m_next, *tmp; 2920 2921 m = m0; 2922 m_next = m->m_next; 2923 while (m_next != NULL && m_next->m_len == 0) { 2924 m = m_next; 2925 m->m_next = NULL; 2926 m_free(m); 2927 m_next = m_next->m_next; 2928 } 2929 m = m0; 2930 m->m_next = m_next; 2931 if ((m_next->m_flags & M_EXT) == 0) { 2932 m = m_defrag(m, M_NOWAIT); 2933 } else { 2934 tmp = m_next->m_next; 2935 memcpy(m_next, m, MPKTHSIZE); 2936 m = m_next; 2937 m->m_next = tmp; 2938 } 2939 return (m); 2940 } 2941 2942 /* 2943 * If dodgy hardware rejects the scatter gather chain we've handed it 2944 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 2945 * m_defrag'd mbufs 2946 */ 2947 static __noinline struct mbuf * 2948 iflib_remove_mbuf(iflib_txq_t txq) 2949 { 2950 int ntxd, i, pidx; 2951 struct mbuf *m, *mh, **ifsd_m; 2952 2953 pidx = txq->ift_pidx; 2954 ifsd_m = txq->ift_sds.ifsd_m; 2955 ntxd = txq->ift_size; 2956 mh = m = ifsd_m[pidx]; 2957 ifsd_m[pidx] = NULL; 2958 #if MEMORY_LOGGING 2959 txq->ift_dequeued++; 2960 #endif 2961 i = 1; 2962 2963 while (m) { 2964 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 2965 #if MEMORY_LOGGING 2966 txq->ift_dequeued++; 2967 #endif 2968 m = m->m_next; 2969 i++; 2970 } 2971 return (mh); 2972 } 2973 2974 static int 2975 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 2976 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 2977 int max_segs, int flags) 2978 { 2979 if_ctx_t ctx; 2980 if_shared_ctx_t sctx; 2981 if_softc_ctx_t scctx; 2982 int i, next, pidx, err, ntxd, count; 2983 struct mbuf *m, *tmp, **ifsd_m; 2984 2985 m = *m0; 2986 2987 /* 2988 * Please don't ever do this 2989 */ 2990 if (__predict_false(m->m_len == 0)) 2991 *m0 = m = collapse_pkthdr(m); 2992 2993 ctx = txq->ift_ctx; 2994 sctx = ctx->ifc_sctx; 2995 scctx = &ctx->ifc_softc_ctx; 2996 ifsd_m = txq->ift_sds.ifsd_m; 2997 ntxd = txq->ift_size; 2998 pidx = txq->ift_pidx; 2999 if (map != NULL) { 3000 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 3001 3002 err = bus_dmamap_load_mbuf_sg(tag, map, 3003 *m0, segs, nsegs, BUS_DMA_NOWAIT); 3004 if (err) 3005 return (err); 3006 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 3007 count = 0; 3008 m = *m0; 3009 do { 3010 if (__predict_false(m->m_len <= 0)) { 3011 tmp = m; 3012 m = m->m_next; 3013 tmp->m_next = NULL; 3014 m_free(tmp); 3015 continue; 3016 } 3017 m = m->m_next; 3018 count++; 3019 } while (m != NULL); 3020 if (count > *nsegs) { 3021 ifsd_m[pidx] = *m0; 3022 ifsd_m[pidx]->m_flags |= M_TOOBIG; 3023 return (0); 3024 } 3025 m = *m0; 3026 count = 0; 3027 do { 3028 next = (pidx + count) & (ntxd-1); 3029 MPASS(ifsd_m[next] == NULL); 3030 ifsd_m[next] = m; 3031 count++; 3032 tmp = m; 3033 m = m->m_next; 3034 } while (m != NULL); 3035 } else { 3036 int buflen, sgsize, maxsegsz, max_sgsize; 3037 vm_offset_t vaddr; 3038 vm_paddr_t curaddr; 3039 3040 count = i = 0; 3041 m = *m0; 3042 if (m->m_pkthdr.csum_flags & CSUM_TSO) 3043 maxsegsz = scctx->isc_tx_tso_segsize_max; 3044 else 3045 maxsegsz = sctx->isc_tx_maxsegsize; 3046 3047 do { 3048 if (__predict_false(m->m_len <= 0)) { 3049 tmp = m; 3050 m = m->m_next; 3051 tmp->m_next = NULL; 3052 m_free(tmp); 3053 continue; 3054 } 3055 buflen = m->m_len; 3056 vaddr = (vm_offset_t)m->m_data; 3057 /* 3058 * see if we can't be smarter about physically 3059 * contiguous mappings 3060 */ 3061 next = (pidx + count) & (ntxd-1); 3062 MPASS(ifsd_m[next] == NULL); 3063 #if MEMORY_LOGGING 3064 txq->ift_enqueued++; 3065 #endif 3066 ifsd_m[next] = m; 3067 while (buflen > 0) { 3068 if (i >= max_segs) 3069 goto err; 3070 max_sgsize = MIN(buflen, maxsegsz); 3071 curaddr = pmap_kextract(vaddr); 3072 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 3073 sgsize = MIN(sgsize, max_sgsize); 3074 segs[i].ds_addr = curaddr; 3075 segs[i].ds_len = sgsize; 3076 vaddr += sgsize; 3077 buflen -= sgsize; 3078 i++; 3079 } 3080 count++; 3081 tmp = m; 3082 m = m->m_next; 3083 } while (m != NULL); 3084 *nsegs = i; 3085 } 3086 return (0); 3087 err: 3088 *m0 = iflib_remove_mbuf(txq); 3089 return (EFBIG); 3090 } 3091 3092 static inline caddr_t 3093 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3094 { 3095 qidx_t size; 3096 int ntxd; 3097 caddr_t start, end, cur, next; 3098 3099 ntxd = txq->ift_size; 3100 size = txq->ift_txd_size[qid]; 3101 start = txq->ift_ifdi[qid].idi_vaddr; 3102 3103 if (__predict_false(size == 0)) 3104 return (start); 3105 cur = start + size*cidx; 3106 end = start + size*ntxd; 3107 next = CACHE_PTR_NEXT(cur); 3108 return (next < end ? next : start); 3109 } 3110 3111 /* 3112 * Pad an mbuf to ensure a minimum ethernet frame size. 3113 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3114 */ 3115 static __noinline int 3116 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3117 { 3118 /* 3119 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3120 * and ARP message is the smallest common payload I can think of 3121 */ 3122 static char pad[18]; /* just zeros */ 3123 int n; 3124 struct mbuf *new_head; 3125 3126 if (!M_WRITABLE(*m_head)) { 3127 new_head = m_dup(*m_head, M_NOWAIT); 3128 if (new_head == NULL) { 3129 m_freem(*m_head); 3130 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3131 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3132 return ENOMEM; 3133 } 3134 m_freem(*m_head); 3135 *m_head = new_head; 3136 } 3137 3138 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3139 n > 0; n -= sizeof(pad)) 3140 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3141 break; 3142 3143 if (n > 0) { 3144 m_freem(*m_head); 3145 device_printf(dev, "cannot pad short frame\n"); 3146 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3147 return (ENOBUFS); 3148 } 3149 3150 return 0; 3151 } 3152 3153 static int 3154 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3155 { 3156 if_ctx_t ctx; 3157 if_shared_ctx_t sctx; 3158 if_softc_ctx_t scctx; 3159 bus_dma_segment_t *segs; 3160 struct mbuf *m_head; 3161 void *next_txd; 3162 bus_dmamap_t map; 3163 struct if_pkt_info pi; 3164 int remap = 0; 3165 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3166 bus_dma_tag_t desc_tag; 3167 3168 segs = txq->ift_segs; 3169 ctx = txq->ift_ctx; 3170 sctx = ctx->ifc_sctx; 3171 scctx = &ctx->ifc_softc_ctx; 3172 segs = txq->ift_segs; 3173 ntxd = txq->ift_size; 3174 m_head = *m_headp; 3175 map = NULL; 3176 3177 /* 3178 * If we're doing TSO the next descriptor to clean may be quite far ahead 3179 */ 3180 cidx = txq->ift_cidx; 3181 pidx = txq->ift_pidx; 3182 if (ctx->ifc_flags & IFC_PREFETCH) { 3183 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3184 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3185 next_txd = calc_next_txd(txq, cidx, 0); 3186 prefetch(next_txd); 3187 } 3188 3189 /* prefetch the next cache line of mbuf pointers and flags */ 3190 prefetch(&txq->ift_sds.ifsd_m[next]); 3191 if (txq->ift_sds.ifsd_map != NULL) { 3192 prefetch(&txq->ift_sds.ifsd_map[next]); 3193 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3194 prefetch(&txq->ift_sds.ifsd_flags[next]); 3195 } 3196 } else if (txq->ift_sds.ifsd_map != NULL) 3197 map = txq->ift_sds.ifsd_map[pidx]; 3198 3199 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3200 desc_tag = txq->ift_tso_desc_tag; 3201 max_segs = scctx->isc_tx_tso_segments_max; 3202 } else { 3203 desc_tag = txq->ift_desc_tag; 3204 max_segs = scctx->isc_tx_nsegments; 3205 } 3206 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3207 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3208 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3209 if (err) 3210 return err; 3211 } 3212 m_head = *m_headp; 3213 3214 pkt_info_zero(&pi); 3215 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3216 pi.ipi_pidx = pidx; 3217 pi.ipi_qsidx = txq->ift_id; 3218 pi.ipi_len = m_head->m_pkthdr.len; 3219 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3220 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3221 3222 /* deliberate bitwise OR to make one condition */ 3223 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3224 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3225 return (err); 3226 m_head = *m_headp; 3227 } 3228 3229 retry: 3230 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3231 defrag: 3232 if (__predict_false(err)) { 3233 switch (err) { 3234 case EFBIG: 3235 /* try collapse once and defrag once */ 3236 if (remap == 0) 3237 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3238 if (remap == 1) 3239 m_head = m_defrag(*m_headp, M_NOWAIT); 3240 remap++; 3241 if (__predict_false(m_head == NULL)) 3242 goto defrag_failed; 3243 txq->ift_mbuf_defrag++; 3244 *m_headp = m_head; 3245 goto retry; 3246 break; 3247 case ENOMEM: 3248 txq->ift_no_tx_dma_setup++; 3249 break; 3250 default: 3251 txq->ift_no_tx_dma_setup++; 3252 m_freem(*m_headp); 3253 DBG_COUNTER_INC(tx_frees); 3254 *m_headp = NULL; 3255 break; 3256 } 3257 txq->ift_map_failed++; 3258 DBG_COUNTER_INC(encap_load_mbuf_fail); 3259 return (err); 3260 } 3261 3262 /* 3263 * XXX assumes a 1 to 1 relationship between segments and 3264 * descriptors - this does not hold true on all drivers, e.g. 3265 * cxgb 3266 */ 3267 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3268 txq->ift_no_desc_avail++; 3269 if (map != NULL) 3270 bus_dmamap_unload(desc_tag, map); 3271 DBG_COUNTER_INC(encap_txq_avail_fail); 3272 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3273 GROUPTASK_ENQUEUE(&txq->ift_task); 3274 return (ENOBUFS); 3275 } 3276 /* 3277 * On Intel cards we can greatly reduce the number of TX interrupts 3278 * we see by only setting report status on every Nth descriptor. 3279 * However, this also means that the driver will need to keep track 3280 * of the descriptors that RS was set on to check them for the DD bit. 3281 */ 3282 txq->ift_rs_pending += nsegs + 1; 3283 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3284 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) { 3285 pi.ipi_flags |= IPI_TX_INTR; 3286 txq->ift_rs_pending = 0; 3287 } 3288 3289 pi.ipi_segs = segs; 3290 pi.ipi_nsegs = nsegs; 3291 3292 MPASS(pidx >= 0 && pidx < txq->ift_size); 3293 #ifdef PKT_DEBUG 3294 print_pkt(&pi); 3295 #endif 3296 if (map != NULL) 3297 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3298 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3299 if (map != NULL) 3300 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3301 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3302 DBG_COUNTER_INC(tx_encap); 3303 MPASS(pi.ipi_new_pidx < txq->ift_size); 3304 3305 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3306 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3307 ndesc += txq->ift_size; 3308 txq->ift_gen = 1; 3309 } 3310 /* 3311 * drivers can need as many as 3312 * two sentinels 3313 */ 3314 MPASS(ndesc <= pi.ipi_nsegs + 2); 3315 MPASS(pi.ipi_new_pidx != pidx); 3316 MPASS(ndesc > 0); 3317 txq->ift_in_use += ndesc; 3318 3319 /* 3320 * We update the last software descriptor again here because there may 3321 * be a sentinel and/or there may be more mbufs than segments 3322 */ 3323 txq->ift_pidx = pi.ipi_new_pidx; 3324 txq->ift_npending += pi.ipi_ndescs; 3325 } else if (__predict_false(err == EFBIG && remap < 2)) { 3326 *m_headp = m_head = iflib_remove_mbuf(txq); 3327 remap = 1; 3328 txq->ift_txd_encap_efbig++; 3329 goto defrag; 3330 } else 3331 DBG_COUNTER_INC(encap_txd_encap_fail); 3332 return (err); 3333 3334 defrag_failed: 3335 txq->ift_mbuf_defrag_failed++; 3336 txq->ift_map_failed++; 3337 m_freem(*m_headp); 3338 DBG_COUNTER_INC(tx_frees); 3339 *m_headp = NULL; 3340 return (ENOMEM); 3341 } 3342 3343 static void 3344 iflib_tx_desc_free(iflib_txq_t txq, int n) 3345 { 3346 int hasmap; 3347 uint32_t qsize, cidx, mask, gen; 3348 struct mbuf *m, **ifsd_m; 3349 uint8_t *ifsd_flags; 3350 bus_dmamap_t *ifsd_map; 3351 bool do_prefetch; 3352 3353 cidx = txq->ift_cidx; 3354 gen = txq->ift_gen; 3355 qsize = txq->ift_size; 3356 mask = qsize-1; 3357 hasmap = txq->ift_sds.ifsd_map != NULL; 3358 ifsd_flags = txq->ift_sds.ifsd_flags; 3359 ifsd_m = txq->ift_sds.ifsd_m; 3360 ifsd_map = txq->ift_sds.ifsd_map; 3361 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3362 3363 while (n--) { 3364 if (do_prefetch) { 3365 prefetch(ifsd_m[(cidx + 3) & mask]); 3366 prefetch(ifsd_m[(cidx + 4) & mask]); 3367 } 3368 if (ifsd_m[cidx] != NULL) { 3369 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3370 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3371 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3372 /* 3373 * does it matter if it's not the TSO tag? If so we'll 3374 * have to add the type to flags 3375 */ 3376 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3377 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3378 } 3379 if ((m = ifsd_m[cidx]) != NULL) { 3380 /* XXX we don't support any drivers that batch packets yet */ 3381 MPASS(m->m_nextpkt == NULL); 3382 /* if the number of clusters exceeds the number of segments 3383 * there won't be space on the ring to save a pointer to each 3384 * cluster so we simply free the list here 3385 */ 3386 if (m->m_flags & M_TOOBIG) { 3387 m_freem(m); 3388 } else { 3389 m_free(m); 3390 } 3391 ifsd_m[cidx] = NULL; 3392 #if MEMORY_LOGGING 3393 txq->ift_dequeued++; 3394 #endif 3395 DBG_COUNTER_INC(tx_frees); 3396 } 3397 } 3398 if (__predict_false(++cidx == qsize)) { 3399 cidx = 0; 3400 gen = 0; 3401 } 3402 } 3403 txq->ift_cidx = cidx; 3404 txq->ift_gen = gen; 3405 } 3406 3407 static __inline int 3408 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3409 { 3410 int reclaim; 3411 if_ctx_t ctx = txq->ift_ctx; 3412 3413 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3414 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3415 3416 /* 3417 * Need a rate-limiting check so that this isn't called every time 3418 */ 3419 iflib_tx_credits_update(ctx, txq); 3420 reclaim = DESC_RECLAIMABLE(txq); 3421 3422 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3423 #ifdef INVARIANTS 3424 if (iflib_verbose_debug) { 3425 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3426 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3427 reclaim, thresh); 3428 3429 } 3430 #endif 3431 return (0); 3432 } 3433 iflib_tx_desc_free(txq, reclaim); 3434 txq->ift_cleaned += reclaim; 3435 txq->ift_in_use -= reclaim; 3436 3437 return (reclaim); 3438 } 3439 3440 static struct mbuf ** 3441 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3442 { 3443 int next, size; 3444 struct mbuf **items; 3445 3446 size = r->size; 3447 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3448 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3449 3450 prefetch(items[(cidx + offset) & (size-1)]); 3451 if (remaining > 1) { 3452 prefetch2cachelines(&items[next]); 3453 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3454 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3455 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3456 } 3457 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3458 } 3459 3460 static void 3461 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3462 { 3463 3464 ifmp_ring_check_drainage(txq->ift_br, budget); 3465 } 3466 3467 static uint32_t 3468 iflib_txq_can_drain(struct ifmp_ring *r) 3469 { 3470 iflib_txq_t txq = r->cookie; 3471 if_ctx_t ctx = txq->ift_ctx; 3472 3473 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3474 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3475 } 3476 3477 static uint32_t 3478 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3479 { 3480 iflib_txq_t txq = r->cookie; 3481 if_ctx_t ctx = txq->ift_ctx; 3482 struct ifnet *ifp = ctx->ifc_ifp; 3483 struct mbuf **mp, *m; 3484 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3485 int reclaimed, err, in_use_prev, desc_used; 3486 bool do_prefetch, ring, rang; 3487 3488 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3489 !LINK_ACTIVE(ctx))) { 3490 DBG_COUNTER_INC(txq_drain_notready); 3491 return (0); 3492 } 3493 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3494 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3495 avail = IDXDIFF(pidx, cidx, r->size); 3496 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3497 DBG_COUNTER_INC(txq_drain_flushing); 3498 for (i = 0; i < avail; i++) { 3499 m_free(r->items[(cidx + i) & (r->size-1)]); 3500 r->items[(cidx + i) & (r->size-1)] = NULL; 3501 } 3502 return (avail); 3503 } 3504 3505 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3506 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3507 CALLOUT_LOCK(txq); 3508 callout_stop(&txq->ift_timer); 3509 CALLOUT_UNLOCK(txq); 3510 DBG_COUNTER_INC(txq_drain_oactive); 3511 return (0); 3512 } 3513 if (reclaimed) 3514 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3515 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3516 count = MIN(avail, TX_BATCH_SIZE); 3517 #ifdef INVARIANTS 3518 if (iflib_verbose_debug) 3519 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3520 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3521 #endif 3522 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3523 avail = TXQ_AVAIL(txq); 3524 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3525 int pidx_prev, rem = do_prefetch ? count - i : 0; 3526 3527 mp = _ring_peek_one(r, cidx, i, rem); 3528 MPASS(mp != NULL && *mp != NULL); 3529 if (__predict_false(*mp == (struct mbuf *)txq)) { 3530 consumed++; 3531 reclaimed++; 3532 continue; 3533 } 3534 in_use_prev = txq->ift_in_use; 3535 pidx_prev = txq->ift_pidx; 3536 err = iflib_encap(txq, mp); 3537 if (__predict_false(err)) { 3538 DBG_COUNTER_INC(txq_drain_encapfail); 3539 /* no room - bail out */ 3540 if (err == ENOBUFS) 3541 break; 3542 consumed++; 3543 DBG_COUNTER_INC(txq_drain_encapfail); 3544 /* we can't send this packet - skip it */ 3545 continue; 3546 } 3547 consumed++; 3548 pkt_sent++; 3549 m = *mp; 3550 DBG_COUNTER_INC(tx_sent); 3551 bytes_sent += m->m_pkthdr.len; 3552 mcast_sent += !!(m->m_flags & M_MCAST); 3553 avail = TXQ_AVAIL(txq); 3554 3555 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3556 desc_used += (txq->ift_in_use - in_use_prev); 3557 ETHER_BPF_MTAP(ifp, m); 3558 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3559 break; 3560 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3561 } 3562 3563 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3564 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3565 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3566 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3567 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3568 if (mcast_sent) 3569 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3570 #ifdef INVARIANTS 3571 if (iflib_verbose_debug) 3572 printf("consumed=%d\n", consumed); 3573 #endif 3574 return (consumed); 3575 } 3576 3577 static uint32_t 3578 iflib_txq_drain_always(struct ifmp_ring *r) 3579 { 3580 return (1); 3581 } 3582 3583 static uint32_t 3584 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3585 { 3586 int i, avail; 3587 struct mbuf **mp; 3588 iflib_txq_t txq; 3589 3590 txq = r->cookie; 3591 3592 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3593 CALLOUT_LOCK(txq); 3594 callout_stop(&txq->ift_timer); 3595 CALLOUT_UNLOCK(txq); 3596 3597 avail = IDXDIFF(pidx, cidx, r->size); 3598 for (i = 0; i < avail; i++) { 3599 mp = _ring_peek_one(r, cidx, i, avail - i); 3600 if (__predict_false(*mp == (struct mbuf *)txq)) 3601 continue; 3602 m_freem(*mp); 3603 } 3604 MPASS(ifmp_ring_is_stalled(r) == 0); 3605 return (avail); 3606 } 3607 3608 static void 3609 iflib_ifmp_purge(iflib_txq_t txq) 3610 { 3611 struct ifmp_ring *r; 3612 3613 r = txq->ift_br; 3614 r->drain = iflib_txq_drain_free; 3615 r->can_drain = iflib_txq_drain_always; 3616 3617 ifmp_ring_check_drainage(r, r->size); 3618 3619 r->drain = iflib_txq_drain; 3620 r->can_drain = iflib_txq_can_drain; 3621 } 3622 3623 static void 3624 _task_fn_tx(void *context) 3625 { 3626 iflib_txq_t txq = context; 3627 if_ctx_t ctx = txq->ift_ctx; 3628 struct ifnet *ifp = ctx->ifc_ifp; 3629 int rc; 3630 3631 #ifdef IFLIB_DIAGNOSTICS 3632 txq->ift_cpu_exec_count[curcpu]++; 3633 #endif 3634 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3635 return; 3636 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3637 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3638 netmap_tx_irq(ifp, txq->ift_id); 3639 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3640 return; 3641 } 3642 if (txq->ift_db_pending) 3643 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); 3644 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3645 if (ctx->ifc_flags & IFC_LEGACY) 3646 IFDI_INTR_ENABLE(ctx); 3647 else { 3648 rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3649 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3650 } 3651 } 3652 3653 static void 3654 _task_fn_rx(void *context) 3655 { 3656 iflib_rxq_t rxq = context; 3657 if_ctx_t ctx = rxq->ifr_ctx; 3658 bool more; 3659 int rc; 3660 uint16_t budget; 3661 3662 #ifdef IFLIB_DIAGNOSTICS 3663 rxq->ifr_cpu_exec_count[curcpu]++; 3664 #endif 3665 DBG_COUNTER_INC(task_fn_rxs); 3666 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3667 return; 3668 more = true; 3669 #ifdef DEV_NETMAP 3670 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3671 u_int work = 0; 3672 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3673 more = false; 3674 } 3675 } 3676 #endif 3677 budget = ctx->ifc_sysctl_rx_budget; 3678 if (budget == 0) 3679 budget = 16; /* XXX */ 3680 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3681 if (ctx->ifc_flags & IFC_LEGACY) 3682 IFDI_INTR_ENABLE(ctx); 3683 else { 3684 DBG_COUNTER_INC(rx_intr_enables); 3685 rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3686 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3687 } 3688 } 3689 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3690 return; 3691 if (more) 3692 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3693 } 3694 3695 static void 3696 _task_fn_admin(void *context) 3697 { 3698 if_ctx_t ctx = context; 3699 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3700 iflib_txq_t txq; 3701 int i; 3702 3703 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) { 3704 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3705 return; 3706 } 3707 } 3708 3709 CTX_LOCK(ctx); 3710 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3711 CALLOUT_LOCK(txq); 3712 callout_stop(&txq->ift_timer); 3713 CALLOUT_UNLOCK(txq); 3714 } 3715 IFDI_UPDATE_ADMIN_STATUS(ctx); 3716 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3717 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 3718 IFDI_LINK_INTR_ENABLE(ctx); 3719 if (ctx->ifc_flags & IFC_DO_RESET) { 3720 ctx->ifc_flags &= ~IFC_DO_RESET; 3721 iflib_if_init_locked(ctx); 3722 } 3723 CTX_UNLOCK(ctx); 3724 3725 if (LINK_ACTIVE(ctx) == 0) 3726 return; 3727 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3728 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3729 } 3730 3731 3732 static void 3733 _task_fn_iov(void *context) 3734 { 3735 if_ctx_t ctx = context; 3736 3737 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3738 return; 3739 3740 CTX_LOCK(ctx); 3741 IFDI_VFLR_HANDLE(ctx); 3742 CTX_UNLOCK(ctx); 3743 } 3744 3745 static int 3746 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3747 { 3748 int err; 3749 if_int_delay_info_t info; 3750 if_ctx_t ctx; 3751 3752 info = (if_int_delay_info_t)arg1; 3753 ctx = info->iidi_ctx; 3754 info->iidi_req = req; 3755 info->iidi_oidp = oidp; 3756 CTX_LOCK(ctx); 3757 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3758 CTX_UNLOCK(ctx); 3759 return (err); 3760 } 3761 3762 /********************************************************************* 3763 * 3764 * IFNET FUNCTIONS 3765 * 3766 **********************************************************************/ 3767 3768 static void 3769 iflib_if_init_locked(if_ctx_t ctx) 3770 { 3771 iflib_stop(ctx); 3772 iflib_init_locked(ctx); 3773 } 3774 3775 3776 static void 3777 iflib_if_init(void *arg) 3778 { 3779 if_ctx_t ctx = arg; 3780 3781 CTX_LOCK(ctx); 3782 iflib_if_init_locked(ctx); 3783 CTX_UNLOCK(ctx); 3784 } 3785 3786 static int 3787 iflib_if_transmit(if_t ifp, struct mbuf *m) 3788 { 3789 if_ctx_t ctx = if_getsoftc(ifp); 3790 3791 iflib_txq_t txq; 3792 int err, qidx; 3793 3794 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3795 DBG_COUNTER_INC(tx_frees); 3796 m_freem(m); 3797 return (ENOBUFS); 3798 } 3799 3800 MPASS(m->m_nextpkt == NULL); 3801 qidx = 0; 3802 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3803 qidx = QIDX(ctx, m); 3804 /* 3805 * XXX calculate buf_ring based on flowid (divvy up bits?) 3806 */ 3807 txq = &ctx->ifc_txqs[qidx]; 3808 3809 #ifdef DRIVER_BACKPRESSURE 3810 if (txq->ift_closed) { 3811 while (m != NULL) { 3812 next = m->m_nextpkt; 3813 m->m_nextpkt = NULL; 3814 m_freem(m); 3815 m = next; 3816 } 3817 return (ENOBUFS); 3818 } 3819 #endif 3820 #ifdef notyet 3821 qidx = count = 0; 3822 mp = marr; 3823 next = m; 3824 do { 3825 count++; 3826 next = next->m_nextpkt; 3827 } while (next != NULL); 3828 3829 if (count > nitems(marr)) 3830 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3831 /* XXX check nextpkt */ 3832 m_freem(m); 3833 /* XXX simplify for now */ 3834 DBG_COUNTER_INC(tx_frees); 3835 return (ENOBUFS); 3836 } 3837 for (next = m, i = 0; next != NULL; i++) { 3838 mp[i] = next; 3839 next = next->m_nextpkt; 3840 mp[i]->m_nextpkt = NULL; 3841 } 3842 #endif 3843 DBG_COUNTER_INC(tx_seen); 3844 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); 3845 3846 GROUPTASK_ENQUEUE(&txq->ift_task); 3847 if (err) { 3848 /* support forthcoming later */ 3849 #ifdef DRIVER_BACKPRESSURE 3850 txq->ift_closed = TRUE; 3851 #endif 3852 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3853 m_freem(m); 3854 } 3855 3856 return (err); 3857 } 3858 3859 static void 3860 iflib_if_qflush(if_t ifp) 3861 { 3862 if_ctx_t ctx = if_getsoftc(ifp); 3863 iflib_txq_t txq = ctx->ifc_txqs; 3864 int i; 3865 3866 CTX_LOCK(ctx); 3867 ctx->ifc_flags |= IFC_QFLUSH; 3868 CTX_UNLOCK(ctx); 3869 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3870 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3871 iflib_txq_check_drain(txq, 0); 3872 CTX_LOCK(ctx); 3873 ctx->ifc_flags &= ~IFC_QFLUSH; 3874 CTX_UNLOCK(ctx); 3875 3876 if_qflush(ifp); 3877 } 3878 3879 3880 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3881 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 3882 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 3883 3884 static int 3885 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 3886 { 3887 if_ctx_t ctx = if_getsoftc(ifp); 3888 struct ifreq *ifr = (struct ifreq *)data; 3889 #if defined(INET) || defined(INET6) 3890 struct ifaddr *ifa = (struct ifaddr *)data; 3891 #endif 3892 bool avoid_reset = FALSE; 3893 int err = 0, reinit = 0, bits; 3894 3895 switch (command) { 3896 case SIOCSIFADDR: 3897 #ifdef INET 3898 if (ifa->ifa_addr->sa_family == AF_INET) 3899 avoid_reset = TRUE; 3900 #endif 3901 #ifdef INET6 3902 if (ifa->ifa_addr->sa_family == AF_INET6) 3903 avoid_reset = TRUE; 3904 #endif 3905 /* 3906 ** Calling init results in link renegotiation, 3907 ** so we avoid doing it when possible. 3908 */ 3909 if (avoid_reset) { 3910 if_setflagbits(ifp, IFF_UP,0); 3911 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING)) 3912 reinit = 1; 3913 #ifdef INET 3914 if (!(if_getflags(ifp) & IFF_NOARP)) 3915 arp_ifinit(ifp, ifa); 3916 #endif 3917 } else 3918 err = ether_ioctl(ifp, command, data); 3919 break; 3920 case SIOCSIFMTU: 3921 CTX_LOCK(ctx); 3922 if (ifr->ifr_mtu == if_getmtu(ifp)) { 3923 CTX_UNLOCK(ctx); 3924 break; 3925 } 3926 bits = if_getdrvflags(ifp); 3927 /* stop the driver and free any clusters before proceeding */ 3928 iflib_stop(ctx); 3929 3930 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 3931 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 3932 ctx->ifc_flags |= IFC_MULTISEG; 3933 else 3934 ctx->ifc_flags &= ~IFC_MULTISEG; 3935 err = if_setmtu(ifp, ifr->ifr_mtu); 3936 } 3937 iflib_init_locked(ctx); 3938 if_setdrvflags(ifp, bits); 3939 CTX_UNLOCK(ctx); 3940 break; 3941 case SIOCSIFFLAGS: 3942 CTX_LOCK(ctx); 3943 if (if_getflags(ifp) & IFF_UP) { 3944 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3945 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 3946 (IFF_PROMISC | IFF_ALLMULTI)) { 3947 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 3948 } 3949 } else 3950 reinit = 1; 3951 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3952 iflib_stop(ctx); 3953 } 3954 ctx->ifc_if_flags = if_getflags(ifp); 3955 CTX_UNLOCK(ctx); 3956 break; 3957 case SIOCADDMULTI: 3958 case SIOCDELMULTI: 3959 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3960 CTX_LOCK(ctx); 3961 IFDI_INTR_DISABLE(ctx); 3962 IFDI_MULTI_SET(ctx); 3963 IFDI_INTR_ENABLE(ctx); 3964 CTX_UNLOCK(ctx); 3965 } 3966 break; 3967 case SIOCSIFMEDIA: 3968 CTX_LOCK(ctx); 3969 IFDI_MEDIA_SET(ctx); 3970 CTX_UNLOCK(ctx); 3971 /* falls thru */ 3972 case SIOCGIFMEDIA: 3973 case SIOCGIFXMEDIA: 3974 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 3975 break; 3976 case SIOCGI2C: 3977 { 3978 struct ifi2creq i2c; 3979 3980 err = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); 3981 if (err != 0) 3982 break; 3983 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 3984 err = EINVAL; 3985 break; 3986 } 3987 if (i2c.len > sizeof(i2c.data)) { 3988 err = EINVAL; 3989 break; 3990 } 3991 3992 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 3993 err = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); 3994 break; 3995 } 3996 case SIOCSIFCAP: 3997 { 3998 int mask, setmask; 3999 4000 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 4001 setmask = 0; 4002 #ifdef TCP_OFFLOAD 4003 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4004 #endif 4005 setmask |= (mask & IFCAP_FLAGS); 4006 4007 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 4008 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4009 if ((mask & IFCAP_WOL) && 4010 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 4011 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 4012 if_vlancap(ifp); 4013 /* 4014 * want to ensure that traffic has stopped before we change any of the flags 4015 */ 4016 if (setmask) { 4017 CTX_LOCK(ctx); 4018 bits = if_getdrvflags(ifp); 4019 if (bits & IFF_DRV_RUNNING) 4020 iflib_stop(ctx); 4021 if_togglecapenable(ifp, setmask); 4022 if (bits & IFF_DRV_RUNNING) 4023 iflib_init_locked(ctx); 4024 if_setdrvflags(ifp, bits); 4025 CTX_UNLOCK(ctx); 4026 } 4027 break; 4028 } 4029 case SIOCGPRIVATE_0: 4030 case SIOCSDRVSPEC: 4031 case SIOCGDRVSPEC: 4032 CTX_LOCK(ctx); 4033 err = IFDI_PRIV_IOCTL(ctx, command, data); 4034 CTX_UNLOCK(ctx); 4035 break; 4036 default: 4037 err = ether_ioctl(ifp, command, data); 4038 break; 4039 } 4040 if (reinit) 4041 iflib_if_init(ctx); 4042 return (err); 4043 } 4044 4045 static uint64_t 4046 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4047 { 4048 if_ctx_t ctx = if_getsoftc(ifp); 4049 4050 return (IFDI_GET_COUNTER(ctx, cnt)); 4051 } 4052 4053 /********************************************************************* 4054 * 4055 * OTHER FUNCTIONS EXPORTED TO THE STACK 4056 * 4057 **********************************************************************/ 4058 4059 static void 4060 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4061 { 4062 if_ctx_t ctx = if_getsoftc(ifp); 4063 4064 if ((void *)ctx != arg) 4065 return; 4066 4067 if ((vtag == 0) || (vtag > 4095)) 4068 return; 4069 4070 CTX_LOCK(ctx); 4071 IFDI_VLAN_REGISTER(ctx, vtag); 4072 /* Re-init to load the changes */ 4073 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4074 iflib_if_init_locked(ctx); 4075 CTX_UNLOCK(ctx); 4076 } 4077 4078 static void 4079 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4080 { 4081 if_ctx_t ctx = if_getsoftc(ifp); 4082 4083 if ((void *)ctx != arg) 4084 return; 4085 4086 if ((vtag == 0) || (vtag > 4095)) 4087 return; 4088 4089 CTX_LOCK(ctx); 4090 IFDI_VLAN_UNREGISTER(ctx, vtag); 4091 /* Re-init to load the changes */ 4092 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4093 iflib_if_init_locked(ctx); 4094 CTX_UNLOCK(ctx); 4095 } 4096 4097 static void 4098 iflib_led_func(void *arg, int onoff) 4099 { 4100 if_ctx_t ctx = arg; 4101 4102 CTX_LOCK(ctx); 4103 IFDI_LED_FUNC(ctx, onoff); 4104 CTX_UNLOCK(ctx); 4105 } 4106 4107 /********************************************************************* 4108 * 4109 * BUS FUNCTION DEFINITIONS 4110 * 4111 **********************************************************************/ 4112 4113 int 4114 iflib_device_probe(device_t dev) 4115 { 4116 pci_vendor_info_t *ent; 4117 4118 uint16_t pci_vendor_id, pci_device_id; 4119 uint16_t pci_subvendor_id, pci_subdevice_id; 4120 uint16_t pci_rev_id; 4121 if_shared_ctx_t sctx; 4122 4123 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4124 return (ENOTSUP); 4125 4126 pci_vendor_id = pci_get_vendor(dev); 4127 pci_device_id = pci_get_device(dev); 4128 pci_subvendor_id = pci_get_subvendor(dev); 4129 pci_subdevice_id = pci_get_subdevice(dev); 4130 pci_rev_id = pci_get_revid(dev); 4131 if (sctx->isc_parse_devinfo != NULL) 4132 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4133 4134 ent = sctx->isc_vendor_info; 4135 while (ent->pvi_vendor_id != 0) { 4136 if (pci_vendor_id != ent->pvi_vendor_id) { 4137 ent++; 4138 continue; 4139 } 4140 if ((pci_device_id == ent->pvi_device_id) && 4141 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4142 (ent->pvi_subvendor_id == 0)) && 4143 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4144 (ent->pvi_subdevice_id == 0)) && 4145 ((pci_rev_id == ent->pvi_rev_id) || 4146 (ent->pvi_rev_id == 0))) { 4147 4148 device_set_desc_copy(dev, ent->pvi_name); 4149 /* this needs to be changed to zero if the bus probing code 4150 * ever stops re-probing on best match because the sctx 4151 * may have its values over written by register calls 4152 * in subsequent probes 4153 */ 4154 return (BUS_PROBE_DEFAULT); 4155 } 4156 ent++; 4157 } 4158 return (ENXIO); 4159 } 4160 4161 int 4162 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4163 { 4164 int err, rid, msix, msix_bar; 4165 if_ctx_t ctx; 4166 if_t ifp; 4167 if_softc_ctx_t scctx; 4168 int i; 4169 uint16_t main_txq; 4170 uint16_t main_rxq; 4171 4172 4173 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4174 4175 if (sc == NULL) { 4176 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4177 device_set_softc(dev, ctx); 4178 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4179 } 4180 4181 ctx->ifc_sctx = sctx; 4182 ctx->ifc_dev = dev; 4183 ctx->ifc_softc = sc; 4184 4185 if ((err = iflib_register(ctx)) != 0) { 4186 device_printf(dev, "iflib_register failed %d\n", err); 4187 return (err); 4188 } 4189 iflib_add_device_sysctl_pre(ctx); 4190 4191 scctx = &ctx->ifc_softc_ctx; 4192 ifp = ctx->ifc_ifp; 4193 4194 /* 4195 * XXX sanity check that ntxd & nrxd are a power of 2 4196 */ 4197 if (ctx->ifc_sysctl_ntxqs != 0) 4198 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4199 if (ctx->ifc_sysctl_nrxqs != 0) 4200 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4201 4202 for (i = 0; i < sctx->isc_ntxqs; i++) { 4203 if (ctx->ifc_sysctl_ntxds[i] != 0) 4204 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4205 else 4206 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4207 } 4208 4209 for (i = 0; i < sctx->isc_nrxqs; i++) { 4210 if (ctx->ifc_sysctl_nrxds[i] != 0) 4211 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4212 else 4213 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4214 } 4215 4216 for (i = 0; i < sctx->isc_nrxqs; i++) { 4217 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4218 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4219 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4220 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4221 } 4222 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4223 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4224 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4225 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4226 } 4227 } 4228 4229 for (i = 0; i < sctx->isc_ntxqs; i++) { 4230 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4231 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4232 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4233 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4234 } 4235 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4236 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4237 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4238 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4239 } 4240 } 4241 4242 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4243 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4244 return (err); 4245 } 4246 _iflib_pre_assert(scctx); 4247 ctx->ifc_txrx = *scctx->isc_txrx; 4248 4249 #ifdef INVARIANTS 4250 MPASS(scctx->isc_capenable); 4251 if (scctx->isc_capenable & IFCAP_TXCSUM) 4252 MPASS(scctx->isc_tx_csum_flags); 4253 #endif 4254 4255 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4256 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4257 4258 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4259 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4260 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4261 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4262 4263 #ifdef ACPI_DMAR 4264 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4265 ctx->ifc_flags |= IFC_DMAR; 4266 #elif !(defined(__i386__) || defined(__amd64__)) 4267 /* set unconditionally for !x86 */ 4268 ctx->ifc_flags |= IFC_DMAR; 4269 #endif 4270 4271 msix_bar = scctx->isc_msix_bar; 4272 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4273 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4274 4275 /* XXX change for per-queue sizes */ 4276 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4277 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4278 for (i = 0; i < sctx->isc_nrxqs; i++) { 4279 if (!powerof2(scctx->isc_nrxd[i])) { 4280 /* round down instead? */ 4281 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4282 err = EINVAL; 4283 goto fail; 4284 } 4285 } 4286 for (i = 0; i < sctx->isc_ntxqs; i++) { 4287 if (!powerof2(scctx->isc_ntxd[i])) { 4288 device_printf(dev, 4289 "# tx descriptors must be a power of 2"); 4290 err = EINVAL; 4291 goto fail; 4292 } 4293 } 4294 4295 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4296 MAX_SINGLE_PACKET_FRACTION) 4297 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4298 MAX_SINGLE_PACKET_FRACTION); 4299 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4300 MAX_SINGLE_PACKET_FRACTION) 4301 scctx->isc_tx_tso_segments_max = max(1, 4302 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4303 4304 /* 4305 * Protect the stack against modern hardware 4306 */ 4307 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4308 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4309 4310 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4311 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4312 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4313 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4314 if (scctx->isc_rss_table_size == 0) 4315 scctx->isc_rss_table_size = 64; 4316 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4317 4318 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4319 /* XXX format name */ 4320 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4321 4322 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4323 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4324 device_printf(dev, "Unable to fetch CPU list\n"); 4325 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4326 } 4327 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4328 4329 /* 4330 ** Now setup MSI or MSI/X, should 4331 ** return us the number of supported 4332 ** vectors. (Will be 1 for MSI) 4333 */ 4334 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4335 msix = scctx->isc_vectors; 4336 } else if (scctx->isc_msix_bar != 0) 4337 /* 4338 * The simple fact that isc_msix_bar is not 0 does not mean we 4339 * we have a good value there that is known to work. 4340 */ 4341 msix = iflib_msix_init(ctx); 4342 else { 4343 scctx->isc_vectors = 1; 4344 scctx->isc_ntxqsets = 1; 4345 scctx->isc_nrxqsets = 1; 4346 scctx->isc_intr = IFLIB_INTR_LEGACY; 4347 msix = 0; 4348 } 4349 /* Get memory for the station queues */ 4350 if ((err = iflib_queues_alloc(ctx))) { 4351 device_printf(dev, "Unable to allocate queue memory\n"); 4352 goto fail; 4353 } 4354 4355 if ((err = iflib_qset_structures_setup(ctx))) { 4356 device_printf(dev, "qset structure setup failed %d\n", err); 4357 goto fail_queues; 4358 } 4359 4360 /* 4361 * Group taskqueues aren't properly set up until SMP is started, 4362 * so we disable interrupts until we can handle them post 4363 * SI_SUB_SMP. 4364 * 4365 * XXX: disabling interrupts doesn't actually work, at least for 4366 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4367 * we do null handling and depend on this not causing too large an 4368 * interrupt storm. 4369 */ 4370 IFDI_INTR_DISABLE(ctx); 4371 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4372 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4373 goto fail_intr_free; 4374 } 4375 if (msix <= 1) { 4376 rid = 0; 4377 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4378 MPASS(msix == 1); 4379 rid = 1; 4380 } 4381 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4382 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4383 goto fail_intr_free; 4384 } 4385 } 4386 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4387 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4388 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4389 goto fail_detach; 4390 } 4391 if ((err = iflib_netmap_attach(ctx))) { 4392 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4393 goto fail_detach; 4394 } 4395 *ctxp = ctx; 4396 4397 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4398 iflib_add_device_sysctl_post(ctx); 4399 ctx->ifc_flags |= IFC_INIT_DONE; 4400 return (0); 4401 fail_detach: 4402 ether_ifdetach(ctx->ifc_ifp); 4403 fail_intr_free: 4404 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4405 pci_release_msi(ctx->ifc_dev); 4406 fail_queues: 4407 /* XXX free queues */ 4408 fail: 4409 IFDI_DETACH(ctx); 4410 return (err); 4411 } 4412 4413 int 4414 iflib_device_attach(device_t dev) 4415 { 4416 if_ctx_t ctx; 4417 if_shared_ctx_t sctx; 4418 4419 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4420 return (ENOTSUP); 4421 4422 pci_enable_busmaster(dev); 4423 4424 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4425 } 4426 4427 int 4428 iflib_device_deregister(if_ctx_t ctx) 4429 { 4430 if_t ifp = ctx->ifc_ifp; 4431 iflib_txq_t txq; 4432 iflib_rxq_t rxq; 4433 device_t dev = ctx->ifc_dev; 4434 int i, j; 4435 struct taskqgroup *tqg; 4436 iflib_fl_t fl; 4437 4438 /* Make sure VLANS are not using driver */ 4439 if (if_vlantrunkinuse(ifp)) { 4440 device_printf(dev,"Vlan in use, detach first\n"); 4441 return (EBUSY); 4442 } 4443 4444 CTX_LOCK(ctx); 4445 ctx->ifc_in_detach = 1; 4446 iflib_stop(ctx); 4447 CTX_UNLOCK(ctx); 4448 4449 /* Unregister VLAN events */ 4450 if (ctx->ifc_vlan_attach_event != NULL) 4451 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4452 if (ctx->ifc_vlan_detach_event != NULL) 4453 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4454 4455 iflib_netmap_detach(ifp); 4456 ether_ifdetach(ifp); 4457 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4458 CTX_LOCK_DESTROY(ctx); 4459 if (ctx->ifc_led_dev != NULL) 4460 led_destroy(ctx->ifc_led_dev); 4461 /* XXX drain any dependent tasks */ 4462 tqg = qgroup_if_io_tqg; 4463 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4464 callout_drain(&txq->ift_timer); 4465 if (txq->ift_task.gt_uniq != NULL) 4466 taskqgroup_detach(tqg, &txq->ift_task); 4467 } 4468 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4469 if (rxq->ifr_task.gt_uniq != NULL) 4470 taskqgroup_detach(tqg, &rxq->ifr_task); 4471 4472 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4473 free(fl->ifl_rx_bitmap, M_IFLIB); 4474 4475 } 4476 tqg = qgroup_if_config_tqg; 4477 if (ctx->ifc_admin_task.gt_uniq != NULL) 4478 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4479 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4480 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4481 4482 IFDI_DETACH(ctx); 4483 device_set_softc(ctx->ifc_dev, NULL); 4484 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4485 pci_release_msi(dev); 4486 } 4487 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4488 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4489 } 4490 if (ctx->ifc_msix_mem != NULL) { 4491 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4492 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4493 ctx->ifc_msix_mem = NULL; 4494 } 4495 4496 bus_generic_detach(dev); 4497 if_free(ifp); 4498 4499 iflib_tx_structures_free(ctx); 4500 iflib_rx_structures_free(ctx); 4501 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4502 free(ctx->ifc_softc, M_IFLIB); 4503 free(ctx, M_IFLIB); 4504 return (0); 4505 } 4506 4507 4508 int 4509 iflib_device_detach(device_t dev) 4510 { 4511 if_ctx_t ctx = device_get_softc(dev); 4512 4513 return (iflib_device_deregister(ctx)); 4514 } 4515 4516 int 4517 iflib_device_suspend(device_t dev) 4518 { 4519 if_ctx_t ctx = device_get_softc(dev); 4520 4521 CTX_LOCK(ctx); 4522 IFDI_SUSPEND(ctx); 4523 CTX_UNLOCK(ctx); 4524 4525 return bus_generic_suspend(dev); 4526 } 4527 int 4528 iflib_device_shutdown(device_t dev) 4529 { 4530 if_ctx_t ctx = device_get_softc(dev); 4531 4532 CTX_LOCK(ctx); 4533 IFDI_SHUTDOWN(ctx); 4534 CTX_UNLOCK(ctx); 4535 4536 return bus_generic_suspend(dev); 4537 } 4538 4539 4540 int 4541 iflib_device_resume(device_t dev) 4542 { 4543 if_ctx_t ctx = device_get_softc(dev); 4544 iflib_txq_t txq = ctx->ifc_txqs; 4545 4546 CTX_LOCK(ctx); 4547 IFDI_RESUME(ctx); 4548 iflib_init_locked(ctx); 4549 CTX_UNLOCK(ctx); 4550 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4551 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4552 4553 return (bus_generic_resume(dev)); 4554 } 4555 4556 int 4557 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4558 { 4559 int error; 4560 if_ctx_t ctx = device_get_softc(dev); 4561 4562 CTX_LOCK(ctx); 4563 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4564 CTX_UNLOCK(ctx); 4565 4566 return (error); 4567 } 4568 4569 void 4570 iflib_device_iov_uninit(device_t dev) 4571 { 4572 if_ctx_t ctx = device_get_softc(dev); 4573 4574 CTX_LOCK(ctx); 4575 IFDI_IOV_UNINIT(ctx); 4576 CTX_UNLOCK(ctx); 4577 } 4578 4579 int 4580 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 4581 { 4582 int error; 4583 if_ctx_t ctx = device_get_softc(dev); 4584 4585 CTX_LOCK(ctx); 4586 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 4587 CTX_UNLOCK(ctx); 4588 4589 return (error); 4590 } 4591 4592 /********************************************************************* 4593 * 4594 * MODULE FUNCTION DEFINITIONS 4595 * 4596 **********************************************************************/ 4597 4598 /* 4599 * - Start a fast taskqueue thread for each core 4600 * - Start a taskqueue for control operations 4601 */ 4602 static int 4603 iflib_module_init(void) 4604 { 4605 return (0); 4606 } 4607 4608 static int 4609 iflib_module_event_handler(module_t mod, int what, void *arg) 4610 { 4611 int err; 4612 4613 switch (what) { 4614 case MOD_LOAD: 4615 if ((err = iflib_module_init()) != 0) 4616 return (err); 4617 break; 4618 case MOD_UNLOAD: 4619 return (EBUSY); 4620 default: 4621 return (EOPNOTSUPP); 4622 } 4623 4624 return (0); 4625 } 4626 4627 /********************************************************************* 4628 * 4629 * PUBLIC FUNCTION DEFINITIONS 4630 * ordered as in iflib.h 4631 * 4632 **********************************************************************/ 4633 4634 4635 static void 4636 _iflib_assert(if_shared_ctx_t sctx) 4637 { 4638 MPASS(sctx->isc_tx_maxsize); 4639 MPASS(sctx->isc_tx_maxsegsize); 4640 4641 MPASS(sctx->isc_rx_maxsize); 4642 MPASS(sctx->isc_rx_nsegments); 4643 MPASS(sctx->isc_rx_maxsegsize); 4644 4645 MPASS(sctx->isc_nrxd_min[0]); 4646 MPASS(sctx->isc_nrxd_max[0]); 4647 MPASS(sctx->isc_nrxd_default[0]); 4648 MPASS(sctx->isc_ntxd_min[0]); 4649 MPASS(sctx->isc_ntxd_max[0]); 4650 MPASS(sctx->isc_ntxd_default[0]); 4651 } 4652 4653 static void 4654 _iflib_pre_assert(if_softc_ctx_t scctx) 4655 { 4656 4657 MPASS(scctx->isc_txrx->ift_txd_encap); 4658 MPASS(scctx->isc_txrx->ift_txd_flush); 4659 MPASS(scctx->isc_txrx->ift_txd_credits_update); 4660 MPASS(scctx->isc_txrx->ift_rxd_available); 4661 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 4662 MPASS(scctx->isc_txrx->ift_rxd_refill); 4663 MPASS(scctx->isc_txrx->ift_rxd_flush); 4664 } 4665 4666 static int 4667 iflib_register(if_ctx_t ctx) 4668 { 4669 if_shared_ctx_t sctx = ctx->ifc_sctx; 4670 driver_t *driver = sctx->isc_driver; 4671 device_t dev = ctx->ifc_dev; 4672 if_t ifp; 4673 4674 _iflib_assert(sctx); 4675 4676 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 4677 4678 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 4679 if (ifp == NULL) { 4680 device_printf(dev, "can not allocate ifnet structure\n"); 4681 return (ENOMEM); 4682 } 4683 4684 /* 4685 * Initialize our context's device specific methods 4686 */ 4687 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 4688 kobj_class_compile((kobj_class_t) driver); 4689 driver->refs++; 4690 4691 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 4692 if_setsoftc(ifp, ctx); 4693 if_setdev(ifp, dev); 4694 if_setinitfn(ifp, iflib_if_init); 4695 if_setioctlfn(ifp, iflib_if_ioctl); 4696 if_settransmitfn(ifp, iflib_if_transmit); 4697 if_setqflushfn(ifp, iflib_if_qflush); 4698 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 4699 4700 ctx->ifc_vlan_attach_event = 4701 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 4702 EVENTHANDLER_PRI_FIRST); 4703 ctx->ifc_vlan_detach_event = 4704 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 4705 EVENTHANDLER_PRI_FIRST); 4706 4707 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 4708 iflib_media_change, iflib_media_status); 4709 4710 return (0); 4711 } 4712 4713 4714 static int 4715 iflib_queues_alloc(if_ctx_t ctx) 4716 { 4717 if_shared_ctx_t sctx = ctx->ifc_sctx; 4718 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4719 device_t dev = ctx->ifc_dev; 4720 int nrxqsets = scctx->isc_nrxqsets; 4721 int ntxqsets = scctx->isc_ntxqsets; 4722 iflib_txq_t txq; 4723 iflib_rxq_t rxq; 4724 iflib_fl_t fl = NULL; 4725 int i, j, cpu, err, txconf, rxconf; 4726 iflib_dma_info_t ifdip; 4727 uint32_t *rxqsizes = scctx->isc_rxqsizes; 4728 uint32_t *txqsizes = scctx->isc_txqsizes; 4729 uint8_t nrxqs = sctx->isc_nrxqs; 4730 uint8_t ntxqs = sctx->isc_ntxqs; 4731 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 4732 caddr_t *vaddrs; 4733 uint64_t *paddrs; 4734 struct ifmp_ring **brscp; 4735 4736 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 4737 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 4738 4739 brscp = NULL; 4740 txq = NULL; 4741 rxq = NULL; 4742 4743 /* Allocate the TX ring struct memory */ 4744 if (!(txq = 4745 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 4746 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4747 device_printf(dev, "Unable to allocate TX ring memory\n"); 4748 err = ENOMEM; 4749 goto fail; 4750 } 4751 4752 /* Now allocate the RX */ 4753 if (!(rxq = 4754 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 4755 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4756 device_printf(dev, "Unable to allocate RX ring memory\n"); 4757 err = ENOMEM; 4758 goto rx_fail; 4759 } 4760 4761 ctx->ifc_txqs = txq; 4762 ctx->ifc_rxqs = rxq; 4763 4764 /* 4765 * XXX handle allocation failure 4766 */ 4767 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 4768 /* Set up some basics */ 4769 4770 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4771 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4772 err = ENOMEM; 4773 goto err_tx_desc; 4774 } 4775 txq->ift_ifdi = ifdip; 4776 for (j = 0; j < ntxqs; j++, ifdip++) { 4777 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4778 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4779 err = ENOMEM; 4780 goto err_tx_desc; 4781 } 4782 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 4783 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 4784 } 4785 txq->ift_ctx = ctx; 4786 txq->ift_id = i; 4787 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 4788 txq->ift_br_offset = 1; 4789 } else { 4790 txq->ift_br_offset = 0; 4791 } 4792 /* XXX fix this */ 4793 txq->ift_timer.c_cpu = cpu; 4794 4795 if (iflib_txsd_alloc(txq)) { 4796 device_printf(dev, "Critical Failure setting up TX buffers\n"); 4797 err = ENOMEM; 4798 goto err_tx_desc; 4799 } 4800 4801 /* Initialize the TX lock */ 4802 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 4803 device_get_nameunit(dev), txq->ift_id); 4804 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 4805 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 4806 4807 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 4808 device_get_nameunit(dev), txq->ift_id); 4809 4810 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 4811 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 4812 if (err) { 4813 /* XXX free any allocated rings */ 4814 device_printf(dev, "Unable to allocate buf_ring\n"); 4815 goto err_tx_desc; 4816 } 4817 } 4818 4819 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 4820 /* Set up some basics */ 4821 4822 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4823 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4824 err = ENOMEM; 4825 goto err_tx_desc; 4826 } 4827 4828 rxq->ifr_ifdi = ifdip; 4829 /* XXX this needs to be changed if #rx queues != #tx queues */ 4830 rxq->ifr_ntxqirq = 1; 4831 rxq->ifr_txqid[0] = i; 4832 for (j = 0; j < nrxqs; j++, ifdip++) { 4833 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4834 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4835 err = ENOMEM; 4836 goto err_tx_desc; 4837 } 4838 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 4839 } 4840 rxq->ifr_ctx = ctx; 4841 rxq->ifr_id = i; 4842 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 4843 rxq->ifr_fl_offset = 1; 4844 } else { 4845 rxq->ifr_fl_offset = 0; 4846 } 4847 rxq->ifr_nfl = nfree_lists; 4848 if (!(fl = 4849 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 4850 device_printf(dev, "Unable to allocate free list memory\n"); 4851 err = ENOMEM; 4852 goto err_tx_desc; 4853 } 4854 rxq->ifr_fl = fl; 4855 for (j = 0; j < nfree_lists; j++) { 4856 fl[j].ifl_rxq = rxq; 4857 fl[j].ifl_id = j; 4858 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 4859 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 4860 } 4861 /* Allocate receive buffers for the ring*/ 4862 if (iflib_rxsd_alloc(rxq)) { 4863 device_printf(dev, 4864 "Critical Failure setting up receive buffers\n"); 4865 err = ENOMEM; 4866 goto err_rx_desc; 4867 } 4868 4869 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4870 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 4871 } 4872 4873 /* TXQs */ 4874 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4875 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4876 for (i = 0; i < ntxqsets; i++) { 4877 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 4878 4879 for (j = 0; j < ntxqs; j++, di++) { 4880 vaddrs[i*ntxqs + j] = di->idi_vaddr; 4881 paddrs[i*ntxqs + j] = di->idi_paddr; 4882 } 4883 } 4884 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 4885 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4886 iflib_tx_structures_free(ctx); 4887 free(vaddrs, M_IFLIB); 4888 free(paddrs, M_IFLIB); 4889 goto err_rx_desc; 4890 } 4891 free(vaddrs, M_IFLIB); 4892 free(paddrs, M_IFLIB); 4893 4894 /* RXQs */ 4895 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4896 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4897 for (i = 0; i < nrxqsets; i++) { 4898 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 4899 4900 for (j = 0; j < nrxqs; j++, di++) { 4901 vaddrs[i*nrxqs + j] = di->idi_vaddr; 4902 paddrs[i*nrxqs + j] = di->idi_paddr; 4903 } 4904 } 4905 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 4906 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4907 iflib_tx_structures_free(ctx); 4908 free(vaddrs, M_IFLIB); 4909 free(paddrs, M_IFLIB); 4910 goto err_rx_desc; 4911 } 4912 free(vaddrs, M_IFLIB); 4913 free(paddrs, M_IFLIB); 4914 4915 return (0); 4916 4917 /* XXX handle allocation failure changes */ 4918 err_rx_desc: 4919 err_tx_desc: 4920 if (ctx->ifc_rxqs != NULL) 4921 free(ctx->ifc_rxqs, M_IFLIB); 4922 ctx->ifc_rxqs = NULL; 4923 if (ctx->ifc_txqs != NULL) 4924 free(ctx->ifc_txqs, M_IFLIB); 4925 ctx->ifc_txqs = NULL; 4926 rx_fail: 4927 if (brscp != NULL) 4928 free(brscp, M_IFLIB); 4929 if (rxq != NULL) 4930 free(rxq, M_IFLIB); 4931 if (txq != NULL) 4932 free(txq, M_IFLIB); 4933 fail: 4934 return (err); 4935 } 4936 4937 static int 4938 iflib_tx_structures_setup(if_ctx_t ctx) 4939 { 4940 iflib_txq_t txq = ctx->ifc_txqs; 4941 int i; 4942 4943 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4944 iflib_txq_setup(txq); 4945 4946 return (0); 4947 } 4948 4949 static void 4950 iflib_tx_structures_free(if_ctx_t ctx) 4951 { 4952 iflib_txq_t txq = ctx->ifc_txqs; 4953 int i, j; 4954 4955 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 4956 iflib_txq_destroy(txq); 4957 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 4958 iflib_dma_free(&txq->ift_ifdi[j]); 4959 } 4960 free(ctx->ifc_txqs, M_IFLIB); 4961 ctx->ifc_txqs = NULL; 4962 IFDI_QUEUES_FREE(ctx); 4963 } 4964 4965 /********************************************************************* 4966 * 4967 * Initialize all receive rings. 4968 * 4969 **********************************************************************/ 4970 static int 4971 iflib_rx_structures_setup(if_ctx_t ctx) 4972 { 4973 iflib_rxq_t rxq = ctx->ifc_rxqs; 4974 int q; 4975 #if defined(INET6) || defined(INET) 4976 int i, err; 4977 #endif 4978 4979 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 4980 #if defined(INET6) || defined(INET) 4981 tcp_lro_free(&rxq->ifr_lc); 4982 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 4983 TCP_LRO_ENTRIES, min(1024, 4984 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 4985 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 4986 goto fail; 4987 } 4988 rxq->ifr_lro_enabled = TRUE; 4989 #endif 4990 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 4991 } 4992 return (0); 4993 #if defined(INET6) || defined(INET) 4994 fail: 4995 /* 4996 * Free RX software descriptors allocated so far, we will only handle 4997 * the rings that completed, the failing case will have 4998 * cleaned up for itself. 'q' failed, so its the terminus. 4999 */ 5000 rxq = ctx->ifc_rxqs; 5001 for (i = 0; i < q; ++i, rxq++) { 5002 iflib_rx_sds_free(rxq); 5003 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5004 } 5005 return (err); 5006 #endif 5007 } 5008 5009 /********************************************************************* 5010 * 5011 * Free all receive rings. 5012 * 5013 **********************************************************************/ 5014 static void 5015 iflib_rx_structures_free(if_ctx_t ctx) 5016 { 5017 iflib_rxq_t rxq = ctx->ifc_rxqs; 5018 5019 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5020 iflib_rx_sds_free(rxq); 5021 } 5022 } 5023 5024 static int 5025 iflib_qset_structures_setup(if_ctx_t ctx) 5026 { 5027 int err; 5028 5029 if ((err = iflib_tx_structures_setup(ctx)) != 0) 5030 return (err); 5031 5032 if ((err = iflib_rx_structures_setup(ctx)) != 0) { 5033 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5034 iflib_tx_structures_free(ctx); 5035 iflib_rx_structures_free(ctx); 5036 } 5037 return (err); 5038 } 5039 5040 int 5041 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5042 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name) 5043 { 5044 5045 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5046 } 5047 5048 #ifdef SMP 5049 static int 5050 find_nth(if_ctx_t ctx, int qid) 5051 { 5052 cpuset_t cpus; 5053 int i, cpuid, eqid, count; 5054 5055 CPU_COPY(&ctx->ifc_cpus, &cpus); 5056 count = CPU_COUNT(&cpus); 5057 eqid = qid % count; 5058 /* clear up to the qid'th bit */ 5059 for (i = 0; i < eqid; i++) { 5060 cpuid = CPU_FFS(&cpus); 5061 MPASS(cpuid != 0); 5062 CPU_CLR(cpuid-1, &cpus); 5063 } 5064 cpuid = CPU_FFS(&cpus); 5065 MPASS(cpuid != 0); 5066 return (cpuid-1); 5067 } 5068 5069 #ifdef SCHED_ULE 5070 extern struct cpu_group *cpu_top; /* CPU topology */ 5071 5072 static int 5073 find_child_with_core(int cpu, struct cpu_group *grp) 5074 { 5075 int i; 5076 5077 if (grp->cg_children == 0) 5078 return -1; 5079 5080 MPASS(grp->cg_child); 5081 for (i = 0; i < grp->cg_children; i++) { 5082 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5083 return i; 5084 } 5085 5086 return -1; 5087 } 5088 5089 /* 5090 * Find the nth thread on the specified core 5091 */ 5092 static int 5093 find_thread(int cpu, int thread_num) 5094 { 5095 struct cpu_group *grp; 5096 int i; 5097 cpuset_t cs; 5098 5099 grp = cpu_top; 5100 if (grp == NULL) 5101 return cpu; 5102 i = 0; 5103 while ((i = find_child_with_core(cpu, grp)) != -1) { 5104 /* If the child only has one cpu, don't descend */ 5105 if (grp->cg_child[i].cg_count <= 1) 5106 break; 5107 grp = &grp->cg_child[i]; 5108 } 5109 5110 /* If they don't share at least an L2 cache, use the same CPU */ 5111 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5112 return cpu; 5113 5114 /* Now pick one */ 5115 CPU_COPY(&grp->cg_mask, &cs); 5116 for (i = thread_num % grp->cg_count; i > 0; i--) { 5117 MPASS(CPU_FFS(&cs)); 5118 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5119 } 5120 MPASS(CPU_FFS(&cs)); 5121 return CPU_FFS(&cs) - 1; 5122 } 5123 #else 5124 static int 5125 find_thread(int cpu, int thread_num __unused) 5126 { 5127 return cpu_id 5128 } 5129 #endif 5130 5131 static int 5132 get_thread_num(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5133 { 5134 switch (type) { 5135 case IFLIB_INTR_TX: 5136 /* TX queues get threads on the same core as the corresponding RX queue */ 5137 /* XXX handle multiple RX threads per core and more than two threads per core */ 5138 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5139 case IFLIB_INTR_RX: 5140 case IFLIB_INTR_RXTX: 5141 /* RX queues get the first thread on their core */ 5142 return qid / CPU_COUNT(&ctx->ifc_cpus); 5143 default: 5144 return -1; 5145 } 5146 } 5147 #else 5148 #define get_thread_num(ctx, type, qid) CPU_FIRST() 5149 #define find_thread(cpuid, tid) CPU_FIRST() 5150 #define find_nth(ctx, gid) CPU_FIRST() 5151 #endif 5152 5153 /* Just to avoid copy/paste */ 5154 static inline int 5155 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid, 5156 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, char *name) 5157 { 5158 int cpuid; 5159 int err, tid; 5160 5161 cpuid = find_nth(ctx, qid); 5162 tid = get_thread_num(ctx, type, qid); 5163 MPASS(tid >= 0); 5164 cpuid = find_thread(cpuid, tid); 5165 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name); 5166 if (err) { 5167 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err); 5168 return (err); 5169 } 5170 #ifdef notyet 5171 if (cpuid > ctx->ifc_cpuid_highest) 5172 ctx->ifc_cpuid_highest = cpuid; 5173 #endif 5174 MPASS(gtask->gt_taskqueue != NULL); 5175 return 0; 5176 } 5177 5178 int 5179 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5180 iflib_intr_type_t type, driver_filter_t *filter, 5181 void *filter_arg, int qid, char *name) 5182 { 5183 struct grouptask *gtask; 5184 struct taskqgroup *tqg; 5185 iflib_filter_info_t info; 5186 gtask_fn_t *fn; 5187 int tqrid, err; 5188 driver_filter_t *intr_fast; 5189 void *q; 5190 5191 info = &ctx->ifc_filter_info; 5192 tqrid = rid; 5193 5194 switch (type) { 5195 /* XXX merge tx/rx for netmap? */ 5196 case IFLIB_INTR_TX: 5197 q = &ctx->ifc_txqs[qid]; 5198 info = &ctx->ifc_txqs[qid].ift_filter_info; 5199 gtask = &ctx->ifc_txqs[qid].ift_task; 5200 tqg = qgroup_if_io_tqg; 5201 fn = _task_fn_tx; 5202 intr_fast = iflib_fast_intr; 5203 GROUPTASK_INIT(gtask, 0, fn, q); 5204 break; 5205 case IFLIB_INTR_RX: 5206 q = &ctx->ifc_rxqs[qid]; 5207 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5208 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5209 tqg = qgroup_if_io_tqg; 5210 fn = _task_fn_rx; 5211 intr_fast = iflib_fast_intr; 5212 GROUPTASK_INIT(gtask, 0, fn, q); 5213 break; 5214 case IFLIB_INTR_RXTX: 5215 q = &ctx->ifc_rxqs[qid]; 5216 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5217 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5218 tqg = qgroup_if_io_tqg; 5219 fn = _task_fn_rx; 5220 intr_fast = iflib_fast_intr_rxtx; 5221 GROUPTASK_INIT(gtask, 0, fn, q); 5222 break; 5223 case IFLIB_INTR_ADMIN: 5224 q = ctx; 5225 tqrid = -1; 5226 info = &ctx->ifc_filter_info; 5227 gtask = &ctx->ifc_admin_task; 5228 tqg = qgroup_if_config_tqg; 5229 fn = _task_fn_admin; 5230 intr_fast = iflib_fast_intr_ctx; 5231 break; 5232 default: 5233 panic("unknown net intr type"); 5234 } 5235 5236 info->ifi_filter = filter; 5237 info->ifi_filter_arg = filter_arg; 5238 info->ifi_task = gtask; 5239 info->ifi_ctx = q; 5240 5241 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5242 if (err != 0) { 5243 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 5244 return (err); 5245 } 5246 if (type == IFLIB_INTR_ADMIN) 5247 return (0); 5248 5249 if (tqrid != -1) { 5250 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name); 5251 if (err) 5252 return (err); 5253 } else { 5254 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5255 } 5256 5257 return (0); 5258 } 5259 5260 void 5261 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, char *name) 5262 { 5263 struct grouptask *gtask; 5264 struct taskqgroup *tqg; 5265 gtask_fn_t *fn; 5266 void *q; 5267 int irq_num = -1; 5268 int err; 5269 5270 switch (type) { 5271 case IFLIB_INTR_TX: 5272 q = &ctx->ifc_txqs[qid]; 5273 gtask = &ctx->ifc_txqs[qid].ift_task; 5274 tqg = qgroup_if_io_tqg; 5275 fn = _task_fn_tx; 5276 if (irq != NULL) 5277 irq_num = rman_get_start(irq->ii_res); 5278 break; 5279 case IFLIB_INTR_RX: 5280 q = &ctx->ifc_rxqs[qid]; 5281 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5282 tqg = qgroup_if_io_tqg; 5283 fn = _task_fn_rx; 5284 if (irq != NULL) 5285 irq_num = rman_get_start(irq->ii_res); 5286 break; 5287 case IFLIB_INTR_IOV: 5288 q = ctx; 5289 gtask = &ctx->ifc_vflr_task; 5290 tqg = qgroup_if_config_tqg; 5291 fn = _task_fn_iov; 5292 break; 5293 default: 5294 panic("unknown net intr type"); 5295 } 5296 GROUPTASK_INIT(gtask, 0, fn, q); 5297 if (irq_num != -1) { 5298 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name); 5299 if (err) 5300 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5301 } 5302 else { 5303 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5304 } 5305 } 5306 5307 void 5308 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5309 { 5310 if (irq->ii_tag) 5311 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5312 5313 if (irq->ii_res) 5314 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5315 } 5316 5317 static int 5318 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name) 5319 { 5320 iflib_txq_t txq = ctx->ifc_txqs; 5321 iflib_rxq_t rxq = ctx->ifc_rxqs; 5322 if_irq_t irq = &ctx->ifc_legacy_irq; 5323 iflib_filter_info_t info; 5324 struct grouptask *gtask; 5325 struct taskqgroup *tqg; 5326 gtask_fn_t *fn; 5327 int tqrid; 5328 void *q; 5329 int err; 5330 5331 q = &ctx->ifc_rxqs[0]; 5332 info = &rxq[0].ifr_filter_info; 5333 gtask = &rxq[0].ifr_task; 5334 tqg = qgroup_if_io_tqg; 5335 tqrid = irq->ii_rid = *rid; 5336 fn = _task_fn_rx; 5337 5338 ctx->ifc_flags |= IFC_LEGACY; 5339 info->ifi_filter = filter; 5340 info->ifi_filter_arg = filter_arg; 5341 info->ifi_task = gtask; 5342 info->ifi_ctx = ctx; 5343 5344 /* We allocate a single interrupt resource */ 5345 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5346 return (err); 5347 GROUPTASK_INIT(gtask, 0, fn, q); 5348 taskqgroup_attach(tqg, gtask, q, tqrid, name); 5349 5350 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5351 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, tqrid, "tx"); 5352 return (0); 5353 } 5354 5355 void 5356 iflib_led_create(if_ctx_t ctx) 5357 { 5358 5359 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5360 device_get_nameunit(ctx->ifc_dev)); 5361 } 5362 5363 void 5364 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5365 { 5366 5367 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5368 } 5369 5370 void 5371 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5372 { 5373 5374 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5375 } 5376 5377 void 5378 iflib_admin_intr_deferred(if_ctx_t ctx) 5379 { 5380 #ifdef INVARIANTS 5381 struct grouptask *gtask; 5382 5383 gtask = &ctx->ifc_admin_task; 5384 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5385 #endif 5386 5387 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5388 } 5389 5390 void 5391 iflib_iov_intr_deferred(if_ctx_t ctx) 5392 { 5393 5394 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5395 } 5396 5397 void 5398 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5399 { 5400 5401 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5402 } 5403 5404 void 5405 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn, 5406 char *name) 5407 { 5408 5409 GROUPTASK_INIT(gtask, 0, fn, ctx); 5410 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5411 } 5412 5413 void 5414 iflib_config_gtask_deinit(struct grouptask *gtask) 5415 { 5416 5417 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5418 } 5419 5420 void 5421 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5422 { 5423 if_t ifp = ctx->ifc_ifp; 5424 iflib_txq_t txq = ctx->ifc_txqs; 5425 5426 if_setbaudrate(ifp, baudrate); 5427 if (baudrate >= IF_Gbps(10)) 5428 ctx->ifc_flags |= IFC_PREFETCH; 5429 5430 /* If link down, disable watchdog */ 5431 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5432 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5433 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5434 } 5435 ctx->ifc_link_state = link_state; 5436 if_link_state_change(ifp, link_state); 5437 } 5438 5439 static int 5440 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5441 { 5442 int credits; 5443 #ifdef INVARIANTS 5444 int credits_pre = txq->ift_cidx_processed; 5445 #endif 5446 5447 if (ctx->isc_txd_credits_update == NULL) 5448 return (0); 5449 5450 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5451 return (0); 5452 5453 txq->ift_processed += credits; 5454 txq->ift_cidx_processed += credits; 5455 5456 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5457 if (txq->ift_cidx_processed >= txq->ift_size) 5458 txq->ift_cidx_processed -= txq->ift_size; 5459 return (credits); 5460 } 5461 5462 static int 5463 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5464 { 5465 5466 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5467 budget)); 5468 } 5469 5470 void 5471 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5472 const char *description, if_int_delay_info_t info, 5473 int offset, int value) 5474 { 5475 info->iidi_ctx = ctx; 5476 info->iidi_offset = offset; 5477 info->iidi_value = value; 5478 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5479 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5480 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5481 info, 0, iflib_sysctl_int_delay, "I", description); 5482 } 5483 5484 struct mtx * 5485 iflib_ctx_lock_get(if_ctx_t ctx) 5486 { 5487 5488 return (&ctx->ifc_mtx); 5489 } 5490 5491 static int 5492 iflib_msix_init(if_ctx_t ctx) 5493 { 5494 device_t dev = ctx->ifc_dev; 5495 if_shared_ctx_t sctx = ctx->ifc_sctx; 5496 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5497 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5498 int iflib_num_tx_queues, iflib_num_rx_queues; 5499 int err, admincnt, bar; 5500 5501 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 5502 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 5503 5504 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 5505 5506 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5507 admincnt = sctx->isc_admin_intrcnt; 5508 /* Override by global tuneable */ 5509 { 5510 int i; 5511 size_t len = sizeof(i); 5512 err = kernel_sysctlbyname(curthread, "hw.pci.enable_msix", &i, &len, NULL, 0, NULL, 0); 5513 if (err == 0) { 5514 if (i == 0) 5515 goto msi; 5516 } 5517 else { 5518 device_printf(dev, "unable to read hw.pci.enable_msix."); 5519 } 5520 } 5521 /* Override by tuneable */ 5522 if (scctx->isc_disable_msix) 5523 goto msi; 5524 5525 /* 5526 ** When used in a virtualized environment 5527 ** PCI BUSMASTER capability may not be set 5528 ** so explicity set it here and rewrite 5529 ** the ENABLE in the MSIX control register 5530 ** at this point to cause the host to 5531 ** successfully initialize us. 5532 */ 5533 { 5534 int msix_ctrl, rid; 5535 5536 pci_enable_busmaster(dev); 5537 rid = 0; 5538 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) { 5539 rid += PCIR_MSIX_CTRL; 5540 msix_ctrl = pci_read_config(dev, rid, 2); 5541 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 5542 pci_write_config(dev, rid, msix_ctrl, 2); 5543 } else { 5544 device_printf(dev, "PCIY_MSIX capability not found; " 5545 "or rid %d == 0.\n", rid); 5546 goto msi; 5547 } 5548 } 5549 5550 /* 5551 * bar == -1 => "trust me I know what I'm doing" 5552 * Some drivers are for hardware that is so shoddily 5553 * documented that no one knows which bars are which 5554 * so the developer has to map all bars. This hack 5555 * allows shoddy garbage to use msix in this framework. 5556 */ 5557 if (bar != -1) { 5558 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5559 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5560 if (ctx->ifc_msix_mem == NULL) { 5561 /* May not be enabled */ 5562 device_printf(dev, "Unable to map MSIX table \n"); 5563 goto msi; 5564 } 5565 } 5566 /* First try MSI/X */ 5567 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5568 device_printf(dev, "System has MSIX disabled \n"); 5569 bus_release_resource(dev, SYS_RES_MEMORY, 5570 bar, ctx->ifc_msix_mem); 5571 ctx->ifc_msix_mem = NULL; 5572 goto msi; 5573 } 5574 #if IFLIB_DEBUG 5575 /* use only 1 qset in debug mode */ 5576 queuemsgs = min(msgs - admincnt, 1); 5577 #else 5578 queuemsgs = msgs - admincnt; 5579 #endif 5580 #ifdef RSS 5581 queues = imin(queuemsgs, rss_getnumbuckets()); 5582 #else 5583 queues = queuemsgs; 5584 #endif 5585 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 5586 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 5587 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 5588 #ifdef RSS 5589 /* If we're doing RSS, clamp at the number of RSS buckets */ 5590 if (queues > rss_getnumbuckets()) 5591 queues = rss_getnumbuckets(); 5592 #endif 5593 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 5594 rx_queues = iflib_num_rx_queues; 5595 else 5596 rx_queues = queues; 5597 5598 if (rx_queues > scctx->isc_nrxqsets) 5599 rx_queues = scctx->isc_nrxqsets; 5600 5601 /* 5602 * We want this to be all logical CPUs by default 5603 */ 5604 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 5605 tx_queues = iflib_num_tx_queues; 5606 else 5607 tx_queues = mp_ncpus; 5608 5609 if (tx_queues > scctx->isc_ntxqsets) 5610 tx_queues = scctx->isc_ntxqsets; 5611 5612 if (ctx->ifc_sysctl_qs_eq_override == 0) { 5613 #ifdef INVARIANTS 5614 if (tx_queues != rx_queues) 5615 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 5616 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 5617 #endif 5618 tx_queues = min(rx_queues, tx_queues); 5619 rx_queues = min(rx_queues, tx_queues); 5620 } 5621 5622 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 5623 5624 vectors = rx_queues + admincnt; 5625 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 5626 device_printf(dev, 5627 "Using MSIX interrupts with %d vectors\n", vectors); 5628 scctx->isc_vectors = vectors; 5629 scctx->isc_nrxqsets = rx_queues; 5630 scctx->isc_ntxqsets = tx_queues; 5631 scctx->isc_intr = IFLIB_INTR_MSIX; 5632 5633 return (vectors); 5634 } else { 5635 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 5636 } 5637 msi: 5638 vectors = pci_msi_count(dev); 5639 scctx->isc_nrxqsets = 1; 5640 scctx->isc_ntxqsets = 1; 5641 scctx->isc_vectors = vectors; 5642 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 5643 device_printf(dev,"Using an MSI interrupt\n"); 5644 scctx->isc_intr = IFLIB_INTR_MSI; 5645 } else { 5646 device_printf(dev,"Using a Legacy interrupt\n"); 5647 scctx->isc_intr = IFLIB_INTR_LEGACY; 5648 } 5649 5650 return (vectors); 5651 } 5652 5653 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 5654 5655 static int 5656 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 5657 { 5658 int rc; 5659 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 5660 struct sbuf *sb; 5661 char *ring_state = "UNKNOWN"; 5662 5663 /* XXX needed ? */ 5664 rc = sysctl_wire_old_buffer(req, 0); 5665 MPASS(rc == 0); 5666 if (rc != 0) 5667 return (rc); 5668 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 5669 MPASS(sb != NULL); 5670 if (sb == NULL) 5671 return (ENOMEM); 5672 if (state[3] <= 3) 5673 ring_state = ring_states[state[3]]; 5674 5675 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 5676 state[0], state[1], state[2], ring_state); 5677 rc = sbuf_finish(sb); 5678 sbuf_delete(sb); 5679 return(rc); 5680 } 5681 5682 enum iflib_ndesc_handler { 5683 IFLIB_NTXD_HANDLER, 5684 IFLIB_NRXD_HANDLER, 5685 }; 5686 5687 static int 5688 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 5689 { 5690 if_ctx_t ctx = (void *)arg1; 5691 enum iflib_ndesc_handler type = arg2; 5692 char buf[256] = {0}; 5693 qidx_t *ndesc; 5694 char *p, *next; 5695 int nqs, rc, i; 5696 5697 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 5698 5699 nqs = 8; 5700 switch(type) { 5701 case IFLIB_NTXD_HANDLER: 5702 ndesc = ctx->ifc_sysctl_ntxds; 5703 if (ctx->ifc_sctx) 5704 nqs = ctx->ifc_sctx->isc_ntxqs; 5705 break; 5706 case IFLIB_NRXD_HANDLER: 5707 ndesc = ctx->ifc_sysctl_nrxds; 5708 if (ctx->ifc_sctx) 5709 nqs = ctx->ifc_sctx->isc_nrxqs; 5710 break; 5711 } 5712 if (nqs == 0) 5713 nqs = 8; 5714 5715 for (i=0; i<8; i++) { 5716 if (i >= nqs) 5717 break; 5718 if (i) 5719 strcat(buf, ","); 5720 sprintf(strchr(buf, 0), "%d", ndesc[i]); 5721 } 5722 5723 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 5724 if (rc || req->newptr == NULL) 5725 return rc; 5726 5727 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 5728 i++, p = strsep(&next, " ,")) { 5729 ndesc[i] = strtoul(p, NULL, 10); 5730 } 5731 5732 return(rc); 5733 } 5734 5735 #define NAME_BUFLEN 32 5736 static void 5737 iflib_add_device_sysctl_pre(if_ctx_t ctx) 5738 { 5739 device_t dev = iflib_get_dev(ctx); 5740 struct sysctl_oid_list *child, *oid_list; 5741 struct sysctl_ctx_list *ctx_list; 5742 struct sysctl_oid *node; 5743 5744 ctx_list = device_get_sysctl_ctx(dev); 5745 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 5746 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 5747 CTLFLAG_RD, NULL, "IFLIB fields"); 5748 oid_list = SYSCTL_CHILDREN(node); 5749 5750 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 5751 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 5752 "driver version"); 5753 5754 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 5755 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 5756 "# of txqs to use, 0 => use default #"); 5757 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 5758 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 5759 "# of rxqs to use, 0 => use default #"); 5760 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 5761 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 5762 "permit #txq != #rxq"); 5763 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 5764 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 5765 "disable MSIX (default 0)"); 5766 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 5767 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 5768 "set the rx budget"); 5769 5770 /* XXX change for per-queue sizes */ 5771 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 5772 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 5773 mp_ndesc_handler, "A", 5774 "list of # of tx descriptors to use, 0 = use default #"); 5775 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 5776 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 5777 mp_ndesc_handler, "A", 5778 "list of # of rx descriptors to use, 0 = use default #"); 5779 } 5780 5781 static void 5782 iflib_add_device_sysctl_post(if_ctx_t ctx) 5783 { 5784 if_shared_ctx_t sctx = ctx->ifc_sctx; 5785 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5786 device_t dev = iflib_get_dev(ctx); 5787 struct sysctl_oid_list *child; 5788 struct sysctl_ctx_list *ctx_list; 5789 iflib_fl_t fl; 5790 iflib_txq_t txq; 5791 iflib_rxq_t rxq; 5792 int i, j; 5793 char namebuf[NAME_BUFLEN]; 5794 char *qfmt; 5795 struct sysctl_oid *queue_node, *fl_node, *node; 5796 struct sysctl_oid_list *queue_list, *fl_list; 5797 ctx_list = device_get_sysctl_ctx(dev); 5798 5799 node = ctx->ifc_sysctl_node; 5800 child = SYSCTL_CHILDREN(node); 5801 5802 if (scctx->isc_ntxqsets > 100) 5803 qfmt = "txq%03d"; 5804 else if (scctx->isc_ntxqsets > 10) 5805 qfmt = "txq%02d"; 5806 else 5807 qfmt = "txq%d"; 5808 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 5809 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5810 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5811 CTLFLAG_RD, NULL, "Queue Name"); 5812 queue_list = SYSCTL_CHILDREN(queue_node); 5813 #if MEMORY_LOGGING 5814 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 5815 CTLFLAG_RD, 5816 &txq->ift_dequeued, "total mbufs freed"); 5817 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 5818 CTLFLAG_RD, 5819 &txq->ift_enqueued, "total mbufs enqueued"); 5820 #endif 5821 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 5822 CTLFLAG_RD, 5823 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 5824 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 5825 CTLFLAG_RD, 5826 &txq->ift_pullups, "# of times m_pullup was called"); 5827 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 5828 CTLFLAG_RD, 5829 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 5830 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 5831 CTLFLAG_RD, 5832 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 5833 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 5834 CTLFLAG_RD, 5835 &txq->ift_map_failed, "# of times dma map failed"); 5836 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 5837 CTLFLAG_RD, 5838 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 5839 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 5840 CTLFLAG_RD, 5841 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 5842 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 5843 CTLFLAG_RD, 5844 &txq->ift_pidx, 1, "Producer Index"); 5845 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 5846 CTLFLAG_RD, 5847 &txq->ift_cidx, 1, "Consumer Index"); 5848 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 5849 CTLFLAG_RD, 5850 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 5851 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 5852 CTLFLAG_RD, 5853 &txq->ift_in_use, 1, "descriptors in use"); 5854 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 5855 CTLFLAG_RD, 5856 &txq->ift_processed, "descriptors procesed for clean"); 5857 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 5858 CTLFLAG_RD, 5859 &txq->ift_cleaned, "total cleaned"); 5860 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 5861 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 5862 0, mp_ring_state_handler, "A", "soft ring state"); 5863 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 5864 CTLFLAG_RD, &txq->ift_br->enqueues, 5865 "# of enqueues to the mp_ring for this queue"); 5866 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 5867 CTLFLAG_RD, &txq->ift_br->drops, 5868 "# of drops in the mp_ring for this queue"); 5869 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 5870 CTLFLAG_RD, &txq->ift_br->starts, 5871 "# of normal consumer starts in the mp_ring for this queue"); 5872 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 5873 CTLFLAG_RD, &txq->ift_br->stalls, 5874 "# of consumer stalls in the mp_ring for this queue"); 5875 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 5876 CTLFLAG_RD, &txq->ift_br->restarts, 5877 "# of consumer restarts in the mp_ring for this queue"); 5878 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 5879 CTLFLAG_RD, &txq->ift_br->abdications, 5880 "# of consumer abdications in the mp_ring for this queue"); 5881 } 5882 5883 if (scctx->isc_nrxqsets > 100) 5884 qfmt = "rxq%03d"; 5885 else if (scctx->isc_nrxqsets > 10) 5886 qfmt = "rxq%02d"; 5887 else 5888 qfmt = "rxq%d"; 5889 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 5890 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5891 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5892 CTLFLAG_RD, NULL, "Queue Name"); 5893 queue_list = SYSCTL_CHILDREN(queue_node); 5894 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5895 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 5896 CTLFLAG_RD, 5897 &rxq->ifr_cq_pidx, 1, "Producer Index"); 5898 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 5899 CTLFLAG_RD, 5900 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 5901 } 5902 5903 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 5904 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 5905 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 5906 CTLFLAG_RD, NULL, "freelist Name"); 5907 fl_list = SYSCTL_CHILDREN(fl_node); 5908 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 5909 CTLFLAG_RD, 5910 &fl->ifl_pidx, 1, "Producer Index"); 5911 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 5912 CTLFLAG_RD, 5913 &fl->ifl_cidx, 1, "Consumer Index"); 5914 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 5915 CTLFLAG_RD, 5916 &fl->ifl_credits, 1, "credits available"); 5917 #if MEMORY_LOGGING 5918 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 5919 CTLFLAG_RD, 5920 &fl->ifl_m_enqueued, "mbufs allocated"); 5921 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 5922 CTLFLAG_RD, 5923 &fl->ifl_m_dequeued, "mbufs freed"); 5924 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 5925 CTLFLAG_RD, 5926 &fl->ifl_cl_enqueued, "clusters allocated"); 5927 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 5928 CTLFLAG_RD, 5929 &fl->ifl_cl_dequeued, "clusters freed"); 5930 #endif 5931 5932 } 5933 } 5934 5935 } 5936 5937 #ifndef __NO_STRICT_ALIGNMENT 5938 static struct mbuf * 5939 iflib_fixup_rx(struct mbuf *m) 5940 { 5941 struct mbuf *n; 5942 5943 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 5944 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 5945 m->m_data += ETHER_HDR_LEN; 5946 n = m; 5947 } else { 5948 MGETHDR(n, M_NOWAIT, MT_DATA); 5949 if (n == NULL) { 5950 m_freem(m); 5951 return (NULL); 5952 } 5953 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 5954 m->m_data += ETHER_HDR_LEN; 5955 m->m_len -= ETHER_HDR_LEN; 5956 n->m_len = ETHER_HDR_LEN; 5957 M_MOVE_PKTHDR(n, m); 5958 n->m_next = m; 5959 } 5960 return (n); 5961 } 5962 #endif 5963