1 /*- 2 * Copyright (c) 2014-2017, Matthew Macy <mmacy@nextbsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 35 #include <sys/param.h> 36 #include <sys/types.h> 37 #include <sys/bus.h> 38 #include <sys/eventhandler.h> 39 #include <sys/sockio.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sysctl.h> 50 #include <sys/syslog.h> 51 #include <sys/taskqueue.h> 52 #include <sys/limits.h> 53 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 63 #include <netinet/in.h> 64 #include <netinet/in_pcb.h> 65 #include <netinet/tcp_lro.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/if_ether.h> 68 #include <netinet/ip.h> 69 #include <netinet/ip6.h> 70 #include <netinet/tcp.h> 71 72 #include <machine/bus.h> 73 #include <machine/in_cksum.h> 74 75 #include <vm/vm.h> 76 #include <vm/pmap.h> 77 78 #include <dev/led/led.h> 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pci_private.h> 82 83 #include <net/iflib.h> 84 85 #include "ifdi_if.h" 86 87 #if defined(__i386__) || defined(__amd64__) 88 #include <sys/memdesc.h> 89 #include <machine/bus.h> 90 #include <machine/md_var.h> 91 #include <machine/specialreg.h> 92 #include <x86/include/busdma_impl.h> 93 #include <x86/iommu/busdma_dmar.h> 94 #endif 95 96 #include <sys/bitstring.h> 97 /* 98 * enable accounting of every mbuf as it comes in to and goes out of 99 * iflib's software descriptor references 100 */ 101 #define MEMORY_LOGGING 0 102 /* 103 * Enable mbuf vectors for compressing long mbuf chains 104 */ 105 106 /* 107 * NB: 108 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 109 * we prefetch needs to be determined by the time spent in m_free vis a vis 110 * the cost of a prefetch. This will of course vary based on the workload: 111 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 112 * is quite expensive, thus suggesting very little prefetch. 113 * - small packet forwarding which is just returning a single mbuf to 114 * UMA will typically be very fast vis a vis the cost of a memory 115 * access. 116 */ 117 118 119 /* 120 * File organization: 121 * - private structures 122 * - iflib private utility functions 123 * - ifnet functions 124 * - vlan registry and other exported functions 125 * - iflib public core functions 126 * 127 * 128 */ 129 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 130 131 struct iflib_txq; 132 typedef struct iflib_txq *iflib_txq_t; 133 struct iflib_rxq; 134 typedef struct iflib_rxq *iflib_rxq_t; 135 struct iflib_fl; 136 typedef struct iflib_fl *iflib_fl_t; 137 138 struct iflib_ctx; 139 140 typedef struct iflib_filter_info { 141 driver_filter_t *ifi_filter; 142 void *ifi_filter_arg; 143 struct grouptask *ifi_task; 144 void *ifi_ctx; 145 } *iflib_filter_info_t; 146 147 struct iflib_ctx { 148 KOBJ_FIELDS; 149 /* 150 * Pointer to hardware driver's softc 151 */ 152 void *ifc_softc; 153 device_t ifc_dev; 154 if_t ifc_ifp; 155 156 cpuset_t ifc_cpus; 157 if_shared_ctx_t ifc_sctx; 158 struct if_softc_ctx ifc_softc_ctx; 159 160 struct mtx ifc_mtx; 161 162 uint16_t ifc_nhwtxqs; 163 uint16_t ifc_nhwrxqs; 164 165 iflib_txq_t ifc_txqs; 166 iflib_rxq_t ifc_rxqs; 167 uint32_t ifc_if_flags; 168 uint32_t ifc_flags; 169 uint32_t ifc_max_fl_buf_size; 170 int ifc_in_detach; 171 172 int ifc_link_state; 173 int ifc_link_irq; 174 int ifc_watchdog_events; 175 struct cdev *ifc_led_dev; 176 struct resource *ifc_msix_mem; 177 178 struct if_irq ifc_legacy_irq; 179 struct grouptask ifc_admin_task; 180 struct grouptask ifc_vflr_task; 181 struct iflib_filter_info ifc_filter_info; 182 struct ifmedia ifc_media; 183 184 struct sysctl_oid *ifc_sysctl_node; 185 uint16_t ifc_sysctl_ntxqs; 186 uint16_t ifc_sysctl_nrxqs; 187 uint16_t ifc_sysctl_qs_eq_override; 188 uint16_t ifc_sysctl_rx_budget; 189 190 qidx_t ifc_sysctl_ntxds[8]; 191 qidx_t ifc_sysctl_nrxds[8]; 192 struct if_txrx ifc_txrx; 193 #define isc_txd_encap ifc_txrx.ift_txd_encap 194 #define isc_txd_flush ifc_txrx.ift_txd_flush 195 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 196 #define isc_rxd_available ifc_txrx.ift_rxd_available 197 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 198 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 199 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 200 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 201 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 202 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 203 eventhandler_tag ifc_vlan_attach_event; 204 eventhandler_tag ifc_vlan_detach_event; 205 uint8_t ifc_mac[ETHER_ADDR_LEN]; 206 char ifc_mtx_name[16]; 207 }; 208 209 210 void * 211 iflib_get_softc(if_ctx_t ctx) 212 { 213 214 return (ctx->ifc_softc); 215 } 216 217 device_t 218 iflib_get_dev(if_ctx_t ctx) 219 { 220 221 return (ctx->ifc_dev); 222 } 223 224 if_t 225 iflib_get_ifp(if_ctx_t ctx) 226 { 227 228 return (ctx->ifc_ifp); 229 } 230 231 struct ifmedia * 232 iflib_get_media(if_ctx_t ctx) 233 { 234 235 return (&ctx->ifc_media); 236 } 237 238 void 239 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 240 { 241 242 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 243 } 244 245 if_softc_ctx_t 246 iflib_get_softc_ctx(if_ctx_t ctx) 247 { 248 249 return (&ctx->ifc_softc_ctx); 250 } 251 252 if_shared_ctx_t 253 iflib_get_sctx(if_ctx_t ctx) 254 { 255 256 return (ctx->ifc_sctx); 257 } 258 259 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 260 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 261 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 262 263 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 264 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 265 266 #define RX_SW_DESC_MAP_CREATED (1 << 0) 267 #define TX_SW_DESC_MAP_CREATED (1 << 1) 268 #define RX_SW_DESC_INUSE (1 << 3) 269 #define TX_SW_DESC_MAPPED (1 << 4) 270 271 #define M_TOOBIG M_PROTO1 272 273 typedef struct iflib_sw_rx_desc_array { 274 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 275 struct mbuf **ifsd_m; /* pkthdr mbufs */ 276 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 277 uint8_t *ifsd_flags; 278 } iflib_rxsd_array_t; 279 280 typedef struct iflib_sw_tx_desc_array { 281 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 282 struct mbuf **ifsd_m; /* pkthdr mbufs */ 283 uint8_t *ifsd_flags; 284 } if_txsd_vec_t; 285 286 287 /* magic number that should be high enough for any hardware */ 288 #define IFLIB_MAX_TX_SEGS 128 289 #define IFLIB_MAX_RX_SEGS 32 290 #define IFLIB_RX_COPY_THRESH 128 291 #define IFLIB_MAX_RX_REFRESH 32 292 /* The minimum descriptors per second before we start coalescing */ 293 #define IFLIB_MIN_DESC_SEC 16384 294 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 295 #define IFLIB_QUEUE_IDLE 0 296 #define IFLIB_QUEUE_HUNG 1 297 #define IFLIB_QUEUE_WORKING 2 298 /* maximum number of txqs that can share an rx interrupt */ 299 #define IFLIB_MAX_TX_SHARED_INTR 4 300 301 /* this should really scale with ring size - this is a fairly arbitrary value */ 302 #define TX_BATCH_SIZE 32 303 304 #define IFLIB_RESTART_BUDGET 8 305 306 #define IFC_LEGACY 0x001 307 #define IFC_QFLUSH 0x002 308 #define IFC_MULTISEG 0x004 309 #define IFC_DMAR 0x008 310 #define IFC_SC_ALLOCATED 0x010 311 #define IFC_INIT_DONE 0x020 312 #define IFC_PREFETCH 0x040 313 #define IFC_DO_RESET 0x080 314 #define IFC_CHECK_HUNG 0x100 315 316 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 317 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 318 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 319 struct iflib_txq { 320 qidx_t ift_in_use; 321 qidx_t ift_cidx; 322 qidx_t ift_cidx_processed; 323 qidx_t ift_pidx; 324 uint8_t ift_gen; 325 uint8_t ift_br_offset; 326 uint16_t ift_npending; 327 uint16_t ift_db_pending; 328 uint16_t ift_rs_pending; 329 /* implicit pad */ 330 uint8_t ift_txd_size[8]; 331 uint64_t ift_processed; 332 uint64_t ift_cleaned; 333 uint64_t ift_cleaned_prev; 334 #if MEMORY_LOGGING 335 uint64_t ift_enqueued; 336 uint64_t ift_dequeued; 337 #endif 338 uint64_t ift_no_tx_dma_setup; 339 uint64_t ift_no_desc_avail; 340 uint64_t ift_mbuf_defrag_failed; 341 uint64_t ift_mbuf_defrag; 342 uint64_t ift_map_failed; 343 uint64_t ift_txd_encap_efbig; 344 uint64_t ift_pullups; 345 346 struct mtx ift_mtx; 347 struct mtx ift_db_mtx; 348 349 /* constant values */ 350 if_ctx_t ift_ctx; 351 struct ifmp_ring *ift_br; 352 struct grouptask ift_task; 353 qidx_t ift_size; 354 uint16_t ift_id; 355 struct callout ift_timer; 356 357 if_txsd_vec_t ift_sds; 358 uint8_t ift_qstatus; 359 uint8_t ift_closed; 360 uint8_t ift_update_freq; 361 struct iflib_filter_info ift_filter_info; 362 bus_dma_tag_t ift_desc_tag; 363 bus_dma_tag_t ift_tso_desc_tag; 364 iflib_dma_info_t ift_ifdi; 365 #define MTX_NAME_LEN 16 366 char ift_mtx_name[MTX_NAME_LEN]; 367 char ift_db_mtx_name[MTX_NAME_LEN]; 368 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 369 #ifdef IFLIB_DIAGNOSTICS 370 uint64_t ift_cpu_exec_count[256]; 371 #endif 372 } __aligned(CACHE_LINE_SIZE); 373 374 struct iflib_fl { 375 qidx_t ifl_cidx; 376 qidx_t ifl_pidx; 377 qidx_t ifl_credits; 378 uint8_t ifl_gen; 379 uint8_t ifl_rxd_size; 380 #if MEMORY_LOGGING 381 uint64_t ifl_m_enqueued; 382 uint64_t ifl_m_dequeued; 383 uint64_t ifl_cl_enqueued; 384 uint64_t ifl_cl_dequeued; 385 #endif 386 /* implicit pad */ 387 388 bitstr_t *ifl_rx_bitmap; 389 qidx_t ifl_fragidx; 390 /* constant */ 391 qidx_t ifl_size; 392 uint16_t ifl_buf_size; 393 uint16_t ifl_cltype; 394 uma_zone_t ifl_zone; 395 iflib_rxsd_array_t ifl_sds; 396 iflib_rxq_t ifl_rxq; 397 uint8_t ifl_id; 398 bus_dma_tag_t ifl_desc_tag; 399 iflib_dma_info_t ifl_ifdi; 400 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 401 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 402 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 403 } __aligned(CACHE_LINE_SIZE); 404 405 static inline qidx_t 406 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 407 { 408 qidx_t used; 409 410 if (pidx > cidx) 411 used = pidx - cidx; 412 else if (pidx < cidx) 413 used = size - cidx + pidx; 414 else if (gen == 0 && pidx == cidx) 415 used = 0; 416 else if (gen == 1 && pidx == cidx) 417 used = size; 418 else 419 panic("bad state"); 420 421 return (used); 422 } 423 424 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 425 426 #define IDXDIFF(head, tail, wrap) \ 427 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 428 429 struct iflib_rxq { 430 /* If there is a separate completion queue - 431 * these are the cq cidx and pidx. Otherwise 432 * these are unused. 433 */ 434 qidx_t ifr_size; 435 qidx_t ifr_cq_cidx; 436 qidx_t ifr_cq_pidx; 437 uint8_t ifr_cq_gen; 438 uint8_t ifr_fl_offset; 439 440 if_ctx_t ifr_ctx; 441 iflib_fl_t ifr_fl; 442 uint64_t ifr_rx_irq; 443 uint16_t ifr_id; 444 uint8_t ifr_lro_enabled; 445 uint8_t ifr_nfl; 446 uint8_t ifr_ntxqirq; 447 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 448 struct lro_ctrl ifr_lc; 449 struct grouptask ifr_task; 450 struct iflib_filter_info ifr_filter_info; 451 iflib_dma_info_t ifr_ifdi; 452 453 /* dynamically allocate if any drivers need a value substantially larger than this */ 454 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 455 #ifdef IFLIB_DIAGNOSTICS 456 uint64_t ifr_cpu_exec_count[256]; 457 #endif 458 } __aligned(CACHE_LINE_SIZE); 459 460 typedef struct if_rxsd { 461 caddr_t *ifsd_cl; 462 struct mbuf **ifsd_m; 463 iflib_fl_t ifsd_fl; 464 qidx_t ifsd_cidx; 465 } *if_rxsd_t; 466 467 /* multiple of word size */ 468 #ifdef __LP64__ 469 #define PKT_INFO_SIZE 6 470 #define RXD_INFO_SIZE 5 471 #define PKT_TYPE uint64_t 472 #else 473 #define PKT_INFO_SIZE 11 474 #define RXD_INFO_SIZE 8 475 #define PKT_TYPE uint32_t 476 #endif 477 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 478 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 479 480 typedef struct if_pkt_info_pad { 481 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 482 } *if_pkt_info_pad_t; 483 typedef struct if_rxd_info_pad { 484 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 485 } *if_rxd_info_pad_t; 486 487 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 488 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 489 490 491 static inline void 492 pkt_info_zero(if_pkt_info_t pi) 493 { 494 if_pkt_info_pad_t pi_pad; 495 496 pi_pad = (if_pkt_info_pad_t)pi; 497 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 498 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 499 #ifndef __LP64__ 500 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 501 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 502 #endif 503 } 504 505 static inline void 506 rxd_info_zero(if_rxd_info_t ri) 507 { 508 if_rxd_info_pad_t ri_pad; 509 int i; 510 511 ri_pad = (if_rxd_info_pad_t)ri; 512 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 513 ri_pad->rxd_val[i] = 0; 514 ri_pad->rxd_val[i+1] = 0; 515 ri_pad->rxd_val[i+2] = 0; 516 ri_pad->rxd_val[i+3] = 0; 517 } 518 #ifdef __LP64__ 519 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 520 #endif 521 } 522 523 /* 524 * Only allow a single packet to take up most 1/nth of the tx ring 525 */ 526 #define MAX_SINGLE_PACKET_FRACTION 12 527 #define IF_BAD_DMA (bus_addr_t)-1 528 529 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 530 531 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF) 532 533 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx) 534 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx) 535 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx) 536 537 538 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 539 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 540 541 542 /* Our boot-time initialization hook */ 543 static int iflib_module_event_handler(module_t, int, void *); 544 545 static moduledata_t iflib_moduledata = { 546 "iflib", 547 iflib_module_event_handler, 548 NULL 549 }; 550 551 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 552 MODULE_VERSION(iflib, 1); 553 554 MODULE_DEPEND(iflib, pci, 1, 1, 1); 555 MODULE_DEPEND(iflib, ether, 1, 1, 1); 556 557 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 558 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 559 560 #ifndef IFLIB_DEBUG_COUNTERS 561 #ifdef INVARIANTS 562 #define IFLIB_DEBUG_COUNTERS 1 563 #else 564 #define IFLIB_DEBUG_COUNTERS 0 565 #endif /* !INVARIANTS */ 566 #endif 567 568 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 569 "iflib driver parameters"); 570 571 /* 572 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 573 */ 574 static int iflib_min_tx_latency = 0; 575 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 576 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 577 static int iflib_no_tx_batch = 0; 578 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 579 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 580 581 582 #if IFLIB_DEBUG_COUNTERS 583 584 static int iflib_tx_seen; 585 static int iflib_tx_sent; 586 static int iflib_tx_encap; 587 static int iflib_rx_allocs; 588 static int iflib_fl_refills; 589 static int iflib_fl_refills_large; 590 static int iflib_tx_frees; 591 592 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 593 &iflib_tx_seen, 0, "# tx mbufs seen"); 594 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 595 &iflib_tx_sent, 0, "# tx mbufs sent"); 596 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 597 &iflib_tx_encap, 0, "# tx mbufs encapped"); 598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 599 &iflib_tx_frees, 0, "# tx frees"); 600 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 601 &iflib_rx_allocs, 0, "# rx allocations"); 602 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 603 &iflib_fl_refills, 0, "# refills"); 604 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 605 &iflib_fl_refills_large, 0, "# large refills"); 606 607 608 static int iflib_txq_drain_flushing; 609 static int iflib_txq_drain_oactive; 610 static int iflib_txq_drain_notready; 611 static int iflib_txq_drain_encapfail; 612 613 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 614 &iflib_txq_drain_flushing, 0, "# drain flushes"); 615 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 616 &iflib_txq_drain_oactive, 0, "# drain oactives"); 617 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 618 &iflib_txq_drain_notready, 0, "# drain notready"); 619 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 620 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 621 622 623 static int iflib_encap_load_mbuf_fail; 624 static int iflib_encap_txq_avail_fail; 625 static int iflib_encap_txd_encap_fail; 626 627 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 628 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 629 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 630 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 632 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 633 634 static int iflib_task_fn_rxs; 635 static int iflib_rx_intr_enables; 636 static int iflib_fast_intrs; 637 static int iflib_intr_link; 638 static int iflib_intr_msix; 639 static int iflib_rx_unavail; 640 static int iflib_rx_ctx_inactive; 641 static int iflib_rx_zero_len; 642 static int iflib_rx_if_input; 643 static int iflib_rx_mbuf_null; 644 static int iflib_rxd_flush; 645 646 static int iflib_verbose_debug; 647 648 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 649 &iflib_intr_link, 0, "# intr link calls"); 650 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 651 &iflib_intr_msix, 0, "# intr msix calls"); 652 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 653 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 654 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 655 &iflib_rx_intr_enables, 0, "# rx intr enables"); 656 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 657 &iflib_fast_intrs, 0, "# fast_intr calls"); 658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 659 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 661 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 663 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 665 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 666 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 667 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 668 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 669 &iflib_rxd_flush, 0, "# times rxd_flush called"); 670 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 671 &iflib_verbose_debug, 0, "enable verbose debugging"); 672 673 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 674 static void 675 iflib_debug_reset(void) 676 { 677 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 678 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 679 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 680 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 681 iflib_encap_load_mbuf_fail = iflib_encap_txq_avail_fail = 682 iflib_encap_txd_encap_fail = iflib_task_fn_rxs = iflib_rx_intr_enables = 683 iflib_fast_intrs = iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 684 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 685 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 686 } 687 688 #else 689 #define DBG_COUNTER_INC(name) 690 static void iflib_debug_reset(void) {} 691 #endif 692 693 694 695 #define IFLIB_DEBUG 0 696 697 static void iflib_tx_structures_free(if_ctx_t ctx); 698 static void iflib_rx_structures_free(if_ctx_t ctx); 699 static int iflib_queues_alloc(if_ctx_t ctx); 700 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 701 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 702 static int iflib_qset_structures_setup(if_ctx_t ctx); 703 static int iflib_msix_init(if_ctx_t ctx); 704 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str); 705 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 706 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 707 static int iflib_register(if_ctx_t); 708 static void iflib_init_locked(if_ctx_t ctx); 709 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 710 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 711 static void iflib_ifmp_purge(iflib_txq_t txq); 712 static void _iflib_pre_assert(if_softc_ctx_t scctx); 713 static void iflib_stop(if_ctx_t ctx); 714 static void iflib_if_init_locked(if_ctx_t ctx); 715 #ifndef __NO_STRICT_ALIGNMENT 716 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 717 #endif 718 719 #ifdef DEV_NETMAP 720 #include <sys/selinfo.h> 721 #include <net/netmap.h> 722 #include <dev/netmap/netmap_kern.h> 723 724 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 725 726 /* 727 * device-specific sysctl variables: 728 * 729 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 730 * During regular operations the CRC is stripped, but on some 731 * hardware reception of frames not multiple of 64 is slower, 732 * so using crcstrip=0 helps in benchmarks. 733 * 734 * iflib_rx_miss, iflib_rx_miss_bufs: 735 * count packets that might be missed due to lost interrupts. 736 */ 737 SYSCTL_DECL(_dev_netmap); 738 /* 739 * The xl driver by default strips CRCs and we do not override it. 740 */ 741 742 int iflib_crcstrip = 1; 743 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 744 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 745 746 int iflib_rx_miss, iflib_rx_miss_bufs; 747 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 748 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 749 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 750 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 751 752 /* 753 * Register/unregister. We are already under netmap lock. 754 * Only called on the first register or the last unregister. 755 */ 756 static int 757 iflib_netmap_register(struct netmap_adapter *na, int onoff) 758 { 759 struct ifnet *ifp = na->ifp; 760 if_ctx_t ctx = ifp->if_softc; 761 int status; 762 763 CTX_LOCK(ctx); 764 IFDI_INTR_DISABLE(ctx); 765 766 /* Tell the stack that the interface is no longer active */ 767 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 768 769 if (!CTX_IS_VF(ctx)) 770 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 771 772 /* enable or disable flags and callbacks in na and ifp */ 773 if (onoff) { 774 nm_set_native_flags(na); 775 } else { 776 nm_clear_native_flags(na); 777 } 778 iflib_stop(ctx); 779 iflib_init_locked(ctx); 780 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 781 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 782 if (status) 783 nm_clear_native_flags(na); 784 CTX_UNLOCK(ctx); 785 return (status); 786 } 787 788 /* 789 * Reconcile kernel and user view of the transmit ring. 790 * 791 * All information is in the kring. 792 * Userspace wants to send packets up to the one before kring->rhead, 793 * kernel knows kring->nr_hwcur is the first unsent packet. 794 * 795 * Here we push packets out (as many as possible), and possibly 796 * reclaim buffers from previously completed transmission. 797 * 798 * The caller (netmap) guarantees that there is only one instance 799 * running at any time. Any interference with other driver 800 * methods should be handled by the individual drivers. 801 */ 802 static int 803 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 804 { 805 struct netmap_adapter *na = kring->na; 806 struct ifnet *ifp = na->ifp; 807 struct netmap_ring *ring = kring->ring; 808 u_int nm_i; /* index into the netmap ring */ 809 u_int nic_i; /* index into the NIC ring */ 810 u_int n; 811 u_int const lim = kring->nkr_num_slots - 1; 812 u_int const head = kring->rhead; 813 struct if_pkt_info pi; 814 815 /* 816 * interrupts on every tx packet are expensive so request 817 * them every half ring, or where NS_REPORT is set 818 */ 819 u_int report_frequency = kring->nkr_num_slots >> 1; 820 /* device-specific */ 821 if_ctx_t ctx = ifp->if_softc; 822 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 823 824 if (txq->ift_sds.ifsd_map) 825 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 826 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 827 828 829 /* 830 * First part: process new packets to send. 831 * nm_i is the current index in the netmap ring, 832 * nic_i is the corresponding index in the NIC ring. 833 * 834 * If we have packets to send (nm_i != head) 835 * iterate over the netmap ring, fetch length and update 836 * the corresponding slot in the NIC ring. Some drivers also 837 * need to update the buffer's physical address in the NIC slot 838 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 839 * 840 * The netmap_reload_map() calls is especially expensive, 841 * even when (as in this case) the tag is 0, so do only 842 * when the buffer has actually changed. 843 * 844 * If possible do not set the report/intr bit on all slots, 845 * but only a few times per ring or when NS_REPORT is set. 846 * 847 * Finally, on 10G and faster drivers, it might be useful 848 * to prefetch the next slot and txr entry. 849 */ 850 851 nm_i = kring->nr_hwcur; 852 pkt_info_zero(&pi); 853 pi.ipi_segs = txq->ift_segs; 854 pi.ipi_qsidx = kring->ring_id; 855 if (nm_i != head) { /* we have new packets to send */ 856 nic_i = netmap_idx_k2n(kring, nm_i); 857 858 __builtin_prefetch(&ring->slot[nm_i]); 859 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 860 if (txq->ift_sds.ifsd_map) 861 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 862 863 for (n = 0; nm_i != head; n++) { 864 struct netmap_slot *slot = &ring->slot[nm_i]; 865 u_int len = slot->len; 866 uint64_t paddr; 867 void *addr = PNMB(na, slot, &paddr); 868 int flags = (slot->flags & NS_REPORT || 869 nic_i == 0 || nic_i == report_frequency) ? 870 IPI_TX_INTR : 0; 871 872 /* device-specific */ 873 pi.ipi_len = len; 874 pi.ipi_segs[0].ds_addr = paddr; 875 pi.ipi_segs[0].ds_len = len; 876 pi.ipi_nsegs = 1; 877 pi.ipi_ndescs = 0; 878 pi.ipi_pidx = nic_i; 879 pi.ipi_flags = flags; 880 881 /* Fill the slot in the NIC ring. */ 882 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 883 884 /* prefetch for next round */ 885 __builtin_prefetch(&ring->slot[nm_i + 1]); 886 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 887 if (txq->ift_sds.ifsd_map) { 888 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 889 890 NM_CHECK_ADDR_LEN(na, addr, len); 891 892 if (slot->flags & NS_BUF_CHANGED) { 893 /* buffer has changed, reload map */ 894 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 895 } 896 /* make sure changes to the buffer are synced */ 897 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 898 BUS_DMASYNC_PREWRITE); 899 } 900 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 901 nm_i = nm_next(nm_i, lim); 902 nic_i = nm_next(nic_i, lim); 903 } 904 kring->nr_hwcur = head; 905 906 /* synchronize the NIC ring */ 907 if (txq->ift_sds.ifsd_map) 908 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 909 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 910 911 /* (re)start the tx unit up to slot nic_i (excluded) */ 912 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 913 } 914 915 /* 916 * Second part: reclaim buffers for completed transmissions. 917 */ 918 if (iflib_tx_credits_update(ctx, txq)) { 919 /* some tx completed, increment avail */ 920 nic_i = txq->ift_cidx_processed; 921 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 922 } 923 return (0); 924 } 925 926 /* 927 * Reconcile kernel and user view of the receive ring. 928 * Same as for the txsync, this routine must be efficient. 929 * The caller guarantees a single invocations, but races against 930 * the rest of the driver should be handled here. 931 * 932 * On call, kring->rhead is the first packet that userspace wants 933 * to keep, and kring->rcur is the wakeup point. 934 * The kernel has previously reported packets up to kring->rtail. 935 * 936 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 937 * of whether or not we received an interrupt. 938 */ 939 static int 940 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 941 { 942 struct netmap_adapter *na = kring->na; 943 struct netmap_ring *ring = kring->ring; 944 uint32_t nm_i; /* index into the netmap ring */ 945 uint32_t nic_i, nic_i_start; /* index into the NIC ring */ 946 u_int i, n; 947 u_int const lim = kring->nkr_num_slots - 1; 948 u_int const head = kring->rhead; 949 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 950 struct if_rxd_info ri; 951 struct if_rxd_update iru; 952 953 struct ifnet *ifp = na->ifp; 954 if_ctx_t ctx = ifp->if_softc; 955 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 956 iflib_fl_t fl = rxq->ifr_fl; 957 if (head > lim) 958 return netmap_ring_reinit(kring); 959 960 /* XXX check sync modes */ 961 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 962 if (fl->ifl_sds.ifsd_map == NULL) 963 continue; 964 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 965 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 966 } 967 /* 968 * First part: import newly received packets. 969 * 970 * nm_i is the index of the next free slot in the netmap ring, 971 * nic_i is the index of the next received packet in the NIC ring, 972 * and they may differ in case if_init() has been called while 973 * in netmap mode. For the receive ring we have 974 * 975 * nic_i = rxr->next_check; 976 * nm_i = kring->nr_hwtail (previous) 977 * and 978 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 979 * 980 * rxr->next_check is set to 0 on a ring reinit 981 */ 982 if (netmap_no_pendintr || force_update) { 983 int crclen = iflib_crcstrip ? 0 : 4; 984 int error, avail; 985 uint16_t slot_flags = kring->nkr_slot_flags; 986 987 for (fl = rxq->ifr_fl, i = 0; i < rxq->ifr_nfl; i++, fl++) { 988 nic_i = fl->ifl_cidx; 989 nm_i = netmap_idx_n2k(kring, nic_i); 990 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 991 for (n = 0; avail > 0; n++, avail--) { 992 rxd_info_zero(&ri); 993 ri.iri_frags = rxq->ifr_frags; 994 ri.iri_qsidx = kring->ring_id; 995 ri.iri_ifp = ctx->ifc_ifp; 996 ri.iri_cidx = nic_i; 997 998 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 999 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1000 ring->slot[nm_i].flags = slot_flags; 1001 if (fl->ifl_sds.ifsd_map) 1002 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1003 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1004 nm_i = nm_next(nm_i, lim); 1005 nic_i = nm_next(nic_i, lim); 1006 } 1007 if (n) { /* update the state variables */ 1008 if (netmap_no_pendintr && !force_update) { 1009 /* diagnostics */ 1010 iflib_rx_miss ++; 1011 iflib_rx_miss_bufs += n; 1012 } 1013 fl->ifl_cidx = nic_i; 1014 kring->nr_hwtail = nm_i; 1015 } 1016 kring->nr_kflags &= ~NKR_PENDINTR; 1017 } 1018 } 1019 /* 1020 * Second part: skip past packets that userspace has released. 1021 * (kring->nr_hwcur to head excluded), 1022 * and make the buffers available for reception. 1023 * As usual nm_i is the index in the netmap ring, 1024 * nic_i is the index in the NIC ring, and 1025 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1026 */ 1027 /* XXX not sure how this will work with multiple free lists */ 1028 nm_i = kring->nr_hwcur; 1029 if (nm_i == head) 1030 return (0); 1031 1032 iru.iru_paddrs = fl->ifl_bus_addrs; 1033 iru.iru_vaddrs = &fl->ifl_vm_addrs[0]; 1034 iru.iru_idxs = fl->ifl_rxd_idxs; 1035 iru.iru_qsidx = rxq->ifr_id; 1036 iru.iru_buf_size = fl->ifl_buf_size; 1037 iru.iru_flidx = fl->ifl_id; 1038 nic_i_start = nic_i = netmap_idx_k2n(kring, nm_i); 1039 for (i = 0; nm_i != head; i++) { 1040 struct netmap_slot *slot = &ring->slot[nm_i]; 1041 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]); 1042 1043 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 1044 goto ring_reset; 1045 1046 fl->ifl_vm_addrs[i] = addr; 1047 if (fl->ifl_sds.ifsd_map && (slot->flags & NS_BUF_CHANGED)) { 1048 /* buffer has changed, reload map */ 1049 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i], addr); 1050 } 1051 slot->flags &= ~NS_BUF_CHANGED; 1052 1053 nm_i = nm_next(nm_i, lim); 1054 fl->ifl_rxd_idxs[i] = nic_i = nm_next(nic_i, lim); 1055 if (nm_i != head && i < IFLIB_MAX_RX_REFRESH) 1056 continue; 1057 1058 iru.iru_pidx = nic_i_start; 1059 iru.iru_count = i; 1060 i = 0; 1061 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1062 if (fl->ifl_sds.ifsd_map == NULL) { 1063 nic_i_start = nic_i; 1064 continue; 1065 } 1066 nic_i = nic_i_start; 1067 for (n = 0; n < iru.iru_count; n++) { 1068 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i], 1069 BUS_DMASYNC_PREREAD); 1070 nic_i = nm_next(nic_i, lim); 1071 } 1072 nic_i_start = nic_i; 1073 } 1074 kring->nr_hwcur = head; 1075 1076 if (fl->ifl_sds.ifsd_map) 1077 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1078 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1079 /* 1080 * IMPORTANT: we must leave one free slot in the ring, 1081 * so move nic_i back by one unit 1082 */ 1083 nic_i = nm_prev(nic_i, lim); 1084 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 1085 return 0; 1086 1087 ring_reset: 1088 return netmap_ring_reinit(kring); 1089 } 1090 1091 static void 1092 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1093 { 1094 struct ifnet *ifp = na->ifp; 1095 if_ctx_t ctx = ifp->if_softc; 1096 1097 CTX_LOCK(ctx); 1098 if (onoff) { 1099 IFDI_INTR_ENABLE(ctx); 1100 } else { 1101 IFDI_INTR_DISABLE(ctx); 1102 } 1103 CTX_UNLOCK(ctx); 1104 } 1105 1106 1107 static int 1108 iflib_netmap_attach(if_ctx_t ctx) 1109 { 1110 struct netmap_adapter na; 1111 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1112 1113 bzero(&na, sizeof(na)); 1114 1115 na.ifp = ctx->ifc_ifp; 1116 na.na_flags = NAF_BDG_MAYSLEEP; 1117 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1118 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1119 1120 na.num_tx_desc = scctx->isc_ntxd[0]; 1121 na.num_rx_desc = scctx->isc_nrxd[0]; 1122 na.nm_txsync = iflib_netmap_txsync; 1123 na.nm_rxsync = iflib_netmap_rxsync; 1124 na.nm_register = iflib_netmap_register; 1125 na.nm_intr = iflib_netmap_intr; 1126 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1127 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1128 return (netmap_attach(&na)); 1129 } 1130 1131 static void 1132 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1133 { 1134 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1135 struct netmap_slot *slot; 1136 1137 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1138 if (slot == NULL) 1139 return; 1140 if (txq->ift_sds.ifsd_map == NULL) 1141 return; 1142 1143 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1144 1145 /* 1146 * In netmap mode, set the map for the packet buffer. 1147 * NOTE: Some drivers (not this one) also need to set 1148 * the physical buffer address in the NIC ring. 1149 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1150 * netmap slot index, si 1151 */ 1152 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i); 1153 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1154 } 1155 } 1156 static void 1157 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1158 { 1159 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1160 struct netmap_slot *slot; 1161 struct if_rxd_update iru; 1162 iflib_fl_t fl; 1163 bus_dmamap_t *map; 1164 int nrxd; 1165 uint32_t i, j, pidx_start; 1166 1167 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1168 if (slot == NULL) 1169 return; 1170 fl = &rxq->ifr_fl[0]; 1171 map = fl->ifl_sds.ifsd_map; 1172 nrxd = ctx->ifc_softc_ctx.isc_nrxd[0]; 1173 iru.iru_paddrs = fl->ifl_bus_addrs; 1174 iru.iru_vaddrs = &fl->ifl_vm_addrs[0]; 1175 iru.iru_idxs = fl->ifl_rxd_idxs; 1176 iru.iru_qsidx = rxq->ifr_id; 1177 iru.iru_buf_size = rxq->ifr_fl[0].ifl_buf_size; 1178 iru.iru_flidx = 0; 1179 1180 for (pidx_start = i = j = 0; i < nrxd; i++, j++) { 1181 int sj = netmap_idx_n2k(&na->rx_rings[rxq->ifr_id], i); 1182 void *addr; 1183 1184 fl->ifl_rxd_idxs[j] = i; 1185 addr = fl->ifl_vm_addrs[j] = PNMB(na, slot + sj, &fl->ifl_bus_addrs[j]); 1186 if (map) { 1187 netmap_load_map(na, rxq->ifr_fl[0].ifl_ifdi->idi_tag, *map, addr); 1188 map++; 1189 } 1190 1191 if (j < IFLIB_MAX_RX_REFRESH && i < nrxd - 1) 1192 continue; 1193 1194 iru.iru_pidx = pidx_start; 1195 pidx_start = i; 1196 iru.iru_count = j; 1197 j = 0; 1198 MPASS(pidx_start + j <= nrxd); 1199 /* Update descriptors and the cached value */ 1200 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1201 } 1202 /* preserve queue */ 1203 if (ctx->ifc_ifp->if_capenable & IFCAP_NETMAP) { 1204 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id]; 1205 int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring); 1206 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, t); 1207 } else 1208 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, nrxd-1); 1209 } 1210 1211 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1212 1213 #else 1214 #define iflib_netmap_txq_init(ctx, txq) 1215 #define iflib_netmap_rxq_init(ctx, rxq) 1216 #define iflib_netmap_detach(ifp) 1217 1218 #define iflib_netmap_attach(ctx) (0) 1219 #define netmap_rx_irq(ifp, qid, budget) (0) 1220 #define netmap_tx_irq(ifp, qid) do {} while (0) 1221 1222 #endif 1223 1224 #if defined(__i386__) || defined(__amd64__) 1225 static __inline void 1226 prefetch(void *x) 1227 { 1228 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1229 } 1230 static __inline void 1231 prefetch2cachelines(void *x) 1232 { 1233 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1234 #if (CACHE_LINE_SIZE < 128) 1235 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1236 #endif 1237 } 1238 #else 1239 #define prefetch(x) 1240 #define prefetch2cachelines(x) 1241 #endif 1242 1243 static void 1244 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1245 { 1246 if (err) 1247 return; 1248 *(bus_addr_t *) arg = segs[0].ds_addr; 1249 } 1250 1251 int 1252 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1253 { 1254 int err; 1255 if_shared_ctx_t sctx = ctx->ifc_sctx; 1256 device_t dev = ctx->ifc_dev; 1257 1258 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1259 1260 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1261 sctx->isc_q_align, 0, /* alignment, bounds */ 1262 BUS_SPACE_MAXADDR, /* lowaddr */ 1263 BUS_SPACE_MAXADDR, /* highaddr */ 1264 NULL, NULL, /* filter, filterarg */ 1265 size, /* maxsize */ 1266 1, /* nsegments */ 1267 size, /* maxsegsize */ 1268 BUS_DMA_ALLOCNOW, /* flags */ 1269 NULL, /* lockfunc */ 1270 NULL, /* lockarg */ 1271 &dma->idi_tag); 1272 if (err) { 1273 device_printf(dev, 1274 "%s: bus_dma_tag_create failed: %d\n", 1275 __func__, err); 1276 goto fail_0; 1277 } 1278 1279 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1280 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1281 if (err) { 1282 device_printf(dev, 1283 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1284 __func__, (uintmax_t)size, err); 1285 goto fail_1; 1286 } 1287 1288 dma->idi_paddr = IF_BAD_DMA; 1289 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1290 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1291 if (err || dma->idi_paddr == IF_BAD_DMA) { 1292 device_printf(dev, 1293 "%s: bus_dmamap_load failed: %d\n", 1294 __func__, err); 1295 goto fail_2; 1296 } 1297 1298 dma->idi_size = size; 1299 return (0); 1300 1301 fail_2: 1302 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1303 fail_1: 1304 bus_dma_tag_destroy(dma->idi_tag); 1305 fail_0: 1306 dma->idi_tag = NULL; 1307 1308 return (err); 1309 } 1310 1311 int 1312 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1313 { 1314 int i, err; 1315 iflib_dma_info_t *dmaiter; 1316 1317 dmaiter = dmalist; 1318 for (i = 0; i < count; i++, dmaiter++) { 1319 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1320 break; 1321 } 1322 if (err) 1323 iflib_dma_free_multi(dmalist, i); 1324 return (err); 1325 } 1326 1327 void 1328 iflib_dma_free(iflib_dma_info_t dma) 1329 { 1330 if (dma->idi_tag == NULL) 1331 return; 1332 if (dma->idi_paddr != IF_BAD_DMA) { 1333 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1334 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1335 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1336 dma->idi_paddr = IF_BAD_DMA; 1337 } 1338 if (dma->idi_vaddr != NULL) { 1339 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1340 dma->idi_vaddr = NULL; 1341 } 1342 bus_dma_tag_destroy(dma->idi_tag); 1343 dma->idi_tag = NULL; 1344 } 1345 1346 void 1347 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1348 { 1349 int i; 1350 iflib_dma_info_t *dmaiter = dmalist; 1351 1352 for (i = 0; i < count; i++, dmaiter++) 1353 iflib_dma_free(*dmaiter); 1354 } 1355 1356 #ifdef EARLY_AP_STARTUP 1357 static const int iflib_started = 1; 1358 #else 1359 /* 1360 * We used to abuse the smp_started flag to decide if the queues have been 1361 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1362 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1363 * is set. Run a SYSINIT() strictly after that to just set a usable 1364 * completion flag. 1365 */ 1366 1367 static int iflib_started; 1368 1369 static void 1370 iflib_record_started(void *arg) 1371 { 1372 iflib_started = 1; 1373 } 1374 1375 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1376 iflib_record_started, NULL); 1377 #endif 1378 1379 static int 1380 iflib_fast_intr(void *arg) 1381 { 1382 iflib_filter_info_t info = arg; 1383 struct grouptask *gtask = info->ifi_task; 1384 if (!iflib_started) 1385 return (FILTER_HANDLED); 1386 1387 DBG_COUNTER_INC(fast_intrs); 1388 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1389 return (FILTER_HANDLED); 1390 1391 GROUPTASK_ENQUEUE(gtask); 1392 return (FILTER_HANDLED); 1393 } 1394 1395 static int 1396 iflib_fast_intr_rxtx(void *arg) 1397 { 1398 iflib_filter_info_t info = arg; 1399 struct grouptask *gtask = info->ifi_task; 1400 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1401 if_ctx_t ctx; 1402 int i, cidx; 1403 1404 if (!iflib_started) 1405 return (FILTER_HANDLED); 1406 1407 DBG_COUNTER_INC(fast_intrs); 1408 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1409 return (FILTER_HANDLED); 1410 1411 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1412 qidx_t txqid = rxq->ifr_txqid[i]; 1413 1414 ctx = rxq->ifr_ctx; 1415 1416 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1417 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1418 continue; 1419 } 1420 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1421 } 1422 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1423 cidx = rxq->ifr_cq_cidx; 1424 else 1425 cidx = rxq->ifr_fl[0].ifl_cidx; 1426 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1427 GROUPTASK_ENQUEUE(gtask); 1428 else 1429 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1430 return (FILTER_HANDLED); 1431 } 1432 1433 1434 static int 1435 iflib_fast_intr_ctx(void *arg) 1436 { 1437 iflib_filter_info_t info = arg; 1438 struct grouptask *gtask = info->ifi_task; 1439 1440 if (!iflib_started) 1441 return (FILTER_HANDLED); 1442 1443 DBG_COUNTER_INC(fast_intrs); 1444 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1445 return (FILTER_HANDLED); 1446 1447 GROUPTASK_ENQUEUE(gtask); 1448 return (FILTER_HANDLED); 1449 } 1450 1451 static int 1452 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1453 driver_filter_t filter, driver_intr_t handler, void *arg, 1454 char *name) 1455 { 1456 int rc, flags; 1457 struct resource *res; 1458 void *tag = NULL; 1459 device_t dev = ctx->ifc_dev; 1460 1461 flags = RF_ACTIVE; 1462 if (ctx->ifc_flags & IFC_LEGACY) 1463 flags |= RF_SHAREABLE; 1464 MPASS(rid < 512); 1465 irq->ii_rid = rid; 1466 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1467 if (res == NULL) { 1468 device_printf(dev, 1469 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1470 return (ENOMEM); 1471 } 1472 irq->ii_res = res; 1473 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1474 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1475 filter, handler, arg, &tag); 1476 if (rc != 0) { 1477 device_printf(dev, 1478 "failed to setup interrupt for rid %d, name %s: %d\n", 1479 rid, name ? name : "unknown", rc); 1480 return (rc); 1481 } else if (name) 1482 bus_describe_intr(dev, res, tag, "%s", name); 1483 1484 irq->ii_tag = tag; 1485 return (0); 1486 } 1487 1488 1489 /********************************************************************* 1490 * 1491 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1492 * the information needed to transmit a packet on the wire. This is 1493 * called only once at attach, setup is done every reset. 1494 * 1495 **********************************************************************/ 1496 1497 static int 1498 iflib_txsd_alloc(iflib_txq_t txq) 1499 { 1500 if_ctx_t ctx = txq->ift_ctx; 1501 if_shared_ctx_t sctx = ctx->ifc_sctx; 1502 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1503 device_t dev = ctx->ifc_dev; 1504 int err, nsegments, ntsosegments; 1505 1506 nsegments = scctx->isc_tx_nsegments; 1507 ntsosegments = scctx->isc_tx_tso_segments_max; 1508 MPASS(scctx->isc_ntxd[0] > 0); 1509 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1510 MPASS(nsegments > 0); 1511 MPASS(ntsosegments > 0); 1512 /* 1513 * Setup DMA descriptor areas. 1514 */ 1515 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1516 1, 0, /* alignment, bounds */ 1517 BUS_SPACE_MAXADDR, /* lowaddr */ 1518 BUS_SPACE_MAXADDR, /* highaddr */ 1519 NULL, NULL, /* filter, filterarg */ 1520 sctx->isc_tx_maxsize, /* maxsize */ 1521 nsegments, /* nsegments */ 1522 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1523 0, /* flags */ 1524 NULL, /* lockfunc */ 1525 NULL, /* lockfuncarg */ 1526 &txq->ift_desc_tag))) { 1527 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1528 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1529 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1530 goto fail; 1531 } 1532 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1533 1, 0, /* alignment, bounds */ 1534 BUS_SPACE_MAXADDR, /* lowaddr */ 1535 BUS_SPACE_MAXADDR, /* highaddr */ 1536 NULL, NULL, /* filter, filterarg */ 1537 scctx->isc_tx_tso_size_max, /* maxsize */ 1538 ntsosegments, /* nsegments */ 1539 scctx->isc_tx_tso_segsize_max, /* maxsegsize */ 1540 0, /* flags */ 1541 NULL, /* lockfunc */ 1542 NULL, /* lockfuncarg */ 1543 &txq->ift_tso_desc_tag))) { 1544 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1545 1546 goto fail; 1547 } 1548 if (!(txq->ift_sds.ifsd_flags = 1549 (uint8_t *) malloc(sizeof(uint8_t) * 1550 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1551 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1552 err = ENOMEM; 1553 goto fail; 1554 } 1555 if (!(txq->ift_sds.ifsd_m = 1556 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1557 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1558 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1559 err = ENOMEM; 1560 goto fail; 1561 } 1562 1563 /* Create the descriptor buffer dma maps */ 1564 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1565 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1566 return (0); 1567 1568 if (!(txq->ift_sds.ifsd_map = 1569 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1570 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1571 err = ENOMEM; 1572 goto fail; 1573 } 1574 1575 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1576 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1577 if (err != 0) { 1578 device_printf(dev, "Unable to create TX DMA map\n"); 1579 goto fail; 1580 } 1581 } 1582 #endif 1583 return (0); 1584 fail: 1585 /* We free all, it handles case where we are in the middle */ 1586 iflib_tx_structures_free(ctx); 1587 return (err); 1588 } 1589 1590 static void 1591 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1592 { 1593 bus_dmamap_t map; 1594 1595 map = NULL; 1596 if (txq->ift_sds.ifsd_map != NULL) 1597 map = txq->ift_sds.ifsd_map[i]; 1598 if (map != NULL) { 1599 bus_dmamap_unload(txq->ift_desc_tag, map); 1600 bus_dmamap_destroy(txq->ift_desc_tag, map); 1601 txq->ift_sds.ifsd_map[i] = NULL; 1602 } 1603 } 1604 1605 static void 1606 iflib_txq_destroy(iflib_txq_t txq) 1607 { 1608 if_ctx_t ctx = txq->ift_ctx; 1609 1610 for (int i = 0; i < txq->ift_size; i++) 1611 iflib_txsd_destroy(ctx, txq, i); 1612 if (txq->ift_sds.ifsd_map != NULL) { 1613 free(txq->ift_sds.ifsd_map, M_IFLIB); 1614 txq->ift_sds.ifsd_map = NULL; 1615 } 1616 if (txq->ift_sds.ifsd_m != NULL) { 1617 free(txq->ift_sds.ifsd_m, M_IFLIB); 1618 txq->ift_sds.ifsd_m = NULL; 1619 } 1620 if (txq->ift_sds.ifsd_flags != NULL) { 1621 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1622 txq->ift_sds.ifsd_flags = NULL; 1623 } 1624 if (txq->ift_desc_tag != NULL) { 1625 bus_dma_tag_destroy(txq->ift_desc_tag); 1626 txq->ift_desc_tag = NULL; 1627 } 1628 if (txq->ift_tso_desc_tag != NULL) { 1629 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1630 txq->ift_tso_desc_tag = NULL; 1631 } 1632 } 1633 1634 static void 1635 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1636 { 1637 struct mbuf **mp; 1638 1639 mp = &txq->ift_sds.ifsd_m[i]; 1640 if (*mp == NULL) 1641 return; 1642 1643 if (txq->ift_sds.ifsd_map != NULL) { 1644 bus_dmamap_sync(txq->ift_desc_tag, 1645 txq->ift_sds.ifsd_map[i], 1646 BUS_DMASYNC_POSTWRITE); 1647 bus_dmamap_unload(txq->ift_desc_tag, 1648 txq->ift_sds.ifsd_map[i]); 1649 } 1650 m_free(*mp); 1651 DBG_COUNTER_INC(tx_frees); 1652 *mp = NULL; 1653 } 1654 1655 static int 1656 iflib_txq_setup(iflib_txq_t txq) 1657 { 1658 if_ctx_t ctx = txq->ift_ctx; 1659 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1660 iflib_dma_info_t di; 1661 int i; 1662 1663 /* Set number of descriptors available */ 1664 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1665 /* XXX make configurable */ 1666 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1667 1668 /* Reset indices */ 1669 txq->ift_cidx_processed = 0; 1670 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1671 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1672 1673 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1674 bzero((void *)di->idi_vaddr, di->idi_size); 1675 1676 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1677 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1678 bus_dmamap_sync(di->idi_tag, di->idi_map, 1679 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1680 return (0); 1681 } 1682 1683 /********************************************************************* 1684 * 1685 * Allocate memory for rx_buffer structures. Since we use one 1686 * rx_buffer per received packet, the maximum number of rx_buffer's 1687 * that we'll need is equal to the number of receive descriptors 1688 * that we've allocated. 1689 * 1690 **********************************************************************/ 1691 static int 1692 iflib_rxsd_alloc(iflib_rxq_t rxq) 1693 { 1694 if_ctx_t ctx = rxq->ifr_ctx; 1695 if_shared_ctx_t sctx = ctx->ifc_sctx; 1696 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1697 device_t dev = ctx->ifc_dev; 1698 iflib_fl_t fl; 1699 int err; 1700 1701 MPASS(scctx->isc_nrxd[0] > 0); 1702 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1703 1704 fl = rxq->ifr_fl; 1705 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1706 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1707 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1708 1, 0, /* alignment, bounds */ 1709 BUS_SPACE_MAXADDR, /* lowaddr */ 1710 BUS_SPACE_MAXADDR, /* highaddr */ 1711 NULL, NULL, /* filter, filterarg */ 1712 sctx->isc_rx_maxsize, /* maxsize */ 1713 sctx->isc_rx_nsegments, /* nsegments */ 1714 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1715 0, /* flags */ 1716 NULL, /* lockfunc */ 1717 NULL, /* lockarg */ 1718 &fl->ifl_desc_tag); 1719 if (err) { 1720 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1721 __func__, err); 1722 goto fail; 1723 } 1724 if (!(fl->ifl_sds.ifsd_flags = 1725 (uint8_t *) malloc(sizeof(uint8_t) * 1726 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1727 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1728 err = ENOMEM; 1729 goto fail; 1730 } 1731 if (!(fl->ifl_sds.ifsd_m = 1732 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1733 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1734 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1735 err = ENOMEM; 1736 goto fail; 1737 } 1738 if (!(fl->ifl_sds.ifsd_cl = 1739 (caddr_t *) malloc(sizeof(caddr_t) * 1740 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1741 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1742 err = ENOMEM; 1743 goto fail; 1744 } 1745 1746 /* Create the descriptor buffer dma maps */ 1747 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1748 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1749 continue; 1750 1751 if (!(fl->ifl_sds.ifsd_map = 1752 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1753 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1754 err = ENOMEM; 1755 goto fail; 1756 } 1757 1758 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1759 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1760 if (err != 0) { 1761 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1762 goto fail; 1763 } 1764 } 1765 #endif 1766 } 1767 return (0); 1768 1769 fail: 1770 iflib_rx_structures_free(ctx); 1771 return (err); 1772 } 1773 1774 1775 /* 1776 * Internal service routines 1777 */ 1778 1779 struct rxq_refill_cb_arg { 1780 int error; 1781 bus_dma_segment_t seg; 1782 int nseg; 1783 }; 1784 1785 static void 1786 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1787 { 1788 struct rxq_refill_cb_arg *cb_arg = arg; 1789 1790 cb_arg->error = error; 1791 cb_arg->seg = segs[0]; 1792 cb_arg->nseg = nseg; 1793 } 1794 1795 1796 #ifdef ACPI_DMAR 1797 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1798 #else 1799 #define IS_DMAR(ctx) (0) 1800 #endif 1801 1802 /** 1803 * rxq_refill - refill an rxq free-buffer list 1804 * @ctx: the iflib context 1805 * @rxq: the free-list to refill 1806 * @n: the number of new buffers to allocate 1807 * 1808 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1809 * The caller must assure that @n does not exceed the queue's capacity. 1810 */ 1811 static void 1812 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1813 { 1814 struct mbuf *m; 1815 int idx, frag_idx = fl->ifl_fragidx; 1816 int pidx = fl->ifl_pidx; 1817 caddr_t cl, *sd_cl; 1818 struct mbuf **sd_m; 1819 uint8_t *sd_flags; 1820 struct if_rxd_update iru; 1821 bus_dmamap_t *sd_map; 1822 int n, i = 0; 1823 uint64_t bus_addr; 1824 int err; 1825 1826 sd_m = fl->ifl_sds.ifsd_m; 1827 sd_map = fl->ifl_sds.ifsd_map; 1828 sd_cl = fl->ifl_sds.ifsd_cl; 1829 sd_flags = fl->ifl_sds.ifsd_flags; 1830 idx = pidx; 1831 1832 n = count; 1833 MPASS(n > 0); 1834 MPASS(fl->ifl_credits + n <= fl->ifl_size); 1835 1836 if (pidx < fl->ifl_cidx) 1837 MPASS(pidx + n <= fl->ifl_cidx); 1838 if (pidx == fl->ifl_cidx && (fl->ifl_credits < fl->ifl_size)) 1839 MPASS(fl->ifl_gen == 0); 1840 if (pidx > fl->ifl_cidx) 1841 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1842 1843 DBG_COUNTER_INC(fl_refills); 1844 if (n > 8) 1845 DBG_COUNTER_INC(fl_refills_large); 1846 iru.iru_paddrs = fl->ifl_bus_addrs; 1847 iru.iru_vaddrs = &fl->ifl_vm_addrs[0]; 1848 iru.iru_idxs = fl->ifl_rxd_idxs; 1849 iru.iru_qsidx = fl->ifl_rxq->ifr_id; 1850 iru.iru_buf_size = fl->ifl_buf_size; 1851 iru.iru_flidx = fl->ifl_id; 1852 while (n--) { 1853 /* 1854 * We allocate an uninitialized mbuf + cluster, mbuf is 1855 * initialized after rx. 1856 * 1857 * If the cluster is still set then we know a minimum sized packet was received 1858 */ 1859 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1860 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1861 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1862 if ((cl = sd_cl[frag_idx]) == NULL) { 1863 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1864 break; 1865 #if MEMORY_LOGGING 1866 fl->ifl_cl_enqueued++; 1867 #endif 1868 } 1869 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1870 break; 1871 } 1872 #if MEMORY_LOGGING 1873 fl->ifl_m_enqueued++; 1874 #endif 1875 1876 DBG_COUNTER_INC(rx_allocs); 1877 #if defined(__i386__) || defined(__amd64__) 1878 if (!IS_DMAR(ctx)) { 1879 bus_addr = pmap_kextract((vm_offset_t)cl); 1880 } else 1881 #endif 1882 { 1883 struct rxq_refill_cb_arg cb_arg; 1884 iflib_rxq_t q; 1885 1886 cb_arg.error = 0; 1887 q = fl->ifl_rxq; 1888 MPASS(sd_map != NULL); 1889 MPASS(sd_map[frag_idx] != NULL); 1890 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1891 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1892 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 1893 BUS_DMASYNC_PREREAD); 1894 1895 if (err != 0 || cb_arg.error) { 1896 /* 1897 * !zone_pack ? 1898 */ 1899 if (fl->ifl_zone == zone_pack) 1900 uma_zfree(fl->ifl_zone, cl); 1901 m_free(m); 1902 n = 0; 1903 goto done; 1904 } 1905 bus_addr = cb_arg.seg.ds_addr; 1906 } 1907 bit_set(fl->ifl_rx_bitmap, frag_idx); 1908 sd_flags[frag_idx] |= RX_SW_DESC_INUSE; 1909 1910 MPASS(sd_m[frag_idx] == NULL); 1911 sd_cl[frag_idx] = cl; 1912 sd_m[frag_idx] = m; 1913 fl->ifl_rxd_idxs[i] = frag_idx; 1914 fl->ifl_bus_addrs[i] = bus_addr; 1915 fl->ifl_vm_addrs[i] = cl; 1916 fl->ifl_credits++; 1917 i++; 1918 MPASS(fl->ifl_credits <= fl->ifl_size); 1919 if (++idx == fl->ifl_size) { 1920 fl->ifl_gen = 1; 1921 idx = 0; 1922 } 1923 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 1924 iru.iru_pidx = pidx; 1925 iru.iru_count = i; 1926 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1927 i = 0; 1928 pidx = idx; 1929 fl->ifl_pidx = idx; 1930 } 1931 1932 } 1933 done: 1934 DBG_COUNTER_INC(rxd_flush); 1935 if (fl->ifl_pidx == 0) 1936 pidx = fl->ifl_size - 1; 1937 else 1938 pidx = fl->ifl_pidx - 1; 1939 1940 if (sd_map) 1941 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1942 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1943 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 1944 fl->ifl_fragidx = frag_idx; 1945 } 1946 1947 static __inline void 1948 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 1949 { 1950 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 1951 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 1952 #ifdef INVARIANTS 1953 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 1954 #endif 1955 1956 MPASS(fl->ifl_credits <= fl->ifl_size); 1957 MPASS(reclaimable == delta); 1958 1959 if (reclaimable > 0) 1960 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 1961 } 1962 1963 static void 1964 iflib_fl_bufs_free(iflib_fl_t fl) 1965 { 1966 iflib_dma_info_t idi = fl->ifl_ifdi; 1967 uint32_t i; 1968 1969 for (i = 0; i < fl->ifl_size; i++) { 1970 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 1971 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 1972 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 1973 1974 if (*sd_flags & RX_SW_DESC_INUSE) { 1975 if (fl->ifl_sds.ifsd_map != NULL) { 1976 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 1977 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 1978 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 1979 } 1980 if (*sd_m != NULL) { 1981 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 1982 uma_zfree(zone_mbuf, *sd_m); 1983 } 1984 if (*sd_cl != NULL) 1985 uma_zfree(fl->ifl_zone, *sd_cl); 1986 *sd_flags = 0; 1987 } else { 1988 MPASS(*sd_cl == NULL); 1989 MPASS(*sd_m == NULL); 1990 } 1991 #if MEMORY_LOGGING 1992 fl->ifl_m_dequeued++; 1993 fl->ifl_cl_dequeued++; 1994 #endif 1995 *sd_cl = NULL; 1996 *sd_m = NULL; 1997 } 1998 #ifdef INVARIANTS 1999 for (i = 0; i < fl->ifl_size; i++) { 2000 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 2001 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2002 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2003 } 2004 #endif 2005 /* 2006 * Reset free list values 2007 */ 2008 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2009 bzero(idi->idi_vaddr, idi->idi_size); 2010 } 2011 2012 /********************************************************************* 2013 * 2014 * Initialize a receive ring and its buffers. 2015 * 2016 **********************************************************************/ 2017 static int 2018 iflib_fl_setup(iflib_fl_t fl) 2019 { 2020 iflib_rxq_t rxq = fl->ifl_rxq; 2021 if_ctx_t ctx = rxq->ifr_ctx; 2022 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2023 2024 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size); 2025 /* 2026 ** Free current RX buffer structs and their mbufs 2027 */ 2028 iflib_fl_bufs_free(fl); 2029 /* Now replenish the mbufs */ 2030 MPASS(fl->ifl_credits == 0); 2031 /* 2032 * XXX don't set the max_frame_size to larger 2033 * than the hardware can handle 2034 */ 2035 if (sctx->isc_max_frame_size <= 2048) 2036 fl->ifl_buf_size = MCLBYTES; 2037 #ifndef CONTIGMALLOC_WORKS 2038 else 2039 fl->ifl_buf_size = MJUMPAGESIZE; 2040 #else 2041 else if (sctx->isc_max_frame_size <= 4096) 2042 fl->ifl_buf_size = MJUMPAGESIZE; 2043 else if (sctx->isc_max_frame_size <= 9216) 2044 fl->ifl_buf_size = MJUM9BYTES; 2045 else 2046 fl->ifl_buf_size = MJUM16BYTES; 2047 #endif 2048 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2049 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2050 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2051 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2052 2053 2054 /* avoid pre-allocating zillions of clusters to an idle card 2055 * potentially speeding up attach 2056 */ 2057 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2058 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2059 if (min(128, fl->ifl_size) != fl->ifl_credits) 2060 return (ENOBUFS); 2061 /* 2062 * handle failure 2063 */ 2064 MPASS(rxq != NULL); 2065 MPASS(fl->ifl_ifdi != NULL); 2066 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2067 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2068 return (0); 2069 } 2070 2071 /********************************************************************* 2072 * 2073 * Free receive ring data structures 2074 * 2075 **********************************************************************/ 2076 static void 2077 iflib_rx_sds_free(iflib_rxq_t rxq) 2078 { 2079 iflib_fl_t fl; 2080 int i; 2081 2082 if (rxq->ifr_fl != NULL) { 2083 for (i = 0; i < rxq->ifr_nfl; i++) { 2084 fl = &rxq->ifr_fl[i]; 2085 if (fl->ifl_desc_tag != NULL) { 2086 bus_dma_tag_destroy(fl->ifl_desc_tag); 2087 fl->ifl_desc_tag = NULL; 2088 } 2089 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2090 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2091 /* XXX destroy maps first */ 2092 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2093 fl->ifl_sds.ifsd_m = NULL; 2094 fl->ifl_sds.ifsd_cl = NULL; 2095 fl->ifl_sds.ifsd_map = NULL; 2096 } 2097 free(rxq->ifr_fl, M_IFLIB); 2098 rxq->ifr_fl = NULL; 2099 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2100 } 2101 } 2102 2103 /* 2104 * MI independent logic 2105 * 2106 */ 2107 static void 2108 iflib_timer(void *arg) 2109 { 2110 iflib_txq_t txq = arg; 2111 if_ctx_t ctx = txq->ift_ctx; 2112 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2113 2114 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2115 return; 2116 /* 2117 ** Check on the state of the TX queue(s), this 2118 ** can be done without the lock because its RO 2119 ** and the HUNG state will be static if set. 2120 */ 2121 IFDI_TIMER(ctx, txq->ift_id); 2122 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2123 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2124 (sctx->isc_pause_frames == 0))) 2125 goto hung; 2126 2127 if (ifmp_ring_is_stalled(txq->ift_br)) 2128 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2129 txq->ift_cleaned_prev = txq->ift_cleaned; 2130 /* handle any laggards */ 2131 if (txq->ift_db_pending) 2132 GROUPTASK_ENQUEUE(&txq->ift_task); 2133 2134 sctx->isc_pause_frames = 0; 2135 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2136 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 2137 return; 2138 hung: 2139 CTX_LOCK(ctx); 2140 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2141 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2142 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2143 2144 IFDI_WATCHDOG_RESET(ctx); 2145 ctx->ifc_watchdog_events++; 2146 2147 ctx->ifc_flags |= IFC_DO_RESET; 2148 iflib_admin_intr_deferred(ctx); 2149 CTX_UNLOCK(ctx); 2150 } 2151 2152 static void 2153 iflib_init_locked(if_ctx_t ctx) 2154 { 2155 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2156 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2157 if_t ifp = ctx->ifc_ifp; 2158 iflib_fl_t fl; 2159 iflib_txq_t txq; 2160 iflib_rxq_t rxq; 2161 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2162 2163 2164 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2165 IFDI_INTR_DISABLE(ctx); 2166 2167 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2168 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2169 /* Set hardware offload abilities */ 2170 if_clearhwassist(ifp); 2171 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2172 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2173 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2174 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2175 if (if_getcapenable(ifp) & IFCAP_TSO4) 2176 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2177 if (if_getcapenable(ifp) & IFCAP_TSO6) 2178 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2179 2180 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2181 CALLOUT_LOCK(txq); 2182 callout_stop(&txq->ift_timer); 2183 CALLOUT_UNLOCK(txq); 2184 iflib_netmap_txq_init(ctx, txq); 2185 } 2186 #ifdef INVARIANTS 2187 i = if_getdrvflags(ifp); 2188 #endif 2189 IFDI_INIT(ctx); 2190 MPASS(if_getdrvflags(ifp) == i); 2191 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2192 /* XXX this should really be done on a per-queue basis */ 2193 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2194 MPASS(rxq->ifr_id == i); 2195 iflib_netmap_rxq_init(ctx, rxq); 2196 continue; 2197 } 2198 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2199 if (iflib_fl_setup(fl)) { 2200 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2201 goto done; 2202 } 2203 } 2204 } 2205 done: 2206 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2207 IFDI_INTR_ENABLE(ctx); 2208 txq = ctx->ifc_txqs; 2209 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2210 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2211 txq->ift_timer.c_cpu); 2212 } 2213 2214 static int 2215 iflib_media_change(if_t ifp) 2216 { 2217 if_ctx_t ctx = if_getsoftc(ifp); 2218 int err; 2219 2220 CTX_LOCK(ctx); 2221 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2222 iflib_init_locked(ctx); 2223 CTX_UNLOCK(ctx); 2224 return (err); 2225 } 2226 2227 static void 2228 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2229 { 2230 if_ctx_t ctx = if_getsoftc(ifp); 2231 2232 CTX_LOCK(ctx); 2233 IFDI_UPDATE_ADMIN_STATUS(ctx); 2234 IFDI_MEDIA_STATUS(ctx, ifmr); 2235 CTX_UNLOCK(ctx); 2236 } 2237 2238 static void 2239 iflib_stop(if_ctx_t ctx) 2240 { 2241 iflib_txq_t txq = ctx->ifc_txqs; 2242 iflib_rxq_t rxq = ctx->ifc_rxqs; 2243 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2244 iflib_dma_info_t di; 2245 iflib_fl_t fl; 2246 int i, j; 2247 2248 /* Tell the stack that the interface is no longer active */ 2249 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2250 2251 IFDI_INTR_DISABLE(ctx); 2252 DELAY(1000); 2253 IFDI_STOP(ctx); 2254 DELAY(1000); 2255 2256 iflib_debug_reset(); 2257 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2258 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2259 /* make sure all transmitters have completed before proceeding XXX */ 2260 2261 /* clean any enqueued buffers */ 2262 iflib_ifmp_purge(txq); 2263 /* Free any existing tx buffers. */ 2264 for (j = 0; j < txq->ift_size; j++) { 2265 iflib_txsd_free(ctx, txq, j); 2266 } 2267 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2268 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2269 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2270 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2271 txq->ift_pullups = 0; 2272 ifmp_ring_reset_stats(txq->ift_br); 2273 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2274 bzero((void *)di->idi_vaddr, di->idi_size); 2275 } 2276 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2277 /* make sure all transmitters have completed before proceeding XXX */ 2278 2279 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++) 2280 bzero((void *)di->idi_vaddr, di->idi_size); 2281 /* also resets the free lists pidx/cidx */ 2282 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2283 iflib_fl_bufs_free(fl); 2284 } 2285 } 2286 2287 static inline caddr_t 2288 calc_next_rxd(iflib_fl_t fl, int cidx) 2289 { 2290 qidx_t size; 2291 int nrxd; 2292 caddr_t start, end, cur, next; 2293 2294 nrxd = fl->ifl_size; 2295 size = fl->ifl_rxd_size; 2296 start = fl->ifl_ifdi->idi_vaddr; 2297 2298 if (__predict_false(size == 0)) 2299 return (start); 2300 cur = start + size*cidx; 2301 end = start + size*nrxd; 2302 next = CACHE_PTR_NEXT(cur); 2303 return (next < end ? next : start); 2304 } 2305 2306 static inline void 2307 prefetch_pkts(iflib_fl_t fl, int cidx) 2308 { 2309 int nextptr; 2310 int nrxd = fl->ifl_size; 2311 caddr_t next_rxd; 2312 2313 2314 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2315 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2316 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2317 next_rxd = calc_next_rxd(fl, cidx); 2318 prefetch(next_rxd); 2319 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2320 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2321 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2322 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2323 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2324 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2325 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2326 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2327 } 2328 2329 static void 2330 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2331 { 2332 int flid, cidx; 2333 bus_dmamap_t map; 2334 iflib_fl_t fl; 2335 iflib_dma_info_t di; 2336 int next; 2337 2338 map = NULL; 2339 flid = irf->irf_flid; 2340 cidx = irf->irf_idx; 2341 fl = &rxq->ifr_fl[flid]; 2342 sd->ifsd_fl = fl; 2343 sd->ifsd_cidx = cidx; 2344 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2345 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2346 fl->ifl_credits--; 2347 #if MEMORY_LOGGING 2348 fl->ifl_m_dequeued++; 2349 #endif 2350 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2351 prefetch_pkts(fl, cidx); 2352 if (fl->ifl_sds.ifsd_map != NULL) { 2353 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2354 prefetch(&fl->ifl_sds.ifsd_map[next]); 2355 map = fl->ifl_sds.ifsd_map[cidx]; 2356 di = fl->ifl_ifdi; 2357 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2358 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2359 bus_dmamap_sync(di->idi_tag, di->idi_map, 2360 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2361 2362 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2363 MPASS(fl->ifl_cidx == cidx); 2364 if (unload) 2365 bus_dmamap_unload(fl->ifl_desc_tag, map); 2366 } 2367 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2368 if (__predict_false(fl->ifl_cidx == 0)) 2369 fl->ifl_gen = 0; 2370 if (map != NULL) 2371 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2372 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2373 bit_clear(fl->ifl_rx_bitmap, cidx); 2374 } 2375 2376 static struct mbuf * 2377 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2378 { 2379 int i, padlen , flags; 2380 struct mbuf *m, *mh, *mt; 2381 caddr_t cl; 2382 2383 i = 0; 2384 mh = NULL; 2385 do { 2386 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2387 2388 MPASS(*sd->ifsd_cl != NULL); 2389 MPASS(*sd->ifsd_m != NULL); 2390 2391 /* Don't include zero-length frags */ 2392 if (ri->iri_frags[i].irf_len == 0) { 2393 /* XXX we can save the cluster here, but not the mbuf */ 2394 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2395 m_free(*sd->ifsd_m); 2396 *sd->ifsd_m = NULL; 2397 continue; 2398 } 2399 m = *sd->ifsd_m; 2400 *sd->ifsd_m = NULL; 2401 if (mh == NULL) { 2402 flags = M_PKTHDR|M_EXT; 2403 mh = mt = m; 2404 padlen = ri->iri_pad; 2405 } else { 2406 flags = M_EXT; 2407 mt->m_next = m; 2408 mt = m; 2409 /* assuming padding is only on the first fragment */ 2410 padlen = 0; 2411 } 2412 cl = *sd->ifsd_cl; 2413 *sd->ifsd_cl = NULL; 2414 2415 /* Can these two be made one ? */ 2416 m_init(m, M_NOWAIT, MT_DATA, flags); 2417 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2418 /* 2419 * These must follow m_init and m_cljset 2420 */ 2421 m->m_data += padlen; 2422 ri->iri_len -= padlen; 2423 m->m_len = ri->iri_frags[i].irf_len; 2424 } while (++i < ri->iri_nfrags); 2425 2426 return (mh); 2427 } 2428 2429 /* 2430 * Process one software descriptor 2431 */ 2432 static struct mbuf * 2433 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2434 { 2435 struct if_rxsd sd; 2436 struct mbuf *m; 2437 2438 /* should I merge this back in now that the two paths are basically duplicated? */ 2439 if (ri->iri_nfrags == 1 && 2440 ri->iri_frags[0].irf_len <= IFLIB_RX_COPY_THRESH) { 2441 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2442 m = *sd.ifsd_m; 2443 *sd.ifsd_m = NULL; 2444 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2445 #ifndef __NO_STRICT_ALIGNMENT 2446 if (!IP_ALIGNED(m)) 2447 m->m_data += 2; 2448 #endif 2449 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2450 m->m_len = ri->iri_frags[0].irf_len; 2451 } else { 2452 m = assemble_segments(rxq, ri, &sd); 2453 } 2454 m->m_pkthdr.len = ri->iri_len; 2455 m->m_pkthdr.rcvif = ri->iri_ifp; 2456 m->m_flags |= ri->iri_flags; 2457 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2458 m->m_pkthdr.flowid = ri->iri_flowid; 2459 M_HASHTYPE_SET(m, ri->iri_rsstype); 2460 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2461 m->m_pkthdr.csum_data = ri->iri_csum_data; 2462 return (m); 2463 } 2464 2465 static bool 2466 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2467 { 2468 if_ctx_t ctx = rxq->ifr_ctx; 2469 if_shared_ctx_t sctx = ctx->ifc_sctx; 2470 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2471 int avail, i; 2472 qidx_t *cidxp; 2473 struct if_rxd_info ri; 2474 int err, budget_left, rx_bytes, rx_pkts; 2475 iflib_fl_t fl; 2476 struct ifnet *ifp; 2477 int lro_enabled; 2478 2479 /* 2480 * XXX early demux data packets so that if_input processing only handles 2481 * acks in interrupt context 2482 */ 2483 struct mbuf *m, *mh, *mt, *mf; 2484 2485 ifp = ctx->ifc_ifp; 2486 mh = mt = NULL; 2487 MPASS(budget > 0); 2488 rx_pkts = rx_bytes = 0; 2489 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2490 cidxp = &rxq->ifr_cq_cidx; 2491 else 2492 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2493 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2494 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2495 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2496 DBG_COUNTER_INC(rx_unavail); 2497 return (false); 2498 } 2499 2500 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2501 if (__predict_false(!CTX_ACTIVE(ctx))) { 2502 DBG_COUNTER_INC(rx_ctx_inactive); 2503 break; 2504 } 2505 /* 2506 * Reset client set fields to their default values 2507 */ 2508 rxd_info_zero(&ri); 2509 ri.iri_qsidx = rxq->ifr_id; 2510 ri.iri_cidx = *cidxp; 2511 ri.iri_ifp = ifp; 2512 ri.iri_frags = rxq->ifr_frags; 2513 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2514 2515 if (err) 2516 goto err; 2517 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2518 *cidxp = ri.iri_cidx; 2519 /* Update our consumer index */ 2520 /* XXX NB: shurd - check if this is still safe */ 2521 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2522 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2523 rxq->ifr_cq_gen = 0; 2524 } 2525 /* was this only a completion queue message? */ 2526 if (__predict_false(ri.iri_nfrags == 0)) 2527 continue; 2528 } 2529 MPASS(ri.iri_nfrags != 0); 2530 MPASS(ri.iri_len != 0); 2531 2532 /* will advance the cidx on the corresponding free lists */ 2533 m = iflib_rxd_pkt_get(rxq, &ri); 2534 if (avail == 0 && budget_left) 2535 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2536 2537 if (__predict_false(m == NULL)) { 2538 DBG_COUNTER_INC(rx_mbuf_null); 2539 continue; 2540 } 2541 /* imm_pkt: -- cxgb */ 2542 if (mh == NULL) 2543 mh = mt = m; 2544 else { 2545 mt->m_nextpkt = m; 2546 mt = m; 2547 } 2548 } 2549 /* make sure that we can refill faster than drain */ 2550 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2551 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2552 2553 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2554 mt = mf = NULL; 2555 while (mh != NULL) { 2556 m = mh; 2557 if (mf == NULL) 2558 mf = m; 2559 mh = mh->m_nextpkt; 2560 m->m_nextpkt = NULL; 2561 #ifndef __NO_STRICT_ALIGNMENT 2562 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2563 continue; 2564 #endif 2565 rx_bytes += m->m_pkthdr.len; 2566 rx_pkts++; 2567 #if defined(INET6) || defined(INET) 2568 if (lro_enabled && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) { 2569 if (mf == m) 2570 mf = NULL; 2571 continue; 2572 } 2573 #endif 2574 if (mt != NULL) 2575 mt->m_nextpkt = m; 2576 mt = m; 2577 } 2578 if (mf != NULL) { 2579 ifp->if_input(ifp, mf); 2580 DBG_COUNTER_INC(rx_if_input); 2581 } 2582 2583 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2584 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2585 2586 /* 2587 * Flush any outstanding LRO work 2588 */ 2589 #if defined(INET6) || defined(INET) 2590 tcp_lro_flush_all(&rxq->ifr_lc); 2591 #endif 2592 if (avail) 2593 return true; 2594 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2595 err: 2596 CTX_LOCK(ctx); 2597 ctx->ifc_flags |= IFC_DO_RESET; 2598 iflib_admin_intr_deferred(ctx); 2599 CTX_UNLOCK(ctx); 2600 return (false); 2601 } 2602 2603 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2604 static inline qidx_t 2605 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2606 { 2607 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2608 qidx_t minthresh = txq->ift_size / 8; 2609 if (in_use > 4*minthresh) 2610 return (notify_count); 2611 if (in_use > 2*minthresh) 2612 return (notify_count >> 1); 2613 if (in_use > minthresh) 2614 return (notify_count >> 3); 2615 return (0); 2616 } 2617 2618 static inline qidx_t 2619 txq_max_rs_deferred(iflib_txq_t txq) 2620 { 2621 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2622 qidx_t minthresh = txq->ift_size / 8; 2623 if (txq->ift_in_use > 4*minthresh) 2624 return (notify_count); 2625 if (txq->ift_in_use > 2*minthresh) 2626 return (notify_count >> 1); 2627 if (txq->ift_in_use > minthresh) 2628 return (notify_count >> 2); 2629 return (2); 2630 } 2631 2632 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2633 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2634 2635 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2636 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2637 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2638 2639 /* forward compatibility for cxgb */ 2640 #define FIRST_QSET(ctx) 0 2641 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2642 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2643 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2644 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2645 2646 /* XXX we should be setting this to something other than zero */ 2647 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2648 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2649 2650 static inline bool 2651 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2652 { 2653 qidx_t dbval, max; 2654 bool rang; 2655 2656 rang = false; 2657 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2658 if (ring || txq->ift_db_pending >= max) { 2659 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2660 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2661 txq->ift_db_pending = txq->ift_npending = 0; 2662 rang = true; 2663 } 2664 return (rang); 2665 } 2666 2667 #ifdef PKT_DEBUG 2668 static void 2669 print_pkt(if_pkt_info_t pi) 2670 { 2671 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2672 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2673 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2674 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2675 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2676 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2677 } 2678 #endif 2679 2680 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2681 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2682 2683 static int 2684 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2685 { 2686 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2687 struct ether_vlan_header *eh; 2688 struct mbuf *m, *n; 2689 2690 n = m = *mp; 2691 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2692 M_WRITABLE(m) == 0) { 2693 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2694 return (ENOMEM); 2695 } else { 2696 m_freem(*mp); 2697 n = *mp = m; 2698 } 2699 } 2700 2701 /* 2702 * Determine where frame payload starts. 2703 * Jump over vlan headers if already present, 2704 * helpful for QinQ too. 2705 */ 2706 if (__predict_false(m->m_len < sizeof(*eh))) { 2707 txq->ift_pullups++; 2708 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2709 return (ENOMEM); 2710 } 2711 eh = mtod(m, struct ether_vlan_header *); 2712 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2713 pi->ipi_etype = ntohs(eh->evl_proto); 2714 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2715 } else { 2716 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2717 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2718 } 2719 2720 if (if_getmtu(txq->ift_ctx->ifc_ifp) >= pi->ipi_len) { 2721 pi->ipi_csum_flags &= ~(CSUM_IP_TSO|CSUM_IP6_TSO); 2722 } 2723 2724 switch (pi->ipi_etype) { 2725 #ifdef INET 2726 case ETHERTYPE_IP: 2727 { 2728 struct ip *ip = NULL; 2729 struct tcphdr *th = NULL; 2730 int minthlen; 2731 2732 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2733 if (__predict_false(m->m_len < minthlen)) { 2734 /* 2735 * if this code bloat is causing too much of a hit 2736 * move it to a separate function and mark it noinline 2737 */ 2738 if (m->m_len == pi->ipi_ehdrlen) { 2739 n = m->m_next; 2740 MPASS(n); 2741 if (n->m_len >= sizeof(*ip)) { 2742 ip = (struct ip *)n->m_data; 2743 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2744 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2745 } else { 2746 txq->ift_pullups++; 2747 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2748 return (ENOMEM); 2749 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2750 } 2751 } else { 2752 txq->ift_pullups++; 2753 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2754 return (ENOMEM); 2755 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2756 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2757 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2758 } 2759 } else { 2760 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2761 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2762 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2763 } 2764 pi->ipi_ip_hlen = ip->ip_hl << 2; 2765 pi->ipi_ipproto = ip->ip_p; 2766 pi->ipi_flags |= IPI_TX_IPV4; 2767 2768 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 2769 ip->ip_sum = 0; 2770 2771 if (IS_TSO4(pi)) { 2772 if (pi->ipi_ipproto == IPPROTO_TCP) { 2773 if (__predict_false(th == NULL)) { 2774 txq->ift_pullups++; 2775 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2776 return (ENOMEM); 2777 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2778 } 2779 pi->ipi_tcp_hflags = th->th_flags; 2780 pi->ipi_tcp_hlen = th->th_off << 2; 2781 pi->ipi_tcp_seq = th->th_seq; 2782 } 2783 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2784 return (ENXIO); 2785 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2786 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2787 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2788 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2789 ip->ip_sum = 0; 2790 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2791 } 2792 } 2793 break; 2794 } 2795 #endif 2796 #ifdef INET6 2797 case ETHERTYPE_IPV6: 2798 { 2799 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2800 struct tcphdr *th; 2801 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2802 2803 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2804 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2805 return (ENOMEM); 2806 } 2807 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2808 2809 /* XXX-BZ this will go badly in case of ext hdrs. */ 2810 pi->ipi_ipproto = ip6->ip6_nxt; 2811 pi->ipi_flags |= IPI_TX_IPV6; 2812 2813 if (IS_TSO6(pi)) { 2814 if (pi->ipi_ipproto == IPPROTO_TCP) { 2815 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2816 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2817 return (ENOMEM); 2818 } 2819 pi->ipi_tcp_hflags = th->th_flags; 2820 pi->ipi_tcp_hlen = th->th_off << 2; 2821 } 2822 2823 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2824 return (ENXIO); 2825 /* 2826 * The corresponding flag is set by the stack in the IPv4 2827 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 2828 * So, set it here because the rest of the flow requires it. 2829 */ 2830 pi->ipi_csum_flags |= CSUM_TCP_IPV6; 2831 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2832 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2833 } 2834 break; 2835 } 2836 #endif 2837 default: 2838 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2839 pi->ipi_ip_hlen = 0; 2840 break; 2841 } 2842 *mp = m; 2843 2844 return (0); 2845 } 2846 2847 static __noinline struct mbuf * 2848 collapse_pkthdr(struct mbuf *m0) 2849 { 2850 struct mbuf *m, *m_next, *tmp; 2851 2852 m = m0; 2853 m_next = m->m_next; 2854 while (m_next != NULL && m_next->m_len == 0) { 2855 m = m_next; 2856 m->m_next = NULL; 2857 m_free(m); 2858 m_next = m_next->m_next; 2859 } 2860 m = m0; 2861 m->m_next = m_next; 2862 if ((m_next->m_flags & M_EXT) == 0) { 2863 m = m_defrag(m, M_NOWAIT); 2864 } else { 2865 tmp = m_next->m_next; 2866 memcpy(m_next, m, MPKTHSIZE); 2867 m = m_next; 2868 m->m_next = tmp; 2869 } 2870 return (m); 2871 } 2872 2873 /* 2874 * If dodgy hardware rejects the scatter gather chain we've handed it 2875 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 2876 * m_defrag'd mbufs 2877 */ 2878 static __noinline struct mbuf * 2879 iflib_remove_mbuf(iflib_txq_t txq) 2880 { 2881 int ntxd, i, pidx; 2882 struct mbuf *m, *mh, **ifsd_m; 2883 2884 pidx = txq->ift_pidx; 2885 ifsd_m = txq->ift_sds.ifsd_m; 2886 ntxd = txq->ift_size; 2887 mh = m = ifsd_m[pidx]; 2888 ifsd_m[pidx] = NULL; 2889 #if MEMORY_LOGGING 2890 txq->ift_dequeued++; 2891 #endif 2892 i = 1; 2893 2894 while (m) { 2895 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 2896 #if MEMORY_LOGGING 2897 txq->ift_dequeued++; 2898 #endif 2899 m = m->m_next; 2900 i++; 2901 } 2902 return (mh); 2903 } 2904 2905 static int 2906 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 2907 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 2908 int max_segs, int flags) 2909 { 2910 if_ctx_t ctx; 2911 if_shared_ctx_t sctx; 2912 if_softc_ctx_t scctx; 2913 int i, next, pidx, err, ntxd, count; 2914 struct mbuf *m, *tmp, **ifsd_m; 2915 2916 m = *m0; 2917 2918 /* 2919 * Please don't ever do this 2920 */ 2921 if (__predict_false(m->m_len == 0)) 2922 *m0 = m = collapse_pkthdr(m); 2923 2924 ctx = txq->ift_ctx; 2925 sctx = ctx->ifc_sctx; 2926 scctx = &ctx->ifc_softc_ctx; 2927 ifsd_m = txq->ift_sds.ifsd_m; 2928 ntxd = txq->ift_size; 2929 pidx = txq->ift_pidx; 2930 if (map != NULL) { 2931 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 2932 2933 err = bus_dmamap_load_mbuf_sg(tag, map, 2934 *m0, segs, nsegs, BUS_DMA_NOWAIT); 2935 if (err) 2936 return (err); 2937 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 2938 count = 0; 2939 m = *m0; 2940 do { 2941 if (__predict_false(m->m_len <= 0)) { 2942 tmp = m; 2943 m = m->m_next; 2944 tmp->m_next = NULL; 2945 m_free(tmp); 2946 continue; 2947 } 2948 m = m->m_next; 2949 count++; 2950 } while (m != NULL); 2951 if (count > *nsegs) { 2952 ifsd_m[pidx] = *m0; 2953 ifsd_m[pidx]->m_flags |= M_TOOBIG; 2954 return (0); 2955 } 2956 m = *m0; 2957 count = 0; 2958 do { 2959 next = (pidx + count) & (ntxd-1); 2960 MPASS(ifsd_m[next] == NULL); 2961 ifsd_m[next] = m; 2962 count++; 2963 tmp = m; 2964 m = m->m_next; 2965 } while (m != NULL); 2966 } else { 2967 int buflen, sgsize, maxsegsz, max_sgsize; 2968 vm_offset_t vaddr; 2969 vm_paddr_t curaddr; 2970 2971 count = i = 0; 2972 m = *m0; 2973 if (m->m_pkthdr.csum_flags & CSUM_TSO) 2974 maxsegsz = scctx->isc_tx_tso_segsize_max; 2975 else 2976 maxsegsz = sctx->isc_tx_maxsegsize; 2977 2978 do { 2979 if (__predict_false(m->m_len <= 0)) { 2980 tmp = m; 2981 m = m->m_next; 2982 tmp->m_next = NULL; 2983 m_free(tmp); 2984 continue; 2985 } 2986 buflen = m->m_len; 2987 vaddr = (vm_offset_t)m->m_data; 2988 /* 2989 * see if we can't be smarter about physically 2990 * contiguous mappings 2991 */ 2992 next = (pidx + count) & (ntxd-1); 2993 MPASS(ifsd_m[next] == NULL); 2994 #if MEMORY_LOGGING 2995 txq->ift_enqueued++; 2996 #endif 2997 ifsd_m[next] = m; 2998 while (buflen > 0) { 2999 if (i >= max_segs) 3000 goto err; 3001 max_sgsize = MIN(buflen, maxsegsz); 3002 curaddr = pmap_kextract(vaddr); 3003 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 3004 sgsize = MIN(sgsize, max_sgsize); 3005 segs[i].ds_addr = curaddr; 3006 segs[i].ds_len = sgsize; 3007 vaddr += sgsize; 3008 buflen -= sgsize; 3009 i++; 3010 } 3011 count++; 3012 tmp = m; 3013 m = m->m_next; 3014 } while (m != NULL); 3015 *nsegs = i; 3016 } 3017 return (0); 3018 err: 3019 *m0 = iflib_remove_mbuf(txq); 3020 return (EFBIG); 3021 } 3022 3023 static inline caddr_t 3024 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3025 { 3026 qidx_t size; 3027 int ntxd; 3028 caddr_t start, end, cur, next; 3029 3030 ntxd = txq->ift_size; 3031 size = txq->ift_txd_size[qid]; 3032 start = txq->ift_ifdi[qid].idi_vaddr; 3033 3034 if (__predict_false(size == 0)) 3035 return (start); 3036 cur = start + size*cidx; 3037 end = start + size*ntxd; 3038 next = CACHE_PTR_NEXT(cur); 3039 return (next < end ? next : start); 3040 } 3041 3042 static int 3043 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3044 { 3045 if_ctx_t ctx; 3046 if_shared_ctx_t sctx; 3047 if_softc_ctx_t scctx; 3048 bus_dma_segment_t *segs; 3049 struct mbuf *m_head; 3050 void *next_txd; 3051 bus_dmamap_t map; 3052 struct if_pkt_info pi; 3053 int remap = 0; 3054 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3055 bus_dma_tag_t desc_tag; 3056 3057 segs = txq->ift_segs; 3058 ctx = txq->ift_ctx; 3059 sctx = ctx->ifc_sctx; 3060 scctx = &ctx->ifc_softc_ctx; 3061 segs = txq->ift_segs; 3062 ntxd = txq->ift_size; 3063 m_head = *m_headp; 3064 map = NULL; 3065 3066 /* 3067 * If we're doing TSO the next descriptor to clean may be quite far ahead 3068 */ 3069 cidx = txq->ift_cidx; 3070 pidx = txq->ift_pidx; 3071 if (ctx->ifc_flags & IFC_PREFETCH) { 3072 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3073 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3074 next_txd = calc_next_txd(txq, cidx, 0); 3075 prefetch(next_txd); 3076 } 3077 3078 /* prefetch the next cache line of mbuf pointers and flags */ 3079 prefetch(&txq->ift_sds.ifsd_m[next]); 3080 if (txq->ift_sds.ifsd_map != NULL) { 3081 prefetch(&txq->ift_sds.ifsd_map[next]); 3082 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3083 prefetch(&txq->ift_sds.ifsd_flags[next]); 3084 } 3085 } else if (txq->ift_sds.ifsd_map != NULL) 3086 map = txq->ift_sds.ifsd_map[pidx]; 3087 3088 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3089 desc_tag = txq->ift_tso_desc_tag; 3090 max_segs = scctx->isc_tx_tso_segments_max; 3091 } else { 3092 desc_tag = txq->ift_desc_tag; 3093 max_segs = scctx->isc_tx_nsegments; 3094 } 3095 m_head = *m_headp; 3096 3097 pkt_info_zero(&pi); 3098 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3099 pi.ipi_pidx = pidx; 3100 pi.ipi_qsidx = txq->ift_id; 3101 pi.ipi_len = m_head->m_pkthdr.len; 3102 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3103 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3104 3105 /* deliberate bitwise OR to make one condition */ 3106 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3107 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3108 return (err); 3109 m_head = *m_headp; 3110 } 3111 3112 retry: 3113 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3114 defrag: 3115 if (__predict_false(err)) { 3116 switch (err) { 3117 case EFBIG: 3118 /* try collapse once and defrag once */ 3119 if (remap == 0) 3120 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3121 if (remap == 1) 3122 m_head = m_defrag(*m_headp, M_NOWAIT); 3123 remap++; 3124 if (__predict_false(m_head == NULL)) 3125 goto defrag_failed; 3126 txq->ift_mbuf_defrag++; 3127 *m_headp = m_head; 3128 goto retry; 3129 break; 3130 case ENOMEM: 3131 txq->ift_no_tx_dma_setup++; 3132 break; 3133 default: 3134 txq->ift_no_tx_dma_setup++; 3135 m_freem(*m_headp); 3136 DBG_COUNTER_INC(tx_frees); 3137 *m_headp = NULL; 3138 break; 3139 } 3140 txq->ift_map_failed++; 3141 DBG_COUNTER_INC(encap_load_mbuf_fail); 3142 return (err); 3143 } 3144 3145 /* 3146 * XXX assumes a 1 to 1 relationship between segments and 3147 * descriptors - this does not hold true on all drivers, e.g. 3148 * cxgb 3149 */ 3150 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3151 txq->ift_no_desc_avail++; 3152 if (map != NULL) 3153 bus_dmamap_unload(desc_tag, map); 3154 DBG_COUNTER_INC(encap_txq_avail_fail); 3155 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3156 GROUPTASK_ENQUEUE(&txq->ift_task); 3157 return (ENOBUFS); 3158 } 3159 /* 3160 * On Intel cards we can greatly reduce the number of TX interrupts 3161 * we see by only setting report status on every Nth descriptor. 3162 * However, this also means that the driver will need to keep track 3163 * of the descriptors that RS was set on to check them for the DD bit. 3164 */ 3165 txq->ift_rs_pending += nsegs + 1; 3166 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3167 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) { 3168 pi.ipi_flags |= IPI_TX_INTR; 3169 txq->ift_rs_pending = 0; 3170 } 3171 3172 pi.ipi_segs = segs; 3173 pi.ipi_nsegs = nsegs; 3174 3175 MPASS(pidx >= 0 && pidx < txq->ift_size); 3176 #ifdef PKT_DEBUG 3177 print_pkt(&pi); 3178 #endif 3179 if (map != NULL) 3180 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3181 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3182 if (map != NULL) 3183 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3184 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3185 DBG_COUNTER_INC(tx_encap); 3186 MPASS(pi.ipi_new_pidx < txq->ift_size); 3187 3188 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3189 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3190 ndesc += txq->ift_size; 3191 txq->ift_gen = 1; 3192 } 3193 /* 3194 * drivers can need as many as 3195 * two sentinels 3196 */ 3197 MPASS(ndesc <= pi.ipi_nsegs + 2); 3198 MPASS(pi.ipi_new_pidx != pidx); 3199 MPASS(ndesc > 0); 3200 txq->ift_in_use += ndesc; 3201 3202 /* 3203 * We update the last software descriptor again here because there may 3204 * be a sentinel and/or there may be more mbufs than segments 3205 */ 3206 txq->ift_pidx = pi.ipi_new_pidx; 3207 txq->ift_npending += pi.ipi_ndescs; 3208 } else if (__predict_false(err == EFBIG && remap < 2)) { 3209 *m_headp = m_head = iflib_remove_mbuf(txq); 3210 remap = 1; 3211 txq->ift_txd_encap_efbig++; 3212 goto defrag; 3213 } else 3214 DBG_COUNTER_INC(encap_txd_encap_fail); 3215 return (err); 3216 3217 defrag_failed: 3218 txq->ift_mbuf_defrag_failed++; 3219 txq->ift_map_failed++; 3220 m_freem(*m_headp); 3221 DBG_COUNTER_INC(tx_frees); 3222 *m_headp = NULL; 3223 return (ENOMEM); 3224 } 3225 3226 static void 3227 iflib_tx_desc_free(iflib_txq_t txq, int n) 3228 { 3229 int hasmap; 3230 uint32_t qsize, cidx, mask, gen; 3231 struct mbuf *m, **ifsd_m; 3232 uint8_t *ifsd_flags; 3233 bus_dmamap_t *ifsd_map; 3234 bool do_prefetch; 3235 3236 cidx = txq->ift_cidx; 3237 gen = txq->ift_gen; 3238 qsize = txq->ift_size; 3239 mask = qsize-1; 3240 hasmap = txq->ift_sds.ifsd_map != NULL; 3241 ifsd_flags = txq->ift_sds.ifsd_flags; 3242 ifsd_m = txq->ift_sds.ifsd_m; 3243 ifsd_map = txq->ift_sds.ifsd_map; 3244 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3245 3246 while (n--) { 3247 if (do_prefetch) { 3248 prefetch(ifsd_m[(cidx + 3) & mask]); 3249 prefetch(ifsd_m[(cidx + 4) & mask]); 3250 } 3251 if (ifsd_m[cidx] != NULL) { 3252 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3253 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3254 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3255 /* 3256 * does it matter if it's not the TSO tag? If so we'll 3257 * have to add the type to flags 3258 */ 3259 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3260 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3261 } 3262 if ((m = ifsd_m[cidx]) != NULL) { 3263 /* XXX we don't support any drivers that batch packets yet */ 3264 MPASS(m->m_nextpkt == NULL); 3265 /* if the number of clusters exceeds the number of segments 3266 * there won't be space on the ring to save a pointer to each 3267 * cluster so we simply free the list here 3268 */ 3269 if (m->m_flags & M_TOOBIG) { 3270 m_freem(m); 3271 } else { 3272 m_free(m); 3273 } 3274 ifsd_m[cidx] = NULL; 3275 #if MEMORY_LOGGING 3276 txq->ift_dequeued++; 3277 #endif 3278 DBG_COUNTER_INC(tx_frees); 3279 } 3280 } 3281 if (__predict_false(++cidx == qsize)) { 3282 cidx = 0; 3283 gen = 0; 3284 } 3285 } 3286 txq->ift_cidx = cidx; 3287 txq->ift_gen = gen; 3288 } 3289 3290 static __inline int 3291 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3292 { 3293 int reclaim; 3294 if_ctx_t ctx = txq->ift_ctx; 3295 3296 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3297 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3298 3299 /* 3300 * Need a rate-limiting check so that this isn't called every time 3301 */ 3302 iflib_tx_credits_update(ctx, txq); 3303 reclaim = DESC_RECLAIMABLE(txq); 3304 3305 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3306 #ifdef INVARIANTS 3307 if (iflib_verbose_debug) { 3308 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3309 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3310 reclaim, thresh); 3311 3312 } 3313 #endif 3314 return (0); 3315 } 3316 iflib_tx_desc_free(txq, reclaim); 3317 txq->ift_cleaned += reclaim; 3318 txq->ift_in_use -= reclaim; 3319 3320 return (reclaim); 3321 } 3322 3323 static struct mbuf ** 3324 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3325 { 3326 int next, size; 3327 struct mbuf **items; 3328 3329 size = r->size; 3330 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3331 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3332 3333 prefetch(items[(cidx + offset) & (size-1)]); 3334 if (remaining > 1) { 3335 prefetch2cachelines(&items[next]); 3336 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3337 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3338 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3339 } 3340 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3341 } 3342 3343 static void 3344 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3345 { 3346 3347 ifmp_ring_check_drainage(txq->ift_br, budget); 3348 } 3349 3350 static uint32_t 3351 iflib_txq_can_drain(struct ifmp_ring *r) 3352 { 3353 iflib_txq_t txq = r->cookie; 3354 if_ctx_t ctx = txq->ift_ctx; 3355 3356 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3357 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3358 } 3359 3360 static uint32_t 3361 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3362 { 3363 iflib_txq_t txq = r->cookie; 3364 if_ctx_t ctx = txq->ift_ctx; 3365 struct ifnet *ifp = ctx->ifc_ifp; 3366 struct mbuf **mp, *m; 3367 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3368 int reclaimed, err, in_use_prev, desc_used; 3369 bool do_prefetch, ring, rang; 3370 3371 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3372 !LINK_ACTIVE(ctx))) { 3373 DBG_COUNTER_INC(txq_drain_notready); 3374 return (0); 3375 } 3376 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3377 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3378 avail = IDXDIFF(pidx, cidx, r->size); 3379 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3380 DBG_COUNTER_INC(txq_drain_flushing); 3381 for (i = 0; i < avail; i++) { 3382 m_free(r->items[(cidx + i) & (r->size-1)]); 3383 r->items[(cidx + i) & (r->size-1)] = NULL; 3384 } 3385 return (avail); 3386 } 3387 3388 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3389 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3390 CALLOUT_LOCK(txq); 3391 callout_stop(&txq->ift_timer); 3392 CALLOUT_UNLOCK(txq); 3393 DBG_COUNTER_INC(txq_drain_oactive); 3394 return (0); 3395 } 3396 if (reclaimed) 3397 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3398 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3399 count = MIN(avail, TX_BATCH_SIZE); 3400 #ifdef INVARIANTS 3401 if (iflib_verbose_debug) 3402 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3403 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3404 #endif 3405 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3406 avail = TXQ_AVAIL(txq); 3407 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3408 int pidx_prev, rem = do_prefetch ? count - i : 0; 3409 3410 mp = _ring_peek_one(r, cidx, i, rem); 3411 MPASS(mp != NULL && *mp != NULL); 3412 if (__predict_false(*mp == (struct mbuf *)txq)) { 3413 consumed++; 3414 reclaimed++; 3415 continue; 3416 } 3417 in_use_prev = txq->ift_in_use; 3418 pidx_prev = txq->ift_pidx; 3419 err = iflib_encap(txq, mp); 3420 if (__predict_false(err)) { 3421 DBG_COUNTER_INC(txq_drain_encapfail); 3422 /* no room - bail out */ 3423 if (err == ENOBUFS) 3424 break; 3425 consumed++; 3426 DBG_COUNTER_INC(txq_drain_encapfail); 3427 /* we can't send this packet - skip it */ 3428 continue; 3429 } 3430 consumed++; 3431 pkt_sent++; 3432 m = *mp; 3433 DBG_COUNTER_INC(tx_sent); 3434 bytes_sent += m->m_pkthdr.len; 3435 mcast_sent += !!(m->m_flags & M_MCAST); 3436 avail = TXQ_AVAIL(txq); 3437 3438 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3439 desc_used += (txq->ift_in_use - in_use_prev); 3440 ETHER_BPF_MTAP(ifp, m); 3441 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3442 break; 3443 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3444 } 3445 3446 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3447 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3448 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3449 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3450 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3451 if (mcast_sent) 3452 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3453 #ifdef INVARIANTS 3454 if (iflib_verbose_debug) 3455 printf("consumed=%d\n", consumed); 3456 #endif 3457 return (consumed); 3458 } 3459 3460 static uint32_t 3461 iflib_txq_drain_always(struct ifmp_ring *r) 3462 { 3463 return (1); 3464 } 3465 3466 static uint32_t 3467 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3468 { 3469 int i, avail; 3470 struct mbuf **mp; 3471 iflib_txq_t txq; 3472 3473 txq = r->cookie; 3474 3475 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3476 CALLOUT_LOCK(txq); 3477 callout_stop(&txq->ift_timer); 3478 CALLOUT_UNLOCK(txq); 3479 3480 avail = IDXDIFF(pidx, cidx, r->size); 3481 for (i = 0; i < avail; i++) { 3482 mp = _ring_peek_one(r, cidx, i, avail - i); 3483 if (__predict_false(*mp == (struct mbuf *)txq)) 3484 continue; 3485 m_freem(*mp); 3486 } 3487 MPASS(ifmp_ring_is_stalled(r) == 0); 3488 return (avail); 3489 } 3490 3491 static void 3492 iflib_ifmp_purge(iflib_txq_t txq) 3493 { 3494 struct ifmp_ring *r; 3495 3496 r = txq->ift_br; 3497 r->drain = iflib_txq_drain_free; 3498 r->can_drain = iflib_txq_drain_always; 3499 3500 ifmp_ring_check_drainage(r, r->size); 3501 3502 r->drain = iflib_txq_drain; 3503 r->can_drain = iflib_txq_can_drain; 3504 } 3505 3506 static void 3507 _task_fn_tx(void *context) 3508 { 3509 iflib_txq_t txq = context; 3510 if_ctx_t ctx = txq->ift_ctx; 3511 struct ifnet *ifp = ctx->ifc_ifp; 3512 int rc; 3513 3514 #ifdef IFLIB_DIAGNOSTICS 3515 txq->ift_cpu_exec_count[curcpu]++; 3516 #endif 3517 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3518 return; 3519 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3520 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3521 netmap_tx_irq(ifp, txq->ift_id); 3522 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3523 return; 3524 } 3525 if (txq->ift_db_pending) 3526 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); 3527 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3528 if (ctx->ifc_flags & IFC_LEGACY) 3529 IFDI_INTR_ENABLE(ctx); 3530 else { 3531 rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3532 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3533 } 3534 } 3535 3536 static void 3537 _task_fn_rx(void *context) 3538 { 3539 iflib_rxq_t rxq = context; 3540 if_ctx_t ctx = rxq->ifr_ctx; 3541 bool more; 3542 int rc; 3543 uint16_t budget; 3544 3545 #ifdef IFLIB_DIAGNOSTICS 3546 rxq->ifr_cpu_exec_count[curcpu]++; 3547 #endif 3548 DBG_COUNTER_INC(task_fn_rxs); 3549 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3550 return; 3551 more = true; 3552 #ifdef DEV_NETMAP 3553 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3554 u_int work = 0; 3555 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3556 more = false; 3557 } 3558 } 3559 #endif 3560 budget = ctx->ifc_sysctl_rx_budget; 3561 if (budget == 0) 3562 budget = 16; /* XXX */ 3563 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3564 if (ctx->ifc_flags & IFC_LEGACY) 3565 IFDI_INTR_ENABLE(ctx); 3566 else { 3567 DBG_COUNTER_INC(rx_intr_enables); 3568 rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3569 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3570 } 3571 } 3572 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3573 return; 3574 if (more) 3575 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3576 } 3577 3578 static void 3579 _task_fn_admin(void *context) 3580 { 3581 if_ctx_t ctx = context; 3582 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3583 iflib_txq_t txq; 3584 int i; 3585 3586 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) { 3587 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3588 return; 3589 } 3590 } 3591 3592 CTX_LOCK(ctx); 3593 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3594 CALLOUT_LOCK(txq); 3595 callout_stop(&txq->ift_timer); 3596 CALLOUT_UNLOCK(txq); 3597 } 3598 IFDI_UPDATE_ADMIN_STATUS(ctx); 3599 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3600 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 3601 IFDI_LINK_INTR_ENABLE(ctx); 3602 if (ctx->ifc_flags & IFC_DO_RESET) { 3603 ctx->ifc_flags &= ~IFC_DO_RESET; 3604 iflib_if_init_locked(ctx); 3605 } 3606 CTX_UNLOCK(ctx); 3607 3608 if (LINK_ACTIVE(ctx) == 0) 3609 return; 3610 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3611 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3612 } 3613 3614 3615 static void 3616 _task_fn_iov(void *context) 3617 { 3618 if_ctx_t ctx = context; 3619 3620 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3621 return; 3622 3623 CTX_LOCK(ctx); 3624 IFDI_VFLR_HANDLE(ctx); 3625 CTX_UNLOCK(ctx); 3626 } 3627 3628 static int 3629 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3630 { 3631 int err; 3632 if_int_delay_info_t info; 3633 if_ctx_t ctx; 3634 3635 info = (if_int_delay_info_t)arg1; 3636 ctx = info->iidi_ctx; 3637 info->iidi_req = req; 3638 info->iidi_oidp = oidp; 3639 CTX_LOCK(ctx); 3640 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3641 CTX_UNLOCK(ctx); 3642 return (err); 3643 } 3644 3645 /********************************************************************* 3646 * 3647 * IFNET FUNCTIONS 3648 * 3649 **********************************************************************/ 3650 3651 static void 3652 iflib_if_init_locked(if_ctx_t ctx) 3653 { 3654 iflib_stop(ctx); 3655 iflib_init_locked(ctx); 3656 } 3657 3658 3659 static void 3660 iflib_if_init(void *arg) 3661 { 3662 if_ctx_t ctx = arg; 3663 3664 CTX_LOCK(ctx); 3665 iflib_if_init_locked(ctx); 3666 CTX_UNLOCK(ctx); 3667 } 3668 3669 static int 3670 iflib_if_transmit(if_t ifp, struct mbuf *m) 3671 { 3672 if_ctx_t ctx = if_getsoftc(ifp); 3673 3674 iflib_txq_t txq; 3675 int err, qidx; 3676 3677 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3678 DBG_COUNTER_INC(tx_frees); 3679 m_freem(m); 3680 return (ENOBUFS); 3681 } 3682 3683 MPASS(m->m_nextpkt == NULL); 3684 qidx = 0; 3685 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3686 qidx = QIDX(ctx, m); 3687 /* 3688 * XXX calculate buf_ring based on flowid (divvy up bits?) 3689 */ 3690 txq = &ctx->ifc_txqs[qidx]; 3691 3692 #ifdef DRIVER_BACKPRESSURE 3693 if (txq->ift_closed) { 3694 while (m != NULL) { 3695 next = m->m_nextpkt; 3696 m->m_nextpkt = NULL; 3697 m_freem(m); 3698 m = next; 3699 } 3700 return (ENOBUFS); 3701 } 3702 #endif 3703 #ifdef notyet 3704 qidx = count = 0; 3705 mp = marr; 3706 next = m; 3707 do { 3708 count++; 3709 next = next->m_nextpkt; 3710 } while (next != NULL); 3711 3712 if (count > nitems(marr)) 3713 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3714 /* XXX check nextpkt */ 3715 m_freem(m); 3716 /* XXX simplify for now */ 3717 DBG_COUNTER_INC(tx_frees); 3718 return (ENOBUFS); 3719 } 3720 for (next = m, i = 0; next != NULL; i++) { 3721 mp[i] = next; 3722 next = next->m_nextpkt; 3723 mp[i]->m_nextpkt = NULL; 3724 } 3725 #endif 3726 DBG_COUNTER_INC(tx_seen); 3727 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); 3728 3729 GROUPTASK_ENQUEUE(&txq->ift_task); 3730 if (err) { 3731 /* support forthcoming later */ 3732 #ifdef DRIVER_BACKPRESSURE 3733 txq->ift_closed = TRUE; 3734 #endif 3735 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3736 m_freem(m); 3737 } 3738 3739 return (err); 3740 } 3741 3742 static void 3743 iflib_if_qflush(if_t ifp) 3744 { 3745 if_ctx_t ctx = if_getsoftc(ifp); 3746 iflib_txq_t txq = ctx->ifc_txqs; 3747 int i; 3748 3749 CTX_LOCK(ctx); 3750 ctx->ifc_flags |= IFC_QFLUSH; 3751 CTX_UNLOCK(ctx); 3752 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3753 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3754 iflib_txq_check_drain(txq, 0); 3755 CTX_LOCK(ctx); 3756 ctx->ifc_flags &= ~IFC_QFLUSH; 3757 CTX_UNLOCK(ctx); 3758 3759 if_qflush(ifp); 3760 } 3761 3762 3763 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3764 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 3765 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 3766 3767 static int 3768 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 3769 { 3770 if_ctx_t ctx = if_getsoftc(ifp); 3771 struct ifreq *ifr = (struct ifreq *)data; 3772 #if defined(INET) || defined(INET6) 3773 struct ifaddr *ifa = (struct ifaddr *)data; 3774 #endif 3775 bool avoid_reset = FALSE; 3776 int err = 0, reinit = 0, bits; 3777 3778 switch (command) { 3779 case SIOCSIFADDR: 3780 #ifdef INET 3781 if (ifa->ifa_addr->sa_family == AF_INET) 3782 avoid_reset = TRUE; 3783 #endif 3784 #ifdef INET6 3785 if (ifa->ifa_addr->sa_family == AF_INET6) 3786 avoid_reset = TRUE; 3787 #endif 3788 /* 3789 ** Calling init results in link renegotiation, 3790 ** so we avoid doing it when possible. 3791 */ 3792 if (avoid_reset) { 3793 if_setflagbits(ifp, IFF_UP,0); 3794 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING)) 3795 reinit = 1; 3796 #ifdef INET 3797 if (!(if_getflags(ifp) & IFF_NOARP)) 3798 arp_ifinit(ifp, ifa); 3799 #endif 3800 } else 3801 err = ether_ioctl(ifp, command, data); 3802 break; 3803 case SIOCSIFMTU: 3804 CTX_LOCK(ctx); 3805 if (ifr->ifr_mtu == if_getmtu(ifp)) { 3806 CTX_UNLOCK(ctx); 3807 break; 3808 } 3809 bits = if_getdrvflags(ifp); 3810 /* stop the driver and free any clusters before proceeding */ 3811 iflib_stop(ctx); 3812 3813 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 3814 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 3815 ctx->ifc_flags |= IFC_MULTISEG; 3816 else 3817 ctx->ifc_flags &= ~IFC_MULTISEG; 3818 err = if_setmtu(ifp, ifr->ifr_mtu); 3819 } 3820 iflib_init_locked(ctx); 3821 if_setdrvflags(ifp, bits); 3822 CTX_UNLOCK(ctx); 3823 break; 3824 case SIOCSIFFLAGS: 3825 CTX_LOCK(ctx); 3826 if (if_getflags(ifp) & IFF_UP) { 3827 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3828 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 3829 (IFF_PROMISC | IFF_ALLMULTI)) { 3830 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 3831 } 3832 } else 3833 reinit = 1; 3834 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3835 iflib_stop(ctx); 3836 } 3837 ctx->ifc_if_flags = if_getflags(ifp); 3838 CTX_UNLOCK(ctx); 3839 break; 3840 case SIOCADDMULTI: 3841 case SIOCDELMULTI: 3842 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3843 CTX_LOCK(ctx); 3844 IFDI_INTR_DISABLE(ctx); 3845 IFDI_MULTI_SET(ctx); 3846 IFDI_INTR_ENABLE(ctx); 3847 CTX_UNLOCK(ctx); 3848 } 3849 break; 3850 case SIOCSIFMEDIA: 3851 CTX_LOCK(ctx); 3852 IFDI_MEDIA_SET(ctx); 3853 CTX_UNLOCK(ctx); 3854 /* falls thru */ 3855 case SIOCGIFMEDIA: 3856 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 3857 break; 3858 case SIOCGI2C: 3859 { 3860 struct ifi2creq i2c; 3861 3862 err = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); 3863 if (err != 0) 3864 break; 3865 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 3866 err = EINVAL; 3867 break; 3868 } 3869 if (i2c.len > sizeof(i2c.data)) { 3870 err = EINVAL; 3871 break; 3872 } 3873 3874 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 3875 err = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); 3876 break; 3877 } 3878 case SIOCSIFCAP: 3879 { 3880 int mask, setmask; 3881 3882 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3883 setmask = 0; 3884 #ifdef TCP_OFFLOAD 3885 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 3886 #endif 3887 setmask |= (mask & IFCAP_FLAGS); 3888 3889 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 3890 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 3891 if ((mask & IFCAP_WOL) && 3892 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 3893 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 3894 if_vlancap(ifp); 3895 /* 3896 * want to ensure that traffic has stopped before we change any of the flags 3897 */ 3898 if (setmask) { 3899 CTX_LOCK(ctx); 3900 bits = if_getdrvflags(ifp); 3901 if (bits & IFF_DRV_RUNNING) 3902 iflib_stop(ctx); 3903 if_togglecapenable(ifp, setmask); 3904 if (bits & IFF_DRV_RUNNING) 3905 iflib_init_locked(ctx); 3906 if_setdrvflags(ifp, bits); 3907 CTX_UNLOCK(ctx); 3908 } 3909 break; 3910 } 3911 case SIOCGPRIVATE_0: 3912 case SIOCSDRVSPEC: 3913 case SIOCGDRVSPEC: 3914 CTX_LOCK(ctx); 3915 err = IFDI_PRIV_IOCTL(ctx, command, data); 3916 CTX_UNLOCK(ctx); 3917 break; 3918 default: 3919 err = ether_ioctl(ifp, command, data); 3920 break; 3921 } 3922 if (reinit) 3923 iflib_if_init(ctx); 3924 return (err); 3925 } 3926 3927 static uint64_t 3928 iflib_if_get_counter(if_t ifp, ift_counter cnt) 3929 { 3930 if_ctx_t ctx = if_getsoftc(ifp); 3931 3932 return (IFDI_GET_COUNTER(ctx, cnt)); 3933 } 3934 3935 /********************************************************************* 3936 * 3937 * OTHER FUNCTIONS EXPORTED TO THE STACK 3938 * 3939 **********************************************************************/ 3940 3941 static void 3942 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 3943 { 3944 if_ctx_t ctx = if_getsoftc(ifp); 3945 3946 if ((void *)ctx != arg) 3947 return; 3948 3949 if ((vtag == 0) || (vtag > 4095)) 3950 return; 3951 3952 CTX_LOCK(ctx); 3953 IFDI_VLAN_REGISTER(ctx, vtag); 3954 /* Re-init to load the changes */ 3955 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 3956 iflib_if_init_locked(ctx); 3957 CTX_UNLOCK(ctx); 3958 } 3959 3960 static void 3961 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 3962 { 3963 if_ctx_t ctx = if_getsoftc(ifp); 3964 3965 if ((void *)ctx != arg) 3966 return; 3967 3968 if ((vtag == 0) || (vtag > 4095)) 3969 return; 3970 3971 CTX_LOCK(ctx); 3972 IFDI_VLAN_UNREGISTER(ctx, vtag); 3973 /* Re-init to load the changes */ 3974 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 3975 iflib_if_init_locked(ctx); 3976 CTX_UNLOCK(ctx); 3977 } 3978 3979 static void 3980 iflib_led_func(void *arg, int onoff) 3981 { 3982 if_ctx_t ctx = arg; 3983 3984 CTX_LOCK(ctx); 3985 IFDI_LED_FUNC(ctx, onoff); 3986 CTX_UNLOCK(ctx); 3987 } 3988 3989 /********************************************************************* 3990 * 3991 * BUS FUNCTION DEFINITIONS 3992 * 3993 **********************************************************************/ 3994 3995 int 3996 iflib_device_probe(device_t dev) 3997 { 3998 pci_vendor_info_t *ent; 3999 4000 uint16_t pci_vendor_id, pci_device_id; 4001 uint16_t pci_subvendor_id, pci_subdevice_id; 4002 uint16_t pci_rev_id; 4003 if_shared_ctx_t sctx; 4004 4005 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4006 return (ENOTSUP); 4007 4008 pci_vendor_id = pci_get_vendor(dev); 4009 pci_device_id = pci_get_device(dev); 4010 pci_subvendor_id = pci_get_subvendor(dev); 4011 pci_subdevice_id = pci_get_subdevice(dev); 4012 pci_rev_id = pci_get_revid(dev); 4013 if (sctx->isc_parse_devinfo != NULL) 4014 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4015 4016 ent = sctx->isc_vendor_info; 4017 while (ent->pvi_vendor_id != 0) { 4018 if (pci_vendor_id != ent->pvi_vendor_id) { 4019 ent++; 4020 continue; 4021 } 4022 if ((pci_device_id == ent->pvi_device_id) && 4023 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4024 (ent->pvi_subvendor_id == 0)) && 4025 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4026 (ent->pvi_subdevice_id == 0)) && 4027 ((pci_rev_id == ent->pvi_rev_id) || 4028 (ent->pvi_rev_id == 0))) { 4029 4030 device_set_desc_copy(dev, ent->pvi_name); 4031 /* this needs to be changed to zero if the bus probing code 4032 * ever stops re-probing on best match because the sctx 4033 * may have its values over written by register calls 4034 * in subsequent probes 4035 */ 4036 return (BUS_PROBE_DEFAULT); 4037 } 4038 ent++; 4039 } 4040 return (ENXIO); 4041 } 4042 4043 int 4044 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4045 { 4046 int err, rid, msix, msix_bar; 4047 if_ctx_t ctx; 4048 if_t ifp; 4049 if_softc_ctx_t scctx; 4050 int i; 4051 uint16_t main_txq; 4052 uint16_t main_rxq; 4053 4054 4055 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4056 4057 if (sc == NULL) { 4058 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4059 device_set_softc(dev, ctx); 4060 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4061 } 4062 4063 ctx->ifc_sctx = sctx; 4064 ctx->ifc_dev = dev; 4065 ctx->ifc_softc = sc; 4066 4067 if ((err = iflib_register(ctx)) != 0) { 4068 device_printf(dev, "iflib_register failed %d\n", err); 4069 return (err); 4070 } 4071 iflib_add_device_sysctl_pre(ctx); 4072 4073 scctx = &ctx->ifc_softc_ctx; 4074 ifp = ctx->ifc_ifp; 4075 4076 /* 4077 * XXX sanity check that ntxd & nrxd are a power of 2 4078 */ 4079 if (ctx->ifc_sysctl_ntxqs != 0) 4080 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4081 if (ctx->ifc_sysctl_nrxqs != 0) 4082 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4083 4084 for (i = 0; i < sctx->isc_ntxqs; i++) { 4085 if (ctx->ifc_sysctl_ntxds[i] != 0) 4086 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4087 else 4088 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4089 } 4090 4091 for (i = 0; i < sctx->isc_nrxqs; i++) { 4092 if (ctx->ifc_sysctl_nrxds[i] != 0) 4093 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4094 else 4095 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4096 } 4097 4098 for (i = 0; i < sctx->isc_nrxqs; i++) { 4099 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4100 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4101 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4102 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4103 } 4104 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4105 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4106 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4107 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4108 } 4109 } 4110 4111 for (i = 0; i < sctx->isc_ntxqs; i++) { 4112 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4113 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4114 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4115 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4116 } 4117 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4118 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4119 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4120 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4121 } 4122 } 4123 4124 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4125 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4126 return (err); 4127 } 4128 _iflib_pre_assert(scctx); 4129 ctx->ifc_txrx = *scctx->isc_txrx; 4130 4131 #ifdef INVARIANTS 4132 MPASS(scctx->isc_capenable); 4133 if (scctx->isc_capenable & IFCAP_TXCSUM) 4134 MPASS(scctx->isc_tx_csum_flags); 4135 #endif 4136 4137 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4138 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4139 4140 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4141 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4142 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4143 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4144 4145 #ifdef ACPI_DMAR 4146 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4147 ctx->ifc_flags |= IFC_DMAR; 4148 #elif !(defined(__i386__) || defined(__amd64__)) 4149 /* set unconditionally for !x86 */ 4150 ctx->ifc_flags |= IFC_DMAR; 4151 #endif 4152 4153 msix_bar = scctx->isc_msix_bar; 4154 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4155 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4156 4157 /* XXX change for per-queue sizes */ 4158 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4159 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4160 for (i = 0; i < sctx->isc_nrxqs; i++) { 4161 if (!powerof2(scctx->isc_nrxd[i])) { 4162 /* round down instead? */ 4163 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4164 err = EINVAL; 4165 goto fail; 4166 } 4167 } 4168 for (i = 0; i < sctx->isc_ntxqs; i++) { 4169 if (!powerof2(scctx->isc_ntxd[i])) { 4170 device_printf(dev, 4171 "# tx descriptors must be a power of 2"); 4172 err = EINVAL; 4173 goto fail; 4174 } 4175 } 4176 4177 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4178 MAX_SINGLE_PACKET_FRACTION) 4179 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4180 MAX_SINGLE_PACKET_FRACTION); 4181 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4182 MAX_SINGLE_PACKET_FRACTION) 4183 scctx->isc_tx_tso_segments_max = max(1, 4184 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4185 4186 /* 4187 * Protect the stack against modern hardware 4188 */ 4189 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4190 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4191 4192 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4193 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4194 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4195 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4196 if (scctx->isc_rss_table_size == 0) 4197 scctx->isc_rss_table_size = 64; 4198 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4199 4200 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4201 /* XXX format name */ 4202 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4203 /* 4204 ** Now setup MSI or MSI/X, should 4205 ** return us the number of supported 4206 ** vectors. (Will be 1 for MSI) 4207 */ 4208 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4209 msix = scctx->isc_vectors; 4210 } else if (scctx->isc_msix_bar != 0) 4211 /* 4212 * The simple fact that isc_msix_bar is not 0 does not mean we 4213 * we have a good value there that is known to work. 4214 */ 4215 msix = iflib_msix_init(ctx); 4216 else { 4217 scctx->isc_vectors = 1; 4218 scctx->isc_ntxqsets = 1; 4219 scctx->isc_nrxqsets = 1; 4220 scctx->isc_intr = IFLIB_INTR_LEGACY; 4221 msix = 0; 4222 } 4223 /* Get memory for the station queues */ 4224 if ((err = iflib_queues_alloc(ctx))) { 4225 device_printf(dev, "Unable to allocate queue memory\n"); 4226 goto fail; 4227 } 4228 4229 if ((err = iflib_qset_structures_setup(ctx))) { 4230 device_printf(dev, "qset structure setup failed %d\n", err); 4231 goto fail_queues; 4232 } 4233 4234 /* 4235 * Group taskqueues aren't properly set up until SMP is started, 4236 * so we disable interrupts until we can handle them post 4237 * SI_SUB_SMP. 4238 * 4239 * XXX: disabling interrupts doesn't actually work, at least for 4240 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4241 * we do null handling and depend on this not causing too large an 4242 * interrupt storm. 4243 */ 4244 IFDI_INTR_DISABLE(ctx); 4245 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4246 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4247 goto fail_intr_free; 4248 } 4249 if (msix <= 1) { 4250 rid = 0; 4251 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4252 MPASS(msix == 1); 4253 rid = 1; 4254 } 4255 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4256 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4257 goto fail_intr_free; 4258 } 4259 } 4260 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4261 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4262 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4263 goto fail_detach; 4264 } 4265 if ((err = iflib_netmap_attach(ctx))) { 4266 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4267 goto fail_detach; 4268 } 4269 *ctxp = ctx; 4270 4271 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4272 iflib_add_device_sysctl_post(ctx); 4273 ctx->ifc_flags |= IFC_INIT_DONE; 4274 return (0); 4275 fail_detach: 4276 ether_ifdetach(ctx->ifc_ifp); 4277 fail_intr_free: 4278 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4279 pci_release_msi(ctx->ifc_dev); 4280 fail_queues: 4281 /* XXX free queues */ 4282 fail: 4283 IFDI_DETACH(ctx); 4284 return (err); 4285 } 4286 4287 int 4288 iflib_device_attach(device_t dev) 4289 { 4290 if_ctx_t ctx; 4291 if_shared_ctx_t sctx; 4292 4293 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4294 return (ENOTSUP); 4295 4296 pci_enable_busmaster(dev); 4297 4298 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4299 } 4300 4301 int 4302 iflib_device_deregister(if_ctx_t ctx) 4303 { 4304 if_t ifp = ctx->ifc_ifp; 4305 iflib_txq_t txq; 4306 iflib_rxq_t rxq; 4307 device_t dev = ctx->ifc_dev; 4308 int i, j; 4309 struct taskqgroup *tqg; 4310 iflib_fl_t fl; 4311 4312 /* Make sure VLANS are not using driver */ 4313 if (if_vlantrunkinuse(ifp)) { 4314 device_printf(dev,"Vlan in use, detach first\n"); 4315 return (EBUSY); 4316 } 4317 4318 CTX_LOCK(ctx); 4319 ctx->ifc_in_detach = 1; 4320 iflib_stop(ctx); 4321 CTX_UNLOCK(ctx); 4322 4323 /* Unregister VLAN events */ 4324 if (ctx->ifc_vlan_attach_event != NULL) 4325 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4326 if (ctx->ifc_vlan_detach_event != NULL) 4327 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4328 4329 iflib_netmap_detach(ifp); 4330 ether_ifdetach(ifp); 4331 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4332 CTX_LOCK_DESTROY(ctx); 4333 if (ctx->ifc_led_dev != NULL) 4334 led_destroy(ctx->ifc_led_dev); 4335 /* XXX drain any dependent tasks */ 4336 tqg = qgroup_if_io_tqg; 4337 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4338 callout_drain(&txq->ift_timer); 4339 if (txq->ift_task.gt_uniq != NULL) 4340 taskqgroup_detach(tqg, &txq->ift_task); 4341 } 4342 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4343 if (rxq->ifr_task.gt_uniq != NULL) 4344 taskqgroup_detach(tqg, &rxq->ifr_task); 4345 4346 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4347 free(fl->ifl_rx_bitmap, M_IFLIB); 4348 4349 } 4350 tqg = qgroup_if_config_tqg; 4351 if (ctx->ifc_admin_task.gt_uniq != NULL) 4352 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4353 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4354 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4355 4356 IFDI_DETACH(ctx); 4357 device_set_softc(ctx->ifc_dev, NULL); 4358 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4359 pci_release_msi(dev); 4360 } 4361 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4362 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4363 } 4364 if (ctx->ifc_msix_mem != NULL) { 4365 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4366 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4367 ctx->ifc_msix_mem = NULL; 4368 } 4369 4370 bus_generic_detach(dev); 4371 if_free(ifp); 4372 4373 iflib_tx_structures_free(ctx); 4374 iflib_rx_structures_free(ctx); 4375 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4376 free(ctx->ifc_softc, M_IFLIB); 4377 free(ctx, M_IFLIB); 4378 return (0); 4379 } 4380 4381 4382 int 4383 iflib_device_detach(device_t dev) 4384 { 4385 if_ctx_t ctx = device_get_softc(dev); 4386 4387 return (iflib_device_deregister(ctx)); 4388 } 4389 4390 int 4391 iflib_device_suspend(device_t dev) 4392 { 4393 if_ctx_t ctx = device_get_softc(dev); 4394 4395 CTX_LOCK(ctx); 4396 IFDI_SUSPEND(ctx); 4397 CTX_UNLOCK(ctx); 4398 4399 return bus_generic_suspend(dev); 4400 } 4401 int 4402 iflib_device_shutdown(device_t dev) 4403 { 4404 if_ctx_t ctx = device_get_softc(dev); 4405 4406 CTX_LOCK(ctx); 4407 IFDI_SHUTDOWN(ctx); 4408 CTX_UNLOCK(ctx); 4409 4410 return bus_generic_suspend(dev); 4411 } 4412 4413 4414 int 4415 iflib_device_resume(device_t dev) 4416 { 4417 if_ctx_t ctx = device_get_softc(dev); 4418 iflib_txq_t txq = ctx->ifc_txqs; 4419 4420 CTX_LOCK(ctx); 4421 IFDI_RESUME(ctx); 4422 iflib_init_locked(ctx); 4423 CTX_UNLOCK(ctx); 4424 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4425 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4426 4427 return (bus_generic_resume(dev)); 4428 } 4429 4430 int 4431 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4432 { 4433 int error; 4434 if_ctx_t ctx = device_get_softc(dev); 4435 4436 CTX_LOCK(ctx); 4437 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4438 CTX_UNLOCK(ctx); 4439 4440 return (error); 4441 } 4442 4443 void 4444 iflib_device_iov_uninit(device_t dev) 4445 { 4446 if_ctx_t ctx = device_get_softc(dev); 4447 4448 CTX_LOCK(ctx); 4449 IFDI_IOV_UNINIT(ctx); 4450 CTX_UNLOCK(ctx); 4451 } 4452 4453 int 4454 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 4455 { 4456 int error; 4457 if_ctx_t ctx = device_get_softc(dev); 4458 4459 CTX_LOCK(ctx); 4460 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 4461 CTX_UNLOCK(ctx); 4462 4463 return (error); 4464 } 4465 4466 /********************************************************************* 4467 * 4468 * MODULE FUNCTION DEFINITIONS 4469 * 4470 **********************************************************************/ 4471 4472 /* 4473 * - Start a fast taskqueue thread for each core 4474 * - Start a taskqueue for control operations 4475 */ 4476 static int 4477 iflib_module_init(void) 4478 { 4479 return (0); 4480 } 4481 4482 static int 4483 iflib_module_event_handler(module_t mod, int what, void *arg) 4484 { 4485 int err; 4486 4487 switch (what) { 4488 case MOD_LOAD: 4489 if ((err = iflib_module_init()) != 0) 4490 return (err); 4491 break; 4492 case MOD_UNLOAD: 4493 return (EBUSY); 4494 default: 4495 return (EOPNOTSUPP); 4496 } 4497 4498 return (0); 4499 } 4500 4501 /********************************************************************* 4502 * 4503 * PUBLIC FUNCTION DEFINITIONS 4504 * ordered as in iflib.h 4505 * 4506 **********************************************************************/ 4507 4508 4509 static void 4510 _iflib_assert(if_shared_ctx_t sctx) 4511 { 4512 MPASS(sctx->isc_tx_maxsize); 4513 MPASS(sctx->isc_tx_maxsegsize); 4514 4515 MPASS(sctx->isc_rx_maxsize); 4516 MPASS(sctx->isc_rx_nsegments); 4517 MPASS(sctx->isc_rx_maxsegsize); 4518 4519 MPASS(sctx->isc_nrxd_min[0]); 4520 MPASS(sctx->isc_nrxd_max[0]); 4521 MPASS(sctx->isc_nrxd_default[0]); 4522 MPASS(sctx->isc_ntxd_min[0]); 4523 MPASS(sctx->isc_ntxd_max[0]); 4524 MPASS(sctx->isc_ntxd_default[0]); 4525 } 4526 4527 static void 4528 _iflib_pre_assert(if_softc_ctx_t scctx) 4529 { 4530 4531 MPASS(scctx->isc_txrx->ift_txd_encap); 4532 MPASS(scctx->isc_txrx->ift_txd_flush); 4533 MPASS(scctx->isc_txrx->ift_txd_credits_update); 4534 MPASS(scctx->isc_txrx->ift_rxd_available); 4535 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 4536 MPASS(scctx->isc_txrx->ift_rxd_refill); 4537 MPASS(scctx->isc_txrx->ift_rxd_flush); 4538 } 4539 4540 static int 4541 iflib_register(if_ctx_t ctx) 4542 { 4543 if_shared_ctx_t sctx = ctx->ifc_sctx; 4544 driver_t *driver = sctx->isc_driver; 4545 device_t dev = ctx->ifc_dev; 4546 if_t ifp; 4547 4548 _iflib_assert(sctx); 4549 4550 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 4551 4552 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 4553 if (ifp == NULL) { 4554 device_printf(dev, "can not allocate ifnet structure\n"); 4555 return (ENOMEM); 4556 } 4557 4558 /* 4559 * Initialize our context's device specific methods 4560 */ 4561 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 4562 kobj_class_compile((kobj_class_t) driver); 4563 driver->refs++; 4564 4565 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 4566 if_setsoftc(ifp, ctx); 4567 if_setdev(ifp, dev); 4568 if_setinitfn(ifp, iflib_if_init); 4569 if_setioctlfn(ifp, iflib_if_ioctl); 4570 if_settransmitfn(ifp, iflib_if_transmit); 4571 if_setqflushfn(ifp, iflib_if_qflush); 4572 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 4573 4574 ctx->ifc_vlan_attach_event = 4575 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 4576 EVENTHANDLER_PRI_FIRST); 4577 ctx->ifc_vlan_detach_event = 4578 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 4579 EVENTHANDLER_PRI_FIRST); 4580 4581 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 4582 iflib_media_change, iflib_media_status); 4583 4584 return (0); 4585 } 4586 4587 4588 static int 4589 iflib_queues_alloc(if_ctx_t ctx) 4590 { 4591 if_shared_ctx_t sctx = ctx->ifc_sctx; 4592 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4593 device_t dev = ctx->ifc_dev; 4594 int nrxqsets = scctx->isc_nrxqsets; 4595 int ntxqsets = scctx->isc_ntxqsets; 4596 iflib_txq_t txq; 4597 iflib_rxq_t rxq; 4598 iflib_fl_t fl = NULL; 4599 int i, j, cpu, err, txconf, rxconf; 4600 iflib_dma_info_t ifdip; 4601 uint32_t *rxqsizes = scctx->isc_rxqsizes; 4602 uint32_t *txqsizes = scctx->isc_txqsizes; 4603 uint8_t nrxqs = sctx->isc_nrxqs; 4604 uint8_t ntxqs = sctx->isc_ntxqs; 4605 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 4606 caddr_t *vaddrs; 4607 uint64_t *paddrs; 4608 struct ifmp_ring **brscp; 4609 4610 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 4611 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 4612 4613 brscp = NULL; 4614 txq = NULL; 4615 rxq = NULL; 4616 4617 /* Allocate the TX ring struct memory */ 4618 if (!(txq = 4619 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 4620 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4621 device_printf(dev, "Unable to allocate TX ring memory\n"); 4622 err = ENOMEM; 4623 goto fail; 4624 } 4625 4626 /* Now allocate the RX */ 4627 if (!(rxq = 4628 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 4629 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4630 device_printf(dev, "Unable to allocate RX ring memory\n"); 4631 err = ENOMEM; 4632 goto rx_fail; 4633 } 4634 4635 ctx->ifc_txqs = txq; 4636 ctx->ifc_rxqs = rxq; 4637 4638 /* 4639 * XXX handle allocation failure 4640 */ 4641 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 4642 /* Set up some basics */ 4643 4644 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4645 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4646 err = ENOMEM; 4647 goto err_tx_desc; 4648 } 4649 txq->ift_ifdi = ifdip; 4650 for (j = 0; j < ntxqs; j++, ifdip++) { 4651 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4652 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4653 err = ENOMEM; 4654 goto err_tx_desc; 4655 } 4656 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 4657 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 4658 } 4659 txq->ift_ctx = ctx; 4660 txq->ift_id = i; 4661 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 4662 txq->ift_br_offset = 1; 4663 } else { 4664 txq->ift_br_offset = 0; 4665 } 4666 /* XXX fix this */ 4667 txq->ift_timer.c_cpu = cpu; 4668 4669 if (iflib_txsd_alloc(txq)) { 4670 device_printf(dev, "Critical Failure setting up TX buffers\n"); 4671 err = ENOMEM; 4672 goto err_tx_desc; 4673 } 4674 4675 /* Initialize the TX lock */ 4676 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 4677 device_get_nameunit(dev), txq->ift_id); 4678 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 4679 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 4680 4681 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 4682 device_get_nameunit(dev), txq->ift_id); 4683 4684 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 4685 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 4686 if (err) { 4687 /* XXX free any allocated rings */ 4688 device_printf(dev, "Unable to allocate buf_ring\n"); 4689 goto err_tx_desc; 4690 } 4691 } 4692 4693 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 4694 /* Set up some basics */ 4695 4696 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4697 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4698 err = ENOMEM; 4699 goto err_tx_desc; 4700 } 4701 4702 rxq->ifr_ifdi = ifdip; 4703 /* XXX this needs to be changed if #rx queues != #tx queues */ 4704 rxq->ifr_ntxqirq = 1; 4705 rxq->ifr_txqid[0] = i; 4706 for (j = 0; j < nrxqs; j++, ifdip++) { 4707 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4708 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4709 err = ENOMEM; 4710 goto err_tx_desc; 4711 } 4712 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 4713 } 4714 rxq->ifr_ctx = ctx; 4715 rxq->ifr_id = i; 4716 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 4717 rxq->ifr_fl_offset = 1; 4718 } else { 4719 rxq->ifr_fl_offset = 0; 4720 } 4721 rxq->ifr_nfl = nfree_lists; 4722 if (!(fl = 4723 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 4724 device_printf(dev, "Unable to allocate free list memory\n"); 4725 err = ENOMEM; 4726 goto err_tx_desc; 4727 } 4728 rxq->ifr_fl = fl; 4729 for (j = 0; j < nfree_lists; j++) { 4730 fl[j].ifl_rxq = rxq; 4731 fl[j].ifl_id = j; 4732 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 4733 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 4734 } 4735 /* Allocate receive buffers for the ring*/ 4736 if (iflib_rxsd_alloc(rxq)) { 4737 device_printf(dev, 4738 "Critical Failure setting up receive buffers\n"); 4739 err = ENOMEM; 4740 goto err_rx_desc; 4741 } 4742 4743 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4744 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 4745 } 4746 4747 /* TXQs */ 4748 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4749 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4750 for (i = 0; i < ntxqsets; i++) { 4751 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 4752 4753 for (j = 0; j < ntxqs; j++, di++) { 4754 vaddrs[i*ntxqs + j] = di->idi_vaddr; 4755 paddrs[i*ntxqs + j] = di->idi_paddr; 4756 } 4757 } 4758 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 4759 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4760 iflib_tx_structures_free(ctx); 4761 free(vaddrs, M_IFLIB); 4762 free(paddrs, M_IFLIB); 4763 goto err_rx_desc; 4764 } 4765 free(vaddrs, M_IFLIB); 4766 free(paddrs, M_IFLIB); 4767 4768 /* RXQs */ 4769 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4770 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4771 for (i = 0; i < nrxqsets; i++) { 4772 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 4773 4774 for (j = 0; j < nrxqs; j++, di++) { 4775 vaddrs[i*nrxqs + j] = di->idi_vaddr; 4776 paddrs[i*nrxqs + j] = di->idi_paddr; 4777 } 4778 } 4779 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 4780 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4781 iflib_tx_structures_free(ctx); 4782 free(vaddrs, M_IFLIB); 4783 free(paddrs, M_IFLIB); 4784 goto err_rx_desc; 4785 } 4786 free(vaddrs, M_IFLIB); 4787 free(paddrs, M_IFLIB); 4788 4789 return (0); 4790 4791 /* XXX handle allocation failure changes */ 4792 err_rx_desc: 4793 err_tx_desc: 4794 if (ctx->ifc_rxqs != NULL) 4795 free(ctx->ifc_rxqs, M_IFLIB); 4796 ctx->ifc_rxqs = NULL; 4797 if (ctx->ifc_txqs != NULL) 4798 free(ctx->ifc_txqs, M_IFLIB); 4799 ctx->ifc_txqs = NULL; 4800 rx_fail: 4801 if (brscp != NULL) 4802 free(brscp, M_IFLIB); 4803 if (rxq != NULL) 4804 free(rxq, M_IFLIB); 4805 if (txq != NULL) 4806 free(txq, M_IFLIB); 4807 fail: 4808 return (err); 4809 } 4810 4811 static int 4812 iflib_tx_structures_setup(if_ctx_t ctx) 4813 { 4814 iflib_txq_t txq = ctx->ifc_txqs; 4815 int i; 4816 4817 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4818 iflib_txq_setup(txq); 4819 4820 return (0); 4821 } 4822 4823 static void 4824 iflib_tx_structures_free(if_ctx_t ctx) 4825 { 4826 iflib_txq_t txq = ctx->ifc_txqs; 4827 int i, j; 4828 4829 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 4830 iflib_txq_destroy(txq); 4831 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 4832 iflib_dma_free(&txq->ift_ifdi[j]); 4833 } 4834 free(ctx->ifc_txqs, M_IFLIB); 4835 ctx->ifc_txqs = NULL; 4836 IFDI_QUEUES_FREE(ctx); 4837 } 4838 4839 /********************************************************************* 4840 * 4841 * Initialize all receive rings. 4842 * 4843 **********************************************************************/ 4844 static int 4845 iflib_rx_structures_setup(if_ctx_t ctx) 4846 { 4847 iflib_rxq_t rxq = ctx->ifc_rxqs; 4848 int q; 4849 #if defined(INET6) || defined(INET) 4850 int i, err; 4851 #endif 4852 4853 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 4854 #if defined(INET6) || defined(INET) 4855 tcp_lro_free(&rxq->ifr_lc); 4856 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 4857 TCP_LRO_ENTRIES, min(1024, 4858 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 4859 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 4860 goto fail; 4861 } 4862 rxq->ifr_lro_enabled = TRUE; 4863 #endif 4864 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 4865 } 4866 return (0); 4867 #if defined(INET6) || defined(INET) 4868 fail: 4869 /* 4870 * Free RX software descriptors allocated so far, we will only handle 4871 * the rings that completed, the failing case will have 4872 * cleaned up for itself. 'q' failed, so its the terminus. 4873 */ 4874 rxq = ctx->ifc_rxqs; 4875 for (i = 0; i < q; ++i, rxq++) { 4876 iflib_rx_sds_free(rxq); 4877 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 4878 } 4879 return (err); 4880 #endif 4881 } 4882 4883 /********************************************************************* 4884 * 4885 * Free all receive rings. 4886 * 4887 **********************************************************************/ 4888 static void 4889 iflib_rx_structures_free(if_ctx_t ctx) 4890 { 4891 iflib_rxq_t rxq = ctx->ifc_rxqs; 4892 4893 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 4894 iflib_rx_sds_free(rxq); 4895 } 4896 } 4897 4898 static int 4899 iflib_qset_structures_setup(if_ctx_t ctx) 4900 { 4901 int err; 4902 4903 if ((err = iflib_tx_structures_setup(ctx)) != 0) 4904 return (err); 4905 4906 if ((err = iflib_rx_structures_setup(ctx)) != 0) { 4907 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 4908 iflib_tx_structures_free(ctx); 4909 iflib_rx_structures_free(ctx); 4910 } 4911 return (err); 4912 } 4913 4914 int 4915 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 4916 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name) 4917 { 4918 4919 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 4920 } 4921 4922 static int 4923 find_nth(if_ctx_t ctx, cpuset_t *cpus, int qid) 4924 { 4925 int i, cpuid, eqid, count; 4926 4927 CPU_COPY(&ctx->ifc_cpus, cpus); 4928 count = CPU_COUNT(&ctx->ifc_cpus); 4929 eqid = qid % count; 4930 /* clear up to the qid'th bit */ 4931 for (i = 0; i < eqid; i++) { 4932 cpuid = CPU_FFS(cpus); 4933 MPASS(cpuid != 0); 4934 CPU_CLR(cpuid-1, cpus); 4935 } 4936 cpuid = CPU_FFS(cpus); 4937 MPASS(cpuid != 0); 4938 return (cpuid-1); 4939 } 4940 4941 int 4942 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 4943 iflib_intr_type_t type, driver_filter_t *filter, 4944 void *filter_arg, int qid, char *name) 4945 { 4946 struct grouptask *gtask; 4947 struct taskqgroup *tqg; 4948 iflib_filter_info_t info; 4949 cpuset_t cpus; 4950 gtask_fn_t *fn; 4951 int tqrid, err, cpuid; 4952 driver_filter_t *intr_fast; 4953 void *q; 4954 4955 info = &ctx->ifc_filter_info; 4956 tqrid = rid; 4957 4958 switch (type) { 4959 /* XXX merge tx/rx for netmap? */ 4960 case IFLIB_INTR_TX: 4961 q = &ctx->ifc_txqs[qid]; 4962 info = &ctx->ifc_txqs[qid].ift_filter_info; 4963 gtask = &ctx->ifc_txqs[qid].ift_task; 4964 tqg = qgroup_if_io_tqg; 4965 fn = _task_fn_tx; 4966 intr_fast = iflib_fast_intr; 4967 GROUPTASK_INIT(gtask, 0, fn, q); 4968 break; 4969 case IFLIB_INTR_RX: 4970 q = &ctx->ifc_rxqs[qid]; 4971 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 4972 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4973 tqg = qgroup_if_io_tqg; 4974 fn = _task_fn_rx; 4975 intr_fast = iflib_fast_intr; 4976 GROUPTASK_INIT(gtask, 0, fn, q); 4977 break; 4978 case IFLIB_INTR_RXTX: 4979 q = &ctx->ifc_rxqs[qid]; 4980 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 4981 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4982 tqg = qgroup_if_io_tqg; 4983 fn = _task_fn_rx; 4984 intr_fast = iflib_fast_intr_rxtx; 4985 GROUPTASK_INIT(gtask, 0, fn, q); 4986 break; 4987 case IFLIB_INTR_ADMIN: 4988 q = ctx; 4989 tqrid = -1; 4990 info = &ctx->ifc_filter_info; 4991 gtask = &ctx->ifc_admin_task; 4992 tqg = qgroup_if_config_tqg; 4993 fn = _task_fn_admin; 4994 intr_fast = iflib_fast_intr_ctx; 4995 break; 4996 default: 4997 panic("unknown net intr type"); 4998 } 4999 5000 info->ifi_filter = filter; 5001 info->ifi_filter_arg = filter_arg; 5002 info->ifi_task = gtask; 5003 info->ifi_ctx = q; 5004 5005 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5006 if (err != 0) { 5007 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 5008 return (err); 5009 } 5010 if (type == IFLIB_INTR_ADMIN) 5011 return (0); 5012 5013 if (tqrid != -1) { 5014 cpuid = find_nth(ctx, &cpus, qid); 5015 taskqgroup_attach_cpu(tqg, gtask, q, cpuid, rman_get_start(irq->ii_res), name); 5016 } else { 5017 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5018 } 5019 5020 return (0); 5021 } 5022 5023 void 5024 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, char *name) 5025 { 5026 struct grouptask *gtask; 5027 struct taskqgroup *tqg; 5028 gtask_fn_t *fn; 5029 void *q; 5030 int irq_num = -1; 5031 5032 switch (type) { 5033 case IFLIB_INTR_TX: 5034 q = &ctx->ifc_txqs[qid]; 5035 gtask = &ctx->ifc_txqs[qid].ift_task; 5036 tqg = qgroup_if_io_tqg; 5037 fn = _task_fn_tx; 5038 if (irq != NULL) 5039 irq_num = rman_get_start(irq->ii_res); 5040 break; 5041 case IFLIB_INTR_RX: 5042 q = &ctx->ifc_rxqs[qid]; 5043 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5044 tqg = qgroup_if_io_tqg; 5045 fn = _task_fn_rx; 5046 if (irq != NULL) 5047 irq_num = rman_get_start(irq->ii_res); 5048 break; 5049 case IFLIB_INTR_IOV: 5050 q = ctx; 5051 gtask = &ctx->ifc_vflr_task; 5052 tqg = qgroup_if_config_tqg; 5053 fn = _task_fn_iov; 5054 break; 5055 default: 5056 panic("unknown net intr type"); 5057 } 5058 GROUPTASK_INIT(gtask, 0, fn, q); 5059 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5060 } 5061 5062 void 5063 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5064 { 5065 if (irq->ii_tag) 5066 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5067 5068 if (irq->ii_res) 5069 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5070 } 5071 5072 static int 5073 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name) 5074 { 5075 iflib_txq_t txq = ctx->ifc_txqs; 5076 iflib_rxq_t rxq = ctx->ifc_rxqs; 5077 if_irq_t irq = &ctx->ifc_legacy_irq; 5078 iflib_filter_info_t info; 5079 struct grouptask *gtask; 5080 struct taskqgroup *tqg; 5081 gtask_fn_t *fn; 5082 int tqrid; 5083 void *q; 5084 int err; 5085 5086 q = &ctx->ifc_rxqs[0]; 5087 info = &rxq[0].ifr_filter_info; 5088 gtask = &rxq[0].ifr_task; 5089 tqg = qgroup_if_io_tqg; 5090 tqrid = irq->ii_rid = *rid; 5091 fn = _task_fn_rx; 5092 5093 ctx->ifc_flags |= IFC_LEGACY; 5094 info->ifi_filter = filter; 5095 info->ifi_filter_arg = filter_arg; 5096 info->ifi_task = gtask; 5097 info->ifi_ctx = ctx; 5098 5099 /* We allocate a single interrupt resource */ 5100 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5101 return (err); 5102 GROUPTASK_INIT(gtask, 0, fn, q); 5103 taskqgroup_attach(tqg, gtask, q, tqrid, name); 5104 5105 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5106 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, tqrid, "tx"); 5107 return (0); 5108 } 5109 5110 void 5111 iflib_led_create(if_ctx_t ctx) 5112 { 5113 5114 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5115 device_get_nameunit(ctx->ifc_dev)); 5116 } 5117 5118 void 5119 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5120 { 5121 5122 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5123 } 5124 5125 void 5126 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5127 { 5128 5129 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5130 } 5131 5132 void 5133 iflib_admin_intr_deferred(if_ctx_t ctx) 5134 { 5135 #ifdef INVARIANTS 5136 struct grouptask *gtask; 5137 5138 gtask = &ctx->ifc_admin_task; 5139 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5140 #endif 5141 5142 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5143 } 5144 5145 void 5146 iflib_iov_intr_deferred(if_ctx_t ctx) 5147 { 5148 5149 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5150 } 5151 5152 void 5153 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5154 { 5155 5156 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5157 } 5158 5159 void 5160 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn, 5161 char *name) 5162 { 5163 5164 GROUPTASK_INIT(gtask, 0, fn, ctx); 5165 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5166 } 5167 5168 void 5169 iflib_config_gtask_deinit(struct grouptask *gtask) 5170 { 5171 5172 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5173 } 5174 5175 void 5176 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5177 { 5178 if_t ifp = ctx->ifc_ifp; 5179 iflib_txq_t txq = ctx->ifc_txqs; 5180 5181 if_setbaudrate(ifp, baudrate); 5182 if (baudrate >= IF_Gbps(10)) 5183 ctx->ifc_flags |= IFC_PREFETCH; 5184 5185 /* If link down, disable watchdog */ 5186 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5187 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5188 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5189 } 5190 ctx->ifc_link_state = link_state; 5191 if_link_state_change(ifp, link_state); 5192 } 5193 5194 static int 5195 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5196 { 5197 int credits; 5198 #ifdef INVARIANTS 5199 int credits_pre = txq->ift_cidx_processed; 5200 #endif 5201 5202 if (ctx->isc_txd_credits_update == NULL) 5203 return (0); 5204 5205 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5206 return (0); 5207 5208 txq->ift_processed += credits; 5209 txq->ift_cidx_processed += credits; 5210 5211 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5212 if (txq->ift_cidx_processed >= txq->ift_size) 5213 txq->ift_cidx_processed -= txq->ift_size; 5214 return (credits); 5215 } 5216 5217 static int 5218 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5219 { 5220 5221 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5222 budget)); 5223 } 5224 5225 void 5226 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5227 const char *description, if_int_delay_info_t info, 5228 int offset, int value) 5229 { 5230 info->iidi_ctx = ctx; 5231 info->iidi_offset = offset; 5232 info->iidi_value = value; 5233 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5234 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5235 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5236 info, 0, iflib_sysctl_int_delay, "I", description); 5237 } 5238 5239 struct mtx * 5240 iflib_ctx_lock_get(if_ctx_t ctx) 5241 { 5242 5243 return (&ctx->ifc_mtx); 5244 } 5245 5246 static int 5247 iflib_msix_init(if_ctx_t ctx) 5248 { 5249 device_t dev = ctx->ifc_dev; 5250 if_shared_ctx_t sctx = ctx->ifc_sctx; 5251 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5252 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5253 int iflib_num_tx_queues, iflib_num_rx_queues; 5254 int err, admincnt, bar; 5255 5256 iflib_num_tx_queues = scctx->isc_ntxqsets; 5257 iflib_num_rx_queues = scctx->isc_nrxqsets; 5258 5259 device_printf(dev, "msix_init qsets capped at %d\n", iflib_num_tx_queues); 5260 5261 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5262 admincnt = sctx->isc_admin_intrcnt; 5263 /* Override by tuneable */ 5264 if (scctx->isc_disable_msix) 5265 goto msi; 5266 5267 /* 5268 ** When used in a virtualized environment 5269 ** PCI BUSMASTER capability may not be set 5270 ** so explicity set it here and rewrite 5271 ** the ENABLE in the MSIX control register 5272 ** at this point to cause the host to 5273 ** successfully initialize us. 5274 */ 5275 { 5276 int msix_ctrl, rid; 5277 5278 pci_enable_busmaster(dev); 5279 rid = 0; 5280 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) { 5281 rid += PCIR_MSIX_CTRL; 5282 msix_ctrl = pci_read_config(dev, rid, 2); 5283 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 5284 pci_write_config(dev, rid, msix_ctrl, 2); 5285 } else { 5286 device_printf(dev, "PCIY_MSIX capability not found; " 5287 "or rid %d == 0.\n", rid); 5288 goto msi; 5289 } 5290 } 5291 5292 /* 5293 * bar == -1 => "trust me I know what I'm doing" 5294 * Some drivers are for hardware that is so shoddily 5295 * documented that no one knows which bars are which 5296 * so the developer has to map all bars. This hack 5297 * allows shoddy garbage to use msix in this framework. 5298 */ 5299 if (bar != -1) { 5300 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5301 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5302 if (ctx->ifc_msix_mem == NULL) { 5303 /* May not be enabled */ 5304 device_printf(dev, "Unable to map MSIX table \n"); 5305 goto msi; 5306 } 5307 } 5308 /* First try MSI/X */ 5309 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5310 device_printf(dev, "System has MSIX disabled \n"); 5311 bus_release_resource(dev, SYS_RES_MEMORY, 5312 bar, ctx->ifc_msix_mem); 5313 ctx->ifc_msix_mem = NULL; 5314 goto msi; 5315 } 5316 #if IFLIB_DEBUG 5317 /* use only 1 qset in debug mode */ 5318 queuemsgs = min(msgs - admincnt, 1); 5319 #else 5320 queuemsgs = msgs - admincnt; 5321 #endif 5322 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) == 0) { 5323 #ifdef RSS 5324 queues = imin(queuemsgs, rss_getnumbuckets()); 5325 #else 5326 queues = queuemsgs; 5327 #endif 5328 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 5329 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 5330 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 5331 } else { 5332 device_printf(dev, "Unable to fetch CPU list\n"); 5333 /* Figure out a reasonable auto config value */ 5334 queues = min(queuemsgs, mp_ncpus); 5335 } 5336 #ifdef RSS 5337 /* If we're doing RSS, clamp at the number of RSS buckets */ 5338 if (queues > rss_getnumbuckets()) 5339 queues = rss_getnumbuckets(); 5340 #endif 5341 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 5342 rx_queues = iflib_num_rx_queues; 5343 else 5344 rx_queues = queues; 5345 /* 5346 * We want this to be all logical CPUs by default 5347 */ 5348 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 5349 tx_queues = iflib_num_tx_queues; 5350 else 5351 tx_queues = mp_ncpus; 5352 5353 if (ctx->ifc_sysctl_qs_eq_override == 0) { 5354 #ifdef INVARIANTS 5355 if (tx_queues != rx_queues) 5356 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 5357 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 5358 #endif 5359 tx_queues = min(rx_queues, tx_queues); 5360 rx_queues = min(rx_queues, tx_queues); 5361 } 5362 5363 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 5364 5365 vectors = rx_queues + admincnt; 5366 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 5367 device_printf(dev, 5368 "Using MSIX interrupts with %d vectors\n", vectors); 5369 scctx->isc_vectors = vectors; 5370 scctx->isc_nrxqsets = rx_queues; 5371 scctx->isc_ntxqsets = tx_queues; 5372 scctx->isc_intr = IFLIB_INTR_MSIX; 5373 5374 return (vectors); 5375 } else { 5376 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 5377 } 5378 msi: 5379 vectors = pci_msi_count(dev); 5380 scctx->isc_nrxqsets = 1; 5381 scctx->isc_ntxqsets = 1; 5382 scctx->isc_vectors = vectors; 5383 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 5384 device_printf(dev,"Using an MSI interrupt\n"); 5385 scctx->isc_intr = IFLIB_INTR_MSI; 5386 } else { 5387 device_printf(dev,"Using a Legacy interrupt\n"); 5388 scctx->isc_intr = IFLIB_INTR_LEGACY; 5389 } 5390 5391 return (vectors); 5392 } 5393 5394 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 5395 5396 static int 5397 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 5398 { 5399 int rc; 5400 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 5401 struct sbuf *sb; 5402 char *ring_state = "UNKNOWN"; 5403 5404 /* XXX needed ? */ 5405 rc = sysctl_wire_old_buffer(req, 0); 5406 MPASS(rc == 0); 5407 if (rc != 0) 5408 return (rc); 5409 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 5410 MPASS(sb != NULL); 5411 if (sb == NULL) 5412 return (ENOMEM); 5413 if (state[3] <= 3) 5414 ring_state = ring_states[state[3]]; 5415 5416 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 5417 state[0], state[1], state[2], ring_state); 5418 rc = sbuf_finish(sb); 5419 sbuf_delete(sb); 5420 return(rc); 5421 } 5422 5423 enum iflib_ndesc_handler { 5424 IFLIB_NTXD_HANDLER, 5425 IFLIB_NRXD_HANDLER, 5426 }; 5427 5428 static int 5429 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 5430 { 5431 if_ctx_t ctx = (void *)arg1; 5432 enum iflib_ndesc_handler type = arg2; 5433 char buf[256] = {0}; 5434 qidx_t *ndesc; 5435 char *p, *next; 5436 int nqs, rc, i; 5437 5438 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 5439 5440 nqs = 8; 5441 switch(type) { 5442 case IFLIB_NTXD_HANDLER: 5443 ndesc = ctx->ifc_sysctl_ntxds; 5444 if (ctx->ifc_sctx) 5445 nqs = ctx->ifc_sctx->isc_ntxqs; 5446 break; 5447 case IFLIB_NRXD_HANDLER: 5448 ndesc = ctx->ifc_sysctl_nrxds; 5449 if (ctx->ifc_sctx) 5450 nqs = ctx->ifc_sctx->isc_nrxqs; 5451 break; 5452 } 5453 if (nqs == 0) 5454 nqs = 8; 5455 5456 for (i=0; i<8; i++) { 5457 if (i >= nqs) 5458 break; 5459 if (i) 5460 strcat(buf, ","); 5461 sprintf(strchr(buf, 0), "%d", ndesc[i]); 5462 } 5463 5464 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 5465 if (rc || req->newptr == NULL) 5466 return rc; 5467 5468 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 5469 i++, p = strsep(&next, " ,")) { 5470 ndesc[i] = strtoul(p, NULL, 10); 5471 } 5472 5473 return(rc); 5474 } 5475 5476 #define NAME_BUFLEN 32 5477 static void 5478 iflib_add_device_sysctl_pre(if_ctx_t ctx) 5479 { 5480 device_t dev = iflib_get_dev(ctx); 5481 struct sysctl_oid_list *child, *oid_list; 5482 struct sysctl_ctx_list *ctx_list; 5483 struct sysctl_oid *node; 5484 5485 ctx_list = device_get_sysctl_ctx(dev); 5486 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 5487 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 5488 CTLFLAG_RD, NULL, "IFLIB fields"); 5489 oid_list = SYSCTL_CHILDREN(node); 5490 5491 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 5492 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 5493 "driver version"); 5494 5495 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 5496 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 5497 "# of txqs to use, 0 => use default #"); 5498 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 5499 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 5500 "# of rxqs to use, 0 => use default #"); 5501 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 5502 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 5503 "permit #txq != #rxq"); 5504 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 5505 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 5506 "disable MSIX (default 0)"); 5507 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 5508 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 5509 "set the rx budget"); 5510 5511 /* XXX change for per-queue sizes */ 5512 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 5513 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 5514 mp_ndesc_handler, "A", 5515 "list of # of tx descriptors to use, 0 = use default #"); 5516 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 5517 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 5518 mp_ndesc_handler, "A", 5519 "list of # of rx descriptors to use, 0 = use default #"); 5520 } 5521 5522 static void 5523 iflib_add_device_sysctl_post(if_ctx_t ctx) 5524 { 5525 if_shared_ctx_t sctx = ctx->ifc_sctx; 5526 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5527 device_t dev = iflib_get_dev(ctx); 5528 struct sysctl_oid_list *child; 5529 struct sysctl_ctx_list *ctx_list; 5530 iflib_fl_t fl; 5531 iflib_txq_t txq; 5532 iflib_rxq_t rxq; 5533 int i, j; 5534 char namebuf[NAME_BUFLEN]; 5535 char *qfmt; 5536 struct sysctl_oid *queue_node, *fl_node, *node; 5537 struct sysctl_oid_list *queue_list, *fl_list; 5538 ctx_list = device_get_sysctl_ctx(dev); 5539 5540 node = ctx->ifc_sysctl_node; 5541 child = SYSCTL_CHILDREN(node); 5542 5543 if (scctx->isc_ntxqsets > 100) 5544 qfmt = "txq%03d"; 5545 else if (scctx->isc_ntxqsets > 10) 5546 qfmt = "txq%02d"; 5547 else 5548 qfmt = "txq%d"; 5549 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 5550 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5551 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5552 CTLFLAG_RD, NULL, "Queue Name"); 5553 queue_list = SYSCTL_CHILDREN(queue_node); 5554 #if MEMORY_LOGGING 5555 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 5556 CTLFLAG_RD, 5557 &txq->ift_dequeued, "total mbufs freed"); 5558 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 5559 CTLFLAG_RD, 5560 &txq->ift_enqueued, "total mbufs enqueued"); 5561 #endif 5562 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 5563 CTLFLAG_RD, 5564 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 5565 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 5566 CTLFLAG_RD, 5567 &txq->ift_pullups, "# of times m_pullup was called"); 5568 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 5569 CTLFLAG_RD, 5570 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 5571 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 5572 CTLFLAG_RD, 5573 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 5574 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 5575 CTLFLAG_RD, 5576 &txq->ift_map_failed, "# of times dma map failed"); 5577 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 5578 CTLFLAG_RD, 5579 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 5580 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 5581 CTLFLAG_RD, 5582 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 5583 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 5584 CTLFLAG_RD, 5585 &txq->ift_pidx, 1, "Producer Index"); 5586 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 5587 CTLFLAG_RD, 5588 &txq->ift_cidx, 1, "Consumer Index"); 5589 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 5590 CTLFLAG_RD, 5591 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 5592 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 5593 CTLFLAG_RD, 5594 &txq->ift_in_use, 1, "descriptors in use"); 5595 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 5596 CTLFLAG_RD, 5597 &txq->ift_processed, "descriptors procesed for clean"); 5598 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 5599 CTLFLAG_RD, 5600 &txq->ift_cleaned, "total cleaned"); 5601 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 5602 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 5603 0, mp_ring_state_handler, "A", "soft ring state"); 5604 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 5605 CTLFLAG_RD, &txq->ift_br->enqueues, 5606 "# of enqueues to the mp_ring for this queue"); 5607 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 5608 CTLFLAG_RD, &txq->ift_br->drops, 5609 "# of drops in the mp_ring for this queue"); 5610 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 5611 CTLFLAG_RD, &txq->ift_br->starts, 5612 "# of normal consumer starts in the mp_ring for this queue"); 5613 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 5614 CTLFLAG_RD, &txq->ift_br->stalls, 5615 "# of consumer stalls in the mp_ring for this queue"); 5616 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 5617 CTLFLAG_RD, &txq->ift_br->restarts, 5618 "# of consumer restarts in the mp_ring for this queue"); 5619 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 5620 CTLFLAG_RD, &txq->ift_br->abdications, 5621 "# of consumer abdications in the mp_ring for this queue"); 5622 } 5623 5624 if (scctx->isc_nrxqsets > 100) 5625 qfmt = "rxq%03d"; 5626 else if (scctx->isc_nrxqsets > 10) 5627 qfmt = "rxq%02d"; 5628 else 5629 qfmt = "rxq%d"; 5630 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 5631 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5632 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5633 CTLFLAG_RD, NULL, "Queue Name"); 5634 queue_list = SYSCTL_CHILDREN(queue_node); 5635 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5636 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 5637 CTLFLAG_RD, 5638 &rxq->ifr_cq_pidx, 1, "Producer Index"); 5639 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 5640 CTLFLAG_RD, 5641 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 5642 } 5643 5644 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 5645 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 5646 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 5647 CTLFLAG_RD, NULL, "freelist Name"); 5648 fl_list = SYSCTL_CHILDREN(fl_node); 5649 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 5650 CTLFLAG_RD, 5651 &fl->ifl_pidx, 1, "Producer Index"); 5652 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 5653 CTLFLAG_RD, 5654 &fl->ifl_cidx, 1, "Consumer Index"); 5655 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 5656 CTLFLAG_RD, 5657 &fl->ifl_credits, 1, "credits available"); 5658 #if MEMORY_LOGGING 5659 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 5660 CTLFLAG_RD, 5661 &fl->ifl_m_enqueued, "mbufs allocated"); 5662 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 5663 CTLFLAG_RD, 5664 &fl->ifl_m_dequeued, "mbufs freed"); 5665 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 5666 CTLFLAG_RD, 5667 &fl->ifl_cl_enqueued, "clusters allocated"); 5668 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 5669 CTLFLAG_RD, 5670 &fl->ifl_cl_dequeued, "clusters freed"); 5671 #endif 5672 5673 } 5674 } 5675 5676 } 5677 5678 #ifndef __NO_STRICT_ALIGNMENT 5679 static struct mbuf * 5680 iflib_fixup_rx(struct mbuf *m) 5681 { 5682 struct mbuf *n; 5683 5684 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 5685 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 5686 m->m_data += ETHER_HDR_LEN; 5687 n = m; 5688 } else { 5689 MGETHDR(n, M_NOWAIT, MT_DATA); 5690 if (n == NULL) { 5691 m_freem(m); 5692 return (NULL); 5693 } 5694 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 5695 m->m_data += ETHER_HDR_LEN; 5696 m->m_len -= ETHER_HDR_LEN; 5697 n->m_len = ETHER_HDR_LEN; 5698 M_MOVE_PKTHDR(n, m); 5699 n->m_next = m; 5700 } 5701 return (n); 5702 } 5703 #endif 5704