1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/jail.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/md5.h> 44 #include <sys/mutex.h> 45 #include <sys/module.h> 46 #include <sys/kobj.h> 47 #include <sys/rman.h> 48 #include <sys/proc.h> 49 #include <sys/sbuf.h> 50 #include <sys/smp.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/syslog.h> 55 #include <sys/taskqueue.h> 56 #include <sys/limits.h> 57 58 #include <net/if.h> 59 #include <net/if_var.h> 60 #include <net/if_types.h> 61 #include <net/if_media.h> 62 #include <net/bpf.h> 63 #include <net/ethernet.h> 64 #include <net/mp_ring.h> 65 #include <net/vnet.h> 66 67 #include <netinet/in.h> 68 #include <netinet/in_pcb.h> 69 #include <netinet/tcp_lro.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/if_ether.h> 72 #include <netinet/ip.h> 73 #include <netinet/ip6.h> 74 #include <netinet/tcp.h> 75 #include <netinet/ip_var.h> 76 #include <netinet/netdump/netdump.h> 77 #include <netinet6/ip6_var.h> 78 79 #include <machine/bus.h> 80 #include <machine/in_cksum.h> 81 82 #include <vm/vm.h> 83 #include <vm/pmap.h> 84 85 #include <dev/led/led.h> 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pci_private.h> 89 90 #include <net/iflib.h> 91 #include <net/iflib_private.h> 92 93 #include "ifdi_if.h" 94 95 #if defined(__i386__) || defined(__amd64__) 96 #include <sys/memdesc.h> 97 #include <machine/bus.h> 98 #include <machine/md_var.h> 99 #include <machine/specialreg.h> 100 #include <x86/include/busdma_impl.h> 101 #include <x86/iommu/busdma_dmar.h> 102 #endif 103 104 #include <sys/bitstring.h> 105 /* 106 * enable accounting of every mbuf as it comes in to and goes out of 107 * iflib's software descriptor references 108 */ 109 #define MEMORY_LOGGING 0 110 /* 111 * Enable mbuf vectors for compressing long mbuf chains 112 */ 113 114 /* 115 * NB: 116 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 117 * we prefetch needs to be determined by the time spent in m_free vis a vis 118 * the cost of a prefetch. This will of course vary based on the workload: 119 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 120 * is quite expensive, thus suggesting very little prefetch. 121 * - small packet forwarding which is just returning a single mbuf to 122 * UMA will typically be very fast vis a vis the cost of a memory 123 * access. 124 */ 125 126 127 /* 128 * File organization: 129 * - private structures 130 * - iflib private utility functions 131 * - ifnet functions 132 * - vlan registry and other exported functions 133 * - iflib public core functions 134 * 135 * 136 */ 137 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 138 139 struct iflib_txq; 140 typedef struct iflib_txq *iflib_txq_t; 141 struct iflib_rxq; 142 typedef struct iflib_rxq *iflib_rxq_t; 143 struct iflib_fl; 144 typedef struct iflib_fl *iflib_fl_t; 145 146 struct iflib_ctx; 147 148 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 149 150 typedef struct iflib_filter_info { 151 driver_filter_t *ifi_filter; 152 void *ifi_filter_arg; 153 struct grouptask *ifi_task; 154 void *ifi_ctx; 155 } *iflib_filter_info_t; 156 157 struct iflib_ctx { 158 KOBJ_FIELDS; 159 /* 160 * Pointer to hardware driver's softc 161 */ 162 void *ifc_softc; 163 device_t ifc_dev; 164 if_t ifc_ifp; 165 166 cpuset_t ifc_cpus; 167 if_shared_ctx_t ifc_sctx; 168 struct if_softc_ctx ifc_softc_ctx; 169 170 struct sx ifc_ctx_sx; 171 struct mtx ifc_state_mtx; 172 173 uint16_t ifc_nhwtxqs; 174 175 iflib_txq_t ifc_txqs; 176 iflib_rxq_t ifc_rxqs; 177 uint32_t ifc_if_flags; 178 uint32_t ifc_flags; 179 uint32_t ifc_max_fl_buf_size; 180 int ifc_in_detach; 181 182 int ifc_link_state; 183 int ifc_link_irq; 184 int ifc_watchdog_events; 185 struct cdev *ifc_led_dev; 186 struct resource *ifc_msix_mem; 187 188 struct if_irq ifc_legacy_irq; 189 struct grouptask ifc_admin_task; 190 struct grouptask ifc_vflr_task; 191 struct iflib_filter_info ifc_filter_info; 192 struct ifmedia ifc_media; 193 194 struct sysctl_oid *ifc_sysctl_node; 195 uint16_t ifc_sysctl_ntxqs; 196 uint16_t ifc_sysctl_nrxqs; 197 uint16_t ifc_sysctl_qs_eq_override; 198 uint16_t ifc_sysctl_rx_budget; 199 200 qidx_t ifc_sysctl_ntxds[8]; 201 qidx_t ifc_sysctl_nrxds[8]; 202 struct if_txrx ifc_txrx; 203 #define isc_txd_encap ifc_txrx.ift_txd_encap 204 #define isc_txd_flush ifc_txrx.ift_txd_flush 205 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 206 #define isc_rxd_available ifc_txrx.ift_rxd_available 207 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 208 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 209 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 210 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 211 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 212 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 213 eventhandler_tag ifc_vlan_attach_event; 214 eventhandler_tag ifc_vlan_detach_event; 215 uint8_t ifc_mac[ETHER_ADDR_LEN]; 216 char ifc_mtx_name[16]; 217 }; 218 219 220 void * 221 iflib_get_softc(if_ctx_t ctx) 222 { 223 224 return (ctx->ifc_softc); 225 } 226 227 device_t 228 iflib_get_dev(if_ctx_t ctx) 229 { 230 231 return (ctx->ifc_dev); 232 } 233 234 if_t 235 iflib_get_ifp(if_ctx_t ctx) 236 { 237 238 return (ctx->ifc_ifp); 239 } 240 241 struct ifmedia * 242 iflib_get_media(if_ctx_t ctx) 243 { 244 245 return (&ctx->ifc_media); 246 } 247 248 uint32_t 249 iflib_get_flags(if_ctx_t ctx) 250 { 251 return (ctx->ifc_flags); 252 } 253 254 void 255 iflib_set_detach(if_ctx_t ctx) 256 { 257 ctx->ifc_in_detach = 1; 258 } 259 260 void 261 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 262 { 263 264 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 265 } 266 267 if_softc_ctx_t 268 iflib_get_softc_ctx(if_ctx_t ctx) 269 { 270 271 return (&ctx->ifc_softc_ctx); 272 } 273 274 if_shared_ctx_t 275 iflib_get_sctx(if_ctx_t ctx) 276 { 277 278 return (ctx->ifc_sctx); 279 } 280 281 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 282 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 283 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 284 285 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 286 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 287 288 #define RX_SW_DESC_MAP_CREATED (1 << 0) 289 #define TX_SW_DESC_MAP_CREATED (1 << 1) 290 #define RX_SW_DESC_INUSE (1 << 3) 291 #define TX_SW_DESC_MAPPED (1 << 4) 292 293 #define M_TOOBIG M_PROTO1 294 295 typedef struct iflib_sw_rx_desc_array { 296 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 297 struct mbuf **ifsd_m; /* pkthdr mbufs */ 298 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 299 uint8_t *ifsd_flags; 300 } iflib_rxsd_array_t; 301 302 typedef struct iflib_sw_tx_desc_array { 303 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 304 struct mbuf **ifsd_m; /* pkthdr mbufs */ 305 uint8_t *ifsd_flags; 306 } if_txsd_vec_t; 307 308 309 /* magic number that should be high enough for any hardware */ 310 #define IFLIB_MAX_TX_SEGS 128 311 /* bnxt supports 64 with hardware LRO enabled */ 312 #define IFLIB_MAX_RX_SEGS 64 313 #define IFLIB_RX_COPY_THRESH 128 314 #define IFLIB_MAX_RX_REFRESH 32 315 /* The minimum descriptors per second before we start coalescing */ 316 #define IFLIB_MIN_DESC_SEC 16384 317 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 318 #define IFLIB_QUEUE_IDLE 0 319 #define IFLIB_QUEUE_HUNG 1 320 #define IFLIB_QUEUE_WORKING 2 321 /* maximum number of txqs that can share an rx interrupt */ 322 #define IFLIB_MAX_TX_SHARED_INTR 4 323 324 /* this should really scale with ring size - this is a fairly arbitrary value */ 325 #define TX_BATCH_SIZE 32 326 327 #define IFLIB_RESTART_BUDGET 8 328 329 330 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 331 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 332 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 333 struct iflib_txq { 334 qidx_t ift_in_use; 335 qidx_t ift_cidx; 336 qidx_t ift_cidx_processed; 337 qidx_t ift_pidx; 338 uint8_t ift_gen; 339 uint8_t ift_br_offset; 340 uint16_t ift_npending; 341 uint16_t ift_db_pending; 342 uint16_t ift_rs_pending; 343 /* implicit pad */ 344 uint8_t ift_txd_size[8]; 345 uint64_t ift_processed; 346 uint64_t ift_cleaned; 347 uint64_t ift_cleaned_prev; 348 #if MEMORY_LOGGING 349 uint64_t ift_enqueued; 350 uint64_t ift_dequeued; 351 #endif 352 uint64_t ift_no_tx_dma_setup; 353 uint64_t ift_no_desc_avail; 354 uint64_t ift_mbuf_defrag_failed; 355 uint64_t ift_mbuf_defrag; 356 uint64_t ift_map_failed; 357 uint64_t ift_txd_encap_efbig; 358 uint64_t ift_pullups; 359 360 struct mtx ift_mtx; 361 struct mtx ift_db_mtx; 362 363 /* constant values */ 364 if_ctx_t ift_ctx; 365 struct ifmp_ring *ift_br; 366 struct grouptask ift_task; 367 qidx_t ift_size; 368 uint16_t ift_id; 369 struct callout ift_timer; 370 371 if_txsd_vec_t ift_sds; 372 uint8_t ift_qstatus; 373 uint8_t ift_closed; 374 uint8_t ift_update_freq; 375 struct iflib_filter_info ift_filter_info; 376 bus_dma_tag_t ift_desc_tag; 377 bus_dma_tag_t ift_tso_desc_tag; 378 iflib_dma_info_t ift_ifdi; 379 #define MTX_NAME_LEN 16 380 char ift_mtx_name[MTX_NAME_LEN]; 381 char ift_db_mtx_name[MTX_NAME_LEN]; 382 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 383 #ifdef IFLIB_DIAGNOSTICS 384 uint64_t ift_cpu_exec_count[256]; 385 #endif 386 } __aligned(CACHE_LINE_SIZE); 387 388 struct iflib_fl { 389 qidx_t ifl_cidx; 390 qidx_t ifl_pidx; 391 qidx_t ifl_credits; 392 uint8_t ifl_gen; 393 uint8_t ifl_rxd_size; 394 #if MEMORY_LOGGING 395 uint64_t ifl_m_enqueued; 396 uint64_t ifl_m_dequeued; 397 uint64_t ifl_cl_enqueued; 398 uint64_t ifl_cl_dequeued; 399 #endif 400 /* implicit pad */ 401 402 bitstr_t *ifl_rx_bitmap; 403 qidx_t ifl_fragidx; 404 /* constant */ 405 qidx_t ifl_size; 406 uint16_t ifl_buf_size; 407 uint16_t ifl_cltype; 408 uma_zone_t ifl_zone; 409 iflib_rxsd_array_t ifl_sds; 410 iflib_rxq_t ifl_rxq; 411 uint8_t ifl_id; 412 bus_dma_tag_t ifl_desc_tag; 413 iflib_dma_info_t ifl_ifdi; 414 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 415 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 416 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 417 } __aligned(CACHE_LINE_SIZE); 418 419 static inline qidx_t 420 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 421 { 422 qidx_t used; 423 424 if (pidx > cidx) 425 used = pidx - cidx; 426 else if (pidx < cidx) 427 used = size - cidx + pidx; 428 else if (gen == 0 && pidx == cidx) 429 used = 0; 430 else if (gen == 1 && pidx == cidx) 431 used = size; 432 else 433 panic("bad state"); 434 435 return (used); 436 } 437 438 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 439 440 #define IDXDIFF(head, tail, wrap) \ 441 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 442 443 struct iflib_rxq { 444 /* If there is a separate completion queue - 445 * these are the cq cidx and pidx. Otherwise 446 * these are unused. 447 */ 448 qidx_t ifr_size; 449 qidx_t ifr_cq_cidx; 450 qidx_t ifr_cq_pidx; 451 uint8_t ifr_cq_gen; 452 uint8_t ifr_fl_offset; 453 454 if_ctx_t ifr_ctx; 455 iflib_fl_t ifr_fl; 456 uint64_t ifr_rx_irq; 457 uint16_t ifr_id; 458 uint8_t ifr_lro_enabled; 459 uint8_t ifr_nfl; 460 uint8_t ifr_ntxqirq; 461 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 462 struct lro_ctrl ifr_lc; 463 struct grouptask ifr_task; 464 struct iflib_filter_info ifr_filter_info; 465 iflib_dma_info_t ifr_ifdi; 466 467 /* dynamically allocate if any drivers need a value substantially larger than this */ 468 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 469 #ifdef IFLIB_DIAGNOSTICS 470 uint64_t ifr_cpu_exec_count[256]; 471 #endif 472 } __aligned(CACHE_LINE_SIZE); 473 474 typedef struct if_rxsd { 475 caddr_t *ifsd_cl; 476 struct mbuf **ifsd_m; 477 iflib_fl_t ifsd_fl; 478 qidx_t ifsd_cidx; 479 } *if_rxsd_t; 480 481 /* multiple of word size */ 482 #ifdef __LP64__ 483 #define PKT_INFO_SIZE 6 484 #define RXD_INFO_SIZE 5 485 #define PKT_TYPE uint64_t 486 #else 487 #define PKT_INFO_SIZE 11 488 #define RXD_INFO_SIZE 8 489 #define PKT_TYPE uint32_t 490 #endif 491 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 492 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 493 494 typedef struct if_pkt_info_pad { 495 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 496 } *if_pkt_info_pad_t; 497 typedef struct if_rxd_info_pad { 498 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 499 } *if_rxd_info_pad_t; 500 501 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 502 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 503 504 505 static inline void 506 pkt_info_zero(if_pkt_info_t pi) 507 { 508 if_pkt_info_pad_t pi_pad; 509 510 pi_pad = (if_pkt_info_pad_t)pi; 511 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 512 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 513 #ifndef __LP64__ 514 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 515 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 516 #endif 517 } 518 519 static device_method_t iflib_pseudo_methods[] = { 520 DEVMETHOD(device_attach, noop_attach), 521 DEVMETHOD(device_detach, iflib_pseudo_detach), 522 DEVMETHOD_END 523 }; 524 525 driver_t iflib_pseudodriver = { 526 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 527 }; 528 529 static inline void 530 rxd_info_zero(if_rxd_info_t ri) 531 { 532 if_rxd_info_pad_t ri_pad; 533 int i; 534 535 ri_pad = (if_rxd_info_pad_t)ri; 536 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 537 ri_pad->rxd_val[i] = 0; 538 ri_pad->rxd_val[i+1] = 0; 539 ri_pad->rxd_val[i+2] = 0; 540 ri_pad->rxd_val[i+3] = 0; 541 } 542 #ifdef __LP64__ 543 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 544 #endif 545 } 546 547 /* 548 * Only allow a single packet to take up most 1/nth of the tx ring 549 */ 550 #define MAX_SINGLE_PACKET_FRACTION 12 551 #define IF_BAD_DMA (bus_addr_t)-1 552 553 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 554 555 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 556 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 557 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 558 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 559 560 561 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 562 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 563 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 564 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 565 566 567 568 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 569 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 570 571 572 /* Our boot-time initialization hook */ 573 static int iflib_module_event_handler(module_t, int, void *); 574 575 static moduledata_t iflib_moduledata = { 576 "iflib", 577 iflib_module_event_handler, 578 NULL 579 }; 580 581 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 582 MODULE_VERSION(iflib, 1); 583 584 MODULE_DEPEND(iflib, pci, 1, 1, 1); 585 MODULE_DEPEND(iflib, ether, 1, 1, 1); 586 587 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 588 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 589 590 #ifndef IFLIB_DEBUG_COUNTERS 591 #ifdef INVARIANTS 592 #define IFLIB_DEBUG_COUNTERS 1 593 #else 594 #define IFLIB_DEBUG_COUNTERS 0 595 #endif /* !INVARIANTS */ 596 #endif 597 598 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 599 "iflib driver parameters"); 600 601 /* 602 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 603 */ 604 static int iflib_min_tx_latency = 0; 605 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 606 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 607 static int iflib_no_tx_batch = 0; 608 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 609 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 610 611 612 #if IFLIB_DEBUG_COUNTERS 613 614 static int iflib_tx_seen; 615 static int iflib_tx_sent; 616 static int iflib_tx_encap; 617 static int iflib_rx_allocs; 618 static int iflib_fl_refills; 619 static int iflib_fl_refills_large; 620 static int iflib_tx_frees; 621 622 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 623 &iflib_tx_seen, 0, "# tx mbufs seen"); 624 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 625 &iflib_tx_sent, 0, "# tx mbufs sent"); 626 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 627 &iflib_tx_encap, 0, "# tx mbufs encapped"); 628 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 629 &iflib_tx_frees, 0, "# tx frees"); 630 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 631 &iflib_rx_allocs, 0, "# rx allocations"); 632 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 633 &iflib_fl_refills, 0, "# refills"); 634 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 635 &iflib_fl_refills_large, 0, "# large refills"); 636 637 638 static int iflib_txq_drain_flushing; 639 static int iflib_txq_drain_oactive; 640 static int iflib_txq_drain_notready; 641 static int iflib_txq_drain_encapfail; 642 643 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 644 &iflib_txq_drain_flushing, 0, "# drain flushes"); 645 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 646 &iflib_txq_drain_oactive, 0, "# drain oactives"); 647 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 648 &iflib_txq_drain_notready, 0, "# drain notready"); 649 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 650 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 651 652 653 static int iflib_encap_load_mbuf_fail; 654 static int iflib_encap_pad_mbuf_fail; 655 static int iflib_encap_txq_avail_fail; 656 static int iflib_encap_txd_encap_fail; 657 658 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 659 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 661 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 663 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 665 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 666 667 static int iflib_task_fn_rxs; 668 static int iflib_rx_intr_enables; 669 static int iflib_fast_intrs; 670 static int iflib_intr_link; 671 static int iflib_intr_msix; 672 static int iflib_rx_unavail; 673 static int iflib_rx_ctx_inactive; 674 static int iflib_rx_zero_len; 675 static int iflib_rx_if_input; 676 static int iflib_rx_mbuf_null; 677 static int iflib_rxd_flush; 678 679 static int iflib_verbose_debug; 680 681 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 682 &iflib_intr_link, 0, "# intr link calls"); 683 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 684 &iflib_intr_msix, 0, "# intr msix calls"); 685 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 686 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 687 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 688 &iflib_rx_intr_enables, 0, "# rx intr enables"); 689 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 690 &iflib_fast_intrs, 0, "# fast_intr calls"); 691 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 692 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 693 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 694 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 695 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 696 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 697 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 698 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 699 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 700 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 701 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 702 &iflib_rxd_flush, 0, "# times rxd_flush called"); 703 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 704 &iflib_verbose_debug, 0, "enable verbose debugging"); 705 706 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 707 static void 708 iflib_debug_reset(void) 709 { 710 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 711 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 712 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 713 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 714 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 715 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 716 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 717 iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 718 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 719 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 720 } 721 722 #else 723 #define DBG_COUNTER_INC(name) 724 static void iflib_debug_reset(void) {} 725 #endif 726 727 #define IFLIB_DEBUG 0 728 729 static void iflib_tx_structures_free(if_ctx_t ctx); 730 static void iflib_rx_structures_free(if_ctx_t ctx); 731 static int iflib_queues_alloc(if_ctx_t ctx); 732 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 733 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 734 static int iflib_qset_structures_setup(if_ctx_t ctx); 735 static int iflib_msix_init(if_ctx_t ctx); 736 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 737 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 738 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 739 static int iflib_register(if_ctx_t); 740 static void iflib_init_locked(if_ctx_t ctx); 741 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 742 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 743 static void iflib_ifmp_purge(iflib_txq_t txq); 744 static void _iflib_pre_assert(if_softc_ctx_t scctx); 745 static void iflib_if_init_locked(if_ctx_t ctx); 746 #ifndef __NO_STRICT_ALIGNMENT 747 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 748 #endif 749 750 NETDUMP_DEFINE(iflib); 751 752 #ifdef DEV_NETMAP 753 #include <sys/selinfo.h> 754 #include <net/netmap.h> 755 #include <dev/netmap/netmap_kern.h> 756 757 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 758 759 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 760 761 /* 762 * device-specific sysctl variables: 763 * 764 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 765 * During regular operations the CRC is stripped, but on some 766 * hardware reception of frames not multiple of 64 is slower, 767 * so using crcstrip=0 helps in benchmarks. 768 * 769 * iflib_rx_miss, iflib_rx_miss_bufs: 770 * count packets that might be missed due to lost interrupts. 771 */ 772 SYSCTL_DECL(_dev_netmap); 773 /* 774 * The xl driver by default strips CRCs and we do not override it. 775 */ 776 777 int iflib_crcstrip = 1; 778 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 779 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 780 781 int iflib_rx_miss, iflib_rx_miss_bufs; 782 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 783 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 784 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 785 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 786 787 /* 788 * Register/unregister. We are already under netmap lock. 789 * Only called on the first register or the last unregister. 790 */ 791 static int 792 iflib_netmap_register(struct netmap_adapter *na, int onoff) 793 { 794 struct ifnet *ifp = na->ifp; 795 if_ctx_t ctx = ifp->if_softc; 796 int status; 797 798 CTX_LOCK(ctx); 799 IFDI_INTR_DISABLE(ctx); 800 801 /* Tell the stack that the interface is no longer active */ 802 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 803 804 if (!CTX_IS_VF(ctx)) 805 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 806 807 /* enable or disable flags and callbacks in na and ifp */ 808 if (onoff) { 809 nm_set_native_flags(na); 810 } else { 811 nm_clear_native_flags(na); 812 } 813 iflib_stop(ctx); 814 iflib_init_locked(ctx); 815 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 816 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 817 if (status) 818 nm_clear_native_flags(na); 819 CTX_UNLOCK(ctx); 820 return (status); 821 } 822 823 static int 824 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 825 { 826 struct netmap_adapter *na = kring->na; 827 u_int const lim = kring->nkr_num_slots - 1; 828 u_int head = kring->rhead; 829 struct netmap_ring *ring = kring->ring; 830 bus_dmamap_t *map; 831 struct if_rxd_update iru; 832 if_ctx_t ctx = rxq->ifr_ctx; 833 iflib_fl_t fl = &rxq->ifr_fl[0]; 834 uint32_t refill_pidx, nic_i; 835 836 if (nm_i == head && __predict_true(!init)) 837 return 0; 838 iru_init(&iru, rxq, 0 /* flid */); 839 map = fl->ifl_sds.ifsd_map; 840 refill_pidx = netmap_idx_k2n(kring, nm_i); 841 /* 842 * IMPORTANT: we must leave one free slot in the ring, 843 * so move head back by one unit 844 */ 845 head = nm_prev(head, lim); 846 nic_i = UINT_MAX; 847 while (nm_i != head) { 848 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 849 struct netmap_slot *slot = &ring->slot[nm_i]; 850 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 851 uint32_t nic_i_dma = refill_pidx; 852 nic_i = netmap_idx_k2n(kring, nm_i); 853 854 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 855 856 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 857 return netmap_ring_reinit(kring); 858 859 fl->ifl_vm_addrs[tmp_pidx] = addr; 860 if (__predict_false(init) && map) { 861 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 862 } else if (map && (slot->flags & NS_BUF_CHANGED)) { 863 /* buffer has changed, reload map */ 864 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 865 } 866 slot->flags &= ~NS_BUF_CHANGED; 867 868 nm_i = nm_next(nm_i, lim); 869 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 870 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 871 continue; 872 873 iru.iru_pidx = refill_pidx; 874 iru.iru_count = tmp_pidx+1; 875 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 876 877 refill_pidx = nic_i; 878 if (map == NULL) 879 continue; 880 881 for (int n = 0; n < iru.iru_count; n++) { 882 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma], 883 BUS_DMASYNC_PREREAD); 884 /* XXX - change this to not use the netmap func*/ 885 nic_i_dma = nm_next(nic_i_dma, lim); 886 } 887 } 888 } 889 kring->nr_hwcur = head; 890 891 if (map) 892 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 893 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 894 if (__predict_true(nic_i != UINT_MAX)) 895 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 896 return (0); 897 } 898 899 /* 900 * Reconcile kernel and user view of the transmit ring. 901 * 902 * All information is in the kring. 903 * Userspace wants to send packets up to the one before kring->rhead, 904 * kernel knows kring->nr_hwcur is the first unsent packet. 905 * 906 * Here we push packets out (as many as possible), and possibly 907 * reclaim buffers from previously completed transmission. 908 * 909 * The caller (netmap) guarantees that there is only one instance 910 * running at any time. Any interference with other driver 911 * methods should be handled by the individual drivers. 912 */ 913 static int 914 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 915 { 916 struct netmap_adapter *na = kring->na; 917 struct ifnet *ifp = na->ifp; 918 struct netmap_ring *ring = kring->ring; 919 u_int nm_i; /* index into the netmap ring */ 920 u_int nic_i; /* index into the NIC ring */ 921 u_int n; 922 u_int const lim = kring->nkr_num_slots - 1; 923 u_int const head = kring->rhead; 924 struct if_pkt_info pi; 925 926 /* 927 * interrupts on every tx packet are expensive so request 928 * them every half ring, or where NS_REPORT is set 929 */ 930 u_int report_frequency = kring->nkr_num_slots >> 1; 931 /* device-specific */ 932 if_ctx_t ctx = ifp->if_softc; 933 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 934 935 if (txq->ift_sds.ifsd_map) 936 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 937 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 938 939 940 /* 941 * First part: process new packets to send. 942 * nm_i is the current index in the netmap ring, 943 * nic_i is the corresponding index in the NIC ring. 944 * 945 * If we have packets to send (nm_i != head) 946 * iterate over the netmap ring, fetch length and update 947 * the corresponding slot in the NIC ring. Some drivers also 948 * need to update the buffer's physical address in the NIC slot 949 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 950 * 951 * The netmap_reload_map() calls is especially expensive, 952 * even when (as in this case) the tag is 0, so do only 953 * when the buffer has actually changed. 954 * 955 * If possible do not set the report/intr bit on all slots, 956 * but only a few times per ring or when NS_REPORT is set. 957 * 958 * Finally, on 10G and faster drivers, it might be useful 959 * to prefetch the next slot and txr entry. 960 */ 961 962 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 963 if (nm_i != head) { /* we have new packets to send */ 964 pkt_info_zero(&pi); 965 pi.ipi_segs = txq->ift_segs; 966 pi.ipi_qsidx = kring->ring_id; 967 nic_i = netmap_idx_k2n(kring, nm_i); 968 969 __builtin_prefetch(&ring->slot[nm_i]); 970 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 971 if (txq->ift_sds.ifsd_map) 972 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 973 974 for (n = 0; nm_i != head; n++) { 975 struct netmap_slot *slot = &ring->slot[nm_i]; 976 u_int len = slot->len; 977 uint64_t paddr; 978 void *addr = PNMB(na, slot, &paddr); 979 int flags = (slot->flags & NS_REPORT || 980 nic_i == 0 || nic_i == report_frequency) ? 981 IPI_TX_INTR : 0; 982 983 /* device-specific */ 984 pi.ipi_len = len; 985 pi.ipi_segs[0].ds_addr = paddr; 986 pi.ipi_segs[0].ds_len = len; 987 pi.ipi_nsegs = 1; 988 pi.ipi_ndescs = 0; 989 pi.ipi_pidx = nic_i; 990 pi.ipi_flags = flags; 991 992 /* Fill the slot in the NIC ring. */ 993 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 994 995 /* prefetch for next round */ 996 __builtin_prefetch(&ring->slot[nm_i + 1]); 997 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 998 if (txq->ift_sds.ifsd_map) { 999 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1000 1001 NM_CHECK_ADDR_LEN(na, addr, len); 1002 1003 if (slot->flags & NS_BUF_CHANGED) { 1004 /* buffer has changed, reload map */ 1005 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 1006 } 1007 /* make sure changes to the buffer are synced */ 1008 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 1009 BUS_DMASYNC_PREWRITE); 1010 } 1011 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1012 nm_i = nm_next(nm_i, lim); 1013 nic_i = nm_next(nic_i, lim); 1014 } 1015 kring->nr_hwcur = head; 1016 1017 /* synchronize the NIC ring */ 1018 if (txq->ift_sds.ifsd_map) 1019 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 1020 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1021 1022 /* (re)start the tx unit up to slot nic_i (excluded) */ 1023 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1024 } 1025 1026 /* 1027 * Second part: reclaim buffers for completed transmissions. 1028 * 1029 * If there are unclaimed buffers, attempt to reclaim them. 1030 * If none are reclaimed, and TX IRQs are not in use, do an initial 1031 * minimal delay, then trigger the tx handler which will spin in the 1032 * group task queue. 1033 */ 1034 if (kring->nr_hwtail != nm_prev(head, lim)) { 1035 if (iflib_tx_credits_update(ctx, txq)) { 1036 /* some tx completed, increment avail */ 1037 nic_i = txq->ift_cidx_processed; 1038 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1039 } 1040 else { 1041 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1042 DELAY(1); 1043 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txq->ift_id].ift_task); 1044 } 1045 } 1046 } 1047 return (0); 1048 } 1049 1050 /* 1051 * Reconcile kernel and user view of the receive ring. 1052 * Same as for the txsync, this routine must be efficient. 1053 * The caller guarantees a single invocations, but races against 1054 * the rest of the driver should be handled here. 1055 * 1056 * On call, kring->rhead is the first packet that userspace wants 1057 * to keep, and kring->rcur is the wakeup point. 1058 * The kernel has previously reported packets up to kring->rtail. 1059 * 1060 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1061 * of whether or not we received an interrupt. 1062 */ 1063 static int 1064 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1065 { 1066 struct netmap_adapter *na = kring->na; 1067 struct netmap_ring *ring = kring->ring; 1068 uint32_t nm_i; /* index into the netmap ring */ 1069 uint32_t nic_i; /* index into the NIC ring */ 1070 u_int i, n; 1071 u_int const lim = kring->nkr_num_slots - 1; 1072 u_int const head = netmap_idx_n2k(kring, kring->rhead); 1073 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1074 struct if_rxd_info ri; 1075 1076 struct ifnet *ifp = na->ifp; 1077 if_ctx_t ctx = ifp->if_softc; 1078 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1079 iflib_fl_t fl = rxq->ifr_fl; 1080 if (head > lim) 1081 return netmap_ring_reinit(kring); 1082 1083 /* XXX check sync modes */ 1084 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1085 if (fl->ifl_sds.ifsd_map == NULL) 1086 continue; 1087 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 1088 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1089 } 1090 /* 1091 * First part: import newly received packets. 1092 * 1093 * nm_i is the index of the next free slot in the netmap ring, 1094 * nic_i is the index of the next received packet in the NIC ring, 1095 * and they may differ in case if_init() has been called while 1096 * in netmap mode. For the receive ring we have 1097 * 1098 * nic_i = rxr->next_check; 1099 * nm_i = kring->nr_hwtail (previous) 1100 * and 1101 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1102 * 1103 * rxr->next_check is set to 0 on a ring reinit 1104 */ 1105 if (netmap_no_pendintr || force_update) { 1106 int crclen = iflib_crcstrip ? 0 : 4; 1107 int error, avail; 1108 1109 for (i = 0; i < rxq->ifr_nfl; i++) { 1110 fl = &rxq->ifr_fl[i]; 1111 nic_i = fl->ifl_cidx; 1112 nm_i = netmap_idx_n2k(kring, nic_i); 1113 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 1114 for (n = 0; avail > 0; n++, avail--) { 1115 rxd_info_zero(&ri); 1116 ri.iri_frags = rxq->ifr_frags; 1117 ri.iri_qsidx = kring->ring_id; 1118 ri.iri_ifp = ctx->ifc_ifp; 1119 ri.iri_cidx = nic_i; 1120 1121 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1122 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1123 ring->slot[nm_i].flags = 0; 1124 if (fl->ifl_sds.ifsd_map) 1125 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1126 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1127 nm_i = nm_next(nm_i, lim); 1128 nic_i = nm_next(nic_i, lim); 1129 } 1130 if (n) { /* update the state variables */ 1131 if (netmap_no_pendintr && !force_update) { 1132 /* diagnostics */ 1133 iflib_rx_miss ++; 1134 iflib_rx_miss_bufs += n; 1135 } 1136 fl->ifl_cidx = nic_i; 1137 kring->nr_hwtail = netmap_idx_k2n(kring, nm_i); 1138 } 1139 kring->nr_kflags &= ~NKR_PENDINTR; 1140 } 1141 } 1142 /* 1143 * Second part: skip past packets that userspace has released. 1144 * (kring->nr_hwcur to head excluded), 1145 * and make the buffers available for reception. 1146 * As usual nm_i is the index in the netmap ring, 1147 * nic_i is the index in the NIC ring, and 1148 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1149 */ 1150 /* XXX not sure how this will work with multiple free lists */ 1151 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 1152 1153 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1154 } 1155 1156 static void 1157 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1158 { 1159 struct ifnet *ifp = na->ifp; 1160 if_ctx_t ctx = ifp->if_softc; 1161 1162 CTX_LOCK(ctx); 1163 if (onoff) { 1164 IFDI_INTR_ENABLE(ctx); 1165 } else { 1166 IFDI_INTR_DISABLE(ctx); 1167 } 1168 CTX_UNLOCK(ctx); 1169 } 1170 1171 1172 static int 1173 iflib_netmap_attach(if_ctx_t ctx) 1174 { 1175 struct netmap_adapter na; 1176 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1177 1178 bzero(&na, sizeof(na)); 1179 1180 na.ifp = ctx->ifc_ifp; 1181 na.na_flags = NAF_BDG_MAYSLEEP; 1182 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1183 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1184 1185 na.num_tx_desc = scctx->isc_ntxd[0]; 1186 na.num_rx_desc = scctx->isc_nrxd[0]; 1187 na.nm_txsync = iflib_netmap_txsync; 1188 na.nm_rxsync = iflib_netmap_rxsync; 1189 na.nm_register = iflib_netmap_register; 1190 na.nm_intr = iflib_netmap_intr; 1191 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1192 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1193 return (netmap_attach(&na)); 1194 } 1195 1196 static void 1197 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1198 { 1199 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1200 struct netmap_slot *slot; 1201 1202 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1203 if (slot == NULL) 1204 return; 1205 if (txq->ift_sds.ifsd_map == NULL) 1206 return; 1207 1208 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1209 1210 /* 1211 * In netmap mode, set the map for the packet buffer. 1212 * NOTE: Some drivers (not this one) also need to set 1213 * the physical buffer address in the NIC ring. 1214 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1215 * netmap slot index, si 1216 */ 1217 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1218 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1219 } 1220 } 1221 1222 static void 1223 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1224 { 1225 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1226 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1227 struct netmap_slot *slot; 1228 uint32_t nm_i; 1229 1230 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1231 if (slot == NULL) 1232 return; 1233 nm_i = netmap_idx_n2k(kring, 0); 1234 netmap_fl_refill(rxq, kring, nm_i, true); 1235 } 1236 1237 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1238 1239 #else 1240 #define iflib_netmap_txq_init(ctx, txq) 1241 #define iflib_netmap_rxq_init(ctx, rxq) 1242 #define iflib_netmap_detach(ifp) 1243 1244 #define iflib_netmap_attach(ctx) (0) 1245 #define netmap_rx_irq(ifp, qid, budget) (0) 1246 #define netmap_tx_irq(ifp, qid) do {} while (0) 1247 1248 #endif 1249 1250 #if defined(__i386__) || defined(__amd64__) 1251 static __inline void 1252 prefetch(void *x) 1253 { 1254 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1255 } 1256 static __inline void 1257 prefetch2cachelines(void *x) 1258 { 1259 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1260 #if (CACHE_LINE_SIZE < 128) 1261 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1262 #endif 1263 } 1264 #else 1265 #define prefetch(x) 1266 #define prefetch2cachelines(x) 1267 #endif 1268 1269 static void 1270 iflib_gen_mac(if_ctx_t ctx) 1271 { 1272 struct thread *td; 1273 MD5_CTX mdctx; 1274 char uuid[HOSTUUIDLEN+1]; 1275 char buf[HOSTUUIDLEN+16]; 1276 uint8_t *mac; 1277 unsigned char digest[16]; 1278 1279 td = curthread; 1280 mac = ctx->ifc_mac; 1281 uuid[HOSTUUIDLEN] = 0; 1282 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN); 1283 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev)); 1284 /* 1285 * Generate a pseudo-random, deterministic MAC 1286 * address based on the UUID and unit number. 1287 * The FreeBSD Foundation OUI of 58-9C-FC is used. 1288 */ 1289 MD5Init(&mdctx); 1290 MD5Update(&mdctx, buf, strlen(buf)); 1291 MD5Final(digest, &mdctx); 1292 1293 mac[0] = 0x58; 1294 mac[1] = 0x9C; 1295 mac[2] = 0xFC; 1296 mac[3] = digest[0]; 1297 mac[4] = digest[1]; 1298 mac[5] = digest[2]; 1299 } 1300 1301 static void 1302 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1303 { 1304 iflib_fl_t fl; 1305 1306 fl = &rxq->ifr_fl[flid]; 1307 iru->iru_paddrs = fl->ifl_bus_addrs; 1308 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1309 iru->iru_idxs = fl->ifl_rxd_idxs; 1310 iru->iru_qsidx = rxq->ifr_id; 1311 iru->iru_buf_size = fl->ifl_buf_size; 1312 iru->iru_flidx = fl->ifl_id; 1313 } 1314 1315 static void 1316 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1317 { 1318 if (err) 1319 return; 1320 *(bus_addr_t *) arg = segs[0].ds_addr; 1321 } 1322 1323 int 1324 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1325 { 1326 int err; 1327 if_shared_ctx_t sctx = ctx->ifc_sctx; 1328 device_t dev = ctx->ifc_dev; 1329 1330 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1331 1332 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1333 sctx->isc_q_align, 0, /* alignment, bounds */ 1334 BUS_SPACE_MAXADDR, /* lowaddr */ 1335 BUS_SPACE_MAXADDR, /* highaddr */ 1336 NULL, NULL, /* filter, filterarg */ 1337 size, /* maxsize */ 1338 1, /* nsegments */ 1339 size, /* maxsegsize */ 1340 BUS_DMA_ALLOCNOW, /* flags */ 1341 NULL, /* lockfunc */ 1342 NULL, /* lockarg */ 1343 &dma->idi_tag); 1344 if (err) { 1345 device_printf(dev, 1346 "%s: bus_dma_tag_create failed: %d\n", 1347 __func__, err); 1348 goto fail_0; 1349 } 1350 1351 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1352 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1353 if (err) { 1354 device_printf(dev, 1355 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1356 __func__, (uintmax_t)size, err); 1357 goto fail_1; 1358 } 1359 1360 dma->idi_paddr = IF_BAD_DMA; 1361 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1362 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1363 if (err || dma->idi_paddr == IF_BAD_DMA) { 1364 device_printf(dev, 1365 "%s: bus_dmamap_load failed: %d\n", 1366 __func__, err); 1367 goto fail_2; 1368 } 1369 1370 dma->idi_size = size; 1371 return (0); 1372 1373 fail_2: 1374 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1375 fail_1: 1376 bus_dma_tag_destroy(dma->idi_tag); 1377 fail_0: 1378 dma->idi_tag = NULL; 1379 1380 return (err); 1381 } 1382 1383 int 1384 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1385 { 1386 int i, err; 1387 iflib_dma_info_t *dmaiter; 1388 1389 dmaiter = dmalist; 1390 for (i = 0; i < count; i++, dmaiter++) { 1391 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1392 break; 1393 } 1394 if (err) 1395 iflib_dma_free_multi(dmalist, i); 1396 return (err); 1397 } 1398 1399 void 1400 iflib_dma_free(iflib_dma_info_t dma) 1401 { 1402 if (dma->idi_tag == NULL) 1403 return; 1404 if (dma->idi_paddr != IF_BAD_DMA) { 1405 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1406 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1407 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1408 dma->idi_paddr = IF_BAD_DMA; 1409 } 1410 if (dma->idi_vaddr != NULL) { 1411 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1412 dma->idi_vaddr = NULL; 1413 } 1414 bus_dma_tag_destroy(dma->idi_tag); 1415 dma->idi_tag = NULL; 1416 } 1417 1418 void 1419 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1420 { 1421 int i; 1422 iflib_dma_info_t *dmaiter = dmalist; 1423 1424 for (i = 0; i < count; i++, dmaiter++) 1425 iflib_dma_free(*dmaiter); 1426 } 1427 1428 #ifdef EARLY_AP_STARTUP 1429 static const int iflib_started = 1; 1430 #else 1431 /* 1432 * We used to abuse the smp_started flag to decide if the queues have been 1433 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1434 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1435 * is set. Run a SYSINIT() strictly after that to just set a usable 1436 * completion flag. 1437 */ 1438 1439 static int iflib_started; 1440 1441 static void 1442 iflib_record_started(void *arg) 1443 { 1444 iflib_started = 1; 1445 } 1446 1447 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1448 iflib_record_started, NULL); 1449 #endif 1450 1451 static int 1452 iflib_fast_intr(void *arg) 1453 { 1454 iflib_filter_info_t info = arg; 1455 struct grouptask *gtask = info->ifi_task; 1456 if (!iflib_started) 1457 return (FILTER_HANDLED); 1458 1459 DBG_COUNTER_INC(fast_intrs); 1460 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1461 return (FILTER_HANDLED); 1462 1463 GROUPTASK_ENQUEUE(gtask); 1464 return (FILTER_HANDLED); 1465 } 1466 1467 static int 1468 iflib_fast_intr_rxtx(void *arg) 1469 { 1470 iflib_filter_info_t info = arg; 1471 struct grouptask *gtask = info->ifi_task; 1472 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1473 if_ctx_t ctx = NULL;; 1474 int i, cidx; 1475 1476 if (!iflib_started) 1477 return (FILTER_HANDLED); 1478 1479 DBG_COUNTER_INC(fast_intrs); 1480 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1481 return (FILTER_HANDLED); 1482 1483 MPASS(rxq->ifr_ntxqirq); 1484 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1485 qidx_t txqid = rxq->ifr_txqid[i]; 1486 1487 ctx = rxq->ifr_ctx; 1488 1489 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1490 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1491 continue; 1492 } 1493 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1494 } 1495 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1496 cidx = rxq->ifr_cq_cidx; 1497 else 1498 cidx = rxq->ifr_fl[0].ifl_cidx; 1499 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1500 GROUPTASK_ENQUEUE(gtask); 1501 else 1502 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1503 return (FILTER_HANDLED); 1504 } 1505 1506 1507 static int 1508 iflib_fast_intr_ctx(void *arg) 1509 { 1510 iflib_filter_info_t info = arg; 1511 struct grouptask *gtask = info->ifi_task; 1512 1513 if (!iflib_started) 1514 return (FILTER_HANDLED); 1515 1516 DBG_COUNTER_INC(fast_intrs); 1517 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1518 return (FILTER_HANDLED); 1519 1520 GROUPTASK_ENQUEUE(gtask); 1521 return (FILTER_HANDLED); 1522 } 1523 1524 static int 1525 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1526 driver_filter_t filter, driver_intr_t handler, void *arg, 1527 const char *name) 1528 { 1529 int rc, flags; 1530 struct resource *res; 1531 void *tag = NULL; 1532 device_t dev = ctx->ifc_dev; 1533 1534 flags = RF_ACTIVE; 1535 if (ctx->ifc_flags & IFC_LEGACY) 1536 flags |= RF_SHAREABLE; 1537 MPASS(rid < 512); 1538 irq->ii_rid = rid; 1539 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1540 if (res == NULL) { 1541 device_printf(dev, 1542 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1543 return (ENOMEM); 1544 } 1545 irq->ii_res = res; 1546 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1547 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1548 filter, handler, arg, &tag); 1549 if (rc != 0) { 1550 device_printf(dev, 1551 "failed to setup interrupt for rid %d, name %s: %d\n", 1552 rid, name ? name : "unknown", rc); 1553 return (rc); 1554 } else if (name) 1555 bus_describe_intr(dev, res, tag, "%s", name); 1556 1557 irq->ii_tag = tag; 1558 return (0); 1559 } 1560 1561 1562 /********************************************************************* 1563 * 1564 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1565 * the information needed to transmit a packet on the wire. This is 1566 * called only once at attach, setup is done every reset. 1567 * 1568 **********************************************************************/ 1569 1570 static int 1571 iflib_txsd_alloc(iflib_txq_t txq) 1572 { 1573 if_ctx_t ctx = txq->ift_ctx; 1574 if_shared_ctx_t sctx = ctx->ifc_sctx; 1575 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1576 device_t dev = ctx->ifc_dev; 1577 int err, nsegments, ntsosegments; 1578 1579 nsegments = scctx->isc_tx_nsegments; 1580 ntsosegments = scctx->isc_tx_tso_segments_max; 1581 MPASS(scctx->isc_ntxd[0] > 0); 1582 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1583 MPASS(nsegments > 0); 1584 MPASS(ntsosegments > 0); 1585 /* 1586 * Setup DMA descriptor areas. 1587 */ 1588 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1589 1, 0, /* alignment, bounds */ 1590 BUS_SPACE_MAXADDR, /* lowaddr */ 1591 BUS_SPACE_MAXADDR, /* highaddr */ 1592 NULL, NULL, /* filter, filterarg */ 1593 sctx->isc_tx_maxsize, /* maxsize */ 1594 nsegments, /* nsegments */ 1595 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1596 0, /* flags */ 1597 NULL, /* lockfunc */ 1598 NULL, /* lockfuncarg */ 1599 &txq->ift_desc_tag))) { 1600 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1601 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1602 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1603 goto fail; 1604 } 1605 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1606 1, 0, /* alignment, bounds */ 1607 BUS_SPACE_MAXADDR, /* lowaddr */ 1608 BUS_SPACE_MAXADDR, /* highaddr */ 1609 NULL, NULL, /* filter, filterarg */ 1610 scctx->isc_tx_tso_size_max, /* maxsize */ 1611 ntsosegments, /* nsegments */ 1612 scctx->isc_tx_tso_segsize_max, /* maxsegsize */ 1613 0, /* flags */ 1614 NULL, /* lockfunc */ 1615 NULL, /* lockfuncarg */ 1616 &txq->ift_tso_desc_tag))) { 1617 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1618 1619 goto fail; 1620 } 1621 if (!(txq->ift_sds.ifsd_flags = 1622 (uint8_t *) malloc(sizeof(uint8_t) * 1623 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1624 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1625 err = ENOMEM; 1626 goto fail; 1627 } 1628 if (!(txq->ift_sds.ifsd_m = 1629 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1630 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1631 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1632 err = ENOMEM; 1633 goto fail; 1634 } 1635 1636 /* Create the descriptor buffer dma maps */ 1637 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1638 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1639 return (0); 1640 1641 if (!(txq->ift_sds.ifsd_map = 1642 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1643 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1644 err = ENOMEM; 1645 goto fail; 1646 } 1647 1648 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1649 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1650 if (err != 0) { 1651 device_printf(dev, "Unable to create TX DMA map\n"); 1652 goto fail; 1653 } 1654 } 1655 #endif 1656 return (0); 1657 fail: 1658 /* We free all, it handles case where we are in the middle */ 1659 iflib_tx_structures_free(ctx); 1660 return (err); 1661 } 1662 1663 static void 1664 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1665 { 1666 bus_dmamap_t map; 1667 1668 map = NULL; 1669 if (txq->ift_sds.ifsd_map != NULL) 1670 map = txq->ift_sds.ifsd_map[i]; 1671 if (map != NULL) { 1672 bus_dmamap_unload(txq->ift_desc_tag, map); 1673 bus_dmamap_destroy(txq->ift_desc_tag, map); 1674 txq->ift_sds.ifsd_map[i] = NULL; 1675 } 1676 } 1677 1678 static void 1679 iflib_txq_destroy(iflib_txq_t txq) 1680 { 1681 if_ctx_t ctx = txq->ift_ctx; 1682 1683 for (int i = 0; i < txq->ift_size; i++) 1684 iflib_txsd_destroy(ctx, txq, i); 1685 if (txq->ift_sds.ifsd_map != NULL) { 1686 free(txq->ift_sds.ifsd_map, M_IFLIB); 1687 txq->ift_sds.ifsd_map = NULL; 1688 } 1689 if (txq->ift_sds.ifsd_m != NULL) { 1690 free(txq->ift_sds.ifsd_m, M_IFLIB); 1691 txq->ift_sds.ifsd_m = NULL; 1692 } 1693 if (txq->ift_sds.ifsd_flags != NULL) { 1694 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1695 txq->ift_sds.ifsd_flags = NULL; 1696 } 1697 if (txq->ift_desc_tag != NULL) { 1698 bus_dma_tag_destroy(txq->ift_desc_tag); 1699 txq->ift_desc_tag = NULL; 1700 } 1701 if (txq->ift_tso_desc_tag != NULL) { 1702 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1703 txq->ift_tso_desc_tag = NULL; 1704 } 1705 } 1706 1707 static void 1708 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1709 { 1710 struct mbuf **mp; 1711 1712 mp = &txq->ift_sds.ifsd_m[i]; 1713 if (*mp == NULL) 1714 return; 1715 1716 if (txq->ift_sds.ifsd_map != NULL) { 1717 bus_dmamap_sync(txq->ift_desc_tag, 1718 txq->ift_sds.ifsd_map[i], 1719 BUS_DMASYNC_POSTWRITE); 1720 bus_dmamap_unload(txq->ift_desc_tag, 1721 txq->ift_sds.ifsd_map[i]); 1722 } 1723 m_free(*mp); 1724 DBG_COUNTER_INC(tx_frees); 1725 *mp = NULL; 1726 } 1727 1728 static int 1729 iflib_txq_setup(iflib_txq_t txq) 1730 { 1731 if_ctx_t ctx = txq->ift_ctx; 1732 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1733 iflib_dma_info_t di; 1734 int i; 1735 1736 /* Set number of descriptors available */ 1737 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1738 /* XXX make configurable */ 1739 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1740 1741 /* Reset indices */ 1742 txq->ift_cidx_processed = 0; 1743 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1744 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1745 1746 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1747 bzero((void *)di->idi_vaddr, di->idi_size); 1748 1749 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1750 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1751 bus_dmamap_sync(di->idi_tag, di->idi_map, 1752 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1753 return (0); 1754 } 1755 1756 /********************************************************************* 1757 * 1758 * Allocate memory for rx_buffer structures. Since we use one 1759 * rx_buffer per received packet, the maximum number of rx_buffer's 1760 * that we'll need is equal to the number of receive descriptors 1761 * that we've allocated. 1762 * 1763 **********************************************************************/ 1764 static int 1765 iflib_rxsd_alloc(iflib_rxq_t rxq) 1766 { 1767 if_ctx_t ctx = rxq->ifr_ctx; 1768 if_shared_ctx_t sctx = ctx->ifc_sctx; 1769 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1770 device_t dev = ctx->ifc_dev; 1771 iflib_fl_t fl; 1772 int err; 1773 1774 MPASS(scctx->isc_nrxd[0] > 0); 1775 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1776 1777 fl = rxq->ifr_fl; 1778 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1779 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1780 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1781 1, 0, /* alignment, bounds */ 1782 BUS_SPACE_MAXADDR, /* lowaddr */ 1783 BUS_SPACE_MAXADDR, /* highaddr */ 1784 NULL, NULL, /* filter, filterarg */ 1785 sctx->isc_rx_maxsize, /* maxsize */ 1786 sctx->isc_rx_nsegments, /* nsegments */ 1787 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1788 0, /* flags */ 1789 NULL, /* lockfunc */ 1790 NULL, /* lockarg */ 1791 &fl->ifl_desc_tag); 1792 if (err) { 1793 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1794 __func__, err); 1795 goto fail; 1796 } 1797 if (!(fl->ifl_sds.ifsd_flags = 1798 (uint8_t *) malloc(sizeof(uint8_t) * 1799 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1800 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1801 err = ENOMEM; 1802 goto fail; 1803 } 1804 if (!(fl->ifl_sds.ifsd_m = 1805 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1806 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1807 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1808 err = ENOMEM; 1809 goto fail; 1810 } 1811 if (!(fl->ifl_sds.ifsd_cl = 1812 (caddr_t *) malloc(sizeof(caddr_t) * 1813 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1814 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1815 err = ENOMEM; 1816 goto fail; 1817 } 1818 1819 /* Create the descriptor buffer dma maps */ 1820 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1821 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1822 continue; 1823 1824 if (!(fl->ifl_sds.ifsd_map = 1825 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1826 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1827 err = ENOMEM; 1828 goto fail; 1829 } 1830 1831 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1832 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1833 if (err != 0) { 1834 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1835 goto fail; 1836 } 1837 } 1838 #endif 1839 } 1840 return (0); 1841 1842 fail: 1843 iflib_rx_structures_free(ctx); 1844 return (err); 1845 } 1846 1847 1848 /* 1849 * Internal service routines 1850 */ 1851 1852 struct rxq_refill_cb_arg { 1853 int error; 1854 bus_dma_segment_t seg; 1855 int nseg; 1856 }; 1857 1858 static void 1859 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1860 { 1861 struct rxq_refill_cb_arg *cb_arg = arg; 1862 1863 cb_arg->error = error; 1864 cb_arg->seg = segs[0]; 1865 cb_arg->nseg = nseg; 1866 } 1867 1868 1869 #ifdef ACPI_DMAR 1870 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1871 #else 1872 #define IS_DMAR(ctx) (0) 1873 #endif 1874 1875 /** 1876 * rxq_refill - refill an rxq free-buffer list 1877 * @ctx: the iflib context 1878 * @rxq: the free-list to refill 1879 * @n: the number of new buffers to allocate 1880 * 1881 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1882 * The caller must assure that @n does not exceed the queue's capacity. 1883 */ 1884 static void 1885 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1886 { 1887 struct mbuf *m; 1888 int idx, frag_idx = fl->ifl_fragidx; 1889 int pidx = fl->ifl_pidx; 1890 caddr_t cl, *sd_cl; 1891 struct mbuf **sd_m; 1892 uint8_t *sd_flags; 1893 struct if_rxd_update iru; 1894 bus_dmamap_t *sd_map; 1895 int n, i = 0; 1896 uint64_t bus_addr; 1897 int err; 1898 qidx_t credits; 1899 1900 sd_m = fl->ifl_sds.ifsd_m; 1901 sd_map = fl->ifl_sds.ifsd_map; 1902 sd_cl = fl->ifl_sds.ifsd_cl; 1903 sd_flags = fl->ifl_sds.ifsd_flags; 1904 idx = pidx; 1905 credits = fl->ifl_credits; 1906 1907 n = count; 1908 MPASS(n > 0); 1909 MPASS(credits + n <= fl->ifl_size); 1910 1911 if (pidx < fl->ifl_cidx) 1912 MPASS(pidx + n <= fl->ifl_cidx); 1913 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1914 MPASS(fl->ifl_gen == 0); 1915 if (pidx > fl->ifl_cidx) 1916 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1917 1918 DBG_COUNTER_INC(fl_refills); 1919 if (n > 8) 1920 DBG_COUNTER_INC(fl_refills_large); 1921 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1922 while (n--) { 1923 /* 1924 * We allocate an uninitialized mbuf + cluster, mbuf is 1925 * initialized after rx. 1926 * 1927 * If the cluster is still set then we know a minimum sized packet was received 1928 */ 1929 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1930 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1931 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1932 if ((cl = sd_cl[frag_idx]) == NULL) { 1933 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1934 break; 1935 #if MEMORY_LOGGING 1936 fl->ifl_cl_enqueued++; 1937 #endif 1938 } 1939 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1940 break; 1941 } 1942 #if MEMORY_LOGGING 1943 fl->ifl_m_enqueued++; 1944 #endif 1945 1946 DBG_COUNTER_INC(rx_allocs); 1947 #if defined(__i386__) || defined(__amd64__) 1948 if (!IS_DMAR(ctx)) { 1949 bus_addr = pmap_kextract((vm_offset_t)cl); 1950 } else 1951 #endif 1952 { 1953 struct rxq_refill_cb_arg cb_arg; 1954 1955 cb_arg.error = 0; 1956 MPASS(sd_map != NULL); 1957 MPASS(sd_map[frag_idx] != NULL); 1958 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1959 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1960 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 1961 BUS_DMASYNC_PREREAD); 1962 1963 if (err != 0 || cb_arg.error) { 1964 /* 1965 * !zone_pack ? 1966 */ 1967 if (fl->ifl_zone == zone_pack) 1968 uma_zfree(fl->ifl_zone, cl); 1969 m_free(m); 1970 n = 0; 1971 goto done; 1972 } 1973 bus_addr = cb_arg.seg.ds_addr; 1974 } 1975 bit_set(fl->ifl_rx_bitmap, frag_idx); 1976 sd_flags[frag_idx] |= RX_SW_DESC_INUSE; 1977 1978 MPASS(sd_m[frag_idx] == NULL); 1979 sd_cl[frag_idx] = cl; 1980 sd_m[frag_idx] = m; 1981 fl->ifl_rxd_idxs[i] = frag_idx; 1982 fl->ifl_bus_addrs[i] = bus_addr; 1983 fl->ifl_vm_addrs[i] = cl; 1984 credits++; 1985 i++; 1986 MPASS(credits <= fl->ifl_size); 1987 if (++idx == fl->ifl_size) { 1988 fl->ifl_gen = 1; 1989 idx = 0; 1990 } 1991 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 1992 iru.iru_pidx = pidx; 1993 iru.iru_count = i; 1994 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1995 i = 0; 1996 pidx = idx; 1997 fl->ifl_pidx = idx; 1998 fl->ifl_credits = credits; 1999 } 2000 2001 } 2002 done: 2003 if (i) { 2004 iru.iru_pidx = pidx; 2005 iru.iru_count = i; 2006 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2007 fl->ifl_pidx = idx; 2008 fl->ifl_credits = credits; 2009 } 2010 DBG_COUNTER_INC(rxd_flush); 2011 if (fl->ifl_pidx == 0) 2012 pidx = fl->ifl_size - 1; 2013 else 2014 pidx = fl->ifl_pidx - 1; 2015 2016 if (sd_map) 2017 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2018 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2019 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2020 fl->ifl_fragidx = frag_idx; 2021 } 2022 2023 static __inline void 2024 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2025 { 2026 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2027 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2028 #ifdef INVARIANTS 2029 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2030 #endif 2031 2032 MPASS(fl->ifl_credits <= fl->ifl_size); 2033 MPASS(reclaimable == delta); 2034 2035 if (reclaimable > 0) 2036 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2037 } 2038 2039 static void 2040 iflib_fl_bufs_free(iflib_fl_t fl) 2041 { 2042 iflib_dma_info_t idi = fl->ifl_ifdi; 2043 uint32_t i; 2044 2045 for (i = 0; i < fl->ifl_size; i++) { 2046 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2047 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 2048 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2049 2050 if (*sd_flags & RX_SW_DESC_INUSE) { 2051 if (fl->ifl_sds.ifsd_map != NULL) { 2052 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 2053 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 2054 if (fl->ifl_rxq->ifr_ctx->ifc_in_detach) 2055 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 2056 } 2057 if (*sd_m != NULL) { 2058 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2059 uma_zfree(zone_mbuf, *sd_m); 2060 } 2061 if (*sd_cl != NULL) 2062 uma_zfree(fl->ifl_zone, *sd_cl); 2063 *sd_flags = 0; 2064 } else { 2065 MPASS(*sd_cl == NULL); 2066 MPASS(*sd_m == NULL); 2067 } 2068 #if MEMORY_LOGGING 2069 fl->ifl_m_dequeued++; 2070 fl->ifl_cl_dequeued++; 2071 #endif 2072 *sd_cl = NULL; 2073 *sd_m = NULL; 2074 } 2075 #ifdef INVARIANTS 2076 for (i = 0; i < fl->ifl_size; i++) { 2077 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 2078 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2079 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2080 } 2081 #endif 2082 /* 2083 * Reset free list values 2084 */ 2085 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2086 bzero(idi->idi_vaddr, idi->idi_size); 2087 } 2088 2089 /********************************************************************* 2090 * 2091 * Initialize a receive ring and its buffers. 2092 * 2093 **********************************************************************/ 2094 static int 2095 iflib_fl_setup(iflib_fl_t fl) 2096 { 2097 iflib_rxq_t rxq = fl->ifl_rxq; 2098 if_ctx_t ctx = rxq->ifr_ctx; 2099 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2100 2101 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2102 /* 2103 ** Free current RX buffer structs and their mbufs 2104 */ 2105 iflib_fl_bufs_free(fl); 2106 /* Now replenish the mbufs */ 2107 MPASS(fl->ifl_credits == 0); 2108 /* 2109 * XXX don't set the max_frame_size to larger 2110 * than the hardware can handle 2111 */ 2112 if (sctx->isc_max_frame_size <= 2048) 2113 fl->ifl_buf_size = MCLBYTES; 2114 #ifndef CONTIGMALLOC_WORKS 2115 else 2116 fl->ifl_buf_size = MJUMPAGESIZE; 2117 #else 2118 else if (sctx->isc_max_frame_size <= 4096) 2119 fl->ifl_buf_size = MJUMPAGESIZE; 2120 else if (sctx->isc_max_frame_size <= 9216) 2121 fl->ifl_buf_size = MJUM9BYTES; 2122 else 2123 fl->ifl_buf_size = MJUM16BYTES; 2124 #endif 2125 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2126 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2127 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2128 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2129 2130 2131 /* avoid pre-allocating zillions of clusters to an idle card 2132 * potentially speeding up attach 2133 */ 2134 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2135 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2136 if (min(128, fl->ifl_size) != fl->ifl_credits) 2137 return (ENOBUFS); 2138 /* 2139 * handle failure 2140 */ 2141 MPASS(rxq != NULL); 2142 MPASS(fl->ifl_ifdi != NULL); 2143 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2144 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2145 return (0); 2146 } 2147 2148 /********************************************************************* 2149 * 2150 * Free receive ring data structures 2151 * 2152 **********************************************************************/ 2153 static void 2154 iflib_rx_sds_free(iflib_rxq_t rxq) 2155 { 2156 iflib_fl_t fl; 2157 int i; 2158 2159 if (rxq->ifr_fl != NULL) { 2160 for (i = 0; i < rxq->ifr_nfl; i++) { 2161 fl = &rxq->ifr_fl[i]; 2162 if (fl->ifl_desc_tag != NULL) { 2163 bus_dma_tag_destroy(fl->ifl_desc_tag); 2164 fl->ifl_desc_tag = NULL; 2165 } 2166 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2167 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2168 /* XXX destroy maps first */ 2169 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2170 fl->ifl_sds.ifsd_m = NULL; 2171 fl->ifl_sds.ifsd_cl = NULL; 2172 fl->ifl_sds.ifsd_map = NULL; 2173 } 2174 free(rxq->ifr_fl, M_IFLIB); 2175 rxq->ifr_fl = NULL; 2176 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2177 } 2178 } 2179 2180 /* 2181 * MI independent logic 2182 * 2183 */ 2184 static void 2185 iflib_timer(void *arg) 2186 { 2187 iflib_txq_t txq = arg; 2188 if_ctx_t ctx = txq->ift_ctx; 2189 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2190 2191 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2192 return; 2193 /* 2194 ** Check on the state of the TX queue(s), this 2195 ** can be done without the lock because its RO 2196 ** and the HUNG state will be static if set. 2197 */ 2198 IFDI_TIMER(ctx, txq->ift_id); 2199 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2200 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2201 (sctx->isc_pause_frames == 0))) 2202 goto hung; 2203 2204 if (ifmp_ring_is_stalled(txq->ift_br)) 2205 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2206 txq->ift_cleaned_prev = txq->ift_cleaned; 2207 /* handle any laggards */ 2208 if (txq->ift_db_pending) 2209 GROUPTASK_ENQUEUE(&txq->ift_task); 2210 2211 sctx->isc_pause_frames = 0; 2212 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2213 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 2214 return; 2215 hung: 2216 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2217 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2218 STATE_LOCK(ctx); 2219 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2220 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2221 iflib_admin_intr_deferred(ctx); 2222 STATE_UNLOCK(ctx); 2223 } 2224 2225 static void 2226 iflib_init_locked(if_ctx_t ctx) 2227 { 2228 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2229 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2230 if_t ifp = ctx->ifc_ifp; 2231 iflib_fl_t fl; 2232 iflib_txq_t txq; 2233 iflib_rxq_t rxq; 2234 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2235 2236 2237 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2238 IFDI_INTR_DISABLE(ctx); 2239 2240 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2241 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2242 /* Set hardware offload abilities */ 2243 if_clearhwassist(ifp); 2244 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2245 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2246 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2247 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2248 if (if_getcapenable(ifp) & IFCAP_TSO4) 2249 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2250 if (if_getcapenable(ifp) & IFCAP_TSO6) 2251 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2252 2253 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2254 CALLOUT_LOCK(txq); 2255 callout_stop(&txq->ift_timer); 2256 CALLOUT_UNLOCK(txq); 2257 iflib_netmap_txq_init(ctx, txq); 2258 } 2259 #ifdef INVARIANTS 2260 i = if_getdrvflags(ifp); 2261 #endif 2262 IFDI_INIT(ctx); 2263 MPASS(if_getdrvflags(ifp) == i); 2264 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2265 /* XXX this should really be done on a per-queue basis */ 2266 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2267 MPASS(rxq->ifr_id == i); 2268 iflib_netmap_rxq_init(ctx, rxq); 2269 continue; 2270 } 2271 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2272 if (iflib_fl_setup(fl)) { 2273 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2274 goto done; 2275 } 2276 } 2277 } 2278 done: 2279 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2280 IFDI_INTR_ENABLE(ctx); 2281 txq = ctx->ifc_txqs; 2282 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2283 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2284 txq->ift_timer.c_cpu); 2285 } 2286 2287 static int 2288 iflib_media_change(if_t ifp) 2289 { 2290 if_ctx_t ctx = if_getsoftc(ifp); 2291 int err; 2292 2293 CTX_LOCK(ctx); 2294 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2295 iflib_init_locked(ctx); 2296 CTX_UNLOCK(ctx); 2297 return (err); 2298 } 2299 2300 static void 2301 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2302 { 2303 if_ctx_t ctx = if_getsoftc(ifp); 2304 2305 CTX_LOCK(ctx); 2306 IFDI_UPDATE_ADMIN_STATUS(ctx); 2307 IFDI_MEDIA_STATUS(ctx, ifmr); 2308 CTX_UNLOCK(ctx); 2309 } 2310 2311 void 2312 iflib_stop(if_ctx_t ctx) 2313 { 2314 iflib_txq_t txq = ctx->ifc_txqs; 2315 iflib_rxq_t rxq = ctx->ifc_rxqs; 2316 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2317 iflib_dma_info_t di; 2318 iflib_fl_t fl; 2319 int i, j; 2320 2321 /* Tell the stack that the interface is no longer active */ 2322 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2323 2324 IFDI_INTR_DISABLE(ctx); 2325 DELAY(1000); 2326 IFDI_STOP(ctx); 2327 DELAY(1000); 2328 2329 iflib_debug_reset(); 2330 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2331 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2332 /* make sure all transmitters have completed before proceeding XXX */ 2333 2334 CALLOUT_LOCK(txq); 2335 callout_stop(&txq->ift_timer); 2336 CALLOUT_UNLOCK(txq); 2337 2338 /* clean any enqueued buffers */ 2339 iflib_ifmp_purge(txq); 2340 /* Free any existing tx buffers. */ 2341 for (j = 0; j < txq->ift_size; j++) { 2342 iflib_txsd_free(ctx, txq, j); 2343 } 2344 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2345 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2346 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2347 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2348 txq->ift_pullups = 0; 2349 ifmp_ring_reset_stats(txq->ift_br); 2350 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2351 bzero((void *)di->idi_vaddr, di->idi_size); 2352 } 2353 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2354 /* make sure all transmitters have completed before proceeding XXX */ 2355 2356 for (j = 0, di = rxq->ifr_ifdi; j < rxq->ifr_nfl; j++, di++) 2357 bzero((void *)di->idi_vaddr, di->idi_size); 2358 /* also resets the free lists pidx/cidx */ 2359 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2360 iflib_fl_bufs_free(fl); 2361 } 2362 } 2363 2364 static inline caddr_t 2365 calc_next_rxd(iflib_fl_t fl, int cidx) 2366 { 2367 qidx_t size; 2368 int nrxd; 2369 caddr_t start, end, cur, next; 2370 2371 nrxd = fl->ifl_size; 2372 size = fl->ifl_rxd_size; 2373 start = fl->ifl_ifdi->idi_vaddr; 2374 2375 if (__predict_false(size == 0)) 2376 return (start); 2377 cur = start + size*cidx; 2378 end = start + size*nrxd; 2379 next = CACHE_PTR_NEXT(cur); 2380 return (next < end ? next : start); 2381 } 2382 2383 static inline void 2384 prefetch_pkts(iflib_fl_t fl, int cidx) 2385 { 2386 int nextptr; 2387 int nrxd = fl->ifl_size; 2388 caddr_t next_rxd; 2389 2390 2391 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2392 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2393 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2394 next_rxd = calc_next_rxd(fl, cidx); 2395 prefetch(next_rxd); 2396 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2397 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2398 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2399 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2400 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2401 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2402 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2403 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2404 } 2405 2406 static void 2407 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2408 { 2409 int flid, cidx; 2410 bus_dmamap_t map; 2411 iflib_fl_t fl; 2412 iflib_dma_info_t di; 2413 int next; 2414 2415 map = NULL; 2416 flid = irf->irf_flid; 2417 cidx = irf->irf_idx; 2418 fl = &rxq->ifr_fl[flid]; 2419 sd->ifsd_fl = fl; 2420 sd->ifsd_cidx = cidx; 2421 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2422 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2423 fl->ifl_credits--; 2424 #if MEMORY_LOGGING 2425 fl->ifl_m_dequeued++; 2426 #endif 2427 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2428 prefetch_pkts(fl, cidx); 2429 if (fl->ifl_sds.ifsd_map != NULL) { 2430 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2431 prefetch(&fl->ifl_sds.ifsd_map[next]); 2432 map = fl->ifl_sds.ifsd_map[cidx]; 2433 di = fl->ifl_ifdi; 2434 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2435 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2436 bus_dmamap_sync(di->idi_tag, di->idi_map, 2437 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2438 2439 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2440 MPASS(fl->ifl_cidx == cidx); 2441 if (unload) 2442 bus_dmamap_unload(fl->ifl_desc_tag, map); 2443 } 2444 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2445 if (__predict_false(fl->ifl_cidx == 0)) 2446 fl->ifl_gen = 0; 2447 if (map != NULL) 2448 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2449 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2450 bit_clear(fl->ifl_rx_bitmap, cidx); 2451 } 2452 2453 static struct mbuf * 2454 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2455 { 2456 int i, padlen , flags; 2457 struct mbuf *m, *mh, *mt; 2458 caddr_t cl; 2459 2460 i = 0; 2461 mh = NULL; 2462 do { 2463 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2464 2465 MPASS(*sd->ifsd_cl != NULL); 2466 MPASS(*sd->ifsd_m != NULL); 2467 2468 /* Don't include zero-length frags */ 2469 if (ri->iri_frags[i].irf_len == 0) { 2470 /* XXX we can save the cluster here, but not the mbuf */ 2471 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2472 m_free(*sd->ifsd_m); 2473 *sd->ifsd_m = NULL; 2474 continue; 2475 } 2476 m = *sd->ifsd_m; 2477 *sd->ifsd_m = NULL; 2478 if (mh == NULL) { 2479 flags = M_PKTHDR|M_EXT; 2480 mh = mt = m; 2481 padlen = ri->iri_pad; 2482 } else { 2483 flags = M_EXT; 2484 mt->m_next = m; 2485 mt = m; 2486 /* assuming padding is only on the first fragment */ 2487 padlen = 0; 2488 } 2489 cl = *sd->ifsd_cl; 2490 *sd->ifsd_cl = NULL; 2491 2492 /* Can these two be made one ? */ 2493 m_init(m, M_NOWAIT, MT_DATA, flags); 2494 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2495 /* 2496 * These must follow m_init and m_cljset 2497 */ 2498 m->m_data += padlen; 2499 ri->iri_len -= padlen; 2500 m->m_len = ri->iri_frags[i].irf_len; 2501 } while (++i < ri->iri_nfrags); 2502 2503 return (mh); 2504 } 2505 2506 /* 2507 * Process one software descriptor 2508 */ 2509 static struct mbuf * 2510 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2511 { 2512 struct if_rxsd sd; 2513 struct mbuf *m; 2514 2515 /* should I merge this back in now that the two paths are basically duplicated? */ 2516 if (ri->iri_nfrags == 1 && 2517 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2518 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2519 m = *sd.ifsd_m; 2520 *sd.ifsd_m = NULL; 2521 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2522 #ifndef __NO_STRICT_ALIGNMENT 2523 if (!IP_ALIGNED(m)) 2524 m->m_data += 2; 2525 #endif 2526 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2527 m->m_len = ri->iri_frags[0].irf_len; 2528 } else { 2529 m = assemble_segments(rxq, ri, &sd); 2530 } 2531 m->m_pkthdr.len = ri->iri_len; 2532 m->m_pkthdr.rcvif = ri->iri_ifp; 2533 m->m_flags |= ri->iri_flags; 2534 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2535 m->m_pkthdr.flowid = ri->iri_flowid; 2536 M_HASHTYPE_SET(m, ri->iri_rsstype); 2537 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2538 m->m_pkthdr.csum_data = ri->iri_csum_data; 2539 return (m); 2540 } 2541 2542 #if defined(INET6) || defined(INET) 2543 static void 2544 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2545 { 2546 CURVNET_SET(lc->ifp->if_vnet); 2547 #if defined(INET6) 2548 *v6 = VNET(ip6_forwarding); 2549 #endif 2550 #if defined(INET) 2551 *v4 = VNET(ipforwarding); 2552 #endif 2553 CURVNET_RESTORE(); 2554 } 2555 2556 /* 2557 * Returns true if it's possible this packet could be LROed. 2558 * if it returns false, it is guaranteed that tcp_lro_rx() 2559 * would not return zero. 2560 */ 2561 static bool 2562 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2563 { 2564 struct ether_header *eh; 2565 uint16_t eh_type; 2566 2567 eh = mtod(m, struct ether_header *); 2568 eh_type = ntohs(eh->ether_type); 2569 switch (eh_type) { 2570 #if defined(INET6) 2571 case ETHERTYPE_IPV6: 2572 return !v6_forwarding; 2573 #endif 2574 #if defined (INET) 2575 case ETHERTYPE_IP: 2576 return !v4_forwarding; 2577 #endif 2578 } 2579 2580 return false; 2581 } 2582 #else 2583 static void 2584 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2585 { 2586 } 2587 #endif 2588 2589 static bool 2590 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2591 { 2592 if_ctx_t ctx = rxq->ifr_ctx; 2593 if_shared_ctx_t sctx = ctx->ifc_sctx; 2594 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2595 int avail, i; 2596 qidx_t *cidxp; 2597 struct if_rxd_info ri; 2598 int err, budget_left, rx_bytes, rx_pkts; 2599 iflib_fl_t fl; 2600 struct ifnet *ifp; 2601 int lro_enabled; 2602 bool v4_forwarding, v6_forwarding, lro_possible; 2603 2604 /* 2605 * XXX early demux data packets so that if_input processing only handles 2606 * acks in interrupt context 2607 */ 2608 struct mbuf *m, *mh, *mt, *mf; 2609 2610 lro_possible = v4_forwarding = v6_forwarding = false; 2611 ifp = ctx->ifc_ifp; 2612 mh = mt = NULL; 2613 MPASS(budget > 0); 2614 rx_pkts = rx_bytes = 0; 2615 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2616 cidxp = &rxq->ifr_cq_cidx; 2617 else 2618 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2619 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2620 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2621 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2622 DBG_COUNTER_INC(rx_unavail); 2623 return (false); 2624 } 2625 2626 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2627 if (__predict_false(!CTX_ACTIVE(ctx))) { 2628 DBG_COUNTER_INC(rx_ctx_inactive); 2629 break; 2630 } 2631 /* 2632 * Reset client set fields to their default values 2633 */ 2634 rxd_info_zero(&ri); 2635 ri.iri_qsidx = rxq->ifr_id; 2636 ri.iri_cidx = *cidxp; 2637 ri.iri_ifp = ifp; 2638 ri.iri_frags = rxq->ifr_frags; 2639 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2640 2641 if (err) 2642 goto err; 2643 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2644 *cidxp = ri.iri_cidx; 2645 /* Update our consumer index */ 2646 /* XXX NB: shurd - check if this is still safe */ 2647 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2648 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2649 rxq->ifr_cq_gen = 0; 2650 } 2651 /* was this only a completion queue message? */ 2652 if (__predict_false(ri.iri_nfrags == 0)) 2653 continue; 2654 } 2655 MPASS(ri.iri_nfrags != 0); 2656 MPASS(ri.iri_len != 0); 2657 2658 /* will advance the cidx on the corresponding free lists */ 2659 m = iflib_rxd_pkt_get(rxq, &ri); 2660 if (avail == 0 && budget_left) 2661 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2662 2663 if (__predict_false(m == NULL)) { 2664 DBG_COUNTER_INC(rx_mbuf_null); 2665 continue; 2666 } 2667 /* imm_pkt: -- cxgb */ 2668 if (mh == NULL) 2669 mh = mt = m; 2670 else { 2671 mt->m_nextpkt = m; 2672 mt = m; 2673 } 2674 } 2675 /* make sure that we can refill faster than drain */ 2676 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2677 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2678 2679 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2680 if (lro_enabled) 2681 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2682 mt = mf = NULL; 2683 while (mh != NULL) { 2684 m = mh; 2685 mh = mh->m_nextpkt; 2686 m->m_nextpkt = NULL; 2687 #ifndef __NO_STRICT_ALIGNMENT 2688 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2689 continue; 2690 #endif 2691 rx_bytes += m->m_pkthdr.len; 2692 rx_pkts++; 2693 #if defined(INET6) || defined(INET) 2694 if (lro_enabled) { 2695 if (!lro_possible) { 2696 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2697 if (lro_possible && mf != NULL) { 2698 ifp->if_input(ifp, mf); 2699 DBG_COUNTER_INC(rx_if_input); 2700 mt = mf = NULL; 2701 } 2702 } 2703 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2704 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2705 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2706 continue; 2707 } 2708 } 2709 #endif 2710 if (lro_possible) { 2711 ifp->if_input(ifp, m); 2712 DBG_COUNTER_INC(rx_if_input); 2713 continue; 2714 } 2715 2716 if (mf == NULL) 2717 mf = m; 2718 if (mt != NULL) 2719 mt->m_nextpkt = m; 2720 mt = m; 2721 } 2722 if (mf != NULL) { 2723 ifp->if_input(ifp, mf); 2724 DBG_COUNTER_INC(rx_if_input); 2725 } 2726 2727 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2728 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2729 2730 /* 2731 * Flush any outstanding LRO work 2732 */ 2733 #if defined(INET6) || defined(INET) 2734 tcp_lro_flush_all(&rxq->ifr_lc); 2735 #endif 2736 if (avail) 2737 return true; 2738 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2739 err: 2740 STATE_LOCK(ctx); 2741 ctx->ifc_flags |= IFC_DO_RESET; 2742 iflib_admin_intr_deferred(ctx); 2743 STATE_UNLOCK(ctx); 2744 return (false); 2745 } 2746 2747 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2748 static inline qidx_t 2749 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2750 { 2751 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2752 qidx_t minthresh = txq->ift_size / 8; 2753 if (in_use > 4*minthresh) 2754 return (notify_count); 2755 if (in_use > 2*minthresh) 2756 return (notify_count >> 1); 2757 if (in_use > minthresh) 2758 return (notify_count >> 3); 2759 return (0); 2760 } 2761 2762 static inline qidx_t 2763 txq_max_rs_deferred(iflib_txq_t txq) 2764 { 2765 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2766 qidx_t minthresh = txq->ift_size / 8; 2767 if (txq->ift_in_use > 4*minthresh) 2768 return (notify_count); 2769 if (txq->ift_in_use > 2*minthresh) 2770 return (notify_count >> 1); 2771 if (txq->ift_in_use > minthresh) 2772 return (notify_count >> 2); 2773 return (2); 2774 } 2775 2776 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2777 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2778 2779 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2780 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2781 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2782 2783 /* forward compatibility for cxgb */ 2784 #define FIRST_QSET(ctx) 0 2785 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2786 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2787 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2788 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2789 2790 /* XXX we should be setting this to something other than zero */ 2791 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2792 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2793 2794 static inline bool 2795 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2796 { 2797 qidx_t dbval, max; 2798 bool rang; 2799 2800 rang = false; 2801 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2802 if (ring || txq->ift_db_pending >= max) { 2803 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2804 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2805 txq->ift_db_pending = txq->ift_npending = 0; 2806 rang = true; 2807 } 2808 return (rang); 2809 } 2810 2811 #ifdef PKT_DEBUG 2812 static void 2813 print_pkt(if_pkt_info_t pi) 2814 { 2815 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2816 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2817 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2818 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2819 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2820 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2821 } 2822 #endif 2823 2824 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2825 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2826 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2827 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2828 2829 static int 2830 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2831 { 2832 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2833 struct ether_vlan_header *eh; 2834 struct mbuf *m, *n; 2835 2836 n = m = *mp; 2837 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2838 M_WRITABLE(m) == 0) { 2839 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2840 return (ENOMEM); 2841 } else { 2842 m_freem(*mp); 2843 n = *mp = m; 2844 } 2845 } 2846 2847 /* 2848 * Determine where frame payload starts. 2849 * Jump over vlan headers if already present, 2850 * helpful for QinQ too. 2851 */ 2852 if (__predict_false(m->m_len < sizeof(*eh))) { 2853 txq->ift_pullups++; 2854 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2855 return (ENOMEM); 2856 } 2857 eh = mtod(m, struct ether_vlan_header *); 2858 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2859 pi->ipi_etype = ntohs(eh->evl_proto); 2860 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2861 } else { 2862 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2863 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2864 } 2865 2866 switch (pi->ipi_etype) { 2867 #ifdef INET 2868 case ETHERTYPE_IP: 2869 { 2870 struct ip *ip = NULL; 2871 struct tcphdr *th = NULL; 2872 int minthlen; 2873 2874 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2875 if (__predict_false(m->m_len < minthlen)) { 2876 /* 2877 * if this code bloat is causing too much of a hit 2878 * move it to a separate function and mark it noinline 2879 */ 2880 if (m->m_len == pi->ipi_ehdrlen) { 2881 n = m->m_next; 2882 MPASS(n); 2883 if (n->m_len >= sizeof(*ip)) { 2884 ip = (struct ip *)n->m_data; 2885 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2886 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2887 } else { 2888 txq->ift_pullups++; 2889 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2890 return (ENOMEM); 2891 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2892 } 2893 } else { 2894 txq->ift_pullups++; 2895 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2896 return (ENOMEM); 2897 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2898 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2899 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2900 } 2901 } else { 2902 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2903 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2904 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2905 } 2906 pi->ipi_ip_hlen = ip->ip_hl << 2; 2907 pi->ipi_ipproto = ip->ip_p; 2908 pi->ipi_flags |= IPI_TX_IPV4; 2909 2910 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 2911 ip->ip_sum = 0; 2912 2913 /* TCP checksum offload may require TCP header length */ 2914 if (IS_TX_OFFLOAD4(pi)) { 2915 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 2916 if (__predict_false(th == NULL)) { 2917 txq->ift_pullups++; 2918 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2919 return (ENOMEM); 2920 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2921 } 2922 pi->ipi_tcp_hflags = th->th_flags; 2923 pi->ipi_tcp_hlen = th->th_off << 2; 2924 pi->ipi_tcp_seq = th->th_seq; 2925 } 2926 if (IS_TSO4(pi)) { 2927 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2928 return (ENXIO); 2929 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2930 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2931 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2932 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2933 ip->ip_sum = 0; 2934 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2935 } 2936 } 2937 } 2938 break; 2939 } 2940 #endif 2941 #ifdef INET6 2942 case ETHERTYPE_IPV6: 2943 { 2944 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2945 struct tcphdr *th; 2946 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2947 2948 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2949 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2950 return (ENOMEM); 2951 } 2952 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2953 2954 /* XXX-BZ this will go badly in case of ext hdrs. */ 2955 pi->ipi_ipproto = ip6->ip6_nxt; 2956 pi->ipi_flags |= IPI_TX_IPV6; 2957 2958 /* TCP checksum offload may require TCP header length */ 2959 if (IS_TX_OFFLOAD6(pi)) { 2960 if (pi->ipi_ipproto == IPPROTO_TCP) { 2961 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2962 txq->ift_pullups++; 2963 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2964 return (ENOMEM); 2965 } 2966 pi->ipi_tcp_hflags = th->th_flags; 2967 pi->ipi_tcp_hlen = th->th_off << 2; 2968 pi->ipi_tcp_seq = th->th_seq; 2969 } 2970 if (IS_TSO6(pi)) { 2971 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2972 return (ENXIO); 2973 /* 2974 * The corresponding flag is set by the stack in the IPv4 2975 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 2976 * So, set it here because the rest of the flow requires it. 2977 */ 2978 pi->ipi_csum_flags |= CSUM_IP6_TCP; 2979 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2980 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2981 } 2982 } 2983 break; 2984 } 2985 #endif 2986 default: 2987 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2988 pi->ipi_ip_hlen = 0; 2989 break; 2990 } 2991 *mp = m; 2992 2993 return (0); 2994 } 2995 2996 static __noinline struct mbuf * 2997 collapse_pkthdr(struct mbuf *m0) 2998 { 2999 struct mbuf *m, *m_next, *tmp; 3000 3001 m = m0; 3002 m_next = m->m_next; 3003 while (m_next != NULL && m_next->m_len == 0) { 3004 m = m_next; 3005 m->m_next = NULL; 3006 m_free(m); 3007 m_next = m_next->m_next; 3008 } 3009 m = m0; 3010 m->m_next = m_next; 3011 if ((m_next->m_flags & M_EXT) == 0) { 3012 m = m_defrag(m, M_NOWAIT); 3013 } else { 3014 tmp = m_next->m_next; 3015 memcpy(m_next, m, MPKTHSIZE); 3016 m = m_next; 3017 m->m_next = tmp; 3018 } 3019 return (m); 3020 } 3021 3022 /* 3023 * If dodgy hardware rejects the scatter gather chain we've handed it 3024 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3025 * m_defrag'd mbufs 3026 */ 3027 static __noinline struct mbuf * 3028 iflib_remove_mbuf(iflib_txq_t txq) 3029 { 3030 int ntxd, i, pidx; 3031 struct mbuf *m, *mh, **ifsd_m; 3032 3033 pidx = txq->ift_pidx; 3034 ifsd_m = txq->ift_sds.ifsd_m; 3035 ntxd = txq->ift_size; 3036 mh = m = ifsd_m[pidx]; 3037 ifsd_m[pidx] = NULL; 3038 #if MEMORY_LOGGING 3039 txq->ift_dequeued++; 3040 #endif 3041 i = 1; 3042 3043 while (m) { 3044 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 3045 #if MEMORY_LOGGING 3046 txq->ift_dequeued++; 3047 #endif 3048 m = m->m_next; 3049 i++; 3050 } 3051 return (mh); 3052 } 3053 3054 static int 3055 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 3056 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 3057 int max_segs, int flags) 3058 { 3059 if_ctx_t ctx; 3060 if_shared_ctx_t sctx; 3061 if_softc_ctx_t scctx; 3062 int i, next, pidx, err, ntxd, count; 3063 struct mbuf *m, *tmp, **ifsd_m; 3064 3065 m = *m0; 3066 3067 /* 3068 * Please don't ever do this 3069 */ 3070 if (__predict_false(m->m_len == 0)) 3071 *m0 = m = collapse_pkthdr(m); 3072 3073 ctx = txq->ift_ctx; 3074 sctx = ctx->ifc_sctx; 3075 scctx = &ctx->ifc_softc_ctx; 3076 ifsd_m = txq->ift_sds.ifsd_m; 3077 ntxd = txq->ift_size; 3078 pidx = txq->ift_pidx; 3079 if (map != NULL) { 3080 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 3081 3082 err = bus_dmamap_load_mbuf_sg(tag, map, 3083 *m0, segs, nsegs, BUS_DMA_NOWAIT); 3084 if (err) 3085 return (err); 3086 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 3087 count = 0; 3088 m = *m0; 3089 do { 3090 if (__predict_false(m->m_len <= 0)) { 3091 tmp = m; 3092 m = m->m_next; 3093 tmp->m_next = NULL; 3094 m_free(tmp); 3095 continue; 3096 } 3097 m = m->m_next; 3098 count++; 3099 } while (m != NULL); 3100 if (count > *nsegs) { 3101 ifsd_m[pidx] = *m0; 3102 ifsd_m[pidx]->m_flags |= M_TOOBIG; 3103 return (0); 3104 } 3105 m = *m0; 3106 count = 0; 3107 do { 3108 next = (pidx + count) & (ntxd-1); 3109 MPASS(ifsd_m[next] == NULL); 3110 ifsd_m[next] = m; 3111 count++; 3112 tmp = m; 3113 m = m->m_next; 3114 } while (m != NULL); 3115 } else { 3116 int buflen, sgsize, maxsegsz, max_sgsize; 3117 vm_offset_t vaddr; 3118 vm_paddr_t curaddr; 3119 3120 count = i = 0; 3121 m = *m0; 3122 if (m->m_pkthdr.csum_flags & CSUM_TSO) 3123 maxsegsz = scctx->isc_tx_tso_segsize_max; 3124 else 3125 maxsegsz = sctx->isc_tx_maxsegsize; 3126 3127 do { 3128 if (__predict_false(m->m_len <= 0)) { 3129 tmp = m; 3130 m = m->m_next; 3131 tmp->m_next = NULL; 3132 m_free(tmp); 3133 continue; 3134 } 3135 buflen = m->m_len; 3136 vaddr = (vm_offset_t)m->m_data; 3137 /* 3138 * see if we can't be smarter about physically 3139 * contiguous mappings 3140 */ 3141 next = (pidx + count) & (ntxd-1); 3142 MPASS(ifsd_m[next] == NULL); 3143 #if MEMORY_LOGGING 3144 txq->ift_enqueued++; 3145 #endif 3146 ifsd_m[next] = m; 3147 while (buflen > 0) { 3148 if (i >= max_segs) 3149 goto err; 3150 max_sgsize = MIN(buflen, maxsegsz); 3151 curaddr = pmap_kextract(vaddr); 3152 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 3153 sgsize = MIN(sgsize, max_sgsize); 3154 segs[i].ds_addr = curaddr; 3155 segs[i].ds_len = sgsize; 3156 vaddr += sgsize; 3157 buflen -= sgsize; 3158 i++; 3159 } 3160 count++; 3161 tmp = m; 3162 m = m->m_next; 3163 } while (m != NULL); 3164 *nsegs = i; 3165 } 3166 return (0); 3167 err: 3168 *m0 = iflib_remove_mbuf(txq); 3169 return (EFBIG); 3170 } 3171 3172 static inline caddr_t 3173 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3174 { 3175 qidx_t size; 3176 int ntxd; 3177 caddr_t start, end, cur, next; 3178 3179 ntxd = txq->ift_size; 3180 size = txq->ift_txd_size[qid]; 3181 start = txq->ift_ifdi[qid].idi_vaddr; 3182 3183 if (__predict_false(size == 0)) 3184 return (start); 3185 cur = start + size*cidx; 3186 end = start + size*ntxd; 3187 next = CACHE_PTR_NEXT(cur); 3188 return (next < end ? next : start); 3189 } 3190 3191 /* 3192 * Pad an mbuf to ensure a minimum ethernet frame size. 3193 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3194 */ 3195 static __noinline int 3196 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3197 { 3198 /* 3199 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3200 * and ARP message is the smallest common payload I can think of 3201 */ 3202 static char pad[18]; /* just zeros */ 3203 int n; 3204 struct mbuf *new_head; 3205 3206 if (!M_WRITABLE(*m_head)) { 3207 new_head = m_dup(*m_head, M_NOWAIT); 3208 if (new_head == NULL) { 3209 m_freem(*m_head); 3210 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3211 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3212 return ENOMEM; 3213 } 3214 m_freem(*m_head); 3215 *m_head = new_head; 3216 } 3217 3218 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3219 n > 0; n -= sizeof(pad)) 3220 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3221 break; 3222 3223 if (n > 0) { 3224 m_freem(*m_head); 3225 device_printf(dev, "cannot pad short frame\n"); 3226 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3227 return (ENOBUFS); 3228 } 3229 3230 return 0; 3231 } 3232 3233 static int 3234 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3235 { 3236 if_ctx_t ctx; 3237 if_shared_ctx_t sctx; 3238 if_softc_ctx_t scctx; 3239 bus_dma_segment_t *segs; 3240 struct mbuf *m_head; 3241 void *next_txd; 3242 bus_dmamap_t map; 3243 struct if_pkt_info pi; 3244 int remap = 0; 3245 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3246 bus_dma_tag_t desc_tag; 3247 3248 segs = txq->ift_segs; 3249 ctx = txq->ift_ctx; 3250 sctx = ctx->ifc_sctx; 3251 scctx = &ctx->ifc_softc_ctx; 3252 segs = txq->ift_segs; 3253 ntxd = txq->ift_size; 3254 m_head = *m_headp; 3255 map = NULL; 3256 3257 /* 3258 * If we're doing TSO the next descriptor to clean may be quite far ahead 3259 */ 3260 cidx = txq->ift_cidx; 3261 pidx = txq->ift_pidx; 3262 if (ctx->ifc_flags & IFC_PREFETCH) { 3263 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3264 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3265 next_txd = calc_next_txd(txq, cidx, 0); 3266 prefetch(next_txd); 3267 } 3268 3269 /* prefetch the next cache line of mbuf pointers and flags */ 3270 prefetch(&txq->ift_sds.ifsd_m[next]); 3271 if (txq->ift_sds.ifsd_map != NULL) { 3272 prefetch(&txq->ift_sds.ifsd_map[next]); 3273 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3274 prefetch(&txq->ift_sds.ifsd_flags[next]); 3275 } 3276 } else if (txq->ift_sds.ifsd_map != NULL) 3277 map = txq->ift_sds.ifsd_map[pidx]; 3278 3279 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3280 desc_tag = txq->ift_tso_desc_tag; 3281 max_segs = scctx->isc_tx_tso_segments_max; 3282 } else { 3283 desc_tag = txq->ift_desc_tag; 3284 max_segs = scctx->isc_tx_nsegments; 3285 } 3286 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3287 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3288 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3289 if (err) 3290 return err; 3291 } 3292 m_head = *m_headp; 3293 3294 pkt_info_zero(&pi); 3295 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3296 pi.ipi_pidx = pidx; 3297 pi.ipi_qsidx = txq->ift_id; 3298 pi.ipi_len = m_head->m_pkthdr.len; 3299 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3300 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3301 3302 /* deliberate bitwise OR to make one condition */ 3303 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3304 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3305 return (err); 3306 m_head = *m_headp; 3307 } 3308 3309 retry: 3310 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3311 defrag: 3312 if (__predict_false(err)) { 3313 switch (err) { 3314 case EFBIG: 3315 /* try collapse once and defrag once */ 3316 if (remap == 0) { 3317 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3318 /* try defrag if collapsing fails */ 3319 if (m_head == NULL) 3320 remap++; 3321 } 3322 if (remap == 1) 3323 m_head = m_defrag(*m_headp, M_NOWAIT); 3324 remap++; 3325 if (__predict_false(m_head == NULL)) 3326 goto defrag_failed; 3327 txq->ift_mbuf_defrag++; 3328 *m_headp = m_head; 3329 goto retry; 3330 break; 3331 case ENOMEM: 3332 txq->ift_no_tx_dma_setup++; 3333 break; 3334 default: 3335 txq->ift_no_tx_dma_setup++; 3336 m_freem(*m_headp); 3337 DBG_COUNTER_INC(tx_frees); 3338 *m_headp = NULL; 3339 break; 3340 } 3341 txq->ift_map_failed++; 3342 DBG_COUNTER_INC(encap_load_mbuf_fail); 3343 return (err); 3344 } 3345 3346 /* 3347 * XXX assumes a 1 to 1 relationship between segments and 3348 * descriptors - this does not hold true on all drivers, e.g. 3349 * cxgb 3350 */ 3351 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3352 txq->ift_no_desc_avail++; 3353 if (map != NULL) 3354 bus_dmamap_unload(desc_tag, map); 3355 DBG_COUNTER_INC(encap_txq_avail_fail); 3356 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3357 GROUPTASK_ENQUEUE(&txq->ift_task); 3358 return (ENOBUFS); 3359 } 3360 /* 3361 * On Intel cards we can greatly reduce the number of TX interrupts 3362 * we see by only setting report status on every Nth descriptor. 3363 * However, this also means that the driver will need to keep track 3364 * of the descriptors that RS was set on to check them for the DD bit. 3365 */ 3366 txq->ift_rs_pending += nsegs + 1; 3367 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3368 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3369 pi.ipi_flags |= IPI_TX_INTR; 3370 txq->ift_rs_pending = 0; 3371 } 3372 3373 pi.ipi_segs = segs; 3374 pi.ipi_nsegs = nsegs; 3375 3376 MPASS(pidx >= 0 && pidx < txq->ift_size); 3377 #ifdef PKT_DEBUG 3378 print_pkt(&pi); 3379 #endif 3380 if (map != NULL) 3381 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3382 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3383 if (map != NULL) 3384 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3385 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3386 DBG_COUNTER_INC(tx_encap); 3387 MPASS(pi.ipi_new_pidx < txq->ift_size); 3388 3389 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3390 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3391 ndesc += txq->ift_size; 3392 txq->ift_gen = 1; 3393 } 3394 /* 3395 * drivers can need as many as 3396 * two sentinels 3397 */ 3398 MPASS(ndesc <= pi.ipi_nsegs + 2); 3399 MPASS(pi.ipi_new_pidx != pidx); 3400 MPASS(ndesc > 0); 3401 txq->ift_in_use += ndesc; 3402 3403 /* 3404 * We update the last software descriptor again here because there may 3405 * be a sentinel and/or there may be more mbufs than segments 3406 */ 3407 txq->ift_pidx = pi.ipi_new_pidx; 3408 txq->ift_npending += pi.ipi_ndescs; 3409 } else { 3410 *m_headp = m_head = iflib_remove_mbuf(txq); 3411 if (err == EFBIG) { 3412 txq->ift_txd_encap_efbig++; 3413 if (remap < 2) { 3414 remap = 1; 3415 goto defrag; 3416 } 3417 } 3418 DBG_COUNTER_INC(encap_txd_encap_fail); 3419 goto defrag_failed; 3420 } 3421 return (err); 3422 3423 defrag_failed: 3424 txq->ift_mbuf_defrag_failed++; 3425 txq->ift_map_failed++; 3426 m_freem(*m_headp); 3427 DBG_COUNTER_INC(tx_frees); 3428 *m_headp = NULL; 3429 return (ENOMEM); 3430 } 3431 3432 static void 3433 iflib_tx_desc_free(iflib_txq_t txq, int n) 3434 { 3435 int hasmap; 3436 uint32_t qsize, cidx, mask, gen; 3437 struct mbuf *m, **ifsd_m; 3438 uint8_t *ifsd_flags; 3439 bus_dmamap_t *ifsd_map; 3440 bool do_prefetch; 3441 3442 cidx = txq->ift_cidx; 3443 gen = txq->ift_gen; 3444 qsize = txq->ift_size; 3445 mask = qsize-1; 3446 hasmap = txq->ift_sds.ifsd_map != NULL; 3447 ifsd_flags = txq->ift_sds.ifsd_flags; 3448 ifsd_m = txq->ift_sds.ifsd_m; 3449 ifsd_map = txq->ift_sds.ifsd_map; 3450 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3451 3452 while (n-- > 0) { 3453 if (do_prefetch) { 3454 prefetch(ifsd_m[(cidx + 3) & mask]); 3455 prefetch(ifsd_m[(cidx + 4) & mask]); 3456 } 3457 if (ifsd_m[cidx] != NULL) { 3458 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3459 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3460 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3461 /* 3462 * does it matter if it's not the TSO tag? If so we'll 3463 * have to add the type to flags 3464 */ 3465 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3466 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3467 } 3468 if ((m = ifsd_m[cidx]) != NULL) { 3469 /* XXX we don't support any drivers that batch packets yet */ 3470 MPASS(m->m_nextpkt == NULL); 3471 /* if the number of clusters exceeds the number of segments 3472 * there won't be space on the ring to save a pointer to each 3473 * cluster so we simply free the list here 3474 */ 3475 if (m->m_flags & M_TOOBIG) { 3476 m_freem(m); 3477 } else { 3478 m_free(m); 3479 } 3480 ifsd_m[cidx] = NULL; 3481 #if MEMORY_LOGGING 3482 txq->ift_dequeued++; 3483 #endif 3484 DBG_COUNTER_INC(tx_frees); 3485 } 3486 } 3487 if (__predict_false(++cidx == qsize)) { 3488 cidx = 0; 3489 gen = 0; 3490 } 3491 } 3492 txq->ift_cidx = cidx; 3493 txq->ift_gen = gen; 3494 } 3495 3496 static __inline int 3497 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3498 { 3499 int reclaim; 3500 if_ctx_t ctx = txq->ift_ctx; 3501 3502 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3503 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3504 3505 /* 3506 * Need a rate-limiting check so that this isn't called every time 3507 */ 3508 iflib_tx_credits_update(ctx, txq); 3509 reclaim = DESC_RECLAIMABLE(txq); 3510 3511 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3512 #ifdef INVARIANTS 3513 if (iflib_verbose_debug) { 3514 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3515 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3516 reclaim, thresh); 3517 3518 } 3519 #endif 3520 return (0); 3521 } 3522 iflib_tx_desc_free(txq, reclaim); 3523 txq->ift_cleaned += reclaim; 3524 txq->ift_in_use -= reclaim; 3525 3526 return (reclaim); 3527 } 3528 3529 static struct mbuf ** 3530 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3531 { 3532 int next, size; 3533 struct mbuf **items; 3534 3535 size = r->size; 3536 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3537 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3538 3539 prefetch(items[(cidx + offset) & (size-1)]); 3540 if (remaining > 1) { 3541 prefetch2cachelines(&items[next]); 3542 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3543 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3544 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3545 } 3546 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3547 } 3548 3549 static void 3550 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3551 { 3552 3553 ifmp_ring_check_drainage(txq->ift_br, budget); 3554 } 3555 3556 static uint32_t 3557 iflib_txq_can_drain(struct ifmp_ring *r) 3558 { 3559 iflib_txq_t txq = r->cookie; 3560 if_ctx_t ctx = txq->ift_ctx; 3561 3562 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3563 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3564 } 3565 3566 static uint32_t 3567 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3568 { 3569 iflib_txq_t txq = r->cookie; 3570 if_ctx_t ctx = txq->ift_ctx; 3571 struct ifnet *ifp = ctx->ifc_ifp; 3572 struct mbuf **mp, *m; 3573 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3574 int reclaimed, err, in_use_prev, desc_used; 3575 bool do_prefetch, ring, rang; 3576 3577 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3578 !LINK_ACTIVE(ctx))) { 3579 DBG_COUNTER_INC(txq_drain_notready); 3580 return (0); 3581 } 3582 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3583 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3584 avail = IDXDIFF(pidx, cidx, r->size); 3585 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3586 DBG_COUNTER_INC(txq_drain_flushing); 3587 for (i = 0; i < avail; i++) { 3588 m_free(r->items[(cidx + i) & (r->size-1)]); 3589 r->items[(cidx + i) & (r->size-1)] = NULL; 3590 } 3591 return (avail); 3592 } 3593 3594 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3595 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3596 CALLOUT_LOCK(txq); 3597 callout_stop(&txq->ift_timer); 3598 CALLOUT_UNLOCK(txq); 3599 DBG_COUNTER_INC(txq_drain_oactive); 3600 return (0); 3601 } 3602 if (reclaimed) 3603 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3604 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3605 count = MIN(avail, TX_BATCH_SIZE); 3606 #ifdef INVARIANTS 3607 if (iflib_verbose_debug) 3608 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3609 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3610 #endif 3611 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3612 avail = TXQ_AVAIL(txq); 3613 err = 0; 3614 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3615 int rem = do_prefetch ? count - i : 0; 3616 3617 mp = _ring_peek_one(r, cidx, i, rem); 3618 MPASS(mp != NULL && *mp != NULL); 3619 if (__predict_false(*mp == (struct mbuf *)txq)) { 3620 consumed++; 3621 reclaimed++; 3622 continue; 3623 } 3624 in_use_prev = txq->ift_in_use; 3625 err = iflib_encap(txq, mp); 3626 if (__predict_false(err)) { 3627 DBG_COUNTER_INC(txq_drain_encapfail); 3628 /* no room - bail out */ 3629 if (err == ENOBUFS) 3630 break; 3631 consumed++; 3632 DBG_COUNTER_INC(txq_drain_encapfail); 3633 /* we can't send this packet - skip it */ 3634 continue; 3635 } 3636 consumed++; 3637 pkt_sent++; 3638 m = *mp; 3639 DBG_COUNTER_INC(tx_sent); 3640 bytes_sent += m->m_pkthdr.len; 3641 mcast_sent += !!(m->m_flags & M_MCAST); 3642 avail = TXQ_AVAIL(txq); 3643 3644 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3645 desc_used += (txq->ift_in_use - in_use_prev); 3646 ETHER_BPF_MTAP(ifp, m); 3647 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3648 break; 3649 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3650 } 3651 3652 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3653 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3654 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3655 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3656 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3657 if (mcast_sent) 3658 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3659 #ifdef INVARIANTS 3660 if (iflib_verbose_debug) 3661 printf("consumed=%d\n", consumed); 3662 #endif 3663 return (consumed); 3664 } 3665 3666 static uint32_t 3667 iflib_txq_drain_always(struct ifmp_ring *r) 3668 { 3669 return (1); 3670 } 3671 3672 static uint32_t 3673 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3674 { 3675 int i, avail; 3676 struct mbuf **mp; 3677 iflib_txq_t txq; 3678 3679 txq = r->cookie; 3680 3681 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3682 CALLOUT_LOCK(txq); 3683 callout_stop(&txq->ift_timer); 3684 CALLOUT_UNLOCK(txq); 3685 3686 avail = IDXDIFF(pidx, cidx, r->size); 3687 for (i = 0; i < avail; i++) { 3688 mp = _ring_peek_one(r, cidx, i, avail - i); 3689 if (__predict_false(*mp == (struct mbuf *)txq)) 3690 continue; 3691 m_freem(*mp); 3692 } 3693 MPASS(ifmp_ring_is_stalled(r) == 0); 3694 return (avail); 3695 } 3696 3697 static void 3698 iflib_ifmp_purge(iflib_txq_t txq) 3699 { 3700 struct ifmp_ring *r; 3701 3702 r = txq->ift_br; 3703 r->drain = iflib_txq_drain_free; 3704 r->can_drain = iflib_txq_drain_always; 3705 3706 ifmp_ring_check_drainage(r, r->size); 3707 3708 r->drain = iflib_txq_drain; 3709 r->can_drain = iflib_txq_can_drain; 3710 } 3711 3712 static void 3713 _task_fn_tx(void *context) 3714 { 3715 iflib_txq_t txq = context; 3716 if_ctx_t ctx = txq->ift_ctx; 3717 struct ifnet *ifp = ctx->ifc_ifp; 3718 3719 #ifdef IFLIB_DIAGNOSTICS 3720 txq->ift_cpu_exec_count[curcpu]++; 3721 #endif 3722 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3723 return; 3724 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3725 /* 3726 * If there are no available credits, and TX IRQs are not in use, 3727 * re-schedule the task immediately. 3728 */ 3729 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3730 netmap_tx_irq(ifp, txq->ift_id); 3731 else { 3732 #ifdef DEV_NETMAP 3733 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 3734 struct netmap_kring *kring = NA(ctx->ifc_ifp)->tx_rings[txq->ift_id]; 3735 3736 if (kring->nr_hwtail != nm_prev(kring->rhead, kring->nkr_num_slots - 1)) 3737 GROUPTASK_ENQUEUE(&txq->ift_task); 3738 } 3739 #endif 3740 } 3741 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3742 return; 3743 } 3744 if (txq->ift_db_pending) 3745 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); 3746 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3747 if (ctx->ifc_flags & IFC_LEGACY) 3748 IFDI_INTR_ENABLE(ctx); 3749 else { 3750 #ifdef INVARIANTS 3751 int rc = 3752 #endif 3753 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3754 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3755 } 3756 } 3757 3758 static void 3759 _task_fn_rx(void *context) 3760 { 3761 iflib_rxq_t rxq = context; 3762 if_ctx_t ctx = rxq->ifr_ctx; 3763 bool more; 3764 uint16_t budget; 3765 3766 #ifdef IFLIB_DIAGNOSTICS 3767 rxq->ifr_cpu_exec_count[curcpu]++; 3768 #endif 3769 DBG_COUNTER_INC(task_fn_rxs); 3770 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3771 return; 3772 more = true; 3773 #ifdef DEV_NETMAP 3774 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3775 u_int work = 0; 3776 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3777 more = false; 3778 } 3779 } 3780 #endif 3781 budget = ctx->ifc_sysctl_rx_budget; 3782 if (budget == 0) 3783 budget = 16; /* XXX */ 3784 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3785 if (ctx->ifc_flags & IFC_LEGACY) 3786 IFDI_INTR_ENABLE(ctx); 3787 else { 3788 #ifdef INVARIANTS 3789 int rc = 3790 #endif 3791 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3792 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3793 DBG_COUNTER_INC(rx_intr_enables); 3794 } 3795 } 3796 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3797 return; 3798 if (more) 3799 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3800 } 3801 3802 static void 3803 _task_fn_admin(void *context) 3804 { 3805 if_ctx_t ctx = context; 3806 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3807 iflib_txq_t txq; 3808 int i; 3809 bool oactive, running, do_reset, do_watchdog; 3810 3811 STATE_LOCK(ctx); 3812 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3813 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3814 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3815 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3816 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3817 STATE_UNLOCK(ctx); 3818 3819 if ((!running & !oactive) && 3820 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3821 return; 3822 3823 CTX_LOCK(ctx); 3824 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3825 CALLOUT_LOCK(txq); 3826 callout_stop(&txq->ift_timer); 3827 CALLOUT_UNLOCK(txq); 3828 } 3829 if (do_watchdog) { 3830 ctx->ifc_watchdog_events++; 3831 IFDI_WATCHDOG_RESET(ctx); 3832 } 3833 IFDI_UPDATE_ADMIN_STATUS(ctx); 3834 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3835 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 3836 IFDI_LINK_INTR_ENABLE(ctx); 3837 if (do_reset) 3838 iflib_if_init_locked(ctx); 3839 CTX_UNLOCK(ctx); 3840 3841 if (LINK_ACTIVE(ctx) == 0) 3842 return; 3843 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3844 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3845 } 3846 3847 3848 static void 3849 _task_fn_iov(void *context) 3850 { 3851 if_ctx_t ctx = context; 3852 3853 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3854 return; 3855 3856 CTX_LOCK(ctx); 3857 IFDI_VFLR_HANDLE(ctx); 3858 CTX_UNLOCK(ctx); 3859 } 3860 3861 static int 3862 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3863 { 3864 int err; 3865 if_int_delay_info_t info; 3866 if_ctx_t ctx; 3867 3868 info = (if_int_delay_info_t)arg1; 3869 ctx = info->iidi_ctx; 3870 info->iidi_req = req; 3871 info->iidi_oidp = oidp; 3872 CTX_LOCK(ctx); 3873 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3874 CTX_UNLOCK(ctx); 3875 return (err); 3876 } 3877 3878 /********************************************************************* 3879 * 3880 * IFNET FUNCTIONS 3881 * 3882 **********************************************************************/ 3883 3884 static void 3885 iflib_if_init_locked(if_ctx_t ctx) 3886 { 3887 iflib_stop(ctx); 3888 iflib_init_locked(ctx); 3889 } 3890 3891 3892 static void 3893 iflib_if_init(void *arg) 3894 { 3895 if_ctx_t ctx = arg; 3896 3897 CTX_LOCK(ctx); 3898 iflib_if_init_locked(ctx); 3899 CTX_UNLOCK(ctx); 3900 } 3901 3902 static int 3903 iflib_if_transmit(if_t ifp, struct mbuf *m) 3904 { 3905 if_ctx_t ctx = if_getsoftc(ifp); 3906 3907 iflib_txq_t txq; 3908 int err, qidx; 3909 3910 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3911 DBG_COUNTER_INC(tx_frees); 3912 m_freem(m); 3913 return (ENOBUFS); 3914 } 3915 3916 MPASS(m->m_nextpkt == NULL); 3917 qidx = 0; 3918 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3919 qidx = QIDX(ctx, m); 3920 /* 3921 * XXX calculate buf_ring based on flowid (divvy up bits?) 3922 */ 3923 txq = &ctx->ifc_txqs[qidx]; 3924 3925 #ifdef DRIVER_BACKPRESSURE 3926 if (txq->ift_closed) { 3927 while (m != NULL) { 3928 next = m->m_nextpkt; 3929 m->m_nextpkt = NULL; 3930 m_freem(m); 3931 m = next; 3932 } 3933 return (ENOBUFS); 3934 } 3935 #endif 3936 #ifdef notyet 3937 qidx = count = 0; 3938 mp = marr; 3939 next = m; 3940 do { 3941 count++; 3942 next = next->m_nextpkt; 3943 } while (next != NULL); 3944 3945 if (count > nitems(marr)) 3946 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3947 /* XXX check nextpkt */ 3948 m_freem(m); 3949 /* XXX simplify for now */ 3950 DBG_COUNTER_INC(tx_frees); 3951 return (ENOBUFS); 3952 } 3953 for (next = m, i = 0; next != NULL; i++) { 3954 mp[i] = next; 3955 next = next->m_nextpkt; 3956 mp[i]->m_nextpkt = NULL; 3957 } 3958 #endif 3959 DBG_COUNTER_INC(tx_seen); 3960 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); 3961 3962 GROUPTASK_ENQUEUE(&txq->ift_task); 3963 if (err) { 3964 /* support forthcoming later */ 3965 #ifdef DRIVER_BACKPRESSURE 3966 txq->ift_closed = TRUE; 3967 #endif 3968 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3969 m_freem(m); 3970 } 3971 3972 return (err); 3973 } 3974 3975 static void 3976 iflib_if_qflush(if_t ifp) 3977 { 3978 if_ctx_t ctx = if_getsoftc(ifp); 3979 iflib_txq_t txq = ctx->ifc_txqs; 3980 int i; 3981 3982 STATE_LOCK(ctx); 3983 ctx->ifc_flags |= IFC_QFLUSH; 3984 STATE_UNLOCK(ctx); 3985 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3986 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3987 iflib_txq_check_drain(txq, 0); 3988 STATE_LOCK(ctx); 3989 ctx->ifc_flags &= ~IFC_QFLUSH; 3990 STATE_UNLOCK(ctx); 3991 3992 if_qflush(ifp); 3993 } 3994 3995 3996 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3997 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 3998 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 3999 4000 static int 4001 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4002 { 4003 if_ctx_t ctx = if_getsoftc(ifp); 4004 struct ifreq *ifr = (struct ifreq *)data; 4005 #if defined(INET) || defined(INET6) 4006 struct ifaddr *ifa = (struct ifaddr *)data; 4007 #endif 4008 bool avoid_reset = FALSE; 4009 int err = 0, reinit = 0, bits; 4010 4011 switch (command) { 4012 case SIOCSIFADDR: 4013 #ifdef INET 4014 if (ifa->ifa_addr->sa_family == AF_INET) 4015 avoid_reset = TRUE; 4016 #endif 4017 #ifdef INET6 4018 if (ifa->ifa_addr->sa_family == AF_INET6) 4019 avoid_reset = TRUE; 4020 #endif 4021 /* 4022 ** Calling init results in link renegotiation, 4023 ** so we avoid doing it when possible. 4024 */ 4025 if (avoid_reset) { 4026 if_setflagbits(ifp, IFF_UP,0); 4027 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING)) 4028 reinit = 1; 4029 #ifdef INET 4030 if (!(if_getflags(ifp) & IFF_NOARP)) 4031 arp_ifinit(ifp, ifa); 4032 #endif 4033 } else 4034 err = ether_ioctl(ifp, command, data); 4035 break; 4036 case SIOCSIFMTU: 4037 CTX_LOCK(ctx); 4038 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4039 CTX_UNLOCK(ctx); 4040 break; 4041 } 4042 bits = if_getdrvflags(ifp); 4043 /* stop the driver and free any clusters before proceeding */ 4044 iflib_stop(ctx); 4045 4046 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4047 STATE_LOCK(ctx); 4048 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4049 ctx->ifc_flags |= IFC_MULTISEG; 4050 else 4051 ctx->ifc_flags &= ~IFC_MULTISEG; 4052 STATE_UNLOCK(ctx); 4053 err = if_setmtu(ifp, ifr->ifr_mtu); 4054 } 4055 iflib_init_locked(ctx); 4056 STATE_LOCK(ctx); 4057 if_setdrvflags(ifp, bits); 4058 STATE_UNLOCK(ctx); 4059 CTX_UNLOCK(ctx); 4060 break; 4061 case SIOCSIFFLAGS: 4062 CTX_LOCK(ctx); 4063 if (if_getflags(ifp) & IFF_UP) { 4064 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4065 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4066 (IFF_PROMISC | IFF_ALLMULTI)) { 4067 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4068 } 4069 } else 4070 reinit = 1; 4071 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4072 iflib_stop(ctx); 4073 } 4074 ctx->ifc_if_flags = if_getflags(ifp); 4075 CTX_UNLOCK(ctx); 4076 break; 4077 case SIOCADDMULTI: 4078 case SIOCDELMULTI: 4079 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4080 CTX_LOCK(ctx); 4081 IFDI_INTR_DISABLE(ctx); 4082 IFDI_MULTI_SET(ctx); 4083 IFDI_INTR_ENABLE(ctx); 4084 CTX_UNLOCK(ctx); 4085 } 4086 break; 4087 case SIOCSIFMEDIA: 4088 CTX_LOCK(ctx); 4089 IFDI_MEDIA_SET(ctx); 4090 CTX_UNLOCK(ctx); 4091 /* falls thru */ 4092 case SIOCGIFMEDIA: 4093 case SIOCGIFXMEDIA: 4094 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 4095 break; 4096 case SIOCGI2C: 4097 { 4098 struct ifi2creq i2c; 4099 4100 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4101 if (err != 0) 4102 break; 4103 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4104 err = EINVAL; 4105 break; 4106 } 4107 if (i2c.len > sizeof(i2c.data)) { 4108 err = EINVAL; 4109 break; 4110 } 4111 4112 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4113 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4114 sizeof(i2c)); 4115 break; 4116 } 4117 case SIOCSIFCAP: 4118 { 4119 int mask, setmask; 4120 4121 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 4122 setmask = 0; 4123 #ifdef TCP_OFFLOAD 4124 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4125 #endif 4126 setmask |= (mask & IFCAP_FLAGS); 4127 4128 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 4129 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4130 if ((mask & IFCAP_WOL) && 4131 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 4132 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 4133 if_vlancap(ifp); 4134 /* 4135 * want to ensure that traffic has stopped before we change any of the flags 4136 */ 4137 if (setmask) { 4138 CTX_LOCK(ctx); 4139 bits = if_getdrvflags(ifp); 4140 if (bits & IFF_DRV_RUNNING) 4141 iflib_stop(ctx); 4142 STATE_LOCK(ctx); 4143 if_togglecapenable(ifp, setmask); 4144 STATE_UNLOCK(ctx); 4145 if (bits & IFF_DRV_RUNNING) 4146 iflib_init_locked(ctx); 4147 STATE_LOCK(ctx); 4148 if_setdrvflags(ifp, bits); 4149 STATE_UNLOCK(ctx); 4150 CTX_UNLOCK(ctx); 4151 } 4152 break; 4153 } 4154 case SIOCGPRIVATE_0: 4155 case SIOCSDRVSPEC: 4156 case SIOCGDRVSPEC: 4157 CTX_LOCK(ctx); 4158 err = IFDI_PRIV_IOCTL(ctx, command, data); 4159 CTX_UNLOCK(ctx); 4160 break; 4161 default: 4162 err = ether_ioctl(ifp, command, data); 4163 break; 4164 } 4165 if (reinit) 4166 iflib_if_init(ctx); 4167 return (err); 4168 } 4169 4170 static uint64_t 4171 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4172 { 4173 if_ctx_t ctx = if_getsoftc(ifp); 4174 4175 return (IFDI_GET_COUNTER(ctx, cnt)); 4176 } 4177 4178 /********************************************************************* 4179 * 4180 * OTHER FUNCTIONS EXPORTED TO THE STACK 4181 * 4182 **********************************************************************/ 4183 4184 static void 4185 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4186 { 4187 if_ctx_t ctx = if_getsoftc(ifp); 4188 4189 if ((void *)ctx != arg) 4190 return; 4191 4192 if ((vtag == 0) || (vtag > 4095)) 4193 return; 4194 4195 CTX_LOCK(ctx); 4196 IFDI_VLAN_REGISTER(ctx, vtag); 4197 /* Re-init to load the changes */ 4198 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4199 iflib_if_init_locked(ctx); 4200 CTX_UNLOCK(ctx); 4201 } 4202 4203 static void 4204 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4205 { 4206 if_ctx_t ctx = if_getsoftc(ifp); 4207 4208 if ((void *)ctx != arg) 4209 return; 4210 4211 if ((vtag == 0) || (vtag > 4095)) 4212 return; 4213 4214 CTX_LOCK(ctx); 4215 IFDI_VLAN_UNREGISTER(ctx, vtag); 4216 /* Re-init to load the changes */ 4217 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4218 iflib_if_init_locked(ctx); 4219 CTX_UNLOCK(ctx); 4220 } 4221 4222 static void 4223 iflib_led_func(void *arg, int onoff) 4224 { 4225 if_ctx_t ctx = arg; 4226 4227 CTX_LOCK(ctx); 4228 IFDI_LED_FUNC(ctx, onoff); 4229 CTX_UNLOCK(ctx); 4230 } 4231 4232 /********************************************************************* 4233 * 4234 * BUS FUNCTION DEFINITIONS 4235 * 4236 **********************************************************************/ 4237 4238 int 4239 iflib_device_probe(device_t dev) 4240 { 4241 pci_vendor_info_t *ent; 4242 4243 uint16_t pci_vendor_id, pci_device_id; 4244 uint16_t pci_subvendor_id, pci_subdevice_id; 4245 uint16_t pci_rev_id; 4246 if_shared_ctx_t sctx; 4247 4248 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4249 return (ENOTSUP); 4250 4251 pci_vendor_id = pci_get_vendor(dev); 4252 pci_device_id = pci_get_device(dev); 4253 pci_subvendor_id = pci_get_subvendor(dev); 4254 pci_subdevice_id = pci_get_subdevice(dev); 4255 pci_rev_id = pci_get_revid(dev); 4256 if (sctx->isc_parse_devinfo != NULL) 4257 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4258 4259 ent = sctx->isc_vendor_info; 4260 while (ent->pvi_vendor_id != 0) { 4261 if (pci_vendor_id != ent->pvi_vendor_id) { 4262 ent++; 4263 continue; 4264 } 4265 if ((pci_device_id == ent->pvi_device_id) && 4266 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4267 (ent->pvi_subvendor_id == 0)) && 4268 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4269 (ent->pvi_subdevice_id == 0)) && 4270 ((pci_rev_id == ent->pvi_rev_id) || 4271 (ent->pvi_rev_id == 0))) { 4272 4273 device_set_desc_copy(dev, ent->pvi_name); 4274 /* this needs to be changed to zero if the bus probing code 4275 * ever stops re-probing on best match because the sctx 4276 * may have its values over written by register calls 4277 * in subsequent probes 4278 */ 4279 return (BUS_PROBE_DEFAULT); 4280 } 4281 ent++; 4282 } 4283 return (ENXIO); 4284 } 4285 4286 static void 4287 iflib_reset_qvalues(if_ctx_t ctx) 4288 { 4289 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4290 if_shared_ctx_t sctx = ctx->ifc_sctx; 4291 device_t dev = ctx->ifc_dev; 4292 int i; 4293 4294 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES; 4295 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH; 4296 /* 4297 * XXX sanity check that ntxd & nrxd are a power of 2 4298 */ 4299 if (ctx->ifc_sysctl_ntxqs != 0) 4300 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4301 if (ctx->ifc_sysctl_nrxqs != 0) 4302 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4303 4304 for (i = 0; i < sctx->isc_ntxqs; i++) { 4305 if (ctx->ifc_sysctl_ntxds[i] != 0) 4306 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4307 else 4308 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4309 } 4310 4311 for (i = 0; i < sctx->isc_nrxqs; i++) { 4312 if (ctx->ifc_sysctl_nrxds[i] != 0) 4313 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4314 else 4315 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4316 } 4317 4318 for (i = 0; i < sctx->isc_nrxqs; i++) { 4319 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4320 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4321 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4322 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4323 } 4324 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4325 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4326 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4327 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4328 } 4329 } 4330 4331 for (i = 0; i < sctx->isc_ntxqs; i++) { 4332 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4333 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4334 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4335 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4336 } 4337 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4338 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4339 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4340 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4341 } 4342 } 4343 } 4344 4345 int 4346 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4347 { 4348 int err, rid, msix; 4349 if_ctx_t ctx; 4350 if_t ifp; 4351 if_softc_ctx_t scctx; 4352 int i; 4353 uint16_t main_txq; 4354 uint16_t main_rxq; 4355 4356 4357 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4358 4359 if (sc == NULL) { 4360 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4361 device_set_softc(dev, ctx); 4362 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4363 } 4364 4365 ctx->ifc_sctx = sctx; 4366 ctx->ifc_dev = dev; 4367 ctx->ifc_softc = sc; 4368 4369 if ((err = iflib_register(ctx)) != 0) { 4370 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4371 free(sc, M_IFLIB); 4372 free(ctx, M_IFLIB); 4373 device_printf(dev, "iflib_register failed %d\n", err); 4374 return (err); 4375 } 4376 iflib_add_device_sysctl_pre(ctx); 4377 4378 scctx = &ctx->ifc_softc_ctx; 4379 ifp = ctx->ifc_ifp; 4380 4381 iflib_reset_qvalues(ctx); 4382 CTX_LOCK(ctx); 4383 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4384 CTX_UNLOCK(ctx); 4385 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4386 return (err); 4387 } 4388 _iflib_pre_assert(scctx); 4389 ctx->ifc_txrx = *scctx->isc_txrx; 4390 4391 #ifdef INVARIANTS 4392 MPASS(scctx->isc_capenable); 4393 if (scctx->isc_capenable & IFCAP_TXCSUM) 4394 MPASS(scctx->isc_tx_csum_flags); 4395 #endif 4396 4397 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4398 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4399 4400 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4401 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4402 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4403 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4404 4405 #ifdef ACPI_DMAR 4406 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4407 ctx->ifc_flags |= IFC_DMAR; 4408 #elif !(defined(__i386__) || defined(__amd64__)) 4409 /* set unconditionally for !x86 */ 4410 ctx->ifc_flags |= IFC_DMAR; 4411 #endif 4412 4413 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4414 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4415 4416 /* XXX change for per-queue sizes */ 4417 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4418 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4419 for (i = 0; i < sctx->isc_nrxqs; i++) { 4420 if (!powerof2(scctx->isc_nrxd[i])) { 4421 /* round down instead? */ 4422 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4423 err = EINVAL; 4424 goto fail; 4425 } 4426 } 4427 for (i = 0; i < sctx->isc_ntxqs; i++) { 4428 if (!powerof2(scctx->isc_ntxd[i])) { 4429 device_printf(dev, 4430 "# tx descriptors must be a power of 2"); 4431 err = EINVAL; 4432 goto fail; 4433 } 4434 } 4435 4436 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4437 MAX_SINGLE_PACKET_FRACTION) 4438 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4439 MAX_SINGLE_PACKET_FRACTION); 4440 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4441 MAX_SINGLE_PACKET_FRACTION) 4442 scctx->isc_tx_tso_segments_max = max(1, 4443 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4444 4445 /* 4446 * Protect the stack against modern hardware 4447 */ 4448 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4449 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4450 4451 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4452 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4453 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4454 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4455 if (scctx->isc_rss_table_size == 0) 4456 scctx->isc_rss_table_size = 64; 4457 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4458 4459 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4460 /* XXX format name */ 4461 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4462 4463 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4464 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4465 device_printf(dev, "Unable to fetch CPU list\n"); 4466 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4467 } 4468 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4469 4470 /* 4471 ** Now setup MSI or MSI/X, should 4472 ** return us the number of supported 4473 ** vectors. (Will be 1 for MSI) 4474 */ 4475 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4476 msix = scctx->isc_vectors; 4477 } else if (scctx->isc_msix_bar != 0) 4478 /* 4479 * The simple fact that isc_msix_bar is not 0 does not mean we 4480 * we have a good value there that is known to work. 4481 */ 4482 msix = iflib_msix_init(ctx); 4483 else { 4484 scctx->isc_vectors = 1; 4485 scctx->isc_ntxqsets = 1; 4486 scctx->isc_nrxqsets = 1; 4487 scctx->isc_intr = IFLIB_INTR_LEGACY; 4488 msix = 0; 4489 } 4490 /* Get memory for the station queues */ 4491 if ((err = iflib_queues_alloc(ctx))) { 4492 device_printf(dev, "Unable to allocate queue memory\n"); 4493 goto fail; 4494 } 4495 4496 if ((err = iflib_qset_structures_setup(ctx))) 4497 goto fail_queues; 4498 4499 /* 4500 * Group taskqueues aren't properly set up until SMP is started, 4501 * so we disable interrupts until we can handle them post 4502 * SI_SUB_SMP. 4503 * 4504 * XXX: disabling interrupts doesn't actually work, at least for 4505 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4506 * we do null handling and depend on this not causing too large an 4507 * interrupt storm. 4508 */ 4509 IFDI_INTR_DISABLE(ctx); 4510 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4511 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4512 goto fail_intr_free; 4513 } 4514 if (msix <= 1) { 4515 rid = 0; 4516 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4517 MPASS(msix == 1); 4518 rid = 1; 4519 } 4520 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4521 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4522 goto fail_intr_free; 4523 } 4524 } 4525 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4526 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4527 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4528 goto fail_detach; 4529 } 4530 if ((err = iflib_netmap_attach(ctx))) { 4531 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4532 goto fail_detach; 4533 } 4534 *ctxp = ctx; 4535 4536 NETDUMP_SET(ctx->ifc_ifp, iflib); 4537 4538 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4539 iflib_add_device_sysctl_post(ctx); 4540 ctx->ifc_flags |= IFC_INIT_DONE; 4541 CTX_UNLOCK(ctx); 4542 return (0); 4543 fail_detach: 4544 ether_ifdetach(ctx->ifc_ifp); 4545 fail_intr_free: 4546 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4547 pci_release_msi(ctx->ifc_dev); 4548 fail_queues: 4549 iflib_tx_structures_free(ctx); 4550 iflib_rx_structures_free(ctx); 4551 fail: 4552 IFDI_DETACH(ctx); 4553 CTX_UNLOCK(ctx); 4554 return (err); 4555 } 4556 4557 int 4558 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4559 struct iflib_cloneattach_ctx *clctx) 4560 { 4561 int err; 4562 if_ctx_t ctx; 4563 if_t ifp; 4564 if_softc_ctx_t scctx; 4565 int i; 4566 void *sc; 4567 uint16_t main_txq; 4568 uint16_t main_rxq; 4569 4570 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4571 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4572 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4573 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4574 ctx->ifc_flags |= IFC_PSEUDO; 4575 4576 ctx->ifc_sctx = sctx; 4577 ctx->ifc_softc = sc; 4578 ctx->ifc_dev = dev; 4579 4580 if ((err = iflib_register(ctx)) != 0) { 4581 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4582 free(sc, M_IFLIB); 4583 free(ctx, M_IFLIB); 4584 return (err); 4585 } 4586 iflib_add_device_sysctl_pre(ctx); 4587 4588 scctx = &ctx->ifc_softc_ctx; 4589 ifp = ctx->ifc_ifp; 4590 4591 /* 4592 * XXX sanity check that ntxd & nrxd are a power of 2 4593 */ 4594 iflib_reset_qvalues(ctx); 4595 4596 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4597 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4598 return (err); 4599 } 4600 if (sctx->isc_flags & IFLIB_GEN_MAC) 4601 iflib_gen_mac(ctx); 4602 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4603 clctx->cc_params)) != 0) { 4604 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4605 return (err); 4606 } 4607 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4608 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 4609 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO); 4610 4611 #ifdef INVARIANTS 4612 MPASS(scctx->isc_capenable); 4613 if (scctx->isc_capenable & IFCAP_TXCSUM) 4614 MPASS(scctx->isc_tx_csum_flags); 4615 #endif 4616 4617 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4618 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4619 4620 ifp->if_flags |= IFF_NOGROUP; 4621 if (sctx->isc_flags & IFLIB_PSEUDO) { 4622 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4623 4624 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4625 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4626 goto fail_detach; 4627 } 4628 *ctxp = ctx; 4629 4630 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4631 iflib_add_device_sysctl_post(ctx); 4632 ctx->ifc_flags |= IFC_INIT_DONE; 4633 return (0); 4634 } 4635 _iflib_pre_assert(scctx); 4636 ctx->ifc_txrx = *scctx->isc_txrx; 4637 4638 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4639 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4640 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4641 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4642 4643 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4644 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4645 4646 /* XXX change for per-queue sizes */ 4647 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4648 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4649 for (i = 0; i < sctx->isc_nrxqs; i++) { 4650 if (!powerof2(scctx->isc_nrxd[i])) { 4651 /* round down instead? */ 4652 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4653 err = EINVAL; 4654 goto fail; 4655 } 4656 } 4657 for (i = 0; i < sctx->isc_ntxqs; i++) { 4658 if (!powerof2(scctx->isc_ntxd[i])) { 4659 device_printf(dev, 4660 "# tx descriptors must be a power of 2"); 4661 err = EINVAL; 4662 goto fail; 4663 } 4664 } 4665 4666 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4667 MAX_SINGLE_PACKET_FRACTION) 4668 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4669 MAX_SINGLE_PACKET_FRACTION); 4670 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4671 MAX_SINGLE_PACKET_FRACTION) 4672 scctx->isc_tx_tso_segments_max = max(1, 4673 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4674 4675 /* 4676 * Protect the stack against modern hardware 4677 */ 4678 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4679 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4680 4681 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4682 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4683 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4684 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4685 if (scctx->isc_rss_table_size == 0) 4686 scctx->isc_rss_table_size = 64; 4687 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4688 4689 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4690 /* XXX format name */ 4691 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4692 4693 /* XXX --- can support > 1 -- but keep it simple for now */ 4694 scctx->isc_intr = IFLIB_INTR_LEGACY; 4695 4696 /* Get memory for the station queues */ 4697 if ((err = iflib_queues_alloc(ctx))) { 4698 device_printf(dev, "Unable to allocate queue memory\n"); 4699 goto fail; 4700 } 4701 4702 if ((err = iflib_qset_structures_setup(ctx))) { 4703 device_printf(dev, "qset structure setup failed %d\n", err); 4704 goto fail_queues; 4705 } 4706 /* 4707 * XXX What if anything do we want to do about interrupts? 4708 */ 4709 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4710 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4711 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4712 goto fail_detach; 4713 } 4714 /* XXX handle more than one queue */ 4715 for (i = 0; i < scctx->isc_nrxqsets; i++) 4716 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4717 4718 *ctxp = ctx; 4719 4720 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4721 iflib_add_device_sysctl_post(ctx); 4722 ctx->ifc_flags |= IFC_INIT_DONE; 4723 return (0); 4724 fail_detach: 4725 ether_ifdetach(ctx->ifc_ifp); 4726 fail_queues: 4727 iflib_tx_structures_free(ctx); 4728 iflib_rx_structures_free(ctx); 4729 fail: 4730 IFDI_DETACH(ctx); 4731 return (err); 4732 } 4733 4734 int 4735 iflib_pseudo_deregister(if_ctx_t ctx) 4736 { 4737 if_t ifp = ctx->ifc_ifp; 4738 iflib_txq_t txq; 4739 iflib_rxq_t rxq; 4740 int i, j; 4741 struct taskqgroup *tqg; 4742 iflib_fl_t fl; 4743 4744 /* Unregister VLAN events */ 4745 if (ctx->ifc_vlan_attach_event != NULL) 4746 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4747 if (ctx->ifc_vlan_detach_event != NULL) 4748 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4749 4750 ether_ifdetach(ifp); 4751 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4752 CTX_LOCK_DESTROY(ctx); 4753 /* XXX drain any dependent tasks */ 4754 tqg = qgroup_if_io_tqg; 4755 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4756 callout_drain(&txq->ift_timer); 4757 if (txq->ift_task.gt_uniq != NULL) 4758 taskqgroup_detach(tqg, &txq->ift_task); 4759 } 4760 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4761 if (rxq->ifr_task.gt_uniq != NULL) 4762 taskqgroup_detach(tqg, &rxq->ifr_task); 4763 4764 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4765 free(fl->ifl_rx_bitmap, M_IFLIB); 4766 } 4767 tqg = qgroup_if_config_tqg; 4768 if (ctx->ifc_admin_task.gt_uniq != NULL) 4769 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4770 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4771 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4772 4773 if_free(ifp); 4774 4775 iflib_tx_structures_free(ctx); 4776 iflib_rx_structures_free(ctx); 4777 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4778 free(ctx->ifc_softc, M_IFLIB); 4779 free(ctx, M_IFLIB); 4780 return (0); 4781 } 4782 4783 int 4784 iflib_device_attach(device_t dev) 4785 { 4786 if_ctx_t ctx; 4787 if_shared_ctx_t sctx; 4788 4789 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4790 return (ENOTSUP); 4791 4792 pci_enable_busmaster(dev); 4793 4794 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4795 } 4796 4797 int 4798 iflib_device_deregister(if_ctx_t ctx) 4799 { 4800 if_t ifp = ctx->ifc_ifp; 4801 iflib_txq_t txq; 4802 iflib_rxq_t rxq; 4803 device_t dev = ctx->ifc_dev; 4804 int i, j; 4805 struct taskqgroup *tqg; 4806 iflib_fl_t fl; 4807 4808 /* Make sure VLANS are not using driver */ 4809 if (if_vlantrunkinuse(ifp)) { 4810 device_printf(dev,"Vlan in use, detach first\n"); 4811 return (EBUSY); 4812 } 4813 4814 CTX_LOCK(ctx); 4815 ctx->ifc_in_detach = 1; 4816 iflib_stop(ctx); 4817 CTX_UNLOCK(ctx); 4818 4819 /* Unregister VLAN events */ 4820 if (ctx->ifc_vlan_attach_event != NULL) 4821 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4822 if (ctx->ifc_vlan_detach_event != NULL) 4823 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4824 4825 iflib_netmap_detach(ifp); 4826 ether_ifdetach(ifp); 4827 if (ctx->ifc_led_dev != NULL) 4828 led_destroy(ctx->ifc_led_dev); 4829 /* XXX drain any dependent tasks */ 4830 tqg = qgroup_if_io_tqg; 4831 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4832 callout_drain(&txq->ift_timer); 4833 if (txq->ift_task.gt_uniq != NULL) 4834 taskqgroup_detach(tqg, &txq->ift_task); 4835 } 4836 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4837 if (rxq->ifr_task.gt_uniq != NULL) 4838 taskqgroup_detach(tqg, &rxq->ifr_task); 4839 4840 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4841 free(fl->ifl_rx_bitmap, M_IFLIB); 4842 4843 } 4844 tqg = qgroup_if_config_tqg; 4845 if (ctx->ifc_admin_task.gt_uniq != NULL) 4846 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4847 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4848 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4849 CTX_LOCK(ctx); 4850 IFDI_DETACH(ctx); 4851 CTX_UNLOCK(ctx); 4852 4853 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4854 CTX_LOCK_DESTROY(ctx); 4855 device_set_softc(ctx->ifc_dev, NULL); 4856 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4857 pci_release_msi(dev); 4858 } 4859 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4860 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4861 } 4862 if (ctx->ifc_msix_mem != NULL) { 4863 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4864 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4865 ctx->ifc_msix_mem = NULL; 4866 } 4867 4868 bus_generic_detach(dev); 4869 if_free(ifp); 4870 4871 iflib_tx_structures_free(ctx); 4872 iflib_rx_structures_free(ctx); 4873 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4874 free(ctx->ifc_softc, M_IFLIB); 4875 free(ctx, M_IFLIB); 4876 return (0); 4877 } 4878 4879 4880 int 4881 iflib_device_detach(device_t dev) 4882 { 4883 if_ctx_t ctx = device_get_softc(dev); 4884 4885 return (iflib_device_deregister(ctx)); 4886 } 4887 4888 int 4889 iflib_device_suspend(device_t dev) 4890 { 4891 if_ctx_t ctx = device_get_softc(dev); 4892 4893 CTX_LOCK(ctx); 4894 IFDI_SUSPEND(ctx); 4895 CTX_UNLOCK(ctx); 4896 4897 return bus_generic_suspend(dev); 4898 } 4899 int 4900 iflib_device_shutdown(device_t dev) 4901 { 4902 if_ctx_t ctx = device_get_softc(dev); 4903 4904 CTX_LOCK(ctx); 4905 IFDI_SHUTDOWN(ctx); 4906 CTX_UNLOCK(ctx); 4907 4908 return bus_generic_suspend(dev); 4909 } 4910 4911 4912 int 4913 iflib_device_resume(device_t dev) 4914 { 4915 if_ctx_t ctx = device_get_softc(dev); 4916 iflib_txq_t txq = ctx->ifc_txqs; 4917 4918 CTX_LOCK(ctx); 4919 IFDI_RESUME(ctx); 4920 iflib_init_locked(ctx); 4921 CTX_UNLOCK(ctx); 4922 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4923 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4924 4925 return (bus_generic_resume(dev)); 4926 } 4927 4928 int 4929 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4930 { 4931 int error; 4932 if_ctx_t ctx = device_get_softc(dev); 4933 4934 CTX_LOCK(ctx); 4935 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4936 CTX_UNLOCK(ctx); 4937 4938 return (error); 4939 } 4940 4941 void 4942 iflib_device_iov_uninit(device_t dev) 4943 { 4944 if_ctx_t ctx = device_get_softc(dev); 4945 4946 CTX_LOCK(ctx); 4947 IFDI_IOV_UNINIT(ctx); 4948 CTX_UNLOCK(ctx); 4949 } 4950 4951 int 4952 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 4953 { 4954 int error; 4955 if_ctx_t ctx = device_get_softc(dev); 4956 4957 CTX_LOCK(ctx); 4958 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 4959 CTX_UNLOCK(ctx); 4960 4961 return (error); 4962 } 4963 4964 /********************************************************************* 4965 * 4966 * MODULE FUNCTION DEFINITIONS 4967 * 4968 **********************************************************************/ 4969 4970 /* 4971 * - Start a fast taskqueue thread for each core 4972 * - Start a taskqueue for control operations 4973 */ 4974 static int 4975 iflib_module_init(void) 4976 { 4977 return (0); 4978 } 4979 4980 static int 4981 iflib_module_event_handler(module_t mod, int what, void *arg) 4982 { 4983 int err; 4984 4985 switch (what) { 4986 case MOD_LOAD: 4987 if ((err = iflib_module_init()) != 0) 4988 return (err); 4989 break; 4990 case MOD_UNLOAD: 4991 return (EBUSY); 4992 default: 4993 return (EOPNOTSUPP); 4994 } 4995 4996 return (0); 4997 } 4998 4999 /********************************************************************* 5000 * 5001 * PUBLIC FUNCTION DEFINITIONS 5002 * ordered as in iflib.h 5003 * 5004 **********************************************************************/ 5005 5006 5007 static void 5008 _iflib_assert(if_shared_ctx_t sctx) 5009 { 5010 MPASS(sctx->isc_tx_maxsize); 5011 MPASS(sctx->isc_tx_maxsegsize); 5012 5013 MPASS(sctx->isc_rx_maxsize); 5014 MPASS(sctx->isc_rx_nsegments); 5015 MPASS(sctx->isc_rx_maxsegsize); 5016 5017 MPASS(sctx->isc_nrxd_min[0]); 5018 MPASS(sctx->isc_nrxd_max[0]); 5019 MPASS(sctx->isc_nrxd_default[0]); 5020 MPASS(sctx->isc_ntxd_min[0]); 5021 MPASS(sctx->isc_ntxd_max[0]); 5022 MPASS(sctx->isc_ntxd_default[0]); 5023 } 5024 5025 static void 5026 _iflib_pre_assert(if_softc_ctx_t scctx) 5027 { 5028 5029 MPASS(scctx->isc_txrx->ift_txd_encap); 5030 MPASS(scctx->isc_txrx->ift_txd_flush); 5031 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5032 MPASS(scctx->isc_txrx->ift_rxd_available); 5033 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5034 MPASS(scctx->isc_txrx->ift_rxd_refill); 5035 MPASS(scctx->isc_txrx->ift_rxd_flush); 5036 } 5037 5038 static int 5039 iflib_register(if_ctx_t ctx) 5040 { 5041 if_shared_ctx_t sctx = ctx->ifc_sctx; 5042 driver_t *driver = sctx->isc_driver; 5043 device_t dev = ctx->ifc_dev; 5044 if_t ifp; 5045 5046 _iflib_assert(sctx); 5047 5048 CTX_LOCK_INIT(ctx); 5049 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5050 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 5051 if (ifp == NULL) { 5052 device_printf(dev, "can not allocate ifnet structure\n"); 5053 return (ENOMEM); 5054 } 5055 5056 /* 5057 * Initialize our context's device specific methods 5058 */ 5059 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5060 kobj_class_compile((kobj_class_t) driver); 5061 driver->refs++; 5062 5063 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5064 if_setsoftc(ifp, ctx); 5065 if_setdev(ifp, dev); 5066 if_setinitfn(ifp, iflib_if_init); 5067 if_setioctlfn(ifp, iflib_if_ioctl); 5068 if_settransmitfn(ifp, iflib_if_transmit); 5069 if_setqflushfn(ifp, iflib_if_qflush); 5070 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5071 5072 ctx->ifc_vlan_attach_event = 5073 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5074 EVENTHANDLER_PRI_FIRST); 5075 ctx->ifc_vlan_detach_event = 5076 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5077 EVENTHANDLER_PRI_FIRST); 5078 5079 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 5080 iflib_media_change, iflib_media_status); 5081 5082 return (0); 5083 } 5084 5085 5086 static int 5087 iflib_queues_alloc(if_ctx_t ctx) 5088 { 5089 if_shared_ctx_t sctx = ctx->ifc_sctx; 5090 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5091 device_t dev = ctx->ifc_dev; 5092 int nrxqsets = scctx->isc_nrxqsets; 5093 int ntxqsets = scctx->isc_ntxqsets; 5094 iflib_txq_t txq; 5095 iflib_rxq_t rxq; 5096 iflib_fl_t fl = NULL; 5097 int i, j, cpu, err, txconf, rxconf; 5098 iflib_dma_info_t ifdip; 5099 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5100 uint32_t *txqsizes = scctx->isc_txqsizes; 5101 uint8_t nrxqs = sctx->isc_nrxqs; 5102 uint8_t ntxqs = sctx->isc_ntxqs; 5103 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5104 caddr_t *vaddrs; 5105 uint64_t *paddrs; 5106 5107 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5108 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5109 5110 /* Allocate the TX ring struct memory */ 5111 if (!(ctx->ifc_txqs = 5112 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5113 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5114 device_printf(dev, "Unable to allocate TX ring memory\n"); 5115 err = ENOMEM; 5116 goto fail; 5117 } 5118 5119 /* Now allocate the RX */ 5120 if (!(ctx->ifc_rxqs = 5121 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5122 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5123 device_printf(dev, "Unable to allocate RX ring memory\n"); 5124 err = ENOMEM; 5125 goto rx_fail; 5126 } 5127 5128 txq = ctx->ifc_txqs; 5129 rxq = ctx->ifc_rxqs; 5130 5131 /* 5132 * XXX handle allocation failure 5133 */ 5134 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5135 /* Set up some basics */ 5136 5137 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 5138 device_printf(dev, "failed to allocate iflib_dma_info\n"); 5139 err = ENOMEM; 5140 goto err_tx_desc; 5141 } 5142 txq->ift_ifdi = ifdip; 5143 for (j = 0; j < ntxqs; j++, ifdip++) { 5144 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 5145 device_printf(dev, "Unable to allocate Descriptor memory\n"); 5146 err = ENOMEM; 5147 goto err_tx_desc; 5148 } 5149 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5150 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5151 } 5152 txq->ift_ctx = ctx; 5153 txq->ift_id = i; 5154 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5155 txq->ift_br_offset = 1; 5156 } else { 5157 txq->ift_br_offset = 0; 5158 } 5159 /* XXX fix this */ 5160 txq->ift_timer.c_cpu = cpu; 5161 5162 if (iflib_txsd_alloc(txq)) { 5163 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5164 err = ENOMEM; 5165 goto err_tx_desc; 5166 } 5167 5168 /* Initialize the TX lock */ 5169 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 5170 device_get_nameunit(dev), txq->ift_id); 5171 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5172 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5173 5174 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 5175 device_get_nameunit(dev), txq->ift_id); 5176 5177 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5178 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5179 if (err) { 5180 /* XXX free any allocated rings */ 5181 device_printf(dev, "Unable to allocate buf_ring\n"); 5182 goto err_tx_desc; 5183 } 5184 } 5185 5186 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5187 /* Set up some basics */ 5188 5189 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 5190 device_printf(dev, "failed to allocate iflib_dma_info\n"); 5191 err = ENOMEM; 5192 goto err_tx_desc; 5193 } 5194 5195 rxq->ifr_ifdi = ifdip; 5196 /* XXX this needs to be changed if #rx queues != #tx queues */ 5197 rxq->ifr_ntxqirq = 1; 5198 rxq->ifr_txqid[0] = i; 5199 for (j = 0; j < nrxqs; j++, ifdip++) { 5200 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 5201 device_printf(dev, "Unable to allocate Descriptor memory\n"); 5202 err = ENOMEM; 5203 goto err_tx_desc; 5204 } 5205 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5206 } 5207 rxq->ifr_ctx = ctx; 5208 rxq->ifr_id = i; 5209 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5210 rxq->ifr_fl_offset = 1; 5211 } else { 5212 rxq->ifr_fl_offset = 0; 5213 } 5214 rxq->ifr_nfl = nfree_lists; 5215 if (!(fl = 5216 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5217 device_printf(dev, "Unable to allocate free list memory\n"); 5218 err = ENOMEM; 5219 goto err_tx_desc; 5220 } 5221 rxq->ifr_fl = fl; 5222 for (j = 0; j < nfree_lists; j++) { 5223 fl[j].ifl_rxq = rxq; 5224 fl[j].ifl_id = j; 5225 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5226 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5227 } 5228 /* Allocate receive buffers for the ring*/ 5229 if (iflib_rxsd_alloc(rxq)) { 5230 device_printf(dev, 5231 "Critical Failure setting up receive buffers\n"); 5232 err = ENOMEM; 5233 goto err_rx_desc; 5234 } 5235 5236 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5237 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 5238 } 5239 5240 /* TXQs */ 5241 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5242 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5243 for (i = 0; i < ntxqsets; i++) { 5244 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5245 5246 for (j = 0; j < ntxqs; j++, di++) { 5247 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5248 paddrs[i*ntxqs + j] = di->idi_paddr; 5249 } 5250 } 5251 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5252 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 5253 iflib_tx_structures_free(ctx); 5254 free(vaddrs, M_IFLIB); 5255 free(paddrs, M_IFLIB); 5256 goto err_rx_desc; 5257 } 5258 free(vaddrs, M_IFLIB); 5259 free(paddrs, M_IFLIB); 5260 5261 /* RXQs */ 5262 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5263 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5264 for (i = 0; i < nrxqsets; i++) { 5265 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5266 5267 for (j = 0; j < nrxqs; j++, di++) { 5268 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5269 paddrs[i*nrxqs + j] = di->idi_paddr; 5270 } 5271 } 5272 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5273 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 5274 iflib_tx_structures_free(ctx); 5275 free(vaddrs, M_IFLIB); 5276 free(paddrs, M_IFLIB); 5277 goto err_rx_desc; 5278 } 5279 free(vaddrs, M_IFLIB); 5280 free(paddrs, M_IFLIB); 5281 5282 return (0); 5283 5284 /* XXX handle allocation failure changes */ 5285 err_rx_desc: 5286 err_tx_desc: 5287 rx_fail: 5288 if (ctx->ifc_rxqs != NULL) 5289 free(ctx->ifc_rxqs, M_IFLIB); 5290 ctx->ifc_rxqs = NULL; 5291 if (ctx->ifc_txqs != NULL) 5292 free(ctx->ifc_txqs, M_IFLIB); 5293 ctx->ifc_txqs = NULL; 5294 fail: 5295 return (err); 5296 } 5297 5298 static int 5299 iflib_tx_structures_setup(if_ctx_t ctx) 5300 { 5301 iflib_txq_t txq = ctx->ifc_txqs; 5302 int i; 5303 5304 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5305 iflib_txq_setup(txq); 5306 5307 return (0); 5308 } 5309 5310 static void 5311 iflib_tx_structures_free(if_ctx_t ctx) 5312 { 5313 iflib_txq_t txq = ctx->ifc_txqs; 5314 int i, j; 5315 5316 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5317 iflib_txq_destroy(txq); 5318 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 5319 iflib_dma_free(&txq->ift_ifdi[j]); 5320 } 5321 free(ctx->ifc_txqs, M_IFLIB); 5322 ctx->ifc_txqs = NULL; 5323 IFDI_QUEUES_FREE(ctx); 5324 } 5325 5326 /********************************************************************* 5327 * 5328 * Initialize all receive rings. 5329 * 5330 **********************************************************************/ 5331 static int 5332 iflib_rx_structures_setup(if_ctx_t ctx) 5333 { 5334 iflib_rxq_t rxq = ctx->ifc_rxqs; 5335 int q; 5336 #if defined(INET6) || defined(INET) 5337 int i, err; 5338 #endif 5339 5340 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5341 #if defined(INET6) || defined(INET) 5342 tcp_lro_free(&rxq->ifr_lc); 5343 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5344 TCP_LRO_ENTRIES, min(1024, 5345 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 5346 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 5347 goto fail; 5348 } 5349 rxq->ifr_lro_enabled = TRUE; 5350 #endif 5351 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5352 } 5353 return (0); 5354 #if defined(INET6) || defined(INET) 5355 fail: 5356 /* 5357 * Free RX software descriptors allocated so far, we will only handle 5358 * the rings that completed, the failing case will have 5359 * cleaned up for itself. 'q' failed, so its the terminus. 5360 */ 5361 rxq = ctx->ifc_rxqs; 5362 for (i = 0; i < q; ++i, rxq++) { 5363 iflib_rx_sds_free(rxq); 5364 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5365 } 5366 return (err); 5367 #endif 5368 } 5369 5370 /********************************************************************* 5371 * 5372 * Free all receive rings. 5373 * 5374 **********************************************************************/ 5375 static void 5376 iflib_rx_structures_free(if_ctx_t ctx) 5377 { 5378 iflib_rxq_t rxq = ctx->ifc_rxqs; 5379 5380 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5381 iflib_rx_sds_free(rxq); 5382 } 5383 } 5384 5385 static int 5386 iflib_qset_structures_setup(if_ctx_t ctx) 5387 { 5388 int err; 5389 5390 /* 5391 * It is expected that the caller takes care of freeing queues if this 5392 * fails. 5393 */ 5394 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5395 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5396 return (err); 5397 } 5398 5399 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5400 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5401 5402 return (err); 5403 } 5404 5405 int 5406 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5407 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5408 { 5409 5410 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5411 } 5412 5413 #ifdef SMP 5414 static int 5415 find_nth(if_ctx_t ctx, int qid) 5416 { 5417 cpuset_t cpus; 5418 int i, cpuid, eqid, count; 5419 5420 CPU_COPY(&ctx->ifc_cpus, &cpus); 5421 count = CPU_COUNT(&cpus); 5422 eqid = qid % count; 5423 /* clear up to the qid'th bit */ 5424 for (i = 0; i < eqid; i++) { 5425 cpuid = CPU_FFS(&cpus); 5426 MPASS(cpuid != 0); 5427 CPU_CLR(cpuid-1, &cpus); 5428 } 5429 cpuid = CPU_FFS(&cpus); 5430 MPASS(cpuid != 0); 5431 return (cpuid-1); 5432 } 5433 5434 #ifdef SCHED_ULE 5435 extern struct cpu_group *cpu_top; /* CPU topology */ 5436 5437 static int 5438 find_child_with_core(int cpu, struct cpu_group *grp) 5439 { 5440 int i; 5441 5442 if (grp->cg_children == 0) 5443 return -1; 5444 5445 MPASS(grp->cg_child); 5446 for (i = 0; i < grp->cg_children; i++) { 5447 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5448 return i; 5449 } 5450 5451 return -1; 5452 } 5453 5454 /* 5455 * Find the nth "close" core to the specified core 5456 * "close" is defined as the deepest level that shares 5457 * at least an L2 cache. With threads, this will be 5458 * threads on the same core. If the sahred cache is L3 5459 * or higher, simply returns the same core. 5460 */ 5461 static int 5462 find_close_core(int cpu, int core_offset) 5463 { 5464 struct cpu_group *grp; 5465 int i; 5466 int fcpu; 5467 cpuset_t cs; 5468 5469 grp = cpu_top; 5470 if (grp == NULL) 5471 return cpu; 5472 i = 0; 5473 while ((i = find_child_with_core(cpu, grp)) != -1) { 5474 /* If the child only has one cpu, don't descend */ 5475 if (grp->cg_child[i].cg_count <= 1) 5476 break; 5477 grp = &grp->cg_child[i]; 5478 } 5479 5480 /* If they don't share at least an L2 cache, use the same CPU */ 5481 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5482 return cpu; 5483 5484 /* Now pick one */ 5485 CPU_COPY(&grp->cg_mask, &cs); 5486 5487 /* Add the selected CPU offset to core offset. */ 5488 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5489 if (fcpu - 1 == cpu) 5490 break; 5491 CPU_CLR(fcpu - 1, &cs); 5492 } 5493 MPASS(fcpu); 5494 5495 core_offset += i; 5496 5497 CPU_COPY(&grp->cg_mask, &cs); 5498 for (i = core_offset % grp->cg_count; i > 0; i--) { 5499 MPASS(CPU_FFS(&cs)); 5500 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5501 } 5502 MPASS(CPU_FFS(&cs)); 5503 return CPU_FFS(&cs) - 1; 5504 } 5505 #else 5506 static int 5507 find_close_core(int cpu, int core_offset __unused) 5508 { 5509 return cpu; 5510 } 5511 #endif 5512 5513 static int 5514 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5515 { 5516 switch (type) { 5517 case IFLIB_INTR_TX: 5518 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5519 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5520 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5521 case IFLIB_INTR_RX: 5522 case IFLIB_INTR_RXTX: 5523 /* RX queues get the specified core */ 5524 return qid / CPU_COUNT(&ctx->ifc_cpus); 5525 default: 5526 return -1; 5527 } 5528 } 5529 #else 5530 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5531 #define find_close_core(cpuid, tid) CPU_FIRST() 5532 #define find_nth(ctx, gid) CPU_FIRST() 5533 #endif 5534 5535 /* Just to avoid copy/paste */ 5536 static inline int 5537 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid, 5538 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, const char *name) 5539 { 5540 int cpuid; 5541 int err, tid; 5542 5543 cpuid = find_nth(ctx, qid); 5544 tid = get_core_offset(ctx, type, qid); 5545 MPASS(tid >= 0); 5546 cpuid = find_close_core(cpuid, tid); 5547 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name); 5548 if (err) { 5549 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err); 5550 return (err); 5551 } 5552 #ifdef notyet 5553 if (cpuid > ctx->ifc_cpuid_highest) 5554 ctx->ifc_cpuid_highest = cpuid; 5555 #endif 5556 return 0; 5557 } 5558 5559 int 5560 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5561 iflib_intr_type_t type, driver_filter_t *filter, 5562 void *filter_arg, int qid, const char *name) 5563 { 5564 struct grouptask *gtask; 5565 struct taskqgroup *tqg; 5566 iflib_filter_info_t info; 5567 gtask_fn_t *fn; 5568 int tqrid, err; 5569 driver_filter_t *intr_fast; 5570 void *q; 5571 5572 info = &ctx->ifc_filter_info; 5573 tqrid = rid; 5574 5575 switch (type) { 5576 /* XXX merge tx/rx for netmap? */ 5577 case IFLIB_INTR_TX: 5578 q = &ctx->ifc_txqs[qid]; 5579 info = &ctx->ifc_txqs[qid].ift_filter_info; 5580 gtask = &ctx->ifc_txqs[qid].ift_task; 5581 tqg = qgroup_if_io_tqg; 5582 fn = _task_fn_tx; 5583 intr_fast = iflib_fast_intr; 5584 GROUPTASK_INIT(gtask, 0, fn, q); 5585 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5586 break; 5587 case IFLIB_INTR_RX: 5588 q = &ctx->ifc_rxqs[qid]; 5589 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5590 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5591 tqg = qgroup_if_io_tqg; 5592 fn = _task_fn_rx; 5593 intr_fast = iflib_fast_intr; 5594 GROUPTASK_INIT(gtask, 0, fn, q); 5595 break; 5596 case IFLIB_INTR_RXTX: 5597 q = &ctx->ifc_rxqs[qid]; 5598 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5599 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5600 tqg = qgroup_if_io_tqg; 5601 fn = _task_fn_rx; 5602 intr_fast = iflib_fast_intr_rxtx; 5603 GROUPTASK_INIT(gtask, 0, fn, q); 5604 break; 5605 case IFLIB_INTR_ADMIN: 5606 q = ctx; 5607 tqrid = -1; 5608 info = &ctx->ifc_filter_info; 5609 gtask = &ctx->ifc_admin_task; 5610 tqg = qgroup_if_config_tqg; 5611 fn = _task_fn_admin; 5612 intr_fast = iflib_fast_intr_ctx; 5613 break; 5614 default: 5615 panic("unknown net intr type"); 5616 } 5617 5618 info->ifi_filter = filter; 5619 info->ifi_filter_arg = filter_arg; 5620 info->ifi_task = gtask; 5621 info->ifi_ctx = q; 5622 5623 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5624 if (err != 0) { 5625 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 5626 return (err); 5627 } 5628 if (type == IFLIB_INTR_ADMIN) 5629 return (0); 5630 5631 if (tqrid != -1) { 5632 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name); 5633 if (err) 5634 return (err); 5635 } else { 5636 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5637 } 5638 5639 return (0); 5640 } 5641 5642 void 5643 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 5644 { 5645 struct grouptask *gtask; 5646 struct taskqgroup *tqg; 5647 gtask_fn_t *fn; 5648 void *q; 5649 int irq_num = -1; 5650 int err; 5651 5652 switch (type) { 5653 case IFLIB_INTR_TX: 5654 q = &ctx->ifc_txqs[qid]; 5655 gtask = &ctx->ifc_txqs[qid].ift_task; 5656 tqg = qgroup_if_io_tqg; 5657 fn = _task_fn_tx; 5658 if (irq != NULL) 5659 irq_num = rman_get_start(irq->ii_res); 5660 break; 5661 case IFLIB_INTR_RX: 5662 q = &ctx->ifc_rxqs[qid]; 5663 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5664 tqg = qgroup_if_io_tqg; 5665 fn = _task_fn_rx; 5666 if (irq != NULL) 5667 irq_num = rman_get_start(irq->ii_res); 5668 break; 5669 case IFLIB_INTR_IOV: 5670 q = ctx; 5671 gtask = &ctx->ifc_vflr_task; 5672 tqg = qgroup_if_config_tqg; 5673 fn = _task_fn_iov; 5674 break; 5675 default: 5676 panic("unknown net intr type"); 5677 } 5678 GROUPTASK_INIT(gtask, 0, fn, q); 5679 if (irq_num != -1) { 5680 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name); 5681 if (err) 5682 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5683 } 5684 else { 5685 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5686 } 5687 } 5688 5689 void 5690 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5691 { 5692 if (irq->ii_tag) 5693 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5694 5695 if (irq->ii_res) 5696 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5697 } 5698 5699 static int 5700 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 5701 { 5702 iflib_txq_t txq = ctx->ifc_txqs; 5703 iflib_rxq_t rxq = ctx->ifc_rxqs; 5704 if_irq_t irq = &ctx->ifc_legacy_irq; 5705 iflib_filter_info_t info; 5706 struct grouptask *gtask; 5707 struct taskqgroup *tqg; 5708 gtask_fn_t *fn; 5709 int tqrid; 5710 void *q; 5711 int err; 5712 5713 q = &ctx->ifc_rxqs[0]; 5714 info = &rxq[0].ifr_filter_info; 5715 gtask = &rxq[0].ifr_task; 5716 tqg = qgroup_if_io_tqg; 5717 tqrid = irq->ii_rid = *rid; 5718 fn = _task_fn_rx; 5719 5720 ctx->ifc_flags |= IFC_LEGACY; 5721 info->ifi_filter = filter; 5722 info->ifi_filter_arg = filter_arg; 5723 info->ifi_task = gtask; 5724 info->ifi_ctx = ctx; 5725 5726 /* We allocate a single interrupt resource */ 5727 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5728 return (err); 5729 GROUPTASK_INIT(gtask, 0, fn, q); 5730 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5731 5732 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5733 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx"); 5734 return (0); 5735 } 5736 5737 void 5738 iflib_led_create(if_ctx_t ctx) 5739 { 5740 5741 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5742 device_get_nameunit(ctx->ifc_dev)); 5743 } 5744 5745 void 5746 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5747 { 5748 5749 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5750 } 5751 5752 void 5753 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5754 { 5755 5756 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5757 } 5758 5759 void 5760 iflib_admin_intr_deferred(if_ctx_t ctx) 5761 { 5762 #ifdef INVARIANTS 5763 struct grouptask *gtask; 5764 5765 gtask = &ctx->ifc_admin_task; 5766 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5767 #endif 5768 5769 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5770 } 5771 5772 void 5773 iflib_iov_intr_deferred(if_ctx_t ctx) 5774 { 5775 5776 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5777 } 5778 5779 void 5780 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5781 { 5782 5783 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5784 } 5785 5786 void 5787 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 5788 const char *name) 5789 { 5790 5791 GROUPTASK_INIT(gtask, 0, fn, ctx); 5792 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5793 } 5794 5795 void 5796 iflib_config_gtask_deinit(struct grouptask *gtask) 5797 { 5798 5799 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5800 } 5801 5802 void 5803 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5804 { 5805 if_t ifp = ctx->ifc_ifp; 5806 iflib_txq_t txq = ctx->ifc_txqs; 5807 5808 if_setbaudrate(ifp, baudrate); 5809 if (baudrate >= IF_Gbps(10)) { 5810 STATE_LOCK(ctx); 5811 ctx->ifc_flags |= IFC_PREFETCH; 5812 STATE_UNLOCK(ctx); 5813 } 5814 /* If link down, disable watchdog */ 5815 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5816 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5817 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5818 } 5819 ctx->ifc_link_state = link_state; 5820 if_link_state_change(ifp, link_state); 5821 } 5822 5823 static int 5824 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5825 { 5826 int credits; 5827 #ifdef INVARIANTS 5828 int credits_pre = txq->ift_cidx_processed; 5829 #endif 5830 5831 if (ctx->isc_txd_credits_update == NULL) 5832 return (0); 5833 5834 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5835 return (0); 5836 5837 txq->ift_processed += credits; 5838 txq->ift_cidx_processed += credits; 5839 5840 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5841 if (txq->ift_cidx_processed >= txq->ift_size) 5842 txq->ift_cidx_processed -= txq->ift_size; 5843 return (credits); 5844 } 5845 5846 static int 5847 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5848 { 5849 5850 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5851 budget)); 5852 } 5853 5854 void 5855 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5856 const char *description, if_int_delay_info_t info, 5857 int offset, int value) 5858 { 5859 info->iidi_ctx = ctx; 5860 info->iidi_offset = offset; 5861 info->iidi_value = value; 5862 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5863 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5864 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5865 info, 0, iflib_sysctl_int_delay, "I", description); 5866 } 5867 5868 struct sx * 5869 iflib_ctx_lock_get(if_ctx_t ctx) 5870 { 5871 5872 return (&ctx->ifc_ctx_sx); 5873 } 5874 5875 static int 5876 iflib_msix_init(if_ctx_t ctx) 5877 { 5878 device_t dev = ctx->ifc_dev; 5879 if_shared_ctx_t sctx = ctx->ifc_sctx; 5880 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5881 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5882 int iflib_num_tx_queues, iflib_num_rx_queues; 5883 int err, admincnt, bar; 5884 5885 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 5886 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 5887 5888 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 5889 5890 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5891 admincnt = sctx->isc_admin_intrcnt; 5892 /* Override by global tuneable */ 5893 { 5894 int i; 5895 size_t len = sizeof(i); 5896 err = kernel_sysctlbyname(curthread, "hw.pci.enable_msix", &i, &len, NULL, 0, NULL, 0); 5897 if (err == 0) { 5898 if (i == 0) 5899 goto msi; 5900 } 5901 else { 5902 device_printf(dev, "unable to read hw.pci.enable_msix."); 5903 } 5904 } 5905 /* Override by tuneable */ 5906 if (scctx->isc_disable_msix) 5907 goto msi; 5908 5909 /* 5910 ** When used in a virtualized environment 5911 ** PCI BUSMASTER capability may not be set 5912 ** so explicity set it here and rewrite 5913 ** the ENABLE in the MSIX control register 5914 ** at this point to cause the host to 5915 ** successfully initialize us. 5916 */ 5917 { 5918 int msix_ctrl, rid; 5919 5920 pci_enable_busmaster(dev); 5921 rid = 0; 5922 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) { 5923 rid += PCIR_MSIX_CTRL; 5924 msix_ctrl = pci_read_config(dev, rid, 2); 5925 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 5926 pci_write_config(dev, rid, msix_ctrl, 2); 5927 } else { 5928 device_printf(dev, "PCIY_MSIX capability not found; " 5929 "or rid %d == 0.\n", rid); 5930 goto msi; 5931 } 5932 } 5933 5934 /* 5935 * bar == -1 => "trust me I know what I'm doing" 5936 * Some drivers are for hardware that is so shoddily 5937 * documented that no one knows which bars are which 5938 * so the developer has to map all bars. This hack 5939 * allows shoddy garbage to use msix in this framework. 5940 */ 5941 if (bar != -1) { 5942 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5943 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5944 if (ctx->ifc_msix_mem == NULL) { 5945 /* May not be enabled */ 5946 device_printf(dev, "Unable to map MSIX table \n"); 5947 goto msi; 5948 } 5949 } 5950 /* First try MSI/X */ 5951 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5952 device_printf(dev, "System has MSIX disabled \n"); 5953 bus_release_resource(dev, SYS_RES_MEMORY, 5954 bar, ctx->ifc_msix_mem); 5955 ctx->ifc_msix_mem = NULL; 5956 goto msi; 5957 } 5958 #if IFLIB_DEBUG 5959 /* use only 1 qset in debug mode */ 5960 queuemsgs = min(msgs - admincnt, 1); 5961 #else 5962 queuemsgs = msgs - admincnt; 5963 #endif 5964 #ifdef RSS 5965 queues = imin(queuemsgs, rss_getnumbuckets()); 5966 #else 5967 queues = queuemsgs; 5968 #endif 5969 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 5970 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 5971 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 5972 #ifdef RSS 5973 /* If we're doing RSS, clamp at the number of RSS buckets */ 5974 if (queues > rss_getnumbuckets()) 5975 queues = rss_getnumbuckets(); 5976 #endif 5977 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 5978 rx_queues = iflib_num_rx_queues; 5979 else 5980 rx_queues = queues; 5981 5982 if (rx_queues > scctx->isc_nrxqsets) 5983 rx_queues = scctx->isc_nrxqsets; 5984 5985 /* 5986 * We want this to be all logical CPUs by default 5987 */ 5988 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 5989 tx_queues = iflib_num_tx_queues; 5990 else 5991 tx_queues = mp_ncpus; 5992 5993 if (tx_queues > scctx->isc_ntxqsets) 5994 tx_queues = scctx->isc_ntxqsets; 5995 5996 if (ctx->ifc_sysctl_qs_eq_override == 0) { 5997 #ifdef INVARIANTS 5998 if (tx_queues != rx_queues) 5999 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6000 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6001 #endif 6002 tx_queues = min(rx_queues, tx_queues); 6003 rx_queues = min(rx_queues, tx_queues); 6004 } 6005 6006 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 6007 6008 vectors = rx_queues + admincnt; 6009 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6010 device_printf(dev, 6011 "Using MSIX interrupts with %d vectors\n", vectors); 6012 scctx->isc_vectors = vectors; 6013 scctx->isc_nrxqsets = rx_queues; 6014 scctx->isc_ntxqsets = tx_queues; 6015 scctx->isc_intr = IFLIB_INTR_MSIX; 6016 6017 return (vectors); 6018 } else { 6019 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 6020 } 6021 msi: 6022 vectors = pci_msi_count(dev); 6023 scctx->isc_nrxqsets = 1; 6024 scctx->isc_ntxqsets = 1; 6025 scctx->isc_vectors = vectors; 6026 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6027 device_printf(dev,"Using an MSI interrupt\n"); 6028 scctx->isc_intr = IFLIB_INTR_MSI; 6029 } else { 6030 device_printf(dev,"Using a Legacy interrupt\n"); 6031 scctx->isc_intr = IFLIB_INTR_LEGACY; 6032 } 6033 6034 return (vectors); 6035 } 6036 6037 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6038 6039 static int 6040 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6041 { 6042 int rc; 6043 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6044 struct sbuf *sb; 6045 char *ring_state = "UNKNOWN"; 6046 6047 /* XXX needed ? */ 6048 rc = sysctl_wire_old_buffer(req, 0); 6049 MPASS(rc == 0); 6050 if (rc != 0) 6051 return (rc); 6052 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6053 MPASS(sb != NULL); 6054 if (sb == NULL) 6055 return (ENOMEM); 6056 if (state[3] <= 3) 6057 ring_state = ring_states[state[3]]; 6058 6059 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6060 state[0], state[1], state[2], ring_state); 6061 rc = sbuf_finish(sb); 6062 sbuf_delete(sb); 6063 return(rc); 6064 } 6065 6066 enum iflib_ndesc_handler { 6067 IFLIB_NTXD_HANDLER, 6068 IFLIB_NRXD_HANDLER, 6069 }; 6070 6071 static int 6072 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6073 { 6074 if_ctx_t ctx = (void *)arg1; 6075 enum iflib_ndesc_handler type = arg2; 6076 char buf[256] = {0}; 6077 qidx_t *ndesc; 6078 char *p, *next; 6079 int nqs, rc, i; 6080 6081 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 6082 6083 nqs = 8; 6084 switch(type) { 6085 case IFLIB_NTXD_HANDLER: 6086 ndesc = ctx->ifc_sysctl_ntxds; 6087 if (ctx->ifc_sctx) 6088 nqs = ctx->ifc_sctx->isc_ntxqs; 6089 break; 6090 case IFLIB_NRXD_HANDLER: 6091 ndesc = ctx->ifc_sysctl_nrxds; 6092 if (ctx->ifc_sctx) 6093 nqs = ctx->ifc_sctx->isc_nrxqs; 6094 break; 6095 default: 6096 panic("unhandled type"); 6097 } 6098 if (nqs == 0) 6099 nqs = 8; 6100 6101 for (i=0; i<8; i++) { 6102 if (i >= nqs) 6103 break; 6104 if (i) 6105 strcat(buf, ","); 6106 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6107 } 6108 6109 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6110 if (rc || req->newptr == NULL) 6111 return rc; 6112 6113 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6114 i++, p = strsep(&next, " ,")) { 6115 ndesc[i] = strtoul(p, NULL, 10); 6116 } 6117 6118 return(rc); 6119 } 6120 6121 #define NAME_BUFLEN 32 6122 static void 6123 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6124 { 6125 device_t dev = iflib_get_dev(ctx); 6126 struct sysctl_oid_list *child, *oid_list; 6127 struct sysctl_ctx_list *ctx_list; 6128 struct sysctl_oid *node; 6129 6130 ctx_list = device_get_sysctl_ctx(dev); 6131 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6132 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6133 CTLFLAG_RD, NULL, "IFLIB fields"); 6134 oid_list = SYSCTL_CHILDREN(node); 6135 6136 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6137 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 6138 "driver version"); 6139 6140 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6141 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6142 "# of txqs to use, 0 => use default #"); 6143 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6144 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6145 "# of rxqs to use, 0 => use default #"); 6146 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6147 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6148 "permit #txq != #rxq"); 6149 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6150 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6151 "disable MSIX (default 0)"); 6152 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6153 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6154 "set the rx budget"); 6155 6156 /* XXX change for per-queue sizes */ 6157 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6158 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6159 mp_ndesc_handler, "A", 6160 "list of # of tx descriptors to use, 0 = use default #"); 6161 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6162 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6163 mp_ndesc_handler, "A", 6164 "list of # of rx descriptors to use, 0 = use default #"); 6165 } 6166 6167 static void 6168 iflib_add_device_sysctl_post(if_ctx_t ctx) 6169 { 6170 if_shared_ctx_t sctx = ctx->ifc_sctx; 6171 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6172 device_t dev = iflib_get_dev(ctx); 6173 struct sysctl_oid_list *child; 6174 struct sysctl_ctx_list *ctx_list; 6175 iflib_fl_t fl; 6176 iflib_txq_t txq; 6177 iflib_rxq_t rxq; 6178 int i, j; 6179 char namebuf[NAME_BUFLEN]; 6180 char *qfmt; 6181 struct sysctl_oid *queue_node, *fl_node, *node; 6182 struct sysctl_oid_list *queue_list, *fl_list; 6183 ctx_list = device_get_sysctl_ctx(dev); 6184 6185 node = ctx->ifc_sysctl_node; 6186 child = SYSCTL_CHILDREN(node); 6187 6188 if (scctx->isc_ntxqsets > 100) 6189 qfmt = "txq%03d"; 6190 else if (scctx->isc_ntxqsets > 10) 6191 qfmt = "txq%02d"; 6192 else 6193 qfmt = "txq%d"; 6194 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6195 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6196 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6197 CTLFLAG_RD, NULL, "Queue Name"); 6198 queue_list = SYSCTL_CHILDREN(queue_node); 6199 #if MEMORY_LOGGING 6200 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6201 CTLFLAG_RD, 6202 &txq->ift_dequeued, "total mbufs freed"); 6203 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6204 CTLFLAG_RD, 6205 &txq->ift_enqueued, "total mbufs enqueued"); 6206 #endif 6207 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6208 CTLFLAG_RD, 6209 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6210 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6211 CTLFLAG_RD, 6212 &txq->ift_pullups, "# of times m_pullup was called"); 6213 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6214 CTLFLAG_RD, 6215 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6216 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6217 CTLFLAG_RD, 6218 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6219 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6220 CTLFLAG_RD, 6221 &txq->ift_map_failed, "# of times dma map failed"); 6222 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6223 CTLFLAG_RD, 6224 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6225 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6226 CTLFLAG_RD, 6227 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6228 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6229 CTLFLAG_RD, 6230 &txq->ift_pidx, 1, "Producer Index"); 6231 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6232 CTLFLAG_RD, 6233 &txq->ift_cidx, 1, "Consumer Index"); 6234 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6235 CTLFLAG_RD, 6236 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6237 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6238 CTLFLAG_RD, 6239 &txq->ift_in_use, 1, "descriptors in use"); 6240 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6241 CTLFLAG_RD, 6242 &txq->ift_processed, "descriptors procesed for clean"); 6243 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6244 CTLFLAG_RD, 6245 &txq->ift_cleaned, "total cleaned"); 6246 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6247 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6248 0, mp_ring_state_handler, "A", "soft ring state"); 6249 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6250 CTLFLAG_RD, &txq->ift_br->enqueues, 6251 "# of enqueues to the mp_ring for this queue"); 6252 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6253 CTLFLAG_RD, &txq->ift_br->drops, 6254 "# of drops in the mp_ring for this queue"); 6255 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6256 CTLFLAG_RD, &txq->ift_br->starts, 6257 "# of normal consumer starts in the mp_ring for this queue"); 6258 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6259 CTLFLAG_RD, &txq->ift_br->stalls, 6260 "# of consumer stalls in the mp_ring for this queue"); 6261 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6262 CTLFLAG_RD, &txq->ift_br->restarts, 6263 "# of consumer restarts in the mp_ring for this queue"); 6264 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6265 CTLFLAG_RD, &txq->ift_br->abdications, 6266 "# of consumer abdications in the mp_ring for this queue"); 6267 } 6268 6269 if (scctx->isc_nrxqsets > 100) 6270 qfmt = "rxq%03d"; 6271 else if (scctx->isc_nrxqsets > 10) 6272 qfmt = "rxq%02d"; 6273 else 6274 qfmt = "rxq%d"; 6275 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6276 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6277 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6278 CTLFLAG_RD, NULL, "Queue Name"); 6279 queue_list = SYSCTL_CHILDREN(queue_node); 6280 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6281 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 6282 CTLFLAG_RD, 6283 &rxq->ifr_cq_pidx, 1, "Producer Index"); 6284 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6285 CTLFLAG_RD, 6286 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6287 } 6288 6289 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6290 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6291 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6292 CTLFLAG_RD, NULL, "freelist Name"); 6293 fl_list = SYSCTL_CHILDREN(fl_node); 6294 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6295 CTLFLAG_RD, 6296 &fl->ifl_pidx, 1, "Producer Index"); 6297 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6298 CTLFLAG_RD, 6299 &fl->ifl_cidx, 1, "Consumer Index"); 6300 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6301 CTLFLAG_RD, 6302 &fl->ifl_credits, 1, "credits available"); 6303 #if MEMORY_LOGGING 6304 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6305 CTLFLAG_RD, 6306 &fl->ifl_m_enqueued, "mbufs allocated"); 6307 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6308 CTLFLAG_RD, 6309 &fl->ifl_m_dequeued, "mbufs freed"); 6310 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6311 CTLFLAG_RD, 6312 &fl->ifl_cl_enqueued, "clusters allocated"); 6313 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6314 CTLFLAG_RD, 6315 &fl->ifl_cl_dequeued, "clusters freed"); 6316 #endif 6317 6318 } 6319 } 6320 6321 } 6322 6323 #ifndef __NO_STRICT_ALIGNMENT 6324 static struct mbuf * 6325 iflib_fixup_rx(struct mbuf *m) 6326 { 6327 struct mbuf *n; 6328 6329 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6330 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6331 m->m_data += ETHER_HDR_LEN; 6332 n = m; 6333 } else { 6334 MGETHDR(n, M_NOWAIT, MT_DATA); 6335 if (n == NULL) { 6336 m_freem(m); 6337 return (NULL); 6338 } 6339 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6340 m->m_data += ETHER_HDR_LEN; 6341 m->m_len -= ETHER_HDR_LEN; 6342 n->m_len = ETHER_HDR_LEN; 6343 M_MOVE_PKTHDR(n, m); 6344 n->m_next = m; 6345 } 6346 return (n); 6347 } 6348 #endif 6349 6350 #ifdef NETDUMP 6351 static void 6352 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 6353 { 6354 if_ctx_t ctx; 6355 6356 ctx = if_getsoftc(ifp); 6357 CTX_LOCK(ctx); 6358 *nrxr = NRXQSETS(ctx); 6359 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6360 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6361 CTX_UNLOCK(ctx); 6362 } 6363 6364 static void 6365 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event) 6366 { 6367 if_ctx_t ctx; 6368 if_softc_ctx_t scctx; 6369 iflib_fl_t fl; 6370 iflib_rxq_t rxq; 6371 int i, j; 6372 6373 ctx = if_getsoftc(ifp); 6374 scctx = &ctx->ifc_softc_ctx; 6375 6376 switch (event) { 6377 case NETDUMP_START: 6378 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6379 rxq = &ctx->ifc_rxqs[i]; 6380 for (j = 0; j < rxq->ifr_nfl; j++) { 6381 fl = rxq->ifr_fl; 6382 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6383 } 6384 } 6385 iflib_no_tx_batch = 1; 6386 break; 6387 default: 6388 break; 6389 } 6390 } 6391 6392 static int 6393 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m) 6394 { 6395 if_ctx_t ctx; 6396 iflib_txq_t txq; 6397 int error; 6398 6399 ctx = if_getsoftc(ifp); 6400 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6401 IFF_DRV_RUNNING) 6402 return (EBUSY); 6403 6404 txq = &ctx->ifc_txqs[0]; 6405 error = iflib_encap(txq, &m); 6406 if (error == 0) 6407 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6408 return (error); 6409 } 6410 6411 static int 6412 iflib_netdump_poll(struct ifnet *ifp, int count) 6413 { 6414 if_ctx_t ctx; 6415 if_softc_ctx_t scctx; 6416 iflib_txq_t txq; 6417 int i; 6418 6419 ctx = if_getsoftc(ifp); 6420 scctx = &ctx->ifc_softc_ctx; 6421 6422 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6423 IFF_DRV_RUNNING) 6424 return (EBUSY); 6425 6426 txq = &ctx->ifc_txqs[0]; 6427 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6428 6429 for (i = 0; i < scctx->isc_nrxqsets; i++) 6430 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6431 return (0); 6432 } 6433 #endif /* NETDUMP */ 6434