1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include "opt_inet.h" 30 #include "opt_inet6.h" 31 #include "opt_acpi.h" 32 33 #include <sys/param.h> 34 #include <sys/types.h> 35 #include <sys/bus.h> 36 #include <sys/eventhandler.h> 37 #include <sys/fail.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/module.h> 42 #include <sys/kobj.h> 43 #include <sys/proc.h> 44 #include <sys/rman.h> 45 #include <sys/sbuf.h> 46 #include <sys/sched.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_private.h> 58 #include <net/if_types.h> 59 #include <net/if_media.h> 60 #include <net/bpf.h> 61 #include <net/ethernet.h> 62 #include <net/mp_ring.h> 63 #include <net/debugnet.h> 64 #include <net/pfil.h> 65 #include <net/vnet.h> 66 67 #include <netinet/in.h> 68 #include <netinet/in_pcb.h> 69 #include <netinet/tcp_lro.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/if_ether.h> 72 #include <netinet/ip.h> 73 #include <netinet/ip6.h> 74 #include <netinet/tcp.h> 75 #include <netinet/udp.h> 76 #include <netinet/ip_var.h> 77 #include <netinet6/ip6_var.h> 78 79 #include <machine/bus.h> 80 #include <machine/in_cksum.h> 81 82 #include <vm/vm.h> 83 #include <vm/pmap.h> 84 85 #include <dev/led/led.h> 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pci_private.h> 89 90 #include <net/iflib.h> 91 92 #include "ifdi_if.h" 93 94 #ifdef PCI_IOV 95 #include <dev/pci/pci_iov.h> 96 #endif 97 98 #include <sys/bitstring.h> 99 /* 100 * enable accounting of every mbuf as it comes in to and goes out of 101 * iflib's software descriptor references 102 */ 103 #define MEMORY_LOGGING 0 104 /* 105 * Enable mbuf vectors for compressing long mbuf chains 106 */ 107 108 /* 109 * NB: 110 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 111 * we prefetch needs to be determined by the time spent in m_free vis a vis 112 * the cost of a prefetch. This will of course vary based on the workload: 113 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 114 * is quite expensive, thus suggesting very little prefetch. 115 * - small packet forwarding which is just returning a single mbuf to 116 * UMA will typically be very fast vis a vis the cost of a memory 117 * access. 118 */ 119 120 /* 121 * File organization: 122 * - private structures 123 * - iflib private utility functions 124 * - ifnet functions 125 * - vlan registry and other exported functions 126 * - iflib public core functions 127 * 128 * 129 */ 130 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 131 132 #define IFLIB_RXEOF_MORE (1U << 0) 133 #define IFLIB_RXEOF_EMPTY (2U << 0) 134 135 struct iflib_txq; 136 typedef struct iflib_txq *iflib_txq_t; 137 struct iflib_rxq; 138 typedef struct iflib_rxq *iflib_rxq_t; 139 struct iflib_fl; 140 typedef struct iflib_fl *iflib_fl_t; 141 142 struct iflib_ctx; 143 144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 145 static void iflib_timer(void *arg); 146 static void iflib_tqg_detach(if_ctx_t ctx); 147 #ifndef ALTQ 148 static int iflib_simple_transmit(if_t ifp, struct mbuf *m); 149 #endif 150 151 typedef struct iflib_filter_info { 152 driver_filter_t *ifi_filter; 153 void *ifi_filter_arg; 154 struct grouptask *ifi_task; 155 void *ifi_ctx; 156 } *iflib_filter_info_t; 157 158 struct iflib_ctx { 159 KOBJ_FIELDS; 160 /* 161 * Pointer to hardware driver's softc 162 */ 163 void *ifc_softc; 164 device_t ifc_dev; 165 if_t ifc_ifp; 166 167 cpuset_t ifc_cpus; 168 if_shared_ctx_t ifc_sctx; 169 struct if_softc_ctx ifc_softc_ctx; 170 171 struct sx ifc_ctx_sx; 172 struct mtx ifc_state_mtx; 173 174 iflib_txq_t ifc_txqs; 175 iflib_rxq_t ifc_rxqs; 176 uint32_t ifc_if_flags; 177 uint32_t ifc_flags; 178 uint32_t ifc_max_fl_buf_size; 179 uint32_t ifc_rx_mbuf_sz; 180 181 int ifc_link_state; 182 uint32_t ifc_tx_watchdog_events; 183 struct cdev *ifc_led_dev; 184 int ifc_led_state; 185 struct resource *ifc_msix_mem; 186 187 struct if_irq ifc_legacy_irq; 188 struct task ifc_admin_task; 189 struct task ifc_led_task; 190 struct task ifc_vflr_task; 191 struct taskqueue *ifc_tq; 192 struct iflib_filter_info ifc_filter_info; 193 struct ifmedia ifc_media; 194 struct ifmedia *ifc_mediap; 195 196 struct sysctl_ctx_list ifc_sysctl_ctx; 197 struct sysctl_oid *ifc_sysctl_node; 198 uint16_t ifc_sysctl_ntxqs; 199 uint16_t ifc_sysctl_nrxqs; 200 uint16_t ifc_sysctl_qs_eq_override; 201 uint16_t ifc_sysctl_rx_budget; 202 uint16_t ifc_sysctl_tx_abdicate; 203 uint16_t ifc_sysctl_core_offset; 204 #define CORE_OFFSET_UNSPECIFIED 0xffff 205 uint8_t ifc_sysctl_separate_txrx; 206 uint8_t ifc_sysctl_use_logical_cores; 207 uint16_t ifc_sysctl_extra_msix_vectors; 208 bool ifc_cpus_are_physical_cores; 209 bool ifc_core_offset_ref; 210 bool ifc_sysctl_simple_tx; 211 bool ifc_sysctl_tx_defer_mfree; 212 uint16_t ifc_sysctl_tx_reclaim_thresh; 213 uint16_t ifc_sysctl_tx_reclaim_ticks; 214 215 qidx_t ifc_sysctl_ntxds[8]; 216 qidx_t ifc_sysctl_nrxds[8]; 217 struct if_txrx ifc_txrx; 218 #define isc_txd_encap ifc_txrx.ift_txd_encap 219 #define isc_txd_flush ifc_txrx.ift_txd_flush 220 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 221 #define isc_rxd_available ifc_txrx.ift_rxd_available 222 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 223 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 224 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 225 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 226 #define isc_txq_select ifc_txrx.ift_txq_select 227 #define isc_txq_select_v2 ifc_txrx.ift_txq_select_v2 228 229 eventhandler_tag ifc_vlan_attach_event; 230 eventhandler_tag ifc_vlan_detach_event; 231 struct ether_addr ifc_mac; 232 }; 233 234 void * 235 iflib_get_softc(if_ctx_t ctx) 236 { 237 238 return (ctx->ifc_softc); 239 } 240 241 device_t 242 iflib_get_dev(if_ctx_t ctx) 243 { 244 245 return (ctx->ifc_dev); 246 } 247 248 if_t 249 iflib_get_ifp(if_ctx_t ctx) 250 { 251 252 return (ctx->ifc_ifp); 253 } 254 255 struct ifmedia * 256 iflib_get_media(if_ctx_t ctx) 257 { 258 259 return (ctx->ifc_mediap); 260 } 261 262 void 263 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 264 { 265 266 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 267 } 268 269 if_softc_ctx_t 270 iflib_get_softc_ctx(if_ctx_t ctx) 271 { 272 273 return (&ctx->ifc_softc_ctx); 274 } 275 276 if_shared_ctx_t 277 iflib_get_sctx(if_ctx_t ctx) 278 { 279 280 return (ctx->ifc_sctx); 281 } 282 283 uint16_t 284 iflib_get_extra_msix_vectors_sysctl(if_ctx_t ctx) 285 { 286 287 return (ctx->ifc_sysctl_extra_msix_vectors); 288 } 289 290 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 291 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE / sizeof(void *)) 292 #define CACHE_PTR_NEXT(ptr) ((void *)(roundup2(ptr, CACHE_LINE_SIZE))) 293 294 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 295 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 296 297 typedef struct iflib_sw_rx_desc_array { 298 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 299 struct mbuf **ifsd_m; /* pkthdr mbufs */ 300 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 301 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 302 } iflib_rxsd_array_t; 303 304 typedef struct iflib_sw_tx_desc_array { 305 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 306 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 307 struct mbuf **ifsd_m; /* pkthdr mbufs */ 308 struct mbuf **ifsd_m_defer; /* deferred mbuf ptr */ 309 struct mbuf **ifsd_m_deferb;/* deferred mbuf backing ptr */ 310 } if_txsd_vec_t; 311 312 /* magic number that should be high enough for any hardware */ 313 #define IFLIB_MAX_TX_SEGS 128 314 #define IFLIB_RX_COPY_THRESH 128 315 #define IFLIB_MAX_RX_REFRESH 32 316 /* The minimum descriptors per second before we start coalescing */ 317 #define IFLIB_MIN_DESC_SEC 16384 318 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 319 /* maximum number of txqs that can share an rx interrupt */ 320 #define IFLIB_MAX_TX_SHARED_INTR 4 321 322 /* this should really scale with ring size - this is a fairly arbitrary value */ 323 #define TX_BATCH_SIZE 32 324 325 #define IFLIB_RESTART_BUDGET 8 326 327 328 /* 329 * Encode TSO or !TSO in the low bits of the tx ifsd_m pointer so as 330 * to avoid defref'ing the mbuf to determine the correct busdma resources 331 * to release 332 */ 333 #define IFLIB_TSO (1ULL << 0) 334 #define IFLIB_NO_TSO (2ULL << 0) 335 #define IFLIB_FLAGS_MASK (0x3ULL) 336 #define IFLIB_SAVE_MBUF(mbuf, flags) ((void *)(((uintptr_t)mbuf) | flags)) 337 #define IFLIB_GET_FLAGS(a) ((uintptr_t)a & IFLIB_FLAGS_MASK) 338 #define IFLIB_GET_MBUF(a) ((struct mbuf *)((uintptr_t)a & ~IFLIB_FLAGS_MASK)) 339 340 341 #define IFC_LEGACY 0x001 342 #define IFC_QFLUSH 0x002 343 #define IFC_MULTISEG 0x004 344 #define IFC_INIT_FAILED 0x008 345 #define IFC_SC_ALLOCATED 0x010 346 #define IFC_INIT_DONE 0x020 347 #define IFC_PREFETCH 0x040 348 #define IFC_DO_RESET 0x080 349 #define IFC_DO_WATCHDOG 0x100 350 #define IFC_DO_RESET_IF_UP 0x200 351 #define IFC_SPARE2 0x400 352 #define IFC_IN_DETACH 0x800 353 354 #define IFC_NETMAP_TX_IRQ 0x80000000 355 356 #define CSUM_OFFLOAD (CSUM_IP_TSO | CSUM_IP6_TSO | CSUM_IP | \ 357 CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_SCTP | \ 358 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_SCTP) 359 360 struct iflib_txq { 361 qidx_t ift_in_use; 362 qidx_t ift_cidx; 363 qidx_t ift_cidx_processed; 364 qidx_t ift_pidx; 365 uint8_t ift_gen; 366 uint8_t ift_br_offset:1, 367 ift_defer_mfree:1, 368 ift_spare_bits0:6; 369 uint16_t ift_npending; 370 uint16_t ift_db_pending; 371 uint16_t ift_rs_pending; 372 uint32_t ift_last_reclaim; 373 uint16_t ift_reclaim_thresh; 374 uint16_t ift_reclaim_ticks; 375 uint8_t ift_txd_size[8]; 376 uint64_t ift_processed; 377 uint64_t ift_cleaned; 378 uint64_t ift_processed_prev; 379 #if MEMORY_LOGGING 380 uint64_t ift_enqueued; 381 uint64_t ift_dequeued; 382 #endif 383 uint64_t ift_no_tx_dma_setup; 384 uint64_t ift_no_desc_avail; 385 uint64_t ift_mbuf_defrag_failed; 386 uint64_t ift_mbuf_defrag; 387 uint64_t ift_map_failed; 388 uint64_t ift_txd_encap_efbig; 389 uint64_t ift_pullups; 390 uint64_t ift_last_timer_tick; 391 392 struct mtx ift_mtx; 393 struct mtx ift_db_mtx; 394 395 /* constant values */ 396 if_ctx_t ift_ctx; 397 struct ifmp_ring *ift_br; 398 struct grouptask ift_task; 399 qidx_t ift_size; 400 qidx_t ift_pad; 401 uint16_t ift_id; 402 struct callout ift_timer; 403 #ifdef DEV_NETMAP 404 struct callout ift_netmap_timer; 405 #endif /* DEV_NETMAP */ 406 407 if_txsd_vec_t ift_sds; 408 /* 409 * TX watchdog state, updated once per iflib_timer period. The 410 * period count saturates instead of wrapping, and is 16 bits 411 * wide so that it still reaches any value 412 * net.iflib.tx_watchdog_periods is plausibly set to; an 8-bit 413 * counter would silently disable the check for a threshold 414 * above 255. 415 */ 416 qidx_t ift_outstanding_prev; 417 uint16_t ift_wdog_armed; 418 uint8_t ift_closed; 419 uint8_t ift_update_freq; 420 uint8_t ift_spare0[2]; /* pad to the next pointer boundary */ 421 struct iflib_filter_info ift_filter_info; 422 bus_dma_tag_t ift_buf_tag; 423 bus_dma_tag_t ift_tso_buf_tag; 424 iflib_dma_info_t ift_ifdi; 425 #define MTX_NAME_LEN 32 426 char ift_mtx_name[MTX_NAME_LEN]; 427 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 428 #ifdef IFLIB_DIAGNOSTICS 429 uint64_t ift_cpu_exec_count[256]; 430 #endif 431 } __aligned(CACHE_LINE_SIZE); 432 433 struct iflib_fl { 434 qidx_t ifl_cidx; 435 qidx_t ifl_pidx; 436 qidx_t ifl_credits; 437 uint8_t ifl_gen; 438 uint8_t ifl_rxd_size; 439 #if MEMORY_LOGGING 440 uint64_t ifl_m_enqueued; 441 uint64_t ifl_m_dequeued; 442 uint64_t ifl_cl_enqueued; 443 uint64_t ifl_cl_dequeued; 444 #endif 445 /* implicit pad */ 446 bitstr_t *ifl_rx_bitmap; 447 qidx_t ifl_fragidx; 448 /* constant */ 449 qidx_t ifl_size; 450 uint16_t ifl_buf_size; 451 uint16_t ifl_cltype; 452 uma_zone_t ifl_zone; 453 iflib_rxsd_array_t ifl_sds; 454 iflib_rxq_t ifl_rxq; 455 uint8_t ifl_id; 456 bus_dma_tag_t ifl_buf_tag; 457 iflib_dma_info_t ifl_ifdi; 458 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 459 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 460 } __aligned(CACHE_LINE_SIZE); 461 462 static inline qidx_t 463 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 464 { 465 qidx_t used; 466 467 if (pidx > cidx) 468 used = pidx - cidx; 469 else if (pidx < cidx) 470 used = size - cidx + pidx; 471 else if (gen == 0 && pidx == cidx) 472 used = 0; 473 else if (gen == 1 && pidx == cidx) 474 used = size; 475 else 476 panic("bad state"); 477 478 return (used); 479 } 480 481 #define TXQ_AVAIL(txq) ((txq->ift_size - txq->ift_pad) -\ 482 get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 483 484 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 485 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 486 487 #define IDXDIFF(head, tail, wrap) \ 488 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 489 490 struct iflib_rxq { 491 if_ctx_t ifr_ctx; 492 iflib_fl_t ifr_fl; 493 struct pfil_head *pfil; 494 /* 495 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 496 * the completion queue consumer index. Otherwise it's unused. 497 */ 498 qidx_t ifr_cq_cidx; 499 uint16_t ifr_id; 500 uint8_t ifr_nfl; 501 uint8_t ifr_ntxqirq; 502 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 503 uint8_t ifr_fl_offset; 504 struct lro_ctrl ifr_lc; 505 struct grouptask ifr_task; 506 struct callout ifr_watchdog; 507 struct iflib_filter_info ifr_filter_info; 508 iflib_dma_info_t ifr_ifdi; 509 510 /* dynamically allocate if any drivers need a value substantially larger than this */ 511 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 512 #ifdef IFLIB_DIAGNOSTICS 513 uint64_t ifr_cpu_exec_count[256]; 514 #endif 515 } __aligned(CACHE_LINE_SIZE); 516 517 typedef struct if_rxsd { 518 caddr_t *ifsd_cl; 519 iflib_fl_t ifsd_fl; 520 } *if_rxsd_t; 521 522 /* 523 * Only allow a single packet to take up most 1/nth of the tx ring 524 */ 525 #define MAX_SINGLE_PACKET_FRACTION 12 526 #define IF_BAD_DMA ((bus_addr_t)-1) 527 528 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 529 530 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 531 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 532 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 533 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 534 535 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 536 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 537 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 538 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 539 540 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 541 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 542 543 /* Our boot-time initialization hook */ 544 static int iflib_module_event_handler(module_t, int, void *); 545 546 static moduledata_t iflib_moduledata = { 547 "iflib", 548 iflib_module_event_handler, 549 NULL 550 }; 551 552 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 553 MODULE_VERSION(iflib, 1); 554 555 MODULE_DEPEND(iflib, pci, 1, 1, 1); 556 MODULE_DEPEND(iflib, ether, 1, 1, 1); 557 558 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 559 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 560 561 #ifndef IFLIB_DEBUG_COUNTERS 562 #ifdef INVARIANTS 563 #define IFLIB_DEBUG_COUNTERS 1 564 #else 565 #define IFLIB_DEBUG_COUNTERS 0 566 #endif /* !INVARIANTS */ 567 #endif 568 569 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 570 "iflib driver parameters"); 571 572 static SYSCTL_NODE(_debug_fail_point, OID_AUTO, iflib, 573 CTLFLAG_RW | CTLFLAG_MPSAFE, 0, "iflib fail points"); 574 575 static char iflib_register_fail_device[32]; 576 SYSCTL_STRING(_debug_fail_point_iflib, OID_AUTO, register_device, 577 CTLFLAG_RW | CTLFLAG_MPSAFE, 578 iflib_register_fail_device, sizeof(iflib_register_fail_device), 579 "device name eligible for registration fail points"); 580 581 static char iflib_admin_task_fail_device[32]; 582 SYSCTL_STRING(_debug_fail_point_iflib, OID_AUTO, admin_task_device, 583 CTLFLAG_RW | CTLFLAG_MPSAFE, 584 iflib_admin_task_fail_device, sizeof(iflib_admin_task_fail_device), 585 "device name eligible for admin task fail points"); 586 587 /* 588 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 589 */ 590 static int iflib_min_tx_latency = 0; 591 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 592 &iflib_min_tx_latency, 0, 593 "minimize transmit latency at the possible expense of throughput"); 594 static int iflib_no_tx_batch = 0; 595 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 596 &iflib_no_tx_batch, 0, 597 "minimize transmit latency at the possible expense of throughput"); 598 static int iflib_timer_default = 1000; 599 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW, 600 &iflib_timer_default, 0, "number of ticks between iflib_timer calls"); 601 /* 602 * Consecutive timer periods a TX queue must stay frozen while demand 603 * persists - see iflib_timer(), which defines those states - before the 604 * hardware is asked whether it has completions pending. Four periods is 605 * roughly two seconds with the default timer interval: a healthy queue on 606 * hardware that coalesces completion reports (e.g. 8254x, TXDCTL.WTHRESH) 607 * stays frozen for at most two (measured on 82541PI), a wedged one until it 608 * is reset. 609 */ 610 static int iflib_tx_watchdog_periods = 4; 611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_watchdog_periods, CTLFLAG_RWTUN, 612 &iflib_tx_watchdog_periods, 0, 613 "consecutive frozen timer periods under demand before a TX queue is " 614 "checked for a hang (0 disables the check)"); 615 616 617 #if IFLIB_DEBUG_COUNTERS 618 619 static int iflib_tx_seen; 620 static int iflib_tx_sent; 621 static int iflib_tx_encap; 622 static int iflib_rx_allocs; 623 static int iflib_fl_refills; 624 static int iflib_fl_refills_large; 625 static int iflib_tx_frees; 626 627 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, &iflib_tx_seen, 0, 628 "# TX mbufs seen"); 629 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, &iflib_tx_sent, 0, 630 "# TX mbufs sent"); 631 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, &iflib_tx_encap, 0, 632 "# TX mbufs encapped"); 633 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, &iflib_tx_frees, 0, 634 "# TX frees"); 635 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, &iflib_rx_allocs, 0, 636 "# RX allocations"); 637 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, &iflib_fl_refills, 0, 638 "# refills"); 639 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 640 &iflib_fl_refills_large, 0, "# large refills"); 641 642 static int iflib_txq_drain_flushing; 643 static int iflib_txq_drain_oactive; 644 static int iflib_txq_drain_notready; 645 646 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 647 &iflib_txq_drain_flushing, 0, "# drain flushes"); 648 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 649 &iflib_txq_drain_oactive, 0, "# drain oactives"); 650 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 651 &iflib_txq_drain_notready, 0, "# drain notready"); 652 653 static int iflib_encap_load_mbuf_fail; 654 static int iflib_encap_pad_mbuf_fail; 655 static int iflib_encap_txq_avail_fail; 656 static int iflib_encap_txd_encap_fail; 657 658 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 659 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 661 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 663 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 665 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 666 667 static int iflib_task_fn_rxs; 668 static int iflib_rx_intr_enables; 669 static int iflib_fast_intrs; 670 static int iflib_rx_unavail; 671 static int iflib_rx_ctx_inactive; 672 static int iflib_rx_if_input; 673 static int iflib_rxd_flush; 674 675 static int iflib_verbose_debug; 676 677 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, &iflib_task_fn_rxs, 0, 678 "# task_fn_rx calls"); 679 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 680 &iflib_rx_intr_enables, 0, "# RX intr enables"); 681 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, &iflib_fast_intrs, 0, 682 "# fast_intr calls"); 683 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, &iflib_rx_unavail, 0, 684 "# times rxeof called with no available data"); 685 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 686 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 687 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, &iflib_rx_if_input, 688 0, "# times rxeof called if_input"); 689 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, &iflib_rxd_flush, 0, 690 "# times rxd_flush called"); 691 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 692 &iflib_verbose_debug, 0, "enable verbose debugging"); 693 694 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 695 static void 696 iflib_debug_reset(void) 697 { 698 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 699 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 700 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 701 iflib_txq_drain_notready = 702 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 703 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 704 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 705 iflib_rx_unavail = 706 iflib_rx_ctx_inactive = iflib_rx_if_input = 707 iflib_rxd_flush = 0; 708 } 709 710 #else 711 #define DBG_COUNTER_INC(name) 712 static void iflib_debug_reset(void) {} 713 #endif 714 715 #define IFLIB_DEBUG 0 716 717 static void iflib_tx_structures_free(if_ctx_t ctx); 718 static void iflib_rx_structures_free(if_ctx_t ctx); 719 static int iflib_queues_alloc(if_ctx_t ctx); 720 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 721 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 722 static int iflib_qset_structures_setup(if_ctx_t ctx); 723 static int iflib_msix_init(if_ctx_t ctx); 724 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 725 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 726 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 727 #ifdef ALTQ 728 static void iflib_altq_if_start(if_t ifp); 729 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 730 #endif 731 static void iflib_register(if_ctx_t); 732 static void iflib_deregister(if_ctx_t); 733 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 734 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 735 static void iflib_init_locked(if_ctx_t ctx); 736 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 737 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 738 static void iflib_ifmp_purge(iflib_txq_t txq); 739 static void _iflib_pre_assert(if_softc_ctx_t scctx); 740 static void iflib_stop(if_ctx_t ctx); 741 static void iflib_if_init_locked(if_ctx_t ctx); 742 static void iflib_free_intr_mem(if_ctx_t ctx); 743 #ifndef __NO_STRICT_ALIGNMENT 744 static struct mbuf *iflib_fixup_rx(struct mbuf *m); 745 #endif 746 static __inline int iflib_completed_tx_reclaim(iflib_txq_t txq, 747 struct mbuf **m_defer); 748 static __inline void iflib_completed_tx_reclaim_force(iflib_txq_t txq); 749 750 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 751 SLIST_HEAD_INITIALIZER(cpu_offsets); 752 struct cpu_offset { 753 SLIST_ENTRY(cpu_offset) entries; 754 cpuset_t set; 755 unsigned int refcount; 756 uint16_t next_cpuid; 757 }; 758 static struct mtx cpu_offset_mtx; 759 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 760 MTX_DEF); 761 762 DEBUGNET_DEFINE(iflib); 763 764 static int 765 iflib_num_rx_descs(if_ctx_t ctx) 766 { 767 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 768 if_shared_ctx_t sctx = ctx->ifc_sctx; 769 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 770 771 return (scctx->isc_nrxd[first_rxq]); 772 } 773 774 static int 775 iflib_num_tx_descs(if_ctx_t ctx) 776 { 777 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 778 if_shared_ctx_t sctx = ctx->ifc_sctx; 779 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 780 781 return (scctx->isc_ntxd[first_txq]); 782 } 783 784 #ifdef DEV_NETMAP 785 #include <sys/selinfo.h> 786 #include <net/netmap.h> 787 #include <dev/netmap/netmap_kern.h> 788 789 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 790 791 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 792 static void iflib_netmap_timer(void *arg); 793 794 /* 795 * device-specific sysctl variables: 796 * 797 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 798 * During regular operations the CRC is stripped, but on some 799 * hardware reception of frames not multiple of 64 is slower, 800 * so using crcstrip=0 helps in benchmarks. 801 * 802 * iflib_rx_miss, iflib_rx_miss_bufs: 803 * count packets that might be missed due to lost interrupts. 804 */ 805 SYSCTL_DECL(_dev_netmap); 806 /* 807 * The xl driver by default strips CRCs and we do not override it. 808 */ 809 810 int iflib_crcstrip = 1; 811 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 812 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 813 814 int iflib_rx_miss, iflib_rx_miss_bufs; 815 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 816 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 817 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 818 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 819 820 /* 821 * Register/unregister. We are already under netmap lock. 822 * Only called on the first register or the last unregister. 823 */ 824 static int 825 iflib_netmap_register(struct netmap_adapter *na, int onoff) 826 { 827 if_t ifp = na->ifp; 828 if_ctx_t ctx = if_getsoftc(ifp); 829 int status; 830 831 CTX_LOCK(ctx); 832 if (!CTX_IS_VF(ctx)) 833 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 834 835 iflib_stop(ctx); 836 837 /* 838 * Enable (or disable) netmap flags, and intercept (or restore) 839 * ifp->if_transmit. This is done once the device has been stopped 840 * to prevent race conditions. Also, this must be done after 841 * calling netmap_disable_all_rings() and before calling 842 * netmap_enable_all_rings(), so that these two functions see the 843 * updated state of the NAF_NETMAP_ON bit. 844 */ 845 if (onoff) { 846 nm_set_native_flags(na); 847 } else { 848 nm_clear_native_flags(na); 849 } 850 851 iflib_init_locked(ctx); 852 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 853 status = if_getdrvflags(ifp) & IFF_DRV_RUNNING ? 0 : 1; 854 if (status) 855 nm_clear_native_flags(na); 856 CTX_UNLOCK(ctx); 857 return (status); 858 } 859 860 static int 861 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info) 862 { 863 if_t ifp = na->ifp; 864 if_ctx_t ctx = if_getsoftc(ifp); 865 iflib_rxq_t rxq = &ctx->ifc_rxqs[0]; 866 iflib_fl_t fl = &rxq->ifr_fl[0]; 867 868 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 869 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 870 info->num_tx_descs = iflib_num_tx_descs(ctx); 871 info->num_rx_descs = iflib_num_rx_descs(ctx); 872 info->rx_buf_maxsize = fl->ifl_buf_size; 873 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u", 874 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs, 875 info->num_rx_descs, info->rx_buf_maxsize); 876 877 return (0); 878 } 879 880 static int 881 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 882 { 883 struct netmap_adapter *na = kring->na; 884 u_int const lim = kring->nkr_num_slots - 1; 885 struct netmap_ring *ring = kring->ring; 886 bus_dmamap_t *map; 887 struct if_rxd_update iru; 888 if_ctx_t ctx = rxq->ifr_ctx; 889 iflib_fl_t fl = &rxq->ifr_fl[0]; 890 u_int nic_i_first, nic_i; 891 u_int nm_i; 892 int i, n; 893 #if IFLIB_DEBUG_COUNTERS 894 int rf_count = 0; 895 #endif 896 897 /* 898 * This function is used both at initialization and in rxsync. 899 * At initialization we need to prepare (with isc_rxd_refill()) 900 * all the netmap buffers currently owned by the kernel, in 901 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync 902 * (except for kring->nkr_hwofs). These may be less than 903 * kring->nkr_num_slots if netmap_reset() was called while 904 * an application using the kring that still owned some 905 * buffers. 906 * At rxsync time, both indexes point to the next buffer to be 907 * refilled. 908 * In any case we publish (with isc_rxd_flush()) up to 909 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 910 * pointer to overrun the head/cons pointer, although this is 911 * not necessary for some NICs (e.g. vmx). 912 */ 913 if (__predict_false(init)) { 914 n = kring->nkr_num_slots - nm_kr_rxspace(kring); 915 } else { 916 n = kring->rhead - kring->nr_hwcur; 917 if (n == 0) 918 return (0); /* Nothing to do. */ 919 if (n < 0) 920 n += kring->nkr_num_slots; 921 } 922 923 iru_init(&iru, rxq, 0 /* flid */); 924 map = fl->ifl_sds.ifsd_map; 925 nic_i = fl->ifl_pidx; 926 nm_i = netmap_idx_n2k(kring, nic_i); 927 if (__predict_false(init)) { 928 /* 929 * On init/reset, nic_i must be 0, and we must 930 * start to refill from hwtail (see netmap_reset()). 931 */ 932 MPASS(nic_i == 0); 933 MPASS(nm_i == kring->nr_hwtail); 934 } else 935 MPASS(nm_i == kring->nr_hwcur); 936 DBG_COUNTER_INC(fl_refills); 937 while (n > 0) { 938 #if IFLIB_DEBUG_COUNTERS 939 if (++rf_count == 9) 940 DBG_COUNTER_INC(fl_refills_large); 941 #endif 942 nic_i_first = nic_i; 943 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 944 struct netmap_slot *slot = &ring->slot[nm_i]; 945 uint64_t paddr; 946 void *addr = PNMB(na, slot, &paddr); 947 948 MPASS(i < IFLIB_MAX_RX_REFRESH); 949 950 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 951 return (netmap_ring_reinit(kring)); 952 953 fl->ifl_bus_addrs[i] = paddr + 954 nm_get_offset(kring, slot); 955 fl->ifl_rxd_idxs[i] = nic_i; 956 957 if (__predict_false(init)) { 958 netmap_load_map(na, fl->ifl_buf_tag, 959 map[nic_i], addr); 960 } else if (slot->flags & NS_BUF_CHANGED) { 961 /* buffer has changed, reload map */ 962 netmap_reload_map(na, fl->ifl_buf_tag, 963 map[nic_i], addr); 964 } 965 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 966 BUS_DMASYNC_PREREAD); 967 slot->flags &= ~NS_BUF_CHANGED; 968 969 nm_i = nm_next(nm_i, lim); 970 nic_i = nm_next(nic_i, lim); 971 } 972 973 iru.iru_pidx = nic_i_first; 974 iru.iru_count = i; 975 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 976 } 977 fl->ifl_pidx = nic_i; 978 /* 979 * At the end of the loop we must have refilled everything 980 * we could possibly refill. 981 */ 982 MPASS(nm_i == kring->rhead); 983 kring->nr_hwcur = nm_i; 984 985 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 986 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 987 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 988 nm_prev(nic_i, lim)); 989 DBG_COUNTER_INC(rxd_flush); 990 991 return (0); 992 } 993 994 #define NETMAP_TX_TIMER_US 90 995 996 /* 997 * Reconcile kernel and user view of the transmit ring. 998 * 999 * All information is in the kring. 1000 * Userspace wants to send packets up to the one before kring->rhead, 1001 * kernel knows kring->nr_hwcur is the first unsent packet. 1002 * 1003 * Here we push packets out (as many as possible), and possibly 1004 * reclaim buffers from previously completed transmission. 1005 * 1006 * The caller (netmap) guarantees that there is only one instance 1007 * running at any time. Any interference with other driver 1008 * methods should be handled by the individual drivers. 1009 */ 1010 static int 1011 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 1012 { 1013 struct netmap_adapter *na = kring->na; 1014 if_t ifp = na->ifp; 1015 struct netmap_ring *ring = kring->ring; 1016 u_int nm_i; /* index into the netmap kring */ 1017 u_int nic_i; /* index into the NIC ring */ 1018 u_int const lim = kring->nkr_num_slots - 1; 1019 u_int const head = kring->rhead; 1020 struct if_pkt_info pi; 1021 int tx_pkts = 0, tx_bytes = 0; 1022 1023 /* 1024 * interrupts on every tx packet are expensive so request 1025 * them every half ring, or where NS_REPORT is set 1026 */ 1027 u_int report_frequency = kring->nkr_num_slots >> 1; 1028 /* device-specific */ 1029 if_ctx_t ctx = if_getsoftc(ifp); 1030 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 1031 1032 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1033 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1034 1035 /* 1036 * First part: process new packets to send. 1037 * nm_i is the current index in the netmap kring, 1038 * nic_i is the corresponding index in the NIC ring. 1039 * 1040 * If we have packets to send (nm_i != head) 1041 * iterate over the netmap ring, fetch length and update 1042 * the corresponding slot in the NIC ring. Some drivers also 1043 * need to update the buffer's physical address in the NIC slot 1044 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 1045 * 1046 * The netmap_reload_map() calls is especially expensive, 1047 * even when (as in this case) the tag is 0, so do only 1048 * when the buffer has actually changed. 1049 * 1050 * If possible do not set the report/intr bit on all slots, 1051 * but only a few times per ring or when NS_REPORT is set. 1052 * 1053 * Finally, on 10G and faster drivers, it might be useful 1054 * to prefetch the next slot and txr entry. 1055 */ 1056 1057 nm_i = kring->nr_hwcur; 1058 if (nm_i != head) { /* we have new packets to send */ 1059 uint32_t pkt_len = 0, seg_idx = 0; 1060 int nic_i_start = -1, flags = 0; 1061 memset(&pi, 0, sizeof(pi)); 1062 pi.ipi_segs = txq->ift_segs; 1063 pi.ipi_qsidx = kring->ring_id; 1064 nic_i = netmap_idx_k2n(kring, nm_i); 1065 1066 __builtin_prefetch(&ring->slot[nm_i]); 1067 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 1068 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 1069 1070 while (nm_i != head) { 1071 struct netmap_slot *slot = &ring->slot[nm_i]; 1072 uint64_t offset = nm_get_offset(kring, slot); 1073 u_int len = slot->len; 1074 uint64_t paddr; 1075 void *addr = PNMB(na, slot, &paddr); 1076 1077 flags |= (slot->flags & NS_REPORT || 1078 nic_i == 0 || nic_i == report_frequency) ? 1079 IPI_TX_INTR : 0; 1080 1081 /* 1082 * If this is the first packet fragment, save the 1083 * index of the first NIC slot for later. 1084 */ 1085 if (nic_i_start < 0) 1086 nic_i_start = nic_i; 1087 1088 pi.ipi_segs[seg_idx].ds_addr = paddr + offset; 1089 pi.ipi_segs[seg_idx].ds_len = len; 1090 if (len) { 1091 pkt_len += len; 1092 seg_idx++; 1093 } 1094 1095 if (!(slot->flags & NS_MOREFRAG)) { 1096 pi.ipi_len = pkt_len; 1097 pi.ipi_nsegs = seg_idx; 1098 pi.ipi_pidx = nic_i_start; 1099 pi.ipi_ndescs = 0; 1100 pi.ipi_flags = flags; 1101 1102 /* Prepare the NIC TX ring. */ 1103 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1104 DBG_COUNTER_INC(tx_encap); 1105 1106 /* Update transmit counters */ 1107 tx_bytes += pi.ipi_len; 1108 tx_pkts++; 1109 1110 /* Reinit per-packet info for the next one. */ 1111 flags = seg_idx = pkt_len = 0; 1112 nic_i_start = -1; 1113 } 1114 1115 /* prefetch for next round */ 1116 __builtin_prefetch(&ring->slot[nm_i + 1]); 1117 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1118 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1119 1120 NM_CHECK_ADDR_LEN_OFF(na, len, offset); 1121 1122 if (slot->flags & NS_BUF_CHANGED) { 1123 /* buffer has changed, reload map */ 1124 netmap_reload_map(na, txq->ift_buf_tag, 1125 txq->ift_sds.ifsd_map[nic_i], addr); 1126 } 1127 /* make sure changes to the buffer are synced */ 1128 bus_dmamap_sync(txq->ift_buf_tag, 1129 txq->ift_sds.ifsd_map[nic_i], 1130 BUS_DMASYNC_PREWRITE); 1131 1132 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG); 1133 nm_i = nm_next(nm_i, lim); 1134 nic_i = nm_next(nic_i, lim); 1135 } 1136 kring->nr_hwcur = nm_i; 1137 1138 /* synchronize the NIC ring */ 1139 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1140 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1141 1142 /* (re)start the tx unit up to slot nic_i (excluded) */ 1143 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1144 } 1145 1146 /* 1147 * Second part: reclaim buffers for completed transmissions. 1148 * 1149 * If there are unclaimed buffers, attempt to reclaim them. 1150 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1151 * trigger a per-tx-queue timer to try again later. 1152 */ 1153 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1154 if (iflib_tx_credits_update(ctx, txq)) { 1155 /* some tx completed, increment avail */ 1156 nic_i = txq->ift_cidx_processed; 1157 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1158 } 1159 } 1160 1161 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1162 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1163 callout_reset_sbt_on(&txq->ift_netmap_timer, 1164 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1165 iflib_netmap_timer, txq, 1166 txq->ift_netmap_timer.c_cpu, 0); 1167 } 1168 1169 if_inc_counter(ifp, IFCOUNTER_OBYTES, tx_bytes); 1170 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tx_pkts); 1171 1172 return (0); 1173 } 1174 1175 /* 1176 * Reconcile kernel and user view of the receive ring. 1177 * Same as for the txsync, this routine must be efficient. 1178 * The caller guarantees a single invocations, but races against 1179 * the rest of the driver should be handled here. 1180 * 1181 * On call, kring->rhead is the first packet that userspace wants 1182 * to keep, and kring->rcur is the wakeup point. 1183 * The kernel has previously reported packets up to kring->rtail. 1184 * 1185 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1186 * of whether or not we received an interrupt. 1187 */ 1188 static int 1189 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1190 { 1191 struct netmap_adapter *na = kring->na; 1192 struct netmap_ring *ring = kring->ring; 1193 if_t ifp = na->ifp; 1194 uint32_t nm_i; /* index into the netmap ring */ 1195 uint32_t nic_i; /* index into the NIC ring */ 1196 u_int n; 1197 u_int const lim = kring->nkr_num_slots - 1; 1198 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1199 int i = 0, rx_bytes = 0, rx_pkts = 0; 1200 1201 if_ctx_t ctx = if_getsoftc(ifp); 1202 if_shared_ctx_t sctx = ctx->ifc_sctx; 1203 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1204 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1205 iflib_fl_t fl = &rxq->ifr_fl[0]; 1206 struct if_rxd_info ri; 1207 qidx_t *cidxp; 1208 1209 /* 1210 * netmap only uses free list 0, to avoid out of order consumption 1211 * of receive buffers 1212 */ 1213 1214 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1215 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1216 1217 /* 1218 * First part: import newly received packets. 1219 * 1220 * nm_i is the index of the next free slot in the netmap ring, 1221 * nic_i is the index of the next received packet in the NIC ring 1222 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1223 * differ in case if_init() has been called while 1224 * in netmap mode. For the receive ring we have 1225 * 1226 * nic_i = fl->ifl_cidx; 1227 * nm_i = kring->nr_hwtail (previous) 1228 * and 1229 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1230 * 1231 * fl->ifl_cidx is set to 0 on a ring reinit 1232 */ 1233 if (netmap_no_pendintr || force_update) { 1234 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1235 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1236 int crclen = iflib_crcstrip ? 0 : 4; 1237 int error, avail; 1238 1239 /* 1240 * For the free list consumer index, we use the same 1241 * logic as in iflib_rxeof(). 1242 */ 1243 if (have_rxcq) 1244 cidxp = &rxq->ifr_cq_cidx; 1245 else 1246 cidxp = &fl->ifl_cidx; 1247 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1248 rxq->ifr_id, *cidxp, USHRT_MAX); 1249 1250 nic_i = fl->ifl_cidx; 1251 nm_i = netmap_idx_n2k(kring, nic_i); 1252 MPASS(nm_i == kring->nr_hwtail); 1253 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1254 memset(&ri, 0, sizeof(ri)); 1255 ri.iri_frags = rxq->ifr_frags; 1256 ri.iri_qsidx = kring->ring_id; 1257 ri.iri_ifp = ctx->ifc_ifp; 1258 ri.iri_cidx = *cidxp; 1259 1260 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1261 for (i = 0; i < ri.iri_nfrags; i++) { 1262 if (error) { 1263 ring->slot[nm_i].len = 0; 1264 ring->slot[nm_i].flags = 0; 1265 } else { 1266 ring->slot[nm_i].len = ri.iri_frags[i].irf_len; 1267 if (i == (ri.iri_nfrags - 1)) { 1268 ring->slot[nm_i].len -= crclen; 1269 ring->slot[nm_i].flags = 0; 1270 1271 /* Update receive counters */ 1272 rx_bytes += ri.iri_len; 1273 rx_pkts++; 1274 } else 1275 ring->slot[nm_i].flags = NS_MOREFRAG; 1276 } 1277 1278 bus_dmamap_sync(fl->ifl_buf_tag, 1279 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1280 nm_i = nm_next(nm_i, lim); 1281 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1282 } 1283 1284 if (have_rxcq) { 1285 *cidxp = ri.iri_cidx; 1286 while (*cidxp >= scctx->isc_nrxd[0]) 1287 *cidxp -= scctx->isc_nrxd[0]; 1288 } 1289 1290 } 1291 if (n) { /* update the state variables */ 1292 if (netmap_no_pendintr && !force_update) { 1293 /* diagnostics */ 1294 iflib_rx_miss++; 1295 iflib_rx_miss_bufs += n; 1296 } 1297 kring->nr_hwtail = nm_i; 1298 } 1299 kring->nr_kflags &= ~NKR_PENDINTR; 1300 } 1301 /* 1302 * Second part: skip past packets that userspace has released. 1303 * (kring->nr_hwcur to head excluded), 1304 * and make the buffers available for reception. 1305 * As usual nm_i is the index in the netmap ring, 1306 * nic_i is the index in the NIC ring, and 1307 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1308 */ 1309 netmap_fl_refill(rxq, kring, false); 1310 1311 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 1312 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 1313 1314 return (0); 1315 } 1316 1317 static void 1318 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1319 { 1320 if_ctx_t ctx = if_getsoftc(na->ifp); 1321 1322 CTX_LOCK(ctx); 1323 if (onoff) { 1324 IFDI_INTR_ENABLE(ctx); 1325 } else { 1326 IFDI_INTR_DISABLE(ctx); 1327 } 1328 CTX_UNLOCK(ctx); 1329 } 1330 1331 static int 1332 iflib_netmap_attach(if_ctx_t ctx) 1333 { 1334 struct netmap_adapter na; 1335 1336 bzero(&na, sizeof(na)); 1337 1338 na.ifp = ctx->ifc_ifp; 1339 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS; 1340 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1341 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1342 1343 na.num_tx_desc = iflib_num_tx_descs(ctx); 1344 na.num_rx_desc = iflib_num_rx_descs(ctx); 1345 na.nm_txsync = iflib_netmap_txsync; 1346 na.nm_rxsync = iflib_netmap_rxsync; 1347 na.nm_register = iflib_netmap_register; 1348 na.nm_intr = iflib_netmap_intr; 1349 na.nm_config = iflib_netmap_config; 1350 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1351 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1352 return (netmap_attach(&na)); 1353 } 1354 1355 static int 1356 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1357 { 1358 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1359 struct netmap_slot *slot; 1360 1361 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1362 if (slot == NULL) 1363 return (0); 1364 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1365 /* 1366 * In netmap mode, set the map for the packet buffer. 1367 * NOTE: Some drivers (not this one) also need to set 1368 * the physical buffer address in the NIC ring. 1369 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1370 * netmap slot index, si 1371 */ 1372 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1373 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1374 NMB(na, slot + si)); 1375 } 1376 return (1); 1377 } 1378 1379 static int 1380 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1381 { 1382 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1383 struct netmap_kring *kring; 1384 struct netmap_slot *slot; 1385 1386 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1387 if (slot == NULL) 1388 return (0); 1389 kring = na->rx_rings[rxq->ifr_id]; 1390 netmap_fl_refill(rxq, kring, true); 1391 return (1); 1392 } 1393 1394 static void 1395 iflib_netmap_timer(void *arg) 1396 { 1397 iflib_txq_t txq = arg; 1398 if_ctx_t ctx = txq->ift_ctx; 1399 1400 /* 1401 * Wake up the netmap application, to give it a chance to 1402 * call txsync and reclaim more completed TX buffers. 1403 */ 1404 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1405 } 1406 1407 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1408 1409 #else 1410 #define iflib_netmap_txq_init(ctx, txq) (0) 1411 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1412 #define iflib_netmap_detach(ifp) 1413 #define netmap_enable_all_rings(ifp) 1414 #define netmap_disable_all_rings(ifp) 1415 1416 #define iflib_netmap_attach(ctx) (0) 1417 #define netmap_rx_irq(ifp, qid, budget) (0) 1418 #endif 1419 1420 #if defined(__i386__) || defined(__amd64__) 1421 static __inline void 1422 prefetch(void *x) 1423 { 1424 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1425 } 1426 1427 static __inline void 1428 prefetch2cachelines(void *x) 1429 { 1430 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1431 #if (CACHE_LINE_SIZE < 128) 1432 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x) + CACHE_LINE_SIZE / (sizeof(unsigned long))))); 1433 #endif 1434 } 1435 #else 1436 static __inline void 1437 prefetch(void *x) 1438 { 1439 } 1440 1441 static __inline void 1442 prefetch2cachelines(void *x) 1443 { 1444 } 1445 #endif 1446 1447 static void 1448 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1449 { 1450 iflib_fl_t fl; 1451 1452 fl = &rxq->ifr_fl[flid]; 1453 iru->iru_paddrs = fl->ifl_bus_addrs; 1454 iru->iru_idxs = fl->ifl_rxd_idxs; 1455 iru->iru_qsidx = rxq->ifr_id; 1456 iru->iru_buf_size = fl->ifl_buf_size; 1457 iru->iru_flidx = fl->ifl_id; 1458 } 1459 1460 static void 1461 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1462 { 1463 if (err) 1464 return; 1465 *(bus_addr_t *) arg = segs[0].ds_addr; 1466 } 1467 1468 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \ 1469 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \ 1470 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL) 1471 1472 int 1473 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1474 { 1475 int err; 1476 device_t dev = ctx->ifc_dev; 1477 bus_addr_t lowaddr; 1478 1479 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width); 1480 1481 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1482 align, 0, /* alignment, bounds */ 1483 lowaddr, /* lowaddr */ 1484 BUS_SPACE_MAXADDR, /* highaddr */ 1485 NULL, NULL, /* filter, filterarg */ 1486 size, /* maxsize */ 1487 1, /* nsegments */ 1488 size, /* maxsegsize */ 1489 BUS_DMA_ALLOCNOW, /* flags */ 1490 NULL, /* lockfunc */ 1491 NULL, /* lockarg */ 1492 &dma->idi_tag); 1493 if (err) { 1494 device_printf(dev, 1495 "%s: bus_dma_tag_create failed: %d (size=%d, align=%d)\n", 1496 __func__, err, size, align); 1497 goto fail_0; 1498 } 1499 1500 err = bus_dmamem_alloc(dma->idi_tag, (void **)&dma->idi_vaddr, 1501 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1502 if (err) { 1503 device_printf(dev, 1504 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1505 __func__, (uintmax_t)size, err); 1506 goto fail_1; 1507 } 1508 1509 dma->idi_paddr = IF_BAD_DMA; 1510 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1511 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1512 if (err || dma->idi_paddr == IF_BAD_DMA) { 1513 device_printf(dev, 1514 "%s: bus_dmamap_load failed: %d\n", 1515 __func__, err); 1516 goto fail_2; 1517 } 1518 1519 dma->idi_size = size; 1520 return (0); 1521 1522 fail_2: 1523 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1524 fail_1: 1525 bus_dma_tag_destroy(dma->idi_tag); 1526 fail_0: 1527 dma->idi_tag = NULL; 1528 1529 return (err); 1530 } 1531 1532 int 1533 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1534 { 1535 if_shared_ctx_t sctx = ctx->ifc_sctx; 1536 1537 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1538 1539 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1540 } 1541 1542 int 1543 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1544 { 1545 int i, err; 1546 iflib_dma_info_t *dmaiter; 1547 1548 dmaiter = dmalist; 1549 for (i = 0; i < count; i++, dmaiter++) { 1550 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1551 break; 1552 } 1553 if (err) 1554 iflib_dma_free_multi(dmalist, i); 1555 return (err); 1556 } 1557 1558 void 1559 iflib_dma_free(iflib_dma_info_t dma) 1560 { 1561 if (dma->idi_tag == NULL) 1562 return; 1563 if (dma->idi_paddr != IF_BAD_DMA) { 1564 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1565 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1566 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1567 dma->idi_paddr = IF_BAD_DMA; 1568 } 1569 if (dma->idi_vaddr != NULL) { 1570 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1571 dma->idi_vaddr = NULL; 1572 } 1573 bus_dma_tag_destroy(dma->idi_tag); 1574 dma->idi_tag = NULL; 1575 } 1576 1577 void 1578 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1579 { 1580 int i; 1581 iflib_dma_info_t *dmaiter = dmalist; 1582 1583 for (i = 0; i < count; i++, dmaiter++) 1584 iflib_dma_free(*dmaiter); 1585 } 1586 1587 static int 1588 iflib_fast_intr(void *arg) 1589 { 1590 iflib_filter_info_t info = arg; 1591 struct grouptask *gtask = info->ifi_task; 1592 int result; 1593 1594 DBG_COUNTER_INC(fast_intrs); 1595 if (info->ifi_filter != NULL) { 1596 result = info->ifi_filter(info->ifi_filter_arg); 1597 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1598 return (result); 1599 } 1600 1601 GROUPTASK_ENQUEUE(gtask); 1602 return (FILTER_HANDLED); 1603 } 1604 1605 static int 1606 iflib_fast_intr_rxtx(void *arg) 1607 { 1608 iflib_filter_info_t info = arg; 1609 struct grouptask *gtask = info->ifi_task; 1610 if_ctx_t ctx; 1611 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1612 iflib_txq_t txq; 1613 void *sc; 1614 int i, cidx, result; 1615 qidx_t txqid; 1616 bool intr_enable, intr_legacy; 1617 1618 DBG_COUNTER_INC(fast_intrs); 1619 if (info->ifi_filter != NULL) { 1620 result = info->ifi_filter(info->ifi_filter_arg); 1621 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1622 return (result); 1623 } 1624 1625 ctx = rxq->ifr_ctx; 1626 sc = ctx->ifc_softc; 1627 intr_enable = false; 1628 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1629 MPASS(rxq->ifr_ntxqirq); 1630 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1631 txqid = rxq->ifr_txqid[i]; 1632 txq = &ctx->ifc_txqs[txqid]; 1633 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1634 BUS_DMASYNC_POSTREAD); 1635 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1636 if (intr_legacy) 1637 intr_enable = true; 1638 else 1639 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1640 continue; 1641 } 1642 GROUPTASK_ENQUEUE(&txq->ift_task); 1643 } 1644 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1645 cidx = rxq->ifr_cq_cidx; 1646 else 1647 cidx = rxq->ifr_fl[0].ifl_cidx; 1648 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1649 GROUPTASK_ENQUEUE(gtask); 1650 else { 1651 if (intr_legacy) 1652 intr_enable = true; 1653 else 1654 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1655 DBG_COUNTER_INC(rx_intr_enables); 1656 } 1657 if (intr_enable) 1658 IFDI_INTR_ENABLE(ctx); 1659 return (FILTER_HANDLED); 1660 } 1661 1662 static int 1663 iflib_fast_intr_ctx(void *arg) 1664 { 1665 iflib_filter_info_t info = arg; 1666 if_ctx_t ctx = info->ifi_ctx; 1667 int result; 1668 1669 DBG_COUNTER_INC(fast_intrs); 1670 if (info->ifi_filter != NULL) { 1671 result = info->ifi_filter(info->ifi_filter_arg); 1672 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1673 return (result); 1674 } 1675 1676 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_admin_task); 1677 return (FILTER_HANDLED); 1678 } 1679 1680 static int 1681 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1682 driver_filter_t filter, driver_intr_t handler, void *arg, 1683 const char *name) 1684 { 1685 struct resource *res; 1686 void *tag = NULL; 1687 device_t dev = ctx->ifc_dev; 1688 int flags, i, rc; 1689 1690 flags = RF_ACTIVE; 1691 if (ctx->ifc_flags & IFC_LEGACY) 1692 flags |= RF_SHAREABLE; 1693 MPASS(rid < 512); 1694 i = rid; 1695 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1696 if (res == NULL) { 1697 device_printf(dev, 1698 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1699 return (ENOMEM); 1700 } 1701 irq->ii_res = res; 1702 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1703 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1704 filter, handler, arg, &tag); 1705 if (rc != 0) { 1706 device_printf(dev, 1707 "failed to setup interrupt for rid %d, name %s: %d\n", 1708 rid, name ? name : "unknown", rc); 1709 return (rc); 1710 } else if (name) 1711 bus_describe_intr(dev, res, tag, "%s", name); 1712 1713 irq->ii_tag = tag; 1714 return (0); 1715 } 1716 1717 /********************************************************************* 1718 * 1719 * Allocate DMA resources for TX buffers as well as memory for the TX 1720 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1721 * iflib_sw_tx_desc_array structure, storing all the information that 1722 * is needed to transmit a packet on the wire. This is called only 1723 * once at attach, setup is done every reset. 1724 * 1725 **********************************************************************/ 1726 static int 1727 iflib_txsd_alloc(iflib_txq_t txq) 1728 { 1729 if_ctx_t ctx = txq->ift_ctx; 1730 if_shared_ctx_t sctx = ctx->ifc_sctx; 1731 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1732 device_t dev = ctx->ifc_dev; 1733 bus_size_t tsomaxsize; 1734 bus_addr_t lowaddr; 1735 int err, nsegments, ntsosegments; 1736 bool tso; 1737 1738 nsegments = scctx->isc_tx_nsegments; 1739 ntsosegments = scctx->isc_tx_tso_segments_max; 1740 tsomaxsize = scctx->isc_tx_tso_size_max; 1741 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1742 tsomaxsize += sizeof(struct ether_vlan_header); 1743 MPASS(scctx->isc_ntxd[0] > 0); 1744 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1745 MPASS(nsegments > 0); 1746 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1747 MPASS(ntsosegments > 0); 1748 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1749 } 1750 1751 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1752 1753 /* 1754 * Set up DMA tags for TX buffers. 1755 */ 1756 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1757 1, 0, /* alignment, bounds */ 1758 lowaddr, /* lowaddr */ 1759 BUS_SPACE_MAXADDR, /* highaddr */ 1760 NULL, NULL, /* filter, filterarg */ 1761 sctx->isc_tx_maxsize, /* maxsize */ 1762 nsegments, /* nsegments */ 1763 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1764 0, /* flags */ 1765 NULL, /* lockfunc */ 1766 NULL, /* lockfuncarg */ 1767 &txq->ift_buf_tag))) { 1768 device_printf(dev, "Unable to allocate TX DMA tag: %d\n", err); 1769 device_printf(dev, "maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1770 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1771 goto fail; 1772 } 1773 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1774 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1775 1, 0, /* alignment, bounds */ 1776 lowaddr, /* lowaddr */ 1777 BUS_SPACE_MAXADDR, /* highaddr */ 1778 NULL, NULL, /* filter, filterarg */ 1779 tsomaxsize, /* maxsize */ 1780 ntsosegments, /* nsegments */ 1781 sctx->isc_tso_maxsegsize, /* maxsegsize */ 1782 0, /* flags */ 1783 NULL, /* lockfunc */ 1784 NULL, /* lockfuncarg */ 1785 &txq->ift_tso_buf_tag))) { 1786 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1787 err); 1788 goto fail; 1789 } 1790 1791 /* Allocate memory for the TX mbuf map. */ 1792 if (!(txq->ift_sds.ifsd_m = 1793 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1794 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1795 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1796 err = ENOMEM; 1797 goto fail; 1798 } 1799 if (ctx->ifc_sysctl_simple_tx) { 1800 if (!(txq->ift_sds.ifsd_m_defer = 1801 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1802 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1803 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1804 err = ENOMEM; 1805 goto fail; 1806 } 1807 } 1808 txq->ift_sds.ifsd_m_deferb = txq->ift_sds.ifsd_m_defer; 1809 /* 1810 * Create the DMA maps for TX buffers. 1811 */ 1812 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1813 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1814 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1815 device_printf(dev, 1816 "Unable to allocate TX buffer DMA map memory\n"); 1817 err = ENOMEM; 1818 goto fail; 1819 } 1820 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1821 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1822 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1823 device_printf(dev, 1824 "Unable to allocate TSO TX buffer map memory\n"); 1825 err = ENOMEM; 1826 goto fail; 1827 } 1828 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1829 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1830 &txq->ift_sds.ifsd_map[i]); 1831 if (err != 0) { 1832 device_printf(dev, "Unable to create TX DMA map\n"); 1833 goto fail; 1834 } 1835 if (!tso) 1836 continue; 1837 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1838 &txq->ift_sds.ifsd_tso_map[i]); 1839 if (err != 0) { 1840 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1841 goto fail; 1842 } 1843 } 1844 return (0); 1845 fail: 1846 /* We free all, it handles case where we are in the middle */ 1847 iflib_tx_structures_free(ctx); 1848 return (err); 1849 } 1850 1851 static void 1852 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1853 { 1854 bus_dmamap_t map; 1855 1856 if (txq->ift_sds.ifsd_map != NULL) { 1857 map = txq->ift_sds.ifsd_map[i]; 1858 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1859 bus_dmamap_unload(txq->ift_buf_tag, map); 1860 bus_dmamap_destroy(txq->ift_buf_tag, map); 1861 txq->ift_sds.ifsd_map[i] = NULL; 1862 } 1863 1864 if (txq->ift_sds.ifsd_tso_map != NULL) { 1865 map = txq->ift_sds.ifsd_tso_map[i]; 1866 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1867 BUS_DMASYNC_POSTWRITE); 1868 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1869 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1870 txq->ift_sds.ifsd_tso_map[i] = NULL; 1871 } 1872 } 1873 1874 static void 1875 iflib_txq_destroy(iflib_txq_t txq) 1876 { 1877 if_ctx_t ctx = txq->ift_ctx; 1878 1879 for (int i = 0; i < txq->ift_size; i++) 1880 iflib_txsd_destroy(ctx, txq, i); 1881 1882 if (txq->ift_br != NULL) { 1883 ifmp_ring_free(txq->ift_br); 1884 txq->ift_br = NULL; 1885 } 1886 1887 mtx_destroy(&txq->ift_mtx); 1888 1889 if (txq->ift_sds.ifsd_map != NULL) { 1890 free(txq->ift_sds.ifsd_map, M_IFLIB); 1891 txq->ift_sds.ifsd_map = NULL; 1892 } 1893 if (txq->ift_sds.ifsd_tso_map != NULL) { 1894 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1895 txq->ift_sds.ifsd_tso_map = NULL; 1896 } 1897 if (txq->ift_sds.ifsd_m != NULL) { 1898 free(txq->ift_sds.ifsd_m, M_IFLIB); 1899 txq->ift_sds.ifsd_m = NULL; 1900 } 1901 if (txq->ift_sds.ifsd_m_defer != NULL) { 1902 free(txq->ift_sds.ifsd_m_defer, M_IFLIB); 1903 txq->ift_sds.ifsd_m_defer = NULL; 1904 } 1905 if (txq->ift_buf_tag != NULL) { 1906 bus_dma_tag_destroy(txq->ift_buf_tag); 1907 txq->ift_buf_tag = NULL; 1908 } 1909 if (txq->ift_tso_buf_tag != NULL) { 1910 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1911 txq->ift_tso_buf_tag = NULL; 1912 } 1913 if (txq->ift_ifdi != NULL) { 1914 free(txq->ift_ifdi, M_IFLIB); 1915 } 1916 } 1917 1918 static void 1919 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1920 { 1921 struct mbuf *m; 1922 1923 m = IFLIB_GET_MBUF(txq->ift_sds.ifsd_m[i]); 1924 if (m == NULL) 1925 return; 1926 1927 if (txq->ift_sds.ifsd_map != NULL) { 1928 bus_dmamap_sync(txq->ift_buf_tag, 1929 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1930 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1931 } 1932 if (txq->ift_sds.ifsd_tso_map != NULL) { 1933 bus_dmamap_sync(txq->ift_tso_buf_tag, 1934 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1935 bus_dmamap_unload(txq->ift_tso_buf_tag, 1936 txq->ift_sds.ifsd_tso_map[i]); 1937 } 1938 txq->ift_sds.ifsd_m[i] = NULL; 1939 m_freem(m); 1940 DBG_COUNTER_INC(tx_frees); 1941 } 1942 1943 static int 1944 iflib_txq_setup(iflib_txq_t txq) 1945 { 1946 if_ctx_t ctx = txq->ift_ctx; 1947 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1948 if_shared_ctx_t sctx = ctx->ifc_sctx; 1949 iflib_dma_info_t di; 1950 int i; 1951 1952 /* XXX make configurable */ 1953 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1954 1955 /* Reset indices */ 1956 txq->ift_cidx_processed = 0; 1957 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1958 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1959 txq->ift_pad = scctx->isc_tx_pad; 1960 1961 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1962 bzero((void *)di->idi_vaddr, di->idi_size); 1963 1964 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1965 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1966 bus_dmamap_sync(di->idi_tag, di->idi_map, 1967 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1968 return (0); 1969 } 1970 1971 /********************************************************************* 1972 * 1973 * Allocate DMA resources for RX buffers as well as memory for the RX 1974 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1975 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1976 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1977 * Since we use use one entry in iflib_sw_rx_desc_array per received 1978 * packet, the maximum number of entries we'll need is equal to the 1979 * number of hardware receive descriptors that we've allocated. 1980 * 1981 **********************************************************************/ 1982 static int 1983 iflib_rxsd_alloc(iflib_rxq_t rxq) 1984 { 1985 if_ctx_t ctx = rxq->ifr_ctx; 1986 if_shared_ctx_t sctx = ctx->ifc_sctx; 1987 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1988 device_t dev = ctx->ifc_dev; 1989 iflib_fl_t fl; 1990 bus_addr_t lowaddr; 1991 int err; 1992 1993 MPASS(scctx->isc_nrxd[0] > 0); 1994 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1995 1996 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1997 1998 fl = rxq->ifr_fl; 1999 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 2000 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 2001 /* Set up DMA tag for RX buffers. */ 2002 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 2003 1, 0, /* alignment, bounds */ 2004 lowaddr, /* lowaddr */ 2005 BUS_SPACE_MAXADDR, /* highaddr */ 2006 NULL, NULL, /* filter, filterarg */ 2007 sctx->isc_rx_maxsize, /* maxsize */ 2008 sctx->isc_rx_nsegments, /* nsegments */ 2009 sctx->isc_rx_maxsegsize, /* maxsegsize */ 2010 0, /* flags */ 2011 NULL, /* lockfunc */ 2012 NULL, /* lockarg */ 2013 &fl->ifl_buf_tag); 2014 if (err) { 2015 device_printf(dev, 2016 "Unable to allocate RX DMA tag: %d\n", err); 2017 goto fail; 2018 } 2019 2020 /* Allocate memory for the RX mbuf map. */ 2021 if (!(fl->ifl_sds.ifsd_m = 2022 (struct mbuf **) malloc(sizeof(struct mbuf *) * 2023 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2024 device_printf(dev, 2025 "Unable to allocate RX mbuf map memory\n"); 2026 err = ENOMEM; 2027 goto fail; 2028 } 2029 2030 /* Allocate memory for the direct RX cluster pointer map. */ 2031 if (!(fl->ifl_sds.ifsd_cl = 2032 (caddr_t *) malloc(sizeof(caddr_t) * 2033 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2034 device_printf(dev, 2035 "Unable to allocate RX cluster map memory\n"); 2036 err = ENOMEM; 2037 goto fail; 2038 } 2039 2040 /* Allocate memory for the RX cluster bus address map. */ 2041 if (!(fl->ifl_sds.ifsd_ba = 2042 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 2043 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2044 device_printf(dev, 2045 "Unable to allocate RX bus address map memory\n"); 2046 err = ENOMEM; 2047 goto fail; 2048 } 2049 2050 /* 2051 * Create the DMA maps for RX buffers. 2052 */ 2053 if (!(fl->ifl_sds.ifsd_map = 2054 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2055 device_printf(dev, 2056 "Unable to allocate RX buffer DMA map memory\n"); 2057 err = ENOMEM; 2058 goto fail; 2059 } 2060 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 2061 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 2062 &fl->ifl_sds.ifsd_map[i]); 2063 if (err != 0) { 2064 device_printf(dev, "Unable to create RX buffer DMA map\n"); 2065 goto fail; 2066 } 2067 } 2068 } 2069 return (0); 2070 2071 fail: 2072 iflib_rx_structures_free(ctx); 2073 return (err); 2074 } 2075 2076 /* 2077 * Internal service routines 2078 */ 2079 2080 struct rxq_refill_cb_arg { 2081 int error; 2082 bus_dma_segment_t seg; 2083 int nseg; 2084 }; 2085 2086 static void 2087 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2088 { 2089 struct rxq_refill_cb_arg *cb_arg = arg; 2090 2091 cb_arg->error = error; 2092 cb_arg->seg = segs[0]; 2093 cb_arg->nseg = nseg; 2094 } 2095 2096 /** 2097 * iflib_fl_refill - refill an rxq free-buffer list 2098 * @ctx: the iflib context 2099 * @fl: the free list to refill 2100 * @count: the number of new buffers to allocate 2101 * 2102 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 2103 * The caller must assure that @count does not exceed the queue's capacity 2104 * minus one (since we always leave a descriptor unavailable). 2105 */ 2106 static uint8_t 2107 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 2108 { 2109 struct if_rxd_update iru; 2110 struct rxq_refill_cb_arg cb_arg; 2111 struct mbuf *m; 2112 caddr_t cl, *sd_cl; 2113 struct mbuf **sd_m; 2114 bus_dmamap_t *sd_map; 2115 bus_addr_t bus_addr, *sd_ba; 2116 int err, frag_idx, i, idx, n, pidx; 2117 qidx_t credits; 2118 2119 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 2120 2121 sd_m = fl->ifl_sds.ifsd_m; 2122 sd_map = fl->ifl_sds.ifsd_map; 2123 sd_cl = fl->ifl_sds.ifsd_cl; 2124 sd_ba = fl->ifl_sds.ifsd_ba; 2125 pidx = fl->ifl_pidx; 2126 idx = pidx; 2127 frag_idx = fl->ifl_fragidx; 2128 credits = fl->ifl_credits; 2129 2130 i = 0; 2131 n = count; 2132 MPASS(n > 0); 2133 MPASS(credits + n <= fl->ifl_size); 2134 2135 if (pidx < fl->ifl_cidx) 2136 MPASS(pidx + n <= fl->ifl_cidx); 2137 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 2138 MPASS(fl->ifl_gen == 0); 2139 if (pidx > fl->ifl_cidx) 2140 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 2141 2142 DBG_COUNTER_INC(fl_refills); 2143 if (n > 8) 2144 DBG_COUNTER_INC(fl_refills_large); 2145 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 2146 while (n-- > 0) { 2147 /* 2148 * We allocate an uninitialized mbuf + cluster, mbuf is 2149 * initialized after rx. 2150 * 2151 * If the cluster is still set then we know a minimum sized 2152 * packet was received 2153 */ 2154 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2155 &frag_idx); 2156 if (frag_idx < 0) 2157 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2158 MPASS(frag_idx >= 0); 2159 if ((cl = sd_cl[frag_idx]) == NULL) { 2160 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2161 if (__predict_false(cl == NULL)) 2162 break; 2163 2164 cb_arg.error = 0; 2165 MPASS(sd_map != NULL); 2166 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2167 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2168 BUS_DMA_NOWAIT); 2169 if (__predict_false(err != 0 || cb_arg.error)) { 2170 uma_zfree(fl->ifl_zone, cl); 2171 break; 2172 } 2173 2174 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2175 sd_cl[frag_idx] = cl; 2176 #if MEMORY_LOGGING 2177 fl->ifl_cl_enqueued++; 2178 #endif 2179 } else { 2180 bus_addr = sd_ba[frag_idx]; 2181 } 2182 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2183 BUS_DMASYNC_PREREAD); 2184 2185 if (sd_m[frag_idx] == NULL) { 2186 m = m_gethdr_raw(M_NOWAIT, 0); 2187 if (__predict_false(m == NULL)) 2188 break; 2189 sd_m[frag_idx] = m; 2190 } 2191 bit_set(fl->ifl_rx_bitmap, frag_idx); 2192 #if MEMORY_LOGGING 2193 fl->ifl_m_enqueued++; 2194 #endif 2195 2196 DBG_COUNTER_INC(rx_allocs); 2197 fl->ifl_rxd_idxs[i] = frag_idx; 2198 fl->ifl_bus_addrs[i] = bus_addr; 2199 credits++; 2200 i++; 2201 MPASS(credits <= fl->ifl_size); 2202 if (++idx == fl->ifl_size) { 2203 #ifdef INVARIANTS 2204 fl->ifl_gen = 1; 2205 #endif 2206 idx = 0; 2207 } 2208 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2209 iru.iru_pidx = pidx; 2210 iru.iru_count = i; 2211 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2212 fl->ifl_pidx = idx; 2213 fl->ifl_credits = credits; 2214 pidx = idx; 2215 i = 0; 2216 } 2217 } 2218 2219 if (n < count - 1) { 2220 if (i != 0) { 2221 iru.iru_pidx = pidx; 2222 iru.iru_count = i; 2223 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2224 fl->ifl_pidx = idx; 2225 fl->ifl_credits = credits; 2226 } 2227 DBG_COUNTER_INC(rxd_flush); 2228 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2229 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2230 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2231 fl->ifl_id, fl->ifl_pidx); 2232 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2233 fl->ifl_fragidx = frag_idx + 1; 2234 if (fl->ifl_fragidx == fl->ifl_size) 2235 fl->ifl_fragidx = 0; 2236 } else { 2237 fl->ifl_fragidx = frag_idx; 2238 } 2239 } 2240 2241 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2242 } 2243 2244 static inline uint8_t 2245 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2246 { 2247 /* 2248 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2249 * This is important as it confuses most NICs. For instance, 2250 * Intel NICs have (per receive ring) RDH and RDT registers, where 2251 * RDH points to the next receive descriptor to be used by the NIC, 2252 * and RDT for the next receive descriptor to be published by the 2253 * driver to the NIC (RDT - 1 is thus the last valid one). 2254 * The condition RDH == RDT means no descriptors are available to 2255 * the NIC, and thus it would be ambiguous if it also meant that 2256 * all the descriptors are available to the NIC. 2257 */ 2258 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2259 #ifdef INVARIANTS 2260 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2261 #endif 2262 2263 MPASS(fl->ifl_credits <= fl->ifl_size); 2264 MPASS(reclaimable == delta); 2265 2266 if (reclaimable > 0) 2267 return (iflib_fl_refill(ctx, fl, reclaimable)); 2268 return (0); 2269 } 2270 2271 uint8_t 2272 iflib_in_detach(if_ctx_t ctx) 2273 { 2274 bool in_detach; 2275 2276 STATE_LOCK(ctx); 2277 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2278 STATE_UNLOCK(ctx); 2279 return (in_detach); 2280 } 2281 2282 static void 2283 iflib_fl_bufs_free(iflib_fl_t fl) 2284 { 2285 iflib_dma_info_t idi = fl->ifl_ifdi; 2286 bus_dmamap_t sd_map; 2287 uint32_t i; 2288 2289 for (i = 0; i < fl->ifl_size; i++) { 2290 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2291 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2292 2293 if (*sd_cl != NULL) { 2294 sd_map = fl->ifl_sds.ifsd_map[i]; 2295 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2296 BUS_DMASYNC_POSTREAD); 2297 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2298 uma_zfree(fl->ifl_zone, *sd_cl); 2299 *sd_cl = NULL; 2300 if (*sd_m != NULL) { 2301 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2302 m_free_raw(*sd_m); 2303 *sd_m = NULL; 2304 } 2305 } else { 2306 MPASS(*sd_m == NULL); 2307 } 2308 #if MEMORY_LOGGING 2309 fl->ifl_m_dequeued++; 2310 fl->ifl_cl_dequeued++; 2311 #endif 2312 } 2313 #ifdef INVARIANTS 2314 for (i = 0; i < fl->ifl_size; i++) { 2315 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2316 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2317 } 2318 #endif 2319 /* 2320 * Reset free list values 2321 */ 2322 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2323 bzero(idi->idi_vaddr, idi->idi_size); 2324 } 2325 2326 /********************************************************************* 2327 * 2328 * Initialize a free list and its buffers. 2329 * 2330 **********************************************************************/ 2331 static int 2332 iflib_fl_setup(iflib_fl_t fl) 2333 { 2334 iflib_rxq_t rxq = fl->ifl_rxq; 2335 if_ctx_t ctx = rxq->ifr_ctx; 2336 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2337 int qidx; 2338 2339 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2340 /* 2341 * Free current RX buffer structs and their mbufs 2342 */ 2343 iflib_fl_bufs_free(fl); 2344 /* Now replenish the mbufs */ 2345 MPASS(fl->ifl_credits == 0); 2346 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2347 if (scctx->isc_rxd_buf_size[qidx] != 0) 2348 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2349 else 2350 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2351 /* 2352 * ifl_buf_size may be a driver-supplied value, so pull it up 2353 * to the selected mbuf size. 2354 */ 2355 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2356 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2357 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2358 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2359 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2360 2361 /* 2362 * Avoid pre-allocating zillions of clusters to an idle card 2363 * potentially speeding up attach. In any case make sure 2364 * to leave a descriptor unavailable. See the comment in 2365 * iflib_fl_refill_all(). 2366 */ 2367 MPASS(fl->ifl_size > 0); 2368 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2369 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2370 return (ENOBUFS); 2371 /* 2372 * handle failure 2373 */ 2374 MPASS(rxq != NULL); 2375 MPASS(fl->ifl_ifdi != NULL); 2376 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2377 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2378 return (0); 2379 } 2380 2381 /********************************************************************* 2382 * 2383 * Free receive ring data structures 2384 * 2385 **********************************************************************/ 2386 static void 2387 iflib_rx_sds_free(iflib_rxq_t rxq) 2388 { 2389 iflib_fl_t fl; 2390 int i, j; 2391 2392 if (rxq->ifr_fl != NULL) { 2393 for (i = 0; i < rxq->ifr_nfl; i++) { 2394 fl = &rxq->ifr_fl[i]; 2395 if (fl->ifl_buf_tag != NULL) { 2396 if (fl->ifl_sds.ifsd_map != NULL) { 2397 for (j = 0; j < fl->ifl_size; j++) { 2398 bus_dmamap_sync( 2399 fl->ifl_buf_tag, 2400 fl->ifl_sds.ifsd_map[j], 2401 BUS_DMASYNC_POSTREAD); 2402 bus_dmamap_unload( 2403 fl->ifl_buf_tag, 2404 fl->ifl_sds.ifsd_map[j]); 2405 bus_dmamap_destroy( 2406 fl->ifl_buf_tag, 2407 fl->ifl_sds.ifsd_map[j]); 2408 } 2409 } 2410 bus_dma_tag_destroy(fl->ifl_buf_tag); 2411 fl->ifl_buf_tag = NULL; 2412 } 2413 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2414 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2415 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2416 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2417 free(fl->ifl_rx_bitmap, M_IFLIB); 2418 fl->ifl_sds.ifsd_m = NULL; 2419 fl->ifl_sds.ifsd_cl = NULL; 2420 fl->ifl_sds.ifsd_ba = NULL; 2421 fl->ifl_sds.ifsd_map = NULL; 2422 fl->ifl_rx_bitmap = NULL; 2423 } 2424 free(rxq->ifr_fl, M_IFLIB); 2425 rxq->ifr_fl = NULL; 2426 free(rxq->ifr_ifdi, M_IFLIB); 2427 rxq->ifr_ifdi = NULL; 2428 rxq->ifr_cq_cidx = 0; 2429 } 2430 } 2431 2432 /* 2433 * Timer routine 2434 */ 2435 static void 2436 iflib_timer(void *arg) 2437 { 2438 iflib_txq_t txq = arg; 2439 if_ctx_t ctx = txq->ift_ctx; 2440 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2441 uint64_t this_tick = ticks; 2442 2443 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2444 return; 2445 2446 /* 2447 * Check on the state of the TX queue(s); this can be done 2448 * without the lock: the counters the check reads are only 2449 * advanced by the queue's tx task and a stale read just 2450 * delays the verdict by one timer period. 2451 */ 2452 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) { 2453 qidx_t in_use, outstanding; 2454 bool demand, frozen; 2455 2456 txq->ift_last_timer_tick = this_tick; 2457 IFDI_TIMER(ctx, txq->ift_id); 2458 2459 /* 2460 * Descriptors the hardware has not reported as 2461 * completed: neither harvested as credits 2462 * (ift_processed) nor reclaimed (ift_cleaned accounts 2463 * the difference to ift_in_use). The tail whose 2464 * report-status request is still deferred is never 2465 * reported and must not count. 2466 */ 2467 in_use = txq->ift_in_use; 2468 outstanding = in_use - 2469 (qidx_t)(txq->ift_processed - txq->ift_cleaned); 2470 2471 /* 2472 * The queue is frozen while it has descriptors the 2473 * hardware has not reported as completed and none 2474 * were reclaimed over the period; the link must be 2475 * up, with no pause frames and no pending doorbell 2476 * (the laggard check below rings it). 2477 * 2478 * Being frozen is not a fault - the hardware may defer 2479 * marking descriptors as completed indefinitely, and 2480 * 8254x hardware does so for a quiet queue. Continue 2481 * arming only while demand persists: the outstanding 2482 * count grows, the software ring is stalled, or the 2483 * hardware ring has reached iflib's backpressure 2484 * threshold. The last condition covers simple-TX, which 2485 * does not use the software ring. This also prevents one 2486 * mixed lockless counter sample from arming a quiet queue 2487 * until the verdict. Act only once it has stayed frozen 2488 * under demand for 2489 * net.iflib.tx_watchdog_periods consecutive periods. 2490 */ 2491 frozen = outstanding > txq->ift_rs_pending && 2492 txq->ift_processed == txq->ift_processed_prev && 2493 txq->ift_db_pending == 0 && 2494 sctx->isc_pause_frames == 0 && 2495 ctx->ifc_link_state == LINK_STATE_UP; 2496 demand = outstanding > txq->ift_outstanding_prev || 2497 ifmp_ring_is_stalled(txq->ift_br) || 2498 in_use + MAX_TX_DESC(ctx) >= txq->ift_size - txq->ift_pad; 2499 if (!frozen || !demand) 2500 txq->ift_wdog_armed = 0; 2501 else { 2502 if (txq->ift_wdog_armed < UINT16_MAX) 2503 txq->ift_wdog_armed++; 2504 } 2505 2506 /* 2507 * Frozen long enough: ask the hardware. Completions 2508 * ready but unharvested for this long mean the 2509 * completion interrupt went missing - kick the 2510 * queue's task. Nothing ready while demand persisted 2511 * means it is hung. 2512 */ 2513 if (iflib_tx_watchdog_periods > 0 && 2514 txq->ift_wdog_armed >= iflib_tx_watchdog_periods) { 2515 bus_dmamap_sync(txq->ift_ifdi->idi_tag, 2516 txq->ift_ifdi->idi_map, BUS_DMASYNC_POSTREAD); 2517 if (ctx->isc_txd_credits_update(ctx->ifc_softc, 2518 txq->ift_id, false) == 0) { 2519 device_printf(ctx->ifc_dev, 2520 "Watchdog timeout (TX: %d desc " 2521 "avail: %d pidx: %d) -- resetting\n", 2522 txq->ift_id, TXQ_AVAIL(txq), 2523 txq->ift_pidx); 2524 STATE_LOCK(ctx); 2525 if_setdrvflagbits(ctx->ifc_ifp, 2526 IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2527 ctx->ifc_flags |= 2528 (IFC_DO_WATCHDOG | IFC_DO_RESET); 2529 iflib_admin_intr_deferred(ctx); 2530 STATE_UNLOCK(ctx); 2531 return; 2532 } 2533 GROUPTASK_ENQUEUE(&txq->ift_task); 2534 } 2535 txq->ift_outstanding_prev = outstanding; 2536 txq->ift_processed_prev = txq->ift_processed; 2537 } 2538 /* handle any laggards */ 2539 if (txq->ift_db_pending) 2540 GROUPTASK_ENQUEUE(&txq->ift_task); 2541 2542 sctx->isc_pause_frames = 0; 2543 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2544 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, 2545 txq, txq->ift_timer.c_cpu); 2546 } 2547 2548 static uint16_t 2549 iflib_get_mbuf_size_for(unsigned int size) 2550 { 2551 2552 if (size <= MCLBYTES) 2553 return (MCLBYTES); 2554 else 2555 return (MJUMPAGESIZE); 2556 } 2557 2558 static void 2559 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2560 { 2561 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2562 2563 /* 2564 * XXX don't set the max_frame_size to larger 2565 * than the hardware can handle 2566 */ 2567 ctx->ifc_rx_mbuf_sz = 2568 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2569 } 2570 2571 uint32_t 2572 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2573 { 2574 2575 return (ctx->ifc_rx_mbuf_sz); 2576 } 2577 2578 static void 2579 iflib_init_locked(if_ctx_t ctx) 2580 { 2581 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2582 if_t ifp = ctx->ifc_ifp; 2583 iflib_fl_t fl; 2584 iflib_txq_t txq; 2585 iflib_rxq_t rxq; 2586 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2587 bool init_failed; 2588 2589 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2590 IFDI_INTR_DISABLE(ctx); 2591 2592 /* 2593 * See iflib_stop(). Useful in case iflib_init_locked() is 2594 * called without first calling iflib_stop(). 2595 */ 2596 netmap_disable_all_rings(ifp); 2597 2598 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2599 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2600 /* Set hardware offload abilities */ 2601 if_clearhwassist(ifp); 2602 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2603 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2604 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2605 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2606 if (if_getcapenable(ifp) & IFCAP_TSO4) 2607 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2608 if (if_getcapenable(ifp) & IFCAP_TSO6) 2609 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2610 2611 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 2612 CALLOUT_LOCK(txq); 2613 callout_stop(&txq->ift_timer); 2614 #ifdef DEV_NETMAP 2615 callout_stop(&txq->ift_netmap_timer); 2616 #endif /* DEV_NETMAP */ 2617 CALLOUT_UNLOCK(txq); 2618 (void)iflib_netmap_txq_init(ctx, txq); 2619 } 2620 2621 /* 2622 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2623 * that drivers can use the value when setting up the hardware receive 2624 * buffers. 2625 */ 2626 iflib_calc_rx_mbuf_sz(ctx); 2627 2628 #ifdef INVARIANTS 2629 i = if_getdrvflags(ifp); 2630 #endif 2631 STATE_LOCK(ctx); 2632 ctx->ifc_flags &= ~IFC_INIT_FAILED; 2633 STATE_UNLOCK(ctx); 2634 IFDI_INIT(ctx); 2635 MPASS(if_getdrvflags(ifp) == i); 2636 STATE_LOCK(ctx); 2637 init_failed = (ctx->ifc_flags & IFC_INIT_FAILED) != 0; 2638 STATE_UNLOCK(ctx); 2639 if (init_failed) 2640 return; 2641 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 2642 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2643 /* This rxq is in netmap mode. Skip normal init. */ 2644 continue; 2645 } 2646 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2647 if (iflib_fl_setup(fl)) { 2648 device_printf(ctx->ifc_dev, 2649 "setting up free list %d failed - " 2650 "check cluster settings\n", j); 2651 goto done; 2652 } 2653 } 2654 } 2655 done: 2656 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2657 IFDI_INTR_ENABLE(ctx); 2658 txq = ctx->ifc_txqs; 2659 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) 2660 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 2661 txq->ift_timer.c_cpu); 2662 2663 /* Re-enable txsync/rxsync. */ 2664 netmap_enable_all_rings(ifp); 2665 } 2666 2667 static int 2668 iflib_media_change(if_t ifp) 2669 { 2670 if_ctx_t ctx = if_getsoftc(ifp); 2671 int err; 2672 2673 CTX_LOCK(ctx); 2674 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2675 iflib_if_init_locked(ctx); 2676 CTX_UNLOCK(ctx); 2677 return (err); 2678 } 2679 2680 static void 2681 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2682 { 2683 if_ctx_t ctx = if_getsoftc(ifp); 2684 bool oactive, running; 2685 2686 STATE_LOCK(ctx); 2687 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 2688 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 2689 STATE_UNLOCK(ctx); 2690 2691 CTX_LOCK(ctx); 2692 /* 2693 * There is no need to update the admin status when it is done regularly by 2694 * _task_fn_admin(), so only do it if that's not running. That can be quite 2695 * expensive on some drivers. 2696 */ 2697 if ((!running && !oactive) && 2698 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) { 2699 IFDI_UPDATE_ADMIN_STATUS(ctx); 2700 } 2701 IFDI_MEDIA_STATUS(ctx, ifmr); 2702 CTX_UNLOCK(ctx); 2703 } 2704 2705 static void 2706 iflib_stop(if_ctx_t ctx) 2707 { 2708 iflib_txq_t txq = ctx->ifc_txqs; 2709 iflib_rxq_t rxq = ctx->ifc_rxqs; 2710 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2711 if_shared_ctx_t sctx = ctx->ifc_sctx; 2712 iflib_dma_info_t di; 2713 iflib_fl_t fl; 2714 int i, j; 2715 2716 /* Tell the stack that the interface is no longer active */ 2717 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2718 2719 IFDI_INTR_DISABLE(ctx); 2720 DELAY(1000); 2721 IFDI_STOP(ctx); 2722 DELAY(1000); 2723 2724 /* 2725 * Stop any pending txsync/rxsync and prevent new ones 2726 * form starting. Processes blocked in poll() will get 2727 * POLLERR. 2728 */ 2729 netmap_disable_all_rings(ctx->ifc_ifp); 2730 2731 iflib_debug_reset(); 2732 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2733 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2734 /* make sure all transmitters have completed before proceeding XXX */ 2735 2736 CALLOUT_LOCK(txq); 2737 callout_stop(&txq->ift_timer); 2738 #ifdef DEV_NETMAP 2739 callout_stop(&txq->ift_netmap_timer); 2740 #endif /* DEV_NETMAP */ 2741 CALLOUT_UNLOCK(txq); 2742 2743 if (!ctx->ifc_sysctl_simple_tx) { 2744 /* clean any enqueued buffers */ 2745 iflib_ifmp_purge(txq); 2746 } 2747 /* Free any existing tx buffers. */ 2748 for (j = 0; j < txq->ift_size; j++) { 2749 iflib_txsd_free(ctx, txq, j); 2750 } 2751 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2752 txq->ift_processed_prev = 0; 2753 txq->ift_outstanding_prev = 0; 2754 txq->ift_wdog_armed = 0; 2755 txq->ift_in_use = txq->ift_gen = txq->ift_no_desc_avail = 0; 2756 txq->ift_npending = txq->ift_db_pending = 0; 2757 txq->ift_rs_pending = 0; 2758 if (sctx->isc_flags & IFLIB_PRESERVE_TX_INDICES) 2759 txq->ift_cidx = txq->ift_pidx; 2760 else 2761 txq->ift_cidx = txq->ift_pidx = 0; 2762 2763 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2764 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2765 txq->ift_pullups = 0; 2766 ifmp_ring_reset_stats(txq->ift_br); 2767 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2768 bzero((void *)di->idi_vaddr, di->idi_size); 2769 } 2770 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2771 if (rxq->ifr_task.gt_taskqueue != NULL) 2772 gtaskqueue_drain(rxq->ifr_task.gt_taskqueue, 2773 &rxq->ifr_task.gt_task); 2774 2775 rxq->ifr_cq_cidx = 0; 2776 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2777 bzero((void *)di->idi_vaddr, di->idi_size); 2778 /* also resets the free lists pidx/cidx */ 2779 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2780 iflib_fl_bufs_free(fl); 2781 } 2782 } 2783 2784 static inline caddr_t 2785 calc_next_rxd(iflib_fl_t fl, int cidx) 2786 { 2787 qidx_t size; 2788 int nrxd; 2789 caddr_t start, end, cur, next; 2790 2791 nrxd = fl->ifl_size; 2792 size = fl->ifl_rxd_size; 2793 start = fl->ifl_ifdi->idi_vaddr; 2794 2795 if (__predict_false(size == 0)) 2796 return (start); 2797 cur = start + size * cidx; 2798 end = start + size * nrxd; 2799 next = CACHE_PTR_NEXT(cur); 2800 return (next < end ? next : start); 2801 } 2802 2803 static inline void 2804 prefetch_pkts(iflib_fl_t fl, int cidx) 2805 { 2806 int nextptr; 2807 int nrxd = fl->ifl_size; 2808 caddr_t next_rxd; 2809 2810 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd - 1); 2811 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2812 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2813 next_rxd = calc_next_rxd(fl, cidx); 2814 prefetch(next_rxd); 2815 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd - 1)]); 2816 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd - 1)]); 2817 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd - 1)]); 2818 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd - 1)]); 2819 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd - 1)]); 2820 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd - 1)]); 2821 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd - 1)]); 2822 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd - 1)]); 2823 } 2824 2825 static struct mbuf * 2826 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2827 int *pf_rv, if_rxd_info_t ri) 2828 { 2829 bus_dmamap_t map; 2830 iflib_fl_t fl; 2831 caddr_t payload; 2832 struct mbuf *m; 2833 int flid, cidx, len, next; 2834 2835 map = NULL; 2836 flid = irf->irf_flid; 2837 cidx = irf->irf_idx; 2838 fl = &rxq->ifr_fl[flid]; 2839 sd->ifsd_fl = fl; 2840 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2841 fl->ifl_credits--; 2842 #if MEMORY_LOGGING 2843 fl->ifl_m_dequeued++; 2844 #endif 2845 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2846 prefetch_pkts(fl, cidx); 2847 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size - 1); 2848 prefetch(&fl->ifl_sds.ifsd_map[next]); 2849 map = fl->ifl_sds.ifsd_map[cidx]; 2850 2851 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2852 2853 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2854 irf->irf_len != 0) { 2855 payload = *sd->ifsd_cl; 2856 payload += ri->iri_pad; 2857 len = ri->iri_len - ri->iri_pad; 2858 *pf_rv = pfil_mem_in(rxq->pfil, payload, len, ri->iri_ifp, &m); 2859 switch (*pf_rv) { 2860 case PFIL_DROPPED: 2861 case PFIL_CONSUMED: 2862 /* 2863 * The filter ate it. Everything is recycled. 2864 */ 2865 m = NULL; 2866 unload = 0; 2867 break; 2868 case PFIL_REALLOCED: 2869 /* 2870 * The filter copied it. Everything is recycled. 2871 * 'm' points at new mbuf. 2872 */ 2873 unload = 0; 2874 break; 2875 case PFIL_PASS: 2876 /* 2877 * Filter said it was OK, so receive like 2878 * normal 2879 */ 2880 m = fl->ifl_sds.ifsd_m[cidx]; 2881 fl->ifl_sds.ifsd_m[cidx] = NULL; 2882 break; 2883 default: 2884 MPASS(0); 2885 } 2886 } else { 2887 m = fl->ifl_sds.ifsd_m[cidx]; 2888 fl->ifl_sds.ifsd_m[cidx] = NULL; 2889 if (pf_rv != NULL) 2890 *pf_rv = PFIL_PASS; 2891 } 2892 2893 if (unload && irf->irf_len != 0) 2894 bus_dmamap_unload(fl->ifl_buf_tag, map); 2895 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size - 1); 2896 if (__predict_false(fl->ifl_cidx == 0)) 2897 fl->ifl_gen = 0; 2898 bit_clear(fl->ifl_rx_bitmap, cidx); 2899 return (m); 2900 } 2901 2902 static struct mbuf * 2903 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2904 { 2905 struct mbuf *m, *mh, *mt; 2906 caddr_t cl; 2907 int *pf_rv_ptr, flags, i, padlen; 2908 bool consumed; 2909 2910 i = 0; 2911 mh = NULL; 2912 consumed = false; 2913 *pf_rv = PFIL_PASS; 2914 pf_rv_ptr = pf_rv; 2915 do { 2916 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2917 pf_rv_ptr, ri); 2918 2919 MPASS(*sd->ifsd_cl != NULL); 2920 2921 /* 2922 * Exclude zero-length frags & frags from 2923 * packets the filter has consumed or dropped 2924 */ 2925 if (ri->iri_frags[i].irf_len == 0 || consumed || 2926 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2927 if (mh == NULL) { 2928 consumed = true; 2929 pf_rv_ptr = NULL; 2930 } 2931 /* XXX we can save the cluster here, but not the mbuf */ 2932 if (m != NULL) { 2933 m_init(m, M_NOWAIT, MT_DATA, 0); 2934 m_free(m); 2935 } 2936 continue; 2937 } 2938 if (mh == NULL) { 2939 flags = M_PKTHDR | M_EXT; 2940 mh = mt = m; 2941 padlen = ri->iri_pad; 2942 } else { 2943 flags = M_EXT; 2944 mt->m_next = m; 2945 mt = m; 2946 /* assuming padding is only on the first fragment */ 2947 padlen = 0; 2948 } 2949 cl = *sd->ifsd_cl; 2950 *sd->ifsd_cl = NULL; 2951 2952 /* Can these two be made one ? */ 2953 m_init(m, M_NOWAIT, MT_DATA, flags); 2954 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2955 /* 2956 * These must follow m_init and m_cljset 2957 */ 2958 m->m_data += padlen; 2959 ri->iri_len -= padlen; 2960 m->m_len = ri->iri_frags[i].irf_len; 2961 } while (++i < ri->iri_nfrags); 2962 2963 return (mh); 2964 } 2965 2966 /* 2967 * Process one software descriptor 2968 */ 2969 static struct mbuf * 2970 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2971 { 2972 struct if_rxsd sd; 2973 struct mbuf *m; 2974 int pf_rv; 2975 2976 /* should I merge this back in now that the two paths are basically duplicated? */ 2977 if (ri->iri_nfrags == 1 && 2978 ri->iri_frags[0].irf_len != 0 && 2979 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2980 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2981 &pf_rv, ri); 2982 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2983 return (m); 2984 if (pf_rv == PFIL_PASS) { 2985 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2986 #ifndef __NO_STRICT_ALIGNMENT 2987 if (!IP_ALIGNED(m) && ri->iri_pad == 0) 2988 m->m_data += 2; 2989 #endif 2990 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2991 m->m_len = ri->iri_frags[0].irf_len; 2992 m->m_data += ri->iri_pad; 2993 ri->iri_len -= ri->iri_pad; 2994 } 2995 } else { 2996 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2997 if (m == NULL) 2998 return (NULL); 2999 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 3000 return (m); 3001 } 3002 m->m_pkthdr.len = ri->iri_len; 3003 m->m_pkthdr.rcvif = ri->iri_ifp; 3004 m->m_flags |= ri->iri_flags & IFLIB_IRI_VALID_FLAGS; 3005 m->m_pkthdr.ether_vtag = ri->iri_vtag; 3006 m->m_pkthdr.flowid = ri->iri_flowid; 3007 #ifdef NUMA 3008 m->m_pkthdr.numa_domain = if_getnumadomain(ri->iri_ifp); 3009 #endif 3010 M_HASHTYPE_SET(m, ri->iri_rsstype); 3011 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 3012 m->m_pkthdr.csum_data = ri->iri_csum_data; 3013 m->m_pkthdr.rcv_tstmp = ri->iri_rcv_tstmp; 3014 return (m); 3015 } 3016 3017 static void 3018 _task_fn_rx_watchdog(void *context) 3019 { 3020 iflib_rxq_t rxq = context; 3021 3022 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3023 } 3024 3025 static uint8_t 3026 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 3027 { 3028 if_t ifp; 3029 if_ctx_t ctx = rxq->ifr_ctx; 3030 if_shared_ctx_t sctx = ctx->ifc_sctx; 3031 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 3032 int avail, i; 3033 qidx_t *cidxp; 3034 struct if_rxd_info ri; 3035 int err, budget_left, rx_bytes, rx_pkts; 3036 iflib_fl_t fl; 3037 #if defined(INET6) || defined(INET) 3038 int lro_enabled; 3039 #endif 3040 uint8_t retval = 0; 3041 3042 /* 3043 * XXX early demux data packets so that if_input processing only handles 3044 * acks in interrupt context 3045 */ 3046 struct mbuf *m, *mh, *mt; 3047 3048 NET_EPOCH_ASSERT(); 3049 3050 ifp = ctx->ifc_ifp; 3051 mh = mt = NULL; 3052 MPASS(budget > 0); 3053 rx_pkts = rx_bytes = 0; 3054 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 3055 cidxp = &rxq->ifr_cq_cidx; 3056 else 3057 cidxp = &rxq->ifr_fl[0].ifl_cidx; 3058 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 3059 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3060 retval |= iflib_fl_refill_all(ctx, fl); 3061 DBG_COUNTER_INC(rx_unavail); 3062 return (retval); 3063 } 3064 3065 #if defined(INET6) || defined(INET) 3066 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 3067 #endif 3068 3069 /* pfil needs the vnet to be set */ 3070 CURVNET_SET_QUIET(if_getvnet(ifp)); 3071 for (budget_left = budget; budget_left > 0 && avail > 0;) { 3072 if (__predict_false(!CTX_ACTIVE(ctx))) { 3073 DBG_COUNTER_INC(rx_ctx_inactive); 3074 break; 3075 } 3076 /* 3077 * Reset client set fields to their default values 3078 */ 3079 memset(&ri, 0, sizeof(ri)); 3080 ri.iri_qsidx = rxq->ifr_id; 3081 ri.iri_cidx = *cidxp; 3082 ri.iri_ifp = ifp; 3083 ri.iri_frags = rxq->ifr_frags; 3084 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 3085 3086 if (err) { 3087 CURVNET_RESTORE(); 3088 goto err; 3089 } 3090 rx_pkts += 1; 3091 rx_bytes += ri.iri_len; 3092 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 3093 *cidxp = ri.iri_cidx; 3094 /* Update our consumer index */ 3095 /* XXX NB: shurd - check if this is still safe */ 3096 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 3097 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 3098 /* was this only a completion queue message? */ 3099 if (__predict_false(ri.iri_nfrags == 0)) 3100 continue; 3101 } 3102 MPASS(ri.iri_nfrags != 0); 3103 MPASS(ri.iri_len != 0); 3104 3105 /* will advance the cidx on the corresponding free lists */ 3106 m = iflib_rxd_pkt_get(rxq, &ri); 3107 avail--; 3108 budget_left--; 3109 if (avail == 0 && budget_left) 3110 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 3111 3112 if (__predict_false(m == NULL)) 3113 continue; 3114 3115 #ifndef __NO_STRICT_ALIGNMENT 3116 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 3117 continue; 3118 #endif 3119 #if defined(INET6) || defined(INET) 3120 if (lro_enabled) { 3121 tcp_lro_queue_mbuf(&rxq->ifr_lc, m); 3122 continue; 3123 } 3124 #endif 3125 3126 if (mh == NULL) 3127 mh = mt = m; 3128 else { 3129 mt->m_nextpkt = m; 3130 mt = m; 3131 } 3132 } 3133 CURVNET_RESTORE(); 3134 /* make sure that we can refill faster than drain */ 3135 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3136 retval |= iflib_fl_refill_all(ctx, fl); 3137 3138 if (mh != NULL) { 3139 if_input(ifp, mh); 3140 DBG_COUNTER_INC(rx_if_input); 3141 } 3142 3143 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 3144 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 3145 3146 /* 3147 * Flush any outstanding LRO work 3148 */ 3149 #if defined(INET6) || defined(INET) 3150 tcp_lro_flush_all(&rxq->ifr_lc); 3151 #endif 3152 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 3153 retval |= IFLIB_RXEOF_MORE; 3154 return (retval); 3155 err: 3156 STATE_LOCK(ctx); 3157 ctx->ifc_flags |= IFC_DO_RESET; 3158 iflib_admin_intr_deferred(ctx); 3159 STATE_UNLOCK(ctx); 3160 return (0); 3161 } 3162 3163 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq) - 1) 3164 static inline qidx_t 3165 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 3166 { 3167 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3168 qidx_t minthresh = txq->ift_size / 8; 3169 if (in_use > 4 * minthresh) 3170 return (notify_count); 3171 if (in_use > 2 * minthresh) 3172 return (notify_count >> 1); 3173 if (in_use > minthresh) 3174 return (notify_count >> 3); 3175 return (0); 3176 } 3177 3178 static inline qidx_t 3179 txq_max_rs_deferred(iflib_txq_t txq) 3180 { 3181 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3182 qidx_t minthresh = txq->ift_size / 8; 3183 if (txq->ift_in_use > 4 * minthresh) 3184 return (notify_count); 3185 if (txq->ift_in_use > 2 * minthresh) 3186 return (notify_count >> 1); 3187 if (txq->ift_in_use > minthresh) 3188 return (notify_count >> 2); 3189 return (2); 3190 } 3191 3192 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 3193 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 3194 3195 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 3196 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 3197 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 3198 3199 /* forward compatibility for cxgb */ 3200 #define FIRST_QSET(ctx) 0 3201 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3202 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3203 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3204 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3205 3206 static inline bool 3207 iflib_txd_db_check(iflib_txq_t txq, int ring) 3208 { 3209 if_ctx_t ctx = txq->ift_ctx; 3210 qidx_t dbval, max; 3211 3212 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use); 3213 3214 /* force || threshold exceeded || at the edge of the ring */ 3215 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx))) { 3216 3217 /* 3218 * 'npending' is used if the card's doorbell is in terms of the number of descriptors 3219 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the 3220 * producer index explicitly (INTC). 3221 */ 3222 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3223 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3224 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3225 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3226 3227 /* 3228 * Absent bugs there are zero packets pending so reset pending counts to zero. 3229 */ 3230 txq->ift_db_pending = txq->ift_npending = 0; 3231 return (true); 3232 } 3233 return (false); 3234 } 3235 3236 #ifdef PKT_DEBUG 3237 static void 3238 print_pkt(if_pkt_info_t pi) 3239 { 3240 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3241 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3242 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3243 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3244 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3245 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3246 } 3247 #endif 3248 3249 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3250 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3251 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3252 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3253 3254 /** 3255 * Parses out ethernet header information in the given mbuf. 3256 * Returns in pi: ipi_etype (EtherType) and ipi_ehdrlen (Ethernet header length) 3257 * 3258 * This will account for the VLAN header if present. 3259 * 3260 * XXX: This doesn't handle QinQ, which could prevent TX offloads for those 3261 * types of packets. 3262 */ 3263 static int 3264 iflib_parse_ether_header(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3265 { 3266 struct ether_vlan_header *eh; 3267 struct mbuf *m; 3268 3269 m = *mp; 3270 if (__predict_false(m->m_len < sizeof(*eh))) { 3271 (*pullups)++; 3272 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3273 return (ENOMEM); 3274 } 3275 eh = mtod(m, struct ether_vlan_header *); 3276 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3277 pi->ipi_etype = ntohs(eh->evl_proto); 3278 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3279 } else { 3280 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3281 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3282 } 3283 *mp = m; 3284 3285 return (0); 3286 } 3287 3288 /** 3289 * Parse up to the L3 header and extract IPv4/IPv6 header information into pi. 3290 * Currently this information includes: IP ToS value, IP header version/presence 3291 * 3292 * This is missing some checks and doesn't edit the packet content as it goes, 3293 * unlike iflib_parse_header(), in order to keep the amount of code here minimal. 3294 */ 3295 static int 3296 iflib_parse_header_partial(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3297 { 3298 struct mbuf *m; 3299 int err; 3300 3301 *pullups = 0; 3302 m = *mp; 3303 if (!M_WRITABLE(m)) { 3304 m = m_dup(m, M_NOWAIT); 3305 m_freem(*mp); 3306 DBG_COUNTER_INC(tx_frees); 3307 *mp = m; 3308 if (m == NULL) 3309 return (ENOMEM); 3310 } 3311 3312 /* Fills out pi->ipi_etype */ 3313 err = iflib_parse_ether_header(pi, mp, pullups); 3314 if (err) 3315 return (err); 3316 m = *mp; 3317 3318 switch (pi->ipi_etype) { 3319 #ifdef INET 3320 case ETHERTYPE_IP: 3321 { 3322 struct mbuf *n; 3323 struct ip *ip = NULL; 3324 int miniplen; 3325 3326 miniplen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip)); 3327 if (__predict_false(m->m_len < miniplen)) { 3328 /* 3329 * Check for common case where the first mbuf only contains 3330 * the Ethernet header 3331 */ 3332 if (m->m_len == pi->ipi_ehdrlen) { 3333 n = m->m_next; 3334 MPASS(n); 3335 /* If next mbuf contains at least the minimal IP header, then stop */ 3336 if (n->m_len >= sizeof(*ip)) { 3337 ip = (struct ip *)n->m_data; 3338 } else { 3339 (*pullups)++; 3340 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3341 return (ENOMEM); 3342 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3343 } 3344 } else { 3345 (*pullups)++; 3346 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3347 return (ENOMEM); 3348 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3349 } 3350 } else { 3351 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3352 } 3353 3354 /* Have the IPv4 header w/ no options here */ 3355 pi->ipi_ip_hlen = ip->ip_hl << 2; 3356 pi->ipi_ipproto = ip->ip_p; 3357 pi->ipi_ip_tos = ip->ip_tos; 3358 pi->ipi_flags |= IPI_TX_IPV4; 3359 3360 break; 3361 } 3362 #endif 3363 #ifdef INET6 3364 case ETHERTYPE_IPV6: 3365 { 3366 struct ip6_hdr *ip6; 3367 3368 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3369 (*pullups)++; 3370 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3371 return (ENOMEM); 3372 } 3373 ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3374 3375 /* Have the IPv6 fixed header here */ 3376 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3377 pi->ipi_ipproto = ip6->ip6_nxt; 3378 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3379 pi->ipi_flags |= IPI_TX_IPV6; 3380 3381 break; 3382 } 3383 #endif 3384 default: 3385 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3386 pi->ipi_ip_hlen = 0; 3387 break; 3388 } 3389 *mp = m; 3390 3391 return (0); 3392 3393 } 3394 3395 static int 3396 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3397 { 3398 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3399 struct mbuf *m; 3400 int err; 3401 3402 m = *mp; 3403 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3404 M_WRITABLE(m) == 0) { 3405 m = m_dup(m, M_NOWAIT); 3406 m_freem(*mp); 3407 DBG_COUNTER_INC(tx_frees); 3408 *mp = m; 3409 if (m == NULL) 3410 return (ENOMEM); 3411 } 3412 3413 /* Fills out pi->ipi_etype */ 3414 err = iflib_parse_ether_header(pi, mp, &txq->ift_pullups); 3415 if (__predict_false(err)) 3416 return (err); 3417 m = *mp; 3418 3419 switch (pi->ipi_etype) { 3420 #ifdef INET 3421 case ETHERTYPE_IP: 3422 { 3423 struct ip *ip; 3424 struct tcphdr *th; 3425 uint8_t hlen; 3426 3427 hlen = pi->ipi_ehdrlen + sizeof(*ip); 3428 if (__predict_false(m->m_len < hlen)) { 3429 txq->ift_pullups++; 3430 if (__predict_false((m = m_pullup(m, hlen)) == NULL)) 3431 return (ENOMEM); 3432 } 3433 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3434 hlen = pi->ipi_ehdrlen + (ip->ip_hl << 2); 3435 if (ip->ip_p == IPPROTO_TCP) { 3436 hlen += sizeof(*th); 3437 th = (struct tcphdr *)((char *)ip + (ip->ip_hl << 2)); 3438 } else if (ip->ip_p == IPPROTO_UDP) { 3439 hlen += sizeof(struct udphdr); 3440 } 3441 if (__predict_false(m->m_len < hlen)) { 3442 txq->ift_pullups++; 3443 if ((m = m_pullup(m, hlen)) == NULL) 3444 return (ENOMEM); 3445 /* reset pointers after pullup */ 3446 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3447 th = (struct tcphdr *)((char *)ip + (ip->ip_hl << 2)); 3448 } 3449 pi->ipi_ip_hlen = ip->ip_hl << 2; 3450 pi->ipi_ipproto = ip->ip_p; 3451 pi->ipi_ip_tos = ip->ip_tos; 3452 pi->ipi_flags |= IPI_TX_IPV4; 3453 3454 /* TCP checksum offload may require TCP header length */ 3455 if (IS_TX_OFFLOAD4(pi)) { 3456 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3457 pi->ipi_tcp_hflags = tcp_get_flags(th); 3458 pi->ipi_tcp_hlen = th->th_off << 2; 3459 pi->ipi_tcp_seq = th->th_seq; 3460 } 3461 if (IS_TSO4(pi)) { 3462 MPASS(ip->ip_p == IPPROTO_TCP); 3463 /* 3464 * TSO always requires hardware checksum offload. 3465 */ 3466 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3467 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3468 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3469 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3470 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3471 ip->ip_sum = 0; 3472 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3473 } 3474 } 3475 } 3476 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3477 ip->ip_sum = 0; 3478 3479 break; 3480 } 3481 #endif 3482 #ifdef INET6 3483 case ETHERTYPE_IPV6: 3484 { 3485 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3486 struct tcphdr *th; 3487 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3488 3489 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3490 txq->ift_pullups++; 3491 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3492 return (ENOMEM); 3493 /* reset pointers after pullup */ 3494 ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3495 } 3496 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3497 3498 /* XXX-BZ this will go badly in case of ext hdrs. */ 3499 pi->ipi_ipproto = ip6->ip6_nxt; 3500 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3501 pi->ipi_flags |= IPI_TX_IPV6; 3502 3503 /* TCP checksum offload may require TCP header length */ 3504 if (IS_TX_OFFLOAD6(pi)) { 3505 if (pi->ipi_ipproto == IPPROTO_TCP) { 3506 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3507 txq->ift_pullups++; 3508 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3509 return (ENOMEM); 3510 /* reset pointers after pullup */ 3511 ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3512 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3513 } 3514 pi->ipi_tcp_hflags = tcp_get_flags(th); 3515 pi->ipi_tcp_hlen = th->th_off << 2; 3516 pi->ipi_tcp_seq = th->th_seq; 3517 } 3518 if (IS_TSO6(pi)) { 3519 MPASS(ip6->ip6_nxt == IPPROTO_TCP); 3520 /* 3521 * TSO always requires hardware checksum offload. 3522 */ 3523 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3524 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3525 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3526 } 3527 } 3528 break; 3529 } 3530 #endif 3531 default: 3532 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3533 pi->ipi_ip_hlen = 0; 3534 break; 3535 } 3536 *mp = m; 3537 3538 return (0); 3539 } 3540 3541 /* 3542 * If dodgy hardware rejects the scatter gather chain we've handed it 3543 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3544 * m_defrag'd mbufs 3545 */ 3546 static __noinline struct mbuf * 3547 iflib_remove_mbuf(iflib_txq_t txq) 3548 { 3549 int ntxd, pidx; 3550 struct mbuf *m, **ifsd_m; 3551 3552 ifsd_m = txq->ift_sds.ifsd_m; 3553 ntxd = txq->ift_size; 3554 pidx = txq->ift_pidx & (ntxd - 1); 3555 ifsd_m = txq->ift_sds.ifsd_m; 3556 m = IFLIB_GET_MBUF(ifsd_m[pidx]); 3557 ifsd_m[pidx] = NULL; 3558 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3559 if (txq->ift_sds.ifsd_tso_map != NULL) 3560 bus_dmamap_unload(txq->ift_tso_buf_tag, 3561 txq->ift_sds.ifsd_tso_map[pidx]); 3562 #if MEMORY_LOGGING 3563 txq->ift_dequeued++; 3564 #endif 3565 return (m); 3566 } 3567 3568 /* 3569 * Pad an mbuf to ensure a minimum ethernet frame size. 3570 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3571 */ 3572 static __noinline int 3573 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3574 { 3575 /* 3576 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3577 * and ARP message is the smallest common payload I can think of 3578 */ 3579 static char pad[18]; /* just zeros */ 3580 int n; 3581 struct mbuf *new_head; 3582 3583 if (!M_WRITABLE(*m_head)) { 3584 new_head = m_dup(*m_head, M_NOWAIT); 3585 m_freem(*m_head); 3586 *m_head = new_head; 3587 if (new_head == NULL) { 3588 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3589 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3590 DBG_COUNTER_INC(tx_frees); 3591 return (ENOMEM); 3592 } 3593 } 3594 3595 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3596 n > 0; n -= sizeof(pad)) 3597 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3598 break; 3599 3600 if (n > 0) { 3601 m_freem(*m_head); 3602 *m_head = NULL; 3603 device_printf(dev, "cannot pad short frame\n"); 3604 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3605 DBG_COUNTER_INC(tx_frees); 3606 return (ENOMEM); 3607 } 3608 3609 return (0); 3610 } 3611 3612 static int 3613 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp, int *obytes, int *opkts) 3614 { 3615 if_ctx_t ctx; 3616 if_shared_ctx_t sctx; 3617 if_softc_ctx_t scctx; 3618 bus_dma_tag_t buf_tag; 3619 bus_dma_segment_t *segs; 3620 struct mbuf *m_head, **ifsd_m; 3621 bus_dmamap_t map; 3622 struct if_pkt_info pi; 3623 uintptr_t flags; 3624 int remap = 0; 3625 int err, nsegs, ndesc, max_segs, pidx; 3626 3627 ctx = txq->ift_ctx; 3628 sctx = ctx->ifc_sctx; 3629 scctx = &ctx->ifc_softc_ctx; 3630 segs = txq->ift_segs; 3631 m_head = *m_headp; 3632 map = NULL; 3633 3634 /* 3635 * If we're doing TSO the next descriptor to clean may be quite far ahead 3636 */ 3637 pidx = txq->ift_pidx; 3638 map = txq->ift_sds.ifsd_map[pidx]; 3639 ifsd_m = txq->ift_sds.ifsd_m; 3640 3641 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3642 buf_tag = txq->ift_tso_buf_tag; 3643 max_segs = scctx->isc_tx_tso_segments_max; 3644 map = txq->ift_sds.ifsd_tso_map[pidx]; 3645 MPASS(buf_tag != NULL); 3646 MPASS(max_segs > 0); 3647 flags = IFLIB_TSO; 3648 } else { 3649 buf_tag = txq->ift_buf_tag; 3650 max_segs = scctx->isc_tx_nsegments; 3651 map = txq->ift_sds.ifsd_map[pidx]; 3652 flags = IFLIB_NO_TSO; 3653 } 3654 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3655 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3656 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3657 if (err) { 3658 DBG_COUNTER_INC(encap_txd_encap_fail); 3659 return (err); 3660 } 3661 } 3662 m_head = *m_headp; 3663 3664 memset(&pi, 0, sizeof(pi)); 3665 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG | M_BCAST | M_MCAST)); 3666 pi.ipi_pidx = pidx; 3667 pi.ipi_qsidx = txq->ift_id; 3668 pi.ipi_len = m_head->m_pkthdr.len; 3669 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3670 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3671 3672 /* deliberate bitwise OR to make one condition */ 3673 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3674 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3675 DBG_COUNTER_INC(encap_txd_encap_fail); 3676 return (err); 3677 } 3678 m_head = *m_headp; 3679 } 3680 3681 retry: 3682 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3683 BUS_DMA_NOWAIT); 3684 defrag: 3685 if (__predict_false(err)) { 3686 switch (err) { 3687 case EFBIG: 3688 /* try collapse once and defrag once */ 3689 if (remap == 0) { 3690 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3691 /* try defrag if collapsing fails */ 3692 if (m_head == NULL) 3693 remap++; 3694 } 3695 if (remap == 1) { 3696 txq->ift_mbuf_defrag++; 3697 m_head = m_defrag(*m_headp, M_NOWAIT); 3698 } 3699 /* 3700 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3701 * failed to map an mbuf that was run through m_defrag 3702 */ 3703 MPASS(remap <= 1); 3704 if (__predict_false(m_head == NULL || remap > 1)) 3705 goto defrag_failed; 3706 remap++; 3707 *m_headp = m_head; 3708 goto retry; 3709 break; 3710 case ENOMEM: 3711 /* FALLTHROUGH */ 3712 default: 3713 txq->ift_no_tx_dma_setup++; 3714 m_freem(*m_headp); 3715 DBG_COUNTER_INC(tx_frees); 3716 *m_headp = NULL; 3717 break; 3718 } 3719 txq->ift_map_failed++; 3720 DBG_COUNTER_INC(encap_load_mbuf_fail); 3721 DBG_COUNTER_INC(encap_txd_encap_fail); 3722 return (err); 3723 } 3724 ifsd_m[pidx] = IFLIB_SAVE_MBUF(m_head, flags); 3725 if (m_head->m_pkthdr.csum_flags & CSUM_SND_TAG) 3726 pi.ipi_mbuf = m_head; 3727 else 3728 pi.ipi_mbuf = NULL; 3729 /* 3730 * XXX assumes a 1 to 1 relationship between segments and 3731 * descriptors - this does not hold true on all drivers, e.g. 3732 * cxgb 3733 */ 3734 if (__predict_false(nsegs > TXQ_AVAIL(txq))) { 3735 iflib_completed_tx_reclaim_force(txq); 3736 if (__predict_false(nsegs > TXQ_AVAIL(txq))) { 3737 txq->ift_no_desc_avail++; 3738 bus_dmamap_unload(buf_tag, map); 3739 DBG_COUNTER_INC(encap_txq_avail_fail); 3740 DBG_COUNTER_INC(encap_txd_encap_fail); 3741 if (ctx->ifc_sysctl_simple_tx) { 3742 *m_headp = m_head = iflib_remove_mbuf(txq); 3743 m_freem(*m_headp); 3744 DBG_COUNTER_INC(tx_frees); 3745 *m_headp = NULL; 3746 } 3747 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3748 GROUPTASK_ENQUEUE(&txq->ift_task); 3749 return (ENOBUFS); 3750 } 3751 } 3752 /* 3753 * On Intel cards we can greatly reduce the number of TX interrupts 3754 * we see by only setting report status on every Nth descriptor. 3755 * However, this also means that the driver will need to keep track 3756 * of the descriptors that RS was set on to check them for the DD bit. 3757 */ 3758 if (txq->ift_rs_pending + nsegs + 1 > TXQ_MAX_RS_DEFERRED(txq) || 3759 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx)) { 3760 pi.ipi_flags |= IPI_TX_INTR; 3761 } 3762 3763 pi.ipi_segs = segs; 3764 pi.ipi_nsegs = nsegs; 3765 3766 MPASS(pidx >= 0 && pidx < txq->ift_size); 3767 #ifdef PKT_DEBUG 3768 print_pkt(&pi); 3769 #endif 3770 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3771 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3772 DBG_COUNTER_INC(tx_encap); 3773 MPASS(pi.ipi_new_pidx < txq->ift_size); 3774 3775 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3776 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3777 ndesc += txq->ift_size; 3778 txq->ift_gen = 1; 3779 } 3780 3781 if (pi.ipi_flags & IPI_TX_INTR) 3782 txq->ift_rs_pending = 0; 3783 else 3784 txq->ift_rs_pending += ndesc; 3785 /* 3786 * drivers can need up to ift_pad sentinels 3787 */ 3788 MPASS(ndesc <= pi.ipi_nsegs + txq->ift_pad); 3789 MPASS(pi.ipi_new_pidx != pidx); 3790 MPASS(ndesc > 0); 3791 txq->ift_in_use += ndesc; 3792 txq->ift_db_pending += ndesc; 3793 3794 /* 3795 * We update the last software descriptor again here because there may 3796 * be a sentinel and/or there may be more mbufs than segments 3797 */ 3798 txq->ift_pidx = pi.ipi_new_pidx; 3799 txq->ift_npending += pi.ipi_ndescs; 3800 3801 /* 3802 * Update packets / bytes sent 3803 */ 3804 if (flags & IFLIB_TSO) { 3805 int hlen = pi.ipi_ehdrlen + pi.ipi_ip_hlen + pi.ipi_tcp_hlen; 3806 int tsolen = pi.ipi_len - hlen; 3807 int nsegs = (tsolen + pi.ipi_tso_segsz - 1) / pi.ipi_tso_segsz; 3808 *obytes += tsolen + nsegs * hlen; 3809 *opkts += nsegs; 3810 } else { 3811 *obytes += pi.ipi_len; 3812 *opkts += 1; 3813 } 3814 } else { 3815 *m_headp = m_head = iflib_remove_mbuf(txq); 3816 if (err == EFBIG) { 3817 txq->ift_txd_encap_efbig++; 3818 if (remap < 2) { 3819 remap = 1; 3820 goto defrag; 3821 } 3822 goto defrag_failed; 3823 } 3824 /* mp_ring assumes ENOBUFS means we didn't consume the mbuf */ 3825 if (err == ENOBUFS && !ctx->ifc_sysctl_simple_tx) 3826 err = ENOMEM; 3827 goto out_with_error; 3828 } 3829 /* 3830 * err can't possibly be non-zero here, so we don't neet to test it 3831 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3832 */ 3833 return (err); 3834 3835 defrag_failed: 3836 err = ENOMEM; 3837 txq->ift_mbuf_defrag_failed++; 3838 out_with_error: 3839 txq->ift_map_failed++; 3840 m_freem(*m_headp); 3841 DBG_COUNTER_INC(tx_frees); 3842 *m_headp = NULL; 3843 DBG_COUNTER_INC(encap_txd_encap_fail); 3844 return (err); 3845 } 3846 3847 static void 3848 iflib_tx_desc_free(iflib_txq_t txq, int n, struct mbuf **m_defer) 3849 { 3850 uint32_t qsize, cidx, gen; 3851 struct mbuf *m, **ifsd_m; 3852 uintptr_t flags; 3853 3854 cidx = txq->ift_cidx; 3855 gen = txq->ift_gen; 3856 qsize = txq->ift_size; 3857 ifsd_m =txq->ift_sds.ifsd_m; 3858 3859 while (n-- > 0) { 3860 if ((m = IFLIB_GET_MBUF(ifsd_m[cidx])) != NULL) { 3861 flags = IFLIB_GET_FLAGS(ifsd_m[cidx]); 3862 MPASS(flags != 0); 3863 if (flags & IFLIB_TSO) { 3864 bus_dmamap_sync(txq->ift_tso_buf_tag, 3865 txq->ift_sds.ifsd_tso_map[cidx], 3866 BUS_DMASYNC_POSTWRITE); 3867 bus_dmamap_unload(txq->ift_tso_buf_tag, 3868 txq->ift_sds.ifsd_tso_map[cidx]); 3869 } else { 3870 bus_dmamap_sync(txq->ift_buf_tag, 3871 txq->ift_sds.ifsd_map[cidx], 3872 BUS_DMASYNC_POSTWRITE); 3873 bus_dmamap_unload(txq->ift_buf_tag, 3874 txq->ift_sds.ifsd_map[cidx]); 3875 } 3876 /* XXX we don't support any drivers that batch packets yet */ 3877 MPASS(m->m_nextpkt == NULL); 3878 if (m_defer == NULL) { 3879 m_freem(m); 3880 } else if (m != NULL) { 3881 *m_defer = m; 3882 m_defer++; 3883 } 3884 ifsd_m[cidx] = NULL; 3885 #if MEMORY_LOGGING 3886 txq->ift_dequeued++; 3887 #endif 3888 DBG_COUNTER_INC(tx_frees); 3889 } 3890 if (__predict_false(++cidx == qsize)) { 3891 cidx = 0; 3892 gen = 0; 3893 } 3894 } 3895 txq->ift_cidx = cidx; 3896 txq->ift_gen = gen; 3897 } 3898 3899 static __inline int 3900 iflib_txq_can_reclaim(iflib_txq_t txq) 3901 { 3902 int reclaim, thresh; 3903 3904 thresh = txq->ift_reclaim_thresh; 3905 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3906 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3907 3908 if (ticks <= (txq->ift_last_reclaim + txq->ift_reclaim_ticks) && 3909 txq->ift_in_use < thresh) 3910 return (false); 3911 iflib_tx_credits_update(txq->ift_ctx, txq); 3912 reclaim = DESC_RECLAIMABLE(txq); 3913 if (reclaim <= thresh) { 3914 #ifdef INVARIANTS 3915 if (iflib_verbose_debug) { 3916 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __func__, 3917 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3918 reclaim, thresh); 3919 } 3920 #endif 3921 return (0); 3922 } 3923 return (reclaim); 3924 } 3925 3926 static __inline void 3927 _iflib_completed_tx_reclaim(iflib_txq_t txq, struct mbuf **m_defer, int reclaim) 3928 { 3929 txq->ift_last_reclaim = ticks; 3930 iflib_tx_desc_free(txq, reclaim, m_defer); 3931 txq->ift_cleaned += reclaim; 3932 txq->ift_in_use -= reclaim; 3933 } 3934 3935 static __inline int 3936 iflib_completed_tx_reclaim(iflib_txq_t txq, struct mbuf **m_defer) 3937 { 3938 int reclaim; 3939 3940 reclaim = iflib_txq_can_reclaim(txq); 3941 if (reclaim == 0) 3942 return (0); 3943 _iflib_completed_tx_reclaim(txq, m_defer, reclaim); 3944 return (reclaim); 3945 } 3946 3947 /* 3948 * Reclaim any transmit descriptors possible, ignoring coalescing 3949 */ 3950 static __inline void 3951 iflib_completed_tx_reclaim_force(iflib_txq_t txq) 3952 { 3953 int reclaim; 3954 3955 iflib_tx_credits_update(txq->ift_ctx, txq); 3956 reclaim = DESC_RECLAIMABLE(txq); 3957 if (reclaim != 0) 3958 _iflib_completed_tx_reclaim(txq, NULL, reclaim); 3959 } 3960 3961 static struct mbuf ** 3962 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3963 { 3964 int next, size; 3965 struct mbuf **items; 3966 3967 size = r->size; 3968 next = (cidx + CACHE_PTR_INCREMENT) & (size - 1); 3969 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3970 3971 prefetch(items[(cidx + offset) & (size - 1)]); 3972 if (remaining > 1) { 3973 prefetch2cachelines(&items[next]); 3974 prefetch2cachelines(items[(cidx + offset + 1) & (size - 1)]); 3975 prefetch2cachelines(items[(cidx + offset + 2) & (size - 1)]); 3976 prefetch2cachelines(items[(cidx + offset + 3) & (size - 1)]); 3977 } 3978 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size - 1)])); 3979 } 3980 3981 static void 3982 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3983 { 3984 3985 ifmp_ring_check_drainage(txq->ift_br, budget); 3986 } 3987 3988 static uint32_t 3989 iflib_txq_can_drain(struct ifmp_ring *r) 3990 { 3991 iflib_txq_t txq = r->cookie; 3992 if_ctx_t ctx = txq->ift_ctx; 3993 3994 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx)) 3995 return (1); 3996 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3997 BUS_DMASYNC_POSTREAD); 3998 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3999 false)); 4000 } 4001 4002 static uint32_t 4003 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 4004 { 4005 iflib_txq_t txq = r->cookie; 4006 if_ctx_t ctx = txq->ift_ctx; 4007 if_t ifp = ctx->ifc_ifp; 4008 struct mbuf *m, **mp; 4009 int avail, bytes_sent, consumed, count, err, i; 4010 int mcast_sent, pkt_sent, reclaimed; 4011 bool do_prefetch, rang, ring; 4012 4013 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 4014 !LINK_ACTIVE(ctx))) { 4015 DBG_COUNTER_INC(txq_drain_notready); 4016 return (0); 4017 } 4018 reclaimed = iflib_completed_tx_reclaim(txq, NULL); 4019 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending); 4020 avail = IDXDIFF(pidx, cidx, r->size); 4021 4022 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 4023 /* 4024 * The driver is unloading so we need to free all pending packets. 4025 */ 4026 DBG_COUNTER_INC(txq_drain_flushing); 4027 for (i = 0; i < avail; i++) { 4028 if (__predict_true(r->items[(cidx + i) & (r->size - 1)] != (void *)txq)) 4029 m_freem(r->items[(cidx + i) & (r->size - 1)]); 4030 r->items[(cidx + i) & (r->size - 1)] = NULL; 4031 } 4032 return (avail); 4033 } 4034 4035 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 4036 CALLOUT_LOCK(txq); 4037 callout_stop(&txq->ift_timer); 4038 CALLOUT_UNLOCK(txq); 4039 DBG_COUNTER_INC(txq_drain_oactive); 4040 return (0); 4041 } 4042 4043 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 4044 count = MIN(avail, TX_BATCH_SIZE); 4045 #ifdef INVARIANTS 4046 if (iflib_verbose_debug) 4047 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __func__, 4048 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 4049 #endif 4050 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 4051 err = 0; 4052 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx); i++) { 4053 int rem = do_prefetch ? count - i : 0; 4054 4055 mp = _ring_peek_one(r, cidx, i, rem); 4056 MPASS(mp != NULL && *mp != NULL); 4057 4058 /* 4059 * Completion interrupts will use the address of the txq 4060 * as a sentinel to enqueue _something_ in order to acquire 4061 * the lock on the mp_ring (there's no direct lock call). 4062 * We obviously whave to check for these sentinel cases 4063 * and skip them. 4064 */ 4065 if (__predict_false(*mp == (struct mbuf *)txq)) { 4066 consumed++; 4067 continue; 4068 } 4069 err = iflib_encap(txq, mp, &bytes_sent, &pkt_sent); 4070 if (__predict_false(err)) { 4071 /* no room - bail out */ 4072 if (err == ENOBUFS) 4073 break; 4074 consumed++; 4075 /* we can't send this packet - skip it */ 4076 continue; 4077 } 4078 consumed++; 4079 m = *mp; 4080 DBG_COUNTER_INC(tx_sent); 4081 mcast_sent += !!(m->m_flags & M_MCAST); 4082 4083 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))) 4084 break; 4085 ETHER_BPF_MTAP(ifp, m); 4086 rang = iflib_txd_db_check(txq, false); 4087 } 4088 4089 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 4090 ring = rang ? false : (iflib_min_tx_latency | err | (!!txq->ift_reclaim_thresh)); 4091 iflib_txd_db_check(txq, ring); 4092 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 4093 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 4094 if (mcast_sent) 4095 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 4096 #ifdef INVARIANTS 4097 if (iflib_verbose_debug) 4098 printf("consumed=%d\n", consumed); 4099 #endif 4100 return (consumed); 4101 } 4102 4103 static uint32_t 4104 iflib_txq_drain_always(struct ifmp_ring *r) 4105 { 4106 return (1); 4107 } 4108 4109 static uint32_t 4110 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 4111 { 4112 int i, avail; 4113 struct mbuf **mp; 4114 iflib_txq_t txq; 4115 4116 txq = r->cookie; 4117 4118 CALLOUT_LOCK(txq); 4119 callout_stop(&txq->ift_timer); 4120 CALLOUT_UNLOCK(txq); 4121 4122 avail = IDXDIFF(pidx, cidx, r->size); 4123 for (i = 0; i < avail; i++) { 4124 mp = _ring_peek_one(r, cidx, i, avail - i); 4125 if (__predict_false(*mp == (struct mbuf *)txq)) 4126 continue; 4127 m_freem(*mp); 4128 DBG_COUNTER_INC(tx_frees); 4129 } 4130 MPASS(ifmp_ring_is_stalled(r) == 0); 4131 return (avail); 4132 } 4133 4134 static void 4135 iflib_ifmp_purge(iflib_txq_t txq) 4136 { 4137 struct ifmp_ring *r; 4138 4139 r = txq->ift_br; 4140 r->drain = iflib_txq_drain_free; 4141 r->can_drain = iflib_txq_drain_always; 4142 4143 ifmp_ring_check_drainage(r, r->size); 4144 4145 r->drain = iflib_txq_drain; 4146 r->can_drain = iflib_txq_can_drain; 4147 } 4148 4149 static void 4150 _task_fn_tx(void *context) 4151 { 4152 iflib_txq_t txq = context; 4153 if_ctx_t ctx = txq->ift_ctx; 4154 if_t ifp = ctx->ifc_ifp; 4155 int abdicate = ctx->ifc_sysctl_tx_abdicate; 4156 4157 #ifdef IFLIB_DIAGNOSTICS 4158 txq->ift_cpu_exec_count[curcpu]++; 4159 #endif 4160 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4161 return; 4162 #ifdef DEV_NETMAP 4163 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 4164 netmap_tx_irq(ifp, txq->ift_id)) 4165 goto skip_ifmp; 4166 #endif 4167 if (ctx->ifc_sysctl_simple_tx) { 4168 mtx_lock(&txq->ift_mtx); 4169 (void)iflib_completed_tx_reclaim(txq, NULL); 4170 mtx_unlock(&txq->ift_mtx); 4171 goto skip_ifmp; 4172 } 4173 #ifdef ALTQ 4174 if (if_altq_is_enabled(ifp)) 4175 iflib_altq_if_start(ifp); 4176 #endif 4177 if (txq->ift_db_pending) 4178 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 4179 else if (!abdicate) 4180 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4181 /* 4182 * When abdicating, we always need to check drainage, not just when we don't enqueue 4183 */ 4184 if (abdicate) 4185 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4186 4187 skip_ifmp: 4188 if (ctx->ifc_flags & IFC_LEGACY) 4189 IFDI_INTR_ENABLE(ctx); 4190 else 4191 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 4192 } 4193 4194 static void 4195 _task_fn_rx(void *context) 4196 { 4197 iflib_rxq_t rxq = context; 4198 if_ctx_t ctx = rxq->ifr_ctx; 4199 uint8_t more; 4200 uint16_t budget; 4201 #ifdef DEV_NETMAP 4202 u_int work = 0; 4203 int nmirq; 4204 #endif 4205 4206 #ifdef IFLIB_DIAGNOSTICS 4207 rxq->ifr_cpu_exec_count[curcpu]++; 4208 #endif 4209 DBG_COUNTER_INC(task_fn_rxs); 4210 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4211 return; 4212 #ifdef DEV_NETMAP 4213 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 4214 if (nmirq != NM_IRQ_PASS) { 4215 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 4216 goto skip_rxeof; 4217 } 4218 #endif 4219 budget = ctx->ifc_sysctl_rx_budget; 4220 if (budget == 0) 4221 budget = 16; /* XXX */ 4222 more = iflib_rxeof(rxq, budget); 4223 #ifdef DEV_NETMAP 4224 skip_rxeof: 4225 #endif 4226 if ((more & IFLIB_RXEOF_MORE) == 0) { 4227 if (ctx->ifc_flags & IFC_LEGACY) 4228 IFDI_INTR_ENABLE(ctx); 4229 else 4230 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 4231 DBG_COUNTER_INC(rx_intr_enables); 4232 } 4233 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4234 return; 4235 4236 if (more & IFLIB_RXEOF_MORE) 4237 GROUPTASK_ENQUEUE(&rxq->ifr_task); 4238 else if (more & IFLIB_RXEOF_EMPTY) 4239 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 4240 } 4241 4242 static void 4243 _task_fn_admin(void *context, int pending) 4244 { 4245 if_ctx_t ctx = context; 4246 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 4247 iflib_txq_t txq; 4248 int i; 4249 bool oactive, running, do_reset, do_reset_if_up, do_watchdog; 4250 bool in_detach; 4251 4252 STATE_LOCK(ctx); 4253 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 4254 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 4255 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 4256 do_reset_if_up = (ctx->ifc_flags & IFC_DO_RESET_IF_UP); 4257 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 4258 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 4259 ctx->ifc_flags &= ~(IFC_DO_RESET | IFC_DO_RESET_IF_UP | 4260 IFC_DO_WATCHDOG); 4261 STATE_UNLOCK(ctx); 4262 4263 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4264 return; 4265 if (in_detach) 4266 return; 4267 KFAIL_POINT_CODE_COND(_debug_fail_point_iflib, 4268 admin_task_after_detach_check, 4269 iflib_admin_task_fail_device[0] != '\0' && 4270 strcmp(device_get_nameunit(ctx->ifc_dev), 4271 iflib_admin_task_fail_device) == 0, FAIL_POINT_NONSLEEPABLE, {}); 4272 4273 CTX_LOCK(ctx); 4274 if (!do_reset && do_reset_if_up && 4275 (if_getflags(ctx->ifc_ifp) & IFF_UP) != 0) 4276 do_reset = true; 4277 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4278 CALLOUT_LOCK(txq); 4279 callout_stop(&txq->ift_timer); 4280 CALLOUT_UNLOCK(txq); 4281 } 4282 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ) 4283 IFDI_ADMIN_COMPLETION_HANDLE(ctx); 4284 if (do_watchdog) { 4285 ctx->ifc_tx_watchdog_events++; 4286 IFDI_WATCHDOG_RESET(ctx); 4287 } 4288 IFDI_UPDATE_ADMIN_STATUS(ctx); 4289 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4290 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 4291 txq->ift_timer.c_cpu); 4292 } 4293 IFDI_LINK_INTR_ENABLE(ctx); 4294 if (do_reset) 4295 iflib_if_init_locked(ctx); 4296 CTX_UNLOCK(ctx); 4297 4298 if (LINK_ACTIVE(ctx) == 0) 4299 return; 4300 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 4301 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4302 } 4303 4304 static void 4305 _task_fn_iov(void *context, int pending) 4306 { 4307 if_ctx_t ctx = context; 4308 4309 if (iflib_in_detach(ctx)) 4310 return; 4311 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 4312 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4313 return; 4314 4315 CTX_LOCK(ctx); 4316 IFDI_VFLR_HANDLE(ctx); 4317 CTX_UNLOCK(ctx); 4318 } 4319 4320 static int 4321 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4322 { 4323 int err; 4324 if_int_delay_info_t info; 4325 if_ctx_t ctx; 4326 4327 info = (if_int_delay_info_t)arg1; 4328 ctx = info->iidi_ctx; 4329 info->iidi_req = req; 4330 info->iidi_oidp = oidp; 4331 CTX_LOCK(ctx); 4332 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 4333 CTX_UNLOCK(ctx); 4334 return (err); 4335 } 4336 4337 /********************************************************************* 4338 * 4339 * IFNET FUNCTIONS 4340 * 4341 **********************************************************************/ 4342 4343 static void 4344 iflib_if_init_locked(if_ctx_t ctx) 4345 { 4346 iflib_stop(ctx); 4347 iflib_init_locked(ctx); 4348 } 4349 4350 static void 4351 iflib_if_init(void *arg) 4352 { 4353 if_ctx_t ctx = arg; 4354 4355 CTX_LOCK(ctx); 4356 iflib_if_init_locked(ctx); 4357 CTX_UNLOCK(ctx); 4358 } 4359 4360 static int 4361 iflib_if_transmit(if_t ifp, struct mbuf *m) 4362 { 4363 if_ctx_t ctx = if_getsoftc(ifp); 4364 iflib_txq_t txq; 4365 int err, qidx; 4366 int abdicate; 4367 4368 if (__predict_false((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 4369 DBG_COUNTER_INC(tx_frees); 4370 m_freem(m); 4371 return (ENETDOWN); 4372 } 4373 4374 MPASS(m->m_nextpkt == NULL); 4375 /* ALTQ-enabled interfaces always use queue 0. */ 4376 qidx = 0; 4377 /* Use driver-supplied queue selection method if it exists */ 4378 if (ctx->isc_txq_select_v2) { 4379 struct if_pkt_info pi; 4380 uint64_t early_pullups = 0; 4381 memset(&pi, 0, sizeof(pi)); 4382 4383 err = iflib_parse_header_partial(&pi, &m, &early_pullups); 4384 if (__predict_false(err != 0)) { 4385 /* Assign pullups for bad pkts to default queue */ 4386 ctx->ifc_txqs[0].ift_pullups += early_pullups; 4387 DBG_COUNTER_INC(encap_txd_encap_fail); 4388 return (err); 4389 } 4390 /* Let driver make queueing decision */ 4391 qidx = ctx->isc_txq_select_v2(ctx->ifc_softc, m, &pi); 4392 ctx->ifc_txqs[qidx].ift_pullups += early_pullups; 4393 } 4394 /* Backwards compatibility w/ simpler queue select */ 4395 else if (ctx->isc_txq_select) 4396 qidx = ctx->isc_txq_select(ctx->ifc_softc, m); 4397 /* If not, use iflib's standard method */ 4398 else if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !if_altq_is_enabled(ifp)) 4399 qidx = QIDX(ctx, m); 4400 4401 /* Set TX queue */ 4402 txq = &ctx->ifc_txqs[qidx]; 4403 4404 #ifdef DRIVER_BACKPRESSURE 4405 if (txq->ift_closed) { 4406 while (m != NULL) { 4407 next = m->m_nextpkt; 4408 m->m_nextpkt = NULL; 4409 m_freem(m); 4410 DBG_COUNTER_INC(tx_frees); 4411 m = next; 4412 } 4413 return (ENOBUFS); 4414 } 4415 #endif 4416 #ifdef notyet 4417 qidx = count = 0; 4418 mp = marr; 4419 next = m; 4420 do { 4421 count++; 4422 next = next->m_nextpkt; 4423 } while (next != NULL); 4424 4425 if (count > nitems(marr)) 4426 if ((mp = malloc(count * sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4427 /* XXX check nextpkt */ 4428 m_freem(m); 4429 /* XXX simplify for now */ 4430 DBG_COUNTER_INC(tx_frees); 4431 return (ENOBUFS); 4432 } 4433 for (next = m, i = 0; next != NULL; i++) { 4434 mp[i] = next; 4435 next = next->m_nextpkt; 4436 mp[i]->m_nextpkt = NULL; 4437 } 4438 #endif 4439 DBG_COUNTER_INC(tx_seen); 4440 abdicate = ctx->ifc_sysctl_tx_abdicate; 4441 4442 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4443 4444 if (abdicate) 4445 GROUPTASK_ENQUEUE(&txq->ift_task); 4446 if (err) { 4447 if (!abdicate) 4448 GROUPTASK_ENQUEUE(&txq->ift_task); 4449 /* support forthcoming later */ 4450 #ifdef DRIVER_BACKPRESSURE 4451 txq->ift_closed = TRUE; 4452 #endif 4453 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4454 m_freem(m); 4455 DBG_COUNTER_INC(tx_frees); 4456 if (err == ENOBUFS) 4457 if_inc_counter(ifp, IFCOUNTER_OQDROPS, 1); 4458 else 4459 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 4460 } 4461 4462 return (err); 4463 } 4464 4465 #ifdef ALTQ 4466 /* 4467 * The overall approach to integrating iflib with ALTQ is to continue to use 4468 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4469 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4470 * is redundant/unnecessary, but doing so minimizes the amount of 4471 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4472 * redundantly queueing to an intermediate mp_ring is swamped by the 4473 * performance limitations inherent in using ALTQ. 4474 * 4475 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4476 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4477 * given interface. If ALTQ is enabled for an interface, then all 4478 * transmitted packets for that interface will be submitted to the ALTQ 4479 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4480 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4481 * update stats that the iflib machinery handles, and which is sensitve to 4482 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4483 * will be installed as the start routine for use by ALTQ facilities that 4484 * need to trigger queue drains on a scheduled basis. 4485 * 4486 */ 4487 static void 4488 iflib_altq_if_start(if_t ifp) 4489 { 4490 struct ifaltq *ifq = &ifp->if_snd; /* XXX - DRVAPI */ 4491 struct mbuf *m; 4492 4493 IFQ_LOCK(ifq); 4494 IFQ_DEQUEUE_NOLOCK(ifq, m); 4495 while (m != NULL) { 4496 iflib_if_transmit(ifp, m); 4497 IFQ_DEQUEUE_NOLOCK(ifq, m); 4498 } 4499 IFQ_UNLOCK(ifq); 4500 } 4501 4502 static int 4503 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4504 { 4505 int err; 4506 4507 if (if_altq_is_enabled(ifp)) { 4508 IFQ_ENQUEUE(&ifp->if_snd, m, err); /* XXX - DRVAPI */ 4509 if (err == 0) 4510 iflib_altq_if_start(ifp); 4511 } else 4512 err = iflib_if_transmit(ifp, m); 4513 4514 return (err); 4515 } 4516 #endif /* ALTQ */ 4517 4518 static void 4519 iflib_if_qflush(if_t ifp) 4520 { 4521 if_ctx_t ctx = if_getsoftc(ifp); 4522 iflib_txq_t txq = ctx->ifc_txqs; 4523 int i; 4524 4525 STATE_LOCK(ctx); 4526 ctx->ifc_flags |= IFC_QFLUSH; 4527 STATE_UNLOCK(ctx); 4528 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4529 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4530 iflib_txq_check_drain(txq, 0); 4531 STATE_LOCK(ctx); 4532 ctx->ifc_flags &= ~IFC_QFLUSH; 4533 STATE_UNLOCK(ctx); 4534 4535 /* 4536 * When ALTQ is enabled, this will also take care of purging the 4537 * ALTQ queue(s). 4538 */ 4539 if_qflush(ifp); 4540 } 4541 4542 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4543 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4544 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4545 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG) 4546 4547 static int 4548 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4549 { 4550 if_ctx_t ctx = if_getsoftc(ifp); 4551 struct ifreq *ifr = (struct ifreq *)data; 4552 #if defined(INET) || defined(INET6) 4553 struct ifaddr *ifa = (struct ifaddr *)data; 4554 #endif 4555 bool avoid_reset = false; 4556 int err = 0, reinit = 0, bits; 4557 4558 switch (command) { 4559 case SIOCSIFADDR: 4560 #ifdef INET 4561 if (ifa->ifa_addr->sa_family == AF_INET) 4562 avoid_reset = true; 4563 #endif 4564 #ifdef INET6 4565 if (ifa->ifa_addr->sa_family == AF_INET6) 4566 avoid_reset = true; 4567 #endif 4568 /* 4569 * Calling init results in link renegotiation, 4570 * so we avoid doing it when possible. 4571 */ 4572 if (avoid_reset) { 4573 if_setflagbits(ifp, IFF_UP, 0); 4574 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4575 reinit = 1; 4576 #ifdef INET 4577 if (!(if_getflags(ifp) & IFF_NOARP)) 4578 arp_ifinit(ifp, ifa); 4579 #endif 4580 } else 4581 err = ether_ioctl(ifp, command, data); 4582 break; 4583 case SIOCSIFMTU: 4584 CTX_LOCK(ctx); 4585 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4586 CTX_UNLOCK(ctx); 4587 break; 4588 } 4589 bits = if_getdrvflags(ifp); 4590 /* stop the driver and free any clusters before proceeding */ 4591 iflib_stop(ctx); 4592 4593 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4594 STATE_LOCK(ctx); 4595 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4596 ctx->ifc_flags |= IFC_MULTISEG; 4597 else 4598 ctx->ifc_flags &= ~IFC_MULTISEG; 4599 STATE_UNLOCK(ctx); 4600 err = if_setmtu(ifp, ifr->ifr_mtu); 4601 } 4602 iflib_init_locked(ctx); 4603 STATE_LOCK(ctx); 4604 /* Preserve the stopped state reported by iflib_init_failed(). */ 4605 if ((ctx->ifc_flags & IFC_INIT_FAILED) == 0) 4606 if_setdrvflags(ifp, bits); 4607 STATE_UNLOCK(ctx); 4608 CTX_UNLOCK(ctx); 4609 break; 4610 case SIOCSIFFLAGS: 4611 CTX_LOCK(ctx); 4612 if (if_getflags(ifp) & IFF_UP) { 4613 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4614 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4615 (IFF_PROMISC | IFF_ALLMULTI)) { 4616 CTX_UNLOCK(ctx); 4617 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4618 CTX_LOCK(ctx); 4619 } 4620 } else 4621 reinit = 1; 4622 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4623 iflib_stop(ctx); 4624 } 4625 ctx->ifc_if_flags = if_getflags(ifp); 4626 CTX_UNLOCK(ctx); 4627 break; 4628 case SIOCADDMULTI: 4629 case SIOCDELMULTI: 4630 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4631 CTX_LOCK(ctx); 4632 IFDI_INTR_DISABLE(ctx); 4633 IFDI_MULTI_SET(ctx); 4634 IFDI_INTR_ENABLE(ctx); 4635 CTX_UNLOCK(ctx); 4636 } 4637 break; 4638 case SIOCSIFMEDIA: 4639 CTX_LOCK(ctx); 4640 IFDI_MEDIA_SET(ctx); 4641 CTX_UNLOCK(ctx); 4642 /* FALLTHROUGH */ 4643 case SIOCGIFMEDIA: 4644 case SIOCGIFXMEDIA: 4645 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4646 break; 4647 case SIOCGI2C: 4648 /* FALLTHROUGH */ 4649 case SIOCGI2CPB: 4650 { 4651 struct ifi2creq i2c; 4652 if_shared_ctx_t sctx = ctx->ifc_sctx; 4653 4654 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4655 if (err != 0) 4656 break; 4657 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4658 err = EINVAL; 4659 break; 4660 } 4661 if (i2c.len > sizeof(i2c.data)) { 4662 err = EINVAL; 4663 break; 4664 } 4665 if (command == SIOCGI2C) { 4666 i2c.page = i2c.bank = 0; 4667 } else if ((sctx->isc_flags & IFLIB_I2C_PAGE_BANK) == 0) { 4668 err = EINVAL; 4669 break; 4670 } 4671 4672 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4673 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4674 sizeof(i2c)); 4675 break; 4676 } 4677 case SIOCSIFCAP: 4678 { 4679 int mask, setmask, oldmask; 4680 4681 oldmask = if_getcapenable(ifp); 4682 mask = ifr->ifr_reqcap ^ oldmask; 4683 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG; 4684 setmask = 0; 4685 #ifdef TCP_OFFLOAD 4686 setmask |= mask & (IFCAP_TOE4 | IFCAP_TOE6); 4687 #endif 4688 setmask |= (mask & IFCAP_FLAGS); 4689 setmask |= (mask & IFCAP_WOL); 4690 4691 /* 4692 * If any RX csum has changed, change all the ones that 4693 * are supported by the driver. 4694 */ 4695 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4696 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4697 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4698 } 4699 4700 /* 4701 * want to ensure that traffic has stopped before we change any of the flags 4702 */ 4703 if (setmask) { 4704 CTX_LOCK(ctx); 4705 bits = if_getdrvflags(ifp); 4706 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4707 iflib_stop(ctx); 4708 STATE_LOCK(ctx); 4709 if_togglecapenable(ifp, setmask); 4710 ctx->ifc_softc_ctx.isc_capenable ^= setmask; 4711 STATE_UNLOCK(ctx); 4712 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4713 iflib_init_locked(ctx); 4714 STATE_LOCK(ctx); 4715 if ((ctx->ifc_flags & IFC_INIT_FAILED) == 0) 4716 if_setdrvflags(ifp, bits); 4717 STATE_UNLOCK(ctx); 4718 CTX_UNLOCK(ctx); 4719 } 4720 if_vlancap(ifp); 4721 break; 4722 } 4723 case SIOCGPRIVATE_0: 4724 case SIOCSDRVSPEC: 4725 case SIOCGDRVSPEC: 4726 CTX_LOCK(ctx); 4727 err = IFDI_PRIV_IOCTL(ctx, command, data); 4728 CTX_UNLOCK(ctx); 4729 break; 4730 case SIOCGIFDOWNREASON: 4731 CTX_LOCK(ctx); 4732 err = IFDI_GET_DOWNREASON(ctx, (struct ifdownreason *)data); 4733 CTX_UNLOCK(ctx); 4734 break; 4735 default: 4736 err = ether_ioctl(ifp, command, data); 4737 break; 4738 } 4739 if (reinit) 4740 iflib_if_init(ctx); 4741 return (err); 4742 } 4743 4744 static uint64_t 4745 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4746 { 4747 if_ctx_t ctx = if_getsoftc(ifp); 4748 4749 return (IFDI_GET_COUNTER(ctx, cnt)); 4750 } 4751 4752 /********************************************************************* 4753 * 4754 * OTHER FUNCTIONS EXPORTED TO THE STACK 4755 * 4756 **********************************************************************/ 4757 4758 static void 4759 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4760 { 4761 if_ctx_t ctx = if_getsoftc(ifp); 4762 4763 if ((void *)ctx != arg) 4764 return; 4765 4766 if ((vtag == 0) || (vtag > 4095)) 4767 return; 4768 4769 if (iflib_in_detach(ctx)) 4770 return; 4771 4772 CTX_LOCK(ctx); 4773 /* Driver may need all untagged packets to be flushed */ 4774 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4775 iflib_stop(ctx); 4776 IFDI_VLAN_REGISTER(ctx, vtag); 4777 /* Re-init to load the changes, if required */ 4778 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4779 iflib_init_locked(ctx); 4780 CTX_UNLOCK(ctx); 4781 } 4782 4783 static void 4784 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4785 { 4786 if_ctx_t ctx = if_getsoftc(ifp); 4787 4788 if ((void *)ctx != arg) 4789 return; 4790 4791 if ((vtag == 0) || (vtag > 4095)) 4792 return; 4793 4794 CTX_LOCK(ctx); 4795 /* Driver may need all tagged packets to be flushed */ 4796 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4797 iflib_stop(ctx); 4798 IFDI_VLAN_UNREGISTER(ctx, vtag); 4799 /* Re-init to load the changes, if required */ 4800 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4801 iflib_init_locked(ctx); 4802 CTX_UNLOCK(ctx); 4803 } 4804 4805 static void 4806 _task_fn_led(void *context, int pending __unused) 4807 { 4808 if_ctx_t ctx = context; 4809 bool in_detach; 4810 int onoff; 4811 4812 STATE_LOCK(ctx); 4813 in_detach = (ctx->ifc_flags & IFC_IN_DETACH) != 0; 4814 onoff = ctx->ifc_led_state; 4815 STATE_UNLOCK(ctx); 4816 if (in_detach) 4817 return; 4818 4819 CTX_LOCK(ctx); 4820 IFDI_LED_FUNC(ctx, onoff); 4821 CTX_UNLOCK(ctx); 4822 } 4823 4824 static void 4825 iflib_led_func(void *arg, int onoff) 4826 { 4827 if_ctx_t ctx = arg; 4828 bool in_detach; 4829 4830 /* led(4) may invoke this callback from a non-sleepable callout. */ 4831 STATE_LOCK(ctx); 4832 ctx->ifc_led_state = onoff; 4833 in_detach = (ctx->ifc_flags & IFC_IN_DETACH) != 0; 4834 STATE_UNLOCK(ctx); 4835 if (!in_detach) 4836 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_led_task); 4837 } 4838 4839 /********************************************************************* 4840 * 4841 * BUS FUNCTION DEFINITIONS 4842 * 4843 **********************************************************************/ 4844 4845 int 4846 iflib_device_probe(device_t dev) 4847 { 4848 const pci_vendor_info_t *ent; 4849 if_shared_ctx_t sctx; 4850 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4851 uint16_t pci_vendor_id; 4852 4853 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4854 return (ENOTSUP); 4855 4856 pci_vendor_id = pci_get_vendor(dev); 4857 pci_device_id = pci_get_device(dev); 4858 pci_subvendor_id = pci_get_subvendor(dev); 4859 pci_subdevice_id = pci_get_subdevice(dev); 4860 pci_rev_id = pci_get_revid(dev); 4861 if (sctx->isc_parse_devinfo != NULL) 4862 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4863 4864 ent = sctx->isc_vendor_info; 4865 while (ent->pvi_vendor_id != 0) { 4866 if (pci_vendor_id != ent->pvi_vendor_id) { 4867 ent++; 4868 continue; 4869 } 4870 if ((pci_device_id == ent->pvi_device_id) && 4871 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4872 (ent->pvi_subvendor_id == 0)) && 4873 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4874 (ent->pvi_subdevice_id == 0)) && 4875 ((pci_rev_id == ent->pvi_rev_id) || 4876 (ent->pvi_rev_id == 0))) { 4877 device_set_desc_copy(dev, ent->pvi_name); 4878 /* this needs to be changed to zero if the bus probing code 4879 * ever stops re-probing on best match because the sctx 4880 * may have its values over written by register calls 4881 * in subsequent probes 4882 */ 4883 return (BUS_PROBE_DEFAULT); 4884 } 4885 ent++; 4886 } 4887 return (ENXIO); 4888 } 4889 4890 int 4891 iflib_device_probe_vendor(device_t dev) 4892 { 4893 int probe; 4894 4895 probe = iflib_device_probe(dev); 4896 if (probe == BUS_PROBE_DEFAULT) 4897 return (BUS_PROBE_VENDOR); 4898 else 4899 return (probe); 4900 } 4901 4902 static void 4903 iflib_reset_qvalues(if_ctx_t ctx) 4904 { 4905 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4906 if_shared_ctx_t sctx = ctx->ifc_sctx; 4907 device_t dev = ctx->ifc_dev; 4908 int i; 4909 4910 if (ctx->ifc_sysctl_ntxqs != 0) 4911 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4912 if (ctx->ifc_sysctl_nrxqs != 0) 4913 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4914 4915 for (i = 0; i < sctx->isc_ntxqs; i++) { 4916 if (ctx->ifc_sysctl_ntxds[i] != 0) 4917 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4918 else 4919 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4920 } 4921 4922 for (i = 0; i < sctx->isc_nrxqs; i++) { 4923 if (ctx->ifc_sysctl_nrxds[i] != 0) 4924 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4925 else 4926 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4927 } 4928 4929 for (i = 0; i < sctx->isc_nrxqs; i++) { 4930 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4931 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4932 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4933 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4934 } 4935 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4936 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4937 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4938 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4939 } 4940 if (!powerof2(scctx->isc_nrxd[i])) { 4941 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4942 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4943 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4944 } 4945 } 4946 4947 for (i = 0; i < sctx->isc_ntxqs; i++) { 4948 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4949 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4950 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4951 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4952 } 4953 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4954 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4955 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4956 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4957 } 4958 if (!powerof2(scctx->isc_ntxd[i])) { 4959 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4960 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4961 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4962 } 4963 } 4964 scctx->isc_tx_pad = 2; 4965 } 4966 4967 static void 4968 iflib_add_pfil(if_ctx_t ctx) 4969 { 4970 struct pfil_head *pfil; 4971 struct pfil_head_args pa; 4972 iflib_rxq_t rxq; 4973 int i; 4974 4975 pa.pa_version = PFIL_VERSION; 4976 pa.pa_flags = PFIL_IN; 4977 pa.pa_type = PFIL_TYPE_ETHERNET; 4978 pa.pa_headname = if_name(ctx->ifc_ifp); 4979 pfil = pfil_head_register(&pa); 4980 4981 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4982 rxq->pfil = pfil; 4983 } 4984 } 4985 4986 static void 4987 iflib_rem_pfil(if_ctx_t ctx) 4988 { 4989 struct pfil_head *pfil; 4990 iflib_rxq_t rxq; 4991 int i; 4992 4993 rxq = ctx->ifc_rxqs; 4994 pfil = rxq->pfil; 4995 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4996 rxq->pfil = NULL; 4997 } 4998 pfil_head_unregister(pfil); 4999 } 5000 5001 5002 /* 5003 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from 5004 * cpuid and wrapping as necessary. 5005 */ 5006 static unsigned int 5007 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n) 5008 { 5009 unsigned int first_valid; 5010 unsigned int last_valid; 5011 5012 /* cpuid should always be in the valid set */ 5013 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus)); 5014 5015 /* valid set should never be empty */ 5016 MPASS(!CPU_EMPTY(&ctx->ifc_cpus)); 5017 5018 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 5019 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 5020 n = n % CPU_COUNT(&ctx->ifc_cpus); 5021 while (n > 0) { 5022 do { 5023 cpuid++; 5024 if (cpuid > last_valid) 5025 cpuid = first_valid; 5026 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus)); 5027 n--; 5028 } 5029 5030 return (cpuid); 5031 } 5032 5033 /* 5034 * CPU mapping behaviors 5035 * --------------------- 5036 * 'separate txrx' refers to the separate_txrx sysctl 5037 * 'use logical' refers to the use_logical_cores sysctl 5038 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded 5039 * 5040 * separate use INTR 5041 * txrx logical CPUS result 5042 * ---------- --------- ------ ------------------------------------------------ 5043 * - - X RX and TX queues mapped to consecutive physical 5044 * cores with RX/TX pairs on same core and excess 5045 * of either following 5046 * - X X RX and TX queues mapped to consecutive cores 5047 * of any type with RX/TX pairs on same core and 5048 * excess of either following 5049 * X - X RX and TX queues mapped to consecutive physical 5050 * cores; all RX then all TX 5051 * X X X RX queues mapped to consecutive physical cores 5052 * first, then TX queues mapped to L2 neighbor of 5053 * the corresponding RX queue if one exists, 5054 * otherwise to consecutive physical cores 5055 * - n/a - RX and TX queues mapped to consecutive cores of 5056 * any type with RX/TX pairs on same core and excess 5057 * of either following 5058 * X n/a - RX and TX queues mapped to consecutive cores of 5059 * any type; all RX then all TX 5060 */ 5061 static unsigned int 5062 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid, 5063 bool is_tx) 5064 { 5065 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5066 unsigned int core_index; 5067 5068 if (ctx->ifc_sysctl_separate_txrx) { 5069 /* 5070 * When using separate CPUs for TX and RX, the assignment 5071 * will always be of a consecutive CPU out of the set of 5072 * context CPUs, except for the specific case where the 5073 * context CPUs are phsyical cores, the use of logical cores 5074 * has been enabled, the assignment is for TX, the TX qid 5075 * corresponds to an RX qid, and the CPU assigned to the 5076 * corresponding RX queue has an L2 neighbor. 5077 */ 5078 if (ctx->ifc_sysctl_use_logical_cores && 5079 ctx->ifc_cpus_are_physical_cores && 5080 is_tx && qid < scctx->isc_nrxqsets) { 5081 int l2_neighbor; 5082 unsigned int rx_cpuid; 5083 5084 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid); 5085 l2_neighbor = sched_find_l2_neighbor(rx_cpuid); 5086 if (l2_neighbor != -1) { 5087 return (l2_neighbor); 5088 } 5089 /* 5090 * ... else fall through to the normal 5091 * consecutive-after-RX assignment scheme. 5092 * 5093 * Note that we are assuming that all RX queue CPUs 5094 * have an L2 neighbor, or all do not. If a mixed 5095 * scenario is possible, we will have to keep track 5096 * separately of how many queues prior to this one 5097 * were not able to be assigned to an L2 neighbor. 5098 */ 5099 } 5100 if (is_tx) 5101 core_index = scctx->isc_nrxqsets + qid; 5102 else 5103 core_index = qid; 5104 } else { 5105 core_index = qid; 5106 } 5107 5108 return (cpuid_advance(ctx, base_cpuid, core_index)); 5109 } 5110 5111 static uint16_t 5112 get_ctx_core_offset(if_ctx_t ctx) 5113 { 5114 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5115 struct cpu_offset *op; 5116 cpuset_t assigned_cpus; 5117 unsigned int cores_consumed; 5118 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset; 5119 unsigned int first_valid; 5120 unsigned int last_valid; 5121 unsigned int i; 5122 5123 MPASS(!ctx->ifc_core_offset_ref); 5124 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 5125 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 5126 5127 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) { 5128 /* 5129 * Align the user-chosen base CPU ID to the next valid CPU 5130 * for this device. If the chosen base CPU ID is smaller 5131 * than the first valid CPU or larger than the last valid 5132 * CPU, we assume the user does not know what the valid 5133 * range is for this device and is thinking in terms of a 5134 * zero-based reference frame, and so we shift the given 5135 * value into the valid range (and wrap accordingly) so the 5136 * intent is translated to the proper frame of reference. 5137 * If the base CPU ID is within the valid first/last, but 5138 * does not correspond to a valid CPU, it is advanced to the 5139 * next valid CPU (wrapping if necessary). 5140 */ 5141 if (base_cpuid < first_valid || base_cpuid > last_valid) { 5142 /* shift from zero-based to first_valid-based */ 5143 base_cpuid += first_valid; 5144 /* wrap to range [first_valid, last_valid] */ 5145 base_cpuid = (base_cpuid - first_valid) % 5146 (last_valid - first_valid + 1); 5147 } 5148 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) { 5149 /* 5150 * base_cpuid is in [first_valid, last_valid], but 5151 * not a member of the valid set. In this case, 5152 * there will always be a member of the valid set 5153 * with a CPU ID that is greater than base_cpuid, 5154 * and we simply advance to it. 5155 */ 5156 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) 5157 base_cpuid++; 5158 } 5159 return (base_cpuid); 5160 } 5161 5162 /* 5163 * Determine how many cores will be consumed by performing the CPU 5164 * assignments and counting how many of the assigned CPUs correspond 5165 * to CPUs in the set of context CPUs. This is done using the CPU 5166 * ID first_valid as the base CPU ID, as the base CPU must be within 5167 * the set of context CPUs. 5168 * 5169 * Note not all assigned CPUs will be in the set of context CPUs 5170 * when separate CPUs are being allocated to TX and RX queues, 5171 * assignment to logical cores has been enabled, the set of context 5172 * CPUs contains only physical CPUs, and TX queues are mapped to L2 5173 * neighbors of CPUs that RX queues have been mapped to - in this 5174 * case we do only want to count how many CPUs in the set of context 5175 * CPUs have been consumed, as that determines the next CPU in that 5176 * set to start allocating at for the next device for which 5177 * core_offset is not set. 5178 */ 5179 CPU_ZERO(&assigned_cpus); 5180 for (i = 0; i < scctx->isc_ntxqsets; i++) 5181 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true), 5182 &assigned_cpus); 5183 for (i = 0; i < scctx->isc_nrxqsets; i++) 5184 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false), 5185 &assigned_cpus); 5186 CPU_AND(&assigned_cpus, &assigned_cpus, &ctx->ifc_cpus); 5187 cores_consumed = CPU_COUNT(&assigned_cpus); 5188 5189 mtx_lock(&cpu_offset_mtx); 5190 SLIST_FOREACH(op, &cpu_offsets, entries) { 5191 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5192 base_cpuid = op->next_cpuid; 5193 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid, 5194 cores_consumed); 5195 MPASS(op->refcount < UINT_MAX); 5196 op->refcount++; 5197 ctx->ifc_core_offset_ref = true; 5198 break; 5199 } 5200 } 5201 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) { 5202 base_cpuid = first_valid; 5203 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 5204 M_NOWAIT | M_ZERO); 5205 if (op == NULL) { 5206 device_printf(ctx->ifc_dev, 5207 "allocation for cpu offset failed.\n"); 5208 } else { 5209 op->next_cpuid = cpuid_advance(ctx, base_cpuid, 5210 cores_consumed); 5211 op->refcount = 1; 5212 CPU_COPY(&ctx->ifc_cpus, &op->set); 5213 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 5214 ctx->ifc_core_offset_ref = true; 5215 } 5216 } 5217 mtx_unlock(&cpu_offset_mtx); 5218 5219 return (base_cpuid); 5220 } 5221 5222 static void 5223 unref_ctx_core_offset(if_ctx_t ctx) 5224 { 5225 struct cpu_offset *op, *top; 5226 5227 if (!ctx->ifc_core_offset_ref) 5228 return; 5229 5230 mtx_lock(&cpu_offset_mtx); 5231 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 5232 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5233 MPASS(op->refcount > 0); 5234 op->refcount--; 5235 if (op->refcount == 0) { 5236 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 5237 free(op, M_IFLIB); 5238 } 5239 ctx->ifc_core_offset_ref = false; 5240 break; 5241 } 5242 } 5243 mtx_unlock(&cpu_offset_mtx); 5244 MPASS(!ctx->ifc_core_offset_ref); 5245 } 5246 5247 static bool 5248 iflib_register_fail_device_matches(device_t dev) 5249 { 5250 const char *nameunit; 5251 5252 nameunit = device_get_nameunit(dev); 5253 return (iflib_register_fail_device[0] != '\0' && nameunit != NULL && 5254 strcmp(nameunit, iflib_register_fail_device) == 0); 5255 } 5256 5257 #define IFLIB_REGISTER_FAIL_POINT(_dev, _name, _error, _label) do { \ 5258 KFAIL_POINT_CODE_COND(_debug_fail_point_iflib, _name, \ 5259 iflib_register_fail_device_matches((_dev)), \ 5260 FAIL_POINT_NONSLEEPABLE, { \ 5261 (_error) = RETURN_VALUE; \ 5262 if ((_error) <= 0) \ 5263 (_error) = EIO; \ 5264 device_printf((_dev), \ 5265 "injecting iflib registration failure at %s: %d\n", \ 5266 #_name, (_error)); \ 5267 goto _label; \ 5268 }); \ 5269 } while (0) 5270 5271 int 5272 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 5273 { 5274 if_ctx_t ctx; 5275 if_t ifp; 5276 if_softc_ctx_t scctx; 5277 kobjop_desc_t kobj_desc; 5278 kobj_method_t *kobj_method; 5279 bool attach_pre_succeeded, intr_allocated, queues_allocated; 5280 int err, msix, rid; 5281 #ifdef PCI_IOV 5282 int iov_error; 5283 #endif 5284 int num_txd, num_rxd; 5285 char namebuf[TASKQUEUE_NAMELEN]; 5286 5287 attach_pre_succeeded = false; 5288 intr_allocated = false; 5289 queues_allocated = false; 5290 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK | M_ZERO); 5291 5292 if (sc == NULL) { 5293 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK | M_ZERO); 5294 device_set_softc(dev, ctx); 5295 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5296 } 5297 5298 ctx->ifc_sctx = sctx; 5299 ctx->ifc_dev = dev; 5300 ctx->ifc_softc = sc; 5301 5302 iflib_register(ctx); 5303 iflib_add_device_sysctl_pre(ctx); 5304 5305 scctx = &ctx->ifc_softc_ctx; 5306 ifp = ctx->ifc_ifp; 5307 if (ctx->ifc_sysctl_simple_tx) { 5308 #ifndef ALTQ 5309 if_settransmitfn(ifp, iflib_simple_transmit); 5310 device_printf(dev, "using simple if_transmit\n"); 5311 #else 5312 device_printf(dev, "ALTQ prevents using simple if_transmit\n"); 5313 ctx->ifc_sysctl_simple_tx = 0; 5314 #endif 5315 } 5316 iflib_reset_qvalues(ctx); 5317 CTX_LOCK(ctx); 5318 IFLIB_REGISTER_FAIL_POINT(dev, register_before_attach_pre, err, 5319 fail_cleanup); 5320 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5321 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5322 goto fail_cleanup; 5323 } 5324 attach_pre_succeeded = true; 5325 IFLIB_REGISTER_FAIL_POINT(dev, register_after_attach_pre, err, 5326 fail_cleanup); 5327 _iflib_pre_assert(scctx); 5328 ctx->ifc_txrx = *scctx->isc_txrx; 5329 5330 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR)); 5331 5332 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 5333 ctx->ifc_mediap = scctx->isc_media; 5334 5335 #ifdef INVARIANTS 5336 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5337 MPASS(scctx->isc_tx_csum_flags); 5338 #endif 5339 5340 if_setcapabilities(ifp, 5341 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG); 5342 if_setcapenable(ifp, 5343 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG); 5344 5345 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5346 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5347 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5348 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5349 5350 num_txd = iflib_num_tx_descs(ctx); 5351 num_rxd = iflib_num_rx_descs(ctx); 5352 5353 /* XXX change for per-queue sizes */ 5354 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5355 num_txd, num_rxd); 5356 5357 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5358 scctx->isc_tx_nsegments = max(1, num_txd / 5359 MAX_SINGLE_PACKET_FRACTION); 5360 if (scctx->isc_tx_tso_segments_max > num_txd / 5361 MAX_SINGLE_PACKET_FRACTION) 5362 scctx->isc_tx_tso_segments_max = max(1, 5363 num_txd / MAX_SINGLE_PACKET_FRACTION); 5364 5365 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5366 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5367 /* 5368 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5369 * but some MACs do. 5370 */ 5371 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5372 IP_MAXPACKET)); 5373 /* 5374 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5375 * into account. In the worst case, each of these calls will 5376 * add another mbuf and, thus, the requirement for another DMA 5377 * segment. So for best performance, it doesn't make sense to 5378 * advertize a maximum of TSO segments that typically will 5379 * require defragmentation in iflib_encap(). 5380 */ 5381 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5382 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5383 } 5384 if (scctx->isc_rss_table_size == 0) 5385 scctx->isc_rss_table_size = 64; 5386 scctx->isc_rss_table_mask = scctx->isc_rss_table_size - 1; 5387 5388 /* Create and start admin taskqueue */ 5389 snprintf(namebuf, TASKQUEUE_NAMELEN, "if_%s_tq", device_get_nameunit(dev)); 5390 ctx->ifc_tq = taskqueue_create_fast(namebuf, M_NOWAIT, 5391 taskqueue_thread_enqueue, &ctx->ifc_tq); 5392 if (ctx->ifc_tq == NULL) { 5393 device_printf(dev, "Unable to create admin taskqueue\n"); 5394 err = ENOMEM; 5395 goto fail_cleanup; 5396 } 5397 5398 err = taskqueue_start_threads(&ctx->ifc_tq, 1, PI_NET, "%s", namebuf); 5399 if (err) { 5400 device_printf(dev, 5401 "Unable to start admin taskqueue threads error: %d\n", 5402 err); 5403 taskqueue_free(ctx->ifc_tq); 5404 ctx->ifc_tq = NULL; 5405 goto fail_cleanup; 5406 } 5407 5408 TASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5409 TASK_INIT(&ctx->ifc_led_task, 0, _task_fn_led, ctx); 5410 TASK_INIT(&ctx->ifc_vflr_task, 0, _task_fn_iov, ctx); 5411 IFLIB_REGISTER_FAIL_POINT(dev, register_after_taskqueue, err, 5412 fail_cleanup); 5413 5414 /* Set up cpu set. If it fails, use the set of all CPUs. */ 5415 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 5416 device_printf(dev, "Unable to fetch CPU list\n"); 5417 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 5418 ctx->ifc_cpus_are_physical_cores = false; 5419 } else 5420 ctx->ifc_cpus_are_physical_cores = true; 5421 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 5422 5423 /* 5424 * Now set up MSI or MSI-X, should return us the number of supported 5425 * vectors (will be 1 for a legacy interrupt and MSI). 5426 */ 5427 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 5428 msix = scctx->isc_vectors; 5429 } else if (scctx->isc_msix_bar != 0) 5430 /* 5431 * The simple fact that isc_msix_bar is not 0 does not mean we 5432 * we have a good value there that is known to work. 5433 */ 5434 msix = iflib_msix_init(ctx); 5435 else { 5436 scctx->isc_vectors = 1; 5437 scctx->isc_ntxqsets = 1; 5438 scctx->isc_nrxqsets = 1; 5439 scctx->isc_intr = IFLIB_INTR_LEGACY; 5440 msix = 0; 5441 } 5442 intr_allocated = true; 5443 IFLIB_REGISTER_FAIL_POINT(dev, register_after_interrupts, err, 5444 fail_cleanup); 5445 /* Get memory for the station queues */ 5446 if ((err = iflib_queues_alloc(ctx))) { 5447 device_printf(dev, "Unable to allocate queue memory\n"); 5448 goto fail_cleanup; 5449 } 5450 queues_allocated = true; 5451 5452 if ((err = iflib_qset_structures_setup(ctx))) 5453 goto fail_cleanup; 5454 5455 /* 5456 * Now that we know how many queues there are, get the core offset. 5457 */ 5458 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 5459 IFLIB_REGISTER_FAIL_POINT(dev, register_after_queues, err, 5460 fail_cleanup); 5461 5462 if (msix > 1) { 5463 /* 5464 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 5465 * aren't the default NULL implementation. 5466 */ 5467 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 5468 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5469 kobj_desc); 5470 if (kobj_method == &kobj_desc->deflt) { 5471 device_printf(dev, 5472 "MSI-X requires ifdi_rx_queue_intr_enable method"); 5473 err = EOPNOTSUPP; 5474 goto fail_cleanup; 5475 } 5476 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 5477 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5478 kobj_desc); 5479 if (kobj_method == &kobj_desc->deflt) { 5480 device_printf(dev, 5481 "MSI-X requires ifdi_tx_queue_intr_enable method"); 5482 err = EOPNOTSUPP; 5483 goto fail_cleanup; 5484 } 5485 5486 /* 5487 * Assign the MSI-X vectors. 5488 * Note that the default NULL ifdi_msix_intr_assign method will 5489 * fail here, too. 5490 */ 5491 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 5492 if (err != 0) { 5493 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 5494 err); 5495 goto fail_cleanup; 5496 } 5497 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 5498 rid = 0; 5499 if (scctx->isc_intr == IFLIB_INTR_MSI) { 5500 MPASS(msix == 1); 5501 rid = 1; 5502 } 5503 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 5504 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 5505 goto fail_cleanup; 5506 } 5507 } else { 5508 device_printf(dev, 5509 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 5510 err = ENODEV; 5511 goto fail_cleanup; 5512 } 5513 5514 /* 5515 * It prevents a double-locking panic with iflib_media_status when 5516 * the driver loads. 5517 */ 5518 CTX_UNLOCK(ctx); 5519 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5520 CTX_LOCK(ctx); 5521 5522 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5523 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5524 goto fail_detach; 5525 } 5526 IFLIB_REGISTER_FAIL_POINT(dev, register_after_attach_post, err, 5527 fail_detach); 5528 5529 /* 5530 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5531 * This must appear after the call to ether_ifattach() because 5532 * ether_ifattach() sets if_hdrlen to the default value. 5533 */ 5534 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5535 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5536 5537 if ((err = iflib_netmap_attach(ctx))) { 5538 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 5539 goto fail_detach; 5540 } 5541 *ctxp = ctx; 5542 5543 DEBUGNET_SET(ctx->ifc_ifp, iflib); 5544 5545 iflib_add_device_sysctl_post(ctx); 5546 iflib_add_pfil(ctx); 5547 ctx->ifc_flags |= IFC_INIT_DONE; 5548 CTX_UNLOCK(ctx); 5549 5550 /* Create led(4) devices if the driver defined the method */ 5551 kobj_desc = &ifdi_led_func_desc; 5552 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5553 kobj_desc); 5554 if (kobj_method != &kobj_desc->deflt && IFDI_LED_SUPPORTED(ctx)) 5555 iflib_led_create(ctx); 5556 5557 return (0); 5558 5559 fail_detach: 5560 STATE_LOCK(ctx); 5561 ctx->ifc_flags |= IFC_IN_DETACH; 5562 STATE_UNLOCK(ctx); 5563 /* Tasks may need the context lock; ether_ifdetach() may sleep. */ 5564 CTX_UNLOCK(ctx); 5565 taskqueue_drain_all(ctx->ifc_tq); 5566 #ifdef PCI_IOV 5567 /* 5568 * IFDI_ATTACH_POST may have registered an SR-IOV schema. Match the 5569 * normal deregistration order so a failed attach cannot leave a stale 5570 * /dev/iov node behind. device_attach() holds Giant throughout this 5571 * path, so an IOV configuration cannot race the detach. 5572 */ 5573 if (!CTX_IS_VF(ctx)) { 5574 iov_error = pci_iov_detach(dev); 5575 if (iov_error != 0) 5576 device_printf(dev, "Could not detach SR-IOV after " 5577 "attach failure: %d\n", iov_error); 5578 } 5579 #endif 5580 ether_ifdetach(ctx->ifc_ifp); 5581 CTX_LOCK(ctx); 5582 goto fail_cleanup_detaching; 5583 5584 fail_cleanup: 5585 STATE_LOCK(ctx); 5586 ctx->ifc_flags |= IFC_IN_DETACH; 5587 STATE_UNLOCK(ctx); 5588 5589 fail_cleanup_detaching: 5590 /* 5591 * The pre-attach sysctls contain pointers into ctx. Remove them on 5592 * every registration failure before iflib_deregister() frees ctx. 5593 */ 5594 if (ctx->ifc_sysctl_node != NULL) { 5595 sysctl_ctx_free(&ctx->ifc_sysctl_ctx); 5596 ctx->ifc_sysctl_node = NULL; 5597 } 5598 5599 if (ctx->ifc_tq != NULL) { 5600 /* 5601 * Drain without holding the context lock so configuration tasks can 5602 * run to completion. On fail_detach a second drain also catches 5603 * tasks queued during the first drain. 5604 */ 5605 CTX_UNLOCK(ctx); 5606 taskqueue_drain_all(ctx->ifc_tq); 5607 CTX_LOCK(ctx); 5608 } 5609 5610 if (queues_allocated) { 5611 iflib_tqg_detach(ctx); 5612 iflib_tx_structures_free(ctx); 5613 iflib_rx_structures_free(ctx); 5614 } 5615 5616 /* 5617 * A successful IFDI_ATTACH_PRE must be matched by IFDI_DETACH, even 5618 * when registration fails before queue allocation. Match 5619 * iflib_device_deregister by detaching before taskqueue_free. 5620 */ 5621 if (attach_pre_succeeded) { 5622 IFDI_DETACH(ctx); 5623 if (queues_allocated) 5624 IFDI_QUEUES_FREE(ctx); 5625 } 5626 if (ctx->ifc_tq != NULL) { 5627 taskqueue_free(ctx->ifc_tq); 5628 ctx->ifc_tq = NULL; 5629 } 5630 if (intr_allocated) 5631 iflib_free_intr_mem(ctx); 5632 5633 CTX_UNLOCK(ctx); 5634 iflib_deregister(ctx); 5635 device_set_softc(ctx->ifc_dev, NULL); 5636 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5637 free(ctx->ifc_softc, M_IFLIB); 5638 unref_ctx_core_offset(ctx); 5639 free(ctx, M_IFLIB); 5640 return (err); 5641 } 5642 5643 int 5644 iflib_device_attach(device_t dev) 5645 { 5646 if_ctx_t ctx; 5647 if_shared_ctx_t sctx; 5648 5649 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5650 return (ENOTSUP); 5651 5652 pci_enable_busmaster(dev); 5653 5654 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5655 } 5656 5657 int 5658 iflib_device_deregister(if_ctx_t ctx) 5659 { 5660 if_t ifp = ctx->ifc_ifp; 5661 device_t dev = ctx->ifc_dev; 5662 5663 sysctl_ctx_free(&ctx->ifc_sysctl_ctx); 5664 ctx->ifc_sysctl_node = NULL; 5665 5666 /* Make sure VLANS are not using driver */ 5667 if (if_vlantrunkinuse(ifp)) { 5668 device_printf(dev, "Vlan in use, detach first\n"); 5669 return (EBUSY); 5670 } 5671 #ifdef PCI_IOV 5672 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5673 device_printf(dev, "SR-IOV in use; detach first.\n"); 5674 return (EBUSY); 5675 } 5676 #endif 5677 5678 STATE_LOCK(ctx); 5679 ctx->ifc_flags |= IFC_IN_DETACH; 5680 STATE_UNLOCK(ctx); 5681 5682 /* Unregister VLAN handlers before calling iflib_stop() */ 5683 iflib_unregister_vlan_handlers(ctx); 5684 5685 iflib_netmap_detach(ifp); 5686 /* 5687 * A task that passed its IFC_IN_DETACH check before the flag was set 5688 * can still report a link change. Drain every private task before 5689 * ether_ifdetach() performs the final if_linktask drain. Drivers may 5690 * register their own link-related tasks on this taskqueue. 5691 */ 5692 taskqueue_drain_all(ctx->ifc_tq); 5693 ether_ifdetach(ifp); 5694 5695 CTX_LOCK(ctx); 5696 iflib_stop(ctx); 5697 CTX_UNLOCK(ctx); 5698 5699 iflib_rem_pfil(ctx); 5700 if (ctx->ifc_led_dev != NULL) { 5701 led_destroy(ctx->ifc_led_dev); 5702 taskqueue_drain(ctx->ifc_tq, &ctx->ifc_led_task); 5703 } 5704 5705 iflib_tqg_detach(ctx); 5706 iflib_tx_structures_free(ctx); 5707 iflib_rx_structures_free(ctx); 5708 5709 CTX_LOCK(ctx); 5710 IFDI_DETACH(ctx); 5711 IFDI_QUEUES_FREE(ctx); 5712 CTX_UNLOCK(ctx); 5713 5714 taskqueue_free(ctx->ifc_tq); 5715 ctx->ifc_tq = NULL; 5716 5717 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5718 iflib_free_intr_mem(ctx); 5719 5720 bus_generic_detach(dev); 5721 5722 iflib_deregister(ctx); 5723 5724 device_set_softc(ctx->ifc_dev, NULL); 5725 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5726 free(ctx->ifc_softc, M_IFLIB); 5727 unref_ctx_core_offset(ctx); 5728 free(ctx, M_IFLIB); 5729 return (0); 5730 } 5731 5732 static void 5733 iflib_tqg_detach(if_ctx_t ctx) 5734 { 5735 iflib_txq_t txq; 5736 iflib_rxq_t rxq; 5737 int i; 5738 struct taskqgroup *tqg; 5739 5740 /* XXX drain any dependent tasks */ 5741 tqg = qgroup_if_io_tqg; 5742 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5743 callout_drain(&txq->ift_timer); 5744 #ifdef DEV_NETMAP 5745 callout_drain(&txq->ift_netmap_timer); 5746 #endif /* DEV_NETMAP */ 5747 if (txq->ift_task.gt_uniq != NULL) 5748 taskqgroup_detach(tqg, &txq->ift_task); 5749 } 5750 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5751 if (rxq->ifr_task.gt_uniq != NULL) 5752 taskqgroup_detach(tqg, &rxq->ifr_task); 5753 } 5754 } 5755 5756 static void 5757 iflib_free_intr_mem(if_ctx_t ctx) 5758 { 5759 5760 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5761 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5762 } 5763 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5764 pci_release_msi(ctx->ifc_dev); 5765 } 5766 if (ctx->ifc_msix_mem != NULL) { 5767 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5768 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5769 ctx->ifc_msix_mem = NULL; 5770 } 5771 } 5772 5773 int 5774 iflib_device_detach(device_t dev) 5775 { 5776 if_ctx_t ctx = device_get_softc(dev); 5777 5778 return (iflib_device_deregister(ctx)); 5779 } 5780 5781 int 5782 iflib_device_suspend(device_t dev) 5783 { 5784 if_ctx_t ctx = device_get_softc(dev); 5785 5786 CTX_LOCK(ctx); 5787 IFDI_SUSPEND(ctx); 5788 CTX_UNLOCK(ctx); 5789 5790 return (bus_generic_suspend(dev)); 5791 } 5792 int 5793 iflib_device_shutdown(device_t dev) 5794 { 5795 if_ctx_t ctx = device_get_softc(dev); 5796 5797 CTX_LOCK(ctx); 5798 IFDI_SHUTDOWN(ctx); 5799 CTX_UNLOCK(ctx); 5800 5801 return (bus_generic_suspend(dev)); 5802 } 5803 5804 int 5805 iflib_device_resume(device_t dev) 5806 { 5807 if_ctx_t ctx = device_get_softc(dev); 5808 iflib_txq_t txq = ctx->ifc_txqs; 5809 5810 CTX_LOCK(ctx); 5811 IFDI_RESUME(ctx); 5812 iflib_if_init_locked(ctx); 5813 CTX_UNLOCK(ctx); 5814 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5815 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5816 5817 return (bus_generic_resume(dev)); 5818 } 5819 5820 int 5821 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5822 { 5823 int error; 5824 if_ctx_t ctx = device_get_softc(dev); 5825 5826 CTX_LOCK(ctx); 5827 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5828 CTX_UNLOCK(ctx); 5829 5830 return (error); 5831 } 5832 5833 int 5834 iflib_device_iov_init_restart(device_t dev, uint16_t num_vfs, 5835 const nvlist_t *params) 5836 { 5837 if_ctx_t ctx; 5838 if_t ifp; 5839 bool restart, running; 5840 int error; 5841 5842 ctx = device_get_softc(dev); 5843 ifp = ctx->ifc_ifp; 5844 5845 CTX_LOCK(ctx); 5846 /* 5847 * Drivers which change the PF queue layout need the complete iflib 5848 * stop/init sequence around their IOV callback when the interface is 5849 * active. An administratively-down interface has no live queues to 5850 * quiesce, and must remain down after the new layout is installed. 5851 * Keep the transition within one context-lock critical section. 5852 */ 5853 restart = (if_getflags(ifp) & IFF_UP) != 0; 5854 running = (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0; 5855 if (restart || running) 5856 iflib_stop(ctx); 5857 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5858 if (restart) 5859 iflib_init_locked(ctx); 5860 CTX_UNLOCK(ctx); 5861 return (error); 5862 } 5863 5864 void 5865 iflib_device_iov_uninit(device_t dev) 5866 { 5867 if_ctx_t ctx = device_get_softc(dev); 5868 5869 CTX_LOCK(ctx); 5870 IFDI_IOV_UNINIT(ctx); 5871 CTX_UNLOCK(ctx); 5872 } 5873 5874 void 5875 iflib_device_iov_uninit_restart(device_t dev) 5876 { 5877 if_ctx_t ctx; 5878 bool restart; 5879 5880 ctx = device_get_softc(dev); 5881 5882 CTX_LOCK(ctx); 5883 /* 5884 * RUNNING can be clear while a watchdog reset is pending but the 5885 * hardware is still live. Always stop before the driver changes its 5886 * queue layout, and use IFF_UP only to preserve administrative state. 5887 */ 5888 restart = (if_getflags(ctx->ifc_ifp) & IFF_UP) != 0; 5889 iflib_stop(ctx); 5890 IFDI_IOV_UNINIT(ctx); 5891 if (restart) 5892 iflib_init_locked(ctx); 5893 CTX_UNLOCK(ctx); 5894 } 5895 5896 int 5897 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5898 { 5899 int error; 5900 if_ctx_t ctx = device_get_softc(dev); 5901 5902 CTX_LOCK(ctx); 5903 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5904 CTX_UNLOCK(ctx); 5905 5906 return (error); 5907 } 5908 5909 /********************************************************************* 5910 * 5911 * MODULE FUNCTION DEFINITIONS 5912 * 5913 **********************************************************************/ 5914 5915 /* 5916 * - Start a fast taskqueue thread for each core 5917 * - Start a taskqueue for control operations 5918 */ 5919 static int 5920 iflib_module_init(void) 5921 { 5922 iflib_timer_default = hz / 2; 5923 return (0); 5924 } 5925 5926 static int 5927 iflib_module_event_handler(module_t mod, int what, void *arg) 5928 { 5929 int err; 5930 5931 switch (what) { 5932 case MOD_LOAD: 5933 if ((err = iflib_module_init()) != 0) 5934 return (err); 5935 break; 5936 case MOD_UNLOAD: 5937 return (EBUSY); 5938 default: 5939 return (EOPNOTSUPP); 5940 } 5941 5942 return (0); 5943 } 5944 5945 /********************************************************************* 5946 * 5947 * PUBLIC FUNCTION DEFINITIONS 5948 * ordered as in iflib.h 5949 * 5950 **********************************************************************/ 5951 5952 static void 5953 _iflib_assert(if_shared_ctx_t sctx) 5954 { 5955 int i; 5956 5957 MPASS(sctx->isc_tx_maxsize); 5958 MPASS(sctx->isc_tx_maxsegsize); 5959 5960 MPASS(sctx->isc_rx_maxsize); 5961 MPASS(sctx->isc_rx_nsegments); 5962 MPASS(sctx->isc_rx_maxsegsize); 5963 5964 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5965 for (i = 0; i < sctx->isc_nrxqs; i++) { 5966 MPASS(sctx->isc_nrxd_min[i]); 5967 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5968 MPASS(sctx->isc_nrxd_max[i]); 5969 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5970 MPASS(sctx->isc_nrxd_default[i]); 5971 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5972 } 5973 5974 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5975 for (i = 0; i < sctx->isc_ntxqs; i++) { 5976 MPASS(sctx->isc_ntxd_min[i]); 5977 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5978 MPASS(sctx->isc_ntxd_max[i]); 5979 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5980 MPASS(sctx->isc_ntxd_default[i]); 5981 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5982 } 5983 } 5984 5985 static void 5986 _iflib_pre_assert(if_softc_ctx_t scctx) 5987 { 5988 5989 MPASS(scctx->isc_txrx->ift_txd_encap); 5990 MPASS(scctx->isc_txrx->ift_txd_flush); 5991 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5992 MPASS(scctx->isc_txrx->ift_rxd_available); 5993 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5994 MPASS(scctx->isc_txrx->ift_rxd_refill); 5995 MPASS(scctx->isc_txrx->ift_rxd_flush); 5996 } 5997 5998 static void 5999 iflib_register(if_ctx_t ctx) 6000 { 6001 if_shared_ctx_t sctx = ctx->ifc_sctx; 6002 driver_t *driver = sctx->isc_driver; 6003 device_t dev = ctx->ifc_dev; 6004 if_t ifp; 6005 6006 _iflib_assert(sctx); 6007 6008 CTX_LOCK_INIT(ctx); 6009 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 6010 ifp = ctx->ifc_ifp = if_alloc_dev(IFT_ETHER, dev); 6011 6012 /* 6013 * Initialize our context's device specific methods 6014 */ 6015 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 6016 kobj_class_compile((kobj_class_t) driver); 6017 6018 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 6019 if_setsoftc(ifp, ctx); 6020 if_setdev(ifp, dev); 6021 if_setinitfn(ifp, iflib_if_init); 6022 if_setioctlfn(ifp, iflib_if_ioctl); 6023 #ifdef ALTQ 6024 if_setstartfn(ifp, iflib_altq_if_start); 6025 if_settransmitfn(ifp, iflib_altq_if_transmit); 6026 if_setsendqready(ifp); 6027 #else 6028 if_settransmitfn(ifp, iflib_if_transmit); 6029 #endif 6030 if_setqflushfn(ifp, iflib_if_qflush); 6031 if_setgetcounterfn(ifp, iflib_if_get_counter); 6032 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 6033 ctx->ifc_vlan_attach_event = 6034 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 6035 EVENTHANDLER_PRI_FIRST); 6036 ctx->ifc_vlan_detach_event = 6037 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 6038 EVENTHANDLER_PRI_FIRST); 6039 6040 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 6041 ctx->ifc_mediap = &ctx->ifc_media; 6042 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 6043 iflib_media_change, iflib_media_status); 6044 } 6045 } 6046 6047 static void 6048 iflib_unregister_vlan_handlers(if_ctx_t ctx) 6049 { 6050 /* Unregister VLAN events */ 6051 if (ctx->ifc_vlan_attach_event != NULL) { 6052 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 6053 ctx->ifc_vlan_attach_event = NULL; 6054 } 6055 if (ctx->ifc_vlan_detach_event != NULL) { 6056 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 6057 ctx->ifc_vlan_detach_event = NULL; 6058 } 6059 6060 } 6061 6062 static void 6063 iflib_deregister(if_ctx_t ctx) 6064 { 6065 if_t ifp = ctx->ifc_ifp; 6066 6067 /* Remove all media */ 6068 ifmedia_removeall(&ctx->ifc_media); 6069 6070 /* Ensure that VLAN event handlers are unregistered */ 6071 iflib_unregister_vlan_handlers(ctx); 6072 6073 /* Release kobject reference */ 6074 kobj_delete((kobj_t) ctx, NULL); 6075 6076 /* Free the ifnet structure */ 6077 if_free(ifp); 6078 6079 STATE_LOCK_DESTROY(ctx); 6080 6081 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 6082 CTX_LOCK_DESTROY(ctx); 6083 } 6084 6085 static int 6086 iflib_queues_alloc(if_ctx_t ctx) 6087 { 6088 if_shared_ctx_t sctx = ctx->ifc_sctx; 6089 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6090 device_t dev = ctx->ifc_dev; 6091 int nrxqsets = scctx->isc_nrxqsets; 6092 int ntxqsets = scctx->isc_ntxqsets; 6093 iflib_txq_t txq; 6094 iflib_rxq_t rxq; 6095 iflib_fl_t fl = NULL; 6096 int i, j, cpu, err, txconf, rxconf; 6097 iflib_dma_info_t ifdip; 6098 uint32_t *rxqsizes = scctx->isc_rxqsizes; 6099 uint32_t *txqsizes = scctx->isc_txqsizes; 6100 uint8_t nrxqs = sctx->isc_nrxqs; 6101 uint8_t ntxqs = sctx->isc_ntxqs; 6102 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 6103 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0); 6104 caddr_t *vaddrs; 6105 uint64_t *paddrs; 6106 6107 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 6108 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 6109 KASSERT(nrxqs >= fl_offset + nfree_lists, 6110 ("there must be at least a rxq for each free list")); 6111 6112 /* Allocate the TX ring struct memory */ 6113 if (!(ctx->ifc_txqs = 6114 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 6115 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 6116 device_printf(dev, "Unable to allocate TX ring memory\n"); 6117 err = ENOMEM; 6118 goto fail; 6119 } 6120 6121 /* Now allocate the RX */ 6122 if (!(ctx->ifc_rxqs = 6123 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 6124 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 6125 device_printf(dev, "Unable to allocate RX ring memory\n"); 6126 err = ENOMEM; 6127 goto rx_fail; 6128 } 6129 6130 txq = ctx->ifc_txqs; 6131 rxq = ctx->ifc_rxqs; 6132 6133 /* 6134 * XXX handle allocation failure 6135 */ 6136 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 6137 /* Set up some basics */ 6138 6139 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 6140 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 6141 device_printf(dev, 6142 "Unable to allocate TX DMA info memory\n"); 6143 err = ENOMEM; 6144 goto err_tx_desc; 6145 } 6146 txq->ift_ifdi = ifdip; 6147 for (j = 0; j < ntxqs; j++, ifdip++) { 6148 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 6149 device_printf(dev, 6150 "Unable to allocate TX descriptors\n"); 6151 err = ENOMEM; 6152 goto err_tx_desc; 6153 } 6154 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 6155 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 6156 } 6157 txq->ift_ctx = ctx; 6158 txq->ift_id = i; 6159 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 6160 txq->ift_br_offset = 1; 6161 } else { 6162 txq->ift_br_offset = 0; 6163 } 6164 6165 if (iflib_txsd_alloc(txq)) { 6166 device_printf(dev, "Critical Failure setting up TX buffers\n"); 6167 err = ENOMEM; 6168 goto err_tx_desc; 6169 } 6170 6171 /* Initialize the TX lock */ 6172 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 6173 device_get_nameunit(dev), txq->ift_id); 6174 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 6175 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 6176 txq->ift_timer.c_cpu = cpu; 6177 #ifdef DEV_NETMAP 6178 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 6179 txq->ift_netmap_timer.c_cpu = cpu; 6180 #endif /* DEV_NETMAP */ 6181 6182 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 6183 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 6184 if (err) { 6185 /* XXX free any allocated rings */ 6186 device_printf(dev, "Unable to allocate buf_ring\n"); 6187 goto err_tx_desc; 6188 } 6189 txq->ift_reclaim_thresh = ctx->ifc_sysctl_tx_reclaim_thresh; 6190 } 6191 6192 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 6193 /* Set up some basics */ 6194 callout_init(&rxq->ifr_watchdog, 1); 6195 6196 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 6197 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 6198 device_printf(dev, 6199 "Unable to allocate RX DMA info memory\n"); 6200 err = ENOMEM; 6201 goto err_tx_desc; 6202 } 6203 6204 rxq->ifr_ifdi = ifdip; 6205 /* XXX this needs to be changed if #rx queues != #tx queues */ 6206 rxq->ifr_ntxqirq = 1; 6207 rxq->ifr_txqid[0] = i; 6208 for (j = 0; j < nrxqs; j++, ifdip++) { 6209 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 6210 device_printf(dev, 6211 "Unable to allocate RX descriptors\n"); 6212 err = ENOMEM; 6213 goto err_tx_desc; 6214 } 6215 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 6216 } 6217 rxq->ifr_ctx = ctx; 6218 rxq->ifr_id = i; 6219 rxq->ifr_fl_offset = fl_offset; 6220 rxq->ifr_nfl = nfree_lists; 6221 if (!(fl = 6222 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 6223 device_printf(dev, "Unable to allocate free list memory\n"); 6224 err = ENOMEM; 6225 goto err_tx_desc; 6226 } 6227 rxq->ifr_fl = fl; 6228 for (j = 0; j < nfree_lists; j++) { 6229 fl[j].ifl_rxq = rxq; 6230 fl[j].ifl_id = j; 6231 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 6232 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 6233 } 6234 /* Allocate receive buffers for the ring */ 6235 if (iflib_rxsd_alloc(rxq)) { 6236 device_printf(dev, 6237 "Critical Failure setting up receive buffers\n"); 6238 err = ENOMEM; 6239 goto err_rx_desc; 6240 } 6241 6242 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 6243 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 6244 M_WAITOK); 6245 } 6246 6247 /* TXQs */ 6248 vaddrs = malloc(sizeof(caddr_t) * ntxqsets * ntxqs, M_IFLIB, M_WAITOK); 6249 paddrs = malloc(sizeof(uint64_t) * ntxqsets * ntxqs, M_IFLIB, M_WAITOK); 6250 for (i = 0; i < ntxqsets; i++) { 6251 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 6252 6253 for (j = 0; j < ntxqs; j++, di++) { 6254 vaddrs[i * ntxqs + j] = di->idi_vaddr; 6255 paddrs[i * ntxqs + j] = di->idi_paddr; 6256 } 6257 } 6258 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 6259 device_printf(ctx->ifc_dev, 6260 "Unable to allocate device TX queue\n"); 6261 iflib_tx_structures_free(ctx); 6262 free(vaddrs, M_IFLIB); 6263 free(paddrs, M_IFLIB); 6264 goto err_rx_desc; 6265 } 6266 free(vaddrs, M_IFLIB); 6267 free(paddrs, M_IFLIB); 6268 6269 /* RXQs */ 6270 vaddrs = malloc(sizeof(caddr_t) * nrxqsets * nrxqs, M_IFLIB, M_WAITOK); 6271 paddrs = malloc(sizeof(uint64_t) * nrxqsets * nrxqs, M_IFLIB, M_WAITOK); 6272 for (i = 0; i < nrxqsets; i++) { 6273 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 6274 6275 for (j = 0; j < nrxqs; j++, di++) { 6276 vaddrs[i * nrxqs + j] = di->idi_vaddr; 6277 paddrs[i * nrxqs + j] = di->idi_paddr; 6278 } 6279 } 6280 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 6281 device_printf(ctx->ifc_dev, 6282 "Unable to allocate device RX queue\n"); 6283 iflib_tx_structures_free(ctx); 6284 free(vaddrs, M_IFLIB); 6285 free(paddrs, M_IFLIB); 6286 goto err_rx_desc; 6287 } 6288 free(vaddrs, M_IFLIB); 6289 free(paddrs, M_IFLIB); 6290 6291 return (0); 6292 6293 /* XXX handle allocation failure changes */ 6294 err_rx_desc: 6295 err_tx_desc: 6296 rx_fail: 6297 if (ctx->ifc_rxqs != NULL) 6298 free(ctx->ifc_rxqs, M_IFLIB); 6299 ctx->ifc_rxqs = NULL; 6300 if (ctx->ifc_txqs != NULL) 6301 free(ctx->ifc_txqs, M_IFLIB); 6302 ctx->ifc_txqs = NULL; 6303 fail: 6304 return (err); 6305 } 6306 6307 static int 6308 iflib_tx_structures_setup(if_ctx_t ctx) 6309 { 6310 iflib_txq_t txq = ctx->ifc_txqs; 6311 int i; 6312 6313 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 6314 iflib_txq_setup(txq); 6315 6316 return (0); 6317 } 6318 6319 static void 6320 iflib_tx_structures_free(if_ctx_t ctx) 6321 { 6322 iflib_txq_t txq = ctx->ifc_txqs; 6323 if_shared_ctx_t sctx = ctx->ifc_sctx; 6324 int i, j; 6325 6326 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6327 for (j = 0; j < sctx->isc_ntxqs; j++) 6328 iflib_dma_free(&txq->ift_ifdi[j]); 6329 iflib_txq_destroy(txq); 6330 } 6331 free(ctx->ifc_txqs, M_IFLIB); 6332 ctx->ifc_txqs = NULL; 6333 } 6334 6335 /********************************************************************* 6336 * 6337 * Initialize all receive rings. 6338 * 6339 **********************************************************************/ 6340 static int 6341 iflib_rx_structures_setup(if_ctx_t ctx) 6342 { 6343 iflib_rxq_t rxq = ctx->ifc_rxqs; 6344 int q; 6345 #if defined(INET6) || defined(INET) 6346 int err, i; 6347 #endif 6348 6349 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 6350 #if defined(INET6) || defined(INET) 6351 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 6352 TCP_LRO_ENTRIES, min(1024, 6353 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 6354 if (err != 0) { 6355 device_printf(ctx->ifc_dev, 6356 "LRO Initialization failed!\n"); 6357 goto fail; 6358 } 6359 #endif 6360 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 6361 } 6362 return (0); 6363 #if defined(INET6) || defined(INET) 6364 fail: 6365 /* 6366 * Free LRO resources allocated so far, we will only handle 6367 * the rings that completed, the failing case will have 6368 * cleaned up for itself. 'q' failed, so its the terminus. 6369 */ 6370 rxq = ctx->ifc_rxqs; 6371 for (i = 0; i < q; ++i, rxq++) { 6372 tcp_lro_free(&rxq->ifr_lc); 6373 } 6374 return (err); 6375 #endif 6376 } 6377 6378 /********************************************************************* 6379 * 6380 * Free all receive rings. 6381 * 6382 **********************************************************************/ 6383 static void 6384 iflib_rx_structures_free(if_ctx_t ctx) 6385 { 6386 iflib_rxq_t rxq = ctx->ifc_rxqs; 6387 if_shared_ctx_t sctx = ctx->ifc_sctx; 6388 int i, j; 6389 6390 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 6391 for (j = 0; j < sctx->isc_nrxqs; j++) 6392 iflib_dma_free(&rxq->ifr_ifdi[j]); 6393 iflib_rx_sds_free(rxq); 6394 #if defined(INET6) || defined(INET) 6395 tcp_lro_free(&rxq->ifr_lc); 6396 #endif 6397 } 6398 free(ctx->ifc_rxqs, M_IFLIB); 6399 ctx->ifc_rxqs = NULL; 6400 } 6401 6402 static int 6403 iflib_qset_structures_setup(if_ctx_t ctx) 6404 { 6405 int err; 6406 6407 /* 6408 * It is expected that the caller takes care of freeing queues if this 6409 * fails. 6410 */ 6411 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 6412 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 6413 return (err); 6414 } 6415 6416 if ((err = iflib_rx_structures_setup(ctx)) != 0) 6417 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 6418 6419 return (err); 6420 } 6421 6422 int 6423 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 6424 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 6425 { 6426 6427 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 6428 } 6429 6430 /* Just to avoid copy/paste */ 6431 static inline int 6432 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6433 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 6434 const char *name) 6435 { 6436 device_t dev; 6437 unsigned int base_cpuid, cpuid; 6438 int err; 6439 6440 dev = ctx->ifc_dev; 6441 base_cpuid = ctx->ifc_sysctl_core_offset; 6442 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX); 6443 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, 6444 irq ? irq->ii_res : NULL, name); 6445 if (err) { 6446 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6447 return (err); 6448 } 6449 #ifdef notyet 6450 if (cpuid > ctx->ifc_cpuid_highest) 6451 ctx->ifc_cpuid_highest = cpuid; 6452 #endif 6453 return (0); 6454 } 6455 6456 /* 6457 * Allocate a hardware interrupt for subctx using the parent (ctx)'s hardware 6458 * resources. 6459 * 6460 * Similar to iflib_irq_alloc_generic(), but for interrupt type IFLIB_INTR_RXTX 6461 * only. 6462 * 6463 * XXX: Could be removed if subctx's dev has its intr resource allocation 6464 * methods replaced with custom ones? 6465 */ 6466 int 6467 iflib_irq_alloc_generic_subctx(if_ctx_t ctx, if_ctx_t subctx, if_irq_t irq, 6468 int rid, iflib_intr_type_t type, 6469 driver_filter_t *filter, void *filter_arg, 6470 int qid, const char *name) 6471 { 6472 device_t dev, subdev; 6473 struct grouptask *gtask; 6474 struct taskqgroup *tqg; 6475 iflib_filter_info_t info; 6476 gtask_fn_t *fn; 6477 int tqrid, err; 6478 driver_filter_t *intr_fast; 6479 void *q; 6480 6481 MPASS(ctx != NULL); 6482 MPASS(subctx != NULL); 6483 6484 tqrid = rid; 6485 dev = ctx->ifc_dev; 6486 subdev = subctx->ifc_dev; 6487 6488 switch (type) { 6489 case IFLIB_INTR_RXTX: 6490 q = &subctx->ifc_rxqs[qid]; 6491 info = &subctx->ifc_rxqs[qid].ifr_filter_info; 6492 gtask = &subctx->ifc_rxqs[qid].ifr_task; 6493 tqg = qgroup_if_io_tqg; 6494 fn = _task_fn_rx; 6495 intr_fast = iflib_fast_intr_rxtx; 6496 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6497 break; 6498 default: 6499 device_printf(dev, "%s: unknown net intr type for subctx %s (%d)\n", 6500 __func__, device_get_nameunit(subdev), type); 6501 return (EINVAL); 6502 } 6503 6504 info->ifi_filter = filter; 6505 info->ifi_filter_arg = filter_arg; 6506 info->ifi_task = gtask; 6507 info->ifi_ctx = q; 6508 6509 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6510 6511 /* Allocate interrupts from hardware using parent context */ 6512 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6513 if (err != 0) { 6514 device_printf(dev, "_iflib_irq_alloc failed for subctx %s: %d\n", 6515 device_get_nameunit(subdev), err); 6516 return (err); 6517 } 6518 6519 if (tqrid != -1) { 6520 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6521 name); 6522 if (err) 6523 return (err); 6524 } else { 6525 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6526 } 6527 6528 return (0); 6529 } 6530 6531 int 6532 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6533 iflib_intr_type_t type, driver_filter_t *filter, 6534 void *filter_arg, int qid, const char *name) 6535 { 6536 device_t dev; 6537 struct grouptask *gtask; 6538 struct taskqgroup *tqg; 6539 iflib_filter_info_t info; 6540 gtask_fn_t *fn; 6541 int tqrid, err; 6542 driver_filter_t *intr_fast; 6543 void *q; 6544 6545 info = &ctx->ifc_filter_info; 6546 tqrid = rid; 6547 6548 switch (type) { 6549 /* XXX merge tx/rx for netmap? */ 6550 case IFLIB_INTR_TX: 6551 q = &ctx->ifc_txqs[qid]; 6552 info = &ctx->ifc_txqs[qid].ift_filter_info; 6553 gtask = &ctx->ifc_txqs[qid].ift_task; 6554 tqg = qgroup_if_io_tqg; 6555 fn = _task_fn_tx; 6556 intr_fast = iflib_fast_intr; 6557 GROUPTASK_INIT(gtask, 0, fn, q); 6558 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6559 break; 6560 case IFLIB_INTR_RX: 6561 q = &ctx->ifc_rxqs[qid]; 6562 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6563 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6564 tqg = qgroup_if_io_tqg; 6565 fn = _task_fn_rx; 6566 intr_fast = iflib_fast_intr; 6567 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6568 break; 6569 case IFLIB_INTR_RXTX: 6570 q = &ctx->ifc_rxqs[qid]; 6571 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6572 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6573 tqg = qgroup_if_io_tqg; 6574 fn = _task_fn_rx; 6575 intr_fast = iflib_fast_intr_rxtx; 6576 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6577 break; 6578 case IFLIB_INTR_ADMIN: 6579 q = ctx; 6580 tqrid = -1; 6581 info = &ctx->ifc_filter_info; 6582 gtask = NULL; 6583 intr_fast = iflib_fast_intr_ctx; 6584 break; 6585 default: 6586 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6587 __func__); 6588 return (EINVAL); 6589 } 6590 6591 info->ifi_filter = filter; 6592 info->ifi_filter_arg = filter_arg; 6593 info->ifi_task = gtask; 6594 info->ifi_ctx = q; 6595 6596 dev = ctx->ifc_dev; 6597 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6598 if (err != 0) { 6599 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6600 return (err); 6601 } 6602 if (type == IFLIB_INTR_ADMIN) 6603 return (0); 6604 6605 if (tqrid != -1) { 6606 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6607 name); 6608 if (err) 6609 return (err); 6610 } else { 6611 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6612 } 6613 6614 return (0); 6615 } 6616 6617 void 6618 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6619 void *arg, int qid, const char *name) 6620 { 6621 device_t dev; 6622 struct grouptask *gtask; 6623 struct taskqgroup *tqg; 6624 gtask_fn_t *fn; 6625 void *q; 6626 int err; 6627 6628 switch (type) { 6629 case IFLIB_INTR_TX: 6630 q = &ctx->ifc_txqs[qid]; 6631 gtask = &ctx->ifc_txqs[qid].ift_task; 6632 tqg = qgroup_if_io_tqg; 6633 fn = _task_fn_tx; 6634 GROUPTASK_INIT(gtask, 0, fn, q); 6635 break; 6636 case IFLIB_INTR_RX: 6637 q = &ctx->ifc_rxqs[qid]; 6638 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6639 tqg = qgroup_if_io_tqg; 6640 fn = _task_fn_rx; 6641 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6642 break; 6643 case IFLIB_INTR_IOV: 6644 return; 6645 default: 6646 panic("unknown net intr type"); 6647 } 6648 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name); 6649 if (err) { 6650 dev = ctx->ifc_dev; 6651 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL, 6652 name); 6653 } 6654 } 6655 6656 void 6657 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6658 { 6659 6660 if (irq->ii_tag) 6661 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6662 6663 if (irq->ii_res) 6664 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6665 rman_get_rid(irq->ii_res), irq->ii_res); 6666 } 6667 6668 static int 6669 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6670 { 6671 iflib_txq_t txq = ctx->ifc_txqs; 6672 iflib_rxq_t rxq = ctx->ifc_rxqs; 6673 if_irq_t irq = &ctx->ifc_legacy_irq; 6674 iflib_filter_info_t info; 6675 device_t dev; 6676 struct grouptask *gtask; 6677 struct resource *res; 6678 int err, tqrid; 6679 bool rx_only; 6680 6681 info = &rxq->ifr_filter_info; 6682 gtask = &rxq->ifr_task; 6683 tqrid = *rid; 6684 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6685 6686 ctx->ifc_flags |= IFC_LEGACY; 6687 info->ifi_filter = filter; 6688 info->ifi_filter_arg = filter_arg; 6689 info->ifi_task = gtask; 6690 info->ifi_ctx = rxq; 6691 6692 dev = ctx->ifc_dev; 6693 /* We allocate a single interrupt resource */ 6694 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr : 6695 iflib_fast_intr_rxtx, NULL, info, name); 6696 if (err != 0) 6697 return (err); 6698 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, rxq); 6699 res = irq->ii_res; 6700 taskqgroup_attach(qgroup_if_io_tqg, gtask, rxq, dev, res, name); 6701 6702 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6703 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6704 "tx"); 6705 return (0); 6706 } 6707 6708 void 6709 iflib_led_create(if_ctx_t ctx) 6710 { 6711 6712 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6713 device_get_nameunit(ctx->ifc_dev)); 6714 } 6715 6716 void 6717 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6718 { 6719 6720 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6721 } 6722 6723 void 6724 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6725 { 6726 6727 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6728 } 6729 6730 void 6731 iflib_admin_intr_deferred(if_ctx_t ctx) 6732 { 6733 6734 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_admin_task); 6735 } 6736 6737 void 6738 iflib_iov_intr_deferred(if_ctx_t ctx) 6739 { 6740 6741 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_vflr_task); 6742 } 6743 6744 void 6745 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6746 { 6747 6748 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6749 name); 6750 } 6751 6752 void 6753 iflib_config_task_init(if_ctx_t ctx, struct task *config_task, task_fn_t *fn) 6754 { 6755 TASK_INIT(config_task, 0, fn, ctx); 6756 } 6757 6758 void 6759 iflib_config_task_enqueue(if_ctx_t ctx, struct task *config_task) 6760 { 6761 taskqueue_enqueue(ctx->ifc_tq, config_task); 6762 } 6763 6764 void 6765 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6766 { 6767 if_t ifp = ctx->ifc_ifp; 6768 6769 if_setbaudrate(ifp, baudrate); 6770 if (baudrate >= IF_Gbps(10)) { 6771 STATE_LOCK(ctx); 6772 ctx->ifc_flags |= IFC_PREFETCH; 6773 STATE_UNLOCK(ctx); 6774 } 6775 ctx->ifc_link_state = link_state; 6776 if_link_state_change(ifp, link_state); 6777 } 6778 6779 static int 6780 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6781 { 6782 int credits; 6783 #ifdef INVARIANTS 6784 int credits_pre = txq->ift_cidx_processed; 6785 #endif 6786 6787 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6788 BUS_DMASYNC_POSTREAD); 6789 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6790 return (0); 6791 6792 txq->ift_processed += credits; 6793 txq->ift_cidx_processed += credits; 6794 6795 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6796 if (txq->ift_cidx_processed >= txq->ift_size) 6797 txq->ift_cidx_processed -= txq->ift_size; 6798 return (credits); 6799 } 6800 6801 static int 6802 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6803 { 6804 iflib_fl_t fl; 6805 u_int i; 6806 6807 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6808 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6809 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6810 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6811 budget)); 6812 } 6813 6814 void 6815 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6816 const char *description, if_int_delay_info_t info, 6817 int offset, int value) 6818 { 6819 info->iidi_ctx = ctx; 6820 info->iidi_offset = offset; 6821 info->iidi_value = value; 6822 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6823 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6824 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6825 info, 0, iflib_sysctl_int_delay, "I", description); 6826 } 6827 6828 struct sx * 6829 iflib_ctx_lock_get(if_ctx_t ctx) 6830 { 6831 6832 return (&ctx->ifc_ctx_sx); 6833 } 6834 6835 static int 6836 iflib_msix_init(if_ctx_t ctx) 6837 { 6838 device_t dev = ctx->ifc_dev; 6839 if_shared_ctx_t sctx = ctx->ifc_sctx; 6840 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6841 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6842 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6843 6844 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6845 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6846 6847 if (bootverbose) 6848 device_printf(dev, "msix_init qsets capped at %d\n", 6849 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6850 6851 /* Override by tuneable */ 6852 if (scctx->isc_disable_msix) 6853 goto msi; 6854 6855 /* First try MSI-X */ 6856 if ((msgs = pci_msix_count(dev)) == 0) { 6857 if (bootverbose) 6858 device_printf(dev, "MSI-X not supported or disabled\n"); 6859 goto msi; 6860 } 6861 6862 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6863 /* 6864 * bar == -1 => "trust me I know what I'm doing" 6865 * Some drivers are for hardware that is so shoddily 6866 * documented that no one knows which bars are which 6867 * so the developer has to map all bars. This hack 6868 * allows shoddy garbage to use MSI-X in this framework. 6869 */ 6870 if (bar != -1) { 6871 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6872 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6873 if (ctx->ifc_msix_mem == NULL) { 6874 device_printf(dev, "Unable to map MSI-X table\n"); 6875 goto msi; 6876 } 6877 } 6878 6879 admincnt = sctx->isc_admin_intrcnt; 6880 #if IFLIB_DEBUG 6881 /* use only 1 qset in debug mode */ 6882 queuemsgs = min(msgs - admincnt, 1); 6883 #else 6884 queuemsgs = msgs - admincnt; 6885 #endif 6886 #ifdef RSS 6887 queues = imin(queuemsgs, rss_getnumbuckets()); 6888 #else 6889 queues = queuemsgs; 6890 #endif 6891 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6892 if (bootverbose) 6893 device_printf(dev, 6894 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6895 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6896 #ifdef RSS 6897 /* If we're doing RSS, clamp at the number of RSS buckets */ 6898 if (queues > rss_getnumbuckets()) 6899 queues = rss_getnumbuckets(); 6900 #endif 6901 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6902 rx_queues = iflib_num_rx_queues; 6903 else 6904 rx_queues = queues; 6905 6906 if (rx_queues > scctx->isc_nrxqsets) 6907 rx_queues = scctx->isc_nrxqsets; 6908 6909 /* 6910 * We want this to be all logical CPUs by default 6911 */ 6912 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6913 tx_queues = iflib_num_tx_queues; 6914 else 6915 tx_queues = mp_ncpus; 6916 6917 if (tx_queues > scctx->isc_ntxqsets) 6918 tx_queues = scctx->isc_ntxqsets; 6919 6920 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6921 #ifdef INVARIANTS 6922 if (tx_queues != rx_queues) 6923 device_printf(dev, 6924 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6925 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6926 #endif 6927 tx_queues = min(rx_queues, tx_queues); 6928 rx_queues = min(rx_queues, tx_queues); 6929 } 6930 6931 vectors = rx_queues + admincnt; 6932 if (msgs < vectors) { 6933 device_printf(dev, 6934 "insufficient number of MSI-X vectors " 6935 "(supported %d, need %d)\n", msgs, vectors); 6936 goto msi; 6937 } 6938 6939 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6940 tx_queues); 6941 msgs = vectors; 6942 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6943 if (vectors != msgs) { 6944 device_printf(dev, 6945 "Unable to allocate sufficient MSI-X vectors " 6946 "(got %d, need %d)\n", vectors, msgs); 6947 pci_release_msi(dev); 6948 if (bar != -1) { 6949 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6950 ctx->ifc_msix_mem); 6951 ctx->ifc_msix_mem = NULL; 6952 } 6953 goto msi; 6954 } 6955 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6956 vectors); 6957 scctx->isc_vectors = vectors; 6958 scctx->isc_nrxqsets = rx_queues; 6959 scctx->isc_ntxqsets = tx_queues; 6960 scctx->isc_intr = IFLIB_INTR_MSIX; 6961 6962 return (vectors); 6963 } else { 6964 device_printf(dev, 6965 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6966 err); 6967 if (bar != -1) { 6968 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6969 ctx->ifc_msix_mem); 6970 ctx->ifc_msix_mem = NULL; 6971 } 6972 } 6973 6974 msi: 6975 vectors = pci_msi_count(dev); 6976 scctx->isc_nrxqsets = 1; 6977 scctx->isc_ntxqsets = 1; 6978 scctx->isc_vectors = vectors; 6979 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6980 device_printf(dev, "Using an MSI interrupt\n"); 6981 scctx->isc_intr = IFLIB_INTR_MSI; 6982 } else { 6983 scctx->isc_vectors = 1; 6984 device_printf(dev, "Using a Legacy interrupt\n"); 6985 scctx->isc_intr = IFLIB_INTR_LEGACY; 6986 } 6987 6988 return (vectors); 6989 } 6990 6991 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6992 6993 static int 6994 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6995 { 6996 int rc; 6997 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6998 struct sbuf *sb; 6999 const char *ring_state = "UNKNOWN"; 7000 7001 /* XXX needed ? */ 7002 rc = sysctl_wire_old_buffer(req, 0); 7003 MPASS(rc == 0); 7004 if (rc != 0) 7005 return (rc); 7006 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 7007 MPASS(sb != NULL); 7008 if (sb == NULL) 7009 return (ENOMEM); 7010 if (state[3] <= 3) 7011 ring_state = ring_states[state[3]]; 7012 7013 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 7014 state[0], state[1], state[2], ring_state); 7015 rc = sbuf_finish(sb); 7016 sbuf_delete(sb); 7017 return (rc); 7018 } 7019 7020 enum iflib_ndesc_handler { 7021 IFLIB_NTXD_HANDLER, 7022 IFLIB_NRXD_HANDLER, 7023 }; 7024 7025 static int 7026 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 7027 { 7028 if_ctx_t ctx = (void *)arg1; 7029 enum iflib_ndesc_handler type = arg2; 7030 char buf[256] = {0}; 7031 qidx_t *ndesc; 7032 char *p, *next; 7033 int nqs, rc, i; 7034 7035 nqs = 8; 7036 switch (type) { 7037 case IFLIB_NTXD_HANDLER: 7038 ndesc = ctx->ifc_sysctl_ntxds; 7039 if (ctx->ifc_sctx) 7040 nqs = ctx->ifc_sctx->isc_ntxqs; 7041 break; 7042 case IFLIB_NRXD_HANDLER: 7043 ndesc = ctx->ifc_sysctl_nrxds; 7044 if (ctx->ifc_sctx) 7045 nqs = ctx->ifc_sctx->isc_nrxqs; 7046 break; 7047 default: 7048 printf("%s: unhandled type\n", __func__); 7049 return (EINVAL); 7050 } 7051 if (nqs == 0) 7052 nqs = 8; 7053 7054 for (i = 0; i < 8; i++) { 7055 if (i >= nqs) 7056 break; 7057 if (i) 7058 strcat(buf, ","); 7059 sprintf(strchr(buf, 0), "%d", ndesc[i]); 7060 } 7061 7062 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 7063 if (rc || req->newptr == NULL) 7064 return (rc); 7065 7066 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 7067 i++, p = strsep(&next, " ,")) { 7068 ndesc[i] = strtoul(p, NULL, 10); 7069 } 7070 7071 return (rc); 7072 } 7073 7074 static int 7075 iflib_handle_tx_reclaim_thresh(SYSCTL_HANDLER_ARGS) 7076 { 7077 if_ctx_t ctx = (void *)arg1; 7078 iflib_txq_t txq; 7079 int i, err; 7080 int thresh; 7081 7082 thresh = ctx->ifc_sysctl_tx_reclaim_thresh; 7083 err = sysctl_handle_int(oidp, &thresh, arg2, req); 7084 if (err != 0) { 7085 return err; 7086 } 7087 7088 if (thresh == ctx->ifc_sysctl_tx_reclaim_thresh) 7089 return 0; 7090 7091 if (thresh > ctx->ifc_softc_ctx.isc_ntxd[0] / 2) { 7092 device_printf(ctx->ifc_dev, "TX Reclaim thresh must be <= %d\n", 7093 ctx->ifc_softc_ctx.isc_ntxd[0] / 2); 7094 return (EINVAL); 7095 } 7096 7097 ctx->ifc_sysctl_tx_reclaim_thresh = thresh; 7098 if (ctx->ifc_txqs == NULL) 7099 return (err); 7100 7101 txq = &ctx->ifc_txqs[0]; 7102 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 7103 txq->ift_reclaim_thresh = thresh; 7104 } 7105 return (err); 7106 } 7107 7108 static int 7109 iflib_handle_tx_reclaim_ticks(SYSCTL_HANDLER_ARGS) 7110 { 7111 if_ctx_t ctx = (void *)arg1; 7112 iflib_txq_t txq; 7113 int i, err; 7114 int ticks; 7115 7116 ticks = ctx->ifc_sysctl_tx_reclaim_ticks; 7117 err = sysctl_handle_int(oidp, &ticks, arg2, req); 7118 if (err != 0) { 7119 return err; 7120 } 7121 7122 if (ticks == ctx->ifc_sysctl_tx_reclaim_ticks) 7123 return 0; 7124 7125 if (ticks > hz) { 7126 device_printf(ctx->ifc_dev, 7127 "TX Reclaim ticks must be <= hz (%d)\n", hz); 7128 return (EINVAL); 7129 } 7130 7131 ctx->ifc_sysctl_tx_reclaim_ticks = ticks; 7132 if (ctx->ifc_txqs == NULL) 7133 return (err); 7134 7135 txq = &ctx->ifc_txqs[0]; 7136 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 7137 txq->ift_reclaim_ticks = ticks; 7138 } 7139 return (err); 7140 } 7141 7142 static int 7143 iflib_handle_tx_defer_mfree(SYSCTL_HANDLER_ARGS) 7144 { 7145 if_ctx_t ctx = (void *)arg1; 7146 iflib_txq_t txq; 7147 int i, err; 7148 int defer; 7149 7150 defer = ctx->ifc_sysctl_tx_defer_mfree; 7151 err = sysctl_handle_int(oidp, &defer, arg2, req); 7152 if (err != 0) { 7153 return err; 7154 } 7155 7156 if (defer == ctx->ifc_sysctl_tx_defer_mfree) 7157 return 0; 7158 7159 ctx->ifc_sysctl_tx_defer_mfree = defer; 7160 if (ctx->ifc_txqs == NULL) 7161 return (err); 7162 7163 txq = &ctx->ifc_txqs[0]; 7164 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 7165 txq->ift_defer_mfree = defer; 7166 } 7167 return (err); 7168 } 7169 7170 #define NAME_BUFLEN 32 7171 static void 7172 iflib_add_device_sysctl_pre(if_ctx_t ctx) 7173 { 7174 device_t dev = iflib_get_dev(ctx); 7175 struct sysctl_oid_list *child, *oid_list; 7176 struct sysctl_oid *node; 7177 7178 sysctl_ctx_init(&ctx->ifc_sysctl_ctx); 7179 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 7180 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(&ctx->ifc_sysctl_ctx, child, 7181 OID_AUTO, "iflib", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 7182 "IFLIB fields"); 7183 oid_list = SYSCTL_CHILDREN(node); 7184 7185 SYSCTL_ADD_CONST_STRING(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "driver_version", 7186 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, "driver version"); 7187 SYSCTL_ADD_U32(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, 7188 "tx_watchdog_events", CTLFLAG_RD, &ctx->ifc_tx_watchdog_events, 0, 7189 "TX watchdog resets initiated by iflib"); 7190 7191 SYSCTL_ADD_BOOL(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "simple_tx", 7192 CTLFLAG_RDTUN, &ctx->ifc_sysctl_simple_tx, 0, 7193 "use simple tx ring"); 7194 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_ntxqs", 7195 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 7196 "# of txqs to use, 0 => use default #"); 7197 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_nrxqs", 7198 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 7199 "# of rxqs to use, 0 => use default #"); 7200 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_qs_enable", 7201 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 7202 "permit #txq != #rxq"); 7203 SYSCTL_ADD_INT(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "disable_msix", 7204 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 7205 "disable MSI-X (default 0)"); 7206 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "rx_budget", 7207 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, "set the RX budget"); 7208 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "tx_abdicate", 7209 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 7210 "cause TX to abdicate instead of running to completion"); 7211 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 7212 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "core_offset", 7213 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 7214 "offset to start using cores at"); 7215 SYSCTL_ADD_U8(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "separate_txrx", 7216 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 7217 "use separate cores for TX and RX"); 7218 SYSCTL_ADD_U8(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "use_logical_cores", 7219 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0, 7220 "try to make use of logical cores for TX and RX"); 7221 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "use_extra_msix_vectors", 7222 CTLFLAG_RDTUN, &ctx->ifc_sysctl_extra_msix_vectors, 0, 7223 "attempt to reserve the given number of extra MSI-X vectors during driver load for the creation of additional interfaces later"); 7224 SYSCTL_ADD_INT(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "allocated_msix_vectors", 7225 CTLFLAG_RDTUN, &ctx->ifc_softc_ctx.isc_vectors, 0, 7226 "total # of MSI-X vectors allocated by driver"); 7227 7228 /* XXX change for per-queue sizes */ 7229 SYSCTL_ADD_PROC(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_ntxds", 7230 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 7231 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 7232 "list of # of TX descriptors to use, 0 = use default #"); 7233 SYSCTL_ADD_PROC(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_nrxds", 7234 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 7235 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 7236 "list of # of RX descriptors to use, 0 = use default #"); 7237 } 7238 7239 static void 7240 iflib_add_device_sysctl_post(if_ctx_t ctx) 7241 { 7242 if_shared_ctx_t sctx = ctx->ifc_sctx; 7243 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 7244 struct sysctl_oid_list *child; 7245 struct sysctl_ctx_list *ctx_list = &ctx->ifc_sysctl_ctx; 7246 iflib_fl_t fl; 7247 iflib_txq_t txq; 7248 iflib_rxq_t rxq; 7249 int i, j; 7250 char namebuf[NAME_BUFLEN]; 7251 char *qfmt; 7252 struct sysctl_oid *queue_node, *fl_node, *node; 7253 struct sysctl_oid_list *queue_list, *fl_list; 7254 7255 node = ctx->ifc_sysctl_node; 7256 child = SYSCTL_CHILDREN(node); 7257 7258 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_reclaim_thresh", 7259 CTLTYPE_INT | CTLFLAG_RWTUN, ctx, 7260 0, iflib_handle_tx_reclaim_thresh, "I", 7261 "Number of TX descs outstanding before reclaim is called"); 7262 7263 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_reclaim_ticks", 7264 CTLTYPE_INT | CTLFLAG_RWTUN, ctx, 7265 0, iflib_handle_tx_reclaim_ticks, "I", 7266 "Number of ticks before a TX reclaim is forced"); 7267 7268 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_defer_mfree", 7269 CTLTYPE_INT | CTLFLAG_RWTUN, ctx, 7270 0, iflib_handle_tx_defer_mfree, "I", 7271 "Free completed transmits outside of TX ring lock"); 7272 7273 if (scctx->isc_ntxqsets > 100) 7274 qfmt = "txq%03d"; 7275 else if (scctx->isc_ntxqsets > 10) 7276 qfmt = "txq%02d"; 7277 else 7278 qfmt = "txq%d"; 7279 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 7280 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 7281 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 7282 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 7283 queue_list = SYSCTL_CHILDREN(queue_node); 7284 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 7285 CTLFLAG_RD, &txq->ift_task.gt_cpu, 0, 7286 "cpu this queue is bound to"); 7287 #if MEMORY_LOGGING 7288 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 7289 CTLFLAG_RD, &txq->ift_dequeued, "total mbufs freed"); 7290 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 7291 CTLFLAG_RD, &txq->ift_enqueued, "total mbufs enqueued"); 7292 #endif 7293 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 7294 CTLFLAG_RD, &txq->ift_mbuf_defrag, 7295 "# of times m_defrag was called"); 7296 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 7297 CTLFLAG_RD, &txq->ift_pullups, 7298 "# of times m_pullup was called"); 7299 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7300 "mbuf_defrag_failed", CTLFLAG_RD, 7301 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 7302 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7303 "no_desc_avail", CTLFLAG_RD, &txq->ift_no_desc_avail, 7304 "# of times no descriptors were available"); 7305 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7306 "tx_map_failed", CTLFLAG_RD, &txq->ift_map_failed, 7307 "# of times DMA map failed"); 7308 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7309 "txd_encap_efbig", CTLFLAG_RD, &txq->ift_txd_encap_efbig, 7310 "# of times txd_encap returned EFBIG"); 7311 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7312 "no_tx_dma_setup", CTLFLAG_RD, &txq->ift_no_tx_dma_setup, 7313 "# of times map failed for other than EFBIG"); 7314 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 7315 CTLFLAG_RD, &txq->ift_pidx, 1, "Producer Index"); 7316 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 7317 CTLFLAG_RD, &txq->ift_cidx, 1, "Consumer Index"); 7318 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, 7319 "txq_cidx_processed", CTLFLAG_RD, &txq->ift_cidx_processed, 7320 1, "Consumer Index seen by credit update"); 7321 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 7322 CTLFLAG_RD, &txq->ift_in_use, 1, "descriptors in use"); 7323 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 7324 "txq_processed", CTLFLAG_RD, &txq->ift_processed, 7325 "descriptors procesed for clean"); 7326 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 7327 CTLFLAG_RD, &txq->ift_cleaned, "total cleaned"); 7328 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 7329 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 7330 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 7331 mp_ring_state_handler, "A", "soft ring state"); 7332 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7333 "r_enqueues", CTLFLAG_RD, &txq->ift_br->enqueues, 7334 "# of enqueues to the mp_ring for this queue"); 7335 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7336 "r_drops", CTLFLAG_RD, &txq->ift_br->drops, 7337 "# of drops in the mp_ring for this queue"); 7338 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7339 "r_starts", CTLFLAG_RD, &txq->ift_br->starts, 7340 "# of normal consumer starts in mp_ring for this queue"); 7341 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7342 "r_stalls", CTLFLAG_RD, &txq->ift_br->stalls, 7343 "# of consumer stalls in the mp_ring for this queue"); 7344 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7345 "r_restarts", CTLFLAG_RD, &txq->ift_br->restarts, 7346 "# of consumer restarts in the mp_ring for this queue"); 7347 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7348 "r_abdications", CTLFLAG_RD, &txq->ift_br->abdications, 7349 "# of consumer abdications in the mp_ring for this queue"); 7350 } 7351 7352 if (scctx->isc_nrxqsets > 100) 7353 qfmt = "rxq%03d"; 7354 else if (scctx->isc_nrxqsets > 10) 7355 qfmt = "rxq%02d"; 7356 else 7357 qfmt = "rxq%d"; 7358 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 7359 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 7360 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 7361 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 7362 queue_list = SYSCTL_CHILDREN(queue_node); 7363 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 7364 CTLFLAG_RD, &rxq->ifr_task.gt_cpu, 0, 7365 "cpu this queue is bound to"); 7366 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 7367 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, 7368 "rxq_cq_cidx", CTLFLAG_RD, &rxq->ifr_cq_cidx, 1, 7369 "Consumer Index"); 7370 } 7371 7372 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 7373 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 7374 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, 7375 OID_AUTO, namebuf, CTLFLAG_RD | CTLFLAG_MPSAFE, 7376 NULL, "freelist Name"); 7377 fl_list = SYSCTL_CHILDREN(fl_node); 7378 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 7379 CTLFLAG_RD, &fl->ifl_pidx, 1, "Producer Index"); 7380 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 7381 CTLFLAG_RD, &fl->ifl_cidx, 1, "Consumer Index"); 7382 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 7383 CTLFLAG_RD, &fl->ifl_credits, 1, 7384 "credits available"); 7385 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 7386 CTLFLAG_RD, &fl->ifl_buf_size, 1, "buffer size"); 7387 #if MEMORY_LOGGING 7388 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7389 "fl_m_enqueued", CTLFLAG_RD, &fl->ifl_m_enqueued, 7390 "mbufs allocated"); 7391 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7392 "fl_m_dequeued", CTLFLAG_RD, &fl->ifl_m_dequeued, 7393 "mbufs freed"); 7394 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7395 "fl_cl_enqueued", CTLFLAG_RD, &fl->ifl_cl_enqueued, 7396 "clusters allocated"); 7397 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7398 "fl_cl_dequeued", CTLFLAG_RD, &fl->ifl_cl_dequeued, 7399 "clusters freed"); 7400 #endif 7401 } 7402 } 7403 7404 } 7405 7406 void 7407 iflib_request_reset(if_ctx_t ctx) 7408 { 7409 7410 STATE_LOCK(ctx); 7411 ctx->ifc_flags |= IFC_DO_RESET; 7412 STATE_UNLOCK(ctx); 7413 } 7414 7415 void 7416 iflib_request_reset_if_up(if_ctx_t ctx) 7417 { 7418 7419 STATE_LOCK(ctx); 7420 ctx->ifc_flags |= IFC_DO_RESET_IF_UP; 7421 STATE_UNLOCK(ctx); 7422 } 7423 7424 void 7425 iflib_init_failed(if_ctx_t ctx) 7426 { 7427 7428 sx_assert(&ctx->ifc_ctx_sx, SA_XLOCKED); 7429 STATE_LOCK(ctx); 7430 ctx->ifc_flags |= IFC_INIT_FAILED; 7431 STATE_UNLOCK(ctx); 7432 } 7433 7434 #ifndef __NO_STRICT_ALIGNMENT 7435 static struct mbuf * 7436 iflib_fixup_rx(struct mbuf *m) 7437 { 7438 struct mbuf *n; 7439 7440 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 7441 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 7442 m->m_data += ETHER_HDR_LEN; 7443 n = m; 7444 } else { 7445 MGETHDR(n, M_NOWAIT, MT_DATA); 7446 if (n == NULL) { 7447 m_freem(m); 7448 return (NULL); 7449 } 7450 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 7451 m->m_data += ETHER_HDR_LEN; 7452 m->m_len -= ETHER_HDR_LEN; 7453 n->m_len = ETHER_HDR_LEN; 7454 M_MOVE_PKTHDR(n, m); 7455 n->m_next = m; 7456 } 7457 return (n); 7458 } 7459 #endif 7460 7461 #ifdef DEBUGNET 7462 static void 7463 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 7464 { 7465 if_ctx_t ctx; 7466 7467 ctx = if_getsoftc(ifp); 7468 CTX_LOCK(ctx); 7469 *nrxr = NRXQSETS(ctx); 7470 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 7471 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 7472 CTX_UNLOCK(ctx); 7473 } 7474 7475 static void 7476 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 7477 { 7478 if_ctx_t ctx; 7479 if_softc_ctx_t scctx; 7480 iflib_fl_t fl; 7481 iflib_rxq_t rxq; 7482 int i, j; 7483 7484 ctx = if_getsoftc(ifp); 7485 scctx = &ctx->ifc_softc_ctx; 7486 7487 switch (event) { 7488 case DEBUGNET_START: 7489 for (i = 0; i < scctx->isc_nrxqsets; i++) { 7490 rxq = &ctx->ifc_rxqs[i]; 7491 for (j = 0; j < rxq->ifr_nfl; j++) { 7492 fl = rxq->ifr_fl; 7493 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 7494 } 7495 } 7496 iflib_no_tx_batch = 1; 7497 break; 7498 default: 7499 break; 7500 } 7501 } 7502 7503 static int 7504 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 7505 { 7506 if_ctx_t ctx; 7507 iflib_txq_t txq; 7508 int error; 7509 int bytes_sent = 0; 7510 int pkt_sent = 0; 7511 7512 ctx = if_getsoftc(ifp); 7513 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7514 IFF_DRV_RUNNING) 7515 return (EBUSY); 7516 7517 txq = &ctx->ifc_txqs[0]; 7518 error = iflib_encap(txq, &m, &bytes_sent, &pkt_sent); 7519 if (error == 0) 7520 (void)iflib_txd_db_check(txq, true); 7521 return (error); 7522 } 7523 7524 static int 7525 iflib_debugnet_poll(if_t ifp, int count) 7526 { 7527 struct epoch_tracker et; 7528 if_ctx_t ctx; 7529 if_softc_ctx_t scctx; 7530 iflib_txq_t txq; 7531 int i; 7532 7533 ctx = if_getsoftc(ifp); 7534 scctx = &ctx->ifc_softc_ctx; 7535 7536 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7537 IFF_DRV_RUNNING) 7538 return (EBUSY); 7539 7540 txq = &ctx->ifc_txqs[0]; 7541 (void)iflib_completed_tx_reclaim(txq, NULL); 7542 7543 NET_EPOCH_ENTER(et); 7544 for (i = 0; i < scctx->isc_nrxqsets; i++) 7545 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 7546 NET_EPOCH_EXIT(et); 7547 return (0); 7548 } 7549 #endif /* DEBUGNET */ 7550 7551 #ifndef ALTQ 7552 static inline iflib_txq_t 7553 iflib_simple_select_queue(if_ctx_t ctx, struct mbuf *m) 7554 { 7555 int qidx; 7556 7557 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 7558 qidx = QIDX(ctx, m); 7559 else 7560 qidx = NTXQSETS(ctx) + FIRST_QSET(ctx) - 1; 7561 return (&ctx->ifc_txqs[qidx]); 7562 } 7563 7564 static int 7565 iflib_simple_transmit(if_t ifp, struct mbuf *m) 7566 { 7567 if_ctx_t ctx; 7568 iflib_txq_t txq; 7569 struct mbuf **m_defer; 7570 int error, i, reclaimable; 7571 int bytes_sent = 0, pkt_sent = 0, mcast_sent = 0; 7572 7573 7574 ctx = if_getsoftc(ifp); 7575 if (__predict_false((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 7576 || !LINK_ACTIVE(ctx))) { 7577 DBG_COUNTER_INC(tx_frees); 7578 m_freem(m); 7579 return (ENETDOWN); 7580 } 7581 7582 txq = iflib_simple_select_queue(ctx, m); 7583 mtx_lock(&txq->ift_mtx); 7584 error = iflib_encap(txq, &m, &bytes_sent, &pkt_sent); 7585 if (error == 0) { 7586 mcast_sent += !!(m->m_flags & M_MCAST); 7587 (void)iflib_txd_db_check(txq, true); 7588 } else { 7589 if (error == ENOBUFS) 7590 if_inc_counter(ifp, IFCOUNTER_OQDROPS, 1); 7591 else 7592 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 7593 } 7594 m_defer = NULL; 7595 reclaimable = iflib_txq_can_reclaim(txq); 7596 if (reclaimable != 0) { 7597 /* 7598 * Try to set m_defer to the deferred mbuf reclaim array. If 7599 * we can, the frees will happen outside the tx lock. If we 7600 * can't, it means another thread is still proccessing frees. 7601 */ 7602 if (txq->ift_defer_mfree && 7603 atomic_cmpset_acq_ptr((uintptr_t *)&txq->ift_sds.ifsd_m_defer, 7604 (uintptr_t )txq->ift_sds.ifsd_m_deferb, 0)) { 7605 m_defer = txq->ift_sds.ifsd_m_deferb; 7606 } 7607 _iflib_completed_tx_reclaim(txq, m_defer, reclaimable); 7608 } 7609 mtx_unlock(&txq->ift_mtx); 7610 7611 /* 7612 * Process mbuf frees outside the tx lock 7613 */ 7614 if (m_defer != NULL) { 7615 for (i = 0; m_defer[i] != NULL; i++) { 7616 m_freem(m_defer[i]); 7617 m_defer[i] = NULL; 7618 } 7619 atomic_store_rel_ptr((uintptr_t *)&txq->ift_sds.ifsd_m_defer, 7620 (uintptr_t)m_defer); 7621 } 7622 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 7623 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 7624 if (mcast_sent) 7625 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 7626 7627 return (error); 7628 } 7629 #endif 7630