1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 120 /* 121 * File organization: 122 * - private structures 123 * - iflib private utility functions 124 * - ifnet functions 125 * - vlan registry and other exported functions 126 * - iflib public core functions 127 * 128 * 129 */ 130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 131 132 #define IFLIB_RXEOF_MORE (1U << 0) 133 #define IFLIB_RXEOF_EMPTY (2U << 0) 134 135 struct iflib_txq; 136 typedef struct iflib_txq *iflib_txq_t; 137 struct iflib_rxq; 138 typedef struct iflib_rxq *iflib_rxq_t; 139 struct iflib_fl; 140 typedef struct iflib_fl *iflib_fl_t; 141 142 struct iflib_ctx; 143 144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 145 static void iflib_timer(void *arg); 146 147 typedef struct iflib_filter_info { 148 driver_filter_t *ifi_filter; 149 void *ifi_filter_arg; 150 struct grouptask *ifi_task; 151 void *ifi_ctx; 152 } *iflib_filter_info_t; 153 154 struct iflib_ctx { 155 KOBJ_FIELDS; 156 /* 157 * Pointer to hardware driver's softc 158 */ 159 void *ifc_softc; 160 device_t ifc_dev; 161 if_t ifc_ifp; 162 163 cpuset_t ifc_cpus; 164 if_shared_ctx_t ifc_sctx; 165 struct if_softc_ctx ifc_softc_ctx; 166 167 struct sx ifc_ctx_sx; 168 struct mtx ifc_state_mtx; 169 170 iflib_txq_t ifc_txqs; 171 iflib_rxq_t ifc_rxqs; 172 uint32_t ifc_if_flags; 173 uint32_t ifc_flags; 174 uint32_t ifc_max_fl_buf_size; 175 uint32_t ifc_rx_mbuf_sz; 176 177 int ifc_link_state; 178 int ifc_watchdog_events; 179 struct cdev *ifc_led_dev; 180 struct resource *ifc_msix_mem; 181 182 struct if_irq ifc_legacy_irq; 183 struct grouptask ifc_admin_task; 184 struct grouptask ifc_vflr_task; 185 struct iflib_filter_info ifc_filter_info; 186 struct ifmedia ifc_media; 187 struct ifmedia *ifc_mediap; 188 189 struct sysctl_oid *ifc_sysctl_node; 190 uint16_t ifc_sysctl_ntxqs; 191 uint16_t ifc_sysctl_nrxqs; 192 uint16_t ifc_sysctl_qs_eq_override; 193 uint16_t ifc_sysctl_rx_budget; 194 uint16_t ifc_sysctl_tx_abdicate; 195 uint16_t ifc_sysctl_core_offset; 196 #define CORE_OFFSET_UNSPECIFIED 0xffff 197 uint8_t ifc_sysctl_separate_txrx; 198 199 qidx_t ifc_sysctl_ntxds[8]; 200 qidx_t ifc_sysctl_nrxds[8]; 201 struct if_txrx ifc_txrx; 202 #define isc_txd_encap ifc_txrx.ift_txd_encap 203 #define isc_txd_flush ifc_txrx.ift_txd_flush 204 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 205 #define isc_rxd_available ifc_txrx.ift_rxd_available 206 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 209 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 210 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 211 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 212 eventhandler_tag ifc_vlan_attach_event; 213 eventhandler_tag ifc_vlan_detach_event; 214 struct ether_addr ifc_mac; 215 }; 216 217 void * 218 iflib_get_softc(if_ctx_t ctx) 219 { 220 221 return (ctx->ifc_softc); 222 } 223 224 device_t 225 iflib_get_dev(if_ctx_t ctx) 226 { 227 228 return (ctx->ifc_dev); 229 } 230 231 if_t 232 iflib_get_ifp(if_ctx_t ctx) 233 { 234 235 return (ctx->ifc_ifp); 236 } 237 238 struct ifmedia * 239 iflib_get_media(if_ctx_t ctx) 240 { 241 242 return (ctx->ifc_mediap); 243 } 244 245 uint32_t 246 iflib_get_flags(if_ctx_t ctx) 247 { 248 return (ctx->ifc_flags); 249 } 250 251 void 252 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 253 { 254 255 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 256 } 257 258 if_softc_ctx_t 259 iflib_get_softc_ctx(if_ctx_t ctx) 260 { 261 262 return (&ctx->ifc_softc_ctx); 263 } 264 265 if_shared_ctx_t 266 iflib_get_sctx(if_ctx_t ctx) 267 { 268 269 return (ctx->ifc_sctx); 270 } 271 272 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 273 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 274 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 275 276 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 277 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 278 279 typedef struct iflib_sw_rx_desc_array { 280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 281 struct mbuf **ifsd_m; /* pkthdr mbufs */ 282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 283 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 284 } iflib_rxsd_array_t; 285 286 typedef struct iflib_sw_tx_desc_array { 287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 288 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 289 struct mbuf **ifsd_m; /* pkthdr mbufs */ 290 } if_txsd_vec_t; 291 292 /* magic number that should be high enough for any hardware */ 293 #define IFLIB_MAX_TX_SEGS 128 294 #define IFLIB_RX_COPY_THRESH 128 295 #define IFLIB_MAX_RX_REFRESH 32 296 /* The minimum descriptors per second before we start coalescing */ 297 #define IFLIB_MIN_DESC_SEC 16384 298 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 299 #define IFLIB_QUEUE_IDLE 0 300 #define IFLIB_QUEUE_HUNG 1 301 #define IFLIB_QUEUE_WORKING 2 302 /* maximum number of txqs that can share an rx interrupt */ 303 #define IFLIB_MAX_TX_SHARED_INTR 4 304 305 /* this should really scale with ring size - this is a fairly arbitrary value */ 306 #define TX_BATCH_SIZE 32 307 308 #define IFLIB_RESTART_BUDGET 8 309 310 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 311 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 312 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 313 314 struct iflib_txq { 315 qidx_t ift_in_use; 316 qidx_t ift_cidx; 317 qidx_t ift_cidx_processed; 318 qidx_t ift_pidx; 319 uint8_t ift_gen; 320 uint8_t ift_br_offset; 321 uint16_t ift_npending; 322 uint16_t ift_db_pending; 323 uint16_t ift_rs_pending; 324 /* implicit pad */ 325 uint8_t ift_txd_size[8]; 326 uint64_t ift_processed; 327 uint64_t ift_cleaned; 328 uint64_t ift_cleaned_prev; 329 #if MEMORY_LOGGING 330 uint64_t ift_enqueued; 331 uint64_t ift_dequeued; 332 #endif 333 uint64_t ift_no_tx_dma_setup; 334 uint64_t ift_no_desc_avail; 335 uint64_t ift_mbuf_defrag_failed; 336 uint64_t ift_mbuf_defrag; 337 uint64_t ift_map_failed; 338 uint64_t ift_txd_encap_efbig; 339 uint64_t ift_pullups; 340 uint64_t ift_last_timer_tick; 341 342 struct mtx ift_mtx; 343 struct mtx ift_db_mtx; 344 345 /* constant values */ 346 if_ctx_t ift_ctx; 347 struct ifmp_ring *ift_br; 348 struct grouptask ift_task; 349 qidx_t ift_size; 350 uint16_t ift_id; 351 struct callout ift_timer; 352 353 if_txsd_vec_t ift_sds; 354 uint8_t ift_qstatus; 355 uint8_t ift_closed; 356 uint8_t ift_update_freq; 357 struct iflib_filter_info ift_filter_info; 358 bus_dma_tag_t ift_buf_tag; 359 bus_dma_tag_t ift_tso_buf_tag; 360 iflib_dma_info_t ift_ifdi; 361 #define MTX_NAME_LEN 32 362 char ift_mtx_name[MTX_NAME_LEN]; 363 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 364 #ifdef IFLIB_DIAGNOSTICS 365 uint64_t ift_cpu_exec_count[256]; 366 #endif 367 } __aligned(CACHE_LINE_SIZE); 368 369 struct iflib_fl { 370 qidx_t ifl_cidx; 371 qidx_t ifl_pidx; 372 qidx_t ifl_credits; 373 uint8_t ifl_gen; 374 uint8_t ifl_rxd_size; 375 #if MEMORY_LOGGING 376 uint64_t ifl_m_enqueued; 377 uint64_t ifl_m_dequeued; 378 uint64_t ifl_cl_enqueued; 379 uint64_t ifl_cl_dequeued; 380 #endif 381 /* implicit pad */ 382 bitstr_t *ifl_rx_bitmap; 383 qidx_t ifl_fragidx; 384 /* constant */ 385 qidx_t ifl_size; 386 uint16_t ifl_buf_size; 387 uint16_t ifl_cltype; 388 uma_zone_t ifl_zone; 389 iflib_rxsd_array_t ifl_sds; 390 iflib_rxq_t ifl_rxq; 391 uint8_t ifl_id; 392 bus_dma_tag_t ifl_buf_tag; 393 iflib_dma_info_t ifl_ifdi; 394 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 395 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 396 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 397 } __aligned(CACHE_LINE_SIZE); 398 399 static inline qidx_t 400 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 401 { 402 qidx_t used; 403 404 if (pidx > cidx) 405 used = pidx - cidx; 406 else if (pidx < cidx) 407 used = size - cidx + pidx; 408 else if (gen == 0 && pidx == cidx) 409 used = 0; 410 else if (gen == 1 && pidx == cidx) 411 used = size; 412 else 413 panic("bad state"); 414 415 return (used); 416 } 417 418 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 419 420 #define IDXDIFF(head, tail, wrap) \ 421 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 422 423 struct iflib_rxq { 424 if_ctx_t ifr_ctx; 425 iflib_fl_t ifr_fl; 426 uint64_t ifr_rx_irq; 427 struct pfil_head *pfil; 428 /* 429 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 430 * the command queue consumer index. Otherwise it's unused. 431 */ 432 qidx_t ifr_cq_cidx; 433 uint16_t ifr_id; 434 uint8_t ifr_nfl; 435 uint8_t ifr_ntxqirq; 436 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 437 uint8_t ifr_fl_offset; 438 struct lro_ctrl ifr_lc; 439 struct grouptask ifr_task; 440 struct callout ifr_watchdog; 441 struct iflib_filter_info ifr_filter_info; 442 iflib_dma_info_t ifr_ifdi; 443 444 /* dynamically allocate if any drivers need a value substantially larger than this */ 445 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 446 #ifdef IFLIB_DIAGNOSTICS 447 uint64_t ifr_cpu_exec_count[256]; 448 #endif 449 } __aligned(CACHE_LINE_SIZE); 450 451 typedef struct if_rxsd { 452 caddr_t *ifsd_cl; 453 iflib_fl_t ifsd_fl; 454 } *if_rxsd_t; 455 456 /* multiple of word size */ 457 #ifdef __LP64__ 458 #define PKT_INFO_SIZE 6 459 #define RXD_INFO_SIZE 5 460 #define PKT_TYPE uint64_t 461 #else 462 #define PKT_INFO_SIZE 11 463 #define RXD_INFO_SIZE 8 464 #define PKT_TYPE uint32_t 465 #endif 466 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 467 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 468 469 typedef struct if_pkt_info_pad { 470 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 471 } *if_pkt_info_pad_t; 472 typedef struct if_rxd_info_pad { 473 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 474 } *if_rxd_info_pad_t; 475 476 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 477 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 478 479 480 static inline void 481 pkt_info_zero(if_pkt_info_t pi) 482 { 483 if_pkt_info_pad_t pi_pad; 484 485 pi_pad = (if_pkt_info_pad_t)pi; 486 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 487 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 488 #ifndef __LP64__ 489 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 490 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 491 #endif 492 } 493 494 static device_method_t iflib_pseudo_methods[] = { 495 DEVMETHOD(device_attach, noop_attach), 496 DEVMETHOD(device_detach, iflib_pseudo_detach), 497 DEVMETHOD_END 498 }; 499 500 driver_t iflib_pseudodriver = { 501 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 502 }; 503 504 static inline void 505 rxd_info_zero(if_rxd_info_t ri) 506 { 507 if_rxd_info_pad_t ri_pad; 508 int i; 509 510 ri_pad = (if_rxd_info_pad_t)ri; 511 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 512 ri_pad->rxd_val[i] = 0; 513 ri_pad->rxd_val[i+1] = 0; 514 ri_pad->rxd_val[i+2] = 0; 515 ri_pad->rxd_val[i+3] = 0; 516 } 517 #ifdef __LP64__ 518 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 519 #endif 520 } 521 522 /* 523 * Only allow a single packet to take up most 1/nth of the tx ring 524 */ 525 #define MAX_SINGLE_PACKET_FRACTION 12 526 #define IF_BAD_DMA (bus_addr_t)-1 527 528 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 529 530 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 531 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 532 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 533 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 534 535 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 536 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 537 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 538 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 539 540 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 541 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 542 543 void 544 iflib_set_detach(if_ctx_t ctx) 545 { 546 STATE_LOCK(ctx); 547 ctx->ifc_flags |= IFC_IN_DETACH; 548 STATE_UNLOCK(ctx); 549 } 550 551 /* Our boot-time initialization hook */ 552 static int iflib_module_event_handler(module_t, int, void *); 553 554 static moduledata_t iflib_moduledata = { 555 "iflib", 556 iflib_module_event_handler, 557 NULL 558 }; 559 560 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 561 MODULE_VERSION(iflib, 1); 562 563 MODULE_DEPEND(iflib, pci, 1, 1, 1); 564 MODULE_DEPEND(iflib, ether, 1, 1, 1); 565 566 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 567 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 568 569 #ifndef IFLIB_DEBUG_COUNTERS 570 #ifdef INVARIANTS 571 #define IFLIB_DEBUG_COUNTERS 1 572 #else 573 #define IFLIB_DEBUG_COUNTERS 0 574 #endif /* !INVARIANTS */ 575 #endif 576 577 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 578 "iflib driver parameters"); 579 580 /* 581 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 582 */ 583 static int iflib_min_tx_latency = 0; 584 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 585 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 586 static int iflib_no_tx_batch = 0; 587 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 588 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 589 590 591 #if IFLIB_DEBUG_COUNTERS 592 593 static int iflib_tx_seen; 594 static int iflib_tx_sent; 595 static int iflib_tx_encap; 596 static int iflib_rx_allocs; 597 static int iflib_fl_refills; 598 static int iflib_fl_refills_large; 599 static int iflib_tx_frees; 600 601 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 602 &iflib_tx_seen, 0, "# TX mbufs seen"); 603 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 604 &iflib_tx_sent, 0, "# TX mbufs sent"); 605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 606 &iflib_tx_encap, 0, "# TX mbufs encapped"); 607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 608 &iflib_tx_frees, 0, "# TX frees"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 610 &iflib_rx_allocs, 0, "# RX allocations"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 612 &iflib_fl_refills, 0, "# refills"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 614 &iflib_fl_refills_large, 0, "# large refills"); 615 616 617 static int iflib_txq_drain_flushing; 618 static int iflib_txq_drain_oactive; 619 static int iflib_txq_drain_notready; 620 621 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 622 &iflib_txq_drain_flushing, 0, "# drain flushes"); 623 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 624 &iflib_txq_drain_oactive, 0, "# drain oactives"); 625 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 626 &iflib_txq_drain_notready, 0, "# drain notready"); 627 628 629 static int iflib_encap_load_mbuf_fail; 630 static int iflib_encap_pad_mbuf_fail; 631 static int iflib_encap_txq_avail_fail; 632 static int iflib_encap_txd_encap_fail; 633 634 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 635 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 637 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 638 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 639 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 640 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 641 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 642 643 static int iflib_task_fn_rxs; 644 static int iflib_rx_intr_enables; 645 static int iflib_fast_intrs; 646 static int iflib_rx_unavail; 647 static int iflib_rx_ctx_inactive; 648 static int iflib_rx_if_input; 649 static int iflib_rxd_flush; 650 651 static int iflib_verbose_debug; 652 653 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 654 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 655 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 656 &iflib_rx_intr_enables, 0, "# RX intr enables"); 657 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 658 &iflib_fast_intrs, 0, "# fast_intr calls"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 660 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 662 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 664 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 666 &iflib_rxd_flush, 0, "# times rxd_flush called"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 668 &iflib_verbose_debug, 0, "enable verbose debugging"); 669 670 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 671 static void 672 iflib_debug_reset(void) 673 { 674 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 675 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 676 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 677 iflib_txq_drain_notready = 678 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 679 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 680 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 681 iflib_rx_unavail = 682 iflib_rx_ctx_inactive = iflib_rx_if_input = 683 iflib_rxd_flush = 0; 684 } 685 686 #else 687 #define DBG_COUNTER_INC(name) 688 static void iflib_debug_reset(void) {} 689 #endif 690 691 #define IFLIB_DEBUG 0 692 693 static void iflib_tx_structures_free(if_ctx_t ctx); 694 static void iflib_rx_structures_free(if_ctx_t ctx); 695 static int iflib_queues_alloc(if_ctx_t ctx); 696 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 697 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 698 static int iflib_qset_structures_setup(if_ctx_t ctx); 699 static int iflib_msix_init(if_ctx_t ctx); 700 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 701 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 702 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 703 #ifdef ALTQ 704 static void iflib_altq_if_start(if_t ifp); 705 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 706 #endif 707 static int iflib_register(if_ctx_t); 708 static void iflib_deregister(if_ctx_t); 709 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 710 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 711 static void iflib_init_locked(if_ctx_t ctx); 712 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 713 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 714 static void iflib_ifmp_purge(iflib_txq_t txq); 715 static void _iflib_pre_assert(if_softc_ctx_t scctx); 716 static void iflib_if_init_locked(if_ctx_t ctx); 717 static void iflib_free_intr_mem(if_ctx_t ctx); 718 #ifndef __NO_STRICT_ALIGNMENT 719 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 720 #endif 721 722 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 723 SLIST_HEAD_INITIALIZER(cpu_offsets); 724 struct cpu_offset { 725 SLIST_ENTRY(cpu_offset) entries; 726 cpuset_t set; 727 unsigned int refcount; 728 uint16_t offset; 729 }; 730 static struct mtx cpu_offset_mtx; 731 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 732 MTX_DEF); 733 734 DEBUGNET_DEFINE(iflib); 735 736 #ifdef DEV_NETMAP 737 #include <sys/selinfo.h> 738 #include <net/netmap.h> 739 #include <dev/netmap/netmap_kern.h> 740 741 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 742 743 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 744 745 /* 746 * device-specific sysctl variables: 747 * 748 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 749 * During regular operations the CRC is stripped, but on some 750 * hardware reception of frames not multiple of 64 is slower, 751 * so using crcstrip=0 helps in benchmarks. 752 * 753 * iflib_rx_miss, iflib_rx_miss_bufs: 754 * count packets that might be missed due to lost interrupts. 755 */ 756 SYSCTL_DECL(_dev_netmap); 757 /* 758 * The xl driver by default strips CRCs and we do not override it. 759 */ 760 761 int iflib_crcstrip = 1; 762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 763 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 764 765 int iflib_rx_miss, iflib_rx_miss_bufs; 766 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 767 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 768 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 769 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 770 771 /* 772 * Register/unregister. We are already under netmap lock. 773 * Only called on the first register or the last unregister. 774 */ 775 static int 776 iflib_netmap_register(struct netmap_adapter *na, int onoff) 777 { 778 if_t ifp = na->ifp; 779 if_ctx_t ctx = ifp->if_softc; 780 int status; 781 782 CTX_LOCK(ctx); 783 IFDI_INTR_DISABLE(ctx); 784 785 /* Tell the stack that the interface is no longer active */ 786 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 787 788 if (!CTX_IS_VF(ctx)) 789 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 790 791 iflib_stop(ctx); 792 793 /* 794 * Enable (or disable) netmap flags, and intercept (or restore) 795 * ifp->if_transmit. This is done once the device has been stopped 796 * to prevent race conditions. 797 */ 798 if (onoff) { 799 nm_set_native_flags(na); 800 } else { 801 nm_clear_native_flags(na); 802 } 803 804 iflib_init_locked(ctx); 805 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 806 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 807 if (status) 808 nm_clear_native_flags(na); 809 CTX_UNLOCK(ctx); 810 return (status); 811 } 812 813 static int 814 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 815 { 816 struct netmap_adapter *na = kring->na; 817 u_int const lim = kring->nkr_num_slots - 1; 818 u_int head = kring->rhead; 819 struct netmap_ring *ring = kring->ring; 820 bus_dmamap_t *map; 821 struct if_rxd_update iru; 822 if_ctx_t ctx = rxq->ifr_ctx; 823 iflib_fl_t fl = &rxq->ifr_fl[0]; 824 uint32_t refill_pidx, nic_i; 825 #if IFLIB_DEBUG_COUNTERS 826 int rf_count = 0; 827 #endif 828 829 if (nm_i == head && __predict_true(!init)) 830 return 0; 831 iru_init(&iru, rxq, 0 /* flid */); 832 map = fl->ifl_sds.ifsd_map; 833 refill_pidx = netmap_idx_k2n(kring, nm_i); 834 /* 835 * IMPORTANT: we must leave one free slot in the ring, 836 * so move head back by one unit 837 */ 838 head = nm_prev(head, lim); 839 nic_i = UINT_MAX; 840 DBG_COUNTER_INC(fl_refills); 841 while (nm_i != head) { 842 #if IFLIB_DEBUG_COUNTERS 843 if (++rf_count == 9) 844 DBG_COUNTER_INC(fl_refills_large); 845 #endif 846 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 847 struct netmap_slot *slot = &ring->slot[nm_i]; 848 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 849 uint32_t nic_i_dma = refill_pidx; 850 nic_i = netmap_idx_k2n(kring, nm_i); 851 852 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 853 854 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 855 return netmap_ring_reinit(kring); 856 857 fl->ifl_vm_addrs[tmp_pidx] = addr; 858 if (__predict_false(init)) { 859 netmap_load_map(na, fl->ifl_buf_tag, 860 map[nic_i], addr); 861 } else if (slot->flags & NS_BUF_CHANGED) { 862 /* buffer has changed, reload map */ 863 netmap_reload_map(na, fl->ifl_buf_tag, 864 map[nic_i], addr); 865 } 866 slot->flags &= ~NS_BUF_CHANGED; 867 868 nm_i = nm_next(nm_i, lim); 869 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 870 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 871 continue; 872 873 iru.iru_pidx = refill_pidx; 874 iru.iru_count = tmp_pidx+1; 875 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 876 refill_pidx = nic_i; 877 for (int n = 0; n < iru.iru_count; n++) { 878 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma], 879 BUS_DMASYNC_PREREAD); 880 /* XXX - change this to not use the netmap func*/ 881 nic_i_dma = nm_next(nic_i_dma, lim); 882 } 883 } 884 } 885 kring->nr_hwcur = head; 886 887 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 888 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 889 if (__predict_true(nic_i != UINT_MAX)) { 890 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 891 DBG_COUNTER_INC(rxd_flush); 892 } 893 return (0); 894 } 895 896 /* 897 * Reconcile kernel and user view of the transmit ring. 898 * 899 * All information is in the kring. 900 * Userspace wants to send packets up to the one before kring->rhead, 901 * kernel knows kring->nr_hwcur is the first unsent packet. 902 * 903 * Here we push packets out (as many as possible), and possibly 904 * reclaim buffers from previously completed transmission. 905 * 906 * The caller (netmap) guarantees that there is only one instance 907 * running at any time. Any interference with other driver 908 * methods should be handled by the individual drivers. 909 */ 910 static int 911 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 912 { 913 struct netmap_adapter *na = kring->na; 914 if_t ifp = na->ifp; 915 struct netmap_ring *ring = kring->ring; 916 u_int nm_i; /* index into the netmap kring */ 917 u_int nic_i; /* index into the NIC ring */ 918 u_int n; 919 u_int const lim = kring->nkr_num_slots - 1; 920 u_int const head = kring->rhead; 921 struct if_pkt_info pi; 922 923 /* 924 * interrupts on every tx packet are expensive so request 925 * them every half ring, or where NS_REPORT is set 926 */ 927 u_int report_frequency = kring->nkr_num_slots >> 1; 928 /* device-specific */ 929 if_ctx_t ctx = ifp->if_softc; 930 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 931 932 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 933 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 934 935 /* 936 * First part: process new packets to send. 937 * nm_i is the current index in the netmap kring, 938 * nic_i is the corresponding index in the NIC ring. 939 * 940 * If we have packets to send (nm_i != head) 941 * iterate over the netmap ring, fetch length and update 942 * the corresponding slot in the NIC ring. Some drivers also 943 * need to update the buffer's physical address in the NIC slot 944 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 945 * 946 * The netmap_reload_map() calls is especially expensive, 947 * even when (as in this case) the tag is 0, so do only 948 * when the buffer has actually changed. 949 * 950 * If possible do not set the report/intr bit on all slots, 951 * but only a few times per ring or when NS_REPORT is set. 952 * 953 * Finally, on 10G and faster drivers, it might be useful 954 * to prefetch the next slot and txr entry. 955 */ 956 957 nm_i = kring->nr_hwcur; 958 if (nm_i != head) { /* we have new packets to send */ 959 pkt_info_zero(&pi); 960 pi.ipi_segs = txq->ift_segs; 961 pi.ipi_qsidx = kring->ring_id; 962 nic_i = netmap_idx_k2n(kring, nm_i); 963 964 __builtin_prefetch(&ring->slot[nm_i]); 965 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 966 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 967 968 for (n = 0; nm_i != head; n++) { 969 struct netmap_slot *slot = &ring->slot[nm_i]; 970 u_int len = slot->len; 971 uint64_t paddr; 972 void *addr = PNMB(na, slot, &paddr); 973 int flags = (slot->flags & NS_REPORT || 974 nic_i == 0 || nic_i == report_frequency) ? 975 IPI_TX_INTR : 0; 976 977 /* device-specific */ 978 pi.ipi_len = len; 979 pi.ipi_segs[0].ds_addr = paddr; 980 pi.ipi_segs[0].ds_len = len; 981 pi.ipi_nsegs = 1; 982 pi.ipi_ndescs = 0; 983 pi.ipi_pidx = nic_i; 984 pi.ipi_flags = flags; 985 986 /* Fill the slot in the NIC ring. */ 987 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 988 DBG_COUNTER_INC(tx_encap); 989 990 /* prefetch for next round */ 991 __builtin_prefetch(&ring->slot[nm_i + 1]); 992 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 993 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 994 995 NM_CHECK_ADDR_LEN(na, addr, len); 996 997 if (slot->flags & NS_BUF_CHANGED) { 998 /* buffer has changed, reload map */ 999 netmap_reload_map(na, txq->ift_buf_tag, 1000 txq->ift_sds.ifsd_map[nic_i], addr); 1001 } 1002 /* make sure changes to the buffer are synced */ 1003 bus_dmamap_sync(txq->ift_buf_tag, 1004 txq->ift_sds.ifsd_map[nic_i], 1005 BUS_DMASYNC_PREWRITE); 1006 1007 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1008 nm_i = nm_next(nm_i, lim); 1009 nic_i = nm_next(nic_i, lim); 1010 } 1011 kring->nr_hwcur = nm_i; 1012 1013 /* synchronize the NIC ring */ 1014 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1015 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1016 1017 /* (re)start the tx unit up to slot nic_i (excluded) */ 1018 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1019 } 1020 1021 /* 1022 * Second part: reclaim buffers for completed transmissions. 1023 * 1024 * If there are unclaimed buffers, attempt to reclaim them. 1025 * If none are reclaimed, and TX IRQs are not in use, do an initial 1026 * minimal delay, then trigger the tx handler which will spin in the 1027 * group task queue. 1028 */ 1029 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1030 if (iflib_tx_credits_update(ctx, txq)) { 1031 /* some tx completed, increment avail */ 1032 nic_i = txq->ift_cidx_processed; 1033 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1034 } 1035 } 1036 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1037 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1038 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1039 iflib_timer, txq, txq->ift_timer.c_cpu); 1040 } 1041 return (0); 1042 } 1043 1044 /* 1045 * Reconcile kernel and user view of the receive ring. 1046 * Same as for the txsync, this routine must be efficient. 1047 * The caller guarantees a single invocations, but races against 1048 * the rest of the driver should be handled here. 1049 * 1050 * On call, kring->rhead is the first packet that userspace wants 1051 * to keep, and kring->rcur is the wakeup point. 1052 * The kernel has previously reported packets up to kring->rtail. 1053 * 1054 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1055 * of whether or not we received an interrupt. 1056 */ 1057 static int 1058 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1059 { 1060 struct netmap_adapter *na = kring->na; 1061 struct netmap_ring *ring = kring->ring; 1062 if_t ifp = na->ifp; 1063 iflib_fl_t fl; 1064 uint32_t nm_i; /* index into the netmap ring */ 1065 uint32_t nic_i; /* index into the NIC ring */ 1066 u_int i, n; 1067 u_int const lim = kring->nkr_num_slots - 1; 1068 u_int const head = kring->rhead; 1069 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1070 struct if_rxd_info ri; 1071 1072 if_ctx_t ctx = ifp->if_softc; 1073 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1074 if (head > lim) 1075 return netmap_ring_reinit(kring); 1076 1077 /* 1078 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far. 1079 */ 1080 1081 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1082 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1083 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1084 } 1085 1086 /* 1087 * First part: import newly received packets. 1088 * 1089 * nm_i is the index of the next free slot in the netmap ring, 1090 * nic_i is the index of the next received packet in the NIC ring, 1091 * and they may differ in case if_init() has been called while 1092 * in netmap mode. For the receive ring we have 1093 * 1094 * nic_i = rxr->next_check; 1095 * nm_i = kring->nr_hwtail (previous) 1096 * and 1097 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1098 * 1099 * rxr->next_check is set to 0 on a ring reinit 1100 */ 1101 if (netmap_no_pendintr || force_update) { 1102 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1103 int crclen = iflib_crcstrip ? 0 : 4; 1104 int error, avail; 1105 1106 for (i = 0; i < rxq->ifr_nfl; i++) { 1107 fl = &rxq->ifr_fl[i]; 1108 nic_i = fl->ifl_cidx; 1109 nm_i = netmap_idx_n2k(kring, nic_i); 1110 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1111 rxq->ifr_id, nic_i, USHRT_MAX); 1112 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1113 rxd_info_zero(&ri); 1114 ri.iri_frags = rxq->ifr_frags; 1115 ri.iri_qsidx = kring->ring_id; 1116 ri.iri_ifp = ctx->ifc_ifp; 1117 ri.iri_cidx = nic_i; 1118 1119 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1120 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1121 ring->slot[nm_i].flags = 0; 1122 bus_dmamap_sync(fl->ifl_buf_tag, 1123 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1124 nm_i = nm_next(nm_i, lim); 1125 nic_i = nm_next(nic_i, lim); 1126 } 1127 if (n) { /* update the state variables */ 1128 if (netmap_no_pendintr && !force_update) { 1129 /* diagnostics */ 1130 iflib_rx_miss ++; 1131 iflib_rx_miss_bufs += n; 1132 } 1133 fl->ifl_cidx = nic_i; 1134 kring->nr_hwtail = nm_i; 1135 } 1136 kring->nr_kflags &= ~NKR_PENDINTR; 1137 } 1138 } 1139 /* 1140 * Second part: skip past packets that userspace has released. 1141 * (kring->nr_hwcur to head excluded), 1142 * and make the buffers available for reception. 1143 * As usual nm_i is the index in the netmap ring, 1144 * nic_i is the index in the NIC ring, and 1145 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1146 */ 1147 /* XXX not sure how this will work with multiple free lists */ 1148 nm_i = kring->nr_hwcur; 1149 1150 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1151 } 1152 1153 static void 1154 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1155 { 1156 if_ctx_t ctx = na->ifp->if_softc; 1157 1158 CTX_LOCK(ctx); 1159 if (onoff) { 1160 IFDI_INTR_ENABLE(ctx); 1161 } else { 1162 IFDI_INTR_DISABLE(ctx); 1163 } 1164 CTX_UNLOCK(ctx); 1165 } 1166 1167 1168 static int 1169 iflib_netmap_attach(if_ctx_t ctx) 1170 { 1171 struct netmap_adapter na; 1172 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1173 1174 bzero(&na, sizeof(na)); 1175 1176 na.ifp = ctx->ifc_ifp; 1177 na.na_flags = NAF_BDG_MAYSLEEP; 1178 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1179 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1180 1181 na.num_tx_desc = scctx->isc_ntxd[0]; 1182 na.num_rx_desc = scctx->isc_nrxd[0]; 1183 na.nm_txsync = iflib_netmap_txsync; 1184 na.nm_rxsync = iflib_netmap_rxsync; 1185 na.nm_register = iflib_netmap_register; 1186 na.nm_intr = iflib_netmap_intr; 1187 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1188 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1189 return (netmap_attach(&na)); 1190 } 1191 1192 static void 1193 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1194 { 1195 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1196 struct netmap_slot *slot; 1197 1198 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1199 if (slot == NULL) 1200 return; 1201 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1202 1203 /* 1204 * In netmap mode, set the map for the packet buffer. 1205 * NOTE: Some drivers (not this one) also need to set 1206 * the physical buffer address in the NIC ring. 1207 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1208 * netmap slot index, si 1209 */ 1210 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1211 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1212 NMB(na, slot + si)); 1213 } 1214 } 1215 1216 static void 1217 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1218 { 1219 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1220 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1221 struct netmap_slot *slot; 1222 uint32_t nm_i; 1223 1224 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1225 if (slot == NULL) 1226 return; 1227 nm_i = netmap_idx_n2k(kring, 0); 1228 netmap_fl_refill(rxq, kring, nm_i, true); 1229 } 1230 1231 static void 1232 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on) 1233 { 1234 struct netmap_kring *kring; 1235 uint16_t txqid; 1236 1237 txqid = txq->ift_id; 1238 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1239 1240 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1241 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1242 BUS_DMASYNC_POSTREAD); 1243 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1244 netmap_tx_irq(ctx->ifc_ifp, txqid); 1245 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1246 if (hz < 2000) 1247 *reset_on = 1; 1248 else 1249 *reset_on = hz / 1000; 1250 } 1251 } 1252 } 1253 1254 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1255 1256 #else 1257 #define iflib_netmap_txq_init(ctx, txq) 1258 #define iflib_netmap_rxq_init(ctx, rxq) 1259 #define iflib_netmap_detach(ifp) 1260 1261 #define iflib_netmap_attach(ctx) (0) 1262 #define netmap_rx_irq(ifp, qid, budget) (0) 1263 #define netmap_tx_irq(ifp, qid) do {} while (0) 1264 #define iflib_netmap_timer_adjust(ctx, txq, reset_on) 1265 #endif 1266 1267 #if defined(__i386__) || defined(__amd64__) 1268 static __inline void 1269 prefetch(void *x) 1270 { 1271 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1272 } 1273 static __inline void 1274 prefetch2cachelines(void *x) 1275 { 1276 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1277 #if (CACHE_LINE_SIZE < 128) 1278 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1279 #endif 1280 } 1281 #else 1282 #define prefetch(x) 1283 #define prefetch2cachelines(x) 1284 #endif 1285 1286 static void 1287 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1288 { 1289 iflib_fl_t fl; 1290 1291 fl = &rxq->ifr_fl[flid]; 1292 iru->iru_paddrs = fl->ifl_bus_addrs; 1293 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1294 iru->iru_idxs = fl->ifl_rxd_idxs; 1295 iru->iru_qsidx = rxq->ifr_id; 1296 iru->iru_buf_size = fl->ifl_buf_size; 1297 iru->iru_flidx = fl->ifl_id; 1298 } 1299 1300 static void 1301 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1302 { 1303 if (err) 1304 return; 1305 *(bus_addr_t *) arg = segs[0].ds_addr; 1306 } 1307 1308 int 1309 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1310 { 1311 int err; 1312 device_t dev = ctx->ifc_dev; 1313 1314 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1315 align, 0, /* alignment, bounds */ 1316 BUS_SPACE_MAXADDR, /* lowaddr */ 1317 BUS_SPACE_MAXADDR, /* highaddr */ 1318 NULL, NULL, /* filter, filterarg */ 1319 size, /* maxsize */ 1320 1, /* nsegments */ 1321 size, /* maxsegsize */ 1322 BUS_DMA_ALLOCNOW, /* flags */ 1323 NULL, /* lockfunc */ 1324 NULL, /* lockarg */ 1325 &dma->idi_tag); 1326 if (err) { 1327 device_printf(dev, 1328 "%s: bus_dma_tag_create failed: %d\n", 1329 __func__, err); 1330 goto fail_0; 1331 } 1332 1333 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1334 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1335 if (err) { 1336 device_printf(dev, 1337 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1338 __func__, (uintmax_t)size, err); 1339 goto fail_1; 1340 } 1341 1342 dma->idi_paddr = IF_BAD_DMA; 1343 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1344 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1345 if (err || dma->idi_paddr == IF_BAD_DMA) { 1346 device_printf(dev, 1347 "%s: bus_dmamap_load failed: %d\n", 1348 __func__, err); 1349 goto fail_2; 1350 } 1351 1352 dma->idi_size = size; 1353 return (0); 1354 1355 fail_2: 1356 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1357 fail_1: 1358 bus_dma_tag_destroy(dma->idi_tag); 1359 fail_0: 1360 dma->idi_tag = NULL; 1361 1362 return (err); 1363 } 1364 1365 int 1366 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1367 { 1368 if_shared_ctx_t sctx = ctx->ifc_sctx; 1369 1370 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1371 1372 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1373 } 1374 1375 int 1376 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1377 { 1378 int i, err; 1379 iflib_dma_info_t *dmaiter; 1380 1381 dmaiter = dmalist; 1382 for (i = 0; i < count; i++, dmaiter++) { 1383 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1384 break; 1385 } 1386 if (err) 1387 iflib_dma_free_multi(dmalist, i); 1388 return (err); 1389 } 1390 1391 void 1392 iflib_dma_free(iflib_dma_info_t dma) 1393 { 1394 if (dma->idi_tag == NULL) 1395 return; 1396 if (dma->idi_paddr != IF_BAD_DMA) { 1397 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1398 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1399 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1400 dma->idi_paddr = IF_BAD_DMA; 1401 } 1402 if (dma->idi_vaddr != NULL) { 1403 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1404 dma->idi_vaddr = NULL; 1405 } 1406 bus_dma_tag_destroy(dma->idi_tag); 1407 dma->idi_tag = NULL; 1408 } 1409 1410 void 1411 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1412 { 1413 int i; 1414 iflib_dma_info_t *dmaiter = dmalist; 1415 1416 for (i = 0; i < count; i++, dmaiter++) 1417 iflib_dma_free(*dmaiter); 1418 } 1419 1420 static int 1421 iflib_fast_intr(void *arg) 1422 { 1423 iflib_filter_info_t info = arg; 1424 struct grouptask *gtask = info->ifi_task; 1425 int result; 1426 1427 DBG_COUNTER_INC(fast_intrs); 1428 if (info->ifi_filter != NULL) { 1429 result = info->ifi_filter(info->ifi_filter_arg); 1430 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1431 return (result); 1432 } 1433 1434 GROUPTASK_ENQUEUE(gtask); 1435 return (FILTER_HANDLED); 1436 } 1437 1438 static int 1439 iflib_fast_intr_rxtx(void *arg) 1440 { 1441 iflib_filter_info_t info = arg; 1442 struct grouptask *gtask = info->ifi_task; 1443 if_ctx_t ctx; 1444 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1445 iflib_txq_t txq; 1446 void *sc; 1447 int i, cidx, result; 1448 qidx_t txqid; 1449 bool intr_enable, intr_legacy; 1450 1451 DBG_COUNTER_INC(fast_intrs); 1452 if (info->ifi_filter != NULL) { 1453 result = info->ifi_filter(info->ifi_filter_arg); 1454 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1455 return (result); 1456 } 1457 1458 ctx = rxq->ifr_ctx; 1459 sc = ctx->ifc_softc; 1460 intr_enable = false; 1461 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1462 MPASS(rxq->ifr_ntxqirq); 1463 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1464 txqid = rxq->ifr_txqid[i]; 1465 txq = &ctx->ifc_txqs[txqid]; 1466 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1467 BUS_DMASYNC_POSTREAD); 1468 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1469 if (intr_legacy) 1470 intr_enable = true; 1471 else 1472 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1473 continue; 1474 } 1475 GROUPTASK_ENQUEUE(&txq->ift_task); 1476 } 1477 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1478 cidx = rxq->ifr_cq_cidx; 1479 else 1480 cidx = rxq->ifr_fl[0].ifl_cidx; 1481 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1482 GROUPTASK_ENQUEUE(gtask); 1483 else { 1484 if (intr_legacy) 1485 intr_enable = true; 1486 else 1487 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1488 DBG_COUNTER_INC(rx_intr_enables); 1489 } 1490 if (intr_enable) 1491 IFDI_INTR_ENABLE(ctx); 1492 return (FILTER_HANDLED); 1493 } 1494 1495 1496 static int 1497 iflib_fast_intr_ctx(void *arg) 1498 { 1499 iflib_filter_info_t info = arg; 1500 struct grouptask *gtask = info->ifi_task; 1501 int result; 1502 1503 DBG_COUNTER_INC(fast_intrs); 1504 if (info->ifi_filter != NULL) { 1505 result = info->ifi_filter(info->ifi_filter_arg); 1506 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1507 return (result); 1508 } 1509 1510 GROUPTASK_ENQUEUE(gtask); 1511 return (FILTER_HANDLED); 1512 } 1513 1514 static int 1515 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1516 driver_filter_t filter, driver_intr_t handler, void *arg, 1517 const char *name) 1518 { 1519 struct resource *res; 1520 void *tag = NULL; 1521 device_t dev = ctx->ifc_dev; 1522 int flags, i, rc; 1523 1524 flags = RF_ACTIVE; 1525 if (ctx->ifc_flags & IFC_LEGACY) 1526 flags |= RF_SHAREABLE; 1527 MPASS(rid < 512); 1528 i = rid; 1529 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1530 if (res == NULL) { 1531 device_printf(dev, 1532 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1533 return (ENOMEM); 1534 } 1535 irq->ii_res = res; 1536 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1537 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1538 filter, handler, arg, &tag); 1539 if (rc != 0) { 1540 device_printf(dev, 1541 "failed to setup interrupt for rid %d, name %s: %d\n", 1542 rid, name ? name : "unknown", rc); 1543 return (rc); 1544 } else if (name) 1545 bus_describe_intr(dev, res, tag, "%s", name); 1546 1547 irq->ii_tag = tag; 1548 return (0); 1549 } 1550 1551 /********************************************************************* 1552 * 1553 * Allocate DMA resources for TX buffers as well as memory for the TX 1554 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1555 * iflib_sw_tx_desc_array structure, storing all the information that 1556 * is needed to transmit a packet on the wire. This is called only 1557 * once at attach, setup is done every reset. 1558 * 1559 **********************************************************************/ 1560 static int 1561 iflib_txsd_alloc(iflib_txq_t txq) 1562 { 1563 if_ctx_t ctx = txq->ift_ctx; 1564 if_shared_ctx_t sctx = ctx->ifc_sctx; 1565 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1566 device_t dev = ctx->ifc_dev; 1567 bus_size_t tsomaxsize; 1568 int err, nsegments, ntsosegments; 1569 bool tso; 1570 1571 nsegments = scctx->isc_tx_nsegments; 1572 ntsosegments = scctx->isc_tx_tso_segments_max; 1573 tsomaxsize = scctx->isc_tx_tso_size_max; 1574 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1575 tsomaxsize += sizeof(struct ether_vlan_header); 1576 MPASS(scctx->isc_ntxd[0] > 0); 1577 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1578 MPASS(nsegments > 0); 1579 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1580 MPASS(ntsosegments > 0); 1581 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1582 } 1583 1584 /* 1585 * Set up DMA tags for TX buffers. 1586 */ 1587 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1588 1, 0, /* alignment, bounds */ 1589 BUS_SPACE_MAXADDR, /* lowaddr */ 1590 BUS_SPACE_MAXADDR, /* highaddr */ 1591 NULL, NULL, /* filter, filterarg */ 1592 sctx->isc_tx_maxsize, /* maxsize */ 1593 nsegments, /* nsegments */ 1594 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1595 0, /* flags */ 1596 NULL, /* lockfunc */ 1597 NULL, /* lockfuncarg */ 1598 &txq->ift_buf_tag))) { 1599 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1600 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1601 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1602 goto fail; 1603 } 1604 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1605 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1606 1, 0, /* alignment, bounds */ 1607 BUS_SPACE_MAXADDR, /* lowaddr */ 1608 BUS_SPACE_MAXADDR, /* highaddr */ 1609 NULL, NULL, /* filter, filterarg */ 1610 tsomaxsize, /* maxsize */ 1611 ntsosegments, /* nsegments */ 1612 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1613 0, /* flags */ 1614 NULL, /* lockfunc */ 1615 NULL, /* lockfuncarg */ 1616 &txq->ift_tso_buf_tag))) { 1617 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1618 err); 1619 goto fail; 1620 } 1621 1622 /* Allocate memory for the TX mbuf map. */ 1623 if (!(txq->ift_sds.ifsd_m = 1624 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1625 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1626 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1627 err = ENOMEM; 1628 goto fail; 1629 } 1630 1631 /* 1632 * Create the DMA maps for TX buffers. 1633 */ 1634 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1635 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1636 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1637 device_printf(dev, 1638 "Unable to allocate TX buffer DMA map memory\n"); 1639 err = ENOMEM; 1640 goto fail; 1641 } 1642 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1643 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1644 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1645 device_printf(dev, 1646 "Unable to allocate TSO TX buffer map memory\n"); 1647 err = ENOMEM; 1648 goto fail; 1649 } 1650 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1651 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1652 &txq->ift_sds.ifsd_map[i]); 1653 if (err != 0) { 1654 device_printf(dev, "Unable to create TX DMA map\n"); 1655 goto fail; 1656 } 1657 if (!tso) 1658 continue; 1659 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1660 &txq->ift_sds.ifsd_tso_map[i]); 1661 if (err != 0) { 1662 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1663 goto fail; 1664 } 1665 } 1666 return (0); 1667 fail: 1668 /* We free all, it handles case where we are in the middle */ 1669 iflib_tx_structures_free(ctx); 1670 return (err); 1671 } 1672 1673 static void 1674 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1675 { 1676 bus_dmamap_t map; 1677 1678 if (txq->ift_sds.ifsd_map != NULL) { 1679 map = txq->ift_sds.ifsd_map[i]; 1680 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1681 bus_dmamap_unload(txq->ift_buf_tag, map); 1682 bus_dmamap_destroy(txq->ift_buf_tag, map); 1683 txq->ift_sds.ifsd_map[i] = NULL; 1684 } 1685 1686 if (txq->ift_sds.ifsd_tso_map != NULL) { 1687 map = txq->ift_sds.ifsd_tso_map[i]; 1688 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1689 BUS_DMASYNC_POSTWRITE); 1690 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1691 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1692 txq->ift_sds.ifsd_tso_map[i] = NULL; 1693 } 1694 } 1695 1696 static void 1697 iflib_txq_destroy(iflib_txq_t txq) 1698 { 1699 if_ctx_t ctx = txq->ift_ctx; 1700 1701 for (int i = 0; i < txq->ift_size; i++) 1702 iflib_txsd_destroy(ctx, txq, i); 1703 1704 if (txq->ift_br != NULL) { 1705 ifmp_ring_free(txq->ift_br); 1706 txq->ift_br = NULL; 1707 } 1708 1709 mtx_destroy(&txq->ift_mtx); 1710 1711 if (txq->ift_sds.ifsd_map != NULL) { 1712 free(txq->ift_sds.ifsd_map, M_IFLIB); 1713 txq->ift_sds.ifsd_map = NULL; 1714 } 1715 if (txq->ift_sds.ifsd_tso_map != NULL) { 1716 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1717 txq->ift_sds.ifsd_tso_map = NULL; 1718 } 1719 if (txq->ift_sds.ifsd_m != NULL) { 1720 free(txq->ift_sds.ifsd_m, M_IFLIB); 1721 txq->ift_sds.ifsd_m = NULL; 1722 } 1723 if (txq->ift_buf_tag != NULL) { 1724 bus_dma_tag_destroy(txq->ift_buf_tag); 1725 txq->ift_buf_tag = NULL; 1726 } 1727 if (txq->ift_tso_buf_tag != NULL) { 1728 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1729 txq->ift_tso_buf_tag = NULL; 1730 } 1731 if (txq->ift_ifdi != NULL) { 1732 free(txq->ift_ifdi, M_IFLIB); 1733 } 1734 } 1735 1736 static void 1737 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1738 { 1739 struct mbuf **mp; 1740 1741 mp = &txq->ift_sds.ifsd_m[i]; 1742 if (*mp == NULL) 1743 return; 1744 1745 if (txq->ift_sds.ifsd_map != NULL) { 1746 bus_dmamap_sync(txq->ift_buf_tag, 1747 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1748 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1749 } 1750 if (txq->ift_sds.ifsd_tso_map != NULL) { 1751 bus_dmamap_sync(txq->ift_tso_buf_tag, 1752 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1753 bus_dmamap_unload(txq->ift_tso_buf_tag, 1754 txq->ift_sds.ifsd_tso_map[i]); 1755 } 1756 m_free(*mp); 1757 DBG_COUNTER_INC(tx_frees); 1758 *mp = NULL; 1759 } 1760 1761 static int 1762 iflib_txq_setup(iflib_txq_t txq) 1763 { 1764 if_ctx_t ctx = txq->ift_ctx; 1765 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1766 if_shared_ctx_t sctx = ctx->ifc_sctx; 1767 iflib_dma_info_t di; 1768 int i; 1769 1770 /* Set number of descriptors available */ 1771 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1772 /* XXX make configurable */ 1773 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1774 1775 /* Reset indices */ 1776 txq->ift_cidx_processed = 0; 1777 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1778 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1779 1780 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1781 bzero((void *)di->idi_vaddr, di->idi_size); 1782 1783 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1784 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1785 bus_dmamap_sync(di->idi_tag, di->idi_map, 1786 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1787 return (0); 1788 } 1789 1790 /********************************************************************* 1791 * 1792 * Allocate DMA resources for RX buffers as well as memory for the RX 1793 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1794 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1795 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1796 * Since we use use one entry in iflib_sw_rx_desc_array per received 1797 * packet, the maximum number of entries we'll need is equal to the 1798 * number of hardware receive descriptors that we've allocated. 1799 * 1800 **********************************************************************/ 1801 static int 1802 iflib_rxsd_alloc(iflib_rxq_t rxq) 1803 { 1804 if_ctx_t ctx = rxq->ifr_ctx; 1805 if_shared_ctx_t sctx = ctx->ifc_sctx; 1806 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1807 device_t dev = ctx->ifc_dev; 1808 iflib_fl_t fl; 1809 int err; 1810 1811 MPASS(scctx->isc_nrxd[0] > 0); 1812 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1813 1814 fl = rxq->ifr_fl; 1815 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1816 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1817 /* Set up DMA tag for RX buffers. */ 1818 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1819 1, 0, /* alignment, bounds */ 1820 BUS_SPACE_MAXADDR, /* lowaddr */ 1821 BUS_SPACE_MAXADDR, /* highaddr */ 1822 NULL, NULL, /* filter, filterarg */ 1823 sctx->isc_rx_maxsize, /* maxsize */ 1824 sctx->isc_rx_nsegments, /* nsegments */ 1825 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1826 0, /* flags */ 1827 NULL, /* lockfunc */ 1828 NULL, /* lockarg */ 1829 &fl->ifl_buf_tag); 1830 if (err) { 1831 device_printf(dev, 1832 "Unable to allocate RX DMA tag: %d\n", err); 1833 goto fail; 1834 } 1835 1836 /* Allocate memory for the RX mbuf map. */ 1837 if (!(fl->ifl_sds.ifsd_m = 1838 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1839 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1840 device_printf(dev, 1841 "Unable to allocate RX mbuf map memory\n"); 1842 err = ENOMEM; 1843 goto fail; 1844 } 1845 1846 /* Allocate memory for the direct RX cluster pointer map. */ 1847 if (!(fl->ifl_sds.ifsd_cl = 1848 (caddr_t *) malloc(sizeof(caddr_t) * 1849 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1850 device_printf(dev, 1851 "Unable to allocate RX cluster map memory\n"); 1852 err = ENOMEM; 1853 goto fail; 1854 } 1855 1856 /* Allocate memory for the RX cluster bus address map. */ 1857 if (!(fl->ifl_sds.ifsd_ba = 1858 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1859 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1860 device_printf(dev, 1861 "Unable to allocate RX bus address map memory\n"); 1862 err = ENOMEM; 1863 goto fail; 1864 } 1865 1866 /* 1867 * Create the DMA maps for RX buffers. 1868 */ 1869 if (!(fl->ifl_sds.ifsd_map = 1870 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1871 device_printf(dev, 1872 "Unable to allocate RX buffer DMA map memory\n"); 1873 err = ENOMEM; 1874 goto fail; 1875 } 1876 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1877 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1878 &fl->ifl_sds.ifsd_map[i]); 1879 if (err != 0) { 1880 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1881 goto fail; 1882 } 1883 } 1884 } 1885 return (0); 1886 1887 fail: 1888 iflib_rx_structures_free(ctx); 1889 return (err); 1890 } 1891 1892 1893 /* 1894 * Internal service routines 1895 */ 1896 1897 struct rxq_refill_cb_arg { 1898 int error; 1899 bus_dma_segment_t seg; 1900 int nseg; 1901 }; 1902 1903 static void 1904 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1905 { 1906 struct rxq_refill_cb_arg *cb_arg = arg; 1907 1908 cb_arg->error = error; 1909 cb_arg->seg = segs[0]; 1910 cb_arg->nseg = nseg; 1911 } 1912 1913 /** 1914 * _iflib_fl_refill - refill an rxq free-buffer list 1915 * @ctx: the iflib context 1916 * @fl: the free list to refill 1917 * @count: the number of new buffers to allocate 1918 * 1919 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 1920 * The caller must assure that @count does not exceed the queue's capacity. 1921 */ 1922 static uint8_t 1923 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1924 { 1925 struct if_rxd_update iru; 1926 struct rxq_refill_cb_arg cb_arg; 1927 struct mbuf *m; 1928 caddr_t cl, *sd_cl; 1929 struct mbuf **sd_m; 1930 bus_dmamap_t *sd_map; 1931 bus_addr_t bus_addr, *sd_ba; 1932 int err, frag_idx, i, idx, n, pidx; 1933 qidx_t credits; 1934 1935 sd_m = fl->ifl_sds.ifsd_m; 1936 sd_map = fl->ifl_sds.ifsd_map; 1937 sd_cl = fl->ifl_sds.ifsd_cl; 1938 sd_ba = fl->ifl_sds.ifsd_ba; 1939 pidx = fl->ifl_pidx; 1940 idx = pidx; 1941 frag_idx = fl->ifl_fragidx; 1942 credits = fl->ifl_credits; 1943 1944 i = 0; 1945 n = count; 1946 MPASS(n > 0); 1947 MPASS(credits + n <= fl->ifl_size); 1948 1949 if (pidx < fl->ifl_cidx) 1950 MPASS(pidx + n <= fl->ifl_cidx); 1951 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1952 MPASS(fl->ifl_gen == 0); 1953 if (pidx > fl->ifl_cidx) 1954 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1955 1956 DBG_COUNTER_INC(fl_refills); 1957 if (n > 8) 1958 DBG_COUNTER_INC(fl_refills_large); 1959 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1960 while (n--) { 1961 /* 1962 * We allocate an uninitialized mbuf + cluster, mbuf is 1963 * initialized after rx. 1964 * 1965 * If the cluster is still set then we know a minimum sized packet was received 1966 */ 1967 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 1968 &frag_idx); 1969 if (frag_idx < 0) 1970 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1971 MPASS(frag_idx >= 0); 1972 if ((cl = sd_cl[frag_idx]) == NULL) { 1973 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1974 break; 1975 1976 cb_arg.error = 0; 1977 MPASS(sd_map != NULL); 1978 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 1979 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 1980 BUS_DMA_NOWAIT); 1981 if (err != 0 || cb_arg.error) { 1982 /* 1983 * !zone_pack ? 1984 */ 1985 if (fl->ifl_zone == zone_pack) 1986 uma_zfree(fl->ifl_zone, cl); 1987 break; 1988 } 1989 1990 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 1991 sd_cl[frag_idx] = cl; 1992 #if MEMORY_LOGGING 1993 fl->ifl_cl_enqueued++; 1994 #endif 1995 } else { 1996 bus_addr = sd_ba[frag_idx]; 1997 } 1998 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 1999 BUS_DMASYNC_PREREAD); 2000 2001 if (sd_m[frag_idx] == NULL) { 2002 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 2003 break; 2004 } 2005 sd_m[frag_idx] = m; 2006 } 2007 bit_set(fl->ifl_rx_bitmap, frag_idx); 2008 #if MEMORY_LOGGING 2009 fl->ifl_m_enqueued++; 2010 #endif 2011 2012 DBG_COUNTER_INC(rx_allocs); 2013 fl->ifl_rxd_idxs[i] = frag_idx; 2014 fl->ifl_bus_addrs[i] = bus_addr; 2015 fl->ifl_vm_addrs[i] = cl; 2016 credits++; 2017 i++; 2018 MPASS(credits <= fl->ifl_size); 2019 if (++idx == fl->ifl_size) { 2020 fl->ifl_gen = 1; 2021 idx = 0; 2022 } 2023 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2024 iru.iru_pidx = pidx; 2025 iru.iru_count = i; 2026 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2027 i = 0; 2028 pidx = idx; 2029 fl->ifl_pidx = idx; 2030 fl->ifl_credits = credits; 2031 } 2032 } 2033 2034 if (i) { 2035 iru.iru_pidx = pidx; 2036 iru.iru_count = i; 2037 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2038 fl->ifl_pidx = idx; 2039 fl->ifl_credits = credits; 2040 } 2041 DBG_COUNTER_INC(rxd_flush); 2042 if (fl->ifl_pidx == 0) 2043 pidx = fl->ifl_size - 1; 2044 else 2045 pidx = fl->ifl_pidx - 1; 2046 2047 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2048 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2049 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2050 fl->ifl_fragidx = frag_idx + 1; 2051 if (fl->ifl_fragidx == fl->ifl_size) 2052 fl->ifl_fragidx = 0; 2053 2054 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2055 } 2056 2057 static __inline uint8_t 2058 __iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2059 { 2060 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2061 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2062 #ifdef INVARIANTS 2063 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2064 #endif 2065 2066 MPASS(fl->ifl_credits <= fl->ifl_size); 2067 MPASS(reclaimable == delta); 2068 2069 if (reclaimable > 0) 2070 return (_iflib_fl_refill(ctx, fl, reclaimable)); 2071 return (0); 2072 } 2073 2074 uint8_t 2075 iflib_in_detach(if_ctx_t ctx) 2076 { 2077 bool in_detach; 2078 2079 STATE_LOCK(ctx); 2080 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2081 STATE_UNLOCK(ctx); 2082 return (in_detach); 2083 } 2084 2085 static void 2086 iflib_fl_bufs_free(iflib_fl_t fl) 2087 { 2088 iflib_dma_info_t idi = fl->ifl_ifdi; 2089 bus_dmamap_t sd_map; 2090 uint32_t i; 2091 2092 for (i = 0; i < fl->ifl_size; i++) { 2093 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2094 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2095 2096 if (*sd_cl != NULL) { 2097 sd_map = fl->ifl_sds.ifsd_map[i]; 2098 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2099 BUS_DMASYNC_POSTREAD); 2100 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2101 if (*sd_cl != NULL) 2102 uma_zfree(fl->ifl_zone, *sd_cl); 2103 if (*sd_m != NULL) { 2104 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2105 uma_zfree(zone_mbuf, *sd_m); 2106 } 2107 } else { 2108 MPASS(*sd_cl == NULL); 2109 MPASS(*sd_m == NULL); 2110 } 2111 #if MEMORY_LOGGING 2112 fl->ifl_m_dequeued++; 2113 fl->ifl_cl_dequeued++; 2114 #endif 2115 *sd_cl = NULL; 2116 *sd_m = NULL; 2117 } 2118 #ifdef INVARIANTS 2119 for (i = 0; i < fl->ifl_size; i++) { 2120 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2121 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2122 } 2123 #endif 2124 /* 2125 * Reset free list values 2126 */ 2127 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2128 bzero(idi->idi_vaddr, idi->idi_size); 2129 } 2130 2131 /********************************************************************* 2132 * 2133 * Initialize a free list and its buffers. 2134 * 2135 **********************************************************************/ 2136 static int 2137 iflib_fl_setup(iflib_fl_t fl) 2138 { 2139 iflib_rxq_t rxq = fl->ifl_rxq; 2140 if_ctx_t ctx = rxq->ifr_ctx; 2141 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2142 int qidx; 2143 2144 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2145 /* 2146 ** Free current RX buffer structs and their mbufs 2147 */ 2148 iflib_fl_bufs_free(fl); 2149 /* Now replenish the mbufs */ 2150 MPASS(fl->ifl_credits == 0); 2151 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2152 if (scctx->isc_rxd_buf_size[qidx] != 0) 2153 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2154 else 2155 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2156 /* 2157 * ifl_buf_size may be a driver-supplied value, so pull it up 2158 * to the selected mbuf size. 2159 */ 2160 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2161 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2162 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2163 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2164 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2165 2166 2167 /* avoid pre-allocating zillions of clusters to an idle card 2168 * potentially speeding up attach 2169 */ 2170 (void) _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2171 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2172 if (min(128, fl->ifl_size) != fl->ifl_credits) 2173 return (ENOBUFS); 2174 /* 2175 * handle failure 2176 */ 2177 MPASS(rxq != NULL); 2178 MPASS(fl->ifl_ifdi != NULL); 2179 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2180 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2181 return (0); 2182 } 2183 2184 /********************************************************************* 2185 * 2186 * Free receive ring data structures 2187 * 2188 **********************************************************************/ 2189 static void 2190 iflib_rx_sds_free(iflib_rxq_t rxq) 2191 { 2192 iflib_fl_t fl; 2193 int i, j; 2194 2195 if (rxq->ifr_fl != NULL) { 2196 for (i = 0; i < rxq->ifr_nfl; i++) { 2197 fl = &rxq->ifr_fl[i]; 2198 if (fl->ifl_buf_tag != NULL) { 2199 if (fl->ifl_sds.ifsd_map != NULL) { 2200 for (j = 0; j < fl->ifl_size; j++) { 2201 bus_dmamap_sync( 2202 fl->ifl_buf_tag, 2203 fl->ifl_sds.ifsd_map[j], 2204 BUS_DMASYNC_POSTREAD); 2205 bus_dmamap_unload( 2206 fl->ifl_buf_tag, 2207 fl->ifl_sds.ifsd_map[j]); 2208 bus_dmamap_destroy( 2209 fl->ifl_buf_tag, 2210 fl->ifl_sds.ifsd_map[j]); 2211 } 2212 } 2213 bus_dma_tag_destroy(fl->ifl_buf_tag); 2214 fl->ifl_buf_tag = NULL; 2215 } 2216 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2217 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2218 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2219 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2220 fl->ifl_sds.ifsd_m = NULL; 2221 fl->ifl_sds.ifsd_cl = NULL; 2222 fl->ifl_sds.ifsd_ba = NULL; 2223 fl->ifl_sds.ifsd_map = NULL; 2224 } 2225 free(rxq->ifr_fl, M_IFLIB); 2226 rxq->ifr_fl = NULL; 2227 free(rxq->ifr_ifdi, M_IFLIB); 2228 rxq->ifr_ifdi = NULL; 2229 rxq->ifr_cq_cidx = 0; 2230 } 2231 } 2232 2233 /* 2234 * Timer routine 2235 */ 2236 static void 2237 iflib_timer(void *arg) 2238 { 2239 iflib_txq_t txq = arg; 2240 if_ctx_t ctx = txq->ift_ctx; 2241 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2242 uint64_t this_tick = ticks; 2243 uint32_t reset_on = hz / 2; 2244 2245 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2246 return; 2247 2248 /* 2249 ** Check on the state of the TX queue(s), this 2250 ** can be done without the lock because its RO 2251 ** and the HUNG state will be static if set. 2252 */ 2253 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2254 txq->ift_last_timer_tick = this_tick; 2255 IFDI_TIMER(ctx, txq->ift_id); 2256 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2257 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2258 (sctx->isc_pause_frames == 0))) 2259 goto hung; 2260 2261 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2262 ifmp_ring_is_stalled(txq->ift_br)) { 2263 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down")); 2264 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2265 } 2266 txq->ift_cleaned_prev = txq->ift_cleaned; 2267 } 2268 #ifdef DEV_NETMAP 2269 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2270 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 2271 #endif 2272 /* handle any laggards */ 2273 if (txq->ift_db_pending) 2274 GROUPTASK_ENQUEUE(&txq->ift_task); 2275 2276 sctx->isc_pause_frames = 0; 2277 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2278 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2279 return; 2280 2281 hung: 2282 device_printf(ctx->ifc_dev, 2283 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2284 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2285 STATE_LOCK(ctx); 2286 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2287 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2288 iflib_admin_intr_deferred(ctx); 2289 STATE_UNLOCK(ctx); 2290 } 2291 2292 static uint16_t 2293 iflib_get_mbuf_size_for(unsigned int size) 2294 { 2295 2296 if (size <= MCLBYTES) 2297 return (MCLBYTES); 2298 else 2299 return (MJUMPAGESIZE); 2300 } 2301 2302 static void 2303 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2304 { 2305 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2306 2307 /* 2308 * XXX don't set the max_frame_size to larger 2309 * than the hardware can handle 2310 */ 2311 ctx->ifc_rx_mbuf_sz = 2312 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2313 } 2314 2315 uint32_t 2316 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2317 { 2318 2319 return (ctx->ifc_rx_mbuf_sz); 2320 } 2321 2322 static void 2323 iflib_init_locked(if_ctx_t ctx) 2324 { 2325 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2326 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2327 if_t ifp = ctx->ifc_ifp; 2328 iflib_fl_t fl; 2329 iflib_txq_t txq; 2330 iflib_rxq_t rxq; 2331 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2332 2333 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2334 IFDI_INTR_DISABLE(ctx); 2335 2336 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2337 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2338 /* Set hardware offload abilities */ 2339 if_clearhwassist(ifp); 2340 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2341 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2342 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2343 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2344 if (if_getcapenable(ifp) & IFCAP_TSO4) 2345 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2346 if (if_getcapenable(ifp) & IFCAP_TSO6) 2347 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2348 2349 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2350 CALLOUT_LOCK(txq); 2351 callout_stop(&txq->ift_timer); 2352 CALLOUT_UNLOCK(txq); 2353 iflib_netmap_txq_init(ctx, txq); 2354 } 2355 2356 /* 2357 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2358 * that drivers can use the value when setting up the hardware receive 2359 * buffers. 2360 */ 2361 iflib_calc_rx_mbuf_sz(ctx); 2362 2363 #ifdef INVARIANTS 2364 i = if_getdrvflags(ifp); 2365 #endif 2366 IFDI_INIT(ctx); 2367 MPASS(if_getdrvflags(ifp) == i); 2368 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2369 /* XXX this should really be done on a per-queue basis */ 2370 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2371 MPASS(rxq->ifr_id == i); 2372 iflib_netmap_rxq_init(ctx, rxq); 2373 continue; 2374 } 2375 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2376 if (iflib_fl_setup(fl)) { 2377 device_printf(ctx->ifc_dev, 2378 "setting up free list %d failed - " 2379 "check cluster settings\n", j); 2380 goto done; 2381 } 2382 } 2383 } 2384 done: 2385 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2386 IFDI_INTR_ENABLE(ctx); 2387 txq = ctx->ifc_txqs; 2388 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2389 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2390 txq->ift_timer.c_cpu); 2391 } 2392 2393 static int 2394 iflib_media_change(if_t ifp) 2395 { 2396 if_ctx_t ctx = if_getsoftc(ifp); 2397 int err; 2398 2399 CTX_LOCK(ctx); 2400 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2401 iflib_init_locked(ctx); 2402 CTX_UNLOCK(ctx); 2403 return (err); 2404 } 2405 2406 static void 2407 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2408 { 2409 if_ctx_t ctx = if_getsoftc(ifp); 2410 2411 CTX_LOCK(ctx); 2412 IFDI_UPDATE_ADMIN_STATUS(ctx); 2413 IFDI_MEDIA_STATUS(ctx, ifmr); 2414 CTX_UNLOCK(ctx); 2415 } 2416 2417 void 2418 iflib_stop(if_ctx_t ctx) 2419 { 2420 iflib_txq_t txq = ctx->ifc_txqs; 2421 iflib_rxq_t rxq = ctx->ifc_rxqs; 2422 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2423 if_shared_ctx_t sctx = ctx->ifc_sctx; 2424 iflib_dma_info_t di; 2425 iflib_fl_t fl; 2426 int i, j; 2427 2428 /* Tell the stack that the interface is no longer active */ 2429 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2430 2431 IFDI_INTR_DISABLE(ctx); 2432 DELAY(1000); 2433 IFDI_STOP(ctx); 2434 DELAY(1000); 2435 2436 iflib_debug_reset(); 2437 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2438 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2439 /* make sure all transmitters have completed before proceeding XXX */ 2440 2441 CALLOUT_LOCK(txq); 2442 callout_stop(&txq->ift_timer); 2443 CALLOUT_UNLOCK(txq); 2444 2445 /* clean any enqueued buffers */ 2446 iflib_ifmp_purge(txq); 2447 /* Free any existing tx buffers. */ 2448 for (j = 0; j < txq->ift_size; j++) { 2449 iflib_txsd_free(ctx, txq, j); 2450 } 2451 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2452 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2453 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2454 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2455 txq->ift_pullups = 0; 2456 ifmp_ring_reset_stats(txq->ift_br); 2457 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2458 bzero((void *)di->idi_vaddr, di->idi_size); 2459 } 2460 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2461 /* make sure all transmitters have completed before proceeding XXX */ 2462 2463 rxq->ifr_cq_cidx = 0; 2464 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2465 bzero((void *)di->idi_vaddr, di->idi_size); 2466 /* also resets the free lists pidx/cidx */ 2467 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2468 iflib_fl_bufs_free(fl); 2469 } 2470 } 2471 2472 static inline caddr_t 2473 calc_next_rxd(iflib_fl_t fl, int cidx) 2474 { 2475 qidx_t size; 2476 int nrxd; 2477 caddr_t start, end, cur, next; 2478 2479 nrxd = fl->ifl_size; 2480 size = fl->ifl_rxd_size; 2481 start = fl->ifl_ifdi->idi_vaddr; 2482 2483 if (__predict_false(size == 0)) 2484 return (start); 2485 cur = start + size*cidx; 2486 end = start + size*nrxd; 2487 next = CACHE_PTR_NEXT(cur); 2488 return (next < end ? next : start); 2489 } 2490 2491 static inline void 2492 prefetch_pkts(iflib_fl_t fl, int cidx) 2493 { 2494 int nextptr; 2495 int nrxd = fl->ifl_size; 2496 caddr_t next_rxd; 2497 2498 2499 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2500 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2501 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2502 next_rxd = calc_next_rxd(fl, cidx); 2503 prefetch(next_rxd); 2504 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2505 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2506 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2507 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2508 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2509 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2510 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2511 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2512 } 2513 2514 static struct mbuf * 2515 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2516 int *pf_rv, if_rxd_info_t ri) 2517 { 2518 bus_dmamap_t map; 2519 iflib_fl_t fl; 2520 caddr_t payload; 2521 struct mbuf *m; 2522 int flid, cidx, len, next; 2523 2524 map = NULL; 2525 flid = irf->irf_flid; 2526 cidx = irf->irf_idx; 2527 fl = &rxq->ifr_fl[flid]; 2528 sd->ifsd_fl = fl; 2529 m = fl->ifl_sds.ifsd_m[cidx]; 2530 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2531 fl->ifl_credits--; 2532 #if MEMORY_LOGGING 2533 fl->ifl_m_dequeued++; 2534 #endif 2535 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2536 prefetch_pkts(fl, cidx); 2537 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2538 prefetch(&fl->ifl_sds.ifsd_map[next]); 2539 map = fl->ifl_sds.ifsd_map[cidx]; 2540 2541 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2542 2543 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2544 irf->irf_len != 0) { 2545 payload = *sd->ifsd_cl; 2546 payload += ri->iri_pad; 2547 len = ri->iri_len - ri->iri_pad; 2548 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2549 len | PFIL_MEMPTR | PFIL_IN, NULL); 2550 switch (*pf_rv) { 2551 case PFIL_DROPPED: 2552 case PFIL_CONSUMED: 2553 /* 2554 * The filter ate it. Everything is recycled. 2555 */ 2556 m = NULL; 2557 unload = 0; 2558 break; 2559 case PFIL_REALLOCED: 2560 /* 2561 * The filter copied it. Everything is recycled. 2562 */ 2563 m = pfil_mem2mbuf(payload); 2564 unload = 0; 2565 break; 2566 case PFIL_PASS: 2567 /* 2568 * Filter said it was OK, so receive like 2569 * normal 2570 */ 2571 fl->ifl_sds.ifsd_m[cidx] = NULL; 2572 break; 2573 default: 2574 MPASS(0); 2575 } 2576 } else { 2577 fl->ifl_sds.ifsd_m[cidx] = NULL; 2578 *pf_rv = PFIL_PASS; 2579 } 2580 2581 if (unload && irf->irf_len != 0) 2582 bus_dmamap_unload(fl->ifl_buf_tag, map); 2583 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2584 if (__predict_false(fl->ifl_cidx == 0)) 2585 fl->ifl_gen = 0; 2586 bit_clear(fl->ifl_rx_bitmap, cidx); 2587 return (m); 2588 } 2589 2590 static struct mbuf * 2591 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2592 { 2593 struct mbuf *m, *mh, *mt; 2594 caddr_t cl; 2595 int *pf_rv_ptr, flags, i, padlen; 2596 bool consumed; 2597 2598 i = 0; 2599 mh = NULL; 2600 consumed = false; 2601 *pf_rv = PFIL_PASS; 2602 pf_rv_ptr = pf_rv; 2603 do { 2604 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2605 pf_rv_ptr, ri); 2606 2607 MPASS(*sd->ifsd_cl != NULL); 2608 2609 /* 2610 * Exclude zero-length frags & frags from 2611 * packets the filter has consumed or dropped 2612 */ 2613 if (ri->iri_frags[i].irf_len == 0 || consumed || 2614 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2615 if (mh == NULL) { 2616 /* everything saved here */ 2617 consumed = true; 2618 pf_rv_ptr = NULL; 2619 continue; 2620 } 2621 /* XXX we can save the cluster here, but not the mbuf */ 2622 m_init(m, M_NOWAIT, MT_DATA, 0); 2623 m_free(m); 2624 continue; 2625 } 2626 if (mh == NULL) { 2627 flags = M_PKTHDR|M_EXT; 2628 mh = mt = m; 2629 padlen = ri->iri_pad; 2630 } else { 2631 flags = M_EXT; 2632 mt->m_next = m; 2633 mt = m; 2634 /* assuming padding is only on the first fragment */ 2635 padlen = 0; 2636 } 2637 cl = *sd->ifsd_cl; 2638 *sd->ifsd_cl = NULL; 2639 2640 /* Can these two be made one ? */ 2641 m_init(m, M_NOWAIT, MT_DATA, flags); 2642 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2643 /* 2644 * These must follow m_init and m_cljset 2645 */ 2646 m->m_data += padlen; 2647 ri->iri_len -= padlen; 2648 m->m_len = ri->iri_frags[i].irf_len; 2649 } while (++i < ri->iri_nfrags); 2650 2651 return (mh); 2652 } 2653 2654 /* 2655 * Process one software descriptor 2656 */ 2657 static struct mbuf * 2658 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2659 { 2660 struct if_rxsd sd; 2661 struct mbuf *m; 2662 int pf_rv; 2663 2664 /* should I merge this back in now that the two paths are basically duplicated? */ 2665 if (ri->iri_nfrags == 1 && 2666 ri->iri_frags[0].irf_len != 0 && 2667 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2668 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2669 &pf_rv, ri); 2670 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2671 return (m); 2672 if (pf_rv == PFIL_PASS) { 2673 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2674 #ifndef __NO_STRICT_ALIGNMENT 2675 if (!IP_ALIGNED(m)) 2676 m->m_data += 2; 2677 #endif 2678 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2679 m->m_len = ri->iri_frags[0].irf_len; 2680 } 2681 } else { 2682 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2683 if (m == NULL) 2684 return (NULL); 2685 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2686 return (m); 2687 } 2688 m->m_pkthdr.len = ri->iri_len; 2689 m->m_pkthdr.rcvif = ri->iri_ifp; 2690 m->m_flags |= ri->iri_flags; 2691 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2692 m->m_pkthdr.flowid = ri->iri_flowid; 2693 M_HASHTYPE_SET(m, ri->iri_rsstype); 2694 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2695 m->m_pkthdr.csum_data = ri->iri_csum_data; 2696 return (m); 2697 } 2698 2699 #if defined(INET6) || defined(INET) 2700 static void 2701 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2702 { 2703 CURVNET_SET(lc->ifp->if_vnet); 2704 #if defined(INET6) 2705 *v6 = V_ip6_forwarding; 2706 #endif 2707 #if defined(INET) 2708 *v4 = V_ipforwarding; 2709 #endif 2710 CURVNET_RESTORE(); 2711 } 2712 2713 /* 2714 * Returns true if it's possible this packet could be LROed. 2715 * if it returns false, it is guaranteed that tcp_lro_rx() 2716 * would not return zero. 2717 */ 2718 static bool 2719 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2720 { 2721 struct ether_header *eh; 2722 2723 eh = mtod(m, struct ether_header *); 2724 switch (eh->ether_type) { 2725 #if defined(INET6) 2726 case htons(ETHERTYPE_IPV6): 2727 return (!v6_forwarding); 2728 #endif 2729 #if defined (INET) 2730 case htons(ETHERTYPE_IP): 2731 return (!v4_forwarding); 2732 #endif 2733 } 2734 2735 return false; 2736 } 2737 #else 2738 static void 2739 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2740 { 2741 } 2742 #endif 2743 2744 static void 2745 _task_fn_rx_watchdog(void *context) 2746 { 2747 iflib_rxq_t rxq = context; 2748 2749 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2750 } 2751 2752 static uint8_t 2753 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2754 { 2755 if_t ifp; 2756 if_ctx_t ctx = rxq->ifr_ctx; 2757 if_shared_ctx_t sctx = ctx->ifc_sctx; 2758 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2759 int avail, i; 2760 qidx_t *cidxp; 2761 struct if_rxd_info ri; 2762 int err, budget_left, rx_bytes, rx_pkts; 2763 iflib_fl_t fl; 2764 int lro_enabled; 2765 bool v4_forwarding, v6_forwarding, lro_possible; 2766 uint8_t retval = 0; 2767 2768 /* 2769 * XXX early demux data packets so that if_input processing only handles 2770 * acks in interrupt context 2771 */ 2772 struct mbuf *m, *mh, *mt, *mf; 2773 2774 NET_EPOCH_ASSERT(); 2775 2776 lro_possible = v4_forwarding = v6_forwarding = false; 2777 ifp = ctx->ifc_ifp; 2778 mh = mt = NULL; 2779 MPASS(budget > 0); 2780 rx_pkts = rx_bytes = 0; 2781 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2782 cidxp = &rxq->ifr_cq_cidx; 2783 else 2784 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2785 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2786 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2787 retval |= __iflib_fl_refill_all(ctx, fl); 2788 DBG_COUNTER_INC(rx_unavail); 2789 return (retval); 2790 } 2791 2792 /* pfil needs the vnet to be set */ 2793 CURVNET_SET_QUIET(ifp->if_vnet); 2794 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2795 if (__predict_false(!CTX_ACTIVE(ctx))) { 2796 DBG_COUNTER_INC(rx_ctx_inactive); 2797 break; 2798 } 2799 /* 2800 * Reset client set fields to their default values 2801 */ 2802 rxd_info_zero(&ri); 2803 ri.iri_qsidx = rxq->ifr_id; 2804 ri.iri_cidx = *cidxp; 2805 ri.iri_ifp = ifp; 2806 ri.iri_frags = rxq->ifr_frags; 2807 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2808 2809 if (err) 2810 goto err; 2811 rx_pkts += 1; 2812 rx_bytes += ri.iri_len; 2813 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2814 *cidxp = ri.iri_cidx; 2815 /* Update our consumer index */ 2816 /* XXX NB: shurd - check if this is still safe */ 2817 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2818 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2819 /* was this only a completion queue message? */ 2820 if (__predict_false(ri.iri_nfrags == 0)) 2821 continue; 2822 } 2823 MPASS(ri.iri_nfrags != 0); 2824 MPASS(ri.iri_len != 0); 2825 2826 /* will advance the cidx on the corresponding free lists */ 2827 m = iflib_rxd_pkt_get(rxq, &ri); 2828 avail--; 2829 budget_left--; 2830 if (avail == 0 && budget_left) 2831 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2832 2833 if (__predict_false(m == NULL)) 2834 continue; 2835 2836 /* imm_pkt: -- cxgb */ 2837 if (mh == NULL) 2838 mh = mt = m; 2839 else { 2840 mt->m_nextpkt = m; 2841 mt = m; 2842 } 2843 } 2844 CURVNET_RESTORE(); 2845 /* make sure that we can refill faster than drain */ 2846 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2847 retval |= __iflib_fl_refill_all(ctx, fl); 2848 2849 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2850 if (lro_enabled) 2851 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2852 mt = mf = NULL; 2853 while (mh != NULL) { 2854 m = mh; 2855 mh = mh->m_nextpkt; 2856 m->m_nextpkt = NULL; 2857 #ifndef __NO_STRICT_ALIGNMENT 2858 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2859 continue; 2860 #endif 2861 rx_bytes += m->m_pkthdr.len; 2862 rx_pkts++; 2863 #if defined(INET6) || defined(INET) 2864 if (lro_enabled) { 2865 if (!lro_possible) { 2866 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2867 if (lro_possible && mf != NULL) { 2868 ifp->if_input(ifp, mf); 2869 DBG_COUNTER_INC(rx_if_input); 2870 mt = mf = NULL; 2871 } 2872 } 2873 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2874 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2875 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2876 continue; 2877 } 2878 } 2879 #endif 2880 if (lro_possible) { 2881 ifp->if_input(ifp, m); 2882 DBG_COUNTER_INC(rx_if_input); 2883 continue; 2884 } 2885 2886 if (mf == NULL) 2887 mf = m; 2888 if (mt != NULL) 2889 mt->m_nextpkt = m; 2890 mt = m; 2891 } 2892 if (mf != NULL) { 2893 ifp->if_input(ifp, mf); 2894 DBG_COUNTER_INC(rx_if_input); 2895 } 2896 2897 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2898 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2899 2900 /* 2901 * Flush any outstanding LRO work 2902 */ 2903 #if defined(INET6) || defined(INET) 2904 tcp_lro_flush_all(&rxq->ifr_lc); 2905 #endif 2906 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 2907 retval |= IFLIB_RXEOF_MORE; 2908 return (retval); 2909 err: 2910 STATE_LOCK(ctx); 2911 ctx->ifc_flags |= IFC_DO_RESET; 2912 iflib_admin_intr_deferred(ctx); 2913 STATE_UNLOCK(ctx); 2914 return (0); 2915 } 2916 2917 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2918 static inline qidx_t 2919 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2920 { 2921 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2922 qidx_t minthresh = txq->ift_size / 8; 2923 if (in_use > 4*minthresh) 2924 return (notify_count); 2925 if (in_use > 2*minthresh) 2926 return (notify_count >> 1); 2927 if (in_use > minthresh) 2928 return (notify_count >> 3); 2929 return (0); 2930 } 2931 2932 static inline qidx_t 2933 txq_max_rs_deferred(iflib_txq_t txq) 2934 { 2935 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2936 qidx_t minthresh = txq->ift_size / 8; 2937 if (txq->ift_in_use > 4*minthresh) 2938 return (notify_count); 2939 if (txq->ift_in_use > 2*minthresh) 2940 return (notify_count >> 1); 2941 if (txq->ift_in_use > minthresh) 2942 return (notify_count >> 2); 2943 return (2); 2944 } 2945 2946 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2947 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2948 2949 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2950 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2951 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2952 2953 /* forward compatibility for cxgb */ 2954 #define FIRST_QSET(ctx) 0 2955 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2956 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2957 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2958 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2959 2960 /* XXX we should be setting this to something other than zero */ 2961 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2962 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2963 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2964 2965 static inline bool 2966 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2967 { 2968 qidx_t dbval, max; 2969 bool rang; 2970 2971 rang = false; 2972 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2973 if (ring || txq->ift_db_pending >= max) { 2974 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2975 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 2976 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2977 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2978 txq->ift_db_pending = txq->ift_npending = 0; 2979 rang = true; 2980 } 2981 return (rang); 2982 } 2983 2984 #ifdef PKT_DEBUG 2985 static void 2986 print_pkt(if_pkt_info_t pi) 2987 { 2988 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2989 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2990 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2991 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2992 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2993 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2994 } 2995 #endif 2996 2997 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2998 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2999 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3000 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3001 3002 static int 3003 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3004 { 3005 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3006 struct ether_vlan_header *eh; 3007 struct mbuf *m; 3008 3009 m = *mp; 3010 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3011 M_WRITABLE(m) == 0) { 3012 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3013 return (ENOMEM); 3014 } else { 3015 m_freem(*mp); 3016 DBG_COUNTER_INC(tx_frees); 3017 *mp = m; 3018 } 3019 } 3020 3021 /* 3022 * Determine where frame payload starts. 3023 * Jump over vlan headers if already present, 3024 * helpful for QinQ too. 3025 */ 3026 if (__predict_false(m->m_len < sizeof(*eh))) { 3027 txq->ift_pullups++; 3028 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3029 return (ENOMEM); 3030 } 3031 eh = mtod(m, struct ether_vlan_header *); 3032 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3033 pi->ipi_etype = ntohs(eh->evl_proto); 3034 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3035 } else { 3036 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3037 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3038 } 3039 3040 switch (pi->ipi_etype) { 3041 #ifdef INET 3042 case ETHERTYPE_IP: 3043 { 3044 struct mbuf *n; 3045 struct ip *ip = NULL; 3046 struct tcphdr *th = NULL; 3047 int minthlen; 3048 3049 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3050 if (__predict_false(m->m_len < minthlen)) { 3051 /* 3052 * if this code bloat is causing too much of a hit 3053 * move it to a separate function and mark it noinline 3054 */ 3055 if (m->m_len == pi->ipi_ehdrlen) { 3056 n = m->m_next; 3057 MPASS(n); 3058 if (n->m_len >= sizeof(*ip)) { 3059 ip = (struct ip *)n->m_data; 3060 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3061 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3062 } else { 3063 txq->ift_pullups++; 3064 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3065 return (ENOMEM); 3066 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3067 } 3068 } else { 3069 txq->ift_pullups++; 3070 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3071 return (ENOMEM); 3072 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3073 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3074 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3075 } 3076 } else { 3077 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3078 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3079 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3080 } 3081 pi->ipi_ip_hlen = ip->ip_hl << 2; 3082 pi->ipi_ipproto = ip->ip_p; 3083 pi->ipi_flags |= IPI_TX_IPV4; 3084 3085 /* TCP checksum offload may require TCP header length */ 3086 if (IS_TX_OFFLOAD4(pi)) { 3087 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3088 if (__predict_false(th == NULL)) { 3089 txq->ift_pullups++; 3090 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3091 return (ENOMEM); 3092 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3093 } 3094 pi->ipi_tcp_hflags = th->th_flags; 3095 pi->ipi_tcp_hlen = th->th_off << 2; 3096 pi->ipi_tcp_seq = th->th_seq; 3097 } 3098 if (IS_TSO4(pi)) { 3099 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3100 return (ENXIO); 3101 /* 3102 * TSO always requires hardware checksum offload. 3103 */ 3104 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3105 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3106 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3107 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3108 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3109 ip->ip_sum = 0; 3110 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3111 } 3112 } 3113 } 3114 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3115 ip->ip_sum = 0; 3116 3117 break; 3118 } 3119 #endif 3120 #ifdef INET6 3121 case ETHERTYPE_IPV6: 3122 { 3123 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3124 struct tcphdr *th; 3125 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3126 3127 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3128 txq->ift_pullups++; 3129 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3130 return (ENOMEM); 3131 } 3132 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3133 3134 /* XXX-BZ this will go badly in case of ext hdrs. */ 3135 pi->ipi_ipproto = ip6->ip6_nxt; 3136 pi->ipi_flags |= IPI_TX_IPV6; 3137 3138 /* TCP checksum offload may require TCP header length */ 3139 if (IS_TX_OFFLOAD6(pi)) { 3140 if (pi->ipi_ipproto == IPPROTO_TCP) { 3141 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3142 txq->ift_pullups++; 3143 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3144 return (ENOMEM); 3145 } 3146 pi->ipi_tcp_hflags = th->th_flags; 3147 pi->ipi_tcp_hlen = th->th_off << 2; 3148 pi->ipi_tcp_seq = th->th_seq; 3149 } 3150 if (IS_TSO6(pi)) { 3151 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3152 return (ENXIO); 3153 /* 3154 * TSO always requires hardware checksum offload. 3155 */ 3156 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3157 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3158 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3159 } 3160 } 3161 break; 3162 } 3163 #endif 3164 default: 3165 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3166 pi->ipi_ip_hlen = 0; 3167 break; 3168 } 3169 *mp = m; 3170 3171 return (0); 3172 } 3173 3174 /* 3175 * If dodgy hardware rejects the scatter gather chain we've handed it 3176 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3177 * m_defrag'd mbufs 3178 */ 3179 static __noinline struct mbuf * 3180 iflib_remove_mbuf(iflib_txq_t txq) 3181 { 3182 int ntxd, pidx; 3183 struct mbuf *m, **ifsd_m; 3184 3185 ifsd_m = txq->ift_sds.ifsd_m; 3186 ntxd = txq->ift_size; 3187 pidx = txq->ift_pidx & (ntxd - 1); 3188 ifsd_m = txq->ift_sds.ifsd_m; 3189 m = ifsd_m[pidx]; 3190 ifsd_m[pidx] = NULL; 3191 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3192 if (txq->ift_sds.ifsd_tso_map != NULL) 3193 bus_dmamap_unload(txq->ift_tso_buf_tag, 3194 txq->ift_sds.ifsd_tso_map[pidx]); 3195 #if MEMORY_LOGGING 3196 txq->ift_dequeued++; 3197 #endif 3198 return (m); 3199 } 3200 3201 static inline caddr_t 3202 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3203 { 3204 qidx_t size; 3205 int ntxd; 3206 caddr_t start, end, cur, next; 3207 3208 ntxd = txq->ift_size; 3209 size = txq->ift_txd_size[qid]; 3210 start = txq->ift_ifdi[qid].idi_vaddr; 3211 3212 if (__predict_false(size == 0)) 3213 return (start); 3214 cur = start + size*cidx; 3215 end = start + size*ntxd; 3216 next = CACHE_PTR_NEXT(cur); 3217 return (next < end ? next : start); 3218 } 3219 3220 /* 3221 * Pad an mbuf to ensure a minimum ethernet frame size. 3222 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3223 */ 3224 static __noinline int 3225 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3226 { 3227 /* 3228 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3229 * and ARP message is the smallest common payload I can think of 3230 */ 3231 static char pad[18]; /* just zeros */ 3232 int n; 3233 struct mbuf *new_head; 3234 3235 if (!M_WRITABLE(*m_head)) { 3236 new_head = m_dup(*m_head, M_NOWAIT); 3237 if (new_head == NULL) { 3238 m_freem(*m_head); 3239 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3240 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3241 DBG_COUNTER_INC(tx_frees); 3242 return ENOMEM; 3243 } 3244 m_freem(*m_head); 3245 *m_head = new_head; 3246 } 3247 3248 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3249 n > 0; n -= sizeof(pad)) 3250 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3251 break; 3252 3253 if (n > 0) { 3254 m_freem(*m_head); 3255 device_printf(dev, "cannot pad short frame\n"); 3256 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3257 DBG_COUNTER_INC(tx_frees); 3258 return (ENOBUFS); 3259 } 3260 3261 return 0; 3262 } 3263 3264 static int 3265 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3266 { 3267 if_ctx_t ctx; 3268 if_shared_ctx_t sctx; 3269 if_softc_ctx_t scctx; 3270 bus_dma_tag_t buf_tag; 3271 bus_dma_segment_t *segs; 3272 struct mbuf *m_head, **ifsd_m; 3273 void *next_txd; 3274 bus_dmamap_t map; 3275 struct if_pkt_info pi; 3276 int remap = 0; 3277 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3278 3279 ctx = txq->ift_ctx; 3280 sctx = ctx->ifc_sctx; 3281 scctx = &ctx->ifc_softc_ctx; 3282 segs = txq->ift_segs; 3283 ntxd = txq->ift_size; 3284 m_head = *m_headp; 3285 map = NULL; 3286 3287 /* 3288 * If we're doing TSO the next descriptor to clean may be quite far ahead 3289 */ 3290 cidx = txq->ift_cidx; 3291 pidx = txq->ift_pidx; 3292 if (ctx->ifc_flags & IFC_PREFETCH) { 3293 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3294 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3295 next_txd = calc_next_txd(txq, cidx, 0); 3296 prefetch(next_txd); 3297 } 3298 3299 /* prefetch the next cache line of mbuf pointers and flags */ 3300 prefetch(&txq->ift_sds.ifsd_m[next]); 3301 prefetch(&txq->ift_sds.ifsd_map[next]); 3302 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3303 } 3304 map = txq->ift_sds.ifsd_map[pidx]; 3305 ifsd_m = txq->ift_sds.ifsd_m; 3306 3307 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3308 buf_tag = txq->ift_tso_buf_tag; 3309 max_segs = scctx->isc_tx_tso_segments_max; 3310 map = txq->ift_sds.ifsd_tso_map[pidx]; 3311 MPASS(buf_tag != NULL); 3312 MPASS(max_segs > 0); 3313 } else { 3314 buf_tag = txq->ift_buf_tag; 3315 max_segs = scctx->isc_tx_nsegments; 3316 map = txq->ift_sds.ifsd_map[pidx]; 3317 } 3318 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3319 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3320 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3321 if (err) { 3322 DBG_COUNTER_INC(encap_txd_encap_fail); 3323 return err; 3324 } 3325 } 3326 m_head = *m_headp; 3327 3328 pkt_info_zero(&pi); 3329 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3330 pi.ipi_pidx = pidx; 3331 pi.ipi_qsidx = txq->ift_id; 3332 pi.ipi_len = m_head->m_pkthdr.len; 3333 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3334 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3335 3336 /* deliberate bitwise OR to make one condition */ 3337 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3338 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3339 DBG_COUNTER_INC(encap_txd_encap_fail); 3340 return (err); 3341 } 3342 m_head = *m_headp; 3343 } 3344 3345 retry: 3346 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3347 BUS_DMA_NOWAIT); 3348 defrag: 3349 if (__predict_false(err)) { 3350 switch (err) { 3351 case EFBIG: 3352 /* try collapse once and defrag once */ 3353 if (remap == 0) { 3354 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3355 /* try defrag if collapsing fails */ 3356 if (m_head == NULL) 3357 remap++; 3358 } 3359 if (remap == 1) { 3360 txq->ift_mbuf_defrag++; 3361 m_head = m_defrag(*m_headp, M_NOWAIT); 3362 } 3363 /* 3364 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3365 * failed to map an mbuf that was run through m_defrag 3366 */ 3367 MPASS(remap <= 1); 3368 if (__predict_false(m_head == NULL || remap > 1)) 3369 goto defrag_failed; 3370 remap++; 3371 *m_headp = m_head; 3372 goto retry; 3373 break; 3374 case ENOMEM: 3375 txq->ift_no_tx_dma_setup++; 3376 break; 3377 default: 3378 txq->ift_no_tx_dma_setup++; 3379 m_freem(*m_headp); 3380 DBG_COUNTER_INC(tx_frees); 3381 *m_headp = NULL; 3382 break; 3383 } 3384 txq->ift_map_failed++; 3385 DBG_COUNTER_INC(encap_load_mbuf_fail); 3386 DBG_COUNTER_INC(encap_txd_encap_fail); 3387 return (err); 3388 } 3389 ifsd_m[pidx] = m_head; 3390 /* 3391 * XXX assumes a 1 to 1 relationship between segments and 3392 * descriptors - this does not hold true on all drivers, e.g. 3393 * cxgb 3394 */ 3395 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3396 txq->ift_no_desc_avail++; 3397 bus_dmamap_unload(buf_tag, map); 3398 DBG_COUNTER_INC(encap_txq_avail_fail); 3399 DBG_COUNTER_INC(encap_txd_encap_fail); 3400 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3401 GROUPTASK_ENQUEUE(&txq->ift_task); 3402 return (ENOBUFS); 3403 } 3404 /* 3405 * On Intel cards we can greatly reduce the number of TX interrupts 3406 * we see by only setting report status on every Nth descriptor. 3407 * However, this also means that the driver will need to keep track 3408 * of the descriptors that RS was set on to check them for the DD bit. 3409 */ 3410 txq->ift_rs_pending += nsegs + 1; 3411 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3412 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3413 pi.ipi_flags |= IPI_TX_INTR; 3414 txq->ift_rs_pending = 0; 3415 } 3416 3417 pi.ipi_segs = segs; 3418 pi.ipi_nsegs = nsegs; 3419 3420 MPASS(pidx >= 0 && pidx < txq->ift_size); 3421 #ifdef PKT_DEBUG 3422 print_pkt(&pi); 3423 #endif 3424 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3425 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3426 DBG_COUNTER_INC(tx_encap); 3427 MPASS(pi.ipi_new_pidx < txq->ift_size); 3428 3429 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3430 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3431 ndesc += txq->ift_size; 3432 txq->ift_gen = 1; 3433 } 3434 /* 3435 * drivers can need as many as 3436 * two sentinels 3437 */ 3438 MPASS(ndesc <= pi.ipi_nsegs + 2); 3439 MPASS(pi.ipi_new_pidx != pidx); 3440 MPASS(ndesc > 0); 3441 txq->ift_in_use += ndesc; 3442 3443 /* 3444 * We update the last software descriptor again here because there may 3445 * be a sentinel and/or there may be more mbufs than segments 3446 */ 3447 txq->ift_pidx = pi.ipi_new_pidx; 3448 txq->ift_npending += pi.ipi_ndescs; 3449 } else { 3450 *m_headp = m_head = iflib_remove_mbuf(txq); 3451 if (err == EFBIG) { 3452 txq->ift_txd_encap_efbig++; 3453 if (remap < 2) { 3454 remap = 1; 3455 goto defrag; 3456 } 3457 } 3458 goto defrag_failed; 3459 } 3460 /* 3461 * err can't possibly be non-zero here, so we don't neet to test it 3462 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3463 */ 3464 return (err); 3465 3466 defrag_failed: 3467 txq->ift_mbuf_defrag_failed++; 3468 txq->ift_map_failed++; 3469 m_freem(*m_headp); 3470 DBG_COUNTER_INC(tx_frees); 3471 *m_headp = NULL; 3472 DBG_COUNTER_INC(encap_txd_encap_fail); 3473 return (ENOMEM); 3474 } 3475 3476 static void 3477 iflib_tx_desc_free(iflib_txq_t txq, int n) 3478 { 3479 uint32_t qsize, cidx, mask, gen; 3480 struct mbuf *m, **ifsd_m; 3481 bool do_prefetch; 3482 3483 cidx = txq->ift_cidx; 3484 gen = txq->ift_gen; 3485 qsize = txq->ift_size; 3486 mask = qsize-1; 3487 ifsd_m = txq->ift_sds.ifsd_m; 3488 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3489 3490 while (n-- > 0) { 3491 if (do_prefetch) { 3492 prefetch(ifsd_m[(cidx + 3) & mask]); 3493 prefetch(ifsd_m[(cidx + 4) & mask]); 3494 } 3495 if ((m = ifsd_m[cidx]) != NULL) { 3496 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3497 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3498 bus_dmamap_sync(txq->ift_tso_buf_tag, 3499 txq->ift_sds.ifsd_tso_map[cidx], 3500 BUS_DMASYNC_POSTWRITE); 3501 bus_dmamap_unload(txq->ift_tso_buf_tag, 3502 txq->ift_sds.ifsd_tso_map[cidx]); 3503 } else { 3504 bus_dmamap_sync(txq->ift_buf_tag, 3505 txq->ift_sds.ifsd_map[cidx], 3506 BUS_DMASYNC_POSTWRITE); 3507 bus_dmamap_unload(txq->ift_buf_tag, 3508 txq->ift_sds.ifsd_map[cidx]); 3509 } 3510 /* XXX we don't support any drivers that batch packets yet */ 3511 MPASS(m->m_nextpkt == NULL); 3512 m_freem(m); 3513 ifsd_m[cidx] = NULL; 3514 #if MEMORY_LOGGING 3515 txq->ift_dequeued++; 3516 #endif 3517 DBG_COUNTER_INC(tx_frees); 3518 } 3519 if (__predict_false(++cidx == qsize)) { 3520 cidx = 0; 3521 gen = 0; 3522 } 3523 } 3524 txq->ift_cidx = cidx; 3525 txq->ift_gen = gen; 3526 } 3527 3528 static __inline int 3529 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3530 { 3531 int reclaim; 3532 if_ctx_t ctx = txq->ift_ctx; 3533 3534 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3535 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3536 3537 /* 3538 * Need a rate-limiting check so that this isn't called every time 3539 */ 3540 iflib_tx_credits_update(ctx, txq); 3541 reclaim = DESC_RECLAIMABLE(txq); 3542 3543 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3544 #ifdef INVARIANTS 3545 if (iflib_verbose_debug) { 3546 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3547 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3548 reclaim, thresh); 3549 3550 } 3551 #endif 3552 return (0); 3553 } 3554 iflib_tx_desc_free(txq, reclaim); 3555 txq->ift_cleaned += reclaim; 3556 txq->ift_in_use -= reclaim; 3557 3558 return (reclaim); 3559 } 3560 3561 static struct mbuf ** 3562 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3563 { 3564 int next, size; 3565 struct mbuf **items; 3566 3567 size = r->size; 3568 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3569 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3570 3571 prefetch(items[(cidx + offset) & (size-1)]); 3572 if (remaining > 1) { 3573 prefetch2cachelines(&items[next]); 3574 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3575 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3576 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3577 } 3578 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3579 } 3580 3581 static void 3582 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3583 { 3584 3585 ifmp_ring_check_drainage(txq->ift_br, budget); 3586 } 3587 3588 static uint32_t 3589 iflib_txq_can_drain(struct ifmp_ring *r) 3590 { 3591 iflib_txq_t txq = r->cookie; 3592 if_ctx_t ctx = txq->ift_ctx; 3593 3594 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3595 return (1); 3596 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3597 BUS_DMASYNC_POSTREAD); 3598 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3599 false)); 3600 } 3601 3602 static uint32_t 3603 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3604 { 3605 iflib_txq_t txq = r->cookie; 3606 if_ctx_t ctx = txq->ift_ctx; 3607 if_t ifp = ctx->ifc_ifp; 3608 struct mbuf *m, **mp; 3609 int avail, bytes_sent, consumed, count, err, i, in_use_prev; 3610 int mcast_sent, pkt_sent, reclaimed, txq_avail; 3611 bool do_prefetch, rang, ring; 3612 3613 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3614 !LINK_ACTIVE(ctx))) { 3615 DBG_COUNTER_INC(txq_drain_notready); 3616 return (0); 3617 } 3618 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3619 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3620 avail = IDXDIFF(pidx, cidx, r->size); 3621 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3622 DBG_COUNTER_INC(txq_drain_flushing); 3623 for (i = 0; i < avail; i++) { 3624 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3625 m_free(r->items[(cidx + i) & (r->size-1)]); 3626 r->items[(cidx + i) & (r->size-1)] = NULL; 3627 } 3628 return (avail); 3629 } 3630 3631 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3632 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3633 CALLOUT_LOCK(txq); 3634 callout_stop(&txq->ift_timer); 3635 CALLOUT_UNLOCK(txq); 3636 DBG_COUNTER_INC(txq_drain_oactive); 3637 return (0); 3638 } 3639 if (reclaimed) 3640 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3641 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3642 count = MIN(avail, TX_BATCH_SIZE); 3643 #ifdef INVARIANTS 3644 if (iflib_verbose_debug) 3645 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3646 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3647 #endif 3648 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3649 txq_avail = TXQ_AVAIL(txq); 3650 err = 0; 3651 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) { 3652 int rem = do_prefetch ? count - i : 0; 3653 3654 mp = _ring_peek_one(r, cidx, i, rem); 3655 MPASS(mp != NULL && *mp != NULL); 3656 if (__predict_false(*mp == (struct mbuf *)txq)) { 3657 consumed++; 3658 continue; 3659 } 3660 in_use_prev = txq->ift_in_use; 3661 err = iflib_encap(txq, mp); 3662 if (__predict_false(err)) { 3663 /* no room - bail out */ 3664 if (err == ENOBUFS) 3665 break; 3666 consumed++; 3667 /* we can't send this packet - skip it */ 3668 continue; 3669 } 3670 consumed++; 3671 pkt_sent++; 3672 m = *mp; 3673 DBG_COUNTER_INC(tx_sent); 3674 bytes_sent += m->m_pkthdr.len; 3675 mcast_sent += !!(m->m_flags & M_MCAST); 3676 txq_avail = TXQ_AVAIL(txq); 3677 3678 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3679 ETHER_BPF_MTAP(ifp, m); 3680 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3681 break; 3682 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3683 } 3684 3685 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3686 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3687 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3688 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3689 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3690 if (mcast_sent) 3691 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3692 #ifdef INVARIANTS 3693 if (iflib_verbose_debug) 3694 printf("consumed=%d\n", consumed); 3695 #endif 3696 return (consumed); 3697 } 3698 3699 static uint32_t 3700 iflib_txq_drain_always(struct ifmp_ring *r) 3701 { 3702 return (1); 3703 } 3704 3705 static uint32_t 3706 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3707 { 3708 int i, avail; 3709 struct mbuf **mp; 3710 iflib_txq_t txq; 3711 3712 txq = r->cookie; 3713 3714 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3715 CALLOUT_LOCK(txq); 3716 callout_stop(&txq->ift_timer); 3717 CALLOUT_UNLOCK(txq); 3718 3719 avail = IDXDIFF(pidx, cidx, r->size); 3720 for (i = 0; i < avail; i++) { 3721 mp = _ring_peek_one(r, cidx, i, avail - i); 3722 if (__predict_false(*mp == (struct mbuf *)txq)) 3723 continue; 3724 m_freem(*mp); 3725 DBG_COUNTER_INC(tx_frees); 3726 } 3727 MPASS(ifmp_ring_is_stalled(r) == 0); 3728 return (avail); 3729 } 3730 3731 static void 3732 iflib_ifmp_purge(iflib_txq_t txq) 3733 { 3734 struct ifmp_ring *r; 3735 3736 r = txq->ift_br; 3737 r->drain = iflib_txq_drain_free; 3738 r->can_drain = iflib_txq_drain_always; 3739 3740 ifmp_ring_check_drainage(r, r->size); 3741 3742 r->drain = iflib_txq_drain; 3743 r->can_drain = iflib_txq_can_drain; 3744 } 3745 3746 static void 3747 _task_fn_tx(void *context) 3748 { 3749 iflib_txq_t txq = context; 3750 if_ctx_t ctx = txq->ift_ctx; 3751 #if defined(ALTQ) || defined(DEV_NETMAP) 3752 if_t ifp = ctx->ifc_ifp; 3753 #endif 3754 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3755 3756 #ifdef IFLIB_DIAGNOSTICS 3757 txq->ift_cpu_exec_count[curcpu]++; 3758 #endif 3759 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3760 return; 3761 #ifdef DEV_NETMAP 3762 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3763 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3764 BUS_DMASYNC_POSTREAD); 3765 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3766 netmap_tx_irq(ifp, txq->ift_id); 3767 if (ctx->ifc_flags & IFC_LEGACY) 3768 IFDI_INTR_ENABLE(ctx); 3769 else 3770 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3771 return; 3772 } 3773 #endif 3774 #ifdef ALTQ 3775 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3776 iflib_altq_if_start(ifp); 3777 #endif 3778 if (txq->ift_db_pending) 3779 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3780 else if (!abdicate) 3781 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3782 /* 3783 * When abdicating, we always need to check drainage, not just when we don't enqueue 3784 */ 3785 if (abdicate) 3786 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3787 if (ctx->ifc_flags & IFC_LEGACY) 3788 IFDI_INTR_ENABLE(ctx); 3789 else 3790 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3791 } 3792 3793 static void 3794 _task_fn_rx(void *context) 3795 { 3796 iflib_rxq_t rxq = context; 3797 if_ctx_t ctx = rxq->ifr_ctx; 3798 uint8_t more; 3799 uint16_t budget; 3800 #ifdef DEV_NETMAP 3801 u_int work = 0; 3802 int nmirq; 3803 #endif 3804 3805 #ifdef IFLIB_DIAGNOSTICS 3806 rxq->ifr_cpu_exec_count[curcpu]++; 3807 #endif 3808 DBG_COUNTER_INC(task_fn_rxs); 3809 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3810 return; 3811 #ifdef DEV_NETMAP 3812 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 3813 if (nmirq != NM_IRQ_PASS) { 3814 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 3815 goto skip_rxeof; 3816 } 3817 #endif 3818 budget = ctx->ifc_sysctl_rx_budget; 3819 if (budget == 0) 3820 budget = 16; /* XXX */ 3821 more = iflib_rxeof(rxq, budget); 3822 #ifdef DEV_NETMAP 3823 skip_rxeof: 3824 #endif 3825 if ((more & IFLIB_RXEOF_MORE) == 0) { 3826 if (ctx->ifc_flags & IFC_LEGACY) 3827 IFDI_INTR_ENABLE(ctx); 3828 else 3829 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3830 DBG_COUNTER_INC(rx_intr_enables); 3831 } 3832 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3833 return; 3834 3835 if (more & IFLIB_RXEOF_MORE) 3836 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3837 else if (more & IFLIB_RXEOF_EMPTY) 3838 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 3839 } 3840 3841 static void 3842 _task_fn_admin(void *context) 3843 { 3844 if_ctx_t ctx = context; 3845 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3846 iflib_txq_t txq; 3847 int i; 3848 bool oactive, running, do_reset, do_watchdog, in_detach; 3849 uint32_t reset_on = hz / 2; 3850 3851 STATE_LOCK(ctx); 3852 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3853 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3854 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3855 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3856 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3857 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3858 STATE_UNLOCK(ctx); 3859 3860 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3861 return; 3862 if (in_detach) 3863 return; 3864 3865 CTX_LOCK(ctx); 3866 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3867 CALLOUT_LOCK(txq); 3868 callout_stop(&txq->ift_timer); 3869 CALLOUT_UNLOCK(txq); 3870 } 3871 if (do_watchdog) { 3872 ctx->ifc_watchdog_events++; 3873 IFDI_WATCHDOG_RESET(ctx); 3874 } 3875 IFDI_UPDATE_ADMIN_STATUS(ctx); 3876 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3877 #ifdef DEV_NETMAP 3878 reset_on = hz / 2; 3879 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3880 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 3881 #endif 3882 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3883 } 3884 IFDI_LINK_INTR_ENABLE(ctx); 3885 if (do_reset) 3886 iflib_if_init_locked(ctx); 3887 CTX_UNLOCK(ctx); 3888 3889 if (LINK_ACTIVE(ctx) == 0) 3890 return; 3891 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3892 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3893 } 3894 3895 3896 static void 3897 _task_fn_iov(void *context) 3898 { 3899 if_ctx_t ctx = context; 3900 3901 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3902 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3903 return; 3904 3905 CTX_LOCK(ctx); 3906 IFDI_VFLR_HANDLE(ctx); 3907 CTX_UNLOCK(ctx); 3908 } 3909 3910 static int 3911 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3912 { 3913 int err; 3914 if_int_delay_info_t info; 3915 if_ctx_t ctx; 3916 3917 info = (if_int_delay_info_t)arg1; 3918 ctx = info->iidi_ctx; 3919 info->iidi_req = req; 3920 info->iidi_oidp = oidp; 3921 CTX_LOCK(ctx); 3922 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3923 CTX_UNLOCK(ctx); 3924 return (err); 3925 } 3926 3927 /********************************************************************* 3928 * 3929 * IFNET FUNCTIONS 3930 * 3931 **********************************************************************/ 3932 3933 static void 3934 iflib_if_init_locked(if_ctx_t ctx) 3935 { 3936 iflib_stop(ctx); 3937 iflib_init_locked(ctx); 3938 } 3939 3940 3941 static void 3942 iflib_if_init(void *arg) 3943 { 3944 if_ctx_t ctx = arg; 3945 3946 CTX_LOCK(ctx); 3947 iflib_if_init_locked(ctx); 3948 CTX_UNLOCK(ctx); 3949 } 3950 3951 static int 3952 iflib_if_transmit(if_t ifp, struct mbuf *m) 3953 { 3954 if_ctx_t ctx = if_getsoftc(ifp); 3955 3956 iflib_txq_t txq; 3957 int err, qidx; 3958 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3959 3960 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3961 DBG_COUNTER_INC(tx_frees); 3962 m_freem(m); 3963 return (ENETDOWN); 3964 } 3965 3966 MPASS(m->m_nextpkt == NULL); 3967 /* ALTQ-enabled interfaces always use queue 0. */ 3968 qidx = 0; 3969 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3970 qidx = QIDX(ctx, m); 3971 /* 3972 * XXX calculate buf_ring based on flowid (divvy up bits?) 3973 */ 3974 txq = &ctx->ifc_txqs[qidx]; 3975 3976 #ifdef DRIVER_BACKPRESSURE 3977 if (txq->ift_closed) { 3978 while (m != NULL) { 3979 next = m->m_nextpkt; 3980 m->m_nextpkt = NULL; 3981 m_freem(m); 3982 DBG_COUNTER_INC(tx_frees); 3983 m = next; 3984 } 3985 return (ENOBUFS); 3986 } 3987 #endif 3988 #ifdef notyet 3989 qidx = count = 0; 3990 mp = marr; 3991 next = m; 3992 do { 3993 count++; 3994 next = next->m_nextpkt; 3995 } while (next != NULL); 3996 3997 if (count > nitems(marr)) 3998 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3999 /* XXX check nextpkt */ 4000 m_freem(m); 4001 /* XXX simplify for now */ 4002 DBG_COUNTER_INC(tx_frees); 4003 return (ENOBUFS); 4004 } 4005 for (next = m, i = 0; next != NULL; i++) { 4006 mp[i] = next; 4007 next = next->m_nextpkt; 4008 mp[i]->m_nextpkt = NULL; 4009 } 4010 #endif 4011 DBG_COUNTER_INC(tx_seen); 4012 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4013 4014 if (abdicate) 4015 GROUPTASK_ENQUEUE(&txq->ift_task); 4016 if (err) { 4017 if (!abdicate) 4018 GROUPTASK_ENQUEUE(&txq->ift_task); 4019 /* support forthcoming later */ 4020 #ifdef DRIVER_BACKPRESSURE 4021 txq->ift_closed = TRUE; 4022 #endif 4023 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4024 m_freem(m); 4025 DBG_COUNTER_INC(tx_frees); 4026 } 4027 4028 return (err); 4029 } 4030 4031 #ifdef ALTQ 4032 /* 4033 * The overall approach to integrating iflib with ALTQ is to continue to use 4034 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4035 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4036 * is redundant/unnecessary, but doing so minimizes the amount of 4037 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4038 * redundantly queueing to an intermediate mp_ring is swamped by the 4039 * performance limitations inherent in using ALTQ. 4040 * 4041 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4042 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4043 * given interface. If ALTQ is enabled for an interface, then all 4044 * transmitted packets for that interface will be submitted to the ALTQ 4045 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4046 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4047 * update stats that the iflib machinery handles, and which is sensitve to 4048 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4049 * will be installed as the start routine for use by ALTQ facilities that 4050 * need to trigger queue drains on a scheduled basis. 4051 * 4052 */ 4053 static void 4054 iflib_altq_if_start(if_t ifp) 4055 { 4056 struct ifaltq *ifq = &ifp->if_snd; 4057 struct mbuf *m; 4058 4059 IFQ_LOCK(ifq); 4060 IFQ_DEQUEUE_NOLOCK(ifq, m); 4061 while (m != NULL) { 4062 iflib_if_transmit(ifp, m); 4063 IFQ_DEQUEUE_NOLOCK(ifq, m); 4064 } 4065 IFQ_UNLOCK(ifq); 4066 } 4067 4068 static int 4069 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4070 { 4071 int err; 4072 4073 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4074 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4075 if (err == 0) 4076 iflib_altq_if_start(ifp); 4077 } else 4078 err = iflib_if_transmit(ifp, m); 4079 4080 return (err); 4081 } 4082 #endif /* ALTQ */ 4083 4084 static void 4085 iflib_if_qflush(if_t ifp) 4086 { 4087 if_ctx_t ctx = if_getsoftc(ifp); 4088 iflib_txq_t txq = ctx->ifc_txqs; 4089 int i; 4090 4091 STATE_LOCK(ctx); 4092 ctx->ifc_flags |= IFC_QFLUSH; 4093 STATE_UNLOCK(ctx); 4094 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4095 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4096 iflib_txq_check_drain(txq, 0); 4097 STATE_LOCK(ctx); 4098 ctx->ifc_flags &= ~IFC_QFLUSH; 4099 STATE_UNLOCK(ctx); 4100 4101 /* 4102 * When ALTQ is enabled, this will also take care of purging the 4103 * ALTQ queue(s). 4104 */ 4105 if_qflush(ifp); 4106 } 4107 4108 4109 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4110 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4111 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4112 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP) 4113 4114 static int 4115 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4116 { 4117 if_ctx_t ctx = if_getsoftc(ifp); 4118 struct ifreq *ifr = (struct ifreq *)data; 4119 #if defined(INET) || defined(INET6) 4120 struct ifaddr *ifa = (struct ifaddr *)data; 4121 #endif 4122 bool avoid_reset = false; 4123 int err = 0, reinit = 0, bits; 4124 4125 switch (command) { 4126 case SIOCSIFADDR: 4127 #ifdef INET 4128 if (ifa->ifa_addr->sa_family == AF_INET) 4129 avoid_reset = true; 4130 #endif 4131 #ifdef INET6 4132 if (ifa->ifa_addr->sa_family == AF_INET6) 4133 avoid_reset = true; 4134 #endif 4135 /* 4136 ** Calling init results in link renegotiation, 4137 ** so we avoid doing it when possible. 4138 */ 4139 if (avoid_reset) { 4140 if_setflagbits(ifp, IFF_UP,0); 4141 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4142 reinit = 1; 4143 #ifdef INET 4144 if (!(if_getflags(ifp) & IFF_NOARP)) 4145 arp_ifinit(ifp, ifa); 4146 #endif 4147 } else 4148 err = ether_ioctl(ifp, command, data); 4149 break; 4150 case SIOCSIFMTU: 4151 CTX_LOCK(ctx); 4152 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4153 CTX_UNLOCK(ctx); 4154 break; 4155 } 4156 bits = if_getdrvflags(ifp); 4157 /* stop the driver and free any clusters before proceeding */ 4158 iflib_stop(ctx); 4159 4160 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4161 STATE_LOCK(ctx); 4162 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4163 ctx->ifc_flags |= IFC_MULTISEG; 4164 else 4165 ctx->ifc_flags &= ~IFC_MULTISEG; 4166 STATE_UNLOCK(ctx); 4167 err = if_setmtu(ifp, ifr->ifr_mtu); 4168 } 4169 iflib_init_locked(ctx); 4170 STATE_LOCK(ctx); 4171 if_setdrvflags(ifp, bits); 4172 STATE_UNLOCK(ctx); 4173 CTX_UNLOCK(ctx); 4174 break; 4175 case SIOCSIFFLAGS: 4176 CTX_LOCK(ctx); 4177 if (if_getflags(ifp) & IFF_UP) { 4178 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4179 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4180 (IFF_PROMISC | IFF_ALLMULTI)) { 4181 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4182 } 4183 } else 4184 reinit = 1; 4185 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4186 iflib_stop(ctx); 4187 } 4188 ctx->ifc_if_flags = if_getflags(ifp); 4189 CTX_UNLOCK(ctx); 4190 break; 4191 case SIOCADDMULTI: 4192 case SIOCDELMULTI: 4193 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4194 CTX_LOCK(ctx); 4195 IFDI_INTR_DISABLE(ctx); 4196 IFDI_MULTI_SET(ctx); 4197 IFDI_INTR_ENABLE(ctx); 4198 CTX_UNLOCK(ctx); 4199 } 4200 break; 4201 case SIOCSIFMEDIA: 4202 CTX_LOCK(ctx); 4203 IFDI_MEDIA_SET(ctx); 4204 CTX_UNLOCK(ctx); 4205 /* FALLTHROUGH */ 4206 case SIOCGIFMEDIA: 4207 case SIOCGIFXMEDIA: 4208 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4209 break; 4210 case SIOCGI2C: 4211 { 4212 struct ifi2creq i2c; 4213 4214 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4215 if (err != 0) 4216 break; 4217 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4218 err = EINVAL; 4219 break; 4220 } 4221 if (i2c.len > sizeof(i2c.data)) { 4222 err = EINVAL; 4223 break; 4224 } 4225 4226 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4227 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4228 sizeof(i2c)); 4229 break; 4230 } 4231 case SIOCSIFCAP: 4232 { 4233 int mask, setmask, oldmask; 4234 4235 oldmask = if_getcapenable(ifp); 4236 mask = ifr->ifr_reqcap ^ oldmask; 4237 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP; 4238 setmask = 0; 4239 #ifdef TCP_OFFLOAD 4240 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4241 #endif 4242 setmask |= (mask & IFCAP_FLAGS); 4243 setmask |= (mask & IFCAP_WOL); 4244 4245 /* 4246 * If any RX csum has changed, change all the ones that 4247 * are supported by the driver. 4248 */ 4249 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4250 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4251 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4252 } 4253 4254 /* 4255 * want to ensure that traffic has stopped before we change any of the flags 4256 */ 4257 if (setmask) { 4258 CTX_LOCK(ctx); 4259 bits = if_getdrvflags(ifp); 4260 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4261 iflib_stop(ctx); 4262 STATE_LOCK(ctx); 4263 if_togglecapenable(ifp, setmask); 4264 STATE_UNLOCK(ctx); 4265 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4266 iflib_init_locked(ctx); 4267 STATE_LOCK(ctx); 4268 if_setdrvflags(ifp, bits); 4269 STATE_UNLOCK(ctx); 4270 CTX_UNLOCK(ctx); 4271 } 4272 if_vlancap(ifp); 4273 break; 4274 } 4275 case SIOCGPRIVATE_0: 4276 case SIOCSDRVSPEC: 4277 case SIOCGDRVSPEC: 4278 CTX_LOCK(ctx); 4279 err = IFDI_PRIV_IOCTL(ctx, command, data); 4280 CTX_UNLOCK(ctx); 4281 break; 4282 default: 4283 err = ether_ioctl(ifp, command, data); 4284 break; 4285 } 4286 if (reinit) 4287 iflib_if_init(ctx); 4288 return (err); 4289 } 4290 4291 static uint64_t 4292 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4293 { 4294 if_ctx_t ctx = if_getsoftc(ifp); 4295 4296 return (IFDI_GET_COUNTER(ctx, cnt)); 4297 } 4298 4299 /********************************************************************* 4300 * 4301 * OTHER FUNCTIONS EXPORTED TO THE STACK 4302 * 4303 **********************************************************************/ 4304 4305 static void 4306 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4307 { 4308 if_ctx_t ctx = if_getsoftc(ifp); 4309 4310 if ((void *)ctx != arg) 4311 return; 4312 4313 if ((vtag == 0) || (vtag > 4095)) 4314 return; 4315 4316 if (iflib_in_detach(ctx)) 4317 return; 4318 4319 CTX_LOCK(ctx); 4320 /* Driver may need all untagged packets to be flushed */ 4321 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4322 iflib_stop(ctx); 4323 IFDI_VLAN_REGISTER(ctx, vtag); 4324 /* Re-init to load the changes, if required */ 4325 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4326 iflib_init_locked(ctx); 4327 CTX_UNLOCK(ctx); 4328 } 4329 4330 static void 4331 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4332 { 4333 if_ctx_t ctx = if_getsoftc(ifp); 4334 4335 if ((void *)ctx != arg) 4336 return; 4337 4338 if ((vtag == 0) || (vtag > 4095)) 4339 return; 4340 4341 CTX_LOCK(ctx); 4342 /* Driver may need all tagged packets to be flushed */ 4343 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4344 iflib_stop(ctx); 4345 IFDI_VLAN_UNREGISTER(ctx, vtag); 4346 /* Re-init to load the changes, if required */ 4347 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4348 iflib_init_locked(ctx); 4349 CTX_UNLOCK(ctx); 4350 } 4351 4352 static void 4353 iflib_led_func(void *arg, int onoff) 4354 { 4355 if_ctx_t ctx = arg; 4356 4357 CTX_LOCK(ctx); 4358 IFDI_LED_FUNC(ctx, onoff); 4359 CTX_UNLOCK(ctx); 4360 } 4361 4362 /********************************************************************* 4363 * 4364 * BUS FUNCTION DEFINITIONS 4365 * 4366 **********************************************************************/ 4367 4368 int 4369 iflib_device_probe(device_t dev) 4370 { 4371 const pci_vendor_info_t *ent; 4372 if_shared_ctx_t sctx; 4373 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4374 uint16_t pci_vendor_id; 4375 4376 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4377 return (ENOTSUP); 4378 4379 pci_vendor_id = pci_get_vendor(dev); 4380 pci_device_id = pci_get_device(dev); 4381 pci_subvendor_id = pci_get_subvendor(dev); 4382 pci_subdevice_id = pci_get_subdevice(dev); 4383 pci_rev_id = pci_get_revid(dev); 4384 if (sctx->isc_parse_devinfo != NULL) 4385 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4386 4387 ent = sctx->isc_vendor_info; 4388 while (ent->pvi_vendor_id != 0) { 4389 if (pci_vendor_id != ent->pvi_vendor_id) { 4390 ent++; 4391 continue; 4392 } 4393 if ((pci_device_id == ent->pvi_device_id) && 4394 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4395 (ent->pvi_subvendor_id == 0)) && 4396 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4397 (ent->pvi_subdevice_id == 0)) && 4398 ((pci_rev_id == ent->pvi_rev_id) || 4399 (ent->pvi_rev_id == 0))) { 4400 4401 device_set_desc_copy(dev, ent->pvi_name); 4402 /* this needs to be changed to zero if the bus probing code 4403 * ever stops re-probing on best match because the sctx 4404 * may have its values over written by register calls 4405 * in subsequent probes 4406 */ 4407 return (BUS_PROBE_DEFAULT); 4408 } 4409 ent++; 4410 } 4411 return (ENXIO); 4412 } 4413 4414 int 4415 iflib_device_probe_vendor(device_t dev) 4416 { 4417 int probe; 4418 4419 probe = iflib_device_probe(dev); 4420 if (probe == BUS_PROBE_DEFAULT) 4421 return (BUS_PROBE_VENDOR); 4422 else 4423 return (probe); 4424 } 4425 4426 static void 4427 iflib_reset_qvalues(if_ctx_t ctx) 4428 { 4429 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4430 if_shared_ctx_t sctx = ctx->ifc_sctx; 4431 device_t dev = ctx->ifc_dev; 4432 int i; 4433 4434 if (ctx->ifc_sysctl_ntxqs != 0) 4435 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4436 if (ctx->ifc_sysctl_nrxqs != 0) 4437 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4438 4439 for (i = 0; i < sctx->isc_ntxqs; i++) { 4440 if (ctx->ifc_sysctl_ntxds[i] != 0) 4441 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4442 else 4443 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4444 } 4445 4446 for (i = 0; i < sctx->isc_nrxqs; i++) { 4447 if (ctx->ifc_sysctl_nrxds[i] != 0) 4448 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4449 else 4450 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4451 } 4452 4453 for (i = 0; i < sctx->isc_nrxqs; i++) { 4454 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4455 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4456 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4457 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4458 } 4459 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4460 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4461 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4462 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4463 } 4464 if (!powerof2(scctx->isc_nrxd[i])) { 4465 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4466 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4467 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4468 } 4469 } 4470 4471 for (i = 0; i < sctx->isc_ntxqs; i++) { 4472 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4473 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4474 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4475 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4476 } 4477 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4478 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4479 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4480 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4481 } 4482 if (!powerof2(scctx->isc_ntxd[i])) { 4483 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4484 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4485 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4486 } 4487 } 4488 } 4489 4490 static void 4491 iflib_add_pfil(if_ctx_t ctx) 4492 { 4493 struct pfil_head *pfil; 4494 struct pfil_head_args pa; 4495 iflib_rxq_t rxq; 4496 int i; 4497 4498 pa.pa_version = PFIL_VERSION; 4499 pa.pa_flags = PFIL_IN; 4500 pa.pa_type = PFIL_TYPE_ETHERNET; 4501 pa.pa_headname = ctx->ifc_ifp->if_xname; 4502 pfil = pfil_head_register(&pa); 4503 4504 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4505 rxq->pfil = pfil; 4506 } 4507 } 4508 4509 static void 4510 iflib_rem_pfil(if_ctx_t ctx) 4511 { 4512 struct pfil_head *pfil; 4513 iflib_rxq_t rxq; 4514 int i; 4515 4516 rxq = ctx->ifc_rxqs; 4517 pfil = rxq->pfil; 4518 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4519 rxq->pfil = NULL; 4520 } 4521 pfil_head_unregister(pfil); 4522 } 4523 4524 static uint16_t 4525 get_ctx_core_offset(if_ctx_t ctx) 4526 { 4527 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4528 struct cpu_offset *op; 4529 uint16_t qc; 4530 uint16_t ret = ctx->ifc_sysctl_core_offset; 4531 4532 if (ret != CORE_OFFSET_UNSPECIFIED) 4533 return (ret); 4534 4535 if (ctx->ifc_sysctl_separate_txrx) 4536 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets; 4537 else 4538 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets); 4539 4540 mtx_lock(&cpu_offset_mtx); 4541 SLIST_FOREACH(op, &cpu_offsets, entries) { 4542 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4543 ret = op->offset; 4544 op->offset += qc; 4545 MPASS(op->refcount < UINT_MAX); 4546 op->refcount++; 4547 break; 4548 } 4549 } 4550 if (ret == CORE_OFFSET_UNSPECIFIED) { 4551 ret = 0; 4552 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4553 M_NOWAIT | M_ZERO); 4554 if (op == NULL) { 4555 device_printf(ctx->ifc_dev, 4556 "allocation for cpu offset failed.\n"); 4557 } else { 4558 op->offset = qc; 4559 op->refcount = 1; 4560 CPU_COPY(&ctx->ifc_cpus, &op->set); 4561 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4562 } 4563 } 4564 mtx_unlock(&cpu_offset_mtx); 4565 4566 return (ret); 4567 } 4568 4569 static void 4570 unref_ctx_core_offset(if_ctx_t ctx) 4571 { 4572 struct cpu_offset *op, *top; 4573 4574 mtx_lock(&cpu_offset_mtx); 4575 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4576 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4577 MPASS(op->refcount > 0); 4578 op->refcount--; 4579 if (op->refcount == 0) { 4580 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4581 free(op, M_IFLIB); 4582 } 4583 break; 4584 } 4585 } 4586 mtx_unlock(&cpu_offset_mtx); 4587 } 4588 4589 int 4590 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4591 { 4592 if_ctx_t ctx; 4593 if_t ifp; 4594 if_softc_ctx_t scctx; 4595 kobjop_desc_t kobj_desc; 4596 kobj_method_t *kobj_method; 4597 int err, msix, rid; 4598 uint16_t main_rxq, main_txq; 4599 4600 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4601 4602 if (sc == NULL) { 4603 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4604 device_set_softc(dev, ctx); 4605 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4606 } 4607 4608 ctx->ifc_sctx = sctx; 4609 ctx->ifc_dev = dev; 4610 ctx->ifc_softc = sc; 4611 4612 if ((err = iflib_register(ctx)) != 0) { 4613 device_printf(dev, "iflib_register failed %d\n", err); 4614 goto fail_ctx_free; 4615 } 4616 iflib_add_device_sysctl_pre(ctx); 4617 4618 scctx = &ctx->ifc_softc_ctx; 4619 ifp = ctx->ifc_ifp; 4620 4621 iflib_reset_qvalues(ctx); 4622 CTX_LOCK(ctx); 4623 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4624 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4625 goto fail_unlock; 4626 } 4627 _iflib_pre_assert(scctx); 4628 ctx->ifc_txrx = *scctx->isc_txrx; 4629 4630 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 4631 ctx->ifc_mediap = scctx->isc_media; 4632 4633 #ifdef INVARIANTS 4634 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4635 MPASS(scctx->isc_tx_csum_flags); 4636 #endif 4637 4638 if_setcapabilities(ifp, 4639 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP); 4640 if_setcapenable(ifp, 4641 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP); 4642 4643 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4644 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4645 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4646 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4647 4648 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4649 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4650 4651 /* XXX change for per-queue sizes */ 4652 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4653 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4654 4655 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4656 MAX_SINGLE_PACKET_FRACTION) 4657 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4658 MAX_SINGLE_PACKET_FRACTION); 4659 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4660 MAX_SINGLE_PACKET_FRACTION) 4661 scctx->isc_tx_tso_segments_max = max(1, 4662 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4663 4664 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4665 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4666 /* 4667 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4668 * but some MACs do. 4669 */ 4670 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4671 IP_MAXPACKET)); 4672 /* 4673 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4674 * into account. In the worst case, each of these calls will 4675 * add another mbuf and, thus, the requirement for another DMA 4676 * segment. So for best performance, it doesn't make sense to 4677 * advertize a maximum of TSO segments that typically will 4678 * require defragmentation in iflib_encap(). 4679 */ 4680 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4681 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4682 } 4683 if (scctx->isc_rss_table_size == 0) 4684 scctx->isc_rss_table_size = 64; 4685 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4686 4687 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4688 /* XXX format name */ 4689 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4690 NULL, NULL, "admin"); 4691 4692 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4693 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4694 device_printf(dev, "Unable to fetch CPU list\n"); 4695 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4696 } 4697 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4698 4699 /* 4700 ** Now set up MSI or MSI-X, should return us the number of supported 4701 ** vectors (will be 1 for a legacy interrupt and MSI). 4702 */ 4703 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4704 msix = scctx->isc_vectors; 4705 } else if (scctx->isc_msix_bar != 0) 4706 /* 4707 * The simple fact that isc_msix_bar is not 0 does not mean we 4708 * we have a good value there that is known to work. 4709 */ 4710 msix = iflib_msix_init(ctx); 4711 else { 4712 scctx->isc_vectors = 1; 4713 scctx->isc_ntxqsets = 1; 4714 scctx->isc_nrxqsets = 1; 4715 scctx->isc_intr = IFLIB_INTR_LEGACY; 4716 msix = 0; 4717 } 4718 /* Get memory for the station queues */ 4719 if ((err = iflib_queues_alloc(ctx))) { 4720 device_printf(dev, "Unable to allocate queue memory\n"); 4721 goto fail_intr_free; 4722 } 4723 4724 if ((err = iflib_qset_structures_setup(ctx))) 4725 goto fail_queues; 4726 4727 /* 4728 * Now that we know how many queues there are, get the core offset. 4729 */ 4730 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 4731 4732 if (msix > 1) { 4733 /* 4734 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 4735 * aren't the default NULL implementation. 4736 */ 4737 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 4738 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4739 kobj_desc); 4740 if (kobj_method == &kobj_desc->deflt) { 4741 device_printf(dev, 4742 "MSI-X requires ifdi_rx_queue_intr_enable method"); 4743 err = EOPNOTSUPP; 4744 goto fail_queues; 4745 } 4746 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 4747 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4748 kobj_desc); 4749 if (kobj_method == &kobj_desc->deflt) { 4750 device_printf(dev, 4751 "MSI-X requires ifdi_tx_queue_intr_enable method"); 4752 err = EOPNOTSUPP; 4753 goto fail_queues; 4754 } 4755 4756 /* 4757 * Assign the MSI-X vectors. 4758 * Note that the default NULL ifdi_msix_intr_assign method will 4759 * fail here, too. 4760 */ 4761 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 4762 if (err != 0) { 4763 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 4764 err); 4765 goto fail_queues; 4766 } 4767 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 4768 rid = 0; 4769 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4770 MPASS(msix == 1); 4771 rid = 1; 4772 } 4773 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4774 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4775 goto fail_queues; 4776 } 4777 } else { 4778 device_printf(dev, 4779 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 4780 err = ENODEV; 4781 goto fail_intr_free; 4782 } 4783 4784 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4785 4786 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4787 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4788 goto fail_detach; 4789 } 4790 4791 /* 4792 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4793 * This must appear after the call to ether_ifattach() because 4794 * ether_ifattach() sets if_hdrlen to the default value. 4795 */ 4796 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4797 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4798 4799 if ((err = iflib_netmap_attach(ctx))) { 4800 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4801 goto fail_detach; 4802 } 4803 *ctxp = ctx; 4804 4805 DEBUGNET_SET(ctx->ifc_ifp, iflib); 4806 4807 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4808 iflib_add_device_sysctl_post(ctx); 4809 iflib_add_pfil(ctx); 4810 ctx->ifc_flags |= IFC_INIT_DONE; 4811 CTX_UNLOCK(ctx); 4812 4813 return (0); 4814 4815 fail_detach: 4816 ether_ifdetach(ctx->ifc_ifp); 4817 fail_intr_free: 4818 iflib_free_intr_mem(ctx); 4819 fail_queues: 4820 iflib_tx_structures_free(ctx); 4821 iflib_rx_structures_free(ctx); 4822 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task); 4823 IFDI_DETACH(ctx); 4824 fail_unlock: 4825 CTX_UNLOCK(ctx); 4826 iflib_deregister(ctx); 4827 fail_ctx_free: 4828 device_set_softc(ctx->ifc_dev, NULL); 4829 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4830 free(ctx->ifc_softc, M_IFLIB); 4831 free(ctx, M_IFLIB); 4832 return (err); 4833 } 4834 4835 int 4836 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4837 struct iflib_cloneattach_ctx *clctx) 4838 { 4839 int err; 4840 if_ctx_t ctx; 4841 if_t ifp; 4842 if_softc_ctx_t scctx; 4843 int i; 4844 void *sc; 4845 uint16_t main_txq; 4846 uint16_t main_rxq; 4847 4848 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4849 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4850 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4851 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4852 ctx->ifc_flags |= IFC_PSEUDO; 4853 4854 ctx->ifc_sctx = sctx; 4855 ctx->ifc_softc = sc; 4856 ctx->ifc_dev = dev; 4857 4858 if ((err = iflib_register(ctx)) != 0) { 4859 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4860 goto fail_ctx_free; 4861 } 4862 iflib_add_device_sysctl_pre(ctx); 4863 4864 scctx = &ctx->ifc_softc_ctx; 4865 ifp = ctx->ifc_ifp; 4866 4867 iflib_reset_qvalues(ctx); 4868 CTX_LOCK(ctx); 4869 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4870 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4871 goto fail_unlock; 4872 } 4873 if (sctx->isc_flags & IFLIB_GEN_MAC) 4874 ether_gen_addr(ifp, &ctx->ifc_mac); 4875 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4876 clctx->cc_params)) != 0) { 4877 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4878 goto fail_unlock; 4879 } 4880 #ifdef INVARIANTS 4881 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4882 MPASS(scctx->isc_tx_csum_flags); 4883 #endif 4884 4885 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4886 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4887 4888 ifp->if_flags |= IFF_NOGROUP; 4889 if (sctx->isc_flags & IFLIB_PSEUDO) { 4890 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4891 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4892 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) { 4893 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4894 } else { 4895 if_attach(ctx->ifc_ifp); 4896 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t)); 4897 } 4898 4899 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4900 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4901 goto fail_detach; 4902 } 4903 *ctxp = ctx; 4904 4905 /* 4906 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4907 * This must appear after the call to ether_ifattach() because 4908 * ether_ifattach() sets if_hdrlen to the default value. 4909 */ 4910 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4911 if_setifheaderlen(ifp, 4912 sizeof(struct ether_vlan_header)); 4913 4914 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4915 iflib_add_device_sysctl_post(ctx); 4916 ctx->ifc_flags |= IFC_INIT_DONE; 4917 CTX_UNLOCK(ctx); 4918 return (0); 4919 } 4920 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4921 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4922 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4923 4924 _iflib_pre_assert(scctx); 4925 ctx->ifc_txrx = *scctx->isc_txrx; 4926 4927 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4928 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4929 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4930 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4931 4932 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4933 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4934 4935 /* XXX change for per-queue sizes */ 4936 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4937 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4938 4939 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4940 MAX_SINGLE_PACKET_FRACTION) 4941 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4942 MAX_SINGLE_PACKET_FRACTION); 4943 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4944 MAX_SINGLE_PACKET_FRACTION) 4945 scctx->isc_tx_tso_segments_max = max(1, 4946 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4947 4948 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4949 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4950 /* 4951 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4952 * but some MACs do. 4953 */ 4954 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4955 IP_MAXPACKET)); 4956 /* 4957 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4958 * into account. In the worst case, each of these calls will 4959 * add another mbuf and, thus, the requirement for another DMA 4960 * segment. So for best performance, it doesn't make sense to 4961 * advertize a maximum of TSO segments that typically will 4962 * require defragmentation in iflib_encap(). 4963 */ 4964 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4965 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4966 } 4967 if (scctx->isc_rss_table_size == 0) 4968 scctx->isc_rss_table_size = 64; 4969 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4970 4971 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4972 /* XXX format name */ 4973 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4974 NULL, NULL, "admin"); 4975 4976 /* XXX --- can support > 1 -- but keep it simple for now */ 4977 scctx->isc_intr = IFLIB_INTR_LEGACY; 4978 4979 /* Get memory for the station queues */ 4980 if ((err = iflib_queues_alloc(ctx))) { 4981 device_printf(dev, "Unable to allocate queue memory\n"); 4982 goto fail_iflib_detach; 4983 } 4984 4985 if ((err = iflib_qset_structures_setup(ctx))) { 4986 device_printf(dev, "qset structure setup failed %d\n", err); 4987 goto fail_queues; 4988 } 4989 4990 /* 4991 * XXX What if anything do we want to do about interrupts? 4992 */ 4993 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4994 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4995 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4996 goto fail_detach; 4997 } 4998 4999 /* 5000 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5001 * This must appear after the call to ether_ifattach() because 5002 * ether_ifattach() sets if_hdrlen to the default value. 5003 */ 5004 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5005 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5006 5007 /* XXX handle more than one queue */ 5008 for (i = 0; i < scctx->isc_nrxqsets; i++) 5009 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 5010 5011 *ctxp = ctx; 5012 5013 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5014 iflib_add_device_sysctl_post(ctx); 5015 ctx->ifc_flags |= IFC_INIT_DONE; 5016 CTX_UNLOCK(ctx); 5017 5018 return (0); 5019 fail_detach: 5020 ether_ifdetach(ctx->ifc_ifp); 5021 fail_queues: 5022 iflib_tx_structures_free(ctx); 5023 iflib_rx_structures_free(ctx); 5024 fail_iflib_detach: 5025 IFDI_DETACH(ctx); 5026 fail_unlock: 5027 CTX_UNLOCK(ctx); 5028 iflib_deregister(ctx); 5029 fail_ctx_free: 5030 free(ctx->ifc_softc, M_IFLIB); 5031 free(ctx, M_IFLIB); 5032 return (err); 5033 } 5034 5035 int 5036 iflib_pseudo_deregister(if_ctx_t ctx) 5037 { 5038 if_t ifp = ctx->ifc_ifp; 5039 if_shared_ctx_t sctx = ctx->ifc_sctx; 5040 iflib_txq_t txq; 5041 iflib_rxq_t rxq; 5042 int i, j; 5043 struct taskqgroup *tqg; 5044 iflib_fl_t fl; 5045 5046 /* Unregister VLAN event handlers early */ 5047 iflib_unregister_vlan_handlers(ctx); 5048 5049 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5050 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) { 5051 bpfdetach(ifp); 5052 if_detach(ifp); 5053 } else { 5054 ether_ifdetach(ifp); 5055 } 5056 /* XXX drain any dependent tasks */ 5057 tqg = qgroup_if_io_tqg; 5058 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5059 callout_drain(&txq->ift_timer); 5060 if (txq->ift_task.gt_uniq != NULL) 5061 taskqgroup_detach(tqg, &txq->ift_task); 5062 } 5063 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5064 callout_drain(&rxq->ifr_watchdog); 5065 if (rxq->ifr_task.gt_uniq != NULL) 5066 taskqgroup_detach(tqg, &rxq->ifr_task); 5067 5068 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5069 free(fl->ifl_rx_bitmap, M_IFLIB); 5070 } 5071 tqg = qgroup_if_config_tqg; 5072 if (ctx->ifc_admin_task.gt_uniq != NULL) 5073 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5074 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5075 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5076 5077 iflib_tx_structures_free(ctx); 5078 iflib_rx_structures_free(ctx); 5079 5080 iflib_deregister(ctx); 5081 5082 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5083 free(ctx->ifc_softc, M_IFLIB); 5084 free(ctx, M_IFLIB); 5085 return (0); 5086 } 5087 5088 int 5089 iflib_device_attach(device_t dev) 5090 { 5091 if_ctx_t ctx; 5092 if_shared_ctx_t sctx; 5093 5094 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5095 return (ENOTSUP); 5096 5097 pci_enable_busmaster(dev); 5098 5099 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5100 } 5101 5102 int 5103 iflib_device_deregister(if_ctx_t ctx) 5104 { 5105 if_t ifp = ctx->ifc_ifp; 5106 iflib_txq_t txq; 5107 iflib_rxq_t rxq; 5108 device_t dev = ctx->ifc_dev; 5109 int i, j; 5110 struct taskqgroup *tqg; 5111 iflib_fl_t fl; 5112 5113 /* Make sure VLANS are not using driver */ 5114 if (if_vlantrunkinuse(ifp)) { 5115 device_printf(dev, "Vlan in use, detach first\n"); 5116 return (EBUSY); 5117 } 5118 #ifdef PCI_IOV 5119 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5120 device_printf(dev, "SR-IOV in use; detach first.\n"); 5121 return (EBUSY); 5122 } 5123 #endif 5124 5125 STATE_LOCK(ctx); 5126 ctx->ifc_flags |= IFC_IN_DETACH; 5127 STATE_UNLOCK(ctx); 5128 5129 /* Unregister VLAN handlers before calling iflib_stop() */ 5130 iflib_unregister_vlan_handlers(ctx); 5131 5132 iflib_netmap_detach(ifp); 5133 ether_ifdetach(ifp); 5134 5135 CTX_LOCK(ctx); 5136 iflib_stop(ctx); 5137 CTX_UNLOCK(ctx); 5138 5139 iflib_rem_pfil(ctx); 5140 if (ctx->ifc_led_dev != NULL) 5141 led_destroy(ctx->ifc_led_dev); 5142 /* XXX drain any dependent tasks */ 5143 tqg = qgroup_if_io_tqg; 5144 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5145 callout_drain(&txq->ift_timer); 5146 if (txq->ift_task.gt_uniq != NULL) 5147 taskqgroup_detach(tqg, &txq->ift_task); 5148 } 5149 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5150 if (rxq->ifr_task.gt_uniq != NULL) 5151 taskqgroup_detach(tqg, &rxq->ifr_task); 5152 5153 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5154 free(fl->ifl_rx_bitmap, M_IFLIB); 5155 } 5156 tqg = qgroup_if_config_tqg; 5157 if (ctx->ifc_admin_task.gt_uniq != NULL) 5158 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5159 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5160 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5161 CTX_LOCK(ctx); 5162 IFDI_DETACH(ctx); 5163 CTX_UNLOCK(ctx); 5164 5165 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5166 iflib_free_intr_mem(ctx); 5167 5168 bus_generic_detach(dev); 5169 5170 iflib_tx_structures_free(ctx); 5171 iflib_rx_structures_free(ctx); 5172 5173 iflib_deregister(ctx); 5174 5175 device_set_softc(ctx->ifc_dev, NULL); 5176 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5177 free(ctx->ifc_softc, M_IFLIB); 5178 unref_ctx_core_offset(ctx); 5179 free(ctx, M_IFLIB); 5180 return (0); 5181 } 5182 5183 static void 5184 iflib_free_intr_mem(if_ctx_t ctx) 5185 { 5186 5187 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5188 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5189 } 5190 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5191 pci_release_msi(ctx->ifc_dev); 5192 } 5193 if (ctx->ifc_msix_mem != NULL) { 5194 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5195 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5196 ctx->ifc_msix_mem = NULL; 5197 } 5198 } 5199 5200 int 5201 iflib_device_detach(device_t dev) 5202 { 5203 if_ctx_t ctx = device_get_softc(dev); 5204 5205 return (iflib_device_deregister(ctx)); 5206 } 5207 5208 int 5209 iflib_device_suspend(device_t dev) 5210 { 5211 if_ctx_t ctx = device_get_softc(dev); 5212 5213 CTX_LOCK(ctx); 5214 IFDI_SUSPEND(ctx); 5215 CTX_UNLOCK(ctx); 5216 5217 return bus_generic_suspend(dev); 5218 } 5219 int 5220 iflib_device_shutdown(device_t dev) 5221 { 5222 if_ctx_t ctx = device_get_softc(dev); 5223 5224 CTX_LOCK(ctx); 5225 IFDI_SHUTDOWN(ctx); 5226 CTX_UNLOCK(ctx); 5227 5228 return bus_generic_suspend(dev); 5229 } 5230 5231 5232 int 5233 iflib_device_resume(device_t dev) 5234 { 5235 if_ctx_t ctx = device_get_softc(dev); 5236 iflib_txq_t txq = ctx->ifc_txqs; 5237 5238 CTX_LOCK(ctx); 5239 IFDI_RESUME(ctx); 5240 iflib_if_init_locked(ctx); 5241 CTX_UNLOCK(ctx); 5242 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5243 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5244 5245 return (bus_generic_resume(dev)); 5246 } 5247 5248 int 5249 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5250 { 5251 int error; 5252 if_ctx_t ctx = device_get_softc(dev); 5253 5254 CTX_LOCK(ctx); 5255 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5256 CTX_UNLOCK(ctx); 5257 5258 return (error); 5259 } 5260 5261 void 5262 iflib_device_iov_uninit(device_t dev) 5263 { 5264 if_ctx_t ctx = device_get_softc(dev); 5265 5266 CTX_LOCK(ctx); 5267 IFDI_IOV_UNINIT(ctx); 5268 CTX_UNLOCK(ctx); 5269 } 5270 5271 int 5272 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5273 { 5274 int error; 5275 if_ctx_t ctx = device_get_softc(dev); 5276 5277 CTX_LOCK(ctx); 5278 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5279 CTX_UNLOCK(ctx); 5280 5281 return (error); 5282 } 5283 5284 /********************************************************************* 5285 * 5286 * MODULE FUNCTION DEFINITIONS 5287 * 5288 **********************************************************************/ 5289 5290 /* 5291 * - Start a fast taskqueue thread for each core 5292 * - Start a taskqueue for control operations 5293 */ 5294 static int 5295 iflib_module_init(void) 5296 { 5297 return (0); 5298 } 5299 5300 static int 5301 iflib_module_event_handler(module_t mod, int what, void *arg) 5302 { 5303 int err; 5304 5305 switch (what) { 5306 case MOD_LOAD: 5307 if ((err = iflib_module_init()) != 0) 5308 return (err); 5309 break; 5310 case MOD_UNLOAD: 5311 return (EBUSY); 5312 default: 5313 return (EOPNOTSUPP); 5314 } 5315 5316 return (0); 5317 } 5318 5319 /********************************************************************* 5320 * 5321 * PUBLIC FUNCTION DEFINITIONS 5322 * ordered as in iflib.h 5323 * 5324 **********************************************************************/ 5325 5326 5327 static void 5328 _iflib_assert(if_shared_ctx_t sctx) 5329 { 5330 int i; 5331 5332 MPASS(sctx->isc_tx_maxsize); 5333 MPASS(sctx->isc_tx_maxsegsize); 5334 5335 MPASS(sctx->isc_rx_maxsize); 5336 MPASS(sctx->isc_rx_nsegments); 5337 MPASS(sctx->isc_rx_maxsegsize); 5338 5339 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5340 for (i = 0; i < sctx->isc_nrxqs; i++) { 5341 MPASS(sctx->isc_nrxd_min[i]); 5342 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5343 MPASS(sctx->isc_nrxd_max[i]); 5344 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5345 MPASS(sctx->isc_nrxd_default[i]); 5346 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5347 } 5348 5349 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5350 for (i = 0; i < sctx->isc_ntxqs; i++) { 5351 MPASS(sctx->isc_ntxd_min[i]); 5352 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5353 MPASS(sctx->isc_ntxd_max[i]); 5354 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5355 MPASS(sctx->isc_ntxd_default[i]); 5356 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5357 } 5358 } 5359 5360 static void 5361 _iflib_pre_assert(if_softc_ctx_t scctx) 5362 { 5363 5364 MPASS(scctx->isc_txrx->ift_txd_encap); 5365 MPASS(scctx->isc_txrx->ift_txd_flush); 5366 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5367 MPASS(scctx->isc_txrx->ift_rxd_available); 5368 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5369 MPASS(scctx->isc_txrx->ift_rxd_refill); 5370 MPASS(scctx->isc_txrx->ift_rxd_flush); 5371 } 5372 5373 static int 5374 iflib_register(if_ctx_t ctx) 5375 { 5376 if_shared_ctx_t sctx = ctx->ifc_sctx; 5377 driver_t *driver = sctx->isc_driver; 5378 device_t dev = ctx->ifc_dev; 5379 if_t ifp; 5380 u_char type; 5381 int iflags; 5382 5383 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0) 5384 _iflib_assert(sctx); 5385 5386 CTX_LOCK_INIT(ctx); 5387 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5388 if (sctx->isc_flags & IFLIB_PSEUDO) { 5389 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) 5390 type = IFT_ETHER; 5391 else 5392 type = IFT_PPP; 5393 } else 5394 type = IFT_ETHER; 5395 ifp = ctx->ifc_ifp = if_alloc(type); 5396 if (ifp == NULL) { 5397 device_printf(dev, "can not allocate ifnet structure\n"); 5398 return (ENOMEM); 5399 } 5400 5401 /* 5402 * Initialize our context's device specific methods 5403 */ 5404 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5405 kobj_class_compile((kobj_class_t) driver); 5406 5407 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5408 if_setsoftc(ifp, ctx); 5409 if_setdev(ifp, dev); 5410 if_setinitfn(ifp, iflib_if_init); 5411 if_setioctlfn(ifp, iflib_if_ioctl); 5412 #ifdef ALTQ 5413 if_setstartfn(ifp, iflib_altq_if_start); 5414 if_settransmitfn(ifp, iflib_altq_if_transmit); 5415 if_setsendqready(ifp); 5416 #else 5417 if_settransmitfn(ifp, iflib_if_transmit); 5418 #endif 5419 if_setqflushfn(ifp, iflib_if_qflush); 5420 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH; 5421 5422 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5423 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) 5424 iflags |= IFF_POINTOPOINT; 5425 else 5426 iflags |= IFF_BROADCAST | IFF_SIMPLEX; 5427 if_setflags(ifp, iflags); 5428 ctx->ifc_vlan_attach_event = 5429 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5430 EVENTHANDLER_PRI_FIRST); 5431 ctx->ifc_vlan_detach_event = 5432 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5433 EVENTHANDLER_PRI_FIRST); 5434 5435 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5436 ctx->ifc_mediap = &ctx->ifc_media; 5437 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5438 iflib_media_change, iflib_media_status); 5439 } 5440 return (0); 5441 } 5442 5443 static void 5444 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5445 { 5446 /* Unregister VLAN events */ 5447 if (ctx->ifc_vlan_attach_event != NULL) { 5448 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5449 ctx->ifc_vlan_attach_event = NULL; 5450 } 5451 if (ctx->ifc_vlan_detach_event != NULL) { 5452 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5453 ctx->ifc_vlan_detach_event = NULL; 5454 } 5455 5456 } 5457 5458 static void 5459 iflib_deregister(if_ctx_t ctx) 5460 { 5461 if_t ifp = ctx->ifc_ifp; 5462 5463 /* Remove all media */ 5464 ifmedia_removeall(&ctx->ifc_media); 5465 5466 /* Ensure that VLAN event handlers are unregistered */ 5467 iflib_unregister_vlan_handlers(ctx); 5468 5469 /* Release kobject reference */ 5470 kobj_delete((kobj_t) ctx, NULL); 5471 5472 /* Free the ifnet structure */ 5473 if_free(ifp); 5474 5475 STATE_LOCK_DESTROY(ctx); 5476 5477 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5478 CTX_LOCK_DESTROY(ctx); 5479 } 5480 5481 static int 5482 iflib_queues_alloc(if_ctx_t ctx) 5483 { 5484 if_shared_ctx_t sctx = ctx->ifc_sctx; 5485 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5486 device_t dev = ctx->ifc_dev; 5487 int nrxqsets = scctx->isc_nrxqsets; 5488 int ntxqsets = scctx->isc_ntxqsets; 5489 iflib_txq_t txq; 5490 iflib_rxq_t rxq; 5491 iflib_fl_t fl = NULL; 5492 int i, j, cpu, err, txconf, rxconf; 5493 iflib_dma_info_t ifdip; 5494 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5495 uint32_t *txqsizes = scctx->isc_txqsizes; 5496 uint8_t nrxqs = sctx->isc_nrxqs; 5497 uint8_t ntxqs = sctx->isc_ntxqs; 5498 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5499 caddr_t *vaddrs; 5500 uint64_t *paddrs; 5501 5502 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5503 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5504 5505 /* Allocate the TX ring struct memory */ 5506 if (!(ctx->ifc_txqs = 5507 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5508 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5509 device_printf(dev, "Unable to allocate TX ring memory\n"); 5510 err = ENOMEM; 5511 goto fail; 5512 } 5513 5514 /* Now allocate the RX */ 5515 if (!(ctx->ifc_rxqs = 5516 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5517 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5518 device_printf(dev, "Unable to allocate RX ring memory\n"); 5519 err = ENOMEM; 5520 goto rx_fail; 5521 } 5522 5523 txq = ctx->ifc_txqs; 5524 rxq = ctx->ifc_rxqs; 5525 5526 /* 5527 * XXX handle allocation failure 5528 */ 5529 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5530 /* Set up some basics */ 5531 5532 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5533 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5534 device_printf(dev, 5535 "Unable to allocate TX DMA info memory\n"); 5536 err = ENOMEM; 5537 goto err_tx_desc; 5538 } 5539 txq->ift_ifdi = ifdip; 5540 for (j = 0; j < ntxqs; j++, ifdip++) { 5541 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5542 device_printf(dev, 5543 "Unable to allocate TX descriptors\n"); 5544 err = ENOMEM; 5545 goto err_tx_desc; 5546 } 5547 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5548 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5549 } 5550 txq->ift_ctx = ctx; 5551 txq->ift_id = i; 5552 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5553 txq->ift_br_offset = 1; 5554 } else { 5555 txq->ift_br_offset = 0; 5556 } 5557 /* XXX fix this */ 5558 txq->ift_timer.c_cpu = cpu; 5559 5560 if (iflib_txsd_alloc(txq)) { 5561 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5562 err = ENOMEM; 5563 goto err_tx_desc; 5564 } 5565 5566 /* Initialize the TX lock */ 5567 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5568 device_get_nameunit(dev), txq->ift_id); 5569 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5570 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5571 5572 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5573 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5574 if (err) { 5575 /* XXX free any allocated rings */ 5576 device_printf(dev, "Unable to allocate buf_ring\n"); 5577 goto err_tx_desc; 5578 } 5579 } 5580 5581 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5582 /* Set up some basics */ 5583 callout_init(&rxq->ifr_watchdog, 1); 5584 5585 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5586 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5587 device_printf(dev, 5588 "Unable to allocate RX DMA info memory\n"); 5589 err = ENOMEM; 5590 goto err_tx_desc; 5591 } 5592 5593 rxq->ifr_ifdi = ifdip; 5594 /* XXX this needs to be changed if #rx queues != #tx queues */ 5595 rxq->ifr_ntxqirq = 1; 5596 rxq->ifr_txqid[0] = i; 5597 for (j = 0; j < nrxqs; j++, ifdip++) { 5598 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5599 device_printf(dev, 5600 "Unable to allocate RX descriptors\n"); 5601 err = ENOMEM; 5602 goto err_tx_desc; 5603 } 5604 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5605 } 5606 rxq->ifr_ctx = ctx; 5607 rxq->ifr_id = i; 5608 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5609 rxq->ifr_fl_offset = 1; 5610 } else { 5611 rxq->ifr_fl_offset = 0; 5612 } 5613 rxq->ifr_nfl = nfree_lists; 5614 if (!(fl = 5615 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5616 device_printf(dev, "Unable to allocate free list memory\n"); 5617 err = ENOMEM; 5618 goto err_tx_desc; 5619 } 5620 rxq->ifr_fl = fl; 5621 for (j = 0; j < nfree_lists; j++) { 5622 fl[j].ifl_rxq = rxq; 5623 fl[j].ifl_id = j; 5624 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5625 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5626 } 5627 /* Allocate receive buffers for the ring */ 5628 if (iflib_rxsd_alloc(rxq)) { 5629 device_printf(dev, 5630 "Critical Failure setting up receive buffers\n"); 5631 err = ENOMEM; 5632 goto err_rx_desc; 5633 } 5634 5635 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5636 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5637 M_WAITOK); 5638 } 5639 5640 /* TXQs */ 5641 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5642 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5643 for (i = 0; i < ntxqsets; i++) { 5644 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5645 5646 for (j = 0; j < ntxqs; j++, di++) { 5647 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5648 paddrs[i*ntxqs + j] = di->idi_paddr; 5649 } 5650 } 5651 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5652 device_printf(ctx->ifc_dev, 5653 "Unable to allocate device TX queue\n"); 5654 iflib_tx_structures_free(ctx); 5655 free(vaddrs, M_IFLIB); 5656 free(paddrs, M_IFLIB); 5657 goto err_rx_desc; 5658 } 5659 free(vaddrs, M_IFLIB); 5660 free(paddrs, M_IFLIB); 5661 5662 /* RXQs */ 5663 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5664 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5665 for (i = 0; i < nrxqsets; i++) { 5666 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5667 5668 for (j = 0; j < nrxqs; j++, di++) { 5669 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5670 paddrs[i*nrxqs + j] = di->idi_paddr; 5671 } 5672 } 5673 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5674 device_printf(ctx->ifc_dev, 5675 "Unable to allocate device RX queue\n"); 5676 iflib_tx_structures_free(ctx); 5677 free(vaddrs, M_IFLIB); 5678 free(paddrs, M_IFLIB); 5679 goto err_rx_desc; 5680 } 5681 free(vaddrs, M_IFLIB); 5682 free(paddrs, M_IFLIB); 5683 5684 return (0); 5685 5686 /* XXX handle allocation failure changes */ 5687 err_rx_desc: 5688 err_tx_desc: 5689 rx_fail: 5690 if (ctx->ifc_rxqs != NULL) 5691 free(ctx->ifc_rxqs, M_IFLIB); 5692 ctx->ifc_rxqs = NULL; 5693 if (ctx->ifc_txqs != NULL) 5694 free(ctx->ifc_txqs, M_IFLIB); 5695 ctx->ifc_txqs = NULL; 5696 fail: 5697 return (err); 5698 } 5699 5700 static int 5701 iflib_tx_structures_setup(if_ctx_t ctx) 5702 { 5703 iflib_txq_t txq = ctx->ifc_txqs; 5704 int i; 5705 5706 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5707 iflib_txq_setup(txq); 5708 5709 return (0); 5710 } 5711 5712 static void 5713 iflib_tx_structures_free(if_ctx_t ctx) 5714 { 5715 iflib_txq_t txq = ctx->ifc_txqs; 5716 if_shared_ctx_t sctx = ctx->ifc_sctx; 5717 int i, j; 5718 5719 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5720 for (j = 0; j < sctx->isc_ntxqs; j++) 5721 iflib_dma_free(&txq->ift_ifdi[j]); 5722 iflib_txq_destroy(txq); 5723 } 5724 free(ctx->ifc_txqs, M_IFLIB); 5725 ctx->ifc_txqs = NULL; 5726 IFDI_QUEUES_FREE(ctx); 5727 } 5728 5729 /********************************************************************* 5730 * 5731 * Initialize all receive rings. 5732 * 5733 **********************************************************************/ 5734 static int 5735 iflib_rx_structures_setup(if_ctx_t ctx) 5736 { 5737 iflib_rxq_t rxq = ctx->ifc_rxqs; 5738 int q; 5739 #if defined(INET6) || defined(INET) 5740 int err, i; 5741 #endif 5742 5743 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5744 #if defined(INET6) || defined(INET) 5745 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) { 5746 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5747 TCP_LRO_ENTRIES, min(1024, 5748 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 5749 if (err != 0) { 5750 device_printf(ctx->ifc_dev, 5751 "LRO Initialization failed!\n"); 5752 goto fail; 5753 } 5754 } 5755 #endif 5756 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5757 } 5758 return (0); 5759 #if defined(INET6) || defined(INET) 5760 fail: 5761 /* 5762 * Free LRO resources allocated so far, we will only handle 5763 * the rings that completed, the failing case will have 5764 * cleaned up for itself. 'q' failed, so its the terminus. 5765 */ 5766 rxq = ctx->ifc_rxqs; 5767 for (i = 0; i < q; ++i, rxq++) { 5768 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5769 tcp_lro_free(&rxq->ifr_lc); 5770 } 5771 return (err); 5772 #endif 5773 } 5774 5775 /********************************************************************* 5776 * 5777 * Free all receive rings. 5778 * 5779 **********************************************************************/ 5780 static void 5781 iflib_rx_structures_free(if_ctx_t ctx) 5782 { 5783 iflib_rxq_t rxq = ctx->ifc_rxqs; 5784 if_shared_ctx_t sctx = ctx->ifc_sctx; 5785 int i, j; 5786 5787 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5788 for (j = 0; j < sctx->isc_nrxqs; j++) 5789 iflib_dma_free(&rxq->ifr_ifdi[j]); 5790 iflib_rx_sds_free(rxq); 5791 #if defined(INET6) || defined(INET) 5792 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5793 tcp_lro_free(&rxq->ifr_lc); 5794 #endif 5795 } 5796 free(ctx->ifc_rxqs, M_IFLIB); 5797 ctx->ifc_rxqs = NULL; 5798 } 5799 5800 static int 5801 iflib_qset_structures_setup(if_ctx_t ctx) 5802 { 5803 int err; 5804 5805 /* 5806 * It is expected that the caller takes care of freeing queues if this 5807 * fails. 5808 */ 5809 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5810 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5811 return (err); 5812 } 5813 5814 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5815 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5816 5817 return (err); 5818 } 5819 5820 int 5821 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5822 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5823 { 5824 5825 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5826 } 5827 5828 #ifdef SMP 5829 static int 5830 find_nth(if_ctx_t ctx, int qid) 5831 { 5832 cpuset_t cpus; 5833 int i, cpuid, eqid, count; 5834 5835 CPU_COPY(&ctx->ifc_cpus, &cpus); 5836 count = CPU_COUNT(&cpus); 5837 eqid = qid % count; 5838 /* clear up to the qid'th bit */ 5839 for (i = 0; i < eqid; i++) { 5840 cpuid = CPU_FFS(&cpus); 5841 MPASS(cpuid != 0); 5842 CPU_CLR(cpuid-1, &cpus); 5843 } 5844 cpuid = CPU_FFS(&cpus); 5845 MPASS(cpuid != 0); 5846 return (cpuid-1); 5847 } 5848 5849 #ifdef SCHED_ULE 5850 extern struct cpu_group *cpu_top; /* CPU topology */ 5851 5852 static int 5853 find_child_with_core(int cpu, struct cpu_group *grp) 5854 { 5855 int i; 5856 5857 if (grp->cg_children == 0) 5858 return -1; 5859 5860 MPASS(grp->cg_child); 5861 for (i = 0; i < grp->cg_children; i++) { 5862 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5863 return i; 5864 } 5865 5866 return -1; 5867 } 5868 5869 /* 5870 * Find the nth "close" core to the specified core 5871 * "close" is defined as the deepest level that shares 5872 * at least an L2 cache. With threads, this will be 5873 * threads on the same core. If the shared cache is L3 5874 * or higher, simply returns the same core. 5875 */ 5876 static int 5877 find_close_core(int cpu, int core_offset) 5878 { 5879 struct cpu_group *grp; 5880 int i; 5881 int fcpu; 5882 cpuset_t cs; 5883 5884 grp = cpu_top; 5885 if (grp == NULL) 5886 return cpu; 5887 i = 0; 5888 while ((i = find_child_with_core(cpu, grp)) != -1) { 5889 /* If the child only has one cpu, don't descend */ 5890 if (grp->cg_child[i].cg_count <= 1) 5891 break; 5892 grp = &grp->cg_child[i]; 5893 } 5894 5895 /* If they don't share at least an L2 cache, use the same CPU */ 5896 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5897 return cpu; 5898 5899 /* Now pick one */ 5900 CPU_COPY(&grp->cg_mask, &cs); 5901 5902 /* Add the selected CPU offset to core offset. */ 5903 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5904 if (fcpu - 1 == cpu) 5905 break; 5906 CPU_CLR(fcpu - 1, &cs); 5907 } 5908 MPASS(fcpu); 5909 5910 core_offset += i; 5911 5912 CPU_COPY(&grp->cg_mask, &cs); 5913 for (i = core_offset % grp->cg_count; i > 0; i--) { 5914 MPASS(CPU_FFS(&cs)); 5915 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5916 } 5917 MPASS(CPU_FFS(&cs)); 5918 return CPU_FFS(&cs) - 1; 5919 } 5920 #else 5921 static int 5922 find_close_core(int cpu, int core_offset __unused) 5923 { 5924 return cpu; 5925 } 5926 #endif 5927 5928 static int 5929 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5930 { 5931 switch (type) { 5932 case IFLIB_INTR_TX: 5933 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5934 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5935 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5936 case IFLIB_INTR_RX: 5937 case IFLIB_INTR_RXTX: 5938 /* RX queues get the specified core */ 5939 return qid / CPU_COUNT(&ctx->ifc_cpus); 5940 default: 5941 return -1; 5942 } 5943 } 5944 #else 5945 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5946 #define find_close_core(cpuid, tid) CPU_FIRST() 5947 #define find_nth(ctx, gid) CPU_FIRST() 5948 #endif 5949 5950 /* Just to avoid copy/paste */ 5951 static inline int 5952 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5953 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5954 const char *name) 5955 { 5956 device_t dev; 5957 int co, cpuid, err, tid; 5958 5959 dev = ctx->ifc_dev; 5960 co = ctx->ifc_sysctl_core_offset; 5961 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX) 5962 co += ctx->ifc_softc_ctx.isc_nrxqsets; 5963 cpuid = find_nth(ctx, qid + co); 5964 tid = get_core_offset(ctx, type, qid); 5965 if (tid < 0) { 5966 device_printf(dev, "get_core_offset failed\n"); 5967 return (EOPNOTSUPP); 5968 } 5969 cpuid = find_close_core(cpuid, tid); 5970 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 5971 name); 5972 if (err) { 5973 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 5974 return (err); 5975 } 5976 #ifdef notyet 5977 if (cpuid > ctx->ifc_cpuid_highest) 5978 ctx->ifc_cpuid_highest = cpuid; 5979 #endif 5980 return (0); 5981 } 5982 5983 int 5984 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5985 iflib_intr_type_t type, driver_filter_t *filter, 5986 void *filter_arg, int qid, const char *name) 5987 { 5988 device_t dev; 5989 struct grouptask *gtask; 5990 struct taskqgroup *tqg; 5991 iflib_filter_info_t info; 5992 gtask_fn_t *fn; 5993 int tqrid, err; 5994 driver_filter_t *intr_fast; 5995 void *q; 5996 5997 info = &ctx->ifc_filter_info; 5998 tqrid = rid; 5999 6000 switch (type) { 6001 /* XXX merge tx/rx for netmap? */ 6002 case IFLIB_INTR_TX: 6003 q = &ctx->ifc_txqs[qid]; 6004 info = &ctx->ifc_txqs[qid].ift_filter_info; 6005 gtask = &ctx->ifc_txqs[qid].ift_task; 6006 tqg = qgroup_if_io_tqg; 6007 fn = _task_fn_tx; 6008 intr_fast = iflib_fast_intr; 6009 GROUPTASK_INIT(gtask, 0, fn, q); 6010 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6011 break; 6012 case IFLIB_INTR_RX: 6013 q = &ctx->ifc_rxqs[qid]; 6014 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6015 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6016 tqg = qgroup_if_io_tqg; 6017 fn = _task_fn_rx; 6018 intr_fast = iflib_fast_intr; 6019 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6020 break; 6021 case IFLIB_INTR_RXTX: 6022 q = &ctx->ifc_rxqs[qid]; 6023 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6024 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6025 tqg = qgroup_if_io_tqg; 6026 fn = _task_fn_rx; 6027 intr_fast = iflib_fast_intr_rxtx; 6028 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6029 break; 6030 case IFLIB_INTR_ADMIN: 6031 q = ctx; 6032 tqrid = -1; 6033 info = &ctx->ifc_filter_info; 6034 gtask = &ctx->ifc_admin_task; 6035 tqg = qgroup_if_config_tqg; 6036 fn = _task_fn_admin; 6037 intr_fast = iflib_fast_intr_ctx; 6038 break; 6039 default: 6040 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6041 __func__); 6042 return (EINVAL); 6043 } 6044 6045 info->ifi_filter = filter; 6046 info->ifi_filter_arg = filter_arg; 6047 info->ifi_task = gtask; 6048 info->ifi_ctx = q; 6049 6050 dev = ctx->ifc_dev; 6051 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6052 if (err != 0) { 6053 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6054 return (err); 6055 } 6056 if (type == IFLIB_INTR_ADMIN) 6057 return (0); 6058 6059 if (tqrid != -1) { 6060 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6061 q, name); 6062 if (err) 6063 return (err); 6064 } else { 6065 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6066 } 6067 6068 return (0); 6069 } 6070 6071 void 6072 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6073 { 6074 struct grouptask *gtask; 6075 struct taskqgroup *tqg; 6076 gtask_fn_t *fn; 6077 void *q; 6078 int err; 6079 6080 switch (type) { 6081 case IFLIB_INTR_TX: 6082 q = &ctx->ifc_txqs[qid]; 6083 gtask = &ctx->ifc_txqs[qid].ift_task; 6084 tqg = qgroup_if_io_tqg; 6085 fn = _task_fn_tx; 6086 GROUPTASK_INIT(gtask, 0, fn, q); 6087 break; 6088 case IFLIB_INTR_RX: 6089 q = &ctx->ifc_rxqs[qid]; 6090 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6091 tqg = qgroup_if_io_tqg; 6092 fn = _task_fn_rx; 6093 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6094 break; 6095 case IFLIB_INTR_IOV: 6096 q = ctx; 6097 gtask = &ctx->ifc_vflr_task; 6098 tqg = qgroup_if_config_tqg; 6099 fn = _task_fn_iov; 6100 GROUPTASK_INIT(gtask, 0, fn, q); 6101 break; 6102 default: 6103 panic("unknown net intr type"); 6104 } 6105 if (irq != NULL) { 6106 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6107 q, name); 6108 if (err) 6109 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 6110 irq->ii_res, name); 6111 } else { 6112 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 6113 } 6114 } 6115 6116 void 6117 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6118 { 6119 6120 if (irq->ii_tag) 6121 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6122 6123 if (irq->ii_res) 6124 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6125 rman_get_rid(irq->ii_res), irq->ii_res); 6126 } 6127 6128 static int 6129 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6130 { 6131 iflib_txq_t txq = ctx->ifc_txqs; 6132 iflib_rxq_t rxq = ctx->ifc_rxqs; 6133 if_irq_t irq = &ctx->ifc_legacy_irq; 6134 iflib_filter_info_t info; 6135 device_t dev; 6136 struct grouptask *gtask; 6137 struct resource *res; 6138 struct taskqgroup *tqg; 6139 void *q; 6140 int err, tqrid; 6141 bool rx_only; 6142 6143 q = &ctx->ifc_rxqs[0]; 6144 info = &rxq[0].ifr_filter_info; 6145 gtask = &rxq[0].ifr_task; 6146 tqg = qgroup_if_io_tqg; 6147 tqrid = *rid; 6148 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6149 6150 ctx->ifc_flags |= IFC_LEGACY; 6151 info->ifi_filter = filter; 6152 info->ifi_filter_arg = filter_arg; 6153 info->ifi_task = gtask; 6154 info->ifi_ctx = rx_only ? ctx : q; 6155 6156 dev = ctx->ifc_dev; 6157 /* We allocate a single interrupt resource */ 6158 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6159 iflib_fast_intr_rxtx, NULL, info, name); 6160 if (err != 0) 6161 return (err); 6162 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6163 res = irq->ii_res; 6164 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6165 6166 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6167 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6168 "tx"); 6169 return (0); 6170 } 6171 6172 void 6173 iflib_led_create(if_ctx_t ctx) 6174 { 6175 6176 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6177 device_get_nameunit(ctx->ifc_dev)); 6178 } 6179 6180 void 6181 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6182 { 6183 6184 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6185 } 6186 6187 void 6188 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6189 { 6190 6191 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6192 } 6193 6194 void 6195 iflib_admin_intr_deferred(if_ctx_t ctx) 6196 { 6197 6198 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6199 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6200 } 6201 6202 void 6203 iflib_iov_intr_deferred(if_ctx_t ctx) 6204 { 6205 6206 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6207 } 6208 6209 void 6210 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6211 { 6212 6213 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6214 name); 6215 } 6216 6217 void 6218 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6219 const char *name) 6220 { 6221 6222 GROUPTASK_INIT(gtask, 0, fn, ctx); 6223 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6224 name); 6225 } 6226 6227 void 6228 iflib_config_gtask_deinit(struct grouptask *gtask) 6229 { 6230 6231 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6232 } 6233 6234 void 6235 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6236 { 6237 if_t ifp = ctx->ifc_ifp; 6238 iflib_txq_t txq = ctx->ifc_txqs; 6239 6240 if_setbaudrate(ifp, baudrate); 6241 if (baudrate >= IF_Gbps(10)) { 6242 STATE_LOCK(ctx); 6243 ctx->ifc_flags |= IFC_PREFETCH; 6244 STATE_UNLOCK(ctx); 6245 } 6246 /* If link down, disable watchdog */ 6247 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6248 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6249 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6250 } 6251 ctx->ifc_link_state = link_state; 6252 if_link_state_change(ifp, link_state); 6253 } 6254 6255 static int 6256 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6257 { 6258 int credits; 6259 #ifdef INVARIANTS 6260 int credits_pre = txq->ift_cidx_processed; 6261 #endif 6262 6263 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6264 BUS_DMASYNC_POSTREAD); 6265 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6266 return (0); 6267 6268 txq->ift_processed += credits; 6269 txq->ift_cidx_processed += credits; 6270 6271 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6272 if (txq->ift_cidx_processed >= txq->ift_size) 6273 txq->ift_cidx_processed -= txq->ift_size; 6274 return (credits); 6275 } 6276 6277 static int 6278 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6279 { 6280 iflib_fl_t fl; 6281 u_int i; 6282 6283 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6284 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6285 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6286 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6287 budget)); 6288 } 6289 6290 void 6291 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6292 const char *description, if_int_delay_info_t info, 6293 int offset, int value) 6294 { 6295 info->iidi_ctx = ctx; 6296 info->iidi_offset = offset; 6297 info->iidi_value = value; 6298 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6299 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6300 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6301 info, 0, iflib_sysctl_int_delay, "I", description); 6302 } 6303 6304 struct sx * 6305 iflib_ctx_lock_get(if_ctx_t ctx) 6306 { 6307 6308 return (&ctx->ifc_ctx_sx); 6309 } 6310 6311 static int 6312 iflib_msix_init(if_ctx_t ctx) 6313 { 6314 device_t dev = ctx->ifc_dev; 6315 if_shared_ctx_t sctx = ctx->ifc_sctx; 6316 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6317 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6318 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6319 6320 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6321 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6322 6323 if (bootverbose) 6324 device_printf(dev, "msix_init qsets capped at %d\n", 6325 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6326 6327 /* Override by tuneable */ 6328 if (scctx->isc_disable_msix) 6329 goto msi; 6330 6331 /* First try MSI-X */ 6332 if ((msgs = pci_msix_count(dev)) == 0) { 6333 if (bootverbose) 6334 device_printf(dev, "MSI-X not supported or disabled\n"); 6335 goto msi; 6336 } 6337 6338 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6339 /* 6340 * bar == -1 => "trust me I know what I'm doing" 6341 * Some drivers are for hardware that is so shoddily 6342 * documented that no one knows which bars are which 6343 * so the developer has to map all bars. This hack 6344 * allows shoddy garbage to use MSI-X in this framework. 6345 */ 6346 if (bar != -1) { 6347 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6348 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6349 if (ctx->ifc_msix_mem == NULL) { 6350 device_printf(dev, "Unable to map MSI-X table\n"); 6351 goto msi; 6352 } 6353 } 6354 6355 admincnt = sctx->isc_admin_intrcnt; 6356 #if IFLIB_DEBUG 6357 /* use only 1 qset in debug mode */ 6358 queuemsgs = min(msgs - admincnt, 1); 6359 #else 6360 queuemsgs = msgs - admincnt; 6361 #endif 6362 #ifdef RSS 6363 queues = imin(queuemsgs, rss_getnumbuckets()); 6364 #else 6365 queues = queuemsgs; 6366 #endif 6367 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6368 if (bootverbose) 6369 device_printf(dev, 6370 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6371 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6372 #ifdef RSS 6373 /* If we're doing RSS, clamp at the number of RSS buckets */ 6374 if (queues > rss_getnumbuckets()) 6375 queues = rss_getnumbuckets(); 6376 #endif 6377 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6378 rx_queues = iflib_num_rx_queues; 6379 else 6380 rx_queues = queues; 6381 6382 if (rx_queues > scctx->isc_nrxqsets) 6383 rx_queues = scctx->isc_nrxqsets; 6384 6385 /* 6386 * We want this to be all logical CPUs by default 6387 */ 6388 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6389 tx_queues = iflib_num_tx_queues; 6390 else 6391 tx_queues = mp_ncpus; 6392 6393 if (tx_queues > scctx->isc_ntxqsets) 6394 tx_queues = scctx->isc_ntxqsets; 6395 6396 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6397 #ifdef INVARIANTS 6398 if (tx_queues != rx_queues) 6399 device_printf(dev, 6400 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6401 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6402 #endif 6403 tx_queues = min(rx_queues, tx_queues); 6404 rx_queues = min(rx_queues, tx_queues); 6405 } 6406 6407 vectors = rx_queues + admincnt; 6408 if (msgs < vectors) { 6409 device_printf(dev, 6410 "insufficient number of MSI-X vectors " 6411 "(supported %d, need %d)\n", msgs, vectors); 6412 goto msi; 6413 } 6414 6415 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6416 tx_queues); 6417 msgs = vectors; 6418 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6419 if (vectors != msgs) { 6420 device_printf(dev, 6421 "Unable to allocate sufficient MSI-X vectors " 6422 "(got %d, need %d)\n", vectors, msgs); 6423 pci_release_msi(dev); 6424 if (bar != -1) { 6425 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6426 ctx->ifc_msix_mem); 6427 ctx->ifc_msix_mem = NULL; 6428 } 6429 goto msi; 6430 } 6431 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6432 vectors); 6433 scctx->isc_vectors = vectors; 6434 scctx->isc_nrxqsets = rx_queues; 6435 scctx->isc_ntxqsets = tx_queues; 6436 scctx->isc_intr = IFLIB_INTR_MSIX; 6437 6438 return (vectors); 6439 } else { 6440 device_printf(dev, 6441 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6442 err); 6443 if (bar != -1) { 6444 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6445 ctx->ifc_msix_mem); 6446 ctx->ifc_msix_mem = NULL; 6447 } 6448 } 6449 6450 msi: 6451 vectors = pci_msi_count(dev); 6452 scctx->isc_nrxqsets = 1; 6453 scctx->isc_ntxqsets = 1; 6454 scctx->isc_vectors = vectors; 6455 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6456 device_printf(dev,"Using an MSI interrupt\n"); 6457 scctx->isc_intr = IFLIB_INTR_MSI; 6458 } else { 6459 scctx->isc_vectors = 1; 6460 device_printf(dev,"Using a Legacy interrupt\n"); 6461 scctx->isc_intr = IFLIB_INTR_LEGACY; 6462 } 6463 6464 return (vectors); 6465 } 6466 6467 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6468 6469 static int 6470 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6471 { 6472 int rc; 6473 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6474 struct sbuf *sb; 6475 const char *ring_state = "UNKNOWN"; 6476 6477 /* XXX needed ? */ 6478 rc = sysctl_wire_old_buffer(req, 0); 6479 MPASS(rc == 0); 6480 if (rc != 0) 6481 return (rc); 6482 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6483 MPASS(sb != NULL); 6484 if (sb == NULL) 6485 return (ENOMEM); 6486 if (state[3] <= 3) 6487 ring_state = ring_states[state[3]]; 6488 6489 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6490 state[0], state[1], state[2], ring_state); 6491 rc = sbuf_finish(sb); 6492 sbuf_delete(sb); 6493 return(rc); 6494 } 6495 6496 enum iflib_ndesc_handler { 6497 IFLIB_NTXD_HANDLER, 6498 IFLIB_NRXD_HANDLER, 6499 }; 6500 6501 static int 6502 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6503 { 6504 if_ctx_t ctx = (void *)arg1; 6505 enum iflib_ndesc_handler type = arg2; 6506 char buf[256] = {0}; 6507 qidx_t *ndesc; 6508 char *p, *next; 6509 int nqs, rc, i; 6510 6511 nqs = 8; 6512 switch(type) { 6513 case IFLIB_NTXD_HANDLER: 6514 ndesc = ctx->ifc_sysctl_ntxds; 6515 if (ctx->ifc_sctx) 6516 nqs = ctx->ifc_sctx->isc_ntxqs; 6517 break; 6518 case IFLIB_NRXD_HANDLER: 6519 ndesc = ctx->ifc_sysctl_nrxds; 6520 if (ctx->ifc_sctx) 6521 nqs = ctx->ifc_sctx->isc_nrxqs; 6522 break; 6523 default: 6524 printf("%s: unhandled type\n", __func__); 6525 return (EINVAL); 6526 } 6527 if (nqs == 0) 6528 nqs = 8; 6529 6530 for (i=0; i<8; i++) { 6531 if (i >= nqs) 6532 break; 6533 if (i) 6534 strcat(buf, ","); 6535 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6536 } 6537 6538 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6539 if (rc || req->newptr == NULL) 6540 return rc; 6541 6542 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6543 i++, p = strsep(&next, " ,")) { 6544 ndesc[i] = strtoul(p, NULL, 10); 6545 } 6546 6547 return(rc); 6548 } 6549 6550 #define NAME_BUFLEN 32 6551 static void 6552 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6553 { 6554 device_t dev = iflib_get_dev(ctx); 6555 struct sysctl_oid_list *child, *oid_list; 6556 struct sysctl_ctx_list *ctx_list; 6557 struct sysctl_oid *node; 6558 6559 ctx_list = device_get_sysctl_ctx(dev); 6560 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6561 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6562 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 6563 oid_list = SYSCTL_CHILDREN(node); 6564 6565 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6566 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6567 "driver version"); 6568 6569 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6570 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6571 "# of txqs to use, 0 => use default #"); 6572 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6573 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6574 "# of rxqs to use, 0 => use default #"); 6575 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6576 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6577 "permit #txq != #rxq"); 6578 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6579 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6580 "disable MSI-X (default 0)"); 6581 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6582 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6583 "set the RX budget"); 6584 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6585 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6586 "cause TX to abdicate instead of running to completion"); 6587 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6588 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6589 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6590 "offset to start using cores at"); 6591 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6592 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6593 "use separate cores for TX and RX"); 6594 6595 /* XXX change for per-queue sizes */ 6596 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6597 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6598 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6599 "list of # of TX descriptors to use, 0 = use default #"); 6600 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6601 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6602 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6603 "list of # of RX descriptors to use, 0 = use default #"); 6604 } 6605 6606 static void 6607 iflib_add_device_sysctl_post(if_ctx_t ctx) 6608 { 6609 if_shared_ctx_t sctx = ctx->ifc_sctx; 6610 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6611 device_t dev = iflib_get_dev(ctx); 6612 struct sysctl_oid_list *child; 6613 struct sysctl_ctx_list *ctx_list; 6614 iflib_fl_t fl; 6615 iflib_txq_t txq; 6616 iflib_rxq_t rxq; 6617 int i, j; 6618 char namebuf[NAME_BUFLEN]; 6619 char *qfmt; 6620 struct sysctl_oid *queue_node, *fl_node, *node; 6621 struct sysctl_oid_list *queue_list, *fl_list; 6622 ctx_list = device_get_sysctl_ctx(dev); 6623 6624 node = ctx->ifc_sysctl_node; 6625 child = SYSCTL_CHILDREN(node); 6626 6627 if (scctx->isc_ntxqsets > 100) 6628 qfmt = "txq%03d"; 6629 else if (scctx->isc_ntxqsets > 10) 6630 qfmt = "txq%02d"; 6631 else 6632 qfmt = "txq%d"; 6633 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6634 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6635 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6636 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6637 queue_list = SYSCTL_CHILDREN(queue_node); 6638 #if MEMORY_LOGGING 6639 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6640 CTLFLAG_RD, 6641 &txq->ift_dequeued, "total mbufs freed"); 6642 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6643 CTLFLAG_RD, 6644 &txq->ift_enqueued, "total mbufs enqueued"); 6645 #endif 6646 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6647 CTLFLAG_RD, 6648 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6649 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6650 CTLFLAG_RD, 6651 &txq->ift_pullups, "# of times m_pullup was called"); 6652 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6653 CTLFLAG_RD, 6654 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6655 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6656 CTLFLAG_RD, 6657 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6658 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6659 CTLFLAG_RD, 6660 &txq->ift_map_failed, "# of times DMA map failed"); 6661 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6662 CTLFLAG_RD, 6663 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6664 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6665 CTLFLAG_RD, 6666 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6667 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6668 CTLFLAG_RD, 6669 &txq->ift_pidx, 1, "Producer Index"); 6670 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6671 CTLFLAG_RD, 6672 &txq->ift_cidx, 1, "Consumer Index"); 6673 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6674 CTLFLAG_RD, 6675 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6676 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6677 CTLFLAG_RD, 6678 &txq->ift_in_use, 1, "descriptors in use"); 6679 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6680 CTLFLAG_RD, 6681 &txq->ift_processed, "descriptors procesed for clean"); 6682 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6683 CTLFLAG_RD, 6684 &txq->ift_cleaned, "total cleaned"); 6685 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6686 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6687 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6688 mp_ring_state_handler, "A", "soft ring state"); 6689 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6690 CTLFLAG_RD, &txq->ift_br->enqueues, 6691 "# of enqueues to the mp_ring for this queue"); 6692 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6693 CTLFLAG_RD, &txq->ift_br->drops, 6694 "# of drops in the mp_ring for this queue"); 6695 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6696 CTLFLAG_RD, &txq->ift_br->starts, 6697 "# of normal consumer starts in the mp_ring for this queue"); 6698 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6699 CTLFLAG_RD, &txq->ift_br->stalls, 6700 "# of consumer stalls in the mp_ring for this queue"); 6701 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6702 CTLFLAG_RD, &txq->ift_br->restarts, 6703 "# of consumer restarts in the mp_ring for this queue"); 6704 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6705 CTLFLAG_RD, &txq->ift_br->abdications, 6706 "# of consumer abdications in the mp_ring for this queue"); 6707 } 6708 6709 if (scctx->isc_nrxqsets > 100) 6710 qfmt = "rxq%03d"; 6711 else if (scctx->isc_nrxqsets > 10) 6712 qfmt = "rxq%02d"; 6713 else 6714 qfmt = "rxq%d"; 6715 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6716 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6717 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6718 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6719 queue_list = SYSCTL_CHILDREN(queue_node); 6720 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6721 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6722 CTLFLAG_RD, 6723 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6724 } 6725 6726 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6727 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6728 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6729 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 6730 fl_list = SYSCTL_CHILDREN(fl_node); 6731 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6732 CTLFLAG_RD, 6733 &fl->ifl_pidx, 1, "Producer Index"); 6734 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6735 CTLFLAG_RD, 6736 &fl->ifl_cidx, 1, "Consumer Index"); 6737 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6738 CTLFLAG_RD, 6739 &fl->ifl_credits, 1, "credits available"); 6740 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 6741 CTLFLAG_RD, 6742 &fl->ifl_buf_size, 1, "buffer size"); 6743 #if MEMORY_LOGGING 6744 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6745 CTLFLAG_RD, 6746 &fl->ifl_m_enqueued, "mbufs allocated"); 6747 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6748 CTLFLAG_RD, 6749 &fl->ifl_m_dequeued, "mbufs freed"); 6750 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6751 CTLFLAG_RD, 6752 &fl->ifl_cl_enqueued, "clusters allocated"); 6753 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6754 CTLFLAG_RD, 6755 &fl->ifl_cl_dequeued, "clusters freed"); 6756 #endif 6757 6758 } 6759 } 6760 6761 } 6762 6763 void 6764 iflib_request_reset(if_ctx_t ctx) 6765 { 6766 6767 STATE_LOCK(ctx); 6768 ctx->ifc_flags |= IFC_DO_RESET; 6769 STATE_UNLOCK(ctx); 6770 } 6771 6772 #ifndef __NO_STRICT_ALIGNMENT 6773 static struct mbuf * 6774 iflib_fixup_rx(struct mbuf *m) 6775 { 6776 struct mbuf *n; 6777 6778 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6779 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6780 m->m_data += ETHER_HDR_LEN; 6781 n = m; 6782 } else { 6783 MGETHDR(n, M_NOWAIT, MT_DATA); 6784 if (n == NULL) { 6785 m_freem(m); 6786 return (NULL); 6787 } 6788 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6789 m->m_data += ETHER_HDR_LEN; 6790 m->m_len -= ETHER_HDR_LEN; 6791 n->m_len = ETHER_HDR_LEN; 6792 M_MOVE_PKTHDR(n, m); 6793 n->m_next = m; 6794 } 6795 return (n); 6796 } 6797 #endif 6798 6799 #ifdef DEBUGNET 6800 static void 6801 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6802 { 6803 if_ctx_t ctx; 6804 6805 ctx = if_getsoftc(ifp); 6806 CTX_LOCK(ctx); 6807 *nrxr = NRXQSETS(ctx); 6808 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6809 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6810 CTX_UNLOCK(ctx); 6811 } 6812 6813 static void 6814 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 6815 { 6816 if_ctx_t ctx; 6817 if_softc_ctx_t scctx; 6818 iflib_fl_t fl; 6819 iflib_rxq_t rxq; 6820 int i, j; 6821 6822 ctx = if_getsoftc(ifp); 6823 scctx = &ctx->ifc_softc_ctx; 6824 6825 switch (event) { 6826 case DEBUGNET_START: 6827 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6828 rxq = &ctx->ifc_rxqs[i]; 6829 for (j = 0; j < rxq->ifr_nfl; j++) { 6830 fl = rxq->ifr_fl; 6831 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6832 } 6833 } 6834 iflib_no_tx_batch = 1; 6835 break; 6836 default: 6837 break; 6838 } 6839 } 6840 6841 static int 6842 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 6843 { 6844 if_ctx_t ctx; 6845 iflib_txq_t txq; 6846 int error; 6847 6848 ctx = if_getsoftc(ifp); 6849 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6850 IFF_DRV_RUNNING) 6851 return (EBUSY); 6852 6853 txq = &ctx->ifc_txqs[0]; 6854 error = iflib_encap(txq, &m); 6855 if (error == 0) 6856 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6857 return (error); 6858 } 6859 6860 static int 6861 iflib_debugnet_poll(if_t ifp, int count) 6862 { 6863 struct epoch_tracker et; 6864 if_ctx_t ctx; 6865 if_softc_ctx_t scctx; 6866 iflib_txq_t txq; 6867 int i; 6868 6869 ctx = if_getsoftc(ifp); 6870 scctx = &ctx->ifc_softc_ctx; 6871 6872 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6873 IFF_DRV_RUNNING) 6874 return (EBUSY); 6875 6876 txq = &ctx->ifc_txqs[0]; 6877 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6878 6879 NET_EPOCH_ENTER(et); 6880 for (i = 0; i < scctx->isc_nrxqsets; i++) 6881 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6882 NET_EPOCH_EXIT(et); 6883 return (0); 6884 } 6885 #endif /* DEBUGNET */ 6886