1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 /* 120 * File organization: 121 * - private structures 122 * - iflib private utility functions 123 * - ifnet functions 124 * - vlan registry and other exported functions 125 * - iflib public core functions 126 * 127 * 128 */ 129 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 130 131 #define IFLIB_RXEOF_MORE (1U << 0) 132 #define IFLIB_RXEOF_EMPTY (2U << 0) 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 static void iflib_tqg_detach(if_ctx_t ctx); 146 147 typedef struct iflib_filter_info { 148 driver_filter_t *ifi_filter; 149 void *ifi_filter_arg; 150 struct grouptask *ifi_task; 151 void *ifi_ctx; 152 } *iflib_filter_info_t; 153 154 struct iflib_ctx { 155 KOBJ_FIELDS; 156 /* 157 * Pointer to hardware driver's softc 158 */ 159 void *ifc_softc; 160 device_t ifc_dev; 161 if_t ifc_ifp; 162 163 cpuset_t ifc_cpus; 164 if_shared_ctx_t ifc_sctx; 165 struct if_softc_ctx ifc_softc_ctx; 166 167 struct sx ifc_ctx_sx; 168 struct mtx ifc_state_mtx; 169 170 iflib_txq_t ifc_txqs; 171 iflib_rxq_t ifc_rxqs; 172 uint32_t ifc_if_flags; 173 uint32_t ifc_flags; 174 uint32_t ifc_max_fl_buf_size; 175 uint32_t ifc_rx_mbuf_sz; 176 177 int ifc_link_state; 178 int ifc_watchdog_events; 179 struct cdev *ifc_led_dev; 180 struct resource *ifc_msix_mem; 181 182 struct if_irq ifc_legacy_irq; 183 struct grouptask ifc_admin_task; 184 struct grouptask ifc_vflr_task; 185 struct iflib_filter_info ifc_filter_info; 186 struct ifmedia ifc_media; 187 struct ifmedia *ifc_mediap; 188 189 struct sysctl_oid *ifc_sysctl_node; 190 uint16_t ifc_sysctl_ntxqs; 191 uint16_t ifc_sysctl_nrxqs; 192 uint16_t ifc_sysctl_qs_eq_override; 193 uint16_t ifc_sysctl_rx_budget; 194 uint16_t ifc_sysctl_tx_abdicate; 195 uint16_t ifc_sysctl_core_offset; 196 #define CORE_OFFSET_UNSPECIFIED 0xffff 197 uint8_t ifc_sysctl_separate_txrx; 198 uint8_t ifc_sysctl_use_logical_cores; 199 bool ifc_cpus_are_physical_cores; 200 201 qidx_t ifc_sysctl_ntxds[8]; 202 qidx_t ifc_sysctl_nrxds[8]; 203 struct if_txrx ifc_txrx; 204 #define isc_txd_encap ifc_txrx.ift_txd_encap 205 #define isc_txd_flush ifc_txrx.ift_txd_flush 206 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 207 #define isc_rxd_available ifc_txrx.ift_rxd_available 208 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 209 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 210 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 211 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 212 #define isc_txq_select ifc_txrx.ift_txq_select 213 eventhandler_tag ifc_vlan_attach_event; 214 eventhandler_tag ifc_vlan_detach_event; 215 struct ether_addr ifc_mac; 216 }; 217 218 void * 219 iflib_get_softc(if_ctx_t ctx) 220 { 221 222 return (ctx->ifc_softc); 223 } 224 225 device_t 226 iflib_get_dev(if_ctx_t ctx) 227 { 228 229 return (ctx->ifc_dev); 230 } 231 232 if_t 233 iflib_get_ifp(if_ctx_t ctx) 234 { 235 236 return (ctx->ifc_ifp); 237 } 238 239 struct ifmedia * 240 iflib_get_media(if_ctx_t ctx) 241 { 242 243 return (ctx->ifc_mediap); 244 } 245 246 uint32_t 247 iflib_get_flags(if_ctx_t ctx) 248 { 249 return (ctx->ifc_flags); 250 } 251 252 void 253 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 254 { 255 256 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 257 } 258 259 if_softc_ctx_t 260 iflib_get_softc_ctx(if_ctx_t ctx) 261 { 262 263 return (&ctx->ifc_softc_ctx); 264 } 265 266 if_shared_ctx_t 267 iflib_get_sctx(if_ctx_t ctx) 268 { 269 270 return (ctx->ifc_sctx); 271 } 272 273 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 274 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 275 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 276 277 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 278 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 279 280 typedef struct iflib_sw_rx_desc_array { 281 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 282 struct mbuf **ifsd_m; /* pkthdr mbufs */ 283 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 284 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 285 } iflib_rxsd_array_t; 286 287 typedef struct iflib_sw_tx_desc_array { 288 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 289 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 290 struct mbuf **ifsd_m; /* pkthdr mbufs */ 291 } if_txsd_vec_t; 292 293 /* magic number that should be high enough for any hardware */ 294 #define IFLIB_MAX_TX_SEGS 128 295 #define IFLIB_RX_COPY_THRESH 128 296 #define IFLIB_MAX_RX_REFRESH 32 297 /* The minimum descriptors per second before we start coalescing */ 298 #define IFLIB_MIN_DESC_SEC 16384 299 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 300 #define IFLIB_QUEUE_IDLE 0 301 #define IFLIB_QUEUE_HUNG 1 302 #define IFLIB_QUEUE_WORKING 2 303 /* maximum number of txqs that can share an rx interrupt */ 304 #define IFLIB_MAX_TX_SHARED_INTR 4 305 306 /* this should really scale with ring size - this is a fairly arbitrary value */ 307 #define TX_BATCH_SIZE 32 308 309 #define IFLIB_RESTART_BUDGET 8 310 311 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 312 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 313 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 314 315 struct iflib_txq { 316 qidx_t ift_in_use; 317 qidx_t ift_cidx; 318 qidx_t ift_cidx_processed; 319 qidx_t ift_pidx; 320 uint8_t ift_gen; 321 uint8_t ift_br_offset; 322 uint16_t ift_npending; 323 uint16_t ift_db_pending; 324 uint16_t ift_rs_pending; 325 /* implicit pad */ 326 uint8_t ift_txd_size[8]; 327 uint64_t ift_processed; 328 uint64_t ift_cleaned; 329 uint64_t ift_cleaned_prev; 330 #if MEMORY_LOGGING 331 uint64_t ift_enqueued; 332 uint64_t ift_dequeued; 333 #endif 334 uint64_t ift_no_tx_dma_setup; 335 uint64_t ift_no_desc_avail; 336 uint64_t ift_mbuf_defrag_failed; 337 uint64_t ift_mbuf_defrag; 338 uint64_t ift_map_failed; 339 uint64_t ift_txd_encap_efbig; 340 uint64_t ift_pullups; 341 uint64_t ift_last_timer_tick; 342 343 struct mtx ift_mtx; 344 struct mtx ift_db_mtx; 345 346 /* constant values */ 347 if_ctx_t ift_ctx; 348 struct ifmp_ring *ift_br; 349 struct grouptask ift_task; 350 qidx_t ift_size; 351 uint16_t ift_id; 352 struct callout ift_timer; 353 #ifdef DEV_NETMAP 354 struct callout ift_netmap_timer; 355 #endif /* DEV_NETMAP */ 356 357 if_txsd_vec_t ift_sds; 358 uint8_t ift_qstatus; 359 uint8_t ift_closed; 360 uint8_t ift_update_freq; 361 struct iflib_filter_info ift_filter_info; 362 bus_dma_tag_t ift_buf_tag; 363 bus_dma_tag_t ift_tso_buf_tag; 364 iflib_dma_info_t ift_ifdi; 365 #define MTX_NAME_LEN 32 366 char ift_mtx_name[MTX_NAME_LEN]; 367 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 368 #ifdef IFLIB_DIAGNOSTICS 369 uint64_t ift_cpu_exec_count[256]; 370 #endif 371 } __aligned(CACHE_LINE_SIZE); 372 373 struct iflib_fl { 374 qidx_t ifl_cidx; 375 qidx_t ifl_pidx; 376 qidx_t ifl_credits; 377 uint8_t ifl_gen; 378 uint8_t ifl_rxd_size; 379 #if MEMORY_LOGGING 380 uint64_t ifl_m_enqueued; 381 uint64_t ifl_m_dequeued; 382 uint64_t ifl_cl_enqueued; 383 uint64_t ifl_cl_dequeued; 384 #endif 385 /* implicit pad */ 386 bitstr_t *ifl_rx_bitmap; 387 qidx_t ifl_fragidx; 388 /* constant */ 389 qidx_t ifl_size; 390 uint16_t ifl_buf_size; 391 uint16_t ifl_cltype; 392 uma_zone_t ifl_zone; 393 iflib_rxsd_array_t ifl_sds; 394 iflib_rxq_t ifl_rxq; 395 uint8_t ifl_id; 396 bus_dma_tag_t ifl_buf_tag; 397 iflib_dma_info_t ifl_ifdi; 398 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 399 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 400 } __aligned(CACHE_LINE_SIZE); 401 402 static inline qidx_t 403 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 404 { 405 qidx_t used; 406 407 if (pidx > cidx) 408 used = pidx - cidx; 409 else if (pidx < cidx) 410 used = size - cidx + pidx; 411 else if (gen == 0 && pidx == cidx) 412 used = 0; 413 else if (gen == 1 && pidx == cidx) 414 used = size; 415 else 416 panic("bad state"); 417 418 return (used); 419 } 420 421 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 422 423 #define IDXDIFF(head, tail, wrap) \ 424 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 425 426 struct iflib_rxq { 427 if_ctx_t ifr_ctx; 428 iflib_fl_t ifr_fl; 429 uint64_t ifr_rx_irq; 430 struct pfil_head *pfil; 431 /* 432 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 433 * the completion queue consumer index. Otherwise it's unused. 434 */ 435 qidx_t ifr_cq_cidx; 436 uint16_t ifr_id; 437 uint8_t ifr_nfl; 438 uint8_t ifr_ntxqirq; 439 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 440 uint8_t ifr_fl_offset; 441 struct lro_ctrl ifr_lc; 442 struct grouptask ifr_task; 443 struct callout ifr_watchdog; 444 struct iflib_filter_info ifr_filter_info; 445 iflib_dma_info_t ifr_ifdi; 446 447 /* dynamically allocate if any drivers need a value substantially larger than this */ 448 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 449 #ifdef IFLIB_DIAGNOSTICS 450 uint64_t ifr_cpu_exec_count[256]; 451 #endif 452 } __aligned(CACHE_LINE_SIZE); 453 454 typedef struct if_rxsd { 455 caddr_t *ifsd_cl; 456 iflib_fl_t ifsd_fl; 457 } *if_rxsd_t; 458 459 /* multiple of word size */ 460 #ifdef __LP64__ 461 #define PKT_INFO_SIZE 6 462 #define RXD_INFO_SIZE 5 463 #define PKT_TYPE uint64_t 464 #else 465 #define PKT_INFO_SIZE 11 466 #define RXD_INFO_SIZE 8 467 #define PKT_TYPE uint32_t 468 #endif 469 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 470 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 471 472 typedef struct if_pkt_info_pad { 473 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 474 } *if_pkt_info_pad_t; 475 typedef struct if_rxd_info_pad { 476 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 477 } *if_rxd_info_pad_t; 478 479 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 480 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 481 482 static inline void 483 pkt_info_zero(if_pkt_info_t pi) 484 { 485 if_pkt_info_pad_t pi_pad; 486 487 pi_pad = (if_pkt_info_pad_t)pi; 488 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 489 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 490 #ifndef __LP64__ 491 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 492 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 493 #endif 494 } 495 496 static device_method_t iflib_pseudo_methods[] = { 497 DEVMETHOD(device_attach, noop_attach), 498 DEVMETHOD(device_detach, iflib_pseudo_detach), 499 DEVMETHOD_END 500 }; 501 502 driver_t iflib_pseudodriver = { 503 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 504 }; 505 506 static inline void 507 rxd_info_zero(if_rxd_info_t ri) 508 { 509 if_rxd_info_pad_t ri_pad; 510 int i; 511 512 ri_pad = (if_rxd_info_pad_t)ri; 513 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 514 ri_pad->rxd_val[i] = 0; 515 ri_pad->rxd_val[i+1] = 0; 516 ri_pad->rxd_val[i+2] = 0; 517 ri_pad->rxd_val[i+3] = 0; 518 } 519 #ifdef __LP64__ 520 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 521 #endif 522 } 523 524 /* 525 * Only allow a single packet to take up most 1/nth of the tx ring 526 */ 527 #define MAX_SINGLE_PACKET_FRACTION 12 528 #define IF_BAD_DMA (bus_addr_t)-1 529 530 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 531 532 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 533 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 534 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 535 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 536 537 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 538 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 539 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 540 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 541 542 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 543 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 544 545 void 546 iflib_set_detach(if_ctx_t ctx) 547 { 548 STATE_LOCK(ctx); 549 ctx->ifc_flags |= IFC_IN_DETACH; 550 STATE_UNLOCK(ctx); 551 } 552 553 /* Our boot-time initialization hook */ 554 static int iflib_module_event_handler(module_t, int, void *); 555 556 static moduledata_t iflib_moduledata = { 557 "iflib", 558 iflib_module_event_handler, 559 NULL 560 }; 561 562 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 563 MODULE_VERSION(iflib, 1); 564 565 MODULE_DEPEND(iflib, pci, 1, 1, 1); 566 MODULE_DEPEND(iflib, ether, 1, 1, 1); 567 568 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 569 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 570 571 #ifndef IFLIB_DEBUG_COUNTERS 572 #ifdef INVARIANTS 573 #define IFLIB_DEBUG_COUNTERS 1 574 #else 575 #define IFLIB_DEBUG_COUNTERS 0 576 #endif /* !INVARIANTS */ 577 #endif 578 579 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 580 "iflib driver parameters"); 581 582 /* 583 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 584 */ 585 static int iflib_min_tx_latency = 0; 586 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 587 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 588 static int iflib_no_tx_batch = 0; 589 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 590 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 591 static int iflib_timer_default = 1000; 592 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW, 593 &iflib_timer_default, 0, "number of ticks between iflib_timer calls"); 594 595 596 #if IFLIB_DEBUG_COUNTERS 597 598 static int iflib_tx_seen; 599 static int iflib_tx_sent; 600 static int iflib_tx_encap; 601 static int iflib_rx_allocs; 602 static int iflib_fl_refills; 603 static int iflib_fl_refills_large; 604 static int iflib_tx_frees; 605 606 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 607 &iflib_tx_seen, 0, "# TX mbufs seen"); 608 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 609 &iflib_tx_sent, 0, "# TX mbufs sent"); 610 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 611 &iflib_tx_encap, 0, "# TX mbufs encapped"); 612 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 613 &iflib_tx_frees, 0, "# TX frees"); 614 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 615 &iflib_rx_allocs, 0, "# RX allocations"); 616 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 617 &iflib_fl_refills, 0, "# refills"); 618 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 619 &iflib_fl_refills_large, 0, "# large refills"); 620 621 static int iflib_txq_drain_flushing; 622 static int iflib_txq_drain_oactive; 623 static int iflib_txq_drain_notready; 624 625 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 626 &iflib_txq_drain_flushing, 0, "# drain flushes"); 627 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 628 &iflib_txq_drain_oactive, 0, "# drain oactives"); 629 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 630 &iflib_txq_drain_notready, 0, "# drain notready"); 631 632 static int iflib_encap_load_mbuf_fail; 633 static int iflib_encap_pad_mbuf_fail; 634 static int iflib_encap_txq_avail_fail; 635 static int iflib_encap_txd_encap_fail; 636 637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 638 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 639 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 640 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 641 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 642 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 643 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 644 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 645 646 static int iflib_task_fn_rxs; 647 static int iflib_rx_intr_enables; 648 static int iflib_fast_intrs; 649 static int iflib_rx_unavail; 650 static int iflib_rx_ctx_inactive; 651 static int iflib_rx_if_input; 652 static int iflib_rxd_flush; 653 654 static int iflib_verbose_debug; 655 656 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 657 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 659 &iflib_rx_intr_enables, 0, "# RX intr enables"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 661 &iflib_fast_intrs, 0, "# fast_intr calls"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 663 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 665 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 666 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 667 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 668 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 669 &iflib_rxd_flush, 0, "# times rxd_flush called"); 670 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 671 &iflib_verbose_debug, 0, "enable verbose debugging"); 672 673 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 674 static void 675 iflib_debug_reset(void) 676 { 677 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 678 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 679 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 680 iflib_txq_drain_notready = 681 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 682 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 683 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 684 iflib_rx_unavail = 685 iflib_rx_ctx_inactive = iflib_rx_if_input = 686 iflib_rxd_flush = 0; 687 } 688 689 #else 690 #define DBG_COUNTER_INC(name) 691 static void iflib_debug_reset(void) {} 692 #endif 693 694 #define IFLIB_DEBUG 0 695 696 static void iflib_tx_structures_free(if_ctx_t ctx); 697 static void iflib_rx_structures_free(if_ctx_t ctx); 698 static int iflib_queues_alloc(if_ctx_t ctx); 699 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 700 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 701 static int iflib_qset_structures_setup(if_ctx_t ctx); 702 static int iflib_msix_init(if_ctx_t ctx); 703 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 704 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 705 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 706 #ifdef ALTQ 707 static void iflib_altq_if_start(if_t ifp); 708 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 709 #endif 710 static int iflib_register(if_ctx_t); 711 static void iflib_deregister(if_ctx_t); 712 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 713 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 714 static void iflib_init_locked(if_ctx_t ctx); 715 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 716 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 717 static void iflib_ifmp_purge(iflib_txq_t txq); 718 static void _iflib_pre_assert(if_softc_ctx_t scctx); 719 static void iflib_if_init_locked(if_ctx_t ctx); 720 static void iflib_free_intr_mem(if_ctx_t ctx); 721 #ifndef __NO_STRICT_ALIGNMENT 722 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 723 #endif 724 725 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 726 SLIST_HEAD_INITIALIZER(cpu_offsets); 727 struct cpu_offset { 728 SLIST_ENTRY(cpu_offset) entries; 729 cpuset_t set; 730 unsigned int refcount; 731 uint16_t next_cpuid; 732 }; 733 static struct mtx cpu_offset_mtx; 734 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 735 MTX_DEF); 736 737 DEBUGNET_DEFINE(iflib); 738 739 static int 740 iflib_num_rx_descs(if_ctx_t ctx) 741 { 742 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 743 if_shared_ctx_t sctx = ctx->ifc_sctx; 744 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 745 746 return scctx->isc_nrxd[first_rxq]; 747 } 748 749 static int 750 iflib_num_tx_descs(if_ctx_t ctx) 751 { 752 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 753 if_shared_ctx_t sctx = ctx->ifc_sctx; 754 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 755 756 return scctx->isc_ntxd[first_txq]; 757 } 758 759 #ifdef DEV_NETMAP 760 #include <sys/selinfo.h> 761 #include <net/netmap.h> 762 #include <dev/netmap/netmap_kern.h> 763 764 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 765 766 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 767 static void iflib_netmap_timer(void *arg); 768 769 /* 770 * device-specific sysctl variables: 771 * 772 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 773 * During regular operations the CRC is stripped, but on some 774 * hardware reception of frames not multiple of 64 is slower, 775 * so using crcstrip=0 helps in benchmarks. 776 * 777 * iflib_rx_miss, iflib_rx_miss_bufs: 778 * count packets that might be missed due to lost interrupts. 779 */ 780 SYSCTL_DECL(_dev_netmap); 781 /* 782 * The xl driver by default strips CRCs and we do not override it. 783 */ 784 785 int iflib_crcstrip = 1; 786 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 787 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 788 789 int iflib_rx_miss, iflib_rx_miss_bufs; 790 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 791 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 792 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 793 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 794 795 /* 796 * Register/unregister. We are already under netmap lock. 797 * Only called on the first register or the last unregister. 798 */ 799 static int 800 iflib_netmap_register(struct netmap_adapter *na, int onoff) 801 { 802 if_t ifp = na->ifp; 803 if_ctx_t ctx = ifp->if_softc; 804 int status; 805 806 CTX_LOCK(ctx); 807 if (!CTX_IS_VF(ctx)) 808 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 809 810 iflib_stop(ctx); 811 812 /* 813 * Enable (or disable) netmap flags, and intercept (or restore) 814 * ifp->if_transmit. This is done once the device has been stopped 815 * to prevent race conditions. Also, this must be done after 816 * calling netmap_disable_all_rings() and before calling 817 * netmap_enable_all_rings(), so that these two functions see the 818 * updated state of the NAF_NETMAP_ON bit. 819 */ 820 if (onoff) { 821 nm_set_native_flags(na); 822 } else { 823 nm_clear_native_flags(na); 824 } 825 826 iflib_init_locked(ctx); 827 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 828 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 829 if (status) 830 nm_clear_native_flags(na); 831 CTX_UNLOCK(ctx); 832 return (status); 833 } 834 835 static int 836 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info) 837 { 838 if_t ifp = na->ifp; 839 if_ctx_t ctx = ifp->if_softc; 840 iflib_rxq_t rxq = &ctx->ifc_rxqs[0]; 841 iflib_fl_t fl = &rxq->ifr_fl[0]; 842 843 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 844 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 845 info->num_tx_descs = iflib_num_tx_descs(ctx); 846 info->num_rx_descs = iflib_num_rx_descs(ctx); 847 info->rx_buf_maxsize = fl->ifl_buf_size; 848 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u", 849 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs, 850 info->num_rx_descs, info->rx_buf_maxsize); 851 852 return 0; 853 } 854 855 static int 856 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 857 { 858 struct netmap_adapter *na = kring->na; 859 u_int const lim = kring->nkr_num_slots - 1; 860 struct netmap_ring *ring = kring->ring; 861 bus_dmamap_t *map; 862 struct if_rxd_update iru; 863 if_ctx_t ctx = rxq->ifr_ctx; 864 iflib_fl_t fl = &rxq->ifr_fl[0]; 865 u_int nic_i_first, nic_i; 866 u_int nm_i; 867 int i, n; 868 #if IFLIB_DEBUG_COUNTERS 869 int rf_count = 0; 870 #endif 871 872 /* 873 * This function is used both at initialization and in rxsync. 874 * At initialization we need to prepare (with isc_rxd_refill()) 875 * all the netmap buffers currently owned by the kernel, in 876 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync 877 * (except for kring->nkr_hwofs). These may be less than 878 * kring->nkr_num_slots if netmap_reset() was called while 879 * an application using the kring that still owned some 880 * buffers. 881 * At rxsync time, both indexes point to the next buffer to be 882 * refilled. 883 * In any case we publish (with isc_rxd_flush()) up to 884 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 885 * pointer to overrun the head/cons pointer, although this is 886 * not necessary for some NICs (e.g. vmx). 887 */ 888 if (__predict_false(init)) { 889 n = kring->nkr_num_slots - nm_kr_rxspace(kring); 890 } else { 891 n = kring->rhead - kring->nr_hwcur; 892 if (n == 0) 893 return (0); /* Nothing to do. */ 894 if (n < 0) 895 n += kring->nkr_num_slots; 896 } 897 898 iru_init(&iru, rxq, 0 /* flid */); 899 map = fl->ifl_sds.ifsd_map; 900 nic_i = fl->ifl_pidx; 901 nm_i = netmap_idx_n2k(kring, nic_i); 902 if (__predict_false(init)) { 903 /* 904 * On init/reset, nic_i must be 0, and we must 905 * start to refill from hwtail (see netmap_reset()). 906 */ 907 MPASS(nic_i == 0); 908 MPASS(nm_i == kring->nr_hwtail); 909 } else 910 MPASS(nm_i == kring->nr_hwcur); 911 DBG_COUNTER_INC(fl_refills); 912 while (n > 0) { 913 #if IFLIB_DEBUG_COUNTERS 914 if (++rf_count == 9) 915 DBG_COUNTER_INC(fl_refills_large); 916 #endif 917 nic_i_first = nic_i; 918 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 919 struct netmap_slot *slot = &ring->slot[nm_i]; 920 uint64_t paddr; 921 void *addr = PNMB(na, slot, &paddr); 922 923 MPASS(i < IFLIB_MAX_RX_REFRESH); 924 925 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 926 return netmap_ring_reinit(kring); 927 928 fl->ifl_bus_addrs[i] = paddr + 929 nm_get_offset(kring, slot); 930 fl->ifl_rxd_idxs[i] = nic_i; 931 932 if (__predict_false(init)) { 933 netmap_load_map(na, fl->ifl_buf_tag, 934 map[nic_i], addr); 935 } else if (slot->flags & NS_BUF_CHANGED) { 936 /* buffer has changed, reload map */ 937 netmap_reload_map(na, fl->ifl_buf_tag, 938 map[nic_i], addr); 939 } 940 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 941 BUS_DMASYNC_PREREAD); 942 slot->flags &= ~NS_BUF_CHANGED; 943 944 nm_i = nm_next(nm_i, lim); 945 nic_i = nm_next(nic_i, lim); 946 } 947 948 iru.iru_pidx = nic_i_first; 949 iru.iru_count = i; 950 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 951 } 952 fl->ifl_pidx = nic_i; 953 /* 954 * At the end of the loop we must have refilled everything 955 * we could possibly refill. 956 */ 957 MPASS(nm_i == kring->rhead); 958 kring->nr_hwcur = nm_i; 959 960 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 961 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 962 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 963 nm_prev(nic_i, lim)); 964 DBG_COUNTER_INC(rxd_flush); 965 966 return (0); 967 } 968 969 #define NETMAP_TX_TIMER_US 90 970 971 /* 972 * Reconcile kernel and user view of the transmit ring. 973 * 974 * All information is in the kring. 975 * Userspace wants to send packets up to the one before kring->rhead, 976 * kernel knows kring->nr_hwcur is the first unsent packet. 977 * 978 * Here we push packets out (as many as possible), and possibly 979 * reclaim buffers from previously completed transmission. 980 * 981 * The caller (netmap) guarantees that there is only one instance 982 * running at any time. Any interference with other driver 983 * methods should be handled by the individual drivers. 984 */ 985 static int 986 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 987 { 988 struct netmap_adapter *na = kring->na; 989 if_t ifp = na->ifp; 990 struct netmap_ring *ring = kring->ring; 991 u_int nm_i; /* index into the netmap kring */ 992 u_int nic_i; /* index into the NIC ring */ 993 u_int const lim = kring->nkr_num_slots - 1; 994 u_int const head = kring->rhead; 995 struct if_pkt_info pi; 996 int tx_pkts = 0, tx_bytes = 0; 997 998 /* 999 * interrupts on every tx packet are expensive so request 1000 * them every half ring, or where NS_REPORT is set 1001 */ 1002 u_int report_frequency = kring->nkr_num_slots >> 1; 1003 /* device-specific */ 1004 if_ctx_t ctx = ifp->if_softc; 1005 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 1006 1007 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1008 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1009 1010 /* 1011 * First part: process new packets to send. 1012 * nm_i is the current index in the netmap kring, 1013 * nic_i is the corresponding index in the NIC ring. 1014 * 1015 * If we have packets to send (nm_i != head) 1016 * iterate over the netmap ring, fetch length and update 1017 * the corresponding slot in the NIC ring. Some drivers also 1018 * need to update the buffer's physical address in the NIC slot 1019 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 1020 * 1021 * The netmap_reload_map() calls is especially expensive, 1022 * even when (as in this case) the tag is 0, so do only 1023 * when the buffer has actually changed. 1024 * 1025 * If possible do not set the report/intr bit on all slots, 1026 * but only a few times per ring or when NS_REPORT is set. 1027 * 1028 * Finally, on 10G and faster drivers, it might be useful 1029 * to prefetch the next slot and txr entry. 1030 */ 1031 1032 nm_i = kring->nr_hwcur; 1033 if (nm_i != head) { /* we have new packets to send */ 1034 uint32_t pkt_len = 0, seg_idx = 0; 1035 int nic_i_start = -1, flags = 0; 1036 pkt_info_zero(&pi); 1037 pi.ipi_segs = txq->ift_segs; 1038 pi.ipi_qsidx = kring->ring_id; 1039 nic_i = netmap_idx_k2n(kring, nm_i); 1040 1041 __builtin_prefetch(&ring->slot[nm_i]); 1042 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 1043 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 1044 1045 while (nm_i != head) { 1046 struct netmap_slot *slot = &ring->slot[nm_i]; 1047 uint64_t offset = nm_get_offset(kring, slot); 1048 u_int len = slot->len; 1049 uint64_t paddr; 1050 void *addr = PNMB(na, slot, &paddr); 1051 1052 flags |= (slot->flags & NS_REPORT || 1053 nic_i == 0 || nic_i == report_frequency) ? 1054 IPI_TX_INTR : 0; 1055 1056 /* 1057 * If this is the first packet fragment, save the 1058 * index of the first NIC slot for later. 1059 */ 1060 if (nic_i_start < 0) 1061 nic_i_start = nic_i; 1062 1063 pi.ipi_segs[seg_idx].ds_addr = paddr + offset; 1064 pi.ipi_segs[seg_idx].ds_len = len; 1065 if (len) { 1066 pkt_len += len; 1067 seg_idx++; 1068 } 1069 1070 if (!(slot->flags & NS_MOREFRAG)) { 1071 pi.ipi_len = pkt_len; 1072 pi.ipi_nsegs = seg_idx; 1073 pi.ipi_pidx = nic_i_start; 1074 pi.ipi_ndescs = 0; 1075 pi.ipi_flags = flags; 1076 1077 /* Prepare the NIC TX ring. */ 1078 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1079 DBG_COUNTER_INC(tx_encap); 1080 1081 /* Update transmit counters */ 1082 tx_bytes += pi.ipi_len; 1083 tx_pkts++; 1084 1085 /* Reinit per-packet info for the next one. */ 1086 flags = seg_idx = pkt_len = 0; 1087 nic_i_start = -1; 1088 } 1089 1090 /* prefetch for next round */ 1091 __builtin_prefetch(&ring->slot[nm_i + 1]); 1092 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1093 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1094 1095 NM_CHECK_ADDR_LEN_OFF(na, len, offset); 1096 1097 if (slot->flags & NS_BUF_CHANGED) { 1098 /* buffer has changed, reload map */ 1099 netmap_reload_map(na, txq->ift_buf_tag, 1100 txq->ift_sds.ifsd_map[nic_i], addr); 1101 } 1102 /* make sure changes to the buffer are synced */ 1103 bus_dmamap_sync(txq->ift_buf_tag, 1104 txq->ift_sds.ifsd_map[nic_i], 1105 BUS_DMASYNC_PREWRITE); 1106 1107 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG); 1108 nm_i = nm_next(nm_i, lim); 1109 nic_i = nm_next(nic_i, lim); 1110 } 1111 kring->nr_hwcur = nm_i; 1112 1113 /* synchronize the NIC ring */ 1114 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1115 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1116 1117 /* (re)start the tx unit up to slot nic_i (excluded) */ 1118 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1119 } 1120 1121 /* 1122 * Second part: reclaim buffers for completed transmissions. 1123 * 1124 * If there are unclaimed buffers, attempt to reclaim them. 1125 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1126 * trigger a per-tx-queue timer to try again later. 1127 */ 1128 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1129 if (iflib_tx_credits_update(ctx, txq)) { 1130 /* some tx completed, increment avail */ 1131 nic_i = txq->ift_cidx_processed; 1132 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1133 } 1134 } 1135 1136 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1137 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1138 callout_reset_sbt_on(&txq->ift_netmap_timer, 1139 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1140 iflib_netmap_timer, txq, 1141 txq->ift_netmap_timer.c_cpu, 0); 1142 } 1143 1144 if_inc_counter(ifp, IFCOUNTER_OBYTES, tx_bytes); 1145 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tx_pkts); 1146 1147 return (0); 1148 } 1149 1150 /* 1151 * Reconcile kernel and user view of the receive ring. 1152 * Same as for the txsync, this routine must be efficient. 1153 * The caller guarantees a single invocations, but races against 1154 * the rest of the driver should be handled here. 1155 * 1156 * On call, kring->rhead is the first packet that userspace wants 1157 * to keep, and kring->rcur is the wakeup point. 1158 * The kernel has previously reported packets up to kring->rtail. 1159 * 1160 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1161 * of whether or not we received an interrupt. 1162 */ 1163 static int 1164 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1165 { 1166 struct netmap_adapter *na = kring->na; 1167 struct netmap_ring *ring = kring->ring; 1168 if_t ifp = na->ifp; 1169 uint32_t nm_i; /* index into the netmap ring */ 1170 uint32_t nic_i; /* index into the NIC ring */ 1171 u_int n; 1172 u_int const lim = kring->nkr_num_slots - 1; 1173 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1174 int i = 0, rx_bytes = 0, rx_pkts = 0; 1175 1176 if_ctx_t ctx = ifp->if_softc; 1177 if_shared_ctx_t sctx = ctx->ifc_sctx; 1178 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1179 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1180 iflib_fl_t fl = &rxq->ifr_fl[0]; 1181 struct if_rxd_info ri; 1182 qidx_t *cidxp; 1183 1184 /* 1185 * netmap only uses free list 0, to avoid out of order consumption 1186 * of receive buffers 1187 */ 1188 1189 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1190 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1191 1192 /* 1193 * First part: import newly received packets. 1194 * 1195 * nm_i is the index of the next free slot in the netmap ring, 1196 * nic_i is the index of the next received packet in the NIC ring 1197 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1198 * differ in case if_init() has been called while 1199 * in netmap mode. For the receive ring we have 1200 * 1201 * nic_i = fl->ifl_cidx; 1202 * nm_i = kring->nr_hwtail (previous) 1203 * and 1204 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1205 * 1206 * fl->ifl_cidx is set to 0 on a ring reinit 1207 */ 1208 if (netmap_no_pendintr || force_update) { 1209 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1210 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1211 int crclen = iflib_crcstrip ? 0 : 4; 1212 int error, avail; 1213 1214 /* 1215 * For the free list consumer index, we use the same 1216 * logic as in iflib_rxeof(). 1217 */ 1218 if (have_rxcq) 1219 cidxp = &rxq->ifr_cq_cidx; 1220 else 1221 cidxp = &fl->ifl_cidx; 1222 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1223 rxq->ifr_id, *cidxp, USHRT_MAX); 1224 1225 nic_i = fl->ifl_cidx; 1226 nm_i = netmap_idx_n2k(kring, nic_i); 1227 MPASS(nm_i == kring->nr_hwtail); 1228 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1229 rxd_info_zero(&ri); 1230 ri.iri_frags = rxq->ifr_frags; 1231 ri.iri_qsidx = kring->ring_id; 1232 ri.iri_ifp = ctx->ifc_ifp; 1233 ri.iri_cidx = *cidxp; 1234 1235 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1236 for (i = 0; i < ri.iri_nfrags; i++) { 1237 if (error) { 1238 ring->slot[nm_i].len = 0; 1239 ring->slot[nm_i].flags = 0; 1240 } else { 1241 ring->slot[nm_i].len = ri.iri_frags[i].irf_len; 1242 if (i == (ri.iri_nfrags - 1)) { 1243 ring->slot[nm_i].len -= crclen; 1244 ring->slot[nm_i].flags = 0; 1245 1246 /* Update receive counters */ 1247 rx_bytes += ri.iri_len; 1248 rx_pkts++; 1249 } else 1250 ring->slot[nm_i].flags = NS_MOREFRAG; 1251 } 1252 1253 bus_dmamap_sync(fl->ifl_buf_tag, 1254 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1255 nm_i = nm_next(nm_i, lim); 1256 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1257 } 1258 1259 if (have_rxcq) { 1260 *cidxp = ri.iri_cidx; 1261 while (*cidxp >= scctx->isc_nrxd[0]) 1262 *cidxp -= scctx->isc_nrxd[0]; 1263 } 1264 1265 } 1266 if (n) { /* update the state variables */ 1267 if (netmap_no_pendintr && !force_update) { 1268 /* diagnostics */ 1269 iflib_rx_miss ++; 1270 iflib_rx_miss_bufs += n; 1271 } 1272 kring->nr_hwtail = nm_i; 1273 } 1274 kring->nr_kflags &= ~NKR_PENDINTR; 1275 } 1276 /* 1277 * Second part: skip past packets that userspace has released. 1278 * (kring->nr_hwcur to head excluded), 1279 * and make the buffers available for reception. 1280 * As usual nm_i is the index in the netmap ring, 1281 * nic_i is the index in the NIC ring, and 1282 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1283 */ 1284 netmap_fl_refill(rxq, kring, false); 1285 1286 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 1287 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 1288 1289 return (0); 1290 } 1291 1292 static void 1293 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1294 { 1295 if_ctx_t ctx = na->ifp->if_softc; 1296 1297 CTX_LOCK(ctx); 1298 if (onoff) { 1299 IFDI_INTR_ENABLE(ctx); 1300 } else { 1301 IFDI_INTR_DISABLE(ctx); 1302 } 1303 CTX_UNLOCK(ctx); 1304 } 1305 1306 static int 1307 iflib_netmap_attach(if_ctx_t ctx) 1308 { 1309 struct netmap_adapter na; 1310 1311 bzero(&na, sizeof(na)); 1312 1313 na.ifp = ctx->ifc_ifp; 1314 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS; 1315 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1316 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1317 1318 na.num_tx_desc = iflib_num_tx_descs(ctx); 1319 na.num_rx_desc = iflib_num_rx_descs(ctx); 1320 na.nm_txsync = iflib_netmap_txsync; 1321 na.nm_rxsync = iflib_netmap_rxsync; 1322 na.nm_register = iflib_netmap_register; 1323 na.nm_intr = iflib_netmap_intr; 1324 na.nm_config = iflib_netmap_config; 1325 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1326 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1327 return (netmap_attach(&na)); 1328 } 1329 1330 static int 1331 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1332 { 1333 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1334 struct netmap_slot *slot; 1335 1336 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1337 if (slot == NULL) 1338 return (0); 1339 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1340 /* 1341 * In netmap mode, set the map for the packet buffer. 1342 * NOTE: Some drivers (not this one) also need to set 1343 * the physical buffer address in the NIC ring. 1344 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1345 * netmap slot index, si 1346 */ 1347 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1348 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1349 NMB(na, slot + si)); 1350 } 1351 return (1); 1352 } 1353 1354 static int 1355 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1356 { 1357 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1358 struct netmap_kring *kring; 1359 struct netmap_slot *slot; 1360 1361 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1362 if (slot == NULL) 1363 return (0); 1364 kring = na->rx_rings[rxq->ifr_id]; 1365 netmap_fl_refill(rxq, kring, true); 1366 return (1); 1367 } 1368 1369 static void 1370 iflib_netmap_timer(void *arg) 1371 { 1372 iflib_txq_t txq = arg; 1373 if_ctx_t ctx = txq->ift_ctx; 1374 1375 /* 1376 * Wake up the netmap application, to give it a chance to 1377 * call txsync and reclaim more completed TX buffers. 1378 */ 1379 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1380 } 1381 1382 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1383 1384 #else 1385 #define iflib_netmap_txq_init(ctx, txq) (0) 1386 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1387 #define iflib_netmap_detach(ifp) 1388 #define netmap_enable_all_rings(ifp) 1389 #define netmap_disable_all_rings(ifp) 1390 1391 #define iflib_netmap_attach(ctx) (0) 1392 #define netmap_rx_irq(ifp, qid, budget) (0) 1393 #endif 1394 1395 #if defined(__i386__) || defined(__amd64__) 1396 static __inline void 1397 prefetch(void *x) 1398 { 1399 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1400 } 1401 1402 static __inline void 1403 prefetch2cachelines(void *x) 1404 { 1405 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1406 #if (CACHE_LINE_SIZE < 128) 1407 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1408 #endif 1409 } 1410 #else 1411 static __inline void 1412 prefetch(void *x) 1413 { 1414 } 1415 1416 static __inline void 1417 prefetch2cachelines(void *x) 1418 { 1419 } 1420 #endif 1421 1422 static void 1423 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1424 { 1425 iflib_fl_t fl; 1426 1427 fl = &rxq->ifr_fl[flid]; 1428 iru->iru_paddrs = fl->ifl_bus_addrs; 1429 iru->iru_idxs = fl->ifl_rxd_idxs; 1430 iru->iru_qsidx = rxq->ifr_id; 1431 iru->iru_buf_size = fl->ifl_buf_size; 1432 iru->iru_flidx = fl->ifl_id; 1433 } 1434 1435 static void 1436 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1437 { 1438 if (err) 1439 return; 1440 *(bus_addr_t *) arg = segs[0].ds_addr; 1441 } 1442 1443 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \ 1444 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \ 1445 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL) 1446 1447 int 1448 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1449 { 1450 int err; 1451 device_t dev = ctx->ifc_dev; 1452 bus_addr_t lowaddr; 1453 1454 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width); 1455 1456 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1457 align, 0, /* alignment, bounds */ 1458 lowaddr, /* lowaddr */ 1459 BUS_SPACE_MAXADDR, /* highaddr */ 1460 NULL, NULL, /* filter, filterarg */ 1461 size, /* maxsize */ 1462 1, /* nsegments */ 1463 size, /* maxsegsize */ 1464 BUS_DMA_ALLOCNOW, /* flags */ 1465 NULL, /* lockfunc */ 1466 NULL, /* lockarg */ 1467 &dma->idi_tag); 1468 if (err) { 1469 device_printf(dev, 1470 "%s: bus_dma_tag_create failed: %d\n", 1471 __func__, err); 1472 goto fail_0; 1473 } 1474 1475 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1476 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1477 if (err) { 1478 device_printf(dev, 1479 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1480 __func__, (uintmax_t)size, err); 1481 goto fail_1; 1482 } 1483 1484 dma->idi_paddr = IF_BAD_DMA; 1485 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1486 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1487 if (err || dma->idi_paddr == IF_BAD_DMA) { 1488 device_printf(dev, 1489 "%s: bus_dmamap_load failed: %d\n", 1490 __func__, err); 1491 goto fail_2; 1492 } 1493 1494 dma->idi_size = size; 1495 return (0); 1496 1497 fail_2: 1498 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1499 fail_1: 1500 bus_dma_tag_destroy(dma->idi_tag); 1501 fail_0: 1502 dma->idi_tag = NULL; 1503 1504 return (err); 1505 } 1506 1507 int 1508 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1509 { 1510 if_shared_ctx_t sctx = ctx->ifc_sctx; 1511 1512 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1513 1514 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1515 } 1516 1517 int 1518 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1519 { 1520 int i, err; 1521 iflib_dma_info_t *dmaiter; 1522 1523 dmaiter = dmalist; 1524 for (i = 0; i < count; i++, dmaiter++) { 1525 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1526 break; 1527 } 1528 if (err) 1529 iflib_dma_free_multi(dmalist, i); 1530 return (err); 1531 } 1532 1533 void 1534 iflib_dma_free(iflib_dma_info_t dma) 1535 { 1536 if (dma->idi_tag == NULL) 1537 return; 1538 if (dma->idi_paddr != IF_BAD_DMA) { 1539 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1540 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1541 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1542 dma->idi_paddr = IF_BAD_DMA; 1543 } 1544 if (dma->idi_vaddr != NULL) { 1545 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1546 dma->idi_vaddr = NULL; 1547 } 1548 bus_dma_tag_destroy(dma->idi_tag); 1549 dma->idi_tag = NULL; 1550 } 1551 1552 void 1553 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1554 { 1555 int i; 1556 iflib_dma_info_t *dmaiter = dmalist; 1557 1558 for (i = 0; i < count; i++, dmaiter++) 1559 iflib_dma_free(*dmaiter); 1560 } 1561 1562 static int 1563 iflib_fast_intr(void *arg) 1564 { 1565 iflib_filter_info_t info = arg; 1566 struct grouptask *gtask = info->ifi_task; 1567 int result; 1568 1569 DBG_COUNTER_INC(fast_intrs); 1570 if (info->ifi_filter != NULL) { 1571 result = info->ifi_filter(info->ifi_filter_arg); 1572 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1573 return (result); 1574 } 1575 1576 GROUPTASK_ENQUEUE(gtask); 1577 return (FILTER_HANDLED); 1578 } 1579 1580 static int 1581 iflib_fast_intr_rxtx(void *arg) 1582 { 1583 iflib_filter_info_t info = arg; 1584 struct grouptask *gtask = info->ifi_task; 1585 if_ctx_t ctx; 1586 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1587 iflib_txq_t txq; 1588 void *sc; 1589 int i, cidx, result; 1590 qidx_t txqid; 1591 bool intr_enable, intr_legacy; 1592 1593 DBG_COUNTER_INC(fast_intrs); 1594 if (info->ifi_filter != NULL) { 1595 result = info->ifi_filter(info->ifi_filter_arg); 1596 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1597 return (result); 1598 } 1599 1600 ctx = rxq->ifr_ctx; 1601 sc = ctx->ifc_softc; 1602 intr_enable = false; 1603 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1604 MPASS(rxq->ifr_ntxqirq); 1605 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1606 txqid = rxq->ifr_txqid[i]; 1607 txq = &ctx->ifc_txqs[txqid]; 1608 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1609 BUS_DMASYNC_POSTREAD); 1610 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1611 if (intr_legacy) 1612 intr_enable = true; 1613 else 1614 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1615 continue; 1616 } 1617 GROUPTASK_ENQUEUE(&txq->ift_task); 1618 } 1619 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1620 cidx = rxq->ifr_cq_cidx; 1621 else 1622 cidx = rxq->ifr_fl[0].ifl_cidx; 1623 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1624 GROUPTASK_ENQUEUE(gtask); 1625 else { 1626 if (intr_legacy) 1627 intr_enable = true; 1628 else 1629 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1630 DBG_COUNTER_INC(rx_intr_enables); 1631 } 1632 if (intr_enable) 1633 IFDI_INTR_ENABLE(ctx); 1634 return (FILTER_HANDLED); 1635 } 1636 1637 static int 1638 iflib_fast_intr_ctx(void *arg) 1639 { 1640 iflib_filter_info_t info = arg; 1641 struct grouptask *gtask = info->ifi_task; 1642 int result; 1643 1644 DBG_COUNTER_INC(fast_intrs); 1645 if (info->ifi_filter != NULL) { 1646 result = info->ifi_filter(info->ifi_filter_arg); 1647 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1648 return (result); 1649 } 1650 1651 GROUPTASK_ENQUEUE(gtask); 1652 return (FILTER_HANDLED); 1653 } 1654 1655 static int 1656 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1657 driver_filter_t filter, driver_intr_t handler, void *arg, 1658 const char *name) 1659 { 1660 struct resource *res; 1661 void *tag = NULL; 1662 device_t dev = ctx->ifc_dev; 1663 int flags, i, rc; 1664 1665 flags = RF_ACTIVE; 1666 if (ctx->ifc_flags & IFC_LEGACY) 1667 flags |= RF_SHAREABLE; 1668 MPASS(rid < 512); 1669 i = rid; 1670 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1671 if (res == NULL) { 1672 device_printf(dev, 1673 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1674 return (ENOMEM); 1675 } 1676 irq->ii_res = res; 1677 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1678 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1679 filter, handler, arg, &tag); 1680 if (rc != 0) { 1681 device_printf(dev, 1682 "failed to setup interrupt for rid %d, name %s: %d\n", 1683 rid, name ? name : "unknown", rc); 1684 return (rc); 1685 } else if (name) 1686 bus_describe_intr(dev, res, tag, "%s", name); 1687 1688 irq->ii_tag = tag; 1689 return (0); 1690 } 1691 1692 /********************************************************************* 1693 * 1694 * Allocate DMA resources for TX buffers as well as memory for the TX 1695 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1696 * iflib_sw_tx_desc_array structure, storing all the information that 1697 * is needed to transmit a packet on the wire. This is called only 1698 * once at attach, setup is done every reset. 1699 * 1700 **********************************************************************/ 1701 static int 1702 iflib_txsd_alloc(iflib_txq_t txq) 1703 { 1704 if_ctx_t ctx = txq->ift_ctx; 1705 if_shared_ctx_t sctx = ctx->ifc_sctx; 1706 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1707 device_t dev = ctx->ifc_dev; 1708 bus_size_t tsomaxsize; 1709 bus_addr_t lowaddr; 1710 int err, nsegments, ntsosegments; 1711 bool tso; 1712 1713 nsegments = scctx->isc_tx_nsegments; 1714 ntsosegments = scctx->isc_tx_tso_segments_max; 1715 tsomaxsize = scctx->isc_tx_tso_size_max; 1716 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1717 tsomaxsize += sizeof(struct ether_vlan_header); 1718 MPASS(scctx->isc_ntxd[0] > 0); 1719 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1720 MPASS(nsegments > 0); 1721 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1722 MPASS(ntsosegments > 0); 1723 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1724 } 1725 1726 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1727 1728 /* 1729 * Set up DMA tags for TX buffers. 1730 */ 1731 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1732 1, 0, /* alignment, bounds */ 1733 lowaddr, /* lowaddr */ 1734 BUS_SPACE_MAXADDR, /* highaddr */ 1735 NULL, NULL, /* filter, filterarg */ 1736 sctx->isc_tx_maxsize, /* maxsize */ 1737 nsegments, /* nsegments */ 1738 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1739 0, /* flags */ 1740 NULL, /* lockfunc */ 1741 NULL, /* lockfuncarg */ 1742 &txq->ift_buf_tag))) { 1743 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1744 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1745 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1746 goto fail; 1747 } 1748 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1749 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1750 1, 0, /* alignment, bounds */ 1751 lowaddr, /* lowaddr */ 1752 BUS_SPACE_MAXADDR, /* highaddr */ 1753 NULL, NULL, /* filter, filterarg */ 1754 tsomaxsize, /* maxsize */ 1755 ntsosegments, /* nsegments */ 1756 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1757 0, /* flags */ 1758 NULL, /* lockfunc */ 1759 NULL, /* lockfuncarg */ 1760 &txq->ift_tso_buf_tag))) { 1761 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1762 err); 1763 goto fail; 1764 } 1765 1766 /* Allocate memory for the TX mbuf map. */ 1767 if (!(txq->ift_sds.ifsd_m = 1768 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1769 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1770 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1771 err = ENOMEM; 1772 goto fail; 1773 } 1774 1775 /* 1776 * Create the DMA maps for TX buffers. 1777 */ 1778 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1779 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1780 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1781 device_printf(dev, 1782 "Unable to allocate TX buffer DMA map memory\n"); 1783 err = ENOMEM; 1784 goto fail; 1785 } 1786 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1787 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1788 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1789 device_printf(dev, 1790 "Unable to allocate TSO TX buffer map memory\n"); 1791 err = ENOMEM; 1792 goto fail; 1793 } 1794 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1795 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1796 &txq->ift_sds.ifsd_map[i]); 1797 if (err != 0) { 1798 device_printf(dev, "Unable to create TX DMA map\n"); 1799 goto fail; 1800 } 1801 if (!tso) 1802 continue; 1803 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1804 &txq->ift_sds.ifsd_tso_map[i]); 1805 if (err != 0) { 1806 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1807 goto fail; 1808 } 1809 } 1810 return (0); 1811 fail: 1812 /* We free all, it handles case where we are in the middle */ 1813 iflib_tx_structures_free(ctx); 1814 return (err); 1815 } 1816 1817 static void 1818 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1819 { 1820 bus_dmamap_t map; 1821 1822 if (txq->ift_sds.ifsd_map != NULL) { 1823 map = txq->ift_sds.ifsd_map[i]; 1824 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1825 bus_dmamap_unload(txq->ift_buf_tag, map); 1826 bus_dmamap_destroy(txq->ift_buf_tag, map); 1827 txq->ift_sds.ifsd_map[i] = NULL; 1828 } 1829 1830 if (txq->ift_sds.ifsd_tso_map != NULL) { 1831 map = txq->ift_sds.ifsd_tso_map[i]; 1832 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1833 BUS_DMASYNC_POSTWRITE); 1834 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1835 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1836 txq->ift_sds.ifsd_tso_map[i] = NULL; 1837 } 1838 } 1839 1840 static void 1841 iflib_txq_destroy(iflib_txq_t txq) 1842 { 1843 if_ctx_t ctx = txq->ift_ctx; 1844 1845 for (int i = 0; i < txq->ift_size; i++) 1846 iflib_txsd_destroy(ctx, txq, i); 1847 1848 if (txq->ift_br != NULL) { 1849 ifmp_ring_free(txq->ift_br); 1850 txq->ift_br = NULL; 1851 } 1852 1853 mtx_destroy(&txq->ift_mtx); 1854 1855 if (txq->ift_sds.ifsd_map != NULL) { 1856 free(txq->ift_sds.ifsd_map, M_IFLIB); 1857 txq->ift_sds.ifsd_map = NULL; 1858 } 1859 if (txq->ift_sds.ifsd_tso_map != NULL) { 1860 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1861 txq->ift_sds.ifsd_tso_map = NULL; 1862 } 1863 if (txq->ift_sds.ifsd_m != NULL) { 1864 free(txq->ift_sds.ifsd_m, M_IFLIB); 1865 txq->ift_sds.ifsd_m = NULL; 1866 } 1867 if (txq->ift_buf_tag != NULL) { 1868 bus_dma_tag_destroy(txq->ift_buf_tag); 1869 txq->ift_buf_tag = NULL; 1870 } 1871 if (txq->ift_tso_buf_tag != NULL) { 1872 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1873 txq->ift_tso_buf_tag = NULL; 1874 } 1875 if (txq->ift_ifdi != NULL) { 1876 free(txq->ift_ifdi, M_IFLIB); 1877 } 1878 } 1879 1880 static void 1881 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1882 { 1883 struct mbuf **mp; 1884 1885 mp = &txq->ift_sds.ifsd_m[i]; 1886 if (*mp == NULL) 1887 return; 1888 1889 if (txq->ift_sds.ifsd_map != NULL) { 1890 bus_dmamap_sync(txq->ift_buf_tag, 1891 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1892 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1893 } 1894 if (txq->ift_sds.ifsd_tso_map != NULL) { 1895 bus_dmamap_sync(txq->ift_tso_buf_tag, 1896 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1897 bus_dmamap_unload(txq->ift_tso_buf_tag, 1898 txq->ift_sds.ifsd_tso_map[i]); 1899 } 1900 m_freem(*mp); 1901 DBG_COUNTER_INC(tx_frees); 1902 *mp = NULL; 1903 } 1904 1905 static int 1906 iflib_txq_setup(iflib_txq_t txq) 1907 { 1908 if_ctx_t ctx = txq->ift_ctx; 1909 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1910 if_shared_ctx_t sctx = ctx->ifc_sctx; 1911 iflib_dma_info_t di; 1912 int i; 1913 1914 /* Set number of descriptors available */ 1915 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1916 /* XXX make configurable */ 1917 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1918 1919 /* Reset indices */ 1920 txq->ift_cidx_processed = 0; 1921 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1922 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1923 1924 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1925 bzero((void *)di->idi_vaddr, di->idi_size); 1926 1927 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1928 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1929 bus_dmamap_sync(di->idi_tag, di->idi_map, 1930 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1931 return (0); 1932 } 1933 1934 /********************************************************************* 1935 * 1936 * Allocate DMA resources for RX buffers as well as memory for the RX 1937 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1938 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1939 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1940 * Since we use use one entry in iflib_sw_rx_desc_array per received 1941 * packet, the maximum number of entries we'll need is equal to the 1942 * number of hardware receive descriptors that we've allocated. 1943 * 1944 **********************************************************************/ 1945 static int 1946 iflib_rxsd_alloc(iflib_rxq_t rxq) 1947 { 1948 if_ctx_t ctx = rxq->ifr_ctx; 1949 if_shared_ctx_t sctx = ctx->ifc_sctx; 1950 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1951 device_t dev = ctx->ifc_dev; 1952 iflib_fl_t fl; 1953 bus_addr_t lowaddr; 1954 int err; 1955 1956 MPASS(scctx->isc_nrxd[0] > 0); 1957 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1958 1959 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1960 1961 fl = rxq->ifr_fl; 1962 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1963 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1964 /* Set up DMA tag for RX buffers. */ 1965 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1966 1, 0, /* alignment, bounds */ 1967 lowaddr, /* lowaddr */ 1968 BUS_SPACE_MAXADDR, /* highaddr */ 1969 NULL, NULL, /* filter, filterarg */ 1970 sctx->isc_rx_maxsize, /* maxsize */ 1971 sctx->isc_rx_nsegments, /* nsegments */ 1972 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1973 0, /* flags */ 1974 NULL, /* lockfunc */ 1975 NULL, /* lockarg */ 1976 &fl->ifl_buf_tag); 1977 if (err) { 1978 device_printf(dev, 1979 "Unable to allocate RX DMA tag: %d\n", err); 1980 goto fail; 1981 } 1982 1983 /* Allocate memory for the RX mbuf map. */ 1984 if (!(fl->ifl_sds.ifsd_m = 1985 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1986 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1987 device_printf(dev, 1988 "Unable to allocate RX mbuf map memory\n"); 1989 err = ENOMEM; 1990 goto fail; 1991 } 1992 1993 /* Allocate memory for the direct RX cluster pointer map. */ 1994 if (!(fl->ifl_sds.ifsd_cl = 1995 (caddr_t *) malloc(sizeof(caddr_t) * 1996 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1997 device_printf(dev, 1998 "Unable to allocate RX cluster map memory\n"); 1999 err = ENOMEM; 2000 goto fail; 2001 } 2002 2003 /* Allocate memory for the RX cluster bus address map. */ 2004 if (!(fl->ifl_sds.ifsd_ba = 2005 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 2006 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2007 device_printf(dev, 2008 "Unable to allocate RX bus address map memory\n"); 2009 err = ENOMEM; 2010 goto fail; 2011 } 2012 2013 /* 2014 * Create the DMA maps for RX buffers. 2015 */ 2016 if (!(fl->ifl_sds.ifsd_map = 2017 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2018 device_printf(dev, 2019 "Unable to allocate RX buffer DMA map memory\n"); 2020 err = ENOMEM; 2021 goto fail; 2022 } 2023 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 2024 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 2025 &fl->ifl_sds.ifsd_map[i]); 2026 if (err != 0) { 2027 device_printf(dev, "Unable to create RX buffer DMA map\n"); 2028 goto fail; 2029 } 2030 } 2031 } 2032 return (0); 2033 2034 fail: 2035 iflib_rx_structures_free(ctx); 2036 return (err); 2037 } 2038 2039 /* 2040 * Internal service routines 2041 */ 2042 2043 struct rxq_refill_cb_arg { 2044 int error; 2045 bus_dma_segment_t seg; 2046 int nseg; 2047 }; 2048 2049 static void 2050 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2051 { 2052 struct rxq_refill_cb_arg *cb_arg = arg; 2053 2054 cb_arg->error = error; 2055 cb_arg->seg = segs[0]; 2056 cb_arg->nseg = nseg; 2057 } 2058 2059 /** 2060 * iflib_fl_refill - refill an rxq free-buffer list 2061 * @ctx: the iflib context 2062 * @fl: the free list to refill 2063 * @count: the number of new buffers to allocate 2064 * 2065 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 2066 * The caller must assure that @count does not exceed the queue's capacity 2067 * minus one (since we always leave a descriptor unavailable). 2068 */ 2069 static uint8_t 2070 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 2071 { 2072 struct if_rxd_update iru; 2073 struct rxq_refill_cb_arg cb_arg; 2074 struct mbuf *m; 2075 caddr_t cl, *sd_cl; 2076 struct mbuf **sd_m; 2077 bus_dmamap_t *sd_map; 2078 bus_addr_t bus_addr, *sd_ba; 2079 int err, frag_idx, i, idx, n, pidx; 2080 qidx_t credits; 2081 2082 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 2083 2084 sd_m = fl->ifl_sds.ifsd_m; 2085 sd_map = fl->ifl_sds.ifsd_map; 2086 sd_cl = fl->ifl_sds.ifsd_cl; 2087 sd_ba = fl->ifl_sds.ifsd_ba; 2088 pidx = fl->ifl_pidx; 2089 idx = pidx; 2090 frag_idx = fl->ifl_fragidx; 2091 credits = fl->ifl_credits; 2092 2093 i = 0; 2094 n = count; 2095 MPASS(n > 0); 2096 MPASS(credits + n <= fl->ifl_size); 2097 2098 if (pidx < fl->ifl_cidx) 2099 MPASS(pidx + n <= fl->ifl_cidx); 2100 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 2101 MPASS(fl->ifl_gen == 0); 2102 if (pidx > fl->ifl_cidx) 2103 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 2104 2105 DBG_COUNTER_INC(fl_refills); 2106 if (n > 8) 2107 DBG_COUNTER_INC(fl_refills_large); 2108 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 2109 while (n-- > 0) { 2110 /* 2111 * We allocate an uninitialized mbuf + cluster, mbuf is 2112 * initialized after rx. 2113 * 2114 * If the cluster is still set then we know a minimum sized 2115 * packet was received 2116 */ 2117 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2118 &frag_idx); 2119 if (frag_idx < 0) 2120 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2121 MPASS(frag_idx >= 0); 2122 if ((cl = sd_cl[frag_idx]) == NULL) { 2123 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2124 if (__predict_false(cl == NULL)) 2125 break; 2126 2127 cb_arg.error = 0; 2128 MPASS(sd_map != NULL); 2129 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2130 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2131 BUS_DMA_NOWAIT); 2132 if (__predict_false(err != 0 || cb_arg.error)) { 2133 uma_zfree(fl->ifl_zone, cl); 2134 break; 2135 } 2136 2137 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2138 sd_cl[frag_idx] = cl; 2139 #if MEMORY_LOGGING 2140 fl->ifl_cl_enqueued++; 2141 #endif 2142 } else { 2143 bus_addr = sd_ba[frag_idx]; 2144 } 2145 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2146 BUS_DMASYNC_PREREAD); 2147 2148 if (sd_m[frag_idx] == NULL) { 2149 m = m_gethdr_raw(M_NOWAIT, 0); 2150 if (__predict_false(m == NULL)) 2151 break; 2152 sd_m[frag_idx] = m; 2153 } 2154 bit_set(fl->ifl_rx_bitmap, frag_idx); 2155 #if MEMORY_LOGGING 2156 fl->ifl_m_enqueued++; 2157 #endif 2158 2159 DBG_COUNTER_INC(rx_allocs); 2160 fl->ifl_rxd_idxs[i] = frag_idx; 2161 fl->ifl_bus_addrs[i] = bus_addr; 2162 credits++; 2163 i++; 2164 MPASS(credits <= fl->ifl_size); 2165 if (++idx == fl->ifl_size) { 2166 #ifdef INVARIANTS 2167 fl->ifl_gen = 1; 2168 #endif 2169 idx = 0; 2170 } 2171 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2172 iru.iru_pidx = pidx; 2173 iru.iru_count = i; 2174 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2175 fl->ifl_pidx = idx; 2176 fl->ifl_credits = credits; 2177 pidx = idx; 2178 i = 0; 2179 } 2180 } 2181 2182 if (n < count - 1) { 2183 if (i != 0) { 2184 iru.iru_pidx = pidx; 2185 iru.iru_count = i; 2186 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2187 fl->ifl_pidx = idx; 2188 fl->ifl_credits = credits; 2189 } 2190 DBG_COUNTER_INC(rxd_flush); 2191 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2192 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2193 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2194 fl->ifl_id, fl->ifl_pidx); 2195 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2196 fl->ifl_fragidx = frag_idx + 1; 2197 if (fl->ifl_fragidx == fl->ifl_size) 2198 fl->ifl_fragidx = 0; 2199 } else { 2200 fl->ifl_fragidx = frag_idx; 2201 } 2202 } 2203 2204 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2205 } 2206 2207 static inline uint8_t 2208 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2209 { 2210 /* 2211 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2212 * This is important as it confuses most NICs. For instance, 2213 * Intel NICs have (per receive ring) RDH and RDT registers, where 2214 * RDH points to the next receive descriptor to be used by the NIC, 2215 * and RDT for the next receive descriptor to be published by the 2216 * driver to the NIC (RDT - 1 is thus the last valid one). 2217 * The condition RDH == RDT means no descriptors are available to 2218 * the NIC, and thus it would be ambiguous if it also meant that 2219 * all the descriptors are available to the NIC. 2220 */ 2221 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2222 #ifdef INVARIANTS 2223 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2224 #endif 2225 2226 MPASS(fl->ifl_credits <= fl->ifl_size); 2227 MPASS(reclaimable == delta); 2228 2229 if (reclaimable > 0) 2230 return (iflib_fl_refill(ctx, fl, reclaimable)); 2231 return (0); 2232 } 2233 2234 uint8_t 2235 iflib_in_detach(if_ctx_t ctx) 2236 { 2237 bool in_detach; 2238 2239 STATE_LOCK(ctx); 2240 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2241 STATE_UNLOCK(ctx); 2242 return (in_detach); 2243 } 2244 2245 static void 2246 iflib_fl_bufs_free(iflib_fl_t fl) 2247 { 2248 iflib_dma_info_t idi = fl->ifl_ifdi; 2249 bus_dmamap_t sd_map; 2250 uint32_t i; 2251 2252 for (i = 0; i < fl->ifl_size; i++) { 2253 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2254 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2255 2256 if (*sd_cl != NULL) { 2257 sd_map = fl->ifl_sds.ifsd_map[i]; 2258 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2259 BUS_DMASYNC_POSTREAD); 2260 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2261 uma_zfree(fl->ifl_zone, *sd_cl); 2262 *sd_cl = NULL; 2263 if (*sd_m != NULL) { 2264 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2265 m_free_raw(*sd_m); 2266 *sd_m = NULL; 2267 } 2268 } else { 2269 MPASS(*sd_m == NULL); 2270 } 2271 #if MEMORY_LOGGING 2272 fl->ifl_m_dequeued++; 2273 fl->ifl_cl_dequeued++; 2274 #endif 2275 } 2276 #ifdef INVARIANTS 2277 for (i = 0; i < fl->ifl_size; i++) { 2278 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2279 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2280 } 2281 #endif 2282 /* 2283 * Reset free list values 2284 */ 2285 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2286 bzero(idi->idi_vaddr, idi->idi_size); 2287 } 2288 2289 /********************************************************************* 2290 * 2291 * Initialize a free list and its buffers. 2292 * 2293 **********************************************************************/ 2294 static int 2295 iflib_fl_setup(iflib_fl_t fl) 2296 { 2297 iflib_rxq_t rxq = fl->ifl_rxq; 2298 if_ctx_t ctx = rxq->ifr_ctx; 2299 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2300 int qidx; 2301 2302 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2303 /* 2304 ** Free current RX buffer structs and their mbufs 2305 */ 2306 iflib_fl_bufs_free(fl); 2307 /* Now replenish the mbufs */ 2308 MPASS(fl->ifl_credits == 0); 2309 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2310 if (scctx->isc_rxd_buf_size[qidx] != 0) 2311 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2312 else 2313 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2314 /* 2315 * ifl_buf_size may be a driver-supplied value, so pull it up 2316 * to the selected mbuf size. 2317 */ 2318 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2319 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2320 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2321 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2322 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2323 2324 /* 2325 * Avoid pre-allocating zillions of clusters to an idle card 2326 * potentially speeding up attach. In any case make sure 2327 * to leave a descriptor unavailable. See the comment in 2328 * iflib_fl_refill_all(). 2329 */ 2330 MPASS(fl->ifl_size > 0); 2331 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2332 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2333 return (ENOBUFS); 2334 /* 2335 * handle failure 2336 */ 2337 MPASS(rxq != NULL); 2338 MPASS(fl->ifl_ifdi != NULL); 2339 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2340 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2341 return (0); 2342 } 2343 2344 /********************************************************************* 2345 * 2346 * Free receive ring data structures 2347 * 2348 **********************************************************************/ 2349 static void 2350 iflib_rx_sds_free(iflib_rxq_t rxq) 2351 { 2352 iflib_fl_t fl; 2353 int i, j; 2354 2355 if (rxq->ifr_fl != NULL) { 2356 for (i = 0; i < rxq->ifr_nfl; i++) { 2357 fl = &rxq->ifr_fl[i]; 2358 if (fl->ifl_buf_tag != NULL) { 2359 if (fl->ifl_sds.ifsd_map != NULL) { 2360 for (j = 0; j < fl->ifl_size; j++) { 2361 bus_dmamap_sync( 2362 fl->ifl_buf_tag, 2363 fl->ifl_sds.ifsd_map[j], 2364 BUS_DMASYNC_POSTREAD); 2365 bus_dmamap_unload( 2366 fl->ifl_buf_tag, 2367 fl->ifl_sds.ifsd_map[j]); 2368 bus_dmamap_destroy( 2369 fl->ifl_buf_tag, 2370 fl->ifl_sds.ifsd_map[j]); 2371 } 2372 } 2373 bus_dma_tag_destroy(fl->ifl_buf_tag); 2374 fl->ifl_buf_tag = NULL; 2375 } 2376 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2377 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2378 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2379 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2380 free(fl->ifl_rx_bitmap, M_IFLIB); 2381 fl->ifl_sds.ifsd_m = NULL; 2382 fl->ifl_sds.ifsd_cl = NULL; 2383 fl->ifl_sds.ifsd_ba = NULL; 2384 fl->ifl_sds.ifsd_map = NULL; 2385 fl->ifl_rx_bitmap = NULL; 2386 } 2387 free(rxq->ifr_fl, M_IFLIB); 2388 rxq->ifr_fl = NULL; 2389 free(rxq->ifr_ifdi, M_IFLIB); 2390 rxq->ifr_ifdi = NULL; 2391 rxq->ifr_cq_cidx = 0; 2392 } 2393 } 2394 2395 /* 2396 * Timer routine 2397 */ 2398 static void 2399 iflib_timer(void *arg) 2400 { 2401 iflib_txq_t txq = arg; 2402 if_ctx_t ctx = txq->ift_ctx; 2403 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2404 uint64_t this_tick = ticks; 2405 2406 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2407 return; 2408 2409 /* 2410 ** Check on the state of the TX queue(s), this 2411 ** can be done without the lock because its RO 2412 ** and the HUNG state will be static if set. 2413 */ 2414 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) { 2415 txq->ift_last_timer_tick = this_tick; 2416 IFDI_TIMER(ctx, txq->ift_id); 2417 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2418 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2419 (sctx->isc_pause_frames == 0))) 2420 goto hung; 2421 2422 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2423 ifmp_ring_is_stalled(txq->ift_br)) { 2424 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, 2425 ("queue can't be marked as hung if interface is down")); 2426 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2427 } 2428 txq->ift_cleaned_prev = txq->ift_cleaned; 2429 } 2430 /* handle any laggards */ 2431 if (txq->ift_db_pending) 2432 GROUPTASK_ENQUEUE(&txq->ift_task); 2433 2434 sctx->isc_pause_frames = 0; 2435 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2436 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, 2437 txq, txq->ift_timer.c_cpu); 2438 return; 2439 2440 hung: 2441 device_printf(ctx->ifc_dev, 2442 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2443 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2444 STATE_LOCK(ctx); 2445 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2446 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2447 iflib_admin_intr_deferred(ctx); 2448 STATE_UNLOCK(ctx); 2449 } 2450 2451 static uint16_t 2452 iflib_get_mbuf_size_for(unsigned int size) 2453 { 2454 2455 if (size <= MCLBYTES) 2456 return (MCLBYTES); 2457 else 2458 return (MJUMPAGESIZE); 2459 } 2460 2461 static void 2462 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2463 { 2464 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2465 2466 /* 2467 * XXX don't set the max_frame_size to larger 2468 * than the hardware can handle 2469 */ 2470 ctx->ifc_rx_mbuf_sz = 2471 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2472 } 2473 2474 uint32_t 2475 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2476 { 2477 2478 return (ctx->ifc_rx_mbuf_sz); 2479 } 2480 2481 static void 2482 iflib_init_locked(if_ctx_t ctx) 2483 { 2484 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2485 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2486 if_t ifp = ctx->ifc_ifp; 2487 iflib_fl_t fl; 2488 iflib_txq_t txq; 2489 iflib_rxq_t rxq; 2490 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2491 2492 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2493 IFDI_INTR_DISABLE(ctx); 2494 2495 /* 2496 * See iflib_stop(). Useful in case iflib_init_locked() is 2497 * called without first calling iflib_stop(). 2498 */ 2499 netmap_disable_all_rings(ifp); 2500 2501 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2502 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2503 /* Set hardware offload abilities */ 2504 if_clearhwassist(ifp); 2505 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2506 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2507 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2508 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2509 if (if_getcapenable(ifp) & IFCAP_TSO4) 2510 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2511 if (if_getcapenable(ifp) & IFCAP_TSO6) 2512 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2513 2514 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2515 CALLOUT_LOCK(txq); 2516 callout_stop(&txq->ift_timer); 2517 #ifdef DEV_NETMAP 2518 callout_stop(&txq->ift_netmap_timer); 2519 #endif /* DEV_NETMAP */ 2520 CALLOUT_UNLOCK(txq); 2521 (void)iflib_netmap_txq_init(ctx, txq); 2522 } 2523 2524 /* 2525 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2526 * that drivers can use the value when setting up the hardware receive 2527 * buffers. 2528 */ 2529 iflib_calc_rx_mbuf_sz(ctx); 2530 2531 #ifdef INVARIANTS 2532 i = if_getdrvflags(ifp); 2533 #endif 2534 IFDI_INIT(ctx); 2535 MPASS(if_getdrvflags(ifp) == i); 2536 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2537 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2538 /* This rxq is in netmap mode. Skip normal init. */ 2539 continue; 2540 } 2541 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2542 if (iflib_fl_setup(fl)) { 2543 device_printf(ctx->ifc_dev, 2544 "setting up free list %d failed - " 2545 "check cluster settings\n", j); 2546 goto done; 2547 } 2548 } 2549 } 2550 done: 2551 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2552 IFDI_INTR_ENABLE(ctx); 2553 txq = ctx->ifc_txqs; 2554 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2555 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 2556 txq->ift_timer.c_cpu); 2557 2558 /* Re-enable txsync/rxsync. */ 2559 netmap_enable_all_rings(ifp); 2560 } 2561 2562 static int 2563 iflib_media_change(if_t ifp) 2564 { 2565 if_ctx_t ctx = if_getsoftc(ifp); 2566 int err; 2567 2568 CTX_LOCK(ctx); 2569 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2570 iflib_if_init_locked(ctx); 2571 CTX_UNLOCK(ctx); 2572 return (err); 2573 } 2574 2575 static void 2576 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2577 { 2578 if_ctx_t ctx = if_getsoftc(ifp); 2579 2580 CTX_LOCK(ctx); 2581 IFDI_UPDATE_ADMIN_STATUS(ctx); 2582 IFDI_MEDIA_STATUS(ctx, ifmr); 2583 CTX_UNLOCK(ctx); 2584 } 2585 2586 void 2587 iflib_stop(if_ctx_t ctx) 2588 { 2589 iflib_txq_t txq = ctx->ifc_txqs; 2590 iflib_rxq_t rxq = ctx->ifc_rxqs; 2591 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2592 if_shared_ctx_t sctx = ctx->ifc_sctx; 2593 iflib_dma_info_t di; 2594 iflib_fl_t fl; 2595 int i, j; 2596 2597 /* Tell the stack that the interface is no longer active */ 2598 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2599 2600 IFDI_INTR_DISABLE(ctx); 2601 DELAY(1000); 2602 IFDI_STOP(ctx); 2603 DELAY(1000); 2604 2605 /* 2606 * Stop any pending txsync/rxsync and prevent new ones 2607 * form starting. Processes blocked in poll() will get 2608 * POLLERR. 2609 */ 2610 netmap_disable_all_rings(ctx->ifc_ifp); 2611 2612 iflib_debug_reset(); 2613 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2614 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2615 /* make sure all transmitters have completed before proceeding XXX */ 2616 2617 CALLOUT_LOCK(txq); 2618 callout_stop(&txq->ift_timer); 2619 #ifdef DEV_NETMAP 2620 callout_stop(&txq->ift_netmap_timer); 2621 #endif /* DEV_NETMAP */ 2622 CALLOUT_UNLOCK(txq); 2623 2624 /* clean any enqueued buffers */ 2625 iflib_ifmp_purge(txq); 2626 /* Free any existing tx buffers. */ 2627 for (j = 0; j < txq->ift_size; j++) { 2628 iflib_txsd_free(ctx, txq, j); 2629 } 2630 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2631 txq->ift_in_use = txq->ift_gen = txq->ift_no_desc_avail = 0; 2632 if (sctx->isc_flags & IFLIB_PRESERVE_TX_INDICES) 2633 txq->ift_cidx = txq->ift_pidx; 2634 else 2635 txq->ift_cidx = txq->ift_pidx = 0; 2636 2637 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2638 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2639 txq->ift_pullups = 0; 2640 ifmp_ring_reset_stats(txq->ift_br); 2641 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2642 bzero((void *)di->idi_vaddr, di->idi_size); 2643 } 2644 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2645 gtaskqueue_drain(rxq->ifr_task.gt_taskqueue, 2646 &rxq->ifr_task.gt_task); 2647 2648 rxq->ifr_cq_cidx = 0; 2649 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2650 bzero((void *)di->idi_vaddr, di->idi_size); 2651 /* also resets the free lists pidx/cidx */ 2652 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2653 iflib_fl_bufs_free(fl); 2654 } 2655 } 2656 2657 static inline caddr_t 2658 calc_next_rxd(iflib_fl_t fl, int cidx) 2659 { 2660 qidx_t size; 2661 int nrxd; 2662 caddr_t start, end, cur, next; 2663 2664 nrxd = fl->ifl_size; 2665 size = fl->ifl_rxd_size; 2666 start = fl->ifl_ifdi->idi_vaddr; 2667 2668 if (__predict_false(size == 0)) 2669 return (start); 2670 cur = start + size*cidx; 2671 end = start + size*nrxd; 2672 next = CACHE_PTR_NEXT(cur); 2673 return (next < end ? next : start); 2674 } 2675 2676 static inline void 2677 prefetch_pkts(iflib_fl_t fl, int cidx) 2678 { 2679 int nextptr; 2680 int nrxd = fl->ifl_size; 2681 caddr_t next_rxd; 2682 2683 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2684 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2685 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2686 next_rxd = calc_next_rxd(fl, cidx); 2687 prefetch(next_rxd); 2688 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2689 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2690 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2691 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2692 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2693 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2694 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2695 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2696 } 2697 2698 static struct mbuf * 2699 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2700 int *pf_rv, if_rxd_info_t ri) 2701 { 2702 bus_dmamap_t map; 2703 iflib_fl_t fl; 2704 caddr_t payload; 2705 struct mbuf *m; 2706 int flid, cidx, len, next; 2707 2708 map = NULL; 2709 flid = irf->irf_flid; 2710 cidx = irf->irf_idx; 2711 fl = &rxq->ifr_fl[flid]; 2712 sd->ifsd_fl = fl; 2713 m = fl->ifl_sds.ifsd_m[cidx]; 2714 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2715 fl->ifl_credits--; 2716 #if MEMORY_LOGGING 2717 fl->ifl_m_dequeued++; 2718 #endif 2719 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2720 prefetch_pkts(fl, cidx); 2721 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2722 prefetch(&fl->ifl_sds.ifsd_map[next]); 2723 map = fl->ifl_sds.ifsd_map[cidx]; 2724 2725 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2726 2727 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2728 irf->irf_len != 0) { 2729 payload = *sd->ifsd_cl; 2730 payload += ri->iri_pad; 2731 len = ri->iri_len - ri->iri_pad; 2732 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2733 len | PFIL_MEMPTR | PFIL_IN, NULL); 2734 switch (*pf_rv) { 2735 case PFIL_DROPPED: 2736 case PFIL_CONSUMED: 2737 /* 2738 * The filter ate it. Everything is recycled. 2739 */ 2740 m = NULL; 2741 unload = 0; 2742 break; 2743 case PFIL_REALLOCED: 2744 /* 2745 * The filter copied it. Everything is recycled. 2746 */ 2747 m = pfil_mem2mbuf(payload); 2748 unload = 0; 2749 break; 2750 case PFIL_PASS: 2751 /* 2752 * Filter said it was OK, so receive like 2753 * normal 2754 */ 2755 fl->ifl_sds.ifsd_m[cidx] = NULL; 2756 break; 2757 default: 2758 MPASS(0); 2759 } 2760 } else { 2761 fl->ifl_sds.ifsd_m[cidx] = NULL; 2762 if (pf_rv != NULL) 2763 *pf_rv = PFIL_PASS; 2764 } 2765 2766 if (unload && irf->irf_len != 0) 2767 bus_dmamap_unload(fl->ifl_buf_tag, map); 2768 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2769 if (__predict_false(fl->ifl_cidx == 0)) 2770 fl->ifl_gen = 0; 2771 bit_clear(fl->ifl_rx_bitmap, cidx); 2772 return (m); 2773 } 2774 2775 static struct mbuf * 2776 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2777 { 2778 struct mbuf *m, *mh, *mt; 2779 caddr_t cl; 2780 int *pf_rv_ptr, flags, i, padlen; 2781 bool consumed; 2782 2783 i = 0; 2784 mh = NULL; 2785 consumed = false; 2786 *pf_rv = PFIL_PASS; 2787 pf_rv_ptr = pf_rv; 2788 do { 2789 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2790 pf_rv_ptr, ri); 2791 2792 MPASS(*sd->ifsd_cl != NULL); 2793 2794 /* 2795 * Exclude zero-length frags & frags from 2796 * packets the filter has consumed or dropped 2797 */ 2798 if (ri->iri_frags[i].irf_len == 0 || consumed || 2799 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2800 if (mh == NULL) { 2801 /* everything saved here */ 2802 consumed = true; 2803 pf_rv_ptr = NULL; 2804 continue; 2805 } 2806 /* XXX we can save the cluster here, but not the mbuf */ 2807 m_init(m, M_NOWAIT, MT_DATA, 0); 2808 m_free(m); 2809 continue; 2810 } 2811 if (mh == NULL) { 2812 flags = M_PKTHDR|M_EXT; 2813 mh = mt = m; 2814 padlen = ri->iri_pad; 2815 } else { 2816 flags = M_EXT; 2817 mt->m_next = m; 2818 mt = m; 2819 /* assuming padding is only on the first fragment */ 2820 padlen = 0; 2821 } 2822 cl = *sd->ifsd_cl; 2823 *sd->ifsd_cl = NULL; 2824 2825 /* Can these two be made one ? */ 2826 m_init(m, M_NOWAIT, MT_DATA, flags); 2827 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2828 /* 2829 * These must follow m_init and m_cljset 2830 */ 2831 m->m_data += padlen; 2832 ri->iri_len -= padlen; 2833 m->m_len = ri->iri_frags[i].irf_len; 2834 } while (++i < ri->iri_nfrags); 2835 2836 return (mh); 2837 } 2838 2839 /* 2840 * Process one software descriptor 2841 */ 2842 static struct mbuf * 2843 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2844 { 2845 struct if_rxsd sd; 2846 struct mbuf *m; 2847 int pf_rv; 2848 2849 /* should I merge this back in now that the two paths are basically duplicated? */ 2850 if (ri->iri_nfrags == 1 && 2851 ri->iri_frags[0].irf_len != 0 && 2852 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2853 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2854 &pf_rv, ri); 2855 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2856 return (m); 2857 if (pf_rv == PFIL_PASS) { 2858 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2859 #ifndef __NO_STRICT_ALIGNMENT 2860 if (!IP_ALIGNED(m) && ri->iri_pad == 0) 2861 m->m_data += 2; 2862 #endif 2863 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2864 m->m_len = ri->iri_frags[0].irf_len; 2865 m->m_data += ri->iri_pad; 2866 ri->iri_len -= ri->iri_pad; 2867 } 2868 } else { 2869 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2870 if (m == NULL) 2871 return (NULL); 2872 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2873 return (m); 2874 } 2875 m->m_pkthdr.len = ri->iri_len; 2876 m->m_pkthdr.rcvif = ri->iri_ifp; 2877 m->m_flags |= ri->iri_flags; 2878 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2879 m->m_pkthdr.flowid = ri->iri_flowid; 2880 M_HASHTYPE_SET(m, ri->iri_rsstype); 2881 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2882 m->m_pkthdr.csum_data = ri->iri_csum_data; 2883 return (m); 2884 } 2885 2886 #if defined(INET6) || defined(INET) 2887 static void 2888 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2889 { 2890 CURVNET_SET(lc->ifp->if_vnet); 2891 #if defined(INET6) 2892 *v6 = V_ip6_forwarding; 2893 #endif 2894 #if defined(INET) 2895 *v4 = V_ipforwarding; 2896 #endif 2897 CURVNET_RESTORE(); 2898 } 2899 2900 /* 2901 * Returns true if it's possible this packet could be LROed. 2902 * if it returns false, it is guaranteed that tcp_lro_rx() 2903 * would not return zero. 2904 */ 2905 static bool 2906 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2907 { 2908 struct ether_header *eh; 2909 2910 eh = mtod(m, struct ether_header *); 2911 switch (eh->ether_type) { 2912 #if defined(INET6) 2913 case htons(ETHERTYPE_IPV6): 2914 return (!v6_forwarding); 2915 #endif 2916 #if defined (INET) 2917 case htons(ETHERTYPE_IP): 2918 return (!v4_forwarding); 2919 #endif 2920 } 2921 2922 return false; 2923 } 2924 #else 2925 static void 2926 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2927 { 2928 } 2929 #endif 2930 2931 static void 2932 _task_fn_rx_watchdog(void *context) 2933 { 2934 iflib_rxq_t rxq = context; 2935 2936 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2937 } 2938 2939 static uint8_t 2940 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2941 { 2942 if_t ifp; 2943 if_ctx_t ctx = rxq->ifr_ctx; 2944 if_shared_ctx_t sctx = ctx->ifc_sctx; 2945 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2946 int avail, i; 2947 qidx_t *cidxp; 2948 struct if_rxd_info ri; 2949 int err, budget_left, rx_bytes, rx_pkts; 2950 iflib_fl_t fl; 2951 int lro_enabled; 2952 bool v4_forwarding, v6_forwarding, lro_possible; 2953 uint8_t retval = 0; 2954 2955 /* 2956 * XXX early demux data packets so that if_input processing only handles 2957 * acks in interrupt context 2958 */ 2959 struct mbuf *m, *mh, *mt, *mf; 2960 2961 NET_EPOCH_ASSERT(); 2962 2963 lro_possible = v4_forwarding = v6_forwarding = false; 2964 ifp = ctx->ifc_ifp; 2965 mh = mt = NULL; 2966 MPASS(budget > 0); 2967 rx_pkts = rx_bytes = 0; 2968 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2969 cidxp = &rxq->ifr_cq_cidx; 2970 else 2971 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2972 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2973 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2974 retval |= iflib_fl_refill_all(ctx, fl); 2975 DBG_COUNTER_INC(rx_unavail); 2976 return (retval); 2977 } 2978 2979 /* pfil needs the vnet to be set */ 2980 CURVNET_SET_QUIET(ifp->if_vnet); 2981 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2982 if (__predict_false(!CTX_ACTIVE(ctx))) { 2983 DBG_COUNTER_INC(rx_ctx_inactive); 2984 break; 2985 } 2986 /* 2987 * Reset client set fields to their default values 2988 */ 2989 rxd_info_zero(&ri); 2990 ri.iri_qsidx = rxq->ifr_id; 2991 ri.iri_cidx = *cidxp; 2992 ri.iri_ifp = ifp; 2993 ri.iri_frags = rxq->ifr_frags; 2994 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2995 2996 if (err) 2997 goto err; 2998 rx_pkts += 1; 2999 rx_bytes += ri.iri_len; 3000 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 3001 *cidxp = ri.iri_cidx; 3002 /* Update our consumer index */ 3003 /* XXX NB: shurd - check if this is still safe */ 3004 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 3005 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 3006 /* was this only a completion queue message? */ 3007 if (__predict_false(ri.iri_nfrags == 0)) 3008 continue; 3009 } 3010 MPASS(ri.iri_nfrags != 0); 3011 MPASS(ri.iri_len != 0); 3012 3013 /* will advance the cidx on the corresponding free lists */ 3014 m = iflib_rxd_pkt_get(rxq, &ri); 3015 avail--; 3016 budget_left--; 3017 if (avail == 0 && budget_left) 3018 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 3019 3020 if (__predict_false(m == NULL)) 3021 continue; 3022 3023 /* imm_pkt: -- cxgb */ 3024 if (mh == NULL) 3025 mh = mt = m; 3026 else { 3027 mt->m_nextpkt = m; 3028 mt = m; 3029 } 3030 } 3031 CURVNET_RESTORE(); 3032 /* make sure that we can refill faster than drain */ 3033 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3034 retval |= iflib_fl_refill_all(ctx, fl); 3035 3036 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 3037 if (lro_enabled) 3038 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 3039 mt = mf = NULL; 3040 while (mh != NULL) { 3041 m = mh; 3042 mh = mh->m_nextpkt; 3043 m->m_nextpkt = NULL; 3044 #ifndef __NO_STRICT_ALIGNMENT 3045 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 3046 continue; 3047 #endif 3048 #if defined(INET6) || defined(INET) 3049 if (lro_enabled) { 3050 if (!lro_possible) { 3051 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 3052 if (lro_possible && mf != NULL) { 3053 ifp->if_input(ifp, mf); 3054 DBG_COUNTER_INC(rx_if_input); 3055 mt = mf = NULL; 3056 } 3057 } 3058 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 3059 (CSUM_L4_CALC|CSUM_L4_VALID)) { 3060 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 3061 continue; 3062 } 3063 } 3064 #endif 3065 if (lro_possible) { 3066 ifp->if_input(ifp, m); 3067 DBG_COUNTER_INC(rx_if_input); 3068 continue; 3069 } 3070 3071 if (mf == NULL) 3072 mf = m; 3073 if (mt != NULL) 3074 mt->m_nextpkt = m; 3075 mt = m; 3076 } 3077 if (mf != NULL) { 3078 ifp->if_input(ifp, mf); 3079 DBG_COUNTER_INC(rx_if_input); 3080 } 3081 3082 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 3083 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 3084 3085 /* 3086 * Flush any outstanding LRO work 3087 */ 3088 #if defined(INET6) || defined(INET) 3089 tcp_lro_flush_all(&rxq->ifr_lc); 3090 #endif 3091 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 3092 retval |= IFLIB_RXEOF_MORE; 3093 return (retval); 3094 err: 3095 STATE_LOCK(ctx); 3096 ctx->ifc_flags |= IFC_DO_RESET; 3097 iflib_admin_intr_deferred(ctx); 3098 STATE_UNLOCK(ctx); 3099 return (0); 3100 } 3101 3102 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 3103 static inline qidx_t 3104 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 3105 { 3106 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3107 qidx_t minthresh = txq->ift_size / 8; 3108 if (in_use > 4*minthresh) 3109 return (notify_count); 3110 if (in_use > 2*minthresh) 3111 return (notify_count >> 1); 3112 if (in_use > minthresh) 3113 return (notify_count >> 3); 3114 return (0); 3115 } 3116 3117 static inline qidx_t 3118 txq_max_rs_deferred(iflib_txq_t txq) 3119 { 3120 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3121 qidx_t minthresh = txq->ift_size / 8; 3122 if (txq->ift_in_use > 4*minthresh) 3123 return (notify_count); 3124 if (txq->ift_in_use > 2*minthresh) 3125 return (notify_count >> 1); 3126 if (txq->ift_in_use > minthresh) 3127 return (notify_count >> 2); 3128 return (2); 3129 } 3130 3131 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 3132 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 3133 3134 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 3135 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 3136 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 3137 3138 /* forward compatibility for cxgb */ 3139 #define FIRST_QSET(ctx) 0 3140 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3141 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3142 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3143 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3144 3145 /* XXX we should be setting this to something other than zero */ 3146 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 3147 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3148 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3149 3150 static inline bool 3151 iflib_txd_db_check(iflib_txq_t txq, int ring) 3152 { 3153 if_ctx_t ctx = txq->ift_ctx; 3154 qidx_t dbval, max; 3155 3156 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use); 3157 3158 /* force || threshold exceeded || at the edge of the ring */ 3159 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2)) { 3160 3161 /* 3162 * 'npending' is used if the card's doorbell is in terms of the number of descriptors 3163 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the 3164 * producer index explicitly (INTC). 3165 */ 3166 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3167 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3168 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3169 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3170 3171 /* 3172 * Absent bugs there are zero packets pending so reset pending counts to zero. 3173 */ 3174 txq->ift_db_pending = txq->ift_npending = 0; 3175 return (true); 3176 } 3177 return (false); 3178 } 3179 3180 #ifdef PKT_DEBUG 3181 static void 3182 print_pkt(if_pkt_info_t pi) 3183 { 3184 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3185 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3186 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3187 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3188 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3189 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3190 } 3191 #endif 3192 3193 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3194 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3195 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3196 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3197 3198 static int 3199 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3200 { 3201 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3202 struct ether_vlan_header *eh; 3203 struct mbuf *m; 3204 3205 m = *mp; 3206 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3207 M_WRITABLE(m) == 0) { 3208 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3209 return (ENOMEM); 3210 } else { 3211 m_freem(*mp); 3212 DBG_COUNTER_INC(tx_frees); 3213 *mp = m; 3214 } 3215 } 3216 3217 /* 3218 * Determine where frame payload starts. 3219 * Jump over vlan headers if already present, 3220 * helpful for QinQ too. 3221 */ 3222 if (__predict_false(m->m_len < sizeof(*eh))) { 3223 txq->ift_pullups++; 3224 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3225 return (ENOMEM); 3226 } 3227 eh = mtod(m, struct ether_vlan_header *); 3228 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3229 pi->ipi_etype = ntohs(eh->evl_proto); 3230 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3231 } else { 3232 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3233 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3234 } 3235 3236 switch (pi->ipi_etype) { 3237 #ifdef INET 3238 case ETHERTYPE_IP: 3239 { 3240 struct mbuf *n; 3241 struct ip *ip = NULL; 3242 struct tcphdr *th = NULL; 3243 int minthlen; 3244 3245 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3246 if (__predict_false(m->m_len < minthlen)) { 3247 /* 3248 * if this code bloat is causing too much of a hit 3249 * move it to a separate function and mark it noinline 3250 */ 3251 if (m->m_len == pi->ipi_ehdrlen) { 3252 n = m->m_next; 3253 MPASS(n); 3254 if (n->m_len >= sizeof(*ip)) { 3255 ip = (struct ip *)n->m_data; 3256 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3257 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3258 } else { 3259 txq->ift_pullups++; 3260 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3261 return (ENOMEM); 3262 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3263 } 3264 } else { 3265 txq->ift_pullups++; 3266 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3267 return (ENOMEM); 3268 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3269 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3270 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3271 } 3272 } else { 3273 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3274 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3275 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3276 } 3277 pi->ipi_ip_hlen = ip->ip_hl << 2; 3278 pi->ipi_ipproto = ip->ip_p; 3279 pi->ipi_flags |= IPI_TX_IPV4; 3280 3281 /* TCP checksum offload may require TCP header length */ 3282 if (IS_TX_OFFLOAD4(pi)) { 3283 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3284 if (__predict_false(th == NULL)) { 3285 txq->ift_pullups++; 3286 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3287 return (ENOMEM); 3288 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3289 } 3290 pi->ipi_tcp_hflags = th->th_flags; 3291 pi->ipi_tcp_hlen = th->th_off << 2; 3292 pi->ipi_tcp_seq = th->th_seq; 3293 } 3294 if (IS_TSO4(pi)) { 3295 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3296 return (ENXIO); 3297 /* 3298 * TSO always requires hardware checksum offload. 3299 */ 3300 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3301 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3302 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3303 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3304 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3305 ip->ip_sum = 0; 3306 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3307 } 3308 } 3309 } 3310 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3311 ip->ip_sum = 0; 3312 3313 break; 3314 } 3315 #endif 3316 #ifdef INET6 3317 case ETHERTYPE_IPV6: 3318 { 3319 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3320 struct tcphdr *th; 3321 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3322 3323 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3324 txq->ift_pullups++; 3325 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3326 return (ENOMEM); 3327 } 3328 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3329 3330 /* XXX-BZ this will go badly in case of ext hdrs. */ 3331 pi->ipi_ipproto = ip6->ip6_nxt; 3332 pi->ipi_flags |= IPI_TX_IPV6; 3333 3334 /* TCP checksum offload may require TCP header length */ 3335 if (IS_TX_OFFLOAD6(pi)) { 3336 if (pi->ipi_ipproto == IPPROTO_TCP) { 3337 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3338 txq->ift_pullups++; 3339 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3340 return (ENOMEM); 3341 } 3342 pi->ipi_tcp_hflags = th->th_flags; 3343 pi->ipi_tcp_hlen = th->th_off << 2; 3344 pi->ipi_tcp_seq = th->th_seq; 3345 } 3346 if (IS_TSO6(pi)) { 3347 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3348 return (ENXIO); 3349 /* 3350 * TSO always requires hardware checksum offload. 3351 */ 3352 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3353 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3354 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3355 } 3356 } 3357 break; 3358 } 3359 #endif 3360 default: 3361 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3362 pi->ipi_ip_hlen = 0; 3363 break; 3364 } 3365 *mp = m; 3366 3367 return (0); 3368 } 3369 3370 /* 3371 * If dodgy hardware rejects the scatter gather chain we've handed it 3372 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3373 * m_defrag'd mbufs 3374 */ 3375 static __noinline struct mbuf * 3376 iflib_remove_mbuf(iflib_txq_t txq) 3377 { 3378 int ntxd, pidx; 3379 struct mbuf *m, **ifsd_m; 3380 3381 ifsd_m = txq->ift_sds.ifsd_m; 3382 ntxd = txq->ift_size; 3383 pidx = txq->ift_pidx & (ntxd - 1); 3384 ifsd_m = txq->ift_sds.ifsd_m; 3385 m = ifsd_m[pidx]; 3386 ifsd_m[pidx] = NULL; 3387 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3388 if (txq->ift_sds.ifsd_tso_map != NULL) 3389 bus_dmamap_unload(txq->ift_tso_buf_tag, 3390 txq->ift_sds.ifsd_tso_map[pidx]); 3391 #if MEMORY_LOGGING 3392 txq->ift_dequeued++; 3393 #endif 3394 return (m); 3395 } 3396 3397 static inline caddr_t 3398 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3399 { 3400 qidx_t size; 3401 int ntxd; 3402 caddr_t start, end, cur, next; 3403 3404 ntxd = txq->ift_size; 3405 size = txq->ift_txd_size[qid]; 3406 start = txq->ift_ifdi[qid].idi_vaddr; 3407 3408 if (__predict_false(size == 0)) 3409 return (start); 3410 cur = start + size*cidx; 3411 end = start + size*ntxd; 3412 next = CACHE_PTR_NEXT(cur); 3413 return (next < end ? next : start); 3414 } 3415 3416 /* 3417 * Pad an mbuf to ensure a minimum ethernet frame size. 3418 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3419 */ 3420 static __noinline int 3421 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3422 { 3423 /* 3424 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3425 * and ARP message is the smallest common payload I can think of 3426 */ 3427 static char pad[18]; /* just zeros */ 3428 int n; 3429 struct mbuf *new_head; 3430 3431 if (!M_WRITABLE(*m_head)) { 3432 new_head = m_dup(*m_head, M_NOWAIT); 3433 if (new_head == NULL) { 3434 m_freem(*m_head); 3435 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3436 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3437 DBG_COUNTER_INC(tx_frees); 3438 return ENOMEM; 3439 } 3440 m_freem(*m_head); 3441 *m_head = new_head; 3442 } 3443 3444 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3445 n > 0; n -= sizeof(pad)) 3446 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3447 break; 3448 3449 if (n > 0) { 3450 m_freem(*m_head); 3451 device_printf(dev, "cannot pad short frame\n"); 3452 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3453 DBG_COUNTER_INC(tx_frees); 3454 return (ENOBUFS); 3455 } 3456 3457 return 0; 3458 } 3459 3460 static int 3461 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3462 { 3463 if_ctx_t ctx; 3464 if_shared_ctx_t sctx; 3465 if_softc_ctx_t scctx; 3466 bus_dma_tag_t buf_tag; 3467 bus_dma_segment_t *segs; 3468 struct mbuf *m_head, **ifsd_m; 3469 void *next_txd; 3470 bus_dmamap_t map; 3471 struct if_pkt_info pi; 3472 int remap = 0; 3473 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3474 3475 ctx = txq->ift_ctx; 3476 sctx = ctx->ifc_sctx; 3477 scctx = &ctx->ifc_softc_ctx; 3478 segs = txq->ift_segs; 3479 ntxd = txq->ift_size; 3480 m_head = *m_headp; 3481 map = NULL; 3482 3483 /* 3484 * If we're doing TSO the next descriptor to clean may be quite far ahead 3485 */ 3486 cidx = txq->ift_cidx; 3487 pidx = txq->ift_pidx; 3488 if (ctx->ifc_flags & IFC_PREFETCH) { 3489 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3490 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3491 next_txd = calc_next_txd(txq, cidx, 0); 3492 prefetch(next_txd); 3493 } 3494 3495 /* prefetch the next cache line of mbuf pointers and flags */ 3496 prefetch(&txq->ift_sds.ifsd_m[next]); 3497 prefetch(&txq->ift_sds.ifsd_map[next]); 3498 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3499 } 3500 map = txq->ift_sds.ifsd_map[pidx]; 3501 ifsd_m = txq->ift_sds.ifsd_m; 3502 3503 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3504 buf_tag = txq->ift_tso_buf_tag; 3505 max_segs = scctx->isc_tx_tso_segments_max; 3506 map = txq->ift_sds.ifsd_tso_map[pidx]; 3507 MPASS(buf_tag != NULL); 3508 MPASS(max_segs > 0); 3509 } else { 3510 buf_tag = txq->ift_buf_tag; 3511 max_segs = scctx->isc_tx_nsegments; 3512 map = txq->ift_sds.ifsd_map[pidx]; 3513 } 3514 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3515 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3516 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3517 if (err) { 3518 DBG_COUNTER_INC(encap_txd_encap_fail); 3519 return err; 3520 } 3521 } 3522 m_head = *m_headp; 3523 3524 pkt_info_zero(&pi); 3525 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3526 pi.ipi_pidx = pidx; 3527 pi.ipi_qsidx = txq->ift_id; 3528 pi.ipi_len = m_head->m_pkthdr.len; 3529 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3530 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3531 3532 /* deliberate bitwise OR to make one condition */ 3533 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3534 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3535 DBG_COUNTER_INC(encap_txd_encap_fail); 3536 return (err); 3537 } 3538 m_head = *m_headp; 3539 } 3540 3541 retry: 3542 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3543 BUS_DMA_NOWAIT); 3544 defrag: 3545 if (__predict_false(err)) { 3546 switch (err) { 3547 case EFBIG: 3548 /* try collapse once and defrag once */ 3549 if (remap == 0) { 3550 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3551 /* try defrag if collapsing fails */ 3552 if (m_head == NULL) 3553 remap++; 3554 } 3555 if (remap == 1) { 3556 txq->ift_mbuf_defrag++; 3557 m_head = m_defrag(*m_headp, M_NOWAIT); 3558 } 3559 /* 3560 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3561 * failed to map an mbuf that was run through m_defrag 3562 */ 3563 MPASS(remap <= 1); 3564 if (__predict_false(m_head == NULL || remap > 1)) 3565 goto defrag_failed; 3566 remap++; 3567 *m_headp = m_head; 3568 goto retry; 3569 break; 3570 case ENOMEM: 3571 txq->ift_no_tx_dma_setup++; 3572 break; 3573 default: 3574 txq->ift_no_tx_dma_setup++; 3575 m_freem(*m_headp); 3576 DBG_COUNTER_INC(tx_frees); 3577 *m_headp = NULL; 3578 break; 3579 } 3580 txq->ift_map_failed++; 3581 DBG_COUNTER_INC(encap_load_mbuf_fail); 3582 DBG_COUNTER_INC(encap_txd_encap_fail); 3583 return (err); 3584 } 3585 ifsd_m[pidx] = m_head; 3586 /* 3587 * XXX assumes a 1 to 1 relationship between segments and 3588 * descriptors - this does not hold true on all drivers, e.g. 3589 * cxgb 3590 */ 3591 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3592 txq->ift_no_desc_avail++; 3593 bus_dmamap_unload(buf_tag, map); 3594 DBG_COUNTER_INC(encap_txq_avail_fail); 3595 DBG_COUNTER_INC(encap_txd_encap_fail); 3596 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3597 GROUPTASK_ENQUEUE(&txq->ift_task); 3598 return (ENOBUFS); 3599 } 3600 /* 3601 * On Intel cards we can greatly reduce the number of TX interrupts 3602 * we see by only setting report status on every Nth descriptor. 3603 * However, this also means that the driver will need to keep track 3604 * of the descriptors that RS was set on to check them for the DD bit. 3605 */ 3606 txq->ift_rs_pending += nsegs + 1; 3607 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3608 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3609 pi.ipi_flags |= IPI_TX_INTR; 3610 txq->ift_rs_pending = 0; 3611 } 3612 3613 pi.ipi_segs = segs; 3614 pi.ipi_nsegs = nsegs; 3615 3616 MPASS(pidx >= 0 && pidx < txq->ift_size); 3617 #ifdef PKT_DEBUG 3618 print_pkt(&pi); 3619 #endif 3620 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3621 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3622 DBG_COUNTER_INC(tx_encap); 3623 MPASS(pi.ipi_new_pidx < txq->ift_size); 3624 3625 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3626 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3627 ndesc += txq->ift_size; 3628 txq->ift_gen = 1; 3629 } 3630 /* 3631 * drivers can need as many as 3632 * two sentinels 3633 */ 3634 MPASS(ndesc <= pi.ipi_nsegs + 2); 3635 MPASS(pi.ipi_new_pidx != pidx); 3636 MPASS(ndesc > 0); 3637 txq->ift_in_use += ndesc; 3638 txq->ift_db_pending += ndesc; 3639 3640 /* 3641 * We update the last software descriptor again here because there may 3642 * be a sentinel and/or there may be more mbufs than segments 3643 */ 3644 txq->ift_pidx = pi.ipi_new_pidx; 3645 txq->ift_npending += pi.ipi_ndescs; 3646 } else { 3647 *m_headp = m_head = iflib_remove_mbuf(txq); 3648 if (err == EFBIG) { 3649 txq->ift_txd_encap_efbig++; 3650 if (remap < 2) { 3651 remap = 1; 3652 goto defrag; 3653 } 3654 } 3655 goto defrag_failed; 3656 } 3657 /* 3658 * err can't possibly be non-zero here, so we don't neet to test it 3659 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3660 */ 3661 return (err); 3662 3663 defrag_failed: 3664 txq->ift_mbuf_defrag_failed++; 3665 txq->ift_map_failed++; 3666 m_freem(*m_headp); 3667 DBG_COUNTER_INC(tx_frees); 3668 *m_headp = NULL; 3669 DBG_COUNTER_INC(encap_txd_encap_fail); 3670 return (ENOMEM); 3671 } 3672 3673 static void 3674 iflib_tx_desc_free(iflib_txq_t txq, int n) 3675 { 3676 uint32_t qsize, cidx, mask, gen; 3677 struct mbuf *m, **ifsd_m; 3678 bool do_prefetch; 3679 3680 cidx = txq->ift_cidx; 3681 gen = txq->ift_gen; 3682 qsize = txq->ift_size; 3683 mask = qsize-1; 3684 ifsd_m = txq->ift_sds.ifsd_m; 3685 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3686 3687 while (n-- > 0) { 3688 if (do_prefetch) { 3689 prefetch(ifsd_m[(cidx + 3) & mask]); 3690 prefetch(ifsd_m[(cidx + 4) & mask]); 3691 } 3692 if ((m = ifsd_m[cidx]) != NULL) { 3693 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3694 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3695 bus_dmamap_sync(txq->ift_tso_buf_tag, 3696 txq->ift_sds.ifsd_tso_map[cidx], 3697 BUS_DMASYNC_POSTWRITE); 3698 bus_dmamap_unload(txq->ift_tso_buf_tag, 3699 txq->ift_sds.ifsd_tso_map[cidx]); 3700 } else { 3701 bus_dmamap_sync(txq->ift_buf_tag, 3702 txq->ift_sds.ifsd_map[cidx], 3703 BUS_DMASYNC_POSTWRITE); 3704 bus_dmamap_unload(txq->ift_buf_tag, 3705 txq->ift_sds.ifsd_map[cidx]); 3706 } 3707 /* XXX we don't support any drivers that batch packets yet */ 3708 MPASS(m->m_nextpkt == NULL); 3709 m_freem(m); 3710 ifsd_m[cidx] = NULL; 3711 #if MEMORY_LOGGING 3712 txq->ift_dequeued++; 3713 #endif 3714 DBG_COUNTER_INC(tx_frees); 3715 } 3716 if (__predict_false(++cidx == qsize)) { 3717 cidx = 0; 3718 gen = 0; 3719 } 3720 } 3721 txq->ift_cidx = cidx; 3722 txq->ift_gen = gen; 3723 } 3724 3725 static __inline int 3726 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3727 { 3728 int reclaim; 3729 if_ctx_t ctx = txq->ift_ctx; 3730 3731 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3732 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3733 3734 /* 3735 * Need a rate-limiting check so that this isn't called every time 3736 */ 3737 iflib_tx_credits_update(ctx, txq); 3738 reclaim = DESC_RECLAIMABLE(txq); 3739 3740 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3741 #ifdef INVARIANTS 3742 if (iflib_verbose_debug) { 3743 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3744 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3745 reclaim, thresh); 3746 } 3747 #endif 3748 return (0); 3749 } 3750 iflib_tx_desc_free(txq, reclaim); 3751 txq->ift_cleaned += reclaim; 3752 txq->ift_in_use -= reclaim; 3753 3754 return (reclaim); 3755 } 3756 3757 static struct mbuf ** 3758 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3759 { 3760 int next, size; 3761 struct mbuf **items; 3762 3763 size = r->size; 3764 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3765 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3766 3767 prefetch(items[(cidx + offset) & (size-1)]); 3768 if (remaining > 1) { 3769 prefetch2cachelines(&items[next]); 3770 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3771 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3772 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3773 } 3774 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3775 } 3776 3777 static void 3778 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3779 { 3780 3781 ifmp_ring_check_drainage(txq->ift_br, budget); 3782 } 3783 3784 static uint32_t 3785 iflib_txq_can_drain(struct ifmp_ring *r) 3786 { 3787 iflib_txq_t txq = r->cookie; 3788 if_ctx_t ctx = txq->ift_ctx; 3789 3790 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3791 return (1); 3792 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3793 BUS_DMASYNC_POSTREAD); 3794 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3795 false)); 3796 } 3797 3798 static uint32_t 3799 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3800 { 3801 iflib_txq_t txq = r->cookie; 3802 if_ctx_t ctx = txq->ift_ctx; 3803 if_t ifp = ctx->ifc_ifp; 3804 struct mbuf *m, **mp; 3805 int avail, bytes_sent, skipped, count, err, i; 3806 int mcast_sent, pkt_sent, reclaimed; 3807 bool do_prefetch, rang, ring; 3808 3809 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3810 !LINK_ACTIVE(ctx))) { 3811 DBG_COUNTER_INC(txq_drain_notready); 3812 return (0); 3813 } 3814 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3815 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending); 3816 avail = IDXDIFF(pidx, cidx, r->size); 3817 3818 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3819 /* 3820 * The driver is unloading so we need to free all pending packets. 3821 */ 3822 DBG_COUNTER_INC(txq_drain_flushing); 3823 for (i = 0; i < avail; i++) { 3824 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3825 m_freem(r->items[(cidx + i) & (r->size-1)]); 3826 r->items[(cidx + i) & (r->size-1)] = NULL; 3827 } 3828 return (avail); 3829 } 3830 3831 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3832 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3833 CALLOUT_LOCK(txq); 3834 callout_stop(&txq->ift_timer); 3835 CALLOUT_UNLOCK(txq); 3836 DBG_COUNTER_INC(txq_drain_oactive); 3837 return (0); 3838 } 3839 3840 /* 3841 * If we've reclaimed any packets this queue cannot be hung. 3842 */ 3843 if (reclaimed) 3844 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3845 skipped = mcast_sent = bytes_sent = pkt_sent = 0; 3846 count = MIN(avail, TX_BATCH_SIZE); 3847 #ifdef INVARIANTS 3848 if (iflib_verbose_debug) 3849 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3850 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3851 #endif 3852 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3853 err = 0; 3854 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx) + 2; i++) { 3855 int rem = do_prefetch ? count - i : 0; 3856 3857 mp = _ring_peek_one(r, cidx, i, rem); 3858 MPASS(mp != NULL && *mp != NULL); 3859 3860 /* 3861 * Completion interrupts will use the address of the txq 3862 * as a sentinel to enqueue _something_ in order to acquire 3863 * the lock on the mp_ring (there's no direct lock call). 3864 * We obviously whave to check for these sentinel cases 3865 * and skip them. 3866 */ 3867 if (__predict_false(*mp == (struct mbuf *)txq)) { 3868 skipped++; 3869 continue; 3870 } 3871 err = iflib_encap(txq, mp); 3872 if (__predict_false(err)) { 3873 /* no room - bail out */ 3874 if (err == ENOBUFS) 3875 break; 3876 skipped++; 3877 /* we can't send this packet - skip it */ 3878 continue; 3879 } 3880 pkt_sent++; 3881 m = *mp; 3882 DBG_COUNTER_INC(tx_sent); 3883 bytes_sent += m->m_pkthdr.len; 3884 mcast_sent += !!(m->m_flags & M_MCAST); 3885 3886 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3887 break; 3888 ETHER_BPF_MTAP(ifp, m); 3889 rang = iflib_txd_db_check(txq, false); 3890 } 3891 3892 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3893 ring = rang ? false : (iflib_min_tx_latency | err); 3894 iflib_txd_db_check(txq, ring); 3895 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3896 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3897 if (mcast_sent) 3898 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3899 #ifdef INVARIANTS 3900 if (iflib_verbose_debug) 3901 printf("consumed=%d\n", skipped + pkt_sent); 3902 #endif 3903 return (skipped + pkt_sent); 3904 } 3905 3906 static uint32_t 3907 iflib_txq_drain_always(struct ifmp_ring *r) 3908 { 3909 return (1); 3910 } 3911 3912 static uint32_t 3913 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3914 { 3915 int i, avail; 3916 struct mbuf **mp; 3917 iflib_txq_t txq; 3918 3919 txq = r->cookie; 3920 3921 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3922 CALLOUT_LOCK(txq); 3923 callout_stop(&txq->ift_timer); 3924 CALLOUT_UNLOCK(txq); 3925 3926 avail = IDXDIFF(pidx, cidx, r->size); 3927 for (i = 0; i < avail; i++) { 3928 mp = _ring_peek_one(r, cidx, i, avail - i); 3929 if (__predict_false(*mp == (struct mbuf *)txq)) 3930 continue; 3931 m_freem(*mp); 3932 DBG_COUNTER_INC(tx_frees); 3933 } 3934 MPASS(ifmp_ring_is_stalled(r) == 0); 3935 return (avail); 3936 } 3937 3938 static void 3939 iflib_ifmp_purge(iflib_txq_t txq) 3940 { 3941 struct ifmp_ring *r; 3942 3943 r = txq->ift_br; 3944 r->drain = iflib_txq_drain_free; 3945 r->can_drain = iflib_txq_drain_always; 3946 3947 ifmp_ring_check_drainage(r, r->size); 3948 3949 r->drain = iflib_txq_drain; 3950 r->can_drain = iflib_txq_can_drain; 3951 } 3952 3953 static void 3954 _task_fn_tx(void *context) 3955 { 3956 iflib_txq_t txq = context; 3957 if_ctx_t ctx = txq->ift_ctx; 3958 if_t ifp = ctx->ifc_ifp; 3959 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3960 3961 #ifdef IFLIB_DIAGNOSTICS 3962 txq->ift_cpu_exec_count[curcpu]++; 3963 #endif 3964 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 3965 return; 3966 #ifdef DEV_NETMAP 3967 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 3968 netmap_tx_irq(ifp, txq->ift_id)) 3969 goto skip_ifmp; 3970 #endif 3971 #ifdef ALTQ 3972 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3973 iflib_altq_if_start(ifp); 3974 #endif 3975 if (txq->ift_db_pending) 3976 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3977 else if (!abdicate) 3978 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3979 /* 3980 * When abdicating, we always need to check drainage, not just when we don't enqueue 3981 */ 3982 if (abdicate) 3983 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3984 #ifdef DEV_NETMAP 3985 skip_ifmp: 3986 #endif 3987 if (ctx->ifc_flags & IFC_LEGACY) 3988 IFDI_INTR_ENABLE(ctx); 3989 else 3990 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3991 } 3992 3993 static void 3994 _task_fn_rx(void *context) 3995 { 3996 iflib_rxq_t rxq = context; 3997 if_ctx_t ctx = rxq->ifr_ctx; 3998 uint8_t more; 3999 uint16_t budget; 4000 #ifdef DEV_NETMAP 4001 u_int work = 0; 4002 int nmirq; 4003 #endif 4004 4005 #ifdef IFLIB_DIAGNOSTICS 4006 rxq->ifr_cpu_exec_count[curcpu]++; 4007 #endif 4008 DBG_COUNTER_INC(task_fn_rxs); 4009 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4010 return; 4011 #ifdef DEV_NETMAP 4012 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 4013 if (nmirq != NM_IRQ_PASS) { 4014 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 4015 goto skip_rxeof; 4016 } 4017 #endif 4018 budget = ctx->ifc_sysctl_rx_budget; 4019 if (budget == 0) 4020 budget = 16; /* XXX */ 4021 more = iflib_rxeof(rxq, budget); 4022 #ifdef DEV_NETMAP 4023 skip_rxeof: 4024 #endif 4025 if ((more & IFLIB_RXEOF_MORE) == 0) { 4026 if (ctx->ifc_flags & IFC_LEGACY) 4027 IFDI_INTR_ENABLE(ctx); 4028 else 4029 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 4030 DBG_COUNTER_INC(rx_intr_enables); 4031 } 4032 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4033 return; 4034 4035 if (more & IFLIB_RXEOF_MORE) 4036 GROUPTASK_ENQUEUE(&rxq->ifr_task); 4037 else if (more & IFLIB_RXEOF_EMPTY) 4038 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 4039 } 4040 4041 static void 4042 _task_fn_admin(void *context) 4043 { 4044 if_ctx_t ctx = context; 4045 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 4046 iflib_txq_t txq; 4047 int i; 4048 bool oactive, running, do_reset, do_watchdog, in_detach; 4049 4050 STATE_LOCK(ctx); 4051 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 4052 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 4053 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 4054 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 4055 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 4056 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 4057 STATE_UNLOCK(ctx); 4058 4059 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4060 return; 4061 if (in_detach) 4062 return; 4063 4064 CTX_LOCK(ctx); 4065 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4066 CALLOUT_LOCK(txq); 4067 callout_stop(&txq->ift_timer); 4068 CALLOUT_UNLOCK(txq); 4069 } 4070 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ) 4071 IFDI_ADMIN_COMPLETION_HANDLE(ctx); 4072 if (do_watchdog) { 4073 ctx->ifc_watchdog_events++; 4074 IFDI_WATCHDOG_RESET(ctx); 4075 } 4076 IFDI_UPDATE_ADMIN_STATUS(ctx); 4077 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4078 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 4079 txq->ift_timer.c_cpu); 4080 } 4081 IFDI_LINK_INTR_ENABLE(ctx); 4082 if (do_reset) 4083 iflib_if_init_locked(ctx); 4084 CTX_UNLOCK(ctx); 4085 4086 if (LINK_ACTIVE(ctx) == 0) 4087 return; 4088 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 4089 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4090 } 4091 4092 static void 4093 _task_fn_iov(void *context) 4094 { 4095 if_ctx_t ctx = context; 4096 4097 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 4098 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4099 return; 4100 4101 CTX_LOCK(ctx); 4102 IFDI_VFLR_HANDLE(ctx); 4103 CTX_UNLOCK(ctx); 4104 } 4105 4106 static int 4107 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4108 { 4109 int err; 4110 if_int_delay_info_t info; 4111 if_ctx_t ctx; 4112 4113 info = (if_int_delay_info_t)arg1; 4114 ctx = info->iidi_ctx; 4115 info->iidi_req = req; 4116 info->iidi_oidp = oidp; 4117 CTX_LOCK(ctx); 4118 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 4119 CTX_UNLOCK(ctx); 4120 return (err); 4121 } 4122 4123 /********************************************************************* 4124 * 4125 * IFNET FUNCTIONS 4126 * 4127 **********************************************************************/ 4128 4129 static void 4130 iflib_if_init_locked(if_ctx_t ctx) 4131 { 4132 iflib_stop(ctx); 4133 iflib_init_locked(ctx); 4134 } 4135 4136 static void 4137 iflib_if_init(void *arg) 4138 { 4139 if_ctx_t ctx = arg; 4140 4141 CTX_LOCK(ctx); 4142 iflib_if_init_locked(ctx); 4143 CTX_UNLOCK(ctx); 4144 } 4145 4146 static int 4147 iflib_if_transmit(if_t ifp, struct mbuf *m) 4148 { 4149 if_ctx_t ctx = if_getsoftc(ifp); 4150 4151 iflib_txq_t txq; 4152 int err, qidx; 4153 int abdicate = ctx->ifc_sysctl_tx_abdicate; 4154 4155 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 4156 DBG_COUNTER_INC(tx_frees); 4157 m_freem(m); 4158 return (ENETDOWN); 4159 } 4160 4161 MPASS(m->m_nextpkt == NULL); 4162 /* ALTQ-enabled interfaces always use queue 0. */ 4163 qidx = 0; 4164 /* Use driver-supplied queue selection method if it exists */ 4165 if (ctx->isc_txq_select) 4166 qidx = ctx->isc_txq_select(ctx->ifc_softc, m); 4167 /* If not, use iflib's standard method */ 4168 else if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 4169 qidx = QIDX(ctx, m); 4170 4171 /* Set TX queue */ 4172 txq = &ctx->ifc_txqs[qidx]; 4173 4174 #ifdef DRIVER_BACKPRESSURE 4175 if (txq->ift_closed) { 4176 while (m != NULL) { 4177 next = m->m_nextpkt; 4178 m->m_nextpkt = NULL; 4179 m_freem(m); 4180 DBG_COUNTER_INC(tx_frees); 4181 m = next; 4182 } 4183 return (ENOBUFS); 4184 } 4185 #endif 4186 #ifdef notyet 4187 qidx = count = 0; 4188 mp = marr; 4189 next = m; 4190 do { 4191 count++; 4192 next = next->m_nextpkt; 4193 } while (next != NULL); 4194 4195 if (count > nitems(marr)) 4196 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4197 /* XXX check nextpkt */ 4198 m_freem(m); 4199 /* XXX simplify for now */ 4200 DBG_COUNTER_INC(tx_frees); 4201 return (ENOBUFS); 4202 } 4203 for (next = m, i = 0; next != NULL; i++) { 4204 mp[i] = next; 4205 next = next->m_nextpkt; 4206 mp[i]->m_nextpkt = NULL; 4207 } 4208 #endif 4209 DBG_COUNTER_INC(tx_seen); 4210 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4211 4212 if (abdicate) 4213 GROUPTASK_ENQUEUE(&txq->ift_task); 4214 if (err) { 4215 if (!abdicate) 4216 GROUPTASK_ENQUEUE(&txq->ift_task); 4217 /* support forthcoming later */ 4218 #ifdef DRIVER_BACKPRESSURE 4219 txq->ift_closed = TRUE; 4220 #endif 4221 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4222 m_freem(m); 4223 DBG_COUNTER_INC(tx_frees); 4224 } 4225 4226 return (err); 4227 } 4228 4229 #ifdef ALTQ 4230 /* 4231 * The overall approach to integrating iflib with ALTQ is to continue to use 4232 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4233 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4234 * is redundant/unnecessary, but doing so minimizes the amount of 4235 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4236 * redundantly queueing to an intermediate mp_ring is swamped by the 4237 * performance limitations inherent in using ALTQ. 4238 * 4239 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4240 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4241 * given interface. If ALTQ is enabled for an interface, then all 4242 * transmitted packets for that interface will be submitted to the ALTQ 4243 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4244 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4245 * update stats that the iflib machinery handles, and which is sensitve to 4246 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4247 * will be installed as the start routine for use by ALTQ facilities that 4248 * need to trigger queue drains on a scheduled basis. 4249 * 4250 */ 4251 static void 4252 iflib_altq_if_start(if_t ifp) 4253 { 4254 struct ifaltq *ifq = &ifp->if_snd; 4255 struct mbuf *m; 4256 4257 IFQ_LOCK(ifq); 4258 IFQ_DEQUEUE_NOLOCK(ifq, m); 4259 while (m != NULL) { 4260 iflib_if_transmit(ifp, m); 4261 IFQ_DEQUEUE_NOLOCK(ifq, m); 4262 } 4263 IFQ_UNLOCK(ifq); 4264 } 4265 4266 static int 4267 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4268 { 4269 int err; 4270 4271 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4272 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4273 if (err == 0) 4274 iflib_altq_if_start(ifp); 4275 } else 4276 err = iflib_if_transmit(ifp, m); 4277 4278 return (err); 4279 } 4280 #endif /* ALTQ */ 4281 4282 static void 4283 iflib_if_qflush(if_t ifp) 4284 { 4285 if_ctx_t ctx = if_getsoftc(ifp); 4286 iflib_txq_t txq = ctx->ifc_txqs; 4287 int i; 4288 4289 STATE_LOCK(ctx); 4290 ctx->ifc_flags |= IFC_QFLUSH; 4291 STATE_UNLOCK(ctx); 4292 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4293 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4294 iflib_txq_check_drain(txq, 0); 4295 STATE_LOCK(ctx); 4296 ctx->ifc_flags &= ~IFC_QFLUSH; 4297 STATE_UNLOCK(ctx); 4298 4299 /* 4300 * When ALTQ is enabled, this will also take care of purging the 4301 * ALTQ queue(s). 4302 */ 4303 if_qflush(ifp); 4304 } 4305 4306 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4307 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4308 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4309 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG) 4310 4311 static int 4312 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4313 { 4314 if_ctx_t ctx = if_getsoftc(ifp); 4315 struct ifreq *ifr = (struct ifreq *)data; 4316 #if defined(INET) || defined(INET6) 4317 struct ifaddr *ifa = (struct ifaddr *)data; 4318 #endif 4319 bool avoid_reset = false; 4320 int err = 0, reinit = 0, bits; 4321 4322 switch (command) { 4323 case SIOCSIFADDR: 4324 #ifdef INET 4325 if (ifa->ifa_addr->sa_family == AF_INET) 4326 avoid_reset = true; 4327 #endif 4328 #ifdef INET6 4329 if (ifa->ifa_addr->sa_family == AF_INET6) 4330 avoid_reset = true; 4331 #endif 4332 /* 4333 ** Calling init results in link renegotiation, 4334 ** so we avoid doing it when possible. 4335 */ 4336 if (avoid_reset) { 4337 if_setflagbits(ifp, IFF_UP,0); 4338 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4339 reinit = 1; 4340 #ifdef INET 4341 if (!(if_getflags(ifp) & IFF_NOARP)) 4342 arp_ifinit(ifp, ifa); 4343 #endif 4344 } else 4345 err = ether_ioctl(ifp, command, data); 4346 break; 4347 case SIOCSIFMTU: 4348 CTX_LOCK(ctx); 4349 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4350 CTX_UNLOCK(ctx); 4351 break; 4352 } 4353 bits = if_getdrvflags(ifp); 4354 /* stop the driver and free any clusters before proceeding */ 4355 iflib_stop(ctx); 4356 4357 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4358 STATE_LOCK(ctx); 4359 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4360 ctx->ifc_flags |= IFC_MULTISEG; 4361 else 4362 ctx->ifc_flags &= ~IFC_MULTISEG; 4363 STATE_UNLOCK(ctx); 4364 err = if_setmtu(ifp, ifr->ifr_mtu); 4365 } 4366 iflib_init_locked(ctx); 4367 STATE_LOCK(ctx); 4368 if_setdrvflags(ifp, bits); 4369 STATE_UNLOCK(ctx); 4370 CTX_UNLOCK(ctx); 4371 break; 4372 case SIOCSIFFLAGS: 4373 CTX_LOCK(ctx); 4374 if (if_getflags(ifp) & IFF_UP) { 4375 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4376 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4377 (IFF_PROMISC | IFF_ALLMULTI)) { 4378 CTX_UNLOCK(ctx); 4379 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4380 CTX_LOCK(ctx); 4381 } 4382 } else 4383 reinit = 1; 4384 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4385 iflib_stop(ctx); 4386 } 4387 ctx->ifc_if_flags = if_getflags(ifp); 4388 CTX_UNLOCK(ctx); 4389 break; 4390 case SIOCADDMULTI: 4391 case SIOCDELMULTI: 4392 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4393 CTX_LOCK(ctx); 4394 IFDI_INTR_DISABLE(ctx); 4395 IFDI_MULTI_SET(ctx); 4396 IFDI_INTR_ENABLE(ctx); 4397 CTX_UNLOCK(ctx); 4398 } 4399 break; 4400 case SIOCSIFMEDIA: 4401 CTX_LOCK(ctx); 4402 IFDI_MEDIA_SET(ctx); 4403 CTX_UNLOCK(ctx); 4404 /* FALLTHROUGH */ 4405 case SIOCGIFMEDIA: 4406 case SIOCGIFXMEDIA: 4407 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4408 break; 4409 case SIOCGI2C: 4410 { 4411 struct ifi2creq i2c; 4412 4413 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4414 if (err != 0) 4415 break; 4416 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4417 err = EINVAL; 4418 break; 4419 } 4420 if (i2c.len > sizeof(i2c.data)) { 4421 err = EINVAL; 4422 break; 4423 } 4424 4425 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4426 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4427 sizeof(i2c)); 4428 break; 4429 } 4430 case SIOCSIFCAP: 4431 { 4432 int mask, setmask, oldmask; 4433 4434 oldmask = if_getcapenable(ifp); 4435 mask = ifr->ifr_reqcap ^ oldmask; 4436 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG; 4437 setmask = 0; 4438 #ifdef TCP_OFFLOAD 4439 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4440 #endif 4441 setmask |= (mask & IFCAP_FLAGS); 4442 setmask |= (mask & IFCAP_WOL); 4443 4444 /* 4445 * If any RX csum has changed, change all the ones that 4446 * are supported by the driver. 4447 */ 4448 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4449 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4450 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4451 } 4452 4453 /* 4454 * want to ensure that traffic has stopped before we change any of the flags 4455 */ 4456 if (setmask) { 4457 CTX_LOCK(ctx); 4458 bits = if_getdrvflags(ifp); 4459 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4460 iflib_stop(ctx); 4461 STATE_LOCK(ctx); 4462 if_togglecapenable(ifp, setmask); 4463 ctx->ifc_softc_ctx.isc_capenable ^= setmask; 4464 STATE_UNLOCK(ctx); 4465 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4466 iflib_init_locked(ctx); 4467 STATE_LOCK(ctx); 4468 if_setdrvflags(ifp, bits); 4469 STATE_UNLOCK(ctx); 4470 CTX_UNLOCK(ctx); 4471 } 4472 if_vlancap(ifp); 4473 break; 4474 } 4475 case SIOCGPRIVATE_0: 4476 case SIOCSDRVSPEC: 4477 case SIOCGDRVSPEC: 4478 CTX_LOCK(ctx); 4479 err = IFDI_PRIV_IOCTL(ctx, command, data); 4480 CTX_UNLOCK(ctx); 4481 break; 4482 default: 4483 err = ether_ioctl(ifp, command, data); 4484 break; 4485 } 4486 if (reinit) 4487 iflib_if_init(ctx); 4488 return (err); 4489 } 4490 4491 static uint64_t 4492 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4493 { 4494 if_ctx_t ctx = if_getsoftc(ifp); 4495 4496 return (IFDI_GET_COUNTER(ctx, cnt)); 4497 } 4498 4499 /********************************************************************* 4500 * 4501 * OTHER FUNCTIONS EXPORTED TO THE STACK 4502 * 4503 **********************************************************************/ 4504 4505 static void 4506 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4507 { 4508 if_ctx_t ctx = if_getsoftc(ifp); 4509 4510 if ((void *)ctx != arg) 4511 return; 4512 4513 if ((vtag == 0) || (vtag > 4095)) 4514 return; 4515 4516 if (iflib_in_detach(ctx)) 4517 return; 4518 4519 CTX_LOCK(ctx); 4520 /* Driver may need all untagged packets to be flushed */ 4521 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4522 iflib_stop(ctx); 4523 IFDI_VLAN_REGISTER(ctx, vtag); 4524 /* Re-init to load the changes, if required */ 4525 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4526 iflib_init_locked(ctx); 4527 CTX_UNLOCK(ctx); 4528 } 4529 4530 static void 4531 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4532 { 4533 if_ctx_t ctx = if_getsoftc(ifp); 4534 4535 if ((void *)ctx != arg) 4536 return; 4537 4538 if ((vtag == 0) || (vtag > 4095)) 4539 return; 4540 4541 CTX_LOCK(ctx); 4542 /* Driver may need all tagged packets to be flushed */ 4543 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4544 iflib_stop(ctx); 4545 IFDI_VLAN_UNREGISTER(ctx, vtag); 4546 /* Re-init to load the changes, if required */ 4547 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4548 iflib_init_locked(ctx); 4549 CTX_UNLOCK(ctx); 4550 } 4551 4552 static void 4553 iflib_led_func(void *arg, int onoff) 4554 { 4555 if_ctx_t ctx = arg; 4556 4557 CTX_LOCK(ctx); 4558 IFDI_LED_FUNC(ctx, onoff); 4559 CTX_UNLOCK(ctx); 4560 } 4561 4562 /********************************************************************* 4563 * 4564 * BUS FUNCTION DEFINITIONS 4565 * 4566 **********************************************************************/ 4567 4568 int 4569 iflib_device_probe(device_t dev) 4570 { 4571 const pci_vendor_info_t *ent; 4572 if_shared_ctx_t sctx; 4573 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4574 uint16_t pci_vendor_id; 4575 4576 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4577 return (ENOTSUP); 4578 4579 pci_vendor_id = pci_get_vendor(dev); 4580 pci_device_id = pci_get_device(dev); 4581 pci_subvendor_id = pci_get_subvendor(dev); 4582 pci_subdevice_id = pci_get_subdevice(dev); 4583 pci_rev_id = pci_get_revid(dev); 4584 if (sctx->isc_parse_devinfo != NULL) 4585 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4586 4587 ent = sctx->isc_vendor_info; 4588 while (ent->pvi_vendor_id != 0) { 4589 if (pci_vendor_id != ent->pvi_vendor_id) { 4590 ent++; 4591 continue; 4592 } 4593 if ((pci_device_id == ent->pvi_device_id) && 4594 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4595 (ent->pvi_subvendor_id == 0)) && 4596 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4597 (ent->pvi_subdevice_id == 0)) && 4598 ((pci_rev_id == ent->pvi_rev_id) || 4599 (ent->pvi_rev_id == 0))) { 4600 device_set_desc_copy(dev, ent->pvi_name); 4601 /* this needs to be changed to zero if the bus probing code 4602 * ever stops re-probing on best match because the sctx 4603 * may have its values over written by register calls 4604 * in subsequent probes 4605 */ 4606 return (BUS_PROBE_DEFAULT); 4607 } 4608 ent++; 4609 } 4610 return (ENXIO); 4611 } 4612 4613 int 4614 iflib_device_probe_vendor(device_t dev) 4615 { 4616 int probe; 4617 4618 probe = iflib_device_probe(dev); 4619 if (probe == BUS_PROBE_DEFAULT) 4620 return (BUS_PROBE_VENDOR); 4621 else 4622 return (probe); 4623 } 4624 4625 static void 4626 iflib_reset_qvalues(if_ctx_t ctx) 4627 { 4628 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4629 if_shared_ctx_t sctx = ctx->ifc_sctx; 4630 device_t dev = ctx->ifc_dev; 4631 int i; 4632 4633 if (ctx->ifc_sysctl_ntxqs != 0) 4634 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4635 if (ctx->ifc_sysctl_nrxqs != 0) 4636 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4637 4638 for (i = 0; i < sctx->isc_ntxqs; i++) { 4639 if (ctx->ifc_sysctl_ntxds[i] != 0) 4640 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4641 else 4642 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4643 } 4644 4645 for (i = 0; i < sctx->isc_nrxqs; i++) { 4646 if (ctx->ifc_sysctl_nrxds[i] != 0) 4647 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4648 else 4649 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4650 } 4651 4652 for (i = 0; i < sctx->isc_nrxqs; i++) { 4653 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4654 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4655 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4656 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4657 } 4658 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4659 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4660 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4661 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4662 } 4663 if (!powerof2(scctx->isc_nrxd[i])) { 4664 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4665 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4666 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4667 } 4668 } 4669 4670 for (i = 0; i < sctx->isc_ntxqs; i++) { 4671 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4672 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4673 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4674 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4675 } 4676 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4677 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4678 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4679 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4680 } 4681 if (!powerof2(scctx->isc_ntxd[i])) { 4682 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4683 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4684 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4685 } 4686 } 4687 } 4688 4689 static void 4690 iflib_add_pfil(if_ctx_t ctx) 4691 { 4692 struct pfil_head *pfil; 4693 struct pfil_head_args pa; 4694 iflib_rxq_t rxq; 4695 int i; 4696 4697 pa.pa_version = PFIL_VERSION; 4698 pa.pa_flags = PFIL_IN; 4699 pa.pa_type = PFIL_TYPE_ETHERNET; 4700 pa.pa_headname = ctx->ifc_ifp->if_xname; 4701 pfil = pfil_head_register(&pa); 4702 4703 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4704 rxq->pfil = pfil; 4705 } 4706 } 4707 4708 static void 4709 iflib_rem_pfil(if_ctx_t ctx) 4710 { 4711 struct pfil_head *pfil; 4712 iflib_rxq_t rxq; 4713 int i; 4714 4715 rxq = ctx->ifc_rxqs; 4716 pfil = rxq->pfil; 4717 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4718 rxq->pfil = NULL; 4719 } 4720 pfil_head_unregister(pfil); 4721 } 4722 4723 4724 /* 4725 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from 4726 * cpuid and wrapping as necessary. 4727 */ 4728 static unsigned int 4729 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n) 4730 { 4731 unsigned int first_valid; 4732 unsigned int last_valid; 4733 4734 /* cpuid should always be in the valid set */ 4735 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4736 4737 /* valid set should never be empty */ 4738 MPASS(!CPU_EMPTY(&ctx->ifc_cpus)); 4739 4740 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4741 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4742 n = n % CPU_COUNT(&ctx->ifc_cpus); 4743 while (n > 0) { 4744 do { 4745 cpuid++; 4746 if (cpuid > last_valid) 4747 cpuid = first_valid; 4748 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4749 n--; 4750 } 4751 4752 return (cpuid); 4753 } 4754 4755 #if defined(SMP) && defined(SCHED_ULE) 4756 extern struct cpu_group *cpu_top; /* CPU topology */ 4757 4758 static int 4759 find_child_with_core(int cpu, struct cpu_group *grp) 4760 { 4761 int i; 4762 4763 if (grp->cg_children == 0) 4764 return -1; 4765 4766 MPASS(grp->cg_child); 4767 for (i = 0; i < grp->cg_children; i++) { 4768 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 4769 return i; 4770 } 4771 4772 return -1; 4773 } 4774 4775 4776 /* 4777 * Find an L2 neighbor of the given CPU or return -1 if none found. This 4778 * does not distinguish among multiple L2 neighbors if the given CPU has 4779 * more than one (it will always return the same result in that case). 4780 */ 4781 static int 4782 find_l2_neighbor(int cpu) 4783 { 4784 struct cpu_group *grp; 4785 int i; 4786 4787 grp = cpu_top; 4788 if (grp == NULL) 4789 return -1; 4790 4791 /* 4792 * Find the smallest CPU group that contains the given core. 4793 */ 4794 i = 0; 4795 while ((i = find_child_with_core(cpu, grp)) != -1) { 4796 /* 4797 * If the smallest group containing the given CPU has less 4798 * than two members, we conclude the given CPU has no 4799 * L2 neighbor. 4800 */ 4801 if (grp->cg_child[i].cg_count <= 1) 4802 return (-1); 4803 grp = &grp->cg_child[i]; 4804 } 4805 4806 /* Must share L2. */ 4807 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 4808 return -1; 4809 4810 /* 4811 * Select the first member of the set that isn't the reference 4812 * CPU, which at this point is guaranteed to exist. 4813 */ 4814 for (i = 0; i < CPU_SETSIZE; i++) { 4815 if (CPU_ISSET(i, &grp->cg_mask) && i != cpu) 4816 return (i); 4817 } 4818 4819 /* Should never be reached */ 4820 return (-1); 4821 } 4822 4823 #else 4824 static int 4825 find_l2_neighbor(int cpu) 4826 { 4827 4828 return (-1); 4829 } 4830 #endif 4831 4832 /* 4833 * CPU mapping behaviors 4834 * --------------------- 4835 * 'separate txrx' refers to the separate_txrx sysctl 4836 * 'use logical' refers to the use_logical_cores sysctl 4837 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded 4838 * 4839 * separate use INTR 4840 * txrx logical CPUS result 4841 * ---------- --------- ------ ------------------------------------------------ 4842 * - - X RX and TX queues mapped to consecutive physical 4843 * cores with RX/TX pairs on same core and excess 4844 * of either following 4845 * - X X RX and TX queues mapped to consecutive cores 4846 * of any type with RX/TX pairs on same core and 4847 * excess of either following 4848 * X - X RX and TX queues mapped to consecutive physical 4849 * cores; all RX then all TX 4850 * X X X RX queues mapped to consecutive physical cores 4851 * first, then TX queues mapped to L2 neighbor of 4852 * the corresponding RX queue if one exists, 4853 * otherwise to consecutive physical cores 4854 * - n/a - RX and TX queues mapped to consecutive cores of 4855 * any type with RX/TX pairs on same core and excess 4856 * of either following 4857 * X n/a - RX and TX queues mapped to consecutive cores of 4858 * any type; all RX then all TX 4859 */ 4860 static unsigned int 4861 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid, 4862 bool is_tx) 4863 { 4864 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4865 unsigned int core_index; 4866 4867 if (ctx->ifc_sysctl_separate_txrx) { 4868 /* 4869 * When using separate CPUs for TX and RX, the assignment 4870 * will always be of a consecutive CPU out of the set of 4871 * context CPUs, except for the specific case where the 4872 * context CPUs are phsyical cores, the use of logical cores 4873 * has been enabled, the assignment is for TX, the TX qid 4874 * corresponds to an RX qid, and the CPU assigned to the 4875 * corresponding RX queue has an L2 neighbor. 4876 */ 4877 if (ctx->ifc_sysctl_use_logical_cores && 4878 ctx->ifc_cpus_are_physical_cores && 4879 is_tx && qid < scctx->isc_nrxqsets) { 4880 int l2_neighbor; 4881 unsigned int rx_cpuid; 4882 4883 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid); 4884 l2_neighbor = find_l2_neighbor(rx_cpuid); 4885 if (l2_neighbor != -1) { 4886 return (l2_neighbor); 4887 } 4888 /* 4889 * ... else fall through to the normal 4890 * consecutive-after-RX assignment scheme. 4891 * 4892 * Note that we are assuming that all RX queue CPUs 4893 * have an L2 neighbor, or all do not. If a mixed 4894 * scenario is possible, we will have to keep track 4895 * separately of how many queues prior to this one 4896 * were not able to be assigned to an L2 neighbor. 4897 */ 4898 } 4899 if (is_tx) 4900 core_index = scctx->isc_nrxqsets + qid; 4901 else 4902 core_index = qid; 4903 } else { 4904 core_index = qid; 4905 } 4906 4907 return (cpuid_advance(ctx, base_cpuid, core_index)); 4908 } 4909 4910 static uint16_t 4911 get_ctx_core_offset(if_ctx_t ctx) 4912 { 4913 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4914 struct cpu_offset *op; 4915 cpuset_t assigned_cpus; 4916 unsigned int cores_consumed; 4917 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset; 4918 unsigned int first_valid; 4919 unsigned int last_valid; 4920 unsigned int i; 4921 4922 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4923 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4924 4925 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) { 4926 /* 4927 * Align the user-chosen base CPU ID to the next valid CPU 4928 * for this device. If the chosen base CPU ID is smaller 4929 * than the first valid CPU or larger than the last valid 4930 * CPU, we assume the user does not know what the valid 4931 * range is for this device and is thinking in terms of a 4932 * zero-based reference frame, and so we shift the given 4933 * value into the valid range (and wrap accordingly) so the 4934 * intent is translated to the proper frame of reference. 4935 * If the base CPU ID is within the valid first/last, but 4936 * does not correspond to a valid CPU, it is advanced to the 4937 * next valid CPU (wrapping if necessary). 4938 */ 4939 if (base_cpuid < first_valid || base_cpuid > last_valid) { 4940 /* shift from zero-based to first_valid-based */ 4941 base_cpuid += first_valid; 4942 /* wrap to range [first_valid, last_valid] */ 4943 base_cpuid = (base_cpuid - first_valid) % 4944 (last_valid - first_valid + 1); 4945 } 4946 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) { 4947 /* 4948 * base_cpuid is in [first_valid, last_valid], but 4949 * not a member of the valid set. In this case, 4950 * there will always be a member of the valid set 4951 * with a CPU ID that is greater than base_cpuid, 4952 * and we simply advance to it. 4953 */ 4954 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) 4955 base_cpuid++; 4956 } 4957 return (base_cpuid); 4958 } 4959 4960 /* 4961 * Determine how many cores will be consumed by performing the CPU 4962 * assignments and counting how many of the assigned CPUs correspond 4963 * to CPUs in the set of context CPUs. This is done using the CPU 4964 * ID first_valid as the base CPU ID, as the base CPU must be within 4965 * the set of context CPUs. 4966 * 4967 * Note not all assigned CPUs will be in the set of context CPUs 4968 * when separate CPUs are being allocated to TX and RX queues, 4969 * assignment to logical cores has been enabled, the set of context 4970 * CPUs contains only physical CPUs, and TX queues are mapped to L2 4971 * neighbors of CPUs that RX queues have been mapped to - in this 4972 * case we do only want to count how many CPUs in the set of context 4973 * CPUs have been consumed, as that determines the next CPU in that 4974 * set to start allocating at for the next device for which 4975 * core_offset is not set. 4976 */ 4977 CPU_ZERO(&assigned_cpus); 4978 for (i = 0; i < scctx->isc_ntxqsets; i++) 4979 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true), 4980 &assigned_cpus); 4981 for (i = 0; i < scctx->isc_nrxqsets; i++) 4982 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false), 4983 &assigned_cpus); 4984 CPU_AND(&assigned_cpus, &assigned_cpus, &ctx->ifc_cpus); 4985 cores_consumed = CPU_COUNT(&assigned_cpus); 4986 4987 mtx_lock(&cpu_offset_mtx); 4988 SLIST_FOREACH(op, &cpu_offsets, entries) { 4989 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4990 base_cpuid = op->next_cpuid; 4991 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid, 4992 cores_consumed); 4993 MPASS(op->refcount < UINT_MAX); 4994 op->refcount++; 4995 break; 4996 } 4997 } 4998 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) { 4999 base_cpuid = first_valid; 5000 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 5001 M_NOWAIT | M_ZERO); 5002 if (op == NULL) { 5003 device_printf(ctx->ifc_dev, 5004 "allocation for cpu offset failed.\n"); 5005 } else { 5006 op->next_cpuid = cpuid_advance(ctx, base_cpuid, 5007 cores_consumed); 5008 op->refcount = 1; 5009 CPU_COPY(&ctx->ifc_cpus, &op->set); 5010 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 5011 } 5012 } 5013 mtx_unlock(&cpu_offset_mtx); 5014 5015 return (base_cpuid); 5016 } 5017 5018 static void 5019 unref_ctx_core_offset(if_ctx_t ctx) 5020 { 5021 struct cpu_offset *op, *top; 5022 5023 mtx_lock(&cpu_offset_mtx); 5024 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 5025 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5026 MPASS(op->refcount > 0); 5027 op->refcount--; 5028 if (op->refcount == 0) { 5029 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 5030 free(op, M_IFLIB); 5031 } 5032 break; 5033 } 5034 } 5035 mtx_unlock(&cpu_offset_mtx); 5036 } 5037 5038 int 5039 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 5040 { 5041 if_ctx_t ctx; 5042 if_t ifp; 5043 if_softc_ctx_t scctx; 5044 kobjop_desc_t kobj_desc; 5045 kobj_method_t *kobj_method; 5046 int err, msix, rid; 5047 int num_txd, num_rxd; 5048 5049 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 5050 5051 if (sc == NULL) { 5052 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 5053 device_set_softc(dev, ctx); 5054 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5055 } 5056 5057 ctx->ifc_sctx = sctx; 5058 ctx->ifc_dev = dev; 5059 ctx->ifc_softc = sc; 5060 5061 if ((err = iflib_register(ctx)) != 0) { 5062 device_printf(dev, "iflib_register failed %d\n", err); 5063 goto fail_ctx_free; 5064 } 5065 iflib_add_device_sysctl_pre(ctx); 5066 5067 scctx = &ctx->ifc_softc_ctx; 5068 ifp = ctx->ifc_ifp; 5069 5070 iflib_reset_qvalues(ctx); 5071 IFNET_WLOCK(); 5072 CTX_LOCK(ctx); 5073 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5074 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5075 goto fail_unlock; 5076 } 5077 _iflib_pre_assert(scctx); 5078 ctx->ifc_txrx = *scctx->isc_txrx; 5079 5080 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR)); 5081 5082 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 5083 ctx->ifc_mediap = scctx->isc_media; 5084 5085 #ifdef INVARIANTS 5086 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5087 MPASS(scctx->isc_tx_csum_flags); 5088 #endif 5089 5090 if_setcapabilities(ifp, 5091 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG); 5092 if_setcapenable(ifp, 5093 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG); 5094 5095 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5096 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5097 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5098 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5099 5100 num_txd = iflib_num_tx_descs(ctx); 5101 num_rxd = iflib_num_rx_descs(ctx); 5102 5103 /* XXX change for per-queue sizes */ 5104 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5105 num_txd, num_rxd); 5106 5107 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5108 scctx->isc_tx_nsegments = max(1, num_txd / 5109 MAX_SINGLE_PACKET_FRACTION); 5110 if (scctx->isc_tx_tso_segments_max > num_txd / 5111 MAX_SINGLE_PACKET_FRACTION) 5112 scctx->isc_tx_tso_segments_max = max(1, 5113 num_txd / MAX_SINGLE_PACKET_FRACTION); 5114 5115 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5116 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5117 /* 5118 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5119 * but some MACs do. 5120 */ 5121 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5122 IP_MAXPACKET)); 5123 /* 5124 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5125 * into account. In the worst case, each of these calls will 5126 * add another mbuf and, thus, the requirement for another DMA 5127 * segment. So for best performance, it doesn't make sense to 5128 * advertize a maximum of TSO segments that typically will 5129 * require defragmentation in iflib_encap(). 5130 */ 5131 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5132 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5133 } 5134 if (scctx->isc_rss_table_size == 0) 5135 scctx->isc_rss_table_size = 64; 5136 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5137 5138 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5139 /* XXX format name */ 5140 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5141 NULL, NULL, "admin"); 5142 5143 /* Set up cpu set. If it fails, use the set of all CPUs. */ 5144 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 5145 device_printf(dev, "Unable to fetch CPU list\n"); 5146 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 5147 ctx->ifc_cpus_are_physical_cores = false; 5148 } else 5149 ctx->ifc_cpus_are_physical_cores = true; 5150 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 5151 5152 /* 5153 ** Now set up MSI or MSI-X, should return us the number of supported 5154 ** vectors (will be 1 for a legacy interrupt and MSI). 5155 */ 5156 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 5157 msix = scctx->isc_vectors; 5158 } else if (scctx->isc_msix_bar != 0) 5159 /* 5160 * The simple fact that isc_msix_bar is not 0 does not mean we 5161 * we have a good value there that is known to work. 5162 */ 5163 msix = iflib_msix_init(ctx); 5164 else { 5165 scctx->isc_vectors = 1; 5166 scctx->isc_ntxqsets = 1; 5167 scctx->isc_nrxqsets = 1; 5168 scctx->isc_intr = IFLIB_INTR_LEGACY; 5169 msix = 0; 5170 } 5171 /* Get memory for the station queues */ 5172 if ((err = iflib_queues_alloc(ctx))) { 5173 device_printf(dev, "Unable to allocate queue memory\n"); 5174 goto fail_intr_free; 5175 } 5176 5177 if ((err = iflib_qset_structures_setup(ctx))) 5178 goto fail_queues; 5179 5180 /* 5181 * Now that we know how many queues there are, get the core offset. 5182 */ 5183 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 5184 5185 if (msix > 1) { 5186 /* 5187 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 5188 * aren't the default NULL implementation. 5189 */ 5190 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 5191 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5192 kobj_desc); 5193 if (kobj_method == &kobj_desc->deflt) { 5194 device_printf(dev, 5195 "MSI-X requires ifdi_rx_queue_intr_enable method"); 5196 err = EOPNOTSUPP; 5197 goto fail_queues; 5198 } 5199 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 5200 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5201 kobj_desc); 5202 if (kobj_method == &kobj_desc->deflt) { 5203 device_printf(dev, 5204 "MSI-X requires ifdi_tx_queue_intr_enable method"); 5205 err = EOPNOTSUPP; 5206 goto fail_queues; 5207 } 5208 5209 /* 5210 * Assign the MSI-X vectors. 5211 * Note that the default NULL ifdi_msix_intr_assign method will 5212 * fail here, too. 5213 */ 5214 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 5215 if (err != 0) { 5216 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 5217 err); 5218 goto fail_queues; 5219 } 5220 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 5221 rid = 0; 5222 if (scctx->isc_intr == IFLIB_INTR_MSI) { 5223 MPASS(msix == 1); 5224 rid = 1; 5225 } 5226 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 5227 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 5228 goto fail_queues; 5229 } 5230 } else { 5231 device_printf(dev, 5232 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 5233 err = ENODEV; 5234 goto fail_queues; 5235 } 5236 5237 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5238 5239 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5240 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5241 goto fail_detach; 5242 } 5243 5244 /* 5245 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5246 * This must appear after the call to ether_ifattach() because 5247 * ether_ifattach() sets if_hdrlen to the default value. 5248 */ 5249 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5250 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5251 5252 if ((err = iflib_netmap_attach(ctx))) { 5253 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 5254 goto fail_detach; 5255 } 5256 *ctxp = ctx; 5257 5258 DEBUGNET_SET(ctx->ifc_ifp, iflib); 5259 5260 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5261 iflib_add_device_sysctl_post(ctx); 5262 iflib_add_pfil(ctx); 5263 ctx->ifc_flags |= IFC_INIT_DONE; 5264 CTX_UNLOCK(ctx); 5265 IFNET_WUNLOCK(); 5266 5267 return (0); 5268 5269 fail_detach: 5270 ether_ifdetach(ctx->ifc_ifp); 5271 fail_queues: 5272 iflib_tqg_detach(ctx); 5273 iflib_tx_structures_free(ctx); 5274 iflib_rx_structures_free(ctx); 5275 IFDI_DETACH(ctx); 5276 IFDI_QUEUES_FREE(ctx); 5277 fail_intr_free: 5278 iflib_free_intr_mem(ctx); 5279 fail_unlock: 5280 CTX_UNLOCK(ctx); 5281 IFNET_WUNLOCK(); 5282 iflib_deregister(ctx); 5283 fail_ctx_free: 5284 device_set_softc(ctx->ifc_dev, NULL); 5285 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5286 free(ctx->ifc_softc, M_IFLIB); 5287 free(ctx, M_IFLIB); 5288 return (err); 5289 } 5290 5291 int 5292 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 5293 struct iflib_cloneattach_ctx *clctx) 5294 { 5295 int num_txd, num_rxd; 5296 int err; 5297 if_ctx_t ctx; 5298 if_t ifp; 5299 if_softc_ctx_t scctx; 5300 int i; 5301 void *sc; 5302 5303 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 5304 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 5305 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5306 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 5307 ctx->ifc_flags |= IFC_PSEUDO; 5308 5309 ctx->ifc_sctx = sctx; 5310 ctx->ifc_softc = sc; 5311 ctx->ifc_dev = dev; 5312 5313 if ((err = iflib_register(ctx)) != 0) { 5314 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 5315 goto fail_ctx_free; 5316 } 5317 iflib_add_device_sysctl_pre(ctx); 5318 5319 scctx = &ctx->ifc_softc_ctx; 5320 ifp = ctx->ifc_ifp; 5321 5322 iflib_reset_qvalues(ctx); 5323 CTX_LOCK(ctx); 5324 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5325 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5326 goto fail_unlock; 5327 } 5328 if (sctx->isc_flags & IFLIB_GEN_MAC) 5329 ether_gen_addr(ifp, &ctx->ifc_mac); 5330 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 5331 clctx->cc_params)) != 0) { 5332 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 5333 goto fail_unlock; 5334 } 5335 #ifdef INVARIANTS 5336 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5337 MPASS(scctx->isc_tx_csum_flags); 5338 #endif 5339 5340 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 5341 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 5342 5343 ifp->if_flags |= IFF_NOGROUP; 5344 if (sctx->isc_flags & IFLIB_PSEUDO) { 5345 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 5346 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 5347 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) { 5348 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5349 } else { 5350 if_attach(ctx->ifc_ifp); 5351 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t)); 5352 } 5353 5354 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5355 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5356 goto fail_detach; 5357 } 5358 *ctxp = ctx; 5359 5360 /* 5361 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5362 * This must appear after the call to ether_ifattach() because 5363 * ether_ifattach() sets if_hdrlen to the default value. 5364 */ 5365 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5366 if_setifheaderlen(ifp, 5367 sizeof(struct ether_vlan_header)); 5368 5369 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5370 iflib_add_device_sysctl_post(ctx); 5371 ctx->ifc_flags |= IFC_INIT_DONE; 5372 CTX_UNLOCK(ctx); 5373 return (0); 5374 } 5375 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 5376 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 5377 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 5378 5379 _iflib_pre_assert(scctx); 5380 ctx->ifc_txrx = *scctx->isc_txrx; 5381 5382 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5383 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5384 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5385 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5386 5387 num_txd = iflib_num_tx_descs(ctx); 5388 num_rxd = iflib_num_rx_descs(ctx); 5389 5390 /* XXX change for per-queue sizes */ 5391 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5392 num_txd, num_rxd); 5393 5394 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5395 scctx->isc_tx_nsegments = max(1, num_txd / 5396 MAX_SINGLE_PACKET_FRACTION); 5397 if (scctx->isc_tx_tso_segments_max > num_txd / 5398 MAX_SINGLE_PACKET_FRACTION) 5399 scctx->isc_tx_tso_segments_max = max(1, 5400 num_txd / MAX_SINGLE_PACKET_FRACTION); 5401 5402 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5403 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5404 /* 5405 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5406 * but some MACs do. 5407 */ 5408 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5409 IP_MAXPACKET)); 5410 /* 5411 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5412 * into account. In the worst case, each of these calls will 5413 * add another mbuf and, thus, the requirement for another DMA 5414 * segment. So for best performance, it doesn't make sense to 5415 * advertize a maximum of TSO segments that typically will 5416 * require defragmentation in iflib_encap(). 5417 */ 5418 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5419 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5420 } 5421 if (scctx->isc_rss_table_size == 0) 5422 scctx->isc_rss_table_size = 64; 5423 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5424 5425 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5426 /* XXX format name */ 5427 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5428 NULL, NULL, "admin"); 5429 5430 /* XXX --- can support > 1 -- but keep it simple for now */ 5431 scctx->isc_intr = IFLIB_INTR_LEGACY; 5432 5433 /* Get memory for the station queues */ 5434 if ((err = iflib_queues_alloc(ctx))) { 5435 device_printf(dev, "Unable to allocate queue memory\n"); 5436 goto fail_iflib_detach; 5437 } 5438 5439 if ((err = iflib_qset_structures_setup(ctx))) { 5440 device_printf(dev, "qset structure setup failed %d\n", err); 5441 goto fail_queues; 5442 } 5443 5444 /* 5445 * XXX What if anything do we want to do about interrupts? 5446 */ 5447 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5448 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5449 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5450 goto fail_detach; 5451 } 5452 5453 /* 5454 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5455 * This must appear after the call to ether_ifattach() because 5456 * ether_ifattach() sets if_hdrlen to the default value. 5457 */ 5458 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5459 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5460 5461 /* XXX handle more than one queue */ 5462 for (i = 0; i < scctx->isc_nrxqsets; i++) 5463 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 5464 5465 *ctxp = ctx; 5466 5467 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5468 iflib_add_device_sysctl_post(ctx); 5469 ctx->ifc_flags |= IFC_INIT_DONE; 5470 CTX_UNLOCK(ctx); 5471 5472 return (0); 5473 fail_detach: 5474 ether_ifdetach(ctx->ifc_ifp); 5475 fail_queues: 5476 iflib_tqg_detach(ctx); 5477 iflib_tx_structures_free(ctx); 5478 iflib_rx_structures_free(ctx); 5479 fail_iflib_detach: 5480 IFDI_DETACH(ctx); 5481 IFDI_QUEUES_FREE(ctx); 5482 fail_unlock: 5483 CTX_UNLOCK(ctx); 5484 iflib_deregister(ctx); 5485 fail_ctx_free: 5486 free(ctx->ifc_softc, M_IFLIB); 5487 free(ctx, M_IFLIB); 5488 return (err); 5489 } 5490 5491 int 5492 iflib_pseudo_deregister(if_ctx_t ctx) 5493 { 5494 if_t ifp = ctx->ifc_ifp; 5495 if_shared_ctx_t sctx = ctx->ifc_sctx; 5496 5497 /* Unregister VLAN event handlers early */ 5498 iflib_unregister_vlan_handlers(ctx); 5499 5500 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5501 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) { 5502 bpfdetach(ifp); 5503 if_detach(ifp); 5504 } else { 5505 ether_ifdetach(ifp); 5506 } 5507 5508 iflib_tqg_detach(ctx); 5509 iflib_tx_structures_free(ctx); 5510 iflib_rx_structures_free(ctx); 5511 IFDI_DETACH(ctx); 5512 IFDI_QUEUES_FREE(ctx); 5513 5514 iflib_deregister(ctx); 5515 5516 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5517 free(ctx->ifc_softc, M_IFLIB); 5518 free(ctx, M_IFLIB); 5519 return (0); 5520 } 5521 5522 int 5523 iflib_device_attach(device_t dev) 5524 { 5525 if_ctx_t ctx; 5526 if_shared_ctx_t sctx; 5527 5528 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5529 return (ENOTSUP); 5530 5531 pci_enable_busmaster(dev); 5532 5533 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5534 } 5535 5536 int 5537 iflib_device_deregister(if_ctx_t ctx) 5538 { 5539 if_t ifp = ctx->ifc_ifp; 5540 device_t dev = ctx->ifc_dev; 5541 5542 /* Make sure VLANS are not using driver */ 5543 if (if_vlantrunkinuse(ifp)) { 5544 device_printf(dev, "Vlan in use, detach first\n"); 5545 return (EBUSY); 5546 } 5547 #ifdef PCI_IOV 5548 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5549 device_printf(dev, "SR-IOV in use; detach first.\n"); 5550 return (EBUSY); 5551 } 5552 #endif 5553 5554 STATE_LOCK(ctx); 5555 ctx->ifc_flags |= IFC_IN_DETACH; 5556 STATE_UNLOCK(ctx); 5557 5558 /* Unregister VLAN handlers before calling iflib_stop() */ 5559 iflib_unregister_vlan_handlers(ctx); 5560 5561 iflib_netmap_detach(ifp); 5562 ether_ifdetach(ifp); 5563 5564 CTX_LOCK(ctx); 5565 iflib_stop(ctx); 5566 CTX_UNLOCK(ctx); 5567 5568 iflib_rem_pfil(ctx); 5569 if (ctx->ifc_led_dev != NULL) 5570 led_destroy(ctx->ifc_led_dev); 5571 5572 iflib_tqg_detach(ctx); 5573 iflib_tx_structures_free(ctx); 5574 iflib_rx_structures_free(ctx); 5575 5576 CTX_LOCK(ctx); 5577 IFDI_DETACH(ctx); 5578 IFDI_QUEUES_FREE(ctx); 5579 CTX_UNLOCK(ctx); 5580 5581 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5582 iflib_free_intr_mem(ctx); 5583 5584 bus_generic_detach(dev); 5585 5586 iflib_deregister(ctx); 5587 5588 device_set_softc(ctx->ifc_dev, NULL); 5589 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5590 free(ctx->ifc_softc, M_IFLIB); 5591 unref_ctx_core_offset(ctx); 5592 free(ctx, M_IFLIB); 5593 return (0); 5594 } 5595 5596 static void 5597 iflib_tqg_detach(if_ctx_t ctx) 5598 { 5599 iflib_txq_t txq; 5600 iflib_rxq_t rxq; 5601 int i; 5602 struct taskqgroup *tqg; 5603 5604 /* XXX drain any dependent tasks */ 5605 tqg = qgroup_if_io_tqg; 5606 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5607 callout_drain(&txq->ift_timer); 5608 #ifdef DEV_NETMAP 5609 callout_drain(&txq->ift_netmap_timer); 5610 #endif /* DEV_NETMAP */ 5611 if (txq->ift_task.gt_uniq != NULL) 5612 taskqgroup_detach(tqg, &txq->ift_task); 5613 } 5614 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5615 if (rxq->ifr_task.gt_uniq != NULL) 5616 taskqgroup_detach(tqg, &rxq->ifr_task); 5617 } 5618 tqg = qgroup_if_config_tqg; 5619 if (ctx->ifc_admin_task.gt_uniq != NULL) 5620 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5621 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5622 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5623 } 5624 5625 static void 5626 iflib_free_intr_mem(if_ctx_t ctx) 5627 { 5628 5629 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5630 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5631 } 5632 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5633 pci_release_msi(ctx->ifc_dev); 5634 } 5635 if (ctx->ifc_msix_mem != NULL) { 5636 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5637 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5638 ctx->ifc_msix_mem = NULL; 5639 } 5640 } 5641 5642 int 5643 iflib_device_detach(device_t dev) 5644 { 5645 if_ctx_t ctx = device_get_softc(dev); 5646 5647 return (iflib_device_deregister(ctx)); 5648 } 5649 5650 int 5651 iflib_device_suspend(device_t dev) 5652 { 5653 if_ctx_t ctx = device_get_softc(dev); 5654 5655 CTX_LOCK(ctx); 5656 IFDI_SUSPEND(ctx); 5657 CTX_UNLOCK(ctx); 5658 5659 return bus_generic_suspend(dev); 5660 } 5661 int 5662 iflib_device_shutdown(device_t dev) 5663 { 5664 if_ctx_t ctx = device_get_softc(dev); 5665 5666 CTX_LOCK(ctx); 5667 IFDI_SHUTDOWN(ctx); 5668 CTX_UNLOCK(ctx); 5669 5670 return bus_generic_suspend(dev); 5671 } 5672 5673 int 5674 iflib_device_resume(device_t dev) 5675 { 5676 if_ctx_t ctx = device_get_softc(dev); 5677 iflib_txq_t txq = ctx->ifc_txqs; 5678 5679 CTX_LOCK(ctx); 5680 IFDI_RESUME(ctx); 5681 iflib_if_init_locked(ctx); 5682 CTX_UNLOCK(ctx); 5683 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5684 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5685 5686 return (bus_generic_resume(dev)); 5687 } 5688 5689 int 5690 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5691 { 5692 int error; 5693 if_ctx_t ctx = device_get_softc(dev); 5694 5695 CTX_LOCK(ctx); 5696 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5697 CTX_UNLOCK(ctx); 5698 5699 return (error); 5700 } 5701 5702 void 5703 iflib_device_iov_uninit(device_t dev) 5704 { 5705 if_ctx_t ctx = device_get_softc(dev); 5706 5707 CTX_LOCK(ctx); 5708 IFDI_IOV_UNINIT(ctx); 5709 CTX_UNLOCK(ctx); 5710 } 5711 5712 int 5713 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5714 { 5715 int error; 5716 if_ctx_t ctx = device_get_softc(dev); 5717 5718 CTX_LOCK(ctx); 5719 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5720 CTX_UNLOCK(ctx); 5721 5722 return (error); 5723 } 5724 5725 /********************************************************************* 5726 * 5727 * MODULE FUNCTION DEFINITIONS 5728 * 5729 **********************************************************************/ 5730 5731 /* 5732 * - Start a fast taskqueue thread for each core 5733 * - Start a taskqueue for control operations 5734 */ 5735 static int 5736 iflib_module_init(void) 5737 { 5738 iflib_timer_default = hz / 2; 5739 return (0); 5740 } 5741 5742 static int 5743 iflib_module_event_handler(module_t mod, int what, void *arg) 5744 { 5745 int err; 5746 5747 switch (what) { 5748 case MOD_LOAD: 5749 if ((err = iflib_module_init()) != 0) 5750 return (err); 5751 break; 5752 case MOD_UNLOAD: 5753 return (EBUSY); 5754 default: 5755 return (EOPNOTSUPP); 5756 } 5757 5758 return (0); 5759 } 5760 5761 /********************************************************************* 5762 * 5763 * PUBLIC FUNCTION DEFINITIONS 5764 * ordered as in iflib.h 5765 * 5766 **********************************************************************/ 5767 5768 static void 5769 _iflib_assert(if_shared_ctx_t sctx) 5770 { 5771 int i; 5772 5773 MPASS(sctx->isc_tx_maxsize); 5774 MPASS(sctx->isc_tx_maxsegsize); 5775 5776 MPASS(sctx->isc_rx_maxsize); 5777 MPASS(sctx->isc_rx_nsegments); 5778 MPASS(sctx->isc_rx_maxsegsize); 5779 5780 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5781 for (i = 0; i < sctx->isc_nrxqs; i++) { 5782 MPASS(sctx->isc_nrxd_min[i]); 5783 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5784 MPASS(sctx->isc_nrxd_max[i]); 5785 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5786 MPASS(sctx->isc_nrxd_default[i]); 5787 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5788 } 5789 5790 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5791 for (i = 0; i < sctx->isc_ntxqs; i++) { 5792 MPASS(sctx->isc_ntxd_min[i]); 5793 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5794 MPASS(sctx->isc_ntxd_max[i]); 5795 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5796 MPASS(sctx->isc_ntxd_default[i]); 5797 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5798 } 5799 } 5800 5801 static void 5802 _iflib_pre_assert(if_softc_ctx_t scctx) 5803 { 5804 5805 MPASS(scctx->isc_txrx->ift_txd_encap); 5806 MPASS(scctx->isc_txrx->ift_txd_flush); 5807 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5808 MPASS(scctx->isc_txrx->ift_rxd_available); 5809 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5810 MPASS(scctx->isc_txrx->ift_rxd_refill); 5811 MPASS(scctx->isc_txrx->ift_rxd_flush); 5812 } 5813 5814 static int 5815 iflib_register(if_ctx_t ctx) 5816 { 5817 if_shared_ctx_t sctx = ctx->ifc_sctx; 5818 driver_t *driver = sctx->isc_driver; 5819 device_t dev = ctx->ifc_dev; 5820 if_t ifp; 5821 u_char type; 5822 int iflags; 5823 5824 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0) 5825 _iflib_assert(sctx); 5826 5827 CTX_LOCK_INIT(ctx); 5828 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5829 if (sctx->isc_flags & IFLIB_PSEUDO) { 5830 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) 5831 type = IFT_ETHER; 5832 else 5833 type = IFT_PPP; 5834 } else 5835 type = IFT_ETHER; 5836 ifp = ctx->ifc_ifp = if_alloc(type); 5837 if (ifp == NULL) { 5838 device_printf(dev, "can not allocate ifnet structure\n"); 5839 return (ENOMEM); 5840 } 5841 5842 /* 5843 * Initialize our context's device specific methods 5844 */ 5845 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5846 kobj_class_compile((kobj_class_t) driver); 5847 5848 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5849 if_setsoftc(ifp, ctx); 5850 if_setdev(ifp, dev); 5851 if_setinitfn(ifp, iflib_if_init); 5852 if_setioctlfn(ifp, iflib_if_ioctl); 5853 #ifdef ALTQ 5854 if_setstartfn(ifp, iflib_altq_if_start); 5855 if_settransmitfn(ifp, iflib_altq_if_transmit); 5856 if_setsendqready(ifp); 5857 #else 5858 if_settransmitfn(ifp, iflib_if_transmit); 5859 #endif 5860 if_setqflushfn(ifp, iflib_if_qflush); 5861 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH; 5862 5863 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5864 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) 5865 iflags |= IFF_POINTOPOINT; 5866 else 5867 iflags |= IFF_BROADCAST | IFF_SIMPLEX; 5868 if_setflags(ifp, iflags); 5869 ctx->ifc_vlan_attach_event = 5870 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5871 EVENTHANDLER_PRI_FIRST); 5872 ctx->ifc_vlan_detach_event = 5873 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5874 EVENTHANDLER_PRI_FIRST); 5875 5876 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5877 ctx->ifc_mediap = &ctx->ifc_media; 5878 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5879 iflib_media_change, iflib_media_status); 5880 } 5881 return (0); 5882 } 5883 5884 static void 5885 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5886 { 5887 /* Unregister VLAN events */ 5888 if (ctx->ifc_vlan_attach_event != NULL) { 5889 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5890 ctx->ifc_vlan_attach_event = NULL; 5891 } 5892 if (ctx->ifc_vlan_detach_event != NULL) { 5893 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5894 ctx->ifc_vlan_detach_event = NULL; 5895 } 5896 5897 } 5898 5899 static void 5900 iflib_deregister(if_ctx_t ctx) 5901 { 5902 if_t ifp = ctx->ifc_ifp; 5903 5904 /* Remove all media */ 5905 ifmedia_removeall(&ctx->ifc_media); 5906 5907 /* Ensure that VLAN event handlers are unregistered */ 5908 iflib_unregister_vlan_handlers(ctx); 5909 5910 /* Release kobject reference */ 5911 kobj_delete((kobj_t) ctx, NULL); 5912 5913 /* Free the ifnet structure */ 5914 if_free(ifp); 5915 5916 STATE_LOCK_DESTROY(ctx); 5917 5918 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5919 CTX_LOCK_DESTROY(ctx); 5920 } 5921 5922 static int 5923 iflib_queues_alloc(if_ctx_t ctx) 5924 { 5925 if_shared_ctx_t sctx = ctx->ifc_sctx; 5926 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5927 device_t dev = ctx->ifc_dev; 5928 int nrxqsets = scctx->isc_nrxqsets; 5929 int ntxqsets = scctx->isc_ntxqsets; 5930 iflib_txq_t txq; 5931 iflib_rxq_t rxq; 5932 iflib_fl_t fl = NULL; 5933 int i, j, cpu, err, txconf, rxconf; 5934 iflib_dma_info_t ifdip; 5935 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5936 uint32_t *txqsizes = scctx->isc_txqsizes; 5937 uint8_t nrxqs = sctx->isc_nrxqs; 5938 uint8_t ntxqs = sctx->isc_ntxqs; 5939 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5940 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0); 5941 caddr_t *vaddrs; 5942 uint64_t *paddrs; 5943 5944 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5945 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5946 KASSERT(nrxqs >= fl_offset + nfree_lists, 5947 ("there must be at least a rxq for each free list")); 5948 5949 /* Allocate the TX ring struct memory */ 5950 if (!(ctx->ifc_txqs = 5951 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5952 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5953 device_printf(dev, "Unable to allocate TX ring memory\n"); 5954 err = ENOMEM; 5955 goto fail; 5956 } 5957 5958 /* Now allocate the RX */ 5959 if (!(ctx->ifc_rxqs = 5960 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5961 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5962 device_printf(dev, "Unable to allocate RX ring memory\n"); 5963 err = ENOMEM; 5964 goto rx_fail; 5965 } 5966 5967 txq = ctx->ifc_txqs; 5968 rxq = ctx->ifc_rxqs; 5969 5970 /* 5971 * XXX handle allocation failure 5972 */ 5973 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5974 /* Set up some basics */ 5975 5976 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5977 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5978 device_printf(dev, 5979 "Unable to allocate TX DMA info memory\n"); 5980 err = ENOMEM; 5981 goto err_tx_desc; 5982 } 5983 txq->ift_ifdi = ifdip; 5984 for (j = 0; j < ntxqs; j++, ifdip++) { 5985 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5986 device_printf(dev, 5987 "Unable to allocate TX descriptors\n"); 5988 err = ENOMEM; 5989 goto err_tx_desc; 5990 } 5991 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5992 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5993 } 5994 txq->ift_ctx = ctx; 5995 txq->ift_id = i; 5996 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5997 txq->ift_br_offset = 1; 5998 } else { 5999 txq->ift_br_offset = 0; 6000 } 6001 6002 if (iflib_txsd_alloc(txq)) { 6003 device_printf(dev, "Critical Failure setting up TX buffers\n"); 6004 err = ENOMEM; 6005 goto err_tx_desc; 6006 } 6007 6008 /* Initialize the TX lock */ 6009 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 6010 device_get_nameunit(dev), txq->ift_id); 6011 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 6012 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 6013 txq->ift_timer.c_cpu = cpu; 6014 #ifdef DEV_NETMAP 6015 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 6016 txq->ift_netmap_timer.c_cpu = cpu; 6017 #endif /* DEV_NETMAP */ 6018 6019 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 6020 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 6021 if (err) { 6022 /* XXX free any allocated rings */ 6023 device_printf(dev, "Unable to allocate buf_ring\n"); 6024 goto err_tx_desc; 6025 } 6026 } 6027 6028 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 6029 /* Set up some basics */ 6030 callout_init(&rxq->ifr_watchdog, 1); 6031 6032 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 6033 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 6034 device_printf(dev, 6035 "Unable to allocate RX DMA info memory\n"); 6036 err = ENOMEM; 6037 goto err_tx_desc; 6038 } 6039 6040 rxq->ifr_ifdi = ifdip; 6041 /* XXX this needs to be changed if #rx queues != #tx queues */ 6042 rxq->ifr_ntxqirq = 1; 6043 rxq->ifr_txqid[0] = i; 6044 for (j = 0; j < nrxqs; j++, ifdip++) { 6045 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 6046 device_printf(dev, 6047 "Unable to allocate RX descriptors\n"); 6048 err = ENOMEM; 6049 goto err_tx_desc; 6050 } 6051 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 6052 } 6053 rxq->ifr_ctx = ctx; 6054 rxq->ifr_id = i; 6055 rxq->ifr_fl_offset = fl_offset; 6056 rxq->ifr_nfl = nfree_lists; 6057 if (!(fl = 6058 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 6059 device_printf(dev, "Unable to allocate free list memory\n"); 6060 err = ENOMEM; 6061 goto err_tx_desc; 6062 } 6063 rxq->ifr_fl = fl; 6064 for (j = 0; j < nfree_lists; j++) { 6065 fl[j].ifl_rxq = rxq; 6066 fl[j].ifl_id = j; 6067 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 6068 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 6069 } 6070 /* Allocate receive buffers for the ring */ 6071 if (iflib_rxsd_alloc(rxq)) { 6072 device_printf(dev, 6073 "Critical Failure setting up receive buffers\n"); 6074 err = ENOMEM; 6075 goto err_rx_desc; 6076 } 6077 6078 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 6079 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 6080 M_WAITOK); 6081 } 6082 6083 /* TXQs */ 6084 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 6085 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 6086 for (i = 0; i < ntxqsets; i++) { 6087 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 6088 6089 for (j = 0; j < ntxqs; j++, di++) { 6090 vaddrs[i*ntxqs + j] = di->idi_vaddr; 6091 paddrs[i*ntxqs + j] = di->idi_paddr; 6092 } 6093 } 6094 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 6095 device_printf(ctx->ifc_dev, 6096 "Unable to allocate device TX queue\n"); 6097 iflib_tx_structures_free(ctx); 6098 free(vaddrs, M_IFLIB); 6099 free(paddrs, M_IFLIB); 6100 goto err_rx_desc; 6101 } 6102 free(vaddrs, M_IFLIB); 6103 free(paddrs, M_IFLIB); 6104 6105 /* RXQs */ 6106 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6107 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6108 for (i = 0; i < nrxqsets; i++) { 6109 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 6110 6111 for (j = 0; j < nrxqs; j++, di++) { 6112 vaddrs[i*nrxqs + j] = di->idi_vaddr; 6113 paddrs[i*nrxqs + j] = di->idi_paddr; 6114 } 6115 } 6116 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 6117 device_printf(ctx->ifc_dev, 6118 "Unable to allocate device RX queue\n"); 6119 iflib_tx_structures_free(ctx); 6120 free(vaddrs, M_IFLIB); 6121 free(paddrs, M_IFLIB); 6122 goto err_rx_desc; 6123 } 6124 free(vaddrs, M_IFLIB); 6125 free(paddrs, M_IFLIB); 6126 6127 return (0); 6128 6129 /* XXX handle allocation failure changes */ 6130 err_rx_desc: 6131 err_tx_desc: 6132 rx_fail: 6133 if (ctx->ifc_rxqs != NULL) 6134 free(ctx->ifc_rxqs, M_IFLIB); 6135 ctx->ifc_rxqs = NULL; 6136 if (ctx->ifc_txqs != NULL) 6137 free(ctx->ifc_txqs, M_IFLIB); 6138 ctx->ifc_txqs = NULL; 6139 fail: 6140 return (err); 6141 } 6142 6143 static int 6144 iflib_tx_structures_setup(if_ctx_t ctx) 6145 { 6146 iflib_txq_t txq = ctx->ifc_txqs; 6147 int i; 6148 6149 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 6150 iflib_txq_setup(txq); 6151 6152 return (0); 6153 } 6154 6155 static void 6156 iflib_tx_structures_free(if_ctx_t ctx) 6157 { 6158 iflib_txq_t txq = ctx->ifc_txqs; 6159 if_shared_ctx_t sctx = ctx->ifc_sctx; 6160 int i, j; 6161 6162 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6163 for (j = 0; j < sctx->isc_ntxqs; j++) 6164 iflib_dma_free(&txq->ift_ifdi[j]); 6165 iflib_txq_destroy(txq); 6166 } 6167 free(ctx->ifc_txqs, M_IFLIB); 6168 ctx->ifc_txqs = NULL; 6169 } 6170 6171 /********************************************************************* 6172 * 6173 * Initialize all receive rings. 6174 * 6175 **********************************************************************/ 6176 static int 6177 iflib_rx_structures_setup(if_ctx_t ctx) 6178 { 6179 iflib_rxq_t rxq = ctx->ifc_rxqs; 6180 int q; 6181 #if defined(INET6) || defined(INET) 6182 int err, i; 6183 #endif 6184 6185 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 6186 #if defined(INET6) || defined(INET) 6187 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 6188 TCP_LRO_ENTRIES, min(1024, 6189 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 6190 if (err != 0) { 6191 device_printf(ctx->ifc_dev, 6192 "LRO Initialization failed!\n"); 6193 goto fail; 6194 } 6195 #endif 6196 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 6197 } 6198 return (0); 6199 #if defined(INET6) || defined(INET) 6200 fail: 6201 /* 6202 * Free LRO resources allocated so far, we will only handle 6203 * the rings that completed, the failing case will have 6204 * cleaned up for itself. 'q' failed, so its the terminus. 6205 */ 6206 rxq = ctx->ifc_rxqs; 6207 for (i = 0; i < q; ++i, rxq++) { 6208 tcp_lro_free(&rxq->ifr_lc); 6209 } 6210 return (err); 6211 #endif 6212 } 6213 6214 /********************************************************************* 6215 * 6216 * Free all receive rings. 6217 * 6218 **********************************************************************/ 6219 static void 6220 iflib_rx_structures_free(if_ctx_t ctx) 6221 { 6222 iflib_rxq_t rxq = ctx->ifc_rxqs; 6223 if_shared_ctx_t sctx = ctx->ifc_sctx; 6224 int i, j; 6225 6226 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 6227 for (j = 0; j < sctx->isc_nrxqs; j++) 6228 iflib_dma_free(&rxq->ifr_ifdi[j]); 6229 iflib_rx_sds_free(rxq); 6230 #if defined(INET6) || defined(INET) 6231 tcp_lro_free(&rxq->ifr_lc); 6232 #endif 6233 } 6234 free(ctx->ifc_rxqs, M_IFLIB); 6235 ctx->ifc_rxqs = NULL; 6236 } 6237 6238 static int 6239 iflib_qset_structures_setup(if_ctx_t ctx) 6240 { 6241 int err; 6242 6243 /* 6244 * It is expected that the caller takes care of freeing queues if this 6245 * fails. 6246 */ 6247 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 6248 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 6249 return (err); 6250 } 6251 6252 if ((err = iflib_rx_structures_setup(ctx)) != 0) 6253 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 6254 6255 return (err); 6256 } 6257 6258 int 6259 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 6260 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 6261 { 6262 6263 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 6264 } 6265 6266 /* Just to avoid copy/paste */ 6267 static inline int 6268 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6269 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 6270 const char *name) 6271 { 6272 device_t dev; 6273 unsigned int base_cpuid, cpuid; 6274 int err; 6275 6276 dev = ctx->ifc_dev; 6277 base_cpuid = ctx->ifc_sysctl_core_offset; 6278 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX); 6279 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, 6280 irq ? irq->ii_res : NULL, name); 6281 if (err) { 6282 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6283 return (err); 6284 } 6285 #ifdef notyet 6286 if (cpuid > ctx->ifc_cpuid_highest) 6287 ctx->ifc_cpuid_highest = cpuid; 6288 #endif 6289 return (0); 6290 } 6291 6292 int 6293 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6294 iflib_intr_type_t type, driver_filter_t *filter, 6295 void *filter_arg, int qid, const char *name) 6296 { 6297 device_t dev; 6298 struct grouptask *gtask; 6299 struct taskqgroup *tqg; 6300 iflib_filter_info_t info; 6301 gtask_fn_t *fn; 6302 int tqrid, err; 6303 driver_filter_t *intr_fast; 6304 void *q; 6305 6306 info = &ctx->ifc_filter_info; 6307 tqrid = rid; 6308 6309 switch (type) { 6310 /* XXX merge tx/rx for netmap? */ 6311 case IFLIB_INTR_TX: 6312 q = &ctx->ifc_txqs[qid]; 6313 info = &ctx->ifc_txqs[qid].ift_filter_info; 6314 gtask = &ctx->ifc_txqs[qid].ift_task; 6315 tqg = qgroup_if_io_tqg; 6316 fn = _task_fn_tx; 6317 intr_fast = iflib_fast_intr; 6318 GROUPTASK_INIT(gtask, 0, fn, q); 6319 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6320 break; 6321 case IFLIB_INTR_RX: 6322 q = &ctx->ifc_rxqs[qid]; 6323 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6324 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6325 tqg = qgroup_if_io_tqg; 6326 fn = _task_fn_rx; 6327 intr_fast = iflib_fast_intr; 6328 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6329 break; 6330 case IFLIB_INTR_RXTX: 6331 q = &ctx->ifc_rxqs[qid]; 6332 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6333 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6334 tqg = qgroup_if_io_tqg; 6335 fn = _task_fn_rx; 6336 intr_fast = iflib_fast_intr_rxtx; 6337 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6338 break; 6339 case IFLIB_INTR_ADMIN: 6340 q = ctx; 6341 tqrid = -1; 6342 info = &ctx->ifc_filter_info; 6343 gtask = &ctx->ifc_admin_task; 6344 tqg = qgroup_if_config_tqg; 6345 fn = _task_fn_admin; 6346 intr_fast = iflib_fast_intr_ctx; 6347 break; 6348 default: 6349 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6350 __func__); 6351 return (EINVAL); 6352 } 6353 6354 info->ifi_filter = filter; 6355 info->ifi_filter_arg = filter_arg; 6356 info->ifi_task = gtask; 6357 info->ifi_ctx = q; 6358 6359 dev = ctx->ifc_dev; 6360 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6361 if (err != 0) { 6362 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6363 return (err); 6364 } 6365 if (type == IFLIB_INTR_ADMIN) 6366 return (0); 6367 6368 if (tqrid != -1) { 6369 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6370 name); 6371 if (err) 6372 return (err); 6373 } else { 6374 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6375 } 6376 6377 return (0); 6378 } 6379 6380 void 6381 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6382 { 6383 device_t dev; 6384 struct grouptask *gtask; 6385 struct taskqgroup *tqg; 6386 gtask_fn_t *fn; 6387 void *q; 6388 int err; 6389 6390 switch (type) { 6391 case IFLIB_INTR_TX: 6392 q = &ctx->ifc_txqs[qid]; 6393 gtask = &ctx->ifc_txqs[qid].ift_task; 6394 tqg = qgroup_if_io_tqg; 6395 fn = _task_fn_tx; 6396 GROUPTASK_INIT(gtask, 0, fn, q); 6397 break; 6398 case IFLIB_INTR_RX: 6399 q = &ctx->ifc_rxqs[qid]; 6400 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6401 tqg = qgroup_if_io_tqg; 6402 fn = _task_fn_rx; 6403 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6404 break; 6405 case IFLIB_INTR_IOV: 6406 q = ctx; 6407 gtask = &ctx->ifc_vflr_task; 6408 tqg = qgroup_if_config_tqg; 6409 fn = _task_fn_iov; 6410 GROUPTASK_INIT(gtask, 0, fn, q); 6411 break; 6412 default: 6413 panic("unknown net intr type"); 6414 } 6415 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name); 6416 if (err) { 6417 dev = ctx->ifc_dev; 6418 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL, 6419 name); 6420 } 6421 } 6422 6423 void 6424 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6425 { 6426 6427 if (irq->ii_tag) 6428 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6429 6430 if (irq->ii_res) 6431 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6432 rman_get_rid(irq->ii_res), irq->ii_res); 6433 } 6434 6435 static int 6436 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6437 { 6438 iflib_txq_t txq = ctx->ifc_txqs; 6439 iflib_rxq_t rxq = ctx->ifc_rxqs; 6440 if_irq_t irq = &ctx->ifc_legacy_irq; 6441 iflib_filter_info_t info; 6442 device_t dev; 6443 struct grouptask *gtask; 6444 struct resource *res; 6445 struct taskqgroup *tqg; 6446 void *q; 6447 int err, tqrid; 6448 bool rx_only; 6449 6450 q = &ctx->ifc_rxqs[0]; 6451 info = &rxq[0].ifr_filter_info; 6452 gtask = &rxq[0].ifr_task; 6453 tqg = qgroup_if_io_tqg; 6454 tqrid = *rid; 6455 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6456 6457 ctx->ifc_flags |= IFC_LEGACY; 6458 info->ifi_filter = filter; 6459 info->ifi_filter_arg = filter_arg; 6460 info->ifi_task = gtask; 6461 info->ifi_ctx = rx_only ? ctx : q; 6462 6463 dev = ctx->ifc_dev; 6464 /* We allocate a single interrupt resource */ 6465 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6466 iflib_fast_intr_rxtx, NULL, info, name); 6467 if (err != 0) 6468 return (err); 6469 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6470 res = irq->ii_res; 6471 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6472 6473 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6474 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6475 "tx"); 6476 return (0); 6477 } 6478 6479 void 6480 iflib_led_create(if_ctx_t ctx) 6481 { 6482 6483 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6484 device_get_nameunit(ctx->ifc_dev)); 6485 } 6486 6487 void 6488 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6489 { 6490 6491 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6492 } 6493 6494 void 6495 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6496 { 6497 6498 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6499 } 6500 6501 void 6502 iflib_admin_intr_deferred(if_ctx_t ctx) 6503 { 6504 6505 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6506 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6507 } 6508 6509 void 6510 iflib_iov_intr_deferred(if_ctx_t ctx) 6511 { 6512 6513 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6514 } 6515 6516 void 6517 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6518 { 6519 6520 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6521 name); 6522 } 6523 6524 void 6525 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6526 const char *name) 6527 { 6528 6529 GROUPTASK_INIT(gtask, 0, fn, ctx); 6530 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6531 name); 6532 } 6533 6534 void 6535 iflib_config_gtask_deinit(struct grouptask *gtask) 6536 { 6537 6538 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6539 } 6540 6541 void 6542 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6543 { 6544 if_t ifp = ctx->ifc_ifp; 6545 iflib_txq_t txq = ctx->ifc_txqs; 6546 6547 if_setbaudrate(ifp, baudrate); 6548 if (baudrate >= IF_Gbps(10)) { 6549 STATE_LOCK(ctx); 6550 ctx->ifc_flags |= IFC_PREFETCH; 6551 STATE_UNLOCK(ctx); 6552 } 6553 /* If link down, disable watchdog */ 6554 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6555 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6556 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6557 } 6558 ctx->ifc_link_state = link_state; 6559 if_link_state_change(ifp, link_state); 6560 } 6561 6562 static int 6563 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6564 { 6565 int credits; 6566 #ifdef INVARIANTS 6567 int credits_pre = txq->ift_cidx_processed; 6568 #endif 6569 6570 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6571 BUS_DMASYNC_POSTREAD); 6572 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6573 return (0); 6574 6575 txq->ift_processed += credits; 6576 txq->ift_cidx_processed += credits; 6577 6578 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6579 if (txq->ift_cidx_processed >= txq->ift_size) 6580 txq->ift_cidx_processed -= txq->ift_size; 6581 return (credits); 6582 } 6583 6584 static int 6585 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6586 { 6587 iflib_fl_t fl; 6588 u_int i; 6589 6590 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6591 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6592 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6593 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6594 budget)); 6595 } 6596 6597 void 6598 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6599 const char *description, if_int_delay_info_t info, 6600 int offset, int value) 6601 { 6602 info->iidi_ctx = ctx; 6603 info->iidi_offset = offset; 6604 info->iidi_value = value; 6605 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6606 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6607 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6608 info, 0, iflib_sysctl_int_delay, "I", description); 6609 } 6610 6611 struct sx * 6612 iflib_ctx_lock_get(if_ctx_t ctx) 6613 { 6614 6615 return (&ctx->ifc_ctx_sx); 6616 } 6617 6618 static int 6619 iflib_msix_init(if_ctx_t ctx) 6620 { 6621 device_t dev = ctx->ifc_dev; 6622 if_shared_ctx_t sctx = ctx->ifc_sctx; 6623 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6624 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6625 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6626 6627 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6628 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6629 6630 if (bootverbose) 6631 device_printf(dev, "msix_init qsets capped at %d\n", 6632 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6633 6634 /* Override by tuneable */ 6635 if (scctx->isc_disable_msix) 6636 goto msi; 6637 6638 /* First try MSI-X */ 6639 if ((msgs = pci_msix_count(dev)) == 0) { 6640 if (bootverbose) 6641 device_printf(dev, "MSI-X not supported or disabled\n"); 6642 goto msi; 6643 } 6644 6645 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6646 /* 6647 * bar == -1 => "trust me I know what I'm doing" 6648 * Some drivers are for hardware that is so shoddily 6649 * documented that no one knows which bars are which 6650 * so the developer has to map all bars. This hack 6651 * allows shoddy garbage to use MSI-X in this framework. 6652 */ 6653 if (bar != -1) { 6654 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6655 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6656 if (ctx->ifc_msix_mem == NULL) { 6657 device_printf(dev, "Unable to map MSI-X table\n"); 6658 goto msi; 6659 } 6660 } 6661 6662 admincnt = sctx->isc_admin_intrcnt; 6663 #if IFLIB_DEBUG 6664 /* use only 1 qset in debug mode */ 6665 queuemsgs = min(msgs - admincnt, 1); 6666 #else 6667 queuemsgs = msgs - admincnt; 6668 #endif 6669 #ifdef RSS 6670 queues = imin(queuemsgs, rss_getnumbuckets()); 6671 #else 6672 queues = queuemsgs; 6673 #endif 6674 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6675 if (bootverbose) 6676 device_printf(dev, 6677 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6678 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6679 #ifdef RSS 6680 /* If we're doing RSS, clamp at the number of RSS buckets */ 6681 if (queues > rss_getnumbuckets()) 6682 queues = rss_getnumbuckets(); 6683 #endif 6684 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6685 rx_queues = iflib_num_rx_queues; 6686 else 6687 rx_queues = queues; 6688 6689 if (rx_queues > scctx->isc_nrxqsets) 6690 rx_queues = scctx->isc_nrxqsets; 6691 6692 /* 6693 * We want this to be all logical CPUs by default 6694 */ 6695 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6696 tx_queues = iflib_num_tx_queues; 6697 else 6698 tx_queues = mp_ncpus; 6699 6700 if (tx_queues > scctx->isc_ntxqsets) 6701 tx_queues = scctx->isc_ntxqsets; 6702 6703 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6704 #ifdef INVARIANTS 6705 if (tx_queues != rx_queues) 6706 device_printf(dev, 6707 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6708 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6709 #endif 6710 tx_queues = min(rx_queues, tx_queues); 6711 rx_queues = min(rx_queues, tx_queues); 6712 } 6713 6714 vectors = rx_queues + admincnt; 6715 if (msgs < vectors) { 6716 device_printf(dev, 6717 "insufficient number of MSI-X vectors " 6718 "(supported %d, need %d)\n", msgs, vectors); 6719 goto msi; 6720 } 6721 6722 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6723 tx_queues); 6724 msgs = vectors; 6725 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6726 if (vectors != msgs) { 6727 device_printf(dev, 6728 "Unable to allocate sufficient MSI-X vectors " 6729 "(got %d, need %d)\n", vectors, msgs); 6730 pci_release_msi(dev); 6731 if (bar != -1) { 6732 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6733 ctx->ifc_msix_mem); 6734 ctx->ifc_msix_mem = NULL; 6735 } 6736 goto msi; 6737 } 6738 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6739 vectors); 6740 scctx->isc_vectors = vectors; 6741 scctx->isc_nrxqsets = rx_queues; 6742 scctx->isc_ntxqsets = tx_queues; 6743 scctx->isc_intr = IFLIB_INTR_MSIX; 6744 6745 return (vectors); 6746 } else { 6747 device_printf(dev, 6748 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6749 err); 6750 if (bar != -1) { 6751 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6752 ctx->ifc_msix_mem); 6753 ctx->ifc_msix_mem = NULL; 6754 } 6755 } 6756 6757 msi: 6758 vectors = pci_msi_count(dev); 6759 scctx->isc_nrxqsets = 1; 6760 scctx->isc_ntxqsets = 1; 6761 scctx->isc_vectors = vectors; 6762 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6763 device_printf(dev,"Using an MSI interrupt\n"); 6764 scctx->isc_intr = IFLIB_INTR_MSI; 6765 } else { 6766 scctx->isc_vectors = 1; 6767 device_printf(dev,"Using a Legacy interrupt\n"); 6768 scctx->isc_intr = IFLIB_INTR_LEGACY; 6769 } 6770 6771 return (vectors); 6772 } 6773 6774 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6775 6776 static int 6777 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6778 { 6779 int rc; 6780 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6781 struct sbuf *sb; 6782 const char *ring_state = "UNKNOWN"; 6783 6784 /* XXX needed ? */ 6785 rc = sysctl_wire_old_buffer(req, 0); 6786 MPASS(rc == 0); 6787 if (rc != 0) 6788 return (rc); 6789 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6790 MPASS(sb != NULL); 6791 if (sb == NULL) 6792 return (ENOMEM); 6793 if (state[3] <= 3) 6794 ring_state = ring_states[state[3]]; 6795 6796 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6797 state[0], state[1], state[2], ring_state); 6798 rc = sbuf_finish(sb); 6799 sbuf_delete(sb); 6800 return(rc); 6801 } 6802 6803 enum iflib_ndesc_handler { 6804 IFLIB_NTXD_HANDLER, 6805 IFLIB_NRXD_HANDLER, 6806 }; 6807 6808 static int 6809 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6810 { 6811 if_ctx_t ctx = (void *)arg1; 6812 enum iflib_ndesc_handler type = arg2; 6813 char buf[256] = {0}; 6814 qidx_t *ndesc; 6815 char *p, *next; 6816 int nqs, rc, i; 6817 6818 nqs = 8; 6819 switch(type) { 6820 case IFLIB_NTXD_HANDLER: 6821 ndesc = ctx->ifc_sysctl_ntxds; 6822 if (ctx->ifc_sctx) 6823 nqs = ctx->ifc_sctx->isc_ntxqs; 6824 break; 6825 case IFLIB_NRXD_HANDLER: 6826 ndesc = ctx->ifc_sysctl_nrxds; 6827 if (ctx->ifc_sctx) 6828 nqs = ctx->ifc_sctx->isc_nrxqs; 6829 break; 6830 default: 6831 printf("%s: unhandled type\n", __func__); 6832 return (EINVAL); 6833 } 6834 if (nqs == 0) 6835 nqs = 8; 6836 6837 for (i=0; i<8; i++) { 6838 if (i >= nqs) 6839 break; 6840 if (i) 6841 strcat(buf, ","); 6842 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6843 } 6844 6845 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6846 if (rc || req->newptr == NULL) 6847 return rc; 6848 6849 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6850 i++, p = strsep(&next, " ,")) { 6851 ndesc[i] = strtoul(p, NULL, 10); 6852 } 6853 6854 return(rc); 6855 } 6856 6857 #define NAME_BUFLEN 32 6858 static void 6859 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6860 { 6861 device_t dev = iflib_get_dev(ctx); 6862 struct sysctl_oid_list *child, *oid_list; 6863 struct sysctl_ctx_list *ctx_list; 6864 struct sysctl_oid *node; 6865 6866 ctx_list = device_get_sysctl_ctx(dev); 6867 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6868 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6869 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 6870 oid_list = SYSCTL_CHILDREN(node); 6871 6872 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6873 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6874 "driver version"); 6875 6876 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6877 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6878 "# of txqs to use, 0 => use default #"); 6879 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6880 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6881 "# of rxqs to use, 0 => use default #"); 6882 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6883 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6884 "permit #txq != #rxq"); 6885 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6886 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6887 "disable MSI-X (default 0)"); 6888 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6889 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6890 "set the RX budget"); 6891 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6892 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6893 "cause TX to abdicate instead of running to completion"); 6894 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6895 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6896 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6897 "offset to start using cores at"); 6898 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6899 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6900 "use separate cores for TX and RX"); 6901 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "use_logical_cores", 6902 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0, 6903 "try to make use of logical cores for TX and RX"); 6904 6905 /* XXX change for per-queue sizes */ 6906 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6907 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6908 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6909 "list of # of TX descriptors to use, 0 = use default #"); 6910 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6911 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6912 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6913 "list of # of RX descriptors to use, 0 = use default #"); 6914 } 6915 6916 static void 6917 iflib_add_device_sysctl_post(if_ctx_t ctx) 6918 { 6919 if_shared_ctx_t sctx = ctx->ifc_sctx; 6920 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6921 device_t dev = iflib_get_dev(ctx); 6922 struct sysctl_oid_list *child; 6923 struct sysctl_ctx_list *ctx_list; 6924 iflib_fl_t fl; 6925 iflib_txq_t txq; 6926 iflib_rxq_t rxq; 6927 int i, j; 6928 char namebuf[NAME_BUFLEN]; 6929 char *qfmt; 6930 struct sysctl_oid *queue_node, *fl_node, *node; 6931 struct sysctl_oid_list *queue_list, *fl_list; 6932 ctx_list = device_get_sysctl_ctx(dev); 6933 6934 node = ctx->ifc_sysctl_node; 6935 child = SYSCTL_CHILDREN(node); 6936 6937 if (scctx->isc_ntxqsets > 100) 6938 qfmt = "txq%03d"; 6939 else if (scctx->isc_ntxqsets > 10) 6940 qfmt = "txq%02d"; 6941 else 6942 qfmt = "txq%d"; 6943 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6944 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6945 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6946 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6947 queue_list = SYSCTL_CHILDREN(queue_node); 6948 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 6949 CTLFLAG_RD, 6950 &txq->ift_task.gt_cpu, 0, "cpu this queue is bound to"); 6951 #if MEMORY_LOGGING 6952 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6953 CTLFLAG_RD, 6954 &txq->ift_dequeued, "total mbufs freed"); 6955 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6956 CTLFLAG_RD, 6957 &txq->ift_enqueued, "total mbufs enqueued"); 6958 #endif 6959 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6960 CTLFLAG_RD, 6961 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6962 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6963 CTLFLAG_RD, 6964 &txq->ift_pullups, "# of times m_pullup was called"); 6965 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6966 CTLFLAG_RD, 6967 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6968 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6969 CTLFLAG_RD, 6970 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6971 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6972 CTLFLAG_RD, 6973 &txq->ift_map_failed, "# of times DMA map failed"); 6974 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6975 CTLFLAG_RD, 6976 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6977 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6978 CTLFLAG_RD, 6979 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6980 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6981 CTLFLAG_RD, 6982 &txq->ift_pidx, 1, "Producer Index"); 6983 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6984 CTLFLAG_RD, 6985 &txq->ift_cidx, 1, "Consumer Index"); 6986 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6987 CTLFLAG_RD, 6988 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6989 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6990 CTLFLAG_RD, 6991 &txq->ift_in_use, 1, "descriptors in use"); 6992 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6993 CTLFLAG_RD, 6994 &txq->ift_processed, "descriptors procesed for clean"); 6995 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6996 CTLFLAG_RD, 6997 &txq->ift_cleaned, "total cleaned"); 6998 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6999 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 7000 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 7001 mp_ring_state_handler, "A", "soft ring state"); 7002 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 7003 CTLFLAG_RD, &txq->ift_br->enqueues, 7004 "# of enqueues to the mp_ring for this queue"); 7005 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 7006 CTLFLAG_RD, &txq->ift_br->drops, 7007 "# of drops in the mp_ring for this queue"); 7008 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 7009 CTLFLAG_RD, &txq->ift_br->starts, 7010 "# of normal consumer starts in the mp_ring for this queue"); 7011 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 7012 CTLFLAG_RD, &txq->ift_br->stalls, 7013 "# of consumer stalls in the mp_ring for this queue"); 7014 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 7015 CTLFLAG_RD, &txq->ift_br->restarts, 7016 "# of consumer restarts in the mp_ring for this queue"); 7017 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 7018 CTLFLAG_RD, &txq->ift_br->abdications, 7019 "# of consumer abdications in the mp_ring for this queue"); 7020 } 7021 7022 if (scctx->isc_nrxqsets > 100) 7023 qfmt = "rxq%03d"; 7024 else if (scctx->isc_nrxqsets > 10) 7025 qfmt = "rxq%02d"; 7026 else 7027 qfmt = "rxq%d"; 7028 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 7029 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 7030 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 7031 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 7032 queue_list = SYSCTL_CHILDREN(queue_node); 7033 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 7034 CTLFLAG_RD, 7035 &rxq->ifr_task.gt_cpu, 0, "cpu this queue is bound to"); 7036 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 7037 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 7038 CTLFLAG_RD, 7039 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 7040 } 7041 7042 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 7043 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 7044 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 7045 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 7046 fl_list = SYSCTL_CHILDREN(fl_node); 7047 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 7048 CTLFLAG_RD, 7049 &fl->ifl_pidx, 1, "Producer Index"); 7050 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 7051 CTLFLAG_RD, 7052 &fl->ifl_cidx, 1, "Consumer Index"); 7053 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 7054 CTLFLAG_RD, 7055 &fl->ifl_credits, 1, "credits available"); 7056 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 7057 CTLFLAG_RD, 7058 &fl->ifl_buf_size, 1, "buffer size"); 7059 #if MEMORY_LOGGING 7060 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 7061 CTLFLAG_RD, 7062 &fl->ifl_m_enqueued, "mbufs allocated"); 7063 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 7064 CTLFLAG_RD, 7065 &fl->ifl_m_dequeued, "mbufs freed"); 7066 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 7067 CTLFLAG_RD, 7068 &fl->ifl_cl_enqueued, "clusters allocated"); 7069 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 7070 CTLFLAG_RD, 7071 &fl->ifl_cl_dequeued, "clusters freed"); 7072 #endif 7073 } 7074 } 7075 7076 } 7077 7078 void 7079 iflib_request_reset(if_ctx_t ctx) 7080 { 7081 7082 STATE_LOCK(ctx); 7083 ctx->ifc_flags |= IFC_DO_RESET; 7084 STATE_UNLOCK(ctx); 7085 } 7086 7087 #ifndef __NO_STRICT_ALIGNMENT 7088 static struct mbuf * 7089 iflib_fixup_rx(struct mbuf *m) 7090 { 7091 struct mbuf *n; 7092 7093 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 7094 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 7095 m->m_data += ETHER_HDR_LEN; 7096 n = m; 7097 } else { 7098 MGETHDR(n, M_NOWAIT, MT_DATA); 7099 if (n == NULL) { 7100 m_freem(m); 7101 return (NULL); 7102 } 7103 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 7104 m->m_data += ETHER_HDR_LEN; 7105 m->m_len -= ETHER_HDR_LEN; 7106 n->m_len = ETHER_HDR_LEN; 7107 M_MOVE_PKTHDR(n, m); 7108 n->m_next = m; 7109 } 7110 return (n); 7111 } 7112 #endif 7113 7114 #ifdef DEBUGNET 7115 static void 7116 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 7117 { 7118 if_ctx_t ctx; 7119 7120 ctx = if_getsoftc(ifp); 7121 CTX_LOCK(ctx); 7122 *nrxr = NRXQSETS(ctx); 7123 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 7124 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 7125 CTX_UNLOCK(ctx); 7126 } 7127 7128 static void 7129 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 7130 { 7131 if_ctx_t ctx; 7132 if_softc_ctx_t scctx; 7133 iflib_fl_t fl; 7134 iflib_rxq_t rxq; 7135 int i, j; 7136 7137 ctx = if_getsoftc(ifp); 7138 scctx = &ctx->ifc_softc_ctx; 7139 7140 switch (event) { 7141 case DEBUGNET_START: 7142 for (i = 0; i < scctx->isc_nrxqsets; i++) { 7143 rxq = &ctx->ifc_rxqs[i]; 7144 for (j = 0; j < rxq->ifr_nfl; j++) { 7145 fl = rxq->ifr_fl; 7146 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 7147 } 7148 } 7149 iflib_no_tx_batch = 1; 7150 break; 7151 default: 7152 break; 7153 } 7154 } 7155 7156 static int 7157 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 7158 { 7159 if_ctx_t ctx; 7160 iflib_txq_t txq; 7161 int error; 7162 7163 ctx = if_getsoftc(ifp); 7164 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7165 IFF_DRV_RUNNING) 7166 return (EBUSY); 7167 7168 txq = &ctx->ifc_txqs[0]; 7169 error = iflib_encap(txq, &m); 7170 if (error == 0) 7171 (void)iflib_txd_db_check(txq, true); 7172 return (error); 7173 } 7174 7175 static int 7176 iflib_debugnet_poll(if_t ifp, int count) 7177 { 7178 struct epoch_tracker et; 7179 if_ctx_t ctx; 7180 if_softc_ctx_t scctx; 7181 iflib_txq_t txq; 7182 int i; 7183 7184 ctx = if_getsoftc(ifp); 7185 scctx = &ctx->ifc_softc_ctx; 7186 7187 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7188 IFF_DRV_RUNNING) 7189 return (EBUSY); 7190 7191 txq = &ctx->ifc_txqs[0]; 7192 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 7193 7194 NET_EPOCH_ENTER(et); 7195 for (i = 0; i < scctx->isc_nrxqsets; i++) 7196 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 7197 NET_EPOCH_EXIT(et); 7198 return (0); 7199 } 7200 #endif /* DEBUGNET */ 7201