1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 /* 120 * File organization: 121 * - private structures 122 * - iflib private utility functions 123 * - ifnet functions 124 * - vlan registry and other exported functions 125 * - iflib public core functions 126 * 127 * 128 */ 129 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 130 131 #define IFLIB_RXEOF_MORE (1U << 0) 132 #define IFLIB_RXEOF_EMPTY (2U << 0) 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 static void iflib_tqg_detach(if_ctx_t ctx); 146 147 typedef struct iflib_filter_info { 148 driver_filter_t *ifi_filter; 149 void *ifi_filter_arg; 150 struct grouptask *ifi_task; 151 void *ifi_ctx; 152 } *iflib_filter_info_t; 153 154 struct iflib_ctx { 155 KOBJ_FIELDS; 156 /* 157 * Pointer to hardware driver's softc 158 */ 159 void *ifc_softc; 160 device_t ifc_dev; 161 if_t ifc_ifp; 162 163 cpuset_t ifc_cpus; 164 if_shared_ctx_t ifc_sctx; 165 struct if_softc_ctx ifc_softc_ctx; 166 167 struct sx ifc_ctx_sx; 168 struct mtx ifc_state_mtx; 169 170 iflib_txq_t ifc_txqs; 171 iflib_rxq_t ifc_rxqs; 172 uint32_t ifc_if_flags; 173 uint32_t ifc_flags; 174 uint32_t ifc_max_fl_buf_size; 175 uint32_t ifc_rx_mbuf_sz; 176 177 int ifc_link_state; 178 int ifc_watchdog_events; 179 struct cdev *ifc_led_dev; 180 struct resource *ifc_msix_mem; 181 182 struct if_irq ifc_legacy_irq; 183 struct grouptask ifc_admin_task; 184 struct grouptask ifc_vflr_task; 185 struct iflib_filter_info ifc_filter_info; 186 struct ifmedia ifc_media; 187 struct ifmedia *ifc_mediap; 188 189 struct sysctl_oid *ifc_sysctl_node; 190 uint16_t ifc_sysctl_ntxqs; 191 uint16_t ifc_sysctl_nrxqs; 192 uint16_t ifc_sysctl_qs_eq_override; 193 uint16_t ifc_sysctl_rx_budget; 194 uint16_t ifc_sysctl_tx_abdicate; 195 uint16_t ifc_sysctl_core_offset; 196 #define CORE_OFFSET_UNSPECIFIED 0xffff 197 uint8_t ifc_sysctl_separate_txrx; 198 199 qidx_t ifc_sysctl_ntxds[8]; 200 qidx_t ifc_sysctl_nrxds[8]; 201 struct if_txrx ifc_txrx; 202 #define isc_txd_encap ifc_txrx.ift_txd_encap 203 #define isc_txd_flush ifc_txrx.ift_txd_flush 204 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 205 #define isc_rxd_available ifc_txrx.ift_rxd_available 206 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 209 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 210 eventhandler_tag ifc_vlan_attach_event; 211 eventhandler_tag ifc_vlan_detach_event; 212 struct ether_addr ifc_mac; 213 }; 214 215 void * 216 iflib_get_softc(if_ctx_t ctx) 217 { 218 219 return (ctx->ifc_softc); 220 } 221 222 device_t 223 iflib_get_dev(if_ctx_t ctx) 224 { 225 226 return (ctx->ifc_dev); 227 } 228 229 if_t 230 iflib_get_ifp(if_ctx_t ctx) 231 { 232 233 return (ctx->ifc_ifp); 234 } 235 236 struct ifmedia * 237 iflib_get_media(if_ctx_t ctx) 238 { 239 240 return (ctx->ifc_mediap); 241 } 242 243 uint32_t 244 iflib_get_flags(if_ctx_t ctx) 245 { 246 return (ctx->ifc_flags); 247 } 248 249 void 250 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 251 { 252 253 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 254 } 255 256 if_softc_ctx_t 257 iflib_get_softc_ctx(if_ctx_t ctx) 258 { 259 260 return (&ctx->ifc_softc_ctx); 261 } 262 263 if_shared_ctx_t 264 iflib_get_sctx(if_ctx_t ctx) 265 { 266 267 return (ctx->ifc_sctx); 268 } 269 270 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 271 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 272 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 273 274 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 275 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 276 277 typedef struct iflib_sw_rx_desc_array { 278 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 279 struct mbuf **ifsd_m; /* pkthdr mbufs */ 280 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 281 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 282 } iflib_rxsd_array_t; 283 284 typedef struct iflib_sw_tx_desc_array { 285 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 286 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 287 struct mbuf **ifsd_m; /* pkthdr mbufs */ 288 } if_txsd_vec_t; 289 290 /* magic number that should be high enough for any hardware */ 291 #define IFLIB_MAX_TX_SEGS 128 292 #define IFLIB_RX_COPY_THRESH 128 293 #define IFLIB_MAX_RX_REFRESH 32 294 /* The minimum descriptors per second before we start coalescing */ 295 #define IFLIB_MIN_DESC_SEC 16384 296 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 297 #define IFLIB_QUEUE_IDLE 0 298 #define IFLIB_QUEUE_HUNG 1 299 #define IFLIB_QUEUE_WORKING 2 300 /* maximum number of txqs that can share an rx interrupt */ 301 #define IFLIB_MAX_TX_SHARED_INTR 4 302 303 /* this should really scale with ring size - this is a fairly arbitrary value */ 304 #define TX_BATCH_SIZE 32 305 306 #define IFLIB_RESTART_BUDGET 8 307 308 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 309 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 310 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 311 312 struct iflib_txq { 313 qidx_t ift_in_use; 314 qidx_t ift_cidx; 315 qidx_t ift_cidx_processed; 316 qidx_t ift_pidx; 317 uint8_t ift_gen; 318 uint8_t ift_br_offset; 319 uint16_t ift_npending; 320 uint16_t ift_db_pending; 321 uint16_t ift_rs_pending; 322 /* implicit pad */ 323 uint8_t ift_txd_size[8]; 324 uint64_t ift_processed; 325 uint64_t ift_cleaned; 326 uint64_t ift_cleaned_prev; 327 #if MEMORY_LOGGING 328 uint64_t ift_enqueued; 329 uint64_t ift_dequeued; 330 #endif 331 uint64_t ift_no_tx_dma_setup; 332 uint64_t ift_no_desc_avail; 333 uint64_t ift_mbuf_defrag_failed; 334 uint64_t ift_mbuf_defrag; 335 uint64_t ift_map_failed; 336 uint64_t ift_txd_encap_efbig; 337 uint64_t ift_pullups; 338 uint64_t ift_last_timer_tick; 339 340 struct mtx ift_mtx; 341 struct mtx ift_db_mtx; 342 343 /* constant values */ 344 if_ctx_t ift_ctx; 345 struct ifmp_ring *ift_br; 346 struct grouptask ift_task; 347 qidx_t ift_size; 348 uint16_t ift_id; 349 struct callout ift_timer; 350 #ifdef DEV_NETMAP 351 struct callout ift_netmap_timer; 352 #endif /* DEV_NETMAP */ 353 354 if_txsd_vec_t ift_sds; 355 uint8_t ift_qstatus; 356 uint8_t ift_closed; 357 uint8_t ift_update_freq; 358 struct iflib_filter_info ift_filter_info; 359 bus_dma_tag_t ift_buf_tag; 360 bus_dma_tag_t ift_tso_buf_tag; 361 iflib_dma_info_t ift_ifdi; 362 #define MTX_NAME_LEN 32 363 char ift_mtx_name[MTX_NAME_LEN]; 364 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 365 #ifdef IFLIB_DIAGNOSTICS 366 uint64_t ift_cpu_exec_count[256]; 367 #endif 368 } __aligned(CACHE_LINE_SIZE); 369 370 struct iflib_fl { 371 qidx_t ifl_cidx; 372 qidx_t ifl_pidx; 373 qidx_t ifl_credits; 374 uint8_t ifl_gen; 375 uint8_t ifl_rxd_size; 376 #if MEMORY_LOGGING 377 uint64_t ifl_m_enqueued; 378 uint64_t ifl_m_dequeued; 379 uint64_t ifl_cl_enqueued; 380 uint64_t ifl_cl_dequeued; 381 #endif 382 /* implicit pad */ 383 bitstr_t *ifl_rx_bitmap; 384 qidx_t ifl_fragidx; 385 /* constant */ 386 qidx_t ifl_size; 387 uint16_t ifl_buf_size; 388 uint16_t ifl_cltype; 389 uma_zone_t ifl_zone; 390 iflib_rxsd_array_t ifl_sds; 391 iflib_rxq_t ifl_rxq; 392 uint8_t ifl_id; 393 bus_dma_tag_t ifl_buf_tag; 394 iflib_dma_info_t ifl_ifdi; 395 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 396 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 397 } __aligned(CACHE_LINE_SIZE); 398 399 static inline qidx_t 400 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 401 { 402 qidx_t used; 403 404 if (pidx > cidx) 405 used = pidx - cidx; 406 else if (pidx < cidx) 407 used = size - cidx + pidx; 408 else if (gen == 0 && pidx == cidx) 409 used = 0; 410 else if (gen == 1 && pidx == cidx) 411 used = size; 412 else 413 panic("bad state"); 414 415 return (used); 416 } 417 418 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 419 420 #define IDXDIFF(head, tail, wrap) \ 421 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 422 423 struct iflib_rxq { 424 if_ctx_t ifr_ctx; 425 iflib_fl_t ifr_fl; 426 uint64_t ifr_rx_irq; 427 struct pfil_head *pfil; 428 /* 429 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 430 * the completion queue consumer index. Otherwise it's unused. 431 */ 432 qidx_t ifr_cq_cidx; 433 uint16_t ifr_id; 434 uint8_t ifr_nfl; 435 uint8_t ifr_ntxqirq; 436 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 437 uint8_t ifr_fl_offset; 438 struct lro_ctrl ifr_lc; 439 struct grouptask ifr_task; 440 struct callout ifr_watchdog; 441 struct iflib_filter_info ifr_filter_info; 442 iflib_dma_info_t ifr_ifdi; 443 444 /* dynamically allocate if any drivers need a value substantially larger than this */ 445 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 446 #ifdef IFLIB_DIAGNOSTICS 447 uint64_t ifr_cpu_exec_count[256]; 448 #endif 449 } __aligned(CACHE_LINE_SIZE); 450 451 typedef struct if_rxsd { 452 caddr_t *ifsd_cl; 453 iflib_fl_t ifsd_fl; 454 } *if_rxsd_t; 455 456 /* multiple of word size */ 457 #ifdef __LP64__ 458 #define PKT_INFO_SIZE 6 459 #define RXD_INFO_SIZE 5 460 #define PKT_TYPE uint64_t 461 #else 462 #define PKT_INFO_SIZE 11 463 #define RXD_INFO_SIZE 8 464 #define PKT_TYPE uint32_t 465 #endif 466 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 467 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 468 469 typedef struct if_pkt_info_pad { 470 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 471 } *if_pkt_info_pad_t; 472 typedef struct if_rxd_info_pad { 473 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 474 } *if_rxd_info_pad_t; 475 476 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 477 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 478 479 static inline void 480 pkt_info_zero(if_pkt_info_t pi) 481 { 482 if_pkt_info_pad_t pi_pad; 483 484 pi_pad = (if_pkt_info_pad_t)pi; 485 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 486 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 487 #ifndef __LP64__ 488 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 489 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 490 #endif 491 } 492 493 static device_method_t iflib_pseudo_methods[] = { 494 DEVMETHOD(device_attach, noop_attach), 495 DEVMETHOD(device_detach, iflib_pseudo_detach), 496 DEVMETHOD_END 497 }; 498 499 driver_t iflib_pseudodriver = { 500 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 501 }; 502 503 static inline void 504 rxd_info_zero(if_rxd_info_t ri) 505 { 506 if_rxd_info_pad_t ri_pad; 507 int i; 508 509 ri_pad = (if_rxd_info_pad_t)ri; 510 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 511 ri_pad->rxd_val[i] = 0; 512 ri_pad->rxd_val[i+1] = 0; 513 ri_pad->rxd_val[i+2] = 0; 514 ri_pad->rxd_val[i+3] = 0; 515 } 516 #ifdef __LP64__ 517 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 518 #endif 519 } 520 521 /* 522 * Only allow a single packet to take up most 1/nth of the tx ring 523 */ 524 #define MAX_SINGLE_PACKET_FRACTION 12 525 #define IF_BAD_DMA (bus_addr_t)-1 526 527 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 528 529 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 530 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 531 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 532 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 533 534 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 535 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 536 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 537 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 538 539 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 540 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 541 542 void 543 iflib_set_detach(if_ctx_t ctx) 544 { 545 STATE_LOCK(ctx); 546 ctx->ifc_flags |= IFC_IN_DETACH; 547 STATE_UNLOCK(ctx); 548 } 549 550 /* Our boot-time initialization hook */ 551 static int iflib_module_event_handler(module_t, int, void *); 552 553 static moduledata_t iflib_moduledata = { 554 "iflib", 555 iflib_module_event_handler, 556 NULL 557 }; 558 559 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 560 MODULE_VERSION(iflib, 1); 561 562 MODULE_DEPEND(iflib, pci, 1, 1, 1); 563 MODULE_DEPEND(iflib, ether, 1, 1, 1); 564 565 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 566 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 567 568 #ifndef IFLIB_DEBUG_COUNTERS 569 #ifdef INVARIANTS 570 #define IFLIB_DEBUG_COUNTERS 1 571 #else 572 #define IFLIB_DEBUG_COUNTERS 0 573 #endif /* !INVARIANTS */ 574 #endif 575 576 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 577 "iflib driver parameters"); 578 579 /* 580 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 581 */ 582 static int iflib_min_tx_latency = 0; 583 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 584 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 585 static int iflib_no_tx_batch = 0; 586 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 587 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 588 static int iflib_timer_default = 1000; 589 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW, 590 &iflib_timer_default, 0, "number of ticks between iflib_timer calls"); 591 592 593 #if IFLIB_DEBUG_COUNTERS 594 595 static int iflib_tx_seen; 596 static int iflib_tx_sent; 597 static int iflib_tx_encap; 598 static int iflib_rx_allocs; 599 static int iflib_fl_refills; 600 static int iflib_fl_refills_large; 601 static int iflib_tx_frees; 602 603 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 604 &iflib_tx_seen, 0, "# TX mbufs seen"); 605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 606 &iflib_tx_sent, 0, "# TX mbufs sent"); 607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 608 &iflib_tx_encap, 0, "# TX mbufs encapped"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 610 &iflib_tx_frees, 0, "# TX frees"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 612 &iflib_rx_allocs, 0, "# RX allocations"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 614 &iflib_fl_refills, 0, "# refills"); 615 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 616 &iflib_fl_refills_large, 0, "# large refills"); 617 618 static int iflib_txq_drain_flushing; 619 static int iflib_txq_drain_oactive; 620 static int iflib_txq_drain_notready; 621 622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 623 &iflib_txq_drain_flushing, 0, "# drain flushes"); 624 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 625 &iflib_txq_drain_oactive, 0, "# drain oactives"); 626 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 627 &iflib_txq_drain_notready, 0, "# drain notready"); 628 629 static int iflib_encap_load_mbuf_fail; 630 static int iflib_encap_pad_mbuf_fail; 631 static int iflib_encap_txq_avail_fail; 632 static int iflib_encap_txd_encap_fail; 633 634 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 635 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 637 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 638 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 639 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 640 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 641 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 642 643 static int iflib_task_fn_rxs; 644 static int iflib_rx_intr_enables; 645 static int iflib_fast_intrs; 646 static int iflib_rx_unavail; 647 static int iflib_rx_ctx_inactive; 648 static int iflib_rx_if_input; 649 static int iflib_rxd_flush; 650 651 static int iflib_verbose_debug; 652 653 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 654 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 655 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 656 &iflib_rx_intr_enables, 0, "# RX intr enables"); 657 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 658 &iflib_fast_intrs, 0, "# fast_intr calls"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 660 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 662 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 664 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 666 &iflib_rxd_flush, 0, "# times rxd_flush called"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 668 &iflib_verbose_debug, 0, "enable verbose debugging"); 669 670 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 671 static void 672 iflib_debug_reset(void) 673 { 674 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 675 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 676 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 677 iflib_txq_drain_notready = 678 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 679 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 680 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 681 iflib_rx_unavail = 682 iflib_rx_ctx_inactive = iflib_rx_if_input = 683 iflib_rxd_flush = 0; 684 } 685 686 #else 687 #define DBG_COUNTER_INC(name) 688 static void iflib_debug_reset(void) {} 689 #endif 690 691 #define IFLIB_DEBUG 0 692 693 static void iflib_tx_structures_free(if_ctx_t ctx); 694 static void iflib_rx_structures_free(if_ctx_t ctx); 695 static int iflib_queues_alloc(if_ctx_t ctx); 696 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 697 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 698 static int iflib_qset_structures_setup(if_ctx_t ctx); 699 static int iflib_msix_init(if_ctx_t ctx); 700 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 701 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 702 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 703 #ifdef ALTQ 704 static void iflib_altq_if_start(if_t ifp); 705 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 706 #endif 707 static int iflib_register(if_ctx_t); 708 static void iflib_deregister(if_ctx_t); 709 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 710 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 711 static void iflib_init_locked(if_ctx_t ctx); 712 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 713 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 714 static void iflib_ifmp_purge(iflib_txq_t txq); 715 static void _iflib_pre_assert(if_softc_ctx_t scctx); 716 static void iflib_if_init_locked(if_ctx_t ctx); 717 static void iflib_free_intr_mem(if_ctx_t ctx); 718 #ifndef __NO_STRICT_ALIGNMENT 719 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 720 #endif 721 722 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 723 SLIST_HEAD_INITIALIZER(cpu_offsets); 724 struct cpu_offset { 725 SLIST_ENTRY(cpu_offset) entries; 726 cpuset_t set; 727 unsigned int refcount; 728 uint16_t offset; 729 }; 730 static struct mtx cpu_offset_mtx; 731 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 732 MTX_DEF); 733 734 DEBUGNET_DEFINE(iflib); 735 736 static int 737 iflib_num_rx_descs(if_ctx_t ctx) 738 { 739 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 740 if_shared_ctx_t sctx = ctx->ifc_sctx; 741 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 742 743 return scctx->isc_nrxd[first_rxq]; 744 } 745 746 static int 747 iflib_num_tx_descs(if_ctx_t ctx) 748 { 749 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 750 if_shared_ctx_t sctx = ctx->ifc_sctx; 751 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 752 753 return scctx->isc_ntxd[first_txq]; 754 } 755 756 #ifdef DEV_NETMAP 757 #include <sys/selinfo.h> 758 #include <net/netmap.h> 759 #include <dev/netmap/netmap_kern.h> 760 761 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 762 763 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 764 static void iflib_netmap_timer(void *arg); 765 766 /* 767 * device-specific sysctl variables: 768 * 769 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 770 * During regular operations the CRC is stripped, but on some 771 * hardware reception of frames not multiple of 64 is slower, 772 * so using crcstrip=0 helps in benchmarks. 773 * 774 * iflib_rx_miss, iflib_rx_miss_bufs: 775 * count packets that might be missed due to lost interrupts. 776 */ 777 SYSCTL_DECL(_dev_netmap); 778 /* 779 * The xl driver by default strips CRCs and we do not override it. 780 */ 781 782 int iflib_crcstrip = 1; 783 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 784 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 785 786 int iflib_rx_miss, iflib_rx_miss_bufs; 787 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 788 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 789 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 790 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 791 792 /* 793 * Register/unregister. We are already under netmap lock. 794 * Only called on the first register or the last unregister. 795 */ 796 static int 797 iflib_netmap_register(struct netmap_adapter *na, int onoff) 798 { 799 if_t ifp = na->ifp; 800 if_ctx_t ctx = ifp->if_softc; 801 int status; 802 803 CTX_LOCK(ctx); 804 if (!CTX_IS_VF(ctx)) 805 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 806 807 iflib_stop(ctx); 808 809 /* 810 * Enable (or disable) netmap flags, and intercept (or restore) 811 * ifp->if_transmit. This is done once the device has been stopped 812 * to prevent race conditions. Also, this must be done after 813 * calling netmap_disable_all_rings() and before calling 814 * netmap_enable_all_rings(), so that these two functions see the 815 * updated state of the NAF_NETMAP_ON bit. 816 */ 817 if (onoff) { 818 nm_set_native_flags(na); 819 } else { 820 nm_clear_native_flags(na); 821 } 822 823 iflib_init_locked(ctx); 824 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 825 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 826 if (status) 827 nm_clear_native_flags(na); 828 CTX_UNLOCK(ctx); 829 return (status); 830 } 831 832 static int 833 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 834 { 835 struct netmap_adapter *na = kring->na; 836 u_int const lim = kring->nkr_num_slots - 1; 837 u_int nm_i = kring->nr_hwcur; 838 struct netmap_ring *ring = kring->ring; 839 bus_dmamap_t *map; 840 struct if_rxd_update iru; 841 if_ctx_t ctx = rxq->ifr_ctx; 842 iflib_fl_t fl = &rxq->ifr_fl[0]; 843 u_int nic_i_first, nic_i; 844 int i, n; 845 #if IFLIB_DEBUG_COUNTERS 846 int rf_count = 0; 847 #endif 848 849 /* 850 * This function is used both at initialization and in rxsync. 851 * At initialization we need to prepare (with isc_rxd_refill()) 852 * all the (N) netmap buffers in the ring, in such a way to keep 853 * fl->ifl_pidx and kring->nr_hwcur in sync (except for 854 * kring->nkr_hwofs); at rxsync time, both indexes point to the 855 * next buffer to be refilled. 856 * In any case we publish (with isc_rxd_flush()) up to 857 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 858 * pointer to overrun the head/cons pointer, although this is 859 * not necessary for some NICs (e.g. vmx). 860 */ 861 if (__predict_false(init)) 862 n = kring->nkr_num_slots; 863 else { 864 n = kring->rhead - nm_i; 865 if (n == 0) 866 return (0); /* Nothing to do. */ 867 if (n < 0) 868 n += kring->nkr_num_slots; 869 } 870 871 /* Start to refill from nr_hwcur, publishing n buffers. */ 872 iru_init(&iru, rxq, 0 /* flid */); 873 map = fl->ifl_sds.ifsd_map; 874 nic_i = fl->ifl_pidx; 875 MPASS(!init || nic_i == 0); /* on init/reset, nic_i must be 0 */ 876 MPASS(nic_i == netmap_idx_k2n(kring, nm_i)); 877 DBG_COUNTER_INC(fl_refills); 878 while (n > 0) { 879 #if IFLIB_DEBUG_COUNTERS 880 if (++rf_count == 9) 881 DBG_COUNTER_INC(fl_refills_large); 882 #endif 883 nic_i_first = nic_i; 884 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 885 struct netmap_slot *slot = &ring->slot[nm_i]; 886 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]); 887 888 MPASS(i < IFLIB_MAX_RX_REFRESH); 889 890 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 891 return netmap_ring_reinit(kring); 892 893 fl->ifl_rxd_idxs[i] = nic_i; 894 895 if (__predict_false(init)) { 896 netmap_load_map(na, fl->ifl_buf_tag, 897 map[nic_i], addr); 898 } else if (slot->flags & NS_BUF_CHANGED) { 899 /* buffer has changed, reload map */ 900 netmap_reload_map(na, fl->ifl_buf_tag, 901 map[nic_i], addr); 902 } 903 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 904 BUS_DMASYNC_PREREAD); 905 slot->flags &= ~NS_BUF_CHANGED; 906 907 nm_i = nm_next(nm_i, lim); 908 nic_i = nm_next(nic_i, lim); 909 } 910 911 iru.iru_pidx = nic_i_first; 912 iru.iru_count = i; 913 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 914 } 915 fl->ifl_pidx = nic_i; 916 MPASS(!init || nic_i == 0); /* on init/reset nic_i wraps around to 0 */ 917 MPASS(nm_i == kring->rhead); 918 kring->nr_hwcur = nm_i; 919 920 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 921 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 922 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 923 nm_prev(nic_i, lim)); 924 DBG_COUNTER_INC(rxd_flush); 925 926 return (0); 927 } 928 929 #define NETMAP_TX_TIMER_US 90 930 931 /* 932 * Reconcile kernel and user view of the transmit ring. 933 * 934 * All information is in the kring. 935 * Userspace wants to send packets up to the one before kring->rhead, 936 * kernel knows kring->nr_hwcur is the first unsent packet. 937 * 938 * Here we push packets out (as many as possible), and possibly 939 * reclaim buffers from previously completed transmission. 940 * 941 * The caller (netmap) guarantees that there is only one instance 942 * running at any time. Any interference with other driver 943 * methods should be handled by the individual drivers. 944 */ 945 static int 946 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 947 { 948 struct netmap_adapter *na = kring->na; 949 if_t ifp = na->ifp; 950 struct netmap_ring *ring = kring->ring; 951 u_int nm_i; /* index into the netmap kring */ 952 u_int nic_i; /* index into the NIC ring */ 953 u_int n; 954 u_int const lim = kring->nkr_num_slots - 1; 955 u_int const head = kring->rhead; 956 struct if_pkt_info pi; 957 958 /* 959 * interrupts on every tx packet are expensive so request 960 * them every half ring, or where NS_REPORT is set 961 */ 962 u_int report_frequency = kring->nkr_num_slots >> 1; 963 /* device-specific */ 964 if_ctx_t ctx = ifp->if_softc; 965 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 966 967 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 968 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 969 970 /* 971 * First part: process new packets to send. 972 * nm_i is the current index in the netmap kring, 973 * nic_i is the corresponding index in the NIC ring. 974 * 975 * If we have packets to send (nm_i != head) 976 * iterate over the netmap ring, fetch length and update 977 * the corresponding slot in the NIC ring. Some drivers also 978 * need to update the buffer's physical address in the NIC slot 979 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 980 * 981 * The netmap_reload_map() calls is especially expensive, 982 * even when (as in this case) the tag is 0, so do only 983 * when the buffer has actually changed. 984 * 985 * If possible do not set the report/intr bit on all slots, 986 * but only a few times per ring or when NS_REPORT is set. 987 * 988 * Finally, on 10G and faster drivers, it might be useful 989 * to prefetch the next slot and txr entry. 990 */ 991 992 nm_i = kring->nr_hwcur; 993 if (nm_i != head) { /* we have new packets to send */ 994 pkt_info_zero(&pi); 995 pi.ipi_segs = txq->ift_segs; 996 pi.ipi_qsidx = kring->ring_id; 997 nic_i = netmap_idx_k2n(kring, nm_i); 998 999 __builtin_prefetch(&ring->slot[nm_i]); 1000 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 1001 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 1002 1003 for (n = 0; nm_i != head; n++) { 1004 struct netmap_slot *slot = &ring->slot[nm_i]; 1005 u_int len = slot->len; 1006 uint64_t paddr; 1007 void *addr = PNMB(na, slot, &paddr); 1008 int flags = (slot->flags & NS_REPORT || 1009 nic_i == 0 || nic_i == report_frequency) ? 1010 IPI_TX_INTR : 0; 1011 1012 /* device-specific */ 1013 pi.ipi_len = len; 1014 pi.ipi_segs[0].ds_addr = paddr; 1015 pi.ipi_segs[0].ds_len = len; 1016 pi.ipi_nsegs = 1; 1017 pi.ipi_ndescs = 0; 1018 pi.ipi_pidx = nic_i; 1019 pi.ipi_flags = flags; 1020 1021 /* Fill the slot in the NIC ring. */ 1022 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1023 DBG_COUNTER_INC(tx_encap); 1024 1025 /* prefetch for next round */ 1026 __builtin_prefetch(&ring->slot[nm_i + 1]); 1027 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1028 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1029 1030 NM_CHECK_ADDR_LEN(na, addr, len); 1031 1032 if (slot->flags & NS_BUF_CHANGED) { 1033 /* buffer has changed, reload map */ 1034 netmap_reload_map(na, txq->ift_buf_tag, 1035 txq->ift_sds.ifsd_map[nic_i], addr); 1036 } 1037 /* make sure changes to the buffer are synced */ 1038 bus_dmamap_sync(txq->ift_buf_tag, 1039 txq->ift_sds.ifsd_map[nic_i], 1040 BUS_DMASYNC_PREWRITE); 1041 1042 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1043 nm_i = nm_next(nm_i, lim); 1044 nic_i = nm_next(nic_i, lim); 1045 } 1046 kring->nr_hwcur = nm_i; 1047 1048 /* synchronize the NIC ring */ 1049 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1050 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1051 1052 /* (re)start the tx unit up to slot nic_i (excluded) */ 1053 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1054 } 1055 1056 /* 1057 * Second part: reclaim buffers for completed transmissions. 1058 * 1059 * If there are unclaimed buffers, attempt to reclaim them. 1060 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1061 * trigger a per-tx-queue timer to try again later. 1062 */ 1063 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1064 if (iflib_tx_credits_update(ctx, txq)) { 1065 /* some tx completed, increment avail */ 1066 nic_i = txq->ift_cidx_processed; 1067 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1068 } 1069 } 1070 1071 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1072 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1073 callout_reset_sbt_on(&txq->ift_netmap_timer, 1074 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1075 iflib_netmap_timer, txq, 1076 txq->ift_netmap_timer.c_cpu, 0); 1077 } 1078 return (0); 1079 } 1080 1081 /* 1082 * Reconcile kernel and user view of the receive ring. 1083 * Same as for the txsync, this routine must be efficient. 1084 * The caller guarantees a single invocations, but races against 1085 * the rest of the driver should be handled here. 1086 * 1087 * On call, kring->rhead is the first packet that userspace wants 1088 * to keep, and kring->rcur is the wakeup point. 1089 * The kernel has previously reported packets up to kring->rtail. 1090 * 1091 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1092 * of whether or not we received an interrupt. 1093 */ 1094 static int 1095 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1096 { 1097 struct netmap_adapter *na = kring->na; 1098 struct netmap_ring *ring = kring->ring; 1099 if_t ifp = na->ifp; 1100 uint32_t nm_i; /* index into the netmap ring */ 1101 uint32_t nic_i; /* index into the NIC ring */ 1102 u_int n; 1103 u_int const lim = kring->nkr_num_slots - 1; 1104 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1105 1106 if_ctx_t ctx = ifp->if_softc; 1107 if_shared_ctx_t sctx = ctx->ifc_sctx; 1108 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1109 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1110 iflib_fl_t fl = &rxq->ifr_fl[0]; 1111 struct if_rxd_info ri; 1112 qidx_t *cidxp; 1113 1114 /* 1115 * netmap only uses free list 0, to avoid out of order consumption 1116 * of receive buffers 1117 */ 1118 1119 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1120 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1121 1122 /* 1123 * First part: import newly received packets. 1124 * 1125 * nm_i is the index of the next free slot in the netmap ring, 1126 * nic_i is the index of the next received packet in the NIC ring 1127 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1128 * differ in case if_init() has been called while 1129 * in netmap mode. For the receive ring we have 1130 * 1131 * nic_i = fl->ifl_cidx; 1132 * nm_i = kring->nr_hwtail (previous) 1133 * and 1134 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1135 * 1136 * fl->ifl_cidx is set to 0 on a ring reinit 1137 */ 1138 if (netmap_no_pendintr || force_update) { 1139 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1140 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1141 int crclen = iflib_crcstrip ? 0 : 4; 1142 int error, avail; 1143 1144 /* 1145 * For the free list consumer index, we use the same 1146 * logic as in iflib_rxeof(). 1147 */ 1148 if (have_rxcq) 1149 cidxp = &rxq->ifr_cq_cidx; 1150 else 1151 cidxp = &fl->ifl_cidx; 1152 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1153 rxq->ifr_id, *cidxp, USHRT_MAX); 1154 1155 nic_i = fl->ifl_cidx; 1156 nm_i = netmap_idx_n2k(kring, nic_i); 1157 MPASS(nm_i == kring->nr_hwtail); 1158 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1159 rxd_info_zero(&ri); 1160 ri.iri_frags = rxq->ifr_frags; 1161 ri.iri_qsidx = kring->ring_id; 1162 ri.iri_ifp = ctx->ifc_ifp; 1163 ri.iri_cidx = *cidxp; 1164 1165 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1166 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1167 ring->slot[nm_i].flags = 0; 1168 if (have_rxcq) { 1169 *cidxp = ri.iri_cidx; 1170 while (*cidxp >= scctx->isc_nrxd[0]) 1171 *cidxp -= scctx->isc_nrxd[0]; 1172 } 1173 bus_dmamap_sync(fl->ifl_buf_tag, 1174 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1175 nm_i = nm_next(nm_i, lim); 1176 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1177 } 1178 if (n) { /* update the state variables */ 1179 if (netmap_no_pendintr && !force_update) { 1180 /* diagnostics */ 1181 iflib_rx_miss ++; 1182 iflib_rx_miss_bufs += n; 1183 } 1184 kring->nr_hwtail = nm_i; 1185 } 1186 kring->nr_kflags &= ~NKR_PENDINTR; 1187 } 1188 /* 1189 * Second part: skip past packets that userspace has released. 1190 * (kring->nr_hwcur to head excluded), 1191 * and make the buffers available for reception. 1192 * As usual nm_i is the index in the netmap ring, 1193 * nic_i is the index in the NIC ring, and 1194 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1195 */ 1196 netmap_fl_refill(rxq, kring, false); 1197 1198 return (0); 1199 } 1200 1201 static void 1202 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1203 { 1204 if_ctx_t ctx = na->ifp->if_softc; 1205 1206 CTX_LOCK(ctx); 1207 if (onoff) { 1208 IFDI_INTR_ENABLE(ctx); 1209 } else { 1210 IFDI_INTR_DISABLE(ctx); 1211 } 1212 CTX_UNLOCK(ctx); 1213 } 1214 1215 static int 1216 iflib_netmap_attach(if_ctx_t ctx) 1217 { 1218 struct netmap_adapter na; 1219 1220 bzero(&na, sizeof(na)); 1221 1222 na.ifp = ctx->ifc_ifp; 1223 na.na_flags = NAF_BDG_MAYSLEEP; 1224 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1225 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1226 1227 na.num_tx_desc = iflib_num_tx_descs(ctx); 1228 na.num_rx_desc = iflib_num_rx_descs(ctx); 1229 na.nm_txsync = iflib_netmap_txsync; 1230 na.nm_rxsync = iflib_netmap_rxsync; 1231 na.nm_register = iflib_netmap_register; 1232 na.nm_intr = iflib_netmap_intr; 1233 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1234 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1235 return (netmap_attach(&na)); 1236 } 1237 1238 static int 1239 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1240 { 1241 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1242 struct netmap_slot *slot; 1243 1244 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1245 if (slot == NULL) 1246 return (0); 1247 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1248 /* 1249 * In netmap mode, set the map for the packet buffer. 1250 * NOTE: Some drivers (not this one) also need to set 1251 * the physical buffer address in the NIC ring. 1252 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1253 * netmap slot index, si 1254 */ 1255 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1256 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1257 NMB(na, slot + si)); 1258 } 1259 return (1); 1260 } 1261 1262 static int 1263 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1264 { 1265 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1266 struct netmap_kring *kring; 1267 struct netmap_slot *slot; 1268 1269 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1270 if (slot == NULL) 1271 return (0); 1272 kring = na->rx_rings[rxq->ifr_id]; 1273 netmap_fl_refill(rxq, kring, true); 1274 return (1); 1275 } 1276 1277 static void 1278 iflib_netmap_timer(void *arg) 1279 { 1280 iflib_txq_t txq = arg; 1281 if_ctx_t ctx = txq->ift_ctx; 1282 1283 /* 1284 * Wake up the netmap application, to give it a chance to 1285 * call txsync and reclaim more completed TX buffers. 1286 */ 1287 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1288 } 1289 1290 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1291 1292 #else 1293 #define iflib_netmap_txq_init(ctx, txq) (0) 1294 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1295 #define iflib_netmap_detach(ifp) 1296 #define netmap_enable_all_rings(ifp) 1297 #define netmap_disable_all_rings(ifp) 1298 1299 #define iflib_netmap_attach(ctx) (0) 1300 #define netmap_rx_irq(ifp, qid, budget) (0) 1301 #endif 1302 1303 #if defined(__i386__) || defined(__amd64__) 1304 static __inline void 1305 prefetch(void *x) 1306 { 1307 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1308 } 1309 static __inline void 1310 prefetch2cachelines(void *x) 1311 { 1312 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1313 #if (CACHE_LINE_SIZE < 128) 1314 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1315 #endif 1316 } 1317 #else 1318 #define prefetch(x) 1319 #define prefetch2cachelines(x) 1320 #endif 1321 1322 static void 1323 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1324 { 1325 iflib_fl_t fl; 1326 1327 fl = &rxq->ifr_fl[flid]; 1328 iru->iru_paddrs = fl->ifl_bus_addrs; 1329 iru->iru_idxs = fl->ifl_rxd_idxs; 1330 iru->iru_qsidx = rxq->ifr_id; 1331 iru->iru_buf_size = fl->ifl_buf_size; 1332 iru->iru_flidx = fl->ifl_id; 1333 } 1334 1335 static void 1336 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1337 { 1338 if (err) 1339 return; 1340 *(bus_addr_t *) arg = segs[0].ds_addr; 1341 } 1342 1343 int 1344 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1345 { 1346 int err; 1347 device_t dev = ctx->ifc_dev; 1348 1349 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1350 align, 0, /* alignment, bounds */ 1351 BUS_SPACE_MAXADDR, /* lowaddr */ 1352 BUS_SPACE_MAXADDR, /* highaddr */ 1353 NULL, NULL, /* filter, filterarg */ 1354 size, /* maxsize */ 1355 1, /* nsegments */ 1356 size, /* maxsegsize */ 1357 BUS_DMA_ALLOCNOW, /* flags */ 1358 NULL, /* lockfunc */ 1359 NULL, /* lockarg */ 1360 &dma->idi_tag); 1361 if (err) { 1362 device_printf(dev, 1363 "%s: bus_dma_tag_create failed: %d\n", 1364 __func__, err); 1365 goto fail_0; 1366 } 1367 1368 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1369 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1370 if (err) { 1371 device_printf(dev, 1372 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1373 __func__, (uintmax_t)size, err); 1374 goto fail_1; 1375 } 1376 1377 dma->idi_paddr = IF_BAD_DMA; 1378 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1379 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1380 if (err || dma->idi_paddr == IF_BAD_DMA) { 1381 device_printf(dev, 1382 "%s: bus_dmamap_load failed: %d\n", 1383 __func__, err); 1384 goto fail_2; 1385 } 1386 1387 dma->idi_size = size; 1388 return (0); 1389 1390 fail_2: 1391 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1392 fail_1: 1393 bus_dma_tag_destroy(dma->idi_tag); 1394 fail_0: 1395 dma->idi_tag = NULL; 1396 1397 return (err); 1398 } 1399 1400 int 1401 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1402 { 1403 if_shared_ctx_t sctx = ctx->ifc_sctx; 1404 1405 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1406 1407 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1408 } 1409 1410 int 1411 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1412 { 1413 int i, err; 1414 iflib_dma_info_t *dmaiter; 1415 1416 dmaiter = dmalist; 1417 for (i = 0; i < count; i++, dmaiter++) { 1418 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1419 break; 1420 } 1421 if (err) 1422 iflib_dma_free_multi(dmalist, i); 1423 return (err); 1424 } 1425 1426 void 1427 iflib_dma_free(iflib_dma_info_t dma) 1428 { 1429 if (dma->idi_tag == NULL) 1430 return; 1431 if (dma->idi_paddr != IF_BAD_DMA) { 1432 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1433 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1434 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1435 dma->idi_paddr = IF_BAD_DMA; 1436 } 1437 if (dma->idi_vaddr != NULL) { 1438 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1439 dma->idi_vaddr = NULL; 1440 } 1441 bus_dma_tag_destroy(dma->idi_tag); 1442 dma->idi_tag = NULL; 1443 } 1444 1445 void 1446 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1447 { 1448 int i; 1449 iflib_dma_info_t *dmaiter = dmalist; 1450 1451 for (i = 0; i < count; i++, dmaiter++) 1452 iflib_dma_free(*dmaiter); 1453 } 1454 1455 static int 1456 iflib_fast_intr(void *arg) 1457 { 1458 iflib_filter_info_t info = arg; 1459 struct grouptask *gtask = info->ifi_task; 1460 int result; 1461 1462 DBG_COUNTER_INC(fast_intrs); 1463 if (info->ifi_filter != NULL) { 1464 result = info->ifi_filter(info->ifi_filter_arg); 1465 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1466 return (result); 1467 } 1468 1469 GROUPTASK_ENQUEUE(gtask); 1470 return (FILTER_HANDLED); 1471 } 1472 1473 static int 1474 iflib_fast_intr_rxtx(void *arg) 1475 { 1476 iflib_filter_info_t info = arg; 1477 struct grouptask *gtask = info->ifi_task; 1478 if_ctx_t ctx; 1479 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1480 iflib_txq_t txq; 1481 void *sc; 1482 int i, cidx, result; 1483 qidx_t txqid; 1484 bool intr_enable, intr_legacy; 1485 1486 DBG_COUNTER_INC(fast_intrs); 1487 if (info->ifi_filter != NULL) { 1488 result = info->ifi_filter(info->ifi_filter_arg); 1489 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1490 return (result); 1491 } 1492 1493 ctx = rxq->ifr_ctx; 1494 sc = ctx->ifc_softc; 1495 intr_enable = false; 1496 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1497 MPASS(rxq->ifr_ntxqirq); 1498 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1499 txqid = rxq->ifr_txqid[i]; 1500 txq = &ctx->ifc_txqs[txqid]; 1501 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1502 BUS_DMASYNC_POSTREAD); 1503 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1504 if (intr_legacy) 1505 intr_enable = true; 1506 else 1507 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1508 continue; 1509 } 1510 GROUPTASK_ENQUEUE(&txq->ift_task); 1511 } 1512 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1513 cidx = rxq->ifr_cq_cidx; 1514 else 1515 cidx = rxq->ifr_fl[0].ifl_cidx; 1516 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1517 GROUPTASK_ENQUEUE(gtask); 1518 else { 1519 if (intr_legacy) 1520 intr_enable = true; 1521 else 1522 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1523 DBG_COUNTER_INC(rx_intr_enables); 1524 } 1525 if (intr_enable) 1526 IFDI_INTR_ENABLE(ctx); 1527 return (FILTER_HANDLED); 1528 } 1529 1530 static int 1531 iflib_fast_intr_ctx(void *arg) 1532 { 1533 iflib_filter_info_t info = arg; 1534 struct grouptask *gtask = info->ifi_task; 1535 int result; 1536 1537 DBG_COUNTER_INC(fast_intrs); 1538 if (info->ifi_filter != NULL) { 1539 result = info->ifi_filter(info->ifi_filter_arg); 1540 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1541 return (result); 1542 } 1543 1544 GROUPTASK_ENQUEUE(gtask); 1545 return (FILTER_HANDLED); 1546 } 1547 1548 static int 1549 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1550 driver_filter_t filter, driver_intr_t handler, void *arg, 1551 const char *name) 1552 { 1553 struct resource *res; 1554 void *tag = NULL; 1555 device_t dev = ctx->ifc_dev; 1556 int flags, i, rc; 1557 1558 flags = RF_ACTIVE; 1559 if (ctx->ifc_flags & IFC_LEGACY) 1560 flags |= RF_SHAREABLE; 1561 MPASS(rid < 512); 1562 i = rid; 1563 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1564 if (res == NULL) { 1565 device_printf(dev, 1566 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1567 return (ENOMEM); 1568 } 1569 irq->ii_res = res; 1570 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1571 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1572 filter, handler, arg, &tag); 1573 if (rc != 0) { 1574 device_printf(dev, 1575 "failed to setup interrupt for rid %d, name %s: %d\n", 1576 rid, name ? name : "unknown", rc); 1577 return (rc); 1578 } else if (name) 1579 bus_describe_intr(dev, res, tag, "%s", name); 1580 1581 irq->ii_tag = tag; 1582 return (0); 1583 } 1584 1585 /********************************************************************* 1586 * 1587 * Allocate DMA resources for TX buffers as well as memory for the TX 1588 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1589 * iflib_sw_tx_desc_array structure, storing all the information that 1590 * is needed to transmit a packet on the wire. This is called only 1591 * once at attach, setup is done every reset. 1592 * 1593 **********************************************************************/ 1594 static int 1595 iflib_txsd_alloc(iflib_txq_t txq) 1596 { 1597 if_ctx_t ctx = txq->ift_ctx; 1598 if_shared_ctx_t sctx = ctx->ifc_sctx; 1599 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1600 device_t dev = ctx->ifc_dev; 1601 bus_size_t tsomaxsize; 1602 int err, nsegments, ntsosegments; 1603 bool tso; 1604 1605 nsegments = scctx->isc_tx_nsegments; 1606 ntsosegments = scctx->isc_tx_tso_segments_max; 1607 tsomaxsize = scctx->isc_tx_tso_size_max; 1608 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1609 tsomaxsize += sizeof(struct ether_vlan_header); 1610 MPASS(scctx->isc_ntxd[0] > 0); 1611 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1612 MPASS(nsegments > 0); 1613 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1614 MPASS(ntsosegments > 0); 1615 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1616 } 1617 1618 /* 1619 * Set up DMA tags for TX buffers. 1620 */ 1621 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1622 1, 0, /* alignment, bounds */ 1623 BUS_SPACE_MAXADDR, /* lowaddr */ 1624 BUS_SPACE_MAXADDR, /* highaddr */ 1625 NULL, NULL, /* filter, filterarg */ 1626 sctx->isc_tx_maxsize, /* maxsize */ 1627 nsegments, /* nsegments */ 1628 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1629 0, /* flags */ 1630 NULL, /* lockfunc */ 1631 NULL, /* lockfuncarg */ 1632 &txq->ift_buf_tag))) { 1633 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1634 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1635 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1636 goto fail; 1637 } 1638 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1639 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1640 1, 0, /* alignment, bounds */ 1641 BUS_SPACE_MAXADDR, /* lowaddr */ 1642 BUS_SPACE_MAXADDR, /* highaddr */ 1643 NULL, NULL, /* filter, filterarg */ 1644 tsomaxsize, /* maxsize */ 1645 ntsosegments, /* nsegments */ 1646 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1647 0, /* flags */ 1648 NULL, /* lockfunc */ 1649 NULL, /* lockfuncarg */ 1650 &txq->ift_tso_buf_tag))) { 1651 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1652 err); 1653 goto fail; 1654 } 1655 1656 /* Allocate memory for the TX mbuf map. */ 1657 if (!(txq->ift_sds.ifsd_m = 1658 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1659 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1660 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1661 err = ENOMEM; 1662 goto fail; 1663 } 1664 1665 /* 1666 * Create the DMA maps for TX buffers. 1667 */ 1668 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1669 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1670 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1671 device_printf(dev, 1672 "Unable to allocate TX buffer DMA map memory\n"); 1673 err = ENOMEM; 1674 goto fail; 1675 } 1676 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1677 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1678 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1679 device_printf(dev, 1680 "Unable to allocate TSO TX buffer map memory\n"); 1681 err = ENOMEM; 1682 goto fail; 1683 } 1684 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1685 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1686 &txq->ift_sds.ifsd_map[i]); 1687 if (err != 0) { 1688 device_printf(dev, "Unable to create TX DMA map\n"); 1689 goto fail; 1690 } 1691 if (!tso) 1692 continue; 1693 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1694 &txq->ift_sds.ifsd_tso_map[i]); 1695 if (err != 0) { 1696 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1697 goto fail; 1698 } 1699 } 1700 return (0); 1701 fail: 1702 /* We free all, it handles case where we are in the middle */ 1703 iflib_tx_structures_free(ctx); 1704 return (err); 1705 } 1706 1707 static void 1708 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1709 { 1710 bus_dmamap_t map; 1711 1712 if (txq->ift_sds.ifsd_map != NULL) { 1713 map = txq->ift_sds.ifsd_map[i]; 1714 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1715 bus_dmamap_unload(txq->ift_buf_tag, map); 1716 bus_dmamap_destroy(txq->ift_buf_tag, map); 1717 txq->ift_sds.ifsd_map[i] = NULL; 1718 } 1719 1720 if (txq->ift_sds.ifsd_tso_map != NULL) { 1721 map = txq->ift_sds.ifsd_tso_map[i]; 1722 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1723 BUS_DMASYNC_POSTWRITE); 1724 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1725 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1726 txq->ift_sds.ifsd_tso_map[i] = NULL; 1727 } 1728 } 1729 1730 static void 1731 iflib_txq_destroy(iflib_txq_t txq) 1732 { 1733 if_ctx_t ctx = txq->ift_ctx; 1734 1735 for (int i = 0; i < txq->ift_size; i++) 1736 iflib_txsd_destroy(ctx, txq, i); 1737 1738 if (txq->ift_br != NULL) { 1739 ifmp_ring_free(txq->ift_br); 1740 txq->ift_br = NULL; 1741 } 1742 1743 mtx_destroy(&txq->ift_mtx); 1744 1745 if (txq->ift_sds.ifsd_map != NULL) { 1746 free(txq->ift_sds.ifsd_map, M_IFLIB); 1747 txq->ift_sds.ifsd_map = NULL; 1748 } 1749 if (txq->ift_sds.ifsd_tso_map != NULL) { 1750 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1751 txq->ift_sds.ifsd_tso_map = NULL; 1752 } 1753 if (txq->ift_sds.ifsd_m != NULL) { 1754 free(txq->ift_sds.ifsd_m, M_IFLIB); 1755 txq->ift_sds.ifsd_m = NULL; 1756 } 1757 if (txq->ift_buf_tag != NULL) { 1758 bus_dma_tag_destroy(txq->ift_buf_tag); 1759 txq->ift_buf_tag = NULL; 1760 } 1761 if (txq->ift_tso_buf_tag != NULL) { 1762 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1763 txq->ift_tso_buf_tag = NULL; 1764 } 1765 if (txq->ift_ifdi != NULL) { 1766 free(txq->ift_ifdi, M_IFLIB); 1767 } 1768 } 1769 1770 static void 1771 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1772 { 1773 struct mbuf **mp; 1774 1775 mp = &txq->ift_sds.ifsd_m[i]; 1776 if (*mp == NULL) 1777 return; 1778 1779 if (txq->ift_sds.ifsd_map != NULL) { 1780 bus_dmamap_sync(txq->ift_buf_tag, 1781 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1782 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1783 } 1784 if (txq->ift_sds.ifsd_tso_map != NULL) { 1785 bus_dmamap_sync(txq->ift_tso_buf_tag, 1786 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1787 bus_dmamap_unload(txq->ift_tso_buf_tag, 1788 txq->ift_sds.ifsd_tso_map[i]); 1789 } 1790 m_freem(*mp); 1791 DBG_COUNTER_INC(tx_frees); 1792 *mp = NULL; 1793 } 1794 1795 static int 1796 iflib_txq_setup(iflib_txq_t txq) 1797 { 1798 if_ctx_t ctx = txq->ift_ctx; 1799 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1800 if_shared_ctx_t sctx = ctx->ifc_sctx; 1801 iflib_dma_info_t di; 1802 int i; 1803 1804 /* Set number of descriptors available */ 1805 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1806 /* XXX make configurable */ 1807 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1808 1809 /* Reset indices */ 1810 txq->ift_cidx_processed = 0; 1811 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1812 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1813 1814 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1815 bzero((void *)di->idi_vaddr, di->idi_size); 1816 1817 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1818 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1819 bus_dmamap_sync(di->idi_tag, di->idi_map, 1820 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1821 return (0); 1822 } 1823 1824 /********************************************************************* 1825 * 1826 * Allocate DMA resources for RX buffers as well as memory for the RX 1827 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1828 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1829 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1830 * Since we use use one entry in iflib_sw_rx_desc_array per received 1831 * packet, the maximum number of entries we'll need is equal to the 1832 * number of hardware receive descriptors that we've allocated. 1833 * 1834 **********************************************************************/ 1835 static int 1836 iflib_rxsd_alloc(iflib_rxq_t rxq) 1837 { 1838 if_ctx_t ctx = rxq->ifr_ctx; 1839 if_shared_ctx_t sctx = ctx->ifc_sctx; 1840 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1841 device_t dev = ctx->ifc_dev; 1842 iflib_fl_t fl; 1843 int err; 1844 1845 MPASS(scctx->isc_nrxd[0] > 0); 1846 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1847 1848 fl = rxq->ifr_fl; 1849 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1850 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1851 /* Set up DMA tag for RX buffers. */ 1852 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1853 1, 0, /* alignment, bounds */ 1854 BUS_SPACE_MAXADDR, /* lowaddr */ 1855 BUS_SPACE_MAXADDR, /* highaddr */ 1856 NULL, NULL, /* filter, filterarg */ 1857 sctx->isc_rx_maxsize, /* maxsize */ 1858 sctx->isc_rx_nsegments, /* nsegments */ 1859 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1860 0, /* flags */ 1861 NULL, /* lockfunc */ 1862 NULL, /* lockarg */ 1863 &fl->ifl_buf_tag); 1864 if (err) { 1865 device_printf(dev, 1866 "Unable to allocate RX DMA tag: %d\n", err); 1867 goto fail; 1868 } 1869 1870 /* Allocate memory for the RX mbuf map. */ 1871 if (!(fl->ifl_sds.ifsd_m = 1872 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1873 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1874 device_printf(dev, 1875 "Unable to allocate RX mbuf map memory\n"); 1876 err = ENOMEM; 1877 goto fail; 1878 } 1879 1880 /* Allocate memory for the direct RX cluster pointer map. */ 1881 if (!(fl->ifl_sds.ifsd_cl = 1882 (caddr_t *) malloc(sizeof(caddr_t) * 1883 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1884 device_printf(dev, 1885 "Unable to allocate RX cluster map memory\n"); 1886 err = ENOMEM; 1887 goto fail; 1888 } 1889 1890 /* Allocate memory for the RX cluster bus address map. */ 1891 if (!(fl->ifl_sds.ifsd_ba = 1892 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1893 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1894 device_printf(dev, 1895 "Unable to allocate RX bus address map memory\n"); 1896 err = ENOMEM; 1897 goto fail; 1898 } 1899 1900 /* 1901 * Create the DMA maps for RX buffers. 1902 */ 1903 if (!(fl->ifl_sds.ifsd_map = 1904 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1905 device_printf(dev, 1906 "Unable to allocate RX buffer DMA map memory\n"); 1907 err = ENOMEM; 1908 goto fail; 1909 } 1910 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1911 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1912 &fl->ifl_sds.ifsd_map[i]); 1913 if (err != 0) { 1914 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1915 goto fail; 1916 } 1917 } 1918 } 1919 return (0); 1920 1921 fail: 1922 iflib_rx_structures_free(ctx); 1923 return (err); 1924 } 1925 1926 /* 1927 * Internal service routines 1928 */ 1929 1930 struct rxq_refill_cb_arg { 1931 int error; 1932 bus_dma_segment_t seg; 1933 int nseg; 1934 }; 1935 1936 static void 1937 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1938 { 1939 struct rxq_refill_cb_arg *cb_arg = arg; 1940 1941 cb_arg->error = error; 1942 cb_arg->seg = segs[0]; 1943 cb_arg->nseg = nseg; 1944 } 1945 1946 /** 1947 * iflib_fl_refill - refill an rxq free-buffer list 1948 * @ctx: the iflib context 1949 * @fl: the free list to refill 1950 * @count: the number of new buffers to allocate 1951 * 1952 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 1953 * The caller must assure that @count does not exceed the queue's capacity 1954 * minus one (since we always leave a descriptor unavailable). 1955 */ 1956 static uint8_t 1957 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1958 { 1959 struct if_rxd_update iru; 1960 struct rxq_refill_cb_arg cb_arg; 1961 struct mbuf *m; 1962 caddr_t cl, *sd_cl; 1963 struct mbuf **sd_m; 1964 bus_dmamap_t *sd_map; 1965 bus_addr_t bus_addr, *sd_ba; 1966 int err, frag_idx, i, idx, n, pidx; 1967 qidx_t credits; 1968 1969 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 1970 1971 sd_m = fl->ifl_sds.ifsd_m; 1972 sd_map = fl->ifl_sds.ifsd_map; 1973 sd_cl = fl->ifl_sds.ifsd_cl; 1974 sd_ba = fl->ifl_sds.ifsd_ba; 1975 pidx = fl->ifl_pidx; 1976 idx = pidx; 1977 frag_idx = fl->ifl_fragidx; 1978 credits = fl->ifl_credits; 1979 1980 i = 0; 1981 n = count; 1982 MPASS(n > 0); 1983 MPASS(credits + n <= fl->ifl_size); 1984 1985 if (pidx < fl->ifl_cidx) 1986 MPASS(pidx + n <= fl->ifl_cidx); 1987 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1988 MPASS(fl->ifl_gen == 0); 1989 if (pidx > fl->ifl_cidx) 1990 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1991 1992 DBG_COUNTER_INC(fl_refills); 1993 if (n > 8) 1994 DBG_COUNTER_INC(fl_refills_large); 1995 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1996 while (n-- > 0) { 1997 /* 1998 * We allocate an uninitialized mbuf + cluster, mbuf is 1999 * initialized after rx. 2000 * 2001 * If the cluster is still set then we know a minimum sized 2002 * packet was received 2003 */ 2004 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2005 &frag_idx); 2006 if (frag_idx < 0) 2007 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2008 MPASS(frag_idx >= 0); 2009 if ((cl = sd_cl[frag_idx]) == NULL) { 2010 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2011 if (__predict_false(cl == NULL)) 2012 break; 2013 2014 cb_arg.error = 0; 2015 MPASS(sd_map != NULL); 2016 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2017 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2018 BUS_DMA_NOWAIT); 2019 if (__predict_false(err != 0 || cb_arg.error)) { 2020 uma_zfree(fl->ifl_zone, cl); 2021 break; 2022 } 2023 2024 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2025 sd_cl[frag_idx] = cl; 2026 #if MEMORY_LOGGING 2027 fl->ifl_cl_enqueued++; 2028 #endif 2029 } else { 2030 bus_addr = sd_ba[frag_idx]; 2031 } 2032 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2033 BUS_DMASYNC_PREREAD); 2034 2035 if (sd_m[frag_idx] == NULL) { 2036 m = m_gethdr(M_NOWAIT, MT_NOINIT); 2037 if (__predict_false(m == NULL)) 2038 break; 2039 sd_m[frag_idx] = m; 2040 } 2041 bit_set(fl->ifl_rx_bitmap, frag_idx); 2042 #if MEMORY_LOGGING 2043 fl->ifl_m_enqueued++; 2044 #endif 2045 2046 DBG_COUNTER_INC(rx_allocs); 2047 fl->ifl_rxd_idxs[i] = frag_idx; 2048 fl->ifl_bus_addrs[i] = bus_addr; 2049 credits++; 2050 i++; 2051 MPASS(credits <= fl->ifl_size); 2052 if (++idx == fl->ifl_size) { 2053 #ifdef INVARIANTS 2054 fl->ifl_gen = 1; 2055 #endif 2056 idx = 0; 2057 } 2058 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2059 iru.iru_pidx = pidx; 2060 iru.iru_count = i; 2061 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2062 fl->ifl_pidx = idx; 2063 fl->ifl_credits = credits; 2064 pidx = idx; 2065 i = 0; 2066 } 2067 } 2068 2069 if (n < count - 1) { 2070 if (i != 0) { 2071 iru.iru_pidx = pidx; 2072 iru.iru_count = i; 2073 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2074 fl->ifl_pidx = idx; 2075 fl->ifl_credits = credits; 2076 } 2077 DBG_COUNTER_INC(rxd_flush); 2078 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2079 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2080 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2081 fl->ifl_id, fl->ifl_pidx); 2082 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2083 fl->ifl_fragidx = frag_idx + 1; 2084 if (fl->ifl_fragidx == fl->ifl_size) 2085 fl->ifl_fragidx = 0; 2086 } else { 2087 fl->ifl_fragidx = frag_idx; 2088 } 2089 } 2090 2091 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2092 } 2093 2094 static inline uint8_t 2095 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2096 { 2097 /* 2098 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2099 * This is important as it confuses most NICs. For instance, 2100 * Intel NICs have (per receive ring) RDH and RDT registers, where 2101 * RDH points to the next receive descriptor to be used by the NIC, 2102 * and RDT for the next receive descriptor to be published by the 2103 * driver to the NIC (RDT - 1 is thus the last valid one). 2104 * The condition RDH == RDT means no descriptors are available to 2105 * the NIC, and thus it would be ambiguous if it also meant that 2106 * all the descriptors are available to the NIC. 2107 */ 2108 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2109 #ifdef INVARIANTS 2110 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2111 #endif 2112 2113 MPASS(fl->ifl_credits <= fl->ifl_size); 2114 MPASS(reclaimable == delta); 2115 2116 if (reclaimable > 0) 2117 return (iflib_fl_refill(ctx, fl, reclaimable)); 2118 return (0); 2119 } 2120 2121 uint8_t 2122 iflib_in_detach(if_ctx_t ctx) 2123 { 2124 bool in_detach; 2125 2126 STATE_LOCK(ctx); 2127 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2128 STATE_UNLOCK(ctx); 2129 return (in_detach); 2130 } 2131 2132 static void 2133 iflib_fl_bufs_free(iflib_fl_t fl) 2134 { 2135 iflib_dma_info_t idi = fl->ifl_ifdi; 2136 bus_dmamap_t sd_map; 2137 uint32_t i; 2138 2139 for (i = 0; i < fl->ifl_size; i++) { 2140 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2141 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2142 2143 if (*sd_cl != NULL) { 2144 sd_map = fl->ifl_sds.ifsd_map[i]; 2145 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2146 BUS_DMASYNC_POSTREAD); 2147 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2148 uma_zfree(fl->ifl_zone, *sd_cl); 2149 *sd_cl = NULL; 2150 if (*sd_m != NULL) { 2151 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2152 uma_zfree(zone_mbuf, *sd_m); 2153 *sd_m = NULL; 2154 } 2155 } else { 2156 MPASS(*sd_m == NULL); 2157 } 2158 #if MEMORY_LOGGING 2159 fl->ifl_m_dequeued++; 2160 fl->ifl_cl_dequeued++; 2161 #endif 2162 } 2163 #ifdef INVARIANTS 2164 for (i = 0; i < fl->ifl_size; i++) { 2165 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2166 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2167 } 2168 #endif 2169 /* 2170 * Reset free list values 2171 */ 2172 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2173 bzero(idi->idi_vaddr, idi->idi_size); 2174 } 2175 2176 /********************************************************************* 2177 * 2178 * Initialize a free list and its buffers. 2179 * 2180 **********************************************************************/ 2181 static int 2182 iflib_fl_setup(iflib_fl_t fl) 2183 { 2184 iflib_rxq_t rxq = fl->ifl_rxq; 2185 if_ctx_t ctx = rxq->ifr_ctx; 2186 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2187 int qidx; 2188 2189 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2190 /* 2191 ** Free current RX buffer structs and their mbufs 2192 */ 2193 iflib_fl_bufs_free(fl); 2194 /* Now replenish the mbufs */ 2195 MPASS(fl->ifl_credits == 0); 2196 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2197 if (scctx->isc_rxd_buf_size[qidx] != 0) 2198 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2199 else 2200 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2201 /* 2202 * ifl_buf_size may be a driver-supplied value, so pull it up 2203 * to the selected mbuf size. 2204 */ 2205 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2206 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2207 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2208 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2209 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2210 2211 /* 2212 * Avoid pre-allocating zillions of clusters to an idle card 2213 * potentially speeding up attach. In any case make sure 2214 * to leave a descriptor unavailable. See the comment in 2215 * iflib_fl_refill_all(). 2216 */ 2217 MPASS(fl->ifl_size > 0); 2218 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2219 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2220 return (ENOBUFS); 2221 /* 2222 * handle failure 2223 */ 2224 MPASS(rxq != NULL); 2225 MPASS(fl->ifl_ifdi != NULL); 2226 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2227 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2228 return (0); 2229 } 2230 2231 /********************************************************************* 2232 * 2233 * Free receive ring data structures 2234 * 2235 **********************************************************************/ 2236 static void 2237 iflib_rx_sds_free(iflib_rxq_t rxq) 2238 { 2239 iflib_fl_t fl; 2240 int i, j; 2241 2242 if (rxq->ifr_fl != NULL) { 2243 for (i = 0; i < rxq->ifr_nfl; i++) { 2244 fl = &rxq->ifr_fl[i]; 2245 if (fl->ifl_buf_tag != NULL) { 2246 if (fl->ifl_sds.ifsd_map != NULL) { 2247 for (j = 0; j < fl->ifl_size; j++) { 2248 bus_dmamap_sync( 2249 fl->ifl_buf_tag, 2250 fl->ifl_sds.ifsd_map[j], 2251 BUS_DMASYNC_POSTREAD); 2252 bus_dmamap_unload( 2253 fl->ifl_buf_tag, 2254 fl->ifl_sds.ifsd_map[j]); 2255 bus_dmamap_destroy( 2256 fl->ifl_buf_tag, 2257 fl->ifl_sds.ifsd_map[j]); 2258 } 2259 } 2260 bus_dma_tag_destroy(fl->ifl_buf_tag); 2261 fl->ifl_buf_tag = NULL; 2262 } 2263 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2264 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2265 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2266 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2267 free(fl->ifl_rx_bitmap, M_IFLIB); 2268 fl->ifl_sds.ifsd_m = NULL; 2269 fl->ifl_sds.ifsd_cl = NULL; 2270 fl->ifl_sds.ifsd_ba = NULL; 2271 fl->ifl_sds.ifsd_map = NULL; 2272 fl->ifl_rx_bitmap = NULL; 2273 } 2274 free(rxq->ifr_fl, M_IFLIB); 2275 rxq->ifr_fl = NULL; 2276 free(rxq->ifr_ifdi, M_IFLIB); 2277 rxq->ifr_ifdi = NULL; 2278 rxq->ifr_cq_cidx = 0; 2279 } 2280 } 2281 2282 /* 2283 * Timer routine 2284 */ 2285 static void 2286 iflib_timer(void *arg) 2287 { 2288 iflib_txq_t txq = arg; 2289 if_ctx_t ctx = txq->ift_ctx; 2290 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2291 uint64_t this_tick = ticks; 2292 2293 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2294 return; 2295 2296 /* 2297 ** Check on the state of the TX queue(s), this 2298 ** can be done without the lock because its RO 2299 ** and the HUNG state will be static if set. 2300 */ 2301 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) { 2302 txq->ift_last_timer_tick = this_tick; 2303 IFDI_TIMER(ctx, txq->ift_id); 2304 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2305 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2306 (sctx->isc_pause_frames == 0))) 2307 goto hung; 2308 2309 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2310 ifmp_ring_is_stalled(txq->ift_br)) { 2311 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, 2312 ("queue can't be marked as hung if interface is down")); 2313 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2314 } 2315 txq->ift_cleaned_prev = txq->ift_cleaned; 2316 } 2317 /* handle any laggards */ 2318 if (txq->ift_db_pending) 2319 GROUPTASK_ENQUEUE(&txq->ift_task); 2320 2321 sctx->isc_pause_frames = 0; 2322 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2323 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, 2324 txq, txq->ift_timer.c_cpu); 2325 return; 2326 2327 hung: 2328 device_printf(ctx->ifc_dev, 2329 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2330 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2331 STATE_LOCK(ctx); 2332 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2333 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2334 iflib_admin_intr_deferred(ctx); 2335 STATE_UNLOCK(ctx); 2336 } 2337 2338 static uint16_t 2339 iflib_get_mbuf_size_for(unsigned int size) 2340 { 2341 2342 if (size <= MCLBYTES) 2343 return (MCLBYTES); 2344 else 2345 return (MJUMPAGESIZE); 2346 } 2347 2348 static void 2349 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2350 { 2351 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2352 2353 /* 2354 * XXX don't set the max_frame_size to larger 2355 * than the hardware can handle 2356 */ 2357 ctx->ifc_rx_mbuf_sz = 2358 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2359 } 2360 2361 uint32_t 2362 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2363 { 2364 2365 return (ctx->ifc_rx_mbuf_sz); 2366 } 2367 2368 static void 2369 iflib_init_locked(if_ctx_t ctx) 2370 { 2371 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2372 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2373 if_t ifp = ctx->ifc_ifp; 2374 iflib_fl_t fl; 2375 iflib_txq_t txq; 2376 iflib_rxq_t rxq; 2377 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2378 2379 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2380 IFDI_INTR_DISABLE(ctx); 2381 2382 /* 2383 * See iflib_stop(). Useful in case iflib_init_locked() is 2384 * called without first calling iflib_stop(). 2385 */ 2386 netmap_disable_all_rings(ifp); 2387 2388 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2389 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2390 /* Set hardware offload abilities */ 2391 if_clearhwassist(ifp); 2392 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2393 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2394 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2395 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2396 if (if_getcapenable(ifp) & IFCAP_TSO4) 2397 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2398 if (if_getcapenable(ifp) & IFCAP_TSO6) 2399 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2400 2401 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2402 CALLOUT_LOCK(txq); 2403 callout_stop(&txq->ift_timer); 2404 #ifdef DEV_NETMAP 2405 callout_stop(&txq->ift_netmap_timer); 2406 #endif /* DEV_NETMAP */ 2407 CALLOUT_UNLOCK(txq); 2408 iflib_netmap_txq_init(ctx, txq); 2409 } 2410 2411 /* 2412 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2413 * that drivers can use the value when setting up the hardware receive 2414 * buffers. 2415 */ 2416 iflib_calc_rx_mbuf_sz(ctx); 2417 2418 #ifdef INVARIANTS 2419 i = if_getdrvflags(ifp); 2420 #endif 2421 IFDI_INIT(ctx); 2422 MPASS(if_getdrvflags(ifp) == i); 2423 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2424 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2425 /* This rxq is in netmap mode. Skip normal init. */ 2426 continue; 2427 } 2428 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2429 if (iflib_fl_setup(fl)) { 2430 device_printf(ctx->ifc_dev, 2431 "setting up free list %d failed - " 2432 "check cluster settings\n", j); 2433 goto done; 2434 } 2435 } 2436 } 2437 done: 2438 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2439 IFDI_INTR_ENABLE(ctx); 2440 txq = ctx->ifc_txqs; 2441 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2442 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 2443 txq->ift_timer.c_cpu); 2444 2445 /* Re-enable txsync/rxsync. */ 2446 netmap_enable_all_rings(ifp); 2447 } 2448 2449 static int 2450 iflib_media_change(if_t ifp) 2451 { 2452 if_ctx_t ctx = if_getsoftc(ifp); 2453 int err; 2454 2455 CTX_LOCK(ctx); 2456 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2457 iflib_init_locked(ctx); 2458 CTX_UNLOCK(ctx); 2459 return (err); 2460 } 2461 2462 static void 2463 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2464 { 2465 if_ctx_t ctx = if_getsoftc(ifp); 2466 2467 CTX_LOCK(ctx); 2468 IFDI_UPDATE_ADMIN_STATUS(ctx); 2469 IFDI_MEDIA_STATUS(ctx, ifmr); 2470 CTX_UNLOCK(ctx); 2471 } 2472 2473 void 2474 iflib_stop(if_ctx_t ctx) 2475 { 2476 iflib_txq_t txq = ctx->ifc_txqs; 2477 iflib_rxq_t rxq = ctx->ifc_rxqs; 2478 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2479 if_shared_ctx_t sctx = ctx->ifc_sctx; 2480 iflib_dma_info_t di; 2481 iflib_fl_t fl; 2482 int i, j; 2483 2484 /* Tell the stack that the interface is no longer active */ 2485 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2486 2487 IFDI_INTR_DISABLE(ctx); 2488 DELAY(1000); 2489 IFDI_STOP(ctx); 2490 DELAY(1000); 2491 2492 /* 2493 * Stop any pending txsync/rxsync and prevent new ones 2494 * form starting. Processes blocked in poll() will get 2495 * POLLERR. 2496 */ 2497 netmap_disable_all_rings(ctx->ifc_ifp); 2498 2499 iflib_debug_reset(); 2500 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2501 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2502 /* make sure all transmitters have completed before proceeding XXX */ 2503 2504 CALLOUT_LOCK(txq); 2505 callout_stop(&txq->ift_timer); 2506 #ifdef DEV_NETMAP 2507 callout_stop(&txq->ift_netmap_timer); 2508 #endif /* DEV_NETMAP */ 2509 CALLOUT_UNLOCK(txq); 2510 2511 /* clean any enqueued buffers */ 2512 iflib_ifmp_purge(txq); 2513 /* Free any existing tx buffers. */ 2514 for (j = 0; j < txq->ift_size; j++) { 2515 iflib_txsd_free(ctx, txq, j); 2516 } 2517 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2518 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2519 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2520 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2521 txq->ift_pullups = 0; 2522 ifmp_ring_reset_stats(txq->ift_br); 2523 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2524 bzero((void *)di->idi_vaddr, di->idi_size); 2525 } 2526 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2527 /* make sure all transmitters have completed before proceeding XXX */ 2528 2529 rxq->ifr_cq_cidx = 0; 2530 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2531 bzero((void *)di->idi_vaddr, di->idi_size); 2532 /* also resets the free lists pidx/cidx */ 2533 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2534 iflib_fl_bufs_free(fl); 2535 } 2536 } 2537 2538 static inline caddr_t 2539 calc_next_rxd(iflib_fl_t fl, int cidx) 2540 { 2541 qidx_t size; 2542 int nrxd; 2543 caddr_t start, end, cur, next; 2544 2545 nrxd = fl->ifl_size; 2546 size = fl->ifl_rxd_size; 2547 start = fl->ifl_ifdi->idi_vaddr; 2548 2549 if (__predict_false(size == 0)) 2550 return (start); 2551 cur = start + size*cidx; 2552 end = start + size*nrxd; 2553 next = CACHE_PTR_NEXT(cur); 2554 return (next < end ? next : start); 2555 } 2556 2557 static inline void 2558 prefetch_pkts(iflib_fl_t fl, int cidx) 2559 { 2560 int nextptr; 2561 int nrxd = fl->ifl_size; 2562 caddr_t next_rxd; 2563 2564 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2565 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2566 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2567 next_rxd = calc_next_rxd(fl, cidx); 2568 prefetch(next_rxd); 2569 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2570 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2571 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2572 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2573 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2574 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2575 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2576 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2577 } 2578 2579 static struct mbuf * 2580 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2581 int *pf_rv, if_rxd_info_t ri) 2582 { 2583 bus_dmamap_t map; 2584 iflib_fl_t fl; 2585 caddr_t payload; 2586 struct mbuf *m; 2587 int flid, cidx, len, next; 2588 2589 map = NULL; 2590 flid = irf->irf_flid; 2591 cidx = irf->irf_idx; 2592 fl = &rxq->ifr_fl[flid]; 2593 sd->ifsd_fl = fl; 2594 m = fl->ifl_sds.ifsd_m[cidx]; 2595 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2596 fl->ifl_credits--; 2597 #if MEMORY_LOGGING 2598 fl->ifl_m_dequeued++; 2599 #endif 2600 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2601 prefetch_pkts(fl, cidx); 2602 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2603 prefetch(&fl->ifl_sds.ifsd_map[next]); 2604 map = fl->ifl_sds.ifsd_map[cidx]; 2605 2606 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2607 2608 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2609 irf->irf_len != 0) { 2610 payload = *sd->ifsd_cl; 2611 payload += ri->iri_pad; 2612 len = ri->iri_len - ri->iri_pad; 2613 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2614 len | PFIL_MEMPTR | PFIL_IN, NULL); 2615 switch (*pf_rv) { 2616 case PFIL_DROPPED: 2617 case PFIL_CONSUMED: 2618 /* 2619 * The filter ate it. Everything is recycled. 2620 */ 2621 m = NULL; 2622 unload = 0; 2623 break; 2624 case PFIL_REALLOCED: 2625 /* 2626 * The filter copied it. Everything is recycled. 2627 */ 2628 m = pfil_mem2mbuf(payload); 2629 unload = 0; 2630 break; 2631 case PFIL_PASS: 2632 /* 2633 * Filter said it was OK, so receive like 2634 * normal 2635 */ 2636 fl->ifl_sds.ifsd_m[cidx] = NULL; 2637 break; 2638 default: 2639 MPASS(0); 2640 } 2641 } else { 2642 fl->ifl_sds.ifsd_m[cidx] = NULL; 2643 *pf_rv = PFIL_PASS; 2644 } 2645 2646 if (unload && irf->irf_len != 0) 2647 bus_dmamap_unload(fl->ifl_buf_tag, map); 2648 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2649 if (__predict_false(fl->ifl_cidx == 0)) 2650 fl->ifl_gen = 0; 2651 bit_clear(fl->ifl_rx_bitmap, cidx); 2652 return (m); 2653 } 2654 2655 static struct mbuf * 2656 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2657 { 2658 struct mbuf *m, *mh, *mt; 2659 caddr_t cl; 2660 int *pf_rv_ptr, flags, i, padlen; 2661 bool consumed; 2662 2663 i = 0; 2664 mh = NULL; 2665 consumed = false; 2666 *pf_rv = PFIL_PASS; 2667 pf_rv_ptr = pf_rv; 2668 do { 2669 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2670 pf_rv_ptr, ri); 2671 2672 MPASS(*sd->ifsd_cl != NULL); 2673 2674 /* 2675 * Exclude zero-length frags & frags from 2676 * packets the filter has consumed or dropped 2677 */ 2678 if (ri->iri_frags[i].irf_len == 0 || consumed || 2679 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2680 if (mh == NULL) { 2681 /* everything saved here */ 2682 consumed = true; 2683 pf_rv_ptr = NULL; 2684 continue; 2685 } 2686 /* XXX we can save the cluster here, but not the mbuf */ 2687 m_init(m, M_NOWAIT, MT_DATA, 0); 2688 m_free(m); 2689 continue; 2690 } 2691 if (mh == NULL) { 2692 flags = M_PKTHDR|M_EXT; 2693 mh = mt = m; 2694 padlen = ri->iri_pad; 2695 } else { 2696 flags = M_EXT; 2697 mt->m_next = m; 2698 mt = m; 2699 /* assuming padding is only on the first fragment */ 2700 padlen = 0; 2701 } 2702 cl = *sd->ifsd_cl; 2703 *sd->ifsd_cl = NULL; 2704 2705 /* Can these two be made one ? */ 2706 m_init(m, M_NOWAIT, MT_DATA, flags); 2707 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2708 /* 2709 * These must follow m_init and m_cljset 2710 */ 2711 m->m_data += padlen; 2712 ri->iri_len -= padlen; 2713 m->m_len = ri->iri_frags[i].irf_len; 2714 } while (++i < ri->iri_nfrags); 2715 2716 return (mh); 2717 } 2718 2719 /* 2720 * Process one software descriptor 2721 */ 2722 static struct mbuf * 2723 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2724 { 2725 struct if_rxsd sd; 2726 struct mbuf *m; 2727 int pf_rv; 2728 2729 /* should I merge this back in now that the two paths are basically duplicated? */ 2730 if (ri->iri_nfrags == 1 && 2731 ri->iri_frags[0].irf_len != 0 && 2732 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2733 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2734 &pf_rv, ri); 2735 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2736 return (m); 2737 if (pf_rv == PFIL_PASS) { 2738 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2739 #ifndef __NO_STRICT_ALIGNMENT 2740 if (!IP_ALIGNED(m)) 2741 m->m_data += 2; 2742 #endif 2743 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2744 m->m_len = ri->iri_frags[0].irf_len; 2745 } 2746 } else { 2747 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2748 if (m == NULL) 2749 return (NULL); 2750 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2751 return (m); 2752 } 2753 m->m_pkthdr.len = ri->iri_len; 2754 m->m_pkthdr.rcvif = ri->iri_ifp; 2755 m->m_flags |= ri->iri_flags; 2756 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2757 m->m_pkthdr.flowid = ri->iri_flowid; 2758 M_HASHTYPE_SET(m, ri->iri_rsstype); 2759 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2760 m->m_pkthdr.csum_data = ri->iri_csum_data; 2761 return (m); 2762 } 2763 2764 #if defined(INET6) || defined(INET) 2765 static void 2766 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2767 { 2768 CURVNET_SET(lc->ifp->if_vnet); 2769 #if defined(INET6) 2770 *v6 = V_ip6_forwarding; 2771 #endif 2772 #if defined(INET) 2773 *v4 = V_ipforwarding; 2774 #endif 2775 CURVNET_RESTORE(); 2776 } 2777 2778 /* 2779 * Returns true if it's possible this packet could be LROed. 2780 * if it returns false, it is guaranteed that tcp_lro_rx() 2781 * would not return zero. 2782 */ 2783 static bool 2784 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2785 { 2786 struct ether_header *eh; 2787 2788 eh = mtod(m, struct ether_header *); 2789 switch (eh->ether_type) { 2790 #if defined(INET6) 2791 case htons(ETHERTYPE_IPV6): 2792 return (!v6_forwarding); 2793 #endif 2794 #if defined (INET) 2795 case htons(ETHERTYPE_IP): 2796 return (!v4_forwarding); 2797 #endif 2798 } 2799 2800 return false; 2801 } 2802 #else 2803 static void 2804 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2805 { 2806 } 2807 #endif 2808 2809 static void 2810 _task_fn_rx_watchdog(void *context) 2811 { 2812 iflib_rxq_t rxq = context; 2813 2814 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2815 } 2816 2817 static uint8_t 2818 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2819 { 2820 if_t ifp; 2821 if_ctx_t ctx = rxq->ifr_ctx; 2822 if_shared_ctx_t sctx = ctx->ifc_sctx; 2823 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2824 int avail, i; 2825 qidx_t *cidxp; 2826 struct if_rxd_info ri; 2827 int err, budget_left, rx_bytes, rx_pkts; 2828 iflib_fl_t fl; 2829 int lro_enabled; 2830 bool v4_forwarding, v6_forwarding, lro_possible; 2831 uint8_t retval = 0; 2832 2833 /* 2834 * XXX early demux data packets so that if_input processing only handles 2835 * acks in interrupt context 2836 */ 2837 struct mbuf *m, *mh, *mt, *mf; 2838 2839 NET_EPOCH_ASSERT(); 2840 2841 lro_possible = v4_forwarding = v6_forwarding = false; 2842 ifp = ctx->ifc_ifp; 2843 mh = mt = NULL; 2844 MPASS(budget > 0); 2845 rx_pkts = rx_bytes = 0; 2846 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2847 cidxp = &rxq->ifr_cq_cidx; 2848 else 2849 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2850 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2851 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2852 retval |= iflib_fl_refill_all(ctx, fl); 2853 DBG_COUNTER_INC(rx_unavail); 2854 return (retval); 2855 } 2856 2857 /* pfil needs the vnet to be set */ 2858 CURVNET_SET_QUIET(ifp->if_vnet); 2859 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2860 if (__predict_false(!CTX_ACTIVE(ctx))) { 2861 DBG_COUNTER_INC(rx_ctx_inactive); 2862 break; 2863 } 2864 /* 2865 * Reset client set fields to their default values 2866 */ 2867 rxd_info_zero(&ri); 2868 ri.iri_qsidx = rxq->ifr_id; 2869 ri.iri_cidx = *cidxp; 2870 ri.iri_ifp = ifp; 2871 ri.iri_frags = rxq->ifr_frags; 2872 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2873 2874 if (err) 2875 goto err; 2876 rx_pkts += 1; 2877 rx_bytes += ri.iri_len; 2878 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2879 *cidxp = ri.iri_cidx; 2880 /* Update our consumer index */ 2881 /* XXX NB: shurd - check if this is still safe */ 2882 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2883 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2884 /* was this only a completion queue message? */ 2885 if (__predict_false(ri.iri_nfrags == 0)) 2886 continue; 2887 } 2888 MPASS(ri.iri_nfrags != 0); 2889 MPASS(ri.iri_len != 0); 2890 2891 /* will advance the cidx on the corresponding free lists */ 2892 m = iflib_rxd_pkt_get(rxq, &ri); 2893 avail--; 2894 budget_left--; 2895 if (avail == 0 && budget_left) 2896 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2897 2898 if (__predict_false(m == NULL)) 2899 continue; 2900 2901 /* imm_pkt: -- cxgb */ 2902 if (mh == NULL) 2903 mh = mt = m; 2904 else { 2905 mt->m_nextpkt = m; 2906 mt = m; 2907 } 2908 } 2909 CURVNET_RESTORE(); 2910 /* make sure that we can refill faster than drain */ 2911 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2912 retval |= iflib_fl_refill_all(ctx, fl); 2913 2914 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2915 if (lro_enabled) 2916 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2917 mt = mf = NULL; 2918 while (mh != NULL) { 2919 m = mh; 2920 mh = mh->m_nextpkt; 2921 m->m_nextpkt = NULL; 2922 #ifndef __NO_STRICT_ALIGNMENT 2923 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2924 continue; 2925 #endif 2926 rx_bytes += m->m_pkthdr.len; 2927 rx_pkts++; 2928 #if defined(INET6) || defined(INET) 2929 if (lro_enabled) { 2930 if (!lro_possible) { 2931 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2932 if (lro_possible && mf != NULL) { 2933 ifp->if_input(ifp, mf); 2934 DBG_COUNTER_INC(rx_if_input); 2935 mt = mf = NULL; 2936 } 2937 } 2938 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2939 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2940 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2941 continue; 2942 } 2943 } 2944 #endif 2945 if (lro_possible) { 2946 ifp->if_input(ifp, m); 2947 DBG_COUNTER_INC(rx_if_input); 2948 continue; 2949 } 2950 2951 if (mf == NULL) 2952 mf = m; 2953 if (mt != NULL) 2954 mt->m_nextpkt = m; 2955 mt = m; 2956 } 2957 if (mf != NULL) { 2958 ifp->if_input(ifp, mf); 2959 DBG_COUNTER_INC(rx_if_input); 2960 } 2961 2962 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2963 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2964 2965 /* 2966 * Flush any outstanding LRO work 2967 */ 2968 #if defined(INET6) || defined(INET) 2969 tcp_lro_flush_all(&rxq->ifr_lc); 2970 #endif 2971 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 2972 retval |= IFLIB_RXEOF_MORE; 2973 return (retval); 2974 err: 2975 STATE_LOCK(ctx); 2976 ctx->ifc_flags |= IFC_DO_RESET; 2977 iflib_admin_intr_deferred(ctx); 2978 STATE_UNLOCK(ctx); 2979 return (0); 2980 } 2981 2982 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2983 static inline qidx_t 2984 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2985 { 2986 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2987 qidx_t minthresh = txq->ift_size / 8; 2988 if (in_use > 4*minthresh) 2989 return (notify_count); 2990 if (in_use > 2*minthresh) 2991 return (notify_count >> 1); 2992 if (in_use > minthresh) 2993 return (notify_count >> 3); 2994 return (0); 2995 } 2996 2997 static inline qidx_t 2998 txq_max_rs_deferred(iflib_txq_t txq) 2999 { 3000 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3001 qidx_t minthresh = txq->ift_size / 8; 3002 if (txq->ift_in_use > 4*minthresh) 3003 return (notify_count); 3004 if (txq->ift_in_use > 2*minthresh) 3005 return (notify_count >> 1); 3006 if (txq->ift_in_use > minthresh) 3007 return (notify_count >> 2); 3008 return (2); 3009 } 3010 3011 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 3012 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 3013 3014 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 3015 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 3016 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 3017 3018 /* forward compatibility for cxgb */ 3019 #define FIRST_QSET(ctx) 0 3020 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3021 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3022 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3023 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3024 3025 /* XXX we should be setting this to something other than zero */ 3026 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 3027 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3028 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3029 3030 static inline bool 3031 iflib_txd_db_check(iflib_txq_t txq, int ring) 3032 { 3033 if_ctx_t ctx = txq->ift_ctx; 3034 qidx_t dbval, max; 3035 3036 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use); 3037 3038 /* force || threshold exceeded || at the edge of the ring */ 3039 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2)) { 3040 3041 /* 3042 * 'npending' is used if the card's doorbell is in terms of the number of descriptors 3043 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the 3044 * producer index explicitly (INTC). 3045 */ 3046 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3047 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3048 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3049 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3050 3051 /* 3052 * Absent bugs there are zero packets pending so reset pending counts to zero. 3053 */ 3054 txq->ift_db_pending = txq->ift_npending = 0; 3055 return (true); 3056 } 3057 return (false); 3058 } 3059 3060 #ifdef PKT_DEBUG 3061 static void 3062 print_pkt(if_pkt_info_t pi) 3063 { 3064 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3065 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3066 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3067 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3068 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3069 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3070 } 3071 #endif 3072 3073 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3074 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3075 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3076 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3077 3078 static int 3079 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3080 { 3081 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3082 struct ether_vlan_header *eh; 3083 struct mbuf *m; 3084 3085 m = *mp; 3086 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3087 M_WRITABLE(m) == 0) { 3088 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3089 return (ENOMEM); 3090 } else { 3091 m_freem(*mp); 3092 DBG_COUNTER_INC(tx_frees); 3093 *mp = m; 3094 } 3095 } 3096 3097 /* 3098 * Determine where frame payload starts. 3099 * Jump over vlan headers if already present, 3100 * helpful for QinQ too. 3101 */ 3102 if (__predict_false(m->m_len < sizeof(*eh))) { 3103 txq->ift_pullups++; 3104 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3105 return (ENOMEM); 3106 } 3107 eh = mtod(m, struct ether_vlan_header *); 3108 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3109 pi->ipi_etype = ntohs(eh->evl_proto); 3110 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3111 } else { 3112 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3113 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3114 } 3115 3116 switch (pi->ipi_etype) { 3117 #ifdef INET 3118 case ETHERTYPE_IP: 3119 { 3120 struct mbuf *n; 3121 struct ip *ip = NULL; 3122 struct tcphdr *th = NULL; 3123 int minthlen; 3124 3125 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3126 if (__predict_false(m->m_len < minthlen)) { 3127 /* 3128 * if this code bloat is causing too much of a hit 3129 * move it to a separate function and mark it noinline 3130 */ 3131 if (m->m_len == pi->ipi_ehdrlen) { 3132 n = m->m_next; 3133 MPASS(n); 3134 if (n->m_len >= sizeof(*ip)) { 3135 ip = (struct ip *)n->m_data; 3136 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3137 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3138 } else { 3139 txq->ift_pullups++; 3140 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3141 return (ENOMEM); 3142 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3143 } 3144 } else { 3145 txq->ift_pullups++; 3146 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3147 return (ENOMEM); 3148 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3149 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3150 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3151 } 3152 } else { 3153 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3154 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3155 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3156 } 3157 pi->ipi_ip_hlen = ip->ip_hl << 2; 3158 pi->ipi_ipproto = ip->ip_p; 3159 pi->ipi_flags |= IPI_TX_IPV4; 3160 3161 /* TCP checksum offload may require TCP header length */ 3162 if (IS_TX_OFFLOAD4(pi)) { 3163 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3164 if (__predict_false(th == NULL)) { 3165 txq->ift_pullups++; 3166 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3167 return (ENOMEM); 3168 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3169 } 3170 pi->ipi_tcp_hflags = th->th_flags; 3171 pi->ipi_tcp_hlen = th->th_off << 2; 3172 pi->ipi_tcp_seq = th->th_seq; 3173 } 3174 if (IS_TSO4(pi)) { 3175 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3176 return (ENXIO); 3177 /* 3178 * TSO always requires hardware checksum offload. 3179 */ 3180 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3181 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3182 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3183 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3184 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3185 ip->ip_sum = 0; 3186 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3187 } 3188 } 3189 } 3190 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3191 ip->ip_sum = 0; 3192 3193 break; 3194 } 3195 #endif 3196 #ifdef INET6 3197 case ETHERTYPE_IPV6: 3198 { 3199 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3200 struct tcphdr *th; 3201 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3202 3203 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3204 txq->ift_pullups++; 3205 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3206 return (ENOMEM); 3207 } 3208 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3209 3210 /* XXX-BZ this will go badly in case of ext hdrs. */ 3211 pi->ipi_ipproto = ip6->ip6_nxt; 3212 pi->ipi_flags |= IPI_TX_IPV6; 3213 3214 /* TCP checksum offload may require TCP header length */ 3215 if (IS_TX_OFFLOAD6(pi)) { 3216 if (pi->ipi_ipproto == IPPROTO_TCP) { 3217 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3218 txq->ift_pullups++; 3219 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3220 return (ENOMEM); 3221 } 3222 pi->ipi_tcp_hflags = th->th_flags; 3223 pi->ipi_tcp_hlen = th->th_off << 2; 3224 pi->ipi_tcp_seq = th->th_seq; 3225 } 3226 if (IS_TSO6(pi)) { 3227 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3228 return (ENXIO); 3229 /* 3230 * TSO always requires hardware checksum offload. 3231 */ 3232 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3233 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3234 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3235 } 3236 } 3237 break; 3238 } 3239 #endif 3240 default: 3241 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3242 pi->ipi_ip_hlen = 0; 3243 break; 3244 } 3245 *mp = m; 3246 3247 return (0); 3248 } 3249 3250 /* 3251 * If dodgy hardware rejects the scatter gather chain we've handed it 3252 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3253 * m_defrag'd mbufs 3254 */ 3255 static __noinline struct mbuf * 3256 iflib_remove_mbuf(iflib_txq_t txq) 3257 { 3258 int ntxd, pidx; 3259 struct mbuf *m, **ifsd_m; 3260 3261 ifsd_m = txq->ift_sds.ifsd_m; 3262 ntxd = txq->ift_size; 3263 pidx = txq->ift_pidx & (ntxd - 1); 3264 ifsd_m = txq->ift_sds.ifsd_m; 3265 m = ifsd_m[pidx]; 3266 ifsd_m[pidx] = NULL; 3267 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3268 if (txq->ift_sds.ifsd_tso_map != NULL) 3269 bus_dmamap_unload(txq->ift_tso_buf_tag, 3270 txq->ift_sds.ifsd_tso_map[pidx]); 3271 #if MEMORY_LOGGING 3272 txq->ift_dequeued++; 3273 #endif 3274 return (m); 3275 } 3276 3277 static inline caddr_t 3278 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3279 { 3280 qidx_t size; 3281 int ntxd; 3282 caddr_t start, end, cur, next; 3283 3284 ntxd = txq->ift_size; 3285 size = txq->ift_txd_size[qid]; 3286 start = txq->ift_ifdi[qid].idi_vaddr; 3287 3288 if (__predict_false(size == 0)) 3289 return (start); 3290 cur = start + size*cidx; 3291 end = start + size*ntxd; 3292 next = CACHE_PTR_NEXT(cur); 3293 return (next < end ? next : start); 3294 } 3295 3296 /* 3297 * Pad an mbuf to ensure a minimum ethernet frame size. 3298 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3299 */ 3300 static __noinline int 3301 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3302 { 3303 /* 3304 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3305 * and ARP message is the smallest common payload I can think of 3306 */ 3307 static char pad[18]; /* just zeros */ 3308 int n; 3309 struct mbuf *new_head; 3310 3311 if (!M_WRITABLE(*m_head)) { 3312 new_head = m_dup(*m_head, M_NOWAIT); 3313 if (new_head == NULL) { 3314 m_freem(*m_head); 3315 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3316 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3317 DBG_COUNTER_INC(tx_frees); 3318 return ENOMEM; 3319 } 3320 m_freem(*m_head); 3321 *m_head = new_head; 3322 } 3323 3324 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3325 n > 0; n -= sizeof(pad)) 3326 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3327 break; 3328 3329 if (n > 0) { 3330 m_freem(*m_head); 3331 device_printf(dev, "cannot pad short frame\n"); 3332 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3333 DBG_COUNTER_INC(tx_frees); 3334 return (ENOBUFS); 3335 } 3336 3337 return 0; 3338 } 3339 3340 static int 3341 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3342 { 3343 if_ctx_t ctx; 3344 if_shared_ctx_t sctx; 3345 if_softc_ctx_t scctx; 3346 bus_dma_tag_t buf_tag; 3347 bus_dma_segment_t *segs; 3348 struct mbuf *m_head, **ifsd_m; 3349 void *next_txd; 3350 bus_dmamap_t map; 3351 struct if_pkt_info pi; 3352 int remap = 0; 3353 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3354 3355 ctx = txq->ift_ctx; 3356 sctx = ctx->ifc_sctx; 3357 scctx = &ctx->ifc_softc_ctx; 3358 segs = txq->ift_segs; 3359 ntxd = txq->ift_size; 3360 m_head = *m_headp; 3361 map = NULL; 3362 3363 /* 3364 * If we're doing TSO the next descriptor to clean may be quite far ahead 3365 */ 3366 cidx = txq->ift_cidx; 3367 pidx = txq->ift_pidx; 3368 if (ctx->ifc_flags & IFC_PREFETCH) { 3369 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3370 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3371 next_txd = calc_next_txd(txq, cidx, 0); 3372 prefetch(next_txd); 3373 } 3374 3375 /* prefetch the next cache line of mbuf pointers and flags */ 3376 prefetch(&txq->ift_sds.ifsd_m[next]); 3377 prefetch(&txq->ift_sds.ifsd_map[next]); 3378 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3379 } 3380 map = txq->ift_sds.ifsd_map[pidx]; 3381 ifsd_m = txq->ift_sds.ifsd_m; 3382 3383 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3384 buf_tag = txq->ift_tso_buf_tag; 3385 max_segs = scctx->isc_tx_tso_segments_max; 3386 map = txq->ift_sds.ifsd_tso_map[pidx]; 3387 MPASS(buf_tag != NULL); 3388 MPASS(max_segs > 0); 3389 } else { 3390 buf_tag = txq->ift_buf_tag; 3391 max_segs = scctx->isc_tx_nsegments; 3392 map = txq->ift_sds.ifsd_map[pidx]; 3393 } 3394 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3395 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3396 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3397 if (err) { 3398 DBG_COUNTER_INC(encap_txd_encap_fail); 3399 return err; 3400 } 3401 } 3402 m_head = *m_headp; 3403 3404 pkt_info_zero(&pi); 3405 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3406 pi.ipi_pidx = pidx; 3407 pi.ipi_qsidx = txq->ift_id; 3408 pi.ipi_len = m_head->m_pkthdr.len; 3409 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3410 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3411 3412 /* deliberate bitwise OR to make one condition */ 3413 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3414 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3415 DBG_COUNTER_INC(encap_txd_encap_fail); 3416 return (err); 3417 } 3418 m_head = *m_headp; 3419 } 3420 3421 retry: 3422 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3423 BUS_DMA_NOWAIT); 3424 defrag: 3425 if (__predict_false(err)) { 3426 switch (err) { 3427 case EFBIG: 3428 /* try collapse once and defrag once */ 3429 if (remap == 0) { 3430 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3431 /* try defrag if collapsing fails */ 3432 if (m_head == NULL) 3433 remap++; 3434 } 3435 if (remap == 1) { 3436 txq->ift_mbuf_defrag++; 3437 m_head = m_defrag(*m_headp, M_NOWAIT); 3438 } 3439 /* 3440 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3441 * failed to map an mbuf that was run through m_defrag 3442 */ 3443 MPASS(remap <= 1); 3444 if (__predict_false(m_head == NULL || remap > 1)) 3445 goto defrag_failed; 3446 remap++; 3447 *m_headp = m_head; 3448 goto retry; 3449 break; 3450 case ENOMEM: 3451 txq->ift_no_tx_dma_setup++; 3452 break; 3453 default: 3454 txq->ift_no_tx_dma_setup++; 3455 m_freem(*m_headp); 3456 DBG_COUNTER_INC(tx_frees); 3457 *m_headp = NULL; 3458 break; 3459 } 3460 txq->ift_map_failed++; 3461 DBG_COUNTER_INC(encap_load_mbuf_fail); 3462 DBG_COUNTER_INC(encap_txd_encap_fail); 3463 return (err); 3464 } 3465 ifsd_m[pidx] = m_head; 3466 /* 3467 * XXX assumes a 1 to 1 relationship between segments and 3468 * descriptors - this does not hold true on all drivers, e.g. 3469 * cxgb 3470 */ 3471 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3472 txq->ift_no_desc_avail++; 3473 bus_dmamap_unload(buf_tag, map); 3474 DBG_COUNTER_INC(encap_txq_avail_fail); 3475 DBG_COUNTER_INC(encap_txd_encap_fail); 3476 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3477 GROUPTASK_ENQUEUE(&txq->ift_task); 3478 return (ENOBUFS); 3479 } 3480 /* 3481 * On Intel cards we can greatly reduce the number of TX interrupts 3482 * we see by only setting report status on every Nth descriptor. 3483 * However, this also means that the driver will need to keep track 3484 * of the descriptors that RS was set on to check them for the DD bit. 3485 */ 3486 txq->ift_rs_pending += nsegs + 1; 3487 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3488 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3489 pi.ipi_flags |= IPI_TX_INTR; 3490 txq->ift_rs_pending = 0; 3491 } 3492 3493 pi.ipi_segs = segs; 3494 pi.ipi_nsegs = nsegs; 3495 3496 MPASS(pidx >= 0 && pidx < txq->ift_size); 3497 #ifdef PKT_DEBUG 3498 print_pkt(&pi); 3499 #endif 3500 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3501 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3502 DBG_COUNTER_INC(tx_encap); 3503 MPASS(pi.ipi_new_pidx < txq->ift_size); 3504 3505 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3506 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3507 ndesc += txq->ift_size; 3508 txq->ift_gen = 1; 3509 } 3510 /* 3511 * drivers can need as many as 3512 * two sentinels 3513 */ 3514 MPASS(ndesc <= pi.ipi_nsegs + 2); 3515 MPASS(pi.ipi_new_pidx != pidx); 3516 MPASS(ndesc > 0); 3517 txq->ift_in_use += ndesc; 3518 txq->ift_db_pending += ndesc; 3519 3520 /* 3521 * We update the last software descriptor again here because there may 3522 * be a sentinel and/or there may be more mbufs than segments 3523 */ 3524 txq->ift_pidx = pi.ipi_new_pidx; 3525 txq->ift_npending += pi.ipi_ndescs; 3526 } else { 3527 *m_headp = m_head = iflib_remove_mbuf(txq); 3528 if (err == EFBIG) { 3529 txq->ift_txd_encap_efbig++; 3530 if (remap < 2) { 3531 remap = 1; 3532 goto defrag; 3533 } 3534 } 3535 goto defrag_failed; 3536 } 3537 /* 3538 * err can't possibly be non-zero here, so we don't neet to test it 3539 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3540 */ 3541 return (err); 3542 3543 defrag_failed: 3544 txq->ift_mbuf_defrag_failed++; 3545 txq->ift_map_failed++; 3546 m_freem(*m_headp); 3547 DBG_COUNTER_INC(tx_frees); 3548 *m_headp = NULL; 3549 DBG_COUNTER_INC(encap_txd_encap_fail); 3550 return (ENOMEM); 3551 } 3552 3553 static void 3554 iflib_tx_desc_free(iflib_txq_t txq, int n) 3555 { 3556 uint32_t qsize, cidx, mask, gen; 3557 struct mbuf *m, **ifsd_m; 3558 bool do_prefetch; 3559 3560 cidx = txq->ift_cidx; 3561 gen = txq->ift_gen; 3562 qsize = txq->ift_size; 3563 mask = qsize-1; 3564 ifsd_m = txq->ift_sds.ifsd_m; 3565 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3566 3567 while (n-- > 0) { 3568 if (do_prefetch) { 3569 prefetch(ifsd_m[(cidx + 3) & mask]); 3570 prefetch(ifsd_m[(cidx + 4) & mask]); 3571 } 3572 if ((m = ifsd_m[cidx]) != NULL) { 3573 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3574 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3575 bus_dmamap_sync(txq->ift_tso_buf_tag, 3576 txq->ift_sds.ifsd_tso_map[cidx], 3577 BUS_DMASYNC_POSTWRITE); 3578 bus_dmamap_unload(txq->ift_tso_buf_tag, 3579 txq->ift_sds.ifsd_tso_map[cidx]); 3580 } else { 3581 bus_dmamap_sync(txq->ift_buf_tag, 3582 txq->ift_sds.ifsd_map[cidx], 3583 BUS_DMASYNC_POSTWRITE); 3584 bus_dmamap_unload(txq->ift_buf_tag, 3585 txq->ift_sds.ifsd_map[cidx]); 3586 } 3587 /* XXX we don't support any drivers that batch packets yet */ 3588 MPASS(m->m_nextpkt == NULL); 3589 m_freem(m); 3590 ifsd_m[cidx] = NULL; 3591 #if MEMORY_LOGGING 3592 txq->ift_dequeued++; 3593 #endif 3594 DBG_COUNTER_INC(tx_frees); 3595 } 3596 if (__predict_false(++cidx == qsize)) { 3597 cidx = 0; 3598 gen = 0; 3599 } 3600 } 3601 txq->ift_cidx = cidx; 3602 txq->ift_gen = gen; 3603 } 3604 3605 static __inline int 3606 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3607 { 3608 int reclaim; 3609 if_ctx_t ctx = txq->ift_ctx; 3610 3611 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3612 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3613 3614 /* 3615 * Need a rate-limiting check so that this isn't called every time 3616 */ 3617 iflib_tx_credits_update(ctx, txq); 3618 reclaim = DESC_RECLAIMABLE(txq); 3619 3620 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3621 #ifdef INVARIANTS 3622 if (iflib_verbose_debug) { 3623 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3624 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3625 reclaim, thresh); 3626 } 3627 #endif 3628 return (0); 3629 } 3630 iflib_tx_desc_free(txq, reclaim); 3631 txq->ift_cleaned += reclaim; 3632 txq->ift_in_use -= reclaim; 3633 3634 return (reclaim); 3635 } 3636 3637 static struct mbuf ** 3638 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3639 { 3640 int next, size; 3641 struct mbuf **items; 3642 3643 size = r->size; 3644 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3645 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3646 3647 prefetch(items[(cidx + offset) & (size-1)]); 3648 if (remaining > 1) { 3649 prefetch2cachelines(&items[next]); 3650 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3651 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3652 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3653 } 3654 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3655 } 3656 3657 static void 3658 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3659 { 3660 3661 ifmp_ring_check_drainage(txq->ift_br, budget); 3662 } 3663 3664 static uint32_t 3665 iflib_txq_can_drain(struct ifmp_ring *r) 3666 { 3667 iflib_txq_t txq = r->cookie; 3668 if_ctx_t ctx = txq->ift_ctx; 3669 3670 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3671 return (1); 3672 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3673 BUS_DMASYNC_POSTREAD); 3674 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3675 false)); 3676 } 3677 3678 static uint32_t 3679 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3680 { 3681 iflib_txq_t txq = r->cookie; 3682 if_ctx_t ctx = txq->ift_ctx; 3683 if_t ifp = ctx->ifc_ifp; 3684 struct mbuf *m, **mp; 3685 int avail, bytes_sent, skipped, count, err, i; 3686 int mcast_sent, pkt_sent, reclaimed; 3687 bool do_prefetch, rang, ring; 3688 3689 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3690 !LINK_ACTIVE(ctx))) { 3691 DBG_COUNTER_INC(txq_drain_notready); 3692 return (0); 3693 } 3694 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3695 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending); 3696 avail = IDXDIFF(pidx, cidx, r->size); 3697 3698 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3699 /* 3700 * The driver is unloading so we need to free all pending packets. 3701 */ 3702 DBG_COUNTER_INC(txq_drain_flushing); 3703 for (i = 0; i < avail; i++) { 3704 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3705 m_freem(r->items[(cidx + i) & (r->size-1)]); 3706 r->items[(cidx + i) & (r->size-1)] = NULL; 3707 } 3708 return (avail); 3709 } 3710 3711 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3712 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3713 CALLOUT_LOCK(txq); 3714 callout_stop(&txq->ift_timer); 3715 CALLOUT_UNLOCK(txq); 3716 DBG_COUNTER_INC(txq_drain_oactive); 3717 return (0); 3718 } 3719 3720 /* 3721 * If we've reclaimed any packets this queue cannot be hung. 3722 */ 3723 if (reclaimed) 3724 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3725 skipped = mcast_sent = bytes_sent = pkt_sent = 0; 3726 count = MIN(avail, TX_BATCH_SIZE); 3727 #ifdef INVARIANTS 3728 if (iflib_verbose_debug) 3729 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3730 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3731 #endif 3732 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3733 err = 0; 3734 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx) + 2; i++) { 3735 int rem = do_prefetch ? count - i : 0; 3736 3737 mp = _ring_peek_one(r, cidx, i, rem); 3738 MPASS(mp != NULL && *mp != NULL); 3739 3740 /* 3741 * Completion interrupts will use the address of the txq 3742 * as a sentinel to enqueue _something_ in order to acquire 3743 * the lock on the mp_ring (there's no direct lock call). 3744 * We obviously whave to check for these sentinel cases 3745 * and skip them. 3746 */ 3747 if (__predict_false(*mp == (struct mbuf *)txq)) { 3748 skipped++; 3749 continue; 3750 } 3751 err = iflib_encap(txq, mp); 3752 if (__predict_false(err)) { 3753 /* no room - bail out */ 3754 if (err == ENOBUFS) 3755 break; 3756 skipped++; 3757 /* we can't send this packet - skip it */ 3758 continue; 3759 } 3760 pkt_sent++; 3761 m = *mp; 3762 DBG_COUNTER_INC(tx_sent); 3763 bytes_sent += m->m_pkthdr.len; 3764 mcast_sent += !!(m->m_flags & M_MCAST); 3765 3766 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3767 break; 3768 ETHER_BPF_MTAP(ifp, m); 3769 rang = iflib_txd_db_check(txq, false); 3770 } 3771 3772 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3773 ring = rang ? false : (iflib_min_tx_latency | err); 3774 iflib_txd_db_check(txq, ring); 3775 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3776 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3777 if (mcast_sent) 3778 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3779 #ifdef INVARIANTS 3780 if (iflib_verbose_debug) 3781 printf("consumed=%d\n", skipped + pkt_sent); 3782 #endif 3783 return (skipped + pkt_sent); 3784 } 3785 3786 static uint32_t 3787 iflib_txq_drain_always(struct ifmp_ring *r) 3788 { 3789 return (1); 3790 } 3791 3792 static uint32_t 3793 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3794 { 3795 int i, avail; 3796 struct mbuf **mp; 3797 iflib_txq_t txq; 3798 3799 txq = r->cookie; 3800 3801 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3802 CALLOUT_LOCK(txq); 3803 callout_stop(&txq->ift_timer); 3804 CALLOUT_UNLOCK(txq); 3805 3806 avail = IDXDIFF(pidx, cidx, r->size); 3807 for (i = 0; i < avail; i++) { 3808 mp = _ring_peek_one(r, cidx, i, avail - i); 3809 if (__predict_false(*mp == (struct mbuf *)txq)) 3810 continue; 3811 m_freem(*mp); 3812 DBG_COUNTER_INC(tx_frees); 3813 } 3814 MPASS(ifmp_ring_is_stalled(r) == 0); 3815 return (avail); 3816 } 3817 3818 static void 3819 iflib_ifmp_purge(iflib_txq_t txq) 3820 { 3821 struct ifmp_ring *r; 3822 3823 r = txq->ift_br; 3824 r->drain = iflib_txq_drain_free; 3825 r->can_drain = iflib_txq_drain_always; 3826 3827 ifmp_ring_check_drainage(r, r->size); 3828 3829 r->drain = iflib_txq_drain; 3830 r->can_drain = iflib_txq_can_drain; 3831 } 3832 3833 static void 3834 _task_fn_tx(void *context) 3835 { 3836 iflib_txq_t txq = context; 3837 if_ctx_t ctx = txq->ift_ctx; 3838 if_t ifp = ctx->ifc_ifp; 3839 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3840 3841 #ifdef IFLIB_DIAGNOSTICS 3842 txq->ift_cpu_exec_count[curcpu]++; 3843 #endif 3844 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 3845 return; 3846 #ifdef DEV_NETMAP 3847 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 3848 netmap_tx_irq(ifp, txq->ift_id)) 3849 goto skip_ifmp; 3850 #endif 3851 #ifdef ALTQ 3852 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3853 iflib_altq_if_start(ifp); 3854 #endif 3855 if (txq->ift_db_pending) 3856 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3857 else if (!abdicate) 3858 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3859 /* 3860 * When abdicating, we always need to check drainage, not just when we don't enqueue 3861 */ 3862 if (abdicate) 3863 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3864 #ifdef DEV_NETMAP 3865 skip_ifmp: 3866 #endif 3867 if (ctx->ifc_flags & IFC_LEGACY) 3868 IFDI_INTR_ENABLE(ctx); 3869 else 3870 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3871 } 3872 3873 static void 3874 _task_fn_rx(void *context) 3875 { 3876 iflib_rxq_t rxq = context; 3877 if_ctx_t ctx = rxq->ifr_ctx; 3878 uint8_t more; 3879 uint16_t budget; 3880 #ifdef DEV_NETMAP 3881 u_int work = 0; 3882 int nmirq; 3883 #endif 3884 3885 #ifdef IFLIB_DIAGNOSTICS 3886 rxq->ifr_cpu_exec_count[curcpu]++; 3887 #endif 3888 DBG_COUNTER_INC(task_fn_rxs); 3889 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3890 return; 3891 #ifdef DEV_NETMAP 3892 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 3893 if (nmirq != NM_IRQ_PASS) { 3894 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 3895 goto skip_rxeof; 3896 } 3897 #endif 3898 budget = ctx->ifc_sysctl_rx_budget; 3899 if (budget == 0) 3900 budget = 16; /* XXX */ 3901 more = iflib_rxeof(rxq, budget); 3902 #ifdef DEV_NETMAP 3903 skip_rxeof: 3904 #endif 3905 if ((more & IFLIB_RXEOF_MORE) == 0) { 3906 if (ctx->ifc_flags & IFC_LEGACY) 3907 IFDI_INTR_ENABLE(ctx); 3908 else 3909 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3910 DBG_COUNTER_INC(rx_intr_enables); 3911 } 3912 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3913 return; 3914 3915 if (more & IFLIB_RXEOF_MORE) 3916 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3917 else if (more & IFLIB_RXEOF_EMPTY) 3918 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 3919 } 3920 3921 static void 3922 _task_fn_admin(void *context) 3923 { 3924 if_ctx_t ctx = context; 3925 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3926 iflib_txq_t txq; 3927 int i; 3928 bool oactive, running, do_reset, do_watchdog, in_detach; 3929 3930 STATE_LOCK(ctx); 3931 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3932 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3933 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3934 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3935 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3936 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3937 STATE_UNLOCK(ctx); 3938 3939 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3940 return; 3941 if (in_detach) 3942 return; 3943 3944 CTX_LOCK(ctx); 3945 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3946 CALLOUT_LOCK(txq); 3947 callout_stop(&txq->ift_timer); 3948 CALLOUT_UNLOCK(txq); 3949 } 3950 if (do_watchdog) { 3951 ctx->ifc_watchdog_events++; 3952 IFDI_WATCHDOG_RESET(ctx); 3953 } 3954 IFDI_UPDATE_ADMIN_STATUS(ctx); 3955 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3956 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 3957 txq->ift_timer.c_cpu); 3958 } 3959 IFDI_LINK_INTR_ENABLE(ctx); 3960 if (do_reset) 3961 iflib_if_init_locked(ctx); 3962 CTX_UNLOCK(ctx); 3963 3964 if (LINK_ACTIVE(ctx) == 0) 3965 return; 3966 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3967 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3968 } 3969 3970 static void 3971 _task_fn_iov(void *context) 3972 { 3973 if_ctx_t ctx = context; 3974 3975 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3976 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3977 return; 3978 3979 CTX_LOCK(ctx); 3980 IFDI_VFLR_HANDLE(ctx); 3981 CTX_UNLOCK(ctx); 3982 } 3983 3984 static int 3985 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3986 { 3987 int err; 3988 if_int_delay_info_t info; 3989 if_ctx_t ctx; 3990 3991 info = (if_int_delay_info_t)arg1; 3992 ctx = info->iidi_ctx; 3993 info->iidi_req = req; 3994 info->iidi_oidp = oidp; 3995 CTX_LOCK(ctx); 3996 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3997 CTX_UNLOCK(ctx); 3998 return (err); 3999 } 4000 4001 /********************************************************************* 4002 * 4003 * IFNET FUNCTIONS 4004 * 4005 **********************************************************************/ 4006 4007 static void 4008 iflib_if_init_locked(if_ctx_t ctx) 4009 { 4010 iflib_stop(ctx); 4011 iflib_init_locked(ctx); 4012 } 4013 4014 static void 4015 iflib_if_init(void *arg) 4016 { 4017 if_ctx_t ctx = arg; 4018 4019 CTX_LOCK(ctx); 4020 iflib_if_init_locked(ctx); 4021 CTX_UNLOCK(ctx); 4022 } 4023 4024 static int 4025 iflib_if_transmit(if_t ifp, struct mbuf *m) 4026 { 4027 if_ctx_t ctx = if_getsoftc(ifp); 4028 4029 iflib_txq_t txq; 4030 int err, qidx; 4031 int abdicate = ctx->ifc_sysctl_tx_abdicate; 4032 4033 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 4034 DBG_COUNTER_INC(tx_frees); 4035 m_freem(m); 4036 return (ENETDOWN); 4037 } 4038 4039 MPASS(m->m_nextpkt == NULL); 4040 /* ALTQ-enabled interfaces always use queue 0. */ 4041 qidx = 0; 4042 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 4043 qidx = QIDX(ctx, m); 4044 /* 4045 * XXX calculate buf_ring based on flowid (divvy up bits?) 4046 */ 4047 txq = &ctx->ifc_txqs[qidx]; 4048 4049 #ifdef DRIVER_BACKPRESSURE 4050 if (txq->ift_closed) { 4051 while (m != NULL) { 4052 next = m->m_nextpkt; 4053 m->m_nextpkt = NULL; 4054 m_freem(m); 4055 DBG_COUNTER_INC(tx_frees); 4056 m = next; 4057 } 4058 return (ENOBUFS); 4059 } 4060 #endif 4061 #ifdef notyet 4062 qidx = count = 0; 4063 mp = marr; 4064 next = m; 4065 do { 4066 count++; 4067 next = next->m_nextpkt; 4068 } while (next != NULL); 4069 4070 if (count > nitems(marr)) 4071 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4072 /* XXX check nextpkt */ 4073 m_freem(m); 4074 /* XXX simplify for now */ 4075 DBG_COUNTER_INC(tx_frees); 4076 return (ENOBUFS); 4077 } 4078 for (next = m, i = 0; next != NULL; i++) { 4079 mp[i] = next; 4080 next = next->m_nextpkt; 4081 mp[i]->m_nextpkt = NULL; 4082 } 4083 #endif 4084 DBG_COUNTER_INC(tx_seen); 4085 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4086 4087 if (abdicate) 4088 GROUPTASK_ENQUEUE(&txq->ift_task); 4089 if (err) { 4090 if (!abdicate) 4091 GROUPTASK_ENQUEUE(&txq->ift_task); 4092 /* support forthcoming later */ 4093 #ifdef DRIVER_BACKPRESSURE 4094 txq->ift_closed = TRUE; 4095 #endif 4096 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4097 m_freem(m); 4098 DBG_COUNTER_INC(tx_frees); 4099 } 4100 4101 return (err); 4102 } 4103 4104 #ifdef ALTQ 4105 /* 4106 * The overall approach to integrating iflib with ALTQ is to continue to use 4107 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4108 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4109 * is redundant/unnecessary, but doing so minimizes the amount of 4110 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4111 * redundantly queueing to an intermediate mp_ring is swamped by the 4112 * performance limitations inherent in using ALTQ. 4113 * 4114 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4115 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4116 * given interface. If ALTQ is enabled for an interface, then all 4117 * transmitted packets for that interface will be submitted to the ALTQ 4118 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4119 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4120 * update stats that the iflib machinery handles, and which is sensitve to 4121 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4122 * will be installed as the start routine for use by ALTQ facilities that 4123 * need to trigger queue drains on a scheduled basis. 4124 * 4125 */ 4126 static void 4127 iflib_altq_if_start(if_t ifp) 4128 { 4129 struct ifaltq *ifq = &ifp->if_snd; 4130 struct mbuf *m; 4131 4132 IFQ_LOCK(ifq); 4133 IFQ_DEQUEUE_NOLOCK(ifq, m); 4134 while (m != NULL) { 4135 iflib_if_transmit(ifp, m); 4136 IFQ_DEQUEUE_NOLOCK(ifq, m); 4137 } 4138 IFQ_UNLOCK(ifq); 4139 } 4140 4141 static int 4142 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4143 { 4144 int err; 4145 4146 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4147 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4148 if (err == 0) 4149 iflib_altq_if_start(ifp); 4150 } else 4151 err = iflib_if_transmit(ifp, m); 4152 4153 return (err); 4154 } 4155 #endif /* ALTQ */ 4156 4157 static void 4158 iflib_if_qflush(if_t ifp) 4159 { 4160 if_ctx_t ctx = if_getsoftc(ifp); 4161 iflib_txq_t txq = ctx->ifc_txqs; 4162 int i; 4163 4164 STATE_LOCK(ctx); 4165 ctx->ifc_flags |= IFC_QFLUSH; 4166 STATE_UNLOCK(ctx); 4167 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4168 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4169 iflib_txq_check_drain(txq, 0); 4170 STATE_LOCK(ctx); 4171 ctx->ifc_flags &= ~IFC_QFLUSH; 4172 STATE_UNLOCK(ctx); 4173 4174 /* 4175 * When ALTQ is enabled, this will also take care of purging the 4176 * ALTQ queue(s). 4177 */ 4178 if_qflush(ifp); 4179 } 4180 4181 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4182 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4183 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4184 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP) 4185 4186 static int 4187 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4188 { 4189 if_ctx_t ctx = if_getsoftc(ifp); 4190 struct ifreq *ifr = (struct ifreq *)data; 4191 #if defined(INET) || defined(INET6) 4192 struct ifaddr *ifa = (struct ifaddr *)data; 4193 #endif 4194 bool avoid_reset = false; 4195 int err = 0, reinit = 0, bits; 4196 4197 switch (command) { 4198 case SIOCSIFADDR: 4199 #ifdef INET 4200 if (ifa->ifa_addr->sa_family == AF_INET) 4201 avoid_reset = true; 4202 #endif 4203 #ifdef INET6 4204 if (ifa->ifa_addr->sa_family == AF_INET6) 4205 avoid_reset = true; 4206 #endif 4207 /* 4208 ** Calling init results in link renegotiation, 4209 ** so we avoid doing it when possible. 4210 */ 4211 if (avoid_reset) { 4212 if_setflagbits(ifp, IFF_UP,0); 4213 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4214 reinit = 1; 4215 #ifdef INET 4216 if (!(if_getflags(ifp) & IFF_NOARP)) 4217 arp_ifinit(ifp, ifa); 4218 #endif 4219 } else 4220 err = ether_ioctl(ifp, command, data); 4221 break; 4222 case SIOCSIFMTU: 4223 CTX_LOCK(ctx); 4224 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4225 CTX_UNLOCK(ctx); 4226 break; 4227 } 4228 bits = if_getdrvflags(ifp); 4229 /* stop the driver and free any clusters before proceeding */ 4230 iflib_stop(ctx); 4231 4232 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4233 STATE_LOCK(ctx); 4234 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4235 ctx->ifc_flags |= IFC_MULTISEG; 4236 else 4237 ctx->ifc_flags &= ~IFC_MULTISEG; 4238 STATE_UNLOCK(ctx); 4239 err = if_setmtu(ifp, ifr->ifr_mtu); 4240 } 4241 iflib_init_locked(ctx); 4242 STATE_LOCK(ctx); 4243 if_setdrvflags(ifp, bits); 4244 STATE_UNLOCK(ctx); 4245 CTX_UNLOCK(ctx); 4246 break; 4247 case SIOCSIFFLAGS: 4248 CTX_LOCK(ctx); 4249 if (if_getflags(ifp) & IFF_UP) { 4250 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4251 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4252 (IFF_PROMISC | IFF_ALLMULTI)) { 4253 CTX_UNLOCK(ctx); 4254 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4255 CTX_LOCK(ctx); 4256 } 4257 } else 4258 reinit = 1; 4259 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4260 iflib_stop(ctx); 4261 } 4262 ctx->ifc_if_flags = if_getflags(ifp); 4263 CTX_UNLOCK(ctx); 4264 break; 4265 case SIOCADDMULTI: 4266 case SIOCDELMULTI: 4267 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4268 CTX_LOCK(ctx); 4269 IFDI_INTR_DISABLE(ctx); 4270 IFDI_MULTI_SET(ctx); 4271 IFDI_INTR_ENABLE(ctx); 4272 CTX_UNLOCK(ctx); 4273 } 4274 break; 4275 case SIOCSIFMEDIA: 4276 CTX_LOCK(ctx); 4277 IFDI_MEDIA_SET(ctx); 4278 CTX_UNLOCK(ctx); 4279 /* FALLTHROUGH */ 4280 case SIOCGIFMEDIA: 4281 case SIOCGIFXMEDIA: 4282 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4283 break; 4284 case SIOCGI2C: 4285 { 4286 struct ifi2creq i2c; 4287 4288 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4289 if (err != 0) 4290 break; 4291 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4292 err = EINVAL; 4293 break; 4294 } 4295 if (i2c.len > sizeof(i2c.data)) { 4296 err = EINVAL; 4297 break; 4298 } 4299 4300 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4301 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4302 sizeof(i2c)); 4303 break; 4304 } 4305 case SIOCSIFCAP: 4306 { 4307 int mask, setmask, oldmask; 4308 4309 oldmask = if_getcapenable(ifp); 4310 mask = ifr->ifr_reqcap ^ oldmask; 4311 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP; 4312 setmask = 0; 4313 #ifdef TCP_OFFLOAD 4314 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4315 #endif 4316 setmask |= (mask & IFCAP_FLAGS); 4317 setmask |= (mask & IFCAP_WOL); 4318 4319 /* 4320 * If any RX csum has changed, change all the ones that 4321 * are supported by the driver. 4322 */ 4323 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4324 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4325 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4326 } 4327 4328 /* 4329 * want to ensure that traffic has stopped before we change any of the flags 4330 */ 4331 if (setmask) { 4332 CTX_LOCK(ctx); 4333 bits = if_getdrvflags(ifp); 4334 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4335 iflib_stop(ctx); 4336 STATE_LOCK(ctx); 4337 if_togglecapenable(ifp, setmask); 4338 STATE_UNLOCK(ctx); 4339 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4340 iflib_init_locked(ctx); 4341 STATE_LOCK(ctx); 4342 if_setdrvflags(ifp, bits); 4343 STATE_UNLOCK(ctx); 4344 CTX_UNLOCK(ctx); 4345 } 4346 if_vlancap(ifp); 4347 break; 4348 } 4349 case SIOCGPRIVATE_0: 4350 case SIOCSDRVSPEC: 4351 case SIOCGDRVSPEC: 4352 CTX_LOCK(ctx); 4353 err = IFDI_PRIV_IOCTL(ctx, command, data); 4354 CTX_UNLOCK(ctx); 4355 break; 4356 default: 4357 err = ether_ioctl(ifp, command, data); 4358 break; 4359 } 4360 if (reinit) 4361 iflib_if_init(ctx); 4362 return (err); 4363 } 4364 4365 static uint64_t 4366 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4367 { 4368 if_ctx_t ctx = if_getsoftc(ifp); 4369 4370 return (IFDI_GET_COUNTER(ctx, cnt)); 4371 } 4372 4373 /********************************************************************* 4374 * 4375 * OTHER FUNCTIONS EXPORTED TO THE STACK 4376 * 4377 **********************************************************************/ 4378 4379 static void 4380 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4381 { 4382 if_ctx_t ctx = if_getsoftc(ifp); 4383 4384 if ((void *)ctx != arg) 4385 return; 4386 4387 if ((vtag == 0) || (vtag > 4095)) 4388 return; 4389 4390 if (iflib_in_detach(ctx)) 4391 return; 4392 4393 CTX_LOCK(ctx); 4394 /* Driver may need all untagged packets to be flushed */ 4395 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4396 iflib_stop(ctx); 4397 IFDI_VLAN_REGISTER(ctx, vtag); 4398 /* Re-init to load the changes, if required */ 4399 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4400 iflib_init_locked(ctx); 4401 CTX_UNLOCK(ctx); 4402 } 4403 4404 static void 4405 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4406 { 4407 if_ctx_t ctx = if_getsoftc(ifp); 4408 4409 if ((void *)ctx != arg) 4410 return; 4411 4412 if ((vtag == 0) || (vtag > 4095)) 4413 return; 4414 4415 CTX_LOCK(ctx); 4416 /* Driver may need all tagged packets to be flushed */ 4417 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4418 iflib_stop(ctx); 4419 IFDI_VLAN_UNREGISTER(ctx, vtag); 4420 /* Re-init to load the changes, if required */ 4421 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4422 iflib_init_locked(ctx); 4423 CTX_UNLOCK(ctx); 4424 } 4425 4426 static void 4427 iflib_led_func(void *arg, int onoff) 4428 { 4429 if_ctx_t ctx = arg; 4430 4431 CTX_LOCK(ctx); 4432 IFDI_LED_FUNC(ctx, onoff); 4433 CTX_UNLOCK(ctx); 4434 } 4435 4436 /********************************************************************* 4437 * 4438 * BUS FUNCTION DEFINITIONS 4439 * 4440 **********************************************************************/ 4441 4442 int 4443 iflib_device_probe(device_t dev) 4444 { 4445 const pci_vendor_info_t *ent; 4446 if_shared_ctx_t sctx; 4447 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4448 uint16_t pci_vendor_id; 4449 4450 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4451 return (ENOTSUP); 4452 4453 pci_vendor_id = pci_get_vendor(dev); 4454 pci_device_id = pci_get_device(dev); 4455 pci_subvendor_id = pci_get_subvendor(dev); 4456 pci_subdevice_id = pci_get_subdevice(dev); 4457 pci_rev_id = pci_get_revid(dev); 4458 if (sctx->isc_parse_devinfo != NULL) 4459 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4460 4461 ent = sctx->isc_vendor_info; 4462 while (ent->pvi_vendor_id != 0) { 4463 if (pci_vendor_id != ent->pvi_vendor_id) { 4464 ent++; 4465 continue; 4466 } 4467 if ((pci_device_id == ent->pvi_device_id) && 4468 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4469 (ent->pvi_subvendor_id == 0)) && 4470 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4471 (ent->pvi_subdevice_id == 0)) && 4472 ((pci_rev_id == ent->pvi_rev_id) || 4473 (ent->pvi_rev_id == 0))) { 4474 device_set_desc_copy(dev, ent->pvi_name); 4475 /* this needs to be changed to zero if the bus probing code 4476 * ever stops re-probing on best match because the sctx 4477 * may have its values over written by register calls 4478 * in subsequent probes 4479 */ 4480 return (BUS_PROBE_DEFAULT); 4481 } 4482 ent++; 4483 } 4484 return (ENXIO); 4485 } 4486 4487 int 4488 iflib_device_probe_vendor(device_t dev) 4489 { 4490 int probe; 4491 4492 probe = iflib_device_probe(dev); 4493 if (probe == BUS_PROBE_DEFAULT) 4494 return (BUS_PROBE_VENDOR); 4495 else 4496 return (probe); 4497 } 4498 4499 static void 4500 iflib_reset_qvalues(if_ctx_t ctx) 4501 { 4502 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4503 if_shared_ctx_t sctx = ctx->ifc_sctx; 4504 device_t dev = ctx->ifc_dev; 4505 int i; 4506 4507 if (ctx->ifc_sysctl_ntxqs != 0) 4508 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4509 if (ctx->ifc_sysctl_nrxqs != 0) 4510 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4511 4512 for (i = 0; i < sctx->isc_ntxqs; i++) { 4513 if (ctx->ifc_sysctl_ntxds[i] != 0) 4514 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4515 else 4516 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4517 } 4518 4519 for (i = 0; i < sctx->isc_nrxqs; i++) { 4520 if (ctx->ifc_sysctl_nrxds[i] != 0) 4521 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4522 else 4523 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4524 } 4525 4526 for (i = 0; i < sctx->isc_nrxqs; i++) { 4527 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4528 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4529 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4530 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4531 } 4532 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4533 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4534 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4535 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4536 } 4537 if (!powerof2(scctx->isc_nrxd[i])) { 4538 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4539 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4540 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4541 } 4542 } 4543 4544 for (i = 0; i < sctx->isc_ntxqs; i++) { 4545 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4546 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4547 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4548 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4549 } 4550 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4551 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4552 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4553 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4554 } 4555 if (!powerof2(scctx->isc_ntxd[i])) { 4556 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4557 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4558 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4559 } 4560 } 4561 } 4562 4563 static void 4564 iflib_add_pfil(if_ctx_t ctx) 4565 { 4566 struct pfil_head *pfil; 4567 struct pfil_head_args pa; 4568 iflib_rxq_t rxq; 4569 int i; 4570 4571 pa.pa_version = PFIL_VERSION; 4572 pa.pa_flags = PFIL_IN; 4573 pa.pa_type = PFIL_TYPE_ETHERNET; 4574 pa.pa_headname = ctx->ifc_ifp->if_xname; 4575 pfil = pfil_head_register(&pa); 4576 4577 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4578 rxq->pfil = pfil; 4579 } 4580 } 4581 4582 static void 4583 iflib_rem_pfil(if_ctx_t ctx) 4584 { 4585 struct pfil_head *pfil; 4586 iflib_rxq_t rxq; 4587 int i; 4588 4589 rxq = ctx->ifc_rxqs; 4590 pfil = rxq->pfil; 4591 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4592 rxq->pfil = NULL; 4593 } 4594 pfil_head_unregister(pfil); 4595 } 4596 4597 static uint16_t 4598 get_ctx_core_offset(if_ctx_t ctx) 4599 { 4600 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4601 struct cpu_offset *op; 4602 uint16_t qc; 4603 uint16_t ret = ctx->ifc_sysctl_core_offset; 4604 4605 if (ret != CORE_OFFSET_UNSPECIFIED) 4606 return (ret); 4607 4608 if (ctx->ifc_sysctl_separate_txrx) 4609 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets; 4610 else 4611 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets); 4612 4613 mtx_lock(&cpu_offset_mtx); 4614 SLIST_FOREACH(op, &cpu_offsets, entries) { 4615 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4616 ret = op->offset; 4617 op->offset += qc; 4618 MPASS(op->refcount < UINT_MAX); 4619 op->refcount++; 4620 break; 4621 } 4622 } 4623 if (ret == CORE_OFFSET_UNSPECIFIED) { 4624 ret = 0; 4625 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4626 M_NOWAIT | M_ZERO); 4627 if (op == NULL) { 4628 device_printf(ctx->ifc_dev, 4629 "allocation for cpu offset failed.\n"); 4630 } else { 4631 op->offset = qc; 4632 op->refcount = 1; 4633 CPU_COPY(&ctx->ifc_cpus, &op->set); 4634 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4635 } 4636 } 4637 mtx_unlock(&cpu_offset_mtx); 4638 4639 return (ret); 4640 } 4641 4642 static void 4643 unref_ctx_core_offset(if_ctx_t ctx) 4644 { 4645 struct cpu_offset *op, *top; 4646 4647 mtx_lock(&cpu_offset_mtx); 4648 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4649 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4650 MPASS(op->refcount > 0); 4651 op->refcount--; 4652 if (op->refcount == 0) { 4653 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4654 free(op, M_IFLIB); 4655 } 4656 break; 4657 } 4658 } 4659 mtx_unlock(&cpu_offset_mtx); 4660 } 4661 4662 int 4663 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4664 { 4665 if_ctx_t ctx; 4666 if_t ifp; 4667 if_softc_ctx_t scctx; 4668 kobjop_desc_t kobj_desc; 4669 kobj_method_t *kobj_method; 4670 int err, msix, rid; 4671 int num_txd, num_rxd; 4672 4673 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4674 4675 if (sc == NULL) { 4676 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4677 device_set_softc(dev, ctx); 4678 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4679 } 4680 4681 ctx->ifc_sctx = sctx; 4682 ctx->ifc_dev = dev; 4683 ctx->ifc_softc = sc; 4684 4685 if ((err = iflib_register(ctx)) != 0) { 4686 device_printf(dev, "iflib_register failed %d\n", err); 4687 goto fail_ctx_free; 4688 } 4689 iflib_add_device_sysctl_pre(ctx); 4690 4691 scctx = &ctx->ifc_softc_ctx; 4692 ifp = ctx->ifc_ifp; 4693 4694 iflib_reset_qvalues(ctx); 4695 CTX_LOCK(ctx); 4696 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4697 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4698 goto fail_unlock; 4699 } 4700 _iflib_pre_assert(scctx); 4701 ctx->ifc_txrx = *scctx->isc_txrx; 4702 4703 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 4704 ctx->ifc_mediap = scctx->isc_media; 4705 4706 #ifdef INVARIANTS 4707 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4708 MPASS(scctx->isc_tx_csum_flags); 4709 #endif 4710 4711 if_setcapabilities(ifp, 4712 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP); 4713 if_setcapenable(ifp, 4714 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP); 4715 4716 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4717 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4718 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4719 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4720 4721 num_txd = iflib_num_tx_descs(ctx); 4722 num_rxd = iflib_num_rx_descs(ctx); 4723 4724 /* XXX change for per-queue sizes */ 4725 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4726 num_txd, num_rxd); 4727 4728 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 4729 scctx->isc_tx_nsegments = max(1, num_txd / 4730 MAX_SINGLE_PACKET_FRACTION); 4731 if (scctx->isc_tx_tso_segments_max > num_txd / 4732 MAX_SINGLE_PACKET_FRACTION) 4733 scctx->isc_tx_tso_segments_max = max(1, 4734 num_txd / MAX_SINGLE_PACKET_FRACTION); 4735 4736 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4737 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4738 /* 4739 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4740 * but some MACs do. 4741 */ 4742 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4743 IP_MAXPACKET)); 4744 /* 4745 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4746 * into account. In the worst case, each of these calls will 4747 * add another mbuf and, thus, the requirement for another DMA 4748 * segment. So for best performance, it doesn't make sense to 4749 * advertize a maximum of TSO segments that typically will 4750 * require defragmentation in iflib_encap(). 4751 */ 4752 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4753 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4754 } 4755 if (scctx->isc_rss_table_size == 0) 4756 scctx->isc_rss_table_size = 64; 4757 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4758 4759 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4760 /* XXX format name */ 4761 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4762 NULL, NULL, "admin"); 4763 4764 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4765 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4766 device_printf(dev, "Unable to fetch CPU list\n"); 4767 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4768 } 4769 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4770 4771 /* 4772 ** Now set up MSI or MSI-X, should return us the number of supported 4773 ** vectors (will be 1 for a legacy interrupt and MSI). 4774 */ 4775 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4776 msix = scctx->isc_vectors; 4777 } else if (scctx->isc_msix_bar != 0) 4778 /* 4779 * The simple fact that isc_msix_bar is not 0 does not mean we 4780 * we have a good value there that is known to work. 4781 */ 4782 msix = iflib_msix_init(ctx); 4783 else { 4784 scctx->isc_vectors = 1; 4785 scctx->isc_ntxqsets = 1; 4786 scctx->isc_nrxqsets = 1; 4787 scctx->isc_intr = IFLIB_INTR_LEGACY; 4788 msix = 0; 4789 } 4790 /* Get memory for the station queues */ 4791 if ((err = iflib_queues_alloc(ctx))) { 4792 device_printf(dev, "Unable to allocate queue memory\n"); 4793 goto fail_intr_free; 4794 } 4795 4796 if ((err = iflib_qset_structures_setup(ctx))) 4797 goto fail_queues; 4798 4799 /* 4800 * Now that we know how many queues there are, get the core offset. 4801 */ 4802 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 4803 4804 if (msix > 1) { 4805 /* 4806 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 4807 * aren't the default NULL implementation. 4808 */ 4809 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 4810 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4811 kobj_desc); 4812 if (kobj_method == &kobj_desc->deflt) { 4813 device_printf(dev, 4814 "MSI-X requires ifdi_rx_queue_intr_enable method"); 4815 err = EOPNOTSUPP; 4816 goto fail_queues; 4817 } 4818 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 4819 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4820 kobj_desc); 4821 if (kobj_method == &kobj_desc->deflt) { 4822 device_printf(dev, 4823 "MSI-X requires ifdi_tx_queue_intr_enable method"); 4824 err = EOPNOTSUPP; 4825 goto fail_queues; 4826 } 4827 4828 /* 4829 * Assign the MSI-X vectors. 4830 * Note that the default NULL ifdi_msix_intr_assign method will 4831 * fail here, too. 4832 */ 4833 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 4834 if (err != 0) { 4835 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 4836 err); 4837 goto fail_queues; 4838 } 4839 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 4840 rid = 0; 4841 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4842 MPASS(msix == 1); 4843 rid = 1; 4844 } 4845 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4846 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4847 goto fail_queues; 4848 } 4849 } else { 4850 device_printf(dev, 4851 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 4852 err = ENODEV; 4853 goto fail_intr_free; 4854 } 4855 4856 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4857 4858 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4859 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4860 goto fail_detach; 4861 } 4862 4863 /* 4864 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4865 * This must appear after the call to ether_ifattach() because 4866 * ether_ifattach() sets if_hdrlen to the default value. 4867 */ 4868 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4869 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4870 4871 if ((err = iflib_netmap_attach(ctx))) { 4872 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4873 goto fail_detach; 4874 } 4875 *ctxp = ctx; 4876 4877 DEBUGNET_SET(ctx->ifc_ifp, iflib); 4878 4879 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4880 iflib_add_device_sysctl_post(ctx); 4881 iflib_add_pfil(ctx); 4882 ctx->ifc_flags |= IFC_INIT_DONE; 4883 CTX_UNLOCK(ctx); 4884 4885 return (0); 4886 4887 fail_detach: 4888 ether_ifdetach(ctx->ifc_ifp); 4889 fail_intr_free: 4890 iflib_free_intr_mem(ctx); 4891 fail_queues: 4892 iflib_tx_structures_free(ctx); 4893 iflib_rx_structures_free(ctx); 4894 iflib_tqg_detach(ctx); 4895 IFDI_DETACH(ctx); 4896 fail_unlock: 4897 CTX_UNLOCK(ctx); 4898 iflib_deregister(ctx); 4899 fail_ctx_free: 4900 device_set_softc(ctx->ifc_dev, NULL); 4901 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4902 free(ctx->ifc_softc, M_IFLIB); 4903 free(ctx, M_IFLIB); 4904 return (err); 4905 } 4906 4907 int 4908 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4909 struct iflib_cloneattach_ctx *clctx) 4910 { 4911 int num_txd, num_rxd; 4912 int err; 4913 if_ctx_t ctx; 4914 if_t ifp; 4915 if_softc_ctx_t scctx; 4916 int i; 4917 void *sc; 4918 4919 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4920 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4921 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4922 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4923 ctx->ifc_flags |= IFC_PSEUDO; 4924 4925 ctx->ifc_sctx = sctx; 4926 ctx->ifc_softc = sc; 4927 ctx->ifc_dev = dev; 4928 4929 if ((err = iflib_register(ctx)) != 0) { 4930 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4931 goto fail_ctx_free; 4932 } 4933 iflib_add_device_sysctl_pre(ctx); 4934 4935 scctx = &ctx->ifc_softc_ctx; 4936 ifp = ctx->ifc_ifp; 4937 4938 iflib_reset_qvalues(ctx); 4939 CTX_LOCK(ctx); 4940 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4941 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4942 goto fail_unlock; 4943 } 4944 if (sctx->isc_flags & IFLIB_GEN_MAC) 4945 ether_gen_addr(ifp, &ctx->ifc_mac); 4946 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4947 clctx->cc_params)) != 0) { 4948 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4949 goto fail_unlock; 4950 } 4951 #ifdef INVARIANTS 4952 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4953 MPASS(scctx->isc_tx_csum_flags); 4954 #endif 4955 4956 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4957 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4958 4959 ifp->if_flags |= IFF_NOGROUP; 4960 if (sctx->isc_flags & IFLIB_PSEUDO) { 4961 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4962 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4963 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) { 4964 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4965 } else { 4966 if_attach(ctx->ifc_ifp); 4967 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t)); 4968 } 4969 4970 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4971 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4972 goto fail_detach; 4973 } 4974 *ctxp = ctx; 4975 4976 /* 4977 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4978 * This must appear after the call to ether_ifattach() because 4979 * ether_ifattach() sets if_hdrlen to the default value. 4980 */ 4981 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4982 if_setifheaderlen(ifp, 4983 sizeof(struct ether_vlan_header)); 4984 4985 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4986 iflib_add_device_sysctl_post(ctx); 4987 ctx->ifc_flags |= IFC_INIT_DONE; 4988 CTX_UNLOCK(ctx); 4989 return (0); 4990 } 4991 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4992 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4993 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4994 4995 _iflib_pre_assert(scctx); 4996 ctx->ifc_txrx = *scctx->isc_txrx; 4997 4998 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4999 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5000 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5001 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5002 5003 num_txd = iflib_num_tx_descs(ctx); 5004 num_rxd = iflib_num_rx_descs(ctx); 5005 5006 /* XXX change for per-queue sizes */ 5007 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5008 num_txd, num_rxd); 5009 5010 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5011 scctx->isc_tx_nsegments = max(1, num_txd / 5012 MAX_SINGLE_PACKET_FRACTION); 5013 if (scctx->isc_tx_tso_segments_max > num_txd / 5014 MAX_SINGLE_PACKET_FRACTION) 5015 scctx->isc_tx_tso_segments_max = max(1, 5016 num_txd / MAX_SINGLE_PACKET_FRACTION); 5017 5018 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5019 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5020 /* 5021 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5022 * but some MACs do. 5023 */ 5024 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5025 IP_MAXPACKET)); 5026 /* 5027 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5028 * into account. In the worst case, each of these calls will 5029 * add another mbuf and, thus, the requirement for another DMA 5030 * segment. So for best performance, it doesn't make sense to 5031 * advertize a maximum of TSO segments that typically will 5032 * require defragmentation in iflib_encap(). 5033 */ 5034 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5035 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5036 } 5037 if (scctx->isc_rss_table_size == 0) 5038 scctx->isc_rss_table_size = 64; 5039 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5040 5041 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5042 /* XXX format name */ 5043 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5044 NULL, NULL, "admin"); 5045 5046 /* XXX --- can support > 1 -- but keep it simple for now */ 5047 scctx->isc_intr = IFLIB_INTR_LEGACY; 5048 5049 /* Get memory for the station queues */ 5050 if ((err = iflib_queues_alloc(ctx))) { 5051 device_printf(dev, "Unable to allocate queue memory\n"); 5052 goto fail_iflib_detach; 5053 } 5054 5055 if ((err = iflib_qset_structures_setup(ctx))) { 5056 device_printf(dev, "qset structure setup failed %d\n", err); 5057 goto fail_queues; 5058 } 5059 5060 /* 5061 * XXX What if anything do we want to do about interrupts? 5062 */ 5063 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5064 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5065 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5066 goto fail_detach; 5067 } 5068 5069 /* 5070 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5071 * This must appear after the call to ether_ifattach() because 5072 * ether_ifattach() sets if_hdrlen to the default value. 5073 */ 5074 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5075 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5076 5077 /* XXX handle more than one queue */ 5078 for (i = 0; i < scctx->isc_nrxqsets; i++) 5079 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 5080 5081 *ctxp = ctx; 5082 5083 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5084 iflib_add_device_sysctl_post(ctx); 5085 ctx->ifc_flags |= IFC_INIT_DONE; 5086 CTX_UNLOCK(ctx); 5087 5088 return (0); 5089 fail_detach: 5090 ether_ifdetach(ctx->ifc_ifp); 5091 fail_queues: 5092 iflib_tx_structures_free(ctx); 5093 iflib_rx_structures_free(ctx); 5094 iflib_tqg_detach(ctx); 5095 fail_iflib_detach: 5096 IFDI_DETACH(ctx); 5097 fail_unlock: 5098 CTX_UNLOCK(ctx); 5099 iflib_deregister(ctx); 5100 fail_ctx_free: 5101 free(ctx->ifc_softc, M_IFLIB); 5102 free(ctx, M_IFLIB); 5103 return (err); 5104 } 5105 5106 int 5107 iflib_pseudo_deregister(if_ctx_t ctx) 5108 { 5109 if_t ifp = ctx->ifc_ifp; 5110 if_shared_ctx_t sctx = ctx->ifc_sctx; 5111 5112 /* Unregister VLAN event handlers early */ 5113 iflib_unregister_vlan_handlers(ctx); 5114 5115 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5116 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) { 5117 bpfdetach(ifp); 5118 if_detach(ifp); 5119 } else { 5120 ether_ifdetach(ifp); 5121 } 5122 5123 iflib_tqg_detach(ctx); 5124 iflib_tx_structures_free(ctx); 5125 iflib_rx_structures_free(ctx); 5126 5127 iflib_deregister(ctx); 5128 5129 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5130 free(ctx->ifc_softc, M_IFLIB); 5131 free(ctx, M_IFLIB); 5132 return (0); 5133 } 5134 5135 int 5136 iflib_device_attach(device_t dev) 5137 { 5138 if_ctx_t ctx; 5139 if_shared_ctx_t sctx; 5140 5141 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5142 return (ENOTSUP); 5143 5144 pci_enable_busmaster(dev); 5145 5146 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5147 } 5148 5149 int 5150 iflib_device_deregister(if_ctx_t ctx) 5151 { 5152 if_t ifp = ctx->ifc_ifp; 5153 device_t dev = ctx->ifc_dev; 5154 5155 /* Make sure VLANS are not using driver */ 5156 if (if_vlantrunkinuse(ifp)) { 5157 device_printf(dev, "Vlan in use, detach first\n"); 5158 return (EBUSY); 5159 } 5160 #ifdef PCI_IOV 5161 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5162 device_printf(dev, "SR-IOV in use; detach first.\n"); 5163 return (EBUSY); 5164 } 5165 #endif 5166 5167 STATE_LOCK(ctx); 5168 ctx->ifc_flags |= IFC_IN_DETACH; 5169 STATE_UNLOCK(ctx); 5170 5171 /* Unregister VLAN handlers before calling iflib_stop() */ 5172 iflib_unregister_vlan_handlers(ctx); 5173 5174 iflib_netmap_detach(ifp); 5175 ether_ifdetach(ifp); 5176 5177 CTX_LOCK(ctx); 5178 iflib_stop(ctx); 5179 CTX_UNLOCK(ctx); 5180 5181 iflib_rem_pfil(ctx); 5182 if (ctx->ifc_led_dev != NULL) 5183 led_destroy(ctx->ifc_led_dev); 5184 5185 iflib_tqg_detach(ctx); 5186 CTX_LOCK(ctx); 5187 IFDI_DETACH(ctx); 5188 CTX_UNLOCK(ctx); 5189 5190 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5191 iflib_free_intr_mem(ctx); 5192 5193 bus_generic_detach(dev); 5194 5195 iflib_tx_structures_free(ctx); 5196 iflib_rx_structures_free(ctx); 5197 5198 iflib_deregister(ctx); 5199 5200 device_set_softc(ctx->ifc_dev, NULL); 5201 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5202 free(ctx->ifc_softc, M_IFLIB); 5203 unref_ctx_core_offset(ctx); 5204 free(ctx, M_IFLIB); 5205 return (0); 5206 } 5207 5208 static void 5209 iflib_tqg_detach(if_ctx_t ctx) 5210 { 5211 iflib_txq_t txq; 5212 iflib_rxq_t rxq; 5213 int i; 5214 struct taskqgroup *tqg; 5215 5216 /* XXX drain any dependent tasks */ 5217 tqg = qgroup_if_io_tqg; 5218 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5219 callout_drain(&txq->ift_timer); 5220 #ifdef DEV_NETMAP 5221 callout_drain(&txq->ift_netmap_timer); 5222 #endif /* DEV_NETMAP */ 5223 if (txq->ift_task.gt_uniq != NULL) 5224 taskqgroup_detach(tqg, &txq->ift_task); 5225 } 5226 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5227 if (rxq->ifr_task.gt_uniq != NULL) 5228 taskqgroup_detach(tqg, &rxq->ifr_task); 5229 } 5230 tqg = qgroup_if_config_tqg; 5231 if (ctx->ifc_admin_task.gt_uniq != NULL) 5232 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5233 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5234 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5235 } 5236 5237 static void 5238 iflib_free_intr_mem(if_ctx_t ctx) 5239 { 5240 5241 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5242 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5243 } 5244 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5245 pci_release_msi(ctx->ifc_dev); 5246 } 5247 if (ctx->ifc_msix_mem != NULL) { 5248 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5249 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5250 ctx->ifc_msix_mem = NULL; 5251 } 5252 } 5253 5254 int 5255 iflib_device_detach(device_t dev) 5256 { 5257 if_ctx_t ctx = device_get_softc(dev); 5258 5259 return (iflib_device_deregister(ctx)); 5260 } 5261 5262 int 5263 iflib_device_suspend(device_t dev) 5264 { 5265 if_ctx_t ctx = device_get_softc(dev); 5266 5267 CTX_LOCK(ctx); 5268 IFDI_SUSPEND(ctx); 5269 CTX_UNLOCK(ctx); 5270 5271 return bus_generic_suspend(dev); 5272 } 5273 int 5274 iflib_device_shutdown(device_t dev) 5275 { 5276 if_ctx_t ctx = device_get_softc(dev); 5277 5278 CTX_LOCK(ctx); 5279 IFDI_SHUTDOWN(ctx); 5280 CTX_UNLOCK(ctx); 5281 5282 return bus_generic_suspend(dev); 5283 } 5284 5285 int 5286 iflib_device_resume(device_t dev) 5287 { 5288 if_ctx_t ctx = device_get_softc(dev); 5289 iflib_txq_t txq = ctx->ifc_txqs; 5290 5291 CTX_LOCK(ctx); 5292 IFDI_RESUME(ctx); 5293 iflib_if_init_locked(ctx); 5294 CTX_UNLOCK(ctx); 5295 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5296 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5297 5298 return (bus_generic_resume(dev)); 5299 } 5300 5301 int 5302 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5303 { 5304 int error; 5305 if_ctx_t ctx = device_get_softc(dev); 5306 5307 CTX_LOCK(ctx); 5308 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5309 CTX_UNLOCK(ctx); 5310 5311 return (error); 5312 } 5313 5314 void 5315 iflib_device_iov_uninit(device_t dev) 5316 { 5317 if_ctx_t ctx = device_get_softc(dev); 5318 5319 CTX_LOCK(ctx); 5320 IFDI_IOV_UNINIT(ctx); 5321 CTX_UNLOCK(ctx); 5322 } 5323 5324 int 5325 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5326 { 5327 int error; 5328 if_ctx_t ctx = device_get_softc(dev); 5329 5330 CTX_LOCK(ctx); 5331 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5332 CTX_UNLOCK(ctx); 5333 5334 return (error); 5335 } 5336 5337 /********************************************************************* 5338 * 5339 * MODULE FUNCTION DEFINITIONS 5340 * 5341 **********************************************************************/ 5342 5343 /* 5344 * - Start a fast taskqueue thread for each core 5345 * - Start a taskqueue for control operations 5346 */ 5347 static int 5348 iflib_module_init(void) 5349 { 5350 iflib_timer_default = hz / 2; 5351 return (0); 5352 } 5353 5354 static int 5355 iflib_module_event_handler(module_t mod, int what, void *arg) 5356 { 5357 int err; 5358 5359 switch (what) { 5360 case MOD_LOAD: 5361 if ((err = iflib_module_init()) != 0) 5362 return (err); 5363 break; 5364 case MOD_UNLOAD: 5365 return (EBUSY); 5366 default: 5367 return (EOPNOTSUPP); 5368 } 5369 5370 return (0); 5371 } 5372 5373 /********************************************************************* 5374 * 5375 * PUBLIC FUNCTION DEFINITIONS 5376 * ordered as in iflib.h 5377 * 5378 **********************************************************************/ 5379 5380 static void 5381 _iflib_assert(if_shared_ctx_t sctx) 5382 { 5383 int i; 5384 5385 MPASS(sctx->isc_tx_maxsize); 5386 MPASS(sctx->isc_tx_maxsegsize); 5387 5388 MPASS(sctx->isc_rx_maxsize); 5389 MPASS(sctx->isc_rx_nsegments); 5390 MPASS(sctx->isc_rx_maxsegsize); 5391 5392 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5393 for (i = 0; i < sctx->isc_nrxqs; i++) { 5394 MPASS(sctx->isc_nrxd_min[i]); 5395 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5396 MPASS(sctx->isc_nrxd_max[i]); 5397 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5398 MPASS(sctx->isc_nrxd_default[i]); 5399 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5400 } 5401 5402 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5403 for (i = 0; i < sctx->isc_ntxqs; i++) { 5404 MPASS(sctx->isc_ntxd_min[i]); 5405 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5406 MPASS(sctx->isc_ntxd_max[i]); 5407 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5408 MPASS(sctx->isc_ntxd_default[i]); 5409 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5410 } 5411 } 5412 5413 static void 5414 _iflib_pre_assert(if_softc_ctx_t scctx) 5415 { 5416 5417 MPASS(scctx->isc_txrx->ift_txd_encap); 5418 MPASS(scctx->isc_txrx->ift_txd_flush); 5419 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5420 MPASS(scctx->isc_txrx->ift_rxd_available); 5421 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5422 MPASS(scctx->isc_txrx->ift_rxd_refill); 5423 MPASS(scctx->isc_txrx->ift_rxd_flush); 5424 } 5425 5426 static int 5427 iflib_register(if_ctx_t ctx) 5428 { 5429 if_shared_ctx_t sctx = ctx->ifc_sctx; 5430 driver_t *driver = sctx->isc_driver; 5431 device_t dev = ctx->ifc_dev; 5432 if_t ifp; 5433 u_char type; 5434 int iflags; 5435 5436 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0) 5437 _iflib_assert(sctx); 5438 5439 CTX_LOCK_INIT(ctx); 5440 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5441 if (sctx->isc_flags & IFLIB_PSEUDO) { 5442 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) 5443 type = IFT_ETHER; 5444 else 5445 type = IFT_PPP; 5446 } else 5447 type = IFT_ETHER; 5448 ifp = ctx->ifc_ifp = if_alloc(type); 5449 if (ifp == NULL) { 5450 device_printf(dev, "can not allocate ifnet structure\n"); 5451 return (ENOMEM); 5452 } 5453 5454 /* 5455 * Initialize our context's device specific methods 5456 */ 5457 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5458 kobj_class_compile((kobj_class_t) driver); 5459 5460 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5461 if_setsoftc(ifp, ctx); 5462 if_setdev(ifp, dev); 5463 if_setinitfn(ifp, iflib_if_init); 5464 if_setioctlfn(ifp, iflib_if_ioctl); 5465 #ifdef ALTQ 5466 if_setstartfn(ifp, iflib_altq_if_start); 5467 if_settransmitfn(ifp, iflib_altq_if_transmit); 5468 if_setsendqready(ifp); 5469 #else 5470 if_settransmitfn(ifp, iflib_if_transmit); 5471 #endif 5472 if_setqflushfn(ifp, iflib_if_qflush); 5473 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH; 5474 5475 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5476 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) 5477 iflags |= IFF_POINTOPOINT; 5478 else 5479 iflags |= IFF_BROADCAST | IFF_SIMPLEX; 5480 if_setflags(ifp, iflags); 5481 ctx->ifc_vlan_attach_event = 5482 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5483 EVENTHANDLER_PRI_FIRST); 5484 ctx->ifc_vlan_detach_event = 5485 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5486 EVENTHANDLER_PRI_FIRST); 5487 5488 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5489 ctx->ifc_mediap = &ctx->ifc_media; 5490 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5491 iflib_media_change, iflib_media_status); 5492 } 5493 return (0); 5494 } 5495 5496 static void 5497 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5498 { 5499 /* Unregister VLAN events */ 5500 if (ctx->ifc_vlan_attach_event != NULL) { 5501 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5502 ctx->ifc_vlan_attach_event = NULL; 5503 } 5504 if (ctx->ifc_vlan_detach_event != NULL) { 5505 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5506 ctx->ifc_vlan_detach_event = NULL; 5507 } 5508 5509 } 5510 5511 static void 5512 iflib_deregister(if_ctx_t ctx) 5513 { 5514 if_t ifp = ctx->ifc_ifp; 5515 5516 /* Remove all media */ 5517 ifmedia_removeall(&ctx->ifc_media); 5518 5519 /* Ensure that VLAN event handlers are unregistered */ 5520 iflib_unregister_vlan_handlers(ctx); 5521 5522 /* Release kobject reference */ 5523 kobj_delete((kobj_t) ctx, NULL); 5524 5525 /* Free the ifnet structure */ 5526 if_free(ifp); 5527 5528 STATE_LOCK_DESTROY(ctx); 5529 5530 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5531 CTX_LOCK_DESTROY(ctx); 5532 } 5533 5534 static int 5535 iflib_queues_alloc(if_ctx_t ctx) 5536 { 5537 if_shared_ctx_t sctx = ctx->ifc_sctx; 5538 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5539 device_t dev = ctx->ifc_dev; 5540 int nrxqsets = scctx->isc_nrxqsets; 5541 int ntxqsets = scctx->isc_ntxqsets; 5542 iflib_txq_t txq; 5543 iflib_rxq_t rxq; 5544 iflib_fl_t fl = NULL; 5545 int i, j, cpu, err, txconf, rxconf; 5546 iflib_dma_info_t ifdip; 5547 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5548 uint32_t *txqsizes = scctx->isc_txqsizes; 5549 uint8_t nrxqs = sctx->isc_nrxqs; 5550 uint8_t ntxqs = sctx->isc_ntxqs; 5551 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5552 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0); 5553 caddr_t *vaddrs; 5554 uint64_t *paddrs; 5555 5556 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5557 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5558 KASSERT(nrxqs >= fl_offset + nfree_lists, 5559 ("there must be at least a rxq for each free list")); 5560 5561 /* Allocate the TX ring struct memory */ 5562 if (!(ctx->ifc_txqs = 5563 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5564 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5565 device_printf(dev, "Unable to allocate TX ring memory\n"); 5566 err = ENOMEM; 5567 goto fail; 5568 } 5569 5570 /* Now allocate the RX */ 5571 if (!(ctx->ifc_rxqs = 5572 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5573 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5574 device_printf(dev, "Unable to allocate RX ring memory\n"); 5575 err = ENOMEM; 5576 goto rx_fail; 5577 } 5578 5579 txq = ctx->ifc_txqs; 5580 rxq = ctx->ifc_rxqs; 5581 5582 /* 5583 * XXX handle allocation failure 5584 */ 5585 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5586 /* Set up some basics */ 5587 5588 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5589 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5590 device_printf(dev, 5591 "Unable to allocate TX DMA info memory\n"); 5592 err = ENOMEM; 5593 goto err_tx_desc; 5594 } 5595 txq->ift_ifdi = ifdip; 5596 for (j = 0; j < ntxqs; j++, ifdip++) { 5597 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5598 device_printf(dev, 5599 "Unable to allocate TX descriptors\n"); 5600 err = ENOMEM; 5601 goto err_tx_desc; 5602 } 5603 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5604 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5605 } 5606 txq->ift_ctx = ctx; 5607 txq->ift_id = i; 5608 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5609 txq->ift_br_offset = 1; 5610 } else { 5611 txq->ift_br_offset = 0; 5612 } 5613 5614 if (iflib_txsd_alloc(txq)) { 5615 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5616 err = ENOMEM; 5617 goto err_tx_desc; 5618 } 5619 5620 /* Initialize the TX lock */ 5621 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5622 device_get_nameunit(dev), txq->ift_id); 5623 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5624 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5625 txq->ift_timer.c_cpu = cpu; 5626 #ifdef DEV_NETMAP 5627 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 5628 txq->ift_netmap_timer.c_cpu = cpu; 5629 #endif /* DEV_NETMAP */ 5630 5631 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5632 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5633 if (err) { 5634 /* XXX free any allocated rings */ 5635 device_printf(dev, "Unable to allocate buf_ring\n"); 5636 goto err_tx_desc; 5637 } 5638 } 5639 5640 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5641 /* Set up some basics */ 5642 callout_init(&rxq->ifr_watchdog, 1); 5643 5644 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5645 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5646 device_printf(dev, 5647 "Unable to allocate RX DMA info memory\n"); 5648 err = ENOMEM; 5649 goto err_tx_desc; 5650 } 5651 5652 rxq->ifr_ifdi = ifdip; 5653 /* XXX this needs to be changed if #rx queues != #tx queues */ 5654 rxq->ifr_ntxqirq = 1; 5655 rxq->ifr_txqid[0] = i; 5656 for (j = 0; j < nrxqs; j++, ifdip++) { 5657 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5658 device_printf(dev, 5659 "Unable to allocate RX descriptors\n"); 5660 err = ENOMEM; 5661 goto err_tx_desc; 5662 } 5663 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5664 } 5665 rxq->ifr_ctx = ctx; 5666 rxq->ifr_id = i; 5667 rxq->ifr_fl_offset = fl_offset; 5668 rxq->ifr_nfl = nfree_lists; 5669 if (!(fl = 5670 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5671 device_printf(dev, "Unable to allocate free list memory\n"); 5672 err = ENOMEM; 5673 goto err_tx_desc; 5674 } 5675 rxq->ifr_fl = fl; 5676 for (j = 0; j < nfree_lists; j++) { 5677 fl[j].ifl_rxq = rxq; 5678 fl[j].ifl_id = j; 5679 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5680 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5681 } 5682 /* Allocate receive buffers for the ring */ 5683 if (iflib_rxsd_alloc(rxq)) { 5684 device_printf(dev, 5685 "Critical Failure setting up receive buffers\n"); 5686 err = ENOMEM; 5687 goto err_rx_desc; 5688 } 5689 5690 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5691 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5692 M_WAITOK); 5693 } 5694 5695 /* TXQs */ 5696 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5697 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5698 for (i = 0; i < ntxqsets; i++) { 5699 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5700 5701 for (j = 0; j < ntxqs; j++, di++) { 5702 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5703 paddrs[i*ntxqs + j] = di->idi_paddr; 5704 } 5705 } 5706 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5707 device_printf(ctx->ifc_dev, 5708 "Unable to allocate device TX queue\n"); 5709 iflib_tx_structures_free(ctx); 5710 free(vaddrs, M_IFLIB); 5711 free(paddrs, M_IFLIB); 5712 goto err_rx_desc; 5713 } 5714 free(vaddrs, M_IFLIB); 5715 free(paddrs, M_IFLIB); 5716 5717 /* RXQs */ 5718 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5719 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5720 for (i = 0; i < nrxqsets; i++) { 5721 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5722 5723 for (j = 0; j < nrxqs; j++, di++) { 5724 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5725 paddrs[i*nrxqs + j] = di->idi_paddr; 5726 } 5727 } 5728 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5729 device_printf(ctx->ifc_dev, 5730 "Unable to allocate device RX queue\n"); 5731 iflib_tx_structures_free(ctx); 5732 free(vaddrs, M_IFLIB); 5733 free(paddrs, M_IFLIB); 5734 goto err_rx_desc; 5735 } 5736 free(vaddrs, M_IFLIB); 5737 free(paddrs, M_IFLIB); 5738 5739 return (0); 5740 5741 /* XXX handle allocation failure changes */ 5742 err_rx_desc: 5743 err_tx_desc: 5744 rx_fail: 5745 if (ctx->ifc_rxqs != NULL) 5746 free(ctx->ifc_rxqs, M_IFLIB); 5747 ctx->ifc_rxqs = NULL; 5748 if (ctx->ifc_txqs != NULL) 5749 free(ctx->ifc_txqs, M_IFLIB); 5750 ctx->ifc_txqs = NULL; 5751 fail: 5752 return (err); 5753 } 5754 5755 static int 5756 iflib_tx_structures_setup(if_ctx_t ctx) 5757 { 5758 iflib_txq_t txq = ctx->ifc_txqs; 5759 int i; 5760 5761 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5762 iflib_txq_setup(txq); 5763 5764 return (0); 5765 } 5766 5767 static void 5768 iflib_tx_structures_free(if_ctx_t ctx) 5769 { 5770 iflib_txq_t txq = ctx->ifc_txqs; 5771 if_shared_ctx_t sctx = ctx->ifc_sctx; 5772 int i, j; 5773 5774 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5775 for (j = 0; j < sctx->isc_ntxqs; j++) 5776 iflib_dma_free(&txq->ift_ifdi[j]); 5777 iflib_txq_destroy(txq); 5778 } 5779 free(ctx->ifc_txqs, M_IFLIB); 5780 ctx->ifc_txqs = NULL; 5781 IFDI_QUEUES_FREE(ctx); 5782 } 5783 5784 /********************************************************************* 5785 * 5786 * Initialize all receive rings. 5787 * 5788 **********************************************************************/ 5789 static int 5790 iflib_rx_structures_setup(if_ctx_t ctx) 5791 { 5792 iflib_rxq_t rxq = ctx->ifc_rxqs; 5793 int q; 5794 #if defined(INET6) || defined(INET) 5795 int err, i; 5796 #endif 5797 5798 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5799 #if defined(INET6) || defined(INET) 5800 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) { 5801 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5802 TCP_LRO_ENTRIES, min(1024, 5803 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 5804 if (err != 0) { 5805 device_printf(ctx->ifc_dev, 5806 "LRO Initialization failed!\n"); 5807 goto fail; 5808 } 5809 } 5810 #endif 5811 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5812 } 5813 return (0); 5814 #if defined(INET6) || defined(INET) 5815 fail: 5816 /* 5817 * Free LRO resources allocated so far, we will only handle 5818 * the rings that completed, the failing case will have 5819 * cleaned up for itself. 'q' failed, so its the terminus. 5820 */ 5821 rxq = ctx->ifc_rxqs; 5822 for (i = 0; i < q; ++i, rxq++) { 5823 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5824 tcp_lro_free(&rxq->ifr_lc); 5825 } 5826 return (err); 5827 #endif 5828 } 5829 5830 /********************************************************************* 5831 * 5832 * Free all receive rings. 5833 * 5834 **********************************************************************/ 5835 static void 5836 iflib_rx_structures_free(if_ctx_t ctx) 5837 { 5838 iflib_rxq_t rxq = ctx->ifc_rxqs; 5839 if_shared_ctx_t sctx = ctx->ifc_sctx; 5840 int i, j; 5841 5842 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5843 for (j = 0; j < sctx->isc_nrxqs; j++) 5844 iflib_dma_free(&rxq->ifr_ifdi[j]); 5845 iflib_rx_sds_free(rxq); 5846 #if defined(INET6) || defined(INET) 5847 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5848 tcp_lro_free(&rxq->ifr_lc); 5849 #endif 5850 } 5851 free(ctx->ifc_rxqs, M_IFLIB); 5852 ctx->ifc_rxqs = NULL; 5853 } 5854 5855 static int 5856 iflib_qset_structures_setup(if_ctx_t ctx) 5857 { 5858 int err; 5859 5860 /* 5861 * It is expected that the caller takes care of freeing queues if this 5862 * fails. 5863 */ 5864 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5865 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5866 return (err); 5867 } 5868 5869 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5870 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5871 5872 return (err); 5873 } 5874 5875 int 5876 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5877 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5878 { 5879 5880 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5881 } 5882 5883 #ifdef SMP 5884 static int 5885 find_nth(if_ctx_t ctx, int qid) 5886 { 5887 cpuset_t cpus; 5888 int i, cpuid, eqid, count; 5889 5890 CPU_COPY(&ctx->ifc_cpus, &cpus); 5891 count = CPU_COUNT(&cpus); 5892 eqid = qid % count; 5893 /* clear up to the qid'th bit */ 5894 for (i = 0; i < eqid; i++) { 5895 cpuid = CPU_FFS(&cpus); 5896 MPASS(cpuid != 0); 5897 CPU_CLR(cpuid-1, &cpus); 5898 } 5899 cpuid = CPU_FFS(&cpus); 5900 MPASS(cpuid != 0); 5901 return (cpuid-1); 5902 } 5903 5904 #ifdef SCHED_ULE 5905 extern struct cpu_group *cpu_top; /* CPU topology */ 5906 5907 static int 5908 find_child_with_core(int cpu, struct cpu_group *grp) 5909 { 5910 int i; 5911 5912 if (grp->cg_children == 0) 5913 return -1; 5914 5915 MPASS(grp->cg_child); 5916 for (i = 0; i < grp->cg_children; i++) { 5917 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5918 return i; 5919 } 5920 5921 return -1; 5922 } 5923 5924 /* 5925 * Find the nth "close" core to the specified core 5926 * "close" is defined as the deepest level that shares 5927 * at least an L2 cache. With threads, this will be 5928 * threads on the same core. If the shared cache is L3 5929 * or higher, simply returns the same core. 5930 */ 5931 static int 5932 find_close_core(int cpu, int core_offset) 5933 { 5934 struct cpu_group *grp; 5935 int i; 5936 int fcpu; 5937 cpuset_t cs; 5938 5939 grp = cpu_top; 5940 if (grp == NULL) 5941 return cpu; 5942 i = 0; 5943 while ((i = find_child_with_core(cpu, grp)) != -1) { 5944 /* If the child only has one cpu, don't descend */ 5945 if (grp->cg_child[i].cg_count <= 1) 5946 break; 5947 grp = &grp->cg_child[i]; 5948 } 5949 5950 /* If they don't share at least an L2 cache, use the same CPU */ 5951 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5952 return cpu; 5953 5954 /* Now pick one */ 5955 CPU_COPY(&grp->cg_mask, &cs); 5956 5957 /* Add the selected CPU offset to core offset. */ 5958 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5959 if (fcpu - 1 == cpu) 5960 break; 5961 CPU_CLR(fcpu - 1, &cs); 5962 } 5963 MPASS(fcpu); 5964 5965 core_offset += i; 5966 5967 CPU_COPY(&grp->cg_mask, &cs); 5968 for (i = core_offset % grp->cg_count; i > 0; i--) { 5969 MPASS(CPU_FFS(&cs)); 5970 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5971 } 5972 MPASS(CPU_FFS(&cs)); 5973 return CPU_FFS(&cs) - 1; 5974 } 5975 #else 5976 static int 5977 find_close_core(int cpu, int core_offset __unused) 5978 { 5979 return cpu; 5980 } 5981 #endif 5982 5983 static int 5984 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5985 { 5986 switch (type) { 5987 case IFLIB_INTR_TX: 5988 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5989 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5990 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5991 case IFLIB_INTR_RX: 5992 case IFLIB_INTR_RXTX: 5993 /* RX queues get the specified core */ 5994 return qid / CPU_COUNT(&ctx->ifc_cpus); 5995 default: 5996 return -1; 5997 } 5998 } 5999 #else 6000 #define get_core_offset(ctx, type, qid) CPU_FIRST() 6001 #define find_close_core(cpuid, tid) CPU_FIRST() 6002 #define find_nth(ctx, gid) CPU_FIRST() 6003 #endif 6004 6005 /* Just to avoid copy/paste */ 6006 static inline int 6007 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6008 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 6009 const char *name) 6010 { 6011 device_t dev; 6012 int co, cpuid, err, tid; 6013 6014 dev = ctx->ifc_dev; 6015 co = ctx->ifc_sysctl_core_offset; 6016 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX) 6017 co += ctx->ifc_softc_ctx.isc_nrxqsets; 6018 cpuid = find_nth(ctx, qid + co); 6019 tid = get_core_offset(ctx, type, qid); 6020 if (tid < 0) { 6021 device_printf(dev, "get_core_offset failed\n"); 6022 return (EOPNOTSUPP); 6023 } 6024 cpuid = find_close_core(cpuid, tid); 6025 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 6026 name); 6027 if (err) { 6028 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6029 return (err); 6030 } 6031 #ifdef notyet 6032 if (cpuid > ctx->ifc_cpuid_highest) 6033 ctx->ifc_cpuid_highest = cpuid; 6034 #endif 6035 return (0); 6036 } 6037 6038 int 6039 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6040 iflib_intr_type_t type, driver_filter_t *filter, 6041 void *filter_arg, int qid, const char *name) 6042 { 6043 device_t dev; 6044 struct grouptask *gtask; 6045 struct taskqgroup *tqg; 6046 iflib_filter_info_t info; 6047 gtask_fn_t *fn; 6048 int tqrid, err; 6049 driver_filter_t *intr_fast; 6050 void *q; 6051 6052 info = &ctx->ifc_filter_info; 6053 tqrid = rid; 6054 6055 switch (type) { 6056 /* XXX merge tx/rx for netmap? */ 6057 case IFLIB_INTR_TX: 6058 q = &ctx->ifc_txqs[qid]; 6059 info = &ctx->ifc_txqs[qid].ift_filter_info; 6060 gtask = &ctx->ifc_txqs[qid].ift_task; 6061 tqg = qgroup_if_io_tqg; 6062 fn = _task_fn_tx; 6063 intr_fast = iflib_fast_intr; 6064 GROUPTASK_INIT(gtask, 0, fn, q); 6065 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6066 break; 6067 case IFLIB_INTR_RX: 6068 q = &ctx->ifc_rxqs[qid]; 6069 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6070 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6071 tqg = qgroup_if_io_tqg; 6072 fn = _task_fn_rx; 6073 intr_fast = iflib_fast_intr; 6074 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6075 break; 6076 case IFLIB_INTR_RXTX: 6077 q = &ctx->ifc_rxqs[qid]; 6078 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6079 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6080 tqg = qgroup_if_io_tqg; 6081 fn = _task_fn_rx; 6082 intr_fast = iflib_fast_intr_rxtx; 6083 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6084 break; 6085 case IFLIB_INTR_ADMIN: 6086 q = ctx; 6087 tqrid = -1; 6088 info = &ctx->ifc_filter_info; 6089 gtask = &ctx->ifc_admin_task; 6090 tqg = qgroup_if_config_tqg; 6091 fn = _task_fn_admin; 6092 intr_fast = iflib_fast_intr_ctx; 6093 break; 6094 default: 6095 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6096 __func__); 6097 return (EINVAL); 6098 } 6099 6100 info->ifi_filter = filter; 6101 info->ifi_filter_arg = filter_arg; 6102 info->ifi_task = gtask; 6103 info->ifi_ctx = q; 6104 6105 dev = ctx->ifc_dev; 6106 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6107 if (err != 0) { 6108 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6109 return (err); 6110 } 6111 if (type == IFLIB_INTR_ADMIN) 6112 return (0); 6113 6114 if (tqrid != -1) { 6115 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6116 q, name); 6117 if (err) 6118 return (err); 6119 } else { 6120 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6121 } 6122 6123 return (0); 6124 } 6125 6126 void 6127 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6128 { 6129 struct grouptask *gtask; 6130 struct taskqgroup *tqg; 6131 gtask_fn_t *fn; 6132 void *q; 6133 int err; 6134 6135 switch (type) { 6136 case IFLIB_INTR_TX: 6137 q = &ctx->ifc_txqs[qid]; 6138 gtask = &ctx->ifc_txqs[qid].ift_task; 6139 tqg = qgroup_if_io_tqg; 6140 fn = _task_fn_tx; 6141 GROUPTASK_INIT(gtask, 0, fn, q); 6142 break; 6143 case IFLIB_INTR_RX: 6144 q = &ctx->ifc_rxqs[qid]; 6145 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6146 tqg = qgroup_if_io_tqg; 6147 fn = _task_fn_rx; 6148 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6149 break; 6150 case IFLIB_INTR_IOV: 6151 q = ctx; 6152 gtask = &ctx->ifc_vflr_task; 6153 tqg = qgroup_if_config_tqg; 6154 fn = _task_fn_iov; 6155 GROUPTASK_INIT(gtask, 0, fn, q); 6156 break; 6157 default: 6158 panic("unknown net intr type"); 6159 } 6160 if (irq != NULL) { 6161 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6162 q, name); 6163 if (err) 6164 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 6165 irq->ii_res, name); 6166 } else { 6167 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 6168 } 6169 } 6170 6171 void 6172 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6173 { 6174 6175 if (irq->ii_tag) 6176 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6177 6178 if (irq->ii_res) 6179 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6180 rman_get_rid(irq->ii_res), irq->ii_res); 6181 } 6182 6183 static int 6184 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6185 { 6186 iflib_txq_t txq = ctx->ifc_txqs; 6187 iflib_rxq_t rxq = ctx->ifc_rxqs; 6188 if_irq_t irq = &ctx->ifc_legacy_irq; 6189 iflib_filter_info_t info; 6190 device_t dev; 6191 struct grouptask *gtask; 6192 struct resource *res; 6193 struct taskqgroup *tqg; 6194 void *q; 6195 int err, tqrid; 6196 bool rx_only; 6197 6198 q = &ctx->ifc_rxqs[0]; 6199 info = &rxq[0].ifr_filter_info; 6200 gtask = &rxq[0].ifr_task; 6201 tqg = qgroup_if_io_tqg; 6202 tqrid = *rid; 6203 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6204 6205 ctx->ifc_flags |= IFC_LEGACY; 6206 info->ifi_filter = filter; 6207 info->ifi_filter_arg = filter_arg; 6208 info->ifi_task = gtask; 6209 info->ifi_ctx = rx_only ? ctx : q; 6210 6211 dev = ctx->ifc_dev; 6212 /* We allocate a single interrupt resource */ 6213 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6214 iflib_fast_intr_rxtx, NULL, info, name); 6215 if (err != 0) 6216 return (err); 6217 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6218 res = irq->ii_res; 6219 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6220 6221 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6222 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6223 "tx"); 6224 return (0); 6225 } 6226 6227 void 6228 iflib_led_create(if_ctx_t ctx) 6229 { 6230 6231 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6232 device_get_nameunit(ctx->ifc_dev)); 6233 } 6234 6235 void 6236 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6237 { 6238 6239 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6240 } 6241 6242 void 6243 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6244 { 6245 6246 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6247 } 6248 6249 void 6250 iflib_admin_intr_deferred(if_ctx_t ctx) 6251 { 6252 6253 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6254 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6255 } 6256 6257 void 6258 iflib_iov_intr_deferred(if_ctx_t ctx) 6259 { 6260 6261 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6262 } 6263 6264 void 6265 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6266 { 6267 6268 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6269 name); 6270 } 6271 6272 void 6273 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6274 const char *name) 6275 { 6276 6277 GROUPTASK_INIT(gtask, 0, fn, ctx); 6278 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6279 name); 6280 } 6281 6282 void 6283 iflib_config_gtask_deinit(struct grouptask *gtask) 6284 { 6285 6286 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6287 } 6288 6289 void 6290 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6291 { 6292 if_t ifp = ctx->ifc_ifp; 6293 iflib_txq_t txq = ctx->ifc_txqs; 6294 6295 if_setbaudrate(ifp, baudrate); 6296 if (baudrate >= IF_Gbps(10)) { 6297 STATE_LOCK(ctx); 6298 ctx->ifc_flags |= IFC_PREFETCH; 6299 STATE_UNLOCK(ctx); 6300 } 6301 /* If link down, disable watchdog */ 6302 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6303 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6304 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6305 } 6306 ctx->ifc_link_state = link_state; 6307 if_link_state_change(ifp, link_state); 6308 } 6309 6310 static int 6311 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6312 { 6313 int credits; 6314 #ifdef INVARIANTS 6315 int credits_pre = txq->ift_cidx_processed; 6316 #endif 6317 6318 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6319 BUS_DMASYNC_POSTREAD); 6320 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6321 return (0); 6322 6323 txq->ift_processed += credits; 6324 txq->ift_cidx_processed += credits; 6325 6326 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6327 if (txq->ift_cidx_processed >= txq->ift_size) 6328 txq->ift_cidx_processed -= txq->ift_size; 6329 return (credits); 6330 } 6331 6332 static int 6333 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6334 { 6335 iflib_fl_t fl; 6336 u_int i; 6337 6338 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6339 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6340 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6341 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6342 budget)); 6343 } 6344 6345 void 6346 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6347 const char *description, if_int_delay_info_t info, 6348 int offset, int value) 6349 { 6350 info->iidi_ctx = ctx; 6351 info->iidi_offset = offset; 6352 info->iidi_value = value; 6353 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6354 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6355 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6356 info, 0, iflib_sysctl_int_delay, "I", description); 6357 } 6358 6359 struct sx * 6360 iflib_ctx_lock_get(if_ctx_t ctx) 6361 { 6362 6363 return (&ctx->ifc_ctx_sx); 6364 } 6365 6366 static int 6367 iflib_msix_init(if_ctx_t ctx) 6368 { 6369 device_t dev = ctx->ifc_dev; 6370 if_shared_ctx_t sctx = ctx->ifc_sctx; 6371 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6372 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6373 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6374 6375 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6376 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6377 6378 if (bootverbose) 6379 device_printf(dev, "msix_init qsets capped at %d\n", 6380 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6381 6382 /* Override by tuneable */ 6383 if (scctx->isc_disable_msix) 6384 goto msi; 6385 6386 /* First try MSI-X */ 6387 if ((msgs = pci_msix_count(dev)) == 0) { 6388 if (bootverbose) 6389 device_printf(dev, "MSI-X not supported or disabled\n"); 6390 goto msi; 6391 } 6392 6393 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6394 /* 6395 * bar == -1 => "trust me I know what I'm doing" 6396 * Some drivers are for hardware that is so shoddily 6397 * documented that no one knows which bars are which 6398 * so the developer has to map all bars. This hack 6399 * allows shoddy garbage to use MSI-X in this framework. 6400 */ 6401 if (bar != -1) { 6402 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6403 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6404 if (ctx->ifc_msix_mem == NULL) { 6405 device_printf(dev, "Unable to map MSI-X table\n"); 6406 goto msi; 6407 } 6408 } 6409 6410 admincnt = sctx->isc_admin_intrcnt; 6411 #if IFLIB_DEBUG 6412 /* use only 1 qset in debug mode */ 6413 queuemsgs = min(msgs - admincnt, 1); 6414 #else 6415 queuemsgs = msgs - admincnt; 6416 #endif 6417 #ifdef RSS 6418 queues = imin(queuemsgs, rss_getnumbuckets()); 6419 #else 6420 queues = queuemsgs; 6421 #endif 6422 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6423 if (bootverbose) 6424 device_printf(dev, 6425 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6426 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6427 #ifdef RSS 6428 /* If we're doing RSS, clamp at the number of RSS buckets */ 6429 if (queues > rss_getnumbuckets()) 6430 queues = rss_getnumbuckets(); 6431 #endif 6432 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6433 rx_queues = iflib_num_rx_queues; 6434 else 6435 rx_queues = queues; 6436 6437 if (rx_queues > scctx->isc_nrxqsets) 6438 rx_queues = scctx->isc_nrxqsets; 6439 6440 /* 6441 * We want this to be all logical CPUs by default 6442 */ 6443 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6444 tx_queues = iflib_num_tx_queues; 6445 else 6446 tx_queues = mp_ncpus; 6447 6448 if (tx_queues > scctx->isc_ntxqsets) 6449 tx_queues = scctx->isc_ntxqsets; 6450 6451 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6452 #ifdef INVARIANTS 6453 if (tx_queues != rx_queues) 6454 device_printf(dev, 6455 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6456 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6457 #endif 6458 tx_queues = min(rx_queues, tx_queues); 6459 rx_queues = min(rx_queues, tx_queues); 6460 } 6461 6462 vectors = rx_queues + admincnt; 6463 if (msgs < vectors) { 6464 device_printf(dev, 6465 "insufficient number of MSI-X vectors " 6466 "(supported %d, need %d)\n", msgs, vectors); 6467 goto msi; 6468 } 6469 6470 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6471 tx_queues); 6472 msgs = vectors; 6473 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6474 if (vectors != msgs) { 6475 device_printf(dev, 6476 "Unable to allocate sufficient MSI-X vectors " 6477 "(got %d, need %d)\n", vectors, msgs); 6478 pci_release_msi(dev); 6479 if (bar != -1) { 6480 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6481 ctx->ifc_msix_mem); 6482 ctx->ifc_msix_mem = NULL; 6483 } 6484 goto msi; 6485 } 6486 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6487 vectors); 6488 scctx->isc_vectors = vectors; 6489 scctx->isc_nrxqsets = rx_queues; 6490 scctx->isc_ntxqsets = tx_queues; 6491 scctx->isc_intr = IFLIB_INTR_MSIX; 6492 6493 return (vectors); 6494 } else { 6495 device_printf(dev, 6496 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6497 err); 6498 if (bar != -1) { 6499 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6500 ctx->ifc_msix_mem); 6501 ctx->ifc_msix_mem = NULL; 6502 } 6503 } 6504 6505 msi: 6506 vectors = pci_msi_count(dev); 6507 scctx->isc_nrxqsets = 1; 6508 scctx->isc_ntxqsets = 1; 6509 scctx->isc_vectors = vectors; 6510 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6511 device_printf(dev,"Using an MSI interrupt\n"); 6512 scctx->isc_intr = IFLIB_INTR_MSI; 6513 } else { 6514 scctx->isc_vectors = 1; 6515 device_printf(dev,"Using a Legacy interrupt\n"); 6516 scctx->isc_intr = IFLIB_INTR_LEGACY; 6517 } 6518 6519 return (vectors); 6520 } 6521 6522 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6523 6524 static int 6525 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6526 { 6527 int rc; 6528 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6529 struct sbuf *sb; 6530 const char *ring_state = "UNKNOWN"; 6531 6532 /* XXX needed ? */ 6533 rc = sysctl_wire_old_buffer(req, 0); 6534 MPASS(rc == 0); 6535 if (rc != 0) 6536 return (rc); 6537 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6538 MPASS(sb != NULL); 6539 if (sb == NULL) 6540 return (ENOMEM); 6541 if (state[3] <= 3) 6542 ring_state = ring_states[state[3]]; 6543 6544 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6545 state[0], state[1], state[2], ring_state); 6546 rc = sbuf_finish(sb); 6547 sbuf_delete(sb); 6548 return(rc); 6549 } 6550 6551 enum iflib_ndesc_handler { 6552 IFLIB_NTXD_HANDLER, 6553 IFLIB_NRXD_HANDLER, 6554 }; 6555 6556 static int 6557 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6558 { 6559 if_ctx_t ctx = (void *)arg1; 6560 enum iflib_ndesc_handler type = arg2; 6561 char buf[256] = {0}; 6562 qidx_t *ndesc; 6563 char *p, *next; 6564 int nqs, rc, i; 6565 6566 nqs = 8; 6567 switch(type) { 6568 case IFLIB_NTXD_HANDLER: 6569 ndesc = ctx->ifc_sysctl_ntxds; 6570 if (ctx->ifc_sctx) 6571 nqs = ctx->ifc_sctx->isc_ntxqs; 6572 break; 6573 case IFLIB_NRXD_HANDLER: 6574 ndesc = ctx->ifc_sysctl_nrxds; 6575 if (ctx->ifc_sctx) 6576 nqs = ctx->ifc_sctx->isc_nrxqs; 6577 break; 6578 default: 6579 printf("%s: unhandled type\n", __func__); 6580 return (EINVAL); 6581 } 6582 if (nqs == 0) 6583 nqs = 8; 6584 6585 for (i=0; i<8; i++) { 6586 if (i >= nqs) 6587 break; 6588 if (i) 6589 strcat(buf, ","); 6590 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6591 } 6592 6593 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6594 if (rc || req->newptr == NULL) 6595 return rc; 6596 6597 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6598 i++, p = strsep(&next, " ,")) { 6599 ndesc[i] = strtoul(p, NULL, 10); 6600 } 6601 6602 return(rc); 6603 } 6604 6605 #define NAME_BUFLEN 32 6606 static void 6607 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6608 { 6609 device_t dev = iflib_get_dev(ctx); 6610 struct sysctl_oid_list *child, *oid_list; 6611 struct sysctl_ctx_list *ctx_list; 6612 struct sysctl_oid *node; 6613 6614 ctx_list = device_get_sysctl_ctx(dev); 6615 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6616 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6617 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 6618 oid_list = SYSCTL_CHILDREN(node); 6619 6620 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6621 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6622 "driver version"); 6623 6624 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6625 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6626 "# of txqs to use, 0 => use default #"); 6627 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6628 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6629 "# of rxqs to use, 0 => use default #"); 6630 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6631 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6632 "permit #txq != #rxq"); 6633 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6634 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6635 "disable MSI-X (default 0)"); 6636 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6637 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6638 "set the RX budget"); 6639 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6640 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6641 "cause TX to abdicate instead of running to completion"); 6642 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6643 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6644 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6645 "offset to start using cores at"); 6646 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6647 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6648 "use separate cores for TX and RX"); 6649 6650 /* XXX change for per-queue sizes */ 6651 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6652 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6653 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6654 "list of # of TX descriptors to use, 0 = use default #"); 6655 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6656 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6657 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6658 "list of # of RX descriptors to use, 0 = use default #"); 6659 } 6660 6661 static void 6662 iflib_add_device_sysctl_post(if_ctx_t ctx) 6663 { 6664 if_shared_ctx_t sctx = ctx->ifc_sctx; 6665 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6666 device_t dev = iflib_get_dev(ctx); 6667 struct sysctl_oid_list *child; 6668 struct sysctl_ctx_list *ctx_list; 6669 iflib_fl_t fl; 6670 iflib_txq_t txq; 6671 iflib_rxq_t rxq; 6672 int i, j; 6673 char namebuf[NAME_BUFLEN]; 6674 char *qfmt; 6675 struct sysctl_oid *queue_node, *fl_node, *node; 6676 struct sysctl_oid_list *queue_list, *fl_list; 6677 ctx_list = device_get_sysctl_ctx(dev); 6678 6679 node = ctx->ifc_sysctl_node; 6680 child = SYSCTL_CHILDREN(node); 6681 6682 if (scctx->isc_ntxqsets > 100) 6683 qfmt = "txq%03d"; 6684 else if (scctx->isc_ntxqsets > 10) 6685 qfmt = "txq%02d"; 6686 else 6687 qfmt = "txq%d"; 6688 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6689 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6690 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6691 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6692 queue_list = SYSCTL_CHILDREN(queue_node); 6693 #if MEMORY_LOGGING 6694 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6695 CTLFLAG_RD, 6696 &txq->ift_dequeued, "total mbufs freed"); 6697 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6698 CTLFLAG_RD, 6699 &txq->ift_enqueued, "total mbufs enqueued"); 6700 #endif 6701 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6702 CTLFLAG_RD, 6703 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6704 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6705 CTLFLAG_RD, 6706 &txq->ift_pullups, "# of times m_pullup was called"); 6707 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6708 CTLFLAG_RD, 6709 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6710 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6711 CTLFLAG_RD, 6712 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6713 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6714 CTLFLAG_RD, 6715 &txq->ift_map_failed, "# of times DMA map failed"); 6716 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6717 CTLFLAG_RD, 6718 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6719 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6720 CTLFLAG_RD, 6721 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6722 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6723 CTLFLAG_RD, 6724 &txq->ift_pidx, 1, "Producer Index"); 6725 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6726 CTLFLAG_RD, 6727 &txq->ift_cidx, 1, "Consumer Index"); 6728 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6729 CTLFLAG_RD, 6730 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6731 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6732 CTLFLAG_RD, 6733 &txq->ift_in_use, 1, "descriptors in use"); 6734 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6735 CTLFLAG_RD, 6736 &txq->ift_processed, "descriptors procesed for clean"); 6737 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6738 CTLFLAG_RD, 6739 &txq->ift_cleaned, "total cleaned"); 6740 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6741 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6742 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6743 mp_ring_state_handler, "A", "soft ring state"); 6744 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6745 CTLFLAG_RD, &txq->ift_br->enqueues, 6746 "# of enqueues to the mp_ring for this queue"); 6747 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6748 CTLFLAG_RD, &txq->ift_br->drops, 6749 "# of drops in the mp_ring for this queue"); 6750 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6751 CTLFLAG_RD, &txq->ift_br->starts, 6752 "# of normal consumer starts in the mp_ring for this queue"); 6753 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6754 CTLFLAG_RD, &txq->ift_br->stalls, 6755 "# of consumer stalls in the mp_ring for this queue"); 6756 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6757 CTLFLAG_RD, &txq->ift_br->restarts, 6758 "# of consumer restarts in the mp_ring for this queue"); 6759 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6760 CTLFLAG_RD, &txq->ift_br->abdications, 6761 "# of consumer abdications in the mp_ring for this queue"); 6762 } 6763 6764 if (scctx->isc_nrxqsets > 100) 6765 qfmt = "rxq%03d"; 6766 else if (scctx->isc_nrxqsets > 10) 6767 qfmt = "rxq%02d"; 6768 else 6769 qfmt = "rxq%d"; 6770 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6771 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6772 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6773 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6774 queue_list = SYSCTL_CHILDREN(queue_node); 6775 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6776 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6777 CTLFLAG_RD, 6778 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6779 } 6780 6781 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6782 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6783 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6784 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 6785 fl_list = SYSCTL_CHILDREN(fl_node); 6786 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6787 CTLFLAG_RD, 6788 &fl->ifl_pidx, 1, "Producer Index"); 6789 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6790 CTLFLAG_RD, 6791 &fl->ifl_cidx, 1, "Consumer Index"); 6792 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6793 CTLFLAG_RD, 6794 &fl->ifl_credits, 1, "credits available"); 6795 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 6796 CTLFLAG_RD, 6797 &fl->ifl_buf_size, 1, "buffer size"); 6798 #if MEMORY_LOGGING 6799 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6800 CTLFLAG_RD, 6801 &fl->ifl_m_enqueued, "mbufs allocated"); 6802 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6803 CTLFLAG_RD, 6804 &fl->ifl_m_dequeued, "mbufs freed"); 6805 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6806 CTLFLAG_RD, 6807 &fl->ifl_cl_enqueued, "clusters allocated"); 6808 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6809 CTLFLAG_RD, 6810 &fl->ifl_cl_dequeued, "clusters freed"); 6811 #endif 6812 } 6813 } 6814 6815 } 6816 6817 void 6818 iflib_request_reset(if_ctx_t ctx) 6819 { 6820 6821 STATE_LOCK(ctx); 6822 ctx->ifc_flags |= IFC_DO_RESET; 6823 STATE_UNLOCK(ctx); 6824 } 6825 6826 #ifndef __NO_STRICT_ALIGNMENT 6827 static struct mbuf * 6828 iflib_fixup_rx(struct mbuf *m) 6829 { 6830 struct mbuf *n; 6831 6832 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6833 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6834 m->m_data += ETHER_HDR_LEN; 6835 n = m; 6836 } else { 6837 MGETHDR(n, M_NOWAIT, MT_DATA); 6838 if (n == NULL) { 6839 m_freem(m); 6840 return (NULL); 6841 } 6842 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6843 m->m_data += ETHER_HDR_LEN; 6844 m->m_len -= ETHER_HDR_LEN; 6845 n->m_len = ETHER_HDR_LEN; 6846 M_MOVE_PKTHDR(n, m); 6847 n->m_next = m; 6848 } 6849 return (n); 6850 } 6851 #endif 6852 6853 #ifdef DEBUGNET 6854 static void 6855 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6856 { 6857 if_ctx_t ctx; 6858 6859 ctx = if_getsoftc(ifp); 6860 CTX_LOCK(ctx); 6861 *nrxr = NRXQSETS(ctx); 6862 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6863 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6864 CTX_UNLOCK(ctx); 6865 } 6866 6867 static void 6868 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 6869 { 6870 if_ctx_t ctx; 6871 if_softc_ctx_t scctx; 6872 iflib_fl_t fl; 6873 iflib_rxq_t rxq; 6874 int i, j; 6875 6876 ctx = if_getsoftc(ifp); 6877 scctx = &ctx->ifc_softc_ctx; 6878 6879 switch (event) { 6880 case DEBUGNET_START: 6881 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6882 rxq = &ctx->ifc_rxqs[i]; 6883 for (j = 0; j < rxq->ifr_nfl; j++) { 6884 fl = rxq->ifr_fl; 6885 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6886 } 6887 } 6888 iflib_no_tx_batch = 1; 6889 break; 6890 default: 6891 break; 6892 } 6893 } 6894 6895 static int 6896 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 6897 { 6898 if_ctx_t ctx; 6899 iflib_txq_t txq; 6900 int error; 6901 6902 ctx = if_getsoftc(ifp); 6903 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6904 IFF_DRV_RUNNING) 6905 return (EBUSY); 6906 6907 txq = &ctx->ifc_txqs[0]; 6908 error = iflib_encap(txq, &m); 6909 if (error == 0) 6910 (void)iflib_txd_db_check(txq, true); 6911 return (error); 6912 } 6913 6914 static int 6915 iflib_debugnet_poll(if_t ifp, int count) 6916 { 6917 struct epoch_tracker et; 6918 if_ctx_t ctx; 6919 if_softc_ctx_t scctx; 6920 iflib_txq_t txq; 6921 int i; 6922 6923 ctx = if_getsoftc(ifp); 6924 scctx = &ctx->ifc_softc_ctx; 6925 6926 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6927 IFF_DRV_RUNNING) 6928 return (EBUSY); 6929 6930 txq = &ctx->ifc_txqs[0]; 6931 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6932 6933 NET_EPOCH_ENTER(et); 6934 for (i = 0; i < scctx->isc_nrxqsets; i++) 6935 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6936 NET_EPOCH_EXIT(et); 6937 return (0); 6938 } 6939 #endif /* DEBUGNET */ 6940