1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/jail.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/md5.h> 44 #include <sys/mutex.h> 45 #include <sys/module.h> 46 #include <sys/kobj.h> 47 #include <sys/rman.h> 48 #include <sys/proc.h> 49 #include <sys/sbuf.h> 50 #include <sys/smp.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/syslog.h> 55 #include <sys/taskqueue.h> 56 #include <sys/limits.h> 57 58 #include <net/if.h> 59 #include <net/if_var.h> 60 #include <net/if_types.h> 61 #include <net/if_media.h> 62 #include <net/bpf.h> 63 #include <net/ethernet.h> 64 #include <net/mp_ring.h> 65 #include <net/vnet.h> 66 67 #include <netinet/in.h> 68 #include <netinet/in_pcb.h> 69 #include <netinet/tcp_lro.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/if_ether.h> 72 #include <netinet/ip.h> 73 #include <netinet/ip6.h> 74 #include <netinet/tcp.h> 75 #include <netinet/ip_var.h> 76 #include <netinet/netdump/netdump.h> 77 #include <netinet6/ip6_var.h> 78 79 #include <machine/bus.h> 80 #include <machine/in_cksum.h> 81 82 #include <vm/vm.h> 83 #include <vm/pmap.h> 84 85 #include <dev/led/led.h> 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pci_private.h> 89 90 #include <net/iflib.h> 91 #include <net/iflib_private.h> 92 93 #include "ifdi_if.h" 94 95 #ifdef PCI_IOV 96 #include <dev/pci/pci_iov.h> 97 #endif 98 99 #include <sys/bitstring.h> 100 /* 101 * enable accounting of every mbuf as it comes in to and goes out of 102 * iflib's software descriptor references 103 */ 104 #define MEMORY_LOGGING 0 105 /* 106 * Enable mbuf vectors for compressing long mbuf chains 107 */ 108 109 /* 110 * NB: 111 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 112 * we prefetch needs to be determined by the time spent in m_free vis a vis 113 * the cost of a prefetch. This will of course vary based on the workload: 114 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 115 * is quite expensive, thus suggesting very little prefetch. 116 * - small packet forwarding which is just returning a single mbuf to 117 * UMA will typically be very fast vis a vis the cost of a memory 118 * access. 119 */ 120 121 122 /* 123 * File organization: 124 * - private structures 125 * - iflib private utility functions 126 * - ifnet functions 127 * - vlan registry and other exported functions 128 * - iflib public core functions 129 * 130 * 131 */ 132 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 146 typedef struct iflib_filter_info { 147 driver_filter_t *ifi_filter; 148 void *ifi_filter_arg; 149 struct grouptask *ifi_task; 150 void *ifi_ctx; 151 } *iflib_filter_info_t; 152 153 struct iflib_ctx { 154 KOBJ_FIELDS; 155 /* 156 * Pointer to hardware driver's softc 157 */ 158 void *ifc_softc; 159 device_t ifc_dev; 160 if_t ifc_ifp; 161 162 cpuset_t ifc_cpus; 163 if_shared_ctx_t ifc_sctx; 164 struct if_softc_ctx ifc_softc_ctx; 165 166 struct sx ifc_ctx_sx; 167 struct mtx ifc_state_mtx; 168 169 iflib_txq_t ifc_txqs; 170 iflib_rxq_t ifc_rxqs; 171 uint32_t ifc_if_flags; 172 uint32_t ifc_flags; 173 uint32_t ifc_max_fl_buf_size; 174 175 int ifc_link_state; 176 int ifc_link_irq; 177 int ifc_watchdog_events; 178 struct cdev *ifc_led_dev; 179 struct resource *ifc_msix_mem; 180 181 struct if_irq ifc_legacy_irq; 182 struct grouptask ifc_admin_task; 183 struct grouptask ifc_vflr_task; 184 struct iflib_filter_info ifc_filter_info; 185 struct ifmedia ifc_media; 186 187 struct sysctl_oid *ifc_sysctl_node; 188 uint16_t ifc_sysctl_ntxqs; 189 uint16_t ifc_sysctl_nrxqs; 190 uint16_t ifc_sysctl_qs_eq_override; 191 uint16_t ifc_sysctl_rx_budget; 192 uint16_t ifc_sysctl_tx_abdicate; 193 194 qidx_t ifc_sysctl_ntxds[8]; 195 qidx_t ifc_sysctl_nrxds[8]; 196 struct if_txrx ifc_txrx; 197 #define isc_txd_encap ifc_txrx.ift_txd_encap 198 #define isc_txd_flush ifc_txrx.ift_txd_flush 199 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 200 #define isc_rxd_available ifc_txrx.ift_rxd_available 201 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 202 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 203 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 205 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 206 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 207 eventhandler_tag ifc_vlan_attach_event; 208 eventhandler_tag ifc_vlan_detach_event; 209 uint8_t ifc_mac[ETHER_ADDR_LEN]; 210 char ifc_mtx_name[16]; 211 }; 212 213 214 void * 215 iflib_get_softc(if_ctx_t ctx) 216 { 217 218 return (ctx->ifc_softc); 219 } 220 221 device_t 222 iflib_get_dev(if_ctx_t ctx) 223 { 224 225 return (ctx->ifc_dev); 226 } 227 228 if_t 229 iflib_get_ifp(if_ctx_t ctx) 230 { 231 232 return (ctx->ifc_ifp); 233 } 234 235 struct ifmedia * 236 iflib_get_media(if_ctx_t ctx) 237 { 238 239 return (&ctx->ifc_media); 240 } 241 242 uint32_t 243 iflib_get_flags(if_ctx_t ctx) 244 { 245 return (ctx->ifc_flags); 246 } 247 248 void 249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 250 { 251 252 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 253 } 254 255 if_softc_ctx_t 256 iflib_get_softc_ctx(if_ctx_t ctx) 257 { 258 259 return (&ctx->ifc_softc_ctx); 260 } 261 262 if_shared_ctx_t 263 iflib_get_sctx(if_ctx_t ctx) 264 { 265 266 return (ctx->ifc_sctx); 267 } 268 269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 272 273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 275 276 typedef struct iflib_sw_rx_desc_array { 277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 278 struct mbuf **ifsd_m; /* pkthdr mbufs */ 279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 281 } iflib_rxsd_array_t; 282 283 typedef struct iflib_sw_tx_desc_array { 284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 286 struct mbuf **ifsd_m; /* pkthdr mbufs */ 287 } if_txsd_vec_t; 288 289 290 /* magic number that should be high enough for any hardware */ 291 #define IFLIB_MAX_TX_SEGS 128 292 /* bnxt supports 64 with hardware LRO enabled */ 293 #define IFLIB_MAX_RX_SEGS 64 294 #define IFLIB_RX_COPY_THRESH 128 295 #define IFLIB_MAX_RX_REFRESH 32 296 /* The minimum descriptors per second before we start coalescing */ 297 #define IFLIB_MIN_DESC_SEC 16384 298 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 299 #define IFLIB_QUEUE_IDLE 0 300 #define IFLIB_QUEUE_HUNG 1 301 #define IFLIB_QUEUE_WORKING 2 302 /* maximum number of txqs that can share an rx interrupt */ 303 #define IFLIB_MAX_TX_SHARED_INTR 4 304 305 /* this should really scale with ring size - this is a fairly arbitrary value */ 306 #define TX_BATCH_SIZE 32 307 308 #define IFLIB_RESTART_BUDGET 8 309 310 311 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 312 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 313 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 314 struct iflib_txq { 315 qidx_t ift_in_use; 316 qidx_t ift_cidx; 317 qidx_t ift_cidx_processed; 318 qidx_t ift_pidx; 319 uint8_t ift_gen; 320 uint8_t ift_br_offset; 321 uint16_t ift_npending; 322 uint16_t ift_db_pending; 323 uint16_t ift_rs_pending; 324 /* implicit pad */ 325 uint8_t ift_txd_size[8]; 326 uint64_t ift_processed; 327 uint64_t ift_cleaned; 328 uint64_t ift_cleaned_prev; 329 #if MEMORY_LOGGING 330 uint64_t ift_enqueued; 331 uint64_t ift_dequeued; 332 #endif 333 uint64_t ift_no_tx_dma_setup; 334 uint64_t ift_no_desc_avail; 335 uint64_t ift_mbuf_defrag_failed; 336 uint64_t ift_mbuf_defrag; 337 uint64_t ift_map_failed; 338 uint64_t ift_txd_encap_efbig; 339 uint64_t ift_pullups; 340 uint64_t ift_last_timer_tick; 341 342 struct mtx ift_mtx; 343 struct mtx ift_db_mtx; 344 345 /* constant values */ 346 if_ctx_t ift_ctx; 347 struct ifmp_ring *ift_br; 348 struct grouptask ift_task; 349 qidx_t ift_size; 350 uint16_t ift_id; 351 struct callout ift_timer; 352 353 if_txsd_vec_t ift_sds; 354 uint8_t ift_qstatus; 355 uint8_t ift_closed; 356 uint8_t ift_update_freq; 357 struct iflib_filter_info ift_filter_info; 358 bus_dma_tag_t ift_desc_tag; 359 bus_dma_tag_t ift_tso_desc_tag; 360 iflib_dma_info_t ift_ifdi; 361 #define MTX_NAME_LEN 16 362 char ift_mtx_name[MTX_NAME_LEN]; 363 char ift_db_mtx_name[MTX_NAME_LEN]; 364 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 365 #ifdef IFLIB_DIAGNOSTICS 366 uint64_t ift_cpu_exec_count[256]; 367 #endif 368 } __aligned(CACHE_LINE_SIZE); 369 370 struct iflib_fl { 371 qidx_t ifl_cidx; 372 qidx_t ifl_pidx; 373 qidx_t ifl_credits; 374 uint8_t ifl_gen; 375 uint8_t ifl_rxd_size; 376 #if MEMORY_LOGGING 377 uint64_t ifl_m_enqueued; 378 uint64_t ifl_m_dequeued; 379 uint64_t ifl_cl_enqueued; 380 uint64_t ifl_cl_dequeued; 381 #endif 382 /* implicit pad */ 383 384 bitstr_t *ifl_rx_bitmap; 385 qidx_t ifl_fragidx; 386 /* constant */ 387 qidx_t ifl_size; 388 uint16_t ifl_buf_size; 389 uint16_t ifl_cltype; 390 uma_zone_t ifl_zone; 391 iflib_rxsd_array_t ifl_sds; 392 iflib_rxq_t ifl_rxq; 393 uint8_t ifl_id; 394 bus_dma_tag_t ifl_desc_tag; 395 iflib_dma_info_t ifl_ifdi; 396 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 397 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 398 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 399 } __aligned(CACHE_LINE_SIZE); 400 401 static inline qidx_t 402 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 403 { 404 qidx_t used; 405 406 if (pidx > cidx) 407 used = pidx - cidx; 408 else if (pidx < cidx) 409 used = size - cidx + pidx; 410 else if (gen == 0 && pidx == cidx) 411 used = 0; 412 else if (gen == 1 && pidx == cidx) 413 used = size; 414 else 415 panic("bad state"); 416 417 return (used); 418 } 419 420 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 421 422 #define IDXDIFF(head, tail, wrap) \ 423 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 424 425 struct iflib_rxq { 426 /* If there is a separate completion queue - 427 * these are the cq cidx and pidx. Otherwise 428 * these are unused. 429 */ 430 qidx_t ifr_size; 431 qidx_t ifr_cq_cidx; 432 qidx_t ifr_cq_pidx; 433 uint8_t ifr_cq_gen; 434 uint8_t ifr_fl_offset; 435 436 if_ctx_t ifr_ctx; 437 iflib_fl_t ifr_fl; 438 uint64_t ifr_rx_irq; 439 uint16_t ifr_id; 440 uint8_t ifr_lro_enabled; 441 uint8_t ifr_nfl; 442 uint8_t ifr_ntxqirq; 443 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 444 struct lro_ctrl ifr_lc; 445 struct grouptask ifr_task; 446 struct iflib_filter_info ifr_filter_info; 447 iflib_dma_info_t ifr_ifdi; 448 449 /* dynamically allocate if any drivers need a value substantially larger than this */ 450 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 451 #ifdef IFLIB_DIAGNOSTICS 452 uint64_t ifr_cpu_exec_count[256]; 453 #endif 454 } __aligned(CACHE_LINE_SIZE); 455 456 typedef struct if_rxsd { 457 caddr_t *ifsd_cl; 458 struct mbuf **ifsd_m; 459 iflib_fl_t ifsd_fl; 460 qidx_t ifsd_cidx; 461 } *if_rxsd_t; 462 463 /* multiple of word size */ 464 #ifdef __LP64__ 465 #define PKT_INFO_SIZE 6 466 #define RXD_INFO_SIZE 5 467 #define PKT_TYPE uint64_t 468 #else 469 #define PKT_INFO_SIZE 11 470 #define RXD_INFO_SIZE 8 471 #define PKT_TYPE uint32_t 472 #endif 473 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 474 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 475 476 typedef struct if_pkt_info_pad { 477 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 478 } *if_pkt_info_pad_t; 479 typedef struct if_rxd_info_pad { 480 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 481 } *if_rxd_info_pad_t; 482 483 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 484 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 485 486 487 static inline void 488 pkt_info_zero(if_pkt_info_t pi) 489 { 490 if_pkt_info_pad_t pi_pad; 491 492 pi_pad = (if_pkt_info_pad_t)pi; 493 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 494 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 495 #ifndef __LP64__ 496 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 497 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 498 #endif 499 } 500 501 static device_method_t iflib_pseudo_methods[] = { 502 DEVMETHOD(device_attach, noop_attach), 503 DEVMETHOD(device_detach, iflib_pseudo_detach), 504 DEVMETHOD_END 505 }; 506 507 driver_t iflib_pseudodriver = { 508 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 509 }; 510 511 static inline void 512 rxd_info_zero(if_rxd_info_t ri) 513 { 514 if_rxd_info_pad_t ri_pad; 515 int i; 516 517 ri_pad = (if_rxd_info_pad_t)ri; 518 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 519 ri_pad->rxd_val[i] = 0; 520 ri_pad->rxd_val[i+1] = 0; 521 ri_pad->rxd_val[i+2] = 0; 522 ri_pad->rxd_val[i+3] = 0; 523 } 524 #ifdef __LP64__ 525 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 526 #endif 527 } 528 529 /* 530 * Only allow a single packet to take up most 1/nth of the tx ring 531 */ 532 #define MAX_SINGLE_PACKET_FRACTION 12 533 #define IF_BAD_DMA (bus_addr_t)-1 534 535 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 536 537 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 538 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 539 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 540 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 541 542 543 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 544 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 545 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 546 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 547 548 549 550 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 551 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 552 553 void 554 iflib_set_detach(if_ctx_t ctx) 555 { 556 STATE_LOCK(ctx); 557 ctx->ifc_flags |= IFC_IN_DETACH; 558 STATE_UNLOCK(ctx); 559 } 560 561 /* Our boot-time initialization hook */ 562 static int iflib_module_event_handler(module_t, int, void *); 563 564 static moduledata_t iflib_moduledata = { 565 "iflib", 566 iflib_module_event_handler, 567 NULL 568 }; 569 570 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 571 MODULE_VERSION(iflib, 1); 572 573 MODULE_DEPEND(iflib, pci, 1, 1, 1); 574 MODULE_DEPEND(iflib, ether, 1, 1, 1); 575 576 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 577 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 578 579 #ifndef IFLIB_DEBUG_COUNTERS 580 #ifdef INVARIANTS 581 #define IFLIB_DEBUG_COUNTERS 1 582 #else 583 #define IFLIB_DEBUG_COUNTERS 0 584 #endif /* !INVARIANTS */ 585 #endif 586 587 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 588 "iflib driver parameters"); 589 590 /* 591 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 592 */ 593 static int iflib_min_tx_latency = 0; 594 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 595 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 596 static int iflib_no_tx_batch = 0; 597 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 598 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 599 600 601 #if IFLIB_DEBUG_COUNTERS 602 603 static int iflib_tx_seen; 604 static int iflib_tx_sent; 605 static int iflib_tx_encap; 606 static int iflib_rx_allocs; 607 static int iflib_fl_refills; 608 static int iflib_fl_refills_large; 609 static int iflib_tx_frees; 610 611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 612 &iflib_tx_seen, 0, "# tx mbufs seen"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 614 &iflib_tx_sent, 0, "# tx mbufs sent"); 615 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 616 &iflib_tx_encap, 0, "# tx mbufs encapped"); 617 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 618 &iflib_tx_frees, 0, "# tx frees"); 619 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 620 &iflib_rx_allocs, 0, "# rx allocations"); 621 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 622 &iflib_fl_refills, 0, "# refills"); 623 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 624 &iflib_fl_refills_large, 0, "# large refills"); 625 626 627 static int iflib_txq_drain_flushing; 628 static int iflib_txq_drain_oactive; 629 static int iflib_txq_drain_notready; 630 631 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 632 &iflib_txq_drain_flushing, 0, "# drain flushes"); 633 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 634 &iflib_txq_drain_oactive, 0, "# drain oactives"); 635 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 636 &iflib_txq_drain_notready, 0, "# drain notready"); 637 638 639 static int iflib_encap_load_mbuf_fail; 640 static int iflib_encap_pad_mbuf_fail; 641 static int iflib_encap_txq_avail_fail; 642 static int iflib_encap_txd_encap_fail; 643 644 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 645 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 646 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 647 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 648 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 649 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 650 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 651 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 652 653 static int iflib_task_fn_rxs; 654 static int iflib_rx_intr_enables; 655 static int iflib_fast_intrs; 656 static int iflib_rx_unavail; 657 static int iflib_rx_ctx_inactive; 658 static int iflib_rx_if_input; 659 static int iflib_rx_mbuf_null; 660 static int iflib_rxd_flush; 661 662 static int iflib_verbose_debug; 663 664 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 665 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 666 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 667 &iflib_rx_intr_enables, 0, "# rx intr enables"); 668 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 669 &iflib_fast_intrs, 0, "# fast_intr calls"); 670 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 671 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 672 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 673 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 674 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 675 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 676 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 677 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 678 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 679 &iflib_rxd_flush, 0, "# times rxd_flush called"); 680 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 681 &iflib_verbose_debug, 0, "enable verbose debugging"); 682 683 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 684 static void 685 iflib_debug_reset(void) 686 { 687 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 688 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 689 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 690 iflib_txq_drain_notready = 691 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 692 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 693 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 694 iflib_rx_unavail = 695 iflib_rx_ctx_inactive = iflib_rx_if_input = 696 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 697 } 698 699 #else 700 #define DBG_COUNTER_INC(name) 701 static void iflib_debug_reset(void) {} 702 #endif 703 704 #define IFLIB_DEBUG 0 705 706 static void iflib_tx_structures_free(if_ctx_t ctx); 707 static void iflib_rx_structures_free(if_ctx_t ctx); 708 static int iflib_queues_alloc(if_ctx_t ctx); 709 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 710 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 711 static int iflib_qset_structures_setup(if_ctx_t ctx); 712 static int iflib_msix_init(if_ctx_t ctx); 713 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 714 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 715 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 716 #ifdef ALTQ 717 static void iflib_altq_if_start(if_t ifp); 718 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 719 #endif 720 static int iflib_register(if_ctx_t); 721 static void iflib_init_locked(if_ctx_t ctx); 722 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 723 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 724 static void iflib_ifmp_purge(iflib_txq_t txq); 725 static void _iflib_pre_assert(if_softc_ctx_t scctx); 726 static void iflib_if_init_locked(if_ctx_t ctx); 727 static void iflib_free_intr_mem(if_ctx_t ctx); 728 #ifndef __NO_STRICT_ALIGNMENT 729 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 730 #endif 731 732 NETDUMP_DEFINE(iflib); 733 734 #ifdef DEV_NETMAP 735 #include <sys/selinfo.h> 736 #include <net/netmap.h> 737 #include <dev/netmap/netmap_kern.h> 738 739 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 740 741 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 742 743 /* 744 * device-specific sysctl variables: 745 * 746 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 747 * During regular operations the CRC is stripped, but on some 748 * hardware reception of frames not multiple of 64 is slower, 749 * so using crcstrip=0 helps in benchmarks. 750 * 751 * iflib_rx_miss, iflib_rx_miss_bufs: 752 * count packets that might be missed due to lost interrupts. 753 */ 754 SYSCTL_DECL(_dev_netmap); 755 /* 756 * The xl driver by default strips CRCs and we do not override it. 757 */ 758 759 int iflib_crcstrip = 1; 760 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 761 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 762 763 int iflib_rx_miss, iflib_rx_miss_bufs; 764 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 765 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 766 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 767 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 768 769 /* 770 * Register/unregister. We are already under netmap lock. 771 * Only called on the first register or the last unregister. 772 */ 773 static int 774 iflib_netmap_register(struct netmap_adapter *na, int onoff) 775 { 776 struct ifnet *ifp = na->ifp; 777 if_ctx_t ctx = ifp->if_softc; 778 int status; 779 780 CTX_LOCK(ctx); 781 IFDI_INTR_DISABLE(ctx); 782 783 /* Tell the stack that the interface is no longer active */ 784 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 785 786 if (!CTX_IS_VF(ctx)) 787 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 788 789 /* enable or disable flags and callbacks in na and ifp */ 790 if (onoff) { 791 nm_set_native_flags(na); 792 } else { 793 nm_clear_native_flags(na); 794 } 795 iflib_stop(ctx); 796 iflib_init_locked(ctx); 797 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 798 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 799 if (status) 800 nm_clear_native_flags(na); 801 CTX_UNLOCK(ctx); 802 return (status); 803 } 804 805 static int 806 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 807 { 808 struct netmap_adapter *na = kring->na; 809 u_int const lim = kring->nkr_num_slots - 1; 810 u_int head = kring->rhead; 811 struct netmap_ring *ring = kring->ring; 812 bus_dmamap_t *map; 813 struct if_rxd_update iru; 814 if_ctx_t ctx = rxq->ifr_ctx; 815 iflib_fl_t fl = &rxq->ifr_fl[0]; 816 uint32_t refill_pidx, nic_i; 817 #if IFLIB_DEBUG_COUNTERS 818 int rf_count = 0; 819 #endif 820 821 if (nm_i == head && __predict_true(!init)) 822 return 0; 823 iru_init(&iru, rxq, 0 /* flid */); 824 map = fl->ifl_sds.ifsd_map; 825 refill_pidx = netmap_idx_k2n(kring, nm_i); 826 /* 827 * IMPORTANT: we must leave one free slot in the ring, 828 * so move head back by one unit 829 */ 830 head = nm_prev(head, lim); 831 nic_i = UINT_MAX; 832 DBG_COUNTER_INC(fl_refills); 833 while (nm_i != head) { 834 #if IFLIB_DEBUG_COUNTERS 835 if (++rf_count == 9) 836 DBG_COUNTER_INC(fl_refills_large); 837 #endif 838 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 839 struct netmap_slot *slot = &ring->slot[nm_i]; 840 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 841 uint32_t nic_i_dma = refill_pidx; 842 nic_i = netmap_idx_k2n(kring, nm_i); 843 844 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 845 846 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 847 return netmap_ring_reinit(kring); 848 849 fl->ifl_vm_addrs[tmp_pidx] = addr; 850 if (__predict_false(init) && map) { 851 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 852 } else if (map && (slot->flags & NS_BUF_CHANGED)) { 853 /* buffer has changed, reload map */ 854 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 855 } 856 slot->flags &= ~NS_BUF_CHANGED; 857 858 nm_i = nm_next(nm_i, lim); 859 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 860 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 861 continue; 862 863 iru.iru_pidx = refill_pidx; 864 iru.iru_count = tmp_pidx+1; 865 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 866 867 refill_pidx = nic_i; 868 if (map == NULL) 869 continue; 870 871 for (int n = 0; n < iru.iru_count; n++) { 872 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma], 873 BUS_DMASYNC_PREREAD); 874 /* XXX - change this to not use the netmap func*/ 875 nic_i_dma = nm_next(nic_i_dma, lim); 876 } 877 } 878 } 879 kring->nr_hwcur = head; 880 881 if (map) 882 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 883 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 884 if (__predict_true(nic_i != UINT_MAX)) { 885 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 886 DBG_COUNTER_INC(rxd_flush); 887 } 888 return (0); 889 } 890 891 /* 892 * Reconcile kernel and user view of the transmit ring. 893 * 894 * All information is in the kring. 895 * Userspace wants to send packets up to the one before kring->rhead, 896 * kernel knows kring->nr_hwcur is the first unsent packet. 897 * 898 * Here we push packets out (as many as possible), and possibly 899 * reclaim buffers from previously completed transmission. 900 * 901 * The caller (netmap) guarantees that there is only one instance 902 * running at any time. Any interference with other driver 903 * methods should be handled by the individual drivers. 904 */ 905 static int 906 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 907 { 908 struct netmap_adapter *na = kring->na; 909 struct ifnet *ifp = na->ifp; 910 struct netmap_ring *ring = kring->ring; 911 u_int nm_i; /* index into the netmap kring */ 912 u_int nic_i; /* index into the NIC ring */ 913 u_int n; 914 u_int const lim = kring->nkr_num_slots - 1; 915 u_int const head = kring->rhead; 916 struct if_pkt_info pi; 917 918 /* 919 * interrupts on every tx packet are expensive so request 920 * them every half ring, or where NS_REPORT is set 921 */ 922 u_int report_frequency = kring->nkr_num_slots >> 1; 923 /* device-specific */ 924 if_ctx_t ctx = ifp->if_softc; 925 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 926 927 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 928 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 929 930 931 /* 932 * First part: process new packets to send. 933 * nm_i is the current index in the netmap kring, 934 * nic_i is the corresponding index in the NIC ring. 935 * 936 * If we have packets to send (nm_i != head) 937 * iterate over the netmap ring, fetch length and update 938 * the corresponding slot in the NIC ring. Some drivers also 939 * need to update the buffer's physical address in the NIC slot 940 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 941 * 942 * The netmap_reload_map() calls is especially expensive, 943 * even when (as in this case) the tag is 0, so do only 944 * when the buffer has actually changed. 945 * 946 * If possible do not set the report/intr bit on all slots, 947 * but only a few times per ring or when NS_REPORT is set. 948 * 949 * Finally, on 10G and faster drivers, it might be useful 950 * to prefetch the next slot and txr entry. 951 */ 952 953 nm_i = kring->nr_hwcur; 954 if (nm_i != head) { /* we have new packets to send */ 955 pkt_info_zero(&pi); 956 pi.ipi_segs = txq->ift_segs; 957 pi.ipi_qsidx = kring->ring_id; 958 nic_i = netmap_idx_k2n(kring, nm_i); 959 960 __builtin_prefetch(&ring->slot[nm_i]); 961 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 962 if (txq->ift_sds.ifsd_map) 963 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 964 965 for (n = 0; nm_i != head; n++) { 966 struct netmap_slot *slot = &ring->slot[nm_i]; 967 u_int len = slot->len; 968 uint64_t paddr; 969 void *addr = PNMB(na, slot, &paddr); 970 int flags = (slot->flags & NS_REPORT || 971 nic_i == 0 || nic_i == report_frequency) ? 972 IPI_TX_INTR : 0; 973 974 /* device-specific */ 975 pi.ipi_len = len; 976 pi.ipi_segs[0].ds_addr = paddr; 977 pi.ipi_segs[0].ds_len = len; 978 pi.ipi_nsegs = 1; 979 pi.ipi_ndescs = 0; 980 pi.ipi_pidx = nic_i; 981 pi.ipi_flags = flags; 982 983 /* Fill the slot in the NIC ring. */ 984 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 985 DBG_COUNTER_INC(tx_encap); 986 987 /* prefetch for next round */ 988 __builtin_prefetch(&ring->slot[nm_i + 1]); 989 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 990 if (txq->ift_sds.ifsd_map) { 991 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 992 993 NM_CHECK_ADDR_LEN(na, addr, len); 994 995 if (slot->flags & NS_BUF_CHANGED) { 996 /* buffer has changed, reload map */ 997 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 998 } 999 /* make sure changes to the buffer are synced */ 1000 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 1001 BUS_DMASYNC_PREWRITE); 1002 } 1003 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1004 nm_i = nm_next(nm_i, lim); 1005 nic_i = nm_next(nic_i, lim); 1006 } 1007 kring->nr_hwcur = nm_i; 1008 1009 /* synchronize the NIC ring */ 1010 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 1011 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1012 1013 /* (re)start the tx unit up to slot nic_i (excluded) */ 1014 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1015 } 1016 1017 /* 1018 * Second part: reclaim buffers for completed transmissions. 1019 * 1020 * If there are unclaimed buffers, attempt to reclaim them. 1021 * If none are reclaimed, and TX IRQs are not in use, do an initial 1022 * minimal delay, then trigger the tx handler which will spin in the 1023 * group task queue. 1024 */ 1025 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1026 if (iflib_tx_credits_update(ctx, txq)) { 1027 /* some tx completed, increment avail */ 1028 nic_i = txq->ift_cidx_processed; 1029 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1030 } 1031 } 1032 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1033 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1034 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1035 iflib_timer, txq, txq->ift_timer.c_cpu); 1036 } 1037 return (0); 1038 } 1039 1040 /* 1041 * Reconcile kernel and user view of the receive ring. 1042 * Same as for the txsync, this routine must be efficient. 1043 * The caller guarantees a single invocations, but races against 1044 * the rest of the driver should be handled here. 1045 * 1046 * On call, kring->rhead is the first packet that userspace wants 1047 * to keep, and kring->rcur is the wakeup point. 1048 * The kernel has previously reported packets up to kring->rtail. 1049 * 1050 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1051 * of whether or not we received an interrupt. 1052 */ 1053 static int 1054 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1055 { 1056 struct netmap_adapter *na = kring->na; 1057 struct netmap_ring *ring = kring->ring; 1058 uint32_t nm_i; /* index into the netmap ring */ 1059 uint32_t nic_i; /* index into the NIC ring */ 1060 u_int i, n; 1061 u_int const lim = kring->nkr_num_slots - 1; 1062 u_int const head = kring->rhead; 1063 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1064 struct if_rxd_info ri; 1065 1066 struct ifnet *ifp = na->ifp; 1067 if_ctx_t ctx = ifp->if_softc; 1068 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1069 iflib_fl_t fl = rxq->ifr_fl; 1070 if (head > lim) 1071 return netmap_ring_reinit(kring); 1072 1073 /* XXX check sync modes */ 1074 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1075 if (fl->ifl_sds.ifsd_map == NULL) 1076 continue; 1077 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 1078 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1079 } 1080 /* 1081 * First part: import newly received packets. 1082 * 1083 * nm_i is the index of the next free slot in the netmap ring, 1084 * nic_i is the index of the next received packet in the NIC ring, 1085 * and they may differ in case if_init() has been called while 1086 * in netmap mode. For the receive ring we have 1087 * 1088 * nic_i = rxr->next_check; 1089 * nm_i = kring->nr_hwtail (previous) 1090 * and 1091 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1092 * 1093 * rxr->next_check is set to 0 on a ring reinit 1094 */ 1095 if (netmap_no_pendintr || force_update) { 1096 int crclen = iflib_crcstrip ? 0 : 4; 1097 int error, avail; 1098 1099 for (i = 0; i < rxq->ifr_nfl; i++) { 1100 fl = &rxq->ifr_fl[i]; 1101 nic_i = fl->ifl_cidx; 1102 nm_i = netmap_idx_n2k(kring, nic_i); 1103 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 1104 for (n = 0; avail > 0; n++, avail--) { 1105 rxd_info_zero(&ri); 1106 ri.iri_frags = rxq->ifr_frags; 1107 ri.iri_qsidx = kring->ring_id; 1108 ri.iri_ifp = ctx->ifc_ifp; 1109 ri.iri_cidx = nic_i; 1110 1111 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1112 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1113 ring->slot[nm_i].flags = 0; 1114 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1115 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1116 nm_i = nm_next(nm_i, lim); 1117 nic_i = nm_next(nic_i, lim); 1118 } 1119 if (n) { /* update the state variables */ 1120 if (netmap_no_pendintr && !force_update) { 1121 /* diagnostics */ 1122 iflib_rx_miss ++; 1123 iflib_rx_miss_bufs += n; 1124 } 1125 fl->ifl_cidx = nic_i; 1126 kring->nr_hwtail = nm_i; 1127 } 1128 kring->nr_kflags &= ~NKR_PENDINTR; 1129 } 1130 } 1131 /* 1132 * Second part: skip past packets that userspace has released. 1133 * (kring->nr_hwcur to head excluded), 1134 * and make the buffers available for reception. 1135 * As usual nm_i is the index in the netmap ring, 1136 * nic_i is the index in the NIC ring, and 1137 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1138 */ 1139 /* XXX not sure how this will work with multiple free lists */ 1140 nm_i = kring->nr_hwcur; 1141 1142 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1143 } 1144 1145 static void 1146 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1147 { 1148 struct ifnet *ifp = na->ifp; 1149 if_ctx_t ctx = ifp->if_softc; 1150 1151 CTX_LOCK(ctx); 1152 if (onoff) { 1153 IFDI_INTR_ENABLE(ctx); 1154 } else { 1155 IFDI_INTR_DISABLE(ctx); 1156 } 1157 CTX_UNLOCK(ctx); 1158 } 1159 1160 1161 static int 1162 iflib_netmap_attach(if_ctx_t ctx) 1163 { 1164 struct netmap_adapter na; 1165 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1166 1167 bzero(&na, sizeof(na)); 1168 1169 na.ifp = ctx->ifc_ifp; 1170 na.na_flags = NAF_BDG_MAYSLEEP; 1171 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1172 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1173 1174 na.num_tx_desc = scctx->isc_ntxd[0]; 1175 na.num_rx_desc = scctx->isc_nrxd[0]; 1176 na.nm_txsync = iflib_netmap_txsync; 1177 na.nm_rxsync = iflib_netmap_rxsync; 1178 na.nm_register = iflib_netmap_register; 1179 na.nm_intr = iflib_netmap_intr; 1180 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1181 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1182 return (netmap_attach(&na)); 1183 } 1184 1185 static void 1186 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1187 { 1188 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1189 struct netmap_slot *slot; 1190 1191 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1192 if (slot == NULL) 1193 return; 1194 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1195 1196 /* 1197 * In netmap mode, set the map for the packet buffer. 1198 * NOTE: Some drivers (not this one) also need to set 1199 * the physical buffer address in the NIC ring. 1200 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1201 * netmap slot index, si 1202 */ 1203 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1204 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1205 } 1206 } 1207 1208 static void 1209 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1210 { 1211 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1212 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1213 struct netmap_slot *slot; 1214 uint32_t nm_i; 1215 1216 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1217 if (slot == NULL) 1218 return; 1219 nm_i = netmap_idx_n2k(kring, 0); 1220 netmap_fl_refill(rxq, kring, nm_i, true); 1221 } 1222 1223 static void 1224 iflib_netmap_timer_adjust(if_ctx_t ctx, uint16_t txqid, uint32_t *reset_on) 1225 { 1226 struct netmap_kring *kring; 1227 1228 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1229 1230 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1231 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1232 netmap_tx_irq(ctx->ifc_ifp, txqid); 1233 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1234 if (hz < 2000) 1235 *reset_on = 1; 1236 else 1237 *reset_on = hz / 1000; 1238 } 1239 } 1240 } 1241 1242 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1243 1244 #else 1245 #define iflib_netmap_txq_init(ctx, txq) 1246 #define iflib_netmap_rxq_init(ctx, rxq) 1247 #define iflib_netmap_detach(ifp) 1248 1249 #define iflib_netmap_attach(ctx) (0) 1250 #define netmap_rx_irq(ifp, qid, budget) (0) 1251 #define netmap_tx_irq(ifp, qid) do {} while (0) 1252 #define iflib_netmap_timer_adjust(ctx, txqid, reset_on) 1253 1254 #endif 1255 1256 #if defined(__i386__) || defined(__amd64__) 1257 static __inline void 1258 prefetch(void *x) 1259 { 1260 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1261 } 1262 static __inline void 1263 prefetch2cachelines(void *x) 1264 { 1265 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1266 #if (CACHE_LINE_SIZE < 128) 1267 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1268 #endif 1269 } 1270 #else 1271 #define prefetch(x) 1272 #define prefetch2cachelines(x) 1273 #endif 1274 1275 static void 1276 iflib_gen_mac(if_ctx_t ctx) 1277 { 1278 struct thread *td; 1279 MD5_CTX mdctx; 1280 char uuid[HOSTUUIDLEN+1]; 1281 char buf[HOSTUUIDLEN+16]; 1282 uint8_t *mac; 1283 unsigned char digest[16]; 1284 1285 td = curthread; 1286 mac = ctx->ifc_mac; 1287 uuid[HOSTUUIDLEN] = 0; 1288 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN); 1289 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev)); 1290 /* 1291 * Generate a pseudo-random, deterministic MAC 1292 * address based on the UUID and unit number. 1293 * The FreeBSD Foundation OUI of 58-9C-FC is used. 1294 */ 1295 MD5Init(&mdctx); 1296 MD5Update(&mdctx, buf, strlen(buf)); 1297 MD5Final(digest, &mdctx); 1298 1299 mac[0] = 0x58; 1300 mac[1] = 0x9C; 1301 mac[2] = 0xFC; 1302 mac[3] = digest[0]; 1303 mac[4] = digest[1]; 1304 mac[5] = digest[2]; 1305 } 1306 1307 static void 1308 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1309 { 1310 iflib_fl_t fl; 1311 1312 fl = &rxq->ifr_fl[flid]; 1313 iru->iru_paddrs = fl->ifl_bus_addrs; 1314 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1315 iru->iru_idxs = fl->ifl_rxd_idxs; 1316 iru->iru_qsidx = rxq->ifr_id; 1317 iru->iru_buf_size = fl->ifl_buf_size; 1318 iru->iru_flidx = fl->ifl_id; 1319 } 1320 1321 static void 1322 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1323 { 1324 if (err) 1325 return; 1326 *(bus_addr_t *) arg = segs[0].ds_addr; 1327 } 1328 1329 int 1330 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1331 { 1332 int err; 1333 if_shared_ctx_t sctx = ctx->ifc_sctx; 1334 device_t dev = ctx->ifc_dev; 1335 1336 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1337 1338 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1339 sctx->isc_q_align, 0, /* alignment, bounds */ 1340 BUS_SPACE_MAXADDR, /* lowaddr */ 1341 BUS_SPACE_MAXADDR, /* highaddr */ 1342 NULL, NULL, /* filter, filterarg */ 1343 size, /* maxsize */ 1344 1, /* nsegments */ 1345 size, /* maxsegsize */ 1346 BUS_DMA_ALLOCNOW, /* flags */ 1347 NULL, /* lockfunc */ 1348 NULL, /* lockarg */ 1349 &dma->idi_tag); 1350 if (err) { 1351 device_printf(dev, 1352 "%s: bus_dma_tag_create failed: %d\n", 1353 __func__, err); 1354 goto fail_0; 1355 } 1356 1357 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1358 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1359 if (err) { 1360 device_printf(dev, 1361 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1362 __func__, (uintmax_t)size, err); 1363 goto fail_1; 1364 } 1365 1366 dma->idi_paddr = IF_BAD_DMA; 1367 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1368 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1369 if (err || dma->idi_paddr == IF_BAD_DMA) { 1370 device_printf(dev, 1371 "%s: bus_dmamap_load failed: %d\n", 1372 __func__, err); 1373 goto fail_2; 1374 } 1375 1376 dma->idi_size = size; 1377 return (0); 1378 1379 fail_2: 1380 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1381 fail_1: 1382 bus_dma_tag_destroy(dma->idi_tag); 1383 fail_0: 1384 dma->idi_tag = NULL; 1385 1386 return (err); 1387 } 1388 1389 int 1390 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1391 { 1392 int i, err; 1393 iflib_dma_info_t *dmaiter; 1394 1395 dmaiter = dmalist; 1396 for (i = 0; i < count; i++, dmaiter++) { 1397 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1398 break; 1399 } 1400 if (err) 1401 iflib_dma_free_multi(dmalist, i); 1402 return (err); 1403 } 1404 1405 void 1406 iflib_dma_free(iflib_dma_info_t dma) 1407 { 1408 if (dma->idi_tag == NULL) 1409 return; 1410 if (dma->idi_paddr != IF_BAD_DMA) { 1411 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1412 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1413 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1414 dma->idi_paddr = IF_BAD_DMA; 1415 } 1416 if (dma->idi_vaddr != NULL) { 1417 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1418 dma->idi_vaddr = NULL; 1419 } 1420 bus_dma_tag_destroy(dma->idi_tag); 1421 dma->idi_tag = NULL; 1422 } 1423 1424 void 1425 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1426 { 1427 int i; 1428 iflib_dma_info_t *dmaiter = dmalist; 1429 1430 for (i = 0; i < count; i++, dmaiter++) 1431 iflib_dma_free(*dmaiter); 1432 } 1433 1434 #ifdef EARLY_AP_STARTUP 1435 static const int iflib_started = 1; 1436 #else 1437 /* 1438 * We used to abuse the smp_started flag to decide if the queues have been 1439 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1440 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1441 * is set. Run a SYSINIT() strictly after that to just set a usable 1442 * completion flag. 1443 */ 1444 1445 static int iflib_started; 1446 1447 static void 1448 iflib_record_started(void *arg) 1449 { 1450 iflib_started = 1; 1451 } 1452 1453 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1454 iflib_record_started, NULL); 1455 #endif 1456 1457 static int 1458 iflib_fast_intr(void *arg) 1459 { 1460 iflib_filter_info_t info = arg; 1461 struct grouptask *gtask = info->ifi_task; 1462 if (!iflib_started) 1463 return (FILTER_HANDLED); 1464 1465 DBG_COUNTER_INC(fast_intrs); 1466 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1467 return (FILTER_HANDLED); 1468 1469 GROUPTASK_ENQUEUE(gtask); 1470 return (FILTER_HANDLED); 1471 } 1472 1473 static int 1474 iflib_fast_intr_rxtx(void *arg) 1475 { 1476 iflib_filter_info_t info = arg; 1477 struct grouptask *gtask = info->ifi_task; 1478 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1479 if_ctx_t ctx = NULL;; 1480 int i, cidx; 1481 1482 if (!iflib_started) 1483 return (FILTER_HANDLED); 1484 1485 DBG_COUNTER_INC(fast_intrs); 1486 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1487 return (FILTER_HANDLED); 1488 1489 MPASS(rxq->ifr_ntxqirq); 1490 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1491 qidx_t txqid = rxq->ifr_txqid[i]; 1492 1493 ctx = rxq->ifr_ctx; 1494 1495 bus_dmamap_sync(rxq->ifr_ifdi->idi_tag, rxq->ifr_ifdi->idi_map, 1496 BUS_DMASYNC_POSTREAD); 1497 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1498 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1499 continue; 1500 } 1501 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1502 } 1503 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1504 cidx = rxq->ifr_cq_cidx; 1505 else 1506 cidx = rxq->ifr_fl[0].ifl_cidx; 1507 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1508 GROUPTASK_ENQUEUE(gtask); 1509 else { 1510 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1511 DBG_COUNTER_INC(rx_intr_enables); 1512 } 1513 return (FILTER_HANDLED); 1514 } 1515 1516 1517 static int 1518 iflib_fast_intr_ctx(void *arg) 1519 { 1520 iflib_filter_info_t info = arg; 1521 struct grouptask *gtask = info->ifi_task; 1522 1523 if (!iflib_started) 1524 return (FILTER_HANDLED); 1525 1526 DBG_COUNTER_INC(fast_intrs); 1527 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1528 return (FILTER_HANDLED); 1529 1530 GROUPTASK_ENQUEUE(gtask); 1531 return (FILTER_HANDLED); 1532 } 1533 1534 static int 1535 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1536 driver_filter_t filter, driver_intr_t handler, void *arg, 1537 const char *name) 1538 { 1539 int rc, flags; 1540 struct resource *res; 1541 void *tag = NULL; 1542 device_t dev = ctx->ifc_dev; 1543 1544 flags = RF_ACTIVE; 1545 if (ctx->ifc_flags & IFC_LEGACY) 1546 flags |= RF_SHAREABLE; 1547 MPASS(rid < 512); 1548 irq->ii_rid = rid; 1549 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1550 if (res == NULL) { 1551 device_printf(dev, 1552 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1553 return (ENOMEM); 1554 } 1555 irq->ii_res = res; 1556 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1557 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1558 filter, handler, arg, &tag); 1559 if (rc != 0) { 1560 device_printf(dev, 1561 "failed to setup interrupt for rid %d, name %s: %d\n", 1562 rid, name ? name : "unknown", rc); 1563 return (rc); 1564 } else if (name) 1565 bus_describe_intr(dev, res, tag, "%s", name); 1566 1567 irq->ii_tag = tag; 1568 return (0); 1569 } 1570 1571 1572 /********************************************************************* 1573 * 1574 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1575 * the information needed to transmit a packet on the wire. This is 1576 * called only once at attach, setup is done every reset. 1577 * 1578 **********************************************************************/ 1579 1580 static int 1581 iflib_txsd_alloc(iflib_txq_t txq) 1582 { 1583 if_ctx_t ctx = txq->ift_ctx; 1584 if_shared_ctx_t sctx = ctx->ifc_sctx; 1585 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1586 device_t dev = ctx->ifc_dev; 1587 bus_size_t tsomaxsize; 1588 int err, nsegments, ntsosegments; 1589 bool tso; 1590 1591 nsegments = scctx->isc_tx_nsegments; 1592 ntsosegments = scctx->isc_tx_tso_segments_max; 1593 tsomaxsize = scctx->isc_tx_tso_size_max; 1594 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1595 tsomaxsize += sizeof(struct ether_vlan_header); 1596 MPASS(scctx->isc_ntxd[0] > 0); 1597 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1598 MPASS(nsegments > 0); 1599 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1600 MPASS(ntsosegments > 0); 1601 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1602 } 1603 1604 /* 1605 * Setup DMA descriptor areas. 1606 */ 1607 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1608 1, 0, /* alignment, bounds */ 1609 BUS_SPACE_MAXADDR, /* lowaddr */ 1610 BUS_SPACE_MAXADDR, /* highaddr */ 1611 NULL, NULL, /* filter, filterarg */ 1612 sctx->isc_tx_maxsize, /* maxsize */ 1613 nsegments, /* nsegments */ 1614 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1615 0, /* flags */ 1616 NULL, /* lockfunc */ 1617 NULL, /* lockfuncarg */ 1618 &txq->ift_desc_tag))) { 1619 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1620 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1621 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1622 goto fail; 1623 } 1624 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1625 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1626 1, 0, /* alignment, bounds */ 1627 BUS_SPACE_MAXADDR, /* lowaddr */ 1628 BUS_SPACE_MAXADDR, /* highaddr */ 1629 NULL, NULL, /* filter, filterarg */ 1630 tsomaxsize, /* maxsize */ 1631 ntsosegments, /* nsegments */ 1632 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1633 0, /* flags */ 1634 NULL, /* lockfunc */ 1635 NULL, /* lockfuncarg */ 1636 &txq->ift_tso_desc_tag))) { 1637 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1638 goto fail; 1639 } 1640 if (!(txq->ift_sds.ifsd_m = 1641 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1642 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1643 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1644 err = ENOMEM; 1645 goto fail; 1646 } 1647 1648 /* Create the descriptor buffer dma maps */ 1649 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1650 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1651 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1652 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1653 err = ENOMEM; 1654 goto fail; 1655 } 1656 1657 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1658 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1659 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1660 device_printf(dev, "Unable to allocate TSO tx_buffer " 1661 "map memory\n"); 1662 err = ENOMEM; 1663 goto fail; 1664 } 1665 1666 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1667 err = bus_dmamap_create(txq->ift_desc_tag, 0, 1668 &txq->ift_sds.ifsd_map[i]); 1669 if (err != 0) { 1670 device_printf(dev, "Unable to create TX DMA map\n"); 1671 goto fail; 1672 } 1673 if (!tso) 1674 continue; 1675 err = bus_dmamap_create(txq->ift_tso_desc_tag, 0, 1676 &txq->ift_sds.ifsd_tso_map[i]); 1677 if (err != 0) { 1678 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1679 goto fail; 1680 } 1681 } 1682 return (0); 1683 fail: 1684 /* We free all, it handles case where we are in the middle */ 1685 iflib_tx_structures_free(ctx); 1686 return (err); 1687 } 1688 1689 static void 1690 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1691 { 1692 bus_dmamap_t map; 1693 1694 map = NULL; 1695 if (txq->ift_sds.ifsd_map != NULL) 1696 map = txq->ift_sds.ifsd_map[i]; 1697 if (map != NULL) { 1698 bus_dmamap_sync(txq->ift_desc_tag, map, BUS_DMASYNC_POSTWRITE); 1699 bus_dmamap_unload(txq->ift_desc_tag, map); 1700 bus_dmamap_destroy(txq->ift_desc_tag, map); 1701 txq->ift_sds.ifsd_map[i] = NULL; 1702 } 1703 1704 map = NULL; 1705 if (txq->ift_sds.ifsd_tso_map != NULL) 1706 map = txq->ift_sds.ifsd_tso_map[i]; 1707 if (map != NULL) { 1708 bus_dmamap_sync(txq->ift_tso_desc_tag, map, 1709 BUS_DMASYNC_POSTWRITE); 1710 bus_dmamap_unload(txq->ift_tso_desc_tag, map); 1711 bus_dmamap_destroy(txq->ift_tso_desc_tag, map); 1712 txq->ift_sds.ifsd_tso_map[i] = NULL; 1713 } 1714 } 1715 1716 static void 1717 iflib_txq_destroy(iflib_txq_t txq) 1718 { 1719 if_ctx_t ctx = txq->ift_ctx; 1720 1721 for (int i = 0; i < txq->ift_size; i++) 1722 iflib_txsd_destroy(ctx, txq, i); 1723 if (txq->ift_sds.ifsd_map != NULL) { 1724 free(txq->ift_sds.ifsd_map, M_IFLIB); 1725 txq->ift_sds.ifsd_map = NULL; 1726 } 1727 if (txq->ift_sds.ifsd_tso_map != NULL) { 1728 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1729 txq->ift_sds.ifsd_tso_map = NULL; 1730 } 1731 if (txq->ift_sds.ifsd_m != NULL) { 1732 free(txq->ift_sds.ifsd_m, M_IFLIB); 1733 txq->ift_sds.ifsd_m = NULL; 1734 } 1735 if (txq->ift_desc_tag != NULL) { 1736 bus_dma_tag_destroy(txq->ift_desc_tag); 1737 txq->ift_desc_tag = NULL; 1738 } 1739 if (txq->ift_tso_desc_tag != NULL) { 1740 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1741 txq->ift_tso_desc_tag = NULL; 1742 } 1743 } 1744 1745 static void 1746 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1747 { 1748 struct mbuf **mp; 1749 1750 mp = &txq->ift_sds.ifsd_m[i]; 1751 if (*mp == NULL) 1752 return; 1753 1754 if (txq->ift_sds.ifsd_map != NULL) { 1755 bus_dmamap_sync(txq->ift_desc_tag, 1756 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1757 bus_dmamap_unload(txq->ift_desc_tag, txq->ift_sds.ifsd_map[i]); 1758 } 1759 if (txq->ift_sds.ifsd_tso_map != NULL) { 1760 bus_dmamap_sync(txq->ift_tso_desc_tag, 1761 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1762 bus_dmamap_unload(txq->ift_tso_desc_tag, 1763 txq->ift_sds.ifsd_tso_map[i]); 1764 } 1765 m_free(*mp); 1766 DBG_COUNTER_INC(tx_frees); 1767 *mp = NULL; 1768 } 1769 1770 static int 1771 iflib_txq_setup(iflib_txq_t txq) 1772 { 1773 if_ctx_t ctx = txq->ift_ctx; 1774 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1775 if_shared_ctx_t sctx = ctx->ifc_sctx; 1776 iflib_dma_info_t di; 1777 int i; 1778 1779 /* Set number of descriptors available */ 1780 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1781 /* XXX make configurable */ 1782 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1783 1784 /* Reset indices */ 1785 txq->ift_cidx_processed = 0; 1786 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1787 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1788 1789 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1790 bzero((void *)di->idi_vaddr, di->idi_size); 1791 1792 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1793 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1794 bus_dmamap_sync(di->idi_tag, di->idi_map, 1795 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1796 return (0); 1797 } 1798 1799 /********************************************************************* 1800 * 1801 * Allocate memory for rx_buffer structures. Since we use one 1802 * rx_buffer per received packet, the maximum number of rx_buffer's 1803 * that we'll need is equal to the number of receive descriptors 1804 * that we've allocated. 1805 * 1806 **********************************************************************/ 1807 static int 1808 iflib_rxsd_alloc(iflib_rxq_t rxq) 1809 { 1810 if_ctx_t ctx = rxq->ifr_ctx; 1811 if_shared_ctx_t sctx = ctx->ifc_sctx; 1812 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1813 device_t dev = ctx->ifc_dev; 1814 iflib_fl_t fl; 1815 int err; 1816 1817 MPASS(scctx->isc_nrxd[0] > 0); 1818 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1819 1820 fl = rxq->ifr_fl; 1821 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1822 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1823 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1824 1, 0, /* alignment, bounds */ 1825 BUS_SPACE_MAXADDR, /* lowaddr */ 1826 BUS_SPACE_MAXADDR, /* highaddr */ 1827 NULL, NULL, /* filter, filterarg */ 1828 sctx->isc_rx_maxsize, /* maxsize */ 1829 sctx->isc_rx_nsegments, /* nsegments */ 1830 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1831 0, /* flags */ 1832 NULL, /* lockfunc */ 1833 NULL, /* lockarg */ 1834 &fl->ifl_desc_tag); 1835 if (err) { 1836 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1837 __func__, err); 1838 goto fail; 1839 } 1840 if (!(fl->ifl_sds.ifsd_m = 1841 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1842 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1843 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1844 err = ENOMEM; 1845 goto fail; 1846 } 1847 if (!(fl->ifl_sds.ifsd_cl = 1848 (caddr_t *) malloc(sizeof(caddr_t) * 1849 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1850 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1851 err = ENOMEM; 1852 goto fail; 1853 } 1854 1855 if (!(fl->ifl_sds.ifsd_ba = 1856 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1857 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1858 device_printf(dev, "Unable to allocate rx bus addr memory\n"); 1859 err = ENOMEM; 1860 goto fail; 1861 } 1862 1863 /* Create the descriptor buffer dma maps */ 1864 if (!(fl->ifl_sds.ifsd_map = 1865 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1866 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1867 err = ENOMEM; 1868 goto fail; 1869 } 1870 1871 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1872 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1873 if (err != 0) { 1874 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1875 goto fail; 1876 } 1877 } 1878 } 1879 return (0); 1880 1881 fail: 1882 iflib_rx_structures_free(ctx); 1883 return (err); 1884 } 1885 1886 1887 /* 1888 * Internal service routines 1889 */ 1890 1891 struct rxq_refill_cb_arg { 1892 int error; 1893 bus_dma_segment_t seg; 1894 int nseg; 1895 }; 1896 1897 static void 1898 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1899 { 1900 struct rxq_refill_cb_arg *cb_arg = arg; 1901 1902 cb_arg->error = error; 1903 cb_arg->seg = segs[0]; 1904 cb_arg->nseg = nseg; 1905 } 1906 1907 /** 1908 * rxq_refill - refill an rxq free-buffer list 1909 * @ctx: the iflib context 1910 * @rxq: the free-list to refill 1911 * @n: the number of new buffers to allocate 1912 * 1913 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1914 * The caller must assure that @n does not exceed the queue's capacity. 1915 */ 1916 static void 1917 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1918 { 1919 struct mbuf *m; 1920 int idx, frag_idx = fl->ifl_fragidx; 1921 int pidx = fl->ifl_pidx; 1922 caddr_t cl, *sd_cl; 1923 struct mbuf **sd_m; 1924 struct if_rxd_update iru; 1925 struct rxq_refill_cb_arg cb_arg; 1926 bus_dmamap_t *sd_map; 1927 int n, i = 0; 1928 bus_addr_t bus_addr, *sd_ba; 1929 int err; 1930 qidx_t credits; 1931 1932 sd_m = fl->ifl_sds.ifsd_m; 1933 sd_map = fl->ifl_sds.ifsd_map; 1934 sd_cl = fl->ifl_sds.ifsd_cl; 1935 sd_ba = fl->ifl_sds.ifsd_ba; 1936 idx = pidx; 1937 credits = fl->ifl_credits; 1938 1939 n = count; 1940 MPASS(n > 0); 1941 MPASS(credits + n <= fl->ifl_size); 1942 1943 if (pidx < fl->ifl_cidx) 1944 MPASS(pidx + n <= fl->ifl_cidx); 1945 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1946 MPASS(fl->ifl_gen == 0); 1947 if (pidx > fl->ifl_cidx) 1948 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1949 1950 DBG_COUNTER_INC(fl_refills); 1951 if (n > 8) 1952 DBG_COUNTER_INC(fl_refills_large); 1953 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1954 while (n--) { 1955 /* 1956 * We allocate an uninitialized mbuf + cluster, mbuf is 1957 * initialized after rx. 1958 * 1959 * If the cluster is still set then we know a minimum sized packet was received 1960 */ 1961 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1962 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1963 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1964 if ((cl = sd_cl[frag_idx]) == NULL) { 1965 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1966 break; 1967 1968 cb_arg.error = 0; 1969 MPASS(sd_map != NULL); 1970 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1971 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 1972 BUS_DMA_NOWAIT); 1973 if (err != 0 || cb_arg.error) { 1974 /* 1975 * !zone_pack ? 1976 */ 1977 if (fl->ifl_zone == zone_pack) 1978 uma_zfree(fl->ifl_zone, cl); 1979 break; 1980 } 1981 1982 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 1983 BUS_DMASYNC_PREREAD); 1984 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 1985 sd_cl[frag_idx] = cl; 1986 #if MEMORY_LOGGING 1987 fl->ifl_cl_enqueued++; 1988 #endif 1989 } else { 1990 bus_addr = sd_ba[frag_idx]; 1991 } 1992 1993 bit_set(fl->ifl_rx_bitmap, frag_idx); 1994 MPASS(sd_m[frag_idx] == NULL); 1995 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1996 break; 1997 } 1998 sd_m[frag_idx] = m; 1999 #if MEMORY_LOGGING 2000 fl->ifl_m_enqueued++; 2001 #endif 2002 2003 DBG_COUNTER_INC(rx_allocs); 2004 fl->ifl_rxd_idxs[i] = frag_idx; 2005 fl->ifl_bus_addrs[i] = bus_addr; 2006 fl->ifl_vm_addrs[i] = cl; 2007 credits++; 2008 i++; 2009 MPASS(credits <= fl->ifl_size); 2010 if (++idx == fl->ifl_size) { 2011 fl->ifl_gen = 1; 2012 idx = 0; 2013 } 2014 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2015 iru.iru_pidx = pidx; 2016 iru.iru_count = i; 2017 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2018 i = 0; 2019 pidx = idx; 2020 fl->ifl_pidx = idx; 2021 fl->ifl_credits = credits; 2022 } 2023 2024 } 2025 2026 if (i) { 2027 iru.iru_pidx = pidx; 2028 iru.iru_count = i; 2029 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2030 fl->ifl_pidx = idx; 2031 fl->ifl_credits = credits; 2032 } 2033 DBG_COUNTER_INC(rxd_flush); 2034 if (fl->ifl_pidx == 0) 2035 pidx = fl->ifl_size - 1; 2036 else 2037 pidx = fl->ifl_pidx - 1; 2038 2039 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2040 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2041 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2042 fl->ifl_fragidx = frag_idx; 2043 } 2044 2045 static __inline void 2046 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2047 { 2048 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2049 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2050 #ifdef INVARIANTS 2051 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2052 #endif 2053 2054 MPASS(fl->ifl_credits <= fl->ifl_size); 2055 MPASS(reclaimable == delta); 2056 2057 if (reclaimable > 0) 2058 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2059 } 2060 2061 uint8_t 2062 iflib_in_detach(if_ctx_t ctx) 2063 { 2064 bool in_detach; 2065 STATE_LOCK(ctx); 2066 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2067 STATE_UNLOCK(ctx); 2068 return (in_detach); 2069 } 2070 2071 static void 2072 iflib_fl_bufs_free(iflib_fl_t fl) 2073 { 2074 iflib_dma_info_t idi = fl->ifl_ifdi; 2075 bus_dmamap_t sd_map; 2076 uint32_t i; 2077 2078 for (i = 0; i < fl->ifl_size; i++) { 2079 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2080 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2081 2082 if (*sd_cl != NULL) { 2083 sd_map = fl->ifl_sds.ifsd_map[i]; 2084 bus_dmamap_sync(fl->ifl_desc_tag, sd_map, 2085 BUS_DMASYNC_POSTREAD); 2086 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 2087 if (*sd_cl != NULL) 2088 uma_zfree(fl->ifl_zone, *sd_cl); 2089 // XXX: Should this get moved out? 2090 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx)) 2091 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 2092 if (*sd_m != NULL) { 2093 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2094 uma_zfree(zone_mbuf, *sd_m); 2095 } 2096 } else { 2097 MPASS(*sd_cl == NULL); 2098 MPASS(*sd_m == NULL); 2099 } 2100 #if MEMORY_LOGGING 2101 fl->ifl_m_dequeued++; 2102 fl->ifl_cl_dequeued++; 2103 #endif 2104 *sd_cl = NULL; 2105 *sd_m = NULL; 2106 } 2107 #ifdef INVARIANTS 2108 for (i = 0; i < fl->ifl_size; i++) { 2109 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2110 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2111 } 2112 #endif 2113 /* 2114 * Reset free list values 2115 */ 2116 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2117 bzero(idi->idi_vaddr, idi->idi_size); 2118 } 2119 2120 /********************************************************************* 2121 * 2122 * Initialize a receive ring and its buffers. 2123 * 2124 **********************************************************************/ 2125 static int 2126 iflib_fl_setup(iflib_fl_t fl) 2127 { 2128 iflib_rxq_t rxq = fl->ifl_rxq; 2129 if_ctx_t ctx = rxq->ifr_ctx; 2130 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2131 2132 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2133 /* 2134 ** Free current RX buffer structs and their mbufs 2135 */ 2136 iflib_fl_bufs_free(fl); 2137 /* Now replenish the mbufs */ 2138 MPASS(fl->ifl_credits == 0); 2139 /* 2140 * XXX don't set the max_frame_size to larger 2141 * than the hardware can handle 2142 */ 2143 if (sctx->isc_max_frame_size <= 2048) 2144 fl->ifl_buf_size = MCLBYTES; 2145 #ifndef CONTIGMALLOC_WORKS 2146 else 2147 fl->ifl_buf_size = MJUMPAGESIZE; 2148 #else 2149 else if (sctx->isc_max_frame_size <= 4096) 2150 fl->ifl_buf_size = MJUMPAGESIZE; 2151 else if (sctx->isc_max_frame_size <= 9216) 2152 fl->ifl_buf_size = MJUM9BYTES; 2153 else 2154 fl->ifl_buf_size = MJUM16BYTES; 2155 #endif 2156 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2157 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2158 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2159 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2160 2161 2162 /* avoid pre-allocating zillions of clusters to an idle card 2163 * potentially speeding up attach 2164 */ 2165 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2166 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2167 if (min(128, fl->ifl_size) != fl->ifl_credits) 2168 return (ENOBUFS); 2169 /* 2170 * handle failure 2171 */ 2172 MPASS(rxq != NULL); 2173 MPASS(fl->ifl_ifdi != NULL); 2174 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2175 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2176 return (0); 2177 } 2178 2179 /********************************************************************* 2180 * 2181 * Free receive ring data structures 2182 * 2183 **********************************************************************/ 2184 static void 2185 iflib_rx_sds_free(iflib_rxq_t rxq) 2186 { 2187 iflib_fl_t fl; 2188 int i, j; 2189 2190 if (rxq->ifr_fl != NULL) { 2191 for (i = 0; i < rxq->ifr_nfl; i++) { 2192 fl = &rxq->ifr_fl[i]; 2193 if (fl->ifl_desc_tag != NULL) { 2194 if (fl->ifl_sds.ifsd_map != NULL) { 2195 for (j = 0; j < fl->ifl_size; i++) { 2196 if (fl->ifl_sds.ifsd_map[i] == 2197 NULL) 2198 continue; 2199 bus_dmamap_sync( 2200 fl->ifl_desc_tag, 2201 fl->ifl_sds.ifsd_map[i], 2202 BUS_DMASYNC_POSTREAD); 2203 bus_dmamap_unload( 2204 fl->ifl_desc_tag, 2205 fl->ifl_sds.ifsd_map[i]); 2206 } 2207 } 2208 bus_dma_tag_destroy(fl->ifl_desc_tag); 2209 fl->ifl_desc_tag = NULL; 2210 } 2211 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2212 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2213 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2214 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2215 fl->ifl_sds.ifsd_m = NULL; 2216 fl->ifl_sds.ifsd_cl = NULL; 2217 fl->ifl_sds.ifsd_ba = NULL; 2218 fl->ifl_sds.ifsd_map = NULL; 2219 } 2220 free(rxq->ifr_fl, M_IFLIB); 2221 rxq->ifr_fl = NULL; 2222 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2223 } 2224 } 2225 2226 /* 2227 * MI independent logic 2228 * 2229 */ 2230 static void 2231 iflib_timer(void *arg) 2232 { 2233 iflib_txq_t txq = arg; 2234 if_ctx_t ctx = txq->ift_ctx; 2235 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2236 uint64_t this_tick = ticks; 2237 uint32_t reset_on = hz / 2; 2238 2239 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2240 return; 2241 /* 2242 ** Check on the state of the TX queue(s), this 2243 ** can be done without the lock because its RO 2244 ** and the HUNG state will be static if set. 2245 */ 2246 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2247 txq->ift_last_timer_tick = this_tick; 2248 IFDI_TIMER(ctx, txq->ift_id); 2249 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2250 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2251 (sctx->isc_pause_frames == 0))) 2252 goto hung; 2253 2254 if (ifmp_ring_is_stalled(txq->ift_br)) 2255 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2256 txq->ift_cleaned_prev = txq->ift_cleaned; 2257 } 2258 #ifdef DEV_NETMAP 2259 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2260 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on); 2261 #endif 2262 /* handle any laggards */ 2263 if (txq->ift_db_pending) 2264 GROUPTASK_ENQUEUE(&txq->ift_task); 2265 2266 sctx->isc_pause_frames = 0; 2267 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2268 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2269 return; 2270 hung: 2271 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2272 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2273 STATE_LOCK(ctx); 2274 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2275 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2276 iflib_admin_intr_deferred(ctx); 2277 STATE_UNLOCK(ctx); 2278 } 2279 2280 static void 2281 iflib_init_locked(if_ctx_t ctx) 2282 { 2283 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2284 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2285 if_t ifp = ctx->ifc_ifp; 2286 iflib_fl_t fl; 2287 iflib_txq_t txq; 2288 iflib_rxq_t rxq; 2289 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2290 2291 2292 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2293 IFDI_INTR_DISABLE(ctx); 2294 2295 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2296 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2297 /* Set hardware offload abilities */ 2298 if_clearhwassist(ifp); 2299 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2300 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2301 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2302 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2303 if (if_getcapenable(ifp) & IFCAP_TSO4) 2304 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2305 if (if_getcapenable(ifp) & IFCAP_TSO6) 2306 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2307 2308 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2309 CALLOUT_LOCK(txq); 2310 callout_stop(&txq->ift_timer); 2311 CALLOUT_UNLOCK(txq); 2312 iflib_netmap_txq_init(ctx, txq); 2313 } 2314 #ifdef INVARIANTS 2315 i = if_getdrvflags(ifp); 2316 #endif 2317 IFDI_INIT(ctx); 2318 MPASS(if_getdrvflags(ifp) == i); 2319 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2320 /* XXX this should really be done on a per-queue basis */ 2321 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2322 MPASS(rxq->ifr_id == i); 2323 iflib_netmap_rxq_init(ctx, rxq); 2324 continue; 2325 } 2326 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2327 if (iflib_fl_setup(fl)) { 2328 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2329 goto done; 2330 } 2331 } 2332 } 2333 done: 2334 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2335 IFDI_INTR_ENABLE(ctx); 2336 txq = ctx->ifc_txqs; 2337 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2338 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2339 txq->ift_timer.c_cpu); 2340 } 2341 2342 static int 2343 iflib_media_change(if_t ifp) 2344 { 2345 if_ctx_t ctx = if_getsoftc(ifp); 2346 int err; 2347 2348 CTX_LOCK(ctx); 2349 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2350 iflib_init_locked(ctx); 2351 CTX_UNLOCK(ctx); 2352 return (err); 2353 } 2354 2355 static void 2356 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2357 { 2358 if_ctx_t ctx = if_getsoftc(ifp); 2359 2360 CTX_LOCK(ctx); 2361 IFDI_UPDATE_ADMIN_STATUS(ctx); 2362 IFDI_MEDIA_STATUS(ctx, ifmr); 2363 CTX_UNLOCK(ctx); 2364 } 2365 2366 void 2367 iflib_stop(if_ctx_t ctx) 2368 { 2369 iflib_txq_t txq = ctx->ifc_txqs; 2370 iflib_rxq_t rxq = ctx->ifc_rxqs; 2371 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2372 if_shared_ctx_t sctx = ctx->ifc_sctx; 2373 iflib_dma_info_t di; 2374 iflib_fl_t fl; 2375 int i, j; 2376 2377 /* Tell the stack that the interface is no longer active */ 2378 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2379 2380 IFDI_INTR_DISABLE(ctx); 2381 DELAY(1000); 2382 IFDI_STOP(ctx); 2383 DELAY(1000); 2384 2385 iflib_debug_reset(); 2386 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2387 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2388 /* make sure all transmitters have completed before proceeding XXX */ 2389 2390 CALLOUT_LOCK(txq); 2391 callout_stop(&txq->ift_timer); 2392 CALLOUT_UNLOCK(txq); 2393 2394 /* clean any enqueued buffers */ 2395 iflib_ifmp_purge(txq); 2396 /* Free any existing tx buffers. */ 2397 for (j = 0; j < txq->ift_size; j++) { 2398 iflib_txsd_free(ctx, txq, j); 2399 } 2400 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2401 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2402 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2403 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2404 txq->ift_pullups = 0; 2405 ifmp_ring_reset_stats(txq->ift_br); 2406 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2407 bzero((void *)di->idi_vaddr, di->idi_size); 2408 } 2409 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2410 /* make sure all transmitters have completed before proceeding XXX */ 2411 2412 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2413 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2414 bzero((void *)di->idi_vaddr, di->idi_size); 2415 /* also resets the free lists pidx/cidx */ 2416 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2417 iflib_fl_bufs_free(fl); 2418 } 2419 } 2420 2421 static inline caddr_t 2422 calc_next_rxd(iflib_fl_t fl, int cidx) 2423 { 2424 qidx_t size; 2425 int nrxd; 2426 caddr_t start, end, cur, next; 2427 2428 nrxd = fl->ifl_size; 2429 size = fl->ifl_rxd_size; 2430 start = fl->ifl_ifdi->idi_vaddr; 2431 2432 if (__predict_false(size == 0)) 2433 return (start); 2434 cur = start + size*cidx; 2435 end = start + size*nrxd; 2436 next = CACHE_PTR_NEXT(cur); 2437 return (next < end ? next : start); 2438 } 2439 2440 static inline void 2441 prefetch_pkts(iflib_fl_t fl, int cidx) 2442 { 2443 int nextptr; 2444 int nrxd = fl->ifl_size; 2445 caddr_t next_rxd; 2446 2447 2448 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2449 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2450 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2451 next_rxd = calc_next_rxd(fl, cidx); 2452 prefetch(next_rxd); 2453 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2454 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2455 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2456 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2457 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2458 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2459 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2460 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2461 } 2462 2463 static void 2464 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2465 { 2466 int flid, cidx; 2467 bus_dmamap_t map; 2468 iflib_fl_t fl; 2469 iflib_dma_info_t di; 2470 int next; 2471 2472 map = NULL; 2473 flid = irf->irf_flid; 2474 cidx = irf->irf_idx; 2475 fl = &rxq->ifr_fl[flid]; 2476 sd->ifsd_fl = fl; 2477 sd->ifsd_cidx = cidx; 2478 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2479 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2480 fl->ifl_credits--; 2481 #if MEMORY_LOGGING 2482 fl->ifl_m_dequeued++; 2483 #endif 2484 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2485 prefetch_pkts(fl, cidx); 2486 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2487 prefetch(&fl->ifl_sds.ifsd_map[next]); 2488 map = fl->ifl_sds.ifsd_map[cidx]; 2489 di = fl->ifl_ifdi; 2490 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2491 2492 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2493 MPASS(fl->ifl_cidx == cidx); 2494 bus_dmamap_sync(fl->ifl_desc_tag, map, BUS_DMASYNC_POSTREAD); 2495 if (unload) 2496 bus_dmamap_unload(fl->ifl_desc_tag, map); 2497 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2498 if (__predict_false(fl->ifl_cidx == 0)) 2499 fl->ifl_gen = 0; 2500 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2501 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2502 bit_clear(fl->ifl_rx_bitmap, cidx); 2503 } 2504 2505 static struct mbuf * 2506 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2507 { 2508 int i, padlen , flags; 2509 struct mbuf *m, *mh, *mt; 2510 caddr_t cl; 2511 2512 i = 0; 2513 mh = NULL; 2514 do { 2515 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2516 2517 MPASS(*sd->ifsd_cl != NULL); 2518 MPASS(*sd->ifsd_m != NULL); 2519 2520 /* Don't include zero-length frags */ 2521 if (ri->iri_frags[i].irf_len == 0) { 2522 /* XXX we can save the cluster here, but not the mbuf */ 2523 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2524 m_free(*sd->ifsd_m); 2525 *sd->ifsd_m = NULL; 2526 continue; 2527 } 2528 m = *sd->ifsd_m; 2529 *sd->ifsd_m = NULL; 2530 if (mh == NULL) { 2531 flags = M_PKTHDR|M_EXT; 2532 mh = mt = m; 2533 padlen = ri->iri_pad; 2534 } else { 2535 flags = M_EXT; 2536 mt->m_next = m; 2537 mt = m; 2538 /* assuming padding is only on the first fragment */ 2539 padlen = 0; 2540 } 2541 cl = *sd->ifsd_cl; 2542 *sd->ifsd_cl = NULL; 2543 2544 /* Can these two be made one ? */ 2545 m_init(m, M_NOWAIT, MT_DATA, flags); 2546 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2547 /* 2548 * These must follow m_init and m_cljset 2549 */ 2550 m->m_data += padlen; 2551 ri->iri_len -= padlen; 2552 m->m_len = ri->iri_frags[i].irf_len; 2553 } while (++i < ri->iri_nfrags); 2554 2555 return (mh); 2556 } 2557 2558 /* 2559 * Process one software descriptor 2560 */ 2561 static struct mbuf * 2562 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2563 { 2564 struct if_rxsd sd; 2565 struct mbuf *m; 2566 2567 /* should I merge this back in now that the two paths are basically duplicated? */ 2568 if (ri->iri_nfrags == 1 && 2569 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2570 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2571 m = *sd.ifsd_m; 2572 *sd.ifsd_m = NULL; 2573 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2574 #ifndef __NO_STRICT_ALIGNMENT 2575 if (!IP_ALIGNED(m)) 2576 m->m_data += 2; 2577 #endif 2578 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2579 bus_dmamap_sync(rxq->ifr_fl->ifl_desc_tag, 2580 rxq->ifr_fl->ifl_sds.ifsd_map[ri->iri_frags[0].irf_idx], 2581 BUS_DMASYNC_PREREAD); 2582 m->m_len = ri->iri_frags[0].irf_len; 2583 } else { 2584 m = assemble_segments(rxq, ri, &sd); 2585 } 2586 m->m_pkthdr.len = ri->iri_len; 2587 m->m_pkthdr.rcvif = ri->iri_ifp; 2588 m->m_flags |= ri->iri_flags; 2589 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2590 m->m_pkthdr.flowid = ri->iri_flowid; 2591 M_HASHTYPE_SET(m, ri->iri_rsstype); 2592 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2593 m->m_pkthdr.csum_data = ri->iri_csum_data; 2594 return (m); 2595 } 2596 2597 #if defined(INET6) || defined(INET) 2598 static void 2599 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2600 { 2601 CURVNET_SET(lc->ifp->if_vnet); 2602 #if defined(INET6) 2603 *v6 = VNET(ip6_forwarding); 2604 #endif 2605 #if defined(INET) 2606 *v4 = VNET(ipforwarding); 2607 #endif 2608 CURVNET_RESTORE(); 2609 } 2610 2611 /* 2612 * Returns true if it's possible this packet could be LROed. 2613 * if it returns false, it is guaranteed that tcp_lro_rx() 2614 * would not return zero. 2615 */ 2616 static bool 2617 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2618 { 2619 struct ether_header *eh; 2620 uint16_t eh_type; 2621 2622 eh = mtod(m, struct ether_header *); 2623 eh_type = ntohs(eh->ether_type); 2624 switch (eh_type) { 2625 #if defined(INET6) 2626 case ETHERTYPE_IPV6: 2627 return !v6_forwarding; 2628 #endif 2629 #if defined (INET) 2630 case ETHERTYPE_IP: 2631 return !v4_forwarding; 2632 #endif 2633 } 2634 2635 return false; 2636 } 2637 #else 2638 static void 2639 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2640 { 2641 } 2642 #endif 2643 2644 static bool 2645 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2646 { 2647 if_ctx_t ctx = rxq->ifr_ctx; 2648 if_shared_ctx_t sctx = ctx->ifc_sctx; 2649 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2650 iflib_dma_info_t di; 2651 int avail, i; 2652 qidx_t *cidxp; 2653 struct if_rxd_info ri; 2654 int err, budget_left, rx_bytes, rx_pkts; 2655 iflib_fl_t fl; 2656 struct ifnet *ifp; 2657 int lro_enabled; 2658 bool v4_forwarding, v6_forwarding, lro_possible; 2659 2660 /* 2661 * XXX early demux data packets so that if_input processing only handles 2662 * acks in interrupt context 2663 */ 2664 struct mbuf *m, *mh, *mt, *mf; 2665 2666 lro_possible = v4_forwarding = v6_forwarding = false; 2667 ifp = ctx->ifc_ifp; 2668 mh = mt = NULL; 2669 MPASS(budget > 0); 2670 rx_pkts = rx_bytes = 0; 2671 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2672 cidxp = &rxq->ifr_cq_cidx; 2673 else 2674 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2675 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2676 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2677 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2678 DBG_COUNTER_INC(rx_unavail); 2679 return (false); 2680 } 2681 2682 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2683 if (__predict_false(!CTX_ACTIVE(ctx))) { 2684 DBG_COUNTER_INC(rx_ctx_inactive); 2685 break; 2686 } 2687 /* 2688 * Reset client set fields to their default values 2689 */ 2690 rxd_info_zero(&ri); 2691 ri.iri_qsidx = rxq->ifr_id; 2692 ri.iri_cidx = *cidxp; 2693 ri.iri_ifp = ifp; 2694 ri.iri_frags = rxq->ifr_frags; 2695 di = rxq->ifr_fl[rxq->ifr_frags[0].irf_flid].ifl_ifdi; 2696 bus_dmamap_sync(di->idi_tag, di->idi_map, 2697 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2698 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2699 2700 if (err) 2701 goto err; 2702 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2703 *cidxp = ri.iri_cidx; 2704 /* Update our consumer index */ 2705 /* XXX NB: shurd - check if this is still safe */ 2706 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2707 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2708 rxq->ifr_cq_gen = 0; 2709 } 2710 /* was this only a completion queue message? */ 2711 if (__predict_false(ri.iri_nfrags == 0)) 2712 continue; 2713 } 2714 MPASS(ri.iri_nfrags != 0); 2715 MPASS(ri.iri_len != 0); 2716 2717 /* will advance the cidx on the corresponding free lists */ 2718 m = iflib_rxd_pkt_get(rxq, &ri); 2719 avail--; 2720 budget_left--; 2721 if (avail == 0 && budget_left) 2722 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2723 2724 if (__predict_false(m == NULL)) { 2725 DBG_COUNTER_INC(rx_mbuf_null); 2726 continue; 2727 } 2728 /* imm_pkt: -- cxgb */ 2729 if (mh == NULL) 2730 mh = mt = m; 2731 else { 2732 mt->m_nextpkt = m; 2733 mt = m; 2734 } 2735 } 2736 /* make sure that we can refill faster than drain */ 2737 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2738 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2739 2740 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2741 if (lro_enabled) 2742 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2743 mt = mf = NULL; 2744 while (mh != NULL) { 2745 m = mh; 2746 mh = mh->m_nextpkt; 2747 m->m_nextpkt = NULL; 2748 #ifndef __NO_STRICT_ALIGNMENT 2749 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2750 continue; 2751 #endif 2752 rx_bytes += m->m_pkthdr.len; 2753 rx_pkts++; 2754 #if defined(INET6) || defined(INET) 2755 if (lro_enabled) { 2756 if (!lro_possible) { 2757 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2758 if (lro_possible && mf != NULL) { 2759 ifp->if_input(ifp, mf); 2760 DBG_COUNTER_INC(rx_if_input); 2761 mt = mf = NULL; 2762 } 2763 } 2764 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2765 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2766 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2767 continue; 2768 } 2769 } 2770 #endif 2771 if (lro_possible) { 2772 ifp->if_input(ifp, m); 2773 DBG_COUNTER_INC(rx_if_input); 2774 continue; 2775 } 2776 2777 if (mf == NULL) 2778 mf = m; 2779 if (mt != NULL) 2780 mt->m_nextpkt = m; 2781 mt = m; 2782 } 2783 if (mf != NULL) { 2784 ifp->if_input(ifp, mf); 2785 DBG_COUNTER_INC(rx_if_input); 2786 } 2787 2788 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2789 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2790 2791 /* 2792 * Flush any outstanding LRO work 2793 */ 2794 #if defined(INET6) || defined(INET) 2795 tcp_lro_flush_all(&rxq->ifr_lc); 2796 #endif 2797 if (avail) 2798 return true; 2799 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2800 err: 2801 STATE_LOCK(ctx); 2802 ctx->ifc_flags |= IFC_DO_RESET; 2803 iflib_admin_intr_deferred(ctx); 2804 STATE_UNLOCK(ctx); 2805 return (false); 2806 } 2807 2808 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2809 static inline qidx_t 2810 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2811 { 2812 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2813 qidx_t minthresh = txq->ift_size / 8; 2814 if (in_use > 4*minthresh) 2815 return (notify_count); 2816 if (in_use > 2*minthresh) 2817 return (notify_count >> 1); 2818 if (in_use > minthresh) 2819 return (notify_count >> 3); 2820 return (0); 2821 } 2822 2823 static inline qidx_t 2824 txq_max_rs_deferred(iflib_txq_t txq) 2825 { 2826 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2827 qidx_t minthresh = txq->ift_size / 8; 2828 if (txq->ift_in_use > 4*minthresh) 2829 return (notify_count); 2830 if (txq->ift_in_use > 2*minthresh) 2831 return (notify_count >> 1); 2832 if (txq->ift_in_use > minthresh) 2833 return (notify_count >> 2); 2834 return (2); 2835 } 2836 2837 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2838 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2839 2840 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2841 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2842 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2843 2844 /* forward compatibility for cxgb */ 2845 #define FIRST_QSET(ctx) 0 2846 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2847 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2848 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2849 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2850 2851 /* XXX we should be setting this to something other than zero */ 2852 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2853 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2854 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2855 2856 static inline bool 2857 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2858 { 2859 qidx_t dbval, max; 2860 bool rang; 2861 2862 rang = false; 2863 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2864 if (ring || txq->ift_db_pending >= max) { 2865 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2866 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2867 txq->ift_db_pending = txq->ift_npending = 0; 2868 rang = true; 2869 } 2870 return (rang); 2871 } 2872 2873 #ifdef PKT_DEBUG 2874 static void 2875 print_pkt(if_pkt_info_t pi) 2876 { 2877 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2878 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2879 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2880 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2881 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2882 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2883 } 2884 #endif 2885 2886 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2887 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2888 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2889 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2890 2891 static int 2892 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2893 { 2894 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2895 struct ether_vlan_header *eh; 2896 struct mbuf *m; 2897 2898 m = *mp; 2899 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2900 M_WRITABLE(m) == 0) { 2901 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2902 return (ENOMEM); 2903 } else { 2904 m_freem(*mp); 2905 DBG_COUNTER_INC(tx_frees); 2906 *mp = m; 2907 } 2908 } 2909 2910 /* 2911 * Determine where frame payload starts. 2912 * Jump over vlan headers if already present, 2913 * helpful for QinQ too. 2914 */ 2915 if (__predict_false(m->m_len < sizeof(*eh))) { 2916 txq->ift_pullups++; 2917 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2918 return (ENOMEM); 2919 } 2920 eh = mtod(m, struct ether_vlan_header *); 2921 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2922 pi->ipi_etype = ntohs(eh->evl_proto); 2923 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2924 } else { 2925 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2926 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2927 } 2928 2929 switch (pi->ipi_etype) { 2930 #ifdef INET 2931 case ETHERTYPE_IP: 2932 { 2933 struct mbuf *n; 2934 struct ip *ip = NULL; 2935 struct tcphdr *th = NULL; 2936 int minthlen; 2937 2938 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2939 if (__predict_false(m->m_len < minthlen)) { 2940 /* 2941 * if this code bloat is causing too much of a hit 2942 * move it to a separate function and mark it noinline 2943 */ 2944 if (m->m_len == pi->ipi_ehdrlen) { 2945 n = m->m_next; 2946 MPASS(n); 2947 if (n->m_len >= sizeof(*ip)) { 2948 ip = (struct ip *)n->m_data; 2949 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2950 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2951 } else { 2952 txq->ift_pullups++; 2953 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2954 return (ENOMEM); 2955 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2956 } 2957 } else { 2958 txq->ift_pullups++; 2959 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2960 return (ENOMEM); 2961 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2962 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2963 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2964 } 2965 } else { 2966 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2967 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2968 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2969 } 2970 pi->ipi_ip_hlen = ip->ip_hl << 2; 2971 pi->ipi_ipproto = ip->ip_p; 2972 pi->ipi_flags |= IPI_TX_IPV4; 2973 2974 /* TCP checksum offload may require TCP header length */ 2975 if (IS_TX_OFFLOAD4(pi)) { 2976 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 2977 if (__predict_false(th == NULL)) { 2978 txq->ift_pullups++; 2979 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2980 return (ENOMEM); 2981 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2982 } 2983 pi->ipi_tcp_hflags = th->th_flags; 2984 pi->ipi_tcp_hlen = th->th_off << 2; 2985 pi->ipi_tcp_seq = th->th_seq; 2986 } 2987 if (IS_TSO4(pi)) { 2988 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2989 return (ENXIO); 2990 /* 2991 * TSO always requires hardware checksum offload. 2992 */ 2993 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 2994 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2995 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2996 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2997 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2998 ip->ip_sum = 0; 2999 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3000 } 3001 } 3002 } 3003 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3004 ip->ip_sum = 0; 3005 3006 break; 3007 } 3008 #endif 3009 #ifdef INET6 3010 case ETHERTYPE_IPV6: 3011 { 3012 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3013 struct tcphdr *th; 3014 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3015 3016 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3017 txq->ift_pullups++; 3018 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3019 return (ENOMEM); 3020 } 3021 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3022 3023 /* XXX-BZ this will go badly in case of ext hdrs. */ 3024 pi->ipi_ipproto = ip6->ip6_nxt; 3025 pi->ipi_flags |= IPI_TX_IPV6; 3026 3027 /* TCP checksum offload may require TCP header length */ 3028 if (IS_TX_OFFLOAD6(pi)) { 3029 if (pi->ipi_ipproto == IPPROTO_TCP) { 3030 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3031 txq->ift_pullups++; 3032 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3033 return (ENOMEM); 3034 } 3035 pi->ipi_tcp_hflags = th->th_flags; 3036 pi->ipi_tcp_hlen = th->th_off << 2; 3037 pi->ipi_tcp_seq = th->th_seq; 3038 } 3039 if (IS_TSO6(pi)) { 3040 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3041 return (ENXIO); 3042 /* 3043 * TSO always requires hardware checksum offload. 3044 */ 3045 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3046 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3047 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3048 } 3049 } 3050 break; 3051 } 3052 #endif 3053 default: 3054 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3055 pi->ipi_ip_hlen = 0; 3056 break; 3057 } 3058 *mp = m; 3059 3060 return (0); 3061 } 3062 3063 /* 3064 * If dodgy hardware rejects the scatter gather chain we've handed it 3065 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3066 * m_defrag'd mbufs 3067 */ 3068 static __noinline struct mbuf * 3069 iflib_remove_mbuf(iflib_txq_t txq) 3070 { 3071 int ntxd, pidx; 3072 struct mbuf *m, **ifsd_m; 3073 3074 ifsd_m = txq->ift_sds.ifsd_m; 3075 ntxd = txq->ift_size; 3076 pidx = txq->ift_pidx & (ntxd - 1); 3077 ifsd_m = txq->ift_sds.ifsd_m; 3078 m = ifsd_m[pidx]; 3079 ifsd_m[pidx] = NULL; 3080 bus_dmamap_unload(txq->ift_desc_tag, txq->ift_sds.ifsd_map[pidx]); 3081 if (txq->ift_sds.ifsd_tso_map != NULL) 3082 bus_dmamap_unload(txq->ift_tso_desc_tag, 3083 txq->ift_sds.ifsd_tso_map[pidx]); 3084 #if MEMORY_LOGGING 3085 txq->ift_dequeued++; 3086 #endif 3087 return (m); 3088 } 3089 3090 static inline caddr_t 3091 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3092 { 3093 qidx_t size; 3094 int ntxd; 3095 caddr_t start, end, cur, next; 3096 3097 ntxd = txq->ift_size; 3098 size = txq->ift_txd_size[qid]; 3099 start = txq->ift_ifdi[qid].idi_vaddr; 3100 3101 if (__predict_false(size == 0)) 3102 return (start); 3103 cur = start + size*cidx; 3104 end = start + size*ntxd; 3105 next = CACHE_PTR_NEXT(cur); 3106 return (next < end ? next : start); 3107 } 3108 3109 /* 3110 * Pad an mbuf to ensure a minimum ethernet frame size. 3111 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3112 */ 3113 static __noinline int 3114 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3115 { 3116 /* 3117 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3118 * and ARP message is the smallest common payload I can think of 3119 */ 3120 static char pad[18]; /* just zeros */ 3121 int n; 3122 struct mbuf *new_head; 3123 3124 if (!M_WRITABLE(*m_head)) { 3125 new_head = m_dup(*m_head, M_NOWAIT); 3126 if (new_head == NULL) { 3127 m_freem(*m_head); 3128 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3129 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3130 DBG_COUNTER_INC(tx_frees); 3131 return ENOMEM; 3132 } 3133 m_freem(*m_head); 3134 *m_head = new_head; 3135 } 3136 3137 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3138 n > 0; n -= sizeof(pad)) 3139 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3140 break; 3141 3142 if (n > 0) { 3143 m_freem(*m_head); 3144 device_printf(dev, "cannot pad short frame\n"); 3145 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3146 DBG_COUNTER_INC(tx_frees); 3147 return (ENOBUFS); 3148 } 3149 3150 return 0; 3151 } 3152 3153 static int 3154 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3155 { 3156 if_ctx_t ctx; 3157 if_shared_ctx_t sctx; 3158 if_softc_ctx_t scctx; 3159 bus_dma_segment_t *segs; 3160 struct mbuf *m_head, **ifsd_m; 3161 void *next_txd; 3162 bus_dmamap_t map; 3163 struct if_pkt_info pi; 3164 int remap = 0; 3165 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3166 bus_dma_tag_t desc_tag; 3167 3168 ctx = txq->ift_ctx; 3169 sctx = ctx->ifc_sctx; 3170 scctx = &ctx->ifc_softc_ctx; 3171 segs = txq->ift_segs; 3172 ntxd = txq->ift_size; 3173 m_head = *m_headp; 3174 map = NULL; 3175 3176 /* 3177 * If we're doing TSO the next descriptor to clean may be quite far ahead 3178 */ 3179 cidx = txq->ift_cidx; 3180 pidx = txq->ift_pidx; 3181 if (ctx->ifc_flags & IFC_PREFETCH) { 3182 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3183 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3184 next_txd = calc_next_txd(txq, cidx, 0); 3185 prefetch(next_txd); 3186 } 3187 3188 /* prefetch the next cache line of mbuf pointers and flags */ 3189 prefetch(&txq->ift_sds.ifsd_m[next]); 3190 prefetch(&txq->ift_sds.ifsd_map[next]); 3191 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3192 } 3193 map = txq->ift_sds.ifsd_map[pidx]; 3194 ifsd_m = txq->ift_sds.ifsd_m; 3195 3196 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3197 desc_tag = txq->ift_tso_desc_tag; 3198 max_segs = scctx->isc_tx_tso_segments_max; 3199 map = txq->ift_sds.ifsd_tso_map[pidx]; 3200 MPASS(desc_tag != NULL); 3201 MPASS(max_segs > 0); 3202 } else { 3203 desc_tag = txq->ift_desc_tag; 3204 max_segs = scctx->isc_tx_nsegments; 3205 map = txq->ift_sds.ifsd_map[pidx]; 3206 } 3207 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3208 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3209 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3210 if (err) { 3211 DBG_COUNTER_INC(encap_txd_encap_fail); 3212 return err; 3213 } 3214 } 3215 m_head = *m_headp; 3216 3217 pkt_info_zero(&pi); 3218 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3219 pi.ipi_pidx = pidx; 3220 pi.ipi_qsidx = txq->ift_id; 3221 pi.ipi_len = m_head->m_pkthdr.len; 3222 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3223 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3224 3225 /* deliberate bitwise OR to make one condition */ 3226 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3227 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3228 DBG_COUNTER_INC(encap_txd_encap_fail); 3229 return (err); 3230 } 3231 m_head = *m_headp; 3232 } 3233 3234 retry: 3235 err = bus_dmamap_load_mbuf_sg(desc_tag, map, m_head, segs, &nsegs, 3236 BUS_DMA_NOWAIT); 3237 defrag: 3238 if (__predict_false(err)) { 3239 switch (err) { 3240 case EFBIG: 3241 /* try collapse once and defrag once */ 3242 if (remap == 0) { 3243 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3244 /* try defrag if collapsing fails */ 3245 if (m_head == NULL) 3246 remap++; 3247 } 3248 if (remap == 1) { 3249 txq->ift_mbuf_defrag++; 3250 m_head = m_defrag(*m_headp, M_NOWAIT); 3251 } 3252 remap++; 3253 if (__predict_false(m_head == NULL)) 3254 goto defrag_failed; 3255 *m_headp = m_head; 3256 goto retry; 3257 break; 3258 case ENOMEM: 3259 txq->ift_no_tx_dma_setup++; 3260 break; 3261 default: 3262 txq->ift_no_tx_dma_setup++; 3263 m_freem(*m_headp); 3264 DBG_COUNTER_INC(tx_frees); 3265 *m_headp = NULL; 3266 break; 3267 } 3268 txq->ift_map_failed++; 3269 DBG_COUNTER_INC(encap_load_mbuf_fail); 3270 DBG_COUNTER_INC(encap_txd_encap_fail); 3271 return (err); 3272 } 3273 ifsd_m[pidx] = m_head; 3274 /* 3275 * XXX assumes a 1 to 1 relationship between segments and 3276 * descriptors - this does not hold true on all drivers, e.g. 3277 * cxgb 3278 */ 3279 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3280 txq->ift_no_desc_avail++; 3281 bus_dmamap_unload(desc_tag, map); 3282 DBG_COUNTER_INC(encap_txq_avail_fail); 3283 DBG_COUNTER_INC(encap_txd_encap_fail); 3284 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3285 GROUPTASK_ENQUEUE(&txq->ift_task); 3286 return (ENOBUFS); 3287 } 3288 /* 3289 * On Intel cards we can greatly reduce the number of TX interrupts 3290 * we see by only setting report status on every Nth descriptor. 3291 * However, this also means that the driver will need to keep track 3292 * of the descriptors that RS was set on to check them for the DD bit. 3293 */ 3294 txq->ift_rs_pending += nsegs + 1; 3295 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3296 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3297 pi.ipi_flags |= IPI_TX_INTR; 3298 txq->ift_rs_pending = 0; 3299 } 3300 3301 pi.ipi_segs = segs; 3302 pi.ipi_nsegs = nsegs; 3303 3304 MPASS(pidx >= 0 && pidx < txq->ift_size); 3305 #ifdef PKT_DEBUG 3306 print_pkt(&pi); 3307 #endif 3308 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3309 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3310 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3311 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3312 DBG_COUNTER_INC(tx_encap); 3313 MPASS(pi.ipi_new_pidx < txq->ift_size); 3314 3315 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3316 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3317 ndesc += txq->ift_size; 3318 txq->ift_gen = 1; 3319 } 3320 /* 3321 * drivers can need as many as 3322 * two sentinels 3323 */ 3324 MPASS(ndesc <= pi.ipi_nsegs + 2); 3325 MPASS(pi.ipi_new_pidx != pidx); 3326 MPASS(ndesc > 0); 3327 txq->ift_in_use += ndesc; 3328 3329 /* 3330 * We update the last software descriptor again here because there may 3331 * be a sentinel and/or there may be more mbufs than segments 3332 */ 3333 txq->ift_pidx = pi.ipi_new_pidx; 3334 txq->ift_npending += pi.ipi_ndescs; 3335 } else { 3336 *m_headp = m_head = iflib_remove_mbuf(txq); 3337 if (err == EFBIG) { 3338 txq->ift_txd_encap_efbig++; 3339 if (remap < 2) { 3340 remap = 1; 3341 goto defrag; 3342 } 3343 } 3344 goto defrag_failed; 3345 } 3346 /* 3347 * err can't possibly be non-zero here, so we don't neet to test it 3348 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3349 */ 3350 return (err); 3351 3352 defrag_failed: 3353 txq->ift_mbuf_defrag_failed++; 3354 txq->ift_map_failed++; 3355 m_freem(*m_headp); 3356 DBG_COUNTER_INC(tx_frees); 3357 *m_headp = NULL; 3358 DBG_COUNTER_INC(encap_txd_encap_fail); 3359 return (ENOMEM); 3360 } 3361 3362 static void 3363 iflib_tx_desc_free(iflib_txq_t txq, int n) 3364 { 3365 uint32_t qsize, cidx, mask, gen; 3366 struct mbuf *m, **ifsd_m; 3367 bool do_prefetch; 3368 3369 cidx = txq->ift_cidx; 3370 gen = txq->ift_gen; 3371 qsize = txq->ift_size; 3372 mask = qsize-1; 3373 ifsd_m = txq->ift_sds.ifsd_m; 3374 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3375 3376 while (n-- > 0) { 3377 if (do_prefetch) { 3378 prefetch(ifsd_m[(cidx + 3) & mask]); 3379 prefetch(ifsd_m[(cidx + 4) & mask]); 3380 } 3381 if ((m = ifsd_m[cidx]) != NULL) { 3382 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3383 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3384 bus_dmamap_sync(txq->ift_tso_desc_tag, 3385 txq->ift_sds.ifsd_tso_map[cidx], 3386 BUS_DMASYNC_POSTWRITE); 3387 bus_dmamap_unload(txq->ift_tso_desc_tag, 3388 txq->ift_sds.ifsd_tso_map[cidx]); 3389 } else { 3390 bus_dmamap_sync(txq->ift_desc_tag, 3391 txq->ift_sds.ifsd_map[cidx], 3392 BUS_DMASYNC_POSTWRITE); 3393 bus_dmamap_unload(txq->ift_desc_tag, 3394 txq->ift_sds.ifsd_map[cidx]); 3395 } 3396 /* XXX we don't support any drivers that batch packets yet */ 3397 MPASS(m->m_nextpkt == NULL); 3398 m_freem(m); 3399 ifsd_m[cidx] = NULL; 3400 #if MEMORY_LOGGING 3401 txq->ift_dequeued++; 3402 #endif 3403 DBG_COUNTER_INC(tx_frees); 3404 } 3405 if (__predict_false(++cidx == qsize)) { 3406 cidx = 0; 3407 gen = 0; 3408 } 3409 } 3410 txq->ift_cidx = cidx; 3411 txq->ift_gen = gen; 3412 } 3413 3414 static __inline int 3415 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3416 { 3417 int reclaim; 3418 if_ctx_t ctx = txq->ift_ctx; 3419 3420 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3421 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3422 3423 /* 3424 * Need a rate-limiting check so that this isn't called every time 3425 */ 3426 iflib_tx_credits_update(ctx, txq); 3427 reclaim = DESC_RECLAIMABLE(txq); 3428 3429 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3430 #ifdef INVARIANTS 3431 if (iflib_verbose_debug) { 3432 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3433 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3434 reclaim, thresh); 3435 3436 } 3437 #endif 3438 return (0); 3439 } 3440 iflib_tx_desc_free(txq, reclaim); 3441 txq->ift_cleaned += reclaim; 3442 txq->ift_in_use -= reclaim; 3443 3444 return (reclaim); 3445 } 3446 3447 static struct mbuf ** 3448 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3449 { 3450 int next, size; 3451 struct mbuf **items; 3452 3453 size = r->size; 3454 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3455 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3456 3457 prefetch(items[(cidx + offset) & (size-1)]); 3458 if (remaining > 1) { 3459 prefetch2cachelines(&items[next]); 3460 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3461 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3462 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3463 } 3464 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3465 } 3466 3467 static void 3468 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3469 { 3470 3471 ifmp_ring_check_drainage(txq->ift_br, budget); 3472 } 3473 3474 static uint32_t 3475 iflib_txq_can_drain(struct ifmp_ring *r) 3476 { 3477 iflib_txq_t txq = r->cookie; 3478 if_ctx_t ctx = txq->ift_ctx; 3479 3480 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3481 BUS_DMASYNC_POSTREAD); 3482 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3483 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3484 } 3485 3486 static uint32_t 3487 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3488 { 3489 iflib_txq_t txq = r->cookie; 3490 if_ctx_t ctx = txq->ift_ctx; 3491 struct ifnet *ifp = ctx->ifc_ifp; 3492 struct mbuf **mp, *m; 3493 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3494 int reclaimed, err, in_use_prev, desc_used; 3495 bool do_prefetch, ring, rang; 3496 3497 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3498 !LINK_ACTIVE(ctx))) { 3499 DBG_COUNTER_INC(txq_drain_notready); 3500 return (0); 3501 } 3502 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3503 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3504 avail = IDXDIFF(pidx, cidx, r->size); 3505 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3506 DBG_COUNTER_INC(txq_drain_flushing); 3507 for (i = 0; i < avail; i++) { 3508 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3509 m_free(r->items[(cidx + i) & (r->size-1)]); 3510 r->items[(cidx + i) & (r->size-1)] = NULL; 3511 } 3512 return (avail); 3513 } 3514 3515 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3516 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3517 CALLOUT_LOCK(txq); 3518 callout_stop(&txq->ift_timer); 3519 CALLOUT_UNLOCK(txq); 3520 DBG_COUNTER_INC(txq_drain_oactive); 3521 return (0); 3522 } 3523 if (reclaimed) 3524 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3525 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3526 count = MIN(avail, TX_BATCH_SIZE); 3527 #ifdef INVARIANTS 3528 if (iflib_verbose_debug) 3529 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3530 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3531 #endif 3532 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3533 avail = TXQ_AVAIL(txq); 3534 err = 0; 3535 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3536 int rem = do_prefetch ? count - i : 0; 3537 3538 mp = _ring_peek_one(r, cidx, i, rem); 3539 MPASS(mp != NULL && *mp != NULL); 3540 if (__predict_false(*mp == (struct mbuf *)txq)) { 3541 consumed++; 3542 reclaimed++; 3543 continue; 3544 } 3545 in_use_prev = txq->ift_in_use; 3546 err = iflib_encap(txq, mp); 3547 if (__predict_false(err)) { 3548 /* no room - bail out */ 3549 if (err == ENOBUFS) 3550 break; 3551 consumed++; 3552 /* we can't send this packet - skip it */ 3553 continue; 3554 } 3555 consumed++; 3556 pkt_sent++; 3557 m = *mp; 3558 DBG_COUNTER_INC(tx_sent); 3559 bytes_sent += m->m_pkthdr.len; 3560 mcast_sent += !!(m->m_flags & M_MCAST); 3561 avail = TXQ_AVAIL(txq); 3562 3563 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3564 desc_used += (txq->ift_in_use - in_use_prev); 3565 ETHER_BPF_MTAP(ifp, m); 3566 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3567 break; 3568 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3569 } 3570 3571 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3572 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3573 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3574 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3575 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3576 if (mcast_sent) 3577 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3578 #ifdef INVARIANTS 3579 if (iflib_verbose_debug) 3580 printf("consumed=%d\n", consumed); 3581 #endif 3582 return (consumed); 3583 } 3584 3585 static uint32_t 3586 iflib_txq_drain_always(struct ifmp_ring *r) 3587 { 3588 return (1); 3589 } 3590 3591 static uint32_t 3592 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3593 { 3594 int i, avail; 3595 struct mbuf **mp; 3596 iflib_txq_t txq; 3597 3598 txq = r->cookie; 3599 3600 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3601 CALLOUT_LOCK(txq); 3602 callout_stop(&txq->ift_timer); 3603 CALLOUT_UNLOCK(txq); 3604 3605 avail = IDXDIFF(pidx, cidx, r->size); 3606 for (i = 0; i < avail; i++) { 3607 mp = _ring_peek_one(r, cidx, i, avail - i); 3608 if (__predict_false(*mp == (struct mbuf *)txq)) 3609 continue; 3610 m_freem(*mp); 3611 DBG_COUNTER_INC(tx_frees); 3612 } 3613 MPASS(ifmp_ring_is_stalled(r) == 0); 3614 return (avail); 3615 } 3616 3617 static void 3618 iflib_ifmp_purge(iflib_txq_t txq) 3619 { 3620 struct ifmp_ring *r; 3621 3622 r = txq->ift_br; 3623 r->drain = iflib_txq_drain_free; 3624 r->can_drain = iflib_txq_drain_always; 3625 3626 ifmp_ring_check_drainage(r, r->size); 3627 3628 r->drain = iflib_txq_drain; 3629 r->can_drain = iflib_txq_can_drain; 3630 } 3631 3632 static void 3633 _task_fn_tx(void *context) 3634 { 3635 iflib_txq_t txq = context; 3636 if_ctx_t ctx = txq->ift_ctx; 3637 struct ifnet *ifp = ctx->ifc_ifp; 3638 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3639 3640 #ifdef IFLIB_DIAGNOSTICS 3641 txq->ift_cpu_exec_count[curcpu]++; 3642 #endif 3643 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3644 return; 3645 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3646 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3647 BUS_DMASYNC_POSTREAD); 3648 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3649 netmap_tx_irq(ifp, txq->ift_id); 3650 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3651 return; 3652 } 3653 #ifdef ALTQ 3654 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3655 iflib_altq_if_start(ifp); 3656 #endif 3657 if (txq->ift_db_pending) 3658 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3659 else if (!abdicate) 3660 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3661 /* 3662 * When abdicating, we always need to check drainage, not just when we don't enqueue 3663 */ 3664 if (abdicate) 3665 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3666 if (ctx->ifc_flags & IFC_LEGACY) 3667 IFDI_INTR_ENABLE(ctx); 3668 else { 3669 #ifdef INVARIANTS 3670 int rc = 3671 #endif 3672 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3673 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3674 } 3675 } 3676 3677 static void 3678 _task_fn_rx(void *context) 3679 { 3680 iflib_rxq_t rxq = context; 3681 if_ctx_t ctx = rxq->ifr_ctx; 3682 bool more; 3683 uint16_t budget; 3684 3685 #ifdef IFLIB_DIAGNOSTICS 3686 rxq->ifr_cpu_exec_count[curcpu]++; 3687 #endif 3688 DBG_COUNTER_INC(task_fn_rxs); 3689 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3690 return; 3691 more = true; 3692 #ifdef DEV_NETMAP 3693 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3694 u_int work = 0; 3695 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3696 more = false; 3697 } 3698 } 3699 #endif 3700 budget = ctx->ifc_sysctl_rx_budget; 3701 if (budget == 0) 3702 budget = 16; /* XXX */ 3703 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3704 if (ctx->ifc_flags & IFC_LEGACY) 3705 IFDI_INTR_ENABLE(ctx); 3706 else { 3707 #ifdef INVARIANTS 3708 int rc = 3709 #endif 3710 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3711 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3712 DBG_COUNTER_INC(rx_intr_enables); 3713 } 3714 } 3715 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3716 return; 3717 if (more) 3718 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3719 } 3720 3721 static void 3722 _task_fn_admin(void *context) 3723 { 3724 if_ctx_t ctx = context; 3725 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3726 iflib_txq_t txq; 3727 int i; 3728 bool oactive, running, do_reset, do_watchdog, in_detach; 3729 uint32_t reset_on = hz / 2; 3730 3731 STATE_LOCK(ctx); 3732 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3733 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3734 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3735 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3736 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3737 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3738 STATE_UNLOCK(ctx); 3739 3740 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3741 return; 3742 if (in_detach) 3743 return; 3744 3745 CTX_LOCK(ctx); 3746 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3747 CALLOUT_LOCK(txq); 3748 callout_stop(&txq->ift_timer); 3749 CALLOUT_UNLOCK(txq); 3750 } 3751 if (do_watchdog) { 3752 ctx->ifc_watchdog_events++; 3753 IFDI_WATCHDOG_RESET(ctx); 3754 } 3755 IFDI_UPDATE_ADMIN_STATUS(ctx); 3756 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3757 #ifdef DEV_NETMAP 3758 reset_on = hz / 2; 3759 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3760 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on); 3761 #endif 3762 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3763 } 3764 IFDI_LINK_INTR_ENABLE(ctx); 3765 if (do_reset) 3766 iflib_if_init_locked(ctx); 3767 CTX_UNLOCK(ctx); 3768 3769 if (LINK_ACTIVE(ctx) == 0) 3770 return; 3771 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3772 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3773 } 3774 3775 3776 static void 3777 _task_fn_iov(void *context) 3778 { 3779 if_ctx_t ctx = context; 3780 3781 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3782 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3783 return; 3784 3785 CTX_LOCK(ctx); 3786 IFDI_VFLR_HANDLE(ctx); 3787 CTX_UNLOCK(ctx); 3788 } 3789 3790 static int 3791 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3792 { 3793 int err; 3794 if_int_delay_info_t info; 3795 if_ctx_t ctx; 3796 3797 info = (if_int_delay_info_t)arg1; 3798 ctx = info->iidi_ctx; 3799 info->iidi_req = req; 3800 info->iidi_oidp = oidp; 3801 CTX_LOCK(ctx); 3802 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3803 CTX_UNLOCK(ctx); 3804 return (err); 3805 } 3806 3807 /********************************************************************* 3808 * 3809 * IFNET FUNCTIONS 3810 * 3811 **********************************************************************/ 3812 3813 static void 3814 iflib_if_init_locked(if_ctx_t ctx) 3815 { 3816 iflib_stop(ctx); 3817 iflib_init_locked(ctx); 3818 } 3819 3820 3821 static void 3822 iflib_if_init(void *arg) 3823 { 3824 if_ctx_t ctx = arg; 3825 3826 CTX_LOCK(ctx); 3827 iflib_if_init_locked(ctx); 3828 CTX_UNLOCK(ctx); 3829 } 3830 3831 static int 3832 iflib_if_transmit(if_t ifp, struct mbuf *m) 3833 { 3834 if_ctx_t ctx = if_getsoftc(ifp); 3835 3836 iflib_txq_t txq; 3837 int err, qidx; 3838 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3839 3840 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3841 DBG_COUNTER_INC(tx_frees); 3842 m_freem(m); 3843 return (ENOBUFS); 3844 } 3845 3846 MPASS(m->m_nextpkt == NULL); 3847 /* ALTQ-enabled interfaces always use queue 0. */ 3848 qidx = 0; 3849 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3850 qidx = QIDX(ctx, m); 3851 /* 3852 * XXX calculate buf_ring based on flowid (divvy up bits?) 3853 */ 3854 txq = &ctx->ifc_txqs[qidx]; 3855 3856 #ifdef DRIVER_BACKPRESSURE 3857 if (txq->ift_closed) { 3858 while (m != NULL) { 3859 next = m->m_nextpkt; 3860 m->m_nextpkt = NULL; 3861 m_freem(m); 3862 DBG_COUNTER_INC(tx_frees); 3863 m = next; 3864 } 3865 return (ENOBUFS); 3866 } 3867 #endif 3868 #ifdef notyet 3869 qidx = count = 0; 3870 mp = marr; 3871 next = m; 3872 do { 3873 count++; 3874 next = next->m_nextpkt; 3875 } while (next != NULL); 3876 3877 if (count > nitems(marr)) 3878 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3879 /* XXX check nextpkt */ 3880 m_freem(m); 3881 /* XXX simplify for now */ 3882 DBG_COUNTER_INC(tx_frees); 3883 return (ENOBUFS); 3884 } 3885 for (next = m, i = 0; next != NULL; i++) { 3886 mp[i] = next; 3887 next = next->m_nextpkt; 3888 mp[i]->m_nextpkt = NULL; 3889 } 3890 #endif 3891 DBG_COUNTER_INC(tx_seen); 3892 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 3893 3894 if (abdicate) 3895 GROUPTASK_ENQUEUE(&txq->ift_task); 3896 if (err) { 3897 if (!abdicate) 3898 GROUPTASK_ENQUEUE(&txq->ift_task); 3899 /* support forthcoming later */ 3900 #ifdef DRIVER_BACKPRESSURE 3901 txq->ift_closed = TRUE; 3902 #endif 3903 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3904 m_freem(m); 3905 DBG_COUNTER_INC(tx_frees); 3906 } 3907 3908 return (err); 3909 } 3910 3911 #ifdef ALTQ 3912 /* 3913 * The overall approach to integrating iflib with ALTQ is to continue to use 3914 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 3915 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 3916 * is redundant/unnecessary, but doing so minimizes the amount of 3917 * ALTQ-specific code required in iflib. It is assumed that the overhead of 3918 * redundantly queueing to an intermediate mp_ring is swamped by the 3919 * performance limitations inherent in using ALTQ. 3920 * 3921 * When ALTQ support is compiled in, all iflib drivers will use a transmit 3922 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 3923 * given interface. If ALTQ is enabled for an interface, then all 3924 * transmitted packets for that interface will be submitted to the ALTQ 3925 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 3926 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 3927 * update stats that the iflib machinery handles, and which is sensitve to 3928 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 3929 * will be installed as the start routine for use by ALTQ facilities that 3930 * need to trigger queue drains on a scheduled basis. 3931 * 3932 */ 3933 static void 3934 iflib_altq_if_start(if_t ifp) 3935 { 3936 struct ifaltq *ifq = &ifp->if_snd; 3937 struct mbuf *m; 3938 3939 IFQ_LOCK(ifq); 3940 IFQ_DEQUEUE_NOLOCK(ifq, m); 3941 while (m != NULL) { 3942 iflib_if_transmit(ifp, m); 3943 IFQ_DEQUEUE_NOLOCK(ifq, m); 3944 } 3945 IFQ_UNLOCK(ifq); 3946 } 3947 3948 static int 3949 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 3950 { 3951 int err; 3952 3953 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 3954 IFQ_ENQUEUE(&ifp->if_snd, m, err); 3955 if (err == 0) 3956 iflib_altq_if_start(ifp); 3957 } else 3958 err = iflib_if_transmit(ifp, m); 3959 3960 return (err); 3961 } 3962 #endif /* ALTQ */ 3963 3964 static void 3965 iflib_if_qflush(if_t ifp) 3966 { 3967 if_ctx_t ctx = if_getsoftc(ifp); 3968 iflib_txq_t txq = ctx->ifc_txqs; 3969 int i; 3970 3971 STATE_LOCK(ctx); 3972 ctx->ifc_flags |= IFC_QFLUSH; 3973 STATE_UNLOCK(ctx); 3974 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3975 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3976 iflib_txq_check_drain(txq, 0); 3977 STATE_LOCK(ctx); 3978 ctx->ifc_flags &= ~IFC_QFLUSH; 3979 STATE_UNLOCK(ctx); 3980 3981 /* 3982 * When ALTQ is enabled, this will also take care of purging the 3983 * ALTQ queue(s). 3984 */ 3985 if_qflush(ifp); 3986 } 3987 3988 3989 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3990 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 3991 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 3992 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM) 3993 3994 static int 3995 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 3996 { 3997 if_ctx_t ctx = if_getsoftc(ifp); 3998 struct ifreq *ifr = (struct ifreq *)data; 3999 #if defined(INET) || defined(INET6) 4000 struct ifaddr *ifa = (struct ifaddr *)data; 4001 #endif 4002 bool avoid_reset = FALSE; 4003 int err = 0, reinit = 0, bits; 4004 4005 switch (command) { 4006 case SIOCSIFADDR: 4007 #ifdef INET 4008 if (ifa->ifa_addr->sa_family == AF_INET) 4009 avoid_reset = TRUE; 4010 #endif 4011 #ifdef INET6 4012 if (ifa->ifa_addr->sa_family == AF_INET6) 4013 avoid_reset = TRUE; 4014 #endif 4015 /* 4016 ** Calling init results in link renegotiation, 4017 ** so we avoid doing it when possible. 4018 */ 4019 if (avoid_reset) { 4020 if_setflagbits(ifp, IFF_UP,0); 4021 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4022 reinit = 1; 4023 #ifdef INET 4024 if (!(if_getflags(ifp) & IFF_NOARP)) 4025 arp_ifinit(ifp, ifa); 4026 #endif 4027 } else 4028 err = ether_ioctl(ifp, command, data); 4029 break; 4030 case SIOCSIFMTU: 4031 CTX_LOCK(ctx); 4032 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4033 CTX_UNLOCK(ctx); 4034 break; 4035 } 4036 bits = if_getdrvflags(ifp); 4037 /* stop the driver and free any clusters before proceeding */ 4038 iflib_stop(ctx); 4039 4040 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4041 STATE_LOCK(ctx); 4042 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4043 ctx->ifc_flags |= IFC_MULTISEG; 4044 else 4045 ctx->ifc_flags &= ~IFC_MULTISEG; 4046 STATE_UNLOCK(ctx); 4047 err = if_setmtu(ifp, ifr->ifr_mtu); 4048 } 4049 iflib_init_locked(ctx); 4050 STATE_LOCK(ctx); 4051 if_setdrvflags(ifp, bits); 4052 STATE_UNLOCK(ctx); 4053 CTX_UNLOCK(ctx); 4054 break; 4055 case SIOCSIFFLAGS: 4056 CTX_LOCK(ctx); 4057 if (if_getflags(ifp) & IFF_UP) { 4058 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4059 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4060 (IFF_PROMISC | IFF_ALLMULTI)) { 4061 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4062 } 4063 } else 4064 reinit = 1; 4065 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4066 iflib_stop(ctx); 4067 } 4068 ctx->ifc_if_flags = if_getflags(ifp); 4069 CTX_UNLOCK(ctx); 4070 break; 4071 case SIOCADDMULTI: 4072 case SIOCDELMULTI: 4073 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4074 CTX_LOCK(ctx); 4075 IFDI_INTR_DISABLE(ctx); 4076 IFDI_MULTI_SET(ctx); 4077 IFDI_INTR_ENABLE(ctx); 4078 CTX_UNLOCK(ctx); 4079 } 4080 break; 4081 case SIOCSIFMEDIA: 4082 CTX_LOCK(ctx); 4083 IFDI_MEDIA_SET(ctx); 4084 CTX_UNLOCK(ctx); 4085 /* falls thru */ 4086 case SIOCGIFMEDIA: 4087 case SIOCGIFXMEDIA: 4088 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 4089 break; 4090 case SIOCGI2C: 4091 { 4092 struct ifi2creq i2c; 4093 4094 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4095 if (err != 0) 4096 break; 4097 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4098 err = EINVAL; 4099 break; 4100 } 4101 if (i2c.len > sizeof(i2c.data)) { 4102 err = EINVAL; 4103 break; 4104 } 4105 4106 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4107 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4108 sizeof(i2c)); 4109 break; 4110 } 4111 case SIOCSIFCAP: 4112 { 4113 int mask, setmask, oldmask; 4114 4115 oldmask = if_getcapenable(ifp); 4116 mask = ifr->ifr_reqcap ^ oldmask; 4117 mask &= ctx->ifc_softc_ctx.isc_capabilities; 4118 setmask = 0; 4119 #ifdef TCP_OFFLOAD 4120 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4121 #endif 4122 setmask |= (mask & IFCAP_FLAGS); 4123 setmask |= (mask & IFCAP_WOL); 4124 4125 /* 4126 * If any RX csum has changed, change all the ones that 4127 * are supported by the driver. 4128 */ 4129 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4130 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4131 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4132 } 4133 4134 /* 4135 * want to ensure that traffic has stopped before we change any of the flags 4136 */ 4137 if (setmask) { 4138 CTX_LOCK(ctx); 4139 bits = if_getdrvflags(ifp); 4140 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4141 iflib_stop(ctx); 4142 STATE_LOCK(ctx); 4143 if_togglecapenable(ifp, setmask); 4144 STATE_UNLOCK(ctx); 4145 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4146 iflib_init_locked(ctx); 4147 STATE_LOCK(ctx); 4148 if_setdrvflags(ifp, bits); 4149 STATE_UNLOCK(ctx); 4150 CTX_UNLOCK(ctx); 4151 } 4152 if_vlancap(ifp); 4153 break; 4154 } 4155 case SIOCGPRIVATE_0: 4156 case SIOCSDRVSPEC: 4157 case SIOCGDRVSPEC: 4158 CTX_LOCK(ctx); 4159 err = IFDI_PRIV_IOCTL(ctx, command, data); 4160 CTX_UNLOCK(ctx); 4161 break; 4162 default: 4163 err = ether_ioctl(ifp, command, data); 4164 break; 4165 } 4166 if (reinit) 4167 iflib_if_init(ctx); 4168 return (err); 4169 } 4170 4171 static uint64_t 4172 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4173 { 4174 if_ctx_t ctx = if_getsoftc(ifp); 4175 4176 return (IFDI_GET_COUNTER(ctx, cnt)); 4177 } 4178 4179 /********************************************************************* 4180 * 4181 * OTHER FUNCTIONS EXPORTED TO THE STACK 4182 * 4183 **********************************************************************/ 4184 4185 static void 4186 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4187 { 4188 if_ctx_t ctx = if_getsoftc(ifp); 4189 4190 if ((void *)ctx != arg) 4191 return; 4192 4193 if ((vtag == 0) || (vtag > 4095)) 4194 return; 4195 4196 CTX_LOCK(ctx); 4197 IFDI_VLAN_REGISTER(ctx, vtag); 4198 /* Re-init to load the changes */ 4199 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4200 iflib_if_init_locked(ctx); 4201 CTX_UNLOCK(ctx); 4202 } 4203 4204 static void 4205 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4206 { 4207 if_ctx_t ctx = if_getsoftc(ifp); 4208 4209 if ((void *)ctx != arg) 4210 return; 4211 4212 if ((vtag == 0) || (vtag > 4095)) 4213 return; 4214 4215 CTX_LOCK(ctx); 4216 IFDI_VLAN_UNREGISTER(ctx, vtag); 4217 /* Re-init to load the changes */ 4218 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4219 iflib_if_init_locked(ctx); 4220 CTX_UNLOCK(ctx); 4221 } 4222 4223 static void 4224 iflib_led_func(void *arg, int onoff) 4225 { 4226 if_ctx_t ctx = arg; 4227 4228 CTX_LOCK(ctx); 4229 IFDI_LED_FUNC(ctx, onoff); 4230 CTX_UNLOCK(ctx); 4231 } 4232 4233 /********************************************************************* 4234 * 4235 * BUS FUNCTION DEFINITIONS 4236 * 4237 **********************************************************************/ 4238 4239 int 4240 iflib_device_probe(device_t dev) 4241 { 4242 pci_vendor_info_t *ent; 4243 4244 uint16_t pci_vendor_id, pci_device_id; 4245 uint16_t pci_subvendor_id, pci_subdevice_id; 4246 uint16_t pci_rev_id; 4247 if_shared_ctx_t sctx; 4248 4249 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4250 return (ENOTSUP); 4251 4252 pci_vendor_id = pci_get_vendor(dev); 4253 pci_device_id = pci_get_device(dev); 4254 pci_subvendor_id = pci_get_subvendor(dev); 4255 pci_subdevice_id = pci_get_subdevice(dev); 4256 pci_rev_id = pci_get_revid(dev); 4257 if (sctx->isc_parse_devinfo != NULL) 4258 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4259 4260 ent = sctx->isc_vendor_info; 4261 while (ent->pvi_vendor_id != 0) { 4262 if (pci_vendor_id != ent->pvi_vendor_id) { 4263 ent++; 4264 continue; 4265 } 4266 if ((pci_device_id == ent->pvi_device_id) && 4267 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4268 (ent->pvi_subvendor_id == 0)) && 4269 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4270 (ent->pvi_subdevice_id == 0)) && 4271 ((pci_rev_id == ent->pvi_rev_id) || 4272 (ent->pvi_rev_id == 0))) { 4273 4274 device_set_desc_copy(dev, ent->pvi_name); 4275 /* this needs to be changed to zero if the bus probing code 4276 * ever stops re-probing on best match because the sctx 4277 * may have its values over written by register calls 4278 * in subsequent probes 4279 */ 4280 return (BUS_PROBE_DEFAULT); 4281 } 4282 ent++; 4283 } 4284 return (ENXIO); 4285 } 4286 4287 static void 4288 iflib_reset_qvalues(if_ctx_t ctx) 4289 { 4290 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4291 if_shared_ctx_t sctx = ctx->ifc_sctx; 4292 device_t dev = ctx->ifc_dev; 4293 int i; 4294 4295 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES; 4296 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH; 4297 /* 4298 * XXX sanity check that ntxd & nrxd are a power of 2 4299 */ 4300 if (ctx->ifc_sysctl_ntxqs != 0) 4301 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4302 if (ctx->ifc_sysctl_nrxqs != 0) 4303 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4304 4305 for (i = 0; i < sctx->isc_ntxqs; i++) { 4306 if (ctx->ifc_sysctl_ntxds[i] != 0) 4307 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4308 else 4309 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4310 } 4311 4312 for (i = 0; i < sctx->isc_nrxqs; i++) { 4313 if (ctx->ifc_sysctl_nrxds[i] != 0) 4314 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4315 else 4316 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4317 } 4318 4319 for (i = 0; i < sctx->isc_nrxqs; i++) { 4320 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4321 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4322 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4323 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4324 } 4325 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4326 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4327 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4328 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4329 } 4330 } 4331 4332 for (i = 0; i < sctx->isc_ntxqs; i++) { 4333 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4334 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4335 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4336 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4337 } 4338 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4339 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4340 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4341 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4342 } 4343 } 4344 } 4345 4346 int 4347 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4348 { 4349 int err, rid, msix; 4350 if_ctx_t ctx; 4351 if_t ifp; 4352 if_softc_ctx_t scctx; 4353 int i; 4354 uint16_t main_txq; 4355 uint16_t main_rxq; 4356 4357 4358 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4359 4360 if (sc == NULL) { 4361 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4362 device_set_softc(dev, ctx); 4363 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4364 } 4365 4366 ctx->ifc_sctx = sctx; 4367 ctx->ifc_dev = dev; 4368 ctx->ifc_softc = sc; 4369 4370 if ((err = iflib_register(ctx)) != 0) { 4371 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4372 free(sc, M_IFLIB); 4373 free(ctx, M_IFLIB); 4374 device_printf(dev, "iflib_register failed %d\n", err); 4375 return (err); 4376 } 4377 iflib_add_device_sysctl_pre(ctx); 4378 4379 scctx = &ctx->ifc_softc_ctx; 4380 ifp = ctx->ifc_ifp; 4381 4382 iflib_reset_qvalues(ctx); 4383 CTX_LOCK(ctx); 4384 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4385 CTX_UNLOCK(ctx); 4386 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4387 return (err); 4388 } 4389 _iflib_pre_assert(scctx); 4390 ctx->ifc_txrx = *scctx->isc_txrx; 4391 4392 #ifdef INVARIANTS 4393 MPASS(scctx->isc_capabilities); 4394 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4395 MPASS(scctx->isc_tx_csum_flags); 4396 #endif 4397 4398 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS); 4399 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4400 4401 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4402 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4403 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4404 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4405 4406 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4407 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4408 4409 /* XXX change for per-queue sizes */ 4410 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4411 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4412 for (i = 0; i < sctx->isc_nrxqs; i++) { 4413 if (!powerof2(scctx->isc_nrxd[i])) { 4414 /* round down instead? */ 4415 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4416 err = EINVAL; 4417 goto fail; 4418 } 4419 } 4420 for (i = 0; i < sctx->isc_ntxqs; i++) { 4421 if (!powerof2(scctx->isc_ntxd[i])) { 4422 device_printf(dev, 4423 "# tx descriptors must be a power of 2"); 4424 err = EINVAL; 4425 goto fail; 4426 } 4427 } 4428 4429 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4430 MAX_SINGLE_PACKET_FRACTION) 4431 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4432 MAX_SINGLE_PACKET_FRACTION); 4433 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4434 MAX_SINGLE_PACKET_FRACTION) 4435 scctx->isc_tx_tso_segments_max = max(1, 4436 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4437 4438 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4439 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4440 /* 4441 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4442 * but some MACs do. 4443 */ 4444 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4445 IP_MAXPACKET)); 4446 /* 4447 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4448 * into account. In the worst case, each of these calls will 4449 * add another mbuf and, thus, the requirement for another DMA 4450 * segment. So for best performance, it doesn't make sense to 4451 * advertize a maximum of TSO segments that typically will 4452 * require defragmentation in iflib_encap(). 4453 */ 4454 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4455 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4456 } 4457 if (scctx->isc_rss_table_size == 0) 4458 scctx->isc_rss_table_size = 64; 4459 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4460 4461 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4462 /* XXX format name */ 4463 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4464 4465 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4466 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4467 device_printf(dev, "Unable to fetch CPU list\n"); 4468 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4469 } 4470 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4471 4472 /* 4473 ** Now setup MSI or MSI/X, should 4474 ** return us the number of supported 4475 ** vectors. (Will be 1 for MSI) 4476 */ 4477 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4478 msix = scctx->isc_vectors; 4479 } else if (scctx->isc_msix_bar != 0) 4480 /* 4481 * The simple fact that isc_msix_bar is not 0 does not mean we 4482 * we have a good value there that is known to work. 4483 */ 4484 msix = iflib_msix_init(ctx); 4485 else { 4486 scctx->isc_vectors = 1; 4487 scctx->isc_ntxqsets = 1; 4488 scctx->isc_nrxqsets = 1; 4489 scctx->isc_intr = IFLIB_INTR_LEGACY; 4490 msix = 0; 4491 } 4492 /* Get memory for the station queues */ 4493 if ((err = iflib_queues_alloc(ctx))) { 4494 device_printf(dev, "Unable to allocate queue memory\n"); 4495 goto fail; 4496 } 4497 4498 if ((err = iflib_qset_structures_setup(ctx))) 4499 goto fail_queues; 4500 4501 /* 4502 * Group taskqueues aren't properly set up until SMP is started, 4503 * so we disable interrupts until we can handle them post 4504 * SI_SUB_SMP. 4505 * 4506 * XXX: disabling interrupts doesn't actually work, at least for 4507 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4508 * we do null handling and depend on this not causing too large an 4509 * interrupt storm. 4510 */ 4511 IFDI_INTR_DISABLE(ctx); 4512 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4513 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4514 goto fail_intr_free; 4515 } 4516 if (msix <= 1) { 4517 rid = 0; 4518 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4519 MPASS(msix == 1); 4520 rid = 1; 4521 } 4522 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4523 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4524 goto fail_intr_free; 4525 } 4526 } 4527 4528 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4529 4530 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4531 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4532 goto fail_detach; 4533 } 4534 4535 /* 4536 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4537 * This must appear after the call to ether_ifattach() because 4538 * ether_ifattach() sets if_hdrlen to the default value. 4539 */ 4540 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4541 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4542 4543 if ((err = iflib_netmap_attach(ctx))) { 4544 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4545 goto fail_detach; 4546 } 4547 *ctxp = ctx; 4548 4549 NETDUMP_SET(ctx->ifc_ifp, iflib); 4550 4551 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4552 iflib_add_device_sysctl_post(ctx); 4553 ctx->ifc_flags |= IFC_INIT_DONE; 4554 CTX_UNLOCK(ctx); 4555 return (0); 4556 4557 fail_detach: 4558 ether_ifdetach(ctx->ifc_ifp); 4559 fail_intr_free: 4560 fail_queues: 4561 iflib_tx_structures_free(ctx); 4562 iflib_rx_structures_free(ctx); 4563 fail: 4564 iflib_free_intr_mem(ctx); 4565 IFDI_DETACH(ctx); 4566 CTX_UNLOCK(ctx); 4567 4568 return (err); 4569 } 4570 4571 int 4572 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4573 struct iflib_cloneattach_ctx *clctx) 4574 { 4575 int err; 4576 if_ctx_t ctx; 4577 if_t ifp; 4578 if_softc_ctx_t scctx; 4579 int i; 4580 void *sc; 4581 uint16_t main_txq; 4582 uint16_t main_rxq; 4583 4584 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4585 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4586 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4587 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4588 ctx->ifc_flags |= IFC_PSEUDO; 4589 4590 ctx->ifc_sctx = sctx; 4591 ctx->ifc_softc = sc; 4592 ctx->ifc_dev = dev; 4593 4594 if ((err = iflib_register(ctx)) != 0) { 4595 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4596 free(sc, M_IFLIB); 4597 free(ctx, M_IFLIB); 4598 return (err); 4599 } 4600 iflib_add_device_sysctl_pre(ctx); 4601 4602 scctx = &ctx->ifc_softc_ctx; 4603 ifp = ctx->ifc_ifp; 4604 4605 /* 4606 * XXX sanity check that ntxd & nrxd are a power of 2 4607 */ 4608 iflib_reset_qvalues(ctx); 4609 4610 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4611 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4612 return (err); 4613 } 4614 if (sctx->isc_flags & IFLIB_GEN_MAC) 4615 iflib_gen_mac(ctx); 4616 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4617 clctx->cc_params)) != 0) { 4618 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4619 return (err); 4620 } 4621 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4622 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 4623 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO); 4624 4625 #ifdef INVARIANTS 4626 MPASS(scctx->isc_capabilities); 4627 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4628 MPASS(scctx->isc_tx_csum_flags); 4629 #endif 4630 4631 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4632 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4633 4634 ifp->if_flags |= IFF_NOGROUP; 4635 if (sctx->isc_flags & IFLIB_PSEUDO) { 4636 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4637 4638 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4639 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4640 goto fail_detach; 4641 } 4642 *ctxp = ctx; 4643 4644 /* 4645 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4646 * This must appear after the call to ether_ifattach() because 4647 * ether_ifattach() sets if_hdrlen to the default value. 4648 */ 4649 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4650 if_setifheaderlen(ifp, 4651 sizeof(struct ether_vlan_header)); 4652 4653 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4654 iflib_add_device_sysctl_post(ctx); 4655 ctx->ifc_flags |= IFC_INIT_DONE; 4656 return (0); 4657 } 4658 _iflib_pre_assert(scctx); 4659 ctx->ifc_txrx = *scctx->isc_txrx; 4660 4661 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4662 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4663 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4664 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4665 4666 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4667 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4668 4669 /* XXX change for per-queue sizes */ 4670 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4671 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4672 for (i = 0; i < sctx->isc_nrxqs; i++) { 4673 if (!powerof2(scctx->isc_nrxd[i])) { 4674 /* round down instead? */ 4675 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4676 err = EINVAL; 4677 goto fail; 4678 } 4679 } 4680 for (i = 0; i < sctx->isc_ntxqs; i++) { 4681 if (!powerof2(scctx->isc_ntxd[i])) { 4682 device_printf(dev, 4683 "# tx descriptors must be a power of 2"); 4684 err = EINVAL; 4685 goto fail; 4686 } 4687 } 4688 4689 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4690 MAX_SINGLE_PACKET_FRACTION) 4691 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4692 MAX_SINGLE_PACKET_FRACTION); 4693 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4694 MAX_SINGLE_PACKET_FRACTION) 4695 scctx->isc_tx_tso_segments_max = max(1, 4696 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4697 4698 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4699 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4700 /* 4701 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4702 * but some MACs do. 4703 */ 4704 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4705 IP_MAXPACKET)); 4706 /* 4707 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4708 * into account. In the worst case, each of these calls will 4709 * add another mbuf and, thus, the requirement for another DMA 4710 * segment. So for best performance, it doesn't make sense to 4711 * advertize a maximum of TSO segments that typically will 4712 * require defragmentation in iflib_encap(). 4713 */ 4714 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4715 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4716 } 4717 if (scctx->isc_rss_table_size == 0) 4718 scctx->isc_rss_table_size = 64; 4719 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4720 4721 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4722 /* XXX format name */ 4723 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4724 4725 /* XXX --- can support > 1 -- but keep it simple for now */ 4726 scctx->isc_intr = IFLIB_INTR_LEGACY; 4727 4728 /* Get memory for the station queues */ 4729 if ((err = iflib_queues_alloc(ctx))) { 4730 device_printf(dev, "Unable to allocate queue memory\n"); 4731 goto fail; 4732 } 4733 4734 if ((err = iflib_qset_structures_setup(ctx))) { 4735 device_printf(dev, "qset structure setup failed %d\n", err); 4736 goto fail_queues; 4737 } 4738 4739 /* 4740 * XXX What if anything do we want to do about interrupts? 4741 */ 4742 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4743 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4744 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4745 goto fail_detach; 4746 } 4747 4748 /* 4749 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4750 * This must appear after the call to ether_ifattach() because 4751 * ether_ifattach() sets if_hdrlen to the default value. 4752 */ 4753 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4754 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4755 4756 /* XXX handle more than one queue */ 4757 for (i = 0; i < scctx->isc_nrxqsets; i++) 4758 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4759 4760 *ctxp = ctx; 4761 4762 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4763 iflib_add_device_sysctl_post(ctx); 4764 ctx->ifc_flags |= IFC_INIT_DONE; 4765 return (0); 4766 fail_detach: 4767 ether_ifdetach(ctx->ifc_ifp); 4768 fail_queues: 4769 iflib_tx_structures_free(ctx); 4770 iflib_rx_structures_free(ctx); 4771 fail: 4772 IFDI_DETACH(ctx); 4773 return (err); 4774 } 4775 4776 int 4777 iflib_pseudo_deregister(if_ctx_t ctx) 4778 { 4779 if_t ifp = ctx->ifc_ifp; 4780 iflib_txq_t txq; 4781 iflib_rxq_t rxq; 4782 int i, j; 4783 struct taskqgroup *tqg; 4784 iflib_fl_t fl; 4785 4786 /* Unregister VLAN events */ 4787 if (ctx->ifc_vlan_attach_event != NULL) 4788 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4789 if (ctx->ifc_vlan_detach_event != NULL) 4790 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4791 4792 ether_ifdetach(ifp); 4793 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4794 CTX_LOCK_DESTROY(ctx); 4795 /* XXX drain any dependent tasks */ 4796 tqg = qgroup_if_io_tqg; 4797 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4798 callout_drain(&txq->ift_timer); 4799 if (txq->ift_task.gt_uniq != NULL) 4800 taskqgroup_detach(tqg, &txq->ift_task); 4801 } 4802 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4803 if (rxq->ifr_task.gt_uniq != NULL) 4804 taskqgroup_detach(tqg, &rxq->ifr_task); 4805 4806 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4807 free(fl->ifl_rx_bitmap, M_IFLIB); 4808 } 4809 tqg = qgroup_if_config_tqg; 4810 if (ctx->ifc_admin_task.gt_uniq != NULL) 4811 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4812 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4813 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4814 4815 if_free(ifp); 4816 4817 iflib_tx_structures_free(ctx); 4818 iflib_rx_structures_free(ctx); 4819 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4820 free(ctx->ifc_softc, M_IFLIB); 4821 free(ctx, M_IFLIB); 4822 return (0); 4823 } 4824 4825 int 4826 iflib_device_attach(device_t dev) 4827 { 4828 if_ctx_t ctx; 4829 if_shared_ctx_t sctx; 4830 4831 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4832 return (ENOTSUP); 4833 4834 pci_enable_busmaster(dev); 4835 4836 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4837 } 4838 4839 int 4840 iflib_device_deregister(if_ctx_t ctx) 4841 { 4842 if_t ifp = ctx->ifc_ifp; 4843 iflib_txq_t txq; 4844 iflib_rxq_t rxq; 4845 device_t dev = ctx->ifc_dev; 4846 int i, j; 4847 struct taskqgroup *tqg; 4848 iflib_fl_t fl; 4849 4850 /* Make sure VLANS are not using driver */ 4851 if (if_vlantrunkinuse(ifp)) { 4852 device_printf(dev, "Vlan in use, detach first\n"); 4853 return (EBUSY); 4854 } 4855 #ifdef PCI_IOV 4856 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 4857 device_printf(dev, "SR-IOV in use; detach first.\n"); 4858 return (EBUSY); 4859 } 4860 #endif 4861 4862 STATE_LOCK(ctx); 4863 ctx->ifc_flags |= IFC_IN_DETACH; 4864 STATE_UNLOCK(ctx); 4865 4866 CTX_LOCK(ctx); 4867 iflib_stop(ctx); 4868 CTX_UNLOCK(ctx); 4869 4870 /* Unregister VLAN events */ 4871 if (ctx->ifc_vlan_attach_event != NULL) 4872 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4873 if (ctx->ifc_vlan_detach_event != NULL) 4874 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4875 4876 iflib_netmap_detach(ifp); 4877 ether_ifdetach(ifp); 4878 if (ctx->ifc_led_dev != NULL) 4879 led_destroy(ctx->ifc_led_dev); 4880 /* XXX drain any dependent tasks */ 4881 tqg = qgroup_if_io_tqg; 4882 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4883 callout_drain(&txq->ift_timer); 4884 if (txq->ift_task.gt_uniq != NULL) 4885 taskqgroup_detach(tqg, &txq->ift_task); 4886 } 4887 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4888 if (rxq->ifr_task.gt_uniq != NULL) 4889 taskqgroup_detach(tqg, &rxq->ifr_task); 4890 4891 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4892 free(fl->ifl_rx_bitmap, M_IFLIB); 4893 4894 } 4895 tqg = qgroup_if_config_tqg; 4896 if (ctx->ifc_admin_task.gt_uniq != NULL) 4897 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4898 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4899 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4900 CTX_LOCK(ctx); 4901 IFDI_DETACH(ctx); 4902 CTX_UNLOCK(ctx); 4903 4904 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4905 CTX_LOCK_DESTROY(ctx); 4906 device_set_softc(ctx->ifc_dev, NULL); 4907 iflib_free_intr_mem(ctx); 4908 4909 bus_generic_detach(dev); 4910 if_free(ifp); 4911 4912 iflib_tx_structures_free(ctx); 4913 iflib_rx_structures_free(ctx); 4914 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4915 free(ctx->ifc_softc, M_IFLIB); 4916 STATE_LOCK_DESTROY(ctx); 4917 free(ctx, M_IFLIB); 4918 return (0); 4919 } 4920 4921 static void 4922 iflib_free_intr_mem(if_ctx_t ctx) 4923 { 4924 4925 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4926 pci_release_msi(ctx->ifc_dev); 4927 } 4928 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4929 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4930 } 4931 if (ctx->ifc_msix_mem != NULL) { 4932 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4933 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4934 ctx->ifc_msix_mem = NULL; 4935 } 4936 } 4937 4938 int 4939 iflib_device_detach(device_t dev) 4940 { 4941 if_ctx_t ctx = device_get_softc(dev); 4942 4943 return (iflib_device_deregister(ctx)); 4944 } 4945 4946 int 4947 iflib_device_suspend(device_t dev) 4948 { 4949 if_ctx_t ctx = device_get_softc(dev); 4950 4951 CTX_LOCK(ctx); 4952 IFDI_SUSPEND(ctx); 4953 CTX_UNLOCK(ctx); 4954 4955 return bus_generic_suspend(dev); 4956 } 4957 int 4958 iflib_device_shutdown(device_t dev) 4959 { 4960 if_ctx_t ctx = device_get_softc(dev); 4961 4962 CTX_LOCK(ctx); 4963 IFDI_SHUTDOWN(ctx); 4964 CTX_UNLOCK(ctx); 4965 4966 return bus_generic_suspend(dev); 4967 } 4968 4969 4970 int 4971 iflib_device_resume(device_t dev) 4972 { 4973 if_ctx_t ctx = device_get_softc(dev); 4974 iflib_txq_t txq = ctx->ifc_txqs; 4975 4976 CTX_LOCK(ctx); 4977 IFDI_RESUME(ctx); 4978 iflib_if_init_locked(ctx); 4979 CTX_UNLOCK(ctx); 4980 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4981 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4982 4983 return (bus_generic_resume(dev)); 4984 } 4985 4986 int 4987 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4988 { 4989 int error; 4990 if_ctx_t ctx = device_get_softc(dev); 4991 4992 CTX_LOCK(ctx); 4993 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4994 CTX_UNLOCK(ctx); 4995 4996 return (error); 4997 } 4998 4999 void 5000 iflib_device_iov_uninit(device_t dev) 5001 { 5002 if_ctx_t ctx = device_get_softc(dev); 5003 5004 CTX_LOCK(ctx); 5005 IFDI_IOV_UNINIT(ctx); 5006 CTX_UNLOCK(ctx); 5007 } 5008 5009 int 5010 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5011 { 5012 int error; 5013 if_ctx_t ctx = device_get_softc(dev); 5014 5015 CTX_LOCK(ctx); 5016 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5017 CTX_UNLOCK(ctx); 5018 5019 return (error); 5020 } 5021 5022 /********************************************************************* 5023 * 5024 * MODULE FUNCTION DEFINITIONS 5025 * 5026 **********************************************************************/ 5027 5028 /* 5029 * - Start a fast taskqueue thread for each core 5030 * - Start a taskqueue for control operations 5031 */ 5032 static int 5033 iflib_module_init(void) 5034 { 5035 return (0); 5036 } 5037 5038 static int 5039 iflib_module_event_handler(module_t mod, int what, void *arg) 5040 { 5041 int err; 5042 5043 switch (what) { 5044 case MOD_LOAD: 5045 if ((err = iflib_module_init()) != 0) 5046 return (err); 5047 break; 5048 case MOD_UNLOAD: 5049 return (EBUSY); 5050 default: 5051 return (EOPNOTSUPP); 5052 } 5053 5054 return (0); 5055 } 5056 5057 /********************************************************************* 5058 * 5059 * PUBLIC FUNCTION DEFINITIONS 5060 * ordered as in iflib.h 5061 * 5062 **********************************************************************/ 5063 5064 5065 static void 5066 _iflib_assert(if_shared_ctx_t sctx) 5067 { 5068 MPASS(sctx->isc_tx_maxsize); 5069 MPASS(sctx->isc_tx_maxsegsize); 5070 5071 MPASS(sctx->isc_rx_maxsize); 5072 MPASS(sctx->isc_rx_nsegments); 5073 MPASS(sctx->isc_rx_maxsegsize); 5074 5075 MPASS(sctx->isc_nrxd_min[0]); 5076 MPASS(sctx->isc_nrxd_max[0]); 5077 MPASS(sctx->isc_nrxd_default[0]); 5078 MPASS(sctx->isc_ntxd_min[0]); 5079 MPASS(sctx->isc_ntxd_max[0]); 5080 MPASS(sctx->isc_ntxd_default[0]); 5081 } 5082 5083 static void 5084 _iflib_pre_assert(if_softc_ctx_t scctx) 5085 { 5086 5087 MPASS(scctx->isc_txrx->ift_txd_encap); 5088 MPASS(scctx->isc_txrx->ift_txd_flush); 5089 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5090 MPASS(scctx->isc_txrx->ift_rxd_available); 5091 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5092 MPASS(scctx->isc_txrx->ift_rxd_refill); 5093 MPASS(scctx->isc_txrx->ift_rxd_flush); 5094 } 5095 5096 static int 5097 iflib_register(if_ctx_t ctx) 5098 { 5099 if_shared_ctx_t sctx = ctx->ifc_sctx; 5100 driver_t *driver = sctx->isc_driver; 5101 device_t dev = ctx->ifc_dev; 5102 if_t ifp; 5103 5104 _iflib_assert(sctx); 5105 5106 CTX_LOCK_INIT(ctx); 5107 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5108 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5109 if (ifp == NULL) { 5110 device_printf(dev, "can not allocate ifnet structure\n"); 5111 return (ENOMEM); 5112 } 5113 5114 /* 5115 * Initialize our context's device specific methods 5116 */ 5117 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5118 kobj_class_compile((kobj_class_t) driver); 5119 driver->refs++; 5120 5121 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5122 if_setsoftc(ifp, ctx); 5123 if_setdev(ifp, dev); 5124 if_setinitfn(ifp, iflib_if_init); 5125 if_setioctlfn(ifp, iflib_if_ioctl); 5126 #ifdef ALTQ 5127 if_setstartfn(ifp, iflib_altq_if_start); 5128 if_settransmitfn(ifp, iflib_altq_if_transmit); 5129 if_setsendqready(ifp); 5130 #else 5131 if_settransmitfn(ifp, iflib_if_transmit); 5132 #endif 5133 if_setqflushfn(ifp, iflib_if_qflush); 5134 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5135 5136 ctx->ifc_vlan_attach_event = 5137 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5138 EVENTHANDLER_PRI_FIRST); 5139 ctx->ifc_vlan_detach_event = 5140 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5141 EVENTHANDLER_PRI_FIRST); 5142 5143 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 5144 iflib_media_change, iflib_media_status); 5145 5146 return (0); 5147 } 5148 5149 5150 static int 5151 iflib_queues_alloc(if_ctx_t ctx) 5152 { 5153 if_shared_ctx_t sctx = ctx->ifc_sctx; 5154 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5155 device_t dev = ctx->ifc_dev; 5156 int nrxqsets = scctx->isc_nrxqsets; 5157 int ntxqsets = scctx->isc_ntxqsets; 5158 iflib_txq_t txq; 5159 iflib_rxq_t rxq; 5160 iflib_fl_t fl = NULL; 5161 int i, j, cpu, err, txconf, rxconf; 5162 iflib_dma_info_t ifdip; 5163 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5164 uint32_t *txqsizes = scctx->isc_txqsizes; 5165 uint8_t nrxqs = sctx->isc_nrxqs; 5166 uint8_t ntxqs = sctx->isc_ntxqs; 5167 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5168 caddr_t *vaddrs; 5169 uint64_t *paddrs; 5170 5171 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5172 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5173 5174 /* Allocate the TX ring struct memory */ 5175 if (!(ctx->ifc_txqs = 5176 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5177 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5178 device_printf(dev, "Unable to allocate TX ring memory\n"); 5179 err = ENOMEM; 5180 goto fail; 5181 } 5182 5183 /* Now allocate the RX */ 5184 if (!(ctx->ifc_rxqs = 5185 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5186 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5187 device_printf(dev, "Unable to allocate RX ring memory\n"); 5188 err = ENOMEM; 5189 goto rx_fail; 5190 } 5191 5192 txq = ctx->ifc_txqs; 5193 rxq = ctx->ifc_rxqs; 5194 5195 /* 5196 * XXX handle allocation failure 5197 */ 5198 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5199 /* Set up some basics */ 5200 5201 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 5202 device_printf(dev, "failed to allocate iflib_dma_info\n"); 5203 err = ENOMEM; 5204 goto err_tx_desc; 5205 } 5206 txq->ift_ifdi = ifdip; 5207 for (j = 0; j < ntxqs; j++, ifdip++) { 5208 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 5209 device_printf(dev, "Unable to allocate Descriptor memory\n"); 5210 err = ENOMEM; 5211 goto err_tx_desc; 5212 } 5213 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5214 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5215 } 5216 txq->ift_ctx = ctx; 5217 txq->ift_id = i; 5218 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5219 txq->ift_br_offset = 1; 5220 } else { 5221 txq->ift_br_offset = 0; 5222 } 5223 /* XXX fix this */ 5224 txq->ift_timer.c_cpu = cpu; 5225 5226 if (iflib_txsd_alloc(txq)) { 5227 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5228 err = ENOMEM; 5229 goto err_tx_desc; 5230 } 5231 5232 /* Initialize the TX lock */ 5233 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 5234 device_get_nameunit(dev), txq->ift_id); 5235 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5236 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5237 5238 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 5239 device_get_nameunit(dev), txq->ift_id); 5240 5241 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5242 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5243 if (err) { 5244 /* XXX free any allocated rings */ 5245 device_printf(dev, "Unable to allocate buf_ring\n"); 5246 goto err_tx_desc; 5247 } 5248 } 5249 5250 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5251 /* Set up some basics */ 5252 5253 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 5254 device_printf(dev, "failed to allocate iflib_dma_info\n"); 5255 err = ENOMEM; 5256 goto err_tx_desc; 5257 } 5258 5259 rxq->ifr_ifdi = ifdip; 5260 /* XXX this needs to be changed if #rx queues != #tx queues */ 5261 rxq->ifr_ntxqirq = 1; 5262 rxq->ifr_txqid[0] = i; 5263 for (j = 0; j < nrxqs; j++, ifdip++) { 5264 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 5265 device_printf(dev, "Unable to allocate Descriptor memory\n"); 5266 err = ENOMEM; 5267 goto err_tx_desc; 5268 } 5269 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5270 } 5271 rxq->ifr_ctx = ctx; 5272 rxq->ifr_id = i; 5273 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5274 rxq->ifr_fl_offset = 1; 5275 } else { 5276 rxq->ifr_fl_offset = 0; 5277 } 5278 rxq->ifr_nfl = nfree_lists; 5279 if (!(fl = 5280 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5281 device_printf(dev, "Unable to allocate free list memory\n"); 5282 err = ENOMEM; 5283 goto err_tx_desc; 5284 } 5285 rxq->ifr_fl = fl; 5286 for (j = 0; j < nfree_lists; j++) { 5287 fl[j].ifl_rxq = rxq; 5288 fl[j].ifl_id = j; 5289 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5290 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5291 } 5292 /* Allocate receive buffers for the ring */ 5293 if (iflib_rxsd_alloc(rxq)) { 5294 device_printf(dev, 5295 "Critical Failure setting up receive buffers\n"); 5296 err = ENOMEM; 5297 goto err_rx_desc; 5298 } 5299 5300 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5301 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 5302 } 5303 5304 /* TXQs */ 5305 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5306 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5307 for (i = 0; i < ntxqsets; i++) { 5308 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5309 5310 for (j = 0; j < ntxqs; j++, di++) { 5311 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5312 paddrs[i*ntxqs + j] = di->idi_paddr; 5313 } 5314 } 5315 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5316 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 5317 iflib_tx_structures_free(ctx); 5318 free(vaddrs, M_IFLIB); 5319 free(paddrs, M_IFLIB); 5320 goto err_rx_desc; 5321 } 5322 free(vaddrs, M_IFLIB); 5323 free(paddrs, M_IFLIB); 5324 5325 /* RXQs */ 5326 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5327 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5328 for (i = 0; i < nrxqsets; i++) { 5329 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5330 5331 for (j = 0; j < nrxqs; j++, di++) { 5332 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5333 paddrs[i*nrxqs + j] = di->idi_paddr; 5334 } 5335 } 5336 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5337 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 5338 iflib_tx_structures_free(ctx); 5339 free(vaddrs, M_IFLIB); 5340 free(paddrs, M_IFLIB); 5341 goto err_rx_desc; 5342 } 5343 free(vaddrs, M_IFLIB); 5344 free(paddrs, M_IFLIB); 5345 5346 return (0); 5347 5348 /* XXX handle allocation failure changes */ 5349 err_rx_desc: 5350 err_tx_desc: 5351 rx_fail: 5352 if (ctx->ifc_rxqs != NULL) 5353 free(ctx->ifc_rxqs, M_IFLIB); 5354 ctx->ifc_rxqs = NULL; 5355 if (ctx->ifc_txqs != NULL) 5356 free(ctx->ifc_txqs, M_IFLIB); 5357 ctx->ifc_txqs = NULL; 5358 fail: 5359 return (err); 5360 } 5361 5362 static int 5363 iflib_tx_structures_setup(if_ctx_t ctx) 5364 { 5365 iflib_txq_t txq = ctx->ifc_txqs; 5366 int i; 5367 5368 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5369 iflib_txq_setup(txq); 5370 5371 return (0); 5372 } 5373 5374 static void 5375 iflib_tx_structures_free(if_ctx_t ctx) 5376 { 5377 iflib_txq_t txq = ctx->ifc_txqs; 5378 if_shared_ctx_t sctx = ctx->ifc_sctx; 5379 int i, j; 5380 5381 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5382 iflib_txq_destroy(txq); 5383 for (j = 0; j < sctx->isc_ntxqs; j++) 5384 iflib_dma_free(&txq->ift_ifdi[j]); 5385 } 5386 free(ctx->ifc_txqs, M_IFLIB); 5387 ctx->ifc_txqs = NULL; 5388 IFDI_QUEUES_FREE(ctx); 5389 } 5390 5391 /********************************************************************* 5392 * 5393 * Initialize all receive rings. 5394 * 5395 **********************************************************************/ 5396 static int 5397 iflib_rx_structures_setup(if_ctx_t ctx) 5398 { 5399 iflib_rxq_t rxq = ctx->ifc_rxqs; 5400 int q; 5401 #if defined(INET6) || defined(INET) 5402 int i, err; 5403 #endif 5404 5405 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5406 #if defined(INET6) || defined(INET) 5407 tcp_lro_free(&rxq->ifr_lc); 5408 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5409 TCP_LRO_ENTRIES, min(1024, 5410 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 5411 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 5412 goto fail; 5413 } 5414 rxq->ifr_lro_enabled = TRUE; 5415 #endif 5416 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5417 } 5418 return (0); 5419 #if defined(INET6) || defined(INET) 5420 fail: 5421 /* 5422 * Free RX software descriptors allocated so far, we will only handle 5423 * the rings that completed, the failing case will have 5424 * cleaned up for itself. 'q' failed, so its the terminus. 5425 */ 5426 rxq = ctx->ifc_rxqs; 5427 for (i = 0; i < q; ++i, rxq++) { 5428 iflib_rx_sds_free(rxq); 5429 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5430 } 5431 return (err); 5432 #endif 5433 } 5434 5435 /********************************************************************* 5436 * 5437 * Free all receive rings. 5438 * 5439 **********************************************************************/ 5440 static void 5441 iflib_rx_structures_free(if_ctx_t ctx) 5442 { 5443 iflib_rxq_t rxq = ctx->ifc_rxqs; 5444 5445 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5446 iflib_rx_sds_free(rxq); 5447 } 5448 free(ctx->ifc_rxqs, M_IFLIB); 5449 ctx->ifc_rxqs = NULL; 5450 } 5451 5452 static int 5453 iflib_qset_structures_setup(if_ctx_t ctx) 5454 { 5455 int err; 5456 5457 /* 5458 * It is expected that the caller takes care of freeing queues if this 5459 * fails. 5460 */ 5461 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5462 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5463 return (err); 5464 } 5465 5466 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5467 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5468 5469 return (err); 5470 } 5471 5472 int 5473 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5474 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5475 { 5476 5477 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5478 } 5479 5480 #ifdef SMP 5481 static int 5482 find_nth(if_ctx_t ctx, int qid) 5483 { 5484 cpuset_t cpus; 5485 int i, cpuid, eqid, count; 5486 5487 CPU_COPY(&ctx->ifc_cpus, &cpus); 5488 count = CPU_COUNT(&cpus); 5489 eqid = qid % count; 5490 /* clear up to the qid'th bit */ 5491 for (i = 0; i < eqid; i++) { 5492 cpuid = CPU_FFS(&cpus); 5493 MPASS(cpuid != 0); 5494 CPU_CLR(cpuid-1, &cpus); 5495 } 5496 cpuid = CPU_FFS(&cpus); 5497 MPASS(cpuid != 0); 5498 return (cpuid-1); 5499 } 5500 5501 #ifdef SCHED_ULE 5502 extern struct cpu_group *cpu_top; /* CPU topology */ 5503 5504 static int 5505 find_child_with_core(int cpu, struct cpu_group *grp) 5506 { 5507 int i; 5508 5509 if (grp->cg_children == 0) 5510 return -1; 5511 5512 MPASS(grp->cg_child); 5513 for (i = 0; i < grp->cg_children; i++) { 5514 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5515 return i; 5516 } 5517 5518 return -1; 5519 } 5520 5521 /* 5522 * Find the nth "close" core to the specified core 5523 * "close" is defined as the deepest level that shares 5524 * at least an L2 cache. With threads, this will be 5525 * threads on the same core. If the sahred cache is L3 5526 * or higher, simply returns the same core. 5527 */ 5528 static int 5529 find_close_core(int cpu, int core_offset) 5530 { 5531 struct cpu_group *grp; 5532 int i; 5533 int fcpu; 5534 cpuset_t cs; 5535 5536 grp = cpu_top; 5537 if (grp == NULL) 5538 return cpu; 5539 i = 0; 5540 while ((i = find_child_with_core(cpu, grp)) != -1) { 5541 /* If the child only has one cpu, don't descend */ 5542 if (grp->cg_child[i].cg_count <= 1) 5543 break; 5544 grp = &grp->cg_child[i]; 5545 } 5546 5547 /* If they don't share at least an L2 cache, use the same CPU */ 5548 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5549 return cpu; 5550 5551 /* Now pick one */ 5552 CPU_COPY(&grp->cg_mask, &cs); 5553 5554 /* Add the selected CPU offset to core offset. */ 5555 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5556 if (fcpu - 1 == cpu) 5557 break; 5558 CPU_CLR(fcpu - 1, &cs); 5559 } 5560 MPASS(fcpu); 5561 5562 core_offset += i; 5563 5564 CPU_COPY(&grp->cg_mask, &cs); 5565 for (i = core_offset % grp->cg_count; i > 0; i--) { 5566 MPASS(CPU_FFS(&cs)); 5567 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5568 } 5569 MPASS(CPU_FFS(&cs)); 5570 return CPU_FFS(&cs) - 1; 5571 } 5572 #else 5573 static int 5574 find_close_core(int cpu, int core_offset __unused) 5575 { 5576 return cpu; 5577 } 5578 #endif 5579 5580 static int 5581 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5582 { 5583 switch (type) { 5584 case IFLIB_INTR_TX: 5585 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5586 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5587 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5588 case IFLIB_INTR_RX: 5589 case IFLIB_INTR_RXTX: 5590 /* RX queues get the specified core */ 5591 return qid / CPU_COUNT(&ctx->ifc_cpus); 5592 default: 5593 return -1; 5594 } 5595 } 5596 #else 5597 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5598 #define find_close_core(cpuid, tid) CPU_FIRST() 5599 #define find_nth(ctx, gid) CPU_FIRST() 5600 #endif 5601 5602 /* Just to avoid copy/paste */ 5603 static inline int 5604 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid, 5605 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, const char *name) 5606 { 5607 int cpuid; 5608 int err, tid; 5609 5610 cpuid = find_nth(ctx, qid); 5611 tid = get_core_offset(ctx, type, qid); 5612 MPASS(tid >= 0); 5613 cpuid = find_close_core(cpuid, tid); 5614 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name); 5615 if (err) { 5616 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err); 5617 return (err); 5618 } 5619 #ifdef notyet 5620 if (cpuid > ctx->ifc_cpuid_highest) 5621 ctx->ifc_cpuid_highest = cpuid; 5622 #endif 5623 return 0; 5624 } 5625 5626 int 5627 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5628 iflib_intr_type_t type, driver_filter_t *filter, 5629 void *filter_arg, int qid, const char *name) 5630 { 5631 struct grouptask *gtask; 5632 struct taskqgroup *tqg; 5633 iflib_filter_info_t info; 5634 gtask_fn_t *fn; 5635 int tqrid, err; 5636 driver_filter_t *intr_fast; 5637 void *q; 5638 5639 info = &ctx->ifc_filter_info; 5640 tqrid = rid; 5641 5642 switch (type) { 5643 /* XXX merge tx/rx for netmap? */ 5644 case IFLIB_INTR_TX: 5645 q = &ctx->ifc_txqs[qid]; 5646 info = &ctx->ifc_txqs[qid].ift_filter_info; 5647 gtask = &ctx->ifc_txqs[qid].ift_task; 5648 tqg = qgroup_if_io_tqg; 5649 fn = _task_fn_tx; 5650 intr_fast = iflib_fast_intr; 5651 GROUPTASK_INIT(gtask, 0, fn, q); 5652 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5653 break; 5654 case IFLIB_INTR_RX: 5655 q = &ctx->ifc_rxqs[qid]; 5656 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5657 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5658 tqg = qgroup_if_io_tqg; 5659 fn = _task_fn_rx; 5660 intr_fast = iflib_fast_intr; 5661 GROUPTASK_INIT(gtask, 0, fn, q); 5662 break; 5663 case IFLIB_INTR_RXTX: 5664 q = &ctx->ifc_rxqs[qid]; 5665 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5666 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5667 tqg = qgroup_if_io_tqg; 5668 fn = _task_fn_rx; 5669 intr_fast = iflib_fast_intr_rxtx; 5670 GROUPTASK_INIT(gtask, 0, fn, q); 5671 break; 5672 case IFLIB_INTR_ADMIN: 5673 q = ctx; 5674 tqrid = -1; 5675 info = &ctx->ifc_filter_info; 5676 gtask = &ctx->ifc_admin_task; 5677 tqg = qgroup_if_config_tqg; 5678 fn = _task_fn_admin; 5679 intr_fast = iflib_fast_intr_ctx; 5680 break; 5681 default: 5682 panic("unknown net intr type"); 5683 } 5684 5685 info->ifi_filter = filter; 5686 info->ifi_filter_arg = filter_arg; 5687 info->ifi_task = gtask; 5688 info->ifi_ctx = q; 5689 5690 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5691 if (err != 0) { 5692 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 5693 return (err); 5694 } 5695 if (type == IFLIB_INTR_ADMIN) 5696 return (0); 5697 5698 if (tqrid != -1) { 5699 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name); 5700 if (err) 5701 return (err); 5702 } else { 5703 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5704 } 5705 5706 return (0); 5707 } 5708 5709 void 5710 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 5711 { 5712 struct grouptask *gtask; 5713 struct taskqgroup *tqg; 5714 gtask_fn_t *fn; 5715 void *q; 5716 int irq_num = -1; 5717 int err; 5718 5719 switch (type) { 5720 case IFLIB_INTR_TX: 5721 q = &ctx->ifc_txqs[qid]; 5722 gtask = &ctx->ifc_txqs[qid].ift_task; 5723 tqg = qgroup_if_io_tqg; 5724 fn = _task_fn_tx; 5725 if (irq != NULL) 5726 irq_num = rman_get_start(irq->ii_res); 5727 break; 5728 case IFLIB_INTR_RX: 5729 q = &ctx->ifc_rxqs[qid]; 5730 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5731 tqg = qgroup_if_io_tqg; 5732 fn = _task_fn_rx; 5733 if (irq != NULL) 5734 irq_num = rman_get_start(irq->ii_res); 5735 break; 5736 case IFLIB_INTR_IOV: 5737 q = ctx; 5738 gtask = &ctx->ifc_vflr_task; 5739 tqg = qgroup_if_config_tqg; 5740 fn = _task_fn_iov; 5741 break; 5742 default: 5743 panic("unknown net intr type"); 5744 } 5745 GROUPTASK_INIT(gtask, 0, fn, q); 5746 if (irq_num != -1) { 5747 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name); 5748 if (err) 5749 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5750 } 5751 else { 5752 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5753 } 5754 } 5755 5756 void 5757 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5758 { 5759 if (irq->ii_tag) 5760 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5761 5762 if (irq->ii_res) 5763 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5764 } 5765 5766 static int 5767 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 5768 { 5769 iflib_txq_t txq = ctx->ifc_txqs; 5770 iflib_rxq_t rxq = ctx->ifc_rxqs; 5771 if_irq_t irq = &ctx->ifc_legacy_irq; 5772 iflib_filter_info_t info; 5773 struct grouptask *gtask; 5774 struct taskqgroup *tqg; 5775 gtask_fn_t *fn; 5776 int tqrid; 5777 void *q; 5778 int err; 5779 5780 q = &ctx->ifc_rxqs[0]; 5781 info = &rxq[0].ifr_filter_info; 5782 gtask = &rxq[0].ifr_task; 5783 tqg = qgroup_if_io_tqg; 5784 tqrid = irq->ii_rid = *rid; 5785 fn = _task_fn_rx; 5786 5787 ctx->ifc_flags |= IFC_LEGACY; 5788 info->ifi_filter = filter; 5789 info->ifi_filter_arg = filter_arg; 5790 info->ifi_task = gtask; 5791 info->ifi_ctx = ctx; 5792 5793 /* We allocate a single interrupt resource */ 5794 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5795 return (err); 5796 GROUPTASK_INIT(gtask, 0, fn, q); 5797 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5798 5799 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5800 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx"); 5801 return (0); 5802 } 5803 5804 void 5805 iflib_led_create(if_ctx_t ctx) 5806 { 5807 5808 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5809 device_get_nameunit(ctx->ifc_dev)); 5810 } 5811 5812 void 5813 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5814 { 5815 5816 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5817 } 5818 5819 void 5820 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5821 { 5822 5823 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5824 } 5825 5826 void 5827 iflib_admin_intr_deferred(if_ctx_t ctx) 5828 { 5829 #ifdef INVARIANTS 5830 struct grouptask *gtask; 5831 5832 gtask = &ctx->ifc_admin_task; 5833 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5834 #endif 5835 5836 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5837 } 5838 5839 void 5840 iflib_iov_intr_deferred(if_ctx_t ctx) 5841 { 5842 5843 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5844 } 5845 5846 void 5847 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5848 { 5849 5850 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5851 } 5852 5853 void 5854 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 5855 const char *name) 5856 { 5857 5858 GROUPTASK_INIT(gtask, 0, fn, ctx); 5859 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5860 } 5861 5862 void 5863 iflib_config_gtask_deinit(struct grouptask *gtask) 5864 { 5865 5866 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5867 } 5868 5869 void 5870 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5871 { 5872 if_t ifp = ctx->ifc_ifp; 5873 iflib_txq_t txq = ctx->ifc_txqs; 5874 5875 if_setbaudrate(ifp, baudrate); 5876 if (baudrate >= IF_Gbps(10)) { 5877 STATE_LOCK(ctx); 5878 ctx->ifc_flags |= IFC_PREFETCH; 5879 STATE_UNLOCK(ctx); 5880 } 5881 /* If link down, disable watchdog */ 5882 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5883 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5884 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5885 } 5886 ctx->ifc_link_state = link_state; 5887 if_link_state_change(ifp, link_state); 5888 } 5889 5890 static int 5891 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5892 { 5893 int credits; 5894 #ifdef INVARIANTS 5895 int credits_pre = txq->ift_cidx_processed; 5896 #endif 5897 5898 if (ctx->isc_txd_credits_update == NULL) 5899 return (0); 5900 5901 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 5902 BUS_DMASYNC_POSTREAD); 5903 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5904 return (0); 5905 5906 txq->ift_processed += credits; 5907 txq->ift_cidx_processed += credits; 5908 5909 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5910 if (txq->ift_cidx_processed >= txq->ift_size) 5911 txq->ift_cidx_processed -= txq->ift_size; 5912 return (credits); 5913 } 5914 5915 static int 5916 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5917 { 5918 5919 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5920 budget)); 5921 } 5922 5923 void 5924 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5925 const char *description, if_int_delay_info_t info, 5926 int offset, int value) 5927 { 5928 info->iidi_ctx = ctx; 5929 info->iidi_offset = offset; 5930 info->iidi_value = value; 5931 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5932 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5933 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5934 info, 0, iflib_sysctl_int_delay, "I", description); 5935 } 5936 5937 struct sx * 5938 iflib_ctx_lock_get(if_ctx_t ctx) 5939 { 5940 5941 return (&ctx->ifc_ctx_sx); 5942 } 5943 5944 static int 5945 iflib_msix_init(if_ctx_t ctx) 5946 { 5947 device_t dev = ctx->ifc_dev; 5948 if_shared_ctx_t sctx = ctx->ifc_sctx; 5949 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5950 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5951 int iflib_num_tx_queues, iflib_num_rx_queues; 5952 int err, admincnt, bar; 5953 5954 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 5955 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 5956 5957 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 5958 5959 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5960 admincnt = sctx->isc_admin_intrcnt; 5961 /* Override by tuneable */ 5962 if (scctx->isc_disable_msix) 5963 goto msi; 5964 5965 /* 5966 * bar == -1 => "trust me I know what I'm doing" 5967 * Some drivers are for hardware that is so shoddily 5968 * documented that no one knows which bars are which 5969 * so the developer has to map all bars. This hack 5970 * allows shoddy garbage to use msix in this framework. 5971 */ 5972 if (bar != -1) { 5973 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5974 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5975 if (ctx->ifc_msix_mem == NULL) { 5976 /* May not be enabled */ 5977 device_printf(dev, "Unable to map MSIX table \n"); 5978 goto msi; 5979 } 5980 } 5981 /* First try MSI/X */ 5982 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5983 device_printf(dev, "System has MSIX disabled \n"); 5984 bus_release_resource(dev, SYS_RES_MEMORY, 5985 bar, ctx->ifc_msix_mem); 5986 ctx->ifc_msix_mem = NULL; 5987 goto msi; 5988 } 5989 #if IFLIB_DEBUG 5990 /* use only 1 qset in debug mode */ 5991 queuemsgs = min(msgs - admincnt, 1); 5992 #else 5993 queuemsgs = msgs - admincnt; 5994 #endif 5995 #ifdef RSS 5996 queues = imin(queuemsgs, rss_getnumbuckets()); 5997 #else 5998 queues = queuemsgs; 5999 #endif 6000 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6001 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 6002 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6003 #ifdef RSS 6004 /* If we're doing RSS, clamp at the number of RSS buckets */ 6005 if (queues > rss_getnumbuckets()) 6006 queues = rss_getnumbuckets(); 6007 #endif 6008 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6009 rx_queues = iflib_num_rx_queues; 6010 else 6011 rx_queues = queues; 6012 6013 if (rx_queues > scctx->isc_nrxqsets) 6014 rx_queues = scctx->isc_nrxqsets; 6015 6016 /* 6017 * We want this to be all logical CPUs by default 6018 */ 6019 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6020 tx_queues = iflib_num_tx_queues; 6021 else 6022 tx_queues = mp_ncpus; 6023 6024 if (tx_queues > scctx->isc_ntxqsets) 6025 tx_queues = scctx->isc_ntxqsets; 6026 6027 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6028 #ifdef INVARIANTS 6029 if (tx_queues != rx_queues) 6030 device_printf(dev, 6031 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6032 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6033 #endif 6034 tx_queues = min(rx_queues, tx_queues); 6035 rx_queues = min(rx_queues, tx_queues); 6036 } 6037 6038 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 6039 6040 vectors = rx_queues + admincnt; 6041 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6042 device_printf(dev, "Using MSIX interrupts with %d vectors\n", vectors); 6043 scctx->isc_vectors = vectors; 6044 scctx->isc_nrxqsets = rx_queues; 6045 scctx->isc_ntxqsets = tx_queues; 6046 scctx->isc_intr = IFLIB_INTR_MSIX; 6047 6048 return (vectors); 6049 } else { 6050 device_printf(dev, 6051 "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 6052 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6053 ctx->ifc_msix_mem); 6054 ctx->ifc_msix_mem = NULL; 6055 } 6056 msi: 6057 vectors = pci_msi_count(dev); 6058 scctx->isc_nrxqsets = 1; 6059 scctx->isc_ntxqsets = 1; 6060 scctx->isc_vectors = vectors; 6061 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6062 device_printf(dev,"Using an MSI interrupt\n"); 6063 scctx->isc_intr = IFLIB_INTR_MSI; 6064 } else { 6065 scctx->isc_vectors = 1; 6066 device_printf(dev,"Using a Legacy interrupt\n"); 6067 scctx->isc_intr = IFLIB_INTR_LEGACY; 6068 } 6069 6070 return (vectors); 6071 } 6072 6073 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6074 6075 static int 6076 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6077 { 6078 int rc; 6079 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6080 struct sbuf *sb; 6081 const char *ring_state = "UNKNOWN"; 6082 6083 /* XXX needed ? */ 6084 rc = sysctl_wire_old_buffer(req, 0); 6085 MPASS(rc == 0); 6086 if (rc != 0) 6087 return (rc); 6088 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6089 MPASS(sb != NULL); 6090 if (sb == NULL) 6091 return (ENOMEM); 6092 if (state[3] <= 3) 6093 ring_state = ring_states[state[3]]; 6094 6095 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6096 state[0], state[1], state[2], ring_state); 6097 rc = sbuf_finish(sb); 6098 sbuf_delete(sb); 6099 return(rc); 6100 } 6101 6102 enum iflib_ndesc_handler { 6103 IFLIB_NTXD_HANDLER, 6104 IFLIB_NRXD_HANDLER, 6105 }; 6106 6107 static int 6108 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6109 { 6110 if_ctx_t ctx = (void *)arg1; 6111 enum iflib_ndesc_handler type = arg2; 6112 char buf[256] = {0}; 6113 qidx_t *ndesc; 6114 char *p, *next; 6115 int nqs, rc, i; 6116 6117 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 6118 6119 nqs = 8; 6120 switch(type) { 6121 case IFLIB_NTXD_HANDLER: 6122 ndesc = ctx->ifc_sysctl_ntxds; 6123 if (ctx->ifc_sctx) 6124 nqs = ctx->ifc_sctx->isc_ntxqs; 6125 break; 6126 case IFLIB_NRXD_HANDLER: 6127 ndesc = ctx->ifc_sysctl_nrxds; 6128 if (ctx->ifc_sctx) 6129 nqs = ctx->ifc_sctx->isc_nrxqs; 6130 break; 6131 default: 6132 panic("unhandled type"); 6133 } 6134 if (nqs == 0) 6135 nqs = 8; 6136 6137 for (i=0; i<8; i++) { 6138 if (i >= nqs) 6139 break; 6140 if (i) 6141 strcat(buf, ","); 6142 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6143 } 6144 6145 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6146 if (rc || req->newptr == NULL) 6147 return rc; 6148 6149 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6150 i++, p = strsep(&next, " ,")) { 6151 ndesc[i] = strtoul(p, NULL, 10); 6152 } 6153 6154 return(rc); 6155 } 6156 6157 #define NAME_BUFLEN 32 6158 static void 6159 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6160 { 6161 device_t dev = iflib_get_dev(ctx); 6162 struct sysctl_oid_list *child, *oid_list; 6163 struct sysctl_ctx_list *ctx_list; 6164 struct sysctl_oid *node; 6165 6166 ctx_list = device_get_sysctl_ctx(dev); 6167 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6168 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6169 CTLFLAG_RD, NULL, "IFLIB fields"); 6170 oid_list = SYSCTL_CHILDREN(node); 6171 6172 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6173 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 6174 "driver version"); 6175 6176 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6177 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6178 "# of txqs to use, 0 => use default #"); 6179 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6180 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6181 "# of rxqs to use, 0 => use default #"); 6182 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6183 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6184 "permit #txq != #rxq"); 6185 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6186 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6187 "disable MSIX (default 0)"); 6188 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6189 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6190 "set the rx budget"); 6191 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6192 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6193 "cause tx to abdicate instead of running to completion"); 6194 6195 /* XXX change for per-queue sizes */ 6196 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6197 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6198 mp_ndesc_handler, "A", 6199 "list of # of tx descriptors to use, 0 = use default #"); 6200 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6201 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6202 mp_ndesc_handler, "A", 6203 "list of # of rx descriptors to use, 0 = use default #"); 6204 } 6205 6206 static void 6207 iflib_add_device_sysctl_post(if_ctx_t ctx) 6208 { 6209 if_shared_ctx_t sctx = ctx->ifc_sctx; 6210 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6211 device_t dev = iflib_get_dev(ctx); 6212 struct sysctl_oid_list *child; 6213 struct sysctl_ctx_list *ctx_list; 6214 iflib_fl_t fl; 6215 iflib_txq_t txq; 6216 iflib_rxq_t rxq; 6217 int i, j; 6218 char namebuf[NAME_BUFLEN]; 6219 char *qfmt; 6220 struct sysctl_oid *queue_node, *fl_node, *node; 6221 struct sysctl_oid_list *queue_list, *fl_list; 6222 ctx_list = device_get_sysctl_ctx(dev); 6223 6224 node = ctx->ifc_sysctl_node; 6225 child = SYSCTL_CHILDREN(node); 6226 6227 if (scctx->isc_ntxqsets > 100) 6228 qfmt = "txq%03d"; 6229 else if (scctx->isc_ntxqsets > 10) 6230 qfmt = "txq%02d"; 6231 else 6232 qfmt = "txq%d"; 6233 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6234 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6235 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6236 CTLFLAG_RD, NULL, "Queue Name"); 6237 queue_list = SYSCTL_CHILDREN(queue_node); 6238 #if MEMORY_LOGGING 6239 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6240 CTLFLAG_RD, 6241 &txq->ift_dequeued, "total mbufs freed"); 6242 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6243 CTLFLAG_RD, 6244 &txq->ift_enqueued, "total mbufs enqueued"); 6245 #endif 6246 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6247 CTLFLAG_RD, 6248 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6249 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6250 CTLFLAG_RD, 6251 &txq->ift_pullups, "# of times m_pullup was called"); 6252 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6253 CTLFLAG_RD, 6254 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6255 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6256 CTLFLAG_RD, 6257 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6258 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6259 CTLFLAG_RD, 6260 &txq->ift_map_failed, "# of times dma map failed"); 6261 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6262 CTLFLAG_RD, 6263 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6264 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6265 CTLFLAG_RD, 6266 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6267 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6268 CTLFLAG_RD, 6269 &txq->ift_pidx, 1, "Producer Index"); 6270 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6271 CTLFLAG_RD, 6272 &txq->ift_cidx, 1, "Consumer Index"); 6273 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6274 CTLFLAG_RD, 6275 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6276 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6277 CTLFLAG_RD, 6278 &txq->ift_in_use, 1, "descriptors in use"); 6279 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6280 CTLFLAG_RD, 6281 &txq->ift_processed, "descriptors procesed for clean"); 6282 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6283 CTLFLAG_RD, 6284 &txq->ift_cleaned, "total cleaned"); 6285 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6286 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6287 0, mp_ring_state_handler, "A", "soft ring state"); 6288 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6289 CTLFLAG_RD, &txq->ift_br->enqueues, 6290 "# of enqueues to the mp_ring for this queue"); 6291 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6292 CTLFLAG_RD, &txq->ift_br->drops, 6293 "# of drops in the mp_ring for this queue"); 6294 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6295 CTLFLAG_RD, &txq->ift_br->starts, 6296 "# of normal consumer starts in the mp_ring for this queue"); 6297 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6298 CTLFLAG_RD, &txq->ift_br->stalls, 6299 "# of consumer stalls in the mp_ring for this queue"); 6300 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6301 CTLFLAG_RD, &txq->ift_br->restarts, 6302 "# of consumer restarts in the mp_ring for this queue"); 6303 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6304 CTLFLAG_RD, &txq->ift_br->abdications, 6305 "# of consumer abdications in the mp_ring for this queue"); 6306 } 6307 6308 if (scctx->isc_nrxqsets > 100) 6309 qfmt = "rxq%03d"; 6310 else if (scctx->isc_nrxqsets > 10) 6311 qfmt = "rxq%02d"; 6312 else 6313 qfmt = "rxq%d"; 6314 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6315 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6316 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6317 CTLFLAG_RD, NULL, "Queue Name"); 6318 queue_list = SYSCTL_CHILDREN(queue_node); 6319 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6320 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 6321 CTLFLAG_RD, 6322 &rxq->ifr_cq_pidx, 1, "Producer Index"); 6323 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6324 CTLFLAG_RD, 6325 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6326 } 6327 6328 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6329 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6330 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6331 CTLFLAG_RD, NULL, "freelist Name"); 6332 fl_list = SYSCTL_CHILDREN(fl_node); 6333 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6334 CTLFLAG_RD, 6335 &fl->ifl_pidx, 1, "Producer Index"); 6336 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6337 CTLFLAG_RD, 6338 &fl->ifl_cidx, 1, "Consumer Index"); 6339 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6340 CTLFLAG_RD, 6341 &fl->ifl_credits, 1, "credits available"); 6342 #if MEMORY_LOGGING 6343 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6344 CTLFLAG_RD, 6345 &fl->ifl_m_enqueued, "mbufs allocated"); 6346 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6347 CTLFLAG_RD, 6348 &fl->ifl_m_dequeued, "mbufs freed"); 6349 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6350 CTLFLAG_RD, 6351 &fl->ifl_cl_enqueued, "clusters allocated"); 6352 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6353 CTLFLAG_RD, 6354 &fl->ifl_cl_dequeued, "clusters freed"); 6355 #endif 6356 6357 } 6358 } 6359 6360 } 6361 6362 void 6363 iflib_request_reset(if_ctx_t ctx) 6364 { 6365 6366 STATE_LOCK(ctx); 6367 ctx->ifc_flags |= IFC_DO_RESET; 6368 STATE_UNLOCK(ctx); 6369 } 6370 6371 #ifndef __NO_STRICT_ALIGNMENT 6372 static struct mbuf * 6373 iflib_fixup_rx(struct mbuf *m) 6374 { 6375 struct mbuf *n; 6376 6377 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6378 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6379 m->m_data += ETHER_HDR_LEN; 6380 n = m; 6381 } else { 6382 MGETHDR(n, M_NOWAIT, MT_DATA); 6383 if (n == NULL) { 6384 m_freem(m); 6385 return (NULL); 6386 } 6387 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6388 m->m_data += ETHER_HDR_LEN; 6389 m->m_len -= ETHER_HDR_LEN; 6390 n->m_len = ETHER_HDR_LEN; 6391 M_MOVE_PKTHDR(n, m); 6392 n->m_next = m; 6393 } 6394 return (n); 6395 } 6396 #endif 6397 6398 #ifdef NETDUMP 6399 static void 6400 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 6401 { 6402 if_ctx_t ctx; 6403 6404 ctx = if_getsoftc(ifp); 6405 CTX_LOCK(ctx); 6406 *nrxr = NRXQSETS(ctx); 6407 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6408 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6409 CTX_UNLOCK(ctx); 6410 } 6411 6412 static void 6413 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event) 6414 { 6415 if_ctx_t ctx; 6416 if_softc_ctx_t scctx; 6417 iflib_fl_t fl; 6418 iflib_rxq_t rxq; 6419 int i, j; 6420 6421 ctx = if_getsoftc(ifp); 6422 scctx = &ctx->ifc_softc_ctx; 6423 6424 switch (event) { 6425 case NETDUMP_START: 6426 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6427 rxq = &ctx->ifc_rxqs[i]; 6428 for (j = 0; j < rxq->ifr_nfl; j++) { 6429 fl = rxq->ifr_fl; 6430 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6431 } 6432 } 6433 iflib_no_tx_batch = 1; 6434 break; 6435 default: 6436 break; 6437 } 6438 } 6439 6440 static int 6441 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m) 6442 { 6443 if_ctx_t ctx; 6444 iflib_txq_t txq; 6445 int error; 6446 6447 ctx = if_getsoftc(ifp); 6448 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6449 IFF_DRV_RUNNING) 6450 return (EBUSY); 6451 6452 txq = &ctx->ifc_txqs[0]; 6453 error = iflib_encap(txq, &m); 6454 if (error == 0) 6455 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6456 return (error); 6457 } 6458 6459 static int 6460 iflib_netdump_poll(struct ifnet *ifp, int count) 6461 { 6462 if_ctx_t ctx; 6463 if_softc_ctx_t scctx; 6464 iflib_txq_t txq; 6465 int i; 6466 6467 ctx = if_getsoftc(ifp); 6468 scctx = &ctx->ifc_softc_ctx; 6469 6470 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6471 IFF_DRV_RUNNING) 6472 return (EBUSY); 6473 6474 txq = &ctx->ifc_txqs[0]; 6475 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6476 6477 for (i = 0; i < scctx->isc_nrxqsets; i++) 6478 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6479 return (0); 6480 } 6481 #endif /* NETDUMP */ 6482