1 /*- 2 * Copyright (c) 2014-2017, Matthew Macy <mmacy@nextbsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 35 #include <sys/param.h> 36 #include <sys/types.h> 37 #include <sys/bus.h> 38 #include <sys/eventhandler.h> 39 #include <sys/sockio.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sysctl.h> 50 #include <sys/syslog.h> 51 #include <sys/taskqueue.h> 52 #include <sys/limits.h> 53 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 63 #include <netinet/in.h> 64 #include <netinet/in_pcb.h> 65 #include <netinet/tcp_lro.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/if_ether.h> 68 #include <netinet/ip.h> 69 #include <netinet/ip6.h> 70 #include <netinet/tcp.h> 71 72 #include <machine/bus.h> 73 #include <machine/in_cksum.h> 74 75 #include <vm/vm.h> 76 #include <vm/pmap.h> 77 78 #include <dev/led/led.h> 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pci_private.h> 82 83 #include <net/iflib.h> 84 85 #include "ifdi_if.h" 86 87 #if defined(__i386__) || defined(__amd64__) 88 #include <sys/memdesc.h> 89 #include <machine/bus.h> 90 #include <machine/md_var.h> 91 #include <machine/specialreg.h> 92 #include <x86/include/busdma_impl.h> 93 #include <x86/iommu/busdma_dmar.h> 94 #endif 95 96 /* 97 * enable accounting of every mbuf as it comes in to and goes out of 98 * iflib's software descriptor references 99 */ 100 #define MEMORY_LOGGING 0 101 /* 102 * Enable mbuf vectors for compressing long mbuf chains 103 */ 104 105 /* 106 * NB: 107 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 108 * we prefetch needs to be determined by the time spent in m_free vis a vis 109 * the cost of a prefetch. This will of course vary based on the workload: 110 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 111 * is quite expensive, thus suggesting very little prefetch. 112 * - small packet forwarding which is just returning a single mbuf to 113 * UMA will typically be very fast vis a vis the cost of a memory 114 * access. 115 */ 116 117 118 /* 119 * File organization: 120 * - private structures 121 * - iflib private utility functions 122 * - ifnet functions 123 * - vlan registry and other exported functions 124 * - iflib public core functions 125 * 126 * 127 */ 128 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 129 130 struct iflib_txq; 131 typedef struct iflib_txq *iflib_txq_t; 132 struct iflib_rxq; 133 typedef struct iflib_rxq *iflib_rxq_t; 134 struct iflib_fl; 135 typedef struct iflib_fl *iflib_fl_t; 136 137 struct iflib_ctx; 138 139 typedef struct iflib_filter_info { 140 driver_filter_t *ifi_filter; 141 void *ifi_filter_arg; 142 struct grouptask *ifi_task; 143 void *ifi_ctx; 144 } *iflib_filter_info_t; 145 146 struct iflib_ctx { 147 KOBJ_FIELDS; 148 /* 149 * Pointer to hardware driver's softc 150 */ 151 void *ifc_softc; 152 device_t ifc_dev; 153 if_t ifc_ifp; 154 155 cpuset_t ifc_cpus; 156 if_shared_ctx_t ifc_sctx; 157 struct if_softc_ctx ifc_softc_ctx; 158 159 struct mtx ifc_mtx; 160 161 uint16_t ifc_nhwtxqs; 162 uint16_t ifc_nhwrxqs; 163 164 iflib_txq_t ifc_txqs; 165 iflib_rxq_t ifc_rxqs; 166 uint32_t ifc_if_flags; 167 uint32_t ifc_flags; 168 uint32_t ifc_max_fl_buf_size; 169 int ifc_in_detach; 170 171 int ifc_link_state; 172 int ifc_link_irq; 173 int ifc_pause_frames; 174 int ifc_watchdog_events; 175 struct cdev *ifc_led_dev; 176 struct resource *ifc_msix_mem; 177 178 struct if_irq ifc_legacy_irq; 179 struct grouptask ifc_admin_task; 180 struct grouptask ifc_vflr_task; 181 struct iflib_filter_info ifc_filter_info; 182 struct ifmedia ifc_media; 183 184 struct sysctl_oid *ifc_sysctl_node; 185 uint16_t ifc_sysctl_ntxqs; 186 uint16_t ifc_sysctl_nrxqs; 187 uint16_t ifc_sysctl_qs_eq_override; 188 189 qidx_t ifc_sysctl_ntxds[8]; 190 qidx_t ifc_sysctl_nrxds[8]; 191 struct if_txrx ifc_txrx; 192 #define isc_txd_encap ifc_txrx.ift_txd_encap 193 #define isc_txd_flush ifc_txrx.ift_txd_flush 194 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 195 #define isc_rxd_available ifc_txrx.ift_rxd_available 196 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 197 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 198 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 199 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 200 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 201 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 202 eventhandler_tag ifc_vlan_attach_event; 203 eventhandler_tag ifc_vlan_detach_event; 204 uint8_t ifc_mac[ETHER_ADDR_LEN]; 205 char ifc_mtx_name[16]; 206 }; 207 208 209 void * 210 iflib_get_softc(if_ctx_t ctx) 211 { 212 213 return (ctx->ifc_softc); 214 } 215 216 device_t 217 iflib_get_dev(if_ctx_t ctx) 218 { 219 220 return (ctx->ifc_dev); 221 } 222 223 if_t 224 iflib_get_ifp(if_ctx_t ctx) 225 { 226 227 return (ctx->ifc_ifp); 228 } 229 230 struct ifmedia * 231 iflib_get_media(if_ctx_t ctx) 232 { 233 234 return (&ctx->ifc_media); 235 } 236 237 void 238 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 239 { 240 241 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 242 } 243 244 if_softc_ctx_t 245 iflib_get_softc_ctx(if_ctx_t ctx) 246 { 247 248 return (&ctx->ifc_softc_ctx); 249 } 250 251 if_shared_ctx_t 252 iflib_get_sctx(if_ctx_t ctx) 253 { 254 255 return (ctx->ifc_sctx); 256 } 257 258 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 259 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 260 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 261 262 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 263 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 264 265 #define RX_SW_DESC_MAP_CREATED (1 << 0) 266 #define TX_SW_DESC_MAP_CREATED (1 << 1) 267 #define RX_SW_DESC_INUSE (1 << 3) 268 #define TX_SW_DESC_MAPPED (1 << 4) 269 270 typedef struct iflib_sw_rx_desc_array { 271 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 272 struct mbuf **ifsd_m; /* pkthdr mbufs */ 273 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 274 uint8_t *ifsd_flags; 275 } iflib_rxsd_array_t; 276 277 typedef struct iflib_sw_tx_desc_array { 278 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 279 struct mbuf **ifsd_m; /* pkthdr mbufs */ 280 uint8_t *ifsd_flags; 281 } if_txsd_vec_t; 282 283 284 /* magic number that should be high enough for any hardware */ 285 #define IFLIB_MAX_TX_SEGS 128 286 #define IFLIB_MAX_RX_SEGS 32 287 #define IFLIB_RX_COPY_THRESH 128 288 #define IFLIB_MAX_RX_REFRESH 32 289 /* The minimum descriptors per second before we start coalescing */ 290 #define IFLIB_MIN_DESC_SEC 16384 291 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 292 #define IFLIB_QUEUE_IDLE 0 293 #define IFLIB_QUEUE_HUNG 1 294 #define IFLIB_QUEUE_WORKING 2 295 /* maximum number of txqs that can share an rx interrupt */ 296 #define IFLIB_MAX_TX_SHARED_INTR 4 297 298 /* this should really scale with ring size - this is a fairly arbitrary value */ 299 #define TX_BATCH_SIZE 32 300 301 #define IFLIB_RESTART_BUDGET 8 302 303 #define IFC_LEGACY 0x001 304 #define IFC_QFLUSH 0x002 305 #define IFC_MULTISEG 0x004 306 #define IFC_DMAR 0x008 307 #define IFC_SC_ALLOCATED 0x010 308 #define IFC_INIT_DONE 0x020 309 #define IFC_PREFETCH 0x040 310 #define IFC_DO_RESET 0x080 311 #define IFC_CHECK_HUNG 0x100 312 313 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 314 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 315 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 316 struct iflib_txq { 317 qidx_t ift_in_use; 318 qidx_t ift_cidx; 319 qidx_t ift_cidx_processed; 320 qidx_t ift_pidx; 321 uint8_t ift_gen; 322 uint8_t ift_br_offset; 323 uint16_t ift_npending; 324 uint16_t ift_db_pending; 325 uint16_t ift_rs_pending; 326 /* implicit pad */ 327 uint8_t ift_txd_size[8]; 328 uint64_t ift_processed; 329 uint64_t ift_cleaned; 330 uint64_t ift_cleaned_prev; 331 #if MEMORY_LOGGING 332 uint64_t ift_enqueued; 333 uint64_t ift_dequeued; 334 #endif 335 uint64_t ift_no_tx_dma_setup; 336 uint64_t ift_no_desc_avail; 337 uint64_t ift_mbuf_defrag_failed; 338 uint64_t ift_mbuf_defrag; 339 uint64_t ift_map_failed; 340 uint64_t ift_txd_encap_efbig; 341 uint64_t ift_pullups; 342 343 struct mtx ift_mtx; 344 struct mtx ift_db_mtx; 345 346 /* constant values */ 347 if_ctx_t ift_ctx; 348 struct ifmp_ring *ift_br; 349 struct grouptask ift_task; 350 qidx_t ift_size; 351 uint16_t ift_id; 352 struct callout ift_timer; 353 354 if_txsd_vec_t ift_sds; 355 uint8_t ift_qstatus; 356 uint8_t ift_closed; 357 uint8_t ift_update_freq; 358 struct iflib_filter_info ift_filter_info; 359 bus_dma_tag_t ift_desc_tag; 360 bus_dma_tag_t ift_tso_desc_tag; 361 iflib_dma_info_t ift_ifdi; 362 #define MTX_NAME_LEN 16 363 char ift_mtx_name[MTX_NAME_LEN]; 364 char ift_db_mtx_name[MTX_NAME_LEN]; 365 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 366 #ifdef IFLIB_DIAGNOSTICS 367 uint64_t ift_cpu_exec_count[256]; 368 #endif 369 } __aligned(CACHE_LINE_SIZE); 370 371 struct iflib_fl { 372 qidx_t ifl_cidx; 373 qidx_t ifl_pidx; 374 qidx_t ifl_credits; 375 uint8_t ifl_gen; 376 uint8_t ifl_rxd_size; 377 #if MEMORY_LOGGING 378 uint64_t ifl_m_enqueued; 379 uint64_t ifl_m_dequeued; 380 uint64_t ifl_cl_enqueued; 381 uint64_t ifl_cl_dequeued; 382 #endif 383 /* implicit pad */ 384 385 /* constant */ 386 qidx_t ifl_size; 387 uint16_t ifl_buf_size; 388 uint16_t ifl_cltype; 389 uma_zone_t ifl_zone; 390 iflib_rxsd_array_t ifl_sds; 391 iflib_rxq_t ifl_rxq; 392 uint8_t ifl_id; 393 bus_dma_tag_t ifl_desc_tag; 394 iflib_dma_info_t ifl_ifdi; 395 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 396 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 397 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 398 } __aligned(CACHE_LINE_SIZE); 399 400 static inline qidx_t 401 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 402 { 403 qidx_t used; 404 405 if (pidx > cidx) 406 used = pidx - cidx; 407 else if (pidx < cidx) 408 used = size - cidx + pidx; 409 else if (gen == 0 && pidx == cidx) 410 used = 0; 411 else if (gen == 1 && pidx == cidx) 412 used = size; 413 else 414 panic("bad state"); 415 416 return (used); 417 } 418 419 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 420 421 #define IDXDIFF(head, tail, wrap) \ 422 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 423 424 struct iflib_rxq { 425 /* If there is a separate completion queue - 426 * these are the cq cidx and pidx. Otherwise 427 * these are unused. 428 */ 429 qidx_t ifr_size; 430 qidx_t ifr_cq_cidx; 431 qidx_t ifr_cq_pidx; 432 uint8_t ifr_cq_gen; 433 uint8_t ifr_fl_offset; 434 435 if_ctx_t ifr_ctx; 436 iflib_fl_t ifr_fl; 437 uint64_t ifr_rx_irq; 438 uint16_t ifr_id; 439 uint8_t ifr_lro_enabled; 440 uint8_t ifr_nfl; 441 uint8_t ifr_ntxqirq; 442 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 443 struct lro_ctrl ifr_lc; 444 struct grouptask ifr_task; 445 struct iflib_filter_info ifr_filter_info; 446 iflib_dma_info_t ifr_ifdi; 447 448 /* dynamically allocate if any drivers need a value substantially larger than this */ 449 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 450 #ifdef IFLIB_DIAGNOSTICS 451 uint64_t ifr_cpu_exec_count[256]; 452 #endif 453 } __aligned(CACHE_LINE_SIZE); 454 455 typedef struct if_rxsd { 456 caddr_t *ifsd_cl; 457 struct mbuf **ifsd_m; 458 iflib_fl_t ifsd_fl; 459 qidx_t ifsd_cidx; 460 } *if_rxsd_t; 461 462 /* multiple of word size */ 463 #ifdef __LP64__ 464 #define PKT_INFO_SIZE 6 465 #define RXD_INFO_SIZE 5 466 #define PKT_TYPE uint64_t 467 #else 468 #define PKT_INFO_SIZE 11 469 #define RXD_INFO_SIZE 8 470 #define PKT_TYPE uint32_t 471 #endif 472 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 473 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 474 475 typedef struct if_pkt_info_pad { 476 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 477 } *if_pkt_info_pad_t; 478 typedef struct if_rxd_info_pad { 479 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 480 } *if_rxd_info_pad_t; 481 482 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 483 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 484 485 486 static inline void 487 pkt_info_zero(if_pkt_info_t pi) 488 { 489 if_pkt_info_pad_t pi_pad; 490 491 pi_pad = (if_pkt_info_pad_t)pi; 492 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 493 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 494 #ifndef __LP64__ 495 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 496 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 497 #endif 498 } 499 500 static inline void 501 rxd_info_zero(if_rxd_info_t ri) 502 { 503 if_rxd_info_pad_t ri_pad; 504 int i; 505 506 ri_pad = (if_rxd_info_pad_t)ri; 507 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 508 ri_pad->rxd_val[i] = 0; 509 ri_pad->rxd_val[i+1] = 0; 510 ri_pad->rxd_val[i+2] = 0; 511 ri_pad->rxd_val[i+3] = 0; 512 } 513 #ifdef __LP64__ 514 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 515 #endif 516 } 517 518 /* 519 * Only allow a single packet to take up most 1/nth of the tx ring 520 */ 521 #define MAX_SINGLE_PACKET_FRACTION 12 522 #define IF_BAD_DMA (bus_addr_t)-1 523 524 static int enable_msix = 1; 525 526 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 527 528 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF) 529 530 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx) 531 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx) 532 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx) 533 534 535 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 536 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 537 538 539 /* Our boot-time initialization hook */ 540 static int iflib_module_event_handler(module_t, int, void *); 541 542 static moduledata_t iflib_moduledata = { 543 "iflib", 544 iflib_module_event_handler, 545 NULL 546 }; 547 548 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 549 MODULE_VERSION(iflib, 1); 550 551 MODULE_DEPEND(iflib, pci, 1, 1, 1); 552 MODULE_DEPEND(iflib, ether, 1, 1, 1); 553 554 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 555 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 556 557 #ifndef IFLIB_DEBUG_COUNTERS 558 #ifdef INVARIANTS 559 #define IFLIB_DEBUG_COUNTERS 1 560 #else 561 #define IFLIB_DEBUG_COUNTERS 0 562 #endif /* !INVARIANTS */ 563 #endif 564 565 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 566 "iflib driver parameters"); 567 568 /* 569 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 570 */ 571 static int iflib_min_tx_latency = 0; 572 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 573 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 574 static int iflib_no_tx_batch = 0; 575 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 576 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 577 578 579 #if IFLIB_DEBUG_COUNTERS 580 581 static int iflib_tx_seen; 582 static int iflib_tx_sent; 583 static int iflib_tx_encap; 584 static int iflib_rx_allocs; 585 static int iflib_fl_refills; 586 static int iflib_fl_refills_large; 587 static int iflib_tx_frees; 588 589 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 590 &iflib_tx_seen, 0, "# tx mbufs seen"); 591 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 592 &iflib_tx_sent, 0, "# tx mbufs sent"); 593 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 594 &iflib_tx_encap, 0, "# tx mbufs encapped"); 595 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 596 &iflib_tx_frees, 0, "# tx frees"); 597 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 598 &iflib_rx_allocs, 0, "# rx allocations"); 599 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 600 &iflib_fl_refills, 0, "# refills"); 601 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 602 &iflib_fl_refills_large, 0, "# large refills"); 603 604 605 static int iflib_txq_drain_flushing; 606 static int iflib_txq_drain_oactive; 607 static int iflib_txq_drain_notready; 608 static int iflib_txq_drain_encapfail; 609 610 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 611 &iflib_txq_drain_flushing, 0, "# drain flushes"); 612 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 613 &iflib_txq_drain_oactive, 0, "# drain oactives"); 614 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 615 &iflib_txq_drain_notready, 0, "# drain notready"); 616 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 617 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 618 619 620 static int iflib_encap_load_mbuf_fail; 621 static int iflib_encap_txq_avail_fail; 622 static int iflib_encap_txd_encap_fail; 623 624 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 625 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 626 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 627 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 628 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 629 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 630 631 static int iflib_task_fn_rxs; 632 static int iflib_rx_intr_enables; 633 static int iflib_fast_intrs; 634 static int iflib_intr_link; 635 static int iflib_intr_msix; 636 static int iflib_rx_unavail; 637 static int iflib_rx_ctx_inactive; 638 static int iflib_rx_zero_len; 639 static int iflib_rx_if_input; 640 static int iflib_rx_mbuf_null; 641 static int iflib_rxd_flush; 642 643 static int iflib_verbose_debug; 644 645 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 646 &iflib_intr_link, 0, "# intr link calls"); 647 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 648 &iflib_intr_msix, 0, "# intr msix calls"); 649 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 650 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 651 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 652 &iflib_rx_intr_enables, 0, "# rx intr enables"); 653 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 654 &iflib_fast_intrs, 0, "# fast_intr calls"); 655 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 656 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 657 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 658 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 660 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 662 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 664 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 666 &iflib_rxd_flush, 0, "# times rxd_flush called"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 668 &iflib_verbose_debug, 0, "enable verbose debugging"); 669 670 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 671 static void 672 iflib_debug_reset(void) 673 { 674 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 675 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 676 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 677 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 678 iflib_encap_load_mbuf_fail = iflib_encap_txq_avail_fail = 679 iflib_encap_txd_encap_fail = iflib_task_fn_rxs = iflib_rx_intr_enables = 680 iflib_fast_intrs = iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 681 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 682 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 683 } 684 685 #else 686 #define DBG_COUNTER_INC(name) 687 static void iflib_debug_reset(void) {} 688 #endif 689 690 691 692 #define IFLIB_DEBUG 0 693 694 static void iflib_tx_structures_free(if_ctx_t ctx); 695 static void iflib_rx_structures_free(if_ctx_t ctx); 696 static int iflib_queues_alloc(if_ctx_t ctx); 697 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 698 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 699 static int iflib_qset_structures_setup(if_ctx_t ctx); 700 static int iflib_msix_init(if_ctx_t ctx); 701 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str); 702 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 703 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 704 static int iflib_register(if_ctx_t); 705 static void iflib_init_locked(if_ctx_t ctx); 706 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 707 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 708 static void iflib_ifmp_purge(iflib_txq_t txq); 709 static void _iflib_pre_assert(if_softc_ctx_t scctx); 710 static void iflib_stop(if_ctx_t ctx); 711 static void iflib_if_init_locked(if_ctx_t ctx); 712 #ifndef __NO_STRICT_ALIGNMENT 713 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 714 #endif 715 716 #ifdef DEV_NETMAP 717 #include <sys/selinfo.h> 718 #include <net/netmap.h> 719 #include <dev/netmap/netmap_kern.h> 720 721 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 722 723 /* 724 * device-specific sysctl variables: 725 * 726 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 727 * During regular operations the CRC is stripped, but on some 728 * hardware reception of frames not multiple of 64 is slower, 729 * so using crcstrip=0 helps in benchmarks. 730 * 731 * iflib_rx_miss, iflib_rx_miss_bufs: 732 * count packets that might be missed due to lost interrupts. 733 */ 734 SYSCTL_DECL(_dev_netmap); 735 /* 736 * The xl driver by default strips CRCs and we do not override it. 737 */ 738 739 int iflib_crcstrip = 1; 740 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 741 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 742 743 int iflib_rx_miss, iflib_rx_miss_bufs; 744 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 745 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 746 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 747 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 748 749 /* 750 * Register/unregister. We are already under netmap lock. 751 * Only called on the first register or the last unregister. 752 */ 753 static int 754 iflib_netmap_register(struct netmap_adapter *na, int onoff) 755 { 756 struct ifnet *ifp = na->ifp; 757 if_ctx_t ctx = ifp->if_softc; 758 int status; 759 760 CTX_LOCK(ctx); 761 IFDI_INTR_DISABLE(ctx); 762 763 /* Tell the stack that the interface is no longer active */ 764 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 765 766 if (!CTX_IS_VF(ctx)) 767 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 768 769 /* enable or disable flags and callbacks in na and ifp */ 770 if (onoff) { 771 nm_set_native_flags(na); 772 } else { 773 nm_clear_native_flags(na); 774 } 775 iflib_stop(ctx); 776 iflib_init_locked(ctx); 777 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 778 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 779 if (status) 780 nm_clear_native_flags(na); 781 CTX_UNLOCK(ctx); 782 return (status); 783 } 784 785 /* 786 * Reconcile kernel and user view of the transmit ring. 787 * 788 * All information is in the kring. 789 * Userspace wants to send packets up to the one before kring->rhead, 790 * kernel knows kring->nr_hwcur is the first unsent packet. 791 * 792 * Here we push packets out (as many as possible), and possibly 793 * reclaim buffers from previously completed transmission. 794 * 795 * The caller (netmap) guarantees that there is only one instance 796 * running at any time. Any interference with other driver 797 * methods should be handled by the individual drivers. 798 */ 799 static int 800 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 801 { 802 struct netmap_adapter *na = kring->na; 803 struct ifnet *ifp = na->ifp; 804 struct netmap_ring *ring = kring->ring; 805 u_int nm_i; /* index into the netmap ring */ 806 u_int nic_i; /* index into the NIC ring */ 807 u_int n; 808 u_int const lim = kring->nkr_num_slots - 1; 809 u_int const head = kring->rhead; 810 struct if_pkt_info pi; 811 812 /* 813 * interrupts on every tx packet are expensive so request 814 * them every half ring, or where NS_REPORT is set 815 */ 816 u_int report_frequency = kring->nkr_num_slots >> 1; 817 /* device-specific */ 818 if_ctx_t ctx = ifp->if_softc; 819 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 820 821 if (txq->ift_sds.ifsd_map) 822 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 823 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 824 825 826 /* 827 * First part: process new packets to send. 828 * nm_i is the current index in the netmap ring, 829 * nic_i is the corresponding index in the NIC ring. 830 * 831 * If we have packets to send (nm_i != head) 832 * iterate over the netmap ring, fetch length and update 833 * the corresponding slot in the NIC ring. Some drivers also 834 * need to update the buffer's physical address in the NIC slot 835 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 836 * 837 * The netmap_reload_map() calls is especially expensive, 838 * even when (as in this case) the tag is 0, so do only 839 * when the buffer has actually changed. 840 * 841 * If possible do not set the report/intr bit on all slots, 842 * but only a few times per ring or when NS_REPORT is set. 843 * 844 * Finally, on 10G and faster drivers, it might be useful 845 * to prefetch the next slot and txr entry. 846 */ 847 848 nm_i = kring->nr_hwcur; 849 pkt_info_zero(&pi); 850 pi.ipi_segs = txq->ift_segs; 851 pi.ipi_qsidx = kring->ring_id; 852 if (nm_i != head) { /* we have new packets to send */ 853 nic_i = netmap_idx_k2n(kring, nm_i); 854 855 __builtin_prefetch(&ring->slot[nm_i]); 856 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 857 if (txq->ift_sds.ifsd_map) 858 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 859 860 for (n = 0; nm_i != head; n++) { 861 struct netmap_slot *slot = &ring->slot[nm_i]; 862 u_int len = slot->len; 863 uint64_t paddr; 864 void *addr = PNMB(na, slot, &paddr); 865 int flags = (slot->flags & NS_REPORT || 866 nic_i == 0 || nic_i == report_frequency) ? 867 IPI_TX_INTR : 0; 868 869 /* device-specific */ 870 pi.ipi_len = len; 871 pi.ipi_segs[0].ds_addr = paddr; 872 pi.ipi_segs[0].ds_len = len; 873 pi.ipi_nsegs = 1; 874 pi.ipi_ndescs = 0; 875 pi.ipi_pidx = nic_i; 876 pi.ipi_flags = flags; 877 878 /* Fill the slot in the NIC ring. */ 879 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 880 881 /* prefetch for next round */ 882 __builtin_prefetch(&ring->slot[nm_i + 1]); 883 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 884 if (txq->ift_sds.ifsd_map) { 885 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 886 887 NM_CHECK_ADDR_LEN(na, addr, len); 888 889 if (slot->flags & NS_BUF_CHANGED) { 890 /* buffer has changed, reload map */ 891 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 892 } 893 /* make sure changes to the buffer are synced */ 894 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 895 BUS_DMASYNC_PREWRITE); 896 } 897 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 898 nm_i = nm_next(nm_i, lim); 899 nic_i = nm_next(nic_i, lim); 900 } 901 kring->nr_hwcur = head; 902 903 /* synchronize the NIC ring */ 904 if (txq->ift_sds.ifsd_map) 905 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 906 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 907 908 /* (re)start the tx unit up to slot nic_i (excluded) */ 909 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 910 } 911 912 /* 913 * Second part: reclaim buffers for completed transmissions. 914 */ 915 if (iflib_tx_credits_update(ctx, txq)) { 916 /* some tx completed, increment avail */ 917 nic_i = txq->ift_cidx_processed; 918 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 919 } 920 return (0); 921 } 922 923 /* 924 * Reconcile kernel and user view of the receive ring. 925 * Same as for the txsync, this routine must be efficient. 926 * The caller guarantees a single invocations, but races against 927 * the rest of the driver should be handled here. 928 * 929 * On call, kring->rhead is the first packet that userspace wants 930 * to keep, and kring->rcur is the wakeup point. 931 * The kernel has previously reported packets up to kring->rtail. 932 * 933 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 934 * of whether or not we received an interrupt. 935 */ 936 static int 937 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 938 { 939 struct netmap_adapter *na = kring->na; 940 struct netmap_ring *ring = kring->ring; 941 uint32_t nm_i; /* index into the netmap ring */ 942 uint32_t nic_i, nic_i_start; /* index into the NIC ring */ 943 u_int i, n; 944 u_int const lim = kring->nkr_num_slots - 1; 945 u_int const head = kring->rhead; 946 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 947 struct if_rxd_info ri; 948 struct if_rxd_update iru; 949 950 struct ifnet *ifp = na->ifp; 951 if_ctx_t ctx = ifp->if_softc; 952 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 953 iflib_fl_t fl = rxq->ifr_fl; 954 if (head > lim) 955 return netmap_ring_reinit(kring); 956 957 /* XXX check sync modes */ 958 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 959 if (fl->ifl_sds.ifsd_map == NULL) 960 continue; 961 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 962 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 963 } 964 /* 965 * First part: import newly received packets. 966 * 967 * nm_i is the index of the next free slot in the netmap ring, 968 * nic_i is the index of the next received packet in the NIC ring, 969 * and they may differ in case if_init() has been called while 970 * in netmap mode. For the receive ring we have 971 * 972 * nic_i = rxr->next_check; 973 * nm_i = kring->nr_hwtail (previous) 974 * and 975 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 976 * 977 * rxr->next_check is set to 0 on a ring reinit 978 */ 979 if (netmap_no_pendintr || force_update) { 980 int crclen = iflib_crcstrip ? 0 : 4; 981 int error, avail; 982 uint16_t slot_flags = kring->nkr_slot_flags; 983 984 for (fl = rxq->ifr_fl, i = 0; i < rxq->ifr_nfl; i++, fl++) { 985 nic_i = fl->ifl_cidx; 986 nm_i = netmap_idx_n2k(kring, nic_i); 987 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 988 for (n = 0; avail > 0; n++, avail--) { 989 rxd_info_zero(&ri); 990 ri.iri_frags = rxq->ifr_frags; 991 ri.iri_qsidx = kring->ring_id; 992 ri.iri_ifp = ctx->ifc_ifp; 993 ri.iri_cidx = nic_i; 994 995 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 996 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 997 ring->slot[nm_i].flags = slot_flags; 998 if (fl->ifl_sds.ifsd_map) 999 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1000 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1001 nm_i = nm_next(nm_i, lim); 1002 nic_i = nm_next(nic_i, lim); 1003 } 1004 if (n) { /* update the state variables */ 1005 if (netmap_no_pendintr && !force_update) { 1006 /* diagnostics */ 1007 iflib_rx_miss ++; 1008 iflib_rx_miss_bufs += n; 1009 } 1010 fl->ifl_cidx = nic_i; 1011 kring->nr_hwtail = nm_i; 1012 } 1013 kring->nr_kflags &= ~NKR_PENDINTR; 1014 } 1015 } 1016 /* 1017 * Second part: skip past packets that userspace has released. 1018 * (kring->nr_hwcur to head excluded), 1019 * and make the buffers available for reception. 1020 * As usual nm_i is the index in the netmap ring, 1021 * nic_i is the index in the NIC ring, and 1022 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1023 */ 1024 /* XXX not sure how this will work with multiple free lists */ 1025 nm_i = kring->nr_hwcur; 1026 if (nm_i == head) 1027 return (0); 1028 1029 iru.iru_paddrs = fl->ifl_bus_addrs; 1030 iru.iru_vaddrs = &fl->ifl_vm_addrs[0]; 1031 iru.iru_idxs = fl->ifl_rxd_idxs; 1032 iru.iru_qsidx = rxq->ifr_id; 1033 iru.iru_buf_size = fl->ifl_buf_size; 1034 iru.iru_flidx = fl->ifl_id; 1035 nic_i_start = nic_i = netmap_idx_k2n(kring, nm_i); 1036 for (i = 0; nm_i != head; i++) { 1037 struct netmap_slot *slot = &ring->slot[nm_i]; 1038 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]); 1039 1040 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 1041 goto ring_reset; 1042 1043 fl->ifl_vm_addrs[i] = addr; 1044 if (fl->ifl_sds.ifsd_map && (slot->flags & NS_BUF_CHANGED)) { 1045 /* buffer has changed, reload map */ 1046 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i], addr); 1047 } 1048 slot->flags &= ~NS_BUF_CHANGED; 1049 1050 nm_i = nm_next(nm_i, lim); 1051 fl->ifl_rxd_idxs[i] = nic_i = nm_next(nic_i, lim); 1052 if (nm_i != head && i < IFLIB_MAX_RX_REFRESH) 1053 continue; 1054 1055 iru.iru_pidx = nic_i_start; 1056 iru.iru_count = i; 1057 i = 0; 1058 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1059 if (fl->ifl_sds.ifsd_map == NULL) { 1060 nic_i_start = nic_i; 1061 continue; 1062 } 1063 nic_i = nic_i_start; 1064 for (n = 0; n < iru.iru_count; n++) { 1065 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i], 1066 BUS_DMASYNC_PREREAD); 1067 nic_i = nm_next(nic_i, lim); 1068 } 1069 nic_i_start = nic_i; 1070 } 1071 kring->nr_hwcur = head; 1072 1073 if (fl->ifl_sds.ifsd_map) 1074 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1075 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1076 /* 1077 * IMPORTANT: we must leave one free slot in the ring, 1078 * so move nic_i back by one unit 1079 */ 1080 nic_i = nm_prev(nic_i, lim); 1081 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 1082 return 0; 1083 1084 ring_reset: 1085 return netmap_ring_reinit(kring); 1086 } 1087 1088 static void 1089 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1090 { 1091 struct ifnet *ifp = na->ifp; 1092 if_ctx_t ctx = ifp->if_softc; 1093 1094 CTX_LOCK(ctx); 1095 if (onoff) { 1096 IFDI_INTR_ENABLE(ctx); 1097 } else { 1098 IFDI_INTR_DISABLE(ctx); 1099 } 1100 CTX_UNLOCK(ctx); 1101 } 1102 1103 1104 static int 1105 iflib_netmap_attach(if_ctx_t ctx) 1106 { 1107 struct netmap_adapter na; 1108 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1109 1110 bzero(&na, sizeof(na)); 1111 1112 na.ifp = ctx->ifc_ifp; 1113 na.na_flags = NAF_BDG_MAYSLEEP; 1114 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1115 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1116 1117 na.num_tx_desc = scctx->isc_ntxd[0]; 1118 na.num_rx_desc = scctx->isc_nrxd[0]; 1119 na.nm_txsync = iflib_netmap_txsync; 1120 na.nm_rxsync = iflib_netmap_rxsync; 1121 na.nm_register = iflib_netmap_register; 1122 na.nm_intr = iflib_netmap_intr; 1123 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1124 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1125 return (netmap_attach(&na)); 1126 } 1127 1128 static void 1129 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1130 { 1131 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1132 struct netmap_slot *slot; 1133 1134 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1135 if (slot == NULL) 1136 return; 1137 if (txq->ift_sds.ifsd_map == NULL) 1138 return; 1139 1140 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1141 1142 /* 1143 * In netmap mode, set the map for the packet buffer. 1144 * NOTE: Some drivers (not this one) also need to set 1145 * the physical buffer address in the NIC ring. 1146 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1147 * netmap slot index, si 1148 */ 1149 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i); 1150 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1151 } 1152 } 1153 static void 1154 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1155 { 1156 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1157 struct netmap_slot *slot; 1158 struct if_rxd_update iru; 1159 iflib_fl_t fl; 1160 bus_dmamap_t *map; 1161 int nrxd; 1162 uint32_t i, j, pidx_start; 1163 1164 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1165 if (slot == NULL) 1166 return; 1167 fl = &rxq->ifr_fl[0]; 1168 map = fl->ifl_sds.ifsd_map; 1169 nrxd = ctx->ifc_softc_ctx.isc_nrxd[0]; 1170 iru.iru_paddrs = fl->ifl_bus_addrs; 1171 iru.iru_vaddrs = &fl->ifl_vm_addrs[0]; 1172 iru.iru_idxs = fl->ifl_rxd_idxs; 1173 iru.iru_qsidx = rxq->ifr_id; 1174 iru.iru_buf_size = rxq->ifr_fl[0].ifl_buf_size; 1175 iru.iru_flidx = 0; 1176 1177 for (pidx_start = i = j = 0; i < nrxd; i++, j++) { 1178 int sj = netmap_idx_n2k(&na->rx_rings[rxq->ifr_id], i); 1179 void *addr; 1180 1181 fl->ifl_rxd_idxs[j] = i; 1182 addr = fl->ifl_vm_addrs[j] = PNMB(na, slot + sj, &fl->ifl_bus_addrs[j]); 1183 if (map) { 1184 netmap_load_map(na, rxq->ifr_fl[0].ifl_ifdi->idi_tag, *map, addr); 1185 map++; 1186 } 1187 1188 if (j < IFLIB_MAX_RX_REFRESH && i < nrxd - 1) 1189 continue; 1190 1191 iru.iru_pidx = pidx_start; 1192 pidx_start = i; 1193 iru.iru_count = j; 1194 j = 0; 1195 MPASS(pidx_start + j <= nrxd); 1196 /* Update descriptors and the cached value */ 1197 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1198 } 1199 /* preserve queue */ 1200 if (ctx->ifc_ifp->if_capenable & IFCAP_NETMAP) { 1201 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id]; 1202 int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring); 1203 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, t); 1204 } else 1205 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, nrxd-1); 1206 } 1207 1208 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1209 1210 #else 1211 #define iflib_netmap_txq_init(ctx, txq) 1212 #define iflib_netmap_rxq_init(ctx, rxq) 1213 #define iflib_netmap_detach(ifp) 1214 1215 #define iflib_netmap_attach(ctx) (0) 1216 #define netmap_rx_irq(ifp, qid, budget) (0) 1217 #define netmap_tx_irq(ifp, qid) do {} while (0) 1218 1219 #endif 1220 1221 #if defined(__i386__) || defined(__amd64__) 1222 static __inline void 1223 prefetch(void *x) 1224 { 1225 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1226 } 1227 #else 1228 #define prefetch(x) 1229 #endif 1230 1231 static void 1232 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1233 { 1234 if (err) 1235 return; 1236 *(bus_addr_t *) arg = segs[0].ds_addr; 1237 } 1238 1239 int 1240 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1241 { 1242 int err; 1243 if_shared_ctx_t sctx = ctx->ifc_sctx; 1244 device_t dev = ctx->ifc_dev; 1245 1246 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1247 1248 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1249 sctx->isc_q_align, 0, /* alignment, bounds */ 1250 BUS_SPACE_MAXADDR, /* lowaddr */ 1251 BUS_SPACE_MAXADDR, /* highaddr */ 1252 NULL, NULL, /* filter, filterarg */ 1253 size, /* maxsize */ 1254 1, /* nsegments */ 1255 size, /* maxsegsize */ 1256 BUS_DMA_ALLOCNOW, /* flags */ 1257 NULL, /* lockfunc */ 1258 NULL, /* lockarg */ 1259 &dma->idi_tag); 1260 if (err) { 1261 device_printf(dev, 1262 "%s: bus_dma_tag_create failed: %d\n", 1263 __func__, err); 1264 goto fail_0; 1265 } 1266 1267 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1268 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1269 if (err) { 1270 device_printf(dev, 1271 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1272 __func__, (uintmax_t)size, err); 1273 goto fail_1; 1274 } 1275 1276 dma->idi_paddr = IF_BAD_DMA; 1277 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1278 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1279 if (err || dma->idi_paddr == IF_BAD_DMA) { 1280 device_printf(dev, 1281 "%s: bus_dmamap_load failed: %d\n", 1282 __func__, err); 1283 goto fail_2; 1284 } 1285 1286 dma->idi_size = size; 1287 return (0); 1288 1289 fail_2: 1290 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1291 fail_1: 1292 bus_dma_tag_destroy(dma->idi_tag); 1293 fail_0: 1294 dma->idi_tag = NULL; 1295 1296 return (err); 1297 } 1298 1299 int 1300 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1301 { 1302 int i, err; 1303 iflib_dma_info_t *dmaiter; 1304 1305 dmaiter = dmalist; 1306 for (i = 0; i < count; i++, dmaiter++) { 1307 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1308 break; 1309 } 1310 if (err) 1311 iflib_dma_free_multi(dmalist, i); 1312 return (err); 1313 } 1314 1315 void 1316 iflib_dma_free(iflib_dma_info_t dma) 1317 { 1318 if (dma->idi_tag == NULL) 1319 return; 1320 if (dma->idi_paddr != IF_BAD_DMA) { 1321 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1322 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1323 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1324 dma->idi_paddr = IF_BAD_DMA; 1325 } 1326 if (dma->idi_vaddr != NULL) { 1327 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1328 dma->idi_vaddr = NULL; 1329 } 1330 bus_dma_tag_destroy(dma->idi_tag); 1331 dma->idi_tag = NULL; 1332 } 1333 1334 void 1335 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1336 { 1337 int i; 1338 iflib_dma_info_t *dmaiter = dmalist; 1339 1340 for (i = 0; i < count; i++, dmaiter++) 1341 iflib_dma_free(*dmaiter); 1342 } 1343 1344 #ifdef EARLY_AP_STARTUP 1345 static const int iflib_started = 1; 1346 #else 1347 /* 1348 * We used to abuse the smp_started flag to decide if the queues have been 1349 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1350 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1351 * is set. Run a SYSINIT() strictly after that to just set a usable 1352 * completion flag. 1353 */ 1354 1355 static int iflib_started; 1356 1357 static void 1358 iflib_record_started(void *arg) 1359 { 1360 iflib_started = 1; 1361 } 1362 1363 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1364 iflib_record_started, NULL); 1365 #endif 1366 1367 static int 1368 iflib_fast_intr(void *arg) 1369 { 1370 iflib_filter_info_t info = arg; 1371 struct grouptask *gtask = info->ifi_task; 1372 if (!iflib_started) 1373 return (FILTER_HANDLED); 1374 1375 DBG_COUNTER_INC(fast_intrs); 1376 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1377 return (FILTER_HANDLED); 1378 1379 GROUPTASK_ENQUEUE(gtask); 1380 return (FILTER_HANDLED); 1381 } 1382 1383 static int 1384 iflib_fast_intr_rxtx(void *arg) 1385 { 1386 iflib_filter_info_t info = arg; 1387 struct grouptask *gtask = info->ifi_task; 1388 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1389 if_ctx_t ctx; 1390 int i, cidx; 1391 1392 if (!iflib_started) 1393 return (FILTER_HANDLED); 1394 1395 DBG_COUNTER_INC(fast_intrs); 1396 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1397 return (FILTER_HANDLED); 1398 1399 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1400 qidx_t txqid = rxq->ifr_txqid[i]; 1401 1402 ctx = rxq->ifr_ctx; 1403 1404 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1405 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1406 continue; 1407 } 1408 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1409 } 1410 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1411 cidx = rxq->ifr_cq_cidx; 1412 else 1413 cidx = rxq->ifr_fl[0].ifl_cidx; 1414 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1415 GROUPTASK_ENQUEUE(gtask); 1416 else 1417 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1418 return (FILTER_HANDLED); 1419 } 1420 1421 1422 static int 1423 iflib_fast_intr_ctx(void *arg) 1424 { 1425 iflib_filter_info_t info = arg; 1426 struct grouptask *gtask = info->ifi_task; 1427 1428 if (!iflib_started) 1429 return (FILTER_HANDLED); 1430 1431 DBG_COUNTER_INC(fast_intrs); 1432 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1433 return (FILTER_HANDLED); 1434 1435 GROUPTASK_ENQUEUE(gtask); 1436 return (FILTER_HANDLED); 1437 } 1438 1439 static int 1440 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1441 driver_filter_t filter, driver_intr_t handler, void *arg, 1442 char *name) 1443 { 1444 int rc, flags; 1445 struct resource *res; 1446 void *tag = NULL; 1447 device_t dev = ctx->ifc_dev; 1448 1449 flags = RF_ACTIVE; 1450 if (ctx->ifc_flags & IFC_LEGACY) 1451 flags |= RF_SHAREABLE; 1452 MPASS(rid < 512); 1453 irq->ii_rid = rid; 1454 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1455 if (res == NULL) { 1456 device_printf(dev, 1457 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1458 return (ENOMEM); 1459 } 1460 irq->ii_res = res; 1461 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1462 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1463 filter, handler, arg, &tag); 1464 if (rc != 0) { 1465 device_printf(dev, 1466 "failed to setup interrupt for rid %d, name %s: %d\n", 1467 rid, name ? name : "unknown", rc); 1468 return (rc); 1469 } else if (name) 1470 bus_describe_intr(dev, res, tag, "%s", name); 1471 1472 irq->ii_tag = tag; 1473 return (0); 1474 } 1475 1476 1477 /********************************************************************* 1478 * 1479 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1480 * the information needed to transmit a packet on the wire. This is 1481 * called only once at attach, setup is done every reset. 1482 * 1483 **********************************************************************/ 1484 1485 static int 1486 iflib_txsd_alloc(iflib_txq_t txq) 1487 { 1488 if_ctx_t ctx = txq->ift_ctx; 1489 if_shared_ctx_t sctx = ctx->ifc_sctx; 1490 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1491 device_t dev = ctx->ifc_dev; 1492 int err, nsegments, ntsosegments; 1493 1494 nsegments = scctx->isc_tx_nsegments; 1495 ntsosegments = scctx->isc_tx_tso_segments_max; 1496 MPASS(scctx->isc_ntxd[0] > 0); 1497 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1498 MPASS(nsegments > 0); 1499 MPASS(ntsosegments > 0); 1500 /* 1501 * Setup DMA descriptor areas. 1502 */ 1503 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1504 1, 0, /* alignment, bounds */ 1505 BUS_SPACE_MAXADDR, /* lowaddr */ 1506 BUS_SPACE_MAXADDR, /* highaddr */ 1507 NULL, NULL, /* filter, filterarg */ 1508 sctx->isc_tx_maxsize, /* maxsize */ 1509 nsegments, /* nsegments */ 1510 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1511 0, /* flags */ 1512 NULL, /* lockfunc */ 1513 NULL, /* lockfuncarg */ 1514 &txq->ift_desc_tag))) { 1515 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1516 device_printf(dev,"maxsize: %zd nsegments: %d maxsegsize: %zd\n", 1517 sctx->isc_tx_maxsize, nsegments, sctx->isc_tx_maxsegsize); 1518 goto fail; 1519 } 1520 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1521 1, 0, /* alignment, bounds */ 1522 BUS_SPACE_MAXADDR, /* lowaddr */ 1523 BUS_SPACE_MAXADDR, /* highaddr */ 1524 NULL, NULL, /* filter, filterarg */ 1525 scctx->isc_tx_tso_size_max, /* maxsize */ 1526 ntsosegments, /* nsegments */ 1527 scctx->isc_tx_tso_segsize_max, /* maxsegsize */ 1528 0, /* flags */ 1529 NULL, /* lockfunc */ 1530 NULL, /* lockfuncarg */ 1531 &txq->ift_tso_desc_tag))) { 1532 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1533 1534 goto fail; 1535 } 1536 if (!(txq->ift_sds.ifsd_flags = 1537 (uint8_t *) malloc(sizeof(uint8_t) * 1538 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1539 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1540 err = ENOMEM; 1541 goto fail; 1542 } 1543 if (!(txq->ift_sds.ifsd_m = 1544 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1545 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1546 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1547 err = ENOMEM; 1548 goto fail; 1549 } 1550 1551 /* Create the descriptor buffer dma maps */ 1552 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1553 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1554 return (0); 1555 1556 if (!(txq->ift_sds.ifsd_map = 1557 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1558 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1559 err = ENOMEM; 1560 goto fail; 1561 } 1562 1563 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1564 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1565 if (err != 0) { 1566 device_printf(dev, "Unable to create TX DMA map\n"); 1567 goto fail; 1568 } 1569 } 1570 #endif 1571 return (0); 1572 fail: 1573 /* We free all, it handles case where we are in the middle */ 1574 iflib_tx_structures_free(ctx); 1575 return (err); 1576 } 1577 1578 static void 1579 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1580 { 1581 bus_dmamap_t map; 1582 1583 map = NULL; 1584 if (txq->ift_sds.ifsd_map != NULL) 1585 map = txq->ift_sds.ifsd_map[i]; 1586 if (map != NULL) { 1587 bus_dmamap_unload(txq->ift_desc_tag, map); 1588 bus_dmamap_destroy(txq->ift_desc_tag, map); 1589 txq->ift_sds.ifsd_map[i] = NULL; 1590 } 1591 } 1592 1593 static void 1594 iflib_txq_destroy(iflib_txq_t txq) 1595 { 1596 if_ctx_t ctx = txq->ift_ctx; 1597 1598 for (int i = 0; i < txq->ift_size; i++) 1599 iflib_txsd_destroy(ctx, txq, i); 1600 if (txq->ift_sds.ifsd_map != NULL) { 1601 free(txq->ift_sds.ifsd_map, M_IFLIB); 1602 txq->ift_sds.ifsd_map = NULL; 1603 } 1604 if (txq->ift_sds.ifsd_m != NULL) { 1605 free(txq->ift_sds.ifsd_m, M_IFLIB); 1606 txq->ift_sds.ifsd_m = NULL; 1607 } 1608 if (txq->ift_sds.ifsd_flags != NULL) { 1609 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1610 txq->ift_sds.ifsd_flags = NULL; 1611 } 1612 if (txq->ift_desc_tag != NULL) { 1613 bus_dma_tag_destroy(txq->ift_desc_tag); 1614 txq->ift_desc_tag = NULL; 1615 } 1616 if (txq->ift_tso_desc_tag != NULL) { 1617 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1618 txq->ift_tso_desc_tag = NULL; 1619 } 1620 } 1621 1622 static void 1623 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1624 { 1625 struct mbuf **mp; 1626 1627 mp = &txq->ift_sds.ifsd_m[i]; 1628 if (*mp == NULL) 1629 return; 1630 1631 if (txq->ift_sds.ifsd_map != NULL) { 1632 bus_dmamap_sync(txq->ift_desc_tag, 1633 txq->ift_sds.ifsd_map[i], 1634 BUS_DMASYNC_POSTWRITE); 1635 bus_dmamap_unload(txq->ift_desc_tag, 1636 txq->ift_sds.ifsd_map[i]); 1637 } 1638 m_free(*mp); 1639 DBG_COUNTER_INC(tx_frees); 1640 *mp = NULL; 1641 } 1642 1643 static int 1644 iflib_txq_setup(iflib_txq_t txq) 1645 { 1646 if_ctx_t ctx = txq->ift_ctx; 1647 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1648 iflib_dma_info_t di; 1649 int i; 1650 1651 /* Set number of descriptors available */ 1652 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1653 /* XXX make configurable */ 1654 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1655 1656 /* Reset indices */ 1657 txq->ift_cidx_processed = 0; 1658 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1659 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1660 1661 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1662 bzero((void *)di->idi_vaddr, di->idi_size); 1663 1664 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1665 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1666 bus_dmamap_sync(di->idi_tag, di->idi_map, 1667 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1668 return (0); 1669 } 1670 1671 /********************************************************************* 1672 * 1673 * Allocate memory for rx_buffer structures. Since we use one 1674 * rx_buffer per received packet, the maximum number of rx_buffer's 1675 * that we'll need is equal to the number of receive descriptors 1676 * that we've allocated. 1677 * 1678 **********************************************************************/ 1679 static int 1680 iflib_rxsd_alloc(iflib_rxq_t rxq) 1681 { 1682 if_ctx_t ctx = rxq->ifr_ctx; 1683 if_shared_ctx_t sctx = ctx->ifc_sctx; 1684 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1685 device_t dev = ctx->ifc_dev; 1686 iflib_fl_t fl; 1687 int err; 1688 1689 MPASS(scctx->isc_nrxd[0] > 0); 1690 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1691 1692 fl = rxq->ifr_fl; 1693 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1694 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1695 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1696 1, 0, /* alignment, bounds */ 1697 BUS_SPACE_MAXADDR, /* lowaddr */ 1698 BUS_SPACE_MAXADDR, /* highaddr */ 1699 NULL, NULL, /* filter, filterarg */ 1700 sctx->isc_rx_maxsize, /* maxsize */ 1701 sctx->isc_rx_nsegments, /* nsegments */ 1702 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1703 0, /* flags */ 1704 NULL, /* lockfunc */ 1705 NULL, /* lockarg */ 1706 &fl->ifl_desc_tag); 1707 if (err) { 1708 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1709 __func__, err); 1710 goto fail; 1711 } 1712 if (!(fl->ifl_sds.ifsd_flags = 1713 (uint8_t *) malloc(sizeof(uint8_t) * 1714 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1715 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1716 err = ENOMEM; 1717 goto fail; 1718 } 1719 if (!(fl->ifl_sds.ifsd_m = 1720 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1721 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1722 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1723 err = ENOMEM; 1724 goto fail; 1725 } 1726 if (!(fl->ifl_sds.ifsd_cl = 1727 (caddr_t *) malloc(sizeof(caddr_t) * 1728 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1729 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1730 err = ENOMEM; 1731 goto fail; 1732 } 1733 1734 /* Create the descriptor buffer dma maps */ 1735 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1736 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1737 continue; 1738 1739 if (!(fl->ifl_sds.ifsd_map = 1740 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1741 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1742 err = ENOMEM; 1743 goto fail; 1744 } 1745 1746 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1747 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1748 if (err != 0) { 1749 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1750 goto fail; 1751 } 1752 } 1753 #endif 1754 } 1755 return (0); 1756 1757 fail: 1758 iflib_rx_structures_free(ctx); 1759 return (err); 1760 } 1761 1762 1763 /* 1764 * Internal service routines 1765 */ 1766 1767 struct rxq_refill_cb_arg { 1768 int error; 1769 bus_dma_segment_t seg; 1770 int nseg; 1771 }; 1772 1773 static void 1774 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1775 { 1776 struct rxq_refill_cb_arg *cb_arg = arg; 1777 1778 cb_arg->error = error; 1779 cb_arg->seg = segs[0]; 1780 cb_arg->nseg = nseg; 1781 } 1782 1783 1784 #ifdef ACPI_DMAR 1785 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1786 #else 1787 #define IS_DMAR(ctx) (0) 1788 #endif 1789 1790 /** 1791 * rxq_refill - refill an rxq free-buffer list 1792 * @ctx: the iflib context 1793 * @rxq: the free-list to refill 1794 * @n: the number of new buffers to allocate 1795 * 1796 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1797 * The caller must assure that @n does not exceed the queue's capacity. 1798 */ 1799 static void 1800 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1801 { 1802 struct mbuf *m; 1803 int idx, pidx = fl->ifl_pidx; 1804 caddr_t cl, *sd_cl; 1805 struct mbuf **sd_m; 1806 uint8_t *sd_flags; 1807 struct if_rxd_update iru; 1808 bus_dmamap_t *sd_map; 1809 int n, i = 0; 1810 uint64_t bus_addr; 1811 int err; 1812 1813 sd_m = fl->ifl_sds.ifsd_m; 1814 sd_map = fl->ifl_sds.ifsd_map; 1815 sd_cl = fl->ifl_sds.ifsd_cl; 1816 sd_flags = fl->ifl_sds.ifsd_flags; 1817 idx = pidx; 1818 1819 n = count; 1820 MPASS(n > 0); 1821 MPASS(fl->ifl_credits + n <= fl->ifl_size); 1822 1823 if (pidx < fl->ifl_cidx) 1824 MPASS(pidx + n <= fl->ifl_cidx); 1825 if (pidx == fl->ifl_cidx && (fl->ifl_credits < fl->ifl_size)) 1826 MPASS(fl->ifl_gen == 0); 1827 if (pidx > fl->ifl_cidx) 1828 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1829 1830 DBG_COUNTER_INC(fl_refills); 1831 if (n > 8) 1832 DBG_COUNTER_INC(fl_refills_large); 1833 iru.iru_paddrs = fl->ifl_bus_addrs; 1834 iru.iru_vaddrs = &fl->ifl_vm_addrs[0]; 1835 iru.iru_idxs = fl->ifl_rxd_idxs; 1836 iru.iru_qsidx = fl->ifl_rxq->ifr_id; 1837 iru.iru_buf_size = fl->ifl_buf_size; 1838 iru.iru_flidx = fl->ifl_id; 1839 while (n--) { 1840 /* 1841 * We allocate an uninitialized mbuf + cluster, mbuf is 1842 * initialized after rx. 1843 * 1844 * If the cluster is still set then we know a minimum sized packet was received 1845 */ 1846 if ((cl = sd_cl[idx]) == NULL) { 1847 if ((cl = sd_cl[idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1848 break; 1849 #if MEMORY_LOGGING 1850 fl->ifl_cl_enqueued++; 1851 #endif 1852 } 1853 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1854 break; 1855 } 1856 #if MEMORY_LOGGING 1857 fl->ifl_m_enqueued++; 1858 #endif 1859 1860 DBG_COUNTER_INC(rx_allocs); 1861 #if defined(__i386__) || defined(__amd64__) 1862 if (!IS_DMAR(ctx)) { 1863 bus_addr = pmap_kextract((vm_offset_t)cl); 1864 } else 1865 #endif 1866 { 1867 struct rxq_refill_cb_arg cb_arg; 1868 iflib_rxq_t q; 1869 1870 cb_arg.error = 0; 1871 q = fl->ifl_rxq; 1872 MPASS(sd_map != NULL); 1873 MPASS(sd_map[idx] != NULL); 1874 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[idx], 1875 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1876 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[idx], BUS_DMASYNC_PREREAD); 1877 1878 if (err != 0 || cb_arg.error) { 1879 /* 1880 * !zone_pack ? 1881 */ 1882 if (fl->ifl_zone == zone_pack) 1883 uma_zfree(fl->ifl_zone, cl); 1884 m_free(m); 1885 n = 0; 1886 goto done; 1887 } 1888 bus_addr = cb_arg.seg.ds_addr; 1889 } 1890 sd_flags[idx] |= RX_SW_DESC_INUSE; 1891 1892 MPASS(sd_m[idx] == NULL); 1893 sd_cl[idx] = cl; 1894 sd_m[idx] = m; 1895 fl->ifl_rxd_idxs[i] = idx; 1896 fl->ifl_bus_addrs[i] = bus_addr; 1897 fl->ifl_vm_addrs[i] = cl; 1898 fl->ifl_credits++; 1899 i++; 1900 MPASS(fl->ifl_credits <= fl->ifl_size); 1901 if (++idx == fl->ifl_size) { 1902 fl->ifl_gen = 1; 1903 idx = 0; 1904 } 1905 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 1906 iru.iru_pidx = pidx; 1907 iru.iru_count = i; 1908 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1909 i = 0; 1910 pidx = idx; 1911 } 1912 fl->ifl_pidx = idx; 1913 1914 } 1915 done: 1916 DBG_COUNTER_INC(rxd_flush); 1917 if (fl->ifl_pidx == 0) 1918 pidx = fl->ifl_size - 1; 1919 else 1920 pidx = fl->ifl_pidx - 1; 1921 1922 if (sd_map) 1923 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1924 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1925 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 1926 } 1927 1928 static __inline void 1929 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 1930 { 1931 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 1932 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 1933 #ifdef INVARIANTS 1934 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 1935 #endif 1936 1937 MPASS(fl->ifl_credits <= fl->ifl_size); 1938 MPASS(reclaimable == delta); 1939 1940 if (reclaimable > 0) 1941 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 1942 } 1943 1944 static void 1945 iflib_fl_bufs_free(iflib_fl_t fl) 1946 { 1947 iflib_dma_info_t idi = fl->ifl_ifdi; 1948 uint32_t i; 1949 1950 for (i = 0; i < fl->ifl_size; i++) { 1951 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 1952 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 1953 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 1954 1955 if (*sd_flags & RX_SW_DESC_INUSE) { 1956 if (fl->ifl_sds.ifsd_map != NULL) { 1957 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 1958 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 1959 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 1960 } 1961 if (*sd_m != NULL) { 1962 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 1963 uma_zfree(zone_mbuf, *sd_m); 1964 } 1965 if (*sd_cl != NULL) 1966 uma_zfree(fl->ifl_zone, *sd_cl); 1967 *sd_flags = 0; 1968 } else { 1969 MPASS(*sd_cl == NULL); 1970 MPASS(*sd_m == NULL); 1971 } 1972 #if MEMORY_LOGGING 1973 fl->ifl_m_dequeued++; 1974 fl->ifl_cl_dequeued++; 1975 #endif 1976 *sd_cl = NULL; 1977 *sd_m = NULL; 1978 } 1979 #ifdef INVARIANTS 1980 for (i = 0; i < fl->ifl_size; i++) { 1981 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 1982 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 1983 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 1984 } 1985 #endif 1986 /* 1987 * Reset free list values 1988 */ 1989 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = 0;; 1990 bzero(idi->idi_vaddr, idi->idi_size); 1991 } 1992 1993 /********************************************************************* 1994 * 1995 * Initialize a receive ring and its buffers. 1996 * 1997 **********************************************************************/ 1998 static int 1999 iflib_fl_setup(iflib_fl_t fl) 2000 { 2001 iflib_rxq_t rxq = fl->ifl_rxq; 2002 if_ctx_t ctx = rxq->ifr_ctx; 2003 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2004 2005 /* 2006 ** Free current RX buffer structs and their mbufs 2007 */ 2008 iflib_fl_bufs_free(fl); 2009 /* Now replenish the mbufs */ 2010 MPASS(fl->ifl_credits == 0); 2011 /* 2012 * XXX don't set the max_frame_size to larger 2013 * than the hardware can handle 2014 */ 2015 if (sctx->isc_max_frame_size <= 2048) 2016 fl->ifl_buf_size = MCLBYTES; 2017 #ifndef CONTIGMALLOC_WORKS 2018 else 2019 fl->ifl_buf_size = MJUMPAGESIZE; 2020 #else 2021 else if (sctx->isc_max_frame_size <= 4096) 2022 fl->ifl_buf_size = MJUMPAGESIZE; 2023 else if (sctx->isc_max_frame_size <= 9216) 2024 fl->ifl_buf_size = MJUM9BYTES; 2025 else 2026 fl->ifl_buf_size = MJUM16BYTES; 2027 #endif 2028 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2029 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2030 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2031 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2032 2033 2034 /* avoid pre-allocating zillions of clusters to an idle card 2035 * potentially speeding up attach 2036 */ 2037 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2038 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2039 if (min(128, fl->ifl_size) != fl->ifl_credits) 2040 return (ENOBUFS); 2041 /* 2042 * handle failure 2043 */ 2044 MPASS(rxq != NULL); 2045 MPASS(fl->ifl_ifdi != NULL); 2046 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2047 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2048 return (0); 2049 } 2050 2051 /********************************************************************* 2052 * 2053 * Free receive ring data structures 2054 * 2055 **********************************************************************/ 2056 static void 2057 iflib_rx_sds_free(iflib_rxq_t rxq) 2058 { 2059 iflib_fl_t fl; 2060 int i; 2061 2062 if (rxq->ifr_fl != NULL) { 2063 for (i = 0; i < rxq->ifr_nfl; i++) { 2064 fl = &rxq->ifr_fl[i]; 2065 if (fl->ifl_desc_tag != NULL) { 2066 bus_dma_tag_destroy(fl->ifl_desc_tag); 2067 fl->ifl_desc_tag = NULL; 2068 } 2069 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2070 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2071 /* XXX destroy maps first */ 2072 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2073 fl->ifl_sds.ifsd_m = NULL; 2074 fl->ifl_sds.ifsd_cl = NULL; 2075 fl->ifl_sds.ifsd_map = NULL; 2076 } 2077 free(rxq->ifr_fl, M_IFLIB); 2078 rxq->ifr_fl = NULL; 2079 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2080 } 2081 } 2082 2083 /* 2084 * MI independent logic 2085 * 2086 */ 2087 static void 2088 iflib_timer(void *arg) 2089 { 2090 iflib_txq_t txq = arg; 2091 if_ctx_t ctx = txq->ift_ctx; 2092 2093 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2094 return; 2095 /* 2096 ** Check on the state of the TX queue(s), this 2097 ** can be done without the lock because its RO 2098 ** and the HUNG state will be static if set. 2099 */ 2100 IFDI_TIMER(ctx, txq->ift_id); 2101 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2102 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2103 (ctx->ifc_pause_frames == 0))) 2104 goto hung; 2105 2106 if (ifmp_ring_is_stalled(txq->ift_br)) 2107 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2108 txq->ift_cleaned_prev = txq->ift_cleaned; 2109 /* handle any laggards */ 2110 if (txq->ift_db_pending) 2111 GROUPTASK_ENQUEUE(&txq->ift_task); 2112 2113 ctx->ifc_pause_frames = 0; 2114 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2115 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 2116 return; 2117 hung: 2118 CTX_LOCK(ctx); 2119 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2120 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2121 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2122 2123 IFDI_WATCHDOG_RESET(ctx); 2124 ctx->ifc_watchdog_events++; 2125 ctx->ifc_pause_frames = 0; 2126 2127 ctx->ifc_flags |= IFC_DO_RESET; 2128 iflib_admin_intr_deferred(ctx); 2129 CTX_UNLOCK(ctx); 2130 } 2131 2132 static void 2133 iflib_init_locked(if_ctx_t ctx) 2134 { 2135 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2136 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2137 if_t ifp = ctx->ifc_ifp; 2138 iflib_fl_t fl; 2139 iflib_txq_t txq; 2140 iflib_rxq_t rxq; 2141 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2142 2143 2144 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2145 IFDI_INTR_DISABLE(ctx); 2146 2147 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2148 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2149 /* Set hardware offload abilities */ 2150 if_clearhwassist(ifp); 2151 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2152 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2153 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2154 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2155 if (if_getcapenable(ifp) & IFCAP_TSO4) 2156 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2157 if (if_getcapenable(ifp) & IFCAP_TSO6) 2158 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2159 2160 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2161 CALLOUT_LOCK(txq); 2162 callout_stop(&txq->ift_timer); 2163 CALLOUT_UNLOCK(txq); 2164 iflib_netmap_txq_init(ctx, txq); 2165 } 2166 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2167 MPASS(rxq->ifr_id == i); 2168 iflib_netmap_rxq_init(ctx, rxq); 2169 } 2170 #ifdef INVARIANTS 2171 i = if_getdrvflags(ifp); 2172 #endif 2173 IFDI_INIT(ctx); 2174 MPASS(if_getdrvflags(ifp) == i); 2175 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2176 /* XXX this should really be done on a per-queue basis */ 2177 if (if_getcapenable(ifp) & IFCAP_NETMAP) 2178 continue; 2179 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2180 if (iflib_fl_setup(fl)) { 2181 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2182 goto done; 2183 } 2184 } 2185 } 2186 done: 2187 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2188 IFDI_INTR_ENABLE(ctx); 2189 txq = ctx->ifc_txqs; 2190 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2191 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2192 txq->ift_timer.c_cpu); 2193 } 2194 2195 static int 2196 iflib_media_change(if_t ifp) 2197 { 2198 if_ctx_t ctx = if_getsoftc(ifp); 2199 int err; 2200 2201 CTX_LOCK(ctx); 2202 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2203 iflib_init_locked(ctx); 2204 CTX_UNLOCK(ctx); 2205 return (err); 2206 } 2207 2208 static void 2209 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2210 { 2211 if_ctx_t ctx = if_getsoftc(ifp); 2212 2213 CTX_LOCK(ctx); 2214 IFDI_UPDATE_ADMIN_STATUS(ctx); 2215 IFDI_MEDIA_STATUS(ctx, ifmr); 2216 CTX_UNLOCK(ctx); 2217 } 2218 2219 static void 2220 iflib_stop(if_ctx_t ctx) 2221 { 2222 iflib_txq_t txq = ctx->ifc_txqs; 2223 iflib_rxq_t rxq = ctx->ifc_rxqs; 2224 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2225 iflib_dma_info_t di; 2226 iflib_fl_t fl; 2227 int i, j; 2228 2229 /* Tell the stack that the interface is no longer active */ 2230 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2231 2232 IFDI_INTR_DISABLE(ctx); 2233 DELAY(1000); 2234 IFDI_STOP(ctx); 2235 DELAY(1000); 2236 2237 iflib_debug_reset(); 2238 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2239 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2240 /* make sure all transmitters have completed before proceeding XXX */ 2241 2242 /* clean any enqueued buffers */ 2243 iflib_ifmp_purge(txq); 2244 /* Free any existing tx buffers. */ 2245 for (j = 0; j < txq->ift_size; j++) { 2246 iflib_txsd_free(ctx, txq, j); 2247 } 2248 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2249 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2250 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2251 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2252 txq->ift_pullups = 0; 2253 ifmp_ring_reset_stats(txq->ift_br); 2254 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2255 bzero((void *)di->idi_vaddr, di->idi_size); 2256 } 2257 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2258 /* make sure all transmitters have completed before proceeding XXX */ 2259 2260 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++) 2261 bzero((void *)di->idi_vaddr, di->idi_size); 2262 /* also resets the free lists pidx/cidx */ 2263 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2264 iflib_fl_bufs_free(fl); 2265 } 2266 } 2267 2268 static inline caddr_t 2269 calc_next_rxd(iflib_fl_t fl, int cidx) 2270 { 2271 qidx_t size; 2272 int nrxd; 2273 caddr_t start, end, cur, next; 2274 2275 nrxd = fl->ifl_size; 2276 size = fl->ifl_rxd_size; 2277 start = fl->ifl_ifdi->idi_vaddr; 2278 2279 if (__predict_false(size == 0)) 2280 return (start); 2281 cur = start + size*cidx; 2282 end = start + size*nrxd; 2283 next = CACHE_PTR_NEXT(cur); 2284 return (next < end ? next : start); 2285 } 2286 2287 static inline void 2288 prefetch_pkts(iflib_fl_t fl, int cidx) 2289 { 2290 int nextptr; 2291 int nrxd = fl->ifl_size; 2292 caddr_t next_rxd; 2293 2294 2295 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2296 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2297 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2298 next_rxd = calc_next_rxd(fl, cidx); 2299 prefetch(next_rxd); 2300 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2301 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2302 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2303 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2304 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2305 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2306 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2307 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2308 } 2309 2310 static void 2311 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2312 { 2313 int flid, cidx; 2314 bus_dmamap_t map; 2315 iflib_fl_t fl; 2316 iflib_dma_info_t di; 2317 int next; 2318 2319 map = NULL; 2320 flid = irf->irf_flid; 2321 cidx = irf->irf_idx; 2322 fl = &rxq->ifr_fl[flid]; 2323 sd->ifsd_fl = fl; 2324 sd->ifsd_cidx = cidx; 2325 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2326 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2327 fl->ifl_credits--; 2328 #if MEMORY_LOGGING 2329 fl->ifl_m_dequeued++; 2330 #endif 2331 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2332 prefetch_pkts(fl, cidx); 2333 if (fl->ifl_sds.ifsd_map != NULL) { 2334 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2335 prefetch(&fl->ifl_sds.ifsd_map[next]); 2336 map = fl->ifl_sds.ifsd_map[cidx]; 2337 di = fl->ifl_ifdi; 2338 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2339 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2340 bus_dmamap_sync(di->idi_tag, di->idi_map, 2341 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2342 2343 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2344 MPASS(fl->ifl_cidx == cidx); 2345 if (unload) 2346 bus_dmamap_unload(fl->ifl_desc_tag, map); 2347 } 2348 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2349 if (__predict_false(fl->ifl_cidx == 0)) 2350 fl->ifl_gen = 0; 2351 if (map != NULL) 2352 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2353 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2354 } 2355 2356 static struct mbuf * 2357 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2358 { 2359 int i, padlen , flags; 2360 struct mbuf *m, *mh, *mt; 2361 caddr_t cl; 2362 2363 i = 0; 2364 mh = NULL; 2365 do { 2366 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2367 2368 MPASS(*sd->ifsd_cl != NULL); 2369 MPASS(*sd->ifsd_m != NULL); 2370 2371 /* Don't include zero-length frags */ 2372 if (ri->iri_frags[i].irf_len == 0) { 2373 /* XXX we can save the cluster here, but not the mbuf */ 2374 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2375 m_free(*sd->ifsd_m); 2376 *sd->ifsd_m = NULL; 2377 continue; 2378 } 2379 m = *sd->ifsd_m; 2380 *sd->ifsd_m = NULL; 2381 if (mh == NULL) { 2382 flags = M_PKTHDR|M_EXT; 2383 mh = mt = m; 2384 padlen = ri->iri_pad; 2385 } else { 2386 flags = M_EXT; 2387 mt->m_next = m; 2388 mt = m; 2389 /* assuming padding is only on the first fragment */ 2390 padlen = 0; 2391 } 2392 cl = *sd->ifsd_cl; 2393 *sd->ifsd_cl = NULL; 2394 2395 /* Can these two be made one ? */ 2396 m_init(m, M_NOWAIT, MT_DATA, flags); 2397 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2398 /* 2399 * These must follow m_init and m_cljset 2400 */ 2401 m->m_data += padlen; 2402 ri->iri_len -= padlen; 2403 m->m_len = ri->iri_frags[i].irf_len; 2404 } while (++i < ri->iri_nfrags); 2405 2406 return (mh); 2407 } 2408 2409 /* 2410 * Process one software descriptor 2411 */ 2412 static struct mbuf * 2413 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2414 { 2415 struct if_rxsd sd; 2416 struct mbuf *m; 2417 2418 /* should I merge this back in now that the two paths are basically duplicated? */ 2419 if (ri->iri_nfrags == 1 && 2420 ri->iri_frags[0].irf_len <= IFLIB_RX_COPY_THRESH) { 2421 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2422 m = *sd.ifsd_m; 2423 *sd.ifsd_m = NULL; 2424 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2425 #ifndef __NO_STRICT_ALIGNMENT 2426 if (!IP_ALIGNED(m)) 2427 m->m_data += 2; 2428 #endif 2429 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2430 m->m_len = ri->iri_frags[0].irf_len; 2431 } else { 2432 m = assemble_segments(rxq, ri, &sd); 2433 } 2434 m->m_pkthdr.len = ri->iri_len; 2435 m->m_pkthdr.rcvif = ri->iri_ifp; 2436 m->m_flags |= ri->iri_flags; 2437 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2438 m->m_pkthdr.flowid = ri->iri_flowid; 2439 M_HASHTYPE_SET(m, ri->iri_rsstype); 2440 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2441 m->m_pkthdr.csum_data = ri->iri_csum_data; 2442 return (m); 2443 } 2444 2445 static bool 2446 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2447 { 2448 if_ctx_t ctx = rxq->ifr_ctx; 2449 if_shared_ctx_t sctx = ctx->ifc_sctx; 2450 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2451 int avail, i; 2452 qidx_t *cidxp; 2453 struct if_rxd_info ri; 2454 int err, budget_left, rx_bytes, rx_pkts; 2455 iflib_fl_t fl; 2456 struct ifnet *ifp; 2457 int lro_enabled; 2458 2459 /* 2460 * XXX early demux data packets so that if_input processing only handles 2461 * acks in interrupt context 2462 */ 2463 struct mbuf *m, *mh, *mt; 2464 2465 ifp = ctx->ifc_ifp; 2466 #ifdef DEV_NETMAP 2467 if (ifp->if_capenable & IFCAP_NETMAP) { 2468 u_int work = 0; 2469 if (netmap_rx_irq(ifp, rxq->ifr_id, &work)) 2470 return (FALSE); 2471 } 2472 #endif 2473 2474 mh = mt = NULL; 2475 MPASS(budget > 0); 2476 rx_pkts = rx_bytes = 0; 2477 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2478 cidxp = &rxq->ifr_cq_cidx; 2479 else 2480 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2481 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2482 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2483 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2484 DBG_COUNTER_INC(rx_unavail); 2485 return (false); 2486 } 2487 2488 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2489 if (__predict_false(!CTX_ACTIVE(ctx))) { 2490 DBG_COUNTER_INC(rx_ctx_inactive); 2491 break; 2492 } 2493 /* 2494 * Reset client set fields to their default values 2495 */ 2496 rxd_info_zero(&ri); 2497 ri.iri_qsidx = rxq->ifr_id; 2498 ri.iri_cidx = *cidxp; 2499 ri.iri_ifp = ifp; 2500 ri.iri_frags = rxq->ifr_frags; 2501 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2502 2503 if (err) 2504 goto err; 2505 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2506 *cidxp = ri.iri_cidx; 2507 /* Update our consumer index */ 2508 /* XXX NB: shurd - check if this is still safe */ 2509 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2510 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2511 rxq->ifr_cq_gen = 0; 2512 } 2513 /* was this only a completion queue message? */ 2514 if (__predict_false(ri.iri_nfrags == 0)) 2515 continue; 2516 } 2517 MPASS(ri.iri_nfrags != 0); 2518 MPASS(ri.iri_len != 0); 2519 2520 /* will advance the cidx on the corresponding free lists */ 2521 m = iflib_rxd_pkt_get(rxq, &ri); 2522 if (avail == 0 && budget_left) 2523 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2524 2525 if (__predict_false(m == NULL)) { 2526 DBG_COUNTER_INC(rx_mbuf_null); 2527 continue; 2528 } 2529 /* imm_pkt: -- cxgb */ 2530 if (mh == NULL) 2531 mh = mt = m; 2532 else { 2533 mt->m_nextpkt = m; 2534 mt = m; 2535 } 2536 } 2537 /* make sure that we can refill faster than drain */ 2538 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2539 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2540 2541 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2542 while (mh != NULL) { 2543 m = mh; 2544 mh = mh->m_nextpkt; 2545 m->m_nextpkt = NULL; 2546 #ifndef __NO_STRICT_ALIGNMENT 2547 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2548 continue; 2549 #endif 2550 rx_bytes += m->m_pkthdr.len; 2551 rx_pkts++; 2552 #if defined(INET6) || defined(INET) 2553 if (lro_enabled && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2554 continue; 2555 #endif 2556 DBG_COUNTER_INC(rx_if_input); 2557 ifp->if_input(ifp, m); 2558 } 2559 2560 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2561 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2562 2563 /* 2564 * Flush any outstanding LRO work 2565 */ 2566 #if defined(INET6) || defined(INET) 2567 tcp_lro_flush_all(&rxq->ifr_lc); 2568 #endif 2569 if (avail) 2570 return true; 2571 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2572 err: 2573 CTX_LOCK(ctx); 2574 ctx->ifc_flags |= IFC_DO_RESET; 2575 iflib_admin_intr_deferred(ctx); 2576 CTX_UNLOCK(ctx); 2577 return (false); 2578 } 2579 2580 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2581 static inline qidx_t 2582 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2583 { 2584 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2585 qidx_t minthresh = txq->ift_size / 8; 2586 if (in_use > 4*minthresh) 2587 return (notify_count); 2588 if (in_use > 2*minthresh) 2589 return (notify_count >> 1); 2590 if (in_use > minthresh) 2591 return (notify_count >> 3); 2592 return (0); 2593 } 2594 2595 static inline qidx_t 2596 txq_max_rs_deferred(iflib_txq_t txq) 2597 { 2598 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2599 qidx_t minthresh = txq->ift_size / 8; 2600 if (txq->ift_in_use > 4*minthresh) 2601 return (notify_count); 2602 if (txq->ift_in_use > 2*minthresh) 2603 return (notify_count >> 1); 2604 if (txq->ift_in_use > minthresh) 2605 return (notify_count >> 2); 2606 return (2); 2607 } 2608 2609 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2610 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2611 2612 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2613 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2614 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2615 2616 /* forward compatibility for cxgb */ 2617 #define FIRST_QSET(ctx) 0 2618 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2619 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2620 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2621 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2622 2623 /* XXX we should be setting this to something other than zero */ 2624 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2625 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2626 2627 static inline bool 2628 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2629 { 2630 qidx_t dbval, max; 2631 bool rang; 2632 2633 rang = false; 2634 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2635 if (ring || txq->ift_db_pending >= max) { 2636 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2637 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2638 txq->ift_db_pending = txq->ift_npending = 0; 2639 rang = true; 2640 } 2641 return (rang); 2642 } 2643 2644 #ifdef PKT_DEBUG 2645 static void 2646 print_pkt(if_pkt_info_t pi) 2647 { 2648 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2649 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2650 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2651 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2652 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2653 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2654 } 2655 #endif 2656 2657 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2658 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2659 2660 static int 2661 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2662 { 2663 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2664 struct ether_vlan_header *eh; 2665 struct mbuf *m, *n; 2666 2667 n = m = *mp; 2668 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2669 M_WRITABLE(m) == 0) { 2670 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2671 return (ENOMEM); 2672 } else { 2673 m_freem(*mp); 2674 n = *mp = m; 2675 } 2676 } 2677 2678 /* 2679 * Determine where frame payload starts. 2680 * Jump over vlan headers if already present, 2681 * helpful for QinQ too. 2682 */ 2683 if (__predict_false(m->m_len < sizeof(*eh))) { 2684 txq->ift_pullups++; 2685 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2686 return (ENOMEM); 2687 } 2688 eh = mtod(m, struct ether_vlan_header *); 2689 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2690 pi->ipi_etype = ntohs(eh->evl_proto); 2691 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2692 } else { 2693 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2694 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2695 } 2696 2697 switch (pi->ipi_etype) { 2698 #ifdef INET 2699 case ETHERTYPE_IP: 2700 { 2701 struct ip *ip = NULL; 2702 struct tcphdr *th = NULL; 2703 int minthlen; 2704 2705 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2706 if (__predict_false(m->m_len < minthlen)) { 2707 /* 2708 * if this code bloat is causing too much of a hit 2709 * move it to a separate function and mark it noinline 2710 */ 2711 if (m->m_len == pi->ipi_ehdrlen) { 2712 n = m->m_next; 2713 MPASS(n); 2714 if (n->m_len >= sizeof(*ip)) { 2715 ip = (struct ip *)n->m_data; 2716 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2717 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2718 } else { 2719 txq->ift_pullups++; 2720 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2721 return (ENOMEM); 2722 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2723 } 2724 } else { 2725 txq->ift_pullups++; 2726 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2727 return (ENOMEM); 2728 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2729 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2730 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2731 } 2732 } else { 2733 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2734 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2735 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2736 } 2737 pi->ipi_ip_hlen = ip->ip_hl << 2; 2738 pi->ipi_ipproto = ip->ip_p; 2739 pi->ipi_flags |= IPI_TX_IPV4; 2740 2741 if (pi->ipi_csum_flags & CSUM_IP) 2742 ip->ip_sum = 0; 2743 2744 if (pi->ipi_ipproto == IPPROTO_TCP) { 2745 if (__predict_false(th == NULL)) { 2746 txq->ift_pullups++; 2747 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2748 return (ENOMEM); 2749 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2750 } 2751 pi->ipi_tcp_hflags = th->th_flags; 2752 pi->ipi_tcp_hlen = th->th_off << 2; 2753 pi->ipi_tcp_seq = th->th_seq; 2754 } 2755 if (IS_TSO4(pi)) { 2756 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2757 return (ENXIO); 2758 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2759 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2760 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2761 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2762 ip->ip_sum = 0; 2763 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2764 } 2765 } 2766 break; 2767 } 2768 #endif 2769 #ifdef INET6 2770 case ETHERTYPE_IPV6: 2771 { 2772 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2773 struct tcphdr *th; 2774 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2775 2776 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2777 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2778 return (ENOMEM); 2779 } 2780 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2781 2782 /* XXX-BZ this will go badly in case of ext hdrs. */ 2783 pi->ipi_ipproto = ip6->ip6_nxt; 2784 pi->ipi_flags |= IPI_TX_IPV6; 2785 2786 if (pi->ipi_ipproto == IPPROTO_TCP) { 2787 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2788 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2789 return (ENOMEM); 2790 } 2791 pi->ipi_tcp_hflags = th->th_flags; 2792 pi->ipi_tcp_hlen = th->th_off << 2; 2793 } 2794 if (IS_TSO6(pi)) { 2795 2796 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2797 return (ENXIO); 2798 /* 2799 * The corresponding flag is set by the stack in the IPv4 2800 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 2801 * So, set it here because the rest of the flow requires it. 2802 */ 2803 pi->ipi_csum_flags |= CSUM_TCP_IPV6; 2804 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2805 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2806 } 2807 break; 2808 } 2809 #endif 2810 default: 2811 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2812 pi->ipi_ip_hlen = 0; 2813 break; 2814 } 2815 *mp = m; 2816 2817 return (0); 2818 } 2819 2820 static __noinline struct mbuf * 2821 collapse_pkthdr(struct mbuf *m0) 2822 { 2823 struct mbuf *m, *m_next, *tmp; 2824 2825 m = m0; 2826 m_next = m->m_next; 2827 while (m_next != NULL && m_next->m_len == 0) { 2828 m = m_next; 2829 m->m_next = NULL; 2830 m_free(m); 2831 m_next = m_next->m_next; 2832 } 2833 m = m0; 2834 m->m_next = m_next; 2835 if ((m_next->m_flags & M_EXT) == 0) { 2836 m = m_defrag(m, M_NOWAIT); 2837 } else { 2838 tmp = m_next->m_next; 2839 memcpy(m_next, m, MPKTHSIZE); 2840 m = m_next; 2841 m->m_next = tmp; 2842 } 2843 return (m); 2844 } 2845 2846 /* 2847 * If dodgy hardware rejects the scatter gather chain we've handed it 2848 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 2849 * m_defrag'd mbufs 2850 */ 2851 static __noinline struct mbuf * 2852 iflib_remove_mbuf(iflib_txq_t txq) 2853 { 2854 int ntxd, i, pidx; 2855 struct mbuf *m, *mh, **ifsd_m; 2856 2857 pidx = txq->ift_pidx; 2858 ifsd_m = txq->ift_sds.ifsd_m; 2859 ntxd = txq->ift_size; 2860 mh = m = ifsd_m[pidx]; 2861 ifsd_m[pidx] = NULL; 2862 #if MEMORY_LOGGING 2863 txq->ift_dequeued++; 2864 #endif 2865 i = 1; 2866 2867 while (m) { 2868 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 2869 #if MEMORY_LOGGING 2870 txq->ift_dequeued++; 2871 #endif 2872 m = m->m_next; 2873 i++; 2874 } 2875 return (mh); 2876 } 2877 2878 static int 2879 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 2880 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 2881 int max_segs, int flags) 2882 { 2883 if_ctx_t ctx; 2884 if_shared_ctx_t sctx; 2885 if_softc_ctx_t scctx; 2886 int i, next, pidx, mask, err, maxsegsz, ntxd, count; 2887 struct mbuf *m, *tmp, **ifsd_m, **mp; 2888 2889 m = *m0; 2890 2891 /* 2892 * Please don't ever do this 2893 */ 2894 if (__predict_false(m->m_len == 0)) 2895 *m0 = m = collapse_pkthdr(m); 2896 2897 ctx = txq->ift_ctx; 2898 sctx = ctx->ifc_sctx; 2899 scctx = &ctx->ifc_softc_ctx; 2900 ifsd_m = txq->ift_sds.ifsd_m; 2901 ntxd = txq->ift_size; 2902 pidx = txq->ift_pidx; 2903 if (map != NULL) { 2904 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 2905 2906 err = bus_dmamap_load_mbuf_sg(tag, map, 2907 *m0, segs, nsegs, BUS_DMA_NOWAIT); 2908 if (err) 2909 return (err); 2910 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 2911 i = 0; 2912 next = pidx; 2913 mask = (txq->ift_size-1); 2914 m = *m0; 2915 do { 2916 mp = &ifsd_m[next]; 2917 *mp = m; 2918 m = m->m_next; 2919 if (__predict_false((*mp)->m_len == 0)) { 2920 m_free(*mp); 2921 *mp = NULL; 2922 } else 2923 next = (pidx + i) & (ntxd-1); 2924 } while (m != NULL); 2925 } else { 2926 int buflen, sgsize, max_sgsize; 2927 vm_offset_t vaddr; 2928 vm_paddr_t curaddr; 2929 2930 count = i = 0; 2931 maxsegsz = sctx->isc_tx_maxsize; 2932 m = *m0; 2933 do { 2934 if (__predict_false(m->m_len <= 0)) { 2935 tmp = m; 2936 m = m->m_next; 2937 tmp->m_next = NULL; 2938 m_free(tmp); 2939 continue; 2940 } 2941 buflen = m->m_len; 2942 vaddr = (vm_offset_t)m->m_data; 2943 /* 2944 * see if we can't be smarter about physically 2945 * contiguous mappings 2946 */ 2947 next = (pidx + count) & (ntxd-1); 2948 MPASS(ifsd_m[next] == NULL); 2949 #if MEMORY_LOGGING 2950 txq->ift_enqueued++; 2951 #endif 2952 ifsd_m[next] = m; 2953 while (buflen > 0) { 2954 max_sgsize = MIN(buflen, maxsegsz); 2955 curaddr = pmap_kextract(vaddr); 2956 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 2957 sgsize = MIN(sgsize, max_sgsize); 2958 segs[i].ds_addr = curaddr; 2959 segs[i].ds_len = sgsize; 2960 vaddr += sgsize; 2961 buflen -= sgsize; 2962 i++; 2963 if (i >= max_segs) 2964 goto err; 2965 } 2966 count++; 2967 tmp = m; 2968 m = m->m_next; 2969 } while (m != NULL); 2970 *nsegs = i; 2971 } 2972 return (0); 2973 err: 2974 *m0 = iflib_remove_mbuf(txq); 2975 return (EFBIG); 2976 } 2977 2978 static inline caddr_t 2979 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 2980 { 2981 qidx_t size; 2982 int ntxd; 2983 caddr_t start, end, cur, next; 2984 2985 ntxd = txq->ift_size; 2986 size = txq->ift_txd_size[qid]; 2987 start = txq->ift_ifdi[qid].idi_vaddr; 2988 2989 if (__predict_false(size == 0)) 2990 return (start); 2991 cur = start + size*cidx; 2992 end = start + size*ntxd; 2993 next = CACHE_PTR_NEXT(cur); 2994 return (next < end ? next : start); 2995 } 2996 2997 static int 2998 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 2999 { 3000 if_ctx_t ctx; 3001 if_shared_ctx_t sctx; 3002 if_softc_ctx_t scctx; 3003 bus_dma_segment_t *segs; 3004 struct mbuf *m_head; 3005 void *next_txd; 3006 bus_dmamap_t map; 3007 struct if_pkt_info pi; 3008 int remap = 0; 3009 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3010 bus_dma_tag_t desc_tag; 3011 3012 segs = txq->ift_segs; 3013 ctx = txq->ift_ctx; 3014 sctx = ctx->ifc_sctx; 3015 scctx = &ctx->ifc_softc_ctx; 3016 segs = txq->ift_segs; 3017 ntxd = txq->ift_size; 3018 m_head = *m_headp; 3019 map = NULL; 3020 3021 /* 3022 * If we're doing TSO the next descriptor to clean may be quite far ahead 3023 */ 3024 cidx = txq->ift_cidx; 3025 pidx = txq->ift_pidx; 3026 if (ctx->ifc_flags & IFC_PREFETCH) { 3027 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3028 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3029 next_txd = calc_next_txd(txq, cidx, 0); 3030 prefetch(next_txd); 3031 } 3032 3033 /* prefetch the next cache line of mbuf pointers and flags */ 3034 prefetch(&txq->ift_sds.ifsd_m[next]); 3035 if (txq->ift_sds.ifsd_map != NULL) { 3036 prefetch(&txq->ift_sds.ifsd_map[next]); 3037 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3038 prefetch(&txq->ift_sds.ifsd_flags[next]); 3039 } 3040 } else if (txq->ift_sds.ifsd_map != NULL) 3041 map = txq->ift_sds.ifsd_map[pidx]; 3042 3043 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3044 desc_tag = txq->ift_tso_desc_tag; 3045 max_segs = scctx->isc_tx_tso_segments_max; 3046 } else { 3047 desc_tag = txq->ift_desc_tag; 3048 max_segs = scctx->isc_tx_nsegments; 3049 } 3050 m_head = *m_headp; 3051 3052 pkt_info_zero(&pi); 3053 pi.ipi_len = m_head->m_pkthdr.len; 3054 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3055 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3056 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3057 pi.ipi_pidx = pidx; 3058 pi.ipi_qsidx = txq->ift_id; 3059 3060 /* deliberate bitwise OR to make one condition */ 3061 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3062 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3063 return (err); 3064 m_head = *m_headp; 3065 } 3066 3067 retry: 3068 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3069 defrag: 3070 if (__predict_false(err)) { 3071 switch (err) { 3072 case EFBIG: 3073 /* try collapse once and defrag once */ 3074 if (remap == 0) 3075 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3076 if (remap == 1) 3077 m_head = m_defrag(*m_headp, M_NOWAIT); 3078 remap++; 3079 if (__predict_false(m_head == NULL)) 3080 goto defrag_failed; 3081 txq->ift_mbuf_defrag++; 3082 *m_headp = m_head; 3083 goto retry; 3084 break; 3085 case ENOMEM: 3086 txq->ift_no_tx_dma_setup++; 3087 break; 3088 default: 3089 txq->ift_no_tx_dma_setup++; 3090 m_freem(*m_headp); 3091 DBG_COUNTER_INC(tx_frees); 3092 *m_headp = NULL; 3093 break; 3094 } 3095 txq->ift_map_failed++; 3096 DBG_COUNTER_INC(encap_load_mbuf_fail); 3097 return (err); 3098 } 3099 3100 /* 3101 * XXX assumes a 1 to 1 relationship between segments and 3102 * descriptors - this does not hold true on all drivers, e.g. 3103 * cxgb 3104 */ 3105 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3106 txq->ift_no_desc_avail++; 3107 if (map != NULL) 3108 bus_dmamap_unload(desc_tag, map); 3109 DBG_COUNTER_INC(encap_txq_avail_fail); 3110 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3111 GROUPTASK_ENQUEUE(&txq->ift_task); 3112 return (ENOBUFS); 3113 } 3114 /* 3115 * On Intel cards we can greatly reduce the number of TX interrupts 3116 * we see by only setting report status on every Nth descriptor. 3117 * However, this also means that the driver will need to keep track 3118 * of the descriptors that RS was set on to check them for the DD bit. 3119 */ 3120 txq->ift_rs_pending += nsegs + 1; 3121 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3122 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) { 3123 pi.ipi_flags |= IPI_TX_INTR; 3124 txq->ift_rs_pending = 0; 3125 } 3126 3127 pi.ipi_segs = segs; 3128 pi.ipi_nsegs = nsegs; 3129 3130 MPASS(pidx >= 0 && pidx < txq->ift_size); 3131 #ifdef PKT_DEBUG 3132 print_pkt(&pi); 3133 #endif 3134 if (map != NULL) 3135 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3136 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3137 if (map != NULL) 3138 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3139 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3140 DBG_COUNTER_INC(tx_encap); 3141 MPASS(pi.ipi_new_pidx < txq->ift_size); 3142 3143 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3144 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3145 ndesc += txq->ift_size; 3146 txq->ift_gen = 1; 3147 } 3148 /* 3149 * drivers can need as many as 3150 * two sentinels 3151 */ 3152 MPASS(ndesc <= pi.ipi_nsegs + 2); 3153 MPASS(pi.ipi_new_pidx != pidx); 3154 MPASS(ndesc > 0); 3155 txq->ift_in_use += ndesc; 3156 3157 /* 3158 * We update the last software descriptor again here because there may 3159 * be a sentinel and/or there may be more mbufs than segments 3160 */ 3161 txq->ift_pidx = pi.ipi_new_pidx; 3162 txq->ift_npending += pi.ipi_ndescs; 3163 } else if (__predict_false(err == EFBIG && remap < 2)) { 3164 *m_headp = m_head = iflib_remove_mbuf(txq); 3165 remap = 1; 3166 txq->ift_txd_encap_efbig++; 3167 goto defrag; 3168 } else 3169 DBG_COUNTER_INC(encap_txd_encap_fail); 3170 return (err); 3171 3172 defrag_failed: 3173 txq->ift_mbuf_defrag_failed++; 3174 txq->ift_map_failed++; 3175 m_freem(*m_headp); 3176 DBG_COUNTER_INC(tx_frees); 3177 *m_headp = NULL; 3178 return (ENOMEM); 3179 } 3180 3181 static void 3182 iflib_tx_desc_free(iflib_txq_t txq, int n) 3183 { 3184 int hasmap; 3185 uint32_t qsize, cidx, mask, gen; 3186 struct mbuf *m, **ifsd_m; 3187 uint8_t *ifsd_flags; 3188 bus_dmamap_t *ifsd_map; 3189 bool do_prefetch; 3190 3191 cidx = txq->ift_cidx; 3192 gen = txq->ift_gen; 3193 qsize = txq->ift_size; 3194 mask = qsize-1; 3195 hasmap = txq->ift_sds.ifsd_map != NULL; 3196 ifsd_flags = txq->ift_sds.ifsd_flags; 3197 ifsd_m = txq->ift_sds.ifsd_m; 3198 ifsd_map = txq->ift_sds.ifsd_map; 3199 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3200 3201 while (n--) { 3202 if (do_prefetch) { 3203 prefetch(ifsd_m[(cidx + 3) & mask]); 3204 prefetch(ifsd_m[(cidx + 4) & mask]); 3205 } 3206 if (ifsd_m[cidx] != NULL) { 3207 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3208 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3209 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3210 /* 3211 * does it matter if it's not the TSO tag? If so we'll 3212 * have to add the type to flags 3213 */ 3214 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3215 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3216 } 3217 if ((m = ifsd_m[cidx]) != NULL) { 3218 /* XXX we don't support any drivers that batch packets yet */ 3219 MPASS(m->m_nextpkt == NULL); 3220 3221 m_free(m); 3222 ifsd_m[cidx] = NULL; 3223 #if MEMORY_LOGGING 3224 txq->ift_dequeued++; 3225 #endif 3226 DBG_COUNTER_INC(tx_frees); 3227 } 3228 } 3229 if (__predict_false(++cidx == qsize)) { 3230 cidx = 0; 3231 gen = 0; 3232 } 3233 } 3234 txq->ift_cidx = cidx; 3235 txq->ift_gen = gen; 3236 } 3237 3238 static __inline int 3239 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3240 { 3241 int reclaim; 3242 if_ctx_t ctx = txq->ift_ctx; 3243 3244 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3245 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3246 3247 /* 3248 * Need a rate-limiting check so that this isn't called every time 3249 */ 3250 iflib_tx_credits_update(ctx, txq); 3251 reclaim = DESC_RECLAIMABLE(txq); 3252 3253 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3254 #ifdef INVARIANTS 3255 if (iflib_verbose_debug) { 3256 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3257 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3258 reclaim, thresh); 3259 3260 } 3261 #endif 3262 return (0); 3263 } 3264 iflib_tx_desc_free(txq, reclaim); 3265 txq->ift_cleaned += reclaim; 3266 txq->ift_in_use -= reclaim; 3267 3268 return (reclaim); 3269 } 3270 3271 static struct mbuf ** 3272 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3273 { 3274 int next, size; 3275 struct mbuf **items; 3276 3277 size = r->size; 3278 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3279 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3280 3281 prefetch(items[(cidx + offset) & (size-1)]); 3282 if (remaining > 1) { 3283 prefetch(&items[next]); 3284 prefetch(items[(cidx + offset + 1) & (size-1)]); 3285 prefetch(items[(cidx + offset + 2) & (size-1)]); 3286 prefetch(items[(cidx + offset + 3) & (size-1)]); 3287 } 3288 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3289 } 3290 3291 static void 3292 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3293 { 3294 3295 ifmp_ring_check_drainage(txq->ift_br, budget); 3296 } 3297 3298 static uint32_t 3299 iflib_txq_can_drain(struct ifmp_ring *r) 3300 { 3301 iflib_txq_t txq = r->cookie; 3302 if_ctx_t ctx = txq->ift_ctx; 3303 3304 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3305 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3306 } 3307 3308 static uint32_t 3309 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3310 { 3311 iflib_txq_t txq = r->cookie; 3312 if_ctx_t ctx = txq->ift_ctx; 3313 struct ifnet *ifp = ctx->ifc_ifp; 3314 struct mbuf **mp, *m; 3315 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3316 int reclaimed, err, in_use_prev, desc_used; 3317 bool do_prefetch, ring, rang; 3318 3319 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3320 !LINK_ACTIVE(ctx))) { 3321 DBG_COUNTER_INC(txq_drain_notready); 3322 return (0); 3323 } 3324 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3325 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3326 avail = IDXDIFF(pidx, cidx, r->size); 3327 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3328 DBG_COUNTER_INC(txq_drain_flushing); 3329 for (i = 0; i < avail; i++) { 3330 m_free(r->items[(cidx + i) & (r->size-1)]); 3331 r->items[(cidx + i) & (r->size-1)] = NULL; 3332 } 3333 return (avail); 3334 } 3335 3336 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3337 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3338 CALLOUT_LOCK(txq); 3339 callout_stop(&txq->ift_timer); 3340 CALLOUT_UNLOCK(txq); 3341 DBG_COUNTER_INC(txq_drain_oactive); 3342 return (0); 3343 } 3344 if (reclaimed) 3345 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3346 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3347 count = MIN(avail, TX_BATCH_SIZE); 3348 #ifdef INVARIANTS 3349 if (iflib_verbose_debug) 3350 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3351 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3352 #endif 3353 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3354 avail = TXQ_AVAIL(txq); 3355 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3356 int pidx_prev, rem = do_prefetch ? count - i : 0; 3357 3358 mp = _ring_peek_one(r, cidx, i, rem); 3359 MPASS(mp != NULL && *mp != NULL); 3360 if (__predict_false(*mp == (struct mbuf *)txq)) { 3361 consumed++; 3362 reclaimed++; 3363 continue; 3364 } 3365 in_use_prev = txq->ift_in_use; 3366 pidx_prev = txq->ift_pidx; 3367 err = iflib_encap(txq, mp); 3368 if (__predict_false(err)) { 3369 DBG_COUNTER_INC(txq_drain_encapfail); 3370 /* no room - bail out */ 3371 if (err == ENOBUFS) 3372 break; 3373 consumed++; 3374 DBG_COUNTER_INC(txq_drain_encapfail); 3375 /* we can't send this packet - skip it */ 3376 continue; 3377 } 3378 consumed++; 3379 pkt_sent++; 3380 m = *mp; 3381 DBG_COUNTER_INC(tx_sent); 3382 bytes_sent += m->m_pkthdr.len; 3383 mcast_sent += !!(m->m_flags & M_MCAST); 3384 avail = TXQ_AVAIL(txq); 3385 3386 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3387 desc_used += (txq->ift_in_use - in_use_prev); 3388 ETHER_BPF_MTAP(ifp, m); 3389 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3390 break; 3391 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3392 } 3393 3394 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3395 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3396 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3397 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3398 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3399 if (mcast_sent) 3400 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3401 #ifdef INVARIANTS 3402 if (iflib_verbose_debug) 3403 printf("consumed=%d\n", consumed); 3404 #endif 3405 return (consumed); 3406 } 3407 3408 static uint32_t 3409 iflib_txq_drain_always(struct ifmp_ring *r) 3410 { 3411 return (1); 3412 } 3413 3414 static uint32_t 3415 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3416 { 3417 int i, avail; 3418 struct mbuf **mp; 3419 iflib_txq_t txq; 3420 3421 txq = r->cookie; 3422 3423 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3424 CALLOUT_LOCK(txq); 3425 callout_stop(&txq->ift_timer); 3426 CALLOUT_UNLOCK(txq); 3427 3428 avail = IDXDIFF(pidx, cidx, r->size); 3429 for (i = 0; i < avail; i++) { 3430 mp = _ring_peek_one(r, cidx, i, avail - i); 3431 if (__predict_false(*mp == (struct mbuf *)txq)) 3432 continue; 3433 m_freem(*mp); 3434 } 3435 MPASS(ifmp_ring_is_stalled(r) == 0); 3436 return (avail); 3437 } 3438 3439 static void 3440 iflib_ifmp_purge(iflib_txq_t txq) 3441 { 3442 struct ifmp_ring *r; 3443 3444 r = txq->ift_br; 3445 r->drain = iflib_txq_drain_free; 3446 r->can_drain = iflib_txq_drain_always; 3447 3448 ifmp_ring_check_drainage(r, r->size); 3449 3450 r->drain = iflib_txq_drain; 3451 r->can_drain = iflib_txq_can_drain; 3452 } 3453 3454 static void 3455 _task_fn_tx(void *context) 3456 { 3457 iflib_txq_t txq = context; 3458 if_ctx_t ctx = txq->ift_ctx; 3459 struct ifnet *ifp = ctx->ifc_ifp; 3460 int rc; 3461 3462 #ifdef IFLIB_DIAGNOSTICS 3463 txq->ift_cpu_exec_count[curcpu]++; 3464 #endif 3465 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3466 return; 3467 if ((ifp->if_capenable & IFCAP_NETMAP)) { 3468 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3469 netmap_tx_irq(ifp, txq->ift_id); 3470 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3471 return; 3472 } 3473 if (txq->ift_db_pending) 3474 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); 3475 else 3476 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3477 if (ctx->ifc_flags & IFC_LEGACY) 3478 IFDI_INTR_ENABLE(ctx); 3479 else { 3480 rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3481 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3482 } 3483 } 3484 3485 static void 3486 _task_fn_rx(void *context) 3487 { 3488 iflib_rxq_t rxq = context; 3489 if_ctx_t ctx = rxq->ifr_ctx; 3490 bool more; 3491 int rc; 3492 3493 #ifdef IFLIB_DIAGNOSTICS 3494 rxq->ifr_cpu_exec_count[curcpu]++; 3495 #endif 3496 DBG_COUNTER_INC(task_fn_rxs); 3497 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3498 return; 3499 if ((more = iflib_rxeof(rxq, 16 /* XXX */)) == false) { 3500 if (ctx->ifc_flags & IFC_LEGACY) 3501 IFDI_INTR_ENABLE(ctx); 3502 else { 3503 DBG_COUNTER_INC(rx_intr_enables); 3504 rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3505 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3506 } 3507 } 3508 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3509 return; 3510 if (more) 3511 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3512 } 3513 3514 static void 3515 _task_fn_admin(void *context) 3516 { 3517 if_ctx_t ctx = context; 3518 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3519 iflib_txq_t txq; 3520 int i; 3521 3522 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) { 3523 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3524 return; 3525 } 3526 } 3527 3528 CTX_LOCK(ctx); 3529 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3530 CALLOUT_LOCK(txq); 3531 callout_stop(&txq->ift_timer); 3532 CALLOUT_UNLOCK(txq); 3533 } 3534 IFDI_UPDATE_ADMIN_STATUS(ctx); 3535 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3536 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 3537 IFDI_LINK_INTR_ENABLE(ctx); 3538 if (ctx->ifc_flags & IFC_DO_RESET) { 3539 ctx->ifc_flags &= ~IFC_DO_RESET; 3540 iflib_if_init_locked(ctx); 3541 } 3542 CTX_UNLOCK(ctx); 3543 3544 if (LINK_ACTIVE(ctx) == 0) 3545 return; 3546 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3547 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3548 } 3549 3550 3551 static void 3552 _task_fn_iov(void *context) 3553 { 3554 if_ctx_t ctx = context; 3555 3556 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3557 return; 3558 3559 CTX_LOCK(ctx); 3560 IFDI_VFLR_HANDLE(ctx); 3561 CTX_UNLOCK(ctx); 3562 } 3563 3564 static int 3565 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3566 { 3567 int err; 3568 if_int_delay_info_t info; 3569 if_ctx_t ctx; 3570 3571 info = (if_int_delay_info_t)arg1; 3572 ctx = info->iidi_ctx; 3573 info->iidi_req = req; 3574 info->iidi_oidp = oidp; 3575 CTX_LOCK(ctx); 3576 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3577 CTX_UNLOCK(ctx); 3578 return (err); 3579 } 3580 3581 /********************************************************************* 3582 * 3583 * IFNET FUNCTIONS 3584 * 3585 **********************************************************************/ 3586 3587 static void 3588 iflib_if_init_locked(if_ctx_t ctx) 3589 { 3590 iflib_stop(ctx); 3591 iflib_init_locked(ctx); 3592 } 3593 3594 3595 static void 3596 iflib_if_init(void *arg) 3597 { 3598 if_ctx_t ctx = arg; 3599 3600 CTX_LOCK(ctx); 3601 iflib_if_init_locked(ctx); 3602 CTX_UNLOCK(ctx); 3603 } 3604 3605 static int 3606 iflib_if_transmit(if_t ifp, struct mbuf *m) 3607 { 3608 if_ctx_t ctx = if_getsoftc(ifp); 3609 3610 iflib_txq_t txq; 3611 int err, qidx; 3612 3613 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3614 DBG_COUNTER_INC(tx_frees); 3615 m_freem(m); 3616 return (ENOBUFS); 3617 } 3618 3619 MPASS(m->m_nextpkt == NULL); 3620 qidx = 0; 3621 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3622 qidx = QIDX(ctx, m); 3623 /* 3624 * XXX calculate buf_ring based on flowid (divvy up bits?) 3625 */ 3626 txq = &ctx->ifc_txqs[qidx]; 3627 3628 #ifdef DRIVER_BACKPRESSURE 3629 if (txq->ift_closed) { 3630 while (m != NULL) { 3631 next = m->m_nextpkt; 3632 m->m_nextpkt = NULL; 3633 m_freem(m); 3634 m = next; 3635 } 3636 return (ENOBUFS); 3637 } 3638 #endif 3639 #ifdef notyet 3640 qidx = count = 0; 3641 mp = marr; 3642 next = m; 3643 do { 3644 count++; 3645 next = next->m_nextpkt; 3646 } while (next != NULL); 3647 3648 if (count > nitems(marr)) 3649 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3650 /* XXX check nextpkt */ 3651 m_freem(m); 3652 /* XXX simplify for now */ 3653 DBG_COUNTER_INC(tx_frees); 3654 return (ENOBUFS); 3655 } 3656 for (next = m, i = 0; next != NULL; i++) { 3657 mp[i] = next; 3658 next = next->m_nextpkt; 3659 mp[i]->m_nextpkt = NULL; 3660 } 3661 #endif 3662 DBG_COUNTER_INC(tx_seen); 3663 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); 3664 3665 if (err) { 3666 GROUPTASK_ENQUEUE(&txq->ift_task); 3667 /* support forthcoming later */ 3668 #ifdef DRIVER_BACKPRESSURE 3669 txq->ift_closed = TRUE; 3670 #endif 3671 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3672 m_freem(m); 3673 } else if (TXQ_AVAIL(txq) < (txq->ift_size >> 1)) { 3674 GROUPTASK_ENQUEUE(&txq->ift_task); 3675 } 3676 3677 return (err); 3678 } 3679 3680 static void 3681 iflib_if_qflush(if_t ifp) 3682 { 3683 if_ctx_t ctx = if_getsoftc(ifp); 3684 iflib_txq_t txq = ctx->ifc_txqs; 3685 int i; 3686 3687 CTX_LOCK(ctx); 3688 ctx->ifc_flags |= IFC_QFLUSH; 3689 CTX_UNLOCK(ctx); 3690 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3691 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3692 iflib_txq_check_drain(txq, 0); 3693 CTX_LOCK(ctx); 3694 ctx->ifc_flags &= ~IFC_QFLUSH; 3695 CTX_UNLOCK(ctx); 3696 3697 if_qflush(ifp); 3698 } 3699 3700 3701 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3702 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | \ 3703 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 3704 3705 static int 3706 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 3707 { 3708 if_ctx_t ctx = if_getsoftc(ifp); 3709 struct ifreq *ifr = (struct ifreq *)data; 3710 #if defined(INET) || defined(INET6) 3711 struct ifaddr *ifa = (struct ifaddr *)data; 3712 #endif 3713 bool avoid_reset = FALSE; 3714 int err = 0, reinit = 0, bits; 3715 3716 switch (command) { 3717 case SIOCSIFADDR: 3718 #ifdef INET 3719 if (ifa->ifa_addr->sa_family == AF_INET) 3720 avoid_reset = TRUE; 3721 #endif 3722 #ifdef INET6 3723 if (ifa->ifa_addr->sa_family == AF_INET6) 3724 avoid_reset = TRUE; 3725 #endif 3726 /* 3727 ** Calling init results in link renegotiation, 3728 ** so we avoid doing it when possible. 3729 */ 3730 if (avoid_reset) { 3731 if_setflagbits(ifp, IFF_UP,0); 3732 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING)) 3733 reinit = 1; 3734 #ifdef INET 3735 if (!(if_getflags(ifp) & IFF_NOARP)) 3736 arp_ifinit(ifp, ifa); 3737 #endif 3738 } else 3739 err = ether_ioctl(ifp, command, data); 3740 break; 3741 case SIOCSIFMTU: 3742 CTX_LOCK(ctx); 3743 if (ifr->ifr_mtu == if_getmtu(ifp)) { 3744 CTX_UNLOCK(ctx); 3745 break; 3746 } 3747 bits = if_getdrvflags(ifp); 3748 /* stop the driver and free any clusters before proceeding */ 3749 iflib_stop(ctx); 3750 3751 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 3752 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 3753 ctx->ifc_flags |= IFC_MULTISEG; 3754 else 3755 ctx->ifc_flags &= ~IFC_MULTISEG; 3756 err = if_setmtu(ifp, ifr->ifr_mtu); 3757 } 3758 iflib_init_locked(ctx); 3759 if_setdrvflags(ifp, bits); 3760 CTX_UNLOCK(ctx); 3761 break; 3762 case SIOCSIFFLAGS: 3763 CTX_LOCK(ctx); 3764 if (if_getflags(ifp) & IFF_UP) { 3765 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3766 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 3767 (IFF_PROMISC | IFF_ALLMULTI)) { 3768 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 3769 } 3770 } else 3771 reinit = 1; 3772 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3773 iflib_stop(ctx); 3774 } 3775 ctx->ifc_if_flags = if_getflags(ifp); 3776 CTX_UNLOCK(ctx); 3777 break; 3778 case SIOCADDMULTI: 3779 case SIOCDELMULTI: 3780 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3781 CTX_LOCK(ctx); 3782 IFDI_INTR_DISABLE(ctx); 3783 IFDI_MULTI_SET(ctx); 3784 IFDI_INTR_ENABLE(ctx); 3785 CTX_UNLOCK(ctx); 3786 } 3787 break; 3788 case SIOCSIFMEDIA: 3789 CTX_LOCK(ctx); 3790 IFDI_MEDIA_SET(ctx); 3791 CTX_UNLOCK(ctx); 3792 /* falls thru */ 3793 case SIOCGIFMEDIA: 3794 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 3795 break; 3796 case SIOCGI2C: 3797 { 3798 struct ifi2creq i2c; 3799 3800 err = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); 3801 if (err != 0) 3802 break; 3803 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 3804 err = EINVAL; 3805 break; 3806 } 3807 if (i2c.len > sizeof(i2c.data)) { 3808 err = EINVAL; 3809 break; 3810 } 3811 3812 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 3813 err = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); 3814 break; 3815 } 3816 case SIOCSIFCAP: 3817 { 3818 int mask, setmask; 3819 3820 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3821 setmask = 0; 3822 #ifdef TCP_OFFLOAD 3823 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 3824 #endif 3825 setmask |= (mask & IFCAP_FLAGS); 3826 3827 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 3828 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 3829 if ((mask & IFCAP_WOL) && 3830 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 3831 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 3832 if_vlancap(ifp); 3833 /* 3834 * want to ensure that traffic has stopped before we change any of the flags 3835 */ 3836 if (setmask) { 3837 CTX_LOCK(ctx); 3838 bits = if_getdrvflags(ifp); 3839 if (bits & IFF_DRV_RUNNING) 3840 iflib_stop(ctx); 3841 if_togglecapenable(ifp, setmask); 3842 if (bits & IFF_DRV_RUNNING) 3843 iflib_init_locked(ctx); 3844 if_setdrvflags(ifp, bits); 3845 CTX_UNLOCK(ctx); 3846 } 3847 break; 3848 } 3849 case SIOCGPRIVATE_0: 3850 case SIOCSDRVSPEC: 3851 case SIOCGDRVSPEC: 3852 CTX_LOCK(ctx); 3853 err = IFDI_PRIV_IOCTL(ctx, command, data); 3854 CTX_UNLOCK(ctx); 3855 break; 3856 default: 3857 err = ether_ioctl(ifp, command, data); 3858 break; 3859 } 3860 if (reinit) 3861 iflib_if_init(ctx); 3862 return (err); 3863 } 3864 3865 static uint64_t 3866 iflib_if_get_counter(if_t ifp, ift_counter cnt) 3867 { 3868 if_ctx_t ctx = if_getsoftc(ifp); 3869 3870 return (IFDI_GET_COUNTER(ctx, cnt)); 3871 } 3872 3873 /********************************************************************* 3874 * 3875 * OTHER FUNCTIONS EXPORTED TO THE STACK 3876 * 3877 **********************************************************************/ 3878 3879 static void 3880 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 3881 { 3882 if_ctx_t ctx = if_getsoftc(ifp); 3883 3884 if ((void *)ctx != arg) 3885 return; 3886 3887 if ((vtag == 0) || (vtag > 4095)) 3888 return; 3889 3890 CTX_LOCK(ctx); 3891 IFDI_VLAN_REGISTER(ctx, vtag); 3892 /* Re-init to load the changes */ 3893 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 3894 iflib_init_locked(ctx); 3895 CTX_UNLOCK(ctx); 3896 } 3897 3898 static void 3899 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 3900 { 3901 if_ctx_t ctx = if_getsoftc(ifp); 3902 3903 if ((void *)ctx != arg) 3904 return; 3905 3906 if ((vtag == 0) || (vtag > 4095)) 3907 return; 3908 3909 CTX_LOCK(ctx); 3910 IFDI_VLAN_UNREGISTER(ctx, vtag); 3911 /* Re-init to load the changes */ 3912 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 3913 iflib_init_locked(ctx); 3914 CTX_UNLOCK(ctx); 3915 } 3916 3917 static void 3918 iflib_led_func(void *arg, int onoff) 3919 { 3920 if_ctx_t ctx = arg; 3921 3922 CTX_LOCK(ctx); 3923 IFDI_LED_FUNC(ctx, onoff); 3924 CTX_UNLOCK(ctx); 3925 } 3926 3927 /********************************************************************* 3928 * 3929 * BUS FUNCTION DEFINITIONS 3930 * 3931 **********************************************************************/ 3932 3933 int 3934 iflib_device_probe(device_t dev) 3935 { 3936 pci_vendor_info_t *ent; 3937 3938 uint16_t pci_vendor_id, pci_device_id; 3939 uint16_t pci_subvendor_id, pci_subdevice_id; 3940 uint16_t pci_rev_id; 3941 if_shared_ctx_t sctx; 3942 3943 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 3944 return (ENOTSUP); 3945 3946 pci_vendor_id = pci_get_vendor(dev); 3947 pci_device_id = pci_get_device(dev); 3948 pci_subvendor_id = pci_get_subvendor(dev); 3949 pci_subdevice_id = pci_get_subdevice(dev); 3950 pci_rev_id = pci_get_revid(dev); 3951 if (sctx->isc_parse_devinfo != NULL) 3952 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 3953 3954 ent = sctx->isc_vendor_info; 3955 while (ent->pvi_vendor_id != 0) { 3956 if (pci_vendor_id != ent->pvi_vendor_id) { 3957 ent++; 3958 continue; 3959 } 3960 if ((pci_device_id == ent->pvi_device_id) && 3961 ((pci_subvendor_id == ent->pvi_subvendor_id) || 3962 (ent->pvi_subvendor_id == 0)) && 3963 ((pci_subdevice_id == ent->pvi_subdevice_id) || 3964 (ent->pvi_subdevice_id == 0)) && 3965 ((pci_rev_id == ent->pvi_rev_id) || 3966 (ent->pvi_rev_id == 0))) { 3967 3968 device_set_desc_copy(dev, ent->pvi_name); 3969 /* this needs to be changed to zero if the bus probing code 3970 * ever stops re-probing on best match because the sctx 3971 * may have its values over written by register calls 3972 * in subsequent probes 3973 */ 3974 return (BUS_PROBE_DEFAULT); 3975 } 3976 ent++; 3977 } 3978 return (ENXIO); 3979 } 3980 3981 int 3982 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 3983 { 3984 int err, rid, msix, msix_bar; 3985 if_ctx_t ctx; 3986 if_t ifp; 3987 if_softc_ctx_t scctx; 3988 int i; 3989 uint16_t main_txq; 3990 uint16_t main_rxq; 3991 3992 3993 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 3994 3995 if (sc == NULL) { 3996 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 3997 device_set_softc(dev, ctx); 3998 ctx->ifc_flags |= IFC_SC_ALLOCATED; 3999 } 4000 4001 ctx->ifc_sctx = sctx; 4002 ctx->ifc_dev = dev; 4003 ctx->ifc_softc = sc; 4004 4005 if ((err = iflib_register(ctx)) != 0) { 4006 device_printf(dev, "iflib_register failed %d\n", err); 4007 return (err); 4008 } 4009 iflib_add_device_sysctl_pre(ctx); 4010 4011 scctx = &ctx->ifc_softc_ctx; 4012 ifp = ctx->ifc_ifp; 4013 4014 /* 4015 * XXX sanity check that ntxd & nrxd are a power of 2 4016 */ 4017 if (ctx->ifc_sysctl_ntxqs != 0) 4018 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4019 if (ctx->ifc_sysctl_nrxqs != 0) 4020 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4021 4022 for (i = 0; i < sctx->isc_ntxqs; i++) { 4023 if (ctx->ifc_sysctl_ntxds[i] != 0) 4024 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4025 else 4026 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4027 } 4028 4029 for (i = 0; i < sctx->isc_nrxqs; i++) { 4030 if (ctx->ifc_sysctl_nrxds[i] != 0) 4031 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4032 else 4033 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4034 } 4035 4036 for (i = 0; i < sctx->isc_nrxqs; i++) { 4037 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4038 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4039 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4040 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4041 } 4042 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4043 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4044 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4045 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4046 } 4047 } 4048 4049 for (i = 0; i < sctx->isc_ntxqs; i++) { 4050 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4051 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4052 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4053 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4054 } 4055 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4056 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4057 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4058 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4059 } 4060 } 4061 4062 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4063 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4064 return (err); 4065 } 4066 _iflib_pre_assert(scctx); 4067 ctx->ifc_txrx = *scctx->isc_txrx; 4068 4069 #ifdef INVARIANTS 4070 MPASS(scctx->isc_capenable); 4071 if (scctx->isc_capenable & IFCAP_TXCSUM) 4072 MPASS(scctx->isc_tx_csum_flags); 4073 #endif 4074 4075 if_setcapabilities(ifp, scctx->isc_capenable); 4076 if_setcapenable(ifp, scctx->isc_capenable); 4077 4078 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4079 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4080 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4081 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4082 4083 #ifdef ACPI_DMAR 4084 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4085 ctx->ifc_flags |= IFC_DMAR; 4086 #elif !(defined(__i386__) || defined(__amd64__)) 4087 /* set unconditionally for !x86 */ 4088 ctx->ifc_flags |= IFC_DMAR; 4089 #endif 4090 4091 msix_bar = scctx->isc_msix_bar; 4092 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4093 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4094 4095 /* XXX change for per-queue sizes */ 4096 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4097 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4098 for (i = 0; i < sctx->isc_nrxqs; i++) { 4099 if (!powerof2(scctx->isc_nrxd[i])) { 4100 /* round down instead? */ 4101 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4102 err = EINVAL; 4103 goto fail; 4104 } 4105 } 4106 for (i = 0; i < sctx->isc_ntxqs; i++) { 4107 if (!powerof2(scctx->isc_ntxd[i])) { 4108 device_printf(dev, 4109 "# tx descriptors must be a power of 2"); 4110 err = EINVAL; 4111 goto fail; 4112 } 4113 } 4114 4115 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4116 MAX_SINGLE_PACKET_FRACTION) 4117 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4118 MAX_SINGLE_PACKET_FRACTION); 4119 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4120 MAX_SINGLE_PACKET_FRACTION) 4121 scctx->isc_tx_tso_segments_max = max(1, 4122 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4123 4124 /* 4125 * Protect the stack against modern hardware 4126 */ 4127 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4128 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4129 4130 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4131 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4132 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4133 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4134 if (scctx->isc_rss_table_size == 0) 4135 scctx->isc_rss_table_size = 64; 4136 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4137 4138 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4139 /* XXX format name */ 4140 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4141 /* 4142 ** Now setup MSI or MSI/X, should 4143 ** return us the number of supported 4144 ** vectors. (Will be 1 for MSI) 4145 */ 4146 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4147 msix = scctx->isc_vectors; 4148 } else if (scctx->isc_msix_bar != 0) 4149 /* 4150 * The simple fact that isc_msix_bar is not 0 does not mean we 4151 * we have a good value there that is known to work. 4152 */ 4153 msix = iflib_msix_init(ctx); 4154 else { 4155 scctx->isc_vectors = 1; 4156 scctx->isc_ntxqsets = 1; 4157 scctx->isc_nrxqsets = 1; 4158 scctx->isc_intr = IFLIB_INTR_LEGACY; 4159 msix = 0; 4160 } 4161 /* Get memory for the station queues */ 4162 if ((err = iflib_queues_alloc(ctx))) { 4163 device_printf(dev, "Unable to allocate queue memory\n"); 4164 goto fail; 4165 } 4166 4167 if ((err = iflib_qset_structures_setup(ctx))) { 4168 device_printf(dev, "qset structure setup failed %d\n", err); 4169 goto fail_queues; 4170 } 4171 4172 /* 4173 * Group taskqueues aren't properly set up until SMP is started, 4174 * so we disable interrupts until we can handle them post 4175 * SI_SUB_SMP. 4176 * 4177 * XXX: disabling interrupts doesn't actually work, at least for 4178 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4179 * we do null handling and depend on this not causing too large an 4180 * interrupt storm. 4181 */ 4182 IFDI_INTR_DISABLE(ctx); 4183 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4184 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4185 goto fail_intr_free; 4186 } 4187 if (msix <= 1) { 4188 rid = 0; 4189 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4190 MPASS(msix == 1); 4191 rid = 1; 4192 } 4193 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4194 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4195 goto fail_intr_free; 4196 } 4197 } 4198 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4199 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4200 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4201 goto fail_detach; 4202 } 4203 if ((err = iflib_netmap_attach(ctx))) { 4204 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4205 goto fail_detach; 4206 } 4207 *ctxp = ctx; 4208 4209 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4210 iflib_add_device_sysctl_post(ctx); 4211 ctx->ifc_flags |= IFC_INIT_DONE; 4212 return (0); 4213 fail_detach: 4214 ether_ifdetach(ctx->ifc_ifp); 4215 fail_intr_free: 4216 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4217 pci_release_msi(ctx->ifc_dev); 4218 fail_queues: 4219 /* XXX free queues */ 4220 fail: 4221 IFDI_DETACH(ctx); 4222 return (err); 4223 } 4224 4225 int 4226 iflib_device_attach(device_t dev) 4227 { 4228 if_ctx_t ctx; 4229 if_shared_ctx_t sctx; 4230 4231 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4232 return (ENOTSUP); 4233 4234 pci_enable_busmaster(dev); 4235 4236 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4237 } 4238 4239 int 4240 iflib_device_deregister(if_ctx_t ctx) 4241 { 4242 if_t ifp = ctx->ifc_ifp; 4243 iflib_txq_t txq; 4244 iflib_rxq_t rxq; 4245 device_t dev = ctx->ifc_dev; 4246 int i; 4247 struct taskqgroup *tqg; 4248 4249 /* Make sure VLANS are not using driver */ 4250 if (if_vlantrunkinuse(ifp)) { 4251 device_printf(dev,"Vlan in use, detach first\n"); 4252 return (EBUSY); 4253 } 4254 4255 CTX_LOCK(ctx); 4256 ctx->ifc_in_detach = 1; 4257 iflib_stop(ctx); 4258 CTX_UNLOCK(ctx); 4259 4260 /* Unregister VLAN events */ 4261 if (ctx->ifc_vlan_attach_event != NULL) 4262 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4263 if (ctx->ifc_vlan_detach_event != NULL) 4264 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4265 4266 iflib_netmap_detach(ifp); 4267 ether_ifdetach(ifp); 4268 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4269 CTX_LOCK_DESTROY(ctx); 4270 if (ctx->ifc_led_dev != NULL) 4271 led_destroy(ctx->ifc_led_dev); 4272 /* XXX drain any dependent tasks */ 4273 tqg = qgroup_if_io_tqg; 4274 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4275 callout_drain(&txq->ift_timer); 4276 if (txq->ift_task.gt_uniq != NULL) 4277 taskqgroup_detach(tqg, &txq->ift_task); 4278 } 4279 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4280 if (rxq->ifr_task.gt_uniq != NULL) 4281 taskqgroup_detach(tqg, &rxq->ifr_task); 4282 } 4283 tqg = qgroup_if_config_tqg; 4284 if (ctx->ifc_admin_task.gt_uniq != NULL) 4285 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4286 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4287 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4288 4289 IFDI_DETACH(ctx); 4290 device_set_softc(ctx->ifc_dev, NULL); 4291 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4292 pci_release_msi(dev); 4293 } 4294 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4295 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4296 } 4297 if (ctx->ifc_msix_mem != NULL) { 4298 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4299 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4300 ctx->ifc_msix_mem = NULL; 4301 } 4302 4303 bus_generic_detach(dev); 4304 if_free(ifp); 4305 4306 iflib_tx_structures_free(ctx); 4307 iflib_rx_structures_free(ctx); 4308 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4309 free(ctx->ifc_softc, M_IFLIB); 4310 free(ctx, M_IFLIB); 4311 return (0); 4312 } 4313 4314 4315 int 4316 iflib_device_detach(device_t dev) 4317 { 4318 if_ctx_t ctx = device_get_softc(dev); 4319 4320 return (iflib_device_deregister(ctx)); 4321 } 4322 4323 int 4324 iflib_device_suspend(device_t dev) 4325 { 4326 if_ctx_t ctx = device_get_softc(dev); 4327 4328 CTX_LOCK(ctx); 4329 IFDI_SUSPEND(ctx); 4330 CTX_UNLOCK(ctx); 4331 4332 return bus_generic_suspend(dev); 4333 } 4334 int 4335 iflib_device_shutdown(device_t dev) 4336 { 4337 if_ctx_t ctx = device_get_softc(dev); 4338 4339 CTX_LOCK(ctx); 4340 IFDI_SHUTDOWN(ctx); 4341 CTX_UNLOCK(ctx); 4342 4343 return bus_generic_suspend(dev); 4344 } 4345 4346 4347 int 4348 iflib_device_resume(device_t dev) 4349 { 4350 if_ctx_t ctx = device_get_softc(dev); 4351 iflib_txq_t txq = ctx->ifc_txqs; 4352 4353 CTX_LOCK(ctx); 4354 IFDI_RESUME(ctx); 4355 iflib_init_locked(ctx); 4356 CTX_UNLOCK(ctx); 4357 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4358 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4359 4360 return (bus_generic_resume(dev)); 4361 } 4362 4363 int 4364 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4365 { 4366 int error; 4367 if_ctx_t ctx = device_get_softc(dev); 4368 4369 CTX_LOCK(ctx); 4370 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4371 CTX_UNLOCK(ctx); 4372 4373 return (error); 4374 } 4375 4376 void 4377 iflib_device_iov_uninit(device_t dev) 4378 { 4379 if_ctx_t ctx = device_get_softc(dev); 4380 4381 CTX_LOCK(ctx); 4382 IFDI_IOV_UNINIT(ctx); 4383 CTX_UNLOCK(ctx); 4384 } 4385 4386 int 4387 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 4388 { 4389 int error; 4390 if_ctx_t ctx = device_get_softc(dev); 4391 4392 CTX_LOCK(ctx); 4393 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 4394 CTX_UNLOCK(ctx); 4395 4396 return (error); 4397 } 4398 4399 /********************************************************************* 4400 * 4401 * MODULE FUNCTION DEFINITIONS 4402 * 4403 **********************************************************************/ 4404 4405 /* 4406 * - Start a fast taskqueue thread for each core 4407 * - Start a taskqueue for control operations 4408 */ 4409 static int 4410 iflib_module_init(void) 4411 { 4412 return (0); 4413 } 4414 4415 static int 4416 iflib_module_event_handler(module_t mod, int what, void *arg) 4417 { 4418 int err; 4419 4420 switch (what) { 4421 case MOD_LOAD: 4422 if ((err = iflib_module_init()) != 0) 4423 return (err); 4424 break; 4425 case MOD_UNLOAD: 4426 return (EBUSY); 4427 default: 4428 return (EOPNOTSUPP); 4429 } 4430 4431 return (0); 4432 } 4433 4434 /********************************************************************* 4435 * 4436 * PUBLIC FUNCTION DEFINITIONS 4437 * ordered as in iflib.h 4438 * 4439 **********************************************************************/ 4440 4441 4442 static void 4443 _iflib_assert(if_shared_ctx_t sctx) 4444 { 4445 MPASS(sctx->isc_tx_maxsize); 4446 MPASS(sctx->isc_tx_maxsegsize); 4447 4448 MPASS(sctx->isc_rx_maxsize); 4449 MPASS(sctx->isc_rx_nsegments); 4450 MPASS(sctx->isc_rx_maxsegsize); 4451 4452 MPASS(sctx->isc_nrxd_min[0]); 4453 MPASS(sctx->isc_nrxd_max[0]); 4454 MPASS(sctx->isc_nrxd_default[0]); 4455 MPASS(sctx->isc_ntxd_min[0]); 4456 MPASS(sctx->isc_ntxd_max[0]); 4457 MPASS(sctx->isc_ntxd_default[0]); 4458 } 4459 4460 static void 4461 _iflib_pre_assert(if_softc_ctx_t scctx) 4462 { 4463 4464 MPASS(scctx->isc_txrx->ift_txd_encap); 4465 MPASS(scctx->isc_txrx->ift_txd_flush); 4466 MPASS(scctx->isc_txrx->ift_txd_credits_update); 4467 MPASS(scctx->isc_txrx->ift_rxd_available); 4468 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 4469 MPASS(scctx->isc_txrx->ift_rxd_refill); 4470 MPASS(scctx->isc_txrx->ift_rxd_flush); 4471 } 4472 4473 static int 4474 iflib_register(if_ctx_t ctx) 4475 { 4476 if_shared_ctx_t sctx = ctx->ifc_sctx; 4477 driver_t *driver = sctx->isc_driver; 4478 device_t dev = ctx->ifc_dev; 4479 if_t ifp; 4480 4481 _iflib_assert(sctx); 4482 4483 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 4484 4485 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 4486 if (ifp == NULL) { 4487 device_printf(dev, "can not allocate ifnet structure\n"); 4488 return (ENOMEM); 4489 } 4490 4491 /* 4492 * Initialize our context's device specific methods 4493 */ 4494 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 4495 kobj_class_compile((kobj_class_t) driver); 4496 driver->refs++; 4497 4498 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 4499 if_setsoftc(ifp, ctx); 4500 if_setdev(ifp, dev); 4501 if_setinitfn(ifp, iflib_if_init); 4502 if_setioctlfn(ifp, iflib_if_ioctl); 4503 if_settransmitfn(ifp, iflib_if_transmit); 4504 if_setqflushfn(ifp, iflib_if_qflush); 4505 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 4506 4507 ctx->ifc_vlan_attach_event = 4508 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 4509 EVENTHANDLER_PRI_FIRST); 4510 ctx->ifc_vlan_detach_event = 4511 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 4512 EVENTHANDLER_PRI_FIRST); 4513 4514 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 4515 iflib_media_change, iflib_media_status); 4516 4517 return (0); 4518 } 4519 4520 4521 static int 4522 iflib_queues_alloc(if_ctx_t ctx) 4523 { 4524 if_shared_ctx_t sctx = ctx->ifc_sctx; 4525 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4526 device_t dev = ctx->ifc_dev; 4527 int nrxqsets = scctx->isc_nrxqsets; 4528 int ntxqsets = scctx->isc_ntxqsets; 4529 iflib_txq_t txq; 4530 iflib_rxq_t rxq; 4531 iflib_fl_t fl = NULL; 4532 int i, j, cpu, err, txconf, rxconf; 4533 iflib_dma_info_t ifdip; 4534 uint32_t *rxqsizes = scctx->isc_rxqsizes; 4535 uint32_t *txqsizes = scctx->isc_txqsizes; 4536 uint8_t nrxqs = sctx->isc_nrxqs; 4537 uint8_t ntxqs = sctx->isc_ntxqs; 4538 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 4539 caddr_t *vaddrs; 4540 uint64_t *paddrs; 4541 struct ifmp_ring **brscp; 4542 4543 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 4544 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 4545 4546 brscp = NULL; 4547 txq = NULL; 4548 rxq = NULL; 4549 4550 /* Allocate the TX ring struct memory */ 4551 if (!(txq = 4552 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 4553 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4554 device_printf(dev, "Unable to allocate TX ring memory\n"); 4555 err = ENOMEM; 4556 goto fail; 4557 } 4558 4559 /* Now allocate the RX */ 4560 if (!(rxq = 4561 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 4562 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4563 device_printf(dev, "Unable to allocate RX ring memory\n"); 4564 err = ENOMEM; 4565 goto rx_fail; 4566 } 4567 4568 ctx->ifc_txqs = txq; 4569 ctx->ifc_rxqs = rxq; 4570 4571 /* 4572 * XXX handle allocation failure 4573 */ 4574 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 4575 /* Set up some basics */ 4576 4577 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4578 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4579 err = ENOMEM; 4580 goto err_tx_desc; 4581 } 4582 txq->ift_ifdi = ifdip; 4583 for (j = 0; j < ntxqs; j++, ifdip++) { 4584 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4585 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4586 err = ENOMEM; 4587 goto err_tx_desc; 4588 } 4589 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 4590 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 4591 } 4592 txq->ift_ctx = ctx; 4593 txq->ift_id = i; 4594 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 4595 txq->ift_br_offset = 1; 4596 } else { 4597 txq->ift_br_offset = 0; 4598 } 4599 /* XXX fix this */ 4600 txq->ift_timer.c_cpu = cpu; 4601 4602 if (iflib_txsd_alloc(txq)) { 4603 device_printf(dev, "Critical Failure setting up TX buffers\n"); 4604 err = ENOMEM; 4605 goto err_tx_desc; 4606 } 4607 4608 /* Initialize the TX lock */ 4609 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 4610 device_get_nameunit(dev), txq->ift_id); 4611 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 4612 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 4613 4614 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 4615 device_get_nameunit(dev), txq->ift_id); 4616 4617 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 4618 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 4619 if (err) { 4620 /* XXX free any allocated rings */ 4621 device_printf(dev, "Unable to allocate buf_ring\n"); 4622 goto err_tx_desc; 4623 } 4624 } 4625 4626 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 4627 /* Set up some basics */ 4628 4629 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4630 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4631 err = ENOMEM; 4632 goto err_tx_desc; 4633 } 4634 4635 rxq->ifr_ifdi = ifdip; 4636 /* XXX this needs to be changed if #rx queues != #tx queues */ 4637 rxq->ifr_ntxqirq = 1; 4638 rxq->ifr_txqid[0] = i; 4639 for (j = 0; j < nrxqs; j++, ifdip++) { 4640 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4641 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4642 err = ENOMEM; 4643 goto err_tx_desc; 4644 } 4645 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 4646 } 4647 rxq->ifr_ctx = ctx; 4648 rxq->ifr_id = i; 4649 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 4650 rxq->ifr_fl_offset = 1; 4651 } else { 4652 rxq->ifr_fl_offset = 0; 4653 } 4654 rxq->ifr_nfl = nfree_lists; 4655 if (!(fl = 4656 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 4657 device_printf(dev, "Unable to allocate free list memory\n"); 4658 err = ENOMEM; 4659 goto err_tx_desc; 4660 } 4661 rxq->ifr_fl = fl; 4662 for (j = 0; j < nfree_lists; j++) { 4663 fl[j].ifl_rxq = rxq; 4664 fl[j].ifl_id = j; 4665 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 4666 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 4667 } 4668 /* Allocate receive buffers for the ring*/ 4669 if (iflib_rxsd_alloc(rxq)) { 4670 device_printf(dev, 4671 "Critical Failure setting up receive buffers\n"); 4672 err = ENOMEM; 4673 goto err_rx_desc; 4674 } 4675 } 4676 4677 /* TXQs */ 4678 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4679 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4680 for (i = 0; i < ntxqsets; i++) { 4681 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 4682 4683 for (j = 0; j < ntxqs; j++, di++) { 4684 vaddrs[i*ntxqs + j] = di->idi_vaddr; 4685 paddrs[i*ntxqs + j] = di->idi_paddr; 4686 } 4687 } 4688 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 4689 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4690 iflib_tx_structures_free(ctx); 4691 free(vaddrs, M_IFLIB); 4692 free(paddrs, M_IFLIB); 4693 goto err_rx_desc; 4694 } 4695 free(vaddrs, M_IFLIB); 4696 free(paddrs, M_IFLIB); 4697 4698 /* RXQs */ 4699 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4700 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4701 for (i = 0; i < nrxqsets; i++) { 4702 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 4703 4704 for (j = 0; j < nrxqs; j++, di++) { 4705 vaddrs[i*nrxqs + j] = di->idi_vaddr; 4706 paddrs[i*nrxqs + j] = di->idi_paddr; 4707 } 4708 } 4709 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 4710 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4711 iflib_tx_structures_free(ctx); 4712 free(vaddrs, M_IFLIB); 4713 free(paddrs, M_IFLIB); 4714 goto err_rx_desc; 4715 } 4716 free(vaddrs, M_IFLIB); 4717 free(paddrs, M_IFLIB); 4718 4719 return (0); 4720 4721 /* XXX handle allocation failure changes */ 4722 err_rx_desc: 4723 err_tx_desc: 4724 if (ctx->ifc_rxqs != NULL) 4725 free(ctx->ifc_rxqs, M_IFLIB); 4726 ctx->ifc_rxqs = NULL; 4727 if (ctx->ifc_txqs != NULL) 4728 free(ctx->ifc_txqs, M_IFLIB); 4729 ctx->ifc_txqs = NULL; 4730 rx_fail: 4731 if (brscp != NULL) 4732 free(brscp, M_IFLIB); 4733 if (rxq != NULL) 4734 free(rxq, M_IFLIB); 4735 if (txq != NULL) 4736 free(txq, M_IFLIB); 4737 fail: 4738 return (err); 4739 } 4740 4741 static int 4742 iflib_tx_structures_setup(if_ctx_t ctx) 4743 { 4744 iflib_txq_t txq = ctx->ifc_txqs; 4745 int i; 4746 4747 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4748 iflib_txq_setup(txq); 4749 4750 return (0); 4751 } 4752 4753 static void 4754 iflib_tx_structures_free(if_ctx_t ctx) 4755 { 4756 iflib_txq_t txq = ctx->ifc_txqs; 4757 int i, j; 4758 4759 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 4760 iflib_txq_destroy(txq); 4761 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 4762 iflib_dma_free(&txq->ift_ifdi[j]); 4763 } 4764 free(ctx->ifc_txqs, M_IFLIB); 4765 ctx->ifc_txqs = NULL; 4766 IFDI_QUEUES_FREE(ctx); 4767 } 4768 4769 /********************************************************************* 4770 * 4771 * Initialize all receive rings. 4772 * 4773 **********************************************************************/ 4774 static int 4775 iflib_rx_structures_setup(if_ctx_t ctx) 4776 { 4777 iflib_rxq_t rxq = ctx->ifc_rxqs; 4778 int q; 4779 #if defined(INET6) || defined(INET) 4780 int i, err; 4781 #endif 4782 4783 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 4784 #if defined(INET6) || defined(INET) 4785 tcp_lro_free(&rxq->ifr_lc); 4786 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 4787 TCP_LRO_ENTRIES, min(1024, 4788 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 4789 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 4790 goto fail; 4791 } 4792 rxq->ifr_lro_enabled = TRUE; 4793 #endif 4794 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 4795 } 4796 return (0); 4797 #if defined(INET6) || defined(INET) 4798 fail: 4799 /* 4800 * Free RX software descriptors allocated so far, we will only handle 4801 * the rings that completed, the failing case will have 4802 * cleaned up for itself. 'q' failed, so its the terminus. 4803 */ 4804 rxq = ctx->ifc_rxqs; 4805 for (i = 0; i < q; ++i, rxq++) { 4806 iflib_rx_sds_free(rxq); 4807 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 4808 } 4809 return (err); 4810 #endif 4811 } 4812 4813 /********************************************************************* 4814 * 4815 * Free all receive rings. 4816 * 4817 **********************************************************************/ 4818 static void 4819 iflib_rx_structures_free(if_ctx_t ctx) 4820 { 4821 iflib_rxq_t rxq = ctx->ifc_rxqs; 4822 4823 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 4824 iflib_rx_sds_free(rxq); 4825 } 4826 } 4827 4828 static int 4829 iflib_qset_structures_setup(if_ctx_t ctx) 4830 { 4831 int err; 4832 4833 if ((err = iflib_tx_structures_setup(ctx)) != 0) 4834 return (err); 4835 4836 if ((err = iflib_rx_structures_setup(ctx)) != 0) { 4837 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 4838 iflib_tx_structures_free(ctx); 4839 iflib_rx_structures_free(ctx); 4840 } 4841 return (err); 4842 } 4843 4844 int 4845 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 4846 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name) 4847 { 4848 4849 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 4850 } 4851 4852 static int 4853 find_nth(if_ctx_t ctx, cpuset_t *cpus, int qid) 4854 { 4855 int i, cpuid, eqid, count; 4856 4857 CPU_COPY(&ctx->ifc_cpus, cpus); 4858 count = CPU_COUNT(&ctx->ifc_cpus); 4859 eqid = qid % count; 4860 /* clear up to the qid'th bit */ 4861 for (i = 0; i < eqid; i++) { 4862 cpuid = CPU_FFS(cpus); 4863 MPASS(cpuid != 0); 4864 CPU_CLR(cpuid-1, cpus); 4865 } 4866 cpuid = CPU_FFS(cpus); 4867 MPASS(cpuid != 0); 4868 return (cpuid-1); 4869 } 4870 4871 int 4872 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 4873 iflib_intr_type_t type, driver_filter_t *filter, 4874 void *filter_arg, int qid, char *name) 4875 { 4876 struct grouptask *gtask; 4877 struct taskqgroup *tqg; 4878 iflib_filter_info_t info; 4879 cpuset_t cpus; 4880 gtask_fn_t *fn; 4881 int tqrid, err, cpuid; 4882 driver_filter_t *intr_fast; 4883 void *q; 4884 4885 info = &ctx->ifc_filter_info; 4886 tqrid = rid; 4887 4888 switch (type) { 4889 /* XXX merge tx/rx for netmap? */ 4890 case IFLIB_INTR_TX: 4891 q = &ctx->ifc_txqs[qid]; 4892 info = &ctx->ifc_txqs[qid].ift_filter_info; 4893 gtask = &ctx->ifc_txqs[qid].ift_task; 4894 tqg = qgroup_if_io_tqg; 4895 fn = _task_fn_tx; 4896 intr_fast = iflib_fast_intr; 4897 GROUPTASK_INIT(gtask, 0, fn, q); 4898 break; 4899 case IFLIB_INTR_RX: 4900 q = &ctx->ifc_rxqs[qid]; 4901 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 4902 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4903 tqg = qgroup_if_io_tqg; 4904 fn = _task_fn_rx; 4905 intr_fast = iflib_fast_intr; 4906 GROUPTASK_INIT(gtask, 0, fn, q); 4907 break; 4908 case IFLIB_INTR_RXTX: 4909 q = &ctx->ifc_rxqs[qid]; 4910 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 4911 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4912 tqg = qgroup_if_io_tqg; 4913 fn = _task_fn_rx; 4914 intr_fast = iflib_fast_intr_rxtx; 4915 GROUPTASK_INIT(gtask, 0, fn, q); 4916 break; 4917 case IFLIB_INTR_ADMIN: 4918 q = ctx; 4919 tqrid = -1; 4920 info = &ctx->ifc_filter_info; 4921 gtask = &ctx->ifc_admin_task; 4922 tqg = qgroup_if_config_tqg; 4923 fn = _task_fn_admin; 4924 intr_fast = iflib_fast_intr_ctx; 4925 break; 4926 default: 4927 panic("unknown net intr type"); 4928 } 4929 4930 info->ifi_filter = filter; 4931 info->ifi_filter_arg = filter_arg; 4932 info->ifi_task = gtask; 4933 info->ifi_ctx = q; 4934 4935 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 4936 if (err != 0) { 4937 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 4938 return (err); 4939 } 4940 if (type == IFLIB_INTR_ADMIN) 4941 return (0); 4942 4943 if (tqrid != -1) { 4944 cpuid = find_nth(ctx, &cpus, qid); 4945 taskqgroup_attach_cpu(tqg, gtask, q, cpuid, irq->ii_rid, name); 4946 } else { 4947 taskqgroup_attach(tqg, gtask, q, tqrid, name); 4948 } 4949 4950 return (0); 4951 } 4952 4953 void 4954 iflib_softirq_alloc_generic(if_ctx_t ctx, int rid, iflib_intr_type_t type, void *arg, int qid, char *name) 4955 { 4956 struct grouptask *gtask; 4957 struct taskqgroup *tqg; 4958 gtask_fn_t *fn; 4959 void *q; 4960 4961 switch (type) { 4962 case IFLIB_INTR_TX: 4963 q = &ctx->ifc_txqs[qid]; 4964 gtask = &ctx->ifc_txqs[qid].ift_task; 4965 tqg = qgroup_if_io_tqg; 4966 fn = _task_fn_tx; 4967 break; 4968 case IFLIB_INTR_RX: 4969 q = &ctx->ifc_rxqs[qid]; 4970 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4971 tqg = qgroup_if_io_tqg; 4972 fn = _task_fn_rx; 4973 break; 4974 case IFLIB_INTR_IOV: 4975 q = ctx; 4976 gtask = &ctx->ifc_vflr_task; 4977 tqg = qgroup_if_config_tqg; 4978 rid = -1; 4979 fn = _task_fn_iov; 4980 break; 4981 default: 4982 panic("unknown net intr type"); 4983 } 4984 GROUPTASK_INIT(gtask, 0, fn, q); 4985 taskqgroup_attach(tqg, gtask, q, rid, name); 4986 } 4987 4988 void 4989 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 4990 { 4991 if (irq->ii_tag) 4992 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 4993 4994 if (irq->ii_res) 4995 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 4996 } 4997 4998 static int 4999 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name) 5000 { 5001 iflib_txq_t txq = ctx->ifc_txqs; 5002 iflib_rxq_t rxq = ctx->ifc_rxqs; 5003 if_irq_t irq = &ctx->ifc_legacy_irq; 5004 iflib_filter_info_t info; 5005 struct grouptask *gtask; 5006 struct taskqgroup *tqg; 5007 gtask_fn_t *fn; 5008 int tqrid; 5009 void *q; 5010 int err; 5011 5012 q = &ctx->ifc_rxqs[0]; 5013 info = &rxq[0].ifr_filter_info; 5014 gtask = &rxq[0].ifr_task; 5015 tqg = qgroup_if_io_tqg; 5016 tqrid = irq->ii_rid = *rid; 5017 fn = _task_fn_rx; 5018 5019 ctx->ifc_flags |= IFC_LEGACY; 5020 info->ifi_filter = filter; 5021 info->ifi_filter_arg = filter_arg; 5022 info->ifi_task = gtask; 5023 info->ifi_ctx = ctx; 5024 5025 /* We allocate a single interrupt resource */ 5026 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5027 return (err); 5028 GROUPTASK_INIT(gtask, 0, fn, q); 5029 taskqgroup_attach(tqg, gtask, q, tqrid, name); 5030 5031 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5032 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, tqrid, "tx"); 5033 return (0); 5034 } 5035 5036 void 5037 iflib_led_create(if_ctx_t ctx) 5038 { 5039 5040 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5041 device_get_nameunit(ctx->ifc_dev)); 5042 } 5043 5044 void 5045 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5046 { 5047 5048 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5049 } 5050 5051 void 5052 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5053 { 5054 5055 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5056 } 5057 5058 void 5059 iflib_admin_intr_deferred(if_ctx_t ctx) 5060 { 5061 #ifdef INVARIANTS 5062 struct grouptask *gtask; 5063 5064 gtask = &ctx->ifc_admin_task; 5065 MPASS(gtask->gt_taskqueue != NULL); 5066 #endif 5067 5068 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5069 } 5070 5071 void 5072 iflib_iov_intr_deferred(if_ctx_t ctx) 5073 { 5074 5075 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5076 } 5077 5078 void 5079 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5080 { 5081 5082 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5083 } 5084 5085 void 5086 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn, 5087 char *name) 5088 { 5089 5090 GROUPTASK_INIT(gtask, 0, fn, ctx); 5091 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5092 } 5093 5094 void 5095 iflib_config_gtask_deinit(struct grouptask *gtask) 5096 { 5097 5098 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5099 } 5100 5101 void 5102 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5103 { 5104 if_t ifp = ctx->ifc_ifp; 5105 iflib_txq_t txq = ctx->ifc_txqs; 5106 5107 if_setbaudrate(ifp, baudrate); 5108 if (baudrate >= IF_Gbps(10)) 5109 ctx->ifc_flags |= IFC_PREFETCH; 5110 5111 /* If link down, disable watchdog */ 5112 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5113 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5114 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5115 } 5116 ctx->ifc_link_state = link_state; 5117 if_link_state_change(ifp, link_state); 5118 } 5119 5120 static int 5121 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5122 { 5123 int credits; 5124 #ifdef INVARIANTS 5125 int credits_pre = txq->ift_cidx_processed; 5126 #endif 5127 5128 if (ctx->isc_txd_credits_update == NULL) 5129 return (0); 5130 5131 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5132 return (0); 5133 5134 txq->ift_processed += credits; 5135 txq->ift_cidx_processed += credits; 5136 5137 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5138 if (txq->ift_cidx_processed >= txq->ift_size) 5139 txq->ift_cidx_processed -= txq->ift_size; 5140 return (credits); 5141 } 5142 5143 static int 5144 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5145 { 5146 5147 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5148 budget)); 5149 } 5150 5151 void 5152 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5153 const char *description, if_int_delay_info_t info, 5154 int offset, int value) 5155 { 5156 info->iidi_ctx = ctx; 5157 info->iidi_offset = offset; 5158 info->iidi_value = value; 5159 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5160 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5161 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5162 info, 0, iflib_sysctl_int_delay, "I", description); 5163 } 5164 5165 struct mtx * 5166 iflib_ctx_lock_get(if_ctx_t ctx) 5167 { 5168 5169 return (&ctx->ifc_mtx); 5170 } 5171 5172 static int 5173 iflib_msix_init(if_ctx_t ctx) 5174 { 5175 device_t dev = ctx->ifc_dev; 5176 if_shared_ctx_t sctx = ctx->ifc_sctx; 5177 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5178 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5179 int iflib_num_tx_queues, iflib_num_rx_queues; 5180 int err, admincnt, bar; 5181 5182 iflib_num_tx_queues = scctx->isc_ntxqsets; 5183 iflib_num_rx_queues = scctx->isc_nrxqsets; 5184 5185 device_printf(dev, "msix_init qsets capped at %d\n", iflib_num_tx_queues); 5186 5187 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5188 admincnt = sctx->isc_admin_intrcnt; 5189 /* Override by tuneable */ 5190 if (enable_msix == 0) 5191 goto msi; 5192 5193 /* 5194 ** When used in a virtualized environment 5195 ** PCI BUSMASTER capability may not be set 5196 ** so explicity set it here and rewrite 5197 ** the ENABLE in the MSIX control register 5198 ** at this point to cause the host to 5199 ** successfully initialize us. 5200 */ 5201 { 5202 int msix_ctrl, rid; 5203 5204 pci_enable_busmaster(dev); 5205 rid = 0; 5206 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) { 5207 rid += PCIR_MSIX_CTRL; 5208 msix_ctrl = pci_read_config(dev, rid, 2); 5209 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 5210 pci_write_config(dev, rid, msix_ctrl, 2); 5211 } else { 5212 device_printf(dev, "PCIY_MSIX capability not found; " 5213 "or rid %d == 0.\n", rid); 5214 goto msi; 5215 } 5216 } 5217 5218 /* 5219 * bar == -1 => "trust me I know what I'm doing" 5220 * https://www.youtube.com/watch?v=nnwWKkNau4I 5221 * Some drivers are for hardware that is so shoddily 5222 * documented that no one knows which bars are which 5223 * so the developer has to map all bars. This hack 5224 * allows shoddy garbage to use msix in this framework. 5225 */ 5226 if (bar != -1) { 5227 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5228 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5229 if (ctx->ifc_msix_mem == NULL) { 5230 /* May not be enabled */ 5231 device_printf(dev, "Unable to map MSIX table \n"); 5232 goto msi; 5233 } 5234 } 5235 /* First try MSI/X */ 5236 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5237 device_printf(dev, "System has MSIX disabled \n"); 5238 bus_release_resource(dev, SYS_RES_MEMORY, 5239 bar, ctx->ifc_msix_mem); 5240 ctx->ifc_msix_mem = NULL; 5241 goto msi; 5242 } 5243 #if IFLIB_DEBUG 5244 /* use only 1 qset in debug mode */ 5245 queuemsgs = min(msgs - admincnt, 1); 5246 #else 5247 queuemsgs = msgs - admincnt; 5248 #endif 5249 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) == 0) { 5250 #ifdef RSS 5251 queues = imin(queuemsgs, rss_getnumbuckets()); 5252 #else 5253 queues = queuemsgs; 5254 #endif 5255 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 5256 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 5257 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 5258 } else { 5259 device_printf(dev, "Unable to fetch CPU list\n"); 5260 /* Figure out a reasonable auto config value */ 5261 queues = min(queuemsgs, mp_ncpus); 5262 } 5263 #ifdef RSS 5264 /* If we're doing RSS, clamp at the number of RSS buckets */ 5265 if (queues > rss_getnumbuckets()) 5266 queues = rss_getnumbuckets(); 5267 #endif 5268 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 5269 rx_queues = iflib_num_rx_queues; 5270 else 5271 rx_queues = queues; 5272 /* 5273 * We want this to be all logical CPUs by default 5274 */ 5275 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 5276 tx_queues = iflib_num_tx_queues; 5277 else 5278 tx_queues = mp_ncpus; 5279 5280 if (ctx->ifc_sysctl_qs_eq_override == 0) { 5281 #ifdef INVARIANTS 5282 if (tx_queues != rx_queues) 5283 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 5284 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 5285 #endif 5286 tx_queues = min(rx_queues, tx_queues); 5287 rx_queues = min(rx_queues, tx_queues); 5288 } 5289 5290 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 5291 5292 vectors = rx_queues + admincnt; 5293 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 5294 device_printf(dev, 5295 "Using MSIX interrupts with %d vectors\n", vectors); 5296 scctx->isc_vectors = vectors; 5297 scctx->isc_nrxqsets = rx_queues; 5298 scctx->isc_ntxqsets = tx_queues; 5299 scctx->isc_intr = IFLIB_INTR_MSIX; 5300 5301 return (vectors); 5302 } else { 5303 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 5304 } 5305 msi: 5306 vectors = pci_msi_count(dev); 5307 scctx->isc_nrxqsets = 1; 5308 scctx->isc_ntxqsets = 1; 5309 scctx->isc_vectors = vectors; 5310 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 5311 device_printf(dev,"Using an MSI interrupt\n"); 5312 scctx->isc_intr = IFLIB_INTR_MSI; 5313 } else { 5314 device_printf(dev,"Using a Legacy interrupt\n"); 5315 scctx->isc_intr = IFLIB_INTR_LEGACY; 5316 } 5317 5318 return (vectors); 5319 } 5320 5321 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 5322 5323 static int 5324 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 5325 { 5326 int rc; 5327 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 5328 struct sbuf *sb; 5329 char *ring_state = "UNKNOWN"; 5330 5331 /* XXX needed ? */ 5332 rc = sysctl_wire_old_buffer(req, 0); 5333 MPASS(rc == 0); 5334 if (rc != 0) 5335 return (rc); 5336 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 5337 MPASS(sb != NULL); 5338 if (sb == NULL) 5339 return (ENOMEM); 5340 if (state[3] <= 3) 5341 ring_state = ring_states[state[3]]; 5342 5343 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 5344 state[0], state[1], state[2], ring_state); 5345 rc = sbuf_finish(sb); 5346 sbuf_delete(sb); 5347 return(rc); 5348 } 5349 5350 enum iflib_ndesc_handler { 5351 IFLIB_NTXD_HANDLER, 5352 IFLIB_NRXD_HANDLER, 5353 }; 5354 5355 static int 5356 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 5357 { 5358 if_ctx_t ctx = (void *)arg1; 5359 enum iflib_ndesc_handler type = arg2; 5360 char buf[256] = {0}; 5361 qidx_t *ndesc; 5362 char *p, *next; 5363 int nqs, rc, i; 5364 5365 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 5366 5367 nqs = 8; 5368 switch(type) { 5369 case IFLIB_NTXD_HANDLER: 5370 ndesc = ctx->ifc_sysctl_ntxds; 5371 if (ctx->ifc_sctx) 5372 nqs = ctx->ifc_sctx->isc_ntxqs; 5373 break; 5374 case IFLIB_NRXD_HANDLER: 5375 ndesc = ctx->ifc_sysctl_nrxds; 5376 if (ctx->ifc_sctx) 5377 nqs = ctx->ifc_sctx->isc_nrxqs; 5378 break; 5379 } 5380 if (nqs == 0) 5381 nqs = 8; 5382 5383 for (i=0; i<8; i++) { 5384 if (i >= nqs) 5385 break; 5386 if (i) 5387 strcat(buf, ","); 5388 sprintf(strchr(buf, 0), "%d", ndesc[i]); 5389 } 5390 5391 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 5392 if (rc || req->newptr == NULL) 5393 return rc; 5394 5395 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 5396 i++, p = strsep(&next, " ,")) { 5397 ndesc[i] = strtoul(p, NULL, 10); 5398 } 5399 5400 return(rc); 5401 } 5402 5403 #define NAME_BUFLEN 32 5404 static void 5405 iflib_add_device_sysctl_pre(if_ctx_t ctx) 5406 { 5407 device_t dev = iflib_get_dev(ctx); 5408 struct sysctl_oid_list *child, *oid_list; 5409 struct sysctl_ctx_list *ctx_list; 5410 struct sysctl_oid *node; 5411 5412 ctx_list = device_get_sysctl_ctx(dev); 5413 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 5414 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 5415 CTLFLAG_RD, NULL, "IFLIB fields"); 5416 oid_list = SYSCTL_CHILDREN(node); 5417 5418 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 5419 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 5420 "driver version"); 5421 5422 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 5423 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 5424 "# of txqs to use, 0 => use default #"); 5425 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 5426 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 5427 "# of rxqs to use, 0 => use default #"); 5428 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 5429 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 5430 "permit #txq != #rxq"); 5431 5432 /* XXX change for per-queue sizes */ 5433 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 5434 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 5435 mp_ndesc_handler, "A", 5436 "list of # of tx descriptors to use, 0 = use default #"); 5437 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 5438 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 5439 mp_ndesc_handler, "A", 5440 "list of # of rx descriptors to use, 0 = use default #"); 5441 } 5442 5443 static void 5444 iflib_add_device_sysctl_post(if_ctx_t ctx) 5445 { 5446 if_shared_ctx_t sctx = ctx->ifc_sctx; 5447 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5448 device_t dev = iflib_get_dev(ctx); 5449 struct sysctl_oid_list *child; 5450 struct sysctl_ctx_list *ctx_list; 5451 iflib_fl_t fl; 5452 iflib_txq_t txq; 5453 iflib_rxq_t rxq; 5454 int i, j; 5455 char namebuf[NAME_BUFLEN]; 5456 char *qfmt; 5457 struct sysctl_oid *queue_node, *fl_node, *node; 5458 struct sysctl_oid_list *queue_list, *fl_list; 5459 ctx_list = device_get_sysctl_ctx(dev); 5460 5461 node = ctx->ifc_sysctl_node; 5462 child = SYSCTL_CHILDREN(node); 5463 5464 if (scctx->isc_ntxqsets > 100) 5465 qfmt = "txq%03d"; 5466 else if (scctx->isc_ntxqsets > 10) 5467 qfmt = "txq%02d"; 5468 else 5469 qfmt = "txq%d"; 5470 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 5471 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5472 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5473 CTLFLAG_RD, NULL, "Queue Name"); 5474 queue_list = SYSCTL_CHILDREN(queue_node); 5475 #if MEMORY_LOGGING 5476 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 5477 CTLFLAG_RD, 5478 &txq->ift_dequeued, "total mbufs freed"); 5479 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 5480 CTLFLAG_RD, 5481 &txq->ift_enqueued, "total mbufs enqueued"); 5482 #endif 5483 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 5484 CTLFLAG_RD, 5485 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 5486 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 5487 CTLFLAG_RD, 5488 &txq->ift_pullups, "# of times m_pullup was called"); 5489 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 5490 CTLFLAG_RD, 5491 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 5492 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 5493 CTLFLAG_RD, 5494 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 5495 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 5496 CTLFLAG_RD, 5497 &txq->ift_map_failed, "# of times dma map failed"); 5498 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 5499 CTLFLAG_RD, 5500 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 5501 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 5502 CTLFLAG_RD, 5503 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 5504 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 5505 CTLFLAG_RD, 5506 &txq->ift_pidx, 1, "Producer Index"); 5507 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 5508 CTLFLAG_RD, 5509 &txq->ift_cidx, 1, "Consumer Index"); 5510 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 5511 CTLFLAG_RD, 5512 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 5513 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 5514 CTLFLAG_RD, 5515 &txq->ift_in_use, 1, "descriptors in use"); 5516 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 5517 CTLFLAG_RD, 5518 &txq->ift_processed, "descriptors procesed for clean"); 5519 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 5520 CTLFLAG_RD, 5521 &txq->ift_cleaned, "total cleaned"); 5522 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 5523 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 5524 0, mp_ring_state_handler, "A", "soft ring state"); 5525 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 5526 CTLFLAG_RD, &txq->ift_br->enqueues, 5527 "# of enqueues to the mp_ring for this queue"); 5528 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 5529 CTLFLAG_RD, &txq->ift_br->drops, 5530 "# of drops in the mp_ring for this queue"); 5531 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 5532 CTLFLAG_RD, &txq->ift_br->starts, 5533 "# of normal consumer starts in the mp_ring for this queue"); 5534 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 5535 CTLFLAG_RD, &txq->ift_br->stalls, 5536 "# of consumer stalls in the mp_ring for this queue"); 5537 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 5538 CTLFLAG_RD, &txq->ift_br->restarts, 5539 "# of consumer restarts in the mp_ring for this queue"); 5540 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 5541 CTLFLAG_RD, &txq->ift_br->abdications, 5542 "# of consumer abdications in the mp_ring for this queue"); 5543 } 5544 5545 if (scctx->isc_nrxqsets > 100) 5546 qfmt = "rxq%03d"; 5547 else if (scctx->isc_nrxqsets > 10) 5548 qfmt = "rxq%02d"; 5549 else 5550 qfmt = "rxq%d"; 5551 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 5552 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5553 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5554 CTLFLAG_RD, NULL, "Queue Name"); 5555 queue_list = SYSCTL_CHILDREN(queue_node); 5556 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5557 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 5558 CTLFLAG_RD, 5559 &rxq->ifr_cq_pidx, 1, "Producer Index"); 5560 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 5561 CTLFLAG_RD, 5562 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 5563 } 5564 5565 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 5566 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 5567 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 5568 CTLFLAG_RD, NULL, "freelist Name"); 5569 fl_list = SYSCTL_CHILDREN(fl_node); 5570 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 5571 CTLFLAG_RD, 5572 &fl->ifl_pidx, 1, "Producer Index"); 5573 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 5574 CTLFLAG_RD, 5575 &fl->ifl_cidx, 1, "Consumer Index"); 5576 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 5577 CTLFLAG_RD, 5578 &fl->ifl_credits, 1, "credits available"); 5579 #if MEMORY_LOGGING 5580 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 5581 CTLFLAG_RD, 5582 &fl->ifl_m_enqueued, "mbufs allocated"); 5583 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 5584 CTLFLAG_RD, 5585 &fl->ifl_m_dequeued, "mbufs freed"); 5586 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 5587 CTLFLAG_RD, 5588 &fl->ifl_cl_enqueued, "clusters allocated"); 5589 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 5590 CTLFLAG_RD, 5591 &fl->ifl_cl_dequeued, "clusters freed"); 5592 #endif 5593 5594 } 5595 } 5596 5597 } 5598 5599 #ifndef __NO_STRICT_ALIGNMENT 5600 static struct mbuf * 5601 iflib_fixup_rx(struct mbuf *m) 5602 { 5603 struct mbuf *n; 5604 5605 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 5606 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 5607 m->m_data += ETHER_HDR_LEN; 5608 n = m; 5609 } else { 5610 MGETHDR(n, M_NOWAIT, MT_DATA); 5611 if (n == NULL) { 5612 m_freem(m); 5613 return (NULL); 5614 } 5615 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 5616 m->m_data += ETHER_HDR_LEN; 5617 m->m_len -= ETHER_HDR_LEN; 5618 n->m_len = ETHER_HDR_LEN; 5619 M_MOVE_PKTHDR(n, m); 5620 n->m_next = m; 5621 } 5622 return (n); 5623 } 5624 #endif 5625