1 /*- 2 * Copyright (c) 2014-2017, Matthew Macy <mmacy@nextbsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 35 #include <sys/param.h> 36 #include <sys/types.h> 37 #include <sys/bus.h> 38 #include <sys/eventhandler.h> 39 #include <sys/sockio.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sysctl.h> 50 #include <sys/syslog.h> 51 #include <sys/taskqueue.h> 52 #include <sys/limits.h> 53 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 63 #include <netinet/in.h> 64 #include <netinet/in_pcb.h> 65 #include <netinet/tcp_lro.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/if_ether.h> 68 #include <netinet/ip.h> 69 #include <netinet/ip6.h> 70 #include <netinet/tcp.h> 71 72 #include <machine/bus.h> 73 #include <machine/in_cksum.h> 74 75 #include <vm/vm.h> 76 #include <vm/pmap.h> 77 78 #include <dev/led/led.h> 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pci_private.h> 82 83 #include <net/iflib.h> 84 85 #include "ifdi_if.h" 86 87 #if defined(__i386__) || defined(__amd64__) 88 #include <sys/memdesc.h> 89 #include <machine/bus.h> 90 #include <machine/md_var.h> 91 #include <machine/specialreg.h> 92 #include <x86/include/busdma_impl.h> 93 #include <x86/iommu/busdma_dmar.h> 94 #endif 95 96 /* 97 * enable accounting of every mbuf as it comes in to and goes out of 98 * iflib's software descriptor references 99 */ 100 #define MEMORY_LOGGING 0 101 /* 102 * Enable mbuf vectors for compressing long mbuf chains 103 */ 104 105 /* 106 * NB: 107 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 108 * we prefetch needs to be determined by the time spent in m_free vis a vis 109 * the cost of a prefetch. This will of course vary based on the workload: 110 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 111 * is quite expensive, thus suggesting very little prefetch. 112 * - small packet forwarding which is just returning a single mbuf to 113 * UMA will typically be very fast vis a vis the cost of a memory 114 * access. 115 */ 116 117 118 /* 119 * File organization: 120 * - private structures 121 * - iflib private utility functions 122 * - ifnet functions 123 * - vlan registry and other exported functions 124 * - iflib public core functions 125 * 126 * 127 */ 128 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 129 130 struct iflib_txq; 131 typedef struct iflib_txq *iflib_txq_t; 132 struct iflib_rxq; 133 typedef struct iflib_rxq *iflib_rxq_t; 134 struct iflib_fl; 135 typedef struct iflib_fl *iflib_fl_t; 136 137 struct iflib_ctx; 138 139 typedef struct iflib_filter_info { 140 driver_filter_t *ifi_filter; 141 void *ifi_filter_arg; 142 struct grouptask *ifi_task; 143 void *ifi_ctx; 144 } *iflib_filter_info_t; 145 146 struct iflib_ctx { 147 KOBJ_FIELDS; 148 /* 149 * Pointer to hardware driver's softc 150 */ 151 void *ifc_softc; 152 device_t ifc_dev; 153 if_t ifc_ifp; 154 155 cpuset_t ifc_cpus; 156 if_shared_ctx_t ifc_sctx; 157 struct if_softc_ctx ifc_softc_ctx; 158 159 struct mtx ifc_mtx; 160 161 uint16_t ifc_nhwtxqs; 162 uint16_t ifc_nhwrxqs; 163 164 iflib_txq_t ifc_txqs; 165 iflib_rxq_t ifc_rxqs; 166 uint32_t ifc_if_flags; 167 uint32_t ifc_flags; 168 uint32_t ifc_max_fl_buf_size; 169 int ifc_in_detach; 170 171 int ifc_link_state; 172 int ifc_link_irq; 173 int ifc_pause_frames; 174 int ifc_watchdog_events; 175 struct cdev *ifc_led_dev; 176 struct resource *ifc_msix_mem; 177 178 struct if_irq ifc_legacy_irq; 179 struct grouptask ifc_admin_task; 180 struct grouptask ifc_vflr_task; 181 struct iflib_filter_info ifc_filter_info; 182 struct ifmedia ifc_media; 183 184 struct sysctl_oid *ifc_sysctl_node; 185 uint16_t ifc_sysctl_ntxqs; 186 uint16_t ifc_sysctl_nrxqs; 187 uint16_t ifc_sysctl_qs_eq_override; 188 189 qidx_t ifc_sysctl_ntxds[8]; 190 qidx_t ifc_sysctl_nrxds[8]; 191 struct if_txrx ifc_txrx; 192 #define isc_txd_encap ifc_txrx.ift_txd_encap 193 #define isc_txd_flush ifc_txrx.ift_txd_flush 194 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 195 #define isc_rxd_available ifc_txrx.ift_rxd_available 196 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 197 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 198 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 199 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 200 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 201 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 202 eventhandler_tag ifc_vlan_attach_event; 203 eventhandler_tag ifc_vlan_detach_event; 204 uint8_t ifc_mac[ETHER_ADDR_LEN]; 205 char ifc_mtx_name[16]; 206 }; 207 208 209 void * 210 iflib_get_softc(if_ctx_t ctx) 211 { 212 213 return (ctx->ifc_softc); 214 } 215 216 device_t 217 iflib_get_dev(if_ctx_t ctx) 218 { 219 220 return (ctx->ifc_dev); 221 } 222 223 if_t 224 iflib_get_ifp(if_ctx_t ctx) 225 { 226 227 return (ctx->ifc_ifp); 228 } 229 230 struct ifmedia * 231 iflib_get_media(if_ctx_t ctx) 232 { 233 234 return (&ctx->ifc_media); 235 } 236 237 void 238 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 239 { 240 241 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 242 } 243 244 if_softc_ctx_t 245 iflib_get_softc_ctx(if_ctx_t ctx) 246 { 247 248 return (&ctx->ifc_softc_ctx); 249 } 250 251 if_shared_ctx_t 252 iflib_get_sctx(if_ctx_t ctx) 253 { 254 255 return (ctx->ifc_sctx); 256 } 257 258 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 259 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 260 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 261 262 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 263 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 264 265 #define RX_SW_DESC_MAP_CREATED (1 << 0) 266 #define TX_SW_DESC_MAP_CREATED (1 << 1) 267 #define RX_SW_DESC_INUSE (1 << 3) 268 #define TX_SW_DESC_MAPPED (1 << 4) 269 270 typedef struct iflib_sw_rx_desc_array { 271 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 272 struct mbuf **ifsd_m; /* pkthdr mbufs */ 273 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 274 uint8_t *ifsd_flags; 275 } iflib_rxsd_array_t; 276 277 typedef struct iflib_sw_tx_desc_array { 278 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 279 struct mbuf **ifsd_m; /* pkthdr mbufs */ 280 uint8_t *ifsd_flags; 281 } if_txsd_vec_t; 282 283 284 /* magic number that should be high enough for any hardware */ 285 #define IFLIB_MAX_TX_SEGS 128 286 #define IFLIB_MAX_RX_SEGS 32 287 #define IFLIB_RX_COPY_THRESH 128 288 #define IFLIB_MAX_RX_REFRESH 32 289 /* The minimum descriptors per second before we start coalescing */ 290 #define IFLIB_MIN_DESC_SEC 16384 291 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 292 #define IFLIB_QUEUE_IDLE 0 293 #define IFLIB_QUEUE_HUNG 1 294 #define IFLIB_QUEUE_WORKING 2 295 /* maximum number of txqs that can share an rx interrupt */ 296 #define IFLIB_MAX_TX_SHARED_INTR 4 297 298 /* this should really scale with ring size - this is a fairly arbitrary value */ 299 #define TX_BATCH_SIZE 32 300 301 #define IFLIB_RESTART_BUDGET 8 302 303 #define IFC_LEGACY 0x001 304 #define IFC_QFLUSH 0x002 305 #define IFC_MULTISEG 0x004 306 #define IFC_DMAR 0x008 307 #define IFC_SC_ALLOCATED 0x010 308 #define IFC_INIT_DONE 0x020 309 #define IFC_PREFETCH 0x040 310 #define IFC_DO_RESET 0x080 311 #define IFC_CHECK_HUNG 0x100 312 313 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 314 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 315 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 316 struct iflib_txq { 317 qidx_t ift_in_use; 318 qidx_t ift_cidx; 319 qidx_t ift_cidx_processed; 320 qidx_t ift_pidx; 321 uint8_t ift_gen; 322 uint8_t ift_br_offset; 323 uint16_t ift_npending; 324 uint16_t ift_db_pending; 325 uint16_t ift_rs_pending; 326 /* implicit pad */ 327 uint8_t ift_txd_size[8]; 328 uint64_t ift_processed; 329 uint64_t ift_cleaned; 330 uint64_t ift_cleaned_prev; 331 #if MEMORY_LOGGING 332 uint64_t ift_enqueued; 333 uint64_t ift_dequeued; 334 #endif 335 uint64_t ift_no_tx_dma_setup; 336 uint64_t ift_no_desc_avail; 337 uint64_t ift_mbuf_defrag_failed; 338 uint64_t ift_mbuf_defrag; 339 uint64_t ift_map_failed; 340 uint64_t ift_txd_encap_efbig; 341 uint64_t ift_pullups; 342 343 struct mtx ift_mtx; 344 struct mtx ift_db_mtx; 345 346 /* constant values */ 347 if_ctx_t ift_ctx; 348 struct ifmp_ring *ift_br; 349 struct grouptask ift_task; 350 qidx_t ift_size; 351 uint16_t ift_id; 352 struct callout ift_timer; 353 354 if_txsd_vec_t ift_sds; 355 uint8_t ift_qstatus; 356 uint8_t ift_closed; 357 uint8_t ift_update_freq; 358 struct iflib_filter_info ift_filter_info; 359 bus_dma_tag_t ift_desc_tag; 360 bus_dma_tag_t ift_tso_desc_tag; 361 iflib_dma_info_t ift_ifdi; 362 #define MTX_NAME_LEN 16 363 char ift_mtx_name[MTX_NAME_LEN]; 364 char ift_db_mtx_name[MTX_NAME_LEN]; 365 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 366 #ifdef IFLIB_DIAGNOSTICS 367 uint64_t ift_cpu_exec_count[256]; 368 #endif 369 } __aligned(CACHE_LINE_SIZE); 370 371 struct iflib_fl { 372 qidx_t ifl_cidx; 373 qidx_t ifl_pidx; 374 qidx_t ifl_credits; 375 uint8_t ifl_gen; 376 uint8_t ifl_rxd_size; 377 #if MEMORY_LOGGING 378 uint64_t ifl_m_enqueued; 379 uint64_t ifl_m_dequeued; 380 uint64_t ifl_cl_enqueued; 381 uint64_t ifl_cl_dequeued; 382 #endif 383 /* implicit pad */ 384 385 /* constant */ 386 qidx_t ifl_size; 387 uint16_t ifl_buf_size; 388 uint16_t ifl_cltype; 389 uma_zone_t ifl_zone; 390 iflib_rxsd_array_t ifl_sds; 391 iflib_rxq_t ifl_rxq; 392 uint8_t ifl_id; 393 bus_dma_tag_t ifl_desc_tag; 394 iflib_dma_info_t ifl_ifdi; 395 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 396 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 397 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 398 } __aligned(CACHE_LINE_SIZE); 399 400 static inline qidx_t 401 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 402 { 403 qidx_t used; 404 405 if (pidx > cidx) 406 used = pidx - cidx; 407 else if (pidx < cidx) 408 used = size - cidx + pidx; 409 else if (gen == 0 && pidx == cidx) 410 used = 0; 411 else if (gen == 1 && pidx == cidx) 412 used = size; 413 else 414 panic("bad state"); 415 416 return (used); 417 } 418 419 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 420 421 #define IDXDIFF(head, tail, wrap) \ 422 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 423 424 struct iflib_rxq { 425 /* If there is a separate completion queue - 426 * these are the cq cidx and pidx. Otherwise 427 * these are unused. 428 */ 429 qidx_t ifr_size; 430 qidx_t ifr_cq_cidx; 431 qidx_t ifr_cq_pidx; 432 uint8_t ifr_cq_gen; 433 uint8_t ifr_fl_offset; 434 435 if_ctx_t ifr_ctx; 436 iflib_fl_t ifr_fl; 437 uint64_t ifr_rx_irq; 438 uint16_t ifr_id; 439 uint8_t ifr_lro_enabled; 440 uint8_t ifr_nfl; 441 uint8_t ifr_ntxqirq; 442 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 443 struct lro_ctrl ifr_lc; 444 struct grouptask ifr_task; 445 struct iflib_filter_info ifr_filter_info; 446 iflib_dma_info_t ifr_ifdi; 447 448 /* dynamically allocate if any drivers need a value substantially larger than this */ 449 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 450 #ifdef IFLIB_DIAGNOSTICS 451 uint64_t ifr_cpu_exec_count[256]; 452 #endif 453 } __aligned(CACHE_LINE_SIZE); 454 455 typedef struct if_rxsd { 456 caddr_t *ifsd_cl; 457 struct mbuf **ifsd_m; 458 iflib_fl_t ifsd_fl; 459 qidx_t ifsd_cidx; 460 } *if_rxsd_t; 461 462 /* multiple of word size */ 463 #ifdef __LP64__ 464 #define PKT_INFO_SIZE 6 465 #define RXD_INFO_SIZE 5 466 #define PKT_TYPE uint64_t 467 #else 468 #define PKT_INFO_SIZE 11 469 #define RXD_INFO_SIZE 8 470 #define PKT_TYPE uint32_t 471 #endif 472 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 473 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 474 475 typedef struct if_pkt_info_pad { 476 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 477 } *if_pkt_info_pad_t; 478 typedef struct if_rxd_info_pad { 479 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 480 } *if_rxd_info_pad_t; 481 482 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 483 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 484 485 486 static inline void 487 pkt_info_zero(if_pkt_info_t pi) 488 { 489 if_pkt_info_pad_t pi_pad; 490 491 pi_pad = (if_pkt_info_pad_t)pi; 492 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 493 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 494 #ifndef __LP64__ 495 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 496 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 497 #endif 498 } 499 500 static inline void 501 rxd_info_zero(if_rxd_info_t ri) 502 { 503 if_rxd_info_pad_t ri_pad; 504 int i; 505 506 ri_pad = (if_rxd_info_pad_t)ri; 507 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 508 ri_pad->rxd_val[i] = 0; 509 ri_pad->rxd_val[i+1] = 0; 510 ri_pad->rxd_val[i+2] = 0; 511 ri_pad->rxd_val[i+3] = 0; 512 } 513 #ifdef __LP64__ 514 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 515 #endif 516 } 517 518 /* 519 * Only allow a single packet to take up most 1/nth of the tx ring 520 */ 521 #define MAX_SINGLE_PACKET_FRACTION 12 522 #define IF_BAD_DMA (bus_addr_t)-1 523 524 static int enable_msix = 1; 525 526 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 527 528 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF) 529 530 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx) 531 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx) 532 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx) 533 534 535 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 536 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 537 538 539 /* Our boot-time initialization hook */ 540 static int iflib_module_event_handler(module_t, int, void *); 541 542 static moduledata_t iflib_moduledata = { 543 "iflib", 544 iflib_module_event_handler, 545 NULL 546 }; 547 548 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 549 MODULE_VERSION(iflib, 1); 550 551 MODULE_DEPEND(iflib, pci, 1, 1, 1); 552 MODULE_DEPEND(iflib, ether, 1, 1, 1); 553 554 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 555 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 556 557 #ifndef IFLIB_DEBUG_COUNTERS 558 #ifdef INVARIANTS 559 #define IFLIB_DEBUG_COUNTERS 1 560 #else 561 #define IFLIB_DEBUG_COUNTERS 0 562 #endif /* !INVARIANTS */ 563 #endif 564 565 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 566 "iflib driver parameters"); 567 568 /* 569 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 570 */ 571 static int iflib_min_tx_latency = 0; 572 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 573 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 574 static int iflib_no_tx_batch = 0; 575 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 576 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 577 578 579 #if IFLIB_DEBUG_COUNTERS 580 581 static int iflib_tx_seen; 582 static int iflib_tx_sent; 583 static int iflib_tx_encap; 584 static int iflib_rx_allocs; 585 static int iflib_fl_refills; 586 static int iflib_fl_refills_large; 587 static int iflib_tx_frees; 588 589 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 590 &iflib_tx_seen, 0, "# tx mbufs seen"); 591 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 592 &iflib_tx_sent, 0, "# tx mbufs sent"); 593 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 594 &iflib_tx_encap, 0, "# tx mbufs encapped"); 595 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 596 &iflib_tx_frees, 0, "# tx frees"); 597 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 598 &iflib_rx_allocs, 0, "# rx allocations"); 599 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 600 &iflib_fl_refills, 0, "# refills"); 601 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 602 &iflib_fl_refills_large, 0, "# large refills"); 603 604 605 static int iflib_txq_drain_flushing; 606 static int iflib_txq_drain_oactive; 607 static int iflib_txq_drain_notready; 608 static int iflib_txq_drain_encapfail; 609 610 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 611 &iflib_txq_drain_flushing, 0, "# drain flushes"); 612 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 613 &iflib_txq_drain_oactive, 0, "# drain oactives"); 614 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 615 &iflib_txq_drain_notready, 0, "# drain notready"); 616 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 617 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 618 619 620 static int iflib_encap_load_mbuf_fail; 621 static int iflib_encap_txq_avail_fail; 622 static int iflib_encap_txd_encap_fail; 623 624 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 625 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 626 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 627 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 628 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 629 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 630 631 static int iflib_task_fn_rxs; 632 static int iflib_rx_intr_enables; 633 static int iflib_fast_intrs; 634 static int iflib_intr_link; 635 static int iflib_intr_msix; 636 static int iflib_rx_unavail; 637 static int iflib_rx_ctx_inactive; 638 static int iflib_rx_zero_len; 639 static int iflib_rx_if_input; 640 static int iflib_rx_mbuf_null; 641 static int iflib_rxd_flush; 642 643 static int iflib_verbose_debug; 644 645 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 646 &iflib_intr_link, 0, "# intr link calls"); 647 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 648 &iflib_intr_msix, 0, "# intr msix calls"); 649 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 650 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 651 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 652 &iflib_rx_intr_enables, 0, "# rx intr enables"); 653 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 654 &iflib_fast_intrs, 0, "# fast_intr calls"); 655 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 656 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 657 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 658 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 660 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 662 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 664 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 666 &iflib_rxd_flush, 0, "# times rxd_flush called"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 668 &iflib_verbose_debug, 0, "enable verbose debugging"); 669 670 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 671 static void 672 iflib_debug_reset(void) 673 { 674 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 675 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 676 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 677 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 678 iflib_encap_load_mbuf_fail = iflib_encap_txq_avail_fail = 679 iflib_encap_txd_encap_fail = iflib_task_fn_rxs = iflib_rx_intr_enables = 680 iflib_fast_intrs = iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 681 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 682 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 683 } 684 685 #else 686 #define DBG_COUNTER_INC(name) 687 static void iflib_debug_reset(void) {} 688 #endif 689 690 691 692 #define IFLIB_DEBUG 0 693 694 static void iflib_tx_structures_free(if_ctx_t ctx); 695 static void iflib_rx_structures_free(if_ctx_t ctx); 696 static int iflib_queues_alloc(if_ctx_t ctx); 697 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 698 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 699 static int iflib_qset_structures_setup(if_ctx_t ctx); 700 static int iflib_msix_init(if_ctx_t ctx); 701 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str); 702 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 703 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 704 static int iflib_register(if_ctx_t); 705 static void iflib_init_locked(if_ctx_t ctx); 706 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 707 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 708 static void iflib_ifmp_purge(iflib_txq_t txq); 709 static void _iflib_pre_assert(if_softc_ctx_t scctx); 710 static void iflib_stop(if_ctx_t ctx); 711 static void iflib_if_init_locked(if_ctx_t ctx); 712 #ifndef __NO_STRICT_ALIGNMENT 713 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 714 #endif 715 716 #ifdef DEV_NETMAP 717 #include <sys/selinfo.h> 718 #include <net/netmap.h> 719 #include <dev/netmap/netmap_kern.h> 720 721 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 722 723 /* 724 * device-specific sysctl variables: 725 * 726 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 727 * During regular operations the CRC is stripped, but on some 728 * hardware reception of frames not multiple of 64 is slower, 729 * so using crcstrip=0 helps in benchmarks. 730 * 731 * iflib_rx_miss, iflib_rx_miss_bufs: 732 * count packets that might be missed due to lost interrupts. 733 */ 734 SYSCTL_DECL(_dev_netmap); 735 /* 736 * The xl driver by default strips CRCs and we do not override it. 737 */ 738 739 int iflib_crcstrip = 1; 740 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 741 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 742 743 int iflib_rx_miss, iflib_rx_miss_bufs; 744 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 745 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 746 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 747 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 748 749 /* 750 * Register/unregister. We are already under netmap lock. 751 * Only called on the first register or the last unregister. 752 */ 753 static int 754 iflib_netmap_register(struct netmap_adapter *na, int onoff) 755 { 756 struct ifnet *ifp = na->ifp; 757 if_ctx_t ctx = ifp->if_softc; 758 int status; 759 760 CTX_LOCK(ctx); 761 IFDI_INTR_DISABLE(ctx); 762 763 /* Tell the stack that the interface is no longer active */ 764 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 765 766 if (!CTX_IS_VF(ctx)) 767 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 768 769 /* enable or disable flags and callbacks in na and ifp */ 770 if (onoff) { 771 nm_set_native_flags(na); 772 } else { 773 nm_clear_native_flags(na); 774 } 775 iflib_stop(ctx); 776 iflib_init_locked(ctx); 777 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 778 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 779 if (status) 780 nm_clear_native_flags(na); 781 CTX_UNLOCK(ctx); 782 return (status); 783 } 784 785 /* 786 * Reconcile kernel and user view of the transmit ring. 787 * 788 * All information is in the kring. 789 * Userspace wants to send packets up to the one before kring->rhead, 790 * kernel knows kring->nr_hwcur is the first unsent packet. 791 * 792 * Here we push packets out (as many as possible), and possibly 793 * reclaim buffers from previously completed transmission. 794 * 795 * The caller (netmap) guarantees that there is only one instance 796 * running at any time. Any interference with other driver 797 * methods should be handled by the individual drivers. 798 */ 799 static int 800 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 801 { 802 struct netmap_adapter *na = kring->na; 803 struct ifnet *ifp = na->ifp; 804 struct netmap_ring *ring = kring->ring; 805 u_int nm_i; /* index into the netmap ring */ 806 u_int nic_i; /* index into the NIC ring */ 807 u_int n; 808 u_int const lim = kring->nkr_num_slots - 1; 809 u_int const head = kring->rhead; 810 struct if_pkt_info pi; 811 812 /* 813 * interrupts on every tx packet are expensive so request 814 * them every half ring, or where NS_REPORT is set 815 */ 816 u_int report_frequency = kring->nkr_num_slots >> 1; 817 /* device-specific */ 818 if_ctx_t ctx = ifp->if_softc; 819 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 820 821 if (txq->ift_sds.ifsd_map) 822 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 823 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 824 825 826 /* 827 * First part: process new packets to send. 828 * nm_i is the current index in the netmap ring, 829 * nic_i is the corresponding index in the NIC ring. 830 * 831 * If we have packets to send (nm_i != head) 832 * iterate over the netmap ring, fetch length and update 833 * the corresponding slot in the NIC ring. Some drivers also 834 * need to update the buffer's physical address in the NIC slot 835 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 836 * 837 * The netmap_reload_map() calls is especially expensive, 838 * even when (as in this case) the tag is 0, so do only 839 * when the buffer has actually changed. 840 * 841 * If possible do not set the report/intr bit on all slots, 842 * but only a few times per ring or when NS_REPORT is set. 843 * 844 * Finally, on 10G and faster drivers, it might be useful 845 * to prefetch the next slot and txr entry. 846 */ 847 848 nm_i = kring->nr_hwcur; 849 pkt_info_zero(&pi); 850 pi.ipi_segs = txq->ift_segs; 851 pi.ipi_qsidx = kring->ring_id; 852 if (nm_i != head) { /* we have new packets to send */ 853 nic_i = netmap_idx_k2n(kring, nm_i); 854 855 __builtin_prefetch(&ring->slot[nm_i]); 856 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 857 if (txq->ift_sds.ifsd_map) 858 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 859 860 for (n = 0; nm_i != head; n++) { 861 struct netmap_slot *slot = &ring->slot[nm_i]; 862 u_int len = slot->len; 863 uint64_t paddr; 864 void *addr = PNMB(na, slot, &paddr); 865 int flags = (slot->flags & NS_REPORT || 866 nic_i == 0 || nic_i == report_frequency) ? 867 IPI_TX_INTR : 0; 868 869 /* device-specific */ 870 pi.ipi_len = len; 871 pi.ipi_segs[0].ds_addr = paddr; 872 pi.ipi_segs[0].ds_len = len; 873 pi.ipi_nsegs = 1; 874 pi.ipi_ndescs = 0; 875 pi.ipi_pidx = nic_i; 876 pi.ipi_flags = flags; 877 878 /* Fill the slot in the NIC ring. */ 879 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 880 881 /* prefetch for next round */ 882 __builtin_prefetch(&ring->slot[nm_i + 1]); 883 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 884 if (txq->ift_sds.ifsd_map) { 885 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 886 887 NM_CHECK_ADDR_LEN(na, addr, len); 888 889 if (slot->flags & NS_BUF_CHANGED) { 890 /* buffer has changed, reload map */ 891 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 892 } 893 /* make sure changes to the buffer are synced */ 894 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 895 BUS_DMASYNC_PREWRITE); 896 } 897 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 898 nm_i = nm_next(nm_i, lim); 899 nic_i = nm_next(nic_i, lim); 900 } 901 kring->nr_hwcur = head; 902 903 /* synchronize the NIC ring */ 904 if (txq->ift_sds.ifsd_map) 905 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 906 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 907 908 /* (re)start the tx unit up to slot nic_i (excluded) */ 909 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 910 } 911 912 /* 913 * Second part: reclaim buffers for completed transmissions. 914 */ 915 if (iflib_tx_credits_update(ctx, txq)) { 916 /* some tx completed, increment avail */ 917 nic_i = txq->ift_cidx_processed; 918 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 919 } 920 return (0); 921 } 922 923 /* 924 * Reconcile kernel and user view of the receive ring. 925 * Same as for the txsync, this routine must be efficient. 926 * The caller guarantees a single invocations, but races against 927 * the rest of the driver should be handled here. 928 * 929 * On call, kring->rhead is the first packet that userspace wants 930 * to keep, and kring->rcur is the wakeup point. 931 * The kernel has previously reported packets up to kring->rtail. 932 * 933 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 934 * of whether or not we received an interrupt. 935 */ 936 static int 937 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 938 { 939 struct netmap_adapter *na = kring->na; 940 struct netmap_ring *ring = kring->ring; 941 uint32_t nm_i; /* index into the netmap ring */ 942 uint32_t nic_i, nic_i_start; /* index into the NIC ring */ 943 u_int i, n; 944 u_int const lim = kring->nkr_num_slots - 1; 945 u_int const head = kring->rhead; 946 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 947 struct if_rxd_info ri; 948 struct if_rxd_update iru; 949 950 struct ifnet *ifp = na->ifp; 951 if_ctx_t ctx = ifp->if_softc; 952 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 953 iflib_fl_t fl = rxq->ifr_fl; 954 if (head > lim) 955 return netmap_ring_reinit(kring); 956 957 /* XXX check sync modes */ 958 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 959 if (fl->ifl_sds.ifsd_map == NULL) 960 continue; 961 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 962 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 963 } 964 /* 965 * First part: import newly received packets. 966 * 967 * nm_i is the index of the next free slot in the netmap ring, 968 * nic_i is the index of the next received packet in the NIC ring, 969 * and they may differ in case if_init() has been called while 970 * in netmap mode. For the receive ring we have 971 * 972 * nic_i = rxr->next_check; 973 * nm_i = kring->nr_hwtail (previous) 974 * and 975 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 976 * 977 * rxr->next_check is set to 0 on a ring reinit 978 */ 979 if (netmap_no_pendintr || force_update) { 980 int crclen = iflib_crcstrip ? 0 : 4; 981 int error, avail; 982 uint16_t slot_flags = kring->nkr_slot_flags; 983 984 for (fl = rxq->ifr_fl, i = 0; i < rxq->ifr_nfl; i++, fl++) { 985 nic_i = fl->ifl_cidx; 986 nm_i = netmap_idx_n2k(kring, nic_i); 987 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 988 for (n = 0; avail > 0; n++, avail--) { 989 rxd_info_zero(&ri); 990 ri.iri_frags = rxq->ifr_frags; 991 ri.iri_qsidx = kring->ring_id; 992 ri.iri_ifp = ctx->ifc_ifp; 993 ri.iri_cidx = nic_i; 994 995 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 996 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 997 ring->slot[nm_i].flags = slot_flags; 998 if (fl->ifl_sds.ifsd_map) 999 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1000 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1001 nm_i = nm_next(nm_i, lim); 1002 nic_i = nm_next(nic_i, lim); 1003 } 1004 if (n) { /* update the state variables */ 1005 if (netmap_no_pendintr && !force_update) { 1006 /* diagnostics */ 1007 iflib_rx_miss ++; 1008 iflib_rx_miss_bufs += n; 1009 } 1010 fl->ifl_cidx = nic_i; 1011 kring->nr_hwtail = nm_i; 1012 } 1013 kring->nr_kflags &= ~NKR_PENDINTR; 1014 } 1015 } 1016 /* 1017 * Second part: skip past packets that userspace has released. 1018 * (kring->nr_hwcur to head excluded), 1019 * and make the buffers available for reception. 1020 * As usual nm_i is the index in the netmap ring, 1021 * nic_i is the index in the NIC ring, and 1022 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1023 */ 1024 /* XXX not sure how this will work with multiple free lists */ 1025 nm_i = kring->nr_hwcur; 1026 if (nm_i == head) 1027 return (0); 1028 1029 iru.iru_paddrs = fl->ifl_bus_addrs; 1030 iru.iru_vaddrs = &fl->ifl_vm_addrs[0]; 1031 iru.iru_idxs = fl->ifl_rxd_idxs; 1032 iru.iru_qsidx = rxq->ifr_id; 1033 iru.iru_buf_size = fl->ifl_buf_size; 1034 iru.iru_flidx = fl->ifl_id; 1035 nic_i_start = nic_i = netmap_idx_k2n(kring, nm_i); 1036 for (i = 0; nm_i != head; i++) { 1037 struct netmap_slot *slot = &ring->slot[nm_i]; 1038 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]); 1039 1040 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 1041 goto ring_reset; 1042 1043 fl->ifl_vm_addrs[i] = addr; 1044 if (fl->ifl_sds.ifsd_map && (slot->flags & NS_BUF_CHANGED)) { 1045 /* buffer has changed, reload map */ 1046 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i], addr); 1047 } 1048 slot->flags &= ~NS_BUF_CHANGED; 1049 1050 nm_i = nm_next(nm_i, lim); 1051 fl->ifl_rxd_idxs[i] = nic_i = nm_next(nic_i, lim); 1052 if (nm_i != head && i < IFLIB_MAX_RX_REFRESH) 1053 continue; 1054 1055 iru.iru_pidx = nic_i_start; 1056 iru.iru_count = i; 1057 i = 0; 1058 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1059 if (fl->ifl_sds.ifsd_map == NULL) { 1060 nic_i_start = nic_i; 1061 continue; 1062 } 1063 nic_i = nic_i_start; 1064 for (n = 0; n < iru.iru_count; n++) { 1065 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i], 1066 BUS_DMASYNC_PREREAD); 1067 nic_i = nm_next(nic_i, lim); 1068 } 1069 nic_i_start = nic_i; 1070 } 1071 kring->nr_hwcur = head; 1072 1073 if (fl->ifl_sds.ifsd_map) 1074 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1075 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1076 /* 1077 * IMPORTANT: we must leave one free slot in the ring, 1078 * so move nic_i back by one unit 1079 */ 1080 nic_i = nm_prev(nic_i, lim); 1081 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 1082 return 0; 1083 1084 ring_reset: 1085 return netmap_ring_reinit(kring); 1086 } 1087 1088 static void 1089 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1090 { 1091 struct ifnet *ifp = na->ifp; 1092 if_ctx_t ctx = ifp->if_softc; 1093 1094 CTX_LOCK(ctx); 1095 if (onoff) { 1096 IFDI_INTR_ENABLE(ctx); 1097 } else { 1098 IFDI_INTR_DISABLE(ctx); 1099 } 1100 CTX_UNLOCK(ctx); 1101 } 1102 1103 1104 static int 1105 iflib_netmap_attach(if_ctx_t ctx) 1106 { 1107 struct netmap_adapter na; 1108 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1109 1110 bzero(&na, sizeof(na)); 1111 1112 na.ifp = ctx->ifc_ifp; 1113 na.na_flags = NAF_BDG_MAYSLEEP; 1114 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1115 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1116 1117 na.num_tx_desc = scctx->isc_ntxd[0]; 1118 na.num_rx_desc = scctx->isc_nrxd[0]; 1119 na.nm_txsync = iflib_netmap_txsync; 1120 na.nm_rxsync = iflib_netmap_rxsync; 1121 na.nm_register = iflib_netmap_register; 1122 na.nm_intr = iflib_netmap_intr; 1123 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1124 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1125 return (netmap_attach(&na)); 1126 } 1127 1128 static void 1129 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1130 { 1131 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1132 struct netmap_slot *slot; 1133 1134 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1135 if (slot == NULL) 1136 return; 1137 if (txq->ift_sds.ifsd_map == NULL) 1138 return; 1139 1140 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1141 1142 /* 1143 * In netmap mode, set the map for the packet buffer. 1144 * NOTE: Some drivers (not this one) also need to set 1145 * the physical buffer address in the NIC ring. 1146 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1147 * netmap slot index, si 1148 */ 1149 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i); 1150 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1151 } 1152 } 1153 static void 1154 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1155 { 1156 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1157 struct netmap_slot *slot; 1158 struct if_rxd_update iru; 1159 iflib_fl_t fl; 1160 bus_dmamap_t *map; 1161 int nrxd; 1162 uint32_t i, j, pidx_start; 1163 1164 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1165 if (slot == NULL) 1166 return; 1167 fl = &rxq->ifr_fl[0]; 1168 map = fl->ifl_sds.ifsd_map; 1169 nrxd = ctx->ifc_softc_ctx.isc_nrxd[0]; 1170 iru.iru_paddrs = fl->ifl_bus_addrs; 1171 iru.iru_vaddrs = &fl->ifl_vm_addrs[0]; 1172 iru.iru_idxs = fl->ifl_rxd_idxs; 1173 iru.iru_qsidx = rxq->ifr_id; 1174 iru.iru_buf_size = rxq->ifr_fl[0].ifl_buf_size; 1175 iru.iru_flidx = 0; 1176 1177 for (pidx_start = i = j = 0; i < nrxd; i++, j++) { 1178 int sj = netmap_idx_n2k(&na->rx_rings[rxq->ifr_id], i); 1179 void *addr; 1180 1181 fl->ifl_rxd_idxs[j] = i; 1182 addr = fl->ifl_vm_addrs[j] = PNMB(na, slot + sj, &fl->ifl_bus_addrs[j]); 1183 if (map) { 1184 netmap_load_map(na, rxq->ifr_fl[0].ifl_ifdi->idi_tag, *map, addr); 1185 map++; 1186 } 1187 1188 if (j < IFLIB_MAX_RX_REFRESH && i < nrxd - 1) 1189 continue; 1190 1191 iru.iru_pidx = pidx_start; 1192 pidx_start = i; 1193 iru.iru_count = j; 1194 j = 0; 1195 MPASS(pidx_start + j <= nrxd); 1196 /* Update descriptors and the cached value */ 1197 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1198 } 1199 /* preserve queue */ 1200 if (ctx->ifc_ifp->if_capenable & IFCAP_NETMAP) { 1201 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id]; 1202 int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring); 1203 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, t); 1204 } else 1205 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, nrxd-1); 1206 } 1207 1208 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1209 1210 #else 1211 #define iflib_netmap_txq_init(ctx, txq) 1212 #define iflib_netmap_rxq_init(ctx, rxq) 1213 #define iflib_netmap_detach(ifp) 1214 1215 #define iflib_netmap_attach(ctx) (0) 1216 #define netmap_rx_irq(ifp, qid, budget) (0) 1217 #define netmap_tx_irq(ifp, qid) do {} while (0) 1218 1219 #endif 1220 1221 #if defined(__i386__) || defined(__amd64__) 1222 static __inline void 1223 prefetch(void *x) 1224 { 1225 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1226 } 1227 #else 1228 #define prefetch(x) 1229 #endif 1230 1231 static void 1232 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1233 { 1234 if (err) 1235 return; 1236 *(bus_addr_t *) arg = segs[0].ds_addr; 1237 } 1238 1239 int 1240 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1241 { 1242 int err; 1243 if_shared_ctx_t sctx = ctx->ifc_sctx; 1244 device_t dev = ctx->ifc_dev; 1245 1246 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1247 1248 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1249 sctx->isc_q_align, 0, /* alignment, bounds */ 1250 BUS_SPACE_MAXADDR, /* lowaddr */ 1251 BUS_SPACE_MAXADDR, /* highaddr */ 1252 NULL, NULL, /* filter, filterarg */ 1253 size, /* maxsize */ 1254 1, /* nsegments */ 1255 size, /* maxsegsize */ 1256 BUS_DMA_ALLOCNOW, /* flags */ 1257 NULL, /* lockfunc */ 1258 NULL, /* lockarg */ 1259 &dma->idi_tag); 1260 if (err) { 1261 device_printf(dev, 1262 "%s: bus_dma_tag_create failed: %d\n", 1263 __func__, err); 1264 goto fail_0; 1265 } 1266 1267 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1268 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1269 if (err) { 1270 device_printf(dev, 1271 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1272 __func__, (uintmax_t)size, err); 1273 goto fail_1; 1274 } 1275 1276 dma->idi_paddr = IF_BAD_DMA; 1277 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1278 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1279 if (err || dma->idi_paddr == IF_BAD_DMA) { 1280 device_printf(dev, 1281 "%s: bus_dmamap_load failed: %d\n", 1282 __func__, err); 1283 goto fail_2; 1284 } 1285 1286 dma->idi_size = size; 1287 return (0); 1288 1289 fail_2: 1290 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1291 fail_1: 1292 bus_dma_tag_destroy(dma->idi_tag); 1293 fail_0: 1294 dma->idi_tag = NULL; 1295 1296 return (err); 1297 } 1298 1299 int 1300 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1301 { 1302 int i, err; 1303 iflib_dma_info_t *dmaiter; 1304 1305 dmaiter = dmalist; 1306 for (i = 0; i < count; i++, dmaiter++) { 1307 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1308 break; 1309 } 1310 if (err) 1311 iflib_dma_free_multi(dmalist, i); 1312 return (err); 1313 } 1314 1315 void 1316 iflib_dma_free(iflib_dma_info_t dma) 1317 { 1318 if (dma->idi_tag == NULL) 1319 return; 1320 if (dma->idi_paddr != IF_BAD_DMA) { 1321 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1322 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1323 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1324 dma->idi_paddr = IF_BAD_DMA; 1325 } 1326 if (dma->idi_vaddr != NULL) { 1327 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1328 dma->idi_vaddr = NULL; 1329 } 1330 bus_dma_tag_destroy(dma->idi_tag); 1331 dma->idi_tag = NULL; 1332 } 1333 1334 void 1335 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1336 { 1337 int i; 1338 iflib_dma_info_t *dmaiter = dmalist; 1339 1340 for (i = 0; i < count; i++, dmaiter++) 1341 iflib_dma_free(*dmaiter); 1342 } 1343 1344 #ifdef EARLY_AP_STARTUP 1345 static const int iflib_started = 1; 1346 #else 1347 /* 1348 * We used to abuse the smp_started flag to decide if the queues have been 1349 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1350 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1351 * is set. Run a SYSINIT() strictly after that to just set a usable 1352 * completion flag. 1353 */ 1354 1355 static int iflib_started; 1356 1357 static void 1358 iflib_record_started(void *arg) 1359 { 1360 iflib_started = 1; 1361 } 1362 1363 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1364 iflib_record_started, NULL); 1365 #endif 1366 1367 static int 1368 iflib_fast_intr(void *arg) 1369 { 1370 iflib_filter_info_t info = arg; 1371 struct grouptask *gtask = info->ifi_task; 1372 if (!iflib_started) 1373 return (FILTER_HANDLED); 1374 1375 DBG_COUNTER_INC(fast_intrs); 1376 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1377 return (FILTER_HANDLED); 1378 1379 GROUPTASK_ENQUEUE(gtask); 1380 return (FILTER_HANDLED); 1381 } 1382 1383 static int 1384 iflib_fast_intr_rxtx(void *arg) 1385 { 1386 iflib_filter_info_t info = arg; 1387 struct grouptask *gtask = info->ifi_task; 1388 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1389 if_ctx_t ctx; 1390 int i, cidx; 1391 1392 if (!iflib_started) 1393 return (FILTER_HANDLED); 1394 1395 DBG_COUNTER_INC(fast_intrs); 1396 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1397 return (FILTER_HANDLED); 1398 1399 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1400 qidx_t txqid = rxq->ifr_txqid[i]; 1401 1402 ctx = rxq->ifr_ctx; 1403 1404 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1405 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1406 continue; 1407 } 1408 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1409 } 1410 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1411 cidx = rxq->ifr_cq_cidx; 1412 else 1413 cidx = rxq->ifr_fl[0].ifl_cidx; 1414 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1415 GROUPTASK_ENQUEUE(gtask); 1416 else 1417 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1418 return (FILTER_HANDLED); 1419 } 1420 1421 1422 static int 1423 iflib_fast_intr_ctx(void *arg) 1424 { 1425 iflib_filter_info_t info = arg; 1426 struct grouptask *gtask = info->ifi_task; 1427 1428 if (!iflib_started) 1429 return (FILTER_HANDLED); 1430 1431 DBG_COUNTER_INC(fast_intrs); 1432 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1433 return (FILTER_HANDLED); 1434 1435 GROUPTASK_ENQUEUE(gtask); 1436 return (FILTER_HANDLED); 1437 } 1438 1439 static int 1440 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1441 driver_filter_t filter, driver_intr_t handler, void *arg, 1442 char *name) 1443 { 1444 int rc; 1445 struct resource *res; 1446 void *tag; 1447 device_t dev = ctx->ifc_dev; 1448 1449 MPASS(rid < 512); 1450 irq->ii_rid = rid; 1451 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, 1452 RF_SHAREABLE | RF_ACTIVE); 1453 if (res == NULL) { 1454 device_printf(dev, 1455 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1456 return (ENOMEM); 1457 } 1458 irq->ii_res = res; 1459 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1460 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1461 filter, handler, arg, &tag); 1462 if (rc != 0) { 1463 device_printf(dev, 1464 "failed to setup interrupt for rid %d, name %s: %d\n", 1465 rid, name ? name : "unknown", rc); 1466 return (rc); 1467 } else if (name) 1468 bus_describe_intr(dev, res, tag, "%s", name); 1469 1470 irq->ii_tag = tag; 1471 return (0); 1472 } 1473 1474 1475 /********************************************************************* 1476 * 1477 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1478 * the information needed to transmit a packet on the wire. This is 1479 * called only once at attach, setup is done every reset. 1480 * 1481 **********************************************************************/ 1482 1483 static int 1484 iflib_txsd_alloc(iflib_txq_t txq) 1485 { 1486 if_ctx_t ctx = txq->ift_ctx; 1487 if_shared_ctx_t sctx = ctx->ifc_sctx; 1488 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1489 device_t dev = ctx->ifc_dev; 1490 int err, nsegments, ntsosegments; 1491 1492 nsegments = scctx->isc_tx_nsegments; 1493 ntsosegments = scctx->isc_tx_tso_segments_max; 1494 MPASS(scctx->isc_ntxd[0] > 0); 1495 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1496 MPASS(nsegments > 0); 1497 MPASS(ntsosegments > 0); 1498 /* 1499 * Setup DMA descriptor areas. 1500 */ 1501 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1502 1, 0, /* alignment, bounds */ 1503 BUS_SPACE_MAXADDR, /* lowaddr */ 1504 BUS_SPACE_MAXADDR, /* highaddr */ 1505 NULL, NULL, /* filter, filterarg */ 1506 sctx->isc_tx_maxsize, /* maxsize */ 1507 nsegments, /* nsegments */ 1508 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1509 0, /* flags */ 1510 NULL, /* lockfunc */ 1511 NULL, /* lockfuncarg */ 1512 &txq->ift_desc_tag))) { 1513 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1514 device_printf(dev,"maxsize: %zd nsegments: %d maxsegsize: %zd\n", 1515 sctx->isc_tx_maxsize, nsegments, sctx->isc_tx_maxsegsize); 1516 goto fail; 1517 } 1518 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1519 1, 0, /* alignment, bounds */ 1520 BUS_SPACE_MAXADDR, /* lowaddr */ 1521 BUS_SPACE_MAXADDR, /* highaddr */ 1522 NULL, NULL, /* filter, filterarg */ 1523 scctx->isc_tx_tso_size_max, /* maxsize */ 1524 ntsosegments, /* nsegments */ 1525 scctx->isc_tx_tso_segsize_max, /* maxsegsize */ 1526 0, /* flags */ 1527 NULL, /* lockfunc */ 1528 NULL, /* lockfuncarg */ 1529 &txq->ift_tso_desc_tag))) { 1530 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1531 1532 goto fail; 1533 } 1534 if (!(txq->ift_sds.ifsd_flags = 1535 (uint8_t *) malloc(sizeof(uint8_t) * 1536 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1537 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1538 err = ENOMEM; 1539 goto fail; 1540 } 1541 if (!(txq->ift_sds.ifsd_m = 1542 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1543 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1544 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1545 err = ENOMEM; 1546 goto fail; 1547 } 1548 1549 /* Create the descriptor buffer dma maps */ 1550 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1551 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1552 return (0); 1553 1554 if (!(txq->ift_sds.ifsd_map = 1555 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1556 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1557 err = ENOMEM; 1558 goto fail; 1559 } 1560 1561 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1562 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1563 if (err != 0) { 1564 device_printf(dev, "Unable to create TX DMA map\n"); 1565 goto fail; 1566 } 1567 } 1568 #endif 1569 return (0); 1570 fail: 1571 /* We free all, it handles case where we are in the middle */ 1572 iflib_tx_structures_free(ctx); 1573 return (err); 1574 } 1575 1576 static void 1577 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1578 { 1579 bus_dmamap_t map; 1580 1581 map = NULL; 1582 if (txq->ift_sds.ifsd_map != NULL) 1583 map = txq->ift_sds.ifsd_map[i]; 1584 if (map != NULL) { 1585 bus_dmamap_unload(txq->ift_desc_tag, map); 1586 bus_dmamap_destroy(txq->ift_desc_tag, map); 1587 txq->ift_sds.ifsd_map[i] = NULL; 1588 } 1589 } 1590 1591 static void 1592 iflib_txq_destroy(iflib_txq_t txq) 1593 { 1594 if_ctx_t ctx = txq->ift_ctx; 1595 1596 for (int i = 0; i < txq->ift_size; i++) 1597 iflib_txsd_destroy(ctx, txq, i); 1598 if (txq->ift_sds.ifsd_map != NULL) { 1599 free(txq->ift_sds.ifsd_map, M_IFLIB); 1600 txq->ift_sds.ifsd_map = NULL; 1601 } 1602 if (txq->ift_sds.ifsd_m != NULL) { 1603 free(txq->ift_sds.ifsd_m, M_IFLIB); 1604 txq->ift_sds.ifsd_m = NULL; 1605 } 1606 if (txq->ift_sds.ifsd_flags != NULL) { 1607 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1608 txq->ift_sds.ifsd_flags = NULL; 1609 } 1610 if (txq->ift_desc_tag != NULL) { 1611 bus_dma_tag_destroy(txq->ift_desc_tag); 1612 txq->ift_desc_tag = NULL; 1613 } 1614 if (txq->ift_tso_desc_tag != NULL) { 1615 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1616 txq->ift_tso_desc_tag = NULL; 1617 } 1618 } 1619 1620 static void 1621 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1622 { 1623 struct mbuf **mp; 1624 1625 mp = &txq->ift_sds.ifsd_m[i]; 1626 if (*mp == NULL) 1627 return; 1628 1629 if (txq->ift_sds.ifsd_map != NULL) { 1630 bus_dmamap_sync(txq->ift_desc_tag, 1631 txq->ift_sds.ifsd_map[i], 1632 BUS_DMASYNC_POSTWRITE); 1633 bus_dmamap_unload(txq->ift_desc_tag, 1634 txq->ift_sds.ifsd_map[i]); 1635 } 1636 m_free(*mp); 1637 DBG_COUNTER_INC(tx_frees); 1638 *mp = NULL; 1639 } 1640 1641 static int 1642 iflib_txq_setup(iflib_txq_t txq) 1643 { 1644 if_ctx_t ctx = txq->ift_ctx; 1645 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1646 iflib_dma_info_t di; 1647 int i; 1648 1649 /* Set number of descriptors available */ 1650 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1651 /* XXX make configurable */ 1652 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1653 1654 /* Reset indices */ 1655 txq->ift_cidx_processed = 0; 1656 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1657 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1658 1659 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1660 bzero((void *)di->idi_vaddr, di->idi_size); 1661 1662 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1663 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1664 bus_dmamap_sync(di->idi_tag, di->idi_map, 1665 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1666 return (0); 1667 } 1668 1669 /********************************************************************* 1670 * 1671 * Allocate memory for rx_buffer structures. Since we use one 1672 * rx_buffer per received packet, the maximum number of rx_buffer's 1673 * that we'll need is equal to the number of receive descriptors 1674 * that we've allocated. 1675 * 1676 **********************************************************************/ 1677 static int 1678 iflib_rxsd_alloc(iflib_rxq_t rxq) 1679 { 1680 if_ctx_t ctx = rxq->ifr_ctx; 1681 if_shared_ctx_t sctx = ctx->ifc_sctx; 1682 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1683 device_t dev = ctx->ifc_dev; 1684 iflib_fl_t fl; 1685 int err; 1686 1687 MPASS(scctx->isc_nrxd[0] > 0); 1688 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1689 1690 fl = rxq->ifr_fl; 1691 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1692 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1693 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1694 1, 0, /* alignment, bounds */ 1695 BUS_SPACE_MAXADDR, /* lowaddr */ 1696 BUS_SPACE_MAXADDR, /* highaddr */ 1697 NULL, NULL, /* filter, filterarg */ 1698 sctx->isc_rx_maxsize, /* maxsize */ 1699 sctx->isc_rx_nsegments, /* nsegments */ 1700 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1701 0, /* flags */ 1702 NULL, /* lockfunc */ 1703 NULL, /* lockarg */ 1704 &fl->ifl_desc_tag); 1705 if (err) { 1706 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1707 __func__, err); 1708 goto fail; 1709 } 1710 if (!(fl->ifl_sds.ifsd_flags = 1711 (uint8_t *) malloc(sizeof(uint8_t) * 1712 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1713 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1714 err = ENOMEM; 1715 goto fail; 1716 } 1717 if (!(fl->ifl_sds.ifsd_m = 1718 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1719 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1720 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1721 err = ENOMEM; 1722 goto fail; 1723 } 1724 if (!(fl->ifl_sds.ifsd_cl = 1725 (caddr_t *) malloc(sizeof(caddr_t) * 1726 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1727 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1728 err = ENOMEM; 1729 goto fail; 1730 } 1731 1732 /* Create the descriptor buffer dma maps */ 1733 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1734 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1735 continue; 1736 1737 if (!(fl->ifl_sds.ifsd_map = 1738 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1739 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1740 err = ENOMEM; 1741 goto fail; 1742 } 1743 1744 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1745 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1746 if (err != 0) { 1747 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1748 goto fail; 1749 } 1750 } 1751 #endif 1752 } 1753 return (0); 1754 1755 fail: 1756 iflib_rx_structures_free(ctx); 1757 return (err); 1758 } 1759 1760 1761 /* 1762 * Internal service routines 1763 */ 1764 1765 struct rxq_refill_cb_arg { 1766 int error; 1767 bus_dma_segment_t seg; 1768 int nseg; 1769 }; 1770 1771 static void 1772 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1773 { 1774 struct rxq_refill_cb_arg *cb_arg = arg; 1775 1776 cb_arg->error = error; 1777 cb_arg->seg = segs[0]; 1778 cb_arg->nseg = nseg; 1779 } 1780 1781 1782 #ifdef ACPI_DMAR 1783 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1784 #else 1785 #define IS_DMAR(ctx) (0) 1786 #endif 1787 1788 /** 1789 * rxq_refill - refill an rxq free-buffer list 1790 * @ctx: the iflib context 1791 * @rxq: the free-list to refill 1792 * @n: the number of new buffers to allocate 1793 * 1794 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1795 * The caller must assure that @n does not exceed the queue's capacity. 1796 */ 1797 static void 1798 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1799 { 1800 struct mbuf *m; 1801 int idx, pidx = fl->ifl_pidx; 1802 caddr_t cl, *sd_cl; 1803 struct mbuf **sd_m; 1804 uint8_t *sd_flags; 1805 struct if_rxd_update iru; 1806 bus_dmamap_t *sd_map; 1807 int n, i = 0; 1808 uint64_t bus_addr; 1809 int err; 1810 1811 sd_m = fl->ifl_sds.ifsd_m; 1812 sd_map = fl->ifl_sds.ifsd_map; 1813 sd_cl = fl->ifl_sds.ifsd_cl; 1814 sd_flags = fl->ifl_sds.ifsd_flags; 1815 idx = pidx; 1816 1817 n = count; 1818 MPASS(n > 0); 1819 MPASS(fl->ifl_credits + n <= fl->ifl_size); 1820 1821 if (pidx < fl->ifl_cidx) 1822 MPASS(pidx + n <= fl->ifl_cidx); 1823 if (pidx == fl->ifl_cidx && (fl->ifl_credits < fl->ifl_size)) 1824 MPASS(fl->ifl_gen == 0); 1825 if (pidx > fl->ifl_cidx) 1826 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1827 1828 DBG_COUNTER_INC(fl_refills); 1829 if (n > 8) 1830 DBG_COUNTER_INC(fl_refills_large); 1831 iru.iru_paddrs = fl->ifl_bus_addrs; 1832 iru.iru_vaddrs = &fl->ifl_vm_addrs[0]; 1833 iru.iru_idxs = fl->ifl_rxd_idxs; 1834 iru.iru_qsidx = fl->ifl_rxq->ifr_id; 1835 iru.iru_buf_size = fl->ifl_buf_size; 1836 iru.iru_flidx = fl->ifl_id; 1837 while (n--) { 1838 /* 1839 * We allocate an uninitialized mbuf + cluster, mbuf is 1840 * initialized after rx. 1841 * 1842 * If the cluster is still set then we know a minimum sized packet was received 1843 */ 1844 if ((cl = sd_cl[idx]) == NULL) { 1845 if ((cl = sd_cl[idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1846 break; 1847 #if MEMORY_LOGGING 1848 fl->ifl_cl_enqueued++; 1849 #endif 1850 } 1851 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1852 break; 1853 } 1854 #if MEMORY_LOGGING 1855 fl->ifl_m_enqueued++; 1856 #endif 1857 1858 DBG_COUNTER_INC(rx_allocs); 1859 #if defined(__i386__) || defined(__amd64__) 1860 if (!IS_DMAR(ctx)) { 1861 bus_addr = pmap_kextract((vm_offset_t)cl); 1862 } else 1863 #endif 1864 { 1865 struct rxq_refill_cb_arg cb_arg; 1866 iflib_rxq_t q; 1867 1868 cb_arg.error = 0; 1869 q = fl->ifl_rxq; 1870 MPASS(sd_map != NULL); 1871 MPASS(sd_map[idx] != NULL); 1872 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[idx], 1873 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1874 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[idx], BUS_DMASYNC_PREREAD); 1875 1876 if (err != 0 || cb_arg.error) { 1877 /* 1878 * !zone_pack ? 1879 */ 1880 if (fl->ifl_zone == zone_pack) 1881 uma_zfree(fl->ifl_zone, cl); 1882 m_free(m); 1883 n = 0; 1884 goto done; 1885 } 1886 bus_addr = cb_arg.seg.ds_addr; 1887 } 1888 sd_flags[idx] |= RX_SW_DESC_INUSE; 1889 1890 MPASS(sd_m[idx] == NULL); 1891 sd_cl[idx] = cl; 1892 sd_m[idx] = m; 1893 fl->ifl_rxd_idxs[i] = idx; 1894 fl->ifl_bus_addrs[i] = bus_addr; 1895 fl->ifl_vm_addrs[i] = cl; 1896 fl->ifl_credits++; 1897 i++; 1898 MPASS(fl->ifl_credits <= fl->ifl_size); 1899 if (++idx == fl->ifl_size) { 1900 fl->ifl_gen = 1; 1901 idx = 0; 1902 } 1903 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 1904 iru.iru_pidx = pidx; 1905 iru.iru_count = i; 1906 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1907 i = 0; 1908 pidx = idx; 1909 } 1910 fl->ifl_pidx = idx; 1911 1912 } 1913 done: 1914 DBG_COUNTER_INC(rxd_flush); 1915 if (fl->ifl_pidx == 0) 1916 pidx = fl->ifl_size - 1; 1917 else 1918 pidx = fl->ifl_pidx - 1; 1919 1920 if (sd_map) 1921 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1922 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1923 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 1924 } 1925 1926 static __inline void 1927 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 1928 { 1929 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 1930 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 1931 #ifdef INVARIANTS 1932 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 1933 #endif 1934 1935 MPASS(fl->ifl_credits <= fl->ifl_size); 1936 MPASS(reclaimable == delta); 1937 1938 if (reclaimable > 0) 1939 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 1940 } 1941 1942 static void 1943 iflib_fl_bufs_free(iflib_fl_t fl) 1944 { 1945 iflib_dma_info_t idi = fl->ifl_ifdi; 1946 uint32_t i; 1947 1948 for (i = 0; i < fl->ifl_size; i++) { 1949 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 1950 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 1951 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 1952 1953 if (*sd_flags & RX_SW_DESC_INUSE) { 1954 if (fl->ifl_sds.ifsd_map != NULL) { 1955 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 1956 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 1957 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 1958 } 1959 if (*sd_m != NULL) { 1960 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 1961 uma_zfree(zone_mbuf, *sd_m); 1962 } 1963 if (*sd_cl != NULL) 1964 uma_zfree(fl->ifl_zone, *sd_cl); 1965 *sd_flags = 0; 1966 } else { 1967 MPASS(*sd_cl == NULL); 1968 MPASS(*sd_m == NULL); 1969 } 1970 #if MEMORY_LOGGING 1971 fl->ifl_m_dequeued++; 1972 fl->ifl_cl_dequeued++; 1973 #endif 1974 *sd_cl = NULL; 1975 *sd_m = NULL; 1976 } 1977 #ifdef INVARIANTS 1978 for (i = 0; i < fl->ifl_size; i++) { 1979 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 1980 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 1981 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 1982 } 1983 #endif 1984 /* 1985 * Reset free list values 1986 */ 1987 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = 0;; 1988 bzero(idi->idi_vaddr, idi->idi_size); 1989 } 1990 1991 /********************************************************************* 1992 * 1993 * Initialize a receive ring and its buffers. 1994 * 1995 **********************************************************************/ 1996 static int 1997 iflib_fl_setup(iflib_fl_t fl) 1998 { 1999 iflib_rxq_t rxq = fl->ifl_rxq; 2000 if_ctx_t ctx = rxq->ifr_ctx; 2001 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2002 2003 /* 2004 ** Free current RX buffer structs and their mbufs 2005 */ 2006 iflib_fl_bufs_free(fl); 2007 /* Now replenish the mbufs */ 2008 MPASS(fl->ifl_credits == 0); 2009 /* 2010 * XXX don't set the max_frame_size to larger 2011 * than the hardware can handle 2012 */ 2013 if (sctx->isc_max_frame_size <= 2048) 2014 fl->ifl_buf_size = MCLBYTES; 2015 #ifndef CONTIGMALLOC_WORKS 2016 else 2017 fl->ifl_buf_size = MJUMPAGESIZE; 2018 #else 2019 else if (sctx->isc_max_frame_size <= 4096) 2020 fl->ifl_buf_size = MJUMPAGESIZE; 2021 else if (sctx->isc_max_frame_size <= 9216) 2022 fl->ifl_buf_size = MJUM9BYTES; 2023 else 2024 fl->ifl_buf_size = MJUM16BYTES; 2025 #endif 2026 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2027 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2028 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2029 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2030 2031 2032 /* avoid pre-allocating zillions of clusters to an idle card 2033 * potentially speeding up attach 2034 */ 2035 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2036 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2037 if (min(128, fl->ifl_size) != fl->ifl_credits) 2038 return (ENOBUFS); 2039 /* 2040 * handle failure 2041 */ 2042 MPASS(rxq != NULL); 2043 MPASS(fl->ifl_ifdi != NULL); 2044 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2045 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2046 return (0); 2047 } 2048 2049 /********************************************************************* 2050 * 2051 * Free receive ring data structures 2052 * 2053 **********************************************************************/ 2054 static void 2055 iflib_rx_sds_free(iflib_rxq_t rxq) 2056 { 2057 iflib_fl_t fl; 2058 int i; 2059 2060 if (rxq->ifr_fl != NULL) { 2061 for (i = 0; i < rxq->ifr_nfl; i++) { 2062 fl = &rxq->ifr_fl[i]; 2063 if (fl->ifl_desc_tag != NULL) { 2064 bus_dma_tag_destroy(fl->ifl_desc_tag); 2065 fl->ifl_desc_tag = NULL; 2066 } 2067 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2068 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2069 /* XXX destroy maps first */ 2070 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2071 fl->ifl_sds.ifsd_m = NULL; 2072 fl->ifl_sds.ifsd_cl = NULL; 2073 fl->ifl_sds.ifsd_map = NULL; 2074 } 2075 free(rxq->ifr_fl, M_IFLIB); 2076 rxq->ifr_fl = NULL; 2077 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2078 } 2079 } 2080 2081 /* 2082 * MI independent logic 2083 * 2084 */ 2085 static void 2086 iflib_timer(void *arg) 2087 { 2088 iflib_txq_t txq = arg; 2089 if_ctx_t ctx = txq->ift_ctx; 2090 2091 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2092 return; 2093 /* 2094 ** Check on the state of the TX queue(s), this 2095 ** can be done without the lock because its RO 2096 ** and the HUNG state will be static if set. 2097 */ 2098 IFDI_TIMER(ctx, txq->ift_id); 2099 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2100 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2101 (ctx->ifc_pause_frames == 0))) 2102 goto hung; 2103 2104 if (ifmp_ring_is_stalled(txq->ift_br)) 2105 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2106 txq->ift_cleaned_prev = txq->ift_cleaned; 2107 /* handle any laggards */ 2108 if (txq->ift_db_pending) 2109 GROUPTASK_ENQUEUE(&txq->ift_task); 2110 2111 ctx->ifc_pause_frames = 0; 2112 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2113 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 2114 return; 2115 hung: 2116 CTX_LOCK(ctx); 2117 if_setdrvflagbits(ctx->ifc_ifp, 0, IFF_DRV_RUNNING); 2118 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2119 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2120 2121 IFDI_WATCHDOG_RESET(ctx); 2122 ctx->ifc_watchdog_events++; 2123 ctx->ifc_pause_frames = 0; 2124 2125 iflib_init_locked(ctx); 2126 CTX_UNLOCK(ctx); 2127 } 2128 2129 static void 2130 iflib_init_locked(if_ctx_t ctx) 2131 { 2132 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2133 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2134 if_t ifp = ctx->ifc_ifp; 2135 iflib_fl_t fl; 2136 iflib_txq_t txq; 2137 iflib_rxq_t rxq; 2138 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2139 2140 2141 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2142 IFDI_INTR_DISABLE(ctx); 2143 2144 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2145 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2146 /* Set hardware offload abilities */ 2147 if_clearhwassist(ifp); 2148 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2149 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2150 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2151 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2152 if (if_getcapenable(ifp) & IFCAP_TSO4) 2153 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2154 if (if_getcapenable(ifp) & IFCAP_TSO6) 2155 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2156 2157 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2158 CALLOUT_LOCK(txq); 2159 callout_stop(&txq->ift_timer); 2160 CALLOUT_UNLOCK(txq); 2161 iflib_netmap_txq_init(ctx, txq); 2162 } 2163 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2164 MPASS(rxq->ifr_id == i); 2165 iflib_netmap_rxq_init(ctx, rxq); 2166 } 2167 #ifdef INVARIANTS 2168 i = if_getdrvflags(ifp); 2169 #endif 2170 IFDI_INIT(ctx); 2171 MPASS(if_getdrvflags(ifp) == i); 2172 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2173 /* XXX this should really be done on a per-queue basis */ 2174 if (if_getcapenable(ifp) & IFCAP_NETMAP) 2175 continue; 2176 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2177 if (iflib_fl_setup(fl)) { 2178 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2179 goto done; 2180 } 2181 } 2182 } 2183 done: 2184 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2185 IFDI_INTR_ENABLE(ctx); 2186 txq = ctx->ifc_txqs; 2187 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2188 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2189 txq->ift_timer.c_cpu); 2190 } 2191 2192 static int 2193 iflib_media_change(if_t ifp) 2194 { 2195 if_ctx_t ctx = if_getsoftc(ifp); 2196 int err; 2197 2198 CTX_LOCK(ctx); 2199 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2200 iflib_init_locked(ctx); 2201 CTX_UNLOCK(ctx); 2202 return (err); 2203 } 2204 2205 static void 2206 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2207 { 2208 if_ctx_t ctx = if_getsoftc(ifp); 2209 2210 CTX_LOCK(ctx); 2211 IFDI_UPDATE_ADMIN_STATUS(ctx); 2212 IFDI_MEDIA_STATUS(ctx, ifmr); 2213 CTX_UNLOCK(ctx); 2214 } 2215 2216 static void 2217 iflib_stop(if_ctx_t ctx) 2218 { 2219 iflib_txq_t txq = ctx->ifc_txqs; 2220 iflib_rxq_t rxq = ctx->ifc_rxqs; 2221 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2222 iflib_dma_info_t di; 2223 iflib_fl_t fl; 2224 int i, j; 2225 2226 /* Tell the stack that the interface is no longer active */ 2227 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2228 2229 IFDI_INTR_DISABLE(ctx); 2230 DELAY(1000); 2231 IFDI_STOP(ctx); 2232 DELAY(1000); 2233 2234 iflib_debug_reset(); 2235 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2236 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2237 /* make sure all transmitters have completed before proceeding XXX */ 2238 2239 /* clean any enqueued buffers */ 2240 iflib_ifmp_purge(txq); 2241 /* Free any existing tx buffers. */ 2242 for (j = 0; j < txq->ift_size; j++) { 2243 iflib_txsd_free(ctx, txq, j); 2244 } 2245 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2246 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2247 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2248 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2249 txq->ift_pullups = 0; 2250 ifmp_ring_reset_stats(txq->ift_br); 2251 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2252 bzero((void *)di->idi_vaddr, di->idi_size); 2253 } 2254 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2255 /* make sure all transmitters have completed before proceeding XXX */ 2256 2257 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++) 2258 bzero((void *)di->idi_vaddr, di->idi_size); 2259 /* also resets the free lists pidx/cidx */ 2260 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2261 iflib_fl_bufs_free(fl); 2262 } 2263 } 2264 2265 static inline caddr_t 2266 calc_next_rxd(iflib_fl_t fl, int cidx) 2267 { 2268 qidx_t size; 2269 int nrxd; 2270 caddr_t start, end, cur, next; 2271 2272 nrxd = fl->ifl_size; 2273 size = fl->ifl_rxd_size; 2274 start = fl->ifl_ifdi->idi_vaddr; 2275 2276 if (__predict_false(size == 0)) 2277 return (start); 2278 cur = start + size*cidx; 2279 end = start + size*nrxd; 2280 next = CACHE_PTR_NEXT(cur); 2281 return (next < end ? next : start); 2282 } 2283 2284 static inline void 2285 prefetch_pkts(iflib_fl_t fl, int cidx) 2286 { 2287 int nextptr; 2288 int nrxd = fl->ifl_size; 2289 caddr_t next_rxd; 2290 2291 2292 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2293 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2294 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2295 next_rxd = calc_next_rxd(fl, cidx); 2296 prefetch(next_rxd); 2297 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2298 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2299 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2300 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2301 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2302 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2303 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2304 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2305 } 2306 2307 static void 2308 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2309 { 2310 int flid, cidx; 2311 bus_dmamap_t map; 2312 iflib_fl_t fl; 2313 iflib_dma_info_t di; 2314 int next; 2315 2316 map = NULL; 2317 flid = irf->irf_flid; 2318 cidx = irf->irf_idx; 2319 fl = &rxq->ifr_fl[flid]; 2320 sd->ifsd_fl = fl; 2321 sd->ifsd_cidx = cidx; 2322 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2323 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2324 fl->ifl_credits--; 2325 #if MEMORY_LOGGING 2326 fl->ifl_m_dequeued++; 2327 #endif 2328 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2329 prefetch_pkts(fl, cidx); 2330 if (fl->ifl_sds.ifsd_map != NULL) { 2331 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2332 prefetch(&fl->ifl_sds.ifsd_map[next]); 2333 map = fl->ifl_sds.ifsd_map[cidx]; 2334 di = fl->ifl_ifdi; 2335 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2336 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2337 bus_dmamap_sync(di->idi_tag, di->idi_map, 2338 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2339 2340 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2341 MPASS(fl->ifl_cidx == cidx); 2342 if (unload) 2343 bus_dmamap_unload(fl->ifl_desc_tag, map); 2344 } 2345 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2346 if (__predict_false(fl->ifl_cidx == 0)) 2347 fl->ifl_gen = 0; 2348 if (map != NULL) 2349 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2350 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2351 } 2352 2353 static struct mbuf * 2354 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2355 { 2356 int i, padlen , flags; 2357 struct mbuf *m, *mh, *mt; 2358 caddr_t cl; 2359 2360 i = 0; 2361 mh = NULL; 2362 do { 2363 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2364 2365 MPASS(*sd->ifsd_cl != NULL); 2366 MPASS(*sd->ifsd_m != NULL); 2367 2368 /* Don't include zero-length frags */ 2369 if (ri->iri_frags[i].irf_len == 0) { 2370 /* XXX we can save the cluster here, but not the mbuf */ 2371 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2372 m_free(*sd->ifsd_m); 2373 *sd->ifsd_m = NULL; 2374 continue; 2375 } 2376 m = *sd->ifsd_m; 2377 *sd->ifsd_m = NULL; 2378 if (mh == NULL) { 2379 flags = M_PKTHDR|M_EXT; 2380 mh = mt = m; 2381 padlen = ri->iri_pad; 2382 } else { 2383 flags = M_EXT; 2384 mt->m_next = m; 2385 mt = m; 2386 /* assuming padding is only on the first fragment */ 2387 padlen = 0; 2388 } 2389 cl = *sd->ifsd_cl; 2390 *sd->ifsd_cl = NULL; 2391 2392 /* Can these two be made one ? */ 2393 m_init(m, M_NOWAIT, MT_DATA, flags); 2394 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2395 /* 2396 * These must follow m_init and m_cljset 2397 */ 2398 m->m_data += padlen; 2399 ri->iri_len -= padlen; 2400 m->m_len = ri->iri_frags[i].irf_len; 2401 } while (++i < ri->iri_nfrags); 2402 2403 return (mh); 2404 } 2405 2406 /* 2407 * Process one software descriptor 2408 */ 2409 static struct mbuf * 2410 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2411 { 2412 struct if_rxsd sd; 2413 struct mbuf *m; 2414 2415 /* should I merge this back in now that the two paths are basically duplicated? */ 2416 if (ri->iri_nfrags == 1 && 2417 ri->iri_frags[0].irf_len <= IFLIB_RX_COPY_THRESH) { 2418 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2419 m = *sd.ifsd_m; 2420 *sd.ifsd_m = NULL; 2421 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2422 #ifndef __NO_STRICT_ALIGNMENT 2423 if (!IP_ALIGNED(m)) 2424 m->m_data += 2; 2425 #endif 2426 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2427 m->m_len = ri->iri_frags[0].irf_len; 2428 } else { 2429 m = assemble_segments(rxq, ri, &sd); 2430 } 2431 m->m_pkthdr.len = ri->iri_len; 2432 m->m_pkthdr.rcvif = ri->iri_ifp; 2433 m->m_flags |= ri->iri_flags; 2434 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2435 m->m_pkthdr.flowid = ri->iri_flowid; 2436 M_HASHTYPE_SET(m, ri->iri_rsstype); 2437 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2438 m->m_pkthdr.csum_data = ri->iri_csum_data; 2439 return (m); 2440 } 2441 2442 static bool 2443 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2444 { 2445 if_ctx_t ctx = rxq->ifr_ctx; 2446 if_shared_ctx_t sctx = ctx->ifc_sctx; 2447 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2448 int avail, i; 2449 qidx_t *cidxp; 2450 struct if_rxd_info ri; 2451 int err, budget_left, rx_bytes, rx_pkts; 2452 iflib_fl_t fl; 2453 struct ifnet *ifp; 2454 int lro_enabled; 2455 2456 /* 2457 * XXX early demux data packets so that if_input processing only handles 2458 * acks in interrupt context 2459 */ 2460 struct mbuf *m, *mh, *mt; 2461 2462 ifp = ctx->ifc_ifp; 2463 #ifdef DEV_NETMAP 2464 if (ifp->if_capenable & IFCAP_NETMAP) { 2465 u_int work = 0; 2466 if (netmap_rx_irq(ifp, rxq->ifr_id, &work)) 2467 return (FALSE); 2468 } 2469 #endif 2470 2471 mh = mt = NULL; 2472 MPASS(budget > 0); 2473 rx_pkts = rx_bytes = 0; 2474 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2475 cidxp = &rxq->ifr_cq_cidx; 2476 else 2477 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2478 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2479 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2480 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2481 DBG_COUNTER_INC(rx_unavail); 2482 return (false); 2483 } 2484 2485 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2486 if (__predict_false(!CTX_ACTIVE(ctx))) { 2487 DBG_COUNTER_INC(rx_ctx_inactive); 2488 break; 2489 } 2490 /* 2491 * Reset client set fields to their default values 2492 */ 2493 rxd_info_zero(&ri); 2494 ri.iri_qsidx = rxq->ifr_id; 2495 ri.iri_cidx = *cidxp; 2496 ri.iri_ifp = ifp; 2497 ri.iri_frags = rxq->ifr_frags; 2498 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2499 2500 if (err) 2501 goto err; 2502 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2503 *cidxp = ri.iri_cidx; 2504 /* Update our consumer index */ 2505 /* XXX NB: shurd - check if this is still safe */ 2506 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2507 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2508 rxq->ifr_cq_gen = 0; 2509 } 2510 /* was this only a completion queue message? */ 2511 if (__predict_false(ri.iri_nfrags == 0)) 2512 continue; 2513 } 2514 MPASS(ri.iri_nfrags != 0); 2515 MPASS(ri.iri_len != 0); 2516 2517 /* will advance the cidx on the corresponding free lists */ 2518 m = iflib_rxd_pkt_get(rxq, &ri); 2519 if (avail == 0 && budget_left) 2520 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2521 2522 if (__predict_false(m == NULL)) { 2523 DBG_COUNTER_INC(rx_mbuf_null); 2524 continue; 2525 } 2526 /* imm_pkt: -- cxgb */ 2527 if (mh == NULL) 2528 mh = mt = m; 2529 else { 2530 mt->m_nextpkt = m; 2531 mt = m; 2532 } 2533 } 2534 /* make sure that we can refill faster than drain */ 2535 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2536 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2537 2538 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2539 while (mh != NULL) { 2540 m = mh; 2541 mh = mh->m_nextpkt; 2542 m->m_nextpkt = NULL; 2543 #ifndef __NO_STRICT_ALIGNMENT 2544 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2545 continue; 2546 #endif 2547 rx_bytes += m->m_pkthdr.len; 2548 rx_pkts++; 2549 #if defined(INET6) || defined(INET) 2550 if (lro_enabled && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2551 continue; 2552 #endif 2553 DBG_COUNTER_INC(rx_if_input); 2554 ifp->if_input(ifp, m); 2555 } 2556 2557 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2558 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2559 2560 /* 2561 * Flush any outstanding LRO work 2562 */ 2563 #if defined(INET6) || defined(INET) 2564 tcp_lro_flush_all(&rxq->ifr_lc); 2565 #endif 2566 if (avail) 2567 return true; 2568 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2569 err: 2570 CTX_LOCK(ctx); 2571 ctx->ifc_flags |= IFC_DO_RESET; 2572 iflib_admin_intr_deferred(ctx); 2573 CTX_UNLOCK(ctx); 2574 return (false); 2575 } 2576 2577 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2578 static inline qidx_t 2579 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2580 { 2581 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2582 qidx_t minthresh = txq->ift_size / 8; 2583 if (in_use > 4*minthresh) 2584 return (notify_count); 2585 if (in_use > 2*minthresh) 2586 return (notify_count >> 1); 2587 if (in_use > minthresh) 2588 return (notify_count >> 3); 2589 return (0); 2590 } 2591 2592 static inline qidx_t 2593 txq_max_rs_deferred(iflib_txq_t txq) 2594 { 2595 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2596 qidx_t minthresh = txq->ift_size / 8; 2597 if (txq->ift_in_use > 4*minthresh) 2598 return (notify_count); 2599 if (txq->ift_in_use > 2*minthresh) 2600 return (notify_count >> 1); 2601 if (txq->ift_in_use > minthresh) 2602 return (notify_count >> 2); 2603 return (notify_count >> 4); 2604 } 2605 2606 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2607 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2608 2609 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2610 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2611 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2612 2613 /* forward compatibility for cxgb */ 2614 #define FIRST_QSET(ctx) 0 2615 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2616 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2617 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2618 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2619 2620 /* XXX we should be setting this to something other than zero */ 2621 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2622 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2623 2624 static inline bool 2625 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2626 { 2627 qidx_t dbval, max; 2628 bool rang; 2629 2630 rang = false; 2631 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2632 if (ring || txq->ift_db_pending >= max) { 2633 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2634 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2635 txq->ift_db_pending = txq->ift_npending = 0; 2636 rang = true; 2637 } 2638 return (rang); 2639 } 2640 2641 #ifdef PKT_DEBUG 2642 static void 2643 print_pkt(if_pkt_info_t pi) 2644 { 2645 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2646 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2647 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2648 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2649 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2650 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2651 } 2652 #endif 2653 2654 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2655 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2656 2657 static int 2658 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2659 { 2660 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2661 struct ether_vlan_header *eh; 2662 struct mbuf *m, *n; 2663 2664 n = m = *mp; 2665 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2666 M_WRITABLE(m) == 0) { 2667 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2668 return (ENOMEM); 2669 } else { 2670 m_freem(*mp); 2671 n = *mp = m; 2672 } 2673 } 2674 2675 /* 2676 * Determine where frame payload starts. 2677 * Jump over vlan headers if already present, 2678 * helpful for QinQ too. 2679 */ 2680 if (__predict_false(m->m_len < sizeof(*eh))) { 2681 txq->ift_pullups++; 2682 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2683 return (ENOMEM); 2684 } 2685 eh = mtod(m, struct ether_vlan_header *); 2686 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2687 pi->ipi_etype = ntohs(eh->evl_proto); 2688 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2689 } else { 2690 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2691 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2692 } 2693 2694 switch (pi->ipi_etype) { 2695 #ifdef INET 2696 case ETHERTYPE_IP: 2697 { 2698 struct ip *ip = NULL; 2699 struct tcphdr *th = NULL; 2700 int minthlen; 2701 2702 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2703 if (__predict_false(m->m_len < minthlen)) { 2704 /* 2705 * if this code bloat is causing too much of a hit 2706 * move it to a separate function and mark it noinline 2707 */ 2708 if (m->m_len == pi->ipi_ehdrlen) { 2709 n = m->m_next; 2710 MPASS(n); 2711 if (n->m_len >= sizeof(*ip)) { 2712 ip = (struct ip *)n->m_data; 2713 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2714 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2715 } else { 2716 txq->ift_pullups++; 2717 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2718 return (ENOMEM); 2719 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2720 } 2721 } else { 2722 txq->ift_pullups++; 2723 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2724 return (ENOMEM); 2725 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2726 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2727 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2728 } 2729 } else { 2730 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2731 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2732 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2733 } 2734 pi->ipi_ip_hlen = ip->ip_hl << 2; 2735 pi->ipi_ipproto = ip->ip_p; 2736 pi->ipi_flags |= IPI_TX_IPV4; 2737 2738 if (pi->ipi_csum_flags & CSUM_IP) 2739 ip->ip_sum = 0; 2740 2741 if (pi->ipi_ipproto == IPPROTO_TCP) { 2742 if (__predict_false(th == NULL)) { 2743 txq->ift_pullups++; 2744 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2745 return (ENOMEM); 2746 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2747 } 2748 pi->ipi_tcp_hflags = th->th_flags; 2749 pi->ipi_tcp_hlen = th->th_off << 2; 2750 pi->ipi_tcp_seq = th->th_seq; 2751 } 2752 if (IS_TSO4(pi)) { 2753 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2754 return (ENXIO); 2755 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2756 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2757 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2758 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2759 ip->ip_sum = 0; 2760 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2761 } 2762 } 2763 break; 2764 } 2765 #endif 2766 #ifdef INET6 2767 case ETHERTYPE_IPV6: 2768 { 2769 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2770 struct tcphdr *th; 2771 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2772 2773 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2774 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2775 return (ENOMEM); 2776 } 2777 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2778 2779 /* XXX-BZ this will go badly in case of ext hdrs. */ 2780 pi->ipi_ipproto = ip6->ip6_nxt; 2781 pi->ipi_flags |= IPI_TX_IPV6; 2782 2783 if (pi->ipi_ipproto == IPPROTO_TCP) { 2784 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2785 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2786 return (ENOMEM); 2787 } 2788 pi->ipi_tcp_hflags = th->th_flags; 2789 pi->ipi_tcp_hlen = th->th_off << 2; 2790 } 2791 if (IS_TSO6(pi)) { 2792 2793 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2794 return (ENXIO); 2795 /* 2796 * The corresponding flag is set by the stack in the IPv4 2797 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 2798 * So, set it here because the rest of the flow requires it. 2799 */ 2800 pi->ipi_csum_flags |= CSUM_TCP_IPV6; 2801 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2802 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2803 } 2804 break; 2805 } 2806 #endif 2807 default: 2808 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2809 pi->ipi_ip_hlen = 0; 2810 break; 2811 } 2812 *mp = m; 2813 2814 return (0); 2815 } 2816 2817 static __noinline struct mbuf * 2818 collapse_pkthdr(struct mbuf *m0) 2819 { 2820 struct mbuf *m, *m_next, *tmp; 2821 2822 m = m0; 2823 m_next = m->m_next; 2824 while (m_next != NULL && m_next->m_len == 0) { 2825 m = m_next; 2826 m->m_next = NULL; 2827 m_free(m); 2828 m_next = m_next->m_next; 2829 } 2830 m = m0; 2831 m->m_next = m_next; 2832 if ((m_next->m_flags & M_EXT) == 0) { 2833 m = m_defrag(m, M_NOWAIT); 2834 } else { 2835 tmp = m_next->m_next; 2836 memcpy(m_next, m, MPKTHSIZE); 2837 m = m_next; 2838 m->m_next = tmp; 2839 } 2840 return (m); 2841 } 2842 2843 /* 2844 * If dodgy hardware rejects the scatter gather chain we've handed it 2845 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 2846 * m_defrag'd mbufs 2847 */ 2848 static __noinline struct mbuf * 2849 iflib_remove_mbuf(iflib_txq_t txq) 2850 { 2851 int ntxd, i, pidx; 2852 struct mbuf *m, *mh, **ifsd_m; 2853 2854 pidx = txq->ift_pidx; 2855 ifsd_m = txq->ift_sds.ifsd_m; 2856 ntxd = txq->ift_size; 2857 mh = m = ifsd_m[pidx]; 2858 ifsd_m[pidx] = NULL; 2859 #if MEMORY_LOGGING 2860 txq->ift_dequeued++; 2861 #endif 2862 i = 1; 2863 2864 while (m) { 2865 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 2866 #if MEMORY_LOGGING 2867 txq->ift_dequeued++; 2868 #endif 2869 m = m->m_next; 2870 i++; 2871 } 2872 return (mh); 2873 } 2874 2875 static int 2876 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 2877 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 2878 int max_segs, int flags) 2879 { 2880 if_ctx_t ctx; 2881 if_shared_ctx_t sctx; 2882 if_softc_ctx_t scctx; 2883 int i, next, pidx, mask, err, maxsegsz, ntxd, count; 2884 struct mbuf *m, *tmp, **ifsd_m, **mp; 2885 2886 m = *m0; 2887 2888 /* 2889 * Please don't ever do this 2890 */ 2891 if (__predict_false(m->m_len == 0)) 2892 *m0 = m = collapse_pkthdr(m); 2893 2894 ctx = txq->ift_ctx; 2895 sctx = ctx->ifc_sctx; 2896 scctx = &ctx->ifc_softc_ctx; 2897 ifsd_m = txq->ift_sds.ifsd_m; 2898 ntxd = txq->ift_size; 2899 pidx = txq->ift_pidx; 2900 if (map != NULL) { 2901 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 2902 2903 err = bus_dmamap_load_mbuf_sg(tag, map, 2904 *m0, segs, nsegs, BUS_DMA_NOWAIT); 2905 if (err) 2906 return (err); 2907 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 2908 i = 0; 2909 next = pidx; 2910 mask = (txq->ift_size-1); 2911 m = *m0; 2912 do { 2913 mp = &ifsd_m[next]; 2914 *mp = m; 2915 m = m->m_next; 2916 if (__predict_false((*mp)->m_len == 0)) { 2917 m_free(*mp); 2918 *mp = NULL; 2919 } else 2920 next = (pidx + i) & (ntxd-1); 2921 } while (m != NULL); 2922 } else { 2923 int buflen, sgsize, max_sgsize; 2924 vm_offset_t vaddr; 2925 vm_paddr_t curaddr; 2926 2927 count = i = 0; 2928 maxsegsz = sctx->isc_tx_maxsize; 2929 m = *m0; 2930 do { 2931 if (__predict_false(m->m_len <= 0)) { 2932 tmp = m; 2933 m = m->m_next; 2934 tmp->m_next = NULL; 2935 m_free(tmp); 2936 continue; 2937 } 2938 buflen = m->m_len; 2939 vaddr = (vm_offset_t)m->m_data; 2940 /* 2941 * see if we can't be smarter about physically 2942 * contiguous mappings 2943 */ 2944 next = (pidx + count) & (ntxd-1); 2945 MPASS(ifsd_m[next] == NULL); 2946 #if MEMORY_LOGGING 2947 txq->ift_enqueued++; 2948 #endif 2949 ifsd_m[next] = m; 2950 while (buflen > 0) { 2951 max_sgsize = MIN(buflen, maxsegsz); 2952 curaddr = pmap_kextract(vaddr); 2953 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 2954 sgsize = MIN(sgsize, max_sgsize); 2955 segs[i].ds_addr = curaddr; 2956 segs[i].ds_len = sgsize; 2957 vaddr += sgsize; 2958 buflen -= sgsize; 2959 i++; 2960 if (i >= max_segs) 2961 goto err; 2962 } 2963 count++; 2964 tmp = m; 2965 m = m->m_next; 2966 } while (m != NULL); 2967 *nsegs = i; 2968 } 2969 return (0); 2970 err: 2971 *m0 = iflib_remove_mbuf(txq); 2972 return (EFBIG); 2973 } 2974 2975 static inline caddr_t 2976 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 2977 { 2978 qidx_t size; 2979 int ntxd; 2980 caddr_t start, end, cur, next; 2981 2982 ntxd = txq->ift_size; 2983 size = txq->ift_txd_size[qid]; 2984 start = txq->ift_ifdi[qid].idi_vaddr; 2985 2986 if (__predict_false(size == 0)) 2987 return (start); 2988 cur = start + size*cidx; 2989 end = start + size*ntxd; 2990 next = CACHE_PTR_NEXT(cur); 2991 return (next < end ? next : start); 2992 } 2993 2994 static int 2995 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 2996 { 2997 if_ctx_t ctx; 2998 if_shared_ctx_t sctx; 2999 if_softc_ctx_t scctx; 3000 bus_dma_segment_t *segs; 3001 struct mbuf *m_head; 3002 void *next_txd; 3003 bus_dmamap_t map; 3004 struct if_pkt_info pi; 3005 int remap = 0; 3006 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3007 bus_dma_tag_t desc_tag; 3008 3009 segs = txq->ift_segs; 3010 ctx = txq->ift_ctx; 3011 sctx = ctx->ifc_sctx; 3012 scctx = &ctx->ifc_softc_ctx; 3013 segs = txq->ift_segs; 3014 ntxd = txq->ift_size; 3015 m_head = *m_headp; 3016 map = NULL; 3017 3018 /* 3019 * If we're doing TSO the next descriptor to clean may be quite far ahead 3020 */ 3021 cidx = txq->ift_cidx; 3022 pidx = txq->ift_pidx; 3023 if (ctx->ifc_flags & IFC_PREFETCH) { 3024 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3025 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3026 next_txd = calc_next_txd(txq, cidx, 0); 3027 prefetch(next_txd); 3028 } 3029 3030 /* prefetch the next cache line of mbuf pointers and flags */ 3031 prefetch(&txq->ift_sds.ifsd_m[next]); 3032 if (txq->ift_sds.ifsd_map != NULL) { 3033 prefetch(&txq->ift_sds.ifsd_map[next]); 3034 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3035 prefetch(&txq->ift_sds.ifsd_flags[next]); 3036 } 3037 } else if (txq->ift_sds.ifsd_map != NULL) 3038 map = txq->ift_sds.ifsd_map[pidx]; 3039 3040 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3041 desc_tag = txq->ift_tso_desc_tag; 3042 max_segs = scctx->isc_tx_tso_segments_max; 3043 } else { 3044 desc_tag = txq->ift_desc_tag; 3045 max_segs = scctx->isc_tx_nsegments; 3046 } 3047 m_head = *m_headp; 3048 3049 pkt_info_zero(&pi); 3050 pi.ipi_len = m_head->m_pkthdr.len; 3051 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3052 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3053 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3054 pi.ipi_pidx = pidx; 3055 pi.ipi_qsidx = txq->ift_id; 3056 3057 /* deliberate bitwise OR to make one condition */ 3058 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3059 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3060 return (err); 3061 m_head = *m_headp; 3062 } 3063 3064 retry: 3065 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3066 defrag: 3067 if (__predict_false(err)) { 3068 switch (err) { 3069 case EFBIG: 3070 /* try collapse once and defrag once */ 3071 if (remap == 0) 3072 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3073 if (remap == 1) 3074 m_head = m_defrag(*m_headp, M_NOWAIT); 3075 remap++; 3076 if (__predict_false(m_head == NULL)) 3077 goto defrag_failed; 3078 txq->ift_mbuf_defrag++; 3079 *m_headp = m_head; 3080 goto retry; 3081 break; 3082 case ENOMEM: 3083 txq->ift_no_tx_dma_setup++; 3084 break; 3085 default: 3086 txq->ift_no_tx_dma_setup++; 3087 m_freem(*m_headp); 3088 DBG_COUNTER_INC(tx_frees); 3089 *m_headp = NULL; 3090 break; 3091 } 3092 txq->ift_map_failed++; 3093 DBG_COUNTER_INC(encap_load_mbuf_fail); 3094 return (err); 3095 } 3096 3097 /* 3098 * XXX assumes a 1 to 1 relationship between segments and 3099 * descriptors - this does not hold true on all drivers, e.g. 3100 * cxgb 3101 */ 3102 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3103 txq->ift_no_desc_avail++; 3104 if (map != NULL) 3105 bus_dmamap_unload(desc_tag, map); 3106 DBG_COUNTER_INC(encap_txq_avail_fail); 3107 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3108 GROUPTASK_ENQUEUE(&txq->ift_task); 3109 return (ENOBUFS); 3110 } 3111 /* 3112 * On Intel cards we can greatly reduce the number of TX interrupts 3113 * we see by only setting report status on every Nth descriptor. 3114 * However, this also means that the driver will need to keep track 3115 * of the descriptors that RS was set on to check them for the DD bit. 3116 */ 3117 txq->ift_rs_pending += nsegs + 1; 3118 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3119 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) { 3120 pi.ipi_flags |= IPI_TX_INTR; 3121 txq->ift_rs_pending = 0; 3122 } 3123 3124 pi.ipi_segs = segs; 3125 pi.ipi_nsegs = nsegs; 3126 3127 MPASS(pidx >= 0 && pidx < txq->ift_size); 3128 #ifdef PKT_DEBUG 3129 print_pkt(&pi); 3130 #endif 3131 if (map != NULL) 3132 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3133 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3134 if (map != NULL) 3135 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3136 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3137 DBG_COUNTER_INC(tx_encap); 3138 MPASS(pi.ipi_new_pidx < txq->ift_size); 3139 3140 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3141 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3142 ndesc += txq->ift_size; 3143 txq->ift_gen = 1; 3144 } 3145 /* 3146 * drivers can need as many as 3147 * two sentinels 3148 */ 3149 MPASS(ndesc <= pi.ipi_nsegs + 2); 3150 MPASS(pi.ipi_new_pidx != pidx); 3151 MPASS(ndesc > 0); 3152 txq->ift_in_use += ndesc; 3153 3154 /* 3155 * We update the last software descriptor again here because there may 3156 * be a sentinel and/or there may be more mbufs than segments 3157 */ 3158 txq->ift_pidx = pi.ipi_new_pidx; 3159 txq->ift_npending += pi.ipi_ndescs; 3160 } else if (__predict_false(err == EFBIG && remap < 2)) { 3161 *m_headp = m_head = iflib_remove_mbuf(txq); 3162 remap = 1; 3163 txq->ift_txd_encap_efbig++; 3164 goto defrag; 3165 } else 3166 DBG_COUNTER_INC(encap_txd_encap_fail); 3167 return (err); 3168 3169 defrag_failed: 3170 txq->ift_mbuf_defrag_failed++; 3171 txq->ift_map_failed++; 3172 m_freem(*m_headp); 3173 DBG_COUNTER_INC(tx_frees); 3174 *m_headp = NULL; 3175 return (ENOMEM); 3176 } 3177 3178 static void 3179 iflib_tx_desc_free(iflib_txq_t txq, int n) 3180 { 3181 int hasmap; 3182 uint32_t qsize, cidx, mask, gen; 3183 struct mbuf *m, **ifsd_m; 3184 uint8_t *ifsd_flags; 3185 bus_dmamap_t *ifsd_map; 3186 bool do_prefetch; 3187 3188 cidx = txq->ift_cidx; 3189 gen = txq->ift_gen; 3190 qsize = txq->ift_size; 3191 mask = qsize-1; 3192 hasmap = txq->ift_sds.ifsd_map != NULL; 3193 ifsd_flags = txq->ift_sds.ifsd_flags; 3194 ifsd_m = txq->ift_sds.ifsd_m; 3195 ifsd_map = txq->ift_sds.ifsd_map; 3196 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3197 3198 while (n--) { 3199 if (do_prefetch) { 3200 prefetch(ifsd_m[(cidx + 3) & mask]); 3201 prefetch(ifsd_m[(cidx + 4) & mask]); 3202 } 3203 if (ifsd_m[cidx] != NULL) { 3204 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3205 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3206 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3207 /* 3208 * does it matter if it's not the TSO tag? If so we'll 3209 * have to add the type to flags 3210 */ 3211 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3212 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3213 } 3214 if ((m = ifsd_m[cidx]) != NULL) { 3215 /* XXX we don't support any drivers that batch packets yet */ 3216 MPASS(m->m_nextpkt == NULL); 3217 3218 m_free(m); 3219 ifsd_m[cidx] = NULL; 3220 #if MEMORY_LOGGING 3221 txq->ift_dequeued++; 3222 #endif 3223 DBG_COUNTER_INC(tx_frees); 3224 } 3225 } 3226 if (__predict_false(++cidx == qsize)) { 3227 cidx = 0; 3228 gen = 0; 3229 } 3230 } 3231 txq->ift_cidx = cidx; 3232 txq->ift_gen = gen; 3233 } 3234 3235 static __inline int 3236 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3237 { 3238 int reclaim; 3239 if_ctx_t ctx = txq->ift_ctx; 3240 3241 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3242 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3243 3244 /* 3245 * Need a rate-limiting check so that this isn't called every time 3246 */ 3247 iflib_tx_credits_update(ctx, txq); 3248 reclaim = DESC_RECLAIMABLE(txq); 3249 3250 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3251 #ifdef INVARIANTS 3252 if (iflib_verbose_debug) { 3253 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3254 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3255 reclaim, thresh); 3256 3257 } 3258 #endif 3259 return (0); 3260 } 3261 iflib_tx_desc_free(txq, reclaim); 3262 txq->ift_cleaned += reclaim; 3263 txq->ift_in_use -= reclaim; 3264 3265 return (reclaim); 3266 } 3267 3268 static struct mbuf ** 3269 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3270 { 3271 int next, size; 3272 struct mbuf **items; 3273 3274 size = r->size; 3275 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3276 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3277 3278 prefetch(items[(cidx + offset) & (size-1)]); 3279 if (remaining > 1) { 3280 prefetch(&items[next]); 3281 prefetch(items[(cidx + offset + 1) & (size-1)]); 3282 prefetch(items[(cidx + offset + 2) & (size-1)]); 3283 prefetch(items[(cidx + offset + 3) & (size-1)]); 3284 } 3285 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3286 } 3287 3288 static void 3289 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3290 { 3291 3292 ifmp_ring_check_drainage(txq->ift_br, budget); 3293 } 3294 3295 static uint32_t 3296 iflib_txq_can_drain(struct ifmp_ring *r) 3297 { 3298 iflib_txq_t txq = r->cookie; 3299 if_ctx_t ctx = txq->ift_ctx; 3300 3301 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3302 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3303 } 3304 3305 static uint32_t 3306 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3307 { 3308 iflib_txq_t txq = r->cookie; 3309 if_ctx_t ctx = txq->ift_ctx; 3310 struct ifnet *ifp = ctx->ifc_ifp; 3311 struct mbuf **mp, *m; 3312 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3313 int reclaimed, err, in_use_prev, desc_used; 3314 bool do_prefetch, ring, rang; 3315 3316 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3317 !LINK_ACTIVE(ctx))) { 3318 DBG_COUNTER_INC(txq_drain_notready); 3319 return (0); 3320 } 3321 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3322 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3323 avail = IDXDIFF(pidx, cidx, r->size); 3324 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3325 DBG_COUNTER_INC(txq_drain_flushing); 3326 for (i = 0; i < avail; i++) { 3327 m_free(r->items[(cidx + i) & (r->size-1)]); 3328 r->items[(cidx + i) & (r->size-1)] = NULL; 3329 } 3330 return (avail); 3331 } 3332 3333 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3334 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3335 CALLOUT_LOCK(txq); 3336 callout_stop(&txq->ift_timer); 3337 CALLOUT_UNLOCK(txq); 3338 DBG_COUNTER_INC(txq_drain_oactive); 3339 return (0); 3340 } 3341 if (reclaimed) 3342 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3343 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3344 count = MIN(avail, TX_BATCH_SIZE); 3345 #ifdef INVARIANTS 3346 if (iflib_verbose_debug) 3347 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3348 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3349 #endif 3350 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3351 avail = TXQ_AVAIL(txq); 3352 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3353 int pidx_prev, rem = do_prefetch ? count - i : 0; 3354 3355 mp = _ring_peek_one(r, cidx, i, rem); 3356 MPASS(mp != NULL && *mp != NULL); 3357 if (__predict_false(*mp == (struct mbuf *)txq)) { 3358 consumed++; 3359 reclaimed++; 3360 continue; 3361 } 3362 in_use_prev = txq->ift_in_use; 3363 pidx_prev = txq->ift_pidx; 3364 err = iflib_encap(txq, mp); 3365 if (__predict_false(err)) { 3366 DBG_COUNTER_INC(txq_drain_encapfail); 3367 /* no room - bail out */ 3368 if (err == ENOBUFS) 3369 break; 3370 consumed++; 3371 DBG_COUNTER_INC(txq_drain_encapfail); 3372 /* we can't send this packet - skip it */ 3373 continue; 3374 } 3375 consumed++; 3376 pkt_sent++; 3377 m = *mp; 3378 DBG_COUNTER_INC(tx_sent); 3379 bytes_sent += m->m_pkthdr.len; 3380 mcast_sent += !!(m->m_flags & M_MCAST); 3381 avail = TXQ_AVAIL(txq); 3382 3383 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3384 desc_used += (txq->ift_in_use - in_use_prev); 3385 ETHER_BPF_MTAP(ifp, m); 3386 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3387 break; 3388 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3389 } 3390 3391 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3392 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3393 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3394 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3395 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3396 if (mcast_sent) 3397 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3398 #ifdef INVARIANTS 3399 if (iflib_verbose_debug) 3400 printf("consumed=%d\n", consumed); 3401 #endif 3402 return (consumed); 3403 } 3404 3405 static uint32_t 3406 iflib_txq_drain_always(struct ifmp_ring *r) 3407 { 3408 return (1); 3409 } 3410 3411 static uint32_t 3412 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3413 { 3414 int i, avail; 3415 struct mbuf **mp; 3416 iflib_txq_t txq; 3417 3418 txq = r->cookie; 3419 3420 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3421 CALLOUT_LOCK(txq); 3422 callout_stop(&txq->ift_timer); 3423 CALLOUT_UNLOCK(txq); 3424 3425 avail = IDXDIFF(pidx, cidx, r->size); 3426 for (i = 0; i < avail; i++) { 3427 mp = _ring_peek_one(r, cidx, i, avail - i); 3428 if (__predict_false(*mp == (struct mbuf *)txq)) 3429 continue; 3430 m_freem(*mp); 3431 } 3432 MPASS(ifmp_ring_is_stalled(r) == 0); 3433 return (avail); 3434 } 3435 3436 static void 3437 iflib_ifmp_purge(iflib_txq_t txq) 3438 { 3439 struct ifmp_ring *r; 3440 3441 r = txq->ift_br; 3442 r->drain = iflib_txq_drain_free; 3443 r->can_drain = iflib_txq_drain_always; 3444 3445 ifmp_ring_check_drainage(r, r->size); 3446 3447 r->drain = iflib_txq_drain; 3448 r->can_drain = iflib_txq_can_drain; 3449 } 3450 3451 static void 3452 _task_fn_tx(void *context) 3453 { 3454 iflib_txq_t txq = context; 3455 if_ctx_t ctx = txq->ift_ctx; 3456 struct ifnet *ifp = ctx->ifc_ifp; 3457 int rc; 3458 3459 #ifdef IFLIB_DIAGNOSTICS 3460 txq->ift_cpu_exec_count[curcpu]++; 3461 #endif 3462 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3463 return; 3464 if ((ifp->if_capenable & IFCAP_NETMAP)) { 3465 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3466 netmap_tx_irq(ifp, txq->ift_id); 3467 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3468 return; 3469 } 3470 if (txq->ift_db_pending) 3471 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); 3472 else 3473 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3474 if (ctx->ifc_flags & IFC_LEGACY) 3475 IFDI_INTR_ENABLE(ctx); 3476 else { 3477 rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3478 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3479 } 3480 } 3481 3482 static void 3483 _task_fn_rx(void *context) 3484 { 3485 iflib_rxq_t rxq = context; 3486 if_ctx_t ctx = rxq->ifr_ctx; 3487 bool more; 3488 int rc; 3489 3490 #ifdef IFLIB_DIAGNOSTICS 3491 rxq->ifr_cpu_exec_count[curcpu]++; 3492 #endif 3493 DBG_COUNTER_INC(task_fn_rxs); 3494 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3495 return; 3496 if ((more = iflib_rxeof(rxq, 16 /* XXX */)) == false) { 3497 if (ctx->ifc_flags & IFC_LEGACY) 3498 IFDI_INTR_ENABLE(ctx); 3499 else { 3500 DBG_COUNTER_INC(rx_intr_enables); 3501 rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3502 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3503 } 3504 } 3505 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3506 return; 3507 if (more) 3508 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3509 } 3510 3511 static void 3512 _task_fn_admin(void *context) 3513 { 3514 if_ctx_t ctx = context; 3515 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3516 iflib_txq_t txq; 3517 int i; 3518 3519 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3520 return; 3521 3522 CTX_LOCK(ctx); 3523 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3524 CALLOUT_LOCK(txq); 3525 callout_stop(&txq->ift_timer); 3526 CALLOUT_UNLOCK(txq); 3527 } 3528 IFDI_UPDATE_ADMIN_STATUS(ctx); 3529 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3530 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 3531 IFDI_LINK_INTR_ENABLE(ctx); 3532 if (ctx->ifc_flags & IFC_DO_RESET) { 3533 ctx->ifc_flags &= ~IFC_DO_RESET; 3534 iflib_if_init_locked(ctx); 3535 } 3536 CTX_UNLOCK(ctx); 3537 3538 if (LINK_ACTIVE(ctx) == 0) 3539 return; 3540 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3541 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3542 } 3543 3544 3545 static void 3546 _task_fn_iov(void *context) 3547 { 3548 if_ctx_t ctx = context; 3549 3550 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3551 return; 3552 3553 CTX_LOCK(ctx); 3554 IFDI_VFLR_HANDLE(ctx); 3555 CTX_UNLOCK(ctx); 3556 } 3557 3558 static int 3559 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3560 { 3561 int err; 3562 if_int_delay_info_t info; 3563 if_ctx_t ctx; 3564 3565 info = (if_int_delay_info_t)arg1; 3566 ctx = info->iidi_ctx; 3567 info->iidi_req = req; 3568 info->iidi_oidp = oidp; 3569 CTX_LOCK(ctx); 3570 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3571 CTX_UNLOCK(ctx); 3572 return (err); 3573 } 3574 3575 /********************************************************************* 3576 * 3577 * IFNET FUNCTIONS 3578 * 3579 **********************************************************************/ 3580 3581 static void 3582 iflib_if_init_locked(if_ctx_t ctx) 3583 { 3584 iflib_stop(ctx); 3585 iflib_init_locked(ctx); 3586 } 3587 3588 3589 static void 3590 iflib_if_init(void *arg) 3591 { 3592 if_ctx_t ctx = arg; 3593 3594 CTX_LOCK(ctx); 3595 iflib_if_init_locked(ctx); 3596 CTX_UNLOCK(ctx); 3597 } 3598 3599 static int 3600 iflib_if_transmit(if_t ifp, struct mbuf *m) 3601 { 3602 if_ctx_t ctx = if_getsoftc(ifp); 3603 3604 iflib_txq_t txq; 3605 int err, qidx; 3606 3607 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3608 DBG_COUNTER_INC(tx_frees); 3609 m_freem(m); 3610 return (ENOBUFS); 3611 } 3612 3613 MPASS(m->m_nextpkt == NULL); 3614 qidx = 0; 3615 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3616 qidx = QIDX(ctx, m); 3617 /* 3618 * XXX calculate buf_ring based on flowid (divvy up bits?) 3619 */ 3620 txq = &ctx->ifc_txqs[qidx]; 3621 3622 #ifdef DRIVER_BACKPRESSURE 3623 if (txq->ift_closed) { 3624 while (m != NULL) { 3625 next = m->m_nextpkt; 3626 m->m_nextpkt = NULL; 3627 m_freem(m); 3628 m = next; 3629 } 3630 return (ENOBUFS); 3631 } 3632 #endif 3633 #ifdef notyet 3634 qidx = count = 0; 3635 mp = marr; 3636 next = m; 3637 do { 3638 count++; 3639 next = next->m_nextpkt; 3640 } while (next != NULL); 3641 3642 if (count > nitems(marr)) 3643 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3644 /* XXX check nextpkt */ 3645 m_freem(m); 3646 /* XXX simplify for now */ 3647 DBG_COUNTER_INC(tx_frees); 3648 return (ENOBUFS); 3649 } 3650 for (next = m, i = 0; next != NULL; i++) { 3651 mp[i] = next; 3652 next = next->m_nextpkt; 3653 mp[i]->m_nextpkt = NULL; 3654 } 3655 #endif 3656 DBG_COUNTER_INC(tx_seen); 3657 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); 3658 3659 if (err) { 3660 GROUPTASK_ENQUEUE(&txq->ift_task); 3661 /* support forthcoming later */ 3662 #ifdef DRIVER_BACKPRESSURE 3663 txq->ift_closed = TRUE; 3664 #endif 3665 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3666 m_freem(m); 3667 } else if (TXQ_AVAIL(txq) < (txq->ift_size >> 1)) { 3668 GROUPTASK_ENQUEUE(&txq->ift_task); 3669 } 3670 3671 return (err); 3672 } 3673 3674 static void 3675 iflib_if_qflush(if_t ifp) 3676 { 3677 if_ctx_t ctx = if_getsoftc(ifp); 3678 iflib_txq_t txq = ctx->ifc_txqs; 3679 int i; 3680 3681 CTX_LOCK(ctx); 3682 ctx->ifc_flags |= IFC_QFLUSH; 3683 CTX_UNLOCK(ctx); 3684 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3685 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3686 iflib_txq_check_drain(txq, 0); 3687 CTX_LOCK(ctx); 3688 ctx->ifc_flags &= ~IFC_QFLUSH; 3689 CTX_UNLOCK(ctx); 3690 3691 if_qflush(ifp); 3692 } 3693 3694 3695 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3696 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | \ 3697 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 3698 3699 static int 3700 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 3701 { 3702 if_ctx_t ctx = if_getsoftc(ifp); 3703 struct ifreq *ifr = (struct ifreq *)data; 3704 #if defined(INET) || defined(INET6) 3705 struct ifaddr *ifa = (struct ifaddr *)data; 3706 #endif 3707 bool avoid_reset = FALSE; 3708 int err = 0, reinit = 0, bits; 3709 3710 switch (command) { 3711 case SIOCSIFADDR: 3712 #ifdef INET 3713 if (ifa->ifa_addr->sa_family == AF_INET) 3714 avoid_reset = TRUE; 3715 #endif 3716 #ifdef INET6 3717 if (ifa->ifa_addr->sa_family == AF_INET6) 3718 avoid_reset = TRUE; 3719 #endif 3720 /* 3721 ** Calling init results in link renegotiation, 3722 ** so we avoid doing it when possible. 3723 */ 3724 if (avoid_reset) { 3725 if_setflagbits(ifp, IFF_UP,0); 3726 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING)) 3727 reinit = 1; 3728 #ifdef INET 3729 if (!(if_getflags(ifp) & IFF_NOARP)) 3730 arp_ifinit(ifp, ifa); 3731 #endif 3732 } else 3733 err = ether_ioctl(ifp, command, data); 3734 break; 3735 case SIOCSIFMTU: 3736 CTX_LOCK(ctx); 3737 if (ifr->ifr_mtu == if_getmtu(ifp)) { 3738 CTX_UNLOCK(ctx); 3739 break; 3740 } 3741 bits = if_getdrvflags(ifp); 3742 /* stop the driver and free any clusters before proceeding */ 3743 iflib_stop(ctx); 3744 3745 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 3746 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 3747 ctx->ifc_flags |= IFC_MULTISEG; 3748 else 3749 ctx->ifc_flags &= ~IFC_MULTISEG; 3750 err = if_setmtu(ifp, ifr->ifr_mtu); 3751 } 3752 iflib_init_locked(ctx); 3753 if_setdrvflags(ifp, bits); 3754 CTX_UNLOCK(ctx); 3755 break; 3756 case SIOCSIFFLAGS: 3757 CTX_LOCK(ctx); 3758 if (if_getflags(ifp) & IFF_UP) { 3759 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3760 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 3761 (IFF_PROMISC | IFF_ALLMULTI)) { 3762 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 3763 } 3764 } else 3765 reinit = 1; 3766 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3767 iflib_stop(ctx); 3768 } 3769 ctx->ifc_if_flags = if_getflags(ifp); 3770 CTX_UNLOCK(ctx); 3771 break; 3772 case SIOCADDMULTI: 3773 case SIOCDELMULTI: 3774 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3775 CTX_LOCK(ctx); 3776 IFDI_INTR_DISABLE(ctx); 3777 IFDI_MULTI_SET(ctx); 3778 IFDI_INTR_ENABLE(ctx); 3779 CTX_UNLOCK(ctx); 3780 } 3781 break; 3782 case SIOCSIFMEDIA: 3783 CTX_LOCK(ctx); 3784 IFDI_MEDIA_SET(ctx); 3785 CTX_UNLOCK(ctx); 3786 /* falls thru */ 3787 case SIOCGIFMEDIA: 3788 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 3789 break; 3790 case SIOCGI2C: 3791 { 3792 struct ifi2creq i2c; 3793 3794 err = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); 3795 if (err != 0) 3796 break; 3797 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 3798 err = EINVAL; 3799 break; 3800 } 3801 if (i2c.len > sizeof(i2c.data)) { 3802 err = EINVAL; 3803 break; 3804 } 3805 3806 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 3807 err = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); 3808 break; 3809 } 3810 case SIOCSIFCAP: 3811 { 3812 int mask, setmask; 3813 3814 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3815 setmask = 0; 3816 #ifdef TCP_OFFLOAD 3817 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 3818 #endif 3819 setmask |= (mask & IFCAP_FLAGS); 3820 3821 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 3822 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 3823 if ((mask & IFCAP_WOL) && 3824 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 3825 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 3826 if_vlancap(ifp); 3827 /* 3828 * want to ensure that traffic has stopped before we change any of the flags 3829 */ 3830 if (setmask) { 3831 CTX_LOCK(ctx); 3832 bits = if_getdrvflags(ifp); 3833 if (bits & IFF_DRV_RUNNING) 3834 iflib_stop(ctx); 3835 if_togglecapenable(ifp, setmask); 3836 if (bits & IFF_DRV_RUNNING) 3837 iflib_init_locked(ctx); 3838 if_setdrvflags(ifp, bits); 3839 CTX_UNLOCK(ctx); 3840 } 3841 break; 3842 } 3843 case SIOCGPRIVATE_0: 3844 case SIOCSDRVSPEC: 3845 case SIOCGDRVSPEC: 3846 CTX_LOCK(ctx); 3847 err = IFDI_PRIV_IOCTL(ctx, command, data); 3848 CTX_UNLOCK(ctx); 3849 break; 3850 default: 3851 err = ether_ioctl(ifp, command, data); 3852 break; 3853 } 3854 if (reinit) 3855 iflib_if_init(ctx); 3856 return (err); 3857 } 3858 3859 static uint64_t 3860 iflib_if_get_counter(if_t ifp, ift_counter cnt) 3861 { 3862 if_ctx_t ctx = if_getsoftc(ifp); 3863 3864 return (IFDI_GET_COUNTER(ctx, cnt)); 3865 } 3866 3867 /********************************************************************* 3868 * 3869 * OTHER FUNCTIONS EXPORTED TO THE STACK 3870 * 3871 **********************************************************************/ 3872 3873 static void 3874 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 3875 { 3876 if_ctx_t ctx = if_getsoftc(ifp); 3877 3878 if ((void *)ctx != arg) 3879 return; 3880 3881 if ((vtag == 0) || (vtag > 4095)) 3882 return; 3883 3884 CTX_LOCK(ctx); 3885 IFDI_VLAN_REGISTER(ctx, vtag); 3886 /* Re-init to load the changes */ 3887 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 3888 iflib_init_locked(ctx); 3889 CTX_UNLOCK(ctx); 3890 } 3891 3892 static void 3893 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 3894 { 3895 if_ctx_t ctx = if_getsoftc(ifp); 3896 3897 if ((void *)ctx != arg) 3898 return; 3899 3900 if ((vtag == 0) || (vtag > 4095)) 3901 return; 3902 3903 CTX_LOCK(ctx); 3904 IFDI_VLAN_UNREGISTER(ctx, vtag); 3905 /* Re-init to load the changes */ 3906 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 3907 iflib_init_locked(ctx); 3908 CTX_UNLOCK(ctx); 3909 } 3910 3911 static void 3912 iflib_led_func(void *arg, int onoff) 3913 { 3914 if_ctx_t ctx = arg; 3915 3916 CTX_LOCK(ctx); 3917 IFDI_LED_FUNC(ctx, onoff); 3918 CTX_UNLOCK(ctx); 3919 } 3920 3921 /********************************************************************* 3922 * 3923 * BUS FUNCTION DEFINITIONS 3924 * 3925 **********************************************************************/ 3926 3927 int 3928 iflib_device_probe(device_t dev) 3929 { 3930 pci_vendor_info_t *ent; 3931 3932 uint16_t pci_vendor_id, pci_device_id; 3933 uint16_t pci_subvendor_id, pci_subdevice_id; 3934 uint16_t pci_rev_id; 3935 if_shared_ctx_t sctx; 3936 3937 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 3938 return (ENOTSUP); 3939 3940 pci_vendor_id = pci_get_vendor(dev); 3941 pci_device_id = pci_get_device(dev); 3942 pci_subvendor_id = pci_get_subvendor(dev); 3943 pci_subdevice_id = pci_get_subdevice(dev); 3944 pci_rev_id = pci_get_revid(dev); 3945 if (sctx->isc_parse_devinfo != NULL) 3946 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 3947 3948 ent = sctx->isc_vendor_info; 3949 while (ent->pvi_vendor_id != 0) { 3950 if (pci_vendor_id != ent->pvi_vendor_id) { 3951 ent++; 3952 continue; 3953 } 3954 if ((pci_device_id == ent->pvi_device_id) && 3955 ((pci_subvendor_id == ent->pvi_subvendor_id) || 3956 (ent->pvi_subvendor_id == 0)) && 3957 ((pci_subdevice_id == ent->pvi_subdevice_id) || 3958 (ent->pvi_subdevice_id == 0)) && 3959 ((pci_rev_id == ent->pvi_rev_id) || 3960 (ent->pvi_rev_id == 0))) { 3961 3962 device_set_desc_copy(dev, ent->pvi_name); 3963 /* this needs to be changed to zero if the bus probing code 3964 * ever stops re-probing on best match because the sctx 3965 * may have its values over written by register calls 3966 * in subsequent probes 3967 */ 3968 return (BUS_PROBE_DEFAULT); 3969 } 3970 ent++; 3971 } 3972 return (ENXIO); 3973 } 3974 3975 int 3976 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 3977 { 3978 int err, rid, msix, msix_bar; 3979 if_ctx_t ctx; 3980 if_t ifp; 3981 if_softc_ctx_t scctx; 3982 int i; 3983 uint16_t main_txq; 3984 uint16_t main_rxq; 3985 3986 3987 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 3988 3989 if (sc == NULL) { 3990 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 3991 device_set_softc(dev, ctx); 3992 ctx->ifc_flags |= IFC_SC_ALLOCATED; 3993 } 3994 3995 ctx->ifc_sctx = sctx; 3996 ctx->ifc_dev = dev; 3997 ctx->ifc_softc = sc; 3998 3999 if ((err = iflib_register(ctx)) != 0) { 4000 device_printf(dev, "iflib_register failed %d\n", err); 4001 return (err); 4002 } 4003 iflib_add_device_sysctl_pre(ctx); 4004 4005 scctx = &ctx->ifc_softc_ctx; 4006 ifp = ctx->ifc_ifp; 4007 4008 /* 4009 * XXX sanity check that ntxd & nrxd are a power of 2 4010 */ 4011 if (ctx->ifc_sysctl_ntxqs != 0) 4012 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4013 if (ctx->ifc_sysctl_nrxqs != 0) 4014 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4015 4016 for (i = 0; i < sctx->isc_ntxqs; i++) { 4017 if (ctx->ifc_sysctl_ntxds[i] != 0) 4018 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4019 else 4020 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4021 } 4022 4023 for (i = 0; i < sctx->isc_nrxqs; i++) { 4024 if (ctx->ifc_sysctl_nrxds[i] != 0) 4025 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4026 else 4027 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4028 } 4029 4030 for (i = 0; i < sctx->isc_nrxqs; i++) { 4031 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4032 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4033 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4034 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4035 } 4036 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4037 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4038 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4039 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4040 } 4041 } 4042 4043 for (i = 0; i < sctx->isc_ntxqs; i++) { 4044 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4045 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4046 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4047 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4048 } 4049 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4050 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4051 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4052 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4053 } 4054 } 4055 4056 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4057 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4058 return (err); 4059 } 4060 _iflib_pre_assert(scctx); 4061 ctx->ifc_txrx = *scctx->isc_txrx; 4062 4063 #ifdef INVARIANTS 4064 MPASS(scctx->isc_capenable); 4065 if (scctx->isc_capenable & IFCAP_TXCSUM) 4066 MPASS(scctx->isc_tx_csum_flags); 4067 #endif 4068 4069 if_setcapabilities(ifp, scctx->isc_capenable); 4070 if_setcapenable(ifp, scctx->isc_capenable); 4071 4072 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4073 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4074 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4075 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4076 4077 #ifdef ACPI_DMAR 4078 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4079 ctx->ifc_flags |= IFC_DMAR; 4080 #elif !(defined(__i386__) || defined(__amd64__)) 4081 /* set unconditionally for !x86 */ 4082 ctx->ifc_flags |= IFC_DMAR; 4083 #endif 4084 4085 msix_bar = scctx->isc_msix_bar; 4086 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4087 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4088 4089 /* XXX change for per-queue sizes */ 4090 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4091 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4092 for (i = 0; i < sctx->isc_nrxqs; i++) { 4093 if (!powerof2(scctx->isc_nrxd[i])) { 4094 /* round down instead? */ 4095 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4096 err = EINVAL; 4097 goto fail; 4098 } 4099 } 4100 for (i = 0; i < sctx->isc_ntxqs; i++) { 4101 if (!powerof2(scctx->isc_ntxd[i])) { 4102 device_printf(dev, 4103 "# tx descriptors must be a power of 2"); 4104 err = EINVAL; 4105 goto fail; 4106 } 4107 } 4108 4109 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4110 MAX_SINGLE_PACKET_FRACTION) 4111 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4112 MAX_SINGLE_PACKET_FRACTION); 4113 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4114 MAX_SINGLE_PACKET_FRACTION) 4115 scctx->isc_tx_tso_segments_max = max(1, 4116 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4117 4118 /* 4119 * Protect the stack against modern hardware 4120 */ 4121 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4122 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4123 4124 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4125 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4126 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4127 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4128 if (scctx->isc_rss_table_size == 0) 4129 scctx->isc_rss_table_size = 64; 4130 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4131 4132 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4133 /* XXX format name */ 4134 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4135 /* 4136 ** Now setup MSI or MSI/X, should 4137 ** return us the number of supported 4138 ** vectors. (Will be 1 for MSI) 4139 */ 4140 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4141 msix = scctx->isc_vectors; 4142 } else if (scctx->isc_msix_bar != 0) 4143 /* 4144 * The simple fact that isc_msix_bar is not 0 does not mean we 4145 * we have a good value there that is known to work. 4146 */ 4147 msix = iflib_msix_init(ctx); 4148 else { 4149 scctx->isc_vectors = 1; 4150 scctx->isc_ntxqsets = 1; 4151 scctx->isc_nrxqsets = 1; 4152 scctx->isc_intr = IFLIB_INTR_LEGACY; 4153 msix = 0; 4154 } 4155 /* Get memory for the station queues */ 4156 if ((err = iflib_queues_alloc(ctx))) { 4157 device_printf(dev, "Unable to allocate queue memory\n"); 4158 goto fail; 4159 } 4160 4161 if ((err = iflib_qset_structures_setup(ctx))) { 4162 device_printf(dev, "qset structure setup failed %d\n", err); 4163 goto fail_queues; 4164 } 4165 4166 /* 4167 * Group taskqueues aren't properly set up until SMP is started, 4168 * so we disable interrupts until we can handle them post 4169 * SI_SUB_SMP. 4170 * 4171 * XXX: disabling interrupts doesn't actually work, at least for 4172 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4173 * we do null handling and depend on this not causing too large an 4174 * interrupt storm. 4175 */ 4176 IFDI_INTR_DISABLE(ctx); 4177 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4178 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4179 goto fail_intr_free; 4180 } 4181 if (msix <= 1) { 4182 rid = 0; 4183 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4184 MPASS(msix == 1); 4185 rid = 1; 4186 } 4187 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4188 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4189 goto fail_intr_free; 4190 } 4191 } 4192 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4193 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4194 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4195 goto fail_detach; 4196 } 4197 if ((err = iflib_netmap_attach(ctx))) { 4198 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4199 goto fail_detach; 4200 } 4201 *ctxp = ctx; 4202 4203 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4204 iflib_add_device_sysctl_post(ctx); 4205 ctx->ifc_flags |= IFC_INIT_DONE; 4206 return (0); 4207 fail_detach: 4208 ether_ifdetach(ctx->ifc_ifp); 4209 fail_intr_free: 4210 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4211 pci_release_msi(ctx->ifc_dev); 4212 fail_queues: 4213 /* XXX free queues */ 4214 fail: 4215 IFDI_DETACH(ctx); 4216 return (err); 4217 } 4218 4219 int 4220 iflib_device_attach(device_t dev) 4221 { 4222 if_ctx_t ctx; 4223 if_shared_ctx_t sctx; 4224 4225 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4226 return (ENOTSUP); 4227 4228 pci_enable_busmaster(dev); 4229 4230 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4231 } 4232 4233 int 4234 iflib_device_deregister(if_ctx_t ctx) 4235 { 4236 if_t ifp = ctx->ifc_ifp; 4237 iflib_txq_t txq; 4238 iflib_rxq_t rxq; 4239 device_t dev = ctx->ifc_dev; 4240 int i; 4241 struct taskqgroup *tqg; 4242 4243 /* Make sure VLANS are not using driver */ 4244 if (if_vlantrunkinuse(ifp)) { 4245 device_printf(dev,"Vlan in use, detach first\n"); 4246 return (EBUSY); 4247 } 4248 4249 CTX_LOCK(ctx); 4250 ctx->ifc_in_detach = 1; 4251 iflib_stop(ctx); 4252 CTX_UNLOCK(ctx); 4253 4254 /* Unregister VLAN events */ 4255 if (ctx->ifc_vlan_attach_event != NULL) 4256 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4257 if (ctx->ifc_vlan_detach_event != NULL) 4258 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4259 4260 iflib_netmap_detach(ifp); 4261 ether_ifdetach(ifp); 4262 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4263 CTX_LOCK_DESTROY(ctx); 4264 if (ctx->ifc_led_dev != NULL) 4265 led_destroy(ctx->ifc_led_dev); 4266 /* XXX drain any dependent tasks */ 4267 tqg = qgroup_if_io_tqg; 4268 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4269 callout_drain(&txq->ift_timer); 4270 if (txq->ift_task.gt_uniq != NULL) 4271 taskqgroup_detach(tqg, &txq->ift_task); 4272 } 4273 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4274 if (rxq->ifr_task.gt_uniq != NULL) 4275 taskqgroup_detach(tqg, &rxq->ifr_task); 4276 } 4277 tqg = qgroup_if_config_tqg; 4278 if (ctx->ifc_admin_task.gt_uniq != NULL) 4279 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4280 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4281 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4282 4283 IFDI_DETACH(ctx); 4284 device_set_softc(ctx->ifc_dev, NULL); 4285 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4286 pci_release_msi(dev); 4287 } 4288 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4289 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4290 } 4291 if (ctx->ifc_msix_mem != NULL) { 4292 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4293 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4294 ctx->ifc_msix_mem = NULL; 4295 } 4296 4297 bus_generic_detach(dev); 4298 if_free(ifp); 4299 4300 iflib_tx_structures_free(ctx); 4301 iflib_rx_structures_free(ctx); 4302 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4303 free(ctx->ifc_softc, M_IFLIB); 4304 free(ctx, M_IFLIB); 4305 return (0); 4306 } 4307 4308 4309 int 4310 iflib_device_detach(device_t dev) 4311 { 4312 if_ctx_t ctx = device_get_softc(dev); 4313 4314 return (iflib_device_deregister(ctx)); 4315 } 4316 4317 int 4318 iflib_device_suspend(device_t dev) 4319 { 4320 if_ctx_t ctx = device_get_softc(dev); 4321 4322 CTX_LOCK(ctx); 4323 IFDI_SUSPEND(ctx); 4324 CTX_UNLOCK(ctx); 4325 4326 return bus_generic_suspend(dev); 4327 } 4328 int 4329 iflib_device_shutdown(device_t dev) 4330 { 4331 if_ctx_t ctx = device_get_softc(dev); 4332 4333 CTX_LOCK(ctx); 4334 IFDI_SHUTDOWN(ctx); 4335 CTX_UNLOCK(ctx); 4336 4337 return bus_generic_suspend(dev); 4338 } 4339 4340 4341 int 4342 iflib_device_resume(device_t dev) 4343 { 4344 if_ctx_t ctx = device_get_softc(dev); 4345 iflib_txq_t txq = ctx->ifc_txqs; 4346 4347 CTX_LOCK(ctx); 4348 IFDI_RESUME(ctx); 4349 iflib_init_locked(ctx); 4350 CTX_UNLOCK(ctx); 4351 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4352 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4353 4354 return (bus_generic_resume(dev)); 4355 } 4356 4357 int 4358 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4359 { 4360 int error; 4361 if_ctx_t ctx = device_get_softc(dev); 4362 4363 CTX_LOCK(ctx); 4364 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4365 CTX_UNLOCK(ctx); 4366 4367 return (error); 4368 } 4369 4370 void 4371 iflib_device_iov_uninit(device_t dev) 4372 { 4373 if_ctx_t ctx = device_get_softc(dev); 4374 4375 CTX_LOCK(ctx); 4376 IFDI_IOV_UNINIT(ctx); 4377 CTX_UNLOCK(ctx); 4378 } 4379 4380 int 4381 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 4382 { 4383 int error; 4384 if_ctx_t ctx = device_get_softc(dev); 4385 4386 CTX_LOCK(ctx); 4387 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 4388 CTX_UNLOCK(ctx); 4389 4390 return (error); 4391 } 4392 4393 /********************************************************************* 4394 * 4395 * MODULE FUNCTION DEFINITIONS 4396 * 4397 **********************************************************************/ 4398 4399 /* 4400 * - Start a fast taskqueue thread for each core 4401 * - Start a taskqueue for control operations 4402 */ 4403 static int 4404 iflib_module_init(void) 4405 { 4406 return (0); 4407 } 4408 4409 static int 4410 iflib_module_event_handler(module_t mod, int what, void *arg) 4411 { 4412 int err; 4413 4414 switch (what) { 4415 case MOD_LOAD: 4416 if ((err = iflib_module_init()) != 0) 4417 return (err); 4418 break; 4419 case MOD_UNLOAD: 4420 return (EBUSY); 4421 default: 4422 return (EOPNOTSUPP); 4423 } 4424 4425 return (0); 4426 } 4427 4428 /********************************************************************* 4429 * 4430 * PUBLIC FUNCTION DEFINITIONS 4431 * ordered as in iflib.h 4432 * 4433 **********************************************************************/ 4434 4435 4436 static void 4437 _iflib_assert(if_shared_ctx_t sctx) 4438 { 4439 MPASS(sctx->isc_tx_maxsize); 4440 MPASS(sctx->isc_tx_maxsegsize); 4441 4442 MPASS(sctx->isc_rx_maxsize); 4443 MPASS(sctx->isc_rx_nsegments); 4444 MPASS(sctx->isc_rx_maxsegsize); 4445 4446 MPASS(sctx->isc_nrxd_min[0]); 4447 MPASS(sctx->isc_nrxd_max[0]); 4448 MPASS(sctx->isc_nrxd_default[0]); 4449 MPASS(sctx->isc_ntxd_min[0]); 4450 MPASS(sctx->isc_ntxd_max[0]); 4451 MPASS(sctx->isc_ntxd_default[0]); 4452 } 4453 4454 static void 4455 _iflib_pre_assert(if_softc_ctx_t scctx) 4456 { 4457 4458 MPASS(scctx->isc_txrx->ift_txd_encap); 4459 MPASS(scctx->isc_txrx->ift_txd_flush); 4460 MPASS(scctx->isc_txrx->ift_txd_credits_update); 4461 MPASS(scctx->isc_txrx->ift_rxd_available); 4462 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 4463 MPASS(scctx->isc_txrx->ift_rxd_refill); 4464 MPASS(scctx->isc_txrx->ift_rxd_flush); 4465 } 4466 4467 static int 4468 iflib_register(if_ctx_t ctx) 4469 { 4470 if_shared_ctx_t sctx = ctx->ifc_sctx; 4471 driver_t *driver = sctx->isc_driver; 4472 device_t dev = ctx->ifc_dev; 4473 if_t ifp; 4474 4475 _iflib_assert(sctx); 4476 4477 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 4478 4479 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 4480 if (ifp == NULL) { 4481 device_printf(dev, "can not allocate ifnet structure\n"); 4482 return (ENOMEM); 4483 } 4484 4485 /* 4486 * Initialize our context's device specific methods 4487 */ 4488 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 4489 kobj_class_compile((kobj_class_t) driver); 4490 driver->refs++; 4491 4492 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 4493 if_setsoftc(ifp, ctx); 4494 if_setdev(ifp, dev); 4495 if_setinitfn(ifp, iflib_if_init); 4496 if_setioctlfn(ifp, iflib_if_ioctl); 4497 if_settransmitfn(ifp, iflib_if_transmit); 4498 if_setqflushfn(ifp, iflib_if_qflush); 4499 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 4500 4501 ctx->ifc_vlan_attach_event = 4502 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 4503 EVENTHANDLER_PRI_FIRST); 4504 ctx->ifc_vlan_detach_event = 4505 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 4506 EVENTHANDLER_PRI_FIRST); 4507 4508 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 4509 iflib_media_change, iflib_media_status); 4510 4511 return (0); 4512 } 4513 4514 4515 static int 4516 iflib_queues_alloc(if_ctx_t ctx) 4517 { 4518 if_shared_ctx_t sctx = ctx->ifc_sctx; 4519 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4520 device_t dev = ctx->ifc_dev; 4521 int nrxqsets = scctx->isc_nrxqsets; 4522 int ntxqsets = scctx->isc_ntxqsets; 4523 iflib_txq_t txq; 4524 iflib_rxq_t rxq; 4525 iflib_fl_t fl = NULL; 4526 int i, j, cpu, err, txconf, rxconf; 4527 iflib_dma_info_t ifdip; 4528 uint32_t *rxqsizes = scctx->isc_rxqsizes; 4529 uint32_t *txqsizes = scctx->isc_txqsizes; 4530 uint8_t nrxqs = sctx->isc_nrxqs; 4531 uint8_t ntxqs = sctx->isc_ntxqs; 4532 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 4533 caddr_t *vaddrs; 4534 uint64_t *paddrs; 4535 struct ifmp_ring **brscp; 4536 4537 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 4538 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 4539 4540 brscp = NULL; 4541 txq = NULL; 4542 rxq = NULL; 4543 4544 /* Allocate the TX ring struct memory */ 4545 if (!(txq = 4546 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 4547 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4548 device_printf(dev, "Unable to allocate TX ring memory\n"); 4549 err = ENOMEM; 4550 goto fail; 4551 } 4552 4553 /* Now allocate the RX */ 4554 if (!(rxq = 4555 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 4556 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4557 device_printf(dev, "Unable to allocate RX ring memory\n"); 4558 err = ENOMEM; 4559 goto rx_fail; 4560 } 4561 4562 ctx->ifc_txqs = txq; 4563 ctx->ifc_rxqs = rxq; 4564 4565 /* 4566 * XXX handle allocation failure 4567 */ 4568 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 4569 /* Set up some basics */ 4570 4571 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4572 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4573 err = ENOMEM; 4574 goto err_tx_desc; 4575 } 4576 txq->ift_ifdi = ifdip; 4577 for (j = 0; j < ntxqs; j++, ifdip++) { 4578 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4579 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4580 err = ENOMEM; 4581 goto err_tx_desc; 4582 } 4583 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 4584 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 4585 } 4586 txq->ift_ctx = ctx; 4587 txq->ift_id = i; 4588 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 4589 txq->ift_br_offset = 1; 4590 } else { 4591 txq->ift_br_offset = 0; 4592 } 4593 /* XXX fix this */ 4594 txq->ift_timer.c_cpu = cpu; 4595 4596 if (iflib_txsd_alloc(txq)) { 4597 device_printf(dev, "Critical Failure setting up TX buffers\n"); 4598 err = ENOMEM; 4599 goto err_tx_desc; 4600 } 4601 4602 /* Initialize the TX lock */ 4603 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 4604 device_get_nameunit(dev), txq->ift_id); 4605 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 4606 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 4607 4608 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 4609 device_get_nameunit(dev), txq->ift_id); 4610 4611 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 4612 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 4613 if (err) { 4614 /* XXX free any allocated rings */ 4615 device_printf(dev, "Unable to allocate buf_ring\n"); 4616 goto err_tx_desc; 4617 } 4618 } 4619 4620 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 4621 /* Set up some basics */ 4622 4623 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4624 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4625 err = ENOMEM; 4626 goto err_tx_desc; 4627 } 4628 4629 rxq->ifr_ifdi = ifdip; 4630 /* XXX this needs to be changed if #rx queues != #tx queues */ 4631 rxq->ifr_ntxqirq = 1; 4632 rxq->ifr_txqid[0] = i; 4633 for (j = 0; j < nrxqs; j++, ifdip++) { 4634 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4635 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4636 err = ENOMEM; 4637 goto err_tx_desc; 4638 } 4639 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 4640 } 4641 rxq->ifr_ctx = ctx; 4642 rxq->ifr_id = i; 4643 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 4644 rxq->ifr_fl_offset = 1; 4645 } else { 4646 rxq->ifr_fl_offset = 0; 4647 } 4648 rxq->ifr_nfl = nfree_lists; 4649 if (!(fl = 4650 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 4651 device_printf(dev, "Unable to allocate free list memory\n"); 4652 err = ENOMEM; 4653 goto err_tx_desc; 4654 } 4655 rxq->ifr_fl = fl; 4656 for (j = 0; j < nfree_lists; j++) { 4657 fl[j].ifl_rxq = rxq; 4658 fl[j].ifl_id = j; 4659 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 4660 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 4661 } 4662 /* Allocate receive buffers for the ring*/ 4663 if (iflib_rxsd_alloc(rxq)) { 4664 device_printf(dev, 4665 "Critical Failure setting up receive buffers\n"); 4666 err = ENOMEM; 4667 goto err_rx_desc; 4668 } 4669 } 4670 4671 /* TXQs */ 4672 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4673 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4674 for (i = 0; i < ntxqsets; i++) { 4675 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 4676 4677 for (j = 0; j < ntxqs; j++, di++) { 4678 vaddrs[i*ntxqs + j] = di->idi_vaddr; 4679 paddrs[i*ntxqs + j] = di->idi_paddr; 4680 } 4681 } 4682 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 4683 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4684 iflib_tx_structures_free(ctx); 4685 free(vaddrs, M_IFLIB); 4686 free(paddrs, M_IFLIB); 4687 goto err_rx_desc; 4688 } 4689 free(vaddrs, M_IFLIB); 4690 free(paddrs, M_IFLIB); 4691 4692 /* RXQs */ 4693 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4694 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4695 for (i = 0; i < nrxqsets; i++) { 4696 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 4697 4698 for (j = 0; j < nrxqs; j++, di++) { 4699 vaddrs[i*nrxqs + j] = di->idi_vaddr; 4700 paddrs[i*nrxqs + j] = di->idi_paddr; 4701 } 4702 } 4703 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 4704 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4705 iflib_tx_structures_free(ctx); 4706 free(vaddrs, M_IFLIB); 4707 free(paddrs, M_IFLIB); 4708 goto err_rx_desc; 4709 } 4710 free(vaddrs, M_IFLIB); 4711 free(paddrs, M_IFLIB); 4712 4713 return (0); 4714 4715 /* XXX handle allocation failure changes */ 4716 err_rx_desc: 4717 err_tx_desc: 4718 if (ctx->ifc_rxqs != NULL) 4719 free(ctx->ifc_rxqs, M_IFLIB); 4720 ctx->ifc_rxqs = NULL; 4721 if (ctx->ifc_txqs != NULL) 4722 free(ctx->ifc_txqs, M_IFLIB); 4723 ctx->ifc_txqs = NULL; 4724 rx_fail: 4725 if (brscp != NULL) 4726 free(brscp, M_IFLIB); 4727 if (rxq != NULL) 4728 free(rxq, M_IFLIB); 4729 if (txq != NULL) 4730 free(txq, M_IFLIB); 4731 fail: 4732 return (err); 4733 } 4734 4735 static int 4736 iflib_tx_structures_setup(if_ctx_t ctx) 4737 { 4738 iflib_txq_t txq = ctx->ifc_txqs; 4739 int i; 4740 4741 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4742 iflib_txq_setup(txq); 4743 4744 return (0); 4745 } 4746 4747 static void 4748 iflib_tx_structures_free(if_ctx_t ctx) 4749 { 4750 iflib_txq_t txq = ctx->ifc_txqs; 4751 int i, j; 4752 4753 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 4754 iflib_txq_destroy(txq); 4755 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 4756 iflib_dma_free(&txq->ift_ifdi[j]); 4757 } 4758 free(ctx->ifc_txqs, M_IFLIB); 4759 ctx->ifc_txqs = NULL; 4760 IFDI_QUEUES_FREE(ctx); 4761 } 4762 4763 /********************************************************************* 4764 * 4765 * Initialize all receive rings. 4766 * 4767 **********************************************************************/ 4768 static int 4769 iflib_rx_structures_setup(if_ctx_t ctx) 4770 { 4771 iflib_rxq_t rxq = ctx->ifc_rxqs; 4772 int q; 4773 #if defined(INET6) || defined(INET) 4774 int i, err; 4775 #endif 4776 4777 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 4778 #if defined(INET6) || defined(INET) 4779 tcp_lro_free(&rxq->ifr_lc); 4780 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 4781 TCP_LRO_ENTRIES, min(1024, 4782 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 4783 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 4784 goto fail; 4785 } 4786 rxq->ifr_lro_enabled = TRUE; 4787 #endif 4788 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 4789 } 4790 return (0); 4791 #if defined(INET6) || defined(INET) 4792 fail: 4793 /* 4794 * Free RX software descriptors allocated so far, we will only handle 4795 * the rings that completed, the failing case will have 4796 * cleaned up for itself. 'q' failed, so its the terminus. 4797 */ 4798 rxq = ctx->ifc_rxqs; 4799 for (i = 0; i < q; ++i, rxq++) { 4800 iflib_rx_sds_free(rxq); 4801 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 4802 } 4803 return (err); 4804 #endif 4805 } 4806 4807 /********************************************************************* 4808 * 4809 * Free all receive rings. 4810 * 4811 **********************************************************************/ 4812 static void 4813 iflib_rx_structures_free(if_ctx_t ctx) 4814 { 4815 iflib_rxq_t rxq = ctx->ifc_rxqs; 4816 4817 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 4818 iflib_rx_sds_free(rxq); 4819 } 4820 } 4821 4822 static int 4823 iflib_qset_structures_setup(if_ctx_t ctx) 4824 { 4825 int err; 4826 4827 if ((err = iflib_tx_structures_setup(ctx)) != 0) 4828 return (err); 4829 4830 if ((err = iflib_rx_structures_setup(ctx)) != 0) { 4831 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 4832 iflib_tx_structures_free(ctx); 4833 iflib_rx_structures_free(ctx); 4834 } 4835 return (err); 4836 } 4837 4838 int 4839 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 4840 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name) 4841 { 4842 4843 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 4844 } 4845 4846 static int 4847 find_nth(if_ctx_t ctx, cpuset_t *cpus, int qid) 4848 { 4849 int i, cpuid, eqid, count; 4850 4851 CPU_COPY(&ctx->ifc_cpus, cpus); 4852 count = CPU_COUNT(&ctx->ifc_cpus); 4853 eqid = qid % count; 4854 /* clear up to the qid'th bit */ 4855 for (i = 0; i < eqid; i++) { 4856 cpuid = CPU_FFS(cpus); 4857 MPASS(cpuid != 0); 4858 CPU_CLR(cpuid-1, cpus); 4859 } 4860 cpuid = CPU_FFS(cpus); 4861 MPASS(cpuid != 0); 4862 return (cpuid-1); 4863 } 4864 4865 int 4866 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 4867 iflib_intr_type_t type, driver_filter_t *filter, 4868 void *filter_arg, int qid, char *name) 4869 { 4870 struct grouptask *gtask; 4871 struct taskqgroup *tqg; 4872 iflib_filter_info_t info; 4873 cpuset_t cpus; 4874 gtask_fn_t *fn; 4875 int tqrid, err, cpuid; 4876 driver_filter_t *intr_fast; 4877 void *q; 4878 4879 info = &ctx->ifc_filter_info; 4880 tqrid = rid; 4881 4882 switch (type) { 4883 /* XXX merge tx/rx for netmap? */ 4884 case IFLIB_INTR_TX: 4885 q = &ctx->ifc_txqs[qid]; 4886 info = &ctx->ifc_txqs[qid].ift_filter_info; 4887 gtask = &ctx->ifc_txqs[qid].ift_task; 4888 tqg = qgroup_if_io_tqg; 4889 fn = _task_fn_tx; 4890 intr_fast = iflib_fast_intr; 4891 GROUPTASK_INIT(gtask, 0, fn, q); 4892 break; 4893 case IFLIB_INTR_RX: 4894 q = &ctx->ifc_rxqs[qid]; 4895 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 4896 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4897 tqg = qgroup_if_io_tqg; 4898 fn = _task_fn_rx; 4899 intr_fast = iflib_fast_intr; 4900 GROUPTASK_INIT(gtask, 0, fn, q); 4901 break; 4902 case IFLIB_INTR_RXTX: 4903 q = &ctx->ifc_rxqs[qid]; 4904 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 4905 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4906 tqg = qgroup_if_io_tqg; 4907 fn = _task_fn_rx; 4908 intr_fast = iflib_fast_intr_rxtx; 4909 GROUPTASK_INIT(gtask, 0, fn, q); 4910 break; 4911 case IFLIB_INTR_ADMIN: 4912 q = ctx; 4913 tqrid = -1; 4914 info = &ctx->ifc_filter_info; 4915 gtask = &ctx->ifc_admin_task; 4916 tqg = qgroup_if_config_tqg; 4917 fn = _task_fn_admin; 4918 intr_fast = iflib_fast_intr_ctx; 4919 break; 4920 default: 4921 panic("unknown net intr type"); 4922 } 4923 4924 info->ifi_filter = filter; 4925 info->ifi_filter_arg = filter_arg; 4926 info->ifi_task = gtask; 4927 info->ifi_ctx = q; 4928 4929 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 4930 if (err != 0) { 4931 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 4932 return (err); 4933 } 4934 if (type == IFLIB_INTR_ADMIN) 4935 return (0); 4936 4937 if (tqrid != -1) { 4938 cpuid = find_nth(ctx, &cpus, qid); 4939 taskqgroup_attach_cpu(tqg, gtask, q, cpuid, irq->ii_rid, name); 4940 } else { 4941 taskqgroup_attach(tqg, gtask, q, tqrid, name); 4942 } 4943 4944 return (0); 4945 } 4946 4947 void 4948 iflib_softirq_alloc_generic(if_ctx_t ctx, int rid, iflib_intr_type_t type, void *arg, int qid, char *name) 4949 { 4950 struct grouptask *gtask; 4951 struct taskqgroup *tqg; 4952 gtask_fn_t *fn; 4953 void *q; 4954 4955 switch (type) { 4956 case IFLIB_INTR_TX: 4957 q = &ctx->ifc_txqs[qid]; 4958 gtask = &ctx->ifc_txqs[qid].ift_task; 4959 tqg = qgroup_if_io_tqg; 4960 fn = _task_fn_tx; 4961 break; 4962 case IFLIB_INTR_RX: 4963 q = &ctx->ifc_rxqs[qid]; 4964 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4965 tqg = qgroup_if_io_tqg; 4966 fn = _task_fn_rx; 4967 break; 4968 case IFLIB_INTR_IOV: 4969 q = ctx; 4970 gtask = &ctx->ifc_vflr_task; 4971 tqg = qgroup_if_config_tqg; 4972 rid = -1; 4973 fn = _task_fn_iov; 4974 break; 4975 default: 4976 panic("unknown net intr type"); 4977 } 4978 GROUPTASK_INIT(gtask, 0, fn, q); 4979 taskqgroup_attach(tqg, gtask, q, rid, name); 4980 } 4981 4982 void 4983 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 4984 { 4985 if (irq->ii_tag) 4986 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 4987 4988 if (irq->ii_res) 4989 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 4990 } 4991 4992 static int 4993 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name) 4994 { 4995 iflib_txq_t txq = ctx->ifc_txqs; 4996 iflib_rxq_t rxq = ctx->ifc_rxqs; 4997 if_irq_t irq = &ctx->ifc_legacy_irq; 4998 iflib_filter_info_t info; 4999 struct grouptask *gtask; 5000 struct taskqgroup *tqg; 5001 gtask_fn_t *fn; 5002 int tqrid; 5003 void *q; 5004 int err; 5005 5006 q = &ctx->ifc_rxqs[0]; 5007 info = &rxq[0].ifr_filter_info; 5008 gtask = &rxq[0].ifr_task; 5009 tqg = qgroup_if_io_tqg; 5010 tqrid = irq->ii_rid = *rid; 5011 fn = _task_fn_rx; 5012 5013 ctx->ifc_flags |= IFC_LEGACY; 5014 info->ifi_filter = filter; 5015 info->ifi_filter_arg = filter_arg; 5016 info->ifi_task = gtask; 5017 info->ifi_ctx = ctx; 5018 5019 /* We allocate a single interrupt resource */ 5020 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5021 return (err); 5022 GROUPTASK_INIT(gtask, 0, fn, q); 5023 taskqgroup_attach(tqg, gtask, q, tqrid, name); 5024 5025 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5026 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, tqrid, "tx"); 5027 return (0); 5028 } 5029 5030 void 5031 iflib_led_create(if_ctx_t ctx) 5032 { 5033 5034 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5035 device_get_nameunit(ctx->ifc_dev)); 5036 } 5037 5038 void 5039 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5040 { 5041 5042 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5043 } 5044 5045 void 5046 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5047 { 5048 5049 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5050 } 5051 5052 void 5053 iflib_admin_intr_deferred(if_ctx_t ctx) 5054 { 5055 #ifdef INVARIANTS 5056 struct grouptask *gtask; 5057 5058 gtask = &ctx->ifc_admin_task; 5059 MPASS(gtask->gt_taskqueue != NULL); 5060 #endif 5061 5062 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5063 } 5064 5065 void 5066 iflib_iov_intr_deferred(if_ctx_t ctx) 5067 { 5068 5069 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5070 } 5071 5072 void 5073 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5074 { 5075 5076 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5077 } 5078 5079 void 5080 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn, 5081 char *name) 5082 { 5083 5084 GROUPTASK_INIT(gtask, 0, fn, ctx); 5085 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5086 } 5087 5088 void 5089 iflib_config_gtask_deinit(struct grouptask *gtask) 5090 { 5091 5092 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5093 } 5094 5095 void 5096 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5097 { 5098 if_t ifp = ctx->ifc_ifp; 5099 iflib_txq_t txq = ctx->ifc_txqs; 5100 5101 if_setbaudrate(ifp, baudrate); 5102 if (baudrate >= IF_Gbps(10)) 5103 ctx->ifc_flags |= IFC_PREFETCH; 5104 5105 /* If link down, disable watchdog */ 5106 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5107 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5108 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5109 } 5110 ctx->ifc_link_state = link_state; 5111 if_link_state_change(ifp, link_state); 5112 } 5113 5114 static int 5115 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5116 { 5117 int credits; 5118 #ifdef INVARIANTS 5119 int credits_pre = txq->ift_cidx_processed; 5120 #endif 5121 5122 if (ctx->isc_txd_credits_update == NULL) 5123 return (0); 5124 5125 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5126 return (0); 5127 5128 txq->ift_processed += credits; 5129 txq->ift_cidx_processed += credits; 5130 5131 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5132 if (txq->ift_cidx_processed >= txq->ift_size) 5133 txq->ift_cidx_processed -= txq->ift_size; 5134 return (credits); 5135 } 5136 5137 static int 5138 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5139 { 5140 5141 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5142 budget)); 5143 } 5144 5145 void 5146 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5147 const char *description, if_int_delay_info_t info, 5148 int offset, int value) 5149 { 5150 info->iidi_ctx = ctx; 5151 info->iidi_offset = offset; 5152 info->iidi_value = value; 5153 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5154 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5155 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5156 info, 0, iflib_sysctl_int_delay, "I", description); 5157 } 5158 5159 struct mtx * 5160 iflib_ctx_lock_get(if_ctx_t ctx) 5161 { 5162 5163 return (&ctx->ifc_mtx); 5164 } 5165 5166 static int 5167 iflib_msix_init(if_ctx_t ctx) 5168 { 5169 device_t dev = ctx->ifc_dev; 5170 if_shared_ctx_t sctx = ctx->ifc_sctx; 5171 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5172 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5173 int iflib_num_tx_queues, iflib_num_rx_queues; 5174 int err, admincnt, bar; 5175 5176 iflib_num_tx_queues = scctx->isc_ntxqsets; 5177 iflib_num_rx_queues = scctx->isc_nrxqsets; 5178 5179 device_printf(dev, "msix_init qsets capped at %d\n", iflib_num_tx_queues); 5180 5181 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5182 admincnt = sctx->isc_admin_intrcnt; 5183 /* Override by tuneable */ 5184 if (enable_msix == 0) 5185 goto msi; 5186 5187 /* 5188 ** When used in a virtualized environment 5189 ** PCI BUSMASTER capability may not be set 5190 ** so explicity set it here and rewrite 5191 ** the ENABLE in the MSIX control register 5192 ** at this point to cause the host to 5193 ** successfully initialize us. 5194 */ 5195 { 5196 int msix_ctrl, rid; 5197 5198 pci_enable_busmaster(dev); 5199 rid = 0; 5200 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) { 5201 rid += PCIR_MSIX_CTRL; 5202 msix_ctrl = pci_read_config(dev, rid, 2); 5203 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 5204 pci_write_config(dev, rid, msix_ctrl, 2); 5205 } else { 5206 device_printf(dev, "PCIY_MSIX capability not found; " 5207 "or rid %d == 0.\n", rid); 5208 goto msi; 5209 } 5210 } 5211 5212 /* 5213 * bar == -1 => "trust me I know what I'm doing" 5214 * https://www.youtube.com/watch?v=nnwWKkNau4I 5215 * Some drivers are for hardware that is so shoddily 5216 * documented that no one knows which bars are which 5217 * so the developer has to map all bars. This hack 5218 * allows shoddy garbage to use msix in this framework. 5219 */ 5220 if (bar != -1) { 5221 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5222 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5223 if (ctx->ifc_msix_mem == NULL) { 5224 /* May not be enabled */ 5225 device_printf(dev, "Unable to map MSIX table \n"); 5226 goto msi; 5227 } 5228 } 5229 /* First try MSI/X */ 5230 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5231 device_printf(dev, "System has MSIX disabled \n"); 5232 bus_release_resource(dev, SYS_RES_MEMORY, 5233 bar, ctx->ifc_msix_mem); 5234 ctx->ifc_msix_mem = NULL; 5235 goto msi; 5236 } 5237 #if IFLIB_DEBUG 5238 /* use only 1 qset in debug mode */ 5239 queuemsgs = min(msgs - admincnt, 1); 5240 #else 5241 queuemsgs = msgs - admincnt; 5242 #endif 5243 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) == 0) { 5244 #ifdef RSS 5245 queues = imin(queuemsgs, rss_getnumbuckets()); 5246 #else 5247 queues = queuemsgs; 5248 #endif 5249 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 5250 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 5251 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 5252 } else { 5253 device_printf(dev, "Unable to fetch CPU list\n"); 5254 /* Figure out a reasonable auto config value */ 5255 queues = min(queuemsgs, mp_ncpus); 5256 } 5257 #ifdef RSS 5258 /* If we're doing RSS, clamp at the number of RSS buckets */ 5259 if (queues > rss_getnumbuckets()) 5260 queues = rss_getnumbuckets(); 5261 #endif 5262 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 5263 rx_queues = iflib_num_rx_queues; 5264 else 5265 rx_queues = queues; 5266 /* 5267 * We want this to be all logical CPUs by default 5268 */ 5269 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 5270 tx_queues = iflib_num_tx_queues; 5271 else 5272 tx_queues = mp_ncpus; 5273 5274 if (ctx->ifc_sysctl_qs_eq_override == 0) { 5275 #ifdef INVARIANTS 5276 if (tx_queues != rx_queues) 5277 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 5278 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 5279 #endif 5280 tx_queues = min(rx_queues, tx_queues); 5281 rx_queues = min(rx_queues, tx_queues); 5282 } 5283 5284 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 5285 5286 vectors = rx_queues + admincnt; 5287 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 5288 device_printf(dev, 5289 "Using MSIX interrupts with %d vectors\n", vectors); 5290 scctx->isc_vectors = vectors; 5291 scctx->isc_nrxqsets = rx_queues; 5292 scctx->isc_ntxqsets = tx_queues; 5293 scctx->isc_intr = IFLIB_INTR_MSIX; 5294 5295 return (vectors); 5296 } else { 5297 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 5298 } 5299 msi: 5300 vectors = pci_msi_count(dev); 5301 scctx->isc_nrxqsets = 1; 5302 scctx->isc_ntxqsets = 1; 5303 scctx->isc_vectors = vectors; 5304 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 5305 device_printf(dev,"Using an MSI interrupt\n"); 5306 scctx->isc_intr = IFLIB_INTR_MSI; 5307 } else { 5308 device_printf(dev,"Using a Legacy interrupt\n"); 5309 scctx->isc_intr = IFLIB_INTR_LEGACY; 5310 } 5311 5312 return (vectors); 5313 } 5314 5315 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 5316 5317 static int 5318 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 5319 { 5320 int rc; 5321 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 5322 struct sbuf *sb; 5323 char *ring_state = "UNKNOWN"; 5324 5325 /* XXX needed ? */ 5326 rc = sysctl_wire_old_buffer(req, 0); 5327 MPASS(rc == 0); 5328 if (rc != 0) 5329 return (rc); 5330 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 5331 MPASS(sb != NULL); 5332 if (sb == NULL) 5333 return (ENOMEM); 5334 if (state[3] <= 3) 5335 ring_state = ring_states[state[3]]; 5336 5337 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 5338 state[0], state[1], state[2], ring_state); 5339 rc = sbuf_finish(sb); 5340 sbuf_delete(sb); 5341 return(rc); 5342 } 5343 5344 enum iflib_ndesc_handler { 5345 IFLIB_NTXD_HANDLER, 5346 IFLIB_NRXD_HANDLER, 5347 }; 5348 5349 static int 5350 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 5351 { 5352 if_ctx_t ctx = (void *)arg1; 5353 enum iflib_ndesc_handler type = arg2; 5354 char buf[256] = {0}; 5355 qidx_t *ndesc; 5356 char *p, *next; 5357 int nqs, rc, i; 5358 5359 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 5360 5361 nqs = 8; 5362 switch(type) { 5363 case IFLIB_NTXD_HANDLER: 5364 ndesc = ctx->ifc_sysctl_ntxds; 5365 if (ctx->ifc_sctx) 5366 nqs = ctx->ifc_sctx->isc_ntxqs; 5367 break; 5368 case IFLIB_NRXD_HANDLER: 5369 ndesc = ctx->ifc_sysctl_nrxds; 5370 if (ctx->ifc_sctx) 5371 nqs = ctx->ifc_sctx->isc_nrxqs; 5372 break; 5373 } 5374 if (nqs == 0) 5375 nqs = 8; 5376 5377 for (i=0; i<8; i++) { 5378 if (i >= nqs) 5379 break; 5380 if (i) 5381 strcat(buf, ","); 5382 sprintf(strchr(buf, 0), "%d", ndesc[i]); 5383 } 5384 5385 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 5386 if (rc || req->newptr == NULL) 5387 return rc; 5388 5389 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 5390 i++, p = strsep(&next, " ,")) { 5391 ndesc[i] = strtoul(p, NULL, 10); 5392 } 5393 5394 return(rc); 5395 } 5396 5397 #define NAME_BUFLEN 32 5398 static void 5399 iflib_add_device_sysctl_pre(if_ctx_t ctx) 5400 { 5401 device_t dev = iflib_get_dev(ctx); 5402 struct sysctl_oid_list *child, *oid_list; 5403 struct sysctl_ctx_list *ctx_list; 5404 struct sysctl_oid *node; 5405 5406 ctx_list = device_get_sysctl_ctx(dev); 5407 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 5408 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 5409 CTLFLAG_RD, NULL, "IFLIB fields"); 5410 oid_list = SYSCTL_CHILDREN(node); 5411 5412 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 5413 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 5414 "driver version"); 5415 5416 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 5417 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 5418 "# of txqs to use, 0 => use default #"); 5419 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 5420 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 5421 "# of rxqs to use, 0 => use default #"); 5422 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 5423 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 5424 "permit #txq != #rxq"); 5425 5426 /* XXX change for per-queue sizes */ 5427 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 5428 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 5429 mp_ndesc_handler, "A", 5430 "list of # of tx descriptors to use, 0 = use default #"); 5431 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 5432 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 5433 mp_ndesc_handler, "A", 5434 "list of # of rx descriptors to use, 0 = use default #"); 5435 } 5436 5437 static void 5438 iflib_add_device_sysctl_post(if_ctx_t ctx) 5439 { 5440 if_shared_ctx_t sctx = ctx->ifc_sctx; 5441 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5442 device_t dev = iflib_get_dev(ctx); 5443 struct sysctl_oid_list *child; 5444 struct sysctl_ctx_list *ctx_list; 5445 iflib_fl_t fl; 5446 iflib_txq_t txq; 5447 iflib_rxq_t rxq; 5448 int i, j; 5449 char namebuf[NAME_BUFLEN]; 5450 char *qfmt; 5451 struct sysctl_oid *queue_node, *fl_node, *node; 5452 struct sysctl_oid_list *queue_list, *fl_list; 5453 ctx_list = device_get_sysctl_ctx(dev); 5454 5455 node = ctx->ifc_sysctl_node; 5456 child = SYSCTL_CHILDREN(node); 5457 5458 if (scctx->isc_ntxqsets > 100) 5459 qfmt = "txq%03d"; 5460 else if (scctx->isc_ntxqsets > 10) 5461 qfmt = "txq%02d"; 5462 else 5463 qfmt = "txq%d"; 5464 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 5465 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5466 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5467 CTLFLAG_RD, NULL, "Queue Name"); 5468 queue_list = SYSCTL_CHILDREN(queue_node); 5469 #if MEMORY_LOGGING 5470 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 5471 CTLFLAG_RD, 5472 &txq->ift_dequeued, "total mbufs freed"); 5473 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 5474 CTLFLAG_RD, 5475 &txq->ift_enqueued, "total mbufs enqueued"); 5476 #endif 5477 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 5478 CTLFLAG_RD, 5479 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 5480 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 5481 CTLFLAG_RD, 5482 &txq->ift_pullups, "# of times m_pullup was called"); 5483 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 5484 CTLFLAG_RD, 5485 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 5486 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 5487 CTLFLAG_RD, 5488 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 5489 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 5490 CTLFLAG_RD, 5491 &txq->ift_map_failed, "# of times dma map failed"); 5492 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 5493 CTLFLAG_RD, 5494 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 5495 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 5496 CTLFLAG_RD, 5497 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 5498 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 5499 CTLFLAG_RD, 5500 &txq->ift_pidx, 1, "Producer Index"); 5501 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 5502 CTLFLAG_RD, 5503 &txq->ift_cidx, 1, "Consumer Index"); 5504 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 5505 CTLFLAG_RD, 5506 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 5507 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 5508 CTLFLAG_RD, 5509 &txq->ift_in_use, 1, "descriptors in use"); 5510 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 5511 CTLFLAG_RD, 5512 &txq->ift_processed, "descriptors procesed for clean"); 5513 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 5514 CTLFLAG_RD, 5515 &txq->ift_cleaned, "total cleaned"); 5516 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 5517 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 5518 0, mp_ring_state_handler, "A", "soft ring state"); 5519 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 5520 CTLFLAG_RD, &txq->ift_br->enqueues, 5521 "# of enqueues to the mp_ring for this queue"); 5522 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 5523 CTLFLAG_RD, &txq->ift_br->drops, 5524 "# of drops in the mp_ring for this queue"); 5525 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 5526 CTLFLAG_RD, &txq->ift_br->starts, 5527 "# of normal consumer starts in the mp_ring for this queue"); 5528 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 5529 CTLFLAG_RD, &txq->ift_br->stalls, 5530 "# of consumer stalls in the mp_ring for this queue"); 5531 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 5532 CTLFLAG_RD, &txq->ift_br->restarts, 5533 "# of consumer restarts in the mp_ring for this queue"); 5534 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 5535 CTLFLAG_RD, &txq->ift_br->abdications, 5536 "# of consumer abdications in the mp_ring for this queue"); 5537 } 5538 5539 if (scctx->isc_nrxqsets > 100) 5540 qfmt = "rxq%03d"; 5541 else if (scctx->isc_nrxqsets > 10) 5542 qfmt = "rxq%02d"; 5543 else 5544 qfmt = "rxq%d"; 5545 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 5546 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5547 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5548 CTLFLAG_RD, NULL, "Queue Name"); 5549 queue_list = SYSCTL_CHILDREN(queue_node); 5550 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5551 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 5552 CTLFLAG_RD, 5553 &rxq->ifr_cq_pidx, 1, "Producer Index"); 5554 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 5555 CTLFLAG_RD, 5556 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 5557 } 5558 5559 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 5560 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 5561 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 5562 CTLFLAG_RD, NULL, "freelist Name"); 5563 fl_list = SYSCTL_CHILDREN(fl_node); 5564 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 5565 CTLFLAG_RD, 5566 &fl->ifl_pidx, 1, "Producer Index"); 5567 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 5568 CTLFLAG_RD, 5569 &fl->ifl_cidx, 1, "Consumer Index"); 5570 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 5571 CTLFLAG_RD, 5572 &fl->ifl_credits, 1, "credits available"); 5573 #if MEMORY_LOGGING 5574 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 5575 CTLFLAG_RD, 5576 &fl->ifl_m_enqueued, "mbufs allocated"); 5577 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 5578 CTLFLAG_RD, 5579 &fl->ifl_m_dequeued, "mbufs freed"); 5580 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 5581 CTLFLAG_RD, 5582 &fl->ifl_cl_enqueued, "clusters allocated"); 5583 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 5584 CTLFLAG_RD, 5585 &fl->ifl_cl_dequeued, "clusters freed"); 5586 #endif 5587 5588 } 5589 } 5590 5591 } 5592 5593 #ifndef __NO_STRICT_ALIGNMENT 5594 static struct mbuf * 5595 iflib_fixup_rx(struct mbuf *m) 5596 { 5597 struct mbuf *n; 5598 5599 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 5600 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 5601 m->m_data += ETHER_HDR_LEN; 5602 n = m; 5603 } else { 5604 MGETHDR(n, M_NOWAIT, MT_DATA); 5605 if (n == NULL) { 5606 m_freem(m); 5607 return (NULL); 5608 } 5609 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 5610 m->m_data += ETHER_HDR_LEN; 5611 m->m_len -= ETHER_HDR_LEN; 5612 n->m_len = ETHER_HDR_LEN; 5613 M_MOVE_PKTHDR(n, m); 5614 n->m_next = m; 5615 } 5616 return (n); 5617 } 5618 #endif 5619