1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/jail.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/md5.h> 44 #include <sys/mutex.h> 45 #include <sys/module.h> 46 #include <sys/kobj.h> 47 #include <sys/rman.h> 48 #include <sys/proc.h> 49 #include <sys/sbuf.h> 50 #include <sys/smp.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/syslog.h> 55 #include <sys/taskqueue.h> 56 #include <sys/limits.h> 57 58 #include <net/if.h> 59 #include <net/if_var.h> 60 #include <net/if_types.h> 61 #include <net/if_media.h> 62 #include <net/bpf.h> 63 #include <net/ethernet.h> 64 #include <net/mp_ring.h> 65 #include <net/vnet.h> 66 67 #include <netinet/in.h> 68 #include <netinet/in_pcb.h> 69 #include <netinet/tcp_lro.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/if_ether.h> 72 #include <netinet/ip.h> 73 #include <netinet/ip6.h> 74 #include <netinet/tcp.h> 75 #include <netinet/ip_var.h> 76 #include <netinet/netdump/netdump.h> 77 #include <netinet6/ip6_var.h> 78 79 #include <machine/bus.h> 80 #include <machine/in_cksum.h> 81 82 #include <vm/vm.h> 83 #include <vm/pmap.h> 84 85 #include <dev/led/led.h> 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pci_private.h> 89 90 #include <net/iflib.h> 91 #include <net/iflib_private.h> 92 93 #include "ifdi_if.h" 94 95 #if defined(__i386__) || defined(__amd64__) 96 #include <sys/memdesc.h> 97 #include <machine/bus.h> 98 #include <machine/md_var.h> 99 #include <machine/specialreg.h> 100 #include <x86/include/busdma_impl.h> 101 #include <x86/iommu/busdma_dmar.h> 102 #endif 103 104 #include <sys/bitstring.h> 105 /* 106 * enable accounting of every mbuf as it comes in to and goes out of 107 * iflib's software descriptor references 108 */ 109 #define MEMORY_LOGGING 0 110 /* 111 * Enable mbuf vectors for compressing long mbuf chains 112 */ 113 114 /* 115 * NB: 116 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 117 * we prefetch needs to be determined by the time spent in m_free vis a vis 118 * the cost of a prefetch. This will of course vary based on the workload: 119 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 120 * is quite expensive, thus suggesting very little prefetch. 121 * - small packet forwarding which is just returning a single mbuf to 122 * UMA will typically be very fast vis a vis the cost of a memory 123 * access. 124 */ 125 126 127 /* 128 * File organization: 129 * - private structures 130 * - iflib private utility functions 131 * - ifnet functions 132 * - vlan registry and other exported functions 133 * - iflib public core functions 134 * 135 * 136 */ 137 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 138 139 struct iflib_txq; 140 typedef struct iflib_txq *iflib_txq_t; 141 struct iflib_rxq; 142 typedef struct iflib_rxq *iflib_rxq_t; 143 struct iflib_fl; 144 typedef struct iflib_fl *iflib_fl_t; 145 146 struct iflib_ctx; 147 148 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 149 150 typedef struct iflib_filter_info { 151 driver_filter_t *ifi_filter; 152 void *ifi_filter_arg; 153 struct grouptask *ifi_task; 154 void *ifi_ctx; 155 } *iflib_filter_info_t; 156 157 struct iflib_ctx { 158 KOBJ_FIELDS; 159 /* 160 * Pointer to hardware driver's softc 161 */ 162 void *ifc_softc; 163 device_t ifc_dev; 164 if_t ifc_ifp; 165 166 cpuset_t ifc_cpus; 167 if_shared_ctx_t ifc_sctx; 168 struct if_softc_ctx ifc_softc_ctx; 169 170 struct sx ifc_ctx_sx; 171 struct mtx ifc_state_mtx; 172 173 uint16_t ifc_nhwtxqs; 174 175 iflib_txq_t ifc_txqs; 176 iflib_rxq_t ifc_rxqs; 177 uint32_t ifc_if_flags; 178 uint32_t ifc_flags; 179 uint32_t ifc_max_fl_buf_size; 180 int ifc_in_detach; 181 182 int ifc_link_state; 183 int ifc_link_irq; 184 int ifc_watchdog_events; 185 struct cdev *ifc_led_dev; 186 struct resource *ifc_msix_mem; 187 188 struct if_irq ifc_legacy_irq; 189 struct grouptask ifc_admin_task; 190 struct grouptask ifc_vflr_task; 191 struct iflib_filter_info ifc_filter_info; 192 struct ifmedia ifc_media; 193 194 struct sysctl_oid *ifc_sysctl_node; 195 uint16_t ifc_sysctl_ntxqs; 196 uint16_t ifc_sysctl_nrxqs; 197 uint16_t ifc_sysctl_qs_eq_override; 198 uint16_t ifc_sysctl_rx_budget; 199 200 qidx_t ifc_sysctl_ntxds[8]; 201 qidx_t ifc_sysctl_nrxds[8]; 202 struct if_txrx ifc_txrx; 203 #define isc_txd_encap ifc_txrx.ift_txd_encap 204 #define isc_txd_flush ifc_txrx.ift_txd_flush 205 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 206 #define isc_rxd_available ifc_txrx.ift_rxd_available 207 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 208 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 209 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 210 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 211 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 212 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 213 eventhandler_tag ifc_vlan_attach_event; 214 eventhandler_tag ifc_vlan_detach_event; 215 uint8_t ifc_mac[ETHER_ADDR_LEN]; 216 char ifc_mtx_name[16]; 217 }; 218 219 220 void * 221 iflib_get_softc(if_ctx_t ctx) 222 { 223 224 return (ctx->ifc_softc); 225 } 226 227 device_t 228 iflib_get_dev(if_ctx_t ctx) 229 { 230 231 return (ctx->ifc_dev); 232 } 233 234 if_t 235 iflib_get_ifp(if_ctx_t ctx) 236 { 237 238 return (ctx->ifc_ifp); 239 } 240 241 struct ifmedia * 242 iflib_get_media(if_ctx_t ctx) 243 { 244 245 return (&ctx->ifc_media); 246 } 247 248 uint32_t 249 iflib_get_flags(if_ctx_t ctx) 250 { 251 return (ctx->ifc_flags); 252 } 253 254 void 255 iflib_set_detach(if_ctx_t ctx) 256 { 257 ctx->ifc_in_detach = 1; 258 } 259 260 void 261 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 262 { 263 264 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 265 } 266 267 if_softc_ctx_t 268 iflib_get_softc_ctx(if_ctx_t ctx) 269 { 270 271 return (&ctx->ifc_softc_ctx); 272 } 273 274 if_shared_ctx_t 275 iflib_get_sctx(if_ctx_t ctx) 276 { 277 278 return (ctx->ifc_sctx); 279 } 280 281 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 282 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 283 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 284 285 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 286 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 287 288 #define RX_SW_DESC_MAP_CREATED (1 << 0) 289 #define TX_SW_DESC_MAP_CREATED (1 << 1) 290 #define RX_SW_DESC_INUSE (1 << 3) 291 #define TX_SW_DESC_MAPPED (1 << 4) 292 293 #define M_TOOBIG M_PROTO1 294 295 typedef struct iflib_sw_rx_desc_array { 296 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 297 struct mbuf **ifsd_m; /* pkthdr mbufs */ 298 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 299 uint8_t *ifsd_flags; 300 } iflib_rxsd_array_t; 301 302 typedef struct iflib_sw_tx_desc_array { 303 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 304 struct mbuf **ifsd_m; /* pkthdr mbufs */ 305 uint8_t *ifsd_flags; 306 } if_txsd_vec_t; 307 308 309 /* magic number that should be high enough for any hardware */ 310 #define IFLIB_MAX_TX_SEGS 128 311 /* bnxt supports 64 with hardware LRO enabled */ 312 #define IFLIB_MAX_RX_SEGS 64 313 #define IFLIB_RX_COPY_THRESH 128 314 #define IFLIB_MAX_RX_REFRESH 32 315 /* The minimum descriptors per second before we start coalescing */ 316 #define IFLIB_MIN_DESC_SEC 16384 317 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 318 #define IFLIB_QUEUE_IDLE 0 319 #define IFLIB_QUEUE_HUNG 1 320 #define IFLIB_QUEUE_WORKING 2 321 /* maximum number of txqs that can share an rx interrupt */ 322 #define IFLIB_MAX_TX_SHARED_INTR 4 323 324 /* this should really scale with ring size - this is a fairly arbitrary value */ 325 #define TX_BATCH_SIZE 32 326 327 #define IFLIB_RESTART_BUDGET 8 328 329 330 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 331 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 332 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 333 struct iflib_txq { 334 qidx_t ift_in_use; 335 qidx_t ift_cidx; 336 qidx_t ift_cidx_processed; 337 qidx_t ift_pidx; 338 uint8_t ift_gen; 339 uint8_t ift_br_offset; 340 uint16_t ift_npending; 341 uint16_t ift_db_pending; 342 uint16_t ift_rs_pending; 343 /* implicit pad */ 344 uint8_t ift_txd_size[8]; 345 uint64_t ift_processed; 346 uint64_t ift_cleaned; 347 uint64_t ift_cleaned_prev; 348 #if MEMORY_LOGGING 349 uint64_t ift_enqueued; 350 uint64_t ift_dequeued; 351 #endif 352 uint64_t ift_no_tx_dma_setup; 353 uint64_t ift_no_desc_avail; 354 uint64_t ift_mbuf_defrag_failed; 355 uint64_t ift_mbuf_defrag; 356 uint64_t ift_map_failed; 357 uint64_t ift_txd_encap_efbig; 358 uint64_t ift_pullups; 359 360 struct mtx ift_mtx; 361 struct mtx ift_db_mtx; 362 363 /* constant values */ 364 if_ctx_t ift_ctx; 365 struct ifmp_ring *ift_br; 366 struct grouptask ift_task; 367 qidx_t ift_size; 368 uint16_t ift_id; 369 struct callout ift_timer; 370 371 if_txsd_vec_t ift_sds; 372 uint8_t ift_qstatus; 373 uint8_t ift_closed; 374 uint8_t ift_update_freq; 375 struct iflib_filter_info ift_filter_info; 376 bus_dma_tag_t ift_desc_tag; 377 bus_dma_tag_t ift_tso_desc_tag; 378 iflib_dma_info_t ift_ifdi; 379 #define MTX_NAME_LEN 16 380 char ift_mtx_name[MTX_NAME_LEN]; 381 char ift_db_mtx_name[MTX_NAME_LEN]; 382 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 383 #ifdef IFLIB_DIAGNOSTICS 384 uint64_t ift_cpu_exec_count[256]; 385 #endif 386 } __aligned(CACHE_LINE_SIZE); 387 388 struct iflib_fl { 389 qidx_t ifl_cidx; 390 qidx_t ifl_pidx; 391 qidx_t ifl_credits; 392 uint8_t ifl_gen; 393 uint8_t ifl_rxd_size; 394 #if MEMORY_LOGGING 395 uint64_t ifl_m_enqueued; 396 uint64_t ifl_m_dequeued; 397 uint64_t ifl_cl_enqueued; 398 uint64_t ifl_cl_dequeued; 399 #endif 400 /* implicit pad */ 401 402 bitstr_t *ifl_rx_bitmap; 403 qidx_t ifl_fragidx; 404 /* constant */ 405 qidx_t ifl_size; 406 uint16_t ifl_buf_size; 407 uint16_t ifl_cltype; 408 uma_zone_t ifl_zone; 409 iflib_rxsd_array_t ifl_sds; 410 iflib_rxq_t ifl_rxq; 411 uint8_t ifl_id; 412 bus_dma_tag_t ifl_desc_tag; 413 iflib_dma_info_t ifl_ifdi; 414 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 415 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 416 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 417 } __aligned(CACHE_LINE_SIZE); 418 419 static inline qidx_t 420 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 421 { 422 qidx_t used; 423 424 if (pidx > cidx) 425 used = pidx - cidx; 426 else if (pidx < cidx) 427 used = size - cidx + pidx; 428 else if (gen == 0 && pidx == cidx) 429 used = 0; 430 else if (gen == 1 && pidx == cidx) 431 used = size; 432 else 433 panic("bad state"); 434 435 return (used); 436 } 437 438 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 439 440 #define IDXDIFF(head, tail, wrap) \ 441 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 442 443 struct iflib_rxq { 444 /* If there is a separate completion queue - 445 * these are the cq cidx and pidx. Otherwise 446 * these are unused. 447 */ 448 qidx_t ifr_size; 449 qidx_t ifr_cq_cidx; 450 qidx_t ifr_cq_pidx; 451 uint8_t ifr_cq_gen; 452 uint8_t ifr_fl_offset; 453 454 if_ctx_t ifr_ctx; 455 iflib_fl_t ifr_fl; 456 uint64_t ifr_rx_irq; 457 uint16_t ifr_id; 458 uint8_t ifr_lro_enabled; 459 uint8_t ifr_nfl; 460 uint8_t ifr_ntxqirq; 461 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 462 struct lro_ctrl ifr_lc; 463 struct grouptask ifr_task; 464 struct iflib_filter_info ifr_filter_info; 465 iflib_dma_info_t ifr_ifdi; 466 467 /* dynamically allocate if any drivers need a value substantially larger than this */ 468 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 469 #ifdef IFLIB_DIAGNOSTICS 470 uint64_t ifr_cpu_exec_count[256]; 471 #endif 472 } __aligned(CACHE_LINE_SIZE); 473 474 typedef struct if_rxsd { 475 caddr_t *ifsd_cl; 476 struct mbuf **ifsd_m; 477 iflib_fl_t ifsd_fl; 478 qidx_t ifsd_cidx; 479 } *if_rxsd_t; 480 481 /* multiple of word size */ 482 #ifdef __LP64__ 483 #define PKT_INFO_SIZE 6 484 #define RXD_INFO_SIZE 5 485 #define PKT_TYPE uint64_t 486 #else 487 #define PKT_INFO_SIZE 11 488 #define RXD_INFO_SIZE 8 489 #define PKT_TYPE uint32_t 490 #endif 491 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 492 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 493 494 typedef struct if_pkt_info_pad { 495 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 496 } *if_pkt_info_pad_t; 497 typedef struct if_rxd_info_pad { 498 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 499 } *if_rxd_info_pad_t; 500 501 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 502 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 503 504 505 static inline void 506 pkt_info_zero(if_pkt_info_t pi) 507 { 508 if_pkt_info_pad_t pi_pad; 509 510 pi_pad = (if_pkt_info_pad_t)pi; 511 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 512 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 513 #ifndef __LP64__ 514 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 515 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 516 #endif 517 } 518 519 static device_method_t iflib_pseudo_methods[] = { 520 DEVMETHOD(device_attach, noop_attach), 521 DEVMETHOD(device_detach, iflib_pseudo_detach), 522 DEVMETHOD_END 523 }; 524 525 driver_t iflib_pseudodriver = { 526 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 527 }; 528 529 static inline void 530 rxd_info_zero(if_rxd_info_t ri) 531 { 532 if_rxd_info_pad_t ri_pad; 533 int i; 534 535 ri_pad = (if_rxd_info_pad_t)ri; 536 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 537 ri_pad->rxd_val[i] = 0; 538 ri_pad->rxd_val[i+1] = 0; 539 ri_pad->rxd_val[i+2] = 0; 540 ri_pad->rxd_val[i+3] = 0; 541 } 542 #ifdef __LP64__ 543 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 544 #endif 545 } 546 547 /* 548 * Only allow a single packet to take up most 1/nth of the tx ring 549 */ 550 #define MAX_SINGLE_PACKET_FRACTION 12 551 #define IF_BAD_DMA (bus_addr_t)-1 552 553 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 554 555 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 556 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 557 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 558 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 559 560 561 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 562 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 563 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 564 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 565 566 567 568 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 569 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 570 571 572 /* Our boot-time initialization hook */ 573 static int iflib_module_event_handler(module_t, int, void *); 574 575 static moduledata_t iflib_moduledata = { 576 "iflib", 577 iflib_module_event_handler, 578 NULL 579 }; 580 581 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 582 MODULE_VERSION(iflib, 1); 583 584 MODULE_DEPEND(iflib, pci, 1, 1, 1); 585 MODULE_DEPEND(iflib, ether, 1, 1, 1); 586 587 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 588 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 589 590 #ifndef IFLIB_DEBUG_COUNTERS 591 #ifdef INVARIANTS 592 #define IFLIB_DEBUG_COUNTERS 1 593 #else 594 #define IFLIB_DEBUG_COUNTERS 0 595 #endif /* !INVARIANTS */ 596 #endif 597 598 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 599 "iflib driver parameters"); 600 601 /* 602 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 603 */ 604 static int iflib_min_tx_latency = 0; 605 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 606 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 607 static int iflib_no_tx_batch = 0; 608 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 609 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 610 611 612 #if IFLIB_DEBUG_COUNTERS 613 614 static int iflib_tx_seen; 615 static int iflib_tx_sent; 616 static int iflib_tx_encap; 617 static int iflib_rx_allocs; 618 static int iflib_fl_refills; 619 static int iflib_fl_refills_large; 620 static int iflib_tx_frees; 621 622 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 623 &iflib_tx_seen, 0, "# tx mbufs seen"); 624 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 625 &iflib_tx_sent, 0, "# tx mbufs sent"); 626 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 627 &iflib_tx_encap, 0, "# tx mbufs encapped"); 628 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 629 &iflib_tx_frees, 0, "# tx frees"); 630 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 631 &iflib_rx_allocs, 0, "# rx allocations"); 632 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 633 &iflib_fl_refills, 0, "# refills"); 634 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 635 &iflib_fl_refills_large, 0, "# large refills"); 636 637 638 static int iflib_txq_drain_flushing; 639 static int iflib_txq_drain_oactive; 640 static int iflib_txq_drain_notready; 641 static int iflib_txq_drain_encapfail; 642 643 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 644 &iflib_txq_drain_flushing, 0, "# drain flushes"); 645 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 646 &iflib_txq_drain_oactive, 0, "# drain oactives"); 647 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 648 &iflib_txq_drain_notready, 0, "# drain notready"); 649 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 650 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 651 652 653 static int iflib_encap_load_mbuf_fail; 654 static int iflib_encap_pad_mbuf_fail; 655 static int iflib_encap_txq_avail_fail; 656 static int iflib_encap_txd_encap_fail; 657 658 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 659 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 661 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 663 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 665 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 666 667 static int iflib_task_fn_rxs; 668 static int iflib_rx_intr_enables; 669 static int iflib_fast_intrs; 670 static int iflib_intr_link; 671 static int iflib_intr_msix; 672 static int iflib_rx_unavail; 673 static int iflib_rx_ctx_inactive; 674 static int iflib_rx_zero_len; 675 static int iflib_rx_if_input; 676 static int iflib_rx_mbuf_null; 677 static int iflib_rxd_flush; 678 679 static int iflib_verbose_debug; 680 681 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 682 &iflib_intr_link, 0, "# intr link calls"); 683 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 684 &iflib_intr_msix, 0, "# intr msix calls"); 685 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 686 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 687 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 688 &iflib_rx_intr_enables, 0, "# rx intr enables"); 689 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 690 &iflib_fast_intrs, 0, "# fast_intr calls"); 691 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 692 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 693 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 694 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 695 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 696 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 697 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 698 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 699 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 700 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 701 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 702 &iflib_rxd_flush, 0, "# times rxd_flush called"); 703 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 704 &iflib_verbose_debug, 0, "enable verbose debugging"); 705 706 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 707 static void 708 iflib_debug_reset(void) 709 { 710 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 711 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 712 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 713 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 714 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 715 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 716 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 717 iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 718 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 719 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 720 } 721 722 #else 723 #define DBG_COUNTER_INC(name) 724 static void iflib_debug_reset(void) {} 725 #endif 726 727 #define IFLIB_DEBUG 0 728 729 static void iflib_tx_structures_free(if_ctx_t ctx); 730 static void iflib_rx_structures_free(if_ctx_t ctx); 731 static int iflib_queues_alloc(if_ctx_t ctx); 732 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 733 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 734 static int iflib_qset_structures_setup(if_ctx_t ctx); 735 static int iflib_msix_init(if_ctx_t ctx); 736 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 737 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 738 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 739 static int iflib_register(if_ctx_t); 740 static void iflib_init_locked(if_ctx_t ctx); 741 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 742 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 743 static void iflib_ifmp_purge(iflib_txq_t txq); 744 static void _iflib_pre_assert(if_softc_ctx_t scctx); 745 static void iflib_if_init_locked(if_ctx_t ctx); 746 #ifndef __NO_STRICT_ALIGNMENT 747 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 748 #endif 749 750 NETDUMP_DEFINE(iflib); 751 752 #ifdef DEV_NETMAP 753 #include <sys/selinfo.h> 754 #include <net/netmap.h> 755 #include <dev/netmap/netmap_kern.h> 756 757 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 758 759 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 760 761 /* 762 * device-specific sysctl variables: 763 * 764 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 765 * During regular operations the CRC is stripped, but on some 766 * hardware reception of frames not multiple of 64 is slower, 767 * so using crcstrip=0 helps in benchmarks. 768 * 769 * iflib_rx_miss, iflib_rx_miss_bufs: 770 * count packets that might be missed due to lost interrupts. 771 */ 772 SYSCTL_DECL(_dev_netmap); 773 /* 774 * The xl driver by default strips CRCs and we do not override it. 775 */ 776 777 int iflib_crcstrip = 1; 778 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 779 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 780 781 int iflib_rx_miss, iflib_rx_miss_bufs; 782 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 783 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 784 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 785 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 786 787 /* 788 * Register/unregister. We are already under netmap lock. 789 * Only called on the first register or the last unregister. 790 */ 791 static int 792 iflib_netmap_register(struct netmap_adapter *na, int onoff) 793 { 794 struct ifnet *ifp = na->ifp; 795 if_ctx_t ctx = ifp->if_softc; 796 int status; 797 798 CTX_LOCK(ctx); 799 IFDI_INTR_DISABLE(ctx); 800 801 /* Tell the stack that the interface is no longer active */ 802 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 803 804 if (!CTX_IS_VF(ctx)) 805 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 806 807 /* enable or disable flags and callbacks in na and ifp */ 808 if (onoff) { 809 nm_set_native_flags(na); 810 } else { 811 nm_clear_native_flags(na); 812 } 813 iflib_stop(ctx); 814 iflib_init_locked(ctx); 815 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 816 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 817 if (status) 818 nm_clear_native_flags(na); 819 CTX_UNLOCK(ctx); 820 return (status); 821 } 822 823 static int 824 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 825 { 826 struct netmap_adapter *na = kring->na; 827 u_int const lim = kring->nkr_num_slots - 1; 828 u_int head = kring->rhead; 829 struct netmap_ring *ring = kring->ring; 830 bus_dmamap_t *map; 831 struct if_rxd_update iru; 832 if_ctx_t ctx = rxq->ifr_ctx; 833 iflib_fl_t fl = &rxq->ifr_fl[0]; 834 uint32_t refill_pidx, nic_i; 835 836 if (nm_i == head && __predict_true(!init)) 837 return 0; 838 iru_init(&iru, rxq, 0 /* flid */); 839 map = fl->ifl_sds.ifsd_map; 840 refill_pidx = netmap_idx_k2n(kring, nm_i); 841 /* 842 * IMPORTANT: we must leave one free slot in the ring, 843 * so move head back by one unit 844 */ 845 head = nm_prev(head, lim); 846 nic_i = UINT_MAX; 847 while (nm_i != head) { 848 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 849 struct netmap_slot *slot = &ring->slot[nm_i]; 850 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 851 uint32_t nic_i_dma = refill_pidx; 852 nic_i = netmap_idx_k2n(kring, nm_i); 853 854 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 855 856 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 857 return netmap_ring_reinit(kring); 858 859 fl->ifl_vm_addrs[tmp_pidx] = addr; 860 if (__predict_false(init) && map) { 861 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 862 } else if (map && (slot->flags & NS_BUF_CHANGED)) { 863 /* buffer has changed, reload map */ 864 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 865 } 866 slot->flags &= ~NS_BUF_CHANGED; 867 868 nm_i = nm_next(nm_i, lim); 869 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 870 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 871 continue; 872 873 iru.iru_pidx = refill_pidx; 874 iru.iru_count = tmp_pidx+1; 875 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 876 877 refill_pidx = nic_i; 878 if (map == NULL) 879 continue; 880 881 for (int n = 0; n < iru.iru_count; n++) { 882 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma], 883 BUS_DMASYNC_PREREAD); 884 /* XXX - change this to not use the netmap func*/ 885 nic_i_dma = nm_next(nic_i_dma, lim); 886 } 887 } 888 } 889 kring->nr_hwcur = head; 890 891 if (map) 892 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 893 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 894 if (__predict_true(nic_i != UINT_MAX)) 895 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 896 return (0); 897 } 898 899 /* 900 * Reconcile kernel and user view of the transmit ring. 901 * 902 * All information is in the kring. 903 * Userspace wants to send packets up to the one before kring->rhead, 904 * kernel knows kring->nr_hwcur is the first unsent packet. 905 * 906 * Here we push packets out (as many as possible), and possibly 907 * reclaim buffers from previously completed transmission. 908 * 909 * The caller (netmap) guarantees that there is only one instance 910 * running at any time. Any interference with other driver 911 * methods should be handled by the individual drivers. 912 */ 913 static int 914 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 915 { 916 struct netmap_adapter *na = kring->na; 917 struct ifnet *ifp = na->ifp; 918 struct netmap_ring *ring = kring->ring; 919 u_int nm_i; /* index into the netmap ring */ 920 u_int nic_i; /* index into the NIC ring */ 921 u_int n; 922 u_int const lim = kring->nkr_num_slots - 1; 923 u_int const head = kring->rhead; 924 struct if_pkt_info pi; 925 926 /* 927 * interrupts on every tx packet are expensive so request 928 * them every half ring, or where NS_REPORT is set 929 */ 930 u_int report_frequency = kring->nkr_num_slots >> 1; 931 /* device-specific */ 932 if_ctx_t ctx = ifp->if_softc; 933 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 934 935 if (txq->ift_sds.ifsd_map) 936 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 937 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 938 939 940 /* 941 * First part: process new packets to send. 942 * nm_i is the current index in the netmap ring, 943 * nic_i is the corresponding index in the NIC ring. 944 * 945 * If we have packets to send (nm_i != head) 946 * iterate over the netmap ring, fetch length and update 947 * the corresponding slot in the NIC ring. Some drivers also 948 * need to update the buffer's physical address in the NIC slot 949 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 950 * 951 * The netmap_reload_map() calls is especially expensive, 952 * even when (as in this case) the tag is 0, so do only 953 * when the buffer has actually changed. 954 * 955 * If possible do not set the report/intr bit on all slots, 956 * but only a few times per ring or when NS_REPORT is set. 957 * 958 * Finally, on 10G and faster drivers, it might be useful 959 * to prefetch the next slot and txr entry. 960 */ 961 962 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 963 if (nm_i != head) { /* we have new packets to send */ 964 pkt_info_zero(&pi); 965 pi.ipi_segs = txq->ift_segs; 966 pi.ipi_qsidx = kring->ring_id; 967 nic_i = netmap_idx_k2n(kring, nm_i); 968 969 __builtin_prefetch(&ring->slot[nm_i]); 970 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 971 if (txq->ift_sds.ifsd_map) 972 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 973 974 for (n = 0; nm_i != head; n++) { 975 struct netmap_slot *slot = &ring->slot[nm_i]; 976 u_int len = slot->len; 977 uint64_t paddr; 978 void *addr = PNMB(na, slot, &paddr); 979 int flags = (slot->flags & NS_REPORT || 980 nic_i == 0 || nic_i == report_frequency) ? 981 IPI_TX_INTR : 0; 982 983 /* device-specific */ 984 pi.ipi_len = len; 985 pi.ipi_segs[0].ds_addr = paddr; 986 pi.ipi_segs[0].ds_len = len; 987 pi.ipi_nsegs = 1; 988 pi.ipi_ndescs = 0; 989 pi.ipi_pidx = nic_i; 990 pi.ipi_flags = flags; 991 992 /* Fill the slot in the NIC ring. */ 993 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 994 995 /* prefetch for next round */ 996 __builtin_prefetch(&ring->slot[nm_i + 1]); 997 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 998 if (txq->ift_sds.ifsd_map) { 999 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1000 1001 NM_CHECK_ADDR_LEN(na, addr, len); 1002 1003 if (slot->flags & NS_BUF_CHANGED) { 1004 /* buffer has changed, reload map */ 1005 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 1006 } 1007 /* make sure changes to the buffer are synced */ 1008 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 1009 BUS_DMASYNC_PREWRITE); 1010 } 1011 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1012 nm_i = nm_next(nm_i, lim); 1013 nic_i = nm_next(nic_i, lim); 1014 } 1015 kring->nr_hwcur = head; 1016 1017 /* synchronize the NIC ring */ 1018 if (txq->ift_sds.ifsd_map) 1019 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 1020 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1021 1022 /* (re)start the tx unit up to slot nic_i (excluded) */ 1023 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1024 } 1025 1026 /* 1027 * Second part: reclaim buffers for completed transmissions. 1028 * 1029 * If there are unclaimed buffers, attempt to reclaim them. 1030 * If none are reclaimed, and TX IRQs are not in use, do an initial 1031 * minimal delay, then trigger the tx handler which will spin in the 1032 * group task queue. 1033 */ 1034 if (kring->nr_hwtail != nm_prev(head, lim)) { 1035 if (iflib_tx_credits_update(ctx, txq)) { 1036 /* some tx completed, increment avail */ 1037 nic_i = txq->ift_cidx_processed; 1038 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1039 } 1040 else { 1041 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1042 DELAY(1); 1043 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txq->ift_id].ift_task); 1044 } 1045 } 1046 } 1047 return (0); 1048 } 1049 1050 /* 1051 * Reconcile kernel and user view of the receive ring. 1052 * Same as for the txsync, this routine must be efficient. 1053 * The caller guarantees a single invocations, but races against 1054 * the rest of the driver should be handled here. 1055 * 1056 * On call, kring->rhead is the first packet that userspace wants 1057 * to keep, and kring->rcur is the wakeup point. 1058 * The kernel has previously reported packets up to kring->rtail. 1059 * 1060 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1061 * of whether or not we received an interrupt. 1062 */ 1063 static int 1064 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1065 { 1066 struct netmap_adapter *na = kring->na; 1067 struct netmap_ring *ring = kring->ring; 1068 uint32_t nm_i; /* index into the netmap ring */ 1069 uint32_t nic_i; /* index into the NIC ring */ 1070 u_int i, n; 1071 u_int const lim = kring->nkr_num_slots - 1; 1072 u_int const head = netmap_idx_n2k(kring, kring->rhead); 1073 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1074 struct if_rxd_info ri; 1075 1076 struct ifnet *ifp = na->ifp; 1077 if_ctx_t ctx = ifp->if_softc; 1078 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1079 iflib_fl_t fl = rxq->ifr_fl; 1080 if (head > lim) 1081 return netmap_ring_reinit(kring); 1082 1083 /* XXX check sync modes */ 1084 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1085 if (fl->ifl_sds.ifsd_map == NULL) 1086 continue; 1087 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 1088 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1089 } 1090 /* 1091 * First part: import newly received packets. 1092 * 1093 * nm_i is the index of the next free slot in the netmap ring, 1094 * nic_i is the index of the next received packet in the NIC ring, 1095 * and they may differ in case if_init() has been called while 1096 * in netmap mode. For the receive ring we have 1097 * 1098 * nic_i = rxr->next_check; 1099 * nm_i = kring->nr_hwtail (previous) 1100 * and 1101 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1102 * 1103 * rxr->next_check is set to 0 on a ring reinit 1104 */ 1105 if (netmap_no_pendintr || force_update) { 1106 int crclen = iflib_crcstrip ? 0 : 4; 1107 int error, avail; 1108 1109 for (i = 0; i < rxq->ifr_nfl; i++) { 1110 fl = &rxq->ifr_fl[i]; 1111 nic_i = fl->ifl_cidx; 1112 nm_i = netmap_idx_n2k(kring, nic_i); 1113 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 1114 for (n = 0; avail > 0; n++, avail--) { 1115 rxd_info_zero(&ri); 1116 ri.iri_frags = rxq->ifr_frags; 1117 ri.iri_qsidx = kring->ring_id; 1118 ri.iri_ifp = ctx->ifc_ifp; 1119 ri.iri_cidx = nic_i; 1120 1121 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1122 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1123 ring->slot[nm_i].flags = 0; 1124 if (fl->ifl_sds.ifsd_map) 1125 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1126 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1127 nm_i = nm_next(nm_i, lim); 1128 nic_i = nm_next(nic_i, lim); 1129 } 1130 if (n) { /* update the state variables */ 1131 if (netmap_no_pendintr && !force_update) { 1132 /* diagnostics */ 1133 iflib_rx_miss ++; 1134 iflib_rx_miss_bufs += n; 1135 } 1136 fl->ifl_cidx = nic_i; 1137 kring->nr_hwtail = netmap_idx_k2n(kring, nm_i); 1138 } 1139 kring->nr_kflags &= ~NKR_PENDINTR; 1140 } 1141 } 1142 /* 1143 * Second part: skip past packets that userspace has released. 1144 * (kring->nr_hwcur to head excluded), 1145 * and make the buffers available for reception. 1146 * As usual nm_i is the index in the netmap ring, 1147 * nic_i is the index in the NIC ring, and 1148 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1149 */ 1150 /* XXX not sure how this will work with multiple free lists */ 1151 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 1152 1153 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1154 } 1155 1156 static void 1157 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1158 { 1159 struct ifnet *ifp = na->ifp; 1160 if_ctx_t ctx = ifp->if_softc; 1161 1162 CTX_LOCK(ctx); 1163 if (onoff) { 1164 IFDI_INTR_ENABLE(ctx); 1165 } else { 1166 IFDI_INTR_DISABLE(ctx); 1167 } 1168 CTX_UNLOCK(ctx); 1169 } 1170 1171 1172 static int 1173 iflib_netmap_attach(if_ctx_t ctx) 1174 { 1175 struct netmap_adapter na; 1176 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1177 1178 bzero(&na, sizeof(na)); 1179 1180 na.ifp = ctx->ifc_ifp; 1181 na.na_flags = NAF_BDG_MAYSLEEP; 1182 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1183 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1184 1185 na.num_tx_desc = scctx->isc_ntxd[0]; 1186 na.num_rx_desc = scctx->isc_nrxd[0]; 1187 na.nm_txsync = iflib_netmap_txsync; 1188 na.nm_rxsync = iflib_netmap_rxsync; 1189 na.nm_register = iflib_netmap_register; 1190 na.nm_intr = iflib_netmap_intr; 1191 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1192 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1193 return (netmap_attach(&na)); 1194 } 1195 1196 static void 1197 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1198 { 1199 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1200 struct netmap_slot *slot; 1201 1202 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1203 if (slot == NULL) 1204 return; 1205 if (txq->ift_sds.ifsd_map == NULL) 1206 return; 1207 1208 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1209 1210 /* 1211 * In netmap mode, set the map for the packet buffer. 1212 * NOTE: Some drivers (not this one) also need to set 1213 * the physical buffer address in the NIC ring. 1214 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1215 * netmap slot index, si 1216 */ 1217 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1218 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1219 } 1220 } 1221 1222 static void 1223 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1224 { 1225 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1226 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1227 struct netmap_slot *slot; 1228 uint32_t nm_i; 1229 1230 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1231 if (slot == NULL) 1232 return; 1233 nm_i = netmap_idx_n2k(kring, 0); 1234 netmap_fl_refill(rxq, kring, nm_i, true); 1235 } 1236 1237 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1238 1239 #else 1240 #define iflib_netmap_txq_init(ctx, txq) 1241 #define iflib_netmap_rxq_init(ctx, rxq) 1242 #define iflib_netmap_detach(ifp) 1243 1244 #define iflib_netmap_attach(ctx) (0) 1245 #define netmap_rx_irq(ifp, qid, budget) (0) 1246 #define netmap_tx_irq(ifp, qid) do {} while (0) 1247 1248 #endif 1249 1250 #if defined(__i386__) || defined(__amd64__) 1251 static __inline void 1252 prefetch(void *x) 1253 { 1254 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1255 } 1256 static __inline void 1257 prefetch2cachelines(void *x) 1258 { 1259 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1260 #if (CACHE_LINE_SIZE < 128) 1261 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1262 #endif 1263 } 1264 #else 1265 #define prefetch(x) 1266 #define prefetch2cachelines(x) 1267 #endif 1268 1269 static void 1270 iflib_gen_mac(if_ctx_t ctx) 1271 { 1272 struct thread *td; 1273 MD5_CTX mdctx; 1274 char uuid[HOSTUUIDLEN+1]; 1275 char buf[HOSTUUIDLEN+16]; 1276 uint8_t *mac; 1277 unsigned char digest[16]; 1278 1279 td = curthread; 1280 mac = ctx->ifc_mac; 1281 uuid[HOSTUUIDLEN] = 0; 1282 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN); 1283 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev)); 1284 /* 1285 * Generate a pseudo-random, deterministic MAC 1286 * address based on the UUID and unit number. 1287 * The FreeBSD Foundation OUI of 58-9C-FC is used. 1288 */ 1289 MD5Init(&mdctx); 1290 MD5Update(&mdctx, buf, strlen(buf)); 1291 MD5Final(digest, &mdctx); 1292 1293 mac[0] = 0x58; 1294 mac[1] = 0x9C; 1295 mac[2] = 0xFC; 1296 mac[3] = digest[0]; 1297 mac[4] = digest[1]; 1298 mac[5] = digest[2]; 1299 } 1300 1301 static void 1302 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1303 { 1304 iflib_fl_t fl; 1305 1306 fl = &rxq->ifr_fl[flid]; 1307 iru->iru_paddrs = fl->ifl_bus_addrs; 1308 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1309 iru->iru_idxs = fl->ifl_rxd_idxs; 1310 iru->iru_qsidx = rxq->ifr_id; 1311 iru->iru_buf_size = fl->ifl_buf_size; 1312 iru->iru_flidx = fl->ifl_id; 1313 } 1314 1315 static void 1316 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1317 { 1318 if (err) 1319 return; 1320 *(bus_addr_t *) arg = segs[0].ds_addr; 1321 } 1322 1323 int 1324 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1325 { 1326 int err; 1327 if_shared_ctx_t sctx = ctx->ifc_sctx; 1328 device_t dev = ctx->ifc_dev; 1329 1330 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1331 1332 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1333 sctx->isc_q_align, 0, /* alignment, bounds */ 1334 BUS_SPACE_MAXADDR, /* lowaddr */ 1335 BUS_SPACE_MAXADDR, /* highaddr */ 1336 NULL, NULL, /* filter, filterarg */ 1337 size, /* maxsize */ 1338 1, /* nsegments */ 1339 size, /* maxsegsize */ 1340 BUS_DMA_ALLOCNOW, /* flags */ 1341 NULL, /* lockfunc */ 1342 NULL, /* lockarg */ 1343 &dma->idi_tag); 1344 if (err) { 1345 device_printf(dev, 1346 "%s: bus_dma_tag_create failed: %d\n", 1347 __func__, err); 1348 goto fail_0; 1349 } 1350 1351 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1352 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1353 if (err) { 1354 device_printf(dev, 1355 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1356 __func__, (uintmax_t)size, err); 1357 goto fail_1; 1358 } 1359 1360 dma->idi_paddr = IF_BAD_DMA; 1361 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1362 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1363 if (err || dma->idi_paddr == IF_BAD_DMA) { 1364 device_printf(dev, 1365 "%s: bus_dmamap_load failed: %d\n", 1366 __func__, err); 1367 goto fail_2; 1368 } 1369 1370 dma->idi_size = size; 1371 return (0); 1372 1373 fail_2: 1374 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1375 fail_1: 1376 bus_dma_tag_destroy(dma->idi_tag); 1377 fail_0: 1378 dma->idi_tag = NULL; 1379 1380 return (err); 1381 } 1382 1383 int 1384 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1385 { 1386 int i, err; 1387 iflib_dma_info_t *dmaiter; 1388 1389 dmaiter = dmalist; 1390 for (i = 0; i < count; i++, dmaiter++) { 1391 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1392 break; 1393 } 1394 if (err) 1395 iflib_dma_free_multi(dmalist, i); 1396 return (err); 1397 } 1398 1399 void 1400 iflib_dma_free(iflib_dma_info_t dma) 1401 { 1402 if (dma->idi_tag == NULL) 1403 return; 1404 if (dma->idi_paddr != IF_BAD_DMA) { 1405 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1406 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1407 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1408 dma->idi_paddr = IF_BAD_DMA; 1409 } 1410 if (dma->idi_vaddr != NULL) { 1411 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1412 dma->idi_vaddr = NULL; 1413 } 1414 bus_dma_tag_destroy(dma->idi_tag); 1415 dma->idi_tag = NULL; 1416 } 1417 1418 void 1419 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1420 { 1421 int i; 1422 iflib_dma_info_t *dmaiter = dmalist; 1423 1424 for (i = 0; i < count; i++, dmaiter++) 1425 iflib_dma_free(*dmaiter); 1426 } 1427 1428 #ifdef EARLY_AP_STARTUP 1429 static const int iflib_started = 1; 1430 #else 1431 /* 1432 * We used to abuse the smp_started flag to decide if the queues have been 1433 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1434 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1435 * is set. Run a SYSINIT() strictly after that to just set a usable 1436 * completion flag. 1437 */ 1438 1439 static int iflib_started; 1440 1441 static void 1442 iflib_record_started(void *arg) 1443 { 1444 iflib_started = 1; 1445 } 1446 1447 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1448 iflib_record_started, NULL); 1449 #endif 1450 1451 static int 1452 iflib_fast_intr(void *arg) 1453 { 1454 iflib_filter_info_t info = arg; 1455 struct grouptask *gtask = info->ifi_task; 1456 if (!iflib_started) 1457 return (FILTER_HANDLED); 1458 1459 DBG_COUNTER_INC(fast_intrs); 1460 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1461 return (FILTER_HANDLED); 1462 1463 GROUPTASK_ENQUEUE(gtask); 1464 return (FILTER_HANDLED); 1465 } 1466 1467 static int 1468 iflib_fast_intr_rxtx(void *arg) 1469 { 1470 iflib_filter_info_t info = arg; 1471 struct grouptask *gtask = info->ifi_task; 1472 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1473 if_ctx_t ctx = NULL;; 1474 int i, cidx; 1475 1476 if (!iflib_started) 1477 return (FILTER_HANDLED); 1478 1479 DBG_COUNTER_INC(fast_intrs); 1480 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1481 return (FILTER_HANDLED); 1482 1483 MPASS(rxq->ifr_ntxqirq); 1484 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1485 qidx_t txqid = rxq->ifr_txqid[i]; 1486 1487 ctx = rxq->ifr_ctx; 1488 1489 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1490 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1491 continue; 1492 } 1493 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1494 } 1495 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1496 cidx = rxq->ifr_cq_cidx; 1497 else 1498 cidx = rxq->ifr_fl[0].ifl_cidx; 1499 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1500 GROUPTASK_ENQUEUE(gtask); 1501 else 1502 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1503 return (FILTER_HANDLED); 1504 } 1505 1506 1507 static int 1508 iflib_fast_intr_ctx(void *arg) 1509 { 1510 iflib_filter_info_t info = arg; 1511 struct grouptask *gtask = info->ifi_task; 1512 1513 if (!iflib_started) 1514 return (FILTER_HANDLED); 1515 1516 DBG_COUNTER_INC(fast_intrs); 1517 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1518 return (FILTER_HANDLED); 1519 1520 GROUPTASK_ENQUEUE(gtask); 1521 return (FILTER_HANDLED); 1522 } 1523 1524 static int 1525 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1526 driver_filter_t filter, driver_intr_t handler, void *arg, 1527 const char *name) 1528 { 1529 int rc, flags; 1530 struct resource *res; 1531 void *tag = NULL; 1532 device_t dev = ctx->ifc_dev; 1533 1534 flags = RF_ACTIVE; 1535 if (ctx->ifc_flags & IFC_LEGACY) 1536 flags |= RF_SHAREABLE; 1537 MPASS(rid < 512); 1538 irq->ii_rid = rid; 1539 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1540 if (res == NULL) { 1541 device_printf(dev, 1542 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1543 return (ENOMEM); 1544 } 1545 irq->ii_res = res; 1546 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1547 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1548 filter, handler, arg, &tag); 1549 if (rc != 0) { 1550 device_printf(dev, 1551 "failed to setup interrupt for rid %d, name %s: %d\n", 1552 rid, name ? name : "unknown", rc); 1553 return (rc); 1554 } else if (name) 1555 bus_describe_intr(dev, res, tag, "%s", name); 1556 1557 irq->ii_tag = tag; 1558 return (0); 1559 } 1560 1561 1562 /********************************************************************* 1563 * 1564 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1565 * the information needed to transmit a packet on the wire. This is 1566 * called only once at attach, setup is done every reset. 1567 * 1568 **********************************************************************/ 1569 1570 static int 1571 iflib_txsd_alloc(iflib_txq_t txq) 1572 { 1573 if_ctx_t ctx = txq->ift_ctx; 1574 if_shared_ctx_t sctx = ctx->ifc_sctx; 1575 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1576 device_t dev = ctx->ifc_dev; 1577 bus_size_t tsomaxsize; 1578 int err, nsegments, ntsosegments; 1579 1580 nsegments = scctx->isc_tx_nsegments; 1581 ntsosegments = scctx->isc_tx_tso_segments_max; 1582 tsomaxsize = scctx->isc_tx_tso_size_max; 1583 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1584 tsomaxsize += sizeof(struct ether_vlan_header); 1585 MPASS(scctx->isc_ntxd[0] > 0); 1586 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1587 MPASS(nsegments > 0); 1588 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1589 MPASS(ntsosegments > 0); 1590 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1591 } 1592 1593 /* 1594 * Setup DMA descriptor areas. 1595 */ 1596 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1597 1, 0, /* alignment, bounds */ 1598 BUS_SPACE_MAXADDR, /* lowaddr */ 1599 BUS_SPACE_MAXADDR, /* highaddr */ 1600 NULL, NULL, /* filter, filterarg */ 1601 sctx->isc_tx_maxsize, /* maxsize */ 1602 nsegments, /* nsegments */ 1603 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1604 0, /* flags */ 1605 NULL, /* lockfunc */ 1606 NULL, /* lockfuncarg */ 1607 &txq->ift_desc_tag))) { 1608 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1609 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1610 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1611 goto fail; 1612 } 1613 if ((if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) & 1614 (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1615 1, 0, /* alignment, bounds */ 1616 BUS_SPACE_MAXADDR, /* lowaddr */ 1617 BUS_SPACE_MAXADDR, /* highaddr */ 1618 NULL, NULL, /* filter, filterarg */ 1619 tsomaxsize, /* maxsize */ 1620 ntsosegments, /* nsegments */ 1621 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1622 0, /* flags */ 1623 NULL, /* lockfunc */ 1624 NULL, /* lockfuncarg */ 1625 &txq->ift_tso_desc_tag))) { 1626 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1627 1628 goto fail; 1629 } 1630 if (!(txq->ift_sds.ifsd_flags = 1631 (uint8_t *) malloc(sizeof(uint8_t) * 1632 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1633 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1634 err = ENOMEM; 1635 goto fail; 1636 } 1637 if (!(txq->ift_sds.ifsd_m = 1638 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1639 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1640 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1641 err = ENOMEM; 1642 goto fail; 1643 } 1644 1645 /* Create the descriptor buffer dma maps */ 1646 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1647 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1648 return (0); 1649 1650 if (!(txq->ift_sds.ifsd_map = 1651 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1652 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1653 err = ENOMEM; 1654 goto fail; 1655 } 1656 1657 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1658 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1659 if (err != 0) { 1660 device_printf(dev, "Unable to create TX DMA map\n"); 1661 goto fail; 1662 } 1663 } 1664 #endif 1665 return (0); 1666 fail: 1667 /* We free all, it handles case where we are in the middle */ 1668 iflib_tx_structures_free(ctx); 1669 return (err); 1670 } 1671 1672 static void 1673 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1674 { 1675 bus_dmamap_t map; 1676 1677 map = NULL; 1678 if (txq->ift_sds.ifsd_map != NULL) 1679 map = txq->ift_sds.ifsd_map[i]; 1680 if (map != NULL) { 1681 bus_dmamap_unload(txq->ift_desc_tag, map); 1682 bus_dmamap_destroy(txq->ift_desc_tag, map); 1683 txq->ift_sds.ifsd_map[i] = NULL; 1684 } 1685 } 1686 1687 static void 1688 iflib_txq_destroy(iflib_txq_t txq) 1689 { 1690 if_ctx_t ctx = txq->ift_ctx; 1691 1692 for (int i = 0; i < txq->ift_size; i++) 1693 iflib_txsd_destroy(ctx, txq, i); 1694 if (txq->ift_sds.ifsd_map != NULL) { 1695 free(txq->ift_sds.ifsd_map, M_IFLIB); 1696 txq->ift_sds.ifsd_map = NULL; 1697 } 1698 if (txq->ift_sds.ifsd_m != NULL) { 1699 free(txq->ift_sds.ifsd_m, M_IFLIB); 1700 txq->ift_sds.ifsd_m = NULL; 1701 } 1702 if (txq->ift_sds.ifsd_flags != NULL) { 1703 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1704 txq->ift_sds.ifsd_flags = NULL; 1705 } 1706 if (txq->ift_desc_tag != NULL) { 1707 bus_dma_tag_destroy(txq->ift_desc_tag); 1708 txq->ift_desc_tag = NULL; 1709 } 1710 if (txq->ift_tso_desc_tag != NULL) { 1711 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1712 txq->ift_tso_desc_tag = NULL; 1713 } 1714 } 1715 1716 static void 1717 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1718 { 1719 struct mbuf **mp; 1720 1721 mp = &txq->ift_sds.ifsd_m[i]; 1722 if (*mp == NULL) 1723 return; 1724 1725 if (txq->ift_sds.ifsd_map != NULL) { 1726 bus_dmamap_sync(txq->ift_desc_tag, 1727 txq->ift_sds.ifsd_map[i], 1728 BUS_DMASYNC_POSTWRITE); 1729 bus_dmamap_unload(txq->ift_desc_tag, 1730 txq->ift_sds.ifsd_map[i]); 1731 } 1732 m_free(*mp); 1733 DBG_COUNTER_INC(tx_frees); 1734 *mp = NULL; 1735 } 1736 1737 static int 1738 iflib_txq_setup(iflib_txq_t txq) 1739 { 1740 if_ctx_t ctx = txq->ift_ctx; 1741 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1742 iflib_dma_info_t di; 1743 int i; 1744 1745 /* Set number of descriptors available */ 1746 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1747 /* XXX make configurable */ 1748 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1749 1750 /* Reset indices */ 1751 txq->ift_cidx_processed = 0; 1752 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1753 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1754 1755 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1756 bzero((void *)di->idi_vaddr, di->idi_size); 1757 1758 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1759 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1760 bus_dmamap_sync(di->idi_tag, di->idi_map, 1761 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1762 return (0); 1763 } 1764 1765 /********************************************************************* 1766 * 1767 * Allocate memory for rx_buffer structures. Since we use one 1768 * rx_buffer per received packet, the maximum number of rx_buffer's 1769 * that we'll need is equal to the number of receive descriptors 1770 * that we've allocated. 1771 * 1772 **********************************************************************/ 1773 static int 1774 iflib_rxsd_alloc(iflib_rxq_t rxq) 1775 { 1776 if_ctx_t ctx = rxq->ifr_ctx; 1777 if_shared_ctx_t sctx = ctx->ifc_sctx; 1778 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1779 device_t dev = ctx->ifc_dev; 1780 iflib_fl_t fl; 1781 int err; 1782 1783 MPASS(scctx->isc_nrxd[0] > 0); 1784 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1785 1786 fl = rxq->ifr_fl; 1787 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1788 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1789 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1790 1, 0, /* alignment, bounds */ 1791 BUS_SPACE_MAXADDR, /* lowaddr */ 1792 BUS_SPACE_MAXADDR, /* highaddr */ 1793 NULL, NULL, /* filter, filterarg */ 1794 sctx->isc_rx_maxsize, /* maxsize */ 1795 sctx->isc_rx_nsegments, /* nsegments */ 1796 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1797 0, /* flags */ 1798 NULL, /* lockfunc */ 1799 NULL, /* lockarg */ 1800 &fl->ifl_desc_tag); 1801 if (err) { 1802 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1803 __func__, err); 1804 goto fail; 1805 } 1806 if (!(fl->ifl_sds.ifsd_flags = 1807 (uint8_t *) malloc(sizeof(uint8_t) * 1808 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1809 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1810 err = ENOMEM; 1811 goto fail; 1812 } 1813 if (!(fl->ifl_sds.ifsd_m = 1814 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1815 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1816 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1817 err = ENOMEM; 1818 goto fail; 1819 } 1820 if (!(fl->ifl_sds.ifsd_cl = 1821 (caddr_t *) malloc(sizeof(caddr_t) * 1822 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1823 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1824 err = ENOMEM; 1825 goto fail; 1826 } 1827 1828 /* Create the descriptor buffer dma maps */ 1829 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1830 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1831 continue; 1832 1833 if (!(fl->ifl_sds.ifsd_map = 1834 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1835 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1836 err = ENOMEM; 1837 goto fail; 1838 } 1839 1840 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1841 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1842 if (err != 0) { 1843 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1844 goto fail; 1845 } 1846 } 1847 #endif 1848 } 1849 return (0); 1850 1851 fail: 1852 iflib_rx_structures_free(ctx); 1853 return (err); 1854 } 1855 1856 1857 /* 1858 * Internal service routines 1859 */ 1860 1861 struct rxq_refill_cb_arg { 1862 int error; 1863 bus_dma_segment_t seg; 1864 int nseg; 1865 }; 1866 1867 static void 1868 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1869 { 1870 struct rxq_refill_cb_arg *cb_arg = arg; 1871 1872 cb_arg->error = error; 1873 cb_arg->seg = segs[0]; 1874 cb_arg->nseg = nseg; 1875 } 1876 1877 1878 #ifdef ACPI_DMAR 1879 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1880 #else 1881 #define IS_DMAR(ctx) (0) 1882 #endif 1883 1884 /** 1885 * rxq_refill - refill an rxq free-buffer list 1886 * @ctx: the iflib context 1887 * @rxq: the free-list to refill 1888 * @n: the number of new buffers to allocate 1889 * 1890 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1891 * The caller must assure that @n does not exceed the queue's capacity. 1892 */ 1893 static void 1894 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1895 { 1896 struct mbuf *m; 1897 int idx, frag_idx = fl->ifl_fragidx; 1898 int pidx = fl->ifl_pidx; 1899 caddr_t cl, *sd_cl; 1900 struct mbuf **sd_m; 1901 uint8_t *sd_flags; 1902 struct if_rxd_update iru; 1903 bus_dmamap_t *sd_map; 1904 int n, i = 0; 1905 uint64_t bus_addr; 1906 int err; 1907 qidx_t credits; 1908 1909 sd_m = fl->ifl_sds.ifsd_m; 1910 sd_map = fl->ifl_sds.ifsd_map; 1911 sd_cl = fl->ifl_sds.ifsd_cl; 1912 sd_flags = fl->ifl_sds.ifsd_flags; 1913 idx = pidx; 1914 credits = fl->ifl_credits; 1915 1916 n = count; 1917 MPASS(n > 0); 1918 MPASS(credits + n <= fl->ifl_size); 1919 1920 if (pidx < fl->ifl_cidx) 1921 MPASS(pidx + n <= fl->ifl_cidx); 1922 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1923 MPASS(fl->ifl_gen == 0); 1924 if (pidx > fl->ifl_cidx) 1925 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1926 1927 DBG_COUNTER_INC(fl_refills); 1928 if (n > 8) 1929 DBG_COUNTER_INC(fl_refills_large); 1930 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1931 while (n--) { 1932 /* 1933 * We allocate an uninitialized mbuf + cluster, mbuf is 1934 * initialized after rx. 1935 * 1936 * If the cluster is still set then we know a minimum sized packet was received 1937 */ 1938 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1939 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1940 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1941 if ((cl = sd_cl[frag_idx]) == NULL) { 1942 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1943 break; 1944 #if MEMORY_LOGGING 1945 fl->ifl_cl_enqueued++; 1946 #endif 1947 } 1948 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1949 break; 1950 } 1951 #if MEMORY_LOGGING 1952 fl->ifl_m_enqueued++; 1953 #endif 1954 1955 DBG_COUNTER_INC(rx_allocs); 1956 #if defined(__i386__) || defined(__amd64__) 1957 if (!IS_DMAR(ctx)) { 1958 bus_addr = pmap_kextract((vm_offset_t)cl); 1959 } else 1960 #endif 1961 { 1962 struct rxq_refill_cb_arg cb_arg; 1963 1964 cb_arg.error = 0; 1965 MPASS(sd_map != NULL); 1966 MPASS(sd_map[frag_idx] != NULL); 1967 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1968 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1969 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 1970 BUS_DMASYNC_PREREAD); 1971 1972 if (err != 0 || cb_arg.error) { 1973 /* 1974 * !zone_pack ? 1975 */ 1976 if (fl->ifl_zone == zone_pack) 1977 uma_zfree(fl->ifl_zone, cl); 1978 m_free(m); 1979 n = 0; 1980 goto done; 1981 } 1982 bus_addr = cb_arg.seg.ds_addr; 1983 } 1984 bit_set(fl->ifl_rx_bitmap, frag_idx); 1985 sd_flags[frag_idx] |= RX_SW_DESC_INUSE; 1986 1987 MPASS(sd_m[frag_idx] == NULL); 1988 sd_cl[frag_idx] = cl; 1989 sd_m[frag_idx] = m; 1990 fl->ifl_rxd_idxs[i] = frag_idx; 1991 fl->ifl_bus_addrs[i] = bus_addr; 1992 fl->ifl_vm_addrs[i] = cl; 1993 credits++; 1994 i++; 1995 MPASS(credits <= fl->ifl_size); 1996 if (++idx == fl->ifl_size) { 1997 fl->ifl_gen = 1; 1998 idx = 0; 1999 } 2000 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2001 iru.iru_pidx = pidx; 2002 iru.iru_count = i; 2003 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2004 i = 0; 2005 pidx = idx; 2006 fl->ifl_pidx = idx; 2007 fl->ifl_credits = credits; 2008 } 2009 2010 } 2011 done: 2012 if (i) { 2013 iru.iru_pidx = pidx; 2014 iru.iru_count = i; 2015 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2016 fl->ifl_pidx = idx; 2017 fl->ifl_credits = credits; 2018 } 2019 DBG_COUNTER_INC(rxd_flush); 2020 if (fl->ifl_pidx == 0) 2021 pidx = fl->ifl_size - 1; 2022 else 2023 pidx = fl->ifl_pidx - 1; 2024 2025 if (sd_map) 2026 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2027 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2028 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2029 fl->ifl_fragidx = frag_idx; 2030 } 2031 2032 static __inline void 2033 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2034 { 2035 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2036 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2037 #ifdef INVARIANTS 2038 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2039 #endif 2040 2041 MPASS(fl->ifl_credits <= fl->ifl_size); 2042 MPASS(reclaimable == delta); 2043 2044 if (reclaimable > 0) 2045 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2046 } 2047 2048 static void 2049 iflib_fl_bufs_free(iflib_fl_t fl) 2050 { 2051 iflib_dma_info_t idi = fl->ifl_ifdi; 2052 uint32_t i; 2053 2054 for (i = 0; i < fl->ifl_size; i++) { 2055 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2056 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 2057 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2058 2059 if (*sd_flags & RX_SW_DESC_INUSE) { 2060 if (fl->ifl_sds.ifsd_map != NULL) { 2061 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 2062 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 2063 if (fl->ifl_rxq->ifr_ctx->ifc_in_detach) 2064 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 2065 } 2066 if (*sd_m != NULL) { 2067 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2068 uma_zfree(zone_mbuf, *sd_m); 2069 } 2070 if (*sd_cl != NULL) 2071 uma_zfree(fl->ifl_zone, *sd_cl); 2072 *sd_flags = 0; 2073 } else { 2074 MPASS(*sd_cl == NULL); 2075 MPASS(*sd_m == NULL); 2076 } 2077 #if MEMORY_LOGGING 2078 fl->ifl_m_dequeued++; 2079 fl->ifl_cl_dequeued++; 2080 #endif 2081 *sd_cl = NULL; 2082 *sd_m = NULL; 2083 } 2084 #ifdef INVARIANTS 2085 for (i = 0; i < fl->ifl_size; i++) { 2086 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 2087 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2088 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2089 } 2090 #endif 2091 /* 2092 * Reset free list values 2093 */ 2094 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2095 bzero(idi->idi_vaddr, idi->idi_size); 2096 } 2097 2098 /********************************************************************* 2099 * 2100 * Initialize a receive ring and its buffers. 2101 * 2102 **********************************************************************/ 2103 static int 2104 iflib_fl_setup(iflib_fl_t fl) 2105 { 2106 iflib_rxq_t rxq = fl->ifl_rxq; 2107 if_ctx_t ctx = rxq->ifr_ctx; 2108 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2109 2110 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2111 /* 2112 ** Free current RX buffer structs and their mbufs 2113 */ 2114 iflib_fl_bufs_free(fl); 2115 /* Now replenish the mbufs */ 2116 MPASS(fl->ifl_credits == 0); 2117 /* 2118 * XXX don't set the max_frame_size to larger 2119 * than the hardware can handle 2120 */ 2121 if (sctx->isc_max_frame_size <= 2048) 2122 fl->ifl_buf_size = MCLBYTES; 2123 #ifndef CONTIGMALLOC_WORKS 2124 else 2125 fl->ifl_buf_size = MJUMPAGESIZE; 2126 #else 2127 else if (sctx->isc_max_frame_size <= 4096) 2128 fl->ifl_buf_size = MJUMPAGESIZE; 2129 else if (sctx->isc_max_frame_size <= 9216) 2130 fl->ifl_buf_size = MJUM9BYTES; 2131 else 2132 fl->ifl_buf_size = MJUM16BYTES; 2133 #endif 2134 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2135 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2136 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2137 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2138 2139 2140 /* avoid pre-allocating zillions of clusters to an idle card 2141 * potentially speeding up attach 2142 */ 2143 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2144 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2145 if (min(128, fl->ifl_size) != fl->ifl_credits) 2146 return (ENOBUFS); 2147 /* 2148 * handle failure 2149 */ 2150 MPASS(rxq != NULL); 2151 MPASS(fl->ifl_ifdi != NULL); 2152 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2153 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2154 return (0); 2155 } 2156 2157 /********************************************************************* 2158 * 2159 * Free receive ring data structures 2160 * 2161 **********************************************************************/ 2162 static void 2163 iflib_rx_sds_free(iflib_rxq_t rxq) 2164 { 2165 iflib_fl_t fl; 2166 int i; 2167 2168 if (rxq->ifr_fl != NULL) { 2169 for (i = 0; i < rxq->ifr_nfl; i++) { 2170 fl = &rxq->ifr_fl[i]; 2171 if (fl->ifl_desc_tag != NULL) { 2172 bus_dma_tag_destroy(fl->ifl_desc_tag); 2173 fl->ifl_desc_tag = NULL; 2174 } 2175 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2176 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2177 /* XXX destroy maps first */ 2178 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2179 fl->ifl_sds.ifsd_m = NULL; 2180 fl->ifl_sds.ifsd_cl = NULL; 2181 fl->ifl_sds.ifsd_map = NULL; 2182 } 2183 free(rxq->ifr_fl, M_IFLIB); 2184 rxq->ifr_fl = NULL; 2185 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2186 } 2187 } 2188 2189 /* 2190 * MI independent logic 2191 * 2192 */ 2193 static void 2194 iflib_timer(void *arg) 2195 { 2196 iflib_txq_t txq = arg; 2197 if_ctx_t ctx = txq->ift_ctx; 2198 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2199 2200 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2201 return; 2202 /* 2203 ** Check on the state of the TX queue(s), this 2204 ** can be done without the lock because its RO 2205 ** and the HUNG state will be static if set. 2206 */ 2207 IFDI_TIMER(ctx, txq->ift_id); 2208 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2209 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2210 (sctx->isc_pause_frames == 0))) 2211 goto hung; 2212 2213 if (ifmp_ring_is_stalled(txq->ift_br)) 2214 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2215 txq->ift_cleaned_prev = txq->ift_cleaned; 2216 /* handle any laggards */ 2217 if (txq->ift_db_pending) 2218 GROUPTASK_ENQUEUE(&txq->ift_task); 2219 2220 sctx->isc_pause_frames = 0; 2221 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2222 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 2223 return; 2224 hung: 2225 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2226 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2227 STATE_LOCK(ctx); 2228 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2229 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2230 iflib_admin_intr_deferred(ctx); 2231 STATE_UNLOCK(ctx); 2232 } 2233 2234 static void 2235 iflib_init_locked(if_ctx_t ctx) 2236 { 2237 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2238 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2239 if_t ifp = ctx->ifc_ifp; 2240 iflib_fl_t fl; 2241 iflib_txq_t txq; 2242 iflib_rxq_t rxq; 2243 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2244 2245 2246 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2247 IFDI_INTR_DISABLE(ctx); 2248 2249 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2250 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2251 /* Set hardware offload abilities */ 2252 if_clearhwassist(ifp); 2253 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2254 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2255 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2256 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2257 if (if_getcapenable(ifp) & IFCAP_TSO4) 2258 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2259 if (if_getcapenable(ifp) & IFCAP_TSO6) 2260 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2261 2262 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2263 CALLOUT_LOCK(txq); 2264 callout_stop(&txq->ift_timer); 2265 CALLOUT_UNLOCK(txq); 2266 iflib_netmap_txq_init(ctx, txq); 2267 } 2268 #ifdef INVARIANTS 2269 i = if_getdrvflags(ifp); 2270 #endif 2271 IFDI_INIT(ctx); 2272 MPASS(if_getdrvflags(ifp) == i); 2273 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2274 /* XXX this should really be done on a per-queue basis */ 2275 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2276 MPASS(rxq->ifr_id == i); 2277 iflib_netmap_rxq_init(ctx, rxq); 2278 continue; 2279 } 2280 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2281 if (iflib_fl_setup(fl)) { 2282 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2283 goto done; 2284 } 2285 } 2286 } 2287 done: 2288 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2289 IFDI_INTR_ENABLE(ctx); 2290 txq = ctx->ifc_txqs; 2291 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2292 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2293 txq->ift_timer.c_cpu); 2294 } 2295 2296 static int 2297 iflib_media_change(if_t ifp) 2298 { 2299 if_ctx_t ctx = if_getsoftc(ifp); 2300 int err; 2301 2302 CTX_LOCK(ctx); 2303 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2304 iflib_init_locked(ctx); 2305 CTX_UNLOCK(ctx); 2306 return (err); 2307 } 2308 2309 static void 2310 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2311 { 2312 if_ctx_t ctx = if_getsoftc(ifp); 2313 2314 CTX_LOCK(ctx); 2315 IFDI_UPDATE_ADMIN_STATUS(ctx); 2316 IFDI_MEDIA_STATUS(ctx, ifmr); 2317 CTX_UNLOCK(ctx); 2318 } 2319 2320 void 2321 iflib_stop(if_ctx_t ctx) 2322 { 2323 iflib_txq_t txq = ctx->ifc_txqs; 2324 iflib_rxq_t rxq = ctx->ifc_rxqs; 2325 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2326 iflib_dma_info_t di; 2327 iflib_fl_t fl; 2328 int i, j; 2329 2330 /* Tell the stack that the interface is no longer active */ 2331 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2332 2333 IFDI_INTR_DISABLE(ctx); 2334 DELAY(1000); 2335 IFDI_STOP(ctx); 2336 DELAY(1000); 2337 2338 iflib_debug_reset(); 2339 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2340 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2341 /* make sure all transmitters have completed before proceeding XXX */ 2342 2343 CALLOUT_LOCK(txq); 2344 callout_stop(&txq->ift_timer); 2345 CALLOUT_UNLOCK(txq); 2346 2347 /* clean any enqueued buffers */ 2348 iflib_ifmp_purge(txq); 2349 /* Free any existing tx buffers. */ 2350 for (j = 0; j < txq->ift_size; j++) { 2351 iflib_txsd_free(ctx, txq, j); 2352 } 2353 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2354 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2355 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2356 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2357 txq->ift_pullups = 0; 2358 ifmp_ring_reset_stats(txq->ift_br); 2359 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2360 bzero((void *)di->idi_vaddr, di->idi_size); 2361 } 2362 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2363 /* make sure all transmitters have completed before proceeding XXX */ 2364 2365 for (j = 0, di = rxq->ifr_ifdi; j < rxq->ifr_nfl; j++, di++) 2366 bzero((void *)di->idi_vaddr, di->idi_size); 2367 /* also resets the free lists pidx/cidx */ 2368 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2369 iflib_fl_bufs_free(fl); 2370 } 2371 } 2372 2373 static inline caddr_t 2374 calc_next_rxd(iflib_fl_t fl, int cidx) 2375 { 2376 qidx_t size; 2377 int nrxd; 2378 caddr_t start, end, cur, next; 2379 2380 nrxd = fl->ifl_size; 2381 size = fl->ifl_rxd_size; 2382 start = fl->ifl_ifdi->idi_vaddr; 2383 2384 if (__predict_false(size == 0)) 2385 return (start); 2386 cur = start + size*cidx; 2387 end = start + size*nrxd; 2388 next = CACHE_PTR_NEXT(cur); 2389 return (next < end ? next : start); 2390 } 2391 2392 static inline void 2393 prefetch_pkts(iflib_fl_t fl, int cidx) 2394 { 2395 int nextptr; 2396 int nrxd = fl->ifl_size; 2397 caddr_t next_rxd; 2398 2399 2400 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2401 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2402 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2403 next_rxd = calc_next_rxd(fl, cidx); 2404 prefetch(next_rxd); 2405 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2406 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2407 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2408 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2409 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2410 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2411 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2412 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2413 } 2414 2415 static void 2416 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2417 { 2418 int flid, cidx; 2419 bus_dmamap_t map; 2420 iflib_fl_t fl; 2421 iflib_dma_info_t di; 2422 int next; 2423 2424 map = NULL; 2425 flid = irf->irf_flid; 2426 cidx = irf->irf_idx; 2427 fl = &rxq->ifr_fl[flid]; 2428 sd->ifsd_fl = fl; 2429 sd->ifsd_cidx = cidx; 2430 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2431 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2432 fl->ifl_credits--; 2433 #if MEMORY_LOGGING 2434 fl->ifl_m_dequeued++; 2435 #endif 2436 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2437 prefetch_pkts(fl, cidx); 2438 if (fl->ifl_sds.ifsd_map != NULL) { 2439 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2440 prefetch(&fl->ifl_sds.ifsd_map[next]); 2441 map = fl->ifl_sds.ifsd_map[cidx]; 2442 di = fl->ifl_ifdi; 2443 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2444 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2445 bus_dmamap_sync(di->idi_tag, di->idi_map, 2446 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2447 2448 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2449 MPASS(fl->ifl_cidx == cidx); 2450 if (unload) 2451 bus_dmamap_unload(fl->ifl_desc_tag, map); 2452 } 2453 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2454 if (__predict_false(fl->ifl_cidx == 0)) 2455 fl->ifl_gen = 0; 2456 if (map != NULL) 2457 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2458 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2459 bit_clear(fl->ifl_rx_bitmap, cidx); 2460 } 2461 2462 static struct mbuf * 2463 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2464 { 2465 int i, padlen , flags; 2466 struct mbuf *m, *mh, *mt; 2467 caddr_t cl; 2468 2469 i = 0; 2470 mh = NULL; 2471 do { 2472 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2473 2474 MPASS(*sd->ifsd_cl != NULL); 2475 MPASS(*sd->ifsd_m != NULL); 2476 2477 /* Don't include zero-length frags */ 2478 if (ri->iri_frags[i].irf_len == 0) { 2479 /* XXX we can save the cluster here, but not the mbuf */ 2480 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2481 m_free(*sd->ifsd_m); 2482 *sd->ifsd_m = NULL; 2483 continue; 2484 } 2485 m = *sd->ifsd_m; 2486 *sd->ifsd_m = NULL; 2487 if (mh == NULL) { 2488 flags = M_PKTHDR|M_EXT; 2489 mh = mt = m; 2490 padlen = ri->iri_pad; 2491 } else { 2492 flags = M_EXT; 2493 mt->m_next = m; 2494 mt = m; 2495 /* assuming padding is only on the first fragment */ 2496 padlen = 0; 2497 } 2498 cl = *sd->ifsd_cl; 2499 *sd->ifsd_cl = NULL; 2500 2501 /* Can these two be made one ? */ 2502 m_init(m, M_NOWAIT, MT_DATA, flags); 2503 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2504 /* 2505 * These must follow m_init and m_cljset 2506 */ 2507 m->m_data += padlen; 2508 ri->iri_len -= padlen; 2509 m->m_len = ri->iri_frags[i].irf_len; 2510 } while (++i < ri->iri_nfrags); 2511 2512 return (mh); 2513 } 2514 2515 /* 2516 * Process one software descriptor 2517 */ 2518 static struct mbuf * 2519 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2520 { 2521 struct if_rxsd sd; 2522 struct mbuf *m; 2523 2524 /* should I merge this back in now that the two paths are basically duplicated? */ 2525 if (ri->iri_nfrags == 1 && 2526 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2527 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2528 m = *sd.ifsd_m; 2529 *sd.ifsd_m = NULL; 2530 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2531 #ifndef __NO_STRICT_ALIGNMENT 2532 if (!IP_ALIGNED(m)) 2533 m->m_data += 2; 2534 #endif 2535 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2536 m->m_len = ri->iri_frags[0].irf_len; 2537 } else { 2538 m = assemble_segments(rxq, ri, &sd); 2539 } 2540 m->m_pkthdr.len = ri->iri_len; 2541 m->m_pkthdr.rcvif = ri->iri_ifp; 2542 m->m_flags |= ri->iri_flags; 2543 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2544 m->m_pkthdr.flowid = ri->iri_flowid; 2545 M_HASHTYPE_SET(m, ri->iri_rsstype); 2546 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2547 m->m_pkthdr.csum_data = ri->iri_csum_data; 2548 return (m); 2549 } 2550 2551 #if defined(INET6) || defined(INET) 2552 static void 2553 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2554 { 2555 CURVNET_SET(lc->ifp->if_vnet); 2556 #if defined(INET6) 2557 *v6 = VNET(ip6_forwarding); 2558 #endif 2559 #if defined(INET) 2560 *v4 = VNET(ipforwarding); 2561 #endif 2562 CURVNET_RESTORE(); 2563 } 2564 2565 /* 2566 * Returns true if it's possible this packet could be LROed. 2567 * if it returns false, it is guaranteed that tcp_lro_rx() 2568 * would not return zero. 2569 */ 2570 static bool 2571 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2572 { 2573 struct ether_header *eh; 2574 uint16_t eh_type; 2575 2576 eh = mtod(m, struct ether_header *); 2577 eh_type = ntohs(eh->ether_type); 2578 switch (eh_type) { 2579 #if defined(INET6) 2580 case ETHERTYPE_IPV6: 2581 return !v6_forwarding; 2582 #endif 2583 #if defined (INET) 2584 case ETHERTYPE_IP: 2585 return !v4_forwarding; 2586 #endif 2587 } 2588 2589 return false; 2590 } 2591 #else 2592 static void 2593 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2594 { 2595 } 2596 #endif 2597 2598 static bool 2599 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2600 { 2601 if_ctx_t ctx = rxq->ifr_ctx; 2602 if_shared_ctx_t sctx = ctx->ifc_sctx; 2603 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2604 int avail, i; 2605 qidx_t *cidxp; 2606 struct if_rxd_info ri; 2607 int err, budget_left, rx_bytes, rx_pkts; 2608 iflib_fl_t fl; 2609 struct ifnet *ifp; 2610 int lro_enabled; 2611 bool v4_forwarding, v6_forwarding, lro_possible; 2612 2613 /* 2614 * XXX early demux data packets so that if_input processing only handles 2615 * acks in interrupt context 2616 */ 2617 struct mbuf *m, *mh, *mt, *mf; 2618 2619 lro_possible = v4_forwarding = v6_forwarding = false; 2620 ifp = ctx->ifc_ifp; 2621 mh = mt = NULL; 2622 MPASS(budget > 0); 2623 rx_pkts = rx_bytes = 0; 2624 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2625 cidxp = &rxq->ifr_cq_cidx; 2626 else 2627 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2628 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2629 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2630 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2631 DBG_COUNTER_INC(rx_unavail); 2632 return (false); 2633 } 2634 2635 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2636 if (__predict_false(!CTX_ACTIVE(ctx))) { 2637 DBG_COUNTER_INC(rx_ctx_inactive); 2638 break; 2639 } 2640 /* 2641 * Reset client set fields to their default values 2642 */ 2643 rxd_info_zero(&ri); 2644 ri.iri_qsidx = rxq->ifr_id; 2645 ri.iri_cidx = *cidxp; 2646 ri.iri_ifp = ifp; 2647 ri.iri_frags = rxq->ifr_frags; 2648 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2649 2650 if (err) 2651 goto err; 2652 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2653 *cidxp = ri.iri_cidx; 2654 /* Update our consumer index */ 2655 /* XXX NB: shurd - check if this is still safe */ 2656 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2657 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2658 rxq->ifr_cq_gen = 0; 2659 } 2660 /* was this only a completion queue message? */ 2661 if (__predict_false(ri.iri_nfrags == 0)) 2662 continue; 2663 } 2664 MPASS(ri.iri_nfrags != 0); 2665 MPASS(ri.iri_len != 0); 2666 2667 /* will advance the cidx on the corresponding free lists */ 2668 m = iflib_rxd_pkt_get(rxq, &ri); 2669 if (avail == 0 && budget_left) 2670 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2671 2672 if (__predict_false(m == NULL)) { 2673 DBG_COUNTER_INC(rx_mbuf_null); 2674 continue; 2675 } 2676 /* imm_pkt: -- cxgb */ 2677 if (mh == NULL) 2678 mh = mt = m; 2679 else { 2680 mt->m_nextpkt = m; 2681 mt = m; 2682 } 2683 } 2684 /* make sure that we can refill faster than drain */ 2685 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2686 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2687 2688 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2689 if (lro_enabled) 2690 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2691 mt = mf = NULL; 2692 while (mh != NULL) { 2693 m = mh; 2694 mh = mh->m_nextpkt; 2695 m->m_nextpkt = NULL; 2696 #ifndef __NO_STRICT_ALIGNMENT 2697 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2698 continue; 2699 #endif 2700 rx_bytes += m->m_pkthdr.len; 2701 rx_pkts++; 2702 #if defined(INET6) || defined(INET) 2703 if (lro_enabled) { 2704 if (!lro_possible) { 2705 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2706 if (lro_possible && mf != NULL) { 2707 ifp->if_input(ifp, mf); 2708 DBG_COUNTER_INC(rx_if_input); 2709 mt = mf = NULL; 2710 } 2711 } 2712 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2713 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2714 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2715 continue; 2716 } 2717 } 2718 #endif 2719 if (lro_possible) { 2720 ifp->if_input(ifp, m); 2721 DBG_COUNTER_INC(rx_if_input); 2722 continue; 2723 } 2724 2725 if (mf == NULL) 2726 mf = m; 2727 if (mt != NULL) 2728 mt->m_nextpkt = m; 2729 mt = m; 2730 } 2731 if (mf != NULL) { 2732 ifp->if_input(ifp, mf); 2733 DBG_COUNTER_INC(rx_if_input); 2734 } 2735 2736 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2737 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2738 2739 /* 2740 * Flush any outstanding LRO work 2741 */ 2742 #if defined(INET6) || defined(INET) 2743 tcp_lro_flush_all(&rxq->ifr_lc); 2744 #endif 2745 if (avail) 2746 return true; 2747 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2748 err: 2749 STATE_LOCK(ctx); 2750 ctx->ifc_flags |= IFC_DO_RESET; 2751 iflib_admin_intr_deferred(ctx); 2752 STATE_UNLOCK(ctx); 2753 return (false); 2754 } 2755 2756 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2757 static inline qidx_t 2758 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2759 { 2760 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2761 qidx_t minthresh = txq->ift_size / 8; 2762 if (in_use > 4*minthresh) 2763 return (notify_count); 2764 if (in_use > 2*minthresh) 2765 return (notify_count >> 1); 2766 if (in_use > minthresh) 2767 return (notify_count >> 3); 2768 return (0); 2769 } 2770 2771 static inline qidx_t 2772 txq_max_rs_deferred(iflib_txq_t txq) 2773 { 2774 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2775 qidx_t minthresh = txq->ift_size / 8; 2776 if (txq->ift_in_use > 4*minthresh) 2777 return (notify_count); 2778 if (txq->ift_in_use > 2*minthresh) 2779 return (notify_count >> 1); 2780 if (txq->ift_in_use > minthresh) 2781 return (notify_count >> 2); 2782 return (2); 2783 } 2784 2785 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2786 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2787 2788 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2789 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2790 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2791 2792 /* forward compatibility for cxgb */ 2793 #define FIRST_QSET(ctx) 0 2794 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2795 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2796 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2797 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2798 2799 /* XXX we should be setting this to something other than zero */ 2800 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2801 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2802 2803 static inline bool 2804 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2805 { 2806 qidx_t dbval, max; 2807 bool rang; 2808 2809 rang = false; 2810 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2811 if (ring || txq->ift_db_pending >= max) { 2812 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2813 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2814 txq->ift_db_pending = txq->ift_npending = 0; 2815 rang = true; 2816 } 2817 return (rang); 2818 } 2819 2820 #ifdef PKT_DEBUG 2821 static void 2822 print_pkt(if_pkt_info_t pi) 2823 { 2824 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2825 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2826 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2827 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2828 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2829 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2830 } 2831 #endif 2832 2833 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2834 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2835 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2836 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2837 2838 static int 2839 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2840 { 2841 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2842 struct ether_vlan_header *eh; 2843 struct mbuf *m, *n; 2844 2845 n = m = *mp; 2846 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2847 M_WRITABLE(m) == 0) { 2848 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2849 return (ENOMEM); 2850 } else { 2851 m_freem(*mp); 2852 n = *mp = m; 2853 } 2854 } 2855 2856 /* 2857 * Determine where frame payload starts. 2858 * Jump over vlan headers if already present, 2859 * helpful for QinQ too. 2860 */ 2861 if (__predict_false(m->m_len < sizeof(*eh))) { 2862 txq->ift_pullups++; 2863 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2864 return (ENOMEM); 2865 } 2866 eh = mtod(m, struct ether_vlan_header *); 2867 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2868 pi->ipi_etype = ntohs(eh->evl_proto); 2869 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2870 } else { 2871 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2872 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2873 } 2874 2875 switch (pi->ipi_etype) { 2876 #ifdef INET 2877 case ETHERTYPE_IP: 2878 { 2879 struct ip *ip = NULL; 2880 struct tcphdr *th = NULL; 2881 int minthlen; 2882 2883 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2884 if (__predict_false(m->m_len < minthlen)) { 2885 /* 2886 * if this code bloat is causing too much of a hit 2887 * move it to a separate function and mark it noinline 2888 */ 2889 if (m->m_len == pi->ipi_ehdrlen) { 2890 n = m->m_next; 2891 MPASS(n); 2892 if (n->m_len >= sizeof(*ip)) { 2893 ip = (struct ip *)n->m_data; 2894 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2895 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2896 } else { 2897 txq->ift_pullups++; 2898 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2899 return (ENOMEM); 2900 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2901 } 2902 } else { 2903 txq->ift_pullups++; 2904 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2905 return (ENOMEM); 2906 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2907 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2908 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2909 } 2910 } else { 2911 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2912 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2913 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2914 } 2915 pi->ipi_ip_hlen = ip->ip_hl << 2; 2916 pi->ipi_ipproto = ip->ip_p; 2917 pi->ipi_flags |= IPI_TX_IPV4; 2918 2919 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 2920 ip->ip_sum = 0; 2921 2922 /* TCP checksum offload may require TCP header length */ 2923 if (IS_TX_OFFLOAD4(pi)) { 2924 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 2925 if (__predict_false(th == NULL)) { 2926 txq->ift_pullups++; 2927 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2928 return (ENOMEM); 2929 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2930 } 2931 pi->ipi_tcp_hflags = th->th_flags; 2932 pi->ipi_tcp_hlen = th->th_off << 2; 2933 pi->ipi_tcp_seq = th->th_seq; 2934 } 2935 if (IS_TSO4(pi)) { 2936 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2937 return (ENXIO); 2938 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2939 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2940 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2941 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2942 ip->ip_sum = 0; 2943 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2944 } 2945 } 2946 } 2947 break; 2948 } 2949 #endif 2950 #ifdef INET6 2951 case ETHERTYPE_IPV6: 2952 { 2953 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2954 struct tcphdr *th; 2955 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2956 2957 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2958 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2959 return (ENOMEM); 2960 } 2961 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2962 2963 /* XXX-BZ this will go badly in case of ext hdrs. */ 2964 pi->ipi_ipproto = ip6->ip6_nxt; 2965 pi->ipi_flags |= IPI_TX_IPV6; 2966 2967 /* TCP checksum offload may require TCP header length */ 2968 if (IS_TX_OFFLOAD6(pi)) { 2969 if (pi->ipi_ipproto == IPPROTO_TCP) { 2970 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2971 txq->ift_pullups++; 2972 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2973 return (ENOMEM); 2974 } 2975 pi->ipi_tcp_hflags = th->th_flags; 2976 pi->ipi_tcp_hlen = th->th_off << 2; 2977 pi->ipi_tcp_seq = th->th_seq; 2978 } 2979 if (IS_TSO6(pi)) { 2980 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2981 return (ENXIO); 2982 /* 2983 * The corresponding flag is set by the stack in the IPv4 2984 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 2985 * So, set it here because the rest of the flow requires it. 2986 */ 2987 pi->ipi_csum_flags |= CSUM_IP6_TCP; 2988 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2989 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2990 } 2991 } 2992 break; 2993 } 2994 #endif 2995 default: 2996 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2997 pi->ipi_ip_hlen = 0; 2998 break; 2999 } 3000 *mp = m; 3001 3002 return (0); 3003 } 3004 3005 static __noinline struct mbuf * 3006 collapse_pkthdr(struct mbuf *m0) 3007 { 3008 struct mbuf *m, *m_next, *tmp; 3009 3010 m = m0; 3011 m_next = m->m_next; 3012 while (m_next != NULL && m_next->m_len == 0) { 3013 m = m_next; 3014 m->m_next = NULL; 3015 m_free(m); 3016 m_next = m_next->m_next; 3017 } 3018 m = m0; 3019 m->m_next = m_next; 3020 if ((m_next->m_flags & M_EXT) == 0) { 3021 m = m_defrag(m, M_NOWAIT); 3022 } else { 3023 tmp = m_next->m_next; 3024 memcpy(m_next, m, MPKTHSIZE); 3025 m = m_next; 3026 m->m_next = tmp; 3027 } 3028 return (m); 3029 } 3030 3031 /* 3032 * If dodgy hardware rejects the scatter gather chain we've handed it 3033 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3034 * m_defrag'd mbufs 3035 */ 3036 static __noinline struct mbuf * 3037 iflib_remove_mbuf(iflib_txq_t txq) 3038 { 3039 int ntxd, i, pidx; 3040 struct mbuf *m, *mh, **ifsd_m; 3041 3042 pidx = txq->ift_pidx; 3043 ifsd_m = txq->ift_sds.ifsd_m; 3044 ntxd = txq->ift_size; 3045 mh = m = ifsd_m[pidx]; 3046 ifsd_m[pidx] = NULL; 3047 #if MEMORY_LOGGING 3048 txq->ift_dequeued++; 3049 #endif 3050 i = 1; 3051 3052 while (m) { 3053 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 3054 #if MEMORY_LOGGING 3055 txq->ift_dequeued++; 3056 #endif 3057 m = m->m_next; 3058 i++; 3059 } 3060 return (mh); 3061 } 3062 3063 static int 3064 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 3065 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 3066 int max_segs, int flags) 3067 { 3068 if_ctx_t ctx; 3069 if_shared_ctx_t sctx; 3070 if_softc_ctx_t scctx; 3071 int i, next, pidx, err, ntxd, count; 3072 struct mbuf *m, *tmp, **ifsd_m; 3073 3074 m = *m0; 3075 3076 /* 3077 * Please don't ever do this 3078 */ 3079 if (__predict_false(m->m_len == 0)) 3080 *m0 = m = collapse_pkthdr(m); 3081 3082 ctx = txq->ift_ctx; 3083 sctx = ctx->ifc_sctx; 3084 scctx = &ctx->ifc_softc_ctx; 3085 ifsd_m = txq->ift_sds.ifsd_m; 3086 ntxd = txq->ift_size; 3087 pidx = txq->ift_pidx; 3088 if (map != NULL) { 3089 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 3090 3091 err = bus_dmamap_load_mbuf_sg(tag, map, 3092 *m0, segs, nsegs, BUS_DMA_NOWAIT); 3093 if (err) 3094 return (err); 3095 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 3096 count = 0; 3097 m = *m0; 3098 do { 3099 if (__predict_false(m->m_len <= 0)) { 3100 tmp = m; 3101 m = m->m_next; 3102 tmp->m_next = NULL; 3103 m_free(tmp); 3104 continue; 3105 } 3106 m = m->m_next; 3107 count++; 3108 } while (m != NULL); 3109 if (count > *nsegs) { 3110 ifsd_m[pidx] = *m0; 3111 ifsd_m[pidx]->m_flags |= M_TOOBIG; 3112 return (0); 3113 } 3114 m = *m0; 3115 count = 0; 3116 do { 3117 next = (pidx + count) & (ntxd-1); 3118 MPASS(ifsd_m[next] == NULL); 3119 ifsd_m[next] = m; 3120 count++; 3121 tmp = m; 3122 m = m->m_next; 3123 } while (m != NULL); 3124 } else { 3125 int buflen, sgsize, maxsegsz, max_sgsize; 3126 vm_offset_t vaddr; 3127 vm_paddr_t curaddr; 3128 3129 count = i = 0; 3130 m = *m0; 3131 if (m->m_pkthdr.csum_flags & CSUM_TSO) 3132 maxsegsz = scctx->isc_tx_tso_segsize_max; 3133 else 3134 maxsegsz = sctx->isc_tx_maxsegsize; 3135 3136 do { 3137 if (__predict_false(m->m_len <= 0)) { 3138 tmp = m; 3139 m = m->m_next; 3140 tmp->m_next = NULL; 3141 m_free(tmp); 3142 continue; 3143 } 3144 buflen = m->m_len; 3145 vaddr = (vm_offset_t)m->m_data; 3146 /* 3147 * see if we can't be smarter about physically 3148 * contiguous mappings 3149 */ 3150 next = (pidx + count) & (ntxd-1); 3151 MPASS(ifsd_m[next] == NULL); 3152 #if MEMORY_LOGGING 3153 txq->ift_enqueued++; 3154 #endif 3155 ifsd_m[next] = m; 3156 while (buflen > 0) { 3157 if (i >= max_segs) 3158 goto err; 3159 max_sgsize = MIN(buflen, maxsegsz); 3160 curaddr = pmap_kextract(vaddr); 3161 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 3162 sgsize = MIN(sgsize, max_sgsize); 3163 segs[i].ds_addr = curaddr; 3164 segs[i].ds_len = sgsize; 3165 vaddr += sgsize; 3166 buflen -= sgsize; 3167 i++; 3168 } 3169 count++; 3170 tmp = m; 3171 m = m->m_next; 3172 } while (m != NULL); 3173 *nsegs = i; 3174 } 3175 return (0); 3176 err: 3177 *m0 = iflib_remove_mbuf(txq); 3178 return (EFBIG); 3179 } 3180 3181 static inline caddr_t 3182 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3183 { 3184 qidx_t size; 3185 int ntxd; 3186 caddr_t start, end, cur, next; 3187 3188 ntxd = txq->ift_size; 3189 size = txq->ift_txd_size[qid]; 3190 start = txq->ift_ifdi[qid].idi_vaddr; 3191 3192 if (__predict_false(size == 0)) 3193 return (start); 3194 cur = start + size*cidx; 3195 end = start + size*ntxd; 3196 next = CACHE_PTR_NEXT(cur); 3197 return (next < end ? next : start); 3198 } 3199 3200 /* 3201 * Pad an mbuf to ensure a minimum ethernet frame size. 3202 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3203 */ 3204 static __noinline int 3205 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3206 { 3207 /* 3208 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3209 * and ARP message is the smallest common payload I can think of 3210 */ 3211 static char pad[18]; /* just zeros */ 3212 int n; 3213 struct mbuf *new_head; 3214 3215 if (!M_WRITABLE(*m_head)) { 3216 new_head = m_dup(*m_head, M_NOWAIT); 3217 if (new_head == NULL) { 3218 m_freem(*m_head); 3219 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3220 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3221 return ENOMEM; 3222 } 3223 m_freem(*m_head); 3224 *m_head = new_head; 3225 } 3226 3227 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3228 n > 0; n -= sizeof(pad)) 3229 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3230 break; 3231 3232 if (n > 0) { 3233 m_freem(*m_head); 3234 device_printf(dev, "cannot pad short frame\n"); 3235 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3236 return (ENOBUFS); 3237 } 3238 3239 return 0; 3240 } 3241 3242 static int 3243 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3244 { 3245 if_ctx_t ctx; 3246 if_shared_ctx_t sctx; 3247 if_softc_ctx_t scctx; 3248 bus_dma_segment_t *segs; 3249 struct mbuf *m_head; 3250 void *next_txd; 3251 bus_dmamap_t map; 3252 struct if_pkt_info pi; 3253 int remap = 0; 3254 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3255 bus_dma_tag_t desc_tag; 3256 3257 segs = txq->ift_segs; 3258 ctx = txq->ift_ctx; 3259 sctx = ctx->ifc_sctx; 3260 scctx = &ctx->ifc_softc_ctx; 3261 segs = txq->ift_segs; 3262 ntxd = txq->ift_size; 3263 m_head = *m_headp; 3264 map = NULL; 3265 3266 /* 3267 * If we're doing TSO the next descriptor to clean may be quite far ahead 3268 */ 3269 cidx = txq->ift_cidx; 3270 pidx = txq->ift_pidx; 3271 if (ctx->ifc_flags & IFC_PREFETCH) { 3272 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3273 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3274 next_txd = calc_next_txd(txq, cidx, 0); 3275 prefetch(next_txd); 3276 } 3277 3278 /* prefetch the next cache line of mbuf pointers and flags */ 3279 prefetch(&txq->ift_sds.ifsd_m[next]); 3280 if (txq->ift_sds.ifsd_map != NULL) { 3281 prefetch(&txq->ift_sds.ifsd_map[next]); 3282 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3283 prefetch(&txq->ift_sds.ifsd_flags[next]); 3284 } 3285 } else if (txq->ift_sds.ifsd_map != NULL) 3286 map = txq->ift_sds.ifsd_map[pidx]; 3287 3288 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3289 desc_tag = txq->ift_tso_desc_tag; 3290 max_segs = scctx->isc_tx_tso_segments_max; 3291 MPASS(desc_tag != NULL); 3292 MPASS(max_segs > 0); 3293 } else { 3294 desc_tag = txq->ift_desc_tag; 3295 max_segs = scctx->isc_tx_nsegments; 3296 } 3297 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3298 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3299 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3300 if (err) 3301 return err; 3302 } 3303 m_head = *m_headp; 3304 3305 pkt_info_zero(&pi); 3306 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3307 pi.ipi_pidx = pidx; 3308 pi.ipi_qsidx = txq->ift_id; 3309 pi.ipi_len = m_head->m_pkthdr.len; 3310 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3311 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3312 3313 /* deliberate bitwise OR to make one condition */ 3314 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3315 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3316 return (err); 3317 m_head = *m_headp; 3318 } 3319 3320 retry: 3321 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3322 defrag: 3323 if (__predict_false(err)) { 3324 switch (err) { 3325 case EFBIG: 3326 /* try collapse once and defrag once */ 3327 if (remap == 0) { 3328 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3329 /* try defrag if collapsing fails */ 3330 if (m_head == NULL) 3331 remap++; 3332 } 3333 if (remap == 1) 3334 m_head = m_defrag(*m_headp, M_NOWAIT); 3335 remap++; 3336 if (__predict_false(m_head == NULL)) 3337 goto defrag_failed; 3338 txq->ift_mbuf_defrag++; 3339 *m_headp = m_head; 3340 goto retry; 3341 break; 3342 case ENOMEM: 3343 txq->ift_no_tx_dma_setup++; 3344 break; 3345 default: 3346 txq->ift_no_tx_dma_setup++; 3347 m_freem(*m_headp); 3348 DBG_COUNTER_INC(tx_frees); 3349 *m_headp = NULL; 3350 break; 3351 } 3352 txq->ift_map_failed++; 3353 DBG_COUNTER_INC(encap_load_mbuf_fail); 3354 return (err); 3355 } 3356 3357 /* 3358 * XXX assumes a 1 to 1 relationship between segments and 3359 * descriptors - this does not hold true on all drivers, e.g. 3360 * cxgb 3361 */ 3362 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3363 txq->ift_no_desc_avail++; 3364 if (map != NULL) 3365 bus_dmamap_unload(desc_tag, map); 3366 DBG_COUNTER_INC(encap_txq_avail_fail); 3367 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3368 GROUPTASK_ENQUEUE(&txq->ift_task); 3369 return (ENOBUFS); 3370 } 3371 /* 3372 * On Intel cards we can greatly reduce the number of TX interrupts 3373 * we see by only setting report status on every Nth descriptor. 3374 * However, this also means that the driver will need to keep track 3375 * of the descriptors that RS was set on to check them for the DD bit. 3376 */ 3377 txq->ift_rs_pending += nsegs + 1; 3378 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3379 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3380 pi.ipi_flags |= IPI_TX_INTR; 3381 txq->ift_rs_pending = 0; 3382 } 3383 3384 pi.ipi_segs = segs; 3385 pi.ipi_nsegs = nsegs; 3386 3387 MPASS(pidx >= 0 && pidx < txq->ift_size); 3388 #ifdef PKT_DEBUG 3389 print_pkt(&pi); 3390 #endif 3391 if (map != NULL) 3392 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3393 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3394 if (map != NULL) 3395 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3396 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3397 DBG_COUNTER_INC(tx_encap); 3398 MPASS(pi.ipi_new_pidx < txq->ift_size); 3399 3400 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3401 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3402 ndesc += txq->ift_size; 3403 txq->ift_gen = 1; 3404 } 3405 /* 3406 * drivers can need as many as 3407 * two sentinels 3408 */ 3409 MPASS(ndesc <= pi.ipi_nsegs + 2); 3410 MPASS(pi.ipi_new_pidx != pidx); 3411 MPASS(ndesc > 0); 3412 txq->ift_in_use += ndesc; 3413 3414 /* 3415 * We update the last software descriptor again here because there may 3416 * be a sentinel and/or there may be more mbufs than segments 3417 */ 3418 txq->ift_pidx = pi.ipi_new_pidx; 3419 txq->ift_npending += pi.ipi_ndescs; 3420 } else { 3421 *m_headp = m_head = iflib_remove_mbuf(txq); 3422 if (err == EFBIG) { 3423 txq->ift_txd_encap_efbig++; 3424 if (remap < 2) { 3425 remap = 1; 3426 goto defrag; 3427 } 3428 } 3429 DBG_COUNTER_INC(encap_txd_encap_fail); 3430 goto defrag_failed; 3431 } 3432 return (err); 3433 3434 defrag_failed: 3435 txq->ift_mbuf_defrag_failed++; 3436 txq->ift_map_failed++; 3437 m_freem(*m_headp); 3438 DBG_COUNTER_INC(tx_frees); 3439 *m_headp = NULL; 3440 return (ENOMEM); 3441 } 3442 3443 static void 3444 iflib_tx_desc_free(iflib_txq_t txq, int n) 3445 { 3446 int hasmap; 3447 uint32_t qsize, cidx, mask, gen; 3448 struct mbuf *m, **ifsd_m; 3449 uint8_t *ifsd_flags; 3450 bus_dmamap_t *ifsd_map; 3451 bool do_prefetch; 3452 3453 cidx = txq->ift_cidx; 3454 gen = txq->ift_gen; 3455 qsize = txq->ift_size; 3456 mask = qsize-1; 3457 hasmap = txq->ift_sds.ifsd_map != NULL; 3458 ifsd_flags = txq->ift_sds.ifsd_flags; 3459 ifsd_m = txq->ift_sds.ifsd_m; 3460 ifsd_map = txq->ift_sds.ifsd_map; 3461 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3462 3463 while (n-- > 0) { 3464 if (do_prefetch) { 3465 prefetch(ifsd_m[(cidx + 3) & mask]); 3466 prefetch(ifsd_m[(cidx + 4) & mask]); 3467 } 3468 if (ifsd_m[cidx] != NULL) { 3469 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3470 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3471 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3472 /* 3473 * does it matter if it's not the TSO tag? If so we'll 3474 * have to add the type to flags 3475 */ 3476 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3477 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3478 } 3479 if ((m = ifsd_m[cidx]) != NULL) { 3480 /* XXX we don't support any drivers that batch packets yet */ 3481 MPASS(m->m_nextpkt == NULL); 3482 /* if the number of clusters exceeds the number of segments 3483 * there won't be space on the ring to save a pointer to each 3484 * cluster so we simply free the list here 3485 */ 3486 if (m->m_flags & M_TOOBIG) { 3487 m_freem(m); 3488 } else { 3489 m_free(m); 3490 } 3491 ifsd_m[cidx] = NULL; 3492 #if MEMORY_LOGGING 3493 txq->ift_dequeued++; 3494 #endif 3495 DBG_COUNTER_INC(tx_frees); 3496 } 3497 } 3498 if (__predict_false(++cidx == qsize)) { 3499 cidx = 0; 3500 gen = 0; 3501 } 3502 } 3503 txq->ift_cidx = cidx; 3504 txq->ift_gen = gen; 3505 } 3506 3507 static __inline int 3508 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3509 { 3510 int reclaim; 3511 if_ctx_t ctx = txq->ift_ctx; 3512 3513 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3514 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3515 3516 /* 3517 * Need a rate-limiting check so that this isn't called every time 3518 */ 3519 iflib_tx_credits_update(ctx, txq); 3520 reclaim = DESC_RECLAIMABLE(txq); 3521 3522 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3523 #ifdef INVARIANTS 3524 if (iflib_verbose_debug) { 3525 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3526 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3527 reclaim, thresh); 3528 3529 } 3530 #endif 3531 return (0); 3532 } 3533 iflib_tx_desc_free(txq, reclaim); 3534 txq->ift_cleaned += reclaim; 3535 txq->ift_in_use -= reclaim; 3536 3537 return (reclaim); 3538 } 3539 3540 static struct mbuf ** 3541 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3542 { 3543 int next, size; 3544 struct mbuf **items; 3545 3546 size = r->size; 3547 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3548 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3549 3550 prefetch(items[(cidx + offset) & (size-1)]); 3551 if (remaining > 1) { 3552 prefetch2cachelines(&items[next]); 3553 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3554 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3555 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3556 } 3557 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3558 } 3559 3560 static void 3561 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3562 { 3563 3564 ifmp_ring_check_drainage(txq->ift_br, budget); 3565 } 3566 3567 static uint32_t 3568 iflib_txq_can_drain(struct ifmp_ring *r) 3569 { 3570 iflib_txq_t txq = r->cookie; 3571 if_ctx_t ctx = txq->ift_ctx; 3572 3573 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3574 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3575 } 3576 3577 static uint32_t 3578 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3579 { 3580 iflib_txq_t txq = r->cookie; 3581 if_ctx_t ctx = txq->ift_ctx; 3582 struct ifnet *ifp = ctx->ifc_ifp; 3583 struct mbuf **mp, *m; 3584 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3585 int reclaimed, err, in_use_prev, desc_used; 3586 bool do_prefetch, ring, rang; 3587 3588 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3589 !LINK_ACTIVE(ctx))) { 3590 DBG_COUNTER_INC(txq_drain_notready); 3591 return (0); 3592 } 3593 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3594 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3595 avail = IDXDIFF(pidx, cidx, r->size); 3596 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3597 DBG_COUNTER_INC(txq_drain_flushing); 3598 for (i = 0; i < avail; i++) { 3599 m_free(r->items[(cidx + i) & (r->size-1)]); 3600 r->items[(cidx + i) & (r->size-1)] = NULL; 3601 } 3602 return (avail); 3603 } 3604 3605 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3606 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3607 CALLOUT_LOCK(txq); 3608 callout_stop(&txq->ift_timer); 3609 CALLOUT_UNLOCK(txq); 3610 DBG_COUNTER_INC(txq_drain_oactive); 3611 return (0); 3612 } 3613 if (reclaimed) 3614 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3615 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3616 count = MIN(avail, TX_BATCH_SIZE); 3617 #ifdef INVARIANTS 3618 if (iflib_verbose_debug) 3619 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3620 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3621 #endif 3622 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3623 avail = TXQ_AVAIL(txq); 3624 err = 0; 3625 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3626 int rem = do_prefetch ? count - i : 0; 3627 3628 mp = _ring_peek_one(r, cidx, i, rem); 3629 MPASS(mp != NULL && *mp != NULL); 3630 if (__predict_false(*mp == (struct mbuf *)txq)) { 3631 consumed++; 3632 reclaimed++; 3633 continue; 3634 } 3635 in_use_prev = txq->ift_in_use; 3636 err = iflib_encap(txq, mp); 3637 if (__predict_false(err)) { 3638 DBG_COUNTER_INC(txq_drain_encapfail); 3639 /* no room - bail out */ 3640 if (err == ENOBUFS) 3641 break; 3642 consumed++; 3643 DBG_COUNTER_INC(txq_drain_encapfail); 3644 /* we can't send this packet - skip it */ 3645 continue; 3646 } 3647 consumed++; 3648 pkt_sent++; 3649 m = *mp; 3650 DBG_COUNTER_INC(tx_sent); 3651 bytes_sent += m->m_pkthdr.len; 3652 mcast_sent += !!(m->m_flags & M_MCAST); 3653 avail = TXQ_AVAIL(txq); 3654 3655 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3656 desc_used += (txq->ift_in_use - in_use_prev); 3657 ETHER_BPF_MTAP(ifp, m); 3658 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3659 break; 3660 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3661 } 3662 3663 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3664 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3665 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3666 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3667 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3668 if (mcast_sent) 3669 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3670 #ifdef INVARIANTS 3671 if (iflib_verbose_debug) 3672 printf("consumed=%d\n", consumed); 3673 #endif 3674 return (consumed); 3675 } 3676 3677 static uint32_t 3678 iflib_txq_drain_always(struct ifmp_ring *r) 3679 { 3680 return (1); 3681 } 3682 3683 static uint32_t 3684 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3685 { 3686 int i, avail; 3687 struct mbuf **mp; 3688 iflib_txq_t txq; 3689 3690 txq = r->cookie; 3691 3692 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3693 CALLOUT_LOCK(txq); 3694 callout_stop(&txq->ift_timer); 3695 CALLOUT_UNLOCK(txq); 3696 3697 avail = IDXDIFF(pidx, cidx, r->size); 3698 for (i = 0; i < avail; i++) { 3699 mp = _ring_peek_one(r, cidx, i, avail - i); 3700 if (__predict_false(*mp == (struct mbuf *)txq)) 3701 continue; 3702 m_freem(*mp); 3703 } 3704 MPASS(ifmp_ring_is_stalled(r) == 0); 3705 return (avail); 3706 } 3707 3708 static void 3709 iflib_ifmp_purge(iflib_txq_t txq) 3710 { 3711 struct ifmp_ring *r; 3712 3713 r = txq->ift_br; 3714 r->drain = iflib_txq_drain_free; 3715 r->can_drain = iflib_txq_drain_always; 3716 3717 ifmp_ring_check_drainage(r, r->size); 3718 3719 r->drain = iflib_txq_drain; 3720 r->can_drain = iflib_txq_can_drain; 3721 } 3722 3723 static void 3724 _task_fn_tx(void *context) 3725 { 3726 iflib_txq_t txq = context; 3727 if_ctx_t ctx = txq->ift_ctx; 3728 struct ifnet *ifp = ctx->ifc_ifp; 3729 3730 #ifdef IFLIB_DIAGNOSTICS 3731 txq->ift_cpu_exec_count[curcpu]++; 3732 #endif 3733 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3734 return; 3735 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3736 /* 3737 * If there are no available credits, and TX IRQs are not in use, 3738 * re-schedule the task immediately. 3739 */ 3740 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3741 netmap_tx_irq(ifp, txq->ift_id); 3742 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3743 return; 3744 } 3745 if (txq->ift_db_pending) 3746 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); 3747 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3748 if (ctx->ifc_flags & IFC_LEGACY) 3749 IFDI_INTR_ENABLE(ctx); 3750 else { 3751 #ifdef INVARIANTS 3752 int rc = 3753 #endif 3754 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3755 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3756 } 3757 } 3758 3759 static void 3760 _task_fn_rx(void *context) 3761 { 3762 iflib_rxq_t rxq = context; 3763 if_ctx_t ctx = rxq->ifr_ctx; 3764 bool more; 3765 uint16_t budget; 3766 3767 #ifdef IFLIB_DIAGNOSTICS 3768 rxq->ifr_cpu_exec_count[curcpu]++; 3769 #endif 3770 DBG_COUNTER_INC(task_fn_rxs); 3771 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3772 return; 3773 more = true; 3774 #ifdef DEV_NETMAP 3775 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3776 u_int work = 0; 3777 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3778 more = false; 3779 } 3780 } 3781 #endif 3782 budget = ctx->ifc_sysctl_rx_budget; 3783 if (budget == 0) 3784 budget = 16; /* XXX */ 3785 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3786 if (ctx->ifc_flags & IFC_LEGACY) 3787 IFDI_INTR_ENABLE(ctx); 3788 else { 3789 #ifdef INVARIANTS 3790 int rc = 3791 #endif 3792 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3793 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3794 DBG_COUNTER_INC(rx_intr_enables); 3795 } 3796 } 3797 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3798 return; 3799 if (more) 3800 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3801 } 3802 3803 static void 3804 _task_fn_admin(void *context) 3805 { 3806 if_ctx_t ctx = context; 3807 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3808 iflib_txq_t txq; 3809 int i; 3810 bool oactive, running, do_reset, do_watchdog; 3811 3812 STATE_LOCK(ctx); 3813 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3814 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3815 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3816 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3817 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3818 STATE_UNLOCK(ctx); 3819 3820 if ((!running & !oactive) && 3821 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3822 return; 3823 3824 CTX_LOCK(ctx); 3825 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3826 CALLOUT_LOCK(txq); 3827 callout_stop(&txq->ift_timer); 3828 CALLOUT_UNLOCK(txq); 3829 } 3830 if (do_watchdog) { 3831 ctx->ifc_watchdog_events++; 3832 IFDI_WATCHDOG_RESET(ctx); 3833 } 3834 IFDI_UPDATE_ADMIN_STATUS(ctx); 3835 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3836 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 3837 IFDI_LINK_INTR_ENABLE(ctx); 3838 if (do_reset) 3839 iflib_if_init_locked(ctx); 3840 CTX_UNLOCK(ctx); 3841 3842 if (LINK_ACTIVE(ctx) == 0) 3843 return; 3844 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3845 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3846 } 3847 3848 3849 static void 3850 _task_fn_iov(void *context) 3851 { 3852 if_ctx_t ctx = context; 3853 3854 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3855 return; 3856 3857 CTX_LOCK(ctx); 3858 IFDI_VFLR_HANDLE(ctx); 3859 CTX_UNLOCK(ctx); 3860 } 3861 3862 static int 3863 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3864 { 3865 int err; 3866 if_int_delay_info_t info; 3867 if_ctx_t ctx; 3868 3869 info = (if_int_delay_info_t)arg1; 3870 ctx = info->iidi_ctx; 3871 info->iidi_req = req; 3872 info->iidi_oidp = oidp; 3873 CTX_LOCK(ctx); 3874 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3875 CTX_UNLOCK(ctx); 3876 return (err); 3877 } 3878 3879 /********************************************************************* 3880 * 3881 * IFNET FUNCTIONS 3882 * 3883 **********************************************************************/ 3884 3885 static void 3886 iflib_if_init_locked(if_ctx_t ctx) 3887 { 3888 iflib_stop(ctx); 3889 iflib_init_locked(ctx); 3890 } 3891 3892 3893 static void 3894 iflib_if_init(void *arg) 3895 { 3896 if_ctx_t ctx = arg; 3897 3898 CTX_LOCK(ctx); 3899 iflib_if_init_locked(ctx); 3900 CTX_UNLOCK(ctx); 3901 } 3902 3903 static int 3904 iflib_if_transmit(if_t ifp, struct mbuf *m) 3905 { 3906 if_ctx_t ctx = if_getsoftc(ifp); 3907 3908 iflib_txq_t txq; 3909 int err, qidx; 3910 3911 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3912 DBG_COUNTER_INC(tx_frees); 3913 m_freem(m); 3914 return (ENOBUFS); 3915 } 3916 3917 MPASS(m->m_nextpkt == NULL); 3918 qidx = 0; 3919 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3920 qidx = QIDX(ctx, m); 3921 /* 3922 * XXX calculate buf_ring based on flowid (divvy up bits?) 3923 */ 3924 txq = &ctx->ifc_txqs[qidx]; 3925 3926 #ifdef DRIVER_BACKPRESSURE 3927 if (txq->ift_closed) { 3928 while (m != NULL) { 3929 next = m->m_nextpkt; 3930 m->m_nextpkt = NULL; 3931 m_freem(m); 3932 m = next; 3933 } 3934 return (ENOBUFS); 3935 } 3936 #endif 3937 #ifdef notyet 3938 qidx = count = 0; 3939 mp = marr; 3940 next = m; 3941 do { 3942 count++; 3943 next = next->m_nextpkt; 3944 } while (next != NULL); 3945 3946 if (count > nitems(marr)) 3947 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3948 /* XXX check nextpkt */ 3949 m_freem(m); 3950 /* XXX simplify for now */ 3951 DBG_COUNTER_INC(tx_frees); 3952 return (ENOBUFS); 3953 } 3954 for (next = m, i = 0; next != NULL; i++) { 3955 mp[i] = next; 3956 next = next->m_nextpkt; 3957 mp[i]->m_nextpkt = NULL; 3958 } 3959 #endif 3960 DBG_COUNTER_INC(tx_seen); 3961 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); 3962 3963 GROUPTASK_ENQUEUE(&txq->ift_task); 3964 if (err) { 3965 /* support forthcoming later */ 3966 #ifdef DRIVER_BACKPRESSURE 3967 txq->ift_closed = TRUE; 3968 #endif 3969 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3970 m_freem(m); 3971 } 3972 3973 return (err); 3974 } 3975 3976 static void 3977 iflib_if_qflush(if_t ifp) 3978 { 3979 if_ctx_t ctx = if_getsoftc(ifp); 3980 iflib_txq_t txq = ctx->ifc_txqs; 3981 int i; 3982 3983 STATE_LOCK(ctx); 3984 ctx->ifc_flags |= IFC_QFLUSH; 3985 STATE_UNLOCK(ctx); 3986 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3987 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3988 iflib_txq_check_drain(txq, 0); 3989 STATE_LOCK(ctx); 3990 ctx->ifc_flags &= ~IFC_QFLUSH; 3991 STATE_UNLOCK(ctx); 3992 3993 if_qflush(ifp); 3994 } 3995 3996 3997 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3998 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 3999 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 4000 4001 static int 4002 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4003 { 4004 if_ctx_t ctx = if_getsoftc(ifp); 4005 struct ifreq *ifr = (struct ifreq *)data; 4006 #if defined(INET) || defined(INET6) 4007 struct ifaddr *ifa = (struct ifaddr *)data; 4008 #endif 4009 bool avoid_reset = FALSE; 4010 int err = 0, reinit = 0, bits; 4011 4012 switch (command) { 4013 case SIOCSIFADDR: 4014 #ifdef INET 4015 if (ifa->ifa_addr->sa_family == AF_INET) 4016 avoid_reset = TRUE; 4017 #endif 4018 #ifdef INET6 4019 if (ifa->ifa_addr->sa_family == AF_INET6) 4020 avoid_reset = TRUE; 4021 #endif 4022 /* 4023 ** Calling init results in link renegotiation, 4024 ** so we avoid doing it when possible. 4025 */ 4026 if (avoid_reset) { 4027 if_setflagbits(ifp, IFF_UP,0); 4028 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4029 reinit = 1; 4030 #ifdef INET 4031 if (!(if_getflags(ifp) & IFF_NOARP)) 4032 arp_ifinit(ifp, ifa); 4033 #endif 4034 } else 4035 err = ether_ioctl(ifp, command, data); 4036 break; 4037 case SIOCSIFMTU: 4038 CTX_LOCK(ctx); 4039 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4040 CTX_UNLOCK(ctx); 4041 break; 4042 } 4043 bits = if_getdrvflags(ifp); 4044 /* stop the driver and free any clusters before proceeding */ 4045 iflib_stop(ctx); 4046 4047 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4048 STATE_LOCK(ctx); 4049 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4050 ctx->ifc_flags |= IFC_MULTISEG; 4051 else 4052 ctx->ifc_flags &= ~IFC_MULTISEG; 4053 STATE_UNLOCK(ctx); 4054 err = if_setmtu(ifp, ifr->ifr_mtu); 4055 } 4056 iflib_init_locked(ctx); 4057 STATE_LOCK(ctx); 4058 if_setdrvflags(ifp, bits); 4059 STATE_UNLOCK(ctx); 4060 CTX_UNLOCK(ctx); 4061 break; 4062 case SIOCSIFFLAGS: 4063 CTX_LOCK(ctx); 4064 if (if_getflags(ifp) & IFF_UP) { 4065 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4066 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4067 (IFF_PROMISC | IFF_ALLMULTI)) { 4068 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4069 } 4070 } else 4071 reinit = 1; 4072 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4073 iflib_stop(ctx); 4074 } 4075 ctx->ifc_if_flags = if_getflags(ifp); 4076 CTX_UNLOCK(ctx); 4077 break; 4078 case SIOCADDMULTI: 4079 case SIOCDELMULTI: 4080 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4081 CTX_LOCK(ctx); 4082 IFDI_INTR_DISABLE(ctx); 4083 IFDI_MULTI_SET(ctx); 4084 IFDI_INTR_ENABLE(ctx); 4085 CTX_UNLOCK(ctx); 4086 } 4087 break; 4088 case SIOCSIFMEDIA: 4089 CTX_LOCK(ctx); 4090 IFDI_MEDIA_SET(ctx); 4091 CTX_UNLOCK(ctx); 4092 /* falls thru */ 4093 case SIOCGIFMEDIA: 4094 case SIOCGIFXMEDIA: 4095 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 4096 break; 4097 case SIOCGI2C: 4098 { 4099 struct ifi2creq i2c; 4100 4101 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4102 if (err != 0) 4103 break; 4104 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4105 err = EINVAL; 4106 break; 4107 } 4108 if (i2c.len > sizeof(i2c.data)) { 4109 err = EINVAL; 4110 break; 4111 } 4112 4113 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4114 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4115 sizeof(i2c)); 4116 break; 4117 } 4118 case SIOCSIFCAP: 4119 { 4120 int mask, setmask; 4121 4122 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 4123 setmask = 0; 4124 #ifdef TCP_OFFLOAD 4125 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4126 #endif 4127 setmask |= (mask & IFCAP_FLAGS); 4128 4129 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 4130 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4131 if ((mask & IFCAP_WOL) && 4132 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 4133 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 4134 if_vlancap(ifp); 4135 /* 4136 * want to ensure that traffic has stopped before we change any of the flags 4137 */ 4138 if (setmask) { 4139 CTX_LOCK(ctx); 4140 bits = if_getdrvflags(ifp); 4141 if (bits & IFF_DRV_RUNNING) 4142 iflib_stop(ctx); 4143 STATE_LOCK(ctx); 4144 if_togglecapenable(ifp, setmask); 4145 STATE_UNLOCK(ctx); 4146 if (bits & IFF_DRV_RUNNING) 4147 iflib_init_locked(ctx); 4148 STATE_LOCK(ctx); 4149 if_setdrvflags(ifp, bits); 4150 STATE_UNLOCK(ctx); 4151 CTX_UNLOCK(ctx); 4152 } 4153 break; 4154 } 4155 case SIOCGPRIVATE_0: 4156 case SIOCSDRVSPEC: 4157 case SIOCGDRVSPEC: 4158 CTX_LOCK(ctx); 4159 err = IFDI_PRIV_IOCTL(ctx, command, data); 4160 CTX_UNLOCK(ctx); 4161 break; 4162 default: 4163 err = ether_ioctl(ifp, command, data); 4164 break; 4165 } 4166 if (reinit) 4167 iflib_if_init(ctx); 4168 return (err); 4169 } 4170 4171 static uint64_t 4172 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4173 { 4174 if_ctx_t ctx = if_getsoftc(ifp); 4175 4176 return (IFDI_GET_COUNTER(ctx, cnt)); 4177 } 4178 4179 /********************************************************************* 4180 * 4181 * OTHER FUNCTIONS EXPORTED TO THE STACK 4182 * 4183 **********************************************************************/ 4184 4185 static void 4186 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4187 { 4188 if_ctx_t ctx = if_getsoftc(ifp); 4189 4190 if ((void *)ctx != arg) 4191 return; 4192 4193 if ((vtag == 0) || (vtag > 4095)) 4194 return; 4195 4196 CTX_LOCK(ctx); 4197 IFDI_VLAN_REGISTER(ctx, vtag); 4198 /* Re-init to load the changes */ 4199 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4200 iflib_if_init_locked(ctx); 4201 CTX_UNLOCK(ctx); 4202 } 4203 4204 static void 4205 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4206 { 4207 if_ctx_t ctx = if_getsoftc(ifp); 4208 4209 if ((void *)ctx != arg) 4210 return; 4211 4212 if ((vtag == 0) || (vtag > 4095)) 4213 return; 4214 4215 CTX_LOCK(ctx); 4216 IFDI_VLAN_UNREGISTER(ctx, vtag); 4217 /* Re-init to load the changes */ 4218 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4219 iflib_if_init_locked(ctx); 4220 CTX_UNLOCK(ctx); 4221 } 4222 4223 static void 4224 iflib_led_func(void *arg, int onoff) 4225 { 4226 if_ctx_t ctx = arg; 4227 4228 CTX_LOCK(ctx); 4229 IFDI_LED_FUNC(ctx, onoff); 4230 CTX_UNLOCK(ctx); 4231 } 4232 4233 /********************************************************************* 4234 * 4235 * BUS FUNCTION DEFINITIONS 4236 * 4237 **********************************************************************/ 4238 4239 int 4240 iflib_device_probe(device_t dev) 4241 { 4242 pci_vendor_info_t *ent; 4243 4244 uint16_t pci_vendor_id, pci_device_id; 4245 uint16_t pci_subvendor_id, pci_subdevice_id; 4246 uint16_t pci_rev_id; 4247 if_shared_ctx_t sctx; 4248 4249 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4250 return (ENOTSUP); 4251 4252 pci_vendor_id = pci_get_vendor(dev); 4253 pci_device_id = pci_get_device(dev); 4254 pci_subvendor_id = pci_get_subvendor(dev); 4255 pci_subdevice_id = pci_get_subdevice(dev); 4256 pci_rev_id = pci_get_revid(dev); 4257 if (sctx->isc_parse_devinfo != NULL) 4258 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4259 4260 ent = sctx->isc_vendor_info; 4261 while (ent->pvi_vendor_id != 0) { 4262 if (pci_vendor_id != ent->pvi_vendor_id) { 4263 ent++; 4264 continue; 4265 } 4266 if ((pci_device_id == ent->pvi_device_id) && 4267 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4268 (ent->pvi_subvendor_id == 0)) && 4269 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4270 (ent->pvi_subdevice_id == 0)) && 4271 ((pci_rev_id == ent->pvi_rev_id) || 4272 (ent->pvi_rev_id == 0))) { 4273 4274 device_set_desc_copy(dev, ent->pvi_name); 4275 /* this needs to be changed to zero if the bus probing code 4276 * ever stops re-probing on best match because the sctx 4277 * may have its values over written by register calls 4278 * in subsequent probes 4279 */ 4280 return (BUS_PROBE_DEFAULT); 4281 } 4282 ent++; 4283 } 4284 return (ENXIO); 4285 } 4286 4287 static void 4288 iflib_reset_qvalues(if_ctx_t ctx) 4289 { 4290 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4291 if_shared_ctx_t sctx = ctx->ifc_sctx; 4292 device_t dev = ctx->ifc_dev; 4293 int i; 4294 4295 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES; 4296 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH; 4297 /* 4298 * XXX sanity check that ntxd & nrxd are a power of 2 4299 */ 4300 if (ctx->ifc_sysctl_ntxqs != 0) 4301 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4302 if (ctx->ifc_sysctl_nrxqs != 0) 4303 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4304 4305 for (i = 0; i < sctx->isc_ntxqs; i++) { 4306 if (ctx->ifc_sysctl_ntxds[i] != 0) 4307 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4308 else 4309 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4310 } 4311 4312 for (i = 0; i < sctx->isc_nrxqs; i++) { 4313 if (ctx->ifc_sysctl_nrxds[i] != 0) 4314 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4315 else 4316 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4317 } 4318 4319 for (i = 0; i < sctx->isc_nrxqs; i++) { 4320 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4321 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4322 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4323 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4324 } 4325 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4326 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4327 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4328 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4329 } 4330 } 4331 4332 for (i = 0; i < sctx->isc_ntxqs; i++) { 4333 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4334 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4335 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4336 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4337 } 4338 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4339 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4340 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4341 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4342 } 4343 } 4344 } 4345 4346 int 4347 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4348 { 4349 int err, rid, msix; 4350 if_ctx_t ctx; 4351 if_t ifp; 4352 if_softc_ctx_t scctx; 4353 int i; 4354 uint16_t main_txq; 4355 uint16_t main_rxq; 4356 4357 4358 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4359 4360 if (sc == NULL) { 4361 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4362 device_set_softc(dev, ctx); 4363 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4364 } 4365 4366 ctx->ifc_sctx = sctx; 4367 ctx->ifc_dev = dev; 4368 ctx->ifc_softc = sc; 4369 4370 if ((err = iflib_register(ctx)) != 0) { 4371 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4372 free(sc, M_IFLIB); 4373 free(ctx, M_IFLIB); 4374 device_printf(dev, "iflib_register failed %d\n", err); 4375 return (err); 4376 } 4377 iflib_add_device_sysctl_pre(ctx); 4378 4379 scctx = &ctx->ifc_softc_ctx; 4380 ifp = ctx->ifc_ifp; 4381 4382 iflib_reset_qvalues(ctx); 4383 CTX_LOCK(ctx); 4384 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4385 CTX_UNLOCK(ctx); 4386 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4387 return (err); 4388 } 4389 _iflib_pre_assert(scctx); 4390 ctx->ifc_txrx = *scctx->isc_txrx; 4391 4392 #ifdef INVARIANTS 4393 MPASS(scctx->isc_capabilities); 4394 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4395 MPASS(scctx->isc_tx_csum_flags); 4396 #endif 4397 4398 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS); 4399 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4400 4401 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4402 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4403 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4404 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4405 4406 #ifdef ACPI_DMAR 4407 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4408 ctx->ifc_flags |= IFC_DMAR; 4409 #elif !(defined(__i386__) || defined(__amd64__)) 4410 /* set unconditionally for !x86 */ 4411 ctx->ifc_flags |= IFC_DMAR; 4412 #endif 4413 4414 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4415 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4416 4417 /* XXX change for per-queue sizes */ 4418 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4419 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4420 for (i = 0; i < sctx->isc_nrxqs; i++) { 4421 if (!powerof2(scctx->isc_nrxd[i])) { 4422 /* round down instead? */ 4423 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4424 err = EINVAL; 4425 goto fail; 4426 } 4427 } 4428 for (i = 0; i < sctx->isc_ntxqs; i++) { 4429 if (!powerof2(scctx->isc_ntxd[i])) { 4430 device_printf(dev, 4431 "# tx descriptors must be a power of 2"); 4432 err = EINVAL; 4433 goto fail; 4434 } 4435 } 4436 4437 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4438 MAX_SINGLE_PACKET_FRACTION) 4439 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4440 MAX_SINGLE_PACKET_FRACTION); 4441 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4442 MAX_SINGLE_PACKET_FRACTION) 4443 scctx->isc_tx_tso_segments_max = max(1, 4444 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4445 4446 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4447 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4448 /* 4449 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4450 * but some MACs do. 4451 */ 4452 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4453 IP_MAXPACKET)); 4454 /* 4455 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4456 * into account. In the worst case, each of these calls will 4457 * add another mbuf and, thus, the requirement for another DMA 4458 * segment. So for best performance, it doesn't make sense to 4459 * advertize a maximum of TSO segments that typically will 4460 * require defragmentation in iflib_encap(). 4461 */ 4462 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4463 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4464 } 4465 if (scctx->isc_rss_table_size == 0) 4466 scctx->isc_rss_table_size = 64; 4467 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4468 4469 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4470 /* XXX format name */ 4471 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4472 4473 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4474 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4475 device_printf(dev, "Unable to fetch CPU list\n"); 4476 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4477 } 4478 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4479 4480 /* 4481 ** Now setup MSI or MSI/X, should 4482 ** return us the number of supported 4483 ** vectors. (Will be 1 for MSI) 4484 */ 4485 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4486 msix = scctx->isc_vectors; 4487 } else if (scctx->isc_msix_bar != 0) 4488 /* 4489 * The simple fact that isc_msix_bar is not 0 does not mean we 4490 * we have a good value there that is known to work. 4491 */ 4492 msix = iflib_msix_init(ctx); 4493 else { 4494 scctx->isc_vectors = 1; 4495 scctx->isc_ntxqsets = 1; 4496 scctx->isc_nrxqsets = 1; 4497 scctx->isc_intr = IFLIB_INTR_LEGACY; 4498 msix = 0; 4499 } 4500 /* Get memory for the station queues */ 4501 if ((err = iflib_queues_alloc(ctx))) { 4502 device_printf(dev, "Unable to allocate queue memory\n"); 4503 goto fail; 4504 } 4505 4506 if ((err = iflib_qset_structures_setup(ctx))) 4507 goto fail_queues; 4508 4509 /* 4510 * Group taskqueues aren't properly set up until SMP is started, 4511 * so we disable interrupts until we can handle them post 4512 * SI_SUB_SMP. 4513 * 4514 * XXX: disabling interrupts doesn't actually work, at least for 4515 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4516 * we do null handling and depend on this not causing too large an 4517 * interrupt storm. 4518 */ 4519 IFDI_INTR_DISABLE(ctx); 4520 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4521 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4522 goto fail_intr_free; 4523 } 4524 if (msix <= 1) { 4525 rid = 0; 4526 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4527 MPASS(msix == 1); 4528 rid = 1; 4529 } 4530 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4531 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4532 goto fail_intr_free; 4533 } 4534 } 4535 4536 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4537 4538 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4539 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4540 goto fail_detach; 4541 } 4542 4543 /* 4544 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4545 * This must appear after the call to ether_ifattach() because 4546 * ether_ifattach() sets if_hdrlen to the default value. 4547 */ 4548 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4549 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4550 4551 if ((err = iflib_netmap_attach(ctx))) { 4552 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4553 goto fail_detach; 4554 } 4555 *ctxp = ctx; 4556 4557 NETDUMP_SET(ctx->ifc_ifp, iflib); 4558 4559 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4560 iflib_add_device_sysctl_post(ctx); 4561 ctx->ifc_flags |= IFC_INIT_DONE; 4562 CTX_UNLOCK(ctx); 4563 return (0); 4564 fail_detach: 4565 ether_ifdetach(ctx->ifc_ifp); 4566 fail_intr_free: 4567 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4568 pci_release_msi(ctx->ifc_dev); 4569 fail_queues: 4570 iflib_tx_structures_free(ctx); 4571 iflib_rx_structures_free(ctx); 4572 fail: 4573 IFDI_DETACH(ctx); 4574 CTX_UNLOCK(ctx); 4575 return (err); 4576 } 4577 4578 int 4579 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4580 struct iflib_cloneattach_ctx *clctx) 4581 { 4582 int err; 4583 if_ctx_t ctx; 4584 if_t ifp; 4585 if_softc_ctx_t scctx; 4586 int i; 4587 void *sc; 4588 uint16_t main_txq; 4589 uint16_t main_rxq; 4590 4591 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4592 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4593 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4594 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4595 ctx->ifc_flags |= IFC_PSEUDO; 4596 4597 ctx->ifc_sctx = sctx; 4598 ctx->ifc_softc = sc; 4599 ctx->ifc_dev = dev; 4600 4601 if ((err = iflib_register(ctx)) != 0) { 4602 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4603 free(sc, M_IFLIB); 4604 free(ctx, M_IFLIB); 4605 return (err); 4606 } 4607 iflib_add_device_sysctl_pre(ctx); 4608 4609 scctx = &ctx->ifc_softc_ctx; 4610 ifp = ctx->ifc_ifp; 4611 4612 /* 4613 * XXX sanity check that ntxd & nrxd are a power of 2 4614 */ 4615 iflib_reset_qvalues(ctx); 4616 4617 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4618 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4619 return (err); 4620 } 4621 if (sctx->isc_flags & IFLIB_GEN_MAC) 4622 iflib_gen_mac(ctx); 4623 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4624 clctx->cc_params)) != 0) { 4625 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4626 return (err); 4627 } 4628 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4629 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 4630 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO); 4631 4632 #ifdef INVARIANTS 4633 MPASS(scctx->isc_capabilities); 4634 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4635 MPASS(scctx->isc_tx_csum_flags); 4636 #endif 4637 4638 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4639 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4640 4641 ifp->if_flags |= IFF_NOGROUP; 4642 if (sctx->isc_flags & IFLIB_PSEUDO) { 4643 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4644 4645 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4646 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4647 goto fail_detach; 4648 } 4649 *ctxp = ctx; 4650 4651 /* 4652 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4653 * This must appear after the call to ether_ifattach() because 4654 * ether_ifattach() sets if_hdrlen to the default value. 4655 */ 4656 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4657 if_setifheaderlen(ifp, 4658 sizeof(struct ether_vlan_header)); 4659 4660 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4661 iflib_add_device_sysctl_post(ctx); 4662 ctx->ifc_flags |= IFC_INIT_DONE; 4663 return (0); 4664 } 4665 _iflib_pre_assert(scctx); 4666 ctx->ifc_txrx = *scctx->isc_txrx; 4667 4668 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4669 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4670 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4671 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4672 4673 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4674 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4675 4676 /* XXX change for per-queue sizes */ 4677 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4678 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4679 for (i = 0; i < sctx->isc_nrxqs; i++) { 4680 if (!powerof2(scctx->isc_nrxd[i])) { 4681 /* round down instead? */ 4682 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4683 err = EINVAL; 4684 goto fail; 4685 } 4686 } 4687 for (i = 0; i < sctx->isc_ntxqs; i++) { 4688 if (!powerof2(scctx->isc_ntxd[i])) { 4689 device_printf(dev, 4690 "# tx descriptors must be a power of 2"); 4691 err = EINVAL; 4692 goto fail; 4693 } 4694 } 4695 4696 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4697 MAX_SINGLE_PACKET_FRACTION) 4698 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4699 MAX_SINGLE_PACKET_FRACTION); 4700 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4701 MAX_SINGLE_PACKET_FRACTION) 4702 scctx->isc_tx_tso_segments_max = max(1, 4703 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4704 4705 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4706 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4707 /* 4708 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4709 * but some MACs do. 4710 */ 4711 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4712 IP_MAXPACKET)); 4713 /* 4714 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4715 * into account. In the worst case, each of these calls will 4716 * add another mbuf and, thus, the requirement for another DMA 4717 * segment. So for best performance, it doesn't make sense to 4718 * advertize a maximum of TSO segments that typically will 4719 * require defragmentation in iflib_encap(). 4720 */ 4721 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4722 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4723 } 4724 if (scctx->isc_rss_table_size == 0) 4725 scctx->isc_rss_table_size = 64; 4726 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4727 4728 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4729 /* XXX format name */ 4730 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4731 4732 /* XXX --- can support > 1 -- but keep it simple for now */ 4733 scctx->isc_intr = IFLIB_INTR_LEGACY; 4734 4735 /* Get memory for the station queues */ 4736 if ((err = iflib_queues_alloc(ctx))) { 4737 device_printf(dev, "Unable to allocate queue memory\n"); 4738 goto fail; 4739 } 4740 4741 if ((err = iflib_qset_structures_setup(ctx))) { 4742 device_printf(dev, "qset structure setup failed %d\n", err); 4743 goto fail_queues; 4744 } 4745 4746 /* 4747 * XXX What if anything do we want to do about interrupts? 4748 */ 4749 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4750 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4751 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4752 goto fail_detach; 4753 } 4754 4755 /* 4756 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4757 * This must appear after the call to ether_ifattach() because 4758 * ether_ifattach() sets if_hdrlen to the default value. 4759 */ 4760 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4761 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4762 4763 /* XXX handle more than one queue */ 4764 for (i = 0; i < scctx->isc_nrxqsets; i++) 4765 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4766 4767 *ctxp = ctx; 4768 4769 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4770 iflib_add_device_sysctl_post(ctx); 4771 ctx->ifc_flags |= IFC_INIT_DONE; 4772 return (0); 4773 fail_detach: 4774 ether_ifdetach(ctx->ifc_ifp); 4775 fail_queues: 4776 iflib_tx_structures_free(ctx); 4777 iflib_rx_structures_free(ctx); 4778 fail: 4779 IFDI_DETACH(ctx); 4780 return (err); 4781 } 4782 4783 int 4784 iflib_pseudo_deregister(if_ctx_t ctx) 4785 { 4786 if_t ifp = ctx->ifc_ifp; 4787 iflib_txq_t txq; 4788 iflib_rxq_t rxq; 4789 int i, j; 4790 struct taskqgroup *tqg; 4791 iflib_fl_t fl; 4792 4793 /* Unregister VLAN events */ 4794 if (ctx->ifc_vlan_attach_event != NULL) 4795 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4796 if (ctx->ifc_vlan_detach_event != NULL) 4797 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4798 4799 ether_ifdetach(ifp); 4800 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4801 CTX_LOCK_DESTROY(ctx); 4802 /* XXX drain any dependent tasks */ 4803 tqg = qgroup_if_io_tqg; 4804 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4805 callout_drain(&txq->ift_timer); 4806 if (txq->ift_task.gt_uniq != NULL) 4807 taskqgroup_detach(tqg, &txq->ift_task); 4808 } 4809 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4810 if (rxq->ifr_task.gt_uniq != NULL) 4811 taskqgroup_detach(tqg, &rxq->ifr_task); 4812 4813 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4814 free(fl->ifl_rx_bitmap, M_IFLIB); 4815 } 4816 tqg = qgroup_if_config_tqg; 4817 if (ctx->ifc_admin_task.gt_uniq != NULL) 4818 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4819 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4820 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4821 4822 if_free(ifp); 4823 4824 iflib_tx_structures_free(ctx); 4825 iflib_rx_structures_free(ctx); 4826 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4827 free(ctx->ifc_softc, M_IFLIB); 4828 free(ctx, M_IFLIB); 4829 return (0); 4830 } 4831 4832 int 4833 iflib_device_attach(device_t dev) 4834 { 4835 if_ctx_t ctx; 4836 if_shared_ctx_t sctx; 4837 4838 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4839 return (ENOTSUP); 4840 4841 pci_enable_busmaster(dev); 4842 4843 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4844 } 4845 4846 int 4847 iflib_device_deregister(if_ctx_t ctx) 4848 { 4849 if_t ifp = ctx->ifc_ifp; 4850 iflib_txq_t txq; 4851 iflib_rxq_t rxq; 4852 device_t dev = ctx->ifc_dev; 4853 int i, j; 4854 struct taskqgroup *tqg; 4855 iflib_fl_t fl; 4856 4857 /* Make sure VLANS are not using driver */ 4858 if (if_vlantrunkinuse(ifp)) { 4859 device_printf(dev,"Vlan in use, detach first\n"); 4860 return (EBUSY); 4861 } 4862 4863 CTX_LOCK(ctx); 4864 ctx->ifc_in_detach = 1; 4865 iflib_stop(ctx); 4866 CTX_UNLOCK(ctx); 4867 4868 /* Unregister VLAN events */ 4869 if (ctx->ifc_vlan_attach_event != NULL) 4870 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4871 if (ctx->ifc_vlan_detach_event != NULL) 4872 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4873 4874 iflib_netmap_detach(ifp); 4875 ether_ifdetach(ifp); 4876 if (ctx->ifc_led_dev != NULL) 4877 led_destroy(ctx->ifc_led_dev); 4878 /* XXX drain any dependent tasks */ 4879 tqg = qgroup_if_io_tqg; 4880 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4881 callout_drain(&txq->ift_timer); 4882 if (txq->ift_task.gt_uniq != NULL) 4883 taskqgroup_detach(tqg, &txq->ift_task); 4884 } 4885 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4886 if (rxq->ifr_task.gt_uniq != NULL) 4887 taskqgroup_detach(tqg, &rxq->ifr_task); 4888 4889 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4890 free(fl->ifl_rx_bitmap, M_IFLIB); 4891 4892 } 4893 tqg = qgroup_if_config_tqg; 4894 if (ctx->ifc_admin_task.gt_uniq != NULL) 4895 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4896 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4897 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4898 CTX_LOCK(ctx); 4899 IFDI_DETACH(ctx); 4900 CTX_UNLOCK(ctx); 4901 4902 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4903 CTX_LOCK_DESTROY(ctx); 4904 device_set_softc(ctx->ifc_dev, NULL); 4905 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4906 pci_release_msi(dev); 4907 } 4908 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4909 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4910 } 4911 if (ctx->ifc_msix_mem != NULL) { 4912 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4913 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4914 ctx->ifc_msix_mem = NULL; 4915 } 4916 4917 bus_generic_detach(dev); 4918 if_free(ifp); 4919 4920 iflib_tx_structures_free(ctx); 4921 iflib_rx_structures_free(ctx); 4922 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4923 free(ctx->ifc_softc, M_IFLIB); 4924 free(ctx, M_IFLIB); 4925 return (0); 4926 } 4927 4928 4929 int 4930 iflib_device_detach(device_t dev) 4931 { 4932 if_ctx_t ctx = device_get_softc(dev); 4933 4934 return (iflib_device_deregister(ctx)); 4935 } 4936 4937 int 4938 iflib_device_suspend(device_t dev) 4939 { 4940 if_ctx_t ctx = device_get_softc(dev); 4941 4942 CTX_LOCK(ctx); 4943 IFDI_SUSPEND(ctx); 4944 CTX_UNLOCK(ctx); 4945 4946 return bus_generic_suspend(dev); 4947 } 4948 int 4949 iflib_device_shutdown(device_t dev) 4950 { 4951 if_ctx_t ctx = device_get_softc(dev); 4952 4953 CTX_LOCK(ctx); 4954 IFDI_SHUTDOWN(ctx); 4955 CTX_UNLOCK(ctx); 4956 4957 return bus_generic_suspend(dev); 4958 } 4959 4960 4961 int 4962 iflib_device_resume(device_t dev) 4963 { 4964 if_ctx_t ctx = device_get_softc(dev); 4965 iflib_txq_t txq = ctx->ifc_txqs; 4966 4967 CTX_LOCK(ctx); 4968 IFDI_RESUME(ctx); 4969 iflib_init_locked(ctx); 4970 CTX_UNLOCK(ctx); 4971 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4972 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4973 4974 return (bus_generic_resume(dev)); 4975 } 4976 4977 int 4978 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4979 { 4980 int error; 4981 if_ctx_t ctx = device_get_softc(dev); 4982 4983 CTX_LOCK(ctx); 4984 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4985 CTX_UNLOCK(ctx); 4986 4987 return (error); 4988 } 4989 4990 void 4991 iflib_device_iov_uninit(device_t dev) 4992 { 4993 if_ctx_t ctx = device_get_softc(dev); 4994 4995 CTX_LOCK(ctx); 4996 IFDI_IOV_UNINIT(ctx); 4997 CTX_UNLOCK(ctx); 4998 } 4999 5000 int 5001 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5002 { 5003 int error; 5004 if_ctx_t ctx = device_get_softc(dev); 5005 5006 CTX_LOCK(ctx); 5007 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5008 CTX_UNLOCK(ctx); 5009 5010 return (error); 5011 } 5012 5013 /********************************************************************* 5014 * 5015 * MODULE FUNCTION DEFINITIONS 5016 * 5017 **********************************************************************/ 5018 5019 /* 5020 * - Start a fast taskqueue thread for each core 5021 * - Start a taskqueue for control operations 5022 */ 5023 static int 5024 iflib_module_init(void) 5025 { 5026 return (0); 5027 } 5028 5029 static int 5030 iflib_module_event_handler(module_t mod, int what, void *arg) 5031 { 5032 int err; 5033 5034 switch (what) { 5035 case MOD_LOAD: 5036 if ((err = iflib_module_init()) != 0) 5037 return (err); 5038 break; 5039 case MOD_UNLOAD: 5040 return (EBUSY); 5041 default: 5042 return (EOPNOTSUPP); 5043 } 5044 5045 return (0); 5046 } 5047 5048 /********************************************************************* 5049 * 5050 * PUBLIC FUNCTION DEFINITIONS 5051 * ordered as in iflib.h 5052 * 5053 **********************************************************************/ 5054 5055 5056 static void 5057 _iflib_assert(if_shared_ctx_t sctx) 5058 { 5059 MPASS(sctx->isc_tx_maxsize); 5060 MPASS(sctx->isc_tx_maxsegsize); 5061 5062 MPASS(sctx->isc_rx_maxsize); 5063 MPASS(sctx->isc_rx_nsegments); 5064 MPASS(sctx->isc_rx_maxsegsize); 5065 5066 MPASS(sctx->isc_nrxd_min[0]); 5067 MPASS(sctx->isc_nrxd_max[0]); 5068 MPASS(sctx->isc_nrxd_default[0]); 5069 MPASS(sctx->isc_ntxd_min[0]); 5070 MPASS(sctx->isc_ntxd_max[0]); 5071 MPASS(sctx->isc_ntxd_default[0]); 5072 } 5073 5074 static void 5075 _iflib_pre_assert(if_softc_ctx_t scctx) 5076 { 5077 5078 MPASS(scctx->isc_txrx->ift_txd_encap); 5079 MPASS(scctx->isc_txrx->ift_txd_flush); 5080 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5081 MPASS(scctx->isc_txrx->ift_rxd_available); 5082 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5083 MPASS(scctx->isc_txrx->ift_rxd_refill); 5084 MPASS(scctx->isc_txrx->ift_rxd_flush); 5085 } 5086 5087 static int 5088 iflib_register(if_ctx_t ctx) 5089 { 5090 if_shared_ctx_t sctx = ctx->ifc_sctx; 5091 driver_t *driver = sctx->isc_driver; 5092 device_t dev = ctx->ifc_dev; 5093 if_t ifp; 5094 5095 _iflib_assert(sctx); 5096 5097 CTX_LOCK_INIT(ctx); 5098 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5099 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 5100 if (ifp == NULL) { 5101 device_printf(dev, "can not allocate ifnet structure\n"); 5102 return (ENOMEM); 5103 } 5104 5105 /* 5106 * Initialize our context's device specific methods 5107 */ 5108 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5109 kobj_class_compile((kobj_class_t) driver); 5110 driver->refs++; 5111 5112 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5113 if_setsoftc(ifp, ctx); 5114 if_setdev(ifp, dev); 5115 if_setinitfn(ifp, iflib_if_init); 5116 if_setioctlfn(ifp, iflib_if_ioctl); 5117 if_settransmitfn(ifp, iflib_if_transmit); 5118 if_setqflushfn(ifp, iflib_if_qflush); 5119 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5120 5121 ctx->ifc_vlan_attach_event = 5122 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5123 EVENTHANDLER_PRI_FIRST); 5124 ctx->ifc_vlan_detach_event = 5125 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5126 EVENTHANDLER_PRI_FIRST); 5127 5128 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 5129 iflib_media_change, iflib_media_status); 5130 5131 return (0); 5132 } 5133 5134 5135 static int 5136 iflib_queues_alloc(if_ctx_t ctx) 5137 { 5138 if_shared_ctx_t sctx = ctx->ifc_sctx; 5139 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5140 device_t dev = ctx->ifc_dev; 5141 int nrxqsets = scctx->isc_nrxqsets; 5142 int ntxqsets = scctx->isc_ntxqsets; 5143 iflib_txq_t txq; 5144 iflib_rxq_t rxq; 5145 iflib_fl_t fl = NULL; 5146 int i, j, cpu, err, txconf, rxconf; 5147 iflib_dma_info_t ifdip; 5148 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5149 uint32_t *txqsizes = scctx->isc_txqsizes; 5150 uint8_t nrxqs = sctx->isc_nrxqs; 5151 uint8_t ntxqs = sctx->isc_ntxqs; 5152 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5153 caddr_t *vaddrs; 5154 uint64_t *paddrs; 5155 5156 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5157 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5158 5159 /* Allocate the TX ring struct memory */ 5160 if (!(ctx->ifc_txqs = 5161 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5162 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5163 device_printf(dev, "Unable to allocate TX ring memory\n"); 5164 err = ENOMEM; 5165 goto fail; 5166 } 5167 5168 /* Now allocate the RX */ 5169 if (!(ctx->ifc_rxqs = 5170 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5171 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5172 device_printf(dev, "Unable to allocate RX ring memory\n"); 5173 err = ENOMEM; 5174 goto rx_fail; 5175 } 5176 5177 txq = ctx->ifc_txqs; 5178 rxq = ctx->ifc_rxqs; 5179 5180 /* 5181 * XXX handle allocation failure 5182 */ 5183 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5184 /* Set up some basics */ 5185 5186 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 5187 device_printf(dev, "failed to allocate iflib_dma_info\n"); 5188 err = ENOMEM; 5189 goto err_tx_desc; 5190 } 5191 txq->ift_ifdi = ifdip; 5192 for (j = 0; j < ntxqs; j++, ifdip++) { 5193 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 5194 device_printf(dev, "Unable to allocate Descriptor memory\n"); 5195 err = ENOMEM; 5196 goto err_tx_desc; 5197 } 5198 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5199 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5200 } 5201 txq->ift_ctx = ctx; 5202 txq->ift_id = i; 5203 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5204 txq->ift_br_offset = 1; 5205 } else { 5206 txq->ift_br_offset = 0; 5207 } 5208 /* XXX fix this */ 5209 txq->ift_timer.c_cpu = cpu; 5210 5211 if (iflib_txsd_alloc(txq)) { 5212 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5213 err = ENOMEM; 5214 goto err_tx_desc; 5215 } 5216 5217 /* Initialize the TX lock */ 5218 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 5219 device_get_nameunit(dev), txq->ift_id); 5220 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5221 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5222 5223 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 5224 device_get_nameunit(dev), txq->ift_id); 5225 5226 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5227 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5228 if (err) { 5229 /* XXX free any allocated rings */ 5230 device_printf(dev, "Unable to allocate buf_ring\n"); 5231 goto err_tx_desc; 5232 } 5233 } 5234 5235 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5236 /* Set up some basics */ 5237 5238 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 5239 device_printf(dev, "failed to allocate iflib_dma_info\n"); 5240 err = ENOMEM; 5241 goto err_tx_desc; 5242 } 5243 5244 rxq->ifr_ifdi = ifdip; 5245 /* XXX this needs to be changed if #rx queues != #tx queues */ 5246 rxq->ifr_ntxqirq = 1; 5247 rxq->ifr_txqid[0] = i; 5248 for (j = 0; j < nrxqs; j++, ifdip++) { 5249 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 5250 device_printf(dev, "Unable to allocate Descriptor memory\n"); 5251 err = ENOMEM; 5252 goto err_tx_desc; 5253 } 5254 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5255 } 5256 rxq->ifr_ctx = ctx; 5257 rxq->ifr_id = i; 5258 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5259 rxq->ifr_fl_offset = 1; 5260 } else { 5261 rxq->ifr_fl_offset = 0; 5262 } 5263 rxq->ifr_nfl = nfree_lists; 5264 if (!(fl = 5265 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5266 device_printf(dev, "Unable to allocate free list memory\n"); 5267 err = ENOMEM; 5268 goto err_tx_desc; 5269 } 5270 rxq->ifr_fl = fl; 5271 for (j = 0; j < nfree_lists; j++) { 5272 fl[j].ifl_rxq = rxq; 5273 fl[j].ifl_id = j; 5274 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5275 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5276 } 5277 /* Allocate receive buffers for the ring*/ 5278 if (iflib_rxsd_alloc(rxq)) { 5279 device_printf(dev, 5280 "Critical Failure setting up receive buffers\n"); 5281 err = ENOMEM; 5282 goto err_rx_desc; 5283 } 5284 5285 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5286 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 5287 } 5288 5289 /* TXQs */ 5290 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5291 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5292 for (i = 0; i < ntxqsets; i++) { 5293 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5294 5295 for (j = 0; j < ntxqs; j++, di++) { 5296 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5297 paddrs[i*ntxqs + j] = di->idi_paddr; 5298 } 5299 } 5300 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5301 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 5302 iflib_tx_structures_free(ctx); 5303 free(vaddrs, M_IFLIB); 5304 free(paddrs, M_IFLIB); 5305 goto err_rx_desc; 5306 } 5307 free(vaddrs, M_IFLIB); 5308 free(paddrs, M_IFLIB); 5309 5310 /* RXQs */ 5311 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5312 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5313 for (i = 0; i < nrxqsets; i++) { 5314 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5315 5316 for (j = 0; j < nrxqs; j++, di++) { 5317 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5318 paddrs[i*nrxqs + j] = di->idi_paddr; 5319 } 5320 } 5321 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5322 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 5323 iflib_tx_structures_free(ctx); 5324 free(vaddrs, M_IFLIB); 5325 free(paddrs, M_IFLIB); 5326 goto err_rx_desc; 5327 } 5328 free(vaddrs, M_IFLIB); 5329 free(paddrs, M_IFLIB); 5330 5331 return (0); 5332 5333 /* XXX handle allocation failure changes */ 5334 err_rx_desc: 5335 err_tx_desc: 5336 rx_fail: 5337 if (ctx->ifc_rxqs != NULL) 5338 free(ctx->ifc_rxqs, M_IFLIB); 5339 ctx->ifc_rxqs = NULL; 5340 if (ctx->ifc_txqs != NULL) 5341 free(ctx->ifc_txqs, M_IFLIB); 5342 ctx->ifc_txqs = NULL; 5343 fail: 5344 return (err); 5345 } 5346 5347 static int 5348 iflib_tx_structures_setup(if_ctx_t ctx) 5349 { 5350 iflib_txq_t txq = ctx->ifc_txqs; 5351 int i; 5352 5353 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5354 iflib_txq_setup(txq); 5355 5356 return (0); 5357 } 5358 5359 static void 5360 iflib_tx_structures_free(if_ctx_t ctx) 5361 { 5362 iflib_txq_t txq = ctx->ifc_txqs; 5363 int i, j; 5364 5365 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5366 iflib_txq_destroy(txq); 5367 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 5368 iflib_dma_free(&txq->ift_ifdi[j]); 5369 } 5370 free(ctx->ifc_txqs, M_IFLIB); 5371 ctx->ifc_txqs = NULL; 5372 IFDI_QUEUES_FREE(ctx); 5373 } 5374 5375 /********************************************************************* 5376 * 5377 * Initialize all receive rings. 5378 * 5379 **********************************************************************/ 5380 static int 5381 iflib_rx_structures_setup(if_ctx_t ctx) 5382 { 5383 iflib_rxq_t rxq = ctx->ifc_rxqs; 5384 int q; 5385 #if defined(INET6) || defined(INET) 5386 int i, err; 5387 #endif 5388 5389 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5390 #if defined(INET6) || defined(INET) 5391 tcp_lro_free(&rxq->ifr_lc); 5392 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5393 TCP_LRO_ENTRIES, min(1024, 5394 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 5395 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 5396 goto fail; 5397 } 5398 rxq->ifr_lro_enabled = TRUE; 5399 #endif 5400 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5401 } 5402 return (0); 5403 #if defined(INET6) || defined(INET) 5404 fail: 5405 /* 5406 * Free RX software descriptors allocated so far, we will only handle 5407 * the rings that completed, the failing case will have 5408 * cleaned up for itself. 'q' failed, so its the terminus. 5409 */ 5410 rxq = ctx->ifc_rxqs; 5411 for (i = 0; i < q; ++i, rxq++) { 5412 iflib_rx_sds_free(rxq); 5413 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5414 } 5415 return (err); 5416 #endif 5417 } 5418 5419 /********************************************************************* 5420 * 5421 * Free all receive rings. 5422 * 5423 **********************************************************************/ 5424 static void 5425 iflib_rx_structures_free(if_ctx_t ctx) 5426 { 5427 iflib_rxq_t rxq = ctx->ifc_rxqs; 5428 5429 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5430 iflib_rx_sds_free(rxq); 5431 } 5432 } 5433 5434 static int 5435 iflib_qset_structures_setup(if_ctx_t ctx) 5436 { 5437 int err; 5438 5439 /* 5440 * It is expected that the caller takes care of freeing queues if this 5441 * fails. 5442 */ 5443 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5444 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5445 return (err); 5446 } 5447 5448 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5449 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5450 5451 return (err); 5452 } 5453 5454 int 5455 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5456 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5457 { 5458 5459 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5460 } 5461 5462 #ifdef SMP 5463 static int 5464 find_nth(if_ctx_t ctx, int qid) 5465 { 5466 cpuset_t cpus; 5467 int i, cpuid, eqid, count; 5468 5469 CPU_COPY(&ctx->ifc_cpus, &cpus); 5470 count = CPU_COUNT(&cpus); 5471 eqid = qid % count; 5472 /* clear up to the qid'th bit */ 5473 for (i = 0; i < eqid; i++) { 5474 cpuid = CPU_FFS(&cpus); 5475 MPASS(cpuid != 0); 5476 CPU_CLR(cpuid-1, &cpus); 5477 } 5478 cpuid = CPU_FFS(&cpus); 5479 MPASS(cpuid != 0); 5480 return (cpuid-1); 5481 } 5482 5483 #ifdef SCHED_ULE 5484 extern struct cpu_group *cpu_top; /* CPU topology */ 5485 5486 static int 5487 find_child_with_core(int cpu, struct cpu_group *grp) 5488 { 5489 int i; 5490 5491 if (grp->cg_children == 0) 5492 return -1; 5493 5494 MPASS(grp->cg_child); 5495 for (i = 0; i < grp->cg_children; i++) { 5496 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5497 return i; 5498 } 5499 5500 return -1; 5501 } 5502 5503 /* 5504 * Find the nth "close" core to the specified core 5505 * "close" is defined as the deepest level that shares 5506 * at least an L2 cache. With threads, this will be 5507 * threads on the same core. If the sahred cache is L3 5508 * or higher, simply returns the same core. 5509 */ 5510 static int 5511 find_close_core(int cpu, int core_offset) 5512 { 5513 struct cpu_group *grp; 5514 int i; 5515 int fcpu; 5516 cpuset_t cs; 5517 5518 grp = cpu_top; 5519 if (grp == NULL) 5520 return cpu; 5521 i = 0; 5522 while ((i = find_child_with_core(cpu, grp)) != -1) { 5523 /* If the child only has one cpu, don't descend */ 5524 if (grp->cg_child[i].cg_count <= 1) 5525 break; 5526 grp = &grp->cg_child[i]; 5527 } 5528 5529 /* If they don't share at least an L2 cache, use the same CPU */ 5530 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5531 return cpu; 5532 5533 /* Now pick one */ 5534 CPU_COPY(&grp->cg_mask, &cs); 5535 5536 /* Add the selected CPU offset to core offset. */ 5537 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5538 if (fcpu - 1 == cpu) 5539 break; 5540 CPU_CLR(fcpu - 1, &cs); 5541 } 5542 MPASS(fcpu); 5543 5544 core_offset += i; 5545 5546 CPU_COPY(&grp->cg_mask, &cs); 5547 for (i = core_offset % grp->cg_count; i > 0; i--) { 5548 MPASS(CPU_FFS(&cs)); 5549 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5550 } 5551 MPASS(CPU_FFS(&cs)); 5552 return CPU_FFS(&cs) - 1; 5553 } 5554 #else 5555 static int 5556 find_close_core(int cpu, int core_offset __unused) 5557 { 5558 return cpu; 5559 } 5560 #endif 5561 5562 static int 5563 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5564 { 5565 switch (type) { 5566 case IFLIB_INTR_TX: 5567 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5568 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5569 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5570 case IFLIB_INTR_RX: 5571 case IFLIB_INTR_RXTX: 5572 /* RX queues get the specified core */ 5573 return qid / CPU_COUNT(&ctx->ifc_cpus); 5574 default: 5575 return -1; 5576 } 5577 } 5578 #else 5579 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5580 #define find_close_core(cpuid, tid) CPU_FIRST() 5581 #define find_nth(ctx, gid) CPU_FIRST() 5582 #endif 5583 5584 /* Just to avoid copy/paste */ 5585 static inline int 5586 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid, 5587 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, const char *name) 5588 { 5589 int cpuid; 5590 int err, tid; 5591 5592 cpuid = find_nth(ctx, qid); 5593 tid = get_core_offset(ctx, type, qid); 5594 MPASS(tid >= 0); 5595 cpuid = find_close_core(cpuid, tid); 5596 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name); 5597 if (err) { 5598 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err); 5599 return (err); 5600 } 5601 #ifdef notyet 5602 if (cpuid > ctx->ifc_cpuid_highest) 5603 ctx->ifc_cpuid_highest = cpuid; 5604 #endif 5605 return 0; 5606 } 5607 5608 int 5609 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5610 iflib_intr_type_t type, driver_filter_t *filter, 5611 void *filter_arg, int qid, const char *name) 5612 { 5613 struct grouptask *gtask; 5614 struct taskqgroup *tqg; 5615 iflib_filter_info_t info; 5616 gtask_fn_t *fn; 5617 int tqrid, err; 5618 driver_filter_t *intr_fast; 5619 void *q; 5620 5621 info = &ctx->ifc_filter_info; 5622 tqrid = rid; 5623 5624 switch (type) { 5625 /* XXX merge tx/rx for netmap? */ 5626 case IFLIB_INTR_TX: 5627 q = &ctx->ifc_txqs[qid]; 5628 info = &ctx->ifc_txqs[qid].ift_filter_info; 5629 gtask = &ctx->ifc_txqs[qid].ift_task; 5630 tqg = qgroup_if_io_tqg; 5631 fn = _task_fn_tx; 5632 intr_fast = iflib_fast_intr; 5633 GROUPTASK_INIT(gtask, 0, fn, q); 5634 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5635 break; 5636 case IFLIB_INTR_RX: 5637 q = &ctx->ifc_rxqs[qid]; 5638 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5639 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5640 tqg = qgroup_if_io_tqg; 5641 fn = _task_fn_rx; 5642 intr_fast = iflib_fast_intr; 5643 GROUPTASK_INIT(gtask, 0, fn, q); 5644 break; 5645 case IFLIB_INTR_RXTX: 5646 q = &ctx->ifc_rxqs[qid]; 5647 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5648 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5649 tqg = qgroup_if_io_tqg; 5650 fn = _task_fn_rx; 5651 intr_fast = iflib_fast_intr_rxtx; 5652 GROUPTASK_INIT(gtask, 0, fn, q); 5653 break; 5654 case IFLIB_INTR_ADMIN: 5655 q = ctx; 5656 tqrid = -1; 5657 info = &ctx->ifc_filter_info; 5658 gtask = &ctx->ifc_admin_task; 5659 tqg = qgroup_if_config_tqg; 5660 fn = _task_fn_admin; 5661 intr_fast = iflib_fast_intr_ctx; 5662 break; 5663 default: 5664 panic("unknown net intr type"); 5665 } 5666 5667 info->ifi_filter = filter; 5668 info->ifi_filter_arg = filter_arg; 5669 info->ifi_task = gtask; 5670 info->ifi_ctx = q; 5671 5672 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5673 if (err != 0) { 5674 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 5675 return (err); 5676 } 5677 if (type == IFLIB_INTR_ADMIN) 5678 return (0); 5679 5680 if (tqrid != -1) { 5681 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name); 5682 if (err) 5683 return (err); 5684 } else { 5685 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5686 } 5687 5688 return (0); 5689 } 5690 5691 void 5692 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 5693 { 5694 struct grouptask *gtask; 5695 struct taskqgroup *tqg; 5696 gtask_fn_t *fn; 5697 void *q; 5698 int irq_num = -1; 5699 int err; 5700 5701 switch (type) { 5702 case IFLIB_INTR_TX: 5703 q = &ctx->ifc_txqs[qid]; 5704 gtask = &ctx->ifc_txqs[qid].ift_task; 5705 tqg = qgroup_if_io_tqg; 5706 fn = _task_fn_tx; 5707 if (irq != NULL) 5708 irq_num = rman_get_start(irq->ii_res); 5709 break; 5710 case IFLIB_INTR_RX: 5711 q = &ctx->ifc_rxqs[qid]; 5712 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5713 tqg = qgroup_if_io_tqg; 5714 fn = _task_fn_rx; 5715 if (irq != NULL) 5716 irq_num = rman_get_start(irq->ii_res); 5717 break; 5718 case IFLIB_INTR_IOV: 5719 q = ctx; 5720 gtask = &ctx->ifc_vflr_task; 5721 tqg = qgroup_if_config_tqg; 5722 fn = _task_fn_iov; 5723 break; 5724 default: 5725 panic("unknown net intr type"); 5726 } 5727 GROUPTASK_INIT(gtask, 0, fn, q); 5728 if (irq_num != -1) { 5729 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name); 5730 if (err) 5731 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5732 } 5733 else { 5734 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5735 } 5736 } 5737 5738 void 5739 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5740 { 5741 if (irq->ii_tag) 5742 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5743 5744 if (irq->ii_res) 5745 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5746 } 5747 5748 static int 5749 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 5750 { 5751 iflib_txq_t txq = ctx->ifc_txqs; 5752 iflib_rxq_t rxq = ctx->ifc_rxqs; 5753 if_irq_t irq = &ctx->ifc_legacy_irq; 5754 iflib_filter_info_t info; 5755 struct grouptask *gtask; 5756 struct taskqgroup *tqg; 5757 gtask_fn_t *fn; 5758 int tqrid; 5759 void *q; 5760 int err; 5761 5762 q = &ctx->ifc_rxqs[0]; 5763 info = &rxq[0].ifr_filter_info; 5764 gtask = &rxq[0].ifr_task; 5765 tqg = qgroup_if_io_tqg; 5766 tqrid = irq->ii_rid = *rid; 5767 fn = _task_fn_rx; 5768 5769 ctx->ifc_flags |= IFC_LEGACY; 5770 info->ifi_filter = filter; 5771 info->ifi_filter_arg = filter_arg; 5772 info->ifi_task = gtask; 5773 info->ifi_ctx = ctx; 5774 5775 /* We allocate a single interrupt resource */ 5776 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5777 return (err); 5778 GROUPTASK_INIT(gtask, 0, fn, q); 5779 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5780 5781 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5782 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx"); 5783 return (0); 5784 } 5785 5786 void 5787 iflib_led_create(if_ctx_t ctx) 5788 { 5789 5790 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5791 device_get_nameunit(ctx->ifc_dev)); 5792 } 5793 5794 void 5795 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5796 { 5797 5798 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5799 } 5800 5801 void 5802 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5803 { 5804 5805 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5806 } 5807 5808 void 5809 iflib_admin_intr_deferred(if_ctx_t ctx) 5810 { 5811 #ifdef INVARIANTS 5812 struct grouptask *gtask; 5813 5814 gtask = &ctx->ifc_admin_task; 5815 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5816 #endif 5817 5818 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5819 } 5820 5821 void 5822 iflib_iov_intr_deferred(if_ctx_t ctx) 5823 { 5824 5825 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5826 } 5827 5828 void 5829 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5830 { 5831 5832 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5833 } 5834 5835 void 5836 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 5837 const char *name) 5838 { 5839 5840 GROUPTASK_INIT(gtask, 0, fn, ctx); 5841 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5842 } 5843 5844 void 5845 iflib_config_gtask_deinit(struct grouptask *gtask) 5846 { 5847 5848 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5849 } 5850 5851 void 5852 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5853 { 5854 if_t ifp = ctx->ifc_ifp; 5855 iflib_txq_t txq = ctx->ifc_txqs; 5856 5857 if_setbaudrate(ifp, baudrate); 5858 if (baudrate >= IF_Gbps(10)) { 5859 STATE_LOCK(ctx); 5860 ctx->ifc_flags |= IFC_PREFETCH; 5861 STATE_UNLOCK(ctx); 5862 } 5863 /* If link down, disable watchdog */ 5864 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5865 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5866 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5867 } 5868 ctx->ifc_link_state = link_state; 5869 if_link_state_change(ifp, link_state); 5870 } 5871 5872 static int 5873 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5874 { 5875 int credits; 5876 #ifdef INVARIANTS 5877 int credits_pre = txq->ift_cidx_processed; 5878 #endif 5879 5880 if (ctx->isc_txd_credits_update == NULL) 5881 return (0); 5882 5883 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5884 return (0); 5885 5886 txq->ift_processed += credits; 5887 txq->ift_cidx_processed += credits; 5888 5889 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5890 if (txq->ift_cidx_processed >= txq->ift_size) 5891 txq->ift_cidx_processed -= txq->ift_size; 5892 return (credits); 5893 } 5894 5895 static int 5896 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5897 { 5898 5899 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5900 budget)); 5901 } 5902 5903 void 5904 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5905 const char *description, if_int_delay_info_t info, 5906 int offset, int value) 5907 { 5908 info->iidi_ctx = ctx; 5909 info->iidi_offset = offset; 5910 info->iidi_value = value; 5911 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5912 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5913 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5914 info, 0, iflib_sysctl_int_delay, "I", description); 5915 } 5916 5917 struct sx * 5918 iflib_ctx_lock_get(if_ctx_t ctx) 5919 { 5920 5921 return (&ctx->ifc_ctx_sx); 5922 } 5923 5924 static int 5925 iflib_msix_init(if_ctx_t ctx) 5926 { 5927 device_t dev = ctx->ifc_dev; 5928 if_shared_ctx_t sctx = ctx->ifc_sctx; 5929 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5930 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5931 int iflib_num_tx_queues, iflib_num_rx_queues; 5932 int err, admincnt, bar; 5933 5934 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 5935 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 5936 5937 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 5938 5939 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5940 admincnt = sctx->isc_admin_intrcnt; 5941 /* Override by tuneable */ 5942 if (scctx->isc_disable_msix) 5943 goto msi; 5944 5945 /* 5946 * bar == -1 => "trust me I know what I'm doing" 5947 * Some drivers are for hardware that is so shoddily 5948 * documented that no one knows which bars are which 5949 * so the developer has to map all bars. This hack 5950 * allows shoddy garbage to use msix in this framework. 5951 */ 5952 if (bar != -1) { 5953 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5954 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5955 if (ctx->ifc_msix_mem == NULL) { 5956 /* May not be enabled */ 5957 device_printf(dev, "Unable to map MSIX table \n"); 5958 goto msi; 5959 } 5960 } 5961 /* First try MSI/X */ 5962 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5963 device_printf(dev, "System has MSIX disabled \n"); 5964 bus_release_resource(dev, SYS_RES_MEMORY, 5965 bar, ctx->ifc_msix_mem); 5966 ctx->ifc_msix_mem = NULL; 5967 goto msi; 5968 } 5969 #if IFLIB_DEBUG 5970 /* use only 1 qset in debug mode */ 5971 queuemsgs = min(msgs - admincnt, 1); 5972 #else 5973 queuemsgs = msgs - admincnt; 5974 #endif 5975 #ifdef RSS 5976 queues = imin(queuemsgs, rss_getnumbuckets()); 5977 #else 5978 queues = queuemsgs; 5979 #endif 5980 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 5981 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 5982 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 5983 #ifdef RSS 5984 /* If we're doing RSS, clamp at the number of RSS buckets */ 5985 if (queues > rss_getnumbuckets()) 5986 queues = rss_getnumbuckets(); 5987 #endif 5988 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 5989 rx_queues = iflib_num_rx_queues; 5990 else 5991 rx_queues = queues; 5992 5993 if (rx_queues > scctx->isc_nrxqsets) 5994 rx_queues = scctx->isc_nrxqsets; 5995 5996 /* 5997 * We want this to be all logical CPUs by default 5998 */ 5999 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6000 tx_queues = iflib_num_tx_queues; 6001 else 6002 tx_queues = mp_ncpus; 6003 6004 if (tx_queues > scctx->isc_ntxqsets) 6005 tx_queues = scctx->isc_ntxqsets; 6006 6007 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6008 #ifdef INVARIANTS 6009 if (tx_queues != rx_queues) 6010 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6011 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6012 #endif 6013 tx_queues = min(rx_queues, tx_queues); 6014 rx_queues = min(rx_queues, tx_queues); 6015 } 6016 6017 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 6018 6019 vectors = rx_queues + admincnt; 6020 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6021 device_printf(dev, 6022 "Using MSIX interrupts with %d vectors\n", vectors); 6023 scctx->isc_vectors = vectors; 6024 scctx->isc_nrxqsets = rx_queues; 6025 scctx->isc_ntxqsets = tx_queues; 6026 scctx->isc_intr = IFLIB_INTR_MSIX; 6027 6028 return (vectors); 6029 } else { 6030 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 6031 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6032 ctx->ifc_msix_mem); 6033 ctx->ifc_msix_mem = NULL; 6034 } 6035 msi: 6036 vectors = pci_msi_count(dev); 6037 scctx->isc_nrxqsets = 1; 6038 scctx->isc_ntxqsets = 1; 6039 scctx->isc_vectors = vectors; 6040 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6041 device_printf(dev,"Using an MSI interrupt\n"); 6042 scctx->isc_intr = IFLIB_INTR_MSI; 6043 } else { 6044 scctx->isc_vectors = 1; 6045 device_printf(dev,"Using a Legacy interrupt\n"); 6046 scctx->isc_intr = IFLIB_INTR_LEGACY; 6047 } 6048 6049 return (vectors); 6050 } 6051 6052 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6053 6054 static int 6055 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6056 { 6057 int rc; 6058 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6059 struct sbuf *sb; 6060 const char *ring_state = "UNKNOWN"; 6061 6062 /* XXX needed ? */ 6063 rc = sysctl_wire_old_buffer(req, 0); 6064 MPASS(rc == 0); 6065 if (rc != 0) 6066 return (rc); 6067 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6068 MPASS(sb != NULL); 6069 if (sb == NULL) 6070 return (ENOMEM); 6071 if (state[3] <= 3) 6072 ring_state = ring_states[state[3]]; 6073 6074 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6075 state[0], state[1], state[2], ring_state); 6076 rc = sbuf_finish(sb); 6077 sbuf_delete(sb); 6078 return(rc); 6079 } 6080 6081 enum iflib_ndesc_handler { 6082 IFLIB_NTXD_HANDLER, 6083 IFLIB_NRXD_HANDLER, 6084 }; 6085 6086 static int 6087 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6088 { 6089 if_ctx_t ctx = (void *)arg1; 6090 enum iflib_ndesc_handler type = arg2; 6091 char buf[256] = {0}; 6092 qidx_t *ndesc; 6093 char *p, *next; 6094 int nqs, rc, i; 6095 6096 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 6097 6098 nqs = 8; 6099 switch(type) { 6100 case IFLIB_NTXD_HANDLER: 6101 ndesc = ctx->ifc_sysctl_ntxds; 6102 if (ctx->ifc_sctx) 6103 nqs = ctx->ifc_sctx->isc_ntxqs; 6104 break; 6105 case IFLIB_NRXD_HANDLER: 6106 ndesc = ctx->ifc_sysctl_nrxds; 6107 if (ctx->ifc_sctx) 6108 nqs = ctx->ifc_sctx->isc_nrxqs; 6109 break; 6110 default: 6111 panic("unhandled type"); 6112 } 6113 if (nqs == 0) 6114 nqs = 8; 6115 6116 for (i=0; i<8; i++) { 6117 if (i >= nqs) 6118 break; 6119 if (i) 6120 strcat(buf, ","); 6121 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6122 } 6123 6124 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6125 if (rc || req->newptr == NULL) 6126 return rc; 6127 6128 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6129 i++, p = strsep(&next, " ,")) { 6130 ndesc[i] = strtoul(p, NULL, 10); 6131 } 6132 6133 return(rc); 6134 } 6135 6136 #define NAME_BUFLEN 32 6137 static void 6138 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6139 { 6140 device_t dev = iflib_get_dev(ctx); 6141 struct sysctl_oid_list *child, *oid_list; 6142 struct sysctl_ctx_list *ctx_list; 6143 struct sysctl_oid *node; 6144 6145 ctx_list = device_get_sysctl_ctx(dev); 6146 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6147 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6148 CTLFLAG_RD, NULL, "IFLIB fields"); 6149 oid_list = SYSCTL_CHILDREN(node); 6150 6151 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6152 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 6153 "driver version"); 6154 6155 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6156 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6157 "# of txqs to use, 0 => use default #"); 6158 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6159 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6160 "# of rxqs to use, 0 => use default #"); 6161 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6162 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6163 "permit #txq != #rxq"); 6164 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6165 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6166 "disable MSIX (default 0)"); 6167 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6168 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6169 "set the rx budget"); 6170 6171 /* XXX change for per-queue sizes */ 6172 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6173 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6174 mp_ndesc_handler, "A", 6175 "list of # of tx descriptors to use, 0 = use default #"); 6176 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6177 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6178 mp_ndesc_handler, "A", 6179 "list of # of rx descriptors to use, 0 = use default #"); 6180 } 6181 6182 static void 6183 iflib_add_device_sysctl_post(if_ctx_t ctx) 6184 { 6185 if_shared_ctx_t sctx = ctx->ifc_sctx; 6186 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6187 device_t dev = iflib_get_dev(ctx); 6188 struct sysctl_oid_list *child; 6189 struct sysctl_ctx_list *ctx_list; 6190 iflib_fl_t fl; 6191 iflib_txq_t txq; 6192 iflib_rxq_t rxq; 6193 int i, j; 6194 char namebuf[NAME_BUFLEN]; 6195 char *qfmt; 6196 struct sysctl_oid *queue_node, *fl_node, *node; 6197 struct sysctl_oid_list *queue_list, *fl_list; 6198 ctx_list = device_get_sysctl_ctx(dev); 6199 6200 node = ctx->ifc_sysctl_node; 6201 child = SYSCTL_CHILDREN(node); 6202 6203 if (scctx->isc_ntxqsets > 100) 6204 qfmt = "txq%03d"; 6205 else if (scctx->isc_ntxqsets > 10) 6206 qfmt = "txq%02d"; 6207 else 6208 qfmt = "txq%d"; 6209 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6210 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6211 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6212 CTLFLAG_RD, NULL, "Queue Name"); 6213 queue_list = SYSCTL_CHILDREN(queue_node); 6214 #if MEMORY_LOGGING 6215 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6216 CTLFLAG_RD, 6217 &txq->ift_dequeued, "total mbufs freed"); 6218 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6219 CTLFLAG_RD, 6220 &txq->ift_enqueued, "total mbufs enqueued"); 6221 #endif 6222 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6223 CTLFLAG_RD, 6224 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6225 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6226 CTLFLAG_RD, 6227 &txq->ift_pullups, "# of times m_pullup was called"); 6228 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6229 CTLFLAG_RD, 6230 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6231 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6232 CTLFLAG_RD, 6233 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6234 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6235 CTLFLAG_RD, 6236 &txq->ift_map_failed, "# of times dma map failed"); 6237 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6238 CTLFLAG_RD, 6239 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6240 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6241 CTLFLAG_RD, 6242 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6243 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6244 CTLFLAG_RD, 6245 &txq->ift_pidx, 1, "Producer Index"); 6246 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6247 CTLFLAG_RD, 6248 &txq->ift_cidx, 1, "Consumer Index"); 6249 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6250 CTLFLAG_RD, 6251 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6252 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6253 CTLFLAG_RD, 6254 &txq->ift_in_use, 1, "descriptors in use"); 6255 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6256 CTLFLAG_RD, 6257 &txq->ift_processed, "descriptors procesed for clean"); 6258 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6259 CTLFLAG_RD, 6260 &txq->ift_cleaned, "total cleaned"); 6261 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6262 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6263 0, mp_ring_state_handler, "A", "soft ring state"); 6264 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6265 CTLFLAG_RD, &txq->ift_br->enqueues, 6266 "# of enqueues to the mp_ring for this queue"); 6267 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6268 CTLFLAG_RD, &txq->ift_br->drops, 6269 "# of drops in the mp_ring for this queue"); 6270 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6271 CTLFLAG_RD, &txq->ift_br->starts, 6272 "# of normal consumer starts in the mp_ring for this queue"); 6273 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6274 CTLFLAG_RD, &txq->ift_br->stalls, 6275 "# of consumer stalls in the mp_ring for this queue"); 6276 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6277 CTLFLAG_RD, &txq->ift_br->restarts, 6278 "# of consumer restarts in the mp_ring for this queue"); 6279 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6280 CTLFLAG_RD, &txq->ift_br->abdications, 6281 "# of consumer abdications in the mp_ring for this queue"); 6282 } 6283 6284 if (scctx->isc_nrxqsets > 100) 6285 qfmt = "rxq%03d"; 6286 else if (scctx->isc_nrxqsets > 10) 6287 qfmt = "rxq%02d"; 6288 else 6289 qfmt = "rxq%d"; 6290 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6291 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6292 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6293 CTLFLAG_RD, NULL, "Queue Name"); 6294 queue_list = SYSCTL_CHILDREN(queue_node); 6295 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6296 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 6297 CTLFLAG_RD, 6298 &rxq->ifr_cq_pidx, 1, "Producer Index"); 6299 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6300 CTLFLAG_RD, 6301 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6302 } 6303 6304 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6305 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6306 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6307 CTLFLAG_RD, NULL, "freelist Name"); 6308 fl_list = SYSCTL_CHILDREN(fl_node); 6309 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6310 CTLFLAG_RD, 6311 &fl->ifl_pidx, 1, "Producer Index"); 6312 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6313 CTLFLAG_RD, 6314 &fl->ifl_cidx, 1, "Consumer Index"); 6315 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6316 CTLFLAG_RD, 6317 &fl->ifl_credits, 1, "credits available"); 6318 #if MEMORY_LOGGING 6319 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6320 CTLFLAG_RD, 6321 &fl->ifl_m_enqueued, "mbufs allocated"); 6322 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6323 CTLFLAG_RD, 6324 &fl->ifl_m_dequeued, "mbufs freed"); 6325 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6326 CTLFLAG_RD, 6327 &fl->ifl_cl_enqueued, "clusters allocated"); 6328 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6329 CTLFLAG_RD, 6330 &fl->ifl_cl_dequeued, "clusters freed"); 6331 #endif 6332 6333 } 6334 } 6335 6336 } 6337 6338 #ifndef __NO_STRICT_ALIGNMENT 6339 static struct mbuf * 6340 iflib_fixup_rx(struct mbuf *m) 6341 { 6342 struct mbuf *n; 6343 6344 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6345 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6346 m->m_data += ETHER_HDR_LEN; 6347 n = m; 6348 } else { 6349 MGETHDR(n, M_NOWAIT, MT_DATA); 6350 if (n == NULL) { 6351 m_freem(m); 6352 return (NULL); 6353 } 6354 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6355 m->m_data += ETHER_HDR_LEN; 6356 m->m_len -= ETHER_HDR_LEN; 6357 n->m_len = ETHER_HDR_LEN; 6358 M_MOVE_PKTHDR(n, m); 6359 n->m_next = m; 6360 } 6361 return (n); 6362 } 6363 #endif 6364 6365 #ifdef NETDUMP 6366 static void 6367 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 6368 { 6369 if_ctx_t ctx; 6370 6371 ctx = if_getsoftc(ifp); 6372 CTX_LOCK(ctx); 6373 *nrxr = NRXQSETS(ctx); 6374 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6375 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6376 CTX_UNLOCK(ctx); 6377 } 6378 6379 static void 6380 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event) 6381 { 6382 if_ctx_t ctx; 6383 if_softc_ctx_t scctx; 6384 iflib_fl_t fl; 6385 iflib_rxq_t rxq; 6386 int i, j; 6387 6388 ctx = if_getsoftc(ifp); 6389 scctx = &ctx->ifc_softc_ctx; 6390 6391 switch (event) { 6392 case NETDUMP_START: 6393 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6394 rxq = &ctx->ifc_rxqs[i]; 6395 for (j = 0; j < rxq->ifr_nfl; j++) { 6396 fl = rxq->ifr_fl; 6397 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6398 } 6399 } 6400 iflib_no_tx_batch = 1; 6401 break; 6402 default: 6403 break; 6404 } 6405 } 6406 6407 static int 6408 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m) 6409 { 6410 if_ctx_t ctx; 6411 iflib_txq_t txq; 6412 int error; 6413 6414 ctx = if_getsoftc(ifp); 6415 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6416 IFF_DRV_RUNNING) 6417 return (EBUSY); 6418 6419 txq = &ctx->ifc_txqs[0]; 6420 error = iflib_encap(txq, &m); 6421 if (error == 0) 6422 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6423 return (error); 6424 } 6425 6426 static int 6427 iflib_netdump_poll(struct ifnet *ifp, int count) 6428 { 6429 if_ctx_t ctx; 6430 if_softc_ctx_t scctx; 6431 iflib_txq_t txq; 6432 int i; 6433 6434 ctx = if_getsoftc(ifp); 6435 scctx = &ctx->ifc_softc_ctx; 6436 6437 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6438 IFF_DRV_RUNNING) 6439 return (EBUSY); 6440 6441 txq = &ctx->ifc_txqs[0]; 6442 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6443 6444 for (i = 0; i < scctx->isc_nrxqsets; i++) 6445 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6446 return (0); 6447 } 6448 #endif /* NETDUMP */ 6449