1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_private.h> 58 #include <net/if_types.h> 59 #include <net/if_media.h> 60 #include <net/bpf.h> 61 #include <net/ethernet.h> 62 #include <net/mp_ring.h> 63 #include <net/debugnet.h> 64 #include <net/pfil.h> 65 #include <net/vnet.h> 66 67 #include <netinet/in.h> 68 #include <netinet/in_pcb.h> 69 #include <netinet/tcp_lro.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/if_ether.h> 72 #include <netinet/ip.h> 73 #include <netinet/ip6.h> 74 #include <netinet/tcp.h> 75 #include <netinet/ip_var.h> 76 #include <netinet6/ip6_var.h> 77 78 #include <machine/bus.h> 79 #include <machine/in_cksum.h> 80 81 #include <vm/vm.h> 82 #include <vm/pmap.h> 83 84 #include <dev/led/led.h> 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pci_private.h> 88 89 #include <net/iflib.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 /* 120 * File organization: 121 * - private structures 122 * - iflib private utility functions 123 * - ifnet functions 124 * - vlan registry and other exported functions 125 * - iflib public core functions 126 * 127 * 128 */ 129 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 130 131 #define IFLIB_RXEOF_MORE (1U << 0) 132 #define IFLIB_RXEOF_EMPTY (2U << 0) 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 static void iflib_tqg_detach(if_ctx_t ctx); 146 147 typedef struct iflib_filter_info { 148 driver_filter_t *ifi_filter; 149 void *ifi_filter_arg; 150 struct grouptask *ifi_task; 151 void *ifi_ctx; 152 } *iflib_filter_info_t; 153 154 struct iflib_ctx { 155 KOBJ_FIELDS; 156 /* 157 * Pointer to hardware driver's softc 158 */ 159 void *ifc_softc; 160 device_t ifc_dev; 161 if_t ifc_ifp; 162 163 cpuset_t ifc_cpus; 164 if_shared_ctx_t ifc_sctx; 165 struct if_softc_ctx ifc_softc_ctx; 166 167 struct sx ifc_ctx_sx; 168 struct mtx ifc_state_mtx; 169 170 iflib_txq_t ifc_txqs; 171 iflib_rxq_t ifc_rxqs; 172 uint32_t ifc_if_flags; 173 uint32_t ifc_flags; 174 uint32_t ifc_max_fl_buf_size; 175 uint32_t ifc_rx_mbuf_sz; 176 177 int ifc_link_state; 178 int ifc_watchdog_events; 179 struct cdev *ifc_led_dev; 180 struct resource *ifc_msix_mem; 181 182 struct if_irq ifc_legacy_irq; 183 struct grouptask ifc_admin_task; 184 struct grouptask ifc_vflr_task; 185 struct iflib_filter_info ifc_filter_info; 186 struct ifmedia ifc_media; 187 struct ifmedia *ifc_mediap; 188 189 struct sysctl_oid *ifc_sysctl_node; 190 uint16_t ifc_sysctl_ntxqs; 191 uint16_t ifc_sysctl_nrxqs; 192 uint16_t ifc_sysctl_qs_eq_override; 193 uint16_t ifc_sysctl_rx_budget; 194 uint16_t ifc_sysctl_tx_abdicate; 195 uint16_t ifc_sysctl_core_offset; 196 #define CORE_OFFSET_UNSPECIFIED 0xffff 197 uint8_t ifc_sysctl_separate_txrx; 198 uint8_t ifc_sysctl_use_logical_cores; 199 bool ifc_cpus_are_physical_cores; 200 201 qidx_t ifc_sysctl_ntxds[8]; 202 qidx_t ifc_sysctl_nrxds[8]; 203 struct if_txrx ifc_txrx; 204 #define isc_txd_encap ifc_txrx.ift_txd_encap 205 #define isc_txd_flush ifc_txrx.ift_txd_flush 206 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 207 #define isc_rxd_available ifc_txrx.ift_rxd_available 208 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 209 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 210 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 211 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 212 #define isc_txq_select ifc_txrx.ift_txq_select 213 #define isc_txq_select_v2 ifc_txrx.ift_txq_select_v2 214 215 eventhandler_tag ifc_vlan_attach_event; 216 eventhandler_tag ifc_vlan_detach_event; 217 struct ether_addr ifc_mac; 218 }; 219 220 void * 221 iflib_get_softc(if_ctx_t ctx) 222 { 223 224 return (ctx->ifc_softc); 225 } 226 227 device_t 228 iflib_get_dev(if_ctx_t ctx) 229 { 230 231 return (ctx->ifc_dev); 232 } 233 234 if_t 235 iflib_get_ifp(if_ctx_t ctx) 236 { 237 238 return (ctx->ifc_ifp); 239 } 240 241 struct ifmedia * 242 iflib_get_media(if_ctx_t ctx) 243 { 244 245 return (ctx->ifc_mediap); 246 } 247 248 void 249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 250 { 251 252 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 253 } 254 255 if_softc_ctx_t 256 iflib_get_softc_ctx(if_ctx_t ctx) 257 { 258 259 return (&ctx->ifc_softc_ctx); 260 } 261 262 if_shared_ctx_t 263 iflib_get_sctx(if_ctx_t ctx) 264 { 265 266 return (ctx->ifc_sctx); 267 } 268 269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 272 273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 275 276 typedef struct iflib_sw_rx_desc_array { 277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 278 struct mbuf **ifsd_m; /* pkthdr mbufs */ 279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 281 } iflib_rxsd_array_t; 282 283 typedef struct iflib_sw_tx_desc_array { 284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 286 struct mbuf **ifsd_m; /* pkthdr mbufs */ 287 } if_txsd_vec_t; 288 289 /* magic number that should be high enough for any hardware */ 290 #define IFLIB_MAX_TX_SEGS 128 291 #define IFLIB_RX_COPY_THRESH 128 292 #define IFLIB_MAX_RX_REFRESH 32 293 /* The minimum descriptors per second before we start coalescing */ 294 #define IFLIB_MIN_DESC_SEC 16384 295 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 296 #define IFLIB_QUEUE_IDLE 0 297 #define IFLIB_QUEUE_HUNG 1 298 #define IFLIB_QUEUE_WORKING 2 299 /* maximum number of txqs that can share an rx interrupt */ 300 #define IFLIB_MAX_TX_SHARED_INTR 4 301 302 /* this should really scale with ring size - this is a fairly arbitrary value */ 303 #define TX_BATCH_SIZE 32 304 305 #define IFLIB_RESTART_BUDGET 8 306 307 #define IFC_LEGACY 0x001 308 #define IFC_QFLUSH 0x002 309 #define IFC_MULTISEG 0x004 310 #define IFC_SPARE1 0x008 311 #define IFC_SC_ALLOCATED 0x010 312 #define IFC_INIT_DONE 0x020 313 #define IFC_PREFETCH 0x040 314 #define IFC_DO_RESET 0x080 315 #define IFC_DO_WATCHDOG 0x100 316 #define IFC_SPARE0 0x200 317 #define IFC_SPARE2 0x400 318 #define IFC_IN_DETACH 0x800 319 320 #define IFC_NETMAP_TX_IRQ 0x80000000 321 322 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 323 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 324 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 325 326 struct iflib_txq { 327 qidx_t ift_in_use; 328 qidx_t ift_cidx; 329 qidx_t ift_cidx_processed; 330 qidx_t ift_pidx; 331 uint8_t ift_gen; 332 uint8_t ift_br_offset; 333 uint16_t ift_npending; 334 uint16_t ift_db_pending; 335 uint16_t ift_rs_pending; 336 /* implicit pad */ 337 uint8_t ift_txd_size[8]; 338 uint64_t ift_processed; 339 uint64_t ift_cleaned; 340 uint64_t ift_cleaned_prev; 341 #if MEMORY_LOGGING 342 uint64_t ift_enqueued; 343 uint64_t ift_dequeued; 344 #endif 345 uint64_t ift_no_tx_dma_setup; 346 uint64_t ift_no_desc_avail; 347 uint64_t ift_mbuf_defrag_failed; 348 uint64_t ift_mbuf_defrag; 349 uint64_t ift_map_failed; 350 uint64_t ift_txd_encap_efbig; 351 uint64_t ift_pullups; 352 uint64_t ift_last_timer_tick; 353 354 struct mtx ift_mtx; 355 struct mtx ift_db_mtx; 356 357 /* constant values */ 358 if_ctx_t ift_ctx; 359 struct ifmp_ring *ift_br; 360 struct grouptask ift_task; 361 qidx_t ift_size; 362 uint16_t ift_id; 363 struct callout ift_timer; 364 #ifdef DEV_NETMAP 365 struct callout ift_netmap_timer; 366 #endif /* DEV_NETMAP */ 367 368 if_txsd_vec_t ift_sds; 369 uint8_t ift_qstatus; 370 uint8_t ift_closed; 371 uint8_t ift_update_freq; 372 struct iflib_filter_info ift_filter_info; 373 bus_dma_tag_t ift_buf_tag; 374 bus_dma_tag_t ift_tso_buf_tag; 375 iflib_dma_info_t ift_ifdi; 376 #define MTX_NAME_LEN 32 377 char ift_mtx_name[MTX_NAME_LEN]; 378 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 379 #ifdef IFLIB_DIAGNOSTICS 380 uint64_t ift_cpu_exec_count[256]; 381 #endif 382 } __aligned(CACHE_LINE_SIZE); 383 384 struct iflib_fl { 385 qidx_t ifl_cidx; 386 qidx_t ifl_pidx; 387 qidx_t ifl_credits; 388 uint8_t ifl_gen; 389 uint8_t ifl_rxd_size; 390 #if MEMORY_LOGGING 391 uint64_t ifl_m_enqueued; 392 uint64_t ifl_m_dequeued; 393 uint64_t ifl_cl_enqueued; 394 uint64_t ifl_cl_dequeued; 395 #endif 396 /* implicit pad */ 397 bitstr_t *ifl_rx_bitmap; 398 qidx_t ifl_fragidx; 399 /* constant */ 400 qidx_t ifl_size; 401 uint16_t ifl_buf_size; 402 uint16_t ifl_cltype; 403 uma_zone_t ifl_zone; 404 iflib_rxsd_array_t ifl_sds; 405 iflib_rxq_t ifl_rxq; 406 uint8_t ifl_id; 407 bus_dma_tag_t ifl_buf_tag; 408 iflib_dma_info_t ifl_ifdi; 409 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 410 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 411 } __aligned(CACHE_LINE_SIZE); 412 413 static inline qidx_t 414 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 415 { 416 qidx_t used; 417 418 if (pidx > cidx) 419 used = pidx - cidx; 420 else if (pidx < cidx) 421 used = size - cidx + pidx; 422 else if (gen == 0 && pidx == cidx) 423 used = 0; 424 else if (gen == 1 && pidx == cidx) 425 used = size; 426 else 427 panic("bad state"); 428 429 return (used); 430 } 431 432 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 433 434 #define IDXDIFF(head, tail, wrap) \ 435 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 436 437 struct iflib_rxq { 438 if_ctx_t ifr_ctx; 439 iflib_fl_t ifr_fl; 440 uint64_t ifr_rx_irq; 441 struct pfil_head *pfil; 442 /* 443 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 444 * the completion queue consumer index. Otherwise it's unused. 445 */ 446 qidx_t ifr_cq_cidx; 447 uint16_t ifr_id; 448 uint8_t ifr_nfl; 449 uint8_t ifr_ntxqirq; 450 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 451 uint8_t ifr_fl_offset; 452 struct lro_ctrl ifr_lc; 453 struct grouptask ifr_task; 454 struct callout ifr_watchdog; 455 struct iflib_filter_info ifr_filter_info; 456 iflib_dma_info_t ifr_ifdi; 457 458 /* dynamically allocate if any drivers need a value substantially larger than this */ 459 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 460 #ifdef IFLIB_DIAGNOSTICS 461 uint64_t ifr_cpu_exec_count[256]; 462 #endif 463 } __aligned(CACHE_LINE_SIZE); 464 465 typedef struct if_rxsd { 466 caddr_t *ifsd_cl; 467 iflib_fl_t ifsd_fl; 468 } *if_rxsd_t; 469 470 /* multiple of word size */ 471 #ifdef __LP64__ 472 #define PKT_INFO_SIZE 6 473 #define RXD_INFO_SIZE 5 474 #define PKT_TYPE uint64_t 475 #else 476 #define PKT_INFO_SIZE 11 477 #define RXD_INFO_SIZE 8 478 #define PKT_TYPE uint32_t 479 #endif 480 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 481 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 482 483 typedef struct if_pkt_info_pad { 484 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 485 } *if_pkt_info_pad_t; 486 typedef struct if_rxd_info_pad { 487 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 488 } *if_rxd_info_pad_t; 489 490 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 491 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 492 493 static inline void 494 pkt_info_zero(if_pkt_info_t pi) 495 { 496 if_pkt_info_pad_t pi_pad; 497 498 pi_pad = (if_pkt_info_pad_t)pi; 499 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 500 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 501 #ifndef __LP64__ 502 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 503 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 504 #endif 505 } 506 507 static inline void 508 rxd_info_zero(if_rxd_info_t ri) 509 { 510 if_rxd_info_pad_t ri_pad; 511 int i; 512 513 ri_pad = (if_rxd_info_pad_t)ri; 514 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 515 ri_pad->rxd_val[i] = 0; 516 ri_pad->rxd_val[i+1] = 0; 517 ri_pad->rxd_val[i+2] = 0; 518 ri_pad->rxd_val[i+3] = 0; 519 } 520 #ifdef __LP64__ 521 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 522 #endif 523 } 524 525 /* 526 * Only allow a single packet to take up most 1/nth of the tx ring 527 */ 528 #define MAX_SINGLE_PACKET_FRACTION 12 529 #define IF_BAD_DMA (bus_addr_t)-1 530 531 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 532 533 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 534 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 535 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 536 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 537 538 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 539 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 540 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 541 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 542 543 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 544 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 545 546 /* Our boot-time initialization hook */ 547 static int iflib_module_event_handler(module_t, int, void *); 548 549 static moduledata_t iflib_moduledata = { 550 "iflib", 551 iflib_module_event_handler, 552 NULL 553 }; 554 555 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 556 MODULE_VERSION(iflib, 1); 557 558 MODULE_DEPEND(iflib, pci, 1, 1, 1); 559 MODULE_DEPEND(iflib, ether, 1, 1, 1); 560 561 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 562 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 563 564 #ifndef IFLIB_DEBUG_COUNTERS 565 #ifdef INVARIANTS 566 #define IFLIB_DEBUG_COUNTERS 1 567 #else 568 #define IFLIB_DEBUG_COUNTERS 0 569 #endif /* !INVARIANTS */ 570 #endif 571 572 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 573 "iflib driver parameters"); 574 575 /* 576 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 577 */ 578 static int iflib_min_tx_latency = 0; 579 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 580 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 581 static int iflib_no_tx_batch = 0; 582 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 583 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 584 static int iflib_timer_default = 1000; 585 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW, 586 &iflib_timer_default, 0, "number of ticks between iflib_timer calls"); 587 588 589 #if IFLIB_DEBUG_COUNTERS 590 591 static int iflib_tx_seen; 592 static int iflib_tx_sent; 593 static int iflib_tx_encap; 594 static int iflib_rx_allocs; 595 static int iflib_fl_refills; 596 static int iflib_fl_refills_large; 597 static int iflib_tx_frees; 598 599 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 600 &iflib_tx_seen, 0, "# TX mbufs seen"); 601 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 602 &iflib_tx_sent, 0, "# TX mbufs sent"); 603 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 604 &iflib_tx_encap, 0, "# TX mbufs encapped"); 605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 606 &iflib_tx_frees, 0, "# TX frees"); 607 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 608 &iflib_rx_allocs, 0, "# RX allocations"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 610 &iflib_fl_refills, 0, "# refills"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 612 &iflib_fl_refills_large, 0, "# large refills"); 613 614 static int iflib_txq_drain_flushing; 615 static int iflib_txq_drain_oactive; 616 static int iflib_txq_drain_notready; 617 618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 619 &iflib_txq_drain_flushing, 0, "# drain flushes"); 620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 621 &iflib_txq_drain_oactive, 0, "# drain oactives"); 622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 623 &iflib_txq_drain_notready, 0, "# drain notready"); 624 625 static int iflib_encap_load_mbuf_fail; 626 static int iflib_encap_pad_mbuf_fail; 627 static int iflib_encap_txq_avail_fail; 628 static int iflib_encap_txd_encap_fail; 629 630 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 631 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 632 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 633 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 634 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 635 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 637 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 638 639 static int iflib_task_fn_rxs; 640 static int iflib_rx_intr_enables; 641 static int iflib_fast_intrs; 642 static int iflib_rx_unavail; 643 static int iflib_rx_ctx_inactive; 644 static int iflib_rx_if_input; 645 static int iflib_rxd_flush; 646 647 static int iflib_verbose_debug; 648 649 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 650 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 651 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 652 &iflib_rx_intr_enables, 0, "# RX intr enables"); 653 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 654 &iflib_fast_intrs, 0, "# fast_intr calls"); 655 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 656 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 657 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 658 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 660 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 662 &iflib_rxd_flush, 0, "# times rxd_flush called"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 664 &iflib_verbose_debug, 0, "enable verbose debugging"); 665 666 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 667 static void 668 iflib_debug_reset(void) 669 { 670 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 671 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 672 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 673 iflib_txq_drain_notready = 674 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 675 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 676 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 677 iflib_rx_unavail = 678 iflib_rx_ctx_inactive = iflib_rx_if_input = 679 iflib_rxd_flush = 0; 680 } 681 682 #else 683 #define DBG_COUNTER_INC(name) 684 static void iflib_debug_reset(void) {} 685 #endif 686 687 #define IFLIB_DEBUG 0 688 689 static void iflib_tx_structures_free(if_ctx_t ctx); 690 static void iflib_rx_structures_free(if_ctx_t ctx); 691 static int iflib_queues_alloc(if_ctx_t ctx); 692 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 693 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 694 static int iflib_qset_structures_setup(if_ctx_t ctx); 695 static int iflib_msix_init(if_ctx_t ctx); 696 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 697 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 698 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 699 #ifdef ALTQ 700 static void iflib_altq_if_start(if_t ifp); 701 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 702 #endif 703 static int iflib_register(if_ctx_t); 704 static void iflib_deregister(if_ctx_t); 705 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 706 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 707 static void iflib_init_locked(if_ctx_t ctx); 708 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 709 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 710 static void iflib_ifmp_purge(iflib_txq_t txq); 711 static void _iflib_pre_assert(if_softc_ctx_t scctx); 712 static void iflib_stop(if_ctx_t ctx); 713 static void iflib_if_init_locked(if_ctx_t ctx); 714 static void iflib_free_intr_mem(if_ctx_t ctx); 715 #ifndef __NO_STRICT_ALIGNMENT 716 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 717 #endif 718 719 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 720 SLIST_HEAD_INITIALIZER(cpu_offsets); 721 struct cpu_offset { 722 SLIST_ENTRY(cpu_offset) entries; 723 cpuset_t set; 724 unsigned int refcount; 725 uint16_t next_cpuid; 726 }; 727 static struct mtx cpu_offset_mtx; 728 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 729 MTX_DEF); 730 731 DEBUGNET_DEFINE(iflib); 732 733 static int 734 iflib_num_rx_descs(if_ctx_t ctx) 735 { 736 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 737 if_shared_ctx_t sctx = ctx->ifc_sctx; 738 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 739 740 return scctx->isc_nrxd[first_rxq]; 741 } 742 743 static int 744 iflib_num_tx_descs(if_ctx_t ctx) 745 { 746 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 747 if_shared_ctx_t sctx = ctx->ifc_sctx; 748 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 749 750 return scctx->isc_ntxd[first_txq]; 751 } 752 753 #ifdef DEV_NETMAP 754 #include <sys/selinfo.h> 755 #include <net/netmap.h> 756 #include <dev/netmap/netmap_kern.h> 757 758 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 759 760 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 761 static void iflib_netmap_timer(void *arg); 762 763 /* 764 * device-specific sysctl variables: 765 * 766 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 767 * During regular operations the CRC is stripped, but on some 768 * hardware reception of frames not multiple of 64 is slower, 769 * so using crcstrip=0 helps in benchmarks. 770 * 771 * iflib_rx_miss, iflib_rx_miss_bufs: 772 * count packets that might be missed due to lost interrupts. 773 */ 774 SYSCTL_DECL(_dev_netmap); 775 /* 776 * The xl driver by default strips CRCs and we do not override it. 777 */ 778 779 int iflib_crcstrip = 1; 780 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 781 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 782 783 int iflib_rx_miss, iflib_rx_miss_bufs; 784 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 785 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 786 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 787 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 788 789 /* 790 * Register/unregister. We are already under netmap lock. 791 * Only called on the first register or the last unregister. 792 */ 793 static int 794 iflib_netmap_register(struct netmap_adapter *na, int onoff) 795 { 796 if_t ifp = na->ifp; 797 if_ctx_t ctx = if_getsoftc(ifp); 798 int status; 799 800 CTX_LOCK(ctx); 801 if (!CTX_IS_VF(ctx)) 802 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 803 804 iflib_stop(ctx); 805 806 /* 807 * Enable (or disable) netmap flags, and intercept (or restore) 808 * ifp->if_transmit. This is done once the device has been stopped 809 * to prevent race conditions. Also, this must be done after 810 * calling netmap_disable_all_rings() and before calling 811 * netmap_enable_all_rings(), so that these two functions see the 812 * updated state of the NAF_NETMAP_ON bit. 813 */ 814 if (onoff) { 815 nm_set_native_flags(na); 816 } else { 817 nm_clear_native_flags(na); 818 } 819 820 iflib_init_locked(ctx); 821 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 822 status = if_getdrvflags(ifp) & IFF_DRV_RUNNING ? 0 : 1; 823 if (status) 824 nm_clear_native_flags(na); 825 CTX_UNLOCK(ctx); 826 return (status); 827 } 828 829 static int 830 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info) 831 { 832 if_t ifp = na->ifp; 833 if_ctx_t ctx = if_getsoftc(ifp); 834 iflib_rxq_t rxq = &ctx->ifc_rxqs[0]; 835 iflib_fl_t fl = &rxq->ifr_fl[0]; 836 837 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 838 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 839 info->num_tx_descs = iflib_num_tx_descs(ctx); 840 info->num_rx_descs = iflib_num_rx_descs(ctx); 841 info->rx_buf_maxsize = fl->ifl_buf_size; 842 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u", 843 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs, 844 info->num_rx_descs, info->rx_buf_maxsize); 845 846 return 0; 847 } 848 849 static int 850 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 851 { 852 struct netmap_adapter *na = kring->na; 853 u_int const lim = kring->nkr_num_slots - 1; 854 struct netmap_ring *ring = kring->ring; 855 bus_dmamap_t *map; 856 struct if_rxd_update iru; 857 if_ctx_t ctx = rxq->ifr_ctx; 858 iflib_fl_t fl = &rxq->ifr_fl[0]; 859 u_int nic_i_first, nic_i; 860 u_int nm_i; 861 int i, n; 862 #if IFLIB_DEBUG_COUNTERS 863 int rf_count = 0; 864 #endif 865 866 /* 867 * This function is used both at initialization and in rxsync. 868 * At initialization we need to prepare (with isc_rxd_refill()) 869 * all the netmap buffers currently owned by the kernel, in 870 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync 871 * (except for kring->nkr_hwofs). These may be less than 872 * kring->nkr_num_slots if netmap_reset() was called while 873 * an application using the kring that still owned some 874 * buffers. 875 * At rxsync time, both indexes point to the next buffer to be 876 * refilled. 877 * In any case we publish (with isc_rxd_flush()) up to 878 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 879 * pointer to overrun the head/cons pointer, although this is 880 * not necessary for some NICs (e.g. vmx). 881 */ 882 if (__predict_false(init)) { 883 n = kring->nkr_num_slots - nm_kr_rxspace(kring); 884 } else { 885 n = kring->rhead - kring->nr_hwcur; 886 if (n == 0) 887 return (0); /* Nothing to do. */ 888 if (n < 0) 889 n += kring->nkr_num_slots; 890 } 891 892 iru_init(&iru, rxq, 0 /* flid */); 893 map = fl->ifl_sds.ifsd_map; 894 nic_i = fl->ifl_pidx; 895 nm_i = netmap_idx_n2k(kring, nic_i); 896 if (__predict_false(init)) { 897 /* 898 * On init/reset, nic_i must be 0, and we must 899 * start to refill from hwtail (see netmap_reset()). 900 */ 901 MPASS(nic_i == 0); 902 MPASS(nm_i == kring->nr_hwtail); 903 } else 904 MPASS(nm_i == kring->nr_hwcur); 905 DBG_COUNTER_INC(fl_refills); 906 while (n > 0) { 907 #if IFLIB_DEBUG_COUNTERS 908 if (++rf_count == 9) 909 DBG_COUNTER_INC(fl_refills_large); 910 #endif 911 nic_i_first = nic_i; 912 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 913 struct netmap_slot *slot = &ring->slot[nm_i]; 914 uint64_t paddr; 915 void *addr = PNMB(na, slot, &paddr); 916 917 MPASS(i < IFLIB_MAX_RX_REFRESH); 918 919 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 920 return netmap_ring_reinit(kring); 921 922 fl->ifl_bus_addrs[i] = paddr + 923 nm_get_offset(kring, slot); 924 fl->ifl_rxd_idxs[i] = nic_i; 925 926 if (__predict_false(init)) { 927 netmap_load_map(na, fl->ifl_buf_tag, 928 map[nic_i], addr); 929 } else if (slot->flags & NS_BUF_CHANGED) { 930 /* buffer has changed, reload map */ 931 netmap_reload_map(na, fl->ifl_buf_tag, 932 map[nic_i], addr); 933 } 934 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 935 BUS_DMASYNC_PREREAD); 936 slot->flags &= ~NS_BUF_CHANGED; 937 938 nm_i = nm_next(nm_i, lim); 939 nic_i = nm_next(nic_i, lim); 940 } 941 942 iru.iru_pidx = nic_i_first; 943 iru.iru_count = i; 944 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 945 } 946 fl->ifl_pidx = nic_i; 947 /* 948 * At the end of the loop we must have refilled everything 949 * we could possibly refill. 950 */ 951 MPASS(nm_i == kring->rhead); 952 kring->nr_hwcur = nm_i; 953 954 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 955 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 956 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 957 nm_prev(nic_i, lim)); 958 DBG_COUNTER_INC(rxd_flush); 959 960 return (0); 961 } 962 963 #define NETMAP_TX_TIMER_US 90 964 965 /* 966 * Reconcile kernel and user view of the transmit ring. 967 * 968 * All information is in the kring. 969 * Userspace wants to send packets up to the one before kring->rhead, 970 * kernel knows kring->nr_hwcur is the first unsent packet. 971 * 972 * Here we push packets out (as many as possible), and possibly 973 * reclaim buffers from previously completed transmission. 974 * 975 * The caller (netmap) guarantees that there is only one instance 976 * running at any time. Any interference with other driver 977 * methods should be handled by the individual drivers. 978 */ 979 static int 980 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 981 { 982 struct netmap_adapter *na = kring->na; 983 if_t ifp = na->ifp; 984 struct netmap_ring *ring = kring->ring; 985 u_int nm_i; /* index into the netmap kring */ 986 u_int nic_i; /* index into the NIC ring */ 987 u_int const lim = kring->nkr_num_slots - 1; 988 u_int const head = kring->rhead; 989 struct if_pkt_info pi; 990 int tx_pkts = 0, tx_bytes = 0; 991 992 /* 993 * interrupts on every tx packet are expensive so request 994 * them every half ring, or where NS_REPORT is set 995 */ 996 u_int report_frequency = kring->nkr_num_slots >> 1; 997 /* device-specific */ 998 if_ctx_t ctx = if_getsoftc(ifp); 999 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 1000 1001 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1002 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1003 1004 /* 1005 * First part: process new packets to send. 1006 * nm_i is the current index in the netmap kring, 1007 * nic_i is the corresponding index in the NIC ring. 1008 * 1009 * If we have packets to send (nm_i != head) 1010 * iterate over the netmap ring, fetch length and update 1011 * the corresponding slot in the NIC ring. Some drivers also 1012 * need to update the buffer's physical address in the NIC slot 1013 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 1014 * 1015 * The netmap_reload_map() calls is especially expensive, 1016 * even when (as in this case) the tag is 0, so do only 1017 * when the buffer has actually changed. 1018 * 1019 * If possible do not set the report/intr bit on all slots, 1020 * but only a few times per ring or when NS_REPORT is set. 1021 * 1022 * Finally, on 10G and faster drivers, it might be useful 1023 * to prefetch the next slot and txr entry. 1024 */ 1025 1026 nm_i = kring->nr_hwcur; 1027 if (nm_i != head) { /* we have new packets to send */ 1028 uint32_t pkt_len = 0, seg_idx = 0; 1029 int nic_i_start = -1, flags = 0; 1030 pkt_info_zero(&pi); 1031 pi.ipi_segs = txq->ift_segs; 1032 pi.ipi_qsidx = kring->ring_id; 1033 nic_i = netmap_idx_k2n(kring, nm_i); 1034 1035 __builtin_prefetch(&ring->slot[nm_i]); 1036 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 1037 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 1038 1039 while (nm_i != head) { 1040 struct netmap_slot *slot = &ring->slot[nm_i]; 1041 uint64_t offset = nm_get_offset(kring, slot); 1042 u_int len = slot->len; 1043 uint64_t paddr; 1044 void *addr = PNMB(na, slot, &paddr); 1045 1046 flags |= (slot->flags & NS_REPORT || 1047 nic_i == 0 || nic_i == report_frequency) ? 1048 IPI_TX_INTR : 0; 1049 1050 /* 1051 * If this is the first packet fragment, save the 1052 * index of the first NIC slot for later. 1053 */ 1054 if (nic_i_start < 0) 1055 nic_i_start = nic_i; 1056 1057 pi.ipi_segs[seg_idx].ds_addr = paddr + offset; 1058 pi.ipi_segs[seg_idx].ds_len = len; 1059 if (len) { 1060 pkt_len += len; 1061 seg_idx++; 1062 } 1063 1064 if (!(slot->flags & NS_MOREFRAG)) { 1065 pi.ipi_len = pkt_len; 1066 pi.ipi_nsegs = seg_idx; 1067 pi.ipi_pidx = nic_i_start; 1068 pi.ipi_ndescs = 0; 1069 pi.ipi_flags = flags; 1070 1071 /* Prepare the NIC TX ring. */ 1072 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1073 DBG_COUNTER_INC(tx_encap); 1074 1075 /* Update transmit counters */ 1076 tx_bytes += pi.ipi_len; 1077 tx_pkts++; 1078 1079 /* Reinit per-packet info for the next one. */ 1080 flags = seg_idx = pkt_len = 0; 1081 nic_i_start = -1; 1082 } 1083 1084 /* prefetch for next round */ 1085 __builtin_prefetch(&ring->slot[nm_i + 1]); 1086 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1087 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1088 1089 NM_CHECK_ADDR_LEN_OFF(na, len, offset); 1090 1091 if (slot->flags & NS_BUF_CHANGED) { 1092 /* buffer has changed, reload map */ 1093 netmap_reload_map(na, txq->ift_buf_tag, 1094 txq->ift_sds.ifsd_map[nic_i], addr); 1095 } 1096 /* make sure changes to the buffer are synced */ 1097 bus_dmamap_sync(txq->ift_buf_tag, 1098 txq->ift_sds.ifsd_map[nic_i], 1099 BUS_DMASYNC_PREWRITE); 1100 1101 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG); 1102 nm_i = nm_next(nm_i, lim); 1103 nic_i = nm_next(nic_i, lim); 1104 } 1105 kring->nr_hwcur = nm_i; 1106 1107 /* synchronize the NIC ring */ 1108 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1109 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1110 1111 /* (re)start the tx unit up to slot nic_i (excluded) */ 1112 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1113 } 1114 1115 /* 1116 * Second part: reclaim buffers for completed transmissions. 1117 * 1118 * If there are unclaimed buffers, attempt to reclaim them. 1119 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1120 * trigger a per-tx-queue timer to try again later. 1121 */ 1122 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1123 if (iflib_tx_credits_update(ctx, txq)) { 1124 /* some tx completed, increment avail */ 1125 nic_i = txq->ift_cidx_processed; 1126 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1127 } 1128 } 1129 1130 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1131 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1132 callout_reset_sbt_on(&txq->ift_netmap_timer, 1133 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1134 iflib_netmap_timer, txq, 1135 txq->ift_netmap_timer.c_cpu, 0); 1136 } 1137 1138 if_inc_counter(ifp, IFCOUNTER_OBYTES, tx_bytes); 1139 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tx_pkts); 1140 1141 return (0); 1142 } 1143 1144 /* 1145 * Reconcile kernel and user view of the receive ring. 1146 * Same as for the txsync, this routine must be efficient. 1147 * The caller guarantees a single invocations, but races against 1148 * the rest of the driver should be handled here. 1149 * 1150 * On call, kring->rhead is the first packet that userspace wants 1151 * to keep, and kring->rcur is the wakeup point. 1152 * The kernel has previously reported packets up to kring->rtail. 1153 * 1154 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1155 * of whether or not we received an interrupt. 1156 */ 1157 static int 1158 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1159 { 1160 struct netmap_adapter *na = kring->na; 1161 struct netmap_ring *ring = kring->ring; 1162 if_t ifp = na->ifp; 1163 uint32_t nm_i; /* index into the netmap ring */ 1164 uint32_t nic_i; /* index into the NIC ring */ 1165 u_int n; 1166 u_int const lim = kring->nkr_num_slots - 1; 1167 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1168 int i = 0, rx_bytes = 0, rx_pkts = 0; 1169 1170 if_ctx_t ctx = if_getsoftc(ifp); 1171 if_shared_ctx_t sctx = ctx->ifc_sctx; 1172 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1173 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1174 iflib_fl_t fl = &rxq->ifr_fl[0]; 1175 struct if_rxd_info ri; 1176 qidx_t *cidxp; 1177 1178 /* 1179 * netmap only uses free list 0, to avoid out of order consumption 1180 * of receive buffers 1181 */ 1182 1183 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1184 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1185 1186 /* 1187 * First part: import newly received packets. 1188 * 1189 * nm_i is the index of the next free slot in the netmap ring, 1190 * nic_i is the index of the next received packet in the NIC ring 1191 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1192 * differ in case if_init() has been called while 1193 * in netmap mode. For the receive ring we have 1194 * 1195 * nic_i = fl->ifl_cidx; 1196 * nm_i = kring->nr_hwtail (previous) 1197 * and 1198 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1199 * 1200 * fl->ifl_cidx is set to 0 on a ring reinit 1201 */ 1202 if (netmap_no_pendintr || force_update) { 1203 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1204 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1205 int crclen = iflib_crcstrip ? 0 : 4; 1206 int error, avail; 1207 1208 /* 1209 * For the free list consumer index, we use the same 1210 * logic as in iflib_rxeof(). 1211 */ 1212 if (have_rxcq) 1213 cidxp = &rxq->ifr_cq_cidx; 1214 else 1215 cidxp = &fl->ifl_cidx; 1216 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1217 rxq->ifr_id, *cidxp, USHRT_MAX); 1218 1219 nic_i = fl->ifl_cidx; 1220 nm_i = netmap_idx_n2k(kring, nic_i); 1221 MPASS(nm_i == kring->nr_hwtail); 1222 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1223 rxd_info_zero(&ri); 1224 ri.iri_frags = rxq->ifr_frags; 1225 ri.iri_qsidx = kring->ring_id; 1226 ri.iri_ifp = ctx->ifc_ifp; 1227 ri.iri_cidx = *cidxp; 1228 1229 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1230 for (i = 0; i < ri.iri_nfrags; i++) { 1231 if (error) { 1232 ring->slot[nm_i].len = 0; 1233 ring->slot[nm_i].flags = 0; 1234 } else { 1235 ring->slot[nm_i].len = ri.iri_frags[i].irf_len; 1236 if (i == (ri.iri_nfrags - 1)) { 1237 ring->slot[nm_i].len -= crclen; 1238 ring->slot[nm_i].flags = 0; 1239 1240 /* Update receive counters */ 1241 rx_bytes += ri.iri_len; 1242 rx_pkts++; 1243 } else 1244 ring->slot[nm_i].flags = NS_MOREFRAG; 1245 } 1246 1247 bus_dmamap_sync(fl->ifl_buf_tag, 1248 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1249 nm_i = nm_next(nm_i, lim); 1250 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1251 } 1252 1253 if (have_rxcq) { 1254 *cidxp = ri.iri_cidx; 1255 while (*cidxp >= scctx->isc_nrxd[0]) 1256 *cidxp -= scctx->isc_nrxd[0]; 1257 } 1258 1259 } 1260 if (n) { /* update the state variables */ 1261 if (netmap_no_pendintr && !force_update) { 1262 /* diagnostics */ 1263 iflib_rx_miss ++; 1264 iflib_rx_miss_bufs += n; 1265 } 1266 kring->nr_hwtail = nm_i; 1267 } 1268 kring->nr_kflags &= ~NKR_PENDINTR; 1269 } 1270 /* 1271 * Second part: skip past packets that userspace has released. 1272 * (kring->nr_hwcur to head excluded), 1273 * and make the buffers available for reception. 1274 * As usual nm_i is the index in the netmap ring, 1275 * nic_i is the index in the NIC ring, and 1276 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1277 */ 1278 netmap_fl_refill(rxq, kring, false); 1279 1280 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 1281 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 1282 1283 return (0); 1284 } 1285 1286 static void 1287 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1288 { 1289 if_ctx_t ctx = if_getsoftc(na->ifp); 1290 1291 CTX_LOCK(ctx); 1292 if (onoff) { 1293 IFDI_INTR_ENABLE(ctx); 1294 } else { 1295 IFDI_INTR_DISABLE(ctx); 1296 } 1297 CTX_UNLOCK(ctx); 1298 } 1299 1300 static int 1301 iflib_netmap_attach(if_ctx_t ctx) 1302 { 1303 struct netmap_adapter na; 1304 1305 bzero(&na, sizeof(na)); 1306 1307 na.ifp = ctx->ifc_ifp; 1308 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS; 1309 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1310 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1311 1312 na.num_tx_desc = iflib_num_tx_descs(ctx); 1313 na.num_rx_desc = iflib_num_rx_descs(ctx); 1314 na.nm_txsync = iflib_netmap_txsync; 1315 na.nm_rxsync = iflib_netmap_rxsync; 1316 na.nm_register = iflib_netmap_register; 1317 na.nm_intr = iflib_netmap_intr; 1318 na.nm_config = iflib_netmap_config; 1319 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1320 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1321 return (netmap_attach(&na)); 1322 } 1323 1324 static int 1325 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1326 { 1327 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1328 struct netmap_slot *slot; 1329 1330 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1331 if (slot == NULL) 1332 return (0); 1333 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1334 /* 1335 * In netmap mode, set the map for the packet buffer. 1336 * NOTE: Some drivers (not this one) also need to set 1337 * the physical buffer address in the NIC ring. 1338 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1339 * netmap slot index, si 1340 */ 1341 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1342 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1343 NMB(na, slot + si)); 1344 } 1345 return (1); 1346 } 1347 1348 static int 1349 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1350 { 1351 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1352 struct netmap_kring *kring; 1353 struct netmap_slot *slot; 1354 1355 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1356 if (slot == NULL) 1357 return (0); 1358 kring = na->rx_rings[rxq->ifr_id]; 1359 netmap_fl_refill(rxq, kring, true); 1360 return (1); 1361 } 1362 1363 static void 1364 iflib_netmap_timer(void *arg) 1365 { 1366 iflib_txq_t txq = arg; 1367 if_ctx_t ctx = txq->ift_ctx; 1368 1369 /* 1370 * Wake up the netmap application, to give it a chance to 1371 * call txsync and reclaim more completed TX buffers. 1372 */ 1373 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1374 } 1375 1376 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1377 1378 #else 1379 #define iflib_netmap_txq_init(ctx, txq) (0) 1380 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1381 #define iflib_netmap_detach(ifp) 1382 #define netmap_enable_all_rings(ifp) 1383 #define netmap_disable_all_rings(ifp) 1384 1385 #define iflib_netmap_attach(ctx) (0) 1386 #define netmap_rx_irq(ifp, qid, budget) (0) 1387 #endif 1388 1389 #if defined(__i386__) || defined(__amd64__) 1390 static __inline void 1391 prefetch(void *x) 1392 { 1393 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1394 } 1395 1396 static __inline void 1397 prefetch2cachelines(void *x) 1398 { 1399 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1400 #if (CACHE_LINE_SIZE < 128) 1401 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1402 #endif 1403 } 1404 #else 1405 static __inline void 1406 prefetch(void *x) 1407 { 1408 } 1409 1410 static __inline void 1411 prefetch2cachelines(void *x) 1412 { 1413 } 1414 #endif 1415 1416 static void 1417 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1418 { 1419 iflib_fl_t fl; 1420 1421 fl = &rxq->ifr_fl[flid]; 1422 iru->iru_paddrs = fl->ifl_bus_addrs; 1423 iru->iru_idxs = fl->ifl_rxd_idxs; 1424 iru->iru_qsidx = rxq->ifr_id; 1425 iru->iru_buf_size = fl->ifl_buf_size; 1426 iru->iru_flidx = fl->ifl_id; 1427 } 1428 1429 static void 1430 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1431 { 1432 if (err) 1433 return; 1434 *(bus_addr_t *) arg = segs[0].ds_addr; 1435 } 1436 1437 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \ 1438 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \ 1439 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL) 1440 1441 int 1442 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1443 { 1444 int err; 1445 device_t dev = ctx->ifc_dev; 1446 bus_addr_t lowaddr; 1447 1448 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width); 1449 1450 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1451 align, 0, /* alignment, bounds */ 1452 lowaddr, /* lowaddr */ 1453 BUS_SPACE_MAXADDR, /* highaddr */ 1454 NULL, NULL, /* filter, filterarg */ 1455 size, /* maxsize */ 1456 1, /* nsegments */ 1457 size, /* maxsegsize */ 1458 BUS_DMA_ALLOCNOW, /* flags */ 1459 NULL, /* lockfunc */ 1460 NULL, /* lockarg */ 1461 &dma->idi_tag); 1462 if (err) { 1463 device_printf(dev, 1464 "%s: bus_dma_tag_create failed: %d\n", 1465 __func__, err); 1466 goto fail_0; 1467 } 1468 1469 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1470 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1471 if (err) { 1472 device_printf(dev, 1473 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1474 __func__, (uintmax_t)size, err); 1475 goto fail_1; 1476 } 1477 1478 dma->idi_paddr = IF_BAD_DMA; 1479 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1480 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1481 if (err || dma->idi_paddr == IF_BAD_DMA) { 1482 device_printf(dev, 1483 "%s: bus_dmamap_load failed: %d\n", 1484 __func__, err); 1485 goto fail_2; 1486 } 1487 1488 dma->idi_size = size; 1489 return (0); 1490 1491 fail_2: 1492 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1493 fail_1: 1494 bus_dma_tag_destroy(dma->idi_tag); 1495 fail_0: 1496 dma->idi_tag = NULL; 1497 1498 return (err); 1499 } 1500 1501 int 1502 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1503 { 1504 if_shared_ctx_t sctx = ctx->ifc_sctx; 1505 1506 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1507 1508 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1509 } 1510 1511 int 1512 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1513 { 1514 int i, err; 1515 iflib_dma_info_t *dmaiter; 1516 1517 dmaiter = dmalist; 1518 for (i = 0; i < count; i++, dmaiter++) { 1519 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1520 break; 1521 } 1522 if (err) 1523 iflib_dma_free_multi(dmalist, i); 1524 return (err); 1525 } 1526 1527 void 1528 iflib_dma_free(iflib_dma_info_t dma) 1529 { 1530 if (dma->idi_tag == NULL) 1531 return; 1532 if (dma->idi_paddr != IF_BAD_DMA) { 1533 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1534 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1535 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1536 dma->idi_paddr = IF_BAD_DMA; 1537 } 1538 if (dma->idi_vaddr != NULL) { 1539 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1540 dma->idi_vaddr = NULL; 1541 } 1542 bus_dma_tag_destroy(dma->idi_tag); 1543 dma->idi_tag = NULL; 1544 } 1545 1546 void 1547 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1548 { 1549 int i; 1550 iflib_dma_info_t *dmaiter = dmalist; 1551 1552 for (i = 0; i < count; i++, dmaiter++) 1553 iflib_dma_free(*dmaiter); 1554 } 1555 1556 static int 1557 iflib_fast_intr(void *arg) 1558 { 1559 iflib_filter_info_t info = arg; 1560 struct grouptask *gtask = info->ifi_task; 1561 int result; 1562 1563 DBG_COUNTER_INC(fast_intrs); 1564 if (info->ifi_filter != NULL) { 1565 result = info->ifi_filter(info->ifi_filter_arg); 1566 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1567 return (result); 1568 } 1569 1570 GROUPTASK_ENQUEUE(gtask); 1571 return (FILTER_HANDLED); 1572 } 1573 1574 static int 1575 iflib_fast_intr_rxtx(void *arg) 1576 { 1577 iflib_filter_info_t info = arg; 1578 struct grouptask *gtask = info->ifi_task; 1579 if_ctx_t ctx; 1580 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1581 iflib_txq_t txq; 1582 void *sc; 1583 int i, cidx, result; 1584 qidx_t txqid; 1585 bool intr_enable, intr_legacy; 1586 1587 DBG_COUNTER_INC(fast_intrs); 1588 if (info->ifi_filter != NULL) { 1589 result = info->ifi_filter(info->ifi_filter_arg); 1590 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1591 return (result); 1592 } 1593 1594 ctx = rxq->ifr_ctx; 1595 sc = ctx->ifc_softc; 1596 intr_enable = false; 1597 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1598 MPASS(rxq->ifr_ntxqirq); 1599 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1600 txqid = rxq->ifr_txqid[i]; 1601 txq = &ctx->ifc_txqs[txqid]; 1602 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1603 BUS_DMASYNC_POSTREAD); 1604 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1605 if (intr_legacy) 1606 intr_enable = true; 1607 else 1608 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1609 continue; 1610 } 1611 GROUPTASK_ENQUEUE(&txq->ift_task); 1612 } 1613 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1614 cidx = rxq->ifr_cq_cidx; 1615 else 1616 cidx = rxq->ifr_fl[0].ifl_cidx; 1617 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1618 GROUPTASK_ENQUEUE(gtask); 1619 else { 1620 if (intr_legacy) 1621 intr_enable = true; 1622 else 1623 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1624 DBG_COUNTER_INC(rx_intr_enables); 1625 } 1626 if (intr_enable) 1627 IFDI_INTR_ENABLE(ctx); 1628 return (FILTER_HANDLED); 1629 } 1630 1631 static int 1632 iflib_fast_intr_ctx(void *arg) 1633 { 1634 iflib_filter_info_t info = arg; 1635 struct grouptask *gtask = info->ifi_task; 1636 int result; 1637 1638 DBG_COUNTER_INC(fast_intrs); 1639 if (info->ifi_filter != NULL) { 1640 result = info->ifi_filter(info->ifi_filter_arg); 1641 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1642 return (result); 1643 } 1644 1645 if (gtask->gt_taskqueue != NULL) 1646 GROUPTASK_ENQUEUE(gtask); 1647 return (FILTER_HANDLED); 1648 } 1649 1650 static int 1651 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1652 driver_filter_t filter, driver_intr_t handler, void *arg, 1653 const char *name) 1654 { 1655 struct resource *res; 1656 void *tag = NULL; 1657 device_t dev = ctx->ifc_dev; 1658 int flags, i, rc; 1659 1660 flags = RF_ACTIVE; 1661 if (ctx->ifc_flags & IFC_LEGACY) 1662 flags |= RF_SHAREABLE; 1663 MPASS(rid < 512); 1664 i = rid; 1665 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1666 if (res == NULL) { 1667 device_printf(dev, 1668 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1669 return (ENOMEM); 1670 } 1671 irq->ii_res = res; 1672 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1673 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1674 filter, handler, arg, &tag); 1675 if (rc != 0) { 1676 device_printf(dev, 1677 "failed to setup interrupt for rid %d, name %s: %d\n", 1678 rid, name ? name : "unknown", rc); 1679 return (rc); 1680 } else if (name) 1681 bus_describe_intr(dev, res, tag, "%s", name); 1682 1683 irq->ii_tag = tag; 1684 return (0); 1685 } 1686 1687 /********************************************************************* 1688 * 1689 * Allocate DMA resources for TX buffers as well as memory for the TX 1690 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1691 * iflib_sw_tx_desc_array structure, storing all the information that 1692 * is needed to transmit a packet on the wire. This is called only 1693 * once at attach, setup is done every reset. 1694 * 1695 **********************************************************************/ 1696 static int 1697 iflib_txsd_alloc(iflib_txq_t txq) 1698 { 1699 if_ctx_t ctx = txq->ift_ctx; 1700 if_shared_ctx_t sctx = ctx->ifc_sctx; 1701 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1702 device_t dev = ctx->ifc_dev; 1703 bus_size_t tsomaxsize; 1704 bus_addr_t lowaddr; 1705 int err, nsegments, ntsosegments; 1706 bool tso; 1707 1708 nsegments = scctx->isc_tx_nsegments; 1709 ntsosegments = scctx->isc_tx_tso_segments_max; 1710 tsomaxsize = scctx->isc_tx_tso_size_max; 1711 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1712 tsomaxsize += sizeof(struct ether_vlan_header); 1713 MPASS(scctx->isc_ntxd[0] > 0); 1714 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1715 MPASS(nsegments > 0); 1716 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1717 MPASS(ntsosegments > 0); 1718 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1719 } 1720 1721 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1722 1723 /* 1724 * Set up DMA tags for TX buffers. 1725 */ 1726 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1727 1, 0, /* alignment, bounds */ 1728 lowaddr, /* lowaddr */ 1729 BUS_SPACE_MAXADDR, /* highaddr */ 1730 NULL, NULL, /* filter, filterarg */ 1731 sctx->isc_tx_maxsize, /* maxsize */ 1732 nsegments, /* nsegments */ 1733 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1734 0, /* flags */ 1735 NULL, /* lockfunc */ 1736 NULL, /* lockfuncarg */ 1737 &txq->ift_buf_tag))) { 1738 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1739 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1740 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1741 goto fail; 1742 } 1743 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1744 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1745 1, 0, /* alignment, bounds */ 1746 lowaddr, /* lowaddr */ 1747 BUS_SPACE_MAXADDR, /* highaddr */ 1748 NULL, NULL, /* filter, filterarg */ 1749 tsomaxsize, /* maxsize */ 1750 ntsosegments, /* nsegments */ 1751 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1752 0, /* flags */ 1753 NULL, /* lockfunc */ 1754 NULL, /* lockfuncarg */ 1755 &txq->ift_tso_buf_tag))) { 1756 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1757 err); 1758 goto fail; 1759 } 1760 1761 /* Allocate memory for the TX mbuf map. */ 1762 if (!(txq->ift_sds.ifsd_m = 1763 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1764 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1765 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1766 err = ENOMEM; 1767 goto fail; 1768 } 1769 1770 /* 1771 * Create the DMA maps for TX buffers. 1772 */ 1773 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1774 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1775 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1776 device_printf(dev, 1777 "Unable to allocate TX buffer DMA map memory\n"); 1778 err = ENOMEM; 1779 goto fail; 1780 } 1781 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1782 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1783 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1784 device_printf(dev, 1785 "Unable to allocate TSO TX buffer map memory\n"); 1786 err = ENOMEM; 1787 goto fail; 1788 } 1789 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1790 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1791 &txq->ift_sds.ifsd_map[i]); 1792 if (err != 0) { 1793 device_printf(dev, "Unable to create TX DMA map\n"); 1794 goto fail; 1795 } 1796 if (!tso) 1797 continue; 1798 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1799 &txq->ift_sds.ifsd_tso_map[i]); 1800 if (err != 0) { 1801 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1802 goto fail; 1803 } 1804 } 1805 return (0); 1806 fail: 1807 /* We free all, it handles case where we are in the middle */ 1808 iflib_tx_structures_free(ctx); 1809 return (err); 1810 } 1811 1812 static void 1813 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1814 { 1815 bus_dmamap_t map; 1816 1817 if (txq->ift_sds.ifsd_map != NULL) { 1818 map = txq->ift_sds.ifsd_map[i]; 1819 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1820 bus_dmamap_unload(txq->ift_buf_tag, map); 1821 bus_dmamap_destroy(txq->ift_buf_tag, map); 1822 txq->ift_sds.ifsd_map[i] = NULL; 1823 } 1824 1825 if (txq->ift_sds.ifsd_tso_map != NULL) { 1826 map = txq->ift_sds.ifsd_tso_map[i]; 1827 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1828 BUS_DMASYNC_POSTWRITE); 1829 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1830 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1831 txq->ift_sds.ifsd_tso_map[i] = NULL; 1832 } 1833 } 1834 1835 static void 1836 iflib_txq_destroy(iflib_txq_t txq) 1837 { 1838 if_ctx_t ctx = txq->ift_ctx; 1839 1840 for (int i = 0; i < txq->ift_size; i++) 1841 iflib_txsd_destroy(ctx, txq, i); 1842 1843 if (txq->ift_br != NULL) { 1844 ifmp_ring_free(txq->ift_br); 1845 txq->ift_br = NULL; 1846 } 1847 1848 mtx_destroy(&txq->ift_mtx); 1849 1850 if (txq->ift_sds.ifsd_map != NULL) { 1851 free(txq->ift_sds.ifsd_map, M_IFLIB); 1852 txq->ift_sds.ifsd_map = NULL; 1853 } 1854 if (txq->ift_sds.ifsd_tso_map != NULL) { 1855 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1856 txq->ift_sds.ifsd_tso_map = NULL; 1857 } 1858 if (txq->ift_sds.ifsd_m != NULL) { 1859 free(txq->ift_sds.ifsd_m, M_IFLIB); 1860 txq->ift_sds.ifsd_m = NULL; 1861 } 1862 if (txq->ift_buf_tag != NULL) { 1863 bus_dma_tag_destroy(txq->ift_buf_tag); 1864 txq->ift_buf_tag = NULL; 1865 } 1866 if (txq->ift_tso_buf_tag != NULL) { 1867 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1868 txq->ift_tso_buf_tag = NULL; 1869 } 1870 if (txq->ift_ifdi != NULL) { 1871 free(txq->ift_ifdi, M_IFLIB); 1872 } 1873 } 1874 1875 static void 1876 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1877 { 1878 struct mbuf **mp; 1879 1880 mp = &txq->ift_sds.ifsd_m[i]; 1881 if (*mp == NULL) 1882 return; 1883 1884 if (txq->ift_sds.ifsd_map != NULL) { 1885 bus_dmamap_sync(txq->ift_buf_tag, 1886 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1887 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1888 } 1889 if (txq->ift_sds.ifsd_tso_map != NULL) { 1890 bus_dmamap_sync(txq->ift_tso_buf_tag, 1891 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1892 bus_dmamap_unload(txq->ift_tso_buf_tag, 1893 txq->ift_sds.ifsd_tso_map[i]); 1894 } 1895 m_freem(*mp); 1896 DBG_COUNTER_INC(tx_frees); 1897 *mp = NULL; 1898 } 1899 1900 static int 1901 iflib_txq_setup(iflib_txq_t txq) 1902 { 1903 if_ctx_t ctx = txq->ift_ctx; 1904 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1905 if_shared_ctx_t sctx = ctx->ifc_sctx; 1906 iflib_dma_info_t di; 1907 int i; 1908 1909 /* Set number of descriptors available */ 1910 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1911 /* XXX make configurable */ 1912 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1913 1914 /* Reset indices */ 1915 txq->ift_cidx_processed = 0; 1916 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1917 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1918 1919 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1920 bzero((void *)di->idi_vaddr, di->idi_size); 1921 1922 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1923 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1924 bus_dmamap_sync(di->idi_tag, di->idi_map, 1925 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1926 return (0); 1927 } 1928 1929 /********************************************************************* 1930 * 1931 * Allocate DMA resources for RX buffers as well as memory for the RX 1932 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1933 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1934 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1935 * Since we use use one entry in iflib_sw_rx_desc_array per received 1936 * packet, the maximum number of entries we'll need is equal to the 1937 * number of hardware receive descriptors that we've allocated. 1938 * 1939 **********************************************************************/ 1940 static int 1941 iflib_rxsd_alloc(iflib_rxq_t rxq) 1942 { 1943 if_ctx_t ctx = rxq->ifr_ctx; 1944 if_shared_ctx_t sctx = ctx->ifc_sctx; 1945 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1946 device_t dev = ctx->ifc_dev; 1947 iflib_fl_t fl; 1948 bus_addr_t lowaddr; 1949 int err; 1950 1951 MPASS(scctx->isc_nrxd[0] > 0); 1952 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1953 1954 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1955 1956 fl = rxq->ifr_fl; 1957 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1958 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1959 /* Set up DMA tag for RX buffers. */ 1960 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1961 1, 0, /* alignment, bounds */ 1962 lowaddr, /* lowaddr */ 1963 BUS_SPACE_MAXADDR, /* highaddr */ 1964 NULL, NULL, /* filter, filterarg */ 1965 sctx->isc_rx_maxsize, /* maxsize */ 1966 sctx->isc_rx_nsegments, /* nsegments */ 1967 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1968 0, /* flags */ 1969 NULL, /* lockfunc */ 1970 NULL, /* lockarg */ 1971 &fl->ifl_buf_tag); 1972 if (err) { 1973 device_printf(dev, 1974 "Unable to allocate RX DMA tag: %d\n", err); 1975 goto fail; 1976 } 1977 1978 /* Allocate memory for the RX mbuf map. */ 1979 if (!(fl->ifl_sds.ifsd_m = 1980 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1981 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1982 device_printf(dev, 1983 "Unable to allocate RX mbuf map memory\n"); 1984 err = ENOMEM; 1985 goto fail; 1986 } 1987 1988 /* Allocate memory for the direct RX cluster pointer map. */ 1989 if (!(fl->ifl_sds.ifsd_cl = 1990 (caddr_t *) malloc(sizeof(caddr_t) * 1991 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1992 device_printf(dev, 1993 "Unable to allocate RX cluster map memory\n"); 1994 err = ENOMEM; 1995 goto fail; 1996 } 1997 1998 /* Allocate memory for the RX cluster bus address map. */ 1999 if (!(fl->ifl_sds.ifsd_ba = 2000 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 2001 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2002 device_printf(dev, 2003 "Unable to allocate RX bus address map memory\n"); 2004 err = ENOMEM; 2005 goto fail; 2006 } 2007 2008 /* 2009 * Create the DMA maps for RX buffers. 2010 */ 2011 if (!(fl->ifl_sds.ifsd_map = 2012 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2013 device_printf(dev, 2014 "Unable to allocate RX buffer DMA map memory\n"); 2015 err = ENOMEM; 2016 goto fail; 2017 } 2018 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 2019 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 2020 &fl->ifl_sds.ifsd_map[i]); 2021 if (err != 0) { 2022 device_printf(dev, "Unable to create RX buffer DMA map\n"); 2023 goto fail; 2024 } 2025 } 2026 } 2027 return (0); 2028 2029 fail: 2030 iflib_rx_structures_free(ctx); 2031 return (err); 2032 } 2033 2034 /* 2035 * Internal service routines 2036 */ 2037 2038 struct rxq_refill_cb_arg { 2039 int error; 2040 bus_dma_segment_t seg; 2041 int nseg; 2042 }; 2043 2044 static void 2045 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2046 { 2047 struct rxq_refill_cb_arg *cb_arg = arg; 2048 2049 cb_arg->error = error; 2050 cb_arg->seg = segs[0]; 2051 cb_arg->nseg = nseg; 2052 } 2053 2054 /** 2055 * iflib_fl_refill - refill an rxq free-buffer list 2056 * @ctx: the iflib context 2057 * @fl: the free list to refill 2058 * @count: the number of new buffers to allocate 2059 * 2060 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 2061 * The caller must assure that @count does not exceed the queue's capacity 2062 * minus one (since we always leave a descriptor unavailable). 2063 */ 2064 static uint8_t 2065 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 2066 { 2067 struct if_rxd_update iru; 2068 struct rxq_refill_cb_arg cb_arg; 2069 struct mbuf *m; 2070 caddr_t cl, *sd_cl; 2071 struct mbuf **sd_m; 2072 bus_dmamap_t *sd_map; 2073 bus_addr_t bus_addr, *sd_ba; 2074 int err, frag_idx, i, idx, n, pidx; 2075 qidx_t credits; 2076 2077 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 2078 2079 sd_m = fl->ifl_sds.ifsd_m; 2080 sd_map = fl->ifl_sds.ifsd_map; 2081 sd_cl = fl->ifl_sds.ifsd_cl; 2082 sd_ba = fl->ifl_sds.ifsd_ba; 2083 pidx = fl->ifl_pidx; 2084 idx = pidx; 2085 frag_idx = fl->ifl_fragidx; 2086 credits = fl->ifl_credits; 2087 2088 i = 0; 2089 n = count; 2090 MPASS(n > 0); 2091 MPASS(credits + n <= fl->ifl_size); 2092 2093 if (pidx < fl->ifl_cidx) 2094 MPASS(pidx + n <= fl->ifl_cidx); 2095 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 2096 MPASS(fl->ifl_gen == 0); 2097 if (pidx > fl->ifl_cidx) 2098 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 2099 2100 DBG_COUNTER_INC(fl_refills); 2101 if (n > 8) 2102 DBG_COUNTER_INC(fl_refills_large); 2103 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 2104 while (n-- > 0) { 2105 /* 2106 * We allocate an uninitialized mbuf + cluster, mbuf is 2107 * initialized after rx. 2108 * 2109 * If the cluster is still set then we know a minimum sized 2110 * packet was received 2111 */ 2112 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2113 &frag_idx); 2114 if (frag_idx < 0) 2115 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2116 MPASS(frag_idx >= 0); 2117 if ((cl = sd_cl[frag_idx]) == NULL) { 2118 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2119 if (__predict_false(cl == NULL)) 2120 break; 2121 2122 cb_arg.error = 0; 2123 MPASS(sd_map != NULL); 2124 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2125 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2126 BUS_DMA_NOWAIT); 2127 if (__predict_false(err != 0 || cb_arg.error)) { 2128 uma_zfree(fl->ifl_zone, cl); 2129 break; 2130 } 2131 2132 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2133 sd_cl[frag_idx] = cl; 2134 #if MEMORY_LOGGING 2135 fl->ifl_cl_enqueued++; 2136 #endif 2137 } else { 2138 bus_addr = sd_ba[frag_idx]; 2139 } 2140 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2141 BUS_DMASYNC_PREREAD); 2142 2143 if (sd_m[frag_idx] == NULL) { 2144 m = m_gethdr_raw(M_NOWAIT, 0); 2145 if (__predict_false(m == NULL)) 2146 break; 2147 sd_m[frag_idx] = m; 2148 } 2149 bit_set(fl->ifl_rx_bitmap, frag_idx); 2150 #if MEMORY_LOGGING 2151 fl->ifl_m_enqueued++; 2152 #endif 2153 2154 DBG_COUNTER_INC(rx_allocs); 2155 fl->ifl_rxd_idxs[i] = frag_idx; 2156 fl->ifl_bus_addrs[i] = bus_addr; 2157 credits++; 2158 i++; 2159 MPASS(credits <= fl->ifl_size); 2160 if (++idx == fl->ifl_size) { 2161 #ifdef INVARIANTS 2162 fl->ifl_gen = 1; 2163 #endif 2164 idx = 0; 2165 } 2166 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2167 iru.iru_pidx = pidx; 2168 iru.iru_count = i; 2169 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2170 fl->ifl_pidx = idx; 2171 fl->ifl_credits = credits; 2172 pidx = idx; 2173 i = 0; 2174 } 2175 } 2176 2177 if (n < count - 1) { 2178 if (i != 0) { 2179 iru.iru_pidx = pidx; 2180 iru.iru_count = i; 2181 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2182 fl->ifl_pidx = idx; 2183 fl->ifl_credits = credits; 2184 } 2185 DBG_COUNTER_INC(rxd_flush); 2186 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2187 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2188 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2189 fl->ifl_id, fl->ifl_pidx); 2190 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2191 fl->ifl_fragidx = frag_idx + 1; 2192 if (fl->ifl_fragidx == fl->ifl_size) 2193 fl->ifl_fragidx = 0; 2194 } else { 2195 fl->ifl_fragidx = frag_idx; 2196 } 2197 } 2198 2199 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2200 } 2201 2202 static inline uint8_t 2203 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2204 { 2205 /* 2206 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2207 * This is important as it confuses most NICs. For instance, 2208 * Intel NICs have (per receive ring) RDH and RDT registers, where 2209 * RDH points to the next receive descriptor to be used by the NIC, 2210 * and RDT for the next receive descriptor to be published by the 2211 * driver to the NIC (RDT - 1 is thus the last valid one). 2212 * The condition RDH == RDT means no descriptors are available to 2213 * the NIC, and thus it would be ambiguous if it also meant that 2214 * all the descriptors are available to the NIC. 2215 */ 2216 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2217 #ifdef INVARIANTS 2218 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2219 #endif 2220 2221 MPASS(fl->ifl_credits <= fl->ifl_size); 2222 MPASS(reclaimable == delta); 2223 2224 if (reclaimable > 0) 2225 return (iflib_fl_refill(ctx, fl, reclaimable)); 2226 return (0); 2227 } 2228 2229 uint8_t 2230 iflib_in_detach(if_ctx_t ctx) 2231 { 2232 bool in_detach; 2233 2234 STATE_LOCK(ctx); 2235 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2236 STATE_UNLOCK(ctx); 2237 return (in_detach); 2238 } 2239 2240 static void 2241 iflib_fl_bufs_free(iflib_fl_t fl) 2242 { 2243 iflib_dma_info_t idi = fl->ifl_ifdi; 2244 bus_dmamap_t sd_map; 2245 uint32_t i; 2246 2247 for (i = 0; i < fl->ifl_size; i++) { 2248 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2249 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2250 2251 if (*sd_cl != NULL) { 2252 sd_map = fl->ifl_sds.ifsd_map[i]; 2253 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2254 BUS_DMASYNC_POSTREAD); 2255 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2256 uma_zfree(fl->ifl_zone, *sd_cl); 2257 *sd_cl = NULL; 2258 if (*sd_m != NULL) { 2259 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2260 m_free_raw(*sd_m); 2261 *sd_m = NULL; 2262 } 2263 } else { 2264 MPASS(*sd_m == NULL); 2265 } 2266 #if MEMORY_LOGGING 2267 fl->ifl_m_dequeued++; 2268 fl->ifl_cl_dequeued++; 2269 #endif 2270 } 2271 #ifdef INVARIANTS 2272 for (i = 0; i < fl->ifl_size; i++) { 2273 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2274 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2275 } 2276 #endif 2277 /* 2278 * Reset free list values 2279 */ 2280 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2281 bzero(idi->idi_vaddr, idi->idi_size); 2282 } 2283 2284 /********************************************************************* 2285 * 2286 * Initialize a free list and its buffers. 2287 * 2288 **********************************************************************/ 2289 static int 2290 iflib_fl_setup(iflib_fl_t fl) 2291 { 2292 iflib_rxq_t rxq = fl->ifl_rxq; 2293 if_ctx_t ctx = rxq->ifr_ctx; 2294 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2295 int qidx; 2296 2297 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2298 /* 2299 ** Free current RX buffer structs and their mbufs 2300 */ 2301 iflib_fl_bufs_free(fl); 2302 /* Now replenish the mbufs */ 2303 MPASS(fl->ifl_credits == 0); 2304 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2305 if (scctx->isc_rxd_buf_size[qidx] != 0) 2306 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2307 else 2308 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2309 /* 2310 * ifl_buf_size may be a driver-supplied value, so pull it up 2311 * to the selected mbuf size. 2312 */ 2313 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2314 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2315 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2316 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2317 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2318 2319 /* 2320 * Avoid pre-allocating zillions of clusters to an idle card 2321 * potentially speeding up attach. In any case make sure 2322 * to leave a descriptor unavailable. See the comment in 2323 * iflib_fl_refill_all(). 2324 */ 2325 MPASS(fl->ifl_size > 0); 2326 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2327 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2328 return (ENOBUFS); 2329 /* 2330 * handle failure 2331 */ 2332 MPASS(rxq != NULL); 2333 MPASS(fl->ifl_ifdi != NULL); 2334 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2335 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2336 return (0); 2337 } 2338 2339 /********************************************************************* 2340 * 2341 * Free receive ring data structures 2342 * 2343 **********************************************************************/ 2344 static void 2345 iflib_rx_sds_free(iflib_rxq_t rxq) 2346 { 2347 iflib_fl_t fl; 2348 int i, j; 2349 2350 if (rxq->ifr_fl != NULL) { 2351 for (i = 0; i < rxq->ifr_nfl; i++) { 2352 fl = &rxq->ifr_fl[i]; 2353 if (fl->ifl_buf_tag != NULL) { 2354 if (fl->ifl_sds.ifsd_map != NULL) { 2355 for (j = 0; j < fl->ifl_size; j++) { 2356 bus_dmamap_sync( 2357 fl->ifl_buf_tag, 2358 fl->ifl_sds.ifsd_map[j], 2359 BUS_DMASYNC_POSTREAD); 2360 bus_dmamap_unload( 2361 fl->ifl_buf_tag, 2362 fl->ifl_sds.ifsd_map[j]); 2363 bus_dmamap_destroy( 2364 fl->ifl_buf_tag, 2365 fl->ifl_sds.ifsd_map[j]); 2366 } 2367 } 2368 bus_dma_tag_destroy(fl->ifl_buf_tag); 2369 fl->ifl_buf_tag = NULL; 2370 } 2371 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2372 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2373 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2374 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2375 free(fl->ifl_rx_bitmap, M_IFLIB); 2376 fl->ifl_sds.ifsd_m = NULL; 2377 fl->ifl_sds.ifsd_cl = NULL; 2378 fl->ifl_sds.ifsd_ba = NULL; 2379 fl->ifl_sds.ifsd_map = NULL; 2380 fl->ifl_rx_bitmap = NULL; 2381 } 2382 free(rxq->ifr_fl, M_IFLIB); 2383 rxq->ifr_fl = NULL; 2384 free(rxq->ifr_ifdi, M_IFLIB); 2385 rxq->ifr_ifdi = NULL; 2386 rxq->ifr_cq_cidx = 0; 2387 } 2388 } 2389 2390 /* 2391 * Timer routine 2392 */ 2393 static void 2394 iflib_timer(void *arg) 2395 { 2396 iflib_txq_t txq = arg; 2397 if_ctx_t ctx = txq->ift_ctx; 2398 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2399 uint64_t this_tick = ticks; 2400 2401 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2402 return; 2403 2404 /* 2405 ** Check on the state of the TX queue(s), this 2406 ** can be done without the lock because its RO 2407 ** and the HUNG state will be static if set. 2408 */ 2409 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) { 2410 txq->ift_last_timer_tick = this_tick; 2411 IFDI_TIMER(ctx, txq->ift_id); 2412 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2413 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2414 (sctx->isc_pause_frames == 0))) 2415 goto hung; 2416 2417 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2418 ifmp_ring_is_stalled(txq->ift_br)) { 2419 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, 2420 ("queue can't be marked as hung if interface is down")); 2421 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2422 } 2423 txq->ift_cleaned_prev = txq->ift_cleaned; 2424 } 2425 /* handle any laggards */ 2426 if (txq->ift_db_pending) 2427 GROUPTASK_ENQUEUE(&txq->ift_task); 2428 2429 sctx->isc_pause_frames = 0; 2430 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2431 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, 2432 txq, txq->ift_timer.c_cpu); 2433 return; 2434 2435 hung: 2436 device_printf(ctx->ifc_dev, 2437 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2438 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2439 STATE_LOCK(ctx); 2440 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2441 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2442 iflib_admin_intr_deferred(ctx); 2443 STATE_UNLOCK(ctx); 2444 } 2445 2446 static uint16_t 2447 iflib_get_mbuf_size_for(unsigned int size) 2448 { 2449 2450 if (size <= MCLBYTES) 2451 return (MCLBYTES); 2452 else 2453 return (MJUMPAGESIZE); 2454 } 2455 2456 static void 2457 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2458 { 2459 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2460 2461 /* 2462 * XXX don't set the max_frame_size to larger 2463 * than the hardware can handle 2464 */ 2465 ctx->ifc_rx_mbuf_sz = 2466 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2467 } 2468 2469 uint32_t 2470 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2471 { 2472 2473 return (ctx->ifc_rx_mbuf_sz); 2474 } 2475 2476 static void 2477 iflib_init_locked(if_ctx_t ctx) 2478 { 2479 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2480 if_t ifp = ctx->ifc_ifp; 2481 iflib_fl_t fl; 2482 iflib_txq_t txq; 2483 iflib_rxq_t rxq; 2484 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2485 2486 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2487 IFDI_INTR_DISABLE(ctx); 2488 2489 /* 2490 * See iflib_stop(). Useful in case iflib_init_locked() is 2491 * called without first calling iflib_stop(). 2492 */ 2493 netmap_disable_all_rings(ifp); 2494 2495 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2496 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2497 /* Set hardware offload abilities */ 2498 if_clearhwassist(ifp); 2499 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2500 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2501 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2502 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2503 if (if_getcapenable(ifp) & IFCAP_TSO4) 2504 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2505 if (if_getcapenable(ifp) & IFCAP_TSO6) 2506 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2507 2508 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 2509 CALLOUT_LOCK(txq); 2510 callout_stop(&txq->ift_timer); 2511 #ifdef DEV_NETMAP 2512 callout_stop(&txq->ift_netmap_timer); 2513 #endif /* DEV_NETMAP */ 2514 CALLOUT_UNLOCK(txq); 2515 (void)iflib_netmap_txq_init(ctx, txq); 2516 } 2517 2518 /* 2519 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2520 * that drivers can use the value when setting up the hardware receive 2521 * buffers. 2522 */ 2523 iflib_calc_rx_mbuf_sz(ctx); 2524 2525 #ifdef INVARIANTS 2526 i = if_getdrvflags(ifp); 2527 #endif 2528 IFDI_INIT(ctx); 2529 MPASS(if_getdrvflags(ifp) == i); 2530 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 2531 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2532 /* This rxq is in netmap mode. Skip normal init. */ 2533 continue; 2534 } 2535 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2536 if (iflib_fl_setup(fl)) { 2537 device_printf(ctx->ifc_dev, 2538 "setting up free list %d failed - " 2539 "check cluster settings\n", j); 2540 goto done; 2541 } 2542 } 2543 } 2544 done: 2545 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2546 IFDI_INTR_ENABLE(ctx); 2547 txq = ctx->ifc_txqs; 2548 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) 2549 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 2550 txq->ift_timer.c_cpu); 2551 2552 /* Re-enable txsync/rxsync. */ 2553 netmap_enable_all_rings(ifp); 2554 } 2555 2556 static int 2557 iflib_media_change(if_t ifp) 2558 { 2559 if_ctx_t ctx = if_getsoftc(ifp); 2560 int err; 2561 2562 CTX_LOCK(ctx); 2563 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2564 iflib_if_init_locked(ctx); 2565 CTX_UNLOCK(ctx); 2566 return (err); 2567 } 2568 2569 static void 2570 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2571 { 2572 if_ctx_t ctx = if_getsoftc(ifp); 2573 2574 CTX_LOCK(ctx); 2575 IFDI_UPDATE_ADMIN_STATUS(ctx); 2576 IFDI_MEDIA_STATUS(ctx, ifmr); 2577 CTX_UNLOCK(ctx); 2578 } 2579 2580 void 2581 iflib_stop(if_ctx_t ctx) 2582 { 2583 iflib_txq_t txq = ctx->ifc_txqs; 2584 iflib_rxq_t rxq = ctx->ifc_rxqs; 2585 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2586 if_shared_ctx_t sctx = ctx->ifc_sctx; 2587 iflib_dma_info_t di; 2588 iflib_fl_t fl; 2589 int i, j; 2590 2591 /* Tell the stack that the interface is no longer active */ 2592 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2593 2594 IFDI_INTR_DISABLE(ctx); 2595 DELAY(1000); 2596 IFDI_STOP(ctx); 2597 DELAY(1000); 2598 2599 /* 2600 * Stop any pending txsync/rxsync and prevent new ones 2601 * form starting. Processes blocked in poll() will get 2602 * POLLERR. 2603 */ 2604 netmap_disable_all_rings(ctx->ifc_ifp); 2605 2606 iflib_debug_reset(); 2607 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2608 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2609 /* make sure all transmitters have completed before proceeding XXX */ 2610 2611 CALLOUT_LOCK(txq); 2612 callout_stop(&txq->ift_timer); 2613 #ifdef DEV_NETMAP 2614 callout_stop(&txq->ift_netmap_timer); 2615 #endif /* DEV_NETMAP */ 2616 CALLOUT_UNLOCK(txq); 2617 2618 /* clean any enqueued buffers */ 2619 iflib_ifmp_purge(txq); 2620 /* Free any existing tx buffers. */ 2621 for (j = 0; j < txq->ift_size; j++) { 2622 iflib_txsd_free(ctx, txq, j); 2623 } 2624 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2625 txq->ift_in_use = txq->ift_gen = txq->ift_no_desc_avail = 0; 2626 if (sctx->isc_flags & IFLIB_PRESERVE_TX_INDICES) 2627 txq->ift_cidx = txq->ift_pidx; 2628 else 2629 txq->ift_cidx = txq->ift_pidx = 0; 2630 2631 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2632 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2633 txq->ift_pullups = 0; 2634 ifmp_ring_reset_stats(txq->ift_br); 2635 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2636 bzero((void *)di->idi_vaddr, di->idi_size); 2637 } 2638 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2639 if (rxq->ifr_task.gt_taskqueue != NULL) 2640 gtaskqueue_drain(rxq->ifr_task.gt_taskqueue, 2641 &rxq->ifr_task.gt_task); 2642 2643 rxq->ifr_cq_cidx = 0; 2644 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2645 bzero((void *)di->idi_vaddr, di->idi_size); 2646 /* also resets the free lists pidx/cidx */ 2647 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2648 iflib_fl_bufs_free(fl); 2649 } 2650 } 2651 2652 static inline caddr_t 2653 calc_next_rxd(iflib_fl_t fl, int cidx) 2654 { 2655 qidx_t size; 2656 int nrxd; 2657 caddr_t start, end, cur, next; 2658 2659 nrxd = fl->ifl_size; 2660 size = fl->ifl_rxd_size; 2661 start = fl->ifl_ifdi->idi_vaddr; 2662 2663 if (__predict_false(size == 0)) 2664 return (start); 2665 cur = start + size*cidx; 2666 end = start + size*nrxd; 2667 next = CACHE_PTR_NEXT(cur); 2668 return (next < end ? next : start); 2669 } 2670 2671 static inline void 2672 prefetch_pkts(iflib_fl_t fl, int cidx) 2673 { 2674 int nextptr; 2675 int nrxd = fl->ifl_size; 2676 caddr_t next_rxd; 2677 2678 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2679 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2680 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2681 next_rxd = calc_next_rxd(fl, cidx); 2682 prefetch(next_rxd); 2683 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2684 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2685 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2686 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2687 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2688 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2689 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2690 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2691 } 2692 2693 static struct mbuf * 2694 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2695 int *pf_rv, if_rxd_info_t ri) 2696 { 2697 bus_dmamap_t map; 2698 iflib_fl_t fl; 2699 caddr_t payload; 2700 struct mbuf *m; 2701 int flid, cidx, len, next; 2702 2703 map = NULL; 2704 flid = irf->irf_flid; 2705 cidx = irf->irf_idx; 2706 fl = &rxq->ifr_fl[flid]; 2707 sd->ifsd_fl = fl; 2708 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2709 fl->ifl_credits--; 2710 #if MEMORY_LOGGING 2711 fl->ifl_m_dequeued++; 2712 #endif 2713 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2714 prefetch_pkts(fl, cidx); 2715 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2716 prefetch(&fl->ifl_sds.ifsd_map[next]); 2717 map = fl->ifl_sds.ifsd_map[cidx]; 2718 2719 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2720 2721 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2722 irf->irf_len != 0) { 2723 payload = *sd->ifsd_cl; 2724 payload += ri->iri_pad; 2725 len = ri->iri_len - ri->iri_pad; 2726 *pf_rv = pfil_mem_in(rxq->pfil, payload, len, ri->iri_ifp, &m); 2727 switch (*pf_rv) { 2728 case PFIL_DROPPED: 2729 case PFIL_CONSUMED: 2730 /* 2731 * The filter ate it. Everything is recycled. 2732 */ 2733 m = NULL; 2734 unload = 0; 2735 break; 2736 case PFIL_REALLOCED: 2737 /* 2738 * The filter copied it. Everything is recycled. 2739 * 'm' points at new mbuf. 2740 */ 2741 unload = 0; 2742 break; 2743 case PFIL_PASS: 2744 /* 2745 * Filter said it was OK, so receive like 2746 * normal 2747 */ 2748 m = fl->ifl_sds.ifsd_m[cidx]; 2749 fl->ifl_sds.ifsd_m[cidx] = NULL; 2750 break; 2751 default: 2752 MPASS(0); 2753 } 2754 } else { 2755 m = fl->ifl_sds.ifsd_m[cidx]; 2756 fl->ifl_sds.ifsd_m[cidx] = NULL; 2757 if (pf_rv != NULL) 2758 *pf_rv = PFIL_PASS; 2759 } 2760 2761 if (unload && irf->irf_len != 0) 2762 bus_dmamap_unload(fl->ifl_buf_tag, map); 2763 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2764 if (__predict_false(fl->ifl_cidx == 0)) 2765 fl->ifl_gen = 0; 2766 bit_clear(fl->ifl_rx_bitmap, cidx); 2767 return (m); 2768 } 2769 2770 static struct mbuf * 2771 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2772 { 2773 struct mbuf *m, *mh, *mt; 2774 caddr_t cl; 2775 int *pf_rv_ptr, flags, i, padlen; 2776 bool consumed; 2777 2778 i = 0; 2779 mh = NULL; 2780 consumed = false; 2781 *pf_rv = PFIL_PASS; 2782 pf_rv_ptr = pf_rv; 2783 do { 2784 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2785 pf_rv_ptr, ri); 2786 2787 MPASS(*sd->ifsd_cl != NULL); 2788 2789 /* 2790 * Exclude zero-length frags & frags from 2791 * packets the filter has consumed or dropped 2792 */ 2793 if (ri->iri_frags[i].irf_len == 0 || consumed || 2794 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2795 if (mh == NULL) { 2796 /* everything saved here */ 2797 consumed = true; 2798 pf_rv_ptr = NULL; 2799 continue; 2800 } 2801 /* XXX we can save the cluster here, but not the mbuf */ 2802 m_init(m, M_NOWAIT, MT_DATA, 0); 2803 m_free(m); 2804 continue; 2805 } 2806 if (mh == NULL) { 2807 flags = M_PKTHDR|M_EXT; 2808 mh = mt = m; 2809 padlen = ri->iri_pad; 2810 } else { 2811 flags = M_EXT; 2812 mt->m_next = m; 2813 mt = m; 2814 /* assuming padding is only on the first fragment */ 2815 padlen = 0; 2816 } 2817 cl = *sd->ifsd_cl; 2818 *sd->ifsd_cl = NULL; 2819 2820 /* Can these two be made one ? */ 2821 m_init(m, M_NOWAIT, MT_DATA, flags); 2822 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2823 /* 2824 * These must follow m_init and m_cljset 2825 */ 2826 m->m_data += padlen; 2827 ri->iri_len -= padlen; 2828 m->m_len = ri->iri_frags[i].irf_len; 2829 } while (++i < ri->iri_nfrags); 2830 2831 return (mh); 2832 } 2833 2834 /* 2835 * Process one software descriptor 2836 */ 2837 static struct mbuf * 2838 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2839 { 2840 struct if_rxsd sd; 2841 struct mbuf *m; 2842 int pf_rv; 2843 2844 /* should I merge this back in now that the two paths are basically duplicated? */ 2845 if (ri->iri_nfrags == 1 && 2846 ri->iri_frags[0].irf_len != 0 && 2847 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2848 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2849 &pf_rv, ri); 2850 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2851 return (m); 2852 if (pf_rv == PFIL_PASS) { 2853 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2854 #ifndef __NO_STRICT_ALIGNMENT 2855 if (!IP_ALIGNED(m) && ri->iri_pad == 0) 2856 m->m_data += 2; 2857 #endif 2858 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2859 m->m_len = ri->iri_frags[0].irf_len; 2860 m->m_data += ri->iri_pad; 2861 ri->iri_len -= ri->iri_pad; 2862 } 2863 } else { 2864 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2865 if (m == NULL) 2866 return (NULL); 2867 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2868 return (m); 2869 } 2870 m->m_pkthdr.len = ri->iri_len; 2871 m->m_pkthdr.rcvif = ri->iri_ifp; 2872 m->m_flags |= ri->iri_flags; 2873 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2874 m->m_pkthdr.flowid = ri->iri_flowid; 2875 M_HASHTYPE_SET(m, ri->iri_rsstype); 2876 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2877 m->m_pkthdr.csum_data = ri->iri_csum_data; 2878 return (m); 2879 } 2880 2881 #if defined(INET6) || defined(INET) 2882 static void 2883 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2884 { 2885 CURVNET_SET(if_getvnet(lc->ifp)); 2886 #if defined(INET6) 2887 *v6 = V_ip6_forwarding; 2888 #endif 2889 #if defined(INET) 2890 *v4 = V_ipforwarding; 2891 #endif 2892 CURVNET_RESTORE(); 2893 } 2894 2895 /* 2896 * Returns true if it's possible this packet could be LROed. 2897 * if it returns false, it is guaranteed that tcp_lro_rx() 2898 * would not return zero. 2899 */ 2900 static bool 2901 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2902 { 2903 struct ether_header *eh; 2904 2905 eh = mtod(m, struct ether_header *); 2906 switch (eh->ether_type) { 2907 #if defined(INET6) 2908 case htons(ETHERTYPE_IPV6): 2909 return (!v6_forwarding); 2910 #endif 2911 #if defined (INET) 2912 case htons(ETHERTYPE_IP): 2913 return (!v4_forwarding); 2914 #endif 2915 } 2916 2917 return false; 2918 } 2919 #else 2920 static void 2921 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2922 { 2923 } 2924 #endif 2925 2926 static void 2927 _task_fn_rx_watchdog(void *context) 2928 { 2929 iflib_rxq_t rxq = context; 2930 2931 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2932 } 2933 2934 static uint8_t 2935 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2936 { 2937 if_t ifp; 2938 if_ctx_t ctx = rxq->ifr_ctx; 2939 if_shared_ctx_t sctx = ctx->ifc_sctx; 2940 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2941 int avail, i; 2942 qidx_t *cidxp; 2943 struct if_rxd_info ri; 2944 int err, budget_left, rx_bytes, rx_pkts; 2945 iflib_fl_t fl; 2946 int lro_enabled; 2947 bool v4_forwarding, v6_forwarding, lro_possible; 2948 uint8_t retval = 0; 2949 2950 /* 2951 * XXX early demux data packets so that if_input processing only handles 2952 * acks in interrupt context 2953 */ 2954 struct mbuf *m, *mh, *mt, *mf; 2955 2956 NET_EPOCH_ASSERT(); 2957 2958 lro_possible = v4_forwarding = v6_forwarding = false; 2959 ifp = ctx->ifc_ifp; 2960 mh = mt = NULL; 2961 MPASS(budget > 0); 2962 rx_pkts = rx_bytes = 0; 2963 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2964 cidxp = &rxq->ifr_cq_cidx; 2965 else 2966 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2967 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2968 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2969 retval |= iflib_fl_refill_all(ctx, fl); 2970 DBG_COUNTER_INC(rx_unavail); 2971 return (retval); 2972 } 2973 2974 /* pfil needs the vnet to be set */ 2975 CURVNET_SET_QUIET(if_getvnet(ifp)); 2976 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2977 if (__predict_false(!CTX_ACTIVE(ctx))) { 2978 DBG_COUNTER_INC(rx_ctx_inactive); 2979 break; 2980 } 2981 /* 2982 * Reset client set fields to their default values 2983 */ 2984 rxd_info_zero(&ri); 2985 ri.iri_qsidx = rxq->ifr_id; 2986 ri.iri_cidx = *cidxp; 2987 ri.iri_ifp = ifp; 2988 ri.iri_frags = rxq->ifr_frags; 2989 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2990 2991 if (err) 2992 goto err; 2993 rx_pkts += 1; 2994 rx_bytes += ri.iri_len; 2995 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2996 *cidxp = ri.iri_cidx; 2997 /* Update our consumer index */ 2998 /* XXX NB: shurd - check if this is still safe */ 2999 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 3000 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 3001 /* was this only a completion queue message? */ 3002 if (__predict_false(ri.iri_nfrags == 0)) 3003 continue; 3004 } 3005 MPASS(ri.iri_nfrags != 0); 3006 MPASS(ri.iri_len != 0); 3007 3008 /* will advance the cidx on the corresponding free lists */ 3009 m = iflib_rxd_pkt_get(rxq, &ri); 3010 avail--; 3011 budget_left--; 3012 if (avail == 0 && budget_left) 3013 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 3014 3015 if (__predict_false(m == NULL)) 3016 continue; 3017 3018 /* imm_pkt: -- cxgb */ 3019 if (mh == NULL) 3020 mh = mt = m; 3021 else { 3022 mt->m_nextpkt = m; 3023 mt = m; 3024 } 3025 } 3026 CURVNET_RESTORE(); 3027 /* make sure that we can refill faster than drain */ 3028 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3029 retval |= iflib_fl_refill_all(ctx, fl); 3030 3031 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 3032 if (lro_enabled) 3033 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 3034 mt = mf = NULL; 3035 while (mh != NULL) { 3036 m = mh; 3037 mh = mh->m_nextpkt; 3038 m->m_nextpkt = NULL; 3039 #ifndef __NO_STRICT_ALIGNMENT 3040 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 3041 continue; 3042 #endif 3043 #if defined(INET6) || defined(INET) 3044 if (lro_enabled) { 3045 if (!lro_possible) { 3046 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 3047 if (lro_possible && mf != NULL) { 3048 if_input(ifp, mf); 3049 DBG_COUNTER_INC(rx_if_input); 3050 mt = mf = NULL; 3051 } 3052 } 3053 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 3054 (CSUM_L4_CALC|CSUM_L4_VALID)) { 3055 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 3056 continue; 3057 } 3058 } 3059 #endif 3060 if (lro_possible) { 3061 if_input(ifp, m); 3062 DBG_COUNTER_INC(rx_if_input); 3063 continue; 3064 } 3065 3066 if (mf == NULL) 3067 mf = m; 3068 if (mt != NULL) 3069 mt->m_nextpkt = m; 3070 mt = m; 3071 } 3072 if (mf != NULL) { 3073 if_input(ifp, mf); 3074 DBG_COUNTER_INC(rx_if_input); 3075 } 3076 3077 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 3078 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 3079 3080 /* 3081 * Flush any outstanding LRO work 3082 */ 3083 #if defined(INET6) || defined(INET) 3084 tcp_lro_flush_all(&rxq->ifr_lc); 3085 #endif 3086 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 3087 retval |= IFLIB_RXEOF_MORE; 3088 return (retval); 3089 err: 3090 STATE_LOCK(ctx); 3091 ctx->ifc_flags |= IFC_DO_RESET; 3092 iflib_admin_intr_deferred(ctx); 3093 STATE_UNLOCK(ctx); 3094 return (0); 3095 } 3096 3097 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 3098 static inline qidx_t 3099 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 3100 { 3101 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3102 qidx_t minthresh = txq->ift_size / 8; 3103 if (in_use > 4*minthresh) 3104 return (notify_count); 3105 if (in_use > 2*minthresh) 3106 return (notify_count >> 1); 3107 if (in_use > minthresh) 3108 return (notify_count >> 3); 3109 return (0); 3110 } 3111 3112 static inline qidx_t 3113 txq_max_rs_deferred(iflib_txq_t txq) 3114 { 3115 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3116 qidx_t minthresh = txq->ift_size / 8; 3117 if (txq->ift_in_use > 4*minthresh) 3118 return (notify_count); 3119 if (txq->ift_in_use > 2*minthresh) 3120 return (notify_count >> 1); 3121 if (txq->ift_in_use > minthresh) 3122 return (notify_count >> 2); 3123 return (2); 3124 } 3125 3126 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 3127 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 3128 3129 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 3130 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 3131 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 3132 3133 /* forward compatibility for cxgb */ 3134 #define FIRST_QSET(ctx) 0 3135 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3136 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3137 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3138 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3139 3140 /* XXX we should be setting this to something other than zero */ 3141 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 3142 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3143 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3144 3145 static inline bool 3146 iflib_txd_db_check(iflib_txq_t txq, int ring) 3147 { 3148 if_ctx_t ctx = txq->ift_ctx; 3149 qidx_t dbval, max; 3150 3151 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use); 3152 3153 /* force || threshold exceeded || at the edge of the ring */ 3154 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2)) { 3155 3156 /* 3157 * 'npending' is used if the card's doorbell is in terms of the number of descriptors 3158 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the 3159 * producer index explicitly (INTC). 3160 */ 3161 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3162 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3163 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3164 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3165 3166 /* 3167 * Absent bugs there are zero packets pending so reset pending counts to zero. 3168 */ 3169 txq->ift_db_pending = txq->ift_npending = 0; 3170 return (true); 3171 } 3172 return (false); 3173 } 3174 3175 #ifdef PKT_DEBUG 3176 static void 3177 print_pkt(if_pkt_info_t pi) 3178 { 3179 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3180 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3181 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3182 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3183 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3184 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3185 } 3186 #endif 3187 3188 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3189 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3190 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3191 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3192 3193 /** 3194 * Parses out ethernet header information in the given mbuf. 3195 * Returns in pi: ipi_etype (EtherType) and ipi_ehdrlen (Ethernet header length) 3196 * 3197 * This will account for the VLAN header if present. 3198 * 3199 * XXX: This doesn't handle QinQ, which could prevent TX offloads for those 3200 * types of packets. 3201 */ 3202 static int 3203 iflib_parse_ether_header(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3204 { 3205 struct ether_vlan_header *eh; 3206 struct mbuf *m; 3207 3208 m = *mp; 3209 if (__predict_false(m->m_len < sizeof(*eh))) { 3210 (*pullups)++; 3211 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3212 return (ENOMEM); 3213 } 3214 eh = mtod(m, struct ether_vlan_header *); 3215 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3216 pi->ipi_etype = ntohs(eh->evl_proto); 3217 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3218 } else { 3219 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3220 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3221 } 3222 *mp = m; 3223 3224 return (0); 3225 } 3226 3227 /** 3228 * Parse up to the L3 header and extract IPv4/IPv6 header information into pi. 3229 * Currently this information includes: IP ToS value, IP header version/presence 3230 * 3231 * This is missing some checks and doesn't edit the packet content as it goes, 3232 * unlike iflib_parse_header(), in order to keep the amount of code here minimal. 3233 */ 3234 static int 3235 iflib_parse_header_partial(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3236 { 3237 struct mbuf *m; 3238 int err; 3239 3240 *pullups = 0; 3241 m = *mp; 3242 if (!M_WRITABLE(m)) { 3243 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3244 return (ENOMEM); 3245 } else { 3246 m_freem(*mp); 3247 DBG_COUNTER_INC(tx_frees); 3248 *mp = m; 3249 } 3250 } 3251 3252 /* Fills out pi->ipi_etype */ 3253 err = iflib_parse_ether_header(pi, mp, pullups); 3254 if (err) 3255 return (err); 3256 m = *mp; 3257 3258 switch (pi->ipi_etype) { 3259 #ifdef INET 3260 case ETHERTYPE_IP: 3261 { 3262 struct mbuf *n; 3263 struct ip *ip = NULL; 3264 int miniplen; 3265 3266 miniplen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip)); 3267 if (__predict_false(m->m_len < miniplen)) { 3268 /* 3269 * Check for common case where the first mbuf only contains 3270 * the Ethernet header 3271 */ 3272 if (m->m_len == pi->ipi_ehdrlen) { 3273 n = m->m_next; 3274 MPASS(n); 3275 /* If next mbuf contains at least the minimal IP header, then stop */ 3276 if (n->m_len >= sizeof(*ip)) { 3277 ip = (struct ip *)n->m_data; 3278 } else { 3279 (*pullups)++; 3280 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3281 return (ENOMEM); 3282 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3283 } 3284 } else { 3285 (*pullups)++; 3286 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3287 return (ENOMEM); 3288 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3289 } 3290 } else { 3291 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3292 } 3293 3294 /* Have the IPv4 header w/ no options here */ 3295 pi->ipi_ip_hlen = ip->ip_hl << 2; 3296 pi->ipi_ipproto = ip->ip_p; 3297 pi->ipi_ip_tos = ip->ip_tos; 3298 pi->ipi_flags |= IPI_TX_IPV4; 3299 3300 break; 3301 } 3302 #endif 3303 #ifdef INET6 3304 case ETHERTYPE_IPV6: 3305 { 3306 struct ip6_hdr *ip6; 3307 3308 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3309 (*pullups)++; 3310 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3311 return (ENOMEM); 3312 } 3313 ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3314 3315 /* Have the IPv6 fixed header here */ 3316 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3317 pi->ipi_ipproto = ip6->ip6_nxt; 3318 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3319 pi->ipi_flags |= IPI_TX_IPV6; 3320 3321 break; 3322 } 3323 #endif 3324 default: 3325 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3326 pi->ipi_ip_hlen = 0; 3327 break; 3328 } 3329 *mp = m; 3330 3331 return (0); 3332 3333 } 3334 3335 static int 3336 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3337 { 3338 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3339 struct mbuf *m; 3340 int err; 3341 3342 m = *mp; 3343 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3344 M_WRITABLE(m) == 0) { 3345 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3346 return (ENOMEM); 3347 } else { 3348 m_freem(*mp); 3349 DBG_COUNTER_INC(tx_frees); 3350 *mp = m; 3351 } 3352 } 3353 3354 /* Fills out pi->ipi_etype */ 3355 err = iflib_parse_ether_header(pi, mp, &txq->ift_pullups); 3356 if (__predict_false(err)) 3357 return (err); 3358 m = *mp; 3359 3360 switch (pi->ipi_etype) { 3361 #ifdef INET 3362 case ETHERTYPE_IP: 3363 { 3364 struct mbuf *n; 3365 struct ip *ip = NULL; 3366 struct tcphdr *th = NULL; 3367 int minthlen; 3368 3369 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3370 if (__predict_false(m->m_len < minthlen)) { 3371 /* 3372 * if this code bloat is causing too much of a hit 3373 * move it to a separate function and mark it noinline 3374 */ 3375 if (m->m_len == pi->ipi_ehdrlen) { 3376 n = m->m_next; 3377 MPASS(n); 3378 if (n->m_len >= sizeof(*ip)) { 3379 ip = (struct ip *)n->m_data; 3380 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3381 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3382 } else { 3383 txq->ift_pullups++; 3384 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3385 return (ENOMEM); 3386 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3387 } 3388 } else { 3389 txq->ift_pullups++; 3390 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3391 return (ENOMEM); 3392 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3393 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3394 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3395 } 3396 } else { 3397 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3398 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3399 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3400 } 3401 pi->ipi_ip_hlen = ip->ip_hl << 2; 3402 pi->ipi_ipproto = ip->ip_p; 3403 pi->ipi_ip_tos = ip->ip_tos; 3404 pi->ipi_flags |= IPI_TX_IPV4; 3405 3406 /* TCP checksum offload may require TCP header length */ 3407 if (IS_TX_OFFLOAD4(pi)) { 3408 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3409 if (__predict_false(th == NULL)) { 3410 txq->ift_pullups++; 3411 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3412 return (ENOMEM); 3413 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3414 } 3415 pi->ipi_tcp_hflags = th->th_flags; 3416 pi->ipi_tcp_hlen = th->th_off << 2; 3417 pi->ipi_tcp_seq = th->th_seq; 3418 } 3419 if (IS_TSO4(pi)) { 3420 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3421 return (ENXIO); 3422 /* 3423 * TSO always requires hardware checksum offload. 3424 */ 3425 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3426 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3427 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3428 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3429 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3430 ip->ip_sum = 0; 3431 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3432 } 3433 } 3434 } 3435 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3436 ip->ip_sum = 0; 3437 3438 break; 3439 } 3440 #endif 3441 #ifdef INET6 3442 case ETHERTYPE_IPV6: 3443 { 3444 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3445 struct tcphdr *th; 3446 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3447 3448 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3449 txq->ift_pullups++; 3450 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3451 return (ENOMEM); 3452 } 3453 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3454 3455 /* XXX-BZ this will go badly in case of ext hdrs. */ 3456 pi->ipi_ipproto = ip6->ip6_nxt; 3457 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3458 pi->ipi_flags |= IPI_TX_IPV6; 3459 3460 /* TCP checksum offload may require TCP header length */ 3461 if (IS_TX_OFFLOAD6(pi)) { 3462 if (pi->ipi_ipproto == IPPROTO_TCP) { 3463 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3464 txq->ift_pullups++; 3465 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3466 return (ENOMEM); 3467 } 3468 pi->ipi_tcp_hflags = th->th_flags; 3469 pi->ipi_tcp_hlen = th->th_off << 2; 3470 pi->ipi_tcp_seq = th->th_seq; 3471 } 3472 if (IS_TSO6(pi)) { 3473 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3474 return (ENXIO); 3475 /* 3476 * TSO always requires hardware checksum offload. 3477 */ 3478 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3479 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3480 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3481 } 3482 } 3483 break; 3484 } 3485 #endif 3486 default: 3487 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3488 pi->ipi_ip_hlen = 0; 3489 break; 3490 } 3491 *mp = m; 3492 3493 return (0); 3494 } 3495 3496 /* 3497 * If dodgy hardware rejects the scatter gather chain we've handed it 3498 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3499 * m_defrag'd mbufs 3500 */ 3501 static __noinline struct mbuf * 3502 iflib_remove_mbuf(iflib_txq_t txq) 3503 { 3504 int ntxd, pidx; 3505 struct mbuf *m, **ifsd_m; 3506 3507 ifsd_m = txq->ift_sds.ifsd_m; 3508 ntxd = txq->ift_size; 3509 pidx = txq->ift_pidx & (ntxd - 1); 3510 ifsd_m = txq->ift_sds.ifsd_m; 3511 m = ifsd_m[pidx]; 3512 ifsd_m[pidx] = NULL; 3513 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3514 if (txq->ift_sds.ifsd_tso_map != NULL) 3515 bus_dmamap_unload(txq->ift_tso_buf_tag, 3516 txq->ift_sds.ifsd_tso_map[pidx]); 3517 #if MEMORY_LOGGING 3518 txq->ift_dequeued++; 3519 #endif 3520 return (m); 3521 } 3522 3523 static inline caddr_t 3524 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3525 { 3526 qidx_t size; 3527 int ntxd; 3528 caddr_t start, end, cur, next; 3529 3530 ntxd = txq->ift_size; 3531 size = txq->ift_txd_size[qid]; 3532 start = txq->ift_ifdi[qid].idi_vaddr; 3533 3534 if (__predict_false(size == 0)) 3535 return (start); 3536 cur = start + size*cidx; 3537 end = start + size*ntxd; 3538 next = CACHE_PTR_NEXT(cur); 3539 return (next < end ? next : start); 3540 } 3541 3542 /* 3543 * Pad an mbuf to ensure a minimum ethernet frame size. 3544 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3545 */ 3546 static __noinline int 3547 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3548 { 3549 /* 3550 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3551 * and ARP message is the smallest common payload I can think of 3552 */ 3553 static char pad[18]; /* just zeros */ 3554 int n; 3555 struct mbuf *new_head; 3556 3557 if (!M_WRITABLE(*m_head)) { 3558 new_head = m_dup(*m_head, M_NOWAIT); 3559 if (new_head == NULL) { 3560 m_freem(*m_head); 3561 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3562 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3563 DBG_COUNTER_INC(tx_frees); 3564 return ENOMEM; 3565 } 3566 m_freem(*m_head); 3567 *m_head = new_head; 3568 } 3569 3570 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3571 n > 0; n -= sizeof(pad)) 3572 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3573 break; 3574 3575 if (n > 0) { 3576 m_freem(*m_head); 3577 device_printf(dev, "cannot pad short frame\n"); 3578 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3579 DBG_COUNTER_INC(tx_frees); 3580 return (ENOBUFS); 3581 } 3582 3583 return 0; 3584 } 3585 3586 static int 3587 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3588 { 3589 if_ctx_t ctx; 3590 if_shared_ctx_t sctx; 3591 if_softc_ctx_t scctx; 3592 bus_dma_tag_t buf_tag; 3593 bus_dma_segment_t *segs; 3594 struct mbuf *m_head, **ifsd_m; 3595 void *next_txd; 3596 bus_dmamap_t map; 3597 struct if_pkt_info pi; 3598 int remap = 0; 3599 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3600 3601 ctx = txq->ift_ctx; 3602 sctx = ctx->ifc_sctx; 3603 scctx = &ctx->ifc_softc_ctx; 3604 segs = txq->ift_segs; 3605 ntxd = txq->ift_size; 3606 m_head = *m_headp; 3607 map = NULL; 3608 3609 /* 3610 * If we're doing TSO the next descriptor to clean may be quite far ahead 3611 */ 3612 cidx = txq->ift_cidx; 3613 pidx = txq->ift_pidx; 3614 if (ctx->ifc_flags & IFC_PREFETCH) { 3615 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3616 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3617 next_txd = calc_next_txd(txq, cidx, 0); 3618 prefetch(next_txd); 3619 } 3620 3621 /* prefetch the next cache line of mbuf pointers and flags */ 3622 prefetch(&txq->ift_sds.ifsd_m[next]); 3623 prefetch(&txq->ift_sds.ifsd_map[next]); 3624 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3625 } 3626 map = txq->ift_sds.ifsd_map[pidx]; 3627 ifsd_m = txq->ift_sds.ifsd_m; 3628 3629 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3630 buf_tag = txq->ift_tso_buf_tag; 3631 max_segs = scctx->isc_tx_tso_segments_max; 3632 map = txq->ift_sds.ifsd_tso_map[pidx]; 3633 MPASS(buf_tag != NULL); 3634 MPASS(max_segs > 0); 3635 } else { 3636 buf_tag = txq->ift_buf_tag; 3637 max_segs = scctx->isc_tx_nsegments; 3638 map = txq->ift_sds.ifsd_map[pidx]; 3639 } 3640 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3641 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3642 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3643 if (err) { 3644 DBG_COUNTER_INC(encap_txd_encap_fail); 3645 return err; 3646 } 3647 } 3648 m_head = *m_headp; 3649 3650 pkt_info_zero(&pi); 3651 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3652 pi.ipi_pidx = pidx; 3653 pi.ipi_qsidx = txq->ift_id; 3654 pi.ipi_len = m_head->m_pkthdr.len; 3655 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3656 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3657 3658 /* deliberate bitwise OR to make one condition */ 3659 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3660 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3661 DBG_COUNTER_INC(encap_txd_encap_fail); 3662 return (err); 3663 } 3664 m_head = *m_headp; 3665 } 3666 3667 retry: 3668 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3669 BUS_DMA_NOWAIT); 3670 defrag: 3671 if (__predict_false(err)) { 3672 switch (err) { 3673 case EFBIG: 3674 /* try collapse once and defrag once */ 3675 if (remap == 0) { 3676 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3677 /* try defrag if collapsing fails */ 3678 if (m_head == NULL) 3679 remap++; 3680 } 3681 if (remap == 1) { 3682 txq->ift_mbuf_defrag++; 3683 m_head = m_defrag(*m_headp, M_NOWAIT); 3684 } 3685 /* 3686 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3687 * failed to map an mbuf that was run through m_defrag 3688 */ 3689 MPASS(remap <= 1); 3690 if (__predict_false(m_head == NULL || remap > 1)) 3691 goto defrag_failed; 3692 remap++; 3693 *m_headp = m_head; 3694 goto retry; 3695 break; 3696 case ENOMEM: 3697 txq->ift_no_tx_dma_setup++; 3698 break; 3699 default: 3700 txq->ift_no_tx_dma_setup++; 3701 m_freem(*m_headp); 3702 DBG_COUNTER_INC(tx_frees); 3703 *m_headp = NULL; 3704 break; 3705 } 3706 txq->ift_map_failed++; 3707 DBG_COUNTER_INC(encap_load_mbuf_fail); 3708 DBG_COUNTER_INC(encap_txd_encap_fail); 3709 return (err); 3710 } 3711 ifsd_m[pidx] = m_head; 3712 /* 3713 * XXX assumes a 1 to 1 relationship between segments and 3714 * descriptors - this does not hold true on all drivers, e.g. 3715 * cxgb 3716 */ 3717 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3718 txq->ift_no_desc_avail++; 3719 bus_dmamap_unload(buf_tag, map); 3720 DBG_COUNTER_INC(encap_txq_avail_fail); 3721 DBG_COUNTER_INC(encap_txd_encap_fail); 3722 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3723 GROUPTASK_ENQUEUE(&txq->ift_task); 3724 return (ENOBUFS); 3725 } 3726 /* 3727 * On Intel cards we can greatly reduce the number of TX interrupts 3728 * we see by only setting report status on every Nth descriptor. 3729 * However, this also means that the driver will need to keep track 3730 * of the descriptors that RS was set on to check them for the DD bit. 3731 */ 3732 txq->ift_rs_pending += nsegs + 1; 3733 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3734 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3735 pi.ipi_flags |= IPI_TX_INTR; 3736 txq->ift_rs_pending = 0; 3737 } 3738 3739 pi.ipi_segs = segs; 3740 pi.ipi_nsegs = nsegs; 3741 3742 MPASS(pidx >= 0 && pidx < txq->ift_size); 3743 #ifdef PKT_DEBUG 3744 print_pkt(&pi); 3745 #endif 3746 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3747 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3748 DBG_COUNTER_INC(tx_encap); 3749 MPASS(pi.ipi_new_pidx < txq->ift_size); 3750 3751 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3752 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3753 ndesc += txq->ift_size; 3754 txq->ift_gen = 1; 3755 } 3756 /* 3757 * drivers can need as many as 3758 * two sentinels 3759 */ 3760 MPASS(ndesc <= pi.ipi_nsegs + 2); 3761 MPASS(pi.ipi_new_pidx != pidx); 3762 MPASS(ndesc > 0); 3763 txq->ift_in_use += ndesc; 3764 txq->ift_db_pending += ndesc; 3765 3766 /* 3767 * We update the last software descriptor again here because there may 3768 * be a sentinel and/or there may be more mbufs than segments 3769 */ 3770 txq->ift_pidx = pi.ipi_new_pidx; 3771 txq->ift_npending += pi.ipi_ndescs; 3772 } else { 3773 *m_headp = m_head = iflib_remove_mbuf(txq); 3774 if (err == EFBIG) { 3775 txq->ift_txd_encap_efbig++; 3776 if (remap < 2) { 3777 remap = 1; 3778 goto defrag; 3779 } 3780 } 3781 goto defrag_failed; 3782 } 3783 /* 3784 * err can't possibly be non-zero here, so we don't neet to test it 3785 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3786 */ 3787 return (err); 3788 3789 defrag_failed: 3790 txq->ift_mbuf_defrag_failed++; 3791 txq->ift_map_failed++; 3792 m_freem(*m_headp); 3793 DBG_COUNTER_INC(tx_frees); 3794 *m_headp = NULL; 3795 DBG_COUNTER_INC(encap_txd_encap_fail); 3796 return (ENOMEM); 3797 } 3798 3799 static void 3800 iflib_tx_desc_free(iflib_txq_t txq, int n) 3801 { 3802 uint32_t qsize, cidx, mask, gen; 3803 struct mbuf *m, **ifsd_m; 3804 bool do_prefetch; 3805 3806 cidx = txq->ift_cidx; 3807 gen = txq->ift_gen; 3808 qsize = txq->ift_size; 3809 mask = qsize-1; 3810 ifsd_m = txq->ift_sds.ifsd_m; 3811 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3812 3813 while (n-- > 0) { 3814 if (do_prefetch) { 3815 prefetch(ifsd_m[(cidx + 3) & mask]); 3816 prefetch(ifsd_m[(cidx + 4) & mask]); 3817 } 3818 if ((m = ifsd_m[cidx]) != NULL) { 3819 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3820 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3821 bus_dmamap_sync(txq->ift_tso_buf_tag, 3822 txq->ift_sds.ifsd_tso_map[cidx], 3823 BUS_DMASYNC_POSTWRITE); 3824 bus_dmamap_unload(txq->ift_tso_buf_tag, 3825 txq->ift_sds.ifsd_tso_map[cidx]); 3826 } else { 3827 bus_dmamap_sync(txq->ift_buf_tag, 3828 txq->ift_sds.ifsd_map[cidx], 3829 BUS_DMASYNC_POSTWRITE); 3830 bus_dmamap_unload(txq->ift_buf_tag, 3831 txq->ift_sds.ifsd_map[cidx]); 3832 } 3833 /* XXX we don't support any drivers that batch packets yet */ 3834 MPASS(m->m_nextpkt == NULL); 3835 m_freem(m); 3836 ifsd_m[cidx] = NULL; 3837 #if MEMORY_LOGGING 3838 txq->ift_dequeued++; 3839 #endif 3840 DBG_COUNTER_INC(tx_frees); 3841 } 3842 if (__predict_false(++cidx == qsize)) { 3843 cidx = 0; 3844 gen = 0; 3845 } 3846 } 3847 txq->ift_cidx = cidx; 3848 txq->ift_gen = gen; 3849 } 3850 3851 static __inline int 3852 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3853 { 3854 int reclaim; 3855 if_ctx_t ctx = txq->ift_ctx; 3856 3857 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3858 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3859 3860 /* 3861 * Need a rate-limiting check so that this isn't called every time 3862 */ 3863 iflib_tx_credits_update(ctx, txq); 3864 reclaim = DESC_RECLAIMABLE(txq); 3865 3866 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3867 #ifdef INVARIANTS 3868 if (iflib_verbose_debug) { 3869 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3870 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3871 reclaim, thresh); 3872 } 3873 #endif 3874 return (0); 3875 } 3876 iflib_tx_desc_free(txq, reclaim); 3877 txq->ift_cleaned += reclaim; 3878 txq->ift_in_use -= reclaim; 3879 3880 return (reclaim); 3881 } 3882 3883 static struct mbuf ** 3884 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3885 { 3886 int next, size; 3887 struct mbuf **items; 3888 3889 size = r->size; 3890 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3891 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3892 3893 prefetch(items[(cidx + offset) & (size-1)]); 3894 if (remaining > 1) { 3895 prefetch2cachelines(&items[next]); 3896 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3897 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3898 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3899 } 3900 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3901 } 3902 3903 static void 3904 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3905 { 3906 3907 ifmp_ring_check_drainage(txq->ift_br, budget); 3908 } 3909 3910 static uint32_t 3911 iflib_txq_can_drain(struct ifmp_ring *r) 3912 { 3913 iflib_txq_t txq = r->cookie; 3914 if_ctx_t ctx = txq->ift_ctx; 3915 3916 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3917 return (1); 3918 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3919 BUS_DMASYNC_POSTREAD); 3920 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3921 false)); 3922 } 3923 3924 static uint32_t 3925 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3926 { 3927 iflib_txq_t txq = r->cookie; 3928 if_ctx_t ctx = txq->ift_ctx; 3929 if_t ifp = ctx->ifc_ifp; 3930 struct mbuf *m, **mp; 3931 int avail, bytes_sent, skipped, count, err, i; 3932 int mcast_sent, pkt_sent, reclaimed; 3933 bool do_prefetch, rang, ring; 3934 3935 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3936 !LINK_ACTIVE(ctx))) { 3937 DBG_COUNTER_INC(txq_drain_notready); 3938 return (0); 3939 } 3940 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3941 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending); 3942 avail = IDXDIFF(pidx, cidx, r->size); 3943 3944 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3945 /* 3946 * The driver is unloading so we need to free all pending packets. 3947 */ 3948 DBG_COUNTER_INC(txq_drain_flushing); 3949 for (i = 0; i < avail; i++) { 3950 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3951 m_freem(r->items[(cidx + i) & (r->size-1)]); 3952 r->items[(cidx + i) & (r->size-1)] = NULL; 3953 } 3954 return (avail); 3955 } 3956 3957 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3958 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3959 CALLOUT_LOCK(txq); 3960 callout_stop(&txq->ift_timer); 3961 CALLOUT_UNLOCK(txq); 3962 DBG_COUNTER_INC(txq_drain_oactive); 3963 return (0); 3964 } 3965 3966 /* 3967 * If we've reclaimed any packets this queue cannot be hung. 3968 */ 3969 if (reclaimed) 3970 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3971 skipped = mcast_sent = bytes_sent = pkt_sent = 0; 3972 count = MIN(avail, TX_BATCH_SIZE); 3973 #ifdef INVARIANTS 3974 if (iflib_verbose_debug) 3975 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3976 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3977 #endif 3978 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3979 err = 0; 3980 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx) + 2; i++) { 3981 int rem = do_prefetch ? count - i : 0; 3982 3983 mp = _ring_peek_one(r, cidx, i, rem); 3984 MPASS(mp != NULL && *mp != NULL); 3985 3986 /* 3987 * Completion interrupts will use the address of the txq 3988 * as a sentinel to enqueue _something_ in order to acquire 3989 * the lock on the mp_ring (there's no direct lock call). 3990 * We obviously whave to check for these sentinel cases 3991 * and skip them. 3992 */ 3993 if (__predict_false(*mp == (struct mbuf *)txq)) { 3994 skipped++; 3995 continue; 3996 } 3997 err = iflib_encap(txq, mp); 3998 if (__predict_false(err)) { 3999 /* no room - bail out */ 4000 if (err == ENOBUFS) 4001 break; 4002 skipped++; 4003 /* we can't send this packet - skip it */ 4004 continue; 4005 } 4006 pkt_sent++; 4007 m = *mp; 4008 DBG_COUNTER_INC(tx_sent); 4009 bytes_sent += m->m_pkthdr.len; 4010 mcast_sent += !!(m->m_flags & M_MCAST); 4011 4012 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))) 4013 break; 4014 ETHER_BPF_MTAP(ifp, m); 4015 rang = iflib_txd_db_check(txq, false); 4016 } 4017 4018 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 4019 ring = rang ? false : (iflib_min_tx_latency | err); 4020 iflib_txd_db_check(txq, ring); 4021 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 4022 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 4023 if (mcast_sent) 4024 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 4025 #ifdef INVARIANTS 4026 if (iflib_verbose_debug) 4027 printf("consumed=%d\n", skipped + pkt_sent); 4028 #endif 4029 return (skipped + pkt_sent); 4030 } 4031 4032 static uint32_t 4033 iflib_txq_drain_always(struct ifmp_ring *r) 4034 { 4035 return (1); 4036 } 4037 4038 static uint32_t 4039 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 4040 { 4041 int i, avail; 4042 struct mbuf **mp; 4043 iflib_txq_t txq; 4044 4045 txq = r->cookie; 4046 4047 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 4048 CALLOUT_LOCK(txq); 4049 callout_stop(&txq->ift_timer); 4050 CALLOUT_UNLOCK(txq); 4051 4052 avail = IDXDIFF(pidx, cidx, r->size); 4053 for (i = 0; i < avail; i++) { 4054 mp = _ring_peek_one(r, cidx, i, avail - i); 4055 if (__predict_false(*mp == (struct mbuf *)txq)) 4056 continue; 4057 m_freem(*mp); 4058 DBG_COUNTER_INC(tx_frees); 4059 } 4060 MPASS(ifmp_ring_is_stalled(r) == 0); 4061 return (avail); 4062 } 4063 4064 static void 4065 iflib_ifmp_purge(iflib_txq_t txq) 4066 { 4067 struct ifmp_ring *r; 4068 4069 r = txq->ift_br; 4070 r->drain = iflib_txq_drain_free; 4071 r->can_drain = iflib_txq_drain_always; 4072 4073 ifmp_ring_check_drainage(r, r->size); 4074 4075 r->drain = iflib_txq_drain; 4076 r->can_drain = iflib_txq_can_drain; 4077 } 4078 4079 static void 4080 _task_fn_tx(void *context) 4081 { 4082 iflib_txq_t txq = context; 4083 if_ctx_t ctx = txq->ift_ctx; 4084 if_t ifp = ctx->ifc_ifp; 4085 int abdicate = ctx->ifc_sysctl_tx_abdicate; 4086 4087 #ifdef IFLIB_DIAGNOSTICS 4088 txq->ift_cpu_exec_count[curcpu]++; 4089 #endif 4090 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4091 return; 4092 #ifdef DEV_NETMAP 4093 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 4094 netmap_tx_irq(ifp, txq->ift_id)) 4095 goto skip_ifmp; 4096 #endif 4097 #ifdef ALTQ 4098 if (if_altq_is_enabled(ifp)) 4099 iflib_altq_if_start(ifp); 4100 #endif 4101 if (txq->ift_db_pending) 4102 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 4103 else if (!abdicate) 4104 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4105 /* 4106 * When abdicating, we always need to check drainage, not just when we don't enqueue 4107 */ 4108 if (abdicate) 4109 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4110 #ifdef DEV_NETMAP 4111 skip_ifmp: 4112 #endif 4113 if (ctx->ifc_flags & IFC_LEGACY) 4114 IFDI_INTR_ENABLE(ctx); 4115 else 4116 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 4117 } 4118 4119 static void 4120 _task_fn_rx(void *context) 4121 { 4122 iflib_rxq_t rxq = context; 4123 if_ctx_t ctx = rxq->ifr_ctx; 4124 uint8_t more; 4125 uint16_t budget; 4126 #ifdef DEV_NETMAP 4127 u_int work = 0; 4128 int nmirq; 4129 #endif 4130 4131 #ifdef IFLIB_DIAGNOSTICS 4132 rxq->ifr_cpu_exec_count[curcpu]++; 4133 #endif 4134 DBG_COUNTER_INC(task_fn_rxs); 4135 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4136 return; 4137 #ifdef DEV_NETMAP 4138 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 4139 if (nmirq != NM_IRQ_PASS) { 4140 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 4141 goto skip_rxeof; 4142 } 4143 #endif 4144 budget = ctx->ifc_sysctl_rx_budget; 4145 if (budget == 0) 4146 budget = 16; /* XXX */ 4147 more = iflib_rxeof(rxq, budget); 4148 #ifdef DEV_NETMAP 4149 skip_rxeof: 4150 #endif 4151 if ((more & IFLIB_RXEOF_MORE) == 0) { 4152 if (ctx->ifc_flags & IFC_LEGACY) 4153 IFDI_INTR_ENABLE(ctx); 4154 else 4155 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 4156 DBG_COUNTER_INC(rx_intr_enables); 4157 } 4158 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4159 return; 4160 4161 if (more & IFLIB_RXEOF_MORE) 4162 GROUPTASK_ENQUEUE(&rxq->ifr_task); 4163 else if (more & IFLIB_RXEOF_EMPTY) 4164 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 4165 } 4166 4167 static void 4168 _task_fn_admin(void *context) 4169 { 4170 if_ctx_t ctx = context; 4171 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 4172 iflib_txq_t txq; 4173 int i; 4174 bool oactive, running, do_reset, do_watchdog, in_detach; 4175 4176 STATE_LOCK(ctx); 4177 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 4178 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 4179 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 4180 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 4181 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 4182 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 4183 STATE_UNLOCK(ctx); 4184 4185 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4186 return; 4187 if (in_detach) 4188 return; 4189 4190 CTX_LOCK(ctx); 4191 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4192 CALLOUT_LOCK(txq); 4193 callout_stop(&txq->ift_timer); 4194 CALLOUT_UNLOCK(txq); 4195 } 4196 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ) 4197 IFDI_ADMIN_COMPLETION_HANDLE(ctx); 4198 if (do_watchdog) { 4199 ctx->ifc_watchdog_events++; 4200 IFDI_WATCHDOG_RESET(ctx); 4201 } 4202 IFDI_UPDATE_ADMIN_STATUS(ctx); 4203 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4204 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 4205 txq->ift_timer.c_cpu); 4206 } 4207 IFDI_LINK_INTR_ENABLE(ctx); 4208 if (do_reset) 4209 iflib_if_init_locked(ctx); 4210 CTX_UNLOCK(ctx); 4211 4212 if (LINK_ACTIVE(ctx) == 0) 4213 return; 4214 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 4215 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4216 } 4217 4218 static void 4219 _task_fn_iov(void *context) 4220 { 4221 if_ctx_t ctx = context; 4222 4223 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 4224 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4225 return; 4226 4227 CTX_LOCK(ctx); 4228 IFDI_VFLR_HANDLE(ctx); 4229 CTX_UNLOCK(ctx); 4230 } 4231 4232 static int 4233 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4234 { 4235 int err; 4236 if_int_delay_info_t info; 4237 if_ctx_t ctx; 4238 4239 info = (if_int_delay_info_t)arg1; 4240 ctx = info->iidi_ctx; 4241 info->iidi_req = req; 4242 info->iidi_oidp = oidp; 4243 CTX_LOCK(ctx); 4244 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 4245 CTX_UNLOCK(ctx); 4246 return (err); 4247 } 4248 4249 /********************************************************************* 4250 * 4251 * IFNET FUNCTIONS 4252 * 4253 **********************************************************************/ 4254 4255 static void 4256 iflib_if_init_locked(if_ctx_t ctx) 4257 { 4258 iflib_stop(ctx); 4259 iflib_init_locked(ctx); 4260 } 4261 4262 static void 4263 iflib_if_init(void *arg) 4264 { 4265 if_ctx_t ctx = arg; 4266 4267 CTX_LOCK(ctx); 4268 iflib_if_init_locked(ctx); 4269 CTX_UNLOCK(ctx); 4270 } 4271 4272 static int 4273 iflib_if_transmit(if_t ifp, struct mbuf *m) 4274 { 4275 if_ctx_t ctx = if_getsoftc(ifp); 4276 iflib_txq_t txq; 4277 int err, qidx; 4278 int abdicate; 4279 4280 if (__predict_false((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 4281 DBG_COUNTER_INC(tx_frees); 4282 m_freem(m); 4283 return (ENETDOWN); 4284 } 4285 4286 MPASS(m->m_nextpkt == NULL); 4287 /* ALTQ-enabled interfaces always use queue 0. */ 4288 qidx = 0; 4289 /* Use driver-supplied queue selection method if it exists */ 4290 if (ctx->isc_txq_select_v2) { 4291 struct if_pkt_info pi; 4292 uint64_t early_pullups = 0; 4293 pkt_info_zero(&pi); 4294 4295 err = iflib_parse_header_partial(&pi, &m, &early_pullups); 4296 if (__predict_false(err != 0)) { 4297 /* Assign pullups for bad pkts to default queue */ 4298 ctx->ifc_txqs[0].ift_pullups += early_pullups; 4299 DBG_COUNTER_INC(encap_txd_encap_fail); 4300 return (err); 4301 } 4302 /* Let driver make queueing decision */ 4303 qidx = ctx->isc_txq_select_v2(ctx->ifc_softc, m, &pi); 4304 ctx->ifc_txqs[qidx].ift_pullups += early_pullups; 4305 } 4306 /* Backwards compatibility w/ simpler queue select */ 4307 else if (ctx->isc_txq_select) 4308 qidx = ctx->isc_txq_select(ctx->ifc_softc, m); 4309 /* If not, use iflib's standard method */ 4310 else if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !if_altq_is_enabled(ifp)) 4311 qidx = QIDX(ctx, m); 4312 4313 /* Set TX queue */ 4314 txq = &ctx->ifc_txqs[qidx]; 4315 4316 #ifdef DRIVER_BACKPRESSURE 4317 if (txq->ift_closed) { 4318 while (m != NULL) { 4319 next = m->m_nextpkt; 4320 m->m_nextpkt = NULL; 4321 m_freem(m); 4322 DBG_COUNTER_INC(tx_frees); 4323 m = next; 4324 } 4325 return (ENOBUFS); 4326 } 4327 #endif 4328 #ifdef notyet 4329 qidx = count = 0; 4330 mp = marr; 4331 next = m; 4332 do { 4333 count++; 4334 next = next->m_nextpkt; 4335 } while (next != NULL); 4336 4337 if (count > nitems(marr)) 4338 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4339 /* XXX check nextpkt */ 4340 m_freem(m); 4341 /* XXX simplify for now */ 4342 DBG_COUNTER_INC(tx_frees); 4343 return (ENOBUFS); 4344 } 4345 for (next = m, i = 0; next != NULL; i++) { 4346 mp[i] = next; 4347 next = next->m_nextpkt; 4348 mp[i]->m_nextpkt = NULL; 4349 } 4350 #endif 4351 DBG_COUNTER_INC(tx_seen); 4352 abdicate = ctx->ifc_sysctl_tx_abdicate; 4353 4354 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4355 4356 if (abdicate) 4357 GROUPTASK_ENQUEUE(&txq->ift_task); 4358 if (err) { 4359 if (!abdicate) 4360 GROUPTASK_ENQUEUE(&txq->ift_task); 4361 /* support forthcoming later */ 4362 #ifdef DRIVER_BACKPRESSURE 4363 txq->ift_closed = TRUE; 4364 #endif 4365 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4366 m_freem(m); 4367 DBG_COUNTER_INC(tx_frees); 4368 } 4369 4370 return (err); 4371 } 4372 4373 #ifdef ALTQ 4374 /* 4375 * The overall approach to integrating iflib with ALTQ is to continue to use 4376 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4377 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4378 * is redundant/unnecessary, but doing so minimizes the amount of 4379 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4380 * redundantly queueing to an intermediate mp_ring is swamped by the 4381 * performance limitations inherent in using ALTQ. 4382 * 4383 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4384 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4385 * given interface. If ALTQ is enabled for an interface, then all 4386 * transmitted packets for that interface will be submitted to the ALTQ 4387 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4388 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4389 * update stats that the iflib machinery handles, and which is sensitve to 4390 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4391 * will be installed as the start routine for use by ALTQ facilities that 4392 * need to trigger queue drains on a scheduled basis. 4393 * 4394 */ 4395 static void 4396 iflib_altq_if_start(if_t ifp) 4397 { 4398 struct ifaltq *ifq = &ifp->if_snd; /* XXX - DRVAPI */ 4399 struct mbuf *m; 4400 4401 IFQ_LOCK(ifq); 4402 IFQ_DEQUEUE_NOLOCK(ifq, m); 4403 while (m != NULL) { 4404 iflib_if_transmit(ifp, m); 4405 IFQ_DEQUEUE_NOLOCK(ifq, m); 4406 } 4407 IFQ_UNLOCK(ifq); 4408 } 4409 4410 static int 4411 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4412 { 4413 int err; 4414 4415 if (if_altq_is_enabled(ifp)) { 4416 IFQ_ENQUEUE(&ifp->if_snd, m, err); /* XXX - DRVAPI */ 4417 if (err == 0) 4418 iflib_altq_if_start(ifp); 4419 } else 4420 err = iflib_if_transmit(ifp, m); 4421 4422 return (err); 4423 } 4424 #endif /* ALTQ */ 4425 4426 static void 4427 iflib_if_qflush(if_t ifp) 4428 { 4429 if_ctx_t ctx = if_getsoftc(ifp); 4430 iflib_txq_t txq = ctx->ifc_txqs; 4431 int i; 4432 4433 STATE_LOCK(ctx); 4434 ctx->ifc_flags |= IFC_QFLUSH; 4435 STATE_UNLOCK(ctx); 4436 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4437 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4438 iflib_txq_check_drain(txq, 0); 4439 STATE_LOCK(ctx); 4440 ctx->ifc_flags &= ~IFC_QFLUSH; 4441 STATE_UNLOCK(ctx); 4442 4443 /* 4444 * When ALTQ is enabled, this will also take care of purging the 4445 * ALTQ queue(s). 4446 */ 4447 if_qflush(ifp); 4448 } 4449 4450 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4451 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4452 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4453 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG) 4454 4455 static int 4456 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4457 { 4458 if_ctx_t ctx = if_getsoftc(ifp); 4459 struct ifreq *ifr = (struct ifreq *)data; 4460 #if defined(INET) || defined(INET6) 4461 struct ifaddr *ifa = (struct ifaddr *)data; 4462 #endif 4463 bool avoid_reset = false; 4464 int err = 0, reinit = 0, bits; 4465 4466 switch (command) { 4467 case SIOCSIFADDR: 4468 #ifdef INET 4469 if (ifa->ifa_addr->sa_family == AF_INET) 4470 avoid_reset = true; 4471 #endif 4472 #ifdef INET6 4473 if (ifa->ifa_addr->sa_family == AF_INET6) 4474 avoid_reset = true; 4475 #endif 4476 /* 4477 ** Calling init results in link renegotiation, 4478 ** so we avoid doing it when possible. 4479 */ 4480 if (avoid_reset) { 4481 if_setflagbits(ifp, IFF_UP,0); 4482 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4483 reinit = 1; 4484 #ifdef INET 4485 if (!(if_getflags(ifp) & IFF_NOARP)) 4486 arp_ifinit(ifp, ifa); 4487 #endif 4488 } else 4489 err = ether_ioctl(ifp, command, data); 4490 break; 4491 case SIOCSIFMTU: 4492 CTX_LOCK(ctx); 4493 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4494 CTX_UNLOCK(ctx); 4495 break; 4496 } 4497 bits = if_getdrvflags(ifp); 4498 /* stop the driver and free any clusters before proceeding */ 4499 iflib_stop(ctx); 4500 4501 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4502 STATE_LOCK(ctx); 4503 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4504 ctx->ifc_flags |= IFC_MULTISEG; 4505 else 4506 ctx->ifc_flags &= ~IFC_MULTISEG; 4507 STATE_UNLOCK(ctx); 4508 err = if_setmtu(ifp, ifr->ifr_mtu); 4509 } 4510 iflib_init_locked(ctx); 4511 STATE_LOCK(ctx); 4512 if_setdrvflags(ifp, bits); 4513 STATE_UNLOCK(ctx); 4514 CTX_UNLOCK(ctx); 4515 break; 4516 case SIOCSIFFLAGS: 4517 CTX_LOCK(ctx); 4518 if (if_getflags(ifp) & IFF_UP) { 4519 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4520 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4521 (IFF_PROMISC | IFF_ALLMULTI)) { 4522 CTX_UNLOCK(ctx); 4523 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4524 CTX_LOCK(ctx); 4525 } 4526 } else 4527 reinit = 1; 4528 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4529 iflib_stop(ctx); 4530 } 4531 ctx->ifc_if_flags = if_getflags(ifp); 4532 CTX_UNLOCK(ctx); 4533 break; 4534 case SIOCADDMULTI: 4535 case SIOCDELMULTI: 4536 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4537 CTX_LOCK(ctx); 4538 IFDI_INTR_DISABLE(ctx); 4539 IFDI_MULTI_SET(ctx); 4540 IFDI_INTR_ENABLE(ctx); 4541 CTX_UNLOCK(ctx); 4542 } 4543 break; 4544 case SIOCSIFMEDIA: 4545 CTX_LOCK(ctx); 4546 IFDI_MEDIA_SET(ctx); 4547 CTX_UNLOCK(ctx); 4548 /* FALLTHROUGH */ 4549 case SIOCGIFMEDIA: 4550 case SIOCGIFXMEDIA: 4551 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4552 break; 4553 case SIOCGI2C: 4554 { 4555 struct ifi2creq i2c; 4556 4557 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4558 if (err != 0) 4559 break; 4560 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4561 err = EINVAL; 4562 break; 4563 } 4564 if (i2c.len > sizeof(i2c.data)) { 4565 err = EINVAL; 4566 break; 4567 } 4568 4569 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4570 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4571 sizeof(i2c)); 4572 break; 4573 } 4574 case SIOCSIFCAP: 4575 { 4576 int mask, setmask, oldmask; 4577 4578 oldmask = if_getcapenable(ifp); 4579 mask = ifr->ifr_reqcap ^ oldmask; 4580 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG; 4581 setmask = 0; 4582 #ifdef TCP_OFFLOAD 4583 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4584 #endif 4585 setmask |= (mask & IFCAP_FLAGS); 4586 setmask |= (mask & IFCAP_WOL); 4587 4588 /* 4589 * If any RX csum has changed, change all the ones that 4590 * are supported by the driver. 4591 */ 4592 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4593 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4594 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4595 } 4596 4597 /* 4598 * want to ensure that traffic has stopped before we change any of the flags 4599 */ 4600 if (setmask) { 4601 CTX_LOCK(ctx); 4602 bits = if_getdrvflags(ifp); 4603 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4604 iflib_stop(ctx); 4605 STATE_LOCK(ctx); 4606 if_togglecapenable(ifp, setmask); 4607 ctx->ifc_softc_ctx.isc_capenable ^= setmask; 4608 STATE_UNLOCK(ctx); 4609 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4610 iflib_init_locked(ctx); 4611 STATE_LOCK(ctx); 4612 if_setdrvflags(ifp, bits); 4613 STATE_UNLOCK(ctx); 4614 CTX_UNLOCK(ctx); 4615 } 4616 if_vlancap(ifp); 4617 break; 4618 } 4619 case SIOCGPRIVATE_0: 4620 case SIOCSDRVSPEC: 4621 case SIOCGDRVSPEC: 4622 CTX_LOCK(ctx); 4623 err = IFDI_PRIV_IOCTL(ctx, command, data); 4624 CTX_UNLOCK(ctx); 4625 break; 4626 default: 4627 err = ether_ioctl(ifp, command, data); 4628 break; 4629 } 4630 if (reinit) 4631 iflib_if_init(ctx); 4632 return (err); 4633 } 4634 4635 static uint64_t 4636 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4637 { 4638 if_ctx_t ctx = if_getsoftc(ifp); 4639 4640 return (IFDI_GET_COUNTER(ctx, cnt)); 4641 } 4642 4643 /********************************************************************* 4644 * 4645 * OTHER FUNCTIONS EXPORTED TO THE STACK 4646 * 4647 **********************************************************************/ 4648 4649 static void 4650 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4651 { 4652 if_ctx_t ctx = if_getsoftc(ifp); 4653 4654 if ((void *)ctx != arg) 4655 return; 4656 4657 if ((vtag == 0) || (vtag > 4095)) 4658 return; 4659 4660 if (iflib_in_detach(ctx)) 4661 return; 4662 4663 CTX_LOCK(ctx); 4664 /* Driver may need all untagged packets to be flushed */ 4665 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4666 iflib_stop(ctx); 4667 IFDI_VLAN_REGISTER(ctx, vtag); 4668 /* Re-init to load the changes, if required */ 4669 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4670 iflib_init_locked(ctx); 4671 CTX_UNLOCK(ctx); 4672 } 4673 4674 static void 4675 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4676 { 4677 if_ctx_t ctx = if_getsoftc(ifp); 4678 4679 if ((void *)ctx != arg) 4680 return; 4681 4682 if ((vtag == 0) || (vtag > 4095)) 4683 return; 4684 4685 CTX_LOCK(ctx); 4686 /* Driver may need all tagged packets to be flushed */ 4687 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4688 iflib_stop(ctx); 4689 IFDI_VLAN_UNREGISTER(ctx, vtag); 4690 /* Re-init to load the changes, if required */ 4691 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4692 iflib_init_locked(ctx); 4693 CTX_UNLOCK(ctx); 4694 } 4695 4696 static void 4697 iflib_led_func(void *arg, int onoff) 4698 { 4699 if_ctx_t ctx = arg; 4700 4701 CTX_LOCK(ctx); 4702 IFDI_LED_FUNC(ctx, onoff); 4703 CTX_UNLOCK(ctx); 4704 } 4705 4706 /********************************************************************* 4707 * 4708 * BUS FUNCTION DEFINITIONS 4709 * 4710 **********************************************************************/ 4711 4712 int 4713 iflib_device_probe(device_t dev) 4714 { 4715 const pci_vendor_info_t *ent; 4716 if_shared_ctx_t sctx; 4717 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4718 uint16_t pci_vendor_id; 4719 4720 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4721 return (ENOTSUP); 4722 4723 pci_vendor_id = pci_get_vendor(dev); 4724 pci_device_id = pci_get_device(dev); 4725 pci_subvendor_id = pci_get_subvendor(dev); 4726 pci_subdevice_id = pci_get_subdevice(dev); 4727 pci_rev_id = pci_get_revid(dev); 4728 if (sctx->isc_parse_devinfo != NULL) 4729 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4730 4731 ent = sctx->isc_vendor_info; 4732 while (ent->pvi_vendor_id != 0) { 4733 if (pci_vendor_id != ent->pvi_vendor_id) { 4734 ent++; 4735 continue; 4736 } 4737 if ((pci_device_id == ent->pvi_device_id) && 4738 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4739 (ent->pvi_subvendor_id == 0)) && 4740 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4741 (ent->pvi_subdevice_id == 0)) && 4742 ((pci_rev_id == ent->pvi_rev_id) || 4743 (ent->pvi_rev_id == 0))) { 4744 device_set_desc_copy(dev, ent->pvi_name); 4745 /* this needs to be changed to zero if the bus probing code 4746 * ever stops re-probing on best match because the sctx 4747 * may have its values over written by register calls 4748 * in subsequent probes 4749 */ 4750 return (BUS_PROBE_DEFAULT); 4751 } 4752 ent++; 4753 } 4754 return (ENXIO); 4755 } 4756 4757 int 4758 iflib_device_probe_vendor(device_t dev) 4759 { 4760 int probe; 4761 4762 probe = iflib_device_probe(dev); 4763 if (probe == BUS_PROBE_DEFAULT) 4764 return (BUS_PROBE_VENDOR); 4765 else 4766 return (probe); 4767 } 4768 4769 static void 4770 iflib_reset_qvalues(if_ctx_t ctx) 4771 { 4772 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4773 if_shared_ctx_t sctx = ctx->ifc_sctx; 4774 device_t dev = ctx->ifc_dev; 4775 int i; 4776 4777 if (ctx->ifc_sysctl_ntxqs != 0) 4778 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4779 if (ctx->ifc_sysctl_nrxqs != 0) 4780 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4781 4782 for (i = 0; i < sctx->isc_ntxqs; i++) { 4783 if (ctx->ifc_sysctl_ntxds[i] != 0) 4784 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4785 else 4786 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4787 } 4788 4789 for (i = 0; i < sctx->isc_nrxqs; i++) { 4790 if (ctx->ifc_sysctl_nrxds[i] != 0) 4791 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4792 else 4793 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4794 } 4795 4796 for (i = 0; i < sctx->isc_nrxqs; i++) { 4797 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4798 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4799 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4800 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4801 } 4802 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4803 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4804 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4805 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4806 } 4807 if (!powerof2(scctx->isc_nrxd[i])) { 4808 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4809 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4810 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4811 } 4812 } 4813 4814 for (i = 0; i < sctx->isc_ntxqs; i++) { 4815 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4816 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4817 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4818 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4819 } 4820 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4821 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4822 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4823 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4824 } 4825 if (!powerof2(scctx->isc_ntxd[i])) { 4826 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4827 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4828 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4829 } 4830 } 4831 } 4832 4833 static void 4834 iflib_add_pfil(if_ctx_t ctx) 4835 { 4836 struct pfil_head *pfil; 4837 struct pfil_head_args pa; 4838 iflib_rxq_t rxq; 4839 int i; 4840 4841 pa.pa_version = PFIL_VERSION; 4842 pa.pa_flags = PFIL_IN; 4843 pa.pa_type = PFIL_TYPE_ETHERNET; 4844 pa.pa_headname = if_name(ctx->ifc_ifp); 4845 pfil = pfil_head_register(&pa); 4846 4847 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4848 rxq->pfil = pfil; 4849 } 4850 } 4851 4852 static void 4853 iflib_rem_pfil(if_ctx_t ctx) 4854 { 4855 struct pfil_head *pfil; 4856 iflib_rxq_t rxq; 4857 int i; 4858 4859 rxq = ctx->ifc_rxqs; 4860 pfil = rxq->pfil; 4861 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4862 rxq->pfil = NULL; 4863 } 4864 pfil_head_unregister(pfil); 4865 } 4866 4867 4868 /* 4869 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from 4870 * cpuid and wrapping as necessary. 4871 */ 4872 static unsigned int 4873 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n) 4874 { 4875 unsigned int first_valid; 4876 unsigned int last_valid; 4877 4878 /* cpuid should always be in the valid set */ 4879 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4880 4881 /* valid set should never be empty */ 4882 MPASS(!CPU_EMPTY(&ctx->ifc_cpus)); 4883 4884 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4885 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4886 n = n % CPU_COUNT(&ctx->ifc_cpus); 4887 while (n > 0) { 4888 do { 4889 cpuid++; 4890 if (cpuid > last_valid) 4891 cpuid = first_valid; 4892 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4893 n--; 4894 } 4895 4896 return (cpuid); 4897 } 4898 4899 #if defined(SMP) && defined(SCHED_ULE) 4900 extern struct cpu_group *cpu_top; /* CPU topology */ 4901 4902 static int 4903 find_child_with_core(int cpu, struct cpu_group *grp) 4904 { 4905 int i; 4906 4907 if (grp->cg_children == 0) 4908 return -1; 4909 4910 MPASS(grp->cg_child); 4911 for (i = 0; i < grp->cg_children; i++) { 4912 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 4913 return i; 4914 } 4915 4916 return -1; 4917 } 4918 4919 4920 /* 4921 * Find an L2 neighbor of the given CPU or return -1 if none found. This 4922 * does not distinguish among multiple L2 neighbors if the given CPU has 4923 * more than one (it will always return the same result in that case). 4924 */ 4925 static int 4926 find_l2_neighbor(int cpu) 4927 { 4928 struct cpu_group *grp; 4929 int i; 4930 4931 grp = cpu_top; 4932 if (grp == NULL) 4933 return -1; 4934 4935 /* 4936 * Find the smallest CPU group that contains the given core. 4937 */ 4938 i = 0; 4939 while ((i = find_child_with_core(cpu, grp)) != -1) { 4940 /* 4941 * If the smallest group containing the given CPU has less 4942 * than two members, we conclude the given CPU has no 4943 * L2 neighbor. 4944 */ 4945 if (grp->cg_child[i].cg_count <= 1) 4946 return (-1); 4947 grp = &grp->cg_child[i]; 4948 } 4949 4950 /* Must share L2. */ 4951 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 4952 return -1; 4953 4954 /* 4955 * Select the first member of the set that isn't the reference 4956 * CPU, which at this point is guaranteed to exist. 4957 */ 4958 for (i = 0; i < CPU_SETSIZE; i++) { 4959 if (CPU_ISSET(i, &grp->cg_mask) && i != cpu) 4960 return (i); 4961 } 4962 4963 /* Should never be reached */ 4964 return (-1); 4965 } 4966 4967 #else 4968 static int 4969 find_l2_neighbor(int cpu) 4970 { 4971 4972 return (-1); 4973 } 4974 #endif 4975 4976 /* 4977 * CPU mapping behaviors 4978 * --------------------- 4979 * 'separate txrx' refers to the separate_txrx sysctl 4980 * 'use logical' refers to the use_logical_cores sysctl 4981 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded 4982 * 4983 * separate use INTR 4984 * txrx logical CPUS result 4985 * ---------- --------- ------ ------------------------------------------------ 4986 * - - X RX and TX queues mapped to consecutive physical 4987 * cores with RX/TX pairs on same core and excess 4988 * of either following 4989 * - X X RX and TX queues mapped to consecutive cores 4990 * of any type with RX/TX pairs on same core and 4991 * excess of either following 4992 * X - X RX and TX queues mapped to consecutive physical 4993 * cores; all RX then all TX 4994 * X X X RX queues mapped to consecutive physical cores 4995 * first, then TX queues mapped to L2 neighbor of 4996 * the corresponding RX queue if one exists, 4997 * otherwise to consecutive physical cores 4998 * - n/a - RX and TX queues mapped to consecutive cores of 4999 * any type with RX/TX pairs on same core and excess 5000 * of either following 5001 * X n/a - RX and TX queues mapped to consecutive cores of 5002 * any type; all RX then all TX 5003 */ 5004 static unsigned int 5005 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid, 5006 bool is_tx) 5007 { 5008 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5009 unsigned int core_index; 5010 5011 if (ctx->ifc_sysctl_separate_txrx) { 5012 /* 5013 * When using separate CPUs for TX and RX, the assignment 5014 * will always be of a consecutive CPU out of the set of 5015 * context CPUs, except for the specific case where the 5016 * context CPUs are phsyical cores, the use of logical cores 5017 * has been enabled, the assignment is for TX, the TX qid 5018 * corresponds to an RX qid, and the CPU assigned to the 5019 * corresponding RX queue has an L2 neighbor. 5020 */ 5021 if (ctx->ifc_sysctl_use_logical_cores && 5022 ctx->ifc_cpus_are_physical_cores && 5023 is_tx && qid < scctx->isc_nrxqsets) { 5024 int l2_neighbor; 5025 unsigned int rx_cpuid; 5026 5027 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid); 5028 l2_neighbor = find_l2_neighbor(rx_cpuid); 5029 if (l2_neighbor != -1) { 5030 return (l2_neighbor); 5031 } 5032 /* 5033 * ... else fall through to the normal 5034 * consecutive-after-RX assignment scheme. 5035 * 5036 * Note that we are assuming that all RX queue CPUs 5037 * have an L2 neighbor, or all do not. If a mixed 5038 * scenario is possible, we will have to keep track 5039 * separately of how many queues prior to this one 5040 * were not able to be assigned to an L2 neighbor. 5041 */ 5042 } 5043 if (is_tx) 5044 core_index = scctx->isc_nrxqsets + qid; 5045 else 5046 core_index = qid; 5047 } else { 5048 core_index = qid; 5049 } 5050 5051 return (cpuid_advance(ctx, base_cpuid, core_index)); 5052 } 5053 5054 static uint16_t 5055 get_ctx_core_offset(if_ctx_t ctx) 5056 { 5057 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5058 struct cpu_offset *op; 5059 cpuset_t assigned_cpus; 5060 unsigned int cores_consumed; 5061 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset; 5062 unsigned int first_valid; 5063 unsigned int last_valid; 5064 unsigned int i; 5065 5066 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 5067 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 5068 5069 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) { 5070 /* 5071 * Align the user-chosen base CPU ID to the next valid CPU 5072 * for this device. If the chosen base CPU ID is smaller 5073 * than the first valid CPU or larger than the last valid 5074 * CPU, we assume the user does not know what the valid 5075 * range is for this device and is thinking in terms of a 5076 * zero-based reference frame, and so we shift the given 5077 * value into the valid range (and wrap accordingly) so the 5078 * intent is translated to the proper frame of reference. 5079 * If the base CPU ID is within the valid first/last, but 5080 * does not correspond to a valid CPU, it is advanced to the 5081 * next valid CPU (wrapping if necessary). 5082 */ 5083 if (base_cpuid < first_valid || base_cpuid > last_valid) { 5084 /* shift from zero-based to first_valid-based */ 5085 base_cpuid += first_valid; 5086 /* wrap to range [first_valid, last_valid] */ 5087 base_cpuid = (base_cpuid - first_valid) % 5088 (last_valid - first_valid + 1); 5089 } 5090 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) { 5091 /* 5092 * base_cpuid is in [first_valid, last_valid], but 5093 * not a member of the valid set. In this case, 5094 * there will always be a member of the valid set 5095 * with a CPU ID that is greater than base_cpuid, 5096 * and we simply advance to it. 5097 */ 5098 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) 5099 base_cpuid++; 5100 } 5101 return (base_cpuid); 5102 } 5103 5104 /* 5105 * Determine how many cores will be consumed by performing the CPU 5106 * assignments and counting how many of the assigned CPUs correspond 5107 * to CPUs in the set of context CPUs. This is done using the CPU 5108 * ID first_valid as the base CPU ID, as the base CPU must be within 5109 * the set of context CPUs. 5110 * 5111 * Note not all assigned CPUs will be in the set of context CPUs 5112 * when separate CPUs are being allocated to TX and RX queues, 5113 * assignment to logical cores has been enabled, the set of context 5114 * CPUs contains only physical CPUs, and TX queues are mapped to L2 5115 * neighbors of CPUs that RX queues have been mapped to - in this 5116 * case we do only want to count how many CPUs in the set of context 5117 * CPUs have been consumed, as that determines the next CPU in that 5118 * set to start allocating at for the next device for which 5119 * core_offset is not set. 5120 */ 5121 CPU_ZERO(&assigned_cpus); 5122 for (i = 0; i < scctx->isc_ntxqsets; i++) 5123 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true), 5124 &assigned_cpus); 5125 for (i = 0; i < scctx->isc_nrxqsets; i++) 5126 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false), 5127 &assigned_cpus); 5128 CPU_AND(&assigned_cpus, &assigned_cpus, &ctx->ifc_cpus); 5129 cores_consumed = CPU_COUNT(&assigned_cpus); 5130 5131 mtx_lock(&cpu_offset_mtx); 5132 SLIST_FOREACH(op, &cpu_offsets, entries) { 5133 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5134 base_cpuid = op->next_cpuid; 5135 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid, 5136 cores_consumed); 5137 MPASS(op->refcount < UINT_MAX); 5138 op->refcount++; 5139 break; 5140 } 5141 } 5142 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) { 5143 base_cpuid = first_valid; 5144 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 5145 M_NOWAIT | M_ZERO); 5146 if (op == NULL) { 5147 device_printf(ctx->ifc_dev, 5148 "allocation for cpu offset failed.\n"); 5149 } else { 5150 op->next_cpuid = cpuid_advance(ctx, base_cpuid, 5151 cores_consumed); 5152 op->refcount = 1; 5153 CPU_COPY(&ctx->ifc_cpus, &op->set); 5154 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 5155 } 5156 } 5157 mtx_unlock(&cpu_offset_mtx); 5158 5159 return (base_cpuid); 5160 } 5161 5162 static void 5163 unref_ctx_core_offset(if_ctx_t ctx) 5164 { 5165 struct cpu_offset *op, *top; 5166 5167 mtx_lock(&cpu_offset_mtx); 5168 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 5169 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5170 MPASS(op->refcount > 0); 5171 op->refcount--; 5172 if (op->refcount == 0) { 5173 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 5174 free(op, M_IFLIB); 5175 } 5176 break; 5177 } 5178 } 5179 mtx_unlock(&cpu_offset_mtx); 5180 } 5181 5182 int 5183 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 5184 { 5185 if_ctx_t ctx; 5186 if_t ifp; 5187 if_softc_ctx_t scctx; 5188 kobjop_desc_t kobj_desc; 5189 kobj_method_t *kobj_method; 5190 int err, msix, rid; 5191 int num_txd, num_rxd; 5192 5193 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 5194 5195 if (sc == NULL) { 5196 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 5197 device_set_softc(dev, ctx); 5198 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5199 } 5200 5201 ctx->ifc_sctx = sctx; 5202 ctx->ifc_dev = dev; 5203 ctx->ifc_softc = sc; 5204 5205 if ((err = iflib_register(ctx)) != 0) { 5206 device_printf(dev, "iflib_register failed %d\n", err); 5207 goto fail_ctx_free; 5208 } 5209 iflib_add_device_sysctl_pre(ctx); 5210 5211 scctx = &ctx->ifc_softc_ctx; 5212 ifp = ctx->ifc_ifp; 5213 5214 iflib_reset_qvalues(ctx); 5215 IFNET_WLOCK(); 5216 CTX_LOCK(ctx); 5217 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5218 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5219 goto fail_unlock; 5220 } 5221 _iflib_pre_assert(scctx); 5222 ctx->ifc_txrx = *scctx->isc_txrx; 5223 5224 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR)); 5225 5226 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 5227 ctx->ifc_mediap = scctx->isc_media; 5228 5229 #ifdef INVARIANTS 5230 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5231 MPASS(scctx->isc_tx_csum_flags); 5232 #endif 5233 5234 if_setcapabilities(ifp, 5235 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG); 5236 if_setcapenable(ifp, 5237 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG); 5238 5239 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5240 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5241 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5242 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5243 5244 num_txd = iflib_num_tx_descs(ctx); 5245 num_rxd = iflib_num_rx_descs(ctx); 5246 5247 /* XXX change for per-queue sizes */ 5248 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5249 num_txd, num_rxd); 5250 5251 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5252 scctx->isc_tx_nsegments = max(1, num_txd / 5253 MAX_SINGLE_PACKET_FRACTION); 5254 if (scctx->isc_tx_tso_segments_max > num_txd / 5255 MAX_SINGLE_PACKET_FRACTION) 5256 scctx->isc_tx_tso_segments_max = max(1, 5257 num_txd / MAX_SINGLE_PACKET_FRACTION); 5258 5259 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5260 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5261 /* 5262 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5263 * but some MACs do. 5264 */ 5265 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5266 IP_MAXPACKET)); 5267 /* 5268 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5269 * into account. In the worst case, each of these calls will 5270 * add another mbuf and, thus, the requirement for another DMA 5271 * segment. So for best performance, it doesn't make sense to 5272 * advertize a maximum of TSO segments that typically will 5273 * require defragmentation in iflib_encap(). 5274 */ 5275 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5276 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5277 } 5278 if (scctx->isc_rss_table_size == 0) 5279 scctx->isc_rss_table_size = 64; 5280 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5281 5282 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5283 /* XXX format name */ 5284 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5285 NULL, NULL, "admin"); 5286 5287 /* Set up cpu set. If it fails, use the set of all CPUs. */ 5288 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 5289 device_printf(dev, "Unable to fetch CPU list\n"); 5290 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 5291 ctx->ifc_cpus_are_physical_cores = false; 5292 } else 5293 ctx->ifc_cpus_are_physical_cores = true; 5294 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 5295 5296 /* 5297 ** Now set up MSI or MSI-X, should return us the number of supported 5298 ** vectors (will be 1 for a legacy interrupt and MSI). 5299 */ 5300 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 5301 msix = scctx->isc_vectors; 5302 } else if (scctx->isc_msix_bar != 0) 5303 /* 5304 * The simple fact that isc_msix_bar is not 0 does not mean we 5305 * we have a good value there that is known to work. 5306 */ 5307 msix = iflib_msix_init(ctx); 5308 else { 5309 scctx->isc_vectors = 1; 5310 scctx->isc_ntxqsets = 1; 5311 scctx->isc_nrxqsets = 1; 5312 scctx->isc_intr = IFLIB_INTR_LEGACY; 5313 msix = 0; 5314 } 5315 /* Get memory for the station queues */ 5316 if ((err = iflib_queues_alloc(ctx))) { 5317 device_printf(dev, "Unable to allocate queue memory\n"); 5318 goto fail_intr_free; 5319 } 5320 5321 if ((err = iflib_qset_structures_setup(ctx))) 5322 goto fail_queues; 5323 5324 /* 5325 * Now that we know how many queues there are, get the core offset. 5326 */ 5327 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 5328 5329 if (msix > 1) { 5330 /* 5331 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 5332 * aren't the default NULL implementation. 5333 */ 5334 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 5335 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5336 kobj_desc); 5337 if (kobj_method == &kobj_desc->deflt) { 5338 device_printf(dev, 5339 "MSI-X requires ifdi_rx_queue_intr_enable method"); 5340 err = EOPNOTSUPP; 5341 goto fail_queues; 5342 } 5343 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 5344 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5345 kobj_desc); 5346 if (kobj_method == &kobj_desc->deflt) { 5347 device_printf(dev, 5348 "MSI-X requires ifdi_tx_queue_intr_enable method"); 5349 err = EOPNOTSUPP; 5350 goto fail_queues; 5351 } 5352 5353 /* 5354 * Assign the MSI-X vectors. 5355 * Note that the default NULL ifdi_msix_intr_assign method will 5356 * fail here, too. 5357 */ 5358 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 5359 if (err != 0) { 5360 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 5361 err); 5362 goto fail_queues; 5363 } 5364 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 5365 rid = 0; 5366 if (scctx->isc_intr == IFLIB_INTR_MSI) { 5367 MPASS(msix == 1); 5368 rid = 1; 5369 } 5370 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 5371 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 5372 goto fail_queues; 5373 } 5374 } else { 5375 device_printf(dev, 5376 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 5377 err = ENODEV; 5378 goto fail_queues; 5379 } 5380 5381 /* 5382 * It prevents a double-locking panic with iflib_media_status when 5383 * the driver loads. 5384 */ 5385 CTX_UNLOCK(ctx); 5386 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5387 CTX_LOCK(ctx); 5388 5389 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5390 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5391 goto fail_detach; 5392 } 5393 5394 /* 5395 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5396 * This must appear after the call to ether_ifattach() because 5397 * ether_ifattach() sets if_hdrlen to the default value. 5398 */ 5399 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5400 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5401 5402 if ((err = iflib_netmap_attach(ctx))) { 5403 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 5404 goto fail_detach; 5405 } 5406 *ctxp = ctx; 5407 5408 DEBUGNET_SET(ctx->ifc_ifp, iflib); 5409 5410 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5411 iflib_add_device_sysctl_post(ctx); 5412 iflib_add_pfil(ctx); 5413 ctx->ifc_flags |= IFC_INIT_DONE; 5414 CTX_UNLOCK(ctx); 5415 IFNET_WUNLOCK(); 5416 5417 return (0); 5418 5419 fail_detach: 5420 ether_ifdetach(ctx->ifc_ifp); 5421 fail_queues: 5422 iflib_tqg_detach(ctx); 5423 iflib_tx_structures_free(ctx); 5424 iflib_rx_structures_free(ctx); 5425 IFDI_DETACH(ctx); 5426 IFDI_QUEUES_FREE(ctx); 5427 fail_intr_free: 5428 iflib_free_intr_mem(ctx); 5429 fail_unlock: 5430 CTX_UNLOCK(ctx); 5431 IFNET_WUNLOCK(); 5432 iflib_deregister(ctx); 5433 fail_ctx_free: 5434 device_set_softc(ctx->ifc_dev, NULL); 5435 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5436 free(ctx->ifc_softc, M_IFLIB); 5437 free(ctx, M_IFLIB); 5438 return (err); 5439 } 5440 5441 int 5442 iflib_device_attach(device_t dev) 5443 { 5444 if_ctx_t ctx; 5445 if_shared_ctx_t sctx; 5446 5447 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5448 return (ENOTSUP); 5449 5450 pci_enable_busmaster(dev); 5451 5452 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5453 } 5454 5455 int 5456 iflib_device_deregister(if_ctx_t ctx) 5457 { 5458 if_t ifp = ctx->ifc_ifp; 5459 device_t dev = ctx->ifc_dev; 5460 5461 /* Make sure VLANS are not using driver */ 5462 if (if_vlantrunkinuse(ifp)) { 5463 device_printf(dev, "Vlan in use, detach first\n"); 5464 return (EBUSY); 5465 } 5466 #ifdef PCI_IOV 5467 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5468 device_printf(dev, "SR-IOV in use; detach first.\n"); 5469 return (EBUSY); 5470 } 5471 #endif 5472 5473 STATE_LOCK(ctx); 5474 ctx->ifc_flags |= IFC_IN_DETACH; 5475 STATE_UNLOCK(ctx); 5476 5477 /* Unregister VLAN handlers before calling iflib_stop() */ 5478 iflib_unregister_vlan_handlers(ctx); 5479 5480 iflib_netmap_detach(ifp); 5481 ether_ifdetach(ifp); 5482 5483 CTX_LOCK(ctx); 5484 iflib_stop(ctx); 5485 CTX_UNLOCK(ctx); 5486 5487 iflib_rem_pfil(ctx); 5488 if (ctx->ifc_led_dev != NULL) 5489 led_destroy(ctx->ifc_led_dev); 5490 5491 iflib_tqg_detach(ctx); 5492 iflib_tx_structures_free(ctx); 5493 iflib_rx_structures_free(ctx); 5494 5495 CTX_LOCK(ctx); 5496 IFDI_DETACH(ctx); 5497 IFDI_QUEUES_FREE(ctx); 5498 CTX_UNLOCK(ctx); 5499 5500 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5501 iflib_free_intr_mem(ctx); 5502 5503 bus_generic_detach(dev); 5504 5505 iflib_deregister(ctx); 5506 5507 device_set_softc(ctx->ifc_dev, NULL); 5508 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5509 free(ctx->ifc_softc, M_IFLIB); 5510 unref_ctx_core_offset(ctx); 5511 free(ctx, M_IFLIB); 5512 return (0); 5513 } 5514 5515 static void 5516 iflib_tqg_detach(if_ctx_t ctx) 5517 { 5518 iflib_txq_t txq; 5519 iflib_rxq_t rxq; 5520 int i; 5521 struct taskqgroup *tqg; 5522 5523 /* XXX drain any dependent tasks */ 5524 tqg = qgroup_if_io_tqg; 5525 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5526 callout_drain(&txq->ift_timer); 5527 #ifdef DEV_NETMAP 5528 callout_drain(&txq->ift_netmap_timer); 5529 #endif /* DEV_NETMAP */ 5530 if (txq->ift_task.gt_uniq != NULL) 5531 taskqgroup_detach(tqg, &txq->ift_task); 5532 } 5533 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5534 if (rxq->ifr_task.gt_uniq != NULL) 5535 taskqgroup_detach(tqg, &rxq->ifr_task); 5536 } 5537 tqg = qgroup_if_config_tqg; 5538 if (ctx->ifc_admin_task.gt_uniq != NULL) 5539 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5540 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5541 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5542 } 5543 5544 static void 5545 iflib_free_intr_mem(if_ctx_t ctx) 5546 { 5547 5548 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5549 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5550 } 5551 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5552 pci_release_msi(ctx->ifc_dev); 5553 } 5554 if (ctx->ifc_msix_mem != NULL) { 5555 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5556 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5557 ctx->ifc_msix_mem = NULL; 5558 } 5559 } 5560 5561 int 5562 iflib_device_detach(device_t dev) 5563 { 5564 if_ctx_t ctx = device_get_softc(dev); 5565 5566 return (iflib_device_deregister(ctx)); 5567 } 5568 5569 int 5570 iflib_device_suspend(device_t dev) 5571 { 5572 if_ctx_t ctx = device_get_softc(dev); 5573 5574 CTX_LOCK(ctx); 5575 IFDI_SUSPEND(ctx); 5576 CTX_UNLOCK(ctx); 5577 5578 return bus_generic_suspend(dev); 5579 } 5580 int 5581 iflib_device_shutdown(device_t dev) 5582 { 5583 if_ctx_t ctx = device_get_softc(dev); 5584 5585 CTX_LOCK(ctx); 5586 IFDI_SHUTDOWN(ctx); 5587 CTX_UNLOCK(ctx); 5588 5589 return bus_generic_suspend(dev); 5590 } 5591 5592 int 5593 iflib_device_resume(device_t dev) 5594 { 5595 if_ctx_t ctx = device_get_softc(dev); 5596 iflib_txq_t txq = ctx->ifc_txqs; 5597 5598 CTX_LOCK(ctx); 5599 IFDI_RESUME(ctx); 5600 iflib_if_init_locked(ctx); 5601 CTX_UNLOCK(ctx); 5602 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5603 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5604 5605 return (bus_generic_resume(dev)); 5606 } 5607 5608 int 5609 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5610 { 5611 int error; 5612 if_ctx_t ctx = device_get_softc(dev); 5613 5614 CTX_LOCK(ctx); 5615 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5616 CTX_UNLOCK(ctx); 5617 5618 return (error); 5619 } 5620 5621 void 5622 iflib_device_iov_uninit(device_t dev) 5623 { 5624 if_ctx_t ctx = device_get_softc(dev); 5625 5626 CTX_LOCK(ctx); 5627 IFDI_IOV_UNINIT(ctx); 5628 CTX_UNLOCK(ctx); 5629 } 5630 5631 int 5632 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5633 { 5634 int error; 5635 if_ctx_t ctx = device_get_softc(dev); 5636 5637 CTX_LOCK(ctx); 5638 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5639 CTX_UNLOCK(ctx); 5640 5641 return (error); 5642 } 5643 5644 /********************************************************************* 5645 * 5646 * MODULE FUNCTION DEFINITIONS 5647 * 5648 **********************************************************************/ 5649 5650 /* 5651 * - Start a fast taskqueue thread for each core 5652 * - Start a taskqueue for control operations 5653 */ 5654 static int 5655 iflib_module_init(void) 5656 { 5657 iflib_timer_default = hz / 2; 5658 return (0); 5659 } 5660 5661 static int 5662 iflib_module_event_handler(module_t mod, int what, void *arg) 5663 { 5664 int err; 5665 5666 switch (what) { 5667 case MOD_LOAD: 5668 if ((err = iflib_module_init()) != 0) 5669 return (err); 5670 break; 5671 case MOD_UNLOAD: 5672 return (EBUSY); 5673 default: 5674 return (EOPNOTSUPP); 5675 } 5676 5677 return (0); 5678 } 5679 5680 /********************************************************************* 5681 * 5682 * PUBLIC FUNCTION DEFINITIONS 5683 * ordered as in iflib.h 5684 * 5685 **********************************************************************/ 5686 5687 static void 5688 _iflib_assert(if_shared_ctx_t sctx) 5689 { 5690 int i; 5691 5692 MPASS(sctx->isc_tx_maxsize); 5693 MPASS(sctx->isc_tx_maxsegsize); 5694 5695 MPASS(sctx->isc_rx_maxsize); 5696 MPASS(sctx->isc_rx_nsegments); 5697 MPASS(sctx->isc_rx_maxsegsize); 5698 5699 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5700 for (i = 0; i < sctx->isc_nrxqs; i++) { 5701 MPASS(sctx->isc_nrxd_min[i]); 5702 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5703 MPASS(sctx->isc_nrxd_max[i]); 5704 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5705 MPASS(sctx->isc_nrxd_default[i]); 5706 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5707 } 5708 5709 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5710 for (i = 0; i < sctx->isc_ntxqs; i++) { 5711 MPASS(sctx->isc_ntxd_min[i]); 5712 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5713 MPASS(sctx->isc_ntxd_max[i]); 5714 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5715 MPASS(sctx->isc_ntxd_default[i]); 5716 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5717 } 5718 } 5719 5720 static void 5721 _iflib_pre_assert(if_softc_ctx_t scctx) 5722 { 5723 5724 MPASS(scctx->isc_txrx->ift_txd_encap); 5725 MPASS(scctx->isc_txrx->ift_txd_flush); 5726 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5727 MPASS(scctx->isc_txrx->ift_rxd_available); 5728 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5729 MPASS(scctx->isc_txrx->ift_rxd_refill); 5730 MPASS(scctx->isc_txrx->ift_rxd_flush); 5731 } 5732 5733 static int 5734 iflib_register(if_ctx_t ctx) 5735 { 5736 if_shared_ctx_t sctx = ctx->ifc_sctx; 5737 driver_t *driver = sctx->isc_driver; 5738 device_t dev = ctx->ifc_dev; 5739 if_t ifp; 5740 5741 _iflib_assert(sctx); 5742 5743 CTX_LOCK_INIT(ctx); 5744 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5745 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5746 if (ifp == NULL) { 5747 device_printf(dev, "can not allocate ifnet structure\n"); 5748 return (ENOMEM); 5749 } 5750 5751 /* 5752 * Initialize our context's device specific methods 5753 */ 5754 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5755 kobj_class_compile((kobj_class_t) driver); 5756 5757 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5758 if_setsoftc(ifp, ctx); 5759 if_setdev(ifp, dev); 5760 if_setinitfn(ifp, iflib_if_init); 5761 if_setioctlfn(ifp, iflib_if_ioctl); 5762 #ifdef ALTQ 5763 if_setstartfn(ifp, iflib_altq_if_start); 5764 if_settransmitfn(ifp, iflib_altq_if_transmit); 5765 if_setsendqready(ifp); 5766 #else 5767 if_settransmitfn(ifp, iflib_if_transmit); 5768 #endif 5769 if_setqflushfn(ifp, iflib_if_qflush); 5770 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5771 ctx->ifc_vlan_attach_event = 5772 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5773 EVENTHANDLER_PRI_FIRST); 5774 ctx->ifc_vlan_detach_event = 5775 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5776 EVENTHANDLER_PRI_FIRST); 5777 5778 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5779 ctx->ifc_mediap = &ctx->ifc_media; 5780 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5781 iflib_media_change, iflib_media_status); 5782 } 5783 return (0); 5784 } 5785 5786 static void 5787 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5788 { 5789 /* Unregister VLAN events */ 5790 if (ctx->ifc_vlan_attach_event != NULL) { 5791 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5792 ctx->ifc_vlan_attach_event = NULL; 5793 } 5794 if (ctx->ifc_vlan_detach_event != NULL) { 5795 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5796 ctx->ifc_vlan_detach_event = NULL; 5797 } 5798 5799 } 5800 5801 static void 5802 iflib_deregister(if_ctx_t ctx) 5803 { 5804 if_t ifp = ctx->ifc_ifp; 5805 5806 /* Remove all media */ 5807 ifmedia_removeall(&ctx->ifc_media); 5808 5809 /* Ensure that VLAN event handlers are unregistered */ 5810 iflib_unregister_vlan_handlers(ctx); 5811 5812 /* Release kobject reference */ 5813 kobj_delete((kobj_t) ctx, NULL); 5814 5815 /* Free the ifnet structure */ 5816 if_free(ifp); 5817 5818 STATE_LOCK_DESTROY(ctx); 5819 5820 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5821 CTX_LOCK_DESTROY(ctx); 5822 } 5823 5824 static int 5825 iflib_queues_alloc(if_ctx_t ctx) 5826 { 5827 if_shared_ctx_t sctx = ctx->ifc_sctx; 5828 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5829 device_t dev = ctx->ifc_dev; 5830 int nrxqsets = scctx->isc_nrxqsets; 5831 int ntxqsets = scctx->isc_ntxqsets; 5832 iflib_txq_t txq; 5833 iflib_rxq_t rxq; 5834 iflib_fl_t fl = NULL; 5835 int i, j, cpu, err, txconf, rxconf; 5836 iflib_dma_info_t ifdip; 5837 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5838 uint32_t *txqsizes = scctx->isc_txqsizes; 5839 uint8_t nrxqs = sctx->isc_nrxqs; 5840 uint8_t ntxqs = sctx->isc_ntxqs; 5841 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5842 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0); 5843 caddr_t *vaddrs; 5844 uint64_t *paddrs; 5845 5846 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5847 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5848 KASSERT(nrxqs >= fl_offset + nfree_lists, 5849 ("there must be at least a rxq for each free list")); 5850 5851 /* Allocate the TX ring struct memory */ 5852 if (!(ctx->ifc_txqs = 5853 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5854 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5855 device_printf(dev, "Unable to allocate TX ring memory\n"); 5856 err = ENOMEM; 5857 goto fail; 5858 } 5859 5860 /* Now allocate the RX */ 5861 if (!(ctx->ifc_rxqs = 5862 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5863 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5864 device_printf(dev, "Unable to allocate RX ring memory\n"); 5865 err = ENOMEM; 5866 goto rx_fail; 5867 } 5868 5869 txq = ctx->ifc_txqs; 5870 rxq = ctx->ifc_rxqs; 5871 5872 /* 5873 * XXX handle allocation failure 5874 */ 5875 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5876 /* Set up some basics */ 5877 5878 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5879 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5880 device_printf(dev, 5881 "Unable to allocate TX DMA info memory\n"); 5882 err = ENOMEM; 5883 goto err_tx_desc; 5884 } 5885 txq->ift_ifdi = ifdip; 5886 for (j = 0; j < ntxqs; j++, ifdip++) { 5887 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5888 device_printf(dev, 5889 "Unable to allocate TX descriptors\n"); 5890 err = ENOMEM; 5891 goto err_tx_desc; 5892 } 5893 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5894 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5895 } 5896 txq->ift_ctx = ctx; 5897 txq->ift_id = i; 5898 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5899 txq->ift_br_offset = 1; 5900 } else { 5901 txq->ift_br_offset = 0; 5902 } 5903 5904 if (iflib_txsd_alloc(txq)) { 5905 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5906 err = ENOMEM; 5907 goto err_tx_desc; 5908 } 5909 5910 /* Initialize the TX lock */ 5911 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5912 device_get_nameunit(dev), txq->ift_id); 5913 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5914 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5915 txq->ift_timer.c_cpu = cpu; 5916 #ifdef DEV_NETMAP 5917 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 5918 txq->ift_netmap_timer.c_cpu = cpu; 5919 #endif /* DEV_NETMAP */ 5920 5921 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5922 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5923 if (err) { 5924 /* XXX free any allocated rings */ 5925 device_printf(dev, "Unable to allocate buf_ring\n"); 5926 goto err_tx_desc; 5927 } 5928 } 5929 5930 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5931 /* Set up some basics */ 5932 callout_init(&rxq->ifr_watchdog, 1); 5933 5934 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5935 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5936 device_printf(dev, 5937 "Unable to allocate RX DMA info memory\n"); 5938 err = ENOMEM; 5939 goto err_tx_desc; 5940 } 5941 5942 rxq->ifr_ifdi = ifdip; 5943 /* XXX this needs to be changed if #rx queues != #tx queues */ 5944 rxq->ifr_ntxqirq = 1; 5945 rxq->ifr_txqid[0] = i; 5946 for (j = 0; j < nrxqs; j++, ifdip++) { 5947 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5948 device_printf(dev, 5949 "Unable to allocate RX descriptors\n"); 5950 err = ENOMEM; 5951 goto err_tx_desc; 5952 } 5953 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5954 } 5955 rxq->ifr_ctx = ctx; 5956 rxq->ifr_id = i; 5957 rxq->ifr_fl_offset = fl_offset; 5958 rxq->ifr_nfl = nfree_lists; 5959 if (!(fl = 5960 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5961 device_printf(dev, "Unable to allocate free list memory\n"); 5962 err = ENOMEM; 5963 goto err_tx_desc; 5964 } 5965 rxq->ifr_fl = fl; 5966 for (j = 0; j < nfree_lists; j++) { 5967 fl[j].ifl_rxq = rxq; 5968 fl[j].ifl_id = j; 5969 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5970 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5971 } 5972 /* Allocate receive buffers for the ring */ 5973 if (iflib_rxsd_alloc(rxq)) { 5974 device_printf(dev, 5975 "Critical Failure setting up receive buffers\n"); 5976 err = ENOMEM; 5977 goto err_rx_desc; 5978 } 5979 5980 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5981 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5982 M_WAITOK); 5983 } 5984 5985 /* TXQs */ 5986 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5987 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5988 for (i = 0; i < ntxqsets; i++) { 5989 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5990 5991 for (j = 0; j < ntxqs; j++, di++) { 5992 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5993 paddrs[i*ntxqs + j] = di->idi_paddr; 5994 } 5995 } 5996 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5997 device_printf(ctx->ifc_dev, 5998 "Unable to allocate device TX queue\n"); 5999 iflib_tx_structures_free(ctx); 6000 free(vaddrs, M_IFLIB); 6001 free(paddrs, M_IFLIB); 6002 goto err_rx_desc; 6003 } 6004 free(vaddrs, M_IFLIB); 6005 free(paddrs, M_IFLIB); 6006 6007 /* RXQs */ 6008 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6009 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6010 for (i = 0; i < nrxqsets; i++) { 6011 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 6012 6013 for (j = 0; j < nrxqs; j++, di++) { 6014 vaddrs[i*nrxqs + j] = di->idi_vaddr; 6015 paddrs[i*nrxqs + j] = di->idi_paddr; 6016 } 6017 } 6018 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 6019 device_printf(ctx->ifc_dev, 6020 "Unable to allocate device RX queue\n"); 6021 iflib_tx_structures_free(ctx); 6022 free(vaddrs, M_IFLIB); 6023 free(paddrs, M_IFLIB); 6024 goto err_rx_desc; 6025 } 6026 free(vaddrs, M_IFLIB); 6027 free(paddrs, M_IFLIB); 6028 6029 return (0); 6030 6031 /* XXX handle allocation failure changes */ 6032 err_rx_desc: 6033 err_tx_desc: 6034 rx_fail: 6035 if (ctx->ifc_rxqs != NULL) 6036 free(ctx->ifc_rxqs, M_IFLIB); 6037 ctx->ifc_rxqs = NULL; 6038 if (ctx->ifc_txqs != NULL) 6039 free(ctx->ifc_txqs, M_IFLIB); 6040 ctx->ifc_txqs = NULL; 6041 fail: 6042 return (err); 6043 } 6044 6045 static int 6046 iflib_tx_structures_setup(if_ctx_t ctx) 6047 { 6048 iflib_txq_t txq = ctx->ifc_txqs; 6049 int i; 6050 6051 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 6052 iflib_txq_setup(txq); 6053 6054 return (0); 6055 } 6056 6057 static void 6058 iflib_tx_structures_free(if_ctx_t ctx) 6059 { 6060 iflib_txq_t txq = ctx->ifc_txqs; 6061 if_shared_ctx_t sctx = ctx->ifc_sctx; 6062 int i, j; 6063 6064 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6065 for (j = 0; j < sctx->isc_ntxqs; j++) 6066 iflib_dma_free(&txq->ift_ifdi[j]); 6067 iflib_txq_destroy(txq); 6068 } 6069 free(ctx->ifc_txqs, M_IFLIB); 6070 ctx->ifc_txqs = NULL; 6071 } 6072 6073 /********************************************************************* 6074 * 6075 * Initialize all receive rings. 6076 * 6077 **********************************************************************/ 6078 static int 6079 iflib_rx_structures_setup(if_ctx_t ctx) 6080 { 6081 iflib_rxq_t rxq = ctx->ifc_rxqs; 6082 int q; 6083 #if defined(INET6) || defined(INET) 6084 int err, i; 6085 #endif 6086 6087 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 6088 #if defined(INET6) || defined(INET) 6089 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 6090 TCP_LRO_ENTRIES, min(1024, 6091 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 6092 if (err != 0) { 6093 device_printf(ctx->ifc_dev, 6094 "LRO Initialization failed!\n"); 6095 goto fail; 6096 } 6097 #endif 6098 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 6099 } 6100 return (0); 6101 #if defined(INET6) || defined(INET) 6102 fail: 6103 /* 6104 * Free LRO resources allocated so far, we will only handle 6105 * the rings that completed, the failing case will have 6106 * cleaned up for itself. 'q' failed, so its the terminus. 6107 */ 6108 rxq = ctx->ifc_rxqs; 6109 for (i = 0; i < q; ++i, rxq++) { 6110 tcp_lro_free(&rxq->ifr_lc); 6111 } 6112 return (err); 6113 #endif 6114 } 6115 6116 /********************************************************************* 6117 * 6118 * Free all receive rings. 6119 * 6120 **********************************************************************/ 6121 static void 6122 iflib_rx_structures_free(if_ctx_t ctx) 6123 { 6124 iflib_rxq_t rxq = ctx->ifc_rxqs; 6125 if_shared_ctx_t sctx = ctx->ifc_sctx; 6126 int i, j; 6127 6128 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 6129 for (j = 0; j < sctx->isc_nrxqs; j++) 6130 iflib_dma_free(&rxq->ifr_ifdi[j]); 6131 iflib_rx_sds_free(rxq); 6132 #if defined(INET6) || defined(INET) 6133 tcp_lro_free(&rxq->ifr_lc); 6134 #endif 6135 } 6136 free(ctx->ifc_rxqs, M_IFLIB); 6137 ctx->ifc_rxqs = NULL; 6138 } 6139 6140 static int 6141 iflib_qset_structures_setup(if_ctx_t ctx) 6142 { 6143 int err; 6144 6145 /* 6146 * It is expected that the caller takes care of freeing queues if this 6147 * fails. 6148 */ 6149 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 6150 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 6151 return (err); 6152 } 6153 6154 if ((err = iflib_rx_structures_setup(ctx)) != 0) 6155 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 6156 6157 return (err); 6158 } 6159 6160 int 6161 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 6162 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 6163 { 6164 6165 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 6166 } 6167 6168 /* Just to avoid copy/paste */ 6169 static inline int 6170 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6171 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 6172 const char *name) 6173 { 6174 device_t dev; 6175 unsigned int base_cpuid, cpuid; 6176 int err; 6177 6178 dev = ctx->ifc_dev; 6179 base_cpuid = ctx->ifc_sysctl_core_offset; 6180 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX); 6181 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, 6182 irq ? irq->ii_res : NULL, name); 6183 if (err) { 6184 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6185 return (err); 6186 } 6187 #ifdef notyet 6188 if (cpuid > ctx->ifc_cpuid_highest) 6189 ctx->ifc_cpuid_highest = cpuid; 6190 #endif 6191 return (0); 6192 } 6193 6194 int 6195 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6196 iflib_intr_type_t type, driver_filter_t *filter, 6197 void *filter_arg, int qid, const char *name) 6198 { 6199 device_t dev; 6200 struct grouptask *gtask; 6201 struct taskqgroup *tqg; 6202 iflib_filter_info_t info; 6203 gtask_fn_t *fn; 6204 int tqrid, err; 6205 driver_filter_t *intr_fast; 6206 void *q; 6207 6208 info = &ctx->ifc_filter_info; 6209 tqrid = rid; 6210 6211 switch (type) { 6212 /* XXX merge tx/rx for netmap? */ 6213 case IFLIB_INTR_TX: 6214 q = &ctx->ifc_txqs[qid]; 6215 info = &ctx->ifc_txqs[qid].ift_filter_info; 6216 gtask = &ctx->ifc_txqs[qid].ift_task; 6217 tqg = qgroup_if_io_tqg; 6218 fn = _task_fn_tx; 6219 intr_fast = iflib_fast_intr; 6220 GROUPTASK_INIT(gtask, 0, fn, q); 6221 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6222 break; 6223 case IFLIB_INTR_RX: 6224 q = &ctx->ifc_rxqs[qid]; 6225 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6226 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6227 tqg = qgroup_if_io_tqg; 6228 fn = _task_fn_rx; 6229 intr_fast = iflib_fast_intr; 6230 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6231 break; 6232 case IFLIB_INTR_RXTX: 6233 q = &ctx->ifc_rxqs[qid]; 6234 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6235 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6236 tqg = qgroup_if_io_tqg; 6237 fn = _task_fn_rx; 6238 intr_fast = iflib_fast_intr_rxtx; 6239 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6240 break; 6241 case IFLIB_INTR_ADMIN: 6242 q = ctx; 6243 tqrid = -1; 6244 info = &ctx->ifc_filter_info; 6245 gtask = &ctx->ifc_admin_task; 6246 tqg = qgroup_if_config_tqg; 6247 fn = _task_fn_admin; 6248 intr_fast = iflib_fast_intr_ctx; 6249 break; 6250 default: 6251 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6252 __func__); 6253 return (EINVAL); 6254 } 6255 6256 info->ifi_filter = filter; 6257 info->ifi_filter_arg = filter_arg; 6258 info->ifi_task = gtask; 6259 info->ifi_ctx = q; 6260 6261 dev = ctx->ifc_dev; 6262 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6263 if (err != 0) { 6264 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6265 return (err); 6266 } 6267 if (type == IFLIB_INTR_ADMIN) 6268 return (0); 6269 6270 if (tqrid != -1) { 6271 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6272 name); 6273 if (err) 6274 return (err); 6275 } else { 6276 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6277 } 6278 6279 return (0); 6280 } 6281 6282 void 6283 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6284 void *arg, int qid, const char *name) 6285 { 6286 device_t dev; 6287 struct grouptask *gtask; 6288 struct taskqgroup *tqg; 6289 gtask_fn_t *fn; 6290 void *q; 6291 int err; 6292 6293 switch (type) { 6294 case IFLIB_INTR_TX: 6295 q = &ctx->ifc_txqs[qid]; 6296 gtask = &ctx->ifc_txqs[qid].ift_task; 6297 tqg = qgroup_if_io_tqg; 6298 fn = _task_fn_tx; 6299 GROUPTASK_INIT(gtask, 0, fn, q); 6300 break; 6301 case IFLIB_INTR_RX: 6302 q = &ctx->ifc_rxqs[qid]; 6303 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6304 tqg = qgroup_if_io_tqg; 6305 fn = _task_fn_rx; 6306 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6307 break; 6308 case IFLIB_INTR_IOV: 6309 q = ctx; 6310 gtask = &ctx->ifc_vflr_task; 6311 tqg = qgroup_if_config_tqg; 6312 fn = _task_fn_iov; 6313 GROUPTASK_INIT(gtask, 0, fn, q); 6314 break; 6315 default: 6316 panic("unknown net intr type"); 6317 } 6318 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name); 6319 if (err) { 6320 dev = ctx->ifc_dev; 6321 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL, 6322 name); 6323 } 6324 } 6325 6326 void 6327 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6328 { 6329 6330 if (irq->ii_tag) 6331 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6332 6333 if (irq->ii_res) 6334 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6335 rman_get_rid(irq->ii_res), irq->ii_res); 6336 } 6337 6338 static int 6339 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6340 { 6341 iflib_txq_t txq = ctx->ifc_txqs; 6342 iflib_rxq_t rxq = ctx->ifc_rxqs; 6343 if_irq_t irq = &ctx->ifc_legacy_irq; 6344 iflib_filter_info_t info; 6345 device_t dev; 6346 struct grouptask *gtask; 6347 struct resource *res; 6348 struct taskqgroup *tqg; 6349 void *q; 6350 int err, tqrid; 6351 bool rx_only; 6352 6353 q = &ctx->ifc_rxqs[0]; 6354 info = &rxq[0].ifr_filter_info; 6355 gtask = &rxq[0].ifr_task; 6356 tqg = qgroup_if_io_tqg; 6357 tqrid = *rid; 6358 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6359 6360 ctx->ifc_flags |= IFC_LEGACY; 6361 info->ifi_filter = filter; 6362 info->ifi_filter_arg = filter_arg; 6363 info->ifi_task = gtask; 6364 info->ifi_ctx = rx_only ? ctx : q; 6365 6366 dev = ctx->ifc_dev; 6367 /* We allocate a single interrupt resource */ 6368 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6369 iflib_fast_intr_rxtx, NULL, info, name); 6370 if (err != 0) 6371 return (err); 6372 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6373 res = irq->ii_res; 6374 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6375 6376 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6377 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6378 "tx"); 6379 return (0); 6380 } 6381 6382 void 6383 iflib_led_create(if_ctx_t ctx) 6384 { 6385 6386 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6387 device_get_nameunit(ctx->ifc_dev)); 6388 } 6389 6390 void 6391 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6392 { 6393 6394 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6395 } 6396 6397 void 6398 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6399 { 6400 6401 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6402 } 6403 6404 void 6405 iflib_admin_intr_deferred(if_ctx_t ctx) 6406 { 6407 6408 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6409 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6410 } 6411 6412 void 6413 iflib_iov_intr_deferred(if_ctx_t ctx) 6414 { 6415 6416 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6417 } 6418 6419 void 6420 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6421 { 6422 6423 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6424 name); 6425 } 6426 6427 void 6428 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6429 const char *name) 6430 { 6431 6432 GROUPTASK_INIT(gtask, 0, fn, ctx); 6433 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6434 name); 6435 } 6436 6437 void 6438 iflib_config_gtask_deinit(struct grouptask *gtask) 6439 { 6440 6441 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6442 } 6443 6444 void 6445 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6446 { 6447 if_t ifp = ctx->ifc_ifp; 6448 iflib_txq_t txq = ctx->ifc_txqs; 6449 6450 if_setbaudrate(ifp, baudrate); 6451 if (baudrate >= IF_Gbps(10)) { 6452 STATE_LOCK(ctx); 6453 ctx->ifc_flags |= IFC_PREFETCH; 6454 STATE_UNLOCK(ctx); 6455 } 6456 /* If link down, disable watchdog */ 6457 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6458 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6459 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6460 } 6461 ctx->ifc_link_state = link_state; 6462 if_link_state_change(ifp, link_state); 6463 } 6464 6465 static int 6466 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6467 { 6468 int credits; 6469 #ifdef INVARIANTS 6470 int credits_pre = txq->ift_cidx_processed; 6471 #endif 6472 6473 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6474 BUS_DMASYNC_POSTREAD); 6475 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6476 return (0); 6477 6478 txq->ift_processed += credits; 6479 txq->ift_cidx_processed += credits; 6480 6481 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6482 if (txq->ift_cidx_processed >= txq->ift_size) 6483 txq->ift_cidx_processed -= txq->ift_size; 6484 return (credits); 6485 } 6486 6487 static int 6488 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6489 { 6490 iflib_fl_t fl; 6491 u_int i; 6492 6493 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6494 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6495 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6496 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6497 budget)); 6498 } 6499 6500 void 6501 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6502 const char *description, if_int_delay_info_t info, 6503 int offset, int value) 6504 { 6505 info->iidi_ctx = ctx; 6506 info->iidi_offset = offset; 6507 info->iidi_value = value; 6508 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6509 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6510 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6511 info, 0, iflib_sysctl_int_delay, "I", description); 6512 } 6513 6514 struct sx * 6515 iflib_ctx_lock_get(if_ctx_t ctx) 6516 { 6517 6518 return (&ctx->ifc_ctx_sx); 6519 } 6520 6521 static int 6522 iflib_msix_init(if_ctx_t ctx) 6523 { 6524 device_t dev = ctx->ifc_dev; 6525 if_shared_ctx_t sctx = ctx->ifc_sctx; 6526 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6527 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6528 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6529 6530 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6531 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6532 6533 if (bootverbose) 6534 device_printf(dev, "msix_init qsets capped at %d\n", 6535 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6536 6537 /* Override by tuneable */ 6538 if (scctx->isc_disable_msix) 6539 goto msi; 6540 6541 /* First try MSI-X */ 6542 if ((msgs = pci_msix_count(dev)) == 0) { 6543 if (bootverbose) 6544 device_printf(dev, "MSI-X not supported or disabled\n"); 6545 goto msi; 6546 } 6547 6548 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6549 /* 6550 * bar == -1 => "trust me I know what I'm doing" 6551 * Some drivers are for hardware that is so shoddily 6552 * documented that no one knows which bars are which 6553 * so the developer has to map all bars. This hack 6554 * allows shoddy garbage to use MSI-X in this framework. 6555 */ 6556 if (bar != -1) { 6557 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6558 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6559 if (ctx->ifc_msix_mem == NULL) { 6560 device_printf(dev, "Unable to map MSI-X table\n"); 6561 goto msi; 6562 } 6563 } 6564 6565 admincnt = sctx->isc_admin_intrcnt; 6566 #if IFLIB_DEBUG 6567 /* use only 1 qset in debug mode */ 6568 queuemsgs = min(msgs - admincnt, 1); 6569 #else 6570 queuemsgs = msgs - admincnt; 6571 #endif 6572 #ifdef RSS 6573 queues = imin(queuemsgs, rss_getnumbuckets()); 6574 #else 6575 queues = queuemsgs; 6576 #endif 6577 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6578 if (bootverbose) 6579 device_printf(dev, 6580 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6581 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6582 #ifdef RSS 6583 /* If we're doing RSS, clamp at the number of RSS buckets */ 6584 if (queues > rss_getnumbuckets()) 6585 queues = rss_getnumbuckets(); 6586 #endif 6587 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6588 rx_queues = iflib_num_rx_queues; 6589 else 6590 rx_queues = queues; 6591 6592 if (rx_queues > scctx->isc_nrxqsets) 6593 rx_queues = scctx->isc_nrxqsets; 6594 6595 /* 6596 * We want this to be all logical CPUs by default 6597 */ 6598 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6599 tx_queues = iflib_num_tx_queues; 6600 else 6601 tx_queues = mp_ncpus; 6602 6603 if (tx_queues > scctx->isc_ntxqsets) 6604 tx_queues = scctx->isc_ntxqsets; 6605 6606 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6607 #ifdef INVARIANTS 6608 if (tx_queues != rx_queues) 6609 device_printf(dev, 6610 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6611 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6612 #endif 6613 tx_queues = min(rx_queues, tx_queues); 6614 rx_queues = min(rx_queues, tx_queues); 6615 } 6616 6617 vectors = rx_queues + admincnt; 6618 if (msgs < vectors) { 6619 device_printf(dev, 6620 "insufficient number of MSI-X vectors " 6621 "(supported %d, need %d)\n", msgs, vectors); 6622 goto msi; 6623 } 6624 6625 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6626 tx_queues); 6627 msgs = vectors; 6628 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6629 if (vectors != msgs) { 6630 device_printf(dev, 6631 "Unable to allocate sufficient MSI-X vectors " 6632 "(got %d, need %d)\n", vectors, msgs); 6633 pci_release_msi(dev); 6634 if (bar != -1) { 6635 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6636 ctx->ifc_msix_mem); 6637 ctx->ifc_msix_mem = NULL; 6638 } 6639 goto msi; 6640 } 6641 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6642 vectors); 6643 scctx->isc_vectors = vectors; 6644 scctx->isc_nrxqsets = rx_queues; 6645 scctx->isc_ntxqsets = tx_queues; 6646 scctx->isc_intr = IFLIB_INTR_MSIX; 6647 6648 return (vectors); 6649 } else { 6650 device_printf(dev, 6651 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6652 err); 6653 if (bar != -1) { 6654 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6655 ctx->ifc_msix_mem); 6656 ctx->ifc_msix_mem = NULL; 6657 } 6658 } 6659 6660 msi: 6661 vectors = pci_msi_count(dev); 6662 scctx->isc_nrxqsets = 1; 6663 scctx->isc_ntxqsets = 1; 6664 scctx->isc_vectors = vectors; 6665 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6666 device_printf(dev,"Using an MSI interrupt\n"); 6667 scctx->isc_intr = IFLIB_INTR_MSI; 6668 } else { 6669 scctx->isc_vectors = 1; 6670 device_printf(dev,"Using a Legacy interrupt\n"); 6671 scctx->isc_intr = IFLIB_INTR_LEGACY; 6672 } 6673 6674 return (vectors); 6675 } 6676 6677 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6678 6679 static int 6680 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6681 { 6682 int rc; 6683 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6684 struct sbuf *sb; 6685 const char *ring_state = "UNKNOWN"; 6686 6687 /* XXX needed ? */ 6688 rc = sysctl_wire_old_buffer(req, 0); 6689 MPASS(rc == 0); 6690 if (rc != 0) 6691 return (rc); 6692 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6693 MPASS(sb != NULL); 6694 if (sb == NULL) 6695 return (ENOMEM); 6696 if (state[3] <= 3) 6697 ring_state = ring_states[state[3]]; 6698 6699 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6700 state[0], state[1], state[2], ring_state); 6701 rc = sbuf_finish(sb); 6702 sbuf_delete(sb); 6703 return(rc); 6704 } 6705 6706 enum iflib_ndesc_handler { 6707 IFLIB_NTXD_HANDLER, 6708 IFLIB_NRXD_HANDLER, 6709 }; 6710 6711 static int 6712 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6713 { 6714 if_ctx_t ctx = (void *)arg1; 6715 enum iflib_ndesc_handler type = arg2; 6716 char buf[256] = {0}; 6717 qidx_t *ndesc; 6718 char *p, *next; 6719 int nqs, rc, i; 6720 6721 nqs = 8; 6722 switch(type) { 6723 case IFLIB_NTXD_HANDLER: 6724 ndesc = ctx->ifc_sysctl_ntxds; 6725 if (ctx->ifc_sctx) 6726 nqs = ctx->ifc_sctx->isc_ntxqs; 6727 break; 6728 case IFLIB_NRXD_HANDLER: 6729 ndesc = ctx->ifc_sysctl_nrxds; 6730 if (ctx->ifc_sctx) 6731 nqs = ctx->ifc_sctx->isc_nrxqs; 6732 break; 6733 default: 6734 printf("%s: unhandled type\n", __func__); 6735 return (EINVAL); 6736 } 6737 if (nqs == 0) 6738 nqs = 8; 6739 6740 for (i=0; i<8; i++) { 6741 if (i >= nqs) 6742 break; 6743 if (i) 6744 strcat(buf, ","); 6745 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6746 } 6747 6748 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6749 if (rc || req->newptr == NULL) 6750 return rc; 6751 6752 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6753 i++, p = strsep(&next, " ,")) { 6754 ndesc[i] = strtoul(p, NULL, 10); 6755 } 6756 6757 return(rc); 6758 } 6759 6760 #define NAME_BUFLEN 32 6761 static void 6762 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6763 { 6764 device_t dev = iflib_get_dev(ctx); 6765 struct sysctl_oid_list *child, *oid_list; 6766 struct sysctl_ctx_list *ctx_list; 6767 struct sysctl_oid *node; 6768 6769 ctx_list = device_get_sysctl_ctx(dev); 6770 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6771 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6772 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 6773 oid_list = SYSCTL_CHILDREN(node); 6774 6775 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6776 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6777 "driver version"); 6778 6779 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6780 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6781 "# of txqs to use, 0 => use default #"); 6782 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6783 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6784 "# of rxqs to use, 0 => use default #"); 6785 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6786 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6787 "permit #txq != #rxq"); 6788 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6789 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6790 "disable MSI-X (default 0)"); 6791 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6792 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6793 "set the RX budget"); 6794 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6795 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6796 "cause TX to abdicate instead of running to completion"); 6797 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6798 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6799 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6800 "offset to start using cores at"); 6801 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6802 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6803 "use separate cores for TX and RX"); 6804 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "use_logical_cores", 6805 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0, 6806 "try to make use of logical cores for TX and RX"); 6807 6808 /* XXX change for per-queue sizes */ 6809 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6810 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6811 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6812 "list of # of TX descriptors to use, 0 = use default #"); 6813 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6814 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6815 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6816 "list of # of RX descriptors to use, 0 = use default #"); 6817 } 6818 6819 static void 6820 iflib_add_device_sysctl_post(if_ctx_t ctx) 6821 { 6822 if_shared_ctx_t sctx = ctx->ifc_sctx; 6823 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6824 device_t dev = iflib_get_dev(ctx); 6825 struct sysctl_oid_list *child; 6826 struct sysctl_ctx_list *ctx_list; 6827 iflib_fl_t fl; 6828 iflib_txq_t txq; 6829 iflib_rxq_t rxq; 6830 int i, j; 6831 char namebuf[NAME_BUFLEN]; 6832 char *qfmt; 6833 struct sysctl_oid *queue_node, *fl_node, *node; 6834 struct sysctl_oid_list *queue_list, *fl_list; 6835 ctx_list = device_get_sysctl_ctx(dev); 6836 6837 node = ctx->ifc_sysctl_node; 6838 child = SYSCTL_CHILDREN(node); 6839 6840 if (scctx->isc_ntxqsets > 100) 6841 qfmt = "txq%03d"; 6842 else if (scctx->isc_ntxqsets > 10) 6843 qfmt = "txq%02d"; 6844 else 6845 qfmt = "txq%d"; 6846 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6847 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6848 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6849 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6850 queue_list = SYSCTL_CHILDREN(queue_node); 6851 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 6852 CTLFLAG_RD, 6853 &txq->ift_task.gt_cpu, 0, "cpu this queue is bound to"); 6854 #if MEMORY_LOGGING 6855 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6856 CTLFLAG_RD, 6857 &txq->ift_dequeued, "total mbufs freed"); 6858 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6859 CTLFLAG_RD, 6860 &txq->ift_enqueued, "total mbufs enqueued"); 6861 #endif 6862 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6863 CTLFLAG_RD, 6864 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6865 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6866 CTLFLAG_RD, 6867 &txq->ift_pullups, "# of times m_pullup was called"); 6868 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6869 CTLFLAG_RD, 6870 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6871 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6872 CTLFLAG_RD, 6873 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6874 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6875 CTLFLAG_RD, 6876 &txq->ift_map_failed, "# of times DMA map failed"); 6877 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6878 CTLFLAG_RD, 6879 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6880 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6881 CTLFLAG_RD, 6882 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6883 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6884 CTLFLAG_RD, 6885 &txq->ift_pidx, 1, "Producer Index"); 6886 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6887 CTLFLAG_RD, 6888 &txq->ift_cidx, 1, "Consumer Index"); 6889 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6890 CTLFLAG_RD, 6891 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6892 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6893 CTLFLAG_RD, 6894 &txq->ift_in_use, 1, "descriptors in use"); 6895 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6896 CTLFLAG_RD, 6897 &txq->ift_processed, "descriptors procesed for clean"); 6898 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6899 CTLFLAG_RD, 6900 &txq->ift_cleaned, "total cleaned"); 6901 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6902 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6903 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6904 mp_ring_state_handler, "A", "soft ring state"); 6905 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6906 CTLFLAG_RD, &txq->ift_br->enqueues, 6907 "# of enqueues to the mp_ring for this queue"); 6908 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6909 CTLFLAG_RD, &txq->ift_br->drops, 6910 "# of drops in the mp_ring for this queue"); 6911 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6912 CTLFLAG_RD, &txq->ift_br->starts, 6913 "# of normal consumer starts in the mp_ring for this queue"); 6914 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6915 CTLFLAG_RD, &txq->ift_br->stalls, 6916 "# of consumer stalls in the mp_ring for this queue"); 6917 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6918 CTLFLAG_RD, &txq->ift_br->restarts, 6919 "# of consumer restarts in the mp_ring for this queue"); 6920 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6921 CTLFLAG_RD, &txq->ift_br->abdications, 6922 "# of consumer abdications in the mp_ring for this queue"); 6923 } 6924 6925 if (scctx->isc_nrxqsets > 100) 6926 qfmt = "rxq%03d"; 6927 else if (scctx->isc_nrxqsets > 10) 6928 qfmt = "rxq%02d"; 6929 else 6930 qfmt = "rxq%d"; 6931 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6932 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6933 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6934 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6935 queue_list = SYSCTL_CHILDREN(queue_node); 6936 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 6937 CTLFLAG_RD, 6938 &rxq->ifr_task.gt_cpu, 0, "cpu this queue is bound to"); 6939 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6940 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6941 CTLFLAG_RD, 6942 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6943 } 6944 6945 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6946 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6947 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6948 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 6949 fl_list = SYSCTL_CHILDREN(fl_node); 6950 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6951 CTLFLAG_RD, 6952 &fl->ifl_pidx, 1, "Producer Index"); 6953 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6954 CTLFLAG_RD, 6955 &fl->ifl_cidx, 1, "Consumer Index"); 6956 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6957 CTLFLAG_RD, 6958 &fl->ifl_credits, 1, "credits available"); 6959 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 6960 CTLFLAG_RD, 6961 &fl->ifl_buf_size, 1, "buffer size"); 6962 #if MEMORY_LOGGING 6963 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6964 CTLFLAG_RD, 6965 &fl->ifl_m_enqueued, "mbufs allocated"); 6966 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6967 CTLFLAG_RD, 6968 &fl->ifl_m_dequeued, "mbufs freed"); 6969 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6970 CTLFLAG_RD, 6971 &fl->ifl_cl_enqueued, "clusters allocated"); 6972 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6973 CTLFLAG_RD, 6974 &fl->ifl_cl_dequeued, "clusters freed"); 6975 #endif 6976 } 6977 } 6978 6979 } 6980 6981 void 6982 iflib_request_reset(if_ctx_t ctx) 6983 { 6984 6985 STATE_LOCK(ctx); 6986 ctx->ifc_flags |= IFC_DO_RESET; 6987 STATE_UNLOCK(ctx); 6988 } 6989 6990 #ifndef __NO_STRICT_ALIGNMENT 6991 static struct mbuf * 6992 iflib_fixup_rx(struct mbuf *m) 6993 { 6994 struct mbuf *n; 6995 6996 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6997 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6998 m->m_data += ETHER_HDR_LEN; 6999 n = m; 7000 } else { 7001 MGETHDR(n, M_NOWAIT, MT_DATA); 7002 if (n == NULL) { 7003 m_freem(m); 7004 return (NULL); 7005 } 7006 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 7007 m->m_data += ETHER_HDR_LEN; 7008 m->m_len -= ETHER_HDR_LEN; 7009 n->m_len = ETHER_HDR_LEN; 7010 M_MOVE_PKTHDR(n, m); 7011 n->m_next = m; 7012 } 7013 return (n); 7014 } 7015 #endif 7016 7017 #ifdef DEBUGNET 7018 static void 7019 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 7020 { 7021 if_ctx_t ctx; 7022 7023 ctx = if_getsoftc(ifp); 7024 CTX_LOCK(ctx); 7025 *nrxr = NRXQSETS(ctx); 7026 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 7027 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 7028 CTX_UNLOCK(ctx); 7029 } 7030 7031 static void 7032 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 7033 { 7034 if_ctx_t ctx; 7035 if_softc_ctx_t scctx; 7036 iflib_fl_t fl; 7037 iflib_rxq_t rxq; 7038 int i, j; 7039 7040 ctx = if_getsoftc(ifp); 7041 scctx = &ctx->ifc_softc_ctx; 7042 7043 switch (event) { 7044 case DEBUGNET_START: 7045 for (i = 0; i < scctx->isc_nrxqsets; i++) { 7046 rxq = &ctx->ifc_rxqs[i]; 7047 for (j = 0; j < rxq->ifr_nfl; j++) { 7048 fl = rxq->ifr_fl; 7049 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 7050 } 7051 } 7052 iflib_no_tx_batch = 1; 7053 break; 7054 default: 7055 break; 7056 } 7057 } 7058 7059 static int 7060 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 7061 { 7062 if_ctx_t ctx; 7063 iflib_txq_t txq; 7064 int error; 7065 7066 ctx = if_getsoftc(ifp); 7067 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7068 IFF_DRV_RUNNING) 7069 return (EBUSY); 7070 7071 txq = &ctx->ifc_txqs[0]; 7072 error = iflib_encap(txq, &m); 7073 if (error == 0) 7074 (void)iflib_txd_db_check(txq, true); 7075 return (error); 7076 } 7077 7078 static int 7079 iflib_debugnet_poll(if_t ifp, int count) 7080 { 7081 struct epoch_tracker et; 7082 if_ctx_t ctx; 7083 if_softc_ctx_t scctx; 7084 iflib_txq_t txq; 7085 int i; 7086 7087 ctx = if_getsoftc(ifp); 7088 scctx = &ctx->ifc_softc_ctx; 7089 7090 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7091 IFF_DRV_RUNNING) 7092 return (EBUSY); 7093 7094 txq = &ctx->ifc_txqs[0]; 7095 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 7096 7097 NET_EPOCH_ENTER(et); 7098 for (i = 0; i < scctx->isc_nrxqsets; i++) 7099 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 7100 NET_EPOCH_EXIT(et); 7101 return (0); 7102 } 7103 #endif /* DEBUGNET */ 7104