1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/jail.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/md5.h> 44 #include <sys/mutex.h> 45 #include <sys/module.h> 46 #include <sys/kobj.h> 47 #include <sys/rman.h> 48 #include <sys/proc.h> 49 #include <sys/sbuf.h> 50 #include <sys/smp.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/syslog.h> 55 #include <sys/taskqueue.h> 56 #include <sys/limits.h> 57 58 #include <net/if.h> 59 #include <net/if_var.h> 60 #include <net/if_types.h> 61 #include <net/if_media.h> 62 #include <net/bpf.h> 63 #include <net/ethernet.h> 64 #include <net/mp_ring.h> 65 #include <net/vnet.h> 66 67 #include <netinet/in.h> 68 #include <netinet/in_pcb.h> 69 #include <netinet/tcp_lro.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/if_ether.h> 72 #include <netinet/ip.h> 73 #include <netinet/ip6.h> 74 #include <netinet/tcp.h> 75 #include <netinet/ip_var.h> 76 #include <netinet/netdump/netdump.h> 77 #include <netinet6/ip6_var.h> 78 79 #include <machine/bus.h> 80 #include <machine/in_cksum.h> 81 82 #include <vm/vm.h> 83 #include <vm/pmap.h> 84 85 #include <dev/led/led.h> 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pci_private.h> 89 90 #include <net/iflib.h> 91 #include <net/iflib_private.h> 92 93 #include "ifdi_if.h" 94 95 #if defined(__i386__) || defined(__amd64__) 96 #include <sys/memdesc.h> 97 #include <machine/bus.h> 98 #include <machine/md_var.h> 99 #include <machine/specialreg.h> 100 #include <x86/include/busdma_impl.h> 101 #include <x86/iommu/busdma_dmar.h> 102 #endif 103 104 #include <sys/bitstring.h> 105 /* 106 * enable accounting of every mbuf as it comes in to and goes out of 107 * iflib's software descriptor references 108 */ 109 #define MEMORY_LOGGING 0 110 /* 111 * Enable mbuf vectors for compressing long mbuf chains 112 */ 113 114 /* 115 * NB: 116 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 117 * we prefetch needs to be determined by the time spent in m_free vis a vis 118 * the cost of a prefetch. This will of course vary based on the workload: 119 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 120 * is quite expensive, thus suggesting very little prefetch. 121 * - small packet forwarding which is just returning a single mbuf to 122 * UMA will typically be very fast vis a vis the cost of a memory 123 * access. 124 */ 125 126 127 /* 128 * File organization: 129 * - private structures 130 * - iflib private utility functions 131 * - ifnet functions 132 * - vlan registry and other exported functions 133 * - iflib public core functions 134 * 135 * 136 */ 137 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 138 139 struct iflib_txq; 140 typedef struct iflib_txq *iflib_txq_t; 141 struct iflib_rxq; 142 typedef struct iflib_rxq *iflib_rxq_t; 143 struct iflib_fl; 144 typedef struct iflib_fl *iflib_fl_t; 145 146 struct iflib_ctx; 147 148 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 149 150 typedef struct iflib_filter_info { 151 driver_filter_t *ifi_filter; 152 void *ifi_filter_arg; 153 struct grouptask *ifi_task; 154 void *ifi_ctx; 155 } *iflib_filter_info_t; 156 157 struct iflib_ctx { 158 KOBJ_FIELDS; 159 /* 160 * Pointer to hardware driver's softc 161 */ 162 void *ifc_softc; 163 device_t ifc_dev; 164 if_t ifc_ifp; 165 166 cpuset_t ifc_cpus; 167 if_shared_ctx_t ifc_sctx; 168 struct if_softc_ctx ifc_softc_ctx; 169 170 struct sx ifc_ctx_sx; 171 struct mtx ifc_state_mtx; 172 173 uint16_t ifc_nhwtxqs; 174 175 iflib_txq_t ifc_txqs; 176 iflib_rxq_t ifc_rxqs; 177 uint32_t ifc_if_flags; 178 uint32_t ifc_flags; 179 uint32_t ifc_max_fl_buf_size; 180 int ifc_in_detach; 181 182 int ifc_link_state; 183 int ifc_link_irq; 184 int ifc_watchdog_events; 185 struct cdev *ifc_led_dev; 186 struct resource *ifc_msix_mem; 187 188 struct if_irq ifc_legacy_irq; 189 struct grouptask ifc_admin_task; 190 struct grouptask ifc_vflr_task; 191 struct iflib_filter_info ifc_filter_info; 192 struct ifmedia ifc_media; 193 194 struct sysctl_oid *ifc_sysctl_node; 195 uint16_t ifc_sysctl_ntxqs; 196 uint16_t ifc_sysctl_nrxqs; 197 uint16_t ifc_sysctl_qs_eq_override; 198 uint16_t ifc_sysctl_rx_budget; 199 200 qidx_t ifc_sysctl_ntxds[8]; 201 qidx_t ifc_sysctl_nrxds[8]; 202 struct if_txrx ifc_txrx; 203 #define isc_txd_encap ifc_txrx.ift_txd_encap 204 #define isc_txd_flush ifc_txrx.ift_txd_flush 205 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 206 #define isc_rxd_available ifc_txrx.ift_rxd_available 207 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 208 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 209 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 210 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 211 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 212 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 213 eventhandler_tag ifc_vlan_attach_event; 214 eventhandler_tag ifc_vlan_detach_event; 215 uint8_t ifc_mac[ETHER_ADDR_LEN]; 216 char ifc_mtx_name[16]; 217 }; 218 219 220 void * 221 iflib_get_softc(if_ctx_t ctx) 222 { 223 224 return (ctx->ifc_softc); 225 } 226 227 device_t 228 iflib_get_dev(if_ctx_t ctx) 229 { 230 231 return (ctx->ifc_dev); 232 } 233 234 if_t 235 iflib_get_ifp(if_ctx_t ctx) 236 { 237 238 return (ctx->ifc_ifp); 239 } 240 241 struct ifmedia * 242 iflib_get_media(if_ctx_t ctx) 243 { 244 245 return (&ctx->ifc_media); 246 } 247 248 uint32_t 249 iflib_get_flags(if_ctx_t ctx) 250 { 251 return (ctx->ifc_flags); 252 } 253 254 void 255 iflib_set_detach(if_ctx_t ctx) 256 { 257 ctx->ifc_in_detach = 1; 258 } 259 260 void 261 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 262 { 263 264 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 265 } 266 267 if_softc_ctx_t 268 iflib_get_softc_ctx(if_ctx_t ctx) 269 { 270 271 return (&ctx->ifc_softc_ctx); 272 } 273 274 if_shared_ctx_t 275 iflib_get_sctx(if_ctx_t ctx) 276 { 277 278 return (ctx->ifc_sctx); 279 } 280 281 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 282 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 283 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 284 285 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 286 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 287 288 #define RX_SW_DESC_MAP_CREATED (1 << 0) 289 #define TX_SW_DESC_MAP_CREATED (1 << 1) 290 #define RX_SW_DESC_INUSE (1 << 3) 291 #define TX_SW_DESC_MAPPED (1 << 4) 292 293 #define M_TOOBIG M_PROTO1 294 295 typedef struct iflib_sw_rx_desc_array { 296 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 297 struct mbuf **ifsd_m; /* pkthdr mbufs */ 298 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 299 uint8_t *ifsd_flags; 300 } iflib_rxsd_array_t; 301 302 typedef struct iflib_sw_tx_desc_array { 303 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 304 struct mbuf **ifsd_m; /* pkthdr mbufs */ 305 uint8_t *ifsd_flags; 306 } if_txsd_vec_t; 307 308 309 /* magic number that should be high enough for any hardware */ 310 #define IFLIB_MAX_TX_SEGS 128 311 /* bnxt supports 64 with hardware LRO enabled */ 312 #define IFLIB_MAX_RX_SEGS 64 313 #define IFLIB_RX_COPY_THRESH 128 314 #define IFLIB_MAX_RX_REFRESH 32 315 /* The minimum descriptors per second before we start coalescing */ 316 #define IFLIB_MIN_DESC_SEC 16384 317 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 318 #define IFLIB_QUEUE_IDLE 0 319 #define IFLIB_QUEUE_HUNG 1 320 #define IFLIB_QUEUE_WORKING 2 321 /* maximum number of txqs that can share an rx interrupt */ 322 #define IFLIB_MAX_TX_SHARED_INTR 4 323 324 /* this should really scale with ring size - this is a fairly arbitrary value */ 325 #define TX_BATCH_SIZE 32 326 327 #define IFLIB_RESTART_BUDGET 8 328 329 330 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 331 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 332 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 333 struct iflib_txq { 334 qidx_t ift_in_use; 335 qidx_t ift_cidx; 336 qidx_t ift_cidx_processed; 337 qidx_t ift_pidx; 338 uint8_t ift_gen; 339 uint8_t ift_br_offset; 340 uint16_t ift_npending; 341 uint16_t ift_db_pending; 342 uint16_t ift_rs_pending; 343 /* implicit pad */ 344 uint8_t ift_txd_size[8]; 345 uint64_t ift_processed; 346 uint64_t ift_cleaned; 347 uint64_t ift_cleaned_prev; 348 #if MEMORY_LOGGING 349 uint64_t ift_enqueued; 350 uint64_t ift_dequeued; 351 #endif 352 uint64_t ift_no_tx_dma_setup; 353 uint64_t ift_no_desc_avail; 354 uint64_t ift_mbuf_defrag_failed; 355 uint64_t ift_mbuf_defrag; 356 uint64_t ift_map_failed; 357 uint64_t ift_txd_encap_efbig; 358 uint64_t ift_pullups; 359 360 struct mtx ift_mtx; 361 struct mtx ift_db_mtx; 362 363 /* constant values */ 364 if_ctx_t ift_ctx; 365 struct ifmp_ring *ift_br; 366 struct grouptask ift_task; 367 qidx_t ift_size; 368 uint16_t ift_id; 369 struct callout ift_timer; 370 371 if_txsd_vec_t ift_sds; 372 uint8_t ift_qstatus; 373 uint8_t ift_closed; 374 uint8_t ift_update_freq; 375 struct iflib_filter_info ift_filter_info; 376 bus_dma_tag_t ift_desc_tag; 377 bus_dma_tag_t ift_tso_desc_tag; 378 iflib_dma_info_t ift_ifdi; 379 #define MTX_NAME_LEN 16 380 char ift_mtx_name[MTX_NAME_LEN]; 381 char ift_db_mtx_name[MTX_NAME_LEN]; 382 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 383 #ifdef IFLIB_DIAGNOSTICS 384 uint64_t ift_cpu_exec_count[256]; 385 #endif 386 } __aligned(CACHE_LINE_SIZE); 387 388 struct iflib_fl { 389 qidx_t ifl_cidx; 390 qidx_t ifl_pidx; 391 qidx_t ifl_credits; 392 uint8_t ifl_gen; 393 uint8_t ifl_rxd_size; 394 #if MEMORY_LOGGING 395 uint64_t ifl_m_enqueued; 396 uint64_t ifl_m_dequeued; 397 uint64_t ifl_cl_enqueued; 398 uint64_t ifl_cl_dequeued; 399 #endif 400 /* implicit pad */ 401 402 bitstr_t *ifl_rx_bitmap; 403 qidx_t ifl_fragidx; 404 /* constant */ 405 qidx_t ifl_size; 406 uint16_t ifl_buf_size; 407 uint16_t ifl_cltype; 408 uma_zone_t ifl_zone; 409 iflib_rxsd_array_t ifl_sds; 410 iflib_rxq_t ifl_rxq; 411 uint8_t ifl_id; 412 bus_dma_tag_t ifl_desc_tag; 413 iflib_dma_info_t ifl_ifdi; 414 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 415 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 416 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 417 } __aligned(CACHE_LINE_SIZE); 418 419 static inline qidx_t 420 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 421 { 422 qidx_t used; 423 424 if (pidx > cidx) 425 used = pidx - cidx; 426 else if (pidx < cidx) 427 used = size - cidx + pidx; 428 else if (gen == 0 && pidx == cidx) 429 used = 0; 430 else if (gen == 1 && pidx == cidx) 431 used = size; 432 else 433 panic("bad state"); 434 435 return (used); 436 } 437 438 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 439 440 #define IDXDIFF(head, tail, wrap) \ 441 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 442 443 struct iflib_rxq { 444 /* If there is a separate completion queue - 445 * these are the cq cidx and pidx. Otherwise 446 * these are unused. 447 */ 448 qidx_t ifr_size; 449 qidx_t ifr_cq_cidx; 450 qidx_t ifr_cq_pidx; 451 uint8_t ifr_cq_gen; 452 uint8_t ifr_fl_offset; 453 454 if_ctx_t ifr_ctx; 455 iflib_fl_t ifr_fl; 456 uint64_t ifr_rx_irq; 457 uint16_t ifr_id; 458 uint8_t ifr_lro_enabled; 459 uint8_t ifr_nfl; 460 uint8_t ifr_ntxqirq; 461 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 462 struct lro_ctrl ifr_lc; 463 struct grouptask ifr_task; 464 struct iflib_filter_info ifr_filter_info; 465 iflib_dma_info_t ifr_ifdi; 466 467 /* dynamically allocate if any drivers need a value substantially larger than this */ 468 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 469 #ifdef IFLIB_DIAGNOSTICS 470 uint64_t ifr_cpu_exec_count[256]; 471 #endif 472 } __aligned(CACHE_LINE_SIZE); 473 474 typedef struct if_rxsd { 475 caddr_t *ifsd_cl; 476 struct mbuf **ifsd_m; 477 iflib_fl_t ifsd_fl; 478 qidx_t ifsd_cidx; 479 } *if_rxsd_t; 480 481 /* multiple of word size */ 482 #ifdef __LP64__ 483 #define PKT_INFO_SIZE 6 484 #define RXD_INFO_SIZE 5 485 #define PKT_TYPE uint64_t 486 #else 487 #define PKT_INFO_SIZE 11 488 #define RXD_INFO_SIZE 8 489 #define PKT_TYPE uint32_t 490 #endif 491 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 492 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 493 494 typedef struct if_pkt_info_pad { 495 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 496 } *if_pkt_info_pad_t; 497 typedef struct if_rxd_info_pad { 498 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 499 } *if_rxd_info_pad_t; 500 501 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 502 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 503 504 505 static inline void 506 pkt_info_zero(if_pkt_info_t pi) 507 { 508 if_pkt_info_pad_t pi_pad; 509 510 pi_pad = (if_pkt_info_pad_t)pi; 511 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 512 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 513 #ifndef __LP64__ 514 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 515 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 516 #endif 517 } 518 519 static device_method_t iflib_pseudo_methods[] = { 520 DEVMETHOD(device_attach, noop_attach), 521 DEVMETHOD(device_detach, iflib_pseudo_detach), 522 DEVMETHOD_END 523 }; 524 525 driver_t iflib_pseudodriver = { 526 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 527 }; 528 529 static inline void 530 rxd_info_zero(if_rxd_info_t ri) 531 { 532 if_rxd_info_pad_t ri_pad; 533 int i; 534 535 ri_pad = (if_rxd_info_pad_t)ri; 536 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 537 ri_pad->rxd_val[i] = 0; 538 ri_pad->rxd_val[i+1] = 0; 539 ri_pad->rxd_val[i+2] = 0; 540 ri_pad->rxd_val[i+3] = 0; 541 } 542 #ifdef __LP64__ 543 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 544 #endif 545 } 546 547 /* 548 * Only allow a single packet to take up most 1/nth of the tx ring 549 */ 550 #define MAX_SINGLE_PACKET_FRACTION 12 551 #define IF_BAD_DMA (bus_addr_t)-1 552 553 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 554 555 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 556 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 557 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 558 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 559 560 561 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 562 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 563 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 564 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 565 566 567 568 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 569 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 570 571 572 /* Our boot-time initialization hook */ 573 static int iflib_module_event_handler(module_t, int, void *); 574 575 static moduledata_t iflib_moduledata = { 576 "iflib", 577 iflib_module_event_handler, 578 NULL 579 }; 580 581 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 582 MODULE_VERSION(iflib, 1); 583 584 MODULE_DEPEND(iflib, pci, 1, 1, 1); 585 MODULE_DEPEND(iflib, ether, 1, 1, 1); 586 587 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 588 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 589 590 #ifndef IFLIB_DEBUG_COUNTERS 591 #ifdef INVARIANTS 592 #define IFLIB_DEBUG_COUNTERS 1 593 #else 594 #define IFLIB_DEBUG_COUNTERS 0 595 #endif /* !INVARIANTS */ 596 #endif 597 598 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 599 "iflib driver parameters"); 600 601 /* 602 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 603 */ 604 static int iflib_min_tx_latency = 0; 605 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 606 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 607 static int iflib_no_tx_batch = 0; 608 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 609 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 610 611 612 #if IFLIB_DEBUG_COUNTERS 613 614 static int iflib_tx_seen; 615 static int iflib_tx_sent; 616 static int iflib_tx_encap; 617 static int iflib_rx_allocs; 618 static int iflib_fl_refills; 619 static int iflib_fl_refills_large; 620 static int iflib_tx_frees; 621 622 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 623 &iflib_tx_seen, 0, "# tx mbufs seen"); 624 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 625 &iflib_tx_sent, 0, "# tx mbufs sent"); 626 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 627 &iflib_tx_encap, 0, "# tx mbufs encapped"); 628 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 629 &iflib_tx_frees, 0, "# tx frees"); 630 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 631 &iflib_rx_allocs, 0, "# rx allocations"); 632 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 633 &iflib_fl_refills, 0, "# refills"); 634 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 635 &iflib_fl_refills_large, 0, "# large refills"); 636 637 638 static int iflib_txq_drain_flushing; 639 static int iflib_txq_drain_oactive; 640 static int iflib_txq_drain_notready; 641 static int iflib_txq_drain_encapfail; 642 643 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 644 &iflib_txq_drain_flushing, 0, "# drain flushes"); 645 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 646 &iflib_txq_drain_oactive, 0, "# drain oactives"); 647 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 648 &iflib_txq_drain_notready, 0, "# drain notready"); 649 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 650 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 651 652 653 static int iflib_encap_load_mbuf_fail; 654 static int iflib_encap_pad_mbuf_fail; 655 static int iflib_encap_txq_avail_fail; 656 static int iflib_encap_txd_encap_fail; 657 658 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 659 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 661 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 663 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 665 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 666 667 static int iflib_task_fn_rxs; 668 static int iflib_rx_intr_enables; 669 static int iflib_fast_intrs; 670 static int iflib_intr_link; 671 static int iflib_intr_msix; 672 static int iflib_rx_unavail; 673 static int iflib_rx_ctx_inactive; 674 static int iflib_rx_zero_len; 675 static int iflib_rx_if_input; 676 static int iflib_rx_mbuf_null; 677 static int iflib_rxd_flush; 678 679 static int iflib_verbose_debug; 680 681 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 682 &iflib_intr_link, 0, "# intr link calls"); 683 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 684 &iflib_intr_msix, 0, "# intr msix calls"); 685 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 686 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 687 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 688 &iflib_rx_intr_enables, 0, "# rx intr enables"); 689 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 690 &iflib_fast_intrs, 0, "# fast_intr calls"); 691 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 692 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 693 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 694 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 695 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 696 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 697 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 698 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 699 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 700 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 701 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 702 &iflib_rxd_flush, 0, "# times rxd_flush called"); 703 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 704 &iflib_verbose_debug, 0, "enable verbose debugging"); 705 706 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 707 static void 708 iflib_debug_reset(void) 709 { 710 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 711 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 712 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 713 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 714 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 715 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 716 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 717 iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 718 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 719 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 720 } 721 722 #else 723 #define DBG_COUNTER_INC(name) 724 static void iflib_debug_reset(void) {} 725 #endif 726 727 #define IFLIB_DEBUG 0 728 729 static void iflib_tx_structures_free(if_ctx_t ctx); 730 static void iflib_rx_structures_free(if_ctx_t ctx); 731 static int iflib_queues_alloc(if_ctx_t ctx); 732 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 733 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 734 static int iflib_qset_structures_setup(if_ctx_t ctx); 735 static int iflib_msix_init(if_ctx_t ctx); 736 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 737 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 738 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 739 static int iflib_register(if_ctx_t); 740 static void iflib_init_locked(if_ctx_t ctx); 741 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 742 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 743 static void iflib_ifmp_purge(iflib_txq_t txq); 744 static void _iflib_pre_assert(if_softc_ctx_t scctx); 745 static void iflib_if_init_locked(if_ctx_t ctx); 746 #ifndef __NO_STRICT_ALIGNMENT 747 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 748 #endif 749 750 NETDUMP_DEFINE(iflib); 751 752 #ifdef DEV_NETMAP 753 #include <sys/selinfo.h> 754 #include <net/netmap.h> 755 #include <dev/netmap/netmap_kern.h> 756 757 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 758 759 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 760 761 /* 762 * device-specific sysctl variables: 763 * 764 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 765 * During regular operations the CRC is stripped, but on some 766 * hardware reception of frames not multiple of 64 is slower, 767 * so using crcstrip=0 helps in benchmarks. 768 * 769 * iflib_rx_miss, iflib_rx_miss_bufs: 770 * count packets that might be missed due to lost interrupts. 771 */ 772 SYSCTL_DECL(_dev_netmap); 773 /* 774 * The xl driver by default strips CRCs and we do not override it. 775 */ 776 777 int iflib_crcstrip = 1; 778 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 779 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 780 781 int iflib_rx_miss, iflib_rx_miss_bufs; 782 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 783 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 784 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 785 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 786 787 /* 788 * Register/unregister. We are already under netmap lock. 789 * Only called on the first register or the last unregister. 790 */ 791 static int 792 iflib_netmap_register(struct netmap_adapter *na, int onoff) 793 { 794 struct ifnet *ifp = na->ifp; 795 if_ctx_t ctx = ifp->if_softc; 796 int status; 797 798 CTX_LOCK(ctx); 799 IFDI_INTR_DISABLE(ctx); 800 801 /* Tell the stack that the interface is no longer active */ 802 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 803 804 if (!CTX_IS_VF(ctx)) 805 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 806 807 /* enable or disable flags and callbacks in na and ifp */ 808 if (onoff) { 809 nm_set_native_flags(na); 810 } else { 811 nm_clear_native_flags(na); 812 } 813 iflib_stop(ctx); 814 iflib_init_locked(ctx); 815 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 816 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 817 if (status) 818 nm_clear_native_flags(na); 819 CTX_UNLOCK(ctx); 820 return (status); 821 } 822 823 static int 824 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 825 { 826 struct netmap_adapter *na = kring->na; 827 u_int const lim = kring->nkr_num_slots - 1; 828 u_int head = kring->rhead; 829 struct netmap_ring *ring = kring->ring; 830 bus_dmamap_t *map; 831 struct if_rxd_update iru; 832 if_ctx_t ctx = rxq->ifr_ctx; 833 iflib_fl_t fl = &rxq->ifr_fl[0]; 834 uint32_t refill_pidx, nic_i; 835 836 if (nm_i == head && __predict_true(!init)) 837 return 0; 838 iru_init(&iru, rxq, 0 /* flid */); 839 map = fl->ifl_sds.ifsd_map; 840 refill_pidx = netmap_idx_k2n(kring, nm_i); 841 /* 842 * IMPORTANT: we must leave one free slot in the ring, 843 * so move head back by one unit 844 */ 845 head = nm_prev(head, lim); 846 nic_i = UINT_MAX; 847 while (nm_i != head) { 848 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 849 struct netmap_slot *slot = &ring->slot[nm_i]; 850 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 851 uint32_t nic_i_dma = refill_pidx; 852 nic_i = netmap_idx_k2n(kring, nm_i); 853 854 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 855 856 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 857 return netmap_ring_reinit(kring); 858 859 fl->ifl_vm_addrs[tmp_pidx] = addr; 860 if (__predict_false(init) && map) { 861 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 862 } else if (map && (slot->flags & NS_BUF_CHANGED)) { 863 /* buffer has changed, reload map */ 864 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 865 } 866 slot->flags &= ~NS_BUF_CHANGED; 867 868 nm_i = nm_next(nm_i, lim); 869 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 870 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 871 continue; 872 873 iru.iru_pidx = refill_pidx; 874 iru.iru_count = tmp_pidx+1; 875 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 876 877 refill_pidx = nic_i; 878 if (map == NULL) 879 continue; 880 881 for (int n = 0; n < iru.iru_count; n++) { 882 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma], 883 BUS_DMASYNC_PREREAD); 884 /* XXX - change this to not use the netmap func*/ 885 nic_i_dma = nm_next(nic_i_dma, lim); 886 } 887 } 888 } 889 kring->nr_hwcur = head; 890 891 if (map) 892 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 893 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 894 if (__predict_true(nic_i != UINT_MAX)) 895 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 896 return (0); 897 } 898 899 /* 900 * Reconcile kernel and user view of the transmit ring. 901 * 902 * All information is in the kring. 903 * Userspace wants to send packets up to the one before kring->rhead, 904 * kernel knows kring->nr_hwcur is the first unsent packet. 905 * 906 * Here we push packets out (as many as possible), and possibly 907 * reclaim buffers from previously completed transmission. 908 * 909 * The caller (netmap) guarantees that there is only one instance 910 * running at any time. Any interference with other driver 911 * methods should be handled by the individual drivers. 912 */ 913 static int 914 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 915 { 916 struct netmap_adapter *na = kring->na; 917 struct ifnet *ifp = na->ifp; 918 struct netmap_ring *ring = kring->ring; 919 u_int nm_i; /* index into the netmap ring */ 920 u_int nic_i; /* index into the NIC ring */ 921 u_int n; 922 u_int const lim = kring->nkr_num_slots - 1; 923 u_int const head = kring->rhead; 924 struct if_pkt_info pi; 925 926 /* 927 * interrupts on every tx packet are expensive so request 928 * them every half ring, or where NS_REPORT is set 929 */ 930 u_int report_frequency = kring->nkr_num_slots >> 1; 931 /* device-specific */ 932 if_ctx_t ctx = ifp->if_softc; 933 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 934 935 if (txq->ift_sds.ifsd_map) 936 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 937 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 938 939 940 /* 941 * First part: process new packets to send. 942 * nm_i is the current index in the netmap ring, 943 * nic_i is the corresponding index in the NIC ring. 944 * 945 * If we have packets to send (nm_i != head) 946 * iterate over the netmap ring, fetch length and update 947 * the corresponding slot in the NIC ring. Some drivers also 948 * need to update the buffer's physical address in the NIC slot 949 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 950 * 951 * The netmap_reload_map() calls is especially expensive, 952 * even when (as in this case) the tag is 0, so do only 953 * when the buffer has actually changed. 954 * 955 * If possible do not set the report/intr bit on all slots, 956 * but only a few times per ring or when NS_REPORT is set. 957 * 958 * Finally, on 10G and faster drivers, it might be useful 959 * to prefetch the next slot and txr entry. 960 */ 961 962 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 963 if (nm_i != head) { /* we have new packets to send */ 964 pkt_info_zero(&pi); 965 pi.ipi_segs = txq->ift_segs; 966 pi.ipi_qsidx = kring->ring_id; 967 nic_i = netmap_idx_k2n(kring, nm_i); 968 969 __builtin_prefetch(&ring->slot[nm_i]); 970 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 971 if (txq->ift_sds.ifsd_map) 972 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 973 974 for (n = 0; nm_i != head; n++) { 975 struct netmap_slot *slot = &ring->slot[nm_i]; 976 u_int len = slot->len; 977 uint64_t paddr; 978 void *addr = PNMB(na, slot, &paddr); 979 int flags = (slot->flags & NS_REPORT || 980 nic_i == 0 || nic_i == report_frequency) ? 981 IPI_TX_INTR : 0; 982 983 /* device-specific */ 984 pi.ipi_len = len; 985 pi.ipi_segs[0].ds_addr = paddr; 986 pi.ipi_segs[0].ds_len = len; 987 pi.ipi_nsegs = 1; 988 pi.ipi_ndescs = 0; 989 pi.ipi_pidx = nic_i; 990 pi.ipi_flags = flags; 991 992 /* Fill the slot in the NIC ring. */ 993 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 994 995 /* prefetch for next round */ 996 __builtin_prefetch(&ring->slot[nm_i + 1]); 997 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 998 if (txq->ift_sds.ifsd_map) { 999 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1000 1001 NM_CHECK_ADDR_LEN(na, addr, len); 1002 1003 if (slot->flags & NS_BUF_CHANGED) { 1004 /* buffer has changed, reload map */ 1005 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 1006 } 1007 /* make sure changes to the buffer are synced */ 1008 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 1009 BUS_DMASYNC_PREWRITE); 1010 } 1011 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1012 nm_i = nm_next(nm_i, lim); 1013 nic_i = nm_next(nic_i, lim); 1014 } 1015 kring->nr_hwcur = head; 1016 1017 /* synchronize the NIC ring */ 1018 if (txq->ift_sds.ifsd_map) 1019 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 1020 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1021 1022 /* (re)start the tx unit up to slot nic_i (excluded) */ 1023 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1024 } 1025 1026 /* 1027 * Second part: reclaim buffers for completed transmissions. 1028 * 1029 * If there are unclaimed buffers, attempt to reclaim them. 1030 * If none are reclaimed, and TX IRQs are not in use, do an initial 1031 * minimal delay, then trigger the tx handler which will spin in the 1032 * group task queue. 1033 */ 1034 if (kring->nr_hwtail != nm_prev(head, lim)) { 1035 if (iflib_tx_credits_update(ctx, txq)) { 1036 /* some tx completed, increment avail */ 1037 nic_i = txq->ift_cidx_processed; 1038 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1039 } 1040 else { 1041 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1042 DELAY(1); 1043 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txq->ift_id].ift_task); 1044 } 1045 } 1046 } 1047 return (0); 1048 } 1049 1050 /* 1051 * Reconcile kernel and user view of the receive ring. 1052 * Same as for the txsync, this routine must be efficient. 1053 * The caller guarantees a single invocations, but races against 1054 * the rest of the driver should be handled here. 1055 * 1056 * On call, kring->rhead is the first packet that userspace wants 1057 * to keep, and kring->rcur is the wakeup point. 1058 * The kernel has previously reported packets up to kring->rtail. 1059 * 1060 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1061 * of whether or not we received an interrupt. 1062 */ 1063 static int 1064 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1065 { 1066 struct netmap_adapter *na = kring->na; 1067 struct netmap_ring *ring = kring->ring; 1068 uint32_t nm_i; /* index into the netmap ring */ 1069 uint32_t nic_i; /* index into the NIC ring */ 1070 u_int i, n; 1071 u_int const lim = kring->nkr_num_slots - 1; 1072 u_int const head = netmap_idx_n2k(kring, kring->rhead); 1073 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1074 struct if_rxd_info ri; 1075 1076 struct ifnet *ifp = na->ifp; 1077 if_ctx_t ctx = ifp->if_softc; 1078 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1079 iflib_fl_t fl = rxq->ifr_fl; 1080 if (head > lim) 1081 return netmap_ring_reinit(kring); 1082 1083 /* XXX check sync modes */ 1084 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1085 if (fl->ifl_sds.ifsd_map == NULL) 1086 continue; 1087 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 1088 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1089 } 1090 /* 1091 * First part: import newly received packets. 1092 * 1093 * nm_i is the index of the next free slot in the netmap ring, 1094 * nic_i is the index of the next received packet in the NIC ring, 1095 * and they may differ in case if_init() has been called while 1096 * in netmap mode. For the receive ring we have 1097 * 1098 * nic_i = rxr->next_check; 1099 * nm_i = kring->nr_hwtail (previous) 1100 * and 1101 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1102 * 1103 * rxr->next_check is set to 0 on a ring reinit 1104 */ 1105 if (netmap_no_pendintr || force_update) { 1106 int crclen = iflib_crcstrip ? 0 : 4; 1107 int error, avail; 1108 1109 for (i = 0; i < rxq->ifr_nfl; i++) { 1110 fl = &rxq->ifr_fl[i]; 1111 nic_i = fl->ifl_cidx; 1112 nm_i = netmap_idx_n2k(kring, nic_i); 1113 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 1114 for (n = 0; avail > 0; n++, avail--) { 1115 rxd_info_zero(&ri); 1116 ri.iri_frags = rxq->ifr_frags; 1117 ri.iri_qsidx = kring->ring_id; 1118 ri.iri_ifp = ctx->ifc_ifp; 1119 ri.iri_cidx = nic_i; 1120 1121 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1122 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1123 ring->slot[nm_i].flags = 0; 1124 if (fl->ifl_sds.ifsd_map) 1125 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1126 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1127 nm_i = nm_next(nm_i, lim); 1128 nic_i = nm_next(nic_i, lim); 1129 } 1130 if (n) { /* update the state variables */ 1131 if (netmap_no_pendintr && !force_update) { 1132 /* diagnostics */ 1133 iflib_rx_miss ++; 1134 iflib_rx_miss_bufs += n; 1135 } 1136 fl->ifl_cidx = nic_i; 1137 kring->nr_hwtail = netmap_idx_k2n(kring, nm_i); 1138 } 1139 kring->nr_kflags &= ~NKR_PENDINTR; 1140 } 1141 } 1142 /* 1143 * Second part: skip past packets that userspace has released. 1144 * (kring->nr_hwcur to head excluded), 1145 * and make the buffers available for reception. 1146 * As usual nm_i is the index in the netmap ring, 1147 * nic_i is the index in the NIC ring, and 1148 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1149 */ 1150 /* XXX not sure how this will work with multiple free lists */ 1151 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 1152 1153 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1154 } 1155 1156 static void 1157 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1158 { 1159 struct ifnet *ifp = na->ifp; 1160 if_ctx_t ctx = ifp->if_softc; 1161 1162 CTX_LOCK(ctx); 1163 if (onoff) { 1164 IFDI_INTR_ENABLE(ctx); 1165 } else { 1166 IFDI_INTR_DISABLE(ctx); 1167 } 1168 CTX_UNLOCK(ctx); 1169 } 1170 1171 1172 static int 1173 iflib_netmap_attach(if_ctx_t ctx) 1174 { 1175 struct netmap_adapter na; 1176 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1177 1178 bzero(&na, sizeof(na)); 1179 1180 na.ifp = ctx->ifc_ifp; 1181 na.na_flags = NAF_BDG_MAYSLEEP; 1182 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1183 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1184 1185 na.num_tx_desc = scctx->isc_ntxd[0]; 1186 na.num_rx_desc = scctx->isc_nrxd[0]; 1187 na.nm_txsync = iflib_netmap_txsync; 1188 na.nm_rxsync = iflib_netmap_rxsync; 1189 na.nm_register = iflib_netmap_register; 1190 na.nm_intr = iflib_netmap_intr; 1191 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1192 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1193 return (netmap_attach(&na)); 1194 } 1195 1196 static void 1197 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1198 { 1199 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1200 struct netmap_slot *slot; 1201 1202 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1203 if (slot == NULL) 1204 return; 1205 if (txq->ift_sds.ifsd_map == NULL) 1206 return; 1207 1208 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1209 1210 /* 1211 * In netmap mode, set the map for the packet buffer. 1212 * NOTE: Some drivers (not this one) also need to set 1213 * the physical buffer address in the NIC ring. 1214 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1215 * netmap slot index, si 1216 */ 1217 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1218 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1219 } 1220 } 1221 1222 static void 1223 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1224 { 1225 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1226 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1227 struct netmap_slot *slot; 1228 uint32_t nm_i; 1229 1230 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1231 if (slot == NULL) 1232 return; 1233 nm_i = netmap_idx_n2k(kring, 0); 1234 netmap_fl_refill(rxq, kring, nm_i, true); 1235 } 1236 1237 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1238 1239 #else 1240 #define iflib_netmap_txq_init(ctx, txq) 1241 #define iflib_netmap_rxq_init(ctx, rxq) 1242 #define iflib_netmap_detach(ifp) 1243 1244 #define iflib_netmap_attach(ctx) (0) 1245 #define netmap_rx_irq(ifp, qid, budget) (0) 1246 #define netmap_tx_irq(ifp, qid) do {} while (0) 1247 1248 #endif 1249 1250 #if defined(__i386__) || defined(__amd64__) 1251 static __inline void 1252 prefetch(void *x) 1253 { 1254 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1255 } 1256 static __inline void 1257 prefetch2cachelines(void *x) 1258 { 1259 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1260 #if (CACHE_LINE_SIZE < 128) 1261 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1262 #endif 1263 } 1264 #else 1265 #define prefetch(x) 1266 #define prefetch2cachelines(x) 1267 #endif 1268 1269 static void 1270 iflib_gen_mac(if_ctx_t ctx) 1271 { 1272 struct thread *td; 1273 MD5_CTX mdctx; 1274 char uuid[HOSTUUIDLEN+1]; 1275 char buf[HOSTUUIDLEN+16]; 1276 uint8_t *mac; 1277 unsigned char digest[16]; 1278 1279 td = curthread; 1280 mac = ctx->ifc_mac; 1281 uuid[HOSTUUIDLEN] = 0; 1282 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN); 1283 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev)); 1284 /* 1285 * Generate a pseudo-random, deterministic MAC 1286 * address based on the UUID and unit number. 1287 * The FreeBSD Foundation OUI of 58-9C-FC is used. 1288 */ 1289 MD5Init(&mdctx); 1290 MD5Update(&mdctx, buf, strlen(buf)); 1291 MD5Final(digest, &mdctx); 1292 1293 mac[0] = 0x58; 1294 mac[1] = 0x9C; 1295 mac[2] = 0xFC; 1296 mac[3] = digest[0]; 1297 mac[4] = digest[1]; 1298 mac[5] = digest[2]; 1299 } 1300 1301 static void 1302 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1303 { 1304 iflib_fl_t fl; 1305 1306 fl = &rxq->ifr_fl[flid]; 1307 iru->iru_paddrs = fl->ifl_bus_addrs; 1308 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1309 iru->iru_idxs = fl->ifl_rxd_idxs; 1310 iru->iru_qsidx = rxq->ifr_id; 1311 iru->iru_buf_size = fl->ifl_buf_size; 1312 iru->iru_flidx = fl->ifl_id; 1313 } 1314 1315 static void 1316 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1317 { 1318 if (err) 1319 return; 1320 *(bus_addr_t *) arg = segs[0].ds_addr; 1321 } 1322 1323 int 1324 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1325 { 1326 int err; 1327 if_shared_ctx_t sctx = ctx->ifc_sctx; 1328 device_t dev = ctx->ifc_dev; 1329 1330 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1331 1332 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1333 sctx->isc_q_align, 0, /* alignment, bounds */ 1334 BUS_SPACE_MAXADDR, /* lowaddr */ 1335 BUS_SPACE_MAXADDR, /* highaddr */ 1336 NULL, NULL, /* filter, filterarg */ 1337 size, /* maxsize */ 1338 1, /* nsegments */ 1339 size, /* maxsegsize */ 1340 BUS_DMA_ALLOCNOW, /* flags */ 1341 NULL, /* lockfunc */ 1342 NULL, /* lockarg */ 1343 &dma->idi_tag); 1344 if (err) { 1345 device_printf(dev, 1346 "%s: bus_dma_tag_create failed: %d\n", 1347 __func__, err); 1348 goto fail_0; 1349 } 1350 1351 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1352 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1353 if (err) { 1354 device_printf(dev, 1355 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1356 __func__, (uintmax_t)size, err); 1357 goto fail_1; 1358 } 1359 1360 dma->idi_paddr = IF_BAD_DMA; 1361 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1362 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1363 if (err || dma->idi_paddr == IF_BAD_DMA) { 1364 device_printf(dev, 1365 "%s: bus_dmamap_load failed: %d\n", 1366 __func__, err); 1367 goto fail_2; 1368 } 1369 1370 dma->idi_size = size; 1371 return (0); 1372 1373 fail_2: 1374 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1375 fail_1: 1376 bus_dma_tag_destroy(dma->idi_tag); 1377 fail_0: 1378 dma->idi_tag = NULL; 1379 1380 return (err); 1381 } 1382 1383 int 1384 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1385 { 1386 int i, err; 1387 iflib_dma_info_t *dmaiter; 1388 1389 dmaiter = dmalist; 1390 for (i = 0; i < count; i++, dmaiter++) { 1391 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1392 break; 1393 } 1394 if (err) 1395 iflib_dma_free_multi(dmalist, i); 1396 return (err); 1397 } 1398 1399 void 1400 iflib_dma_free(iflib_dma_info_t dma) 1401 { 1402 if (dma->idi_tag == NULL) 1403 return; 1404 if (dma->idi_paddr != IF_BAD_DMA) { 1405 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1406 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1407 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1408 dma->idi_paddr = IF_BAD_DMA; 1409 } 1410 if (dma->idi_vaddr != NULL) { 1411 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1412 dma->idi_vaddr = NULL; 1413 } 1414 bus_dma_tag_destroy(dma->idi_tag); 1415 dma->idi_tag = NULL; 1416 } 1417 1418 void 1419 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1420 { 1421 int i; 1422 iflib_dma_info_t *dmaiter = dmalist; 1423 1424 for (i = 0; i < count; i++, dmaiter++) 1425 iflib_dma_free(*dmaiter); 1426 } 1427 1428 #ifdef EARLY_AP_STARTUP 1429 static const int iflib_started = 1; 1430 #else 1431 /* 1432 * We used to abuse the smp_started flag to decide if the queues have been 1433 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1434 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1435 * is set. Run a SYSINIT() strictly after that to just set a usable 1436 * completion flag. 1437 */ 1438 1439 static int iflib_started; 1440 1441 static void 1442 iflib_record_started(void *arg) 1443 { 1444 iflib_started = 1; 1445 } 1446 1447 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1448 iflib_record_started, NULL); 1449 #endif 1450 1451 static int 1452 iflib_fast_intr(void *arg) 1453 { 1454 iflib_filter_info_t info = arg; 1455 struct grouptask *gtask = info->ifi_task; 1456 if (!iflib_started) 1457 return (FILTER_HANDLED); 1458 1459 DBG_COUNTER_INC(fast_intrs); 1460 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1461 return (FILTER_HANDLED); 1462 1463 GROUPTASK_ENQUEUE(gtask); 1464 return (FILTER_HANDLED); 1465 } 1466 1467 static int 1468 iflib_fast_intr_rxtx(void *arg) 1469 { 1470 iflib_filter_info_t info = arg; 1471 struct grouptask *gtask = info->ifi_task; 1472 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1473 if_ctx_t ctx = NULL;; 1474 int i, cidx; 1475 1476 if (!iflib_started) 1477 return (FILTER_HANDLED); 1478 1479 DBG_COUNTER_INC(fast_intrs); 1480 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1481 return (FILTER_HANDLED); 1482 1483 MPASS(rxq->ifr_ntxqirq); 1484 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1485 qidx_t txqid = rxq->ifr_txqid[i]; 1486 1487 ctx = rxq->ifr_ctx; 1488 1489 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1490 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1491 continue; 1492 } 1493 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1494 } 1495 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1496 cidx = rxq->ifr_cq_cidx; 1497 else 1498 cidx = rxq->ifr_fl[0].ifl_cidx; 1499 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1500 GROUPTASK_ENQUEUE(gtask); 1501 else 1502 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1503 return (FILTER_HANDLED); 1504 } 1505 1506 1507 static int 1508 iflib_fast_intr_ctx(void *arg) 1509 { 1510 iflib_filter_info_t info = arg; 1511 struct grouptask *gtask = info->ifi_task; 1512 1513 if (!iflib_started) 1514 return (FILTER_HANDLED); 1515 1516 DBG_COUNTER_INC(fast_intrs); 1517 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1518 return (FILTER_HANDLED); 1519 1520 GROUPTASK_ENQUEUE(gtask); 1521 return (FILTER_HANDLED); 1522 } 1523 1524 static int 1525 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1526 driver_filter_t filter, driver_intr_t handler, void *arg, 1527 const char *name) 1528 { 1529 int rc, flags; 1530 struct resource *res; 1531 void *tag = NULL; 1532 device_t dev = ctx->ifc_dev; 1533 1534 flags = RF_ACTIVE; 1535 if (ctx->ifc_flags & IFC_LEGACY) 1536 flags |= RF_SHAREABLE; 1537 MPASS(rid < 512); 1538 irq->ii_rid = rid; 1539 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1540 if (res == NULL) { 1541 device_printf(dev, 1542 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1543 return (ENOMEM); 1544 } 1545 irq->ii_res = res; 1546 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1547 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1548 filter, handler, arg, &tag); 1549 if (rc != 0) { 1550 device_printf(dev, 1551 "failed to setup interrupt for rid %d, name %s: %d\n", 1552 rid, name ? name : "unknown", rc); 1553 return (rc); 1554 } else if (name) 1555 bus_describe_intr(dev, res, tag, "%s", name); 1556 1557 irq->ii_tag = tag; 1558 return (0); 1559 } 1560 1561 1562 /********************************************************************* 1563 * 1564 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1565 * the information needed to transmit a packet on the wire. This is 1566 * called only once at attach, setup is done every reset. 1567 * 1568 **********************************************************************/ 1569 1570 static int 1571 iflib_txsd_alloc(iflib_txq_t txq) 1572 { 1573 if_ctx_t ctx = txq->ift_ctx; 1574 if_shared_ctx_t sctx = ctx->ifc_sctx; 1575 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1576 device_t dev = ctx->ifc_dev; 1577 int err, nsegments, ntsosegments; 1578 1579 nsegments = scctx->isc_tx_nsegments; 1580 ntsosegments = scctx->isc_tx_tso_segments_max; 1581 MPASS(scctx->isc_ntxd[0] > 0); 1582 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1583 MPASS(nsegments > 0); 1584 MPASS(ntsosegments > 0); 1585 /* 1586 * Setup DMA descriptor areas. 1587 */ 1588 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1589 1, 0, /* alignment, bounds */ 1590 BUS_SPACE_MAXADDR, /* lowaddr */ 1591 BUS_SPACE_MAXADDR, /* highaddr */ 1592 NULL, NULL, /* filter, filterarg */ 1593 sctx->isc_tx_maxsize, /* maxsize */ 1594 nsegments, /* nsegments */ 1595 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1596 0, /* flags */ 1597 NULL, /* lockfunc */ 1598 NULL, /* lockfuncarg */ 1599 &txq->ift_desc_tag))) { 1600 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1601 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1602 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1603 goto fail; 1604 } 1605 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1606 1, 0, /* alignment, bounds */ 1607 BUS_SPACE_MAXADDR, /* lowaddr */ 1608 BUS_SPACE_MAXADDR, /* highaddr */ 1609 NULL, NULL, /* filter, filterarg */ 1610 scctx->isc_tx_tso_size_max, /* maxsize */ 1611 ntsosegments, /* nsegments */ 1612 scctx->isc_tx_tso_segsize_max, /* maxsegsize */ 1613 0, /* flags */ 1614 NULL, /* lockfunc */ 1615 NULL, /* lockfuncarg */ 1616 &txq->ift_tso_desc_tag))) { 1617 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1618 1619 goto fail; 1620 } 1621 if (!(txq->ift_sds.ifsd_flags = 1622 (uint8_t *) malloc(sizeof(uint8_t) * 1623 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1624 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1625 err = ENOMEM; 1626 goto fail; 1627 } 1628 if (!(txq->ift_sds.ifsd_m = 1629 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1630 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1631 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1632 err = ENOMEM; 1633 goto fail; 1634 } 1635 1636 /* Create the descriptor buffer dma maps */ 1637 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1638 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1639 return (0); 1640 1641 if (!(txq->ift_sds.ifsd_map = 1642 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1643 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1644 err = ENOMEM; 1645 goto fail; 1646 } 1647 1648 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1649 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1650 if (err != 0) { 1651 device_printf(dev, "Unable to create TX DMA map\n"); 1652 goto fail; 1653 } 1654 } 1655 #endif 1656 return (0); 1657 fail: 1658 /* We free all, it handles case where we are in the middle */ 1659 iflib_tx_structures_free(ctx); 1660 return (err); 1661 } 1662 1663 static void 1664 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1665 { 1666 bus_dmamap_t map; 1667 1668 map = NULL; 1669 if (txq->ift_sds.ifsd_map != NULL) 1670 map = txq->ift_sds.ifsd_map[i]; 1671 if (map != NULL) { 1672 bus_dmamap_unload(txq->ift_desc_tag, map); 1673 bus_dmamap_destroy(txq->ift_desc_tag, map); 1674 txq->ift_sds.ifsd_map[i] = NULL; 1675 } 1676 } 1677 1678 static void 1679 iflib_txq_destroy(iflib_txq_t txq) 1680 { 1681 if_ctx_t ctx = txq->ift_ctx; 1682 1683 for (int i = 0; i < txq->ift_size; i++) 1684 iflib_txsd_destroy(ctx, txq, i); 1685 if (txq->ift_sds.ifsd_map != NULL) { 1686 free(txq->ift_sds.ifsd_map, M_IFLIB); 1687 txq->ift_sds.ifsd_map = NULL; 1688 } 1689 if (txq->ift_sds.ifsd_m != NULL) { 1690 free(txq->ift_sds.ifsd_m, M_IFLIB); 1691 txq->ift_sds.ifsd_m = NULL; 1692 } 1693 if (txq->ift_sds.ifsd_flags != NULL) { 1694 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1695 txq->ift_sds.ifsd_flags = NULL; 1696 } 1697 if (txq->ift_desc_tag != NULL) { 1698 bus_dma_tag_destroy(txq->ift_desc_tag); 1699 txq->ift_desc_tag = NULL; 1700 } 1701 if (txq->ift_tso_desc_tag != NULL) { 1702 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1703 txq->ift_tso_desc_tag = NULL; 1704 } 1705 } 1706 1707 static void 1708 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1709 { 1710 struct mbuf **mp; 1711 1712 mp = &txq->ift_sds.ifsd_m[i]; 1713 if (*mp == NULL) 1714 return; 1715 1716 if (txq->ift_sds.ifsd_map != NULL) { 1717 bus_dmamap_sync(txq->ift_desc_tag, 1718 txq->ift_sds.ifsd_map[i], 1719 BUS_DMASYNC_POSTWRITE); 1720 bus_dmamap_unload(txq->ift_desc_tag, 1721 txq->ift_sds.ifsd_map[i]); 1722 } 1723 m_free(*mp); 1724 DBG_COUNTER_INC(tx_frees); 1725 *mp = NULL; 1726 } 1727 1728 static int 1729 iflib_txq_setup(iflib_txq_t txq) 1730 { 1731 if_ctx_t ctx = txq->ift_ctx; 1732 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1733 iflib_dma_info_t di; 1734 int i; 1735 1736 /* Set number of descriptors available */ 1737 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1738 /* XXX make configurable */ 1739 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1740 1741 /* Reset indices */ 1742 txq->ift_cidx_processed = 0; 1743 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1744 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1745 1746 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1747 bzero((void *)di->idi_vaddr, di->idi_size); 1748 1749 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1750 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1751 bus_dmamap_sync(di->idi_tag, di->idi_map, 1752 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1753 return (0); 1754 } 1755 1756 /********************************************************************* 1757 * 1758 * Allocate memory for rx_buffer structures. Since we use one 1759 * rx_buffer per received packet, the maximum number of rx_buffer's 1760 * that we'll need is equal to the number of receive descriptors 1761 * that we've allocated. 1762 * 1763 **********************************************************************/ 1764 static int 1765 iflib_rxsd_alloc(iflib_rxq_t rxq) 1766 { 1767 if_ctx_t ctx = rxq->ifr_ctx; 1768 if_shared_ctx_t sctx = ctx->ifc_sctx; 1769 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1770 device_t dev = ctx->ifc_dev; 1771 iflib_fl_t fl; 1772 int err; 1773 1774 MPASS(scctx->isc_nrxd[0] > 0); 1775 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1776 1777 fl = rxq->ifr_fl; 1778 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1779 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1780 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1781 1, 0, /* alignment, bounds */ 1782 BUS_SPACE_MAXADDR, /* lowaddr */ 1783 BUS_SPACE_MAXADDR, /* highaddr */ 1784 NULL, NULL, /* filter, filterarg */ 1785 sctx->isc_rx_maxsize, /* maxsize */ 1786 sctx->isc_rx_nsegments, /* nsegments */ 1787 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1788 0, /* flags */ 1789 NULL, /* lockfunc */ 1790 NULL, /* lockarg */ 1791 &fl->ifl_desc_tag); 1792 if (err) { 1793 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1794 __func__, err); 1795 goto fail; 1796 } 1797 if (!(fl->ifl_sds.ifsd_flags = 1798 (uint8_t *) malloc(sizeof(uint8_t) * 1799 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1800 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1801 err = ENOMEM; 1802 goto fail; 1803 } 1804 if (!(fl->ifl_sds.ifsd_m = 1805 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1806 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1807 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1808 err = ENOMEM; 1809 goto fail; 1810 } 1811 if (!(fl->ifl_sds.ifsd_cl = 1812 (caddr_t *) malloc(sizeof(caddr_t) * 1813 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1814 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1815 err = ENOMEM; 1816 goto fail; 1817 } 1818 1819 /* Create the descriptor buffer dma maps */ 1820 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1821 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1822 continue; 1823 1824 if (!(fl->ifl_sds.ifsd_map = 1825 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1826 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1827 err = ENOMEM; 1828 goto fail; 1829 } 1830 1831 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1832 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1833 if (err != 0) { 1834 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1835 goto fail; 1836 } 1837 } 1838 #endif 1839 } 1840 return (0); 1841 1842 fail: 1843 iflib_rx_structures_free(ctx); 1844 return (err); 1845 } 1846 1847 1848 /* 1849 * Internal service routines 1850 */ 1851 1852 struct rxq_refill_cb_arg { 1853 int error; 1854 bus_dma_segment_t seg; 1855 int nseg; 1856 }; 1857 1858 static void 1859 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1860 { 1861 struct rxq_refill_cb_arg *cb_arg = arg; 1862 1863 cb_arg->error = error; 1864 cb_arg->seg = segs[0]; 1865 cb_arg->nseg = nseg; 1866 } 1867 1868 1869 #ifdef ACPI_DMAR 1870 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1871 #else 1872 #define IS_DMAR(ctx) (0) 1873 #endif 1874 1875 /** 1876 * rxq_refill - refill an rxq free-buffer list 1877 * @ctx: the iflib context 1878 * @rxq: the free-list to refill 1879 * @n: the number of new buffers to allocate 1880 * 1881 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1882 * The caller must assure that @n does not exceed the queue's capacity. 1883 */ 1884 static void 1885 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1886 { 1887 struct mbuf *m; 1888 int idx, frag_idx = fl->ifl_fragidx; 1889 int pidx = fl->ifl_pidx; 1890 caddr_t cl, *sd_cl; 1891 struct mbuf **sd_m; 1892 uint8_t *sd_flags; 1893 struct if_rxd_update iru; 1894 bus_dmamap_t *sd_map; 1895 int n, i = 0; 1896 uint64_t bus_addr; 1897 int err; 1898 qidx_t credits; 1899 1900 sd_m = fl->ifl_sds.ifsd_m; 1901 sd_map = fl->ifl_sds.ifsd_map; 1902 sd_cl = fl->ifl_sds.ifsd_cl; 1903 sd_flags = fl->ifl_sds.ifsd_flags; 1904 idx = pidx; 1905 credits = fl->ifl_credits; 1906 1907 n = count; 1908 MPASS(n > 0); 1909 MPASS(credits + n <= fl->ifl_size); 1910 1911 if (pidx < fl->ifl_cidx) 1912 MPASS(pidx + n <= fl->ifl_cidx); 1913 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1914 MPASS(fl->ifl_gen == 0); 1915 if (pidx > fl->ifl_cidx) 1916 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1917 1918 DBG_COUNTER_INC(fl_refills); 1919 if (n > 8) 1920 DBG_COUNTER_INC(fl_refills_large); 1921 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1922 while (n--) { 1923 /* 1924 * We allocate an uninitialized mbuf + cluster, mbuf is 1925 * initialized after rx. 1926 * 1927 * If the cluster is still set then we know a minimum sized packet was received 1928 */ 1929 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1930 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1931 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1932 if ((cl = sd_cl[frag_idx]) == NULL) { 1933 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1934 break; 1935 #if MEMORY_LOGGING 1936 fl->ifl_cl_enqueued++; 1937 #endif 1938 } 1939 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1940 break; 1941 } 1942 #if MEMORY_LOGGING 1943 fl->ifl_m_enqueued++; 1944 #endif 1945 1946 DBG_COUNTER_INC(rx_allocs); 1947 #if defined(__i386__) || defined(__amd64__) 1948 if (!IS_DMAR(ctx)) { 1949 bus_addr = pmap_kextract((vm_offset_t)cl); 1950 } else 1951 #endif 1952 { 1953 struct rxq_refill_cb_arg cb_arg; 1954 1955 cb_arg.error = 0; 1956 MPASS(sd_map != NULL); 1957 MPASS(sd_map[frag_idx] != NULL); 1958 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1959 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1960 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 1961 BUS_DMASYNC_PREREAD); 1962 1963 if (err != 0 || cb_arg.error) { 1964 /* 1965 * !zone_pack ? 1966 */ 1967 if (fl->ifl_zone == zone_pack) 1968 uma_zfree(fl->ifl_zone, cl); 1969 m_free(m); 1970 n = 0; 1971 goto done; 1972 } 1973 bus_addr = cb_arg.seg.ds_addr; 1974 } 1975 bit_set(fl->ifl_rx_bitmap, frag_idx); 1976 sd_flags[frag_idx] |= RX_SW_DESC_INUSE; 1977 1978 MPASS(sd_m[frag_idx] == NULL); 1979 sd_cl[frag_idx] = cl; 1980 sd_m[frag_idx] = m; 1981 fl->ifl_rxd_idxs[i] = frag_idx; 1982 fl->ifl_bus_addrs[i] = bus_addr; 1983 fl->ifl_vm_addrs[i] = cl; 1984 credits++; 1985 i++; 1986 MPASS(credits <= fl->ifl_size); 1987 if (++idx == fl->ifl_size) { 1988 fl->ifl_gen = 1; 1989 idx = 0; 1990 } 1991 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 1992 iru.iru_pidx = pidx; 1993 iru.iru_count = i; 1994 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1995 i = 0; 1996 pidx = idx; 1997 fl->ifl_pidx = idx; 1998 fl->ifl_credits = credits; 1999 } 2000 2001 } 2002 done: 2003 if (i) { 2004 iru.iru_pidx = pidx; 2005 iru.iru_count = i; 2006 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2007 fl->ifl_pidx = idx; 2008 fl->ifl_credits = credits; 2009 } 2010 DBG_COUNTER_INC(rxd_flush); 2011 if (fl->ifl_pidx == 0) 2012 pidx = fl->ifl_size - 1; 2013 else 2014 pidx = fl->ifl_pidx - 1; 2015 2016 if (sd_map) 2017 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2018 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2019 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2020 fl->ifl_fragidx = frag_idx; 2021 } 2022 2023 static __inline void 2024 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2025 { 2026 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2027 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2028 #ifdef INVARIANTS 2029 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2030 #endif 2031 2032 MPASS(fl->ifl_credits <= fl->ifl_size); 2033 MPASS(reclaimable == delta); 2034 2035 if (reclaimable > 0) 2036 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2037 } 2038 2039 static void 2040 iflib_fl_bufs_free(iflib_fl_t fl) 2041 { 2042 iflib_dma_info_t idi = fl->ifl_ifdi; 2043 uint32_t i; 2044 2045 for (i = 0; i < fl->ifl_size; i++) { 2046 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2047 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 2048 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2049 2050 if (*sd_flags & RX_SW_DESC_INUSE) { 2051 if (fl->ifl_sds.ifsd_map != NULL) { 2052 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 2053 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 2054 if (fl->ifl_rxq->ifr_ctx->ifc_in_detach) 2055 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 2056 } 2057 if (*sd_m != NULL) { 2058 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2059 uma_zfree(zone_mbuf, *sd_m); 2060 } 2061 if (*sd_cl != NULL) 2062 uma_zfree(fl->ifl_zone, *sd_cl); 2063 *sd_flags = 0; 2064 } else { 2065 MPASS(*sd_cl == NULL); 2066 MPASS(*sd_m == NULL); 2067 } 2068 #if MEMORY_LOGGING 2069 fl->ifl_m_dequeued++; 2070 fl->ifl_cl_dequeued++; 2071 #endif 2072 *sd_cl = NULL; 2073 *sd_m = NULL; 2074 } 2075 #ifdef INVARIANTS 2076 for (i = 0; i < fl->ifl_size; i++) { 2077 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 2078 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2079 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2080 } 2081 #endif 2082 /* 2083 * Reset free list values 2084 */ 2085 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2086 bzero(idi->idi_vaddr, idi->idi_size); 2087 } 2088 2089 /********************************************************************* 2090 * 2091 * Initialize a receive ring and its buffers. 2092 * 2093 **********************************************************************/ 2094 static int 2095 iflib_fl_setup(iflib_fl_t fl) 2096 { 2097 iflib_rxq_t rxq = fl->ifl_rxq; 2098 if_ctx_t ctx = rxq->ifr_ctx; 2099 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2100 2101 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2102 /* 2103 ** Free current RX buffer structs and their mbufs 2104 */ 2105 iflib_fl_bufs_free(fl); 2106 /* Now replenish the mbufs */ 2107 MPASS(fl->ifl_credits == 0); 2108 /* 2109 * XXX don't set the max_frame_size to larger 2110 * than the hardware can handle 2111 */ 2112 if (sctx->isc_max_frame_size <= 2048) 2113 fl->ifl_buf_size = MCLBYTES; 2114 #ifndef CONTIGMALLOC_WORKS 2115 else 2116 fl->ifl_buf_size = MJUMPAGESIZE; 2117 #else 2118 else if (sctx->isc_max_frame_size <= 4096) 2119 fl->ifl_buf_size = MJUMPAGESIZE; 2120 else if (sctx->isc_max_frame_size <= 9216) 2121 fl->ifl_buf_size = MJUM9BYTES; 2122 else 2123 fl->ifl_buf_size = MJUM16BYTES; 2124 #endif 2125 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2126 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2127 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2128 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2129 2130 2131 /* avoid pre-allocating zillions of clusters to an idle card 2132 * potentially speeding up attach 2133 */ 2134 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2135 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2136 if (min(128, fl->ifl_size) != fl->ifl_credits) 2137 return (ENOBUFS); 2138 /* 2139 * handle failure 2140 */ 2141 MPASS(rxq != NULL); 2142 MPASS(fl->ifl_ifdi != NULL); 2143 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2144 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2145 return (0); 2146 } 2147 2148 /********************************************************************* 2149 * 2150 * Free receive ring data structures 2151 * 2152 **********************************************************************/ 2153 static void 2154 iflib_rx_sds_free(iflib_rxq_t rxq) 2155 { 2156 iflib_fl_t fl; 2157 int i; 2158 2159 if (rxq->ifr_fl != NULL) { 2160 for (i = 0; i < rxq->ifr_nfl; i++) { 2161 fl = &rxq->ifr_fl[i]; 2162 if (fl->ifl_desc_tag != NULL) { 2163 bus_dma_tag_destroy(fl->ifl_desc_tag); 2164 fl->ifl_desc_tag = NULL; 2165 } 2166 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2167 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2168 /* XXX destroy maps first */ 2169 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2170 fl->ifl_sds.ifsd_m = NULL; 2171 fl->ifl_sds.ifsd_cl = NULL; 2172 fl->ifl_sds.ifsd_map = NULL; 2173 } 2174 free(rxq->ifr_fl, M_IFLIB); 2175 rxq->ifr_fl = NULL; 2176 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2177 } 2178 } 2179 2180 /* 2181 * MI independent logic 2182 * 2183 */ 2184 static void 2185 iflib_timer(void *arg) 2186 { 2187 iflib_txq_t txq = arg; 2188 if_ctx_t ctx = txq->ift_ctx; 2189 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2190 2191 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2192 return; 2193 /* 2194 ** Check on the state of the TX queue(s), this 2195 ** can be done without the lock because its RO 2196 ** and the HUNG state will be static if set. 2197 */ 2198 IFDI_TIMER(ctx, txq->ift_id); 2199 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2200 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2201 (sctx->isc_pause_frames == 0))) 2202 goto hung; 2203 2204 if (ifmp_ring_is_stalled(txq->ift_br)) 2205 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2206 txq->ift_cleaned_prev = txq->ift_cleaned; 2207 /* handle any laggards */ 2208 if (txq->ift_db_pending) 2209 GROUPTASK_ENQUEUE(&txq->ift_task); 2210 2211 sctx->isc_pause_frames = 0; 2212 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2213 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 2214 return; 2215 hung: 2216 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2217 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2218 STATE_LOCK(ctx); 2219 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2220 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2221 iflib_admin_intr_deferred(ctx); 2222 STATE_UNLOCK(ctx); 2223 } 2224 2225 static void 2226 iflib_init_locked(if_ctx_t ctx) 2227 { 2228 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2229 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2230 if_t ifp = ctx->ifc_ifp; 2231 iflib_fl_t fl; 2232 iflib_txq_t txq; 2233 iflib_rxq_t rxq; 2234 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2235 2236 2237 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2238 IFDI_INTR_DISABLE(ctx); 2239 2240 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2241 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2242 /* Set hardware offload abilities */ 2243 if_clearhwassist(ifp); 2244 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2245 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2246 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2247 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2248 if (if_getcapenable(ifp) & IFCAP_TSO4) 2249 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2250 if (if_getcapenable(ifp) & IFCAP_TSO6) 2251 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2252 2253 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2254 CALLOUT_LOCK(txq); 2255 callout_stop(&txq->ift_timer); 2256 CALLOUT_UNLOCK(txq); 2257 iflib_netmap_txq_init(ctx, txq); 2258 } 2259 #ifdef INVARIANTS 2260 i = if_getdrvflags(ifp); 2261 #endif 2262 IFDI_INIT(ctx); 2263 MPASS(if_getdrvflags(ifp) == i); 2264 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2265 /* XXX this should really be done on a per-queue basis */ 2266 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2267 MPASS(rxq->ifr_id == i); 2268 iflib_netmap_rxq_init(ctx, rxq); 2269 continue; 2270 } 2271 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2272 if (iflib_fl_setup(fl)) { 2273 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2274 goto done; 2275 } 2276 } 2277 } 2278 done: 2279 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2280 IFDI_INTR_ENABLE(ctx); 2281 txq = ctx->ifc_txqs; 2282 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2283 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2284 txq->ift_timer.c_cpu); 2285 } 2286 2287 static int 2288 iflib_media_change(if_t ifp) 2289 { 2290 if_ctx_t ctx = if_getsoftc(ifp); 2291 int err; 2292 2293 CTX_LOCK(ctx); 2294 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2295 iflib_init_locked(ctx); 2296 CTX_UNLOCK(ctx); 2297 return (err); 2298 } 2299 2300 static void 2301 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2302 { 2303 if_ctx_t ctx = if_getsoftc(ifp); 2304 2305 CTX_LOCK(ctx); 2306 IFDI_UPDATE_ADMIN_STATUS(ctx); 2307 IFDI_MEDIA_STATUS(ctx, ifmr); 2308 CTX_UNLOCK(ctx); 2309 } 2310 2311 void 2312 iflib_stop(if_ctx_t ctx) 2313 { 2314 iflib_txq_t txq = ctx->ifc_txqs; 2315 iflib_rxq_t rxq = ctx->ifc_rxqs; 2316 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2317 iflib_dma_info_t di; 2318 iflib_fl_t fl; 2319 int i, j; 2320 2321 /* Tell the stack that the interface is no longer active */ 2322 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2323 2324 IFDI_INTR_DISABLE(ctx); 2325 DELAY(1000); 2326 IFDI_STOP(ctx); 2327 DELAY(1000); 2328 2329 iflib_debug_reset(); 2330 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2331 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2332 /* make sure all transmitters have completed before proceeding XXX */ 2333 2334 CALLOUT_LOCK(txq); 2335 callout_stop(&txq->ift_timer); 2336 CALLOUT_UNLOCK(txq); 2337 2338 /* clean any enqueued buffers */ 2339 iflib_ifmp_purge(txq); 2340 /* Free any existing tx buffers. */ 2341 for (j = 0; j < txq->ift_size; j++) { 2342 iflib_txsd_free(ctx, txq, j); 2343 } 2344 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2345 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2346 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2347 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2348 txq->ift_pullups = 0; 2349 ifmp_ring_reset_stats(txq->ift_br); 2350 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2351 bzero((void *)di->idi_vaddr, di->idi_size); 2352 } 2353 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2354 /* make sure all transmitters have completed before proceeding XXX */ 2355 2356 for (j = 0, di = rxq->ifr_ifdi; j < rxq->ifr_nfl; j++, di++) 2357 bzero((void *)di->idi_vaddr, di->idi_size); 2358 /* also resets the free lists pidx/cidx */ 2359 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2360 iflib_fl_bufs_free(fl); 2361 } 2362 } 2363 2364 static inline caddr_t 2365 calc_next_rxd(iflib_fl_t fl, int cidx) 2366 { 2367 qidx_t size; 2368 int nrxd; 2369 caddr_t start, end, cur, next; 2370 2371 nrxd = fl->ifl_size; 2372 size = fl->ifl_rxd_size; 2373 start = fl->ifl_ifdi->idi_vaddr; 2374 2375 if (__predict_false(size == 0)) 2376 return (start); 2377 cur = start + size*cidx; 2378 end = start + size*nrxd; 2379 next = CACHE_PTR_NEXT(cur); 2380 return (next < end ? next : start); 2381 } 2382 2383 static inline void 2384 prefetch_pkts(iflib_fl_t fl, int cidx) 2385 { 2386 int nextptr; 2387 int nrxd = fl->ifl_size; 2388 caddr_t next_rxd; 2389 2390 2391 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2392 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2393 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2394 next_rxd = calc_next_rxd(fl, cidx); 2395 prefetch(next_rxd); 2396 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2397 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2398 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2399 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2400 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2401 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2402 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2403 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2404 } 2405 2406 static void 2407 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2408 { 2409 int flid, cidx; 2410 bus_dmamap_t map; 2411 iflib_fl_t fl; 2412 iflib_dma_info_t di; 2413 int next; 2414 2415 map = NULL; 2416 flid = irf->irf_flid; 2417 cidx = irf->irf_idx; 2418 fl = &rxq->ifr_fl[flid]; 2419 sd->ifsd_fl = fl; 2420 sd->ifsd_cidx = cidx; 2421 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2422 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2423 fl->ifl_credits--; 2424 #if MEMORY_LOGGING 2425 fl->ifl_m_dequeued++; 2426 #endif 2427 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2428 prefetch_pkts(fl, cidx); 2429 if (fl->ifl_sds.ifsd_map != NULL) { 2430 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2431 prefetch(&fl->ifl_sds.ifsd_map[next]); 2432 map = fl->ifl_sds.ifsd_map[cidx]; 2433 di = fl->ifl_ifdi; 2434 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2435 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2436 bus_dmamap_sync(di->idi_tag, di->idi_map, 2437 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2438 2439 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2440 MPASS(fl->ifl_cidx == cidx); 2441 if (unload) 2442 bus_dmamap_unload(fl->ifl_desc_tag, map); 2443 } 2444 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2445 if (__predict_false(fl->ifl_cidx == 0)) 2446 fl->ifl_gen = 0; 2447 if (map != NULL) 2448 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2449 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2450 bit_clear(fl->ifl_rx_bitmap, cidx); 2451 } 2452 2453 static struct mbuf * 2454 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2455 { 2456 int i, padlen , flags; 2457 struct mbuf *m, *mh, *mt; 2458 caddr_t cl; 2459 2460 i = 0; 2461 mh = NULL; 2462 do { 2463 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2464 2465 MPASS(*sd->ifsd_cl != NULL); 2466 MPASS(*sd->ifsd_m != NULL); 2467 2468 /* Don't include zero-length frags */ 2469 if (ri->iri_frags[i].irf_len == 0) { 2470 /* XXX we can save the cluster here, but not the mbuf */ 2471 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2472 m_free(*sd->ifsd_m); 2473 *sd->ifsd_m = NULL; 2474 continue; 2475 } 2476 m = *sd->ifsd_m; 2477 *sd->ifsd_m = NULL; 2478 if (mh == NULL) { 2479 flags = M_PKTHDR|M_EXT; 2480 mh = mt = m; 2481 padlen = ri->iri_pad; 2482 } else { 2483 flags = M_EXT; 2484 mt->m_next = m; 2485 mt = m; 2486 /* assuming padding is only on the first fragment */ 2487 padlen = 0; 2488 } 2489 cl = *sd->ifsd_cl; 2490 *sd->ifsd_cl = NULL; 2491 2492 /* Can these two be made one ? */ 2493 m_init(m, M_NOWAIT, MT_DATA, flags); 2494 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2495 /* 2496 * These must follow m_init and m_cljset 2497 */ 2498 m->m_data += padlen; 2499 ri->iri_len -= padlen; 2500 m->m_len = ri->iri_frags[i].irf_len; 2501 } while (++i < ri->iri_nfrags); 2502 2503 return (mh); 2504 } 2505 2506 /* 2507 * Process one software descriptor 2508 */ 2509 static struct mbuf * 2510 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2511 { 2512 struct if_rxsd sd; 2513 struct mbuf *m; 2514 2515 /* should I merge this back in now that the two paths are basically duplicated? */ 2516 if (ri->iri_nfrags == 1 && 2517 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2518 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2519 m = *sd.ifsd_m; 2520 *sd.ifsd_m = NULL; 2521 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2522 #ifndef __NO_STRICT_ALIGNMENT 2523 if (!IP_ALIGNED(m)) 2524 m->m_data += 2; 2525 #endif 2526 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2527 m->m_len = ri->iri_frags[0].irf_len; 2528 } else { 2529 m = assemble_segments(rxq, ri, &sd); 2530 } 2531 m->m_pkthdr.len = ri->iri_len; 2532 m->m_pkthdr.rcvif = ri->iri_ifp; 2533 m->m_flags |= ri->iri_flags; 2534 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2535 m->m_pkthdr.flowid = ri->iri_flowid; 2536 M_HASHTYPE_SET(m, ri->iri_rsstype); 2537 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2538 m->m_pkthdr.csum_data = ri->iri_csum_data; 2539 return (m); 2540 } 2541 2542 #if defined(INET6) || defined(INET) 2543 static void 2544 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2545 { 2546 CURVNET_SET(lc->ifp->if_vnet); 2547 #if defined(INET6) 2548 *v6 = VNET(ip6_forwarding); 2549 #endif 2550 #if defined(INET) 2551 *v4 = VNET(ipforwarding); 2552 #endif 2553 CURVNET_RESTORE(); 2554 } 2555 2556 /* 2557 * Returns true if it's possible this packet could be LROed. 2558 * if it returns false, it is guaranteed that tcp_lro_rx() 2559 * would not return zero. 2560 */ 2561 static bool 2562 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2563 { 2564 struct ether_header *eh; 2565 uint16_t eh_type; 2566 2567 eh = mtod(m, struct ether_header *); 2568 eh_type = ntohs(eh->ether_type); 2569 switch (eh_type) { 2570 #if defined(INET6) 2571 case ETHERTYPE_IPV6: 2572 return !v6_forwarding; 2573 #endif 2574 #if defined (INET) 2575 case ETHERTYPE_IP: 2576 return !v4_forwarding; 2577 #endif 2578 } 2579 2580 return false; 2581 } 2582 #else 2583 static void 2584 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2585 { 2586 } 2587 #endif 2588 2589 static bool 2590 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2591 { 2592 if_ctx_t ctx = rxq->ifr_ctx; 2593 if_shared_ctx_t sctx = ctx->ifc_sctx; 2594 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2595 int avail, i; 2596 qidx_t *cidxp; 2597 struct if_rxd_info ri; 2598 int err, budget_left, rx_bytes, rx_pkts; 2599 iflib_fl_t fl; 2600 struct ifnet *ifp; 2601 int lro_enabled; 2602 bool v4_forwarding, v6_forwarding, lro_possible; 2603 2604 /* 2605 * XXX early demux data packets so that if_input processing only handles 2606 * acks in interrupt context 2607 */ 2608 struct mbuf *m, *mh, *mt, *mf; 2609 2610 lro_possible = v4_forwarding = v6_forwarding = false; 2611 ifp = ctx->ifc_ifp; 2612 mh = mt = NULL; 2613 MPASS(budget > 0); 2614 rx_pkts = rx_bytes = 0; 2615 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2616 cidxp = &rxq->ifr_cq_cidx; 2617 else 2618 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2619 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2620 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2621 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2622 DBG_COUNTER_INC(rx_unavail); 2623 return (false); 2624 } 2625 2626 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2627 if (__predict_false(!CTX_ACTIVE(ctx))) { 2628 DBG_COUNTER_INC(rx_ctx_inactive); 2629 break; 2630 } 2631 /* 2632 * Reset client set fields to their default values 2633 */ 2634 rxd_info_zero(&ri); 2635 ri.iri_qsidx = rxq->ifr_id; 2636 ri.iri_cidx = *cidxp; 2637 ri.iri_ifp = ifp; 2638 ri.iri_frags = rxq->ifr_frags; 2639 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2640 2641 if (err) 2642 goto err; 2643 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2644 *cidxp = ri.iri_cidx; 2645 /* Update our consumer index */ 2646 /* XXX NB: shurd - check if this is still safe */ 2647 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2648 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2649 rxq->ifr_cq_gen = 0; 2650 } 2651 /* was this only a completion queue message? */ 2652 if (__predict_false(ri.iri_nfrags == 0)) 2653 continue; 2654 } 2655 MPASS(ri.iri_nfrags != 0); 2656 MPASS(ri.iri_len != 0); 2657 2658 /* will advance the cidx on the corresponding free lists */ 2659 m = iflib_rxd_pkt_get(rxq, &ri); 2660 if (avail == 0 && budget_left) 2661 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2662 2663 if (__predict_false(m == NULL)) { 2664 DBG_COUNTER_INC(rx_mbuf_null); 2665 continue; 2666 } 2667 /* imm_pkt: -- cxgb */ 2668 if (mh == NULL) 2669 mh = mt = m; 2670 else { 2671 mt->m_nextpkt = m; 2672 mt = m; 2673 } 2674 } 2675 /* make sure that we can refill faster than drain */ 2676 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2677 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2678 2679 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2680 if (lro_enabled) 2681 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2682 mt = mf = NULL; 2683 while (mh != NULL) { 2684 m = mh; 2685 mh = mh->m_nextpkt; 2686 m->m_nextpkt = NULL; 2687 #ifndef __NO_STRICT_ALIGNMENT 2688 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2689 continue; 2690 #endif 2691 rx_bytes += m->m_pkthdr.len; 2692 rx_pkts++; 2693 #if defined(INET6) || defined(INET) 2694 if (lro_enabled) { 2695 if (!lro_possible) { 2696 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2697 if (lro_possible && mf != NULL) { 2698 ifp->if_input(ifp, mf); 2699 DBG_COUNTER_INC(rx_if_input); 2700 mt = mf = NULL; 2701 } 2702 } 2703 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2704 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2705 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2706 continue; 2707 } 2708 } 2709 #endif 2710 if (lro_possible) { 2711 ifp->if_input(ifp, m); 2712 DBG_COUNTER_INC(rx_if_input); 2713 continue; 2714 } 2715 2716 if (mf == NULL) 2717 mf = m; 2718 if (mt != NULL) 2719 mt->m_nextpkt = m; 2720 mt = m; 2721 } 2722 if (mf != NULL) { 2723 ifp->if_input(ifp, mf); 2724 DBG_COUNTER_INC(rx_if_input); 2725 } 2726 2727 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2728 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2729 2730 /* 2731 * Flush any outstanding LRO work 2732 */ 2733 #if defined(INET6) || defined(INET) 2734 tcp_lro_flush_all(&rxq->ifr_lc); 2735 #endif 2736 if (avail) 2737 return true; 2738 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2739 err: 2740 STATE_LOCK(ctx); 2741 ctx->ifc_flags |= IFC_DO_RESET; 2742 iflib_admin_intr_deferred(ctx); 2743 STATE_UNLOCK(ctx); 2744 return (false); 2745 } 2746 2747 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2748 static inline qidx_t 2749 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2750 { 2751 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2752 qidx_t minthresh = txq->ift_size / 8; 2753 if (in_use > 4*minthresh) 2754 return (notify_count); 2755 if (in_use > 2*minthresh) 2756 return (notify_count >> 1); 2757 if (in_use > minthresh) 2758 return (notify_count >> 3); 2759 return (0); 2760 } 2761 2762 static inline qidx_t 2763 txq_max_rs_deferred(iflib_txq_t txq) 2764 { 2765 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2766 qidx_t minthresh = txq->ift_size / 8; 2767 if (txq->ift_in_use > 4*minthresh) 2768 return (notify_count); 2769 if (txq->ift_in_use > 2*minthresh) 2770 return (notify_count >> 1); 2771 if (txq->ift_in_use > minthresh) 2772 return (notify_count >> 2); 2773 return (2); 2774 } 2775 2776 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2777 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2778 2779 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2780 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2781 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2782 2783 /* forward compatibility for cxgb */ 2784 #define FIRST_QSET(ctx) 0 2785 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2786 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2787 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2788 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2789 2790 /* XXX we should be setting this to something other than zero */ 2791 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2792 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2793 2794 static inline bool 2795 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2796 { 2797 qidx_t dbval, max; 2798 bool rang; 2799 2800 rang = false; 2801 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2802 if (ring || txq->ift_db_pending >= max) { 2803 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2804 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2805 txq->ift_db_pending = txq->ift_npending = 0; 2806 rang = true; 2807 } 2808 return (rang); 2809 } 2810 2811 #ifdef PKT_DEBUG 2812 static void 2813 print_pkt(if_pkt_info_t pi) 2814 { 2815 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2816 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2817 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2818 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2819 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2820 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2821 } 2822 #endif 2823 2824 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2825 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2826 2827 static int 2828 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2829 { 2830 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2831 struct ether_vlan_header *eh; 2832 struct mbuf *m, *n; 2833 2834 n = m = *mp; 2835 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2836 M_WRITABLE(m) == 0) { 2837 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2838 return (ENOMEM); 2839 } else { 2840 m_freem(*mp); 2841 n = *mp = m; 2842 } 2843 } 2844 2845 /* 2846 * Determine where frame payload starts. 2847 * Jump over vlan headers if already present, 2848 * helpful for QinQ too. 2849 */ 2850 if (__predict_false(m->m_len < sizeof(*eh))) { 2851 txq->ift_pullups++; 2852 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2853 return (ENOMEM); 2854 } 2855 eh = mtod(m, struct ether_vlan_header *); 2856 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2857 pi->ipi_etype = ntohs(eh->evl_proto); 2858 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2859 } else { 2860 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2861 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2862 } 2863 2864 switch (pi->ipi_etype) { 2865 #ifdef INET 2866 case ETHERTYPE_IP: 2867 { 2868 struct ip *ip = NULL; 2869 struct tcphdr *th = NULL; 2870 int minthlen; 2871 2872 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2873 if (__predict_false(m->m_len < minthlen)) { 2874 /* 2875 * if this code bloat is causing too much of a hit 2876 * move it to a separate function and mark it noinline 2877 */ 2878 if (m->m_len == pi->ipi_ehdrlen) { 2879 n = m->m_next; 2880 MPASS(n); 2881 if (n->m_len >= sizeof(*ip)) { 2882 ip = (struct ip *)n->m_data; 2883 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2884 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2885 } else { 2886 txq->ift_pullups++; 2887 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2888 return (ENOMEM); 2889 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2890 } 2891 } else { 2892 txq->ift_pullups++; 2893 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2894 return (ENOMEM); 2895 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2896 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2897 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2898 } 2899 } else { 2900 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2901 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2902 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2903 } 2904 pi->ipi_ip_hlen = ip->ip_hl << 2; 2905 pi->ipi_ipproto = ip->ip_p; 2906 pi->ipi_flags |= IPI_TX_IPV4; 2907 2908 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 2909 ip->ip_sum = 0; 2910 2911 if (IS_TSO4(pi)) { 2912 if (pi->ipi_ipproto == IPPROTO_TCP) { 2913 if (__predict_false(th == NULL)) { 2914 txq->ift_pullups++; 2915 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2916 return (ENOMEM); 2917 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2918 } 2919 pi->ipi_tcp_hflags = th->th_flags; 2920 pi->ipi_tcp_hlen = th->th_off << 2; 2921 pi->ipi_tcp_seq = th->th_seq; 2922 } 2923 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2924 return (ENXIO); 2925 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2926 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2927 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2928 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2929 ip->ip_sum = 0; 2930 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2931 } 2932 } 2933 break; 2934 } 2935 #endif 2936 #ifdef INET6 2937 case ETHERTYPE_IPV6: 2938 { 2939 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2940 struct tcphdr *th; 2941 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2942 2943 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2944 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2945 return (ENOMEM); 2946 } 2947 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2948 2949 /* XXX-BZ this will go badly in case of ext hdrs. */ 2950 pi->ipi_ipproto = ip6->ip6_nxt; 2951 pi->ipi_flags |= IPI_TX_IPV6; 2952 2953 if (IS_TSO6(pi)) { 2954 if (pi->ipi_ipproto == IPPROTO_TCP) { 2955 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2956 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2957 return (ENOMEM); 2958 } 2959 pi->ipi_tcp_hflags = th->th_flags; 2960 pi->ipi_tcp_hlen = th->th_off << 2; 2961 } 2962 2963 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2964 return (ENXIO); 2965 /* 2966 * The corresponding flag is set by the stack in the IPv4 2967 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 2968 * So, set it here because the rest of the flow requires it. 2969 */ 2970 pi->ipi_csum_flags |= CSUM_TCP_IPV6; 2971 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2972 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2973 } 2974 break; 2975 } 2976 #endif 2977 default: 2978 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2979 pi->ipi_ip_hlen = 0; 2980 break; 2981 } 2982 *mp = m; 2983 2984 return (0); 2985 } 2986 2987 static __noinline struct mbuf * 2988 collapse_pkthdr(struct mbuf *m0) 2989 { 2990 struct mbuf *m, *m_next, *tmp; 2991 2992 m = m0; 2993 m_next = m->m_next; 2994 while (m_next != NULL && m_next->m_len == 0) { 2995 m = m_next; 2996 m->m_next = NULL; 2997 m_free(m); 2998 m_next = m_next->m_next; 2999 } 3000 m = m0; 3001 m->m_next = m_next; 3002 if ((m_next->m_flags & M_EXT) == 0) { 3003 m = m_defrag(m, M_NOWAIT); 3004 } else { 3005 tmp = m_next->m_next; 3006 memcpy(m_next, m, MPKTHSIZE); 3007 m = m_next; 3008 m->m_next = tmp; 3009 } 3010 return (m); 3011 } 3012 3013 /* 3014 * If dodgy hardware rejects the scatter gather chain we've handed it 3015 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3016 * m_defrag'd mbufs 3017 */ 3018 static __noinline struct mbuf * 3019 iflib_remove_mbuf(iflib_txq_t txq) 3020 { 3021 int ntxd, i, pidx; 3022 struct mbuf *m, *mh, **ifsd_m; 3023 3024 pidx = txq->ift_pidx; 3025 ifsd_m = txq->ift_sds.ifsd_m; 3026 ntxd = txq->ift_size; 3027 mh = m = ifsd_m[pidx]; 3028 ifsd_m[pidx] = NULL; 3029 #if MEMORY_LOGGING 3030 txq->ift_dequeued++; 3031 #endif 3032 i = 1; 3033 3034 while (m) { 3035 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 3036 #if MEMORY_LOGGING 3037 txq->ift_dequeued++; 3038 #endif 3039 m = m->m_next; 3040 i++; 3041 } 3042 return (mh); 3043 } 3044 3045 static int 3046 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 3047 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 3048 int max_segs, int flags) 3049 { 3050 if_ctx_t ctx; 3051 if_shared_ctx_t sctx; 3052 if_softc_ctx_t scctx; 3053 int i, next, pidx, err, ntxd, count; 3054 struct mbuf *m, *tmp, **ifsd_m; 3055 3056 m = *m0; 3057 3058 /* 3059 * Please don't ever do this 3060 */ 3061 if (__predict_false(m->m_len == 0)) 3062 *m0 = m = collapse_pkthdr(m); 3063 3064 ctx = txq->ift_ctx; 3065 sctx = ctx->ifc_sctx; 3066 scctx = &ctx->ifc_softc_ctx; 3067 ifsd_m = txq->ift_sds.ifsd_m; 3068 ntxd = txq->ift_size; 3069 pidx = txq->ift_pidx; 3070 if (map != NULL) { 3071 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 3072 3073 err = bus_dmamap_load_mbuf_sg(tag, map, 3074 *m0, segs, nsegs, BUS_DMA_NOWAIT); 3075 if (err) 3076 return (err); 3077 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 3078 count = 0; 3079 m = *m0; 3080 do { 3081 if (__predict_false(m->m_len <= 0)) { 3082 tmp = m; 3083 m = m->m_next; 3084 tmp->m_next = NULL; 3085 m_free(tmp); 3086 continue; 3087 } 3088 m = m->m_next; 3089 count++; 3090 } while (m != NULL); 3091 if (count > *nsegs) { 3092 ifsd_m[pidx] = *m0; 3093 ifsd_m[pidx]->m_flags |= M_TOOBIG; 3094 return (0); 3095 } 3096 m = *m0; 3097 count = 0; 3098 do { 3099 next = (pidx + count) & (ntxd-1); 3100 MPASS(ifsd_m[next] == NULL); 3101 ifsd_m[next] = m; 3102 count++; 3103 tmp = m; 3104 m = m->m_next; 3105 } while (m != NULL); 3106 } else { 3107 int buflen, sgsize, maxsegsz, max_sgsize; 3108 vm_offset_t vaddr; 3109 vm_paddr_t curaddr; 3110 3111 count = i = 0; 3112 m = *m0; 3113 if (m->m_pkthdr.csum_flags & CSUM_TSO) 3114 maxsegsz = scctx->isc_tx_tso_segsize_max; 3115 else 3116 maxsegsz = sctx->isc_tx_maxsegsize; 3117 3118 do { 3119 if (__predict_false(m->m_len <= 0)) { 3120 tmp = m; 3121 m = m->m_next; 3122 tmp->m_next = NULL; 3123 m_free(tmp); 3124 continue; 3125 } 3126 buflen = m->m_len; 3127 vaddr = (vm_offset_t)m->m_data; 3128 /* 3129 * see if we can't be smarter about physically 3130 * contiguous mappings 3131 */ 3132 next = (pidx + count) & (ntxd-1); 3133 MPASS(ifsd_m[next] == NULL); 3134 #if MEMORY_LOGGING 3135 txq->ift_enqueued++; 3136 #endif 3137 ifsd_m[next] = m; 3138 while (buflen > 0) { 3139 if (i >= max_segs) 3140 goto err; 3141 max_sgsize = MIN(buflen, maxsegsz); 3142 curaddr = pmap_kextract(vaddr); 3143 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 3144 sgsize = MIN(sgsize, max_sgsize); 3145 segs[i].ds_addr = curaddr; 3146 segs[i].ds_len = sgsize; 3147 vaddr += sgsize; 3148 buflen -= sgsize; 3149 i++; 3150 } 3151 count++; 3152 tmp = m; 3153 m = m->m_next; 3154 } while (m != NULL); 3155 *nsegs = i; 3156 } 3157 return (0); 3158 err: 3159 *m0 = iflib_remove_mbuf(txq); 3160 return (EFBIG); 3161 } 3162 3163 static inline caddr_t 3164 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3165 { 3166 qidx_t size; 3167 int ntxd; 3168 caddr_t start, end, cur, next; 3169 3170 ntxd = txq->ift_size; 3171 size = txq->ift_txd_size[qid]; 3172 start = txq->ift_ifdi[qid].idi_vaddr; 3173 3174 if (__predict_false(size == 0)) 3175 return (start); 3176 cur = start + size*cidx; 3177 end = start + size*ntxd; 3178 next = CACHE_PTR_NEXT(cur); 3179 return (next < end ? next : start); 3180 } 3181 3182 /* 3183 * Pad an mbuf to ensure a minimum ethernet frame size. 3184 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3185 */ 3186 static __noinline int 3187 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3188 { 3189 /* 3190 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3191 * and ARP message is the smallest common payload I can think of 3192 */ 3193 static char pad[18]; /* just zeros */ 3194 int n; 3195 struct mbuf *new_head; 3196 3197 if (!M_WRITABLE(*m_head)) { 3198 new_head = m_dup(*m_head, M_NOWAIT); 3199 if (new_head == NULL) { 3200 m_freem(*m_head); 3201 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3202 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3203 return ENOMEM; 3204 } 3205 m_freem(*m_head); 3206 *m_head = new_head; 3207 } 3208 3209 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3210 n > 0; n -= sizeof(pad)) 3211 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3212 break; 3213 3214 if (n > 0) { 3215 m_freem(*m_head); 3216 device_printf(dev, "cannot pad short frame\n"); 3217 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3218 return (ENOBUFS); 3219 } 3220 3221 return 0; 3222 } 3223 3224 static int 3225 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3226 { 3227 if_ctx_t ctx; 3228 if_shared_ctx_t sctx; 3229 if_softc_ctx_t scctx; 3230 bus_dma_segment_t *segs; 3231 struct mbuf *m_head; 3232 void *next_txd; 3233 bus_dmamap_t map; 3234 struct if_pkt_info pi; 3235 int remap = 0; 3236 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3237 bus_dma_tag_t desc_tag; 3238 3239 segs = txq->ift_segs; 3240 ctx = txq->ift_ctx; 3241 sctx = ctx->ifc_sctx; 3242 scctx = &ctx->ifc_softc_ctx; 3243 segs = txq->ift_segs; 3244 ntxd = txq->ift_size; 3245 m_head = *m_headp; 3246 map = NULL; 3247 3248 /* 3249 * If we're doing TSO the next descriptor to clean may be quite far ahead 3250 */ 3251 cidx = txq->ift_cidx; 3252 pidx = txq->ift_pidx; 3253 if (ctx->ifc_flags & IFC_PREFETCH) { 3254 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3255 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3256 next_txd = calc_next_txd(txq, cidx, 0); 3257 prefetch(next_txd); 3258 } 3259 3260 /* prefetch the next cache line of mbuf pointers and flags */ 3261 prefetch(&txq->ift_sds.ifsd_m[next]); 3262 if (txq->ift_sds.ifsd_map != NULL) { 3263 prefetch(&txq->ift_sds.ifsd_map[next]); 3264 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3265 prefetch(&txq->ift_sds.ifsd_flags[next]); 3266 } 3267 } else if (txq->ift_sds.ifsd_map != NULL) 3268 map = txq->ift_sds.ifsd_map[pidx]; 3269 3270 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3271 desc_tag = txq->ift_tso_desc_tag; 3272 max_segs = scctx->isc_tx_tso_segments_max; 3273 } else { 3274 desc_tag = txq->ift_desc_tag; 3275 max_segs = scctx->isc_tx_nsegments; 3276 } 3277 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3278 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3279 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3280 if (err) 3281 return err; 3282 } 3283 m_head = *m_headp; 3284 3285 pkt_info_zero(&pi); 3286 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3287 pi.ipi_pidx = pidx; 3288 pi.ipi_qsidx = txq->ift_id; 3289 pi.ipi_len = m_head->m_pkthdr.len; 3290 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3291 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3292 3293 /* deliberate bitwise OR to make one condition */ 3294 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3295 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3296 return (err); 3297 m_head = *m_headp; 3298 } 3299 3300 retry: 3301 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3302 defrag: 3303 if (__predict_false(err)) { 3304 switch (err) { 3305 case EFBIG: 3306 /* try collapse once and defrag once */ 3307 if (remap == 0) { 3308 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3309 /* try defrag if collapsing fails */ 3310 if (m_head == NULL) 3311 remap++; 3312 } 3313 if (remap == 1) 3314 m_head = m_defrag(*m_headp, M_NOWAIT); 3315 remap++; 3316 if (__predict_false(m_head == NULL)) 3317 goto defrag_failed; 3318 txq->ift_mbuf_defrag++; 3319 *m_headp = m_head; 3320 goto retry; 3321 break; 3322 case ENOMEM: 3323 txq->ift_no_tx_dma_setup++; 3324 break; 3325 default: 3326 txq->ift_no_tx_dma_setup++; 3327 m_freem(*m_headp); 3328 DBG_COUNTER_INC(tx_frees); 3329 *m_headp = NULL; 3330 break; 3331 } 3332 txq->ift_map_failed++; 3333 DBG_COUNTER_INC(encap_load_mbuf_fail); 3334 return (err); 3335 } 3336 3337 /* 3338 * XXX assumes a 1 to 1 relationship between segments and 3339 * descriptors - this does not hold true on all drivers, e.g. 3340 * cxgb 3341 */ 3342 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3343 txq->ift_no_desc_avail++; 3344 if (map != NULL) 3345 bus_dmamap_unload(desc_tag, map); 3346 DBG_COUNTER_INC(encap_txq_avail_fail); 3347 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3348 GROUPTASK_ENQUEUE(&txq->ift_task); 3349 return (ENOBUFS); 3350 } 3351 /* 3352 * On Intel cards we can greatly reduce the number of TX interrupts 3353 * we see by only setting report status on every Nth descriptor. 3354 * However, this also means that the driver will need to keep track 3355 * of the descriptors that RS was set on to check them for the DD bit. 3356 */ 3357 txq->ift_rs_pending += nsegs + 1; 3358 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3359 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3360 pi.ipi_flags |= IPI_TX_INTR; 3361 txq->ift_rs_pending = 0; 3362 } 3363 3364 pi.ipi_segs = segs; 3365 pi.ipi_nsegs = nsegs; 3366 3367 MPASS(pidx >= 0 && pidx < txq->ift_size); 3368 #ifdef PKT_DEBUG 3369 print_pkt(&pi); 3370 #endif 3371 if (map != NULL) 3372 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3373 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3374 if (map != NULL) 3375 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3376 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3377 DBG_COUNTER_INC(tx_encap); 3378 MPASS(pi.ipi_new_pidx < txq->ift_size); 3379 3380 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3381 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3382 ndesc += txq->ift_size; 3383 txq->ift_gen = 1; 3384 } 3385 /* 3386 * drivers can need as many as 3387 * two sentinels 3388 */ 3389 MPASS(ndesc <= pi.ipi_nsegs + 2); 3390 MPASS(pi.ipi_new_pidx != pidx); 3391 MPASS(ndesc > 0); 3392 txq->ift_in_use += ndesc; 3393 3394 /* 3395 * We update the last software descriptor again here because there may 3396 * be a sentinel and/or there may be more mbufs than segments 3397 */ 3398 txq->ift_pidx = pi.ipi_new_pidx; 3399 txq->ift_npending += pi.ipi_ndescs; 3400 } else { 3401 *m_headp = m_head = iflib_remove_mbuf(txq); 3402 if (err == EFBIG) { 3403 txq->ift_txd_encap_efbig++; 3404 if (remap < 2) { 3405 remap = 1; 3406 goto defrag; 3407 } 3408 } 3409 DBG_COUNTER_INC(encap_txd_encap_fail); 3410 goto defrag_failed; 3411 } 3412 return (err); 3413 3414 defrag_failed: 3415 txq->ift_mbuf_defrag_failed++; 3416 txq->ift_map_failed++; 3417 m_freem(*m_headp); 3418 DBG_COUNTER_INC(tx_frees); 3419 *m_headp = NULL; 3420 return (ENOMEM); 3421 } 3422 3423 static void 3424 iflib_tx_desc_free(iflib_txq_t txq, int n) 3425 { 3426 int hasmap; 3427 uint32_t qsize, cidx, mask, gen; 3428 struct mbuf *m, **ifsd_m; 3429 uint8_t *ifsd_flags; 3430 bus_dmamap_t *ifsd_map; 3431 bool do_prefetch; 3432 3433 cidx = txq->ift_cidx; 3434 gen = txq->ift_gen; 3435 qsize = txq->ift_size; 3436 mask = qsize-1; 3437 hasmap = txq->ift_sds.ifsd_map != NULL; 3438 ifsd_flags = txq->ift_sds.ifsd_flags; 3439 ifsd_m = txq->ift_sds.ifsd_m; 3440 ifsd_map = txq->ift_sds.ifsd_map; 3441 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3442 3443 while (n-- > 0) { 3444 if (do_prefetch) { 3445 prefetch(ifsd_m[(cidx + 3) & mask]); 3446 prefetch(ifsd_m[(cidx + 4) & mask]); 3447 } 3448 if (ifsd_m[cidx] != NULL) { 3449 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3450 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3451 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3452 /* 3453 * does it matter if it's not the TSO tag? If so we'll 3454 * have to add the type to flags 3455 */ 3456 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3457 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3458 } 3459 if ((m = ifsd_m[cidx]) != NULL) { 3460 /* XXX we don't support any drivers that batch packets yet */ 3461 MPASS(m->m_nextpkt == NULL); 3462 /* if the number of clusters exceeds the number of segments 3463 * there won't be space on the ring to save a pointer to each 3464 * cluster so we simply free the list here 3465 */ 3466 if (m->m_flags & M_TOOBIG) { 3467 m_freem(m); 3468 } else { 3469 m_free(m); 3470 } 3471 ifsd_m[cidx] = NULL; 3472 #if MEMORY_LOGGING 3473 txq->ift_dequeued++; 3474 #endif 3475 DBG_COUNTER_INC(tx_frees); 3476 } 3477 } 3478 if (__predict_false(++cidx == qsize)) { 3479 cidx = 0; 3480 gen = 0; 3481 } 3482 } 3483 txq->ift_cidx = cidx; 3484 txq->ift_gen = gen; 3485 } 3486 3487 static __inline int 3488 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3489 { 3490 int reclaim; 3491 if_ctx_t ctx = txq->ift_ctx; 3492 3493 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3494 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3495 3496 /* 3497 * Need a rate-limiting check so that this isn't called every time 3498 */ 3499 iflib_tx_credits_update(ctx, txq); 3500 reclaim = DESC_RECLAIMABLE(txq); 3501 3502 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3503 #ifdef INVARIANTS 3504 if (iflib_verbose_debug) { 3505 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3506 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3507 reclaim, thresh); 3508 3509 } 3510 #endif 3511 return (0); 3512 } 3513 iflib_tx_desc_free(txq, reclaim); 3514 txq->ift_cleaned += reclaim; 3515 txq->ift_in_use -= reclaim; 3516 3517 return (reclaim); 3518 } 3519 3520 static struct mbuf ** 3521 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3522 { 3523 int next, size; 3524 struct mbuf **items; 3525 3526 size = r->size; 3527 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3528 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3529 3530 prefetch(items[(cidx + offset) & (size-1)]); 3531 if (remaining > 1) { 3532 prefetch2cachelines(&items[next]); 3533 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3534 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3535 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3536 } 3537 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3538 } 3539 3540 static void 3541 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3542 { 3543 3544 ifmp_ring_check_drainage(txq->ift_br, budget); 3545 } 3546 3547 static uint32_t 3548 iflib_txq_can_drain(struct ifmp_ring *r) 3549 { 3550 iflib_txq_t txq = r->cookie; 3551 if_ctx_t ctx = txq->ift_ctx; 3552 3553 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3554 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3555 } 3556 3557 static uint32_t 3558 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3559 { 3560 iflib_txq_t txq = r->cookie; 3561 if_ctx_t ctx = txq->ift_ctx; 3562 struct ifnet *ifp = ctx->ifc_ifp; 3563 struct mbuf **mp, *m; 3564 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3565 int reclaimed, err, in_use_prev, desc_used; 3566 bool do_prefetch, ring, rang; 3567 3568 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3569 !LINK_ACTIVE(ctx))) { 3570 DBG_COUNTER_INC(txq_drain_notready); 3571 return (0); 3572 } 3573 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3574 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3575 avail = IDXDIFF(pidx, cidx, r->size); 3576 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3577 DBG_COUNTER_INC(txq_drain_flushing); 3578 for (i = 0; i < avail; i++) { 3579 m_free(r->items[(cidx + i) & (r->size-1)]); 3580 r->items[(cidx + i) & (r->size-1)] = NULL; 3581 } 3582 return (avail); 3583 } 3584 3585 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3586 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3587 CALLOUT_LOCK(txq); 3588 callout_stop(&txq->ift_timer); 3589 CALLOUT_UNLOCK(txq); 3590 DBG_COUNTER_INC(txq_drain_oactive); 3591 return (0); 3592 } 3593 if (reclaimed) 3594 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3595 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3596 count = MIN(avail, TX_BATCH_SIZE); 3597 #ifdef INVARIANTS 3598 if (iflib_verbose_debug) 3599 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3600 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3601 #endif 3602 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3603 avail = TXQ_AVAIL(txq); 3604 err = 0; 3605 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3606 int rem = do_prefetch ? count - i : 0; 3607 3608 mp = _ring_peek_one(r, cidx, i, rem); 3609 MPASS(mp != NULL && *mp != NULL); 3610 if (__predict_false(*mp == (struct mbuf *)txq)) { 3611 consumed++; 3612 reclaimed++; 3613 continue; 3614 } 3615 in_use_prev = txq->ift_in_use; 3616 err = iflib_encap(txq, mp); 3617 if (__predict_false(err)) { 3618 DBG_COUNTER_INC(txq_drain_encapfail); 3619 /* no room - bail out */ 3620 if (err == ENOBUFS) 3621 break; 3622 consumed++; 3623 DBG_COUNTER_INC(txq_drain_encapfail); 3624 /* we can't send this packet - skip it */ 3625 continue; 3626 } 3627 consumed++; 3628 pkt_sent++; 3629 m = *mp; 3630 DBG_COUNTER_INC(tx_sent); 3631 bytes_sent += m->m_pkthdr.len; 3632 mcast_sent += !!(m->m_flags & M_MCAST); 3633 avail = TXQ_AVAIL(txq); 3634 3635 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3636 desc_used += (txq->ift_in_use - in_use_prev); 3637 ETHER_BPF_MTAP(ifp, m); 3638 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3639 break; 3640 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3641 } 3642 3643 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3644 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3645 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3646 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3647 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3648 if (mcast_sent) 3649 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3650 #ifdef INVARIANTS 3651 if (iflib_verbose_debug) 3652 printf("consumed=%d\n", consumed); 3653 #endif 3654 return (consumed); 3655 } 3656 3657 static uint32_t 3658 iflib_txq_drain_always(struct ifmp_ring *r) 3659 { 3660 return (1); 3661 } 3662 3663 static uint32_t 3664 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3665 { 3666 int i, avail; 3667 struct mbuf **mp; 3668 iflib_txq_t txq; 3669 3670 txq = r->cookie; 3671 3672 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3673 CALLOUT_LOCK(txq); 3674 callout_stop(&txq->ift_timer); 3675 CALLOUT_UNLOCK(txq); 3676 3677 avail = IDXDIFF(pidx, cidx, r->size); 3678 for (i = 0; i < avail; i++) { 3679 mp = _ring_peek_one(r, cidx, i, avail - i); 3680 if (__predict_false(*mp == (struct mbuf *)txq)) 3681 continue; 3682 m_freem(*mp); 3683 } 3684 MPASS(ifmp_ring_is_stalled(r) == 0); 3685 return (avail); 3686 } 3687 3688 static void 3689 iflib_ifmp_purge(iflib_txq_t txq) 3690 { 3691 struct ifmp_ring *r; 3692 3693 r = txq->ift_br; 3694 r->drain = iflib_txq_drain_free; 3695 r->can_drain = iflib_txq_drain_always; 3696 3697 ifmp_ring_check_drainage(r, r->size); 3698 3699 r->drain = iflib_txq_drain; 3700 r->can_drain = iflib_txq_can_drain; 3701 } 3702 3703 static void 3704 _task_fn_tx(void *context) 3705 { 3706 iflib_txq_t txq = context; 3707 if_ctx_t ctx = txq->ift_ctx; 3708 struct ifnet *ifp = ctx->ifc_ifp; 3709 3710 #ifdef IFLIB_DIAGNOSTICS 3711 txq->ift_cpu_exec_count[curcpu]++; 3712 #endif 3713 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3714 return; 3715 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3716 /* 3717 * If there are no available credits, and TX IRQs are not in use, 3718 * re-schedule the task immediately. 3719 */ 3720 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3721 netmap_tx_irq(ifp, txq->ift_id); 3722 else { 3723 #ifdef DEV_NETMAP 3724 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 3725 struct netmap_kring *kring = NA(ctx->ifc_ifp)->tx_rings[txq->ift_id]; 3726 3727 if (kring->nr_hwtail != nm_prev(kring->rhead, kring->nkr_num_slots - 1)) 3728 GROUPTASK_ENQUEUE(&txq->ift_task); 3729 } 3730 #endif 3731 } 3732 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3733 return; 3734 } 3735 if (txq->ift_db_pending) 3736 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); 3737 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3738 if (ctx->ifc_flags & IFC_LEGACY) 3739 IFDI_INTR_ENABLE(ctx); 3740 else { 3741 #ifdef INVARIANTS 3742 int rc = 3743 #endif 3744 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3745 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3746 } 3747 } 3748 3749 static void 3750 _task_fn_rx(void *context) 3751 { 3752 iflib_rxq_t rxq = context; 3753 if_ctx_t ctx = rxq->ifr_ctx; 3754 bool more; 3755 uint16_t budget; 3756 3757 #ifdef IFLIB_DIAGNOSTICS 3758 rxq->ifr_cpu_exec_count[curcpu]++; 3759 #endif 3760 DBG_COUNTER_INC(task_fn_rxs); 3761 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3762 return; 3763 more = true; 3764 #ifdef DEV_NETMAP 3765 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3766 u_int work = 0; 3767 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3768 more = false; 3769 } 3770 } 3771 #endif 3772 budget = ctx->ifc_sysctl_rx_budget; 3773 if (budget == 0) 3774 budget = 16; /* XXX */ 3775 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3776 if (ctx->ifc_flags & IFC_LEGACY) 3777 IFDI_INTR_ENABLE(ctx); 3778 else { 3779 #ifdef INVARIANTS 3780 int rc = 3781 #endif 3782 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3783 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3784 DBG_COUNTER_INC(rx_intr_enables); 3785 } 3786 } 3787 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3788 return; 3789 if (more) 3790 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3791 } 3792 3793 static void 3794 _task_fn_admin(void *context) 3795 { 3796 if_ctx_t ctx = context; 3797 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3798 iflib_txq_t txq; 3799 int i; 3800 bool oactive, running, do_reset, do_watchdog; 3801 3802 STATE_LOCK(ctx); 3803 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3804 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3805 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3806 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3807 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3808 STATE_UNLOCK(ctx); 3809 3810 if ((!running & !oactive) && 3811 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3812 return; 3813 3814 CTX_LOCK(ctx); 3815 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3816 CALLOUT_LOCK(txq); 3817 callout_stop(&txq->ift_timer); 3818 CALLOUT_UNLOCK(txq); 3819 } 3820 if (do_watchdog) { 3821 ctx->ifc_watchdog_events++; 3822 IFDI_WATCHDOG_RESET(ctx); 3823 } 3824 IFDI_UPDATE_ADMIN_STATUS(ctx); 3825 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3826 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 3827 IFDI_LINK_INTR_ENABLE(ctx); 3828 if (do_reset) 3829 iflib_if_init_locked(ctx); 3830 CTX_UNLOCK(ctx); 3831 3832 if (LINK_ACTIVE(ctx) == 0) 3833 return; 3834 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3835 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3836 } 3837 3838 3839 static void 3840 _task_fn_iov(void *context) 3841 { 3842 if_ctx_t ctx = context; 3843 3844 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3845 return; 3846 3847 CTX_LOCK(ctx); 3848 IFDI_VFLR_HANDLE(ctx); 3849 CTX_UNLOCK(ctx); 3850 } 3851 3852 static int 3853 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3854 { 3855 int err; 3856 if_int_delay_info_t info; 3857 if_ctx_t ctx; 3858 3859 info = (if_int_delay_info_t)arg1; 3860 ctx = info->iidi_ctx; 3861 info->iidi_req = req; 3862 info->iidi_oidp = oidp; 3863 CTX_LOCK(ctx); 3864 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3865 CTX_UNLOCK(ctx); 3866 return (err); 3867 } 3868 3869 /********************************************************************* 3870 * 3871 * IFNET FUNCTIONS 3872 * 3873 **********************************************************************/ 3874 3875 static void 3876 iflib_if_init_locked(if_ctx_t ctx) 3877 { 3878 iflib_stop(ctx); 3879 iflib_init_locked(ctx); 3880 } 3881 3882 3883 static void 3884 iflib_if_init(void *arg) 3885 { 3886 if_ctx_t ctx = arg; 3887 3888 CTX_LOCK(ctx); 3889 iflib_if_init_locked(ctx); 3890 CTX_UNLOCK(ctx); 3891 } 3892 3893 static int 3894 iflib_if_transmit(if_t ifp, struct mbuf *m) 3895 { 3896 if_ctx_t ctx = if_getsoftc(ifp); 3897 3898 iflib_txq_t txq; 3899 int err, qidx; 3900 3901 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3902 DBG_COUNTER_INC(tx_frees); 3903 m_freem(m); 3904 return (ENOBUFS); 3905 } 3906 3907 MPASS(m->m_nextpkt == NULL); 3908 qidx = 0; 3909 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3910 qidx = QIDX(ctx, m); 3911 /* 3912 * XXX calculate buf_ring based on flowid (divvy up bits?) 3913 */ 3914 txq = &ctx->ifc_txqs[qidx]; 3915 3916 #ifdef DRIVER_BACKPRESSURE 3917 if (txq->ift_closed) { 3918 while (m != NULL) { 3919 next = m->m_nextpkt; 3920 m->m_nextpkt = NULL; 3921 m_freem(m); 3922 m = next; 3923 } 3924 return (ENOBUFS); 3925 } 3926 #endif 3927 #ifdef notyet 3928 qidx = count = 0; 3929 mp = marr; 3930 next = m; 3931 do { 3932 count++; 3933 next = next->m_nextpkt; 3934 } while (next != NULL); 3935 3936 if (count > nitems(marr)) 3937 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3938 /* XXX check nextpkt */ 3939 m_freem(m); 3940 /* XXX simplify for now */ 3941 DBG_COUNTER_INC(tx_frees); 3942 return (ENOBUFS); 3943 } 3944 for (next = m, i = 0; next != NULL; i++) { 3945 mp[i] = next; 3946 next = next->m_nextpkt; 3947 mp[i]->m_nextpkt = NULL; 3948 } 3949 #endif 3950 DBG_COUNTER_INC(tx_seen); 3951 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); 3952 3953 GROUPTASK_ENQUEUE(&txq->ift_task); 3954 if (err) { 3955 /* support forthcoming later */ 3956 #ifdef DRIVER_BACKPRESSURE 3957 txq->ift_closed = TRUE; 3958 #endif 3959 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3960 m_freem(m); 3961 } 3962 3963 return (err); 3964 } 3965 3966 static void 3967 iflib_if_qflush(if_t ifp) 3968 { 3969 if_ctx_t ctx = if_getsoftc(ifp); 3970 iflib_txq_t txq = ctx->ifc_txqs; 3971 int i; 3972 3973 STATE_LOCK(ctx); 3974 ctx->ifc_flags |= IFC_QFLUSH; 3975 STATE_UNLOCK(ctx); 3976 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3977 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3978 iflib_txq_check_drain(txq, 0); 3979 STATE_LOCK(ctx); 3980 ctx->ifc_flags &= ~IFC_QFLUSH; 3981 STATE_UNLOCK(ctx); 3982 3983 if_qflush(ifp); 3984 } 3985 3986 3987 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3988 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 3989 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 3990 3991 static int 3992 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 3993 { 3994 if_ctx_t ctx = if_getsoftc(ifp); 3995 struct ifreq *ifr = (struct ifreq *)data; 3996 #if defined(INET) || defined(INET6) 3997 struct ifaddr *ifa = (struct ifaddr *)data; 3998 #endif 3999 bool avoid_reset = FALSE; 4000 int err = 0, reinit = 0, bits; 4001 4002 switch (command) { 4003 case SIOCSIFADDR: 4004 #ifdef INET 4005 if (ifa->ifa_addr->sa_family == AF_INET) 4006 avoid_reset = TRUE; 4007 #endif 4008 #ifdef INET6 4009 if (ifa->ifa_addr->sa_family == AF_INET6) 4010 avoid_reset = TRUE; 4011 #endif 4012 /* 4013 ** Calling init results in link renegotiation, 4014 ** so we avoid doing it when possible. 4015 */ 4016 if (avoid_reset) { 4017 if_setflagbits(ifp, IFF_UP,0); 4018 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING)) 4019 reinit = 1; 4020 #ifdef INET 4021 if (!(if_getflags(ifp) & IFF_NOARP)) 4022 arp_ifinit(ifp, ifa); 4023 #endif 4024 } else 4025 err = ether_ioctl(ifp, command, data); 4026 break; 4027 case SIOCSIFMTU: 4028 CTX_LOCK(ctx); 4029 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4030 CTX_UNLOCK(ctx); 4031 break; 4032 } 4033 bits = if_getdrvflags(ifp); 4034 /* stop the driver and free any clusters before proceeding */ 4035 iflib_stop(ctx); 4036 4037 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4038 STATE_LOCK(ctx); 4039 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4040 ctx->ifc_flags |= IFC_MULTISEG; 4041 else 4042 ctx->ifc_flags &= ~IFC_MULTISEG; 4043 STATE_UNLOCK(ctx); 4044 err = if_setmtu(ifp, ifr->ifr_mtu); 4045 } 4046 iflib_init_locked(ctx); 4047 STATE_LOCK(ctx); 4048 if_setdrvflags(ifp, bits); 4049 STATE_UNLOCK(ctx); 4050 CTX_UNLOCK(ctx); 4051 break; 4052 case SIOCSIFFLAGS: 4053 CTX_LOCK(ctx); 4054 if (if_getflags(ifp) & IFF_UP) { 4055 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4056 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4057 (IFF_PROMISC | IFF_ALLMULTI)) { 4058 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4059 } 4060 } else 4061 reinit = 1; 4062 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4063 iflib_stop(ctx); 4064 } 4065 ctx->ifc_if_flags = if_getflags(ifp); 4066 CTX_UNLOCK(ctx); 4067 break; 4068 case SIOCADDMULTI: 4069 case SIOCDELMULTI: 4070 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4071 CTX_LOCK(ctx); 4072 IFDI_INTR_DISABLE(ctx); 4073 IFDI_MULTI_SET(ctx); 4074 IFDI_INTR_ENABLE(ctx); 4075 CTX_UNLOCK(ctx); 4076 } 4077 break; 4078 case SIOCSIFMEDIA: 4079 CTX_LOCK(ctx); 4080 IFDI_MEDIA_SET(ctx); 4081 CTX_UNLOCK(ctx); 4082 /* falls thru */ 4083 case SIOCGIFMEDIA: 4084 case SIOCGIFXMEDIA: 4085 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 4086 break; 4087 case SIOCGI2C: 4088 { 4089 struct ifi2creq i2c; 4090 4091 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4092 if (err != 0) 4093 break; 4094 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4095 err = EINVAL; 4096 break; 4097 } 4098 if (i2c.len > sizeof(i2c.data)) { 4099 err = EINVAL; 4100 break; 4101 } 4102 4103 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4104 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4105 sizeof(i2c)); 4106 break; 4107 } 4108 case SIOCSIFCAP: 4109 { 4110 int mask, setmask; 4111 4112 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 4113 setmask = 0; 4114 #ifdef TCP_OFFLOAD 4115 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4116 #endif 4117 setmask |= (mask & IFCAP_FLAGS); 4118 4119 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 4120 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4121 if ((mask & IFCAP_WOL) && 4122 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 4123 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 4124 if_vlancap(ifp); 4125 /* 4126 * want to ensure that traffic has stopped before we change any of the flags 4127 */ 4128 if (setmask) { 4129 CTX_LOCK(ctx); 4130 bits = if_getdrvflags(ifp); 4131 if (bits & IFF_DRV_RUNNING) 4132 iflib_stop(ctx); 4133 STATE_LOCK(ctx); 4134 if_togglecapenable(ifp, setmask); 4135 STATE_UNLOCK(ctx); 4136 if (bits & IFF_DRV_RUNNING) 4137 iflib_init_locked(ctx); 4138 STATE_LOCK(ctx); 4139 if_setdrvflags(ifp, bits); 4140 STATE_UNLOCK(ctx); 4141 CTX_UNLOCK(ctx); 4142 } 4143 break; 4144 } 4145 case SIOCGPRIVATE_0: 4146 case SIOCSDRVSPEC: 4147 case SIOCGDRVSPEC: 4148 CTX_LOCK(ctx); 4149 err = IFDI_PRIV_IOCTL(ctx, command, data); 4150 CTX_UNLOCK(ctx); 4151 break; 4152 default: 4153 err = ether_ioctl(ifp, command, data); 4154 break; 4155 } 4156 if (reinit) 4157 iflib_if_init(ctx); 4158 return (err); 4159 } 4160 4161 static uint64_t 4162 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4163 { 4164 if_ctx_t ctx = if_getsoftc(ifp); 4165 4166 return (IFDI_GET_COUNTER(ctx, cnt)); 4167 } 4168 4169 /********************************************************************* 4170 * 4171 * OTHER FUNCTIONS EXPORTED TO THE STACK 4172 * 4173 **********************************************************************/ 4174 4175 static void 4176 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4177 { 4178 if_ctx_t ctx = if_getsoftc(ifp); 4179 4180 if ((void *)ctx != arg) 4181 return; 4182 4183 if ((vtag == 0) || (vtag > 4095)) 4184 return; 4185 4186 CTX_LOCK(ctx); 4187 IFDI_VLAN_REGISTER(ctx, vtag); 4188 /* Re-init to load the changes */ 4189 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4190 iflib_if_init_locked(ctx); 4191 CTX_UNLOCK(ctx); 4192 } 4193 4194 static void 4195 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4196 { 4197 if_ctx_t ctx = if_getsoftc(ifp); 4198 4199 if ((void *)ctx != arg) 4200 return; 4201 4202 if ((vtag == 0) || (vtag > 4095)) 4203 return; 4204 4205 CTX_LOCK(ctx); 4206 IFDI_VLAN_UNREGISTER(ctx, vtag); 4207 /* Re-init to load the changes */ 4208 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4209 iflib_if_init_locked(ctx); 4210 CTX_UNLOCK(ctx); 4211 } 4212 4213 static void 4214 iflib_led_func(void *arg, int onoff) 4215 { 4216 if_ctx_t ctx = arg; 4217 4218 CTX_LOCK(ctx); 4219 IFDI_LED_FUNC(ctx, onoff); 4220 CTX_UNLOCK(ctx); 4221 } 4222 4223 /********************************************************************* 4224 * 4225 * BUS FUNCTION DEFINITIONS 4226 * 4227 **********************************************************************/ 4228 4229 int 4230 iflib_device_probe(device_t dev) 4231 { 4232 pci_vendor_info_t *ent; 4233 4234 uint16_t pci_vendor_id, pci_device_id; 4235 uint16_t pci_subvendor_id, pci_subdevice_id; 4236 uint16_t pci_rev_id; 4237 if_shared_ctx_t sctx; 4238 4239 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4240 return (ENOTSUP); 4241 4242 pci_vendor_id = pci_get_vendor(dev); 4243 pci_device_id = pci_get_device(dev); 4244 pci_subvendor_id = pci_get_subvendor(dev); 4245 pci_subdevice_id = pci_get_subdevice(dev); 4246 pci_rev_id = pci_get_revid(dev); 4247 if (sctx->isc_parse_devinfo != NULL) 4248 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4249 4250 ent = sctx->isc_vendor_info; 4251 while (ent->pvi_vendor_id != 0) { 4252 if (pci_vendor_id != ent->pvi_vendor_id) { 4253 ent++; 4254 continue; 4255 } 4256 if ((pci_device_id == ent->pvi_device_id) && 4257 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4258 (ent->pvi_subvendor_id == 0)) && 4259 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4260 (ent->pvi_subdevice_id == 0)) && 4261 ((pci_rev_id == ent->pvi_rev_id) || 4262 (ent->pvi_rev_id == 0))) { 4263 4264 device_set_desc_copy(dev, ent->pvi_name); 4265 /* this needs to be changed to zero if the bus probing code 4266 * ever stops re-probing on best match because the sctx 4267 * may have its values over written by register calls 4268 * in subsequent probes 4269 */ 4270 return (BUS_PROBE_DEFAULT); 4271 } 4272 ent++; 4273 } 4274 return (ENXIO); 4275 } 4276 4277 static void 4278 iflib_reset_qvalues(if_ctx_t ctx) 4279 { 4280 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4281 if_shared_ctx_t sctx = ctx->ifc_sctx; 4282 device_t dev = ctx->ifc_dev; 4283 int i; 4284 4285 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES; 4286 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH; 4287 /* 4288 * XXX sanity check that ntxd & nrxd are a power of 2 4289 */ 4290 if (ctx->ifc_sysctl_ntxqs != 0) 4291 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4292 if (ctx->ifc_sysctl_nrxqs != 0) 4293 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4294 4295 for (i = 0; i < sctx->isc_ntxqs; i++) { 4296 if (ctx->ifc_sysctl_ntxds[i] != 0) 4297 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4298 else 4299 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4300 } 4301 4302 for (i = 0; i < sctx->isc_nrxqs; i++) { 4303 if (ctx->ifc_sysctl_nrxds[i] != 0) 4304 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4305 else 4306 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4307 } 4308 4309 for (i = 0; i < sctx->isc_nrxqs; i++) { 4310 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4311 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4312 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4313 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4314 } 4315 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4316 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4317 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4318 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4319 } 4320 } 4321 4322 for (i = 0; i < sctx->isc_ntxqs; i++) { 4323 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4324 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4325 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4326 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4327 } 4328 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4329 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4330 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4331 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4332 } 4333 } 4334 } 4335 4336 int 4337 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4338 { 4339 int err, rid, msix; 4340 if_ctx_t ctx; 4341 if_t ifp; 4342 if_softc_ctx_t scctx; 4343 int i; 4344 uint16_t main_txq; 4345 uint16_t main_rxq; 4346 4347 4348 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4349 4350 if (sc == NULL) { 4351 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4352 device_set_softc(dev, ctx); 4353 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4354 } 4355 4356 ctx->ifc_sctx = sctx; 4357 ctx->ifc_dev = dev; 4358 ctx->ifc_softc = sc; 4359 4360 if ((err = iflib_register(ctx)) != 0) { 4361 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4362 free(sc, M_IFLIB); 4363 free(ctx, M_IFLIB); 4364 device_printf(dev, "iflib_register failed %d\n", err); 4365 return (err); 4366 } 4367 iflib_add_device_sysctl_pre(ctx); 4368 4369 scctx = &ctx->ifc_softc_ctx; 4370 ifp = ctx->ifc_ifp; 4371 4372 iflib_reset_qvalues(ctx); 4373 CTX_LOCK(ctx); 4374 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4375 CTX_UNLOCK(ctx); 4376 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4377 return (err); 4378 } 4379 _iflib_pre_assert(scctx); 4380 ctx->ifc_txrx = *scctx->isc_txrx; 4381 4382 #ifdef INVARIANTS 4383 MPASS(scctx->isc_capenable); 4384 if (scctx->isc_capenable & IFCAP_TXCSUM) 4385 MPASS(scctx->isc_tx_csum_flags); 4386 #endif 4387 4388 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4389 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4390 4391 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4392 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4393 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4394 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4395 4396 #ifdef ACPI_DMAR 4397 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4398 ctx->ifc_flags |= IFC_DMAR; 4399 #elif !(defined(__i386__) || defined(__amd64__)) 4400 /* set unconditionally for !x86 */ 4401 ctx->ifc_flags |= IFC_DMAR; 4402 #endif 4403 4404 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4405 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4406 4407 /* XXX change for per-queue sizes */ 4408 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4409 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4410 for (i = 0; i < sctx->isc_nrxqs; i++) { 4411 if (!powerof2(scctx->isc_nrxd[i])) { 4412 /* round down instead? */ 4413 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4414 err = EINVAL; 4415 goto fail; 4416 } 4417 } 4418 for (i = 0; i < sctx->isc_ntxqs; i++) { 4419 if (!powerof2(scctx->isc_ntxd[i])) { 4420 device_printf(dev, 4421 "# tx descriptors must be a power of 2"); 4422 err = EINVAL; 4423 goto fail; 4424 } 4425 } 4426 4427 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4428 MAX_SINGLE_PACKET_FRACTION) 4429 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4430 MAX_SINGLE_PACKET_FRACTION); 4431 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4432 MAX_SINGLE_PACKET_FRACTION) 4433 scctx->isc_tx_tso_segments_max = max(1, 4434 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4435 4436 /* 4437 * Protect the stack against modern hardware 4438 */ 4439 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4440 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4441 4442 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4443 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4444 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4445 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4446 if (scctx->isc_rss_table_size == 0) 4447 scctx->isc_rss_table_size = 64; 4448 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4449 4450 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4451 /* XXX format name */ 4452 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4453 4454 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4455 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4456 device_printf(dev, "Unable to fetch CPU list\n"); 4457 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4458 } 4459 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4460 4461 /* 4462 ** Now setup MSI or MSI/X, should 4463 ** return us the number of supported 4464 ** vectors. (Will be 1 for MSI) 4465 */ 4466 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4467 msix = scctx->isc_vectors; 4468 } else if (scctx->isc_msix_bar != 0) 4469 /* 4470 * The simple fact that isc_msix_bar is not 0 does not mean we 4471 * we have a good value there that is known to work. 4472 */ 4473 msix = iflib_msix_init(ctx); 4474 else { 4475 scctx->isc_vectors = 1; 4476 scctx->isc_ntxqsets = 1; 4477 scctx->isc_nrxqsets = 1; 4478 scctx->isc_intr = IFLIB_INTR_LEGACY; 4479 msix = 0; 4480 } 4481 /* Get memory for the station queues */ 4482 if ((err = iflib_queues_alloc(ctx))) { 4483 device_printf(dev, "Unable to allocate queue memory\n"); 4484 goto fail; 4485 } 4486 4487 if ((err = iflib_qset_structures_setup(ctx))) 4488 goto fail_queues; 4489 4490 /* 4491 * Group taskqueues aren't properly set up until SMP is started, 4492 * so we disable interrupts until we can handle them post 4493 * SI_SUB_SMP. 4494 * 4495 * XXX: disabling interrupts doesn't actually work, at least for 4496 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4497 * we do null handling and depend on this not causing too large an 4498 * interrupt storm. 4499 */ 4500 IFDI_INTR_DISABLE(ctx); 4501 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4502 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4503 goto fail_intr_free; 4504 } 4505 if (msix <= 1) { 4506 rid = 0; 4507 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4508 MPASS(msix == 1); 4509 rid = 1; 4510 } 4511 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4512 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4513 goto fail_intr_free; 4514 } 4515 } 4516 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4517 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4518 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4519 goto fail_detach; 4520 } 4521 if ((err = iflib_netmap_attach(ctx))) { 4522 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4523 goto fail_detach; 4524 } 4525 *ctxp = ctx; 4526 4527 NETDUMP_SET(ctx->ifc_ifp, iflib); 4528 4529 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4530 iflib_add_device_sysctl_post(ctx); 4531 ctx->ifc_flags |= IFC_INIT_DONE; 4532 CTX_UNLOCK(ctx); 4533 return (0); 4534 fail_detach: 4535 ether_ifdetach(ctx->ifc_ifp); 4536 fail_intr_free: 4537 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4538 pci_release_msi(ctx->ifc_dev); 4539 fail_queues: 4540 iflib_tx_structures_free(ctx); 4541 iflib_rx_structures_free(ctx); 4542 fail: 4543 IFDI_DETACH(ctx); 4544 CTX_UNLOCK(ctx); 4545 return (err); 4546 } 4547 4548 int 4549 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4550 struct iflib_cloneattach_ctx *clctx) 4551 { 4552 int err; 4553 if_ctx_t ctx; 4554 if_t ifp; 4555 if_softc_ctx_t scctx; 4556 int i; 4557 void *sc; 4558 uint16_t main_txq; 4559 uint16_t main_rxq; 4560 4561 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4562 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4563 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4564 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4565 ctx->ifc_flags |= IFC_PSEUDO; 4566 4567 ctx->ifc_sctx = sctx; 4568 ctx->ifc_softc = sc; 4569 ctx->ifc_dev = dev; 4570 4571 if ((err = iflib_register(ctx)) != 0) { 4572 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4573 free(sc, M_IFLIB); 4574 free(ctx, M_IFLIB); 4575 return (err); 4576 } 4577 iflib_add_device_sysctl_pre(ctx); 4578 4579 scctx = &ctx->ifc_softc_ctx; 4580 ifp = ctx->ifc_ifp; 4581 4582 /* 4583 * XXX sanity check that ntxd & nrxd are a power of 2 4584 */ 4585 iflib_reset_qvalues(ctx); 4586 4587 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4588 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4589 return (err); 4590 } 4591 if (sctx->isc_flags & IFLIB_GEN_MAC) 4592 iflib_gen_mac(ctx); 4593 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4594 clctx->cc_params)) != 0) { 4595 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4596 return (err); 4597 } 4598 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4599 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 4600 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO); 4601 4602 #ifdef INVARIANTS 4603 MPASS(scctx->isc_capenable); 4604 if (scctx->isc_capenable & IFCAP_TXCSUM) 4605 MPASS(scctx->isc_tx_csum_flags); 4606 #endif 4607 4608 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4609 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4610 4611 ifp->if_flags |= IFF_NOGROUP; 4612 if (sctx->isc_flags & IFLIB_PSEUDO) { 4613 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4614 4615 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4616 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4617 goto fail_detach; 4618 } 4619 *ctxp = ctx; 4620 4621 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4622 iflib_add_device_sysctl_post(ctx); 4623 ctx->ifc_flags |= IFC_INIT_DONE; 4624 return (0); 4625 } 4626 _iflib_pre_assert(scctx); 4627 ctx->ifc_txrx = *scctx->isc_txrx; 4628 4629 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4630 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4631 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4632 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4633 4634 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4635 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4636 4637 /* XXX change for per-queue sizes */ 4638 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4639 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4640 for (i = 0; i < sctx->isc_nrxqs; i++) { 4641 if (!powerof2(scctx->isc_nrxd[i])) { 4642 /* round down instead? */ 4643 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4644 err = EINVAL; 4645 goto fail; 4646 } 4647 } 4648 for (i = 0; i < sctx->isc_ntxqs; i++) { 4649 if (!powerof2(scctx->isc_ntxd[i])) { 4650 device_printf(dev, 4651 "# tx descriptors must be a power of 2"); 4652 err = EINVAL; 4653 goto fail; 4654 } 4655 } 4656 4657 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4658 MAX_SINGLE_PACKET_FRACTION) 4659 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4660 MAX_SINGLE_PACKET_FRACTION); 4661 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4662 MAX_SINGLE_PACKET_FRACTION) 4663 scctx->isc_tx_tso_segments_max = max(1, 4664 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4665 4666 /* 4667 * Protect the stack against modern hardware 4668 */ 4669 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4670 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4671 4672 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4673 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4674 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4675 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4676 if (scctx->isc_rss_table_size == 0) 4677 scctx->isc_rss_table_size = 64; 4678 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4679 4680 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4681 /* XXX format name */ 4682 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4683 4684 /* XXX --- can support > 1 -- but keep it simple for now */ 4685 scctx->isc_intr = IFLIB_INTR_LEGACY; 4686 4687 /* Get memory for the station queues */ 4688 if ((err = iflib_queues_alloc(ctx))) { 4689 device_printf(dev, "Unable to allocate queue memory\n"); 4690 goto fail; 4691 } 4692 4693 if ((err = iflib_qset_structures_setup(ctx))) { 4694 device_printf(dev, "qset structure setup failed %d\n", err); 4695 goto fail_queues; 4696 } 4697 /* 4698 * XXX What if anything do we want to do about interrupts? 4699 */ 4700 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4701 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4702 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4703 goto fail_detach; 4704 } 4705 /* XXX handle more than one queue */ 4706 for (i = 0; i < scctx->isc_nrxqsets; i++) 4707 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4708 4709 *ctxp = ctx; 4710 4711 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4712 iflib_add_device_sysctl_post(ctx); 4713 ctx->ifc_flags |= IFC_INIT_DONE; 4714 return (0); 4715 fail_detach: 4716 ether_ifdetach(ctx->ifc_ifp); 4717 fail_queues: 4718 iflib_tx_structures_free(ctx); 4719 iflib_rx_structures_free(ctx); 4720 fail: 4721 IFDI_DETACH(ctx); 4722 return (err); 4723 } 4724 4725 int 4726 iflib_pseudo_deregister(if_ctx_t ctx) 4727 { 4728 if_t ifp = ctx->ifc_ifp; 4729 iflib_txq_t txq; 4730 iflib_rxq_t rxq; 4731 int i, j; 4732 struct taskqgroup *tqg; 4733 iflib_fl_t fl; 4734 4735 /* Unregister VLAN events */ 4736 if (ctx->ifc_vlan_attach_event != NULL) 4737 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4738 if (ctx->ifc_vlan_detach_event != NULL) 4739 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4740 4741 ether_ifdetach(ifp); 4742 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4743 CTX_LOCK_DESTROY(ctx); 4744 /* XXX drain any dependent tasks */ 4745 tqg = qgroup_if_io_tqg; 4746 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4747 callout_drain(&txq->ift_timer); 4748 if (txq->ift_task.gt_uniq != NULL) 4749 taskqgroup_detach(tqg, &txq->ift_task); 4750 } 4751 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4752 if (rxq->ifr_task.gt_uniq != NULL) 4753 taskqgroup_detach(tqg, &rxq->ifr_task); 4754 4755 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4756 free(fl->ifl_rx_bitmap, M_IFLIB); 4757 } 4758 tqg = qgroup_if_config_tqg; 4759 if (ctx->ifc_admin_task.gt_uniq != NULL) 4760 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4761 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4762 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4763 4764 if_free(ifp); 4765 4766 iflib_tx_structures_free(ctx); 4767 iflib_rx_structures_free(ctx); 4768 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4769 free(ctx->ifc_softc, M_IFLIB); 4770 free(ctx, M_IFLIB); 4771 return (0); 4772 } 4773 4774 int 4775 iflib_device_attach(device_t dev) 4776 { 4777 if_ctx_t ctx; 4778 if_shared_ctx_t sctx; 4779 4780 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4781 return (ENOTSUP); 4782 4783 pci_enable_busmaster(dev); 4784 4785 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4786 } 4787 4788 int 4789 iflib_device_deregister(if_ctx_t ctx) 4790 { 4791 if_t ifp = ctx->ifc_ifp; 4792 iflib_txq_t txq; 4793 iflib_rxq_t rxq; 4794 device_t dev = ctx->ifc_dev; 4795 int i, j; 4796 struct taskqgroup *tqg; 4797 iflib_fl_t fl; 4798 4799 /* Make sure VLANS are not using driver */ 4800 if (if_vlantrunkinuse(ifp)) { 4801 device_printf(dev,"Vlan in use, detach first\n"); 4802 return (EBUSY); 4803 } 4804 4805 CTX_LOCK(ctx); 4806 ctx->ifc_in_detach = 1; 4807 iflib_stop(ctx); 4808 CTX_UNLOCK(ctx); 4809 4810 /* Unregister VLAN events */ 4811 if (ctx->ifc_vlan_attach_event != NULL) 4812 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4813 if (ctx->ifc_vlan_detach_event != NULL) 4814 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4815 4816 iflib_netmap_detach(ifp); 4817 ether_ifdetach(ifp); 4818 if (ctx->ifc_led_dev != NULL) 4819 led_destroy(ctx->ifc_led_dev); 4820 /* XXX drain any dependent tasks */ 4821 tqg = qgroup_if_io_tqg; 4822 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4823 callout_drain(&txq->ift_timer); 4824 if (txq->ift_task.gt_uniq != NULL) 4825 taskqgroup_detach(tqg, &txq->ift_task); 4826 } 4827 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4828 if (rxq->ifr_task.gt_uniq != NULL) 4829 taskqgroup_detach(tqg, &rxq->ifr_task); 4830 4831 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4832 free(fl->ifl_rx_bitmap, M_IFLIB); 4833 4834 } 4835 tqg = qgroup_if_config_tqg; 4836 if (ctx->ifc_admin_task.gt_uniq != NULL) 4837 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4838 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4839 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4840 CTX_LOCK(ctx); 4841 IFDI_DETACH(ctx); 4842 CTX_UNLOCK(ctx); 4843 4844 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4845 CTX_LOCK_DESTROY(ctx); 4846 device_set_softc(ctx->ifc_dev, NULL); 4847 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4848 pci_release_msi(dev); 4849 } 4850 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4851 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4852 } 4853 if (ctx->ifc_msix_mem != NULL) { 4854 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4855 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4856 ctx->ifc_msix_mem = NULL; 4857 } 4858 4859 bus_generic_detach(dev); 4860 if_free(ifp); 4861 4862 iflib_tx_structures_free(ctx); 4863 iflib_rx_structures_free(ctx); 4864 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4865 free(ctx->ifc_softc, M_IFLIB); 4866 free(ctx, M_IFLIB); 4867 return (0); 4868 } 4869 4870 4871 int 4872 iflib_device_detach(device_t dev) 4873 { 4874 if_ctx_t ctx = device_get_softc(dev); 4875 4876 return (iflib_device_deregister(ctx)); 4877 } 4878 4879 int 4880 iflib_device_suspend(device_t dev) 4881 { 4882 if_ctx_t ctx = device_get_softc(dev); 4883 4884 CTX_LOCK(ctx); 4885 IFDI_SUSPEND(ctx); 4886 CTX_UNLOCK(ctx); 4887 4888 return bus_generic_suspend(dev); 4889 } 4890 int 4891 iflib_device_shutdown(device_t dev) 4892 { 4893 if_ctx_t ctx = device_get_softc(dev); 4894 4895 CTX_LOCK(ctx); 4896 IFDI_SHUTDOWN(ctx); 4897 CTX_UNLOCK(ctx); 4898 4899 return bus_generic_suspend(dev); 4900 } 4901 4902 4903 int 4904 iflib_device_resume(device_t dev) 4905 { 4906 if_ctx_t ctx = device_get_softc(dev); 4907 iflib_txq_t txq = ctx->ifc_txqs; 4908 4909 CTX_LOCK(ctx); 4910 IFDI_RESUME(ctx); 4911 iflib_init_locked(ctx); 4912 CTX_UNLOCK(ctx); 4913 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4914 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4915 4916 return (bus_generic_resume(dev)); 4917 } 4918 4919 int 4920 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4921 { 4922 int error; 4923 if_ctx_t ctx = device_get_softc(dev); 4924 4925 CTX_LOCK(ctx); 4926 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4927 CTX_UNLOCK(ctx); 4928 4929 return (error); 4930 } 4931 4932 void 4933 iflib_device_iov_uninit(device_t dev) 4934 { 4935 if_ctx_t ctx = device_get_softc(dev); 4936 4937 CTX_LOCK(ctx); 4938 IFDI_IOV_UNINIT(ctx); 4939 CTX_UNLOCK(ctx); 4940 } 4941 4942 int 4943 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 4944 { 4945 int error; 4946 if_ctx_t ctx = device_get_softc(dev); 4947 4948 CTX_LOCK(ctx); 4949 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 4950 CTX_UNLOCK(ctx); 4951 4952 return (error); 4953 } 4954 4955 /********************************************************************* 4956 * 4957 * MODULE FUNCTION DEFINITIONS 4958 * 4959 **********************************************************************/ 4960 4961 /* 4962 * - Start a fast taskqueue thread for each core 4963 * - Start a taskqueue for control operations 4964 */ 4965 static int 4966 iflib_module_init(void) 4967 { 4968 return (0); 4969 } 4970 4971 static int 4972 iflib_module_event_handler(module_t mod, int what, void *arg) 4973 { 4974 int err; 4975 4976 switch (what) { 4977 case MOD_LOAD: 4978 if ((err = iflib_module_init()) != 0) 4979 return (err); 4980 break; 4981 case MOD_UNLOAD: 4982 return (EBUSY); 4983 default: 4984 return (EOPNOTSUPP); 4985 } 4986 4987 return (0); 4988 } 4989 4990 /********************************************************************* 4991 * 4992 * PUBLIC FUNCTION DEFINITIONS 4993 * ordered as in iflib.h 4994 * 4995 **********************************************************************/ 4996 4997 4998 static void 4999 _iflib_assert(if_shared_ctx_t sctx) 5000 { 5001 MPASS(sctx->isc_tx_maxsize); 5002 MPASS(sctx->isc_tx_maxsegsize); 5003 5004 MPASS(sctx->isc_rx_maxsize); 5005 MPASS(sctx->isc_rx_nsegments); 5006 MPASS(sctx->isc_rx_maxsegsize); 5007 5008 MPASS(sctx->isc_nrxd_min[0]); 5009 MPASS(sctx->isc_nrxd_max[0]); 5010 MPASS(sctx->isc_nrxd_default[0]); 5011 MPASS(sctx->isc_ntxd_min[0]); 5012 MPASS(sctx->isc_ntxd_max[0]); 5013 MPASS(sctx->isc_ntxd_default[0]); 5014 } 5015 5016 static void 5017 _iflib_pre_assert(if_softc_ctx_t scctx) 5018 { 5019 5020 MPASS(scctx->isc_txrx->ift_txd_encap); 5021 MPASS(scctx->isc_txrx->ift_txd_flush); 5022 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5023 MPASS(scctx->isc_txrx->ift_rxd_available); 5024 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5025 MPASS(scctx->isc_txrx->ift_rxd_refill); 5026 MPASS(scctx->isc_txrx->ift_rxd_flush); 5027 } 5028 5029 static int 5030 iflib_register(if_ctx_t ctx) 5031 { 5032 if_shared_ctx_t sctx = ctx->ifc_sctx; 5033 driver_t *driver = sctx->isc_driver; 5034 device_t dev = ctx->ifc_dev; 5035 if_t ifp; 5036 5037 _iflib_assert(sctx); 5038 5039 CTX_LOCK_INIT(ctx); 5040 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5041 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 5042 if (ifp == NULL) { 5043 device_printf(dev, "can not allocate ifnet structure\n"); 5044 return (ENOMEM); 5045 } 5046 5047 /* 5048 * Initialize our context's device specific methods 5049 */ 5050 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5051 kobj_class_compile((kobj_class_t) driver); 5052 driver->refs++; 5053 5054 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5055 if_setsoftc(ifp, ctx); 5056 if_setdev(ifp, dev); 5057 if_setinitfn(ifp, iflib_if_init); 5058 if_setioctlfn(ifp, iflib_if_ioctl); 5059 if_settransmitfn(ifp, iflib_if_transmit); 5060 if_setqflushfn(ifp, iflib_if_qflush); 5061 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5062 5063 ctx->ifc_vlan_attach_event = 5064 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5065 EVENTHANDLER_PRI_FIRST); 5066 ctx->ifc_vlan_detach_event = 5067 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5068 EVENTHANDLER_PRI_FIRST); 5069 5070 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 5071 iflib_media_change, iflib_media_status); 5072 5073 return (0); 5074 } 5075 5076 5077 static int 5078 iflib_queues_alloc(if_ctx_t ctx) 5079 { 5080 if_shared_ctx_t sctx = ctx->ifc_sctx; 5081 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5082 device_t dev = ctx->ifc_dev; 5083 int nrxqsets = scctx->isc_nrxqsets; 5084 int ntxqsets = scctx->isc_ntxqsets; 5085 iflib_txq_t txq; 5086 iflib_rxq_t rxq; 5087 iflib_fl_t fl = NULL; 5088 int i, j, cpu, err, txconf, rxconf; 5089 iflib_dma_info_t ifdip; 5090 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5091 uint32_t *txqsizes = scctx->isc_txqsizes; 5092 uint8_t nrxqs = sctx->isc_nrxqs; 5093 uint8_t ntxqs = sctx->isc_ntxqs; 5094 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5095 caddr_t *vaddrs; 5096 uint64_t *paddrs; 5097 5098 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5099 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5100 5101 /* Allocate the TX ring struct memory */ 5102 if (!(ctx->ifc_txqs = 5103 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5104 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5105 device_printf(dev, "Unable to allocate TX ring memory\n"); 5106 err = ENOMEM; 5107 goto fail; 5108 } 5109 5110 /* Now allocate the RX */ 5111 if (!(ctx->ifc_rxqs = 5112 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5113 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5114 device_printf(dev, "Unable to allocate RX ring memory\n"); 5115 err = ENOMEM; 5116 goto rx_fail; 5117 } 5118 5119 txq = ctx->ifc_txqs; 5120 rxq = ctx->ifc_rxqs; 5121 5122 /* 5123 * XXX handle allocation failure 5124 */ 5125 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5126 /* Set up some basics */ 5127 5128 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 5129 device_printf(dev, "failed to allocate iflib_dma_info\n"); 5130 err = ENOMEM; 5131 goto err_tx_desc; 5132 } 5133 txq->ift_ifdi = ifdip; 5134 for (j = 0; j < ntxqs; j++, ifdip++) { 5135 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 5136 device_printf(dev, "Unable to allocate Descriptor memory\n"); 5137 err = ENOMEM; 5138 goto err_tx_desc; 5139 } 5140 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5141 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5142 } 5143 txq->ift_ctx = ctx; 5144 txq->ift_id = i; 5145 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5146 txq->ift_br_offset = 1; 5147 } else { 5148 txq->ift_br_offset = 0; 5149 } 5150 /* XXX fix this */ 5151 txq->ift_timer.c_cpu = cpu; 5152 5153 if (iflib_txsd_alloc(txq)) { 5154 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5155 err = ENOMEM; 5156 goto err_tx_desc; 5157 } 5158 5159 /* Initialize the TX lock */ 5160 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 5161 device_get_nameunit(dev), txq->ift_id); 5162 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5163 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5164 5165 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 5166 device_get_nameunit(dev), txq->ift_id); 5167 5168 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5169 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5170 if (err) { 5171 /* XXX free any allocated rings */ 5172 device_printf(dev, "Unable to allocate buf_ring\n"); 5173 goto err_tx_desc; 5174 } 5175 } 5176 5177 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5178 /* Set up some basics */ 5179 5180 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 5181 device_printf(dev, "failed to allocate iflib_dma_info\n"); 5182 err = ENOMEM; 5183 goto err_tx_desc; 5184 } 5185 5186 rxq->ifr_ifdi = ifdip; 5187 /* XXX this needs to be changed if #rx queues != #tx queues */ 5188 rxq->ifr_ntxqirq = 1; 5189 rxq->ifr_txqid[0] = i; 5190 for (j = 0; j < nrxqs; j++, ifdip++) { 5191 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 5192 device_printf(dev, "Unable to allocate Descriptor memory\n"); 5193 err = ENOMEM; 5194 goto err_tx_desc; 5195 } 5196 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5197 } 5198 rxq->ifr_ctx = ctx; 5199 rxq->ifr_id = i; 5200 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5201 rxq->ifr_fl_offset = 1; 5202 } else { 5203 rxq->ifr_fl_offset = 0; 5204 } 5205 rxq->ifr_nfl = nfree_lists; 5206 if (!(fl = 5207 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5208 device_printf(dev, "Unable to allocate free list memory\n"); 5209 err = ENOMEM; 5210 goto err_tx_desc; 5211 } 5212 rxq->ifr_fl = fl; 5213 for (j = 0; j < nfree_lists; j++) { 5214 fl[j].ifl_rxq = rxq; 5215 fl[j].ifl_id = j; 5216 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5217 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5218 } 5219 /* Allocate receive buffers for the ring*/ 5220 if (iflib_rxsd_alloc(rxq)) { 5221 device_printf(dev, 5222 "Critical Failure setting up receive buffers\n"); 5223 err = ENOMEM; 5224 goto err_rx_desc; 5225 } 5226 5227 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5228 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 5229 } 5230 5231 /* TXQs */ 5232 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5233 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5234 for (i = 0; i < ntxqsets; i++) { 5235 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5236 5237 for (j = 0; j < ntxqs; j++, di++) { 5238 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5239 paddrs[i*ntxqs + j] = di->idi_paddr; 5240 } 5241 } 5242 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5243 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 5244 iflib_tx_structures_free(ctx); 5245 free(vaddrs, M_IFLIB); 5246 free(paddrs, M_IFLIB); 5247 goto err_rx_desc; 5248 } 5249 free(vaddrs, M_IFLIB); 5250 free(paddrs, M_IFLIB); 5251 5252 /* RXQs */ 5253 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5254 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5255 for (i = 0; i < nrxqsets; i++) { 5256 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5257 5258 for (j = 0; j < nrxqs; j++, di++) { 5259 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5260 paddrs[i*nrxqs + j] = di->idi_paddr; 5261 } 5262 } 5263 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5264 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 5265 iflib_tx_structures_free(ctx); 5266 free(vaddrs, M_IFLIB); 5267 free(paddrs, M_IFLIB); 5268 goto err_rx_desc; 5269 } 5270 free(vaddrs, M_IFLIB); 5271 free(paddrs, M_IFLIB); 5272 5273 return (0); 5274 5275 /* XXX handle allocation failure changes */ 5276 err_rx_desc: 5277 err_tx_desc: 5278 rx_fail: 5279 if (ctx->ifc_rxqs != NULL) 5280 free(ctx->ifc_rxqs, M_IFLIB); 5281 ctx->ifc_rxqs = NULL; 5282 if (ctx->ifc_txqs != NULL) 5283 free(ctx->ifc_txqs, M_IFLIB); 5284 ctx->ifc_txqs = NULL; 5285 fail: 5286 return (err); 5287 } 5288 5289 static int 5290 iflib_tx_structures_setup(if_ctx_t ctx) 5291 { 5292 iflib_txq_t txq = ctx->ifc_txqs; 5293 int i; 5294 5295 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5296 iflib_txq_setup(txq); 5297 5298 return (0); 5299 } 5300 5301 static void 5302 iflib_tx_structures_free(if_ctx_t ctx) 5303 { 5304 iflib_txq_t txq = ctx->ifc_txqs; 5305 int i, j; 5306 5307 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5308 iflib_txq_destroy(txq); 5309 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 5310 iflib_dma_free(&txq->ift_ifdi[j]); 5311 } 5312 free(ctx->ifc_txqs, M_IFLIB); 5313 ctx->ifc_txqs = NULL; 5314 IFDI_QUEUES_FREE(ctx); 5315 } 5316 5317 /********************************************************************* 5318 * 5319 * Initialize all receive rings. 5320 * 5321 **********************************************************************/ 5322 static int 5323 iflib_rx_structures_setup(if_ctx_t ctx) 5324 { 5325 iflib_rxq_t rxq = ctx->ifc_rxqs; 5326 int q; 5327 #if defined(INET6) || defined(INET) 5328 int i, err; 5329 #endif 5330 5331 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5332 #if defined(INET6) || defined(INET) 5333 tcp_lro_free(&rxq->ifr_lc); 5334 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5335 TCP_LRO_ENTRIES, min(1024, 5336 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 5337 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 5338 goto fail; 5339 } 5340 rxq->ifr_lro_enabled = TRUE; 5341 #endif 5342 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5343 } 5344 return (0); 5345 #if defined(INET6) || defined(INET) 5346 fail: 5347 /* 5348 * Free RX software descriptors allocated so far, we will only handle 5349 * the rings that completed, the failing case will have 5350 * cleaned up for itself. 'q' failed, so its the terminus. 5351 */ 5352 rxq = ctx->ifc_rxqs; 5353 for (i = 0; i < q; ++i, rxq++) { 5354 iflib_rx_sds_free(rxq); 5355 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5356 } 5357 return (err); 5358 #endif 5359 } 5360 5361 /********************************************************************* 5362 * 5363 * Free all receive rings. 5364 * 5365 **********************************************************************/ 5366 static void 5367 iflib_rx_structures_free(if_ctx_t ctx) 5368 { 5369 iflib_rxq_t rxq = ctx->ifc_rxqs; 5370 5371 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5372 iflib_rx_sds_free(rxq); 5373 } 5374 } 5375 5376 static int 5377 iflib_qset_structures_setup(if_ctx_t ctx) 5378 { 5379 int err; 5380 5381 /* 5382 * It is expected that the caller takes care of freeing queues if this 5383 * fails. 5384 */ 5385 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5386 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5387 return (err); 5388 } 5389 5390 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5391 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5392 5393 return (err); 5394 } 5395 5396 int 5397 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5398 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5399 { 5400 5401 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5402 } 5403 5404 #ifdef SMP 5405 static int 5406 find_nth(if_ctx_t ctx, int qid) 5407 { 5408 cpuset_t cpus; 5409 int i, cpuid, eqid, count; 5410 5411 CPU_COPY(&ctx->ifc_cpus, &cpus); 5412 count = CPU_COUNT(&cpus); 5413 eqid = qid % count; 5414 /* clear up to the qid'th bit */ 5415 for (i = 0; i < eqid; i++) { 5416 cpuid = CPU_FFS(&cpus); 5417 MPASS(cpuid != 0); 5418 CPU_CLR(cpuid-1, &cpus); 5419 } 5420 cpuid = CPU_FFS(&cpus); 5421 MPASS(cpuid != 0); 5422 return (cpuid-1); 5423 } 5424 5425 #ifdef SCHED_ULE 5426 extern struct cpu_group *cpu_top; /* CPU topology */ 5427 5428 static int 5429 find_child_with_core(int cpu, struct cpu_group *grp) 5430 { 5431 int i; 5432 5433 if (grp->cg_children == 0) 5434 return -1; 5435 5436 MPASS(grp->cg_child); 5437 for (i = 0; i < grp->cg_children; i++) { 5438 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5439 return i; 5440 } 5441 5442 return -1; 5443 } 5444 5445 /* 5446 * Find the nth "close" core to the specified core 5447 * "close" is defined as the deepest level that shares 5448 * at least an L2 cache. With threads, this will be 5449 * threads on the same core. If the sahred cache is L3 5450 * or higher, simply returns the same core. 5451 */ 5452 static int 5453 find_close_core(int cpu, int core_offset) 5454 { 5455 struct cpu_group *grp; 5456 int i; 5457 int fcpu; 5458 cpuset_t cs; 5459 5460 grp = cpu_top; 5461 if (grp == NULL) 5462 return cpu; 5463 i = 0; 5464 while ((i = find_child_with_core(cpu, grp)) != -1) { 5465 /* If the child only has one cpu, don't descend */ 5466 if (grp->cg_child[i].cg_count <= 1) 5467 break; 5468 grp = &grp->cg_child[i]; 5469 } 5470 5471 /* If they don't share at least an L2 cache, use the same CPU */ 5472 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5473 return cpu; 5474 5475 /* Now pick one */ 5476 CPU_COPY(&grp->cg_mask, &cs); 5477 5478 /* Add the selected CPU offset to core offset. */ 5479 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5480 if (fcpu - 1 == cpu) 5481 break; 5482 CPU_CLR(fcpu - 1, &cs); 5483 } 5484 MPASS(fcpu); 5485 5486 core_offset += i; 5487 5488 CPU_COPY(&grp->cg_mask, &cs); 5489 for (i = core_offset % grp->cg_count; i > 0; i--) { 5490 MPASS(CPU_FFS(&cs)); 5491 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5492 } 5493 MPASS(CPU_FFS(&cs)); 5494 return CPU_FFS(&cs) - 1; 5495 } 5496 #else 5497 static int 5498 find_close_core(int cpu, int core_offset __unused) 5499 { 5500 return cpu; 5501 } 5502 #endif 5503 5504 static int 5505 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5506 { 5507 switch (type) { 5508 case IFLIB_INTR_TX: 5509 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5510 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5511 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5512 case IFLIB_INTR_RX: 5513 case IFLIB_INTR_RXTX: 5514 /* RX queues get the specified core */ 5515 return qid / CPU_COUNT(&ctx->ifc_cpus); 5516 default: 5517 return -1; 5518 } 5519 } 5520 #else 5521 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5522 #define find_close_core(cpuid, tid) CPU_FIRST() 5523 #define find_nth(ctx, gid) CPU_FIRST() 5524 #endif 5525 5526 /* Just to avoid copy/paste */ 5527 static inline int 5528 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid, 5529 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, const char *name) 5530 { 5531 int cpuid; 5532 int err, tid; 5533 5534 cpuid = find_nth(ctx, qid); 5535 tid = get_core_offset(ctx, type, qid); 5536 MPASS(tid >= 0); 5537 cpuid = find_close_core(cpuid, tid); 5538 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name); 5539 if (err) { 5540 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err); 5541 return (err); 5542 } 5543 #ifdef notyet 5544 if (cpuid > ctx->ifc_cpuid_highest) 5545 ctx->ifc_cpuid_highest = cpuid; 5546 #endif 5547 return 0; 5548 } 5549 5550 int 5551 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5552 iflib_intr_type_t type, driver_filter_t *filter, 5553 void *filter_arg, int qid, const char *name) 5554 { 5555 struct grouptask *gtask; 5556 struct taskqgroup *tqg; 5557 iflib_filter_info_t info; 5558 gtask_fn_t *fn; 5559 int tqrid, err; 5560 driver_filter_t *intr_fast; 5561 void *q; 5562 5563 info = &ctx->ifc_filter_info; 5564 tqrid = rid; 5565 5566 switch (type) { 5567 /* XXX merge tx/rx for netmap? */ 5568 case IFLIB_INTR_TX: 5569 q = &ctx->ifc_txqs[qid]; 5570 info = &ctx->ifc_txqs[qid].ift_filter_info; 5571 gtask = &ctx->ifc_txqs[qid].ift_task; 5572 tqg = qgroup_if_io_tqg; 5573 fn = _task_fn_tx; 5574 intr_fast = iflib_fast_intr; 5575 GROUPTASK_INIT(gtask, 0, fn, q); 5576 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5577 break; 5578 case IFLIB_INTR_RX: 5579 q = &ctx->ifc_rxqs[qid]; 5580 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5581 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5582 tqg = qgroup_if_io_tqg; 5583 fn = _task_fn_rx; 5584 intr_fast = iflib_fast_intr; 5585 GROUPTASK_INIT(gtask, 0, fn, q); 5586 break; 5587 case IFLIB_INTR_RXTX: 5588 q = &ctx->ifc_rxqs[qid]; 5589 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5590 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5591 tqg = qgroup_if_io_tqg; 5592 fn = _task_fn_rx; 5593 intr_fast = iflib_fast_intr_rxtx; 5594 GROUPTASK_INIT(gtask, 0, fn, q); 5595 break; 5596 case IFLIB_INTR_ADMIN: 5597 q = ctx; 5598 tqrid = -1; 5599 info = &ctx->ifc_filter_info; 5600 gtask = &ctx->ifc_admin_task; 5601 tqg = qgroup_if_config_tqg; 5602 fn = _task_fn_admin; 5603 intr_fast = iflib_fast_intr_ctx; 5604 break; 5605 default: 5606 panic("unknown net intr type"); 5607 } 5608 5609 info->ifi_filter = filter; 5610 info->ifi_filter_arg = filter_arg; 5611 info->ifi_task = gtask; 5612 info->ifi_ctx = q; 5613 5614 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5615 if (err != 0) { 5616 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 5617 return (err); 5618 } 5619 if (type == IFLIB_INTR_ADMIN) 5620 return (0); 5621 5622 if (tqrid != -1) { 5623 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name); 5624 if (err) 5625 return (err); 5626 } else { 5627 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5628 } 5629 5630 return (0); 5631 } 5632 5633 void 5634 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 5635 { 5636 struct grouptask *gtask; 5637 struct taskqgroup *tqg; 5638 gtask_fn_t *fn; 5639 void *q; 5640 int irq_num = -1; 5641 int err; 5642 5643 switch (type) { 5644 case IFLIB_INTR_TX: 5645 q = &ctx->ifc_txqs[qid]; 5646 gtask = &ctx->ifc_txqs[qid].ift_task; 5647 tqg = qgroup_if_io_tqg; 5648 fn = _task_fn_tx; 5649 if (irq != NULL) 5650 irq_num = rman_get_start(irq->ii_res); 5651 break; 5652 case IFLIB_INTR_RX: 5653 q = &ctx->ifc_rxqs[qid]; 5654 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5655 tqg = qgroup_if_io_tqg; 5656 fn = _task_fn_rx; 5657 if (irq != NULL) 5658 irq_num = rman_get_start(irq->ii_res); 5659 break; 5660 case IFLIB_INTR_IOV: 5661 q = ctx; 5662 gtask = &ctx->ifc_vflr_task; 5663 tqg = qgroup_if_config_tqg; 5664 fn = _task_fn_iov; 5665 break; 5666 default: 5667 panic("unknown net intr type"); 5668 } 5669 GROUPTASK_INIT(gtask, 0, fn, q); 5670 if (irq_num != -1) { 5671 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name); 5672 if (err) 5673 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5674 } 5675 else { 5676 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5677 } 5678 } 5679 5680 void 5681 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5682 { 5683 if (irq->ii_tag) 5684 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5685 5686 if (irq->ii_res) 5687 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5688 } 5689 5690 static int 5691 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 5692 { 5693 iflib_txq_t txq = ctx->ifc_txqs; 5694 iflib_rxq_t rxq = ctx->ifc_rxqs; 5695 if_irq_t irq = &ctx->ifc_legacy_irq; 5696 iflib_filter_info_t info; 5697 struct grouptask *gtask; 5698 struct taskqgroup *tqg; 5699 gtask_fn_t *fn; 5700 int tqrid; 5701 void *q; 5702 int err; 5703 5704 q = &ctx->ifc_rxqs[0]; 5705 info = &rxq[0].ifr_filter_info; 5706 gtask = &rxq[0].ifr_task; 5707 tqg = qgroup_if_io_tqg; 5708 tqrid = irq->ii_rid = *rid; 5709 fn = _task_fn_rx; 5710 5711 ctx->ifc_flags |= IFC_LEGACY; 5712 info->ifi_filter = filter; 5713 info->ifi_filter_arg = filter_arg; 5714 info->ifi_task = gtask; 5715 info->ifi_ctx = ctx; 5716 5717 /* We allocate a single interrupt resource */ 5718 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5719 return (err); 5720 GROUPTASK_INIT(gtask, 0, fn, q); 5721 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5722 5723 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5724 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx"); 5725 return (0); 5726 } 5727 5728 void 5729 iflib_led_create(if_ctx_t ctx) 5730 { 5731 5732 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5733 device_get_nameunit(ctx->ifc_dev)); 5734 } 5735 5736 void 5737 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5738 { 5739 5740 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5741 } 5742 5743 void 5744 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5745 { 5746 5747 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5748 } 5749 5750 void 5751 iflib_admin_intr_deferred(if_ctx_t ctx) 5752 { 5753 #ifdef INVARIANTS 5754 struct grouptask *gtask; 5755 5756 gtask = &ctx->ifc_admin_task; 5757 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5758 #endif 5759 5760 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5761 } 5762 5763 void 5764 iflib_iov_intr_deferred(if_ctx_t ctx) 5765 { 5766 5767 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5768 } 5769 5770 void 5771 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5772 { 5773 5774 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5775 } 5776 5777 void 5778 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 5779 const char *name) 5780 { 5781 5782 GROUPTASK_INIT(gtask, 0, fn, ctx); 5783 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5784 } 5785 5786 void 5787 iflib_config_gtask_deinit(struct grouptask *gtask) 5788 { 5789 5790 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5791 } 5792 5793 void 5794 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5795 { 5796 if_t ifp = ctx->ifc_ifp; 5797 iflib_txq_t txq = ctx->ifc_txqs; 5798 5799 if_setbaudrate(ifp, baudrate); 5800 if (baudrate >= IF_Gbps(10)) { 5801 STATE_LOCK(ctx); 5802 ctx->ifc_flags |= IFC_PREFETCH; 5803 STATE_UNLOCK(ctx); 5804 } 5805 /* If link down, disable watchdog */ 5806 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5807 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5808 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5809 } 5810 ctx->ifc_link_state = link_state; 5811 if_link_state_change(ifp, link_state); 5812 } 5813 5814 static int 5815 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5816 { 5817 int credits; 5818 #ifdef INVARIANTS 5819 int credits_pre = txq->ift_cidx_processed; 5820 #endif 5821 5822 if (ctx->isc_txd_credits_update == NULL) 5823 return (0); 5824 5825 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5826 return (0); 5827 5828 txq->ift_processed += credits; 5829 txq->ift_cidx_processed += credits; 5830 5831 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5832 if (txq->ift_cidx_processed >= txq->ift_size) 5833 txq->ift_cidx_processed -= txq->ift_size; 5834 return (credits); 5835 } 5836 5837 static int 5838 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5839 { 5840 5841 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5842 budget)); 5843 } 5844 5845 void 5846 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5847 const char *description, if_int_delay_info_t info, 5848 int offset, int value) 5849 { 5850 info->iidi_ctx = ctx; 5851 info->iidi_offset = offset; 5852 info->iidi_value = value; 5853 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5854 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5855 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5856 info, 0, iflib_sysctl_int_delay, "I", description); 5857 } 5858 5859 struct sx * 5860 iflib_ctx_lock_get(if_ctx_t ctx) 5861 { 5862 5863 return (&ctx->ifc_ctx_sx); 5864 } 5865 5866 static int 5867 iflib_msix_init(if_ctx_t ctx) 5868 { 5869 device_t dev = ctx->ifc_dev; 5870 if_shared_ctx_t sctx = ctx->ifc_sctx; 5871 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5872 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5873 int iflib_num_tx_queues, iflib_num_rx_queues; 5874 int err, admincnt, bar; 5875 5876 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 5877 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 5878 5879 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 5880 5881 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5882 admincnt = sctx->isc_admin_intrcnt; 5883 /* Override by global tuneable */ 5884 { 5885 int i; 5886 size_t len = sizeof(i); 5887 err = kernel_sysctlbyname(curthread, "hw.pci.enable_msix", &i, &len, NULL, 0, NULL, 0); 5888 if (err == 0) { 5889 if (i == 0) 5890 goto msi; 5891 } 5892 else { 5893 device_printf(dev, "unable to read hw.pci.enable_msix."); 5894 } 5895 } 5896 /* Override by tuneable */ 5897 if (scctx->isc_disable_msix) 5898 goto msi; 5899 5900 /* 5901 ** When used in a virtualized environment 5902 ** PCI BUSMASTER capability may not be set 5903 ** so explicity set it here and rewrite 5904 ** the ENABLE in the MSIX control register 5905 ** at this point to cause the host to 5906 ** successfully initialize us. 5907 */ 5908 { 5909 int msix_ctrl, rid; 5910 5911 pci_enable_busmaster(dev); 5912 rid = 0; 5913 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) { 5914 rid += PCIR_MSIX_CTRL; 5915 msix_ctrl = pci_read_config(dev, rid, 2); 5916 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 5917 pci_write_config(dev, rid, msix_ctrl, 2); 5918 } else { 5919 device_printf(dev, "PCIY_MSIX capability not found; " 5920 "or rid %d == 0.\n", rid); 5921 goto msi; 5922 } 5923 } 5924 5925 /* 5926 * bar == -1 => "trust me I know what I'm doing" 5927 * Some drivers are for hardware that is so shoddily 5928 * documented that no one knows which bars are which 5929 * so the developer has to map all bars. This hack 5930 * allows shoddy garbage to use msix in this framework. 5931 */ 5932 if (bar != -1) { 5933 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5934 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5935 if (ctx->ifc_msix_mem == NULL) { 5936 /* May not be enabled */ 5937 device_printf(dev, "Unable to map MSIX table \n"); 5938 goto msi; 5939 } 5940 } 5941 /* First try MSI/X */ 5942 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5943 device_printf(dev, "System has MSIX disabled \n"); 5944 bus_release_resource(dev, SYS_RES_MEMORY, 5945 bar, ctx->ifc_msix_mem); 5946 ctx->ifc_msix_mem = NULL; 5947 goto msi; 5948 } 5949 #if IFLIB_DEBUG 5950 /* use only 1 qset in debug mode */ 5951 queuemsgs = min(msgs - admincnt, 1); 5952 #else 5953 queuemsgs = msgs - admincnt; 5954 #endif 5955 #ifdef RSS 5956 queues = imin(queuemsgs, rss_getnumbuckets()); 5957 #else 5958 queues = queuemsgs; 5959 #endif 5960 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 5961 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 5962 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 5963 #ifdef RSS 5964 /* If we're doing RSS, clamp at the number of RSS buckets */ 5965 if (queues > rss_getnumbuckets()) 5966 queues = rss_getnumbuckets(); 5967 #endif 5968 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 5969 rx_queues = iflib_num_rx_queues; 5970 else 5971 rx_queues = queues; 5972 5973 if (rx_queues > scctx->isc_nrxqsets) 5974 rx_queues = scctx->isc_nrxqsets; 5975 5976 /* 5977 * We want this to be all logical CPUs by default 5978 */ 5979 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 5980 tx_queues = iflib_num_tx_queues; 5981 else 5982 tx_queues = mp_ncpus; 5983 5984 if (tx_queues > scctx->isc_ntxqsets) 5985 tx_queues = scctx->isc_ntxqsets; 5986 5987 if (ctx->ifc_sysctl_qs_eq_override == 0) { 5988 #ifdef INVARIANTS 5989 if (tx_queues != rx_queues) 5990 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 5991 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 5992 #endif 5993 tx_queues = min(rx_queues, tx_queues); 5994 rx_queues = min(rx_queues, tx_queues); 5995 } 5996 5997 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 5998 5999 vectors = rx_queues + admincnt; 6000 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6001 device_printf(dev, 6002 "Using MSIX interrupts with %d vectors\n", vectors); 6003 scctx->isc_vectors = vectors; 6004 scctx->isc_nrxqsets = rx_queues; 6005 scctx->isc_ntxqsets = tx_queues; 6006 scctx->isc_intr = IFLIB_INTR_MSIX; 6007 6008 return (vectors); 6009 } else { 6010 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 6011 } 6012 msi: 6013 vectors = pci_msi_count(dev); 6014 scctx->isc_nrxqsets = 1; 6015 scctx->isc_ntxqsets = 1; 6016 scctx->isc_vectors = vectors; 6017 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6018 device_printf(dev,"Using an MSI interrupt\n"); 6019 scctx->isc_intr = IFLIB_INTR_MSI; 6020 } else { 6021 device_printf(dev,"Using a Legacy interrupt\n"); 6022 scctx->isc_intr = IFLIB_INTR_LEGACY; 6023 } 6024 6025 return (vectors); 6026 } 6027 6028 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6029 6030 static int 6031 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6032 { 6033 int rc; 6034 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6035 struct sbuf *sb; 6036 char *ring_state = "UNKNOWN"; 6037 6038 /* XXX needed ? */ 6039 rc = sysctl_wire_old_buffer(req, 0); 6040 MPASS(rc == 0); 6041 if (rc != 0) 6042 return (rc); 6043 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6044 MPASS(sb != NULL); 6045 if (sb == NULL) 6046 return (ENOMEM); 6047 if (state[3] <= 3) 6048 ring_state = ring_states[state[3]]; 6049 6050 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6051 state[0], state[1], state[2], ring_state); 6052 rc = sbuf_finish(sb); 6053 sbuf_delete(sb); 6054 return(rc); 6055 } 6056 6057 enum iflib_ndesc_handler { 6058 IFLIB_NTXD_HANDLER, 6059 IFLIB_NRXD_HANDLER, 6060 }; 6061 6062 static int 6063 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6064 { 6065 if_ctx_t ctx = (void *)arg1; 6066 enum iflib_ndesc_handler type = arg2; 6067 char buf[256] = {0}; 6068 qidx_t *ndesc; 6069 char *p, *next; 6070 int nqs, rc, i; 6071 6072 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 6073 6074 nqs = 8; 6075 switch(type) { 6076 case IFLIB_NTXD_HANDLER: 6077 ndesc = ctx->ifc_sysctl_ntxds; 6078 if (ctx->ifc_sctx) 6079 nqs = ctx->ifc_sctx->isc_ntxqs; 6080 break; 6081 case IFLIB_NRXD_HANDLER: 6082 ndesc = ctx->ifc_sysctl_nrxds; 6083 if (ctx->ifc_sctx) 6084 nqs = ctx->ifc_sctx->isc_nrxqs; 6085 break; 6086 default: 6087 panic("unhandled type"); 6088 } 6089 if (nqs == 0) 6090 nqs = 8; 6091 6092 for (i=0; i<8; i++) { 6093 if (i >= nqs) 6094 break; 6095 if (i) 6096 strcat(buf, ","); 6097 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6098 } 6099 6100 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6101 if (rc || req->newptr == NULL) 6102 return rc; 6103 6104 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6105 i++, p = strsep(&next, " ,")) { 6106 ndesc[i] = strtoul(p, NULL, 10); 6107 } 6108 6109 return(rc); 6110 } 6111 6112 #define NAME_BUFLEN 32 6113 static void 6114 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6115 { 6116 device_t dev = iflib_get_dev(ctx); 6117 struct sysctl_oid_list *child, *oid_list; 6118 struct sysctl_ctx_list *ctx_list; 6119 struct sysctl_oid *node; 6120 6121 ctx_list = device_get_sysctl_ctx(dev); 6122 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6123 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6124 CTLFLAG_RD, NULL, "IFLIB fields"); 6125 oid_list = SYSCTL_CHILDREN(node); 6126 6127 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6128 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 6129 "driver version"); 6130 6131 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6132 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6133 "# of txqs to use, 0 => use default #"); 6134 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6135 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6136 "# of rxqs to use, 0 => use default #"); 6137 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6138 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6139 "permit #txq != #rxq"); 6140 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6141 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6142 "disable MSIX (default 0)"); 6143 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6144 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6145 "set the rx budget"); 6146 6147 /* XXX change for per-queue sizes */ 6148 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6149 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6150 mp_ndesc_handler, "A", 6151 "list of # of tx descriptors to use, 0 = use default #"); 6152 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6153 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6154 mp_ndesc_handler, "A", 6155 "list of # of rx descriptors to use, 0 = use default #"); 6156 } 6157 6158 static void 6159 iflib_add_device_sysctl_post(if_ctx_t ctx) 6160 { 6161 if_shared_ctx_t sctx = ctx->ifc_sctx; 6162 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6163 device_t dev = iflib_get_dev(ctx); 6164 struct sysctl_oid_list *child; 6165 struct sysctl_ctx_list *ctx_list; 6166 iflib_fl_t fl; 6167 iflib_txq_t txq; 6168 iflib_rxq_t rxq; 6169 int i, j; 6170 char namebuf[NAME_BUFLEN]; 6171 char *qfmt; 6172 struct sysctl_oid *queue_node, *fl_node, *node; 6173 struct sysctl_oid_list *queue_list, *fl_list; 6174 ctx_list = device_get_sysctl_ctx(dev); 6175 6176 node = ctx->ifc_sysctl_node; 6177 child = SYSCTL_CHILDREN(node); 6178 6179 if (scctx->isc_ntxqsets > 100) 6180 qfmt = "txq%03d"; 6181 else if (scctx->isc_ntxqsets > 10) 6182 qfmt = "txq%02d"; 6183 else 6184 qfmt = "txq%d"; 6185 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6186 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6187 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6188 CTLFLAG_RD, NULL, "Queue Name"); 6189 queue_list = SYSCTL_CHILDREN(queue_node); 6190 #if MEMORY_LOGGING 6191 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6192 CTLFLAG_RD, 6193 &txq->ift_dequeued, "total mbufs freed"); 6194 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6195 CTLFLAG_RD, 6196 &txq->ift_enqueued, "total mbufs enqueued"); 6197 #endif 6198 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6199 CTLFLAG_RD, 6200 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6201 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6202 CTLFLAG_RD, 6203 &txq->ift_pullups, "# of times m_pullup was called"); 6204 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6205 CTLFLAG_RD, 6206 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6207 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6208 CTLFLAG_RD, 6209 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6210 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6211 CTLFLAG_RD, 6212 &txq->ift_map_failed, "# of times dma map failed"); 6213 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6214 CTLFLAG_RD, 6215 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6216 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6217 CTLFLAG_RD, 6218 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6219 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6220 CTLFLAG_RD, 6221 &txq->ift_pidx, 1, "Producer Index"); 6222 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6223 CTLFLAG_RD, 6224 &txq->ift_cidx, 1, "Consumer Index"); 6225 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6226 CTLFLAG_RD, 6227 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6228 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6229 CTLFLAG_RD, 6230 &txq->ift_in_use, 1, "descriptors in use"); 6231 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6232 CTLFLAG_RD, 6233 &txq->ift_processed, "descriptors procesed for clean"); 6234 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6235 CTLFLAG_RD, 6236 &txq->ift_cleaned, "total cleaned"); 6237 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6238 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6239 0, mp_ring_state_handler, "A", "soft ring state"); 6240 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6241 CTLFLAG_RD, &txq->ift_br->enqueues, 6242 "# of enqueues to the mp_ring for this queue"); 6243 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6244 CTLFLAG_RD, &txq->ift_br->drops, 6245 "# of drops in the mp_ring for this queue"); 6246 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6247 CTLFLAG_RD, &txq->ift_br->starts, 6248 "# of normal consumer starts in the mp_ring for this queue"); 6249 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6250 CTLFLAG_RD, &txq->ift_br->stalls, 6251 "# of consumer stalls in the mp_ring for this queue"); 6252 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6253 CTLFLAG_RD, &txq->ift_br->restarts, 6254 "# of consumer restarts in the mp_ring for this queue"); 6255 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6256 CTLFLAG_RD, &txq->ift_br->abdications, 6257 "# of consumer abdications in the mp_ring for this queue"); 6258 } 6259 6260 if (scctx->isc_nrxqsets > 100) 6261 qfmt = "rxq%03d"; 6262 else if (scctx->isc_nrxqsets > 10) 6263 qfmt = "rxq%02d"; 6264 else 6265 qfmt = "rxq%d"; 6266 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6267 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6268 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6269 CTLFLAG_RD, NULL, "Queue Name"); 6270 queue_list = SYSCTL_CHILDREN(queue_node); 6271 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6272 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 6273 CTLFLAG_RD, 6274 &rxq->ifr_cq_pidx, 1, "Producer Index"); 6275 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6276 CTLFLAG_RD, 6277 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6278 } 6279 6280 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6281 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6282 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6283 CTLFLAG_RD, NULL, "freelist Name"); 6284 fl_list = SYSCTL_CHILDREN(fl_node); 6285 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6286 CTLFLAG_RD, 6287 &fl->ifl_pidx, 1, "Producer Index"); 6288 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6289 CTLFLAG_RD, 6290 &fl->ifl_cidx, 1, "Consumer Index"); 6291 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6292 CTLFLAG_RD, 6293 &fl->ifl_credits, 1, "credits available"); 6294 #if MEMORY_LOGGING 6295 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6296 CTLFLAG_RD, 6297 &fl->ifl_m_enqueued, "mbufs allocated"); 6298 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6299 CTLFLAG_RD, 6300 &fl->ifl_m_dequeued, "mbufs freed"); 6301 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6302 CTLFLAG_RD, 6303 &fl->ifl_cl_enqueued, "clusters allocated"); 6304 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6305 CTLFLAG_RD, 6306 &fl->ifl_cl_dequeued, "clusters freed"); 6307 #endif 6308 6309 } 6310 } 6311 6312 } 6313 6314 #ifndef __NO_STRICT_ALIGNMENT 6315 static struct mbuf * 6316 iflib_fixup_rx(struct mbuf *m) 6317 { 6318 struct mbuf *n; 6319 6320 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6321 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6322 m->m_data += ETHER_HDR_LEN; 6323 n = m; 6324 } else { 6325 MGETHDR(n, M_NOWAIT, MT_DATA); 6326 if (n == NULL) { 6327 m_freem(m); 6328 return (NULL); 6329 } 6330 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6331 m->m_data += ETHER_HDR_LEN; 6332 m->m_len -= ETHER_HDR_LEN; 6333 n->m_len = ETHER_HDR_LEN; 6334 M_MOVE_PKTHDR(n, m); 6335 n->m_next = m; 6336 } 6337 return (n); 6338 } 6339 #endif 6340 6341 #ifdef NETDUMP 6342 static void 6343 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 6344 { 6345 if_ctx_t ctx; 6346 6347 ctx = if_getsoftc(ifp); 6348 CTX_LOCK(ctx); 6349 *nrxr = NRXQSETS(ctx); 6350 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6351 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6352 CTX_UNLOCK(ctx); 6353 } 6354 6355 static void 6356 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event) 6357 { 6358 if_ctx_t ctx; 6359 if_softc_ctx_t scctx; 6360 iflib_fl_t fl; 6361 iflib_rxq_t rxq; 6362 int i, j; 6363 6364 ctx = if_getsoftc(ifp); 6365 scctx = &ctx->ifc_softc_ctx; 6366 6367 switch (event) { 6368 case NETDUMP_START: 6369 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6370 rxq = &ctx->ifc_rxqs[i]; 6371 for (j = 0; j < rxq->ifr_nfl; j++) { 6372 fl = rxq->ifr_fl; 6373 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6374 } 6375 } 6376 iflib_no_tx_batch = 1; 6377 break; 6378 default: 6379 break; 6380 } 6381 } 6382 6383 static int 6384 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m) 6385 { 6386 if_ctx_t ctx; 6387 iflib_txq_t txq; 6388 int error; 6389 6390 ctx = if_getsoftc(ifp); 6391 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6392 IFF_DRV_RUNNING) 6393 return (EBUSY); 6394 6395 txq = &ctx->ifc_txqs[0]; 6396 error = iflib_encap(txq, &m); 6397 if (error == 0) 6398 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6399 return (error); 6400 } 6401 6402 static int 6403 iflib_netdump_poll(struct ifnet *ifp, int count) 6404 { 6405 if_ctx_t ctx; 6406 if_softc_ctx_t scctx; 6407 iflib_txq_t txq; 6408 int i; 6409 6410 ctx = if_getsoftc(ifp); 6411 scctx = &ctx->ifc_softc_ctx; 6412 6413 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6414 IFF_DRV_RUNNING) 6415 return (EBUSY); 6416 6417 txq = &ctx->ifc_txqs[0]; 6418 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6419 6420 for (i = 0; i < scctx->isc_nrxqsets; i++) 6421 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6422 return (0); 6423 } 6424 #endif /* NETDUMP */ 6425