1 /*- 2 * Copyright (c) 2014-2017, Matthew Macy <mmacy@nextbsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 35 #include <sys/param.h> 36 #include <sys/types.h> 37 #include <sys/bus.h> 38 #include <sys/eventhandler.h> 39 #include <sys/sockio.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sysctl.h> 50 #include <sys/syslog.h> 51 #include <sys/taskqueue.h> 52 #include <sys/limits.h> 53 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 63 #include <netinet/in.h> 64 #include <netinet/in_pcb.h> 65 #include <netinet/tcp_lro.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/if_ether.h> 68 #include <netinet/ip.h> 69 #include <netinet/ip6.h> 70 #include <netinet/tcp.h> 71 72 #include <machine/bus.h> 73 #include <machine/in_cksum.h> 74 75 #include <vm/vm.h> 76 #include <vm/pmap.h> 77 78 #include <dev/led/led.h> 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pci_private.h> 82 83 #include <net/iflib.h> 84 85 #include "ifdi_if.h" 86 87 #if defined(__i386__) || defined(__amd64__) 88 #include <sys/memdesc.h> 89 #include <machine/bus.h> 90 #include <machine/md_var.h> 91 #include <machine/specialreg.h> 92 #include <x86/include/busdma_impl.h> 93 #include <x86/iommu/busdma_dmar.h> 94 #endif 95 96 #include <sys/bitstring.h> 97 /* 98 * enable accounting of every mbuf as it comes in to and goes out of 99 * iflib's software descriptor references 100 */ 101 #define MEMORY_LOGGING 0 102 /* 103 * Enable mbuf vectors for compressing long mbuf chains 104 */ 105 106 /* 107 * NB: 108 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 109 * we prefetch needs to be determined by the time spent in m_free vis a vis 110 * the cost of a prefetch. This will of course vary based on the workload: 111 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 112 * is quite expensive, thus suggesting very little prefetch. 113 * - small packet forwarding which is just returning a single mbuf to 114 * UMA will typically be very fast vis a vis the cost of a memory 115 * access. 116 */ 117 118 119 /* 120 * File organization: 121 * - private structures 122 * - iflib private utility functions 123 * - ifnet functions 124 * - vlan registry and other exported functions 125 * - iflib public core functions 126 * 127 * 128 */ 129 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 130 131 struct iflib_txq; 132 typedef struct iflib_txq *iflib_txq_t; 133 struct iflib_rxq; 134 typedef struct iflib_rxq *iflib_rxq_t; 135 struct iflib_fl; 136 typedef struct iflib_fl *iflib_fl_t; 137 138 struct iflib_ctx; 139 140 typedef struct iflib_filter_info { 141 driver_filter_t *ifi_filter; 142 void *ifi_filter_arg; 143 struct grouptask *ifi_task; 144 void *ifi_ctx; 145 } *iflib_filter_info_t; 146 147 struct iflib_ctx { 148 KOBJ_FIELDS; 149 /* 150 * Pointer to hardware driver's softc 151 */ 152 void *ifc_softc; 153 device_t ifc_dev; 154 if_t ifc_ifp; 155 156 cpuset_t ifc_cpus; 157 if_shared_ctx_t ifc_sctx; 158 struct if_softc_ctx ifc_softc_ctx; 159 160 struct mtx ifc_mtx; 161 162 uint16_t ifc_nhwtxqs; 163 uint16_t ifc_nhwrxqs; 164 165 iflib_txq_t ifc_txqs; 166 iflib_rxq_t ifc_rxqs; 167 uint32_t ifc_if_flags; 168 uint32_t ifc_flags; 169 uint32_t ifc_max_fl_buf_size; 170 int ifc_in_detach; 171 172 int ifc_link_state; 173 int ifc_link_irq; 174 int ifc_watchdog_events; 175 struct cdev *ifc_led_dev; 176 struct resource *ifc_msix_mem; 177 178 struct if_irq ifc_legacy_irq; 179 struct grouptask ifc_admin_task; 180 struct grouptask ifc_vflr_task; 181 struct iflib_filter_info ifc_filter_info; 182 struct ifmedia ifc_media; 183 184 struct sysctl_oid *ifc_sysctl_node; 185 uint16_t ifc_sysctl_ntxqs; 186 uint16_t ifc_sysctl_nrxqs; 187 uint16_t ifc_sysctl_qs_eq_override; 188 189 qidx_t ifc_sysctl_ntxds[8]; 190 qidx_t ifc_sysctl_nrxds[8]; 191 struct if_txrx ifc_txrx; 192 #define isc_txd_encap ifc_txrx.ift_txd_encap 193 #define isc_txd_flush ifc_txrx.ift_txd_flush 194 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 195 #define isc_rxd_available ifc_txrx.ift_rxd_available 196 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 197 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 198 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 199 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 200 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 201 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 202 eventhandler_tag ifc_vlan_attach_event; 203 eventhandler_tag ifc_vlan_detach_event; 204 uint8_t ifc_mac[ETHER_ADDR_LEN]; 205 char ifc_mtx_name[16]; 206 }; 207 208 209 void * 210 iflib_get_softc(if_ctx_t ctx) 211 { 212 213 return (ctx->ifc_softc); 214 } 215 216 device_t 217 iflib_get_dev(if_ctx_t ctx) 218 { 219 220 return (ctx->ifc_dev); 221 } 222 223 if_t 224 iflib_get_ifp(if_ctx_t ctx) 225 { 226 227 return (ctx->ifc_ifp); 228 } 229 230 struct ifmedia * 231 iflib_get_media(if_ctx_t ctx) 232 { 233 234 return (&ctx->ifc_media); 235 } 236 237 void 238 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 239 { 240 241 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 242 } 243 244 if_softc_ctx_t 245 iflib_get_softc_ctx(if_ctx_t ctx) 246 { 247 248 return (&ctx->ifc_softc_ctx); 249 } 250 251 if_shared_ctx_t 252 iflib_get_sctx(if_ctx_t ctx) 253 { 254 255 return (ctx->ifc_sctx); 256 } 257 258 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 259 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 260 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 261 262 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 263 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 264 265 #define RX_SW_DESC_MAP_CREATED (1 << 0) 266 #define TX_SW_DESC_MAP_CREATED (1 << 1) 267 #define RX_SW_DESC_INUSE (1 << 3) 268 #define TX_SW_DESC_MAPPED (1 << 4) 269 270 #define M_TOOBIG M_PROTO1 271 272 typedef struct iflib_sw_rx_desc_array { 273 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 274 struct mbuf **ifsd_m; /* pkthdr mbufs */ 275 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 276 uint8_t *ifsd_flags; 277 } iflib_rxsd_array_t; 278 279 typedef struct iflib_sw_tx_desc_array { 280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 281 struct mbuf **ifsd_m; /* pkthdr mbufs */ 282 uint8_t *ifsd_flags; 283 } if_txsd_vec_t; 284 285 286 /* magic number that should be high enough for any hardware */ 287 #define IFLIB_MAX_TX_SEGS 128 288 #define IFLIB_MAX_RX_SEGS 32 289 #define IFLIB_RX_COPY_THRESH 128 290 #define IFLIB_MAX_RX_REFRESH 32 291 /* The minimum descriptors per second before we start coalescing */ 292 #define IFLIB_MIN_DESC_SEC 16384 293 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 294 #define IFLIB_QUEUE_IDLE 0 295 #define IFLIB_QUEUE_HUNG 1 296 #define IFLIB_QUEUE_WORKING 2 297 /* maximum number of txqs that can share an rx interrupt */ 298 #define IFLIB_MAX_TX_SHARED_INTR 4 299 300 /* this should really scale with ring size - this is a fairly arbitrary value */ 301 #define TX_BATCH_SIZE 32 302 303 #define IFLIB_RESTART_BUDGET 8 304 305 #define IFC_LEGACY 0x001 306 #define IFC_QFLUSH 0x002 307 #define IFC_MULTISEG 0x004 308 #define IFC_DMAR 0x008 309 #define IFC_SC_ALLOCATED 0x010 310 #define IFC_INIT_DONE 0x020 311 #define IFC_PREFETCH 0x040 312 #define IFC_DO_RESET 0x080 313 #define IFC_CHECK_HUNG 0x100 314 315 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 316 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 317 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 318 struct iflib_txq { 319 qidx_t ift_in_use; 320 qidx_t ift_cidx; 321 qidx_t ift_cidx_processed; 322 qidx_t ift_pidx; 323 uint8_t ift_gen; 324 uint8_t ift_br_offset; 325 uint16_t ift_npending; 326 uint16_t ift_db_pending; 327 uint16_t ift_rs_pending; 328 /* implicit pad */ 329 uint8_t ift_txd_size[8]; 330 uint64_t ift_processed; 331 uint64_t ift_cleaned; 332 uint64_t ift_cleaned_prev; 333 #if MEMORY_LOGGING 334 uint64_t ift_enqueued; 335 uint64_t ift_dequeued; 336 #endif 337 uint64_t ift_no_tx_dma_setup; 338 uint64_t ift_no_desc_avail; 339 uint64_t ift_mbuf_defrag_failed; 340 uint64_t ift_mbuf_defrag; 341 uint64_t ift_map_failed; 342 uint64_t ift_txd_encap_efbig; 343 uint64_t ift_pullups; 344 345 struct mtx ift_mtx; 346 struct mtx ift_db_mtx; 347 348 /* constant values */ 349 if_ctx_t ift_ctx; 350 struct ifmp_ring *ift_br; 351 struct grouptask ift_task; 352 qidx_t ift_size; 353 uint16_t ift_id; 354 struct callout ift_timer; 355 356 if_txsd_vec_t ift_sds; 357 uint8_t ift_qstatus; 358 uint8_t ift_closed; 359 uint8_t ift_update_freq; 360 struct iflib_filter_info ift_filter_info; 361 bus_dma_tag_t ift_desc_tag; 362 bus_dma_tag_t ift_tso_desc_tag; 363 iflib_dma_info_t ift_ifdi; 364 #define MTX_NAME_LEN 16 365 char ift_mtx_name[MTX_NAME_LEN]; 366 char ift_db_mtx_name[MTX_NAME_LEN]; 367 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 368 #ifdef IFLIB_DIAGNOSTICS 369 uint64_t ift_cpu_exec_count[256]; 370 #endif 371 } __aligned(CACHE_LINE_SIZE); 372 373 struct iflib_fl { 374 qidx_t ifl_cidx; 375 qidx_t ifl_pidx; 376 qidx_t ifl_credits; 377 uint8_t ifl_gen; 378 uint8_t ifl_rxd_size; 379 #if MEMORY_LOGGING 380 uint64_t ifl_m_enqueued; 381 uint64_t ifl_m_dequeued; 382 uint64_t ifl_cl_enqueued; 383 uint64_t ifl_cl_dequeued; 384 #endif 385 /* implicit pad */ 386 387 bitstr_t *ifl_rx_bitmap; 388 qidx_t ifl_fragidx; 389 /* constant */ 390 qidx_t ifl_size; 391 uint16_t ifl_buf_size; 392 uint16_t ifl_cltype; 393 uma_zone_t ifl_zone; 394 iflib_rxsd_array_t ifl_sds; 395 iflib_rxq_t ifl_rxq; 396 uint8_t ifl_id; 397 bus_dma_tag_t ifl_desc_tag; 398 iflib_dma_info_t ifl_ifdi; 399 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 400 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 401 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 402 } __aligned(CACHE_LINE_SIZE); 403 404 static inline qidx_t 405 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 406 { 407 qidx_t used; 408 409 if (pidx > cidx) 410 used = pidx - cidx; 411 else if (pidx < cidx) 412 used = size - cidx + pidx; 413 else if (gen == 0 && pidx == cidx) 414 used = 0; 415 else if (gen == 1 && pidx == cidx) 416 used = size; 417 else 418 panic("bad state"); 419 420 return (used); 421 } 422 423 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 424 425 #define IDXDIFF(head, tail, wrap) \ 426 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 427 428 struct iflib_rxq { 429 /* If there is a separate completion queue - 430 * these are the cq cidx and pidx. Otherwise 431 * these are unused. 432 */ 433 qidx_t ifr_size; 434 qidx_t ifr_cq_cidx; 435 qidx_t ifr_cq_pidx; 436 uint8_t ifr_cq_gen; 437 uint8_t ifr_fl_offset; 438 439 if_ctx_t ifr_ctx; 440 iflib_fl_t ifr_fl; 441 uint64_t ifr_rx_irq; 442 uint16_t ifr_id; 443 uint8_t ifr_lro_enabled; 444 uint8_t ifr_nfl; 445 uint8_t ifr_ntxqirq; 446 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 447 struct lro_ctrl ifr_lc; 448 struct grouptask ifr_task; 449 struct iflib_filter_info ifr_filter_info; 450 iflib_dma_info_t ifr_ifdi; 451 452 /* dynamically allocate if any drivers need a value substantially larger than this */ 453 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 454 #ifdef IFLIB_DIAGNOSTICS 455 uint64_t ifr_cpu_exec_count[256]; 456 #endif 457 } __aligned(CACHE_LINE_SIZE); 458 459 typedef struct if_rxsd { 460 caddr_t *ifsd_cl; 461 struct mbuf **ifsd_m; 462 iflib_fl_t ifsd_fl; 463 qidx_t ifsd_cidx; 464 } *if_rxsd_t; 465 466 /* multiple of word size */ 467 #ifdef __LP64__ 468 #define PKT_INFO_SIZE 6 469 #define RXD_INFO_SIZE 5 470 #define PKT_TYPE uint64_t 471 #else 472 #define PKT_INFO_SIZE 11 473 #define RXD_INFO_SIZE 8 474 #define PKT_TYPE uint32_t 475 #endif 476 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 477 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 478 479 typedef struct if_pkt_info_pad { 480 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 481 } *if_pkt_info_pad_t; 482 typedef struct if_rxd_info_pad { 483 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 484 } *if_rxd_info_pad_t; 485 486 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 487 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 488 489 490 static inline void 491 pkt_info_zero(if_pkt_info_t pi) 492 { 493 if_pkt_info_pad_t pi_pad; 494 495 pi_pad = (if_pkt_info_pad_t)pi; 496 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 497 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 498 #ifndef __LP64__ 499 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 500 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 501 #endif 502 } 503 504 static inline void 505 rxd_info_zero(if_rxd_info_t ri) 506 { 507 if_rxd_info_pad_t ri_pad; 508 int i; 509 510 ri_pad = (if_rxd_info_pad_t)ri; 511 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 512 ri_pad->rxd_val[i] = 0; 513 ri_pad->rxd_val[i+1] = 0; 514 ri_pad->rxd_val[i+2] = 0; 515 ri_pad->rxd_val[i+3] = 0; 516 } 517 #ifdef __LP64__ 518 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 519 #endif 520 } 521 522 /* 523 * Only allow a single packet to take up most 1/nth of the tx ring 524 */ 525 #define MAX_SINGLE_PACKET_FRACTION 12 526 #define IF_BAD_DMA (bus_addr_t)-1 527 528 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 529 530 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF) 531 532 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx) 533 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx) 534 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx) 535 536 537 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 538 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 539 540 541 /* Our boot-time initialization hook */ 542 static int iflib_module_event_handler(module_t, int, void *); 543 544 static moduledata_t iflib_moduledata = { 545 "iflib", 546 iflib_module_event_handler, 547 NULL 548 }; 549 550 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 551 MODULE_VERSION(iflib, 1); 552 553 MODULE_DEPEND(iflib, pci, 1, 1, 1); 554 MODULE_DEPEND(iflib, ether, 1, 1, 1); 555 556 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 557 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 558 559 #ifndef IFLIB_DEBUG_COUNTERS 560 #ifdef INVARIANTS 561 #define IFLIB_DEBUG_COUNTERS 1 562 #else 563 #define IFLIB_DEBUG_COUNTERS 0 564 #endif /* !INVARIANTS */ 565 #endif 566 567 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 568 "iflib driver parameters"); 569 570 /* 571 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 572 */ 573 static int iflib_min_tx_latency = 0; 574 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 575 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 576 static int iflib_no_tx_batch = 0; 577 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 578 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 579 580 581 #if IFLIB_DEBUG_COUNTERS 582 583 static int iflib_tx_seen; 584 static int iflib_tx_sent; 585 static int iflib_tx_encap; 586 static int iflib_rx_allocs; 587 static int iflib_fl_refills; 588 static int iflib_fl_refills_large; 589 static int iflib_tx_frees; 590 591 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 592 &iflib_tx_seen, 0, "# tx mbufs seen"); 593 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 594 &iflib_tx_sent, 0, "# tx mbufs sent"); 595 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 596 &iflib_tx_encap, 0, "# tx mbufs encapped"); 597 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 598 &iflib_tx_frees, 0, "# tx frees"); 599 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 600 &iflib_rx_allocs, 0, "# rx allocations"); 601 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 602 &iflib_fl_refills, 0, "# refills"); 603 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 604 &iflib_fl_refills_large, 0, "# large refills"); 605 606 607 static int iflib_txq_drain_flushing; 608 static int iflib_txq_drain_oactive; 609 static int iflib_txq_drain_notready; 610 static int iflib_txq_drain_encapfail; 611 612 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 613 &iflib_txq_drain_flushing, 0, "# drain flushes"); 614 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 615 &iflib_txq_drain_oactive, 0, "# drain oactives"); 616 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 617 &iflib_txq_drain_notready, 0, "# drain notready"); 618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 619 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 620 621 622 static int iflib_encap_load_mbuf_fail; 623 static int iflib_encap_txq_avail_fail; 624 static int iflib_encap_txd_encap_fail; 625 626 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 627 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 628 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 629 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 630 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 631 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 632 633 static int iflib_task_fn_rxs; 634 static int iflib_rx_intr_enables; 635 static int iflib_fast_intrs; 636 static int iflib_intr_link; 637 static int iflib_intr_msix; 638 static int iflib_rx_unavail; 639 static int iflib_rx_ctx_inactive; 640 static int iflib_rx_zero_len; 641 static int iflib_rx_if_input; 642 static int iflib_rx_mbuf_null; 643 static int iflib_rxd_flush; 644 645 static int iflib_verbose_debug; 646 647 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 648 &iflib_intr_link, 0, "# intr link calls"); 649 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 650 &iflib_intr_msix, 0, "# intr msix calls"); 651 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 652 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 653 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 654 &iflib_rx_intr_enables, 0, "# rx intr enables"); 655 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 656 &iflib_fast_intrs, 0, "# fast_intr calls"); 657 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 658 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 660 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 662 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 664 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 666 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 668 &iflib_rxd_flush, 0, "# times rxd_flush called"); 669 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 670 &iflib_verbose_debug, 0, "enable verbose debugging"); 671 672 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 673 static void 674 iflib_debug_reset(void) 675 { 676 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 677 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 678 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 679 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 680 iflib_encap_load_mbuf_fail = iflib_encap_txq_avail_fail = 681 iflib_encap_txd_encap_fail = iflib_task_fn_rxs = iflib_rx_intr_enables = 682 iflib_fast_intrs = iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 683 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 684 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 685 } 686 687 #else 688 #define DBG_COUNTER_INC(name) 689 static void iflib_debug_reset(void) {} 690 #endif 691 692 693 694 #define IFLIB_DEBUG 0 695 696 static void iflib_tx_structures_free(if_ctx_t ctx); 697 static void iflib_rx_structures_free(if_ctx_t ctx); 698 static int iflib_queues_alloc(if_ctx_t ctx); 699 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 700 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 701 static int iflib_qset_structures_setup(if_ctx_t ctx); 702 static int iflib_msix_init(if_ctx_t ctx); 703 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str); 704 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 705 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 706 static int iflib_register(if_ctx_t); 707 static void iflib_init_locked(if_ctx_t ctx); 708 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 709 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 710 static void iflib_ifmp_purge(iflib_txq_t txq); 711 static void _iflib_pre_assert(if_softc_ctx_t scctx); 712 static void iflib_stop(if_ctx_t ctx); 713 static void iflib_if_init_locked(if_ctx_t ctx); 714 #ifndef __NO_STRICT_ALIGNMENT 715 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 716 #endif 717 718 #ifdef DEV_NETMAP 719 #include <sys/selinfo.h> 720 #include <net/netmap.h> 721 #include <dev/netmap/netmap_kern.h> 722 723 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 724 725 /* 726 * device-specific sysctl variables: 727 * 728 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 729 * During regular operations the CRC is stripped, but on some 730 * hardware reception of frames not multiple of 64 is slower, 731 * so using crcstrip=0 helps in benchmarks. 732 * 733 * iflib_rx_miss, iflib_rx_miss_bufs: 734 * count packets that might be missed due to lost interrupts. 735 */ 736 SYSCTL_DECL(_dev_netmap); 737 /* 738 * The xl driver by default strips CRCs and we do not override it. 739 */ 740 741 int iflib_crcstrip = 1; 742 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 743 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 744 745 int iflib_rx_miss, iflib_rx_miss_bufs; 746 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 747 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 748 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 749 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 750 751 /* 752 * Register/unregister. We are already under netmap lock. 753 * Only called on the first register or the last unregister. 754 */ 755 static int 756 iflib_netmap_register(struct netmap_adapter *na, int onoff) 757 { 758 struct ifnet *ifp = na->ifp; 759 if_ctx_t ctx = ifp->if_softc; 760 int status; 761 762 CTX_LOCK(ctx); 763 IFDI_INTR_DISABLE(ctx); 764 765 /* Tell the stack that the interface is no longer active */ 766 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 767 768 if (!CTX_IS_VF(ctx)) 769 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 770 771 /* enable or disable flags and callbacks in na and ifp */ 772 if (onoff) { 773 nm_set_native_flags(na); 774 } else { 775 nm_clear_native_flags(na); 776 } 777 iflib_stop(ctx); 778 iflib_init_locked(ctx); 779 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 780 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 781 if (status) 782 nm_clear_native_flags(na); 783 CTX_UNLOCK(ctx); 784 return (status); 785 } 786 787 /* 788 * Reconcile kernel and user view of the transmit ring. 789 * 790 * All information is in the kring. 791 * Userspace wants to send packets up to the one before kring->rhead, 792 * kernel knows kring->nr_hwcur is the first unsent packet. 793 * 794 * Here we push packets out (as many as possible), and possibly 795 * reclaim buffers from previously completed transmission. 796 * 797 * The caller (netmap) guarantees that there is only one instance 798 * running at any time. Any interference with other driver 799 * methods should be handled by the individual drivers. 800 */ 801 static int 802 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 803 { 804 struct netmap_adapter *na = kring->na; 805 struct ifnet *ifp = na->ifp; 806 struct netmap_ring *ring = kring->ring; 807 u_int nm_i; /* index into the netmap ring */ 808 u_int nic_i; /* index into the NIC ring */ 809 u_int n; 810 u_int const lim = kring->nkr_num_slots - 1; 811 u_int const head = kring->rhead; 812 struct if_pkt_info pi; 813 814 /* 815 * interrupts on every tx packet are expensive so request 816 * them every half ring, or where NS_REPORT is set 817 */ 818 u_int report_frequency = kring->nkr_num_slots >> 1; 819 /* device-specific */ 820 if_ctx_t ctx = ifp->if_softc; 821 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 822 823 if (txq->ift_sds.ifsd_map) 824 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 825 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 826 827 828 /* 829 * First part: process new packets to send. 830 * nm_i is the current index in the netmap ring, 831 * nic_i is the corresponding index in the NIC ring. 832 * 833 * If we have packets to send (nm_i != head) 834 * iterate over the netmap ring, fetch length and update 835 * the corresponding slot in the NIC ring. Some drivers also 836 * need to update the buffer's physical address in the NIC slot 837 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 838 * 839 * The netmap_reload_map() calls is especially expensive, 840 * even when (as in this case) the tag is 0, so do only 841 * when the buffer has actually changed. 842 * 843 * If possible do not set the report/intr bit on all slots, 844 * but only a few times per ring or when NS_REPORT is set. 845 * 846 * Finally, on 10G and faster drivers, it might be useful 847 * to prefetch the next slot and txr entry. 848 */ 849 850 nm_i = kring->nr_hwcur; 851 pkt_info_zero(&pi); 852 pi.ipi_segs = txq->ift_segs; 853 pi.ipi_qsidx = kring->ring_id; 854 if (nm_i != head) { /* we have new packets to send */ 855 nic_i = netmap_idx_k2n(kring, nm_i); 856 857 __builtin_prefetch(&ring->slot[nm_i]); 858 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 859 if (txq->ift_sds.ifsd_map) 860 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 861 862 for (n = 0; nm_i != head; n++) { 863 struct netmap_slot *slot = &ring->slot[nm_i]; 864 u_int len = slot->len; 865 uint64_t paddr; 866 void *addr = PNMB(na, slot, &paddr); 867 int flags = (slot->flags & NS_REPORT || 868 nic_i == 0 || nic_i == report_frequency) ? 869 IPI_TX_INTR : 0; 870 871 /* device-specific */ 872 pi.ipi_len = len; 873 pi.ipi_segs[0].ds_addr = paddr; 874 pi.ipi_segs[0].ds_len = len; 875 pi.ipi_nsegs = 1; 876 pi.ipi_ndescs = 0; 877 pi.ipi_pidx = nic_i; 878 pi.ipi_flags = flags; 879 880 /* Fill the slot in the NIC ring. */ 881 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 882 883 /* prefetch for next round */ 884 __builtin_prefetch(&ring->slot[nm_i + 1]); 885 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 886 if (txq->ift_sds.ifsd_map) { 887 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 888 889 NM_CHECK_ADDR_LEN(na, addr, len); 890 891 if (slot->flags & NS_BUF_CHANGED) { 892 /* buffer has changed, reload map */ 893 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 894 } 895 /* make sure changes to the buffer are synced */ 896 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 897 BUS_DMASYNC_PREWRITE); 898 } 899 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 900 nm_i = nm_next(nm_i, lim); 901 nic_i = nm_next(nic_i, lim); 902 } 903 kring->nr_hwcur = head; 904 905 /* synchronize the NIC ring */ 906 if (txq->ift_sds.ifsd_map) 907 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 908 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 909 910 /* (re)start the tx unit up to slot nic_i (excluded) */ 911 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 912 } 913 914 /* 915 * Second part: reclaim buffers for completed transmissions. 916 */ 917 if (iflib_tx_credits_update(ctx, txq)) { 918 /* some tx completed, increment avail */ 919 nic_i = txq->ift_cidx_processed; 920 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 921 } 922 return (0); 923 } 924 925 /* 926 * Reconcile kernel and user view of the receive ring. 927 * Same as for the txsync, this routine must be efficient. 928 * The caller guarantees a single invocations, but races against 929 * the rest of the driver should be handled here. 930 * 931 * On call, kring->rhead is the first packet that userspace wants 932 * to keep, and kring->rcur is the wakeup point. 933 * The kernel has previously reported packets up to kring->rtail. 934 * 935 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 936 * of whether or not we received an interrupt. 937 */ 938 static int 939 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 940 { 941 struct netmap_adapter *na = kring->na; 942 struct netmap_ring *ring = kring->ring; 943 uint32_t nm_i; /* index into the netmap ring */ 944 uint32_t nic_i, nic_i_start; /* index into the NIC ring */ 945 u_int i, n; 946 u_int const lim = kring->nkr_num_slots - 1; 947 u_int const head = kring->rhead; 948 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 949 struct if_rxd_info ri; 950 struct if_rxd_update iru; 951 952 struct ifnet *ifp = na->ifp; 953 if_ctx_t ctx = ifp->if_softc; 954 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 955 iflib_fl_t fl = rxq->ifr_fl; 956 if (head > lim) 957 return netmap_ring_reinit(kring); 958 959 /* XXX check sync modes */ 960 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 961 if (fl->ifl_sds.ifsd_map == NULL) 962 continue; 963 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 964 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 965 } 966 /* 967 * First part: import newly received packets. 968 * 969 * nm_i is the index of the next free slot in the netmap ring, 970 * nic_i is the index of the next received packet in the NIC ring, 971 * and they may differ in case if_init() has been called while 972 * in netmap mode. For the receive ring we have 973 * 974 * nic_i = rxr->next_check; 975 * nm_i = kring->nr_hwtail (previous) 976 * and 977 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 978 * 979 * rxr->next_check is set to 0 on a ring reinit 980 */ 981 if (netmap_no_pendintr || force_update) { 982 int crclen = iflib_crcstrip ? 0 : 4; 983 int error, avail; 984 uint16_t slot_flags = kring->nkr_slot_flags; 985 986 for (fl = rxq->ifr_fl, i = 0; i < rxq->ifr_nfl; i++, fl++) { 987 nic_i = fl->ifl_cidx; 988 nm_i = netmap_idx_n2k(kring, nic_i); 989 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 990 for (n = 0; avail > 0; n++, avail--) { 991 rxd_info_zero(&ri); 992 ri.iri_frags = rxq->ifr_frags; 993 ri.iri_qsidx = kring->ring_id; 994 ri.iri_ifp = ctx->ifc_ifp; 995 ri.iri_cidx = nic_i; 996 997 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 998 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 999 ring->slot[nm_i].flags = slot_flags; 1000 if (fl->ifl_sds.ifsd_map) 1001 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1002 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1003 nm_i = nm_next(nm_i, lim); 1004 nic_i = nm_next(nic_i, lim); 1005 } 1006 if (n) { /* update the state variables */ 1007 if (netmap_no_pendintr && !force_update) { 1008 /* diagnostics */ 1009 iflib_rx_miss ++; 1010 iflib_rx_miss_bufs += n; 1011 } 1012 fl->ifl_cidx = nic_i; 1013 kring->nr_hwtail = nm_i; 1014 } 1015 kring->nr_kflags &= ~NKR_PENDINTR; 1016 } 1017 } 1018 /* 1019 * Second part: skip past packets that userspace has released. 1020 * (kring->nr_hwcur to head excluded), 1021 * and make the buffers available for reception. 1022 * As usual nm_i is the index in the netmap ring, 1023 * nic_i is the index in the NIC ring, and 1024 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1025 */ 1026 /* XXX not sure how this will work with multiple free lists */ 1027 nm_i = kring->nr_hwcur; 1028 if (nm_i == head) 1029 return (0); 1030 1031 iru.iru_paddrs = fl->ifl_bus_addrs; 1032 iru.iru_vaddrs = &fl->ifl_vm_addrs[0]; 1033 iru.iru_idxs = fl->ifl_rxd_idxs; 1034 iru.iru_qsidx = rxq->ifr_id; 1035 iru.iru_buf_size = fl->ifl_buf_size; 1036 iru.iru_flidx = fl->ifl_id; 1037 nic_i_start = nic_i = netmap_idx_k2n(kring, nm_i); 1038 for (i = 0; nm_i != head; i++) { 1039 struct netmap_slot *slot = &ring->slot[nm_i]; 1040 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]); 1041 1042 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 1043 goto ring_reset; 1044 1045 fl->ifl_vm_addrs[i] = addr; 1046 if (fl->ifl_sds.ifsd_map && (slot->flags & NS_BUF_CHANGED)) { 1047 /* buffer has changed, reload map */ 1048 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i], addr); 1049 } 1050 slot->flags &= ~NS_BUF_CHANGED; 1051 1052 nm_i = nm_next(nm_i, lim); 1053 fl->ifl_rxd_idxs[i] = nic_i = nm_next(nic_i, lim); 1054 if (nm_i != head && i < IFLIB_MAX_RX_REFRESH) 1055 continue; 1056 1057 iru.iru_pidx = nic_i_start; 1058 iru.iru_count = i; 1059 i = 0; 1060 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1061 if (fl->ifl_sds.ifsd_map == NULL) { 1062 nic_i_start = nic_i; 1063 continue; 1064 } 1065 nic_i = nic_i_start; 1066 for (n = 0; n < iru.iru_count; n++) { 1067 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i], 1068 BUS_DMASYNC_PREREAD); 1069 nic_i = nm_next(nic_i, lim); 1070 } 1071 nic_i_start = nic_i; 1072 } 1073 kring->nr_hwcur = head; 1074 1075 if (fl->ifl_sds.ifsd_map) 1076 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1077 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1078 /* 1079 * IMPORTANT: we must leave one free slot in the ring, 1080 * so move nic_i back by one unit 1081 */ 1082 nic_i = nm_prev(nic_i, lim); 1083 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 1084 return 0; 1085 1086 ring_reset: 1087 return netmap_ring_reinit(kring); 1088 } 1089 1090 static void 1091 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1092 { 1093 struct ifnet *ifp = na->ifp; 1094 if_ctx_t ctx = ifp->if_softc; 1095 1096 CTX_LOCK(ctx); 1097 if (onoff) { 1098 IFDI_INTR_ENABLE(ctx); 1099 } else { 1100 IFDI_INTR_DISABLE(ctx); 1101 } 1102 CTX_UNLOCK(ctx); 1103 } 1104 1105 1106 static int 1107 iflib_netmap_attach(if_ctx_t ctx) 1108 { 1109 struct netmap_adapter na; 1110 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1111 1112 bzero(&na, sizeof(na)); 1113 1114 na.ifp = ctx->ifc_ifp; 1115 na.na_flags = NAF_BDG_MAYSLEEP; 1116 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1117 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1118 1119 na.num_tx_desc = scctx->isc_ntxd[0]; 1120 na.num_rx_desc = scctx->isc_nrxd[0]; 1121 na.nm_txsync = iflib_netmap_txsync; 1122 na.nm_rxsync = iflib_netmap_rxsync; 1123 na.nm_register = iflib_netmap_register; 1124 na.nm_intr = iflib_netmap_intr; 1125 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1126 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1127 return (netmap_attach(&na)); 1128 } 1129 1130 static void 1131 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1132 { 1133 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1134 struct netmap_slot *slot; 1135 1136 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1137 if (slot == NULL) 1138 return; 1139 if (txq->ift_sds.ifsd_map == NULL) 1140 return; 1141 1142 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1143 1144 /* 1145 * In netmap mode, set the map for the packet buffer. 1146 * NOTE: Some drivers (not this one) also need to set 1147 * the physical buffer address in the NIC ring. 1148 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1149 * netmap slot index, si 1150 */ 1151 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i); 1152 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1153 } 1154 } 1155 static void 1156 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1157 { 1158 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1159 struct netmap_slot *slot; 1160 struct if_rxd_update iru; 1161 iflib_fl_t fl; 1162 bus_dmamap_t *map; 1163 int nrxd; 1164 uint32_t i, j, pidx_start; 1165 1166 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1167 if (slot == NULL) 1168 return; 1169 fl = &rxq->ifr_fl[0]; 1170 map = fl->ifl_sds.ifsd_map; 1171 nrxd = ctx->ifc_softc_ctx.isc_nrxd[0]; 1172 iru.iru_paddrs = fl->ifl_bus_addrs; 1173 iru.iru_vaddrs = &fl->ifl_vm_addrs[0]; 1174 iru.iru_idxs = fl->ifl_rxd_idxs; 1175 iru.iru_qsidx = rxq->ifr_id; 1176 iru.iru_buf_size = rxq->ifr_fl[0].ifl_buf_size; 1177 iru.iru_flidx = 0; 1178 1179 for (pidx_start = i = j = 0; i < nrxd; i++, j++) { 1180 int sj = netmap_idx_n2k(&na->rx_rings[rxq->ifr_id], i); 1181 void *addr; 1182 1183 fl->ifl_rxd_idxs[j] = i; 1184 addr = fl->ifl_vm_addrs[j] = PNMB(na, slot + sj, &fl->ifl_bus_addrs[j]); 1185 if (map) { 1186 netmap_load_map(na, rxq->ifr_fl[0].ifl_ifdi->idi_tag, *map, addr); 1187 map++; 1188 } 1189 1190 if (j < IFLIB_MAX_RX_REFRESH && i < nrxd - 1) 1191 continue; 1192 1193 iru.iru_pidx = pidx_start; 1194 pidx_start = i; 1195 iru.iru_count = j; 1196 j = 0; 1197 MPASS(pidx_start + j <= nrxd); 1198 /* Update descriptors and the cached value */ 1199 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1200 } 1201 /* preserve queue */ 1202 if (ctx->ifc_ifp->if_capenable & IFCAP_NETMAP) { 1203 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id]; 1204 int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring); 1205 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, t); 1206 } else 1207 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, nrxd-1); 1208 } 1209 1210 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1211 1212 #else 1213 #define iflib_netmap_txq_init(ctx, txq) 1214 #define iflib_netmap_rxq_init(ctx, rxq) 1215 #define iflib_netmap_detach(ifp) 1216 1217 #define iflib_netmap_attach(ctx) (0) 1218 #define netmap_rx_irq(ifp, qid, budget) (0) 1219 #define netmap_tx_irq(ifp, qid) do {} while (0) 1220 1221 #endif 1222 1223 #if defined(__i386__) || defined(__amd64__) 1224 static __inline void 1225 prefetch(void *x) 1226 { 1227 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1228 } 1229 #else 1230 #define prefetch(x) 1231 #endif 1232 1233 static void 1234 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1235 { 1236 if (err) 1237 return; 1238 *(bus_addr_t *) arg = segs[0].ds_addr; 1239 } 1240 1241 int 1242 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1243 { 1244 int err; 1245 if_shared_ctx_t sctx = ctx->ifc_sctx; 1246 device_t dev = ctx->ifc_dev; 1247 1248 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1249 1250 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1251 sctx->isc_q_align, 0, /* alignment, bounds */ 1252 BUS_SPACE_MAXADDR, /* lowaddr */ 1253 BUS_SPACE_MAXADDR, /* highaddr */ 1254 NULL, NULL, /* filter, filterarg */ 1255 size, /* maxsize */ 1256 1, /* nsegments */ 1257 size, /* maxsegsize */ 1258 BUS_DMA_ALLOCNOW, /* flags */ 1259 NULL, /* lockfunc */ 1260 NULL, /* lockarg */ 1261 &dma->idi_tag); 1262 if (err) { 1263 device_printf(dev, 1264 "%s: bus_dma_tag_create failed: %d\n", 1265 __func__, err); 1266 goto fail_0; 1267 } 1268 1269 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1270 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1271 if (err) { 1272 device_printf(dev, 1273 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1274 __func__, (uintmax_t)size, err); 1275 goto fail_1; 1276 } 1277 1278 dma->idi_paddr = IF_BAD_DMA; 1279 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1280 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1281 if (err || dma->idi_paddr == IF_BAD_DMA) { 1282 device_printf(dev, 1283 "%s: bus_dmamap_load failed: %d\n", 1284 __func__, err); 1285 goto fail_2; 1286 } 1287 1288 dma->idi_size = size; 1289 return (0); 1290 1291 fail_2: 1292 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1293 fail_1: 1294 bus_dma_tag_destroy(dma->idi_tag); 1295 fail_0: 1296 dma->idi_tag = NULL; 1297 1298 return (err); 1299 } 1300 1301 int 1302 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1303 { 1304 int i, err; 1305 iflib_dma_info_t *dmaiter; 1306 1307 dmaiter = dmalist; 1308 for (i = 0; i < count; i++, dmaiter++) { 1309 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1310 break; 1311 } 1312 if (err) 1313 iflib_dma_free_multi(dmalist, i); 1314 return (err); 1315 } 1316 1317 void 1318 iflib_dma_free(iflib_dma_info_t dma) 1319 { 1320 if (dma->idi_tag == NULL) 1321 return; 1322 if (dma->idi_paddr != IF_BAD_DMA) { 1323 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1324 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1325 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1326 dma->idi_paddr = IF_BAD_DMA; 1327 } 1328 if (dma->idi_vaddr != NULL) { 1329 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1330 dma->idi_vaddr = NULL; 1331 } 1332 bus_dma_tag_destroy(dma->idi_tag); 1333 dma->idi_tag = NULL; 1334 } 1335 1336 void 1337 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1338 { 1339 int i; 1340 iflib_dma_info_t *dmaiter = dmalist; 1341 1342 for (i = 0; i < count; i++, dmaiter++) 1343 iflib_dma_free(*dmaiter); 1344 } 1345 1346 #ifdef EARLY_AP_STARTUP 1347 static const int iflib_started = 1; 1348 #else 1349 /* 1350 * We used to abuse the smp_started flag to decide if the queues have been 1351 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1352 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1353 * is set. Run a SYSINIT() strictly after that to just set a usable 1354 * completion flag. 1355 */ 1356 1357 static int iflib_started; 1358 1359 static void 1360 iflib_record_started(void *arg) 1361 { 1362 iflib_started = 1; 1363 } 1364 1365 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1366 iflib_record_started, NULL); 1367 #endif 1368 1369 static int 1370 iflib_fast_intr(void *arg) 1371 { 1372 iflib_filter_info_t info = arg; 1373 struct grouptask *gtask = info->ifi_task; 1374 if (!iflib_started) 1375 return (FILTER_HANDLED); 1376 1377 DBG_COUNTER_INC(fast_intrs); 1378 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1379 return (FILTER_HANDLED); 1380 1381 GROUPTASK_ENQUEUE(gtask); 1382 return (FILTER_HANDLED); 1383 } 1384 1385 static int 1386 iflib_fast_intr_rxtx(void *arg) 1387 { 1388 iflib_filter_info_t info = arg; 1389 struct grouptask *gtask = info->ifi_task; 1390 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1391 if_ctx_t ctx; 1392 int i, cidx; 1393 1394 if (!iflib_started) 1395 return (FILTER_HANDLED); 1396 1397 DBG_COUNTER_INC(fast_intrs); 1398 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1399 return (FILTER_HANDLED); 1400 1401 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1402 qidx_t txqid = rxq->ifr_txqid[i]; 1403 1404 ctx = rxq->ifr_ctx; 1405 1406 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1407 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1408 continue; 1409 } 1410 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1411 } 1412 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1413 cidx = rxq->ifr_cq_cidx; 1414 else 1415 cidx = rxq->ifr_fl[0].ifl_cidx; 1416 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1417 GROUPTASK_ENQUEUE(gtask); 1418 else 1419 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1420 return (FILTER_HANDLED); 1421 } 1422 1423 1424 static int 1425 iflib_fast_intr_ctx(void *arg) 1426 { 1427 iflib_filter_info_t info = arg; 1428 struct grouptask *gtask = info->ifi_task; 1429 1430 if (!iflib_started) 1431 return (FILTER_HANDLED); 1432 1433 DBG_COUNTER_INC(fast_intrs); 1434 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1435 return (FILTER_HANDLED); 1436 1437 GROUPTASK_ENQUEUE(gtask); 1438 return (FILTER_HANDLED); 1439 } 1440 1441 static int 1442 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1443 driver_filter_t filter, driver_intr_t handler, void *arg, 1444 char *name) 1445 { 1446 int rc, flags; 1447 struct resource *res; 1448 void *tag = NULL; 1449 device_t dev = ctx->ifc_dev; 1450 1451 flags = RF_ACTIVE; 1452 if (ctx->ifc_flags & IFC_LEGACY) 1453 flags |= RF_SHAREABLE; 1454 MPASS(rid < 512); 1455 irq->ii_rid = rid; 1456 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1457 if (res == NULL) { 1458 device_printf(dev, 1459 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1460 return (ENOMEM); 1461 } 1462 irq->ii_res = res; 1463 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1464 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1465 filter, handler, arg, &tag); 1466 if (rc != 0) { 1467 device_printf(dev, 1468 "failed to setup interrupt for rid %d, name %s: %d\n", 1469 rid, name ? name : "unknown", rc); 1470 return (rc); 1471 } else if (name) 1472 bus_describe_intr(dev, res, tag, "%s", name); 1473 1474 irq->ii_tag = tag; 1475 return (0); 1476 } 1477 1478 1479 /********************************************************************* 1480 * 1481 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1482 * the information needed to transmit a packet on the wire. This is 1483 * called only once at attach, setup is done every reset. 1484 * 1485 **********************************************************************/ 1486 1487 static int 1488 iflib_txsd_alloc(iflib_txq_t txq) 1489 { 1490 if_ctx_t ctx = txq->ift_ctx; 1491 if_shared_ctx_t sctx = ctx->ifc_sctx; 1492 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1493 device_t dev = ctx->ifc_dev; 1494 int err, nsegments, ntsosegments; 1495 1496 nsegments = scctx->isc_tx_nsegments; 1497 ntsosegments = scctx->isc_tx_tso_segments_max; 1498 MPASS(scctx->isc_ntxd[0] > 0); 1499 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1500 MPASS(nsegments > 0); 1501 MPASS(ntsosegments > 0); 1502 /* 1503 * Setup DMA descriptor areas. 1504 */ 1505 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1506 1, 0, /* alignment, bounds */ 1507 BUS_SPACE_MAXADDR, /* lowaddr */ 1508 BUS_SPACE_MAXADDR, /* highaddr */ 1509 NULL, NULL, /* filter, filterarg */ 1510 sctx->isc_tx_maxsize, /* maxsize */ 1511 nsegments, /* nsegments */ 1512 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1513 0, /* flags */ 1514 NULL, /* lockfunc */ 1515 NULL, /* lockfuncarg */ 1516 &txq->ift_desc_tag))) { 1517 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1518 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1519 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1520 goto fail; 1521 } 1522 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1523 1, 0, /* alignment, bounds */ 1524 BUS_SPACE_MAXADDR, /* lowaddr */ 1525 BUS_SPACE_MAXADDR, /* highaddr */ 1526 NULL, NULL, /* filter, filterarg */ 1527 scctx->isc_tx_tso_size_max, /* maxsize */ 1528 ntsosegments, /* nsegments */ 1529 scctx->isc_tx_tso_segsize_max, /* maxsegsize */ 1530 0, /* flags */ 1531 NULL, /* lockfunc */ 1532 NULL, /* lockfuncarg */ 1533 &txq->ift_tso_desc_tag))) { 1534 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1535 1536 goto fail; 1537 } 1538 if (!(txq->ift_sds.ifsd_flags = 1539 (uint8_t *) malloc(sizeof(uint8_t) * 1540 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1541 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1542 err = ENOMEM; 1543 goto fail; 1544 } 1545 if (!(txq->ift_sds.ifsd_m = 1546 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1547 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1548 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1549 err = ENOMEM; 1550 goto fail; 1551 } 1552 1553 /* Create the descriptor buffer dma maps */ 1554 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1555 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1556 return (0); 1557 1558 if (!(txq->ift_sds.ifsd_map = 1559 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1560 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1561 err = ENOMEM; 1562 goto fail; 1563 } 1564 1565 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1566 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1567 if (err != 0) { 1568 device_printf(dev, "Unable to create TX DMA map\n"); 1569 goto fail; 1570 } 1571 } 1572 #endif 1573 return (0); 1574 fail: 1575 /* We free all, it handles case where we are in the middle */ 1576 iflib_tx_structures_free(ctx); 1577 return (err); 1578 } 1579 1580 static void 1581 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1582 { 1583 bus_dmamap_t map; 1584 1585 map = NULL; 1586 if (txq->ift_sds.ifsd_map != NULL) 1587 map = txq->ift_sds.ifsd_map[i]; 1588 if (map != NULL) { 1589 bus_dmamap_unload(txq->ift_desc_tag, map); 1590 bus_dmamap_destroy(txq->ift_desc_tag, map); 1591 txq->ift_sds.ifsd_map[i] = NULL; 1592 } 1593 } 1594 1595 static void 1596 iflib_txq_destroy(iflib_txq_t txq) 1597 { 1598 if_ctx_t ctx = txq->ift_ctx; 1599 1600 for (int i = 0; i < txq->ift_size; i++) 1601 iflib_txsd_destroy(ctx, txq, i); 1602 if (txq->ift_sds.ifsd_map != NULL) { 1603 free(txq->ift_sds.ifsd_map, M_IFLIB); 1604 txq->ift_sds.ifsd_map = NULL; 1605 } 1606 if (txq->ift_sds.ifsd_m != NULL) { 1607 free(txq->ift_sds.ifsd_m, M_IFLIB); 1608 txq->ift_sds.ifsd_m = NULL; 1609 } 1610 if (txq->ift_sds.ifsd_flags != NULL) { 1611 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1612 txq->ift_sds.ifsd_flags = NULL; 1613 } 1614 if (txq->ift_desc_tag != NULL) { 1615 bus_dma_tag_destroy(txq->ift_desc_tag); 1616 txq->ift_desc_tag = NULL; 1617 } 1618 if (txq->ift_tso_desc_tag != NULL) { 1619 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1620 txq->ift_tso_desc_tag = NULL; 1621 } 1622 } 1623 1624 static void 1625 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1626 { 1627 struct mbuf **mp; 1628 1629 mp = &txq->ift_sds.ifsd_m[i]; 1630 if (*mp == NULL) 1631 return; 1632 1633 if (txq->ift_sds.ifsd_map != NULL) { 1634 bus_dmamap_sync(txq->ift_desc_tag, 1635 txq->ift_sds.ifsd_map[i], 1636 BUS_DMASYNC_POSTWRITE); 1637 bus_dmamap_unload(txq->ift_desc_tag, 1638 txq->ift_sds.ifsd_map[i]); 1639 } 1640 m_free(*mp); 1641 DBG_COUNTER_INC(tx_frees); 1642 *mp = NULL; 1643 } 1644 1645 static int 1646 iflib_txq_setup(iflib_txq_t txq) 1647 { 1648 if_ctx_t ctx = txq->ift_ctx; 1649 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1650 iflib_dma_info_t di; 1651 int i; 1652 1653 /* Set number of descriptors available */ 1654 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1655 /* XXX make configurable */ 1656 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1657 1658 /* Reset indices */ 1659 txq->ift_cidx_processed = 0; 1660 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1661 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1662 1663 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1664 bzero((void *)di->idi_vaddr, di->idi_size); 1665 1666 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1667 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1668 bus_dmamap_sync(di->idi_tag, di->idi_map, 1669 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1670 return (0); 1671 } 1672 1673 /********************************************************************* 1674 * 1675 * Allocate memory for rx_buffer structures. Since we use one 1676 * rx_buffer per received packet, the maximum number of rx_buffer's 1677 * that we'll need is equal to the number of receive descriptors 1678 * that we've allocated. 1679 * 1680 **********************************************************************/ 1681 static int 1682 iflib_rxsd_alloc(iflib_rxq_t rxq) 1683 { 1684 if_ctx_t ctx = rxq->ifr_ctx; 1685 if_shared_ctx_t sctx = ctx->ifc_sctx; 1686 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1687 device_t dev = ctx->ifc_dev; 1688 iflib_fl_t fl; 1689 int err; 1690 1691 MPASS(scctx->isc_nrxd[0] > 0); 1692 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1693 1694 fl = rxq->ifr_fl; 1695 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1696 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1697 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1698 1, 0, /* alignment, bounds */ 1699 BUS_SPACE_MAXADDR, /* lowaddr */ 1700 BUS_SPACE_MAXADDR, /* highaddr */ 1701 NULL, NULL, /* filter, filterarg */ 1702 sctx->isc_rx_maxsize, /* maxsize */ 1703 sctx->isc_rx_nsegments, /* nsegments */ 1704 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1705 0, /* flags */ 1706 NULL, /* lockfunc */ 1707 NULL, /* lockarg */ 1708 &fl->ifl_desc_tag); 1709 if (err) { 1710 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1711 __func__, err); 1712 goto fail; 1713 } 1714 if (!(fl->ifl_sds.ifsd_flags = 1715 (uint8_t *) malloc(sizeof(uint8_t) * 1716 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1717 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1718 err = ENOMEM; 1719 goto fail; 1720 } 1721 if (!(fl->ifl_sds.ifsd_m = 1722 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1723 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1724 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1725 err = ENOMEM; 1726 goto fail; 1727 } 1728 if (!(fl->ifl_sds.ifsd_cl = 1729 (caddr_t *) malloc(sizeof(caddr_t) * 1730 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1731 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1732 err = ENOMEM; 1733 goto fail; 1734 } 1735 1736 /* Create the descriptor buffer dma maps */ 1737 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1738 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1739 continue; 1740 1741 if (!(fl->ifl_sds.ifsd_map = 1742 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1743 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1744 err = ENOMEM; 1745 goto fail; 1746 } 1747 1748 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1749 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1750 if (err != 0) { 1751 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1752 goto fail; 1753 } 1754 } 1755 #endif 1756 } 1757 return (0); 1758 1759 fail: 1760 iflib_rx_structures_free(ctx); 1761 return (err); 1762 } 1763 1764 1765 /* 1766 * Internal service routines 1767 */ 1768 1769 struct rxq_refill_cb_arg { 1770 int error; 1771 bus_dma_segment_t seg; 1772 int nseg; 1773 }; 1774 1775 static void 1776 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1777 { 1778 struct rxq_refill_cb_arg *cb_arg = arg; 1779 1780 cb_arg->error = error; 1781 cb_arg->seg = segs[0]; 1782 cb_arg->nseg = nseg; 1783 } 1784 1785 1786 #ifdef ACPI_DMAR 1787 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1788 #else 1789 #define IS_DMAR(ctx) (0) 1790 #endif 1791 1792 /** 1793 * rxq_refill - refill an rxq free-buffer list 1794 * @ctx: the iflib context 1795 * @rxq: the free-list to refill 1796 * @n: the number of new buffers to allocate 1797 * 1798 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1799 * The caller must assure that @n does not exceed the queue's capacity. 1800 */ 1801 static void 1802 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1803 { 1804 struct mbuf *m; 1805 int idx, frag_idx = fl->ifl_fragidx; 1806 int pidx = fl->ifl_pidx; 1807 caddr_t cl, *sd_cl; 1808 struct mbuf **sd_m; 1809 uint8_t *sd_flags; 1810 struct if_rxd_update iru; 1811 bus_dmamap_t *sd_map; 1812 int n, i = 0; 1813 uint64_t bus_addr; 1814 int err; 1815 1816 sd_m = fl->ifl_sds.ifsd_m; 1817 sd_map = fl->ifl_sds.ifsd_map; 1818 sd_cl = fl->ifl_sds.ifsd_cl; 1819 sd_flags = fl->ifl_sds.ifsd_flags; 1820 idx = pidx; 1821 1822 n = count; 1823 MPASS(n > 0); 1824 MPASS(fl->ifl_credits + n <= fl->ifl_size); 1825 1826 if (pidx < fl->ifl_cidx) 1827 MPASS(pidx + n <= fl->ifl_cidx); 1828 if (pidx == fl->ifl_cidx && (fl->ifl_credits < fl->ifl_size)) 1829 MPASS(fl->ifl_gen == 0); 1830 if (pidx > fl->ifl_cidx) 1831 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1832 1833 DBG_COUNTER_INC(fl_refills); 1834 if (n > 8) 1835 DBG_COUNTER_INC(fl_refills_large); 1836 iru.iru_paddrs = fl->ifl_bus_addrs; 1837 iru.iru_vaddrs = &fl->ifl_vm_addrs[0]; 1838 iru.iru_idxs = fl->ifl_rxd_idxs; 1839 iru.iru_qsidx = fl->ifl_rxq->ifr_id; 1840 iru.iru_buf_size = fl->ifl_buf_size; 1841 iru.iru_flidx = fl->ifl_id; 1842 while (n--) { 1843 /* 1844 * We allocate an uninitialized mbuf + cluster, mbuf is 1845 * initialized after rx. 1846 * 1847 * If the cluster is still set then we know a minimum sized packet was received 1848 */ 1849 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1850 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1851 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1852 if ((cl = sd_cl[frag_idx]) == NULL) { 1853 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1854 break; 1855 #if MEMORY_LOGGING 1856 fl->ifl_cl_enqueued++; 1857 #endif 1858 } 1859 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1860 break; 1861 } 1862 #if MEMORY_LOGGING 1863 fl->ifl_m_enqueued++; 1864 #endif 1865 1866 DBG_COUNTER_INC(rx_allocs); 1867 #if defined(__i386__) || defined(__amd64__) 1868 if (!IS_DMAR(ctx)) { 1869 bus_addr = pmap_kextract((vm_offset_t)cl); 1870 } else 1871 #endif 1872 { 1873 struct rxq_refill_cb_arg cb_arg; 1874 iflib_rxq_t q; 1875 1876 cb_arg.error = 0; 1877 q = fl->ifl_rxq; 1878 MPASS(sd_map != NULL); 1879 MPASS(sd_map[frag_idx] != NULL); 1880 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1881 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1882 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 1883 BUS_DMASYNC_PREREAD); 1884 1885 if (err != 0 || cb_arg.error) { 1886 /* 1887 * !zone_pack ? 1888 */ 1889 if (fl->ifl_zone == zone_pack) 1890 uma_zfree(fl->ifl_zone, cl); 1891 m_free(m); 1892 n = 0; 1893 goto done; 1894 } 1895 bus_addr = cb_arg.seg.ds_addr; 1896 } 1897 bit_set(fl->ifl_rx_bitmap, frag_idx); 1898 sd_flags[frag_idx] |= RX_SW_DESC_INUSE; 1899 1900 MPASS(sd_m[frag_idx] == NULL); 1901 sd_cl[frag_idx] = cl; 1902 sd_m[frag_idx] = m; 1903 fl->ifl_rxd_idxs[i] = frag_idx; 1904 fl->ifl_bus_addrs[i] = bus_addr; 1905 fl->ifl_vm_addrs[i] = cl; 1906 fl->ifl_credits++; 1907 i++; 1908 MPASS(fl->ifl_credits <= fl->ifl_size); 1909 if (++idx == fl->ifl_size) { 1910 fl->ifl_gen = 1; 1911 idx = 0; 1912 } 1913 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 1914 iru.iru_pidx = pidx; 1915 iru.iru_count = i; 1916 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1917 i = 0; 1918 pidx = idx; 1919 fl->ifl_pidx = idx; 1920 } 1921 1922 } 1923 done: 1924 DBG_COUNTER_INC(rxd_flush); 1925 if (fl->ifl_pidx == 0) 1926 pidx = fl->ifl_size - 1; 1927 else 1928 pidx = fl->ifl_pidx - 1; 1929 1930 if (sd_map) 1931 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1932 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1933 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 1934 fl->ifl_fragidx = frag_idx; 1935 } 1936 1937 static __inline void 1938 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 1939 { 1940 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 1941 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 1942 #ifdef INVARIANTS 1943 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 1944 #endif 1945 1946 MPASS(fl->ifl_credits <= fl->ifl_size); 1947 MPASS(reclaimable == delta); 1948 1949 if (reclaimable > 0) 1950 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 1951 } 1952 1953 static void 1954 iflib_fl_bufs_free(iflib_fl_t fl) 1955 { 1956 iflib_dma_info_t idi = fl->ifl_ifdi; 1957 uint32_t i; 1958 1959 for (i = 0; i < fl->ifl_size; i++) { 1960 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 1961 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 1962 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 1963 1964 if (*sd_flags & RX_SW_DESC_INUSE) { 1965 if (fl->ifl_sds.ifsd_map != NULL) { 1966 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 1967 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 1968 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 1969 } 1970 if (*sd_m != NULL) { 1971 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 1972 uma_zfree(zone_mbuf, *sd_m); 1973 } 1974 if (*sd_cl != NULL) 1975 uma_zfree(fl->ifl_zone, *sd_cl); 1976 *sd_flags = 0; 1977 } else { 1978 MPASS(*sd_cl == NULL); 1979 MPASS(*sd_m == NULL); 1980 } 1981 #if MEMORY_LOGGING 1982 fl->ifl_m_dequeued++; 1983 fl->ifl_cl_dequeued++; 1984 #endif 1985 *sd_cl = NULL; 1986 *sd_m = NULL; 1987 } 1988 #ifdef INVARIANTS 1989 for (i = 0; i < fl->ifl_size; i++) { 1990 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 1991 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 1992 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 1993 } 1994 #endif 1995 /* 1996 * Reset free list values 1997 */ 1998 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 1999 bzero(idi->idi_vaddr, idi->idi_size); 2000 } 2001 2002 /********************************************************************* 2003 * 2004 * Initialize a receive ring and its buffers. 2005 * 2006 **********************************************************************/ 2007 static int 2008 iflib_fl_setup(iflib_fl_t fl) 2009 { 2010 iflib_rxq_t rxq = fl->ifl_rxq; 2011 if_ctx_t ctx = rxq->ifr_ctx; 2012 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2013 2014 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size); 2015 /* 2016 ** Free current RX buffer structs and their mbufs 2017 */ 2018 iflib_fl_bufs_free(fl); 2019 /* Now replenish the mbufs */ 2020 MPASS(fl->ifl_credits == 0); 2021 /* 2022 * XXX don't set the max_frame_size to larger 2023 * than the hardware can handle 2024 */ 2025 if (sctx->isc_max_frame_size <= 2048) 2026 fl->ifl_buf_size = MCLBYTES; 2027 #ifndef CONTIGMALLOC_WORKS 2028 else 2029 fl->ifl_buf_size = MJUMPAGESIZE; 2030 #else 2031 else if (sctx->isc_max_frame_size <= 4096) 2032 fl->ifl_buf_size = MJUMPAGESIZE; 2033 else if (sctx->isc_max_frame_size <= 9216) 2034 fl->ifl_buf_size = MJUM9BYTES; 2035 else 2036 fl->ifl_buf_size = MJUM16BYTES; 2037 #endif 2038 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2039 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2040 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2041 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2042 2043 2044 /* avoid pre-allocating zillions of clusters to an idle card 2045 * potentially speeding up attach 2046 */ 2047 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2048 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2049 if (min(128, fl->ifl_size) != fl->ifl_credits) 2050 return (ENOBUFS); 2051 /* 2052 * handle failure 2053 */ 2054 MPASS(rxq != NULL); 2055 MPASS(fl->ifl_ifdi != NULL); 2056 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2057 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2058 return (0); 2059 } 2060 2061 /********************************************************************* 2062 * 2063 * Free receive ring data structures 2064 * 2065 **********************************************************************/ 2066 static void 2067 iflib_rx_sds_free(iflib_rxq_t rxq) 2068 { 2069 iflib_fl_t fl; 2070 int i; 2071 2072 if (rxq->ifr_fl != NULL) { 2073 for (i = 0; i < rxq->ifr_nfl; i++) { 2074 fl = &rxq->ifr_fl[i]; 2075 if (fl->ifl_desc_tag != NULL) { 2076 bus_dma_tag_destroy(fl->ifl_desc_tag); 2077 fl->ifl_desc_tag = NULL; 2078 } 2079 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2080 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2081 /* XXX destroy maps first */ 2082 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2083 fl->ifl_sds.ifsd_m = NULL; 2084 fl->ifl_sds.ifsd_cl = NULL; 2085 fl->ifl_sds.ifsd_map = NULL; 2086 } 2087 free(rxq->ifr_fl, M_IFLIB); 2088 rxq->ifr_fl = NULL; 2089 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2090 } 2091 } 2092 2093 /* 2094 * MI independent logic 2095 * 2096 */ 2097 static void 2098 iflib_timer(void *arg) 2099 { 2100 iflib_txq_t txq = arg; 2101 if_ctx_t ctx = txq->ift_ctx; 2102 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2103 2104 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2105 return; 2106 /* 2107 ** Check on the state of the TX queue(s), this 2108 ** can be done without the lock because its RO 2109 ** and the HUNG state will be static if set. 2110 */ 2111 IFDI_TIMER(ctx, txq->ift_id); 2112 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2113 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2114 (sctx->isc_pause_frames == 0))) 2115 goto hung; 2116 2117 if (ifmp_ring_is_stalled(txq->ift_br)) 2118 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2119 txq->ift_cleaned_prev = txq->ift_cleaned; 2120 /* handle any laggards */ 2121 if (txq->ift_db_pending) 2122 GROUPTASK_ENQUEUE(&txq->ift_task); 2123 2124 sctx->isc_pause_frames = 0; 2125 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2126 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 2127 return; 2128 hung: 2129 CTX_LOCK(ctx); 2130 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2131 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2132 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2133 2134 IFDI_WATCHDOG_RESET(ctx); 2135 ctx->ifc_watchdog_events++; 2136 2137 ctx->ifc_flags |= IFC_DO_RESET; 2138 iflib_admin_intr_deferred(ctx); 2139 CTX_UNLOCK(ctx); 2140 } 2141 2142 static void 2143 iflib_init_locked(if_ctx_t ctx) 2144 { 2145 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2146 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2147 if_t ifp = ctx->ifc_ifp; 2148 iflib_fl_t fl; 2149 iflib_txq_t txq; 2150 iflib_rxq_t rxq; 2151 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2152 2153 2154 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2155 IFDI_INTR_DISABLE(ctx); 2156 2157 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2158 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2159 /* Set hardware offload abilities */ 2160 if_clearhwassist(ifp); 2161 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2162 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2163 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2164 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2165 if (if_getcapenable(ifp) & IFCAP_TSO4) 2166 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2167 if (if_getcapenable(ifp) & IFCAP_TSO6) 2168 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2169 2170 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2171 CALLOUT_LOCK(txq); 2172 callout_stop(&txq->ift_timer); 2173 CALLOUT_UNLOCK(txq); 2174 iflib_netmap_txq_init(ctx, txq); 2175 } 2176 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2177 MPASS(rxq->ifr_id == i); 2178 iflib_netmap_rxq_init(ctx, rxq); 2179 } 2180 #ifdef INVARIANTS 2181 i = if_getdrvflags(ifp); 2182 #endif 2183 IFDI_INIT(ctx); 2184 MPASS(if_getdrvflags(ifp) == i); 2185 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2186 /* XXX this should really be done on a per-queue basis */ 2187 if (if_getcapenable(ifp) & IFCAP_NETMAP) 2188 continue; 2189 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2190 if (iflib_fl_setup(fl)) { 2191 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2192 goto done; 2193 } 2194 } 2195 } 2196 done: 2197 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2198 IFDI_INTR_ENABLE(ctx); 2199 txq = ctx->ifc_txqs; 2200 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2201 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2202 txq->ift_timer.c_cpu); 2203 } 2204 2205 static int 2206 iflib_media_change(if_t ifp) 2207 { 2208 if_ctx_t ctx = if_getsoftc(ifp); 2209 int err; 2210 2211 CTX_LOCK(ctx); 2212 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2213 iflib_init_locked(ctx); 2214 CTX_UNLOCK(ctx); 2215 return (err); 2216 } 2217 2218 static void 2219 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2220 { 2221 if_ctx_t ctx = if_getsoftc(ifp); 2222 2223 CTX_LOCK(ctx); 2224 IFDI_UPDATE_ADMIN_STATUS(ctx); 2225 IFDI_MEDIA_STATUS(ctx, ifmr); 2226 CTX_UNLOCK(ctx); 2227 } 2228 2229 static void 2230 iflib_stop(if_ctx_t ctx) 2231 { 2232 iflib_txq_t txq = ctx->ifc_txqs; 2233 iflib_rxq_t rxq = ctx->ifc_rxqs; 2234 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2235 iflib_dma_info_t di; 2236 iflib_fl_t fl; 2237 int i, j; 2238 2239 /* Tell the stack that the interface is no longer active */ 2240 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2241 2242 IFDI_INTR_DISABLE(ctx); 2243 DELAY(1000); 2244 IFDI_STOP(ctx); 2245 DELAY(1000); 2246 2247 iflib_debug_reset(); 2248 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2249 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2250 /* make sure all transmitters have completed before proceeding XXX */ 2251 2252 /* clean any enqueued buffers */ 2253 iflib_ifmp_purge(txq); 2254 /* Free any existing tx buffers. */ 2255 for (j = 0; j < txq->ift_size; j++) { 2256 iflib_txsd_free(ctx, txq, j); 2257 } 2258 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2259 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2260 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2261 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2262 txq->ift_pullups = 0; 2263 ifmp_ring_reset_stats(txq->ift_br); 2264 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2265 bzero((void *)di->idi_vaddr, di->idi_size); 2266 } 2267 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2268 /* make sure all transmitters have completed before proceeding XXX */ 2269 2270 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++) 2271 bzero((void *)di->idi_vaddr, di->idi_size); 2272 /* also resets the free lists pidx/cidx */ 2273 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2274 iflib_fl_bufs_free(fl); 2275 } 2276 } 2277 2278 static inline caddr_t 2279 calc_next_rxd(iflib_fl_t fl, int cidx) 2280 { 2281 qidx_t size; 2282 int nrxd; 2283 caddr_t start, end, cur, next; 2284 2285 nrxd = fl->ifl_size; 2286 size = fl->ifl_rxd_size; 2287 start = fl->ifl_ifdi->idi_vaddr; 2288 2289 if (__predict_false(size == 0)) 2290 return (start); 2291 cur = start + size*cidx; 2292 end = start + size*nrxd; 2293 next = CACHE_PTR_NEXT(cur); 2294 return (next < end ? next : start); 2295 } 2296 2297 static inline void 2298 prefetch_pkts(iflib_fl_t fl, int cidx) 2299 { 2300 int nextptr; 2301 int nrxd = fl->ifl_size; 2302 caddr_t next_rxd; 2303 2304 2305 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2306 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2307 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2308 next_rxd = calc_next_rxd(fl, cidx); 2309 prefetch(next_rxd); 2310 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2311 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2312 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2313 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2314 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2315 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2316 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2317 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2318 } 2319 2320 static void 2321 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2322 { 2323 int flid, cidx; 2324 bus_dmamap_t map; 2325 iflib_fl_t fl; 2326 iflib_dma_info_t di; 2327 int next; 2328 2329 map = NULL; 2330 flid = irf->irf_flid; 2331 cidx = irf->irf_idx; 2332 fl = &rxq->ifr_fl[flid]; 2333 sd->ifsd_fl = fl; 2334 sd->ifsd_cidx = cidx; 2335 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2336 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2337 fl->ifl_credits--; 2338 #if MEMORY_LOGGING 2339 fl->ifl_m_dequeued++; 2340 #endif 2341 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2342 prefetch_pkts(fl, cidx); 2343 if (fl->ifl_sds.ifsd_map != NULL) { 2344 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2345 prefetch(&fl->ifl_sds.ifsd_map[next]); 2346 map = fl->ifl_sds.ifsd_map[cidx]; 2347 di = fl->ifl_ifdi; 2348 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2349 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2350 bus_dmamap_sync(di->idi_tag, di->idi_map, 2351 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2352 2353 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2354 MPASS(fl->ifl_cidx == cidx); 2355 if (unload) 2356 bus_dmamap_unload(fl->ifl_desc_tag, map); 2357 } 2358 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2359 if (__predict_false(fl->ifl_cidx == 0)) 2360 fl->ifl_gen = 0; 2361 if (map != NULL) 2362 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2363 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2364 bit_clear(fl->ifl_rx_bitmap, cidx); 2365 } 2366 2367 static struct mbuf * 2368 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2369 { 2370 int i, padlen , flags; 2371 struct mbuf *m, *mh, *mt; 2372 caddr_t cl; 2373 2374 i = 0; 2375 mh = NULL; 2376 do { 2377 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2378 2379 MPASS(*sd->ifsd_cl != NULL); 2380 MPASS(*sd->ifsd_m != NULL); 2381 2382 /* Don't include zero-length frags */ 2383 if (ri->iri_frags[i].irf_len == 0) { 2384 /* XXX we can save the cluster here, but not the mbuf */ 2385 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2386 m_free(*sd->ifsd_m); 2387 *sd->ifsd_m = NULL; 2388 continue; 2389 } 2390 m = *sd->ifsd_m; 2391 *sd->ifsd_m = NULL; 2392 if (mh == NULL) { 2393 flags = M_PKTHDR|M_EXT; 2394 mh = mt = m; 2395 padlen = ri->iri_pad; 2396 } else { 2397 flags = M_EXT; 2398 mt->m_next = m; 2399 mt = m; 2400 /* assuming padding is only on the first fragment */ 2401 padlen = 0; 2402 } 2403 cl = *sd->ifsd_cl; 2404 *sd->ifsd_cl = NULL; 2405 2406 /* Can these two be made one ? */ 2407 m_init(m, M_NOWAIT, MT_DATA, flags); 2408 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2409 /* 2410 * These must follow m_init and m_cljset 2411 */ 2412 m->m_data += padlen; 2413 ri->iri_len -= padlen; 2414 m->m_len = ri->iri_frags[i].irf_len; 2415 } while (++i < ri->iri_nfrags); 2416 2417 return (mh); 2418 } 2419 2420 /* 2421 * Process one software descriptor 2422 */ 2423 static struct mbuf * 2424 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2425 { 2426 struct if_rxsd sd; 2427 struct mbuf *m; 2428 2429 /* should I merge this back in now that the two paths are basically duplicated? */ 2430 if (ri->iri_nfrags == 1 && 2431 ri->iri_frags[0].irf_len <= IFLIB_RX_COPY_THRESH) { 2432 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2433 m = *sd.ifsd_m; 2434 *sd.ifsd_m = NULL; 2435 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2436 #ifndef __NO_STRICT_ALIGNMENT 2437 if (!IP_ALIGNED(m)) 2438 m->m_data += 2; 2439 #endif 2440 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2441 m->m_len = ri->iri_frags[0].irf_len; 2442 } else { 2443 m = assemble_segments(rxq, ri, &sd); 2444 } 2445 m->m_pkthdr.len = ri->iri_len; 2446 m->m_pkthdr.rcvif = ri->iri_ifp; 2447 m->m_flags |= ri->iri_flags; 2448 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2449 m->m_pkthdr.flowid = ri->iri_flowid; 2450 M_HASHTYPE_SET(m, ri->iri_rsstype); 2451 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2452 m->m_pkthdr.csum_data = ri->iri_csum_data; 2453 return (m); 2454 } 2455 2456 static bool 2457 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2458 { 2459 if_ctx_t ctx = rxq->ifr_ctx; 2460 if_shared_ctx_t sctx = ctx->ifc_sctx; 2461 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2462 int avail, i; 2463 qidx_t *cidxp; 2464 struct if_rxd_info ri; 2465 int err, budget_left, rx_bytes, rx_pkts; 2466 iflib_fl_t fl; 2467 struct ifnet *ifp; 2468 int lro_enabled; 2469 2470 /* 2471 * XXX early demux data packets so that if_input processing only handles 2472 * acks in interrupt context 2473 */ 2474 struct mbuf *m, *mh, *mt; 2475 2476 ifp = ctx->ifc_ifp; 2477 #ifdef DEV_NETMAP 2478 if (ifp->if_capenable & IFCAP_NETMAP) { 2479 u_int work = 0; 2480 if (netmap_rx_irq(ifp, rxq->ifr_id, &work)) 2481 return (FALSE); 2482 } 2483 #endif 2484 2485 mh = mt = NULL; 2486 MPASS(budget > 0); 2487 rx_pkts = rx_bytes = 0; 2488 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2489 cidxp = &rxq->ifr_cq_cidx; 2490 else 2491 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2492 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2493 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2494 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2495 DBG_COUNTER_INC(rx_unavail); 2496 return (false); 2497 } 2498 2499 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2500 if (__predict_false(!CTX_ACTIVE(ctx))) { 2501 DBG_COUNTER_INC(rx_ctx_inactive); 2502 break; 2503 } 2504 /* 2505 * Reset client set fields to their default values 2506 */ 2507 rxd_info_zero(&ri); 2508 ri.iri_qsidx = rxq->ifr_id; 2509 ri.iri_cidx = *cidxp; 2510 ri.iri_ifp = ifp; 2511 ri.iri_frags = rxq->ifr_frags; 2512 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2513 2514 if (err) 2515 goto err; 2516 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2517 *cidxp = ri.iri_cidx; 2518 /* Update our consumer index */ 2519 /* XXX NB: shurd - check if this is still safe */ 2520 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2521 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2522 rxq->ifr_cq_gen = 0; 2523 } 2524 /* was this only a completion queue message? */ 2525 if (__predict_false(ri.iri_nfrags == 0)) 2526 continue; 2527 } 2528 MPASS(ri.iri_nfrags != 0); 2529 MPASS(ri.iri_len != 0); 2530 2531 /* will advance the cidx on the corresponding free lists */ 2532 m = iflib_rxd_pkt_get(rxq, &ri); 2533 if (avail == 0 && budget_left) 2534 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2535 2536 if (__predict_false(m == NULL)) { 2537 DBG_COUNTER_INC(rx_mbuf_null); 2538 continue; 2539 } 2540 /* imm_pkt: -- cxgb */ 2541 if (mh == NULL) 2542 mh = mt = m; 2543 else { 2544 mt->m_nextpkt = m; 2545 mt = m; 2546 } 2547 } 2548 /* make sure that we can refill faster than drain */ 2549 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2550 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2551 2552 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2553 while (mh != NULL) { 2554 m = mh; 2555 mh = mh->m_nextpkt; 2556 m->m_nextpkt = NULL; 2557 #ifndef __NO_STRICT_ALIGNMENT 2558 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2559 continue; 2560 #endif 2561 rx_bytes += m->m_pkthdr.len; 2562 rx_pkts++; 2563 #if defined(INET6) || defined(INET) 2564 if (lro_enabled && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2565 continue; 2566 #endif 2567 DBG_COUNTER_INC(rx_if_input); 2568 ifp->if_input(ifp, m); 2569 } 2570 2571 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2572 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2573 2574 /* 2575 * Flush any outstanding LRO work 2576 */ 2577 #if defined(INET6) || defined(INET) 2578 tcp_lro_flush_all(&rxq->ifr_lc); 2579 #endif 2580 if (avail) 2581 return true; 2582 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2583 err: 2584 CTX_LOCK(ctx); 2585 ctx->ifc_flags |= IFC_DO_RESET; 2586 iflib_admin_intr_deferred(ctx); 2587 CTX_UNLOCK(ctx); 2588 return (false); 2589 } 2590 2591 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2592 static inline qidx_t 2593 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2594 { 2595 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2596 qidx_t minthresh = txq->ift_size / 8; 2597 if (in_use > 4*minthresh) 2598 return (notify_count); 2599 if (in_use > 2*minthresh) 2600 return (notify_count >> 1); 2601 if (in_use > minthresh) 2602 return (notify_count >> 3); 2603 return (0); 2604 } 2605 2606 static inline qidx_t 2607 txq_max_rs_deferred(iflib_txq_t txq) 2608 { 2609 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2610 qidx_t minthresh = txq->ift_size / 8; 2611 if (txq->ift_in_use > 4*minthresh) 2612 return (notify_count); 2613 if (txq->ift_in_use > 2*minthresh) 2614 return (notify_count >> 1); 2615 if (txq->ift_in_use > minthresh) 2616 return (notify_count >> 2); 2617 return (2); 2618 } 2619 2620 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2621 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2622 2623 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2624 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2625 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2626 2627 /* forward compatibility for cxgb */ 2628 #define FIRST_QSET(ctx) 0 2629 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2630 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2631 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2632 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2633 2634 /* XXX we should be setting this to something other than zero */ 2635 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2636 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2637 2638 static inline bool 2639 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2640 { 2641 qidx_t dbval, max; 2642 bool rang; 2643 2644 rang = false; 2645 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2646 if (ring || txq->ift_db_pending >= max) { 2647 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2648 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2649 txq->ift_db_pending = txq->ift_npending = 0; 2650 rang = true; 2651 } 2652 return (rang); 2653 } 2654 2655 #ifdef PKT_DEBUG 2656 static void 2657 print_pkt(if_pkt_info_t pi) 2658 { 2659 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2660 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2661 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2662 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2663 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2664 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2665 } 2666 #endif 2667 2668 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2669 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2670 2671 static int 2672 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2673 { 2674 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2675 struct ether_vlan_header *eh; 2676 struct mbuf *m, *n; 2677 2678 n = m = *mp; 2679 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2680 M_WRITABLE(m) == 0) { 2681 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2682 return (ENOMEM); 2683 } else { 2684 m_freem(*mp); 2685 n = *mp = m; 2686 } 2687 } 2688 2689 /* 2690 * Determine where frame payload starts. 2691 * Jump over vlan headers if already present, 2692 * helpful for QinQ too. 2693 */ 2694 if (__predict_false(m->m_len < sizeof(*eh))) { 2695 txq->ift_pullups++; 2696 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2697 return (ENOMEM); 2698 } 2699 eh = mtod(m, struct ether_vlan_header *); 2700 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2701 pi->ipi_etype = ntohs(eh->evl_proto); 2702 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2703 } else { 2704 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2705 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2706 } 2707 2708 switch (pi->ipi_etype) { 2709 #ifdef INET 2710 case ETHERTYPE_IP: 2711 { 2712 struct ip *ip = NULL; 2713 struct tcphdr *th = NULL; 2714 int minthlen; 2715 2716 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2717 if (__predict_false(m->m_len < minthlen)) { 2718 /* 2719 * if this code bloat is causing too much of a hit 2720 * move it to a separate function and mark it noinline 2721 */ 2722 if (m->m_len == pi->ipi_ehdrlen) { 2723 n = m->m_next; 2724 MPASS(n); 2725 if (n->m_len >= sizeof(*ip)) { 2726 ip = (struct ip *)n->m_data; 2727 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2728 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2729 } else { 2730 txq->ift_pullups++; 2731 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2732 return (ENOMEM); 2733 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2734 } 2735 } else { 2736 txq->ift_pullups++; 2737 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2738 return (ENOMEM); 2739 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2740 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2741 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2742 } 2743 } else { 2744 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2745 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2746 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2747 } 2748 pi->ipi_ip_hlen = ip->ip_hl << 2; 2749 pi->ipi_ipproto = ip->ip_p; 2750 pi->ipi_flags |= IPI_TX_IPV4; 2751 2752 if (pi->ipi_csum_flags & CSUM_IP) 2753 ip->ip_sum = 0; 2754 2755 if (pi->ipi_ipproto == IPPROTO_TCP) { 2756 if (__predict_false(th == NULL)) { 2757 txq->ift_pullups++; 2758 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2759 return (ENOMEM); 2760 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2761 } 2762 pi->ipi_tcp_hflags = th->th_flags; 2763 pi->ipi_tcp_hlen = th->th_off << 2; 2764 pi->ipi_tcp_seq = th->th_seq; 2765 } 2766 if (IS_TSO4(pi)) { 2767 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2768 return (ENXIO); 2769 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2770 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2771 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2772 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2773 ip->ip_sum = 0; 2774 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2775 } 2776 } 2777 break; 2778 } 2779 #endif 2780 #ifdef INET6 2781 case ETHERTYPE_IPV6: 2782 { 2783 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2784 struct tcphdr *th; 2785 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2786 2787 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2788 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2789 return (ENOMEM); 2790 } 2791 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2792 2793 /* XXX-BZ this will go badly in case of ext hdrs. */ 2794 pi->ipi_ipproto = ip6->ip6_nxt; 2795 pi->ipi_flags |= IPI_TX_IPV6; 2796 2797 if (pi->ipi_ipproto == IPPROTO_TCP) { 2798 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2799 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2800 return (ENOMEM); 2801 } 2802 pi->ipi_tcp_hflags = th->th_flags; 2803 pi->ipi_tcp_hlen = th->th_off << 2; 2804 } 2805 if (IS_TSO6(pi)) { 2806 2807 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2808 return (ENXIO); 2809 /* 2810 * The corresponding flag is set by the stack in the IPv4 2811 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 2812 * So, set it here because the rest of the flow requires it. 2813 */ 2814 pi->ipi_csum_flags |= CSUM_TCP_IPV6; 2815 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2816 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2817 } 2818 break; 2819 } 2820 #endif 2821 default: 2822 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2823 pi->ipi_ip_hlen = 0; 2824 break; 2825 } 2826 *mp = m; 2827 2828 return (0); 2829 } 2830 2831 static __noinline struct mbuf * 2832 collapse_pkthdr(struct mbuf *m0) 2833 { 2834 struct mbuf *m, *m_next, *tmp; 2835 2836 m = m0; 2837 m_next = m->m_next; 2838 while (m_next != NULL && m_next->m_len == 0) { 2839 m = m_next; 2840 m->m_next = NULL; 2841 m_free(m); 2842 m_next = m_next->m_next; 2843 } 2844 m = m0; 2845 m->m_next = m_next; 2846 if ((m_next->m_flags & M_EXT) == 0) { 2847 m = m_defrag(m, M_NOWAIT); 2848 } else { 2849 tmp = m_next->m_next; 2850 memcpy(m_next, m, MPKTHSIZE); 2851 m = m_next; 2852 m->m_next = tmp; 2853 } 2854 return (m); 2855 } 2856 2857 /* 2858 * If dodgy hardware rejects the scatter gather chain we've handed it 2859 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 2860 * m_defrag'd mbufs 2861 */ 2862 static __noinline struct mbuf * 2863 iflib_remove_mbuf(iflib_txq_t txq) 2864 { 2865 int ntxd, i, pidx; 2866 struct mbuf *m, *mh, **ifsd_m; 2867 2868 pidx = txq->ift_pidx; 2869 ifsd_m = txq->ift_sds.ifsd_m; 2870 ntxd = txq->ift_size; 2871 mh = m = ifsd_m[pidx]; 2872 ifsd_m[pidx] = NULL; 2873 #if MEMORY_LOGGING 2874 txq->ift_dequeued++; 2875 #endif 2876 i = 1; 2877 2878 while (m) { 2879 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 2880 #if MEMORY_LOGGING 2881 txq->ift_dequeued++; 2882 #endif 2883 m = m->m_next; 2884 i++; 2885 } 2886 return (mh); 2887 } 2888 2889 static int 2890 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 2891 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 2892 int max_segs, int flags) 2893 { 2894 if_ctx_t ctx; 2895 if_shared_ctx_t sctx; 2896 if_softc_ctx_t scctx; 2897 int i, next, pidx, err, ntxd, count; 2898 struct mbuf *m, *tmp, **ifsd_m; 2899 2900 m = *m0; 2901 2902 /* 2903 * Please don't ever do this 2904 */ 2905 if (__predict_false(m->m_len == 0)) 2906 *m0 = m = collapse_pkthdr(m); 2907 2908 ctx = txq->ift_ctx; 2909 sctx = ctx->ifc_sctx; 2910 scctx = &ctx->ifc_softc_ctx; 2911 ifsd_m = txq->ift_sds.ifsd_m; 2912 ntxd = txq->ift_size; 2913 pidx = txq->ift_pidx; 2914 if (map != NULL) { 2915 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 2916 2917 err = bus_dmamap_load_mbuf_sg(tag, map, 2918 *m0, segs, nsegs, BUS_DMA_NOWAIT); 2919 if (err) 2920 return (err); 2921 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 2922 count = 0; 2923 m = *m0; 2924 do { 2925 if (__predict_false(m->m_len <= 0)) { 2926 tmp = m; 2927 m = m->m_next; 2928 tmp->m_next = NULL; 2929 m_free(tmp); 2930 continue; 2931 } 2932 m = m->m_next; 2933 count++; 2934 } while (m != NULL); 2935 if (count > *nsegs) { 2936 ifsd_m[pidx] = *m0; 2937 ifsd_m[pidx]->m_flags |= M_TOOBIG; 2938 return (0); 2939 } 2940 m = *m0; 2941 count = 0; 2942 do { 2943 next = (pidx + count) & (ntxd-1); 2944 MPASS(ifsd_m[next] == NULL); 2945 ifsd_m[next] = m; 2946 count++; 2947 tmp = m; 2948 m = m->m_next; 2949 } while (m != NULL); 2950 } else { 2951 int buflen, sgsize, maxsegsz, max_sgsize; 2952 vm_offset_t vaddr; 2953 vm_paddr_t curaddr; 2954 2955 count = i = 0; 2956 m = *m0; 2957 if (m->m_pkthdr.csum_flags & CSUM_TSO) 2958 maxsegsz = scctx->isc_tx_tso_segsize_max; 2959 else 2960 maxsegsz = sctx->isc_tx_maxsegsize; 2961 2962 do { 2963 if (__predict_false(m->m_len <= 0)) { 2964 tmp = m; 2965 m = m->m_next; 2966 tmp->m_next = NULL; 2967 m_free(tmp); 2968 continue; 2969 } 2970 buflen = m->m_len; 2971 vaddr = (vm_offset_t)m->m_data; 2972 /* 2973 * see if we can't be smarter about physically 2974 * contiguous mappings 2975 */ 2976 next = (pidx + count) & (ntxd-1); 2977 MPASS(ifsd_m[next] == NULL); 2978 #if MEMORY_LOGGING 2979 txq->ift_enqueued++; 2980 #endif 2981 ifsd_m[next] = m; 2982 while (buflen > 0) { 2983 if (i >= max_segs) 2984 goto err; 2985 max_sgsize = MIN(buflen, maxsegsz); 2986 curaddr = pmap_kextract(vaddr); 2987 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 2988 sgsize = MIN(sgsize, max_sgsize); 2989 segs[i].ds_addr = curaddr; 2990 segs[i].ds_len = sgsize; 2991 vaddr += sgsize; 2992 buflen -= sgsize; 2993 i++; 2994 } 2995 count++; 2996 tmp = m; 2997 m = m->m_next; 2998 } while (m != NULL); 2999 *nsegs = i; 3000 } 3001 return (0); 3002 err: 3003 *m0 = iflib_remove_mbuf(txq); 3004 return (EFBIG); 3005 } 3006 3007 static inline caddr_t 3008 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3009 { 3010 qidx_t size; 3011 int ntxd; 3012 caddr_t start, end, cur, next; 3013 3014 ntxd = txq->ift_size; 3015 size = txq->ift_txd_size[qid]; 3016 start = txq->ift_ifdi[qid].idi_vaddr; 3017 3018 if (__predict_false(size == 0)) 3019 return (start); 3020 cur = start + size*cidx; 3021 end = start + size*ntxd; 3022 next = CACHE_PTR_NEXT(cur); 3023 return (next < end ? next : start); 3024 } 3025 3026 static int 3027 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3028 { 3029 if_ctx_t ctx; 3030 if_shared_ctx_t sctx; 3031 if_softc_ctx_t scctx; 3032 bus_dma_segment_t *segs; 3033 struct mbuf *m_head; 3034 void *next_txd; 3035 bus_dmamap_t map; 3036 struct if_pkt_info pi; 3037 int remap = 0; 3038 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3039 bus_dma_tag_t desc_tag; 3040 3041 segs = txq->ift_segs; 3042 ctx = txq->ift_ctx; 3043 sctx = ctx->ifc_sctx; 3044 scctx = &ctx->ifc_softc_ctx; 3045 segs = txq->ift_segs; 3046 ntxd = txq->ift_size; 3047 m_head = *m_headp; 3048 map = NULL; 3049 3050 /* 3051 * If we're doing TSO the next descriptor to clean may be quite far ahead 3052 */ 3053 cidx = txq->ift_cidx; 3054 pidx = txq->ift_pidx; 3055 if (ctx->ifc_flags & IFC_PREFETCH) { 3056 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3057 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3058 next_txd = calc_next_txd(txq, cidx, 0); 3059 prefetch(next_txd); 3060 } 3061 3062 /* prefetch the next cache line of mbuf pointers and flags */ 3063 prefetch(&txq->ift_sds.ifsd_m[next]); 3064 if (txq->ift_sds.ifsd_map != NULL) { 3065 prefetch(&txq->ift_sds.ifsd_map[next]); 3066 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3067 prefetch(&txq->ift_sds.ifsd_flags[next]); 3068 } 3069 } else if (txq->ift_sds.ifsd_map != NULL) 3070 map = txq->ift_sds.ifsd_map[pidx]; 3071 3072 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3073 desc_tag = txq->ift_tso_desc_tag; 3074 max_segs = scctx->isc_tx_tso_segments_max; 3075 } else { 3076 desc_tag = txq->ift_desc_tag; 3077 max_segs = scctx->isc_tx_nsegments; 3078 } 3079 m_head = *m_headp; 3080 3081 pkt_info_zero(&pi); 3082 pi.ipi_len = m_head->m_pkthdr.len; 3083 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3084 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3085 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3086 pi.ipi_pidx = pidx; 3087 pi.ipi_qsidx = txq->ift_id; 3088 3089 /* deliberate bitwise OR to make one condition */ 3090 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3091 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3092 return (err); 3093 m_head = *m_headp; 3094 } 3095 3096 retry: 3097 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3098 defrag: 3099 if (__predict_false(err)) { 3100 switch (err) { 3101 case EFBIG: 3102 /* try collapse once and defrag once */ 3103 if (remap == 0) 3104 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3105 if (remap == 1) 3106 m_head = m_defrag(*m_headp, M_NOWAIT); 3107 remap++; 3108 if (__predict_false(m_head == NULL)) 3109 goto defrag_failed; 3110 txq->ift_mbuf_defrag++; 3111 *m_headp = m_head; 3112 goto retry; 3113 break; 3114 case ENOMEM: 3115 txq->ift_no_tx_dma_setup++; 3116 break; 3117 default: 3118 txq->ift_no_tx_dma_setup++; 3119 m_freem(*m_headp); 3120 DBG_COUNTER_INC(tx_frees); 3121 *m_headp = NULL; 3122 break; 3123 } 3124 txq->ift_map_failed++; 3125 DBG_COUNTER_INC(encap_load_mbuf_fail); 3126 return (err); 3127 } 3128 3129 /* 3130 * XXX assumes a 1 to 1 relationship between segments and 3131 * descriptors - this does not hold true on all drivers, e.g. 3132 * cxgb 3133 */ 3134 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3135 txq->ift_no_desc_avail++; 3136 if (map != NULL) 3137 bus_dmamap_unload(desc_tag, map); 3138 DBG_COUNTER_INC(encap_txq_avail_fail); 3139 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3140 GROUPTASK_ENQUEUE(&txq->ift_task); 3141 return (ENOBUFS); 3142 } 3143 /* 3144 * On Intel cards we can greatly reduce the number of TX interrupts 3145 * we see by only setting report status on every Nth descriptor. 3146 * However, this also means that the driver will need to keep track 3147 * of the descriptors that RS was set on to check them for the DD bit. 3148 */ 3149 txq->ift_rs_pending += nsegs + 1; 3150 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3151 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) { 3152 pi.ipi_flags |= IPI_TX_INTR; 3153 txq->ift_rs_pending = 0; 3154 } 3155 3156 pi.ipi_segs = segs; 3157 pi.ipi_nsegs = nsegs; 3158 3159 MPASS(pidx >= 0 && pidx < txq->ift_size); 3160 #ifdef PKT_DEBUG 3161 print_pkt(&pi); 3162 #endif 3163 if (map != NULL) 3164 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3165 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3166 if (map != NULL) 3167 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3168 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3169 DBG_COUNTER_INC(tx_encap); 3170 MPASS(pi.ipi_new_pidx < txq->ift_size); 3171 3172 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3173 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3174 ndesc += txq->ift_size; 3175 txq->ift_gen = 1; 3176 } 3177 /* 3178 * drivers can need as many as 3179 * two sentinels 3180 */ 3181 MPASS(ndesc <= pi.ipi_nsegs + 2); 3182 MPASS(pi.ipi_new_pidx != pidx); 3183 MPASS(ndesc > 0); 3184 txq->ift_in_use += ndesc; 3185 3186 /* 3187 * We update the last software descriptor again here because there may 3188 * be a sentinel and/or there may be more mbufs than segments 3189 */ 3190 txq->ift_pidx = pi.ipi_new_pidx; 3191 txq->ift_npending += pi.ipi_ndescs; 3192 } else if (__predict_false(err == EFBIG && remap < 2)) { 3193 *m_headp = m_head = iflib_remove_mbuf(txq); 3194 remap = 1; 3195 txq->ift_txd_encap_efbig++; 3196 goto defrag; 3197 } else 3198 DBG_COUNTER_INC(encap_txd_encap_fail); 3199 return (err); 3200 3201 defrag_failed: 3202 txq->ift_mbuf_defrag_failed++; 3203 txq->ift_map_failed++; 3204 m_freem(*m_headp); 3205 DBG_COUNTER_INC(tx_frees); 3206 *m_headp = NULL; 3207 return (ENOMEM); 3208 } 3209 3210 static void 3211 iflib_tx_desc_free(iflib_txq_t txq, int n) 3212 { 3213 int hasmap; 3214 uint32_t qsize, cidx, mask, gen; 3215 struct mbuf *m, **ifsd_m; 3216 uint8_t *ifsd_flags; 3217 bus_dmamap_t *ifsd_map; 3218 bool do_prefetch; 3219 3220 cidx = txq->ift_cidx; 3221 gen = txq->ift_gen; 3222 qsize = txq->ift_size; 3223 mask = qsize-1; 3224 hasmap = txq->ift_sds.ifsd_map != NULL; 3225 ifsd_flags = txq->ift_sds.ifsd_flags; 3226 ifsd_m = txq->ift_sds.ifsd_m; 3227 ifsd_map = txq->ift_sds.ifsd_map; 3228 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3229 3230 while (n--) { 3231 if (do_prefetch) { 3232 prefetch(ifsd_m[(cidx + 3) & mask]); 3233 prefetch(ifsd_m[(cidx + 4) & mask]); 3234 } 3235 if (ifsd_m[cidx] != NULL) { 3236 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3237 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3238 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3239 /* 3240 * does it matter if it's not the TSO tag? If so we'll 3241 * have to add the type to flags 3242 */ 3243 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3244 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3245 } 3246 if ((m = ifsd_m[cidx]) != NULL) { 3247 /* XXX we don't support any drivers that batch packets yet */ 3248 MPASS(m->m_nextpkt == NULL); 3249 /* if the number of clusters exceeds the number of segments 3250 * there won't be space on the ring to save a pointer to each 3251 * cluster so we simply free the list here 3252 */ 3253 if (m->m_flags & M_TOOBIG) { 3254 m_freem(m); 3255 } else { 3256 m_free(m); 3257 } 3258 ifsd_m[cidx] = NULL; 3259 #if MEMORY_LOGGING 3260 txq->ift_dequeued++; 3261 #endif 3262 DBG_COUNTER_INC(tx_frees); 3263 } 3264 } 3265 if (__predict_false(++cidx == qsize)) { 3266 cidx = 0; 3267 gen = 0; 3268 } 3269 } 3270 txq->ift_cidx = cidx; 3271 txq->ift_gen = gen; 3272 } 3273 3274 static __inline int 3275 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3276 { 3277 int reclaim; 3278 if_ctx_t ctx = txq->ift_ctx; 3279 3280 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3281 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3282 3283 /* 3284 * Need a rate-limiting check so that this isn't called every time 3285 */ 3286 iflib_tx_credits_update(ctx, txq); 3287 reclaim = DESC_RECLAIMABLE(txq); 3288 3289 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3290 #ifdef INVARIANTS 3291 if (iflib_verbose_debug) { 3292 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3293 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3294 reclaim, thresh); 3295 3296 } 3297 #endif 3298 return (0); 3299 } 3300 iflib_tx_desc_free(txq, reclaim); 3301 txq->ift_cleaned += reclaim; 3302 txq->ift_in_use -= reclaim; 3303 3304 return (reclaim); 3305 } 3306 3307 static struct mbuf ** 3308 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3309 { 3310 int next, size; 3311 struct mbuf **items; 3312 3313 size = r->size; 3314 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3315 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3316 3317 prefetch(items[(cidx + offset) & (size-1)]); 3318 if (remaining > 1) { 3319 prefetch(&items[next]); 3320 prefetch(items[(cidx + offset + 1) & (size-1)]); 3321 prefetch(items[(cidx + offset + 2) & (size-1)]); 3322 prefetch(items[(cidx + offset + 3) & (size-1)]); 3323 } 3324 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3325 } 3326 3327 static void 3328 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3329 { 3330 3331 ifmp_ring_check_drainage(txq->ift_br, budget); 3332 } 3333 3334 static uint32_t 3335 iflib_txq_can_drain(struct ifmp_ring *r) 3336 { 3337 iflib_txq_t txq = r->cookie; 3338 if_ctx_t ctx = txq->ift_ctx; 3339 3340 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3341 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3342 } 3343 3344 static uint32_t 3345 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3346 { 3347 iflib_txq_t txq = r->cookie; 3348 if_ctx_t ctx = txq->ift_ctx; 3349 struct ifnet *ifp = ctx->ifc_ifp; 3350 struct mbuf **mp, *m; 3351 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3352 int reclaimed, err, in_use_prev, desc_used; 3353 bool do_prefetch, ring, rang; 3354 3355 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3356 !LINK_ACTIVE(ctx))) { 3357 DBG_COUNTER_INC(txq_drain_notready); 3358 return (0); 3359 } 3360 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3361 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3362 avail = IDXDIFF(pidx, cidx, r->size); 3363 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3364 DBG_COUNTER_INC(txq_drain_flushing); 3365 for (i = 0; i < avail; i++) { 3366 m_free(r->items[(cidx + i) & (r->size-1)]); 3367 r->items[(cidx + i) & (r->size-1)] = NULL; 3368 } 3369 return (avail); 3370 } 3371 3372 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3373 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3374 CALLOUT_LOCK(txq); 3375 callout_stop(&txq->ift_timer); 3376 CALLOUT_UNLOCK(txq); 3377 DBG_COUNTER_INC(txq_drain_oactive); 3378 return (0); 3379 } 3380 if (reclaimed) 3381 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3382 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3383 count = MIN(avail, TX_BATCH_SIZE); 3384 #ifdef INVARIANTS 3385 if (iflib_verbose_debug) 3386 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3387 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3388 #endif 3389 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3390 avail = TXQ_AVAIL(txq); 3391 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3392 int pidx_prev, rem = do_prefetch ? count - i : 0; 3393 3394 mp = _ring_peek_one(r, cidx, i, rem); 3395 MPASS(mp != NULL && *mp != NULL); 3396 if (__predict_false(*mp == (struct mbuf *)txq)) { 3397 consumed++; 3398 reclaimed++; 3399 continue; 3400 } 3401 in_use_prev = txq->ift_in_use; 3402 pidx_prev = txq->ift_pidx; 3403 err = iflib_encap(txq, mp); 3404 if (__predict_false(err)) { 3405 DBG_COUNTER_INC(txq_drain_encapfail); 3406 /* no room - bail out */ 3407 if (err == ENOBUFS) 3408 break; 3409 consumed++; 3410 DBG_COUNTER_INC(txq_drain_encapfail); 3411 /* we can't send this packet - skip it */ 3412 continue; 3413 } 3414 consumed++; 3415 pkt_sent++; 3416 m = *mp; 3417 DBG_COUNTER_INC(tx_sent); 3418 bytes_sent += m->m_pkthdr.len; 3419 mcast_sent += !!(m->m_flags & M_MCAST); 3420 avail = TXQ_AVAIL(txq); 3421 3422 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3423 desc_used += (txq->ift_in_use - in_use_prev); 3424 ETHER_BPF_MTAP(ifp, m); 3425 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3426 break; 3427 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3428 } 3429 3430 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3431 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3432 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3433 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3434 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3435 if (mcast_sent) 3436 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3437 #ifdef INVARIANTS 3438 if (iflib_verbose_debug) 3439 printf("consumed=%d\n", consumed); 3440 #endif 3441 return (consumed); 3442 } 3443 3444 static uint32_t 3445 iflib_txq_drain_always(struct ifmp_ring *r) 3446 { 3447 return (1); 3448 } 3449 3450 static uint32_t 3451 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3452 { 3453 int i, avail; 3454 struct mbuf **mp; 3455 iflib_txq_t txq; 3456 3457 txq = r->cookie; 3458 3459 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3460 CALLOUT_LOCK(txq); 3461 callout_stop(&txq->ift_timer); 3462 CALLOUT_UNLOCK(txq); 3463 3464 avail = IDXDIFF(pidx, cidx, r->size); 3465 for (i = 0; i < avail; i++) { 3466 mp = _ring_peek_one(r, cidx, i, avail - i); 3467 if (__predict_false(*mp == (struct mbuf *)txq)) 3468 continue; 3469 m_freem(*mp); 3470 } 3471 MPASS(ifmp_ring_is_stalled(r) == 0); 3472 return (avail); 3473 } 3474 3475 static void 3476 iflib_ifmp_purge(iflib_txq_t txq) 3477 { 3478 struct ifmp_ring *r; 3479 3480 r = txq->ift_br; 3481 r->drain = iflib_txq_drain_free; 3482 r->can_drain = iflib_txq_drain_always; 3483 3484 ifmp_ring_check_drainage(r, r->size); 3485 3486 r->drain = iflib_txq_drain; 3487 r->can_drain = iflib_txq_can_drain; 3488 } 3489 3490 static void 3491 _task_fn_tx(void *context) 3492 { 3493 iflib_txq_t txq = context; 3494 if_ctx_t ctx = txq->ift_ctx; 3495 struct ifnet *ifp = ctx->ifc_ifp; 3496 int rc; 3497 3498 #ifdef IFLIB_DIAGNOSTICS 3499 txq->ift_cpu_exec_count[curcpu]++; 3500 #endif 3501 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3502 return; 3503 if ((ifp->if_capenable & IFCAP_NETMAP)) { 3504 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3505 netmap_tx_irq(ifp, txq->ift_id); 3506 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3507 return; 3508 } 3509 if (txq->ift_db_pending) 3510 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); 3511 else 3512 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3513 if (ctx->ifc_flags & IFC_LEGACY) 3514 IFDI_INTR_ENABLE(ctx); 3515 else { 3516 rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3517 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3518 } 3519 } 3520 3521 static void 3522 _task_fn_rx(void *context) 3523 { 3524 iflib_rxq_t rxq = context; 3525 if_ctx_t ctx = rxq->ifr_ctx; 3526 bool more; 3527 int rc; 3528 3529 #ifdef IFLIB_DIAGNOSTICS 3530 rxq->ifr_cpu_exec_count[curcpu]++; 3531 #endif 3532 DBG_COUNTER_INC(task_fn_rxs); 3533 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3534 return; 3535 if ((more = iflib_rxeof(rxq, 16 /* XXX */)) == false) { 3536 if (ctx->ifc_flags & IFC_LEGACY) 3537 IFDI_INTR_ENABLE(ctx); 3538 else { 3539 DBG_COUNTER_INC(rx_intr_enables); 3540 rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3541 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3542 } 3543 } 3544 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3545 return; 3546 if (more) 3547 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3548 } 3549 3550 static void 3551 _task_fn_admin(void *context) 3552 { 3553 if_ctx_t ctx = context; 3554 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3555 iflib_txq_t txq; 3556 int i; 3557 3558 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) { 3559 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3560 return; 3561 } 3562 } 3563 3564 CTX_LOCK(ctx); 3565 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3566 CALLOUT_LOCK(txq); 3567 callout_stop(&txq->ift_timer); 3568 CALLOUT_UNLOCK(txq); 3569 } 3570 IFDI_UPDATE_ADMIN_STATUS(ctx); 3571 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3572 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 3573 IFDI_LINK_INTR_ENABLE(ctx); 3574 if (ctx->ifc_flags & IFC_DO_RESET) { 3575 ctx->ifc_flags &= ~IFC_DO_RESET; 3576 iflib_if_init_locked(ctx); 3577 } 3578 CTX_UNLOCK(ctx); 3579 3580 if (LINK_ACTIVE(ctx) == 0) 3581 return; 3582 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3583 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3584 } 3585 3586 3587 static void 3588 _task_fn_iov(void *context) 3589 { 3590 if_ctx_t ctx = context; 3591 3592 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3593 return; 3594 3595 CTX_LOCK(ctx); 3596 IFDI_VFLR_HANDLE(ctx); 3597 CTX_UNLOCK(ctx); 3598 } 3599 3600 static int 3601 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3602 { 3603 int err; 3604 if_int_delay_info_t info; 3605 if_ctx_t ctx; 3606 3607 info = (if_int_delay_info_t)arg1; 3608 ctx = info->iidi_ctx; 3609 info->iidi_req = req; 3610 info->iidi_oidp = oidp; 3611 CTX_LOCK(ctx); 3612 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3613 CTX_UNLOCK(ctx); 3614 return (err); 3615 } 3616 3617 /********************************************************************* 3618 * 3619 * IFNET FUNCTIONS 3620 * 3621 **********************************************************************/ 3622 3623 static void 3624 iflib_if_init_locked(if_ctx_t ctx) 3625 { 3626 iflib_stop(ctx); 3627 iflib_init_locked(ctx); 3628 } 3629 3630 3631 static void 3632 iflib_if_init(void *arg) 3633 { 3634 if_ctx_t ctx = arg; 3635 3636 CTX_LOCK(ctx); 3637 iflib_if_init_locked(ctx); 3638 CTX_UNLOCK(ctx); 3639 } 3640 3641 static int 3642 iflib_if_transmit(if_t ifp, struct mbuf *m) 3643 { 3644 if_ctx_t ctx = if_getsoftc(ifp); 3645 3646 iflib_txq_t txq; 3647 int err, qidx; 3648 3649 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3650 DBG_COUNTER_INC(tx_frees); 3651 m_freem(m); 3652 return (ENOBUFS); 3653 } 3654 3655 MPASS(m->m_nextpkt == NULL); 3656 qidx = 0; 3657 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3658 qidx = QIDX(ctx, m); 3659 /* 3660 * XXX calculate buf_ring based on flowid (divvy up bits?) 3661 */ 3662 txq = &ctx->ifc_txqs[qidx]; 3663 3664 #ifdef DRIVER_BACKPRESSURE 3665 if (txq->ift_closed) { 3666 while (m != NULL) { 3667 next = m->m_nextpkt; 3668 m->m_nextpkt = NULL; 3669 m_freem(m); 3670 m = next; 3671 } 3672 return (ENOBUFS); 3673 } 3674 #endif 3675 #ifdef notyet 3676 qidx = count = 0; 3677 mp = marr; 3678 next = m; 3679 do { 3680 count++; 3681 next = next->m_nextpkt; 3682 } while (next != NULL); 3683 3684 if (count > nitems(marr)) 3685 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3686 /* XXX check nextpkt */ 3687 m_freem(m); 3688 /* XXX simplify for now */ 3689 DBG_COUNTER_INC(tx_frees); 3690 return (ENOBUFS); 3691 } 3692 for (next = m, i = 0; next != NULL; i++) { 3693 mp[i] = next; 3694 next = next->m_nextpkt; 3695 mp[i]->m_nextpkt = NULL; 3696 } 3697 #endif 3698 DBG_COUNTER_INC(tx_seen); 3699 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); 3700 3701 if (err) { 3702 GROUPTASK_ENQUEUE(&txq->ift_task); 3703 /* support forthcoming later */ 3704 #ifdef DRIVER_BACKPRESSURE 3705 txq->ift_closed = TRUE; 3706 #endif 3707 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3708 m_freem(m); 3709 } else if (TXQ_AVAIL(txq) < (txq->ift_size >> 1)) { 3710 GROUPTASK_ENQUEUE(&txq->ift_task); 3711 } 3712 3713 return (err); 3714 } 3715 3716 static void 3717 iflib_if_qflush(if_t ifp) 3718 { 3719 if_ctx_t ctx = if_getsoftc(ifp); 3720 iflib_txq_t txq = ctx->ifc_txqs; 3721 int i; 3722 3723 CTX_LOCK(ctx); 3724 ctx->ifc_flags |= IFC_QFLUSH; 3725 CTX_UNLOCK(ctx); 3726 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3727 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3728 iflib_txq_check_drain(txq, 0); 3729 CTX_LOCK(ctx); 3730 ctx->ifc_flags &= ~IFC_QFLUSH; 3731 CTX_UNLOCK(ctx); 3732 3733 if_qflush(ifp); 3734 } 3735 3736 3737 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3738 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 3739 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 3740 3741 static int 3742 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 3743 { 3744 if_ctx_t ctx = if_getsoftc(ifp); 3745 struct ifreq *ifr = (struct ifreq *)data; 3746 #if defined(INET) || defined(INET6) 3747 struct ifaddr *ifa = (struct ifaddr *)data; 3748 #endif 3749 bool avoid_reset = FALSE; 3750 int err = 0, reinit = 0, bits; 3751 3752 switch (command) { 3753 case SIOCSIFADDR: 3754 #ifdef INET 3755 if (ifa->ifa_addr->sa_family == AF_INET) 3756 avoid_reset = TRUE; 3757 #endif 3758 #ifdef INET6 3759 if (ifa->ifa_addr->sa_family == AF_INET6) 3760 avoid_reset = TRUE; 3761 #endif 3762 /* 3763 ** Calling init results in link renegotiation, 3764 ** so we avoid doing it when possible. 3765 */ 3766 if (avoid_reset) { 3767 if_setflagbits(ifp, IFF_UP,0); 3768 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING)) 3769 reinit = 1; 3770 #ifdef INET 3771 if (!(if_getflags(ifp) & IFF_NOARP)) 3772 arp_ifinit(ifp, ifa); 3773 #endif 3774 } else 3775 err = ether_ioctl(ifp, command, data); 3776 break; 3777 case SIOCSIFMTU: 3778 CTX_LOCK(ctx); 3779 if (ifr->ifr_mtu == if_getmtu(ifp)) { 3780 CTX_UNLOCK(ctx); 3781 break; 3782 } 3783 bits = if_getdrvflags(ifp); 3784 /* stop the driver and free any clusters before proceeding */ 3785 iflib_stop(ctx); 3786 3787 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 3788 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 3789 ctx->ifc_flags |= IFC_MULTISEG; 3790 else 3791 ctx->ifc_flags &= ~IFC_MULTISEG; 3792 err = if_setmtu(ifp, ifr->ifr_mtu); 3793 } 3794 iflib_init_locked(ctx); 3795 if_setdrvflags(ifp, bits); 3796 CTX_UNLOCK(ctx); 3797 break; 3798 case SIOCSIFFLAGS: 3799 CTX_LOCK(ctx); 3800 if (if_getflags(ifp) & IFF_UP) { 3801 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3802 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 3803 (IFF_PROMISC | IFF_ALLMULTI)) { 3804 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 3805 } 3806 } else 3807 reinit = 1; 3808 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3809 iflib_stop(ctx); 3810 } 3811 ctx->ifc_if_flags = if_getflags(ifp); 3812 CTX_UNLOCK(ctx); 3813 break; 3814 case SIOCADDMULTI: 3815 case SIOCDELMULTI: 3816 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3817 CTX_LOCK(ctx); 3818 IFDI_INTR_DISABLE(ctx); 3819 IFDI_MULTI_SET(ctx); 3820 IFDI_INTR_ENABLE(ctx); 3821 CTX_UNLOCK(ctx); 3822 } 3823 break; 3824 case SIOCSIFMEDIA: 3825 CTX_LOCK(ctx); 3826 IFDI_MEDIA_SET(ctx); 3827 CTX_UNLOCK(ctx); 3828 /* falls thru */ 3829 case SIOCGIFMEDIA: 3830 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 3831 break; 3832 case SIOCGI2C: 3833 { 3834 struct ifi2creq i2c; 3835 3836 err = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); 3837 if (err != 0) 3838 break; 3839 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 3840 err = EINVAL; 3841 break; 3842 } 3843 if (i2c.len > sizeof(i2c.data)) { 3844 err = EINVAL; 3845 break; 3846 } 3847 3848 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 3849 err = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); 3850 break; 3851 } 3852 case SIOCSIFCAP: 3853 { 3854 int mask, setmask; 3855 3856 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3857 setmask = 0; 3858 #ifdef TCP_OFFLOAD 3859 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 3860 #endif 3861 setmask |= (mask & IFCAP_FLAGS); 3862 3863 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 3864 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 3865 if ((mask & IFCAP_WOL) && 3866 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 3867 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 3868 if_vlancap(ifp); 3869 /* 3870 * want to ensure that traffic has stopped before we change any of the flags 3871 */ 3872 if (setmask) { 3873 CTX_LOCK(ctx); 3874 bits = if_getdrvflags(ifp); 3875 if (bits & IFF_DRV_RUNNING) 3876 iflib_stop(ctx); 3877 if_togglecapenable(ifp, setmask); 3878 if (bits & IFF_DRV_RUNNING) 3879 iflib_init_locked(ctx); 3880 if_setdrvflags(ifp, bits); 3881 CTX_UNLOCK(ctx); 3882 } 3883 break; 3884 } 3885 case SIOCGPRIVATE_0: 3886 case SIOCSDRVSPEC: 3887 case SIOCGDRVSPEC: 3888 CTX_LOCK(ctx); 3889 err = IFDI_PRIV_IOCTL(ctx, command, data); 3890 CTX_UNLOCK(ctx); 3891 break; 3892 default: 3893 err = ether_ioctl(ifp, command, data); 3894 break; 3895 } 3896 if (reinit) 3897 iflib_if_init(ctx); 3898 return (err); 3899 } 3900 3901 static uint64_t 3902 iflib_if_get_counter(if_t ifp, ift_counter cnt) 3903 { 3904 if_ctx_t ctx = if_getsoftc(ifp); 3905 3906 return (IFDI_GET_COUNTER(ctx, cnt)); 3907 } 3908 3909 /********************************************************************* 3910 * 3911 * OTHER FUNCTIONS EXPORTED TO THE STACK 3912 * 3913 **********************************************************************/ 3914 3915 static void 3916 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 3917 { 3918 if_ctx_t ctx = if_getsoftc(ifp); 3919 3920 if ((void *)ctx != arg) 3921 return; 3922 3923 if ((vtag == 0) || (vtag > 4095)) 3924 return; 3925 3926 CTX_LOCK(ctx); 3927 IFDI_VLAN_REGISTER(ctx, vtag); 3928 /* Re-init to load the changes */ 3929 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 3930 iflib_if_init_locked(ctx); 3931 CTX_UNLOCK(ctx); 3932 } 3933 3934 static void 3935 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 3936 { 3937 if_ctx_t ctx = if_getsoftc(ifp); 3938 3939 if ((void *)ctx != arg) 3940 return; 3941 3942 if ((vtag == 0) || (vtag > 4095)) 3943 return; 3944 3945 CTX_LOCK(ctx); 3946 IFDI_VLAN_UNREGISTER(ctx, vtag); 3947 /* Re-init to load the changes */ 3948 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 3949 iflib_if_init_locked(ctx); 3950 CTX_UNLOCK(ctx); 3951 } 3952 3953 static void 3954 iflib_led_func(void *arg, int onoff) 3955 { 3956 if_ctx_t ctx = arg; 3957 3958 CTX_LOCK(ctx); 3959 IFDI_LED_FUNC(ctx, onoff); 3960 CTX_UNLOCK(ctx); 3961 } 3962 3963 /********************************************************************* 3964 * 3965 * BUS FUNCTION DEFINITIONS 3966 * 3967 **********************************************************************/ 3968 3969 int 3970 iflib_device_probe(device_t dev) 3971 { 3972 pci_vendor_info_t *ent; 3973 3974 uint16_t pci_vendor_id, pci_device_id; 3975 uint16_t pci_subvendor_id, pci_subdevice_id; 3976 uint16_t pci_rev_id; 3977 if_shared_ctx_t sctx; 3978 3979 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 3980 return (ENOTSUP); 3981 3982 pci_vendor_id = pci_get_vendor(dev); 3983 pci_device_id = pci_get_device(dev); 3984 pci_subvendor_id = pci_get_subvendor(dev); 3985 pci_subdevice_id = pci_get_subdevice(dev); 3986 pci_rev_id = pci_get_revid(dev); 3987 if (sctx->isc_parse_devinfo != NULL) 3988 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 3989 3990 ent = sctx->isc_vendor_info; 3991 while (ent->pvi_vendor_id != 0) { 3992 if (pci_vendor_id != ent->pvi_vendor_id) { 3993 ent++; 3994 continue; 3995 } 3996 if ((pci_device_id == ent->pvi_device_id) && 3997 ((pci_subvendor_id == ent->pvi_subvendor_id) || 3998 (ent->pvi_subvendor_id == 0)) && 3999 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4000 (ent->pvi_subdevice_id == 0)) && 4001 ((pci_rev_id == ent->pvi_rev_id) || 4002 (ent->pvi_rev_id == 0))) { 4003 4004 device_set_desc_copy(dev, ent->pvi_name); 4005 /* this needs to be changed to zero if the bus probing code 4006 * ever stops re-probing on best match because the sctx 4007 * may have its values over written by register calls 4008 * in subsequent probes 4009 */ 4010 return (BUS_PROBE_DEFAULT); 4011 } 4012 ent++; 4013 } 4014 return (ENXIO); 4015 } 4016 4017 int 4018 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4019 { 4020 int err, rid, msix, msix_bar; 4021 if_ctx_t ctx; 4022 if_t ifp; 4023 if_softc_ctx_t scctx; 4024 int i; 4025 uint16_t main_txq; 4026 uint16_t main_rxq; 4027 4028 4029 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4030 4031 if (sc == NULL) { 4032 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4033 device_set_softc(dev, ctx); 4034 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4035 } 4036 4037 ctx->ifc_sctx = sctx; 4038 ctx->ifc_dev = dev; 4039 ctx->ifc_softc = sc; 4040 4041 if ((err = iflib_register(ctx)) != 0) { 4042 device_printf(dev, "iflib_register failed %d\n", err); 4043 return (err); 4044 } 4045 iflib_add_device_sysctl_pre(ctx); 4046 4047 scctx = &ctx->ifc_softc_ctx; 4048 ifp = ctx->ifc_ifp; 4049 4050 /* 4051 * XXX sanity check that ntxd & nrxd are a power of 2 4052 */ 4053 if (ctx->ifc_sysctl_ntxqs != 0) 4054 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4055 if (ctx->ifc_sysctl_nrxqs != 0) 4056 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4057 4058 for (i = 0; i < sctx->isc_ntxqs; i++) { 4059 if (ctx->ifc_sysctl_ntxds[i] != 0) 4060 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4061 else 4062 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4063 } 4064 4065 for (i = 0; i < sctx->isc_nrxqs; i++) { 4066 if (ctx->ifc_sysctl_nrxds[i] != 0) 4067 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4068 else 4069 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4070 } 4071 4072 for (i = 0; i < sctx->isc_nrxqs; i++) { 4073 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4074 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4075 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4076 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4077 } 4078 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4079 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4080 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4081 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4082 } 4083 } 4084 4085 for (i = 0; i < sctx->isc_ntxqs; i++) { 4086 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4087 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4088 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4089 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4090 } 4091 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4092 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4093 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4094 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4095 } 4096 } 4097 4098 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4099 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4100 return (err); 4101 } 4102 _iflib_pre_assert(scctx); 4103 ctx->ifc_txrx = *scctx->isc_txrx; 4104 4105 #ifdef INVARIANTS 4106 MPASS(scctx->isc_capenable); 4107 if (scctx->isc_capenable & IFCAP_TXCSUM) 4108 MPASS(scctx->isc_tx_csum_flags); 4109 #endif 4110 4111 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4112 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4113 4114 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4115 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4116 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4117 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4118 4119 #ifdef ACPI_DMAR 4120 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4121 ctx->ifc_flags |= IFC_DMAR; 4122 #elif !(defined(__i386__) || defined(__amd64__)) 4123 /* set unconditionally for !x86 */ 4124 ctx->ifc_flags |= IFC_DMAR; 4125 #endif 4126 4127 msix_bar = scctx->isc_msix_bar; 4128 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4129 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4130 4131 /* XXX change for per-queue sizes */ 4132 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4133 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4134 for (i = 0; i < sctx->isc_nrxqs; i++) { 4135 if (!powerof2(scctx->isc_nrxd[i])) { 4136 /* round down instead? */ 4137 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4138 err = EINVAL; 4139 goto fail; 4140 } 4141 } 4142 for (i = 0; i < sctx->isc_ntxqs; i++) { 4143 if (!powerof2(scctx->isc_ntxd[i])) { 4144 device_printf(dev, 4145 "# tx descriptors must be a power of 2"); 4146 err = EINVAL; 4147 goto fail; 4148 } 4149 } 4150 4151 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4152 MAX_SINGLE_PACKET_FRACTION) 4153 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4154 MAX_SINGLE_PACKET_FRACTION); 4155 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4156 MAX_SINGLE_PACKET_FRACTION) 4157 scctx->isc_tx_tso_segments_max = max(1, 4158 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4159 4160 /* 4161 * Protect the stack against modern hardware 4162 */ 4163 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4164 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4165 4166 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4167 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4168 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4169 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4170 if (scctx->isc_rss_table_size == 0) 4171 scctx->isc_rss_table_size = 64; 4172 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4173 4174 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4175 /* XXX format name */ 4176 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4177 /* 4178 ** Now setup MSI or MSI/X, should 4179 ** return us the number of supported 4180 ** vectors. (Will be 1 for MSI) 4181 */ 4182 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4183 msix = scctx->isc_vectors; 4184 } else if (scctx->isc_msix_bar != 0) 4185 /* 4186 * The simple fact that isc_msix_bar is not 0 does not mean we 4187 * we have a good value there that is known to work. 4188 */ 4189 msix = iflib_msix_init(ctx); 4190 else { 4191 scctx->isc_vectors = 1; 4192 scctx->isc_ntxqsets = 1; 4193 scctx->isc_nrxqsets = 1; 4194 scctx->isc_intr = IFLIB_INTR_LEGACY; 4195 msix = 0; 4196 } 4197 /* Get memory for the station queues */ 4198 if ((err = iflib_queues_alloc(ctx))) { 4199 device_printf(dev, "Unable to allocate queue memory\n"); 4200 goto fail; 4201 } 4202 4203 if ((err = iflib_qset_structures_setup(ctx))) { 4204 device_printf(dev, "qset structure setup failed %d\n", err); 4205 goto fail_queues; 4206 } 4207 4208 /* 4209 * Group taskqueues aren't properly set up until SMP is started, 4210 * so we disable interrupts until we can handle them post 4211 * SI_SUB_SMP. 4212 * 4213 * XXX: disabling interrupts doesn't actually work, at least for 4214 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4215 * we do null handling and depend on this not causing too large an 4216 * interrupt storm. 4217 */ 4218 IFDI_INTR_DISABLE(ctx); 4219 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4220 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4221 goto fail_intr_free; 4222 } 4223 if (msix <= 1) { 4224 rid = 0; 4225 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4226 MPASS(msix == 1); 4227 rid = 1; 4228 } 4229 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4230 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4231 goto fail_intr_free; 4232 } 4233 } 4234 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4235 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4236 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4237 goto fail_detach; 4238 } 4239 if ((err = iflib_netmap_attach(ctx))) { 4240 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4241 goto fail_detach; 4242 } 4243 *ctxp = ctx; 4244 4245 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4246 iflib_add_device_sysctl_post(ctx); 4247 ctx->ifc_flags |= IFC_INIT_DONE; 4248 return (0); 4249 fail_detach: 4250 ether_ifdetach(ctx->ifc_ifp); 4251 fail_intr_free: 4252 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4253 pci_release_msi(ctx->ifc_dev); 4254 fail_queues: 4255 /* XXX free queues */ 4256 fail: 4257 IFDI_DETACH(ctx); 4258 return (err); 4259 } 4260 4261 int 4262 iflib_device_attach(device_t dev) 4263 { 4264 if_ctx_t ctx; 4265 if_shared_ctx_t sctx; 4266 4267 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4268 return (ENOTSUP); 4269 4270 pci_enable_busmaster(dev); 4271 4272 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4273 } 4274 4275 int 4276 iflib_device_deregister(if_ctx_t ctx) 4277 { 4278 if_t ifp = ctx->ifc_ifp; 4279 iflib_txq_t txq; 4280 iflib_rxq_t rxq; 4281 device_t dev = ctx->ifc_dev; 4282 int i, j; 4283 struct taskqgroup *tqg; 4284 iflib_fl_t fl; 4285 4286 /* Make sure VLANS are not using driver */ 4287 if (if_vlantrunkinuse(ifp)) { 4288 device_printf(dev,"Vlan in use, detach first\n"); 4289 return (EBUSY); 4290 } 4291 4292 CTX_LOCK(ctx); 4293 ctx->ifc_in_detach = 1; 4294 iflib_stop(ctx); 4295 CTX_UNLOCK(ctx); 4296 4297 /* Unregister VLAN events */ 4298 if (ctx->ifc_vlan_attach_event != NULL) 4299 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4300 if (ctx->ifc_vlan_detach_event != NULL) 4301 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4302 4303 iflib_netmap_detach(ifp); 4304 ether_ifdetach(ifp); 4305 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4306 CTX_LOCK_DESTROY(ctx); 4307 if (ctx->ifc_led_dev != NULL) 4308 led_destroy(ctx->ifc_led_dev); 4309 /* XXX drain any dependent tasks */ 4310 tqg = qgroup_if_io_tqg; 4311 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4312 callout_drain(&txq->ift_timer); 4313 if (txq->ift_task.gt_uniq != NULL) 4314 taskqgroup_detach(tqg, &txq->ift_task); 4315 } 4316 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4317 if (rxq->ifr_task.gt_uniq != NULL) 4318 taskqgroup_detach(tqg, &rxq->ifr_task); 4319 4320 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4321 free(fl->ifl_rx_bitmap, M_IFLIB); 4322 4323 } 4324 tqg = qgroup_if_config_tqg; 4325 if (ctx->ifc_admin_task.gt_uniq != NULL) 4326 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4327 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4328 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4329 4330 IFDI_DETACH(ctx); 4331 device_set_softc(ctx->ifc_dev, NULL); 4332 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4333 pci_release_msi(dev); 4334 } 4335 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4336 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4337 } 4338 if (ctx->ifc_msix_mem != NULL) { 4339 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4340 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4341 ctx->ifc_msix_mem = NULL; 4342 } 4343 4344 bus_generic_detach(dev); 4345 if_free(ifp); 4346 4347 iflib_tx_structures_free(ctx); 4348 iflib_rx_structures_free(ctx); 4349 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4350 free(ctx->ifc_softc, M_IFLIB); 4351 free(ctx, M_IFLIB); 4352 return (0); 4353 } 4354 4355 4356 int 4357 iflib_device_detach(device_t dev) 4358 { 4359 if_ctx_t ctx = device_get_softc(dev); 4360 4361 return (iflib_device_deregister(ctx)); 4362 } 4363 4364 int 4365 iflib_device_suspend(device_t dev) 4366 { 4367 if_ctx_t ctx = device_get_softc(dev); 4368 4369 CTX_LOCK(ctx); 4370 IFDI_SUSPEND(ctx); 4371 CTX_UNLOCK(ctx); 4372 4373 return bus_generic_suspend(dev); 4374 } 4375 int 4376 iflib_device_shutdown(device_t dev) 4377 { 4378 if_ctx_t ctx = device_get_softc(dev); 4379 4380 CTX_LOCK(ctx); 4381 IFDI_SHUTDOWN(ctx); 4382 CTX_UNLOCK(ctx); 4383 4384 return bus_generic_suspend(dev); 4385 } 4386 4387 4388 int 4389 iflib_device_resume(device_t dev) 4390 { 4391 if_ctx_t ctx = device_get_softc(dev); 4392 iflib_txq_t txq = ctx->ifc_txqs; 4393 4394 CTX_LOCK(ctx); 4395 IFDI_RESUME(ctx); 4396 iflib_init_locked(ctx); 4397 CTX_UNLOCK(ctx); 4398 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4399 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4400 4401 return (bus_generic_resume(dev)); 4402 } 4403 4404 int 4405 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4406 { 4407 int error; 4408 if_ctx_t ctx = device_get_softc(dev); 4409 4410 CTX_LOCK(ctx); 4411 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4412 CTX_UNLOCK(ctx); 4413 4414 return (error); 4415 } 4416 4417 void 4418 iflib_device_iov_uninit(device_t dev) 4419 { 4420 if_ctx_t ctx = device_get_softc(dev); 4421 4422 CTX_LOCK(ctx); 4423 IFDI_IOV_UNINIT(ctx); 4424 CTX_UNLOCK(ctx); 4425 } 4426 4427 int 4428 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 4429 { 4430 int error; 4431 if_ctx_t ctx = device_get_softc(dev); 4432 4433 CTX_LOCK(ctx); 4434 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 4435 CTX_UNLOCK(ctx); 4436 4437 return (error); 4438 } 4439 4440 /********************************************************************* 4441 * 4442 * MODULE FUNCTION DEFINITIONS 4443 * 4444 **********************************************************************/ 4445 4446 /* 4447 * - Start a fast taskqueue thread for each core 4448 * - Start a taskqueue for control operations 4449 */ 4450 static int 4451 iflib_module_init(void) 4452 { 4453 return (0); 4454 } 4455 4456 static int 4457 iflib_module_event_handler(module_t mod, int what, void *arg) 4458 { 4459 int err; 4460 4461 switch (what) { 4462 case MOD_LOAD: 4463 if ((err = iflib_module_init()) != 0) 4464 return (err); 4465 break; 4466 case MOD_UNLOAD: 4467 return (EBUSY); 4468 default: 4469 return (EOPNOTSUPP); 4470 } 4471 4472 return (0); 4473 } 4474 4475 /********************************************************************* 4476 * 4477 * PUBLIC FUNCTION DEFINITIONS 4478 * ordered as in iflib.h 4479 * 4480 **********************************************************************/ 4481 4482 4483 static void 4484 _iflib_assert(if_shared_ctx_t sctx) 4485 { 4486 MPASS(sctx->isc_tx_maxsize); 4487 MPASS(sctx->isc_tx_maxsegsize); 4488 4489 MPASS(sctx->isc_rx_maxsize); 4490 MPASS(sctx->isc_rx_nsegments); 4491 MPASS(sctx->isc_rx_maxsegsize); 4492 4493 MPASS(sctx->isc_nrxd_min[0]); 4494 MPASS(sctx->isc_nrxd_max[0]); 4495 MPASS(sctx->isc_nrxd_default[0]); 4496 MPASS(sctx->isc_ntxd_min[0]); 4497 MPASS(sctx->isc_ntxd_max[0]); 4498 MPASS(sctx->isc_ntxd_default[0]); 4499 } 4500 4501 static void 4502 _iflib_pre_assert(if_softc_ctx_t scctx) 4503 { 4504 4505 MPASS(scctx->isc_txrx->ift_txd_encap); 4506 MPASS(scctx->isc_txrx->ift_txd_flush); 4507 MPASS(scctx->isc_txrx->ift_txd_credits_update); 4508 MPASS(scctx->isc_txrx->ift_rxd_available); 4509 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 4510 MPASS(scctx->isc_txrx->ift_rxd_refill); 4511 MPASS(scctx->isc_txrx->ift_rxd_flush); 4512 } 4513 4514 static int 4515 iflib_register(if_ctx_t ctx) 4516 { 4517 if_shared_ctx_t sctx = ctx->ifc_sctx; 4518 driver_t *driver = sctx->isc_driver; 4519 device_t dev = ctx->ifc_dev; 4520 if_t ifp; 4521 4522 _iflib_assert(sctx); 4523 4524 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 4525 4526 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 4527 if (ifp == NULL) { 4528 device_printf(dev, "can not allocate ifnet structure\n"); 4529 return (ENOMEM); 4530 } 4531 4532 /* 4533 * Initialize our context's device specific methods 4534 */ 4535 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 4536 kobj_class_compile((kobj_class_t) driver); 4537 driver->refs++; 4538 4539 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 4540 if_setsoftc(ifp, ctx); 4541 if_setdev(ifp, dev); 4542 if_setinitfn(ifp, iflib_if_init); 4543 if_setioctlfn(ifp, iflib_if_ioctl); 4544 if_settransmitfn(ifp, iflib_if_transmit); 4545 if_setqflushfn(ifp, iflib_if_qflush); 4546 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 4547 4548 ctx->ifc_vlan_attach_event = 4549 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 4550 EVENTHANDLER_PRI_FIRST); 4551 ctx->ifc_vlan_detach_event = 4552 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 4553 EVENTHANDLER_PRI_FIRST); 4554 4555 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 4556 iflib_media_change, iflib_media_status); 4557 4558 return (0); 4559 } 4560 4561 4562 static int 4563 iflib_queues_alloc(if_ctx_t ctx) 4564 { 4565 if_shared_ctx_t sctx = ctx->ifc_sctx; 4566 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4567 device_t dev = ctx->ifc_dev; 4568 int nrxqsets = scctx->isc_nrxqsets; 4569 int ntxqsets = scctx->isc_ntxqsets; 4570 iflib_txq_t txq; 4571 iflib_rxq_t rxq; 4572 iflib_fl_t fl = NULL; 4573 int i, j, cpu, err, txconf, rxconf; 4574 iflib_dma_info_t ifdip; 4575 uint32_t *rxqsizes = scctx->isc_rxqsizes; 4576 uint32_t *txqsizes = scctx->isc_txqsizes; 4577 uint8_t nrxqs = sctx->isc_nrxqs; 4578 uint8_t ntxqs = sctx->isc_ntxqs; 4579 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 4580 caddr_t *vaddrs; 4581 uint64_t *paddrs; 4582 struct ifmp_ring **brscp; 4583 4584 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 4585 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 4586 4587 brscp = NULL; 4588 txq = NULL; 4589 rxq = NULL; 4590 4591 /* Allocate the TX ring struct memory */ 4592 if (!(txq = 4593 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 4594 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4595 device_printf(dev, "Unable to allocate TX ring memory\n"); 4596 err = ENOMEM; 4597 goto fail; 4598 } 4599 4600 /* Now allocate the RX */ 4601 if (!(rxq = 4602 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 4603 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4604 device_printf(dev, "Unable to allocate RX ring memory\n"); 4605 err = ENOMEM; 4606 goto rx_fail; 4607 } 4608 4609 ctx->ifc_txqs = txq; 4610 ctx->ifc_rxqs = rxq; 4611 4612 /* 4613 * XXX handle allocation failure 4614 */ 4615 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 4616 /* Set up some basics */ 4617 4618 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4619 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4620 err = ENOMEM; 4621 goto err_tx_desc; 4622 } 4623 txq->ift_ifdi = ifdip; 4624 for (j = 0; j < ntxqs; j++, ifdip++) { 4625 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4626 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4627 err = ENOMEM; 4628 goto err_tx_desc; 4629 } 4630 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 4631 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 4632 } 4633 txq->ift_ctx = ctx; 4634 txq->ift_id = i; 4635 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 4636 txq->ift_br_offset = 1; 4637 } else { 4638 txq->ift_br_offset = 0; 4639 } 4640 /* XXX fix this */ 4641 txq->ift_timer.c_cpu = cpu; 4642 4643 if (iflib_txsd_alloc(txq)) { 4644 device_printf(dev, "Critical Failure setting up TX buffers\n"); 4645 err = ENOMEM; 4646 goto err_tx_desc; 4647 } 4648 4649 /* Initialize the TX lock */ 4650 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 4651 device_get_nameunit(dev), txq->ift_id); 4652 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 4653 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 4654 4655 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 4656 device_get_nameunit(dev), txq->ift_id); 4657 4658 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 4659 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 4660 if (err) { 4661 /* XXX free any allocated rings */ 4662 device_printf(dev, "Unable to allocate buf_ring\n"); 4663 goto err_tx_desc; 4664 } 4665 } 4666 4667 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 4668 /* Set up some basics */ 4669 4670 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4671 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4672 err = ENOMEM; 4673 goto err_tx_desc; 4674 } 4675 4676 rxq->ifr_ifdi = ifdip; 4677 /* XXX this needs to be changed if #rx queues != #tx queues */ 4678 rxq->ifr_ntxqirq = 1; 4679 rxq->ifr_txqid[0] = i; 4680 for (j = 0; j < nrxqs; j++, ifdip++) { 4681 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4682 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4683 err = ENOMEM; 4684 goto err_tx_desc; 4685 } 4686 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 4687 } 4688 rxq->ifr_ctx = ctx; 4689 rxq->ifr_id = i; 4690 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 4691 rxq->ifr_fl_offset = 1; 4692 } else { 4693 rxq->ifr_fl_offset = 0; 4694 } 4695 rxq->ifr_nfl = nfree_lists; 4696 if (!(fl = 4697 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 4698 device_printf(dev, "Unable to allocate free list memory\n"); 4699 err = ENOMEM; 4700 goto err_tx_desc; 4701 } 4702 rxq->ifr_fl = fl; 4703 for (j = 0; j < nfree_lists; j++) { 4704 fl[j].ifl_rxq = rxq; 4705 fl[j].ifl_id = j; 4706 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 4707 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 4708 } 4709 /* Allocate receive buffers for the ring*/ 4710 if (iflib_rxsd_alloc(rxq)) { 4711 device_printf(dev, 4712 "Critical Failure setting up receive buffers\n"); 4713 err = ENOMEM; 4714 goto err_rx_desc; 4715 } 4716 4717 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4718 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 4719 } 4720 4721 /* TXQs */ 4722 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4723 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4724 for (i = 0; i < ntxqsets; i++) { 4725 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 4726 4727 for (j = 0; j < ntxqs; j++, di++) { 4728 vaddrs[i*ntxqs + j] = di->idi_vaddr; 4729 paddrs[i*ntxqs + j] = di->idi_paddr; 4730 } 4731 } 4732 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 4733 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4734 iflib_tx_structures_free(ctx); 4735 free(vaddrs, M_IFLIB); 4736 free(paddrs, M_IFLIB); 4737 goto err_rx_desc; 4738 } 4739 free(vaddrs, M_IFLIB); 4740 free(paddrs, M_IFLIB); 4741 4742 /* RXQs */ 4743 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4744 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4745 for (i = 0; i < nrxqsets; i++) { 4746 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 4747 4748 for (j = 0; j < nrxqs; j++, di++) { 4749 vaddrs[i*nrxqs + j] = di->idi_vaddr; 4750 paddrs[i*nrxqs + j] = di->idi_paddr; 4751 } 4752 } 4753 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 4754 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4755 iflib_tx_structures_free(ctx); 4756 free(vaddrs, M_IFLIB); 4757 free(paddrs, M_IFLIB); 4758 goto err_rx_desc; 4759 } 4760 free(vaddrs, M_IFLIB); 4761 free(paddrs, M_IFLIB); 4762 4763 return (0); 4764 4765 /* XXX handle allocation failure changes */ 4766 err_rx_desc: 4767 err_tx_desc: 4768 if (ctx->ifc_rxqs != NULL) 4769 free(ctx->ifc_rxqs, M_IFLIB); 4770 ctx->ifc_rxqs = NULL; 4771 if (ctx->ifc_txqs != NULL) 4772 free(ctx->ifc_txqs, M_IFLIB); 4773 ctx->ifc_txqs = NULL; 4774 rx_fail: 4775 if (brscp != NULL) 4776 free(brscp, M_IFLIB); 4777 if (rxq != NULL) 4778 free(rxq, M_IFLIB); 4779 if (txq != NULL) 4780 free(txq, M_IFLIB); 4781 fail: 4782 return (err); 4783 } 4784 4785 static int 4786 iflib_tx_structures_setup(if_ctx_t ctx) 4787 { 4788 iflib_txq_t txq = ctx->ifc_txqs; 4789 int i; 4790 4791 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4792 iflib_txq_setup(txq); 4793 4794 return (0); 4795 } 4796 4797 static void 4798 iflib_tx_structures_free(if_ctx_t ctx) 4799 { 4800 iflib_txq_t txq = ctx->ifc_txqs; 4801 int i, j; 4802 4803 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 4804 iflib_txq_destroy(txq); 4805 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 4806 iflib_dma_free(&txq->ift_ifdi[j]); 4807 } 4808 free(ctx->ifc_txqs, M_IFLIB); 4809 ctx->ifc_txqs = NULL; 4810 IFDI_QUEUES_FREE(ctx); 4811 } 4812 4813 /********************************************************************* 4814 * 4815 * Initialize all receive rings. 4816 * 4817 **********************************************************************/ 4818 static int 4819 iflib_rx_structures_setup(if_ctx_t ctx) 4820 { 4821 iflib_rxq_t rxq = ctx->ifc_rxqs; 4822 int q; 4823 #if defined(INET6) || defined(INET) 4824 int i, err; 4825 #endif 4826 4827 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 4828 #if defined(INET6) || defined(INET) 4829 tcp_lro_free(&rxq->ifr_lc); 4830 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 4831 TCP_LRO_ENTRIES, min(1024, 4832 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 4833 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 4834 goto fail; 4835 } 4836 rxq->ifr_lro_enabled = TRUE; 4837 #endif 4838 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 4839 } 4840 return (0); 4841 #if defined(INET6) || defined(INET) 4842 fail: 4843 /* 4844 * Free RX software descriptors allocated so far, we will only handle 4845 * the rings that completed, the failing case will have 4846 * cleaned up for itself. 'q' failed, so its the terminus. 4847 */ 4848 rxq = ctx->ifc_rxqs; 4849 for (i = 0; i < q; ++i, rxq++) { 4850 iflib_rx_sds_free(rxq); 4851 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 4852 } 4853 return (err); 4854 #endif 4855 } 4856 4857 /********************************************************************* 4858 * 4859 * Free all receive rings. 4860 * 4861 **********************************************************************/ 4862 static void 4863 iflib_rx_structures_free(if_ctx_t ctx) 4864 { 4865 iflib_rxq_t rxq = ctx->ifc_rxqs; 4866 4867 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 4868 iflib_rx_sds_free(rxq); 4869 } 4870 } 4871 4872 static int 4873 iflib_qset_structures_setup(if_ctx_t ctx) 4874 { 4875 int err; 4876 4877 if ((err = iflib_tx_structures_setup(ctx)) != 0) 4878 return (err); 4879 4880 if ((err = iflib_rx_structures_setup(ctx)) != 0) { 4881 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 4882 iflib_tx_structures_free(ctx); 4883 iflib_rx_structures_free(ctx); 4884 } 4885 return (err); 4886 } 4887 4888 int 4889 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 4890 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name) 4891 { 4892 4893 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 4894 } 4895 4896 static int 4897 find_nth(if_ctx_t ctx, cpuset_t *cpus, int qid) 4898 { 4899 int i, cpuid, eqid, count; 4900 4901 CPU_COPY(&ctx->ifc_cpus, cpus); 4902 count = CPU_COUNT(&ctx->ifc_cpus); 4903 eqid = qid % count; 4904 /* clear up to the qid'th bit */ 4905 for (i = 0; i < eqid; i++) { 4906 cpuid = CPU_FFS(cpus); 4907 MPASS(cpuid != 0); 4908 CPU_CLR(cpuid-1, cpus); 4909 } 4910 cpuid = CPU_FFS(cpus); 4911 MPASS(cpuid != 0); 4912 return (cpuid-1); 4913 } 4914 4915 int 4916 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 4917 iflib_intr_type_t type, driver_filter_t *filter, 4918 void *filter_arg, int qid, char *name) 4919 { 4920 struct grouptask *gtask; 4921 struct taskqgroup *tqg; 4922 iflib_filter_info_t info; 4923 cpuset_t cpus; 4924 gtask_fn_t *fn; 4925 int tqrid, err, cpuid; 4926 driver_filter_t *intr_fast; 4927 void *q; 4928 4929 info = &ctx->ifc_filter_info; 4930 tqrid = rid; 4931 4932 switch (type) { 4933 /* XXX merge tx/rx for netmap? */ 4934 case IFLIB_INTR_TX: 4935 q = &ctx->ifc_txqs[qid]; 4936 info = &ctx->ifc_txqs[qid].ift_filter_info; 4937 gtask = &ctx->ifc_txqs[qid].ift_task; 4938 tqg = qgroup_if_io_tqg; 4939 fn = _task_fn_tx; 4940 intr_fast = iflib_fast_intr; 4941 GROUPTASK_INIT(gtask, 0, fn, q); 4942 break; 4943 case IFLIB_INTR_RX: 4944 q = &ctx->ifc_rxqs[qid]; 4945 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 4946 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4947 tqg = qgroup_if_io_tqg; 4948 fn = _task_fn_rx; 4949 intr_fast = iflib_fast_intr; 4950 GROUPTASK_INIT(gtask, 0, fn, q); 4951 break; 4952 case IFLIB_INTR_RXTX: 4953 q = &ctx->ifc_rxqs[qid]; 4954 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 4955 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4956 tqg = qgroup_if_io_tqg; 4957 fn = _task_fn_rx; 4958 intr_fast = iflib_fast_intr_rxtx; 4959 GROUPTASK_INIT(gtask, 0, fn, q); 4960 break; 4961 case IFLIB_INTR_ADMIN: 4962 q = ctx; 4963 tqrid = -1; 4964 info = &ctx->ifc_filter_info; 4965 gtask = &ctx->ifc_admin_task; 4966 tqg = qgroup_if_config_tqg; 4967 fn = _task_fn_admin; 4968 intr_fast = iflib_fast_intr_ctx; 4969 break; 4970 default: 4971 panic("unknown net intr type"); 4972 } 4973 4974 info->ifi_filter = filter; 4975 info->ifi_filter_arg = filter_arg; 4976 info->ifi_task = gtask; 4977 info->ifi_ctx = q; 4978 4979 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 4980 if (err != 0) { 4981 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 4982 return (err); 4983 } 4984 if (type == IFLIB_INTR_ADMIN) 4985 return (0); 4986 4987 if (tqrid != -1) { 4988 cpuid = find_nth(ctx, &cpus, qid); 4989 taskqgroup_attach_cpu(tqg, gtask, q, cpuid, irq->ii_rid, name); 4990 } else { 4991 taskqgroup_attach(tqg, gtask, q, tqrid, name); 4992 } 4993 4994 return (0); 4995 } 4996 4997 void 4998 iflib_softirq_alloc_generic(if_ctx_t ctx, int rid, iflib_intr_type_t type, void *arg, int qid, char *name) 4999 { 5000 struct grouptask *gtask; 5001 struct taskqgroup *tqg; 5002 gtask_fn_t *fn; 5003 void *q; 5004 5005 switch (type) { 5006 case IFLIB_INTR_TX: 5007 q = &ctx->ifc_txqs[qid]; 5008 gtask = &ctx->ifc_txqs[qid].ift_task; 5009 tqg = qgroup_if_io_tqg; 5010 fn = _task_fn_tx; 5011 break; 5012 case IFLIB_INTR_RX: 5013 q = &ctx->ifc_rxqs[qid]; 5014 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5015 tqg = qgroup_if_io_tqg; 5016 fn = _task_fn_rx; 5017 break; 5018 case IFLIB_INTR_IOV: 5019 q = ctx; 5020 gtask = &ctx->ifc_vflr_task; 5021 tqg = qgroup_if_config_tqg; 5022 rid = -1; 5023 fn = _task_fn_iov; 5024 break; 5025 default: 5026 panic("unknown net intr type"); 5027 } 5028 GROUPTASK_INIT(gtask, 0, fn, q); 5029 taskqgroup_attach(tqg, gtask, q, rid, name); 5030 } 5031 5032 void 5033 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5034 { 5035 if (irq->ii_tag) 5036 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5037 5038 if (irq->ii_res) 5039 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5040 } 5041 5042 static int 5043 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name) 5044 { 5045 iflib_txq_t txq = ctx->ifc_txqs; 5046 iflib_rxq_t rxq = ctx->ifc_rxqs; 5047 if_irq_t irq = &ctx->ifc_legacy_irq; 5048 iflib_filter_info_t info; 5049 struct grouptask *gtask; 5050 struct taskqgroup *tqg; 5051 gtask_fn_t *fn; 5052 int tqrid; 5053 void *q; 5054 int err; 5055 5056 q = &ctx->ifc_rxqs[0]; 5057 info = &rxq[0].ifr_filter_info; 5058 gtask = &rxq[0].ifr_task; 5059 tqg = qgroup_if_io_tqg; 5060 tqrid = irq->ii_rid = *rid; 5061 fn = _task_fn_rx; 5062 5063 ctx->ifc_flags |= IFC_LEGACY; 5064 info->ifi_filter = filter; 5065 info->ifi_filter_arg = filter_arg; 5066 info->ifi_task = gtask; 5067 info->ifi_ctx = ctx; 5068 5069 /* We allocate a single interrupt resource */ 5070 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5071 return (err); 5072 GROUPTASK_INIT(gtask, 0, fn, q); 5073 taskqgroup_attach(tqg, gtask, q, tqrid, name); 5074 5075 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5076 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, tqrid, "tx"); 5077 return (0); 5078 } 5079 5080 void 5081 iflib_led_create(if_ctx_t ctx) 5082 { 5083 5084 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5085 device_get_nameunit(ctx->ifc_dev)); 5086 } 5087 5088 void 5089 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5090 { 5091 5092 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5093 } 5094 5095 void 5096 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5097 { 5098 5099 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5100 } 5101 5102 void 5103 iflib_admin_intr_deferred(if_ctx_t ctx) 5104 { 5105 #ifdef INVARIANTS 5106 struct grouptask *gtask; 5107 5108 gtask = &ctx->ifc_admin_task; 5109 MPASS(gtask->gt_taskqueue != NULL); 5110 #endif 5111 5112 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5113 } 5114 5115 void 5116 iflib_iov_intr_deferred(if_ctx_t ctx) 5117 { 5118 5119 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5120 } 5121 5122 void 5123 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5124 { 5125 5126 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5127 } 5128 5129 void 5130 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn, 5131 char *name) 5132 { 5133 5134 GROUPTASK_INIT(gtask, 0, fn, ctx); 5135 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5136 } 5137 5138 void 5139 iflib_config_gtask_deinit(struct grouptask *gtask) 5140 { 5141 5142 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5143 } 5144 5145 void 5146 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5147 { 5148 if_t ifp = ctx->ifc_ifp; 5149 iflib_txq_t txq = ctx->ifc_txqs; 5150 5151 if_setbaudrate(ifp, baudrate); 5152 if (baudrate >= IF_Gbps(10)) 5153 ctx->ifc_flags |= IFC_PREFETCH; 5154 5155 /* If link down, disable watchdog */ 5156 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5157 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5158 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5159 } 5160 ctx->ifc_link_state = link_state; 5161 if_link_state_change(ifp, link_state); 5162 } 5163 5164 static int 5165 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5166 { 5167 int credits; 5168 #ifdef INVARIANTS 5169 int credits_pre = txq->ift_cidx_processed; 5170 #endif 5171 5172 if (ctx->isc_txd_credits_update == NULL) 5173 return (0); 5174 5175 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5176 return (0); 5177 5178 txq->ift_processed += credits; 5179 txq->ift_cidx_processed += credits; 5180 5181 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5182 if (txq->ift_cidx_processed >= txq->ift_size) 5183 txq->ift_cidx_processed -= txq->ift_size; 5184 return (credits); 5185 } 5186 5187 static int 5188 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5189 { 5190 5191 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5192 budget)); 5193 } 5194 5195 void 5196 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5197 const char *description, if_int_delay_info_t info, 5198 int offset, int value) 5199 { 5200 info->iidi_ctx = ctx; 5201 info->iidi_offset = offset; 5202 info->iidi_value = value; 5203 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5204 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5205 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5206 info, 0, iflib_sysctl_int_delay, "I", description); 5207 } 5208 5209 struct mtx * 5210 iflib_ctx_lock_get(if_ctx_t ctx) 5211 { 5212 5213 return (&ctx->ifc_mtx); 5214 } 5215 5216 static int 5217 iflib_msix_init(if_ctx_t ctx) 5218 { 5219 device_t dev = ctx->ifc_dev; 5220 if_shared_ctx_t sctx = ctx->ifc_sctx; 5221 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5222 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5223 int iflib_num_tx_queues, iflib_num_rx_queues; 5224 int err, admincnt, bar; 5225 5226 iflib_num_tx_queues = scctx->isc_ntxqsets; 5227 iflib_num_rx_queues = scctx->isc_nrxqsets; 5228 5229 device_printf(dev, "msix_init qsets capped at %d\n", iflib_num_tx_queues); 5230 5231 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5232 admincnt = sctx->isc_admin_intrcnt; 5233 /* Override by tuneable */ 5234 if (scctx->isc_disable_msix) 5235 goto msi; 5236 5237 /* 5238 ** When used in a virtualized environment 5239 ** PCI BUSMASTER capability may not be set 5240 ** so explicity set it here and rewrite 5241 ** the ENABLE in the MSIX control register 5242 ** at this point to cause the host to 5243 ** successfully initialize us. 5244 */ 5245 { 5246 int msix_ctrl, rid; 5247 5248 pci_enable_busmaster(dev); 5249 rid = 0; 5250 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) { 5251 rid += PCIR_MSIX_CTRL; 5252 msix_ctrl = pci_read_config(dev, rid, 2); 5253 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 5254 pci_write_config(dev, rid, msix_ctrl, 2); 5255 } else { 5256 device_printf(dev, "PCIY_MSIX capability not found; " 5257 "or rid %d == 0.\n", rid); 5258 goto msi; 5259 } 5260 } 5261 5262 /* 5263 * bar == -1 => "trust me I know what I'm doing" 5264 * Some drivers are for hardware that is so shoddily 5265 * documented that no one knows which bars are which 5266 * so the developer has to map all bars. This hack 5267 * allows shoddy garbage to use msix in this framework. 5268 */ 5269 if (bar != -1) { 5270 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5271 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5272 if (ctx->ifc_msix_mem == NULL) { 5273 /* May not be enabled */ 5274 device_printf(dev, "Unable to map MSIX table \n"); 5275 goto msi; 5276 } 5277 } 5278 /* First try MSI/X */ 5279 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5280 device_printf(dev, "System has MSIX disabled \n"); 5281 bus_release_resource(dev, SYS_RES_MEMORY, 5282 bar, ctx->ifc_msix_mem); 5283 ctx->ifc_msix_mem = NULL; 5284 goto msi; 5285 } 5286 #if IFLIB_DEBUG 5287 /* use only 1 qset in debug mode */ 5288 queuemsgs = min(msgs - admincnt, 1); 5289 #else 5290 queuemsgs = msgs - admincnt; 5291 #endif 5292 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) == 0) { 5293 #ifdef RSS 5294 queues = imin(queuemsgs, rss_getnumbuckets()); 5295 #else 5296 queues = queuemsgs; 5297 #endif 5298 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 5299 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 5300 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 5301 } else { 5302 device_printf(dev, "Unable to fetch CPU list\n"); 5303 /* Figure out a reasonable auto config value */ 5304 queues = min(queuemsgs, mp_ncpus); 5305 } 5306 #ifdef RSS 5307 /* If we're doing RSS, clamp at the number of RSS buckets */ 5308 if (queues > rss_getnumbuckets()) 5309 queues = rss_getnumbuckets(); 5310 #endif 5311 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 5312 rx_queues = iflib_num_rx_queues; 5313 else 5314 rx_queues = queues; 5315 /* 5316 * We want this to be all logical CPUs by default 5317 */ 5318 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 5319 tx_queues = iflib_num_tx_queues; 5320 else 5321 tx_queues = mp_ncpus; 5322 5323 if (ctx->ifc_sysctl_qs_eq_override == 0) { 5324 #ifdef INVARIANTS 5325 if (tx_queues != rx_queues) 5326 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 5327 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 5328 #endif 5329 tx_queues = min(rx_queues, tx_queues); 5330 rx_queues = min(rx_queues, tx_queues); 5331 } 5332 5333 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 5334 5335 vectors = rx_queues + admincnt; 5336 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 5337 device_printf(dev, 5338 "Using MSIX interrupts with %d vectors\n", vectors); 5339 scctx->isc_vectors = vectors; 5340 scctx->isc_nrxqsets = rx_queues; 5341 scctx->isc_ntxqsets = tx_queues; 5342 scctx->isc_intr = IFLIB_INTR_MSIX; 5343 5344 return (vectors); 5345 } else { 5346 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 5347 } 5348 msi: 5349 vectors = pci_msi_count(dev); 5350 scctx->isc_nrxqsets = 1; 5351 scctx->isc_ntxqsets = 1; 5352 scctx->isc_vectors = vectors; 5353 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 5354 device_printf(dev,"Using an MSI interrupt\n"); 5355 scctx->isc_intr = IFLIB_INTR_MSI; 5356 } else { 5357 device_printf(dev,"Using a Legacy interrupt\n"); 5358 scctx->isc_intr = IFLIB_INTR_LEGACY; 5359 } 5360 5361 return (vectors); 5362 } 5363 5364 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 5365 5366 static int 5367 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 5368 { 5369 int rc; 5370 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 5371 struct sbuf *sb; 5372 char *ring_state = "UNKNOWN"; 5373 5374 /* XXX needed ? */ 5375 rc = sysctl_wire_old_buffer(req, 0); 5376 MPASS(rc == 0); 5377 if (rc != 0) 5378 return (rc); 5379 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 5380 MPASS(sb != NULL); 5381 if (sb == NULL) 5382 return (ENOMEM); 5383 if (state[3] <= 3) 5384 ring_state = ring_states[state[3]]; 5385 5386 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 5387 state[0], state[1], state[2], ring_state); 5388 rc = sbuf_finish(sb); 5389 sbuf_delete(sb); 5390 return(rc); 5391 } 5392 5393 enum iflib_ndesc_handler { 5394 IFLIB_NTXD_HANDLER, 5395 IFLIB_NRXD_HANDLER, 5396 }; 5397 5398 static int 5399 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 5400 { 5401 if_ctx_t ctx = (void *)arg1; 5402 enum iflib_ndesc_handler type = arg2; 5403 char buf[256] = {0}; 5404 qidx_t *ndesc; 5405 char *p, *next; 5406 int nqs, rc, i; 5407 5408 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 5409 5410 nqs = 8; 5411 switch(type) { 5412 case IFLIB_NTXD_HANDLER: 5413 ndesc = ctx->ifc_sysctl_ntxds; 5414 if (ctx->ifc_sctx) 5415 nqs = ctx->ifc_sctx->isc_ntxqs; 5416 break; 5417 case IFLIB_NRXD_HANDLER: 5418 ndesc = ctx->ifc_sysctl_nrxds; 5419 if (ctx->ifc_sctx) 5420 nqs = ctx->ifc_sctx->isc_nrxqs; 5421 break; 5422 } 5423 if (nqs == 0) 5424 nqs = 8; 5425 5426 for (i=0; i<8; i++) { 5427 if (i >= nqs) 5428 break; 5429 if (i) 5430 strcat(buf, ","); 5431 sprintf(strchr(buf, 0), "%d", ndesc[i]); 5432 } 5433 5434 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 5435 if (rc || req->newptr == NULL) 5436 return rc; 5437 5438 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 5439 i++, p = strsep(&next, " ,")) { 5440 ndesc[i] = strtoul(p, NULL, 10); 5441 } 5442 5443 return(rc); 5444 } 5445 5446 #define NAME_BUFLEN 32 5447 static void 5448 iflib_add_device_sysctl_pre(if_ctx_t ctx) 5449 { 5450 device_t dev = iflib_get_dev(ctx); 5451 struct sysctl_oid_list *child, *oid_list; 5452 struct sysctl_ctx_list *ctx_list; 5453 struct sysctl_oid *node; 5454 5455 ctx_list = device_get_sysctl_ctx(dev); 5456 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 5457 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 5458 CTLFLAG_RD, NULL, "IFLIB fields"); 5459 oid_list = SYSCTL_CHILDREN(node); 5460 5461 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 5462 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 5463 "driver version"); 5464 5465 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 5466 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 5467 "# of txqs to use, 0 => use default #"); 5468 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 5469 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 5470 "# of rxqs to use, 0 => use default #"); 5471 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 5472 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 5473 "permit #txq != #rxq"); 5474 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 5475 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 5476 "disable MSIX (default 0)"); 5477 5478 /* XXX change for per-queue sizes */ 5479 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 5480 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 5481 mp_ndesc_handler, "A", 5482 "list of # of tx descriptors to use, 0 = use default #"); 5483 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 5484 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 5485 mp_ndesc_handler, "A", 5486 "list of # of rx descriptors to use, 0 = use default #"); 5487 } 5488 5489 static void 5490 iflib_add_device_sysctl_post(if_ctx_t ctx) 5491 { 5492 if_shared_ctx_t sctx = ctx->ifc_sctx; 5493 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5494 device_t dev = iflib_get_dev(ctx); 5495 struct sysctl_oid_list *child; 5496 struct sysctl_ctx_list *ctx_list; 5497 iflib_fl_t fl; 5498 iflib_txq_t txq; 5499 iflib_rxq_t rxq; 5500 int i, j; 5501 char namebuf[NAME_BUFLEN]; 5502 char *qfmt; 5503 struct sysctl_oid *queue_node, *fl_node, *node; 5504 struct sysctl_oid_list *queue_list, *fl_list; 5505 ctx_list = device_get_sysctl_ctx(dev); 5506 5507 node = ctx->ifc_sysctl_node; 5508 child = SYSCTL_CHILDREN(node); 5509 5510 if (scctx->isc_ntxqsets > 100) 5511 qfmt = "txq%03d"; 5512 else if (scctx->isc_ntxqsets > 10) 5513 qfmt = "txq%02d"; 5514 else 5515 qfmt = "txq%d"; 5516 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 5517 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5518 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5519 CTLFLAG_RD, NULL, "Queue Name"); 5520 queue_list = SYSCTL_CHILDREN(queue_node); 5521 #if MEMORY_LOGGING 5522 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 5523 CTLFLAG_RD, 5524 &txq->ift_dequeued, "total mbufs freed"); 5525 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 5526 CTLFLAG_RD, 5527 &txq->ift_enqueued, "total mbufs enqueued"); 5528 #endif 5529 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 5530 CTLFLAG_RD, 5531 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 5532 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 5533 CTLFLAG_RD, 5534 &txq->ift_pullups, "# of times m_pullup was called"); 5535 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 5536 CTLFLAG_RD, 5537 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 5538 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 5539 CTLFLAG_RD, 5540 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 5541 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 5542 CTLFLAG_RD, 5543 &txq->ift_map_failed, "# of times dma map failed"); 5544 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 5545 CTLFLAG_RD, 5546 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 5547 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 5548 CTLFLAG_RD, 5549 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 5550 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 5551 CTLFLAG_RD, 5552 &txq->ift_pidx, 1, "Producer Index"); 5553 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 5554 CTLFLAG_RD, 5555 &txq->ift_cidx, 1, "Consumer Index"); 5556 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 5557 CTLFLAG_RD, 5558 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 5559 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 5560 CTLFLAG_RD, 5561 &txq->ift_in_use, 1, "descriptors in use"); 5562 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 5563 CTLFLAG_RD, 5564 &txq->ift_processed, "descriptors procesed for clean"); 5565 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 5566 CTLFLAG_RD, 5567 &txq->ift_cleaned, "total cleaned"); 5568 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 5569 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 5570 0, mp_ring_state_handler, "A", "soft ring state"); 5571 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 5572 CTLFLAG_RD, &txq->ift_br->enqueues, 5573 "# of enqueues to the mp_ring for this queue"); 5574 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 5575 CTLFLAG_RD, &txq->ift_br->drops, 5576 "# of drops in the mp_ring for this queue"); 5577 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 5578 CTLFLAG_RD, &txq->ift_br->starts, 5579 "# of normal consumer starts in the mp_ring for this queue"); 5580 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 5581 CTLFLAG_RD, &txq->ift_br->stalls, 5582 "# of consumer stalls in the mp_ring for this queue"); 5583 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 5584 CTLFLAG_RD, &txq->ift_br->restarts, 5585 "# of consumer restarts in the mp_ring for this queue"); 5586 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 5587 CTLFLAG_RD, &txq->ift_br->abdications, 5588 "# of consumer abdications in the mp_ring for this queue"); 5589 } 5590 5591 if (scctx->isc_nrxqsets > 100) 5592 qfmt = "rxq%03d"; 5593 else if (scctx->isc_nrxqsets > 10) 5594 qfmt = "rxq%02d"; 5595 else 5596 qfmt = "rxq%d"; 5597 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 5598 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5599 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5600 CTLFLAG_RD, NULL, "Queue Name"); 5601 queue_list = SYSCTL_CHILDREN(queue_node); 5602 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5603 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 5604 CTLFLAG_RD, 5605 &rxq->ifr_cq_pidx, 1, "Producer Index"); 5606 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 5607 CTLFLAG_RD, 5608 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 5609 } 5610 5611 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 5612 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 5613 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 5614 CTLFLAG_RD, NULL, "freelist Name"); 5615 fl_list = SYSCTL_CHILDREN(fl_node); 5616 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 5617 CTLFLAG_RD, 5618 &fl->ifl_pidx, 1, "Producer Index"); 5619 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 5620 CTLFLAG_RD, 5621 &fl->ifl_cidx, 1, "Consumer Index"); 5622 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 5623 CTLFLAG_RD, 5624 &fl->ifl_credits, 1, "credits available"); 5625 #if MEMORY_LOGGING 5626 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 5627 CTLFLAG_RD, 5628 &fl->ifl_m_enqueued, "mbufs allocated"); 5629 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 5630 CTLFLAG_RD, 5631 &fl->ifl_m_dequeued, "mbufs freed"); 5632 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 5633 CTLFLAG_RD, 5634 &fl->ifl_cl_enqueued, "clusters allocated"); 5635 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 5636 CTLFLAG_RD, 5637 &fl->ifl_cl_dequeued, "clusters freed"); 5638 #endif 5639 5640 } 5641 } 5642 5643 } 5644 5645 #ifndef __NO_STRICT_ALIGNMENT 5646 static struct mbuf * 5647 iflib_fixup_rx(struct mbuf *m) 5648 { 5649 struct mbuf *n; 5650 5651 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 5652 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 5653 m->m_data += ETHER_HDR_LEN; 5654 n = m; 5655 } else { 5656 MGETHDR(n, M_NOWAIT, MT_DATA); 5657 if (n == NULL) { 5658 m_freem(m); 5659 return (NULL); 5660 } 5661 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 5662 m->m_data += ETHER_HDR_LEN; 5663 m->m_len -= ETHER_HDR_LEN; 5664 n->m_len = ETHER_HDR_LEN; 5665 M_MOVE_PKTHDR(n, m); 5666 n->m_next = m; 5667 } 5668 return (n); 5669 } 5670 #endif 5671