1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 /* 120 * File organization: 121 * - private structures 122 * - iflib private utility functions 123 * - ifnet functions 124 * - vlan registry and other exported functions 125 * - iflib public core functions 126 * 127 * 128 */ 129 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 130 131 #define IFLIB_RXEOF_MORE (1U << 0) 132 #define IFLIB_RXEOF_EMPTY (2U << 0) 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 static void iflib_tqg_detach(if_ctx_t ctx); 146 147 typedef struct iflib_filter_info { 148 driver_filter_t *ifi_filter; 149 void *ifi_filter_arg; 150 struct grouptask *ifi_task; 151 void *ifi_ctx; 152 } *iflib_filter_info_t; 153 154 struct iflib_ctx { 155 KOBJ_FIELDS; 156 /* 157 * Pointer to hardware driver's softc 158 */ 159 void *ifc_softc; 160 device_t ifc_dev; 161 if_t ifc_ifp; 162 163 cpuset_t ifc_cpus; 164 if_shared_ctx_t ifc_sctx; 165 struct if_softc_ctx ifc_softc_ctx; 166 167 struct sx ifc_ctx_sx; 168 struct mtx ifc_state_mtx; 169 170 iflib_txq_t ifc_txqs; 171 iflib_rxq_t ifc_rxqs; 172 uint32_t ifc_if_flags; 173 uint32_t ifc_flags; 174 uint32_t ifc_max_fl_buf_size; 175 uint32_t ifc_rx_mbuf_sz; 176 177 int ifc_link_state; 178 int ifc_watchdog_events; 179 struct cdev *ifc_led_dev; 180 struct resource *ifc_msix_mem; 181 182 struct if_irq ifc_legacy_irq; 183 struct grouptask ifc_admin_task; 184 struct grouptask ifc_vflr_task; 185 struct iflib_filter_info ifc_filter_info; 186 struct ifmedia ifc_media; 187 struct ifmedia *ifc_mediap; 188 189 struct sysctl_oid *ifc_sysctl_node; 190 uint16_t ifc_sysctl_ntxqs; 191 uint16_t ifc_sysctl_nrxqs; 192 uint16_t ifc_sysctl_qs_eq_override; 193 uint16_t ifc_sysctl_rx_budget; 194 uint16_t ifc_sysctl_tx_abdicate; 195 uint16_t ifc_sysctl_core_offset; 196 #define CORE_OFFSET_UNSPECIFIED 0xffff 197 uint8_t ifc_sysctl_separate_txrx; 198 199 qidx_t ifc_sysctl_ntxds[8]; 200 qidx_t ifc_sysctl_nrxds[8]; 201 struct if_txrx ifc_txrx; 202 #define isc_txd_encap ifc_txrx.ift_txd_encap 203 #define isc_txd_flush ifc_txrx.ift_txd_flush 204 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 205 #define isc_rxd_available ifc_txrx.ift_rxd_available 206 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 209 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 210 eventhandler_tag ifc_vlan_attach_event; 211 eventhandler_tag ifc_vlan_detach_event; 212 struct ether_addr ifc_mac; 213 }; 214 215 void * 216 iflib_get_softc(if_ctx_t ctx) 217 { 218 219 return (ctx->ifc_softc); 220 } 221 222 device_t 223 iflib_get_dev(if_ctx_t ctx) 224 { 225 226 return (ctx->ifc_dev); 227 } 228 229 if_t 230 iflib_get_ifp(if_ctx_t ctx) 231 { 232 233 return (ctx->ifc_ifp); 234 } 235 236 struct ifmedia * 237 iflib_get_media(if_ctx_t ctx) 238 { 239 240 return (ctx->ifc_mediap); 241 } 242 243 uint32_t 244 iflib_get_flags(if_ctx_t ctx) 245 { 246 return (ctx->ifc_flags); 247 } 248 249 void 250 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 251 { 252 253 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 254 } 255 256 if_softc_ctx_t 257 iflib_get_softc_ctx(if_ctx_t ctx) 258 { 259 260 return (&ctx->ifc_softc_ctx); 261 } 262 263 if_shared_ctx_t 264 iflib_get_sctx(if_ctx_t ctx) 265 { 266 267 return (ctx->ifc_sctx); 268 } 269 270 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 271 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 272 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 273 274 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 275 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 276 277 typedef struct iflib_sw_rx_desc_array { 278 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 279 struct mbuf **ifsd_m; /* pkthdr mbufs */ 280 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 281 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 282 } iflib_rxsd_array_t; 283 284 typedef struct iflib_sw_tx_desc_array { 285 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 286 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 287 struct mbuf **ifsd_m; /* pkthdr mbufs */ 288 } if_txsd_vec_t; 289 290 /* magic number that should be high enough for any hardware */ 291 #define IFLIB_MAX_TX_SEGS 128 292 #define IFLIB_RX_COPY_THRESH 128 293 #define IFLIB_MAX_RX_REFRESH 32 294 /* The minimum descriptors per second before we start coalescing */ 295 #define IFLIB_MIN_DESC_SEC 16384 296 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 297 #define IFLIB_QUEUE_IDLE 0 298 #define IFLIB_QUEUE_HUNG 1 299 #define IFLIB_QUEUE_WORKING 2 300 /* maximum number of txqs that can share an rx interrupt */ 301 #define IFLIB_MAX_TX_SHARED_INTR 4 302 303 /* this should really scale with ring size - this is a fairly arbitrary value */ 304 #define TX_BATCH_SIZE 32 305 306 #define IFLIB_RESTART_BUDGET 8 307 308 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 309 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 310 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 311 312 struct iflib_txq { 313 qidx_t ift_in_use; 314 qidx_t ift_cidx; 315 qidx_t ift_cidx_processed; 316 qidx_t ift_pidx; 317 uint8_t ift_gen; 318 uint8_t ift_br_offset; 319 uint16_t ift_npending; 320 uint16_t ift_db_pending; 321 uint16_t ift_rs_pending; 322 /* implicit pad */ 323 uint8_t ift_txd_size[8]; 324 uint64_t ift_processed; 325 uint64_t ift_cleaned; 326 uint64_t ift_cleaned_prev; 327 #if MEMORY_LOGGING 328 uint64_t ift_enqueued; 329 uint64_t ift_dequeued; 330 #endif 331 uint64_t ift_no_tx_dma_setup; 332 uint64_t ift_no_desc_avail; 333 uint64_t ift_mbuf_defrag_failed; 334 uint64_t ift_mbuf_defrag; 335 uint64_t ift_map_failed; 336 uint64_t ift_txd_encap_efbig; 337 uint64_t ift_pullups; 338 uint64_t ift_last_timer_tick; 339 340 struct mtx ift_mtx; 341 struct mtx ift_db_mtx; 342 343 /* constant values */ 344 if_ctx_t ift_ctx; 345 struct ifmp_ring *ift_br; 346 struct grouptask ift_task; 347 qidx_t ift_size; 348 uint16_t ift_id; 349 struct callout ift_timer; 350 #ifdef DEV_NETMAP 351 struct callout ift_netmap_timer; 352 #endif /* DEV_NETMAP */ 353 354 if_txsd_vec_t ift_sds; 355 uint8_t ift_qstatus; 356 uint8_t ift_closed; 357 uint8_t ift_update_freq; 358 struct iflib_filter_info ift_filter_info; 359 bus_dma_tag_t ift_buf_tag; 360 bus_dma_tag_t ift_tso_buf_tag; 361 iflib_dma_info_t ift_ifdi; 362 #define MTX_NAME_LEN 32 363 char ift_mtx_name[MTX_NAME_LEN]; 364 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 365 #ifdef IFLIB_DIAGNOSTICS 366 uint64_t ift_cpu_exec_count[256]; 367 #endif 368 } __aligned(CACHE_LINE_SIZE); 369 370 struct iflib_fl { 371 qidx_t ifl_cidx; 372 qidx_t ifl_pidx; 373 qidx_t ifl_credits; 374 uint8_t ifl_gen; 375 uint8_t ifl_rxd_size; 376 #if MEMORY_LOGGING 377 uint64_t ifl_m_enqueued; 378 uint64_t ifl_m_dequeued; 379 uint64_t ifl_cl_enqueued; 380 uint64_t ifl_cl_dequeued; 381 #endif 382 /* implicit pad */ 383 bitstr_t *ifl_rx_bitmap; 384 qidx_t ifl_fragidx; 385 /* constant */ 386 qidx_t ifl_size; 387 uint16_t ifl_buf_size; 388 uint16_t ifl_cltype; 389 uma_zone_t ifl_zone; 390 iflib_rxsd_array_t ifl_sds; 391 iflib_rxq_t ifl_rxq; 392 uint8_t ifl_id; 393 bus_dma_tag_t ifl_buf_tag; 394 iflib_dma_info_t ifl_ifdi; 395 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 396 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 397 } __aligned(CACHE_LINE_SIZE); 398 399 static inline qidx_t 400 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 401 { 402 qidx_t used; 403 404 if (pidx > cidx) 405 used = pidx - cidx; 406 else if (pidx < cidx) 407 used = size - cidx + pidx; 408 else if (gen == 0 && pidx == cidx) 409 used = 0; 410 else if (gen == 1 && pidx == cidx) 411 used = size; 412 else 413 panic("bad state"); 414 415 return (used); 416 } 417 418 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 419 420 #define IDXDIFF(head, tail, wrap) \ 421 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 422 423 struct iflib_rxq { 424 if_ctx_t ifr_ctx; 425 iflib_fl_t ifr_fl; 426 uint64_t ifr_rx_irq; 427 struct pfil_head *pfil; 428 /* 429 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 430 * the completion queue consumer index. Otherwise it's unused. 431 */ 432 qidx_t ifr_cq_cidx; 433 uint16_t ifr_id; 434 uint8_t ifr_nfl; 435 uint8_t ifr_ntxqirq; 436 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 437 uint8_t ifr_fl_offset; 438 struct lro_ctrl ifr_lc; 439 struct grouptask ifr_task; 440 struct callout ifr_watchdog; 441 struct iflib_filter_info ifr_filter_info; 442 iflib_dma_info_t ifr_ifdi; 443 444 /* dynamically allocate if any drivers need a value substantially larger than this */ 445 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 446 #ifdef IFLIB_DIAGNOSTICS 447 uint64_t ifr_cpu_exec_count[256]; 448 #endif 449 } __aligned(CACHE_LINE_SIZE); 450 451 typedef struct if_rxsd { 452 caddr_t *ifsd_cl; 453 iflib_fl_t ifsd_fl; 454 } *if_rxsd_t; 455 456 /* multiple of word size */ 457 #ifdef __LP64__ 458 #define PKT_INFO_SIZE 6 459 #define RXD_INFO_SIZE 5 460 #define PKT_TYPE uint64_t 461 #else 462 #define PKT_INFO_SIZE 11 463 #define RXD_INFO_SIZE 8 464 #define PKT_TYPE uint32_t 465 #endif 466 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 467 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 468 469 typedef struct if_pkt_info_pad { 470 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 471 } *if_pkt_info_pad_t; 472 typedef struct if_rxd_info_pad { 473 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 474 } *if_rxd_info_pad_t; 475 476 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 477 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 478 479 static inline void 480 pkt_info_zero(if_pkt_info_t pi) 481 { 482 if_pkt_info_pad_t pi_pad; 483 484 pi_pad = (if_pkt_info_pad_t)pi; 485 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 486 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 487 #ifndef __LP64__ 488 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 489 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 490 #endif 491 } 492 493 static device_method_t iflib_pseudo_methods[] = { 494 DEVMETHOD(device_attach, noop_attach), 495 DEVMETHOD(device_detach, iflib_pseudo_detach), 496 DEVMETHOD_END 497 }; 498 499 driver_t iflib_pseudodriver = { 500 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 501 }; 502 503 static inline void 504 rxd_info_zero(if_rxd_info_t ri) 505 { 506 if_rxd_info_pad_t ri_pad; 507 int i; 508 509 ri_pad = (if_rxd_info_pad_t)ri; 510 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 511 ri_pad->rxd_val[i] = 0; 512 ri_pad->rxd_val[i+1] = 0; 513 ri_pad->rxd_val[i+2] = 0; 514 ri_pad->rxd_val[i+3] = 0; 515 } 516 #ifdef __LP64__ 517 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 518 #endif 519 } 520 521 /* 522 * Only allow a single packet to take up most 1/nth of the tx ring 523 */ 524 #define MAX_SINGLE_PACKET_FRACTION 12 525 #define IF_BAD_DMA (bus_addr_t)-1 526 527 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 528 529 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 530 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 531 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 532 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 533 534 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 535 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 536 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 537 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 538 539 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 540 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 541 542 void 543 iflib_set_detach(if_ctx_t ctx) 544 { 545 STATE_LOCK(ctx); 546 ctx->ifc_flags |= IFC_IN_DETACH; 547 STATE_UNLOCK(ctx); 548 } 549 550 /* Our boot-time initialization hook */ 551 static int iflib_module_event_handler(module_t, int, void *); 552 553 static moduledata_t iflib_moduledata = { 554 "iflib", 555 iflib_module_event_handler, 556 NULL 557 }; 558 559 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 560 MODULE_VERSION(iflib, 1); 561 562 MODULE_DEPEND(iflib, pci, 1, 1, 1); 563 MODULE_DEPEND(iflib, ether, 1, 1, 1); 564 565 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 566 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 567 568 #ifndef IFLIB_DEBUG_COUNTERS 569 #ifdef INVARIANTS 570 #define IFLIB_DEBUG_COUNTERS 1 571 #else 572 #define IFLIB_DEBUG_COUNTERS 0 573 #endif /* !INVARIANTS */ 574 #endif 575 576 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 577 "iflib driver parameters"); 578 579 /* 580 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 581 */ 582 static int iflib_min_tx_latency = 0; 583 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 584 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 585 static int iflib_no_tx_batch = 0; 586 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 587 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 588 static int iflib_timer_default = 1000; 589 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW, 590 &iflib_timer_default, 0, "number of ticks between iflib_timer calls"); 591 592 593 #if IFLIB_DEBUG_COUNTERS 594 595 static int iflib_tx_seen; 596 static int iflib_tx_sent; 597 static int iflib_tx_encap; 598 static int iflib_rx_allocs; 599 static int iflib_fl_refills; 600 static int iflib_fl_refills_large; 601 static int iflib_tx_frees; 602 603 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 604 &iflib_tx_seen, 0, "# TX mbufs seen"); 605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 606 &iflib_tx_sent, 0, "# TX mbufs sent"); 607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 608 &iflib_tx_encap, 0, "# TX mbufs encapped"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 610 &iflib_tx_frees, 0, "# TX frees"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 612 &iflib_rx_allocs, 0, "# RX allocations"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 614 &iflib_fl_refills, 0, "# refills"); 615 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 616 &iflib_fl_refills_large, 0, "# large refills"); 617 618 static int iflib_txq_drain_flushing; 619 static int iflib_txq_drain_oactive; 620 static int iflib_txq_drain_notready; 621 622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 623 &iflib_txq_drain_flushing, 0, "# drain flushes"); 624 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 625 &iflib_txq_drain_oactive, 0, "# drain oactives"); 626 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 627 &iflib_txq_drain_notready, 0, "# drain notready"); 628 629 static int iflib_encap_load_mbuf_fail; 630 static int iflib_encap_pad_mbuf_fail; 631 static int iflib_encap_txq_avail_fail; 632 static int iflib_encap_txd_encap_fail; 633 634 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 635 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 637 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 638 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 639 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 640 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 641 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 642 643 static int iflib_task_fn_rxs; 644 static int iflib_rx_intr_enables; 645 static int iflib_fast_intrs; 646 static int iflib_rx_unavail; 647 static int iflib_rx_ctx_inactive; 648 static int iflib_rx_if_input; 649 static int iflib_rxd_flush; 650 651 static int iflib_verbose_debug; 652 653 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 654 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 655 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 656 &iflib_rx_intr_enables, 0, "# RX intr enables"); 657 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 658 &iflib_fast_intrs, 0, "# fast_intr calls"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 660 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 662 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 664 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 666 &iflib_rxd_flush, 0, "# times rxd_flush called"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 668 &iflib_verbose_debug, 0, "enable verbose debugging"); 669 670 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 671 static void 672 iflib_debug_reset(void) 673 { 674 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 675 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 676 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 677 iflib_txq_drain_notready = 678 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 679 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 680 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 681 iflib_rx_unavail = 682 iflib_rx_ctx_inactive = iflib_rx_if_input = 683 iflib_rxd_flush = 0; 684 } 685 686 #else 687 #define DBG_COUNTER_INC(name) 688 static void iflib_debug_reset(void) {} 689 #endif 690 691 #define IFLIB_DEBUG 0 692 693 static void iflib_tx_structures_free(if_ctx_t ctx); 694 static void iflib_rx_structures_free(if_ctx_t ctx); 695 static int iflib_queues_alloc(if_ctx_t ctx); 696 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 697 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 698 static int iflib_qset_structures_setup(if_ctx_t ctx); 699 static int iflib_msix_init(if_ctx_t ctx); 700 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 701 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 702 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 703 #ifdef ALTQ 704 static void iflib_altq_if_start(if_t ifp); 705 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 706 #endif 707 static int iflib_register(if_ctx_t); 708 static void iflib_deregister(if_ctx_t); 709 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 710 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 711 static void iflib_init_locked(if_ctx_t ctx); 712 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 713 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 714 static void iflib_ifmp_purge(iflib_txq_t txq); 715 static void _iflib_pre_assert(if_softc_ctx_t scctx); 716 static void iflib_if_init_locked(if_ctx_t ctx); 717 static void iflib_free_intr_mem(if_ctx_t ctx); 718 #ifndef __NO_STRICT_ALIGNMENT 719 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 720 #endif 721 722 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 723 SLIST_HEAD_INITIALIZER(cpu_offsets); 724 struct cpu_offset { 725 SLIST_ENTRY(cpu_offset) entries; 726 cpuset_t set; 727 unsigned int refcount; 728 uint16_t offset; 729 }; 730 static struct mtx cpu_offset_mtx; 731 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 732 MTX_DEF); 733 734 DEBUGNET_DEFINE(iflib); 735 736 static int 737 iflib_num_rx_descs(if_ctx_t ctx) 738 { 739 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 740 if_shared_ctx_t sctx = ctx->ifc_sctx; 741 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 742 743 return scctx->isc_nrxd[first_rxq]; 744 } 745 746 static int 747 iflib_num_tx_descs(if_ctx_t ctx) 748 { 749 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 750 if_shared_ctx_t sctx = ctx->ifc_sctx; 751 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 752 753 return scctx->isc_ntxd[first_txq]; 754 } 755 756 #ifdef DEV_NETMAP 757 #include <sys/selinfo.h> 758 #include <net/netmap.h> 759 #include <dev/netmap/netmap_kern.h> 760 761 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 762 763 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 764 static void iflib_netmap_timer(void *arg); 765 766 /* 767 * device-specific sysctl variables: 768 * 769 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 770 * During regular operations the CRC is stripped, but on some 771 * hardware reception of frames not multiple of 64 is slower, 772 * so using crcstrip=0 helps in benchmarks. 773 * 774 * iflib_rx_miss, iflib_rx_miss_bufs: 775 * count packets that might be missed due to lost interrupts. 776 */ 777 SYSCTL_DECL(_dev_netmap); 778 /* 779 * The xl driver by default strips CRCs and we do not override it. 780 */ 781 782 int iflib_crcstrip = 1; 783 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 784 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 785 786 int iflib_rx_miss, iflib_rx_miss_bufs; 787 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 788 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 789 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 790 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 791 792 /* 793 * Register/unregister. We are already under netmap lock. 794 * Only called on the first register or the last unregister. 795 */ 796 static int 797 iflib_netmap_register(struct netmap_adapter *na, int onoff) 798 { 799 if_t ifp = na->ifp; 800 if_ctx_t ctx = ifp->if_softc; 801 int status; 802 803 CTX_LOCK(ctx); 804 IFDI_INTR_DISABLE(ctx); 805 806 /* Tell the stack that the interface is no longer active */ 807 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 808 809 if (!CTX_IS_VF(ctx)) 810 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 811 812 iflib_stop(ctx); 813 814 /* 815 * Enable (or disable) netmap flags, and intercept (or restore) 816 * ifp->if_transmit. This is done once the device has been stopped 817 * to prevent race conditions. 818 */ 819 if (onoff) { 820 nm_set_native_flags(na); 821 } else { 822 nm_clear_native_flags(na); 823 } 824 825 iflib_init_locked(ctx); 826 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 827 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 828 if (status) 829 nm_clear_native_flags(na); 830 CTX_UNLOCK(ctx); 831 return (status); 832 } 833 834 static int 835 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 836 { 837 struct netmap_adapter *na = kring->na; 838 u_int const lim = kring->nkr_num_slots - 1; 839 u_int nm_i = kring->nr_hwcur; 840 struct netmap_ring *ring = kring->ring; 841 bus_dmamap_t *map; 842 struct if_rxd_update iru; 843 if_ctx_t ctx = rxq->ifr_ctx; 844 iflib_fl_t fl = &rxq->ifr_fl[0]; 845 u_int nic_i_first, nic_i; 846 int i, n; 847 #if IFLIB_DEBUG_COUNTERS 848 int rf_count = 0; 849 #endif 850 851 /* 852 * This function is used both at initialization and in rxsync. 853 * At initialization we need to prepare (with isc_rxd_refill()) 854 * all the (N) netmap buffers in the ring, in such a way to keep 855 * fl->ifl_pidx and kring->nr_hwcur in sync (except for 856 * kring->nkr_hwofs); at rxsync time, both indexes point to the 857 * next buffer to be refilled. 858 * In any case we publish (with isc_rxd_flush()) up to 859 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 860 * pointer to overrun the head/cons pointer, although this is 861 * not necessary for some NICs (e.g. vmx). 862 */ 863 if (__predict_false(init)) 864 n = kring->nkr_num_slots; 865 else { 866 n = kring->rhead - nm_i; 867 if (n == 0) 868 return (0); /* Nothing to do. */ 869 if (n < 0) 870 n += kring->nkr_num_slots; 871 } 872 873 /* Start to refill from nr_hwcur, publishing n buffers. */ 874 iru_init(&iru, rxq, 0 /* flid */); 875 map = fl->ifl_sds.ifsd_map; 876 nic_i = fl->ifl_pidx; 877 MPASS(nic_i == netmap_idx_k2n(kring, nm_i)); 878 DBG_COUNTER_INC(fl_refills); 879 while (n > 0) { 880 #if IFLIB_DEBUG_COUNTERS 881 if (++rf_count == 9) 882 DBG_COUNTER_INC(fl_refills_large); 883 #endif 884 nic_i_first = nic_i; 885 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 886 struct netmap_slot *slot = &ring->slot[nm_i]; 887 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]); 888 889 MPASS(i < IFLIB_MAX_RX_REFRESH); 890 891 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 892 return netmap_ring_reinit(kring); 893 894 fl->ifl_rxd_idxs[i] = nic_i; 895 896 if (__predict_false(init)) { 897 netmap_load_map(na, fl->ifl_buf_tag, 898 map[nic_i], addr); 899 } else if (slot->flags & NS_BUF_CHANGED) { 900 /* buffer has changed, reload map */ 901 netmap_reload_map(na, fl->ifl_buf_tag, 902 map[nic_i], addr); 903 } 904 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 905 BUS_DMASYNC_PREREAD); 906 slot->flags &= ~NS_BUF_CHANGED; 907 908 nm_i = nm_next(nm_i, lim); 909 nic_i = nm_next(nic_i, lim); 910 } 911 912 iru.iru_pidx = nic_i_first; 913 iru.iru_count = i; 914 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 915 } 916 fl->ifl_pidx = nic_i; 917 MPASS(!init || nm_i == 0); 918 MPASS(nm_i == kring->rhead); 919 kring->nr_hwcur = nm_i; 920 921 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 922 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 923 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 924 nm_prev(nic_i, lim)); 925 DBG_COUNTER_INC(rxd_flush); 926 927 return (0); 928 } 929 930 #define NETMAP_TX_TIMER_US 90 931 932 /* 933 * Reconcile kernel and user view of the transmit ring. 934 * 935 * All information is in the kring. 936 * Userspace wants to send packets up to the one before kring->rhead, 937 * kernel knows kring->nr_hwcur is the first unsent packet. 938 * 939 * Here we push packets out (as many as possible), and possibly 940 * reclaim buffers from previously completed transmission. 941 * 942 * The caller (netmap) guarantees that there is only one instance 943 * running at any time. Any interference with other driver 944 * methods should be handled by the individual drivers. 945 */ 946 static int 947 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 948 { 949 struct netmap_adapter *na = kring->na; 950 if_t ifp = na->ifp; 951 struct netmap_ring *ring = kring->ring; 952 u_int nm_i; /* index into the netmap kring */ 953 u_int nic_i; /* index into the NIC ring */ 954 u_int n; 955 u_int const lim = kring->nkr_num_slots - 1; 956 u_int const head = kring->rhead; 957 struct if_pkt_info pi; 958 959 /* 960 * interrupts on every tx packet are expensive so request 961 * them every half ring, or where NS_REPORT is set 962 */ 963 u_int report_frequency = kring->nkr_num_slots >> 1; 964 /* device-specific */ 965 if_ctx_t ctx = ifp->if_softc; 966 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 967 968 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 969 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 970 971 /* 972 * First part: process new packets to send. 973 * nm_i is the current index in the netmap kring, 974 * nic_i is the corresponding index in the NIC ring. 975 * 976 * If we have packets to send (nm_i != head) 977 * iterate over the netmap ring, fetch length and update 978 * the corresponding slot in the NIC ring. Some drivers also 979 * need to update the buffer's physical address in the NIC slot 980 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 981 * 982 * The netmap_reload_map() calls is especially expensive, 983 * even when (as in this case) the tag is 0, so do only 984 * when the buffer has actually changed. 985 * 986 * If possible do not set the report/intr bit on all slots, 987 * but only a few times per ring or when NS_REPORT is set. 988 * 989 * Finally, on 10G and faster drivers, it might be useful 990 * to prefetch the next slot and txr entry. 991 */ 992 993 nm_i = kring->nr_hwcur; 994 if (nm_i != head) { /* we have new packets to send */ 995 pkt_info_zero(&pi); 996 pi.ipi_segs = txq->ift_segs; 997 pi.ipi_qsidx = kring->ring_id; 998 nic_i = netmap_idx_k2n(kring, nm_i); 999 1000 __builtin_prefetch(&ring->slot[nm_i]); 1001 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 1002 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 1003 1004 for (n = 0; nm_i != head; n++) { 1005 struct netmap_slot *slot = &ring->slot[nm_i]; 1006 u_int len = slot->len; 1007 uint64_t paddr; 1008 void *addr = PNMB(na, slot, &paddr); 1009 int flags = (slot->flags & NS_REPORT || 1010 nic_i == 0 || nic_i == report_frequency) ? 1011 IPI_TX_INTR : 0; 1012 1013 /* device-specific */ 1014 pi.ipi_len = len; 1015 pi.ipi_segs[0].ds_addr = paddr; 1016 pi.ipi_segs[0].ds_len = len; 1017 pi.ipi_nsegs = 1; 1018 pi.ipi_ndescs = 0; 1019 pi.ipi_pidx = nic_i; 1020 pi.ipi_flags = flags; 1021 1022 /* Fill the slot in the NIC ring. */ 1023 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1024 DBG_COUNTER_INC(tx_encap); 1025 1026 /* prefetch for next round */ 1027 __builtin_prefetch(&ring->slot[nm_i + 1]); 1028 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1029 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1030 1031 NM_CHECK_ADDR_LEN(na, addr, len); 1032 1033 if (slot->flags & NS_BUF_CHANGED) { 1034 /* buffer has changed, reload map */ 1035 netmap_reload_map(na, txq->ift_buf_tag, 1036 txq->ift_sds.ifsd_map[nic_i], addr); 1037 } 1038 /* make sure changes to the buffer are synced */ 1039 bus_dmamap_sync(txq->ift_buf_tag, 1040 txq->ift_sds.ifsd_map[nic_i], 1041 BUS_DMASYNC_PREWRITE); 1042 1043 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1044 nm_i = nm_next(nm_i, lim); 1045 nic_i = nm_next(nic_i, lim); 1046 } 1047 kring->nr_hwcur = nm_i; 1048 1049 /* synchronize the NIC ring */ 1050 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1051 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1052 1053 /* (re)start the tx unit up to slot nic_i (excluded) */ 1054 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1055 } 1056 1057 /* 1058 * Second part: reclaim buffers for completed transmissions. 1059 * 1060 * If there are unclaimed buffers, attempt to reclaim them. 1061 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1062 * trigger a per-tx-queue timer to try again later. 1063 */ 1064 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1065 if (iflib_tx_credits_update(ctx, txq)) { 1066 /* some tx completed, increment avail */ 1067 nic_i = txq->ift_cidx_processed; 1068 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1069 } 1070 } 1071 1072 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1073 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1074 callout_reset_sbt_on(&txq->ift_netmap_timer, 1075 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1076 iflib_netmap_timer, txq, 1077 txq->ift_netmap_timer.c_cpu, 0); 1078 } 1079 return (0); 1080 } 1081 1082 /* 1083 * Reconcile kernel and user view of the receive ring. 1084 * Same as for the txsync, this routine must be efficient. 1085 * The caller guarantees a single invocations, but races against 1086 * the rest of the driver should be handled here. 1087 * 1088 * On call, kring->rhead is the first packet that userspace wants 1089 * to keep, and kring->rcur is the wakeup point. 1090 * The kernel has previously reported packets up to kring->rtail. 1091 * 1092 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1093 * of whether or not we received an interrupt. 1094 */ 1095 static int 1096 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1097 { 1098 struct netmap_adapter *na = kring->na; 1099 struct netmap_ring *ring = kring->ring; 1100 if_t ifp = na->ifp; 1101 uint32_t nm_i; /* index into the netmap ring */ 1102 uint32_t nic_i; /* index into the NIC ring */ 1103 u_int n; 1104 u_int const lim = kring->nkr_num_slots - 1; 1105 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1106 1107 if_ctx_t ctx = ifp->if_softc; 1108 if_shared_ctx_t sctx = ctx->ifc_sctx; 1109 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1110 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1111 iflib_fl_t fl = &rxq->ifr_fl[0]; 1112 struct if_rxd_info ri; 1113 qidx_t *cidxp; 1114 1115 /* 1116 * netmap only uses free list 0, to avoid out of order consumption 1117 * of receive buffers 1118 */ 1119 1120 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1121 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1122 1123 /* 1124 * First part: import newly received packets. 1125 * 1126 * nm_i is the index of the next free slot in the netmap ring, 1127 * nic_i is the index of the next received packet in the NIC ring 1128 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1129 * differ in case if_init() has been called while 1130 * in netmap mode. For the receive ring we have 1131 * 1132 * nic_i = fl->ifl_cidx; 1133 * nm_i = kring->nr_hwtail (previous) 1134 * and 1135 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1136 * 1137 * fl->ifl_cidx is set to 0 on a ring reinit 1138 */ 1139 if (netmap_no_pendintr || force_update) { 1140 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1141 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1142 int crclen = iflib_crcstrip ? 0 : 4; 1143 int error, avail; 1144 1145 /* 1146 * For the free list consumer index, we use the same 1147 * logic as in iflib_rxeof(). 1148 */ 1149 if (have_rxcq) 1150 cidxp = &rxq->ifr_cq_cidx; 1151 else 1152 cidxp = &fl->ifl_cidx; 1153 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1154 rxq->ifr_id, *cidxp, USHRT_MAX); 1155 1156 nic_i = fl->ifl_cidx; 1157 nm_i = netmap_idx_n2k(kring, nic_i); 1158 MPASS(nm_i == kring->nr_hwtail); 1159 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1160 rxd_info_zero(&ri); 1161 ri.iri_frags = rxq->ifr_frags; 1162 ri.iri_qsidx = kring->ring_id; 1163 ri.iri_ifp = ctx->ifc_ifp; 1164 ri.iri_cidx = *cidxp; 1165 1166 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1167 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1168 ring->slot[nm_i].flags = 0; 1169 if (have_rxcq) { 1170 *cidxp = ri.iri_cidx; 1171 while (*cidxp >= scctx->isc_nrxd[0]) 1172 *cidxp -= scctx->isc_nrxd[0]; 1173 } 1174 bus_dmamap_sync(fl->ifl_buf_tag, 1175 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1176 nm_i = nm_next(nm_i, lim); 1177 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1178 } 1179 if (n) { /* update the state variables */ 1180 if (netmap_no_pendintr && !force_update) { 1181 /* diagnostics */ 1182 iflib_rx_miss ++; 1183 iflib_rx_miss_bufs += n; 1184 } 1185 kring->nr_hwtail = nm_i; 1186 } 1187 kring->nr_kflags &= ~NKR_PENDINTR; 1188 } 1189 /* 1190 * Second part: skip past packets that userspace has released. 1191 * (kring->nr_hwcur to head excluded), 1192 * and make the buffers available for reception. 1193 * As usual nm_i is the index in the netmap ring, 1194 * nic_i is the index in the NIC ring, and 1195 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1196 */ 1197 netmap_fl_refill(rxq, kring, false); 1198 1199 return (0); 1200 } 1201 1202 static void 1203 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1204 { 1205 if_ctx_t ctx = na->ifp->if_softc; 1206 1207 CTX_LOCK(ctx); 1208 if (onoff) { 1209 IFDI_INTR_ENABLE(ctx); 1210 } else { 1211 IFDI_INTR_DISABLE(ctx); 1212 } 1213 CTX_UNLOCK(ctx); 1214 } 1215 1216 static int 1217 iflib_netmap_attach(if_ctx_t ctx) 1218 { 1219 struct netmap_adapter na; 1220 1221 bzero(&na, sizeof(na)); 1222 1223 na.ifp = ctx->ifc_ifp; 1224 na.na_flags = NAF_BDG_MAYSLEEP; 1225 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1226 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1227 1228 na.num_tx_desc = iflib_num_tx_descs(ctx); 1229 na.num_rx_desc = iflib_num_rx_descs(ctx); 1230 na.nm_txsync = iflib_netmap_txsync; 1231 na.nm_rxsync = iflib_netmap_rxsync; 1232 na.nm_register = iflib_netmap_register; 1233 na.nm_intr = iflib_netmap_intr; 1234 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1235 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1236 return (netmap_attach(&na)); 1237 } 1238 1239 static int 1240 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1241 { 1242 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1243 struct netmap_slot *slot; 1244 1245 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1246 if (slot == NULL) 1247 return (0); 1248 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1249 /* 1250 * In netmap mode, set the map for the packet buffer. 1251 * NOTE: Some drivers (not this one) also need to set 1252 * the physical buffer address in the NIC ring. 1253 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1254 * netmap slot index, si 1255 */ 1256 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1257 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1258 NMB(na, slot + si)); 1259 } 1260 return (1); 1261 } 1262 1263 static int 1264 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1265 { 1266 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1267 struct netmap_kring *kring; 1268 struct netmap_slot *slot; 1269 1270 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1271 if (slot == NULL) 1272 return (0); 1273 kring = na->rx_rings[rxq->ifr_id]; 1274 netmap_fl_refill(rxq, kring, true); 1275 return (1); 1276 } 1277 1278 static void 1279 iflib_netmap_timer(void *arg) 1280 { 1281 iflib_txq_t txq = arg; 1282 if_ctx_t ctx = txq->ift_ctx; 1283 1284 /* 1285 * Wake up the netmap application, to give it a chance to 1286 * call txsync and reclaim more completed TX buffers. 1287 */ 1288 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1289 } 1290 1291 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1292 1293 #else 1294 #define iflib_netmap_txq_init(ctx, txq) (0) 1295 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1296 #define iflib_netmap_detach(ifp) 1297 1298 #define iflib_netmap_attach(ctx) (0) 1299 #define netmap_rx_irq(ifp, qid, budget) (0) 1300 #endif 1301 1302 #if defined(__i386__) || defined(__amd64__) 1303 static __inline void 1304 prefetch(void *x) 1305 { 1306 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1307 } 1308 static __inline void 1309 prefetch2cachelines(void *x) 1310 { 1311 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1312 #if (CACHE_LINE_SIZE < 128) 1313 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1314 #endif 1315 } 1316 #else 1317 #define prefetch(x) 1318 #define prefetch2cachelines(x) 1319 #endif 1320 1321 static void 1322 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1323 { 1324 iflib_fl_t fl; 1325 1326 fl = &rxq->ifr_fl[flid]; 1327 iru->iru_paddrs = fl->ifl_bus_addrs; 1328 iru->iru_idxs = fl->ifl_rxd_idxs; 1329 iru->iru_qsidx = rxq->ifr_id; 1330 iru->iru_buf_size = fl->ifl_buf_size; 1331 iru->iru_flidx = fl->ifl_id; 1332 } 1333 1334 static void 1335 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1336 { 1337 if (err) 1338 return; 1339 *(bus_addr_t *) arg = segs[0].ds_addr; 1340 } 1341 1342 int 1343 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1344 { 1345 int err; 1346 device_t dev = ctx->ifc_dev; 1347 1348 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1349 align, 0, /* alignment, bounds */ 1350 BUS_SPACE_MAXADDR, /* lowaddr */ 1351 BUS_SPACE_MAXADDR, /* highaddr */ 1352 NULL, NULL, /* filter, filterarg */ 1353 size, /* maxsize */ 1354 1, /* nsegments */ 1355 size, /* maxsegsize */ 1356 BUS_DMA_ALLOCNOW, /* flags */ 1357 NULL, /* lockfunc */ 1358 NULL, /* lockarg */ 1359 &dma->idi_tag); 1360 if (err) { 1361 device_printf(dev, 1362 "%s: bus_dma_tag_create failed: %d\n", 1363 __func__, err); 1364 goto fail_0; 1365 } 1366 1367 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1368 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1369 if (err) { 1370 device_printf(dev, 1371 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1372 __func__, (uintmax_t)size, err); 1373 goto fail_1; 1374 } 1375 1376 dma->idi_paddr = IF_BAD_DMA; 1377 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1378 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1379 if (err || dma->idi_paddr == IF_BAD_DMA) { 1380 device_printf(dev, 1381 "%s: bus_dmamap_load failed: %d\n", 1382 __func__, err); 1383 goto fail_2; 1384 } 1385 1386 dma->idi_size = size; 1387 return (0); 1388 1389 fail_2: 1390 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1391 fail_1: 1392 bus_dma_tag_destroy(dma->idi_tag); 1393 fail_0: 1394 dma->idi_tag = NULL; 1395 1396 return (err); 1397 } 1398 1399 int 1400 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1401 { 1402 if_shared_ctx_t sctx = ctx->ifc_sctx; 1403 1404 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1405 1406 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1407 } 1408 1409 int 1410 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1411 { 1412 int i, err; 1413 iflib_dma_info_t *dmaiter; 1414 1415 dmaiter = dmalist; 1416 for (i = 0; i < count; i++, dmaiter++) { 1417 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1418 break; 1419 } 1420 if (err) 1421 iflib_dma_free_multi(dmalist, i); 1422 return (err); 1423 } 1424 1425 void 1426 iflib_dma_free(iflib_dma_info_t dma) 1427 { 1428 if (dma->idi_tag == NULL) 1429 return; 1430 if (dma->idi_paddr != IF_BAD_DMA) { 1431 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1432 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1433 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1434 dma->idi_paddr = IF_BAD_DMA; 1435 } 1436 if (dma->idi_vaddr != NULL) { 1437 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1438 dma->idi_vaddr = NULL; 1439 } 1440 bus_dma_tag_destroy(dma->idi_tag); 1441 dma->idi_tag = NULL; 1442 } 1443 1444 void 1445 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1446 { 1447 int i; 1448 iflib_dma_info_t *dmaiter = dmalist; 1449 1450 for (i = 0; i < count; i++, dmaiter++) 1451 iflib_dma_free(*dmaiter); 1452 } 1453 1454 static int 1455 iflib_fast_intr(void *arg) 1456 { 1457 iflib_filter_info_t info = arg; 1458 struct grouptask *gtask = info->ifi_task; 1459 int result; 1460 1461 DBG_COUNTER_INC(fast_intrs); 1462 if (info->ifi_filter != NULL) { 1463 result = info->ifi_filter(info->ifi_filter_arg); 1464 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1465 return (result); 1466 } 1467 1468 GROUPTASK_ENQUEUE(gtask); 1469 return (FILTER_HANDLED); 1470 } 1471 1472 static int 1473 iflib_fast_intr_rxtx(void *arg) 1474 { 1475 iflib_filter_info_t info = arg; 1476 struct grouptask *gtask = info->ifi_task; 1477 if_ctx_t ctx; 1478 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1479 iflib_txq_t txq; 1480 void *sc; 1481 int i, cidx, result; 1482 qidx_t txqid; 1483 bool intr_enable, intr_legacy; 1484 1485 DBG_COUNTER_INC(fast_intrs); 1486 if (info->ifi_filter != NULL) { 1487 result = info->ifi_filter(info->ifi_filter_arg); 1488 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1489 return (result); 1490 } 1491 1492 ctx = rxq->ifr_ctx; 1493 sc = ctx->ifc_softc; 1494 intr_enable = false; 1495 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1496 MPASS(rxq->ifr_ntxqirq); 1497 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1498 txqid = rxq->ifr_txqid[i]; 1499 txq = &ctx->ifc_txqs[txqid]; 1500 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1501 BUS_DMASYNC_POSTREAD); 1502 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1503 if (intr_legacy) 1504 intr_enable = true; 1505 else 1506 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1507 continue; 1508 } 1509 GROUPTASK_ENQUEUE(&txq->ift_task); 1510 } 1511 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1512 cidx = rxq->ifr_cq_cidx; 1513 else 1514 cidx = rxq->ifr_fl[0].ifl_cidx; 1515 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1516 GROUPTASK_ENQUEUE(gtask); 1517 else { 1518 if (intr_legacy) 1519 intr_enable = true; 1520 else 1521 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1522 DBG_COUNTER_INC(rx_intr_enables); 1523 } 1524 if (intr_enable) 1525 IFDI_INTR_ENABLE(ctx); 1526 return (FILTER_HANDLED); 1527 } 1528 1529 static int 1530 iflib_fast_intr_ctx(void *arg) 1531 { 1532 iflib_filter_info_t info = arg; 1533 struct grouptask *gtask = info->ifi_task; 1534 int result; 1535 1536 DBG_COUNTER_INC(fast_intrs); 1537 if (info->ifi_filter != NULL) { 1538 result = info->ifi_filter(info->ifi_filter_arg); 1539 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1540 return (result); 1541 } 1542 1543 GROUPTASK_ENQUEUE(gtask); 1544 return (FILTER_HANDLED); 1545 } 1546 1547 static int 1548 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1549 driver_filter_t filter, driver_intr_t handler, void *arg, 1550 const char *name) 1551 { 1552 struct resource *res; 1553 void *tag = NULL; 1554 device_t dev = ctx->ifc_dev; 1555 int flags, i, rc; 1556 1557 flags = RF_ACTIVE; 1558 if (ctx->ifc_flags & IFC_LEGACY) 1559 flags |= RF_SHAREABLE; 1560 MPASS(rid < 512); 1561 i = rid; 1562 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1563 if (res == NULL) { 1564 device_printf(dev, 1565 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1566 return (ENOMEM); 1567 } 1568 irq->ii_res = res; 1569 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1570 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1571 filter, handler, arg, &tag); 1572 if (rc != 0) { 1573 device_printf(dev, 1574 "failed to setup interrupt for rid %d, name %s: %d\n", 1575 rid, name ? name : "unknown", rc); 1576 return (rc); 1577 } else if (name) 1578 bus_describe_intr(dev, res, tag, "%s", name); 1579 1580 irq->ii_tag = tag; 1581 return (0); 1582 } 1583 1584 /********************************************************************* 1585 * 1586 * Allocate DMA resources for TX buffers as well as memory for the TX 1587 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1588 * iflib_sw_tx_desc_array structure, storing all the information that 1589 * is needed to transmit a packet on the wire. This is called only 1590 * once at attach, setup is done every reset. 1591 * 1592 **********************************************************************/ 1593 static int 1594 iflib_txsd_alloc(iflib_txq_t txq) 1595 { 1596 if_ctx_t ctx = txq->ift_ctx; 1597 if_shared_ctx_t sctx = ctx->ifc_sctx; 1598 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1599 device_t dev = ctx->ifc_dev; 1600 bus_size_t tsomaxsize; 1601 int err, nsegments, ntsosegments; 1602 bool tso; 1603 1604 nsegments = scctx->isc_tx_nsegments; 1605 ntsosegments = scctx->isc_tx_tso_segments_max; 1606 tsomaxsize = scctx->isc_tx_tso_size_max; 1607 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1608 tsomaxsize += sizeof(struct ether_vlan_header); 1609 MPASS(scctx->isc_ntxd[0] > 0); 1610 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1611 MPASS(nsegments > 0); 1612 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1613 MPASS(ntsosegments > 0); 1614 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1615 } 1616 1617 /* 1618 * Set up DMA tags for TX buffers. 1619 */ 1620 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1621 1, 0, /* alignment, bounds */ 1622 BUS_SPACE_MAXADDR, /* lowaddr */ 1623 BUS_SPACE_MAXADDR, /* highaddr */ 1624 NULL, NULL, /* filter, filterarg */ 1625 sctx->isc_tx_maxsize, /* maxsize */ 1626 nsegments, /* nsegments */ 1627 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1628 0, /* flags */ 1629 NULL, /* lockfunc */ 1630 NULL, /* lockfuncarg */ 1631 &txq->ift_buf_tag))) { 1632 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1633 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1634 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1635 goto fail; 1636 } 1637 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1638 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1639 1, 0, /* alignment, bounds */ 1640 BUS_SPACE_MAXADDR, /* lowaddr */ 1641 BUS_SPACE_MAXADDR, /* highaddr */ 1642 NULL, NULL, /* filter, filterarg */ 1643 tsomaxsize, /* maxsize */ 1644 ntsosegments, /* nsegments */ 1645 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1646 0, /* flags */ 1647 NULL, /* lockfunc */ 1648 NULL, /* lockfuncarg */ 1649 &txq->ift_tso_buf_tag))) { 1650 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1651 err); 1652 goto fail; 1653 } 1654 1655 /* Allocate memory for the TX mbuf map. */ 1656 if (!(txq->ift_sds.ifsd_m = 1657 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1658 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1659 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1660 err = ENOMEM; 1661 goto fail; 1662 } 1663 1664 /* 1665 * Create the DMA maps for TX buffers. 1666 */ 1667 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1668 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1669 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1670 device_printf(dev, 1671 "Unable to allocate TX buffer DMA map memory\n"); 1672 err = ENOMEM; 1673 goto fail; 1674 } 1675 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1676 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1677 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1678 device_printf(dev, 1679 "Unable to allocate TSO TX buffer map memory\n"); 1680 err = ENOMEM; 1681 goto fail; 1682 } 1683 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1684 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1685 &txq->ift_sds.ifsd_map[i]); 1686 if (err != 0) { 1687 device_printf(dev, "Unable to create TX DMA map\n"); 1688 goto fail; 1689 } 1690 if (!tso) 1691 continue; 1692 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1693 &txq->ift_sds.ifsd_tso_map[i]); 1694 if (err != 0) { 1695 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1696 goto fail; 1697 } 1698 } 1699 return (0); 1700 fail: 1701 /* We free all, it handles case where we are in the middle */ 1702 iflib_tx_structures_free(ctx); 1703 return (err); 1704 } 1705 1706 static void 1707 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1708 { 1709 bus_dmamap_t map; 1710 1711 if (txq->ift_sds.ifsd_map != NULL) { 1712 map = txq->ift_sds.ifsd_map[i]; 1713 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1714 bus_dmamap_unload(txq->ift_buf_tag, map); 1715 bus_dmamap_destroy(txq->ift_buf_tag, map); 1716 txq->ift_sds.ifsd_map[i] = NULL; 1717 } 1718 1719 if (txq->ift_sds.ifsd_tso_map != NULL) { 1720 map = txq->ift_sds.ifsd_tso_map[i]; 1721 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1722 BUS_DMASYNC_POSTWRITE); 1723 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1724 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1725 txq->ift_sds.ifsd_tso_map[i] = NULL; 1726 } 1727 } 1728 1729 static void 1730 iflib_txq_destroy(iflib_txq_t txq) 1731 { 1732 if_ctx_t ctx = txq->ift_ctx; 1733 1734 for (int i = 0; i < txq->ift_size; i++) 1735 iflib_txsd_destroy(ctx, txq, i); 1736 1737 if (txq->ift_br != NULL) { 1738 ifmp_ring_free(txq->ift_br); 1739 txq->ift_br = NULL; 1740 } 1741 1742 mtx_destroy(&txq->ift_mtx); 1743 1744 if (txq->ift_sds.ifsd_map != NULL) { 1745 free(txq->ift_sds.ifsd_map, M_IFLIB); 1746 txq->ift_sds.ifsd_map = NULL; 1747 } 1748 if (txq->ift_sds.ifsd_tso_map != NULL) { 1749 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1750 txq->ift_sds.ifsd_tso_map = NULL; 1751 } 1752 if (txq->ift_sds.ifsd_m != NULL) { 1753 free(txq->ift_sds.ifsd_m, M_IFLIB); 1754 txq->ift_sds.ifsd_m = NULL; 1755 } 1756 if (txq->ift_buf_tag != NULL) { 1757 bus_dma_tag_destroy(txq->ift_buf_tag); 1758 txq->ift_buf_tag = NULL; 1759 } 1760 if (txq->ift_tso_buf_tag != NULL) { 1761 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1762 txq->ift_tso_buf_tag = NULL; 1763 } 1764 if (txq->ift_ifdi != NULL) { 1765 free(txq->ift_ifdi, M_IFLIB); 1766 } 1767 } 1768 1769 static void 1770 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1771 { 1772 struct mbuf **mp; 1773 1774 mp = &txq->ift_sds.ifsd_m[i]; 1775 if (*mp == NULL) 1776 return; 1777 1778 if (txq->ift_sds.ifsd_map != NULL) { 1779 bus_dmamap_sync(txq->ift_buf_tag, 1780 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1781 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1782 } 1783 if (txq->ift_sds.ifsd_tso_map != NULL) { 1784 bus_dmamap_sync(txq->ift_tso_buf_tag, 1785 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1786 bus_dmamap_unload(txq->ift_tso_buf_tag, 1787 txq->ift_sds.ifsd_tso_map[i]); 1788 } 1789 m_freem(*mp); 1790 DBG_COUNTER_INC(tx_frees); 1791 *mp = NULL; 1792 } 1793 1794 static int 1795 iflib_txq_setup(iflib_txq_t txq) 1796 { 1797 if_ctx_t ctx = txq->ift_ctx; 1798 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1799 if_shared_ctx_t sctx = ctx->ifc_sctx; 1800 iflib_dma_info_t di; 1801 int i; 1802 1803 /* Set number of descriptors available */ 1804 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1805 /* XXX make configurable */ 1806 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1807 1808 /* Reset indices */ 1809 txq->ift_cidx_processed = 0; 1810 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1811 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1812 1813 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1814 bzero((void *)di->idi_vaddr, di->idi_size); 1815 1816 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1817 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1818 bus_dmamap_sync(di->idi_tag, di->idi_map, 1819 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1820 return (0); 1821 } 1822 1823 /********************************************************************* 1824 * 1825 * Allocate DMA resources for RX buffers as well as memory for the RX 1826 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1827 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1828 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1829 * Since we use use one entry in iflib_sw_rx_desc_array per received 1830 * packet, the maximum number of entries we'll need is equal to the 1831 * number of hardware receive descriptors that we've allocated. 1832 * 1833 **********************************************************************/ 1834 static int 1835 iflib_rxsd_alloc(iflib_rxq_t rxq) 1836 { 1837 if_ctx_t ctx = rxq->ifr_ctx; 1838 if_shared_ctx_t sctx = ctx->ifc_sctx; 1839 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1840 device_t dev = ctx->ifc_dev; 1841 iflib_fl_t fl; 1842 int err; 1843 1844 MPASS(scctx->isc_nrxd[0] > 0); 1845 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1846 1847 fl = rxq->ifr_fl; 1848 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1849 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1850 /* Set up DMA tag for RX buffers. */ 1851 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1852 1, 0, /* alignment, bounds */ 1853 BUS_SPACE_MAXADDR, /* lowaddr */ 1854 BUS_SPACE_MAXADDR, /* highaddr */ 1855 NULL, NULL, /* filter, filterarg */ 1856 sctx->isc_rx_maxsize, /* maxsize */ 1857 sctx->isc_rx_nsegments, /* nsegments */ 1858 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1859 0, /* flags */ 1860 NULL, /* lockfunc */ 1861 NULL, /* lockarg */ 1862 &fl->ifl_buf_tag); 1863 if (err) { 1864 device_printf(dev, 1865 "Unable to allocate RX DMA tag: %d\n", err); 1866 goto fail; 1867 } 1868 1869 /* Allocate memory for the RX mbuf map. */ 1870 if (!(fl->ifl_sds.ifsd_m = 1871 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1872 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1873 device_printf(dev, 1874 "Unable to allocate RX mbuf map memory\n"); 1875 err = ENOMEM; 1876 goto fail; 1877 } 1878 1879 /* Allocate memory for the direct RX cluster pointer map. */ 1880 if (!(fl->ifl_sds.ifsd_cl = 1881 (caddr_t *) malloc(sizeof(caddr_t) * 1882 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1883 device_printf(dev, 1884 "Unable to allocate RX cluster map memory\n"); 1885 err = ENOMEM; 1886 goto fail; 1887 } 1888 1889 /* Allocate memory for the RX cluster bus address map. */ 1890 if (!(fl->ifl_sds.ifsd_ba = 1891 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1892 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1893 device_printf(dev, 1894 "Unable to allocate RX bus address map memory\n"); 1895 err = ENOMEM; 1896 goto fail; 1897 } 1898 1899 /* 1900 * Create the DMA maps for RX buffers. 1901 */ 1902 if (!(fl->ifl_sds.ifsd_map = 1903 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1904 device_printf(dev, 1905 "Unable to allocate RX buffer DMA map memory\n"); 1906 err = ENOMEM; 1907 goto fail; 1908 } 1909 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1910 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1911 &fl->ifl_sds.ifsd_map[i]); 1912 if (err != 0) { 1913 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1914 goto fail; 1915 } 1916 } 1917 } 1918 return (0); 1919 1920 fail: 1921 iflib_rx_structures_free(ctx); 1922 return (err); 1923 } 1924 1925 /* 1926 * Internal service routines 1927 */ 1928 1929 struct rxq_refill_cb_arg { 1930 int error; 1931 bus_dma_segment_t seg; 1932 int nseg; 1933 }; 1934 1935 static void 1936 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1937 { 1938 struct rxq_refill_cb_arg *cb_arg = arg; 1939 1940 cb_arg->error = error; 1941 cb_arg->seg = segs[0]; 1942 cb_arg->nseg = nseg; 1943 } 1944 1945 /** 1946 * iflib_fl_refill - refill an rxq free-buffer list 1947 * @ctx: the iflib context 1948 * @fl: the free list to refill 1949 * @count: the number of new buffers to allocate 1950 * 1951 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 1952 * The caller must assure that @count does not exceed the queue's capacity 1953 * minus one (since we always leave a descriptor unavailable). 1954 */ 1955 static uint8_t 1956 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1957 { 1958 struct if_rxd_update iru; 1959 struct rxq_refill_cb_arg cb_arg; 1960 struct mbuf *m; 1961 caddr_t cl, *sd_cl; 1962 struct mbuf **sd_m; 1963 bus_dmamap_t *sd_map; 1964 bus_addr_t bus_addr, *sd_ba; 1965 int err, frag_idx, i, idx, n, pidx; 1966 qidx_t credits; 1967 1968 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 1969 1970 sd_m = fl->ifl_sds.ifsd_m; 1971 sd_map = fl->ifl_sds.ifsd_map; 1972 sd_cl = fl->ifl_sds.ifsd_cl; 1973 sd_ba = fl->ifl_sds.ifsd_ba; 1974 pidx = fl->ifl_pidx; 1975 idx = pidx; 1976 frag_idx = fl->ifl_fragidx; 1977 credits = fl->ifl_credits; 1978 1979 i = 0; 1980 n = count; 1981 MPASS(n > 0); 1982 MPASS(credits + n <= fl->ifl_size); 1983 1984 if (pidx < fl->ifl_cidx) 1985 MPASS(pidx + n <= fl->ifl_cidx); 1986 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1987 MPASS(fl->ifl_gen == 0); 1988 if (pidx > fl->ifl_cidx) 1989 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1990 1991 DBG_COUNTER_INC(fl_refills); 1992 if (n > 8) 1993 DBG_COUNTER_INC(fl_refills_large); 1994 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1995 while (n-- > 0) { 1996 /* 1997 * We allocate an uninitialized mbuf + cluster, mbuf is 1998 * initialized after rx. 1999 * 2000 * If the cluster is still set then we know a minimum sized 2001 * packet was received 2002 */ 2003 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2004 &frag_idx); 2005 if (frag_idx < 0) 2006 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2007 MPASS(frag_idx >= 0); 2008 if ((cl = sd_cl[frag_idx]) == NULL) { 2009 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2010 if (__predict_false(cl == NULL)) 2011 break; 2012 2013 cb_arg.error = 0; 2014 MPASS(sd_map != NULL); 2015 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2016 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2017 BUS_DMA_NOWAIT); 2018 if (__predict_false(err != 0 || cb_arg.error)) { 2019 uma_zfree(fl->ifl_zone, cl); 2020 break; 2021 } 2022 2023 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2024 sd_cl[frag_idx] = cl; 2025 #if MEMORY_LOGGING 2026 fl->ifl_cl_enqueued++; 2027 #endif 2028 } else { 2029 bus_addr = sd_ba[frag_idx]; 2030 } 2031 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2032 BUS_DMASYNC_PREREAD); 2033 2034 if (sd_m[frag_idx] == NULL) { 2035 m = m_gethdr(M_NOWAIT, MT_NOINIT); 2036 if (__predict_false(m == NULL)) 2037 break; 2038 sd_m[frag_idx] = m; 2039 } 2040 bit_set(fl->ifl_rx_bitmap, frag_idx); 2041 #if MEMORY_LOGGING 2042 fl->ifl_m_enqueued++; 2043 #endif 2044 2045 DBG_COUNTER_INC(rx_allocs); 2046 fl->ifl_rxd_idxs[i] = frag_idx; 2047 fl->ifl_bus_addrs[i] = bus_addr; 2048 credits++; 2049 i++; 2050 MPASS(credits <= fl->ifl_size); 2051 if (++idx == fl->ifl_size) { 2052 #ifdef INVARIANTS 2053 fl->ifl_gen = 1; 2054 #endif 2055 idx = 0; 2056 } 2057 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2058 iru.iru_pidx = pidx; 2059 iru.iru_count = i; 2060 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2061 fl->ifl_pidx = idx; 2062 fl->ifl_credits = credits; 2063 pidx = idx; 2064 i = 0; 2065 } 2066 } 2067 2068 if (n < count - 1) { 2069 if (i != 0) { 2070 iru.iru_pidx = pidx; 2071 iru.iru_count = i; 2072 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2073 fl->ifl_pidx = idx; 2074 fl->ifl_credits = credits; 2075 } 2076 DBG_COUNTER_INC(rxd_flush); 2077 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2078 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2079 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2080 fl->ifl_id, fl->ifl_pidx); 2081 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2082 fl->ifl_fragidx = frag_idx + 1; 2083 if (fl->ifl_fragidx == fl->ifl_size) 2084 fl->ifl_fragidx = 0; 2085 } else { 2086 fl->ifl_fragidx = frag_idx; 2087 } 2088 } 2089 2090 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2091 } 2092 2093 static inline uint8_t 2094 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2095 { 2096 /* 2097 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2098 * This is important as it confuses most NICs. For instance, 2099 * Intel NICs have (per receive ring) RDH and RDT registers, where 2100 * RDH points to the next receive descriptor to be used by the NIC, 2101 * and RDT for the next receive descriptor to be published by the 2102 * driver to the NIC (RDT - 1 is thus the last valid one). 2103 * The condition RDH == RDT means no descriptors are available to 2104 * the NIC, and thus it would be ambiguous if it also meant that 2105 * all the descriptors are available to the NIC. 2106 */ 2107 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2108 #ifdef INVARIANTS 2109 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2110 #endif 2111 2112 MPASS(fl->ifl_credits <= fl->ifl_size); 2113 MPASS(reclaimable == delta); 2114 2115 if (reclaimable > 0) 2116 return (iflib_fl_refill(ctx, fl, reclaimable)); 2117 return (0); 2118 } 2119 2120 uint8_t 2121 iflib_in_detach(if_ctx_t ctx) 2122 { 2123 bool in_detach; 2124 2125 STATE_LOCK(ctx); 2126 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2127 STATE_UNLOCK(ctx); 2128 return (in_detach); 2129 } 2130 2131 static void 2132 iflib_fl_bufs_free(iflib_fl_t fl) 2133 { 2134 iflib_dma_info_t idi = fl->ifl_ifdi; 2135 bus_dmamap_t sd_map; 2136 uint32_t i; 2137 2138 for (i = 0; i < fl->ifl_size; i++) { 2139 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2140 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2141 2142 if (*sd_cl != NULL) { 2143 sd_map = fl->ifl_sds.ifsd_map[i]; 2144 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2145 BUS_DMASYNC_POSTREAD); 2146 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2147 uma_zfree(fl->ifl_zone, *sd_cl); 2148 *sd_cl = NULL; 2149 if (*sd_m != NULL) { 2150 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2151 uma_zfree(zone_mbuf, *sd_m); 2152 *sd_m = NULL; 2153 } 2154 } else { 2155 MPASS(*sd_m == NULL); 2156 } 2157 #if MEMORY_LOGGING 2158 fl->ifl_m_dequeued++; 2159 fl->ifl_cl_dequeued++; 2160 #endif 2161 } 2162 #ifdef INVARIANTS 2163 for (i = 0; i < fl->ifl_size; i++) { 2164 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2165 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2166 } 2167 #endif 2168 /* 2169 * Reset free list values 2170 */ 2171 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2172 bzero(idi->idi_vaddr, idi->idi_size); 2173 } 2174 2175 /********************************************************************* 2176 * 2177 * Initialize a free list and its buffers. 2178 * 2179 **********************************************************************/ 2180 static int 2181 iflib_fl_setup(iflib_fl_t fl) 2182 { 2183 iflib_rxq_t rxq = fl->ifl_rxq; 2184 if_ctx_t ctx = rxq->ifr_ctx; 2185 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2186 int qidx; 2187 2188 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2189 /* 2190 ** Free current RX buffer structs and their mbufs 2191 */ 2192 iflib_fl_bufs_free(fl); 2193 /* Now replenish the mbufs */ 2194 MPASS(fl->ifl_credits == 0); 2195 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2196 if (scctx->isc_rxd_buf_size[qidx] != 0) 2197 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2198 else 2199 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2200 /* 2201 * ifl_buf_size may be a driver-supplied value, so pull it up 2202 * to the selected mbuf size. 2203 */ 2204 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2205 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2206 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2207 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2208 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2209 2210 /* 2211 * Avoid pre-allocating zillions of clusters to an idle card 2212 * potentially speeding up attach. In any case make sure 2213 * to leave a descriptor unavailable. See the comment in 2214 * iflib_fl_refill_all(). 2215 */ 2216 MPASS(fl->ifl_size > 0); 2217 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2218 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2219 return (ENOBUFS); 2220 /* 2221 * handle failure 2222 */ 2223 MPASS(rxq != NULL); 2224 MPASS(fl->ifl_ifdi != NULL); 2225 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2226 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2227 return (0); 2228 } 2229 2230 /********************************************************************* 2231 * 2232 * Free receive ring data structures 2233 * 2234 **********************************************************************/ 2235 static void 2236 iflib_rx_sds_free(iflib_rxq_t rxq) 2237 { 2238 iflib_fl_t fl; 2239 int i, j; 2240 2241 if (rxq->ifr_fl != NULL) { 2242 for (i = 0; i < rxq->ifr_nfl; i++) { 2243 fl = &rxq->ifr_fl[i]; 2244 if (fl->ifl_buf_tag != NULL) { 2245 if (fl->ifl_sds.ifsd_map != NULL) { 2246 for (j = 0; j < fl->ifl_size; j++) { 2247 bus_dmamap_sync( 2248 fl->ifl_buf_tag, 2249 fl->ifl_sds.ifsd_map[j], 2250 BUS_DMASYNC_POSTREAD); 2251 bus_dmamap_unload( 2252 fl->ifl_buf_tag, 2253 fl->ifl_sds.ifsd_map[j]); 2254 bus_dmamap_destroy( 2255 fl->ifl_buf_tag, 2256 fl->ifl_sds.ifsd_map[j]); 2257 } 2258 } 2259 bus_dma_tag_destroy(fl->ifl_buf_tag); 2260 fl->ifl_buf_tag = NULL; 2261 } 2262 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2263 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2264 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2265 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2266 free(fl->ifl_rx_bitmap, M_IFLIB); 2267 fl->ifl_sds.ifsd_m = NULL; 2268 fl->ifl_sds.ifsd_cl = NULL; 2269 fl->ifl_sds.ifsd_ba = NULL; 2270 fl->ifl_sds.ifsd_map = NULL; 2271 fl->ifl_rx_bitmap = NULL; 2272 } 2273 free(rxq->ifr_fl, M_IFLIB); 2274 rxq->ifr_fl = NULL; 2275 free(rxq->ifr_ifdi, M_IFLIB); 2276 rxq->ifr_ifdi = NULL; 2277 rxq->ifr_cq_cidx = 0; 2278 } 2279 } 2280 2281 /* 2282 * Timer routine 2283 */ 2284 static void 2285 iflib_timer(void *arg) 2286 { 2287 iflib_txq_t txq = arg; 2288 if_ctx_t ctx = txq->ift_ctx; 2289 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2290 uint64_t this_tick = ticks; 2291 2292 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2293 return; 2294 2295 /* 2296 ** Check on the state of the TX queue(s), this 2297 ** can be done without the lock because its RO 2298 ** and the HUNG state will be static if set. 2299 */ 2300 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) { 2301 txq->ift_last_timer_tick = this_tick; 2302 IFDI_TIMER(ctx, txq->ift_id); 2303 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2304 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2305 (sctx->isc_pause_frames == 0))) 2306 goto hung; 2307 2308 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2309 ifmp_ring_is_stalled(txq->ift_br)) { 2310 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, 2311 ("queue can't be marked as hung if interface is down")); 2312 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2313 } 2314 txq->ift_cleaned_prev = txq->ift_cleaned; 2315 } 2316 /* handle any laggards */ 2317 if (txq->ift_db_pending) 2318 GROUPTASK_ENQUEUE(&txq->ift_task); 2319 2320 sctx->isc_pause_frames = 0; 2321 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2322 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, 2323 txq, txq->ift_timer.c_cpu); 2324 return; 2325 2326 hung: 2327 device_printf(ctx->ifc_dev, 2328 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2329 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2330 STATE_LOCK(ctx); 2331 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2332 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2333 iflib_admin_intr_deferred(ctx); 2334 STATE_UNLOCK(ctx); 2335 } 2336 2337 static uint16_t 2338 iflib_get_mbuf_size_for(unsigned int size) 2339 { 2340 2341 if (size <= MCLBYTES) 2342 return (MCLBYTES); 2343 else 2344 return (MJUMPAGESIZE); 2345 } 2346 2347 static void 2348 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2349 { 2350 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2351 2352 /* 2353 * XXX don't set the max_frame_size to larger 2354 * than the hardware can handle 2355 */ 2356 ctx->ifc_rx_mbuf_sz = 2357 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2358 } 2359 2360 uint32_t 2361 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2362 { 2363 2364 return (ctx->ifc_rx_mbuf_sz); 2365 } 2366 2367 static void 2368 iflib_init_locked(if_ctx_t ctx) 2369 { 2370 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2371 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2372 if_t ifp = ctx->ifc_ifp; 2373 iflib_fl_t fl; 2374 iflib_txq_t txq; 2375 iflib_rxq_t rxq; 2376 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2377 2378 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2379 IFDI_INTR_DISABLE(ctx); 2380 2381 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2382 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2383 /* Set hardware offload abilities */ 2384 if_clearhwassist(ifp); 2385 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2386 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2387 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2388 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2389 if (if_getcapenable(ifp) & IFCAP_TSO4) 2390 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2391 if (if_getcapenable(ifp) & IFCAP_TSO6) 2392 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2393 2394 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2395 CALLOUT_LOCK(txq); 2396 callout_stop(&txq->ift_timer); 2397 #ifdef DEV_NETMAP 2398 callout_stop(&txq->ift_netmap_timer); 2399 #endif /* DEV_NETMAP */ 2400 CALLOUT_UNLOCK(txq); 2401 iflib_netmap_txq_init(ctx, txq); 2402 } 2403 2404 /* 2405 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2406 * that drivers can use the value when setting up the hardware receive 2407 * buffers. 2408 */ 2409 iflib_calc_rx_mbuf_sz(ctx); 2410 2411 #ifdef INVARIANTS 2412 i = if_getdrvflags(ifp); 2413 #endif 2414 IFDI_INIT(ctx); 2415 MPASS(if_getdrvflags(ifp) == i); 2416 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2417 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2418 /* This rxq is in netmap mode. Skip normal init. */ 2419 continue; 2420 } 2421 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2422 if (iflib_fl_setup(fl)) { 2423 device_printf(ctx->ifc_dev, 2424 "setting up free list %d failed - " 2425 "check cluster settings\n", j); 2426 goto done; 2427 } 2428 } 2429 } 2430 done: 2431 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2432 IFDI_INTR_ENABLE(ctx); 2433 txq = ctx->ifc_txqs; 2434 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2435 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 2436 txq->ift_timer.c_cpu); 2437 } 2438 2439 static int 2440 iflib_media_change(if_t ifp) 2441 { 2442 if_ctx_t ctx = if_getsoftc(ifp); 2443 int err; 2444 2445 CTX_LOCK(ctx); 2446 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2447 iflib_init_locked(ctx); 2448 CTX_UNLOCK(ctx); 2449 return (err); 2450 } 2451 2452 static void 2453 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2454 { 2455 if_ctx_t ctx = if_getsoftc(ifp); 2456 2457 CTX_LOCK(ctx); 2458 IFDI_UPDATE_ADMIN_STATUS(ctx); 2459 IFDI_MEDIA_STATUS(ctx, ifmr); 2460 CTX_UNLOCK(ctx); 2461 } 2462 2463 void 2464 iflib_stop(if_ctx_t ctx) 2465 { 2466 iflib_txq_t txq = ctx->ifc_txqs; 2467 iflib_rxq_t rxq = ctx->ifc_rxqs; 2468 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2469 if_shared_ctx_t sctx = ctx->ifc_sctx; 2470 iflib_dma_info_t di; 2471 iflib_fl_t fl; 2472 int i, j; 2473 2474 /* Tell the stack that the interface is no longer active */ 2475 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2476 2477 IFDI_INTR_DISABLE(ctx); 2478 DELAY(1000); 2479 IFDI_STOP(ctx); 2480 DELAY(1000); 2481 2482 iflib_debug_reset(); 2483 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2484 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2485 /* make sure all transmitters have completed before proceeding XXX */ 2486 2487 CALLOUT_LOCK(txq); 2488 callout_stop(&txq->ift_timer); 2489 #ifdef DEV_NETMAP 2490 callout_stop(&txq->ift_netmap_timer); 2491 #endif /* DEV_NETMAP */ 2492 CALLOUT_UNLOCK(txq); 2493 2494 /* clean any enqueued buffers */ 2495 iflib_ifmp_purge(txq); 2496 /* Free any existing tx buffers. */ 2497 for (j = 0; j < txq->ift_size; j++) { 2498 iflib_txsd_free(ctx, txq, j); 2499 } 2500 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2501 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2502 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2503 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2504 txq->ift_pullups = 0; 2505 ifmp_ring_reset_stats(txq->ift_br); 2506 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2507 bzero((void *)di->idi_vaddr, di->idi_size); 2508 } 2509 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2510 /* make sure all transmitters have completed before proceeding XXX */ 2511 2512 rxq->ifr_cq_cidx = 0; 2513 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2514 bzero((void *)di->idi_vaddr, di->idi_size); 2515 /* also resets the free lists pidx/cidx */ 2516 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2517 iflib_fl_bufs_free(fl); 2518 } 2519 } 2520 2521 static inline caddr_t 2522 calc_next_rxd(iflib_fl_t fl, int cidx) 2523 { 2524 qidx_t size; 2525 int nrxd; 2526 caddr_t start, end, cur, next; 2527 2528 nrxd = fl->ifl_size; 2529 size = fl->ifl_rxd_size; 2530 start = fl->ifl_ifdi->idi_vaddr; 2531 2532 if (__predict_false(size == 0)) 2533 return (start); 2534 cur = start + size*cidx; 2535 end = start + size*nrxd; 2536 next = CACHE_PTR_NEXT(cur); 2537 return (next < end ? next : start); 2538 } 2539 2540 static inline void 2541 prefetch_pkts(iflib_fl_t fl, int cidx) 2542 { 2543 int nextptr; 2544 int nrxd = fl->ifl_size; 2545 caddr_t next_rxd; 2546 2547 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2548 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2549 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2550 next_rxd = calc_next_rxd(fl, cidx); 2551 prefetch(next_rxd); 2552 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2553 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2554 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2555 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2556 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2557 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2558 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2559 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2560 } 2561 2562 static struct mbuf * 2563 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2564 int *pf_rv, if_rxd_info_t ri) 2565 { 2566 bus_dmamap_t map; 2567 iflib_fl_t fl; 2568 caddr_t payload; 2569 struct mbuf *m; 2570 int flid, cidx, len, next; 2571 2572 map = NULL; 2573 flid = irf->irf_flid; 2574 cidx = irf->irf_idx; 2575 fl = &rxq->ifr_fl[flid]; 2576 sd->ifsd_fl = fl; 2577 m = fl->ifl_sds.ifsd_m[cidx]; 2578 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2579 fl->ifl_credits--; 2580 #if MEMORY_LOGGING 2581 fl->ifl_m_dequeued++; 2582 #endif 2583 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2584 prefetch_pkts(fl, cidx); 2585 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2586 prefetch(&fl->ifl_sds.ifsd_map[next]); 2587 map = fl->ifl_sds.ifsd_map[cidx]; 2588 2589 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2590 2591 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2592 irf->irf_len != 0) { 2593 payload = *sd->ifsd_cl; 2594 payload += ri->iri_pad; 2595 len = ri->iri_len - ri->iri_pad; 2596 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2597 len | PFIL_MEMPTR | PFIL_IN, NULL); 2598 switch (*pf_rv) { 2599 case PFIL_DROPPED: 2600 case PFIL_CONSUMED: 2601 /* 2602 * The filter ate it. Everything is recycled. 2603 */ 2604 m = NULL; 2605 unload = 0; 2606 break; 2607 case PFIL_REALLOCED: 2608 /* 2609 * The filter copied it. Everything is recycled. 2610 */ 2611 m = pfil_mem2mbuf(payload); 2612 unload = 0; 2613 break; 2614 case PFIL_PASS: 2615 /* 2616 * Filter said it was OK, so receive like 2617 * normal 2618 */ 2619 fl->ifl_sds.ifsd_m[cidx] = NULL; 2620 break; 2621 default: 2622 MPASS(0); 2623 } 2624 } else { 2625 fl->ifl_sds.ifsd_m[cidx] = NULL; 2626 *pf_rv = PFIL_PASS; 2627 } 2628 2629 if (unload && irf->irf_len != 0) 2630 bus_dmamap_unload(fl->ifl_buf_tag, map); 2631 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2632 if (__predict_false(fl->ifl_cidx == 0)) 2633 fl->ifl_gen = 0; 2634 bit_clear(fl->ifl_rx_bitmap, cidx); 2635 return (m); 2636 } 2637 2638 static struct mbuf * 2639 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2640 { 2641 struct mbuf *m, *mh, *mt; 2642 caddr_t cl; 2643 int *pf_rv_ptr, flags, i, padlen; 2644 bool consumed; 2645 2646 i = 0; 2647 mh = NULL; 2648 consumed = false; 2649 *pf_rv = PFIL_PASS; 2650 pf_rv_ptr = pf_rv; 2651 do { 2652 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2653 pf_rv_ptr, ri); 2654 2655 MPASS(*sd->ifsd_cl != NULL); 2656 2657 /* 2658 * Exclude zero-length frags & frags from 2659 * packets the filter has consumed or dropped 2660 */ 2661 if (ri->iri_frags[i].irf_len == 0 || consumed || 2662 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2663 if (mh == NULL) { 2664 /* everything saved here */ 2665 consumed = true; 2666 pf_rv_ptr = NULL; 2667 continue; 2668 } 2669 /* XXX we can save the cluster here, but not the mbuf */ 2670 m_init(m, M_NOWAIT, MT_DATA, 0); 2671 m_free(m); 2672 continue; 2673 } 2674 if (mh == NULL) { 2675 flags = M_PKTHDR|M_EXT; 2676 mh = mt = m; 2677 padlen = ri->iri_pad; 2678 } else { 2679 flags = M_EXT; 2680 mt->m_next = m; 2681 mt = m; 2682 /* assuming padding is only on the first fragment */ 2683 padlen = 0; 2684 } 2685 cl = *sd->ifsd_cl; 2686 *sd->ifsd_cl = NULL; 2687 2688 /* Can these two be made one ? */ 2689 m_init(m, M_NOWAIT, MT_DATA, flags); 2690 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2691 /* 2692 * These must follow m_init and m_cljset 2693 */ 2694 m->m_data += padlen; 2695 ri->iri_len -= padlen; 2696 m->m_len = ri->iri_frags[i].irf_len; 2697 } while (++i < ri->iri_nfrags); 2698 2699 return (mh); 2700 } 2701 2702 /* 2703 * Process one software descriptor 2704 */ 2705 static struct mbuf * 2706 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2707 { 2708 struct if_rxsd sd; 2709 struct mbuf *m; 2710 int pf_rv; 2711 2712 /* should I merge this back in now that the two paths are basically duplicated? */ 2713 if (ri->iri_nfrags == 1 && 2714 ri->iri_frags[0].irf_len != 0 && 2715 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2716 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2717 &pf_rv, ri); 2718 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2719 return (m); 2720 if (pf_rv == PFIL_PASS) { 2721 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2722 #ifndef __NO_STRICT_ALIGNMENT 2723 if (!IP_ALIGNED(m)) 2724 m->m_data += 2; 2725 #endif 2726 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2727 m->m_len = ri->iri_frags[0].irf_len; 2728 } 2729 } else { 2730 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2731 if (m == NULL) 2732 return (NULL); 2733 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2734 return (m); 2735 } 2736 m->m_pkthdr.len = ri->iri_len; 2737 m->m_pkthdr.rcvif = ri->iri_ifp; 2738 m->m_flags |= ri->iri_flags; 2739 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2740 m->m_pkthdr.flowid = ri->iri_flowid; 2741 M_HASHTYPE_SET(m, ri->iri_rsstype); 2742 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2743 m->m_pkthdr.csum_data = ri->iri_csum_data; 2744 return (m); 2745 } 2746 2747 #if defined(INET6) || defined(INET) 2748 static void 2749 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2750 { 2751 CURVNET_SET(lc->ifp->if_vnet); 2752 #if defined(INET6) 2753 *v6 = V_ip6_forwarding; 2754 #endif 2755 #if defined(INET) 2756 *v4 = V_ipforwarding; 2757 #endif 2758 CURVNET_RESTORE(); 2759 } 2760 2761 /* 2762 * Returns true if it's possible this packet could be LROed. 2763 * if it returns false, it is guaranteed that tcp_lro_rx() 2764 * would not return zero. 2765 */ 2766 static bool 2767 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2768 { 2769 struct ether_header *eh; 2770 2771 eh = mtod(m, struct ether_header *); 2772 switch (eh->ether_type) { 2773 #if defined(INET6) 2774 case htons(ETHERTYPE_IPV6): 2775 return (!v6_forwarding); 2776 #endif 2777 #if defined (INET) 2778 case htons(ETHERTYPE_IP): 2779 return (!v4_forwarding); 2780 #endif 2781 } 2782 2783 return false; 2784 } 2785 #else 2786 static void 2787 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2788 { 2789 } 2790 #endif 2791 2792 static void 2793 _task_fn_rx_watchdog(void *context) 2794 { 2795 iflib_rxq_t rxq = context; 2796 2797 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2798 } 2799 2800 static uint8_t 2801 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2802 { 2803 if_t ifp; 2804 if_ctx_t ctx = rxq->ifr_ctx; 2805 if_shared_ctx_t sctx = ctx->ifc_sctx; 2806 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2807 int avail, i; 2808 qidx_t *cidxp; 2809 struct if_rxd_info ri; 2810 int err, budget_left, rx_bytes, rx_pkts; 2811 iflib_fl_t fl; 2812 int lro_enabled; 2813 bool v4_forwarding, v6_forwarding, lro_possible; 2814 uint8_t retval = 0; 2815 2816 /* 2817 * XXX early demux data packets so that if_input processing only handles 2818 * acks in interrupt context 2819 */ 2820 struct mbuf *m, *mh, *mt, *mf; 2821 2822 NET_EPOCH_ASSERT(); 2823 2824 lro_possible = v4_forwarding = v6_forwarding = false; 2825 ifp = ctx->ifc_ifp; 2826 mh = mt = NULL; 2827 MPASS(budget > 0); 2828 rx_pkts = rx_bytes = 0; 2829 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2830 cidxp = &rxq->ifr_cq_cidx; 2831 else 2832 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2833 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2834 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2835 retval |= iflib_fl_refill_all(ctx, fl); 2836 DBG_COUNTER_INC(rx_unavail); 2837 return (retval); 2838 } 2839 2840 /* pfil needs the vnet to be set */ 2841 CURVNET_SET_QUIET(ifp->if_vnet); 2842 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2843 if (__predict_false(!CTX_ACTIVE(ctx))) { 2844 DBG_COUNTER_INC(rx_ctx_inactive); 2845 break; 2846 } 2847 /* 2848 * Reset client set fields to their default values 2849 */ 2850 rxd_info_zero(&ri); 2851 ri.iri_qsidx = rxq->ifr_id; 2852 ri.iri_cidx = *cidxp; 2853 ri.iri_ifp = ifp; 2854 ri.iri_frags = rxq->ifr_frags; 2855 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2856 2857 if (err) 2858 goto err; 2859 rx_pkts += 1; 2860 rx_bytes += ri.iri_len; 2861 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2862 *cidxp = ri.iri_cidx; 2863 /* Update our consumer index */ 2864 /* XXX NB: shurd - check if this is still safe */ 2865 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2866 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2867 /* was this only a completion queue message? */ 2868 if (__predict_false(ri.iri_nfrags == 0)) 2869 continue; 2870 } 2871 MPASS(ri.iri_nfrags != 0); 2872 MPASS(ri.iri_len != 0); 2873 2874 /* will advance the cidx on the corresponding free lists */ 2875 m = iflib_rxd_pkt_get(rxq, &ri); 2876 avail--; 2877 budget_left--; 2878 if (avail == 0 && budget_left) 2879 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2880 2881 if (__predict_false(m == NULL)) 2882 continue; 2883 2884 /* imm_pkt: -- cxgb */ 2885 if (mh == NULL) 2886 mh = mt = m; 2887 else { 2888 mt->m_nextpkt = m; 2889 mt = m; 2890 } 2891 } 2892 CURVNET_RESTORE(); 2893 /* make sure that we can refill faster than drain */ 2894 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2895 retval |= iflib_fl_refill_all(ctx, fl); 2896 2897 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2898 if (lro_enabled) 2899 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2900 mt = mf = NULL; 2901 while (mh != NULL) { 2902 m = mh; 2903 mh = mh->m_nextpkt; 2904 m->m_nextpkt = NULL; 2905 #ifndef __NO_STRICT_ALIGNMENT 2906 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2907 continue; 2908 #endif 2909 rx_bytes += m->m_pkthdr.len; 2910 rx_pkts++; 2911 #if defined(INET6) || defined(INET) 2912 if (lro_enabled) { 2913 if (!lro_possible) { 2914 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2915 if (lro_possible && mf != NULL) { 2916 ifp->if_input(ifp, mf); 2917 DBG_COUNTER_INC(rx_if_input); 2918 mt = mf = NULL; 2919 } 2920 } 2921 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2922 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2923 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2924 continue; 2925 } 2926 } 2927 #endif 2928 if (lro_possible) { 2929 ifp->if_input(ifp, m); 2930 DBG_COUNTER_INC(rx_if_input); 2931 continue; 2932 } 2933 2934 if (mf == NULL) 2935 mf = m; 2936 if (mt != NULL) 2937 mt->m_nextpkt = m; 2938 mt = m; 2939 } 2940 if (mf != NULL) { 2941 ifp->if_input(ifp, mf); 2942 DBG_COUNTER_INC(rx_if_input); 2943 } 2944 2945 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2946 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2947 2948 /* 2949 * Flush any outstanding LRO work 2950 */ 2951 #if defined(INET6) || defined(INET) 2952 tcp_lro_flush_all(&rxq->ifr_lc); 2953 #endif 2954 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 2955 retval |= IFLIB_RXEOF_MORE; 2956 return (retval); 2957 err: 2958 STATE_LOCK(ctx); 2959 ctx->ifc_flags |= IFC_DO_RESET; 2960 iflib_admin_intr_deferred(ctx); 2961 STATE_UNLOCK(ctx); 2962 return (0); 2963 } 2964 2965 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2966 static inline qidx_t 2967 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2968 { 2969 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2970 qidx_t minthresh = txq->ift_size / 8; 2971 if (in_use > 4*minthresh) 2972 return (notify_count); 2973 if (in_use > 2*minthresh) 2974 return (notify_count >> 1); 2975 if (in_use > minthresh) 2976 return (notify_count >> 3); 2977 return (0); 2978 } 2979 2980 static inline qidx_t 2981 txq_max_rs_deferred(iflib_txq_t txq) 2982 { 2983 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2984 qidx_t minthresh = txq->ift_size / 8; 2985 if (txq->ift_in_use > 4*minthresh) 2986 return (notify_count); 2987 if (txq->ift_in_use > 2*minthresh) 2988 return (notify_count >> 1); 2989 if (txq->ift_in_use > minthresh) 2990 return (notify_count >> 2); 2991 return (2); 2992 } 2993 2994 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2995 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2996 2997 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2998 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2999 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 3000 3001 /* forward compatibility for cxgb */ 3002 #define FIRST_QSET(ctx) 0 3003 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3004 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3005 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3006 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3007 3008 /* XXX we should be setting this to something other than zero */ 3009 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 3010 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3011 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3012 3013 static inline bool 3014 iflib_txd_db_check(iflib_txq_t txq, int ring) 3015 { 3016 if_ctx_t ctx = txq->ift_ctx; 3017 qidx_t dbval, max; 3018 3019 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use); 3020 3021 /* force || threshold exceeded || at the edge of the ring */ 3022 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2)) { 3023 3024 /* 3025 * 'npending' is used if the card's doorbell is in terms of the number of descriptors 3026 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the 3027 * producer index explicitly (INTC). 3028 */ 3029 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3030 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3031 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3032 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3033 3034 /* 3035 * Absent bugs there are zero packets pending so reset pending counts to zero. 3036 */ 3037 txq->ift_db_pending = txq->ift_npending = 0; 3038 return (true); 3039 } 3040 return (false); 3041 } 3042 3043 #ifdef PKT_DEBUG 3044 static void 3045 print_pkt(if_pkt_info_t pi) 3046 { 3047 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3048 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3049 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3050 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3051 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3052 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3053 } 3054 #endif 3055 3056 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3057 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3058 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3059 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3060 3061 static int 3062 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3063 { 3064 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3065 struct ether_vlan_header *eh; 3066 struct mbuf *m; 3067 3068 m = *mp; 3069 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3070 M_WRITABLE(m) == 0) { 3071 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3072 return (ENOMEM); 3073 } else { 3074 m_freem(*mp); 3075 DBG_COUNTER_INC(tx_frees); 3076 *mp = m; 3077 } 3078 } 3079 3080 /* 3081 * Determine where frame payload starts. 3082 * Jump over vlan headers if already present, 3083 * helpful for QinQ too. 3084 */ 3085 if (__predict_false(m->m_len < sizeof(*eh))) { 3086 txq->ift_pullups++; 3087 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3088 return (ENOMEM); 3089 } 3090 eh = mtod(m, struct ether_vlan_header *); 3091 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3092 pi->ipi_etype = ntohs(eh->evl_proto); 3093 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3094 } else { 3095 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3096 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3097 } 3098 3099 switch (pi->ipi_etype) { 3100 #ifdef INET 3101 case ETHERTYPE_IP: 3102 { 3103 struct mbuf *n; 3104 struct ip *ip = NULL; 3105 struct tcphdr *th = NULL; 3106 int minthlen; 3107 3108 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3109 if (__predict_false(m->m_len < minthlen)) { 3110 /* 3111 * if this code bloat is causing too much of a hit 3112 * move it to a separate function and mark it noinline 3113 */ 3114 if (m->m_len == pi->ipi_ehdrlen) { 3115 n = m->m_next; 3116 MPASS(n); 3117 if (n->m_len >= sizeof(*ip)) { 3118 ip = (struct ip *)n->m_data; 3119 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3120 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3121 } else { 3122 txq->ift_pullups++; 3123 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3124 return (ENOMEM); 3125 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3126 } 3127 } else { 3128 txq->ift_pullups++; 3129 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3130 return (ENOMEM); 3131 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3132 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3133 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3134 } 3135 } else { 3136 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3137 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3138 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3139 } 3140 pi->ipi_ip_hlen = ip->ip_hl << 2; 3141 pi->ipi_ipproto = ip->ip_p; 3142 pi->ipi_flags |= IPI_TX_IPV4; 3143 3144 /* TCP checksum offload may require TCP header length */ 3145 if (IS_TX_OFFLOAD4(pi)) { 3146 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3147 if (__predict_false(th == NULL)) { 3148 txq->ift_pullups++; 3149 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3150 return (ENOMEM); 3151 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3152 } 3153 pi->ipi_tcp_hflags = th->th_flags; 3154 pi->ipi_tcp_hlen = th->th_off << 2; 3155 pi->ipi_tcp_seq = th->th_seq; 3156 } 3157 if (IS_TSO4(pi)) { 3158 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3159 return (ENXIO); 3160 /* 3161 * TSO always requires hardware checksum offload. 3162 */ 3163 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3164 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3165 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3166 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3167 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3168 ip->ip_sum = 0; 3169 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3170 } 3171 } 3172 } 3173 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3174 ip->ip_sum = 0; 3175 3176 break; 3177 } 3178 #endif 3179 #ifdef INET6 3180 case ETHERTYPE_IPV6: 3181 { 3182 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3183 struct tcphdr *th; 3184 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3185 3186 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3187 txq->ift_pullups++; 3188 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3189 return (ENOMEM); 3190 } 3191 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3192 3193 /* XXX-BZ this will go badly in case of ext hdrs. */ 3194 pi->ipi_ipproto = ip6->ip6_nxt; 3195 pi->ipi_flags |= IPI_TX_IPV6; 3196 3197 /* TCP checksum offload may require TCP header length */ 3198 if (IS_TX_OFFLOAD6(pi)) { 3199 if (pi->ipi_ipproto == IPPROTO_TCP) { 3200 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3201 txq->ift_pullups++; 3202 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3203 return (ENOMEM); 3204 } 3205 pi->ipi_tcp_hflags = th->th_flags; 3206 pi->ipi_tcp_hlen = th->th_off << 2; 3207 pi->ipi_tcp_seq = th->th_seq; 3208 } 3209 if (IS_TSO6(pi)) { 3210 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3211 return (ENXIO); 3212 /* 3213 * TSO always requires hardware checksum offload. 3214 */ 3215 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3216 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3217 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3218 } 3219 } 3220 break; 3221 } 3222 #endif 3223 default: 3224 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3225 pi->ipi_ip_hlen = 0; 3226 break; 3227 } 3228 *mp = m; 3229 3230 return (0); 3231 } 3232 3233 /* 3234 * If dodgy hardware rejects the scatter gather chain we've handed it 3235 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3236 * m_defrag'd mbufs 3237 */ 3238 static __noinline struct mbuf * 3239 iflib_remove_mbuf(iflib_txq_t txq) 3240 { 3241 int ntxd, pidx; 3242 struct mbuf *m, **ifsd_m; 3243 3244 ifsd_m = txq->ift_sds.ifsd_m; 3245 ntxd = txq->ift_size; 3246 pidx = txq->ift_pidx & (ntxd - 1); 3247 ifsd_m = txq->ift_sds.ifsd_m; 3248 m = ifsd_m[pidx]; 3249 ifsd_m[pidx] = NULL; 3250 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3251 if (txq->ift_sds.ifsd_tso_map != NULL) 3252 bus_dmamap_unload(txq->ift_tso_buf_tag, 3253 txq->ift_sds.ifsd_tso_map[pidx]); 3254 #if MEMORY_LOGGING 3255 txq->ift_dequeued++; 3256 #endif 3257 return (m); 3258 } 3259 3260 static inline caddr_t 3261 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3262 { 3263 qidx_t size; 3264 int ntxd; 3265 caddr_t start, end, cur, next; 3266 3267 ntxd = txq->ift_size; 3268 size = txq->ift_txd_size[qid]; 3269 start = txq->ift_ifdi[qid].idi_vaddr; 3270 3271 if (__predict_false(size == 0)) 3272 return (start); 3273 cur = start + size*cidx; 3274 end = start + size*ntxd; 3275 next = CACHE_PTR_NEXT(cur); 3276 return (next < end ? next : start); 3277 } 3278 3279 /* 3280 * Pad an mbuf to ensure a minimum ethernet frame size. 3281 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3282 */ 3283 static __noinline int 3284 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3285 { 3286 /* 3287 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3288 * and ARP message is the smallest common payload I can think of 3289 */ 3290 static char pad[18]; /* just zeros */ 3291 int n; 3292 struct mbuf *new_head; 3293 3294 if (!M_WRITABLE(*m_head)) { 3295 new_head = m_dup(*m_head, M_NOWAIT); 3296 if (new_head == NULL) { 3297 m_freem(*m_head); 3298 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3299 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3300 DBG_COUNTER_INC(tx_frees); 3301 return ENOMEM; 3302 } 3303 m_freem(*m_head); 3304 *m_head = new_head; 3305 } 3306 3307 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3308 n > 0; n -= sizeof(pad)) 3309 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3310 break; 3311 3312 if (n > 0) { 3313 m_freem(*m_head); 3314 device_printf(dev, "cannot pad short frame\n"); 3315 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3316 DBG_COUNTER_INC(tx_frees); 3317 return (ENOBUFS); 3318 } 3319 3320 return 0; 3321 } 3322 3323 static int 3324 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3325 { 3326 if_ctx_t ctx; 3327 if_shared_ctx_t sctx; 3328 if_softc_ctx_t scctx; 3329 bus_dma_tag_t buf_tag; 3330 bus_dma_segment_t *segs; 3331 struct mbuf *m_head, **ifsd_m; 3332 void *next_txd; 3333 bus_dmamap_t map; 3334 struct if_pkt_info pi; 3335 int remap = 0; 3336 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3337 3338 ctx = txq->ift_ctx; 3339 sctx = ctx->ifc_sctx; 3340 scctx = &ctx->ifc_softc_ctx; 3341 segs = txq->ift_segs; 3342 ntxd = txq->ift_size; 3343 m_head = *m_headp; 3344 map = NULL; 3345 3346 /* 3347 * If we're doing TSO the next descriptor to clean may be quite far ahead 3348 */ 3349 cidx = txq->ift_cidx; 3350 pidx = txq->ift_pidx; 3351 if (ctx->ifc_flags & IFC_PREFETCH) { 3352 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3353 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3354 next_txd = calc_next_txd(txq, cidx, 0); 3355 prefetch(next_txd); 3356 } 3357 3358 /* prefetch the next cache line of mbuf pointers and flags */ 3359 prefetch(&txq->ift_sds.ifsd_m[next]); 3360 prefetch(&txq->ift_sds.ifsd_map[next]); 3361 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3362 } 3363 map = txq->ift_sds.ifsd_map[pidx]; 3364 ifsd_m = txq->ift_sds.ifsd_m; 3365 3366 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3367 buf_tag = txq->ift_tso_buf_tag; 3368 max_segs = scctx->isc_tx_tso_segments_max; 3369 map = txq->ift_sds.ifsd_tso_map[pidx]; 3370 MPASS(buf_tag != NULL); 3371 MPASS(max_segs > 0); 3372 } else { 3373 buf_tag = txq->ift_buf_tag; 3374 max_segs = scctx->isc_tx_nsegments; 3375 map = txq->ift_sds.ifsd_map[pidx]; 3376 } 3377 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3378 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3379 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3380 if (err) { 3381 DBG_COUNTER_INC(encap_txd_encap_fail); 3382 return err; 3383 } 3384 } 3385 m_head = *m_headp; 3386 3387 pkt_info_zero(&pi); 3388 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3389 pi.ipi_pidx = pidx; 3390 pi.ipi_qsidx = txq->ift_id; 3391 pi.ipi_len = m_head->m_pkthdr.len; 3392 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3393 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3394 3395 /* deliberate bitwise OR to make one condition */ 3396 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3397 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3398 DBG_COUNTER_INC(encap_txd_encap_fail); 3399 return (err); 3400 } 3401 m_head = *m_headp; 3402 } 3403 3404 retry: 3405 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3406 BUS_DMA_NOWAIT); 3407 defrag: 3408 if (__predict_false(err)) { 3409 switch (err) { 3410 case EFBIG: 3411 /* try collapse once and defrag once */ 3412 if (remap == 0) { 3413 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3414 /* try defrag if collapsing fails */ 3415 if (m_head == NULL) 3416 remap++; 3417 } 3418 if (remap == 1) { 3419 txq->ift_mbuf_defrag++; 3420 m_head = m_defrag(*m_headp, M_NOWAIT); 3421 } 3422 /* 3423 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3424 * failed to map an mbuf that was run through m_defrag 3425 */ 3426 MPASS(remap <= 1); 3427 if (__predict_false(m_head == NULL || remap > 1)) 3428 goto defrag_failed; 3429 remap++; 3430 *m_headp = m_head; 3431 goto retry; 3432 break; 3433 case ENOMEM: 3434 txq->ift_no_tx_dma_setup++; 3435 break; 3436 default: 3437 txq->ift_no_tx_dma_setup++; 3438 m_freem(*m_headp); 3439 DBG_COUNTER_INC(tx_frees); 3440 *m_headp = NULL; 3441 break; 3442 } 3443 txq->ift_map_failed++; 3444 DBG_COUNTER_INC(encap_load_mbuf_fail); 3445 DBG_COUNTER_INC(encap_txd_encap_fail); 3446 return (err); 3447 } 3448 ifsd_m[pidx] = m_head; 3449 /* 3450 * XXX assumes a 1 to 1 relationship between segments and 3451 * descriptors - this does not hold true on all drivers, e.g. 3452 * cxgb 3453 */ 3454 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3455 txq->ift_no_desc_avail++; 3456 bus_dmamap_unload(buf_tag, map); 3457 DBG_COUNTER_INC(encap_txq_avail_fail); 3458 DBG_COUNTER_INC(encap_txd_encap_fail); 3459 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3460 GROUPTASK_ENQUEUE(&txq->ift_task); 3461 return (ENOBUFS); 3462 } 3463 /* 3464 * On Intel cards we can greatly reduce the number of TX interrupts 3465 * we see by only setting report status on every Nth descriptor. 3466 * However, this also means that the driver will need to keep track 3467 * of the descriptors that RS was set on to check them for the DD bit. 3468 */ 3469 txq->ift_rs_pending += nsegs + 1; 3470 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3471 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3472 pi.ipi_flags |= IPI_TX_INTR; 3473 txq->ift_rs_pending = 0; 3474 } 3475 3476 pi.ipi_segs = segs; 3477 pi.ipi_nsegs = nsegs; 3478 3479 MPASS(pidx >= 0 && pidx < txq->ift_size); 3480 #ifdef PKT_DEBUG 3481 print_pkt(&pi); 3482 #endif 3483 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3484 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3485 DBG_COUNTER_INC(tx_encap); 3486 MPASS(pi.ipi_new_pidx < txq->ift_size); 3487 3488 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3489 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3490 ndesc += txq->ift_size; 3491 txq->ift_gen = 1; 3492 } 3493 /* 3494 * drivers can need as many as 3495 * two sentinels 3496 */ 3497 MPASS(ndesc <= pi.ipi_nsegs + 2); 3498 MPASS(pi.ipi_new_pidx != pidx); 3499 MPASS(ndesc > 0); 3500 txq->ift_in_use += ndesc; 3501 txq->ift_db_pending += ndesc; 3502 3503 /* 3504 * We update the last software descriptor again here because there may 3505 * be a sentinel and/or there may be more mbufs than segments 3506 */ 3507 txq->ift_pidx = pi.ipi_new_pidx; 3508 txq->ift_npending += pi.ipi_ndescs; 3509 } else { 3510 *m_headp = m_head = iflib_remove_mbuf(txq); 3511 if (err == EFBIG) { 3512 txq->ift_txd_encap_efbig++; 3513 if (remap < 2) { 3514 remap = 1; 3515 goto defrag; 3516 } 3517 } 3518 goto defrag_failed; 3519 } 3520 /* 3521 * err can't possibly be non-zero here, so we don't neet to test it 3522 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3523 */ 3524 return (err); 3525 3526 defrag_failed: 3527 txq->ift_mbuf_defrag_failed++; 3528 txq->ift_map_failed++; 3529 m_freem(*m_headp); 3530 DBG_COUNTER_INC(tx_frees); 3531 *m_headp = NULL; 3532 DBG_COUNTER_INC(encap_txd_encap_fail); 3533 return (ENOMEM); 3534 } 3535 3536 static void 3537 iflib_tx_desc_free(iflib_txq_t txq, int n) 3538 { 3539 uint32_t qsize, cidx, mask, gen; 3540 struct mbuf *m, **ifsd_m; 3541 bool do_prefetch; 3542 3543 cidx = txq->ift_cidx; 3544 gen = txq->ift_gen; 3545 qsize = txq->ift_size; 3546 mask = qsize-1; 3547 ifsd_m = txq->ift_sds.ifsd_m; 3548 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3549 3550 while (n-- > 0) { 3551 if (do_prefetch) { 3552 prefetch(ifsd_m[(cidx + 3) & mask]); 3553 prefetch(ifsd_m[(cidx + 4) & mask]); 3554 } 3555 if ((m = ifsd_m[cidx]) != NULL) { 3556 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3557 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3558 bus_dmamap_sync(txq->ift_tso_buf_tag, 3559 txq->ift_sds.ifsd_tso_map[cidx], 3560 BUS_DMASYNC_POSTWRITE); 3561 bus_dmamap_unload(txq->ift_tso_buf_tag, 3562 txq->ift_sds.ifsd_tso_map[cidx]); 3563 } else { 3564 bus_dmamap_sync(txq->ift_buf_tag, 3565 txq->ift_sds.ifsd_map[cidx], 3566 BUS_DMASYNC_POSTWRITE); 3567 bus_dmamap_unload(txq->ift_buf_tag, 3568 txq->ift_sds.ifsd_map[cidx]); 3569 } 3570 /* XXX we don't support any drivers that batch packets yet */ 3571 MPASS(m->m_nextpkt == NULL); 3572 m_freem(m); 3573 ifsd_m[cidx] = NULL; 3574 #if MEMORY_LOGGING 3575 txq->ift_dequeued++; 3576 #endif 3577 DBG_COUNTER_INC(tx_frees); 3578 } 3579 if (__predict_false(++cidx == qsize)) { 3580 cidx = 0; 3581 gen = 0; 3582 } 3583 } 3584 txq->ift_cidx = cidx; 3585 txq->ift_gen = gen; 3586 } 3587 3588 static __inline int 3589 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3590 { 3591 int reclaim; 3592 if_ctx_t ctx = txq->ift_ctx; 3593 3594 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3595 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3596 3597 /* 3598 * Need a rate-limiting check so that this isn't called every time 3599 */ 3600 iflib_tx_credits_update(ctx, txq); 3601 reclaim = DESC_RECLAIMABLE(txq); 3602 3603 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3604 #ifdef INVARIANTS 3605 if (iflib_verbose_debug) { 3606 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3607 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3608 reclaim, thresh); 3609 } 3610 #endif 3611 return (0); 3612 } 3613 iflib_tx_desc_free(txq, reclaim); 3614 txq->ift_cleaned += reclaim; 3615 txq->ift_in_use -= reclaim; 3616 3617 return (reclaim); 3618 } 3619 3620 static struct mbuf ** 3621 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3622 { 3623 int next, size; 3624 struct mbuf **items; 3625 3626 size = r->size; 3627 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3628 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3629 3630 prefetch(items[(cidx + offset) & (size-1)]); 3631 if (remaining > 1) { 3632 prefetch2cachelines(&items[next]); 3633 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3634 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3635 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3636 } 3637 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3638 } 3639 3640 static void 3641 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3642 { 3643 3644 ifmp_ring_check_drainage(txq->ift_br, budget); 3645 } 3646 3647 static uint32_t 3648 iflib_txq_can_drain(struct ifmp_ring *r) 3649 { 3650 iflib_txq_t txq = r->cookie; 3651 if_ctx_t ctx = txq->ift_ctx; 3652 3653 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3654 return (1); 3655 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3656 BUS_DMASYNC_POSTREAD); 3657 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3658 false)); 3659 } 3660 3661 static uint32_t 3662 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3663 { 3664 iflib_txq_t txq = r->cookie; 3665 if_ctx_t ctx = txq->ift_ctx; 3666 if_t ifp = ctx->ifc_ifp; 3667 struct mbuf *m, **mp; 3668 int avail, bytes_sent, skipped, count, err, i; 3669 int mcast_sent, pkt_sent, reclaimed; 3670 bool do_prefetch, rang, ring; 3671 3672 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3673 !LINK_ACTIVE(ctx))) { 3674 DBG_COUNTER_INC(txq_drain_notready); 3675 return (0); 3676 } 3677 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3678 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending); 3679 avail = IDXDIFF(pidx, cidx, r->size); 3680 3681 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3682 /* 3683 * The driver is unloading so we need to free all pending packets. 3684 */ 3685 DBG_COUNTER_INC(txq_drain_flushing); 3686 for (i = 0; i < avail; i++) { 3687 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3688 m_freem(r->items[(cidx + i) & (r->size-1)]); 3689 r->items[(cidx + i) & (r->size-1)] = NULL; 3690 } 3691 return (avail); 3692 } 3693 3694 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3695 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3696 CALLOUT_LOCK(txq); 3697 callout_stop(&txq->ift_timer); 3698 CALLOUT_UNLOCK(txq); 3699 DBG_COUNTER_INC(txq_drain_oactive); 3700 return (0); 3701 } 3702 3703 /* 3704 * If we've reclaimed any packets this queue cannot be hung. 3705 */ 3706 if (reclaimed) 3707 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3708 skipped = mcast_sent = bytes_sent = pkt_sent = 0; 3709 count = MIN(avail, TX_BATCH_SIZE); 3710 #ifdef INVARIANTS 3711 if (iflib_verbose_debug) 3712 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3713 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3714 #endif 3715 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3716 err = 0; 3717 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx) + 2; i++) { 3718 int rem = do_prefetch ? count - i : 0; 3719 3720 mp = _ring_peek_one(r, cidx, i, rem); 3721 MPASS(mp != NULL && *mp != NULL); 3722 3723 /* 3724 * Completion interrupts will use the address of the txq 3725 * as a sentinel to enqueue _something_ in order to acquire 3726 * the lock on the mp_ring (there's no direct lock call). 3727 * We obviously whave to check for these sentinel cases 3728 * and skip them. 3729 */ 3730 if (__predict_false(*mp == (struct mbuf *)txq)) { 3731 skipped++; 3732 continue; 3733 } 3734 err = iflib_encap(txq, mp); 3735 if (__predict_false(err)) { 3736 /* no room - bail out */ 3737 if (err == ENOBUFS) 3738 break; 3739 skipped++; 3740 /* we can't send this packet - skip it */ 3741 continue; 3742 } 3743 pkt_sent++; 3744 m = *mp; 3745 DBG_COUNTER_INC(tx_sent); 3746 bytes_sent += m->m_pkthdr.len; 3747 mcast_sent += !!(m->m_flags & M_MCAST); 3748 3749 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3750 break; 3751 ETHER_BPF_MTAP(ifp, m); 3752 rang = iflib_txd_db_check(txq, false); 3753 } 3754 3755 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3756 ring = rang ? false : (iflib_min_tx_latency | err); 3757 iflib_txd_db_check(txq, ring); 3758 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3759 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3760 if (mcast_sent) 3761 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3762 #ifdef INVARIANTS 3763 if (iflib_verbose_debug) 3764 printf("consumed=%d\n", skipped + pkt_sent); 3765 #endif 3766 return (skipped + pkt_sent); 3767 } 3768 3769 static uint32_t 3770 iflib_txq_drain_always(struct ifmp_ring *r) 3771 { 3772 return (1); 3773 } 3774 3775 static uint32_t 3776 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3777 { 3778 int i, avail; 3779 struct mbuf **mp; 3780 iflib_txq_t txq; 3781 3782 txq = r->cookie; 3783 3784 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3785 CALLOUT_LOCK(txq); 3786 callout_stop(&txq->ift_timer); 3787 CALLOUT_UNLOCK(txq); 3788 3789 avail = IDXDIFF(pidx, cidx, r->size); 3790 for (i = 0; i < avail; i++) { 3791 mp = _ring_peek_one(r, cidx, i, avail - i); 3792 if (__predict_false(*mp == (struct mbuf *)txq)) 3793 continue; 3794 m_freem(*mp); 3795 DBG_COUNTER_INC(tx_frees); 3796 } 3797 MPASS(ifmp_ring_is_stalled(r) == 0); 3798 return (avail); 3799 } 3800 3801 static void 3802 iflib_ifmp_purge(iflib_txq_t txq) 3803 { 3804 struct ifmp_ring *r; 3805 3806 r = txq->ift_br; 3807 r->drain = iflib_txq_drain_free; 3808 r->can_drain = iflib_txq_drain_always; 3809 3810 ifmp_ring_check_drainage(r, r->size); 3811 3812 r->drain = iflib_txq_drain; 3813 r->can_drain = iflib_txq_can_drain; 3814 } 3815 3816 static void 3817 _task_fn_tx(void *context) 3818 { 3819 iflib_txq_t txq = context; 3820 if_ctx_t ctx = txq->ift_ctx; 3821 if_t ifp = ctx->ifc_ifp; 3822 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3823 3824 #ifdef IFLIB_DIAGNOSTICS 3825 txq->ift_cpu_exec_count[curcpu]++; 3826 #endif 3827 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 3828 return; 3829 #ifdef DEV_NETMAP 3830 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 3831 netmap_tx_irq(ifp, txq->ift_id)) 3832 goto skip_ifmp; 3833 #endif 3834 #ifdef ALTQ 3835 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3836 iflib_altq_if_start(ifp); 3837 #endif 3838 if (txq->ift_db_pending) 3839 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3840 else if (!abdicate) 3841 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3842 /* 3843 * When abdicating, we always need to check drainage, not just when we don't enqueue 3844 */ 3845 if (abdicate) 3846 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3847 #ifdef DEV_NETMAP 3848 skip_ifmp: 3849 #endif 3850 if (ctx->ifc_flags & IFC_LEGACY) 3851 IFDI_INTR_ENABLE(ctx); 3852 else 3853 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3854 } 3855 3856 static void 3857 _task_fn_rx(void *context) 3858 { 3859 iflib_rxq_t rxq = context; 3860 if_ctx_t ctx = rxq->ifr_ctx; 3861 uint8_t more; 3862 uint16_t budget; 3863 #ifdef DEV_NETMAP 3864 u_int work = 0; 3865 int nmirq; 3866 #endif 3867 3868 #ifdef IFLIB_DIAGNOSTICS 3869 rxq->ifr_cpu_exec_count[curcpu]++; 3870 #endif 3871 DBG_COUNTER_INC(task_fn_rxs); 3872 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3873 return; 3874 #ifdef DEV_NETMAP 3875 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 3876 if (nmirq != NM_IRQ_PASS) { 3877 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 3878 goto skip_rxeof; 3879 } 3880 #endif 3881 budget = ctx->ifc_sysctl_rx_budget; 3882 if (budget == 0) 3883 budget = 16; /* XXX */ 3884 more = iflib_rxeof(rxq, budget); 3885 #ifdef DEV_NETMAP 3886 skip_rxeof: 3887 #endif 3888 if ((more & IFLIB_RXEOF_MORE) == 0) { 3889 if (ctx->ifc_flags & IFC_LEGACY) 3890 IFDI_INTR_ENABLE(ctx); 3891 else 3892 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3893 DBG_COUNTER_INC(rx_intr_enables); 3894 } 3895 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3896 return; 3897 3898 if (more & IFLIB_RXEOF_MORE) 3899 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3900 else if (more & IFLIB_RXEOF_EMPTY) 3901 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 3902 } 3903 3904 static void 3905 _task_fn_admin(void *context) 3906 { 3907 if_ctx_t ctx = context; 3908 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3909 iflib_txq_t txq; 3910 int i; 3911 bool oactive, running, do_reset, do_watchdog, in_detach; 3912 3913 STATE_LOCK(ctx); 3914 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3915 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3916 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3917 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3918 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3919 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3920 STATE_UNLOCK(ctx); 3921 3922 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3923 return; 3924 if (in_detach) 3925 return; 3926 3927 CTX_LOCK(ctx); 3928 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3929 CALLOUT_LOCK(txq); 3930 callout_stop(&txq->ift_timer); 3931 CALLOUT_UNLOCK(txq); 3932 } 3933 if (do_watchdog) { 3934 ctx->ifc_watchdog_events++; 3935 IFDI_WATCHDOG_RESET(ctx); 3936 } 3937 IFDI_UPDATE_ADMIN_STATUS(ctx); 3938 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3939 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 3940 txq->ift_timer.c_cpu); 3941 } 3942 IFDI_LINK_INTR_ENABLE(ctx); 3943 if (do_reset) 3944 iflib_if_init_locked(ctx); 3945 CTX_UNLOCK(ctx); 3946 3947 if (LINK_ACTIVE(ctx) == 0) 3948 return; 3949 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3950 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3951 } 3952 3953 static void 3954 _task_fn_iov(void *context) 3955 { 3956 if_ctx_t ctx = context; 3957 3958 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3959 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3960 return; 3961 3962 CTX_LOCK(ctx); 3963 IFDI_VFLR_HANDLE(ctx); 3964 CTX_UNLOCK(ctx); 3965 } 3966 3967 static int 3968 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3969 { 3970 int err; 3971 if_int_delay_info_t info; 3972 if_ctx_t ctx; 3973 3974 info = (if_int_delay_info_t)arg1; 3975 ctx = info->iidi_ctx; 3976 info->iidi_req = req; 3977 info->iidi_oidp = oidp; 3978 CTX_LOCK(ctx); 3979 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3980 CTX_UNLOCK(ctx); 3981 return (err); 3982 } 3983 3984 /********************************************************************* 3985 * 3986 * IFNET FUNCTIONS 3987 * 3988 **********************************************************************/ 3989 3990 static void 3991 iflib_if_init_locked(if_ctx_t ctx) 3992 { 3993 iflib_stop(ctx); 3994 iflib_init_locked(ctx); 3995 } 3996 3997 static void 3998 iflib_if_init(void *arg) 3999 { 4000 if_ctx_t ctx = arg; 4001 4002 CTX_LOCK(ctx); 4003 iflib_if_init_locked(ctx); 4004 CTX_UNLOCK(ctx); 4005 } 4006 4007 static int 4008 iflib_if_transmit(if_t ifp, struct mbuf *m) 4009 { 4010 if_ctx_t ctx = if_getsoftc(ifp); 4011 4012 iflib_txq_t txq; 4013 int err, qidx; 4014 int abdicate = ctx->ifc_sysctl_tx_abdicate; 4015 4016 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 4017 DBG_COUNTER_INC(tx_frees); 4018 m_freem(m); 4019 return (ENETDOWN); 4020 } 4021 4022 MPASS(m->m_nextpkt == NULL); 4023 /* ALTQ-enabled interfaces always use queue 0. */ 4024 qidx = 0; 4025 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 4026 qidx = QIDX(ctx, m); 4027 /* 4028 * XXX calculate buf_ring based on flowid (divvy up bits?) 4029 */ 4030 txq = &ctx->ifc_txqs[qidx]; 4031 4032 #ifdef DRIVER_BACKPRESSURE 4033 if (txq->ift_closed) { 4034 while (m != NULL) { 4035 next = m->m_nextpkt; 4036 m->m_nextpkt = NULL; 4037 m_freem(m); 4038 DBG_COUNTER_INC(tx_frees); 4039 m = next; 4040 } 4041 return (ENOBUFS); 4042 } 4043 #endif 4044 #ifdef notyet 4045 qidx = count = 0; 4046 mp = marr; 4047 next = m; 4048 do { 4049 count++; 4050 next = next->m_nextpkt; 4051 } while (next != NULL); 4052 4053 if (count > nitems(marr)) 4054 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4055 /* XXX check nextpkt */ 4056 m_freem(m); 4057 /* XXX simplify for now */ 4058 DBG_COUNTER_INC(tx_frees); 4059 return (ENOBUFS); 4060 } 4061 for (next = m, i = 0; next != NULL; i++) { 4062 mp[i] = next; 4063 next = next->m_nextpkt; 4064 mp[i]->m_nextpkt = NULL; 4065 } 4066 #endif 4067 DBG_COUNTER_INC(tx_seen); 4068 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4069 4070 if (abdicate) 4071 GROUPTASK_ENQUEUE(&txq->ift_task); 4072 if (err) { 4073 if (!abdicate) 4074 GROUPTASK_ENQUEUE(&txq->ift_task); 4075 /* support forthcoming later */ 4076 #ifdef DRIVER_BACKPRESSURE 4077 txq->ift_closed = TRUE; 4078 #endif 4079 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4080 m_freem(m); 4081 DBG_COUNTER_INC(tx_frees); 4082 } 4083 4084 return (err); 4085 } 4086 4087 #ifdef ALTQ 4088 /* 4089 * The overall approach to integrating iflib with ALTQ is to continue to use 4090 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4091 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4092 * is redundant/unnecessary, but doing so minimizes the amount of 4093 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4094 * redundantly queueing to an intermediate mp_ring is swamped by the 4095 * performance limitations inherent in using ALTQ. 4096 * 4097 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4098 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4099 * given interface. If ALTQ is enabled for an interface, then all 4100 * transmitted packets for that interface will be submitted to the ALTQ 4101 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4102 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4103 * update stats that the iflib machinery handles, and which is sensitve to 4104 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4105 * will be installed as the start routine for use by ALTQ facilities that 4106 * need to trigger queue drains on a scheduled basis. 4107 * 4108 */ 4109 static void 4110 iflib_altq_if_start(if_t ifp) 4111 { 4112 struct ifaltq *ifq = &ifp->if_snd; 4113 struct mbuf *m; 4114 4115 IFQ_LOCK(ifq); 4116 IFQ_DEQUEUE_NOLOCK(ifq, m); 4117 while (m != NULL) { 4118 iflib_if_transmit(ifp, m); 4119 IFQ_DEQUEUE_NOLOCK(ifq, m); 4120 } 4121 IFQ_UNLOCK(ifq); 4122 } 4123 4124 static int 4125 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4126 { 4127 int err; 4128 4129 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4130 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4131 if (err == 0) 4132 iflib_altq_if_start(ifp); 4133 } else 4134 err = iflib_if_transmit(ifp, m); 4135 4136 return (err); 4137 } 4138 #endif /* ALTQ */ 4139 4140 static void 4141 iflib_if_qflush(if_t ifp) 4142 { 4143 if_ctx_t ctx = if_getsoftc(ifp); 4144 iflib_txq_t txq = ctx->ifc_txqs; 4145 int i; 4146 4147 STATE_LOCK(ctx); 4148 ctx->ifc_flags |= IFC_QFLUSH; 4149 STATE_UNLOCK(ctx); 4150 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4151 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4152 iflib_txq_check_drain(txq, 0); 4153 STATE_LOCK(ctx); 4154 ctx->ifc_flags &= ~IFC_QFLUSH; 4155 STATE_UNLOCK(ctx); 4156 4157 /* 4158 * When ALTQ is enabled, this will also take care of purging the 4159 * ALTQ queue(s). 4160 */ 4161 if_qflush(ifp); 4162 } 4163 4164 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4165 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4166 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4167 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP) 4168 4169 static int 4170 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4171 { 4172 if_ctx_t ctx = if_getsoftc(ifp); 4173 struct ifreq *ifr = (struct ifreq *)data; 4174 #if defined(INET) || defined(INET6) 4175 struct ifaddr *ifa = (struct ifaddr *)data; 4176 #endif 4177 bool avoid_reset = false; 4178 int err = 0, reinit = 0, bits; 4179 4180 switch (command) { 4181 case SIOCSIFADDR: 4182 #ifdef INET 4183 if (ifa->ifa_addr->sa_family == AF_INET) 4184 avoid_reset = true; 4185 #endif 4186 #ifdef INET6 4187 if (ifa->ifa_addr->sa_family == AF_INET6) 4188 avoid_reset = true; 4189 #endif 4190 /* 4191 ** Calling init results in link renegotiation, 4192 ** so we avoid doing it when possible. 4193 */ 4194 if (avoid_reset) { 4195 if_setflagbits(ifp, IFF_UP,0); 4196 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4197 reinit = 1; 4198 #ifdef INET 4199 if (!(if_getflags(ifp) & IFF_NOARP)) 4200 arp_ifinit(ifp, ifa); 4201 #endif 4202 } else 4203 err = ether_ioctl(ifp, command, data); 4204 break; 4205 case SIOCSIFMTU: 4206 CTX_LOCK(ctx); 4207 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4208 CTX_UNLOCK(ctx); 4209 break; 4210 } 4211 bits = if_getdrvflags(ifp); 4212 /* stop the driver and free any clusters before proceeding */ 4213 iflib_stop(ctx); 4214 4215 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4216 STATE_LOCK(ctx); 4217 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4218 ctx->ifc_flags |= IFC_MULTISEG; 4219 else 4220 ctx->ifc_flags &= ~IFC_MULTISEG; 4221 STATE_UNLOCK(ctx); 4222 err = if_setmtu(ifp, ifr->ifr_mtu); 4223 } 4224 iflib_init_locked(ctx); 4225 STATE_LOCK(ctx); 4226 if_setdrvflags(ifp, bits); 4227 STATE_UNLOCK(ctx); 4228 CTX_UNLOCK(ctx); 4229 break; 4230 case SIOCSIFFLAGS: 4231 CTX_LOCK(ctx); 4232 if (if_getflags(ifp) & IFF_UP) { 4233 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4234 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4235 (IFF_PROMISC | IFF_ALLMULTI)) { 4236 CTX_UNLOCK(ctx); 4237 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4238 CTX_LOCK(ctx); 4239 } 4240 } else 4241 reinit = 1; 4242 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4243 iflib_stop(ctx); 4244 } 4245 ctx->ifc_if_flags = if_getflags(ifp); 4246 CTX_UNLOCK(ctx); 4247 break; 4248 case SIOCADDMULTI: 4249 case SIOCDELMULTI: 4250 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4251 CTX_LOCK(ctx); 4252 IFDI_INTR_DISABLE(ctx); 4253 IFDI_MULTI_SET(ctx); 4254 IFDI_INTR_ENABLE(ctx); 4255 CTX_UNLOCK(ctx); 4256 } 4257 break; 4258 case SIOCSIFMEDIA: 4259 CTX_LOCK(ctx); 4260 IFDI_MEDIA_SET(ctx); 4261 CTX_UNLOCK(ctx); 4262 /* FALLTHROUGH */ 4263 case SIOCGIFMEDIA: 4264 case SIOCGIFXMEDIA: 4265 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4266 break; 4267 case SIOCGI2C: 4268 { 4269 struct ifi2creq i2c; 4270 4271 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4272 if (err != 0) 4273 break; 4274 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4275 err = EINVAL; 4276 break; 4277 } 4278 if (i2c.len > sizeof(i2c.data)) { 4279 err = EINVAL; 4280 break; 4281 } 4282 4283 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4284 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4285 sizeof(i2c)); 4286 break; 4287 } 4288 case SIOCSIFCAP: 4289 { 4290 int mask, setmask, oldmask; 4291 4292 oldmask = if_getcapenable(ifp); 4293 mask = ifr->ifr_reqcap ^ oldmask; 4294 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP; 4295 setmask = 0; 4296 #ifdef TCP_OFFLOAD 4297 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4298 #endif 4299 setmask |= (mask & IFCAP_FLAGS); 4300 setmask |= (mask & IFCAP_WOL); 4301 4302 /* 4303 * If any RX csum has changed, change all the ones that 4304 * are supported by the driver. 4305 */ 4306 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4307 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4308 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4309 } 4310 4311 /* 4312 * want to ensure that traffic has stopped before we change any of the flags 4313 */ 4314 if (setmask) { 4315 CTX_LOCK(ctx); 4316 bits = if_getdrvflags(ifp); 4317 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4318 iflib_stop(ctx); 4319 STATE_LOCK(ctx); 4320 if_togglecapenable(ifp, setmask); 4321 STATE_UNLOCK(ctx); 4322 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4323 iflib_init_locked(ctx); 4324 STATE_LOCK(ctx); 4325 if_setdrvflags(ifp, bits); 4326 STATE_UNLOCK(ctx); 4327 CTX_UNLOCK(ctx); 4328 } 4329 if_vlancap(ifp); 4330 break; 4331 } 4332 case SIOCGPRIVATE_0: 4333 case SIOCSDRVSPEC: 4334 case SIOCGDRVSPEC: 4335 CTX_LOCK(ctx); 4336 err = IFDI_PRIV_IOCTL(ctx, command, data); 4337 CTX_UNLOCK(ctx); 4338 break; 4339 default: 4340 err = ether_ioctl(ifp, command, data); 4341 break; 4342 } 4343 if (reinit) 4344 iflib_if_init(ctx); 4345 return (err); 4346 } 4347 4348 static uint64_t 4349 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4350 { 4351 if_ctx_t ctx = if_getsoftc(ifp); 4352 4353 return (IFDI_GET_COUNTER(ctx, cnt)); 4354 } 4355 4356 /********************************************************************* 4357 * 4358 * OTHER FUNCTIONS EXPORTED TO THE STACK 4359 * 4360 **********************************************************************/ 4361 4362 static void 4363 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4364 { 4365 if_ctx_t ctx = if_getsoftc(ifp); 4366 4367 if ((void *)ctx != arg) 4368 return; 4369 4370 if ((vtag == 0) || (vtag > 4095)) 4371 return; 4372 4373 if (iflib_in_detach(ctx)) 4374 return; 4375 4376 CTX_LOCK(ctx); 4377 /* Driver may need all untagged packets to be flushed */ 4378 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4379 iflib_stop(ctx); 4380 IFDI_VLAN_REGISTER(ctx, vtag); 4381 /* Re-init to load the changes, if required */ 4382 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4383 iflib_init_locked(ctx); 4384 CTX_UNLOCK(ctx); 4385 } 4386 4387 static void 4388 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4389 { 4390 if_ctx_t ctx = if_getsoftc(ifp); 4391 4392 if ((void *)ctx != arg) 4393 return; 4394 4395 if ((vtag == 0) || (vtag > 4095)) 4396 return; 4397 4398 CTX_LOCK(ctx); 4399 /* Driver may need all tagged packets to be flushed */ 4400 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4401 iflib_stop(ctx); 4402 IFDI_VLAN_UNREGISTER(ctx, vtag); 4403 /* Re-init to load the changes, if required */ 4404 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4405 iflib_init_locked(ctx); 4406 CTX_UNLOCK(ctx); 4407 } 4408 4409 static void 4410 iflib_led_func(void *arg, int onoff) 4411 { 4412 if_ctx_t ctx = arg; 4413 4414 CTX_LOCK(ctx); 4415 IFDI_LED_FUNC(ctx, onoff); 4416 CTX_UNLOCK(ctx); 4417 } 4418 4419 /********************************************************************* 4420 * 4421 * BUS FUNCTION DEFINITIONS 4422 * 4423 **********************************************************************/ 4424 4425 int 4426 iflib_device_probe(device_t dev) 4427 { 4428 const pci_vendor_info_t *ent; 4429 if_shared_ctx_t sctx; 4430 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4431 uint16_t pci_vendor_id; 4432 4433 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4434 return (ENOTSUP); 4435 4436 pci_vendor_id = pci_get_vendor(dev); 4437 pci_device_id = pci_get_device(dev); 4438 pci_subvendor_id = pci_get_subvendor(dev); 4439 pci_subdevice_id = pci_get_subdevice(dev); 4440 pci_rev_id = pci_get_revid(dev); 4441 if (sctx->isc_parse_devinfo != NULL) 4442 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4443 4444 ent = sctx->isc_vendor_info; 4445 while (ent->pvi_vendor_id != 0) { 4446 if (pci_vendor_id != ent->pvi_vendor_id) { 4447 ent++; 4448 continue; 4449 } 4450 if ((pci_device_id == ent->pvi_device_id) && 4451 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4452 (ent->pvi_subvendor_id == 0)) && 4453 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4454 (ent->pvi_subdevice_id == 0)) && 4455 ((pci_rev_id == ent->pvi_rev_id) || 4456 (ent->pvi_rev_id == 0))) { 4457 device_set_desc_copy(dev, ent->pvi_name); 4458 /* this needs to be changed to zero if the bus probing code 4459 * ever stops re-probing on best match because the sctx 4460 * may have its values over written by register calls 4461 * in subsequent probes 4462 */ 4463 return (BUS_PROBE_DEFAULT); 4464 } 4465 ent++; 4466 } 4467 return (ENXIO); 4468 } 4469 4470 int 4471 iflib_device_probe_vendor(device_t dev) 4472 { 4473 int probe; 4474 4475 probe = iflib_device_probe(dev); 4476 if (probe == BUS_PROBE_DEFAULT) 4477 return (BUS_PROBE_VENDOR); 4478 else 4479 return (probe); 4480 } 4481 4482 static void 4483 iflib_reset_qvalues(if_ctx_t ctx) 4484 { 4485 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4486 if_shared_ctx_t sctx = ctx->ifc_sctx; 4487 device_t dev = ctx->ifc_dev; 4488 int i; 4489 4490 if (ctx->ifc_sysctl_ntxqs != 0) 4491 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4492 if (ctx->ifc_sysctl_nrxqs != 0) 4493 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4494 4495 for (i = 0; i < sctx->isc_ntxqs; i++) { 4496 if (ctx->ifc_sysctl_ntxds[i] != 0) 4497 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4498 else 4499 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4500 } 4501 4502 for (i = 0; i < sctx->isc_nrxqs; i++) { 4503 if (ctx->ifc_sysctl_nrxds[i] != 0) 4504 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4505 else 4506 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4507 } 4508 4509 for (i = 0; i < sctx->isc_nrxqs; i++) { 4510 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4511 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4512 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4513 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4514 } 4515 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4516 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4517 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4518 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4519 } 4520 if (!powerof2(scctx->isc_nrxd[i])) { 4521 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4522 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4523 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4524 } 4525 } 4526 4527 for (i = 0; i < sctx->isc_ntxqs; i++) { 4528 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4529 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4530 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4531 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4532 } 4533 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4534 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4535 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4536 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4537 } 4538 if (!powerof2(scctx->isc_ntxd[i])) { 4539 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4540 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4541 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4542 } 4543 } 4544 } 4545 4546 static void 4547 iflib_add_pfil(if_ctx_t ctx) 4548 { 4549 struct pfil_head *pfil; 4550 struct pfil_head_args pa; 4551 iflib_rxq_t rxq; 4552 int i; 4553 4554 pa.pa_version = PFIL_VERSION; 4555 pa.pa_flags = PFIL_IN; 4556 pa.pa_type = PFIL_TYPE_ETHERNET; 4557 pa.pa_headname = ctx->ifc_ifp->if_xname; 4558 pfil = pfil_head_register(&pa); 4559 4560 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4561 rxq->pfil = pfil; 4562 } 4563 } 4564 4565 static void 4566 iflib_rem_pfil(if_ctx_t ctx) 4567 { 4568 struct pfil_head *pfil; 4569 iflib_rxq_t rxq; 4570 int i; 4571 4572 rxq = ctx->ifc_rxqs; 4573 pfil = rxq->pfil; 4574 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4575 rxq->pfil = NULL; 4576 } 4577 pfil_head_unregister(pfil); 4578 } 4579 4580 static uint16_t 4581 get_ctx_core_offset(if_ctx_t ctx) 4582 { 4583 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4584 struct cpu_offset *op; 4585 uint16_t qc; 4586 uint16_t ret = ctx->ifc_sysctl_core_offset; 4587 4588 if (ret != CORE_OFFSET_UNSPECIFIED) 4589 return (ret); 4590 4591 if (ctx->ifc_sysctl_separate_txrx) 4592 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets; 4593 else 4594 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets); 4595 4596 mtx_lock(&cpu_offset_mtx); 4597 SLIST_FOREACH(op, &cpu_offsets, entries) { 4598 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4599 ret = op->offset; 4600 op->offset += qc; 4601 MPASS(op->refcount < UINT_MAX); 4602 op->refcount++; 4603 break; 4604 } 4605 } 4606 if (ret == CORE_OFFSET_UNSPECIFIED) { 4607 ret = 0; 4608 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4609 M_NOWAIT | M_ZERO); 4610 if (op == NULL) { 4611 device_printf(ctx->ifc_dev, 4612 "allocation for cpu offset failed.\n"); 4613 } else { 4614 op->offset = qc; 4615 op->refcount = 1; 4616 CPU_COPY(&ctx->ifc_cpus, &op->set); 4617 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4618 } 4619 } 4620 mtx_unlock(&cpu_offset_mtx); 4621 4622 return (ret); 4623 } 4624 4625 static void 4626 unref_ctx_core_offset(if_ctx_t ctx) 4627 { 4628 struct cpu_offset *op, *top; 4629 4630 mtx_lock(&cpu_offset_mtx); 4631 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4632 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4633 MPASS(op->refcount > 0); 4634 op->refcount--; 4635 if (op->refcount == 0) { 4636 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4637 free(op, M_IFLIB); 4638 } 4639 break; 4640 } 4641 } 4642 mtx_unlock(&cpu_offset_mtx); 4643 } 4644 4645 int 4646 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4647 { 4648 if_ctx_t ctx; 4649 if_t ifp; 4650 if_softc_ctx_t scctx; 4651 kobjop_desc_t kobj_desc; 4652 kobj_method_t *kobj_method; 4653 int err, msix, rid; 4654 int num_txd, num_rxd; 4655 4656 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4657 4658 if (sc == NULL) { 4659 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4660 device_set_softc(dev, ctx); 4661 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4662 } 4663 4664 ctx->ifc_sctx = sctx; 4665 ctx->ifc_dev = dev; 4666 ctx->ifc_softc = sc; 4667 4668 if ((err = iflib_register(ctx)) != 0) { 4669 device_printf(dev, "iflib_register failed %d\n", err); 4670 goto fail_ctx_free; 4671 } 4672 iflib_add_device_sysctl_pre(ctx); 4673 4674 scctx = &ctx->ifc_softc_ctx; 4675 ifp = ctx->ifc_ifp; 4676 4677 iflib_reset_qvalues(ctx); 4678 CTX_LOCK(ctx); 4679 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4680 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4681 goto fail_unlock; 4682 } 4683 _iflib_pre_assert(scctx); 4684 ctx->ifc_txrx = *scctx->isc_txrx; 4685 4686 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 4687 ctx->ifc_mediap = scctx->isc_media; 4688 4689 #ifdef INVARIANTS 4690 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4691 MPASS(scctx->isc_tx_csum_flags); 4692 #endif 4693 4694 if_setcapabilities(ifp, 4695 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP); 4696 if_setcapenable(ifp, 4697 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP); 4698 4699 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4700 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4701 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4702 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4703 4704 num_txd = iflib_num_tx_descs(ctx); 4705 num_rxd = iflib_num_rx_descs(ctx); 4706 4707 /* XXX change for per-queue sizes */ 4708 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4709 num_txd, num_rxd); 4710 4711 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 4712 scctx->isc_tx_nsegments = max(1, num_txd / 4713 MAX_SINGLE_PACKET_FRACTION); 4714 if (scctx->isc_tx_tso_segments_max > num_txd / 4715 MAX_SINGLE_PACKET_FRACTION) 4716 scctx->isc_tx_tso_segments_max = max(1, 4717 num_txd / MAX_SINGLE_PACKET_FRACTION); 4718 4719 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4720 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4721 /* 4722 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4723 * but some MACs do. 4724 */ 4725 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4726 IP_MAXPACKET)); 4727 /* 4728 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4729 * into account. In the worst case, each of these calls will 4730 * add another mbuf and, thus, the requirement for another DMA 4731 * segment. So for best performance, it doesn't make sense to 4732 * advertize a maximum of TSO segments that typically will 4733 * require defragmentation in iflib_encap(). 4734 */ 4735 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4736 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4737 } 4738 if (scctx->isc_rss_table_size == 0) 4739 scctx->isc_rss_table_size = 64; 4740 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4741 4742 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4743 /* XXX format name */ 4744 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4745 NULL, NULL, "admin"); 4746 4747 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4748 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4749 device_printf(dev, "Unable to fetch CPU list\n"); 4750 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4751 } 4752 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4753 4754 /* 4755 ** Now set up MSI or MSI-X, should return us the number of supported 4756 ** vectors (will be 1 for a legacy interrupt and MSI). 4757 */ 4758 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4759 msix = scctx->isc_vectors; 4760 } else if (scctx->isc_msix_bar != 0) 4761 /* 4762 * The simple fact that isc_msix_bar is not 0 does not mean we 4763 * we have a good value there that is known to work. 4764 */ 4765 msix = iflib_msix_init(ctx); 4766 else { 4767 scctx->isc_vectors = 1; 4768 scctx->isc_ntxqsets = 1; 4769 scctx->isc_nrxqsets = 1; 4770 scctx->isc_intr = IFLIB_INTR_LEGACY; 4771 msix = 0; 4772 } 4773 /* Get memory for the station queues */ 4774 if ((err = iflib_queues_alloc(ctx))) { 4775 device_printf(dev, "Unable to allocate queue memory\n"); 4776 goto fail_intr_free; 4777 } 4778 4779 if ((err = iflib_qset_structures_setup(ctx))) 4780 goto fail_queues; 4781 4782 /* 4783 * Now that we know how many queues there are, get the core offset. 4784 */ 4785 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 4786 4787 if (msix > 1) { 4788 /* 4789 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 4790 * aren't the default NULL implementation. 4791 */ 4792 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 4793 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4794 kobj_desc); 4795 if (kobj_method == &kobj_desc->deflt) { 4796 device_printf(dev, 4797 "MSI-X requires ifdi_rx_queue_intr_enable method"); 4798 err = EOPNOTSUPP; 4799 goto fail_queues; 4800 } 4801 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 4802 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4803 kobj_desc); 4804 if (kobj_method == &kobj_desc->deflt) { 4805 device_printf(dev, 4806 "MSI-X requires ifdi_tx_queue_intr_enable method"); 4807 err = EOPNOTSUPP; 4808 goto fail_queues; 4809 } 4810 4811 /* 4812 * Assign the MSI-X vectors. 4813 * Note that the default NULL ifdi_msix_intr_assign method will 4814 * fail here, too. 4815 */ 4816 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 4817 if (err != 0) { 4818 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 4819 err); 4820 goto fail_queues; 4821 } 4822 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 4823 rid = 0; 4824 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4825 MPASS(msix == 1); 4826 rid = 1; 4827 } 4828 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4829 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4830 goto fail_queues; 4831 } 4832 } else { 4833 device_printf(dev, 4834 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 4835 err = ENODEV; 4836 goto fail_intr_free; 4837 } 4838 4839 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4840 4841 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4842 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4843 goto fail_detach; 4844 } 4845 4846 /* 4847 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4848 * This must appear after the call to ether_ifattach() because 4849 * ether_ifattach() sets if_hdrlen to the default value. 4850 */ 4851 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4852 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4853 4854 if ((err = iflib_netmap_attach(ctx))) { 4855 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4856 goto fail_detach; 4857 } 4858 *ctxp = ctx; 4859 4860 DEBUGNET_SET(ctx->ifc_ifp, iflib); 4861 4862 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4863 iflib_add_device_sysctl_post(ctx); 4864 iflib_add_pfil(ctx); 4865 ctx->ifc_flags |= IFC_INIT_DONE; 4866 CTX_UNLOCK(ctx); 4867 4868 return (0); 4869 4870 fail_detach: 4871 ether_ifdetach(ctx->ifc_ifp); 4872 fail_intr_free: 4873 iflib_free_intr_mem(ctx); 4874 fail_queues: 4875 iflib_tx_structures_free(ctx); 4876 iflib_rx_structures_free(ctx); 4877 iflib_tqg_detach(ctx); 4878 IFDI_DETACH(ctx); 4879 fail_unlock: 4880 CTX_UNLOCK(ctx); 4881 iflib_deregister(ctx); 4882 fail_ctx_free: 4883 device_set_softc(ctx->ifc_dev, NULL); 4884 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4885 free(ctx->ifc_softc, M_IFLIB); 4886 free(ctx, M_IFLIB); 4887 return (err); 4888 } 4889 4890 int 4891 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4892 struct iflib_cloneattach_ctx *clctx) 4893 { 4894 int num_txd, num_rxd; 4895 int err; 4896 if_ctx_t ctx; 4897 if_t ifp; 4898 if_softc_ctx_t scctx; 4899 int i; 4900 void *sc; 4901 4902 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4903 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4904 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4905 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4906 ctx->ifc_flags |= IFC_PSEUDO; 4907 4908 ctx->ifc_sctx = sctx; 4909 ctx->ifc_softc = sc; 4910 ctx->ifc_dev = dev; 4911 4912 if ((err = iflib_register(ctx)) != 0) { 4913 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4914 goto fail_ctx_free; 4915 } 4916 iflib_add_device_sysctl_pre(ctx); 4917 4918 scctx = &ctx->ifc_softc_ctx; 4919 ifp = ctx->ifc_ifp; 4920 4921 iflib_reset_qvalues(ctx); 4922 CTX_LOCK(ctx); 4923 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4924 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4925 goto fail_unlock; 4926 } 4927 if (sctx->isc_flags & IFLIB_GEN_MAC) 4928 ether_gen_addr(ifp, &ctx->ifc_mac); 4929 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4930 clctx->cc_params)) != 0) { 4931 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4932 goto fail_unlock; 4933 } 4934 #ifdef INVARIANTS 4935 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4936 MPASS(scctx->isc_tx_csum_flags); 4937 #endif 4938 4939 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4940 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4941 4942 ifp->if_flags |= IFF_NOGROUP; 4943 if (sctx->isc_flags & IFLIB_PSEUDO) { 4944 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4945 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4946 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) { 4947 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4948 } else { 4949 if_attach(ctx->ifc_ifp); 4950 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t)); 4951 } 4952 4953 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4954 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4955 goto fail_detach; 4956 } 4957 *ctxp = ctx; 4958 4959 /* 4960 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4961 * This must appear after the call to ether_ifattach() because 4962 * ether_ifattach() sets if_hdrlen to the default value. 4963 */ 4964 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4965 if_setifheaderlen(ifp, 4966 sizeof(struct ether_vlan_header)); 4967 4968 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4969 iflib_add_device_sysctl_post(ctx); 4970 ctx->ifc_flags |= IFC_INIT_DONE; 4971 CTX_UNLOCK(ctx); 4972 return (0); 4973 } 4974 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4975 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4976 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4977 4978 _iflib_pre_assert(scctx); 4979 ctx->ifc_txrx = *scctx->isc_txrx; 4980 4981 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4982 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4983 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4984 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4985 4986 num_txd = iflib_num_tx_descs(ctx); 4987 num_rxd = iflib_num_rx_descs(ctx); 4988 4989 /* XXX change for per-queue sizes */ 4990 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4991 num_txd, num_rxd); 4992 4993 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 4994 scctx->isc_tx_nsegments = max(1, num_txd / 4995 MAX_SINGLE_PACKET_FRACTION); 4996 if (scctx->isc_tx_tso_segments_max > num_txd / 4997 MAX_SINGLE_PACKET_FRACTION) 4998 scctx->isc_tx_tso_segments_max = max(1, 4999 num_txd / MAX_SINGLE_PACKET_FRACTION); 5000 5001 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5002 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5003 /* 5004 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5005 * but some MACs do. 5006 */ 5007 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5008 IP_MAXPACKET)); 5009 /* 5010 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5011 * into account. In the worst case, each of these calls will 5012 * add another mbuf and, thus, the requirement for another DMA 5013 * segment. So for best performance, it doesn't make sense to 5014 * advertize a maximum of TSO segments that typically will 5015 * require defragmentation in iflib_encap(). 5016 */ 5017 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5018 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5019 } 5020 if (scctx->isc_rss_table_size == 0) 5021 scctx->isc_rss_table_size = 64; 5022 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5023 5024 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5025 /* XXX format name */ 5026 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5027 NULL, NULL, "admin"); 5028 5029 /* XXX --- can support > 1 -- but keep it simple for now */ 5030 scctx->isc_intr = IFLIB_INTR_LEGACY; 5031 5032 /* Get memory for the station queues */ 5033 if ((err = iflib_queues_alloc(ctx))) { 5034 device_printf(dev, "Unable to allocate queue memory\n"); 5035 goto fail_iflib_detach; 5036 } 5037 5038 if ((err = iflib_qset_structures_setup(ctx))) { 5039 device_printf(dev, "qset structure setup failed %d\n", err); 5040 goto fail_queues; 5041 } 5042 5043 /* 5044 * XXX What if anything do we want to do about interrupts? 5045 */ 5046 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5047 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5048 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5049 goto fail_detach; 5050 } 5051 5052 /* 5053 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5054 * This must appear after the call to ether_ifattach() because 5055 * ether_ifattach() sets if_hdrlen to the default value. 5056 */ 5057 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5058 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5059 5060 /* XXX handle more than one queue */ 5061 for (i = 0; i < scctx->isc_nrxqsets; i++) 5062 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 5063 5064 *ctxp = ctx; 5065 5066 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5067 iflib_add_device_sysctl_post(ctx); 5068 ctx->ifc_flags |= IFC_INIT_DONE; 5069 CTX_UNLOCK(ctx); 5070 5071 return (0); 5072 fail_detach: 5073 ether_ifdetach(ctx->ifc_ifp); 5074 fail_queues: 5075 iflib_tx_structures_free(ctx); 5076 iflib_rx_structures_free(ctx); 5077 iflib_tqg_detach(ctx); 5078 fail_iflib_detach: 5079 IFDI_DETACH(ctx); 5080 fail_unlock: 5081 CTX_UNLOCK(ctx); 5082 iflib_deregister(ctx); 5083 fail_ctx_free: 5084 free(ctx->ifc_softc, M_IFLIB); 5085 free(ctx, M_IFLIB); 5086 return (err); 5087 } 5088 5089 int 5090 iflib_pseudo_deregister(if_ctx_t ctx) 5091 { 5092 if_t ifp = ctx->ifc_ifp; 5093 if_shared_ctx_t sctx = ctx->ifc_sctx; 5094 5095 /* Unregister VLAN event handlers early */ 5096 iflib_unregister_vlan_handlers(ctx); 5097 5098 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5099 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) { 5100 bpfdetach(ifp); 5101 if_detach(ifp); 5102 } else { 5103 ether_ifdetach(ifp); 5104 } 5105 5106 iflib_tqg_detach(ctx); 5107 iflib_tx_structures_free(ctx); 5108 iflib_rx_structures_free(ctx); 5109 5110 iflib_deregister(ctx); 5111 5112 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5113 free(ctx->ifc_softc, M_IFLIB); 5114 free(ctx, M_IFLIB); 5115 return (0); 5116 } 5117 5118 int 5119 iflib_device_attach(device_t dev) 5120 { 5121 if_ctx_t ctx; 5122 if_shared_ctx_t sctx; 5123 5124 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5125 return (ENOTSUP); 5126 5127 pci_enable_busmaster(dev); 5128 5129 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5130 } 5131 5132 int 5133 iflib_device_deregister(if_ctx_t ctx) 5134 { 5135 if_t ifp = ctx->ifc_ifp; 5136 device_t dev = ctx->ifc_dev; 5137 5138 /* Make sure VLANS are not using driver */ 5139 if (if_vlantrunkinuse(ifp)) { 5140 device_printf(dev, "Vlan in use, detach first\n"); 5141 return (EBUSY); 5142 } 5143 #ifdef PCI_IOV 5144 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5145 device_printf(dev, "SR-IOV in use; detach first.\n"); 5146 return (EBUSY); 5147 } 5148 #endif 5149 5150 STATE_LOCK(ctx); 5151 ctx->ifc_flags |= IFC_IN_DETACH; 5152 STATE_UNLOCK(ctx); 5153 5154 /* Unregister VLAN handlers before calling iflib_stop() */ 5155 iflib_unregister_vlan_handlers(ctx); 5156 5157 iflib_netmap_detach(ifp); 5158 ether_ifdetach(ifp); 5159 5160 CTX_LOCK(ctx); 5161 iflib_stop(ctx); 5162 CTX_UNLOCK(ctx); 5163 5164 iflib_rem_pfil(ctx); 5165 if (ctx->ifc_led_dev != NULL) 5166 led_destroy(ctx->ifc_led_dev); 5167 5168 iflib_tqg_detach(ctx); 5169 CTX_LOCK(ctx); 5170 IFDI_DETACH(ctx); 5171 CTX_UNLOCK(ctx); 5172 5173 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5174 iflib_free_intr_mem(ctx); 5175 5176 bus_generic_detach(dev); 5177 5178 iflib_tx_structures_free(ctx); 5179 iflib_rx_structures_free(ctx); 5180 5181 iflib_deregister(ctx); 5182 5183 device_set_softc(ctx->ifc_dev, NULL); 5184 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5185 free(ctx->ifc_softc, M_IFLIB); 5186 unref_ctx_core_offset(ctx); 5187 free(ctx, M_IFLIB); 5188 return (0); 5189 } 5190 5191 static void 5192 iflib_tqg_detach(if_ctx_t ctx) 5193 { 5194 iflib_txq_t txq; 5195 iflib_rxq_t rxq; 5196 int i; 5197 struct taskqgroup *tqg; 5198 5199 /* XXX drain any dependent tasks */ 5200 tqg = qgroup_if_io_tqg; 5201 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5202 callout_drain(&txq->ift_timer); 5203 #ifdef DEV_NETMAP 5204 callout_drain(&txq->ift_netmap_timer); 5205 #endif /* DEV_NETMAP */ 5206 if (txq->ift_task.gt_uniq != NULL) 5207 taskqgroup_detach(tqg, &txq->ift_task); 5208 } 5209 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5210 if (rxq->ifr_task.gt_uniq != NULL) 5211 taskqgroup_detach(tqg, &rxq->ifr_task); 5212 } 5213 tqg = qgroup_if_config_tqg; 5214 if (ctx->ifc_admin_task.gt_uniq != NULL) 5215 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5216 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5217 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5218 } 5219 5220 static void 5221 iflib_free_intr_mem(if_ctx_t ctx) 5222 { 5223 5224 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5225 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5226 } 5227 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5228 pci_release_msi(ctx->ifc_dev); 5229 } 5230 if (ctx->ifc_msix_mem != NULL) { 5231 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5232 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5233 ctx->ifc_msix_mem = NULL; 5234 } 5235 } 5236 5237 int 5238 iflib_device_detach(device_t dev) 5239 { 5240 if_ctx_t ctx = device_get_softc(dev); 5241 5242 return (iflib_device_deregister(ctx)); 5243 } 5244 5245 int 5246 iflib_device_suspend(device_t dev) 5247 { 5248 if_ctx_t ctx = device_get_softc(dev); 5249 5250 CTX_LOCK(ctx); 5251 IFDI_SUSPEND(ctx); 5252 CTX_UNLOCK(ctx); 5253 5254 return bus_generic_suspend(dev); 5255 } 5256 int 5257 iflib_device_shutdown(device_t dev) 5258 { 5259 if_ctx_t ctx = device_get_softc(dev); 5260 5261 CTX_LOCK(ctx); 5262 IFDI_SHUTDOWN(ctx); 5263 CTX_UNLOCK(ctx); 5264 5265 return bus_generic_suspend(dev); 5266 } 5267 5268 int 5269 iflib_device_resume(device_t dev) 5270 { 5271 if_ctx_t ctx = device_get_softc(dev); 5272 iflib_txq_t txq = ctx->ifc_txqs; 5273 5274 CTX_LOCK(ctx); 5275 IFDI_RESUME(ctx); 5276 iflib_if_init_locked(ctx); 5277 CTX_UNLOCK(ctx); 5278 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5279 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5280 5281 return (bus_generic_resume(dev)); 5282 } 5283 5284 int 5285 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5286 { 5287 int error; 5288 if_ctx_t ctx = device_get_softc(dev); 5289 5290 CTX_LOCK(ctx); 5291 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5292 CTX_UNLOCK(ctx); 5293 5294 return (error); 5295 } 5296 5297 void 5298 iflib_device_iov_uninit(device_t dev) 5299 { 5300 if_ctx_t ctx = device_get_softc(dev); 5301 5302 CTX_LOCK(ctx); 5303 IFDI_IOV_UNINIT(ctx); 5304 CTX_UNLOCK(ctx); 5305 } 5306 5307 int 5308 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5309 { 5310 int error; 5311 if_ctx_t ctx = device_get_softc(dev); 5312 5313 CTX_LOCK(ctx); 5314 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5315 CTX_UNLOCK(ctx); 5316 5317 return (error); 5318 } 5319 5320 /********************************************************************* 5321 * 5322 * MODULE FUNCTION DEFINITIONS 5323 * 5324 **********************************************************************/ 5325 5326 /* 5327 * - Start a fast taskqueue thread for each core 5328 * - Start a taskqueue for control operations 5329 */ 5330 static int 5331 iflib_module_init(void) 5332 { 5333 iflib_timer_default = hz / 2; 5334 return (0); 5335 } 5336 5337 static int 5338 iflib_module_event_handler(module_t mod, int what, void *arg) 5339 { 5340 int err; 5341 5342 switch (what) { 5343 case MOD_LOAD: 5344 if ((err = iflib_module_init()) != 0) 5345 return (err); 5346 break; 5347 case MOD_UNLOAD: 5348 return (EBUSY); 5349 default: 5350 return (EOPNOTSUPP); 5351 } 5352 5353 return (0); 5354 } 5355 5356 /********************************************************************* 5357 * 5358 * PUBLIC FUNCTION DEFINITIONS 5359 * ordered as in iflib.h 5360 * 5361 **********************************************************************/ 5362 5363 static void 5364 _iflib_assert(if_shared_ctx_t sctx) 5365 { 5366 int i; 5367 5368 MPASS(sctx->isc_tx_maxsize); 5369 MPASS(sctx->isc_tx_maxsegsize); 5370 5371 MPASS(sctx->isc_rx_maxsize); 5372 MPASS(sctx->isc_rx_nsegments); 5373 MPASS(sctx->isc_rx_maxsegsize); 5374 5375 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5376 for (i = 0; i < sctx->isc_nrxqs; i++) { 5377 MPASS(sctx->isc_nrxd_min[i]); 5378 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5379 MPASS(sctx->isc_nrxd_max[i]); 5380 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5381 MPASS(sctx->isc_nrxd_default[i]); 5382 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5383 } 5384 5385 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5386 for (i = 0; i < sctx->isc_ntxqs; i++) { 5387 MPASS(sctx->isc_ntxd_min[i]); 5388 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5389 MPASS(sctx->isc_ntxd_max[i]); 5390 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5391 MPASS(sctx->isc_ntxd_default[i]); 5392 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5393 } 5394 } 5395 5396 static void 5397 _iflib_pre_assert(if_softc_ctx_t scctx) 5398 { 5399 5400 MPASS(scctx->isc_txrx->ift_txd_encap); 5401 MPASS(scctx->isc_txrx->ift_txd_flush); 5402 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5403 MPASS(scctx->isc_txrx->ift_rxd_available); 5404 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5405 MPASS(scctx->isc_txrx->ift_rxd_refill); 5406 MPASS(scctx->isc_txrx->ift_rxd_flush); 5407 } 5408 5409 static int 5410 iflib_register(if_ctx_t ctx) 5411 { 5412 if_shared_ctx_t sctx = ctx->ifc_sctx; 5413 driver_t *driver = sctx->isc_driver; 5414 device_t dev = ctx->ifc_dev; 5415 if_t ifp; 5416 u_char type; 5417 int iflags; 5418 5419 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0) 5420 _iflib_assert(sctx); 5421 5422 CTX_LOCK_INIT(ctx); 5423 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5424 if (sctx->isc_flags & IFLIB_PSEUDO) { 5425 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) 5426 type = IFT_ETHER; 5427 else 5428 type = IFT_PPP; 5429 } else 5430 type = IFT_ETHER; 5431 ifp = ctx->ifc_ifp = if_alloc(type); 5432 if (ifp == NULL) { 5433 device_printf(dev, "can not allocate ifnet structure\n"); 5434 return (ENOMEM); 5435 } 5436 5437 /* 5438 * Initialize our context's device specific methods 5439 */ 5440 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5441 kobj_class_compile((kobj_class_t) driver); 5442 5443 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5444 if_setsoftc(ifp, ctx); 5445 if_setdev(ifp, dev); 5446 if_setinitfn(ifp, iflib_if_init); 5447 if_setioctlfn(ifp, iflib_if_ioctl); 5448 #ifdef ALTQ 5449 if_setstartfn(ifp, iflib_altq_if_start); 5450 if_settransmitfn(ifp, iflib_altq_if_transmit); 5451 if_setsendqready(ifp); 5452 #else 5453 if_settransmitfn(ifp, iflib_if_transmit); 5454 #endif 5455 if_setqflushfn(ifp, iflib_if_qflush); 5456 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH; 5457 5458 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5459 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) 5460 iflags |= IFF_POINTOPOINT; 5461 else 5462 iflags |= IFF_BROADCAST | IFF_SIMPLEX; 5463 if_setflags(ifp, iflags); 5464 ctx->ifc_vlan_attach_event = 5465 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5466 EVENTHANDLER_PRI_FIRST); 5467 ctx->ifc_vlan_detach_event = 5468 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5469 EVENTHANDLER_PRI_FIRST); 5470 5471 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5472 ctx->ifc_mediap = &ctx->ifc_media; 5473 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5474 iflib_media_change, iflib_media_status); 5475 } 5476 return (0); 5477 } 5478 5479 static void 5480 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5481 { 5482 /* Unregister VLAN events */ 5483 if (ctx->ifc_vlan_attach_event != NULL) { 5484 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5485 ctx->ifc_vlan_attach_event = NULL; 5486 } 5487 if (ctx->ifc_vlan_detach_event != NULL) { 5488 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5489 ctx->ifc_vlan_detach_event = NULL; 5490 } 5491 5492 } 5493 5494 static void 5495 iflib_deregister(if_ctx_t ctx) 5496 { 5497 if_t ifp = ctx->ifc_ifp; 5498 5499 /* Remove all media */ 5500 ifmedia_removeall(&ctx->ifc_media); 5501 5502 /* Ensure that VLAN event handlers are unregistered */ 5503 iflib_unregister_vlan_handlers(ctx); 5504 5505 /* Release kobject reference */ 5506 kobj_delete((kobj_t) ctx, NULL); 5507 5508 /* Free the ifnet structure */ 5509 if_free(ifp); 5510 5511 STATE_LOCK_DESTROY(ctx); 5512 5513 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5514 CTX_LOCK_DESTROY(ctx); 5515 } 5516 5517 static int 5518 iflib_queues_alloc(if_ctx_t ctx) 5519 { 5520 if_shared_ctx_t sctx = ctx->ifc_sctx; 5521 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5522 device_t dev = ctx->ifc_dev; 5523 int nrxqsets = scctx->isc_nrxqsets; 5524 int ntxqsets = scctx->isc_ntxqsets; 5525 iflib_txq_t txq; 5526 iflib_rxq_t rxq; 5527 iflib_fl_t fl = NULL; 5528 int i, j, cpu, err, txconf, rxconf; 5529 iflib_dma_info_t ifdip; 5530 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5531 uint32_t *txqsizes = scctx->isc_txqsizes; 5532 uint8_t nrxqs = sctx->isc_nrxqs; 5533 uint8_t ntxqs = sctx->isc_ntxqs; 5534 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5535 caddr_t *vaddrs; 5536 uint64_t *paddrs; 5537 5538 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5539 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5540 5541 /* Allocate the TX ring struct memory */ 5542 if (!(ctx->ifc_txqs = 5543 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5544 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5545 device_printf(dev, "Unable to allocate TX ring memory\n"); 5546 err = ENOMEM; 5547 goto fail; 5548 } 5549 5550 /* Now allocate the RX */ 5551 if (!(ctx->ifc_rxqs = 5552 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5553 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5554 device_printf(dev, "Unable to allocate RX ring memory\n"); 5555 err = ENOMEM; 5556 goto rx_fail; 5557 } 5558 5559 txq = ctx->ifc_txqs; 5560 rxq = ctx->ifc_rxqs; 5561 5562 /* 5563 * XXX handle allocation failure 5564 */ 5565 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5566 /* Set up some basics */ 5567 5568 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5569 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5570 device_printf(dev, 5571 "Unable to allocate TX DMA info memory\n"); 5572 err = ENOMEM; 5573 goto err_tx_desc; 5574 } 5575 txq->ift_ifdi = ifdip; 5576 for (j = 0; j < ntxqs; j++, ifdip++) { 5577 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5578 device_printf(dev, 5579 "Unable to allocate TX descriptors\n"); 5580 err = ENOMEM; 5581 goto err_tx_desc; 5582 } 5583 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5584 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5585 } 5586 txq->ift_ctx = ctx; 5587 txq->ift_id = i; 5588 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5589 txq->ift_br_offset = 1; 5590 } else { 5591 txq->ift_br_offset = 0; 5592 } 5593 5594 if (iflib_txsd_alloc(txq)) { 5595 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5596 err = ENOMEM; 5597 goto err_tx_desc; 5598 } 5599 5600 /* Initialize the TX lock */ 5601 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5602 device_get_nameunit(dev), txq->ift_id); 5603 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5604 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5605 txq->ift_timer.c_cpu = cpu; 5606 #ifdef DEV_NETMAP 5607 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 5608 txq->ift_netmap_timer.c_cpu = cpu; 5609 #endif /* DEV_NETMAP */ 5610 5611 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5612 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5613 if (err) { 5614 /* XXX free any allocated rings */ 5615 device_printf(dev, "Unable to allocate buf_ring\n"); 5616 goto err_tx_desc; 5617 } 5618 } 5619 5620 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5621 /* Set up some basics */ 5622 callout_init(&rxq->ifr_watchdog, 1); 5623 5624 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5625 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5626 device_printf(dev, 5627 "Unable to allocate RX DMA info memory\n"); 5628 err = ENOMEM; 5629 goto err_tx_desc; 5630 } 5631 5632 rxq->ifr_ifdi = ifdip; 5633 /* XXX this needs to be changed if #rx queues != #tx queues */ 5634 rxq->ifr_ntxqirq = 1; 5635 rxq->ifr_txqid[0] = i; 5636 for (j = 0; j < nrxqs; j++, ifdip++) { 5637 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5638 device_printf(dev, 5639 "Unable to allocate RX descriptors\n"); 5640 err = ENOMEM; 5641 goto err_tx_desc; 5642 } 5643 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5644 } 5645 rxq->ifr_ctx = ctx; 5646 rxq->ifr_id = i; 5647 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5648 rxq->ifr_fl_offset = 1; 5649 } else { 5650 rxq->ifr_fl_offset = 0; 5651 } 5652 rxq->ifr_nfl = nfree_lists; 5653 if (!(fl = 5654 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5655 device_printf(dev, "Unable to allocate free list memory\n"); 5656 err = ENOMEM; 5657 goto err_tx_desc; 5658 } 5659 rxq->ifr_fl = fl; 5660 for (j = 0; j < nfree_lists; j++) { 5661 fl[j].ifl_rxq = rxq; 5662 fl[j].ifl_id = j; 5663 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5664 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5665 } 5666 /* Allocate receive buffers for the ring */ 5667 if (iflib_rxsd_alloc(rxq)) { 5668 device_printf(dev, 5669 "Critical Failure setting up receive buffers\n"); 5670 err = ENOMEM; 5671 goto err_rx_desc; 5672 } 5673 5674 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5675 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5676 M_WAITOK); 5677 } 5678 5679 /* TXQs */ 5680 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5681 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5682 for (i = 0; i < ntxqsets; i++) { 5683 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5684 5685 for (j = 0; j < ntxqs; j++, di++) { 5686 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5687 paddrs[i*ntxqs + j] = di->idi_paddr; 5688 } 5689 } 5690 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5691 device_printf(ctx->ifc_dev, 5692 "Unable to allocate device TX queue\n"); 5693 iflib_tx_structures_free(ctx); 5694 free(vaddrs, M_IFLIB); 5695 free(paddrs, M_IFLIB); 5696 goto err_rx_desc; 5697 } 5698 free(vaddrs, M_IFLIB); 5699 free(paddrs, M_IFLIB); 5700 5701 /* RXQs */ 5702 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5703 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5704 for (i = 0; i < nrxqsets; i++) { 5705 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5706 5707 for (j = 0; j < nrxqs; j++, di++) { 5708 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5709 paddrs[i*nrxqs + j] = di->idi_paddr; 5710 } 5711 } 5712 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5713 device_printf(ctx->ifc_dev, 5714 "Unable to allocate device RX queue\n"); 5715 iflib_tx_structures_free(ctx); 5716 free(vaddrs, M_IFLIB); 5717 free(paddrs, M_IFLIB); 5718 goto err_rx_desc; 5719 } 5720 free(vaddrs, M_IFLIB); 5721 free(paddrs, M_IFLIB); 5722 5723 return (0); 5724 5725 /* XXX handle allocation failure changes */ 5726 err_rx_desc: 5727 err_tx_desc: 5728 rx_fail: 5729 if (ctx->ifc_rxqs != NULL) 5730 free(ctx->ifc_rxqs, M_IFLIB); 5731 ctx->ifc_rxqs = NULL; 5732 if (ctx->ifc_txqs != NULL) 5733 free(ctx->ifc_txqs, M_IFLIB); 5734 ctx->ifc_txqs = NULL; 5735 fail: 5736 return (err); 5737 } 5738 5739 static int 5740 iflib_tx_structures_setup(if_ctx_t ctx) 5741 { 5742 iflib_txq_t txq = ctx->ifc_txqs; 5743 int i; 5744 5745 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5746 iflib_txq_setup(txq); 5747 5748 return (0); 5749 } 5750 5751 static void 5752 iflib_tx_structures_free(if_ctx_t ctx) 5753 { 5754 iflib_txq_t txq = ctx->ifc_txqs; 5755 if_shared_ctx_t sctx = ctx->ifc_sctx; 5756 int i, j; 5757 5758 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5759 for (j = 0; j < sctx->isc_ntxqs; j++) 5760 iflib_dma_free(&txq->ift_ifdi[j]); 5761 iflib_txq_destroy(txq); 5762 } 5763 free(ctx->ifc_txqs, M_IFLIB); 5764 ctx->ifc_txqs = NULL; 5765 IFDI_QUEUES_FREE(ctx); 5766 } 5767 5768 /********************************************************************* 5769 * 5770 * Initialize all receive rings. 5771 * 5772 **********************************************************************/ 5773 static int 5774 iflib_rx_structures_setup(if_ctx_t ctx) 5775 { 5776 iflib_rxq_t rxq = ctx->ifc_rxqs; 5777 int q; 5778 #if defined(INET6) || defined(INET) 5779 int err, i; 5780 #endif 5781 5782 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5783 #if defined(INET6) || defined(INET) 5784 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) { 5785 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5786 TCP_LRO_ENTRIES, min(1024, 5787 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 5788 if (err != 0) { 5789 device_printf(ctx->ifc_dev, 5790 "LRO Initialization failed!\n"); 5791 goto fail; 5792 } 5793 } 5794 #endif 5795 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5796 } 5797 return (0); 5798 #if defined(INET6) || defined(INET) 5799 fail: 5800 /* 5801 * Free LRO resources allocated so far, we will only handle 5802 * the rings that completed, the failing case will have 5803 * cleaned up for itself. 'q' failed, so its the terminus. 5804 */ 5805 rxq = ctx->ifc_rxqs; 5806 for (i = 0; i < q; ++i, rxq++) { 5807 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5808 tcp_lro_free(&rxq->ifr_lc); 5809 } 5810 return (err); 5811 #endif 5812 } 5813 5814 /********************************************************************* 5815 * 5816 * Free all receive rings. 5817 * 5818 **********************************************************************/ 5819 static void 5820 iflib_rx_structures_free(if_ctx_t ctx) 5821 { 5822 iflib_rxq_t rxq = ctx->ifc_rxqs; 5823 if_shared_ctx_t sctx = ctx->ifc_sctx; 5824 int i, j; 5825 5826 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5827 for (j = 0; j < sctx->isc_nrxqs; j++) 5828 iflib_dma_free(&rxq->ifr_ifdi[j]); 5829 iflib_rx_sds_free(rxq); 5830 #if defined(INET6) || defined(INET) 5831 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5832 tcp_lro_free(&rxq->ifr_lc); 5833 #endif 5834 } 5835 free(ctx->ifc_rxqs, M_IFLIB); 5836 ctx->ifc_rxqs = NULL; 5837 } 5838 5839 static int 5840 iflib_qset_structures_setup(if_ctx_t ctx) 5841 { 5842 int err; 5843 5844 /* 5845 * It is expected that the caller takes care of freeing queues if this 5846 * fails. 5847 */ 5848 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5849 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5850 return (err); 5851 } 5852 5853 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5854 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5855 5856 return (err); 5857 } 5858 5859 int 5860 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5861 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5862 { 5863 5864 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5865 } 5866 5867 #ifdef SMP 5868 static int 5869 find_nth(if_ctx_t ctx, int qid) 5870 { 5871 cpuset_t cpus; 5872 int i, cpuid, eqid, count; 5873 5874 CPU_COPY(&ctx->ifc_cpus, &cpus); 5875 count = CPU_COUNT(&cpus); 5876 eqid = qid % count; 5877 /* clear up to the qid'th bit */ 5878 for (i = 0; i < eqid; i++) { 5879 cpuid = CPU_FFS(&cpus); 5880 MPASS(cpuid != 0); 5881 CPU_CLR(cpuid-1, &cpus); 5882 } 5883 cpuid = CPU_FFS(&cpus); 5884 MPASS(cpuid != 0); 5885 return (cpuid-1); 5886 } 5887 5888 #ifdef SCHED_ULE 5889 extern struct cpu_group *cpu_top; /* CPU topology */ 5890 5891 static int 5892 find_child_with_core(int cpu, struct cpu_group *grp) 5893 { 5894 int i; 5895 5896 if (grp->cg_children == 0) 5897 return -1; 5898 5899 MPASS(grp->cg_child); 5900 for (i = 0; i < grp->cg_children; i++) { 5901 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5902 return i; 5903 } 5904 5905 return -1; 5906 } 5907 5908 /* 5909 * Find the nth "close" core to the specified core 5910 * "close" is defined as the deepest level that shares 5911 * at least an L2 cache. With threads, this will be 5912 * threads on the same core. If the shared cache is L3 5913 * or higher, simply returns the same core. 5914 */ 5915 static int 5916 find_close_core(int cpu, int core_offset) 5917 { 5918 struct cpu_group *grp; 5919 int i; 5920 int fcpu; 5921 cpuset_t cs; 5922 5923 grp = cpu_top; 5924 if (grp == NULL) 5925 return cpu; 5926 i = 0; 5927 while ((i = find_child_with_core(cpu, grp)) != -1) { 5928 /* If the child only has one cpu, don't descend */ 5929 if (grp->cg_child[i].cg_count <= 1) 5930 break; 5931 grp = &grp->cg_child[i]; 5932 } 5933 5934 /* If they don't share at least an L2 cache, use the same CPU */ 5935 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5936 return cpu; 5937 5938 /* Now pick one */ 5939 CPU_COPY(&grp->cg_mask, &cs); 5940 5941 /* Add the selected CPU offset to core offset. */ 5942 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5943 if (fcpu - 1 == cpu) 5944 break; 5945 CPU_CLR(fcpu - 1, &cs); 5946 } 5947 MPASS(fcpu); 5948 5949 core_offset += i; 5950 5951 CPU_COPY(&grp->cg_mask, &cs); 5952 for (i = core_offset % grp->cg_count; i > 0; i--) { 5953 MPASS(CPU_FFS(&cs)); 5954 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5955 } 5956 MPASS(CPU_FFS(&cs)); 5957 return CPU_FFS(&cs) - 1; 5958 } 5959 #else 5960 static int 5961 find_close_core(int cpu, int core_offset __unused) 5962 { 5963 return cpu; 5964 } 5965 #endif 5966 5967 static int 5968 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5969 { 5970 switch (type) { 5971 case IFLIB_INTR_TX: 5972 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5973 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5974 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5975 case IFLIB_INTR_RX: 5976 case IFLIB_INTR_RXTX: 5977 /* RX queues get the specified core */ 5978 return qid / CPU_COUNT(&ctx->ifc_cpus); 5979 default: 5980 return -1; 5981 } 5982 } 5983 #else 5984 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5985 #define find_close_core(cpuid, tid) CPU_FIRST() 5986 #define find_nth(ctx, gid) CPU_FIRST() 5987 #endif 5988 5989 /* Just to avoid copy/paste */ 5990 static inline int 5991 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5992 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5993 const char *name) 5994 { 5995 device_t dev; 5996 int co, cpuid, err, tid; 5997 5998 dev = ctx->ifc_dev; 5999 co = ctx->ifc_sysctl_core_offset; 6000 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX) 6001 co += ctx->ifc_softc_ctx.isc_nrxqsets; 6002 cpuid = find_nth(ctx, qid + co); 6003 tid = get_core_offset(ctx, type, qid); 6004 if (tid < 0) { 6005 device_printf(dev, "get_core_offset failed\n"); 6006 return (EOPNOTSUPP); 6007 } 6008 cpuid = find_close_core(cpuid, tid); 6009 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 6010 name); 6011 if (err) { 6012 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6013 return (err); 6014 } 6015 #ifdef notyet 6016 if (cpuid > ctx->ifc_cpuid_highest) 6017 ctx->ifc_cpuid_highest = cpuid; 6018 #endif 6019 return (0); 6020 } 6021 6022 int 6023 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6024 iflib_intr_type_t type, driver_filter_t *filter, 6025 void *filter_arg, int qid, const char *name) 6026 { 6027 device_t dev; 6028 struct grouptask *gtask; 6029 struct taskqgroup *tqg; 6030 iflib_filter_info_t info; 6031 gtask_fn_t *fn; 6032 int tqrid, err; 6033 driver_filter_t *intr_fast; 6034 void *q; 6035 6036 info = &ctx->ifc_filter_info; 6037 tqrid = rid; 6038 6039 switch (type) { 6040 /* XXX merge tx/rx for netmap? */ 6041 case IFLIB_INTR_TX: 6042 q = &ctx->ifc_txqs[qid]; 6043 info = &ctx->ifc_txqs[qid].ift_filter_info; 6044 gtask = &ctx->ifc_txqs[qid].ift_task; 6045 tqg = qgroup_if_io_tqg; 6046 fn = _task_fn_tx; 6047 intr_fast = iflib_fast_intr; 6048 GROUPTASK_INIT(gtask, 0, fn, q); 6049 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6050 break; 6051 case IFLIB_INTR_RX: 6052 q = &ctx->ifc_rxqs[qid]; 6053 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6054 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6055 tqg = qgroup_if_io_tqg; 6056 fn = _task_fn_rx; 6057 intr_fast = iflib_fast_intr; 6058 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6059 break; 6060 case IFLIB_INTR_RXTX: 6061 q = &ctx->ifc_rxqs[qid]; 6062 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6063 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6064 tqg = qgroup_if_io_tqg; 6065 fn = _task_fn_rx; 6066 intr_fast = iflib_fast_intr_rxtx; 6067 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6068 break; 6069 case IFLIB_INTR_ADMIN: 6070 q = ctx; 6071 tqrid = -1; 6072 info = &ctx->ifc_filter_info; 6073 gtask = &ctx->ifc_admin_task; 6074 tqg = qgroup_if_config_tqg; 6075 fn = _task_fn_admin; 6076 intr_fast = iflib_fast_intr_ctx; 6077 break; 6078 default: 6079 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6080 __func__); 6081 return (EINVAL); 6082 } 6083 6084 info->ifi_filter = filter; 6085 info->ifi_filter_arg = filter_arg; 6086 info->ifi_task = gtask; 6087 info->ifi_ctx = q; 6088 6089 dev = ctx->ifc_dev; 6090 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6091 if (err != 0) { 6092 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6093 return (err); 6094 } 6095 if (type == IFLIB_INTR_ADMIN) 6096 return (0); 6097 6098 if (tqrid != -1) { 6099 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6100 q, name); 6101 if (err) 6102 return (err); 6103 } else { 6104 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6105 } 6106 6107 return (0); 6108 } 6109 6110 void 6111 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6112 { 6113 struct grouptask *gtask; 6114 struct taskqgroup *tqg; 6115 gtask_fn_t *fn; 6116 void *q; 6117 int err; 6118 6119 switch (type) { 6120 case IFLIB_INTR_TX: 6121 q = &ctx->ifc_txqs[qid]; 6122 gtask = &ctx->ifc_txqs[qid].ift_task; 6123 tqg = qgroup_if_io_tqg; 6124 fn = _task_fn_tx; 6125 GROUPTASK_INIT(gtask, 0, fn, q); 6126 break; 6127 case IFLIB_INTR_RX: 6128 q = &ctx->ifc_rxqs[qid]; 6129 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6130 tqg = qgroup_if_io_tqg; 6131 fn = _task_fn_rx; 6132 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6133 break; 6134 case IFLIB_INTR_IOV: 6135 q = ctx; 6136 gtask = &ctx->ifc_vflr_task; 6137 tqg = qgroup_if_config_tqg; 6138 fn = _task_fn_iov; 6139 GROUPTASK_INIT(gtask, 0, fn, q); 6140 break; 6141 default: 6142 panic("unknown net intr type"); 6143 } 6144 if (irq != NULL) { 6145 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6146 q, name); 6147 if (err) 6148 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 6149 irq->ii_res, name); 6150 } else { 6151 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 6152 } 6153 } 6154 6155 void 6156 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6157 { 6158 6159 if (irq->ii_tag) 6160 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6161 6162 if (irq->ii_res) 6163 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6164 rman_get_rid(irq->ii_res), irq->ii_res); 6165 } 6166 6167 static int 6168 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6169 { 6170 iflib_txq_t txq = ctx->ifc_txqs; 6171 iflib_rxq_t rxq = ctx->ifc_rxqs; 6172 if_irq_t irq = &ctx->ifc_legacy_irq; 6173 iflib_filter_info_t info; 6174 device_t dev; 6175 struct grouptask *gtask; 6176 struct resource *res; 6177 struct taskqgroup *tqg; 6178 void *q; 6179 int err, tqrid; 6180 bool rx_only; 6181 6182 q = &ctx->ifc_rxqs[0]; 6183 info = &rxq[0].ifr_filter_info; 6184 gtask = &rxq[0].ifr_task; 6185 tqg = qgroup_if_io_tqg; 6186 tqrid = *rid; 6187 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6188 6189 ctx->ifc_flags |= IFC_LEGACY; 6190 info->ifi_filter = filter; 6191 info->ifi_filter_arg = filter_arg; 6192 info->ifi_task = gtask; 6193 info->ifi_ctx = rx_only ? ctx : q; 6194 6195 dev = ctx->ifc_dev; 6196 /* We allocate a single interrupt resource */ 6197 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6198 iflib_fast_intr_rxtx, NULL, info, name); 6199 if (err != 0) 6200 return (err); 6201 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6202 res = irq->ii_res; 6203 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6204 6205 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6206 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6207 "tx"); 6208 return (0); 6209 } 6210 6211 void 6212 iflib_led_create(if_ctx_t ctx) 6213 { 6214 6215 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6216 device_get_nameunit(ctx->ifc_dev)); 6217 } 6218 6219 void 6220 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6221 { 6222 6223 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6224 } 6225 6226 void 6227 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6228 { 6229 6230 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6231 } 6232 6233 void 6234 iflib_admin_intr_deferred(if_ctx_t ctx) 6235 { 6236 6237 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6238 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6239 } 6240 6241 void 6242 iflib_iov_intr_deferred(if_ctx_t ctx) 6243 { 6244 6245 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6246 } 6247 6248 void 6249 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6250 { 6251 6252 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6253 name); 6254 } 6255 6256 void 6257 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6258 const char *name) 6259 { 6260 6261 GROUPTASK_INIT(gtask, 0, fn, ctx); 6262 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6263 name); 6264 } 6265 6266 void 6267 iflib_config_gtask_deinit(struct grouptask *gtask) 6268 { 6269 6270 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6271 } 6272 6273 void 6274 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6275 { 6276 if_t ifp = ctx->ifc_ifp; 6277 iflib_txq_t txq = ctx->ifc_txqs; 6278 6279 if_setbaudrate(ifp, baudrate); 6280 if (baudrate >= IF_Gbps(10)) { 6281 STATE_LOCK(ctx); 6282 ctx->ifc_flags |= IFC_PREFETCH; 6283 STATE_UNLOCK(ctx); 6284 } 6285 /* If link down, disable watchdog */ 6286 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6287 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6288 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6289 } 6290 ctx->ifc_link_state = link_state; 6291 if_link_state_change(ifp, link_state); 6292 } 6293 6294 static int 6295 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6296 { 6297 int credits; 6298 #ifdef INVARIANTS 6299 int credits_pre = txq->ift_cidx_processed; 6300 #endif 6301 6302 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6303 BUS_DMASYNC_POSTREAD); 6304 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6305 return (0); 6306 6307 txq->ift_processed += credits; 6308 txq->ift_cidx_processed += credits; 6309 6310 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6311 if (txq->ift_cidx_processed >= txq->ift_size) 6312 txq->ift_cidx_processed -= txq->ift_size; 6313 return (credits); 6314 } 6315 6316 static int 6317 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6318 { 6319 iflib_fl_t fl; 6320 u_int i; 6321 6322 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6323 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6324 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6325 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6326 budget)); 6327 } 6328 6329 void 6330 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6331 const char *description, if_int_delay_info_t info, 6332 int offset, int value) 6333 { 6334 info->iidi_ctx = ctx; 6335 info->iidi_offset = offset; 6336 info->iidi_value = value; 6337 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6338 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6339 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6340 info, 0, iflib_sysctl_int_delay, "I", description); 6341 } 6342 6343 struct sx * 6344 iflib_ctx_lock_get(if_ctx_t ctx) 6345 { 6346 6347 return (&ctx->ifc_ctx_sx); 6348 } 6349 6350 static int 6351 iflib_msix_init(if_ctx_t ctx) 6352 { 6353 device_t dev = ctx->ifc_dev; 6354 if_shared_ctx_t sctx = ctx->ifc_sctx; 6355 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6356 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6357 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6358 6359 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6360 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6361 6362 if (bootverbose) 6363 device_printf(dev, "msix_init qsets capped at %d\n", 6364 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6365 6366 /* Override by tuneable */ 6367 if (scctx->isc_disable_msix) 6368 goto msi; 6369 6370 /* First try MSI-X */ 6371 if ((msgs = pci_msix_count(dev)) == 0) { 6372 if (bootverbose) 6373 device_printf(dev, "MSI-X not supported or disabled\n"); 6374 goto msi; 6375 } 6376 6377 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6378 /* 6379 * bar == -1 => "trust me I know what I'm doing" 6380 * Some drivers are for hardware that is so shoddily 6381 * documented that no one knows which bars are which 6382 * so the developer has to map all bars. This hack 6383 * allows shoddy garbage to use MSI-X in this framework. 6384 */ 6385 if (bar != -1) { 6386 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6387 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6388 if (ctx->ifc_msix_mem == NULL) { 6389 device_printf(dev, "Unable to map MSI-X table\n"); 6390 goto msi; 6391 } 6392 } 6393 6394 admincnt = sctx->isc_admin_intrcnt; 6395 #if IFLIB_DEBUG 6396 /* use only 1 qset in debug mode */ 6397 queuemsgs = min(msgs - admincnt, 1); 6398 #else 6399 queuemsgs = msgs - admincnt; 6400 #endif 6401 #ifdef RSS 6402 queues = imin(queuemsgs, rss_getnumbuckets()); 6403 #else 6404 queues = queuemsgs; 6405 #endif 6406 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6407 if (bootverbose) 6408 device_printf(dev, 6409 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6410 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6411 #ifdef RSS 6412 /* If we're doing RSS, clamp at the number of RSS buckets */ 6413 if (queues > rss_getnumbuckets()) 6414 queues = rss_getnumbuckets(); 6415 #endif 6416 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6417 rx_queues = iflib_num_rx_queues; 6418 else 6419 rx_queues = queues; 6420 6421 if (rx_queues > scctx->isc_nrxqsets) 6422 rx_queues = scctx->isc_nrxqsets; 6423 6424 /* 6425 * We want this to be all logical CPUs by default 6426 */ 6427 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6428 tx_queues = iflib_num_tx_queues; 6429 else 6430 tx_queues = mp_ncpus; 6431 6432 if (tx_queues > scctx->isc_ntxqsets) 6433 tx_queues = scctx->isc_ntxqsets; 6434 6435 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6436 #ifdef INVARIANTS 6437 if (tx_queues != rx_queues) 6438 device_printf(dev, 6439 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6440 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6441 #endif 6442 tx_queues = min(rx_queues, tx_queues); 6443 rx_queues = min(rx_queues, tx_queues); 6444 } 6445 6446 vectors = rx_queues + admincnt; 6447 if (msgs < vectors) { 6448 device_printf(dev, 6449 "insufficient number of MSI-X vectors " 6450 "(supported %d, need %d)\n", msgs, vectors); 6451 goto msi; 6452 } 6453 6454 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6455 tx_queues); 6456 msgs = vectors; 6457 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6458 if (vectors != msgs) { 6459 device_printf(dev, 6460 "Unable to allocate sufficient MSI-X vectors " 6461 "(got %d, need %d)\n", vectors, msgs); 6462 pci_release_msi(dev); 6463 if (bar != -1) { 6464 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6465 ctx->ifc_msix_mem); 6466 ctx->ifc_msix_mem = NULL; 6467 } 6468 goto msi; 6469 } 6470 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6471 vectors); 6472 scctx->isc_vectors = vectors; 6473 scctx->isc_nrxqsets = rx_queues; 6474 scctx->isc_ntxqsets = tx_queues; 6475 scctx->isc_intr = IFLIB_INTR_MSIX; 6476 6477 return (vectors); 6478 } else { 6479 device_printf(dev, 6480 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6481 err); 6482 if (bar != -1) { 6483 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6484 ctx->ifc_msix_mem); 6485 ctx->ifc_msix_mem = NULL; 6486 } 6487 } 6488 6489 msi: 6490 vectors = pci_msi_count(dev); 6491 scctx->isc_nrxqsets = 1; 6492 scctx->isc_ntxqsets = 1; 6493 scctx->isc_vectors = vectors; 6494 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6495 device_printf(dev,"Using an MSI interrupt\n"); 6496 scctx->isc_intr = IFLIB_INTR_MSI; 6497 } else { 6498 scctx->isc_vectors = 1; 6499 device_printf(dev,"Using a Legacy interrupt\n"); 6500 scctx->isc_intr = IFLIB_INTR_LEGACY; 6501 } 6502 6503 return (vectors); 6504 } 6505 6506 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6507 6508 static int 6509 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6510 { 6511 int rc; 6512 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6513 struct sbuf *sb; 6514 const char *ring_state = "UNKNOWN"; 6515 6516 /* XXX needed ? */ 6517 rc = sysctl_wire_old_buffer(req, 0); 6518 MPASS(rc == 0); 6519 if (rc != 0) 6520 return (rc); 6521 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6522 MPASS(sb != NULL); 6523 if (sb == NULL) 6524 return (ENOMEM); 6525 if (state[3] <= 3) 6526 ring_state = ring_states[state[3]]; 6527 6528 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6529 state[0], state[1], state[2], ring_state); 6530 rc = sbuf_finish(sb); 6531 sbuf_delete(sb); 6532 return(rc); 6533 } 6534 6535 enum iflib_ndesc_handler { 6536 IFLIB_NTXD_HANDLER, 6537 IFLIB_NRXD_HANDLER, 6538 }; 6539 6540 static int 6541 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6542 { 6543 if_ctx_t ctx = (void *)arg1; 6544 enum iflib_ndesc_handler type = arg2; 6545 char buf[256] = {0}; 6546 qidx_t *ndesc; 6547 char *p, *next; 6548 int nqs, rc, i; 6549 6550 nqs = 8; 6551 switch(type) { 6552 case IFLIB_NTXD_HANDLER: 6553 ndesc = ctx->ifc_sysctl_ntxds; 6554 if (ctx->ifc_sctx) 6555 nqs = ctx->ifc_sctx->isc_ntxqs; 6556 break; 6557 case IFLIB_NRXD_HANDLER: 6558 ndesc = ctx->ifc_sysctl_nrxds; 6559 if (ctx->ifc_sctx) 6560 nqs = ctx->ifc_sctx->isc_nrxqs; 6561 break; 6562 default: 6563 printf("%s: unhandled type\n", __func__); 6564 return (EINVAL); 6565 } 6566 if (nqs == 0) 6567 nqs = 8; 6568 6569 for (i=0; i<8; i++) { 6570 if (i >= nqs) 6571 break; 6572 if (i) 6573 strcat(buf, ","); 6574 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6575 } 6576 6577 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6578 if (rc || req->newptr == NULL) 6579 return rc; 6580 6581 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6582 i++, p = strsep(&next, " ,")) { 6583 ndesc[i] = strtoul(p, NULL, 10); 6584 } 6585 6586 return(rc); 6587 } 6588 6589 #define NAME_BUFLEN 32 6590 static void 6591 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6592 { 6593 device_t dev = iflib_get_dev(ctx); 6594 struct sysctl_oid_list *child, *oid_list; 6595 struct sysctl_ctx_list *ctx_list; 6596 struct sysctl_oid *node; 6597 6598 ctx_list = device_get_sysctl_ctx(dev); 6599 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6600 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6601 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 6602 oid_list = SYSCTL_CHILDREN(node); 6603 6604 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6605 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6606 "driver version"); 6607 6608 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6609 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6610 "# of txqs to use, 0 => use default #"); 6611 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6612 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6613 "# of rxqs to use, 0 => use default #"); 6614 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6615 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6616 "permit #txq != #rxq"); 6617 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6618 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6619 "disable MSI-X (default 0)"); 6620 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6621 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6622 "set the RX budget"); 6623 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6624 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6625 "cause TX to abdicate instead of running to completion"); 6626 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6627 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6628 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6629 "offset to start using cores at"); 6630 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6631 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6632 "use separate cores for TX and RX"); 6633 6634 /* XXX change for per-queue sizes */ 6635 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6636 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6637 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6638 "list of # of TX descriptors to use, 0 = use default #"); 6639 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6640 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6641 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6642 "list of # of RX descriptors to use, 0 = use default #"); 6643 } 6644 6645 static void 6646 iflib_add_device_sysctl_post(if_ctx_t ctx) 6647 { 6648 if_shared_ctx_t sctx = ctx->ifc_sctx; 6649 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6650 device_t dev = iflib_get_dev(ctx); 6651 struct sysctl_oid_list *child; 6652 struct sysctl_ctx_list *ctx_list; 6653 iflib_fl_t fl; 6654 iflib_txq_t txq; 6655 iflib_rxq_t rxq; 6656 int i, j; 6657 char namebuf[NAME_BUFLEN]; 6658 char *qfmt; 6659 struct sysctl_oid *queue_node, *fl_node, *node; 6660 struct sysctl_oid_list *queue_list, *fl_list; 6661 ctx_list = device_get_sysctl_ctx(dev); 6662 6663 node = ctx->ifc_sysctl_node; 6664 child = SYSCTL_CHILDREN(node); 6665 6666 if (scctx->isc_ntxqsets > 100) 6667 qfmt = "txq%03d"; 6668 else if (scctx->isc_ntxqsets > 10) 6669 qfmt = "txq%02d"; 6670 else 6671 qfmt = "txq%d"; 6672 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6673 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6674 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6675 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6676 queue_list = SYSCTL_CHILDREN(queue_node); 6677 #if MEMORY_LOGGING 6678 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6679 CTLFLAG_RD, 6680 &txq->ift_dequeued, "total mbufs freed"); 6681 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6682 CTLFLAG_RD, 6683 &txq->ift_enqueued, "total mbufs enqueued"); 6684 #endif 6685 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6686 CTLFLAG_RD, 6687 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6688 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6689 CTLFLAG_RD, 6690 &txq->ift_pullups, "# of times m_pullup was called"); 6691 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6692 CTLFLAG_RD, 6693 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6694 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6695 CTLFLAG_RD, 6696 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6697 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6698 CTLFLAG_RD, 6699 &txq->ift_map_failed, "# of times DMA map failed"); 6700 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6701 CTLFLAG_RD, 6702 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6703 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6704 CTLFLAG_RD, 6705 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6706 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6707 CTLFLAG_RD, 6708 &txq->ift_pidx, 1, "Producer Index"); 6709 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6710 CTLFLAG_RD, 6711 &txq->ift_cidx, 1, "Consumer Index"); 6712 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6713 CTLFLAG_RD, 6714 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6715 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6716 CTLFLAG_RD, 6717 &txq->ift_in_use, 1, "descriptors in use"); 6718 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6719 CTLFLAG_RD, 6720 &txq->ift_processed, "descriptors procesed for clean"); 6721 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6722 CTLFLAG_RD, 6723 &txq->ift_cleaned, "total cleaned"); 6724 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6725 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6726 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6727 mp_ring_state_handler, "A", "soft ring state"); 6728 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6729 CTLFLAG_RD, &txq->ift_br->enqueues, 6730 "# of enqueues to the mp_ring for this queue"); 6731 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6732 CTLFLAG_RD, &txq->ift_br->drops, 6733 "# of drops in the mp_ring for this queue"); 6734 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6735 CTLFLAG_RD, &txq->ift_br->starts, 6736 "# of normal consumer starts in the mp_ring for this queue"); 6737 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6738 CTLFLAG_RD, &txq->ift_br->stalls, 6739 "# of consumer stalls in the mp_ring for this queue"); 6740 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6741 CTLFLAG_RD, &txq->ift_br->restarts, 6742 "# of consumer restarts in the mp_ring for this queue"); 6743 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6744 CTLFLAG_RD, &txq->ift_br->abdications, 6745 "# of consumer abdications in the mp_ring for this queue"); 6746 } 6747 6748 if (scctx->isc_nrxqsets > 100) 6749 qfmt = "rxq%03d"; 6750 else if (scctx->isc_nrxqsets > 10) 6751 qfmt = "rxq%02d"; 6752 else 6753 qfmt = "rxq%d"; 6754 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6755 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6756 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6757 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6758 queue_list = SYSCTL_CHILDREN(queue_node); 6759 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6760 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6761 CTLFLAG_RD, 6762 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6763 } 6764 6765 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6766 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6767 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6768 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 6769 fl_list = SYSCTL_CHILDREN(fl_node); 6770 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6771 CTLFLAG_RD, 6772 &fl->ifl_pidx, 1, "Producer Index"); 6773 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6774 CTLFLAG_RD, 6775 &fl->ifl_cidx, 1, "Consumer Index"); 6776 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6777 CTLFLAG_RD, 6778 &fl->ifl_credits, 1, "credits available"); 6779 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 6780 CTLFLAG_RD, 6781 &fl->ifl_buf_size, 1, "buffer size"); 6782 #if MEMORY_LOGGING 6783 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6784 CTLFLAG_RD, 6785 &fl->ifl_m_enqueued, "mbufs allocated"); 6786 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6787 CTLFLAG_RD, 6788 &fl->ifl_m_dequeued, "mbufs freed"); 6789 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6790 CTLFLAG_RD, 6791 &fl->ifl_cl_enqueued, "clusters allocated"); 6792 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6793 CTLFLAG_RD, 6794 &fl->ifl_cl_dequeued, "clusters freed"); 6795 #endif 6796 } 6797 } 6798 6799 } 6800 6801 void 6802 iflib_request_reset(if_ctx_t ctx) 6803 { 6804 6805 STATE_LOCK(ctx); 6806 ctx->ifc_flags |= IFC_DO_RESET; 6807 STATE_UNLOCK(ctx); 6808 } 6809 6810 #ifndef __NO_STRICT_ALIGNMENT 6811 static struct mbuf * 6812 iflib_fixup_rx(struct mbuf *m) 6813 { 6814 struct mbuf *n; 6815 6816 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6817 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6818 m->m_data += ETHER_HDR_LEN; 6819 n = m; 6820 } else { 6821 MGETHDR(n, M_NOWAIT, MT_DATA); 6822 if (n == NULL) { 6823 m_freem(m); 6824 return (NULL); 6825 } 6826 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6827 m->m_data += ETHER_HDR_LEN; 6828 m->m_len -= ETHER_HDR_LEN; 6829 n->m_len = ETHER_HDR_LEN; 6830 M_MOVE_PKTHDR(n, m); 6831 n->m_next = m; 6832 } 6833 return (n); 6834 } 6835 #endif 6836 6837 #ifdef DEBUGNET 6838 static void 6839 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6840 { 6841 if_ctx_t ctx; 6842 6843 ctx = if_getsoftc(ifp); 6844 CTX_LOCK(ctx); 6845 *nrxr = NRXQSETS(ctx); 6846 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6847 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6848 CTX_UNLOCK(ctx); 6849 } 6850 6851 static void 6852 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 6853 { 6854 if_ctx_t ctx; 6855 if_softc_ctx_t scctx; 6856 iflib_fl_t fl; 6857 iflib_rxq_t rxq; 6858 int i, j; 6859 6860 ctx = if_getsoftc(ifp); 6861 scctx = &ctx->ifc_softc_ctx; 6862 6863 switch (event) { 6864 case DEBUGNET_START: 6865 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6866 rxq = &ctx->ifc_rxqs[i]; 6867 for (j = 0; j < rxq->ifr_nfl; j++) { 6868 fl = rxq->ifr_fl; 6869 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6870 } 6871 } 6872 iflib_no_tx_batch = 1; 6873 break; 6874 default: 6875 break; 6876 } 6877 } 6878 6879 static int 6880 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 6881 { 6882 if_ctx_t ctx; 6883 iflib_txq_t txq; 6884 int error; 6885 6886 ctx = if_getsoftc(ifp); 6887 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6888 IFF_DRV_RUNNING) 6889 return (EBUSY); 6890 6891 txq = &ctx->ifc_txqs[0]; 6892 error = iflib_encap(txq, &m); 6893 if (error == 0) 6894 (void)iflib_txd_db_check(txq, true); 6895 return (error); 6896 } 6897 6898 static int 6899 iflib_debugnet_poll(if_t ifp, int count) 6900 { 6901 struct epoch_tracker et; 6902 if_ctx_t ctx; 6903 if_softc_ctx_t scctx; 6904 iflib_txq_t txq; 6905 int i; 6906 6907 ctx = if_getsoftc(ifp); 6908 scctx = &ctx->ifc_softc_ctx; 6909 6910 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6911 IFF_DRV_RUNNING) 6912 return (EBUSY); 6913 6914 txq = &ctx->ifc_txqs[0]; 6915 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6916 6917 NET_EPOCH_ENTER(et); 6918 for (i = 0; i < scctx->isc_nrxqsets; i++) 6919 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6920 NET_EPOCH_EXIT(et); 6921 return (0); 6922 } 6923 #endif /* DEBUGNET */ 6924