1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/pfil.h> 63 #include <net/vnet.h> 64 65 #include <netinet/in.h> 66 #include <netinet/in_pcb.h> 67 #include <netinet/tcp_lro.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/if_ether.h> 70 #include <netinet/ip.h> 71 #include <netinet/ip6.h> 72 #include <netinet/tcp.h> 73 #include <netinet/ip_var.h> 74 #include <netinet/netdump/netdump.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 120 /* 121 * File organization: 122 * - private structures 123 * - iflib private utility functions 124 * - ifnet functions 125 * - vlan registry and other exported functions 126 * - iflib public core functions 127 * 128 * 129 */ 130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 131 132 struct iflib_txq; 133 typedef struct iflib_txq *iflib_txq_t; 134 struct iflib_rxq; 135 typedef struct iflib_rxq *iflib_rxq_t; 136 struct iflib_fl; 137 typedef struct iflib_fl *iflib_fl_t; 138 139 struct iflib_ctx; 140 141 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 142 static void iflib_timer(void *arg); 143 144 typedef struct iflib_filter_info { 145 driver_filter_t *ifi_filter; 146 void *ifi_filter_arg; 147 struct grouptask *ifi_task; 148 void *ifi_ctx; 149 } *iflib_filter_info_t; 150 151 struct iflib_ctx { 152 KOBJ_FIELDS; 153 /* 154 * Pointer to hardware driver's softc 155 */ 156 void *ifc_softc; 157 device_t ifc_dev; 158 if_t ifc_ifp; 159 160 cpuset_t ifc_cpus; 161 if_shared_ctx_t ifc_sctx; 162 struct if_softc_ctx ifc_softc_ctx; 163 164 struct sx ifc_ctx_sx; 165 struct mtx ifc_state_mtx; 166 167 iflib_txq_t ifc_txqs; 168 iflib_rxq_t ifc_rxqs; 169 uint32_t ifc_if_flags; 170 uint32_t ifc_flags; 171 uint32_t ifc_max_fl_buf_size; 172 uint32_t ifc_rx_mbuf_sz; 173 174 int ifc_link_state; 175 int ifc_link_irq; 176 int ifc_watchdog_events; 177 struct cdev *ifc_led_dev; 178 struct resource *ifc_msix_mem; 179 180 struct if_irq ifc_legacy_irq; 181 struct grouptask ifc_admin_task; 182 struct grouptask ifc_vflr_task; 183 struct iflib_filter_info ifc_filter_info; 184 struct ifmedia ifc_media; 185 struct ifmedia *ifc_mediap; 186 187 struct sysctl_oid *ifc_sysctl_node; 188 uint16_t ifc_sysctl_ntxqs; 189 uint16_t ifc_sysctl_nrxqs; 190 uint16_t ifc_sysctl_qs_eq_override; 191 uint16_t ifc_sysctl_rx_budget; 192 uint16_t ifc_sysctl_tx_abdicate; 193 uint16_t ifc_sysctl_core_offset; 194 #define CORE_OFFSET_UNSPECIFIED 0xffff 195 uint8_t ifc_sysctl_separate_txrx; 196 197 qidx_t ifc_sysctl_ntxds[8]; 198 qidx_t ifc_sysctl_nrxds[8]; 199 struct if_txrx ifc_txrx; 200 #define isc_txd_encap ifc_txrx.ift_txd_encap 201 #define isc_txd_flush ifc_txrx.ift_txd_flush 202 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 203 #define isc_rxd_available ifc_txrx.ift_rxd_available 204 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 205 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 206 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 209 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 210 eventhandler_tag ifc_vlan_attach_event; 211 eventhandler_tag ifc_vlan_detach_event; 212 struct ether_addr ifc_mac; 213 char ifc_mtx_name[16]; 214 }; 215 216 217 void * 218 iflib_get_softc(if_ctx_t ctx) 219 { 220 221 return (ctx->ifc_softc); 222 } 223 224 device_t 225 iflib_get_dev(if_ctx_t ctx) 226 { 227 228 return (ctx->ifc_dev); 229 } 230 231 if_t 232 iflib_get_ifp(if_ctx_t ctx) 233 { 234 235 return (ctx->ifc_ifp); 236 } 237 238 struct ifmedia * 239 iflib_get_media(if_ctx_t ctx) 240 { 241 242 return (ctx->ifc_mediap); 243 } 244 245 uint32_t 246 iflib_get_flags(if_ctx_t ctx) 247 { 248 return (ctx->ifc_flags); 249 } 250 251 void 252 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 253 { 254 255 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 256 } 257 258 if_softc_ctx_t 259 iflib_get_softc_ctx(if_ctx_t ctx) 260 { 261 262 return (&ctx->ifc_softc_ctx); 263 } 264 265 if_shared_ctx_t 266 iflib_get_sctx(if_ctx_t ctx) 267 { 268 269 return (ctx->ifc_sctx); 270 } 271 272 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 273 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 274 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 275 276 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 277 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 278 279 typedef struct iflib_sw_rx_desc_array { 280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 281 struct mbuf **ifsd_m; /* pkthdr mbufs */ 282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 283 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 284 } iflib_rxsd_array_t; 285 286 typedef struct iflib_sw_tx_desc_array { 287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 288 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 289 struct mbuf **ifsd_m; /* pkthdr mbufs */ 290 } if_txsd_vec_t; 291 292 293 /* magic number that should be high enough for any hardware */ 294 #define IFLIB_MAX_TX_SEGS 128 295 #define IFLIB_RX_COPY_THRESH 128 296 #define IFLIB_MAX_RX_REFRESH 32 297 /* The minimum descriptors per second before we start coalescing */ 298 #define IFLIB_MIN_DESC_SEC 16384 299 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 300 #define IFLIB_QUEUE_IDLE 0 301 #define IFLIB_QUEUE_HUNG 1 302 #define IFLIB_QUEUE_WORKING 2 303 /* maximum number of txqs that can share an rx interrupt */ 304 #define IFLIB_MAX_TX_SHARED_INTR 4 305 306 /* this should really scale with ring size - this is a fairly arbitrary value */ 307 #define TX_BATCH_SIZE 32 308 309 #define IFLIB_RESTART_BUDGET 8 310 311 312 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 313 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 314 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 315 struct iflib_txq { 316 qidx_t ift_in_use; 317 qidx_t ift_cidx; 318 qidx_t ift_cidx_processed; 319 qidx_t ift_pidx; 320 uint8_t ift_gen; 321 uint8_t ift_br_offset; 322 uint16_t ift_npending; 323 uint16_t ift_db_pending; 324 uint16_t ift_rs_pending; 325 /* implicit pad */ 326 uint8_t ift_txd_size[8]; 327 uint64_t ift_processed; 328 uint64_t ift_cleaned; 329 uint64_t ift_cleaned_prev; 330 #if MEMORY_LOGGING 331 uint64_t ift_enqueued; 332 uint64_t ift_dequeued; 333 #endif 334 uint64_t ift_no_tx_dma_setup; 335 uint64_t ift_no_desc_avail; 336 uint64_t ift_mbuf_defrag_failed; 337 uint64_t ift_mbuf_defrag; 338 uint64_t ift_map_failed; 339 uint64_t ift_txd_encap_efbig; 340 uint64_t ift_pullups; 341 uint64_t ift_last_timer_tick; 342 343 struct mtx ift_mtx; 344 struct mtx ift_db_mtx; 345 346 /* constant values */ 347 if_ctx_t ift_ctx; 348 struct ifmp_ring *ift_br; 349 struct grouptask ift_task; 350 qidx_t ift_size; 351 uint16_t ift_id; 352 struct callout ift_timer; 353 354 if_txsd_vec_t ift_sds; 355 uint8_t ift_qstatus; 356 uint8_t ift_closed; 357 uint8_t ift_update_freq; 358 struct iflib_filter_info ift_filter_info; 359 bus_dma_tag_t ift_buf_tag; 360 bus_dma_tag_t ift_tso_buf_tag; 361 iflib_dma_info_t ift_ifdi; 362 #define MTX_NAME_LEN 16 363 char ift_mtx_name[MTX_NAME_LEN]; 364 char ift_db_mtx_name[MTX_NAME_LEN]; 365 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 366 #ifdef IFLIB_DIAGNOSTICS 367 uint64_t ift_cpu_exec_count[256]; 368 #endif 369 } __aligned(CACHE_LINE_SIZE); 370 371 struct iflib_fl { 372 qidx_t ifl_cidx; 373 qidx_t ifl_pidx; 374 qidx_t ifl_credits; 375 uint8_t ifl_gen; 376 uint8_t ifl_rxd_size; 377 #if MEMORY_LOGGING 378 uint64_t ifl_m_enqueued; 379 uint64_t ifl_m_dequeued; 380 uint64_t ifl_cl_enqueued; 381 uint64_t ifl_cl_dequeued; 382 #endif 383 /* implicit pad */ 384 385 bitstr_t *ifl_rx_bitmap; 386 qidx_t ifl_fragidx; 387 /* constant */ 388 qidx_t ifl_size; 389 uint16_t ifl_buf_size; 390 uint16_t ifl_cltype; 391 uma_zone_t ifl_zone; 392 iflib_rxsd_array_t ifl_sds; 393 iflib_rxq_t ifl_rxq; 394 uint8_t ifl_id; 395 bus_dma_tag_t ifl_buf_tag; 396 iflib_dma_info_t ifl_ifdi; 397 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 398 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 399 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 400 } __aligned(CACHE_LINE_SIZE); 401 402 static inline qidx_t 403 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 404 { 405 qidx_t used; 406 407 if (pidx > cidx) 408 used = pidx - cidx; 409 else if (pidx < cidx) 410 used = size - cidx + pidx; 411 else if (gen == 0 && pidx == cidx) 412 used = 0; 413 else if (gen == 1 && pidx == cidx) 414 used = size; 415 else 416 panic("bad state"); 417 418 return (used); 419 } 420 421 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 422 423 #define IDXDIFF(head, tail, wrap) \ 424 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 425 426 struct iflib_rxq { 427 /* If there is a separate completion queue - 428 * these are the cq cidx and pidx. Otherwise 429 * these are unused. 430 */ 431 qidx_t ifr_size; 432 qidx_t ifr_cq_cidx; 433 qidx_t ifr_cq_pidx; 434 uint8_t ifr_cq_gen; 435 uint8_t ifr_fl_offset; 436 437 if_ctx_t ifr_ctx; 438 iflib_fl_t ifr_fl; 439 uint64_t ifr_rx_irq; 440 struct pfil_head *pfil; 441 uint16_t ifr_id; 442 uint8_t ifr_lro_enabled; 443 uint8_t ifr_nfl; 444 uint8_t ifr_ntxqirq; 445 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 446 struct lro_ctrl ifr_lc; 447 struct grouptask ifr_task; 448 struct iflib_filter_info ifr_filter_info; 449 iflib_dma_info_t ifr_ifdi; 450 451 /* dynamically allocate if any drivers need a value substantially larger than this */ 452 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 453 #ifdef IFLIB_DIAGNOSTICS 454 uint64_t ifr_cpu_exec_count[256]; 455 #endif 456 } __aligned(CACHE_LINE_SIZE); 457 458 typedef struct if_rxsd { 459 caddr_t *ifsd_cl; 460 iflib_fl_t ifsd_fl; 461 qidx_t ifsd_cidx; 462 } *if_rxsd_t; 463 464 /* multiple of word size */ 465 #ifdef __LP64__ 466 #define PKT_INFO_SIZE 6 467 #define RXD_INFO_SIZE 5 468 #define PKT_TYPE uint64_t 469 #else 470 #define PKT_INFO_SIZE 11 471 #define RXD_INFO_SIZE 8 472 #define PKT_TYPE uint32_t 473 #endif 474 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 475 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 476 477 typedef struct if_pkt_info_pad { 478 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 479 } *if_pkt_info_pad_t; 480 typedef struct if_rxd_info_pad { 481 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 482 } *if_rxd_info_pad_t; 483 484 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 485 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 486 487 488 static inline void 489 pkt_info_zero(if_pkt_info_t pi) 490 { 491 if_pkt_info_pad_t pi_pad; 492 493 pi_pad = (if_pkt_info_pad_t)pi; 494 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 495 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 496 #ifndef __LP64__ 497 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 498 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 499 #endif 500 } 501 502 static device_method_t iflib_pseudo_methods[] = { 503 DEVMETHOD(device_attach, noop_attach), 504 DEVMETHOD(device_detach, iflib_pseudo_detach), 505 DEVMETHOD_END 506 }; 507 508 driver_t iflib_pseudodriver = { 509 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 510 }; 511 512 static inline void 513 rxd_info_zero(if_rxd_info_t ri) 514 { 515 if_rxd_info_pad_t ri_pad; 516 int i; 517 518 ri_pad = (if_rxd_info_pad_t)ri; 519 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 520 ri_pad->rxd_val[i] = 0; 521 ri_pad->rxd_val[i+1] = 0; 522 ri_pad->rxd_val[i+2] = 0; 523 ri_pad->rxd_val[i+3] = 0; 524 } 525 #ifdef __LP64__ 526 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 527 #endif 528 } 529 530 /* 531 * Only allow a single packet to take up most 1/nth of the tx ring 532 */ 533 #define MAX_SINGLE_PACKET_FRACTION 12 534 #define IF_BAD_DMA (bus_addr_t)-1 535 536 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 537 538 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 539 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 540 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 541 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 542 543 544 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 545 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 546 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 547 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 548 549 550 551 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 552 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 553 554 void 555 iflib_set_detach(if_ctx_t ctx) 556 { 557 STATE_LOCK(ctx); 558 ctx->ifc_flags |= IFC_IN_DETACH; 559 STATE_UNLOCK(ctx); 560 } 561 562 /* Our boot-time initialization hook */ 563 static int iflib_module_event_handler(module_t, int, void *); 564 565 static moduledata_t iflib_moduledata = { 566 "iflib", 567 iflib_module_event_handler, 568 NULL 569 }; 570 571 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 572 MODULE_VERSION(iflib, 1); 573 574 MODULE_DEPEND(iflib, pci, 1, 1, 1); 575 MODULE_DEPEND(iflib, ether, 1, 1, 1); 576 577 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 578 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 579 580 #ifndef IFLIB_DEBUG_COUNTERS 581 #ifdef INVARIANTS 582 #define IFLIB_DEBUG_COUNTERS 1 583 #else 584 #define IFLIB_DEBUG_COUNTERS 0 585 #endif /* !INVARIANTS */ 586 #endif 587 588 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 589 "iflib driver parameters"); 590 591 /* 592 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 593 */ 594 static int iflib_min_tx_latency = 0; 595 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 596 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 597 static int iflib_no_tx_batch = 0; 598 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 599 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 600 601 602 #if IFLIB_DEBUG_COUNTERS 603 604 static int iflib_tx_seen; 605 static int iflib_tx_sent; 606 static int iflib_tx_encap; 607 static int iflib_rx_allocs; 608 static int iflib_fl_refills; 609 static int iflib_fl_refills_large; 610 static int iflib_tx_frees; 611 612 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 613 &iflib_tx_seen, 0, "# tx mbufs seen"); 614 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 615 &iflib_tx_sent, 0, "# tx mbufs sent"); 616 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 617 &iflib_tx_encap, 0, "# tx mbufs encapped"); 618 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 619 &iflib_tx_frees, 0, "# tx frees"); 620 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 621 &iflib_rx_allocs, 0, "# rx allocations"); 622 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 623 &iflib_fl_refills, 0, "# refills"); 624 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 625 &iflib_fl_refills_large, 0, "# large refills"); 626 627 628 static int iflib_txq_drain_flushing; 629 static int iflib_txq_drain_oactive; 630 static int iflib_txq_drain_notready; 631 632 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 633 &iflib_txq_drain_flushing, 0, "# drain flushes"); 634 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 635 &iflib_txq_drain_oactive, 0, "# drain oactives"); 636 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 637 &iflib_txq_drain_notready, 0, "# drain notready"); 638 639 640 static int iflib_encap_load_mbuf_fail; 641 static int iflib_encap_pad_mbuf_fail; 642 static int iflib_encap_txq_avail_fail; 643 static int iflib_encap_txd_encap_fail; 644 645 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 646 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 647 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 648 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 649 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 650 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 651 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 652 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 653 654 static int iflib_task_fn_rxs; 655 static int iflib_rx_intr_enables; 656 static int iflib_fast_intrs; 657 static int iflib_rx_unavail; 658 static int iflib_rx_ctx_inactive; 659 static int iflib_rx_if_input; 660 static int iflib_rxd_flush; 661 662 static int iflib_verbose_debug; 663 664 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 665 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 666 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 667 &iflib_rx_intr_enables, 0, "# rx intr enables"); 668 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 669 &iflib_fast_intrs, 0, "# fast_intr calls"); 670 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 671 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 672 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 673 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 674 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 675 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 676 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 677 &iflib_rxd_flush, 0, "# times rxd_flush called"); 678 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 679 &iflib_verbose_debug, 0, "enable verbose debugging"); 680 681 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 682 static void 683 iflib_debug_reset(void) 684 { 685 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 686 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 687 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 688 iflib_txq_drain_notready = 689 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 690 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 691 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 692 iflib_rx_unavail = 693 iflib_rx_ctx_inactive = iflib_rx_if_input = 694 iflib_rxd_flush = 0; 695 } 696 697 #else 698 #define DBG_COUNTER_INC(name) 699 static void iflib_debug_reset(void) {} 700 #endif 701 702 #define IFLIB_DEBUG 0 703 704 static void iflib_tx_structures_free(if_ctx_t ctx); 705 static void iflib_rx_structures_free(if_ctx_t ctx); 706 static int iflib_queues_alloc(if_ctx_t ctx); 707 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 708 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 709 static int iflib_qset_structures_setup(if_ctx_t ctx); 710 static int iflib_msix_init(if_ctx_t ctx); 711 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 712 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 713 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 714 #ifdef ALTQ 715 static void iflib_altq_if_start(if_t ifp); 716 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 717 #endif 718 static int iflib_register(if_ctx_t); 719 static void iflib_init_locked(if_ctx_t ctx); 720 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 721 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 722 static void iflib_ifmp_purge(iflib_txq_t txq); 723 static void _iflib_pre_assert(if_softc_ctx_t scctx); 724 static void iflib_if_init_locked(if_ctx_t ctx); 725 static void iflib_free_intr_mem(if_ctx_t ctx); 726 #ifndef __NO_STRICT_ALIGNMENT 727 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 728 #endif 729 730 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 731 SLIST_HEAD_INITIALIZER(cpu_offsets); 732 struct cpu_offset { 733 SLIST_ENTRY(cpu_offset) entries; 734 cpuset_t set; 735 unsigned int refcount; 736 uint16_t offset; 737 }; 738 static struct mtx cpu_offset_mtx; 739 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 740 MTX_DEF); 741 742 NETDUMP_DEFINE(iflib); 743 744 #ifdef DEV_NETMAP 745 #include <sys/selinfo.h> 746 #include <net/netmap.h> 747 #include <dev/netmap/netmap_kern.h> 748 749 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 750 751 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 752 753 /* 754 * device-specific sysctl variables: 755 * 756 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 757 * During regular operations the CRC is stripped, but on some 758 * hardware reception of frames not multiple of 64 is slower, 759 * so using crcstrip=0 helps in benchmarks. 760 * 761 * iflib_rx_miss, iflib_rx_miss_bufs: 762 * count packets that might be missed due to lost interrupts. 763 */ 764 SYSCTL_DECL(_dev_netmap); 765 /* 766 * The xl driver by default strips CRCs and we do not override it. 767 */ 768 769 int iflib_crcstrip = 1; 770 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 771 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 772 773 int iflib_rx_miss, iflib_rx_miss_bufs; 774 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 775 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 776 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 777 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 778 779 /* 780 * Register/unregister. We are already under netmap lock. 781 * Only called on the first register or the last unregister. 782 */ 783 static int 784 iflib_netmap_register(struct netmap_adapter *na, int onoff) 785 { 786 struct ifnet *ifp = na->ifp; 787 if_ctx_t ctx = ifp->if_softc; 788 int status; 789 790 CTX_LOCK(ctx); 791 IFDI_INTR_DISABLE(ctx); 792 793 /* Tell the stack that the interface is no longer active */ 794 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 795 796 if (!CTX_IS_VF(ctx)) 797 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 798 799 /* enable or disable flags and callbacks in na and ifp */ 800 if (onoff) { 801 nm_set_native_flags(na); 802 } else { 803 nm_clear_native_flags(na); 804 } 805 iflib_stop(ctx); 806 iflib_init_locked(ctx); 807 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 808 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 809 if (status) 810 nm_clear_native_flags(na); 811 CTX_UNLOCK(ctx); 812 return (status); 813 } 814 815 static int 816 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 817 { 818 struct netmap_adapter *na = kring->na; 819 u_int const lim = kring->nkr_num_slots - 1; 820 u_int head = kring->rhead; 821 struct netmap_ring *ring = kring->ring; 822 bus_dmamap_t *map; 823 struct if_rxd_update iru; 824 if_ctx_t ctx = rxq->ifr_ctx; 825 iflib_fl_t fl = &rxq->ifr_fl[0]; 826 uint32_t refill_pidx, nic_i; 827 #if IFLIB_DEBUG_COUNTERS 828 int rf_count = 0; 829 #endif 830 831 if (nm_i == head && __predict_true(!init)) 832 return 0; 833 iru_init(&iru, rxq, 0 /* flid */); 834 map = fl->ifl_sds.ifsd_map; 835 refill_pidx = netmap_idx_k2n(kring, nm_i); 836 /* 837 * IMPORTANT: we must leave one free slot in the ring, 838 * so move head back by one unit 839 */ 840 head = nm_prev(head, lim); 841 nic_i = UINT_MAX; 842 DBG_COUNTER_INC(fl_refills); 843 while (nm_i != head) { 844 #if IFLIB_DEBUG_COUNTERS 845 if (++rf_count == 9) 846 DBG_COUNTER_INC(fl_refills_large); 847 #endif 848 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 849 struct netmap_slot *slot = &ring->slot[nm_i]; 850 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 851 uint32_t nic_i_dma = refill_pidx; 852 nic_i = netmap_idx_k2n(kring, nm_i); 853 854 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 855 856 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 857 return netmap_ring_reinit(kring); 858 859 fl->ifl_vm_addrs[tmp_pidx] = addr; 860 if (__predict_false(init)) { 861 netmap_load_map(na, fl->ifl_buf_tag, 862 map[nic_i], addr); 863 } else if (slot->flags & NS_BUF_CHANGED) { 864 /* buffer has changed, reload map */ 865 netmap_reload_map(na, fl->ifl_buf_tag, 866 map[nic_i], addr); 867 } 868 slot->flags &= ~NS_BUF_CHANGED; 869 870 nm_i = nm_next(nm_i, lim); 871 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 872 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 873 continue; 874 875 iru.iru_pidx = refill_pidx; 876 iru.iru_count = tmp_pidx+1; 877 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 878 refill_pidx = nic_i; 879 for (int n = 0; n < iru.iru_count; n++) { 880 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma], 881 BUS_DMASYNC_PREREAD); 882 /* XXX - change this to not use the netmap func*/ 883 nic_i_dma = nm_next(nic_i_dma, lim); 884 } 885 } 886 } 887 kring->nr_hwcur = head; 888 889 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 890 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 891 if (__predict_true(nic_i != UINT_MAX)) { 892 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 893 DBG_COUNTER_INC(rxd_flush); 894 } 895 return (0); 896 } 897 898 /* 899 * Reconcile kernel and user view of the transmit ring. 900 * 901 * All information is in the kring. 902 * Userspace wants to send packets up to the one before kring->rhead, 903 * kernel knows kring->nr_hwcur is the first unsent packet. 904 * 905 * Here we push packets out (as many as possible), and possibly 906 * reclaim buffers from previously completed transmission. 907 * 908 * The caller (netmap) guarantees that there is only one instance 909 * running at any time. Any interference with other driver 910 * methods should be handled by the individual drivers. 911 */ 912 static int 913 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 914 { 915 struct netmap_adapter *na = kring->na; 916 struct ifnet *ifp = na->ifp; 917 struct netmap_ring *ring = kring->ring; 918 u_int nm_i; /* index into the netmap kring */ 919 u_int nic_i; /* index into the NIC ring */ 920 u_int n; 921 u_int const lim = kring->nkr_num_slots - 1; 922 u_int const head = kring->rhead; 923 struct if_pkt_info pi; 924 925 /* 926 * interrupts on every tx packet are expensive so request 927 * them every half ring, or where NS_REPORT is set 928 */ 929 u_int report_frequency = kring->nkr_num_slots >> 1; 930 /* device-specific */ 931 if_ctx_t ctx = ifp->if_softc; 932 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 933 934 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 935 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 936 937 /* 938 * First part: process new packets to send. 939 * nm_i is the current index in the netmap kring, 940 * nic_i is the corresponding index in the NIC ring. 941 * 942 * If we have packets to send (nm_i != head) 943 * iterate over the netmap ring, fetch length and update 944 * the corresponding slot in the NIC ring. Some drivers also 945 * need to update the buffer's physical address in the NIC slot 946 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 947 * 948 * The netmap_reload_map() calls is especially expensive, 949 * even when (as in this case) the tag is 0, so do only 950 * when the buffer has actually changed. 951 * 952 * If possible do not set the report/intr bit on all slots, 953 * but only a few times per ring or when NS_REPORT is set. 954 * 955 * Finally, on 10G and faster drivers, it might be useful 956 * to prefetch the next slot and txr entry. 957 */ 958 959 nm_i = kring->nr_hwcur; 960 if (nm_i != head) { /* we have new packets to send */ 961 pkt_info_zero(&pi); 962 pi.ipi_segs = txq->ift_segs; 963 pi.ipi_qsidx = kring->ring_id; 964 nic_i = netmap_idx_k2n(kring, nm_i); 965 966 __builtin_prefetch(&ring->slot[nm_i]); 967 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 968 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 969 970 for (n = 0; nm_i != head; n++) { 971 struct netmap_slot *slot = &ring->slot[nm_i]; 972 u_int len = slot->len; 973 uint64_t paddr; 974 void *addr = PNMB(na, slot, &paddr); 975 int flags = (slot->flags & NS_REPORT || 976 nic_i == 0 || nic_i == report_frequency) ? 977 IPI_TX_INTR : 0; 978 979 /* device-specific */ 980 pi.ipi_len = len; 981 pi.ipi_segs[0].ds_addr = paddr; 982 pi.ipi_segs[0].ds_len = len; 983 pi.ipi_nsegs = 1; 984 pi.ipi_ndescs = 0; 985 pi.ipi_pidx = nic_i; 986 pi.ipi_flags = flags; 987 988 /* Fill the slot in the NIC ring. */ 989 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 990 DBG_COUNTER_INC(tx_encap); 991 992 /* prefetch for next round */ 993 __builtin_prefetch(&ring->slot[nm_i + 1]); 994 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 995 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 996 997 NM_CHECK_ADDR_LEN(na, addr, len); 998 999 if (slot->flags & NS_BUF_CHANGED) { 1000 /* buffer has changed, reload map */ 1001 netmap_reload_map(na, txq->ift_buf_tag, 1002 txq->ift_sds.ifsd_map[nic_i], addr); 1003 } 1004 /* make sure changes to the buffer are synced */ 1005 bus_dmamap_sync(txq->ift_buf_tag, 1006 txq->ift_sds.ifsd_map[nic_i], 1007 BUS_DMASYNC_PREWRITE); 1008 1009 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1010 nm_i = nm_next(nm_i, lim); 1011 nic_i = nm_next(nic_i, lim); 1012 } 1013 kring->nr_hwcur = nm_i; 1014 1015 /* synchronize the NIC ring */ 1016 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1017 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1018 1019 /* (re)start the tx unit up to slot nic_i (excluded) */ 1020 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1021 } 1022 1023 /* 1024 * Second part: reclaim buffers for completed transmissions. 1025 * 1026 * If there are unclaimed buffers, attempt to reclaim them. 1027 * If none are reclaimed, and TX IRQs are not in use, do an initial 1028 * minimal delay, then trigger the tx handler which will spin in the 1029 * group task queue. 1030 */ 1031 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1032 if (iflib_tx_credits_update(ctx, txq)) { 1033 /* some tx completed, increment avail */ 1034 nic_i = txq->ift_cidx_processed; 1035 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1036 } 1037 } 1038 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1039 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1040 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1041 iflib_timer, txq, txq->ift_timer.c_cpu); 1042 } 1043 return (0); 1044 } 1045 1046 /* 1047 * Reconcile kernel and user view of the receive ring. 1048 * Same as for the txsync, this routine must be efficient. 1049 * The caller guarantees a single invocations, but races against 1050 * the rest of the driver should be handled here. 1051 * 1052 * On call, kring->rhead is the first packet that userspace wants 1053 * to keep, and kring->rcur is the wakeup point. 1054 * The kernel has previously reported packets up to kring->rtail. 1055 * 1056 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1057 * of whether or not we received an interrupt. 1058 */ 1059 static int 1060 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1061 { 1062 struct netmap_adapter *na = kring->na; 1063 struct netmap_ring *ring = kring->ring; 1064 iflib_fl_t fl; 1065 uint32_t nm_i; /* index into the netmap ring */ 1066 uint32_t nic_i; /* index into the NIC ring */ 1067 u_int i, n; 1068 u_int const lim = kring->nkr_num_slots - 1; 1069 u_int const head = kring->rhead; 1070 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1071 struct if_rxd_info ri; 1072 1073 struct ifnet *ifp = na->ifp; 1074 if_ctx_t ctx = ifp->if_softc; 1075 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1076 if (head > lim) 1077 return netmap_ring_reinit(kring); 1078 1079 /* 1080 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far. 1081 */ 1082 1083 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1084 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1085 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1086 } 1087 1088 /* 1089 * First part: import newly received packets. 1090 * 1091 * nm_i is the index of the next free slot in the netmap ring, 1092 * nic_i is the index of the next received packet in the NIC ring, 1093 * and they may differ in case if_init() has been called while 1094 * in netmap mode. For the receive ring we have 1095 * 1096 * nic_i = rxr->next_check; 1097 * nm_i = kring->nr_hwtail (previous) 1098 * and 1099 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1100 * 1101 * rxr->next_check is set to 0 on a ring reinit 1102 */ 1103 if (netmap_no_pendintr || force_update) { 1104 int crclen = iflib_crcstrip ? 0 : 4; 1105 int error, avail; 1106 1107 for (i = 0; i < rxq->ifr_nfl; i++) { 1108 fl = &rxq->ifr_fl[i]; 1109 nic_i = fl->ifl_cidx; 1110 nm_i = netmap_idx_n2k(kring, nic_i); 1111 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1112 rxq->ifr_id, nic_i, USHRT_MAX); 1113 for (n = 0; avail > 0; n++, avail--) { 1114 rxd_info_zero(&ri); 1115 ri.iri_frags = rxq->ifr_frags; 1116 ri.iri_qsidx = kring->ring_id; 1117 ri.iri_ifp = ctx->ifc_ifp; 1118 ri.iri_cidx = nic_i; 1119 1120 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1121 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1122 ring->slot[nm_i].flags = 0; 1123 bus_dmamap_sync(fl->ifl_buf_tag, 1124 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1125 nm_i = nm_next(nm_i, lim); 1126 nic_i = nm_next(nic_i, lim); 1127 } 1128 if (n) { /* update the state variables */ 1129 if (netmap_no_pendintr && !force_update) { 1130 /* diagnostics */ 1131 iflib_rx_miss ++; 1132 iflib_rx_miss_bufs += n; 1133 } 1134 fl->ifl_cidx = nic_i; 1135 kring->nr_hwtail = nm_i; 1136 } 1137 kring->nr_kflags &= ~NKR_PENDINTR; 1138 } 1139 } 1140 /* 1141 * Second part: skip past packets that userspace has released. 1142 * (kring->nr_hwcur to head excluded), 1143 * and make the buffers available for reception. 1144 * As usual nm_i is the index in the netmap ring, 1145 * nic_i is the index in the NIC ring, and 1146 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1147 */ 1148 /* XXX not sure how this will work with multiple free lists */ 1149 nm_i = kring->nr_hwcur; 1150 1151 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1152 } 1153 1154 static void 1155 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1156 { 1157 struct ifnet *ifp = na->ifp; 1158 if_ctx_t ctx = ifp->if_softc; 1159 1160 CTX_LOCK(ctx); 1161 if (onoff) { 1162 IFDI_INTR_ENABLE(ctx); 1163 } else { 1164 IFDI_INTR_DISABLE(ctx); 1165 } 1166 CTX_UNLOCK(ctx); 1167 } 1168 1169 1170 static int 1171 iflib_netmap_attach(if_ctx_t ctx) 1172 { 1173 struct netmap_adapter na; 1174 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1175 1176 bzero(&na, sizeof(na)); 1177 1178 na.ifp = ctx->ifc_ifp; 1179 na.na_flags = NAF_BDG_MAYSLEEP; 1180 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1181 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1182 1183 na.num_tx_desc = scctx->isc_ntxd[0]; 1184 na.num_rx_desc = scctx->isc_nrxd[0]; 1185 na.nm_txsync = iflib_netmap_txsync; 1186 na.nm_rxsync = iflib_netmap_rxsync; 1187 na.nm_register = iflib_netmap_register; 1188 na.nm_intr = iflib_netmap_intr; 1189 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1190 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1191 return (netmap_attach(&na)); 1192 } 1193 1194 static void 1195 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1196 { 1197 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1198 struct netmap_slot *slot; 1199 1200 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1201 if (slot == NULL) 1202 return; 1203 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1204 1205 /* 1206 * In netmap mode, set the map for the packet buffer. 1207 * NOTE: Some drivers (not this one) also need to set 1208 * the physical buffer address in the NIC ring. 1209 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1210 * netmap slot index, si 1211 */ 1212 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1213 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1214 NMB(na, slot + si)); 1215 } 1216 } 1217 1218 static void 1219 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1220 { 1221 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1222 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1223 struct netmap_slot *slot; 1224 uint32_t nm_i; 1225 1226 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1227 if (slot == NULL) 1228 return; 1229 nm_i = netmap_idx_n2k(kring, 0); 1230 netmap_fl_refill(rxq, kring, nm_i, true); 1231 } 1232 1233 static void 1234 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on) 1235 { 1236 struct netmap_kring *kring; 1237 uint16_t txqid; 1238 1239 txqid = txq->ift_id; 1240 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1241 1242 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1243 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1244 BUS_DMASYNC_POSTREAD); 1245 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1246 netmap_tx_irq(ctx->ifc_ifp, txqid); 1247 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1248 if (hz < 2000) 1249 *reset_on = 1; 1250 else 1251 *reset_on = hz / 1000; 1252 } 1253 } 1254 } 1255 1256 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1257 1258 #else 1259 #define iflib_netmap_txq_init(ctx, txq) 1260 #define iflib_netmap_rxq_init(ctx, rxq) 1261 #define iflib_netmap_detach(ifp) 1262 1263 #define iflib_netmap_attach(ctx) (0) 1264 #define netmap_rx_irq(ifp, qid, budget) (0) 1265 #define netmap_tx_irq(ifp, qid) do {} while (0) 1266 #define iflib_netmap_timer_adjust(ctx, txq, reset_on) 1267 1268 #endif 1269 1270 #if defined(__i386__) || defined(__amd64__) 1271 static __inline void 1272 prefetch(void *x) 1273 { 1274 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1275 } 1276 static __inline void 1277 prefetch2cachelines(void *x) 1278 { 1279 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1280 #if (CACHE_LINE_SIZE < 128) 1281 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1282 #endif 1283 } 1284 #else 1285 #define prefetch(x) 1286 #define prefetch2cachelines(x) 1287 #endif 1288 1289 static void 1290 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1291 { 1292 iflib_fl_t fl; 1293 1294 fl = &rxq->ifr_fl[flid]; 1295 iru->iru_paddrs = fl->ifl_bus_addrs; 1296 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1297 iru->iru_idxs = fl->ifl_rxd_idxs; 1298 iru->iru_qsidx = rxq->ifr_id; 1299 iru->iru_buf_size = fl->ifl_buf_size; 1300 iru->iru_flidx = fl->ifl_id; 1301 } 1302 1303 static void 1304 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1305 { 1306 if (err) 1307 return; 1308 *(bus_addr_t *) arg = segs[0].ds_addr; 1309 } 1310 1311 int 1312 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1313 { 1314 int err; 1315 device_t dev = ctx->ifc_dev; 1316 1317 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1318 align, 0, /* alignment, bounds */ 1319 BUS_SPACE_MAXADDR, /* lowaddr */ 1320 BUS_SPACE_MAXADDR, /* highaddr */ 1321 NULL, NULL, /* filter, filterarg */ 1322 size, /* maxsize */ 1323 1, /* nsegments */ 1324 size, /* maxsegsize */ 1325 BUS_DMA_ALLOCNOW, /* flags */ 1326 NULL, /* lockfunc */ 1327 NULL, /* lockarg */ 1328 &dma->idi_tag); 1329 if (err) { 1330 device_printf(dev, 1331 "%s: bus_dma_tag_create failed: %d\n", 1332 __func__, err); 1333 goto fail_0; 1334 } 1335 1336 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1337 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1338 if (err) { 1339 device_printf(dev, 1340 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1341 __func__, (uintmax_t)size, err); 1342 goto fail_1; 1343 } 1344 1345 dma->idi_paddr = IF_BAD_DMA; 1346 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1347 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1348 if (err || dma->idi_paddr == IF_BAD_DMA) { 1349 device_printf(dev, 1350 "%s: bus_dmamap_load failed: %d\n", 1351 __func__, err); 1352 goto fail_2; 1353 } 1354 1355 dma->idi_size = size; 1356 return (0); 1357 1358 fail_2: 1359 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1360 fail_1: 1361 bus_dma_tag_destroy(dma->idi_tag); 1362 fail_0: 1363 dma->idi_tag = NULL; 1364 1365 return (err); 1366 } 1367 1368 int 1369 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1370 { 1371 if_shared_ctx_t sctx = ctx->ifc_sctx; 1372 1373 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1374 1375 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1376 } 1377 1378 int 1379 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1380 { 1381 int i, err; 1382 iflib_dma_info_t *dmaiter; 1383 1384 dmaiter = dmalist; 1385 for (i = 0; i < count; i++, dmaiter++) { 1386 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1387 break; 1388 } 1389 if (err) 1390 iflib_dma_free_multi(dmalist, i); 1391 return (err); 1392 } 1393 1394 void 1395 iflib_dma_free(iflib_dma_info_t dma) 1396 { 1397 if (dma->idi_tag == NULL) 1398 return; 1399 if (dma->idi_paddr != IF_BAD_DMA) { 1400 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1401 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1402 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1403 dma->idi_paddr = IF_BAD_DMA; 1404 } 1405 if (dma->idi_vaddr != NULL) { 1406 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1407 dma->idi_vaddr = NULL; 1408 } 1409 bus_dma_tag_destroy(dma->idi_tag); 1410 dma->idi_tag = NULL; 1411 } 1412 1413 void 1414 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1415 { 1416 int i; 1417 iflib_dma_info_t *dmaiter = dmalist; 1418 1419 for (i = 0; i < count; i++, dmaiter++) 1420 iflib_dma_free(*dmaiter); 1421 } 1422 1423 #ifdef EARLY_AP_STARTUP 1424 static const int iflib_started = 1; 1425 #else 1426 /* 1427 * We used to abuse the smp_started flag to decide if the queues have been 1428 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1429 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1430 * is set. Run a SYSINIT() strictly after that to just set a usable 1431 * completion flag. 1432 */ 1433 1434 static int iflib_started; 1435 1436 static void 1437 iflib_record_started(void *arg) 1438 { 1439 iflib_started = 1; 1440 } 1441 1442 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1443 iflib_record_started, NULL); 1444 #endif 1445 1446 static int 1447 iflib_fast_intr(void *arg) 1448 { 1449 iflib_filter_info_t info = arg; 1450 struct grouptask *gtask = info->ifi_task; 1451 int result; 1452 1453 if (!iflib_started) 1454 return (FILTER_STRAY); 1455 1456 DBG_COUNTER_INC(fast_intrs); 1457 if (info->ifi_filter != NULL) { 1458 result = info->ifi_filter(info->ifi_filter_arg); 1459 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1460 return (result); 1461 } 1462 1463 GROUPTASK_ENQUEUE(gtask); 1464 return (FILTER_HANDLED); 1465 } 1466 1467 static int 1468 iflib_fast_intr_rxtx(void *arg) 1469 { 1470 iflib_filter_info_t info = arg; 1471 struct grouptask *gtask = info->ifi_task; 1472 if_ctx_t ctx; 1473 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1474 iflib_txq_t txq; 1475 void *sc; 1476 int i, cidx, result; 1477 qidx_t txqid; 1478 1479 if (!iflib_started) 1480 return (FILTER_STRAY); 1481 1482 DBG_COUNTER_INC(fast_intrs); 1483 if (info->ifi_filter != NULL) { 1484 result = info->ifi_filter(info->ifi_filter_arg); 1485 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1486 return (result); 1487 } 1488 1489 ctx = rxq->ifr_ctx; 1490 sc = ctx->ifc_softc; 1491 MPASS(rxq->ifr_ntxqirq); 1492 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1493 txqid = rxq->ifr_txqid[i]; 1494 txq = &ctx->ifc_txqs[txqid]; 1495 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1496 BUS_DMASYNC_POSTREAD); 1497 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1498 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1499 continue; 1500 } 1501 GROUPTASK_ENQUEUE(&txq->ift_task); 1502 } 1503 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1504 cidx = rxq->ifr_cq_cidx; 1505 else 1506 cidx = rxq->ifr_fl[0].ifl_cidx; 1507 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1508 GROUPTASK_ENQUEUE(gtask); 1509 else { 1510 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1511 DBG_COUNTER_INC(rx_intr_enables); 1512 } 1513 return (FILTER_HANDLED); 1514 } 1515 1516 1517 static int 1518 iflib_fast_intr_ctx(void *arg) 1519 { 1520 iflib_filter_info_t info = arg; 1521 struct grouptask *gtask = info->ifi_task; 1522 int result; 1523 1524 if (!iflib_started) 1525 return (FILTER_STRAY); 1526 1527 DBG_COUNTER_INC(fast_intrs); 1528 if (info->ifi_filter != NULL) { 1529 result = info->ifi_filter(info->ifi_filter_arg); 1530 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1531 return (result); 1532 } 1533 1534 GROUPTASK_ENQUEUE(gtask); 1535 return (FILTER_HANDLED); 1536 } 1537 1538 static int 1539 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1540 driver_filter_t filter, driver_intr_t handler, void *arg, 1541 const char *name) 1542 { 1543 int rc, flags; 1544 struct resource *res; 1545 void *tag = NULL; 1546 device_t dev = ctx->ifc_dev; 1547 1548 flags = RF_ACTIVE; 1549 if (ctx->ifc_flags & IFC_LEGACY) 1550 flags |= RF_SHAREABLE; 1551 MPASS(rid < 512); 1552 irq->ii_rid = rid; 1553 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1554 if (res == NULL) { 1555 device_printf(dev, 1556 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1557 return (ENOMEM); 1558 } 1559 irq->ii_res = res; 1560 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1561 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1562 filter, handler, arg, &tag); 1563 if (rc != 0) { 1564 device_printf(dev, 1565 "failed to setup interrupt for rid %d, name %s: %d\n", 1566 rid, name ? name : "unknown", rc); 1567 return (rc); 1568 } else if (name) 1569 bus_describe_intr(dev, res, tag, "%s", name); 1570 1571 irq->ii_tag = tag; 1572 return (0); 1573 } 1574 1575 1576 /********************************************************************* 1577 * 1578 * Allocate DMA resources for TX buffers as well as memory for the TX 1579 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1580 * iflib_sw_tx_desc_array structure, storing all the information that 1581 * is needed to transmit a packet on the wire. This is called only 1582 * once at attach, setup is done every reset. 1583 * 1584 **********************************************************************/ 1585 static int 1586 iflib_txsd_alloc(iflib_txq_t txq) 1587 { 1588 if_ctx_t ctx = txq->ift_ctx; 1589 if_shared_ctx_t sctx = ctx->ifc_sctx; 1590 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1591 device_t dev = ctx->ifc_dev; 1592 bus_size_t tsomaxsize; 1593 int err, nsegments, ntsosegments; 1594 bool tso; 1595 1596 nsegments = scctx->isc_tx_nsegments; 1597 ntsosegments = scctx->isc_tx_tso_segments_max; 1598 tsomaxsize = scctx->isc_tx_tso_size_max; 1599 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1600 tsomaxsize += sizeof(struct ether_vlan_header); 1601 MPASS(scctx->isc_ntxd[0] > 0); 1602 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1603 MPASS(nsegments > 0); 1604 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1605 MPASS(ntsosegments > 0); 1606 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1607 } 1608 1609 /* 1610 * Set up DMA tags for TX buffers. 1611 */ 1612 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1613 1, 0, /* alignment, bounds */ 1614 BUS_SPACE_MAXADDR, /* lowaddr */ 1615 BUS_SPACE_MAXADDR, /* highaddr */ 1616 NULL, NULL, /* filter, filterarg */ 1617 sctx->isc_tx_maxsize, /* maxsize */ 1618 nsegments, /* nsegments */ 1619 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1620 0, /* flags */ 1621 NULL, /* lockfunc */ 1622 NULL, /* lockfuncarg */ 1623 &txq->ift_buf_tag))) { 1624 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1625 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1626 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1627 goto fail; 1628 } 1629 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1630 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1631 1, 0, /* alignment, bounds */ 1632 BUS_SPACE_MAXADDR, /* lowaddr */ 1633 BUS_SPACE_MAXADDR, /* highaddr */ 1634 NULL, NULL, /* filter, filterarg */ 1635 tsomaxsize, /* maxsize */ 1636 ntsosegments, /* nsegments */ 1637 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1638 0, /* flags */ 1639 NULL, /* lockfunc */ 1640 NULL, /* lockfuncarg */ 1641 &txq->ift_tso_buf_tag))) { 1642 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1643 err); 1644 goto fail; 1645 } 1646 1647 /* Allocate memory for the TX mbuf map. */ 1648 if (!(txq->ift_sds.ifsd_m = 1649 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1650 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1651 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1652 err = ENOMEM; 1653 goto fail; 1654 } 1655 1656 /* 1657 * Create the DMA maps for TX buffers. 1658 */ 1659 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1660 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1661 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1662 device_printf(dev, 1663 "Unable to allocate TX buffer DMA map memory\n"); 1664 err = ENOMEM; 1665 goto fail; 1666 } 1667 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1668 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1669 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1670 device_printf(dev, 1671 "Unable to allocate TSO TX buffer map memory\n"); 1672 err = ENOMEM; 1673 goto fail; 1674 } 1675 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1676 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1677 &txq->ift_sds.ifsd_map[i]); 1678 if (err != 0) { 1679 device_printf(dev, "Unable to create TX DMA map\n"); 1680 goto fail; 1681 } 1682 if (!tso) 1683 continue; 1684 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1685 &txq->ift_sds.ifsd_tso_map[i]); 1686 if (err != 0) { 1687 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1688 goto fail; 1689 } 1690 } 1691 return (0); 1692 fail: 1693 /* We free all, it handles case where we are in the middle */ 1694 iflib_tx_structures_free(ctx); 1695 return (err); 1696 } 1697 1698 static void 1699 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1700 { 1701 bus_dmamap_t map; 1702 1703 map = NULL; 1704 if (txq->ift_sds.ifsd_map != NULL) 1705 map = txq->ift_sds.ifsd_map[i]; 1706 if (map != NULL) { 1707 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1708 bus_dmamap_unload(txq->ift_buf_tag, map); 1709 bus_dmamap_destroy(txq->ift_buf_tag, map); 1710 txq->ift_sds.ifsd_map[i] = NULL; 1711 } 1712 1713 map = NULL; 1714 if (txq->ift_sds.ifsd_tso_map != NULL) 1715 map = txq->ift_sds.ifsd_tso_map[i]; 1716 if (map != NULL) { 1717 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1718 BUS_DMASYNC_POSTWRITE); 1719 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1720 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1721 txq->ift_sds.ifsd_tso_map[i] = NULL; 1722 } 1723 } 1724 1725 static void 1726 iflib_txq_destroy(iflib_txq_t txq) 1727 { 1728 if_ctx_t ctx = txq->ift_ctx; 1729 1730 for (int i = 0; i < txq->ift_size; i++) 1731 iflib_txsd_destroy(ctx, txq, i); 1732 if (txq->ift_sds.ifsd_map != NULL) { 1733 free(txq->ift_sds.ifsd_map, M_IFLIB); 1734 txq->ift_sds.ifsd_map = NULL; 1735 } 1736 if (txq->ift_sds.ifsd_tso_map != NULL) { 1737 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1738 txq->ift_sds.ifsd_tso_map = NULL; 1739 } 1740 if (txq->ift_sds.ifsd_m != NULL) { 1741 free(txq->ift_sds.ifsd_m, M_IFLIB); 1742 txq->ift_sds.ifsd_m = NULL; 1743 } 1744 if (txq->ift_buf_tag != NULL) { 1745 bus_dma_tag_destroy(txq->ift_buf_tag); 1746 txq->ift_buf_tag = NULL; 1747 } 1748 if (txq->ift_tso_buf_tag != NULL) { 1749 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1750 txq->ift_tso_buf_tag = NULL; 1751 } 1752 } 1753 1754 static void 1755 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1756 { 1757 struct mbuf **mp; 1758 1759 mp = &txq->ift_sds.ifsd_m[i]; 1760 if (*mp == NULL) 1761 return; 1762 1763 if (txq->ift_sds.ifsd_map != NULL) { 1764 bus_dmamap_sync(txq->ift_buf_tag, 1765 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1766 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1767 } 1768 if (txq->ift_sds.ifsd_tso_map != NULL) { 1769 bus_dmamap_sync(txq->ift_tso_buf_tag, 1770 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1771 bus_dmamap_unload(txq->ift_tso_buf_tag, 1772 txq->ift_sds.ifsd_tso_map[i]); 1773 } 1774 m_free(*mp); 1775 DBG_COUNTER_INC(tx_frees); 1776 *mp = NULL; 1777 } 1778 1779 static int 1780 iflib_txq_setup(iflib_txq_t txq) 1781 { 1782 if_ctx_t ctx = txq->ift_ctx; 1783 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1784 if_shared_ctx_t sctx = ctx->ifc_sctx; 1785 iflib_dma_info_t di; 1786 int i; 1787 1788 /* Set number of descriptors available */ 1789 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1790 /* XXX make configurable */ 1791 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1792 1793 /* Reset indices */ 1794 txq->ift_cidx_processed = 0; 1795 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1796 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1797 1798 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1799 bzero((void *)di->idi_vaddr, di->idi_size); 1800 1801 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1802 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1803 bus_dmamap_sync(di->idi_tag, di->idi_map, 1804 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1805 return (0); 1806 } 1807 1808 /********************************************************************* 1809 * 1810 * Allocate DMA resources for RX buffers as well as memory for the RX 1811 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1812 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1813 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1814 * Since we use use one entry in iflib_sw_rx_desc_array per received 1815 * packet, the maximum number of entries we'll need is equal to the 1816 * number of hardware receive descriptors that we've allocated. 1817 * 1818 **********************************************************************/ 1819 static int 1820 iflib_rxsd_alloc(iflib_rxq_t rxq) 1821 { 1822 if_ctx_t ctx = rxq->ifr_ctx; 1823 if_shared_ctx_t sctx = ctx->ifc_sctx; 1824 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1825 device_t dev = ctx->ifc_dev; 1826 iflib_fl_t fl; 1827 int err; 1828 1829 MPASS(scctx->isc_nrxd[0] > 0); 1830 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1831 1832 fl = rxq->ifr_fl; 1833 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1834 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1835 /* Set up DMA tag for RX buffers. */ 1836 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1837 1, 0, /* alignment, bounds */ 1838 BUS_SPACE_MAXADDR, /* lowaddr */ 1839 BUS_SPACE_MAXADDR, /* highaddr */ 1840 NULL, NULL, /* filter, filterarg */ 1841 sctx->isc_rx_maxsize, /* maxsize */ 1842 sctx->isc_rx_nsegments, /* nsegments */ 1843 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1844 0, /* flags */ 1845 NULL, /* lockfunc */ 1846 NULL, /* lockarg */ 1847 &fl->ifl_buf_tag); 1848 if (err) { 1849 device_printf(dev, 1850 "Unable to allocate RX DMA tag: %d\n", err); 1851 goto fail; 1852 } 1853 1854 /* Allocate memory for the RX mbuf map. */ 1855 if (!(fl->ifl_sds.ifsd_m = 1856 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1857 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1858 device_printf(dev, 1859 "Unable to allocate RX mbuf map memory\n"); 1860 err = ENOMEM; 1861 goto fail; 1862 } 1863 1864 /* Allocate memory for the direct RX cluster pointer map. */ 1865 if (!(fl->ifl_sds.ifsd_cl = 1866 (caddr_t *) malloc(sizeof(caddr_t) * 1867 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1868 device_printf(dev, 1869 "Unable to allocate RX cluster map memory\n"); 1870 err = ENOMEM; 1871 goto fail; 1872 } 1873 1874 /* Allocate memory for the RX cluster bus address map. */ 1875 if (!(fl->ifl_sds.ifsd_ba = 1876 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1877 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1878 device_printf(dev, 1879 "Unable to allocate RX bus address map memory\n"); 1880 err = ENOMEM; 1881 goto fail; 1882 } 1883 1884 /* 1885 * Create the DMA maps for RX buffers. 1886 */ 1887 if (!(fl->ifl_sds.ifsd_map = 1888 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1889 device_printf(dev, 1890 "Unable to allocate RX buffer DMA map memory\n"); 1891 err = ENOMEM; 1892 goto fail; 1893 } 1894 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1895 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1896 &fl->ifl_sds.ifsd_map[i]); 1897 if (err != 0) { 1898 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1899 goto fail; 1900 } 1901 } 1902 } 1903 return (0); 1904 1905 fail: 1906 iflib_rx_structures_free(ctx); 1907 return (err); 1908 } 1909 1910 1911 /* 1912 * Internal service routines 1913 */ 1914 1915 struct rxq_refill_cb_arg { 1916 int error; 1917 bus_dma_segment_t seg; 1918 int nseg; 1919 }; 1920 1921 static void 1922 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1923 { 1924 struct rxq_refill_cb_arg *cb_arg = arg; 1925 1926 cb_arg->error = error; 1927 cb_arg->seg = segs[0]; 1928 cb_arg->nseg = nseg; 1929 } 1930 1931 /** 1932 * rxq_refill - refill an rxq free-buffer list 1933 * @ctx: the iflib context 1934 * @rxq: the free-list to refill 1935 * @n: the number of new buffers to allocate 1936 * 1937 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1938 * The caller must assure that @n does not exceed the queue's capacity. 1939 */ 1940 static void 1941 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1942 { 1943 struct if_rxd_update iru; 1944 struct rxq_refill_cb_arg cb_arg; 1945 struct mbuf *m; 1946 caddr_t cl, *sd_cl; 1947 struct mbuf **sd_m; 1948 bus_dmamap_t *sd_map; 1949 bus_addr_t bus_addr, *sd_ba; 1950 int err, frag_idx, i, idx, n, pidx; 1951 qidx_t credits; 1952 1953 sd_m = fl->ifl_sds.ifsd_m; 1954 sd_map = fl->ifl_sds.ifsd_map; 1955 sd_cl = fl->ifl_sds.ifsd_cl; 1956 sd_ba = fl->ifl_sds.ifsd_ba; 1957 pidx = fl->ifl_pidx; 1958 idx = pidx; 1959 frag_idx = fl->ifl_fragidx; 1960 credits = fl->ifl_credits; 1961 1962 i = 0; 1963 n = count; 1964 MPASS(n > 0); 1965 MPASS(credits + n <= fl->ifl_size); 1966 1967 if (pidx < fl->ifl_cidx) 1968 MPASS(pidx + n <= fl->ifl_cidx); 1969 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1970 MPASS(fl->ifl_gen == 0); 1971 if (pidx > fl->ifl_cidx) 1972 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1973 1974 DBG_COUNTER_INC(fl_refills); 1975 if (n > 8) 1976 DBG_COUNTER_INC(fl_refills_large); 1977 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1978 while (n--) { 1979 /* 1980 * We allocate an uninitialized mbuf + cluster, mbuf is 1981 * initialized after rx. 1982 * 1983 * If the cluster is still set then we know a minimum sized packet was received 1984 */ 1985 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 1986 &frag_idx); 1987 if (frag_idx < 0) 1988 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1989 MPASS(frag_idx >= 0); 1990 if ((cl = sd_cl[frag_idx]) == NULL) { 1991 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1992 break; 1993 1994 cb_arg.error = 0; 1995 MPASS(sd_map != NULL); 1996 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 1997 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 1998 BUS_DMA_NOWAIT); 1999 if (err != 0 || cb_arg.error) { 2000 /* 2001 * !zone_pack ? 2002 */ 2003 if (fl->ifl_zone == zone_pack) 2004 uma_zfree(fl->ifl_zone, cl); 2005 break; 2006 } 2007 2008 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2009 sd_cl[frag_idx] = cl; 2010 #if MEMORY_LOGGING 2011 fl->ifl_cl_enqueued++; 2012 #endif 2013 } else { 2014 bus_addr = sd_ba[frag_idx]; 2015 } 2016 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2017 BUS_DMASYNC_PREREAD); 2018 2019 if (sd_m[frag_idx] == NULL) { 2020 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 2021 break; 2022 } 2023 sd_m[frag_idx] = m; 2024 } 2025 bit_set(fl->ifl_rx_bitmap, frag_idx); 2026 #if MEMORY_LOGGING 2027 fl->ifl_m_enqueued++; 2028 #endif 2029 2030 DBG_COUNTER_INC(rx_allocs); 2031 fl->ifl_rxd_idxs[i] = frag_idx; 2032 fl->ifl_bus_addrs[i] = bus_addr; 2033 fl->ifl_vm_addrs[i] = cl; 2034 credits++; 2035 i++; 2036 MPASS(credits <= fl->ifl_size); 2037 if (++idx == fl->ifl_size) { 2038 fl->ifl_gen = 1; 2039 idx = 0; 2040 } 2041 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2042 iru.iru_pidx = pidx; 2043 iru.iru_count = i; 2044 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2045 i = 0; 2046 pidx = idx; 2047 fl->ifl_pidx = idx; 2048 fl->ifl_credits = credits; 2049 } 2050 } 2051 2052 if (i) { 2053 iru.iru_pidx = pidx; 2054 iru.iru_count = i; 2055 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2056 fl->ifl_pidx = idx; 2057 fl->ifl_credits = credits; 2058 } 2059 DBG_COUNTER_INC(rxd_flush); 2060 if (fl->ifl_pidx == 0) 2061 pidx = fl->ifl_size - 1; 2062 else 2063 pidx = fl->ifl_pidx - 1; 2064 2065 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2066 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2067 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2068 fl->ifl_fragidx = frag_idx; 2069 } 2070 2071 static __inline void 2072 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2073 { 2074 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2075 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2076 #ifdef INVARIANTS 2077 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2078 #endif 2079 2080 MPASS(fl->ifl_credits <= fl->ifl_size); 2081 MPASS(reclaimable == delta); 2082 2083 if (reclaimable > 0) 2084 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2085 } 2086 2087 uint8_t 2088 iflib_in_detach(if_ctx_t ctx) 2089 { 2090 bool in_detach; 2091 STATE_LOCK(ctx); 2092 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2093 STATE_UNLOCK(ctx); 2094 return (in_detach); 2095 } 2096 2097 static void 2098 iflib_fl_bufs_free(iflib_fl_t fl) 2099 { 2100 iflib_dma_info_t idi = fl->ifl_ifdi; 2101 bus_dmamap_t sd_map; 2102 uint32_t i; 2103 2104 for (i = 0; i < fl->ifl_size; i++) { 2105 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2106 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2107 2108 if (*sd_cl != NULL) { 2109 sd_map = fl->ifl_sds.ifsd_map[i]; 2110 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2111 BUS_DMASYNC_POSTREAD); 2112 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2113 if (*sd_cl != NULL) 2114 uma_zfree(fl->ifl_zone, *sd_cl); 2115 // XXX: Should this get moved out? 2116 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx)) 2117 bus_dmamap_destroy(fl->ifl_buf_tag, sd_map); 2118 if (*sd_m != NULL) { 2119 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2120 uma_zfree(zone_mbuf, *sd_m); 2121 } 2122 } else { 2123 MPASS(*sd_cl == NULL); 2124 MPASS(*sd_m == NULL); 2125 } 2126 #if MEMORY_LOGGING 2127 fl->ifl_m_dequeued++; 2128 fl->ifl_cl_dequeued++; 2129 #endif 2130 *sd_cl = NULL; 2131 *sd_m = NULL; 2132 } 2133 #ifdef INVARIANTS 2134 for (i = 0; i < fl->ifl_size; i++) { 2135 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2136 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2137 } 2138 #endif 2139 /* 2140 * Reset free list values 2141 */ 2142 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2143 bzero(idi->idi_vaddr, idi->idi_size); 2144 } 2145 2146 /********************************************************************* 2147 * 2148 * Initialize a receive ring and its buffers. 2149 * 2150 **********************************************************************/ 2151 static int 2152 iflib_fl_setup(iflib_fl_t fl) 2153 { 2154 iflib_rxq_t rxq = fl->ifl_rxq; 2155 if_ctx_t ctx = rxq->ifr_ctx; 2156 2157 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2158 /* 2159 ** Free current RX buffer structs and their mbufs 2160 */ 2161 iflib_fl_bufs_free(fl); 2162 /* Now replenish the mbufs */ 2163 MPASS(fl->ifl_credits == 0); 2164 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2165 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2166 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2167 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2168 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2169 2170 2171 /* avoid pre-allocating zillions of clusters to an idle card 2172 * potentially speeding up attach 2173 */ 2174 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2175 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2176 if (min(128, fl->ifl_size) != fl->ifl_credits) 2177 return (ENOBUFS); 2178 /* 2179 * handle failure 2180 */ 2181 MPASS(rxq != NULL); 2182 MPASS(fl->ifl_ifdi != NULL); 2183 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2184 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2185 return (0); 2186 } 2187 2188 /********************************************************************* 2189 * 2190 * Free receive ring data structures 2191 * 2192 **********************************************************************/ 2193 static void 2194 iflib_rx_sds_free(iflib_rxq_t rxq) 2195 { 2196 iflib_fl_t fl; 2197 int i, j; 2198 2199 if (rxq->ifr_fl != NULL) { 2200 for (i = 0; i < rxq->ifr_nfl; i++) { 2201 fl = &rxq->ifr_fl[i]; 2202 if (fl->ifl_buf_tag != NULL) { 2203 if (fl->ifl_sds.ifsd_map != NULL) { 2204 for (j = 0; j < fl->ifl_size; j++) { 2205 if (fl->ifl_sds.ifsd_map[j] == 2206 NULL) 2207 continue; 2208 bus_dmamap_sync( 2209 fl->ifl_buf_tag, 2210 fl->ifl_sds.ifsd_map[j], 2211 BUS_DMASYNC_POSTREAD); 2212 bus_dmamap_unload( 2213 fl->ifl_buf_tag, 2214 fl->ifl_sds.ifsd_map[j]); 2215 } 2216 } 2217 bus_dma_tag_destroy(fl->ifl_buf_tag); 2218 fl->ifl_buf_tag = NULL; 2219 } 2220 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2221 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2222 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2223 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2224 fl->ifl_sds.ifsd_m = NULL; 2225 fl->ifl_sds.ifsd_cl = NULL; 2226 fl->ifl_sds.ifsd_ba = NULL; 2227 fl->ifl_sds.ifsd_map = NULL; 2228 } 2229 free(rxq->ifr_fl, M_IFLIB); 2230 rxq->ifr_fl = NULL; 2231 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2232 } 2233 } 2234 2235 /* 2236 * MI independent logic 2237 * 2238 */ 2239 static void 2240 iflib_timer(void *arg) 2241 { 2242 iflib_txq_t txq = arg; 2243 if_ctx_t ctx = txq->ift_ctx; 2244 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2245 uint64_t this_tick = ticks; 2246 uint32_t reset_on = hz / 2; 2247 2248 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2249 return; 2250 /* 2251 ** Check on the state of the TX queue(s), this 2252 ** can be done without the lock because its RO 2253 ** and the HUNG state will be static if set. 2254 */ 2255 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2256 txq->ift_last_timer_tick = this_tick; 2257 IFDI_TIMER(ctx, txq->ift_id); 2258 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2259 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2260 (sctx->isc_pause_frames == 0))) 2261 goto hung; 2262 2263 if (ifmp_ring_is_stalled(txq->ift_br)) 2264 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2265 txq->ift_cleaned_prev = txq->ift_cleaned; 2266 } 2267 #ifdef DEV_NETMAP 2268 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2269 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 2270 #endif 2271 /* handle any laggards */ 2272 if (txq->ift_db_pending) 2273 GROUPTASK_ENQUEUE(&txq->ift_task); 2274 2275 sctx->isc_pause_frames = 0; 2276 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2277 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2278 return; 2279 hung: 2280 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2281 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2282 STATE_LOCK(ctx); 2283 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2284 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2285 iflib_admin_intr_deferred(ctx); 2286 STATE_UNLOCK(ctx); 2287 } 2288 2289 static void 2290 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2291 { 2292 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2293 2294 /* 2295 * XXX don't set the max_frame_size to larger 2296 * than the hardware can handle 2297 */ 2298 if (sctx->isc_max_frame_size <= MCLBYTES) 2299 ctx->ifc_rx_mbuf_sz = MCLBYTES; 2300 else 2301 ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE; 2302 } 2303 2304 uint32_t 2305 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2306 { 2307 return (ctx->ifc_rx_mbuf_sz); 2308 } 2309 2310 static void 2311 iflib_init_locked(if_ctx_t ctx) 2312 { 2313 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2314 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2315 if_t ifp = ctx->ifc_ifp; 2316 iflib_fl_t fl; 2317 iflib_txq_t txq; 2318 iflib_rxq_t rxq; 2319 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2320 2321 2322 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2323 IFDI_INTR_DISABLE(ctx); 2324 2325 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2326 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2327 /* Set hardware offload abilities */ 2328 if_clearhwassist(ifp); 2329 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2330 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2331 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2332 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2333 if (if_getcapenable(ifp) & IFCAP_TSO4) 2334 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2335 if (if_getcapenable(ifp) & IFCAP_TSO6) 2336 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2337 2338 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2339 CALLOUT_LOCK(txq); 2340 callout_stop(&txq->ift_timer); 2341 CALLOUT_UNLOCK(txq); 2342 iflib_netmap_txq_init(ctx, txq); 2343 } 2344 2345 /* 2346 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2347 * that drivers can use the value when setting up the hardware receive 2348 * buffers. 2349 */ 2350 iflib_calc_rx_mbuf_sz(ctx); 2351 2352 #ifdef INVARIANTS 2353 i = if_getdrvflags(ifp); 2354 #endif 2355 IFDI_INIT(ctx); 2356 MPASS(if_getdrvflags(ifp) == i); 2357 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2358 /* XXX this should really be done on a per-queue basis */ 2359 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2360 MPASS(rxq->ifr_id == i); 2361 iflib_netmap_rxq_init(ctx, rxq); 2362 continue; 2363 } 2364 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2365 if (iflib_fl_setup(fl)) { 2366 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2367 goto done; 2368 } 2369 } 2370 } 2371 done: 2372 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2373 IFDI_INTR_ENABLE(ctx); 2374 txq = ctx->ifc_txqs; 2375 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2376 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2377 txq->ift_timer.c_cpu); 2378 } 2379 2380 static int 2381 iflib_media_change(if_t ifp) 2382 { 2383 if_ctx_t ctx = if_getsoftc(ifp); 2384 int err; 2385 2386 CTX_LOCK(ctx); 2387 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2388 iflib_init_locked(ctx); 2389 CTX_UNLOCK(ctx); 2390 return (err); 2391 } 2392 2393 static void 2394 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2395 { 2396 if_ctx_t ctx = if_getsoftc(ifp); 2397 2398 CTX_LOCK(ctx); 2399 IFDI_UPDATE_ADMIN_STATUS(ctx); 2400 IFDI_MEDIA_STATUS(ctx, ifmr); 2401 CTX_UNLOCK(ctx); 2402 } 2403 2404 void 2405 iflib_stop(if_ctx_t ctx) 2406 { 2407 iflib_txq_t txq = ctx->ifc_txqs; 2408 iflib_rxq_t rxq = ctx->ifc_rxqs; 2409 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2410 if_shared_ctx_t sctx = ctx->ifc_sctx; 2411 iflib_dma_info_t di; 2412 iflib_fl_t fl; 2413 int i, j; 2414 2415 /* Tell the stack that the interface is no longer active */ 2416 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2417 2418 IFDI_INTR_DISABLE(ctx); 2419 DELAY(1000); 2420 IFDI_STOP(ctx); 2421 DELAY(1000); 2422 2423 iflib_debug_reset(); 2424 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2425 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2426 /* make sure all transmitters have completed before proceeding XXX */ 2427 2428 CALLOUT_LOCK(txq); 2429 callout_stop(&txq->ift_timer); 2430 CALLOUT_UNLOCK(txq); 2431 2432 /* clean any enqueued buffers */ 2433 iflib_ifmp_purge(txq); 2434 /* Free any existing tx buffers. */ 2435 for (j = 0; j < txq->ift_size; j++) { 2436 iflib_txsd_free(ctx, txq, j); 2437 } 2438 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2439 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2440 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2441 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2442 txq->ift_pullups = 0; 2443 ifmp_ring_reset_stats(txq->ift_br); 2444 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2445 bzero((void *)di->idi_vaddr, di->idi_size); 2446 } 2447 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2448 /* make sure all transmitters have completed before proceeding XXX */ 2449 2450 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2451 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2452 bzero((void *)di->idi_vaddr, di->idi_size); 2453 /* also resets the free lists pidx/cidx */ 2454 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2455 iflib_fl_bufs_free(fl); 2456 } 2457 } 2458 2459 static inline caddr_t 2460 calc_next_rxd(iflib_fl_t fl, int cidx) 2461 { 2462 qidx_t size; 2463 int nrxd; 2464 caddr_t start, end, cur, next; 2465 2466 nrxd = fl->ifl_size; 2467 size = fl->ifl_rxd_size; 2468 start = fl->ifl_ifdi->idi_vaddr; 2469 2470 if (__predict_false(size == 0)) 2471 return (start); 2472 cur = start + size*cidx; 2473 end = start + size*nrxd; 2474 next = CACHE_PTR_NEXT(cur); 2475 return (next < end ? next : start); 2476 } 2477 2478 static inline void 2479 prefetch_pkts(iflib_fl_t fl, int cidx) 2480 { 2481 int nextptr; 2482 int nrxd = fl->ifl_size; 2483 caddr_t next_rxd; 2484 2485 2486 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2487 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2488 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2489 next_rxd = calc_next_rxd(fl, cidx); 2490 prefetch(next_rxd); 2491 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2492 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2493 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2494 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2495 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2496 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2497 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2498 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2499 } 2500 2501 static struct mbuf * 2502 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2503 int *pf_rv, if_rxd_info_t ri) 2504 { 2505 bus_dmamap_t map; 2506 iflib_fl_t fl; 2507 caddr_t payload; 2508 struct mbuf *m; 2509 int flid, cidx, len, next; 2510 2511 map = NULL; 2512 flid = irf->irf_flid; 2513 cidx = irf->irf_idx; 2514 fl = &rxq->ifr_fl[flid]; 2515 sd->ifsd_fl = fl; 2516 sd->ifsd_cidx = cidx; 2517 m = fl->ifl_sds.ifsd_m[cidx]; 2518 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2519 fl->ifl_credits--; 2520 #if MEMORY_LOGGING 2521 fl->ifl_m_dequeued++; 2522 #endif 2523 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2524 prefetch_pkts(fl, cidx); 2525 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2526 prefetch(&fl->ifl_sds.ifsd_map[next]); 2527 map = fl->ifl_sds.ifsd_map[cidx]; 2528 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2529 2530 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2531 MPASS(fl->ifl_cidx == cidx); 2532 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2533 2534 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL) { 2535 payload = *sd->ifsd_cl; 2536 payload += ri->iri_pad; 2537 len = ri->iri_len - ri->iri_pad; 2538 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2539 len | PFIL_MEMPTR | PFIL_IN, NULL); 2540 switch (*pf_rv) { 2541 case PFIL_DROPPED: 2542 case PFIL_CONSUMED: 2543 /* 2544 * The filter ate it. Everything is recycled. 2545 */ 2546 m = NULL; 2547 unload = 0; 2548 break; 2549 case PFIL_REALLOCED: 2550 /* 2551 * The filter copied it. Everything is recycled. 2552 */ 2553 m = pfil_mem2mbuf(payload); 2554 unload = 0; 2555 break; 2556 case PFIL_PASS: 2557 /* 2558 * Filter said it was OK, so receive like 2559 * normal 2560 */ 2561 fl->ifl_sds.ifsd_m[cidx] = NULL; 2562 break; 2563 default: 2564 MPASS(0); 2565 } 2566 } else { 2567 fl->ifl_sds.ifsd_m[cidx] = NULL; 2568 *pf_rv = PFIL_PASS; 2569 } 2570 2571 if (unload) 2572 bus_dmamap_unload(fl->ifl_buf_tag, map); 2573 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2574 if (__predict_false(fl->ifl_cidx == 0)) 2575 fl->ifl_gen = 0; 2576 bit_clear(fl->ifl_rx_bitmap, cidx); 2577 return (m); 2578 } 2579 2580 static struct mbuf * 2581 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2582 { 2583 struct mbuf *m, *mh, *mt; 2584 caddr_t cl; 2585 int *pf_rv_ptr, flags, i, padlen; 2586 bool consumed; 2587 2588 i = 0; 2589 mh = NULL; 2590 consumed = false; 2591 *pf_rv = PFIL_PASS; 2592 pf_rv_ptr = pf_rv; 2593 do { 2594 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2595 pf_rv_ptr, ri); 2596 2597 MPASS(*sd->ifsd_cl != NULL); 2598 2599 /* 2600 * Exclude zero-length frags & frags from 2601 * packets the filter has consumed or dropped 2602 */ 2603 if (ri->iri_frags[i].irf_len == 0 || consumed || 2604 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2605 if (mh == NULL) { 2606 /* everything saved here */ 2607 consumed = true; 2608 pf_rv_ptr = NULL; 2609 continue; 2610 } 2611 /* XXX we can save the cluster here, but not the mbuf */ 2612 m_init(m, M_NOWAIT, MT_DATA, 0); 2613 m_free(m); 2614 continue; 2615 } 2616 if (mh == NULL) { 2617 flags = M_PKTHDR|M_EXT; 2618 mh = mt = m; 2619 padlen = ri->iri_pad; 2620 } else { 2621 flags = M_EXT; 2622 mt->m_next = m; 2623 mt = m; 2624 /* assuming padding is only on the first fragment */ 2625 padlen = 0; 2626 } 2627 cl = *sd->ifsd_cl; 2628 *sd->ifsd_cl = NULL; 2629 2630 /* Can these two be made one ? */ 2631 m_init(m, M_NOWAIT, MT_DATA, flags); 2632 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2633 /* 2634 * These must follow m_init and m_cljset 2635 */ 2636 m->m_data += padlen; 2637 ri->iri_len -= padlen; 2638 m->m_len = ri->iri_frags[i].irf_len; 2639 } while (++i < ri->iri_nfrags); 2640 2641 return (mh); 2642 } 2643 2644 /* 2645 * Process one software descriptor 2646 */ 2647 static struct mbuf * 2648 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2649 { 2650 struct if_rxsd sd; 2651 struct mbuf *m; 2652 int pf_rv; 2653 2654 /* should I merge this back in now that the two paths are basically duplicated? */ 2655 if (ri->iri_nfrags == 1 && 2656 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2657 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2658 &pf_rv, ri); 2659 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2660 return (m); 2661 if (pf_rv == PFIL_PASS) { 2662 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2663 #ifndef __NO_STRICT_ALIGNMENT 2664 if (!IP_ALIGNED(m)) 2665 m->m_data += 2; 2666 #endif 2667 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2668 m->m_len = ri->iri_frags[0].irf_len; 2669 } 2670 } else { 2671 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2672 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2673 return (m); 2674 } 2675 m->m_pkthdr.len = ri->iri_len; 2676 m->m_pkthdr.rcvif = ri->iri_ifp; 2677 m->m_flags |= ri->iri_flags; 2678 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2679 m->m_pkthdr.flowid = ri->iri_flowid; 2680 M_HASHTYPE_SET(m, ri->iri_rsstype); 2681 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2682 m->m_pkthdr.csum_data = ri->iri_csum_data; 2683 return (m); 2684 } 2685 2686 #if defined(INET6) || defined(INET) 2687 static void 2688 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2689 { 2690 CURVNET_SET(lc->ifp->if_vnet); 2691 #if defined(INET6) 2692 *v6 = VNET(ip6_forwarding); 2693 #endif 2694 #if defined(INET) 2695 *v4 = VNET(ipforwarding); 2696 #endif 2697 CURVNET_RESTORE(); 2698 } 2699 2700 /* 2701 * Returns true if it's possible this packet could be LROed. 2702 * if it returns false, it is guaranteed that tcp_lro_rx() 2703 * would not return zero. 2704 */ 2705 static bool 2706 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2707 { 2708 struct ether_header *eh; 2709 uint16_t eh_type; 2710 2711 eh = mtod(m, struct ether_header *); 2712 eh_type = ntohs(eh->ether_type); 2713 switch (eh_type) { 2714 #if defined(INET6) 2715 case ETHERTYPE_IPV6: 2716 return !v6_forwarding; 2717 #endif 2718 #if defined (INET) 2719 case ETHERTYPE_IP: 2720 return !v4_forwarding; 2721 #endif 2722 } 2723 2724 return false; 2725 } 2726 #else 2727 static void 2728 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2729 { 2730 } 2731 #endif 2732 2733 static bool 2734 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2735 { 2736 if_ctx_t ctx = rxq->ifr_ctx; 2737 if_shared_ctx_t sctx = ctx->ifc_sctx; 2738 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2739 int avail, i; 2740 qidx_t *cidxp; 2741 struct if_rxd_info ri; 2742 int err, budget_left, rx_bytes, rx_pkts; 2743 iflib_fl_t fl; 2744 struct ifnet *ifp; 2745 int lro_enabled; 2746 bool v4_forwarding, v6_forwarding, lro_possible; 2747 2748 /* 2749 * XXX early demux data packets so that if_input processing only handles 2750 * acks in interrupt context 2751 */ 2752 struct mbuf *m, *mh, *mt, *mf; 2753 2754 lro_possible = v4_forwarding = v6_forwarding = false; 2755 ifp = ctx->ifc_ifp; 2756 mh = mt = NULL; 2757 MPASS(budget > 0); 2758 rx_pkts = rx_bytes = 0; 2759 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2760 cidxp = &rxq->ifr_cq_cidx; 2761 else 2762 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2763 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2764 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2765 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2766 DBG_COUNTER_INC(rx_unavail); 2767 return (false); 2768 } 2769 2770 /* pfil needs the vnet to be set */ 2771 CURVNET_SET_QUIET(ifp->if_vnet); 2772 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2773 if (__predict_false(!CTX_ACTIVE(ctx))) { 2774 DBG_COUNTER_INC(rx_ctx_inactive); 2775 break; 2776 } 2777 /* 2778 * Reset client set fields to their default values 2779 */ 2780 rxd_info_zero(&ri); 2781 ri.iri_qsidx = rxq->ifr_id; 2782 ri.iri_cidx = *cidxp; 2783 ri.iri_ifp = ifp; 2784 ri.iri_frags = rxq->ifr_frags; 2785 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2786 2787 if (err) 2788 goto err; 2789 rx_pkts += 1; 2790 rx_bytes += ri.iri_len; 2791 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2792 *cidxp = ri.iri_cidx; 2793 /* Update our consumer index */ 2794 /* XXX NB: shurd - check if this is still safe */ 2795 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2796 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2797 rxq->ifr_cq_gen = 0; 2798 } 2799 /* was this only a completion queue message? */ 2800 if (__predict_false(ri.iri_nfrags == 0)) 2801 continue; 2802 } 2803 MPASS(ri.iri_nfrags != 0); 2804 MPASS(ri.iri_len != 0); 2805 2806 /* will advance the cidx on the corresponding free lists */ 2807 m = iflib_rxd_pkt_get(rxq, &ri); 2808 avail--; 2809 budget_left--; 2810 if (avail == 0 && budget_left) 2811 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2812 2813 if (__predict_false(m == NULL)) 2814 continue; 2815 2816 /* imm_pkt: -- cxgb */ 2817 if (mh == NULL) 2818 mh = mt = m; 2819 else { 2820 mt->m_nextpkt = m; 2821 mt = m; 2822 } 2823 } 2824 CURVNET_RESTORE(); 2825 /* make sure that we can refill faster than drain */ 2826 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2827 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2828 2829 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2830 if (lro_enabled) 2831 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2832 mt = mf = NULL; 2833 while (mh != NULL) { 2834 m = mh; 2835 mh = mh->m_nextpkt; 2836 m->m_nextpkt = NULL; 2837 #ifndef __NO_STRICT_ALIGNMENT 2838 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2839 continue; 2840 #endif 2841 rx_bytes += m->m_pkthdr.len; 2842 rx_pkts++; 2843 #if defined(INET6) || defined(INET) 2844 if (lro_enabled) { 2845 if (!lro_possible) { 2846 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2847 if (lro_possible && mf != NULL) { 2848 ifp->if_input(ifp, mf); 2849 DBG_COUNTER_INC(rx_if_input); 2850 mt = mf = NULL; 2851 } 2852 } 2853 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2854 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2855 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2856 continue; 2857 } 2858 } 2859 #endif 2860 if (lro_possible) { 2861 ifp->if_input(ifp, m); 2862 DBG_COUNTER_INC(rx_if_input); 2863 continue; 2864 } 2865 2866 if (mf == NULL) 2867 mf = m; 2868 if (mt != NULL) 2869 mt->m_nextpkt = m; 2870 mt = m; 2871 } 2872 if (mf != NULL) { 2873 ifp->if_input(ifp, mf); 2874 DBG_COUNTER_INC(rx_if_input); 2875 } 2876 2877 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2878 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2879 2880 /* 2881 * Flush any outstanding LRO work 2882 */ 2883 #if defined(INET6) || defined(INET) 2884 tcp_lro_flush_all(&rxq->ifr_lc); 2885 #endif 2886 if (avail) 2887 return true; 2888 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2889 err: 2890 STATE_LOCK(ctx); 2891 ctx->ifc_flags |= IFC_DO_RESET; 2892 iflib_admin_intr_deferred(ctx); 2893 STATE_UNLOCK(ctx); 2894 return (false); 2895 } 2896 2897 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2898 static inline qidx_t 2899 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2900 { 2901 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2902 qidx_t minthresh = txq->ift_size / 8; 2903 if (in_use > 4*minthresh) 2904 return (notify_count); 2905 if (in_use > 2*minthresh) 2906 return (notify_count >> 1); 2907 if (in_use > minthresh) 2908 return (notify_count >> 3); 2909 return (0); 2910 } 2911 2912 static inline qidx_t 2913 txq_max_rs_deferred(iflib_txq_t txq) 2914 { 2915 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2916 qidx_t minthresh = txq->ift_size / 8; 2917 if (txq->ift_in_use > 4*minthresh) 2918 return (notify_count); 2919 if (txq->ift_in_use > 2*minthresh) 2920 return (notify_count >> 1); 2921 if (txq->ift_in_use > minthresh) 2922 return (notify_count >> 2); 2923 return (2); 2924 } 2925 2926 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2927 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2928 2929 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2930 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2931 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2932 2933 /* forward compatibility for cxgb */ 2934 #define FIRST_QSET(ctx) 0 2935 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2936 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2937 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2938 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2939 2940 /* XXX we should be setting this to something other than zero */ 2941 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2942 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2943 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2944 2945 static inline bool 2946 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2947 { 2948 qidx_t dbval, max; 2949 bool rang; 2950 2951 rang = false; 2952 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2953 if (ring || txq->ift_db_pending >= max) { 2954 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2955 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 2956 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2957 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2958 txq->ift_db_pending = txq->ift_npending = 0; 2959 rang = true; 2960 } 2961 return (rang); 2962 } 2963 2964 #ifdef PKT_DEBUG 2965 static void 2966 print_pkt(if_pkt_info_t pi) 2967 { 2968 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2969 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2970 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2971 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2972 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2973 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2974 } 2975 #endif 2976 2977 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2978 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2979 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2980 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2981 2982 static int 2983 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2984 { 2985 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2986 struct ether_vlan_header *eh; 2987 struct mbuf *m; 2988 2989 m = *mp; 2990 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2991 M_WRITABLE(m) == 0) { 2992 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2993 return (ENOMEM); 2994 } else { 2995 m_freem(*mp); 2996 DBG_COUNTER_INC(tx_frees); 2997 *mp = m; 2998 } 2999 } 3000 3001 /* 3002 * Determine where frame payload starts. 3003 * Jump over vlan headers if already present, 3004 * helpful for QinQ too. 3005 */ 3006 if (__predict_false(m->m_len < sizeof(*eh))) { 3007 txq->ift_pullups++; 3008 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3009 return (ENOMEM); 3010 } 3011 eh = mtod(m, struct ether_vlan_header *); 3012 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3013 pi->ipi_etype = ntohs(eh->evl_proto); 3014 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3015 } else { 3016 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3017 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3018 } 3019 3020 switch (pi->ipi_etype) { 3021 #ifdef INET 3022 case ETHERTYPE_IP: 3023 { 3024 struct mbuf *n; 3025 struct ip *ip = NULL; 3026 struct tcphdr *th = NULL; 3027 int minthlen; 3028 3029 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3030 if (__predict_false(m->m_len < minthlen)) { 3031 /* 3032 * if this code bloat is causing too much of a hit 3033 * move it to a separate function and mark it noinline 3034 */ 3035 if (m->m_len == pi->ipi_ehdrlen) { 3036 n = m->m_next; 3037 MPASS(n); 3038 if (n->m_len >= sizeof(*ip)) { 3039 ip = (struct ip *)n->m_data; 3040 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3041 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3042 } else { 3043 txq->ift_pullups++; 3044 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3045 return (ENOMEM); 3046 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3047 } 3048 } else { 3049 txq->ift_pullups++; 3050 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3051 return (ENOMEM); 3052 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3053 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3054 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3055 } 3056 } else { 3057 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3058 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3059 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3060 } 3061 pi->ipi_ip_hlen = ip->ip_hl << 2; 3062 pi->ipi_ipproto = ip->ip_p; 3063 pi->ipi_flags |= IPI_TX_IPV4; 3064 3065 /* TCP checksum offload may require TCP header length */ 3066 if (IS_TX_OFFLOAD4(pi)) { 3067 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3068 if (__predict_false(th == NULL)) { 3069 txq->ift_pullups++; 3070 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3071 return (ENOMEM); 3072 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3073 } 3074 pi->ipi_tcp_hflags = th->th_flags; 3075 pi->ipi_tcp_hlen = th->th_off << 2; 3076 pi->ipi_tcp_seq = th->th_seq; 3077 } 3078 if (IS_TSO4(pi)) { 3079 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3080 return (ENXIO); 3081 /* 3082 * TSO always requires hardware checksum offload. 3083 */ 3084 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3085 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3086 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3087 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3088 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3089 ip->ip_sum = 0; 3090 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3091 } 3092 } 3093 } 3094 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3095 ip->ip_sum = 0; 3096 3097 break; 3098 } 3099 #endif 3100 #ifdef INET6 3101 case ETHERTYPE_IPV6: 3102 { 3103 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3104 struct tcphdr *th; 3105 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3106 3107 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3108 txq->ift_pullups++; 3109 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3110 return (ENOMEM); 3111 } 3112 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3113 3114 /* XXX-BZ this will go badly in case of ext hdrs. */ 3115 pi->ipi_ipproto = ip6->ip6_nxt; 3116 pi->ipi_flags |= IPI_TX_IPV6; 3117 3118 /* TCP checksum offload may require TCP header length */ 3119 if (IS_TX_OFFLOAD6(pi)) { 3120 if (pi->ipi_ipproto == IPPROTO_TCP) { 3121 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3122 txq->ift_pullups++; 3123 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3124 return (ENOMEM); 3125 } 3126 pi->ipi_tcp_hflags = th->th_flags; 3127 pi->ipi_tcp_hlen = th->th_off << 2; 3128 pi->ipi_tcp_seq = th->th_seq; 3129 } 3130 if (IS_TSO6(pi)) { 3131 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3132 return (ENXIO); 3133 /* 3134 * TSO always requires hardware checksum offload. 3135 */ 3136 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3137 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3138 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3139 } 3140 } 3141 break; 3142 } 3143 #endif 3144 default: 3145 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3146 pi->ipi_ip_hlen = 0; 3147 break; 3148 } 3149 *mp = m; 3150 3151 return (0); 3152 } 3153 3154 /* 3155 * If dodgy hardware rejects the scatter gather chain we've handed it 3156 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3157 * m_defrag'd mbufs 3158 */ 3159 static __noinline struct mbuf * 3160 iflib_remove_mbuf(iflib_txq_t txq) 3161 { 3162 int ntxd, pidx; 3163 struct mbuf *m, **ifsd_m; 3164 3165 ifsd_m = txq->ift_sds.ifsd_m; 3166 ntxd = txq->ift_size; 3167 pidx = txq->ift_pidx & (ntxd - 1); 3168 ifsd_m = txq->ift_sds.ifsd_m; 3169 m = ifsd_m[pidx]; 3170 ifsd_m[pidx] = NULL; 3171 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3172 if (txq->ift_sds.ifsd_tso_map != NULL) 3173 bus_dmamap_unload(txq->ift_tso_buf_tag, 3174 txq->ift_sds.ifsd_tso_map[pidx]); 3175 #if MEMORY_LOGGING 3176 txq->ift_dequeued++; 3177 #endif 3178 return (m); 3179 } 3180 3181 static inline caddr_t 3182 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3183 { 3184 qidx_t size; 3185 int ntxd; 3186 caddr_t start, end, cur, next; 3187 3188 ntxd = txq->ift_size; 3189 size = txq->ift_txd_size[qid]; 3190 start = txq->ift_ifdi[qid].idi_vaddr; 3191 3192 if (__predict_false(size == 0)) 3193 return (start); 3194 cur = start + size*cidx; 3195 end = start + size*ntxd; 3196 next = CACHE_PTR_NEXT(cur); 3197 return (next < end ? next : start); 3198 } 3199 3200 /* 3201 * Pad an mbuf to ensure a minimum ethernet frame size. 3202 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3203 */ 3204 static __noinline int 3205 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3206 { 3207 /* 3208 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3209 * and ARP message is the smallest common payload I can think of 3210 */ 3211 static char pad[18]; /* just zeros */ 3212 int n; 3213 struct mbuf *new_head; 3214 3215 if (!M_WRITABLE(*m_head)) { 3216 new_head = m_dup(*m_head, M_NOWAIT); 3217 if (new_head == NULL) { 3218 m_freem(*m_head); 3219 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3220 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3221 DBG_COUNTER_INC(tx_frees); 3222 return ENOMEM; 3223 } 3224 m_freem(*m_head); 3225 *m_head = new_head; 3226 } 3227 3228 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3229 n > 0; n -= sizeof(pad)) 3230 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3231 break; 3232 3233 if (n > 0) { 3234 m_freem(*m_head); 3235 device_printf(dev, "cannot pad short frame\n"); 3236 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3237 DBG_COUNTER_INC(tx_frees); 3238 return (ENOBUFS); 3239 } 3240 3241 return 0; 3242 } 3243 3244 static int 3245 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3246 { 3247 if_ctx_t ctx; 3248 if_shared_ctx_t sctx; 3249 if_softc_ctx_t scctx; 3250 bus_dma_tag_t buf_tag; 3251 bus_dma_segment_t *segs; 3252 struct mbuf *m_head, **ifsd_m; 3253 void *next_txd; 3254 bus_dmamap_t map; 3255 struct if_pkt_info pi; 3256 int remap = 0; 3257 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3258 3259 ctx = txq->ift_ctx; 3260 sctx = ctx->ifc_sctx; 3261 scctx = &ctx->ifc_softc_ctx; 3262 segs = txq->ift_segs; 3263 ntxd = txq->ift_size; 3264 m_head = *m_headp; 3265 map = NULL; 3266 3267 /* 3268 * If we're doing TSO the next descriptor to clean may be quite far ahead 3269 */ 3270 cidx = txq->ift_cidx; 3271 pidx = txq->ift_pidx; 3272 if (ctx->ifc_flags & IFC_PREFETCH) { 3273 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3274 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3275 next_txd = calc_next_txd(txq, cidx, 0); 3276 prefetch(next_txd); 3277 } 3278 3279 /* prefetch the next cache line of mbuf pointers and flags */ 3280 prefetch(&txq->ift_sds.ifsd_m[next]); 3281 prefetch(&txq->ift_sds.ifsd_map[next]); 3282 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3283 } 3284 map = txq->ift_sds.ifsd_map[pidx]; 3285 ifsd_m = txq->ift_sds.ifsd_m; 3286 3287 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3288 buf_tag = txq->ift_tso_buf_tag; 3289 max_segs = scctx->isc_tx_tso_segments_max; 3290 map = txq->ift_sds.ifsd_tso_map[pidx]; 3291 MPASS(buf_tag != NULL); 3292 MPASS(max_segs > 0); 3293 } else { 3294 buf_tag = txq->ift_buf_tag; 3295 max_segs = scctx->isc_tx_nsegments; 3296 map = txq->ift_sds.ifsd_map[pidx]; 3297 } 3298 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3299 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3300 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3301 if (err) { 3302 DBG_COUNTER_INC(encap_txd_encap_fail); 3303 return err; 3304 } 3305 } 3306 m_head = *m_headp; 3307 3308 pkt_info_zero(&pi); 3309 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3310 pi.ipi_pidx = pidx; 3311 pi.ipi_qsidx = txq->ift_id; 3312 pi.ipi_len = m_head->m_pkthdr.len; 3313 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3314 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3315 3316 /* deliberate bitwise OR to make one condition */ 3317 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3318 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3319 DBG_COUNTER_INC(encap_txd_encap_fail); 3320 return (err); 3321 } 3322 m_head = *m_headp; 3323 } 3324 3325 retry: 3326 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3327 BUS_DMA_NOWAIT); 3328 defrag: 3329 if (__predict_false(err)) { 3330 switch (err) { 3331 case EFBIG: 3332 /* try collapse once and defrag once */ 3333 if (remap == 0) { 3334 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3335 /* try defrag if collapsing fails */ 3336 if (m_head == NULL) 3337 remap++; 3338 } 3339 if (remap == 1) { 3340 txq->ift_mbuf_defrag++; 3341 m_head = m_defrag(*m_headp, M_NOWAIT); 3342 } 3343 /* 3344 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3345 * failed to map an mbuf that was run through m_defrag 3346 */ 3347 MPASS(remap <= 1); 3348 if (__predict_false(m_head == NULL || remap > 1)) 3349 goto defrag_failed; 3350 remap++; 3351 *m_headp = m_head; 3352 goto retry; 3353 break; 3354 case ENOMEM: 3355 txq->ift_no_tx_dma_setup++; 3356 break; 3357 default: 3358 txq->ift_no_tx_dma_setup++; 3359 m_freem(*m_headp); 3360 DBG_COUNTER_INC(tx_frees); 3361 *m_headp = NULL; 3362 break; 3363 } 3364 txq->ift_map_failed++; 3365 DBG_COUNTER_INC(encap_load_mbuf_fail); 3366 DBG_COUNTER_INC(encap_txd_encap_fail); 3367 return (err); 3368 } 3369 ifsd_m[pidx] = m_head; 3370 /* 3371 * XXX assumes a 1 to 1 relationship between segments and 3372 * descriptors - this does not hold true on all drivers, e.g. 3373 * cxgb 3374 */ 3375 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3376 txq->ift_no_desc_avail++; 3377 bus_dmamap_unload(buf_tag, map); 3378 DBG_COUNTER_INC(encap_txq_avail_fail); 3379 DBG_COUNTER_INC(encap_txd_encap_fail); 3380 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3381 GROUPTASK_ENQUEUE(&txq->ift_task); 3382 return (ENOBUFS); 3383 } 3384 /* 3385 * On Intel cards we can greatly reduce the number of TX interrupts 3386 * we see by only setting report status on every Nth descriptor. 3387 * However, this also means that the driver will need to keep track 3388 * of the descriptors that RS was set on to check them for the DD bit. 3389 */ 3390 txq->ift_rs_pending += nsegs + 1; 3391 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3392 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3393 pi.ipi_flags |= IPI_TX_INTR; 3394 txq->ift_rs_pending = 0; 3395 } 3396 3397 pi.ipi_segs = segs; 3398 pi.ipi_nsegs = nsegs; 3399 3400 MPASS(pidx >= 0 && pidx < txq->ift_size); 3401 #ifdef PKT_DEBUG 3402 print_pkt(&pi); 3403 #endif 3404 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3405 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3406 DBG_COUNTER_INC(tx_encap); 3407 MPASS(pi.ipi_new_pidx < txq->ift_size); 3408 3409 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3410 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3411 ndesc += txq->ift_size; 3412 txq->ift_gen = 1; 3413 } 3414 /* 3415 * drivers can need as many as 3416 * two sentinels 3417 */ 3418 MPASS(ndesc <= pi.ipi_nsegs + 2); 3419 MPASS(pi.ipi_new_pidx != pidx); 3420 MPASS(ndesc > 0); 3421 txq->ift_in_use += ndesc; 3422 3423 /* 3424 * We update the last software descriptor again here because there may 3425 * be a sentinel and/or there may be more mbufs than segments 3426 */ 3427 txq->ift_pidx = pi.ipi_new_pidx; 3428 txq->ift_npending += pi.ipi_ndescs; 3429 } else { 3430 *m_headp = m_head = iflib_remove_mbuf(txq); 3431 if (err == EFBIG) { 3432 txq->ift_txd_encap_efbig++; 3433 if (remap < 2) { 3434 remap = 1; 3435 goto defrag; 3436 } 3437 } 3438 goto defrag_failed; 3439 } 3440 /* 3441 * err can't possibly be non-zero here, so we don't neet to test it 3442 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3443 */ 3444 return (err); 3445 3446 defrag_failed: 3447 txq->ift_mbuf_defrag_failed++; 3448 txq->ift_map_failed++; 3449 m_freem(*m_headp); 3450 DBG_COUNTER_INC(tx_frees); 3451 *m_headp = NULL; 3452 DBG_COUNTER_INC(encap_txd_encap_fail); 3453 return (ENOMEM); 3454 } 3455 3456 static void 3457 iflib_tx_desc_free(iflib_txq_t txq, int n) 3458 { 3459 uint32_t qsize, cidx, mask, gen; 3460 struct mbuf *m, **ifsd_m; 3461 bool do_prefetch; 3462 3463 cidx = txq->ift_cidx; 3464 gen = txq->ift_gen; 3465 qsize = txq->ift_size; 3466 mask = qsize-1; 3467 ifsd_m = txq->ift_sds.ifsd_m; 3468 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3469 3470 while (n-- > 0) { 3471 if (do_prefetch) { 3472 prefetch(ifsd_m[(cidx + 3) & mask]); 3473 prefetch(ifsd_m[(cidx + 4) & mask]); 3474 } 3475 if ((m = ifsd_m[cidx]) != NULL) { 3476 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3477 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3478 bus_dmamap_sync(txq->ift_tso_buf_tag, 3479 txq->ift_sds.ifsd_tso_map[cidx], 3480 BUS_DMASYNC_POSTWRITE); 3481 bus_dmamap_unload(txq->ift_tso_buf_tag, 3482 txq->ift_sds.ifsd_tso_map[cidx]); 3483 } else { 3484 bus_dmamap_sync(txq->ift_buf_tag, 3485 txq->ift_sds.ifsd_map[cidx], 3486 BUS_DMASYNC_POSTWRITE); 3487 bus_dmamap_unload(txq->ift_buf_tag, 3488 txq->ift_sds.ifsd_map[cidx]); 3489 } 3490 /* XXX we don't support any drivers that batch packets yet */ 3491 MPASS(m->m_nextpkt == NULL); 3492 m_freem(m); 3493 ifsd_m[cidx] = NULL; 3494 #if MEMORY_LOGGING 3495 txq->ift_dequeued++; 3496 #endif 3497 DBG_COUNTER_INC(tx_frees); 3498 } 3499 if (__predict_false(++cidx == qsize)) { 3500 cidx = 0; 3501 gen = 0; 3502 } 3503 } 3504 txq->ift_cidx = cidx; 3505 txq->ift_gen = gen; 3506 } 3507 3508 static __inline int 3509 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3510 { 3511 int reclaim; 3512 if_ctx_t ctx = txq->ift_ctx; 3513 3514 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3515 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3516 3517 /* 3518 * Need a rate-limiting check so that this isn't called every time 3519 */ 3520 iflib_tx_credits_update(ctx, txq); 3521 reclaim = DESC_RECLAIMABLE(txq); 3522 3523 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3524 #ifdef INVARIANTS 3525 if (iflib_verbose_debug) { 3526 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3527 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3528 reclaim, thresh); 3529 3530 } 3531 #endif 3532 return (0); 3533 } 3534 iflib_tx_desc_free(txq, reclaim); 3535 txq->ift_cleaned += reclaim; 3536 txq->ift_in_use -= reclaim; 3537 3538 return (reclaim); 3539 } 3540 3541 static struct mbuf ** 3542 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3543 { 3544 int next, size; 3545 struct mbuf **items; 3546 3547 size = r->size; 3548 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3549 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3550 3551 prefetch(items[(cidx + offset) & (size-1)]); 3552 if (remaining > 1) { 3553 prefetch2cachelines(&items[next]); 3554 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3555 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3556 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3557 } 3558 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3559 } 3560 3561 static void 3562 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3563 { 3564 3565 ifmp_ring_check_drainage(txq->ift_br, budget); 3566 } 3567 3568 static uint32_t 3569 iflib_txq_can_drain(struct ifmp_ring *r) 3570 { 3571 iflib_txq_t txq = r->cookie; 3572 if_ctx_t ctx = txq->ift_ctx; 3573 3574 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3575 return (1); 3576 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3577 BUS_DMASYNC_POSTREAD); 3578 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3579 false)); 3580 } 3581 3582 static uint32_t 3583 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3584 { 3585 iflib_txq_t txq = r->cookie; 3586 if_ctx_t ctx = txq->ift_ctx; 3587 struct ifnet *ifp = ctx->ifc_ifp; 3588 struct mbuf **mp, *m; 3589 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3590 int reclaimed, err, in_use_prev, desc_used; 3591 bool do_prefetch, ring, rang; 3592 3593 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3594 !LINK_ACTIVE(ctx))) { 3595 DBG_COUNTER_INC(txq_drain_notready); 3596 return (0); 3597 } 3598 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3599 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3600 avail = IDXDIFF(pidx, cidx, r->size); 3601 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3602 DBG_COUNTER_INC(txq_drain_flushing); 3603 for (i = 0; i < avail; i++) { 3604 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3605 m_free(r->items[(cidx + i) & (r->size-1)]); 3606 r->items[(cidx + i) & (r->size-1)] = NULL; 3607 } 3608 return (avail); 3609 } 3610 3611 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3612 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3613 CALLOUT_LOCK(txq); 3614 callout_stop(&txq->ift_timer); 3615 CALLOUT_UNLOCK(txq); 3616 DBG_COUNTER_INC(txq_drain_oactive); 3617 return (0); 3618 } 3619 if (reclaimed) 3620 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3621 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3622 count = MIN(avail, TX_BATCH_SIZE); 3623 #ifdef INVARIANTS 3624 if (iflib_verbose_debug) 3625 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3626 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3627 #endif 3628 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3629 avail = TXQ_AVAIL(txq); 3630 err = 0; 3631 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3632 int rem = do_prefetch ? count - i : 0; 3633 3634 mp = _ring_peek_one(r, cidx, i, rem); 3635 MPASS(mp != NULL && *mp != NULL); 3636 if (__predict_false(*mp == (struct mbuf *)txq)) { 3637 consumed++; 3638 reclaimed++; 3639 continue; 3640 } 3641 in_use_prev = txq->ift_in_use; 3642 err = iflib_encap(txq, mp); 3643 if (__predict_false(err)) { 3644 /* no room - bail out */ 3645 if (err == ENOBUFS) 3646 break; 3647 consumed++; 3648 /* we can't send this packet - skip it */ 3649 continue; 3650 } 3651 consumed++; 3652 pkt_sent++; 3653 m = *mp; 3654 DBG_COUNTER_INC(tx_sent); 3655 bytes_sent += m->m_pkthdr.len; 3656 mcast_sent += !!(m->m_flags & M_MCAST); 3657 avail = TXQ_AVAIL(txq); 3658 3659 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3660 desc_used += (txq->ift_in_use - in_use_prev); 3661 ETHER_BPF_MTAP(ifp, m); 3662 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3663 break; 3664 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3665 } 3666 3667 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3668 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3669 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3670 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3671 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3672 if (mcast_sent) 3673 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3674 #ifdef INVARIANTS 3675 if (iflib_verbose_debug) 3676 printf("consumed=%d\n", consumed); 3677 #endif 3678 return (consumed); 3679 } 3680 3681 static uint32_t 3682 iflib_txq_drain_always(struct ifmp_ring *r) 3683 { 3684 return (1); 3685 } 3686 3687 static uint32_t 3688 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3689 { 3690 int i, avail; 3691 struct mbuf **mp; 3692 iflib_txq_t txq; 3693 3694 txq = r->cookie; 3695 3696 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3697 CALLOUT_LOCK(txq); 3698 callout_stop(&txq->ift_timer); 3699 CALLOUT_UNLOCK(txq); 3700 3701 avail = IDXDIFF(pidx, cidx, r->size); 3702 for (i = 0; i < avail; i++) { 3703 mp = _ring_peek_one(r, cidx, i, avail - i); 3704 if (__predict_false(*mp == (struct mbuf *)txq)) 3705 continue; 3706 m_freem(*mp); 3707 DBG_COUNTER_INC(tx_frees); 3708 } 3709 MPASS(ifmp_ring_is_stalled(r) == 0); 3710 return (avail); 3711 } 3712 3713 static void 3714 iflib_ifmp_purge(iflib_txq_t txq) 3715 { 3716 struct ifmp_ring *r; 3717 3718 r = txq->ift_br; 3719 r->drain = iflib_txq_drain_free; 3720 r->can_drain = iflib_txq_drain_always; 3721 3722 ifmp_ring_check_drainage(r, r->size); 3723 3724 r->drain = iflib_txq_drain; 3725 r->can_drain = iflib_txq_can_drain; 3726 } 3727 3728 static void 3729 _task_fn_tx(void *context) 3730 { 3731 iflib_txq_t txq = context; 3732 if_ctx_t ctx = txq->ift_ctx; 3733 #if defined(ALTQ) || defined(DEV_NETMAP) 3734 if_t ifp = ctx->ifc_ifp; 3735 #endif 3736 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3737 3738 #ifdef IFLIB_DIAGNOSTICS 3739 txq->ift_cpu_exec_count[curcpu]++; 3740 #endif 3741 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3742 return; 3743 #ifdef DEV_NETMAP 3744 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3745 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3746 BUS_DMASYNC_POSTREAD); 3747 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3748 netmap_tx_irq(ifp, txq->ift_id); 3749 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3750 return; 3751 } 3752 #endif 3753 #ifdef ALTQ 3754 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3755 iflib_altq_if_start(ifp); 3756 #endif 3757 if (txq->ift_db_pending) 3758 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3759 else if (!abdicate) 3760 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3761 /* 3762 * When abdicating, we always need to check drainage, not just when we don't enqueue 3763 */ 3764 if (abdicate) 3765 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3766 if (ctx->ifc_flags & IFC_LEGACY) 3767 IFDI_INTR_ENABLE(ctx); 3768 else { 3769 #ifdef INVARIANTS 3770 int rc = 3771 #endif 3772 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3773 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3774 } 3775 } 3776 3777 static void 3778 _task_fn_rx(void *context) 3779 { 3780 iflib_rxq_t rxq = context; 3781 if_ctx_t ctx = rxq->ifr_ctx; 3782 bool more; 3783 uint16_t budget; 3784 3785 #ifdef IFLIB_DIAGNOSTICS 3786 rxq->ifr_cpu_exec_count[curcpu]++; 3787 #endif 3788 DBG_COUNTER_INC(task_fn_rxs); 3789 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3790 return; 3791 more = true; 3792 #ifdef DEV_NETMAP 3793 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3794 u_int work = 0; 3795 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3796 more = false; 3797 } 3798 } 3799 #endif 3800 budget = ctx->ifc_sysctl_rx_budget; 3801 if (budget == 0) 3802 budget = 16; /* XXX */ 3803 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3804 if (ctx->ifc_flags & IFC_LEGACY) 3805 IFDI_INTR_ENABLE(ctx); 3806 else { 3807 #ifdef INVARIANTS 3808 int rc = 3809 #endif 3810 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3811 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3812 DBG_COUNTER_INC(rx_intr_enables); 3813 } 3814 } 3815 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3816 return; 3817 if (more) 3818 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3819 } 3820 3821 static void 3822 _task_fn_admin(void *context) 3823 { 3824 if_ctx_t ctx = context; 3825 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3826 iflib_txq_t txq; 3827 int i; 3828 bool oactive, running, do_reset, do_watchdog, in_detach; 3829 uint32_t reset_on = hz / 2; 3830 3831 STATE_LOCK(ctx); 3832 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3833 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3834 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3835 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3836 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3837 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3838 STATE_UNLOCK(ctx); 3839 3840 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3841 return; 3842 if (in_detach) 3843 return; 3844 3845 CTX_LOCK(ctx); 3846 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3847 CALLOUT_LOCK(txq); 3848 callout_stop(&txq->ift_timer); 3849 CALLOUT_UNLOCK(txq); 3850 } 3851 if (do_watchdog) { 3852 ctx->ifc_watchdog_events++; 3853 IFDI_WATCHDOG_RESET(ctx); 3854 } 3855 IFDI_UPDATE_ADMIN_STATUS(ctx); 3856 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3857 #ifdef DEV_NETMAP 3858 reset_on = hz / 2; 3859 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3860 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 3861 #endif 3862 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3863 } 3864 IFDI_LINK_INTR_ENABLE(ctx); 3865 if (do_reset) 3866 iflib_if_init_locked(ctx); 3867 CTX_UNLOCK(ctx); 3868 3869 if (LINK_ACTIVE(ctx) == 0) 3870 return; 3871 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3872 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3873 } 3874 3875 3876 static void 3877 _task_fn_iov(void *context) 3878 { 3879 if_ctx_t ctx = context; 3880 3881 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3882 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3883 return; 3884 3885 CTX_LOCK(ctx); 3886 IFDI_VFLR_HANDLE(ctx); 3887 CTX_UNLOCK(ctx); 3888 } 3889 3890 static int 3891 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3892 { 3893 int err; 3894 if_int_delay_info_t info; 3895 if_ctx_t ctx; 3896 3897 info = (if_int_delay_info_t)arg1; 3898 ctx = info->iidi_ctx; 3899 info->iidi_req = req; 3900 info->iidi_oidp = oidp; 3901 CTX_LOCK(ctx); 3902 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3903 CTX_UNLOCK(ctx); 3904 return (err); 3905 } 3906 3907 /********************************************************************* 3908 * 3909 * IFNET FUNCTIONS 3910 * 3911 **********************************************************************/ 3912 3913 static void 3914 iflib_if_init_locked(if_ctx_t ctx) 3915 { 3916 iflib_stop(ctx); 3917 iflib_init_locked(ctx); 3918 } 3919 3920 3921 static void 3922 iflib_if_init(void *arg) 3923 { 3924 if_ctx_t ctx = arg; 3925 3926 CTX_LOCK(ctx); 3927 iflib_if_init_locked(ctx); 3928 CTX_UNLOCK(ctx); 3929 } 3930 3931 static int 3932 iflib_if_transmit(if_t ifp, struct mbuf *m) 3933 { 3934 if_ctx_t ctx = if_getsoftc(ifp); 3935 3936 iflib_txq_t txq; 3937 int err, qidx; 3938 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3939 3940 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3941 DBG_COUNTER_INC(tx_frees); 3942 m_freem(m); 3943 return (ENETDOWN); 3944 } 3945 3946 MPASS(m->m_nextpkt == NULL); 3947 /* ALTQ-enabled interfaces always use queue 0. */ 3948 qidx = 0; 3949 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3950 qidx = QIDX(ctx, m); 3951 /* 3952 * XXX calculate buf_ring based on flowid (divvy up bits?) 3953 */ 3954 txq = &ctx->ifc_txqs[qidx]; 3955 3956 #ifdef DRIVER_BACKPRESSURE 3957 if (txq->ift_closed) { 3958 while (m != NULL) { 3959 next = m->m_nextpkt; 3960 m->m_nextpkt = NULL; 3961 m_freem(m); 3962 DBG_COUNTER_INC(tx_frees); 3963 m = next; 3964 } 3965 return (ENOBUFS); 3966 } 3967 #endif 3968 #ifdef notyet 3969 qidx = count = 0; 3970 mp = marr; 3971 next = m; 3972 do { 3973 count++; 3974 next = next->m_nextpkt; 3975 } while (next != NULL); 3976 3977 if (count > nitems(marr)) 3978 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3979 /* XXX check nextpkt */ 3980 m_freem(m); 3981 /* XXX simplify for now */ 3982 DBG_COUNTER_INC(tx_frees); 3983 return (ENOBUFS); 3984 } 3985 for (next = m, i = 0; next != NULL; i++) { 3986 mp[i] = next; 3987 next = next->m_nextpkt; 3988 mp[i]->m_nextpkt = NULL; 3989 } 3990 #endif 3991 DBG_COUNTER_INC(tx_seen); 3992 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 3993 3994 if (abdicate) 3995 GROUPTASK_ENQUEUE(&txq->ift_task); 3996 if (err) { 3997 if (!abdicate) 3998 GROUPTASK_ENQUEUE(&txq->ift_task); 3999 /* support forthcoming later */ 4000 #ifdef DRIVER_BACKPRESSURE 4001 txq->ift_closed = TRUE; 4002 #endif 4003 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4004 m_freem(m); 4005 DBG_COUNTER_INC(tx_frees); 4006 } 4007 4008 return (err); 4009 } 4010 4011 #ifdef ALTQ 4012 /* 4013 * The overall approach to integrating iflib with ALTQ is to continue to use 4014 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4015 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4016 * is redundant/unnecessary, but doing so minimizes the amount of 4017 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4018 * redundantly queueing to an intermediate mp_ring is swamped by the 4019 * performance limitations inherent in using ALTQ. 4020 * 4021 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4022 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4023 * given interface. If ALTQ is enabled for an interface, then all 4024 * transmitted packets for that interface will be submitted to the ALTQ 4025 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4026 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4027 * update stats that the iflib machinery handles, and which is sensitve to 4028 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4029 * will be installed as the start routine for use by ALTQ facilities that 4030 * need to trigger queue drains on a scheduled basis. 4031 * 4032 */ 4033 static void 4034 iflib_altq_if_start(if_t ifp) 4035 { 4036 struct ifaltq *ifq = &ifp->if_snd; 4037 struct mbuf *m; 4038 4039 IFQ_LOCK(ifq); 4040 IFQ_DEQUEUE_NOLOCK(ifq, m); 4041 while (m != NULL) { 4042 iflib_if_transmit(ifp, m); 4043 IFQ_DEQUEUE_NOLOCK(ifq, m); 4044 } 4045 IFQ_UNLOCK(ifq); 4046 } 4047 4048 static int 4049 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4050 { 4051 int err; 4052 4053 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4054 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4055 if (err == 0) 4056 iflib_altq_if_start(ifp); 4057 } else 4058 err = iflib_if_transmit(ifp, m); 4059 4060 return (err); 4061 } 4062 #endif /* ALTQ */ 4063 4064 static void 4065 iflib_if_qflush(if_t ifp) 4066 { 4067 if_ctx_t ctx = if_getsoftc(ifp); 4068 iflib_txq_t txq = ctx->ifc_txqs; 4069 int i; 4070 4071 STATE_LOCK(ctx); 4072 ctx->ifc_flags |= IFC_QFLUSH; 4073 STATE_UNLOCK(ctx); 4074 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4075 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4076 iflib_txq_check_drain(txq, 0); 4077 STATE_LOCK(ctx); 4078 ctx->ifc_flags &= ~IFC_QFLUSH; 4079 STATE_UNLOCK(ctx); 4080 4081 /* 4082 * When ALTQ is enabled, this will also take care of purging the 4083 * ALTQ queue(s). 4084 */ 4085 if_qflush(ifp); 4086 } 4087 4088 4089 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4090 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4091 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4092 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM) 4093 4094 static int 4095 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4096 { 4097 if_ctx_t ctx = if_getsoftc(ifp); 4098 struct ifreq *ifr = (struct ifreq *)data; 4099 #if defined(INET) || defined(INET6) 4100 struct ifaddr *ifa = (struct ifaddr *)data; 4101 #endif 4102 bool avoid_reset = FALSE; 4103 int err = 0, reinit = 0, bits; 4104 4105 switch (command) { 4106 case SIOCSIFADDR: 4107 #ifdef INET 4108 if (ifa->ifa_addr->sa_family == AF_INET) 4109 avoid_reset = TRUE; 4110 #endif 4111 #ifdef INET6 4112 if (ifa->ifa_addr->sa_family == AF_INET6) 4113 avoid_reset = TRUE; 4114 #endif 4115 /* 4116 ** Calling init results in link renegotiation, 4117 ** so we avoid doing it when possible. 4118 */ 4119 if (avoid_reset) { 4120 if_setflagbits(ifp, IFF_UP,0); 4121 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4122 reinit = 1; 4123 #ifdef INET 4124 if (!(if_getflags(ifp) & IFF_NOARP)) 4125 arp_ifinit(ifp, ifa); 4126 #endif 4127 } else 4128 err = ether_ioctl(ifp, command, data); 4129 break; 4130 case SIOCSIFMTU: 4131 CTX_LOCK(ctx); 4132 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4133 CTX_UNLOCK(ctx); 4134 break; 4135 } 4136 bits = if_getdrvflags(ifp); 4137 /* stop the driver and free any clusters before proceeding */ 4138 iflib_stop(ctx); 4139 4140 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4141 STATE_LOCK(ctx); 4142 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4143 ctx->ifc_flags |= IFC_MULTISEG; 4144 else 4145 ctx->ifc_flags &= ~IFC_MULTISEG; 4146 STATE_UNLOCK(ctx); 4147 err = if_setmtu(ifp, ifr->ifr_mtu); 4148 } 4149 iflib_init_locked(ctx); 4150 STATE_LOCK(ctx); 4151 if_setdrvflags(ifp, bits); 4152 STATE_UNLOCK(ctx); 4153 CTX_UNLOCK(ctx); 4154 break; 4155 case SIOCSIFFLAGS: 4156 CTX_LOCK(ctx); 4157 if (if_getflags(ifp) & IFF_UP) { 4158 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4159 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4160 (IFF_PROMISC | IFF_ALLMULTI)) { 4161 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4162 } 4163 } else 4164 reinit = 1; 4165 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4166 iflib_stop(ctx); 4167 } 4168 ctx->ifc_if_flags = if_getflags(ifp); 4169 CTX_UNLOCK(ctx); 4170 break; 4171 case SIOCADDMULTI: 4172 case SIOCDELMULTI: 4173 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4174 CTX_LOCK(ctx); 4175 IFDI_INTR_DISABLE(ctx); 4176 IFDI_MULTI_SET(ctx); 4177 IFDI_INTR_ENABLE(ctx); 4178 CTX_UNLOCK(ctx); 4179 } 4180 break; 4181 case SIOCSIFMEDIA: 4182 CTX_LOCK(ctx); 4183 IFDI_MEDIA_SET(ctx); 4184 CTX_UNLOCK(ctx); 4185 /* falls thru */ 4186 case SIOCGIFMEDIA: 4187 case SIOCGIFXMEDIA: 4188 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4189 break; 4190 case SIOCGI2C: 4191 { 4192 struct ifi2creq i2c; 4193 4194 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4195 if (err != 0) 4196 break; 4197 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4198 err = EINVAL; 4199 break; 4200 } 4201 if (i2c.len > sizeof(i2c.data)) { 4202 err = EINVAL; 4203 break; 4204 } 4205 4206 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4207 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4208 sizeof(i2c)); 4209 break; 4210 } 4211 case SIOCSIFCAP: 4212 { 4213 int mask, setmask, oldmask; 4214 4215 oldmask = if_getcapenable(ifp); 4216 mask = ifr->ifr_reqcap ^ oldmask; 4217 mask &= ctx->ifc_softc_ctx.isc_capabilities; 4218 setmask = 0; 4219 #ifdef TCP_OFFLOAD 4220 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4221 #endif 4222 setmask |= (mask & IFCAP_FLAGS); 4223 setmask |= (mask & IFCAP_WOL); 4224 4225 /* 4226 * If any RX csum has changed, change all the ones that 4227 * are supported by the driver. 4228 */ 4229 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4230 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4231 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4232 } 4233 4234 /* 4235 * want to ensure that traffic has stopped before we change any of the flags 4236 */ 4237 if (setmask) { 4238 CTX_LOCK(ctx); 4239 bits = if_getdrvflags(ifp); 4240 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4241 iflib_stop(ctx); 4242 STATE_LOCK(ctx); 4243 if_togglecapenable(ifp, setmask); 4244 STATE_UNLOCK(ctx); 4245 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4246 iflib_init_locked(ctx); 4247 STATE_LOCK(ctx); 4248 if_setdrvflags(ifp, bits); 4249 STATE_UNLOCK(ctx); 4250 CTX_UNLOCK(ctx); 4251 } 4252 if_vlancap(ifp); 4253 break; 4254 } 4255 case SIOCGPRIVATE_0: 4256 case SIOCSDRVSPEC: 4257 case SIOCGDRVSPEC: 4258 CTX_LOCK(ctx); 4259 err = IFDI_PRIV_IOCTL(ctx, command, data); 4260 CTX_UNLOCK(ctx); 4261 break; 4262 default: 4263 err = ether_ioctl(ifp, command, data); 4264 break; 4265 } 4266 if (reinit) 4267 iflib_if_init(ctx); 4268 return (err); 4269 } 4270 4271 static uint64_t 4272 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4273 { 4274 if_ctx_t ctx = if_getsoftc(ifp); 4275 4276 return (IFDI_GET_COUNTER(ctx, cnt)); 4277 } 4278 4279 /********************************************************************* 4280 * 4281 * OTHER FUNCTIONS EXPORTED TO THE STACK 4282 * 4283 **********************************************************************/ 4284 4285 static void 4286 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4287 { 4288 if_ctx_t ctx = if_getsoftc(ifp); 4289 4290 if ((void *)ctx != arg) 4291 return; 4292 4293 if ((vtag == 0) || (vtag > 4095)) 4294 return; 4295 4296 CTX_LOCK(ctx); 4297 IFDI_VLAN_REGISTER(ctx, vtag); 4298 /* Re-init to load the changes */ 4299 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4300 iflib_if_init_locked(ctx); 4301 CTX_UNLOCK(ctx); 4302 } 4303 4304 static void 4305 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4306 { 4307 if_ctx_t ctx = if_getsoftc(ifp); 4308 4309 if ((void *)ctx != arg) 4310 return; 4311 4312 if ((vtag == 0) || (vtag > 4095)) 4313 return; 4314 4315 CTX_LOCK(ctx); 4316 IFDI_VLAN_UNREGISTER(ctx, vtag); 4317 /* Re-init to load the changes */ 4318 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4319 iflib_if_init_locked(ctx); 4320 CTX_UNLOCK(ctx); 4321 } 4322 4323 static void 4324 iflib_led_func(void *arg, int onoff) 4325 { 4326 if_ctx_t ctx = arg; 4327 4328 CTX_LOCK(ctx); 4329 IFDI_LED_FUNC(ctx, onoff); 4330 CTX_UNLOCK(ctx); 4331 } 4332 4333 /********************************************************************* 4334 * 4335 * BUS FUNCTION DEFINITIONS 4336 * 4337 **********************************************************************/ 4338 4339 int 4340 iflib_device_probe(device_t dev) 4341 { 4342 pci_vendor_info_t *ent; 4343 4344 uint16_t pci_vendor_id, pci_device_id; 4345 uint16_t pci_subvendor_id, pci_subdevice_id; 4346 uint16_t pci_rev_id; 4347 if_shared_ctx_t sctx; 4348 4349 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4350 return (ENOTSUP); 4351 4352 pci_vendor_id = pci_get_vendor(dev); 4353 pci_device_id = pci_get_device(dev); 4354 pci_subvendor_id = pci_get_subvendor(dev); 4355 pci_subdevice_id = pci_get_subdevice(dev); 4356 pci_rev_id = pci_get_revid(dev); 4357 if (sctx->isc_parse_devinfo != NULL) 4358 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4359 4360 ent = sctx->isc_vendor_info; 4361 while (ent->pvi_vendor_id != 0) { 4362 if (pci_vendor_id != ent->pvi_vendor_id) { 4363 ent++; 4364 continue; 4365 } 4366 if ((pci_device_id == ent->pvi_device_id) && 4367 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4368 (ent->pvi_subvendor_id == 0)) && 4369 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4370 (ent->pvi_subdevice_id == 0)) && 4371 ((pci_rev_id == ent->pvi_rev_id) || 4372 (ent->pvi_rev_id == 0))) { 4373 4374 device_set_desc_copy(dev, ent->pvi_name); 4375 /* this needs to be changed to zero if the bus probing code 4376 * ever stops re-probing on best match because the sctx 4377 * may have its values over written by register calls 4378 * in subsequent probes 4379 */ 4380 return (BUS_PROBE_DEFAULT); 4381 } 4382 ent++; 4383 } 4384 return (ENXIO); 4385 } 4386 4387 static void 4388 iflib_reset_qvalues(if_ctx_t ctx) 4389 { 4390 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4391 if_shared_ctx_t sctx = ctx->ifc_sctx; 4392 device_t dev = ctx->ifc_dev; 4393 int i; 4394 4395 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES; 4396 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH; 4397 /* 4398 * XXX sanity check that ntxd & nrxd are a power of 2 4399 */ 4400 if (ctx->ifc_sysctl_ntxqs != 0) 4401 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4402 if (ctx->ifc_sysctl_nrxqs != 0) 4403 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4404 4405 for (i = 0; i < sctx->isc_ntxqs; i++) { 4406 if (ctx->ifc_sysctl_ntxds[i] != 0) 4407 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4408 else 4409 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4410 } 4411 4412 for (i = 0; i < sctx->isc_nrxqs; i++) { 4413 if (ctx->ifc_sysctl_nrxds[i] != 0) 4414 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4415 else 4416 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4417 } 4418 4419 for (i = 0; i < sctx->isc_nrxqs; i++) { 4420 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4421 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4422 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4423 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4424 } 4425 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4426 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4427 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4428 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4429 } 4430 } 4431 4432 for (i = 0; i < sctx->isc_ntxqs; i++) { 4433 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4434 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4435 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4436 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4437 } 4438 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4439 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4440 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4441 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4442 } 4443 } 4444 } 4445 4446 static void 4447 iflib_add_pfil(if_ctx_t ctx) 4448 { 4449 struct pfil_head *pfil; 4450 struct pfil_head_args pa; 4451 iflib_rxq_t rxq; 4452 int i; 4453 4454 pa.pa_version = PFIL_VERSION; 4455 pa.pa_flags = PFIL_IN; 4456 pa.pa_type = PFIL_TYPE_ETHERNET; 4457 pa.pa_headname = ctx->ifc_ifp->if_xname; 4458 pfil = pfil_head_register(&pa); 4459 4460 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4461 rxq->pfil = pfil; 4462 } 4463 } 4464 4465 static void 4466 iflib_rem_pfil(if_ctx_t ctx) 4467 { 4468 struct pfil_head *pfil; 4469 iflib_rxq_t rxq; 4470 int i; 4471 4472 rxq = ctx->ifc_rxqs; 4473 pfil = rxq->pfil; 4474 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4475 rxq->pfil = NULL; 4476 } 4477 pfil_head_unregister(pfil); 4478 } 4479 4480 static uint16_t 4481 get_ctx_core_offset(if_ctx_t ctx) 4482 { 4483 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4484 struct cpu_offset *op; 4485 uint16_t qc; 4486 uint16_t ret = ctx->ifc_sysctl_core_offset; 4487 4488 if (ret != CORE_OFFSET_UNSPECIFIED) 4489 return (ret); 4490 4491 if (ctx->ifc_sysctl_separate_txrx) 4492 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets; 4493 else 4494 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets); 4495 4496 mtx_lock(&cpu_offset_mtx); 4497 SLIST_FOREACH(op, &cpu_offsets, entries) { 4498 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4499 ret = op->offset; 4500 op->offset += qc; 4501 MPASS(op->refcount < UINT_MAX); 4502 op->refcount++; 4503 break; 4504 } 4505 } 4506 if (ret == CORE_OFFSET_UNSPECIFIED) { 4507 ret = 0; 4508 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4509 M_NOWAIT | M_ZERO); 4510 if (op == NULL) { 4511 device_printf(ctx->ifc_dev, 4512 "allocation for cpu offset failed.\n"); 4513 } else { 4514 op->offset = qc; 4515 op->refcount = 1; 4516 CPU_COPY(&ctx->ifc_cpus, &op->set); 4517 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4518 } 4519 } 4520 mtx_unlock(&cpu_offset_mtx); 4521 4522 return (ret); 4523 } 4524 4525 static void 4526 unref_ctx_core_offset(if_ctx_t ctx) 4527 { 4528 struct cpu_offset *op, *top; 4529 4530 mtx_lock(&cpu_offset_mtx); 4531 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4532 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4533 MPASS(op->refcount > 0); 4534 op->refcount--; 4535 if (op->refcount == 0) { 4536 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4537 free(op, M_IFLIB); 4538 } 4539 break; 4540 } 4541 } 4542 mtx_unlock(&cpu_offset_mtx); 4543 } 4544 4545 int 4546 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4547 { 4548 int err, rid, msix; 4549 if_ctx_t ctx; 4550 if_t ifp; 4551 if_softc_ctx_t scctx; 4552 int i; 4553 uint16_t main_txq; 4554 uint16_t main_rxq; 4555 4556 4557 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4558 4559 if (sc == NULL) { 4560 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4561 device_set_softc(dev, ctx); 4562 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4563 } 4564 4565 ctx->ifc_sctx = sctx; 4566 ctx->ifc_dev = dev; 4567 ctx->ifc_softc = sc; 4568 4569 if ((err = iflib_register(ctx)) != 0) { 4570 device_printf(dev, "iflib_register failed %d\n", err); 4571 goto fail_ctx_free; 4572 } 4573 iflib_add_device_sysctl_pre(ctx); 4574 4575 scctx = &ctx->ifc_softc_ctx; 4576 ifp = ctx->ifc_ifp; 4577 4578 iflib_reset_qvalues(ctx); 4579 CTX_LOCK(ctx); 4580 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4581 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4582 goto fail_unlock; 4583 } 4584 _iflib_pre_assert(scctx); 4585 ctx->ifc_txrx = *scctx->isc_txrx; 4586 4587 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 4588 ctx->ifc_mediap = scctx->isc_media; 4589 4590 #ifdef INVARIANTS 4591 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4592 MPASS(scctx->isc_tx_csum_flags); 4593 #endif 4594 4595 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS); 4596 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4597 4598 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4599 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4600 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4601 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4602 4603 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4604 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4605 4606 /* XXX change for per-queue sizes */ 4607 device_printf(dev, "Using %d tx descriptors and %d rx descriptors\n", 4608 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4609 for (i = 0; i < sctx->isc_nrxqs; i++) { 4610 if (!powerof2(scctx->isc_nrxd[i])) { 4611 /* round down instead? */ 4612 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4613 err = EINVAL; 4614 goto fail_iflib_detach; 4615 } 4616 } 4617 for (i = 0; i < sctx->isc_ntxqs; i++) { 4618 if (!powerof2(scctx->isc_ntxd[i])) { 4619 device_printf(dev, 4620 "# tx descriptors must be a power of 2"); 4621 err = EINVAL; 4622 goto fail_iflib_detach; 4623 } 4624 } 4625 4626 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4627 MAX_SINGLE_PACKET_FRACTION) 4628 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4629 MAX_SINGLE_PACKET_FRACTION); 4630 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4631 MAX_SINGLE_PACKET_FRACTION) 4632 scctx->isc_tx_tso_segments_max = max(1, 4633 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4634 4635 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4636 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4637 /* 4638 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4639 * but some MACs do. 4640 */ 4641 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4642 IP_MAXPACKET)); 4643 /* 4644 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4645 * into account. In the worst case, each of these calls will 4646 * add another mbuf and, thus, the requirement for another DMA 4647 * segment. So for best performance, it doesn't make sense to 4648 * advertize a maximum of TSO segments that typically will 4649 * require defragmentation in iflib_encap(). 4650 */ 4651 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4652 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4653 } 4654 if (scctx->isc_rss_table_size == 0) 4655 scctx->isc_rss_table_size = 64; 4656 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4657 4658 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4659 /* XXX format name */ 4660 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4661 NULL, NULL, "admin"); 4662 4663 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4664 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4665 device_printf(dev, "Unable to fetch CPU list\n"); 4666 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4667 } 4668 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4669 4670 /* 4671 ** Now set up MSI or MSI-X, should return us the number of supported 4672 ** vectors (will be 1 for a legacy interrupt and MSI). 4673 */ 4674 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4675 msix = scctx->isc_vectors; 4676 } else if (scctx->isc_msix_bar != 0) 4677 /* 4678 * The simple fact that isc_msix_bar is not 0 does not mean we 4679 * we have a good value there that is known to work. 4680 */ 4681 msix = iflib_msix_init(ctx); 4682 else { 4683 scctx->isc_vectors = 1; 4684 scctx->isc_ntxqsets = 1; 4685 scctx->isc_nrxqsets = 1; 4686 scctx->isc_intr = IFLIB_INTR_LEGACY; 4687 msix = 0; 4688 } 4689 /* Get memory for the station queues */ 4690 if ((err = iflib_queues_alloc(ctx))) { 4691 device_printf(dev, "Unable to allocate queue memory\n"); 4692 goto fail_intr_free; 4693 } 4694 4695 if ((err = iflib_qset_structures_setup(ctx))) 4696 goto fail_queues; 4697 4698 /* 4699 * Now that we know how many queues there are, get the core offset. 4700 */ 4701 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 4702 4703 /* 4704 * Group taskqueues aren't properly set up until SMP is started, 4705 * so we disable interrupts until we can handle them post 4706 * SI_SUB_SMP. 4707 * 4708 * XXX: disabling interrupts doesn't actually work, at least for 4709 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4710 * we do null handling and depend on this not causing too large an 4711 * interrupt storm. 4712 */ 4713 IFDI_INTR_DISABLE(ctx); 4714 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4715 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4716 goto fail_queues; 4717 } 4718 if (msix <= 1) { 4719 rid = 0; 4720 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4721 MPASS(msix == 1); 4722 rid = 1; 4723 } 4724 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4725 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4726 goto fail_queues; 4727 } 4728 } 4729 4730 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4731 4732 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4733 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4734 goto fail_detach; 4735 } 4736 4737 /* 4738 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4739 * This must appear after the call to ether_ifattach() because 4740 * ether_ifattach() sets if_hdrlen to the default value. 4741 */ 4742 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4743 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4744 4745 if ((err = iflib_netmap_attach(ctx))) { 4746 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4747 goto fail_detach; 4748 } 4749 *ctxp = ctx; 4750 4751 NETDUMP_SET(ctx->ifc_ifp, iflib); 4752 4753 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4754 iflib_add_device_sysctl_post(ctx); 4755 iflib_add_pfil(ctx); 4756 ctx->ifc_flags |= IFC_INIT_DONE; 4757 CTX_UNLOCK(ctx); 4758 return (0); 4759 4760 fail_detach: 4761 ether_ifdetach(ctx->ifc_ifp); 4762 fail_intr_free: 4763 iflib_free_intr_mem(ctx); 4764 fail_queues: 4765 iflib_tx_structures_free(ctx); 4766 iflib_rx_structures_free(ctx); 4767 fail_iflib_detach: 4768 IFDI_DETACH(ctx); 4769 fail_unlock: 4770 CTX_UNLOCK(ctx); 4771 fail_ctx_free: 4772 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4773 free(ctx->ifc_softc, M_IFLIB); 4774 free(ctx, M_IFLIB); 4775 return (err); 4776 } 4777 4778 int 4779 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4780 struct iflib_cloneattach_ctx *clctx) 4781 { 4782 int err; 4783 if_ctx_t ctx; 4784 if_t ifp; 4785 if_softc_ctx_t scctx; 4786 int i; 4787 void *sc; 4788 uint16_t main_txq; 4789 uint16_t main_rxq; 4790 4791 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4792 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4793 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4794 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4795 ctx->ifc_flags |= IFC_PSEUDO; 4796 4797 ctx->ifc_sctx = sctx; 4798 ctx->ifc_softc = sc; 4799 ctx->ifc_dev = dev; 4800 4801 if ((err = iflib_register(ctx)) != 0) { 4802 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4803 goto fail_ctx_free; 4804 } 4805 iflib_add_device_sysctl_pre(ctx); 4806 4807 scctx = &ctx->ifc_softc_ctx; 4808 ifp = ctx->ifc_ifp; 4809 4810 /* 4811 * XXX sanity check that ntxd & nrxd are a power of 2 4812 */ 4813 iflib_reset_qvalues(ctx); 4814 CTX_LOCK(ctx); 4815 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4816 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4817 goto fail_unlock; 4818 } 4819 if (sctx->isc_flags & IFLIB_GEN_MAC) 4820 ether_gen_addr(ifp, &ctx->ifc_mac); 4821 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4822 clctx->cc_params)) != 0) { 4823 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4824 goto fail_ctx_free; 4825 } 4826 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4827 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4828 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4829 4830 #ifdef INVARIANTS 4831 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4832 MPASS(scctx->isc_tx_csum_flags); 4833 #endif 4834 4835 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4836 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4837 4838 ifp->if_flags |= IFF_NOGROUP; 4839 if (sctx->isc_flags & IFLIB_PSEUDO) { 4840 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4841 4842 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4843 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4844 goto fail_detach; 4845 } 4846 *ctxp = ctx; 4847 4848 /* 4849 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4850 * This must appear after the call to ether_ifattach() because 4851 * ether_ifattach() sets if_hdrlen to the default value. 4852 */ 4853 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4854 if_setifheaderlen(ifp, 4855 sizeof(struct ether_vlan_header)); 4856 4857 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4858 iflib_add_device_sysctl_post(ctx); 4859 ctx->ifc_flags |= IFC_INIT_DONE; 4860 return (0); 4861 } 4862 _iflib_pre_assert(scctx); 4863 ctx->ifc_txrx = *scctx->isc_txrx; 4864 4865 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4866 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4867 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4868 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4869 4870 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4871 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4872 4873 /* XXX change for per-queue sizes */ 4874 device_printf(dev, "Using %d tx descriptors and %d rx descriptors\n", 4875 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4876 for (i = 0; i < sctx->isc_nrxqs; i++) { 4877 if (!powerof2(scctx->isc_nrxd[i])) { 4878 /* round down instead? */ 4879 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4880 err = EINVAL; 4881 goto fail_iflib_detach; 4882 } 4883 } 4884 for (i = 0; i < sctx->isc_ntxqs; i++) { 4885 if (!powerof2(scctx->isc_ntxd[i])) { 4886 device_printf(dev, 4887 "# tx descriptors must be a power of 2"); 4888 err = EINVAL; 4889 goto fail_iflib_detach; 4890 } 4891 } 4892 4893 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4894 MAX_SINGLE_PACKET_FRACTION) 4895 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4896 MAX_SINGLE_PACKET_FRACTION); 4897 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4898 MAX_SINGLE_PACKET_FRACTION) 4899 scctx->isc_tx_tso_segments_max = max(1, 4900 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4901 4902 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4903 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4904 /* 4905 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4906 * but some MACs do. 4907 */ 4908 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4909 IP_MAXPACKET)); 4910 /* 4911 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4912 * into account. In the worst case, each of these calls will 4913 * add another mbuf and, thus, the requirement for another DMA 4914 * segment. So for best performance, it doesn't make sense to 4915 * advertize a maximum of TSO segments that typically will 4916 * require defragmentation in iflib_encap(). 4917 */ 4918 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4919 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4920 } 4921 if (scctx->isc_rss_table_size == 0) 4922 scctx->isc_rss_table_size = 64; 4923 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4924 4925 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4926 /* XXX format name */ 4927 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4928 NULL, NULL, "admin"); 4929 4930 /* XXX --- can support > 1 -- but keep it simple for now */ 4931 scctx->isc_intr = IFLIB_INTR_LEGACY; 4932 4933 /* Get memory for the station queues */ 4934 if ((err = iflib_queues_alloc(ctx))) { 4935 device_printf(dev, "Unable to allocate queue memory\n"); 4936 goto fail_iflib_detach; 4937 } 4938 4939 if ((err = iflib_qset_structures_setup(ctx))) { 4940 device_printf(dev, "qset structure setup failed %d\n", err); 4941 goto fail_queues; 4942 } 4943 4944 /* 4945 * XXX What if anything do we want to do about interrupts? 4946 */ 4947 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4948 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4949 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4950 goto fail_detach; 4951 } 4952 4953 /* 4954 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4955 * This must appear after the call to ether_ifattach() because 4956 * ether_ifattach() sets if_hdrlen to the default value. 4957 */ 4958 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4959 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4960 4961 /* XXX handle more than one queue */ 4962 for (i = 0; i < scctx->isc_nrxqsets; i++) 4963 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4964 4965 *ctxp = ctx; 4966 4967 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4968 iflib_add_device_sysctl_post(ctx); 4969 ctx->ifc_flags |= IFC_INIT_DONE; 4970 CTX_UNLOCK(ctx); 4971 return (0); 4972 fail_detach: 4973 ether_ifdetach(ctx->ifc_ifp); 4974 fail_queues: 4975 iflib_tx_structures_free(ctx); 4976 iflib_rx_structures_free(ctx); 4977 fail_iflib_detach: 4978 IFDI_DETACH(ctx); 4979 fail_unlock: 4980 CTX_UNLOCK(ctx); 4981 fail_ctx_free: 4982 free(ctx->ifc_softc, M_IFLIB); 4983 free(ctx, M_IFLIB); 4984 return (err); 4985 } 4986 4987 int 4988 iflib_pseudo_deregister(if_ctx_t ctx) 4989 { 4990 if_t ifp = ctx->ifc_ifp; 4991 iflib_txq_t txq; 4992 iflib_rxq_t rxq; 4993 int i, j; 4994 struct taskqgroup *tqg; 4995 iflib_fl_t fl; 4996 4997 /* Unregister VLAN events */ 4998 if (ctx->ifc_vlan_attach_event != NULL) 4999 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5000 if (ctx->ifc_vlan_detach_event != NULL) 5001 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5002 5003 ether_ifdetach(ifp); 5004 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5005 CTX_LOCK_DESTROY(ctx); 5006 /* XXX drain any dependent tasks */ 5007 tqg = qgroup_if_io_tqg; 5008 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5009 callout_drain(&txq->ift_timer); 5010 if (txq->ift_task.gt_uniq != NULL) 5011 taskqgroup_detach(tqg, &txq->ift_task); 5012 } 5013 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5014 if (rxq->ifr_task.gt_uniq != NULL) 5015 taskqgroup_detach(tqg, &rxq->ifr_task); 5016 5017 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5018 free(fl->ifl_rx_bitmap, M_IFLIB); 5019 } 5020 tqg = qgroup_if_config_tqg; 5021 if (ctx->ifc_admin_task.gt_uniq != NULL) 5022 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5023 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5024 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5025 5026 if_free(ifp); 5027 5028 iflib_tx_structures_free(ctx); 5029 iflib_rx_structures_free(ctx); 5030 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5031 free(ctx->ifc_softc, M_IFLIB); 5032 free(ctx, M_IFLIB); 5033 return (0); 5034 } 5035 5036 int 5037 iflib_device_attach(device_t dev) 5038 { 5039 if_ctx_t ctx; 5040 if_shared_ctx_t sctx; 5041 5042 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5043 return (ENOTSUP); 5044 5045 pci_enable_busmaster(dev); 5046 5047 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5048 } 5049 5050 int 5051 iflib_device_deregister(if_ctx_t ctx) 5052 { 5053 if_t ifp = ctx->ifc_ifp; 5054 iflib_txq_t txq; 5055 iflib_rxq_t rxq; 5056 device_t dev = ctx->ifc_dev; 5057 int i, j; 5058 struct taskqgroup *tqg; 5059 iflib_fl_t fl; 5060 5061 /* Make sure VLANS are not using driver */ 5062 if (if_vlantrunkinuse(ifp)) { 5063 device_printf(dev, "Vlan in use, detach first\n"); 5064 return (EBUSY); 5065 } 5066 #ifdef PCI_IOV 5067 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5068 device_printf(dev, "SR-IOV in use; detach first.\n"); 5069 return (EBUSY); 5070 } 5071 #endif 5072 5073 STATE_LOCK(ctx); 5074 ctx->ifc_flags |= IFC_IN_DETACH; 5075 STATE_UNLOCK(ctx); 5076 5077 CTX_LOCK(ctx); 5078 iflib_stop(ctx); 5079 CTX_UNLOCK(ctx); 5080 5081 /* Unregister VLAN events */ 5082 if (ctx->ifc_vlan_attach_event != NULL) 5083 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5084 if (ctx->ifc_vlan_detach_event != NULL) 5085 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5086 5087 iflib_netmap_detach(ifp); 5088 ether_ifdetach(ifp); 5089 iflib_rem_pfil(ctx); 5090 if (ctx->ifc_led_dev != NULL) 5091 led_destroy(ctx->ifc_led_dev); 5092 /* XXX drain any dependent tasks */ 5093 tqg = qgroup_if_io_tqg; 5094 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5095 callout_drain(&txq->ift_timer); 5096 if (txq->ift_task.gt_uniq != NULL) 5097 taskqgroup_detach(tqg, &txq->ift_task); 5098 } 5099 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5100 if (rxq->ifr_task.gt_uniq != NULL) 5101 taskqgroup_detach(tqg, &rxq->ifr_task); 5102 5103 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5104 free(fl->ifl_rx_bitmap, M_IFLIB); 5105 } 5106 tqg = qgroup_if_config_tqg; 5107 if (ctx->ifc_admin_task.gt_uniq != NULL) 5108 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5109 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5110 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5111 CTX_LOCK(ctx); 5112 IFDI_DETACH(ctx); 5113 CTX_UNLOCK(ctx); 5114 5115 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5116 CTX_LOCK_DESTROY(ctx); 5117 device_set_softc(ctx->ifc_dev, NULL); 5118 iflib_free_intr_mem(ctx); 5119 5120 bus_generic_detach(dev); 5121 if_free(ifp); 5122 5123 iflib_tx_structures_free(ctx); 5124 iflib_rx_structures_free(ctx); 5125 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5126 free(ctx->ifc_softc, M_IFLIB); 5127 unref_ctx_core_offset(ctx); 5128 STATE_LOCK_DESTROY(ctx); 5129 free(ctx, M_IFLIB); 5130 return (0); 5131 } 5132 5133 static void 5134 iflib_free_intr_mem(if_ctx_t ctx) 5135 { 5136 5137 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5138 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5139 } 5140 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5141 pci_release_msi(ctx->ifc_dev); 5142 } 5143 if (ctx->ifc_msix_mem != NULL) { 5144 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5145 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5146 ctx->ifc_msix_mem = NULL; 5147 } 5148 } 5149 5150 int 5151 iflib_device_detach(device_t dev) 5152 { 5153 if_ctx_t ctx = device_get_softc(dev); 5154 5155 return (iflib_device_deregister(ctx)); 5156 } 5157 5158 int 5159 iflib_device_suspend(device_t dev) 5160 { 5161 if_ctx_t ctx = device_get_softc(dev); 5162 5163 CTX_LOCK(ctx); 5164 IFDI_SUSPEND(ctx); 5165 CTX_UNLOCK(ctx); 5166 5167 return bus_generic_suspend(dev); 5168 } 5169 int 5170 iflib_device_shutdown(device_t dev) 5171 { 5172 if_ctx_t ctx = device_get_softc(dev); 5173 5174 CTX_LOCK(ctx); 5175 IFDI_SHUTDOWN(ctx); 5176 CTX_UNLOCK(ctx); 5177 5178 return bus_generic_suspend(dev); 5179 } 5180 5181 5182 int 5183 iflib_device_resume(device_t dev) 5184 { 5185 if_ctx_t ctx = device_get_softc(dev); 5186 iflib_txq_t txq = ctx->ifc_txqs; 5187 5188 CTX_LOCK(ctx); 5189 IFDI_RESUME(ctx); 5190 iflib_if_init_locked(ctx); 5191 CTX_UNLOCK(ctx); 5192 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5193 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5194 5195 return (bus_generic_resume(dev)); 5196 } 5197 5198 int 5199 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5200 { 5201 int error; 5202 if_ctx_t ctx = device_get_softc(dev); 5203 5204 CTX_LOCK(ctx); 5205 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5206 CTX_UNLOCK(ctx); 5207 5208 return (error); 5209 } 5210 5211 void 5212 iflib_device_iov_uninit(device_t dev) 5213 { 5214 if_ctx_t ctx = device_get_softc(dev); 5215 5216 CTX_LOCK(ctx); 5217 IFDI_IOV_UNINIT(ctx); 5218 CTX_UNLOCK(ctx); 5219 } 5220 5221 int 5222 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5223 { 5224 int error; 5225 if_ctx_t ctx = device_get_softc(dev); 5226 5227 CTX_LOCK(ctx); 5228 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5229 CTX_UNLOCK(ctx); 5230 5231 return (error); 5232 } 5233 5234 /********************************************************************* 5235 * 5236 * MODULE FUNCTION DEFINITIONS 5237 * 5238 **********************************************************************/ 5239 5240 /* 5241 * - Start a fast taskqueue thread for each core 5242 * - Start a taskqueue for control operations 5243 */ 5244 static int 5245 iflib_module_init(void) 5246 { 5247 return (0); 5248 } 5249 5250 static int 5251 iflib_module_event_handler(module_t mod, int what, void *arg) 5252 { 5253 int err; 5254 5255 switch (what) { 5256 case MOD_LOAD: 5257 if ((err = iflib_module_init()) != 0) 5258 return (err); 5259 break; 5260 case MOD_UNLOAD: 5261 return (EBUSY); 5262 default: 5263 return (EOPNOTSUPP); 5264 } 5265 5266 return (0); 5267 } 5268 5269 /********************************************************************* 5270 * 5271 * PUBLIC FUNCTION DEFINITIONS 5272 * ordered as in iflib.h 5273 * 5274 **********************************************************************/ 5275 5276 5277 static void 5278 _iflib_assert(if_shared_ctx_t sctx) 5279 { 5280 MPASS(sctx->isc_tx_maxsize); 5281 MPASS(sctx->isc_tx_maxsegsize); 5282 5283 MPASS(sctx->isc_rx_maxsize); 5284 MPASS(sctx->isc_rx_nsegments); 5285 MPASS(sctx->isc_rx_maxsegsize); 5286 5287 MPASS(sctx->isc_nrxd_min[0]); 5288 MPASS(sctx->isc_nrxd_max[0]); 5289 MPASS(sctx->isc_nrxd_default[0]); 5290 MPASS(sctx->isc_ntxd_min[0]); 5291 MPASS(sctx->isc_ntxd_max[0]); 5292 MPASS(sctx->isc_ntxd_default[0]); 5293 } 5294 5295 static void 5296 _iflib_pre_assert(if_softc_ctx_t scctx) 5297 { 5298 5299 MPASS(scctx->isc_txrx->ift_txd_encap); 5300 MPASS(scctx->isc_txrx->ift_txd_flush); 5301 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5302 MPASS(scctx->isc_txrx->ift_rxd_available); 5303 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5304 MPASS(scctx->isc_txrx->ift_rxd_refill); 5305 MPASS(scctx->isc_txrx->ift_rxd_flush); 5306 } 5307 5308 static int 5309 iflib_register(if_ctx_t ctx) 5310 { 5311 if_shared_ctx_t sctx = ctx->ifc_sctx; 5312 driver_t *driver = sctx->isc_driver; 5313 device_t dev = ctx->ifc_dev; 5314 if_t ifp; 5315 5316 _iflib_assert(sctx); 5317 5318 CTX_LOCK_INIT(ctx); 5319 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5320 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5321 if (ifp == NULL) { 5322 device_printf(dev, "can not allocate ifnet structure\n"); 5323 return (ENOMEM); 5324 } 5325 5326 /* 5327 * Initialize our context's device specific methods 5328 */ 5329 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5330 kobj_class_compile((kobj_class_t) driver); 5331 driver->refs++; 5332 5333 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5334 if_setsoftc(ifp, ctx); 5335 if_setdev(ifp, dev); 5336 if_setinitfn(ifp, iflib_if_init); 5337 if_setioctlfn(ifp, iflib_if_ioctl); 5338 #ifdef ALTQ 5339 if_setstartfn(ifp, iflib_altq_if_start); 5340 if_settransmitfn(ifp, iflib_altq_if_transmit); 5341 if_setsendqready(ifp); 5342 #else 5343 if_settransmitfn(ifp, iflib_if_transmit); 5344 #endif 5345 if_setqflushfn(ifp, iflib_if_qflush); 5346 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5347 5348 ctx->ifc_vlan_attach_event = 5349 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5350 EVENTHANDLER_PRI_FIRST); 5351 ctx->ifc_vlan_detach_event = 5352 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5353 EVENTHANDLER_PRI_FIRST); 5354 5355 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5356 ctx->ifc_mediap = &ctx->ifc_media; 5357 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5358 iflib_media_change, iflib_media_status); 5359 } 5360 return (0); 5361 } 5362 5363 5364 static int 5365 iflib_queues_alloc(if_ctx_t ctx) 5366 { 5367 if_shared_ctx_t sctx = ctx->ifc_sctx; 5368 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5369 device_t dev = ctx->ifc_dev; 5370 int nrxqsets = scctx->isc_nrxqsets; 5371 int ntxqsets = scctx->isc_ntxqsets; 5372 iflib_txq_t txq; 5373 iflib_rxq_t rxq; 5374 iflib_fl_t fl = NULL; 5375 int i, j, cpu, err, txconf, rxconf; 5376 iflib_dma_info_t ifdip; 5377 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5378 uint32_t *txqsizes = scctx->isc_txqsizes; 5379 uint8_t nrxqs = sctx->isc_nrxqs; 5380 uint8_t ntxqs = sctx->isc_ntxqs; 5381 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5382 caddr_t *vaddrs; 5383 uint64_t *paddrs; 5384 5385 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5386 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5387 5388 /* Allocate the TX ring struct memory */ 5389 if (!(ctx->ifc_txqs = 5390 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5391 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5392 device_printf(dev, "Unable to allocate TX ring memory\n"); 5393 err = ENOMEM; 5394 goto fail; 5395 } 5396 5397 /* Now allocate the RX */ 5398 if (!(ctx->ifc_rxqs = 5399 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5400 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5401 device_printf(dev, "Unable to allocate RX ring memory\n"); 5402 err = ENOMEM; 5403 goto rx_fail; 5404 } 5405 5406 txq = ctx->ifc_txqs; 5407 rxq = ctx->ifc_rxqs; 5408 5409 /* 5410 * XXX handle allocation failure 5411 */ 5412 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5413 /* Set up some basics */ 5414 5415 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5416 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5417 device_printf(dev, 5418 "Unable to allocate TX DMA info memory\n"); 5419 err = ENOMEM; 5420 goto err_tx_desc; 5421 } 5422 txq->ift_ifdi = ifdip; 5423 for (j = 0; j < ntxqs; j++, ifdip++) { 5424 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5425 device_printf(dev, 5426 "Unable to allocate TX descriptors\n"); 5427 err = ENOMEM; 5428 goto err_tx_desc; 5429 } 5430 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5431 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5432 } 5433 txq->ift_ctx = ctx; 5434 txq->ift_id = i; 5435 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5436 txq->ift_br_offset = 1; 5437 } else { 5438 txq->ift_br_offset = 0; 5439 } 5440 /* XXX fix this */ 5441 txq->ift_timer.c_cpu = cpu; 5442 5443 if (iflib_txsd_alloc(txq)) { 5444 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5445 err = ENOMEM; 5446 goto err_tx_desc; 5447 } 5448 5449 /* Initialize the TX lock */ 5450 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 5451 device_get_nameunit(dev), txq->ift_id); 5452 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5453 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5454 5455 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 5456 device_get_nameunit(dev), txq->ift_id); 5457 5458 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5459 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5460 if (err) { 5461 /* XXX free any allocated rings */ 5462 device_printf(dev, "Unable to allocate buf_ring\n"); 5463 goto err_tx_desc; 5464 } 5465 } 5466 5467 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5468 /* Set up some basics */ 5469 5470 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5471 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5472 device_printf(dev, 5473 "Unable to allocate RX DMA info memory\n"); 5474 err = ENOMEM; 5475 goto err_tx_desc; 5476 } 5477 5478 rxq->ifr_ifdi = ifdip; 5479 /* XXX this needs to be changed if #rx queues != #tx queues */ 5480 rxq->ifr_ntxqirq = 1; 5481 rxq->ifr_txqid[0] = i; 5482 for (j = 0; j < nrxqs; j++, ifdip++) { 5483 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5484 device_printf(dev, 5485 "Unable to allocate RX descriptors\n"); 5486 err = ENOMEM; 5487 goto err_tx_desc; 5488 } 5489 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5490 } 5491 rxq->ifr_ctx = ctx; 5492 rxq->ifr_id = i; 5493 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5494 rxq->ifr_fl_offset = 1; 5495 } else { 5496 rxq->ifr_fl_offset = 0; 5497 } 5498 rxq->ifr_nfl = nfree_lists; 5499 if (!(fl = 5500 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5501 device_printf(dev, "Unable to allocate free list memory\n"); 5502 err = ENOMEM; 5503 goto err_tx_desc; 5504 } 5505 rxq->ifr_fl = fl; 5506 for (j = 0; j < nfree_lists; j++) { 5507 fl[j].ifl_rxq = rxq; 5508 fl[j].ifl_id = j; 5509 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5510 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5511 } 5512 /* Allocate receive buffers for the ring */ 5513 if (iflib_rxsd_alloc(rxq)) { 5514 device_printf(dev, 5515 "Critical Failure setting up receive buffers\n"); 5516 err = ENOMEM; 5517 goto err_rx_desc; 5518 } 5519 5520 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5521 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5522 M_WAITOK); 5523 } 5524 5525 /* TXQs */ 5526 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5527 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5528 for (i = 0; i < ntxqsets; i++) { 5529 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5530 5531 for (j = 0; j < ntxqs; j++, di++) { 5532 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5533 paddrs[i*ntxqs + j] = di->idi_paddr; 5534 } 5535 } 5536 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5537 device_printf(ctx->ifc_dev, 5538 "Unable to allocate device TX queue\n"); 5539 iflib_tx_structures_free(ctx); 5540 free(vaddrs, M_IFLIB); 5541 free(paddrs, M_IFLIB); 5542 goto err_rx_desc; 5543 } 5544 free(vaddrs, M_IFLIB); 5545 free(paddrs, M_IFLIB); 5546 5547 /* RXQs */ 5548 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5549 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5550 for (i = 0; i < nrxqsets; i++) { 5551 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5552 5553 for (j = 0; j < nrxqs; j++, di++) { 5554 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5555 paddrs[i*nrxqs + j] = di->idi_paddr; 5556 } 5557 } 5558 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5559 device_printf(ctx->ifc_dev, 5560 "Unable to allocate device RX queue\n"); 5561 iflib_tx_structures_free(ctx); 5562 free(vaddrs, M_IFLIB); 5563 free(paddrs, M_IFLIB); 5564 goto err_rx_desc; 5565 } 5566 free(vaddrs, M_IFLIB); 5567 free(paddrs, M_IFLIB); 5568 5569 return (0); 5570 5571 /* XXX handle allocation failure changes */ 5572 err_rx_desc: 5573 err_tx_desc: 5574 rx_fail: 5575 if (ctx->ifc_rxqs != NULL) 5576 free(ctx->ifc_rxqs, M_IFLIB); 5577 ctx->ifc_rxqs = NULL; 5578 if (ctx->ifc_txqs != NULL) 5579 free(ctx->ifc_txqs, M_IFLIB); 5580 ctx->ifc_txqs = NULL; 5581 fail: 5582 return (err); 5583 } 5584 5585 static int 5586 iflib_tx_structures_setup(if_ctx_t ctx) 5587 { 5588 iflib_txq_t txq = ctx->ifc_txqs; 5589 int i; 5590 5591 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5592 iflib_txq_setup(txq); 5593 5594 return (0); 5595 } 5596 5597 static void 5598 iflib_tx_structures_free(if_ctx_t ctx) 5599 { 5600 iflib_txq_t txq = ctx->ifc_txqs; 5601 if_shared_ctx_t sctx = ctx->ifc_sctx; 5602 int i, j; 5603 5604 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5605 iflib_txq_destroy(txq); 5606 for (j = 0; j < sctx->isc_ntxqs; j++) 5607 iflib_dma_free(&txq->ift_ifdi[j]); 5608 } 5609 free(ctx->ifc_txqs, M_IFLIB); 5610 ctx->ifc_txqs = NULL; 5611 IFDI_QUEUES_FREE(ctx); 5612 } 5613 5614 /********************************************************************* 5615 * 5616 * Initialize all receive rings. 5617 * 5618 **********************************************************************/ 5619 static int 5620 iflib_rx_structures_setup(if_ctx_t ctx) 5621 { 5622 iflib_rxq_t rxq = ctx->ifc_rxqs; 5623 int q; 5624 #if defined(INET6) || defined(INET) 5625 int i, err; 5626 #endif 5627 5628 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5629 #if defined(INET6) || defined(INET) 5630 tcp_lro_free(&rxq->ifr_lc); 5631 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5632 TCP_LRO_ENTRIES, min(1024, 5633 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 5634 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 5635 goto fail; 5636 } 5637 rxq->ifr_lro_enabled = TRUE; 5638 #endif 5639 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5640 } 5641 return (0); 5642 #if defined(INET6) || defined(INET) 5643 fail: 5644 /* 5645 * Free RX software descriptors allocated so far, we will only handle 5646 * the rings that completed, the failing case will have 5647 * cleaned up for itself. 'q' failed, so its the terminus. 5648 */ 5649 rxq = ctx->ifc_rxqs; 5650 for (i = 0; i < q; ++i, rxq++) { 5651 iflib_rx_sds_free(rxq); 5652 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5653 } 5654 return (err); 5655 #endif 5656 } 5657 5658 /********************************************************************* 5659 * 5660 * Free all receive rings. 5661 * 5662 **********************************************************************/ 5663 static void 5664 iflib_rx_structures_free(if_ctx_t ctx) 5665 { 5666 iflib_rxq_t rxq = ctx->ifc_rxqs; 5667 5668 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5669 iflib_rx_sds_free(rxq); 5670 } 5671 free(ctx->ifc_rxqs, M_IFLIB); 5672 ctx->ifc_rxqs = NULL; 5673 } 5674 5675 static int 5676 iflib_qset_structures_setup(if_ctx_t ctx) 5677 { 5678 int err; 5679 5680 /* 5681 * It is expected that the caller takes care of freeing queues if this 5682 * fails. 5683 */ 5684 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5685 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5686 return (err); 5687 } 5688 5689 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5690 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5691 5692 return (err); 5693 } 5694 5695 int 5696 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5697 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5698 { 5699 5700 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5701 } 5702 5703 #ifdef SMP 5704 static int 5705 find_nth(if_ctx_t ctx, int qid) 5706 { 5707 cpuset_t cpus; 5708 int i, cpuid, eqid, count; 5709 5710 CPU_COPY(&ctx->ifc_cpus, &cpus); 5711 count = CPU_COUNT(&cpus); 5712 eqid = qid % count; 5713 /* clear up to the qid'th bit */ 5714 for (i = 0; i < eqid; i++) { 5715 cpuid = CPU_FFS(&cpus); 5716 MPASS(cpuid != 0); 5717 CPU_CLR(cpuid-1, &cpus); 5718 } 5719 cpuid = CPU_FFS(&cpus); 5720 MPASS(cpuid != 0); 5721 return (cpuid-1); 5722 } 5723 5724 #ifdef SCHED_ULE 5725 extern struct cpu_group *cpu_top; /* CPU topology */ 5726 5727 static int 5728 find_child_with_core(int cpu, struct cpu_group *grp) 5729 { 5730 int i; 5731 5732 if (grp->cg_children == 0) 5733 return -1; 5734 5735 MPASS(grp->cg_child); 5736 for (i = 0; i < grp->cg_children; i++) { 5737 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5738 return i; 5739 } 5740 5741 return -1; 5742 } 5743 5744 /* 5745 * Find the nth "close" core to the specified core 5746 * "close" is defined as the deepest level that shares 5747 * at least an L2 cache. With threads, this will be 5748 * threads on the same core. If the shared cache is L3 5749 * or higher, simply returns the same core. 5750 */ 5751 static int 5752 find_close_core(int cpu, int core_offset) 5753 { 5754 struct cpu_group *grp; 5755 int i; 5756 int fcpu; 5757 cpuset_t cs; 5758 5759 grp = cpu_top; 5760 if (grp == NULL) 5761 return cpu; 5762 i = 0; 5763 while ((i = find_child_with_core(cpu, grp)) != -1) { 5764 /* If the child only has one cpu, don't descend */ 5765 if (grp->cg_child[i].cg_count <= 1) 5766 break; 5767 grp = &grp->cg_child[i]; 5768 } 5769 5770 /* If they don't share at least an L2 cache, use the same CPU */ 5771 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5772 return cpu; 5773 5774 /* Now pick one */ 5775 CPU_COPY(&grp->cg_mask, &cs); 5776 5777 /* Add the selected CPU offset to core offset. */ 5778 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5779 if (fcpu - 1 == cpu) 5780 break; 5781 CPU_CLR(fcpu - 1, &cs); 5782 } 5783 MPASS(fcpu); 5784 5785 core_offset += i; 5786 5787 CPU_COPY(&grp->cg_mask, &cs); 5788 for (i = core_offset % grp->cg_count; i > 0; i--) { 5789 MPASS(CPU_FFS(&cs)); 5790 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5791 } 5792 MPASS(CPU_FFS(&cs)); 5793 return CPU_FFS(&cs) - 1; 5794 } 5795 #else 5796 static int 5797 find_close_core(int cpu, int core_offset __unused) 5798 { 5799 return cpu; 5800 } 5801 #endif 5802 5803 static int 5804 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5805 { 5806 switch (type) { 5807 case IFLIB_INTR_TX: 5808 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5809 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5810 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5811 case IFLIB_INTR_RX: 5812 case IFLIB_INTR_RXTX: 5813 /* RX queues get the specified core */ 5814 return qid / CPU_COUNT(&ctx->ifc_cpus); 5815 default: 5816 return -1; 5817 } 5818 } 5819 #else 5820 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5821 #define find_close_core(cpuid, tid) CPU_FIRST() 5822 #define find_nth(ctx, gid) CPU_FIRST() 5823 #endif 5824 5825 /* Just to avoid copy/paste */ 5826 static inline int 5827 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5828 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5829 const char *name) 5830 { 5831 device_t dev; 5832 int co, cpuid, err, tid; 5833 5834 dev = ctx->ifc_dev; 5835 co = ctx->ifc_sysctl_core_offset; 5836 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX) 5837 co += ctx->ifc_softc_ctx.isc_nrxqsets; 5838 cpuid = find_nth(ctx, qid + co); 5839 tid = get_core_offset(ctx, type, qid); 5840 MPASS(tid >= 0); 5841 cpuid = find_close_core(cpuid, tid); 5842 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 5843 name); 5844 if (err) { 5845 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 5846 return (err); 5847 } 5848 #ifdef notyet 5849 if (cpuid > ctx->ifc_cpuid_highest) 5850 ctx->ifc_cpuid_highest = cpuid; 5851 #endif 5852 return 0; 5853 } 5854 5855 int 5856 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5857 iflib_intr_type_t type, driver_filter_t *filter, 5858 void *filter_arg, int qid, const char *name) 5859 { 5860 device_t dev; 5861 struct grouptask *gtask; 5862 struct taskqgroup *tqg; 5863 iflib_filter_info_t info; 5864 gtask_fn_t *fn; 5865 int tqrid, err; 5866 driver_filter_t *intr_fast; 5867 void *q; 5868 5869 info = &ctx->ifc_filter_info; 5870 tqrid = rid; 5871 5872 switch (type) { 5873 /* XXX merge tx/rx for netmap? */ 5874 case IFLIB_INTR_TX: 5875 q = &ctx->ifc_txqs[qid]; 5876 info = &ctx->ifc_txqs[qid].ift_filter_info; 5877 gtask = &ctx->ifc_txqs[qid].ift_task; 5878 tqg = qgroup_if_io_tqg; 5879 fn = _task_fn_tx; 5880 intr_fast = iflib_fast_intr; 5881 GROUPTASK_INIT(gtask, 0, fn, q); 5882 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5883 break; 5884 case IFLIB_INTR_RX: 5885 q = &ctx->ifc_rxqs[qid]; 5886 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5887 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5888 tqg = qgroup_if_io_tqg; 5889 fn = _task_fn_rx; 5890 intr_fast = iflib_fast_intr; 5891 GROUPTASK_INIT(gtask, 0, fn, q); 5892 break; 5893 case IFLIB_INTR_RXTX: 5894 q = &ctx->ifc_rxqs[qid]; 5895 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5896 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5897 tqg = qgroup_if_io_tqg; 5898 fn = _task_fn_rx; 5899 intr_fast = iflib_fast_intr_rxtx; 5900 GROUPTASK_INIT(gtask, 0, fn, q); 5901 break; 5902 case IFLIB_INTR_ADMIN: 5903 q = ctx; 5904 tqrid = -1; 5905 info = &ctx->ifc_filter_info; 5906 gtask = &ctx->ifc_admin_task; 5907 tqg = qgroup_if_config_tqg; 5908 fn = _task_fn_admin; 5909 intr_fast = iflib_fast_intr_ctx; 5910 break; 5911 default: 5912 panic("unknown net intr type"); 5913 } 5914 5915 info->ifi_filter = filter; 5916 info->ifi_filter_arg = filter_arg; 5917 info->ifi_task = gtask; 5918 info->ifi_ctx = q; 5919 5920 dev = ctx->ifc_dev; 5921 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5922 if (err != 0) { 5923 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 5924 return (err); 5925 } 5926 if (type == IFLIB_INTR_ADMIN) 5927 return (0); 5928 5929 if (tqrid != -1) { 5930 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 5931 q, name); 5932 if (err) 5933 return (err); 5934 } else { 5935 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 5936 } 5937 5938 return (0); 5939 } 5940 5941 void 5942 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 5943 { 5944 struct grouptask *gtask; 5945 struct taskqgroup *tqg; 5946 gtask_fn_t *fn; 5947 void *q; 5948 int err; 5949 5950 switch (type) { 5951 case IFLIB_INTR_TX: 5952 q = &ctx->ifc_txqs[qid]; 5953 gtask = &ctx->ifc_txqs[qid].ift_task; 5954 tqg = qgroup_if_io_tqg; 5955 fn = _task_fn_tx; 5956 break; 5957 case IFLIB_INTR_RX: 5958 q = &ctx->ifc_rxqs[qid]; 5959 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5960 tqg = qgroup_if_io_tqg; 5961 fn = _task_fn_rx; 5962 break; 5963 case IFLIB_INTR_IOV: 5964 q = ctx; 5965 gtask = &ctx->ifc_vflr_task; 5966 tqg = qgroup_if_config_tqg; 5967 fn = _task_fn_iov; 5968 break; 5969 default: 5970 panic("unknown net intr type"); 5971 } 5972 GROUPTASK_INIT(gtask, 0, fn, q); 5973 if (irq != NULL) { 5974 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 5975 q, name); 5976 if (err) 5977 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 5978 irq->ii_res, name); 5979 } else { 5980 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 5981 } 5982 } 5983 5984 void 5985 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5986 { 5987 5988 if (irq->ii_tag) 5989 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5990 5991 if (irq->ii_res) 5992 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 5993 rman_get_rid(irq->ii_res), irq->ii_res); 5994 } 5995 5996 static int 5997 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 5998 { 5999 iflib_txq_t txq = ctx->ifc_txqs; 6000 iflib_rxq_t rxq = ctx->ifc_rxqs; 6001 if_irq_t irq = &ctx->ifc_legacy_irq; 6002 iflib_filter_info_t info; 6003 device_t dev; 6004 struct grouptask *gtask; 6005 struct resource *res; 6006 struct taskqgroup *tqg; 6007 gtask_fn_t *fn; 6008 int tqrid; 6009 void *q; 6010 int err; 6011 6012 q = &ctx->ifc_rxqs[0]; 6013 info = &rxq[0].ifr_filter_info; 6014 gtask = &rxq[0].ifr_task; 6015 tqg = qgroup_if_io_tqg; 6016 tqrid = irq->ii_rid = *rid; 6017 fn = _task_fn_rx; 6018 6019 ctx->ifc_flags |= IFC_LEGACY; 6020 info->ifi_filter = filter; 6021 info->ifi_filter_arg = filter_arg; 6022 info->ifi_task = gtask; 6023 info->ifi_ctx = ctx; 6024 6025 dev = ctx->ifc_dev; 6026 /* We allocate a single interrupt resource */ 6027 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 6028 return (err); 6029 GROUPTASK_INIT(gtask, 0, fn, q); 6030 res = irq->ii_res; 6031 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6032 6033 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6034 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6035 "tx"); 6036 return (0); 6037 } 6038 6039 void 6040 iflib_led_create(if_ctx_t ctx) 6041 { 6042 6043 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6044 device_get_nameunit(ctx->ifc_dev)); 6045 } 6046 6047 void 6048 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6049 { 6050 6051 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6052 } 6053 6054 void 6055 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6056 { 6057 6058 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6059 } 6060 6061 void 6062 iflib_admin_intr_deferred(if_ctx_t ctx) 6063 { 6064 #ifdef INVARIANTS 6065 struct grouptask *gtask; 6066 6067 gtask = &ctx->ifc_admin_task; 6068 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 6069 #endif 6070 6071 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6072 } 6073 6074 void 6075 iflib_iov_intr_deferred(if_ctx_t ctx) 6076 { 6077 6078 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6079 } 6080 6081 void 6082 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 6083 { 6084 6085 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6086 name); 6087 } 6088 6089 void 6090 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6091 const char *name) 6092 { 6093 6094 GROUPTASK_INIT(gtask, 0, fn, ctx); 6095 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6096 name); 6097 } 6098 6099 void 6100 iflib_config_gtask_deinit(struct grouptask *gtask) 6101 { 6102 6103 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6104 } 6105 6106 void 6107 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6108 { 6109 if_t ifp = ctx->ifc_ifp; 6110 iflib_txq_t txq = ctx->ifc_txqs; 6111 6112 if_setbaudrate(ifp, baudrate); 6113 if (baudrate >= IF_Gbps(10)) { 6114 STATE_LOCK(ctx); 6115 ctx->ifc_flags |= IFC_PREFETCH; 6116 STATE_UNLOCK(ctx); 6117 } 6118 /* If link down, disable watchdog */ 6119 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6120 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6121 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6122 } 6123 ctx->ifc_link_state = link_state; 6124 if_link_state_change(ifp, link_state); 6125 } 6126 6127 static int 6128 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6129 { 6130 int credits; 6131 #ifdef INVARIANTS 6132 int credits_pre = txq->ift_cidx_processed; 6133 #endif 6134 6135 if (ctx->isc_txd_credits_update == NULL) 6136 return (0); 6137 6138 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6139 BUS_DMASYNC_POSTREAD); 6140 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6141 return (0); 6142 6143 txq->ift_processed += credits; 6144 txq->ift_cidx_processed += credits; 6145 6146 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6147 if (txq->ift_cidx_processed >= txq->ift_size) 6148 txq->ift_cidx_processed -= txq->ift_size; 6149 return (credits); 6150 } 6151 6152 static int 6153 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6154 { 6155 iflib_fl_t fl; 6156 u_int i; 6157 6158 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6159 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6160 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6161 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6162 budget)); 6163 } 6164 6165 void 6166 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6167 const char *description, if_int_delay_info_t info, 6168 int offset, int value) 6169 { 6170 info->iidi_ctx = ctx; 6171 info->iidi_offset = offset; 6172 info->iidi_value = value; 6173 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6174 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6175 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 6176 info, 0, iflib_sysctl_int_delay, "I", description); 6177 } 6178 6179 struct sx * 6180 iflib_ctx_lock_get(if_ctx_t ctx) 6181 { 6182 6183 return (&ctx->ifc_ctx_sx); 6184 } 6185 6186 static int 6187 iflib_msix_init(if_ctx_t ctx) 6188 { 6189 device_t dev = ctx->ifc_dev; 6190 if_shared_ctx_t sctx = ctx->ifc_sctx; 6191 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6192 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 6193 int iflib_num_tx_queues, iflib_num_rx_queues; 6194 int err, admincnt, bar; 6195 6196 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6197 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6198 6199 if (bootverbose) 6200 device_printf(dev, "msix_init qsets capped at %d\n", 6201 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6202 6203 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6204 admincnt = sctx->isc_admin_intrcnt; 6205 /* Override by tuneable */ 6206 if (scctx->isc_disable_msix) 6207 goto msi; 6208 6209 /* First try MSI-X */ 6210 if ((msgs = pci_msix_count(dev)) == 0) { 6211 if (bootverbose) 6212 device_printf(dev, "MSI-X not supported or disabled\n"); 6213 goto msi; 6214 } 6215 /* 6216 * bar == -1 => "trust me I know what I'm doing" 6217 * Some drivers are for hardware that is so shoddily 6218 * documented that no one knows which bars are which 6219 * so the developer has to map all bars. This hack 6220 * allows shoddy garbage to use MSI-X in this framework. 6221 */ 6222 if (bar != -1) { 6223 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6224 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6225 if (ctx->ifc_msix_mem == NULL) { 6226 device_printf(dev, "Unable to map MSI-X table\n"); 6227 goto msi; 6228 } 6229 } 6230 #if IFLIB_DEBUG 6231 /* use only 1 qset in debug mode */ 6232 queuemsgs = min(msgs - admincnt, 1); 6233 #else 6234 queuemsgs = msgs - admincnt; 6235 #endif 6236 #ifdef RSS 6237 queues = imin(queuemsgs, rss_getnumbuckets()); 6238 #else 6239 queues = queuemsgs; 6240 #endif 6241 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6242 if (bootverbose) 6243 device_printf(dev, 6244 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6245 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6246 #ifdef RSS 6247 /* If we're doing RSS, clamp at the number of RSS buckets */ 6248 if (queues > rss_getnumbuckets()) 6249 queues = rss_getnumbuckets(); 6250 #endif 6251 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6252 rx_queues = iflib_num_rx_queues; 6253 else 6254 rx_queues = queues; 6255 6256 if (rx_queues > scctx->isc_nrxqsets) 6257 rx_queues = scctx->isc_nrxqsets; 6258 6259 /* 6260 * We want this to be all logical CPUs by default 6261 */ 6262 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6263 tx_queues = iflib_num_tx_queues; 6264 else 6265 tx_queues = mp_ncpus; 6266 6267 if (tx_queues > scctx->isc_ntxqsets) 6268 tx_queues = scctx->isc_ntxqsets; 6269 6270 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6271 #ifdef INVARIANTS 6272 if (tx_queues != rx_queues) 6273 device_printf(dev, 6274 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6275 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6276 #endif 6277 tx_queues = min(rx_queues, tx_queues); 6278 rx_queues = min(rx_queues, tx_queues); 6279 } 6280 6281 device_printf(dev, "Using %d rx queues %d tx queues\n", 6282 rx_queues, tx_queues); 6283 6284 vectors = rx_queues + admincnt; 6285 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6286 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6287 vectors); 6288 scctx->isc_vectors = vectors; 6289 scctx->isc_nrxqsets = rx_queues; 6290 scctx->isc_ntxqsets = tx_queues; 6291 scctx->isc_intr = IFLIB_INTR_MSIX; 6292 6293 return (vectors); 6294 } else { 6295 device_printf(dev, 6296 "failed to allocate %d MSI-X vectors, err: %d - using MSI\n", 6297 vectors, err); 6298 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6299 ctx->ifc_msix_mem); 6300 ctx->ifc_msix_mem = NULL; 6301 } 6302 msi: 6303 vectors = pci_msi_count(dev); 6304 scctx->isc_nrxqsets = 1; 6305 scctx->isc_ntxqsets = 1; 6306 scctx->isc_vectors = vectors; 6307 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6308 device_printf(dev,"Using an MSI interrupt\n"); 6309 scctx->isc_intr = IFLIB_INTR_MSI; 6310 } else { 6311 scctx->isc_vectors = 1; 6312 device_printf(dev,"Using a Legacy interrupt\n"); 6313 scctx->isc_intr = IFLIB_INTR_LEGACY; 6314 } 6315 6316 return (vectors); 6317 } 6318 6319 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6320 6321 static int 6322 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6323 { 6324 int rc; 6325 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6326 struct sbuf *sb; 6327 const char *ring_state = "UNKNOWN"; 6328 6329 /* XXX needed ? */ 6330 rc = sysctl_wire_old_buffer(req, 0); 6331 MPASS(rc == 0); 6332 if (rc != 0) 6333 return (rc); 6334 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6335 MPASS(sb != NULL); 6336 if (sb == NULL) 6337 return (ENOMEM); 6338 if (state[3] <= 3) 6339 ring_state = ring_states[state[3]]; 6340 6341 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6342 state[0], state[1], state[2], ring_state); 6343 rc = sbuf_finish(sb); 6344 sbuf_delete(sb); 6345 return(rc); 6346 } 6347 6348 enum iflib_ndesc_handler { 6349 IFLIB_NTXD_HANDLER, 6350 IFLIB_NRXD_HANDLER, 6351 }; 6352 6353 static int 6354 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6355 { 6356 if_ctx_t ctx = (void *)arg1; 6357 enum iflib_ndesc_handler type = arg2; 6358 char buf[256] = {0}; 6359 qidx_t *ndesc; 6360 char *p, *next; 6361 int nqs, rc, i; 6362 6363 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 6364 6365 nqs = 8; 6366 switch(type) { 6367 case IFLIB_NTXD_HANDLER: 6368 ndesc = ctx->ifc_sysctl_ntxds; 6369 if (ctx->ifc_sctx) 6370 nqs = ctx->ifc_sctx->isc_ntxqs; 6371 break; 6372 case IFLIB_NRXD_HANDLER: 6373 ndesc = ctx->ifc_sysctl_nrxds; 6374 if (ctx->ifc_sctx) 6375 nqs = ctx->ifc_sctx->isc_nrxqs; 6376 break; 6377 default: 6378 panic("unhandled type"); 6379 } 6380 if (nqs == 0) 6381 nqs = 8; 6382 6383 for (i=0; i<8; i++) { 6384 if (i >= nqs) 6385 break; 6386 if (i) 6387 strcat(buf, ","); 6388 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6389 } 6390 6391 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6392 if (rc || req->newptr == NULL) 6393 return rc; 6394 6395 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6396 i++, p = strsep(&next, " ,")) { 6397 ndesc[i] = strtoul(p, NULL, 10); 6398 } 6399 6400 return(rc); 6401 } 6402 6403 #define NAME_BUFLEN 32 6404 static void 6405 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6406 { 6407 device_t dev = iflib_get_dev(ctx); 6408 struct sysctl_oid_list *child, *oid_list; 6409 struct sysctl_ctx_list *ctx_list; 6410 struct sysctl_oid *node; 6411 6412 ctx_list = device_get_sysctl_ctx(dev); 6413 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6414 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6415 CTLFLAG_RD, NULL, "IFLIB fields"); 6416 oid_list = SYSCTL_CHILDREN(node); 6417 6418 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6419 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6420 "driver version"); 6421 6422 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6423 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6424 "# of txqs to use, 0 => use default #"); 6425 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6426 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6427 "# of rxqs to use, 0 => use default #"); 6428 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6429 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6430 "permit #txq != #rxq"); 6431 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6432 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6433 "disable MSI-X (default 0)"); 6434 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6435 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6436 "set the rx budget"); 6437 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6438 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6439 "cause tx to abdicate instead of running to completion"); 6440 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6441 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6442 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6443 "offset to start using cores at"); 6444 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6445 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6446 "use separate cores for TX and RX"); 6447 6448 /* XXX change for per-queue sizes */ 6449 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6450 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6451 mp_ndesc_handler, "A", 6452 "list of # of tx descriptors to use, 0 = use default #"); 6453 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6454 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6455 mp_ndesc_handler, "A", 6456 "list of # of rx descriptors to use, 0 = use default #"); 6457 } 6458 6459 static void 6460 iflib_add_device_sysctl_post(if_ctx_t ctx) 6461 { 6462 if_shared_ctx_t sctx = ctx->ifc_sctx; 6463 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6464 device_t dev = iflib_get_dev(ctx); 6465 struct sysctl_oid_list *child; 6466 struct sysctl_ctx_list *ctx_list; 6467 iflib_fl_t fl; 6468 iflib_txq_t txq; 6469 iflib_rxq_t rxq; 6470 int i, j; 6471 char namebuf[NAME_BUFLEN]; 6472 char *qfmt; 6473 struct sysctl_oid *queue_node, *fl_node, *node; 6474 struct sysctl_oid_list *queue_list, *fl_list; 6475 ctx_list = device_get_sysctl_ctx(dev); 6476 6477 node = ctx->ifc_sysctl_node; 6478 child = SYSCTL_CHILDREN(node); 6479 6480 if (scctx->isc_ntxqsets > 100) 6481 qfmt = "txq%03d"; 6482 else if (scctx->isc_ntxqsets > 10) 6483 qfmt = "txq%02d"; 6484 else 6485 qfmt = "txq%d"; 6486 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6487 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6488 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6489 CTLFLAG_RD, NULL, "Queue Name"); 6490 queue_list = SYSCTL_CHILDREN(queue_node); 6491 #if MEMORY_LOGGING 6492 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6493 CTLFLAG_RD, 6494 &txq->ift_dequeued, "total mbufs freed"); 6495 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6496 CTLFLAG_RD, 6497 &txq->ift_enqueued, "total mbufs enqueued"); 6498 #endif 6499 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6500 CTLFLAG_RD, 6501 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6502 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6503 CTLFLAG_RD, 6504 &txq->ift_pullups, "# of times m_pullup was called"); 6505 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6506 CTLFLAG_RD, 6507 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6508 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6509 CTLFLAG_RD, 6510 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6511 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6512 CTLFLAG_RD, 6513 &txq->ift_map_failed, "# of times dma map failed"); 6514 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6515 CTLFLAG_RD, 6516 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6517 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6518 CTLFLAG_RD, 6519 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6520 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6521 CTLFLAG_RD, 6522 &txq->ift_pidx, 1, "Producer Index"); 6523 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6524 CTLFLAG_RD, 6525 &txq->ift_cidx, 1, "Consumer Index"); 6526 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6527 CTLFLAG_RD, 6528 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6529 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6530 CTLFLAG_RD, 6531 &txq->ift_in_use, 1, "descriptors in use"); 6532 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6533 CTLFLAG_RD, 6534 &txq->ift_processed, "descriptors procesed for clean"); 6535 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6536 CTLFLAG_RD, 6537 &txq->ift_cleaned, "total cleaned"); 6538 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6539 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6540 0, mp_ring_state_handler, "A", "soft ring state"); 6541 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6542 CTLFLAG_RD, &txq->ift_br->enqueues, 6543 "# of enqueues to the mp_ring for this queue"); 6544 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6545 CTLFLAG_RD, &txq->ift_br->drops, 6546 "# of drops in the mp_ring for this queue"); 6547 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6548 CTLFLAG_RD, &txq->ift_br->starts, 6549 "# of normal consumer starts in the mp_ring for this queue"); 6550 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6551 CTLFLAG_RD, &txq->ift_br->stalls, 6552 "# of consumer stalls in the mp_ring for this queue"); 6553 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6554 CTLFLAG_RD, &txq->ift_br->restarts, 6555 "# of consumer restarts in the mp_ring for this queue"); 6556 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6557 CTLFLAG_RD, &txq->ift_br->abdications, 6558 "# of consumer abdications in the mp_ring for this queue"); 6559 } 6560 6561 if (scctx->isc_nrxqsets > 100) 6562 qfmt = "rxq%03d"; 6563 else if (scctx->isc_nrxqsets > 10) 6564 qfmt = "rxq%02d"; 6565 else 6566 qfmt = "rxq%d"; 6567 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6568 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6569 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6570 CTLFLAG_RD, NULL, "Queue Name"); 6571 queue_list = SYSCTL_CHILDREN(queue_node); 6572 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6573 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 6574 CTLFLAG_RD, 6575 &rxq->ifr_cq_pidx, 1, "Producer Index"); 6576 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6577 CTLFLAG_RD, 6578 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6579 } 6580 6581 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6582 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6583 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6584 CTLFLAG_RD, NULL, "freelist Name"); 6585 fl_list = SYSCTL_CHILDREN(fl_node); 6586 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6587 CTLFLAG_RD, 6588 &fl->ifl_pidx, 1, "Producer Index"); 6589 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6590 CTLFLAG_RD, 6591 &fl->ifl_cidx, 1, "Consumer Index"); 6592 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6593 CTLFLAG_RD, 6594 &fl->ifl_credits, 1, "credits available"); 6595 #if MEMORY_LOGGING 6596 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6597 CTLFLAG_RD, 6598 &fl->ifl_m_enqueued, "mbufs allocated"); 6599 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6600 CTLFLAG_RD, 6601 &fl->ifl_m_dequeued, "mbufs freed"); 6602 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6603 CTLFLAG_RD, 6604 &fl->ifl_cl_enqueued, "clusters allocated"); 6605 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6606 CTLFLAG_RD, 6607 &fl->ifl_cl_dequeued, "clusters freed"); 6608 #endif 6609 6610 } 6611 } 6612 6613 } 6614 6615 void 6616 iflib_request_reset(if_ctx_t ctx) 6617 { 6618 6619 STATE_LOCK(ctx); 6620 ctx->ifc_flags |= IFC_DO_RESET; 6621 STATE_UNLOCK(ctx); 6622 } 6623 6624 #ifndef __NO_STRICT_ALIGNMENT 6625 static struct mbuf * 6626 iflib_fixup_rx(struct mbuf *m) 6627 { 6628 struct mbuf *n; 6629 6630 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6631 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6632 m->m_data += ETHER_HDR_LEN; 6633 n = m; 6634 } else { 6635 MGETHDR(n, M_NOWAIT, MT_DATA); 6636 if (n == NULL) { 6637 m_freem(m); 6638 return (NULL); 6639 } 6640 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6641 m->m_data += ETHER_HDR_LEN; 6642 m->m_len -= ETHER_HDR_LEN; 6643 n->m_len = ETHER_HDR_LEN; 6644 M_MOVE_PKTHDR(n, m); 6645 n->m_next = m; 6646 } 6647 return (n); 6648 } 6649 #endif 6650 6651 #ifdef NETDUMP 6652 static void 6653 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 6654 { 6655 if_ctx_t ctx; 6656 6657 ctx = if_getsoftc(ifp); 6658 CTX_LOCK(ctx); 6659 *nrxr = NRXQSETS(ctx); 6660 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6661 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6662 CTX_UNLOCK(ctx); 6663 } 6664 6665 static void 6666 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event) 6667 { 6668 if_ctx_t ctx; 6669 if_softc_ctx_t scctx; 6670 iflib_fl_t fl; 6671 iflib_rxq_t rxq; 6672 int i, j; 6673 6674 ctx = if_getsoftc(ifp); 6675 scctx = &ctx->ifc_softc_ctx; 6676 6677 switch (event) { 6678 case NETDUMP_START: 6679 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6680 rxq = &ctx->ifc_rxqs[i]; 6681 for (j = 0; j < rxq->ifr_nfl; j++) { 6682 fl = rxq->ifr_fl; 6683 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6684 } 6685 } 6686 iflib_no_tx_batch = 1; 6687 break; 6688 default: 6689 break; 6690 } 6691 } 6692 6693 static int 6694 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m) 6695 { 6696 if_ctx_t ctx; 6697 iflib_txq_t txq; 6698 int error; 6699 6700 ctx = if_getsoftc(ifp); 6701 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6702 IFF_DRV_RUNNING) 6703 return (EBUSY); 6704 6705 txq = &ctx->ifc_txqs[0]; 6706 error = iflib_encap(txq, &m); 6707 if (error == 0) 6708 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6709 return (error); 6710 } 6711 6712 static int 6713 iflib_netdump_poll(struct ifnet *ifp, int count) 6714 { 6715 if_ctx_t ctx; 6716 if_softc_ctx_t scctx; 6717 iflib_txq_t txq; 6718 int i; 6719 6720 ctx = if_getsoftc(ifp); 6721 scctx = &ctx->ifc_softc_ctx; 6722 6723 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6724 IFF_DRV_RUNNING) 6725 return (EBUSY); 6726 6727 txq = &ctx->ifc_txqs[0]; 6728 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6729 6730 for (i = 0; i < scctx->isc_nrxqsets; i++) 6731 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6732 return (0); 6733 } 6734 #endif /* NETDUMP */ 6735