1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_private.h> 58 #include <net/if_types.h> 59 #include <net/if_media.h> 60 #include <net/bpf.h> 61 #include <net/ethernet.h> 62 #include <net/mp_ring.h> 63 #include <net/debugnet.h> 64 #include <net/pfil.h> 65 #include <net/vnet.h> 66 67 #include <netinet/in.h> 68 #include <netinet/in_pcb.h> 69 #include <netinet/tcp_lro.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/if_ether.h> 72 #include <netinet/ip.h> 73 #include <netinet/ip6.h> 74 #include <netinet/tcp.h> 75 #include <netinet/ip_var.h> 76 #include <netinet6/ip6_var.h> 77 78 #include <machine/bus.h> 79 #include <machine/in_cksum.h> 80 81 #include <vm/vm.h> 82 #include <vm/pmap.h> 83 84 #include <dev/led/led.h> 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pci_private.h> 88 89 #include <net/iflib.h> 90 #include <net/iflib_private.h> 91 92 #include "ifdi_if.h" 93 94 #ifdef PCI_IOV 95 #include <dev/pci/pci_iov.h> 96 #endif 97 98 #include <sys/bitstring.h> 99 /* 100 * enable accounting of every mbuf as it comes in to and goes out of 101 * iflib's software descriptor references 102 */ 103 #define MEMORY_LOGGING 0 104 /* 105 * Enable mbuf vectors for compressing long mbuf chains 106 */ 107 108 /* 109 * NB: 110 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 111 * we prefetch needs to be determined by the time spent in m_free vis a vis 112 * the cost of a prefetch. This will of course vary based on the workload: 113 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 114 * is quite expensive, thus suggesting very little prefetch. 115 * - small packet forwarding which is just returning a single mbuf to 116 * UMA will typically be very fast vis a vis the cost of a memory 117 * access. 118 */ 119 120 /* 121 * File organization: 122 * - private structures 123 * - iflib private utility functions 124 * - ifnet functions 125 * - vlan registry and other exported functions 126 * - iflib public core functions 127 * 128 * 129 */ 130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 131 132 #define IFLIB_RXEOF_MORE (1U << 0) 133 #define IFLIB_RXEOF_EMPTY (2U << 0) 134 135 struct iflib_txq; 136 typedef struct iflib_txq *iflib_txq_t; 137 struct iflib_rxq; 138 typedef struct iflib_rxq *iflib_rxq_t; 139 struct iflib_fl; 140 typedef struct iflib_fl *iflib_fl_t; 141 142 struct iflib_ctx; 143 144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 145 static void iflib_timer(void *arg); 146 static void iflib_tqg_detach(if_ctx_t ctx); 147 148 typedef struct iflib_filter_info { 149 driver_filter_t *ifi_filter; 150 void *ifi_filter_arg; 151 struct grouptask *ifi_task; 152 void *ifi_ctx; 153 } *iflib_filter_info_t; 154 155 struct iflib_ctx { 156 KOBJ_FIELDS; 157 /* 158 * Pointer to hardware driver's softc 159 */ 160 void *ifc_softc; 161 device_t ifc_dev; 162 if_t ifc_ifp; 163 164 cpuset_t ifc_cpus; 165 if_shared_ctx_t ifc_sctx; 166 struct if_softc_ctx ifc_softc_ctx; 167 168 struct sx ifc_ctx_sx; 169 struct mtx ifc_state_mtx; 170 171 iflib_txq_t ifc_txqs; 172 iflib_rxq_t ifc_rxqs; 173 uint32_t ifc_if_flags; 174 uint32_t ifc_flags; 175 uint32_t ifc_max_fl_buf_size; 176 uint32_t ifc_rx_mbuf_sz; 177 178 int ifc_link_state; 179 int ifc_watchdog_events; 180 struct cdev *ifc_led_dev; 181 struct resource *ifc_msix_mem; 182 183 struct if_irq ifc_legacy_irq; 184 struct grouptask ifc_admin_task; 185 struct grouptask ifc_vflr_task; 186 struct iflib_filter_info ifc_filter_info; 187 struct ifmedia ifc_media; 188 struct ifmedia *ifc_mediap; 189 190 struct sysctl_oid *ifc_sysctl_node; 191 uint16_t ifc_sysctl_ntxqs; 192 uint16_t ifc_sysctl_nrxqs; 193 uint16_t ifc_sysctl_qs_eq_override; 194 uint16_t ifc_sysctl_rx_budget; 195 uint16_t ifc_sysctl_tx_abdicate; 196 uint16_t ifc_sysctl_core_offset; 197 #define CORE_OFFSET_UNSPECIFIED 0xffff 198 uint8_t ifc_sysctl_separate_txrx; 199 uint8_t ifc_sysctl_use_logical_cores; 200 bool ifc_cpus_are_physical_cores; 201 202 qidx_t ifc_sysctl_ntxds[8]; 203 qidx_t ifc_sysctl_nrxds[8]; 204 struct if_txrx ifc_txrx; 205 #define isc_txd_encap ifc_txrx.ift_txd_encap 206 #define isc_txd_flush ifc_txrx.ift_txd_flush 207 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 208 #define isc_rxd_available ifc_txrx.ift_rxd_available 209 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 210 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 211 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 212 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 213 #define isc_txq_select ifc_txrx.ift_txq_select 214 #define isc_txq_select_v2 ifc_txrx.ift_txq_select_v2 215 eventhandler_tag ifc_vlan_attach_event; 216 eventhandler_tag ifc_vlan_detach_event; 217 struct ether_addr ifc_mac; 218 }; 219 220 void * 221 iflib_get_softc(if_ctx_t ctx) 222 { 223 224 return (ctx->ifc_softc); 225 } 226 227 device_t 228 iflib_get_dev(if_ctx_t ctx) 229 { 230 231 return (ctx->ifc_dev); 232 } 233 234 if_t 235 iflib_get_ifp(if_ctx_t ctx) 236 { 237 238 return (ctx->ifc_ifp); 239 } 240 241 struct ifmedia * 242 iflib_get_media(if_ctx_t ctx) 243 { 244 245 return (ctx->ifc_mediap); 246 } 247 248 uint32_t 249 iflib_get_flags(if_ctx_t ctx) 250 { 251 return (ctx->ifc_flags); 252 } 253 254 void 255 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 256 { 257 258 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 259 } 260 261 if_softc_ctx_t 262 iflib_get_softc_ctx(if_ctx_t ctx) 263 { 264 265 return (&ctx->ifc_softc_ctx); 266 } 267 268 if_shared_ctx_t 269 iflib_get_sctx(if_ctx_t ctx) 270 { 271 272 return (ctx->ifc_sctx); 273 } 274 275 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 276 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 277 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 278 279 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 280 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 281 282 typedef struct iflib_sw_rx_desc_array { 283 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 284 struct mbuf **ifsd_m; /* pkthdr mbufs */ 285 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 286 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 287 } iflib_rxsd_array_t; 288 289 typedef struct iflib_sw_tx_desc_array { 290 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 291 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 292 struct mbuf **ifsd_m; /* pkthdr mbufs */ 293 } if_txsd_vec_t; 294 295 /* magic number that should be high enough for any hardware */ 296 #define IFLIB_MAX_TX_SEGS 128 297 #define IFLIB_RX_COPY_THRESH 128 298 #define IFLIB_MAX_RX_REFRESH 32 299 /* The minimum descriptors per second before we start coalescing */ 300 #define IFLIB_MIN_DESC_SEC 16384 301 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 302 #define IFLIB_QUEUE_IDLE 0 303 #define IFLIB_QUEUE_HUNG 1 304 #define IFLIB_QUEUE_WORKING 2 305 /* maximum number of txqs that can share an rx interrupt */ 306 #define IFLIB_MAX_TX_SHARED_INTR 4 307 308 /* this should really scale with ring size - this is a fairly arbitrary value */ 309 #define TX_BATCH_SIZE 32 310 311 #define IFLIB_RESTART_BUDGET 8 312 313 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 314 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 315 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 316 317 struct iflib_txq { 318 qidx_t ift_in_use; 319 qidx_t ift_cidx; 320 qidx_t ift_cidx_processed; 321 qidx_t ift_pidx; 322 uint8_t ift_gen; 323 uint8_t ift_br_offset; 324 uint16_t ift_npending; 325 uint16_t ift_db_pending; 326 uint16_t ift_rs_pending; 327 /* implicit pad */ 328 uint8_t ift_txd_size[8]; 329 uint64_t ift_processed; 330 uint64_t ift_cleaned; 331 uint64_t ift_cleaned_prev; 332 #if MEMORY_LOGGING 333 uint64_t ift_enqueued; 334 uint64_t ift_dequeued; 335 #endif 336 uint64_t ift_no_tx_dma_setup; 337 uint64_t ift_no_desc_avail; 338 uint64_t ift_mbuf_defrag_failed; 339 uint64_t ift_mbuf_defrag; 340 uint64_t ift_map_failed; 341 uint64_t ift_txd_encap_efbig; 342 uint64_t ift_pullups; 343 uint64_t ift_last_timer_tick; 344 345 struct mtx ift_mtx; 346 struct mtx ift_db_mtx; 347 348 /* constant values */ 349 if_ctx_t ift_ctx; 350 struct ifmp_ring *ift_br; 351 struct grouptask ift_task; 352 qidx_t ift_size; 353 uint16_t ift_id; 354 struct callout ift_timer; 355 #ifdef DEV_NETMAP 356 struct callout ift_netmap_timer; 357 #endif /* DEV_NETMAP */ 358 359 if_txsd_vec_t ift_sds; 360 uint8_t ift_qstatus; 361 uint8_t ift_closed; 362 uint8_t ift_update_freq; 363 struct iflib_filter_info ift_filter_info; 364 bus_dma_tag_t ift_buf_tag; 365 bus_dma_tag_t ift_tso_buf_tag; 366 iflib_dma_info_t ift_ifdi; 367 #define MTX_NAME_LEN 32 368 char ift_mtx_name[MTX_NAME_LEN]; 369 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 370 #ifdef IFLIB_DIAGNOSTICS 371 uint64_t ift_cpu_exec_count[256]; 372 #endif 373 } __aligned(CACHE_LINE_SIZE); 374 375 struct iflib_fl { 376 qidx_t ifl_cidx; 377 qidx_t ifl_pidx; 378 qidx_t ifl_credits; 379 uint8_t ifl_gen; 380 uint8_t ifl_rxd_size; 381 #if MEMORY_LOGGING 382 uint64_t ifl_m_enqueued; 383 uint64_t ifl_m_dequeued; 384 uint64_t ifl_cl_enqueued; 385 uint64_t ifl_cl_dequeued; 386 #endif 387 /* implicit pad */ 388 bitstr_t *ifl_rx_bitmap; 389 qidx_t ifl_fragidx; 390 /* constant */ 391 qidx_t ifl_size; 392 uint16_t ifl_buf_size; 393 uint16_t ifl_cltype; 394 uma_zone_t ifl_zone; 395 iflib_rxsd_array_t ifl_sds; 396 iflib_rxq_t ifl_rxq; 397 uint8_t ifl_id; 398 bus_dma_tag_t ifl_buf_tag; 399 iflib_dma_info_t ifl_ifdi; 400 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 401 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 402 } __aligned(CACHE_LINE_SIZE); 403 404 static inline qidx_t 405 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 406 { 407 qidx_t used; 408 409 if (pidx > cidx) 410 used = pidx - cidx; 411 else if (pidx < cidx) 412 used = size - cidx + pidx; 413 else if (gen == 0 && pidx == cidx) 414 used = 0; 415 else if (gen == 1 && pidx == cidx) 416 used = size; 417 else 418 panic("bad state"); 419 420 return (used); 421 } 422 423 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 424 425 #define IDXDIFF(head, tail, wrap) \ 426 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 427 428 struct iflib_rxq { 429 if_ctx_t ifr_ctx; 430 iflib_fl_t ifr_fl; 431 uint64_t ifr_rx_irq; 432 struct pfil_head *pfil; 433 /* 434 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 435 * the completion queue consumer index. Otherwise it's unused. 436 */ 437 qidx_t ifr_cq_cidx; 438 uint16_t ifr_id; 439 uint8_t ifr_nfl; 440 uint8_t ifr_ntxqirq; 441 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 442 uint8_t ifr_fl_offset; 443 struct lro_ctrl ifr_lc; 444 struct grouptask ifr_task; 445 struct callout ifr_watchdog; 446 struct iflib_filter_info ifr_filter_info; 447 iflib_dma_info_t ifr_ifdi; 448 449 /* dynamically allocate if any drivers need a value substantially larger than this */ 450 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 451 #ifdef IFLIB_DIAGNOSTICS 452 uint64_t ifr_cpu_exec_count[256]; 453 #endif 454 } __aligned(CACHE_LINE_SIZE); 455 456 typedef struct if_rxsd { 457 caddr_t *ifsd_cl; 458 iflib_fl_t ifsd_fl; 459 } *if_rxsd_t; 460 461 /* multiple of word size */ 462 #ifdef __LP64__ 463 #define PKT_INFO_SIZE 6 464 #define RXD_INFO_SIZE 5 465 #define PKT_TYPE uint64_t 466 #else 467 #define PKT_INFO_SIZE 11 468 #define RXD_INFO_SIZE 8 469 #define PKT_TYPE uint32_t 470 #endif 471 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 472 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 473 474 typedef struct if_pkt_info_pad { 475 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 476 } *if_pkt_info_pad_t; 477 typedef struct if_rxd_info_pad { 478 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 479 } *if_rxd_info_pad_t; 480 481 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 482 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 483 484 static inline void 485 pkt_info_zero(if_pkt_info_t pi) 486 { 487 if_pkt_info_pad_t pi_pad; 488 489 pi_pad = (if_pkt_info_pad_t)pi; 490 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 491 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 492 #ifndef __LP64__ 493 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 494 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 495 #endif 496 } 497 498 static device_method_t iflib_pseudo_methods[] = { 499 DEVMETHOD(device_attach, noop_attach), 500 DEVMETHOD(device_detach, iflib_pseudo_detach), 501 DEVMETHOD_END 502 }; 503 504 driver_t iflib_pseudodriver = { 505 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 506 }; 507 508 static inline void 509 rxd_info_zero(if_rxd_info_t ri) 510 { 511 if_rxd_info_pad_t ri_pad; 512 int i; 513 514 ri_pad = (if_rxd_info_pad_t)ri; 515 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 516 ri_pad->rxd_val[i] = 0; 517 ri_pad->rxd_val[i+1] = 0; 518 ri_pad->rxd_val[i+2] = 0; 519 ri_pad->rxd_val[i+3] = 0; 520 } 521 #ifdef __LP64__ 522 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 523 #endif 524 } 525 526 /* 527 * Only allow a single packet to take up most 1/nth of the tx ring 528 */ 529 #define MAX_SINGLE_PACKET_FRACTION 12 530 #define IF_BAD_DMA (bus_addr_t)-1 531 532 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 533 534 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 535 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 536 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 537 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 538 539 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 540 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 541 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 542 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 543 544 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 545 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 546 547 void 548 iflib_set_detach(if_ctx_t ctx) 549 { 550 STATE_LOCK(ctx); 551 ctx->ifc_flags |= IFC_IN_DETACH; 552 STATE_UNLOCK(ctx); 553 } 554 555 /* Our boot-time initialization hook */ 556 static int iflib_module_event_handler(module_t, int, void *); 557 558 static moduledata_t iflib_moduledata = { 559 "iflib", 560 iflib_module_event_handler, 561 NULL 562 }; 563 564 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 565 MODULE_VERSION(iflib, 1); 566 567 MODULE_DEPEND(iflib, pci, 1, 1, 1); 568 MODULE_DEPEND(iflib, ether, 1, 1, 1); 569 570 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 571 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 572 573 #ifndef IFLIB_DEBUG_COUNTERS 574 #ifdef INVARIANTS 575 #define IFLIB_DEBUG_COUNTERS 1 576 #else 577 #define IFLIB_DEBUG_COUNTERS 0 578 #endif /* !INVARIANTS */ 579 #endif 580 581 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 582 "iflib driver parameters"); 583 584 /* 585 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 586 */ 587 static int iflib_min_tx_latency = 0; 588 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 589 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 590 static int iflib_no_tx_batch = 0; 591 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 592 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 593 static int iflib_timer_default = 1000; 594 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW, 595 &iflib_timer_default, 0, "number of ticks between iflib_timer calls"); 596 597 598 #if IFLIB_DEBUG_COUNTERS 599 600 static int iflib_tx_seen; 601 static int iflib_tx_sent; 602 static int iflib_tx_encap; 603 static int iflib_rx_allocs; 604 static int iflib_fl_refills; 605 static int iflib_fl_refills_large; 606 static int iflib_tx_frees; 607 608 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 609 &iflib_tx_seen, 0, "# TX mbufs seen"); 610 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 611 &iflib_tx_sent, 0, "# TX mbufs sent"); 612 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 613 &iflib_tx_encap, 0, "# TX mbufs encapped"); 614 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 615 &iflib_tx_frees, 0, "# TX frees"); 616 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 617 &iflib_rx_allocs, 0, "# RX allocations"); 618 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 619 &iflib_fl_refills, 0, "# refills"); 620 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 621 &iflib_fl_refills_large, 0, "# large refills"); 622 623 static int iflib_txq_drain_flushing; 624 static int iflib_txq_drain_oactive; 625 static int iflib_txq_drain_notready; 626 627 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 628 &iflib_txq_drain_flushing, 0, "# drain flushes"); 629 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 630 &iflib_txq_drain_oactive, 0, "# drain oactives"); 631 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 632 &iflib_txq_drain_notready, 0, "# drain notready"); 633 634 static int iflib_encap_load_mbuf_fail; 635 static int iflib_encap_pad_mbuf_fail; 636 static int iflib_encap_txq_avail_fail; 637 static int iflib_encap_txd_encap_fail; 638 639 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 640 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 641 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 642 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 643 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 644 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 645 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 646 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 647 648 static int iflib_task_fn_rxs; 649 static int iflib_rx_intr_enables; 650 static int iflib_fast_intrs; 651 static int iflib_rx_unavail; 652 static int iflib_rx_ctx_inactive; 653 static int iflib_rx_if_input; 654 static int iflib_rxd_flush; 655 656 static int iflib_verbose_debug; 657 658 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 659 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 661 &iflib_rx_intr_enables, 0, "# RX intr enables"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 663 &iflib_fast_intrs, 0, "# fast_intr calls"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 665 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 666 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 667 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 668 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 669 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 670 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 671 &iflib_rxd_flush, 0, "# times rxd_flush called"); 672 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 673 &iflib_verbose_debug, 0, "enable verbose debugging"); 674 675 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 676 static void 677 iflib_debug_reset(void) 678 { 679 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 680 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 681 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 682 iflib_txq_drain_notready = 683 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 684 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 685 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 686 iflib_rx_unavail = 687 iflib_rx_ctx_inactive = iflib_rx_if_input = 688 iflib_rxd_flush = 0; 689 } 690 691 #else 692 #define DBG_COUNTER_INC(name) 693 static void iflib_debug_reset(void) {} 694 #endif 695 696 #define IFLIB_DEBUG 0 697 698 static void iflib_tx_structures_free(if_ctx_t ctx); 699 static void iflib_rx_structures_free(if_ctx_t ctx); 700 static int iflib_queues_alloc(if_ctx_t ctx); 701 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 702 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 703 static int iflib_qset_structures_setup(if_ctx_t ctx); 704 static int iflib_msix_init(if_ctx_t ctx); 705 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 706 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 707 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 708 #ifdef ALTQ 709 static void iflib_altq_if_start(if_t ifp); 710 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 711 #endif 712 static int iflib_register(if_ctx_t); 713 static void iflib_deregister(if_ctx_t); 714 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 715 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 716 static void iflib_init_locked(if_ctx_t ctx); 717 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 718 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 719 static void iflib_ifmp_purge(iflib_txq_t txq); 720 static void _iflib_pre_assert(if_softc_ctx_t scctx); 721 static void iflib_if_init_locked(if_ctx_t ctx); 722 static void iflib_free_intr_mem(if_ctx_t ctx); 723 #ifndef __NO_STRICT_ALIGNMENT 724 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 725 #endif 726 727 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 728 SLIST_HEAD_INITIALIZER(cpu_offsets); 729 struct cpu_offset { 730 SLIST_ENTRY(cpu_offset) entries; 731 cpuset_t set; 732 unsigned int refcount; 733 uint16_t next_cpuid; 734 }; 735 static struct mtx cpu_offset_mtx; 736 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 737 MTX_DEF); 738 739 DEBUGNET_DEFINE(iflib); 740 741 static int 742 iflib_num_rx_descs(if_ctx_t ctx) 743 { 744 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 745 if_shared_ctx_t sctx = ctx->ifc_sctx; 746 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 747 748 return scctx->isc_nrxd[first_rxq]; 749 } 750 751 static int 752 iflib_num_tx_descs(if_ctx_t ctx) 753 { 754 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 755 if_shared_ctx_t sctx = ctx->ifc_sctx; 756 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 757 758 return scctx->isc_ntxd[first_txq]; 759 } 760 761 #ifdef DEV_NETMAP 762 #include <sys/selinfo.h> 763 #include <net/netmap.h> 764 #include <dev/netmap/netmap_kern.h> 765 766 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 767 768 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 769 static void iflib_netmap_timer(void *arg); 770 771 /* 772 * device-specific sysctl variables: 773 * 774 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 775 * During regular operations the CRC is stripped, but on some 776 * hardware reception of frames not multiple of 64 is slower, 777 * so using crcstrip=0 helps in benchmarks. 778 * 779 * iflib_rx_miss, iflib_rx_miss_bufs: 780 * count packets that might be missed due to lost interrupts. 781 */ 782 SYSCTL_DECL(_dev_netmap); 783 /* 784 * The xl driver by default strips CRCs and we do not override it. 785 */ 786 787 int iflib_crcstrip = 1; 788 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 789 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 790 791 int iflib_rx_miss, iflib_rx_miss_bufs; 792 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 793 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 794 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 795 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 796 797 /* 798 * Register/unregister. We are already under netmap lock. 799 * Only called on the first register or the last unregister. 800 */ 801 static int 802 iflib_netmap_register(struct netmap_adapter *na, int onoff) 803 { 804 if_t ifp = na->ifp; 805 if_ctx_t ctx = if_getsoftc(ifp); 806 int status; 807 808 CTX_LOCK(ctx); 809 if (!CTX_IS_VF(ctx)) 810 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 811 812 iflib_stop(ctx); 813 814 /* 815 * Enable (or disable) netmap flags, and intercept (or restore) 816 * ifp->if_transmit. This is done once the device has been stopped 817 * to prevent race conditions. Also, this must be done after 818 * calling netmap_disable_all_rings() and before calling 819 * netmap_enable_all_rings(), so that these two functions see the 820 * updated state of the NAF_NETMAP_ON bit. 821 */ 822 if (onoff) { 823 nm_set_native_flags(na); 824 } else { 825 nm_clear_native_flags(na); 826 } 827 828 iflib_init_locked(ctx); 829 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 830 status = if_getdrvflags(ifp) & IFF_DRV_RUNNING ? 0 : 1; 831 if (status) 832 nm_clear_native_flags(na); 833 CTX_UNLOCK(ctx); 834 return (status); 835 } 836 837 static int 838 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info) 839 { 840 if_t ifp = na->ifp; 841 if_ctx_t ctx = if_getsoftc(ifp); 842 iflib_rxq_t rxq = &ctx->ifc_rxqs[0]; 843 iflib_fl_t fl = &rxq->ifr_fl[0]; 844 845 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 846 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 847 info->num_tx_descs = iflib_num_tx_descs(ctx); 848 info->num_rx_descs = iflib_num_rx_descs(ctx); 849 info->rx_buf_maxsize = fl->ifl_buf_size; 850 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u", 851 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs, 852 info->num_rx_descs, info->rx_buf_maxsize); 853 854 return 0; 855 } 856 857 static int 858 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 859 { 860 struct netmap_adapter *na = kring->na; 861 u_int const lim = kring->nkr_num_slots - 1; 862 struct netmap_ring *ring = kring->ring; 863 bus_dmamap_t *map; 864 struct if_rxd_update iru; 865 if_ctx_t ctx = rxq->ifr_ctx; 866 iflib_fl_t fl = &rxq->ifr_fl[0]; 867 u_int nic_i_first, nic_i; 868 u_int nm_i; 869 int i, n; 870 #if IFLIB_DEBUG_COUNTERS 871 int rf_count = 0; 872 #endif 873 874 /* 875 * This function is used both at initialization and in rxsync. 876 * At initialization we need to prepare (with isc_rxd_refill()) 877 * all the netmap buffers currently owned by the kernel, in 878 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync 879 * (except for kring->nkr_hwofs). These may be less than 880 * kring->nkr_num_slots if netmap_reset() was called while 881 * an application using the kring that still owned some 882 * buffers. 883 * At rxsync time, both indexes point to the next buffer to be 884 * refilled. 885 * In any case we publish (with isc_rxd_flush()) up to 886 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 887 * pointer to overrun the head/cons pointer, although this is 888 * not necessary for some NICs (e.g. vmx). 889 */ 890 if (__predict_false(init)) { 891 n = kring->nkr_num_slots - nm_kr_rxspace(kring); 892 } else { 893 n = kring->rhead - kring->nr_hwcur; 894 if (n == 0) 895 return (0); /* Nothing to do. */ 896 if (n < 0) 897 n += kring->nkr_num_slots; 898 } 899 900 iru_init(&iru, rxq, 0 /* flid */); 901 map = fl->ifl_sds.ifsd_map; 902 nic_i = fl->ifl_pidx; 903 nm_i = netmap_idx_n2k(kring, nic_i); 904 if (__predict_false(init)) { 905 /* 906 * On init/reset, nic_i must be 0, and we must 907 * start to refill from hwtail (see netmap_reset()). 908 */ 909 MPASS(nic_i == 0); 910 MPASS(nm_i == kring->nr_hwtail); 911 } else 912 MPASS(nm_i == kring->nr_hwcur); 913 DBG_COUNTER_INC(fl_refills); 914 while (n > 0) { 915 #if IFLIB_DEBUG_COUNTERS 916 if (++rf_count == 9) 917 DBG_COUNTER_INC(fl_refills_large); 918 #endif 919 nic_i_first = nic_i; 920 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 921 struct netmap_slot *slot = &ring->slot[nm_i]; 922 uint64_t paddr; 923 void *addr = PNMB(na, slot, &paddr); 924 925 MPASS(i < IFLIB_MAX_RX_REFRESH); 926 927 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 928 return netmap_ring_reinit(kring); 929 930 fl->ifl_bus_addrs[i] = paddr + 931 nm_get_offset(kring, slot); 932 fl->ifl_rxd_idxs[i] = nic_i; 933 934 if (__predict_false(init)) { 935 netmap_load_map(na, fl->ifl_buf_tag, 936 map[nic_i], addr); 937 } else if (slot->flags & NS_BUF_CHANGED) { 938 /* buffer has changed, reload map */ 939 netmap_reload_map(na, fl->ifl_buf_tag, 940 map[nic_i], addr); 941 } 942 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 943 BUS_DMASYNC_PREREAD); 944 slot->flags &= ~NS_BUF_CHANGED; 945 946 nm_i = nm_next(nm_i, lim); 947 nic_i = nm_next(nic_i, lim); 948 } 949 950 iru.iru_pidx = nic_i_first; 951 iru.iru_count = i; 952 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 953 } 954 fl->ifl_pidx = nic_i; 955 /* 956 * At the end of the loop we must have refilled everything 957 * we could possibly refill. 958 */ 959 MPASS(nm_i == kring->rhead); 960 kring->nr_hwcur = nm_i; 961 962 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 963 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 964 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 965 nm_prev(nic_i, lim)); 966 DBG_COUNTER_INC(rxd_flush); 967 968 return (0); 969 } 970 971 #define NETMAP_TX_TIMER_US 90 972 973 /* 974 * Reconcile kernel and user view of the transmit ring. 975 * 976 * All information is in the kring. 977 * Userspace wants to send packets up to the one before kring->rhead, 978 * kernel knows kring->nr_hwcur is the first unsent packet. 979 * 980 * Here we push packets out (as many as possible), and possibly 981 * reclaim buffers from previously completed transmission. 982 * 983 * The caller (netmap) guarantees that there is only one instance 984 * running at any time. Any interference with other driver 985 * methods should be handled by the individual drivers. 986 */ 987 static int 988 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 989 { 990 struct netmap_adapter *na = kring->na; 991 if_t ifp = na->ifp; 992 struct netmap_ring *ring = kring->ring; 993 u_int nm_i; /* index into the netmap kring */ 994 u_int nic_i; /* index into the NIC ring */ 995 u_int const lim = kring->nkr_num_slots - 1; 996 u_int const head = kring->rhead; 997 struct if_pkt_info pi; 998 int tx_pkts = 0, tx_bytes = 0; 999 1000 /* 1001 * interrupts on every tx packet are expensive so request 1002 * them every half ring, or where NS_REPORT is set 1003 */ 1004 u_int report_frequency = kring->nkr_num_slots >> 1; 1005 /* device-specific */ 1006 if_ctx_t ctx = if_getsoftc(ifp); 1007 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 1008 1009 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1010 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1011 1012 /* 1013 * First part: process new packets to send. 1014 * nm_i is the current index in the netmap kring, 1015 * nic_i is the corresponding index in the NIC ring. 1016 * 1017 * If we have packets to send (nm_i != head) 1018 * iterate over the netmap ring, fetch length and update 1019 * the corresponding slot in the NIC ring. Some drivers also 1020 * need to update the buffer's physical address in the NIC slot 1021 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 1022 * 1023 * The netmap_reload_map() calls is especially expensive, 1024 * even when (as in this case) the tag is 0, so do only 1025 * when the buffer has actually changed. 1026 * 1027 * If possible do not set the report/intr bit on all slots, 1028 * but only a few times per ring or when NS_REPORT is set. 1029 * 1030 * Finally, on 10G and faster drivers, it might be useful 1031 * to prefetch the next slot and txr entry. 1032 */ 1033 1034 nm_i = kring->nr_hwcur; 1035 if (nm_i != head) { /* we have new packets to send */ 1036 uint32_t pkt_len = 0, seg_idx = 0; 1037 int nic_i_start = -1, flags = 0; 1038 pkt_info_zero(&pi); 1039 pi.ipi_segs = txq->ift_segs; 1040 pi.ipi_qsidx = kring->ring_id; 1041 nic_i = netmap_idx_k2n(kring, nm_i); 1042 1043 __builtin_prefetch(&ring->slot[nm_i]); 1044 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 1045 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 1046 1047 while (nm_i != head) { 1048 struct netmap_slot *slot = &ring->slot[nm_i]; 1049 uint64_t offset = nm_get_offset(kring, slot); 1050 u_int len = slot->len; 1051 uint64_t paddr; 1052 void *addr = PNMB(na, slot, &paddr); 1053 1054 flags |= (slot->flags & NS_REPORT || 1055 nic_i == 0 || nic_i == report_frequency) ? 1056 IPI_TX_INTR : 0; 1057 1058 /* 1059 * If this is the first packet fragment, save the 1060 * index of the first NIC slot for later. 1061 */ 1062 if (nic_i_start < 0) 1063 nic_i_start = nic_i; 1064 1065 pi.ipi_segs[seg_idx].ds_addr = paddr + offset; 1066 pi.ipi_segs[seg_idx].ds_len = len; 1067 if (len) { 1068 pkt_len += len; 1069 seg_idx++; 1070 } 1071 1072 if (!(slot->flags & NS_MOREFRAG)) { 1073 pi.ipi_len = pkt_len; 1074 pi.ipi_nsegs = seg_idx; 1075 pi.ipi_pidx = nic_i_start; 1076 pi.ipi_ndescs = 0; 1077 pi.ipi_flags = flags; 1078 1079 /* Prepare the NIC TX ring. */ 1080 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1081 DBG_COUNTER_INC(tx_encap); 1082 1083 /* Update transmit counters */ 1084 tx_bytes += pi.ipi_len; 1085 tx_pkts++; 1086 1087 /* Reinit per-packet info for the next one. */ 1088 flags = seg_idx = pkt_len = 0; 1089 nic_i_start = -1; 1090 } 1091 1092 /* prefetch for next round */ 1093 __builtin_prefetch(&ring->slot[nm_i + 1]); 1094 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1095 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1096 1097 NM_CHECK_ADDR_LEN_OFF(na, len, offset); 1098 1099 if (slot->flags & NS_BUF_CHANGED) { 1100 /* buffer has changed, reload map */ 1101 netmap_reload_map(na, txq->ift_buf_tag, 1102 txq->ift_sds.ifsd_map[nic_i], addr); 1103 } 1104 /* make sure changes to the buffer are synced */ 1105 bus_dmamap_sync(txq->ift_buf_tag, 1106 txq->ift_sds.ifsd_map[nic_i], 1107 BUS_DMASYNC_PREWRITE); 1108 1109 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG); 1110 nm_i = nm_next(nm_i, lim); 1111 nic_i = nm_next(nic_i, lim); 1112 } 1113 kring->nr_hwcur = nm_i; 1114 1115 /* synchronize the NIC ring */ 1116 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1117 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1118 1119 /* (re)start the tx unit up to slot nic_i (excluded) */ 1120 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1121 } 1122 1123 /* 1124 * Second part: reclaim buffers for completed transmissions. 1125 * 1126 * If there are unclaimed buffers, attempt to reclaim them. 1127 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1128 * trigger a per-tx-queue timer to try again later. 1129 */ 1130 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1131 if (iflib_tx_credits_update(ctx, txq)) { 1132 /* some tx completed, increment avail */ 1133 nic_i = txq->ift_cidx_processed; 1134 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1135 } 1136 } 1137 1138 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1139 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1140 callout_reset_sbt_on(&txq->ift_netmap_timer, 1141 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1142 iflib_netmap_timer, txq, 1143 txq->ift_netmap_timer.c_cpu, 0); 1144 } 1145 1146 if_inc_counter(ifp, IFCOUNTER_OBYTES, tx_bytes); 1147 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tx_pkts); 1148 1149 return (0); 1150 } 1151 1152 /* 1153 * Reconcile kernel and user view of the receive ring. 1154 * Same as for the txsync, this routine must be efficient. 1155 * The caller guarantees a single invocations, but races against 1156 * the rest of the driver should be handled here. 1157 * 1158 * On call, kring->rhead is the first packet that userspace wants 1159 * to keep, and kring->rcur is the wakeup point. 1160 * The kernel has previously reported packets up to kring->rtail. 1161 * 1162 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1163 * of whether or not we received an interrupt. 1164 */ 1165 static int 1166 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1167 { 1168 struct netmap_adapter *na = kring->na; 1169 struct netmap_ring *ring = kring->ring; 1170 if_t ifp = na->ifp; 1171 uint32_t nm_i; /* index into the netmap ring */ 1172 uint32_t nic_i; /* index into the NIC ring */ 1173 u_int n; 1174 u_int const lim = kring->nkr_num_slots - 1; 1175 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1176 int i = 0, rx_bytes = 0, rx_pkts = 0; 1177 1178 if_ctx_t ctx = if_getsoftc(ifp); 1179 if_shared_ctx_t sctx = ctx->ifc_sctx; 1180 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1181 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1182 iflib_fl_t fl = &rxq->ifr_fl[0]; 1183 struct if_rxd_info ri; 1184 qidx_t *cidxp; 1185 1186 /* 1187 * netmap only uses free list 0, to avoid out of order consumption 1188 * of receive buffers 1189 */ 1190 1191 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1192 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1193 1194 /* 1195 * First part: import newly received packets. 1196 * 1197 * nm_i is the index of the next free slot in the netmap ring, 1198 * nic_i is the index of the next received packet in the NIC ring 1199 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1200 * differ in case if_init() has been called while 1201 * in netmap mode. For the receive ring we have 1202 * 1203 * nic_i = fl->ifl_cidx; 1204 * nm_i = kring->nr_hwtail (previous) 1205 * and 1206 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1207 * 1208 * fl->ifl_cidx is set to 0 on a ring reinit 1209 */ 1210 if (netmap_no_pendintr || force_update) { 1211 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1212 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1213 int crclen = iflib_crcstrip ? 0 : 4; 1214 int error, avail; 1215 1216 /* 1217 * For the free list consumer index, we use the same 1218 * logic as in iflib_rxeof(). 1219 */ 1220 if (have_rxcq) 1221 cidxp = &rxq->ifr_cq_cidx; 1222 else 1223 cidxp = &fl->ifl_cidx; 1224 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1225 rxq->ifr_id, *cidxp, USHRT_MAX); 1226 1227 nic_i = fl->ifl_cidx; 1228 nm_i = netmap_idx_n2k(kring, nic_i); 1229 MPASS(nm_i == kring->nr_hwtail); 1230 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1231 rxd_info_zero(&ri); 1232 ri.iri_frags = rxq->ifr_frags; 1233 ri.iri_qsidx = kring->ring_id; 1234 ri.iri_ifp = ctx->ifc_ifp; 1235 ri.iri_cidx = *cidxp; 1236 1237 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1238 for (i = 0; i < ri.iri_nfrags; i++) { 1239 if (error) { 1240 ring->slot[nm_i].len = 0; 1241 ring->slot[nm_i].flags = 0; 1242 } else { 1243 ring->slot[nm_i].len = ri.iri_frags[i].irf_len; 1244 if (i == (ri.iri_nfrags - 1)) { 1245 ring->slot[nm_i].len -= crclen; 1246 ring->slot[nm_i].flags = 0; 1247 1248 /* Update receive counters */ 1249 rx_bytes += ri.iri_len; 1250 rx_pkts++; 1251 } else 1252 ring->slot[nm_i].flags = NS_MOREFRAG; 1253 } 1254 1255 bus_dmamap_sync(fl->ifl_buf_tag, 1256 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1257 nm_i = nm_next(nm_i, lim); 1258 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1259 } 1260 1261 if (have_rxcq) { 1262 *cidxp = ri.iri_cidx; 1263 while (*cidxp >= scctx->isc_nrxd[0]) 1264 *cidxp -= scctx->isc_nrxd[0]; 1265 } 1266 1267 } 1268 if (n) { /* update the state variables */ 1269 if (netmap_no_pendintr && !force_update) { 1270 /* diagnostics */ 1271 iflib_rx_miss ++; 1272 iflib_rx_miss_bufs += n; 1273 } 1274 kring->nr_hwtail = nm_i; 1275 } 1276 kring->nr_kflags &= ~NKR_PENDINTR; 1277 } 1278 /* 1279 * Second part: skip past packets that userspace has released. 1280 * (kring->nr_hwcur to head excluded), 1281 * and make the buffers available for reception. 1282 * As usual nm_i is the index in the netmap ring, 1283 * nic_i is the index in the NIC ring, and 1284 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1285 */ 1286 netmap_fl_refill(rxq, kring, false); 1287 1288 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 1289 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 1290 1291 return (0); 1292 } 1293 1294 static void 1295 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1296 { 1297 if_ctx_t ctx = if_getsoftc(na->ifp); 1298 1299 CTX_LOCK(ctx); 1300 if (onoff) { 1301 IFDI_INTR_ENABLE(ctx); 1302 } else { 1303 IFDI_INTR_DISABLE(ctx); 1304 } 1305 CTX_UNLOCK(ctx); 1306 } 1307 1308 static int 1309 iflib_netmap_attach(if_ctx_t ctx) 1310 { 1311 struct netmap_adapter na; 1312 1313 bzero(&na, sizeof(na)); 1314 1315 na.ifp = ctx->ifc_ifp; 1316 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS; 1317 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1318 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1319 1320 na.num_tx_desc = iflib_num_tx_descs(ctx); 1321 na.num_rx_desc = iflib_num_rx_descs(ctx); 1322 na.nm_txsync = iflib_netmap_txsync; 1323 na.nm_rxsync = iflib_netmap_rxsync; 1324 na.nm_register = iflib_netmap_register; 1325 na.nm_intr = iflib_netmap_intr; 1326 na.nm_config = iflib_netmap_config; 1327 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1328 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1329 return (netmap_attach(&na)); 1330 } 1331 1332 static int 1333 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1334 { 1335 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1336 struct netmap_slot *slot; 1337 1338 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1339 if (slot == NULL) 1340 return (0); 1341 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1342 /* 1343 * In netmap mode, set the map for the packet buffer. 1344 * NOTE: Some drivers (not this one) also need to set 1345 * the physical buffer address in the NIC ring. 1346 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1347 * netmap slot index, si 1348 */ 1349 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1350 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1351 NMB(na, slot + si)); 1352 } 1353 return (1); 1354 } 1355 1356 static int 1357 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1358 { 1359 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1360 struct netmap_kring *kring; 1361 struct netmap_slot *slot; 1362 1363 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1364 if (slot == NULL) 1365 return (0); 1366 kring = na->rx_rings[rxq->ifr_id]; 1367 netmap_fl_refill(rxq, kring, true); 1368 return (1); 1369 } 1370 1371 static void 1372 iflib_netmap_timer(void *arg) 1373 { 1374 iflib_txq_t txq = arg; 1375 if_ctx_t ctx = txq->ift_ctx; 1376 1377 /* 1378 * Wake up the netmap application, to give it a chance to 1379 * call txsync and reclaim more completed TX buffers. 1380 */ 1381 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1382 } 1383 1384 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1385 1386 #else 1387 #define iflib_netmap_txq_init(ctx, txq) (0) 1388 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1389 #define iflib_netmap_detach(ifp) 1390 #define netmap_enable_all_rings(ifp) 1391 #define netmap_disable_all_rings(ifp) 1392 1393 #define iflib_netmap_attach(ctx) (0) 1394 #define netmap_rx_irq(ifp, qid, budget) (0) 1395 #endif 1396 1397 #if defined(__i386__) || defined(__amd64__) 1398 static __inline void 1399 prefetch(void *x) 1400 { 1401 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1402 } 1403 1404 static __inline void 1405 prefetch2cachelines(void *x) 1406 { 1407 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1408 #if (CACHE_LINE_SIZE < 128) 1409 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1410 #endif 1411 } 1412 #else 1413 static __inline void 1414 prefetch(void *x) 1415 { 1416 } 1417 1418 static __inline void 1419 prefetch2cachelines(void *x) 1420 { 1421 } 1422 #endif 1423 1424 static void 1425 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1426 { 1427 iflib_fl_t fl; 1428 1429 fl = &rxq->ifr_fl[flid]; 1430 iru->iru_paddrs = fl->ifl_bus_addrs; 1431 iru->iru_idxs = fl->ifl_rxd_idxs; 1432 iru->iru_qsidx = rxq->ifr_id; 1433 iru->iru_buf_size = fl->ifl_buf_size; 1434 iru->iru_flidx = fl->ifl_id; 1435 } 1436 1437 static void 1438 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1439 { 1440 if (err) 1441 return; 1442 *(bus_addr_t *) arg = segs[0].ds_addr; 1443 } 1444 1445 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \ 1446 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \ 1447 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL) 1448 1449 int 1450 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1451 { 1452 int err; 1453 device_t dev = ctx->ifc_dev; 1454 bus_addr_t lowaddr; 1455 1456 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width); 1457 1458 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1459 align, 0, /* alignment, bounds */ 1460 lowaddr, /* lowaddr */ 1461 BUS_SPACE_MAXADDR, /* highaddr */ 1462 NULL, NULL, /* filter, filterarg */ 1463 size, /* maxsize */ 1464 1, /* nsegments */ 1465 size, /* maxsegsize */ 1466 BUS_DMA_ALLOCNOW, /* flags */ 1467 NULL, /* lockfunc */ 1468 NULL, /* lockarg */ 1469 &dma->idi_tag); 1470 if (err) { 1471 device_printf(dev, 1472 "%s: bus_dma_tag_create failed: %d\n", 1473 __func__, err); 1474 goto fail_0; 1475 } 1476 1477 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1478 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1479 if (err) { 1480 device_printf(dev, 1481 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1482 __func__, (uintmax_t)size, err); 1483 goto fail_1; 1484 } 1485 1486 dma->idi_paddr = IF_BAD_DMA; 1487 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1488 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1489 if (err || dma->idi_paddr == IF_BAD_DMA) { 1490 device_printf(dev, 1491 "%s: bus_dmamap_load failed: %d\n", 1492 __func__, err); 1493 goto fail_2; 1494 } 1495 1496 dma->idi_size = size; 1497 return (0); 1498 1499 fail_2: 1500 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1501 fail_1: 1502 bus_dma_tag_destroy(dma->idi_tag); 1503 fail_0: 1504 dma->idi_tag = NULL; 1505 1506 return (err); 1507 } 1508 1509 int 1510 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1511 { 1512 if_shared_ctx_t sctx = ctx->ifc_sctx; 1513 1514 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1515 1516 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1517 } 1518 1519 int 1520 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1521 { 1522 int i, err; 1523 iflib_dma_info_t *dmaiter; 1524 1525 dmaiter = dmalist; 1526 for (i = 0; i < count; i++, dmaiter++) { 1527 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1528 break; 1529 } 1530 if (err) 1531 iflib_dma_free_multi(dmalist, i); 1532 return (err); 1533 } 1534 1535 void 1536 iflib_dma_free(iflib_dma_info_t dma) 1537 { 1538 if (dma->idi_tag == NULL) 1539 return; 1540 if (dma->idi_paddr != IF_BAD_DMA) { 1541 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1542 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1543 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1544 dma->idi_paddr = IF_BAD_DMA; 1545 } 1546 if (dma->idi_vaddr != NULL) { 1547 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1548 dma->idi_vaddr = NULL; 1549 } 1550 bus_dma_tag_destroy(dma->idi_tag); 1551 dma->idi_tag = NULL; 1552 } 1553 1554 void 1555 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1556 { 1557 int i; 1558 iflib_dma_info_t *dmaiter = dmalist; 1559 1560 for (i = 0; i < count; i++, dmaiter++) 1561 iflib_dma_free(*dmaiter); 1562 } 1563 1564 static int 1565 iflib_fast_intr(void *arg) 1566 { 1567 iflib_filter_info_t info = arg; 1568 struct grouptask *gtask = info->ifi_task; 1569 int result; 1570 1571 DBG_COUNTER_INC(fast_intrs); 1572 if (info->ifi_filter != NULL) { 1573 result = info->ifi_filter(info->ifi_filter_arg); 1574 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1575 return (result); 1576 } 1577 1578 GROUPTASK_ENQUEUE(gtask); 1579 return (FILTER_HANDLED); 1580 } 1581 1582 static int 1583 iflib_fast_intr_rxtx(void *arg) 1584 { 1585 iflib_filter_info_t info = arg; 1586 struct grouptask *gtask = info->ifi_task; 1587 if_ctx_t ctx; 1588 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1589 iflib_txq_t txq; 1590 void *sc; 1591 int i, cidx, result; 1592 qidx_t txqid; 1593 bool intr_enable, intr_legacy; 1594 1595 DBG_COUNTER_INC(fast_intrs); 1596 if (info->ifi_filter != NULL) { 1597 result = info->ifi_filter(info->ifi_filter_arg); 1598 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1599 return (result); 1600 } 1601 1602 ctx = rxq->ifr_ctx; 1603 sc = ctx->ifc_softc; 1604 intr_enable = false; 1605 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1606 MPASS(rxq->ifr_ntxqirq); 1607 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1608 txqid = rxq->ifr_txqid[i]; 1609 txq = &ctx->ifc_txqs[txqid]; 1610 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1611 BUS_DMASYNC_POSTREAD); 1612 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1613 if (intr_legacy) 1614 intr_enable = true; 1615 else 1616 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1617 continue; 1618 } 1619 GROUPTASK_ENQUEUE(&txq->ift_task); 1620 } 1621 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1622 cidx = rxq->ifr_cq_cidx; 1623 else 1624 cidx = rxq->ifr_fl[0].ifl_cidx; 1625 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1626 GROUPTASK_ENQUEUE(gtask); 1627 else { 1628 if (intr_legacy) 1629 intr_enable = true; 1630 else 1631 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1632 DBG_COUNTER_INC(rx_intr_enables); 1633 } 1634 if (intr_enable) 1635 IFDI_INTR_ENABLE(ctx); 1636 return (FILTER_HANDLED); 1637 } 1638 1639 static int 1640 iflib_fast_intr_ctx(void *arg) 1641 { 1642 iflib_filter_info_t info = arg; 1643 struct grouptask *gtask = info->ifi_task; 1644 int result; 1645 1646 DBG_COUNTER_INC(fast_intrs); 1647 if (info->ifi_filter != NULL) { 1648 result = info->ifi_filter(info->ifi_filter_arg); 1649 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1650 return (result); 1651 } 1652 1653 if (gtask->gt_taskqueue != NULL) 1654 GROUPTASK_ENQUEUE(gtask); 1655 return (FILTER_HANDLED); 1656 } 1657 1658 static int 1659 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1660 driver_filter_t filter, driver_intr_t handler, void *arg, 1661 const char *name) 1662 { 1663 struct resource *res; 1664 void *tag = NULL; 1665 device_t dev = ctx->ifc_dev; 1666 int flags, i, rc; 1667 1668 flags = RF_ACTIVE; 1669 if (ctx->ifc_flags & IFC_LEGACY) 1670 flags |= RF_SHAREABLE; 1671 MPASS(rid < 512); 1672 i = rid; 1673 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1674 if (res == NULL) { 1675 device_printf(dev, 1676 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1677 return (ENOMEM); 1678 } 1679 irq->ii_res = res; 1680 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1681 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1682 filter, handler, arg, &tag); 1683 if (rc != 0) { 1684 device_printf(dev, 1685 "failed to setup interrupt for rid %d, name %s: %d\n", 1686 rid, name ? name : "unknown", rc); 1687 return (rc); 1688 } else if (name) 1689 bus_describe_intr(dev, res, tag, "%s", name); 1690 1691 irq->ii_tag = tag; 1692 return (0); 1693 } 1694 1695 /********************************************************************* 1696 * 1697 * Allocate DMA resources for TX buffers as well as memory for the TX 1698 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1699 * iflib_sw_tx_desc_array structure, storing all the information that 1700 * is needed to transmit a packet on the wire. This is called only 1701 * once at attach, setup is done every reset. 1702 * 1703 **********************************************************************/ 1704 static int 1705 iflib_txsd_alloc(iflib_txq_t txq) 1706 { 1707 if_ctx_t ctx = txq->ift_ctx; 1708 if_shared_ctx_t sctx = ctx->ifc_sctx; 1709 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1710 device_t dev = ctx->ifc_dev; 1711 bus_size_t tsomaxsize; 1712 bus_addr_t lowaddr; 1713 int err, nsegments, ntsosegments; 1714 bool tso; 1715 1716 nsegments = scctx->isc_tx_nsegments; 1717 ntsosegments = scctx->isc_tx_tso_segments_max; 1718 tsomaxsize = scctx->isc_tx_tso_size_max; 1719 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1720 tsomaxsize += sizeof(struct ether_vlan_header); 1721 MPASS(scctx->isc_ntxd[0] > 0); 1722 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1723 MPASS(nsegments > 0); 1724 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1725 MPASS(ntsosegments > 0); 1726 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1727 } 1728 1729 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1730 1731 /* 1732 * Set up DMA tags for TX buffers. 1733 */ 1734 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1735 1, 0, /* alignment, bounds */ 1736 lowaddr, /* lowaddr */ 1737 BUS_SPACE_MAXADDR, /* highaddr */ 1738 NULL, NULL, /* filter, filterarg */ 1739 sctx->isc_tx_maxsize, /* maxsize */ 1740 nsegments, /* nsegments */ 1741 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1742 0, /* flags */ 1743 NULL, /* lockfunc */ 1744 NULL, /* lockfuncarg */ 1745 &txq->ift_buf_tag))) { 1746 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1747 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1748 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1749 goto fail; 1750 } 1751 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1752 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1753 1, 0, /* alignment, bounds */ 1754 lowaddr, /* lowaddr */ 1755 BUS_SPACE_MAXADDR, /* highaddr */ 1756 NULL, NULL, /* filter, filterarg */ 1757 tsomaxsize, /* maxsize */ 1758 ntsosegments, /* nsegments */ 1759 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1760 0, /* flags */ 1761 NULL, /* lockfunc */ 1762 NULL, /* lockfuncarg */ 1763 &txq->ift_tso_buf_tag))) { 1764 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1765 err); 1766 goto fail; 1767 } 1768 1769 /* Allocate memory for the TX mbuf map. */ 1770 if (!(txq->ift_sds.ifsd_m = 1771 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1772 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1773 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1774 err = ENOMEM; 1775 goto fail; 1776 } 1777 1778 /* 1779 * Create the DMA maps for TX buffers. 1780 */ 1781 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1782 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1783 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1784 device_printf(dev, 1785 "Unable to allocate TX buffer DMA map memory\n"); 1786 err = ENOMEM; 1787 goto fail; 1788 } 1789 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1790 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1791 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1792 device_printf(dev, 1793 "Unable to allocate TSO TX buffer map memory\n"); 1794 err = ENOMEM; 1795 goto fail; 1796 } 1797 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1798 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1799 &txq->ift_sds.ifsd_map[i]); 1800 if (err != 0) { 1801 device_printf(dev, "Unable to create TX DMA map\n"); 1802 goto fail; 1803 } 1804 if (!tso) 1805 continue; 1806 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1807 &txq->ift_sds.ifsd_tso_map[i]); 1808 if (err != 0) { 1809 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1810 goto fail; 1811 } 1812 } 1813 return (0); 1814 fail: 1815 /* We free all, it handles case where we are in the middle */ 1816 iflib_tx_structures_free(ctx); 1817 return (err); 1818 } 1819 1820 static void 1821 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1822 { 1823 bus_dmamap_t map; 1824 1825 if (txq->ift_sds.ifsd_map != NULL) { 1826 map = txq->ift_sds.ifsd_map[i]; 1827 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1828 bus_dmamap_unload(txq->ift_buf_tag, map); 1829 bus_dmamap_destroy(txq->ift_buf_tag, map); 1830 txq->ift_sds.ifsd_map[i] = NULL; 1831 } 1832 1833 if (txq->ift_sds.ifsd_tso_map != NULL) { 1834 map = txq->ift_sds.ifsd_tso_map[i]; 1835 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1836 BUS_DMASYNC_POSTWRITE); 1837 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1838 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1839 txq->ift_sds.ifsd_tso_map[i] = NULL; 1840 } 1841 } 1842 1843 static void 1844 iflib_txq_destroy(iflib_txq_t txq) 1845 { 1846 if_ctx_t ctx = txq->ift_ctx; 1847 1848 for (int i = 0; i < txq->ift_size; i++) 1849 iflib_txsd_destroy(ctx, txq, i); 1850 1851 if (txq->ift_br != NULL) { 1852 ifmp_ring_free(txq->ift_br); 1853 txq->ift_br = NULL; 1854 } 1855 1856 mtx_destroy(&txq->ift_mtx); 1857 1858 if (txq->ift_sds.ifsd_map != NULL) { 1859 free(txq->ift_sds.ifsd_map, M_IFLIB); 1860 txq->ift_sds.ifsd_map = NULL; 1861 } 1862 if (txq->ift_sds.ifsd_tso_map != NULL) { 1863 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1864 txq->ift_sds.ifsd_tso_map = NULL; 1865 } 1866 if (txq->ift_sds.ifsd_m != NULL) { 1867 free(txq->ift_sds.ifsd_m, M_IFLIB); 1868 txq->ift_sds.ifsd_m = NULL; 1869 } 1870 if (txq->ift_buf_tag != NULL) { 1871 bus_dma_tag_destroy(txq->ift_buf_tag); 1872 txq->ift_buf_tag = NULL; 1873 } 1874 if (txq->ift_tso_buf_tag != NULL) { 1875 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1876 txq->ift_tso_buf_tag = NULL; 1877 } 1878 if (txq->ift_ifdi != NULL) { 1879 free(txq->ift_ifdi, M_IFLIB); 1880 } 1881 } 1882 1883 static void 1884 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1885 { 1886 struct mbuf **mp; 1887 1888 mp = &txq->ift_sds.ifsd_m[i]; 1889 if (*mp == NULL) 1890 return; 1891 1892 if (txq->ift_sds.ifsd_map != NULL) { 1893 bus_dmamap_sync(txq->ift_buf_tag, 1894 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1895 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1896 } 1897 if (txq->ift_sds.ifsd_tso_map != NULL) { 1898 bus_dmamap_sync(txq->ift_tso_buf_tag, 1899 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1900 bus_dmamap_unload(txq->ift_tso_buf_tag, 1901 txq->ift_sds.ifsd_tso_map[i]); 1902 } 1903 m_freem(*mp); 1904 DBG_COUNTER_INC(tx_frees); 1905 *mp = NULL; 1906 } 1907 1908 static int 1909 iflib_txq_setup(iflib_txq_t txq) 1910 { 1911 if_ctx_t ctx = txq->ift_ctx; 1912 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1913 if_shared_ctx_t sctx = ctx->ifc_sctx; 1914 iflib_dma_info_t di; 1915 int i; 1916 1917 /* Set number of descriptors available */ 1918 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1919 /* XXX make configurable */ 1920 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1921 1922 /* Reset indices */ 1923 txq->ift_cidx_processed = 0; 1924 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1925 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1926 1927 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1928 bzero((void *)di->idi_vaddr, di->idi_size); 1929 1930 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1931 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1932 bus_dmamap_sync(di->idi_tag, di->idi_map, 1933 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1934 return (0); 1935 } 1936 1937 /********************************************************************* 1938 * 1939 * Allocate DMA resources for RX buffers as well as memory for the RX 1940 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1941 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1942 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1943 * Since we use use one entry in iflib_sw_rx_desc_array per received 1944 * packet, the maximum number of entries we'll need is equal to the 1945 * number of hardware receive descriptors that we've allocated. 1946 * 1947 **********************************************************************/ 1948 static int 1949 iflib_rxsd_alloc(iflib_rxq_t rxq) 1950 { 1951 if_ctx_t ctx = rxq->ifr_ctx; 1952 if_shared_ctx_t sctx = ctx->ifc_sctx; 1953 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1954 device_t dev = ctx->ifc_dev; 1955 iflib_fl_t fl; 1956 bus_addr_t lowaddr; 1957 int err; 1958 1959 MPASS(scctx->isc_nrxd[0] > 0); 1960 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1961 1962 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1963 1964 fl = rxq->ifr_fl; 1965 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1966 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1967 /* Set up DMA tag for RX buffers. */ 1968 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1969 1, 0, /* alignment, bounds */ 1970 lowaddr, /* lowaddr */ 1971 BUS_SPACE_MAXADDR, /* highaddr */ 1972 NULL, NULL, /* filter, filterarg */ 1973 sctx->isc_rx_maxsize, /* maxsize */ 1974 sctx->isc_rx_nsegments, /* nsegments */ 1975 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1976 0, /* flags */ 1977 NULL, /* lockfunc */ 1978 NULL, /* lockarg */ 1979 &fl->ifl_buf_tag); 1980 if (err) { 1981 device_printf(dev, 1982 "Unable to allocate RX DMA tag: %d\n", err); 1983 goto fail; 1984 } 1985 1986 /* Allocate memory for the RX mbuf map. */ 1987 if (!(fl->ifl_sds.ifsd_m = 1988 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1989 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1990 device_printf(dev, 1991 "Unable to allocate RX mbuf map memory\n"); 1992 err = ENOMEM; 1993 goto fail; 1994 } 1995 1996 /* Allocate memory for the direct RX cluster pointer map. */ 1997 if (!(fl->ifl_sds.ifsd_cl = 1998 (caddr_t *) malloc(sizeof(caddr_t) * 1999 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2000 device_printf(dev, 2001 "Unable to allocate RX cluster map memory\n"); 2002 err = ENOMEM; 2003 goto fail; 2004 } 2005 2006 /* Allocate memory for the RX cluster bus address map. */ 2007 if (!(fl->ifl_sds.ifsd_ba = 2008 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 2009 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2010 device_printf(dev, 2011 "Unable to allocate RX bus address map memory\n"); 2012 err = ENOMEM; 2013 goto fail; 2014 } 2015 2016 /* 2017 * Create the DMA maps for RX buffers. 2018 */ 2019 if (!(fl->ifl_sds.ifsd_map = 2020 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2021 device_printf(dev, 2022 "Unable to allocate RX buffer DMA map memory\n"); 2023 err = ENOMEM; 2024 goto fail; 2025 } 2026 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 2027 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 2028 &fl->ifl_sds.ifsd_map[i]); 2029 if (err != 0) { 2030 device_printf(dev, "Unable to create RX buffer DMA map\n"); 2031 goto fail; 2032 } 2033 } 2034 } 2035 return (0); 2036 2037 fail: 2038 iflib_rx_structures_free(ctx); 2039 return (err); 2040 } 2041 2042 /* 2043 * Internal service routines 2044 */ 2045 2046 struct rxq_refill_cb_arg { 2047 int error; 2048 bus_dma_segment_t seg; 2049 int nseg; 2050 }; 2051 2052 static void 2053 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2054 { 2055 struct rxq_refill_cb_arg *cb_arg = arg; 2056 2057 cb_arg->error = error; 2058 cb_arg->seg = segs[0]; 2059 cb_arg->nseg = nseg; 2060 } 2061 2062 /** 2063 * iflib_fl_refill - refill an rxq free-buffer list 2064 * @ctx: the iflib context 2065 * @fl: the free list to refill 2066 * @count: the number of new buffers to allocate 2067 * 2068 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 2069 * The caller must assure that @count does not exceed the queue's capacity 2070 * minus one (since we always leave a descriptor unavailable). 2071 */ 2072 static uint8_t 2073 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 2074 { 2075 struct if_rxd_update iru; 2076 struct rxq_refill_cb_arg cb_arg; 2077 struct mbuf *m; 2078 caddr_t cl, *sd_cl; 2079 struct mbuf **sd_m; 2080 bus_dmamap_t *sd_map; 2081 bus_addr_t bus_addr, *sd_ba; 2082 int err, frag_idx, i, idx, n, pidx; 2083 qidx_t credits; 2084 2085 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 2086 2087 sd_m = fl->ifl_sds.ifsd_m; 2088 sd_map = fl->ifl_sds.ifsd_map; 2089 sd_cl = fl->ifl_sds.ifsd_cl; 2090 sd_ba = fl->ifl_sds.ifsd_ba; 2091 pidx = fl->ifl_pidx; 2092 idx = pidx; 2093 frag_idx = fl->ifl_fragidx; 2094 credits = fl->ifl_credits; 2095 2096 i = 0; 2097 n = count; 2098 MPASS(n > 0); 2099 MPASS(credits + n <= fl->ifl_size); 2100 2101 if (pidx < fl->ifl_cidx) 2102 MPASS(pidx + n <= fl->ifl_cidx); 2103 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 2104 MPASS(fl->ifl_gen == 0); 2105 if (pidx > fl->ifl_cidx) 2106 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 2107 2108 DBG_COUNTER_INC(fl_refills); 2109 if (n > 8) 2110 DBG_COUNTER_INC(fl_refills_large); 2111 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 2112 while (n-- > 0) { 2113 /* 2114 * We allocate an uninitialized mbuf + cluster, mbuf is 2115 * initialized after rx. 2116 * 2117 * If the cluster is still set then we know a minimum sized 2118 * packet was received 2119 */ 2120 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2121 &frag_idx); 2122 if (frag_idx < 0) 2123 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2124 MPASS(frag_idx >= 0); 2125 if ((cl = sd_cl[frag_idx]) == NULL) { 2126 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2127 if (__predict_false(cl == NULL)) 2128 break; 2129 2130 cb_arg.error = 0; 2131 MPASS(sd_map != NULL); 2132 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2133 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2134 BUS_DMA_NOWAIT); 2135 if (__predict_false(err != 0 || cb_arg.error)) { 2136 uma_zfree(fl->ifl_zone, cl); 2137 break; 2138 } 2139 2140 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2141 sd_cl[frag_idx] = cl; 2142 #if MEMORY_LOGGING 2143 fl->ifl_cl_enqueued++; 2144 #endif 2145 } else { 2146 bus_addr = sd_ba[frag_idx]; 2147 } 2148 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2149 BUS_DMASYNC_PREREAD); 2150 2151 if (sd_m[frag_idx] == NULL) { 2152 m = m_gethdr_raw(M_NOWAIT, 0); 2153 if (__predict_false(m == NULL)) 2154 break; 2155 sd_m[frag_idx] = m; 2156 } 2157 bit_set(fl->ifl_rx_bitmap, frag_idx); 2158 #if MEMORY_LOGGING 2159 fl->ifl_m_enqueued++; 2160 #endif 2161 2162 DBG_COUNTER_INC(rx_allocs); 2163 fl->ifl_rxd_idxs[i] = frag_idx; 2164 fl->ifl_bus_addrs[i] = bus_addr; 2165 credits++; 2166 i++; 2167 MPASS(credits <= fl->ifl_size); 2168 if (++idx == fl->ifl_size) { 2169 #ifdef INVARIANTS 2170 fl->ifl_gen = 1; 2171 #endif 2172 idx = 0; 2173 } 2174 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2175 iru.iru_pidx = pidx; 2176 iru.iru_count = i; 2177 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2178 fl->ifl_pidx = idx; 2179 fl->ifl_credits = credits; 2180 pidx = idx; 2181 i = 0; 2182 } 2183 } 2184 2185 if (n < count - 1) { 2186 if (i != 0) { 2187 iru.iru_pidx = pidx; 2188 iru.iru_count = i; 2189 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2190 fl->ifl_pidx = idx; 2191 fl->ifl_credits = credits; 2192 } 2193 DBG_COUNTER_INC(rxd_flush); 2194 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2195 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2196 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2197 fl->ifl_id, fl->ifl_pidx); 2198 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2199 fl->ifl_fragidx = frag_idx + 1; 2200 if (fl->ifl_fragidx == fl->ifl_size) 2201 fl->ifl_fragidx = 0; 2202 } else { 2203 fl->ifl_fragidx = frag_idx; 2204 } 2205 } 2206 2207 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2208 } 2209 2210 static inline uint8_t 2211 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2212 { 2213 /* 2214 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2215 * This is important as it confuses most NICs. For instance, 2216 * Intel NICs have (per receive ring) RDH and RDT registers, where 2217 * RDH points to the next receive descriptor to be used by the NIC, 2218 * and RDT for the next receive descriptor to be published by the 2219 * driver to the NIC (RDT - 1 is thus the last valid one). 2220 * The condition RDH == RDT means no descriptors are available to 2221 * the NIC, and thus it would be ambiguous if it also meant that 2222 * all the descriptors are available to the NIC. 2223 */ 2224 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2225 #ifdef INVARIANTS 2226 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2227 #endif 2228 2229 MPASS(fl->ifl_credits <= fl->ifl_size); 2230 MPASS(reclaimable == delta); 2231 2232 if (reclaimable > 0) 2233 return (iflib_fl_refill(ctx, fl, reclaimable)); 2234 return (0); 2235 } 2236 2237 uint8_t 2238 iflib_in_detach(if_ctx_t ctx) 2239 { 2240 bool in_detach; 2241 2242 STATE_LOCK(ctx); 2243 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2244 STATE_UNLOCK(ctx); 2245 return (in_detach); 2246 } 2247 2248 static void 2249 iflib_fl_bufs_free(iflib_fl_t fl) 2250 { 2251 iflib_dma_info_t idi = fl->ifl_ifdi; 2252 bus_dmamap_t sd_map; 2253 uint32_t i; 2254 2255 for (i = 0; i < fl->ifl_size; i++) { 2256 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2257 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2258 2259 if (*sd_cl != NULL) { 2260 sd_map = fl->ifl_sds.ifsd_map[i]; 2261 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2262 BUS_DMASYNC_POSTREAD); 2263 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2264 uma_zfree(fl->ifl_zone, *sd_cl); 2265 *sd_cl = NULL; 2266 if (*sd_m != NULL) { 2267 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2268 m_free_raw(*sd_m); 2269 *sd_m = NULL; 2270 } 2271 } else { 2272 MPASS(*sd_m == NULL); 2273 } 2274 #if MEMORY_LOGGING 2275 fl->ifl_m_dequeued++; 2276 fl->ifl_cl_dequeued++; 2277 #endif 2278 } 2279 #ifdef INVARIANTS 2280 for (i = 0; i < fl->ifl_size; i++) { 2281 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2282 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2283 } 2284 #endif 2285 /* 2286 * Reset free list values 2287 */ 2288 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2289 bzero(idi->idi_vaddr, idi->idi_size); 2290 } 2291 2292 /********************************************************************* 2293 * 2294 * Initialize a free list and its buffers. 2295 * 2296 **********************************************************************/ 2297 static int 2298 iflib_fl_setup(iflib_fl_t fl) 2299 { 2300 iflib_rxq_t rxq = fl->ifl_rxq; 2301 if_ctx_t ctx = rxq->ifr_ctx; 2302 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2303 int qidx; 2304 2305 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2306 /* 2307 ** Free current RX buffer structs and their mbufs 2308 */ 2309 iflib_fl_bufs_free(fl); 2310 /* Now replenish the mbufs */ 2311 MPASS(fl->ifl_credits == 0); 2312 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2313 if (scctx->isc_rxd_buf_size[qidx] != 0) 2314 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2315 else 2316 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2317 /* 2318 * ifl_buf_size may be a driver-supplied value, so pull it up 2319 * to the selected mbuf size. 2320 */ 2321 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2322 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2323 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2324 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2325 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2326 2327 /* 2328 * Avoid pre-allocating zillions of clusters to an idle card 2329 * potentially speeding up attach. In any case make sure 2330 * to leave a descriptor unavailable. See the comment in 2331 * iflib_fl_refill_all(). 2332 */ 2333 MPASS(fl->ifl_size > 0); 2334 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2335 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2336 return (ENOBUFS); 2337 /* 2338 * handle failure 2339 */ 2340 MPASS(rxq != NULL); 2341 MPASS(fl->ifl_ifdi != NULL); 2342 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2343 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2344 return (0); 2345 } 2346 2347 /********************************************************************* 2348 * 2349 * Free receive ring data structures 2350 * 2351 **********************************************************************/ 2352 static void 2353 iflib_rx_sds_free(iflib_rxq_t rxq) 2354 { 2355 iflib_fl_t fl; 2356 int i, j; 2357 2358 if (rxq->ifr_fl != NULL) { 2359 for (i = 0; i < rxq->ifr_nfl; i++) { 2360 fl = &rxq->ifr_fl[i]; 2361 if (fl->ifl_buf_tag != NULL) { 2362 if (fl->ifl_sds.ifsd_map != NULL) { 2363 for (j = 0; j < fl->ifl_size; j++) { 2364 bus_dmamap_sync( 2365 fl->ifl_buf_tag, 2366 fl->ifl_sds.ifsd_map[j], 2367 BUS_DMASYNC_POSTREAD); 2368 bus_dmamap_unload( 2369 fl->ifl_buf_tag, 2370 fl->ifl_sds.ifsd_map[j]); 2371 bus_dmamap_destroy( 2372 fl->ifl_buf_tag, 2373 fl->ifl_sds.ifsd_map[j]); 2374 } 2375 } 2376 bus_dma_tag_destroy(fl->ifl_buf_tag); 2377 fl->ifl_buf_tag = NULL; 2378 } 2379 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2380 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2381 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2382 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2383 free(fl->ifl_rx_bitmap, M_IFLIB); 2384 fl->ifl_sds.ifsd_m = NULL; 2385 fl->ifl_sds.ifsd_cl = NULL; 2386 fl->ifl_sds.ifsd_ba = NULL; 2387 fl->ifl_sds.ifsd_map = NULL; 2388 fl->ifl_rx_bitmap = NULL; 2389 } 2390 free(rxq->ifr_fl, M_IFLIB); 2391 rxq->ifr_fl = NULL; 2392 free(rxq->ifr_ifdi, M_IFLIB); 2393 rxq->ifr_ifdi = NULL; 2394 rxq->ifr_cq_cidx = 0; 2395 } 2396 } 2397 2398 /* 2399 * Timer routine 2400 */ 2401 static void 2402 iflib_timer(void *arg) 2403 { 2404 iflib_txq_t txq = arg; 2405 if_ctx_t ctx = txq->ift_ctx; 2406 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2407 uint64_t this_tick = ticks; 2408 2409 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2410 return; 2411 2412 /* 2413 ** Check on the state of the TX queue(s), this 2414 ** can be done without the lock because its RO 2415 ** and the HUNG state will be static if set. 2416 */ 2417 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) { 2418 txq->ift_last_timer_tick = this_tick; 2419 IFDI_TIMER(ctx, txq->ift_id); 2420 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2421 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2422 (sctx->isc_pause_frames == 0))) 2423 goto hung; 2424 2425 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2426 ifmp_ring_is_stalled(txq->ift_br)) { 2427 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, 2428 ("queue can't be marked as hung if interface is down")); 2429 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2430 } 2431 txq->ift_cleaned_prev = txq->ift_cleaned; 2432 } 2433 /* handle any laggards */ 2434 if (txq->ift_db_pending) 2435 GROUPTASK_ENQUEUE(&txq->ift_task); 2436 2437 sctx->isc_pause_frames = 0; 2438 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2439 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, 2440 txq, txq->ift_timer.c_cpu); 2441 return; 2442 2443 hung: 2444 device_printf(ctx->ifc_dev, 2445 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2446 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2447 STATE_LOCK(ctx); 2448 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2449 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2450 iflib_admin_intr_deferred(ctx); 2451 STATE_UNLOCK(ctx); 2452 } 2453 2454 static uint16_t 2455 iflib_get_mbuf_size_for(unsigned int size) 2456 { 2457 2458 if (size <= MCLBYTES) 2459 return (MCLBYTES); 2460 else 2461 return (MJUMPAGESIZE); 2462 } 2463 2464 static void 2465 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2466 { 2467 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2468 2469 /* 2470 * XXX don't set the max_frame_size to larger 2471 * than the hardware can handle 2472 */ 2473 ctx->ifc_rx_mbuf_sz = 2474 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2475 } 2476 2477 uint32_t 2478 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2479 { 2480 2481 return (ctx->ifc_rx_mbuf_sz); 2482 } 2483 2484 static void 2485 iflib_init_locked(if_ctx_t ctx) 2486 { 2487 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2488 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2489 if_t ifp = ctx->ifc_ifp; 2490 iflib_fl_t fl; 2491 iflib_txq_t txq; 2492 iflib_rxq_t rxq; 2493 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2494 2495 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2496 IFDI_INTR_DISABLE(ctx); 2497 2498 /* 2499 * See iflib_stop(). Useful in case iflib_init_locked() is 2500 * called without first calling iflib_stop(). 2501 */ 2502 netmap_disable_all_rings(ifp); 2503 2504 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2505 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2506 /* Set hardware offload abilities */ 2507 if_clearhwassist(ifp); 2508 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2509 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2510 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2511 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2512 if (if_getcapenable(ifp) & IFCAP_TSO4) 2513 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2514 if (if_getcapenable(ifp) & IFCAP_TSO6) 2515 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2516 2517 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2518 CALLOUT_LOCK(txq); 2519 callout_stop(&txq->ift_timer); 2520 #ifdef DEV_NETMAP 2521 callout_stop(&txq->ift_netmap_timer); 2522 #endif /* DEV_NETMAP */ 2523 CALLOUT_UNLOCK(txq); 2524 (void)iflib_netmap_txq_init(ctx, txq); 2525 } 2526 2527 /* 2528 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2529 * that drivers can use the value when setting up the hardware receive 2530 * buffers. 2531 */ 2532 iflib_calc_rx_mbuf_sz(ctx); 2533 2534 #ifdef INVARIANTS 2535 i = if_getdrvflags(ifp); 2536 #endif 2537 IFDI_INIT(ctx); 2538 MPASS(if_getdrvflags(ifp) == i); 2539 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2540 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2541 /* This rxq is in netmap mode. Skip normal init. */ 2542 continue; 2543 } 2544 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2545 if (iflib_fl_setup(fl)) { 2546 device_printf(ctx->ifc_dev, 2547 "setting up free list %d failed - " 2548 "check cluster settings\n", j); 2549 goto done; 2550 } 2551 } 2552 } 2553 done: 2554 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2555 IFDI_INTR_ENABLE(ctx); 2556 txq = ctx->ifc_txqs; 2557 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2558 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 2559 txq->ift_timer.c_cpu); 2560 2561 /* Re-enable txsync/rxsync. */ 2562 netmap_enable_all_rings(ifp); 2563 } 2564 2565 static int 2566 iflib_media_change(if_t ifp) 2567 { 2568 if_ctx_t ctx = if_getsoftc(ifp); 2569 int err; 2570 2571 CTX_LOCK(ctx); 2572 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2573 iflib_if_init_locked(ctx); 2574 CTX_UNLOCK(ctx); 2575 return (err); 2576 } 2577 2578 static void 2579 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2580 { 2581 if_ctx_t ctx = if_getsoftc(ifp); 2582 2583 CTX_LOCK(ctx); 2584 IFDI_UPDATE_ADMIN_STATUS(ctx); 2585 IFDI_MEDIA_STATUS(ctx, ifmr); 2586 CTX_UNLOCK(ctx); 2587 } 2588 2589 void 2590 iflib_stop(if_ctx_t ctx) 2591 { 2592 iflib_txq_t txq = ctx->ifc_txqs; 2593 iflib_rxq_t rxq = ctx->ifc_rxqs; 2594 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2595 if_shared_ctx_t sctx = ctx->ifc_sctx; 2596 iflib_dma_info_t di; 2597 iflib_fl_t fl; 2598 int i, j; 2599 2600 /* Tell the stack that the interface is no longer active */ 2601 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2602 2603 IFDI_INTR_DISABLE(ctx); 2604 DELAY(1000); 2605 IFDI_STOP(ctx); 2606 DELAY(1000); 2607 2608 /* 2609 * Stop any pending txsync/rxsync and prevent new ones 2610 * form starting. Processes blocked in poll() will get 2611 * POLLERR. 2612 */ 2613 netmap_disable_all_rings(ctx->ifc_ifp); 2614 2615 iflib_debug_reset(); 2616 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2617 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2618 /* make sure all transmitters have completed before proceeding XXX */ 2619 2620 CALLOUT_LOCK(txq); 2621 callout_stop(&txq->ift_timer); 2622 #ifdef DEV_NETMAP 2623 callout_stop(&txq->ift_netmap_timer); 2624 #endif /* DEV_NETMAP */ 2625 CALLOUT_UNLOCK(txq); 2626 2627 /* clean any enqueued buffers */ 2628 iflib_ifmp_purge(txq); 2629 /* Free any existing tx buffers. */ 2630 for (j = 0; j < txq->ift_size; j++) { 2631 iflib_txsd_free(ctx, txq, j); 2632 } 2633 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2634 txq->ift_in_use = txq->ift_gen = txq->ift_no_desc_avail = 0; 2635 if (sctx->isc_flags & IFLIB_PRESERVE_TX_INDICES) 2636 txq->ift_cidx = txq->ift_pidx; 2637 else 2638 txq->ift_cidx = txq->ift_pidx = 0; 2639 2640 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2641 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2642 txq->ift_pullups = 0; 2643 ifmp_ring_reset_stats(txq->ift_br); 2644 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2645 bzero((void *)di->idi_vaddr, di->idi_size); 2646 } 2647 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2648 if (rxq->ifr_task.gt_taskqueue != NULL) 2649 gtaskqueue_drain(rxq->ifr_task.gt_taskqueue, 2650 &rxq->ifr_task.gt_task); 2651 2652 rxq->ifr_cq_cidx = 0; 2653 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2654 bzero((void *)di->idi_vaddr, di->idi_size); 2655 /* also resets the free lists pidx/cidx */ 2656 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2657 iflib_fl_bufs_free(fl); 2658 } 2659 } 2660 2661 static inline caddr_t 2662 calc_next_rxd(iflib_fl_t fl, int cidx) 2663 { 2664 qidx_t size; 2665 int nrxd; 2666 caddr_t start, end, cur, next; 2667 2668 nrxd = fl->ifl_size; 2669 size = fl->ifl_rxd_size; 2670 start = fl->ifl_ifdi->idi_vaddr; 2671 2672 if (__predict_false(size == 0)) 2673 return (start); 2674 cur = start + size*cidx; 2675 end = start + size*nrxd; 2676 next = CACHE_PTR_NEXT(cur); 2677 return (next < end ? next : start); 2678 } 2679 2680 static inline void 2681 prefetch_pkts(iflib_fl_t fl, int cidx) 2682 { 2683 int nextptr; 2684 int nrxd = fl->ifl_size; 2685 caddr_t next_rxd; 2686 2687 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2688 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2689 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2690 next_rxd = calc_next_rxd(fl, cidx); 2691 prefetch(next_rxd); 2692 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2693 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2694 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2695 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2696 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2697 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2698 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2699 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2700 } 2701 2702 static struct mbuf * 2703 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2704 int *pf_rv, if_rxd_info_t ri) 2705 { 2706 bus_dmamap_t map; 2707 iflib_fl_t fl; 2708 caddr_t payload; 2709 struct mbuf *m; 2710 int flid, cidx, len, next; 2711 2712 map = NULL; 2713 flid = irf->irf_flid; 2714 cidx = irf->irf_idx; 2715 fl = &rxq->ifr_fl[flid]; 2716 sd->ifsd_fl = fl; 2717 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2718 fl->ifl_credits--; 2719 #if MEMORY_LOGGING 2720 fl->ifl_m_dequeued++; 2721 #endif 2722 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2723 prefetch_pkts(fl, cidx); 2724 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2725 prefetch(&fl->ifl_sds.ifsd_map[next]); 2726 map = fl->ifl_sds.ifsd_map[cidx]; 2727 2728 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2729 2730 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2731 irf->irf_len != 0) { 2732 payload = *sd->ifsd_cl; 2733 payload += ri->iri_pad; 2734 len = ri->iri_len - ri->iri_pad; 2735 *pf_rv = pfil_mem_in(rxq->pfil, payload, len, ri->iri_ifp, &m); 2736 switch (*pf_rv) { 2737 case PFIL_DROPPED: 2738 case PFIL_CONSUMED: 2739 /* 2740 * The filter ate it. Everything is recycled. 2741 */ 2742 m = NULL; 2743 unload = 0; 2744 break; 2745 case PFIL_REALLOCED: 2746 /* 2747 * The filter copied it. Everything is recycled. 2748 * 'm' points at new mbuf. 2749 */ 2750 unload = 0; 2751 break; 2752 case PFIL_PASS: 2753 /* 2754 * Filter said it was OK, so receive like 2755 * normal 2756 */ 2757 m = fl->ifl_sds.ifsd_m[cidx]; 2758 fl->ifl_sds.ifsd_m[cidx] = NULL; 2759 break; 2760 default: 2761 MPASS(0); 2762 } 2763 } else { 2764 m = fl->ifl_sds.ifsd_m[cidx]; 2765 fl->ifl_sds.ifsd_m[cidx] = NULL; 2766 if (pf_rv != NULL) 2767 *pf_rv = PFIL_PASS; 2768 } 2769 2770 if (unload && irf->irf_len != 0) 2771 bus_dmamap_unload(fl->ifl_buf_tag, map); 2772 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2773 if (__predict_false(fl->ifl_cidx == 0)) 2774 fl->ifl_gen = 0; 2775 bit_clear(fl->ifl_rx_bitmap, cidx); 2776 return (m); 2777 } 2778 2779 static struct mbuf * 2780 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2781 { 2782 struct mbuf *m, *mh, *mt; 2783 caddr_t cl; 2784 int *pf_rv_ptr, flags, i, padlen; 2785 bool consumed; 2786 2787 i = 0; 2788 mh = NULL; 2789 consumed = false; 2790 *pf_rv = PFIL_PASS; 2791 pf_rv_ptr = pf_rv; 2792 do { 2793 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2794 pf_rv_ptr, ri); 2795 2796 MPASS(*sd->ifsd_cl != NULL); 2797 2798 /* 2799 * Exclude zero-length frags & frags from 2800 * packets the filter has consumed or dropped 2801 */ 2802 if (ri->iri_frags[i].irf_len == 0 || consumed || 2803 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2804 if (mh == NULL) { 2805 /* everything saved here */ 2806 consumed = true; 2807 pf_rv_ptr = NULL; 2808 continue; 2809 } 2810 /* XXX we can save the cluster here, but not the mbuf */ 2811 m_init(m, M_NOWAIT, MT_DATA, 0); 2812 m_free(m); 2813 continue; 2814 } 2815 if (mh == NULL) { 2816 flags = M_PKTHDR|M_EXT; 2817 mh = mt = m; 2818 padlen = ri->iri_pad; 2819 } else { 2820 flags = M_EXT; 2821 mt->m_next = m; 2822 mt = m; 2823 /* assuming padding is only on the first fragment */ 2824 padlen = 0; 2825 } 2826 cl = *sd->ifsd_cl; 2827 *sd->ifsd_cl = NULL; 2828 2829 /* Can these two be made one ? */ 2830 m_init(m, M_NOWAIT, MT_DATA, flags); 2831 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2832 /* 2833 * These must follow m_init and m_cljset 2834 */ 2835 m->m_data += padlen; 2836 ri->iri_len -= padlen; 2837 m->m_len = ri->iri_frags[i].irf_len; 2838 } while (++i < ri->iri_nfrags); 2839 2840 return (mh); 2841 } 2842 2843 /* 2844 * Process one software descriptor 2845 */ 2846 static struct mbuf * 2847 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2848 { 2849 struct if_rxsd sd; 2850 struct mbuf *m; 2851 int pf_rv; 2852 2853 /* should I merge this back in now that the two paths are basically duplicated? */ 2854 if (ri->iri_nfrags == 1 && 2855 ri->iri_frags[0].irf_len != 0 && 2856 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2857 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2858 &pf_rv, ri); 2859 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2860 return (m); 2861 if (pf_rv == PFIL_PASS) { 2862 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2863 #ifndef __NO_STRICT_ALIGNMENT 2864 if (!IP_ALIGNED(m) && ri->iri_pad == 0) 2865 m->m_data += 2; 2866 #endif 2867 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2868 m->m_len = ri->iri_frags[0].irf_len; 2869 m->m_data += ri->iri_pad; 2870 ri->iri_len -= ri->iri_pad; 2871 } 2872 } else { 2873 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2874 if (m == NULL) 2875 return (NULL); 2876 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2877 return (m); 2878 } 2879 m->m_pkthdr.len = ri->iri_len; 2880 m->m_pkthdr.rcvif = ri->iri_ifp; 2881 m->m_flags |= ri->iri_flags; 2882 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2883 m->m_pkthdr.flowid = ri->iri_flowid; 2884 M_HASHTYPE_SET(m, ri->iri_rsstype); 2885 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2886 m->m_pkthdr.csum_data = ri->iri_csum_data; 2887 return (m); 2888 } 2889 2890 #if defined(INET6) || defined(INET) 2891 static void 2892 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2893 { 2894 CURVNET_SET(if_getvnet(lc->ifp)); 2895 #if defined(INET6) 2896 *v6 = V_ip6_forwarding; 2897 #endif 2898 #if defined(INET) 2899 *v4 = V_ipforwarding; 2900 #endif 2901 CURVNET_RESTORE(); 2902 } 2903 2904 /* 2905 * Returns true if it's possible this packet could be LROed. 2906 * if it returns false, it is guaranteed that tcp_lro_rx() 2907 * would not return zero. 2908 */ 2909 static bool 2910 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2911 { 2912 struct ether_header *eh; 2913 2914 eh = mtod(m, struct ether_header *); 2915 switch (eh->ether_type) { 2916 #if defined(INET6) 2917 case htons(ETHERTYPE_IPV6): 2918 return (!v6_forwarding); 2919 #endif 2920 #if defined (INET) 2921 case htons(ETHERTYPE_IP): 2922 return (!v4_forwarding); 2923 #endif 2924 } 2925 2926 return false; 2927 } 2928 #else 2929 static void 2930 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2931 { 2932 } 2933 #endif 2934 2935 static void 2936 _task_fn_rx_watchdog(void *context) 2937 { 2938 iflib_rxq_t rxq = context; 2939 2940 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2941 } 2942 2943 static uint8_t 2944 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2945 { 2946 if_t ifp; 2947 if_ctx_t ctx = rxq->ifr_ctx; 2948 if_shared_ctx_t sctx = ctx->ifc_sctx; 2949 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2950 int avail, i; 2951 qidx_t *cidxp; 2952 struct if_rxd_info ri; 2953 int err, budget_left, rx_bytes, rx_pkts; 2954 iflib_fl_t fl; 2955 int lro_enabled; 2956 bool v4_forwarding, v6_forwarding, lro_possible; 2957 uint8_t retval = 0; 2958 2959 /* 2960 * XXX early demux data packets so that if_input processing only handles 2961 * acks in interrupt context 2962 */ 2963 struct mbuf *m, *mh, *mt, *mf; 2964 2965 NET_EPOCH_ASSERT(); 2966 2967 lro_possible = v4_forwarding = v6_forwarding = false; 2968 ifp = ctx->ifc_ifp; 2969 mh = mt = NULL; 2970 MPASS(budget > 0); 2971 rx_pkts = rx_bytes = 0; 2972 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2973 cidxp = &rxq->ifr_cq_cidx; 2974 else 2975 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2976 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2977 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2978 retval |= iflib_fl_refill_all(ctx, fl); 2979 DBG_COUNTER_INC(rx_unavail); 2980 return (retval); 2981 } 2982 2983 /* pfil needs the vnet to be set */ 2984 CURVNET_SET_QUIET(if_getvnet(ifp)); 2985 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2986 if (__predict_false(!CTX_ACTIVE(ctx))) { 2987 DBG_COUNTER_INC(rx_ctx_inactive); 2988 break; 2989 } 2990 /* 2991 * Reset client set fields to their default values 2992 */ 2993 rxd_info_zero(&ri); 2994 ri.iri_qsidx = rxq->ifr_id; 2995 ri.iri_cidx = *cidxp; 2996 ri.iri_ifp = ifp; 2997 ri.iri_frags = rxq->ifr_frags; 2998 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2999 3000 if (err) 3001 goto err; 3002 rx_pkts += 1; 3003 rx_bytes += ri.iri_len; 3004 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 3005 *cidxp = ri.iri_cidx; 3006 /* Update our consumer index */ 3007 /* XXX NB: shurd - check if this is still safe */ 3008 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 3009 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 3010 /* was this only a completion queue message? */ 3011 if (__predict_false(ri.iri_nfrags == 0)) 3012 continue; 3013 } 3014 MPASS(ri.iri_nfrags != 0); 3015 MPASS(ri.iri_len != 0); 3016 3017 /* will advance the cidx on the corresponding free lists */ 3018 m = iflib_rxd_pkt_get(rxq, &ri); 3019 avail--; 3020 budget_left--; 3021 if (avail == 0 && budget_left) 3022 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 3023 3024 if (__predict_false(m == NULL)) 3025 continue; 3026 3027 /* imm_pkt: -- cxgb */ 3028 if (mh == NULL) 3029 mh = mt = m; 3030 else { 3031 mt->m_nextpkt = m; 3032 mt = m; 3033 } 3034 } 3035 CURVNET_RESTORE(); 3036 /* make sure that we can refill faster than drain */ 3037 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3038 retval |= iflib_fl_refill_all(ctx, fl); 3039 3040 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 3041 if (lro_enabled) 3042 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 3043 mt = mf = NULL; 3044 while (mh != NULL) { 3045 m = mh; 3046 mh = mh->m_nextpkt; 3047 m->m_nextpkt = NULL; 3048 #ifndef __NO_STRICT_ALIGNMENT 3049 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 3050 continue; 3051 #endif 3052 #if defined(INET6) || defined(INET) 3053 if (lro_enabled) { 3054 if (!lro_possible) { 3055 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 3056 if (lro_possible && mf != NULL) { 3057 if_input(ifp, mf); 3058 DBG_COUNTER_INC(rx_if_input); 3059 mt = mf = NULL; 3060 } 3061 } 3062 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 3063 (CSUM_L4_CALC|CSUM_L4_VALID)) { 3064 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 3065 continue; 3066 } 3067 } 3068 #endif 3069 if (lro_possible) { 3070 if_input(ifp, m); 3071 DBG_COUNTER_INC(rx_if_input); 3072 continue; 3073 } 3074 3075 if (mf == NULL) 3076 mf = m; 3077 if (mt != NULL) 3078 mt->m_nextpkt = m; 3079 mt = m; 3080 } 3081 if (mf != NULL) { 3082 if_input(ifp, mf); 3083 DBG_COUNTER_INC(rx_if_input); 3084 } 3085 3086 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 3087 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 3088 3089 /* 3090 * Flush any outstanding LRO work 3091 */ 3092 #if defined(INET6) || defined(INET) 3093 tcp_lro_flush_all(&rxq->ifr_lc); 3094 #endif 3095 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 3096 retval |= IFLIB_RXEOF_MORE; 3097 return (retval); 3098 err: 3099 STATE_LOCK(ctx); 3100 ctx->ifc_flags |= IFC_DO_RESET; 3101 iflib_admin_intr_deferred(ctx); 3102 STATE_UNLOCK(ctx); 3103 return (0); 3104 } 3105 3106 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 3107 static inline qidx_t 3108 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 3109 { 3110 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3111 qidx_t minthresh = txq->ift_size / 8; 3112 if (in_use > 4*minthresh) 3113 return (notify_count); 3114 if (in_use > 2*minthresh) 3115 return (notify_count >> 1); 3116 if (in_use > minthresh) 3117 return (notify_count >> 3); 3118 return (0); 3119 } 3120 3121 static inline qidx_t 3122 txq_max_rs_deferred(iflib_txq_t txq) 3123 { 3124 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3125 qidx_t minthresh = txq->ift_size / 8; 3126 if (txq->ift_in_use > 4*minthresh) 3127 return (notify_count); 3128 if (txq->ift_in_use > 2*minthresh) 3129 return (notify_count >> 1); 3130 if (txq->ift_in_use > minthresh) 3131 return (notify_count >> 2); 3132 return (2); 3133 } 3134 3135 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 3136 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 3137 3138 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 3139 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 3140 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 3141 3142 /* forward compatibility for cxgb */ 3143 #define FIRST_QSET(ctx) 0 3144 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3145 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3146 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3147 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3148 3149 /* XXX we should be setting this to something other than zero */ 3150 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 3151 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3152 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3153 3154 static inline bool 3155 iflib_txd_db_check(iflib_txq_t txq, int ring) 3156 { 3157 if_ctx_t ctx = txq->ift_ctx; 3158 qidx_t dbval, max; 3159 3160 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use); 3161 3162 /* force || threshold exceeded || at the edge of the ring */ 3163 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2)) { 3164 3165 /* 3166 * 'npending' is used if the card's doorbell is in terms of the number of descriptors 3167 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the 3168 * producer index explicitly (INTC). 3169 */ 3170 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3171 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3172 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3173 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3174 3175 /* 3176 * Absent bugs there are zero packets pending so reset pending counts to zero. 3177 */ 3178 txq->ift_db_pending = txq->ift_npending = 0; 3179 return (true); 3180 } 3181 return (false); 3182 } 3183 3184 #ifdef PKT_DEBUG 3185 static void 3186 print_pkt(if_pkt_info_t pi) 3187 { 3188 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3189 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3190 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3191 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3192 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3193 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3194 } 3195 #endif 3196 3197 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3198 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3199 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3200 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3201 3202 /** 3203 * Parses out ethernet header information in the given mbuf. 3204 * Returns in pi: ipi_etype (EtherType) and ipi_ehdrlen (Ethernet header length) 3205 * 3206 * This will account for the VLAN header if present. 3207 * 3208 * XXX: This doesn't handle QinQ, which could prevent TX offloads for those 3209 * types of packets. 3210 */ 3211 static int 3212 iflib_parse_ether_header(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3213 { 3214 struct ether_vlan_header *eh; 3215 struct mbuf *m; 3216 3217 m = *mp; 3218 if (__predict_false(m->m_len < sizeof(*eh))) { 3219 (*pullups)++; 3220 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3221 return (ENOMEM); 3222 } 3223 eh = mtod(m, struct ether_vlan_header *); 3224 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3225 pi->ipi_etype = ntohs(eh->evl_proto); 3226 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3227 } else { 3228 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3229 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3230 } 3231 *mp = m; 3232 3233 return (0); 3234 } 3235 3236 /** 3237 * Parse up to the L3 header and extract IPv4/IPv6 header information into pi. 3238 * Currently this information includes: IP ToS value, IP header version/presence 3239 * 3240 * This is missing some checks and doesn't edit the packet content as it goes, 3241 * unlike iflib_parse_header(), in order to keep the amount of code here minimal. 3242 */ 3243 static int 3244 iflib_parse_header_partial(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3245 { 3246 struct mbuf *m; 3247 int err; 3248 3249 *pullups = 0; 3250 m = *mp; 3251 if (!M_WRITABLE(m)) { 3252 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3253 return (ENOMEM); 3254 } else { 3255 m_freem(*mp); 3256 DBG_COUNTER_INC(tx_frees); 3257 *mp = m; 3258 } 3259 } 3260 3261 /* Fills out pi->ipi_etype */ 3262 err = iflib_parse_ether_header(pi, mp, pullups); 3263 if (err) 3264 return (err); 3265 m = *mp; 3266 3267 switch (pi->ipi_etype) { 3268 #ifdef INET 3269 case ETHERTYPE_IP: 3270 { 3271 struct mbuf *n; 3272 struct ip *ip = NULL; 3273 int miniplen; 3274 3275 miniplen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip)); 3276 if (__predict_false(m->m_len < miniplen)) { 3277 /* 3278 * Check for common case where the first mbuf only contains 3279 * the Ethernet header 3280 */ 3281 if (m->m_len == pi->ipi_ehdrlen) { 3282 n = m->m_next; 3283 MPASS(n); 3284 /* If next mbuf contains at least the minimal IP header, then stop */ 3285 if (n->m_len >= sizeof(*ip)) { 3286 ip = (struct ip *)n->m_data; 3287 } else { 3288 (*pullups)++; 3289 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3290 return (ENOMEM); 3291 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3292 } 3293 } else { 3294 (*pullups)++; 3295 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3296 return (ENOMEM); 3297 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3298 } 3299 } else { 3300 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3301 } 3302 3303 /* Have the IPv4 header w/ no options here */ 3304 pi->ipi_ip_hlen = ip->ip_hl << 2; 3305 pi->ipi_ipproto = ip->ip_p; 3306 pi->ipi_ip_tos = ip->ip_tos; 3307 pi->ipi_flags |= IPI_TX_IPV4; 3308 3309 break; 3310 } 3311 #endif 3312 #ifdef INET6 3313 case ETHERTYPE_IPV6: 3314 { 3315 struct ip6_hdr *ip6; 3316 3317 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3318 (*pullups)++; 3319 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3320 return (ENOMEM); 3321 } 3322 ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3323 3324 /* Have the IPv6 fixed header here */ 3325 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3326 pi->ipi_ipproto = ip6->ip6_nxt; 3327 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3328 pi->ipi_flags |= IPI_TX_IPV6; 3329 3330 break; 3331 } 3332 #endif 3333 default: 3334 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3335 pi->ipi_ip_hlen = 0; 3336 break; 3337 } 3338 *mp = m; 3339 3340 return (0); 3341 3342 } 3343 3344 static int 3345 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3346 { 3347 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3348 struct mbuf *m; 3349 int err; 3350 3351 m = *mp; 3352 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3353 M_WRITABLE(m) == 0) { 3354 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3355 return (ENOMEM); 3356 } else { 3357 m_freem(*mp); 3358 DBG_COUNTER_INC(tx_frees); 3359 *mp = m; 3360 } 3361 } 3362 3363 /* Fills out pi->ipi_etype */ 3364 err = iflib_parse_ether_header(pi, mp, &txq->ift_pullups); 3365 if (__predict_false(err)) 3366 return (err); 3367 m = *mp; 3368 3369 switch (pi->ipi_etype) { 3370 #ifdef INET 3371 case ETHERTYPE_IP: 3372 { 3373 struct mbuf *n; 3374 struct ip *ip = NULL; 3375 struct tcphdr *th = NULL; 3376 int minthlen; 3377 3378 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3379 if (__predict_false(m->m_len < minthlen)) { 3380 /* 3381 * if this code bloat is causing too much of a hit 3382 * move it to a separate function and mark it noinline 3383 */ 3384 if (m->m_len == pi->ipi_ehdrlen) { 3385 n = m->m_next; 3386 MPASS(n); 3387 if (n->m_len >= sizeof(*ip)) { 3388 ip = (struct ip *)n->m_data; 3389 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3390 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3391 } else { 3392 txq->ift_pullups++; 3393 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3394 return (ENOMEM); 3395 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3396 } 3397 } else { 3398 txq->ift_pullups++; 3399 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3400 return (ENOMEM); 3401 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3402 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3403 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3404 } 3405 } else { 3406 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3407 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3408 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3409 } 3410 pi->ipi_ip_hlen = ip->ip_hl << 2; 3411 pi->ipi_ipproto = ip->ip_p; 3412 pi->ipi_ip_tos = ip->ip_tos; 3413 pi->ipi_flags |= IPI_TX_IPV4; 3414 3415 /* TCP checksum offload may require TCP header length */ 3416 if (IS_TX_OFFLOAD4(pi)) { 3417 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3418 if (__predict_false(th == NULL)) { 3419 txq->ift_pullups++; 3420 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3421 return (ENOMEM); 3422 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3423 } 3424 pi->ipi_tcp_hflags = th->th_flags; 3425 pi->ipi_tcp_hlen = th->th_off << 2; 3426 pi->ipi_tcp_seq = th->th_seq; 3427 } 3428 if (IS_TSO4(pi)) { 3429 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3430 return (ENXIO); 3431 /* 3432 * TSO always requires hardware checksum offload. 3433 */ 3434 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3435 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3436 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3437 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3438 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3439 ip->ip_sum = 0; 3440 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3441 } 3442 } 3443 } 3444 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3445 ip->ip_sum = 0; 3446 3447 break; 3448 } 3449 #endif 3450 #ifdef INET6 3451 case ETHERTYPE_IPV6: 3452 { 3453 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3454 struct tcphdr *th; 3455 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3456 3457 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3458 txq->ift_pullups++; 3459 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3460 return (ENOMEM); 3461 } 3462 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3463 3464 /* XXX-BZ this will go badly in case of ext hdrs. */ 3465 pi->ipi_ipproto = ip6->ip6_nxt; 3466 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3467 pi->ipi_flags |= IPI_TX_IPV6; 3468 3469 /* TCP checksum offload may require TCP header length */ 3470 if (IS_TX_OFFLOAD6(pi)) { 3471 if (pi->ipi_ipproto == IPPROTO_TCP) { 3472 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3473 txq->ift_pullups++; 3474 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3475 return (ENOMEM); 3476 } 3477 pi->ipi_tcp_hflags = th->th_flags; 3478 pi->ipi_tcp_hlen = th->th_off << 2; 3479 pi->ipi_tcp_seq = th->th_seq; 3480 } 3481 if (IS_TSO6(pi)) { 3482 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3483 return (ENXIO); 3484 /* 3485 * TSO always requires hardware checksum offload. 3486 */ 3487 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3488 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3489 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3490 } 3491 } 3492 break; 3493 } 3494 #endif 3495 default: 3496 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3497 pi->ipi_ip_hlen = 0; 3498 break; 3499 } 3500 *mp = m; 3501 3502 return (0); 3503 } 3504 3505 /* 3506 * If dodgy hardware rejects the scatter gather chain we've handed it 3507 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3508 * m_defrag'd mbufs 3509 */ 3510 static __noinline struct mbuf * 3511 iflib_remove_mbuf(iflib_txq_t txq) 3512 { 3513 int ntxd, pidx; 3514 struct mbuf *m, **ifsd_m; 3515 3516 ifsd_m = txq->ift_sds.ifsd_m; 3517 ntxd = txq->ift_size; 3518 pidx = txq->ift_pidx & (ntxd - 1); 3519 ifsd_m = txq->ift_sds.ifsd_m; 3520 m = ifsd_m[pidx]; 3521 ifsd_m[pidx] = NULL; 3522 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3523 if (txq->ift_sds.ifsd_tso_map != NULL) 3524 bus_dmamap_unload(txq->ift_tso_buf_tag, 3525 txq->ift_sds.ifsd_tso_map[pidx]); 3526 #if MEMORY_LOGGING 3527 txq->ift_dequeued++; 3528 #endif 3529 return (m); 3530 } 3531 3532 static inline caddr_t 3533 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3534 { 3535 qidx_t size; 3536 int ntxd; 3537 caddr_t start, end, cur, next; 3538 3539 ntxd = txq->ift_size; 3540 size = txq->ift_txd_size[qid]; 3541 start = txq->ift_ifdi[qid].idi_vaddr; 3542 3543 if (__predict_false(size == 0)) 3544 return (start); 3545 cur = start + size*cidx; 3546 end = start + size*ntxd; 3547 next = CACHE_PTR_NEXT(cur); 3548 return (next < end ? next : start); 3549 } 3550 3551 /* 3552 * Pad an mbuf to ensure a minimum ethernet frame size. 3553 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3554 */ 3555 static __noinline int 3556 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3557 { 3558 /* 3559 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3560 * and ARP message is the smallest common payload I can think of 3561 */ 3562 static char pad[18]; /* just zeros */ 3563 int n; 3564 struct mbuf *new_head; 3565 3566 if (!M_WRITABLE(*m_head)) { 3567 new_head = m_dup(*m_head, M_NOWAIT); 3568 if (new_head == NULL) { 3569 m_freem(*m_head); 3570 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3571 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3572 DBG_COUNTER_INC(tx_frees); 3573 return ENOMEM; 3574 } 3575 m_freem(*m_head); 3576 *m_head = new_head; 3577 } 3578 3579 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3580 n > 0; n -= sizeof(pad)) 3581 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3582 break; 3583 3584 if (n > 0) { 3585 m_freem(*m_head); 3586 device_printf(dev, "cannot pad short frame\n"); 3587 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3588 DBG_COUNTER_INC(tx_frees); 3589 return (ENOBUFS); 3590 } 3591 3592 return 0; 3593 } 3594 3595 static int 3596 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3597 { 3598 if_ctx_t ctx; 3599 if_shared_ctx_t sctx; 3600 if_softc_ctx_t scctx; 3601 bus_dma_tag_t buf_tag; 3602 bus_dma_segment_t *segs; 3603 struct mbuf *m_head, **ifsd_m; 3604 void *next_txd; 3605 bus_dmamap_t map; 3606 struct if_pkt_info pi; 3607 int remap = 0; 3608 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3609 3610 ctx = txq->ift_ctx; 3611 sctx = ctx->ifc_sctx; 3612 scctx = &ctx->ifc_softc_ctx; 3613 segs = txq->ift_segs; 3614 ntxd = txq->ift_size; 3615 m_head = *m_headp; 3616 map = NULL; 3617 3618 /* 3619 * If we're doing TSO the next descriptor to clean may be quite far ahead 3620 */ 3621 cidx = txq->ift_cidx; 3622 pidx = txq->ift_pidx; 3623 if (ctx->ifc_flags & IFC_PREFETCH) { 3624 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3625 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3626 next_txd = calc_next_txd(txq, cidx, 0); 3627 prefetch(next_txd); 3628 } 3629 3630 /* prefetch the next cache line of mbuf pointers and flags */ 3631 prefetch(&txq->ift_sds.ifsd_m[next]); 3632 prefetch(&txq->ift_sds.ifsd_map[next]); 3633 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3634 } 3635 map = txq->ift_sds.ifsd_map[pidx]; 3636 ifsd_m = txq->ift_sds.ifsd_m; 3637 3638 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3639 buf_tag = txq->ift_tso_buf_tag; 3640 max_segs = scctx->isc_tx_tso_segments_max; 3641 map = txq->ift_sds.ifsd_tso_map[pidx]; 3642 MPASS(buf_tag != NULL); 3643 MPASS(max_segs > 0); 3644 } else { 3645 buf_tag = txq->ift_buf_tag; 3646 max_segs = scctx->isc_tx_nsegments; 3647 map = txq->ift_sds.ifsd_map[pidx]; 3648 } 3649 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3650 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3651 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3652 if (err) { 3653 DBG_COUNTER_INC(encap_txd_encap_fail); 3654 return err; 3655 } 3656 } 3657 m_head = *m_headp; 3658 3659 pkt_info_zero(&pi); 3660 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3661 pi.ipi_pidx = pidx; 3662 pi.ipi_qsidx = txq->ift_id; 3663 pi.ipi_len = m_head->m_pkthdr.len; 3664 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3665 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3666 3667 /* deliberate bitwise OR to make one condition */ 3668 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3669 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3670 DBG_COUNTER_INC(encap_txd_encap_fail); 3671 return (err); 3672 } 3673 m_head = *m_headp; 3674 } 3675 3676 retry: 3677 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3678 BUS_DMA_NOWAIT); 3679 defrag: 3680 if (__predict_false(err)) { 3681 switch (err) { 3682 case EFBIG: 3683 /* try collapse once and defrag once */ 3684 if (remap == 0) { 3685 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3686 /* try defrag if collapsing fails */ 3687 if (m_head == NULL) 3688 remap++; 3689 } 3690 if (remap == 1) { 3691 txq->ift_mbuf_defrag++; 3692 m_head = m_defrag(*m_headp, M_NOWAIT); 3693 } 3694 /* 3695 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3696 * failed to map an mbuf that was run through m_defrag 3697 */ 3698 MPASS(remap <= 1); 3699 if (__predict_false(m_head == NULL || remap > 1)) 3700 goto defrag_failed; 3701 remap++; 3702 *m_headp = m_head; 3703 goto retry; 3704 break; 3705 case ENOMEM: 3706 txq->ift_no_tx_dma_setup++; 3707 break; 3708 default: 3709 txq->ift_no_tx_dma_setup++; 3710 m_freem(*m_headp); 3711 DBG_COUNTER_INC(tx_frees); 3712 *m_headp = NULL; 3713 break; 3714 } 3715 txq->ift_map_failed++; 3716 DBG_COUNTER_INC(encap_load_mbuf_fail); 3717 DBG_COUNTER_INC(encap_txd_encap_fail); 3718 return (err); 3719 } 3720 ifsd_m[pidx] = m_head; 3721 /* 3722 * XXX assumes a 1 to 1 relationship between segments and 3723 * descriptors - this does not hold true on all drivers, e.g. 3724 * cxgb 3725 */ 3726 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3727 txq->ift_no_desc_avail++; 3728 bus_dmamap_unload(buf_tag, map); 3729 DBG_COUNTER_INC(encap_txq_avail_fail); 3730 DBG_COUNTER_INC(encap_txd_encap_fail); 3731 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3732 GROUPTASK_ENQUEUE(&txq->ift_task); 3733 return (ENOBUFS); 3734 } 3735 /* 3736 * On Intel cards we can greatly reduce the number of TX interrupts 3737 * we see by only setting report status on every Nth descriptor. 3738 * However, this also means that the driver will need to keep track 3739 * of the descriptors that RS was set on to check them for the DD bit. 3740 */ 3741 txq->ift_rs_pending += nsegs + 1; 3742 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3743 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3744 pi.ipi_flags |= IPI_TX_INTR; 3745 txq->ift_rs_pending = 0; 3746 } 3747 3748 pi.ipi_segs = segs; 3749 pi.ipi_nsegs = nsegs; 3750 3751 MPASS(pidx >= 0 && pidx < txq->ift_size); 3752 #ifdef PKT_DEBUG 3753 print_pkt(&pi); 3754 #endif 3755 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3756 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3757 DBG_COUNTER_INC(tx_encap); 3758 MPASS(pi.ipi_new_pidx < txq->ift_size); 3759 3760 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3761 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3762 ndesc += txq->ift_size; 3763 txq->ift_gen = 1; 3764 } 3765 /* 3766 * drivers can need as many as 3767 * two sentinels 3768 */ 3769 MPASS(ndesc <= pi.ipi_nsegs + 2); 3770 MPASS(pi.ipi_new_pidx != pidx); 3771 MPASS(ndesc > 0); 3772 txq->ift_in_use += ndesc; 3773 txq->ift_db_pending += ndesc; 3774 3775 /* 3776 * We update the last software descriptor again here because there may 3777 * be a sentinel and/or there may be more mbufs than segments 3778 */ 3779 txq->ift_pidx = pi.ipi_new_pidx; 3780 txq->ift_npending += pi.ipi_ndescs; 3781 } else { 3782 *m_headp = m_head = iflib_remove_mbuf(txq); 3783 if (err == EFBIG) { 3784 txq->ift_txd_encap_efbig++; 3785 if (remap < 2) { 3786 remap = 1; 3787 goto defrag; 3788 } 3789 } 3790 goto defrag_failed; 3791 } 3792 /* 3793 * err can't possibly be non-zero here, so we don't neet to test it 3794 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3795 */ 3796 return (err); 3797 3798 defrag_failed: 3799 txq->ift_mbuf_defrag_failed++; 3800 txq->ift_map_failed++; 3801 m_freem(*m_headp); 3802 DBG_COUNTER_INC(tx_frees); 3803 *m_headp = NULL; 3804 DBG_COUNTER_INC(encap_txd_encap_fail); 3805 return (ENOMEM); 3806 } 3807 3808 static void 3809 iflib_tx_desc_free(iflib_txq_t txq, int n) 3810 { 3811 uint32_t qsize, cidx, mask, gen; 3812 struct mbuf *m, **ifsd_m; 3813 bool do_prefetch; 3814 3815 cidx = txq->ift_cidx; 3816 gen = txq->ift_gen; 3817 qsize = txq->ift_size; 3818 mask = qsize-1; 3819 ifsd_m = txq->ift_sds.ifsd_m; 3820 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3821 3822 while (n-- > 0) { 3823 if (do_prefetch) { 3824 prefetch(ifsd_m[(cidx + 3) & mask]); 3825 prefetch(ifsd_m[(cidx + 4) & mask]); 3826 } 3827 if ((m = ifsd_m[cidx]) != NULL) { 3828 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3829 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3830 bus_dmamap_sync(txq->ift_tso_buf_tag, 3831 txq->ift_sds.ifsd_tso_map[cidx], 3832 BUS_DMASYNC_POSTWRITE); 3833 bus_dmamap_unload(txq->ift_tso_buf_tag, 3834 txq->ift_sds.ifsd_tso_map[cidx]); 3835 } else { 3836 bus_dmamap_sync(txq->ift_buf_tag, 3837 txq->ift_sds.ifsd_map[cidx], 3838 BUS_DMASYNC_POSTWRITE); 3839 bus_dmamap_unload(txq->ift_buf_tag, 3840 txq->ift_sds.ifsd_map[cidx]); 3841 } 3842 /* XXX we don't support any drivers that batch packets yet */ 3843 MPASS(m->m_nextpkt == NULL); 3844 m_freem(m); 3845 ifsd_m[cidx] = NULL; 3846 #if MEMORY_LOGGING 3847 txq->ift_dequeued++; 3848 #endif 3849 DBG_COUNTER_INC(tx_frees); 3850 } 3851 if (__predict_false(++cidx == qsize)) { 3852 cidx = 0; 3853 gen = 0; 3854 } 3855 } 3856 txq->ift_cidx = cidx; 3857 txq->ift_gen = gen; 3858 } 3859 3860 static __inline int 3861 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3862 { 3863 int reclaim; 3864 if_ctx_t ctx = txq->ift_ctx; 3865 3866 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3867 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3868 3869 /* 3870 * Need a rate-limiting check so that this isn't called every time 3871 */ 3872 iflib_tx_credits_update(ctx, txq); 3873 reclaim = DESC_RECLAIMABLE(txq); 3874 3875 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3876 #ifdef INVARIANTS 3877 if (iflib_verbose_debug) { 3878 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3879 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3880 reclaim, thresh); 3881 } 3882 #endif 3883 return (0); 3884 } 3885 iflib_tx_desc_free(txq, reclaim); 3886 txq->ift_cleaned += reclaim; 3887 txq->ift_in_use -= reclaim; 3888 3889 return (reclaim); 3890 } 3891 3892 static struct mbuf ** 3893 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3894 { 3895 int next, size; 3896 struct mbuf **items; 3897 3898 size = r->size; 3899 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3900 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3901 3902 prefetch(items[(cidx + offset) & (size-1)]); 3903 if (remaining > 1) { 3904 prefetch2cachelines(&items[next]); 3905 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3906 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3907 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3908 } 3909 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3910 } 3911 3912 static void 3913 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3914 { 3915 3916 ifmp_ring_check_drainage(txq->ift_br, budget); 3917 } 3918 3919 static uint32_t 3920 iflib_txq_can_drain(struct ifmp_ring *r) 3921 { 3922 iflib_txq_t txq = r->cookie; 3923 if_ctx_t ctx = txq->ift_ctx; 3924 3925 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3926 return (1); 3927 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3928 BUS_DMASYNC_POSTREAD); 3929 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3930 false)); 3931 } 3932 3933 static uint32_t 3934 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3935 { 3936 iflib_txq_t txq = r->cookie; 3937 if_ctx_t ctx = txq->ift_ctx; 3938 if_t ifp = ctx->ifc_ifp; 3939 struct mbuf *m, **mp; 3940 int avail, bytes_sent, skipped, count, err, i; 3941 int mcast_sent, pkt_sent, reclaimed; 3942 bool do_prefetch, rang, ring; 3943 3944 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3945 !LINK_ACTIVE(ctx))) { 3946 DBG_COUNTER_INC(txq_drain_notready); 3947 return (0); 3948 } 3949 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3950 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending); 3951 avail = IDXDIFF(pidx, cidx, r->size); 3952 3953 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3954 /* 3955 * The driver is unloading so we need to free all pending packets. 3956 */ 3957 DBG_COUNTER_INC(txq_drain_flushing); 3958 for (i = 0; i < avail; i++) { 3959 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3960 m_freem(r->items[(cidx + i) & (r->size-1)]); 3961 r->items[(cidx + i) & (r->size-1)] = NULL; 3962 } 3963 return (avail); 3964 } 3965 3966 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3967 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3968 CALLOUT_LOCK(txq); 3969 callout_stop(&txq->ift_timer); 3970 CALLOUT_UNLOCK(txq); 3971 DBG_COUNTER_INC(txq_drain_oactive); 3972 return (0); 3973 } 3974 3975 /* 3976 * If we've reclaimed any packets this queue cannot be hung. 3977 */ 3978 if (reclaimed) 3979 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3980 skipped = mcast_sent = bytes_sent = pkt_sent = 0; 3981 count = MIN(avail, TX_BATCH_SIZE); 3982 #ifdef INVARIANTS 3983 if (iflib_verbose_debug) 3984 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3985 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3986 #endif 3987 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3988 err = 0; 3989 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx) + 2; i++) { 3990 int rem = do_prefetch ? count - i : 0; 3991 3992 mp = _ring_peek_one(r, cidx, i, rem); 3993 MPASS(mp != NULL && *mp != NULL); 3994 3995 /* 3996 * Completion interrupts will use the address of the txq 3997 * as a sentinel to enqueue _something_ in order to acquire 3998 * the lock on the mp_ring (there's no direct lock call). 3999 * We obviously whave to check for these sentinel cases 4000 * and skip them. 4001 */ 4002 if (__predict_false(*mp == (struct mbuf *)txq)) { 4003 skipped++; 4004 continue; 4005 } 4006 err = iflib_encap(txq, mp); 4007 if (__predict_false(err)) { 4008 /* no room - bail out */ 4009 if (err == ENOBUFS) 4010 break; 4011 skipped++; 4012 /* we can't send this packet - skip it */ 4013 continue; 4014 } 4015 pkt_sent++; 4016 m = *mp; 4017 DBG_COUNTER_INC(tx_sent); 4018 bytes_sent += m->m_pkthdr.len; 4019 mcast_sent += !!(m->m_flags & M_MCAST); 4020 4021 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))) 4022 break; 4023 ETHER_BPF_MTAP(ifp, m); 4024 rang = iflib_txd_db_check(txq, false); 4025 } 4026 4027 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 4028 ring = rang ? false : (iflib_min_tx_latency | err); 4029 iflib_txd_db_check(txq, ring); 4030 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 4031 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 4032 if (mcast_sent) 4033 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 4034 #ifdef INVARIANTS 4035 if (iflib_verbose_debug) 4036 printf("consumed=%d\n", skipped + pkt_sent); 4037 #endif 4038 return (skipped + pkt_sent); 4039 } 4040 4041 static uint32_t 4042 iflib_txq_drain_always(struct ifmp_ring *r) 4043 { 4044 return (1); 4045 } 4046 4047 static uint32_t 4048 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 4049 { 4050 int i, avail; 4051 struct mbuf **mp; 4052 iflib_txq_t txq; 4053 4054 txq = r->cookie; 4055 4056 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 4057 CALLOUT_LOCK(txq); 4058 callout_stop(&txq->ift_timer); 4059 CALLOUT_UNLOCK(txq); 4060 4061 avail = IDXDIFF(pidx, cidx, r->size); 4062 for (i = 0; i < avail; i++) { 4063 mp = _ring_peek_one(r, cidx, i, avail - i); 4064 if (__predict_false(*mp == (struct mbuf *)txq)) 4065 continue; 4066 m_freem(*mp); 4067 DBG_COUNTER_INC(tx_frees); 4068 } 4069 MPASS(ifmp_ring_is_stalled(r) == 0); 4070 return (avail); 4071 } 4072 4073 static void 4074 iflib_ifmp_purge(iflib_txq_t txq) 4075 { 4076 struct ifmp_ring *r; 4077 4078 r = txq->ift_br; 4079 r->drain = iflib_txq_drain_free; 4080 r->can_drain = iflib_txq_drain_always; 4081 4082 ifmp_ring_check_drainage(r, r->size); 4083 4084 r->drain = iflib_txq_drain; 4085 r->can_drain = iflib_txq_can_drain; 4086 } 4087 4088 static void 4089 _task_fn_tx(void *context) 4090 { 4091 iflib_txq_t txq = context; 4092 if_ctx_t ctx = txq->ift_ctx; 4093 if_t ifp = ctx->ifc_ifp; 4094 int abdicate = ctx->ifc_sysctl_tx_abdicate; 4095 4096 #ifdef IFLIB_DIAGNOSTICS 4097 txq->ift_cpu_exec_count[curcpu]++; 4098 #endif 4099 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4100 return; 4101 #ifdef DEV_NETMAP 4102 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 4103 netmap_tx_irq(ifp, txq->ift_id)) 4104 goto skip_ifmp; 4105 #endif 4106 #ifdef ALTQ 4107 if (if_altq_is_enabled(ifp)) 4108 iflib_altq_if_start(ifp); 4109 #endif 4110 if (txq->ift_db_pending) 4111 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 4112 else if (!abdicate) 4113 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4114 /* 4115 * When abdicating, we always need to check drainage, not just when we don't enqueue 4116 */ 4117 if (abdicate) 4118 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4119 #ifdef DEV_NETMAP 4120 skip_ifmp: 4121 #endif 4122 if (ctx->ifc_flags & IFC_LEGACY) 4123 IFDI_INTR_ENABLE(ctx); 4124 else 4125 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 4126 } 4127 4128 static void 4129 _task_fn_rx(void *context) 4130 { 4131 iflib_rxq_t rxq = context; 4132 if_ctx_t ctx = rxq->ifr_ctx; 4133 uint8_t more; 4134 uint16_t budget; 4135 #ifdef DEV_NETMAP 4136 u_int work = 0; 4137 int nmirq; 4138 #endif 4139 4140 #ifdef IFLIB_DIAGNOSTICS 4141 rxq->ifr_cpu_exec_count[curcpu]++; 4142 #endif 4143 DBG_COUNTER_INC(task_fn_rxs); 4144 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4145 return; 4146 #ifdef DEV_NETMAP 4147 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 4148 if (nmirq != NM_IRQ_PASS) { 4149 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 4150 goto skip_rxeof; 4151 } 4152 #endif 4153 budget = ctx->ifc_sysctl_rx_budget; 4154 if (budget == 0) 4155 budget = 16; /* XXX */ 4156 more = iflib_rxeof(rxq, budget); 4157 #ifdef DEV_NETMAP 4158 skip_rxeof: 4159 #endif 4160 if ((more & IFLIB_RXEOF_MORE) == 0) { 4161 if (ctx->ifc_flags & IFC_LEGACY) 4162 IFDI_INTR_ENABLE(ctx); 4163 else 4164 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 4165 DBG_COUNTER_INC(rx_intr_enables); 4166 } 4167 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4168 return; 4169 4170 if (more & IFLIB_RXEOF_MORE) 4171 GROUPTASK_ENQUEUE(&rxq->ifr_task); 4172 else if (more & IFLIB_RXEOF_EMPTY) 4173 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 4174 } 4175 4176 static void 4177 _task_fn_admin(void *context) 4178 { 4179 if_ctx_t ctx = context; 4180 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 4181 iflib_txq_t txq; 4182 int i; 4183 bool oactive, running, do_reset, do_watchdog, in_detach; 4184 4185 STATE_LOCK(ctx); 4186 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 4187 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 4188 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 4189 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 4190 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 4191 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 4192 STATE_UNLOCK(ctx); 4193 4194 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4195 return; 4196 if (in_detach) 4197 return; 4198 4199 CTX_LOCK(ctx); 4200 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4201 CALLOUT_LOCK(txq); 4202 callout_stop(&txq->ift_timer); 4203 CALLOUT_UNLOCK(txq); 4204 } 4205 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ) 4206 IFDI_ADMIN_COMPLETION_HANDLE(ctx); 4207 if (do_watchdog) { 4208 ctx->ifc_watchdog_events++; 4209 IFDI_WATCHDOG_RESET(ctx); 4210 } 4211 IFDI_UPDATE_ADMIN_STATUS(ctx); 4212 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4213 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 4214 txq->ift_timer.c_cpu); 4215 } 4216 IFDI_LINK_INTR_ENABLE(ctx); 4217 if (do_reset) 4218 iflib_if_init_locked(ctx); 4219 CTX_UNLOCK(ctx); 4220 4221 if (LINK_ACTIVE(ctx) == 0) 4222 return; 4223 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 4224 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4225 } 4226 4227 static void 4228 _task_fn_iov(void *context) 4229 { 4230 if_ctx_t ctx = context; 4231 4232 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 4233 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4234 return; 4235 4236 CTX_LOCK(ctx); 4237 IFDI_VFLR_HANDLE(ctx); 4238 CTX_UNLOCK(ctx); 4239 } 4240 4241 static int 4242 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4243 { 4244 int err; 4245 if_int_delay_info_t info; 4246 if_ctx_t ctx; 4247 4248 info = (if_int_delay_info_t)arg1; 4249 ctx = info->iidi_ctx; 4250 info->iidi_req = req; 4251 info->iidi_oidp = oidp; 4252 CTX_LOCK(ctx); 4253 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 4254 CTX_UNLOCK(ctx); 4255 return (err); 4256 } 4257 4258 /********************************************************************* 4259 * 4260 * IFNET FUNCTIONS 4261 * 4262 **********************************************************************/ 4263 4264 static void 4265 iflib_if_init_locked(if_ctx_t ctx) 4266 { 4267 iflib_stop(ctx); 4268 iflib_init_locked(ctx); 4269 } 4270 4271 static void 4272 iflib_if_init(void *arg) 4273 { 4274 if_ctx_t ctx = arg; 4275 4276 CTX_LOCK(ctx); 4277 iflib_if_init_locked(ctx); 4278 CTX_UNLOCK(ctx); 4279 } 4280 4281 static int 4282 iflib_if_transmit(if_t ifp, struct mbuf *m) 4283 { 4284 if_ctx_t ctx = if_getsoftc(ifp); 4285 iflib_txq_t txq; 4286 int err, qidx; 4287 int abdicate; 4288 4289 if (__predict_false((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 4290 DBG_COUNTER_INC(tx_frees); 4291 m_freem(m); 4292 return (ENETDOWN); 4293 } 4294 4295 MPASS(m->m_nextpkt == NULL); 4296 /* ALTQ-enabled interfaces always use queue 0. */ 4297 qidx = 0; 4298 /* Use driver-supplied queue selection method if it exists */ 4299 if (ctx->isc_txq_select_v2) { 4300 struct if_pkt_info pi; 4301 uint64_t early_pullups = 0; 4302 pkt_info_zero(&pi); 4303 4304 err = iflib_parse_header_partial(&pi, &m, &early_pullups); 4305 if (__predict_false(err != 0)) { 4306 /* Assign pullups for bad pkts to default queue */ 4307 ctx->ifc_txqs[0].ift_pullups += early_pullups; 4308 DBG_COUNTER_INC(encap_txd_encap_fail); 4309 return (err); 4310 } 4311 /* Let driver make queueing decision */ 4312 qidx = ctx->isc_txq_select_v2(ctx->ifc_softc, m, &pi); 4313 ctx->ifc_txqs[qidx].ift_pullups += early_pullups; 4314 } 4315 /* Backwards compatibility w/ simpler queue select */ 4316 else if (ctx->isc_txq_select) 4317 qidx = ctx->isc_txq_select(ctx->ifc_softc, m); 4318 /* If not, use iflib's standard method */ 4319 else if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !if_altq_is_enabled(ifp)) 4320 qidx = QIDX(ctx, m); 4321 4322 /* Set TX queue */ 4323 txq = &ctx->ifc_txqs[qidx]; 4324 4325 #ifdef DRIVER_BACKPRESSURE 4326 if (txq->ift_closed) { 4327 while (m != NULL) { 4328 next = m->m_nextpkt; 4329 m->m_nextpkt = NULL; 4330 m_freem(m); 4331 DBG_COUNTER_INC(tx_frees); 4332 m = next; 4333 } 4334 return (ENOBUFS); 4335 } 4336 #endif 4337 #ifdef notyet 4338 qidx = count = 0; 4339 mp = marr; 4340 next = m; 4341 do { 4342 count++; 4343 next = next->m_nextpkt; 4344 } while (next != NULL); 4345 4346 if (count > nitems(marr)) 4347 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4348 /* XXX check nextpkt */ 4349 m_freem(m); 4350 /* XXX simplify for now */ 4351 DBG_COUNTER_INC(tx_frees); 4352 return (ENOBUFS); 4353 } 4354 for (next = m, i = 0; next != NULL; i++) { 4355 mp[i] = next; 4356 next = next->m_nextpkt; 4357 mp[i]->m_nextpkt = NULL; 4358 } 4359 #endif 4360 DBG_COUNTER_INC(tx_seen); 4361 abdicate = ctx->ifc_sysctl_tx_abdicate; 4362 4363 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4364 4365 if (abdicate) 4366 GROUPTASK_ENQUEUE(&txq->ift_task); 4367 if (err) { 4368 if (!abdicate) 4369 GROUPTASK_ENQUEUE(&txq->ift_task); 4370 /* support forthcoming later */ 4371 #ifdef DRIVER_BACKPRESSURE 4372 txq->ift_closed = TRUE; 4373 #endif 4374 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4375 m_freem(m); 4376 DBG_COUNTER_INC(tx_frees); 4377 } 4378 4379 return (err); 4380 } 4381 4382 #ifdef ALTQ 4383 /* 4384 * The overall approach to integrating iflib with ALTQ is to continue to use 4385 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4386 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4387 * is redundant/unnecessary, but doing so minimizes the amount of 4388 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4389 * redundantly queueing to an intermediate mp_ring is swamped by the 4390 * performance limitations inherent in using ALTQ. 4391 * 4392 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4393 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4394 * given interface. If ALTQ is enabled for an interface, then all 4395 * transmitted packets for that interface will be submitted to the ALTQ 4396 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4397 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4398 * update stats that the iflib machinery handles, and which is sensitve to 4399 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4400 * will be installed as the start routine for use by ALTQ facilities that 4401 * need to trigger queue drains on a scheduled basis. 4402 * 4403 */ 4404 static void 4405 iflib_altq_if_start(if_t ifp) 4406 { 4407 struct ifaltq *ifq = &ifp->if_snd; /* XXX - DRVAPI */ 4408 struct mbuf *m; 4409 4410 IFQ_LOCK(ifq); 4411 IFQ_DEQUEUE_NOLOCK(ifq, m); 4412 while (m != NULL) { 4413 iflib_if_transmit(ifp, m); 4414 IFQ_DEQUEUE_NOLOCK(ifq, m); 4415 } 4416 IFQ_UNLOCK(ifq); 4417 } 4418 4419 static int 4420 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4421 { 4422 int err; 4423 4424 if (if_altq_is_enabled(ifp)) { 4425 IFQ_ENQUEUE(&ifp->if_snd, m, err); /* XXX - DRVAPI */ 4426 if (err == 0) 4427 iflib_altq_if_start(ifp); 4428 } else 4429 err = iflib_if_transmit(ifp, m); 4430 4431 return (err); 4432 } 4433 #endif /* ALTQ */ 4434 4435 static void 4436 iflib_if_qflush(if_t ifp) 4437 { 4438 if_ctx_t ctx = if_getsoftc(ifp); 4439 iflib_txq_t txq = ctx->ifc_txqs; 4440 int i; 4441 4442 STATE_LOCK(ctx); 4443 ctx->ifc_flags |= IFC_QFLUSH; 4444 STATE_UNLOCK(ctx); 4445 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4446 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4447 iflib_txq_check_drain(txq, 0); 4448 STATE_LOCK(ctx); 4449 ctx->ifc_flags &= ~IFC_QFLUSH; 4450 STATE_UNLOCK(ctx); 4451 4452 /* 4453 * When ALTQ is enabled, this will also take care of purging the 4454 * ALTQ queue(s). 4455 */ 4456 if_qflush(ifp); 4457 } 4458 4459 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4460 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4461 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4462 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG) 4463 4464 static int 4465 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4466 { 4467 if_ctx_t ctx = if_getsoftc(ifp); 4468 struct ifreq *ifr = (struct ifreq *)data; 4469 #if defined(INET) || defined(INET6) 4470 struct ifaddr *ifa = (struct ifaddr *)data; 4471 #endif 4472 bool avoid_reset = false; 4473 int err = 0, reinit = 0, bits; 4474 4475 switch (command) { 4476 case SIOCSIFADDR: 4477 #ifdef INET 4478 if (ifa->ifa_addr->sa_family == AF_INET) 4479 avoid_reset = true; 4480 #endif 4481 #ifdef INET6 4482 if (ifa->ifa_addr->sa_family == AF_INET6) 4483 avoid_reset = true; 4484 #endif 4485 /* 4486 ** Calling init results in link renegotiation, 4487 ** so we avoid doing it when possible. 4488 */ 4489 if (avoid_reset) { 4490 if_setflagbits(ifp, IFF_UP,0); 4491 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4492 reinit = 1; 4493 #ifdef INET 4494 if (!(if_getflags(ifp) & IFF_NOARP)) 4495 arp_ifinit(ifp, ifa); 4496 #endif 4497 } else 4498 err = ether_ioctl(ifp, command, data); 4499 break; 4500 case SIOCSIFMTU: 4501 CTX_LOCK(ctx); 4502 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4503 CTX_UNLOCK(ctx); 4504 break; 4505 } 4506 bits = if_getdrvflags(ifp); 4507 /* stop the driver and free any clusters before proceeding */ 4508 iflib_stop(ctx); 4509 4510 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4511 STATE_LOCK(ctx); 4512 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4513 ctx->ifc_flags |= IFC_MULTISEG; 4514 else 4515 ctx->ifc_flags &= ~IFC_MULTISEG; 4516 STATE_UNLOCK(ctx); 4517 err = if_setmtu(ifp, ifr->ifr_mtu); 4518 } 4519 iflib_init_locked(ctx); 4520 STATE_LOCK(ctx); 4521 if_setdrvflags(ifp, bits); 4522 STATE_UNLOCK(ctx); 4523 CTX_UNLOCK(ctx); 4524 break; 4525 case SIOCSIFFLAGS: 4526 CTX_LOCK(ctx); 4527 if (if_getflags(ifp) & IFF_UP) { 4528 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4529 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4530 (IFF_PROMISC | IFF_ALLMULTI)) { 4531 CTX_UNLOCK(ctx); 4532 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4533 CTX_LOCK(ctx); 4534 } 4535 } else 4536 reinit = 1; 4537 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4538 iflib_stop(ctx); 4539 } 4540 ctx->ifc_if_flags = if_getflags(ifp); 4541 CTX_UNLOCK(ctx); 4542 break; 4543 case SIOCADDMULTI: 4544 case SIOCDELMULTI: 4545 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4546 CTX_LOCK(ctx); 4547 IFDI_INTR_DISABLE(ctx); 4548 IFDI_MULTI_SET(ctx); 4549 IFDI_INTR_ENABLE(ctx); 4550 CTX_UNLOCK(ctx); 4551 } 4552 break; 4553 case SIOCSIFMEDIA: 4554 CTX_LOCK(ctx); 4555 IFDI_MEDIA_SET(ctx); 4556 CTX_UNLOCK(ctx); 4557 /* FALLTHROUGH */ 4558 case SIOCGIFMEDIA: 4559 case SIOCGIFXMEDIA: 4560 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4561 break; 4562 case SIOCGI2C: 4563 { 4564 struct ifi2creq i2c; 4565 4566 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4567 if (err != 0) 4568 break; 4569 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4570 err = EINVAL; 4571 break; 4572 } 4573 if (i2c.len > sizeof(i2c.data)) { 4574 err = EINVAL; 4575 break; 4576 } 4577 4578 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4579 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4580 sizeof(i2c)); 4581 break; 4582 } 4583 case SIOCSIFCAP: 4584 { 4585 int mask, setmask, oldmask; 4586 4587 oldmask = if_getcapenable(ifp); 4588 mask = ifr->ifr_reqcap ^ oldmask; 4589 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG; 4590 setmask = 0; 4591 #ifdef TCP_OFFLOAD 4592 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4593 #endif 4594 setmask |= (mask & IFCAP_FLAGS); 4595 setmask |= (mask & IFCAP_WOL); 4596 4597 /* 4598 * If any RX csum has changed, change all the ones that 4599 * are supported by the driver. 4600 */ 4601 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4602 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4603 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4604 } 4605 4606 /* 4607 * want to ensure that traffic has stopped before we change any of the flags 4608 */ 4609 if (setmask) { 4610 CTX_LOCK(ctx); 4611 bits = if_getdrvflags(ifp); 4612 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4613 iflib_stop(ctx); 4614 STATE_LOCK(ctx); 4615 if_togglecapenable(ifp, setmask); 4616 ctx->ifc_softc_ctx.isc_capenable ^= setmask; 4617 STATE_UNLOCK(ctx); 4618 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4619 iflib_init_locked(ctx); 4620 STATE_LOCK(ctx); 4621 if_setdrvflags(ifp, bits); 4622 STATE_UNLOCK(ctx); 4623 CTX_UNLOCK(ctx); 4624 } 4625 if_vlancap(ifp); 4626 break; 4627 } 4628 case SIOCGPRIVATE_0: 4629 case SIOCSDRVSPEC: 4630 case SIOCGDRVSPEC: 4631 CTX_LOCK(ctx); 4632 err = IFDI_PRIV_IOCTL(ctx, command, data); 4633 CTX_UNLOCK(ctx); 4634 break; 4635 default: 4636 err = ether_ioctl(ifp, command, data); 4637 break; 4638 } 4639 if (reinit) 4640 iflib_if_init(ctx); 4641 return (err); 4642 } 4643 4644 static uint64_t 4645 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4646 { 4647 if_ctx_t ctx = if_getsoftc(ifp); 4648 4649 return (IFDI_GET_COUNTER(ctx, cnt)); 4650 } 4651 4652 /********************************************************************* 4653 * 4654 * OTHER FUNCTIONS EXPORTED TO THE STACK 4655 * 4656 **********************************************************************/ 4657 4658 static void 4659 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4660 { 4661 if_ctx_t ctx = if_getsoftc(ifp); 4662 4663 if ((void *)ctx != arg) 4664 return; 4665 4666 if ((vtag == 0) || (vtag > 4095)) 4667 return; 4668 4669 if (iflib_in_detach(ctx)) 4670 return; 4671 4672 CTX_LOCK(ctx); 4673 /* Driver may need all untagged packets to be flushed */ 4674 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4675 iflib_stop(ctx); 4676 IFDI_VLAN_REGISTER(ctx, vtag); 4677 /* Re-init to load the changes, if required */ 4678 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4679 iflib_init_locked(ctx); 4680 CTX_UNLOCK(ctx); 4681 } 4682 4683 static void 4684 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4685 { 4686 if_ctx_t ctx = if_getsoftc(ifp); 4687 4688 if ((void *)ctx != arg) 4689 return; 4690 4691 if ((vtag == 0) || (vtag > 4095)) 4692 return; 4693 4694 CTX_LOCK(ctx); 4695 /* Driver may need all tagged packets to be flushed */ 4696 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4697 iflib_stop(ctx); 4698 IFDI_VLAN_UNREGISTER(ctx, vtag); 4699 /* Re-init to load the changes, if required */ 4700 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4701 iflib_init_locked(ctx); 4702 CTX_UNLOCK(ctx); 4703 } 4704 4705 static void 4706 iflib_led_func(void *arg, int onoff) 4707 { 4708 if_ctx_t ctx = arg; 4709 4710 CTX_LOCK(ctx); 4711 IFDI_LED_FUNC(ctx, onoff); 4712 CTX_UNLOCK(ctx); 4713 } 4714 4715 /********************************************************************* 4716 * 4717 * BUS FUNCTION DEFINITIONS 4718 * 4719 **********************************************************************/ 4720 4721 int 4722 iflib_device_probe(device_t dev) 4723 { 4724 const pci_vendor_info_t *ent; 4725 if_shared_ctx_t sctx; 4726 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4727 uint16_t pci_vendor_id; 4728 4729 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4730 return (ENOTSUP); 4731 4732 pci_vendor_id = pci_get_vendor(dev); 4733 pci_device_id = pci_get_device(dev); 4734 pci_subvendor_id = pci_get_subvendor(dev); 4735 pci_subdevice_id = pci_get_subdevice(dev); 4736 pci_rev_id = pci_get_revid(dev); 4737 if (sctx->isc_parse_devinfo != NULL) 4738 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4739 4740 ent = sctx->isc_vendor_info; 4741 while (ent->pvi_vendor_id != 0) { 4742 if (pci_vendor_id != ent->pvi_vendor_id) { 4743 ent++; 4744 continue; 4745 } 4746 if ((pci_device_id == ent->pvi_device_id) && 4747 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4748 (ent->pvi_subvendor_id == 0)) && 4749 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4750 (ent->pvi_subdevice_id == 0)) && 4751 ((pci_rev_id == ent->pvi_rev_id) || 4752 (ent->pvi_rev_id == 0))) { 4753 device_set_desc_copy(dev, ent->pvi_name); 4754 /* this needs to be changed to zero if the bus probing code 4755 * ever stops re-probing on best match because the sctx 4756 * may have its values over written by register calls 4757 * in subsequent probes 4758 */ 4759 return (BUS_PROBE_DEFAULT); 4760 } 4761 ent++; 4762 } 4763 return (ENXIO); 4764 } 4765 4766 int 4767 iflib_device_probe_vendor(device_t dev) 4768 { 4769 int probe; 4770 4771 probe = iflib_device_probe(dev); 4772 if (probe == BUS_PROBE_DEFAULT) 4773 return (BUS_PROBE_VENDOR); 4774 else 4775 return (probe); 4776 } 4777 4778 static void 4779 iflib_reset_qvalues(if_ctx_t ctx) 4780 { 4781 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4782 if_shared_ctx_t sctx = ctx->ifc_sctx; 4783 device_t dev = ctx->ifc_dev; 4784 int i; 4785 4786 if (ctx->ifc_sysctl_ntxqs != 0) 4787 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4788 if (ctx->ifc_sysctl_nrxqs != 0) 4789 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4790 4791 for (i = 0; i < sctx->isc_ntxqs; i++) { 4792 if (ctx->ifc_sysctl_ntxds[i] != 0) 4793 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4794 else 4795 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4796 } 4797 4798 for (i = 0; i < sctx->isc_nrxqs; i++) { 4799 if (ctx->ifc_sysctl_nrxds[i] != 0) 4800 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4801 else 4802 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4803 } 4804 4805 for (i = 0; i < sctx->isc_nrxqs; i++) { 4806 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4807 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4808 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4809 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4810 } 4811 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4812 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4813 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4814 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4815 } 4816 if (!powerof2(scctx->isc_nrxd[i])) { 4817 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4818 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4819 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4820 } 4821 } 4822 4823 for (i = 0; i < sctx->isc_ntxqs; i++) { 4824 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4825 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4826 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4827 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4828 } 4829 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4830 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4831 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4832 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4833 } 4834 if (!powerof2(scctx->isc_ntxd[i])) { 4835 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4836 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4837 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4838 } 4839 } 4840 } 4841 4842 static void 4843 iflib_add_pfil(if_ctx_t ctx) 4844 { 4845 struct pfil_head *pfil; 4846 struct pfil_head_args pa; 4847 iflib_rxq_t rxq; 4848 int i; 4849 4850 pa.pa_version = PFIL_VERSION; 4851 pa.pa_flags = PFIL_IN; 4852 pa.pa_type = PFIL_TYPE_ETHERNET; 4853 pa.pa_headname = if_name(ctx->ifc_ifp); 4854 pfil = pfil_head_register(&pa); 4855 4856 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4857 rxq->pfil = pfil; 4858 } 4859 } 4860 4861 static void 4862 iflib_rem_pfil(if_ctx_t ctx) 4863 { 4864 struct pfil_head *pfil; 4865 iflib_rxq_t rxq; 4866 int i; 4867 4868 rxq = ctx->ifc_rxqs; 4869 pfil = rxq->pfil; 4870 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4871 rxq->pfil = NULL; 4872 } 4873 pfil_head_unregister(pfil); 4874 } 4875 4876 4877 /* 4878 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from 4879 * cpuid and wrapping as necessary. 4880 */ 4881 static unsigned int 4882 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n) 4883 { 4884 unsigned int first_valid; 4885 unsigned int last_valid; 4886 4887 /* cpuid should always be in the valid set */ 4888 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4889 4890 /* valid set should never be empty */ 4891 MPASS(!CPU_EMPTY(&ctx->ifc_cpus)); 4892 4893 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4894 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4895 n = n % CPU_COUNT(&ctx->ifc_cpus); 4896 while (n > 0) { 4897 do { 4898 cpuid++; 4899 if (cpuid > last_valid) 4900 cpuid = first_valid; 4901 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4902 n--; 4903 } 4904 4905 return (cpuid); 4906 } 4907 4908 #if defined(SMP) && defined(SCHED_ULE) 4909 extern struct cpu_group *cpu_top; /* CPU topology */ 4910 4911 static int 4912 find_child_with_core(int cpu, struct cpu_group *grp) 4913 { 4914 int i; 4915 4916 if (grp->cg_children == 0) 4917 return -1; 4918 4919 MPASS(grp->cg_child); 4920 for (i = 0; i < grp->cg_children; i++) { 4921 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 4922 return i; 4923 } 4924 4925 return -1; 4926 } 4927 4928 4929 /* 4930 * Find an L2 neighbor of the given CPU or return -1 if none found. This 4931 * does not distinguish among multiple L2 neighbors if the given CPU has 4932 * more than one (it will always return the same result in that case). 4933 */ 4934 static int 4935 find_l2_neighbor(int cpu) 4936 { 4937 struct cpu_group *grp; 4938 int i; 4939 4940 grp = cpu_top; 4941 if (grp == NULL) 4942 return -1; 4943 4944 /* 4945 * Find the smallest CPU group that contains the given core. 4946 */ 4947 i = 0; 4948 while ((i = find_child_with_core(cpu, grp)) != -1) { 4949 /* 4950 * If the smallest group containing the given CPU has less 4951 * than two members, we conclude the given CPU has no 4952 * L2 neighbor. 4953 */ 4954 if (grp->cg_child[i].cg_count <= 1) 4955 return (-1); 4956 grp = &grp->cg_child[i]; 4957 } 4958 4959 /* Must share L2. */ 4960 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 4961 return -1; 4962 4963 /* 4964 * Select the first member of the set that isn't the reference 4965 * CPU, which at this point is guaranteed to exist. 4966 */ 4967 for (i = 0; i < CPU_SETSIZE; i++) { 4968 if (CPU_ISSET(i, &grp->cg_mask) && i != cpu) 4969 return (i); 4970 } 4971 4972 /* Should never be reached */ 4973 return (-1); 4974 } 4975 4976 #else 4977 static int 4978 find_l2_neighbor(int cpu) 4979 { 4980 4981 return (-1); 4982 } 4983 #endif 4984 4985 /* 4986 * CPU mapping behaviors 4987 * --------------------- 4988 * 'separate txrx' refers to the separate_txrx sysctl 4989 * 'use logical' refers to the use_logical_cores sysctl 4990 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded 4991 * 4992 * separate use INTR 4993 * txrx logical CPUS result 4994 * ---------- --------- ------ ------------------------------------------------ 4995 * - - X RX and TX queues mapped to consecutive physical 4996 * cores with RX/TX pairs on same core and excess 4997 * of either following 4998 * - X X RX and TX queues mapped to consecutive cores 4999 * of any type with RX/TX pairs on same core and 5000 * excess of either following 5001 * X - X RX and TX queues mapped to consecutive physical 5002 * cores; all RX then all TX 5003 * X X X RX queues mapped to consecutive physical cores 5004 * first, then TX queues mapped to L2 neighbor of 5005 * the corresponding RX queue if one exists, 5006 * otherwise to consecutive physical cores 5007 * - n/a - RX and TX queues mapped to consecutive cores of 5008 * any type with RX/TX pairs on same core and excess 5009 * of either following 5010 * X n/a - RX and TX queues mapped to consecutive cores of 5011 * any type; all RX then all TX 5012 */ 5013 static unsigned int 5014 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid, 5015 bool is_tx) 5016 { 5017 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5018 unsigned int core_index; 5019 5020 if (ctx->ifc_sysctl_separate_txrx) { 5021 /* 5022 * When using separate CPUs for TX and RX, the assignment 5023 * will always be of a consecutive CPU out of the set of 5024 * context CPUs, except for the specific case where the 5025 * context CPUs are phsyical cores, the use of logical cores 5026 * has been enabled, the assignment is for TX, the TX qid 5027 * corresponds to an RX qid, and the CPU assigned to the 5028 * corresponding RX queue has an L2 neighbor. 5029 */ 5030 if (ctx->ifc_sysctl_use_logical_cores && 5031 ctx->ifc_cpus_are_physical_cores && 5032 is_tx && qid < scctx->isc_nrxqsets) { 5033 int l2_neighbor; 5034 unsigned int rx_cpuid; 5035 5036 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid); 5037 l2_neighbor = find_l2_neighbor(rx_cpuid); 5038 if (l2_neighbor != -1) { 5039 return (l2_neighbor); 5040 } 5041 /* 5042 * ... else fall through to the normal 5043 * consecutive-after-RX assignment scheme. 5044 * 5045 * Note that we are assuming that all RX queue CPUs 5046 * have an L2 neighbor, or all do not. If a mixed 5047 * scenario is possible, we will have to keep track 5048 * separately of how many queues prior to this one 5049 * were not able to be assigned to an L2 neighbor. 5050 */ 5051 } 5052 if (is_tx) 5053 core_index = scctx->isc_nrxqsets + qid; 5054 else 5055 core_index = qid; 5056 } else { 5057 core_index = qid; 5058 } 5059 5060 return (cpuid_advance(ctx, base_cpuid, core_index)); 5061 } 5062 5063 static uint16_t 5064 get_ctx_core_offset(if_ctx_t ctx) 5065 { 5066 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5067 struct cpu_offset *op; 5068 cpuset_t assigned_cpus; 5069 unsigned int cores_consumed; 5070 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset; 5071 unsigned int first_valid; 5072 unsigned int last_valid; 5073 unsigned int i; 5074 5075 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 5076 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 5077 5078 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) { 5079 /* 5080 * Align the user-chosen base CPU ID to the next valid CPU 5081 * for this device. If the chosen base CPU ID is smaller 5082 * than the first valid CPU or larger than the last valid 5083 * CPU, we assume the user does not know what the valid 5084 * range is for this device and is thinking in terms of a 5085 * zero-based reference frame, and so we shift the given 5086 * value into the valid range (and wrap accordingly) so the 5087 * intent is translated to the proper frame of reference. 5088 * If the base CPU ID is within the valid first/last, but 5089 * does not correspond to a valid CPU, it is advanced to the 5090 * next valid CPU (wrapping if necessary). 5091 */ 5092 if (base_cpuid < first_valid || base_cpuid > last_valid) { 5093 /* shift from zero-based to first_valid-based */ 5094 base_cpuid += first_valid; 5095 /* wrap to range [first_valid, last_valid] */ 5096 base_cpuid = (base_cpuid - first_valid) % 5097 (last_valid - first_valid + 1); 5098 } 5099 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) { 5100 /* 5101 * base_cpuid is in [first_valid, last_valid], but 5102 * not a member of the valid set. In this case, 5103 * there will always be a member of the valid set 5104 * with a CPU ID that is greater than base_cpuid, 5105 * and we simply advance to it. 5106 */ 5107 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) 5108 base_cpuid++; 5109 } 5110 return (base_cpuid); 5111 } 5112 5113 /* 5114 * Determine how many cores will be consumed by performing the CPU 5115 * assignments and counting how many of the assigned CPUs correspond 5116 * to CPUs in the set of context CPUs. This is done using the CPU 5117 * ID first_valid as the base CPU ID, as the base CPU must be within 5118 * the set of context CPUs. 5119 * 5120 * Note not all assigned CPUs will be in the set of context CPUs 5121 * when separate CPUs are being allocated to TX and RX queues, 5122 * assignment to logical cores has been enabled, the set of context 5123 * CPUs contains only physical CPUs, and TX queues are mapped to L2 5124 * neighbors of CPUs that RX queues have been mapped to - in this 5125 * case we do only want to count how many CPUs in the set of context 5126 * CPUs have been consumed, as that determines the next CPU in that 5127 * set to start allocating at for the next device for which 5128 * core_offset is not set. 5129 */ 5130 CPU_ZERO(&assigned_cpus); 5131 for (i = 0; i < scctx->isc_ntxqsets; i++) 5132 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true), 5133 &assigned_cpus); 5134 for (i = 0; i < scctx->isc_nrxqsets; i++) 5135 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false), 5136 &assigned_cpus); 5137 CPU_AND(&assigned_cpus, &assigned_cpus, &ctx->ifc_cpus); 5138 cores_consumed = CPU_COUNT(&assigned_cpus); 5139 5140 mtx_lock(&cpu_offset_mtx); 5141 SLIST_FOREACH(op, &cpu_offsets, entries) { 5142 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5143 base_cpuid = op->next_cpuid; 5144 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid, 5145 cores_consumed); 5146 MPASS(op->refcount < UINT_MAX); 5147 op->refcount++; 5148 break; 5149 } 5150 } 5151 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) { 5152 base_cpuid = first_valid; 5153 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 5154 M_NOWAIT | M_ZERO); 5155 if (op == NULL) { 5156 device_printf(ctx->ifc_dev, 5157 "allocation for cpu offset failed.\n"); 5158 } else { 5159 op->next_cpuid = cpuid_advance(ctx, base_cpuid, 5160 cores_consumed); 5161 op->refcount = 1; 5162 CPU_COPY(&ctx->ifc_cpus, &op->set); 5163 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 5164 } 5165 } 5166 mtx_unlock(&cpu_offset_mtx); 5167 5168 return (base_cpuid); 5169 } 5170 5171 static void 5172 unref_ctx_core_offset(if_ctx_t ctx) 5173 { 5174 struct cpu_offset *op, *top; 5175 5176 mtx_lock(&cpu_offset_mtx); 5177 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 5178 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5179 MPASS(op->refcount > 0); 5180 op->refcount--; 5181 if (op->refcount == 0) { 5182 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 5183 free(op, M_IFLIB); 5184 } 5185 break; 5186 } 5187 } 5188 mtx_unlock(&cpu_offset_mtx); 5189 } 5190 5191 int 5192 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 5193 { 5194 if_ctx_t ctx; 5195 if_t ifp; 5196 if_softc_ctx_t scctx; 5197 kobjop_desc_t kobj_desc; 5198 kobj_method_t *kobj_method; 5199 int err, msix, rid; 5200 int num_txd, num_rxd; 5201 5202 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 5203 5204 if (sc == NULL) { 5205 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 5206 device_set_softc(dev, ctx); 5207 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5208 } 5209 5210 ctx->ifc_sctx = sctx; 5211 ctx->ifc_dev = dev; 5212 ctx->ifc_softc = sc; 5213 5214 if ((err = iflib_register(ctx)) != 0) { 5215 device_printf(dev, "iflib_register failed %d\n", err); 5216 goto fail_ctx_free; 5217 } 5218 iflib_add_device_sysctl_pre(ctx); 5219 5220 scctx = &ctx->ifc_softc_ctx; 5221 ifp = ctx->ifc_ifp; 5222 5223 iflib_reset_qvalues(ctx); 5224 IFNET_WLOCK(); 5225 CTX_LOCK(ctx); 5226 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5227 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5228 goto fail_unlock; 5229 } 5230 _iflib_pre_assert(scctx); 5231 ctx->ifc_txrx = *scctx->isc_txrx; 5232 5233 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR)); 5234 5235 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 5236 ctx->ifc_mediap = scctx->isc_media; 5237 5238 #ifdef INVARIANTS 5239 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5240 MPASS(scctx->isc_tx_csum_flags); 5241 #endif 5242 5243 if_setcapabilities(ifp, 5244 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG); 5245 if_setcapenable(ifp, 5246 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG); 5247 5248 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5249 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5250 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5251 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5252 5253 num_txd = iflib_num_tx_descs(ctx); 5254 num_rxd = iflib_num_rx_descs(ctx); 5255 5256 /* XXX change for per-queue sizes */ 5257 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5258 num_txd, num_rxd); 5259 5260 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5261 scctx->isc_tx_nsegments = max(1, num_txd / 5262 MAX_SINGLE_PACKET_FRACTION); 5263 if (scctx->isc_tx_tso_segments_max > num_txd / 5264 MAX_SINGLE_PACKET_FRACTION) 5265 scctx->isc_tx_tso_segments_max = max(1, 5266 num_txd / MAX_SINGLE_PACKET_FRACTION); 5267 5268 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5269 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5270 /* 5271 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5272 * but some MACs do. 5273 */ 5274 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5275 IP_MAXPACKET)); 5276 /* 5277 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5278 * into account. In the worst case, each of these calls will 5279 * add another mbuf and, thus, the requirement for another DMA 5280 * segment. So for best performance, it doesn't make sense to 5281 * advertize a maximum of TSO segments that typically will 5282 * require defragmentation in iflib_encap(). 5283 */ 5284 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5285 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5286 } 5287 if (scctx->isc_rss_table_size == 0) 5288 scctx->isc_rss_table_size = 64; 5289 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5290 5291 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5292 /* XXX format name */ 5293 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5294 NULL, NULL, "admin"); 5295 5296 /* Set up cpu set. If it fails, use the set of all CPUs. */ 5297 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 5298 device_printf(dev, "Unable to fetch CPU list\n"); 5299 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 5300 ctx->ifc_cpus_are_physical_cores = false; 5301 } else 5302 ctx->ifc_cpus_are_physical_cores = true; 5303 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 5304 5305 /* 5306 ** Now set up MSI or MSI-X, should return us the number of supported 5307 ** vectors (will be 1 for a legacy interrupt and MSI). 5308 */ 5309 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 5310 msix = scctx->isc_vectors; 5311 } else if (scctx->isc_msix_bar != 0) 5312 /* 5313 * The simple fact that isc_msix_bar is not 0 does not mean we 5314 * we have a good value there that is known to work. 5315 */ 5316 msix = iflib_msix_init(ctx); 5317 else { 5318 scctx->isc_vectors = 1; 5319 scctx->isc_ntxqsets = 1; 5320 scctx->isc_nrxqsets = 1; 5321 scctx->isc_intr = IFLIB_INTR_LEGACY; 5322 msix = 0; 5323 } 5324 /* Get memory for the station queues */ 5325 if ((err = iflib_queues_alloc(ctx))) { 5326 device_printf(dev, "Unable to allocate queue memory\n"); 5327 goto fail_intr_free; 5328 } 5329 5330 if ((err = iflib_qset_structures_setup(ctx))) 5331 goto fail_queues; 5332 5333 /* 5334 * Now that we know how many queues there are, get the core offset. 5335 */ 5336 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 5337 5338 if (msix > 1) { 5339 /* 5340 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 5341 * aren't the default NULL implementation. 5342 */ 5343 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 5344 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5345 kobj_desc); 5346 if (kobj_method == &kobj_desc->deflt) { 5347 device_printf(dev, 5348 "MSI-X requires ifdi_rx_queue_intr_enable method"); 5349 err = EOPNOTSUPP; 5350 goto fail_queues; 5351 } 5352 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 5353 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5354 kobj_desc); 5355 if (kobj_method == &kobj_desc->deflt) { 5356 device_printf(dev, 5357 "MSI-X requires ifdi_tx_queue_intr_enable method"); 5358 err = EOPNOTSUPP; 5359 goto fail_queues; 5360 } 5361 5362 /* 5363 * Assign the MSI-X vectors. 5364 * Note that the default NULL ifdi_msix_intr_assign method will 5365 * fail here, too. 5366 */ 5367 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 5368 if (err != 0) { 5369 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 5370 err); 5371 goto fail_queues; 5372 } 5373 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 5374 rid = 0; 5375 if (scctx->isc_intr == IFLIB_INTR_MSI) { 5376 MPASS(msix == 1); 5377 rid = 1; 5378 } 5379 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 5380 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 5381 goto fail_queues; 5382 } 5383 } else { 5384 device_printf(dev, 5385 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 5386 err = ENODEV; 5387 goto fail_queues; 5388 } 5389 5390 /* 5391 * It prevents a double-locking panic with iflib_media_status when 5392 * the driver loads. 5393 */ 5394 CTX_UNLOCK(ctx); 5395 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5396 CTX_LOCK(ctx); 5397 5398 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5399 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5400 goto fail_detach; 5401 } 5402 5403 /* 5404 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5405 * This must appear after the call to ether_ifattach() because 5406 * ether_ifattach() sets if_hdrlen to the default value. 5407 */ 5408 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5409 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5410 5411 if ((err = iflib_netmap_attach(ctx))) { 5412 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 5413 goto fail_detach; 5414 } 5415 *ctxp = ctx; 5416 5417 DEBUGNET_SET(ctx->ifc_ifp, iflib); 5418 5419 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5420 iflib_add_device_sysctl_post(ctx); 5421 iflib_add_pfil(ctx); 5422 ctx->ifc_flags |= IFC_INIT_DONE; 5423 CTX_UNLOCK(ctx); 5424 IFNET_WUNLOCK(); 5425 5426 return (0); 5427 5428 fail_detach: 5429 ether_ifdetach(ctx->ifc_ifp); 5430 fail_queues: 5431 iflib_tqg_detach(ctx); 5432 iflib_tx_structures_free(ctx); 5433 iflib_rx_structures_free(ctx); 5434 IFDI_DETACH(ctx); 5435 IFDI_QUEUES_FREE(ctx); 5436 fail_intr_free: 5437 iflib_free_intr_mem(ctx); 5438 fail_unlock: 5439 CTX_UNLOCK(ctx); 5440 IFNET_WUNLOCK(); 5441 iflib_deregister(ctx); 5442 fail_ctx_free: 5443 device_set_softc(ctx->ifc_dev, NULL); 5444 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5445 free(ctx->ifc_softc, M_IFLIB); 5446 free(ctx, M_IFLIB); 5447 return (err); 5448 } 5449 5450 int 5451 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 5452 struct iflib_cloneattach_ctx *clctx) 5453 { 5454 int num_txd, num_rxd; 5455 int err; 5456 if_ctx_t ctx; 5457 if_t ifp; 5458 if_softc_ctx_t scctx; 5459 int i; 5460 void *sc; 5461 5462 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 5463 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 5464 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5465 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 5466 ctx->ifc_flags |= IFC_PSEUDO; 5467 5468 ctx->ifc_sctx = sctx; 5469 ctx->ifc_softc = sc; 5470 ctx->ifc_dev = dev; 5471 5472 if ((err = iflib_register(ctx)) != 0) { 5473 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 5474 goto fail_ctx_free; 5475 } 5476 iflib_add_device_sysctl_pre(ctx); 5477 5478 scctx = &ctx->ifc_softc_ctx; 5479 ifp = ctx->ifc_ifp; 5480 5481 iflib_reset_qvalues(ctx); 5482 CTX_LOCK(ctx); 5483 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5484 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5485 goto fail_unlock; 5486 } 5487 if (sctx->isc_flags & IFLIB_GEN_MAC) 5488 ether_gen_addr(ifp, &ctx->ifc_mac); 5489 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 5490 clctx->cc_params)) != 0) { 5491 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 5492 goto fail_unlock; 5493 } 5494 #ifdef INVARIANTS 5495 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5496 MPASS(scctx->isc_tx_csum_flags); 5497 #endif 5498 5499 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 5500 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 5501 5502 if_setflagbits(ifp, IFF_NOGROUP, 0); 5503 if (sctx->isc_flags & IFLIB_PSEUDO) { 5504 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 5505 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 5506 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) { 5507 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5508 } else { 5509 if_attach(ctx->ifc_ifp); 5510 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t)); 5511 } 5512 5513 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5514 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5515 goto fail_detach; 5516 } 5517 *ctxp = ctx; 5518 5519 /* 5520 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5521 * This must appear after the call to ether_ifattach() because 5522 * ether_ifattach() sets if_hdrlen to the default value. 5523 */ 5524 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5525 if_setifheaderlen(ifp, 5526 sizeof(struct ether_vlan_header)); 5527 5528 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5529 iflib_add_device_sysctl_post(ctx); 5530 ctx->ifc_flags |= IFC_INIT_DONE; 5531 CTX_UNLOCK(ctx); 5532 return (0); 5533 } 5534 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 5535 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 5536 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 5537 5538 _iflib_pre_assert(scctx); 5539 ctx->ifc_txrx = *scctx->isc_txrx; 5540 5541 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5542 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5543 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5544 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5545 5546 num_txd = iflib_num_tx_descs(ctx); 5547 num_rxd = iflib_num_rx_descs(ctx); 5548 5549 /* XXX change for per-queue sizes */ 5550 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5551 num_txd, num_rxd); 5552 5553 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5554 scctx->isc_tx_nsegments = max(1, num_txd / 5555 MAX_SINGLE_PACKET_FRACTION); 5556 if (scctx->isc_tx_tso_segments_max > num_txd / 5557 MAX_SINGLE_PACKET_FRACTION) 5558 scctx->isc_tx_tso_segments_max = max(1, 5559 num_txd / MAX_SINGLE_PACKET_FRACTION); 5560 5561 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5562 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5563 /* 5564 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5565 * but some MACs do. 5566 */ 5567 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5568 IP_MAXPACKET)); 5569 /* 5570 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5571 * into account. In the worst case, each of these calls will 5572 * add another mbuf and, thus, the requirement for another DMA 5573 * segment. So for best performance, it doesn't make sense to 5574 * advertize a maximum of TSO segments that typically will 5575 * require defragmentation in iflib_encap(). 5576 */ 5577 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5578 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5579 } 5580 if (scctx->isc_rss_table_size == 0) 5581 scctx->isc_rss_table_size = 64; 5582 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5583 5584 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5585 /* XXX format name */ 5586 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5587 NULL, NULL, "admin"); 5588 5589 /* XXX --- can support > 1 -- but keep it simple for now */ 5590 scctx->isc_intr = IFLIB_INTR_LEGACY; 5591 5592 /* Get memory for the station queues */ 5593 if ((err = iflib_queues_alloc(ctx))) { 5594 device_printf(dev, "Unable to allocate queue memory\n"); 5595 goto fail_iflib_detach; 5596 } 5597 5598 if ((err = iflib_qset_structures_setup(ctx))) { 5599 device_printf(dev, "qset structure setup failed %d\n", err); 5600 goto fail_queues; 5601 } 5602 5603 /* 5604 * XXX What if anything do we want to do about interrupts? 5605 */ 5606 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5607 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5608 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5609 goto fail_detach; 5610 } 5611 5612 /* 5613 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5614 * This must appear after the call to ether_ifattach() because 5615 * ether_ifattach() sets if_hdrlen to the default value. 5616 */ 5617 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5618 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5619 5620 /* XXX handle more than one queue */ 5621 for (i = 0; i < scctx->isc_nrxqsets; i++) 5622 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 5623 5624 *ctxp = ctx; 5625 5626 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5627 iflib_add_device_sysctl_post(ctx); 5628 ctx->ifc_flags |= IFC_INIT_DONE; 5629 CTX_UNLOCK(ctx); 5630 5631 return (0); 5632 fail_detach: 5633 ether_ifdetach(ctx->ifc_ifp); 5634 fail_queues: 5635 iflib_tqg_detach(ctx); 5636 iflib_tx_structures_free(ctx); 5637 iflib_rx_structures_free(ctx); 5638 fail_iflib_detach: 5639 IFDI_DETACH(ctx); 5640 IFDI_QUEUES_FREE(ctx); 5641 fail_unlock: 5642 CTX_UNLOCK(ctx); 5643 iflib_deregister(ctx); 5644 fail_ctx_free: 5645 free(ctx->ifc_softc, M_IFLIB); 5646 free(ctx, M_IFLIB); 5647 return (err); 5648 } 5649 5650 int 5651 iflib_pseudo_deregister(if_ctx_t ctx) 5652 { 5653 if_t ifp = ctx->ifc_ifp; 5654 if_shared_ctx_t sctx = ctx->ifc_sctx; 5655 5656 /* Unregister VLAN event handlers early */ 5657 iflib_unregister_vlan_handlers(ctx); 5658 5659 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5660 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) { 5661 bpfdetach(ifp); 5662 if_detach(ifp); 5663 } else { 5664 ether_ifdetach(ifp); 5665 } 5666 5667 iflib_tqg_detach(ctx); 5668 iflib_tx_structures_free(ctx); 5669 iflib_rx_structures_free(ctx); 5670 IFDI_DETACH(ctx); 5671 IFDI_QUEUES_FREE(ctx); 5672 5673 iflib_deregister(ctx); 5674 5675 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5676 free(ctx->ifc_softc, M_IFLIB); 5677 free(ctx, M_IFLIB); 5678 return (0); 5679 } 5680 5681 int 5682 iflib_device_attach(device_t dev) 5683 { 5684 if_ctx_t ctx; 5685 if_shared_ctx_t sctx; 5686 5687 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5688 return (ENOTSUP); 5689 5690 pci_enable_busmaster(dev); 5691 5692 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5693 } 5694 5695 int 5696 iflib_device_deregister(if_ctx_t ctx) 5697 { 5698 if_t ifp = ctx->ifc_ifp; 5699 device_t dev = ctx->ifc_dev; 5700 5701 /* Make sure VLANS are not using driver */ 5702 if (if_vlantrunkinuse(ifp)) { 5703 device_printf(dev, "Vlan in use, detach first\n"); 5704 return (EBUSY); 5705 } 5706 #ifdef PCI_IOV 5707 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5708 device_printf(dev, "SR-IOV in use; detach first.\n"); 5709 return (EBUSY); 5710 } 5711 #endif 5712 5713 STATE_LOCK(ctx); 5714 ctx->ifc_flags |= IFC_IN_DETACH; 5715 STATE_UNLOCK(ctx); 5716 5717 /* Unregister VLAN handlers before calling iflib_stop() */ 5718 iflib_unregister_vlan_handlers(ctx); 5719 5720 iflib_netmap_detach(ifp); 5721 ether_ifdetach(ifp); 5722 5723 CTX_LOCK(ctx); 5724 iflib_stop(ctx); 5725 CTX_UNLOCK(ctx); 5726 5727 iflib_rem_pfil(ctx); 5728 if (ctx->ifc_led_dev != NULL) 5729 led_destroy(ctx->ifc_led_dev); 5730 5731 iflib_tqg_detach(ctx); 5732 iflib_tx_structures_free(ctx); 5733 iflib_rx_structures_free(ctx); 5734 5735 CTX_LOCK(ctx); 5736 IFDI_DETACH(ctx); 5737 IFDI_QUEUES_FREE(ctx); 5738 CTX_UNLOCK(ctx); 5739 5740 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5741 iflib_free_intr_mem(ctx); 5742 5743 bus_generic_detach(dev); 5744 5745 iflib_deregister(ctx); 5746 5747 device_set_softc(ctx->ifc_dev, NULL); 5748 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5749 free(ctx->ifc_softc, M_IFLIB); 5750 unref_ctx_core_offset(ctx); 5751 free(ctx, M_IFLIB); 5752 return (0); 5753 } 5754 5755 static void 5756 iflib_tqg_detach(if_ctx_t ctx) 5757 { 5758 iflib_txq_t txq; 5759 iflib_rxq_t rxq; 5760 int i; 5761 struct taskqgroup *tqg; 5762 5763 /* XXX drain any dependent tasks */ 5764 tqg = qgroup_if_io_tqg; 5765 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5766 callout_drain(&txq->ift_timer); 5767 #ifdef DEV_NETMAP 5768 callout_drain(&txq->ift_netmap_timer); 5769 #endif /* DEV_NETMAP */ 5770 if (txq->ift_task.gt_uniq != NULL) 5771 taskqgroup_detach(tqg, &txq->ift_task); 5772 } 5773 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5774 if (rxq->ifr_task.gt_uniq != NULL) 5775 taskqgroup_detach(tqg, &rxq->ifr_task); 5776 } 5777 tqg = qgroup_if_config_tqg; 5778 if (ctx->ifc_admin_task.gt_uniq != NULL) 5779 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5780 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5781 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5782 } 5783 5784 static void 5785 iflib_free_intr_mem(if_ctx_t ctx) 5786 { 5787 5788 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5789 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5790 } 5791 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5792 pci_release_msi(ctx->ifc_dev); 5793 } 5794 if (ctx->ifc_msix_mem != NULL) { 5795 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5796 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5797 ctx->ifc_msix_mem = NULL; 5798 } 5799 } 5800 5801 int 5802 iflib_device_detach(device_t dev) 5803 { 5804 if_ctx_t ctx = device_get_softc(dev); 5805 5806 return (iflib_device_deregister(ctx)); 5807 } 5808 5809 int 5810 iflib_device_suspend(device_t dev) 5811 { 5812 if_ctx_t ctx = device_get_softc(dev); 5813 5814 CTX_LOCK(ctx); 5815 IFDI_SUSPEND(ctx); 5816 CTX_UNLOCK(ctx); 5817 5818 return bus_generic_suspend(dev); 5819 } 5820 int 5821 iflib_device_shutdown(device_t dev) 5822 { 5823 if_ctx_t ctx = device_get_softc(dev); 5824 5825 CTX_LOCK(ctx); 5826 IFDI_SHUTDOWN(ctx); 5827 CTX_UNLOCK(ctx); 5828 5829 return bus_generic_suspend(dev); 5830 } 5831 5832 int 5833 iflib_device_resume(device_t dev) 5834 { 5835 if_ctx_t ctx = device_get_softc(dev); 5836 iflib_txq_t txq = ctx->ifc_txqs; 5837 5838 CTX_LOCK(ctx); 5839 IFDI_RESUME(ctx); 5840 iflib_if_init_locked(ctx); 5841 CTX_UNLOCK(ctx); 5842 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5843 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5844 5845 return (bus_generic_resume(dev)); 5846 } 5847 5848 int 5849 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5850 { 5851 int error; 5852 if_ctx_t ctx = device_get_softc(dev); 5853 5854 CTX_LOCK(ctx); 5855 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5856 CTX_UNLOCK(ctx); 5857 5858 return (error); 5859 } 5860 5861 void 5862 iflib_device_iov_uninit(device_t dev) 5863 { 5864 if_ctx_t ctx = device_get_softc(dev); 5865 5866 CTX_LOCK(ctx); 5867 IFDI_IOV_UNINIT(ctx); 5868 CTX_UNLOCK(ctx); 5869 } 5870 5871 int 5872 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5873 { 5874 int error; 5875 if_ctx_t ctx = device_get_softc(dev); 5876 5877 CTX_LOCK(ctx); 5878 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5879 CTX_UNLOCK(ctx); 5880 5881 return (error); 5882 } 5883 5884 /********************************************************************* 5885 * 5886 * MODULE FUNCTION DEFINITIONS 5887 * 5888 **********************************************************************/ 5889 5890 /* 5891 * - Start a fast taskqueue thread for each core 5892 * - Start a taskqueue for control operations 5893 */ 5894 static int 5895 iflib_module_init(void) 5896 { 5897 iflib_timer_default = hz / 2; 5898 return (0); 5899 } 5900 5901 static int 5902 iflib_module_event_handler(module_t mod, int what, void *arg) 5903 { 5904 int err; 5905 5906 switch (what) { 5907 case MOD_LOAD: 5908 if ((err = iflib_module_init()) != 0) 5909 return (err); 5910 break; 5911 case MOD_UNLOAD: 5912 return (EBUSY); 5913 default: 5914 return (EOPNOTSUPP); 5915 } 5916 5917 return (0); 5918 } 5919 5920 /********************************************************************* 5921 * 5922 * PUBLIC FUNCTION DEFINITIONS 5923 * ordered as in iflib.h 5924 * 5925 **********************************************************************/ 5926 5927 static void 5928 _iflib_assert(if_shared_ctx_t sctx) 5929 { 5930 int i; 5931 5932 MPASS(sctx->isc_tx_maxsize); 5933 MPASS(sctx->isc_tx_maxsegsize); 5934 5935 MPASS(sctx->isc_rx_maxsize); 5936 MPASS(sctx->isc_rx_nsegments); 5937 MPASS(sctx->isc_rx_maxsegsize); 5938 5939 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5940 for (i = 0; i < sctx->isc_nrxqs; i++) { 5941 MPASS(sctx->isc_nrxd_min[i]); 5942 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5943 MPASS(sctx->isc_nrxd_max[i]); 5944 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5945 MPASS(sctx->isc_nrxd_default[i]); 5946 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5947 } 5948 5949 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5950 for (i = 0; i < sctx->isc_ntxqs; i++) { 5951 MPASS(sctx->isc_ntxd_min[i]); 5952 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5953 MPASS(sctx->isc_ntxd_max[i]); 5954 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5955 MPASS(sctx->isc_ntxd_default[i]); 5956 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5957 } 5958 } 5959 5960 static void 5961 _iflib_pre_assert(if_softc_ctx_t scctx) 5962 { 5963 5964 MPASS(scctx->isc_txrx->ift_txd_encap); 5965 MPASS(scctx->isc_txrx->ift_txd_flush); 5966 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5967 MPASS(scctx->isc_txrx->ift_rxd_available); 5968 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5969 MPASS(scctx->isc_txrx->ift_rxd_refill); 5970 MPASS(scctx->isc_txrx->ift_rxd_flush); 5971 } 5972 5973 static int 5974 iflib_register(if_ctx_t ctx) 5975 { 5976 if_shared_ctx_t sctx = ctx->ifc_sctx; 5977 driver_t *driver = sctx->isc_driver; 5978 device_t dev = ctx->ifc_dev; 5979 if_t ifp; 5980 u_char type; 5981 int iflags; 5982 5983 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0) 5984 _iflib_assert(sctx); 5985 5986 CTX_LOCK_INIT(ctx); 5987 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5988 if (sctx->isc_flags & IFLIB_PSEUDO) { 5989 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) 5990 type = IFT_ETHER; 5991 else 5992 type = IFT_PPP; 5993 } else 5994 type = IFT_ETHER; 5995 ifp = ctx->ifc_ifp = if_alloc(type); 5996 if (ifp == NULL) { 5997 device_printf(dev, "can not allocate ifnet structure\n"); 5998 return (ENOMEM); 5999 } 6000 6001 /* 6002 * Initialize our context's device specific methods 6003 */ 6004 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 6005 kobj_class_compile((kobj_class_t) driver); 6006 6007 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 6008 if_setsoftc(ifp, ctx); 6009 if_setdev(ifp, dev); 6010 if_setinitfn(ifp, iflib_if_init); 6011 if_setioctlfn(ifp, iflib_if_ioctl); 6012 #ifdef ALTQ 6013 if_setstartfn(ifp, iflib_altq_if_start); 6014 if_settransmitfn(ifp, iflib_altq_if_transmit); 6015 if_setsendqready(ifp); 6016 #else 6017 if_settransmitfn(ifp, iflib_if_transmit); 6018 #endif 6019 if_setqflushfn(ifp, iflib_if_qflush); 6020 iflags = IFF_MULTICAST; 6021 6022 if ((sctx->isc_flags & IFLIB_PSEUDO) && 6023 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) 6024 iflags |= IFF_POINTOPOINT; 6025 else 6026 iflags |= IFF_BROADCAST | IFF_SIMPLEX; 6027 if_setflags(ifp, iflags); 6028 ctx->ifc_vlan_attach_event = 6029 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 6030 EVENTHANDLER_PRI_FIRST); 6031 ctx->ifc_vlan_detach_event = 6032 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 6033 EVENTHANDLER_PRI_FIRST); 6034 6035 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 6036 ctx->ifc_mediap = &ctx->ifc_media; 6037 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 6038 iflib_media_change, iflib_media_status); 6039 } 6040 return (0); 6041 } 6042 6043 static void 6044 iflib_unregister_vlan_handlers(if_ctx_t ctx) 6045 { 6046 /* Unregister VLAN events */ 6047 if (ctx->ifc_vlan_attach_event != NULL) { 6048 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 6049 ctx->ifc_vlan_attach_event = NULL; 6050 } 6051 if (ctx->ifc_vlan_detach_event != NULL) { 6052 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 6053 ctx->ifc_vlan_detach_event = NULL; 6054 } 6055 6056 } 6057 6058 static void 6059 iflib_deregister(if_ctx_t ctx) 6060 { 6061 if_t ifp = ctx->ifc_ifp; 6062 6063 /* Remove all media */ 6064 ifmedia_removeall(&ctx->ifc_media); 6065 6066 /* Ensure that VLAN event handlers are unregistered */ 6067 iflib_unregister_vlan_handlers(ctx); 6068 6069 /* Release kobject reference */ 6070 kobj_delete((kobj_t) ctx, NULL); 6071 6072 /* Free the ifnet structure */ 6073 if_free(ifp); 6074 6075 STATE_LOCK_DESTROY(ctx); 6076 6077 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 6078 CTX_LOCK_DESTROY(ctx); 6079 } 6080 6081 static int 6082 iflib_queues_alloc(if_ctx_t ctx) 6083 { 6084 if_shared_ctx_t sctx = ctx->ifc_sctx; 6085 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6086 device_t dev = ctx->ifc_dev; 6087 int nrxqsets = scctx->isc_nrxqsets; 6088 int ntxqsets = scctx->isc_ntxqsets; 6089 iflib_txq_t txq; 6090 iflib_rxq_t rxq; 6091 iflib_fl_t fl = NULL; 6092 int i, j, cpu, err, txconf, rxconf; 6093 iflib_dma_info_t ifdip; 6094 uint32_t *rxqsizes = scctx->isc_rxqsizes; 6095 uint32_t *txqsizes = scctx->isc_txqsizes; 6096 uint8_t nrxqs = sctx->isc_nrxqs; 6097 uint8_t ntxqs = sctx->isc_ntxqs; 6098 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 6099 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0); 6100 caddr_t *vaddrs; 6101 uint64_t *paddrs; 6102 6103 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 6104 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 6105 KASSERT(nrxqs >= fl_offset + nfree_lists, 6106 ("there must be at least a rxq for each free list")); 6107 6108 /* Allocate the TX ring struct memory */ 6109 if (!(ctx->ifc_txqs = 6110 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 6111 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 6112 device_printf(dev, "Unable to allocate TX ring memory\n"); 6113 err = ENOMEM; 6114 goto fail; 6115 } 6116 6117 /* Now allocate the RX */ 6118 if (!(ctx->ifc_rxqs = 6119 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 6120 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 6121 device_printf(dev, "Unable to allocate RX ring memory\n"); 6122 err = ENOMEM; 6123 goto rx_fail; 6124 } 6125 6126 txq = ctx->ifc_txqs; 6127 rxq = ctx->ifc_rxqs; 6128 6129 /* 6130 * XXX handle allocation failure 6131 */ 6132 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 6133 /* Set up some basics */ 6134 6135 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 6136 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 6137 device_printf(dev, 6138 "Unable to allocate TX DMA info memory\n"); 6139 err = ENOMEM; 6140 goto err_tx_desc; 6141 } 6142 txq->ift_ifdi = ifdip; 6143 for (j = 0; j < ntxqs; j++, ifdip++) { 6144 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 6145 device_printf(dev, 6146 "Unable to allocate TX descriptors\n"); 6147 err = ENOMEM; 6148 goto err_tx_desc; 6149 } 6150 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 6151 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 6152 } 6153 txq->ift_ctx = ctx; 6154 txq->ift_id = i; 6155 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 6156 txq->ift_br_offset = 1; 6157 } else { 6158 txq->ift_br_offset = 0; 6159 } 6160 6161 if (iflib_txsd_alloc(txq)) { 6162 device_printf(dev, "Critical Failure setting up TX buffers\n"); 6163 err = ENOMEM; 6164 goto err_tx_desc; 6165 } 6166 6167 /* Initialize the TX lock */ 6168 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 6169 device_get_nameunit(dev), txq->ift_id); 6170 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 6171 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 6172 txq->ift_timer.c_cpu = cpu; 6173 #ifdef DEV_NETMAP 6174 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 6175 txq->ift_netmap_timer.c_cpu = cpu; 6176 #endif /* DEV_NETMAP */ 6177 6178 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 6179 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 6180 if (err) { 6181 /* XXX free any allocated rings */ 6182 device_printf(dev, "Unable to allocate buf_ring\n"); 6183 goto err_tx_desc; 6184 } 6185 } 6186 6187 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 6188 /* Set up some basics */ 6189 callout_init(&rxq->ifr_watchdog, 1); 6190 6191 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 6192 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 6193 device_printf(dev, 6194 "Unable to allocate RX DMA info memory\n"); 6195 err = ENOMEM; 6196 goto err_tx_desc; 6197 } 6198 6199 rxq->ifr_ifdi = ifdip; 6200 /* XXX this needs to be changed if #rx queues != #tx queues */ 6201 rxq->ifr_ntxqirq = 1; 6202 rxq->ifr_txqid[0] = i; 6203 for (j = 0; j < nrxqs; j++, ifdip++) { 6204 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 6205 device_printf(dev, 6206 "Unable to allocate RX descriptors\n"); 6207 err = ENOMEM; 6208 goto err_tx_desc; 6209 } 6210 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 6211 } 6212 rxq->ifr_ctx = ctx; 6213 rxq->ifr_id = i; 6214 rxq->ifr_fl_offset = fl_offset; 6215 rxq->ifr_nfl = nfree_lists; 6216 if (!(fl = 6217 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 6218 device_printf(dev, "Unable to allocate free list memory\n"); 6219 err = ENOMEM; 6220 goto err_tx_desc; 6221 } 6222 rxq->ifr_fl = fl; 6223 for (j = 0; j < nfree_lists; j++) { 6224 fl[j].ifl_rxq = rxq; 6225 fl[j].ifl_id = j; 6226 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 6227 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 6228 } 6229 /* Allocate receive buffers for the ring */ 6230 if (iflib_rxsd_alloc(rxq)) { 6231 device_printf(dev, 6232 "Critical Failure setting up receive buffers\n"); 6233 err = ENOMEM; 6234 goto err_rx_desc; 6235 } 6236 6237 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 6238 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 6239 M_WAITOK); 6240 } 6241 6242 /* TXQs */ 6243 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 6244 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 6245 for (i = 0; i < ntxqsets; i++) { 6246 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 6247 6248 for (j = 0; j < ntxqs; j++, di++) { 6249 vaddrs[i*ntxqs + j] = di->idi_vaddr; 6250 paddrs[i*ntxqs + j] = di->idi_paddr; 6251 } 6252 } 6253 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 6254 device_printf(ctx->ifc_dev, 6255 "Unable to allocate device TX queue\n"); 6256 iflib_tx_structures_free(ctx); 6257 free(vaddrs, M_IFLIB); 6258 free(paddrs, M_IFLIB); 6259 goto err_rx_desc; 6260 } 6261 free(vaddrs, M_IFLIB); 6262 free(paddrs, M_IFLIB); 6263 6264 /* RXQs */ 6265 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6266 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6267 for (i = 0; i < nrxqsets; i++) { 6268 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 6269 6270 for (j = 0; j < nrxqs; j++, di++) { 6271 vaddrs[i*nrxqs + j] = di->idi_vaddr; 6272 paddrs[i*nrxqs + j] = di->idi_paddr; 6273 } 6274 } 6275 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 6276 device_printf(ctx->ifc_dev, 6277 "Unable to allocate device RX queue\n"); 6278 iflib_tx_structures_free(ctx); 6279 free(vaddrs, M_IFLIB); 6280 free(paddrs, M_IFLIB); 6281 goto err_rx_desc; 6282 } 6283 free(vaddrs, M_IFLIB); 6284 free(paddrs, M_IFLIB); 6285 6286 return (0); 6287 6288 /* XXX handle allocation failure changes */ 6289 err_rx_desc: 6290 err_tx_desc: 6291 rx_fail: 6292 if (ctx->ifc_rxqs != NULL) 6293 free(ctx->ifc_rxqs, M_IFLIB); 6294 ctx->ifc_rxqs = NULL; 6295 if (ctx->ifc_txqs != NULL) 6296 free(ctx->ifc_txqs, M_IFLIB); 6297 ctx->ifc_txqs = NULL; 6298 fail: 6299 return (err); 6300 } 6301 6302 static int 6303 iflib_tx_structures_setup(if_ctx_t ctx) 6304 { 6305 iflib_txq_t txq = ctx->ifc_txqs; 6306 int i; 6307 6308 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 6309 iflib_txq_setup(txq); 6310 6311 return (0); 6312 } 6313 6314 static void 6315 iflib_tx_structures_free(if_ctx_t ctx) 6316 { 6317 iflib_txq_t txq = ctx->ifc_txqs; 6318 if_shared_ctx_t sctx = ctx->ifc_sctx; 6319 int i, j; 6320 6321 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6322 for (j = 0; j < sctx->isc_ntxqs; j++) 6323 iflib_dma_free(&txq->ift_ifdi[j]); 6324 iflib_txq_destroy(txq); 6325 } 6326 free(ctx->ifc_txqs, M_IFLIB); 6327 ctx->ifc_txqs = NULL; 6328 } 6329 6330 /********************************************************************* 6331 * 6332 * Initialize all receive rings. 6333 * 6334 **********************************************************************/ 6335 static int 6336 iflib_rx_structures_setup(if_ctx_t ctx) 6337 { 6338 iflib_rxq_t rxq = ctx->ifc_rxqs; 6339 int q; 6340 #if defined(INET6) || defined(INET) 6341 int err, i; 6342 #endif 6343 6344 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 6345 #if defined(INET6) || defined(INET) 6346 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 6347 TCP_LRO_ENTRIES, min(1024, 6348 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 6349 if (err != 0) { 6350 device_printf(ctx->ifc_dev, 6351 "LRO Initialization failed!\n"); 6352 goto fail; 6353 } 6354 #endif 6355 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 6356 } 6357 return (0); 6358 #if defined(INET6) || defined(INET) 6359 fail: 6360 /* 6361 * Free LRO resources allocated so far, we will only handle 6362 * the rings that completed, the failing case will have 6363 * cleaned up for itself. 'q' failed, so its the terminus. 6364 */ 6365 rxq = ctx->ifc_rxqs; 6366 for (i = 0; i < q; ++i, rxq++) { 6367 tcp_lro_free(&rxq->ifr_lc); 6368 } 6369 return (err); 6370 #endif 6371 } 6372 6373 /********************************************************************* 6374 * 6375 * Free all receive rings. 6376 * 6377 **********************************************************************/ 6378 static void 6379 iflib_rx_structures_free(if_ctx_t ctx) 6380 { 6381 iflib_rxq_t rxq = ctx->ifc_rxqs; 6382 if_shared_ctx_t sctx = ctx->ifc_sctx; 6383 int i, j; 6384 6385 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 6386 for (j = 0; j < sctx->isc_nrxqs; j++) 6387 iflib_dma_free(&rxq->ifr_ifdi[j]); 6388 iflib_rx_sds_free(rxq); 6389 #if defined(INET6) || defined(INET) 6390 tcp_lro_free(&rxq->ifr_lc); 6391 #endif 6392 } 6393 free(ctx->ifc_rxqs, M_IFLIB); 6394 ctx->ifc_rxqs = NULL; 6395 } 6396 6397 static int 6398 iflib_qset_structures_setup(if_ctx_t ctx) 6399 { 6400 int err; 6401 6402 /* 6403 * It is expected that the caller takes care of freeing queues if this 6404 * fails. 6405 */ 6406 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 6407 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 6408 return (err); 6409 } 6410 6411 if ((err = iflib_rx_structures_setup(ctx)) != 0) 6412 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 6413 6414 return (err); 6415 } 6416 6417 int 6418 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 6419 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 6420 { 6421 6422 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 6423 } 6424 6425 /* Just to avoid copy/paste */ 6426 static inline int 6427 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6428 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 6429 const char *name) 6430 { 6431 device_t dev; 6432 unsigned int base_cpuid, cpuid; 6433 int err; 6434 6435 dev = ctx->ifc_dev; 6436 base_cpuid = ctx->ifc_sysctl_core_offset; 6437 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX); 6438 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, 6439 irq ? irq->ii_res : NULL, name); 6440 if (err) { 6441 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6442 return (err); 6443 } 6444 #ifdef notyet 6445 if (cpuid > ctx->ifc_cpuid_highest) 6446 ctx->ifc_cpuid_highest = cpuid; 6447 #endif 6448 return (0); 6449 } 6450 6451 int 6452 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6453 iflib_intr_type_t type, driver_filter_t *filter, 6454 void *filter_arg, int qid, const char *name) 6455 { 6456 device_t dev; 6457 struct grouptask *gtask; 6458 struct taskqgroup *tqg; 6459 iflib_filter_info_t info; 6460 gtask_fn_t *fn; 6461 int tqrid, err; 6462 driver_filter_t *intr_fast; 6463 void *q; 6464 6465 info = &ctx->ifc_filter_info; 6466 tqrid = rid; 6467 6468 switch (type) { 6469 /* XXX merge tx/rx for netmap? */ 6470 case IFLIB_INTR_TX: 6471 q = &ctx->ifc_txqs[qid]; 6472 info = &ctx->ifc_txqs[qid].ift_filter_info; 6473 gtask = &ctx->ifc_txqs[qid].ift_task; 6474 tqg = qgroup_if_io_tqg; 6475 fn = _task_fn_tx; 6476 intr_fast = iflib_fast_intr; 6477 GROUPTASK_INIT(gtask, 0, fn, q); 6478 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6479 break; 6480 case IFLIB_INTR_RX: 6481 q = &ctx->ifc_rxqs[qid]; 6482 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6483 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6484 tqg = qgroup_if_io_tqg; 6485 fn = _task_fn_rx; 6486 intr_fast = iflib_fast_intr; 6487 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6488 break; 6489 case IFLIB_INTR_RXTX: 6490 q = &ctx->ifc_rxqs[qid]; 6491 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6492 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6493 tqg = qgroup_if_io_tqg; 6494 fn = _task_fn_rx; 6495 intr_fast = iflib_fast_intr_rxtx; 6496 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6497 break; 6498 case IFLIB_INTR_ADMIN: 6499 q = ctx; 6500 tqrid = -1; 6501 info = &ctx->ifc_filter_info; 6502 gtask = &ctx->ifc_admin_task; 6503 tqg = qgroup_if_config_tqg; 6504 fn = _task_fn_admin; 6505 intr_fast = iflib_fast_intr_ctx; 6506 break; 6507 default: 6508 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6509 __func__); 6510 return (EINVAL); 6511 } 6512 6513 info->ifi_filter = filter; 6514 info->ifi_filter_arg = filter_arg; 6515 info->ifi_task = gtask; 6516 info->ifi_ctx = q; 6517 6518 dev = ctx->ifc_dev; 6519 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6520 if (err != 0) { 6521 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6522 return (err); 6523 } 6524 if (type == IFLIB_INTR_ADMIN) 6525 return (0); 6526 6527 if (tqrid != -1) { 6528 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6529 name); 6530 if (err) 6531 return (err); 6532 } else { 6533 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6534 } 6535 6536 return (0); 6537 } 6538 6539 void 6540 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6541 { 6542 device_t dev; 6543 struct grouptask *gtask; 6544 struct taskqgroup *tqg; 6545 gtask_fn_t *fn; 6546 void *q; 6547 int err; 6548 6549 switch (type) { 6550 case IFLIB_INTR_TX: 6551 q = &ctx->ifc_txqs[qid]; 6552 gtask = &ctx->ifc_txqs[qid].ift_task; 6553 tqg = qgroup_if_io_tqg; 6554 fn = _task_fn_tx; 6555 GROUPTASK_INIT(gtask, 0, fn, q); 6556 break; 6557 case IFLIB_INTR_RX: 6558 q = &ctx->ifc_rxqs[qid]; 6559 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6560 tqg = qgroup_if_io_tqg; 6561 fn = _task_fn_rx; 6562 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6563 break; 6564 case IFLIB_INTR_IOV: 6565 q = ctx; 6566 gtask = &ctx->ifc_vflr_task; 6567 tqg = qgroup_if_config_tqg; 6568 fn = _task_fn_iov; 6569 GROUPTASK_INIT(gtask, 0, fn, q); 6570 break; 6571 default: 6572 panic("unknown net intr type"); 6573 } 6574 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name); 6575 if (err) { 6576 dev = ctx->ifc_dev; 6577 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL, 6578 name); 6579 } 6580 } 6581 6582 void 6583 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6584 { 6585 6586 if (irq->ii_tag) 6587 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6588 6589 if (irq->ii_res) 6590 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6591 rman_get_rid(irq->ii_res), irq->ii_res); 6592 } 6593 6594 static int 6595 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6596 { 6597 iflib_txq_t txq = ctx->ifc_txqs; 6598 iflib_rxq_t rxq = ctx->ifc_rxqs; 6599 if_irq_t irq = &ctx->ifc_legacy_irq; 6600 iflib_filter_info_t info; 6601 device_t dev; 6602 struct grouptask *gtask; 6603 struct resource *res; 6604 struct taskqgroup *tqg; 6605 void *q; 6606 int err, tqrid; 6607 bool rx_only; 6608 6609 q = &ctx->ifc_rxqs[0]; 6610 info = &rxq[0].ifr_filter_info; 6611 gtask = &rxq[0].ifr_task; 6612 tqg = qgroup_if_io_tqg; 6613 tqrid = *rid; 6614 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6615 6616 ctx->ifc_flags |= IFC_LEGACY; 6617 info->ifi_filter = filter; 6618 info->ifi_filter_arg = filter_arg; 6619 info->ifi_task = gtask; 6620 info->ifi_ctx = rx_only ? ctx : q; 6621 6622 dev = ctx->ifc_dev; 6623 /* We allocate a single interrupt resource */ 6624 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6625 iflib_fast_intr_rxtx, NULL, info, name); 6626 if (err != 0) 6627 return (err); 6628 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6629 res = irq->ii_res; 6630 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6631 6632 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6633 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6634 "tx"); 6635 return (0); 6636 } 6637 6638 void 6639 iflib_led_create(if_ctx_t ctx) 6640 { 6641 6642 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6643 device_get_nameunit(ctx->ifc_dev)); 6644 } 6645 6646 void 6647 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6648 { 6649 6650 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6651 } 6652 6653 void 6654 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6655 { 6656 6657 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6658 } 6659 6660 void 6661 iflib_admin_intr_deferred(if_ctx_t ctx) 6662 { 6663 6664 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6665 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6666 } 6667 6668 void 6669 iflib_iov_intr_deferred(if_ctx_t ctx) 6670 { 6671 6672 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6673 } 6674 6675 void 6676 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6677 { 6678 6679 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6680 name); 6681 } 6682 6683 void 6684 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6685 const char *name) 6686 { 6687 6688 GROUPTASK_INIT(gtask, 0, fn, ctx); 6689 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6690 name); 6691 } 6692 6693 void 6694 iflib_config_gtask_deinit(struct grouptask *gtask) 6695 { 6696 6697 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6698 } 6699 6700 void 6701 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6702 { 6703 if_t ifp = ctx->ifc_ifp; 6704 iflib_txq_t txq = ctx->ifc_txqs; 6705 6706 if_setbaudrate(ifp, baudrate); 6707 if (baudrate >= IF_Gbps(10)) { 6708 STATE_LOCK(ctx); 6709 ctx->ifc_flags |= IFC_PREFETCH; 6710 STATE_UNLOCK(ctx); 6711 } 6712 /* If link down, disable watchdog */ 6713 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6714 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6715 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6716 } 6717 ctx->ifc_link_state = link_state; 6718 if_link_state_change(ifp, link_state); 6719 } 6720 6721 static int 6722 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6723 { 6724 int credits; 6725 #ifdef INVARIANTS 6726 int credits_pre = txq->ift_cidx_processed; 6727 #endif 6728 6729 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6730 BUS_DMASYNC_POSTREAD); 6731 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6732 return (0); 6733 6734 txq->ift_processed += credits; 6735 txq->ift_cidx_processed += credits; 6736 6737 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6738 if (txq->ift_cidx_processed >= txq->ift_size) 6739 txq->ift_cidx_processed -= txq->ift_size; 6740 return (credits); 6741 } 6742 6743 static int 6744 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6745 { 6746 iflib_fl_t fl; 6747 u_int i; 6748 6749 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6750 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6751 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6752 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6753 budget)); 6754 } 6755 6756 void 6757 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6758 const char *description, if_int_delay_info_t info, 6759 int offset, int value) 6760 { 6761 info->iidi_ctx = ctx; 6762 info->iidi_offset = offset; 6763 info->iidi_value = value; 6764 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6765 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6766 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6767 info, 0, iflib_sysctl_int_delay, "I", description); 6768 } 6769 6770 struct sx * 6771 iflib_ctx_lock_get(if_ctx_t ctx) 6772 { 6773 6774 return (&ctx->ifc_ctx_sx); 6775 } 6776 6777 static int 6778 iflib_msix_init(if_ctx_t ctx) 6779 { 6780 device_t dev = ctx->ifc_dev; 6781 if_shared_ctx_t sctx = ctx->ifc_sctx; 6782 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6783 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6784 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6785 6786 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6787 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6788 6789 if (bootverbose) 6790 device_printf(dev, "msix_init qsets capped at %d\n", 6791 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6792 6793 /* Override by tuneable */ 6794 if (scctx->isc_disable_msix) 6795 goto msi; 6796 6797 /* First try MSI-X */ 6798 if ((msgs = pci_msix_count(dev)) == 0) { 6799 if (bootverbose) 6800 device_printf(dev, "MSI-X not supported or disabled\n"); 6801 goto msi; 6802 } 6803 6804 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6805 /* 6806 * bar == -1 => "trust me I know what I'm doing" 6807 * Some drivers are for hardware that is so shoddily 6808 * documented that no one knows which bars are which 6809 * so the developer has to map all bars. This hack 6810 * allows shoddy garbage to use MSI-X in this framework. 6811 */ 6812 if (bar != -1) { 6813 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6814 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6815 if (ctx->ifc_msix_mem == NULL) { 6816 device_printf(dev, "Unable to map MSI-X table\n"); 6817 goto msi; 6818 } 6819 } 6820 6821 admincnt = sctx->isc_admin_intrcnt; 6822 #if IFLIB_DEBUG 6823 /* use only 1 qset in debug mode */ 6824 queuemsgs = min(msgs - admincnt, 1); 6825 #else 6826 queuemsgs = msgs - admincnt; 6827 #endif 6828 #ifdef RSS 6829 queues = imin(queuemsgs, rss_getnumbuckets()); 6830 #else 6831 queues = queuemsgs; 6832 #endif 6833 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6834 if (bootverbose) 6835 device_printf(dev, 6836 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6837 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6838 #ifdef RSS 6839 /* If we're doing RSS, clamp at the number of RSS buckets */ 6840 if (queues > rss_getnumbuckets()) 6841 queues = rss_getnumbuckets(); 6842 #endif 6843 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6844 rx_queues = iflib_num_rx_queues; 6845 else 6846 rx_queues = queues; 6847 6848 if (rx_queues > scctx->isc_nrxqsets) 6849 rx_queues = scctx->isc_nrxqsets; 6850 6851 /* 6852 * We want this to be all logical CPUs by default 6853 */ 6854 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6855 tx_queues = iflib_num_tx_queues; 6856 else 6857 tx_queues = mp_ncpus; 6858 6859 if (tx_queues > scctx->isc_ntxqsets) 6860 tx_queues = scctx->isc_ntxqsets; 6861 6862 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6863 #ifdef INVARIANTS 6864 if (tx_queues != rx_queues) 6865 device_printf(dev, 6866 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6867 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6868 #endif 6869 tx_queues = min(rx_queues, tx_queues); 6870 rx_queues = min(rx_queues, tx_queues); 6871 } 6872 6873 vectors = rx_queues + admincnt; 6874 if (msgs < vectors) { 6875 device_printf(dev, 6876 "insufficient number of MSI-X vectors " 6877 "(supported %d, need %d)\n", msgs, vectors); 6878 goto msi; 6879 } 6880 6881 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6882 tx_queues); 6883 msgs = vectors; 6884 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6885 if (vectors != msgs) { 6886 device_printf(dev, 6887 "Unable to allocate sufficient MSI-X vectors " 6888 "(got %d, need %d)\n", vectors, msgs); 6889 pci_release_msi(dev); 6890 if (bar != -1) { 6891 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6892 ctx->ifc_msix_mem); 6893 ctx->ifc_msix_mem = NULL; 6894 } 6895 goto msi; 6896 } 6897 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6898 vectors); 6899 scctx->isc_vectors = vectors; 6900 scctx->isc_nrxqsets = rx_queues; 6901 scctx->isc_ntxqsets = tx_queues; 6902 scctx->isc_intr = IFLIB_INTR_MSIX; 6903 6904 return (vectors); 6905 } else { 6906 device_printf(dev, 6907 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6908 err); 6909 if (bar != -1) { 6910 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6911 ctx->ifc_msix_mem); 6912 ctx->ifc_msix_mem = NULL; 6913 } 6914 } 6915 6916 msi: 6917 vectors = pci_msi_count(dev); 6918 scctx->isc_nrxqsets = 1; 6919 scctx->isc_ntxqsets = 1; 6920 scctx->isc_vectors = vectors; 6921 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6922 device_printf(dev,"Using an MSI interrupt\n"); 6923 scctx->isc_intr = IFLIB_INTR_MSI; 6924 } else { 6925 scctx->isc_vectors = 1; 6926 device_printf(dev,"Using a Legacy interrupt\n"); 6927 scctx->isc_intr = IFLIB_INTR_LEGACY; 6928 } 6929 6930 return (vectors); 6931 } 6932 6933 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6934 6935 static int 6936 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6937 { 6938 int rc; 6939 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6940 struct sbuf *sb; 6941 const char *ring_state = "UNKNOWN"; 6942 6943 /* XXX needed ? */ 6944 rc = sysctl_wire_old_buffer(req, 0); 6945 MPASS(rc == 0); 6946 if (rc != 0) 6947 return (rc); 6948 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6949 MPASS(sb != NULL); 6950 if (sb == NULL) 6951 return (ENOMEM); 6952 if (state[3] <= 3) 6953 ring_state = ring_states[state[3]]; 6954 6955 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6956 state[0], state[1], state[2], ring_state); 6957 rc = sbuf_finish(sb); 6958 sbuf_delete(sb); 6959 return(rc); 6960 } 6961 6962 enum iflib_ndesc_handler { 6963 IFLIB_NTXD_HANDLER, 6964 IFLIB_NRXD_HANDLER, 6965 }; 6966 6967 static int 6968 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6969 { 6970 if_ctx_t ctx = (void *)arg1; 6971 enum iflib_ndesc_handler type = arg2; 6972 char buf[256] = {0}; 6973 qidx_t *ndesc; 6974 char *p, *next; 6975 int nqs, rc, i; 6976 6977 nqs = 8; 6978 switch(type) { 6979 case IFLIB_NTXD_HANDLER: 6980 ndesc = ctx->ifc_sysctl_ntxds; 6981 if (ctx->ifc_sctx) 6982 nqs = ctx->ifc_sctx->isc_ntxqs; 6983 break; 6984 case IFLIB_NRXD_HANDLER: 6985 ndesc = ctx->ifc_sysctl_nrxds; 6986 if (ctx->ifc_sctx) 6987 nqs = ctx->ifc_sctx->isc_nrxqs; 6988 break; 6989 default: 6990 printf("%s: unhandled type\n", __func__); 6991 return (EINVAL); 6992 } 6993 if (nqs == 0) 6994 nqs = 8; 6995 6996 for (i=0; i<8; i++) { 6997 if (i >= nqs) 6998 break; 6999 if (i) 7000 strcat(buf, ","); 7001 sprintf(strchr(buf, 0), "%d", ndesc[i]); 7002 } 7003 7004 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 7005 if (rc || req->newptr == NULL) 7006 return rc; 7007 7008 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 7009 i++, p = strsep(&next, " ,")) { 7010 ndesc[i] = strtoul(p, NULL, 10); 7011 } 7012 7013 return(rc); 7014 } 7015 7016 #define NAME_BUFLEN 32 7017 static void 7018 iflib_add_device_sysctl_pre(if_ctx_t ctx) 7019 { 7020 device_t dev = iflib_get_dev(ctx); 7021 struct sysctl_oid_list *child, *oid_list; 7022 struct sysctl_ctx_list *ctx_list; 7023 struct sysctl_oid *node; 7024 7025 ctx_list = device_get_sysctl_ctx(dev); 7026 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 7027 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 7028 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 7029 oid_list = SYSCTL_CHILDREN(node); 7030 7031 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 7032 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 7033 "driver version"); 7034 7035 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 7036 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 7037 "# of txqs to use, 0 => use default #"); 7038 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 7039 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 7040 "# of rxqs to use, 0 => use default #"); 7041 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 7042 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 7043 "permit #txq != #rxq"); 7044 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 7045 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 7046 "disable MSI-X (default 0)"); 7047 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 7048 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 7049 "set the RX budget"); 7050 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 7051 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 7052 "cause TX to abdicate instead of running to completion"); 7053 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 7054 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 7055 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 7056 "offset to start using cores at"); 7057 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 7058 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 7059 "use separate cores for TX and RX"); 7060 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "use_logical_cores", 7061 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0, 7062 "try to make use of logical cores for TX and RX"); 7063 7064 /* XXX change for per-queue sizes */ 7065 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 7066 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 7067 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 7068 "list of # of TX descriptors to use, 0 = use default #"); 7069 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 7070 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 7071 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 7072 "list of # of RX descriptors to use, 0 = use default #"); 7073 } 7074 7075 static void 7076 iflib_add_device_sysctl_post(if_ctx_t ctx) 7077 { 7078 if_shared_ctx_t sctx = ctx->ifc_sctx; 7079 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 7080 device_t dev = iflib_get_dev(ctx); 7081 struct sysctl_oid_list *child; 7082 struct sysctl_ctx_list *ctx_list; 7083 iflib_fl_t fl; 7084 iflib_txq_t txq; 7085 iflib_rxq_t rxq; 7086 int i, j; 7087 char namebuf[NAME_BUFLEN]; 7088 char *qfmt; 7089 struct sysctl_oid *queue_node, *fl_node, *node; 7090 struct sysctl_oid_list *queue_list, *fl_list; 7091 ctx_list = device_get_sysctl_ctx(dev); 7092 7093 node = ctx->ifc_sysctl_node; 7094 child = SYSCTL_CHILDREN(node); 7095 7096 if (scctx->isc_ntxqsets > 100) 7097 qfmt = "txq%03d"; 7098 else if (scctx->isc_ntxqsets > 10) 7099 qfmt = "txq%02d"; 7100 else 7101 qfmt = "txq%d"; 7102 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 7103 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 7104 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 7105 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 7106 queue_list = SYSCTL_CHILDREN(queue_node); 7107 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 7108 CTLFLAG_RD, 7109 &txq->ift_task.gt_cpu, 0, "cpu this queue is bound to"); 7110 #if MEMORY_LOGGING 7111 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 7112 CTLFLAG_RD, 7113 &txq->ift_dequeued, "total mbufs freed"); 7114 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 7115 CTLFLAG_RD, 7116 &txq->ift_enqueued, "total mbufs enqueued"); 7117 #endif 7118 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 7119 CTLFLAG_RD, 7120 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 7121 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 7122 CTLFLAG_RD, 7123 &txq->ift_pullups, "# of times m_pullup was called"); 7124 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 7125 CTLFLAG_RD, 7126 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 7127 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 7128 CTLFLAG_RD, 7129 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 7130 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 7131 CTLFLAG_RD, 7132 &txq->ift_map_failed, "# of times DMA map failed"); 7133 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 7134 CTLFLAG_RD, 7135 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 7136 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 7137 CTLFLAG_RD, 7138 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 7139 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 7140 CTLFLAG_RD, 7141 &txq->ift_pidx, 1, "Producer Index"); 7142 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 7143 CTLFLAG_RD, 7144 &txq->ift_cidx, 1, "Consumer Index"); 7145 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 7146 CTLFLAG_RD, 7147 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 7148 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 7149 CTLFLAG_RD, 7150 &txq->ift_in_use, 1, "descriptors in use"); 7151 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 7152 CTLFLAG_RD, 7153 &txq->ift_processed, "descriptors procesed for clean"); 7154 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 7155 CTLFLAG_RD, 7156 &txq->ift_cleaned, "total cleaned"); 7157 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 7158 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 7159 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 7160 mp_ring_state_handler, "A", "soft ring state"); 7161 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 7162 CTLFLAG_RD, &txq->ift_br->enqueues, 7163 "# of enqueues to the mp_ring for this queue"); 7164 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 7165 CTLFLAG_RD, &txq->ift_br->drops, 7166 "# of drops in the mp_ring for this queue"); 7167 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 7168 CTLFLAG_RD, &txq->ift_br->starts, 7169 "# of normal consumer starts in the mp_ring for this queue"); 7170 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 7171 CTLFLAG_RD, &txq->ift_br->stalls, 7172 "# of consumer stalls in the mp_ring for this queue"); 7173 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 7174 CTLFLAG_RD, &txq->ift_br->restarts, 7175 "# of consumer restarts in the mp_ring for this queue"); 7176 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 7177 CTLFLAG_RD, &txq->ift_br->abdications, 7178 "# of consumer abdications in the mp_ring for this queue"); 7179 } 7180 7181 if (scctx->isc_nrxqsets > 100) 7182 qfmt = "rxq%03d"; 7183 else if (scctx->isc_nrxqsets > 10) 7184 qfmt = "rxq%02d"; 7185 else 7186 qfmt = "rxq%d"; 7187 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 7188 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 7189 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 7190 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 7191 queue_list = SYSCTL_CHILDREN(queue_node); 7192 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 7193 CTLFLAG_RD, 7194 &rxq->ifr_task.gt_cpu, 0, "cpu this queue is bound to"); 7195 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 7196 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 7197 CTLFLAG_RD, 7198 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 7199 } 7200 7201 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 7202 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 7203 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 7204 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 7205 fl_list = SYSCTL_CHILDREN(fl_node); 7206 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 7207 CTLFLAG_RD, 7208 &fl->ifl_pidx, 1, "Producer Index"); 7209 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 7210 CTLFLAG_RD, 7211 &fl->ifl_cidx, 1, "Consumer Index"); 7212 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 7213 CTLFLAG_RD, 7214 &fl->ifl_credits, 1, "credits available"); 7215 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 7216 CTLFLAG_RD, 7217 &fl->ifl_buf_size, 1, "buffer size"); 7218 #if MEMORY_LOGGING 7219 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 7220 CTLFLAG_RD, 7221 &fl->ifl_m_enqueued, "mbufs allocated"); 7222 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 7223 CTLFLAG_RD, 7224 &fl->ifl_m_dequeued, "mbufs freed"); 7225 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 7226 CTLFLAG_RD, 7227 &fl->ifl_cl_enqueued, "clusters allocated"); 7228 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 7229 CTLFLAG_RD, 7230 &fl->ifl_cl_dequeued, "clusters freed"); 7231 #endif 7232 } 7233 } 7234 7235 } 7236 7237 void 7238 iflib_request_reset(if_ctx_t ctx) 7239 { 7240 7241 STATE_LOCK(ctx); 7242 ctx->ifc_flags |= IFC_DO_RESET; 7243 STATE_UNLOCK(ctx); 7244 } 7245 7246 #ifndef __NO_STRICT_ALIGNMENT 7247 static struct mbuf * 7248 iflib_fixup_rx(struct mbuf *m) 7249 { 7250 struct mbuf *n; 7251 7252 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 7253 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 7254 m->m_data += ETHER_HDR_LEN; 7255 n = m; 7256 } else { 7257 MGETHDR(n, M_NOWAIT, MT_DATA); 7258 if (n == NULL) { 7259 m_freem(m); 7260 return (NULL); 7261 } 7262 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 7263 m->m_data += ETHER_HDR_LEN; 7264 m->m_len -= ETHER_HDR_LEN; 7265 n->m_len = ETHER_HDR_LEN; 7266 M_MOVE_PKTHDR(n, m); 7267 n->m_next = m; 7268 } 7269 return (n); 7270 } 7271 #endif 7272 7273 #ifdef DEBUGNET 7274 static void 7275 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 7276 { 7277 if_ctx_t ctx; 7278 7279 ctx = if_getsoftc(ifp); 7280 CTX_LOCK(ctx); 7281 *nrxr = NRXQSETS(ctx); 7282 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 7283 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 7284 CTX_UNLOCK(ctx); 7285 } 7286 7287 static void 7288 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 7289 { 7290 if_ctx_t ctx; 7291 if_softc_ctx_t scctx; 7292 iflib_fl_t fl; 7293 iflib_rxq_t rxq; 7294 int i, j; 7295 7296 ctx = if_getsoftc(ifp); 7297 scctx = &ctx->ifc_softc_ctx; 7298 7299 switch (event) { 7300 case DEBUGNET_START: 7301 for (i = 0; i < scctx->isc_nrxqsets; i++) { 7302 rxq = &ctx->ifc_rxqs[i]; 7303 for (j = 0; j < rxq->ifr_nfl; j++) { 7304 fl = rxq->ifr_fl; 7305 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 7306 } 7307 } 7308 iflib_no_tx_batch = 1; 7309 break; 7310 default: 7311 break; 7312 } 7313 } 7314 7315 static int 7316 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 7317 { 7318 if_ctx_t ctx; 7319 iflib_txq_t txq; 7320 int error; 7321 7322 ctx = if_getsoftc(ifp); 7323 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7324 IFF_DRV_RUNNING) 7325 return (EBUSY); 7326 7327 txq = &ctx->ifc_txqs[0]; 7328 error = iflib_encap(txq, &m); 7329 if (error == 0) 7330 (void)iflib_txd_db_check(txq, true); 7331 return (error); 7332 } 7333 7334 static int 7335 iflib_debugnet_poll(if_t ifp, int count) 7336 { 7337 struct epoch_tracker et; 7338 if_ctx_t ctx; 7339 if_softc_ctx_t scctx; 7340 iflib_txq_t txq; 7341 int i; 7342 7343 ctx = if_getsoftc(ifp); 7344 scctx = &ctx->ifc_softc_ctx; 7345 7346 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7347 IFF_DRV_RUNNING) 7348 return (EBUSY); 7349 7350 txq = &ctx->ifc_txqs[0]; 7351 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 7352 7353 NET_EPOCH_ENTER(et); 7354 for (i = 0; i < scctx->isc_nrxqsets; i++) 7355 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 7356 NET_EPOCH_EXIT(et); 7357 return (0); 7358 } 7359 #endif /* DEBUGNET */ 7360