1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include "opt_inet.h" 30 #include "opt_inet6.h" 31 #include "opt_acpi.h" 32 33 #include <sys/param.h> 34 #include <sys/types.h> 35 #include <sys/bus.h> 36 #include <sys/eventhandler.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/module.h> 41 #include <sys/kobj.h> 42 #include <sys/proc.h> 43 #include <sys/rman.h> 44 #include <sys/sbuf.h> 45 #include <sys/sched.h> 46 #include <sys/smp.h> 47 #include <sys/socket.h> 48 #include <sys/sockio.h> 49 #include <sys/sysctl.h> 50 #include <sys/syslog.h> 51 #include <sys/taskqueue.h> 52 #include <sys/limits.h> 53 54 #include <net/if.h> 55 #include <net/if_var.h> 56 #include <net/if_private.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/udp.h> 75 #include <netinet/ip_var.h> 76 #include <netinet6/ip6_var.h> 77 78 #include <machine/bus.h> 79 #include <machine/in_cksum.h> 80 81 #include <vm/vm.h> 82 #include <vm/pmap.h> 83 84 #include <dev/led/led.h> 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pci_private.h> 88 89 #include <net/iflib.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 /* 120 * File organization: 121 * - private structures 122 * - iflib private utility functions 123 * - ifnet functions 124 * - vlan registry and other exported functions 125 * - iflib public core functions 126 * 127 * 128 */ 129 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 130 131 #define IFLIB_RXEOF_MORE (1U << 0) 132 #define IFLIB_RXEOF_EMPTY (2U << 0) 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 static void iflib_tqg_detach(if_ctx_t ctx); 146 #ifndef ALTQ 147 static int iflib_simple_transmit(if_t ifp, struct mbuf *m); 148 #endif 149 150 typedef struct iflib_filter_info { 151 driver_filter_t *ifi_filter; 152 void *ifi_filter_arg; 153 struct grouptask *ifi_task; 154 void *ifi_ctx; 155 } *iflib_filter_info_t; 156 157 struct iflib_ctx { 158 KOBJ_FIELDS; 159 /* 160 * Pointer to hardware driver's softc 161 */ 162 void *ifc_softc; 163 device_t ifc_dev; 164 if_t ifc_ifp; 165 166 cpuset_t ifc_cpus; 167 if_shared_ctx_t ifc_sctx; 168 struct if_softc_ctx ifc_softc_ctx; 169 170 struct sx ifc_ctx_sx; 171 struct mtx ifc_state_mtx; 172 173 iflib_txq_t ifc_txqs; 174 iflib_rxq_t ifc_rxqs; 175 uint32_t ifc_if_flags; 176 uint32_t ifc_flags; 177 uint32_t ifc_max_fl_buf_size; 178 uint32_t ifc_rx_mbuf_sz; 179 180 int ifc_link_state; 181 int ifc_watchdog_events; 182 struct cdev *ifc_led_dev; 183 struct resource *ifc_msix_mem; 184 185 struct if_irq ifc_legacy_irq; 186 struct task ifc_admin_task; 187 struct task ifc_vflr_task; 188 struct taskqueue *ifc_tq; 189 struct iflib_filter_info ifc_filter_info; 190 struct ifmedia ifc_media; 191 struct ifmedia *ifc_mediap; 192 193 struct sysctl_ctx_list ifc_sysctl_ctx; 194 struct sysctl_oid *ifc_sysctl_node; 195 uint16_t ifc_sysctl_ntxqs; 196 uint16_t ifc_sysctl_nrxqs; 197 uint16_t ifc_sysctl_qs_eq_override; 198 uint16_t ifc_sysctl_rx_budget; 199 uint16_t ifc_sysctl_tx_abdicate; 200 uint16_t ifc_sysctl_core_offset; 201 #define CORE_OFFSET_UNSPECIFIED 0xffff 202 uint8_t ifc_sysctl_separate_txrx; 203 uint8_t ifc_sysctl_use_logical_cores; 204 uint16_t ifc_sysctl_extra_msix_vectors; 205 bool ifc_cpus_are_physical_cores; 206 bool ifc_sysctl_simple_tx; 207 bool ifc_sysctl_tx_defer_mfree; 208 uint16_t ifc_sysctl_tx_reclaim_thresh; 209 uint16_t ifc_sysctl_tx_reclaim_ticks; 210 211 qidx_t ifc_sysctl_ntxds[8]; 212 qidx_t ifc_sysctl_nrxds[8]; 213 struct if_txrx ifc_txrx; 214 #define isc_txd_encap ifc_txrx.ift_txd_encap 215 #define isc_txd_flush ifc_txrx.ift_txd_flush 216 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 217 #define isc_rxd_available ifc_txrx.ift_rxd_available 218 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 219 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 220 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 221 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 222 #define isc_txq_select ifc_txrx.ift_txq_select 223 #define isc_txq_select_v2 ifc_txrx.ift_txq_select_v2 224 225 eventhandler_tag ifc_vlan_attach_event; 226 eventhandler_tag ifc_vlan_detach_event; 227 struct ether_addr ifc_mac; 228 }; 229 230 void * 231 iflib_get_softc(if_ctx_t ctx) 232 { 233 234 return (ctx->ifc_softc); 235 } 236 237 device_t 238 iflib_get_dev(if_ctx_t ctx) 239 { 240 241 return (ctx->ifc_dev); 242 } 243 244 if_t 245 iflib_get_ifp(if_ctx_t ctx) 246 { 247 248 return (ctx->ifc_ifp); 249 } 250 251 struct ifmedia * 252 iflib_get_media(if_ctx_t ctx) 253 { 254 255 return (ctx->ifc_mediap); 256 } 257 258 void 259 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 260 { 261 262 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 263 } 264 265 if_softc_ctx_t 266 iflib_get_softc_ctx(if_ctx_t ctx) 267 { 268 269 return (&ctx->ifc_softc_ctx); 270 } 271 272 if_shared_ctx_t 273 iflib_get_sctx(if_ctx_t ctx) 274 { 275 276 return (ctx->ifc_sctx); 277 } 278 279 uint16_t 280 iflib_get_extra_msix_vectors_sysctl(if_ctx_t ctx) 281 { 282 283 return (ctx->ifc_sysctl_extra_msix_vectors); 284 } 285 286 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 287 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE / sizeof(void *)) 288 #define CACHE_PTR_NEXT(ptr) ((void *)(roundup2(ptr, CACHE_LINE_SIZE))) 289 290 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 291 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 292 293 typedef struct iflib_sw_rx_desc_array { 294 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 295 struct mbuf **ifsd_m; /* pkthdr mbufs */ 296 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 297 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 298 } iflib_rxsd_array_t; 299 300 typedef struct iflib_sw_tx_desc_array { 301 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 302 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 303 struct mbuf **ifsd_m; /* pkthdr mbufs */ 304 struct mbuf **ifsd_m_defer; /* deferred mbuf ptr */ 305 struct mbuf **ifsd_m_deferb;/* deferred mbuf backing ptr */ 306 } if_txsd_vec_t; 307 308 /* magic number that should be high enough for any hardware */ 309 #define IFLIB_MAX_TX_SEGS 128 310 #define IFLIB_RX_COPY_THRESH 128 311 #define IFLIB_MAX_RX_REFRESH 32 312 /* The minimum descriptors per second before we start coalescing */ 313 #define IFLIB_MIN_DESC_SEC 16384 314 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 315 #define IFLIB_QUEUE_IDLE 0 316 #define IFLIB_QUEUE_HUNG 1 317 #define IFLIB_QUEUE_WORKING 2 318 /* maximum number of txqs that can share an rx interrupt */ 319 #define IFLIB_MAX_TX_SHARED_INTR 4 320 321 /* this should really scale with ring size - this is a fairly arbitrary value */ 322 #define TX_BATCH_SIZE 32 323 324 #define IFLIB_RESTART_BUDGET 8 325 326 327 /* 328 * Encode TSO or !TSO in the low bits of the tx ifsd_m pointer so as 329 * to avoid defref'ing the mbuf to determine the correct busdma resources 330 * to release 331 */ 332 #define IFLIB_TSO (1ULL << 0) 333 #define IFLIB_NO_TSO (2ULL << 0) 334 #define IFLIB_FLAGS_MASK (0x3ULL) 335 #define IFLIB_SAVE_MBUF(mbuf, flags) ((void *)(((uintptr_t)mbuf) | flags)) 336 #define IFLIB_GET_FLAGS(a) ((uintptr_t)a & IFLIB_FLAGS_MASK) 337 #define IFLIB_GET_MBUF(a) ((struct mbuf *)((uintptr_t)a & ~IFLIB_FLAGS_MASK)) 338 339 340 #define IFC_LEGACY 0x001 341 #define IFC_QFLUSH 0x002 342 #define IFC_MULTISEG 0x004 343 #define IFC_SPARE1 0x008 344 #define IFC_SC_ALLOCATED 0x010 345 #define IFC_INIT_DONE 0x020 346 #define IFC_PREFETCH 0x040 347 #define IFC_DO_RESET 0x080 348 #define IFC_DO_WATCHDOG 0x100 349 #define IFC_SPARE0 0x200 350 #define IFC_SPARE2 0x400 351 #define IFC_IN_DETACH 0x800 352 353 #define IFC_NETMAP_TX_IRQ 0x80000000 354 355 #define CSUM_OFFLOAD (CSUM_IP_TSO | CSUM_IP6_TSO | CSUM_IP | \ 356 CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_SCTP | \ 357 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_SCTP) 358 359 struct iflib_txq { 360 qidx_t ift_in_use; 361 qidx_t ift_cidx; 362 qidx_t ift_cidx_processed; 363 qidx_t ift_pidx; 364 uint8_t ift_gen; 365 uint8_t ift_br_offset:1, 366 ift_defer_mfree:1, 367 ift_spare_bits0:6; 368 uint16_t ift_npending; 369 uint16_t ift_db_pending; 370 uint16_t ift_rs_pending; 371 uint32_t ift_last_reclaim; 372 uint16_t ift_reclaim_thresh; 373 uint16_t ift_reclaim_ticks; 374 uint8_t ift_txd_size[8]; 375 uint64_t ift_processed; 376 uint64_t ift_cleaned; 377 uint64_t ift_cleaned_prev; 378 #if MEMORY_LOGGING 379 uint64_t ift_enqueued; 380 uint64_t ift_dequeued; 381 #endif 382 uint64_t ift_no_tx_dma_setup; 383 uint64_t ift_no_desc_avail; 384 uint64_t ift_mbuf_defrag_failed; 385 uint64_t ift_mbuf_defrag; 386 uint64_t ift_map_failed; 387 uint64_t ift_txd_encap_efbig; 388 uint64_t ift_pullups; 389 uint64_t ift_last_timer_tick; 390 391 struct mtx ift_mtx; 392 struct mtx ift_db_mtx; 393 394 /* constant values */ 395 if_ctx_t ift_ctx; 396 struct ifmp_ring *ift_br; 397 struct grouptask ift_task; 398 qidx_t ift_size; 399 qidx_t ift_pad; 400 uint16_t ift_id; 401 struct callout ift_timer; 402 #ifdef DEV_NETMAP 403 struct callout ift_netmap_timer; 404 #endif /* DEV_NETMAP */ 405 406 if_txsd_vec_t ift_sds; 407 uint8_t ift_qstatus; 408 uint8_t ift_closed; 409 uint8_t ift_update_freq; 410 struct iflib_filter_info ift_filter_info; 411 bus_dma_tag_t ift_buf_tag; 412 bus_dma_tag_t ift_tso_buf_tag; 413 iflib_dma_info_t ift_ifdi; 414 #define MTX_NAME_LEN 32 415 char ift_mtx_name[MTX_NAME_LEN]; 416 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 417 #ifdef IFLIB_DIAGNOSTICS 418 uint64_t ift_cpu_exec_count[256]; 419 #endif 420 } __aligned(CACHE_LINE_SIZE); 421 422 struct iflib_fl { 423 qidx_t ifl_cidx; 424 qidx_t ifl_pidx; 425 qidx_t ifl_credits; 426 uint8_t ifl_gen; 427 uint8_t ifl_rxd_size; 428 #if MEMORY_LOGGING 429 uint64_t ifl_m_enqueued; 430 uint64_t ifl_m_dequeued; 431 uint64_t ifl_cl_enqueued; 432 uint64_t ifl_cl_dequeued; 433 #endif 434 /* implicit pad */ 435 bitstr_t *ifl_rx_bitmap; 436 qidx_t ifl_fragidx; 437 /* constant */ 438 qidx_t ifl_size; 439 uint16_t ifl_buf_size; 440 uint16_t ifl_cltype; 441 uma_zone_t ifl_zone; 442 iflib_rxsd_array_t ifl_sds; 443 iflib_rxq_t ifl_rxq; 444 uint8_t ifl_id; 445 bus_dma_tag_t ifl_buf_tag; 446 iflib_dma_info_t ifl_ifdi; 447 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 448 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 449 } __aligned(CACHE_LINE_SIZE); 450 451 static inline qidx_t 452 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 453 { 454 qidx_t used; 455 456 if (pidx > cidx) 457 used = pidx - cidx; 458 else if (pidx < cidx) 459 used = size - cidx + pidx; 460 else if (gen == 0 && pidx == cidx) 461 used = 0; 462 else if (gen == 1 && pidx == cidx) 463 used = size; 464 else 465 panic("bad state"); 466 467 return (used); 468 } 469 470 #define TXQ_AVAIL(txq) ((txq->ift_size - txq->ift_pad) -\ 471 get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 472 473 #define IDXDIFF(head, tail, wrap) \ 474 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 475 476 struct iflib_rxq { 477 if_ctx_t ifr_ctx; 478 iflib_fl_t ifr_fl; 479 struct pfil_head *pfil; 480 /* 481 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 482 * the completion queue consumer index. Otherwise it's unused. 483 */ 484 qidx_t ifr_cq_cidx; 485 uint16_t ifr_id; 486 uint8_t ifr_nfl; 487 uint8_t ifr_ntxqirq; 488 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 489 uint8_t ifr_fl_offset; 490 struct lro_ctrl ifr_lc; 491 struct grouptask ifr_task; 492 struct callout ifr_watchdog; 493 struct iflib_filter_info ifr_filter_info; 494 iflib_dma_info_t ifr_ifdi; 495 496 /* dynamically allocate if any drivers need a value substantially larger than this */ 497 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 498 #ifdef IFLIB_DIAGNOSTICS 499 uint64_t ifr_cpu_exec_count[256]; 500 #endif 501 } __aligned(CACHE_LINE_SIZE); 502 503 typedef struct if_rxsd { 504 caddr_t *ifsd_cl; 505 iflib_fl_t ifsd_fl; 506 } *if_rxsd_t; 507 508 /* 509 * Only allow a single packet to take up most 1/nth of the tx ring 510 */ 511 #define MAX_SINGLE_PACKET_FRACTION 12 512 #define IF_BAD_DMA ((bus_addr_t)-1) 513 514 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 515 516 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 517 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 518 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 519 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 520 521 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 522 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 523 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 524 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 525 526 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 527 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 528 529 /* Our boot-time initialization hook */ 530 static int iflib_module_event_handler(module_t, int, void *); 531 532 static moduledata_t iflib_moduledata = { 533 "iflib", 534 iflib_module_event_handler, 535 NULL 536 }; 537 538 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 539 MODULE_VERSION(iflib, 1); 540 541 MODULE_DEPEND(iflib, pci, 1, 1, 1); 542 MODULE_DEPEND(iflib, ether, 1, 1, 1); 543 544 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 545 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 546 547 #ifndef IFLIB_DEBUG_COUNTERS 548 #ifdef INVARIANTS 549 #define IFLIB_DEBUG_COUNTERS 1 550 #else 551 #define IFLIB_DEBUG_COUNTERS 0 552 #endif /* !INVARIANTS */ 553 #endif 554 555 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 556 "iflib driver parameters"); 557 558 /* 559 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 560 */ 561 static int iflib_min_tx_latency = 0; 562 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 563 &iflib_min_tx_latency, 0, 564 "minimize transmit latency at the possible expense of throughput"); 565 static int iflib_no_tx_batch = 0; 566 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 567 &iflib_no_tx_batch, 0, 568 "minimize transmit latency at the possible expense of throughput"); 569 static int iflib_timer_default = 1000; 570 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW, 571 &iflib_timer_default, 0, "number of ticks between iflib_timer calls"); 572 573 574 #if IFLIB_DEBUG_COUNTERS 575 576 static int iflib_tx_seen; 577 static int iflib_tx_sent; 578 static int iflib_tx_encap; 579 static int iflib_rx_allocs; 580 static int iflib_fl_refills; 581 static int iflib_fl_refills_large; 582 static int iflib_tx_frees; 583 584 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, &iflib_tx_seen, 0, 585 "# TX mbufs seen"); 586 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, &iflib_tx_sent, 0, 587 "# TX mbufs sent"); 588 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, &iflib_tx_encap, 0, 589 "# TX mbufs encapped"); 590 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, &iflib_tx_frees, 0, 591 "# TX frees"); 592 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, &iflib_rx_allocs, 0, 593 "# RX allocations"); 594 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, &iflib_fl_refills, 0, 595 "# refills"); 596 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 597 &iflib_fl_refills_large, 0, "# large refills"); 598 599 static int iflib_txq_drain_flushing; 600 static int iflib_txq_drain_oactive; 601 static int iflib_txq_drain_notready; 602 603 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 604 &iflib_txq_drain_flushing, 0, "# drain flushes"); 605 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 606 &iflib_txq_drain_oactive, 0, "# drain oactives"); 607 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 608 &iflib_txq_drain_notready, 0, "# drain notready"); 609 610 static int iflib_encap_load_mbuf_fail; 611 static int iflib_encap_pad_mbuf_fail; 612 static int iflib_encap_txq_avail_fail; 613 static int iflib_encap_txd_encap_fail; 614 615 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 616 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 617 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 618 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 619 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 620 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 621 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 622 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 623 624 static int iflib_task_fn_rxs; 625 static int iflib_rx_intr_enables; 626 static int iflib_fast_intrs; 627 static int iflib_rx_unavail; 628 static int iflib_rx_ctx_inactive; 629 static int iflib_rx_if_input; 630 static int iflib_rxd_flush; 631 632 static int iflib_verbose_debug; 633 634 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, &iflib_task_fn_rxs, 0, 635 "# task_fn_rx calls"); 636 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 637 &iflib_rx_intr_enables, 0, "# RX intr enables"); 638 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, &iflib_fast_intrs, 0, 639 "# fast_intr calls"); 640 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, &iflib_rx_unavail, 0, 641 "# times rxeof called with no available data"); 642 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 643 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 644 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, &iflib_rx_if_input, 645 0, "# times rxeof called if_input"); 646 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, &iflib_rxd_flush, 0, 647 "# times rxd_flush called"); 648 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 649 &iflib_verbose_debug, 0, "enable verbose debugging"); 650 651 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 652 static void 653 iflib_debug_reset(void) 654 { 655 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 656 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 657 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 658 iflib_txq_drain_notready = 659 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 660 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 661 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 662 iflib_rx_unavail = 663 iflib_rx_ctx_inactive = iflib_rx_if_input = 664 iflib_rxd_flush = 0; 665 } 666 667 #else 668 #define DBG_COUNTER_INC(name) 669 static void iflib_debug_reset(void) {} 670 #endif 671 672 #define IFLIB_DEBUG 0 673 674 static void iflib_tx_structures_free(if_ctx_t ctx); 675 static void iflib_rx_structures_free(if_ctx_t ctx); 676 static int iflib_queues_alloc(if_ctx_t ctx); 677 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 678 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 679 static int iflib_qset_structures_setup(if_ctx_t ctx); 680 static int iflib_msix_init(if_ctx_t ctx); 681 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 682 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 683 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 684 #ifdef ALTQ 685 static void iflib_altq_if_start(if_t ifp); 686 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 687 #endif 688 static void iflib_register(if_ctx_t); 689 static void iflib_deregister(if_ctx_t); 690 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 691 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 692 static void iflib_init_locked(if_ctx_t ctx); 693 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 694 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 695 static void iflib_ifmp_purge(iflib_txq_t txq); 696 static void _iflib_pre_assert(if_softc_ctx_t scctx); 697 static void iflib_stop(if_ctx_t ctx); 698 static void iflib_if_init_locked(if_ctx_t ctx); 699 static void iflib_free_intr_mem(if_ctx_t ctx); 700 #ifndef __NO_STRICT_ALIGNMENT 701 static struct mbuf *iflib_fixup_rx(struct mbuf *m); 702 #endif 703 static __inline int iflib_completed_tx_reclaim(iflib_txq_t txq, 704 struct mbuf **m_defer); 705 static __inline void iflib_completed_tx_reclaim_force(iflib_txq_t txq); 706 707 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 708 SLIST_HEAD_INITIALIZER(cpu_offsets); 709 struct cpu_offset { 710 SLIST_ENTRY(cpu_offset) entries; 711 cpuset_t set; 712 unsigned int refcount; 713 uint16_t next_cpuid; 714 }; 715 static struct mtx cpu_offset_mtx; 716 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 717 MTX_DEF); 718 719 DEBUGNET_DEFINE(iflib); 720 721 static int 722 iflib_num_rx_descs(if_ctx_t ctx) 723 { 724 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 725 if_shared_ctx_t sctx = ctx->ifc_sctx; 726 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 727 728 return (scctx->isc_nrxd[first_rxq]); 729 } 730 731 static int 732 iflib_num_tx_descs(if_ctx_t ctx) 733 { 734 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 735 if_shared_ctx_t sctx = ctx->ifc_sctx; 736 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 737 738 return (scctx->isc_ntxd[first_txq]); 739 } 740 741 #ifdef DEV_NETMAP 742 #include <sys/selinfo.h> 743 #include <net/netmap.h> 744 #include <dev/netmap/netmap_kern.h> 745 746 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 747 748 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 749 static void iflib_netmap_timer(void *arg); 750 751 /* 752 * device-specific sysctl variables: 753 * 754 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 755 * During regular operations the CRC is stripped, but on some 756 * hardware reception of frames not multiple of 64 is slower, 757 * so using crcstrip=0 helps in benchmarks. 758 * 759 * iflib_rx_miss, iflib_rx_miss_bufs: 760 * count packets that might be missed due to lost interrupts. 761 */ 762 SYSCTL_DECL(_dev_netmap); 763 /* 764 * The xl driver by default strips CRCs and we do not override it. 765 */ 766 767 int iflib_crcstrip = 1; 768 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 769 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 770 771 int iflib_rx_miss, iflib_rx_miss_bufs; 772 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 773 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 774 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 775 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 776 777 /* 778 * Register/unregister. We are already under netmap lock. 779 * Only called on the first register or the last unregister. 780 */ 781 static int 782 iflib_netmap_register(struct netmap_adapter *na, int onoff) 783 { 784 if_t ifp = na->ifp; 785 if_ctx_t ctx = if_getsoftc(ifp); 786 int status; 787 788 CTX_LOCK(ctx); 789 if (!CTX_IS_VF(ctx)) 790 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 791 792 iflib_stop(ctx); 793 794 /* 795 * Enable (or disable) netmap flags, and intercept (or restore) 796 * ifp->if_transmit. This is done once the device has been stopped 797 * to prevent race conditions. Also, this must be done after 798 * calling netmap_disable_all_rings() and before calling 799 * netmap_enable_all_rings(), so that these two functions see the 800 * updated state of the NAF_NETMAP_ON bit. 801 */ 802 if (onoff) { 803 nm_set_native_flags(na); 804 } else { 805 nm_clear_native_flags(na); 806 } 807 808 iflib_init_locked(ctx); 809 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 810 status = if_getdrvflags(ifp) & IFF_DRV_RUNNING ? 0 : 1; 811 if (status) 812 nm_clear_native_flags(na); 813 CTX_UNLOCK(ctx); 814 return (status); 815 } 816 817 static int 818 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info) 819 { 820 if_t ifp = na->ifp; 821 if_ctx_t ctx = if_getsoftc(ifp); 822 iflib_rxq_t rxq = &ctx->ifc_rxqs[0]; 823 iflib_fl_t fl = &rxq->ifr_fl[0]; 824 825 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 826 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 827 info->num_tx_descs = iflib_num_tx_descs(ctx); 828 info->num_rx_descs = iflib_num_rx_descs(ctx); 829 info->rx_buf_maxsize = fl->ifl_buf_size; 830 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u", 831 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs, 832 info->num_rx_descs, info->rx_buf_maxsize); 833 834 return (0); 835 } 836 837 static int 838 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 839 { 840 struct netmap_adapter *na = kring->na; 841 u_int const lim = kring->nkr_num_slots - 1; 842 struct netmap_ring *ring = kring->ring; 843 bus_dmamap_t *map; 844 struct if_rxd_update iru; 845 if_ctx_t ctx = rxq->ifr_ctx; 846 iflib_fl_t fl = &rxq->ifr_fl[0]; 847 u_int nic_i_first, nic_i; 848 u_int nm_i; 849 int i, n; 850 #if IFLIB_DEBUG_COUNTERS 851 int rf_count = 0; 852 #endif 853 854 /* 855 * This function is used both at initialization and in rxsync. 856 * At initialization we need to prepare (with isc_rxd_refill()) 857 * all the netmap buffers currently owned by the kernel, in 858 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync 859 * (except for kring->nkr_hwofs). These may be less than 860 * kring->nkr_num_slots if netmap_reset() was called while 861 * an application using the kring that still owned some 862 * buffers. 863 * At rxsync time, both indexes point to the next buffer to be 864 * refilled. 865 * In any case we publish (with isc_rxd_flush()) up to 866 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 867 * pointer to overrun the head/cons pointer, although this is 868 * not necessary for some NICs (e.g. vmx). 869 */ 870 if (__predict_false(init)) { 871 n = kring->nkr_num_slots - nm_kr_rxspace(kring); 872 } else { 873 n = kring->rhead - kring->nr_hwcur; 874 if (n == 0) 875 return (0); /* Nothing to do. */ 876 if (n < 0) 877 n += kring->nkr_num_slots; 878 } 879 880 iru_init(&iru, rxq, 0 /* flid */); 881 map = fl->ifl_sds.ifsd_map; 882 nic_i = fl->ifl_pidx; 883 nm_i = netmap_idx_n2k(kring, nic_i); 884 if (__predict_false(init)) { 885 /* 886 * On init/reset, nic_i must be 0, and we must 887 * start to refill from hwtail (see netmap_reset()). 888 */ 889 MPASS(nic_i == 0); 890 MPASS(nm_i == kring->nr_hwtail); 891 } else 892 MPASS(nm_i == kring->nr_hwcur); 893 DBG_COUNTER_INC(fl_refills); 894 while (n > 0) { 895 #if IFLIB_DEBUG_COUNTERS 896 if (++rf_count == 9) 897 DBG_COUNTER_INC(fl_refills_large); 898 #endif 899 nic_i_first = nic_i; 900 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 901 struct netmap_slot *slot = &ring->slot[nm_i]; 902 uint64_t paddr; 903 void *addr = PNMB(na, slot, &paddr); 904 905 MPASS(i < IFLIB_MAX_RX_REFRESH); 906 907 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 908 return (netmap_ring_reinit(kring)); 909 910 fl->ifl_bus_addrs[i] = paddr + 911 nm_get_offset(kring, slot); 912 fl->ifl_rxd_idxs[i] = nic_i; 913 914 if (__predict_false(init)) { 915 netmap_load_map(na, fl->ifl_buf_tag, 916 map[nic_i], addr); 917 } else if (slot->flags & NS_BUF_CHANGED) { 918 /* buffer has changed, reload map */ 919 netmap_reload_map(na, fl->ifl_buf_tag, 920 map[nic_i], addr); 921 } 922 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 923 BUS_DMASYNC_PREREAD); 924 slot->flags &= ~NS_BUF_CHANGED; 925 926 nm_i = nm_next(nm_i, lim); 927 nic_i = nm_next(nic_i, lim); 928 } 929 930 iru.iru_pidx = nic_i_first; 931 iru.iru_count = i; 932 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 933 } 934 fl->ifl_pidx = nic_i; 935 /* 936 * At the end of the loop we must have refilled everything 937 * we could possibly refill. 938 */ 939 MPASS(nm_i == kring->rhead); 940 kring->nr_hwcur = nm_i; 941 942 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 943 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 944 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 945 nm_prev(nic_i, lim)); 946 DBG_COUNTER_INC(rxd_flush); 947 948 return (0); 949 } 950 951 #define NETMAP_TX_TIMER_US 90 952 953 /* 954 * Reconcile kernel and user view of the transmit ring. 955 * 956 * All information is in the kring. 957 * Userspace wants to send packets up to the one before kring->rhead, 958 * kernel knows kring->nr_hwcur is the first unsent packet. 959 * 960 * Here we push packets out (as many as possible), and possibly 961 * reclaim buffers from previously completed transmission. 962 * 963 * The caller (netmap) guarantees that there is only one instance 964 * running at any time. Any interference with other driver 965 * methods should be handled by the individual drivers. 966 */ 967 static int 968 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 969 { 970 struct netmap_adapter *na = kring->na; 971 if_t ifp = na->ifp; 972 struct netmap_ring *ring = kring->ring; 973 u_int nm_i; /* index into the netmap kring */ 974 u_int nic_i; /* index into the NIC ring */ 975 u_int const lim = kring->nkr_num_slots - 1; 976 u_int const head = kring->rhead; 977 struct if_pkt_info pi; 978 int tx_pkts = 0, tx_bytes = 0; 979 980 /* 981 * interrupts on every tx packet are expensive so request 982 * them every half ring, or where NS_REPORT is set 983 */ 984 u_int report_frequency = kring->nkr_num_slots >> 1; 985 /* device-specific */ 986 if_ctx_t ctx = if_getsoftc(ifp); 987 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 988 989 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 990 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 991 992 /* 993 * First part: process new packets to send. 994 * nm_i is the current index in the netmap kring, 995 * nic_i is the corresponding index in the NIC ring. 996 * 997 * If we have packets to send (nm_i != head) 998 * iterate over the netmap ring, fetch length and update 999 * the corresponding slot in the NIC ring. Some drivers also 1000 * need to update the buffer's physical address in the NIC slot 1001 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 1002 * 1003 * The netmap_reload_map() calls is especially expensive, 1004 * even when (as in this case) the tag is 0, so do only 1005 * when the buffer has actually changed. 1006 * 1007 * If possible do not set the report/intr bit on all slots, 1008 * but only a few times per ring or when NS_REPORT is set. 1009 * 1010 * Finally, on 10G and faster drivers, it might be useful 1011 * to prefetch the next slot and txr entry. 1012 */ 1013 1014 nm_i = kring->nr_hwcur; 1015 if (nm_i != head) { /* we have new packets to send */ 1016 uint32_t pkt_len = 0, seg_idx = 0; 1017 int nic_i_start = -1, flags = 0; 1018 memset(&pi, 0, sizeof(pi)); 1019 pi.ipi_segs = txq->ift_segs; 1020 pi.ipi_qsidx = kring->ring_id; 1021 nic_i = netmap_idx_k2n(kring, nm_i); 1022 1023 __builtin_prefetch(&ring->slot[nm_i]); 1024 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 1025 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 1026 1027 while (nm_i != head) { 1028 struct netmap_slot *slot = &ring->slot[nm_i]; 1029 uint64_t offset = nm_get_offset(kring, slot); 1030 u_int len = slot->len; 1031 uint64_t paddr; 1032 void *addr = PNMB(na, slot, &paddr); 1033 1034 flags |= (slot->flags & NS_REPORT || 1035 nic_i == 0 || nic_i == report_frequency) ? 1036 IPI_TX_INTR : 0; 1037 1038 /* 1039 * If this is the first packet fragment, save the 1040 * index of the first NIC slot for later. 1041 */ 1042 if (nic_i_start < 0) 1043 nic_i_start = nic_i; 1044 1045 pi.ipi_segs[seg_idx].ds_addr = paddr + offset; 1046 pi.ipi_segs[seg_idx].ds_len = len; 1047 if (len) { 1048 pkt_len += len; 1049 seg_idx++; 1050 } 1051 1052 if (!(slot->flags & NS_MOREFRAG)) { 1053 pi.ipi_len = pkt_len; 1054 pi.ipi_nsegs = seg_idx; 1055 pi.ipi_pidx = nic_i_start; 1056 pi.ipi_ndescs = 0; 1057 pi.ipi_flags = flags; 1058 1059 /* Prepare the NIC TX ring. */ 1060 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1061 DBG_COUNTER_INC(tx_encap); 1062 1063 /* Update transmit counters */ 1064 tx_bytes += pi.ipi_len; 1065 tx_pkts++; 1066 1067 /* Reinit per-packet info for the next one. */ 1068 flags = seg_idx = pkt_len = 0; 1069 nic_i_start = -1; 1070 } 1071 1072 /* prefetch for next round */ 1073 __builtin_prefetch(&ring->slot[nm_i + 1]); 1074 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1075 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1076 1077 NM_CHECK_ADDR_LEN_OFF(na, len, offset); 1078 1079 if (slot->flags & NS_BUF_CHANGED) { 1080 /* buffer has changed, reload map */ 1081 netmap_reload_map(na, txq->ift_buf_tag, 1082 txq->ift_sds.ifsd_map[nic_i], addr); 1083 } 1084 /* make sure changes to the buffer are synced */ 1085 bus_dmamap_sync(txq->ift_buf_tag, 1086 txq->ift_sds.ifsd_map[nic_i], 1087 BUS_DMASYNC_PREWRITE); 1088 1089 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG); 1090 nm_i = nm_next(nm_i, lim); 1091 nic_i = nm_next(nic_i, lim); 1092 } 1093 kring->nr_hwcur = nm_i; 1094 1095 /* synchronize the NIC ring */ 1096 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1097 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1098 1099 /* (re)start the tx unit up to slot nic_i (excluded) */ 1100 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1101 } 1102 1103 /* 1104 * Second part: reclaim buffers for completed transmissions. 1105 * 1106 * If there are unclaimed buffers, attempt to reclaim them. 1107 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1108 * trigger a per-tx-queue timer to try again later. 1109 */ 1110 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1111 if (iflib_tx_credits_update(ctx, txq)) { 1112 /* some tx completed, increment avail */ 1113 nic_i = txq->ift_cidx_processed; 1114 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1115 } 1116 } 1117 1118 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1119 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1120 callout_reset_sbt_on(&txq->ift_netmap_timer, 1121 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1122 iflib_netmap_timer, txq, 1123 txq->ift_netmap_timer.c_cpu, 0); 1124 } 1125 1126 if_inc_counter(ifp, IFCOUNTER_OBYTES, tx_bytes); 1127 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tx_pkts); 1128 1129 return (0); 1130 } 1131 1132 /* 1133 * Reconcile kernel and user view of the receive ring. 1134 * Same as for the txsync, this routine must be efficient. 1135 * The caller guarantees a single invocations, but races against 1136 * the rest of the driver should be handled here. 1137 * 1138 * On call, kring->rhead is the first packet that userspace wants 1139 * to keep, and kring->rcur is the wakeup point. 1140 * The kernel has previously reported packets up to kring->rtail. 1141 * 1142 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1143 * of whether or not we received an interrupt. 1144 */ 1145 static int 1146 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1147 { 1148 struct netmap_adapter *na = kring->na; 1149 struct netmap_ring *ring = kring->ring; 1150 if_t ifp = na->ifp; 1151 uint32_t nm_i; /* index into the netmap ring */ 1152 uint32_t nic_i; /* index into the NIC ring */ 1153 u_int n; 1154 u_int const lim = kring->nkr_num_slots - 1; 1155 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1156 int i = 0, rx_bytes = 0, rx_pkts = 0; 1157 1158 if_ctx_t ctx = if_getsoftc(ifp); 1159 if_shared_ctx_t sctx = ctx->ifc_sctx; 1160 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1161 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1162 iflib_fl_t fl = &rxq->ifr_fl[0]; 1163 struct if_rxd_info ri; 1164 qidx_t *cidxp; 1165 1166 /* 1167 * netmap only uses free list 0, to avoid out of order consumption 1168 * of receive buffers 1169 */ 1170 1171 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1172 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1173 1174 /* 1175 * First part: import newly received packets. 1176 * 1177 * nm_i is the index of the next free slot in the netmap ring, 1178 * nic_i is the index of the next received packet in the NIC ring 1179 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1180 * differ in case if_init() has been called while 1181 * in netmap mode. For the receive ring we have 1182 * 1183 * nic_i = fl->ifl_cidx; 1184 * nm_i = kring->nr_hwtail (previous) 1185 * and 1186 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1187 * 1188 * fl->ifl_cidx is set to 0 on a ring reinit 1189 */ 1190 if (netmap_no_pendintr || force_update) { 1191 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1192 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1193 int crclen = iflib_crcstrip ? 0 : 4; 1194 int error, avail; 1195 1196 /* 1197 * For the free list consumer index, we use the same 1198 * logic as in iflib_rxeof(). 1199 */ 1200 if (have_rxcq) 1201 cidxp = &rxq->ifr_cq_cidx; 1202 else 1203 cidxp = &fl->ifl_cidx; 1204 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1205 rxq->ifr_id, *cidxp, USHRT_MAX); 1206 1207 nic_i = fl->ifl_cidx; 1208 nm_i = netmap_idx_n2k(kring, nic_i); 1209 MPASS(nm_i == kring->nr_hwtail); 1210 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1211 memset(&ri, 0, sizeof(ri)); 1212 ri.iri_frags = rxq->ifr_frags; 1213 ri.iri_qsidx = kring->ring_id; 1214 ri.iri_ifp = ctx->ifc_ifp; 1215 ri.iri_cidx = *cidxp; 1216 1217 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1218 for (i = 0; i < ri.iri_nfrags; i++) { 1219 if (error) { 1220 ring->slot[nm_i].len = 0; 1221 ring->slot[nm_i].flags = 0; 1222 } else { 1223 ring->slot[nm_i].len = ri.iri_frags[i].irf_len; 1224 if (i == (ri.iri_nfrags - 1)) { 1225 ring->slot[nm_i].len -= crclen; 1226 ring->slot[nm_i].flags = 0; 1227 1228 /* Update receive counters */ 1229 rx_bytes += ri.iri_len; 1230 rx_pkts++; 1231 } else 1232 ring->slot[nm_i].flags = NS_MOREFRAG; 1233 } 1234 1235 bus_dmamap_sync(fl->ifl_buf_tag, 1236 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1237 nm_i = nm_next(nm_i, lim); 1238 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1239 } 1240 1241 if (have_rxcq) { 1242 *cidxp = ri.iri_cidx; 1243 while (*cidxp >= scctx->isc_nrxd[0]) 1244 *cidxp -= scctx->isc_nrxd[0]; 1245 } 1246 1247 } 1248 if (n) { /* update the state variables */ 1249 if (netmap_no_pendintr && !force_update) { 1250 /* diagnostics */ 1251 iflib_rx_miss++; 1252 iflib_rx_miss_bufs += n; 1253 } 1254 kring->nr_hwtail = nm_i; 1255 } 1256 kring->nr_kflags &= ~NKR_PENDINTR; 1257 } 1258 /* 1259 * Second part: skip past packets that userspace has released. 1260 * (kring->nr_hwcur to head excluded), 1261 * and make the buffers available for reception. 1262 * As usual nm_i is the index in the netmap ring, 1263 * nic_i is the index in the NIC ring, and 1264 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1265 */ 1266 netmap_fl_refill(rxq, kring, false); 1267 1268 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 1269 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 1270 1271 return (0); 1272 } 1273 1274 static void 1275 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1276 { 1277 if_ctx_t ctx = if_getsoftc(na->ifp); 1278 1279 CTX_LOCK(ctx); 1280 if (onoff) { 1281 IFDI_INTR_ENABLE(ctx); 1282 } else { 1283 IFDI_INTR_DISABLE(ctx); 1284 } 1285 CTX_UNLOCK(ctx); 1286 } 1287 1288 static int 1289 iflib_netmap_attach(if_ctx_t ctx) 1290 { 1291 struct netmap_adapter na; 1292 1293 bzero(&na, sizeof(na)); 1294 1295 na.ifp = ctx->ifc_ifp; 1296 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS; 1297 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1298 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1299 1300 na.num_tx_desc = iflib_num_tx_descs(ctx); 1301 na.num_rx_desc = iflib_num_rx_descs(ctx); 1302 na.nm_txsync = iflib_netmap_txsync; 1303 na.nm_rxsync = iflib_netmap_rxsync; 1304 na.nm_register = iflib_netmap_register; 1305 na.nm_intr = iflib_netmap_intr; 1306 na.nm_config = iflib_netmap_config; 1307 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1308 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1309 return (netmap_attach(&na)); 1310 } 1311 1312 static int 1313 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1314 { 1315 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1316 struct netmap_slot *slot; 1317 1318 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1319 if (slot == NULL) 1320 return (0); 1321 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1322 /* 1323 * In netmap mode, set the map for the packet buffer. 1324 * NOTE: Some drivers (not this one) also need to set 1325 * the physical buffer address in the NIC ring. 1326 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1327 * netmap slot index, si 1328 */ 1329 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1330 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1331 NMB(na, slot + si)); 1332 } 1333 return (1); 1334 } 1335 1336 static int 1337 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1338 { 1339 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1340 struct netmap_kring *kring; 1341 struct netmap_slot *slot; 1342 1343 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1344 if (slot == NULL) 1345 return (0); 1346 kring = na->rx_rings[rxq->ifr_id]; 1347 netmap_fl_refill(rxq, kring, true); 1348 return (1); 1349 } 1350 1351 static void 1352 iflib_netmap_timer(void *arg) 1353 { 1354 iflib_txq_t txq = arg; 1355 if_ctx_t ctx = txq->ift_ctx; 1356 1357 /* 1358 * Wake up the netmap application, to give it a chance to 1359 * call txsync and reclaim more completed TX buffers. 1360 */ 1361 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1362 } 1363 1364 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1365 1366 #else 1367 #define iflib_netmap_txq_init(ctx, txq) (0) 1368 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1369 #define iflib_netmap_detach(ifp) 1370 #define netmap_enable_all_rings(ifp) 1371 #define netmap_disable_all_rings(ifp) 1372 1373 #define iflib_netmap_attach(ctx) (0) 1374 #define netmap_rx_irq(ifp, qid, budget) (0) 1375 #endif 1376 1377 #if defined(__i386__) || defined(__amd64__) 1378 static __inline void 1379 prefetch(void *x) 1380 { 1381 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1382 } 1383 1384 static __inline void 1385 prefetch2cachelines(void *x) 1386 { 1387 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1388 #if (CACHE_LINE_SIZE < 128) 1389 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x) + CACHE_LINE_SIZE / (sizeof(unsigned long))))); 1390 #endif 1391 } 1392 #else 1393 static __inline void 1394 prefetch(void *x) 1395 { 1396 } 1397 1398 static __inline void 1399 prefetch2cachelines(void *x) 1400 { 1401 } 1402 #endif 1403 1404 static void 1405 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1406 { 1407 iflib_fl_t fl; 1408 1409 fl = &rxq->ifr_fl[flid]; 1410 iru->iru_paddrs = fl->ifl_bus_addrs; 1411 iru->iru_idxs = fl->ifl_rxd_idxs; 1412 iru->iru_qsidx = rxq->ifr_id; 1413 iru->iru_buf_size = fl->ifl_buf_size; 1414 iru->iru_flidx = fl->ifl_id; 1415 } 1416 1417 static void 1418 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1419 { 1420 if (err) 1421 return; 1422 *(bus_addr_t *) arg = segs[0].ds_addr; 1423 } 1424 1425 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \ 1426 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \ 1427 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL) 1428 1429 int 1430 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1431 { 1432 int err; 1433 device_t dev = ctx->ifc_dev; 1434 bus_addr_t lowaddr; 1435 1436 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width); 1437 1438 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1439 align, 0, /* alignment, bounds */ 1440 lowaddr, /* lowaddr */ 1441 BUS_SPACE_MAXADDR, /* highaddr */ 1442 NULL, NULL, /* filter, filterarg */ 1443 size, /* maxsize */ 1444 1, /* nsegments */ 1445 size, /* maxsegsize */ 1446 BUS_DMA_ALLOCNOW, /* flags */ 1447 NULL, /* lockfunc */ 1448 NULL, /* lockarg */ 1449 &dma->idi_tag); 1450 if (err) { 1451 device_printf(dev, 1452 "%s: bus_dma_tag_create failed: %d (size=%d, align=%d)\n", 1453 __func__, err, size, align); 1454 goto fail_0; 1455 } 1456 1457 err = bus_dmamem_alloc(dma->idi_tag, (void **)&dma->idi_vaddr, 1458 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1459 if (err) { 1460 device_printf(dev, 1461 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1462 __func__, (uintmax_t)size, err); 1463 goto fail_1; 1464 } 1465 1466 dma->idi_paddr = IF_BAD_DMA; 1467 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1468 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1469 if (err || dma->idi_paddr == IF_BAD_DMA) { 1470 device_printf(dev, 1471 "%s: bus_dmamap_load failed: %d\n", 1472 __func__, err); 1473 goto fail_2; 1474 } 1475 1476 dma->idi_size = size; 1477 return (0); 1478 1479 fail_2: 1480 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1481 fail_1: 1482 bus_dma_tag_destroy(dma->idi_tag); 1483 fail_0: 1484 dma->idi_tag = NULL; 1485 1486 return (err); 1487 } 1488 1489 int 1490 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1491 { 1492 if_shared_ctx_t sctx = ctx->ifc_sctx; 1493 1494 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1495 1496 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1497 } 1498 1499 int 1500 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1501 { 1502 int i, err; 1503 iflib_dma_info_t *dmaiter; 1504 1505 dmaiter = dmalist; 1506 for (i = 0; i < count; i++, dmaiter++) { 1507 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1508 break; 1509 } 1510 if (err) 1511 iflib_dma_free_multi(dmalist, i); 1512 return (err); 1513 } 1514 1515 void 1516 iflib_dma_free(iflib_dma_info_t dma) 1517 { 1518 if (dma->idi_tag == NULL) 1519 return; 1520 if (dma->idi_paddr != IF_BAD_DMA) { 1521 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1522 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1523 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1524 dma->idi_paddr = IF_BAD_DMA; 1525 } 1526 if (dma->idi_vaddr != NULL) { 1527 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1528 dma->idi_vaddr = NULL; 1529 } 1530 bus_dma_tag_destroy(dma->idi_tag); 1531 dma->idi_tag = NULL; 1532 } 1533 1534 void 1535 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1536 { 1537 int i; 1538 iflib_dma_info_t *dmaiter = dmalist; 1539 1540 for (i = 0; i < count; i++, dmaiter++) 1541 iflib_dma_free(*dmaiter); 1542 } 1543 1544 static int 1545 iflib_fast_intr(void *arg) 1546 { 1547 iflib_filter_info_t info = arg; 1548 struct grouptask *gtask = info->ifi_task; 1549 int result; 1550 1551 DBG_COUNTER_INC(fast_intrs); 1552 if (info->ifi_filter != NULL) { 1553 result = info->ifi_filter(info->ifi_filter_arg); 1554 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1555 return (result); 1556 } 1557 1558 GROUPTASK_ENQUEUE(gtask); 1559 return (FILTER_HANDLED); 1560 } 1561 1562 static int 1563 iflib_fast_intr_rxtx(void *arg) 1564 { 1565 iflib_filter_info_t info = arg; 1566 struct grouptask *gtask = info->ifi_task; 1567 if_ctx_t ctx; 1568 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1569 iflib_txq_t txq; 1570 void *sc; 1571 int i, cidx, result; 1572 qidx_t txqid; 1573 bool intr_enable, intr_legacy; 1574 1575 DBG_COUNTER_INC(fast_intrs); 1576 if (info->ifi_filter != NULL) { 1577 result = info->ifi_filter(info->ifi_filter_arg); 1578 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1579 return (result); 1580 } 1581 1582 ctx = rxq->ifr_ctx; 1583 sc = ctx->ifc_softc; 1584 intr_enable = false; 1585 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1586 MPASS(rxq->ifr_ntxqirq); 1587 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1588 txqid = rxq->ifr_txqid[i]; 1589 txq = &ctx->ifc_txqs[txqid]; 1590 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1591 BUS_DMASYNC_POSTREAD); 1592 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1593 if (intr_legacy) 1594 intr_enable = true; 1595 else 1596 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1597 continue; 1598 } 1599 GROUPTASK_ENQUEUE(&txq->ift_task); 1600 } 1601 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1602 cidx = rxq->ifr_cq_cidx; 1603 else 1604 cidx = rxq->ifr_fl[0].ifl_cidx; 1605 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1606 GROUPTASK_ENQUEUE(gtask); 1607 else { 1608 if (intr_legacy) 1609 intr_enable = true; 1610 else 1611 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1612 DBG_COUNTER_INC(rx_intr_enables); 1613 } 1614 if (intr_enable) 1615 IFDI_INTR_ENABLE(ctx); 1616 return (FILTER_HANDLED); 1617 } 1618 1619 static int 1620 iflib_fast_intr_ctx(void *arg) 1621 { 1622 iflib_filter_info_t info = arg; 1623 if_ctx_t ctx = info->ifi_ctx; 1624 int result; 1625 1626 DBG_COUNTER_INC(fast_intrs); 1627 if (info->ifi_filter != NULL) { 1628 result = info->ifi_filter(info->ifi_filter_arg); 1629 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1630 return (result); 1631 } 1632 1633 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_admin_task); 1634 return (FILTER_HANDLED); 1635 } 1636 1637 static int 1638 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1639 driver_filter_t filter, driver_intr_t handler, void *arg, 1640 const char *name) 1641 { 1642 struct resource *res; 1643 void *tag = NULL; 1644 device_t dev = ctx->ifc_dev; 1645 int flags, i, rc; 1646 1647 flags = RF_ACTIVE; 1648 if (ctx->ifc_flags & IFC_LEGACY) 1649 flags |= RF_SHAREABLE; 1650 MPASS(rid < 512); 1651 i = rid; 1652 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1653 if (res == NULL) { 1654 device_printf(dev, 1655 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1656 return (ENOMEM); 1657 } 1658 irq->ii_res = res; 1659 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1660 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1661 filter, handler, arg, &tag); 1662 if (rc != 0) { 1663 device_printf(dev, 1664 "failed to setup interrupt for rid %d, name %s: %d\n", 1665 rid, name ? name : "unknown", rc); 1666 return (rc); 1667 } else if (name) 1668 bus_describe_intr(dev, res, tag, "%s", name); 1669 1670 irq->ii_tag = tag; 1671 return (0); 1672 } 1673 1674 /********************************************************************* 1675 * 1676 * Allocate DMA resources for TX buffers as well as memory for the TX 1677 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1678 * iflib_sw_tx_desc_array structure, storing all the information that 1679 * is needed to transmit a packet on the wire. This is called only 1680 * once at attach, setup is done every reset. 1681 * 1682 **********************************************************************/ 1683 static int 1684 iflib_txsd_alloc(iflib_txq_t txq) 1685 { 1686 if_ctx_t ctx = txq->ift_ctx; 1687 if_shared_ctx_t sctx = ctx->ifc_sctx; 1688 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1689 device_t dev = ctx->ifc_dev; 1690 bus_size_t tsomaxsize; 1691 bus_addr_t lowaddr; 1692 int err, nsegments, ntsosegments; 1693 bool tso; 1694 1695 nsegments = scctx->isc_tx_nsegments; 1696 ntsosegments = scctx->isc_tx_tso_segments_max; 1697 tsomaxsize = scctx->isc_tx_tso_size_max; 1698 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1699 tsomaxsize += sizeof(struct ether_vlan_header); 1700 MPASS(scctx->isc_ntxd[0] > 0); 1701 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1702 MPASS(nsegments > 0); 1703 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1704 MPASS(ntsosegments > 0); 1705 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1706 } 1707 1708 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1709 1710 /* 1711 * Set up DMA tags for TX buffers. 1712 */ 1713 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1714 1, 0, /* alignment, bounds */ 1715 lowaddr, /* lowaddr */ 1716 BUS_SPACE_MAXADDR, /* highaddr */ 1717 NULL, NULL, /* filter, filterarg */ 1718 sctx->isc_tx_maxsize, /* maxsize */ 1719 nsegments, /* nsegments */ 1720 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1721 0, /* flags */ 1722 NULL, /* lockfunc */ 1723 NULL, /* lockfuncarg */ 1724 &txq->ift_buf_tag))) { 1725 device_printf(dev, "Unable to allocate TX DMA tag: %d\n", err); 1726 device_printf(dev, "maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1727 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1728 goto fail; 1729 } 1730 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1731 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1732 1, 0, /* alignment, bounds */ 1733 lowaddr, /* lowaddr */ 1734 BUS_SPACE_MAXADDR, /* highaddr */ 1735 NULL, NULL, /* filter, filterarg */ 1736 tsomaxsize, /* maxsize */ 1737 ntsosegments, /* nsegments */ 1738 sctx->isc_tso_maxsegsize, /* maxsegsize */ 1739 0, /* flags */ 1740 NULL, /* lockfunc */ 1741 NULL, /* lockfuncarg */ 1742 &txq->ift_tso_buf_tag))) { 1743 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1744 err); 1745 goto fail; 1746 } 1747 1748 /* Allocate memory for the TX mbuf map. */ 1749 if (!(txq->ift_sds.ifsd_m = 1750 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1751 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1752 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1753 err = ENOMEM; 1754 goto fail; 1755 } 1756 if (ctx->ifc_sysctl_simple_tx) { 1757 if (!(txq->ift_sds.ifsd_m_defer = 1758 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1759 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1760 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1761 err = ENOMEM; 1762 goto fail; 1763 } 1764 } 1765 txq->ift_sds.ifsd_m_deferb = txq->ift_sds.ifsd_m_defer; 1766 /* 1767 * Create the DMA maps for TX buffers. 1768 */ 1769 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1770 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1771 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1772 device_printf(dev, 1773 "Unable to allocate TX buffer DMA map memory\n"); 1774 err = ENOMEM; 1775 goto fail; 1776 } 1777 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1778 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1779 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1780 device_printf(dev, 1781 "Unable to allocate TSO TX buffer map memory\n"); 1782 err = ENOMEM; 1783 goto fail; 1784 } 1785 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1786 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1787 &txq->ift_sds.ifsd_map[i]); 1788 if (err != 0) { 1789 device_printf(dev, "Unable to create TX DMA map\n"); 1790 goto fail; 1791 } 1792 if (!tso) 1793 continue; 1794 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1795 &txq->ift_sds.ifsd_tso_map[i]); 1796 if (err != 0) { 1797 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1798 goto fail; 1799 } 1800 } 1801 return (0); 1802 fail: 1803 /* We free all, it handles case where we are in the middle */ 1804 iflib_tx_structures_free(ctx); 1805 return (err); 1806 } 1807 1808 static void 1809 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1810 { 1811 bus_dmamap_t map; 1812 1813 if (txq->ift_sds.ifsd_map != NULL) { 1814 map = txq->ift_sds.ifsd_map[i]; 1815 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1816 bus_dmamap_unload(txq->ift_buf_tag, map); 1817 bus_dmamap_destroy(txq->ift_buf_tag, map); 1818 txq->ift_sds.ifsd_map[i] = NULL; 1819 } 1820 1821 if (txq->ift_sds.ifsd_tso_map != NULL) { 1822 map = txq->ift_sds.ifsd_tso_map[i]; 1823 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1824 BUS_DMASYNC_POSTWRITE); 1825 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1826 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1827 txq->ift_sds.ifsd_tso_map[i] = NULL; 1828 } 1829 } 1830 1831 static void 1832 iflib_txq_destroy(iflib_txq_t txq) 1833 { 1834 if_ctx_t ctx = txq->ift_ctx; 1835 1836 for (int i = 0; i < txq->ift_size; i++) 1837 iflib_txsd_destroy(ctx, txq, i); 1838 1839 if (txq->ift_br != NULL) { 1840 ifmp_ring_free(txq->ift_br); 1841 txq->ift_br = NULL; 1842 } 1843 1844 mtx_destroy(&txq->ift_mtx); 1845 1846 if (txq->ift_sds.ifsd_map != NULL) { 1847 free(txq->ift_sds.ifsd_map, M_IFLIB); 1848 txq->ift_sds.ifsd_map = NULL; 1849 } 1850 if (txq->ift_sds.ifsd_tso_map != NULL) { 1851 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1852 txq->ift_sds.ifsd_tso_map = NULL; 1853 } 1854 if (txq->ift_sds.ifsd_m != NULL) { 1855 free(txq->ift_sds.ifsd_m, M_IFLIB); 1856 txq->ift_sds.ifsd_m = NULL; 1857 } 1858 if (txq->ift_sds.ifsd_m_defer != NULL) { 1859 free(txq->ift_sds.ifsd_m_defer, M_IFLIB); 1860 txq->ift_sds.ifsd_m_defer = NULL; 1861 } 1862 if (txq->ift_buf_tag != NULL) { 1863 bus_dma_tag_destroy(txq->ift_buf_tag); 1864 txq->ift_buf_tag = NULL; 1865 } 1866 if (txq->ift_tso_buf_tag != NULL) { 1867 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1868 txq->ift_tso_buf_tag = NULL; 1869 } 1870 if (txq->ift_ifdi != NULL) { 1871 free(txq->ift_ifdi, M_IFLIB); 1872 } 1873 } 1874 1875 static void 1876 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1877 { 1878 struct mbuf *m; 1879 1880 m = IFLIB_GET_MBUF(txq->ift_sds.ifsd_m[i]); 1881 if (m == NULL) 1882 return; 1883 1884 if (txq->ift_sds.ifsd_map != NULL) { 1885 bus_dmamap_sync(txq->ift_buf_tag, 1886 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1887 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1888 } 1889 if (txq->ift_sds.ifsd_tso_map != NULL) { 1890 bus_dmamap_sync(txq->ift_tso_buf_tag, 1891 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1892 bus_dmamap_unload(txq->ift_tso_buf_tag, 1893 txq->ift_sds.ifsd_tso_map[i]); 1894 } 1895 txq->ift_sds.ifsd_m[i] = NULL; 1896 m_freem(m); 1897 DBG_COUNTER_INC(tx_frees); 1898 } 1899 1900 static int 1901 iflib_txq_setup(iflib_txq_t txq) 1902 { 1903 if_ctx_t ctx = txq->ift_ctx; 1904 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1905 if_shared_ctx_t sctx = ctx->ifc_sctx; 1906 iflib_dma_info_t di; 1907 int i; 1908 1909 /* Set number of descriptors available */ 1910 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1911 /* XXX make configurable */ 1912 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1913 1914 /* Reset indices */ 1915 txq->ift_cidx_processed = 0; 1916 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1917 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1918 txq->ift_pad = scctx->isc_tx_pad; 1919 1920 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1921 bzero((void *)di->idi_vaddr, di->idi_size); 1922 1923 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1924 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1925 bus_dmamap_sync(di->idi_tag, di->idi_map, 1926 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1927 return (0); 1928 } 1929 1930 /********************************************************************* 1931 * 1932 * Allocate DMA resources for RX buffers as well as memory for the RX 1933 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1934 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1935 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1936 * Since we use use one entry in iflib_sw_rx_desc_array per received 1937 * packet, the maximum number of entries we'll need is equal to the 1938 * number of hardware receive descriptors that we've allocated. 1939 * 1940 **********************************************************************/ 1941 static int 1942 iflib_rxsd_alloc(iflib_rxq_t rxq) 1943 { 1944 if_ctx_t ctx = rxq->ifr_ctx; 1945 if_shared_ctx_t sctx = ctx->ifc_sctx; 1946 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1947 device_t dev = ctx->ifc_dev; 1948 iflib_fl_t fl; 1949 bus_addr_t lowaddr; 1950 int err; 1951 1952 MPASS(scctx->isc_nrxd[0] > 0); 1953 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1954 1955 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1956 1957 fl = rxq->ifr_fl; 1958 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1959 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1960 /* Set up DMA tag for RX buffers. */ 1961 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1962 1, 0, /* alignment, bounds */ 1963 lowaddr, /* lowaddr */ 1964 BUS_SPACE_MAXADDR, /* highaddr */ 1965 NULL, NULL, /* filter, filterarg */ 1966 sctx->isc_rx_maxsize, /* maxsize */ 1967 sctx->isc_rx_nsegments, /* nsegments */ 1968 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1969 0, /* flags */ 1970 NULL, /* lockfunc */ 1971 NULL, /* lockarg */ 1972 &fl->ifl_buf_tag); 1973 if (err) { 1974 device_printf(dev, 1975 "Unable to allocate RX DMA tag: %d\n", err); 1976 goto fail; 1977 } 1978 1979 /* Allocate memory for the RX mbuf map. */ 1980 if (!(fl->ifl_sds.ifsd_m = 1981 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1982 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1983 device_printf(dev, 1984 "Unable to allocate RX mbuf map memory\n"); 1985 err = ENOMEM; 1986 goto fail; 1987 } 1988 1989 /* Allocate memory for the direct RX cluster pointer map. */ 1990 if (!(fl->ifl_sds.ifsd_cl = 1991 (caddr_t *) malloc(sizeof(caddr_t) * 1992 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1993 device_printf(dev, 1994 "Unable to allocate RX cluster map memory\n"); 1995 err = ENOMEM; 1996 goto fail; 1997 } 1998 1999 /* Allocate memory for the RX cluster bus address map. */ 2000 if (!(fl->ifl_sds.ifsd_ba = 2001 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 2002 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2003 device_printf(dev, 2004 "Unable to allocate RX bus address map memory\n"); 2005 err = ENOMEM; 2006 goto fail; 2007 } 2008 2009 /* 2010 * Create the DMA maps for RX buffers. 2011 */ 2012 if (!(fl->ifl_sds.ifsd_map = 2013 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2014 device_printf(dev, 2015 "Unable to allocate RX buffer DMA map memory\n"); 2016 err = ENOMEM; 2017 goto fail; 2018 } 2019 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 2020 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 2021 &fl->ifl_sds.ifsd_map[i]); 2022 if (err != 0) { 2023 device_printf(dev, "Unable to create RX buffer DMA map\n"); 2024 goto fail; 2025 } 2026 } 2027 } 2028 return (0); 2029 2030 fail: 2031 iflib_rx_structures_free(ctx); 2032 return (err); 2033 } 2034 2035 /* 2036 * Internal service routines 2037 */ 2038 2039 struct rxq_refill_cb_arg { 2040 int error; 2041 bus_dma_segment_t seg; 2042 int nseg; 2043 }; 2044 2045 static void 2046 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2047 { 2048 struct rxq_refill_cb_arg *cb_arg = arg; 2049 2050 cb_arg->error = error; 2051 cb_arg->seg = segs[0]; 2052 cb_arg->nseg = nseg; 2053 } 2054 2055 /** 2056 * iflib_fl_refill - refill an rxq free-buffer list 2057 * @ctx: the iflib context 2058 * @fl: the free list to refill 2059 * @count: the number of new buffers to allocate 2060 * 2061 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 2062 * The caller must assure that @count does not exceed the queue's capacity 2063 * minus one (since we always leave a descriptor unavailable). 2064 */ 2065 static uint8_t 2066 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 2067 { 2068 struct if_rxd_update iru; 2069 struct rxq_refill_cb_arg cb_arg; 2070 struct mbuf *m; 2071 caddr_t cl, *sd_cl; 2072 struct mbuf **sd_m; 2073 bus_dmamap_t *sd_map; 2074 bus_addr_t bus_addr, *sd_ba; 2075 int err, frag_idx, i, idx, n, pidx; 2076 qidx_t credits; 2077 2078 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 2079 2080 sd_m = fl->ifl_sds.ifsd_m; 2081 sd_map = fl->ifl_sds.ifsd_map; 2082 sd_cl = fl->ifl_sds.ifsd_cl; 2083 sd_ba = fl->ifl_sds.ifsd_ba; 2084 pidx = fl->ifl_pidx; 2085 idx = pidx; 2086 frag_idx = fl->ifl_fragidx; 2087 credits = fl->ifl_credits; 2088 2089 i = 0; 2090 n = count; 2091 MPASS(n > 0); 2092 MPASS(credits + n <= fl->ifl_size); 2093 2094 if (pidx < fl->ifl_cidx) 2095 MPASS(pidx + n <= fl->ifl_cidx); 2096 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 2097 MPASS(fl->ifl_gen == 0); 2098 if (pidx > fl->ifl_cidx) 2099 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 2100 2101 DBG_COUNTER_INC(fl_refills); 2102 if (n > 8) 2103 DBG_COUNTER_INC(fl_refills_large); 2104 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 2105 while (n-- > 0) { 2106 /* 2107 * We allocate an uninitialized mbuf + cluster, mbuf is 2108 * initialized after rx. 2109 * 2110 * If the cluster is still set then we know a minimum sized 2111 * packet was received 2112 */ 2113 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2114 &frag_idx); 2115 if (frag_idx < 0) 2116 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2117 MPASS(frag_idx >= 0); 2118 if ((cl = sd_cl[frag_idx]) == NULL) { 2119 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2120 if (__predict_false(cl == NULL)) 2121 break; 2122 2123 cb_arg.error = 0; 2124 MPASS(sd_map != NULL); 2125 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2126 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2127 BUS_DMA_NOWAIT); 2128 if (__predict_false(err != 0 || cb_arg.error)) { 2129 uma_zfree(fl->ifl_zone, cl); 2130 break; 2131 } 2132 2133 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2134 sd_cl[frag_idx] = cl; 2135 #if MEMORY_LOGGING 2136 fl->ifl_cl_enqueued++; 2137 #endif 2138 } else { 2139 bus_addr = sd_ba[frag_idx]; 2140 } 2141 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2142 BUS_DMASYNC_PREREAD); 2143 2144 if (sd_m[frag_idx] == NULL) { 2145 m = m_gethdr_raw(M_NOWAIT, 0); 2146 if (__predict_false(m == NULL)) 2147 break; 2148 sd_m[frag_idx] = m; 2149 } 2150 bit_set(fl->ifl_rx_bitmap, frag_idx); 2151 #if MEMORY_LOGGING 2152 fl->ifl_m_enqueued++; 2153 #endif 2154 2155 DBG_COUNTER_INC(rx_allocs); 2156 fl->ifl_rxd_idxs[i] = frag_idx; 2157 fl->ifl_bus_addrs[i] = bus_addr; 2158 credits++; 2159 i++; 2160 MPASS(credits <= fl->ifl_size); 2161 if (++idx == fl->ifl_size) { 2162 #ifdef INVARIANTS 2163 fl->ifl_gen = 1; 2164 #endif 2165 idx = 0; 2166 } 2167 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2168 iru.iru_pidx = pidx; 2169 iru.iru_count = i; 2170 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2171 fl->ifl_pidx = idx; 2172 fl->ifl_credits = credits; 2173 pidx = idx; 2174 i = 0; 2175 } 2176 } 2177 2178 if (n < count - 1) { 2179 if (i != 0) { 2180 iru.iru_pidx = pidx; 2181 iru.iru_count = i; 2182 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2183 fl->ifl_pidx = idx; 2184 fl->ifl_credits = credits; 2185 } 2186 DBG_COUNTER_INC(rxd_flush); 2187 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2188 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2189 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2190 fl->ifl_id, fl->ifl_pidx); 2191 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2192 fl->ifl_fragidx = frag_idx + 1; 2193 if (fl->ifl_fragidx == fl->ifl_size) 2194 fl->ifl_fragidx = 0; 2195 } else { 2196 fl->ifl_fragidx = frag_idx; 2197 } 2198 } 2199 2200 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2201 } 2202 2203 static inline uint8_t 2204 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2205 { 2206 /* 2207 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2208 * This is important as it confuses most NICs. For instance, 2209 * Intel NICs have (per receive ring) RDH and RDT registers, where 2210 * RDH points to the next receive descriptor to be used by the NIC, 2211 * and RDT for the next receive descriptor to be published by the 2212 * driver to the NIC (RDT - 1 is thus the last valid one). 2213 * The condition RDH == RDT means no descriptors are available to 2214 * the NIC, and thus it would be ambiguous if it also meant that 2215 * all the descriptors are available to the NIC. 2216 */ 2217 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2218 #ifdef INVARIANTS 2219 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2220 #endif 2221 2222 MPASS(fl->ifl_credits <= fl->ifl_size); 2223 MPASS(reclaimable == delta); 2224 2225 if (reclaimable > 0) 2226 return (iflib_fl_refill(ctx, fl, reclaimable)); 2227 return (0); 2228 } 2229 2230 uint8_t 2231 iflib_in_detach(if_ctx_t ctx) 2232 { 2233 bool in_detach; 2234 2235 STATE_LOCK(ctx); 2236 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2237 STATE_UNLOCK(ctx); 2238 return (in_detach); 2239 } 2240 2241 static void 2242 iflib_fl_bufs_free(iflib_fl_t fl) 2243 { 2244 iflib_dma_info_t idi = fl->ifl_ifdi; 2245 bus_dmamap_t sd_map; 2246 uint32_t i; 2247 2248 for (i = 0; i < fl->ifl_size; i++) { 2249 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2250 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2251 2252 if (*sd_cl != NULL) { 2253 sd_map = fl->ifl_sds.ifsd_map[i]; 2254 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2255 BUS_DMASYNC_POSTREAD); 2256 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2257 uma_zfree(fl->ifl_zone, *sd_cl); 2258 *sd_cl = NULL; 2259 if (*sd_m != NULL) { 2260 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2261 m_free_raw(*sd_m); 2262 *sd_m = NULL; 2263 } 2264 } else { 2265 MPASS(*sd_m == NULL); 2266 } 2267 #if MEMORY_LOGGING 2268 fl->ifl_m_dequeued++; 2269 fl->ifl_cl_dequeued++; 2270 #endif 2271 } 2272 #ifdef INVARIANTS 2273 for (i = 0; i < fl->ifl_size; i++) { 2274 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2275 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2276 } 2277 #endif 2278 /* 2279 * Reset free list values 2280 */ 2281 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2282 bzero(idi->idi_vaddr, idi->idi_size); 2283 } 2284 2285 /********************************************************************* 2286 * 2287 * Initialize a free list and its buffers. 2288 * 2289 **********************************************************************/ 2290 static int 2291 iflib_fl_setup(iflib_fl_t fl) 2292 { 2293 iflib_rxq_t rxq = fl->ifl_rxq; 2294 if_ctx_t ctx = rxq->ifr_ctx; 2295 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2296 int qidx; 2297 2298 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2299 /* 2300 * Free current RX buffer structs and their mbufs 2301 */ 2302 iflib_fl_bufs_free(fl); 2303 /* Now replenish the mbufs */ 2304 MPASS(fl->ifl_credits == 0); 2305 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2306 if (scctx->isc_rxd_buf_size[qidx] != 0) 2307 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2308 else 2309 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2310 /* 2311 * ifl_buf_size may be a driver-supplied value, so pull it up 2312 * to the selected mbuf size. 2313 */ 2314 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2315 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2316 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2317 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2318 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2319 2320 /* 2321 * Avoid pre-allocating zillions of clusters to an idle card 2322 * potentially speeding up attach. In any case make sure 2323 * to leave a descriptor unavailable. See the comment in 2324 * iflib_fl_refill_all(). 2325 */ 2326 MPASS(fl->ifl_size > 0); 2327 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2328 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2329 return (ENOBUFS); 2330 /* 2331 * handle failure 2332 */ 2333 MPASS(rxq != NULL); 2334 MPASS(fl->ifl_ifdi != NULL); 2335 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2336 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2337 return (0); 2338 } 2339 2340 /********************************************************************* 2341 * 2342 * Free receive ring data structures 2343 * 2344 **********************************************************************/ 2345 static void 2346 iflib_rx_sds_free(iflib_rxq_t rxq) 2347 { 2348 iflib_fl_t fl; 2349 int i, j; 2350 2351 if (rxq->ifr_fl != NULL) { 2352 for (i = 0; i < rxq->ifr_nfl; i++) { 2353 fl = &rxq->ifr_fl[i]; 2354 if (fl->ifl_buf_tag != NULL) { 2355 if (fl->ifl_sds.ifsd_map != NULL) { 2356 for (j = 0; j < fl->ifl_size; j++) { 2357 bus_dmamap_sync( 2358 fl->ifl_buf_tag, 2359 fl->ifl_sds.ifsd_map[j], 2360 BUS_DMASYNC_POSTREAD); 2361 bus_dmamap_unload( 2362 fl->ifl_buf_tag, 2363 fl->ifl_sds.ifsd_map[j]); 2364 bus_dmamap_destroy( 2365 fl->ifl_buf_tag, 2366 fl->ifl_sds.ifsd_map[j]); 2367 } 2368 } 2369 bus_dma_tag_destroy(fl->ifl_buf_tag); 2370 fl->ifl_buf_tag = NULL; 2371 } 2372 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2373 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2374 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2375 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2376 free(fl->ifl_rx_bitmap, M_IFLIB); 2377 fl->ifl_sds.ifsd_m = NULL; 2378 fl->ifl_sds.ifsd_cl = NULL; 2379 fl->ifl_sds.ifsd_ba = NULL; 2380 fl->ifl_sds.ifsd_map = NULL; 2381 fl->ifl_rx_bitmap = NULL; 2382 } 2383 free(rxq->ifr_fl, M_IFLIB); 2384 rxq->ifr_fl = NULL; 2385 free(rxq->ifr_ifdi, M_IFLIB); 2386 rxq->ifr_ifdi = NULL; 2387 rxq->ifr_cq_cidx = 0; 2388 } 2389 } 2390 2391 /* 2392 * Timer routine 2393 */ 2394 static void 2395 iflib_timer(void *arg) 2396 { 2397 iflib_txq_t txq = arg; 2398 if_ctx_t ctx = txq->ift_ctx; 2399 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2400 uint64_t this_tick = ticks; 2401 2402 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2403 return; 2404 2405 /* 2406 ** Check on the state of the TX queue(s), this 2407 ** can be done without the lock because its RO 2408 ** and the HUNG state will be static if set. 2409 */ 2410 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) { 2411 txq->ift_last_timer_tick = this_tick; 2412 IFDI_TIMER(ctx, txq->ift_id); 2413 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2414 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2415 (sctx->isc_pause_frames == 0))) 2416 goto hung; 2417 2418 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2419 ifmp_ring_is_stalled(txq->ift_br)) { 2420 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, 2421 ("queue can't be marked as hung if interface is down")); 2422 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2423 } 2424 txq->ift_cleaned_prev = txq->ift_cleaned; 2425 } 2426 /* handle any laggards */ 2427 if (txq->ift_db_pending) 2428 GROUPTASK_ENQUEUE(&txq->ift_task); 2429 2430 sctx->isc_pause_frames = 0; 2431 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2432 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, 2433 txq, txq->ift_timer.c_cpu); 2434 return; 2435 2436 hung: 2437 device_printf(ctx->ifc_dev, 2438 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2439 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2440 STATE_LOCK(ctx); 2441 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2442 ctx->ifc_flags |= (IFC_DO_WATCHDOG | IFC_DO_RESET); 2443 iflib_admin_intr_deferred(ctx); 2444 STATE_UNLOCK(ctx); 2445 } 2446 2447 static uint16_t 2448 iflib_get_mbuf_size_for(unsigned int size) 2449 { 2450 2451 if (size <= MCLBYTES) 2452 return (MCLBYTES); 2453 else 2454 return (MJUMPAGESIZE); 2455 } 2456 2457 static void 2458 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2459 { 2460 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2461 2462 /* 2463 * XXX don't set the max_frame_size to larger 2464 * than the hardware can handle 2465 */ 2466 ctx->ifc_rx_mbuf_sz = 2467 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2468 } 2469 2470 uint32_t 2471 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2472 { 2473 2474 return (ctx->ifc_rx_mbuf_sz); 2475 } 2476 2477 static void 2478 iflib_init_locked(if_ctx_t ctx) 2479 { 2480 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2481 if_t ifp = ctx->ifc_ifp; 2482 iflib_fl_t fl; 2483 iflib_txq_t txq; 2484 iflib_rxq_t rxq; 2485 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2486 2487 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2488 IFDI_INTR_DISABLE(ctx); 2489 2490 /* 2491 * See iflib_stop(). Useful in case iflib_init_locked() is 2492 * called without first calling iflib_stop(). 2493 */ 2494 netmap_disable_all_rings(ifp); 2495 2496 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2497 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2498 /* Set hardware offload abilities */ 2499 if_clearhwassist(ifp); 2500 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2501 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2502 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2503 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2504 if (if_getcapenable(ifp) & IFCAP_TSO4) 2505 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2506 if (if_getcapenable(ifp) & IFCAP_TSO6) 2507 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2508 2509 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 2510 CALLOUT_LOCK(txq); 2511 callout_stop(&txq->ift_timer); 2512 #ifdef DEV_NETMAP 2513 callout_stop(&txq->ift_netmap_timer); 2514 #endif /* DEV_NETMAP */ 2515 CALLOUT_UNLOCK(txq); 2516 (void)iflib_netmap_txq_init(ctx, txq); 2517 } 2518 2519 /* 2520 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2521 * that drivers can use the value when setting up the hardware receive 2522 * buffers. 2523 */ 2524 iflib_calc_rx_mbuf_sz(ctx); 2525 2526 #ifdef INVARIANTS 2527 i = if_getdrvflags(ifp); 2528 #endif 2529 IFDI_INIT(ctx); 2530 MPASS(if_getdrvflags(ifp) == i); 2531 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 2532 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2533 /* This rxq is in netmap mode. Skip normal init. */ 2534 continue; 2535 } 2536 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2537 if (iflib_fl_setup(fl)) { 2538 device_printf(ctx->ifc_dev, 2539 "setting up free list %d failed - " 2540 "check cluster settings\n", j); 2541 goto done; 2542 } 2543 } 2544 } 2545 done: 2546 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2547 IFDI_INTR_ENABLE(ctx); 2548 txq = ctx->ifc_txqs; 2549 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) 2550 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 2551 txq->ift_timer.c_cpu); 2552 2553 /* Re-enable txsync/rxsync. */ 2554 netmap_enable_all_rings(ifp); 2555 } 2556 2557 static int 2558 iflib_media_change(if_t ifp) 2559 { 2560 if_ctx_t ctx = if_getsoftc(ifp); 2561 int err; 2562 2563 CTX_LOCK(ctx); 2564 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2565 iflib_if_init_locked(ctx); 2566 CTX_UNLOCK(ctx); 2567 return (err); 2568 } 2569 2570 static void 2571 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2572 { 2573 if_ctx_t ctx = if_getsoftc(ifp); 2574 2575 CTX_LOCK(ctx); 2576 IFDI_UPDATE_ADMIN_STATUS(ctx); 2577 IFDI_MEDIA_STATUS(ctx, ifmr); 2578 CTX_UNLOCK(ctx); 2579 } 2580 2581 static void 2582 iflib_stop(if_ctx_t ctx) 2583 { 2584 iflib_txq_t txq = ctx->ifc_txqs; 2585 iflib_rxq_t rxq = ctx->ifc_rxqs; 2586 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2587 if_shared_ctx_t sctx = ctx->ifc_sctx; 2588 iflib_dma_info_t di; 2589 iflib_fl_t fl; 2590 int i, j; 2591 2592 /* Tell the stack that the interface is no longer active */ 2593 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2594 2595 IFDI_INTR_DISABLE(ctx); 2596 DELAY(1000); 2597 IFDI_STOP(ctx); 2598 DELAY(1000); 2599 2600 /* 2601 * Stop any pending txsync/rxsync and prevent new ones 2602 * form starting. Processes blocked in poll() will get 2603 * POLLERR. 2604 */ 2605 netmap_disable_all_rings(ctx->ifc_ifp); 2606 2607 iflib_debug_reset(); 2608 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2609 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2610 /* make sure all transmitters have completed before proceeding XXX */ 2611 2612 CALLOUT_LOCK(txq); 2613 callout_stop(&txq->ift_timer); 2614 #ifdef DEV_NETMAP 2615 callout_stop(&txq->ift_netmap_timer); 2616 #endif /* DEV_NETMAP */ 2617 CALLOUT_UNLOCK(txq); 2618 2619 if (!ctx->ifc_sysctl_simple_tx) { 2620 /* clean any enqueued buffers */ 2621 iflib_ifmp_purge(txq); 2622 } 2623 /* Free any existing tx buffers. */ 2624 for (j = 0; j < txq->ift_size; j++) { 2625 iflib_txsd_free(ctx, txq, j); 2626 } 2627 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2628 txq->ift_in_use = txq->ift_gen = txq->ift_no_desc_avail = 0; 2629 if (sctx->isc_flags & IFLIB_PRESERVE_TX_INDICES) 2630 txq->ift_cidx = txq->ift_pidx; 2631 else 2632 txq->ift_cidx = txq->ift_pidx = 0; 2633 2634 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2635 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2636 txq->ift_pullups = 0; 2637 ifmp_ring_reset_stats(txq->ift_br); 2638 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2639 bzero((void *)di->idi_vaddr, di->idi_size); 2640 } 2641 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2642 if (rxq->ifr_task.gt_taskqueue != NULL) 2643 gtaskqueue_drain(rxq->ifr_task.gt_taskqueue, 2644 &rxq->ifr_task.gt_task); 2645 2646 rxq->ifr_cq_cidx = 0; 2647 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2648 bzero((void *)di->idi_vaddr, di->idi_size); 2649 /* also resets the free lists pidx/cidx */ 2650 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2651 iflib_fl_bufs_free(fl); 2652 } 2653 } 2654 2655 static inline caddr_t 2656 calc_next_rxd(iflib_fl_t fl, int cidx) 2657 { 2658 qidx_t size; 2659 int nrxd; 2660 caddr_t start, end, cur, next; 2661 2662 nrxd = fl->ifl_size; 2663 size = fl->ifl_rxd_size; 2664 start = fl->ifl_ifdi->idi_vaddr; 2665 2666 if (__predict_false(size == 0)) 2667 return (start); 2668 cur = start + size * cidx; 2669 end = start + size * nrxd; 2670 next = CACHE_PTR_NEXT(cur); 2671 return (next < end ? next : start); 2672 } 2673 2674 static inline void 2675 prefetch_pkts(iflib_fl_t fl, int cidx) 2676 { 2677 int nextptr; 2678 int nrxd = fl->ifl_size; 2679 caddr_t next_rxd; 2680 2681 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd - 1); 2682 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2683 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2684 next_rxd = calc_next_rxd(fl, cidx); 2685 prefetch(next_rxd); 2686 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd - 1)]); 2687 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd - 1)]); 2688 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd - 1)]); 2689 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd - 1)]); 2690 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd - 1)]); 2691 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd - 1)]); 2692 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd - 1)]); 2693 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd - 1)]); 2694 } 2695 2696 static struct mbuf * 2697 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2698 int *pf_rv, if_rxd_info_t ri) 2699 { 2700 bus_dmamap_t map; 2701 iflib_fl_t fl; 2702 caddr_t payload; 2703 struct mbuf *m; 2704 int flid, cidx, len, next; 2705 2706 map = NULL; 2707 flid = irf->irf_flid; 2708 cidx = irf->irf_idx; 2709 fl = &rxq->ifr_fl[flid]; 2710 sd->ifsd_fl = fl; 2711 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2712 fl->ifl_credits--; 2713 #if MEMORY_LOGGING 2714 fl->ifl_m_dequeued++; 2715 #endif 2716 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2717 prefetch_pkts(fl, cidx); 2718 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size - 1); 2719 prefetch(&fl->ifl_sds.ifsd_map[next]); 2720 map = fl->ifl_sds.ifsd_map[cidx]; 2721 2722 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2723 2724 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2725 irf->irf_len != 0) { 2726 payload = *sd->ifsd_cl; 2727 payload += ri->iri_pad; 2728 len = ri->iri_len - ri->iri_pad; 2729 *pf_rv = pfil_mem_in(rxq->pfil, payload, len, ri->iri_ifp, &m); 2730 switch (*pf_rv) { 2731 case PFIL_DROPPED: 2732 case PFIL_CONSUMED: 2733 /* 2734 * The filter ate it. Everything is recycled. 2735 */ 2736 m = NULL; 2737 unload = 0; 2738 break; 2739 case PFIL_REALLOCED: 2740 /* 2741 * The filter copied it. Everything is recycled. 2742 * 'm' points at new mbuf. 2743 */ 2744 unload = 0; 2745 break; 2746 case PFIL_PASS: 2747 /* 2748 * Filter said it was OK, so receive like 2749 * normal 2750 */ 2751 m = fl->ifl_sds.ifsd_m[cidx]; 2752 fl->ifl_sds.ifsd_m[cidx] = NULL; 2753 break; 2754 default: 2755 MPASS(0); 2756 } 2757 } else { 2758 m = fl->ifl_sds.ifsd_m[cidx]; 2759 fl->ifl_sds.ifsd_m[cidx] = NULL; 2760 if (pf_rv != NULL) 2761 *pf_rv = PFIL_PASS; 2762 } 2763 2764 if (unload && irf->irf_len != 0) 2765 bus_dmamap_unload(fl->ifl_buf_tag, map); 2766 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size - 1); 2767 if (__predict_false(fl->ifl_cidx == 0)) 2768 fl->ifl_gen = 0; 2769 bit_clear(fl->ifl_rx_bitmap, cidx); 2770 return (m); 2771 } 2772 2773 static struct mbuf * 2774 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2775 { 2776 struct mbuf *m, *mh, *mt; 2777 caddr_t cl; 2778 int *pf_rv_ptr, flags, i, padlen; 2779 bool consumed; 2780 2781 i = 0; 2782 mh = NULL; 2783 consumed = false; 2784 *pf_rv = PFIL_PASS; 2785 pf_rv_ptr = pf_rv; 2786 do { 2787 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2788 pf_rv_ptr, ri); 2789 2790 MPASS(*sd->ifsd_cl != NULL); 2791 2792 /* 2793 * Exclude zero-length frags & frags from 2794 * packets the filter has consumed or dropped 2795 */ 2796 if (ri->iri_frags[i].irf_len == 0 || consumed || 2797 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2798 if (mh == NULL) { 2799 consumed = true; 2800 pf_rv_ptr = NULL; 2801 } 2802 /* XXX we can save the cluster here, but not the mbuf */ 2803 if (m != NULL) { 2804 m_init(m, M_NOWAIT, MT_DATA, 0); 2805 m_free(m); 2806 } 2807 continue; 2808 } 2809 if (mh == NULL) { 2810 flags = M_PKTHDR | M_EXT; 2811 mh = mt = m; 2812 padlen = ri->iri_pad; 2813 } else { 2814 flags = M_EXT; 2815 mt->m_next = m; 2816 mt = m; 2817 /* assuming padding is only on the first fragment */ 2818 padlen = 0; 2819 } 2820 cl = *sd->ifsd_cl; 2821 *sd->ifsd_cl = NULL; 2822 2823 /* Can these two be made one ? */ 2824 m_init(m, M_NOWAIT, MT_DATA, flags); 2825 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2826 /* 2827 * These must follow m_init and m_cljset 2828 */ 2829 m->m_data += padlen; 2830 ri->iri_len -= padlen; 2831 m->m_len = ri->iri_frags[i].irf_len; 2832 } while (++i < ri->iri_nfrags); 2833 2834 return (mh); 2835 } 2836 2837 /* 2838 * Process one software descriptor 2839 */ 2840 static struct mbuf * 2841 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2842 { 2843 struct if_rxsd sd; 2844 struct mbuf *m; 2845 int pf_rv; 2846 2847 /* should I merge this back in now that the two paths are basically duplicated? */ 2848 if (ri->iri_nfrags == 1 && 2849 ri->iri_frags[0].irf_len != 0 && 2850 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2851 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2852 &pf_rv, ri); 2853 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2854 return (m); 2855 if (pf_rv == PFIL_PASS) { 2856 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2857 #ifndef __NO_STRICT_ALIGNMENT 2858 if (!IP_ALIGNED(m) && ri->iri_pad == 0) 2859 m->m_data += 2; 2860 #endif 2861 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2862 m->m_len = ri->iri_frags[0].irf_len; 2863 m->m_data += ri->iri_pad; 2864 ri->iri_len -= ri->iri_pad; 2865 } 2866 } else { 2867 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2868 if (m == NULL) 2869 return (NULL); 2870 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2871 return (m); 2872 } 2873 m->m_pkthdr.len = ri->iri_len; 2874 m->m_pkthdr.rcvif = ri->iri_ifp; 2875 m->m_flags |= ri->iri_flags; 2876 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2877 m->m_pkthdr.flowid = ri->iri_flowid; 2878 #ifdef NUMA 2879 m->m_pkthdr.numa_domain = if_getnumadomain(ri->iri_ifp); 2880 #endif 2881 M_HASHTYPE_SET(m, ri->iri_rsstype); 2882 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2883 m->m_pkthdr.csum_data = ri->iri_csum_data; 2884 return (m); 2885 } 2886 2887 static void 2888 _task_fn_rx_watchdog(void *context) 2889 { 2890 iflib_rxq_t rxq = context; 2891 2892 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2893 } 2894 2895 static uint8_t 2896 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2897 { 2898 if_t ifp; 2899 if_ctx_t ctx = rxq->ifr_ctx; 2900 if_shared_ctx_t sctx = ctx->ifc_sctx; 2901 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2902 int avail, i; 2903 qidx_t *cidxp; 2904 struct if_rxd_info ri; 2905 int err, budget_left, rx_bytes, rx_pkts; 2906 iflib_fl_t fl; 2907 #if defined(INET6) || defined(INET) 2908 int lro_enabled; 2909 #endif 2910 uint8_t retval = 0; 2911 2912 /* 2913 * XXX early demux data packets so that if_input processing only handles 2914 * acks in interrupt context 2915 */ 2916 struct mbuf *m, *mh, *mt; 2917 2918 NET_EPOCH_ASSERT(); 2919 2920 ifp = ctx->ifc_ifp; 2921 mh = mt = NULL; 2922 MPASS(budget > 0); 2923 rx_pkts = rx_bytes = 0; 2924 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2925 cidxp = &rxq->ifr_cq_cidx; 2926 else 2927 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2928 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2929 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2930 retval |= iflib_fl_refill_all(ctx, fl); 2931 DBG_COUNTER_INC(rx_unavail); 2932 return (retval); 2933 } 2934 2935 #if defined(INET6) || defined(INET) 2936 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2937 #endif 2938 2939 /* pfil needs the vnet to be set */ 2940 CURVNET_SET_QUIET(if_getvnet(ifp)); 2941 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2942 if (__predict_false(!CTX_ACTIVE(ctx))) { 2943 DBG_COUNTER_INC(rx_ctx_inactive); 2944 break; 2945 } 2946 /* 2947 * Reset client set fields to their default values 2948 */ 2949 memset(&ri, 0, sizeof(ri)); 2950 ri.iri_qsidx = rxq->ifr_id; 2951 ri.iri_cidx = *cidxp; 2952 ri.iri_ifp = ifp; 2953 ri.iri_frags = rxq->ifr_frags; 2954 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2955 2956 if (err) { 2957 CURVNET_RESTORE(); 2958 goto err; 2959 } 2960 rx_pkts += 1; 2961 rx_bytes += ri.iri_len; 2962 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2963 *cidxp = ri.iri_cidx; 2964 /* Update our consumer index */ 2965 /* XXX NB: shurd - check if this is still safe */ 2966 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2967 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2968 /* was this only a completion queue message? */ 2969 if (__predict_false(ri.iri_nfrags == 0)) 2970 continue; 2971 } 2972 MPASS(ri.iri_nfrags != 0); 2973 MPASS(ri.iri_len != 0); 2974 2975 /* will advance the cidx on the corresponding free lists */ 2976 m = iflib_rxd_pkt_get(rxq, &ri); 2977 avail--; 2978 budget_left--; 2979 if (avail == 0 && budget_left) 2980 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2981 2982 if (__predict_false(m == NULL)) 2983 continue; 2984 2985 #ifndef __NO_STRICT_ALIGNMENT 2986 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2987 continue; 2988 #endif 2989 #if defined(INET6) || defined(INET) 2990 if (lro_enabled) { 2991 tcp_lro_queue_mbuf(&rxq->ifr_lc, m); 2992 continue; 2993 } 2994 #endif 2995 2996 if (mh == NULL) 2997 mh = mt = m; 2998 else { 2999 mt->m_nextpkt = m; 3000 mt = m; 3001 } 3002 } 3003 CURVNET_RESTORE(); 3004 /* make sure that we can refill faster than drain */ 3005 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3006 retval |= iflib_fl_refill_all(ctx, fl); 3007 3008 if (mh != NULL) { 3009 if_input(ifp, mh); 3010 DBG_COUNTER_INC(rx_if_input); 3011 } 3012 3013 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 3014 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 3015 3016 /* 3017 * Flush any outstanding LRO work 3018 */ 3019 #if defined(INET6) || defined(INET) 3020 tcp_lro_flush_all(&rxq->ifr_lc); 3021 #endif 3022 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 3023 retval |= IFLIB_RXEOF_MORE; 3024 return (retval); 3025 err: 3026 STATE_LOCK(ctx); 3027 ctx->ifc_flags |= IFC_DO_RESET; 3028 iflib_admin_intr_deferred(ctx); 3029 STATE_UNLOCK(ctx); 3030 return (0); 3031 } 3032 3033 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq) - 1) 3034 static inline qidx_t 3035 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 3036 { 3037 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3038 qidx_t minthresh = txq->ift_size / 8; 3039 if (in_use > 4 * minthresh) 3040 return (notify_count); 3041 if (in_use > 2 * minthresh) 3042 return (notify_count >> 1); 3043 if (in_use > minthresh) 3044 return (notify_count >> 3); 3045 return (0); 3046 } 3047 3048 static inline qidx_t 3049 txq_max_rs_deferred(iflib_txq_t txq) 3050 { 3051 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3052 qidx_t minthresh = txq->ift_size / 8; 3053 if (txq->ift_in_use > 4 * minthresh) 3054 return (notify_count); 3055 if (txq->ift_in_use > 2 * minthresh) 3056 return (notify_count >> 1); 3057 if (txq->ift_in_use > minthresh) 3058 return (notify_count >> 2); 3059 return (2); 3060 } 3061 3062 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 3063 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 3064 3065 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 3066 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 3067 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 3068 3069 /* forward compatibility for cxgb */ 3070 #define FIRST_QSET(ctx) 0 3071 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3072 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3073 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3074 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3075 3076 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3077 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3078 3079 static inline bool 3080 iflib_txd_db_check(iflib_txq_t txq, int ring) 3081 { 3082 if_ctx_t ctx = txq->ift_ctx; 3083 qidx_t dbval, max; 3084 3085 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use); 3086 3087 /* force || threshold exceeded || at the edge of the ring */ 3088 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx))) { 3089 3090 /* 3091 * 'npending' is used if the card's doorbell is in terms of the number of descriptors 3092 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the 3093 * producer index explicitly (INTC). 3094 */ 3095 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3096 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3097 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3098 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3099 3100 /* 3101 * Absent bugs there are zero packets pending so reset pending counts to zero. 3102 */ 3103 txq->ift_db_pending = txq->ift_npending = 0; 3104 return (true); 3105 } 3106 return (false); 3107 } 3108 3109 #ifdef PKT_DEBUG 3110 static void 3111 print_pkt(if_pkt_info_t pi) 3112 { 3113 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3114 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3115 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3116 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3117 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3118 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3119 } 3120 #endif 3121 3122 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3123 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3124 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3125 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3126 3127 /** 3128 * Parses out ethernet header information in the given mbuf. 3129 * Returns in pi: ipi_etype (EtherType) and ipi_ehdrlen (Ethernet header length) 3130 * 3131 * This will account for the VLAN header if present. 3132 * 3133 * XXX: This doesn't handle QinQ, which could prevent TX offloads for those 3134 * types of packets. 3135 */ 3136 static int 3137 iflib_parse_ether_header(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3138 { 3139 struct ether_vlan_header *eh; 3140 struct mbuf *m; 3141 3142 m = *mp; 3143 if (__predict_false(m->m_len < sizeof(*eh))) { 3144 (*pullups)++; 3145 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3146 return (ENOMEM); 3147 } 3148 eh = mtod(m, struct ether_vlan_header *); 3149 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3150 pi->ipi_etype = ntohs(eh->evl_proto); 3151 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3152 } else { 3153 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3154 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3155 } 3156 *mp = m; 3157 3158 return (0); 3159 } 3160 3161 /** 3162 * Parse up to the L3 header and extract IPv4/IPv6 header information into pi. 3163 * Currently this information includes: IP ToS value, IP header version/presence 3164 * 3165 * This is missing some checks and doesn't edit the packet content as it goes, 3166 * unlike iflib_parse_header(), in order to keep the amount of code here minimal. 3167 */ 3168 static int 3169 iflib_parse_header_partial(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3170 { 3171 struct mbuf *m; 3172 int err; 3173 3174 *pullups = 0; 3175 m = *mp; 3176 if (!M_WRITABLE(m)) { 3177 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3178 return (ENOMEM); 3179 } else { 3180 m_freem(*mp); 3181 DBG_COUNTER_INC(tx_frees); 3182 *mp = m; 3183 } 3184 } 3185 3186 /* Fills out pi->ipi_etype */ 3187 err = iflib_parse_ether_header(pi, mp, pullups); 3188 if (err) 3189 return (err); 3190 m = *mp; 3191 3192 switch (pi->ipi_etype) { 3193 #ifdef INET 3194 case ETHERTYPE_IP: 3195 { 3196 struct mbuf *n; 3197 struct ip *ip = NULL; 3198 int miniplen; 3199 3200 miniplen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip)); 3201 if (__predict_false(m->m_len < miniplen)) { 3202 /* 3203 * Check for common case where the first mbuf only contains 3204 * the Ethernet header 3205 */ 3206 if (m->m_len == pi->ipi_ehdrlen) { 3207 n = m->m_next; 3208 MPASS(n); 3209 /* If next mbuf contains at least the minimal IP header, then stop */ 3210 if (n->m_len >= sizeof(*ip)) { 3211 ip = (struct ip *)n->m_data; 3212 } else { 3213 (*pullups)++; 3214 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3215 return (ENOMEM); 3216 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3217 } 3218 } else { 3219 (*pullups)++; 3220 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3221 return (ENOMEM); 3222 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3223 } 3224 } else { 3225 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3226 } 3227 3228 /* Have the IPv4 header w/ no options here */ 3229 pi->ipi_ip_hlen = ip->ip_hl << 2; 3230 pi->ipi_ipproto = ip->ip_p; 3231 pi->ipi_ip_tos = ip->ip_tos; 3232 pi->ipi_flags |= IPI_TX_IPV4; 3233 3234 break; 3235 } 3236 #endif 3237 #ifdef INET6 3238 case ETHERTYPE_IPV6: 3239 { 3240 struct ip6_hdr *ip6; 3241 3242 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3243 (*pullups)++; 3244 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3245 return (ENOMEM); 3246 } 3247 ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3248 3249 /* Have the IPv6 fixed header here */ 3250 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3251 pi->ipi_ipproto = ip6->ip6_nxt; 3252 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3253 pi->ipi_flags |= IPI_TX_IPV6; 3254 3255 break; 3256 } 3257 #endif 3258 default: 3259 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3260 pi->ipi_ip_hlen = 0; 3261 break; 3262 } 3263 *mp = m; 3264 3265 return (0); 3266 3267 } 3268 3269 static int 3270 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3271 { 3272 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3273 struct mbuf *m; 3274 int err; 3275 3276 m = *mp; 3277 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3278 M_WRITABLE(m) == 0) { 3279 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3280 return (ENOMEM); 3281 } else { 3282 m_freem(*mp); 3283 DBG_COUNTER_INC(tx_frees); 3284 *mp = m; 3285 } 3286 } 3287 3288 /* Fills out pi->ipi_etype */ 3289 err = iflib_parse_ether_header(pi, mp, &txq->ift_pullups); 3290 if (__predict_false(err)) 3291 return (err); 3292 m = *mp; 3293 3294 switch (pi->ipi_etype) { 3295 #ifdef INET 3296 case ETHERTYPE_IP: 3297 { 3298 struct ip *ip; 3299 struct tcphdr *th; 3300 uint8_t hlen; 3301 3302 hlen = pi->ipi_ehdrlen + sizeof(*ip); 3303 if (__predict_false(m->m_len < hlen)) { 3304 txq->ift_pullups++; 3305 if (__predict_false((m = m_pullup(m, hlen)) == NULL)) 3306 return (ENOMEM); 3307 } 3308 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3309 hlen = pi->ipi_ehdrlen + (ip->ip_hl << 2); 3310 if (ip->ip_p == IPPROTO_TCP) { 3311 hlen += sizeof(*th); 3312 th = (struct tcphdr *)((char *)ip + (ip->ip_hl << 2)); 3313 } else if (ip->ip_p == IPPROTO_UDP) { 3314 hlen += sizeof(struct udphdr); 3315 } 3316 if (__predict_false(m->m_len < hlen)) { 3317 txq->ift_pullups++; 3318 if ((m = m_pullup(m, hlen)) == NULL) 3319 return (ENOMEM); 3320 } 3321 pi->ipi_ip_hlen = ip->ip_hl << 2; 3322 pi->ipi_ipproto = ip->ip_p; 3323 pi->ipi_ip_tos = ip->ip_tos; 3324 pi->ipi_flags |= IPI_TX_IPV4; 3325 3326 /* TCP checksum offload may require TCP header length */ 3327 if (IS_TX_OFFLOAD4(pi)) { 3328 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3329 pi->ipi_tcp_hflags = tcp_get_flags(th); 3330 pi->ipi_tcp_hlen = th->th_off << 2; 3331 pi->ipi_tcp_seq = th->th_seq; 3332 } 3333 if (IS_TSO4(pi)) { 3334 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3335 return (ENXIO); 3336 /* 3337 * TSO always requires hardware checksum offload. 3338 */ 3339 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3340 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3341 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3342 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3343 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3344 ip->ip_sum = 0; 3345 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3346 } 3347 } 3348 } 3349 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3350 ip->ip_sum = 0; 3351 3352 break; 3353 } 3354 #endif 3355 #ifdef INET6 3356 case ETHERTYPE_IPV6: 3357 { 3358 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3359 struct tcphdr *th; 3360 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3361 3362 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3363 txq->ift_pullups++; 3364 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3365 return (ENOMEM); 3366 } 3367 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3368 3369 /* XXX-BZ this will go badly in case of ext hdrs. */ 3370 pi->ipi_ipproto = ip6->ip6_nxt; 3371 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3372 pi->ipi_flags |= IPI_TX_IPV6; 3373 3374 /* TCP checksum offload may require TCP header length */ 3375 if (IS_TX_OFFLOAD6(pi)) { 3376 if (pi->ipi_ipproto == IPPROTO_TCP) { 3377 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3378 txq->ift_pullups++; 3379 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3380 return (ENOMEM); 3381 } 3382 pi->ipi_tcp_hflags = tcp_get_flags(th); 3383 pi->ipi_tcp_hlen = th->th_off << 2; 3384 pi->ipi_tcp_seq = th->th_seq; 3385 } 3386 if (IS_TSO6(pi)) { 3387 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3388 return (ENXIO); 3389 /* 3390 * TSO always requires hardware checksum offload. 3391 */ 3392 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3393 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3394 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3395 } 3396 } 3397 break; 3398 } 3399 #endif 3400 default: 3401 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3402 pi->ipi_ip_hlen = 0; 3403 break; 3404 } 3405 *mp = m; 3406 3407 return (0); 3408 } 3409 3410 /* 3411 * If dodgy hardware rejects the scatter gather chain we've handed it 3412 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3413 * m_defrag'd mbufs 3414 */ 3415 static __noinline struct mbuf * 3416 iflib_remove_mbuf(iflib_txq_t txq) 3417 { 3418 int ntxd, pidx; 3419 struct mbuf *m, **ifsd_m; 3420 3421 ifsd_m = txq->ift_sds.ifsd_m; 3422 ntxd = txq->ift_size; 3423 pidx = txq->ift_pidx & (ntxd - 1); 3424 ifsd_m = txq->ift_sds.ifsd_m; 3425 m = IFLIB_GET_MBUF(ifsd_m[pidx]); 3426 ifsd_m[pidx] = NULL; 3427 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3428 if (txq->ift_sds.ifsd_tso_map != NULL) 3429 bus_dmamap_unload(txq->ift_tso_buf_tag, 3430 txq->ift_sds.ifsd_tso_map[pidx]); 3431 #if MEMORY_LOGGING 3432 txq->ift_dequeued++; 3433 #endif 3434 return (m); 3435 } 3436 3437 /* 3438 * Pad an mbuf to ensure a minimum ethernet frame size. 3439 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3440 */ 3441 static __noinline int 3442 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3443 { 3444 /* 3445 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3446 * and ARP message is the smallest common payload I can think of 3447 */ 3448 static char pad[18]; /* just zeros */ 3449 int n; 3450 struct mbuf *new_head; 3451 3452 if (!M_WRITABLE(*m_head)) { 3453 new_head = m_dup(*m_head, M_NOWAIT); 3454 if (new_head == NULL) { 3455 m_freem(*m_head); 3456 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3457 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3458 DBG_COUNTER_INC(tx_frees); 3459 return (ENOMEM); 3460 } 3461 m_freem(*m_head); 3462 *m_head = new_head; 3463 } 3464 3465 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3466 n > 0; n -= sizeof(pad)) 3467 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3468 break; 3469 3470 if (n > 0) { 3471 m_freem(*m_head); 3472 device_printf(dev, "cannot pad short frame\n"); 3473 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3474 DBG_COUNTER_INC(tx_frees); 3475 return (ENOBUFS); 3476 } 3477 3478 return (0); 3479 } 3480 3481 static int 3482 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp, int *obytes, int *opkts) 3483 { 3484 if_ctx_t ctx; 3485 if_shared_ctx_t sctx; 3486 if_softc_ctx_t scctx; 3487 bus_dma_tag_t buf_tag; 3488 bus_dma_segment_t *segs; 3489 struct mbuf *m_head, **ifsd_m; 3490 bus_dmamap_t map; 3491 struct if_pkt_info pi; 3492 uintptr_t flags; 3493 int remap = 0; 3494 int err, nsegs, ndesc, max_segs, pidx; 3495 3496 ctx = txq->ift_ctx; 3497 sctx = ctx->ifc_sctx; 3498 scctx = &ctx->ifc_softc_ctx; 3499 segs = txq->ift_segs; 3500 m_head = *m_headp; 3501 map = NULL; 3502 3503 /* 3504 * If we're doing TSO the next descriptor to clean may be quite far ahead 3505 */ 3506 pidx = txq->ift_pidx; 3507 map = txq->ift_sds.ifsd_map[pidx]; 3508 ifsd_m = txq->ift_sds.ifsd_m; 3509 3510 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3511 buf_tag = txq->ift_tso_buf_tag; 3512 max_segs = scctx->isc_tx_tso_segments_max; 3513 map = txq->ift_sds.ifsd_tso_map[pidx]; 3514 MPASS(buf_tag != NULL); 3515 MPASS(max_segs > 0); 3516 flags = IFLIB_TSO; 3517 } else { 3518 buf_tag = txq->ift_buf_tag; 3519 max_segs = scctx->isc_tx_nsegments; 3520 map = txq->ift_sds.ifsd_map[pidx]; 3521 flags = IFLIB_NO_TSO; 3522 } 3523 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3524 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3525 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3526 if (err) { 3527 DBG_COUNTER_INC(encap_txd_encap_fail); 3528 return (err); 3529 } 3530 } 3531 m_head = *m_headp; 3532 3533 memset(&pi, 0, sizeof(pi)); 3534 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG | M_BCAST | M_MCAST)); 3535 pi.ipi_pidx = pidx; 3536 pi.ipi_qsidx = txq->ift_id; 3537 pi.ipi_len = m_head->m_pkthdr.len; 3538 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3539 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3540 3541 /* deliberate bitwise OR to make one condition */ 3542 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3543 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3544 DBG_COUNTER_INC(encap_txd_encap_fail); 3545 return (err); 3546 } 3547 m_head = *m_headp; 3548 } 3549 3550 retry: 3551 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3552 BUS_DMA_NOWAIT); 3553 defrag: 3554 if (__predict_false(err)) { 3555 switch (err) { 3556 case EFBIG: 3557 /* try collapse once and defrag once */ 3558 if (remap == 0) { 3559 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3560 /* try defrag if collapsing fails */ 3561 if (m_head == NULL) 3562 remap++; 3563 } 3564 if (remap == 1) { 3565 txq->ift_mbuf_defrag++; 3566 m_head = m_defrag(*m_headp, M_NOWAIT); 3567 } 3568 /* 3569 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3570 * failed to map an mbuf that was run through m_defrag 3571 */ 3572 MPASS(remap <= 1); 3573 if (__predict_false(m_head == NULL || remap > 1)) 3574 goto defrag_failed; 3575 remap++; 3576 *m_headp = m_head; 3577 goto retry; 3578 break; 3579 case ENOMEM: 3580 txq->ift_no_tx_dma_setup++; 3581 break; 3582 default: 3583 txq->ift_no_tx_dma_setup++; 3584 m_freem(*m_headp); 3585 DBG_COUNTER_INC(tx_frees); 3586 *m_headp = NULL; 3587 break; 3588 } 3589 txq->ift_map_failed++; 3590 DBG_COUNTER_INC(encap_load_mbuf_fail); 3591 DBG_COUNTER_INC(encap_txd_encap_fail); 3592 return (err); 3593 } 3594 ifsd_m[pidx] = IFLIB_SAVE_MBUF(m_head, flags); 3595 if (m_head->m_pkthdr.csum_flags & CSUM_SND_TAG) 3596 pi.ipi_mbuf = m_head; 3597 else 3598 pi.ipi_mbuf = NULL; 3599 /* 3600 * XXX assumes a 1 to 1 relationship between segments and 3601 * descriptors - this does not hold true on all drivers, e.g. 3602 * cxgb 3603 */ 3604 if (__predict_false(nsegs > TXQ_AVAIL(txq))) { 3605 iflib_completed_tx_reclaim_force(txq); 3606 if (__predict_false(nsegs > TXQ_AVAIL(txq))) { 3607 txq->ift_no_desc_avail++; 3608 bus_dmamap_unload(buf_tag, map); 3609 DBG_COUNTER_INC(encap_txq_avail_fail); 3610 DBG_COUNTER_INC(encap_txd_encap_fail); 3611 if (ctx->ifc_sysctl_simple_tx) { 3612 *m_headp = m_head = iflib_remove_mbuf(txq); 3613 m_freem(*m_headp); 3614 DBG_COUNTER_INC(tx_frees); 3615 *m_headp = NULL; 3616 } 3617 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3618 GROUPTASK_ENQUEUE(&txq->ift_task); 3619 return (ENOBUFS); 3620 } 3621 } 3622 /* 3623 * On Intel cards we can greatly reduce the number of TX interrupts 3624 * we see by only setting report status on every Nth descriptor. 3625 * However, this also means that the driver will need to keep track 3626 * of the descriptors that RS was set on to check them for the DD bit. 3627 */ 3628 txq->ift_rs_pending += nsegs + 1; 3629 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3630 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx)) { 3631 pi.ipi_flags |= IPI_TX_INTR; 3632 txq->ift_rs_pending = 0; 3633 } 3634 3635 pi.ipi_segs = segs; 3636 pi.ipi_nsegs = nsegs; 3637 3638 MPASS(pidx >= 0 && pidx < txq->ift_size); 3639 #ifdef PKT_DEBUG 3640 print_pkt(&pi); 3641 #endif 3642 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3643 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3644 DBG_COUNTER_INC(tx_encap); 3645 MPASS(pi.ipi_new_pidx < txq->ift_size); 3646 3647 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3648 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3649 ndesc += txq->ift_size; 3650 txq->ift_gen = 1; 3651 } 3652 /* 3653 * drivers can need up to ift_pad sentinels 3654 */ 3655 MPASS(ndesc <= pi.ipi_nsegs + txq->ift_pad); 3656 MPASS(pi.ipi_new_pidx != pidx); 3657 MPASS(ndesc > 0); 3658 txq->ift_in_use += ndesc; 3659 txq->ift_db_pending += ndesc; 3660 3661 /* 3662 * We update the last software descriptor again here because there may 3663 * be a sentinel and/or there may be more mbufs than segments 3664 */ 3665 txq->ift_pidx = pi.ipi_new_pidx; 3666 txq->ift_npending += pi.ipi_ndescs; 3667 3668 /* 3669 * Update packets / bytes sent 3670 */ 3671 if (flags & IFLIB_TSO) { 3672 int hlen = pi.ipi_ehdrlen + pi.ipi_ip_hlen + pi.ipi_tcp_hlen; 3673 int tsolen = pi.ipi_len - hlen; 3674 int nsegs = (tsolen + pi.ipi_tso_segsz - 1) / pi.ipi_tso_segsz; 3675 *obytes += tsolen + nsegs * hlen; 3676 *opkts += nsegs; 3677 } else { 3678 *obytes += pi.ipi_len; 3679 *opkts += 1; 3680 } 3681 } else { 3682 *m_headp = m_head = iflib_remove_mbuf(txq); 3683 if (err == EFBIG) { 3684 txq->ift_txd_encap_efbig++; 3685 if (remap < 2) { 3686 remap = 1; 3687 goto defrag; 3688 } 3689 goto defrag_failed; 3690 } 3691 goto out_with_error; 3692 } 3693 /* 3694 * err can't possibly be non-zero here, so we don't neet to test it 3695 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3696 */ 3697 return (err); 3698 3699 defrag_failed: 3700 err = ENOMEM; 3701 txq->ift_mbuf_defrag_failed++; 3702 out_with_error: 3703 txq->ift_map_failed++; 3704 m_freem(*m_headp); 3705 DBG_COUNTER_INC(tx_frees); 3706 *m_headp = NULL; 3707 DBG_COUNTER_INC(encap_txd_encap_fail); 3708 return (err); 3709 } 3710 3711 static void 3712 iflib_tx_desc_free(iflib_txq_t txq, int n, struct mbuf **m_defer) 3713 { 3714 uint32_t qsize, cidx, gen; 3715 struct mbuf *m, **ifsd_m; 3716 uintptr_t flags; 3717 3718 cidx = txq->ift_cidx; 3719 gen = txq->ift_gen; 3720 qsize = txq->ift_size; 3721 ifsd_m =txq->ift_sds.ifsd_m; 3722 3723 while (n-- > 0) { 3724 if ((m = IFLIB_GET_MBUF(ifsd_m[cidx])) != NULL) { 3725 flags = IFLIB_GET_FLAGS(ifsd_m[cidx]); 3726 MPASS(flags != 0); 3727 if (flags & IFLIB_TSO) { 3728 bus_dmamap_sync(txq->ift_tso_buf_tag, 3729 txq->ift_sds.ifsd_tso_map[cidx], 3730 BUS_DMASYNC_POSTWRITE); 3731 bus_dmamap_unload(txq->ift_tso_buf_tag, 3732 txq->ift_sds.ifsd_tso_map[cidx]); 3733 } else { 3734 bus_dmamap_sync(txq->ift_buf_tag, 3735 txq->ift_sds.ifsd_map[cidx], 3736 BUS_DMASYNC_POSTWRITE); 3737 bus_dmamap_unload(txq->ift_buf_tag, 3738 txq->ift_sds.ifsd_map[cidx]); 3739 } 3740 /* XXX we don't support any drivers that batch packets yet */ 3741 MPASS(m->m_nextpkt == NULL); 3742 if (m_defer == NULL) { 3743 m_freem(m); 3744 } else if (m != NULL) { 3745 *m_defer = m; 3746 m_defer++; 3747 } 3748 ifsd_m[cidx] = NULL; 3749 #if MEMORY_LOGGING 3750 txq->ift_dequeued++; 3751 #endif 3752 DBG_COUNTER_INC(tx_frees); 3753 } 3754 if (__predict_false(++cidx == qsize)) { 3755 cidx = 0; 3756 gen = 0; 3757 } 3758 } 3759 txq->ift_cidx = cidx; 3760 txq->ift_gen = gen; 3761 } 3762 3763 static __inline int 3764 iflib_txq_can_reclaim(iflib_txq_t txq) 3765 { 3766 int reclaim, thresh; 3767 3768 thresh = txq->ift_reclaim_thresh; 3769 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3770 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3771 3772 if (ticks <= (txq->ift_last_reclaim + txq->ift_reclaim_ticks) && 3773 txq->ift_in_use < thresh) 3774 return (false); 3775 iflib_tx_credits_update(txq->ift_ctx, txq); 3776 reclaim = DESC_RECLAIMABLE(txq); 3777 if (reclaim <= thresh) { 3778 #ifdef INVARIANTS 3779 if (iflib_verbose_debug) { 3780 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __func__, 3781 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3782 reclaim, thresh); 3783 } 3784 #endif 3785 return (0); 3786 } 3787 return (reclaim); 3788 } 3789 3790 static __inline void 3791 _iflib_completed_tx_reclaim(iflib_txq_t txq, struct mbuf **m_defer, int reclaim) 3792 { 3793 txq->ift_last_reclaim = ticks; 3794 iflib_tx_desc_free(txq, reclaim, m_defer); 3795 txq->ift_cleaned += reclaim; 3796 txq->ift_in_use -= reclaim; 3797 } 3798 3799 static __inline int 3800 iflib_completed_tx_reclaim(iflib_txq_t txq, struct mbuf **m_defer) 3801 { 3802 int reclaim; 3803 3804 reclaim = iflib_txq_can_reclaim(txq); 3805 if (reclaim == 0) 3806 return (0); 3807 _iflib_completed_tx_reclaim(txq, m_defer, reclaim); 3808 return (reclaim); 3809 } 3810 3811 /* 3812 * Reclaim any transmit descriptors possible, ignoring coalescing 3813 */ 3814 static __inline void 3815 iflib_completed_tx_reclaim_force(iflib_txq_t txq) 3816 { 3817 int reclaim; 3818 3819 iflib_tx_credits_update(txq->ift_ctx, txq); 3820 reclaim = DESC_RECLAIMABLE(txq); 3821 if (reclaim != 0) 3822 _iflib_completed_tx_reclaim(txq, NULL, reclaim); 3823 } 3824 3825 static struct mbuf ** 3826 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3827 { 3828 int next, size; 3829 struct mbuf **items; 3830 3831 size = r->size; 3832 next = (cidx + CACHE_PTR_INCREMENT) & (size - 1); 3833 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3834 3835 prefetch(items[(cidx + offset) & (size - 1)]); 3836 if (remaining > 1) { 3837 prefetch2cachelines(&items[next]); 3838 prefetch2cachelines(items[(cidx + offset + 1) & (size - 1)]); 3839 prefetch2cachelines(items[(cidx + offset + 2) & (size - 1)]); 3840 prefetch2cachelines(items[(cidx + offset + 3) & (size - 1)]); 3841 } 3842 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size - 1)])); 3843 } 3844 3845 static void 3846 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3847 { 3848 3849 ifmp_ring_check_drainage(txq->ift_br, budget); 3850 } 3851 3852 static uint32_t 3853 iflib_txq_can_drain(struct ifmp_ring *r) 3854 { 3855 iflib_txq_t txq = r->cookie; 3856 if_ctx_t ctx = txq->ift_ctx; 3857 3858 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx)) 3859 return (1); 3860 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3861 BUS_DMASYNC_POSTREAD); 3862 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3863 false)); 3864 } 3865 3866 static uint32_t 3867 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3868 { 3869 iflib_txq_t txq = r->cookie; 3870 if_ctx_t ctx = txq->ift_ctx; 3871 if_t ifp = ctx->ifc_ifp; 3872 struct mbuf *m, **mp; 3873 int avail, bytes_sent, consumed, count, err, i; 3874 int mcast_sent, pkt_sent, reclaimed; 3875 bool do_prefetch, rang, ring; 3876 3877 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3878 !LINK_ACTIVE(ctx))) { 3879 DBG_COUNTER_INC(txq_drain_notready); 3880 return (0); 3881 } 3882 reclaimed = iflib_completed_tx_reclaim(txq, NULL); 3883 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending); 3884 avail = IDXDIFF(pidx, cidx, r->size); 3885 3886 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3887 /* 3888 * The driver is unloading so we need to free all pending packets. 3889 */ 3890 DBG_COUNTER_INC(txq_drain_flushing); 3891 for (i = 0; i < avail; i++) { 3892 if (__predict_true(r->items[(cidx + i) & (r->size - 1)] != (void *)txq)) 3893 m_freem(r->items[(cidx + i) & (r->size - 1)]); 3894 r->items[(cidx + i) & (r->size - 1)] = NULL; 3895 } 3896 return (avail); 3897 } 3898 3899 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3900 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3901 CALLOUT_LOCK(txq); 3902 callout_stop(&txq->ift_timer); 3903 CALLOUT_UNLOCK(txq); 3904 DBG_COUNTER_INC(txq_drain_oactive); 3905 return (0); 3906 } 3907 3908 /* 3909 * If we've reclaimed any packets this queue cannot be hung. 3910 */ 3911 if (reclaimed) 3912 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3913 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3914 count = MIN(avail, TX_BATCH_SIZE); 3915 #ifdef INVARIANTS 3916 if (iflib_verbose_debug) 3917 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __func__, 3918 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3919 #endif 3920 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3921 err = 0; 3922 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx); i++) { 3923 int rem = do_prefetch ? count - i : 0; 3924 3925 mp = _ring_peek_one(r, cidx, i, rem); 3926 MPASS(mp != NULL && *mp != NULL); 3927 3928 /* 3929 * Completion interrupts will use the address of the txq 3930 * as a sentinel to enqueue _something_ in order to acquire 3931 * the lock on the mp_ring (there's no direct lock call). 3932 * We obviously whave to check for these sentinel cases 3933 * and skip them. 3934 */ 3935 if (__predict_false(*mp == (struct mbuf *)txq)) { 3936 consumed++; 3937 continue; 3938 } 3939 err = iflib_encap(txq, mp, &bytes_sent, &pkt_sent); 3940 if (__predict_false(err)) { 3941 /* no room - bail out */ 3942 if (err == ENOBUFS) 3943 break; 3944 consumed++; 3945 /* we can't send this packet - skip it */ 3946 continue; 3947 } 3948 consumed++; 3949 m = *mp; 3950 DBG_COUNTER_INC(tx_sent); 3951 mcast_sent += !!(m->m_flags & M_MCAST); 3952 3953 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))) 3954 break; 3955 ETHER_BPF_MTAP(ifp, m); 3956 rang = iflib_txd_db_check(txq, false); 3957 } 3958 3959 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3960 ring = rang ? false : (iflib_min_tx_latency | err | (!!txq->ift_reclaim_thresh)); 3961 iflib_txd_db_check(txq, ring); 3962 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3963 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3964 if (mcast_sent) 3965 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3966 #ifdef INVARIANTS 3967 if (iflib_verbose_debug) 3968 printf("consumed=%d\n", consumed); 3969 #endif 3970 return (consumed); 3971 } 3972 3973 static uint32_t 3974 iflib_txq_drain_always(struct ifmp_ring *r) 3975 { 3976 return (1); 3977 } 3978 3979 static uint32_t 3980 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3981 { 3982 int i, avail; 3983 struct mbuf **mp; 3984 iflib_txq_t txq; 3985 3986 txq = r->cookie; 3987 3988 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3989 CALLOUT_LOCK(txq); 3990 callout_stop(&txq->ift_timer); 3991 CALLOUT_UNLOCK(txq); 3992 3993 avail = IDXDIFF(pidx, cidx, r->size); 3994 for (i = 0; i < avail; i++) { 3995 mp = _ring_peek_one(r, cidx, i, avail - i); 3996 if (__predict_false(*mp == (struct mbuf *)txq)) 3997 continue; 3998 m_freem(*mp); 3999 DBG_COUNTER_INC(tx_frees); 4000 } 4001 MPASS(ifmp_ring_is_stalled(r) == 0); 4002 return (avail); 4003 } 4004 4005 static void 4006 iflib_ifmp_purge(iflib_txq_t txq) 4007 { 4008 struct ifmp_ring *r; 4009 4010 r = txq->ift_br; 4011 r->drain = iflib_txq_drain_free; 4012 r->can_drain = iflib_txq_drain_always; 4013 4014 ifmp_ring_check_drainage(r, r->size); 4015 4016 r->drain = iflib_txq_drain; 4017 r->can_drain = iflib_txq_can_drain; 4018 } 4019 4020 static void 4021 _task_fn_tx(void *context) 4022 { 4023 iflib_txq_t txq = context; 4024 if_ctx_t ctx = txq->ift_ctx; 4025 if_t ifp = ctx->ifc_ifp; 4026 int abdicate = ctx->ifc_sysctl_tx_abdicate; 4027 4028 #ifdef IFLIB_DIAGNOSTICS 4029 txq->ift_cpu_exec_count[curcpu]++; 4030 #endif 4031 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4032 return; 4033 #ifdef DEV_NETMAP 4034 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 4035 netmap_tx_irq(ifp, txq->ift_id)) 4036 goto skip_ifmp; 4037 #endif 4038 if (ctx->ifc_sysctl_simple_tx) { 4039 mtx_lock(&txq->ift_mtx); 4040 (void)iflib_completed_tx_reclaim(txq, NULL); 4041 mtx_unlock(&txq->ift_mtx); 4042 goto skip_ifmp; 4043 } 4044 #ifdef ALTQ 4045 if (if_altq_is_enabled(ifp)) 4046 iflib_altq_if_start(ifp); 4047 #endif 4048 if (txq->ift_db_pending) 4049 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 4050 else if (!abdicate) 4051 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4052 /* 4053 * When abdicating, we always need to check drainage, not just when we don't enqueue 4054 */ 4055 if (abdicate) 4056 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4057 4058 skip_ifmp: 4059 if (ctx->ifc_flags & IFC_LEGACY) 4060 IFDI_INTR_ENABLE(ctx); 4061 else 4062 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 4063 } 4064 4065 static void 4066 _task_fn_rx(void *context) 4067 { 4068 iflib_rxq_t rxq = context; 4069 if_ctx_t ctx = rxq->ifr_ctx; 4070 uint8_t more; 4071 uint16_t budget; 4072 #ifdef DEV_NETMAP 4073 u_int work = 0; 4074 int nmirq; 4075 #endif 4076 4077 #ifdef IFLIB_DIAGNOSTICS 4078 rxq->ifr_cpu_exec_count[curcpu]++; 4079 #endif 4080 DBG_COUNTER_INC(task_fn_rxs); 4081 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4082 return; 4083 #ifdef DEV_NETMAP 4084 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 4085 if (nmirq != NM_IRQ_PASS) { 4086 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 4087 goto skip_rxeof; 4088 } 4089 #endif 4090 budget = ctx->ifc_sysctl_rx_budget; 4091 if (budget == 0) 4092 budget = 16; /* XXX */ 4093 more = iflib_rxeof(rxq, budget); 4094 #ifdef DEV_NETMAP 4095 skip_rxeof: 4096 #endif 4097 if ((more & IFLIB_RXEOF_MORE) == 0) { 4098 if (ctx->ifc_flags & IFC_LEGACY) 4099 IFDI_INTR_ENABLE(ctx); 4100 else 4101 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 4102 DBG_COUNTER_INC(rx_intr_enables); 4103 } 4104 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4105 return; 4106 4107 if (more & IFLIB_RXEOF_MORE) 4108 GROUPTASK_ENQUEUE(&rxq->ifr_task); 4109 else if (more & IFLIB_RXEOF_EMPTY) 4110 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 4111 } 4112 4113 static void 4114 _task_fn_admin(void *context, int pending) 4115 { 4116 if_ctx_t ctx = context; 4117 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 4118 iflib_txq_t txq; 4119 int i; 4120 bool oactive, running, do_reset, do_watchdog, in_detach; 4121 4122 STATE_LOCK(ctx); 4123 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 4124 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 4125 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 4126 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 4127 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 4128 ctx->ifc_flags &= ~(IFC_DO_RESET | IFC_DO_WATCHDOG); 4129 STATE_UNLOCK(ctx); 4130 4131 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4132 return; 4133 if (in_detach) 4134 return; 4135 4136 CTX_LOCK(ctx); 4137 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4138 CALLOUT_LOCK(txq); 4139 callout_stop(&txq->ift_timer); 4140 CALLOUT_UNLOCK(txq); 4141 } 4142 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ) 4143 IFDI_ADMIN_COMPLETION_HANDLE(ctx); 4144 if (do_watchdog) { 4145 ctx->ifc_watchdog_events++; 4146 IFDI_WATCHDOG_RESET(ctx); 4147 } 4148 IFDI_UPDATE_ADMIN_STATUS(ctx); 4149 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4150 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 4151 txq->ift_timer.c_cpu); 4152 } 4153 IFDI_LINK_INTR_ENABLE(ctx); 4154 if (do_reset) 4155 iflib_if_init_locked(ctx); 4156 CTX_UNLOCK(ctx); 4157 4158 if (LINK_ACTIVE(ctx) == 0) 4159 return; 4160 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 4161 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4162 } 4163 4164 static void 4165 _task_fn_iov(void *context, int pending) 4166 { 4167 if_ctx_t ctx = context; 4168 4169 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 4170 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4171 return; 4172 4173 CTX_LOCK(ctx); 4174 IFDI_VFLR_HANDLE(ctx); 4175 CTX_UNLOCK(ctx); 4176 } 4177 4178 static int 4179 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4180 { 4181 int err; 4182 if_int_delay_info_t info; 4183 if_ctx_t ctx; 4184 4185 info = (if_int_delay_info_t)arg1; 4186 ctx = info->iidi_ctx; 4187 info->iidi_req = req; 4188 info->iidi_oidp = oidp; 4189 CTX_LOCK(ctx); 4190 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 4191 CTX_UNLOCK(ctx); 4192 return (err); 4193 } 4194 4195 /********************************************************************* 4196 * 4197 * IFNET FUNCTIONS 4198 * 4199 **********************************************************************/ 4200 4201 static void 4202 iflib_if_init_locked(if_ctx_t ctx) 4203 { 4204 iflib_stop(ctx); 4205 iflib_init_locked(ctx); 4206 } 4207 4208 static void 4209 iflib_if_init(void *arg) 4210 { 4211 if_ctx_t ctx = arg; 4212 4213 CTX_LOCK(ctx); 4214 iflib_if_init_locked(ctx); 4215 CTX_UNLOCK(ctx); 4216 } 4217 4218 static int 4219 iflib_if_transmit(if_t ifp, struct mbuf *m) 4220 { 4221 if_ctx_t ctx = if_getsoftc(ifp); 4222 iflib_txq_t txq; 4223 int err, qidx; 4224 int abdicate; 4225 4226 if (__predict_false((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 4227 DBG_COUNTER_INC(tx_frees); 4228 m_freem(m); 4229 return (ENETDOWN); 4230 } 4231 4232 MPASS(m->m_nextpkt == NULL); 4233 /* ALTQ-enabled interfaces always use queue 0. */ 4234 qidx = 0; 4235 /* Use driver-supplied queue selection method if it exists */ 4236 if (ctx->isc_txq_select_v2) { 4237 struct if_pkt_info pi; 4238 uint64_t early_pullups = 0; 4239 memset(&pi, 0, sizeof(pi)); 4240 4241 err = iflib_parse_header_partial(&pi, &m, &early_pullups); 4242 if (__predict_false(err != 0)) { 4243 /* Assign pullups for bad pkts to default queue */ 4244 ctx->ifc_txqs[0].ift_pullups += early_pullups; 4245 DBG_COUNTER_INC(encap_txd_encap_fail); 4246 return (err); 4247 } 4248 /* Let driver make queueing decision */ 4249 qidx = ctx->isc_txq_select_v2(ctx->ifc_softc, m, &pi); 4250 ctx->ifc_txqs[qidx].ift_pullups += early_pullups; 4251 } 4252 /* Backwards compatibility w/ simpler queue select */ 4253 else if (ctx->isc_txq_select) 4254 qidx = ctx->isc_txq_select(ctx->ifc_softc, m); 4255 /* If not, use iflib's standard method */ 4256 else if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !if_altq_is_enabled(ifp)) 4257 qidx = QIDX(ctx, m); 4258 4259 /* Set TX queue */ 4260 txq = &ctx->ifc_txqs[qidx]; 4261 4262 #ifdef DRIVER_BACKPRESSURE 4263 if (txq->ift_closed) { 4264 while (m != NULL) { 4265 next = m->m_nextpkt; 4266 m->m_nextpkt = NULL; 4267 m_freem(m); 4268 DBG_COUNTER_INC(tx_frees); 4269 m = next; 4270 } 4271 return (ENOBUFS); 4272 } 4273 #endif 4274 #ifdef notyet 4275 qidx = count = 0; 4276 mp = marr; 4277 next = m; 4278 do { 4279 count++; 4280 next = next->m_nextpkt; 4281 } while (next != NULL); 4282 4283 if (count > nitems(marr)) 4284 if ((mp = malloc(count * sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4285 /* XXX check nextpkt */ 4286 m_freem(m); 4287 /* XXX simplify for now */ 4288 DBG_COUNTER_INC(tx_frees); 4289 return (ENOBUFS); 4290 } 4291 for (next = m, i = 0; next != NULL; i++) { 4292 mp[i] = next; 4293 next = next->m_nextpkt; 4294 mp[i]->m_nextpkt = NULL; 4295 } 4296 #endif 4297 DBG_COUNTER_INC(tx_seen); 4298 abdicate = ctx->ifc_sysctl_tx_abdicate; 4299 4300 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4301 4302 if (abdicate) 4303 GROUPTASK_ENQUEUE(&txq->ift_task); 4304 if (err) { 4305 if (!abdicate) 4306 GROUPTASK_ENQUEUE(&txq->ift_task); 4307 /* support forthcoming later */ 4308 #ifdef DRIVER_BACKPRESSURE 4309 txq->ift_closed = TRUE; 4310 #endif 4311 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4312 m_freem(m); 4313 DBG_COUNTER_INC(tx_frees); 4314 if (err == ENOBUFS) 4315 if_inc_counter(ifp, IFCOUNTER_OQDROPS, 1); 4316 else 4317 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 4318 } 4319 4320 return (err); 4321 } 4322 4323 #ifdef ALTQ 4324 /* 4325 * The overall approach to integrating iflib with ALTQ is to continue to use 4326 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4327 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4328 * is redundant/unnecessary, but doing so minimizes the amount of 4329 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4330 * redundantly queueing to an intermediate mp_ring is swamped by the 4331 * performance limitations inherent in using ALTQ. 4332 * 4333 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4334 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4335 * given interface. If ALTQ is enabled for an interface, then all 4336 * transmitted packets for that interface will be submitted to the ALTQ 4337 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4338 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4339 * update stats that the iflib machinery handles, and which is sensitve to 4340 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4341 * will be installed as the start routine for use by ALTQ facilities that 4342 * need to trigger queue drains on a scheduled basis. 4343 * 4344 */ 4345 static void 4346 iflib_altq_if_start(if_t ifp) 4347 { 4348 struct ifaltq *ifq = &ifp->if_snd; /* XXX - DRVAPI */ 4349 struct mbuf *m; 4350 4351 IFQ_LOCK(ifq); 4352 IFQ_DEQUEUE_NOLOCK(ifq, m); 4353 while (m != NULL) { 4354 iflib_if_transmit(ifp, m); 4355 IFQ_DEQUEUE_NOLOCK(ifq, m); 4356 } 4357 IFQ_UNLOCK(ifq); 4358 } 4359 4360 static int 4361 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4362 { 4363 int err; 4364 4365 if (if_altq_is_enabled(ifp)) { 4366 IFQ_ENQUEUE(&ifp->if_snd, m, err); /* XXX - DRVAPI */ 4367 if (err == 0) 4368 iflib_altq_if_start(ifp); 4369 } else 4370 err = iflib_if_transmit(ifp, m); 4371 4372 return (err); 4373 } 4374 #endif /* ALTQ */ 4375 4376 static void 4377 iflib_if_qflush(if_t ifp) 4378 { 4379 if_ctx_t ctx = if_getsoftc(ifp); 4380 iflib_txq_t txq = ctx->ifc_txqs; 4381 int i; 4382 4383 STATE_LOCK(ctx); 4384 ctx->ifc_flags |= IFC_QFLUSH; 4385 STATE_UNLOCK(ctx); 4386 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4387 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4388 iflib_txq_check_drain(txq, 0); 4389 STATE_LOCK(ctx); 4390 ctx->ifc_flags &= ~IFC_QFLUSH; 4391 STATE_UNLOCK(ctx); 4392 4393 /* 4394 * When ALTQ is enabled, this will also take care of purging the 4395 * ALTQ queue(s). 4396 */ 4397 if_qflush(ifp); 4398 } 4399 4400 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4401 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4402 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4403 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG) 4404 4405 static int 4406 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4407 { 4408 if_ctx_t ctx = if_getsoftc(ifp); 4409 struct ifreq *ifr = (struct ifreq *)data; 4410 #if defined(INET) || defined(INET6) 4411 struct ifaddr *ifa = (struct ifaddr *)data; 4412 #endif 4413 bool avoid_reset = false; 4414 int err = 0, reinit = 0, bits; 4415 4416 switch (command) { 4417 case SIOCSIFADDR: 4418 #ifdef INET 4419 if (ifa->ifa_addr->sa_family == AF_INET) 4420 avoid_reset = true; 4421 #endif 4422 #ifdef INET6 4423 if (ifa->ifa_addr->sa_family == AF_INET6) 4424 avoid_reset = true; 4425 #endif 4426 /* 4427 * Calling init results in link renegotiation, 4428 * so we avoid doing it when possible. 4429 */ 4430 if (avoid_reset) { 4431 if_setflagbits(ifp, IFF_UP, 0); 4432 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4433 reinit = 1; 4434 #ifdef INET 4435 if (!(if_getflags(ifp) & IFF_NOARP)) 4436 arp_ifinit(ifp, ifa); 4437 #endif 4438 } else 4439 err = ether_ioctl(ifp, command, data); 4440 break; 4441 case SIOCSIFMTU: 4442 CTX_LOCK(ctx); 4443 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4444 CTX_UNLOCK(ctx); 4445 break; 4446 } 4447 bits = if_getdrvflags(ifp); 4448 /* stop the driver and free any clusters before proceeding */ 4449 iflib_stop(ctx); 4450 4451 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4452 STATE_LOCK(ctx); 4453 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4454 ctx->ifc_flags |= IFC_MULTISEG; 4455 else 4456 ctx->ifc_flags &= ~IFC_MULTISEG; 4457 STATE_UNLOCK(ctx); 4458 err = if_setmtu(ifp, ifr->ifr_mtu); 4459 } 4460 iflib_init_locked(ctx); 4461 STATE_LOCK(ctx); 4462 if_setdrvflags(ifp, bits); 4463 STATE_UNLOCK(ctx); 4464 CTX_UNLOCK(ctx); 4465 break; 4466 case SIOCSIFFLAGS: 4467 CTX_LOCK(ctx); 4468 if (if_getflags(ifp) & IFF_UP) { 4469 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4470 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4471 (IFF_PROMISC | IFF_ALLMULTI)) { 4472 CTX_UNLOCK(ctx); 4473 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4474 CTX_LOCK(ctx); 4475 } 4476 } else 4477 reinit = 1; 4478 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4479 iflib_stop(ctx); 4480 } 4481 ctx->ifc_if_flags = if_getflags(ifp); 4482 CTX_UNLOCK(ctx); 4483 break; 4484 case SIOCADDMULTI: 4485 case SIOCDELMULTI: 4486 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4487 CTX_LOCK(ctx); 4488 IFDI_INTR_DISABLE(ctx); 4489 IFDI_MULTI_SET(ctx); 4490 IFDI_INTR_ENABLE(ctx); 4491 CTX_UNLOCK(ctx); 4492 } 4493 break; 4494 case SIOCSIFMEDIA: 4495 CTX_LOCK(ctx); 4496 IFDI_MEDIA_SET(ctx); 4497 CTX_UNLOCK(ctx); 4498 /* FALLTHROUGH */ 4499 case SIOCGIFMEDIA: 4500 case SIOCGIFXMEDIA: 4501 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4502 break; 4503 case SIOCGI2C: 4504 /* FALLTHROUGH */ 4505 case SIOCGI2CPB: 4506 { 4507 struct ifi2creq i2c; 4508 if_shared_ctx_t sctx = ctx->ifc_sctx; 4509 4510 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4511 if (err != 0) 4512 break; 4513 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4514 err = EINVAL; 4515 break; 4516 } 4517 if (i2c.len > sizeof(i2c.data)) { 4518 err = EINVAL; 4519 break; 4520 } 4521 if (command == SIOCGI2C) { 4522 i2c.page = i2c.bank = 0; 4523 } else if ((sctx->isc_flags & IFLIB_I2C_PAGE_BANK) == 0) { 4524 err = EINVAL; 4525 break; 4526 } 4527 4528 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4529 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4530 sizeof(i2c)); 4531 break; 4532 } 4533 case SIOCSIFCAP: 4534 { 4535 int mask, setmask, oldmask; 4536 4537 oldmask = if_getcapenable(ifp); 4538 mask = ifr->ifr_reqcap ^ oldmask; 4539 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG; 4540 setmask = 0; 4541 #ifdef TCP_OFFLOAD 4542 setmask |= mask & (IFCAP_TOE4 | IFCAP_TOE6); 4543 #endif 4544 setmask |= (mask & IFCAP_FLAGS); 4545 setmask |= (mask & IFCAP_WOL); 4546 4547 /* 4548 * If any RX csum has changed, change all the ones that 4549 * are supported by the driver. 4550 */ 4551 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4552 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4553 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4554 } 4555 4556 /* 4557 * want to ensure that traffic has stopped before we change any of the flags 4558 */ 4559 if (setmask) { 4560 CTX_LOCK(ctx); 4561 bits = if_getdrvflags(ifp); 4562 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4563 iflib_stop(ctx); 4564 STATE_LOCK(ctx); 4565 if_togglecapenable(ifp, setmask); 4566 ctx->ifc_softc_ctx.isc_capenable ^= setmask; 4567 STATE_UNLOCK(ctx); 4568 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4569 iflib_init_locked(ctx); 4570 STATE_LOCK(ctx); 4571 if_setdrvflags(ifp, bits); 4572 STATE_UNLOCK(ctx); 4573 CTX_UNLOCK(ctx); 4574 } 4575 if_vlancap(ifp); 4576 break; 4577 } 4578 case SIOCGPRIVATE_0: 4579 case SIOCSDRVSPEC: 4580 case SIOCGDRVSPEC: 4581 CTX_LOCK(ctx); 4582 err = IFDI_PRIV_IOCTL(ctx, command, data); 4583 CTX_UNLOCK(ctx); 4584 break; 4585 case SIOCGIFDOWNREASON: 4586 CTX_LOCK(ctx); 4587 err = IFDI_GET_DOWNREASON(ctx, (struct ifdownreason *)data); 4588 CTX_UNLOCK(ctx); 4589 break; 4590 default: 4591 err = ether_ioctl(ifp, command, data); 4592 break; 4593 } 4594 if (reinit) 4595 iflib_if_init(ctx); 4596 return (err); 4597 } 4598 4599 static uint64_t 4600 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4601 { 4602 if_ctx_t ctx = if_getsoftc(ifp); 4603 4604 return (IFDI_GET_COUNTER(ctx, cnt)); 4605 } 4606 4607 /********************************************************************* 4608 * 4609 * OTHER FUNCTIONS EXPORTED TO THE STACK 4610 * 4611 **********************************************************************/ 4612 4613 static void 4614 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4615 { 4616 if_ctx_t ctx = if_getsoftc(ifp); 4617 4618 if ((void *)ctx != arg) 4619 return; 4620 4621 if ((vtag == 0) || (vtag > 4095)) 4622 return; 4623 4624 if (iflib_in_detach(ctx)) 4625 return; 4626 4627 CTX_LOCK(ctx); 4628 /* Driver may need all untagged packets to be flushed */ 4629 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4630 iflib_stop(ctx); 4631 IFDI_VLAN_REGISTER(ctx, vtag); 4632 /* Re-init to load the changes, if required */ 4633 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4634 iflib_init_locked(ctx); 4635 CTX_UNLOCK(ctx); 4636 } 4637 4638 static void 4639 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4640 { 4641 if_ctx_t ctx = if_getsoftc(ifp); 4642 4643 if ((void *)ctx != arg) 4644 return; 4645 4646 if ((vtag == 0) || (vtag > 4095)) 4647 return; 4648 4649 CTX_LOCK(ctx); 4650 /* Driver may need all tagged packets to be flushed */ 4651 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4652 iflib_stop(ctx); 4653 IFDI_VLAN_UNREGISTER(ctx, vtag); 4654 /* Re-init to load the changes, if required */ 4655 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4656 iflib_init_locked(ctx); 4657 CTX_UNLOCK(ctx); 4658 } 4659 4660 static void 4661 iflib_led_func(void *arg, int onoff) 4662 { 4663 if_ctx_t ctx = arg; 4664 4665 CTX_LOCK(ctx); 4666 IFDI_LED_FUNC(ctx, onoff); 4667 CTX_UNLOCK(ctx); 4668 } 4669 4670 /********************************************************************* 4671 * 4672 * BUS FUNCTION DEFINITIONS 4673 * 4674 **********************************************************************/ 4675 4676 int 4677 iflib_device_probe(device_t dev) 4678 { 4679 const pci_vendor_info_t *ent; 4680 if_shared_ctx_t sctx; 4681 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4682 uint16_t pci_vendor_id; 4683 4684 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4685 return (ENOTSUP); 4686 4687 pci_vendor_id = pci_get_vendor(dev); 4688 pci_device_id = pci_get_device(dev); 4689 pci_subvendor_id = pci_get_subvendor(dev); 4690 pci_subdevice_id = pci_get_subdevice(dev); 4691 pci_rev_id = pci_get_revid(dev); 4692 if (sctx->isc_parse_devinfo != NULL) 4693 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4694 4695 ent = sctx->isc_vendor_info; 4696 while (ent->pvi_vendor_id != 0) { 4697 if (pci_vendor_id != ent->pvi_vendor_id) { 4698 ent++; 4699 continue; 4700 } 4701 if ((pci_device_id == ent->pvi_device_id) && 4702 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4703 (ent->pvi_subvendor_id == 0)) && 4704 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4705 (ent->pvi_subdevice_id == 0)) && 4706 ((pci_rev_id == ent->pvi_rev_id) || 4707 (ent->pvi_rev_id == 0))) { 4708 device_set_desc_copy(dev, ent->pvi_name); 4709 /* this needs to be changed to zero if the bus probing code 4710 * ever stops re-probing on best match because the sctx 4711 * may have its values over written by register calls 4712 * in subsequent probes 4713 */ 4714 return (BUS_PROBE_DEFAULT); 4715 } 4716 ent++; 4717 } 4718 return (ENXIO); 4719 } 4720 4721 int 4722 iflib_device_probe_vendor(device_t dev) 4723 { 4724 int probe; 4725 4726 probe = iflib_device_probe(dev); 4727 if (probe == BUS_PROBE_DEFAULT) 4728 return (BUS_PROBE_VENDOR); 4729 else 4730 return (probe); 4731 } 4732 4733 static void 4734 iflib_reset_qvalues(if_ctx_t ctx) 4735 { 4736 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4737 if_shared_ctx_t sctx = ctx->ifc_sctx; 4738 device_t dev = ctx->ifc_dev; 4739 int i; 4740 4741 if (ctx->ifc_sysctl_ntxqs != 0) 4742 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4743 if (ctx->ifc_sysctl_nrxqs != 0) 4744 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4745 4746 for (i = 0; i < sctx->isc_ntxqs; i++) { 4747 if (ctx->ifc_sysctl_ntxds[i] != 0) 4748 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4749 else 4750 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4751 } 4752 4753 for (i = 0; i < sctx->isc_nrxqs; i++) { 4754 if (ctx->ifc_sysctl_nrxds[i] != 0) 4755 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4756 else 4757 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4758 } 4759 4760 for (i = 0; i < sctx->isc_nrxqs; i++) { 4761 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4762 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4763 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4764 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4765 } 4766 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4767 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4768 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4769 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4770 } 4771 if (!powerof2(scctx->isc_nrxd[i])) { 4772 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4773 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4774 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4775 } 4776 } 4777 4778 for (i = 0; i < sctx->isc_ntxqs; i++) { 4779 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4780 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4781 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4782 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4783 } 4784 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4785 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4786 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4787 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4788 } 4789 if (!powerof2(scctx->isc_ntxd[i])) { 4790 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4791 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4792 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4793 } 4794 } 4795 scctx->isc_tx_pad = 2; 4796 } 4797 4798 static void 4799 iflib_add_pfil(if_ctx_t ctx) 4800 { 4801 struct pfil_head *pfil; 4802 struct pfil_head_args pa; 4803 iflib_rxq_t rxq; 4804 int i; 4805 4806 pa.pa_version = PFIL_VERSION; 4807 pa.pa_flags = PFIL_IN; 4808 pa.pa_type = PFIL_TYPE_ETHERNET; 4809 pa.pa_headname = if_name(ctx->ifc_ifp); 4810 pfil = pfil_head_register(&pa); 4811 4812 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4813 rxq->pfil = pfil; 4814 } 4815 } 4816 4817 static void 4818 iflib_rem_pfil(if_ctx_t ctx) 4819 { 4820 struct pfil_head *pfil; 4821 iflib_rxq_t rxq; 4822 int i; 4823 4824 rxq = ctx->ifc_rxqs; 4825 pfil = rxq->pfil; 4826 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4827 rxq->pfil = NULL; 4828 } 4829 pfil_head_unregister(pfil); 4830 } 4831 4832 4833 /* 4834 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from 4835 * cpuid and wrapping as necessary. 4836 */ 4837 static unsigned int 4838 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n) 4839 { 4840 unsigned int first_valid; 4841 unsigned int last_valid; 4842 4843 /* cpuid should always be in the valid set */ 4844 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4845 4846 /* valid set should never be empty */ 4847 MPASS(!CPU_EMPTY(&ctx->ifc_cpus)); 4848 4849 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4850 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4851 n = n % CPU_COUNT(&ctx->ifc_cpus); 4852 while (n > 0) { 4853 do { 4854 cpuid++; 4855 if (cpuid > last_valid) 4856 cpuid = first_valid; 4857 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4858 n--; 4859 } 4860 4861 return (cpuid); 4862 } 4863 4864 /* 4865 * CPU mapping behaviors 4866 * --------------------- 4867 * 'separate txrx' refers to the separate_txrx sysctl 4868 * 'use logical' refers to the use_logical_cores sysctl 4869 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded 4870 * 4871 * separate use INTR 4872 * txrx logical CPUS result 4873 * ---------- --------- ------ ------------------------------------------------ 4874 * - - X RX and TX queues mapped to consecutive physical 4875 * cores with RX/TX pairs on same core and excess 4876 * of either following 4877 * - X X RX and TX queues mapped to consecutive cores 4878 * of any type with RX/TX pairs on same core and 4879 * excess of either following 4880 * X - X RX and TX queues mapped to consecutive physical 4881 * cores; all RX then all TX 4882 * X X X RX queues mapped to consecutive physical cores 4883 * first, then TX queues mapped to L2 neighbor of 4884 * the corresponding RX queue if one exists, 4885 * otherwise to consecutive physical cores 4886 * - n/a - RX and TX queues mapped to consecutive cores of 4887 * any type with RX/TX pairs on same core and excess 4888 * of either following 4889 * X n/a - RX and TX queues mapped to consecutive cores of 4890 * any type; all RX then all TX 4891 */ 4892 static unsigned int 4893 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid, 4894 bool is_tx) 4895 { 4896 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4897 unsigned int core_index; 4898 4899 if (ctx->ifc_sysctl_separate_txrx) { 4900 /* 4901 * When using separate CPUs for TX and RX, the assignment 4902 * will always be of a consecutive CPU out of the set of 4903 * context CPUs, except for the specific case where the 4904 * context CPUs are phsyical cores, the use of logical cores 4905 * has been enabled, the assignment is for TX, the TX qid 4906 * corresponds to an RX qid, and the CPU assigned to the 4907 * corresponding RX queue has an L2 neighbor. 4908 */ 4909 if (ctx->ifc_sysctl_use_logical_cores && 4910 ctx->ifc_cpus_are_physical_cores && 4911 is_tx && qid < scctx->isc_nrxqsets) { 4912 int l2_neighbor; 4913 unsigned int rx_cpuid; 4914 4915 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid); 4916 l2_neighbor = sched_find_l2_neighbor(rx_cpuid); 4917 if (l2_neighbor != -1) { 4918 return (l2_neighbor); 4919 } 4920 /* 4921 * ... else fall through to the normal 4922 * consecutive-after-RX assignment scheme. 4923 * 4924 * Note that we are assuming that all RX queue CPUs 4925 * have an L2 neighbor, or all do not. If a mixed 4926 * scenario is possible, we will have to keep track 4927 * separately of how many queues prior to this one 4928 * were not able to be assigned to an L2 neighbor. 4929 */ 4930 } 4931 if (is_tx) 4932 core_index = scctx->isc_nrxqsets + qid; 4933 else 4934 core_index = qid; 4935 } else { 4936 core_index = qid; 4937 } 4938 4939 return (cpuid_advance(ctx, base_cpuid, core_index)); 4940 } 4941 4942 static uint16_t 4943 get_ctx_core_offset(if_ctx_t ctx) 4944 { 4945 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4946 struct cpu_offset *op; 4947 cpuset_t assigned_cpus; 4948 unsigned int cores_consumed; 4949 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset; 4950 unsigned int first_valid; 4951 unsigned int last_valid; 4952 unsigned int i; 4953 4954 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4955 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4956 4957 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) { 4958 /* 4959 * Align the user-chosen base CPU ID to the next valid CPU 4960 * for this device. If the chosen base CPU ID is smaller 4961 * than the first valid CPU or larger than the last valid 4962 * CPU, we assume the user does not know what the valid 4963 * range is for this device and is thinking in terms of a 4964 * zero-based reference frame, and so we shift the given 4965 * value into the valid range (and wrap accordingly) so the 4966 * intent is translated to the proper frame of reference. 4967 * If the base CPU ID is within the valid first/last, but 4968 * does not correspond to a valid CPU, it is advanced to the 4969 * next valid CPU (wrapping if necessary). 4970 */ 4971 if (base_cpuid < first_valid || base_cpuid > last_valid) { 4972 /* shift from zero-based to first_valid-based */ 4973 base_cpuid += first_valid; 4974 /* wrap to range [first_valid, last_valid] */ 4975 base_cpuid = (base_cpuid - first_valid) % 4976 (last_valid - first_valid + 1); 4977 } 4978 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) { 4979 /* 4980 * base_cpuid is in [first_valid, last_valid], but 4981 * not a member of the valid set. In this case, 4982 * there will always be a member of the valid set 4983 * with a CPU ID that is greater than base_cpuid, 4984 * and we simply advance to it. 4985 */ 4986 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) 4987 base_cpuid++; 4988 } 4989 return (base_cpuid); 4990 } 4991 4992 /* 4993 * Determine how many cores will be consumed by performing the CPU 4994 * assignments and counting how many of the assigned CPUs correspond 4995 * to CPUs in the set of context CPUs. This is done using the CPU 4996 * ID first_valid as the base CPU ID, as the base CPU must be within 4997 * the set of context CPUs. 4998 * 4999 * Note not all assigned CPUs will be in the set of context CPUs 5000 * when separate CPUs are being allocated to TX and RX queues, 5001 * assignment to logical cores has been enabled, the set of context 5002 * CPUs contains only physical CPUs, and TX queues are mapped to L2 5003 * neighbors of CPUs that RX queues have been mapped to - in this 5004 * case we do only want to count how many CPUs in the set of context 5005 * CPUs have been consumed, as that determines the next CPU in that 5006 * set to start allocating at for the next device for which 5007 * core_offset is not set. 5008 */ 5009 CPU_ZERO(&assigned_cpus); 5010 for (i = 0; i < scctx->isc_ntxqsets; i++) 5011 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true), 5012 &assigned_cpus); 5013 for (i = 0; i < scctx->isc_nrxqsets; i++) 5014 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false), 5015 &assigned_cpus); 5016 CPU_AND(&assigned_cpus, &assigned_cpus, &ctx->ifc_cpus); 5017 cores_consumed = CPU_COUNT(&assigned_cpus); 5018 5019 mtx_lock(&cpu_offset_mtx); 5020 SLIST_FOREACH(op, &cpu_offsets, entries) { 5021 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5022 base_cpuid = op->next_cpuid; 5023 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid, 5024 cores_consumed); 5025 MPASS(op->refcount < UINT_MAX); 5026 op->refcount++; 5027 break; 5028 } 5029 } 5030 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) { 5031 base_cpuid = first_valid; 5032 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 5033 M_NOWAIT | M_ZERO); 5034 if (op == NULL) { 5035 device_printf(ctx->ifc_dev, 5036 "allocation for cpu offset failed.\n"); 5037 } else { 5038 op->next_cpuid = cpuid_advance(ctx, base_cpuid, 5039 cores_consumed); 5040 op->refcount = 1; 5041 CPU_COPY(&ctx->ifc_cpus, &op->set); 5042 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 5043 } 5044 } 5045 mtx_unlock(&cpu_offset_mtx); 5046 5047 return (base_cpuid); 5048 } 5049 5050 static void 5051 unref_ctx_core_offset(if_ctx_t ctx) 5052 { 5053 struct cpu_offset *op, *top; 5054 5055 mtx_lock(&cpu_offset_mtx); 5056 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 5057 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5058 MPASS(op->refcount > 0); 5059 op->refcount--; 5060 if (op->refcount == 0) { 5061 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 5062 free(op, M_IFLIB); 5063 } 5064 break; 5065 } 5066 } 5067 mtx_unlock(&cpu_offset_mtx); 5068 } 5069 5070 int 5071 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 5072 { 5073 if_ctx_t ctx; 5074 if_t ifp; 5075 if_softc_ctx_t scctx; 5076 kobjop_desc_t kobj_desc; 5077 kobj_method_t *kobj_method; 5078 int err, msix, rid; 5079 int num_txd, num_rxd; 5080 char namebuf[TASKQUEUE_NAMELEN]; 5081 5082 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK | M_ZERO); 5083 5084 if (sc == NULL) { 5085 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK | M_ZERO); 5086 device_set_softc(dev, ctx); 5087 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5088 } 5089 5090 ctx->ifc_sctx = sctx; 5091 ctx->ifc_dev = dev; 5092 ctx->ifc_softc = sc; 5093 5094 iflib_register(ctx); 5095 iflib_add_device_sysctl_pre(ctx); 5096 5097 scctx = &ctx->ifc_softc_ctx; 5098 ifp = ctx->ifc_ifp; 5099 if (ctx->ifc_sysctl_simple_tx) { 5100 #ifndef ALTQ 5101 if_settransmitfn(ifp, iflib_simple_transmit); 5102 device_printf(dev, "using simple if_transmit\n"); 5103 #else 5104 device_printf(dev, "ALTQ prevents using simple if_transmit\n"); 5105 #endif 5106 } 5107 iflib_reset_qvalues(ctx); 5108 IFNET_WLOCK(); 5109 CTX_LOCK(ctx); 5110 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5111 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5112 goto fail_unlock; 5113 } 5114 _iflib_pre_assert(scctx); 5115 ctx->ifc_txrx = *scctx->isc_txrx; 5116 5117 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR)); 5118 5119 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 5120 ctx->ifc_mediap = scctx->isc_media; 5121 5122 #ifdef INVARIANTS 5123 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5124 MPASS(scctx->isc_tx_csum_flags); 5125 #endif 5126 5127 if_setcapabilities(ifp, 5128 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG); 5129 if_setcapenable(ifp, 5130 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG); 5131 5132 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5133 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5134 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5135 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5136 5137 num_txd = iflib_num_tx_descs(ctx); 5138 num_rxd = iflib_num_rx_descs(ctx); 5139 5140 /* XXX change for per-queue sizes */ 5141 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5142 num_txd, num_rxd); 5143 5144 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5145 scctx->isc_tx_nsegments = max(1, num_txd / 5146 MAX_SINGLE_PACKET_FRACTION); 5147 if (scctx->isc_tx_tso_segments_max > num_txd / 5148 MAX_SINGLE_PACKET_FRACTION) 5149 scctx->isc_tx_tso_segments_max = max(1, 5150 num_txd / MAX_SINGLE_PACKET_FRACTION); 5151 5152 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5153 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5154 /* 5155 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5156 * but some MACs do. 5157 */ 5158 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5159 IP_MAXPACKET)); 5160 /* 5161 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5162 * into account. In the worst case, each of these calls will 5163 * add another mbuf and, thus, the requirement for another DMA 5164 * segment. So for best performance, it doesn't make sense to 5165 * advertize a maximum of TSO segments that typically will 5166 * require defragmentation in iflib_encap(). 5167 */ 5168 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5169 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5170 } 5171 if (scctx->isc_rss_table_size == 0) 5172 scctx->isc_rss_table_size = 64; 5173 scctx->isc_rss_table_mask = scctx->isc_rss_table_size - 1; 5174 5175 /* Create and start admin taskqueue */ 5176 snprintf(namebuf, TASKQUEUE_NAMELEN, "if_%s_tq", device_get_nameunit(dev)); 5177 ctx->ifc_tq = taskqueue_create_fast(namebuf, M_NOWAIT, 5178 taskqueue_thread_enqueue, &ctx->ifc_tq); 5179 if (ctx->ifc_tq == NULL) { 5180 device_printf(dev, "Unable to create admin taskqueue\n"); 5181 return (ENOMEM); 5182 } 5183 5184 err = taskqueue_start_threads(&ctx->ifc_tq, 1, PI_NET, "%s", namebuf); 5185 if (err) { 5186 device_printf(dev, 5187 "Unable to start admin taskqueue threads error: %d\n", 5188 err); 5189 taskqueue_free(ctx->ifc_tq); 5190 return (err); 5191 } 5192 5193 TASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5194 5195 /* Set up cpu set. If it fails, use the set of all CPUs. */ 5196 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 5197 device_printf(dev, "Unable to fetch CPU list\n"); 5198 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 5199 ctx->ifc_cpus_are_physical_cores = false; 5200 } else 5201 ctx->ifc_cpus_are_physical_cores = true; 5202 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 5203 5204 /* 5205 * Now set up MSI or MSI-X, should return us the number of supported 5206 * vectors (will be 1 for a legacy interrupt and MSI). 5207 */ 5208 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 5209 msix = scctx->isc_vectors; 5210 } else if (scctx->isc_msix_bar != 0) 5211 /* 5212 * The simple fact that isc_msix_bar is not 0 does not mean we 5213 * we have a good value there that is known to work. 5214 */ 5215 msix = iflib_msix_init(ctx); 5216 else { 5217 scctx->isc_vectors = 1; 5218 scctx->isc_ntxqsets = 1; 5219 scctx->isc_nrxqsets = 1; 5220 scctx->isc_intr = IFLIB_INTR_LEGACY; 5221 msix = 0; 5222 } 5223 /* Get memory for the station queues */ 5224 if ((err = iflib_queues_alloc(ctx))) { 5225 device_printf(dev, "Unable to allocate queue memory\n"); 5226 goto fail_intr_free; 5227 } 5228 5229 if ((err = iflib_qset_structures_setup(ctx))) 5230 goto fail_queues; 5231 5232 /* 5233 * Now that we know how many queues there are, get the core offset. 5234 */ 5235 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 5236 5237 if (msix > 1) { 5238 /* 5239 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 5240 * aren't the default NULL implementation. 5241 */ 5242 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 5243 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5244 kobj_desc); 5245 if (kobj_method == &kobj_desc->deflt) { 5246 device_printf(dev, 5247 "MSI-X requires ifdi_rx_queue_intr_enable method"); 5248 err = EOPNOTSUPP; 5249 goto fail_queues; 5250 } 5251 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 5252 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5253 kobj_desc); 5254 if (kobj_method == &kobj_desc->deflt) { 5255 device_printf(dev, 5256 "MSI-X requires ifdi_tx_queue_intr_enable method"); 5257 err = EOPNOTSUPP; 5258 goto fail_queues; 5259 } 5260 5261 /* 5262 * Assign the MSI-X vectors. 5263 * Note that the default NULL ifdi_msix_intr_assign method will 5264 * fail here, too. 5265 */ 5266 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 5267 if (err != 0) { 5268 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 5269 err); 5270 goto fail_queues; 5271 } 5272 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 5273 rid = 0; 5274 if (scctx->isc_intr == IFLIB_INTR_MSI) { 5275 MPASS(msix == 1); 5276 rid = 1; 5277 } 5278 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 5279 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 5280 goto fail_queues; 5281 } 5282 } else { 5283 device_printf(dev, 5284 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 5285 err = ENODEV; 5286 goto fail_queues; 5287 } 5288 5289 /* 5290 * It prevents a double-locking panic with iflib_media_status when 5291 * the driver loads. 5292 */ 5293 CTX_UNLOCK(ctx); 5294 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5295 CTX_LOCK(ctx); 5296 5297 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5298 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5299 goto fail_detach; 5300 } 5301 5302 /* 5303 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5304 * This must appear after the call to ether_ifattach() because 5305 * ether_ifattach() sets if_hdrlen to the default value. 5306 */ 5307 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5308 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5309 5310 if ((err = iflib_netmap_attach(ctx))) { 5311 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 5312 goto fail_detach; 5313 } 5314 *ctxp = ctx; 5315 5316 DEBUGNET_SET(ctx->ifc_ifp, iflib); 5317 5318 iflib_add_device_sysctl_post(ctx); 5319 iflib_add_pfil(ctx); 5320 ctx->ifc_flags |= IFC_INIT_DONE; 5321 CTX_UNLOCK(ctx); 5322 IFNET_WUNLOCK(); 5323 5324 return (0); 5325 5326 fail_detach: 5327 CTX_UNLOCK(ctx); 5328 taskqueue_drain(ctx->ifc_tq, &ctx->ifc_admin_task); 5329 ether_ifdetach(ctx->ifc_ifp); 5330 CTX_LOCK(ctx); 5331 fail_queues: 5332 sysctl_ctx_free(&ctx->ifc_sysctl_ctx); 5333 ctx->ifc_sysctl_node = NULL; 5334 /* 5335 * Drain without holding CTX_LOCK so _task_fn_admin can run to 5336 * completion if it needs the context lock. On fail_detach we already 5337 * drained above; a second drain is a no-op when the queue is empty. 5338 */ 5339 CTX_UNLOCK(ctx); 5340 taskqueue_drain(ctx->ifc_tq, &ctx->ifc_admin_task); 5341 CTX_LOCK(ctx); 5342 iflib_tqg_detach(ctx); 5343 iflib_tx_structures_free(ctx); 5344 iflib_rx_structures_free(ctx); 5345 /* 5346 * Match iflib_device_deregister: IFDI_DETACH before taskqueue_free. 5347 * Avoid IFNET_WLOCK across driver detach (LinuxKPI workqueue drain). 5348 */ 5349 IFNET_WUNLOCK(); 5350 IFDI_DETACH(ctx); 5351 IFDI_QUEUES_FREE(ctx); 5352 IFNET_WLOCK(); 5353 taskqueue_free(ctx->ifc_tq); 5354 fail_intr_free: 5355 iflib_free_intr_mem(ctx); 5356 fail_unlock: 5357 CTX_UNLOCK(ctx); 5358 IFNET_WUNLOCK(); 5359 iflib_deregister(ctx); 5360 device_set_softc(ctx->ifc_dev, NULL); 5361 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5362 free(ctx->ifc_softc, M_IFLIB); 5363 free(ctx, M_IFLIB); 5364 return (err); 5365 } 5366 5367 int 5368 iflib_device_attach(device_t dev) 5369 { 5370 if_ctx_t ctx; 5371 if_shared_ctx_t sctx; 5372 5373 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5374 return (ENOTSUP); 5375 5376 pci_enable_busmaster(dev); 5377 5378 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5379 } 5380 5381 int 5382 iflib_device_deregister(if_ctx_t ctx) 5383 { 5384 if_t ifp = ctx->ifc_ifp; 5385 device_t dev = ctx->ifc_dev; 5386 5387 sysctl_ctx_free(&ctx->ifc_sysctl_ctx); 5388 ctx->ifc_sysctl_node = NULL; 5389 5390 /* Make sure VLANS are not using driver */ 5391 if (if_vlantrunkinuse(ifp)) { 5392 device_printf(dev, "Vlan in use, detach first\n"); 5393 return (EBUSY); 5394 } 5395 #ifdef PCI_IOV 5396 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5397 device_printf(dev, "SR-IOV in use; detach first.\n"); 5398 return (EBUSY); 5399 } 5400 #endif 5401 5402 STATE_LOCK(ctx); 5403 ctx->ifc_flags |= IFC_IN_DETACH; 5404 STATE_UNLOCK(ctx); 5405 5406 /* Unregister VLAN handlers before calling iflib_stop() */ 5407 iflib_unregister_vlan_handlers(ctx); 5408 5409 iflib_netmap_detach(ifp); 5410 ether_ifdetach(ifp); 5411 5412 CTX_LOCK(ctx); 5413 iflib_stop(ctx); 5414 CTX_UNLOCK(ctx); 5415 5416 iflib_rem_pfil(ctx); 5417 if (ctx->ifc_led_dev != NULL) 5418 led_destroy(ctx->ifc_led_dev); 5419 5420 iflib_tqg_detach(ctx); 5421 iflib_tx_structures_free(ctx); 5422 iflib_rx_structures_free(ctx); 5423 5424 CTX_LOCK(ctx); 5425 IFDI_DETACH(ctx); 5426 IFDI_QUEUES_FREE(ctx); 5427 CTX_UNLOCK(ctx); 5428 5429 taskqueue_free(ctx->ifc_tq); 5430 ctx->ifc_tq = NULL; 5431 5432 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5433 iflib_free_intr_mem(ctx); 5434 5435 bus_generic_detach(dev); 5436 5437 iflib_deregister(ctx); 5438 5439 device_set_softc(ctx->ifc_dev, NULL); 5440 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5441 free(ctx->ifc_softc, M_IFLIB); 5442 unref_ctx_core_offset(ctx); 5443 free(ctx, M_IFLIB); 5444 return (0); 5445 } 5446 5447 static void 5448 iflib_tqg_detach(if_ctx_t ctx) 5449 { 5450 iflib_txq_t txq; 5451 iflib_rxq_t rxq; 5452 int i; 5453 struct taskqgroup *tqg; 5454 5455 /* XXX drain any dependent tasks */ 5456 tqg = qgroup_if_io_tqg; 5457 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5458 callout_drain(&txq->ift_timer); 5459 #ifdef DEV_NETMAP 5460 callout_drain(&txq->ift_netmap_timer); 5461 #endif /* DEV_NETMAP */ 5462 if (txq->ift_task.gt_uniq != NULL) 5463 taskqgroup_detach(tqg, &txq->ift_task); 5464 } 5465 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5466 if (rxq->ifr_task.gt_uniq != NULL) 5467 taskqgroup_detach(tqg, &rxq->ifr_task); 5468 } 5469 } 5470 5471 static void 5472 iflib_free_intr_mem(if_ctx_t ctx) 5473 { 5474 5475 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5476 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5477 } 5478 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5479 pci_release_msi(ctx->ifc_dev); 5480 } 5481 if (ctx->ifc_msix_mem != NULL) { 5482 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5483 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5484 ctx->ifc_msix_mem = NULL; 5485 } 5486 } 5487 5488 int 5489 iflib_device_detach(device_t dev) 5490 { 5491 if_ctx_t ctx = device_get_softc(dev); 5492 5493 return (iflib_device_deregister(ctx)); 5494 } 5495 5496 int 5497 iflib_device_suspend(device_t dev) 5498 { 5499 if_ctx_t ctx = device_get_softc(dev); 5500 5501 CTX_LOCK(ctx); 5502 IFDI_SUSPEND(ctx); 5503 CTX_UNLOCK(ctx); 5504 5505 return (bus_generic_suspend(dev)); 5506 } 5507 int 5508 iflib_device_shutdown(device_t dev) 5509 { 5510 if_ctx_t ctx = device_get_softc(dev); 5511 5512 CTX_LOCK(ctx); 5513 IFDI_SHUTDOWN(ctx); 5514 CTX_UNLOCK(ctx); 5515 5516 return (bus_generic_suspend(dev)); 5517 } 5518 5519 int 5520 iflib_device_resume(device_t dev) 5521 { 5522 if_ctx_t ctx = device_get_softc(dev); 5523 iflib_txq_t txq = ctx->ifc_txqs; 5524 5525 CTX_LOCK(ctx); 5526 IFDI_RESUME(ctx); 5527 iflib_if_init_locked(ctx); 5528 CTX_UNLOCK(ctx); 5529 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5530 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5531 5532 return (bus_generic_resume(dev)); 5533 } 5534 5535 int 5536 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5537 { 5538 int error; 5539 if_ctx_t ctx = device_get_softc(dev); 5540 5541 CTX_LOCK(ctx); 5542 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5543 CTX_UNLOCK(ctx); 5544 5545 return (error); 5546 } 5547 5548 void 5549 iflib_device_iov_uninit(device_t dev) 5550 { 5551 if_ctx_t ctx = device_get_softc(dev); 5552 5553 CTX_LOCK(ctx); 5554 IFDI_IOV_UNINIT(ctx); 5555 CTX_UNLOCK(ctx); 5556 } 5557 5558 int 5559 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5560 { 5561 int error; 5562 if_ctx_t ctx = device_get_softc(dev); 5563 5564 CTX_LOCK(ctx); 5565 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5566 CTX_UNLOCK(ctx); 5567 5568 return (error); 5569 } 5570 5571 /********************************************************************* 5572 * 5573 * MODULE FUNCTION DEFINITIONS 5574 * 5575 **********************************************************************/ 5576 5577 /* 5578 * - Start a fast taskqueue thread for each core 5579 * - Start a taskqueue for control operations 5580 */ 5581 static int 5582 iflib_module_init(void) 5583 { 5584 iflib_timer_default = hz / 2; 5585 return (0); 5586 } 5587 5588 static int 5589 iflib_module_event_handler(module_t mod, int what, void *arg) 5590 { 5591 int err; 5592 5593 switch (what) { 5594 case MOD_LOAD: 5595 if ((err = iflib_module_init()) != 0) 5596 return (err); 5597 break; 5598 case MOD_UNLOAD: 5599 return (EBUSY); 5600 default: 5601 return (EOPNOTSUPP); 5602 } 5603 5604 return (0); 5605 } 5606 5607 /********************************************************************* 5608 * 5609 * PUBLIC FUNCTION DEFINITIONS 5610 * ordered as in iflib.h 5611 * 5612 **********************************************************************/ 5613 5614 static void 5615 _iflib_assert(if_shared_ctx_t sctx) 5616 { 5617 int i; 5618 5619 MPASS(sctx->isc_tx_maxsize); 5620 MPASS(sctx->isc_tx_maxsegsize); 5621 5622 MPASS(sctx->isc_rx_maxsize); 5623 MPASS(sctx->isc_rx_nsegments); 5624 MPASS(sctx->isc_rx_maxsegsize); 5625 5626 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5627 for (i = 0; i < sctx->isc_nrxqs; i++) { 5628 MPASS(sctx->isc_nrxd_min[i]); 5629 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5630 MPASS(sctx->isc_nrxd_max[i]); 5631 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5632 MPASS(sctx->isc_nrxd_default[i]); 5633 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5634 } 5635 5636 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5637 for (i = 0; i < sctx->isc_ntxqs; i++) { 5638 MPASS(sctx->isc_ntxd_min[i]); 5639 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5640 MPASS(sctx->isc_ntxd_max[i]); 5641 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5642 MPASS(sctx->isc_ntxd_default[i]); 5643 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5644 } 5645 } 5646 5647 static void 5648 _iflib_pre_assert(if_softc_ctx_t scctx) 5649 { 5650 5651 MPASS(scctx->isc_txrx->ift_txd_encap); 5652 MPASS(scctx->isc_txrx->ift_txd_flush); 5653 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5654 MPASS(scctx->isc_txrx->ift_rxd_available); 5655 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5656 MPASS(scctx->isc_txrx->ift_rxd_refill); 5657 MPASS(scctx->isc_txrx->ift_rxd_flush); 5658 } 5659 5660 static void 5661 iflib_register(if_ctx_t ctx) 5662 { 5663 if_shared_ctx_t sctx = ctx->ifc_sctx; 5664 driver_t *driver = sctx->isc_driver; 5665 device_t dev = ctx->ifc_dev; 5666 if_t ifp; 5667 5668 _iflib_assert(sctx); 5669 5670 CTX_LOCK_INIT(ctx); 5671 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5672 ifp = ctx->ifc_ifp = if_alloc_dev(IFT_ETHER, dev); 5673 5674 /* 5675 * Initialize our context's device specific methods 5676 */ 5677 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5678 kobj_class_compile((kobj_class_t) driver); 5679 5680 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5681 if_setsoftc(ifp, ctx); 5682 if_setdev(ifp, dev); 5683 if_setinitfn(ifp, iflib_if_init); 5684 if_setioctlfn(ifp, iflib_if_ioctl); 5685 #ifdef ALTQ 5686 if_setstartfn(ifp, iflib_altq_if_start); 5687 if_settransmitfn(ifp, iflib_altq_if_transmit); 5688 if_setsendqready(ifp); 5689 #else 5690 if_settransmitfn(ifp, iflib_if_transmit); 5691 #endif 5692 if_setqflushfn(ifp, iflib_if_qflush); 5693 if_setgetcounterfn(ifp, iflib_if_get_counter); 5694 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5695 ctx->ifc_vlan_attach_event = 5696 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5697 EVENTHANDLER_PRI_FIRST); 5698 ctx->ifc_vlan_detach_event = 5699 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5700 EVENTHANDLER_PRI_FIRST); 5701 5702 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5703 ctx->ifc_mediap = &ctx->ifc_media; 5704 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5705 iflib_media_change, iflib_media_status); 5706 } 5707 } 5708 5709 static void 5710 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5711 { 5712 /* Unregister VLAN events */ 5713 if (ctx->ifc_vlan_attach_event != NULL) { 5714 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5715 ctx->ifc_vlan_attach_event = NULL; 5716 } 5717 if (ctx->ifc_vlan_detach_event != NULL) { 5718 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5719 ctx->ifc_vlan_detach_event = NULL; 5720 } 5721 5722 } 5723 5724 static void 5725 iflib_deregister(if_ctx_t ctx) 5726 { 5727 if_t ifp = ctx->ifc_ifp; 5728 5729 /* Remove all media */ 5730 ifmedia_removeall(&ctx->ifc_media); 5731 5732 /* Ensure that VLAN event handlers are unregistered */ 5733 iflib_unregister_vlan_handlers(ctx); 5734 5735 /* Release kobject reference */ 5736 kobj_delete((kobj_t) ctx, NULL); 5737 5738 /* Free the ifnet structure */ 5739 if_free(ifp); 5740 5741 STATE_LOCK_DESTROY(ctx); 5742 5743 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5744 CTX_LOCK_DESTROY(ctx); 5745 } 5746 5747 static int 5748 iflib_queues_alloc(if_ctx_t ctx) 5749 { 5750 if_shared_ctx_t sctx = ctx->ifc_sctx; 5751 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5752 device_t dev = ctx->ifc_dev; 5753 int nrxqsets = scctx->isc_nrxqsets; 5754 int ntxqsets = scctx->isc_ntxqsets; 5755 iflib_txq_t txq; 5756 iflib_rxq_t rxq; 5757 iflib_fl_t fl = NULL; 5758 int i, j, cpu, err, txconf, rxconf; 5759 iflib_dma_info_t ifdip; 5760 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5761 uint32_t *txqsizes = scctx->isc_txqsizes; 5762 uint8_t nrxqs = sctx->isc_nrxqs; 5763 uint8_t ntxqs = sctx->isc_ntxqs; 5764 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5765 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0); 5766 caddr_t *vaddrs; 5767 uint64_t *paddrs; 5768 5769 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5770 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5771 KASSERT(nrxqs >= fl_offset + nfree_lists, 5772 ("there must be at least a rxq for each free list")); 5773 5774 /* Allocate the TX ring struct memory */ 5775 if (!(ctx->ifc_txqs = 5776 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5777 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5778 device_printf(dev, "Unable to allocate TX ring memory\n"); 5779 err = ENOMEM; 5780 goto fail; 5781 } 5782 5783 /* Now allocate the RX */ 5784 if (!(ctx->ifc_rxqs = 5785 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5786 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5787 device_printf(dev, "Unable to allocate RX ring memory\n"); 5788 err = ENOMEM; 5789 goto rx_fail; 5790 } 5791 5792 txq = ctx->ifc_txqs; 5793 rxq = ctx->ifc_rxqs; 5794 5795 /* 5796 * XXX handle allocation failure 5797 */ 5798 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5799 /* Set up some basics */ 5800 5801 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5802 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5803 device_printf(dev, 5804 "Unable to allocate TX DMA info memory\n"); 5805 err = ENOMEM; 5806 goto err_tx_desc; 5807 } 5808 txq->ift_ifdi = ifdip; 5809 for (j = 0; j < ntxqs; j++, ifdip++) { 5810 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5811 device_printf(dev, 5812 "Unable to allocate TX descriptors\n"); 5813 err = ENOMEM; 5814 goto err_tx_desc; 5815 } 5816 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5817 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5818 } 5819 txq->ift_ctx = ctx; 5820 txq->ift_id = i; 5821 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5822 txq->ift_br_offset = 1; 5823 } else { 5824 txq->ift_br_offset = 0; 5825 } 5826 5827 if (iflib_txsd_alloc(txq)) { 5828 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5829 err = ENOMEM; 5830 goto err_tx_desc; 5831 } 5832 5833 /* Initialize the TX lock */ 5834 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5835 device_get_nameunit(dev), txq->ift_id); 5836 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5837 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5838 txq->ift_timer.c_cpu = cpu; 5839 #ifdef DEV_NETMAP 5840 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 5841 txq->ift_netmap_timer.c_cpu = cpu; 5842 #endif /* DEV_NETMAP */ 5843 5844 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5845 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5846 if (err) { 5847 /* XXX free any allocated rings */ 5848 device_printf(dev, "Unable to allocate buf_ring\n"); 5849 goto err_tx_desc; 5850 } 5851 txq->ift_reclaim_thresh = ctx->ifc_sysctl_tx_reclaim_thresh; 5852 } 5853 5854 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5855 /* Set up some basics */ 5856 callout_init(&rxq->ifr_watchdog, 1); 5857 5858 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5859 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5860 device_printf(dev, 5861 "Unable to allocate RX DMA info memory\n"); 5862 err = ENOMEM; 5863 goto err_tx_desc; 5864 } 5865 5866 rxq->ifr_ifdi = ifdip; 5867 /* XXX this needs to be changed if #rx queues != #tx queues */ 5868 rxq->ifr_ntxqirq = 1; 5869 rxq->ifr_txqid[0] = i; 5870 for (j = 0; j < nrxqs; j++, ifdip++) { 5871 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5872 device_printf(dev, 5873 "Unable to allocate RX descriptors\n"); 5874 err = ENOMEM; 5875 goto err_tx_desc; 5876 } 5877 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5878 } 5879 rxq->ifr_ctx = ctx; 5880 rxq->ifr_id = i; 5881 rxq->ifr_fl_offset = fl_offset; 5882 rxq->ifr_nfl = nfree_lists; 5883 if (!(fl = 5884 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5885 device_printf(dev, "Unable to allocate free list memory\n"); 5886 err = ENOMEM; 5887 goto err_tx_desc; 5888 } 5889 rxq->ifr_fl = fl; 5890 for (j = 0; j < nfree_lists; j++) { 5891 fl[j].ifl_rxq = rxq; 5892 fl[j].ifl_id = j; 5893 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5894 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5895 } 5896 /* Allocate receive buffers for the ring */ 5897 if (iflib_rxsd_alloc(rxq)) { 5898 device_printf(dev, 5899 "Critical Failure setting up receive buffers\n"); 5900 err = ENOMEM; 5901 goto err_rx_desc; 5902 } 5903 5904 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5905 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5906 M_WAITOK); 5907 } 5908 5909 /* TXQs */ 5910 vaddrs = malloc(sizeof(caddr_t) * ntxqsets * ntxqs, M_IFLIB, M_WAITOK); 5911 paddrs = malloc(sizeof(uint64_t) * ntxqsets * ntxqs, M_IFLIB, M_WAITOK); 5912 for (i = 0; i < ntxqsets; i++) { 5913 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5914 5915 for (j = 0; j < ntxqs; j++, di++) { 5916 vaddrs[i * ntxqs + j] = di->idi_vaddr; 5917 paddrs[i * ntxqs + j] = di->idi_paddr; 5918 } 5919 } 5920 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5921 device_printf(ctx->ifc_dev, 5922 "Unable to allocate device TX queue\n"); 5923 iflib_tx_structures_free(ctx); 5924 free(vaddrs, M_IFLIB); 5925 free(paddrs, M_IFLIB); 5926 goto err_rx_desc; 5927 } 5928 free(vaddrs, M_IFLIB); 5929 free(paddrs, M_IFLIB); 5930 5931 /* RXQs */ 5932 vaddrs = malloc(sizeof(caddr_t) * nrxqsets * nrxqs, M_IFLIB, M_WAITOK); 5933 paddrs = malloc(sizeof(uint64_t) * nrxqsets * nrxqs, M_IFLIB, M_WAITOK); 5934 for (i = 0; i < nrxqsets; i++) { 5935 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5936 5937 for (j = 0; j < nrxqs; j++, di++) { 5938 vaddrs[i * nrxqs + j] = di->idi_vaddr; 5939 paddrs[i * nrxqs + j] = di->idi_paddr; 5940 } 5941 } 5942 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5943 device_printf(ctx->ifc_dev, 5944 "Unable to allocate device RX queue\n"); 5945 iflib_tx_structures_free(ctx); 5946 free(vaddrs, M_IFLIB); 5947 free(paddrs, M_IFLIB); 5948 goto err_rx_desc; 5949 } 5950 free(vaddrs, M_IFLIB); 5951 free(paddrs, M_IFLIB); 5952 5953 return (0); 5954 5955 /* XXX handle allocation failure changes */ 5956 err_rx_desc: 5957 err_tx_desc: 5958 rx_fail: 5959 if (ctx->ifc_rxqs != NULL) 5960 free(ctx->ifc_rxqs, M_IFLIB); 5961 ctx->ifc_rxqs = NULL; 5962 if (ctx->ifc_txqs != NULL) 5963 free(ctx->ifc_txqs, M_IFLIB); 5964 ctx->ifc_txqs = NULL; 5965 fail: 5966 return (err); 5967 } 5968 5969 static int 5970 iflib_tx_structures_setup(if_ctx_t ctx) 5971 { 5972 iflib_txq_t txq = ctx->ifc_txqs; 5973 int i; 5974 5975 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5976 iflib_txq_setup(txq); 5977 5978 return (0); 5979 } 5980 5981 static void 5982 iflib_tx_structures_free(if_ctx_t ctx) 5983 { 5984 iflib_txq_t txq = ctx->ifc_txqs; 5985 if_shared_ctx_t sctx = ctx->ifc_sctx; 5986 int i, j; 5987 5988 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5989 for (j = 0; j < sctx->isc_ntxqs; j++) 5990 iflib_dma_free(&txq->ift_ifdi[j]); 5991 iflib_txq_destroy(txq); 5992 } 5993 free(ctx->ifc_txqs, M_IFLIB); 5994 ctx->ifc_txqs = NULL; 5995 } 5996 5997 /********************************************************************* 5998 * 5999 * Initialize all receive rings. 6000 * 6001 **********************************************************************/ 6002 static int 6003 iflib_rx_structures_setup(if_ctx_t ctx) 6004 { 6005 iflib_rxq_t rxq = ctx->ifc_rxqs; 6006 int q; 6007 #if defined(INET6) || defined(INET) 6008 int err, i; 6009 #endif 6010 6011 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 6012 #if defined(INET6) || defined(INET) 6013 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 6014 TCP_LRO_ENTRIES, min(1024, 6015 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 6016 if (err != 0) { 6017 device_printf(ctx->ifc_dev, 6018 "LRO Initialization failed!\n"); 6019 goto fail; 6020 } 6021 #endif 6022 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 6023 } 6024 return (0); 6025 #if defined(INET6) || defined(INET) 6026 fail: 6027 /* 6028 * Free LRO resources allocated so far, we will only handle 6029 * the rings that completed, the failing case will have 6030 * cleaned up for itself. 'q' failed, so its the terminus. 6031 */ 6032 rxq = ctx->ifc_rxqs; 6033 for (i = 0; i < q; ++i, rxq++) { 6034 tcp_lro_free(&rxq->ifr_lc); 6035 } 6036 return (err); 6037 #endif 6038 } 6039 6040 /********************************************************************* 6041 * 6042 * Free all receive rings. 6043 * 6044 **********************************************************************/ 6045 static void 6046 iflib_rx_structures_free(if_ctx_t ctx) 6047 { 6048 iflib_rxq_t rxq = ctx->ifc_rxqs; 6049 if_shared_ctx_t sctx = ctx->ifc_sctx; 6050 int i, j; 6051 6052 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 6053 for (j = 0; j < sctx->isc_nrxqs; j++) 6054 iflib_dma_free(&rxq->ifr_ifdi[j]); 6055 iflib_rx_sds_free(rxq); 6056 #if defined(INET6) || defined(INET) 6057 tcp_lro_free(&rxq->ifr_lc); 6058 #endif 6059 } 6060 free(ctx->ifc_rxqs, M_IFLIB); 6061 ctx->ifc_rxqs = NULL; 6062 } 6063 6064 static int 6065 iflib_qset_structures_setup(if_ctx_t ctx) 6066 { 6067 int err; 6068 6069 /* 6070 * It is expected that the caller takes care of freeing queues if this 6071 * fails. 6072 */ 6073 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 6074 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 6075 return (err); 6076 } 6077 6078 if ((err = iflib_rx_structures_setup(ctx)) != 0) 6079 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 6080 6081 return (err); 6082 } 6083 6084 int 6085 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 6086 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 6087 { 6088 6089 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 6090 } 6091 6092 /* Just to avoid copy/paste */ 6093 static inline int 6094 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6095 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 6096 const char *name) 6097 { 6098 device_t dev; 6099 unsigned int base_cpuid, cpuid; 6100 int err; 6101 6102 dev = ctx->ifc_dev; 6103 base_cpuid = ctx->ifc_sysctl_core_offset; 6104 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX); 6105 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, 6106 irq ? irq->ii_res : NULL, name); 6107 if (err) { 6108 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6109 return (err); 6110 } 6111 #ifdef notyet 6112 if (cpuid > ctx->ifc_cpuid_highest) 6113 ctx->ifc_cpuid_highest = cpuid; 6114 #endif 6115 return (0); 6116 } 6117 6118 /* 6119 * Allocate a hardware interrupt for subctx using the parent (ctx)'s hardware 6120 * resources. 6121 * 6122 * Similar to iflib_irq_alloc_generic(), but for interrupt type IFLIB_INTR_RXTX 6123 * only. 6124 * 6125 * XXX: Could be removed if subctx's dev has its intr resource allocation 6126 * methods replaced with custom ones? 6127 */ 6128 int 6129 iflib_irq_alloc_generic_subctx(if_ctx_t ctx, if_ctx_t subctx, if_irq_t irq, 6130 int rid, iflib_intr_type_t type, 6131 driver_filter_t *filter, void *filter_arg, 6132 int qid, const char *name) 6133 { 6134 device_t dev, subdev; 6135 struct grouptask *gtask; 6136 struct taskqgroup *tqg; 6137 iflib_filter_info_t info; 6138 gtask_fn_t *fn; 6139 int tqrid, err; 6140 driver_filter_t *intr_fast; 6141 void *q; 6142 6143 MPASS(ctx != NULL); 6144 MPASS(subctx != NULL); 6145 6146 tqrid = rid; 6147 dev = ctx->ifc_dev; 6148 subdev = subctx->ifc_dev; 6149 6150 switch (type) { 6151 case IFLIB_INTR_RXTX: 6152 q = &subctx->ifc_rxqs[qid]; 6153 info = &subctx->ifc_rxqs[qid].ifr_filter_info; 6154 gtask = &subctx->ifc_rxqs[qid].ifr_task; 6155 tqg = qgroup_if_io_tqg; 6156 fn = _task_fn_rx; 6157 intr_fast = iflib_fast_intr_rxtx; 6158 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6159 break; 6160 default: 6161 device_printf(dev, "%s: unknown net intr type for subctx %s (%d)\n", 6162 __func__, device_get_nameunit(subdev), type); 6163 return (EINVAL); 6164 } 6165 6166 info->ifi_filter = filter; 6167 info->ifi_filter_arg = filter_arg; 6168 info->ifi_task = gtask; 6169 info->ifi_ctx = q; 6170 6171 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6172 6173 /* Allocate interrupts from hardware using parent context */ 6174 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6175 if (err != 0) { 6176 device_printf(dev, "_iflib_irq_alloc failed for subctx %s: %d\n", 6177 device_get_nameunit(subdev), err); 6178 return (err); 6179 } 6180 6181 if (tqrid != -1) { 6182 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6183 name); 6184 if (err) 6185 return (err); 6186 } else { 6187 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6188 } 6189 6190 return (0); 6191 } 6192 6193 int 6194 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6195 iflib_intr_type_t type, driver_filter_t *filter, 6196 void *filter_arg, int qid, const char *name) 6197 { 6198 device_t dev; 6199 struct grouptask *gtask; 6200 struct taskqgroup *tqg; 6201 iflib_filter_info_t info; 6202 gtask_fn_t *fn; 6203 int tqrid, err; 6204 driver_filter_t *intr_fast; 6205 void *q; 6206 6207 info = &ctx->ifc_filter_info; 6208 tqrid = rid; 6209 6210 switch (type) { 6211 /* XXX merge tx/rx for netmap? */ 6212 case IFLIB_INTR_TX: 6213 q = &ctx->ifc_txqs[qid]; 6214 info = &ctx->ifc_txqs[qid].ift_filter_info; 6215 gtask = &ctx->ifc_txqs[qid].ift_task; 6216 tqg = qgroup_if_io_tqg; 6217 fn = _task_fn_tx; 6218 intr_fast = iflib_fast_intr; 6219 GROUPTASK_INIT(gtask, 0, fn, q); 6220 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6221 break; 6222 case IFLIB_INTR_RX: 6223 q = &ctx->ifc_rxqs[qid]; 6224 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6225 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6226 tqg = qgroup_if_io_tqg; 6227 fn = _task_fn_rx; 6228 intr_fast = iflib_fast_intr; 6229 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6230 break; 6231 case IFLIB_INTR_RXTX: 6232 q = &ctx->ifc_rxqs[qid]; 6233 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6234 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6235 tqg = qgroup_if_io_tqg; 6236 fn = _task_fn_rx; 6237 intr_fast = iflib_fast_intr_rxtx; 6238 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6239 break; 6240 case IFLIB_INTR_ADMIN: 6241 q = ctx; 6242 tqrid = -1; 6243 info = &ctx->ifc_filter_info; 6244 gtask = NULL; 6245 intr_fast = iflib_fast_intr_ctx; 6246 break; 6247 default: 6248 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6249 __func__); 6250 return (EINVAL); 6251 } 6252 6253 info->ifi_filter = filter; 6254 info->ifi_filter_arg = filter_arg; 6255 info->ifi_task = gtask; 6256 info->ifi_ctx = q; 6257 6258 dev = ctx->ifc_dev; 6259 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6260 if (err != 0) { 6261 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6262 return (err); 6263 } 6264 if (type == IFLIB_INTR_ADMIN) 6265 return (0); 6266 6267 if (tqrid != -1) { 6268 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6269 name); 6270 if (err) 6271 return (err); 6272 } else { 6273 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6274 } 6275 6276 return (0); 6277 } 6278 6279 void 6280 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6281 void *arg, int qid, const char *name) 6282 { 6283 device_t dev; 6284 struct grouptask *gtask; 6285 struct taskqgroup *tqg; 6286 gtask_fn_t *fn; 6287 void *q; 6288 int err; 6289 6290 switch (type) { 6291 case IFLIB_INTR_TX: 6292 q = &ctx->ifc_txqs[qid]; 6293 gtask = &ctx->ifc_txqs[qid].ift_task; 6294 tqg = qgroup_if_io_tqg; 6295 fn = _task_fn_tx; 6296 GROUPTASK_INIT(gtask, 0, fn, q); 6297 break; 6298 case IFLIB_INTR_RX: 6299 q = &ctx->ifc_rxqs[qid]; 6300 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6301 tqg = qgroup_if_io_tqg; 6302 fn = _task_fn_rx; 6303 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6304 break; 6305 case IFLIB_INTR_IOV: 6306 TASK_INIT(&ctx->ifc_vflr_task, 0, _task_fn_iov, ctx); 6307 return; 6308 default: 6309 panic("unknown net intr type"); 6310 } 6311 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name); 6312 if (err) { 6313 dev = ctx->ifc_dev; 6314 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL, 6315 name); 6316 } 6317 } 6318 6319 void 6320 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6321 { 6322 6323 if (irq->ii_tag) 6324 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6325 6326 if (irq->ii_res) 6327 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6328 rman_get_rid(irq->ii_res), irq->ii_res); 6329 } 6330 6331 static int 6332 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6333 { 6334 iflib_txq_t txq = ctx->ifc_txqs; 6335 iflib_rxq_t rxq = ctx->ifc_rxqs; 6336 if_irq_t irq = &ctx->ifc_legacy_irq; 6337 iflib_filter_info_t info; 6338 device_t dev; 6339 struct grouptask *gtask; 6340 struct resource *res; 6341 int err, tqrid; 6342 bool rx_only; 6343 6344 info = &rxq->ifr_filter_info; 6345 gtask = &rxq->ifr_task; 6346 tqrid = *rid; 6347 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6348 6349 ctx->ifc_flags |= IFC_LEGACY; 6350 info->ifi_filter = filter; 6351 info->ifi_filter_arg = filter_arg; 6352 info->ifi_task = gtask; 6353 info->ifi_ctx = rxq; 6354 6355 dev = ctx->ifc_dev; 6356 /* We allocate a single interrupt resource */ 6357 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr : 6358 iflib_fast_intr_rxtx, NULL, info, name); 6359 if (err != 0) 6360 return (err); 6361 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, rxq); 6362 res = irq->ii_res; 6363 taskqgroup_attach(qgroup_if_io_tqg, gtask, rxq, dev, res, name); 6364 6365 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6366 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6367 "tx"); 6368 return (0); 6369 } 6370 6371 void 6372 iflib_led_create(if_ctx_t ctx) 6373 { 6374 6375 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6376 device_get_nameunit(ctx->ifc_dev)); 6377 } 6378 6379 void 6380 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6381 { 6382 6383 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6384 } 6385 6386 void 6387 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6388 { 6389 6390 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6391 } 6392 6393 void 6394 iflib_admin_intr_deferred(if_ctx_t ctx) 6395 { 6396 6397 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_admin_task); 6398 } 6399 6400 void 6401 iflib_iov_intr_deferred(if_ctx_t ctx) 6402 { 6403 6404 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_vflr_task); 6405 } 6406 6407 void 6408 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6409 { 6410 6411 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6412 name); 6413 } 6414 6415 void 6416 iflib_config_task_init(if_ctx_t ctx, struct task *config_task, task_fn_t *fn) 6417 { 6418 TASK_INIT(config_task, 0, fn, ctx); 6419 } 6420 6421 void 6422 iflib_config_task_enqueue(if_ctx_t ctx, struct task *config_task) 6423 { 6424 taskqueue_enqueue(ctx->ifc_tq, config_task); 6425 } 6426 6427 void 6428 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6429 { 6430 if_t ifp = ctx->ifc_ifp; 6431 iflib_txq_t txq = ctx->ifc_txqs; 6432 6433 if_setbaudrate(ifp, baudrate); 6434 if (baudrate >= IF_Gbps(10)) { 6435 STATE_LOCK(ctx); 6436 ctx->ifc_flags |= IFC_PREFETCH; 6437 STATE_UNLOCK(ctx); 6438 } 6439 /* If link down, disable watchdog */ 6440 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6441 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6442 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6443 } 6444 ctx->ifc_link_state = link_state; 6445 if_link_state_change(ifp, link_state); 6446 } 6447 6448 static int 6449 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6450 { 6451 int credits; 6452 #ifdef INVARIANTS 6453 int credits_pre = txq->ift_cidx_processed; 6454 #endif 6455 6456 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6457 BUS_DMASYNC_POSTREAD); 6458 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6459 return (0); 6460 6461 txq->ift_processed += credits; 6462 txq->ift_cidx_processed += credits; 6463 6464 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6465 if (txq->ift_cidx_processed >= txq->ift_size) 6466 txq->ift_cidx_processed -= txq->ift_size; 6467 return (credits); 6468 } 6469 6470 static int 6471 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6472 { 6473 iflib_fl_t fl; 6474 u_int i; 6475 6476 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6477 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6478 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6479 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6480 budget)); 6481 } 6482 6483 void 6484 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6485 const char *description, if_int_delay_info_t info, 6486 int offset, int value) 6487 { 6488 info->iidi_ctx = ctx; 6489 info->iidi_offset = offset; 6490 info->iidi_value = value; 6491 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6492 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6493 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6494 info, 0, iflib_sysctl_int_delay, "I", description); 6495 } 6496 6497 struct sx * 6498 iflib_ctx_lock_get(if_ctx_t ctx) 6499 { 6500 6501 return (&ctx->ifc_ctx_sx); 6502 } 6503 6504 static int 6505 iflib_msix_init(if_ctx_t ctx) 6506 { 6507 device_t dev = ctx->ifc_dev; 6508 if_shared_ctx_t sctx = ctx->ifc_sctx; 6509 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6510 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6511 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6512 6513 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6514 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6515 6516 if (bootverbose) 6517 device_printf(dev, "msix_init qsets capped at %d\n", 6518 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6519 6520 /* Override by tuneable */ 6521 if (scctx->isc_disable_msix) 6522 goto msi; 6523 6524 /* First try MSI-X */ 6525 if ((msgs = pci_msix_count(dev)) == 0) { 6526 if (bootverbose) 6527 device_printf(dev, "MSI-X not supported or disabled\n"); 6528 goto msi; 6529 } 6530 6531 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6532 /* 6533 * bar == -1 => "trust me I know what I'm doing" 6534 * Some drivers are for hardware that is so shoddily 6535 * documented that no one knows which bars are which 6536 * so the developer has to map all bars. This hack 6537 * allows shoddy garbage to use MSI-X in this framework. 6538 */ 6539 if (bar != -1) { 6540 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6541 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6542 if (ctx->ifc_msix_mem == NULL) { 6543 device_printf(dev, "Unable to map MSI-X table\n"); 6544 goto msi; 6545 } 6546 } 6547 6548 admincnt = sctx->isc_admin_intrcnt; 6549 #if IFLIB_DEBUG 6550 /* use only 1 qset in debug mode */ 6551 queuemsgs = min(msgs - admincnt, 1); 6552 #else 6553 queuemsgs = msgs - admincnt; 6554 #endif 6555 #ifdef RSS 6556 queues = imin(queuemsgs, rss_getnumbuckets()); 6557 #else 6558 queues = queuemsgs; 6559 #endif 6560 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6561 if (bootverbose) 6562 device_printf(dev, 6563 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6564 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6565 #ifdef RSS 6566 /* If we're doing RSS, clamp at the number of RSS buckets */ 6567 if (queues > rss_getnumbuckets()) 6568 queues = rss_getnumbuckets(); 6569 #endif 6570 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6571 rx_queues = iflib_num_rx_queues; 6572 else 6573 rx_queues = queues; 6574 6575 if (rx_queues > scctx->isc_nrxqsets) 6576 rx_queues = scctx->isc_nrxqsets; 6577 6578 /* 6579 * We want this to be all logical CPUs by default 6580 */ 6581 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6582 tx_queues = iflib_num_tx_queues; 6583 else 6584 tx_queues = mp_ncpus; 6585 6586 if (tx_queues > scctx->isc_ntxqsets) 6587 tx_queues = scctx->isc_ntxqsets; 6588 6589 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6590 #ifdef INVARIANTS 6591 if (tx_queues != rx_queues) 6592 device_printf(dev, 6593 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6594 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6595 #endif 6596 tx_queues = min(rx_queues, tx_queues); 6597 rx_queues = min(rx_queues, tx_queues); 6598 } 6599 6600 vectors = rx_queues + admincnt; 6601 if (msgs < vectors) { 6602 device_printf(dev, 6603 "insufficient number of MSI-X vectors " 6604 "(supported %d, need %d)\n", msgs, vectors); 6605 goto msi; 6606 } 6607 6608 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6609 tx_queues); 6610 msgs = vectors; 6611 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6612 if (vectors != msgs) { 6613 device_printf(dev, 6614 "Unable to allocate sufficient MSI-X vectors " 6615 "(got %d, need %d)\n", vectors, msgs); 6616 pci_release_msi(dev); 6617 if (bar != -1) { 6618 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6619 ctx->ifc_msix_mem); 6620 ctx->ifc_msix_mem = NULL; 6621 } 6622 goto msi; 6623 } 6624 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6625 vectors); 6626 scctx->isc_vectors = vectors; 6627 scctx->isc_nrxqsets = rx_queues; 6628 scctx->isc_ntxqsets = tx_queues; 6629 scctx->isc_intr = IFLIB_INTR_MSIX; 6630 6631 return (vectors); 6632 } else { 6633 device_printf(dev, 6634 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6635 err); 6636 if (bar != -1) { 6637 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6638 ctx->ifc_msix_mem); 6639 ctx->ifc_msix_mem = NULL; 6640 } 6641 } 6642 6643 msi: 6644 vectors = pci_msi_count(dev); 6645 scctx->isc_nrxqsets = 1; 6646 scctx->isc_ntxqsets = 1; 6647 scctx->isc_vectors = vectors; 6648 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6649 device_printf(dev, "Using an MSI interrupt\n"); 6650 scctx->isc_intr = IFLIB_INTR_MSI; 6651 } else { 6652 scctx->isc_vectors = 1; 6653 device_printf(dev, "Using a Legacy interrupt\n"); 6654 scctx->isc_intr = IFLIB_INTR_LEGACY; 6655 } 6656 6657 return (vectors); 6658 } 6659 6660 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6661 6662 static int 6663 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6664 { 6665 int rc; 6666 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6667 struct sbuf *sb; 6668 const char *ring_state = "UNKNOWN"; 6669 6670 /* XXX needed ? */ 6671 rc = sysctl_wire_old_buffer(req, 0); 6672 MPASS(rc == 0); 6673 if (rc != 0) 6674 return (rc); 6675 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6676 MPASS(sb != NULL); 6677 if (sb == NULL) 6678 return (ENOMEM); 6679 if (state[3] <= 3) 6680 ring_state = ring_states[state[3]]; 6681 6682 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6683 state[0], state[1], state[2], ring_state); 6684 rc = sbuf_finish(sb); 6685 sbuf_delete(sb); 6686 return (rc); 6687 } 6688 6689 enum iflib_ndesc_handler { 6690 IFLIB_NTXD_HANDLER, 6691 IFLIB_NRXD_HANDLER, 6692 }; 6693 6694 static int 6695 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6696 { 6697 if_ctx_t ctx = (void *)arg1; 6698 enum iflib_ndesc_handler type = arg2; 6699 char buf[256] = {0}; 6700 qidx_t *ndesc; 6701 char *p, *next; 6702 int nqs, rc, i; 6703 6704 nqs = 8; 6705 switch (type) { 6706 case IFLIB_NTXD_HANDLER: 6707 ndesc = ctx->ifc_sysctl_ntxds; 6708 if (ctx->ifc_sctx) 6709 nqs = ctx->ifc_sctx->isc_ntxqs; 6710 break; 6711 case IFLIB_NRXD_HANDLER: 6712 ndesc = ctx->ifc_sysctl_nrxds; 6713 if (ctx->ifc_sctx) 6714 nqs = ctx->ifc_sctx->isc_nrxqs; 6715 break; 6716 default: 6717 printf("%s: unhandled type\n", __func__); 6718 return (EINVAL); 6719 } 6720 if (nqs == 0) 6721 nqs = 8; 6722 6723 for (i = 0; i < 8; i++) { 6724 if (i >= nqs) 6725 break; 6726 if (i) 6727 strcat(buf, ","); 6728 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6729 } 6730 6731 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6732 if (rc || req->newptr == NULL) 6733 return (rc); 6734 6735 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6736 i++, p = strsep(&next, " ,")) { 6737 ndesc[i] = strtoul(p, NULL, 10); 6738 } 6739 6740 return (rc); 6741 } 6742 6743 static int 6744 iflib_handle_tx_reclaim_thresh(SYSCTL_HANDLER_ARGS) 6745 { 6746 if_ctx_t ctx = (void *)arg1; 6747 iflib_txq_t txq; 6748 int i, err; 6749 int thresh; 6750 6751 thresh = ctx->ifc_sysctl_tx_reclaim_thresh; 6752 err = sysctl_handle_int(oidp, &thresh, arg2, req); 6753 if (err != 0) { 6754 return err; 6755 } 6756 6757 if (thresh == ctx->ifc_sysctl_tx_reclaim_thresh) 6758 return 0; 6759 6760 if (thresh > ctx->ifc_softc_ctx.isc_ntxd[0] / 2) { 6761 device_printf(ctx->ifc_dev, "TX Reclaim thresh must be <= %d\n", 6762 ctx->ifc_softc_ctx.isc_ntxd[0] / 2); 6763 return (EINVAL); 6764 } 6765 6766 ctx->ifc_sysctl_tx_reclaim_thresh = thresh; 6767 if (ctx->ifc_txqs == NULL) 6768 return (err); 6769 6770 txq = &ctx->ifc_txqs[0]; 6771 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6772 txq->ift_reclaim_thresh = thresh; 6773 } 6774 return (err); 6775 } 6776 6777 static int 6778 iflib_handle_tx_reclaim_ticks(SYSCTL_HANDLER_ARGS) 6779 { 6780 if_ctx_t ctx = (void *)arg1; 6781 iflib_txq_t txq; 6782 int i, err; 6783 int ticks; 6784 6785 ticks = ctx->ifc_sysctl_tx_reclaim_ticks; 6786 err = sysctl_handle_int(oidp, &ticks, arg2, req); 6787 if (err != 0) { 6788 return err; 6789 } 6790 6791 if (ticks == ctx->ifc_sysctl_tx_reclaim_ticks) 6792 return 0; 6793 6794 if (ticks > hz) { 6795 device_printf(ctx->ifc_dev, 6796 "TX Reclaim ticks must be <= hz (%d)\n", hz); 6797 return (EINVAL); 6798 } 6799 6800 ctx->ifc_sysctl_tx_reclaim_ticks = ticks; 6801 if (ctx->ifc_txqs == NULL) 6802 return (err); 6803 6804 txq = &ctx->ifc_txqs[0]; 6805 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6806 txq->ift_reclaim_ticks = ticks; 6807 } 6808 return (err); 6809 } 6810 6811 static int 6812 iflib_handle_tx_defer_mfree(SYSCTL_HANDLER_ARGS) 6813 { 6814 if_ctx_t ctx = (void *)arg1; 6815 iflib_txq_t txq; 6816 int i, err; 6817 int defer; 6818 6819 defer = ctx->ifc_sysctl_tx_defer_mfree; 6820 err = sysctl_handle_int(oidp, &defer, arg2, req); 6821 if (err != 0) { 6822 return err; 6823 } 6824 6825 if (defer == ctx->ifc_sysctl_tx_defer_mfree) 6826 return 0; 6827 6828 ctx->ifc_sysctl_tx_defer_mfree = defer; 6829 if (ctx->ifc_txqs == NULL) 6830 return (err); 6831 6832 txq = &ctx->ifc_txqs[0]; 6833 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6834 txq->ift_defer_mfree = defer; 6835 } 6836 return (err); 6837 } 6838 6839 #define NAME_BUFLEN 32 6840 static void 6841 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6842 { 6843 device_t dev = iflib_get_dev(ctx); 6844 struct sysctl_oid_list *child, *oid_list; 6845 struct sysctl_oid *node; 6846 6847 sysctl_ctx_init(&ctx->ifc_sysctl_ctx); 6848 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6849 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(&ctx->ifc_sysctl_ctx, child, 6850 OID_AUTO, "iflib", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 6851 "IFLIB fields"); 6852 oid_list = SYSCTL_CHILDREN(node); 6853 6854 SYSCTL_ADD_CONST_STRING(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "driver_version", 6855 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, "driver version"); 6856 6857 SYSCTL_ADD_BOOL(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "simple_tx", 6858 CTLFLAG_RDTUN, &ctx->ifc_sysctl_simple_tx, 0, 6859 "use simple tx ring"); 6860 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_ntxqs", 6861 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6862 "# of txqs to use, 0 => use default #"); 6863 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_nrxqs", 6864 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6865 "# of rxqs to use, 0 => use default #"); 6866 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_qs_enable", 6867 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6868 "permit #txq != #rxq"); 6869 SYSCTL_ADD_INT(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "disable_msix", 6870 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6871 "disable MSI-X (default 0)"); 6872 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "rx_budget", 6873 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, "set the RX budget"); 6874 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "tx_abdicate", 6875 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6876 "cause TX to abdicate instead of running to completion"); 6877 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6878 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "core_offset", 6879 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6880 "offset to start using cores at"); 6881 SYSCTL_ADD_U8(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "separate_txrx", 6882 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6883 "use separate cores for TX and RX"); 6884 SYSCTL_ADD_U8(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "use_logical_cores", 6885 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0, 6886 "try to make use of logical cores for TX and RX"); 6887 SYSCTL_ADD_U16(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "use_extra_msix_vectors", 6888 CTLFLAG_RDTUN, &ctx->ifc_sysctl_extra_msix_vectors, 0, 6889 "attempt to reserve the given number of extra MSI-X vectors during driver load for the creation of additional interfaces later"); 6890 SYSCTL_ADD_INT(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "allocated_msix_vectors", 6891 CTLFLAG_RDTUN, &ctx->ifc_softc_ctx.isc_vectors, 0, 6892 "total # of MSI-X vectors allocated by driver"); 6893 6894 /* XXX change for per-queue sizes */ 6895 SYSCTL_ADD_PROC(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_ntxds", 6896 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6897 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6898 "list of # of TX descriptors to use, 0 = use default #"); 6899 SYSCTL_ADD_PROC(&ctx->ifc_sysctl_ctx, oid_list, OID_AUTO, "override_nrxds", 6900 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6901 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6902 "list of # of RX descriptors to use, 0 = use default #"); 6903 } 6904 6905 static void 6906 iflib_add_device_sysctl_post(if_ctx_t ctx) 6907 { 6908 if_shared_ctx_t sctx = ctx->ifc_sctx; 6909 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6910 struct sysctl_oid_list *child; 6911 struct sysctl_ctx_list *ctx_list = &ctx->ifc_sysctl_ctx; 6912 iflib_fl_t fl; 6913 iflib_txq_t txq; 6914 iflib_rxq_t rxq; 6915 int i, j; 6916 char namebuf[NAME_BUFLEN]; 6917 char *qfmt; 6918 struct sysctl_oid *queue_node, *fl_node, *node; 6919 struct sysctl_oid_list *queue_list, *fl_list; 6920 6921 node = ctx->ifc_sysctl_node; 6922 child = SYSCTL_CHILDREN(node); 6923 6924 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_reclaim_thresh", 6925 CTLTYPE_INT | CTLFLAG_RWTUN, ctx, 6926 0, iflib_handle_tx_reclaim_thresh, "I", 6927 "Number of TX descs outstanding before reclaim is called"); 6928 6929 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_reclaim_ticks", 6930 CTLTYPE_INT | CTLFLAG_RWTUN, ctx, 6931 0, iflib_handle_tx_reclaim_ticks, "I", 6932 "Number of ticks before a TX reclaim is forced"); 6933 6934 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_defer_mfree", 6935 CTLTYPE_INT | CTLFLAG_RWTUN, ctx, 6936 0, iflib_handle_tx_defer_mfree, "I", 6937 "Free completed transmits outside of TX ring lock"); 6938 6939 if (scctx->isc_ntxqsets > 100) 6940 qfmt = "txq%03d"; 6941 else if (scctx->isc_ntxqsets > 10) 6942 qfmt = "txq%02d"; 6943 else 6944 qfmt = "txq%d"; 6945 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6946 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6947 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6948 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6949 queue_list = SYSCTL_CHILDREN(queue_node); 6950 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 6951 CTLFLAG_RD, &txq->ift_task.gt_cpu, 0, 6952 "cpu this queue is bound to"); 6953 #if MEMORY_LOGGING 6954 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6955 CTLFLAG_RD, &txq->ift_dequeued, "total mbufs freed"); 6956 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6957 CTLFLAG_RD, &txq->ift_enqueued, "total mbufs enqueued"); 6958 #endif 6959 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6960 CTLFLAG_RD, &txq->ift_mbuf_defrag, 6961 "# of times m_defrag was called"); 6962 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6963 CTLFLAG_RD, &txq->ift_pullups, 6964 "# of times m_pullup was called"); 6965 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 6966 "mbuf_defrag_failed", CTLFLAG_RD, 6967 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6968 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 6969 "no_desc_avail", CTLFLAG_RD, &txq->ift_no_desc_avail, 6970 "# of times no descriptors were available"); 6971 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 6972 "tx_map_failed", CTLFLAG_RD, &txq->ift_map_failed, 6973 "# of times DMA map failed"); 6974 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 6975 "txd_encap_efbig", CTLFLAG_RD, &txq->ift_txd_encap_efbig, 6976 "# of times txd_encap returned EFBIG"); 6977 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 6978 "no_tx_dma_setup", CTLFLAG_RD, &txq->ift_no_tx_dma_setup, 6979 "# of times map failed for other than EFBIG"); 6980 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6981 CTLFLAG_RD, &txq->ift_pidx, 1, "Producer Index"); 6982 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6983 CTLFLAG_RD, &txq->ift_cidx, 1, "Consumer Index"); 6984 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, 6985 "txq_cidx_processed", CTLFLAG_RD, &txq->ift_cidx_processed, 6986 1, "Consumer Index seen by credit update"); 6987 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6988 CTLFLAG_RD, &txq->ift_in_use, 1, "descriptors in use"); 6989 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, 6990 "txq_processed", CTLFLAG_RD, &txq->ift_processed, 6991 "descriptors procesed for clean"); 6992 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6993 CTLFLAG_RD, &txq->ift_cleaned, "total cleaned"); 6994 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6995 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6996 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6997 mp_ring_state_handler, "A", "soft ring state"); 6998 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 6999 "r_enqueues", CTLFLAG_RD, &txq->ift_br->enqueues, 7000 "# of enqueues to the mp_ring for this queue"); 7001 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7002 "r_drops", CTLFLAG_RD, &txq->ift_br->drops, 7003 "# of drops in the mp_ring for this queue"); 7004 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7005 "r_starts", CTLFLAG_RD, &txq->ift_br->starts, 7006 "# of normal consumer starts in mp_ring for this queue"); 7007 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7008 "r_stalls", CTLFLAG_RD, &txq->ift_br->stalls, 7009 "# of consumer stalls in the mp_ring for this queue"); 7010 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7011 "r_restarts", CTLFLAG_RD, &txq->ift_br->restarts, 7012 "# of consumer restarts in the mp_ring for this queue"); 7013 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, 7014 "r_abdications", CTLFLAG_RD, &txq->ift_br->abdications, 7015 "# of consumer abdications in the mp_ring for this queue"); 7016 } 7017 7018 if (scctx->isc_nrxqsets > 100) 7019 qfmt = "rxq%03d"; 7020 else if (scctx->isc_nrxqsets > 10) 7021 qfmt = "rxq%02d"; 7022 else 7023 qfmt = "rxq%d"; 7024 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 7025 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 7026 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 7027 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 7028 queue_list = SYSCTL_CHILDREN(queue_node); 7029 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 7030 CTLFLAG_RD, &rxq->ifr_task.gt_cpu, 0, 7031 "cpu this queue is bound to"); 7032 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 7033 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, 7034 "rxq_cq_cidx", CTLFLAG_RD, &rxq->ifr_cq_cidx, 1, 7035 "Consumer Index"); 7036 } 7037 7038 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 7039 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 7040 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, 7041 OID_AUTO, namebuf, CTLFLAG_RD | CTLFLAG_MPSAFE, 7042 NULL, "freelist Name"); 7043 fl_list = SYSCTL_CHILDREN(fl_node); 7044 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 7045 CTLFLAG_RD, &fl->ifl_pidx, 1, "Producer Index"); 7046 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 7047 CTLFLAG_RD, &fl->ifl_cidx, 1, "Consumer Index"); 7048 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 7049 CTLFLAG_RD, &fl->ifl_credits, 1, 7050 "credits available"); 7051 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 7052 CTLFLAG_RD, &fl->ifl_buf_size, 1, "buffer size"); 7053 #if MEMORY_LOGGING 7054 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7055 "fl_m_enqueued", CTLFLAG_RD, &fl->ifl_m_enqueued, 7056 "mbufs allocated"); 7057 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7058 "fl_m_dequeued", CTLFLAG_RD, &fl->ifl_m_dequeued, 7059 "mbufs freed"); 7060 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7061 "fl_cl_enqueued", CTLFLAG_RD, &fl->ifl_cl_enqueued, 7062 "clusters allocated"); 7063 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO, 7064 "fl_cl_dequeued", CTLFLAG_RD, &fl->ifl_cl_dequeued, 7065 "clusters freed"); 7066 #endif 7067 } 7068 } 7069 7070 } 7071 7072 void 7073 iflib_request_reset(if_ctx_t ctx) 7074 { 7075 7076 STATE_LOCK(ctx); 7077 ctx->ifc_flags |= IFC_DO_RESET; 7078 STATE_UNLOCK(ctx); 7079 } 7080 7081 #ifndef __NO_STRICT_ALIGNMENT 7082 static struct mbuf * 7083 iflib_fixup_rx(struct mbuf *m) 7084 { 7085 struct mbuf *n; 7086 7087 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 7088 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 7089 m->m_data += ETHER_HDR_LEN; 7090 n = m; 7091 } else { 7092 MGETHDR(n, M_NOWAIT, MT_DATA); 7093 if (n == NULL) { 7094 m_freem(m); 7095 return (NULL); 7096 } 7097 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 7098 m->m_data += ETHER_HDR_LEN; 7099 m->m_len -= ETHER_HDR_LEN; 7100 n->m_len = ETHER_HDR_LEN; 7101 M_MOVE_PKTHDR(n, m); 7102 n->m_next = m; 7103 } 7104 return (n); 7105 } 7106 #endif 7107 7108 #ifdef DEBUGNET 7109 static void 7110 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 7111 { 7112 if_ctx_t ctx; 7113 7114 ctx = if_getsoftc(ifp); 7115 CTX_LOCK(ctx); 7116 *nrxr = NRXQSETS(ctx); 7117 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 7118 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 7119 CTX_UNLOCK(ctx); 7120 } 7121 7122 static void 7123 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 7124 { 7125 if_ctx_t ctx; 7126 if_softc_ctx_t scctx; 7127 iflib_fl_t fl; 7128 iflib_rxq_t rxq; 7129 int i, j; 7130 7131 ctx = if_getsoftc(ifp); 7132 scctx = &ctx->ifc_softc_ctx; 7133 7134 switch (event) { 7135 case DEBUGNET_START: 7136 for (i = 0; i < scctx->isc_nrxqsets; i++) { 7137 rxq = &ctx->ifc_rxqs[i]; 7138 for (j = 0; j < rxq->ifr_nfl; j++) { 7139 fl = rxq->ifr_fl; 7140 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 7141 } 7142 } 7143 iflib_no_tx_batch = 1; 7144 break; 7145 default: 7146 break; 7147 } 7148 } 7149 7150 static int 7151 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 7152 { 7153 if_ctx_t ctx; 7154 iflib_txq_t txq; 7155 int error; 7156 int bytes_sent = 0; 7157 int pkt_sent = 0; 7158 7159 ctx = if_getsoftc(ifp); 7160 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7161 IFF_DRV_RUNNING) 7162 return (EBUSY); 7163 7164 txq = &ctx->ifc_txqs[0]; 7165 error = iflib_encap(txq, &m, &bytes_sent, &pkt_sent); 7166 if (error == 0) 7167 (void)iflib_txd_db_check(txq, true); 7168 return (error); 7169 } 7170 7171 static int 7172 iflib_debugnet_poll(if_t ifp, int count) 7173 { 7174 struct epoch_tracker et; 7175 if_ctx_t ctx; 7176 if_softc_ctx_t scctx; 7177 iflib_txq_t txq; 7178 int i; 7179 7180 ctx = if_getsoftc(ifp); 7181 scctx = &ctx->ifc_softc_ctx; 7182 7183 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7184 IFF_DRV_RUNNING) 7185 return (EBUSY); 7186 7187 txq = &ctx->ifc_txqs[0]; 7188 (void)iflib_completed_tx_reclaim(txq, NULL); 7189 7190 NET_EPOCH_ENTER(et); 7191 for (i = 0; i < scctx->isc_nrxqsets; i++) 7192 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 7193 NET_EPOCH_EXIT(et); 7194 return (0); 7195 } 7196 #endif /* DEBUGNET */ 7197 7198 #ifndef ALTQ 7199 static inline iflib_txq_t 7200 iflib_simple_select_queue(if_ctx_t ctx, struct mbuf *m) 7201 { 7202 int qidx; 7203 7204 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 7205 qidx = QIDX(ctx, m); 7206 else 7207 qidx = NTXQSETS(ctx) + FIRST_QSET(ctx) - 1; 7208 return (&ctx->ifc_txqs[qidx]); 7209 } 7210 7211 static int 7212 iflib_simple_transmit(if_t ifp, struct mbuf *m) 7213 { 7214 if_ctx_t ctx; 7215 iflib_txq_t txq; 7216 struct mbuf **m_defer; 7217 int error, i, reclaimable; 7218 int bytes_sent = 0, pkt_sent = 0, mcast_sent = 0; 7219 7220 7221 ctx = if_getsoftc(ifp); 7222 if (__predict_false((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 7223 || !LINK_ACTIVE(ctx))) { 7224 DBG_COUNTER_INC(tx_frees); 7225 m_freem(m); 7226 return (ENETDOWN); 7227 } 7228 7229 txq = iflib_simple_select_queue(ctx, m); 7230 mtx_lock(&txq->ift_mtx); 7231 error = iflib_encap(txq, &m, &bytes_sent, &pkt_sent); 7232 if (error == 0) { 7233 mcast_sent += !!(m->m_flags & M_MCAST); 7234 (void)iflib_txd_db_check(txq, true); 7235 } else { 7236 if (error == ENOBUFS) 7237 if_inc_counter(ifp, IFCOUNTER_OQDROPS, 1); 7238 else 7239 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 7240 } 7241 m_defer = NULL; 7242 reclaimable = iflib_txq_can_reclaim(txq); 7243 if (reclaimable != 0) { 7244 /* 7245 * Try to set m_defer to the deferred mbuf reclaim array. If 7246 * we can, the frees will happen outside the tx lock. If we 7247 * can't, it means another thread is still proccessing frees. 7248 */ 7249 if (txq->ift_defer_mfree && 7250 atomic_cmpset_acq_ptr((uintptr_t *)&txq->ift_sds.ifsd_m_defer, 7251 (uintptr_t )txq->ift_sds.ifsd_m_deferb, 0)) { 7252 m_defer = txq->ift_sds.ifsd_m_deferb; 7253 } 7254 _iflib_completed_tx_reclaim(txq, m_defer, reclaimable); 7255 } 7256 mtx_unlock(&txq->ift_mtx); 7257 7258 /* 7259 * Process mbuf frees outside the tx lock 7260 */ 7261 if (m_defer != NULL) { 7262 for (i = 0; m_defer[i] != NULL; i++) { 7263 m_freem(m_defer[i]); 7264 m_defer[i] = NULL; 7265 } 7266 atomic_store_rel_ptr((uintptr_t *)&txq->ift_sds.ifsd_m_defer, 7267 (uintptr_t)m_defer); 7268 } 7269 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 7270 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 7271 if (mcast_sent) 7272 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 7273 7274 return (error); 7275 } 7276 #endif 7277