1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 /* 120 * File organization: 121 * - private structures 122 * - iflib private utility functions 123 * - ifnet functions 124 * - vlan registry and other exported functions 125 * - iflib public core functions 126 * 127 * 128 */ 129 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 130 131 #define IFLIB_RXEOF_MORE (1U << 0) 132 #define IFLIB_RXEOF_EMPTY (2U << 0) 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 146 typedef struct iflib_filter_info { 147 driver_filter_t *ifi_filter; 148 void *ifi_filter_arg; 149 struct grouptask *ifi_task; 150 void *ifi_ctx; 151 } *iflib_filter_info_t; 152 153 struct iflib_ctx { 154 KOBJ_FIELDS; 155 /* 156 * Pointer to hardware driver's softc 157 */ 158 void *ifc_softc; 159 device_t ifc_dev; 160 if_t ifc_ifp; 161 162 cpuset_t ifc_cpus; 163 if_shared_ctx_t ifc_sctx; 164 struct if_softc_ctx ifc_softc_ctx; 165 166 struct sx ifc_ctx_sx; 167 struct mtx ifc_state_mtx; 168 169 iflib_txq_t ifc_txqs; 170 iflib_rxq_t ifc_rxqs; 171 uint32_t ifc_if_flags; 172 uint32_t ifc_flags; 173 uint32_t ifc_max_fl_buf_size; 174 uint32_t ifc_rx_mbuf_sz; 175 176 int ifc_link_state; 177 int ifc_watchdog_events; 178 struct cdev *ifc_led_dev; 179 struct resource *ifc_msix_mem; 180 181 struct if_irq ifc_legacy_irq; 182 struct grouptask ifc_admin_task; 183 struct grouptask ifc_vflr_task; 184 struct iflib_filter_info ifc_filter_info; 185 struct ifmedia ifc_media; 186 struct ifmedia *ifc_mediap; 187 188 struct sysctl_oid *ifc_sysctl_node; 189 uint16_t ifc_sysctl_ntxqs; 190 uint16_t ifc_sysctl_nrxqs; 191 uint16_t ifc_sysctl_qs_eq_override; 192 uint16_t ifc_sysctl_rx_budget; 193 uint16_t ifc_sysctl_tx_abdicate; 194 uint16_t ifc_sysctl_core_offset; 195 #define CORE_OFFSET_UNSPECIFIED 0xffff 196 uint8_t ifc_sysctl_separate_txrx; 197 198 qidx_t ifc_sysctl_ntxds[8]; 199 qidx_t ifc_sysctl_nrxds[8]; 200 struct if_txrx ifc_txrx; 201 #define isc_txd_encap ifc_txrx.ift_txd_encap 202 #define isc_txd_flush ifc_txrx.ift_txd_flush 203 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 204 #define isc_rxd_available ifc_txrx.ift_rxd_available 205 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 207 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 209 eventhandler_tag ifc_vlan_attach_event; 210 eventhandler_tag ifc_vlan_detach_event; 211 struct ether_addr ifc_mac; 212 }; 213 214 void * 215 iflib_get_softc(if_ctx_t ctx) 216 { 217 218 return (ctx->ifc_softc); 219 } 220 221 device_t 222 iflib_get_dev(if_ctx_t ctx) 223 { 224 225 return (ctx->ifc_dev); 226 } 227 228 if_t 229 iflib_get_ifp(if_ctx_t ctx) 230 { 231 232 return (ctx->ifc_ifp); 233 } 234 235 struct ifmedia * 236 iflib_get_media(if_ctx_t ctx) 237 { 238 239 return (ctx->ifc_mediap); 240 } 241 242 uint32_t 243 iflib_get_flags(if_ctx_t ctx) 244 { 245 return (ctx->ifc_flags); 246 } 247 248 void 249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 250 { 251 252 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 253 } 254 255 if_softc_ctx_t 256 iflib_get_softc_ctx(if_ctx_t ctx) 257 { 258 259 return (&ctx->ifc_softc_ctx); 260 } 261 262 if_shared_ctx_t 263 iflib_get_sctx(if_ctx_t ctx) 264 { 265 266 return (ctx->ifc_sctx); 267 } 268 269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 272 273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 275 276 typedef struct iflib_sw_rx_desc_array { 277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 278 struct mbuf **ifsd_m; /* pkthdr mbufs */ 279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 281 } iflib_rxsd_array_t; 282 283 typedef struct iflib_sw_tx_desc_array { 284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 286 struct mbuf **ifsd_m; /* pkthdr mbufs */ 287 } if_txsd_vec_t; 288 289 /* magic number that should be high enough for any hardware */ 290 #define IFLIB_MAX_TX_SEGS 128 291 #define IFLIB_RX_COPY_THRESH 128 292 #define IFLIB_MAX_RX_REFRESH 32 293 /* The minimum descriptors per second before we start coalescing */ 294 #define IFLIB_MIN_DESC_SEC 16384 295 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 296 #define IFLIB_QUEUE_IDLE 0 297 #define IFLIB_QUEUE_HUNG 1 298 #define IFLIB_QUEUE_WORKING 2 299 /* maximum number of txqs that can share an rx interrupt */ 300 #define IFLIB_MAX_TX_SHARED_INTR 4 301 302 /* this should really scale with ring size - this is a fairly arbitrary value */ 303 #define TX_BATCH_SIZE 32 304 305 #define IFLIB_RESTART_BUDGET 8 306 307 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 308 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 309 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 310 311 struct iflib_txq { 312 qidx_t ift_in_use; 313 qidx_t ift_cidx; 314 qidx_t ift_cidx_processed; 315 qidx_t ift_pidx; 316 uint8_t ift_gen; 317 uint8_t ift_br_offset; 318 uint16_t ift_npending; 319 uint16_t ift_db_pending; 320 uint16_t ift_rs_pending; 321 /* implicit pad */ 322 uint8_t ift_txd_size[8]; 323 uint64_t ift_processed; 324 uint64_t ift_cleaned; 325 uint64_t ift_cleaned_prev; 326 #if MEMORY_LOGGING 327 uint64_t ift_enqueued; 328 uint64_t ift_dequeued; 329 #endif 330 uint64_t ift_no_tx_dma_setup; 331 uint64_t ift_no_desc_avail; 332 uint64_t ift_mbuf_defrag_failed; 333 uint64_t ift_mbuf_defrag; 334 uint64_t ift_map_failed; 335 uint64_t ift_txd_encap_efbig; 336 uint64_t ift_pullups; 337 uint64_t ift_last_timer_tick; 338 339 struct mtx ift_mtx; 340 struct mtx ift_db_mtx; 341 342 /* constant values */ 343 if_ctx_t ift_ctx; 344 struct ifmp_ring *ift_br; 345 struct grouptask ift_task; 346 qidx_t ift_size; 347 uint16_t ift_id; 348 struct callout ift_timer; 349 350 if_txsd_vec_t ift_sds; 351 uint8_t ift_qstatus; 352 uint8_t ift_closed; 353 uint8_t ift_update_freq; 354 struct iflib_filter_info ift_filter_info; 355 bus_dma_tag_t ift_buf_tag; 356 bus_dma_tag_t ift_tso_buf_tag; 357 iflib_dma_info_t ift_ifdi; 358 #define MTX_NAME_LEN 32 359 char ift_mtx_name[MTX_NAME_LEN]; 360 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 361 #ifdef IFLIB_DIAGNOSTICS 362 uint64_t ift_cpu_exec_count[256]; 363 #endif 364 } __aligned(CACHE_LINE_SIZE); 365 366 struct iflib_fl { 367 qidx_t ifl_cidx; 368 qidx_t ifl_pidx; 369 qidx_t ifl_credits; 370 uint8_t ifl_gen; 371 uint8_t ifl_rxd_size; 372 #if MEMORY_LOGGING 373 uint64_t ifl_m_enqueued; 374 uint64_t ifl_m_dequeued; 375 uint64_t ifl_cl_enqueued; 376 uint64_t ifl_cl_dequeued; 377 #endif 378 /* implicit pad */ 379 bitstr_t *ifl_rx_bitmap; 380 qidx_t ifl_fragidx; 381 /* constant */ 382 qidx_t ifl_size; 383 uint16_t ifl_buf_size; 384 uint16_t ifl_cltype; 385 uma_zone_t ifl_zone; 386 iflib_rxsd_array_t ifl_sds; 387 iflib_rxq_t ifl_rxq; 388 uint8_t ifl_id; 389 bus_dma_tag_t ifl_buf_tag; 390 iflib_dma_info_t ifl_ifdi; 391 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 392 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 393 } __aligned(CACHE_LINE_SIZE); 394 395 static inline qidx_t 396 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 397 { 398 qidx_t used; 399 400 if (pidx > cidx) 401 used = pidx - cidx; 402 else if (pidx < cidx) 403 used = size - cidx + pidx; 404 else if (gen == 0 && pidx == cidx) 405 used = 0; 406 else if (gen == 1 && pidx == cidx) 407 used = size; 408 else 409 panic("bad state"); 410 411 return (used); 412 } 413 414 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 415 416 #define IDXDIFF(head, tail, wrap) \ 417 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 418 419 struct iflib_rxq { 420 if_ctx_t ifr_ctx; 421 iflib_fl_t ifr_fl; 422 uint64_t ifr_rx_irq; 423 struct pfil_head *pfil; 424 /* 425 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 426 * the completion queue consumer index. Otherwise it's unused. 427 */ 428 qidx_t ifr_cq_cidx; 429 uint16_t ifr_id; 430 uint8_t ifr_nfl; 431 uint8_t ifr_ntxqirq; 432 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 433 uint8_t ifr_fl_offset; 434 struct lro_ctrl ifr_lc; 435 struct grouptask ifr_task; 436 struct callout ifr_watchdog; 437 struct iflib_filter_info ifr_filter_info; 438 iflib_dma_info_t ifr_ifdi; 439 440 /* dynamically allocate if any drivers need a value substantially larger than this */ 441 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 442 #ifdef IFLIB_DIAGNOSTICS 443 uint64_t ifr_cpu_exec_count[256]; 444 #endif 445 } __aligned(CACHE_LINE_SIZE); 446 447 typedef struct if_rxsd { 448 caddr_t *ifsd_cl; 449 iflib_fl_t ifsd_fl; 450 } *if_rxsd_t; 451 452 /* multiple of word size */ 453 #ifdef __LP64__ 454 #define PKT_INFO_SIZE 6 455 #define RXD_INFO_SIZE 5 456 #define PKT_TYPE uint64_t 457 #else 458 #define PKT_INFO_SIZE 11 459 #define RXD_INFO_SIZE 8 460 #define PKT_TYPE uint32_t 461 #endif 462 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 463 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 464 465 typedef struct if_pkt_info_pad { 466 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 467 } *if_pkt_info_pad_t; 468 typedef struct if_rxd_info_pad { 469 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 470 } *if_rxd_info_pad_t; 471 472 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 473 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 474 475 static inline void 476 pkt_info_zero(if_pkt_info_t pi) 477 { 478 if_pkt_info_pad_t pi_pad; 479 480 pi_pad = (if_pkt_info_pad_t)pi; 481 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 482 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 483 #ifndef __LP64__ 484 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 485 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 486 #endif 487 } 488 489 static device_method_t iflib_pseudo_methods[] = { 490 DEVMETHOD(device_attach, noop_attach), 491 DEVMETHOD(device_detach, iflib_pseudo_detach), 492 DEVMETHOD_END 493 }; 494 495 driver_t iflib_pseudodriver = { 496 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 497 }; 498 499 static inline void 500 rxd_info_zero(if_rxd_info_t ri) 501 { 502 if_rxd_info_pad_t ri_pad; 503 int i; 504 505 ri_pad = (if_rxd_info_pad_t)ri; 506 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 507 ri_pad->rxd_val[i] = 0; 508 ri_pad->rxd_val[i+1] = 0; 509 ri_pad->rxd_val[i+2] = 0; 510 ri_pad->rxd_val[i+3] = 0; 511 } 512 #ifdef __LP64__ 513 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 514 #endif 515 } 516 517 /* 518 * Only allow a single packet to take up most 1/nth of the tx ring 519 */ 520 #define MAX_SINGLE_PACKET_FRACTION 12 521 #define IF_BAD_DMA (bus_addr_t)-1 522 523 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 524 525 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 526 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 527 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 528 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 529 530 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 531 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 532 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 533 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 534 535 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 536 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 537 538 void 539 iflib_set_detach(if_ctx_t ctx) 540 { 541 STATE_LOCK(ctx); 542 ctx->ifc_flags |= IFC_IN_DETACH; 543 STATE_UNLOCK(ctx); 544 } 545 546 /* Our boot-time initialization hook */ 547 static int iflib_module_event_handler(module_t, int, void *); 548 549 static moduledata_t iflib_moduledata = { 550 "iflib", 551 iflib_module_event_handler, 552 NULL 553 }; 554 555 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 556 MODULE_VERSION(iflib, 1); 557 558 MODULE_DEPEND(iflib, pci, 1, 1, 1); 559 MODULE_DEPEND(iflib, ether, 1, 1, 1); 560 561 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 562 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 563 564 #ifndef IFLIB_DEBUG_COUNTERS 565 #ifdef INVARIANTS 566 #define IFLIB_DEBUG_COUNTERS 1 567 #else 568 #define IFLIB_DEBUG_COUNTERS 0 569 #endif /* !INVARIANTS */ 570 #endif 571 572 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 573 "iflib driver parameters"); 574 575 /* 576 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 577 */ 578 static int iflib_min_tx_latency = 0; 579 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 580 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 581 static int iflib_no_tx_batch = 0; 582 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 583 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 584 585 #if IFLIB_DEBUG_COUNTERS 586 587 static int iflib_tx_seen; 588 static int iflib_tx_sent; 589 static int iflib_tx_encap; 590 static int iflib_rx_allocs; 591 static int iflib_fl_refills; 592 static int iflib_fl_refills_large; 593 static int iflib_tx_frees; 594 595 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 596 &iflib_tx_seen, 0, "# TX mbufs seen"); 597 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 598 &iflib_tx_sent, 0, "# TX mbufs sent"); 599 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 600 &iflib_tx_encap, 0, "# TX mbufs encapped"); 601 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 602 &iflib_tx_frees, 0, "# TX frees"); 603 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 604 &iflib_rx_allocs, 0, "# RX allocations"); 605 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 606 &iflib_fl_refills, 0, "# refills"); 607 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 608 &iflib_fl_refills_large, 0, "# large refills"); 609 610 static int iflib_txq_drain_flushing; 611 static int iflib_txq_drain_oactive; 612 static int iflib_txq_drain_notready; 613 614 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 615 &iflib_txq_drain_flushing, 0, "# drain flushes"); 616 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 617 &iflib_txq_drain_oactive, 0, "# drain oactives"); 618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 619 &iflib_txq_drain_notready, 0, "# drain notready"); 620 621 static int iflib_encap_load_mbuf_fail; 622 static int iflib_encap_pad_mbuf_fail; 623 static int iflib_encap_txq_avail_fail; 624 static int iflib_encap_txd_encap_fail; 625 626 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 627 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 628 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 629 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 630 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 631 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 632 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 633 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 634 635 static int iflib_task_fn_rxs; 636 static int iflib_rx_intr_enables; 637 static int iflib_fast_intrs; 638 static int iflib_rx_unavail; 639 static int iflib_rx_ctx_inactive; 640 static int iflib_rx_if_input; 641 static int iflib_rxd_flush; 642 643 static int iflib_verbose_debug; 644 645 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 646 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 647 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 648 &iflib_rx_intr_enables, 0, "# RX intr enables"); 649 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 650 &iflib_fast_intrs, 0, "# fast_intr calls"); 651 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 652 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 653 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 654 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 655 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 656 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 657 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 658 &iflib_rxd_flush, 0, "# times rxd_flush called"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 660 &iflib_verbose_debug, 0, "enable verbose debugging"); 661 662 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 663 static void 664 iflib_debug_reset(void) 665 { 666 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 667 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 668 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 669 iflib_txq_drain_notready = 670 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 671 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 672 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 673 iflib_rx_unavail = 674 iflib_rx_ctx_inactive = iflib_rx_if_input = 675 iflib_rxd_flush = 0; 676 } 677 678 #else 679 #define DBG_COUNTER_INC(name) 680 static void iflib_debug_reset(void) {} 681 #endif 682 683 #define IFLIB_DEBUG 0 684 685 static void iflib_tx_structures_free(if_ctx_t ctx); 686 static void iflib_rx_structures_free(if_ctx_t ctx); 687 static int iflib_queues_alloc(if_ctx_t ctx); 688 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 689 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 690 static int iflib_qset_structures_setup(if_ctx_t ctx); 691 static int iflib_msix_init(if_ctx_t ctx); 692 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 693 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 694 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 695 #ifdef ALTQ 696 static void iflib_altq_if_start(if_t ifp); 697 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 698 #endif 699 static int iflib_register(if_ctx_t); 700 static void iflib_deregister(if_ctx_t); 701 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 702 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 703 static void iflib_init_locked(if_ctx_t ctx); 704 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 705 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 706 static void iflib_ifmp_purge(iflib_txq_t txq); 707 static void _iflib_pre_assert(if_softc_ctx_t scctx); 708 static void iflib_if_init_locked(if_ctx_t ctx); 709 static void iflib_free_intr_mem(if_ctx_t ctx); 710 #ifndef __NO_STRICT_ALIGNMENT 711 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 712 #endif 713 714 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 715 SLIST_HEAD_INITIALIZER(cpu_offsets); 716 struct cpu_offset { 717 SLIST_ENTRY(cpu_offset) entries; 718 cpuset_t set; 719 unsigned int refcount; 720 uint16_t offset; 721 }; 722 static struct mtx cpu_offset_mtx; 723 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 724 MTX_DEF); 725 726 DEBUGNET_DEFINE(iflib); 727 728 static int 729 iflib_num_rx_descs(if_ctx_t ctx) 730 { 731 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 732 if_shared_ctx_t sctx = ctx->ifc_sctx; 733 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 734 735 return scctx->isc_nrxd[first_rxq]; 736 } 737 738 static int 739 iflib_num_tx_descs(if_ctx_t ctx) 740 { 741 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 742 if_shared_ctx_t sctx = ctx->ifc_sctx; 743 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 744 745 return scctx->isc_ntxd[first_txq]; 746 } 747 748 #ifdef DEV_NETMAP 749 #include <sys/selinfo.h> 750 #include <net/netmap.h> 751 #include <dev/netmap/netmap_kern.h> 752 753 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 754 755 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 756 757 /* 758 * device-specific sysctl variables: 759 * 760 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 761 * During regular operations the CRC is stripped, but on some 762 * hardware reception of frames not multiple of 64 is slower, 763 * so using crcstrip=0 helps in benchmarks. 764 * 765 * iflib_rx_miss, iflib_rx_miss_bufs: 766 * count packets that might be missed due to lost interrupts. 767 */ 768 SYSCTL_DECL(_dev_netmap); 769 /* 770 * The xl driver by default strips CRCs and we do not override it. 771 */ 772 773 int iflib_crcstrip = 1; 774 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 775 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 776 777 int iflib_rx_miss, iflib_rx_miss_bufs; 778 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 779 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 780 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 781 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 782 783 /* 784 * Register/unregister. We are already under netmap lock. 785 * Only called on the first register or the last unregister. 786 */ 787 static int 788 iflib_netmap_register(struct netmap_adapter *na, int onoff) 789 { 790 if_t ifp = na->ifp; 791 if_ctx_t ctx = ifp->if_softc; 792 int status; 793 794 CTX_LOCK(ctx); 795 IFDI_INTR_DISABLE(ctx); 796 797 /* Tell the stack that the interface is no longer active */ 798 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 799 800 if (!CTX_IS_VF(ctx)) 801 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 802 803 iflib_stop(ctx); 804 805 /* 806 * Enable (or disable) netmap flags, and intercept (or restore) 807 * ifp->if_transmit. This is done once the device has been stopped 808 * to prevent race conditions. 809 */ 810 if (onoff) { 811 nm_set_native_flags(na); 812 } else { 813 nm_clear_native_flags(na); 814 } 815 816 iflib_init_locked(ctx); 817 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 818 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 819 if (status) 820 nm_clear_native_flags(na); 821 CTX_UNLOCK(ctx); 822 return (status); 823 } 824 825 static int 826 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 827 { 828 struct netmap_adapter *na = kring->na; 829 u_int const lim = kring->nkr_num_slots - 1; 830 u_int nm_i = kring->nr_hwcur; 831 struct netmap_ring *ring = kring->ring; 832 bus_dmamap_t *map; 833 struct if_rxd_update iru; 834 if_ctx_t ctx = rxq->ifr_ctx; 835 iflib_fl_t fl = &rxq->ifr_fl[0]; 836 u_int nic_i_first, nic_i; 837 int i, n; 838 #if IFLIB_DEBUG_COUNTERS 839 int rf_count = 0; 840 #endif 841 842 /* 843 * This function is used both at initialization and in rxsync. 844 * At initialization we need to prepare (with isc_rxd_refill()) 845 * all the (N) netmap buffers in the ring, in such a way to keep 846 * fl->ifl_pidx and kring->nr_hwcur in sync (except for 847 * kring->nkr_hwofs); at rxsync time, both indexes point to the 848 * next buffer to be refilled. 849 * In any case we publish (with isc_rxd_flush()) up to 850 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 851 * pointer to overrun the head/cons pointer, although this is 852 * not necessary for some NICs (e.g. vmx). 853 */ 854 if (__predict_false(init)) 855 n = kring->nkr_num_slots; 856 else { 857 n = kring->rhead - nm_i; 858 if (n == 0) 859 return (0); /* Nothing to do. */ 860 if (n < 0) 861 n += kring->nkr_num_slots; 862 } 863 864 /* Start to refill from nr_hwcur, publishing n buffers. */ 865 iru_init(&iru, rxq, 0 /* flid */); 866 map = fl->ifl_sds.ifsd_map; 867 nic_i = fl->ifl_pidx; 868 MPASS(nic_i == netmap_idx_k2n(kring, nm_i)); 869 DBG_COUNTER_INC(fl_refills); 870 while (n > 0) { 871 #if IFLIB_DEBUG_COUNTERS 872 if (++rf_count == 9) 873 DBG_COUNTER_INC(fl_refills_large); 874 #endif 875 nic_i_first = nic_i; 876 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 877 struct netmap_slot *slot = &ring->slot[nm_i]; 878 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]); 879 880 MPASS(i < IFLIB_MAX_RX_REFRESH); 881 882 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 883 return netmap_ring_reinit(kring); 884 885 fl->ifl_rxd_idxs[i] = nic_i; 886 887 if (__predict_false(init)) { 888 netmap_load_map(na, fl->ifl_buf_tag, 889 map[nic_i], addr); 890 } else if (slot->flags & NS_BUF_CHANGED) { 891 /* buffer has changed, reload map */ 892 netmap_reload_map(na, fl->ifl_buf_tag, 893 map[nic_i], addr); 894 } 895 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 896 BUS_DMASYNC_PREREAD); 897 slot->flags &= ~NS_BUF_CHANGED; 898 899 nm_i = nm_next(nm_i, lim); 900 nic_i = nm_next(nic_i, lim); 901 } 902 903 iru.iru_pidx = nic_i_first; 904 iru.iru_count = i; 905 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 906 } 907 fl->ifl_pidx = nic_i; 908 MPASS(!init || nm_i == 0); 909 MPASS(nm_i == kring->rhead); 910 kring->nr_hwcur = nm_i; 911 912 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 913 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 914 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 915 nm_prev(nic_i, lim)); 916 DBG_COUNTER_INC(rxd_flush); 917 918 return (0); 919 } 920 921 /* 922 * Reconcile kernel and user view of the transmit ring. 923 * 924 * All information is in the kring. 925 * Userspace wants to send packets up to the one before kring->rhead, 926 * kernel knows kring->nr_hwcur is the first unsent packet. 927 * 928 * Here we push packets out (as many as possible), and possibly 929 * reclaim buffers from previously completed transmission. 930 * 931 * The caller (netmap) guarantees that there is only one instance 932 * running at any time. Any interference with other driver 933 * methods should be handled by the individual drivers. 934 */ 935 static int 936 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 937 { 938 struct netmap_adapter *na = kring->na; 939 if_t ifp = na->ifp; 940 struct netmap_ring *ring = kring->ring; 941 u_int nm_i; /* index into the netmap kring */ 942 u_int nic_i; /* index into the NIC ring */ 943 u_int n; 944 u_int const lim = kring->nkr_num_slots - 1; 945 u_int const head = kring->rhead; 946 struct if_pkt_info pi; 947 948 /* 949 * interrupts on every tx packet are expensive so request 950 * them every half ring, or where NS_REPORT is set 951 */ 952 u_int report_frequency = kring->nkr_num_slots >> 1; 953 /* device-specific */ 954 if_ctx_t ctx = ifp->if_softc; 955 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 956 957 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 958 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 959 960 /* 961 * First part: process new packets to send. 962 * nm_i is the current index in the netmap kring, 963 * nic_i is the corresponding index in the NIC ring. 964 * 965 * If we have packets to send (nm_i != head) 966 * iterate over the netmap ring, fetch length and update 967 * the corresponding slot in the NIC ring. Some drivers also 968 * need to update the buffer's physical address in the NIC slot 969 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 970 * 971 * The netmap_reload_map() calls is especially expensive, 972 * even when (as in this case) the tag is 0, so do only 973 * when the buffer has actually changed. 974 * 975 * If possible do not set the report/intr bit on all slots, 976 * but only a few times per ring or when NS_REPORT is set. 977 * 978 * Finally, on 10G and faster drivers, it might be useful 979 * to prefetch the next slot and txr entry. 980 */ 981 982 nm_i = kring->nr_hwcur; 983 if (nm_i != head) { /* we have new packets to send */ 984 pkt_info_zero(&pi); 985 pi.ipi_segs = txq->ift_segs; 986 pi.ipi_qsidx = kring->ring_id; 987 nic_i = netmap_idx_k2n(kring, nm_i); 988 989 __builtin_prefetch(&ring->slot[nm_i]); 990 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 991 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 992 993 for (n = 0; nm_i != head; n++) { 994 struct netmap_slot *slot = &ring->slot[nm_i]; 995 u_int len = slot->len; 996 uint64_t paddr; 997 void *addr = PNMB(na, slot, &paddr); 998 int flags = (slot->flags & NS_REPORT || 999 nic_i == 0 || nic_i == report_frequency) ? 1000 IPI_TX_INTR : 0; 1001 1002 /* device-specific */ 1003 pi.ipi_len = len; 1004 pi.ipi_segs[0].ds_addr = paddr; 1005 pi.ipi_segs[0].ds_len = len; 1006 pi.ipi_nsegs = 1; 1007 pi.ipi_ndescs = 0; 1008 pi.ipi_pidx = nic_i; 1009 pi.ipi_flags = flags; 1010 1011 /* Fill the slot in the NIC ring. */ 1012 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1013 DBG_COUNTER_INC(tx_encap); 1014 1015 /* prefetch for next round */ 1016 __builtin_prefetch(&ring->slot[nm_i + 1]); 1017 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1018 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1019 1020 NM_CHECK_ADDR_LEN(na, addr, len); 1021 1022 if (slot->flags & NS_BUF_CHANGED) { 1023 /* buffer has changed, reload map */ 1024 netmap_reload_map(na, txq->ift_buf_tag, 1025 txq->ift_sds.ifsd_map[nic_i], addr); 1026 } 1027 /* make sure changes to the buffer are synced */ 1028 bus_dmamap_sync(txq->ift_buf_tag, 1029 txq->ift_sds.ifsd_map[nic_i], 1030 BUS_DMASYNC_PREWRITE); 1031 1032 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1033 nm_i = nm_next(nm_i, lim); 1034 nic_i = nm_next(nic_i, lim); 1035 } 1036 kring->nr_hwcur = nm_i; 1037 1038 /* synchronize the NIC ring */ 1039 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1040 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1041 1042 /* (re)start the tx unit up to slot nic_i (excluded) */ 1043 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1044 } 1045 1046 /* 1047 * Second part: reclaim buffers for completed transmissions. 1048 * 1049 * If there are unclaimed buffers, attempt to reclaim them. 1050 * If none are reclaimed, and TX IRQs are not in use, do an initial 1051 * minimal delay, then trigger the tx handler which will spin in the 1052 * group task queue. 1053 */ 1054 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1055 if (iflib_tx_credits_update(ctx, txq)) { 1056 /* some tx completed, increment avail */ 1057 nic_i = txq->ift_cidx_processed; 1058 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1059 } 1060 } 1061 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1062 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1063 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1064 iflib_timer, txq, txq->ift_timer.c_cpu); 1065 } 1066 return (0); 1067 } 1068 1069 /* 1070 * Reconcile kernel and user view of the receive ring. 1071 * Same as for the txsync, this routine must be efficient. 1072 * The caller guarantees a single invocations, but races against 1073 * the rest of the driver should be handled here. 1074 * 1075 * On call, kring->rhead is the first packet that userspace wants 1076 * to keep, and kring->rcur is the wakeup point. 1077 * The kernel has previously reported packets up to kring->rtail. 1078 * 1079 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1080 * of whether or not we received an interrupt. 1081 */ 1082 static int 1083 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1084 { 1085 struct netmap_adapter *na = kring->na; 1086 struct netmap_ring *ring = kring->ring; 1087 if_t ifp = na->ifp; 1088 uint32_t nm_i; /* index into the netmap ring */ 1089 uint32_t nic_i; /* index into the NIC ring */ 1090 u_int n; 1091 u_int const lim = kring->nkr_num_slots - 1; 1092 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1093 1094 if_ctx_t ctx = ifp->if_softc; 1095 if_shared_ctx_t sctx = ctx->ifc_sctx; 1096 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1097 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1098 iflib_fl_t fl = &rxq->ifr_fl[0]; 1099 struct if_rxd_info ri; 1100 qidx_t *cidxp; 1101 1102 /* 1103 * netmap only uses free list 0, to avoid out of order consumption 1104 * of receive buffers 1105 */ 1106 1107 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1108 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1109 1110 /* 1111 * First part: import newly received packets. 1112 * 1113 * nm_i is the index of the next free slot in the netmap ring, 1114 * nic_i is the index of the next received packet in the NIC ring 1115 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1116 * differ in case if_init() has been called while 1117 * in netmap mode. For the receive ring we have 1118 * 1119 * nic_i = fl->ifl_cidx; 1120 * nm_i = kring->nr_hwtail (previous) 1121 * and 1122 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1123 * 1124 * fl->ifl_cidx is set to 0 on a ring reinit 1125 */ 1126 if (netmap_no_pendintr || force_update) { 1127 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1128 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1129 int crclen = iflib_crcstrip ? 0 : 4; 1130 int error, avail; 1131 1132 /* 1133 * For the free list consumer index, we use the same 1134 * logic as in iflib_rxeof(). 1135 */ 1136 if (have_rxcq) 1137 cidxp = &rxq->ifr_cq_cidx; 1138 else 1139 cidxp = &fl->ifl_cidx; 1140 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1141 rxq->ifr_id, *cidxp, USHRT_MAX); 1142 1143 nic_i = fl->ifl_cidx; 1144 nm_i = netmap_idx_n2k(kring, nic_i); 1145 MPASS(nm_i == kring->nr_hwtail); 1146 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1147 rxd_info_zero(&ri); 1148 ri.iri_frags = rxq->ifr_frags; 1149 ri.iri_qsidx = kring->ring_id; 1150 ri.iri_ifp = ctx->ifc_ifp; 1151 ri.iri_cidx = *cidxp; 1152 1153 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1154 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1155 ring->slot[nm_i].flags = 0; 1156 if (have_rxcq) { 1157 *cidxp = ri.iri_cidx; 1158 while (*cidxp >= scctx->isc_nrxd[0]) 1159 *cidxp -= scctx->isc_nrxd[0]; 1160 } 1161 bus_dmamap_sync(fl->ifl_buf_tag, 1162 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1163 nm_i = nm_next(nm_i, lim); 1164 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1165 } 1166 if (n) { /* update the state variables */ 1167 if (netmap_no_pendintr && !force_update) { 1168 /* diagnostics */ 1169 iflib_rx_miss ++; 1170 iflib_rx_miss_bufs += n; 1171 } 1172 kring->nr_hwtail = nm_i; 1173 } 1174 kring->nr_kflags &= ~NKR_PENDINTR; 1175 } 1176 /* 1177 * Second part: skip past packets that userspace has released. 1178 * (kring->nr_hwcur to head excluded), 1179 * and make the buffers available for reception. 1180 * As usual nm_i is the index in the netmap ring, 1181 * nic_i is the index in the NIC ring, and 1182 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1183 */ 1184 netmap_fl_refill(rxq, kring, false); 1185 1186 return (0); 1187 } 1188 1189 static void 1190 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1191 { 1192 if_ctx_t ctx = na->ifp->if_softc; 1193 1194 CTX_LOCK(ctx); 1195 if (onoff) { 1196 IFDI_INTR_ENABLE(ctx); 1197 } else { 1198 IFDI_INTR_DISABLE(ctx); 1199 } 1200 CTX_UNLOCK(ctx); 1201 } 1202 1203 static int 1204 iflib_netmap_attach(if_ctx_t ctx) 1205 { 1206 struct netmap_adapter na; 1207 1208 bzero(&na, sizeof(na)); 1209 1210 na.ifp = ctx->ifc_ifp; 1211 na.na_flags = NAF_BDG_MAYSLEEP; 1212 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1213 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1214 1215 na.num_tx_desc = iflib_num_tx_descs(ctx); 1216 na.num_rx_desc = iflib_num_rx_descs(ctx); 1217 na.nm_txsync = iflib_netmap_txsync; 1218 na.nm_rxsync = iflib_netmap_rxsync; 1219 na.nm_register = iflib_netmap_register; 1220 na.nm_intr = iflib_netmap_intr; 1221 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1222 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1223 return (netmap_attach(&na)); 1224 } 1225 1226 static int 1227 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1228 { 1229 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1230 struct netmap_slot *slot; 1231 1232 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1233 if (slot == NULL) 1234 return (0); 1235 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1236 /* 1237 * In netmap mode, set the map for the packet buffer. 1238 * NOTE: Some drivers (not this one) also need to set 1239 * the physical buffer address in the NIC ring. 1240 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1241 * netmap slot index, si 1242 */ 1243 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1244 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1245 NMB(na, slot + si)); 1246 } 1247 return (1); 1248 } 1249 1250 static int 1251 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1252 { 1253 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1254 struct netmap_kring *kring; 1255 struct netmap_slot *slot; 1256 1257 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1258 if (slot == NULL) 1259 return (0); 1260 kring = na->rx_rings[rxq->ifr_id]; 1261 netmap_fl_refill(rxq, kring, true); 1262 return (1); 1263 } 1264 1265 static void 1266 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on) 1267 { 1268 struct netmap_kring *kring; 1269 uint16_t txqid; 1270 1271 txqid = txq->ift_id; 1272 kring = netmap_kring_on(NA(ctx->ifc_ifp), txqid, NR_TX); 1273 if (kring == NULL) 1274 return; 1275 1276 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1277 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1278 BUS_DMASYNC_POSTREAD); 1279 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1280 netmap_tx_irq(ctx->ifc_ifp, txqid); 1281 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1282 if (hz < 2000) 1283 *reset_on = 1; 1284 else 1285 *reset_on = hz / 1000; 1286 } 1287 } 1288 } 1289 1290 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1291 1292 #else 1293 #define iflib_netmap_txq_init(ctx, txq) (0) 1294 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1295 #define iflib_netmap_detach(ifp) 1296 1297 #define iflib_netmap_attach(ctx) (0) 1298 #define netmap_rx_irq(ifp, qid, budget) (0) 1299 #define netmap_tx_irq(ifp, qid) do {} while (0) 1300 #define iflib_netmap_timer_adjust(ctx, txq, reset_on) 1301 #endif 1302 1303 #if defined(__i386__) || defined(__amd64__) 1304 static __inline void 1305 prefetch(void *x) 1306 { 1307 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1308 } 1309 static __inline void 1310 prefetch2cachelines(void *x) 1311 { 1312 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1313 #if (CACHE_LINE_SIZE < 128) 1314 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1315 #endif 1316 } 1317 #else 1318 #define prefetch(x) 1319 #define prefetch2cachelines(x) 1320 #endif 1321 1322 static void 1323 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1324 { 1325 iflib_fl_t fl; 1326 1327 fl = &rxq->ifr_fl[flid]; 1328 iru->iru_paddrs = fl->ifl_bus_addrs; 1329 iru->iru_idxs = fl->ifl_rxd_idxs; 1330 iru->iru_qsidx = rxq->ifr_id; 1331 iru->iru_buf_size = fl->ifl_buf_size; 1332 iru->iru_flidx = fl->ifl_id; 1333 } 1334 1335 static void 1336 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1337 { 1338 if (err) 1339 return; 1340 *(bus_addr_t *) arg = segs[0].ds_addr; 1341 } 1342 1343 int 1344 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1345 { 1346 int err; 1347 device_t dev = ctx->ifc_dev; 1348 1349 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1350 align, 0, /* alignment, bounds */ 1351 BUS_SPACE_MAXADDR, /* lowaddr */ 1352 BUS_SPACE_MAXADDR, /* highaddr */ 1353 NULL, NULL, /* filter, filterarg */ 1354 size, /* maxsize */ 1355 1, /* nsegments */ 1356 size, /* maxsegsize */ 1357 BUS_DMA_ALLOCNOW, /* flags */ 1358 NULL, /* lockfunc */ 1359 NULL, /* lockarg */ 1360 &dma->idi_tag); 1361 if (err) { 1362 device_printf(dev, 1363 "%s: bus_dma_tag_create failed: %d\n", 1364 __func__, err); 1365 goto fail_0; 1366 } 1367 1368 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1369 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1370 if (err) { 1371 device_printf(dev, 1372 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1373 __func__, (uintmax_t)size, err); 1374 goto fail_1; 1375 } 1376 1377 dma->idi_paddr = IF_BAD_DMA; 1378 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1379 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1380 if (err || dma->idi_paddr == IF_BAD_DMA) { 1381 device_printf(dev, 1382 "%s: bus_dmamap_load failed: %d\n", 1383 __func__, err); 1384 goto fail_2; 1385 } 1386 1387 dma->idi_size = size; 1388 return (0); 1389 1390 fail_2: 1391 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1392 fail_1: 1393 bus_dma_tag_destroy(dma->idi_tag); 1394 fail_0: 1395 dma->idi_tag = NULL; 1396 1397 return (err); 1398 } 1399 1400 int 1401 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1402 { 1403 if_shared_ctx_t sctx = ctx->ifc_sctx; 1404 1405 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1406 1407 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1408 } 1409 1410 int 1411 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1412 { 1413 int i, err; 1414 iflib_dma_info_t *dmaiter; 1415 1416 dmaiter = dmalist; 1417 for (i = 0; i < count; i++, dmaiter++) { 1418 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1419 break; 1420 } 1421 if (err) 1422 iflib_dma_free_multi(dmalist, i); 1423 return (err); 1424 } 1425 1426 void 1427 iflib_dma_free(iflib_dma_info_t dma) 1428 { 1429 if (dma->idi_tag == NULL) 1430 return; 1431 if (dma->idi_paddr != IF_BAD_DMA) { 1432 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1433 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1434 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1435 dma->idi_paddr = IF_BAD_DMA; 1436 } 1437 if (dma->idi_vaddr != NULL) { 1438 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1439 dma->idi_vaddr = NULL; 1440 } 1441 bus_dma_tag_destroy(dma->idi_tag); 1442 dma->idi_tag = NULL; 1443 } 1444 1445 void 1446 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1447 { 1448 int i; 1449 iflib_dma_info_t *dmaiter = dmalist; 1450 1451 for (i = 0; i < count; i++, dmaiter++) 1452 iflib_dma_free(*dmaiter); 1453 } 1454 1455 static int 1456 iflib_fast_intr(void *arg) 1457 { 1458 iflib_filter_info_t info = arg; 1459 struct grouptask *gtask = info->ifi_task; 1460 int result; 1461 1462 DBG_COUNTER_INC(fast_intrs); 1463 if (info->ifi_filter != NULL) { 1464 result = info->ifi_filter(info->ifi_filter_arg); 1465 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1466 return (result); 1467 } 1468 1469 GROUPTASK_ENQUEUE(gtask); 1470 return (FILTER_HANDLED); 1471 } 1472 1473 static int 1474 iflib_fast_intr_rxtx(void *arg) 1475 { 1476 iflib_filter_info_t info = arg; 1477 struct grouptask *gtask = info->ifi_task; 1478 if_ctx_t ctx; 1479 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1480 iflib_txq_t txq; 1481 void *sc; 1482 int i, cidx, result; 1483 qidx_t txqid; 1484 bool intr_enable, intr_legacy; 1485 1486 DBG_COUNTER_INC(fast_intrs); 1487 if (info->ifi_filter != NULL) { 1488 result = info->ifi_filter(info->ifi_filter_arg); 1489 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1490 return (result); 1491 } 1492 1493 ctx = rxq->ifr_ctx; 1494 sc = ctx->ifc_softc; 1495 intr_enable = false; 1496 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1497 MPASS(rxq->ifr_ntxqirq); 1498 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1499 txqid = rxq->ifr_txqid[i]; 1500 txq = &ctx->ifc_txqs[txqid]; 1501 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1502 BUS_DMASYNC_POSTREAD); 1503 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1504 if (intr_legacy) 1505 intr_enable = true; 1506 else 1507 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1508 continue; 1509 } 1510 GROUPTASK_ENQUEUE(&txq->ift_task); 1511 } 1512 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1513 cidx = rxq->ifr_cq_cidx; 1514 else 1515 cidx = rxq->ifr_fl[0].ifl_cidx; 1516 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1517 GROUPTASK_ENQUEUE(gtask); 1518 else { 1519 if (intr_legacy) 1520 intr_enable = true; 1521 else 1522 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1523 DBG_COUNTER_INC(rx_intr_enables); 1524 } 1525 if (intr_enable) 1526 IFDI_INTR_ENABLE(ctx); 1527 return (FILTER_HANDLED); 1528 } 1529 1530 static int 1531 iflib_fast_intr_ctx(void *arg) 1532 { 1533 iflib_filter_info_t info = arg; 1534 struct grouptask *gtask = info->ifi_task; 1535 int result; 1536 1537 DBG_COUNTER_INC(fast_intrs); 1538 if (info->ifi_filter != NULL) { 1539 result = info->ifi_filter(info->ifi_filter_arg); 1540 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1541 return (result); 1542 } 1543 1544 GROUPTASK_ENQUEUE(gtask); 1545 return (FILTER_HANDLED); 1546 } 1547 1548 static int 1549 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1550 driver_filter_t filter, driver_intr_t handler, void *arg, 1551 const char *name) 1552 { 1553 struct resource *res; 1554 void *tag = NULL; 1555 device_t dev = ctx->ifc_dev; 1556 int flags, i, rc; 1557 1558 flags = RF_ACTIVE; 1559 if (ctx->ifc_flags & IFC_LEGACY) 1560 flags |= RF_SHAREABLE; 1561 MPASS(rid < 512); 1562 i = rid; 1563 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1564 if (res == NULL) { 1565 device_printf(dev, 1566 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1567 return (ENOMEM); 1568 } 1569 irq->ii_res = res; 1570 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1571 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1572 filter, handler, arg, &tag); 1573 if (rc != 0) { 1574 device_printf(dev, 1575 "failed to setup interrupt for rid %d, name %s: %d\n", 1576 rid, name ? name : "unknown", rc); 1577 return (rc); 1578 } else if (name) 1579 bus_describe_intr(dev, res, tag, "%s", name); 1580 1581 irq->ii_tag = tag; 1582 return (0); 1583 } 1584 1585 /********************************************************************* 1586 * 1587 * Allocate DMA resources for TX buffers as well as memory for the TX 1588 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1589 * iflib_sw_tx_desc_array structure, storing all the information that 1590 * is needed to transmit a packet on the wire. This is called only 1591 * once at attach, setup is done every reset. 1592 * 1593 **********************************************************************/ 1594 static int 1595 iflib_txsd_alloc(iflib_txq_t txq) 1596 { 1597 if_ctx_t ctx = txq->ift_ctx; 1598 if_shared_ctx_t sctx = ctx->ifc_sctx; 1599 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1600 device_t dev = ctx->ifc_dev; 1601 bus_size_t tsomaxsize; 1602 int err, nsegments, ntsosegments; 1603 bool tso; 1604 1605 nsegments = scctx->isc_tx_nsegments; 1606 ntsosegments = scctx->isc_tx_tso_segments_max; 1607 tsomaxsize = scctx->isc_tx_tso_size_max; 1608 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1609 tsomaxsize += sizeof(struct ether_vlan_header); 1610 MPASS(scctx->isc_ntxd[0] > 0); 1611 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1612 MPASS(nsegments > 0); 1613 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1614 MPASS(ntsosegments > 0); 1615 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1616 } 1617 1618 /* 1619 * Set up DMA tags for TX buffers. 1620 */ 1621 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1622 1, 0, /* alignment, bounds */ 1623 BUS_SPACE_MAXADDR, /* lowaddr */ 1624 BUS_SPACE_MAXADDR, /* highaddr */ 1625 NULL, NULL, /* filter, filterarg */ 1626 sctx->isc_tx_maxsize, /* maxsize */ 1627 nsegments, /* nsegments */ 1628 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1629 0, /* flags */ 1630 NULL, /* lockfunc */ 1631 NULL, /* lockfuncarg */ 1632 &txq->ift_buf_tag))) { 1633 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1634 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1635 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1636 goto fail; 1637 } 1638 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1639 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1640 1, 0, /* alignment, bounds */ 1641 BUS_SPACE_MAXADDR, /* lowaddr */ 1642 BUS_SPACE_MAXADDR, /* highaddr */ 1643 NULL, NULL, /* filter, filterarg */ 1644 tsomaxsize, /* maxsize */ 1645 ntsosegments, /* nsegments */ 1646 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1647 0, /* flags */ 1648 NULL, /* lockfunc */ 1649 NULL, /* lockfuncarg */ 1650 &txq->ift_tso_buf_tag))) { 1651 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1652 err); 1653 goto fail; 1654 } 1655 1656 /* Allocate memory for the TX mbuf map. */ 1657 if (!(txq->ift_sds.ifsd_m = 1658 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1659 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1660 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1661 err = ENOMEM; 1662 goto fail; 1663 } 1664 1665 /* 1666 * Create the DMA maps for TX buffers. 1667 */ 1668 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1669 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1670 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1671 device_printf(dev, 1672 "Unable to allocate TX buffer DMA map memory\n"); 1673 err = ENOMEM; 1674 goto fail; 1675 } 1676 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1677 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1678 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1679 device_printf(dev, 1680 "Unable to allocate TSO TX buffer map memory\n"); 1681 err = ENOMEM; 1682 goto fail; 1683 } 1684 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1685 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1686 &txq->ift_sds.ifsd_map[i]); 1687 if (err != 0) { 1688 device_printf(dev, "Unable to create TX DMA map\n"); 1689 goto fail; 1690 } 1691 if (!tso) 1692 continue; 1693 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1694 &txq->ift_sds.ifsd_tso_map[i]); 1695 if (err != 0) { 1696 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1697 goto fail; 1698 } 1699 } 1700 return (0); 1701 fail: 1702 /* We free all, it handles case where we are in the middle */ 1703 iflib_tx_structures_free(ctx); 1704 return (err); 1705 } 1706 1707 static void 1708 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1709 { 1710 bus_dmamap_t map; 1711 1712 if (txq->ift_sds.ifsd_map != NULL) { 1713 map = txq->ift_sds.ifsd_map[i]; 1714 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1715 bus_dmamap_unload(txq->ift_buf_tag, map); 1716 bus_dmamap_destroy(txq->ift_buf_tag, map); 1717 txq->ift_sds.ifsd_map[i] = NULL; 1718 } 1719 1720 if (txq->ift_sds.ifsd_tso_map != NULL) { 1721 map = txq->ift_sds.ifsd_tso_map[i]; 1722 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1723 BUS_DMASYNC_POSTWRITE); 1724 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1725 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1726 txq->ift_sds.ifsd_tso_map[i] = NULL; 1727 } 1728 } 1729 1730 static void 1731 iflib_txq_destroy(iflib_txq_t txq) 1732 { 1733 if_ctx_t ctx = txq->ift_ctx; 1734 1735 for (int i = 0; i < txq->ift_size; i++) 1736 iflib_txsd_destroy(ctx, txq, i); 1737 1738 if (txq->ift_br != NULL) { 1739 ifmp_ring_free(txq->ift_br); 1740 txq->ift_br = NULL; 1741 } 1742 1743 mtx_destroy(&txq->ift_mtx); 1744 1745 if (txq->ift_sds.ifsd_map != NULL) { 1746 free(txq->ift_sds.ifsd_map, M_IFLIB); 1747 txq->ift_sds.ifsd_map = NULL; 1748 } 1749 if (txq->ift_sds.ifsd_tso_map != NULL) { 1750 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1751 txq->ift_sds.ifsd_tso_map = NULL; 1752 } 1753 if (txq->ift_sds.ifsd_m != NULL) { 1754 free(txq->ift_sds.ifsd_m, M_IFLIB); 1755 txq->ift_sds.ifsd_m = NULL; 1756 } 1757 if (txq->ift_buf_tag != NULL) { 1758 bus_dma_tag_destroy(txq->ift_buf_tag); 1759 txq->ift_buf_tag = NULL; 1760 } 1761 if (txq->ift_tso_buf_tag != NULL) { 1762 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1763 txq->ift_tso_buf_tag = NULL; 1764 } 1765 if (txq->ift_ifdi != NULL) { 1766 free(txq->ift_ifdi, M_IFLIB); 1767 } 1768 } 1769 1770 static void 1771 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1772 { 1773 struct mbuf **mp; 1774 1775 mp = &txq->ift_sds.ifsd_m[i]; 1776 if (*mp == NULL) 1777 return; 1778 1779 if (txq->ift_sds.ifsd_map != NULL) { 1780 bus_dmamap_sync(txq->ift_buf_tag, 1781 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1782 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1783 } 1784 if (txq->ift_sds.ifsd_tso_map != NULL) { 1785 bus_dmamap_sync(txq->ift_tso_buf_tag, 1786 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1787 bus_dmamap_unload(txq->ift_tso_buf_tag, 1788 txq->ift_sds.ifsd_tso_map[i]); 1789 } 1790 m_free(*mp); 1791 DBG_COUNTER_INC(tx_frees); 1792 *mp = NULL; 1793 } 1794 1795 static int 1796 iflib_txq_setup(iflib_txq_t txq) 1797 { 1798 if_ctx_t ctx = txq->ift_ctx; 1799 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1800 if_shared_ctx_t sctx = ctx->ifc_sctx; 1801 iflib_dma_info_t di; 1802 int i; 1803 1804 /* Set number of descriptors available */ 1805 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1806 /* XXX make configurable */ 1807 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1808 1809 /* Reset indices */ 1810 txq->ift_cidx_processed = 0; 1811 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1812 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1813 1814 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1815 bzero((void *)di->idi_vaddr, di->idi_size); 1816 1817 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1818 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1819 bus_dmamap_sync(di->idi_tag, di->idi_map, 1820 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1821 return (0); 1822 } 1823 1824 /********************************************************************* 1825 * 1826 * Allocate DMA resources for RX buffers as well as memory for the RX 1827 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1828 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1829 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1830 * Since we use use one entry in iflib_sw_rx_desc_array per received 1831 * packet, the maximum number of entries we'll need is equal to the 1832 * number of hardware receive descriptors that we've allocated. 1833 * 1834 **********************************************************************/ 1835 static int 1836 iflib_rxsd_alloc(iflib_rxq_t rxq) 1837 { 1838 if_ctx_t ctx = rxq->ifr_ctx; 1839 if_shared_ctx_t sctx = ctx->ifc_sctx; 1840 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1841 device_t dev = ctx->ifc_dev; 1842 iflib_fl_t fl; 1843 int err; 1844 1845 MPASS(scctx->isc_nrxd[0] > 0); 1846 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1847 1848 fl = rxq->ifr_fl; 1849 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1850 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1851 /* Set up DMA tag for RX buffers. */ 1852 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1853 1, 0, /* alignment, bounds */ 1854 BUS_SPACE_MAXADDR, /* lowaddr */ 1855 BUS_SPACE_MAXADDR, /* highaddr */ 1856 NULL, NULL, /* filter, filterarg */ 1857 sctx->isc_rx_maxsize, /* maxsize */ 1858 sctx->isc_rx_nsegments, /* nsegments */ 1859 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1860 0, /* flags */ 1861 NULL, /* lockfunc */ 1862 NULL, /* lockarg */ 1863 &fl->ifl_buf_tag); 1864 if (err) { 1865 device_printf(dev, 1866 "Unable to allocate RX DMA tag: %d\n", err); 1867 goto fail; 1868 } 1869 1870 /* Allocate memory for the RX mbuf map. */ 1871 if (!(fl->ifl_sds.ifsd_m = 1872 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1873 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1874 device_printf(dev, 1875 "Unable to allocate RX mbuf map memory\n"); 1876 err = ENOMEM; 1877 goto fail; 1878 } 1879 1880 /* Allocate memory for the direct RX cluster pointer map. */ 1881 if (!(fl->ifl_sds.ifsd_cl = 1882 (caddr_t *) malloc(sizeof(caddr_t) * 1883 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1884 device_printf(dev, 1885 "Unable to allocate RX cluster map memory\n"); 1886 err = ENOMEM; 1887 goto fail; 1888 } 1889 1890 /* Allocate memory for the RX cluster bus address map. */ 1891 if (!(fl->ifl_sds.ifsd_ba = 1892 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1893 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1894 device_printf(dev, 1895 "Unable to allocate RX bus address map memory\n"); 1896 err = ENOMEM; 1897 goto fail; 1898 } 1899 1900 /* 1901 * Create the DMA maps for RX buffers. 1902 */ 1903 if (!(fl->ifl_sds.ifsd_map = 1904 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1905 device_printf(dev, 1906 "Unable to allocate RX buffer DMA map memory\n"); 1907 err = ENOMEM; 1908 goto fail; 1909 } 1910 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1911 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1912 &fl->ifl_sds.ifsd_map[i]); 1913 if (err != 0) { 1914 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1915 goto fail; 1916 } 1917 } 1918 } 1919 return (0); 1920 1921 fail: 1922 iflib_rx_structures_free(ctx); 1923 return (err); 1924 } 1925 1926 /* 1927 * Internal service routines 1928 */ 1929 1930 struct rxq_refill_cb_arg { 1931 int error; 1932 bus_dma_segment_t seg; 1933 int nseg; 1934 }; 1935 1936 static void 1937 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1938 { 1939 struct rxq_refill_cb_arg *cb_arg = arg; 1940 1941 cb_arg->error = error; 1942 cb_arg->seg = segs[0]; 1943 cb_arg->nseg = nseg; 1944 } 1945 1946 /** 1947 * iflib_fl_refill - refill an rxq free-buffer list 1948 * @ctx: the iflib context 1949 * @fl: the free list to refill 1950 * @count: the number of new buffers to allocate 1951 * 1952 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 1953 * The caller must assure that @count does not exceed the queue's capacity 1954 * minus one (since we always leave a descriptor unavailable). 1955 */ 1956 static uint8_t 1957 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1958 { 1959 struct if_rxd_update iru; 1960 struct rxq_refill_cb_arg cb_arg; 1961 struct mbuf *m; 1962 caddr_t cl, *sd_cl; 1963 struct mbuf **sd_m; 1964 bus_dmamap_t *sd_map; 1965 bus_addr_t bus_addr, *sd_ba; 1966 int err, frag_idx, i, idx, n, pidx; 1967 qidx_t credits; 1968 1969 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 1970 1971 sd_m = fl->ifl_sds.ifsd_m; 1972 sd_map = fl->ifl_sds.ifsd_map; 1973 sd_cl = fl->ifl_sds.ifsd_cl; 1974 sd_ba = fl->ifl_sds.ifsd_ba; 1975 pidx = fl->ifl_pidx; 1976 idx = pidx; 1977 frag_idx = fl->ifl_fragidx; 1978 credits = fl->ifl_credits; 1979 1980 i = 0; 1981 n = count; 1982 MPASS(n > 0); 1983 MPASS(credits + n <= fl->ifl_size); 1984 1985 if (pidx < fl->ifl_cidx) 1986 MPASS(pidx + n <= fl->ifl_cidx); 1987 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1988 MPASS(fl->ifl_gen == 0); 1989 if (pidx > fl->ifl_cidx) 1990 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1991 1992 DBG_COUNTER_INC(fl_refills); 1993 if (n > 8) 1994 DBG_COUNTER_INC(fl_refills_large); 1995 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1996 while (n-- > 0) { 1997 /* 1998 * We allocate an uninitialized mbuf + cluster, mbuf is 1999 * initialized after rx. 2000 * 2001 * If the cluster is still set then we know a minimum sized 2002 * packet was received 2003 */ 2004 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2005 &frag_idx); 2006 if (frag_idx < 0) 2007 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2008 MPASS(frag_idx >= 0); 2009 if ((cl = sd_cl[frag_idx]) == NULL) { 2010 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2011 if (__predict_false(cl == NULL)) 2012 break; 2013 2014 cb_arg.error = 0; 2015 MPASS(sd_map != NULL); 2016 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2017 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2018 BUS_DMA_NOWAIT); 2019 if (__predict_false(err != 0 || cb_arg.error)) { 2020 uma_zfree(fl->ifl_zone, cl); 2021 break; 2022 } 2023 2024 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2025 sd_cl[frag_idx] = cl; 2026 #if MEMORY_LOGGING 2027 fl->ifl_cl_enqueued++; 2028 #endif 2029 } else { 2030 bus_addr = sd_ba[frag_idx]; 2031 } 2032 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2033 BUS_DMASYNC_PREREAD); 2034 2035 if (sd_m[frag_idx] == NULL) { 2036 m = m_gethdr(M_NOWAIT, MT_NOINIT); 2037 if (__predict_false(m == NULL)) 2038 break; 2039 sd_m[frag_idx] = m; 2040 } 2041 bit_set(fl->ifl_rx_bitmap, frag_idx); 2042 #if MEMORY_LOGGING 2043 fl->ifl_m_enqueued++; 2044 #endif 2045 2046 DBG_COUNTER_INC(rx_allocs); 2047 fl->ifl_rxd_idxs[i] = frag_idx; 2048 fl->ifl_bus_addrs[i] = bus_addr; 2049 credits++; 2050 i++; 2051 MPASS(credits <= fl->ifl_size); 2052 if (++idx == fl->ifl_size) { 2053 #ifdef INVARIANTS 2054 fl->ifl_gen = 1; 2055 #endif 2056 idx = 0; 2057 } 2058 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2059 iru.iru_pidx = pidx; 2060 iru.iru_count = i; 2061 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2062 fl->ifl_pidx = idx; 2063 fl->ifl_credits = credits; 2064 pidx = idx; 2065 i = 0; 2066 } 2067 } 2068 2069 if (n < count - 1) { 2070 if (i != 0) { 2071 iru.iru_pidx = pidx; 2072 iru.iru_count = i; 2073 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2074 fl->ifl_pidx = idx; 2075 fl->ifl_credits = credits; 2076 } 2077 DBG_COUNTER_INC(rxd_flush); 2078 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2079 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2080 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2081 fl->ifl_id, fl->ifl_pidx); 2082 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2083 fl->ifl_fragidx = frag_idx + 1; 2084 if (fl->ifl_fragidx == fl->ifl_size) 2085 fl->ifl_fragidx = 0; 2086 } else { 2087 fl->ifl_fragidx = frag_idx; 2088 } 2089 } 2090 2091 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2092 } 2093 2094 static inline uint8_t 2095 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2096 { 2097 /* 2098 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2099 * This is important as it confuses most NICs. For instance, 2100 * Intel NICs have (per receive ring) RDH and RDT registers, where 2101 * RDH points to the next receive descriptor to be used by the NIC, 2102 * and RDT for the next receive descriptor to be published by the 2103 * driver to the NIC (RDT - 1 is thus the last valid one). 2104 * The condition RDH == RDT means no descriptors are available to 2105 * the NIC, and thus it would be ambiguous if it also meant that 2106 * all the descriptors are available to the NIC. 2107 */ 2108 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2109 #ifdef INVARIANTS 2110 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2111 #endif 2112 2113 MPASS(fl->ifl_credits <= fl->ifl_size); 2114 MPASS(reclaimable == delta); 2115 2116 if (reclaimable > 0) 2117 return (iflib_fl_refill(ctx, fl, reclaimable)); 2118 return (0); 2119 } 2120 2121 uint8_t 2122 iflib_in_detach(if_ctx_t ctx) 2123 { 2124 bool in_detach; 2125 2126 STATE_LOCK(ctx); 2127 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2128 STATE_UNLOCK(ctx); 2129 return (in_detach); 2130 } 2131 2132 static void 2133 iflib_fl_bufs_free(iflib_fl_t fl) 2134 { 2135 iflib_dma_info_t idi = fl->ifl_ifdi; 2136 bus_dmamap_t sd_map; 2137 uint32_t i; 2138 2139 for (i = 0; i < fl->ifl_size; i++) { 2140 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2141 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2142 2143 if (*sd_cl != NULL) { 2144 sd_map = fl->ifl_sds.ifsd_map[i]; 2145 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2146 BUS_DMASYNC_POSTREAD); 2147 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2148 uma_zfree(fl->ifl_zone, *sd_cl); 2149 *sd_cl = NULL; 2150 if (*sd_m != NULL) { 2151 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2152 uma_zfree(zone_mbuf, *sd_m); 2153 *sd_m = NULL; 2154 } 2155 } else { 2156 MPASS(*sd_m == NULL); 2157 } 2158 #if MEMORY_LOGGING 2159 fl->ifl_m_dequeued++; 2160 fl->ifl_cl_dequeued++; 2161 #endif 2162 } 2163 #ifdef INVARIANTS 2164 for (i = 0; i < fl->ifl_size; i++) { 2165 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2166 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2167 } 2168 #endif 2169 /* 2170 * Reset free list values 2171 */ 2172 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2173 bzero(idi->idi_vaddr, idi->idi_size); 2174 } 2175 2176 /********************************************************************* 2177 * 2178 * Initialize a free list and its buffers. 2179 * 2180 **********************************************************************/ 2181 static int 2182 iflib_fl_setup(iflib_fl_t fl) 2183 { 2184 iflib_rxq_t rxq = fl->ifl_rxq; 2185 if_ctx_t ctx = rxq->ifr_ctx; 2186 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2187 int qidx; 2188 2189 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2190 /* 2191 ** Free current RX buffer structs and their mbufs 2192 */ 2193 iflib_fl_bufs_free(fl); 2194 /* Now replenish the mbufs */ 2195 MPASS(fl->ifl_credits == 0); 2196 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2197 if (scctx->isc_rxd_buf_size[qidx] != 0) 2198 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2199 else 2200 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2201 /* 2202 * ifl_buf_size may be a driver-supplied value, so pull it up 2203 * to the selected mbuf size. 2204 */ 2205 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2206 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2207 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2208 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2209 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2210 2211 /* 2212 * Avoid pre-allocating zillions of clusters to an idle card 2213 * potentially speeding up attach. In any case make sure 2214 * to leave a descriptor unavailable. See the comment in 2215 * iflib_fl_refill_all(). 2216 */ 2217 MPASS(fl->ifl_size > 0); 2218 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2219 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2220 return (ENOBUFS); 2221 /* 2222 * handle failure 2223 */ 2224 MPASS(rxq != NULL); 2225 MPASS(fl->ifl_ifdi != NULL); 2226 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2227 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2228 return (0); 2229 } 2230 2231 /********************************************************************* 2232 * 2233 * Free receive ring data structures 2234 * 2235 **********************************************************************/ 2236 static void 2237 iflib_rx_sds_free(iflib_rxq_t rxq) 2238 { 2239 iflib_fl_t fl; 2240 int i, j; 2241 2242 if (rxq->ifr_fl != NULL) { 2243 for (i = 0; i < rxq->ifr_nfl; i++) { 2244 fl = &rxq->ifr_fl[i]; 2245 if (fl->ifl_buf_tag != NULL) { 2246 if (fl->ifl_sds.ifsd_map != NULL) { 2247 for (j = 0; j < fl->ifl_size; j++) { 2248 bus_dmamap_sync( 2249 fl->ifl_buf_tag, 2250 fl->ifl_sds.ifsd_map[j], 2251 BUS_DMASYNC_POSTREAD); 2252 bus_dmamap_unload( 2253 fl->ifl_buf_tag, 2254 fl->ifl_sds.ifsd_map[j]); 2255 bus_dmamap_destroy( 2256 fl->ifl_buf_tag, 2257 fl->ifl_sds.ifsd_map[j]); 2258 } 2259 } 2260 bus_dma_tag_destroy(fl->ifl_buf_tag); 2261 fl->ifl_buf_tag = NULL; 2262 } 2263 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2264 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2265 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2266 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2267 fl->ifl_sds.ifsd_m = NULL; 2268 fl->ifl_sds.ifsd_cl = NULL; 2269 fl->ifl_sds.ifsd_ba = NULL; 2270 fl->ifl_sds.ifsd_map = NULL; 2271 } 2272 free(rxq->ifr_fl, M_IFLIB); 2273 rxq->ifr_fl = NULL; 2274 free(rxq->ifr_ifdi, M_IFLIB); 2275 rxq->ifr_ifdi = NULL; 2276 rxq->ifr_cq_cidx = 0; 2277 } 2278 } 2279 2280 /* 2281 * Timer routine 2282 */ 2283 static void 2284 iflib_timer(void *arg) 2285 { 2286 iflib_txq_t txq = arg; 2287 if_ctx_t ctx = txq->ift_ctx; 2288 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2289 uint64_t this_tick = ticks; 2290 uint32_t reset_on = hz / 2; 2291 2292 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2293 return; 2294 2295 /* 2296 ** Check on the state of the TX queue(s), this 2297 ** can be done without the lock because its RO 2298 ** and the HUNG state will be static if set. 2299 */ 2300 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2301 txq->ift_last_timer_tick = this_tick; 2302 IFDI_TIMER(ctx, txq->ift_id); 2303 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2304 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2305 (sctx->isc_pause_frames == 0))) 2306 goto hung; 2307 2308 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2309 ifmp_ring_is_stalled(txq->ift_br)) { 2310 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down")); 2311 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2312 } 2313 txq->ift_cleaned_prev = txq->ift_cleaned; 2314 } 2315 #ifdef DEV_NETMAP 2316 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2317 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 2318 #endif 2319 /* handle any laggards */ 2320 if (txq->ift_db_pending) 2321 GROUPTASK_ENQUEUE(&txq->ift_task); 2322 2323 sctx->isc_pause_frames = 0; 2324 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2325 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2326 return; 2327 2328 hung: 2329 device_printf(ctx->ifc_dev, 2330 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2331 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2332 STATE_LOCK(ctx); 2333 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2334 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2335 iflib_admin_intr_deferred(ctx); 2336 STATE_UNLOCK(ctx); 2337 } 2338 2339 static uint16_t 2340 iflib_get_mbuf_size_for(unsigned int size) 2341 { 2342 2343 if (size <= MCLBYTES) 2344 return (MCLBYTES); 2345 else 2346 return (MJUMPAGESIZE); 2347 } 2348 2349 static void 2350 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2351 { 2352 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2353 2354 /* 2355 * XXX don't set the max_frame_size to larger 2356 * than the hardware can handle 2357 */ 2358 ctx->ifc_rx_mbuf_sz = 2359 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2360 } 2361 2362 uint32_t 2363 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2364 { 2365 2366 return (ctx->ifc_rx_mbuf_sz); 2367 } 2368 2369 static void 2370 iflib_init_locked(if_ctx_t ctx) 2371 { 2372 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2373 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2374 if_t ifp = ctx->ifc_ifp; 2375 iflib_fl_t fl; 2376 iflib_txq_t txq; 2377 iflib_rxq_t rxq; 2378 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2379 2380 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2381 IFDI_INTR_DISABLE(ctx); 2382 2383 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2384 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2385 /* Set hardware offload abilities */ 2386 if_clearhwassist(ifp); 2387 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2388 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2389 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2390 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2391 if (if_getcapenable(ifp) & IFCAP_TSO4) 2392 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2393 if (if_getcapenable(ifp) & IFCAP_TSO6) 2394 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2395 2396 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2397 CALLOUT_LOCK(txq); 2398 callout_stop(&txq->ift_timer); 2399 CALLOUT_UNLOCK(txq); 2400 iflib_netmap_txq_init(ctx, txq); 2401 } 2402 2403 /* 2404 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2405 * that drivers can use the value when setting up the hardware receive 2406 * buffers. 2407 */ 2408 iflib_calc_rx_mbuf_sz(ctx); 2409 2410 #ifdef INVARIANTS 2411 i = if_getdrvflags(ifp); 2412 #endif 2413 IFDI_INIT(ctx); 2414 MPASS(if_getdrvflags(ifp) == i); 2415 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2416 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2417 /* This rxq is in netmap mode. Skip normal init. */ 2418 continue; 2419 } 2420 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2421 if (iflib_fl_setup(fl)) { 2422 device_printf(ctx->ifc_dev, 2423 "setting up free list %d failed - " 2424 "check cluster settings\n", j); 2425 goto done; 2426 } 2427 } 2428 } 2429 done: 2430 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2431 IFDI_INTR_ENABLE(ctx); 2432 txq = ctx->ifc_txqs; 2433 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2434 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2435 txq->ift_timer.c_cpu); 2436 } 2437 2438 static int 2439 iflib_media_change(if_t ifp) 2440 { 2441 if_ctx_t ctx = if_getsoftc(ifp); 2442 int err; 2443 2444 CTX_LOCK(ctx); 2445 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2446 iflib_init_locked(ctx); 2447 CTX_UNLOCK(ctx); 2448 return (err); 2449 } 2450 2451 static void 2452 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2453 { 2454 if_ctx_t ctx = if_getsoftc(ifp); 2455 2456 CTX_LOCK(ctx); 2457 IFDI_UPDATE_ADMIN_STATUS(ctx); 2458 IFDI_MEDIA_STATUS(ctx, ifmr); 2459 CTX_UNLOCK(ctx); 2460 } 2461 2462 void 2463 iflib_stop(if_ctx_t ctx) 2464 { 2465 iflib_txq_t txq = ctx->ifc_txqs; 2466 iflib_rxq_t rxq = ctx->ifc_rxqs; 2467 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2468 if_shared_ctx_t sctx = ctx->ifc_sctx; 2469 iflib_dma_info_t di; 2470 iflib_fl_t fl; 2471 int i, j; 2472 2473 /* Tell the stack that the interface is no longer active */ 2474 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2475 2476 IFDI_INTR_DISABLE(ctx); 2477 DELAY(1000); 2478 IFDI_STOP(ctx); 2479 DELAY(1000); 2480 2481 iflib_debug_reset(); 2482 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2483 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2484 /* make sure all transmitters have completed before proceeding XXX */ 2485 2486 CALLOUT_LOCK(txq); 2487 callout_stop(&txq->ift_timer); 2488 CALLOUT_UNLOCK(txq); 2489 2490 /* clean any enqueued buffers */ 2491 iflib_ifmp_purge(txq); 2492 /* Free any existing tx buffers. */ 2493 for (j = 0; j < txq->ift_size; j++) { 2494 iflib_txsd_free(ctx, txq, j); 2495 } 2496 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2497 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2498 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2499 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2500 txq->ift_pullups = 0; 2501 ifmp_ring_reset_stats(txq->ift_br); 2502 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2503 bzero((void *)di->idi_vaddr, di->idi_size); 2504 } 2505 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2506 /* make sure all transmitters have completed before proceeding XXX */ 2507 2508 rxq->ifr_cq_cidx = 0; 2509 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2510 bzero((void *)di->idi_vaddr, di->idi_size); 2511 /* also resets the free lists pidx/cidx */ 2512 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2513 iflib_fl_bufs_free(fl); 2514 } 2515 } 2516 2517 static inline caddr_t 2518 calc_next_rxd(iflib_fl_t fl, int cidx) 2519 { 2520 qidx_t size; 2521 int nrxd; 2522 caddr_t start, end, cur, next; 2523 2524 nrxd = fl->ifl_size; 2525 size = fl->ifl_rxd_size; 2526 start = fl->ifl_ifdi->idi_vaddr; 2527 2528 if (__predict_false(size == 0)) 2529 return (start); 2530 cur = start + size*cidx; 2531 end = start + size*nrxd; 2532 next = CACHE_PTR_NEXT(cur); 2533 return (next < end ? next : start); 2534 } 2535 2536 static inline void 2537 prefetch_pkts(iflib_fl_t fl, int cidx) 2538 { 2539 int nextptr; 2540 int nrxd = fl->ifl_size; 2541 caddr_t next_rxd; 2542 2543 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2544 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2545 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2546 next_rxd = calc_next_rxd(fl, cidx); 2547 prefetch(next_rxd); 2548 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2549 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2550 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2551 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2552 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2553 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2554 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2555 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2556 } 2557 2558 static struct mbuf * 2559 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2560 int *pf_rv, if_rxd_info_t ri) 2561 { 2562 bus_dmamap_t map; 2563 iflib_fl_t fl; 2564 caddr_t payload; 2565 struct mbuf *m; 2566 int flid, cidx, len, next; 2567 2568 map = NULL; 2569 flid = irf->irf_flid; 2570 cidx = irf->irf_idx; 2571 fl = &rxq->ifr_fl[flid]; 2572 sd->ifsd_fl = fl; 2573 m = fl->ifl_sds.ifsd_m[cidx]; 2574 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2575 fl->ifl_credits--; 2576 #if MEMORY_LOGGING 2577 fl->ifl_m_dequeued++; 2578 #endif 2579 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2580 prefetch_pkts(fl, cidx); 2581 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2582 prefetch(&fl->ifl_sds.ifsd_map[next]); 2583 map = fl->ifl_sds.ifsd_map[cidx]; 2584 2585 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2586 2587 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2588 irf->irf_len != 0) { 2589 payload = *sd->ifsd_cl; 2590 payload += ri->iri_pad; 2591 len = ri->iri_len - ri->iri_pad; 2592 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2593 len | PFIL_MEMPTR | PFIL_IN, NULL); 2594 switch (*pf_rv) { 2595 case PFIL_DROPPED: 2596 case PFIL_CONSUMED: 2597 /* 2598 * The filter ate it. Everything is recycled. 2599 */ 2600 m = NULL; 2601 unload = 0; 2602 break; 2603 case PFIL_REALLOCED: 2604 /* 2605 * The filter copied it. Everything is recycled. 2606 */ 2607 m = pfil_mem2mbuf(payload); 2608 unload = 0; 2609 break; 2610 case PFIL_PASS: 2611 /* 2612 * Filter said it was OK, so receive like 2613 * normal 2614 */ 2615 fl->ifl_sds.ifsd_m[cidx] = NULL; 2616 break; 2617 default: 2618 MPASS(0); 2619 } 2620 } else { 2621 fl->ifl_sds.ifsd_m[cidx] = NULL; 2622 *pf_rv = PFIL_PASS; 2623 } 2624 2625 if (unload && irf->irf_len != 0) 2626 bus_dmamap_unload(fl->ifl_buf_tag, map); 2627 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2628 if (__predict_false(fl->ifl_cidx == 0)) 2629 fl->ifl_gen = 0; 2630 bit_clear(fl->ifl_rx_bitmap, cidx); 2631 return (m); 2632 } 2633 2634 static struct mbuf * 2635 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2636 { 2637 struct mbuf *m, *mh, *mt; 2638 caddr_t cl; 2639 int *pf_rv_ptr, flags, i, padlen; 2640 bool consumed; 2641 2642 i = 0; 2643 mh = NULL; 2644 consumed = false; 2645 *pf_rv = PFIL_PASS; 2646 pf_rv_ptr = pf_rv; 2647 do { 2648 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2649 pf_rv_ptr, ri); 2650 2651 MPASS(*sd->ifsd_cl != NULL); 2652 2653 /* 2654 * Exclude zero-length frags & frags from 2655 * packets the filter has consumed or dropped 2656 */ 2657 if (ri->iri_frags[i].irf_len == 0 || consumed || 2658 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2659 if (mh == NULL) { 2660 /* everything saved here */ 2661 consumed = true; 2662 pf_rv_ptr = NULL; 2663 continue; 2664 } 2665 /* XXX we can save the cluster here, but not the mbuf */ 2666 m_init(m, M_NOWAIT, MT_DATA, 0); 2667 m_free(m); 2668 continue; 2669 } 2670 if (mh == NULL) { 2671 flags = M_PKTHDR|M_EXT; 2672 mh = mt = m; 2673 padlen = ri->iri_pad; 2674 } else { 2675 flags = M_EXT; 2676 mt->m_next = m; 2677 mt = m; 2678 /* assuming padding is only on the first fragment */ 2679 padlen = 0; 2680 } 2681 cl = *sd->ifsd_cl; 2682 *sd->ifsd_cl = NULL; 2683 2684 /* Can these two be made one ? */ 2685 m_init(m, M_NOWAIT, MT_DATA, flags); 2686 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2687 /* 2688 * These must follow m_init and m_cljset 2689 */ 2690 m->m_data += padlen; 2691 ri->iri_len -= padlen; 2692 m->m_len = ri->iri_frags[i].irf_len; 2693 } while (++i < ri->iri_nfrags); 2694 2695 return (mh); 2696 } 2697 2698 /* 2699 * Process one software descriptor 2700 */ 2701 static struct mbuf * 2702 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2703 { 2704 struct if_rxsd sd; 2705 struct mbuf *m; 2706 int pf_rv; 2707 2708 /* should I merge this back in now that the two paths are basically duplicated? */ 2709 if (ri->iri_nfrags == 1 && 2710 ri->iri_frags[0].irf_len != 0 && 2711 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2712 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2713 &pf_rv, ri); 2714 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2715 return (m); 2716 if (pf_rv == PFIL_PASS) { 2717 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2718 #ifndef __NO_STRICT_ALIGNMENT 2719 if (!IP_ALIGNED(m)) 2720 m->m_data += 2; 2721 #endif 2722 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2723 m->m_len = ri->iri_frags[0].irf_len; 2724 } 2725 } else { 2726 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2727 if (m == NULL) 2728 return (NULL); 2729 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2730 return (m); 2731 } 2732 m->m_pkthdr.len = ri->iri_len; 2733 m->m_pkthdr.rcvif = ri->iri_ifp; 2734 m->m_flags |= ri->iri_flags; 2735 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2736 m->m_pkthdr.flowid = ri->iri_flowid; 2737 M_HASHTYPE_SET(m, ri->iri_rsstype); 2738 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2739 m->m_pkthdr.csum_data = ri->iri_csum_data; 2740 return (m); 2741 } 2742 2743 #if defined(INET6) || defined(INET) 2744 static void 2745 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2746 { 2747 CURVNET_SET(lc->ifp->if_vnet); 2748 #if defined(INET6) 2749 *v6 = V_ip6_forwarding; 2750 #endif 2751 #if defined(INET) 2752 *v4 = V_ipforwarding; 2753 #endif 2754 CURVNET_RESTORE(); 2755 } 2756 2757 /* 2758 * Returns true if it's possible this packet could be LROed. 2759 * if it returns false, it is guaranteed that tcp_lro_rx() 2760 * would not return zero. 2761 */ 2762 static bool 2763 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2764 { 2765 struct ether_header *eh; 2766 2767 eh = mtod(m, struct ether_header *); 2768 switch (eh->ether_type) { 2769 #if defined(INET6) 2770 case htons(ETHERTYPE_IPV6): 2771 return (!v6_forwarding); 2772 #endif 2773 #if defined (INET) 2774 case htons(ETHERTYPE_IP): 2775 return (!v4_forwarding); 2776 #endif 2777 } 2778 2779 return false; 2780 } 2781 #else 2782 static void 2783 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2784 { 2785 } 2786 #endif 2787 2788 static void 2789 _task_fn_rx_watchdog(void *context) 2790 { 2791 iflib_rxq_t rxq = context; 2792 2793 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2794 } 2795 2796 static uint8_t 2797 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2798 { 2799 if_t ifp; 2800 if_ctx_t ctx = rxq->ifr_ctx; 2801 if_shared_ctx_t sctx = ctx->ifc_sctx; 2802 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2803 int avail, i; 2804 qidx_t *cidxp; 2805 struct if_rxd_info ri; 2806 int err, budget_left, rx_bytes, rx_pkts; 2807 iflib_fl_t fl; 2808 int lro_enabled; 2809 bool v4_forwarding, v6_forwarding, lro_possible; 2810 uint8_t retval = 0; 2811 2812 /* 2813 * XXX early demux data packets so that if_input processing only handles 2814 * acks in interrupt context 2815 */ 2816 struct mbuf *m, *mh, *mt, *mf; 2817 2818 NET_EPOCH_ASSERT(); 2819 2820 lro_possible = v4_forwarding = v6_forwarding = false; 2821 ifp = ctx->ifc_ifp; 2822 mh = mt = NULL; 2823 MPASS(budget > 0); 2824 rx_pkts = rx_bytes = 0; 2825 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2826 cidxp = &rxq->ifr_cq_cidx; 2827 else 2828 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2829 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2830 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2831 retval |= iflib_fl_refill_all(ctx, fl); 2832 DBG_COUNTER_INC(rx_unavail); 2833 return (retval); 2834 } 2835 2836 /* pfil needs the vnet to be set */ 2837 CURVNET_SET_QUIET(ifp->if_vnet); 2838 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2839 if (__predict_false(!CTX_ACTIVE(ctx))) { 2840 DBG_COUNTER_INC(rx_ctx_inactive); 2841 break; 2842 } 2843 /* 2844 * Reset client set fields to their default values 2845 */ 2846 rxd_info_zero(&ri); 2847 ri.iri_qsidx = rxq->ifr_id; 2848 ri.iri_cidx = *cidxp; 2849 ri.iri_ifp = ifp; 2850 ri.iri_frags = rxq->ifr_frags; 2851 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2852 2853 if (err) 2854 goto err; 2855 rx_pkts += 1; 2856 rx_bytes += ri.iri_len; 2857 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2858 *cidxp = ri.iri_cidx; 2859 /* Update our consumer index */ 2860 /* XXX NB: shurd - check if this is still safe */ 2861 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2862 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2863 /* was this only a completion queue message? */ 2864 if (__predict_false(ri.iri_nfrags == 0)) 2865 continue; 2866 } 2867 MPASS(ri.iri_nfrags != 0); 2868 MPASS(ri.iri_len != 0); 2869 2870 /* will advance the cidx on the corresponding free lists */ 2871 m = iflib_rxd_pkt_get(rxq, &ri); 2872 avail--; 2873 budget_left--; 2874 if (avail == 0 && budget_left) 2875 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2876 2877 if (__predict_false(m == NULL)) 2878 continue; 2879 2880 /* imm_pkt: -- cxgb */ 2881 if (mh == NULL) 2882 mh = mt = m; 2883 else { 2884 mt->m_nextpkt = m; 2885 mt = m; 2886 } 2887 } 2888 CURVNET_RESTORE(); 2889 /* make sure that we can refill faster than drain */ 2890 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2891 retval |= iflib_fl_refill_all(ctx, fl); 2892 2893 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2894 if (lro_enabled) 2895 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2896 mt = mf = NULL; 2897 while (mh != NULL) { 2898 m = mh; 2899 mh = mh->m_nextpkt; 2900 m->m_nextpkt = NULL; 2901 #ifndef __NO_STRICT_ALIGNMENT 2902 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2903 continue; 2904 #endif 2905 rx_bytes += m->m_pkthdr.len; 2906 rx_pkts++; 2907 #if defined(INET6) || defined(INET) 2908 if (lro_enabled) { 2909 if (!lro_possible) { 2910 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2911 if (lro_possible && mf != NULL) { 2912 ifp->if_input(ifp, mf); 2913 DBG_COUNTER_INC(rx_if_input); 2914 mt = mf = NULL; 2915 } 2916 } 2917 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2918 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2919 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2920 continue; 2921 } 2922 } 2923 #endif 2924 if (lro_possible) { 2925 ifp->if_input(ifp, m); 2926 DBG_COUNTER_INC(rx_if_input); 2927 continue; 2928 } 2929 2930 if (mf == NULL) 2931 mf = m; 2932 if (mt != NULL) 2933 mt->m_nextpkt = m; 2934 mt = m; 2935 } 2936 if (mf != NULL) { 2937 ifp->if_input(ifp, mf); 2938 DBG_COUNTER_INC(rx_if_input); 2939 } 2940 2941 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2942 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2943 2944 /* 2945 * Flush any outstanding LRO work 2946 */ 2947 #if defined(INET6) || defined(INET) 2948 tcp_lro_flush_all(&rxq->ifr_lc); 2949 #endif 2950 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 2951 retval |= IFLIB_RXEOF_MORE; 2952 return (retval); 2953 err: 2954 STATE_LOCK(ctx); 2955 ctx->ifc_flags |= IFC_DO_RESET; 2956 iflib_admin_intr_deferred(ctx); 2957 STATE_UNLOCK(ctx); 2958 return (0); 2959 } 2960 2961 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2962 static inline qidx_t 2963 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2964 { 2965 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2966 qidx_t minthresh = txq->ift_size / 8; 2967 if (in_use > 4*minthresh) 2968 return (notify_count); 2969 if (in_use > 2*minthresh) 2970 return (notify_count >> 1); 2971 if (in_use > minthresh) 2972 return (notify_count >> 3); 2973 return (0); 2974 } 2975 2976 static inline qidx_t 2977 txq_max_rs_deferred(iflib_txq_t txq) 2978 { 2979 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2980 qidx_t minthresh = txq->ift_size / 8; 2981 if (txq->ift_in_use > 4*minthresh) 2982 return (notify_count); 2983 if (txq->ift_in_use > 2*minthresh) 2984 return (notify_count >> 1); 2985 if (txq->ift_in_use > minthresh) 2986 return (notify_count >> 2); 2987 return (2); 2988 } 2989 2990 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2991 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2992 2993 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2994 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2995 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2996 2997 /* forward compatibility for cxgb */ 2998 #define FIRST_QSET(ctx) 0 2999 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3000 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3001 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3002 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3003 3004 /* XXX we should be setting this to something other than zero */ 3005 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 3006 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3007 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3008 3009 static inline bool 3010 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 3011 { 3012 qidx_t dbval, max; 3013 bool rang; 3014 3015 rang = false; 3016 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 3017 if (ring || txq->ift_db_pending >= max) { 3018 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3019 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3020 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3021 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3022 txq->ift_db_pending = txq->ift_npending = 0; 3023 rang = true; 3024 } 3025 return (rang); 3026 } 3027 3028 #ifdef PKT_DEBUG 3029 static void 3030 print_pkt(if_pkt_info_t pi) 3031 { 3032 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3033 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3034 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3035 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3036 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3037 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3038 } 3039 #endif 3040 3041 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3042 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3043 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3044 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3045 3046 static int 3047 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3048 { 3049 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3050 struct ether_vlan_header *eh; 3051 struct mbuf *m; 3052 3053 m = *mp; 3054 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3055 M_WRITABLE(m) == 0) { 3056 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3057 return (ENOMEM); 3058 } else { 3059 m_freem(*mp); 3060 DBG_COUNTER_INC(tx_frees); 3061 *mp = m; 3062 } 3063 } 3064 3065 /* 3066 * Determine where frame payload starts. 3067 * Jump over vlan headers if already present, 3068 * helpful for QinQ too. 3069 */ 3070 if (__predict_false(m->m_len < sizeof(*eh))) { 3071 txq->ift_pullups++; 3072 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3073 return (ENOMEM); 3074 } 3075 eh = mtod(m, struct ether_vlan_header *); 3076 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3077 pi->ipi_etype = ntohs(eh->evl_proto); 3078 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3079 } else { 3080 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3081 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3082 } 3083 3084 switch (pi->ipi_etype) { 3085 #ifdef INET 3086 case ETHERTYPE_IP: 3087 { 3088 struct mbuf *n; 3089 struct ip *ip = NULL; 3090 struct tcphdr *th = NULL; 3091 int minthlen; 3092 3093 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3094 if (__predict_false(m->m_len < minthlen)) { 3095 /* 3096 * if this code bloat is causing too much of a hit 3097 * move it to a separate function and mark it noinline 3098 */ 3099 if (m->m_len == pi->ipi_ehdrlen) { 3100 n = m->m_next; 3101 MPASS(n); 3102 if (n->m_len >= sizeof(*ip)) { 3103 ip = (struct ip *)n->m_data; 3104 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3105 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3106 } else { 3107 txq->ift_pullups++; 3108 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3109 return (ENOMEM); 3110 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3111 } 3112 } else { 3113 txq->ift_pullups++; 3114 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3115 return (ENOMEM); 3116 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3117 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3118 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3119 } 3120 } else { 3121 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3122 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3123 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3124 } 3125 pi->ipi_ip_hlen = ip->ip_hl << 2; 3126 pi->ipi_ipproto = ip->ip_p; 3127 pi->ipi_flags |= IPI_TX_IPV4; 3128 3129 /* TCP checksum offload may require TCP header length */ 3130 if (IS_TX_OFFLOAD4(pi)) { 3131 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3132 if (__predict_false(th == NULL)) { 3133 txq->ift_pullups++; 3134 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3135 return (ENOMEM); 3136 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3137 } 3138 pi->ipi_tcp_hflags = th->th_flags; 3139 pi->ipi_tcp_hlen = th->th_off << 2; 3140 pi->ipi_tcp_seq = th->th_seq; 3141 } 3142 if (IS_TSO4(pi)) { 3143 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3144 return (ENXIO); 3145 /* 3146 * TSO always requires hardware checksum offload. 3147 */ 3148 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3149 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3150 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3151 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3152 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3153 ip->ip_sum = 0; 3154 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3155 } 3156 } 3157 } 3158 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3159 ip->ip_sum = 0; 3160 3161 break; 3162 } 3163 #endif 3164 #ifdef INET6 3165 case ETHERTYPE_IPV6: 3166 { 3167 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3168 struct tcphdr *th; 3169 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3170 3171 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3172 txq->ift_pullups++; 3173 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3174 return (ENOMEM); 3175 } 3176 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3177 3178 /* XXX-BZ this will go badly in case of ext hdrs. */ 3179 pi->ipi_ipproto = ip6->ip6_nxt; 3180 pi->ipi_flags |= IPI_TX_IPV6; 3181 3182 /* TCP checksum offload may require TCP header length */ 3183 if (IS_TX_OFFLOAD6(pi)) { 3184 if (pi->ipi_ipproto == IPPROTO_TCP) { 3185 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3186 txq->ift_pullups++; 3187 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3188 return (ENOMEM); 3189 } 3190 pi->ipi_tcp_hflags = th->th_flags; 3191 pi->ipi_tcp_hlen = th->th_off << 2; 3192 pi->ipi_tcp_seq = th->th_seq; 3193 } 3194 if (IS_TSO6(pi)) { 3195 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3196 return (ENXIO); 3197 /* 3198 * TSO always requires hardware checksum offload. 3199 */ 3200 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3201 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3202 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3203 } 3204 } 3205 break; 3206 } 3207 #endif 3208 default: 3209 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3210 pi->ipi_ip_hlen = 0; 3211 break; 3212 } 3213 *mp = m; 3214 3215 return (0); 3216 } 3217 3218 /* 3219 * If dodgy hardware rejects the scatter gather chain we've handed it 3220 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3221 * m_defrag'd mbufs 3222 */ 3223 static __noinline struct mbuf * 3224 iflib_remove_mbuf(iflib_txq_t txq) 3225 { 3226 int ntxd, pidx; 3227 struct mbuf *m, **ifsd_m; 3228 3229 ifsd_m = txq->ift_sds.ifsd_m; 3230 ntxd = txq->ift_size; 3231 pidx = txq->ift_pidx & (ntxd - 1); 3232 ifsd_m = txq->ift_sds.ifsd_m; 3233 m = ifsd_m[pidx]; 3234 ifsd_m[pidx] = NULL; 3235 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3236 if (txq->ift_sds.ifsd_tso_map != NULL) 3237 bus_dmamap_unload(txq->ift_tso_buf_tag, 3238 txq->ift_sds.ifsd_tso_map[pidx]); 3239 #if MEMORY_LOGGING 3240 txq->ift_dequeued++; 3241 #endif 3242 return (m); 3243 } 3244 3245 static inline caddr_t 3246 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3247 { 3248 qidx_t size; 3249 int ntxd; 3250 caddr_t start, end, cur, next; 3251 3252 ntxd = txq->ift_size; 3253 size = txq->ift_txd_size[qid]; 3254 start = txq->ift_ifdi[qid].idi_vaddr; 3255 3256 if (__predict_false(size == 0)) 3257 return (start); 3258 cur = start + size*cidx; 3259 end = start + size*ntxd; 3260 next = CACHE_PTR_NEXT(cur); 3261 return (next < end ? next : start); 3262 } 3263 3264 /* 3265 * Pad an mbuf to ensure a minimum ethernet frame size. 3266 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3267 */ 3268 static __noinline int 3269 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3270 { 3271 /* 3272 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3273 * and ARP message is the smallest common payload I can think of 3274 */ 3275 static char pad[18]; /* just zeros */ 3276 int n; 3277 struct mbuf *new_head; 3278 3279 if (!M_WRITABLE(*m_head)) { 3280 new_head = m_dup(*m_head, M_NOWAIT); 3281 if (new_head == NULL) { 3282 m_freem(*m_head); 3283 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3284 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3285 DBG_COUNTER_INC(tx_frees); 3286 return ENOMEM; 3287 } 3288 m_freem(*m_head); 3289 *m_head = new_head; 3290 } 3291 3292 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3293 n > 0; n -= sizeof(pad)) 3294 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3295 break; 3296 3297 if (n > 0) { 3298 m_freem(*m_head); 3299 device_printf(dev, "cannot pad short frame\n"); 3300 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3301 DBG_COUNTER_INC(tx_frees); 3302 return (ENOBUFS); 3303 } 3304 3305 return 0; 3306 } 3307 3308 static int 3309 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3310 { 3311 if_ctx_t ctx; 3312 if_shared_ctx_t sctx; 3313 if_softc_ctx_t scctx; 3314 bus_dma_tag_t buf_tag; 3315 bus_dma_segment_t *segs; 3316 struct mbuf *m_head, **ifsd_m; 3317 void *next_txd; 3318 bus_dmamap_t map; 3319 struct if_pkt_info pi; 3320 int remap = 0; 3321 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3322 3323 ctx = txq->ift_ctx; 3324 sctx = ctx->ifc_sctx; 3325 scctx = &ctx->ifc_softc_ctx; 3326 segs = txq->ift_segs; 3327 ntxd = txq->ift_size; 3328 m_head = *m_headp; 3329 map = NULL; 3330 3331 /* 3332 * If we're doing TSO the next descriptor to clean may be quite far ahead 3333 */ 3334 cidx = txq->ift_cidx; 3335 pidx = txq->ift_pidx; 3336 if (ctx->ifc_flags & IFC_PREFETCH) { 3337 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3338 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3339 next_txd = calc_next_txd(txq, cidx, 0); 3340 prefetch(next_txd); 3341 } 3342 3343 /* prefetch the next cache line of mbuf pointers and flags */ 3344 prefetch(&txq->ift_sds.ifsd_m[next]); 3345 prefetch(&txq->ift_sds.ifsd_map[next]); 3346 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3347 } 3348 map = txq->ift_sds.ifsd_map[pidx]; 3349 ifsd_m = txq->ift_sds.ifsd_m; 3350 3351 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3352 buf_tag = txq->ift_tso_buf_tag; 3353 max_segs = scctx->isc_tx_tso_segments_max; 3354 map = txq->ift_sds.ifsd_tso_map[pidx]; 3355 MPASS(buf_tag != NULL); 3356 MPASS(max_segs > 0); 3357 } else { 3358 buf_tag = txq->ift_buf_tag; 3359 max_segs = scctx->isc_tx_nsegments; 3360 map = txq->ift_sds.ifsd_map[pidx]; 3361 } 3362 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3363 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3364 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3365 if (err) { 3366 DBG_COUNTER_INC(encap_txd_encap_fail); 3367 return err; 3368 } 3369 } 3370 m_head = *m_headp; 3371 3372 pkt_info_zero(&pi); 3373 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3374 pi.ipi_pidx = pidx; 3375 pi.ipi_qsidx = txq->ift_id; 3376 pi.ipi_len = m_head->m_pkthdr.len; 3377 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3378 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3379 3380 /* deliberate bitwise OR to make one condition */ 3381 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3382 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3383 DBG_COUNTER_INC(encap_txd_encap_fail); 3384 return (err); 3385 } 3386 m_head = *m_headp; 3387 } 3388 3389 retry: 3390 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3391 BUS_DMA_NOWAIT); 3392 defrag: 3393 if (__predict_false(err)) { 3394 switch (err) { 3395 case EFBIG: 3396 /* try collapse once and defrag once */ 3397 if (remap == 0) { 3398 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3399 /* try defrag if collapsing fails */ 3400 if (m_head == NULL) 3401 remap++; 3402 } 3403 if (remap == 1) { 3404 txq->ift_mbuf_defrag++; 3405 m_head = m_defrag(*m_headp, M_NOWAIT); 3406 } 3407 /* 3408 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3409 * failed to map an mbuf that was run through m_defrag 3410 */ 3411 MPASS(remap <= 1); 3412 if (__predict_false(m_head == NULL || remap > 1)) 3413 goto defrag_failed; 3414 remap++; 3415 *m_headp = m_head; 3416 goto retry; 3417 break; 3418 case ENOMEM: 3419 txq->ift_no_tx_dma_setup++; 3420 break; 3421 default: 3422 txq->ift_no_tx_dma_setup++; 3423 m_freem(*m_headp); 3424 DBG_COUNTER_INC(tx_frees); 3425 *m_headp = NULL; 3426 break; 3427 } 3428 txq->ift_map_failed++; 3429 DBG_COUNTER_INC(encap_load_mbuf_fail); 3430 DBG_COUNTER_INC(encap_txd_encap_fail); 3431 return (err); 3432 } 3433 ifsd_m[pidx] = m_head; 3434 /* 3435 * XXX assumes a 1 to 1 relationship between segments and 3436 * descriptors - this does not hold true on all drivers, e.g. 3437 * cxgb 3438 */ 3439 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3440 txq->ift_no_desc_avail++; 3441 bus_dmamap_unload(buf_tag, map); 3442 DBG_COUNTER_INC(encap_txq_avail_fail); 3443 DBG_COUNTER_INC(encap_txd_encap_fail); 3444 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3445 GROUPTASK_ENQUEUE(&txq->ift_task); 3446 return (ENOBUFS); 3447 } 3448 /* 3449 * On Intel cards we can greatly reduce the number of TX interrupts 3450 * we see by only setting report status on every Nth descriptor. 3451 * However, this also means that the driver will need to keep track 3452 * of the descriptors that RS was set on to check them for the DD bit. 3453 */ 3454 txq->ift_rs_pending += nsegs + 1; 3455 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3456 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3457 pi.ipi_flags |= IPI_TX_INTR; 3458 txq->ift_rs_pending = 0; 3459 } 3460 3461 pi.ipi_segs = segs; 3462 pi.ipi_nsegs = nsegs; 3463 3464 MPASS(pidx >= 0 && pidx < txq->ift_size); 3465 #ifdef PKT_DEBUG 3466 print_pkt(&pi); 3467 #endif 3468 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3469 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3470 DBG_COUNTER_INC(tx_encap); 3471 MPASS(pi.ipi_new_pidx < txq->ift_size); 3472 3473 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3474 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3475 ndesc += txq->ift_size; 3476 txq->ift_gen = 1; 3477 } 3478 /* 3479 * drivers can need as many as 3480 * two sentinels 3481 */ 3482 MPASS(ndesc <= pi.ipi_nsegs + 2); 3483 MPASS(pi.ipi_new_pidx != pidx); 3484 MPASS(ndesc > 0); 3485 txq->ift_in_use += ndesc; 3486 3487 /* 3488 * We update the last software descriptor again here because there may 3489 * be a sentinel and/or there may be more mbufs than segments 3490 */ 3491 txq->ift_pidx = pi.ipi_new_pidx; 3492 txq->ift_npending += pi.ipi_ndescs; 3493 } else { 3494 *m_headp = m_head = iflib_remove_mbuf(txq); 3495 if (err == EFBIG) { 3496 txq->ift_txd_encap_efbig++; 3497 if (remap < 2) { 3498 remap = 1; 3499 goto defrag; 3500 } 3501 } 3502 goto defrag_failed; 3503 } 3504 /* 3505 * err can't possibly be non-zero here, so we don't neet to test it 3506 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3507 */ 3508 return (err); 3509 3510 defrag_failed: 3511 txq->ift_mbuf_defrag_failed++; 3512 txq->ift_map_failed++; 3513 m_freem(*m_headp); 3514 DBG_COUNTER_INC(tx_frees); 3515 *m_headp = NULL; 3516 DBG_COUNTER_INC(encap_txd_encap_fail); 3517 return (ENOMEM); 3518 } 3519 3520 static void 3521 iflib_tx_desc_free(iflib_txq_t txq, int n) 3522 { 3523 uint32_t qsize, cidx, mask, gen; 3524 struct mbuf *m, **ifsd_m; 3525 bool do_prefetch; 3526 3527 cidx = txq->ift_cidx; 3528 gen = txq->ift_gen; 3529 qsize = txq->ift_size; 3530 mask = qsize-1; 3531 ifsd_m = txq->ift_sds.ifsd_m; 3532 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3533 3534 while (n-- > 0) { 3535 if (do_prefetch) { 3536 prefetch(ifsd_m[(cidx + 3) & mask]); 3537 prefetch(ifsd_m[(cidx + 4) & mask]); 3538 } 3539 if ((m = ifsd_m[cidx]) != NULL) { 3540 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3541 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3542 bus_dmamap_sync(txq->ift_tso_buf_tag, 3543 txq->ift_sds.ifsd_tso_map[cidx], 3544 BUS_DMASYNC_POSTWRITE); 3545 bus_dmamap_unload(txq->ift_tso_buf_tag, 3546 txq->ift_sds.ifsd_tso_map[cidx]); 3547 } else { 3548 bus_dmamap_sync(txq->ift_buf_tag, 3549 txq->ift_sds.ifsd_map[cidx], 3550 BUS_DMASYNC_POSTWRITE); 3551 bus_dmamap_unload(txq->ift_buf_tag, 3552 txq->ift_sds.ifsd_map[cidx]); 3553 } 3554 /* XXX we don't support any drivers that batch packets yet */ 3555 MPASS(m->m_nextpkt == NULL); 3556 m_freem(m); 3557 ifsd_m[cidx] = NULL; 3558 #if MEMORY_LOGGING 3559 txq->ift_dequeued++; 3560 #endif 3561 DBG_COUNTER_INC(tx_frees); 3562 } 3563 if (__predict_false(++cidx == qsize)) { 3564 cidx = 0; 3565 gen = 0; 3566 } 3567 } 3568 txq->ift_cidx = cidx; 3569 txq->ift_gen = gen; 3570 } 3571 3572 static __inline int 3573 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3574 { 3575 int reclaim; 3576 if_ctx_t ctx = txq->ift_ctx; 3577 3578 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3579 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3580 3581 /* 3582 * Need a rate-limiting check so that this isn't called every time 3583 */ 3584 iflib_tx_credits_update(ctx, txq); 3585 reclaim = DESC_RECLAIMABLE(txq); 3586 3587 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3588 #ifdef INVARIANTS 3589 if (iflib_verbose_debug) { 3590 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3591 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3592 reclaim, thresh); 3593 } 3594 #endif 3595 return (0); 3596 } 3597 iflib_tx_desc_free(txq, reclaim); 3598 txq->ift_cleaned += reclaim; 3599 txq->ift_in_use -= reclaim; 3600 3601 return (reclaim); 3602 } 3603 3604 static struct mbuf ** 3605 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3606 { 3607 int next, size; 3608 struct mbuf **items; 3609 3610 size = r->size; 3611 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3612 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3613 3614 prefetch(items[(cidx + offset) & (size-1)]); 3615 if (remaining > 1) { 3616 prefetch2cachelines(&items[next]); 3617 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3618 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3619 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3620 } 3621 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3622 } 3623 3624 static void 3625 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3626 { 3627 3628 ifmp_ring_check_drainage(txq->ift_br, budget); 3629 } 3630 3631 static uint32_t 3632 iflib_txq_can_drain(struct ifmp_ring *r) 3633 { 3634 iflib_txq_t txq = r->cookie; 3635 if_ctx_t ctx = txq->ift_ctx; 3636 3637 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3638 return (1); 3639 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3640 BUS_DMASYNC_POSTREAD); 3641 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3642 false)); 3643 } 3644 3645 static uint32_t 3646 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3647 { 3648 iflib_txq_t txq = r->cookie; 3649 if_ctx_t ctx = txq->ift_ctx; 3650 if_t ifp = ctx->ifc_ifp; 3651 struct mbuf *m, **mp; 3652 int avail, bytes_sent, consumed, count, err, i, in_use_prev; 3653 int mcast_sent, pkt_sent, reclaimed, txq_avail; 3654 bool do_prefetch, rang, ring; 3655 3656 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3657 !LINK_ACTIVE(ctx))) { 3658 DBG_COUNTER_INC(txq_drain_notready); 3659 return (0); 3660 } 3661 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3662 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3663 avail = IDXDIFF(pidx, cidx, r->size); 3664 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3665 DBG_COUNTER_INC(txq_drain_flushing); 3666 for (i = 0; i < avail; i++) { 3667 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3668 m_free(r->items[(cidx + i) & (r->size-1)]); 3669 r->items[(cidx + i) & (r->size-1)] = NULL; 3670 } 3671 return (avail); 3672 } 3673 3674 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3675 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3676 CALLOUT_LOCK(txq); 3677 callout_stop(&txq->ift_timer); 3678 CALLOUT_UNLOCK(txq); 3679 DBG_COUNTER_INC(txq_drain_oactive); 3680 return (0); 3681 } 3682 if (reclaimed) 3683 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3684 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3685 count = MIN(avail, TX_BATCH_SIZE); 3686 #ifdef INVARIANTS 3687 if (iflib_verbose_debug) 3688 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3689 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3690 #endif 3691 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3692 txq_avail = TXQ_AVAIL(txq); 3693 err = 0; 3694 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) { 3695 int rem = do_prefetch ? count - i : 0; 3696 3697 mp = _ring_peek_one(r, cidx, i, rem); 3698 MPASS(mp != NULL && *mp != NULL); 3699 if (__predict_false(*mp == (struct mbuf *)txq)) { 3700 consumed++; 3701 continue; 3702 } 3703 in_use_prev = txq->ift_in_use; 3704 err = iflib_encap(txq, mp); 3705 if (__predict_false(err)) { 3706 /* no room - bail out */ 3707 if (err == ENOBUFS) 3708 break; 3709 consumed++; 3710 /* we can't send this packet - skip it */ 3711 continue; 3712 } 3713 consumed++; 3714 pkt_sent++; 3715 m = *mp; 3716 DBG_COUNTER_INC(tx_sent); 3717 bytes_sent += m->m_pkthdr.len; 3718 mcast_sent += !!(m->m_flags & M_MCAST); 3719 txq_avail = TXQ_AVAIL(txq); 3720 3721 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3722 ETHER_BPF_MTAP(ifp, m); 3723 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3724 break; 3725 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3726 } 3727 3728 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3729 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3730 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3731 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3732 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3733 if (mcast_sent) 3734 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3735 #ifdef INVARIANTS 3736 if (iflib_verbose_debug) 3737 printf("consumed=%d\n", consumed); 3738 #endif 3739 return (consumed); 3740 } 3741 3742 static uint32_t 3743 iflib_txq_drain_always(struct ifmp_ring *r) 3744 { 3745 return (1); 3746 } 3747 3748 static uint32_t 3749 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3750 { 3751 int i, avail; 3752 struct mbuf **mp; 3753 iflib_txq_t txq; 3754 3755 txq = r->cookie; 3756 3757 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3758 CALLOUT_LOCK(txq); 3759 callout_stop(&txq->ift_timer); 3760 CALLOUT_UNLOCK(txq); 3761 3762 avail = IDXDIFF(pidx, cidx, r->size); 3763 for (i = 0; i < avail; i++) { 3764 mp = _ring_peek_one(r, cidx, i, avail - i); 3765 if (__predict_false(*mp == (struct mbuf *)txq)) 3766 continue; 3767 m_freem(*mp); 3768 DBG_COUNTER_INC(tx_frees); 3769 } 3770 MPASS(ifmp_ring_is_stalled(r) == 0); 3771 return (avail); 3772 } 3773 3774 static void 3775 iflib_ifmp_purge(iflib_txq_t txq) 3776 { 3777 struct ifmp_ring *r; 3778 3779 r = txq->ift_br; 3780 r->drain = iflib_txq_drain_free; 3781 r->can_drain = iflib_txq_drain_always; 3782 3783 ifmp_ring_check_drainage(r, r->size); 3784 3785 r->drain = iflib_txq_drain; 3786 r->can_drain = iflib_txq_can_drain; 3787 } 3788 3789 static void 3790 _task_fn_tx(void *context) 3791 { 3792 iflib_txq_t txq = context; 3793 if_ctx_t ctx = txq->ift_ctx; 3794 if_t ifp = ctx->ifc_ifp; 3795 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3796 3797 #ifdef IFLIB_DIAGNOSTICS 3798 txq->ift_cpu_exec_count[curcpu]++; 3799 #endif 3800 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 3801 return; 3802 #ifdef DEV_NETMAP 3803 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 3804 netmap_tx_irq(ifp, txq->ift_id)) 3805 goto skip_ifmp; 3806 #endif 3807 #ifdef ALTQ 3808 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3809 iflib_altq_if_start(ifp); 3810 #endif 3811 if (txq->ift_db_pending) 3812 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3813 else if (!abdicate) 3814 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3815 /* 3816 * When abdicating, we always need to check drainage, not just when we don't enqueue 3817 */ 3818 if (abdicate) 3819 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3820 #ifdef DEV_NETMAP 3821 skip_ifmp: 3822 #endif 3823 if (ctx->ifc_flags & IFC_LEGACY) 3824 IFDI_INTR_ENABLE(ctx); 3825 else 3826 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3827 } 3828 3829 static void 3830 _task_fn_rx(void *context) 3831 { 3832 iflib_rxq_t rxq = context; 3833 if_ctx_t ctx = rxq->ifr_ctx; 3834 uint8_t more; 3835 uint16_t budget; 3836 #ifdef DEV_NETMAP 3837 u_int work = 0; 3838 int nmirq; 3839 #endif 3840 3841 #ifdef IFLIB_DIAGNOSTICS 3842 rxq->ifr_cpu_exec_count[curcpu]++; 3843 #endif 3844 DBG_COUNTER_INC(task_fn_rxs); 3845 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3846 return; 3847 #ifdef DEV_NETMAP 3848 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 3849 if (nmirq != NM_IRQ_PASS) { 3850 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 3851 goto skip_rxeof; 3852 } 3853 #endif 3854 budget = ctx->ifc_sysctl_rx_budget; 3855 if (budget == 0) 3856 budget = 16; /* XXX */ 3857 more = iflib_rxeof(rxq, budget); 3858 #ifdef DEV_NETMAP 3859 skip_rxeof: 3860 #endif 3861 if ((more & IFLIB_RXEOF_MORE) == 0) { 3862 if (ctx->ifc_flags & IFC_LEGACY) 3863 IFDI_INTR_ENABLE(ctx); 3864 else 3865 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3866 DBG_COUNTER_INC(rx_intr_enables); 3867 } 3868 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3869 return; 3870 3871 if (more & IFLIB_RXEOF_MORE) 3872 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3873 else if (more & IFLIB_RXEOF_EMPTY) 3874 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 3875 } 3876 3877 static void 3878 _task_fn_admin(void *context) 3879 { 3880 if_ctx_t ctx = context; 3881 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3882 iflib_txq_t txq; 3883 int i; 3884 bool oactive, running, do_reset, do_watchdog, in_detach; 3885 uint32_t reset_on = hz / 2; 3886 3887 STATE_LOCK(ctx); 3888 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3889 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3890 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3891 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3892 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3893 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3894 STATE_UNLOCK(ctx); 3895 3896 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3897 return; 3898 if (in_detach) 3899 return; 3900 3901 CTX_LOCK(ctx); 3902 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3903 CALLOUT_LOCK(txq); 3904 callout_stop(&txq->ift_timer); 3905 CALLOUT_UNLOCK(txq); 3906 } 3907 if (do_watchdog) { 3908 ctx->ifc_watchdog_events++; 3909 IFDI_WATCHDOG_RESET(ctx); 3910 } 3911 IFDI_UPDATE_ADMIN_STATUS(ctx); 3912 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3913 #ifdef DEV_NETMAP 3914 reset_on = hz / 2; 3915 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3916 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 3917 #endif 3918 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3919 } 3920 IFDI_LINK_INTR_ENABLE(ctx); 3921 if (do_reset) 3922 iflib_if_init_locked(ctx); 3923 CTX_UNLOCK(ctx); 3924 3925 if (LINK_ACTIVE(ctx) == 0) 3926 return; 3927 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3928 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3929 } 3930 3931 static void 3932 _task_fn_iov(void *context) 3933 { 3934 if_ctx_t ctx = context; 3935 3936 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3937 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3938 return; 3939 3940 CTX_LOCK(ctx); 3941 IFDI_VFLR_HANDLE(ctx); 3942 CTX_UNLOCK(ctx); 3943 } 3944 3945 static int 3946 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3947 { 3948 int err; 3949 if_int_delay_info_t info; 3950 if_ctx_t ctx; 3951 3952 info = (if_int_delay_info_t)arg1; 3953 ctx = info->iidi_ctx; 3954 info->iidi_req = req; 3955 info->iidi_oidp = oidp; 3956 CTX_LOCK(ctx); 3957 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3958 CTX_UNLOCK(ctx); 3959 return (err); 3960 } 3961 3962 /********************************************************************* 3963 * 3964 * IFNET FUNCTIONS 3965 * 3966 **********************************************************************/ 3967 3968 static void 3969 iflib_if_init_locked(if_ctx_t ctx) 3970 { 3971 iflib_stop(ctx); 3972 iflib_init_locked(ctx); 3973 } 3974 3975 static void 3976 iflib_if_init(void *arg) 3977 { 3978 if_ctx_t ctx = arg; 3979 3980 CTX_LOCK(ctx); 3981 iflib_if_init_locked(ctx); 3982 CTX_UNLOCK(ctx); 3983 } 3984 3985 static int 3986 iflib_if_transmit(if_t ifp, struct mbuf *m) 3987 { 3988 if_ctx_t ctx = if_getsoftc(ifp); 3989 3990 iflib_txq_t txq; 3991 int err, qidx; 3992 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3993 3994 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3995 DBG_COUNTER_INC(tx_frees); 3996 m_freem(m); 3997 return (ENETDOWN); 3998 } 3999 4000 MPASS(m->m_nextpkt == NULL); 4001 /* ALTQ-enabled interfaces always use queue 0. */ 4002 qidx = 0; 4003 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 4004 qidx = QIDX(ctx, m); 4005 /* 4006 * XXX calculate buf_ring based on flowid (divvy up bits?) 4007 */ 4008 txq = &ctx->ifc_txqs[qidx]; 4009 4010 #ifdef DRIVER_BACKPRESSURE 4011 if (txq->ift_closed) { 4012 while (m != NULL) { 4013 next = m->m_nextpkt; 4014 m->m_nextpkt = NULL; 4015 m_freem(m); 4016 DBG_COUNTER_INC(tx_frees); 4017 m = next; 4018 } 4019 return (ENOBUFS); 4020 } 4021 #endif 4022 #ifdef notyet 4023 qidx = count = 0; 4024 mp = marr; 4025 next = m; 4026 do { 4027 count++; 4028 next = next->m_nextpkt; 4029 } while (next != NULL); 4030 4031 if (count > nitems(marr)) 4032 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4033 /* XXX check nextpkt */ 4034 m_freem(m); 4035 /* XXX simplify for now */ 4036 DBG_COUNTER_INC(tx_frees); 4037 return (ENOBUFS); 4038 } 4039 for (next = m, i = 0; next != NULL; i++) { 4040 mp[i] = next; 4041 next = next->m_nextpkt; 4042 mp[i]->m_nextpkt = NULL; 4043 } 4044 #endif 4045 DBG_COUNTER_INC(tx_seen); 4046 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4047 4048 if (abdicate) 4049 GROUPTASK_ENQUEUE(&txq->ift_task); 4050 if (err) { 4051 if (!abdicate) 4052 GROUPTASK_ENQUEUE(&txq->ift_task); 4053 /* support forthcoming later */ 4054 #ifdef DRIVER_BACKPRESSURE 4055 txq->ift_closed = TRUE; 4056 #endif 4057 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4058 m_freem(m); 4059 DBG_COUNTER_INC(tx_frees); 4060 } 4061 4062 return (err); 4063 } 4064 4065 #ifdef ALTQ 4066 /* 4067 * The overall approach to integrating iflib with ALTQ is to continue to use 4068 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4069 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4070 * is redundant/unnecessary, but doing so minimizes the amount of 4071 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4072 * redundantly queueing to an intermediate mp_ring is swamped by the 4073 * performance limitations inherent in using ALTQ. 4074 * 4075 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4076 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4077 * given interface. If ALTQ is enabled for an interface, then all 4078 * transmitted packets for that interface will be submitted to the ALTQ 4079 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4080 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4081 * update stats that the iflib machinery handles, and which is sensitve to 4082 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4083 * will be installed as the start routine for use by ALTQ facilities that 4084 * need to trigger queue drains on a scheduled basis. 4085 * 4086 */ 4087 static void 4088 iflib_altq_if_start(if_t ifp) 4089 { 4090 struct ifaltq *ifq = &ifp->if_snd; 4091 struct mbuf *m; 4092 4093 IFQ_LOCK(ifq); 4094 IFQ_DEQUEUE_NOLOCK(ifq, m); 4095 while (m != NULL) { 4096 iflib_if_transmit(ifp, m); 4097 IFQ_DEQUEUE_NOLOCK(ifq, m); 4098 } 4099 IFQ_UNLOCK(ifq); 4100 } 4101 4102 static int 4103 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4104 { 4105 int err; 4106 4107 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4108 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4109 if (err == 0) 4110 iflib_altq_if_start(ifp); 4111 } else 4112 err = iflib_if_transmit(ifp, m); 4113 4114 return (err); 4115 } 4116 #endif /* ALTQ */ 4117 4118 static void 4119 iflib_if_qflush(if_t ifp) 4120 { 4121 if_ctx_t ctx = if_getsoftc(ifp); 4122 iflib_txq_t txq = ctx->ifc_txqs; 4123 int i; 4124 4125 STATE_LOCK(ctx); 4126 ctx->ifc_flags |= IFC_QFLUSH; 4127 STATE_UNLOCK(ctx); 4128 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4129 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4130 iflib_txq_check_drain(txq, 0); 4131 STATE_LOCK(ctx); 4132 ctx->ifc_flags &= ~IFC_QFLUSH; 4133 STATE_UNLOCK(ctx); 4134 4135 /* 4136 * When ALTQ is enabled, this will also take care of purging the 4137 * ALTQ queue(s). 4138 */ 4139 if_qflush(ifp); 4140 } 4141 4142 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4143 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4144 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4145 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP) 4146 4147 static int 4148 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4149 { 4150 if_ctx_t ctx = if_getsoftc(ifp); 4151 struct ifreq *ifr = (struct ifreq *)data; 4152 #if defined(INET) || defined(INET6) 4153 struct ifaddr *ifa = (struct ifaddr *)data; 4154 #endif 4155 bool avoid_reset = false; 4156 int err = 0, reinit = 0, bits; 4157 4158 switch (command) { 4159 case SIOCSIFADDR: 4160 #ifdef INET 4161 if (ifa->ifa_addr->sa_family == AF_INET) 4162 avoid_reset = true; 4163 #endif 4164 #ifdef INET6 4165 if (ifa->ifa_addr->sa_family == AF_INET6) 4166 avoid_reset = true; 4167 #endif 4168 /* 4169 ** Calling init results in link renegotiation, 4170 ** so we avoid doing it when possible. 4171 */ 4172 if (avoid_reset) { 4173 if_setflagbits(ifp, IFF_UP,0); 4174 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4175 reinit = 1; 4176 #ifdef INET 4177 if (!(if_getflags(ifp) & IFF_NOARP)) 4178 arp_ifinit(ifp, ifa); 4179 #endif 4180 } else 4181 err = ether_ioctl(ifp, command, data); 4182 break; 4183 case SIOCSIFMTU: 4184 CTX_LOCK(ctx); 4185 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4186 CTX_UNLOCK(ctx); 4187 break; 4188 } 4189 bits = if_getdrvflags(ifp); 4190 /* stop the driver and free any clusters before proceeding */ 4191 iflib_stop(ctx); 4192 4193 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4194 STATE_LOCK(ctx); 4195 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4196 ctx->ifc_flags |= IFC_MULTISEG; 4197 else 4198 ctx->ifc_flags &= ~IFC_MULTISEG; 4199 STATE_UNLOCK(ctx); 4200 err = if_setmtu(ifp, ifr->ifr_mtu); 4201 } 4202 iflib_init_locked(ctx); 4203 STATE_LOCK(ctx); 4204 if_setdrvflags(ifp, bits); 4205 STATE_UNLOCK(ctx); 4206 CTX_UNLOCK(ctx); 4207 break; 4208 case SIOCSIFFLAGS: 4209 CTX_LOCK(ctx); 4210 if (if_getflags(ifp) & IFF_UP) { 4211 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4212 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4213 (IFF_PROMISC | IFF_ALLMULTI)) { 4214 CTX_UNLOCK(ctx); 4215 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4216 CTX_LOCK(ctx); 4217 } 4218 } else 4219 reinit = 1; 4220 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4221 iflib_stop(ctx); 4222 } 4223 ctx->ifc_if_flags = if_getflags(ifp); 4224 CTX_UNLOCK(ctx); 4225 break; 4226 case SIOCADDMULTI: 4227 case SIOCDELMULTI: 4228 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4229 CTX_LOCK(ctx); 4230 IFDI_INTR_DISABLE(ctx); 4231 IFDI_MULTI_SET(ctx); 4232 IFDI_INTR_ENABLE(ctx); 4233 CTX_UNLOCK(ctx); 4234 } 4235 break; 4236 case SIOCSIFMEDIA: 4237 CTX_LOCK(ctx); 4238 IFDI_MEDIA_SET(ctx); 4239 CTX_UNLOCK(ctx); 4240 /* FALLTHROUGH */ 4241 case SIOCGIFMEDIA: 4242 case SIOCGIFXMEDIA: 4243 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4244 break; 4245 case SIOCGI2C: 4246 { 4247 struct ifi2creq i2c; 4248 4249 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4250 if (err != 0) 4251 break; 4252 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4253 err = EINVAL; 4254 break; 4255 } 4256 if (i2c.len > sizeof(i2c.data)) { 4257 err = EINVAL; 4258 break; 4259 } 4260 4261 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4262 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4263 sizeof(i2c)); 4264 break; 4265 } 4266 case SIOCSIFCAP: 4267 { 4268 int mask, setmask, oldmask; 4269 4270 oldmask = if_getcapenable(ifp); 4271 mask = ifr->ifr_reqcap ^ oldmask; 4272 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP; 4273 setmask = 0; 4274 #ifdef TCP_OFFLOAD 4275 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4276 #endif 4277 setmask |= (mask & IFCAP_FLAGS); 4278 setmask |= (mask & IFCAP_WOL); 4279 4280 /* 4281 * If any RX csum has changed, change all the ones that 4282 * are supported by the driver. 4283 */ 4284 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4285 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4286 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4287 } 4288 4289 /* 4290 * want to ensure that traffic has stopped before we change any of the flags 4291 */ 4292 if (setmask) { 4293 CTX_LOCK(ctx); 4294 bits = if_getdrvflags(ifp); 4295 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4296 iflib_stop(ctx); 4297 STATE_LOCK(ctx); 4298 if_togglecapenable(ifp, setmask); 4299 STATE_UNLOCK(ctx); 4300 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4301 iflib_init_locked(ctx); 4302 STATE_LOCK(ctx); 4303 if_setdrvflags(ifp, bits); 4304 STATE_UNLOCK(ctx); 4305 CTX_UNLOCK(ctx); 4306 } 4307 if_vlancap(ifp); 4308 break; 4309 } 4310 case SIOCGPRIVATE_0: 4311 case SIOCSDRVSPEC: 4312 case SIOCGDRVSPEC: 4313 CTX_LOCK(ctx); 4314 err = IFDI_PRIV_IOCTL(ctx, command, data); 4315 CTX_UNLOCK(ctx); 4316 break; 4317 default: 4318 err = ether_ioctl(ifp, command, data); 4319 break; 4320 } 4321 if (reinit) 4322 iflib_if_init(ctx); 4323 return (err); 4324 } 4325 4326 static uint64_t 4327 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4328 { 4329 if_ctx_t ctx = if_getsoftc(ifp); 4330 4331 return (IFDI_GET_COUNTER(ctx, cnt)); 4332 } 4333 4334 /********************************************************************* 4335 * 4336 * OTHER FUNCTIONS EXPORTED TO THE STACK 4337 * 4338 **********************************************************************/ 4339 4340 static void 4341 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4342 { 4343 if_ctx_t ctx = if_getsoftc(ifp); 4344 4345 if ((void *)ctx != arg) 4346 return; 4347 4348 if ((vtag == 0) || (vtag > 4095)) 4349 return; 4350 4351 if (iflib_in_detach(ctx)) 4352 return; 4353 4354 CTX_LOCK(ctx); 4355 /* Driver may need all untagged packets to be flushed */ 4356 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4357 iflib_stop(ctx); 4358 IFDI_VLAN_REGISTER(ctx, vtag); 4359 /* Re-init to load the changes, if required */ 4360 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4361 iflib_init_locked(ctx); 4362 CTX_UNLOCK(ctx); 4363 } 4364 4365 static void 4366 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4367 { 4368 if_ctx_t ctx = if_getsoftc(ifp); 4369 4370 if ((void *)ctx != arg) 4371 return; 4372 4373 if ((vtag == 0) || (vtag > 4095)) 4374 return; 4375 4376 CTX_LOCK(ctx); 4377 /* Driver may need all tagged packets to be flushed */ 4378 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4379 iflib_stop(ctx); 4380 IFDI_VLAN_UNREGISTER(ctx, vtag); 4381 /* Re-init to load the changes, if required */ 4382 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4383 iflib_init_locked(ctx); 4384 CTX_UNLOCK(ctx); 4385 } 4386 4387 static void 4388 iflib_led_func(void *arg, int onoff) 4389 { 4390 if_ctx_t ctx = arg; 4391 4392 CTX_LOCK(ctx); 4393 IFDI_LED_FUNC(ctx, onoff); 4394 CTX_UNLOCK(ctx); 4395 } 4396 4397 /********************************************************************* 4398 * 4399 * BUS FUNCTION DEFINITIONS 4400 * 4401 **********************************************************************/ 4402 4403 int 4404 iflib_device_probe(device_t dev) 4405 { 4406 const pci_vendor_info_t *ent; 4407 if_shared_ctx_t sctx; 4408 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4409 uint16_t pci_vendor_id; 4410 4411 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4412 return (ENOTSUP); 4413 4414 pci_vendor_id = pci_get_vendor(dev); 4415 pci_device_id = pci_get_device(dev); 4416 pci_subvendor_id = pci_get_subvendor(dev); 4417 pci_subdevice_id = pci_get_subdevice(dev); 4418 pci_rev_id = pci_get_revid(dev); 4419 if (sctx->isc_parse_devinfo != NULL) 4420 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4421 4422 ent = sctx->isc_vendor_info; 4423 while (ent->pvi_vendor_id != 0) { 4424 if (pci_vendor_id != ent->pvi_vendor_id) { 4425 ent++; 4426 continue; 4427 } 4428 if ((pci_device_id == ent->pvi_device_id) && 4429 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4430 (ent->pvi_subvendor_id == 0)) && 4431 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4432 (ent->pvi_subdevice_id == 0)) && 4433 ((pci_rev_id == ent->pvi_rev_id) || 4434 (ent->pvi_rev_id == 0))) { 4435 device_set_desc_copy(dev, ent->pvi_name); 4436 /* this needs to be changed to zero if the bus probing code 4437 * ever stops re-probing on best match because the sctx 4438 * may have its values over written by register calls 4439 * in subsequent probes 4440 */ 4441 return (BUS_PROBE_DEFAULT); 4442 } 4443 ent++; 4444 } 4445 return (ENXIO); 4446 } 4447 4448 int 4449 iflib_device_probe_vendor(device_t dev) 4450 { 4451 int probe; 4452 4453 probe = iflib_device_probe(dev); 4454 if (probe == BUS_PROBE_DEFAULT) 4455 return (BUS_PROBE_VENDOR); 4456 else 4457 return (probe); 4458 } 4459 4460 static void 4461 iflib_reset_qvalues(if_ctx_t ctx) 4462 { 4463 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4464 if_shared_ctx_t sctx = ctx->ifc_sctx; 4465 device_t dev = ctx->ifc_dev; 4466 int i; 4467 4468 if (ctx->ifc_sysctl_ntxqs != 0) 4469 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4470 if (ctx->ifc_sysctl_nrxqs != 0) 4471 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4472 4473 for (i = 0; i < sctx->isc_ntxqs; i++) { 4474 if (ctx->ifc_sysctl_ntxds[i] != 0) 4475 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4476 else 4477 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4478 } 4479 4480 for (i = 0; i < sctx->isc_nrxqs; i++) { 4481 if (ctx->ifc_sysctl_nrxds[i] != 0) 4482 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4483 else 4484 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4485 } 4486 4487 for (i = 0; i < sctx->isc_nrxqs; i++) { 4488 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4489 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4490 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4491 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4492 } 4493 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4494 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4495 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4496 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4497 } 4498 if (!powerof2(scctx->isc_nrxd[i])) { 4499 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4500 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4501 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4502 } 4503 } 4504 4505 for (i = 0; i < sctx->isc_ntxqs; i++) { 4506 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4507 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4508 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4509 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4510 } 4511 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4512 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4513 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4514 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4515 } 4516 if (!powerof2(scctx->isc_ntxd[i])) { 4517 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4518 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4519 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4520 } 4521 } 4522 } 4523 4524 static void 4525 iflib_add_pfil(if_ctx_t ctx) 4526 { 4527 struct pfil_head *pfil; 4528 struct pfil_head_args pa; 4529 iflib_rxq_t rxq; 4530 int i; 4531 4532 pa.pa_version = PFIL_VERSION; 4533 pa.pa_flags = PFIL_IN; 4534 pa.pa_type = PFIL_TYPE_ETHERNET; 4535 pa.pa_headname = ctx->ifc_ifp->if_xname; 4536 pfil = pfil_head_register(&pa); 4537 4538 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4539 rxq->pfil = pfil; 4540 } 4541 } 4542 4543 static void 4544 iflib_rem_pfil(if_ctx_t ctx) 4545 { 4546 struct pfil_head *pfil; 4547 iflib_rxq_t rxq; 4548 int i; 4549 4550 rxq = ctx->ifc_rxqs; 4551 pfil = rxq->pfil; 4552 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4553 rxq->pfil = NULL; 4554 } 4555 pfil_head_unregister(pfil); 4556 } 4557 4558 static uint16_t 4559 get_ctx_core_offset(if_ctx_t ctx) 4560 { 4561 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4562 struct cpu_offset *op; 4563 uint16_t qc; 4564 uint16_t ret = ctx->ifc_sysctl_core_offset; 4565 4566 if (ret != CORE_OFFSET_UNSPECIFIED) 4567 return (ret); 4568 4569 if (ctx->ifc_sysctl_separate_txrx) 4570 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets; 4571 else 4572 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets); 4573 4574 mtx_lock(&cpu_offset_mtx); 4575 SLIST_FOREACH(op, &cpu_offsets, entries) { 4576 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4577 ret = op->offset; 4578 op->offset += qc; 4579 MPASS(op->refcount < UINT_MAX); 4580 op->refcount++; 4581 break; 4582 } 4583 } 4584 if (ret == CORE_OFFSET_UNSPECIFIED) { 4585 ret = 0; 4586 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4587 M_NOWAIT | M_ZERO); 4588 if (op == NULL) { 4589 device_printf(ctx->ifc_dev, 4590 "allocation for cpu offset failed.\n"); 4591 } else { 4592 op->offset = qc; 4593 op->refcount = 1; 4594 CPU_COPY(&ctx->ifc_cpus, &op->set); 4595 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4596 } 4597 } 4598 mtx_unlock(&cpu_offset_mtx); 4599 4600 return (ret); 4601 } 4602 4603 static void 4604 unref_ctx_core_offset(if_ctx_t ctx) 4605 { 4606 struct cpu_offset *op, *top; 4607 4608 mtx_lock(&cpu_offset_mtx); 4609 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4610 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4611 MPASS(op->refcount > 0); 4612 op->refcount--; 4613 if (op->refcount == 0) { 4614 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4615 free(op, M_IFLIB); 4616 } 4617 break; 4618 } 4619 } 4620 mtx_unlock(&cpu_offset_mtx); 4621 } 4622 4623 int 4624 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4625 { 4626 if_ctx_t ctx; 4627 if_t ifp; 4628 if_softc_ctx_t scctx; 4629 kobjop_desc_t kobj_desc; 4630 kobj_method_t *kobj_method; 4631 int err, msix, rid; 4632 int num_txd, num_rxd; 4633 4634 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4635 4636 if (sc == NULL) { 4637 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4638 device_set_softc(dev, ctx); 4639 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4640 } 4641 4642 ctx->ifc_sctx = sctx; 4643 ctx->ifc_dev = dev; 4644 ctx->ifc_softc = sc; 4645 4646 if ((err = iflib_register(ctx)) != 0) { 4647 device_printf(dev, "iflib_register failed %d\n", err); 4648 goto fail_ctx_free; 4649 } 4650 iflib_add_device_sysctl_pre(ctx); 4651 4652 scctx = &ctx->ifc_softc_ctx; 4653 ifp = ctx->ifc_ifp; 4654 4655 iflib_reset_qvalues(ctx); 4656 CTX_LOCK(ctx); 4657 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4658 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4659 goto fail_unlock; 4660 } 4661 _iflib_pre_assert(scctx); 4662 ctx->ifc_txrx = *scctx->isc_txrx; 4663 4664 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 4665 ctx->ifc_mediap = scctx->isc_media; 4666 4667 #ifdef INVARIANTS 4668 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4669 MPASS(scctx->isc_tx_csum_flags); 4670 #endif 4671 4672 if_setcapabilities(ifp, 4673 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP); 4674 if_setcapenable(ifp, 4675 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP); 4676 4677 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4678 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4679 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4680 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4681 4682 num_txd = iflib_num_tx_descs(ctx); 4683 num_rxd = iflib_num_rx_descs(ctx); 4684 4685 /* XXX change for per-queue sizes */ 4686 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4687 num_txd, num_rxd); 4688 4689 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 4690 scctx->isc_tx_nsegments = max(1, num_txd / 4691 MAX_SINGLE_PACKET_FRACTION); 4692 if (scctx->isc_tx_tso_segments_max > num_txd / 4693 MAX_SINGLE_PACKET_FRACTION) 4694 scctx->isc_tx_tso_segments_max = max(1, 4695 num_txd / MAX_SINGLE_PACKET_FRACTION); 4696 4697 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4698 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4699 /* 4700 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4701 * but some MACs do. 4702 */ 4703 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4704 IP_MAXPACKET)); 4705 /* 4706 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4707 * into account. In the worst case, each of these calls will 4708 * add another mbuf and, thus, the requirement for another DMA 4709 * segment. So for best performance, it doesn't make sense to 4710 * advertize a maximum of TSO segments that typically will 4711 * require defragmentation in iflib_encap(). 4712 */ 4713 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4714 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4715 } 4716 if (scctx->isc_rss_table_size == 0) 4717 scctx->isc_rss_table_size = 64; 4718 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4719 4720 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4721 /* XXX format name */ 4722 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4723 NULL, NULL, "admin"); 4724 4725 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4726 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4727 device_printf(dev, "Unable to fetch CPU list\n"); 4728 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4729 } 4730 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4731 4732 /* 4733 ** Now set up MSI or MSI-X, should return us the number of supported 4734 ** vectors (will be 1 for a legacy interrupt and MSI). 4735 */ 4736 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4737 msix = scctx->isc_vectors; 4738 } else if (scctx->isc_msix_bar != 0) 4739 /* 4740 * The simple fact that isc_msix_bar is not 0 does not mean we 4741 * we have a good value there that is known to work. 4742 */ 4743 msix = iflib_msix_init(ctx); 4744 else { 4745 scctx->isc_vectors = 1; 4746 scctx->isc_ntxqsets = 1; 4747 scctx->isc_nrxqsets = 1; 4748 scctx->isc_intr = IFLIB_INTR_LEGACY; 4749 msix = 0; 4750 } 4751 /* Get memory for the station queues */ 4752 if ((err = iflib_queues_alloc(ctx))) { 4753 device_printf(dev, "Unable to allocate queue memory\n"); 4754 goto fail_intr_free; 4755 } 4756 4757 if ((err = iflib_qset_structures_setup(ctx))) 4758 goto fail_queues; 4759 4760 /* 4761 * Now that we know how many queues there are, get the core offset. 4762 */ 4763 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 4764 4765 if (msix > 1) { 4766 /* 4767 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 4768 * aren't the default NULL implementation. 4769 */ 4770 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 4771 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4772 kobj_desc); 4773 if (kobj_method == &kobj_desc->deflt) { 4774 device_printf(dev, 4775 "MSI-X requires ifdi_rx_queue_intr_enable method"); 4776 err = EOPNOTSUPP; 4777 goto fail_queues; 4778 } 4779 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 4780 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4781 kobj_desc); 4782 if (kobj_method == &kobj_desc->deflt) { 4783 device_printf(dev, 4784 "MSI-X requires ifdi_tx_queue_intr_enable method"); 4785 err = EOPNOTSUPP; 4786 goto fail_queues; 4787 } 4788 4789 /* 4790 * Assign the MSI-X vectors. 4791 * Note that the default NULL ifdi_msix_intr_assign method will 4792 * fail here, too. 4793 */ 4794 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 4795 if (err != 0) { 4796 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 4797 err); 4798 goto fail_queues; 4799 } 4800 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 4801 rid = 0; 4802 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4803 MPASS(msix == 1); 4804 rid = 1; 4805 } 4806 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4807 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4808 goto fail_queues; 4809 } 4810 } else { 4811 device_printf(dev, 4812 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 4813 err = ENODEV; 4814 goto fail_intr_free; 4815 } 4816 4817 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4818 4819 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4820 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4821 goto fail_detach; 4822 } 4823 4824 /* 4825 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4826 * This must appear after the call to ether_ifattach() because 4827 * ether_ifattach() sets if_hdrlen to the default value. 4828 */ 4829 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4830 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4831 4832 if ((err = iflib_netmap_attach(ctx))) { 4833 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4834 goto fail_detach; 4835 } 4836 *ctxp = ctx; 4837 4838 DEBUGNET_SET(ctx->ifc_ifp, iflib); 4839 4840 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4841 iflib_add_device_sysctl_post(ctx); 4842 iflib_add_pfil(ctx); 4843 ctx->ifc_flags |= IFC_INIT_DONE; 4844 CTX_UNLOCK(ctx); 4845 4846 return (0); 4847 4848 fail_detach: 4849 ether_ifdetach(ctx->ifc_ifp); 4850 fail_intr_free: 4851 iflib_free_intr_mem(ctx); 4852 fail_queues: 4853 iflib_tx_structures_free(ctx); 4854 iflib_rx_structures_free(ctx); 4855 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task); 4856 IFDI_DETACH(ctx); 4857 fail_unlock: 4858 CTX_UNLOCK(ctx); 4859 iflib_deregister(ctx); 4860 fail_ctx_free: 4861 device_set_softc(ctx->ifc_dev, NULL); 4862 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4863 free(ctx->ifc_softc, M_IFLIB); 4864 free(ctx, M_IFLIB); 4865 return (err); 4866 } 4867 4868 int 4869 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4870 struct iflib_cloneattach_ctx *clctx) 4871 { 4872 int num_txd, num_rxd; 4873 int err; 4874 if_ctx_t ctx; 4875 if_t ifp; 4876 if_softc_ctx_t scctx; 4877 int i; 4878 void *sc; 4879 4880 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4881 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4882 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4883 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4884 ctx->ifc_flags |= IFC_PSEUDO; 4885 4886 ctx->ifc_sctx = sctx; 4887 ctx->ifc_softc = sc; 4888 ctx->ifc_dev = dev; 4889 4890 if ((err = iflib_register(ctx)) != 0) { 4891 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4892 goto fail_ctx_free; 4893 } 4894 iflib_add_device_sysctl_pre(ctx); 4895 4896 scctx = &ctx->ifc_softc_ctx; 4897 ifp = ctx->ifc_ifp; 4898 4899 iflib_reset_qvalues(ctx); 4900 CTX_LOCK(ctx); 4901 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4902 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4903 goto fail_unlock; 4904 } 4905 if (sctx->isc_flags & IFLIB_GEN_MAC) 4906 ether_gen_addr(ifp, &ctx->ifc_mac); 4907 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4908 clctx->cc_params)) != 0) { 4909 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4910 goto fail_unlock; 4911 } 4912 #ifdef INVARIANTS 4913 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4914 MPASS(scctx->isc_tx_csum_flags); 4915 #endif 4916 4917 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4918 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4919 4920 ifp->if_flags |= IFF_NOGROUP; 4921 if (sctx->isc_flags & IFLIB_PSEUDO) { 4922 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4923 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4924 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) { 4925 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4926 } else { 4927 if_attach(ctx->ifc_ifp); 4928 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t)); 4929 } 4930 4931 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4932 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4933 goto fail_detach; 4934 } 4935 *ctxp = ctx; 4936 4937 /* 4938 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4939 * This must appear after the call to ether_ifattach() because 4940 * ether_ifattach() sets if_hdrlen to the default value. 4941 */ 4942 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4943 if_setifheaderlen(ifp, 4944 sizeof(struct ether_vlan_header)); 4945 4946 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4947 iflib_add_device_sysctl_post(ctx); 4948 ctx->ifc_flags |= IFC_INIT_DONE; 4949 CTX_UNLOCK(ctx); 4950 return (0); 4951 } 4952 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4953 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4954 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4955 4956 _iflib_pre_assert(scctx); 4957 ctx->ifc_txrx = *scctx->isc_txrx; 4958 4959 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4960 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4961 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4962 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4963 4964 num_txd = iflib_num_tx_descs(ctx); 4965 num_rxd = iflib_num_rx_descs(ctx); 4966 4967 /* XXX change for per-queue sizes */ 4968 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4969 num_txd, num_rxd); 4970 4971 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 4972 scctx->isc_tx_nsegments = max(1, num_txd / 4973 MAX_SINGLE_PACKET_FRACTION); 4974 if (scctx->isc_tx_tso_segments_max > num_txd / 4975 MAX_SINGLE_PACKET_FRACTION) 4976 scctx->isc_tx_tso_segments_max = max(1, 4977 num_txd / MAX_SINGLE_PACKET_FRACTION); 4978 4979 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4980 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4981 /* 4982 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4983 * but some MACs do. 4984 */ 4985 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4986 IP_MAXPACKET)); 4987 /* 4988 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4989 * into account. In the worst case, each of these calls will 4990 * add another mbuf and, thus, the requirement for another DMA 4991 * segment. So for best performance, it doesn't make sense to 4992 * advertize a maximum of TSO segments that typically will 4993 * require defragmentation in iflib_encap(). 4994 */ 4995 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4996 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4997 } 4998 if (scctx->isc_rss_table_size == 0) 4999 scctx->isc_rss_table_size = 64; 5000 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5001 5002 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5003 /* XXX format name */ 5004 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5005 NULL, NULL, "admin"); 5006 5007 /* XXX --- can support > 1 -- but keep it simple for now */ 5008 scctx->isc_intr = IFLIB_INTR_LEGACY; 5009 5010 /* Get memory for the station queues */ 5011 if ((err = iflib_queues_alloc(ctx))) { 5012 device_printf(dev, "Unable to allocate queue memory\n"); 5013 goto fail_iflib_detach; 5014 } 5015 5016 if ((err = iflib_qset_structures_setup(ctx))) { 5017 device_printf(dev, "qset structure setup failed %d\n", err); 5018 goto fail_queues; 5019 } 5020 5021 /* 5022 * XXX What if anything do we want to do about interrupts? 5023 */ 5024 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5025 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5026 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5027 goto fail_detach; 5028 } 5029 5030 /* 5031 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5032 * This must appear after the call to ether_ifattach() because 5033 * ether_ifattach() sets if_hdrlen to the default value. 5034 */ 5035 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5036 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5037 5038 /* XXX handle more than one queue */ 5039 for (i = 0; i < scctx->isc_nrxqsets; i++) 5040 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 5041 5042 *ctxp = ctx; 5043 5044 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5045 iflib_add_device_sysctl_post(ctx); 5046 ctx->ifc_flags |= IFC_INIT_DONE; 5047 CTX_UNLOCK(ctx); 5048 5049 return (0); 5050 fail_detach: 5051 ether_ifdetach(ctx->ifc_ifp); 5052 fail_queues: 5053 iflib_tx_structures_free(ctx); 5054 iflib_rx_structures_free(ctx); 5055 fail_iflib_detach: 5056 IFDI_DETACH(ctx); 5057 fail_unlock: 5058 CTX_UNLOCK(ctx); 5059 iflib_deregister(ctx); 5060 fail_ctx_free: 5061 free(ctx->ifc_softc, M_IFLIB); 5062 free(ctx, M_IFLIB); 5063 return (err); 5064 } 5065 5066 int 5067 iflib_pseudo_deregister(if_ctx_t ctx) 5068 { 5069 if_t ifp = ctx->ifc_ifp; 5070 if_shared_ctx_t sctx = ctx->ifc_sctx; 5071 iflib_txq_t txq; 5072 iflib_rxq_t rxq; 5073 int i, j; 5074 struct taskqgroup *tqg; 5075 iflib_fl_t fl; 5076 5077 /* Unregister VLAN event handlers early */ 5078 iflib_unregister_vlan_handlers(ctx); 5079 5080 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5081 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) { 5082 bpfdetach(ifp); 5083 if_detach(ifp); 5084 } else { 5085 ether_ifdetach(ifp); 5086 } 5087 /* XXX drain any dependent tasks */ 5088 tqg = qgroup_if_io_tqg; 5089 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5090 callout_drain(&txq->ift_timer); 5091 if (txq->ift_task.gt_uniq != NULL) 5092 taskqgroup_detach(tqg, &txq->ift_task); 5093 } 5094 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5095 callout_drain(&rxq->ifr_watchdog); 5096 if (rxq->ifr_task.gt_uniq != NULL) 5097 taskqgroup_detach(tqg, &rxq->ifr_task); 5098 5099 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5100 free(fl->ifl_rx_bitmap, M_IFLIB); 5101 } 5102 tqg = qgroup_if_config_tqg; 5103 if (ctx->ifc_admin_task.gt_uniq != NULL) 5104 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5105 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5106 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5107 5108 iflib_tx_structures_free(ctx); 5109 iflib_rx_structures_free(ctx); 5110 5111 iflib_deregister(ctx); 5112 5113 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5114 free(ctx->ifc_softc, M_IFLIB); 5115 free(ctx, M_IFLIB); 5116 return (0); 5117 } 5118 5119 int 5120 iflib_device_attach(device_t dev) 5121 { 5122 if_ctx_t ctx; 5123 if_shared_ctx_t sctx; 5124 5125 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5126 return (ENOTSUP); 5127 5128 pci_enable_busmaster(dev); 5129 5130 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5131 } 5132 5133 int 5134 iflib_device_deregister(if_ctx_t ctx) 5135 { 5136 if_t ifp = ctx->ifc_ifp; 5137 iflib_txq_t txq; 5138 iflib_rxq_t rxq; 5139 device_t dev = ctx->ifc_dev; 5140 int i, j; 5141 struct taskqgroup *tqg; 5142 iflib_fl_t fl; 5143 5144 /* Make sure VLANS are not using driver */ 5145 if (if_vlantrunkinuse(ifp)) { 5146 device_printf(dev, "Vlan in use, detach first\n"); 5147 return (EBUSY); 5148 } 5149 #ifdef PCI_IOV 5150 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5151 device_printf(dev, "SR-IOV in use; detach first.\n"); 5152 return (EBUSY); 5153 } 5154 #endif 5155 5156 STATE_LOCK(ctx); 5157 ctx->ifc_flags |= IFC_IN_DETACH; 5158 STATE_UNLOCK(ctx); 5159 5160 /* Unregister VLAN handlers before calling iflib_stop() */ 5161 iflib_unregister_vlan_handlers(ctx); 5162 5163 iflib_netmap_detach(ifp); 5164 ether_ifdetach(ifp); 5165 5166 CTX_LOCK(ctx); 5167 iflib_stop(ctx); 5168 CTX_UNLOCK(ctx); 5169 5170 iflib_rem_pfil(ctx); 5171 if (ctx->ifc_led_dev != NULL) 5172 led_destroy(ctx->ifc_led_dev); 5173 /* XXX drain any dependent tasks */ 5174 tqg = qgroup_if_io_tqg; 5175 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5176 callout_drain(&txq->ift_timer); 5177 if (txq->ift_task.gt_uniq != NULL) 5178 taskqgroup_detach(tqg, &txq->ift_task); 5179 } 5180 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5181 if (rxq->ifr_task.gt_uniq != NULL) 5182 taskqgroup_detach(tqg, &rxq->ifr_task); 5183 5184 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5185 free(fl->ifl_rx_bitmap, M_IFLIB); 5186 } 5187 tqg = qgroup_if_config_tqg; 5188 if (ctx->ifc_admin_task.gt_uniq != NULL) 5189 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5190 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5191 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5192 CTX_LOCK(ctx); 5193 IFDI_DETACH(ctx); 5194 CTX_UNLOCK(ctx); 5195 5196 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5197 iflib_free_intr_mem(ctx); 5198 5199 bus_generic_detach(dev); 5200 5201 iflib_tx_structures_free(ctx); 5202 iflib_rx_structures_free(ctx); 5203 5204 iflib_deregister(ctx); 5205 5206 device_set_softc(ctx->ifc_dev, NULL); 5207 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5208 free(ctx->ifc_softc, M_IFLIB); 5209 unref_ctx_core_offset(ctx); 5210 free(ctx, M_IFLIB); 5211 return (0); 5212 } 5213 5214 static void 5215 iflib_free_intr_mem(if_ctx_t ctx) 5216 { 5217 5218 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5219 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5220 } 5221 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5222 pci_release_msi(ctx->ifc_dev); 5223 } 5224 if (ctx->ifc_msix_mem != NULL) { 5225 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5226 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5227 ctx->ifc_msix_mem = NULL; 5228 } 5229 } 5230 5231 int 5232 iflib_device_detach(device_t dev) 5233 { 5234 if_ctx_t ctx = device_get_softc(dev); 5235 5236 return (iflib_device_deregister(ctx)); 5237 } 5238 5239 int 5240 iflib_device_suspend(device_t dev) 5241 { 5242 if_ctx_t ctx = device_get_softc(dev); 5243 5244 CTX_LOCK(ctx); 5245 IFDI_SUSPEND(ctx); 5246 CTX_UNLOCK(ctx); 5247 5248 return bus_generic_suspend(dev); 5249 } 5250 int 5251 iflib_device_shutdown(device_t dev) 5252 { 5253 if_ctx_t ctx = device_get_softc(dev); 5254 5255 CTX_LOCK(ctx); 5256 IFDI_SHUTDOWN(ctx); 5257 CTX_UNLOCK(ctx); 5258 5259 return bus_generic_suspend(dev); 5260 } 5261 5262 int 5263 iflib_device_resume(device_t dev) 5264 { 5265 if_ctx_t ctx = device_get_softc(dev); 5266 iflib_txq_t txq = ctx->ifc_txqs; 5267 5268 CTX_LOCK(ctx); 5269 IFDI_RESUME(ctx); 5270 iflib_if_init_locked(ctx); 5271 CTX_UNLOCK(ctx); 5272 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5273 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5274 5275 return (bus_generic_resume(dev)); 5276 } 5277 5278 int 5279 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5280 { 5281 int error; 5282 if_ctx_t ctx = device_get_softc(dev); 5283 5284 CTX_LOCK(ctx); 5285 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5286 CTX_UNLOCK(ctx); 5287 5288 return (error); 5289 } 5290 5291 void 5292 iflib_device_iov_uninit(device_t dev) 5293 { 5294 if_ctx_t ctx = device_get_softc(dev); 5295 5296 CTX_LOCK(ctx); 5297 IFDI_IOV_UNINIT(ctx); 5298 CTX_UNLOCK(ctx); 5299 } 5300 5301 int 5302 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5303 { 5304 int error; 5305 if_ctx_t ctx = device_get_softc(dev); 5306 5307 CTX_LOCK(ctx); 5308 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5309 CTX_UNLOCK(ctx); 5310 5311 return (error); 5312 } 5313 5314 /********************************************************************* 5315 * 5316 * MODULE FUNCTION DEFINITIONS 5317 * 5318 **********************************************************************/ 5319 5320 /* 5321 * - Start a fast taskqueue thread for each core 5322 * - Start a taskqueue for control operations 5323 */ 5324 static int 5325 iflib_module_init(void) 5326 { 5327 return (0); 5328 } 5329 5330 static int 5331 iflib_module_event_handler(module_t mod, int what, void *arg) 5332 { 5333 int err; 5334 5335 switch (what) { 5336 case MOD_LOAD: 5337 if ((err = iflib_module_init()) != 0) 5338 return (err); 5339 break; 5340 case MOD_UNLOAD: 5341 return (EBUSY); 5342 default: 5343 return (EOPNOTSUPP); 5344 } 5345 5346 return (0); 5347 } 5348 5349 /********************************************************************* 5350 * 5351 * PUBLIC FUNCTION DEFINITIONS 5352 * ordered as in iflib.h 5353 * 5354 **********************************************************************/ 5355 5356 static void 5357 _iflib_assert(if_shared_ctx_t sctx) 5358 { 5359 int i; 5360 5361 MPASS(sctx->isc_tx_maxsize); 5362 MPASS(sctx->isc_tx_maxsegsize); 5363 5364 MPASS(sctx->isc_rx_maxsize); 5365 MPASS(sctx->isc_rx_nsegments); 5366 MPASS(sctx->isc_rx_maxsegsize); 5367 5368 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5369 for (i = 0; i < sctx->isc_nrxqs; i++) { 5370 MPASS(sctx->isc_nrxd_min[i]); 5371 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5372 MPASS(sctx->isc_nrxd_max[i]); 5373 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5374 MPASS(sctx->isc_nrxd_default[i]); 5375 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5376 } 5377 5378 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5379 for (i = 0; i < sctx->isc_ntxqs; i++) { 5380 MPASS(sctx->isc_ntxd_min[i]); 5381 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5382 MPASS(sctx->isc_ntxd_max[i]); 5383 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5384 MPASS(sctx->isc_ntxd_default[i]); 5385 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5386 } 5387 } 5388 5389 static void 5390 _iflib_pre_assert(if_softc_ctx_t scctx) 5391 { 5392 5393 MPASS(scctx->isc_txrx->ift_txd_encap); 5394 MPASS(scctx->isc_txrx->ift_txd_flush); 5395 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5396 MPASS(scctx->isc_txrx->ift_rxd_available); 5397 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5398 MPASS(scctx->isc_txrx->ift_rxd_refill); 5399 MPASS(scctx->isc_txrx->ift_rxd_flush); 5400 } 5401 5402 static int 5403 iflib_register(if_ctx_t ctx) 5404 { 5405 if_shared_ctx_t sctx = ctx->ifc_sctx; 5406 driver_t *driver = sctx->isc_driver; 5407 device_t dev = ctx->ifc_dev; 5408 if_t ifp; 5409 u_char type; 5410 int iflags; 5411 5412 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0) 5413 _iflib_assert(sctx); 5414 5415 CTX_LOCK_INIT(ctx); 5416 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5417 if (sctx->isc_flags & IFLIB_PSEUDO) { 5418 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) 5419 type = IFT_ETHER; 5420 else 5421 type = IFT_PPP; 5422 } else 5423 type = IFT_ETHER; 5424 ifp = ctx->ifc_ifp = if_alloc(type); 5425 if (ifp == NULL) { 5426 device_printf(dev, "can not allocate ifnet structure\n"); 5427 return (ENOMEM); 5428 } 5429 5430 /* 5431 * Initialize our context's device specific methods 5432 */ 5433 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5434 kobj_class_compile((kobj_class_t) driver); 5435 5436 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5437 if_setsoftc(ifp, ctx); 5438 if_setdev(ifp, dev); 5439 if_setinitfn(ifp, iflib_if_init); 5440 if_setioctlfn(ifp, iflib_if_ioctl); 5441 #ifdef ALTQ 5442 if_setstartfn(ifp, iflib_altq_if_start); 5443 if_settransmitfn(ifp, iflib_altq_if_transmit); 5444 if_setsendqready(ifp); 5445 #else 5446 if_settransmitfn(ifp, iflib_if_transmit); 5447 #endif 5448 if_setqflushfn(ifp, iflib_if_qflush); 5449 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH; 5450 5451 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5452 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) 5453 iflags |= IFF_POINTOPOINT; 5454 else 5455 iflags |= IFF_BROADCAST | IFF_SIMPLEX; 5456 if_setflags(ifp, iflags); 5457 ctx->ifc_vlan_attach_event = 5458 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5459 EVENTHANDLER_PRI_FIRST); 5460 ctx->ifc_vlan_detach_event = 5461 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5462 EVENTHANDLER_PRI_FIRST); 5463 5464 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5465 ctx->ifc_mediap = &ctx->ifc_media; 5466 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5467 iflib_media_change, iflib_media_status); 5468 } 5469 return (0); 5470 } 5471 5472 static void 5473 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5474 { 5475 /* Unregister VLAN events */ 5476 if (ctx->ifc_vlan_attach_event != NULL) { 5477 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5478 ctx->ifc_vlan_attach_event = NULL; 5479 } 5480 if (ctx->ifc_vlan_detach_event != NULL) { 5481 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5482 ctx->ifc_vlan_detach_event = NULL; 5483 } 5484 5485 } 5486 5487 static void 5488 iflib_deregister(if_ctx_t ctx) 5489 { 5490 if_t ifp = ctx->ifc_ifp; 5491 5492 /* Remove all media */ 5493 ifmedia_removeall(&ctx->ifc_media); 5494 5495 /* Ensure that VLAN event handlers are unregistered */ 5496 iflib_unregister_vlan_handlers(ctx); 5497 5498 /* Release kobject reference */ 5499 kobj_delete((kobj_t) ctx, NULL); 5500 5501 /* Free the ifnet structure */ 5502 if_free(ifp); 5503 5504 STATE_LOCK_DESTROY(ctx); 5505 5506 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5507 CTX_LOCK_DESTROY(ctx); 5508 } 5509 5510 static int 5511 iflib_queues_alloc(if_ctx_t ctx) 5512 { 5513 if_shared_ctx_t sctx = ctx->ifc_sctx; 5514 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5515 device_t dev = ctx->ifc_dev; 5516 int nrxqsets = scctx->isc_nrxqsets; 5517 int ntxqsets = scctx->isc_ntxqsets; 5518 iflib_txq_t txq; 5519 iflib_rxq_t rxq; 5520 iflib_fl_t fl = NULL; 5521 int i, j, cpu, err, txconf, rxconf; 5522 iflib_dma_info_t ifdip; 5523 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5524 uint32_t *txqsizes = scctx->isc_txqsizes; 5525 uint8_t nrxqs = sctx->isc_nrxqs; 5526 uint8_t ntxqs = sctx->isc_ntxqs; 5527 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5528 caddr_t *vaddrs; 5529 uint64_t *paddrs; 5530 5531 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5532 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5533 5534 /* Allocate the TX ring struct memory */ 5535 if (!(ctx->ifc_txqs = 5536 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5537 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5538 device_printf(dev, "Unable to allocate TX ring memory\n"); 5539 err = ENOMEM; 5540 goto fail; 5541 } 5542 5543 /* Now allocate the RX */ 5544 if (!(ctx->ifc_rxqs = 5545 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5546 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5547 device_printf(dev, "Unable to allocate RX ring memory\n"); 5548 err = ENOMEM; 5549 goto rx_fail; 5550 } 5551 5552 txq = ctx->ifc_txqs; 5553 rxq = ctx->ifc_rxqs; 5554 5555 /* 5556 * XXX handle allocation failure 5557 */ 5558 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5559 /* Set up some basics */ 5560 5561 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5562 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5563 device_printf(dev, 5564 "Unable to allocate TX DMA info memory\n"); 5565 err = ENOMEM; 5566 goto err_tx_desc; 5567 } 5568 txq->ift_ifdi = ifdip; 5569 for (j = 0; j < ntxqs; j++, ifdip++) { 5570 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5571 device_printf(dev, 5572 "Unable to allocate TX descriptors\n"); 5573 err = ENOMEM; 5574 goto err_tx_desc; 5575 } 5576 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5577 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5578 } 5579 txq->ift_ctx = ctx; 5580 txq->ift_id = i; 5581 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5582 txq->ift_br_offset = 1; 5583 } else { 5584 txq->ift_br_offset = 0; 5585 } 5586 /* XXX fix this */ 5587 txq->ift_timer.c_cpu = cpu; 5588 5589 if (iflib_txsd_alloc(txq)) { 5590 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5591 err = ENOMEM; 5592 goto err_tx_desc; 5593 } 5594 5595 /* Initialize the TX lock */ 5596 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5597 device_get_nameunit(dev), txq->ift_id); 5598 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5599 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5600 5601 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5602 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5603 if (err) { 5604 /* XXX free any allocated rings */ 5605 device_printf(dev, "Unable to allocate buf_ring\n"); 5606 goto err_tx_desc; 5607 } 5608 } 5609 5610 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5611 /* Set up some basics */ 5612 callout_init(&rxq->ifr_watchdog, 1); 5613 5614 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5615 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5616 device_printf(dev, 5617 "Unable to allocate RX DMA info memory\n"); 5618 err = ENOMEM; 5619 goto err_tx_desc; 5620 } 5621 5622 rxq->ifr_ifdi = ifdip; 5623 /* XXX this needs to be changed if #rx queues != #tx queues */ 5624 rxq->ifr_ntxqirq = 1; 5625 rxq->ifr_txqid[0] = i; 5626 for (j = 0; j < nrxqs; j++, ifdip++) { 5627 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5628 device_printf(dev, 5629 "Unable to allocate RX descriptors\n"); 5630 err = ENOMEM; 5631 goto err_tx_desc; 5632 } 5633 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5634 } 5635 rxq->ifr_ctx = ctx; 5636 rxq->ifr_id = i; 5637 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5638 rxq->ifr_fl_offset = 1; 5639 } else { 5640 rxq->ifr_fl_offset = 0; 5641 } 5642 rxq->ifr_nfl = nfree_lists; 5643 if (!(fl = 5644 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5645 device_printf(dev, "Unable to allocate free list memory\n"); 5646 err = ENOMEM; 5647 goto err_tx_desc; 5648 } 5649 rxq->ifr_fl = fl; 5650 for (j = 0; j < nfree_lists; j++) { 5651 fl[j].ifl_rxq = rxq; 5652 fl[j].ifl_id = j; 5653 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5654 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5655 } 5656 /* Allocate receive buffers for the ring */ 5657 if (iflib_rxsd_alloc(rxq)) { 5658 device_printf(dev, 5659 "Critical Failure setting up receive buffers\n"); 5660 err = ENOMEM; 5661 goto err_rx_desc; 5662 } 5663 5664 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5665 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5666 M_WAITOK); 5667 } 5668 5669 /* TXQs */ 5670 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5671 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5672 for (i = 0; i < ntxqsets; i++) { 5673 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5674 5675 for (j = 0; j < ntxqs; j++, di++) { 5676 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5677 paddrs[i*ntxqs + j] = di->idi_paddr; 5678 } 5679 } 5680 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5681 device_printf(ctx->ifc_dev, 5682 "Unable to allocate device TX queue\n"); 5683 iflib_tx_structures_free(ctx); 5684 free(vaddrs, M_IFLIB); 5685 free(paddrs, M_IFLIB); 5686 goto err_rx_desc; 5687 } 5688 free(vaddrs, M_IFLIB); 5689 free(paddrs, M_IFLIB); 5690 5691 /* RXQs */ 5692 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5693 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5694 for (i = 0; i < nrxqsets; i++) { 5695 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5696 5697 for (j = 0; j < nrxqs; j++, di++) { 5698 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5699 paddrs[i*nrxqs + j] = di->idi_paddr; 5700 } 5701 } 5702 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5703 device_printf(ctx->ifc_dev, 5704 "Unable to allocate device RX queue\n"); 5705 iflib_tx_structures_free(ctx); 5706 free(vaddrs, M_IFLIB); 5707 free(paddrs, M_IFLIB); 5708 goto err_rx_desc; 5709 } 5710 free(vaddrs, M_IFLIB); 5711 free(paddrs, M_IFLIB); 5712 5713 return (0); 5714 5715 /* XXX handle allocation failure changes */ 5716 err_rx_desc: 5717 err_tx_desc: 5718 rx_fail: 5719 if (ctx->ifc_rxqs != NULL) 5720 free(ctx->ifc_rxqs, M_IFLIB); 5721 ctx->ifc_rxqs = NULL; 5722 if (ctx->ifc_txqs != NULL) 5723 free(ctx->ifc_txqs, M_IFLIB); 5724 ctx->ifc_txqs = NULL; 5725 fail: 5726 return (err); 5727 } 5728 5729 static int 5730 iflib_tx_structures_setup(if_ctx_t ctx) 5731 { 5732 iflib_txq_t txq = ctx->ifc_txqs; 5733 int i; 5734 5735 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5736 iflib_txq_setup(txq); 5737 5738 return (0); 5739 } 5740 5741 static void 5742 iflib_tx_structures_free(if_ctx_t ctx) 5743 { 5744 iflib_txq_t txq = ctx->ifc_txqs; 5745 if_shared_ctx_t sctx = ctx->ifc_sctx; 5746 int i, j; 5747 5748 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5749 for (j = 0; j < sctx->isc_ntxqs; j++) 5750 iflib_dma_free(&txq->ift_ifdi[j]); 5751 iflib_txq_destroy(txq); 5752 } 5753 free(ctx->ifc_txqs, M_IFLIB); 5754 ctx->ifc_txqs = NULL; 5755 IFDI_QUEUES_FREE(ctx); 5756 } 5757 5758 /********************************************************************* 5759 * 5760 * Initialize all receive rings. 5761 * 5762 **********************************************************************/ 5763 static int 5764 iflib_rx_structures_setup(if_ctx_t ctx) 5765 { 5766 iflib_rxq_t rxq = ctx->ifc_rxqs; 5767 int q; 5768 #if defined(INET6) || defined(INET) 5769 int err, i; 5770 #endif 5771 5772 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5773 #if defined(INET6) || defined(INET) 5774 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) { 5775 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5776 TCP_LRO_ENTRIES, min(1024, 5777 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 5778 if (err != 0) { 5779 device_printf(ctx->ifc_dev, 5780 "LRO Initialization failed!\n"); 5781 goto fail; 5782 } 5783 } 5784 #endif 5785 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5786 } 5787 return (0); 5788 #if defined(INET6) || defined(INET) 5789 fail: 5790 /* 5791 * Free LRO resources allocated so far, we will only handle 5792 * the rings that completed, the failing case will have 5793 * cleaned up for itself. 'q' failed, so its the terminus. 5794 */ 5795 rxq = ctx->ifc_rxqs; 5796 for (i = 0; i < q; ++i, rxq++) { 5797 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5798 tcp_lro_free(&rxq->ifr_lc); 5799 } 5800 return (err); 5801 #endif 5802 } 5803 5804 /********************************************************************* 5805 * 5806 * Free all receive rings. 5807 * 5808 **********************************************************************/ 5809 static void 5810 iflib_rx_structures_free(if_ctx_t ctx) 5811 { 5812 iflib_rxq_t rxq = ctx->ifc_rxqs; 5813 if_shared_ctx_t sctx = ctx->ifc_sctx; 5814 int i, j; 5815 5816 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5817 for (j = 0; j < sctx->isc_nrxqs; j++) 5818 iflib_dma_free(&rxq->ifr_ifdi[j]); 5819 iflib_rx_sds_free(rxq); 5820 #if defined(INET6) || defined(INET) 5821 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5822 tcp_lro_free(&rxq->ifr_lc); 5823 #endif 5824 } 5825 free(ctx->ifc_rxqs, M_IFLIB); 5826 ctx->ifc_rxqs = NULL; 5827 } 5828 5829 static int 5830 iflib_qset_structures_setup(if_ctx_t ctx) 5831 { 5832 int err; 5833 5834 /* 5835 * It is expected that the caller takes care of freeing queues if this 5836 * fails. 5837 */ 5838 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5839 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5840 return (err); 5841 } 5842 5843 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5844 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5845 5846 return (err); 5847 } 5848 5849 int 5850 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5851 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5852 { 5853 5854 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5855 } 5856 5857 #ifdef SMP 5858 static int 5859 find_nth(if_ctx_t ctx, int qid) 5860 { 5861 cpuset_t cpus; 5862 int i, cpuid, eqid, count; 5863 5864 CPU_COPY(&ctx->ifc_cpus, &cpus); 5865 count = CPU_COUNT(&cpus); 5866 eqid = qid % count; 5867 /* clear up to the qid'th bit */ 5868 for (i = 0; i < eqid; i++) { 5869 cpuid = CPU_FFS(&cpus); 5870 MPASS(cpuid != 0); 5871 CPU_CLR(cpuid-1, &cpus); 5872 } 5873 cpuid = CPU_FFS(&cpus); 5874 MPASS(cpuid != 0); 5875 return (cpuid-1); 5876 } 5877 5878 #ifdef SCHED_ULE 5879 extern struct cpu_group *cpu_top; /* CPU topology */ 5880 5881 static int 5882 find_child_with_core(int cpu, struct cpu_group *grp) 5883 { 5884 int i; 5885 5886 if (grp->cg_children == 0) 5887 return -1; 5888 5889 MPASS(grp->cg_child); 5890 for (i = 0; i < grp->cg_children; i++) { 5891 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5892 return i; 5893 } 5894 5895 return -1; 5896 } 5897 5898 /* 5899 * Find the nth "close" core to the specified core 5900 * "close" is defined as the deepest level that shares 5901 * at least an L2 cache. With threads, this will be 5902 * threads on the same core. If the shared cache is L3 5903 * or higher, simply returns the same core. 5904 */ 5905 static int 5906 find_close_core(int cpu, int core_offset) 5907 { 5908 struct cpu_group *grp; 5909 int i; 5910 int fcpu; 5911 cpuset_t cs; 5912 5913 grp = cpu_top; 5914 if (grp == NULL) 5915 return cpu; 5916 i = 0; 5917 while ((i = find_child_with_core(cpu, grp)) != -1) { 5918 /* If the child only has one cpu, don't descend */ 5919 if (grp->cg_child[i].cg_count <= 1) 5920 break; 5921 grp = &grp->cg_child[i]; 5922 } 5923 5924 /* If they don't share at least an L2 cache, use the same CPU */ 5925 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5926 return cpu; 5927 5928 /* Now pick one */ 5929 CPU_COPY(&grp->cg_mask, &cs); 5930 5931 /* Add the selected CPU offset to core offset. */ 5932 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5933 if (fcpu - 1 == cpu) 5934 break; 5935 CPU_CLR(fcpu - 1, &cs); 5936 } 5937 MPASS(fcpu); 5938 5939 core_offset += i; 5940 5941 CPU_COPY(&grp->cg_mask, &cs); 5942 for (i = core_offset % grp->cg_count; i > 0; i--) { 5943 MPASS(CPU_FFS(&cs)); 5944 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5945 } 5946 MPASS(CPU_FFS(&cs)); 5947 return CPU_FFS(&cs) - 1; 5948 } 5949 #else 5950 static int 5951 find_close_core(int cpu, int core_offset __unused) 5952 { 5953 return cpu; 5954 } 5955 #endif 5956 5957 static int 5958 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5959 { 5960 switch (type) { 5961 case IFLIB_INTR_TX: 5962 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5963 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5964 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5965 case IFLIB_INTR_RX: 5966 case IFLIB_INTR_RXTX: 5967 /* RX queues get the specified core */ 5968 return qid / CPU_COUNT(&ctx->ifc_cpus); 5969 default: 5970 return -1; 5971 } 5972 } 5973 #else 5974 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5975 #define find_close_core(cpuid, tid) CPU_FIRST() 5976 #define find_nth(ctx, gid) CPU_FIRST() 5977 #endif 5978 5979 /* Just to avoid copy/paste */ 5980 static inline int 5981 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5982 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5983 const char *name) 5984 { 5985 device_t dev; 5986 int co, cpuid, err, tid; 5987 5988 dev = ctx->ifc_dev; 5989 co = ctx->ifc_sysctl_core_offset; 5990 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX) 5991 co += ctx->ifc_softc_ctx.isc_nrxqsets; 5992 cpuid = find_nth(ctx, qid + co); 5993 tid = get_core_offset(ctx, type, qid); 5994 if (tid < 0) { 5995 device_printf(dev, "get_core_offset failed\n"); 5996 return (EOPNOTSUPP); 5997 } 5998 cpuid = find_close_core(cpuid, tid); 5999 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 6000 name); 6001 if (err) { 6002 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6003 return (err); 6004 } 6005 #ifdef notyet 6006 if (cpuid > ctx->ifc_cpuid_highest) 6007 ctx->ifc_cpuid_highest = cpuid; 6008 #endif 6009 return (0); 6010 } 6011 6012 int 6013 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6014 iflib_intr_type_t type, driver_filter_t *filter, 6015 void *filter_arg, int qid, const char *name) 6016 { 6017 device_t dev; 6018 struct grouptask *gtask; 6019 struct taskqgroup *tqg; 6020 iflib_filter_info_t info; 6021 gtask_fn_t *fn; 6022 int tqrid, err; 6023 driver_filter_t *intr_fast; 6024 void *q; 6025 6026 info = &ctx->ifc_filter_info; 6027 tqrid = rid; 6028 6029 switch (type) { 6030 /* XXX merge tx/rx for netmap? */ 6031 case IFLIB_INTR_TX: 6032 q = &ctx->ifc_txqs[qid]; 6033 info = &ctx->ifc_txqs[qid].ift_filter_info; 6034 gtask = &ctx->ifc_txqs[qid].ift_task; 6035 tqg = qgroup_if_io_tqg; 6036 fn = _task_fn_tx; 6037 intr_fast = iflib_fast_intr; 6038 GROUPTASK_INIT(gtask, 0, fn, q); 6039 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6040 break; 6041 case IFLIB_INTR_RX: 6042 q = &ctx->ifc_rxqs[qid]; 6043 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6044 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6045 tqg = qgroup_if_io_tqg; 6046 fn = _task_fn_rx; 6047 intr_fast = iflib_fast_intr; 6048 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6049 break; 6050 case IFLIB_INTR_RXTX: 6051 q = &ctx->ifc_rxqs[qid]; 6052 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6053 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6054 tqg = qgroup_if_io_tqg; 6055 fn = _task_fn_rx; 6056 intr_fast = iflib_fast_intr_rxtx; 6057 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6058 break; 6059 case IFLIB_INTR_ADMIN: 6060 q = ctx; 6061 tqrid = -1; 6062 info = &ctx->ifc_filter_info; 6063 gtask = &ctx->ifc_admin_task; 6064 tqg = qgroup_if_config_tqg; 6065 fn = _task_fn_admin; 6066 intr_fast = iflib_fast_intr_ctx; 6067 break; 6068 default: 6069 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6070 __func__); 6071 return (EINVAL); 6072 } 6073 6074 info->ifi_filter = filter; 6075 info->ifi_filter_arg = filter_arg; 6076 info->ifi_task = gtask; 6077 info->ifi_ctx = q; 6078 6079 dev = ctx->ifc_dev; 6080 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6081 if (err != 0) { 6082 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6083 return (err); 6084 } 6085 if (type == IFLIB_INTR_ADMIN) 6086 return (0); 6087 6088 if (tqrid != -1) { 6089 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6090 q, name); 6091 if (err) 6092 return (err); 6093 } else { 6094 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6095 } 6096 6097 return (0); 6098 } 6099 6100 void 6101 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6102 { 6103 struct grouptask *gtask; 6104 struct taskqgroup *tqg; 6105 gtask_fn_t *fn; 6106 void *q; 6107 int err; 6108 6109 switch (type) { 6110 case IFLIB_INTR_TX: 6111 q = &ctx->ifc_txqs[qid]; 6112 gtask = &ctx->ifc_txqs[qid].ift_task; 6113 tqg = qgroup_if_io_tqg; 6114 fn = _task_fn_tx; 6115 GROUPTASK_INIT(gtask, 0, fn, q); 6116 break; 6117 case IFLIB_INTR_RX: 6118 q = &ctx->ifc_rxqs[qid]; 6119 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6120 tqg = qgroup_if_io_tqg; 6121 fn = _task_fn_rx; 6122 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6123 break; 6124 case IFLIB_INTR_IOV: 6125 q = ctx; 6126 gtask = &ctx->ifc_vflr_task; 6127 tqg = qgroup_if_config_tqg; 6128 fn = _task_fn_iov; 6129 GROUPTASK_INIT(gtask, 0, fn, q); 6130 break; 6131 default: 6132 panic("unknown net intr type"); 6133 } 6134 if (irq != NULL) { 6135 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6136 q, name); 6137 if (err) 6138 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 6139 irq->ii_res, name); 6140 } else { 6141 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 6142 } 6143 } 6144 6145 void 6146 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6147 { 6148 6149 if (irq->ii_tag) 6150 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6151 6152 if (irq->ii_res) 6153 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6154 rman_get_rid(irq->ii_res), irq->ii_res); 6155 } 6156 6157 static int 6158 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6159 { 6160 iflib_txq_t txq = ctx->ifc_txqs; 6161 iflib_rxq_t rxq = ctx->ifc_rxqs; 6162 if_irq_t irq = &ctx->ifc_legacy_irq; 6163 iflib_filter_info_t info; 6164 device_t dev; 6165 struct grouptask *gtask; 6166 struct resource *res; 6167 struct taskqgroup *tqg; 6168 void *q; 6169 int err, tqrid; 6170 bool rx_only; 6171 6172 q = &ctx->ifc_rxqs[0]; 6173 info = &rxq[0].ifr_filter_info; 6174 gtask = &rxq[0].ifr_task; 6175 tqg = qgroup_if_io_tqg; 6176 tqrid = *rid; 6177 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6178 6179 ctx->ifc_flags |= IFC_LEGACY; 6180 info->ifi_filter = filter; 6181 info->ifi_filter_arg = filter_arg; 6182 info->ifi_task = gtask; 6183 info->ifi_ctx = rx_only ? ctx : q; 6184 6185 dev = ctx->ifc_dev; 6186 /* We allocate a single interrupt resource */ 6187 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6188 iflib_fast_intr_rxtx, NULL, info, name); 6189 if (err != 0) 6190 return (err); 6191 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6192 res = irq->ii_res; 6193 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6194 6195 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6196 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6197 "tx"); 6198 return (0); 6199 } 6200 6201 void 6202 iflib_led_create(if_ctx_t ctx) 6203 { 6204 6205 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6206 device_get_nameunit(ctx->ifc_dev)); 6207 } 6208 6209 void 6210 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6211 { 6212 6213 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6214 } 6215 6216 void 6217 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6218 { 6219 6220 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6221 } 6222 6223 void 6224 iflib_admin_intr_deferred(if_ctx_t ctx) 6225 { 6226 6227 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6228 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6229 } 6230 6231 void 6232 iflib_iov_intr_deferred(if_ctx_t ctx) 6233 { 6234 6235 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6236 } 6237 6238 void 6239 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6240 { 6241 6242 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6243 name); 6244 } 6245 6246 void 6247 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6248 const char *name) 6249 { 6250 6251 GROUPTASK_INIT(gtask, 0, fn, ctx); 6252 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6253 name); 6254 } 6255 6256 void 6257 iflib_config_gtask_deinit(struct grouptask *gtask) 6258 { 6259 6260 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6261 } 6262 6263 void 6264 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6265 { 6266 if_t ifp = ctx->ifc_ifp; 6267 iflib_txq_t txq = ctx->ifc_txqs; 6268 6269 if_setbaudrate(ifp, baudrate); 6270 if (baudrate >= IF_Gbps(10)) { 6271 STATE_LOCK(ctx); 6272 ctx->ifc_flags |= IFC_PREFETCH; 6273 STATE_UNLOCK(ctx); 6274 } 6275 /* If link down, disable watchdog */ 6276 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6277 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6278 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6279 } 6280 ctx->ifc_link_state = link_state; 6281 if_link_state_change(ifp, link_state); 6282 } 6283 6284 static int 6285 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6286 { 6287 int credits; 6288 #ifdef INVARIANTS 6289 int credits_pre = txq->ift_cidx_processed; 6290 #endif 6291 6292 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6293 BUS_DMASYNC_POSTREAD); 6294 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6295 return (0); 6296 6297 txq->ift_processed += credits; 6298 txq->ift_cidx_processed += credits; 6299 6300 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6301 if (txq->ift_cidx_processed >= txq->ift_size) 6302 txq->ift_cidx_processed -= txq->ift_size; 6303 return (credits); 6304 } 6305 6306 static int 6307 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6308 { 6309 iflib_fl_t fl; 6310 u_int i; 6311 6312 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6313 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6314 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6315 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6316 budget)); 6317 } 6318 6319 void 6320 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6321 const char *description, if_int_delay_info_t info, 6322 int offset, int value) 6323 { 6324 info->iidi_ctx = ctx; 6325 info->iidi_offset = offset; 6326 info->iidi_value = value; 6327 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6328 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6329 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6330 info, 0, iflib_sysctl_int_delay, "I", description); 6331 } 6332 6333 struct sx * 6334 iflib_ctx_lock_get(if_ctx_t ctx) 6335 { 6336 6337 return (&ctx->ifc_ctx_sx); 6338 } 6339 6340 static int 6341 iflib_msix_init(if_ctx_t ctx) 6342 { 6343 device_t dev = ctx->ifc_dev; 6344 if_shared_ctx_t sctx = ctx->ifc_sctx; 6345 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6346 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6347 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6348 6349 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6350 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6351 6352 if (bootverbose) 6353 device_printf(dev, "msix_init qsets capped at %d\n", 6354 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6355 6356 /* Override by tuneable */ 6357 if (scctx->isc_disable_msix) 6358 goto msi; 6359 6360 /* First try MSI-X */ 6361 if ((msgs = pci_msix_count(dev)) == 0) { 6362 if (bootverbose) 6363 device_printf(dev, "MSI-X not supported or disabled\n"); 6364 goto msi; 6365 } 6366 6367 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6368 /* 6369 * bar == -1 => "trust me I know what I'm doing" 6370 * Some drivers are for hardware that is so shoddily 6371 * documented that no one knows which bars are which 6372 * so the developer has to map all bars. This hack 6373 * allows shoddy garbage to use MSI-X in this framework. 6374 */ 6375 if (bar != -1) { 6376 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6377 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6378 if (ctx->ifc_msix_mem == NULL) { 6379 device_printf(dev, "Unable to map MSI-X table\n"); 6380 goto msi; 6381 } 6382 } 6383 6384 admincnt = sctx->isc_admin_intrcnt; 6385 #if IFLIB_DEBUG 6386 /* use only 1 qset in debug mode */ 6387 queuemsgs = min(msgs - admincnt, 1); 6388 #else 6389 queuemsgs = msgs - admincnt; 6390 #endif 6391 #ifdef RSS 6392 queues = imin(queuemsgs, rss_getnumbuckets()); 6393 #else 6394 queues = queuemsgs; 6395 #endif 6396 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6397 if (bootverbose) 6398 device_printf(dev, 6399 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6400 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6401 #ifdef RSS 6402 /* If we're doing RSS, clamp at the number of RSS buckets */ 6403 if (queues > rss_getnumbuckets()) 6404 queues = rss_getnumbuckets(); 6405 #endif 6406 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6407 rx_queues = iflib_num_rx_queues; 6408 else 6409 rx_queues = queues; 6410 6411 if (rx_queues > scctx->isc_nrxqsets) 6412 rx_queues = scctx->isc_nrxqsets; 6413 6414 /* 6415 * We want this to be all logical CPUs by default 6416 */ 6417 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6418 tx_queues = iflib_num_tx_queues; 6419 else 6420 tx_queues = mp_ncpus; 6421 6422 if (tx_queues > scctx->isc_ntxqsets) 6423 tx_queues = scctx->isc_ntxqsets; 6424 6425 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6426 #ifdef INVARIANTS 6427 if (tx_queues != rx_queues) 6428 device_printf(dev, 6429 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6430 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6431 #endif 6432 tx_queues = min(rx_queues, tx_queues); 6433 rx_queues = min(rx_queues, tx_queues); 6434 } 6435 6436 vectors = rx_queues + admincnt; 6437 if (msgs < vectors) { 6438 device_printf(dev, 6439 "insufficient number of MSI-X vectors " 6440 "(supported %d, need %d)\n", msgs, vectors); 6441 goto msi; 6442 } 6443 6444 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6445 tx_queues); 6446 msgs = vectors; 6447 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6448 if (vectors != msgs) { 6449 device_printf(dev, 6450 "Unable to allocate sufficient MSI-X vectors " 6451 "(got %d, need %d)\n", vectors, msgs); 6452 pci_release_msi(dev); 6453 if (bar != -1) { 6454 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6455 ctx->ifc_msix_mem); 6456 ctx->ifc_msix_mem = NULL; 6457 } 6458 goto msi; 6459 } 6460 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6461 vectors); 6462 scctx->isc_vectors = vectors; 6463 scctx->isc_nrxqsets = rx_queues; 6464 scctx->isc_ntxqsets = tx_queues; 6465 scctx->isc_intr = IFLIB_INTR_MSIX; 6466 6467 return (vectors); 6468 } else { 6469 device_printf(dev, 6470 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6471 err); 6472 if (bar != -1) { 6473 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6474 ctx->ifc_msix_mem); 6475 ctx->ifc_msix_mem = NULL; 6476 } 6477 } 6478 6479 msi: 6480 vectors = pci_msi_count(dev); 6481 scctx->isc_nrxqsets = 1; 6482 scctx->isc_ntxqsets = 1; 6483 scctx->isc_vectors = vectors; 6484 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6485 device_printf(dev,"Using an MSI interrupt\n"); 6486 scctx->isc_intr = IFLIB_INTR_MSI; 6487 } else { 6488 scctx->isc_vectors = 1; 6489 device_printf(dev,"Using a Legacy interrupt\n"); 6490 scctx->isc_intr = IFLIB_INTR_LEGACY; 6491 } 6492 6493 return (vectors); 6494 } 6495 6496 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6497 6498 static int 6499 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6500 { 6501 int rc; 6502 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6503 struct sbuf *sb; 6504 const char *ring_state = "UNKNOWN"; 6505 6506 /* XXX needed ? */ 6507 rc = sysctl_wire_old_buffer(req, 0); 6508 MPASS(rc == 0); 6509 if (rc != 0) 6510 return (rc); 6511 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6512 MPASS(sb != NULL); 6513 if (sb == NULL) 6514 return (ENOMEM); 6515 if (state[3] <= 3) 6516 ring_state = ring_states[state[3]]; 6517 6518 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6519 state[0], state[1], state[2], ring_state); 6520 rc = sbuf_finish(sb); 6521 sbuf_delete(sb); 6522 return(rc); 6523 } 6524 6525 enum iflib_ndesc_handler { 6526 IFLIB_NTXD_HANDLER, 6527 IFLIB_NRXD_HANDLER, 6528 }; 6529 6530 static int 6531 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6532 { 6533 if_ctx_t ctx = (void *)arg1; 6534 enum iflib_ndesc_handler type = arg2; 6535 char buf[256] = {0}; 6536 qidx_t *ndesc; 6537 char *p, *next; 6538 int nqs, rc, i; 6539 6540 nqs = 8; 6541 switch(type) { 6542 case IFLIB_NTXD_HANDLER: 6543 ndesc = ctx->ifc_sysctl_ntxds; 6544 if (ctx->ifc_sctx) 6545 nqs = ctx->ifc_sctx->isc_ntxqs; 6546 break; 6547 case IFLIB_NRXD_HANDLER: 6548 ndesc = ctx->ifc_sysctl_nrxds; 6549 if (ctx->ifc_sctx) 6550 nqs = ctx->ifc_sctx->isc_nrxqs; 6551 break; 6552 default: 6553 printf("%s: unhandled type\n", __func__); 6554 return (EINVAL); 6555 } 6556 if (nqs == 0) 6557 nqs = 8; 6558 6559 for (i=0; i<8; i++) { 6560 if (i >= nqs) 6561 break; 6562 if (i) 6563 strcat(buf, ","); 6564 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6565 } 6566 6567 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6568 if (rc || req->newptr == NULL) 6569 return rc; 6570 6571 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6572 i++, p = strsep(&next, " ,")) { 6573 ndesc[i] = strtoul(p, NULL, 10); 6574 } 6575 6576 return(rc); 6577 } 6578 6579 #define NAME_BUFLEN 32 6580 static void 6581 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6582 { 6583 device_t dev = iflib_get_dev(ctx); 6584 struct sysctl_oid_list *child, *oid_list; 6585 struct sysctl_ctx_list *ctx_list; 6586 struct sysctl_oid *node; 6587 6588 ctx_list = device_get_sysctl_ctx(dev); 6589 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6590 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6591 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 6592 oid_list = SYSCTL_CHILDREN(node); 6593 6594 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6595 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6596 "driver version"); 6597 6598 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6599 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6600 "# of txqs to use, 0 => use default #"); 6601 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6602 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6603 "# of rxqs to use, 0 => use default #"); 6604 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6605 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6606 "permit #txq != #rxq"); 6607 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6608 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6609 "disable MSI-X (default 0)"); 6610 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6611 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6612 "set the RX budget"); 6613 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6614 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6615 "cause TX to abdicate instead of running to completion"); 6616 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6617 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6618 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6619 "offset to start using cores at"); 6620 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6621 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6622 "use separate cores for TX and RX"); 6623 6624 /* XXX change for per-queue sizes */ 6625 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6626 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6627 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6628 "list of # of TX descriptors to use, 0 = use default #"); 6629 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6630 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6631 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6632 "list of # of RX descriptors to use, 0 = use default #"); 6633 } 6634 6635 static void 6636 iflib_add_device_sysctl_post(if_ctx_t ctx) 6637 { 6638 if_shared_ctx_t sctx = ctx->ifc_sctx; 6639 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6640 device_t dev = iflib_get_dev(ctx); 6641 struct sysctl_oid_list *child; 6642 struct sysctl_ctx_list *ctx_list; 6643 iflib_fl_t fl; 6644 iflib_txq_t txq; 6645 iflib_rxq_t rxq; 6646 int i, j; 6647 char namebuf[NAME_BUFLEN]; 6648 char *qfmt; 6649 struct sysctl_oid *queue_node, *fl_node, *node; 6650 struct sysctl_oid_list *queue_list, *fl_list; 6651 ctx_list = device_get_sysctl_ctx(dev); 6652 6653 node = ctx->ifc_sysctl_node; 6654 child = SYSCTL_CHILDREN(node); 6655 6656 if (scctx->isc_ntxqsets > 100) 6657 qfmt = "txq%03d"; 6658 else if (scctx->isc_ntxqsets > 10) 6659 qfmt = "txq%02d"; 6660 else 6661 qfmt = "txq%d"; 6662 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6663 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6664 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6665 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6666 queue_list = SYSCTL_CHILDREN(queue_node); 6667 #if MEMORY_LOGGING 6668 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6669 CTLFLAG_RD, 6670 &txq->ift_dequeued, "total mbufs freed"); 6671 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6672 CTLFLAG_RD, 6673 &txq->ift_enqueued, "total mbufs enqueued"); 6674 #endif 6675 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6676 CTLFLAG_RD, 6677 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6678 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6679 CTLFLAG_RD, 6680 &txq->ift_pullups, "# of times m_pullup was called"); 6681 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6682 CTLFLAG_RD, 6683 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6684 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6685 CTLFLAG_RD, 6686 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6687 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6688 CTLFLAG_RD, 6689 &txq->ift_map_failed, "# of times DMA map failed"); 6690 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6691 CTLFLAG_RD, 6692 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6693 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6694 CTLFLAG_RD, 6695 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6696 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6697 CTLFLAG_RD, 6698 &txq->ift_pidx, 1, "Producer Index"); 6699 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6700 CTLFLAG_RD, 6701 &txq->ift_cidx, 1, "Consumer Index"); 6702 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6703 CTLFLAG_RD, 6704 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6705 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6706 CTLFLAG_RD, 6707 &txq->ift_in_use, 1, "descriptors in use"); 6708 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6709 CTLFLAG_RD, 6710 &txq->ift_processed, "descriptors procesed for clean"); 6711 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6712 CTLFLAG_RD, 6713 &txq->ift_cleaned, "total cleaned"); 6714 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6715 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6716 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6717 mp_ring_state_handler, "A", "soft ring state"); 6718 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6719 CTLFLAG_RD, &txq->ift_br->enqueues, 6720 "# of enqueues to the mp_ring for this queue"); 6721 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6722 CTLFLAG_RD, &txq->ift_br->drops, 6723 "# of drops in the mp_ring for this queue"); 6724 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6725 CTLFLAG_RD, &txq->ift_br->starts, 6726 "# of normal consumer starts in the mp_ring for this queue"); 6727 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6728 CTLFLAG_RD, &txq->ift_br->stalls, 6729 "# of consumer stalls in the mp_ring for this queue"); 6730 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6731 CTLFLAG_RD, &txq->ift_br->restarts, 6732 "# of consumer restarts in the mp_ring for this queue"); 6733 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6734 CTLFLAG_RD, &txq->ift_br->abdications, 6735 "# of consumer abdications in the mp_ring for this queue"); 6736 } 6737 6738 if (scctx->isc_nrxqsets > 100) 6739 qfmt = "rxq%03d"; 6740 else if (scctx->isc_nrxqsets > 10) 6741 qfmt = "rxq%02d"; 6742 else 6743 qfmt = "rxq%d"; 6744 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6745 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6746 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6747 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6748 queue_list = SYSCTL_CHILDREN(queue_node); 6749 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6750 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6751 CTLFLAG_RD, 6752 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6753 } 6754 6755 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6756 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6757 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6758 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 6759 fl_list = SYSCTL_CHILDREN(fl_node); 6760 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6761 CTLFLAG_RD, 6762 &fl->ifl_pidx, 1, "Producer Index"); 6763 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6764 CTLFLAG_RD, 6765 &fl->ifl_cidx, 1, "Consumer Index"); 6766 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6767 CTLFLAG_RD, 6768 &fl->ifl_credits, 1, "credits available"); 6769 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 6770 CTLFLAG_RD, 6771 &fl->ifl_buf_size, 1, "buffer size"); 6772 #if MEMORY_LOGGING 6773 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6774 CTLFLAG_RD, 6775 &fl->ifl_m_enqueued, "mbufs allocated"); 6776 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6777 CTLFLAG_RD, 6778 &fl->ifl_m_dequeued, "mbufs freed"); 6779 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6780 CTLFLAG_RD, 6781 &fl->ifl_cl_enqueued, "clusters allocated"); 6782 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6783 CTLFLAG_RD, 6784 &fl->ifl_cl_dequeued, "clusters freed"); 6785 #endif 6786 } 6787 } 6788 6789 } 6790 6791 void 6792 iflib_request_reset(if_ctx_t ctx) 6793 { 6794 6795 STATE_LOCK(ctx); 6796 ctx->ifc_flags |= IFC_DO_RESET; 6797 STATE_UNLOCK(ctx); 6798 } 6799 6800 #ifndef __NO_STRICT_ALIGNMENT 6801 static struct mbuf * 6802 iflib_fixup_rx(struct mbuf *m) 6803 { 6804 struct mbuf *n; 6805 6806 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6807 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6808 m->m_data += ETHER_HDR_LEN; 6809 n = m; 6810 } else { 6811 MGETHDR(n, M_NOWAIT, MT_DATA); 6812 if (n == NULL) { 6813 m_freem(m); 6814 return (NULL); 6815 } 6816 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6817 m->m_data += ETHER_HDR_LEN; 6818 m->m_len -= ETHER_HDR_LEN; 6819 n->m_len = ETHER_HDR_LEN; 6820 M_MOVE_PKTHDR(n, m); 6821 n->m_next = m; 6822 } 6823 return (n); 6824 } 6825 #endif 6826 6827 #ifdef DEBUGNET 6828 static void 6829 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6830 { 6831 if_ctx_t ctx; 6832 6833 ctx = if_getsoftc(ifp); 6834 CTX_LOCK(ctx); 6835 *nrxr = NRXQSETS(ctx); 6836 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6837 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6838 CTX_UNLOCK(ctx); 6839 } 6840 6841 static void 6842 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 6843 { 6844 if_ctx_t ctx; 6845 if_softc_ctx_t scctx; 6846 iflib_fl_t fl; 6847 iflib_rxq_t rxq; 6848 int i, j; 6849 6850 ctx = if_getsoftc(ifp); 6851 scctx = &ctx->ifc_softc_ctx; 6852 6853 switch (event) { 6854 case DEBUGNET_START: 6855 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6856 rxq = &ctx->ifc_rxqs[i]; 6857 for (j = 0; j < rxq->ifr_nfl; j++) { 6858 fl = rxq->ifr_fl; 6859 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6860 } 6861 } 6862 iflib_no_tx_batch = 1; 6863 break; 6864 default: 6865 break; 6866 } 6867 } 6868 6869 static int 6870 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 6871 { 6872 if_ctx_t ctx; 6873 iflib_txq_t txq; 6874 int error; 6875 6876 ctx = if_getsoftc(ifp); 6877 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6878 IFF_DRV_RUNNING) 6879 return (EBUSY); 6880 6881 txq = &ctx->ifc_txqs[0]; 6882 error = iflib_encap(txq, &m); 6883 if (error == 0) 6884 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6885 return (error); 6886 } 6887 6888 static int 6889 iflib_debugnet_poll(if_t ifp, int count) 6890 { 6891 struct epoch_tracker et; 6892 if_ctx_t ctx; 6893 if_softc_ctx_t scctx; 6894 iflib_txq_t txq; 6895 int i; 6896 6897 ctx = if_getsoftc(ifp); 6898 scctx = &ctx->ifc_softc_ctx; 6899 6900 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6901 IFF_DRV_RUNNING) 6902 return (EBUSY); 6903 6904 txq = &ctx->ifc_txqs[0]; 6905 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6906 6907 NET_EPOCH_ENTER(et); 6908 for (i = 0; i < scctx->isc_nrxqsets; i++) 6909 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6910 NET_EPOCH_EXIT(et); 6911 return (0); 6912 } 6913 #endif /* DEBUGNET */ 6914