1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/sockio.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/mutex.h> 44 #include <sys/module.h> 45 #include <sys/kobj.h> 46 #include <sys/rman.h> 47 #include <sys/sbuf.h> 48 #include <sys/smp.h> 49 #include <sys/socket.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 56 #include <net/if.h> 57 #include <net/if_var.h> 58 #include <net/if_types.h> 59 #include <net/if_media.h> 60 #include <net/bpf.h> 61 #include <net/ethernet.h> 62 #include <net/mp_ring.h> 63 #include <net/vnet.h> 64 65 #include <netinet/in.h> 66 #include <netinet/in_pcb.h> 67 #include <netinet/tcp_lro.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/if_ether.h> 70 #include <netinet/ip.h> 71 #include <netinet/ip6.h> 72 #include <netinet/tcp.h> 73 #include <netinet/ip_var.h> 74 #include <netinet6/ip6_var.h> 75 76 #include <machine/bus.h> 77 #include <machine/in_cksum.h> 78 79 #include <vm/vm.h> 80 #include <vm/pmap.h> 81 82 #include <dev/led/led.h> 83 #include <dev/pci/pcireg.h> 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pci_private.h> 86 87 #include <net/iflib.h> 88 89 #include "ifdi_if.h" 90 91 #if defined(__i386__) || defined(__amd64__) 92 #include <sys/memdesc.h> 93 #include <machine/bus.h> 94 #include <machine/md_var.h> 95 #include <machine/specialreg.h> 96 #include <x86/include/busdma_impl.h> 97 #include <x86/iommu/busdma_dmar.h> 98 #endif 99 100 #include <sys/bitstring.h> 101 /* 102 * enable accounting of every mbuf as it comes in to and goes out of 103 * iflib's software descriptor references 104 */ 105 #define MEMORY_LOGGING 0 106 /* 107 * Enable mbuf vectors for compressing long mbuf chains 108 */ 109 110 /* 111 * NB: 112 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 113 * we prefetch needs to be determined by the time spent in m_free vis a vis 114 * the cost of a prefetch. This will of course vary based on the workload: 115 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 116 * is quite expensive, thus suggesting very little prefetch. 117 * - small packet forwarding which is just returning a single mbuf to 118 * UMA will typically be very fast vis a vis the cost of a memory 119 * access. 120 */ 121 122 123 /* 124 * File organization: 125 * - private structures 126 * - iflib private utility functions 127 * - ifnet functions 128 * - vlan registry and other exported functions 129 * - iflib public core functions 130 * 131 * 132 */ 133 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 134 135 struct iflib_txq; 136 typedef struct iflib_txq *iflib_txq_t; 137 struct iflib_rxq; 138 typedef struct iflib_rxq *iflib_rxq_t; 139 struct iflib_fl; 140 typedef struct iflib_fl *iflib_fl_t; 141 142 struct iflib_ctx; 143 144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 145 146 typedef struct iflib_filter_info { 147 driver_filter_t *ifi_filter; 148 void *ifi_filter_arg; 149 struct grouptask *ifi_task; 150 void *ifi_ctx; 151 } *iflib_filter_info_t; 152 153 struct iflib_ctx { 154 KOBJ_FIELDS; 155 /* 156 * Pointer to hardware driver's softc 157 */ 158 void *ifc_softc; 159 device_t ifc_dev; 160 if_t ifc_ifp; 161 162 cpuset_t ifc_cpus; 163 if_shared_ctx_t ifc_sctx; 164 struct if_softc_ctx ifc_softc_ctx; 165 166 struct mtx ifc_ctx_mtx; 167 struct mtx ifc_state_mtx; 168 169 uint16_t ifc_nhwtxqs; 170 uint16_t ifc_nhwrxqs; 171 172 iflib_txq_t ifc_txqs; 173 iflib_rxq_t ifc_rxqs; 174 uint32_t ifc_if_flags; 175 uint32_t ifc_flags; 176 uint32_t ifc_max_fl_buf_size; 177 int ifc_in_detach; 178 179 int ifc_link_state; 180 int ifc_link_irq; 181 int ifc_watchdog_events; 182 struct cdev *ifc_led_dev; 183 struct resource *ifc_msix_mem; 184 185 struct if_irq ifc_legacy_irq; 186 struct grouptask ifc_admin_task; 187 struct grouptask ifc_vflr_task; 188 struct iflib_filter_info ifc_filter_info; 189 struct ifmedia ifc_media; 190 191 struct sysctl_oid *ifc_sysctl_node; 192 uint16_t ifc_sysctl_ntxqs; 193 uint16_t ifc_sysctl_nrxqs; 194 uint16_t ifc_sysctl_qs_eq_override; 195 uint16_t ifc_sysctl_rx_budget; 196 197 qidx_t ifc_sysctl_ntxds[8]; 198 qidx_t ifc_sysctl_nrxds[8]; 199 struct if_txrx ifc_txrx; 200 #define isc_txd_encap ifc_txrx.ift_txd_encap 201 #define isc_txd_flush ifc_txrx.ift_txd_flush 202 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 203 #define isc_rxd_available ifc_txrx.ift_rxd_available 204 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 205 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 206 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 209 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 210 eventhandler_tag ifc_vlan_attach_event; 211 eventhandler_tag ifc_vlan_detach_event; 212 uint8_t ifc_mac[ETHER_ADDR_LEN]; 213 char ifc_mtx_name[16]; 214 }; 215 216 217 void * 218 iflib_get_softc(if_ctx_t ctx) 219 { 220 221 return (ctx->ifc_softc); 222 } 223 224 device_t 225 iflib_get_dev(if_ctx_t ctx) 226 { 227 228 return (ctx->ifc_dev); 229 } 230 231 if_t 232 iflib_get_ifp(if_ctx_t ctx) 233 { 234 235 return (ctx->ifc_ifp); 236 } 237 238 struct ifmedia * 239 iflib_get_media(if_ctx_t ctx) 240 { 241 242 return (&ctx->ifc_media); 243 } 244 245 void 246 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 247 { 248 249 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 250 } 251 252 if_softc_ctx_t 253 iflib_get_softc_ctx(if_ctx_t ctx) 254 { 255 256 return (&ctx->ifc_softc_ctx); 257 } 258 259 if_shared_ctx_t 260 iflib_get_sctx(if_ctx_t ctx) 261 { 262 263 return (ctx->ifc_sctx); 264 } 265 266 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 267 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 268 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 269 270 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 271 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 272 273 #define RX_SW_DESC_MAP_CREATED (1 << 0) 274 #define TX_SW_DESC_MAP_CREATED (1 << 1) 275 #define RX_SW_DESC_INUSE (1 << 3) 276 #define TX_SW_DESC_MAPPED (1 << 4) 277 278 #define M_TOOBIG M_PROTO1 279 280 typedef struct iflib_sw_rx_desc_array { 281 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 282 struct mbuf **ifsd_m; /* pkthdr mbufs */ 283 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 284 uint8_t *ifsd_flags; 285 } iflib_rxsd_array_t; 286 287 typedef struct iflib_sw_tx_desc_array { 288 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 289 struct mbuf **ifsd_m; /* pkthdr mbufs */ 290 uint8_t *ifsd_flags; 291 } if_txsd_vec_t; 292 293 294 /* magic number that should be high enough for any hardware */ 295 #define IFLIB_MAX_TX_SEGS 128 296 /* bnxt supports 64 with hardware LRO enabled */ 297 #define IFLIB_MAX_RX_SEGS 64 298 #define IFLIB_RX_COPY_THRESH 128 299 #define IFLIB_MAX_RX_REFRESH 32 300 /* The minimum descriptors per second before we start coalescing */ 301 #define IFLIB_MIN_DESC_SEC 16384 302 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 303 #define IFLIB_QUEUE_IDLE 0 304 #define IFLIB_QUEUE_HUNG 1 305 #define IFLIB_QUEUE_WORKING 2 306 /* maximum number of txqs that can share an rx interrupt */ 307 #define IFLIB_MAX_TX_SHARED_INTR 4 308 309 /* this should really scale with ring size - this is a fairly arbitrary value */ 310 #define TX_BATCH_SIZE 32 311 312 #define IFLIB_RESTART_BUDGET 8 313 314 #define IFC_LEGACY 0x001 315 #define IFC_QFLUSH 0x002 316 #define IFC_MULTISEG 0x004 317 #define IFC_DMAR 0x008 318 #define IFC_SC_ALLOCATED 0x010 319 #define IFC_INIT_DONE 0x020 320 #define IFC_PREFETCH 0x040 321 #define IFC_DO_RESET 0x080 322 #define IFC_DO_WATCHDOG 0x100 323 #define IFC_CHECK_HUNG 0x200 324 325 326 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 327 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 328 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 329 struct iflib_txq { 330 qidx_t ift_in_use; 331 qidx_t ift_cidx; 332 qidx_t ift_cidx_processed; 333 qidx_t ift_pidx; 334 uint8_t ift_gen; 335 uint8_t ift_br_offset; 336 uint16_t ift_npending; 337 uint16_t ift_db_pending; 338 uint16_t ift_rs_pending; 339 /* implicit pad */ 340 uint8_t ift_txd_size[8]; 341 uint64_t ift_processed; 342 uint64_t ift_cleaned; 343 uint64_t ift_cleaned_prev; 344 #if MEMORY_LOGGING 345 uint64_t ift_enqueued; 346 uint64_t ift_dequeued; 347 #endif 348 uint64_t ift_no_tx_dma_setup; 349 uint64_t ift_no_desc_avail; 350 uint64_t ift_mbuf_defrag_failed; 351 uint64_t ift_mbuf_defrag; 352 uint64_t ift_map_failed; 353 uint64_t ift_txd_encap_efbig; 354 uint64_t ift_pullups; 355 356 struct mtx ift_mtx; 357 struct mtx ift_db_mtx; 358 359 /* constant values */ 360 if_ctx_t ift_ctx; 361 struct ifmp_ring *ift_br; 362 struct grouptask ift_task; 363 qidx_t ift_size; 364 uint16_t ift_id; 365 struct callout ift_timer; 366 367 if_txsd_vec_t ift_sds; 368 uint8_t ift_qstatus; 369 uint8_t ift_closed; 370 uint8_t ift_update_freq; 371 struct iflib_filter_info ift_filter_info; 372 bus_dma_tag_t ift_desc_tag; 373 bus_dma_tag_t ift_tso_desc_tag; 374 iflib_dma_info_t ift_ifdi; 375 #define MTX_NAME_LEN 16 376 char ift_mtx_name[MTX_NAME_LEN]; 377 char ift_db_mtx_name[MTX_NAME_LEN]; 378 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 379 #ifdef IFLIB_DIAGNOSTICS 380 uint64_t ift_cpu_exec_count[256]; 381 #endif 382 } __aligned(CACHE_LINE_SIZE); 383 384 struct iflib_fl { 385 qidx_t ifl_cidx; 386 qidx_t ifl_pidx; 387 qidx_t ifl_credits; 388 uint8_t ifl_gen; 389 uint8_t ifl_rxd_size; 390 #if MEMORY_LOGGING 391 uint64_t ifl_m_enqueued; 392 uint64_t ifl_m_dequeued; 393 uint64_t ifl_cl_enqueued; 394 uint64_t ifl_cl_dequeued; 395 #endif 396 /* implicit pad */ 397 398 bitstr_t *ifl_rx_bitmap; 399 qidx_t ifl_fragidx; 400 /* constant */ 401 qidx_t ifl_size; 402 uint16_t ifl_buf_size; 403 uint16_t ifl_cltype; 404 uma_zone_t ifl_zone; 405 iflib_rxsd_array_t ifl_sds; 406 iflib_rxq_t ifl_rxq; 407 uint8_t ifl_id; 408 bus_dma_tag_t ifl_desc_tag; 409 iflib_dma_info_t ifl_ifdi; 410 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 411 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 412 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 413 } __aligned(CACHE_LINE_SIZE); 414 415 static inline qidx_t 416 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 417 { 418 qidx_t used; 419 420 if (pidx > cidx) 421 used = pidx - cidx; 422 else if (pidx < cidx) 423 used = size - cidx + pidx; 424 else if (gen == 0 && pidx == cidx) 425 used = 0; 426 else if (gen == 1 && pidx == cidx) 427 used = size; 428 else 429 panic("bad state"); 430 431 return (used); 432 } 433 434 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 435 436 #define IDXDIFF(head, tail, wrap) \ 437 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 438 439 struct iflib_rxq { 440 /* If there is a separate completion queue - 441 * these are the cq cidx and pidx. Otherwise 442 * these are unused. 443 */ 444 qidx_t ifr_size; 445 qidx_t ifr_cq_cidx; 446 qidx_t ifr_cq_pidx; 447 uint8_t ifr_cq_gen; 448 uint8_t ifr_fl_offset; 449 450 if_ctx_t ifr_ctx; 451 iflib_fl_t ifr_fl; 452 uint64_t ifr_rx_irq; 453 uint16_t ifr_id; 454 uint8_t ifr_lro_enabled; 455 uint8_t ifr_nfl; 456 uint8_t ifr_ntxqirq; 457 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 458 struct lro_ctrl ifr_lc; 459 struct grouptask ifr_task; 460 struct iflib_filter_info ifr_filter_info; 461 iflib_dma_info_t ifr_ifdi; 462 463 /* dynamically allocate if any drivers need a value substantially larger than this */ 464 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 465 #ifdef IFLIB_DIAGNOSTICS 466 uint64_t ifr_cpu_exec_count[256]; 467 #endif 468 } __aligned(CACHE_LINE_SIZE); 469 470 typedef struct if_rxsd { 471 caddr_t *ifsd_cl; 472 struct mbuf **ifsd_m; 473 iflib_fl_t ifsd_fl; 474 qidx_t ifsd_cidx; 475 } *if_rxsd_t; 476 477 /* multiple of word size */ 478 #ifdef __LP64__ 479 #define PKT_INFO_SIZE 6 480 #define RXD_INFO_SIZE 5 481 #define PKT_TYPE uint64_t 482 #else 483 #define PKT_INFO_SIZE 11 484 #define RXD_INFO_SIZE 8 485 #define PKT_TYPE uint32_t 486 #endif 487 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 488 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 489 490 typedef struct if_pkt_info_pad { 491 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 492 } *if_pkt_info_pad_t; 493 typedef struct if_rxd_info_pad { 494 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 495 } *if_rxd_info_pad_t; 496 497 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 498 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 499 500 501 static inline void 502 pkt_info_zero(if_pkt_info_t pi) 503 { 504 if_pkt_info_pad_t pi_pad; 505 506 pi_pad = (if_pkt_info_pad_t)pi; 507 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 508 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 509 #ifndef __LP64__ 510 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 511 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 512 #endif 513 } 514 515 static inline void 516 rxd_info_zero(if_rxd_info_t ri) 517 { 518 if_rxd_info_pad_t ri_pad; 519 int i; 520 521 ri_pad = (if_rxd_info_pad_t)ri; 522 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 523 ri_pad->rxd_val[i] = 0; 524 ri_pad->rxd_val[i+1] = 0; 525 ri_pad->rxd_val[i+2] = 0; 526 ri_pad->rxd_val[i+3] = 0; 527 } 528 #ifdef __LP64__ 529 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 530 #endif 531 } 532 533 /* 534 * Only allow a single packet to take up most 1/nth of the tx ring 535 */ 536 #define MAX_SINGLE_PACKET_FRACTION 12 537 #define IF_BAD_DMA (bus_addr_t)-1 538 539 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 540 541 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_ctx_mtx, _name, "iflib ctx lock", MTX_DEF) 542 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_ctx_mtx) 543 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_ctx_mtx) 544 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_ctx_mtx) 545 546 547 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 548 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 549 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 550 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 551 552 553 554 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 555 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 556 557 558 /* Our boot-time initialization hook */ 559 static int iflib_module_event_handler(module_t, int, void *); 560 561 static moduledata_t iflib_moduledata = { 562 "iflib", 563 iflib_module_event_handler, 564 NULL 565 }; 566 567 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 568 MODULE_VERSION(iflib, 1); 569 570 MODULE_DEPEND(iflib, pci, 1, 1, 1); 571 MODULE_DEPEND(iflib, ether, 1, 1, 1); 572 573 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 574 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 575 576 #ifndef IFLIB_DEBUG_COUNTERS 577 #ifdef INVARIANTS 578 #define IFLIB_DEBUG_COUNTERS 1 579 #else 580 #define IFLIB_DEBUG_COUNTERS 0 581 #endif /* !INVARIANTS */ 582 #endif 583 584 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 585 "iflib driver parameters"); 586 587 /* 588 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 589 */ 590 static int iflib_min_tx_latency = 0; 591 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 592 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 593 static int iflib_no_tx_batch = 0; 594 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 595 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 596 597 598 #if IFLIB_DEBUG_COUNTERS 599 600 static int iflib_tx_seen; 601 static int iflib_tx_sent; 602 static int iflib_tx_encap; 603 static int iflib_rx_allocs; 604 static int iflib_fl_refills; 605 static int iflib_fl_refills_large; 606 static int iflib_tx_frees; 607 608 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 609 &iflib_tx_seen, 0, "# tx mbufs seen"); 610 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 611 &iflib_tx_sent, 0, "# tx mbufs sent"); 612 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 613 &iflib_tx_encap, 0, "# tx mbufs encapped"); 614 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 615 &iflib_tx_frees, 0, "# tx frees"); 616 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 617 &iflib_rx_allocs, 0, "# rx allocations"); 618 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 619 &iflib_fl_refills, 0, "# refills"); 620 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 621 &iflib_fl_refills_large, 0, "# large refills"); 622 623 624 static int iflib_txq_drain_flushing; 625 static int iflib_txq_drain_oactive; 626 static int iflib_txq_drain_notready; 627 static int iflib_txq_drain_encapfail; 628 629 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 630 &iflib_txq_drain_flushing, 0, "# drain flushes"); 631 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 632 &iflib_txq_drain_oactive, 0, "# drain oactives"); 633 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 634 &iflib_txq_drain_notready, 0, "# drain notready"); 635 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 636 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 637 638 639 static int iflib_encap_load_mbuf_fail; 640 static int iflib_encap_pad_mbuf_fail; 641 static int iflib_encap_txq_avail_fail; 642 static int iflib_encap_txd_encap_fail; 643 644 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 645 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 646 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 647 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 648 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 649 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 650 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 651 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 652 653 static int iflib_task_fn_rxs; 654 static int iflib_rx_intr_enables; 655 static int iflib_fast_intrs; 656 static int iflib_intr_link; 657 static int iflib_intr_msix; 658 static int iflib_rx_unavail; 659 static int iflib_rx_ctx_inactive; 660 static int iflib_rx_zero_len; 661 static int iflib_rx_if_input; 662 static int iflib_rx_mbuf_null; 663 static int iflib_rxd_flush; 664 665 static int iflib_verbose_debug; 666 667 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 668 &iflib_intr_link, 0, "# intr link calls"); 669 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 670 &iflib_intr_msix, 0, "# intr msix calls"); 671 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 672 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 673 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 674 &iflib_rx_intr_enables, 0, "# rx intr enables"); 675 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 676 &iflib_fast_intrs, 0, "# fast_intr calls"); 677 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 678 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 679 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 680 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 681 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 682 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 683 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 684 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 685 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 686 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 687 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 688 &iflib_rxd_flush, 0, "# times rxd_flush called"); 689 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 690 &iflib_verbose_debug, 0, "enable verbose debugging"); 691 692 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 693 static void 694 iflib_debug_reset(void) 695 { 696 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 697 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 698 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 699 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 700 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 701 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 702 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 703 iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 704 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 705 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 706 } 707 708 #else 709 #define DBG_COUNTER_INC(name) 710 static void iflib_debug_reset(void) {} 711 #endif 712 713 714 715 #define IFLIB_DEBUG 0 716 717 static void iflib_tx_structures_free(if_ctx_t ctx); 718 static void iflib_rx_structures_free(if_ctx_t ctx); 719 static int iflib_queues_alloc(if_ctx_t ctx); 720 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 721 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 722 static int iflib_qset_structures_setup(if_ctx_t ctx); 723 static int iflib_msix_init(if_ctx_t ctx); 724 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str); 725 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 726 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 727 static int iflib_register(if_ctx_t); 728 static void iflib_init_locked(if_ctx_t ctx); 729 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 730 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 731 static void iflib_ifmp_purge(iflib_txq_t txq); 732 static void _iflib_pre_assert(if_softc_ctx_t scctx); 733 static void iflib_stop(if_ctx_t ctx); 734 static void iflib_if_init_locked(if_ctx_t ctx); 735 #ifndef __NO_STRICT_ALIGNMENT 736 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 737 #endif 738 739 #ifdef DEV_NETMAP 740 #include <sys/selinfo.h> 741 #include <net/netmap.h> 742 #include <dev/netmap/netmap_kern.h> 743 744 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 745 746 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 747 748 /* 749 * device-specific sysctl variables: 750 * 751 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 752 * During regular operations the CRC is stripped, but on some 753 * hardware reception of frames not multiple of 64 is slower, 754 * so using crcstrip=0 helps in benchmarks. 755 * 756 * iflib_rx_miss, iflib_rx_miss_bufs: 757 * count packets that might be missed due to lost interrupts. 758 */ 759 SYSCTL_DECL(_dev_netmap); 760 /* 761 * The xl driver by default strips CRCs and we do not override it. 762 */ 763 764 int iflib_crcstrip = 1; 765 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 766 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 767 768 int iflib_rx_miss, iflib_rx_miss_bufs; 769 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 770 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 771 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 772 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 773 774 /* 775 * Register/unregister. We are already under netmap lock. 776 * Only called on the first register or the last unregister. 777 */ 778 static int 779 iflib_netmap_register(struct netmap_adapter *na, int onoff) 780 { 781 struct ifnet *ifp = na->ifp; 782 if_ctx_t ctx = ifp->if_softc; 783 int status; 784 785 CTX_LOCK(ctx); 786 IFDI_INTR_DISABLE(ctx); 787 788 /* Tell the stack that the interface is no longer active */ 789 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 790 791 if (!CTX_IS_VF(ctx)) 792 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 793 794 /* enable or disable flags and callbacks in na and ifp */ 795 if (onoff) { 796 nm_set_native_flags(na); 797 } else { 798 nm_clear_native_flags(na); 799 } 800 iflib_stop(ctx); 801 iflib_init_locked(ctx); 802 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 803 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 804 if (status) 805 nm_clear_native_flags(na); 806 CTX_UNLOCK(ctx); 807 return (status); 808 } 809 810 static int 811 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 812 { 813 struct netmap_adapter *na = kring->na; 814 u_int const lim = kring->nkr_num_slots - 1; 815 u_int head = kring->rhead; 816 struct netmap_ring *ring = kring->ring; 817 bus_dmamap_t *map; 818 struct if_rxd_update iru; 819 if_ctx_t ctx = rxq->ifr_ctx; 820 iflib_fl_t fl = &rxq->ifr_fl[0]; 821 uint32_t refill_pidx, nic_i; 822 823 if (nm_i == head && __predict_true(!init)) 824 return 0; 825 iru_init(&iru, rxq, 0 /* flid */); 826 map = fl->ifl_sds.ifsd_map; 827 refill_pidx = netmap_idx_k2n(kring, nm_i); 828 /* 829 * IMPORTANT: we must leave one free slot in the ring, 830 * so move head back by one unit 831 */ 832 head = nm_prev(head, lim); 833 while (nm_i != head) { 834 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 835 struct netmap_slot *slot = &ring->slot[nm_i]; 836 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 837 uint32_t nic_i_dma = refill_pidx; 838 nic_i = netmap_idx_k2n(kring, nm_i); 839 840 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 841 842 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 843 return netmap_ring_reinit(kring); 844 845 fl->ifl_vm_addrs[tmp_pidx] = addr; 846 if (__predict_false(init) && map) { 847 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 848 } else if (map && (slot->flags & NS_BUF_CHANGED)) { 849 /* buffer has changed, reload map */ 850 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 851 } 852 slot->flags &= ~NS_BUF_CHANGED; 853 854 nm_i = nm_next(nm_i, lim); 855 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 856 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 857 continue; 858 859 iru.iru_pidx = refill_pidx; 860 iru.iru_count = tmp_pidx+1; 861 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 862 863 refill_pidx = nic_i; 864 if (map == NULL) 865 continue; 866 867 for (int n = 0; n < iru.iru_count; n++) { 868 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma], 869 BUS_DMASYNC_PREREAD); 870 /* XXX - change this to not use the netmap func*/ 871 nic_i_dma = nm_next(nic_i_dma, lim); 872 } 873 } 874 } 875 kring->nr_hwcur = head; 876 877 if (map) 878 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 879 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 880 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 881 return (0); 882 } 883 884 /* 885 * Reconcile kernel and user view of the transmit ring. 886 * 887 * All information is in the kring. 888 * Userspace wants to send packets up to the one before kring->rhead, 889 * kernel knows kring->nr_hwcur is the first unsent packet. 890 * 891 * Here we push packets out (as many as possible), and possibly 892 * reclaim buffers from previously completed transmission. 893 * 894 * The caller (netmap) guarantees that there is only one instance 895 * running at any time. Any interference with other driver 896 * methods should be handled by the individual drivers. 897 */ 898 static int 899 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 900 { 901 struct netmap_adapter *na = kring->na; 902 struct ifnet *ifp = na->ifp; 903 struct netmap_ring *ring = kring->ring; 904 u_int nm_i; /* index into the netmap ring */ 905 u_int nic_i; /* index into the NIC ring */ 906 u_int n; 907 u_int const lim = kring->nkr_num_slots - 1; 908 u_int const head = kring->rhead; 909 struct if_pkt_info pi; 910 911 /* 912 * interrupts on every tx packet are expensive so request 913 * them every half ring, or where NS_REPORT is set 914 */ 915 u_int report_frequency = kring->nkr_num_slots >> 1; 916 /* device-specific */ 917 if_ctx_t ctx = ifp->if_softc; 918 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 919 920 if (txq->ift_sds.ifsd_map) 921 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 922 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 923 924 925 /* 926 * First part: process new packets to send. 927 * nm_i is the current index in the netmap ring, 928 * nic_i is the corresponding index in the NIC ring. 929 * 930 * If we have packets to send (nm_i != head) 931 * iterate over the netmap ring, fetch length and update 932 * the corresponding slot in the NIC ring. Some drivers also 933 * need to update the buffer's physical address in the NIC slot 934 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 935 * 936 * The netmap_reload_map() calls is especially expensive, 937 * even when (as in this case) the tag is 0, so do only 938 * when the buffer has actually changed. 939 * 940 * If possible do not set the report/intr bit on all slots, 941 * but only a few times per ring or when NS_REPORT is set. 942 * 943 * Finally, on 10G and faster drivers, it might be useful 944 * to prefetch the next slot and txr entry. 945 */ 946 947 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 948 pkt_info_zero(&pi); 949 pi.ipi_segs = txq->ift_segs; 950 pi.ipi_qsidx = kring->ring_id; 951 if (nm_i != head) { /* we have new packets to send */ 952 nic_i = netmap_idx_k2n(kring, nm_i); 953 954 __builtin_prefetch(&ring->slot[nm_i]); 955 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 956 if (txq->ift_sds.ifsd_map) 957 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 958 959 for (n = 0; nm_i != head; n++) { 960 struct netmap_slot *slot = &ring->slot[nm_i]; 961 u_int len = slot->len; 962 uint64_t paddr; 963 void *addr = PNMB(na, slot, &paddr); 964 int flags = (slot->flags & NS_REPORT || 965 nic_i == 0 || nic_i == report_frequency) ? 966 IPI_TX_INTR : 0; 967 968 /* device-specific */ 969 pi.ipi_len = len; 970 pi.ipi_segs[0].ds_addr = paddr; 971 pi.ipi_segs[0].ds_len = len; 972 pi.ipi_nsegs = 1; 973 pi.ipi_ndescs = 0; 974 pi.ipi_pidx = nic_i; 975 pi.ipi_flags = flags; 976 977 /* Fill the slot in the NIC ring. */ 978 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 979 980 /* prefetch for next round */ 981 __builtin_prefetch(&ring->slot[nm_i + 1]); 982 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 983 if (txq->ift_sds.ifsd_map) { 984 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 985 986 NM_CHECK_ADDR_LEN(na, addr, len); 987 988 if (slot->flags & NS_BUF_CHANGED) { 989 /* buffer has changed, reload map */ 990 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 991 } 992 /* make sure changes to the buffer are synced */ 993 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 994 BUS_DMASYNC_PREWRITE); 995 } 996 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 997 nm_i = nm_next(nm_i, lim); 998 nic_i = nm_next(nic_i, lim); 999 } 1000 kring->nr_hwcur = head; 1001 1002 /* synchronize the NIC ring */ 1003 if (txq->ift_sds.ifsd_map) 1004 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 1005 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1006 1007 /* (re)start the tx unit up to slot nic_i (excluded) */ 1008 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1009 } 1010 1011 /* 1012 * Second part: reclaim buffers for completed transmissions. 1013 */ 1014 if (iflib_tx_credits_update(ctx, txq)) { 1015 /* some tx completed, increment avail */ 1016 nic_i = txq->ift_cidx_processed; 1017 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1018 } 1019 return (0); 1020 } 1021 1022 /* 1023 * Reconcile kernel and user view of the receive ring. 1024 * Same as for the txsync, this routine must be efficient. 1025 * The caller guarantees a single invocations, but races against 1026 * the rest of the driver should be handled here. 1027 * 1028 * On call, kring->rhead is the first packet that userspace wants 1029 * to keep, and kring->rcur is the wakeup point. 1030 * The kernel has previously reported packets up to kring->rtail. 1031 * 1032 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1033 * of whether or not we received an interrupt. 1034 */ 1035 static int 1036 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1037 { 1038 struct netmap_adapter *na = kring->na; 1039 struct netmap_ring *ring = kring->ring; 1040 uint32_t nm_i; /* index into the netmap ring */ 1041 uint32_t nic_i; /* index into the NIC ring */ 1042 u_int i, n; 1043 u_int const lim = kring->nkr_num_slots - 1; 1044 u_int const head = netmap_idx_n2k(kring, kring->rhead); 1045 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1046 struct if_rxd_info ri; 1047 1048 struct ifnet *ifp = na->ifp; 1049 if_ctx_t ctx = ifp->if_softc; 1050 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1051 iflib_fl_t fl = rxq->ifr_fl; 1052 if (head > lim) 1053 return netmap_ring_reinit(kring); 1054 1055 /* XXX check sync modes */ 1056 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1057 if (fl->ifl_sds.ifsd_map == NULL) 1058 continue; 1059 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 1060 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1061 } 1062 /* 1063 * First part: import newly received packets. 1064 * 1065 * nm_i is the index of the next free slot in the netmap ring, 1066 * nic_i is the index of the next received packet in the NIC ring, 1067 * and they may differ in case if_init() has been called while 1068 * in netmap mode. For the receive ring we have 1069 * 1070 * nic_i = rxr->next_check; 1071 * nm_i = kring->nr_hwtail (previous) 1072 * and 1073 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1074 * 1075 * rxr->next_check is set to 0 on a ring reinit 1076 */ 1077 if (netmap_no_pendintr || force_update) { 1078 int crclen = iflib_crcstrip ? 0 : 4; 1079 int error, avail; 1080 1081 for (i = 0; i < rxq->ifr_nfl; i++) { 1082 fl = &rxq->ifr_fl[i]; 1083 nic_i = fl->ifl_cidx; 1084 nm_i = netmap_idx_n2k(kring, nic_i); 1085 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 1086 for (n = 0; avail > 0; n++, avail--) { 1087 rxd_info_zero(&ri); 1088 ri.iri_frags = rxq->ifr_frags; 1089 ri.iri_qsidx = kring->ring_id; 1090 ri.iri_ifp = ctx->ifc_ifp; 1091 ri.iri_cidx = nic_i; 1092 1093 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1094 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1095 ring->slot[nm_i].flags = 0; 1096 if (fl->ifl_sds.ifsd_map) 1097 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1098 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1099 nm_i = nm_next(nm_i, lim); 1100 nic_i = nm_next(nic_i, lim); 1101 } 1102 if (n) { /* update the state variables */ 1103 if (netmap_no_pendintr && !force_update) { 1104 /* diagnostics */ 1105 iflib_rx_miss ++; 1106 iflib_rx_miss_bufs += n; 1107 } 1108 fl->ifl_cidx = nic_i; 1109 kring->nr_hwtail = netmap_idx_k2n(kring, nm_i); 1110 } 1111 kring->nr_kflags &= ~NKR_PENDINTR; 1112 } 1113 } 1114 /* 1115 * Second part: skip past packets that userspace has released. 1116 * (kring->nr_hwcur to head excluded), 1117 * and make the buffers available for reception. 1118 * As usual nm_i is the index in the netmap ring, 1119 * nic_i is the index in the NIC ring, and 1120 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1121 */ 1122 /* XXX not sure how this will work with multiple free lists */ 1123 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 1124 1125 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1126 } 1127 1128 static void 1129 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1130 { 1131 struct ifnet *ifp = na->ifp; 1132 if_ctx_t ctx = ifp->if_softc; 1133 1134 CTX_LOCK(ctx); 1135 if (onoff) { 1136 IFDI_INTR_ENABLE(ctx); 1137 } else { 1138 IFDI_INTR_DISABLE(ctx); 1139 } 1140 CTX_UNLOCK(ctx); 1141 } 1142 1143 1144 static int 1145 iflib_netmap_attach(if_ctx_t ctx) 1146 { 1147 struct netmap_adapter na; 1148 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1149 1150 bzero(&na, sizeof(na)); 1151 1152 na.ifp = ctx->ifc_ifp; 1153 na.na_flags = NAF_BDG_MAYSLEEP; 1154 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1155 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1156 1157 na.num_tx_desc = scctx->isc_ntxd[0]; 1158 na.num_rx_desc = scctx->isc_nrxd[0]; 1159 na.nm_txsync = iflib_netmap_txsync; 1160 na.nm_rxsync = iflib_netmap_rxsync; 1161 na.nm_register = iflib_netmap_register; 1162 na.nm_intr = iflib_netmap_intr; 1163 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1164 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1165 return (netmap_attach(&na)); 1166 } 1167 1168 static void 1169 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1170 { 1171 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1172 struct netmap_slot *slot; 1173 1174 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1175 if (slot == NULL) 1176 return; 1177 if (txq->ift_sds.ifsd_map == NULL) 1178 return; 1179 1180 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1181 1182 /* 1183 * In netmap mode, set the map for the packet buffer. 1184 * NOTE: Some drivers (not this one) also need to set 1185 * the physical buffer address in the NIC ring. 1186 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1187 * netmap slot index, si 1188 */ 1189 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i); 1190 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1191 } 1192 } 1193 1194 static void 1195 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1196 { 1197 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1198 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id]; 1199 struct netmap_slot *slot; 1200 uint32_t nm_i; 1201 1202 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1203 if (slot == NULL) 1204 return; 1205 nm_i = netmap_idx_n2k(kring, 0); 1206 netmap_fl_refill(rxq, kring, nm_i, true); 1207 } 1208 1209 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1210 1211 #else 1212 #define iflib_netmap_txq_init(ctx, txq) 1213 #define iflib_netmap_rxq_init(ctx, rxq) 1214 #define iflib_netmap_detach(ifp) 1215 1216 #define iflib_netmap_attach(ctx) (0) 1217 #define netmap_rx_irq(ifp, qid, budget) (0) 1218 #define netmap_tx_irq(ifp, qid) do {} while (0) 1219 1220 #endif 1221 1222 #if defined(__i386__) || defined(__amd64__) 1223 static __inline void 1224 prefetch(void *x) 1225 { 1226 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1227 } 1228 static __inline void 1229 prefetch2cachelines(void *x) 1230 { 1231 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1232 #if (CACHE_LINE_SIZE < 128) 1233 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1234 #endif 1235 } 1236 #else 1237 #define prefetch(x) 1238 #define prefetch2cachelines(x) 1239 #endif 1240 1241 static void 1242 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1243 { 1244 iflib_fl_t fl; 1245 1246 fl = &rxq->ifr_fl[flid]; 1247 iru->iru_paddrs = fl->ifl_bus_addrs; 1248 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1249 iru->iru_idxs = fl->ifl_rxd_idxs; 1250 iru->iru_qsidx = rxq->ifr_id; 1251 iru->iru_buf_size = fl->ifl_buf_size; 1252 iru->iru_flidx = fl->ifl_id; 1253 } 1254 1255 static void 1256 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1257 { 1258 if (err) 1259 return; 1260 *(bus_addr_t *) arg = segs[0].ds_addr; 1261 } 1262 1263 int 1264 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1265 { 1266 int err; 1267 if_shared_ctx_t sctx = ctx->ifc_sctx; 1268 device_t dev = ctx->ifc_dev; 1269 1270 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1271 1272 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1273 sctx->isc_q_align, 0, /* alignment, bounds */ 1274 BUS_SPACE_MAXADDR, /* lowaddr */ 1275 BUS_SPACE_MAXADDR, /* highaddr */ 1276 NULL, NULL, /* filter, filterarg */ 1277 size, /* maxsize */ 1278 1, /* nsegments */ 1279 size, /* maxsegsize */ 1280 BUS_DMA_ALLOCNOW, /* flags */ 1281 NULL, /* lockfunc */ 1282 NULL, /* lockarg */ 1283 &dma->idi_tag); 1284 if (err) { 1285 device_printf(dev, 1286 "%s: bus_dma_tag_create failed: %d\n", 1287 __func__, err); 1288 goto fail_0; 1289 } 1290 1291 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1292 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1293 if (err) { 1294 device_printf(dev, 1295 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1296 __func__, (uintmax_t)size, err); 1297 goto fail_1; 1298 } 1299 1300 dma->idi_paddr = IF_BAD_DMA; 1301 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1302 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1303 if (err || dma->idi_paddr == IF_BAD_DMA) { 1304 device_printf(dev, 1305 "%s: bus_dmamap_load failed: %d\n", 1306 __func__, err); 1307 goto fail_2; 1308 } 1309 1310 dma->idi_size = size; 1311 return (0); 1312 1313 fail_2: 1314 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1315 fail_1: 1316 bus_dma_tag_destroy(dma->idi_tag); 1317 fail_0: 1318 dma->idi_tag = NULL; 1319 1320 return (err); 1321 } 1322 1323 int 1324 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1325 { 1326 int i, err; 1327 iflib_dma_info_t *dmaiter; 1328 1329 dmaiter = dmalist; 1330 for (i = 0; i < count; i++, dmaiter++) { 1331 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1332 break; 1333 } 1334 if (err) 1335 iflib_dma_free_multi(dmalist, i); 1336 return (err); 1337 } 1338 1339 void 1340 iflib_dma_free(iflib_dma_info_t dma) 1341 { 1342 if (dma->idi_tag == NULL) 1343 return; 1344 if (dma->idi_paddr != IF_BAD_DMA) { 1345 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1346 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1347 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1348 dma->idi_paddr = IF_BAD_DMA; 1349 } 1350 if (dma->idi_vaddr != NULL) { 1351 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1352 dma->idi_vaddr = NULL; 1353 } 1354 bus_dma_tag_destroy(dma->idi_tag); 1355 dma->idi_tag = NULL; 1356 } 1357 1358 void 1359 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1360 { 1361 int i; 1362 iflib_dma_info_t *dmaiter = dmalist; 1363 1364 for (i = 0; i < count; i++, dmaiter++) 1365 iflib_dma_free(*dmaiter); 1366 } 1367 1368 #ifdef EARLY_AP_STARTUP 1369 static const int iflib_started = 1; 1370 #else 1371 /* 1372 * We used to abuse the smp_started flag to decide if the queues have been 1373 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1374 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1375 * is set. Run a SYSINIT() strictly after that to just set a usable 1376 * completion flag. 1377 */ 1378 1379 static int iflib_started; 1380 1381 static void 1382 iflib_record_started(void *arg) 1383 { 1384 iflib_started = 1; 1385 } 1386 1387 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1388 iflib_record_started, NULL); 1389 #endif 1390 1391 static int 1392 iflib_fast_intr(void *arg) 1393 { 1394 iflib_filter_info_t info = arg; 1395 struct grouptask *gtask = info->ifi_task; 1396 if (!iflib_started) 1397 return (FILTER_HANDLED); 1398 1399 DBG_COUNTER_INC(fast_intrs); 1400 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1401 return (FILTER_HANDLED); 1402 1403 GROUPTASK_ENQUEUE(gtask); 1404 return (FILTER_HANDLED); 1405 } 1406 1407 static int 1408 iflib_fast_intr_rxtx(void *arg) 1409 { 1410 iflib_filter_info_t info = arg; 1411 struct grouptask *gtask = info->ifi_task; 1412 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1413 if_ctx_t ctx; 1414 int i, cidx; 1415 1416 if (!iflib_started) 1417 return (FILTER_HANDLED); 1418 1419 DBG_COUNTER_INC(fast_intrs); 1420 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1421 return (FILTER_HANDLED); 1422 1423 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1424 qidx_t txqid = rxq->ifr_txqid[i]; 1425 1426 ctx = rxq->ifr_ctx; 1427 1428 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1429 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1430 continue; 1431 } 1432 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1433 } 1434 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1435 cidx = rxq->ifr_cq_cidx; 1436 else 1437 cidx = rxq->ifr_fl[0].ifl_cidx; 1438 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1439 GROUPTASK_ENQUEUE(gtask); 1440 else 1441 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1442 return (FILTER_HANDLED); 1443 } 1444 1445 1446 static int 1447 iflib_fast_intr_ctx(void *arg) 1448 { 1449 iflib_filter_info_t info = arg; 1450 struct grouptask *gtask = info->ifi_task; 1451 1452 if (!iflib_started) 1453 return (FILTER_HANDLED); 1454 1455 DBG_COUNTER_INC(fast_intrs); 1456 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1457 return (FILTER_HANDLED); 1458 1459 GROUPTASK_ENQUEUE(gtask); 1460 return (FILTER_HANDLED); 1461 } 1462 1463 static int 1464 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1465 driver_filter_t filter, driver_intr_t handler, void *arg, 1466 char *name) 1467 { 1468 int rc, flags; 1469 struct resource *res; 1470 void *tag = NULL; 1471 device_t dev = ctx->ifc_dev; 1472 1473 flags = RF_ACTIVE; 1474 if (ctx->ifc_flags & IFC_LEGACY) 1475 flags |= RF_SHAREABLE; 1476 MPASS(rid < 512); 1477 irq->ii_rid = rid; 1478 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1479 if (res == NULL) { 1480 device_printf(dev, 1481 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1482 return (ENOMEM); 1483 } 1484 irq->ii_res = res; 1485 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1486 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1487 filter, handler, arg, &tag); 1488 if (rc != 0) { 1489 device_printf(dev, 1490 "failed to setup interrupt for rid %d, name %s: %d\n", 1491 rid, name ? name : "unknown", rc); 1492 return (rc); 1493 } else if (name) 1494 bus_describe_intr(dev, res, tag, "%s", name); 1495 1496 irq->ii_tag = tag; 1497 return (0); 1498 } 1499 1500 1501 /********************************************************************* 1502 * 1503 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1504 * the information needed to transmit a packet on the wire. This is 1505 * called only once at attach, setup is done every reset. 1506 * 1507 **********************************************************************/ 1508 1509 static int 1510 iflib_txsd_alloc(iflib_txq_t txq) 1511 { 1512 if_ctx_t ctx = txq->ift_ctx; 1513 if_shared_ctx_t sctx = ctx->ifc_sctx; 1514 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1515 device_t dev = ctx->ifc_dev; 1516 int err, nsegments, ntsosegments; 1517 1518 nsegments = scctx->isc_tx_nsegments; 1519 ntsosegments = scctx->isc_tx_tso_segments_max; 1520 MPASS(scctx->isc_ntxd[0] > 0); 1521 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1522 MPASS(nsegments > 0); 1523 MPASS(ntsosegments > 0); 1524 /* 1525 * Setup DMA descriptor areas. 1526 */ 1527 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1528 1, 0, /* alignment, bounds */ 1529 BUS_SPACE_MAXADDR, /* lowaddr */ 1530 BUS_SPACE_MAXADDR, /* highaddr */ 1531 NULL, NULL, /* filter, filterarg */ 1532 sctx->isc_tx_maxsize, /* maxsize */ 1533 nsegments, /* nsegments */ 1534 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1535 0, /* flags */ 1536 NULL, /* lockfunc */ 1537 NULL, /* lockfuncarg */ 1538 &txq->ift_desc_tag))) { 1539 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1540 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1541 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1542 goto fail; 1543 } 1544 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1545 1, 0, /* alignment, bounds */ 1546 BUS_SPACE_MAXADDR, /* lowaddr */ 1547 BUS_SPACE_MAXADDR, /* highaddr */ 1548 NULL, NULL, /* filter, filterarg */ 1549 scctx->isc_tx_tso_size_max, /* maxsize */ 1550 ntsosegments, /* nsegments */ 1551 scctx->isc_tx_tso_segsize_max, /* maxsegsize */ 1552 0, /* flags */ 1553 NULL, /* lockfunc */ 1554 NULL, /* lockfuncarg */ 1555 &txq->ift_tso_desc_tag))) { 1556 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1557 1558 goto fail; 1559 } 1560 if (!(txq->ift_sds.ifsd_flags = 1561 (uint8_t *) malloc(sizeof(uint8_t) * 1562 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1563 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1564 err = ENOMEM; 1565 goto fail; 1566 } 1567 if (!(txq->ift_sds.ifsd_m = 1568 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1569 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1570 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1571 err = ENOMEM; 1572 goto fail; 1573 } 1574 1575 /* Create the descriptor buffer dma maps */ 1576 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1577 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1578 return (0); 1579 1580 if (!(txq->ift_sds.ifsd_map = 1581 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1582 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1583 err = ENOMEM; 1584 goto fail; 1585 } 1586 1587 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1588 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1589 if (err != 0) { 1590 device_printf(dev, "Unable to create TX DMA map\n"); 1591 goto fail; 1592 } 1593 } 1594 #endif 1595 return (0); 1596 fail: 1597 /* We free all, it handles case where we are in the middle */ 1598 iflib_tx_structures_free(ctx); 1599 return (err); 1600 } 1601 1602 static void 1603 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1604 { 1605 bus_dmamap_t map; 1606 1607 map = NULL; 1608 if (txq->ift_sds.ifsd_map != NULL) 1609 map = txq->ift_sds.ifsd_map[i]; 1610 if (map != NULL) { 1611 bus_dmamap_unload(txq->ift_desc_tag, map); 1612 bus_dmamap_destroy(txq->ift_desc_tag, map); 1613 txq->ift_sds.ifsd_map[i] = NULL; 1614 } 1615 } 1616 1617 static void 1618 iflib_txq_destroy(iflib_txq_t txq) 1619 { 1620 if_ctx_t ctx = txq->ift_ctx; 1621 1622 for (int i = 0; i < txq->ift_size; i++) 1623 iflib_txsd_destroy(ctx, txq, i); 1624 if (txq->ift_sds.ifsd_map != NULL) { 1625 free(txq->ift_sds.ifsd_map, M_IFLIB); 1626 txq->ift_sds.ifsd_map = NULL; 1627 } 1628 if (txq->ift_sds.ifsd_m != NULL) { 1629 free(txq->ift_sds.ifsd_m, M_IFLIB); 1630 txq->ift_sds.ifsd_m = NULL; 1631 } 1632 if (txq->ift_sds.ifsd_flags != NULL) { 1633 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1634 txq->ift_sds.ifsd_flags = NULL; 1635 } 1636 if (txq->ift_desc_tag != NULL) { 1637 bus_dma_tag_destroy(txq->ift_desc_tag); 1638 txq->ift_desc_tag = NULL; 1639 } 1640 if (txq->ift_tso_desc_tag != NULL) { 1641 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1642 txq->ift_tso_desc_tag = NULL; 1643 } 1644 } 1645 1646 static void 1647 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1648 { 1649 struct mbuf **mp; 1650 1651 mp = &txq->ift_sds.ifsd_m[i]; 1652 if (*mp == NULL) 1653 return; 1654 1655 if (txq->ift_sds.ifsd_map != NULL) { 1656 bus_dmamap_sync(txq->ift_desc_tag, 1657 txq->ift_sds.ifsd_map[i], 1658 BUS_DMASYNC_POSTWRITE); 1659 bus_dmamap_unload(txq->ift_desc_tag, 1660 txq->ift_sds.ifsd_map[i]); 1661 } 1662 m_free(*mp); 1663 DBG_COUNTER_INC(tx_frees); 1664 *mp = NULL; 1665 } 1666 1667 static int 1668 iflib_txq_setup(iflib_txq_t txq) 1669 { 1670 if_ctx_t ctx = txq->ift_ctx; 1671 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1672 iflib_dma_info_t di; 1673 int i; 1674 1675 /* Set number of descriptors available */ 1676 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1677 /* XXX make configurable */ 1678 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1679 1680 /* Reset indices */ 1681 txq->ift_cidx_processed = 0; 1682 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1683 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1684 1685 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1686 bzero((void *)di->idi_vaddr, di->idi_size); 1687 1688 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1689 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1690 bus_dmamap_sync(di->idi_tag, di->idi_map, 1691 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1692 return (0); 1693 } 1694 1695 /********************************************************************* 1696 * 1697 * Allocate memory for rx_buffer structures. Since we use one 1698 * rx_buffer per received packet, the maximum number of rx_buffer's 1699 * that we'll need is equal to the number of receive descriptors 1700 * that we've allocated. 1701 * 1702 **********************************************************************/ 1703 static int 1704 iflib_rxsd_alloc(iflib_rxq_t rxq) 1705 { 1706 if_ctx_t ctx = rxq->ifr_ctx; 1707 if_shared_ctx_t sctx = ctx->ifc_sctx; 1708 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1709 device_t dev = ctx->ifc_dev; 1710 iflib_fl_t fl; 1711 int err; 1712 1713 MPASS(scctx->isc_nrxd[0] > 0); 1714 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1715 1716 fl = rxq->ifr_fl; 1717 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1718 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1719 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1720 1, 0, /* alignment, bounds */ 1721 BUS_SPACE_MAXADDR, /* lowaddr */ 1722 BUS_SPACE_MAXADDR, /* highaddr */ 1723 NULL, NULL, /* filter, filterarg */ 1724 sctx->isc_rx_maxsize, /* maxsize */ 1725 sctx->isc_rx_nsegments, /* nsegments */ 1726 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1727 0, /* flags */ 1728 NULL, /* lockfunc */ 1729 NULL, /* lockarg */ 1730 &fl->ifl_desc_tag); 1731 if (err) { 1732 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1733 __func__, err); 1734 goto fail; 1735 } 1736 if (!(fl->ifl_sds.ifsd_flags = 1737 (uint8_t *) malloc(sizeof(uint8_t) * 1738 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1739 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1740 err = ENOMEM; 1741 goto fail; 1742 } 1743 if (!(fl->ifl_sds.ifsd_m = 1744 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1745 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1746 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1747 err = ENOMEM; 1748 goto fail; 1749 } 1750 if (!(fl->ifl_sds.ifsd_cl = 1751 (caddr_t *) malloc(sizeof(caddr_t) * 1752 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1753 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1754 err = ENOMEM; 1755 goto fail; 1756 } 1757 1758 /* Create the descriptor buffer dma maps */ 1759 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1760 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1761 continue; 1762 1763 if (!(fl->ifl_sds.ifsd_map = 1764 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1765 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1766 err = ENOMEM; 1767 goto fail; 1768 } 1769 1770 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1771 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1772 if (err != 0) { 1773 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1774 goto fail; 1775 } 1776 } 1777 #endif 1778 } 1779 return (0); 1780 1781 fail: 1782 iflib_rx_structures_free(ctx); 1783 return (err); 1784 } 1785 1786 1787 /* 1788 * Internal service routines 1789 */ 1790 1791 struct rxq_refill_cb_arg { 1792 int error; 1793 bus_dma_segment_t seg; 1794 int nseg; 1795 }; 1796 1797 static void 1798 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1799 { 1800 struct rxq_refill_cb_arg *cb_arg = arg; 1801 1802 cb_arg->error = error; 1803 cb_arg->seg = segs[0]; 1804 cb_arg->nseg = nseg; 1805 } 1806 1807 1808 #ifdef ACPI_DMAR 1809 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1810 #else 1811 #define IS_DMAR(ctx) (0) 1812 #endif 1813 1814 /** 1815 * rxq_refill - refill an rxq free-buffer list 1816 * @ctx: the iflib context 1817 * @rxq: the free-list to refill 1818 * @n: the number of new buffers to allocate 1819 * 1820 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1821 * The caller must assure that @n does not exceed the queue's capacity. 1822 */ 1823 static void 1824 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1825 { 1826 struct mbuf *m; 1827 int idx, frag_idx = fl->ifl_fragidx; 1828 int pidx = fl->ifl_pidx; 1829 caddr_t cl, *sd_cl; 1830 struct mbuf **sd_m; 1831 uint8_t *sd_flags; 1832 struct if_rxd_update iru; 1833 bus_dmamap_t *sd_map; 1834 int n, i = 0; 1835 uint64_t bus_addr; 1836 int err; 1837 qidx_t credits; 1838 1839 sd_m = fl->ifl_sds.ifsd_m; 1840 sd_map = fl->ifl_sds.ifsd_map; 1841 sd_cl = fl->ifl_sds.ifsd_cl; 1842 sd_flags = fl->ifl_sds.ifsd_flags; 1843 idx = pidx; 1844 credits = fl->ifl_credits; 1845 1846 n = count; 1847 MPASS(n > 0); 1848 MPASS(credits + n <= fl->ifl_size); 1849 1850 if (pidx < fl->ifl_cidx) 1851 MPASS(pidx + n <= fl->ifl_cidx); 1852 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1853 MPASS(fl->ifl_gen == 0); 1854 if (pidx > fl->ifl_cidx) 1855 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1856 1857 DBG_COUNTER_INC(fl_refills); 1858 if (n > 8) 1859 DBG_COUNTER_INC(fl_refills_large); 1860 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1861 while (n--) { 1862 /* 1863 * We allocate an uninitialized mbuf + cluster, mbuf is 1864 * initialized after rx. 1865 * 1866 * If the cluster is still set then we know a minimum sized packet was received 1867 */ 1868 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1869 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1870 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1871 if ((cl = sd_cl[frag_idx]) == NULL) { 1872 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1873 break; 1874 #if MEMORY_LOGGING 1875 fl->ifl_cl_enqueued++; 1876 #endif 1877 } 1878 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1879 break; 1880 } 1881 #if MEMORY_LOGGING 1882 fl->ifl_m_enqueued++; 1883 #endif 1884 1885 DBG_COUNTER_INC(rx_allocs); 1886 #if defined(__i386__) || defined(__amd64__) 1887 if (!IS_DMAR(ctx)) { 1888 bus_addr = pmap_kextract((vm_offset_t)cl); 1889 } else 1890 #endif 1891 { 1892 struct rxq_refill_cb_arg cb_arg; 1893 iflib_rxq_t q; 1894 1895 cb_arg.error = 0; 1896 q = fl->ifl_rxq; 1897 MPASS(sd_map != NULL); 1898 MPASS(sd_map[frag_idx] != NULL); 1899 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1900 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1901 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 1902 BUS_DMASYNC_PREREAD); 1903 1904 if (err != 0 || cb_arg.error) { 1905 /* 1906 * !zone_pack ? 1907 */ 1908 if (fl->ifl_zone == zone_pack) 1909 uma_zfree(fl->ifl_zone, cl); 1910 m_free(m); 1911 n = 0; 1912 goto done; 1913 } 1914 bus_addr = cb_arg.seg.ds_addr; 1915 } 1916 bit_set(fl->ifl_rx_bitmap, frag_idx); 1917 sd_flags[frag_idx] |= RX_SW_DESC_INUSE; 1918 1919 MPASS(sd_m[frag_idx] == NULL); 1920 sd_cl[frag_idx] = cl; 1921 sd_m[frag_idx] = m; 1922 fl->ifl_rxd_idxs[i] = frag_idx; 1923 fl->ifl_bus_addrs[i] = bus_addr; 1924 fl->ifl_vm_addrs[i] = cl; 1925 credits++; 1926 i++; 1927 MPASS(credits <= fl->ifl_size); 1928 if (++idx == fl->ifl_size) { 1929 fl->ifl_gen = 1; 1930 idx = 0; 1931 } 1932 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 1933 iru.iru_pidx = pidx; 1934 iru.iru_count = i; 1935 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1936 i = 0; 1937 pidx = idx; 1938 fl->ifl_pidx = idx; 1939 fl->ifl_credits = credits; 1940 } 1941 1942 } 1943 done: 1944 if (i) { 1945 iru.iru_pidx = pidx; 1946 iru.iru_count = i; 1947 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1948 fl->ifl_pidx = idx; 1949 fl->ifl_credits = credits; 1950 } 1951 DBG_COUNTER_INC(rxd_flush); 1952 if (fl->ifl_pidx == 0) 1953 pidx = fl->ifl_size - 1; 1954 else 1955 pidx = fl->ifl_pidx - 1; 1956 1957 if (sd_map) 1958 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1959 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1960 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 1961 fl->ifl_fragidx = frag_idx; 1962 } 1963 1964 static __inline void 1965 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 1966 { 1967 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 1968 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 1969 #ifdef INVARIANTS 1970 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 1971 #endif 1972 1973 MPASS(fl->ifl_credits <= fl->ifl_size); 1974 MPASS(reclaimable == delta); 1975 1976 if (reclaimable > 0) 1977 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 1978 } 1979 1980 static void 1981 iflib_fl_bufs_free(iflib_fl_t fl) 1982 { 1983 iflib_dma_info_t idi = fl->ifl_ifdi; 1984 uint32_t i; 1985 1986 for (i = 0; i < fl->ifl_size; i++) { 1987 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 1988 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 1989 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 1990 1991 if (*sd_flags & RX_SW_DESC_INUSE) { 1992 if (fl->ifl_sds.ifsd_map != NULL) { 1993 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 1994 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 1995 if (fl->ifl_rxq->ifr_ctx->ifc_in_detach) 1996 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 1997 } 1998 if (*sd_m != NULL) { 1999 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2000 uma_zfree(zone_mbuf, *sd_m); 2001 } 2002 if (*sd_cl != NULL) 2003 uma_zfree(fl->ifl_zone, *sd_cl); 2004 *sd_flags = 0; 2005 } else { 2006 MPASS(*sd_cl == NULL); 2007 MPASS(*sd_m == NULL); 2008 } 2009 #if MEMORY_LOGGING 2010 fl->ifl_m_dequeued++; 2011 fl->ifl_cl_dequeued++; 2012 #endif 2013 *sd_cl = NULL; 2014 *sd_m = NULL; 2015 } 2016 #ifdef INVARIANTS 2017 for (i = 0; i < fl->ifl_size; i++) { 2018 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 2019 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2020 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2021 } 2022 #endif 2023 /* 2024 * Reset free list values 2025 */ 2026 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2027 bzero(idi->idi_vaddr, idi->idi_size); 2028 } 2029 2030 /********************************************************************* 2031 * 2032 * Initialize a receive ring and its buffers. 2033 * 2034 **********************************************************************/ 2035 static int 2036 iflib_fl_setup(iflib_fl_t fl) 2037 { 2038 iflib_rxq_t rxq = fl->ifl_rxq; 2039 if_ctx_t ctx = rxq->ifr_ctx; 2040 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2041 2042 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2043 /* 2044 ** Free current RX buffer structs and their mbufs 2045 */ 2046 iflib_fl_bufs_free(fl); 2047 /* Now replenish the mbufs */ 2048 MPASS(fl->ifl_credits == 0); 2049 /* 2050 * XXX don't set the max_frame_size to larger 2051 * than the hardware can handle 2052 */ 2053 if (sctx->isc_max_frame_size <= 2048) 2054 fl->ifl_buf_size = MCLBYTES; 2055 #ifndef CONTIGMALLOC_WORKS 2056 else 2057 fl->ifl_buf_size = MJUMPAGESIZE; 2058 #else 2059 else if (sctx->isc_max_frame_size <= 4096) 2060 fl->ifl_buf_size = MJUMPAGESIZE; 2061 else if (sctx->isc_max_frame_size <= 9216) 2062 fl->ifl_buf_size = MJUM9BYTES; 2063 else 2064 fl->ifl_buf_size = MJUM16BYTES; 2065 #endif 2066 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2067 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2068 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2069 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2070 2071 2072 /* avoid pre-allocating zillions of clusters to an idle card 2073 * potentially speeding up attach 2074 */ 2075 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2076 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2077 if (min(128, fl->ifl_size) != fl->ifl_credits) 2078 return (ENOBUFS); 2079 /* 2080 * handle failure 2081 */ 2082 MPASS(rxq != NULL); 2083 MPASS(fl->ifl_ifdi != NULL); 2084 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2085 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2086 return (0); 2087 } 2088 2089 /********************************************************************* 2090 * 2091 * Free receive ring data structures 2092 * 2093 **********************************************************************/ 2094 static void 2095 iflib_rx_sds_free(iflib_rxq_t rxq) 2096 { 2097 iflib_fl_t fl; 2098 int i; 2099 2100 if (rxq->ifr_fl != NULL) { 2101 for (i = 0; i < rxq->ifr_nfl; i++) { 2102 fl = &rxq->ifr_fl[i]; 2103 if (fl->ifl_desc_tag != NULL) { 2104 bus_dma_tag_destroy(fl->ifl_desc_tag); 2105 fl->ifl_desc_tag = NULL; 2106 } 2107 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2108 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2109 /* XXX destroy maps first */ 2110 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2111 fl->ifl_sds.ifsd_m = NULL; 2112 fl->ifl_sds.ifsd_cl = NULL; 2113 fl->ifl_sds.ifsd_map = NULL; 2114 } 2115 free(rxq->ifr_fl, M_IFLIB); 2116 rxq->ifr_fl = NULL; 2117 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2118 } 2119 } 2120 2121 /* 2122 * MI independent logic 2123 * 2124 */ 2125 static void 2126 iflib_timer(void *arg) 2127 { 2128 iflib_txq_t txq = arg; 2129 if_ctx_t ctx = txq->ift_ctx; 2130 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2131 2132 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2133 return; 2134 /* 2135 ** Check on the state of the TX queue(s), this 2136 ** can be done without the lock because its RO 2137 ** and the HUNG state will be static if set. 2138 */ 2139 IFDI_TIMER(ctx, txq->ift_id); 2140 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2141 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2142 (sctx->isc_pause_frames == 0))) 2143 goto hung; 2144 2145 if (ifmp_ring_is_stalled(txq->ift_br)) 2146 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2147 txq->ift_cleaned_prev = txq->ift_cleaned; 2148 /* handle any laggards */ 2149 if (txq->ift_db_pending) 2150 GROUPTASK_ENQUEUE(&txq->ift_task); 2151 2152 sctx->isc_pause_frames = 0; 2153 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2154 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 2155 return; 2156 hung: 2157 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2158 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2159 STATE_LOCK(ctx); 2160 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2161 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2162 iflib_admin_intr_deferred(ctx); 2163 STATE_UNLOCK(ctx); 2164 } 2165 2166 static void 2167 iflib_init_locked(if_ctx_t ctx) 2168 { 2169 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2170 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2171 if_t ifp = ctx->ifc_ifp; 2172 iflib_fl_t fl; 2173 iflib_txq_t txq; 2174 iflib_rxq_t rxq; 2175 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2176 2177 2178 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2179 IFDI_INTR_DISABLE(ctx); 2180 2181 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2182 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2183 /* Set hardware offload abilities */ 2184 if_clearhwassist(ifp); 2185 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2186 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2187 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2188 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2189 if (if_getcapenable(ifp) & IFCAP_TSO4) 2190 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2191 if (if_getcapenable(ifp) & IFCAP_TSO6) 2192 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2193 2194 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2195 CALLOUT_LOCK(txq); 2196 callout_stop(&txq->ift_timer); 2197 CALLOUT_UNLOCK(txq); 2198 iflib_netmap_txq_init(ctx, txq); 2199 } 2200 #ifdef INVARIANTS 2201 i = if_getdrvflags(ifp); 2202 #endif 2203 IFDI_INIT(ctx); 2204 MPASS(if_getdrvflags(ifp) == i); 2205 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2206 /* XXX this should really be done on a per-queue basis */ 2207 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2208 MPASS(rxq->ifr_id == i); 2209 iflib_netmap_rxq_init(ctx, rxq); 2210 continue; 2211 } 2212 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2213 if (iflib_fl_setup(fl)) { 2214 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2215 goto done; 2216 } 2217 } 2218 } 2219 done: 2220 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2221 IFDI_INTR_ENABLE(ctx); 2222 txq = ctx->ifc_txqs; 2223 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2224 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2225 txq->ift_timer.c_cpu); 2226 } 2227 2228 static int 2229 iflib_media_change(if_t ifp) 2230 { 2231 if_ctx_t ctx = if_getsoftc(ifp); 2232 int err; 2233 2234 CTX_LOCK(ctx); 2235 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2236 iflib_init_locked(ctx); 2237 CTX_UNLOCK(ctx); 2238 return (err); 2239 } 2240 2241 static void 2242 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2243 { 2244 if_ctx_t ctx = if_getsoftc(ifp); 2245 2246 CTX_LOCK(ctx); 2247 IFDI_UPDATE_ADMIN_STATUS(ctx); 2248 IFDI_MEDIA_STATUS(ctx, ifmr); 2249 CTX_UNLOCK(ctx); 2250 } 2251 2252 static void 2253 iflib_stop(if_ctx_t ctx) 2254 { 2255 iflib_txq_t txq = ctx->ifc_txqs; 2256 iflib_rxq_t rxq = ctx->ifc_rxqs; 2257 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2258 iflib_dma_info_t di; 2259 iflib_fl_t fl; 2260 int i, j; 2261 2262 /* Tell the stack that the interface is no longer active */ 2263 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2264 2265 IFDI_INTR_DISABLE(ctx); 2266 DELAY(1000); 2267 IFDI_STOP(ctx); 2268 DELAY(1000); 2269 2270 iflib_debug_reset(); 2271 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2272 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2273 /* make sure all transmitters have completed before proceeding XXX */ 2274 2275 CALLOUT_LOCK(txq); 2276 callout_stop(&txq->ift_timer); 2277 CALLOUT_UNLOCK(txq); 2278 2279 /* clean any enqueued buffers */ 2280 iflib_ifmp_purge(txq); 2281 /* Free any existing tx buffers. */ 2282 for (j = 0; j < txq->ift_size; j++) { 2283 iflib_txsd_free(ctx, txq, j); 2284 } 2285 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2286 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2287 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2288 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2289 txq->ift_pullups = 0; 2290 ifmp_ring_reset_stats(txq->ift_br); 2291 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2292 bzero((void *)di->idi_vaddr, di->idi_size); 2293 } 2294 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2295 /* make sure all transmitters have completed before proceeding XXX */ 2296 2297 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++) 2298 bzero((void *)di->idi_vaddr, di->idi_size); 2299 /* also resets the free lists pidx/cidx */ 2300 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2301 iflib_fl_bufs_free(fl); 2302 } 2303 } 2304 2305 static inline caddr_t 2306 calc_next_rxd(iflib_fl_t fl, int cidx) 2307 { 2308 qidx_t size; 2309 int nrxd; 2310 caddr_t start, end, cur, next; 2311 2312 nrxd = fl->ifl_size; 2313 size = fl->ifl_rxd_size; 2314 start = fl->ifl_ifdi->idi_vaddr; 2315 2316 if (__predict_false(size == 0)) 2317 return (start); 2318 cur = start + size*cidx; 2319 end = start + size*nrxd; 2320 next = CACHE_PTR_NEXT(cur); 2321 return (next < end ? next : start); 2322 } 2323 2324 static inline void 2325 prefetch_pkts(iflib_fl_t fl, int cidx) 2326 { 2327 int nextptr; 2328 int nrxd = fl->ifl_size; 2329 caddr_t next_rxd; 2330 2331 2332 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2333 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2334 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2335 next_rxd = calc_next_rxd(fl, cidx); 2336 prefetch(next_rxd); 2337 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2338 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2339 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2340 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2341 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2342 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2343 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2344 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2345 } 2346 2347 static void 2348 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2349 { 2350 int flid, cidx; 2351 bus_dmamap_t map; 2352 iflib_fl_t fl; 2353 iflib_dma_info_t di; 2354 int next; 2355 2356 map = NULL; 2357 flid = irf->irf_flid; 2358 cidx = irf->irf_idx; 2359 fl = &rxq->ifr_fl[flid]; 2360 sd->ifsd_fl = fl; 2361 sd->ifsd_cidx = cidx; 2362 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2363 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2364 fl->ifl_credits--; 2365 #if MEMORY_LOGGING 2366 fl->ifl_m_dequeued++; 2367 #endif 2368 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2369 prefetch_pkts(fl, cidx); 2370 if (fl->ifl_sds.ifsd_map != NULL) { 2371 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2372 prefetch(&fl->ifl_sds.ifsd_map[next]); 2373 map = fl->ifl_sds.ifsd_map[cidx]; 2374 di = fl->ifl_ifdi; 2375 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2376 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2377 bus_dmamap_sync(di->idi_tag, di->idi_map, 2378 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2379 2380 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2381 MPASS(fl->ifl_cidx == cidx); 2382 if (unload) 2383 bus_dmamap_unload(fl->ifl_desc_tag, map); 2384 } 2385 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2386 if (__predict_false(fl->ifl_cidx == 0)) 2387 fl->ifl_gen = 0; 2388 if (map != NULL) 2389 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2390 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2391 bit_clear(fl->ifl_rx_bitmap, cidx); 2392 } 2393 2394 static struct mbuf * 2395 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2396 { 2397 int i, padlen , flags; 2398 struct mbuf *m, *mh, *mt; 2399 caddr_t cl; 2400 2401 i = 0; 2402 mh = NULL; 2403 do { 2404 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2405 2406 MPASS(*sd->ifsd_cl != NULL); 2407 MPASS(*sd->ifsd_m != NULL); 2408 2409 /* Don't include zero-length frags */ 2410 if (ri->iri_frags[i].irf_len == 0) { 2411 /* XXX we can save the cluster here, but not the mbuf */ 2412 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2413 m_free(*sd->ifsd_m); 2414 *sd->ifsd_m = NULL; 2415 continue; 2416 } 2417 m = *sd->ifsd_m; 2418 *sd->ifsd_m = NULL; 2419 if (mh == NULL) { 2420 flags = M_PKTHDR|M_EXT; 2421 mh = mt = m; 2422 padlen = ri->iri_pad; 2423 } else { 2424 flags = M_EXT; 2425 mt->m_next = m; 2426 mt = m; 2427 /* assuming padding is only on the first fragment */ 2428 padlen = 0; 2429 } 2430 cl = *sd->ifsd_cl; 2431 *sd->ifsd_cl = NULL; 2432 2433 /* Can these two be made one ? */ 2434 m_init(m, M_NOWAIT, MT_DATA, flags); 2435 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2436 /* 2437 * These must follow m_init and m_cljset 2438 */ 2439 m->m_data += padlen; 2440 ri->iri_len -= padlen; 2441 m->m_len = ri->iri_frags[i].irf_len; 2442 } while (++i < ri->iri_nfrags); 2443 2444 return (mh); 2445 } 2446 2447 /* 2448 * Process one software descriptor 2449 */ 2450 static struct mbuf * 2451 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2452 { 2453 struct if_rxsd sd; 2454 struct mbuf *m; 2455 2456 /* should I merge this back in now that the two paths are basically duplicated? */ 2457 if (ri->iri_nfrags == 1 && 2458 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2459 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2460 m = *sd.ifsd_m; 2461 *sd.ifsd_m = NULL; 2462 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2463 #ifndef __NO_STRICT_ALIGNMENT 2464 if (!IP_ALIGNED(m)) 2465 m->m_data += 2; 2466 #endif 2467 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2468 m->m_len = ri->iri_frags[0].irf_len; 2469 } else { 2470 m = assemble_segments(rxq, ri, &sd); 2471 } 2472 m->m_pkthdr.len = ri->iri_len; 2473 m->m_pkthdr.rcvif = ri->iri_ifp; 2474 m->m_flags |= ri->iri_flags; 2475 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2476 m->m_pkthdr.flowid = ri->iri_flowid; 2477 M_HASHTYPE_SET(m, ri->iri_rsstype); 2478 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2479 m->m_pkthdr.csum_data = ri->iri_csum_data; 2480 return (m); 2481 } 2482 2483 #if defined(INET6) || defined(INET) 2484 static void 2485 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2486 { 2487 CURVNET_SET(lc->ifp->if_vnet); 2488 #if defined(INET6) 2489 *v6 = VNET(ip6_forwarding); 2490 #endif 2491 #if defined(INET) 2492 *v4 = VNET(ipforwarding); 2493 #endif 2494 CURVNET_RESTORE(); 2495 } 2496 2497 /* 2498 * Returns true if it's possible this packet could be LROed. 2499 * if it returns false, it is guaranteed that tcp_lro_rx() 2500 * would not return zero. 2501 */ 2502 static bool 2503 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2504 { 2505 struct ether_header *eh; 2506 uint16_t eh_type; 2507 2508 eh = mtod(m, struct ether_header *); 2509 eh_type = ntohs(eh->ether_type); 2510 switch (eh_type) { 2511 #if defined(INET6) 2512 case ETHERTYPE_IPV6: 2513 return !v6_forwarding; 2514 #endif 2515 #if defined (INET) 2516 case ETHERTYPE_IP: 2517 return !v4_forwarding; 2518 #endif 2519 } 2520 2521 return false; 2522 } 2523 #else 2524 static void 2525 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2526 { 2527 } 2528 #endif 2529 2530 static bool 2531 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2532 { 2533 if_ctx_t ctx = rxq->ifr_ctx; 2534 if_shared_ctx_t sctx = ctx->ifc_sctx; 2535 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2536 int avail, i; 2537 qidx_t *cidxp; 2538 struct if_rxd_info ri; 2539 int err, budget_left, rx_bytes, rx_pkts; 2540 iflib_fl_t fl; 2541 struct ifnet *ifp; 2542 int lro_enabled; 2543 bool lro_possible = false; 2544 bool v4_forwarding, v6_forwarding; 2545 2546 /* 2547 * XXX early demux data packets so that if_input processing only handles 2548 * acks in interrupt context 2549 */ 2550 struct mbuf *m, *mh, *mt, *mf; 2551 2552 ifp = ctx->ifc_ifp; 2553 mh = mt = NULL; 2554 MPASS(budget > 0); 2555 rx_pkts = rx_bytes = 0; 2556 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2557 cidxp = &rxq->ifr_cq_cidx; 2558 else 2559 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2560 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2561 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2562 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2563 DBG_COUNTER_INC(rx_unavail); 2564 return (false); 2565 } 2566 2567 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2568 if (__predict_false(!CTX_ACTIVE(ctx))) { 2569 DBG_COUNTER_INC(rx_ctx_inactive); 2570 break; 2571 } 2572 /* 2573 * Reset client set fields to their default values 2574 */ 2575 rxd_info_zero(&ri); 2576 ri.iri_qsidx = rxq->ifr_id; 2577 ri.iri_cidx = *cidxp; 2578 ri.iri_ifp = ifp; 2579 ri.iri_frags = rxq->ifr_frags; 2580 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2581 2582 if (err) 2583 goto err; 2584 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2585 *cidxp = ri.iri_cidx; 2586 /* Update our consumer index */ 2587 /* XXX NB: shurd - check if this is still safe */ 2588 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2589 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2590 rxq->ifr_cq_gen = 0; 2591 } 2592 /* was this only a completion queue message? */ 2593 if (__predict_false(ri.iri_nfrags == 0)) 2594 continue; 2595 } 2596 MPASS(ri.iri_nfrags != 0); 2597 MPASS(ri.iri_len != 0); 2598 2599 /* will advance the cidx on the corresponding free lists */ 2600 m = iflib_rxd_pkt_get(rxq, &ri); 2601 if (avail == 0 && budget_left) 2602 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2603 2604 if (__predict_false(m == NULL)) { 2605 DBG_COUNTER_INC(rx_mbuf_null); 2606 continue; 2607 } 2608 /* imm_pkt: -- cxgb */ 2609 if (mh == NULL) 2610 mh = mt = m; 2611 else { 2612 mt->m_nextpkt = m; 2613 mt = m; 2614 } 2615 } 2616 /* make sure that we can refill faster than drain */ 2617 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2618 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2619 2620 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2621 if (lro_enabled) 2622 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2623 mt = mf = NULL; 2624 while (mh != NULL) { 2625 m = mh; 2626 mh = mh->m_nextpkt; 2627 m->m_nextpkt = NULL; 2628 #ifndef __NO_STRICT_ALIGNMENT 2629 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2630 continue; 2631 #endif 2632 rx_bytes += m->m_pkthdr.len; 2633 rx_pkts++; 2634 #if defined(INET6) || defined(INET) 2635 if (lro_enabled) { 2636 if (!lro_possible) { 2637 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2638 if (lro_possible && mf != NULL) { 2639 ifp->if_input(ifp, mf); 2640 DBG_COUNTER_INC(rx_if_input); 2641 mt = mf = NULL; 2642 } 2643 } 2644 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2645 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2646 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2647 continue; 2648 } 2649 } 2650 #endif 2651 if (lro_possible) { 2652 ifp->if_input(ifp, m); 2653 DBG_COUNTER_INC(rx_if_input); 2654 continue; 2655 } 2656 2657 if (mf == NULL) 2658 mf = m; 2659 if (mt != NULL) 2660 mt->m_nextpkt = m; 2661 mt = m; 2662 } 2663 if (mf != NULL) { 2664 ifp->if_input(ifp, mf); 2665 DBG_COUNTER_INC(rx_if_input); 2666 } 2667 2668 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2669 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2670 2671 /* 2672 * Flush any outstanding LRO work 2673 */ 2674 #if defined(INET6) || defined(INET) 2675 tcp_lro_flush_all(&rxq->ifr_lc); 2676 #endif 2677 if (avail) 2678 return true; 2679 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2680 err: 2681 STATE_LOCK(ctx); 2682 ctx->ifc_flags |= IFC_DO_RESET; 2683 iflib_admin_intr_deferred(ctx); 2684 STATE_UNLOCK(ctx); 2685 return (false); 2686 } 2687 2688 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2689 static inline qidx_t 2690 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2691 { 2692 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2693 qidx_t minthresh = txq->ift_size / 8; 2694 if (in_use > 4*minthresh) 2695 return (notify_count); 2696 if (in_use > 2*minthresh) 2697 return (notify_count >> 1); 2698 if (in_use > minthresh) 2699 return (notify_count >> 3); 2700 return (0); 2701 } 2702 2703 static inline qidx_t 2704 txq_max_rs_deferred(iflib_txq_t txq) 2705 { 2706 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2707 qidx_t minthresh = txq->ift_size / 8; 2708 if (txq->ift_in_use > 4*minthresh) 2709 return (notify_count); 2710 if (txq->ift_in_use > 2*minthresh) 2711 return (notify_count >> 1); 2712 if (txq->ift_in_use > minthresh) 2713 return (notify_count >> 2); 2714 return (2); 2715 } 2716 2717 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2718 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2719 2720 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2721 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2722 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2723 2724 /* forward compatibility for cxgb */ 2725 #define FIRST_QSET(ctx) 0 2726 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2727 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2728 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2729 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2730 2731 /* XXX we should be setting this to something other than zero */ 2732 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2733 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2734 2735 static inline bool 2736 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2737 { 2738 qidx_t dbval, max; 2739 bool rang; 2740 2741 rang = false; 2742 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2743 if (ring || txq->ift_db_pending >= max) { 2744 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2745 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2746 txq->ift_db_pending = txq->ift_npending = 0; 2747 rang = true; 2748 } 2749 return (rang); 2750 } 2751 2752 #ifdef PKT_DEBUG 2753 static void 2754 print_pkt(if_pkt_info_t pi) 2755 { 2756 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2757 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2758 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2759 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2760 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2761 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2762 } 2763 #endif 2764 2765 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2766 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2767 2768 static int 2769 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2770 { 2771 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2772 struct ether_vlan_header *eh; 2773 struct mbuf *m, *n; 2774 2775 n = m = *mp; 2776 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2777 M_WRITABLE(m) == 0) { 2778 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2779 return (ENOMEM); 2780 } else { 2781 m_freem(*mp); 2782 n = *mp = m; 2783 } 2784 } 2785 2786 /* 2787 * Determine where frame payload starts. 2788 * Jump over vlan headers if already present, 2789 * helpful for QinQ too. 2790 */ 2791 if (__predict_false(m->m_len < sizeof(*eh))) { 2792 txq->ift_pullups++; 2793 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2794 return (ENOMEM); 2795 } 2796 eh = mtod(m, struct ether_vlan_header *); 2797 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2798 pi->ipi_etype = ntohs(eh->evl_proto); 2799 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2800 } else { 2801 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2802 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2803 } 2804 2805 switch (pi->ipi_etype) { 2806 #ifdef INET 2807 case ETHERTYPE_IP: 2808 { 2809 struct ip *ip = NULL; 2810 struct tcphdr *th = NULL; 2811 int minthlen; 2812 2813 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2814 if (__predict_false(m->m_len < minthlen)) { 2815 /* 2816 * if this code bloat is causing too much of a hit 2817 * move it to a separate function and mark it noinline 2818 */ 2819 if (m->m_len == pi->ipi_ehdrlen) { 2820 n = m->m_next; 2821 MPASS(n); 2822 if (n->m_len >= sizeof(*ip)) { 2823 ip = (struct ip *)n->m_data; 2824 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2825 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2826 } else { 2827 txq->ift_pullups++; 2828 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2829 return (ENOMEM); 2830 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2831 } 2832 } else { 2833 txq->ift_pullups++; 2834 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2835 return (ENOMEM); 2836 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2837 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2838 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2839 } 2840 } else { 2841 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2842 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2843 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2844 } 2845 pi->ipi_ip_hlen = ip->ip_hl << 2; 2846 pi->ipi_ipproto = ip->ip_p; 2847 pi->ipi_flags |= IPI_TX_IPV4; 2848 2849 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 2850 ip->ip_sum = 0; 2851 2852 if (IS_TSO4(pi)) { 2853 if (pi->ipi_ipproto == IPPROTO_TCP) { 2854 if (__predict_false(th == NULL)) { 2855 txq->ift_pullups++; 2856 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2857 return (ENOMEM); 2858 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2859 } 2860 pi->ipi_tcp_hflags = th->th_flags; 2861 pi->ipi_tcp_hlen = th->th_off << 2; 2862 pi->ipi_tcp_seq = th->th_seq; 2863 } 2864 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2865 return (ENXIO); 2866 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2867 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2868 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2869 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2870 ip->ip_sum = 0; 2871 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2872 } 2873 } 2874 break; 2875 } 2876 #endif 2877 #ifdef INET6 2878 case ETHERTYPE_IPV6: 2879 { 2880 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2881 struct tcphdr *th; 2882 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2883 2884 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2885 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2886 return (ENOMEM); 2887 } 2888 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2889 2890 /* XXX-BZ this will go badly in case of ext hdrs. */ 2891 pi->ipi_ipproto = ip6->ip6_nxt; 2892 pi->ipi_flags |= IPI_TX_IPV6; 2893 2894 if (IS_TSO6(pi)) { 2895 if (pi->ipi_ipproto == IPPROTO_TCP) { 2896 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2897 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2898 return (ENOMEM); 2899 } 2900 pi->ipi_tcp_hflags = th->th_flags; 2901 pi->ipi_tcp_hlen = th->th_off << 2; 2902 } 2903 2904 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2905 return (ENXIO); 2906 /* 2907 * The corresponding flag is set by the stack in the IPv4 2908 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 2909 * So, set it here because the rest of the flow requires it. 2910 */ 2911 pi->ipi_csum_flags |= CSUM_TCP_IPV6; 2912 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2913 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2914 } 2915 break; 2916 } 2917 #endif 2918 default: 2919 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2920 pi->ipi_ip_hlen = 0; 2921 break; 2922 } 2923 *mp = m; 2924 2925 return (0); 2926 } 2927 2928 static __noinline struct mbuf * 2929 collapse_pkthdr(struct mbuf *m0) 2930 { 2931 struct mbuf *m, *m_next, *tmp; 2932 2933 m = m0; 2934 m_next = m->m_next; 2935 while (m_next != NULL && m_next->m_len == 0) { 2936 m = m_next; 2937 m->m_next = NULL; 2938 m_free(m); 2939 m_next = m_next->m_next; 2940 } 2941 m = m0; 2942 m->m_next = m_next; 2943 if ((m_next->m_flags & M_EXT) == 0) { 2944 m = m_defrag(m, M_NOWAIT); 2945 } else { 2946 tmp = m_next->m_next; 2947 memcpy(m_next, m, MPKTHSIZE); 2948 m = m_next; 2949 m->m_next = tmp; 2950 } 2951 return (m); 2952 } 2953 2954 /* 2955 * If dodgy hardware rejects the scatter gather chain we've handed it 2956 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 2957 * m_defrag'd mbufs 2958 */ 2959 static __noinline struct mbuf * 2960 iflib_remove_mbuf(iflib_txq_t txq) 2961 { 2962 int ntxd, i, pidx; 2963 struct mbuf *m, *mh, **ifsd_m; 2964 2965 pidx = txq->ift_pidx; 2966 ifsd_m = txq->ift_sds.ifsd_m; 2967 ntxd = txq->ift_size; 2968 mh = m = ifsd_m[pidx]; 2969 ifsd_m[pidx] = NULL; 2970 #if MEMORY_LOGGING 2971 txq->ift_dequeued++; 2972 #endif 2973 i = 1; 2974 2975 while (m) { 2976 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 2977 #if MEMORY_LOGGING 2978 txq->ift_dequeued++; 2979 #endif 2980 m = m->m_next; 2981 i++; 2982 } 2983 return (mh); 2984 } 2985 2986 static int 2987 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 2988 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 2989 int max_segs, int flags) 2990 { 2991 if_ctx_t ctx; 2992 if_shared_ctx_t sctx; 2993 if_softc_ctx_t scctx; 2994 int i, next, pidx, err, ntxd, count; 2995 struct mbuf *m, *tmp, **ifsd_m; 2996 2997 m = *m0; 2998 2999 /* 3000 * Please don't ever do this 3001 */ 3002 if (__predict_false(m->m_len == 0)) 3003 *m0 = m = collapse_pkthdr(m); 3004 3005 ctx = txq->ift_ctx; 3006 sctx = ctx->ifc_sctx; 3007 scctx = &ctx->ifc_softc_ctx; 3008 ifsd_m = txq->ift_sds.ifsd_m; 3009 ntxd = txq->ift_size; 3010 pidx = txq->ift_pidx; 3011 if (map != NULL) { 3012 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 3013 3014 err = bus_dmamap_load_mbuf_sg(tag, map, 3015 *m0, segs, nsegs, BUS_DMA_NOWAIT); 3016 if (err) 3017 return (err); 3018 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 3019 count = 0; 3020 m = *m0; 3021 do { 3022 if (__predict_false(m->m_len <= 0)) { 3023 tmp = m; 3024 m = m->m_next; 3025 tmp->m_next = NULL; 3026 m_free(tmp); 3027 continue; 3028 } 3029 m = m->m_next; 3030 count++; 3031 } while (m != NULL); 3032 if (count > *nsegs) { 3033 ifsd_m[pidx] = *m0; 3034 ifsd_m[pidx]->m_flags |= M_TOOBIG; 3035 return (0); 3036 } 3037 m = *m0; 3038 count = 0; 3039 do { 3040 next = (pidx + count) & (ntxd-1); 3041 MPASS(ifsd_m[next] == NULL); 3042 ifsd_m[next] = m; 3043 count++; 3044 tmp = m; 3045 m = m->m_next; 3046 } while (m != NULL); 3047 } else { 3048 int buflen, sgsize, maxsegsz, max_sgsize; 3049 vm_offset_t vaddr; 3050 vm_paddr_t curaddr; 3051 3052 count = i = 0; 3053 m = *m0; 3054 if (m->m_pkthdr.csum_flags & CSUM_TSO) 3055 maxsegsz = scctx->isc_tx_tso_segsize_max; 3056 else 3057 maxsegsz = sctx->isc_tx_maxsegsize; 3058 3059 do { 3060 if (__predict_false(m->m_len <= 0)) { 3061 tmp = m; 3062 m = m->m_next; 3063 tmp->m_next = NULL; 3064 m_free(tmp); 3065 continue; 3066 } 3067 buflen = m->m_len; 3068 vaddr = (vm_offset_t)m->m_data; 3069 /* 3070 * see if we can't be smarter about physically 3071 * contiguous mappings 3072 */ 3073 next = (pidx + count) & (ntxd-1); 3074 MPASS(ifsd_m[next] == NULL); 3075 #if MEMORY_LOGGING 3076 txq->ift_enqueued++; 3077 #endif 3078 ifsd_m[next] = m; 3079 while (buflen > 0) { 3080 if (i >= max_segs) 3081 goto err; 3082 max_sgsize = MIN(buflen, maxsegsz); 3083 curaddr = pmap_kextract(vaddr); 3084 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 3085 sgsize = MIN(sgsize, max_sgsize); 3086 segs[i].ds_addr = curaddr; 3087 segs[i].ds_len = sgsize; 3088 vaddr += sgsize; 3089 buflen -= sgsize; 3090 i++; 3091 } 3092 count++; 3093 tmp = m; 3094 m = m->m_next; 3095 } while (m != NULL); 3096 *nsegs = i; 3097 } 3098 return (0); 3099 err: 3100 *m0 = iflib_remove_mbuf(txq); 3101 return (EFBIG); 3102 } 3103 3104 static inline caddr_t 3105 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3106 { 3107 qidx_t size; 3108 int ntxd; 3109 caddr_t start, end, cur, next; 3110 3111 ntxd = txq->ift_size; 3112 size = txq->ift_txd_size[qid]; 3113 start = txq->ift_ifdi[qid].idi_vaddr; 3114 3115 if (__predict_false(size == 0)) 3116 return (start); 3117 cur = start + size*cidx; 3118 end = start + size*ntxd; 3119 next = CACHE_PTR_NEXT(cur); 3120 return (next < end ? next : start); 3121 } 3122 3123 /* 3124 * Pad an mbuf to ensure a minimum ethernet frame size. 3125 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3126 */ 3127 static __noinline int 3128 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3129 { 3130 /* 3131 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3132 * and ARP message is the smallest common payload I can think of 3133 */ 3134 static char pad[18]; /* just zeros */ 3135 int n; 3136 struct mbuf *new_head; 3137 3138 if (!M_WRITABLE(*m_head)) { 3139 new_head = m_dup(*m_head, M_NOWAIT); 3140 if (new_head == NULL) { 3141 m_freem(*m_head); 3142 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3143 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3144 return ENOMEM; 3145 } 3146 m_freem(*m_head); 3147 *m_head = new_head; 3148 } 3149 3150 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3151 n > 0; n -= sizeof(pad)) 3152 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3153 break; 3154 3155 if (n > 0) { 3156 m_freem(*m_head); 3157 device_printf(dev, "cannot pad short frame\n"); 3158 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3159 return (ENOBUFS); 3160 } 3161 3162 return 0; 3163 } 3164 3165 static int 3166 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3167 { 3168 if_ctx_t ctx; 3169 if_shared_ctx_t sctx; 3170 if_softc_ctx_t scctx; 3171 bus_dma_segment_t *segs; 3172 struct mbuf *m_head; 3173 void *next_txd; 3174 bus_dmamap_t map; 3175 struct if_pkt_info pi; 3176 int remap = 0; 3177 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3178 bus_dma_tag_t desc_tag; 3179 3180 segs = txq->ift_segs; 3181 ctx = txq->ift_ctx; 3182 sctx = ctx->ifc_sctx; 3183 scctx = &ctx->ifc_softc_ctx; 3184 segs = txq->ift_segs; 3185 ntxd = txq->ift_size; 3186 m_head = *m_headp; 3187 map = NULL; 3188 3189 /* 3190 * If we're doing TSO the next descriptor to clean may be quite far ahead 3191 */ 3192 cidx = txq->ift_cidx; 3193 pidx = txq->ift_pidx; 3194 if (ctx->ifc_flags & IFC_PREFETCH) { 3195 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3196 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3197 next_txd = calc_next_txd(txq, cidx, 0); 3198 prefetch(next_txd); 3199 } 3200 3201 /* prefetch the next cache line of mbuf pointers and flags */ 3202 prefetch(&txq->ift_sds.ifsd_m[next]); 3203 if (txq->ift_sds.ifsd_map != NULL) { 3204 prefetch(&txq->ift_sds.ifsd_map[next]); 3205 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3206 prefetch(&txq->ift_sds.ifsd_flags[next]); 3207 } 3208 } else if (txq->ift_sds.ifsd_map != NULL) 3209 map = txq->ift_sds.ifsd_map[pidx]; 3210 3211 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3212 desc_tag = txq->ift_tso_desc_tag; 3213 max_segs = scctx->isc_tx_tso_segments_max; 3214 } else { 3215 desc_tag = txq->ift_desc_tag; 3216 max_segs = scctx->isc_tx_nsegments; 3217 } 3218 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3219 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3220 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3221 if (err) 3222 return err; 3223 } 3224 m_head = *m_headp; 3225 3226 pkt_info_zero(&pi); 3227 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3228 pi.ipi_pidx = pidx; 3229 pi.ipi_qsidx = txq->ift_id; 3230 pi.ipi_len = m_head->m_pkthdr.len; 3231 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3232 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3233 3234 /* deliberate bitwise OR to make one condition */ 3235 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3236 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3237 return (err); 3238 m_head = *m_headp; 3239 } 3240 3241 retry: 3242 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3243 defrag: 3244 if (__predict_false(err)) { 3245 switch (err) { 3246 case EFBIG: 3247 /* try collapse once and defrag once */ 3248 if (remap == 0) 3249 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3250 if (remap == 1) 3251 m_head = m_defrag(*m_headp, M_NOWAIT); 3252 remap++; 3253 if (__predict_false(m_head == NULL)) 3254 goto defrag_failed; 3255 txq->ift_mbuf_defrag++; 3256 *m_headp = m_head; 3257 goto retry; 3258 break; 3259 case ENOMEM: 3260 txq->ift_no_tx_dma_setup++; 3261 break; 3262 default: 3263 txq->ift_no_tx_dma_setup++; 3264 m_freem(*m_headp); 3265 DBG_COUNTER_INC(tx_frees); 3266 *m_headp = NULL; 3267 break; 3268 } 3269 txq->ift_map_failed++; 3270 DBG_COUNTER_INC(encap_load_mbuf_fail); 3271 return (err); 3272 } 3273 3274 /* 3275 * XXX assumes a 1 to 1 relationship between segments and 3276 * descriptors - this does not hold true on all drivers, e.g. 3277 * cxgb 3278 */ 3279 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3280 txq->ift_no_desc_avail++; 3281 if (map != NULL) 3282 bus_dmamap_unload(desc_tag, map); 3283 DBG_COUNTER_INC(encap_txq_avail_fail); 3284 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3285 GROUPTASK_ENQUEUE(&txq->ift_task); 3286 return (ENOBUFS); 3287 } 3288 /* 3289 * On Intel cards we can greatly reduce the number of TX interrupts 3290 * we see by only setting report status on every Nth descriptor. 3291 * However, this also means that the driver will need to keep track 3292 * of the descriptors that RS was set on to check them for the DD bit. 3293 */ 3294 txq->ift_rs_pending += nsegs + 1; 3295 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3296 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) { 3297 pi.ipi_flags |= IPI_TX_INTR; 3298 txq->ift_rs_pending = 0; 3299 } 3300 3301 pi.ipi_segs = segs; 3302 pi.ipi_nsegs = nsegs; 3303 3304 MPASS(pidx >= 0 && pidx < txq->ift_size); 3305 #ifdef PKT_DEBUG 3306 print_pkt(&pi); 3307 #endif 3308 if (map != NULL) 3309 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3310 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3311 if (map != NULL) 3312 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3313 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3314 DBG_COUNTER_INC(tx_encap); 3315 MPASS(pi.ipi_new_pidx < txq->ift_size); 3316 3317 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3318 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3319 ndesc += txq->ift_size; 3320 txq->ift_gen = 1; 3321 } 3322 /* 3323 * drivers can need as many as 3324 * two sentinels 3325 */ 3326 MPASS(ndesc <= pi.ipi_nsegs + 2); 3327 MPASS(pi.ipi_new_pidx != pidx); 3328 MPASS(ndesc > 0); 3329 txq->ift_in_use += ndesc; 3330 3331 /* 3332 * We update the last software descriptor again here because there may 3333 * be a sentinel and/or there may be more mbufs than segments 3334 */ 3335 txq->ift_pidx = pi.ipi_new_pidx; 3336 txq->ift_npending += pi.ipi_ndescs; 3337 } else if (__predict_false(err == EFBIG && remap < 2)) { 3338 *m_headp = m_head = iflib_remove_mbuf(txq); 3339 remap = 1; 3340 txq->ift_txd_encap_efbig++; 3341 goto defrag; 3342 } else 3343 DBG_COUNTER_INC(encap_txd_encap_fail); 3344 return (err); 3345 3346 defrag_failed: 3347 txq->ift_mbuf_defrag_failed++; 3348 txq->ift_map_failed++; 3349 m_freem(*m_headp); 3350 DBG_COUNTER_INC(tx_frees); 3351 *m_headp = NULL; 3352 return (ENOMEM); 3353 } 3354 3355 static void 3356 iflib_tx_desc_free(iflib_txq_t txq, int n) 3357 { 3358 int hasmap; 3359 uint32_t qsize, cidx, mask, gen; 3360 struct mbuf *m, **ifsd_m; 3361 uint8_t *ifsd_flags; 3362 bus_dmamap_t *ifsd_map; 3363 bool do_prefetch; 3364 3365 cidx = txq->ift_cidx; 3366 gen = txq->ift_gen; 3367 qsize = txq->ift_size; 3368 mask = qsize-1; 3369 hasmap = txq->ift_sds.ifsd_map != NULL; 3370 ifsd_flags = txq->ift_sds.ifsd_flags; 3371 ifsd_m = txq->ift_sds.ifsd_m; 3372 ifsd_map = txq->ift_sds.ifsd_map; 3373 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3374 3375 while (n--) { 3376 if (do_prefetch) { 3377 prefetch(ifsd_m[(cidx + 3) & mask]); 3378 prefetch(ifsd_m[(cidx + 4) & mask]); 3379 } 3380 if (ifsd_m[cidx] != NULL) { 3381 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3382 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3383 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3384 /* 3385 * does it matter if it's not the TSO tag? If so we'll 3386 * have to add the type to flags 3387 */ 3388 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3389 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3390 } 3391 if ((m = ifsd_m[cidx]) != NULL) { 3392 /* XXX we don't support any drivers that batch packets yet */ 3393 MPASS(m->m_nextpkt == NULL); 3394 /* if the number of clusters exceeds the number of segments 3395 * there won't be space on the ring to save a pointer to each 3396 * cluster so we simply free the list here 3397 */ 3398 if (m->m_flags & M_TOOBIG) { 3399 m_freem(m); 3400 } else { 3401 m_free(m); 3402 } 3403 ifsd_m[cidx] = NULL; 3404 #if MEMORY_LOGGING 3405 txq->ift_dequeued++; 3406 #endif 3407 DBG_COUNTER_INC(tx_frees); 3408 } 3409 } 3410 if (__predict_false(++cidx == qsize)) { 3411 cidx = 0; 3412 gen = 0; 3413 } 3414 } 3415 txq->ift_cidx = cidx; 3416 txq->ift_gen = gen; 3417 } 3418 3419 static __inline int 3420 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3421 { 3422 int reclaim; 3423 if_ctx_t ctx = txq->ift_ctx; 3424 3425 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3426 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3427 3428 /* 3429 * Need a rate-limiting check so that this isn't called every time 3430 */ 3431 iflib_tx_credits_update(ctx, txq); 3432 reclaim = DESC_RECLAIMABLE(txq); 3433 3434 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3435 #ifdef INVARIANTS 3436 if (iflib_verbose_debug) { 3437 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3438 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3439 reclaim, thresh); 3440 3441 } 3442 #endif 3443 return (0); 3444 } 3445 iflib_tx_desc_free(txq, reclaim); 3446 txq->ift_cleaned += reclaim; 3447 txq->ift_in_use -= reclaim; 3448 3449 return (reclaim); 3450 } 3451 3452 static struct mbuf ** 3453 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3454 { 3455 int next, size; 3456 struct mbuf **items; 3457 3458 size = r->size; 3459 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3460 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3461 3462 prefetch(items[(cidx + offset) & (size-1)]); 3463 if (remaining > 1) { 3464 prefetch2cachelines(&items[next]); 3465 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3466 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3467 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3468 } 3469 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3470 } 3471 3472 static void 3473 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3474 { 3475 3476 ifmp_ring_check_drainage(txq->ift_br, budget); 3477 } 3478 3479 static uint32_t 3480 iflib_txq_can_drain(struct ifmp_ring *r) 3481 { 3482 iflib_txq_t txq = r->cookie; 3483 if_ctx_t ctx = txq->ift_ctx; 3484 3485 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3486 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3487 } 3488 3489 static uint32_t 3490 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3491 { 3492 iflib_txq_t txq = r->cookie; 3493 if_ctx_t ctx = txq->ift_ctx; 3494 struct ifnet *ifp = ctx->ifc_ifp; 3495 struct mbuf **mp, *m; 3496 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3497 int reclaimed, err, in_use_prev, desc_used; 3498 bool do_prefetch, ring, rang; 3499 3500 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3501 !LINK_ACTIVE(ctx))) { 3502 DBG_COUNTER_INC(txq_drain_notready); 3503 return (0); 3504 } 3505 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3506 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3507 avail = IDXDIFF(pidx, cidx, r->size); 3508 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3509 DBG_COUNTER_INC(txq_drain_flushing); 3510 for (i = 0; i < avail; i++) { 3511 m_free(r->items[(cidx + i) & (r->size-1)]); 3512 r->items[(cidx + i) & (r->size-1)] = NULL; 3513 } 3514 return (avail); 3515 } 3516 3517 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3518 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3519 CALLOUT_LOCK(txq); 3520 callout_stop(&txq->ift_timer); 3521 CALLOUT_UNLOCK(txq); 3522 DBG_COUNTER_INC(txq_drain_oactive); 3523 return (0); 3524 } 3525 if (reclaimed) 3526 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3527 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3528 count = MIN(avail, TX_BATCH_SIZE); 3529 #ifdef INVARIANTS 3530 if (iflib_verbose_debug) 3531 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3532 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3533 #endif 3534 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3535 avail = TXQ_AVAIL(txq); 3536 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3537 int pidx_prev, rem = do_prefetch ? count - i : 0; 3538 3539 mp = _ring_peek_one(r, cidx, i, rem); 3540 MPASS(mp != NULL && *mp != NULL); 3541 if (__predict_false(*mp == (struct mbuf *)txq)) { 3542 consumed++; 3543 reclaimed++; 3544 continue; 3545 } 3546 in_use_prev = txq->ift_in_use; 3547 pidx_prev = txq->ift_pidx; 3548 err = iflib_encap(txq, mp); 3549 if (__predict_false(err)) { 3550 DBG_COUNTER_INC(txq_drain_encapfail); 3551 /* no room - bail out */ 3552 if (err == ENOBUFS) 3553 break; 3554 consumed++; 3555 DBG_COUNTER_INC(txq_drain_encapfail); 3556 /* we can't send this packet - skip it */ 3557 continue; 3558 } 3559 consumed++; 3560 pkt_sent++; 3561 m = *mp; 3562 DBG_COUNTER_INC(tx_sent); 3563 bytes_sent += m->m_pkthdr.len; 3564 mcast_sent += !!(m->m_flags & M_MCAST); 3565 avail = TXQ_AVAIL(txq); 3566 3567 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3568 desc_used += (txq->ift_in_use - in_use_prev); 3569 ETHER_BPF_MTAP(ifp, m); 3570 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3571 break; 3572 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3573 } 3574 3575 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3576 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3577 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3578 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3579 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3580 if (mcast_sent) 3581 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3582 #ifdef INVARIANTS 3583 if (iflib_verbose_debug) 3584 printf("consumed=%d\n", consumed); 3585 #endif 3586 return (consumed); 3587 } 3588 3589 static uint32_t 3590 iflib_txq_drain_always(struct ifmp_ring *r) 3591 { 3592 return (1); 3593 } 3594 3595 static uint32_t 3596 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3597 { 3598 int i, avail; 3599 struct mbuf **mp; 3600 iflib_txq_t txq; 3601 3602 txq = r->cookie; 3603 3604 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3605 CALLOUT_LOCK(txq); 3606 callout_stop(&txq->ift_timer); 3607 CALLOUT_UNLOCK(txq); 3608 3609 avail = IDXDIFF(pidx, cidx, r->size); 3610 for (i = 0; i < avail; i++) { 3611 mp = _ring_peek_one(r, cidx, i, avail - i); 3612 if (__predict_false(*mp == (struct mbuf *)txq)) 3613 continue; 3614 m_freem(*mp); 3615 } 3616 MPASS(ifmp_ring_is_stalled(r) == 0); 3617 return (avail); 3618 } 3619 3620 static void 3621 iflib_ifmp_purge(iflib_txq_t txq) 3622 { 3623 struct ifmp_ring *r; 3624 3625 r = txq->ift_br; 3626 r->drain = iflib_txq_drain_free; 3627 r->can_drain = iflib_txq_drain_always; 3628 3629 ifmp_ring_check_drainage(r, r->size); 3630 3631 r->drain = iflib_txq_drain; 3632 r->can_drain = iflib_txq_can_drain; 3633 } 3634 3635 static void 3636 _task_fn_tx(void *context) 3637 { 3638 iflib_txq_t txq = context; 3639 if_ctx_t ctx = txq->ift_ctx; 3640 struct ifnet *ifp = ctx->ifc_ifp; 3641 int rc; 3642 3643 #ifdef IFLIB_DIAGNOSTICS 3644 txq->ift_cpu_exec_count[curcpu]++; 3645 #endif 3646 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3647 return; 3648 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3649 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3650 netmap_tx_irq(ifp, txq->ift_id); 3651 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3652 return; 3653 } 3654 if (txq->ift_db_pending) 3655 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); 3656 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3657 if (ctx->ifc_flags & IFC_LEGACY) 3658 IFDI_INTR_ENABLE(ctx); 3659 else { 3660 rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3661 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3662 } 3663 } 3664 3665 static void 3666 _task_fn_rx(void *context) 3667 { 3668 iflib_rxq_t rxq = context; 3669 if_ctx_t ctx = rxq->ifr_ctx; 3670 bool more; 3671 int rc; 3672 uint16_t budget; 3673 3674 #ifdef IFLIB_DIAGNOSTICS 3675 rxq->ifr_cpu_exec_count[curcpu]++; 3676 #endif 3677 DBG_COUNTER_INC(task_fn_rxs); 3678 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3679 return; 3680 more = true; 3681 #ifdef DEV_NETMAP 3682 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3683 u_int work = 0; 3684 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3685 more = false; 3686 } 3687 } 3688 #endif 3689 budget = ctx->ifc_sysctl_rx_budget; 3690 if (budget == 0) 3691 budget = 16; /* XXX */ 3692 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3693 if (ctx->ifc_flags & IFC_LEGACY) 3694 IFDI_INTR_ENABLE(ctx); 3695 else { 3696 DBG_COUNTER_INC(rx_intr_enables); 3697 rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3698 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3699 } 3700 } 3701 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3702 return; 3703 if (more) 3704 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3705 } 3706 3707 static void 3708 _task_fn_admin(void *context) 3709 { 3710 if_ctx_t ctx = context; 3711 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3712 iflib_txq_t txq; 3713 int i; 3714 bool oactive, running, do_reset, do_watchdog; 3715 3716 STATE_LOCK(ctx); 3717 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3718 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3719 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3720 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3721 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3722 STATE_UNLOCK(ctx); 3723 3724 if (!running & !oactive) 3725 return; 3726 3727 CTX_LOCK(ctx); 3728 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3729 CALLOUT_LOCK(txq); 3730 callout_stop(&txq->ift_timer); 3731 CALLOUT_UNLOCK(txq); 3732 } 3733 if (do_watchdog) { 3734 ctx->ifc_watchdog_events++; 3735 IFDI_WATCHDOG_RESET(ctx); 3736 } 3737 IFDI_UPDATE_ADMIN_STATUS(ctx); 3738 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3739 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 3740 IFDI_LINK_INTR_ENABLE(ctx); 3741 if (do_reset) 3742 iflib_if_init_locked(ctx); 3743 CTX_UNLOCK(ctx); 3744 3745 if (LINK_ACTIVE(ctx) == 0) 3746 return; 3747 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3748 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3749 } 3750 3751 3752 static void 3753 _task_fn_iov(void *context) 3754 { 3755 if_ctx_t ctx = context; 3756 3757 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3758 return; 3759 3760 CTX_LOCK(ctx); 3761 IFDI_VFLR_HANDLE(ctx); 3762 CTX_UNLOCK(ctx); 3763 } 3764 3765 static int 3766 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3767 { 3768 int err; 3769 if_int_delay_info_t info; 3770 if_ctx_t ctx; 3771 3772 info = (if_int_delay_info_t)arg1; 3773 ctx = info->iidi_ctx; 3774 info->iidi_req = req; 3775 info->iidi_oidp = oidp; 3776 CTX_LOCK(ctx); 3777 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3778 CTX_UNLOCK(ctx); 3779 return (err); 3780 } 3781 3782 /********************************************************************* 3783 * 3784 * IFNET FUNCTIONS 3785 * 3786 **********************************************************************/ 3787 3788 static void 3789 iflib_if_init_locked(if_ctx_t ctx) 3790 { 3791 iflib_stop(ctx); 3792 iflib_init_locked(ctx); 3793 } 3794 3795 3796 static void 3797 iflib_if_init(void *arg) 3798 { 3799 if_ctx_t ctx = arg; 3800 3801 CTX_LOCK(ctx); 3802 iflib_if_init_locked(ctx); 3803 CTX_UNLOCK(ctx); 3804 } 3805 3806 static int 3807 iflib_if_transmit(if_t ifp, struct mbuf *m) 3808 { 3809 if_ctx_t ctx = if_getsoftc(ifp); 3810 3811 iflib_txq_t txq; 3812 int err, qidx; 3813 3814 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3815 DBG_COUNTER_INC(tx_frees); 3816 m_freem(m); 3817 return (ENOBUFS); 3818 } 3819 3820 MPASS(m->m_nextpkt == NULL); 3821 qidx = 0; 3822 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3823 qidx = QIDX(ctx, m); 3824 /* 3825 * XXX calculate buf_ring based on flowid (divvy up bits?) 3826 */ 3827 txq = &ctx->ifc_txqs[qidx]; 3828 3829 #ifdef DRIVER_BACKPRESSURE 3830 if (txq->ift_closed) { 3831 while (m != NULL) { 3832 next = m->m_nextpkt; 3833 m->m_nextpkt = NULL; 3834 m_freem(m); 3835 m = next; 3836 } 3837 return (ENOBUFS); 3838 } 3839 #endif 3840 #ifdef notyet 3841 qidx = count = 0; 3842 mp = marr; 3843 next = m; 3844 do { 3845 count++; 3846 next = next->m_nextpkt; 3847 } while (next != NULL); 3848 3849 if (count > nitems(marr)) 3850 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3851 /* XXX check nextpkt */ 3852 m_freem(m); 3853 /* XXX simplify for now */ 3854 DBG_COUNTER_INC(tx_frees); 3855 return (ENOBUFS); 3856 } 3857 for (next = m, i = 0; next != NULL; i++) { 3858 mp[i] = next; 3859 next = next->m_nextpkt; 3860 mp[i]->m_nextpkt = NULL; 3861 } 3862 #endif 3863 DBG_COUNTER_INC(tx_seen); 3864 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); 3865 3866 GROUPTASK_ENQUEUE(&txq->ift_task); 3867 if (err) { 3868 /* support forthcoming later */ 3869 #ifdef DRIVER_BACKPRESSURE 3870 txq->ift_closed = TRUE; 3871 #endif 3872 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3873 m_freem(m); 3874 } 3875 3876 return (err); 3877 } 3878 3879 static void 3880 iflib_if_qflush(if_t ifp) 3881 { 3882 if_ctx_t ctx = if_getsoftc(ifp); 3883 iflib_txq_t txq = ctx->ifc_txqs; 3884 int i; 3885 3886 STATE_LOCK(ctx); 3887 ctx->ifc_flags |= IFC_QFLUSH; 3888 STATE_UNLOCK(ctx); 3889 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3890 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3891 iflib_txq_check_drain(txq, 0); 3892 STATE_LOCK(ctx); 3893 ctx->ifc_flags &= ~IFC_QFLUSH; 3894 STATE_UNLOCK(ctx); 3895 3896 if_qflush(ifp); 3897 } 3898 3899 3900 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3901 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 3902 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 3903 3904 static int 3905 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 3906 { 3907 if_ctx_t ctx = if_getsoftc(ifp); 3908 struct ifreq *ifr = (struct ifreq *)data; 3909 #if defined(INET) || defined(INET6) 3910 struct ifaddr *ifa = (struct ifaddr *)data; 3911 #endif 3912 bool avoid_reset = FALSE; 3913 int err = 0, reinit = 0, bits; 3914 3915 switch (command) { 3916 case SIOCSIFADDR: 3917 #ifdef INET 3918 if (ifa->ifa_addr->sa_family == AF_INET) 3919 avoid_reset = TRUE; 3920 #endif 3921 #ifdef INET6 3922 if (ifa->ifa_addr->sa_family == AF_INET6) 3923 avoid_reset = TRUE; 3924 #endif 3925 /* 3926 ** Calling init results in link renegotiation, 3927 ** so we avoid doing it when possible. 3928 */ 3929 if (avoid_reset) { 3930 if_setflagbits(ifp, IFF_UP,0); 3931 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING)) 3932 reinit = 1; 3933 #ifdef INET 3934 if (!(if_getflags(ifp) & IFF_NOARP)) 3935 arp_ifinit(ifp, ifa); 3936 #endif 3937 } else 3938 err = ether_ioctl(ifp, command, data); 3939 break; 3940 case SIOCSIFMTU: 3941 CTX_LOCK(ctx); 3942 if (ifr->ifr_mtu == if_getmtu(ifp)) { 3943 CTX_UNLOCK(ctx); 3944 break; 3945 } 3946 bits = if_getdrvflags(ifp); 3947 /* stop the driver and free any clusters before proceeding */ 3948 iflib_stop(ctx); 3949 3950 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 3951 STATE_LOCK(ctx); 3952 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 3953 ctx->ifc_flags |= IFC_MULTISEG; 3954 else 3955 ctx->ifc_flags &= ~IFC_MULTISEG; 3956 STATE_UNLOCK(ctx); 3957 err = if_setmtu(ifp, ifr->ifr_mtu); 3958 } 3959 iflib_init_locked(ctx); 3960 STATE_LOCK(ctx); 3961 if_setdrvflags(ifp, bits); 3962 STATE_UNLOCK(ctx); 3963 CTX_UNLOCK(ctx); 3964 break; 3965 case SIOCSIFFLAGS: 3966 CTX_LOCK(ctx); 3967 if (if_getflags(ifp) & IFF_UP) { 3968 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3969 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 3970 (IFF_PROMISC | IFF_ALLMULTI)) { 3971 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 3972 } 3973 } else 3974 reinit = 1; 3975 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3976 iflib_stop(ctx); 3977 } 3978 ctx->ifc_if_flags = if_getflags(ifp); 3979 CTX_UNLOCK(ctx); 3980 break; 3981 case SIOCADDMULTI: 3982 case SIOCDELMULTI: 3983 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3984 CTX_LOCK(ctx); 3985 IFDI_INTR_DISABLE(ctx); 3986 IFDI_MULTI_SET(ctx); 3987 IFDI_INTR_ENABLE(ctx); 3988 CTX_UNLOCK(ctx); 3989 } 3990 break; 3991 case SIOCSIFMEDIA: 3992 CTX_LOCK(ctx); 3993 IFDI_MEDIA_SET(ctx); 3994 CTX_UNLOCK(ctx); 3995 /* falls thru */ 3996 case SIOCGIFMEDIA: 3997 case SIOCGIFXMEDIA: 3998 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 3999 break; 4000 case SIOCGI2C: 4001 { 4002 struct ifi2creq i2c; 4003 4004 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4005 if (err != 0) 4006 break; 4007 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4008 err = EINVAL; 4009 break; 4010 } 4011 if (i2c.len > sizeof(i2c.data)) { 4012 err = EINVAL; 4013 break; 4014 } 4015 4016 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4017 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4018 sizeof(i2c)); 4019 break; 4020 } 4021 case SIOCSIFCAP: 4022 { 4023 int mask, setmask; 4024 4025 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 4026 setmask = 0; 4027 #ifdef TCP_OFFLOAD 4028 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4029 #endif 4030 setmask |= (mask & IFCAP_FLAGS); 4031 4032 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 4033 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4034 if ((mask & IFCAP_WOL) && 4035 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 4036 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 4037 if_vlancap(ifp); 4038 /* 4039 * want to ensure that traffic has stopped before we change any of the flags 4040 */ 4041 if (setmask) { 4042 CTX_LOCK(ctx); 4043 bits = if_getdrvflags(ifp); 4044 if (bits & IFF_DRV_RUNNING) 4045 iflib_stop(ctx); 4046 STATE_LOCK(ctx); 4047 if_togglecapenable(ifp, setmask); 4048 STATE_UNLOCK(ctx); 4049 if (bits & IFF_DRV_RUNNING) 4050 iflib_init_locked(ctx); 4051 STATE_LOCK(ctx); 4052 if_setdrvflags(ifp, bits); 4053 STATE_UNLOCK(ctx); 4054 CTX_UNLOCK(ctx); 4055 } 4056 break; 4057 } 4058 case SIOCGPRIVATE_0: 4059 case SIOCSDRVSPEC: 4060 case SIOCGDRVSPEC: 4061 CTX_LOCK(ctx); 4062 err = IFDI_PRIV_IOCTL(ctx, command, data); 4063 CTX_UNLOCK(ctx); 4064 break; 4065 default: 4066 err = ether_ioctl(ifp, command, data); 4067 break; 4068 } 4069 if (reinit) 4070 iflib_if_init(ctx); 4071 return (err); 4072 } 4073 4074 static uint64_t 4075 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4076 { 4077 if_ctx_t ctx = if_getsoftc(ifp); 4078 4079 return (IFDI_GET_COUNTER(ctx, cnt)); 4080 } 4081 4082 /********************************************************************* 4083 * 4084 * OTHER FUNCTIONS EXPORTED TO THE STACK 4085 * 4086 **********************************************************************/ 4087 4088 static void 4089 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4090 { 4091 if_ctx_t ctx = if_getsoftc(ifp); 4092 4093 if ((void *)ctx != arg) 4094 return; 4095 4096 if ((vtag == 0) || (vtag > 4095)) 4097 return; 4098 4099 CTX_LOCK(ctx); 4100 IFDI_VLAN_REGISTER(ctx, vtag); 4101 /* Re-init to load the changes */ 4102 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4103 iflib_if_init_locked(ctx); 4104 CTX_UNLOCK(ctx); 4105 } 4106 4107 static void 4108 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4109 { 4110 if_ctx_t ctx = if_getsoftc(ifp); 4111 4112 if ((void *)ctx != arg) 4113 return; 4114 4115 if ((vtag == 0) || (vtag > 4095)) 4116 return; 4117 4118 CTX_LOCK(ctx); 4119 IFDI_VLAN_UNREGISTER(ctx, vtag); 4120 /* Re-init to load the changes */ 4121 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4122 iflib_if_init_locked(ctx); 4123 CTX_UNLOCK(ctx); 4124 } 4125 4126 static void 4127 iflib_led_func(void *arg, int onoff) 4128 { 4129 if_ctx_t ctx = arg; 4130 4131 CTX_LOCK(ctx); 4132 IFDI_LED_FUNC(ctx, onoff); 4133 CTX_UNLOCK(ctx); 4134 } 4135 4136 /********************************************************************* 4137 * 4138 * BUS FUNCTION DEFINITIONS 4139 * 4140 **********************************************************************/ 4141 4142 int 4143 iflib_device_probe(device_t dev) 4144 { 4145 pci_vendor_info_t *ent; 4146 4147 uint16_t pci_vendor_id, pci_device_id; 4148 uint16_t pci_subvendor_id, pci_subdevice_id; 4149 uint16_t pci_rev_id; 4150 if_shared_ctx_t sctx; 4151 4152 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4153 return (ENOTSUP); 4154 4155 pci_vendor_id = pci_get_vendor(dev); 4156 pci_device_id = pci_get_device(dev); 4157 pci_subvendor_id = pci_get_subvendor(dev); 4158 pci_subdevice_id = pci_get_subdevice(dev); 4159 pci_rev_id = pci_get_revid(dev); 4160 if (sctx->isc_parse_devinfo != NULL) 4161 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4162 4163 ent = sctx->isc_vendor_info; 4164 while (ent->pvi_vendor_id != 0) { 4165 if (pci_vendor_id != ent->pvi_vendor_id) { 4166 ent++; 4167 continue; 4168 } 4169 if ((pci_device_id == ent->pvi_device_id) && 4170 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4171 (ent->pvi_subvendor_id == 0)) && 4172 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4173 (ent->pvi_subdevice_id == 0)) && 4174 ((pci_rev_id == ent->pvi_rev_id) || 4175 (ent->pvi_rev_id == 0))) { 4176 4177 device_set_desc_copy(dev, ent->pvi_name); 4178 /* this needs to be changed to zero if the bus probing code 4179 * ever stops re-probing on best match because the sctx 4180 * may have its values over written by register calls 4181 * in subsequent probes 4182 */ 4183 return (BUS_PROBE_DEFAULT); 4184 } 4185 ent++; 4186 } 4187 return (ENXIO); 4188 } 4189 4190 int 4191 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4192 { 4193 int err, rid, msix, msix_bar; 4194 if_ctx_t ctx; 4195 if_t ifp; 4196 if_softc_ctx_t scctx; 4197 int i; 4198 uint16_t main_txq; 4199 uint16_t main_rxq; 4200 4201 4202 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4203 4204 if (sc == NULL) { 4205 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4206 device_set_softc(dev, ctx); 4207 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4208 } 4209 4210 ctx->ifc_sctx = sctx; 4211 ctx->ifc_dev = dev; 4212 ctx->ifc_softc = sc; 4213 4214 if ((err = iflib_register(ctx)) != 0) { 4215 device_printf(dev, "iflib_register failed %d\n", err); 4216 return (err); 4217 } 4218 iflib_add_device_sysctl_pre(ctx); 4219 4220 scctx = &ctx->ifc_softc_ctx; 4221 ifp = ctx->ifc_ifp; 4222 4223 /* 4224 * XXX sanity check that ntxd & nrxd are a power of 2 4225 */ 4226 if (ctx->ifc_sysctl_ntxqs != 0) 4227 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4228 if (ctx->ifc_sysctl_nrxqs != 0) 4229 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4230 4231 for (i = 0; i < sctx->isc_ntxqs; i++) { 4232 if (ctx->ifc_sysctl_ntxds[i] != 0) 4233 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4234 else 4235 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4236 } 4237 4238 for (i = 0; i < sctx->isc_nrxqs; i++) { 4239 if (ctx->ifc_sysctl_nrxds[i] != 0) 4240 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4241 else 4242 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4243 } 4244 4245 for (i = 0; i < sctx->isc_nrxqs; i++) { 4246 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4247 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4248 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4249 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4250 } 4251 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4252 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4253 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4254 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4255 } 4256 } 4257 4258 for (i = 0; i < sctx->isc_ntxqs; i++) { 4259 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4260 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4261 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4262 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4263 } 4264 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4265 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4266 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4267 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4268 } 4269 } 4270 4271 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4272 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4273 return (err); 4274 } 4275 _iflib_pre_assert(scctx); 4276 ctx->ifc_txrx = *scctx->isc_txrx; 4277 4278 #ifdef INVARIANTS 4279 MPASS(scctx->isc_capenable); 4280 if (scctx->isc_capenable & IFCAP_TXCSUM) 4281 MPASS(scctx->isc_tx_csum_flags); 4282 #endif 4283 4284 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4285 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4286 4287 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4288 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4289 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4290 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4291 4292 #ifdef ACPI_DMAR 4293 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4294 ctx->ifc_flags |= IFC_DMAR; 4295 #elif !(defined(__i386__) || defined(__amd64__)) 4296 /* set unconditionally for !x86 */ 4297 ctx->ifc_flags |= IFC_DMAR; 4298 #endif 4299 4300 msix_bar = scctx->isc_msix_bar; 4301 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4302 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4303 4304 /* XXX change for per-queue sizes */ 4305 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4306 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4307 for (i = 0; i < sctx->isc_nrxqs; i++) { 4308 if (!powerof2(scctx->isc_nrxd[i])) { 4309 /* round down instead? */ 4310 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4311 err = EINVAL; 4312 goto fail; 4313 } 4314 } 4315 for (i = 0; i < sctx->isc_ntxqs; i++) { 4316 if (!powerof2(scctx->isc_ntxd[i])) { 4317 device_printf(dev, 4318 "# tx descriptors must be a power of 2"); 4319 err = EINVAL; 4320 goto fail; 4321 } 4322 } 4323 4324 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4325 MAX_SINGLE_PACKET_FRACTION) 4326 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4327 MAX_SINGLE_PACKET_FRACTION); 4328 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4329 MAX_SINGLE_PACKET_FRACTION) 4330 scctx->isc_tx_tso_segments_max = max(1, 4331 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4332 4333 /* 4334 * Protect the stack against modern hardware 4335 */ 4336 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4337 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4338 4339 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4340 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4341 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4342 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4343 if (scctx->isc_rss_table_size == 0) 4344 scctx->isc_rss_table_size = 64; 4345 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4346 4347 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4348 /* XXX format name */ 4349 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4350 4351 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4352 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4353 device_printf(dev, "Unable to fetch CPU list\n"); 4354 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4355 } 4356 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4357 4358 /* 4359 ** Now setup MSI or MSI/X, should 4360 ** return us the number of supported 4361 ** vectors. (Will be 1 for MSI) 4362 */ 4363 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4364 msix = scctx->isc_vectors; 4365 } else if (scctx->isc_msix_bar != 0) 4366 /* 4367 * The simple fact that isc_msix_bar is not 0 does not mean we 4368 * we have a good value there that is known to work. 4369 */ 4370 msix = iflib_msix_init(ctx); 4371 else { 4372 scctx->isc_vectors = 1; 4373 scctx->isc_ntxqsets = 1; 4374 scctx->isc_nrxqsets = 1; 4375 scctx->isc_intr = IFLIB_INTR_LEGACY; 4376 msix = 0; 4377 } 4378 /* Get memory for the station queues */ 4379 if ((err = iflib_queues_alloc(ctx))) { 4380 device_printf(dev, "Unable to allocate queue memory\n"); 4381 goto fail; 4382 } 4383 4384 if ((err = iflib_qset_structures_setup(ctx))) { 4385 device_printf(dev, "qset structure setup failed %d\n", err); 4386 goto fail_queues; 4387 } 4388 4389 /* 4390 * Group taskqueues aren't properly set up until SMP is started, 4391 * so we disable interrupts until we can handle them post 4392 * SI_SUB_SMP. 4393 * 4394 * XXX: disabling interrupts doesn't actually work, at least for 4395 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4396 * we do null handling and depend on this not causing too large an 4397 * interrupt storm. 4398 */ 4399 IFDI_INTR_DISABLE(ctx); 4400 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4401 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4402 goto fail_intr_free; 4403 } 4404 if (msix <= 1) { 4405 rid = 0; 4406 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4407 MPASS(msix == 1); 4408 rid = 1; 4409 } 4410 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4411 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4412 goto fail_intr_free; 4413 } 4414 } 4415 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4416 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4417 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4418 goto fail_detach; 4419 } 4420 if ((err = iflib_netmap_attach(ctx))) { 4421 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4422 goto fail_detach; 4423 } 4424 *ctxp = ctx; 4425 4426 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4427 iflib_add_device_sysctl_post(ctx); 4428 ctx->ifc_flags |= IFC_INIT_DONE; 4429 return (0); 4430 fail_detach: 4431 ether_ifdetach(ctx->ifc_ifp); 4432 fail_intr_free: 4433 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4434 pci_release_msi(ctx->ifc_dev); 4435 fail_queues: 4436 /* XXX free queues */ 4437 fail: 4438 IFDI_DETACH(ctx); 4439 return (err); 4440 } 4441 4442 int 4443 iflib_device_attach(device_t dev) 4444 { 4445 if_ctx_t ctx; 4446 if_shared_ctx_t sctx; 4447 4448 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4449 return (ENOTSUP); 4450 4451 pci_enable_busmaster(dev); 4452 4453 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4454 } 4455 4456 int 4457 iflib_device_deregister(if_ctx_t ctx) 4458 { 4459 if_t ifp = ctx->ifc_ifp; 4460 iflib_txq_t txq; 4461 iflib_rxq_t rxq; 4462 device_t dev = ctx->ifc_dev; 4463 int i, j; 4464 struct taskqgroup *tqg; 4465 iflib_fl_t fl; 4466 4467 /* Make sure VLANS are not using driver */ 4468 if (if_vlantrunkinuse(ifp)) { 4469 device_printf(dev,"Vlan in use, detach first\n"); 4470 return (EBUSY); 4471 } 4472 4473 CTX_LOCK(ctx); 4474 ctx->ifc_in_detach = 1; 4475 iflib_stop(ctx); 4476 CTX_UNLOCK(ctx); 4477 4478 /* Unregister VLAN events */ 4479 if (ctx->ifc_vlan_attach_event != NULL) 4480 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4481 if (ctx->ifc_vlan_detach_event != NULL) 4482 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4483 4484 iflib_netmap_detach(ifp); 4485 ether_ifdetach(ifp); 4486 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4487 CTX_LOCK_DESTROY(ctx); 4488 if (ctx->ifc_led_dev != NULL) 4489 led_destroy(ctx->ifc_led_dev); 4490 /* XXX drain any dependent tasks */ 4491 tqg = qgroup_if_io_tqg; 4492 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4493 callout_drain(&txq->ift_timer); 4494 if (txq->ift_task.gt_uniq != NULL) 4495 taskqgroup_detach(tqg, &txq->ift_task); 4496 } 4497 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4498 if (rxq->ifr_task.gt_uniq != NULL) 4499 taskqgroup_detach(tqg, &rxq->ifr_task); 4500 4501 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4502 free(fl->ifl_rx_bitmap, M_IFLIB); 4503 4504 } 4505 tqg = qgroup_if_config_tqg; 4506 if (ctx->ifc_admin_task.gt_uniq != NULL) 4507 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4508 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4509 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4510 4511 IFDI_DETACH(ctx); 4512 device_set_softc(ctx->ifc_dev, NULL); 4513 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4514 pci_release_msi(dev); 4515 } 4516 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4517 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4518 } 4519 if (ctx->ifc_msix_mem != NULL) { 4520 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4521 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4522 ctx->ifc_msix_mem = NULL; 4523 } 4524 4525 bus_generic_detach(dev); 4526 if_free(ifp); 4527 4528 iflib_tx_structures_free(ctx); 4529 iflib_rx_structures_free(ctx); 4530 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4531 free(ctx->ifc_softc, M_IFLIB); 4532 free(ctx, M_IFLIB); 4533 return (0); 4534 } 4535 4536 4537 int 4538 iflib_device_detach(device_t dev) 4539 { 4540 if_ctx_t ctx = device_get_softc(dev); 4541 4542 return (iflib_device_deregister(ctx)); 4543 } 4544 4545 int 4546 iflib_device_suspend(device_t dev) 4547 { 4548 if_ctx_t ctx = device_get_softc(dev); 4549 4550 CTX_LOCK(ctx); 4551 IFDI_SUSPEND(ctx); 4552 CTX_UNLOCK(ctx); 4553 4554 return bus_generic_suspend(dev); 4555 } 4556 int 4557 iflib_device_shutdown(device_t dev) 4558 { 4559 if_ctx_t ctx = device_get_softc(dev); 4560 4561 CTX_LOCK(ctx); 4562 IFDI_SHUTDOWN(ctx); 4563 CTX_UNLOCK(ctx); 4564 4565 return bus_generic_suspend(dev); 4566 } 4567 4568 4569 int 4570 iflib_device_resume(device_t dev) 4571 { 4572 if_ctx_t ctx = device_get_softc(dev); 4573 iflib_txq_t txq = ctx->ifc_txqs; 4574 4575 CTX_LOCK(ctx); 4576 IFDI_RESUME(ctx); 4577 iflib_init_locked(ctx); 4578 CTX_UNLOCK(ctx); 4579 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4580 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4581 4582 return (bus_generic_resume(dev)); 4583 } 4584 4585 int 4586 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4587 { 4588 int error; 4589 if_ctx_t ctx = device_get_softc(dev); 4590 4591 CTX_LOCK(ctx); 4592 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4593 CTX_UNLOCK(ctx); 4594 4595 return (error); 4596 } 4597 4598 void 4599 iflib_device_iov_uninit(device_t dev) 4600 { 4601 if_ctx_t ctx = device_get_softc(dev); 4602 4603 CTX_LOCK(ctx); 4604 IFDI_IOV_UNINIT(ctx); 4605 CTX_UNLOCK(ctx); 4606 } 4607 4608 int 4609 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 4610 { 4611 int error; 4612 if_ctx_t ctx = device_get_softc(dev); 4613 4614 CTX_LOCK(ctx); 4615 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 4616 CTX_UNLOCK(ctx); 4617 4618 return (error); 4619 } 4620 4621 /********************************************************************* 4622 * 4623 * MODULE FUNCTION DEFINITIONS 4624 * 4625 **********************************************************************/ 4626 4627 /* 4628 * - Start a fast taskqueue thread for each core 4629 * - Start a taskqueue for control operations 4630 */ 4631 static int 4632 iflib_module_init(void) 4633 { 4634 return (0); 4635 } 4636 4637 static int 4638 iflib_module_event_handler(module_t mod, int what, void *arg) 4639 { 4640 int err; 4641 4642 switch (what) { 4643 case MOD_LOAD: 4644 if ((err = iflib_module_init()) != 0) 4645 return (err); 4646 break; 4647 case MOD_UNLOAD: 4648 return (EBUSY); 4649 default: 4650 return (EOPNOTSUPP); 4651 } 4652 4653 return (0); 4654 } 4655 4656 /********************************************************************* 4657 * 4658 * PUBLIC FUNCTION DEFINITIONS 4659 * ordered as in iflib.h 4660 * 4661 **********************************************************************/ 4662 4663 4664 static void 4665 _iflib_assert(if_shared_ctx_t sctx) 4666 { 4667 MPASS(sctx->isc_tx_maxsize); 4668 MPASS(sctx->isc_tx_maxsegsize); 4669 4670 MPASS(sctx->isc_rx_maxsize); 4671 MPASS(sctx->isc_rx_nsegments); 4672 MPASS(sctx->isc_rx_maxsegsize); 4673 4674 MPASS(sctx->isc_nrxd_min[0]); 4675 MPASS(sctx->isc_nrxd_max[0]); 4676 MPASS(sctx->isc_nrxd_default[0]); 4677 MPASS(sctx->isc_ntxd_min[0]); 4678 MPASS(sctx->isc_ntxd_max[0]); 4679 MPASS(sctx->isc_ntxd_default[0]); 4680 } 4681 4682 static void 4683 _iflib_pre_assert(if_softc_ctx_t scctx) 4684 { 4685 4686 MPASS(scctx->isc_txrx->ift_txd_encap); 4687 MPASS(scctx->isc_txrx->ift_txd_flush); 4688 MPASS(scctx->isc_txrx->ift_txd_credits_update); 4689 MPASS(scctx->isc_txrx->ift_rxd_available); 4690 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 4691 MPASS(scctx->isc_txrx->ift_rxd_refill); 4692 MPASS(scctx->isc_txrx->ift_rxd_flush); 4693 } 4694 4695 static int 4696 iflib_register(if_ctx_t ctx) 4697 { 4698 if_shared_ctx_t sctx = ctx->ifc_sctx; 4699 driver_t *driver = sctx->isc_driver; 4700 device_t dev = ctx->ifc_dev; 4701 if_t ifp; 4702 4703 _iflib_assert(sctx); 4704 4705 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 4706 4707 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 4708 if (ifp == NULL) { 4709 device_printf(dev, "can not allocate ifnet structure\n"); 4710 return (ENOMEM); 4711 } 4712 4713 /* 4714 * Initialize our context's device specific methods 4715 */ 4716 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 4717 kobj_class_compile((kobj_class_t) driver); 4718 driver->refs++; 4719 4720 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 4721 if_setsoftc(ifp, ctx); 4722 if_setdev(ifp, dev); 4723 if_setinitfn(ifp, iflib_if_init); 4724 if_setioctlfn(ifp, iflib_if_ioctl); 4725 if_settransmitfn(ifp, iflib_if_transmit); 4726 if_setqflushfn(ifp, iflib_if_qflush); 4727 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 4728 4729 ctx->ifc_vlan_attach_event = 4730 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 4731 EVENTHANDLER_PRI_FIRST); 4732 ctx->ifc_vlan_detach_event = 4733 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 4734 EVENTHANDLER_PRI_FIRST); 4735 4736 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 4737 iflib_media_change, iflib_media_status); 4738 4739 return (0); 4740 } 4741 4742 4743 static int 4744 iflib_queues_alloc(if_ctx_t ctx) 4745 { 4746 if_shared_ctx_t sctx = ctx->ifc_sctx; 4747 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4748 device_t dev = ctx->ifc_dev; 4749 int nrxqsets = scctx->isc_nrxqsets; 4750 int ntxqsets = scctx->isc_ntxqsets; 4751 iflib_txq_t txq; 4752 iflib_rxq_t rxq; 4753 iflib_fl_t fl = NULL; 4754 int i, j, cpu, err, txconf, rxconf; 4755 iflib_dma_info_t ifdip; 4756 uint32_t *rxqsizes = scctx->isc_rxqsizes; 4757 uint32_t *txqsizes = scctx->isc_txqsizes; 4758 uint8_t nrxqs = sctx->isc_nrxqs; 4759 uint8_t ntxqs = sctx->isc_ntxqs; 4760 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 4761 caddr_t *vaddrs; 4762 uint64_t *paddrs; 4763 struct ifmp_ring **brscp; 4764 4765 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 4766 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 4767 4768 brscp = NULL; 4769 txq = NULL; 4770 rxq = NULL; 4771 4772 /* Allocate the TX ring struct memory */ 4773 if (!(txq = 4774 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 4775 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4776 device_printf(dev, "Unable to allocate TX ring memory\n"); 4777 err = ENOMEM; 4778 goto fail; 4779 } 4780 4781 /* Now allocate the RX */ 4782 if (!(rxq = 4783 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 4784 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4785 device_printf(dev, "Unable to allocate RX ring memory\n"); 4786 err = ENOMEM; 4787 goto rx_fail; 4788 } 4789 4790 ctx->ifc_txqs = txq; 4791 ctx->ifc_rxqs = rxq; 4792 4793 /* 4794 * XXX handle allocation failure 4795 */ 4796 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 4797 /* Set up some basics */ 4798 4799 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4800 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4801 err = ENOMEM; 4802 goto err_tx_desc; 4803 } 4804 txq->ift_ifdi = ifdip; 4805 for (j = 0; j < ntxqs; j++, ifdip++) { 4806 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4807 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4808 err = ENOMEM; 4809 goto err_tx_desc; 4810 } 4811 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 4812 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 4813 } 4814 txq->ift_ctx = ctx; 4815 txq->ift_id = i; 4816 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 4817 txq->ift_br_offset = 1; 4818 } else { 4819 txq->ift_br_offset = 0; 4820 } 4821 /* XXX fix this */ 4822 txq->ift_timer.c_cpu = cpu; 4823 4824 if (iflib_txsd_alloc(txq)) { 4825 device_printf(dev, "Critical Failure setting up TX buffers\n"); 4826 err = ENOMEM; 4827 goto err_tx_desc; 4828 } 4829 4830 /* Initialize the TX lock */ 4831 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 4832 device_get_nameunit(dev), txq->ift_id); 4833 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 4834 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 4835 4836 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 4837 device_get_nameunit(dev), txq->ift_id); 4838 4839 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 4840 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 4841 if (err) { 4842 /* XXX free any allocated rings */ 4843 device_printf(dev, "Unable to allocate buf_ring\n"); 4844 goto err_tx_desc; 4845 } 4846 } 4847 4848 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 4849 /* Set up some basics */ 4850 4851 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4852 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4853 err = ENOMEM; 4854 goto err_tx_desc; 4855 } 4856 4857 rxq->ifr_ifdi = ifdip; 4858 /* XXX this needs to be changed if #rx queues != #tx queues */ 4859 rxq->ifr_ntxqirq = 1; 4860 rxq->ifr_txqid[0] = i; 4861 for (j = 0; j < nrxqs; j++, ifdip++) { 4862 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4863 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4864 err = ENOMEM; 4865 goto err_tx_desc; 4866 } 4867 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 4868 } 4869 rxq->ifr_ctx = ctx; 4870 rxq->ifr_id = i; 4871 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 4872 rxq->ifr_fl_offset = 1; 4873 } else { 4874 rxq->ifr_fl_offset = 0; 4875 } 4876 rxq->ifr_nfl = nfree_lists; 4877 if (!(fl = 4878 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 4879 device_printf(dev, "Unable to allocate free list memory\n"); 4880 err = ENOMEM; 4881 goto err_tx_desc; 4882 } 4883 rxq->ifr_fl = fl; 4884 for (j = 0; j < nfree_lists; j++) { 4885 fl[j].ifl_rxq = rxq; 4886 fl[j].ifl_id = j; 4887 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 4888 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 4889 } 4890 /* Allocate receive buffers for the ring*/ 4891 if (iflib_rxsd_alloc(rxq)) { 4892 device_printf(dev, 4893 "Critical Failure setting up receive buffers\n"); 4894 err = ENOMEM; 4895 goto err_rx_desc; 4896 } 4897 4898 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4899 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 4900 } 4901 4902 /* TXQs */ 4903 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4904 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4905 for (i = 0; i < ntxqsets; i++) { 4906 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 4907 4908 for (j = 0; j < ntxqs; j++, di++) { 4909 vaddrs[i*ntxqs + j] = di->idi_vaddr; 4910 paddrs[i*ntxqs + j] = di->idi_paddr; 4911 } 4912 } 4913 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 4914 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4915 iflib_tx_structures_free(ctx); 4916 free(vaddrs, M_IFLIB); 4917 free(paddrs, M_IFLIB); 4918 goto err_rx_desc; 4919 } 4920 free(vaddrs, M_IFLIB); 4921 free(paddrs, M_IFLIB); 4922 4923 /* RXQs */ 4924 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4925 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4926 for (i = 0; i < nrxqsets; i++) { 4927 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 4928 4929 for (j = 0; j < nrxqs; j++, di++) { 4930 vaddrs[i*nrxqs + j] = di->idi_vaddr; 4931 paddrs[i*nrxqs + j] = di->idi_paddr; 4932 } 4933 } 4934 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 4935 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4936 iflib_tx_structures_free(ctx); 4937 free(vaddrs, M_IFLIB); 4938 free(paddrs, M_IFLIB); 4939 goto err_rx_desc; 4940 } 4941 free(vaddrs, M_IFLIB); 4942 free(paddrs, M_IFLIB); 4943 4944 return (0); 4945 4946 /* XXX handle allocation failure changes */ 4947 err_rx_desc: 4948 err_tx_desc: 4949 if (ctx->ifc_rxqs != NULL) 4950 free(ctx->ifc_rxqs, M_IFLIB); 4951 ctx->ifc_rxqs = NULL; 4952 if (ctx->ifc_txqs != NULL) 4953 free(ctx->ifc_txqs, M_IFLIB); 4954 ctx->ifc_txqs = NULL; 4955 rx_fail: 4956 if (brscp != NULL) 4957 free(brscp, M_IFLIB); 4958 if (rxq != NULL) 4959 free(rxq, M_IFLIB); 4960 if (txq != NULL) 4961 free(txq, M_IFLIB); 4962 fail: 4963 return (err); 4964 } 4965 4966 static int 4967 iflib_tx_structures_setup(if_ctx_t ctx) 4968 { 4969 iflib_txq_t txq = ctx->ifc_txqs; 4970 int i; 4971 4972 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4973 iflib_txq_setup(txq); 4974 4975 return (0); 4976 } 4977 4978 static void 4979 iflib_tx_structures_free(if_ctx_t ctx) 4980 { 4981 iflib_txq_t txq = ctx->ifc_txqs; 4982 int i, j; 4983 4984 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 4985 iflib_txq_destroy(txq); 4986 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 4987 iflib_dma_free(&txq->ift_ifdi[j]); 4988 } 4989 free(ctx->ifc_txqs, M_IFLIB); 4990 ctx->ifc_txqs = NULL; 4991 IFDI_QUEUES_FREE(ctx); 4992 } 4993 4994 /********************************************************************* 4995 * 4996 * Initialize all receive rings. 4997 * 4998 **********************************************************************/ 4999 static int 5000 iflib_rx_structures_setup(if_ctx_t ctx) 5001 { 5002 iflib_rxq_t rxq = ctx->ifc_rxqs; 5003 int q; 5004 #if defined(INET6) || defined(INET) 5005 int i, err; 5006 #endif 5007 5008 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5009 #if defined(INET6) || defined(INET) 5010 tcp_lro_free(&rxq->ifr_lc); 5011 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5012 TCP_LRO_ENTRIES, min(1024, 5013 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 5014 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 5015 goto fail; 5016 } 5017 rxq->ifr_lro_enabled = TRUE; 5018 #endif 5019 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5020 } 5021 return (0); 5022 #if defined(INET6) || defined(INET) 5023 fail: 5024 /* 5025 * Free RX software descriptors allocated so far, we will only handle 5026 * the rings that completed, the failing case will have 5027 * cleaned up for itself. 'q' failed, so its the terminus. 5028 */ 5029 rxq = ctx->ifc_rxqs; 5030 for (i = 0; i < q; ++i, rxq++) { 5031 iflib_rx_sds_free(rxq); 5032 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5033 } 5034 return (err); 5035 #endif 5036 } 5037 5038 /********************************************************************* 5039 * 5040 * Free all receive rings. 5041 * 5042 **********************************************************************/ 5043 static void 5044 iflib_rx_structures_free(if_ctx_t ctx) 5045 { 5046 iflib_rxq_t rxq = ctx->ifc_rxqs; 5047 5048 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5049 iflib_rx_sds_free(rxq); 5050 } 5051 } 5052 5053 static int 5054 iflib_qset_structures_setup(if_ctx_t ctx) 5055 { 5056 int err; 5057 5058 if ((err = iflib_tx_structures_setup(ctx)) != 0) 5059 return (err); 5060 5061 if ((err = iflib_rx_structures_setup(ctx)) != 0) { 5062 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5063 iflib_tx_structures_free(ctx); 5064 iflib_rx_structures_free(ctx); 5065 } 5066 return (err); 5067 } 5068 5069 int 5070 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5071 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name) 5072 { 5073 5074 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5075 } 5076 5077 #ifdef SMP 5078 static int 5079 find_nth(if_ctx_t ctx, int qid) 5080 { 5081 cpuset_t cpus; 5082 int i, cpuid, eqid, count; 5083 5084 CPU_COPY(&ctx->ifc_cpus, &cpus); 5085 count = CPU_COUNT(&cpus); 5086 eqid = qid % count; 5087 /* clear up to the qid'th bit */ 5088 for (i = 0; i < eqid; i++) { 5089 cpuid = CPU_FFS(&cpus); 5090 MPASS(cpuid != 0); 5091 CPU_CLR(cpuid-1, &cpus); 5092 } 5093 cpuid = CPU_FFS(&cpus); 5094 MPASS(cpuid != 0); 5095 return (cpuid-1); 5096 } 5097 5098 #ifdef SCHED_ULE 5099 extern struct cpu_group *cpu_top; /* CPU topology */ 5100 5101 static int 5102 find_child_with_core(int cpu, struct cpu_group *grp) 5103 { 5104 int i; 5105 5106 if (grp->cg_children == 0) 5107 return -1; 5108 5109 MPASS(grp->cg_child); 5110 for (i = 0; i < grp->cg_children; i++) { 5111 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5112 return i; 5113 } 5114 5115 return -1; 5116 } 5117 5118 /* 5119 * Find the nth thread on the specified core 5120 */ 5121 static int 5122 find_thread(int cpu, int thread_num) 5123 { 5124 struct cpu_group *grp; 5125 int i; 5126 cpuset_t cs; 5127 5128 grp = cpu_top; 5129 if (grp == NULL) 5130 return cpu; 5131 i = 0; 5132 while ((i = find_child_with_core(cpu, grp)) != -1) { 5133 /* If the child only has one cpu, don't descend */ 5134 if (grp->cg_child[i].cg_count <= 1) 5135 break; 5136 grp = &grp->cg_child[i]; 5137 } 5138 5139 /* If they don't share at least an L2 cache, use the same CPU */ 5140 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5141 return cpu; 5142 5143 /* Now pick one */ 5144 CPU_COPY(&grp->cg_mask, &cs); 5145 for (i = thread_num % grp->cg_count; i > 0; i--) { 5146 MPASS(CPU_FFS(&cs)); 5147 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5148 } 5149 MPASS(CPU_FFS(&cs)); 5150 return CPU_FFS(&cs) - 1; 5151 } 5152 #else 5153 static int 5154 find_thread(int cpu, int thread_num __unused) 5155 { 5156 return cpu; 5157 } 5158 #endif 5159 5160 static int 5161 get_thread_num(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5162 { 5163 switch (type) { 5164 case IFLIB_INTR_TX: 5165 /* TX queues get threads on the same core as the corresponding RX queue */ 5166 /* XXX handle multiple RX threads per core and more than two threads per core */ 5167 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5168 case IFLIB_INTR_RX: 5169 case IFLIB_INTR_RXTX: 5170 /* RX queues get the first thread on their core */ 5171 return qid / CPU_COUNT(&ctx->ifc_cpus); 5172 default: 5173 return -1; 5174 } 5175 } 5176 #else 5177 #define get_thread_num(ctx, type, qid) CPU_FIRST() 5178 #define find_thread(cpuid, tid) CPU_FIRST() 5179 #define find_nth(ctx, gid) CPU_FIRST() 5180 #endif 5181 5182 /* Just to avoid copy/paste */ 5183 static inline int 5184 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid, 5185 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, char *name) 5186 { 5187 int cpuid; 5188 int err, tid; 5189 5190 cpuid = find_nth(ctx, qid); 5191 tid = get_thread_num(ctx, type, qid); 5192 MPASS(tid >= 0); 5193 cpuid = find_thread(cpuid, tid); 5194 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name); 5195 if (err) { 5196 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err); 5197 return (err); 5198 } 5199 #ifdef notyet 5200 if (cpuid > ctx->ifc_cpuid_highest) 5201 ctx->ifc_cpuid_highest = cpuid; 5202 #endif 5203 return 0; 5204 } 5205 5206 int 5207 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5208 iflib_intr_type_t type, driver_filter_t *filter, 5209 void *filter_arg, int qid, char *name) 5210 { 5211 struct grouptask *gtask; 5212 struct taskqgroup *tqg; 5213 iflib_filter_info_t info; 5214 gtask_fn_t *fn; 5215 int tqrid, err; 5216 driver_filter_t *intr_fast; 5217 void *q; 5218 5219 info = &ctx->ifc_filter_info; 5220 tqrid = rid; 5221 5222 switch (type) { 5223 /* XXX merge tx/rx for netmap? */ 5224 case IFLIB_INTR_TX: 5225 q = &ctx->ifc_txqs[qid]; 5226 info = &ctx->ifc_txqs[qid].ift_filter_info; 5227 gtask = &ctx->ifc_txqs[qid].ift_task; 5228 tqg = qgroup_if_io_tqg; 5229 fn = _task_fn_tx; 5230 intr_fast = iflib_fast_intr; 5231 GROUPTASK_INIT(gtask, 0, fn, q); 5232 break; 5233 case IFLIB_INTR_RX: 5234 q = &ctx->ifc_rxqs[qid]; 5235 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5236 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5237 tqg = qgroup_if_io_tqg; 5238 fn = _task_fn_rx; 5239 intr_fast = iflib_fast_intr; 5240 GROUPTASK_INIT(gtask, 0, fn, q); 5241 break; 5242 case IFLIB_INTR_RXTX: 5243 q = &ctx->ifc_rxqs[qid]; 5244 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5245 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5246 tqg = qgroup_if_io_tqg; 5247 fn = _task_fn_rx; 5248 intr_fast = iflib_fast_intr_rxtx; 5249 GROUPTASK_INIT(gtask, 0, fn, q); 5250 break; 5251 case IFLIB_INTR_ADMIN: 5252 q = ctx; 5253 tqrid = -1; 5254 info = &ctx->ifc_filter_info; 5255 gtask = &ctx->ifc_admin_task; 5256 tqg = qgroup_if_config_tqg; 5257 fn = _task_fn_admin; 5258 intr_fast = iflib_fast_intr_ctx; 5259 break; 5260 default: 5261 panic("unknown net intr type"); 5262 } 5263 5264 info->ifi_filter = filter; 5265 info->ifi_filter_arg = filter_arg; 5266 info->ifi_task = gtask; 5267 info->ifi_ctx = q; 5268 5269 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5270 if (err != 0) { 5271 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 5272 return (err); 5273 } 5274 if (type == IFLIB_INTR_ADMIN) 5275 return (0); 5276 5277 if (tqrid != -1) { 5278 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name); 5279 if (err) 5280 return (err); 5281 } else { 5282 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5283 } 5284 5285 return (0); 5286 } 5287 5288 void 5289 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, char *name) 5290 { 5291 struct grouptask *gtask; 5292 struct taskqgroup *tqg; 5293 gtask_fn_t *fn; 5294 void *q; 5295 int irq_num = -1; 5296 int err; 5297 5298 switch (type) { 5299 case IFLIB_INTR_TX: 5300 q = &ctx->ifc_txqs[qid]; 5301 gtask = &ctx->ifc_txqs[qid].ift_task; 5302 tqg = qgroup_if_io_tqg; 5303 fn = _task_fn_tx; 5304 if (irq != NULL) 5305 irq_num = rman_get_start(irq->ii_res); 5306 break; 5307 case IFLIB_INTR_RX: 5308 q = &ctx->ifc_rxqs[qid]; 5309 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5310 tqg = qgroup_if_io_tqg; 5311 fn = _task_fn_rx; 5312 if (irq != NULL) 5313 irq_num = rman_get_start(irq->ii_res); 5314 break; 5315 case IFLIB_INTR_IOV: 5316 q = ctx; 5317 gtask = &ctx->ifc_vflr_task; 5318 tqg = qgroup_if_config_tqg; 5319 fn = _task_fn_iov; 5320 break; 5321 default: 5322 panic("unknown net intr type"); 5323 } 5324 GROUPTASK_INIT(gtask, 0, fn, q); 5325 if (irq_num != -1) { 5326 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name); 5327 if (err) 5328 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5329 } 5330 else { 5331 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5332 } 5333 } 5334 5335 void 5336 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5337 { 5338 if (irq->ii_tag) 5339 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5340 5341 if (irq->ii_res) 5342 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5343 } 5344 5345 static int 5346 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name) 5347 { 5348 iflib_txq_t txq = ctx->ifc_txqs; 5349 iflib_rxq_t rxq = ctx->ifc_rxqs; 5350 if_irq_t irq = &ctx->ifc_legacy_irq; 5351 iflib_filter_info_t info; 5352 struct grouptask *gtask; 5353 struct taskqgroup *tqg; 5354 gtask_fn_t *fn; 5355 int tqrid; 5356 void *q; 5357 int err; 5358 5359 q = &ctx->ifc_rxqs[0]; 5360 info = &rxq[0].ifr_filter_info; 5361 gtask = &rxq[0].ifr_task; 5362 tqg = qgroup_if_io_tqg; 5363 tqrid = irq->ii_rid = *rid; 5364 fn = _task_fn_rx; 5365 5366 ctx->ifc_flags |= IFC_LEGACY; 5367 info->ifi_filter = filter; 5368 info->ifi_filter_arg = filter_arg; 5369 info->ifi_task = gtask; 5370 info->ifi_ctx = ctx; 5371 5372 /* We allocate a single interrupt resource */ 5373 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5374 return (err); 5375 GROUPTASK_INIT(gtask, 0, fn, q); 5376 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5377 5378 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5379 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx"); 5380 return (0); 5381 } 5382 5383 void 5384 iflib_led_create(if_ctx_t ctx) 5385 { 5386 5387 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5388 device_get_nameunit(ctx->ifc_dev)); 5389 } 5390 5391 void 5392 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5393 { 5394 5395 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5396 } 5397 5398 void 5399 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5400 { 5401 5402 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5403 } 5404 5405 void 5406 iflib_admin_intr_deferred(if_ctx_t ctx) 5407 { 5408 #ifdef INVARIANTS 5409 struct grouptask *gtask; 5410 5411 gtask = &ctx->ifc_admin_task; 5412 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5413 #endif 5414 5415 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5416 } 5417 5418 void 5419 iflib_iov_intr_deferred(if_ctx_t ctx) 5420 { 5421 5422 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5423 } 5424 5425 void 5426 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5427 { 5428 5429 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5430 } 5431 5432 void 5433 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn, 5434 char *name) 5435 { 5436 5437 GROUPTASK_INIT(gtask, 0, fn, ctx); 5438 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5439 } 5440 5441 void 5442 iflib_config_gtask_deinit(struct grouptask *gtask) 5443 { 5444 5445 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5446 } 5447 5448 void 5449 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5450 { 5451 if_t ifp = ctx->ifc_ifp; 5452 iflib_txq_t txq = ctx->ifc_txqs; 5453 5454 if_setbaudrate(ifp, baudrate); 5455 if (baudrate >= IF_Gbps(10)) { 5456 STATE_LOCK(ctx); 5457 ctx->ifc_flags |= IFC_PREFETCH; 5458 STATE_UNLOCK(ctx); 5459 } 5460 /* If link down, disable watchdog */ 5461 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5462 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5463 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5464 } 5465 ctx->ifc_link_state = link_state; 5466 if_link_state_change(ifp, link_state); 5467 } 5468 5469 static int 5470 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5471 { 5472 int credits; 5473 #ifdef INVARIANTS 5474 int credits_pre = txq->ift_cidx_processed; 5475 #endif 5476 5477 if (ctx->isc_txd_credits_update == NULL) 5478 return (0); 5479 5480 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5481 return (0); 5482 5483 txq->ift_processed += credits; 5484 txq->ift_cidx_processed += credits; 5485 5486 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5487 if (txq->ift_cidx_processed >= txq->ift_size) 5488 txq->ift_cidx_processed -= txq->ift_size; 5489 return (credits); 5490 } 5491 5492 static int 5493 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5494 { 5495 5496 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5497 budget)); 5498 } 5499 5500 void 5501 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5502 const char *description, if_int_delay_info_t info, 5503 int offset, int value) 5504 { 5505 info->iidi_ctx = ctx; 5506 info->iidi_offset = offset; 5507 info->iidi_value = value; 5508 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5509 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5510 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5511 info, 0, iflib_sysctl_int_delay, "I", description); 5512 } 5513 5514 struct mtx * 5515 iflib_ctx_lock_get(if_ctx_t ctx) 5516 { 5517 5518 return (&ctx->ifc_ctx_mtx); 5519 } 5520 5521 static int 5522 iflib_msix_init(if_ctx_t ctx) 5523 { 5524 device_t dev = ctx->ifc_dev; 5525 if_shared_ctx_t sctx = ctx->ifc_sctx; 5526 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5527 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5528 int iflib_num_tx_queues, iflib_num_rx_queues; 5529 int err, admincnt, bar; 5530 5531 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 5532 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 5533 5534 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 5535 5536 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5537 admincnt = sctx->isc_admin_intrcnt; 5538 /* Override by global tuneable */ 5539 { 5540 int i; 5541 size_t len = sizeof(i); 5542 err = kernel_sysctlbyname(curthread, "hw.pci.enable_msix", &i, &len, NULL, 0, NULL, 0); 5543 if (err == 0) { 5544 if (i == 0) 5545 goto msi; 5546 } 5547 else { 5548 device_printf(dev, "unable to read hw.pci.enable_msix."); 5549 } 5550 } 5551 /* Override by tuneable */ 5552 if (scctx->isc_disable_msix) 5553 goto msi; 5554 5555 /* 5556 ** When used in a virtualized environment 5557 ** PCI BUSMASTER capability may not be set 5558 ** so explicity set it here and rewrite 5559 ** the ENABLE in the MSIX control register 5560 ** at this point to cause the host to 5561 ** successfully initialize us. 5562 */ 5563 { 5564 int msix_ctrl, rid; 5565 5566 pci_enable_busmaster(dev); 5567 rid = 0; 5568 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) { 5569 rid += PCIR_MSIX_CTRL; 5570 msix_ctrl = pci_read_config(dev, rid, 2); 5571 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 5572 pci_write_config(dev, rid, msix_ctrl, 2); 5573 } else { 5574 device_printf(dev, "PCIY_MSIX capability not found; " 5575 "or rid %d == 0.\n", rid); 5576 goto msi; 5577 } 5578 } 5579 5580 /* 5581 * bar == -1 => "trust me I know what I'm doing" 5582 * Some drivers are for hardware that is so shoddily 5583 * documented that no one knows which bars are which 5584 * so the developer has to map all bars. This hack 5585 * allows shoddy garbage to use msix in this framework. 5586 */ 5587 if (bar != -1) { 5588 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5589 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5590 if (ctx->ifc_msix_mem == NULL) { 5591 /* May not be enabled */ 5592 device_printf(dev, "Unable to map MSIX table \n"); 5593 goto msi; 5594 } 5595 } 5596 /* First try MSI/X */ 5597 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5598 device_printf(dev, "System has MSIX disabled \n"); 5599 bus_release_resource(dev, SYS_RES_MEMORY, 5600 bar, ctx->ifc_msix_mem); 5601 ctx->ifc_msix_mem = NULL; 5602 goto msi; 5603 } 5604 #if IFLIB_DEBUG 5605 /* use only 1 qset in debug mode */ 5606 queuemsgs = min(msgs - admincnt, 1); 5607 #else 5608 queuemsgs = msgs - admincnt; 5609 #endif 5610 #ifdef RSS 5611 queues = imin(queuemsgs, rss_getnumbuckets()); 5612 #else 5613 queues = queuemsgs; 5614 #endif 5615 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 5616 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 5617 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 5618 #ifdef RSS 5619 /* If we're doing RSS, clamp at the number of RSS buckets */ 5620 if (queues > rss_getnumbuckets()) 5621 queues = rss_getnumbuckets(); 5622 #endif 5623 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 5624 rx_queues = iflib_num_rx_queues; 5625 else 5626 rx_queues = queues; 5627 5628 if (rx_queues > scctx->isc_nrxqsets) 5629 rx_queues = scctx->isc_nrxqsets; 5630 5631 /* 5632 * We want this to be all logical CPUs by default 5633 */ 5634 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 5635 tx_queues = iflib_num_tx_queues; 5636 else 5637 tx_queues = mp_ncpus; 5638 5639 if (tx_queues > scctx->isc_ntxqsets) 5640 tx_queues = scctx->isc_ntxqsets; 5641 5642 if (ctx->ifc_sysctl_qs_eq_override == 0) { 5643 #ifdef INVARIANTS 5644 if (tx_queues != rx_queues) 5645 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 5646 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 5647 #endif 5648 tx_queues = min(rx_queues, tx_queues); 5649 rx_queues = min(rx_queues, tx_queues); 5650 } 5651 5652 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 5653 5654 vectors = rx_queues + admincnt; 5655 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 5656 device_printf(dev, 5657 "Using MSIX interrupts with %d vectors\n", vectors); 5658 scctx->isc_vectors = vectors; 5659 scctx->isc_nrxqsets = rx_queues; 5660 scctx->isc_ntxqsets = tx_queues; 5661 scctx->isc_intr = IFLIB_INTR_MSIX; 5662 5663 return (vectors); 5664 } else { 5665 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 5666 } 5667 msi: 5668 vectors = pci_msi_count(dev); 5669 scctx->isc_nrxqsets = 1; 5670 scctx->isc_ntxqsets = 1; 5671 scctx->isc_vectors = vectors; 5672 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 5673 device_printf(dev,"Using an MSI interrupt\n"); 5674 scctx->isc_intr = IFLIB_INTR_MSI; 5675 } else { 5676 device_printf(dev,"Using a Legacy interrupt\n"); 5677 scctx->isc_intr = IFLIB_INTR_LEGACY; 5678 } 5679 5680 return (vectors); 5681 } 5682 5683 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 5684 5685 static int 5686 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 5687 { 5688 int rc; 5689 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 5690 struct sbuf *sb; 5691 char *ring_state = "UNKNOWN"; 5692 5693 /* XXX needed ? */ 5694 rc = sysctl_wire_old_buffer(req, 0); 5695 MPASS(rc == 0); 5696 if (rc != 0) 5697 return (rc); 5698 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 5699 MPASS(sb != NULL); 5700 if (sb == NULL) 5701 return (ENOMEM); 5702 if (state[3] <= 3) 5703 ring_state = ring_states[state[3]]; 5704 5705 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 5706 state[0], state[1], state[2], ring_state); 5707 rc = sbuf_finish(sb); 5708 sbuf_delete(sb); 5709 return(rc); 5710 } 5711 5712 enum iflib_ndesc_handler { 5713 IFLIB_NTXD_HANDLER, 5714 IFLIB_NRXD_HANDLER, 5715 }; 5716 5717 static int 5718 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 5719 { 5720 if_ctx_t ctx = (void *)arg1; 5721 enum iflib_ndesc_handler type = arg2; 5722 char buf[256] = {0}; 5723 qidx_t *ndesc; 5724 char *p, *next; 5725 int nqs, rc, i; 5726 5727 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 5728 5729 nqs = 8; 5730 switch(type) { 5731 case IFLIB_NTXD_HANDLER: 5732 ndesc = ctx->ifc_sysctl_ntxds; 5733 if (ctx->ifc_sctx) 5734 nqs = ctx->ifc_sctx->isc_ntxqs; 5735 break; 5736 case IFLIB_NRXD_HANDLER: 5737 ndesc = ctx->ifc_sysctl_nrxds; 5738 if (ctx->ifc_sctx) 5739 nqs = ctx->ifc_sctx->isc_nrxqs; 5740 break; 5741 } 5742 if (nqs == 0) 5743 nqs = 8; 5744 5745 for (i=0; i<8; i++) { 5746 if (i >= nqs) 5747 break; 5748 if (i) 5749 strcat(buf, ","); 5750 sprintf(strchr(buf, 0), "%d", ndesc[i]); 5751 } 5752 5753 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 5754 if (rc || req->newptr == NULL) 5755 return rc; 5756 5757 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 5758 i++, p = strsep(&next, " ,")) { 5759 ndesc[i] = strtoul(p, NULL, 10); 5760 } 5761 5762 return(rc); 5763 } 5764 5765 #define NAME_BUFLEN 32 5766 static void 5767 iflib_add_device_sysctl_pre(if_ctx_t ctx) 5768 { 5769 device_t dev = iflib_get_dev(ctx); 5770 struct sysctl_oid_list *child, *oid_list; 5771 struct sysctl_ctx_list *ctx_list; 5772 struct sysctl_oid *node; 5773 5774 ctx_list = device_get_sysctl_ctx(dev); 5775 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 5776 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 5777 CTLFLAG_RD, NULL, "IFLIB fields"); 5778 oid_list = SYSCTL_CHILDREN(node); 5779 5780 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 5781 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 5782 "driver version"); 5783 5784 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 5785 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 5786 "# of txqs to use, 0 => use default #"); 5787 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 5788 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 5789 "# of rxqs to use, 0 => use default #"); 5790 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 5791 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 5792 "permit #txq != #rxq"); 5793 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 5794 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 5795 "disable MSIX (default 0)"); 5796 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 5797 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 5798 "set the rx budget"); 5799 5800 /* XXX change for per-queue sizes */ 5801 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 5802 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 5803 mp_ndesc_handler, "A", 5804 "list of # of tx descriptors to use, 0 = use default #"); 5805 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 5806 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 5807 mp_ndesc_handler, "A", 5808 "list of # of rx descriptors to use, 0 = use default #"); 5809 } 5810 5811 static void 5812 iflib_add_device_sysctl_post(if_ctx_t ctx) 5813 { 5814 if_shared_ctx_t sctx = ctx->ifc_sctx; 5815 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5816 device_t dev = iflib_get_dev(ctx); 5817 struct sysctl_oid_list *child; 5818 struct sysctl_ctx_list *ctx_list; 5819 iflib_fl_t fl; 5820 iflib_txq_t txq; 5821 iflib_rxq_t rxq; 5822 int i, j; 5823 char namebuf[NAME_BUFLEN]; 5824 char *qfmt; 5825 struct sysctl_oid *queue_node, *fl_node, *node; 5826 struct sysctl_oid_list *queue_list, *fl_list; 5827 ctx_list = device_get_sysctl_ctx(dev); 5828 5829 node = ctx->ifc_sysctl_node; 5830 child = SYSCTL_CHILDREN(node); 5831 5832 if (scctx->isc_ntxqsets > 100) 5833 qfmt = "txq%03d"; 5834 else if (scctx->isc_ntxqsets > 10) 5835 qfmt = "txq%02d"; 5836 else 5837 qfmt = "txq%d"; 5838 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 5839 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5840 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5841 CTLFLAG_RD, NULL, "Queue Name"); 5842 queue_list = SYSCTL_CHILDREN(queue_node); 5843 #if MEMORY_LOGGING 5844 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 5845 CTLFLAG_RD, 5846 &txq->ift_dequeued, "total mbufs freed"); 5847 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 5848 CTLFLAG_RD, 5849 &txq->ift_enqueued, "total mbufs enqueued"); 5850 #endif 5851 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 5852 CTLFLAG_RD, 5853 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 5854 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 5855 CTLFLAG_RD, 5856 &txq->ift_pullups, "# of times m_pullup was called"); 5857 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 5858 CTLFLAG_RD, 5859 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 5860 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 5861 CTLFLAG_RD, 5862 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 5863 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 5864 CTLFLAG_RD, 5865 &txq->ift_map_failed, "# of times dma map failed"); 5866 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 5867 CTLFLAG_RD, 5868 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 5869 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 5870 CTLFLAG_RD, 5871 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 5872 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 5873 CTLFLAG_RD, 5874 &txq->ift_pidx, 1, "Producer Index"); 5875 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 5876 CTLFLAG_RD, 5877 &txq->ift_cidx, 1, "Consumer Index"); 5878 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 5879 CTLFLAG_RD, 5880 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 5881 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 5882 CTLFLAG_RD, 5883 &txq->ift_in_use, 1, "descriptors in use"); 5884 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 5885 CTLFLAG_RD, 5886 &txq->ift_processed, "descriptors procesed for clean"); 5887 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 5888 CTLFLAG_RD, 5889 &txq->ift_cleaned, "total cleaned"); 5890 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 5891 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 5892 0, mp_ring_state_handler, "A", "soft ring state"); 5893 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 5894 CTLFLAG_RD, &txq->ift_br->enqueues, 5895 "# of enqueues to the mp_ring for this queue"); 5896 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 5897 CTLFLAG_RD, &txq->ift_br->drops, 5898 "# of drops in the mp_ring for this queue"); 5899 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 5900 CTLFLAG_RD, &txq->ift_br->starts, 5901 "# of normal consumer starts in the mp_ring for this queue"); 5902 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 5903 CTLFLAG_RD, &txq->ift_br->stalls, 5904 "# of consumer stalls in the mp_ring for this queue"); 5905 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 5906 CTLFLAG_RD, &txq->ift_br->restarts, 5907 "# of consumer restarts in the mp_ring for this queue"); 5908 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 5909 CTLFLAG_RD, &txq->ift_br->abdications, 5910 "# of consumer abdications in the mp_ring for this queue"); 5911 } 5912 5913 if (scctx->isc_nrxqsets > 100) 5914 qfmt = "rxq%03d"; 5915 else if (scctx->isc_nrxqsets > 10) 5916 qfmt = "rxq%02d"; 5917 else 5918 qfmt = "rxq%d"; 5919 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 5920 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5921 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5922 CTLFLAG_RD, NULL, "Queue Name"); 5923 queue_list = SYSCTL_CHILDREN(queue_node); 5924 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5925 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 5926 CTLFLAG_RD, 5927 &rxq->ifr_cq_pidx, 1, "Producer Index"); 5928 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 5929 CTLFLAG_RD, 5930 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 5931 } 5932 5933 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 5934 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 5935 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 5936 CTLFLAG_RD, NULL, "freelist Name"); 5937 fl_list = SYSCTL_CHILDREN(fl_node); 5938 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 5939 CTLFLAG_RD, 5940 &fl->ifl_pidx, 1, "Producer Index"); 5941 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 5942 CTLFLAG_RD, 5943 &fl->ifl_cidx, 1, "Consumer Index"); 5944 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 5945 CTLFLAG_RD, 5946 &fl->ifl_credits, 1, "credits available"); 5947 #if MEMORY_LOGGING 5948 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 5949 CTLFLAG_RD, 5950 &fl->ifl_m_enqueued, "mbufs allocated"); 5951 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 5952 CTLFLAG_RD, 5953 &fl->ifl_m_dequeued, "mbufs freed"); 5954 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 5955 CTLFLAG_RD, 5956 &fl->ifl_cl_enqueued, "clusters allocated"); 5957 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 5958 CTLFLAG_RD, 5959 &fl->ifl_cl_dequeued, "clusters freed"); 5960 #endif 5961 5962 } 5963 } 5964 5965 } 5966 5967 #ifndef __NO_STRICT_ALIGNMENT 5968 static struct mbuf * 5969 iflib_fixup_rx(struct mbuf *m) 5970 { 5971 struct mbuf *n; 5972 5973 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 5974 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 5975 m->m_data += ETHER_HDR_LEN; 5976 n = m; 5977 } else { 5978 MGETHDR(n, M_NOWAIT, MT_DATA); 5979 if (n == NULL) { 5980 m_freem(m); 5981 return (NULL); 5982 } 5983 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 5984 m->m_data += ETHER_HDR_LEN; 5985 m->m_len -= ETHER_HDR_LEN; 5986 n->m_len = ETHER_HDR_LEN; 5987 M_MOVE_PKTHDR(n, m); 5988 n->m_next = m; 5989 } 5990 return (n); 5991 } 5992 #endif 5993