1 /*- 2 * Copyright (c) 2014-2017, Matthew Macy <mmacy@nextbsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 35 #include <sys/param.h> 36 #include <sys/types.h> 37 #include <sys/bus.h> 38 #include <sys/eventhandler.h> 39 #include <sys/sockio.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sysctl.h> 50 #include <sys/syslog.h> 51 #include <sys/taskqueue.h> 52 #include <sys/limits.h> 53 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 63 #include <netinet/in.h> 64 #include <netinet/in_pcb.h> 65 #include <netinet/tcp_lro.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/if_ether.h> 68 #include <netinet/ip.h> 69 #include <netinet/ip6.h> 70 #include <netinet/tcp.h> 71 72 #include <machine/bus.h> 73 #include <machine/in_cksum.h> 74 75 #include <vm/vm.h> 76 #include <vm/pmap.h> 77 78 #include <dev/led/led.h> 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pci_private.h> 82 83 #include <net/iflib.h> 84 85 #include "ifdi_if.h" 86 87 #if defined(__i386__) || defined(__amd64__) 88 #include <sys/memdesc.h> 89 #include <machine/bus.h> 90 #include <machine/md_var.h> 91 #include <machine/specialreg.h> 92 #include <x86/include/busdma_impl.h> 93 #include <x86/iommu/busdma_dmar.h> 94 #endif 95 96 /* 97 * enable accounting of every mbuf as it comes in to and goes out of 98 * iflib's software descriptor references 99 */ 100 #define MEMORY_LOGGING 0 101 /* 102 * Enable mbuf vectors for compressing long mbuf chains 103 */ 104 105 /* 106 * NB: 107 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 108 * we prefetch needs to be determined by the time spent in m_free vis a vis 109 * the cost of a prefetch. This will of course vary based on the workload: 110 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 111 * is quite expensive, thus suggesting very little prefetch. 112 * - small packet forwarding which is just returning a single mbuf to 113 * UMA will typically be very fast vis a vis the cost of a memory 114 * access. 115 */ 116 117 118 /* 119 * File organization: 120 * - private structures 121 * - iflib private utility functions 122 * - ifnet functions 123 * - vlan registry and other exported functions 124 * - iflib public core functions 125 * 126 * 127 */ 128 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 129 130 struct iflib_txq; 131 typedef struct iflib_txq *iflib_txq_t; 132 struct iflib_rxq; 133 typedef struct iflib_rxq *iflib_rxq_t; 134 struct iflib_fl; 135 typedef struct iflib_fl *iflib_fl_t; 136 137 struct iflib_ctx; 138 139 typedef struct iflib_filter_info { 140 driver_filter_t *ifi_filter; 141 void *ifi_filter_arg; 142 struct grouptask *ifi_task; 143 void *ifi_ctx; 144 } *iflib_filter_info_t; 145 146 struct iflib_ctx { 147 KOBJ_FIELDS; 148 /* 149 * Pointer to hardware driver's softc 150 */ 151 void *ifc_softc; 152 device_t ifc_dev; 153 if_t ifc_ifp; 154 155 cpuset_t ifc_cpus; 156 if_shared_ctx_t ifc_sctx; 157 struct if_softc_ctx ifc_softc_ctx; 158 159 struct mtx ifc_mtx; 160 161 uint16_t ifc_nhwtxqs; 162 uint16_t ifc_nhwrxqs; 163 164 iflib_txq_t ifc_txqs; 165 iflib_rxq_t ifc_rxqs; 166 uint32_t ifc_if_flags; 167 uint32_t ifc_flags; 168 uint32_t ifc_max_fl_buf_size; 169 int ifc_in_detach; 170 171 int ifc_link_state; 172 int ifc_link_irq; 173 int ifc_watchdog_events; 174 struct cdev *ifc_led_dev; 175 struct resource *ifc_msix_mem; 176 177 struct if_irq ifc_legacy_irq; 178 struct grouptask ifc_admin_task; 179 struct grouptask ifc_vflr_task; 180 struct iflib_filter_info ifc_filter_info; 181 struct ifmedia ifc_media; 182 183 struct sysctl_oid *ifc_sysctl_node; 184 uint16_t ifc_sysctl_ntxqs; 185 uint16_t ifc_sysctl_nrxqs; 186 uint16_t ifc_sysctl_qs_eq_override; 187 188 qidx_t ifc_sysctl_ntxds[8]; 189 qidx_t ifc_sysctl_nrxds[8]; 190 struct if_txrx ifc_txrx; 191 #define isc_txd_encap ifc_txrx.ift_txd_encap 192 #define isc_txd_flush ifc_txrx.ift_txd_flush 193 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 194 #define isc_rxd_available ifc_txrx.ift_rxd_available 195 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 196 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 197 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 198 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 199 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 200 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 201 eventhandler_tag ifc_vlan_attach_event; 202 eventhandler_tag ifc_vlan_detach_event; 203 uint8_t ifc_mac[ETHER_ADDR_LEN]; 204 char ifc_mtx_name[16]; 205 }; 206 207 208 void * 209 iflib_get_softc(if_ctx_t ctx) 210 { 211 212 return (ctx->ifc_softc); 213 } 214 215 device_t 216 iflib_get_dev(if_ctx_t ctx) 217 { 218 219 return (ctx->ifc_dev); 220 } 221 222 if_t 223 iflib_get_ifp(if_ctx_t ctx) 224 { 225 226 return (ctx->ifc_ifp); 227 } 228 229 struct ifmedia * 230 iflib_get_media(if_ctx_t ctx) 231 { 232 233 return (&ctx->ifc_media); 234 } 235 236 void 237 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 238 { 239 240 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 241 } 242 243 if_softc_ctx_t 244 iflib_get_softc_ctx(if_ctx_t ctx) 245 { 246 247 return (&ctx->ifc_softc_ctx); 248 } 249 250 if_shared_ctx_t 251 iflib_get_sctx(if_ctx_t ctx) 252 { 253 254 return (ctx->ifc_sctx); 255 } 256 257 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 258 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 259 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 260 261 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 262 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 263 264 #define RX_SW_DESC_MAP_CREATED (1 << 0) 265 #define TX_SW_DESC_MAP_CREATED (1 << 1) 266 #define RX_SW_DESC_INUSE (1 << 3) 267 #define TX_SW_DESC_MAPPED (1 << 4) 268 269 typedef struct iflib_sw_rx_desc_array { 270 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 271 struct mbuf **ifsd_m; /* pkthdr mbufs */ 272 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 273 uint8_t *ifsd_flags; 274 } iflib_rxsd_array_t; 275 276 typedef struct iflib_sw_tx_desc_array { 277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 278 struct mbuf **ifsd_m; /* pkthdr mbufs */ 279 uint8_t *ifsd_flags; 280 } if_txsd_vec_t; 281 282 283 /* magic number that should be high enough for any hardware */ 284 #define IFLIB_MAX_TX_SEGS 128 285 #define IFLIB_MAX_RX_SEGS 32 286 #define IFLIB_RX_COPY_THRESH 128 287 #define IFLIB_MAX_RX_REFRESH 32 288 /* The minimum descriptors per second before we start coalescing */ 289 #define IFLIB_MIN_DESC_SEC 16384 290 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 291 #define IFLIB_QUEUE_IDLE 0 292 #define IFLIB_QUEUE_HUNG 1 293 #define IFLIB_QUEUE_WORKING 2 294 /* maximum number of txqs that can share an rx interrupt */ 295 #define IFLIB_MAX_TX_SHARED_INTR 4 296 297 /* this should really scale with ring size - this is a fairly arbitrary value */ 298 #define TX_BATCH_SIZE 32 299 300 #define IFLIB_RESTART_BUDGET 8 301 302 #define IFC_LEGACY 0x001 303 #define IFC_QFLUSH 0x002 304 #define IFC_MULTISEG 0x004 305 #define IFC_DMAR 0x008 306 #define IFC_SC_ALLOCATED 0x010 307 #define IFC_INIT_DONE 0x020 308 #define IFC_PREFETCH 0x040 309 #define IFC_DO_RESET 0x080 310 #define IFC_CHECK_HUNG 0x100 311 312 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 313 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 314 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 315 struct iflib_txq { 316 qidx_t ift_in_use; 317 qidx_t ift_cidx; 318 qidx_t ift_cidx_processed; 319 qidx_t ift_pidx; 320 uint8_t ift_gen; 321 uint8_t ift_br_offset; 322 uint16_t ift_npending; 323 uint16_t ift_db_pending; 324 uint16_t ift_rs_pending; 325 /* implicit pad */ 326 uint8_t ift_txd_size[8]; 327 uint64_t ift_processed; 328 uint64_t ift_cleaned; 329 uint64_t ift_cleaned_prev; 330 #if MEMORY_LOGGING 331 uint64_t ift_enqueued; 332 uint64_t ift_dequeued; 333 #endif 334 uint64_t ift_no_tx_dma_setup; 335 uint64_t ift_no_desc_avail; 336 uint64_t ift_mbuf_defrag_failed; 337 uint64_t ift_mbuf_defrag; 338 uint64_t ift_map_failed; 339 uint64_t ift_txd_encap_efbig; 340 uint64_t ift_pullups; 341 342 struct mtx ift_mtx; 343 struct mtx ift_db_mtx; 344 345 /* constant values */ 346 if_ctx_t ift_ctx; 347 struct ifmp_ring *ift_br; 348 struct grouptask ift_task; 349 qidx_t ift_size; 350 uint16_t ift_id; 351 struct callout ift_timer; 352 353 if_txsd_vec_t ift_sds; 354 uint8_t ift_qstatus; 355 uint8_t ift_closed; 356 uint8_t ift_update_freq; 357 struct iflib_filter_info ift_filter_info; 358 bus_dma_tag_t ift_desc_tag; 359 bus_dma_tag_t ift_tso_desc_tag; 360 iflib_dma_info_t ift_ifdi; 361 #define MTX_NAME_LEN 16 362 char ift_mtx_name[MTX_NAME_LEN]; 363 char ift_db_mtx_name[MTX_NAME_LEN]; 364 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 365 #ifdef IFLIB_DIAGNOSTICS 366 uint64_t ift_cpu_exec_count[256]; 367 #endif 368 } __aligned(CACHE_LINE_SIZE); 369 370 struct iflib_fl { 371 qidx_t ifl_cidx; 372 qidx_t ifl_pidx; 373 qidx_t ifl_credits; 374 uint8_t ifl_gen; 375 uint8_t ifl_rxd_size; 376 #if MEMORY_LOGGING 377 uint64_t ifl_m_enqueued; 378 uint64_t ifl_m_dequeued; 379 uint64_t ifl_cl_enqueued; 380 uint64_t ifl_cl_dequeued; 381 #endif 382 /* implicit pad */ 383 384 /* constant */ 385 qidx_t ifl_size; 386 uint16_t ifl_buf_size; 387 uint16_t ifl_cltype; 388 uma_zone_t ifl_zone; 389 iflib_rxsd_array_t ifl_sds; 390 iflib_rxq_t ifl_rxq; 391 uint8_t ifl_id; 392 bus_dma_tag_t ifl_desc_tag; 393 iflib_dma_info_t ifl_ifdi; 394 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 395 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 396 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 397 } __aligned(CACHE_LINE_SIZE); 398 399 static inline qidx_t 400 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 401 { 402 qidx_t used; 403 404 if (pidx > cidx) 405 used = pidx - cidx; 406 else if (pidx < cidx) 407 used = size - cidx + pidx; 408 else if (gen == 0 && pidx == cidx) 409 used = 0; 410 else if (gen == 1 && pidx == cidx) 411 used = size; 412 else 413 panic("bad state"); 414 415 return (used); 416 } 417 418 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 419 420 #define IDXDIFF(head, tail, wrap) \ 421 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 422 423 struct iflib_rxq { 424 /* If there is a separate completion queue - 425 * these are the cq cidx and pidx. Otherwise 426 * these are unused. 427 */ 428 qidx_t ifr_size; 429 qidx_t ifr_cq_cidx; 430 qidx_t ifr_cq_pidx; 431 uint8_t ifr_cq_gen; 432 uint8_t ifr_fl_offset; 433 434 if_ctx_t ifr_ctx; 435 iflib_fl_t ifr_fl; 436 uint64_t ifr_rx_irq; 437 uint16_t ifr_id; 438 uint8_t ifr_lro_enabled; 439 uint8_t ifr_nfl; 440 uint8_t ifr_ntxqirq; 441 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 442 struct lro_ctrl ifr_lc; 443 struct grouptask ifr_task; 444 struct iflib_filter_info ifr_filter_info; 445 iflib_dma_info_t ifr_ifdi; 446 447 /* dynamically allocate if any drivers need a value substantially larger than this */ 448 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 449 #ifdef IFLIB_DIAGNOSTICS 450 uint64_t ifr_cpu_exec_count[256]; 451 #endif 452 } __aligned(CACHE_LINE_SIZE); 453 454 typedef struct if_rxsd { 455 caddr_t *ifsd_cl; 456 struct mbuf **ifsd_m; 457 iflib_fl_t ifsd_fl; 458 qidx_t ifsd_cidx; 459 } *if_rxsd_t; 460 461 /* multiple of word size */ 462 #ifdef __LP64__ 463 #define PKT_INFO_SIZE 6 464 #define RXD_INFO_SIZE 5 465 #define PKT_TYPE uint64_t 466 #else 467 #define PKT_INFO_SIZE 11 468 #define RXD_INFO_SIZE 8 469 #define PKT_TYPE uint32_t 470 #endif 471 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 472 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 473 474 typedef struct if_pkt_info_pad { 475 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 476 } *if_pkt_info_pad_t; 477 typedef struct if_rxd_info_pad { 478 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 479 } *if_rxd_info_pad_t; 480 481 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 482 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 483 484 485 static inline void 486 pkt_info_zero(if_pkt_info_t pi) 487 { 488 if_pkt_info_pad_t pi_pad; 489 490 pi_pad = (if_pkt_info_pad_t)pi; 491 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 492 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 493 #ifndef __LP64__ 494 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 495 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 496 #endif 497 } 498 499 static inline void 500 rxd_info_zero(if_rxd_info_t ri) 501 { 502 if_rxd_info_pad_t ri_pad; 503 int i; 504 505 ri_pad = (if_rxd_info_pad_t)ri; 506 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 507 ri_pad->rxd_val[i] = 0; 508 ri_pad->rxd_val[i+1] = 0; 509 ri_pad->rxd_val[i+2] = 0; 510 ri_pad->rxd_val[i+3] = 0; 511 } 512 #ifdef __LP64__ 513 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 514 #endif 515 } 516 517 /* 518 * Only allow a single packet to take up most 1/nth of the tx ring 519 */ 520 #define MAX_SINGLE_PACKET_FRACTION 12 521 #define IF_BAD_DMA (bus_addr_t)-1 522 523 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 524 525 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF) 526 527 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx) 528 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx) 529 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx) 530 531 532 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 533 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 534 535 536 /* Our boot-time initialization hook */ 537 static int iflib_module_event_handler(module_t, int, void *); 538 539 static moduledata_t iflib_moduledata = { 540 "iflib", 541 iflib_module_event_handler, 542 NULL 543 }; 544 545 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 546 MODULE_VERSION(iflib, 1); 547 548 MODULE_DEPEND(iflib, pci, 1, 1, 1); 549 MODULE_DEPEND(iflib, ether, 1, 1, 1); 550 551 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 552 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 553 554 #ifndef IFLIB_DEBUG_COUNTERS 555 #ifdef INVARIANTS 556 #define IFLIB_DEBUG_COUNTERS 1 557 #else 558 #define IFLIB_DEBUG_COUNTERS 0 559 #endif /* !INVARIANTS */ 560 #endif 561 562 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 563 "iflib driver parameters"); 564 565 /* 566 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 567 */ 568 static int iflib_min_tx_latency = 0; 569 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 570 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 571 static int iflib_no_tx_batch = 0; 572 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 573 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 574 575 576 #if IFLIB_DEBUG_COUNTERS 577 578 static int iflib_tx_seen; 579 static int iflib_tx_sent; 580 static int iflib_tx_encap; 581 static int iflib_rx_allocs; 582 static int iflib_fl_refills; 583 static int iflib_fl_refills_large; 584 static int iflib_tx_frees; 585 586 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 587 &iflib_tx_seen, 0, "# tx mbufs seen"); 588 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 589 &iflib_tx_sent, 0, "# tx mbufs sent"); 590 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 591 &iflib_tx_encap, 0, "# tx mbufs encapped"); 592 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 593 &iflib_tx_frees, 0, "# tx frees"); 594 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 595 &iflib_rx_allocs, 0, "# rx allocations"); 596 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 597 &iflib_fl_refills, 0, "# refills"); 598 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 599 &iflib_fl_refills_large, 0, "# large refills"); 600 601 602 static int iflib_txq_drain_flushing; 603 static int iflib_txq_drain_oactive; 604 static int iflib_txq_drain_notready; 605 static int iflib_txq_drain_encapfail; 606 607 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 608 &iflib_txq_drain_flushing, 0, "# drain flushes"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 610 &iflib_txq_drain_oactive, 0, "# drain oactives"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 612 &iflib_txq_drain_notready, 0, "# drain notready"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 614 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 615 616 617 static int iflib_encap_load_mbuf_fail; 618 static int iflib_encap_txq_avail_fail; 619 static int iflib_encap_txd_encap_fail; 620 621 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 622 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 623 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 624 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 625 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 626 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 627 628 static int iflib_task_fn_rxs; 629 static int iflib_rx_intr_enables; 630 static int iflib_fast_intrs; 631 static int iflib_intr_link; 632 static int iflib_intr_msix; 633 static int iflib_rx_unavail; 634 static int iflib_rx_ctx_inactive; 635 static int iflib_rx_zero_len; 636 static int iflib_rx_if_input; 637 static int iflib_rx_mbuf_null; 638 static int iflib_rxd_flush; 639 640 static int iflib_verbose_debug; 641 642 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 643 &iflib_intr_link, 0, "# intr link calls"); 644 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 645 &iflib_intr_msix, 0, "# intr msix calls"); 646 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 647 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 648 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 649 &iflib_rx_intr_enables, 0, "# rx intr enables"); 650 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 651 &iflib_fast_intrs, 0, "# fast_intr calls"); 652 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 653 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 654 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 655 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 657 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 659 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 661 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 663 &iflib_rxd_flush, 0, "# times rxd_flush called"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 665 &iflib_verbose_debug, 0, "enable verbose debugging"); 666 667 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 668 static void 669 iflib_debug_reset(void) 670 { 671 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 672 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 673 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 674 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 675 iflib_encap_load_mbuf_fail = iflib_encap_txq_avail_fail = 676 iflib_encap_txd_encap_fail = iflib_task_fn_rxs = iflib_rx_intr_enables = 677 iflib_fast_intrs = iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 678 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 679 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 680 } 681 682 #else 683 #define DBG_COUNTER_INC(name) 684 static void iflib_debug_reset(void) {} 685 #endif 686 687 688 689 #define IFLIB_DEBUG 0 690 691 static void iflib_tx_structures_free(if_ctx_t ctx); 692 static void iflib_rx_structures_free(if_ctx_t ctx); 693 static int iflib_queues_alloc(if_ctx_t ctx); 694 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 695 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 696 static int iflib_qset_structures_setup(if_ctx_t ctx); 697 static int iflib_msix_init(if_ctx_t ctx); 698 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str); 699 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 700 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 701 static int iflib_register(if_ctx_t); 702 static void iflib_init_locked(if_ctx_t ctx); 703 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 704 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 705 static void iflib_ifmp_purge(iflib_txq_t txq); 706 static void _iflib_pre_assert(if_softc_ctx_t scctx); 707 static void iflib_stop(if_ctx_t ctx); 708 static void iflib_if_init_locked(if_ctx_t ctx); 709 #ifndef __NO_STRICT_ALIGNMENT 710 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 711 #endif 712 713 #ifdef DEV_NETMAP 714 #include <sys/selinfo.h> 715 #include <net/netmap.h> 716 #include <dev/netmap/netmap_kern.h> 717 718 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 719 720 /* 721 * device-specific sysctl variables: 722 * 723 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 724 * During regular operations the CRC is stripped, but on some 725 * hardware reception of frames not multiple of 64 is slower, 726 * so using crcstrip=0 helps in benchmarks. 727 * 728 * iflib_rx_miss, iflib_rx_miss_bufs: 729 * count packets that might be missed due to lost interrupts. 730 */ 731 SYSCTL_DECL(_dev_netmap); 732 /* 733 * The xl driver by default strips CRCs and we do not override it. 734 */ 735 736 int iflib_crcstrip = 1; 737 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 738 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 739 740 int iflib_rx_miss, iflib_rx_miss_bufs; 741 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 742 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 743 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 744 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 745 746 /* 747 * Register/unregister. We are already under netmap lock. 748 * Only called on the first register or the last unregister. 749 */ 750 static int 751 iflib_netmap_register(struct netmap_adapter *na, int onoff) 752 { 753 struct ifnet *ifp = na->ifp; 754 if_ctx_t ctx = ifp->if_softc; 755 int status; 756 757 CTX_LOCK(ctx); 758 IFDI_INTR_DISABLE(ctx); 759 760 /* Tell the stack that the interface is no longer active */ 761 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 762 763 if (!CTX_IS_VF(ctx)) 764 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 765 766 /* enable or disable flags and callbacks in na and ifp */ 767 if (onoff) { 768 nm_set_native_flags(na); 769 } else { 770 nm_clear_native_flags(na); 771 } 772 iflib_stop(ctx); 773 iflib_init_locked(ctx); 774 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 775 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 776 if (status) 777 nm_clear_native_flags(na); 778 CTX_UNLOCK(ctx); 779 return (status); 780 } 781 782 /* 783 * Reconcile kernel and user view of the transmit ring. 784 * 785 * All information is in the kring. 786 * Userspace wants to send packets up to the one before kring->rhead, 787 * kernel knows kring->nr_hwcur is the first unsent packet. 788 * 789 * Here we push packets out (as many as possible), and possibly 790 * reclaim buffers from previously completed transmission. 791 * 792 * The caller (netmap) guarantees that there is only one instance 793 * running at any time. Any interference with other driver 794 * methods should be handled by the individual drivers. 795 */ 796 static int 797 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 798 { 799 struct netmap_adapter *na = kring->na; 800 struct ifnet *ifp = na->ifp; 801 struct netmap_ring *ring = kring->ring; 802 u_int nm_i; /* index into the netmap ring */ 803 u_int nic_i; /* index into the NIC ring */ 804 u_int n; 805 u_int const lim = kring->nkr_num_slots - 1; 806 u_int const head = kring->rhead; 807 struct if_pkt_info pi; 808 809 /* 810 * interrupts on every tx packet are expensive so request 811 * them every half ring, or where NS_REPORT is set 812 */ 813 u_int report_frequency = kring->nkr_num_slots >> 1; 814 /* device-specific */ 815 if_ctx_t ctx = ifp->if_softc; 816 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 817 818 if (txq->ift_sds.ifsd_map) 819 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 820 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 821 822 823 /* 824 * First part: process new packets to send. 825 * nm_i is the current index in the netmap ring, 826 * nic_i is the corresponding index in the NIC ring. 827 * 828 * If we have packets to send (nm_i != head) 829 * iterate over the netmap ring, fetch length and update 830 * the corresponding slot in the NIC ring. Some drivers also 831 * need to update the buffer's physical address in the NIC slot 832 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 833 * 834 * The netmap_reload_map() calls is especially expensive, 835 * even when (as in this case) the tag is 0, so do only 836 * when the buffer has actually changed. 837 * 838 * If possible do not set the report/intr bit on all slots, 839 * but only a few times per ring or when NS_REPORT is set. 840 * 841 * Finally, on 10G and faster drivers, it might be useful 842 * to prefetch the next slot and txr entry. 843 */ 844 845 nm_i = kring->nr_hwcur; 846 pkt_info_zero(&pi); 847 pi.ipi_segs = txq->ift_segs; 848 pi.ipi_qsidx = kring->ring_id; 849 if (nm_i != head) { /* we have new packets to send */ 850 nic_i = netmap_idx_k2n(kring, nm_i); 851 852 __builtin_prefetch(&ring->slot[nm_i]); 853 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 854 if (txq->ift_sds.ifsd_map) 855 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 856 857 for (n = 0; nm_i != head; n++) { 858 struct netmap_slot *slot = &ring->slot[nm_i]; 859 u_int len = slot->len; 860 uint64_t paddr; 861 void *addr = PNMB(na, slot, &paddr); 862 int flags = (slot->flags & NS_REPORT || 863 nic_i == 0 || nic_i == report_frequency) ? 864 IPI_TX_INTR : 0; 865 866 /* device-specific */ 867 pi.ipi_len = len; 868 pi.ipi_segs[0].ds_addr = paddr; 869 pi.ipi_segs[0].ds_len = len; 870 pi.ipi_nsegs = 1; 871 pi.ipi_ndescs = 0; 872 pi.ipi_pidx = nic_i; 873 pi.ipi_flags = flags; 874 875 /* Fill the slot in the NIC ring. */ 876 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 877 878 /* prefetch for next round */ 879 __builtin_prefetch(&ring->slot[nm_i + 1]); 880 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 881 if (txq->ift_sds.ifsd_map) { 882 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 883 884 NM_CHECK_ADDR_LEN(na, addr, len); 885 886 if (slot->flags & NS_BUF_CHANGED) { 887 /* buffer has changed, reload map */ 888 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 889 } 890 /* make sure changes to the buffer are synced */ 891 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 892 BUS_DMASYNC_PREWRITE); 893 } 894 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 895 nm_i = nm_next(nm_i, lim); 896 nic_i = nm_next(nic_i, lim); 897 } 898 kring->nr_hwcur = head; 899 900 /* synchronize the NIC ring */ 901 if (txq->ift_sds.ifsd_map) 902 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 903 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 904 905 /* (re)start the tx unit up to slot nic_i (excluded) */ 906 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 907 } 908 909 /* 910 * Second part: reclaim buffers for completed transmissions. 911 */ 912 if (iflib_tx_credits_update(ctx, txq)) { 913 /* some tx completed, increment avail */ 914 nic_i = txq->ift_cidx_processed; 915 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 916 } 917 return (0); 918 } 919 920 /* 921 * Reconcile kernel and user view of the receive ring. 922 * Same as for the txsync, this routine must be efficient. 923 * The caller guarantees a single invocations, but races against 924 * the rest of the driver should be handled here. 925 * 926 * On call, kring->rhead is the first packet that userspace wants 927 * to keep, and kring->rcur is the wakeup point. 928 * The kernel has previously reported packets up to kring->rtail. 929 * 930 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 931 * of whether or not we received an interrupt. 932 */ 933 static int 934 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 935 { 936 struct netmap_adapter *na = kring->na; 937 struct netmap_ring *ring = kring->ring; 938 uint32_t nm_i; /* index into the netmap ring */ 939 uint32_t nic_i, nic_i_start; /* index into the NIC ring */ 940 u_int i, n; 941 u_int const lim = kring->nkr_num_slots - 1; 942 u_int const head = kring->rhead; 943 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 944 struct if_rxd_info ri; 945 struct if_rxd_update iru; 946 947 struct ifnet *ifp = na->ifp; 948 if_ctx_t ctx = ifp->if_softc; 949 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 950 iflib_fl_t fl = rxq->ifr_fl; 951 if (head > lim) 952 return netmap_ring_reinit(kring); 953 954 /* XXX check sync modes */ 955 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 956 if (fl->ifl_sds.ifsd_map == NULL) 957 continue; 958 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 959 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 960 } 961 /* 962 * First part: import newly received packets. 963 * 964 * nm_i is the index of the next free slot in the netmap ring, 965 * nic_i is the index of the next received packet in the NIC ring, 966 * and they may differ in case if_init() has been called while 967 * in netmap mode. For the receive ring we have 968 * 969 * nic_i = rxr->next_check; 970 * nm_i = kring->nr_hwtail (previous) 971 * and 972 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 973 * 974 * rxr->next_check is set to 0 on a ring reinit 975 */ 976 if (netmap_no_pendintr || force_update) { 977 int crclen = iflib_crcstrip ? 0 : 4; 978 int error, avail; 979 uint16_t slot_flags = kring->nkr_slot_flags; 980 981 for (fl = rxq->ifr_fl, i = 0; i < rxq->ifr_nfl; i++, fl++) { 982 nic_i = fl->ifl_cidx; 983 nm_i = netmap_idx_n2k(kring, nic_i); 984 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 985 for (n = 0; avail > 0; n++, avail--) { 986 rxd_info_zero(&ri); 987 ri.iri_frags = rxq->ifr_frags; 988 ri.iri_qsidx = kring->ring_id; 989 ri.iri_ifp = ctx->ifc_ifp; 990 ri.iri_cidx = nic_i; 991 992 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 993 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 994 ring->slot[nm_i].flags = slot_flags; 995 if (fl->ifl_sds.ifsd_map) 996 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 997 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 998 nm_i = nm_next(nm_i, lim); 999 nic_i = nm_next(nic_i, lim); 1000 } 1001 if (n) { /* update the state variables */ 1002 if (netmap_no_pendintr && !force_update) { 1003 /* diagnostics */ 1004 iflib_rx_miss ++; 1005 iflib_rx_miss_bufs += n; 1006 } 1007 fl->ifl_cidx = nic_i; 1008 kring->nr_hwtail = nm_i; 1009 } 1010 kring->nr_kflags &= ~NKR_PENDINTR; 1011 } 1012 } 1013 /* 1014 * Second part: skip past packets that userspace has released. 1015 * (kring->nr_hwcur to head excluded), 1016 * and make the buffers available for reception. 1017 * As usual nm_i is the index in the netmap ring, 1018 * nic_i is the index in the NIC ring, and 1019 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1020 */ 1021 /* XXX not sure how this will work with multiple free lists */ 1022 nm_i = kring->nr_hwcur; 1023 if (nm_i == head) 1024 return (0); 1025 1026 iru.iru_paddrs = fl->ifl_bus_addrs; 1027 iru.iru_vaddrs = &fl->ifl_vm_addrs[0]; 1028 iru.iru_idxs = fl->ifl_rxd_idxs; 1029 iru.iru_qsidx = rxq->ifr_id; 1030 iru.iru_buf_size = fl->ifl_buf_size; 1031 iru.iru_flidx = fl->ifl_id; 1032 nic_i_start = nic_i = netmap_idx_k2n(kring, nm_i); 1033 for (i = 0; nm_i != head; i++) { 1034 struct netmap_slot *slot = &ring->slot[nm_i]; 1035 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]); 1036 1037 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 1038 goto ring_reset; 1039 1040 fl->ifl_vm_addrs[i] = addr; 1041 if (fl->ifl_sds.ifsd_map && (slot->flags & NS_BUF_CHANGED)) { 1042 /* buffer has changed, reload map */ 1043 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i], addr); 1044 } 1045 slot->flags &= ~NS_BUF_CHANGED; 1046 1047 nm_i = nm_next(nm_i, lim); 1048 fl->ifl_rxd_idxs[i] = nic_i = nm_next(nic_i, lim); 1049 if (nm_i != head && i < IFLIB_MAX_RX_REFRESH) 1050 continue; 1051 1052 iru.iru_pidx = nic_i_start; 1053 iru.iru_count = i; 1054 i = 0; 1055 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1056 if (fl->ifl_sds.ifsd_map == NULL) { 1057 nic_i_start = nic_i; 1058 continue; 1059 } 1060 nic_i = nic_i_start; 1061 for (n = 0; n < iru.iru_count; n++) { 1062 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i], 1063 BUS_DMASYNC_PREREAD); 1064 nic_i = nm_next(nic_i, lim); 1065 } 1066 nic_i_start = nic_i; 1067 } 1068 kring->nr_hwcur = head; 1069 1070 if (fl->ifl_sds.ifsd_map) 1071 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1072 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1073 /* 1074 * IMPORTANT: we must leave one free slot in the ring, 1075 * so move nic_i back by one unit 1076 */ 1077 nic_i = nm_prev(nic_i, lim); 1078 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 1079 return 0; 1080 1081 ring_reset: 1082 return netmap_ring_reinit(kring); 1083 } 1084 1085 static void 1086 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1087 { 1088 struct ifnet *ifp = na->ifp; 1089 if_ctx_t ctx = ifp->if_softc; 1090 1091 CTX_LOCK(ctx); 1092 if (onoff) { 1093 IFDI_INTR_ENABLE(ctx); 1094 } else { 1095 IFDI_INTR_DISABLE(ctx); 1096 } 1097 CTX_UNLOCK(ctx); 1098 } 1099 1100 1101 static int 1102 iflib_netmap_attach(if_ctx_t ctx) 1103 { 1104 struct netmap_adapter na; 1105 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1106 1107 bzero(&na, sizeof(na)); 1108 1109 na.ifp = ctx->ifc_ifp; 1110 na.na_flags = NAF_BDG_MAYSLEEP; 1111 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1112 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1113 1114 na.num_tx_desc = scctx->isc_ntxd[0]; 1115 na.num_rx_desc = scctx->isc_nrxd[0]; 1116 na.nm_txsync = iflib_netmap_txsync; 1117 na.nm_rxsync = iflib_netmap_rxsync; 1118 na.nm_register = iflib_netmap_register; 1119 na.nm_intr = iflib_netmap_intr; 1120 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1121 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1122 return (netmap_attach(&na)); 1123 } 1124 1125 static void 1126 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1127 { 1128 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1129 struct netmap_slot *slot; 1130 1131 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1132 if (slot == NULL) 1133 return; 1134 if (txq->ift_sds.ifsd_map == NULL) 1135 return; 1136 1137 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1138 1139 /* 1140 * In netmap mode, set the map for the packet buffer. 1141 * NOTE: Some drivers (not this one) also need to set 1142 * the physical buffer address in the NIC ring. 1143 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1144 * netmap slot index, si 1145 */ 1146 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i); 1147 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1148 } 1149 } 1150 static void 1151 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1152 { 1153 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1154 struct netmap_slot *slot; 1155 struct if_rxd_update iru; 1156 iflib_fl_t fl; 1157 bus_dmamap_t *map; 1158 int nrxd; 1159 uint32_t i, j, pidx_start; 1160 1161 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1162 if (slot == NULL) 1163 return; 1164 fl = &rxq->ifr_fl[0]; 1165 map = fl->ifl_sds.ifsd_map; 1166 nrxd = ctx->ifc_softc_ctx.isc_nrxd[0]; 1167 iru.iru_paddrs = fl->ifl_bus_addrs; 1168 iru.iru_vaddrs = &fl->ifl_vm_addrs[0]; 1169 iru.iru_idxs = fl->ifl_rxd_idxs; 1170 iru.iru_qsidx = rxq->ifr_id; 1171 iru.iru_buf_size = rxq->ifr_fl[0].ifl_buf_size; 1172 iru.iru_flidx = 0; 1173 1174 for (pidx_start = i = j = 0; i < nrxd; i++, j++) { 1175 int sj = netmap_idx_n2k(&na->rx_rings[rxq->ifr_id], i); 1176 void *addr; 1177 1178 fl->ifl_rxd_idxs[j] = i; 1179 addr = fl->ifl_vm_addrs[j] = PNMB(na, slot + sj, &fl->ifl_bus_addrs[j]); 1180 if (map) { 1181 netmap_load_map(na, rxq->ifr_fl[0].ifl_ifdi->idi_tag, *map, addr); 1182 map++; 1183 } 1184 1185 if (j < IFLIB_MAX_RX_REFRESH && i < nrxd - 1) 1186 continue; 1187 1188 iru.iru_pidx = pidx_start; 1189 pidx_start = i; 1190 iru.iru_count = j; 1191 j = 0; 1192 MPASS(pidx_start + j <= nrxd); 1193 /* Update descriptors and the cached value */ 1194 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1195 } 1196 /* preserve queue */ 1197 if (ctx->ifc_ifp->if_capenable & IFCAP_NETMAP) { 1198 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id]; 1199 int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring); 1200 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, t); 1201 } else 1202 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, nrxd-1); 1203 } 1204 1205 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1206 1207 #else 1208 #define iflib_netmap_txq_init(ctx, txq) 1209 #define iflib_netmap_rxq_init(ctx, rxq) 1210 #define iflib_netmap_detach(ifp) 1211 1212 #define iflib_netmap_attach(ctx) (0) 1213 #define netmap_rx_irq(ifp, qid, budget) (0) 1214 #define netmap_tx_irq(ifp, qid) do {} while (0) 1215 1216 #endif 1217 1218 #if defined(__i386__) || defined(__amd64__) 1219 static __inline void 1220 prefetch(void *x) 1221 { 1222 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1223 } 1224 #else 1225 #define prefetch(x) 1226 #endif 1227 1228 static void 1229 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1230 { 1231 if (err) 1232 return; 1233 *(bus_addr_t *) arg = segs[0].ds_addr; 1234 } 1235 1236 int 1237 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1238 { 1239 int err; 1240 if_shared_ctx_t sctx = ctx->ifc_sctx; 1241 device_t dev = ctx->ifc_dev; 1242 1243 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1244 1245 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1246 sctx->isc_q_align, 0, /* alignment, bounds */ 1247 BUS_SPACE_MAXADDR, /* lowaddr */ 1248 BUS_SPACE_MAXADDR, /* highaddr */ 1249 NULL, NULL, /* filter, filterarg */ 1250 size, /* maxsize */ 1251 1, /* nsegments */ 1252 size, /* maxsegsize */ 1253 BUS_DMA_ALLOCNOW, /* flags */ 1254 NULL, /* lockfunc */ 1255 NULL, /* lockarg */ 1256 &dma->idi_tag); 1257 if (err) { 1258 device_printf(dev, 1259 "%s: bus_dma_tag_create failed: %d\n", 1260 __func__, err); 1261 goto fail_0; 1262 } 1263 1264 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1265 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1266 if (err) { 1267 device_printf(dev, 1268 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1269 __func__, (uintmax_t)size, err); 1270 goto fail_1; 1271 } 1272 1273 dma->idi_paddr = IF_BAD_DMA; 1274 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1275 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1276 if (err || dma->idi_paddr == IF_BAD_DMA) { 1277 device_printf(dev, 1278 "%s: bus_dmamap_load failed: %d\n", 1279 __func__, err); 1280 goto fail_2; 1281 } 1282 1283 dma->idi_size = size; 1284 return (0); 1285 1286 fail_2: 1287 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1288 fail_1: 1289 bus_dma_tag_destroy(dma->idi_tag); 1290 fail_0: 1291 dma->idi_tag = NULL; 1292 1293 return (err); 1294 } 1295 1296 int 1297 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1298 { 1299 int i, err; 1300 iflib_dma_info_t *dmaiter; 1301 1302 dmaiter = dmalist; 1303 for (i = 0; i < count; i++, dmaiter++) { 1304 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1305 break; 1306 } 1307 if (err) 1308 iflib_dma_free_multi(dmalist, i); 1309 return (err); 1310 } 1311 1312 void 1313 iflib_dma_free(iflib_dma_info_t dma) 1314 { 1315 if (dma->idi_tag == NULL) 1316 return; 1317 if (dma->idi_paddr != IF_BAD_DMA) { 1318 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1319 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1320 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1321 dma->idi_paddr = IF_BAD_DMA; 1322 } 1323 if (dma->idi_vaddr != NULL) { 1324 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1325 dma->idi_vaddr = NULL; 1326 } 1327 bus_dma_tag_destroy(dma->idi_tag); 1328 dma->idi_tag = NULL; 1329 } 1330 1331 void 1332 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1333 { 1334 int i; 1335 iflib_dma_info_t *dmaiter = dmalist; 1336 1337 for (i = 0; i < count; i++, dmaiter++) 1338 iflib_dma_free(*dmaiter); 1339 } 1340 1341 #ifdef EARLY_AP_STARTUP 1342 static const int iflib_started = 1; 1343 #else 1344 /* 1345 * We used to abuse the smp_started flag to decide if the queues have been 1346 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1347 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1348 * is set. Run a SYSINIT() strictly after that to just set a usable 1349 * completion flag. 1350 */ 1351 1352 static int iflib_started; 1353 1354 static void 1355 iflib_record_started(void *arg) 1356 { 1357 iflib_started = 1; 1358 } 1359 1360 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1361 iflib_record_started, NULL); 1362 #endif 1363 1364 static int 1365 iflib_fast_intr(void *arg) 1366 { 1367 iflib_filter_info_t info = arg; 1368 struct grouptask *gtask = info->ifi_task; 1369 if (!iflib_started) 1370 return (FILTER_HANDLED); 1371 1372 DBG_COUNTER_INC(fast_intrs); 1373 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1374 return (FILTER_HANDLED); 1375 1376 GROUPTASK_ENQUEUE(gtask); 1377 return (FILTER_HANDLED); 1378 } 1379 1380 static int 1381 iflib_fast_intr_rxtx(void *arg) 1382 { 1383 iflib_filter_info_t info = arg; 1384 struct grouptask *gtask = info->ifi_task; 1385 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1386 if_ctx_t ctx; 1387 int i, cidx; 1388 1389 if (!iflib_started) 1390 return (FILTER_HANDLED); 1391 1392 DBG_COUNTER_INC(fast_intrs); 1393 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1394 return (FILTER_HANDLED); 1395 1396 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1397 qidx_t txqid = rxq->ifr_txqid[i]; 1398 1399 ctx = rxq->ifr_ctx; 1400 1401 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1402 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1403 continue; 1404 } 1405 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1406 } 1407 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1408 cidx = rxq->ifr_cq_cidx; 1409 else 1410 cidx = rxq->ifr_fl[0].ifl_cidx; 1411 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1412 GROUPTASK_ENQUEUE(gtask); 1413 else 1414 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1415 return (FILTER_HANDLED); 1416 } 1417 1418 1419 static int 1420 iflib_fast_intr_ctx(void *arg) 1421 { 1422 iflib_filter_info_t info = arg; 1423 struct grouptask *gtask = info->ifi_task; 1424 1425 if (!iflib_started) 1426 return (FILTER_HANDLED); 1427 1428 DBG_COUNTER_INC(fast_intrs); 1429 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1430 return (FILTER_HANDLED); 1431 1432 GROUPTASK_ENQUEUE(gtask); 1433 return (FILTER_HANDLED); 1434 } 1435 1436 static int 1437 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1438 driver_filter_t filter, driver_intr_t handler, void *arg, 1439 char *name) 1440 { 1441 int rc, flags; 1442 struct resource *res; 1443 void *tag = NULL; 1444 device_t dev = ctx->ifc_dev; 1445 1446 flags = RF_ACTIVE; 1447 if (ctx->ifc_flags & IFC_LEGACY) 1448 flags |= RF_SHAREABLE; 1449 MPASS(rid < 512); 1450 irq->ii_rid = rid; 1451 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1452 if (res == NULL) { 1453 device_printf(dev, 1454 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1455 return (ENOMEM); 1456 } 1457 irq->ii_res = res; 1458 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1459 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1460 filter, handler, arg, &tag); 1461 if (rc != 0) { 1462 device_printf(dev, 1463 "failed to setup interrupt for rid %d, name %s: %d\n", 1464 rid, name ? name : "unknown", rc); 1465 return (rc); 1466 } else if (name) 1467 bus_describe_intr(dev, res, tag, "%s", name); 1468 1469 irq->ii_tag = tag; 1470 return (0); 1471 } 1472 1473 1474 /********************************************************************* 1475 * 1476 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1477 * the information needed to transmit a packet on the wire. This is 1478 * called only once at attach, setup is done every reset. 1479 * 1480 **********************************************************************/ 1481 1482 static int 1483 iflib_txsd_alloc(iflib_txq_t txq) 1484 { 1485 if_ctx_t ctx = txq->ift_ctx; 1486 if_shared_ctx_t sctx = ctx->ifc_sctx; 1487 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1488 device_t dev = ctx->ifc_dev; 1489 int err, nsegments, ntsosegments; 1490 1491 nsegments = scctx->isc_tx_nsegments; 1492 ntsosegments = scctx->isc_tx_tso_segments_max; 1493 MPASS(scctx->isc_ntxd[0] > 0); 1494 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1495 MPASS(nsegments > 0); 1496 MPASS(ntsosegments > 0); 1497 /* 1498 * Setup DMA descriptor areas. 1499 */ 1500 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1501 1, 0, /* alignment, bounds */ 1502 BUS_SPACE_MAXADDR, /* lowaddr */ 1503 BUS_SPACE_MAXADDR, /* highaddr */ 1504 NULL, NULL, /* filter, filterarg */ 1505 sctx->isc_tx_maxsize, /* maxsize */ 1506 nsegments, /* nsegments */ 1507 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1508 0, /* flags */ 1509 NULL, /* lockfunc */ 1510 NULL, /* lockfuncarg */ 1511 &txq->ift_desc_tag))) { 1512 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1513 device_printf(dev,"maxsize: %zd nsegments: %d maxsegsize: %zd\n", 1514 sctx->isc_tx_maxsize, nsegments, sctx->isc_tx_maxsegsize); 1515 goto fail; 1516 } 1517 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1518 1, 0, /* alignment, bounds */ 1519 BUS_SPACE_MAXADDR, /* lowaddr */ 1520 BUS_SPACE_MAXADDR, /* highaddr */ 1521 NULL, NULL, /* filter, filterarg */ 1522 scctx->isc_tx_tso_size_max, /* maxsize */ 1523 ntsosegments, /* nsegments */ 1524 scctx->isc_tx_tso_segsize_max, /* maxsegsize */ 1525 0, /* flags */ 1526 NULL, /* lockfunc */ 1527 NULL, /* lockfuncarg */ 1528 &txq->ift_tso_desc_tag))) { 1529 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1530 1531 goto fail; 1532 } 1533 if (!(txq->ift_sds.ifsd_flags = 1534 (uint8_t *) malloc(sizeof(uint8_t) * 1535 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1536 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1537 err = ENOMEM; 1538 goto fail; 1539 } 1540 if (!(txq->ift_sds.ifsd_m = 1541 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1542 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1543 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1544 err = ENOMEM; 1545 goto fail; 1546 } 1547 1548 /* Create the descriptor buffer dma maps */ 1549 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1550 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1551 return (0); 1552 1553 if (!(txq->ift_sds.ifsd_map = 1554 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1555 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1556 err = ENOMEM; 1557 goto fail; 1558 } 1559 1560 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1561 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1562 if (err != 0) { 1563 device_printf(dev, "Unable to create TX DMA map\n"); 1564 goto fail; 1565 } 1566 } 1567 #endif 1568 return (0); 1569 fail: 1570 /* We free all, it handles case where we are in the middle */ 1571 iflib_tx_structures_free(ctx); 1572 return (err); 1573 } 1574 1575 static void 1576 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1577 { 1578 bus_dmamap_t map; 1579 1580 map = NULL; 1581 if (txq->ift_sds.ifsd_map != NULL) 1582 map = txq->ift_sds.ifsd_map[i]; 1583 if (map != NULL) { 1584 bus_dmamap_unload(txq->ift_desc_tag, map); 1585 bus_dmamap_destroy(txq->ift_desc_tag, map); 1586 txq->ift_sds.ifsd_map[i] = NULL; 1587 } 1588 } 1589 1590 static void 1591 iflib_txq_destroy(iflib_txq_t txq) 1592 { 1593 if_ctx_t ctx = txq->ift_ctx; 1594 1595 for (int i = 0; i < txq->ift_size; i++) 1596 iflib_txsd_destroy(ctx, txq, i); 1597 if (txq->ift_sds.ifsd_map != NULL) { 1598 free(txq->ift_sds.ifsd_map, M_IFLIB); 1599 txq->ift_sds.ifsd_map = NULL; 1600 } 1601 if (txq->ift_sds.ifsd_m != NULL) { 1602 free(txq->ift_sds.ifsd_m, M_IFLIB); 1603 txq->ift_sds.ifsd_m = NULL; 1604 } 1605 if (txq->ift_sds.ifsd_flags != NULL) { 1606 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1607 txq->ift_sds.ifsd_flags = NULL; 1608 } 1609 if (txq->ift_desc_tag != NULL) { 1610 bus_dma_tag_destroy(txq->ift_desc_tag); 1611 txq->ift_desc_tag = NULL; 1612 } 1613 if (txq->ift_tso_desc_tag != NULL) { 1614 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1615 txq->ift_tso_desc_tag = NULL; 1616 } 1617 } 1618 1619 static void 1620 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1621 { 1622 struct mbuf **mp; 1623 1624 mp = &txq->ift_sds.ifsd_m[i]; 1625 if (*mp == NULL) 1626 return; 1627 1628 if (txq->ift_sds.ifsd_map != NULL) { 1629 bus_dmamap_sync(txq->ift_desc_tag, 1630 txq->ift_sds.ifsd_map[i], 1631 BUS_DMASYNC_POSTWRITE); 1632 bus_dmamap_unload(txq->ift_desc_tag, 1633 txq->ift_sds.ifsd_map[i]); 1634 } 1635 m_free(*mp); 1636 DBG_COUNTER_INC(tx_frees); 1637 *mp = NULL; 1638 } 1639 1640 static int 1641 iflib_txq_setup(iflib_txq_t txq) 1642 { 1643 if_ctx_t ctx = txq->ift_ctx; 1644 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1645 iflib_dma_info_t di; 1646 int i; 1647 1648 /* Set number of descriptors available */ 1649 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1650 /* XXX make configurable */ 1651 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1652 1653 /* Reset indices */ 1654 txq->ift_cidx_processed = 0; 1655 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1656 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1657 1658 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1659 bzero((void *)di->idi_vaddr, di->idi_size); 1660 1661 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1662 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1663 bus_dmamap_sync(di->idi_tag, di->idi_map, 1664 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1665 return (0); 1666 } 1667 1668 /********************************************************************* 1669 * 1670 * Allocate memory for rx_buffer structures. Since we use one 1671 * rx_buffer per received packet, the maximum number of rx_buffer's 1672 * that we'll need is equal to the number of receive descriptors 1673 * that we've allocated. 1674 * 1675 **********************************************************************/ 1676 static int 1677 iflib_rxsd_alloc(iflib_rxq_t rxq) 1678 { 1679 if_ctx_t ctx = rxq->ifr_ctx; 1680 if_shared_ctx_t sctx = ctx->ifc_sctx; 1681 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1682 device_t dev = ctx->ifc_dev; 1683 iflib_fl_t fl; 1684 int err; 1685 1686 MPASS(scctx->isc_nrxd[0] > 0); 1687 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1688 1689 fl = rxq->ifr_fl; 1690 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1691 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1692 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1693 1, 0, /* alignment, bounds */ 1694 BUS_SPACE_MAXADDR, /* lowaddr */ 1695 BUS_SPACE_MAXADDR, /* highaddr */ 1696 NULL, NULL, /* filter, filterarg */ 1697 sctx->isc_rx_maxsize, /* maxsize */ 1698 sctx->isc_rx_nsegments, /* nsegments */ 1699 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1700 0, /* flags */ 1701 NULL, /* lockfunc */ 1702 NULL, /* lockarg */ 1703 &fl->ifl_desc_tag); 1704 if (err) { 1705 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1706 __func__, err); 1707 goto fail; 1708 } 1709 if (!(fl->ifl_sds.ifsd_flags = 1710 (uint8_t *) malloc(sizeof(uint8_t) * 1711 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1712 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1713 err = ENOMEM; 1714 goto fail; 1715 } 1716 if (!(fl->ifl_sds.ifsd_m = 1717 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1718 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1719 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1720 err = ENOMEM; 1721 goto fail; 1722 } 1723 if (!(fl->ifl_sds.ifsd_cl = 1724 (caddr_t *) malloc(sizeof(caddr_t) * 1725 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1726 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1727 err = ENOMEM; 1728 goto fail; 1729 } 1730 1731 /* Create the descriptor buffer dma maps */ 1732 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1733 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1734 continue; 1735 1736 if (!(fl->ifl_sds.ifsd_map = 1737 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1738 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1739 err = ENOMEM; 1740 goto fail; 1741 } 1742 1743 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1744 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1745 if (err != 0) { 1746 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1747 goto fail; 1748 } 1749 } 1750 #endif 1751 } 1752 return (0); 1753 1754 fail: 1755 iflib_rx_structures_free(ctx); 1756 return (err); 1757 } 1758 1759 1760 /* 1761 * Internal service routines 1762 */ 1763 1764 struct rxq_refill_cb_arg { 1765 int error; 1766 bus_dma_segment_t seg; 1767 int nseg; 1768 }; 1769 1770 static void 1771 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1772 { 1773 struct rxq_refill_cb_arg *cb_arg = arg; 1774 1775 cb_arg->error = error; 1776 cb_arg->seg = segs[0]; 1777 cb_arg->nseg = nseg; 1778 } 1779 1780 1781 #ifdef ACPI_DMAR 1782 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1783 #else 1784 #define IS_DMAR(ctx) (0) 1785 #endif 1786 1787 /** 1788 * rxq_refill - refill an rxq free-buffer list 1789 * @ctx: the iflib context 1790 * @rxq: the free-list to refill 1791 * @n: the number of new buffers to allocate 1792 * 1793 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1794 * The caller must assure that @n does not exceed the queue's capacity. 1795 */ 1796 static void 1797 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1798 { 1799 struct mbuf *m; 1800 int idx, pidx = fl->ifl_pidx; 1801 caddr_t cl, *sd_cl; 1802 struct mbuf **sd_m; 1803 uint8_t *sd_flags; 1804 struct if_rxd_update iru; 1805 bus_dmamap_t *sd_map; 1806 int n, i = 0; 1807 uint64_t bus_addr; 1808 int err; 1809 1810 sd_m = fl->ifl_sds.ifsd_m; 1811 sd_map = fl->ifl_sds.ifsd_map; 1812 sd_cl = fl->ifl_sds.ifsd_cl; 1813 sd_flags = fl->ifl_sds.ifsd_flags; 1814 idx = pidx; 1815 1816 n = count; 1817 MPASS(n > 0); 1818 MPASS(fl->ifl_credits + n <= fl->ifl_size); 1819 1820 if (pidx < fl->ifl_cidx) 1821 MPASS(pidx + n <= fl->ifl_cidx); 1822 if (pidx == fl->ifl_cidx && (fl->ifl_credits < fl->ifl_size)) 1823 MPASS(fl->ifl_gen == 0); 1824 if (pidx > fl->ifl_cidx) 1825 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1826 1827 DBG_COUNTER_INC(fl_refills); 1828 if (n > 8) 1829 DBG_COUNTER_INC(fl_refills_large); 1830 iru.iru_paddrs = fl->ifl_bus_addrs; 1831 iru.iru_vaddrs = &fl->ifl_vm_addrs[0]; 1832 iru.iru_idxs = fl->ifl_rxd_idxs; 1833 iru.iru_qsidx = fl->ifl_rxq->ifr_id; 1834 iru.iru_buf_size = fl->ifl_buf_size; 1835 iru.iru_flidx = fl->ifl_id; 1836 while (n--) { 1837 /* 1838 * We allocate an uninitialized mbuf + cluster, mbuf is 1839 * initialized after rx. 1840 * 1841 * If the cluster is still set then we know a minimum sized packet was received 1842 */ 1843 if ((cl = sd_cl[idx]) == NULL) { 1844 if ((cl = sd_cl[idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1845 break; 1846 #if MEMORY_LOGGING 1847 fl->ifl_cl_enqueued++; 1848 #endif 1849 } 1850 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1851 break; 1852 } 1853 #if MEMORY_LOGGING 1854 fl->ifl_m_enqueued++; 1855 #endif 1856 1857 DBG_COUNTER_INC(rx_allocs); 1858 #if defined(__i386__) || defined(__amd64__) 1859 if (!IS_DMAR(ctx)) { 1860 bus_addr = pmap_kextract((vm_offset_t)cl); 1861 } else 1862 #endif 1863 { 1864 struct rxq_refill_cb_arg cb_arg; 1865 iflib_rxq_t q; 1866 1867 cb_arg.error = 0; 1868 q = fl->ifl_rxq; 1869 MPASS(sd_map != NULL); 1870 MPASS(sd_map[idx] != NULL); 1871 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[idx], 1872 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1873 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[idx], BUS_DMASYNC_PREREAD); 1874 1875 if (err != 0 || cb_arg.error) { 1876 /* 1877 * !zone_pack ? 1878 */ 1879 if (fl->ifl_zone == zone_pack) 1880 uma_zfree(fl->ifl_zone, cl); 1881 m_free(m); 1882 n = 0; 1883 goto done; 1884 } 1885 bus_addr = cb_arg.seg.ds_addr; 1886 } 1887 sd_flags[idx] |= RX_SW_DESC_INUSE; 1888 1889 MPASS(sd_m[idx] == NULL); 1890 sd_cl[idx] = cl; 1891 sd_m[idx] = m; 1892 fl->ifl_rxd_idxs[i] = idx; 1893 fl->ifl_bus_addrs[i] = bus_addr; 1894 fl->ifl_vm_addrs[i] = cl; 1895 fl->ifl_credits++; 1896 i++; 1897 MPASS(fl->ifl_credits <= fl->ifl_size); 1898 if (++idx == fl->ifl_size) { 1899 fl->ifl_gen = 1; 1900 idx = 0; 1901 } 1902 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 1903 iru.iru_pidx = pidx; 1904 iru.iru_count = i; 1905 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1906 i = 0; 1907 pidx = idx; 1908 } 1909 fl->ifl_pidx = idx; 1910 1911 } 1912 done: 1913 DBG_COUNTER_INC(rxd_flush); 1914 if (fl->ifl_pidx == 0) 1915 pidx = fl->ifl_size - 1; 1916 else 1917 pidx = fl->ifl_pidx - 1; 1918 1919 if (sd_map) 1920 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1921 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1922 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 1923 } 1924 1925 static __inline void 1926 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 1927 { 1928 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 1929 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 1930 #ifdef INVARIANTS 1931 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 1932 #endif 1933 1934 MPASS(fl->ifl_credits <= fl->ifl_size); 1935 MPASS(reclaimable == delta); 1936 1937 if (reclaimable > 0) 1938 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 1939 } 1940 1941 static void 1942 iflib_fl_bufs_free(iflib_fl_t fl) 1943 { 1944 iflib_dma_info_t idi = fl->ifl_ifdi; 1945 uint32_t i; 1946 1947 for (i = 0; i < fl->ifl_size; i++) { 1948 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 1949 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 1950 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 1951 1952 if (*sd_flags & RX_SW_DESC_INUSE) { 1953 if (fl->ifl_sds.ifsd_map != NULL) { 1954 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 1955 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 1956 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 1957 } 1958 if (*sd_m != NULL) { 1959 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 1960 uma_zfree(zone_mbuf, *sd_m); 1961 } 1962 if (*sd_cl != NULL) 1963 uma_zfree(fl->ifl_zone, *sd_cl); 1964 *sd_flags = 0; 1965 } else { 1966 MPASS(*sd_cl == NULL); 1967 MPASS(*sd_m == NULL); 1968 } 1969 #if MEMORY_LOGGING 1970 fl->ifl_m_dequeued++; 1971 fl->ifl_cl_dequeued++; 1972 #endif 1973 *sd_cl = NULL; 1974 *sd_m = NULL; 1975 } 1976 #ifdef INVARIANTS 1977 for (i = 0; i < fl->ifl_size; i++) { 1978 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 1979 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 1980 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 1981 } 1982 #endif 1983 /* 1984 * Reset free list values 1985 */ 1986 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = 0;; 1987 bzero(idi->idi_vaddr, idi->idi_size); 1988 } 1989 1990 /********************************************************************* 1991 * 1992 * Initialize a receive ring and its buffers. 1993 * 1994 **********************************************************************/ 1995 static int 1996 iflib_fl_setup(iflib_fl_t fl) 1997 { 1998 iflib_rxq_t rxq = fl->ifl_rxq; 1999 if_ctx_t ctx = rxq->ifr_ctx; 2000 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2001 2002 /* 2003 ** Free current RX buffer structs and their mbufs 2004 */ 2005 iflib_fl_bufs_free(fl); 2006 /* Now replenish the mbufs */ 2007 MPASS(fl->ifl_credits == 0); 2008 /* 2009 * XXX don't set the max_frame_size to larger 2010 * than the hardware can handle 2011 */ 2012 if (sctx->isc_max_frame_size <= 2048) 2013 fl->ifl_buf_size = MCLBYTES; 2014 #ifndef CONTIGMALLOC_WORKS 2015 else 2016 fl->ifl_buf_size = MJUMPAGESIZE; 2017 #else 2018 else if (sctx->isc_max_frame_size <= 4096) 2019 fl->ifl_buf_size = MJUMPAGESIZE; 2020 else if (sctx->isc_max_frame_size <= 9216) 2021 fl->ifl_buf_size = MJUM9BYTES; 2022 else 2023 fl->ifl_buf_size = MJUM16BYTES; 2024 #endif 2025 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2026 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2027 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2028 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2029 2030 2031 /* avoid pre-allocating zillions of clusters to an idle card 2032 * potentially speeding up attach 2033 */ 2034 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2035 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2036 if (min(128, fl->ifl_size) != fl->ifl_credits) 2037 return (ENOBUFS); 2038 /* 2039 * handle failure 2040 */ 2041 MPASS(rxq != NULL); 2042 MPASS(fl->ifl_ifdi != NULL); 2043 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2044 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2045 return (0); 2046 } 2047 2048 /********************************************************************* 2049 * 2050 * Free receive ring data structures 2051 * 2052 **********************************************************************/ 2053 static void 2054 iflib_rx_sds_free(iflib_rxq_t rxq) 2055 { 2056 iflib_fl_t fl; 2057 int i; 2058 2059 if (rxq->ifr_fl != NULL) { 2060 for (i = 0; i < rxq->ifr_nfl; i++) { 2061 fl = &rxq->ifr_fl[i]; 2062 if (fl->ifl_desc_tag != NULL) { 2063 bus_dma_tag_destroy(fl->ifl_desc_tag); 2064 fl->ifl_desc_tag = NULL; 2065 } 2066 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2067 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2068 /* XXX destroy maps first */ 2069 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2070 fl->ifl_sds.ifsd_m = NULL; 2071 fl->ifl_sds.ifsd_cl = NULL; 2072 fl->ifl_sds.ifsd_map = NULL; 2073 } 2074 free(rxq->ifr_fl, M_IFLIB); 2075 rxq->ifr_fl = NULL; 2076 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2077 } 2078 } 2079 2080 /* 2081 * MI independent logic 2082 * 2083 */ 2084 static void 2085 iflib_timer(void *arg) 2086 { 2087 iflib_txq_t txq = arg; 2088 if_ctx_t ctx = txq->ift_ctx; 2089 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2090 2091 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2092 return; 2093 /* 2094 ** Check on the state of the TX queue(s), this 2095 ** can be done without the lock because its RO 2096 ** and the HUNG state will be static if set. 2097 */ 2098 IFDI_TIMER(ctx, txq->ift_id); 2099 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2100 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2101 (sctx->isc_pause_frames == 0))) 2102 goto hung; 2103 2104 if (ifmp_ring_is_stalled(txq->ift_br)) 2105 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2106 txq->ift_cleaned_prev = txq->ift_cleaned; 2107 /* handle any laggards */ 2108 if (txq->ift_db_pending) 2109 GROUPTASK_ENQUEUE(&txq->ift_task); 2110 2111 sctx->isc_pause_frames = 0; 2112 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2113 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 2114 return; 2115 hung: 2116 CTX_LOCK(ctx); 2117 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2118 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2119 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2120 2121 IFDI_WATCHDOG_RESET(ctx); 2122 ctx->ifc_watchdog_events++; 2123 2124 ctx->ifc_flags |= IFC_DO_RESET; 2125 iflib_admin_intr_deferred(ctx); 2126 CTX_UNLOCK(ctx); 2127 } 2128 2129 static void 2130 iflib_init_locked(if_ctx_t ctx) 2131 { 2132 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2133 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2134 if_t ifp = ctx->ifc_ifp; 2135 iflib_fl_t fl; 2136 iflib_txq_t txq; 2137 iflib_rxq_t rxq; 2138 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2139 2140 2141 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2142 IFDI_INTR_DISABLE(ctx); 2143 2144 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2145 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2146 /* Set hardware offload abilities */ 2147 if_clearhwassist(ifp); 2148 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2149 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2150 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2151 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2152 if (if_getcapenable(ifp) & IFCAP_TSO4) 2153 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2154 if (if_getcapenable(ifp) & IFCAP_TSO6) 2155 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2156 2157 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2158 CALLOUT_LOCK(txq); 2159 callout_stop(&txq->ift_timer); 2160 CALLOUT_UNLOCK(txq); 2161 iflib_netmap_txq_init(ctx, txq); 2162 } 2163 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2164 MPASS(rxq->ifr_id == i); 2165 iflib_netmap_rxq_init(ctx, rxq); 2166 } 2167 #ifdef INVARIANTS 2168 i = if_getdrvflags(ifp); 2169 #endif 2170 IFDI_INIT(ctx); 2171 MPASS(if_getdrvflags(ifp) == i); 2172 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2173 /* XXX this should really be done on a per-queue basis */ 2174 if (if_getcapenable(ifp) & IFCAP_NETMAP) 2175 continue; 2176 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2177 if (iflib_fl_setup(fl)) { 2178 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2179 goto done; 2180 } 2181 } 2182 } 2183 done: 2184 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2185 IFDI_INTR_ENABLE(ctx); 2186 txq = ctx->ifc_txqs; 2187 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2188 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2189 txq->ift_timer.c_cpu); 2190 } 2191 2192 static int 2193 iflib_media_change(if_t ifp) 2194 { 2195 if_ctx_t ctx = if_getsoftc(ifp); 2196 int err; 2197 2198 CTX_LOCK(ctx); 2199 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2200 iflib_init_locked(ctx); 2201 CTX_UNLOCK(ctx); 2202 return (err); 2203 } 2204 2205 static void 2206 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2207 { 2208 if_ctx_t ctx = if_getsoftc(ifp); 2209 2210 CTX_LOCK(ctx); 2211 IFDI_UPDATE_ADMIN_STATUS(ctx); 2212 IFDI_MEDIA_STATUS(ctx, ifmr); 2213 CTX_UNLOCK(ctx); 2214 } 2215 2216 static void 2217 iflib_stop(if_ctx_t ctx) 2218 { 2219 iflib_txq_t txq = ctx->ifc_txqs; 2220 iflib_rxq_t rxq = ctx->ifc_rxqs; 2221 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2222 iflib_dma_info_t di; 2223 iflib_fl_t fl; 2224 int i, j; 2225 2226 /* Tell the stack that the interface is no longer active */ 2227 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2228 2229 IFDI_INTR_DISABLE(ctx); 2230 DELAY(1000); 2231 IFDI_STOP(ctx); 2232 DELAY(1000); 2233 2234 iflib_debug_reset(); 2235 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2236 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2237 /* make sure all transmitters have completed before proceeding XXX */ 2238 2239 /* clean any enqueued buffers */ 2240 iflib_ifmp_purge(txq); 2241 /* Free any existing tx buffers. */ 2242 for (j = 0; j < txq->ift_size; j++) { 2243 iflib_txsd_free(ctx, txq, j); 2244 } 2245 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2246 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2247 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2248 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2249 txq->ift_pullups = 0; 2250 ifmp_ring_reset_stats(txq->ift_br); 2251 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2252 bzero((void *)di->idi_vaddr, di->idi_size); 2253 } 2254 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2255 /* make sure all transmitters have completed before proceeding XXX */ 2256 2257 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++) 2258 bzero((void *)di->idi_vaddr, di->idi_size); 2259 /* also resets the free lists pidx/cidx */ 2260 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2261 iflib_fl_bufs_free(fl); 2262 } 2263 } 2264 2265 static inline caddr_t 2266 calc_next_rxd(iflib_fl_t fl, int cidx) 2267 { 2268 qidx_t size; 2269 int nrxd; 2270 caddr_t start, end, cur, next; 2271 2272 nrxd = fl->ifl_size; 2273 size = fl->ifl_rxd_size; 2274 start = fl->ifl_ifdi->idi_vaddr; 2275 2276 if (__predict_false(size == 0)) 2277 return (start); 2278 cur = start + size*cidx; 2279 end = start + size*nrxd; 2280 next = CACHE_PTR_NEXT(cur); 2281 return (next < end ? next : start); 2282 } 2283 2284 static inline void 2285 prefetch_pkts(iflib_fl_t fl, int cidx) 2286 { 2287 int nextptr; 2288 int nrxd = fl->ifl_size; 2289 caddr_t next_rxd; 2290 2291 2292 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2293 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2294 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2295 next_rxd = calc_next_rxd(fl, cidx); 2296 prefetch(next_rxd); 2297 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2298 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2299 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2300 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2301 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2302 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2303 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2304 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2305 } 2306 2307 static void 2308 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2309 { 2310 int flid, cidx; 2311 bus_dmamap_t map; 2312 iflib_fl_t fl; 2313 iflib_dma_info_t di; 2314 int next; 2315 2316 map = NULL; 2317 flid = irf->irf_flid; 2318 cidx = irf->irf_idx; 2319 fl = &rxq->ifr_fl[flid]; 2320 sd->ifsd_fl = fl; 2321 sd->ifsd_cidx = cidx; 2322 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2323 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2324 fl->ifl_credits--; 2325 #if MEMORY_LOGGING 2326 fl->ifl_m_dequeued++; 2327 #endif 2328 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2329 prefetch_pkts(fl, cidx); 2330 if (fl->ifl_sds.ifsd_map != NULL) { 2331 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2332 prefetch(&fl->ifl_sds.ifsd_map[next]); 2333 map = fl->ifl_sds.ifsd_map[cidx]; 2334 di = fl->ifl_ifdi; 2335 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2336 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2337 bus_dmamap_sync(di->idi_tag, di->idi_map, 2338 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2339 2340 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2341 MPASS(fl->ifl_cidx == cidx); 2342 if (unload) 2343 bus_dmamap_unload(fl->ifl_desc_tag, map); 2344 } 2345 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2346 if (__predict_false(fl->ifl_cidx == 0)) 2347 fl->ifl_gen = 0; 2348 if (map != NULL) 2349 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2350 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2351 } 2352 2353 static struct mbuf * 2354 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2355 { 2356 int i, padlen , flags; 2357 struct mbuf *m, *mh, *mt; 2358 caddr_t cl; 2359 2360 i = 0; 2361 mh = NULL; 2362 do { 2363 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2364 2365 MPASS(*sd->ifsd_cl != NULL); 2366 MPASS(*sd->ifsd_m != NULL); 2367 2368 /* Don't include zero-length frags */ 2369 if (ri->iri_frags[i].irf_len == 0) { 2370 /* XXX we can save the cluster here, but not the mbuf */ 2371 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2372 m_free(*sd->ifsd_m); 2373 *sd->ifsd_m = NULL; 2374 continue; 2375 } 2376 m = *sd->ifsd_m; 2377 *sd->ifsd_m = NULL; 2378 if (mh == NULL) { 2379 flags = M_PKTHDR|M_EXT; 2380 mh = mt = m; 2381 padlen = ri->iri_pad; 2382 } else { 2383 flags = M_EXT; 2384 mt->m_next = m; 2385 mt = m; 2386 /* assuming padding is only on the first fragment */ 2387 padlen = 0; 2388 } 2389 cl = *sd->ifsd_cl; 2390 *sd->ifsd_cl = NULL; 2391 2392 /* Can these two be made one ? */ 2393 m_init(m, M_NOWAIT, MT_DATA, flags); 2394 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2395 /* 2396 * These must follow m_init and m_cljset 2397 */ 2398 m->m_data += padlen; 2399 ri->iri_len -= padlen; 2400 m->m_len = ri->iri_frags[i].irf_len; 2401 } while (++i < ri->iri_nfrags); 2402 2403 return (mh); 2404 } 2405 2406 /* 2407 * Process one software descriptor 2408 */ 2409 static struct mbuf * 2410 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2411 { 2412 struct if_rxsd sd; 2413 struct mbuf *m; 2414 2415 /* should I merge this back in now that the two paths are basically duplicated? */ 2416 if (ri->iri_nfrags == 1 && 2417 ri->iri_frags[0].irf_len <= IFLIB_RX_COPY_THRESH) { 2418 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2419 m = *sd.ifsd_m; 2420 *sd.ifsd_m = NULL; 2421 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2422 #ifndef __NO_STRICT_ALIGNMENT 2423 if (!IP_ALIGNED(m)) 2424 m->m_data += 2; 2425 #endif 2426 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2427 m->m_len = ri->iri_frags[0].irf_len; 2428 } else { 2429 m = assemble_segments(rxq, ri, &sd); 2430 } 2431 m->m_pkthdr.len = ri->iri_len; 2432 m->m_pkthdr.rcvif = ri->iri_ifp; 2433 m->m_flags |= ri->iri_flags; 2434 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2435 m->m_pkthdr.flowid = ri->iri_flowid; 2436 M_HASHTYPE_SET(m, ri->iri_rsstype); 2437 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2438 m->m_pkthdr.csum_data = ri->iri_csum_data; 2439 return (m); 2440 } 2441 2442 static bool 2443 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2444 { 2445 if_ctx_t ctx = rxq->ifr_ctx; 2446 if_shared_ctx_t sctx = ctx->ifc_sctx; 2447 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2448 int avail, i; 2449 qidx_t *cidxp; 2450 struct if_rxd_info ri; 2451 int err, budget_left, rx_bytes, rx_pkts; 2452 iflib_fl_t fl; 2453 struct ifnet *ifp; 2454 int lro_enabled; 2455 2456 /* 2457 * XXX early demux data packets so that if_input processing only handles 2458 * acks in interrupt context 2459 */ 2460 struct mbuf *m, *mh, *mt; 2461 2462 ifp = ctx->ifc_ifp; 2463 #ifdef DEV_NETMAP 2464 if (ifp->if_capenable & IFCAP_NETMAP) { 2465 u_int work = 0; 2466 if (netmap_rx_irq(ifp, rxq->ifr_id, &work)) 2467 return (FALSE); 2468 } 2469 #endif 2470 2471 mh = mt = NULL; 2472 MPASS(budget > 0); 2473 rx_pkts = rx_bytes = 0; 2474 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2475 cidxp = &rxq->ifr_cq_cidx; 2476 else 2477 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2478 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2479 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2480 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2481 DBG_COUNTER_INC(rx_unavail); 2482 return (false); 2483 } 2484 2485 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2486 if (__predict_false(!CTX_ACTIVE(ctx))) { 2487 DBG_COUNTER_INC(rx_ctx_inactive); 2488 break; 2489 } 2490 /* 2491 * Reset client set fields to their default values 2492 */ 2493 rxd_info_zero(&ri); 2494 ri.iri_qsidx = rxq->ifr_id; 2495 ri.iri_cidx = *cidxp; 2496 ri.iri_ifp = ifp; 2497 ri.iri_frags = rxq->ifr_frags; 2498 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2499 2500 if (err) 2501 goto err; 2502 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2503 *cidxp = ri.iri_cidx; 2504 /* Update our consumer index */ 2505 /* XXX NB: shurd - check if this is still safe */ 2506 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2507 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2508 rxq->ifr_cq_gen = 0; 2509 } 2510 /* was this only a completion queue message? */ 2511 if (__predict_false(ri.iri_nfrags == 0)) 2512 continue; 2513 } 2514 MPASS(ri.iri_nfrags != 0); 2515 MPASS(ri.iri_len != 0); 2516 2517 /* will advance the cidx on the corresponding free lists */ 2518 m = iflib_rxd_pkt_get(rxq, &ri); 2519 if (avail == 0 && budget_left) 2520 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2521 2522 if (__predict_false(m == NULL)) { 2523 DBG_COUNTER_INC(rx_mbuf_null); 2524 continue; 2525 } 2526 /* imm_pkt: -- cxgb */ 2527 if (mh == NULL) 2528 mh = mt = m; 2529 else { 2530 mt->m_nextpkt = m; 2531 mt = m; 2532 } 2533 } 2534 /* make sure that we can refill faster than drain */ 2535 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2536 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2537 2538 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2539 while (mh != NULL) { 2540 m = mh; 2541 mh = mh->m_nextpkt; 2542 m->m_nextpkt = NULL; 2543 #ifndef __NO_STRICT_ALIGNMENT 2544 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2545 continue; 2546 #endif 2547 rx_bytes += m->m_pkthdr.len; 2548 rx_pkts++; 2549 #if defined(INET6) || defined(INET) 2550 if (lro_enabled && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2551 continue; 2552 #endif 2553 DBG_COUNTER_INC(rx_if_input); 2554 ifp->if_input(ifp, m); 2555 } 2556 2557 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2558 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2559 2560 /* 2561 * Flush any outstanding LRO work 2562 */ 2563 #if defined(INET6) || defined(INET) 2564 tcp_lro_flush_all(&rxq->ifr_lc); 2565 #endif 2566 if (avail) 2567 return true; 2568 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2569 err: 2570 CTX_LOCK(ctx); 2571 ctx->ifc_flags |= IFC_DO_RESET; 2572 iflib_admin_intr_deferred(ctx); 2573 CTX_UNLOCK(ctx); 2574 return (false); 2575 } 2576 2577 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2578 static inline qidx_t 2579 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2580 { 2581 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2582 qidx_t minthresh = txq->ift_size / 8; 2583 if (in_use > 4*minthresh) 2584 return (notify_count); 2585 if (in_use > 2*minthresh) 2586 return (notify_count >> 1); 2587 if (in_use > minthresh) 2588 return (notify_count >> 3); 2589 return (0); 2590 } 2591 2592 static inline qidx_t 2593 txq_max_rs_deferred(iflib_txq_t txq) 2594 { 2595 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2596 qidx_t minthresh = txq->ift_size / 8; 2597 if (txq->ift_in_use > 4*minthresh) 2598 return (notify_count); 2599 if (txq->ift_in_use > 2*minthresh) 2600 return (notify_count >> 1); 2601 if (txq->ift_in_use > minthresh) 2602 return (notify_count >> 2); 2603 return (2); 2604 } 2605 2606 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2607 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2608 2609 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2610 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2611 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2612 2613 /* forward compatibility for cxgb */ 2614 #define FIRST_QSET(ctx) 0 2615 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2616 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2617 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2618 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2619 2620 /* XXX we should be setting this to something other than zero */ 2621 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2622 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2623 2624 static inline bool 2625 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2626 { 2627 qidx_t dbval, max; 2628 bool rang; 2629 2630 rang = false; 2631 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2632 if (ring || txq->ift_db_pending >= max) { 2633 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2634 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2635 txq->ift_db_pending = txq->ift_npending = 0; 2636 rang = true; 2637 } 2638 return (rang); 2639 } 2640 2641 #ifdef PKT_DEBUG 2642 static void 2643 print_pkt(if_pkt_info_t pi) 2644 { 2645 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2646 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2647 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2648 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2649 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2650 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2651 } 2652 #endif 2653 2654 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2655 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2656 2657 static int 2658 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2659 { 2660 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2661 struct ether_vlan_header *eh; 2662 struct mbuf *m, *n; 2663 2664 n = m = *mp; 2665 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2666 M_WRITABLE(m) == 0) { 2667 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2668 return (ENOMEM); 2669 } else { 2670 m_freem(*mp); 2671 n = *mp = m; 2672 } 2673 } 2674 2675 /* 2676 * Determine where frame payload starts. 2677 * Jump over vlan headers if already present, 2678 * helpful for QinQ too. 2679 */ 2680 if (__predict_false(m->m_len < sizeof(*eh))) { 2681 txq->ift_pullups++; 2682 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2683 return (ENOMEM); 2684 } 2685 eh = mtod(m, struct ether_vlan_header *); 2686 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2687 pi->ipi_etype = ntohs(eh->evl_proto); 2688 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2689 } else { 2690 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2691 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2692 } 2693 2694 switch (pi->ipi_etype) { 2695 #ifdef INET 2696 case ETHERTYPE_IP: 2697 { 2698 struct ip *ip = NULL; 2699 struct tcphdr *th = NULL; 2700 int minthlen; 2701 2702 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2703 if (__predict_false(m->m_len < minthlen)) { 2704 /* 2705 * if this code bloat is causing too much of a hit 2706 * move it to a separate function and mark it noinline 2707 */ 2708 if (m->m_len == pi->ipi_ehdrlen) { 2709 n = m->m_next; 2710 MPASS(n); 2711 if (n->m_len >= sizeof(*ip)) { 2712 ip = (struct ip *)n->m_data; 2713 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2714 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2715 } else { 2716 txq->ift_pullups++; 2717 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2718 return (ENOMEM); 2719 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2720 } 2721 } else { 2722 txq->ift_pullups++; 2723 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2724 return (ENOMEM); 2725 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2726 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2727 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2728 } 2729 } else { 2730 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2731 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2732 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2733 } 2734 pi->ipi_ip_hlen = ip->ip_hl << 2; 2735 pi->ipi_ipproto = ip->ip_p; 2736 pi->ipi_flags |= IPI_TX_IPV4; 2737 2738 if (pi->ipi_csum_flags & CSUM_IP) 2739 ip->ip_sum = 0; 2740 2741 if (pi->ipi_ipproto == IPPROTO_TCP) { 2742 if (__predict_false(th == NULL)) { 2743 txq->ift_pullups++; 2744 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2745 return (ENOMEM); 2746 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2747 } 2748 pi->ipi_tcp_hflags = th->th_flags; 2749 pi->ipi_tcp_hlen = th->th_off << 2; 2750 pi->ipi_tcp_seq = th->th_seq; 2751 } 2752 if (IS_TSO4(pi)) { 2753 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2754 return (ENXIO); 2755 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2756 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2757 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2758 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2759 ip->ip_sum = 0; 2760 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2761 } 2762 } 2763 break; 2764 } 2765 #endif 2766 #ifdef INET6 2767 case ETHERTYPE_IPV6: 2768 { 2769 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2770 struct tcphdr *th; 2771 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2772 2773 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2774 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2775 return (ENOMEM); 2776 } 2777 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2778 2779 /* XXX-BZ this will go badly in case of ext hdrs. */ 2780 pi->ipi_ipproto = ip6->ip6_nxt; 2781 pi->ipi_flags |= IPI_TX_IPV6; 2782 2783 if (pi->ipi_ipproto == IPPROTO_TCP) { 2784 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2785 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2786 return (ENOMEM); 2787 } 2788 pi->ipi_tcp_hflags = th->th_flags; 2789 pi->ipi_tcp_hlen = th->th_off << 2; 2790 } 2791 if (IS_TSO6(pi)) { 2792 2793 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2794 return (ENXIO); 2795 /* 2796 * The corresponding flag is set by the stack in the IPv4 2797 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 2798 * So, set it here because the rest of the flow requires it. 2799 */ 2800 pi->ipi_csum_flags |= CSUM_TCP_IPV6; 2801 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2802 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2803 } 2804 break; 2805 } 2806 #endif 2807 default: 2808 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2809 pi->ipi_ip_hlen = 0; 2810 break; 2811 } 2812 *mp = m; 2813 2814 return (0); 2815 } 2816 2817 static __noinline struct mbuf * 2818 collapse_pkthdr(struct mbuf *m0) 2819 { 2820 struct mbuf *m, *m_next, *tmp; 2821 2822 m = m0; 2823 m_next = m->m_next; 2824 while (m_next != NULL && m_next->m_len == 0) { 2825 m = m_next; 2826 m->m_next = NULL; 2827 m_free(m); 2828 m_next = m_next->m_next; 2829 } 2830 m = m0; 2831 m->m_next = m_next; 2832 if ((m_next->m_flags & M_EXT) == 0) { 2833 m = m_defrag(m, M_NOWAIT); 2834 } else { 2835 tmp = m_next->m_next; 2836 memcpy(m_next, m, MPKTHSIZE); 2837 m = m_next; 2838 m->m_next = tmp; 2839 } 2840 return (m); 2841 } 2842 2843 /* 2844 * If dodgy hardware rejects the scatter gather chain we've handed it 2845 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 2846 * m_defrag'd mbufs 2847 */ 2848 static __noinline struct mbuf * 2849 iflib_remove_mbuf(iflib_txq_t txq) 2850 { 2851 int ntxd, i, pidx; 2852 struct mbuf *m, *mh, **ifsd_m; 2853 2854 pidx = txq->ift_pidx; 2855 ifsd_m = txq->ift_sds.ifsd_m; 2856 ntxd = txq->ift_size; 2857 mh = m = ifsd_m[pidx]; 2858 ifsd_m[pidx] = NULL; 2859 #if MEMORY_LOGGING 2860 txq->ift_dequeued++; 2861 #endif 2862 i = 1; 2863 2864 while (m) { 2865 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 2866 #if MEMORY_LOGGING 2867 txq->ift_dequeued++; 2868 #endif 2869 m = m->m_next; 2870 i++; 2871 } 2872 return (mh); 2873 } 2874 2875 static int 2876 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 2877 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 2878 int max_segs, int flags) 2879 { 2880 if_ctx_t ctx; 2881 if_shared_ctx_t sctx; 2882 if_softc_ctx_t scctx; 2883 int i, next, pidx, mask, err, maxsegsz, ntxd, count; 2884 struct mbuf *m, *tmp, **ifsd_m, **mp; 2885 2886 m = *m0; 2887 2888 /* 2889 * Please don't ever do this 2890 */ 2891 if (__predict_false(m->m_len == 0)) 2892 *m0 = m = collapse_pkthdr(m); 2893 2894 ctx = txq->ift_ctx; 2895 sctx = ctx->ifc_sctx; 2896 scctx = &ctx->ifc_softc_ctx; 2897 ifsd_m = txq->ift_sds.ifsd_m; 2898 ntxd = txq->ift_size; 2899 pidx = txq->ift_pidx; 2900 if (map != NULL) { 2901 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 2902 2903 err = bus_dmamap_load_mbuf_sg(tag, map, 2904 *m0, segs, nsegs, BUS_DMA_NOWAIT); 2905 if (err) 2906 return (err); 2907 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 2908 i = 0; 2909 next = pidx; 2910 mask = (txq->ift_size-1); 2911 m = *m0; 2912 do { 2913 mp = &ifsd_m[next]; 2914 *mp = m; 2915 m = m->m_next; 2916 if (__predict_false((*mp)->m_len == 0)) { 2917 m_free(*mp); 2918 *mp = NULL; 2919 } else 2920 next = (pidx + i) & (ntxd-1); 2921 } while (m != NULL); 2922 } else { 2923 int buflen, sgsize, max_sgsize; 2924 vm_offset_t vaddr; 2925 vm_paddr_t curaddr; 2926 2927 count = i = 0; 2928 maxsegsz = sctx->isc_tx_maxsize; 2929 m = *m0; 2930 do { 2931 if (__predict_false(m->m_len <= 0)) { 2932 tmp = m; 2933 m = m->m_next; 2934 tmp->m_next = NULL; 2935 m_free(tmp); 2936 continue; 2937 } 2938 buflen = m->m_len; 2939 vaddr = (vm_offset_t)m->m_data; 2940 /* 2941 * see if we can't be smarter about physically 2942 * contiguous mappings 2943 */ 2944 next = (pidx + count) & (ntxd-1); 2945 MPASS(ifsd_m[next] == NULL); 2946 #if MEMORY_LOGGING 2947 txq->ift_enqueued++; 2948 #endif 2949 ifsd_m[next] = m; 2950 while (buflen > 0) { 2951 max_sgsize = MIN(buflen, maxsegsz); 2952 curaddr = pmap_kextract(vaddr); 2953 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 2954 sgsize = MIN(sgsize, max_sgsize); 2955 segs[i].ds_addr = curaddr; 2956 segs[i].ds_len = sgsize; 2957 vaddr += sgsize; 2958 buflen -= sgsize; 2959 i++; 2960 if (i >= max_segs) 2961 goto err; 2962 } 2963 count++; 2964 tmp = m; 2965 m = m->m_next; 2966 } while (m != NULL); 2967 *nsegs = i; 2968 } 2969 return (0); 2970 err: 2971 *m0 = iflib_remove_mbuf(txq); 2972 return (EFBIG); 2973 } 2974 2975 static inline caddr_t 2976 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 2977 { 2978 qidx_t size; 2979 int ntxd; 2980 caddr_t start, end, cur, next; 2981 2982 ntxd = txq->ift_size; 2983 size = txq->ift_txd_size[qid]; 2984 start = txq->ift_ifdi[qid].idi_vaddr; 2985 2986 if (__predict_false(size == 0)) 2987 return (start); 2988 cur = start + size*cidx; 2989 end = start + size*ntxd; 2990 next = CACHE_PTR_NEXT(cur); 2991 return (next < end ? next : start); 2992 } 2993 2994 static int 2995 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 2996 { 2997 if_ctx_t ctx; 2998 if_shared_ctx_t sctx; 2999 if_softc_ctx_t scctx; 3000 bus_dma_segment_t *segs; 3001 struct mbuf *m_head; 3002 void *next_txd; 3003 bus_dmamap_t map; 3004 struct if_pkt_info pi; 3005 int remap = 0; 3006 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3007 bus_dma_tag_t desc_tag; 3008 3009 segs = txq->ift_segs; 3010 ctx = txq->ift_ctx; 3011 sctx = ctx->ifc_sctx; 3012 scctx = &ctx->ifc_softc_ctx; 3013 segs = txq->ift_segs; 3014 ntxd = txq->ift_size; 3015 m_head = *m_headp; 3016 map = NULL; 3017 3018 /* 3019 * If we're doing TSO the next descriptor to clean may be quite far ahead 3020 */ 3021 cidx = txq->ift_cidx; 3022 pidx = txq->ift_pidx; 3023 if (ctx->ifc_flags & IFC_PREFETCH) { 3024 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3025 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3026 next_txd = calc_next_txd(txq, cidx, 0); 3027 prefetch(next_txd); 3028 } 3029 3030 /* prefetch the next cache line of mbuf pointers and flags */ 3031 prefetch(&txq->ift_sds.ifsd_m[next]); 3032 if (txq->ift_sds.ifsd_map != NULL) { 3033 prefetch(&txq->ift_sds.ifsd_map[next]); 3034 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3035 prefetch(&txq->ift_sds.ifsd_flags[next]); 3036 } 3037 } else if (txq->ift_sds.ifsd_map != NULL) 3038 map = txq->ift_sds.ifsd_map[pidx]; 3039 3040 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3041 desc_tag = txq->ift_tso_desc_tag; 3042 max_segs = scctx->isc_tx_tso_segments_max; 3043 } else { 3044 desc_tag = txq->ift_desc_tag; 3045 max_segs = scctx->isc_tx_nsegments; 3046 } 3047 m_head = *m_headp; 3048 3049 pkt_info_zero(&pi); 3050 pi.ipi_len = m_head->m_pkthdr.len; 3051 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3052 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3053 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3054 pi.ipi_pidx = pidx; 3055 pi.ipi_qsidx = txq->ift_id; 3056 3057 /* deliberate bitwise OR to make one condition */ 3058 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3059 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3060 return (err); 3061 m_head = *m_headp; 3062 } 3063 3064 retry: 3065 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3066 defrag: 3067 if (__predict_false(err)) { 3068 switch (err) { 3069 case EFBIG: 3070 /* try collapse once and defrag once */ 3071 if (remap == 0) 3072 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3073 if (remap == 1) 3074 m_head = m_defrag(*m_headp, M_NOWAIT); 3075 remap++; 3076 if (__predict_false(m_head == NULL)) 3077 goto defrag_failed; 3078 txq->ift_mbuf_defrag++; 3079 *m_headp = m_head; 3080 goto retry; 3081 break; 3082 case ENOMEM: 3083 txq->ift_no_tx_dma_setup++; 3084 break; 3085 default: 3086 txq->ift_no_tx_dma_setup++; 3087 m_freem(*m_headp); 3088 DBG_COUNTER_INC(tx_frees); 3089 *m_headp = NULL; 3090 break; 3091 } 3092 txq->ift_map_failed++; 3093 DBG_COUNTER_INC(encap_load_mbuf_fail); 3094 return (err); 3095 } 3096 3097 /* 3098 * XXX assumes a 1 to 1 relationship between segments and 3099 * descriptors - this does not hold true on all drivers, e.g. 3100 * cxgb 3101 */ 3102 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3103 txq->ift_no_desc_avail++; 3104 if (map != NULL) 3105 bus_dmamap_unload(desc_tag, map); 3106 DBG_COUNTER_INC(encap_txq_avail_fail); 3107 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3108 GROUPTASK_ENQUEUE(&txq->ift_task); 3109 return (ENOBUFS); 3110 } 3111 /* 3112 * On Intel cards we can greatly reduce the number of TX interrupts 3113 * we see by only setting report status on every Nth descriptor. 3114 * However, this also means that the driver will need to keep track 3115 * of the descriptors that RS was set on to check them for the DD bit. 3116 */ 3117 txq->ift_rs_pending += nsegs + 1; 3118 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3119 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) { 3120 pi.ipi_flags |= IPI_TX_INTR; 3121 txq->ift_rs_pending = 0; 3122 } 3123 3124 pi.ipi_segs = segs; 3125 pi.ipi_nsegs = nsegs; 3126 3127 MPASS(pidx >= 0 && pidx < txq->ift_size); 3128 #ifdef PKT_DEBUG 3129 print_pkt(&pi); 3130 #endif 3131 if (map != NULL) 3132 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3133 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3134 if (map != NULL) 3135 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3136 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3137 DBG_COUNTER_INC(tx_encap); 3138 MPASS(pi.ipi_new_pidx < txq->ift_size); 3139 3140 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3141 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3142 ndesc += txq->ift_size; 3143 txq->ift_gen = 1; 3144 } 3145 /* 3146 * drivers can need as many as 3147 * two sentinels 3148 */ 3149 MPASS(ndesc <= pi.ipi_nsegs + 2); 3150 MPASS(pi.ipi_new_pidx != pidx); 3151 MPASS(ndesc > 0); 3152 txq->ift_in_use += ndesc; 3153 3154 /* 3155 * We update the last software descriptor again here because there may 3156 * be a sentinel and/or there may be more mbufs than segments 3157 */ 3158 txq->ift_pidx = pi.ipi_new_pidx; 3159 txq->ift_npending += pi.ipi_ndescs; 3160 } else if (__predict_false(err == EFBIG && remap < 2)) { 3161 *m_headp = m_head = iflib_remove_mbuf(txq); 3162 remap = 1; 3163 txq->ift_txd_encap_efbig++; 3164 goto defrag; 3165 } else 3166 DBG_COUNTER_INC(encap_txd_encap_fail); 3167 return (err); 3168 3169 defrag_failed: 3170 txq->ift_mbuf_defrag_failed++; 3171 txq->ift_map_failed++; 3172 m_freem(*m_headp); 3173 DBG_COUNTER_INC(tx_frees); 3174 *m_headp = NULL; 3175 return (ENOMEM); 3176 } 3177 3178 static void 3179 iflib_tx_desc_free(iflib_txq_t txq, int n) 3180 { 3181 int hasmap; 3182 uint32_t qsize, cidx, mask, gen; 3183 struct mbuf *m, **ifsd_m; 3184 uint8_t *ifsd_flags; 3185 bus_dmamap_t *ifsd_map; 3186 bool do_prefetch; 3187 3188 cidx = txq->ift_cidx; 3189 gen = txq->ift_gen; 3190 qsize = txq->ift_size; 3191 mask = qsize-1; 3192 hasmap = txq->ift_sds.ifsd_map != NULL; 3193 ifsd_flags = txq->ift_sds.ifsd_flags; 3194 ifsd_m = txq->ift_sds.ifsd_m; 3195 ifsd_map = txq->ift_sds.ifsd_map; 3196 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3197 3198 while (n--) { 3199 if (do_prefetch) { 3200 prefetch(ifsd_m[(cidx + 3) & mask]); 3201 prefetch(ifsd_m[(cidx + 4) & mask]); 3202 } 3203 if (ifsd_m[cidx] != NULL) { 3204 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3205 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3206 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3207 /* 3208 * does it matter if it's not the TSO tag? If so we'll 3209 * have to add the type to flags 3210 */ 3211 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3212 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3213 } 3214 if ((m = ifsd_m[cidx]) != NULL) { 3215 /* XXX we don't support any drivers that batch packets yet */ 3216 MPASS(m->m_nextpkt == NULL); 3217 3218 m_free(m); 3219 ifsd_m[cidx] = NULL; 3220 #if MEMORY_LOGGING 3221 txq->ift_dequeued++; 3222 #endif 3223 DBG_COUNTER_INC(tx_frees); 3224 } 3225 } 3226 if (__predict_false(++cidx == qsize)) { 3227 cidx = 0; 3228 gen = 0; 3229 } 3230 } 3231 txq->ift_cidx = cidx; 3232 txq->ift_gen = gen; 3233 } 3234 3235 static __inline int 3236 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3237 { 3238 int reclaim; 3239 if_ctx_t ctx = txq->ift_ctx; 3240 3241 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3242 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3243 3244 /* 3245 * Need a rate-limiting check so that this isn't called every time 3246 */ 3247 iflib_tx_credits_update(ctx, txq); 3248 reclaim = DESC_RECLAIMABLE(txq); 3249 3250 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3251 #ifdef INVARIANTS 3252 if (iflib_verbose_debug) { 3253 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3254 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3255 reclaim, thresh); 3256 3257 } 3258 #endif 3259 return (0); 3260 } 3261 iflib_tx_desc_free(txq, reclaim); 3262 txq->ift_cleaned += reclaim; 3263 txq->ift_in_use -= reclaim; 3264 3265 return (reclaim); 3266 } 3267 3268 static struct mbuf ** 3269 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3270 { 3271 int next, size; 3272 struct mbuf **items; 3273 3274 size = r->size; 3275 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3276 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3277 3278 prefetch(items[(cidx + offset) & (size-1)]); 3279 if (remaining > 1) { 3280 prefetch(&items[next]); 3281 prefetch(items[(cidx + offset + 1) & (size-1)]); 3282 prefetch(items[(cidx + offset + 2) & (size-1)]); 3283 prefetch(items[(cidx + offset + 3) & (size-1)]); 3284 } 3285 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3286 } 3287 3288 static void 3289 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3290 { 3291 3292 ifmp_ring_check_drainage(txq->ift_br, budget); 3293 } 3294 3295 static uint32_t 3296 iflib_txq_can_drain(struct ifmp_ring *r) 3297 { 3298 iflib_txq_t txq = r->cookie; 3299 if_ctx_t ctx = txq->ift_ctx; 3300 3301 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3302 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3303 } 3304 3305 static uint32_t 3306 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3307 { 3308 iflib_txq_t txq = r->cookie; 3309 if_ctx_t ctx = txq->ift_ctx; 3310 struct ifnet *ifp = ctx->ifc_ifp; 3311 struct mbuf **mp, *m; 3312 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3313 int reclaimed, err, in_use_prev, desc_used; 3314 bool do_prefetch, ring, rang; 3315 3316 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3317 !LINK_ACTIVE(ctx))) { 3318 DBG_COUNTER_INC(txq_drain_notready); 3319 return (0); 3320 } 3321 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3322 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3323 avail = IDXDIFF(pidx, cidx, r->size); 3324 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3325 DBG_COUNTER_INC(txq_drain_flushing); 3326 for (i = 0; i < avail; i++) { 3327 m_free(r->items[(cidx + i) & (r->size-1)]); 3328 r->items[(cidx + i) & (r->size-1)] = NULL; 3329 } 3330 return (avail); 3331 } 3332 3333 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3334 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3335 CALLOUT_LOCK(txq); 3336 callout_stop(&txq->ift_timer); 3337 CALLOUT_UNLOCK(txq); 3338 DBG_COUNTER_INC(txq_drain_oactive); 3339 return (0); 3340 } 3341 if (reclaimed) 3342 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3343 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3344 count = MIN(avail, TX_BATCH_SIZE); 3345 #ifdef INVARIANTS 3346 if (iflib_verbose_debug) 3347 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3348 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3349 #endif 3350 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3351 avail = TXQ_AVAIL(txq); 3352 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3353 int pidx_prev, rem = do_prefetch ? count - i : 0; 3354 3355 mp = _ring_peek_one(r, cidx, i, rem); 3356 MPASS(mp != NULL && *mp != NULL); 3357 if (__predict_false(*mp == (struct mbuf *)txq)) { 3358 consumed++; 3359 reclaimed++; 3360 continue; 3361 } 3362 in_use_prev = txq->ift_in_use; 3363 pidx_prev = txq->ift_pidx; 3364 err = iflib_encap(txq, mp); 3365 if (__predict_false(err)) { 3366 DBG_COUNTER_INC(txq_drain_encapfail); 3367 /* no room - bail out */ 3368 if (err == ENOBUFS) 3369 break; 3370 consumed++; 3371 DBG_COUNTER_INC(txq_drain_encapfail); 3372 /* we can't send this packet - skip it */ 3373 continue; 3374 } 3375 consumed++; 3376 pkt_sent++; 3377 m = *mp; 3378 DBG_COUNTER_INC(tx_sent); 3379 bytes_sent += m->m_pkthdr.len; 3380 mcast_sent += !!(m->m_flags & M_MCAST); 3381 avail = TXQ_AVAIL(txq); 3382 3383 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3384 desc_used += (txq->ift_in_use - in_use_prev); 3385 ETHER_BPF_MTAP(ifp, m); 3386 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3387 break; 3388 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3389 } 3390 3391 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3392 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3393 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3394 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3395 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3396 if (mcast_sent) 3397 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3398 #ifdef INVARIANTS 3399 if (iflib_verbose_debug) 3400 printf("consumed=%d\n", consumed); 3401 #endif 3402 return (consumed); 3403 } 3404 3405 static uint32_t 3406 iflib_txq_drain_always(struct ifmp_ring *r) 3407 { 3408 return (1); 3409 } 3410 3411 static uint32_t 3412 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3413 { 3414 int i, avail; 3415 struct mbuf **mp; 3416 iflib_txq_t txq; 3417 3418 txq = r->cookie; 3419 3420 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3421 CALLOUT_LOCK(txq); 3422 callout_stop(&txq->ift_timer); 3423 CALLOUT_UNLOCK(txq); 3424 3425 avail = IDXDIFF(pidx, cidx, r->size); 3426 for (i = 0; i < avail; i++) { 3427 mp = _ring_peek_one(r, cidx, i, avail - i); 3428 if (__predict_false(*mp == (struct mbuf *)txq)) 3429 continue; 3430 m_freem(*mp); 3431 } 3432 MPASS(ifmp_ring_is_stalled(r) == 0); 3433 return (avail); 3434 } 3435 3436 static void 3437 iflib_ifmp_purge(iflib_txq_t txq) 3438 { 3439 struct ifmp_ring *r; 3440 3441 r = txq->ift_br; 3442 r->drain = iflib_txq_drain_free; 3443 r->can_drain = iflib_txq_drain_always; 3444 3445 ifmp_ring_check_drainage(r, r->size); 3446 3447 r->drain = iflib_txq_drain; 3448 r->can_drain = iflib_txq_can_drain; 3449 } 3450 3451 static void 3452 _task_fn_tx(void *context) 3453 { 3454 iflib_txq_t txq = context; 3455 if_ctx_t ctx = txq->ift_ctx; 3456 struct ifnet *ifp = ctx->ifc_ifp; 3457 int rc; 3458 3459 #ifdef IFLIB_DIAGNOSTICS 3460 txq->ift_cpu_exec_count[curcpu]++; 3461 #endif 3462 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3463 return; 3464 if ((ifp->if_capenable & IFCAP_NETMAP)) { 3465 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3466 netmap_tx_irq(ifp, txq->ift_id); 3467 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3468 return; 3469 } 3470 if (txq->ift_db_pending) 3471 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); 3472 else 3473 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3474 if (ctx->ifc_flags & IFC_LEGACY) 3475 IFDI_INTR_ENABLE(ctx); 3476 else { 3477 rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3478 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3479 } 3480 } 3481 3482 static void 3483 _task_fn_rx(void *context) 3484 { 3485 iflib_rxq_t rxq = context; 3486 if_ctx_t ctx = rxq->ifr_ctx; 3487 bool more; 3488 int rc; 3489 3490 #ifdef IFLIB_DIAGNOSTICS 3491 rxq->ifr_cpu_exec_count[curcpu]++; 3492 #endif 3493 DBG_COUNTER_INC(task_fn_rxs); 3494 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3495 return; 3496 if ((more = iflib_rxeof(rxq, 16 /* XXX */)) == false) { 3497 if (ctx->ifc_flags & IFC_LEGACY) 3498 IFDI_INTR_ENABLE(ctx); 3499 else { 3500 DBG_COUNTER_INC(rx_intr_enables); 3501 rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3502 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3503 } 3504 } 3505 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3506 return; 3507 if (more) 3508 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3509 } 3510 3511 static void 3512 _task_fn_admin(void *context) 3513 { 3514 if_ctx_t ctx = context; 3515 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3516 iflib_txq_t txq; 3517 int i; 3518 3519 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) { 3520 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3521 return; 3522 } 3523 } 3524 3525 CTX_LOCK(ctx); 3526 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3527 CALLOUT_LOCK(txq); 3528 callout_stop(&txq->ift_timer); 3529 CALLOUT_UNLOCK(txq); 3530 } 3531 IFDI_UPDATE_ADMIN_STATUS(ctx); 3532 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3533 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 3534 IFDI_LINK_INTR_ENABLE(ctx); 3535 if (ctx->ifc_flags & IFC_DO_RESET) { 3536 ctx->ifc_flags &= ~IFC_DO_RESET; 3537 iflib_if_init_locked(ctx); 3538 } 3539 CTX_UNLOCK(ctx); 3540 3541 if (LINK_ACTIVE(ctx) == 0) 3542 return; 3543 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3544 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3545 } 3546 3547 3548 static void 3549 _task_fn_iov(void *context) 3550 { 3551 if_ctx_t ctx = context; 3552 3553 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3554 return; 3555 3556 CTX_LOCK(ctx); 3557 IFDI_VFLR_HANDLE(ctx); 3558 CTX_UNLOCK(ctx); 3559 } 3560 3561 static int 3562 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3563 { 3564 int err; 3565 if_int_delay_info_t info; 3566 if_ctx_t ctx; 3567 3568 info = (if_int_delay_info_t)arg1; 3569 ctx = info->iidi_ctx; 3570 info->iidi_req = req; 3571 info->iidi_oidp = oidp; 3572 CTX_LOCK(ctx); 3573 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3574 CTX_UNLOCK(ctx); 3575 return (err); 3576 } 3577 3578 /********************************************************************* 3579 * 3580 * IFNET FUNCTIONS 3581 * 3582 **********************************************************************/ 3583 3584 static void 3585 iflib_if_init_locked(if_ctx_t ctx) 3586 { 3587 iflib_stop(ctx); 3588 iflib_init_locked(ctx); 3589 } 3590 3591 3592 static void 3593 iflib_if_init(void *arg) 3594 { 3595 if_ctx_t ctx = arg; 3596 3597 CTX_LOCK(ctx); 3598 iflib_if_init_locked(ctx); 3599 CTX_UNLOCK(ctx); 3600 } 3601 3602 static int 3603 iflib_if_transmit(if_t ifp, struct mbuf *m) 3604 { 3605 if_ctx_t ctx = if_getsoftc(ifp); 3606 3607 iflib_txq_t txq; 3608 int err, qidx; 3609 3610 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3611 DBG_COUNTER_INC(tx_frees); 3612 m_freem(m); 3613 return (ENOBUFS); 3614 } 3615 3616 MPASS(m->m_nextpkt == NULL); 3617 qidx = 0; 3618 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3619 qidx = QIDX(ctx, m); 3620 /* 3621 * XXX calculate buf_ring based on flowid (divvy up bits?) 3622 */ 3623 txq = &ctx->ifc_txqs[qidx]; 3624 3625 #ifdef DRIVER_BACKPRESSURE 3626 if (txq->ift_closed) { 3627 while (m != NULL) { 3628 next = m->m_nextpkt; 3629 m->m_nextpkt = NULL; 3630 m_freem(m); 3631 m = next; 3632 } 3633 return (ENOBUFS); 3634 } 3635 #endif 3636 #ifdef notyet 3637 qidx = count = 0; 3638 mp = marr; 3639 next = m; 3640 do { 3641 count++; 3642 next = next->m_nextpkt; 3643 } while (next != NULL); 3644 3645 if (count > nitems(marr)) 3646 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3647 /* XXX check nextpkt */ 3648 m_freem(m); 3649 /* XXX simplify for now */ 3650 DBG_COUNTER_INC(tx_frees); 3651 return (ENOBUFS); 3652 } 3653 for (next = m, i = 0; next != NULL; i++) { 3654 mp[i] = next; 3655 next = next->m_nextpkt; 3656 mp[i]->m_nextpkt = NULL; 3657 } 3658 #endif 3659 DBG_COUNTER_INC(tx_seen); 3660 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); 3661 3662 if (err) { 3663 GROUPTASK_ENQUEUE(&txq->ift_task); 3664 /* support forthcoming later */ 3665 #ifdef DRIVER_BACKPRESSURE 3666 txq->ift_closed = TRUE; 3667 #endif 3668 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3669 m_freem(m); 3670 } else if (TXQ_AVAIL(txq) < (txq->ift_size >> 1)) { 3671 GROUPTASK_ENQUEUE(&txq->ift_task); 3672 } 3673 3674 return (err); 3675 } 3676 3677 static void 3678 iflib_if_qflush(if_t ifp) 3679 { 3680 if_ctx_t ctx = if_getsoftc(ifp); 3681 iflib_txq_t txq = ctx->ifc_txqs; 3682 int i; 3683 3684 CTX_LOCK(ctx); 3685 ctx->ifc_flags |= IFC_QFLUSH; 3686 CTX_UNLOCK(ctx); 3687 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3688 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3689 iflib_txq_check_drain(txq, 0); 3690 CTX_LOCK(ctx); 3691 ctx->ifc_flags &= ~IFC_QFLUSH; 3692 CTX_UNLOCK(ctx); 3693 3694 if_qflush(ifp); 3695 } 3696 3697 3698 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3699 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | \ 3700 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 3701 3702 static int 3703 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 3704 { 3705 if_ctx_t ctx = if_getsoftc(ifp); 3706 struct ifreq *ifr = (struct ifreq *)data; 3707 #if defined(INET) || defined(INET6) 3708 struct ifaddr *ifa = (struct ifaddr *)data; 3709 #endif 3710 bool avoid_reset = FALSE; 3711 int err = 0, reinit = 0, bits; 3712 3713 switch (command) { 3714 case SIOCSIFADDR: 3715 #ifdef INET 3716 if (ifa->ifa_addr->sa_family == AF_INET) 3717 avoid_reset = TRUE; 3718 #endif 3719 #ifdef INET6 3720 if (ifa->ifa_addr->sa_family == AF_INET6) 3721 avoid_reset = TRUE; 3722 #endif 3723 /* 3724 ** Calling init results in link renegotiation, 3725 ** so we avoid doing it when possible. 3726 */ 3727 if (avoid_reset) { 3728 if_setflagbits(ifp, IFF_UP,0); 3729 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING)) 3730 reinit = 1; 3731 #ifdef INET 3732 if (!(if_getflags(ifp) & IFF_NOARP)) 3733 arp_ifinit(ifp, ifa); 3734 #endif 3735 } else 3736 err = ether_ioctl(ifp, command, data); 3737 break; 3738 case SIOCSIFMTU: 3739 CTX_LOCK(ctx); 3740 if (ifr->ifr_mtu == if_getmtu(ifp)) { 3741 CTX_UNLOCK(ctx); 3742 break; 3743 } 3744 bits = if_getdrvflags(ifp); 3745 /* stop the driver and free any clusters before proceeding */ 3746 iflib_stop(ctx); 3747 3748 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 3749 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 3750 ctx->ifc_flags |= IFC_MULTISEG; 3751 else 3752 ctx->ifc_flags &= ~IFC_MULTISEG; 3753 err = if_setmtu(ifp, ifr->ifr_mtu); 3754 } 3755 iflib_init_locked(ctx); 3756 if_setdrvflags(ifp, bits); 3757 CTX_UNLOCK(ctx); 3758 break; 3759 case SIOCSIFFLAGS: 3760 CTX_LOCK(ctx); 3761 if (if_getflags(ifp) & IFF_UP) { 3762 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3763 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 3764 (IFF_PROMISC | IFF_ALLMULTI)) { 3765 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 3766 } 3767 } else 3768 reinit = 1; 3769 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3770 iflib_stop(ctx); 3771 } 3772 ctx->ifc_if_flags = if_getflags(ifp); 3773 CTX_UNLOCK(ctx); 3774 break; 3775 case SIOCADDMULTI: 3776 case SIOCDELMULTI: 3777 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3778 CTX_LOCK(ctx); 3779 IFDI_INTR_DISABLE(ctx); 3780 IFDI_MULTI_SET(ctx); 3781 IFDI_INTR_ENABLE(ctx); 3782 CTX_UNLOCK(ctx); 3783 } 3784 break; 3785 case SIOCSIFMEDIA: 3786 CTX_LOCK(ctx); 3787 IFDI_MEDIA_SET(ctx); 3788 CTX_UNLOCK(ctx); 3789 /* falls thru */ 3790 case SIOCGIFMEDIA: 3791 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 3792 break; 3793 case SIOCGI2C: 3794 { 3795 struct ifi2creq i2c; 3796 3797 err = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); 3798 if (err != 0) 3799 break; 3800 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 3801 err = EINVAL; 3802 break; 3803 } 3804 if (i2c.len > sizeof(i2c.data)) { 3805 err = EINVAL; 3806 break; 3807 } 3808 3809 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 3810 err = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); 3811 break; 3812 } 3813 case SIOCSIFCAP: 3814 { 3815 int mask, setmask; 3816 3817 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3818 setmask = 0; 3819 #ifdef TCP_OFFLOAD 3820 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 3821 #endif 3822 setmask |= (mask & IFCAP_FLAGS); 3823 3824 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 3825 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 3826 if ((mask & IFCAP_WOL) && 3827 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 3828 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 3829 if_vlancap(ifp); 3830 /* 3831 * want to ensure that traffic has stopped before we change any of the flags 3832 */ 3833 if (setmask) { 3834 CTX_LOCK(ctx); 3835 bits = if_getdrvflags(ifp); 3836 if (bits & IFF_DRV_RUNNING) 3837 iflib_stop(ctx); 3838 if_togglecapenable(ifp, setmask); 3839 if (bits & IFF_DRV_RUNNING) 3840 iflib_init_locked(ctx); 3841 if_setdrvflags(ifp, bits); 3842 CTX_UNLOCK(ctx); 3843 } 3844 break; 3845 } 3846 case SIOCGPRIVATE_0: 3847 case SIOCSDRVSPEC: 3848 case SIOCGDRVSPEC: 3849 CTX_LOCK(ctx); 3850 err = IFDI_PRIV_IOCTL(ctx, command, data); 3851 CTX_UNLOCK(ctx); 3852 break; 3853 default: 3854 err = ether_ioctl(ifp, command, data); 3855 break; 3856 } 3857 if (reinit) 3858 iflib_if_init(ctx); 3859 return (err); 3860 } 3861 3862 static uint64_t 3863 iflib_if_get_counter(if_t ifp, ift_counter cnt) 3864 { 3865 if_ctx_t ctx = if_getsoftc(ifp); 3866 3867 return (IFDI_GET_COUNTER(ctx, cnt)); 3868 } 3869 3870 /********************************************************************* 3871 * 3872 * OTHER FUNCTIONS EXPORTED TO THE STACK 3873 * 3874 **********************************************************************/ 3875 3876 static void 3877 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 3878 { 3879 if_ctx_t ctx = if_getsoftc(ifp); 3880 3881 if ((void *)ctx != arg) 3882 return; 3883 3884 if ((vtag == 0) || (vtag > 4095)) 3885 return; 3886 3887 CTX_LOCK(ctx); 3888 IFDI_VLAN_REGISTER(ctx, vtag); 3889 /* Re-init to load the changes */ 3890 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 3891 iflib_init_locked(ctx); 3892 CTX_UNLOCK(ctx); 3893 } 3894 3895 static void 3896 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 3897 { 3898 if_ctx_t ctx = if_getsoftc(ifp); 3899 3900 if ((void *)ctx != arg) 3901 return; 3902 3903 if ((vtag == 0) || (vtag > 4095)) 3904 return; 3905 3906 CTX_LOCK(ctx); 3907 IFDI_VLAN_UNREGISTER(ctx, vtag); 3908 /* Re-init to load the changes */ 3909 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 3910 iflib_init_locked(ctx); 3911 CTX_UNLOCK(ctx); 3912 } 3913 3914 static void 3915 iflib_led_func(void *arg, int onoff) 3916 { 3917 if_ctx_t ctx = arg; 3918 3919 CTX_LOCK(ctx); 3920 IFDI_LED_FUNC(ctx, onoff); 3921 CTX_UNLOCK(ctx); 3922 } 3923 3924 /********************************************************************* 3925 * 3926 * BUS FUNCTION DEFINITIONS 3927 * 3928 **********************************************************************/ 3929 3930 int 3931 iflib_device_probe(device_t dev) 3932 { 3933 pci_vendor_info_t *ent; 3934 3935 uint16_t pci_vendor_id, pci_device_id; 3936 uint16_t pci_subvendor_id, pci_subdevice_id; 3937 uint16_t pci_rev_id; 3938 if_shared_ctx_t sctx; 3939 3940 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 3941 return (ENOTSUP); 3942 3943 pci_vendor_id = pci_get_vendor(dev); 3944 pci_device_id = pci_get_device(dev); 3945 pci_subvendor_id = pci_get_subvendor(dev); 3946 pci_subdevice_id = pci_get_subdevice(dev); 3947 pci_rev_id = pci_get_revid(dev); 3948 if (sctx->isc_parse_devinfo != NULL) 3949 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 3950 3951 ent = sctx->isc_vendor_info; 3952 while (ent->pvi_vendor_id != 0) { 3953 if (pci_vendor_id != ent->pvi_vendor_id) { 3954 ent++; 3955 continue; 3956 } 3957 if ((pci_device_id == ent->pvi_device_id) && 3958 ((pci_subvendor_id == ent->pvi_subvendor_id) || 3959 (ent->pvi_subvendor_id == 0)) && 3960 ((pci_subdevice_id == ent->pvi_subdevice_id) || 3961 (ent->pvi_subdevice_id == 0)) && 3962 ((pci_rev_id == ent->pvi_rev_id) || 3963 (ent->pvi_rev_id == 0))) { 3964 3965 device_set_desc_copy(dev, ent->pvi_name); 3966 /* this needs to be changed to zero if the bus probing code 3967 * ever stops re-probing on best match because the sctx 3968 * may have its values over written by register calls 3969 * in subsequent probes 3970 */ 3971 return (BUS_PROBE_DEFAULT); 3972 } 3973 ent++; 3974 } 3975 return (ENXIO); 3976 } 3977 3978 int 3979 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 3980 { 3981 int err, rid, msix, msix_bar; 3982 if_ctx_t ctx; 3983 if_t ifp; 3984 if_softc_ctx_t scctx; 3985 int i; 3986 uint16_t main_txq; 3987 uint16_t main_rxq; 3988 3989 3990 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 3991 3992 if (sc == NULL) { 3993 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 3994 device_set_softc(dev, ctx); 3995 ctx->ifc_flags |= IFC_SC_ALLOCATED; 3996 } 3997 3998 ctx->ifc_sctx = sctx; 3999 ctx->ifc_dev = dev; 4000 ctx->ifc_softc = sc; 4001 4002 if ((err = iflib_register(ctx)) != 0) { 4003 device_printf(dev, "iflib_register failed %d\n", err); 4004 return (err); 4005 } 4006 iflib_add_device_sysctl_pre(ctx); 4007 4008 scctx = &ctx->ifc_softc_ctx; 4009 ifp = ctx->ifc_ifp; 4010 4011 /* 4012 * XXX sanity check that ntxd & nrxd are a power of 2 4013 */ 4014 if (ctx->ifc_sysctl_ntxqs != 0) 4015 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4016 if (ctx->ifc_sysctl_nrxqs != 0) 4017 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4018 4019 for (i = 0; i < sctx->isc_ntxqs; i++) { 4020 if (ctx->ifc_sysctl_ntxds[i] != 0) 4021 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4022 else 4023 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4024 } 4025 4026 for (i = 0; i < sctx->isc_nrxqs; i++) { 4027 if (ctx->ifc_sysctl_nrxds[i] != 0) 4028 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4029 else 4030 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4031 } 4032 4033 for (i = 0; i < sctx->isc_nrxqs; i++) { 4034 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4035 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4036 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4037 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4038 } 4039 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4040 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4041 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4042 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4043 } 4044 } 4045 4046 for (i = 0; i < sctx->isc_ntxqs; i++) { 4047 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4048 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4049 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4050 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4051 } 4052 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4053 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4054 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4055 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4056 } 4057 } 4058 4059 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4060 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4061 return (err); 4062 } 4063 _iflib_pre_assert(scctx); 4064 ctx->ifc_txrx = *scctx->isc_txrx; 4065 4066 #ifdef INVARIANTS 4067 MPASS(scctx->isc_capenable); 4068 if (scctx->isc_capenable & IFCAP_TXCSUM) 4069 MPASS(scctx->isc_tx_csum_flags); 4070 #endif 4071 4072 if_setcapabilities(ifp, scctx->isc_capenable); 4073 if_setcapenable(ifp, scctx->isc_capenable); 4074 4075 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4076 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4077 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4078 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4079 4080 #ifdef ACPI_DMAR 4081 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4082 ctx->ifc_flags |= IFC_DMAR; 4083 #elif !(defined(__i386__) || defined(__amd64__)) 4084 /* set unconditionally for !x86 */ 4085 ctx->ifc_flags |= IFC_DMAR; 4086 #endif 4087 4088 msix_bar = scctx->isc_msix_bar; 4089 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4090 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4091 4092 /* XXX change for per-queue sizes */ 4093 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4094 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4095 for (i = 0; i < sctx->isc_nrxqs; i++) { 4096 if (!powerof2(scctx->isc_nrxd[i])) { 4097 /* round down instead? */ 4098 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4099 err = EINVAL; 4100 goto fail; 4101 } 4102 } 4103 for (i = 0; i < sctx->isc_ntxqs; i++) { 4104 if (!powerof2(scctx->isc_ntxd[i])) { 4105 device_printf(dev, 4106 "# tx descriptors must be a power of 2"); 4107 err = EINVAL; 4108 goto fail; 4109 } 4110 } 4111 4112 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4113 MAX_SINGLE_PACKET_FRACTION) 4114 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4115 MAX_SINGLE_PACKET_FRACTION); 4116 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4117 MAX_SINGLE_PACKET_FRACTION) 4118 scctx->isc_tx_tso_segments_max = max(1, 4119 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4120 4121 /* 4122 * Protect the stack against modern hardware 4123 */ 4124 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4125 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4126 4127 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4128 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4129 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4130 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4131 if (scctx->isc_rss_table_size == 0) 4132 scctx->isc_rss_table_size = 64; 4133 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4134 4135 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4136 /* XXX format name */ 4137 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4138 /* 4139 ** Now setup MSI or MSI/X, should 4140 ** return us the number of supported 4141 ** vectors. (Will be 1 for MSI) 4142 */ 4143 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4144 msix = scctx->isc_vectors; 4145 } else if (scctx->isc_msix_bar != 0) 4146 /* 4147 * The simple fact that isc_msix_bar is not 0 does not mean we 4148 * we have a good value there that is known to work. 4149 */ 4150 msix = iflib_msix_init(ctx); 4151 else { 4152 scctx->isc_vectors = 1; 4153 scctx->isc_ntxqsets = 1; 4154 scctx->isc_nrxqsets = 1; 4155 scctx->isc_intr = IFLIB_INTR_LEGACY; 4156 msix = 0; 4157 } 4158 /* Get memory for the station queues */ 4159 if ((err = iflib_queues_alloc(ctx))) { 4160 device_printf(dev, "Unable to allocate queue memory\n"); 4161 goto fail; 4162 } 4163 4164 if ((err = iflib_qset_structures_setup(ctx))) { 4165 device_printf(dev, "qset structure setup failed %d\n", err); 4166 goto fail_queues; 4167 } 4168 4169 /* 4170 * Group taskqueues aren't properly set up until SMP is started, 4171 * so we disable interrupts until we can handle them post 4172 * SI_SUB_SMP. 4173 * 4174 * XXX: disabling interrupts doesn't actually work, at least for 4175 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4176 * we do null handling and depend on this not causing too large an 4177 * interrupt storm. 4178 */ 4179 IFDI_INTR_DISABLE(ctx); 4180 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4181 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4182 goto fail_intr_free; 4183 } 4184 if (msix <= 1) { 4185 rid = 0; 4186 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4187 MPASS(msix == 1); 4188 rid = 1; 4189 } 4190 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4191 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4192 goto fail_intr_free; 4193 } 4194 } 4195 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4196 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4197 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4198 goto fail_detach; 4199 } 4200 if ((err = iflib_netmap_attach(ctx))) { 4201 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4202 goto fail_detach; 4203 } 4204 *ctxp = ctx; 4205 4206 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4207 iflib_add_device_sysctl_post(ctx); 4208 ctx->ifc_flags |= IFC_INIT_DONE; 4209 return (0); 4210 fail_detach: 4211 ether_ifdetach(ctx->ifc_ifp); 4212 fail_intr_free: 4213 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4214 pci_release_msi(ctx->ifc_dev); 4215 fail_queues: 4216 /* XXX free queues */ 4217 fail: 4218 IFDI_DETACH(ctx); 4219 return (err); 4220 } 4221 4222 int 4223 iflib_device_attach(device_t dev) 4224 { 4225 if_ctx_t ctx; 4226 if_shared_ctx_t sctx; 4227 4228 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4229 return (ENOTSUP); 4230 4231 pci_enable_busmaster(dev); 4232 4233 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4234 } 4235 4236 int 4237 iflib_device_deregister(if_ctx_t ctx) 4238 { 4239 if_t ifp = ctx->ifc_ifp; 4240 iflib_txq_t txq; 4241 iflib_rxq_t rxq; 4242 device_t dev = ctx->ifc_dev; 4243 int i; 4244 struct taskqgroup *tqg; 4245 4246 /* Make sure VLANS are not using driver */ 4247 if (if_vlantrunkinuse(ifp)) { 4248 device_printf(dev,"Vlan in use, detach first\n"); 4249 return (EBUSY); 4250 } 4251 4252 CTX_LOCK(ctx); 4253 ctx->ifc_in_detach = 1; 4254 iflib_stop(ctx); 4255 CTX_UNLOCK(ctx); 4256 4257 /* Unregister VLAN events */ 4258 if (ctx->ifc_vlan_attach_event != NULL) 4259 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4260 if (ctx->ifc_vlan_detach_event != NULL) 4261 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4262 4263 iflib_netmap_detach(ifp); 4264 ether_ifdetach(ifp); 4265 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4266 CTX_LOCK_DESTROY(ctx); 4267 if (ctx->ifc_led_dev != NULL) 4268 led_destroy(ctx->ifc_led_dev); 4269 /* XXX drain any dependent tasks */ 4270 tqg = qgroup_if_io_tqg; 4271 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4272 callout_drain(&txq->ift_timer); 4273 if (txq->ift_task.gt_uniq != NULL) 4274 taskqgroup_detach(tqg, &txq->ift_task); 4275 } 4276 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4277 if (rxq->ifr_task.gt_uniq != NULL) 4278 taskqgroup_detach(tqg, &rxq->ifr_task); 4279 } 4280 tqg = qgroup_if_config_tqg; 4281 if (ctx->ifc_admin_task.gt_uniq != NULL) 4282 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4283 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4284 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4285 4286 IFDI_DETACH(ctx); 4287 device_set_softc(ctx->ifc_dev, NULL); 4288 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4289 pci_release_msi(dev); 4290 } 4291 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4292 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4293 } 4294 if (ctx->ifc_msix_mem != NULL) { 4295 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4296 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4297 ctx->ifc_msix_mem = NULL; 4298 } 4299 4300 bus_generic_detach(dev); 4301 if_free(ifp); 4302 4303 iflib_tx_structures_free(ctx); 4304 iflib_rx_structures_free(ctx); 4305 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4306 free(ctx->ifc_softc, M_IFLIB); 4307 free(ctx, M_IFLIB); 4308 return (0); 4309 } 4310 4311 4312 int 4313 iflib_device_detach(device_t dev) 4314 { 4315 if_ctx_t ctx = device_get_softc(dev); 4316 4317 return (iflib_device_deregister(ctx)); 4318 } 4319 4320 int 4321 iflib_device_suspend(device_t dev) 4322 { 4323 if_ctx_t ctx = device_get_softc(dev); 4324 4325 CTX_LOCK(ctx); 4326 IFDI_SUSPEND(ctx); 4327 CTX_UNLOCK(ctx); 4328 4329 return bus_generic_suspend(dev); 4330 } 4331 int 4332 iflib_device_shutdown(device_t dev) 4333 { 4334 if_ctx_t ctx = device_get_softc(dev); 4335 4336 CTX_LOCK(ctx); 4337 IFDI_SHUTDOWN(ctx); 4338 CTX_UNLOCK(ctx); 4339 4340 return bus_generic_suspend(dev); 4341 } 4342 4343 4344 int 4345 iflib_device_resume(device_t dev) 4346 { 4347 if_ctx_t ctx = device_get_softc(dev); 4348 iflib_txq_t txq = ctx->ifc_txqs; 4349 4350 CTX_LOCK(ctx); 4351 IFDI_RESUME(ctx); 4352 iflib_init_locked(ctx); 4353 CTX_UNLOCK(ctx); 4354 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4355 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4356 4357 return (bus_generic_resume(dev)); 4358 } 4359 4360 int 4361 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4362 { 4363 int error; 4364 if_ctx_t ctx = device_get_softc(dev); 4365 4366 CTX_LOCK(ctx); 4367 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4368 CTX_UNLOCK(ctx); 4369 4370 return (error); 4371 } 4372 4373 void 4374 iflib_device_iov_uninit(device_t dev) 4375 { 4376 if_ctx_t ctx = device_get_softc(dev); 4377 4378 CTX_LOCK(ctx); 4379 IFDI_IOV_UNINIT(ctx); 4380 CTX_UNLOCK(ctx); 4381 } 4382 4383 int 4384 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 4385 { 4386 int error; 4387 if_ctx_t ctx = device_get_softc(dev); 4388 4389 CTX_LOCK(ctx); 4390 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 4391 CTX_UNLOCK(ctx); 4392 4393 return (error); 4394 } 4395 4396 /********************************************************************* 4397 * 4398 * MODULE FUNCTION DEFINITIONS 4399 * 4400 **********************************************************************/ 4401 4402 /* 4403 * - Start a fast taskqueue thread for each core 4404 * - Start a taskqueue for control operations 4405 */ 4406 static int 4407 iflib_module_init(void) 4408 { 4409 return (0); 4410 } 4411 4412 static int 4413 iflib_module_event_handler(module_t mod, int what, void *arg) 4414 { 4415 int err; 4416 4417 switch (what) { 4418 case MOD_LOAD: 4419 if ((err = iflib_module_init()) != 0) 4420 return (err); 4421 break; 4422 case MOD_UNLOAD: 4423 return (EBUSY); 4424 default: 4425 return (EOPNOTSUPP); 4426 } 4427 4428 return (0); 4429 } 4430 4431 /********************************************************************* 4432 * 4433 * PUBLIC FUNCTION DEFINITIONS 4434 * ordered as in iflib.h 4435 * 4436 **********************************************************************/ 4437 4438 4439 static void 4440 _iflib_assert(if_shared_ctx_t sctx) 4441 { 4442 MPASS(sctx->isc_tx_maxsize); 4443 MPASS(sctx->isc_tx_maxsegsize); 4444 4445 MPASS(sctx->isc_rx_maxsize); 4446 MPASS(sctx->isc_rx_nsegments); 4447 MPASS(sctx->isc_rx_maxsegsize); 4448 4449 MPASS(sctx->isc_nrxd_min[0]); 4450 MPASS(sctx->isc_nrxd_max[0]); 4451 MPASS(sctx->isc_nrxd_default[0]); 4452 MPASS(sctx->isc_ntxd_min[0]); 4453 MPASS(sctx->isc_ntxd_max[0]); 4454 MPASS(sctx->isc_ntxd_default[0]); 4455 } 4456 4457 static void 4458 _iflib_pre_assert(if_softc_ctx_t scctx) 4459 { 4460 4461 MPASS(scctx->isc_txrx->ift_txd_encap); 4462 MPASS(scctx->isc_txrx->ift_txd_flush); 4463 MPASS(scctx->isc_txrx->ift_txd_credits_update); 4464 MPASS(scctx->isc_txrx->ift_rxd_available); 4465 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 4466 MPASS(scctx->isc_txrx->ift_rxd_refill); 4467 MPASS(scctx->isc_txrx->ift_rxd_flush); 4468 } 4469 4470 static int 4471 iflib_register(if_ctx_t ctx) 4472 { 4473 if_shared_ctx_t sctx = ctx->ifc_sctx; 4474 driver_t *driver = sctx->isc_driver; 4475 device_t dev = ctx->ifc_dev; 4476 if_t ifp; 4477 4478 _iflib_assert(sctx); 4479 4480 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 4481 4482 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 4483 if (ifp == NULL) { 4484 device_printf(dev, "can not allocate ifnet structure\n"); 4485 return (ENOMEM); 4486 } 4487 4488 /* 4489 * Initialize our context's device specific methods 4490 */ 4491 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 4492 kobj_class_compile((kobj_class_t) driver); 4493 driver->refs++; 4494 4495 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 4496 if_setsoftc(ifp, ctx); 4497 if_setdev(ifp, dev); 4498 if_setinitfn(ifp, iflib_if_init); 4499 if_setioctlfn(ifp, iflib_if_ioctl); 4500 if_settransmitfn(ifp, iflib_if_transmit); 4501 if_setqflushfn(ifp, iflib_if_qflush); 4502 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 4503 4504 ctx->ifc_vlan_attach_event = 4505 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 4506 EVENTHANDLER_PRI_FIRST); 4507 ctx->ifc_vlan_detach_event = 4508 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 4509 EVENTHANDLER_PRI_FIRST); 4510 4511 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 4512 iflib_media_change, iflib_media_status); 4513 4514 return (0); 4515 } 4516 4517 4518 static int 4519 iflib_queues_alloc(if_ctx_t ctx) 4520 { 4521 if_shared_ctx_t sctx = ctx->ifc_sctx; 4522 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4523 device_t dev = ctx->ifc_dev; 4524 int nrxqsets = scctx->isc_nrxqsets; 4525 int ntxqsets = scctx->isc_ntxqsets; 4526 iflib_txq_t txq; 4527 iflib_rxq_t rxq; 4528 iflib_fl_t fl = NULL; 4529 int i, j, cpu, err, txconf, rxconf; 4530 iflib_dma_info_t ifdip; 4531 uint32_t *rxqsizes = scctx->isc_rxqsizes; 4532 uint32_t *txqsizes = scctx->isc_txqsizes; 4533 uint8_t nrxqs = sctx->isc_nrxqs; 4534 uint8_t ntxqs = sctx->isc_ntxqs; 4535 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 4536 caddr_t *vaddrs; 4537 uint64_t *paddrs; 4538 struct ifmp_ring **brscp; 4539 4540 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 4541 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 4542 4543 brscp = NULL; 4544 txq = NULL; 4545 rxq = NULL; 4546 4547 /* Allocate the TX ring struct memory */ 4548 if (!(txq = 4549 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 4550 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4551 device_printf(dev, "Unable to allocate TX ring memory\n"); 4552 err = ENOMEM; 4553 goto fail; 4554 } 4555 4556 /* Now allocate the RX */ 4557 if (!(rxq = 4558 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 4559 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4560 device_printf(dev, "Unable to allocate RX ring memory\n"); 4561 err = ENOMEM; 4562 goto rx_fail; 4563 } 4564 4565 ctx->ifc_txqs = txq; 4566 ctx->ifc_rxqs = rxq; 4567 4568 /* 4569 * XXX handle allocation failure 4570 */ 4571 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 4572 /* Set up some basics */ 4573 4574 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4575 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4576 err = ENOMEM; 4577 goto err_tx_desc; 4578 } 4579 txq->ift_ifdi = ifdip; 4580 for (j = 0; j < ntxqs; j++, ifdip++) { 4581 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4582 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4583 err = ENOMEM; 4584 goto err_tx_desc; 4585 } 4586 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 4587 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 4588 } 4589 txq->ift_ctx = ctx; 4590 txq->ift_id = i; 4591 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 4592 txq->ift_br_offset = 1; 4593 } else { 4594 txq->ift_br_offset = 0; 4595 } 4596 /* XXX fix this */ 4597 txq->ift_timer.c_cpu = cpu; 4598 4599 if (iflib_txsd_alloc(txq)) { 4600 device_printf(dev, "Critical Failure setting up TX buffers\n"); 4601 err = ENOMEM; 4602 goto err_tx_desc; 4603 } 4604 4605 /* Initialize the TX lock */ 4606 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 4607 device_get_nameunit(dev), txq->ift_id); 4608 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 4609 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 4610 4611 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 4612 device_get_nameunit(dev), txq->ift_id); 4613 4614 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 4615 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 4616 if (err) { 4617 /* XXX free any allocated rings */ 4618 device_printf(dev, "Unable to allocate buf_ring\n"); 4619 goto err_tx_desc; 4620 } 4621 } 4622 4623 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 4624 /* Set up some basics */ 4625 4626 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4627 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4628 err = ENOMEM; 4629 goto err_tx_desc; 4630 } 4631 4632 rxq->ifr_ifdi = ifdip; 4633 /* XXX this needs to be changed if #rx queues != #tx queues */ 4634 rxq->ifr_ntxqirq = 1; 4635 rxq->ifr_txqid[0] = i; 4636 for (j = 0; j < nrxqs; j++, ifdip++) { 4637 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4638 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4639 err = ENOMEM; 4640 goto err_tx_desc; 4641 } 4642 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 4643 } 4644 rxq->ifr_ctx = ctx; 4645 rxq->ifr_id = i; 4646 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 4647 rxq->ifr_fl_offset = 1; 4648 } else { 4649 rxq->ifr_fl_offset = 0; 4650 } 4651 rxq->ifr_nfl = nfree_lists; 4652 if (!(fl = 4653 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 4654 device_printf(dev, "Unable to allocate free list memory\n"); 4655 err = ENOMEM; 4656 goto err_tx_desc; 4657 } 4658 rxq->ifr_fl = fl; 4659 for (j = 0; j < nfree_lists; j++) { 4660 fl[j].ifl_rxq = rxq; 4661 fl[j].ifl_id = j; 4662 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 4663 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 4664 } 4665 /* Allocate receive buffers for the ring*/ 4666 if (iflib_rxsd_alloc(rxq)) { 4667 device_printf(dev, 4668 "Critical Failure setting up receive buffers\n"); 4669 err = ENOMEM; 4670 goto err_rx_desc; 4671 } 4672 } 4673 4674 /* TXQs */ 4675 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4676 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4677 for (i = 0; i < ntxqsets; i++) { 4678 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 4679 4680 for (j = 0; j < ntxqs; j++, di++) { 4681 vaddrs[i*ntxqs + j] = di->idi_vaddr; 4682 paddrs[i*ntxqs + j] = di->idi_paddr; 4683 } 4684 } 4685 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 4686 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4687 iflib_tx_structures_free(ctx); 4688 free(vaddrs, M_IFLIB); 4689 free(paddrs, M_IFLIB); 4690 goto err_rx_desc; 4691 } 4692 free(vaddrs, M_IFLIB); 4693 free(paddrs, M_IFLIB); 4694 4695 /* RXQs */ 4696 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4697 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4698 for (i = 0; i < nrxqsets; i++) { 4699 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 4700 4701 for (j = 0; j < nrxqs; j++, di++) { 4702 vaddrs[i*nrxqs + j] = di->idi_vaddr; 4703 paddrs[i*nrxqs + j] = di->idi_paddr; 4704 } 4705 } 4706 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 4707 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4708 iflib_tx_structures_free(ctx); 4709 free(vaddrs, M_IFLIB); 4710 free(paddrs, M_IFLIB); 4711 goto err_rx_desc; 4712 } 4713 free(vaddrs, M_IFLIB); 4714 free(paddrs, M_IFLIB); 4715 4716 return (0); 4717 4718 /* XXX handle allocation failure changes */ 4719 err_rx_desc: 4720 err_tx_desc: 4721 if (ctx->ifc_rxqs != NULL) 4722 free(ctx->ifc_rxqs, M_IFLIB); 4723 ctx->ifc_rxqs = NULL; 4724 if (ctx->ifc_txqs != NULL) 4725 free(ctx->ifc_txqs, M_IFLIB); 4726 ctx->ifc_txqs = NULL; 4727 rx_fail: 4728 if (brscp != NULL) 4729 free(brscp, M_IFLIB); 4730 if (rxq != NULL) 4731 free(rxq, M_IFLIB); 4732 if (txq != NULL) 4733 free(txq, M_IFLIB); 4734 fail: 4735 return (err); 4736 } 4737 4738 static int 4739 iflib_tx_structures_setup(if_ctx_t ctx) 4740 { 4741 iflib_txq_t txq = ctx->ifc_txqs; 4742 int i; 4743 4744 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4745 iflib_txq_setup(txq); 4746 4747 return (0); 4748 } 4749 4750 static void 4751 iflib_tx_structures_free(if_ctx_t ctx) 4752 { 4753 iflib_txq_t txq = ctx->ifc_txqs; 4754 int i, j; 4755 4756 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 4757 iflib_txq_destroy(txq); 4758 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 4759 iflib_dma_free(&txq->ift_ifdi[j]); 4760 } 4761 free(ctx->ifc_txqs, M_IFLIB); 4762 ctx->ifc_txqs = NULL; 4763 IFDI_QUEUES_FREE(ctx); 4764 } 4765 4766 /********************************************************************* 4767 * 4768 * Initialize all receive rings. 4769 * 4770 **********************************************************************/ 4771 static int 4772 iflib_rx_structures_setup(if_ctx_t ctx) 4773 { 4774 iflib_rxq_t rxq = ctx->ifc_rxqs; 4775 int q; 4776 #if defined(INET6) || defined(INET) 4777 int i, err; 4778 #endif 4779 4780 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 4781 #if defined(INET6) || defined(INET) 4782 tcp_lro_free(&rxq->ifr_lc); 4783 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 4784 TCP_LRO_ENTRIES, min(1024, 4785 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 4786 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 4787 goto fail; 4788 } 4789 rxq->ifr_lro_enabled = TRUE; 4790 #endif 4791 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 4792 } 4793 return (0); 4794 #if defined(INET6) || defined(INET) 4795 fail: 4796 /* 4797 * Free RX software descriptors allocated so far, we will only handle 4798 * the rings that completed, the failing case will have 4799 * cleaned up for itself. 'q' failed, so its the terminus. 4800 */ 4801 rxq = ctx->ifc_rxqs; 4802 for (i = 0; i < q; ++i, rxq++) { 4803 iflib_rx_sds_free(rxq); 4804 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 4805 } 4806 return (err); 4807 #endif 4808 } 4809 4810 /********************************************************************* 4811 * 4812 * Free all receive rings. 4813 * 4814 **********************************************************************/ 4815 static void 4816 iflib_rx_structures_free(if_ctx_t ctx) 4817 { 4818 iflib_rxq_t rxq = ctx->ifc_rxqs; 4819 4820 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 4821 iflib_rx_sds_free(rxq); 4822 } 4823 } 4824 4825 static int 4826 iflib_qset_structures_setup(if_ctx_t ctx) 4827 { 4828 int err; 4829 4830 if ((err = iflib_tx_structures_setup(ctx)) != 0) 4831 return (err); 4832 4833 if ((err = iflib_rx_structures_setup(ctx)) != 0) { 4834 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 4835 iflib_tx_structures_free(ctx); 4836 iflib_rx_structures_free(ctx); 4837 } 4838 return (err); 4839 } 4840 4841 int 4842 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 4843 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name) 4844 { 4845 4846 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 4847 } 4848 4849 static int 4850 find_nth(if_ctx_t ctx, cpuset_t *cpus, int qid) 4851 { 4852 int i, cpuid, eqid, count; 4853 4854 CPU_COPY(&ctx->ifc_cpus, cpus); 4855 count = CPU_COUNT(&ctx->ifc_cpus); 4856 eqid = qid % count; 4857 /* clear up to the qid'th bit */ 4858 for (i = 0; i < eqid; i++) { 4859 cpuid = CPU_FFS(cpus); 4860 MPASS(cpuid != 0); 4861 CPU_CLR(cpuid-1, cpus); 4862 } 4863 cpuid = CPU_FFS(cpus); 4864 MPASS(cpuid != 0); 4865 return (cpuid-1); 4866 } 4867 4868 int 4869 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 4870 iflib_intr_type_t type, driver_filter_t *filter, 4871 void *filter_arg, int qid, char *name) 4872 { 4873 struct grouptask *gtask; 4874 struct taskqgroup *tqg; 4875 iflib_filter_info_t info; 4876 cpuset_t cpus; 4877 gtask_fn_t *fn; 4878 int tqrid, err, cpuid; 4879 driver_filter_t *intr_fast; 4880 void *q; 4881 4882 info = &ctx->ifc_filter_info; 4883 tqrid = rid; 4884 4885 switch (type) { 4886 /* XXX merge tx/rx for netmap? */ 4887 case IFLIB_INTR_TX: 4888 q = &ctx->ifc_txqs[qid]; 4889 info = &ctx->ifc_txqs[qid].ift_filter_info; 4890 gtask = &ctx->ifc_txqs[qid].ift_task; 4891 tqg = qgroup_if_io_tqg; 4892 fn = _task_fn_tx; 4893 intr_fast = iflib_fast_intr; 4894 GROUPTASK_INIT(gtask, 0, fn, q); 4895 break; 4896 case IFLIB_INTR_RX: 4897 q = &ctx->ifc_rxqs[qid]; 4898 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 4899 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4900 tqg = qgroup_if_io_tqg; 4901 fn = _task_fn_rx; 4902 intr_fast = iflib_fast_intr; 4903 GROUPTASK_INIT(gtask, 0, fn, q); 4904 break; 4905 case IFLIB_INTR_RXTX: 4906 q = &ctx->ifc_rxqs[qid]; 4907 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 4908 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4909 tqg = qgroup_if_io_tqg; 4910 fn = _task_fn_rx; 4911 intr_fast = iflib_fast_intr_rxtx; 4912 GROUPTASK_INIT(gtask, 0, fn, q); 4913 break; 4914 case IFLIB_INTR_ADMIN: 4915 q = ctx; 4916 tqrid = -1; 4917 info = &ctx->ifc_filter_info; 4918 gtask = &ctx->ifc_admin_task; 4919 tqg = qgroup_if_config_tqg; 4920 fn = _task_fn_admin; 4921 intr_fast = iflib_fast_intr_ctx; 4922 break; 4923 default: 4924 panic("unknown net intr type"); 4925 } 4926 4927 info->ifi_filter = filter; 4928 info->ifi_filter_arg = filter_arg; 4929 info->ifi_task = gtask; 4930 info->ifi_ctx = q; 4931 4932 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 4933 if (err != 0) { 4934 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 4935 return (err); 4936 } 4937 if (type == IFLIB_INTR_ADMIN) 4938 return (0); 4939 4940 if (tqrid != -1) { 4941 cpuid = find_nth(ctx, &cpus, qid); 4942 taskqgroup_attach_cpu(tqg, gtask, q, cpuid, irq->ii_rid, name); 4943 } else { 4944 taskqgroup_attach(tqg, gtask, q, tqrid, name); 4945 } 4946 4947 return (0); 4948 } 4949 4950 void 4951 iflib_softirq_alloc_generic(if_ctx_t ctx, int rid, iflib_intr_type_t type, void *arg, int qid, char *name) 4952 { 4953 struct grouptask *gtask; 4954 struct taskqgroup *tqg; 4955 gtask_fn_t *fn; 4956 void *q; 4957 4958 switch (type) { 4959 case IFLIB_INTR_TX: 4960 q = &ctx->ifc_txqs[qid]; 4961 gtask = &ctx->ifc_txqs[qid].ift_task; 4962 tqg = qgroup_if_io_tqg; 4963 fn = _task_fn_tx; 4964 break; 4965 case IFLIB_INTR_RX: 4966 q = &ctx->ifc_rxqs[qid]; 4967 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4968 tqg = qgroup_if_io_tqg; 4969 fn = _task_fn_rx; 4970 break; 4971 case IFLIB_INTR_IOV: 4972 q = ctx; 4973 gtask = &ctx->ifc_vflr_task; 4974 tqg = qgroup_if_config_tqg; 4975 rid = -1; 4976 fn = _task_fn_iov; 4977 break; 4978 default: 4979 panic("unknown net intr type"); 4980 } 4981 GROUPTASK_INIT(gtask, 0, fn, q); 4982 taskqgroup_attach(tqg, gtask, q, rid, name); 4983 } 4984 4985 void 4986 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 4987 { 4988 if (irq->ii_tag) 4989 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 4990 4991 if (irq->ii_res) 4992 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 4993 } 4994 4995 static int 4996 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name) 4997 { 4998 iflib_txq_t txq = ctx->ifc_txqs; 4999 iflib_rxq_t rxq = ctx->ifc_rxqs; 5000 if_irq_t irq = &ctx->ifc_legacy_irq; 5001 iflib_filter_info_t info; 5002 struct grouptask *gtask; 5003 struct taskqgroup *tqg; 5004 gtask_fn_t *fn; 5005 int tqrid; 5006 void *q; 5007 int err; 5008 5009 q = &ctx->ifc_rxqs[0]; 5010 info = &rxq[0].ifr_filter_info; 5011 gtask = &rxq[0].ifr_task; 5012 tqg = qgroup_if_io_tqg; 5013 tqrid = irq->ii_rid = *rid; 5014 fn = _task_fn_rx; 5015 5016 ctx->ifc_flags |= IFC_LEGACY; 5017 info->ifi_filter = filter; 5018 info->ifi_filter_arg = filter_arg; 5019 info->ifi_task = gtask; 5020 info->ifi_ctx = ctx; 5021 5022 /* We allocate a single interrupt resource */ 5023 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5024 return (err); 5025 GROUPTASK_INIT(gtask, 0, fn, q); 5026 taskqgroup_attach(tqg, gtask, q, tqrid, name); 5027 5028 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5029 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, tqrid, "tx"); 5030 return (0); 5031 } 5032 5033 void 5034 iflib_led_create(if_ctx_t ctx) 5035 { 5036 5037 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5038 device_get_nameunit(ctx->ifc_dev)); 5039 } 5040 5041 void 5042 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5043 { 5044 5045 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5046 } 5047 5048 void 5049 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5050 { 5051 5052 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5053 } 5054 5055 void 5056 iflib_admin_intr_deferred(if_ctx_t ctx) 5057 { 5058 #ifdef INVARIANTS 5059 struct grouptask *gtask; 5060 5061 gtask = &ctx->ifc_admin_task; 5062 MPASS(gtask->gt_taskqueue != NULL); 5063 #endif 5064 5065 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5066 } 5067 5068 void 5069 iflib_iov_intr_deferred(if_ctx_t ctx) 5070 { 5071 5072 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5073 } 5074 5075 void 5076 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5077 { 5078 5079 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5080 } 5081 5082 void 5083 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn, 5084 char *name) 5085 { 5086 5087 GROUPTASK_INIT(gtask, 0, fn, ctx); 5088 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5089 } 5090 5091 void 5092 iflib_config_gtask_deinit(struct grouptask *gtask) 5093 { 5094 5095 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5096 } 5097 5098 void 5099 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5100 { 5101 if_t ifp = ctx->ifc_ifp; 5102 iflib_txq_t txq = ctx->ifc_txqs; 5103 5104 if_setbaudrate(ifp, baudrate); 5105 if (baudrate >= IF_Gbps(10)) 5106 ctx->ifc_flags |= IFC_PREFETCH; 5107 5108 /* If link down, disable watchdog */ 5109 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5110 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5111 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5112 } 5113 ctx->ifc_link_state = link_state; 5114 if_link_state_change(ifp, link_state); 5115 } 5116 5117 static int 5118 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5119 { 5120 int credits; 5121 #ifdef INVARIANTS 5122 int credits_pre = txq->ift_cidx_processed; 5123 #endif 5124 5125 if (ctx->isc_txd_credits_update == NULL) 5126 return (0); 5127 5128 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5129 return (0); 5130 5131 txq->ift_processed += credits; 5132 txq->ift_cidx_processed += credits; 5133 5134 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5135 if (txq->ift_cidx_processed >= txq->ift_size) 5136 txq->ift_cidx_processed -= txq->ift_size; 5137 return (credits); 5138 } 5139 5140 static int 5141 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5142 { 5143 5144 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5145 budget)); 5146 } 5147 5148 void 5149 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5150 const char *description, if_int_delay_info_t info, 5151 int offset, int value) 5152 { 5153 info->iidi_ctx = ctx; 5154 info->iidi_offset = offset; 5155 info->iidi_value = value; 5156 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5157 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5158 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5159 info, 0, iflib_sysctl_int_delay, "I", description); 5160 } 5161 5162 struct mtx * 5163 iflib_ctx_lock_get(if_ctx_t ctx) 5164 { 5165 5166 return (&ctx->ifc_mtx); 5167 } 5168 5169 static int 5170 iflib_msix_init(if_ctx_t ctx) 5171 { 5172 device_t dev = ctx->ifc_dev; 5173 if_shared_ctx_t sctx = ctx->ifc_sctx; 5174 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5175 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5176 int iflib_num_tx_queues, iflib_num_rx_queues; 5177 int err, admincnt, bar; 5178 5179 iflib_num_tx_queues = scctx->isc_ntxqsets; 5180 iflib_num_rx_queues = scctx->isc_nrxqsets; 5181 5182 device_printf(dev, "msix_init qsets capped at %d\n", iflib_num_tx_queues); 5183 5184 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5185 admincnt = sctx->isc_admin_intrcnt; 5186 /* Override by tuneable */ 5187 if (scctx->isc_disable_msix) 5188 goto msi; 5189 5190 /* 5191 ** When used in a virtualized environment 5192 ** PCI BUSMASTER capability may not be set 5193 ** so explicity set it here and rewrite 5194 ** the ENABLE in the MSIX control register 5195 ** at this point to cause the host to 5196 ** successfully initialize us. 5197 */ 5198 { 5199 int msix_ctrl, rid; 5200 5201 pci_enable_busmaster(dev); 5202 rid = 0; 5203 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) { 5204 rid += PCIR_MSIX_CTRL; 5205 msix_ctrl = pci_read_config(dev, rid, 2); 5206 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 5207 pci_write_config(dev, rid, msix_ctrl, 2); 5208 } else { 5209 device_printf(dev, "PCIY_MSIX capability not found; " 5210 "or rid %d == 0.\n", rid); 5211 goto msi; 5212 } 5213 } 5214 5215 /* 5216 * bar == -1 => "trust me I know what I'm doing" 5217 * https://www.youtube.com/watch?v=nnwWKkNau4I 5218 * Some drivers are for hardware that is so shoddily 5219 * documented that no one knows which bars are which 5220 * so the developer has to map all bars. This hack 5221 * allows shoddy garbage to use msix in this framework. 5222 */ 5223 if (bar != -1) { 5224 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5225 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5226 if (ctx->ifc_msix_mem == NULL) { 5227 /* May not be enabled */ 5228 device_printf(dev, "Unable to map MSIX table \n"); 5229 goto msi; 5230 } 5231 } 5232 /* First try MSI/X */ 5233 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5234 device_printf(dev, "System has MSIX disabled \n"); 5235 bus_release_resource(dev, SYS_RES_MEMORY, 5236 bar, ctx->ifc_msix_mem); 5237 ctx->ifc_msix_mem = NULL; 5238 goto msi; 5239 } 5240 #if IFLIB_DEBUG 5241 /* use only 1 qset in debug mode */ 5242 queuemsgs = min(msgs - admincnt, 1); 5243 #else 5244 queuemsgs = msgs - admincnt; 5245 #endif 5246 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) == 0) { 5247 #ifdef RSS 5248 queues = imin(queuemsgs, rss_getnumbuckets()); 5249 #else 5250 queues = queuemsgs; 5251 #endif 5252 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 5253 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 5254 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 5255 } else { 5256 device_printf(dev, "Unable to fetch CPU list\n"); 5257 /* Figure out a reasonable auto config value */ 5258 queues = min(queuemsgs, mp_ncpus); 5259 } 5260 #ifdef RSS 5261 /* If we're doing RSS, clamp at the number of RSS buckets */ 5262 if (queues > rss_getnumbuckets()) 5263 queues = rss_getnumbuckets(); 5264 #endif 5265 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 5266 rx_queues = iflib_num_rx_queues; 5267 else 5268 rx_queues = queues; 5269 /* 5270 * We want this to be all logical CPUs by default 5271 */ 5272 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 5273 tx_queues = iflib_num_tx_queues; 5274 else 5275 tx_queues = mp_ncpus; 5276 5277 if (ctx->ifc_sysctl_qs_eq_override == 0) { 5278 #ifdef INVARIANTS 5279 if (tx_queues != rx_queues) 5280 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 5281 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 5282 #endif 5283 tx_queues = min(rx_queues, tx_queues); 5284 rx_queues = min(rx_queues, tx_queues); 5285 } 5286 5287 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 5288 5289 vectors = rx_queues + admincnt; 5290 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 5291 device_printf(dev, 5292 "Using MSIX interrupts with %d vectors\n", vectors); 5293 scctx->isc_vectors = vectors; 5294 scctx->isc_nrxqsets = rx_queues; 5295 scctx->isc_ntxqsets = tx_queues; 5296 scctx->isc_intr = IFLIB_INTR_MSIX; 5297 5298 return (vectors); 5299 } else { 5300 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 5301 } 5302 msi: 5303 vectors = pci_msi_count(dev); 5304 scctx->isc_nrxqsets = 1; 5305 scctx->isc_ntxqsets = 1; 5306 scctx->isc_vectors = vectors; 5307 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 5308 device_printf(dev,"Using an MSI interrupt\n"); 5309 scctx->isc_intr = IFLIB_INTR_MSI; 5310 } else { 5311 device_printf(dev,"Using a Legacy interrupt\n"); 5312 scctx->isc_intr = IFLIB_INTR_LEGACY; 5313 } 5314 5315 return (vectors); 5316 } 5317 5318 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 5319 5320 static int 5321 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 5322 { 5323 int rc; 5324 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 5325 struct sbuf *sb; 5326 char *ring_state = "UNKNOWN"; 5327 5328 /* XXX needed ? */ 5329 rc = sysctl_wire_old_buffer(req, 0); 5330 MPASS(rc == 0); 5331 if (rc != 0) 5332 return (rc); 5333 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 5334 MPASS(sb != NULL); 5335 if (sb == NULL) 5336 return (ENOMEM); 5337 if (state[3] <= 3) 5338 ring_state = ring_states[state[3]]; 5339 5340 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 5341 state[0], state[1], state[2], ring_state); 5342 rc = sbuf_finish(sb); 5343 sbuf_delete(sb); 5344 return(rc); 5345 } 5346 5347 enum iflib_ndesc_handler { 5348 IFLIB_NTXD_HANDLER, 5349 IFLIB_NRXD_HANDLER, 5350 }; 5351 5352 static int 5353 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 5354 { 5355 if_ctx_t ctx = (void *)arg1; 5356 enum iflib_ndesc_handler type = arg2; 5357 char buf[256] = {0}; 5358 qidx_t *ndesc; 5359 char *p, *next; 5360 int nqs, rc, i; 5361 5362 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 5363 5364 nqs = 8; 5365 switch(type) { 5366 case IFLIB_NTXD_HANDLER: 5367 ndesc = ctx->ifc_sysctl_ntxds; 5368 if (ctx->ifc_sctx) 5369 nqs = ctx->ifc_sctx->isc_ntxqs; 5370 break; 5371 case IFLIB_NRXD_HANDLER: 5372 ndesc = ctx->ifc_sysctl_nrxds; 5373 if (ctx->ifc_sctx) 5374 nqs = ctx->ifc_sctx->isc_nrxqs; 5375 break; 5376 } 5377 if (nqs == 0) 5378 nqs = 8; 5379 5380 for (i=0; i<8; i++) { 5381 if (i >= nqs) 5382 break; 5383 if (i) 5384 strcat(buf, ","); 5385 sprintf(strchr(buf, 0), "%d", ndesc[i]); 5386 } 5387 5388 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 5389 if (rc || req->newptr == NULL) 5390 return rc; 5391 5392 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 5393 i++, p = strsep(&next, " ,")) { 5394 ndesc[i] = strtoul(p, NULL, 10); 5395 } 5396 5397 return(rc); 5398 } 5399 5400 #define NAME_BUFLEN 32 5401 static void 5402 iflib_add_device_sysctl_pre(if_ctx_t ctx) 5403 { 5404 device_t dev = iflib_get_dev(ctx); 5405 struct sysctl_oid_list *child, *oid_list; 5406 struct sysctl_ctx_list *ctx_list; 5407 struct sysctl_oid *node; 5408 5409 ctx_list = device_get_sysctl_ctx(dev); 5410 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 5411 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 5412 CTLFLAG_RD, NULL, "IFLIB fields"); 5413 oid_list = SYSCTL_CHILDREN(node); 5414 5415 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 5416 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 5417 "driver version"); 5418 5419 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 5420 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 5421 "# of txqs to use, 0 => use default #"); 5422 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 5423 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 5424 "# of rxqs to use, 0 => use default #"); 5425 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 5426 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 5427 "permit #txq != #rxq"); 5428 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 5429 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 5430 "disable MSIX (default 0)"); 5431 5432 /* XXX change for per-queue sizes */ 5433 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 5434 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 5435 mp_ndesc_handler, "A", 5436 "list of # of tx descriptors to use, 0 = use default #"); 5437 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 5438 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 5439 mp_ndesc_handler, "A", 5440 "list of # of rx descriptors to use, 0 = use default #"); 5441 } 5442 5443 static void 5444 iflib_add_device_sysctl_post(if_ctx_t ctx) 5445 { 5446 if_shared_ctx_t sctx = ctx->ifc_sctx; 5447 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5448 device_t dev = iflib_get_dev(ctx); 5449 struct sysctl_oid_list *child; 5450 struct sysctl_ctx_list *ctx_list; 5451 iflib_fl_t fl; 5452 iflib_txq_t txq; 5453 iflib_rxq_t rxq; 5454 int i, j; 5455 char namebuf[NAME_BUFLEN]; 5456 char *qfmt; 5457 struct sysctl_oid *queue_node, *fl_node, *node; 5458 struct sysctl_oid_list *queue_list, *fl_list; 5459 ctx_list = device_get_sysctl_ctx(dev); 5460 5461 node = ctx->ifc_sysctl_node; 5462 child = SYSCTL_CHILDREN(node); 5463 5464 if (scctx->isc_ntxqsets > 100) 5465 qfmt = "txq%03d"; 5466 else if (scctx->isc_ntxqsets > 10) 5467 qfmt = "txq%02d"; 5468 else 5469 qfmt = "txq%d"; 5470 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 5471 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5472 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5473 CTLFLAG_RD, NULL, "Queue Name"); 5474 queue_list = SYSCTL_CHILDREN(queue_node); 5475 #if MEMORY_LOGGING 5476 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 5477 CTLFLAG_RD, 5478 &txq->ift_dequeued, "total mbufs freed"); 5479 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 5480 CTLFLAG_RD, 5481 &txq->ift_enqueued, "total mbufs enqueued"); 5482 #endif 5483 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 5484 CTLFLAG_RD, 5485 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 5486 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 5487 CTLFLAG_RD, 5488 &txq->ift_pullups, "# of times m_pullup was called"); 5489 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 5490 CTLFLAG_RD, 5491 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 5492 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 5493 CTLFLAG_RD, 5494 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 5495 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 5496 CTLFLAG_RD, 5497 &txq->ift_map_failed, "# of times dma map failed"); 5498 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 5499 CTLFLAG_RD, 5500 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 5501 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 5502 CTLFLAG_RD, 5503 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 5504 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 5505 CTLFLAG_RD, 5506 &txq->ift_pidx, 1, "Producer Index"); 5507 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 5508 CTLFLAG_RD, 5509 &txq->ift_cidx, 1, "Consumer Index"); 5510 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 5511 CTLFLAG_RD, 5512 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 5513 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 5514 CTLFLAG_RD, 5515 &txq->ift_in_use, 1, "descriptors in use"); 5516 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 5517 CTLFLAG_RD, 5518 &txq->ift_processed, "descriptors procesed for clean"); 5519 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 5520 CTLFLAG_RD, 5521 &txq->ift_cleaned, "total cleaned"); 5522 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 5523 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 5524 0, mp_ring_state_handler, "A", "soft ring state"); 5525 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 5526 CTLFLAG_RD, &txq->ift_br->enqueues, 5527 "# of enqueues to the mp_ring for this queue"); 5528 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 5529 CTLFLAG_RD, &txq->ift_br->drops, 5530 "# of drops in the mp_ring for this queue"); 5531 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 5532 CTLFLAG_RD, &txq->ift_br->starts, 5533 "# of normal consumer starts in the mp_ring for this queue"); 5534 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 5535 CTLFLAG_RD, &txq->ift_br->stalls, 5536 "# of consumer stalls in the mp_ring for this queue"); 5537 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 5538 CTLFLAG_RD, &txq->ift_br->restarts, 5539 "# of consumer restarts in the mp_ring for this queue"); 5540 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 5541 CTLFLAG_RD, &txq->ift_br->abdications, 5542 "# of consumer abdications in the mp_ring for this queue"); 5543 } 5544 5545 if (scctx->isc_nrxqsets > 100) 5546 qfmt = "rxq%03d"; 5547 else if (scctx->isc_nrxqsets > 10) 5548 qfmt = "rxq%02d"; 5549 else 5550 qfmt = "rxq%d"; 5551 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 5552 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5553 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5554 CTLFLAG_RD, NULL, "Queue Name"); 5555 queue_list = SYSCTL_CHILDREN(queue_node); 5556 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5557 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 5558 CTLFLAG_RD, 5559 &rxq->ifr_cq_pidx, 1, "Producer Index"); 5560 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 5561 CTLFLAG_RD, 5562 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 5563 } 5564 5565 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 5566 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 5567 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 5568 CTLFLAG_RD, NULL, "freelist Name"); 5569 fl_list = SYSCTL_CHILDREN(fl_node); 5570 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 5571 CTLFLAG_RD, 5572 &fl->ifl_pidx, 1, "Producer Index"); 5573 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 5574 CTLFLAG_RD, 5575 &fl->ifl_cidx, 1, "Consumer Index"); 5576 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 5577 CTLFLAG_RD, 5578 &fl->ifl_credits, 1, "credits available"); 5579 #if MEMORY_LOGGING 5580 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 5581 CTLFLAG_RD, 5582 &fl->ifl_m_enqueued, "mbufs allocated"); 5583 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 5584 CTLFLAG_RD, 5585 &fl->ifl_m_dequeued, "mbufs freed"); 5586 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 5587 CTLFLAG_RD, 5588 &fl->ifl_cl_enqueued, "clusters allocated"); 5589 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 5590 CTLFLAG_RD, 5591 &fl->ifl_cl_dequeued, "clusters freed"); 5592 #endif 5593 5594 } 5595 } 5596 5597 } 5598 5599 #ifndef __NO_STRICT_ALIGNMENT 5600 static struct mbuf * 5601 iflib_fixup_rx(struct mbuf *m) 5602 { 5603 struct mbuf *n; 5604 5605 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 5606 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 5607 m->m_data += ETHER_HDR_LEN; 5608 n = m; 5609 } else { 5610 MGETHDR(n, M_NOWAIT, MT_DATA); 5611 if (n == NULL) { 5612 m_freem(m); 5613 return (NULL); 5614 } 5615 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 5616 m->m_data += ETHER_HDR_LEN; 5617 m->m_len -= ETHER_HDR_LEN; 5618 n->m_len = ETHER_HDR_LEN; 5619 M_MOVE_PKTHDR(n, m); 5620 n->m_next = m; 5621 } 5622 return (n); 5623 } 5624 #endif 5625