1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/pfil.h> 63 #include <net/vnet.h> 64 65 #include <netinet/in.h> 66 #include <netinet/in_pcb.h> 67 #include <netinet/tcp_lro.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/if_ether.h> 70 #include <netinet/ip.h> 71 #include <netinet/ip6.h> 72 #include <netinet/tcp.h> 73 #include <netinet/ip_var.h> 74 #include <netinet/netdump/netdump.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 120 /* 121 * File organization: 122 * - private structures 123 * - iflib private utility functions 124 * - ifnet functions 125 * - vlan registry and other exported functions 126 * - iflib public core functions 127 * 128 * 129 */ 130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 131 132 struct iflib_txq; 133 typedef struct iflib_txq *iflib_txq_t; 134 struct iflib_rxq; 135 typedef struct iflib_rxq *iflib_rxq_t; 136 struct iflib_fl; 137 typedef struct iflib_fl *iflib_fl_t; 138 139 struct iflib_ctx; 140 141 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 142 static void iflib_timer(void *arg); 143 144 typedef struct iflib_filter_info { 145 driver_filter_t *ifi_filter; 146 void *ifi_filter_arg; 147 struct grouptask *ifi_task; 148 void *ifi_ctx; 149 } *iflib_filter_info_t; 150 151 struct iflib_ctx { 152 KOBJ_FIELDS; 153 /* 154 * Pointer to hardware driver's softc 155 */ 156 void *ifc_softc; 157 device_t ifc_dev; 158 if_t ifc_ifp; 159 160 cpuset_t ifc_cpus; 161 if_shared_ctx_t ifc_sctx; 162 struct if_softc_ctx ifc_softc_ctx; 163 164 struct sx ifc_ctx_sx; 165 struct mtx ifc_state_mtx; 166 167 iflib_txq_t ifc_txqs; 168 iflib_rxq_t ifc_rxqs; 169 uint32_t ifc_if_flags; 170 uint32_t ifc_flags; 171 uint32_t ifc_max_fl_buf_size; 172 uint32_t ifc_rx_mbuf_sz; 173 174 int ifc_link_state; 175 int ifc_watchdog_events; 176 struct cdev *ifc_led_dev; 177 struct resource *ifc_msix_mem; 178 179 struct if_irq ifc_legacy_irq; 180 struct grouptask ifc_admin_task; 181 struct grouptask ifc_vflr_task; 182 struct iflib_filter_info ifc_filter_info; 183 struct ifmedia ifc_media; 184 struct ifmedia *ifc_mediap; 185 186 struct sysctl_oid *ifc_sysctl_node; 187 uint16_t ifc_sysctl_ntxqs; 188 uint16_t ifc_sysctl_nrxqs; 189 uint16_t ifc_sysctl_qs_eq_override; 190 uint16_t ifc_sysctl_rx_budget; 191 uint16_t ifc_sysctl_tx_abdicate; 192 uint16_t ifc_sysctl_core_offset; 193 #define CORE_OFFSET_UNSPECIFIED 0xffff 194 uint8_t ifc_sysctl_separate_txrx; 195 196 qidx_t ifc_sysctl_ntxds[8]; 197 qidx_t ifc_sysctl_nrxds[8]; 198 struct if_txrx ifc_txrx; 199 #define isc_txd_encap ifc_txrx.ift_txd_encap 200 #define isc_txd_flush ifc_txrx.ift_txd_flush 201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 202 #define isc_rxd_available ifc_txrx.ift_rxd_available 203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 209 eventhandler_tag ifc_vlan_attach_event; 210 eventhandler_tag ifc_vlan_detach_event; 211 struct ether_addr ifc_mac; 212 }; 213 214 void * 215 iflib_get_softc(if_ctx_t ctx) 216 { 217 218 return (ctx->ifc_softc); 219 } 220 221 device_t 222 iflib_get_dev(if_ctx_t ctx) 223 { 224 225 return (ctx->ifc_dev); 226 } 227 228 if_t 229 iflib_get_ifp(if_ctx_t ctx) 230 { 231 232 return (ctx->ifc_ifp); 233 } 234 235 struct ifmedia * 236 iflib_get_media(if_ctx_t ctx) 237 { 238 239 return (ctx->ifc_mediap); 240 } 241 242 uint32_t 243 iflib_get_flags(if_ctx_t ctx) 244 { 245 return (ctx->ifc_flags); 246 } 247 248 void 249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 250 { 251 252 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 253 } 254 255 if_softc_ctx_t 256 iflib_get_softc_ctx(if_ctx_t ctx) 257 { 258 259 return (&ctx->ifc_softc_ctx); 260 } 261 262 if_shared_ctx_t 263 iflib_get_sctx(if_ctx_t ctx) 264 { 265 266 return (ctx->ifc_sctx); 267 } 268 269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 272 273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 275 276 typedef struct iflib_sw_rx_desc_array { 277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 278 struct mbuf **ifsd_m; /* pkthdr mbufs */ 279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 281 } iflib_rxsd_array_t; 282 283 typedef struct iflib_sw_tx_desc_array { 284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 286 struct mbuf **ifsd_m; /* pkthdr mbufs */ 287 } if_txsd_vec_t; 288 289 /* magic number that should be high enough for any hardware */ 290 #define IFLIB_MAX_TX_SEGS 128 291 #define IFLIB_RX_COPY_THRESH 128 292 #define IFLIB_MAX_RX_REFRESH 32 293 /* The minimum descriptors per second before we start coalescing */ 294 #define IFLIB_MIN_DESC_SEC 16384 295 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 296 #define IFLIB_QUEUE_IDLE 0 297 #define IFLIB_QUEUE_HUNG 1 298 #define IFLIB_QUEUE_WORKING 2 299 /* maximum number of txqs that can share an rx interrupt */ 300 #define IFLIB_MAX_TX_SHARED_INTR 4 301 302 /* this should really scale with ring size - this is a fairly arbitrary value */ 303 #define TX_BATCH_SIZE 32 304 305 #define IFLIB_RESTART_BUDGET 8 306 307 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 308 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 309 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 310 311 struct iflib_txq { 312 qidx_t ift_in_use; 313 qidx_t ift_cidx; 314 qidx_t ift_cidx_processed; 315 qidx_t ift_pidx; 316 uint8_t ift_gen; 317 uint8_t ift_br_offset; 318 uint16_t ift_npending; 319 uint16_t ift_db_pending; 320 uint16_t ift_rs_pending; 321 /* implicit pad */ 322 uint8_t ift_txd_size[8]; 323 uint64_t ift_processed; 324 uint64_t ift_cleaned; 325 uint64_t ift_cleaned_prev; 326 #if MEMORY_LOGGING 327 uint64_t ift_enqueued; 328 uint64_t ift_dequeued; 329 #endif 330 uint64_t ift_no_tx_dma_setup; 331 uint64_t ift_no_desc_avail; 332 uint64_t ift_mbuf_defrag_failed; 333 uint64_t ift_mbuf_defrag; 334 uint64_t ift_map_failed; 335 uint64_t ift_txd_encap_efbig; 336 uint64_t ift_pullups; 337 uint64_t ift_last_timer_tick; 338 339 struct mtx ift_mtx; 340 struct mtx ift_db_mtx; 341 342 /* constant values */ 343 if_ctx_t ift_ctx; 344 struct ifmp_ring *ift_br; 345 struct grouptask ift_task; 346 qidx_t ift_size; 347 uint16_t ift_id; 348 struct callout ift_timer; 349 350 if_txsd_vec_t ift_sds; 351 uint8_t ift_qstatus; 352 uint8_t ift_closed; 353 uint8_t ift_update_freq; 354 struct iflib_filter_info ift_filter_info; 355 bus_dma_tag_t ift_buf_tag; 356 bus_dma_tag_t ift_tso_buf_tag; 357 iflib_dma_info_t ift_ifdi; 358 #define MTX_NAME_LEN 16 359 char ift_mtx_name[MTX_NAME_LEN]; 360 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 361 #ifdef IFLIB_DIAGNOSTICS 362 uint64_t ift_cpu_exec_count[256]; 363 #endif 364 } __aligned(CACHE_LINE_SIZE); 365 366 struct iflib_fl { 367 qidx_t ifl_cidx; 368 qidx_t ifl_pidx; 369 qidx_t ifl_credits; 370 uint8_t ifl_gen; 371 uint8_t ifl_rxd_size; 372 #if MEMORY_LOGGING 373 uint64_t ifl_m_enqueued; 374 uint64_t ifl_m_dequeued; 375 uint64_t ifl_cl_enqueued; 376 uint64_t ifl_cl_dequeued; 377 #endif 378 /* implicit pad */ 379 380 bitstr_t *ifl_rx_bitmap; 381 qidx_t ifl_fragidx; 382 /* constant */ 383 qidx_t ifl_size; 384 uint16_t ifl_buf_size; 385 uint16_t ifl_cltype; 386 uma_zone_t ifl_zone; 387 iflib_rxsd_array_t ifl_sds; 388 iflib_rxq_t ifl_rxq; 389 uint8_t ifl_id; 390 bus_dma_tag_t ifl_buf_tag; 391 iflib_dma_info_t ifl_ifdi; 392 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 393 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 394 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 395 } __aligned(CACHE_LINE_SIZE); 396 397 static inline qidx_t 398 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 399 { 400 qidx_t used; 401 402 if (pidx > cidx) 403 used = pidx - cidx; 404 else if (pidx < cidx) 405 used = size - cidx + pidx; 406 else if (gen == 0 && pidx == cidx) 407 used = 0; 408 else if (gen == 1 && pidx == cidx) 409 used = size; 410 else 411 panic("bad state"); 412 413 return (used); 414 } 415 416 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 417 418 #define IDXDIFF(head, tail, wrap) \ 419 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 420 421 struct iflib_rxq { 422 if_ctx_t ifr_ctx; 423 iflib_fl_t ifr_fl; 424 uint64_t ifr_rx_irq; 425 struct pfil_head *pfil; 426 /* 427 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 428 * the command queue consumer index. Otherwise it's unused. 429 */ 430 qidx_t ifr_cq_cidx; 431 uint16_t ifr_id; 432 uint8_t ifr_nfl; 433 uint8_t ifr_ntxqirq; 434 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 435 uint8_t ifr_fl_offset; 436 struct lro_ctrl ifr_lc; 437 struct grouptask ifr_task; 438 struct iflib_filter_info ifr_filter_info; 439 iflib_dma_info_t ifr_ifdi; 440 441 /* dynamically allocate if any drivers need a value substantially larger than this */ 442 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 443 #ifdef IFLIB_DIAGNOSTICS 444 uint64_t ifr_cpu_exec_count[256]; 445 #endif 446 } __aligned(CACHE_LINE_SIZE); 447 448 typedef struct if_rxsd { 449 caddr_t *ifsd_cl; 450 iflib_fl_t ifsd_fl; 451 qidx_t ifsd_cidx; 452 } *if_rxsd_t; 453 454 /* multiple of word size */ 455 #ifdef __LP64__ 456 #define PKT_INFO_SIZE 6 457 #define RXD_INFO_SIZE 5 458 #define PKT_TYPE uint64_t 459 #else 460 #define PKT_INFO_SIZE 11 461 #define RXD_INFO_SIZE 8 462 #define PKT_TYPE uint32_t 463 #endif 464 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 465 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 466 467 typedef struct if_pkt_info_pad { 468 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 469 } *if_pkt_info_pad_t; 470 typedef struct if_rxd_info_pad { 471 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 472 } *if_rxd_info_pad_t; 473 474 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 475 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 476 477 478 static inline void 479 pkt_info_zero(if_pkt_info_t pi) 480 { 481 if_pkt_info_pad_t pi_pad; 482 483 pi_pad = (if_pkt_info_pad_t)pi; 484 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 485 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 486 #ifndef __LP64__ 487 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 488 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 489 #endif 490 } 491 492 static device_method_t iflib_pseudo_methods[] = { 493 DEVMETHOD(device_attach, noop_attach), 494 DEVMETHOD(device_detach, iflib_pseudo_detach), 495 DEVMETHOD_END 496 }; 497 498 driver_t iflib_pseudodriver = { 499 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 500 }; 501 502 static inline void 503 rxd_info_zero(if_rxd_info_t ri) 504 { 505 if_rxd_info_pad_t ri_pad; 506 int i; 507 508 ri_pad = (if_rxd_info_pad_t)ri; 509 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 510 ri_pad->rxd_val[i] = 0; 511 ri_pad->rxd_val[i+1] = 0; 512 ri_pad->rxd_val[i+2] = 0; 513 ri_pad->rxd_val[i+3] = 0; 514 } 515 #ifdef __LP64__ 516 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 517 #endif 518 } 519 520 /* 521 * Only allow a single packet to take up most 1/nth of the tx ring 522 */ 523 #define MAX_SINGLE_PACKET_FRACTION 12 524 #define IF_BAD_DMA (bus_addr_t)-1 525 526 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 527 528 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 529 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 530 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 531 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 532 533 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 534 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 535 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 536 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 537 538 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 539 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 540 541 void 542 iflib_set_detach(if_ctx_t ctx) 543 { 544 STATE_LOCK(ctx); 545 ctx->ifc_flags |= IFC_IN_DETACH; 546 STATE_UNLOCK(ctx); 547 } 548 549 /* Our boot-time initialization hook */ 550 static int iflib_module_event_handler(module_t, int, void *); 551 552 static moduledata_t iflib_moduledata = { 553 "iflib", 554 iflib_module_event_handler, 555 NULL 556 }; 557 558 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 559 MODULE_VERSION(iflib, 1); 560 561 MODULE_DEPEND(iflib, pci, 1, 1, 1); 562 MODULE_DEPEND(iflib, ether, 1, 1, 1); 563 564 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 565 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 566 567 #ifndef IFLIB_DEBUG_COUNTERS 568 #ifdef INVARIANTS 569 #define IFLIB_DEBUG_COUNTERS 1 570 #else 571 #define IFLIB_DEBUG_COUNTERS 0 572 #endif /* !INVARIANTS */ 573 #endif 574 575 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 576 "iflib driver parameters"); 577 578 /* 579 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 580 */ 581 static int iflib_min_tx_latency = 0; 582 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 583 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 584 static int iflib_no_tx_batch = 0; 585 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 586 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 587 588 589 #if IFLIB_DEBUG_COUNTERS 590 591 static int iflib_tx_seen; 592 static int iflib_tx_sent; 593 static int iflib_tx_encap; 594 static int iflib_rx_allocs; 595 static int iflib_fl_refills; 596 static int iflib_fl_refills_large; 597 static int iflib_tx_frees; 598 599 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 600 &iflib_tx_seen, 0, "# TX mbufs seen"); 601 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 602 &iflib_tx_sent, 0, "# TX mbufs sent"); 603 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 604 &iflib_tx_encap, 0, "# TX mbufs encapped"); 605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 606 &iflib_tx_frees, 0, "# TX frees"); 607 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 608 &iflib_rx_allocs, 0, "# RX allocations"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 610 &iflib_fl_refills, 0, "# refills"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 612 &iflib_fl_refills_large, 0, "# large refills"); 613 614 615 static int iflib_txq_drain_flushing; 616 static int iflib_txq_drain_oactive; 617 static int iflib_txq_drain_notready; 618 619 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 620 &iflib_txq_drain_flushing, 0, "# drain flushes"); 621 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 622 &iflib_txq_drain_oactive, 0, "# drain oactives"); 623 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 624 &iflib_txq_drain_notready, 0, "# drain notready"); 625 626 627 static int iflib_encap_load_mbuf_fail; 628 static int iflib_encap_pad_mbuf_fail; 629 static int iflib_encap_txq_avail_fail; 630 static int iflib_encap_txd_encap_fail; 631 632 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 633 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 634 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 635 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 637 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 638 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 639 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 640 641 static int iflib_task_fn_rxs; 642 static int iflib_rx_intr_enables; 643 static int iflib_fast_intrs; 644 static int iflib_rx_unavail; 645 static int iflib_rx_ctx_inactive; 646 static int iflib_rx_if_input; 647 static int iflib_rxd_flush; 648 649 static int iflib_verbose_debug; 650 651 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 652 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 653 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 654 &iflib_rx_intr_enables, 0, "# RX intr enables"); 655 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 656 &iflib_fast_intrs, 0, "# fast_intr calls"); 657 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 658 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 660 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 662 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 664 &iflib_rxd_flush, 0, "# times rxd_flush called"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 666 &iflib_verbose_debug, 0, "enable verbose debugging"); 667 668 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 669 static void 670 iflib_debug_reset(void) 671 { 672 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 673 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 674 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 675 iflib_txq_drain_notready = 676 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 677 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 678 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 679 iflib_rx_unavail = 680 iflib_rx_ctx_inactive = iflib_rx_if_input = 681 iflib_rxd_flush = 0; 682 } 683 684 #else 685 #define DBG_COUNTER_INC(name) 686 static void iflib_debug_reset(void) {} 687 #endif 688 689 #define IFLIB_DEBUG 0 690 691 static void iflib_tx_structures_free(if_ctx_t ctx); 692 static void iflib_rx_structures_free(if_ctx_t ctx); 693 static int iflib_queues_alloc(if_ctx_t ctx); 694 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 695 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 696 static int iflib_qset_structures_setup(if_ctx_t ctx); 697 static int iflib_msix_init(if_ctx_t ctx); 698 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 699 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 700 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 701 #ifdef ALTQ 702 static void iflib_altq_if_start(if_t ifp); 703 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 704 #endif 705 static int iflib_register(if_ctx_t); 706 static void iflib_init_locked(if_ctx_t ctx); 707 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 708 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 709 static void iflib_ifmp_purge(iflib_txq_t txq); 710 static void _iflib_pre_assert(if_softc_ctx_t scctx); 711 static void iflib_if_init_locked(if_ctx_t ctx); 712 static void iflib_free_intr_mem(if_ctx_t ctx); 713 #ifndef __NO_STRICT_ALIGNMENT 714 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 715 #endif 716 717 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 718 SLIST_HEAD_INITIALIZER(cpu_offsets); 719 struct cpu_offset { 720 SLIST_ENTRY(cpu_offset) entries; 721 cpuset_t set; 722 unsigned int refcount; 723 uint16_t offset; 724 }; 725 static struct mtx cpu_offset_mtx; 726 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 727 MTX_DEF); 728 729 NETDUMP_DEFINE(iflib); 730 731 #ifdef DEV_NETMAP 732 #include <sys/selinfo.h> 733 #include <net/netmap.h> 734 #include <dev/netmap/netmap_kern.h> 735 736 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 737 738 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 739 740 /* 741 * device-specific sysctl variables: 742 * 743 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 744 * During regular operations the CRC is stripped, but on some 745 * hardware reception of frames not multiple of 64 is slower, 746 * so using crcstrip=0 helps in benchmarks. 747 * 748 * iflib_rx_miss, iflib_rx_miss_bufs: 749 * count packets that might be missed due to lost interrupts. 750 */ 751 SYSCTL_DECL(_dev_netmap); 752 /* 753 * The xl driver by default strips CRCs and we do not override it. 754 */ 755 756 int iflib_crcstrip = 1; 757 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 758 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 759 760 int iflib_rx_miss, iflib_rx_miss_bufs; 761 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 762 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 763 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 764 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 765 766 /* 767 * Register/unregister. We are already under netmap lock. 768 * Only called on the first register or the last unregister. 769 */ 770 static int 771 iflib_netmap_register(struct netmap_adapter *na, int onoff) 772 { 773 if_t ifp = na->ifp; 774 if_ctx_t ctx = ifp->if_softc; 775 int status; 776 777 CTX_LOCK(ctx); 778 IFDI_INTR_DISABLE(ctx); 779 780 /* Tell the stack that the interface is no longer active */ 781 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 782 783 if (!CTX_IS_VF(ctx)) 784 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 785 786 /* enable or disable flags and callbacks in na and ifp */ 787 if (onoff) { 788 nm_set_native_flags(na); 789 } else { 790 nm_clear_native_flags(na); 791 } 792 iflib_stop(ctx); 793 iflib_init_locked(ctx); 794 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 795 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 796 if (status) 797 nm_clear_native_flags(na); 798 CTX_UNLOCK(ctx); 799 return (status); 800 } 801 802 static int 803 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 804 { 805 struct netmap_adapter *na = kring->na; 806 u_int const lim = kring->nkr_num_slots - 1; 807 u_int head = kring->rhead; 808 struct netmap_ring *ring = kring->ring; 809 bus_dmamap_t *map; 810 struct if_rxd_update iru; 811 if_ctx_t ctx = rxq->ifr_ctx; 812 iflib_fl_t fl = &rxq->ifr_fl[0]; 813 uint32_t refill_pidx, nic_i; 814 #if IFLIB_DEBUG_COUNTERS 815 int rf_count = 0; 816 #endif 817 818 if (nm_i == head && __predict_true(!init)) 819 return 0; 820 iru_init(&iru, rxq, 0 /* flid */); 821 map = fl->ifl_sds.ifsd_map; 822 refill_pidx = netmap_idx_k2n(kring, nm_i); 823 /* 824 * IMPORTANT: we must leave one free slot in the ring, 825 * so move head back by one unit 826 */ 827 head = nm_prev(head, lim); 828 nic_i = UINT_MAX; 829 DBG_COUNTER_INC(fl_refills); 830 while (nm_i != head) { 831 #if IFLIB_DEBUG_COUNTERS 832 if (++rf_count == 9) 833 DBG_COUNTER_INC(fl_refills_large); 834 #endif 835 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 836 struct netmap_slot *slot = &ring->slot[nm_i]; 837 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 838 uint32_t nic_i_dma = refill_pidx; 839 nic_i = netmap_idx_k2n(kring, nm_i); 840 841 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 842 843 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 844 return netmap_ring_reinit(kring); 845 846 fl->ifl_vm_addrs[tmp_pidx] = addr; 847 if (__predict_false(init)) { 848 netmap_load_map(na, fl->ifl_buf_tag, 849 map[nic_i], addr); 850 } else if (slot->flags & NS_BUF_CHANGED) { 851 /* buffer has changed, reload map */ 852 netmap_reload_map(na, fl->ifl_buf_tag, 853 map[nic_i], addr); 854 } 855 slot->flags &= ~NS_BUF_CHANGED; 856 857 nm_i = nm_next(nm_i, lim); 858 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 859 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 860 continue; 861 862 iru.iru_pidx = refill_pidx; 863 iru.iru_count = tmp_pidx+1; 864 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 865 refill_pidx = nic_i; 866 for (int n = 0; n < iru.iru_count; n++) { 867 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma], 868 BUS_DMASYNC_PREREAD); 869 /* XXX - change this to not use the netmap func*/ 870 nic_i_dma = nm_next(nic_i_dma, lim); 871 } 872 } 873 } 874 kring->nr_hwcur = head; 875 876 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 877 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 878 if (__predict_true(nic_i != UINT_MAX)) { 879 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 880 DBG_COUNTER_INC(rxd_flush); 881 } 882 return (0); 883 } 884 885 /* 886 * Reconcile kernel and user view of the transmit ring. 887 * 888 * All information is in the kring. 889 * Userspace wants to send packets up to the one before kring->rhead, 890 * kernel knows kring->nr_hwcur is the first unsent packet. 891 * 892 * Here we push packets out (as many as possible), and possibly 893 * reclaim buffers from previously completed transmission. 894 * 895 * The caller (netmap) guarantees that there is only one instance 896 * running at any time. Any interference with other driver 897 * methods should be handled by the individual drivers. 898 */ 899 static int 900 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 901 { 902 struct netmap_adapter *na = kring->na; 903 if_t ifp = na->ifp; 904 struct netmap_ring *ring = kring->ring; 905 u_int nm_i; /* index into the netmap kring */ 906 u_int nic_i; /* index into the NIC ring */ 907 u_int n; 908 u_int const lim = kring->nkr_num_slots - 1; 909 u_int const head = kring->rhead; 910 struct if_pkt_info pi; 911 912 /* 913 * interrupts on every tx packet are expensive so request 914 * them every half ring, or where NS_REPORT is set 915 */ 916 u_int report_frequency = kring->nkr_num_slots >> 1; 917 /* device-specific */ 918 if_ctx_t ctx = ifp->if_softc; 919 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 920 921 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 922 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 923 924 /* 925 * First part: process new packets to send. 926 * nm_i is the current index in the netmap kring, 927 * nic_i is the corresponding index in the NIC ring. 928 * 929 * If we have packets to send (nm_i != head) 930 * iterate over the netmap ring, fetch length and update 931 * the corresponding slot in the NIC ring. Some drivers also 932 * need to update the buffer's physical address in the NIC slot 933 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 934 * 935 * The netmap_reload_map() calls is especially expensive, 936 * even when (as in this case) the tag is 0, so do only 937 * when the buffer has actually changed. 938 * 939 * If possible do not set the report/intr bit on all slots, 940 * but only a few times per ring or when NS_REPORT is set. 941 * 942 * Finally, on 10G and faster drivers, it might be useful 943 * to prefetch the next slot and txr entry. 944 */ 945 946 nm_i = kring->nr_hwcur; 947 if (nm_i != head) { /* we have new packets to send */ 948 pkt_info_zero(&pi); 949 pi.ipi_segs = txq->ift_segs; 950 pi.ipi_qsidx = kring->ring_id; 951 nic_i = netmap_idx_k2n(kring, nm_i); 952 953 __builtin_prefetch(&ring->slot[nm_i]); 954 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 955 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 956 957 for (n = 0; nm_i != head; n++) { 958 struct netmap_slot *slot = &ring->slot[nm_i]; 959 u_int len = slot->len; 960 uint64_t paddr; 961 void *addr = PNMB(na, slot, &paddr); 962 int flags = (slot->flags & NS_REPORT || 963 nic_i == 0 || nic_i == report_frequency) ? 964 IPI_TX_INTR : 0; 965 966 /* device-specific */ 967 pi.ipi_len = len; 968 pi.ipi_segs[0].ds_addr = paddr; 969 pi.ipi_segs[0].ds_len = len; 970 pi.ipi_nsegs = 1; 971 pi.ipi_ndescs = 0; 972 pi.ipi_pidx = nic_i; 973 pi.ipi_flags = flags; 974 975 /* Fill the slot in the NIC ring. */ 976 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 977 DBG_COUNTER_INC(tx_encap); 978 979 /* prefetch for next round */ 980 __builtin_prefetch(&ring->slot[nm_i + 1]); 981 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 982 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 983 984 NM_CHECK_ADDR_LEN(na, addr, len); 985 986 if (slot->flags & NS_BUF_CHANGED) { 987 /* buffer has changed, reload map */ 988 netmap_reload_map(na, txq->ift_buf_tag, 989 txq->ift_sds.ifsd_map[nic_i], addr); 990 } 991 /* make sure changes to the buffer are synced */ 992 bus_dmamap_sync(txq->ift_buf_tag, 993 txq->ift_sds.ifsd_map[nic_i], 994 BUS_DMASYNC_PREWRITE); 995 996 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 997 nm_i = nm_next(nm_i, lim); 998 nic_i = nm_next(nic_i, lim); 999 } 1000 kring->nr_hwcur = nm_i; 1001 1002 /* synchronize the NIC ring */ 1003 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1004 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1005 1006 /* (re)start the tx unit up to slot nic_i (excluded) */ 1007 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1008 } 1009 1010 /* 1011 * Second part: reclaim buffers for completed transmissions. 1012 * 1013 * If there are unclaimed buffers, attempt to reclaim them. 1014 * If none are reclaimed, and TX IRQs are not in use, do an initial 1015 * minimal delay, then trigger the tx handler which will spin in the 1016 * group task queue. 1017 */ 1018 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1019 if (iflib_tx_credits_update(ctx, txq)) { 1020 /* some tx completed, increment avail */ 1021 nic_i = txq->ift_cidx_processed; 1022 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1023 } 1024 } 1025 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1026 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1027 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1028 iflib_timer, txq, txq->ift_timer.c_cpu); 1029 } 1030 return (0); 1031 } 1032 1033 /* 1034 * Reconcile kernel and user view of the receive ring. 1035 * Same as for the txsync, this routine must be efficient. 1036 * The caller guarantees a single invocations, but races against 1037 * the rest of the driver should be handled here. 1038 * 1039 * On call, kring->rhead is the first packet that userspace wants 1040 * to keep, and kring->rcur is the wakeup point. 1041 * The kernel has previously reported packets up to kring->rtail. 1042 * 1043 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1044 * of whether or not we received an interrupt. 1045 */ 1046 static int 1047 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1048 { 1049 struct netmap_adapter *na = kring->na; 1050 struct netmap_ring *ring = kring->ring; 1051 if_t ifp = na->ifp; 1052 iflib_fl_t fl; 1053 uint32_t nm_i; /* index into the netmap ring */ 1054 uint32_t nic_i; /* index into the NIC ring */ 1055 u_int i, n; 1056 u_int const lim = kring->nkr_num_slots - 1; 1057 u_int const head = kring->rhead; 1058 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1059 struct if_rxd_info ri; 1060 1061 if_ctx_t ctx = ifp->if_softc; 1062 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1063 if (head > lim) 1064 return netmap_ring_reinit(kring); 1065 1066 /* 1067 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far. 1068 */ 1069 1070 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1071 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1072 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1073 } 1074 1075 /* 1076 * First part: import newly received packets. 1077 * 1078 * nm_i is the index of the next free slot in the netmap ring, 1079 * nic_i is the index of the next received packet in the NIC ring, 1080 * and they may differ in case if_init() has been called while 1081 * in netmap mode. For the receive ring we have 1082 * 1083 * nic_i = rxr->next_check; 1084 * nm_i = kring->nr_hwtail (previous) 1085 * and 1086 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1087 * 1088 * rxr->next_check is set to 0 on a ring reinit 1089 */ 1090 if (netmap_no_pendintr || force_update) { 1091 int crclen = iflib_crcstrip ? 0 : 4; 1092 int error, avail; 1093 1094 for (i = 0; i < rxq->ifr_nfl; i++) { 1095 fl = &rxq->ifr_fl[i]; 1096 nic_i = fl->ifl_cidx; 1097 nm_i = netmap_idx_n2k(kring, nic_i); 1098 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1099 rxq->ifr_id, nic_i, USHRT_MAX); 1100 for (n = 0; avail > 0; n++, avail--) { 1101 rxd_info_zero(&ri); 1102 ri.iri_frags = rxq->ifr_frags; 1103 ri.iri_qsidx = kring->ring_id; 1104 ri.iri_ifp = ctx->ifc_ifp; 1105 ri.iri_cidx = nic_i; 1106 1107 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1108 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1109 ring->slot[nm_i].flags = 0; 1110 bus_dmamap_sync(fl->ifl_buf_tag, 1111 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1112 nm_i = nm_next(nm_i, lim); 1113 nic_i = nm_next(nic_i, lim); 1114 } 1115 if (n) { /* update the state variables */ 1116 if (netmap_no_pendintr && !force_update) { 1117 /* diagnostics */ 1118 iflib_rx_miss ++; 1119 iflib_rx_miss_bufs += n; 1120 } 1121 fl->ifl_cidx = nic_i; 1122 kring->nr_hwtail = nm_i; 1123 } 1124 kring->nr_kflags &= ~NKR_PENDINTR; 1125 } 1126 } 1127 /* 1128 * Second part: skip past packets that userspace has released. 1129 * (kring->nr_hwcur to head excluded), 1130 * and make the buffers available for reception. 1131 * As usual nm_i is the index in the netmap ring, 1132 * nic_i is the index in the NIC ring, and 1133 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1134 */ 1135 /* XXX not sure how this will work with multiple free lists */ 1136 nm_i = kring->nr_hwcur; 1137 1138 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1139 } 1140 1141 static void 1142 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1143 { 1144 if_ctx_t ctx = na->ifp->if_softc; 1145 1146 CTX_LOCK(ctx); 1147 if (onoff) { 1148 IFDI_INTR_ENABLE(ctx); 1149 } else { 1150 IFDI_INTR_DISABLE(ctx); 1151 } 1152 CTX_UNLOCK(ctx); 1153 } 1154 1155 1156 static int 1157 iflib_netmap_attach(if_ctx_t ctx) 1158 { 1159 struct netmap_adapter na; 1160 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1161 1162 bzero(&na, sizeof(na)); 1163 1164 na.ifp = ctx->ifc_ifp; 1165 na.na_flags = NAF_BDG_MAYSLEEP; 1166 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1167 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1168 1169 na.num_tx_desc = scctx->isc_ntxd[0]; 1170 na.num_rx_desc = scctx->isc_nrxd[0]; 1171 na.nm_txsync = iflib_netmap_txsync; 1172 na.nm_rxsync = iflib_netmap_rxsync; 1173 na.nm_register = iflib_netmap_register; 1174 na.nm_intr = iflib_netmap_intr; 1175 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1176 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1177 return (netmap_attach(&na)); 1178 } 1179 1180 static void 1181 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1182 { 1183 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1184 struct netmap_slot *slot; 1185 1186 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1187 if (slot == NULL) 1188 return; 1189 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1190 1191 /* 1192 * In netmap mode, set the map for the packet buffer. 1193 * NOTE: Some drivers (not this one) also need to set 1194 * the physical buffer address in the NIC ring. 1195 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1196 * netmap slot index, si 1197 */ 1198 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1199 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1200 NMB(na, slot + si)); 1201 } 1202 } 1203 1204 static void 1205 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1206 { 1207 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1208 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1209 struct netmap_slot *slot; 1210 uint32_t nm_i; 1211 1212 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1213 if (slot == NULL) 1214 return; 1215 nm_i = netmap_idx_n2k(kring, 0); 1216 netmap_fl_refill(rxq, kring, nm_i, true); 1217 } 1218 1219 static void 1220 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on) 1221 { 1222 struct netmap_kring *kring; 1223 uint16_t txqid; 1224 1225 txqid = txq->ift_id; 1226 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1227 1228 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1229 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1230 BUS_DMASYNC_POSTREAD); 1231 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1232 netmap_tx_irq(ctx->ifc_ifp, txqid); 1233 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1234 if (hz < 2000) 1235 *reset_on = 1; 1236 else 1237 *reset_on = hz / 1000; 1238 } 1239 } 1240 } 1241 1242 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1243 1244 #else 1245 #define iflib_netmap_txq_init(ctx, txq) 1246 #define iflib_netmap_rxq_init(ctx, rxq) 1247 #define iflib_netmap_detach(ifp) 1248 1249 #define iflib_netmap_attach(ctx) (0) 1250 #define netmap_rx_irq(ifp, qid, budget) (0) 1251 #define netmap_tx_irq(ifp, qid) do {} while (0) 1252 #define iflib_netmap_timer_adjust(ctx, txq, reset_on) 1253 1254 #endif 1255 1256 #if defined(__i386__) || defined(__amd64__) 1257 static __inline void 1258 prefetch(void *x) 1259 { 1260 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1261 } 1262 static __inline void 1263 prefetch2cachelines(void *x) 1264 { 1265 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1266 #if (CACHE_LINE_SIZE < 128) 1267 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1268 #endif 1269 } 1270 #else 1271 #define prefetch(x) 1272 #define prefetch2cachelines(x) 1273 #endif 1274 1275 static void 1276 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1277 { 1278 iflib_fl_t fl; 1279 1280 fl = &rxq->ifr_fl[flid]; 1281 iru->iru_paddrs = fl->ifl_bus_addrs; 1282 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1283 iru->iru_idxs = fl->ifl_rxd_idxs; 1284 iru->iru_qsidx = rxq->ifr_id; 1285 iru->iru_buf_size = fl->ifl_buf_size; 1286 iru->iru_flidx = fl->ifl_id; 1287 } 1288 1289 static void 1290 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1291 { 1292 if (err) 1293 return; 1294 *(bus_addr_t *) arg = segs[0].ds_addr; 1295 } 1296 1297 int 1298 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1299 { 1300 int err; 1301 device_t dev = ctx->ifc_dev; 1302 1303 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1304 align, 0, /* alignment, bounds */ 1305 BUS_SPACE_MAXADDR, /* lowaddr */ 1306 BUS_SPACE_MAXADDR, /* highaddr */ 1307 NULL, NULL, /* filter, filterarg */ 1308 size, /* maxsize */ 1309 1, /* nsegments */ 1310 size, /* maxsegsize */ 1311 BUS_DMA_ALLOCNOW, /* flags */ 1312 NULL, /* lockfunc */ 1313 NULL, /* lockarg */ 1314 &dma->idi_tag); 1315 if (err) { 1316 device_printf(dev, 1317 "%s: bus_dma_tag_create failed: %d\n", 1318 __func__, err); 1319 goto fail_0; 1320 } 1321 1322 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1323 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1324 if (err) { 1325 device_printf(dev, 1326 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1327 __func__, (uintmax_t)size, err); 1328 goto fail_1; 1329 } 1330 1331 dma->idi_paddr = IF_BAD_DMA; 1332 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1333 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1334 if (err || dma->idi_paddr == IF_BAD_DMA) { 1335 device_printf(dev, 1336 "%s: bus_dmamap_load failed: %d\n", 1337 __func__, err); 1338 goto fail_2; 1339 } 1340 1341 dma->idi_size = size; 1342 return (0); 1343 1344 fail_2: 1345 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1346 fail_1: 1347 bus_dma_tag_destroy(dma->idi_tag); 1348 fail_0: 1349 dma->idi_tag = NULL; 1350 1351 return (err); 1352 } 1353 1354 int 1355 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1356 { 1357 if_shared_ctx_t sctx = ctx->ifc_sctx; 1358 1359 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1360 1361 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1362 } 1363 1364 int 1365 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1366 { 1367 int i, err; 1368 iflib_dma_info_t *dmaiter; 1369 1370 dmaiter = dmalist; 1371 for (i = 0; i < count; i++, dmaiter++) { 1372 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1373 break; 1374 } 1375 if (err) 1376 iflib_dma_free_multi(dmalist, i); 1377 return (err); 1378 } 1379 1380 void 1381 iflib_dma_free(iflib_dma_info_t dma) 1382 { 1383 if (dma->idi_tag == NULL) 1384 return; 1385 if (dma->idi_paddr != IF_BAD_DMA) { 1386 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1387 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1388 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1389 dma->idi_paddr = IF_BAD_DMA; 1390 } 1391 if (dma->idi_vaddr != NULL) { 1392 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1393 dma->idi_vaddr = NULL; 1394 } 1395 bus_dma_tag_destroy(dma->idi_tag); 1396 dma->idi_tag = NULL; 1397 } 1398 1399 void 1400 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1401 { 1402 int i; 1403 iflib_dma_info_t *dmaiter = dmalist; 1404 1405 for (i = 0; i < count; i++, dmaiter++) 1406 iflib_dma_free(*dmaiter); 1407 } 1408 1409 #ifdef EARLY_AP_STARTUP 1410 static const int iflib_started = 1; 1411 #else 1412 /* 1413 * We used to abuse the smp_started flag to decide if the queues have been 1414 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1415 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1416 * is set. Run a SYSINIT() strictly after that to just set a usable 1417 * completion flag. 1418 */ 1419 1420 static int iflib_started; 1421 1422 static void 1423 iflib_record_started(void *arg) 1424 { 1425 iflib_started = 1; 1426 } 1427 1428 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1429 iflib_record_started, NULL); 1430 #endif 1431 1432 static int 1433 iflib_fast_intr(void *arg) 1434 { 1435 iflib_filter_info_t info = arg; 1436 struct grouptask *gtask = info->ifi_task; 1437 int result; 1438 1439 if (!iflib_started) 1440 return (FILTER_STRAY); 1441 1442 DBG_COUNTER_INC(fast_intrs); 1443 if (info->ifi_filter != NULL) { 1444 result = info->ifi_filter(info->ifi_filter_arg); 1445 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1446 return (result); 1447 } 1448 1449 GROUPTASK_ENQUEUE(gtask); 1450 return (FILTER_HANDLED); 1451 } 1452 1453 static int 1454 iflib_fast_intr_rxtx(void *arg) 1455 { 1456 iflib_filter_info_t info = arg; 1457 struct grouptask *gtask = info->ifi_task; 1458 if_ctx_t ctx; 1459 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1460 iflib_txq_t txq; 1461 void *sc; 1462 int i, cidx, result; 1463 qidx_t txqid; 1464 bool intr_enable, intr_legacy; 1465 1466 if (!iflib_started) 1467 return (FILTER_STRAY); 1468 1469 DBG_COUNTER_INC(fast_intrs); 1470 if (info->ifi_filter != NULL) { 1471 result = info->ifi_filter(info->ifi_filter_arg); 1472 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1473 return (result); 1474 } 1475 1476 ctx = rxq->ifr_ctx; 1477 sc = ctx->ifc_softc; 1478 intr_enable = false; 1479 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1480 MPASS(rxq->ifr_ntxqirq); 1481 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1482 txqid = rxq->ifr_txqid[i]; 1483 txq = &ctx->ifc_txqs[txqid]; 1484 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1485 BUS_DMASYNC_POSTREAD); 1486 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1487 if (intr_legacy) 1488 intr_enable = true; 1489 else 1490 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1491 continue; 1492 } 1493 GROUPTASK_ENQUEUE(&txq->ift_task); 1494 } 1495 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1496 cidx = rxq->ifr_cq_cidx; 1497 else 1498 cidx = rxq->ifr_fl[0].ifl_cidx; 1499 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1500 GROUPTASK_ENQUEUE(gtask); 1501 else { 1502 if (intr_legacy) 1503 intr_enable = true; 1504 else 1505 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1506 DBG_COUNTER_INC(rx_intr_enables); 1507 } 1508 if (intr_enable) 1509 IFDI_INTR_ENABLE(ctx); 1510 return (FILTER_HANDLED); 1511 } 1512 1513 1514 static int 1515 iflib_fast_intr_ctx(void *arg) 1516 { 1517 iflib_filter_info_t info = arg; 1518 struct grouptask *gtask = info->ifi_task; 1519 int result; 1520 1521 if (!iflib_started) 1522 return (FILTER_STRAY); 1523 1524 DBG_COUNTER_INC(fast_intrs); 1525 if (info->ifi_filter != NULL) { 1526 result = info->ifi_filter(info->ifi_filter_arg); 1527 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1528 return (result); 1529 } 1530 1531 GROUPTASK_ENQUEUE(gtask); 1532 return (FILTER_HANDLED); 1533 } 1534 1535 static int 1536 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1537 driver_filter_t filter, driver_intr_t handler, void *arg, 1538 const char *name) 1539 { 1540 int rc, flags; 1541 struct resource *res; 1542 void *tag = NULL; 1543 device_t dev = ctx->ifc_dev; 1544 1545 flags = RF_ACTIVE; 1546 if (ctx->ifc_flags & IFC_LEGACY) 1547 flags |= RF_SHAREABLE; 1548 MPASS(rid < 512); 1549 irq->ii_rid = rid; 1550 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1551 if (res == NULL) { 1552 device_printf(dev, 1553 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1554 return (ENOMEM); 1555 } 1556 irq->ii_res = res; 1557 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1558 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1559 filter, handler, arg, &tag); 1560 if (rc != 0) { 1561 device_printf(dev, 1562 "failed to setup interrupt for rid %d, name %s: %d\n", 1563 rid, name ? name : "unknown", rc); 1564 return (rc); 1565 } else if (name) 1566 bus_describe_intr(dev, res, tag, "%s", name); 1567 1568 irq->ii_tag = tag; 1569 return (0); 1570 } 1571 1572 1573 /********************************************************************* 1574 * 1575 * Allocate DMA resources for TX buffers as well as memory for the TX 1576 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1577 * iflib_sw_tx_desc_array structure, storing all the information that 1578 * is needed to transmit a packet on the wire. This is called only 1579 * once at attach, setup is done every reset. 1580 * 1581 **********************************************************************/ 1582 static int 1583 iflib_txsd_alloc(iflib_txq_t txq) 1584 { 1585 if_ctx_t ctx = txq->ift_ctx; 1586 if_shared_ctx_t sctx = ctx->ifc_sctx; 1587 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1588 device_t dev = ctx->ifc_dev; 1589 bus_size_t tsomaxsize; 1590 int err, nsegments, ntsosegments; 1591 bool tso; 1592 1593 nsegments = scctx->isc_tx_nsegments; 1594 ntsosegments = scctx->isc_tx_tso_segments_max; 1595 tsomaxsize = scctx->isc_tx_tso_size_max; 1596 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1597 tsomaxsize += sizeof(struct ether_vlan_header); 1598 MPASS(scctx->isc_ntxd[0] > 0); 1599 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1600 MPASS(nsegments > 0); 1601 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1602 MPASS(ntsosegments > 0); 1603 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1604 } 1605 1606 /* 1607 * Set up DMA tags for TX buffers. 1608 */ 1609 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1610 1, 0, /* alignment, bounds */ 1611 BUS_SPACE_MAXADDR, /* lowaddr */ 1612 BUS_SPACE_MAXADDR, /* highaddr */ 1613 NULL, NULL, /* filter, filterarg */ 1614 sctx->isc_tx_maxsize, /* maxsize */ 1615 nsegments, /* nsegments */ 1616 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1617 0, /* flags */ 1618 NULL, /* lockfunc */ 1619 NULL, /* lockfuncarg */ 1620 &txq->ift_buf_tag))) { 1621 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1622 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1623 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1624 goto fail; 1625 } 1626 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1627 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1628 1, 0, /* alignment, bounds */ 1629 BUS_SPACE_MAXADDR, /* lowaddr */ 1630 BUS_SPACE_MAXADDR, /* highaddr */ 1631 NULL, NULL, /* filter, filterarg */ 1632 tsomaxsize, /* maxsize */ 1633 ntsosegments, /* nsegments */ 1634 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1635 0, /* flags */ 1636 NULL, /* lockfunc */ 1637 NULL, /* lockfuncarg */ 1638 &txq->ift_tso_buf_tag))) { 1639 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1640 err); 1641 goto fail; 1642 } 1643 1644 /* Allocate memory for the TX mbuf map. */ 1645 if (!(txq->ift_sds.ifsd_m = 1646 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1647 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1648 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1649 err = ENOMEM; 1650 goto fail; 1651 } 1652 1653 /* 1654 * Create the DMA maps for TX buffers. 1655 */ 1656 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1657 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1658 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1659 device_printf(dev, 1660 "Unable to allocate TX buffer DMA map memory\n"); 1661 err = ENOMEM; 1662 goto fail; 1663 } 1664 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1665 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1666 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1667 device_printf(dev, 1668 "Unable to allocate TSO TX buffer map memory\n"); 1669 err = ENOMEM; 1670 goto fail; 1671 } 1672 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1673 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1674 &txq->ift_sds.ifsd_map[i]); 1675 if (err != 0) { 1676 device_printf(dev, "Unable to create TX DMA map\n"); 1677 goto fail; 1678 } 1679 if (!tso) 1680 continue; 1681 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1682 &txq->ift_sds.ifsd_tso_map[i]); 1683 if (err != 0) { 1684 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1685 goto fail; 1686 } 1687 } 1688 return (0); 1689 fail: 1690 /* We free all, it handles case where we are in the middle */ 1691 iflib_tx_structures_free(ctx); 1692 return (err); 1693 } 1694 1695 static void 1696 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1697 { 1698 bus_dmamap_t map; 1699 1700 map = NULL; 1701 if (txq->ift_sds.ifsd_map != NULL) 1702 map = txq->ift_sds.ifsd_map[i]; 1703 if (map != NULL) { 1704 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1705 bus_dmamap_unload(txq->ift_buf_tag, map); 1706 bus_dmamap_destroy(txq->ift_buf_tag, map); 1707 txq->ift_sds.ifsd_map[i] = NULL; 1708 } 1709 1710 map = NULL; 1711 if (txq->ift_sds.ifsd_tso_map != NULL) 1712 map = txq->ift_sds.ifsd_tso_map[i]; 1713 if (map != NULL) { 1714 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1715 BUS_DMASYNC_POSTWRITE); 1716 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1717 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1718 txq->ift_sds.ifsd_tso_map[i] = NULL; 1719 } 1720 } 1721 1722 static void 1723 iflib_txq_destroy(iflib_txq_t txq) 1724 { 1725 if_ctx_t ctx = txq->ift_ctx; 1726 1727 for (int i = 0; i < txq->ift_size; i++) 1728 iflib_txsd_destroy(ctx, txq, i); 1729 if (txq->ift_sds.ifsd_map != NULL) { 1730 free(txq->ift_sds.ifsd_map, M_IFLIB); 1731 txq->ift_sds.ifsd_map = NULL; 1732 } 1733 if (txq->ift_sds.ifsd_tso_map != NULL) { 1734 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1735 txq->ift_sds.ifsd_tso_map = NULL; 1736 } 1737 if (txq->ift_sds.ifsd_m != NULL) { 1738 free(txq->ift_sds.ifsd_m, M_IFLIB); 1739 txq->ift_sds.ifsd_m = NULL; 1740 } 1741 if (txq->ift_buf_tag != NULL) { 1742 bus_dma_tag_destroy(txq->ift_buf_tag); 1743 txq->ift_buf_tag = NULL; 1744 } 1745 if (txq->ift_tso_buf_tag != NULL) { 1746 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1747 txq->ift_tso_buf_tag = NULL; 1748 } 1749 } 1750 1751 static void 1752 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1753 { 1754 struct mbuf **mp; 1755 1756 mp = &txq->ift_sds.ifsd_m[i]; 1757 if (*mp == NULL) 1758 return; 1759 1760 if (txq->ift_sds.ifsd_map != NULL) { 1761 bus_dmamap_sync(txq->ift_buf_tag, 1762 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1763 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1764 } 1765 if (txq->ift_sds.ifsd_tso_map != NULL) { 1766 bus_dmamap_sync(txq->ift_tso_buf_tag, 1767 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1768 bus_dmamap_unload(txq->ift_tso_buf_tag, 1769 txq->ift_sds.ifsd_tso_map[i]); 1770 } 1771 m_free(*mp); 1772 DBG_COUNTER_INC(tx_frees); 1773 *mp = NULL; 1774 } 1775 1776 static int 1777 iflib_txq_setup(iflib_txq_t txq) 1778 { 1779 if_ctx_t ctx = txq->ift_ctx; 1780 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1781 if_shared_ctx_t sctx = ctx->ifc_sctx; 1782 iflib_dma_info_t di; 1783 int i; 1784 1785 /* Set number of descriptors available */ 1786 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1787 /* XXX make configurable */ 1788 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1789 1790 /* Reset indices */ 1791 txq->ift_cidx_processed = 0; 1792 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1793 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1794 1795 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1796 bzero((void *)di->idi_vaddr, di->idi_size); 1797 1798 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1799 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1800 bus_dmamap_sync(di->idi_tag, di->idi_map, 1801 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1802 return (0); 1803 } 1804 1805 /********************************************************************* 1806 * 1807 * Allocate DMA resources for RX buffers as well as memory for the RX 1808 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1809 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1810 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1811 * Since we use use one entry in iflib_sw_rx_desc_array per received 1812 * packet, the maximum number of entries we'll need is equal to the 1813 * number of hardware receive descriptors that we've allocated. 1814 * 1815 **********************************************************************/ 1816 static int 1817 iflib_rxsd_alloc(iflib_rxq_t rxq) 1818 { 1819 if_ctx_t ctx = rxq->ifr_ctx; 1820 if_shared_ctx_t sctx = ctx->ifc_sctx; 1821 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1822 device_t dev = ctx->ifc_dev; 1823 iflib_fl_t fl; 1824 int err; 1825 1826 MPASS(scctx->isc_nrxd[0] > 0); 1827 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1828 1829 fl = rxq->ifr_fl; 1830 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1831 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1832 /* Set up DMA tag for RX buffers. */ 1833 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1834 1, 0, /* alignment, bounds */ 1835 BUS_SPACE_MAXADDR, /* lowaddr */ 1836 BUS_SPACE_MAXADDR, /* highaddr */ 1837 NULL, NULL, /* filter, filterarg */ 1838 sctx->isc_rx_maxsize, /* maxsize */ 1839 sctx->isc_rx_nsegments, /* nsegments */ 1840 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1841 0, /* flags */ 1842 NULL, /* lockfunc */ 1843 NULL, /* lockarg */ 1844 &fl->ifl_buf_tag); 1845 if (err) { 1846 device_printf(dev, 1847 "Unable to allocate RX DMA tag: %d\n", err); 1848 goto fail; 1849 } 1850 1851 /* Allocate memory for the RX mbuf map. */ 1852 if (!(fl->ifl_sds.ifsd_m = 1853 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1854 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1855 device_printf(dev, 1856 "Unable to allocate RX mbuf map memory\n"); 1857 err = ENOMEM; 1858 goto fail; 1859 } 1860 1861 /* Allocate memory for the direct RX cluster pointer map. */ 1862 if (!(fl->ifl_sds.ifsd_cl = 1863 (caddr_t *) malloc(sizeof(caddr_t) * 1864 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1865 device_printf(dev, 1866 "Unable to allocate RX cluster map memory\n"); 1867 err = ENOMEM; 1868 goto fail; 1869 } 1870 1871 /* Allocate memory for the RX cluster bus address map. */ 1872 if (!(fl->ifl_sds.ifsd_ba = 1873 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1874 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1875 device_printf(dev, 1876 "Unable to allocate RX bus address map memory\n"); 1877 err = ENOMEM; 1878 goto fail; 1879 } 1880 1881 /* 1882 * Create the DMA maps for RX buffers. 1883 */ 1884 if (!(fl->ifl_sds.ifsd_map = 1885 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1886 device_printf(dev, 1887 "Unable to allocate RX buffer DMA map memory\n"); 1888 err = ENOMEM; 1889 goto fail; 1890 } 1891 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1892 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1893 &fl->ifl_sds.ifsd_map[i]); 1894 if (err != 0) { 1895 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1896 goto fail; 1897 } 1898 } 1899 } 1900 return (0); 1901 1902 fail: 1903 iflib_rx_structures_free(ctx); 1904 return (err); 1905 } 1906 1907 1908 /* 1909 * Internal service routines 1910 */ 1911 1912 struct rxq_refill_cb_arg { 1913 int error; 1914 bus_dma_segment_t seg; 1915 int nseg; 1916 }; 1917 1918 static void 1919 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1920 { 1921 struct rxq_refill_cb_arg *cb_arg = arg; 1922 1923 cb_arg->error = error; 1924 cb_arg->seg = segs[0]; 1925 cb_arg->nseg = nseg; 1926 } 1927 1928 /** 1929 * _iflib_fl_refill - refill an rxq free-buffer list 1930 * @ctx: the iflib context 1931 * @fl: the free list to refill 1932 * @count: the number of new buffers to allocate 1933 * 1934 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 1935 * The caller must assure that @count does not exceed the queue's capacity. 1936 */ 1937 static void 1938 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1939 { 1940 struct if_rxd_update iru; 1941 struct rxq_refill_cb_arg cb_arg; 1942 struct mbuf *m; 1943 caddr_t cl, *sd_cl; 1944 struct mbuf **sd_m; 1945 bus_dmamap_t *sd_map; 1946 bus_addr_t bus_addr, *sd_ba; 1947 int err, frag_idx, i, idx, n, pidx; 1948 qidx_t credits; 1949 1950 sd_m = fl->ifl_sds.ifsd_m; 1951 sd_map = fl->ifl_sds.ifsd_map; 1952 sd_cl = fl->ifl_sds.ifsd_cl; 1953 sd_ba = fl->ifl_sds.ifsd_ba; 1954 pidx = fl->ifl_pidx; 1955 idx = pidx; 1956 frag_idx = fl->ifl_fragidx; 1957 credits = fl->ifl_credits; 1958 1959 i = 0; 1960 n = count; 1961 MPASS(n > 0); 1962 MPASS(credits + n <= fl->ifl_size); 1963 1964 if (pidx < fl->ifl_cidx) 1965 MPASS(pidx + n <= fl->ifl_cidx); 1966 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1967 MPASS(fl->ifl_gen == 0); 1968 if (pidx > fl->ifl_cidx) 1969 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1970 1971 DBG_COUNTER_INC(fl_refills); 1972 if (n > 8) 1973 DBG_COUNTER_INC(fl_refills_large); 1974 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1975 while (n--) { 1976 /* 1977 * We allocate an uninitialized mbuf + cluster, mbuf is 1978 * initialized after rx. 1979 * 1980 * If the cluster is still set then we know a minimum sized packet was received 1981 */ 1982 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 1983 &frag_idx); 1984 if (frag_idx < 0) 1985 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1986 MPASS(frag_idx >= 0); 1987 if ((cl = sd_cl[frag_idx]) == NULL) { 1988 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1989 break; 1990 1991 cb_arg.error = 0; 1992 MPASS(sd_map != NULL); 1993 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 1994 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 1995 BUS_DMA_NOWAIT); 1996 if (err != 0 || cb_arg.error) { 1997 /* 1998 * !zone_pack ? 1999 */ 2000 if (fl->ifl_zone == zone_pack) 2001 uma_zfree(fl->ifl_zone, cl); 2002 break; 2003 } 2004 2005 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2006 sd_cl[frag_idx] = cl; 2007 #if MEMORY_LOGGING 2008 fl->ifl_cl_enqueued++; 2009 #endif 2010 } else { 2011 bus_addr = sd_ba[frag_idx]; 2012 } 2013 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2014 BUS_DMASYNC_PREREAD); 2015 2016 if (sd_m[frag_idx] == NULL) { 2017 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 2018 break; 2019 } 2020 sd_m[frag_idx] = m; 2021 } 2022 bit_set(fl->ifl_rx_bitmap, frag_idx); 2023 #if MEMORY_LOGGING 2024 fl->ifl_m_enqueued++; 2025 #endif 2026 2027 DBG_COUNTER_INC(rx_allocs); 2028 fl->ifl_rxd_idxs[i] = frag_idx; 2029 fl->ifl_bus_addrs[i] = bus_addr; 2030 fl->ifl_vm_addrs[i] = cl; 2031 credits++; 2032 i++; 2033 MPASS(credits <= fl->ifl_size); 2034 if (++idx == fl->ifl_size) { 2035 fl->ifl_gen = 1; 2036 idx = 0; 2037 } 2038 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2039 iru.iru_pidx = pidx; 2040 iru.iru_count = i; 2041 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2042 i = 0; 2043 pidx = idx; 2044 fl->ifl_pidx = idx; 2045 fl->ifl_credits = credits; 2046 } 2047 } 2048 2049 if (i) { 2050 iru.iru_pidx = pidx; 2051 iru.iru_count = i; 2052 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2053 fl->ifl_pidx = idx; 2054 fl->ifl_credits = credits; 2055 } 2056 DBG_COUNTER_INC(rxd_flush); 2057 if (fl->ifl_pidx == 0) 2058 pidx = fl->ifl_size - 1; 2059 else 2060 pidx = fl->ifl_pidx - 1; 2061 2062 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2063 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2064 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2065 fl->ifl_fragidx = frag_idx; 2066 } 2067 2068 static __inline void 2069 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2070 { 2071 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2072 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2073 #ifdef INVARIANTS 2074 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2075 #endif 2076 2077 MPASS(fl->ifl_credits <= fl->ifl_size); 2078 MPASS(reclaimable == delta); 2079 2080 if (reclaimable > 0) 2081 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2082 } 2083 2084 uint8_t 2085 iflib_in_detach(if_ctx_t ctx) 2086 { 2087 bool in_detach; 2088 2089 STATE_LOCK(ctx); 2090 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2091 STATE_UNLOCK(ctx); 2092 return (in_detach); 2093 } 2094 2095 static void 2096 iflib_fl_bufs_free(iflib_fl_t fl) 2097 { 2098 iflib_dma_info_t idi = fl->ifl_ifdi; 2099 bus_dmamap_t sd_map; 2100 uint32_t i; 2101 2102 for (i = 0; i < fl->ifl_size; i++) { 2103 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2104 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2105 2106 if (*sd_cl != NULL) { 2107 sd_map = fl->ifl_sds.ifsd_map[i]; 2108 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2109 BUS_DMASYNC_POSTREAD); 2110 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2111 if (*sd_cl != NULL) 2112 uma_zfree(fl->ifl_zone, *sd_cl); 2113 // XXX: Should this get moved out? 2114 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx)) 2115 bus_dmamap_destroy(fl->ifl_buf_tag, sd_map); 2116 if (*sd_m != NULL) { 2117 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2118 uma_zfree(zone_mbuf, *sd_m); 2119 } 2120 } else { 2121 MPASS(*sd_cl == NULL); 2122 MPASS(*sd_m == NULL); 2123 } 2124 #if MEMORY_LOGGING 2125 fl->ifl_m_dequeued++; 2126 fl->ifl_cl_dequeued++; 2127 #endif 2128 *sd_cl = NULL; 2129 *sd_m = NULL; 2130 } 2131 #ifdef INVARIANTS 2132 for (i = 0; i < fl->ifl_size; i++) { 2133 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2134 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2135 } 2136 #endif 2137 /* 2138 * Reset free list values 2139 */ 2140 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2141 bzero(idi->idi_vaddr, idi->idi_size); 2142 } 2143 2144 /********************************************************************* 2145 * 2146 * Initialize a free list and its buffers. 2147 * 2148 **********************************************************************/ 2149 static int 2150 iflib_fl_setup(iflib_fl_t fl) 2151 { 2152 iflib_rxq_t rxq = fl->ifl_rxq; 2153 if_ctx_t ctx = rxq->ifr_ctx; 2154 2155 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2156 /* 2157 ** Free current RX buffer structs and their mbufs 2158 */ 2159 iflib_fl_bufs_free(fl); 2160 /* Now replenish the mbufs */ 2161 MPASS(fl->ifl_credits == 0); 2162 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2163 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2164 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2165 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2166 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2167 2168 2169 /* avoid pre-allocating zillions of clusters to an idle card 2170 * potentially speeding up attach 2171 */ 2172 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2173 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2174 if (min(128, fl->ifl_size) != fl->ifl_credits) 2175 return (ENOBUFS); 2176 /* 2177 * handle failure 2178 */ 2179 MPASS(rxq != NULL); 2180 MPASS(fl->ifl_ifdi != NULL); 2181 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2182 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2183 return (0); 2184 } 2185 2186 /********************************************************************* 2187 * 2188 * Free receive ring data structures 2189 * 2190 **********************************************************************/ 2191 static void 2192 iflib_rx_sds_free(iflib_rxq_t rxq) 2193 { 2194 iflib_fl_t fl; 2195 int i, j; 2196 2197 if (rxq->ifr_fl != NULL) { 2198 for (i = 0; i < rxq->ifr_nfl; i++) { 2199 fl = &rxq->ifr_fl[i]; 2200 if (fl->ifl_buf_tag != NULL) { 2201 if (fl->ifl_sds.ifsd_map != NULL) { 2202 for (j = 0; j < fl->ifl_size; j++) { 2203 if (fl->ifl_sds.ifsd_map[j] == 2204 NULL) 2205 continue; 2206 bus_dmamap_sync( 2207 fl->ifl_buf_tag, 2208 fl->ifl_sds.ifsd_map[j], 2209 BUS_DMASYNC_POSTREAD); 2210 bus_dmamap_unload( 2211 fl->ifl_buf_tag, 2212 fl->ifl_sds.ifsd_map[j]); 2213 } 2214 } 2215 bus_dma_tag_destroy(fl->ifl_buf_tag); 2216 fl->ifl_buf_tag = NULL; 2217 } 2218 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2219 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2220 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2221 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2222 fl->ifl_sds.ifsd_m = NULL; 2223 fl->ifl_sds.ifsd_cl = NULL; 2224 fl->ifl_sds.ifsd_ba = NULL; 2225 fl->ifl_sds.ifsd_map = NULL; 2226 } 2227 free(rxq->ifr_fl, M_IFLIB); 2228 rxq->ifr_fl = NULL; 2229 rxq->ifr_cq_cidx = 0; 2230 } 2231 } 2232 2233 /* 2234 * Timer routine 2235 */ 2236 static void 2237 iflib_timer(void *arg) 2238 { 2239 iflib_txq_t txq = arg; 2240 if_ctx_t ctx = txq->ift_ctx; 2241 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2242 uint64_t this_tick = ticks; 2243 uint32_t reset_on = hz / 2; 2244 2245 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2246 return; 2247 2248 /* 2249 ** Check on the state of the TX queue(s), this 2250 ** can be done without the lock because its RO 2251 ** and the HUNG state will be static if set. 2252 */ 2253 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2254 txq->ift_last_timer_tick = this_tick; 2255 IFDI_TIMER(ctx, txq->ift_id); 2256 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2257 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2258 (sctx->isc_pause_frames == 0))) 2259 goto hung; 2260 2261 if (ifmp_ring_is_stalled(txq->ift_br)) 2262 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2263 txq->ift_cleaned_prev = txq->ift_cleaned; 2264 } 2265 #ifdef DEV_NETMAP 2266 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2267 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 2268 #endif 2269 /* handle any laggards */ 2270 if (txq->ift_db_pending) 2271 GROUPTASK_ENQUEUE(&txq->ift_task); 2272 2273 sctx->isc_pause_frames = 0; 2274 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2275 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2276 return; 2277 2278 hung: 2279 device_printf(ctx->ifc_dev, 2280 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2281 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2282 STATE_LOCK(ctx); 2283 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2284 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2285 iflib_admin_intr_deferred(ctx); 2286 STATE_UNLOCK(ctx); 2287 } 2288 2289 static void 2290 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2291 { 2292 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2293 2294 /* 2295 * XXX don't set the max_frame_size to larger 2296 * than the hardware can handle 2297 */ 2298 if (sctx->isc_max_frame_size <= MCLBYTES) 2299 ctx->ifc_rx_mbuf_sz = MCLBYTES; 2300 else 2301 ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE; 2302 } 2303 2304 uint32_t 2305 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2306 { 2307 2308 return (ctx->ifc_rx_mbuf_sz); 2309 } 2310 2311 static void 2312 iflib_init_locked(if_ctx_t ctx) 2313 { 2314 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2315 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2316 if_t ifp = ctx->ifc_ifp; 2317 iflib_fl_t fl; 2318 iflib_txq_t txq; 2319 iflib_rxq_t rxq; 2320 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2321 2322 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2323 IFDI_INTR_DISABLE(ctx); 2324 2325 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2326 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2327 /* Set hardware offload abilities */ 2328 if_clearhwassist(ifp); 2329 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2330 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2331 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2332 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2333 if (if_getcapenable(ifp) & IFCAP_TSO4) 2334 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2335 if (if_getcapenable(ifp) & IFCAP_TSO6) 2336 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2337 2338 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2339 CALLOUT_LOCK(txq); 2340 callout_stop(&txq->ift_timer); 2341 CALLOUT_UNLOCK(txq); 2342 iflib_netmap_txq_init(ctx, txq); 2343 } 2344 2345 /* 2346 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2347 * that drivers can use the value when setting up the hardware receive 2348 * buffers. 2349 */ 2350 iflib_calc_rx_mbuf_sz(ctx); 2351 2352 #ifdef INVARIANTS 2353 i = if_getdrvflags(ifp); 2354 #endif 2355 IFDI_INIT(ctx); 2356 MPASS(if_getdrvflags(ifp) == i); 2357 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2358 /* XXX this should really be done on a per-queue basis */ 2359 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2360 MPASS(rxq->ifr_id == i); 2361 iflib_netmap_rxq_init(ctx, rxq); 2362 continue; 2363 } 2364 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2365 if (iflib_fl_setup(fl)) { 2366 device_printf(ctx->ifc_dev, 2367 "setting up free list %d failed - " 2368 "check cluster settings\n", j); 2369 goto done; 2370 } 2371 } 2372 } 2373 done: 2374 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2375 IFDI_INTR_ENABLE(ctx); 2376 txq = ctx->ifc_txqs; 2377 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2378 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2379 txq->ift_timer.c_cpu); 2380 } 2381 2382 static int 2383 iflib_media_change(if_t ifp) 2384 { 2385 if_ctx_t ctx = if_getsoftc(ifp); 2386 int err; 2387 2388 CTX_LOCK(ctx); 2389 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2390 iflib_init_locked(ctx); 2391 CTX_UNLOCK(ctx); 2392 return (err); 2393 } 2394 2395 static void 2396 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2397 { 2398 if_ctx_t ctx = if_getsoftc(ifp); 2399 2400 CTX_LOCK(ctx); 2401 IFDI_UPDATE_ADMIN_STATUS(ctx); 2402 IFDI_MEDIA_STATUS(ctx, ifmr); 2403 CTX_UNLOCK(ctx); 2404 } 2405 2406 void 2407 iflib_stop(if_ctx_t ctx) 2408 { 2409 iflib_txq_t txq = ctx->ifc_txqs; 2410 iflib_rxq_t rxq = ctx->ifc_rxqs; 2411 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2412 if_shared_ctx_t sctx = ctx->ifc_sctx; 2413 iflib_dma_info_t di; 2414 iflib_fl_t fl; 2415 int i, j; 2416 2417 /* Tell the stack that the interface is no longer active */ 2418 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2419 2420 IFDI_INTR_DISABLE(ctx); 2421 DELAY(1000); 2422 IFDI_STOP(ctx); 2423 DELAY(1000); 2424 2425 iflib_debug_reset(); 2426 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2427 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2428 /* make sure all transmitters have completed before proceeding XXX */ 2429 2430 CALLOUT_LOCK(txq); 2431 callout_stop(&txq->ift_timer); 2432 CALLOUT_UNLOCK(txq); 2433 2434 /* clean any enqueued buffers */ 2435 iflib_ifmp_purge(txq); 2436 /* Free any existing tx buffers. */ 2437 for (j = 0; j < txq->ift_size; j++) { 2438 iflib_txsd_free(ctx, txq, j); 2439 } 2440 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2441 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2442 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2443 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2444 txq->ift_pullups = 0; 2445 ifmp_ring_reset_stats(txq->ift_br); 2446 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2447 bzero((void *)di->idi_vaddr, di->idi_size); 2448 } 2449 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2450 /* make sure all transmitters have completed before proceeding XXX */ 2451 2452 rxq->ifr_cq_cidx = 0; 2453 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2454 bzero((void *)di->idi_vaddr, di->idi_size); 2455 /* also resets the free lists pidx/cidx */ 2456 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2457 iflib_fl_bufs_free(fl); 2458 } 2459 } 2460 2461 static inline caddr_t 2462 calc_next_rxd(iflib_fl_t fl, int cidx) 2463 { 2464 qidx_t size; 2465 int nrxd; 2466 caddr_t start, end, cur, next; 2467 2468 nrxd = fl->ifl_size; 2469 size = fl->ifl_rxd_size; 2470 start = fl->ifl_ifdi->idi_vaddr; 2471 2472 if (__predict_false(size == 0)) 2473 return (start); 2474 cur = start + size*cidx; 2475 end = start + size*nrxd; 2476 next = CACHE_PTR_NEXT(cur); 2477 return (next < end ? next : start); 2478 } 2479 2480 static inline void 2481 prefetch_pkts(iflib_fl_t fl, int cidx) 2482 { 2483 int nextptr; 2484 int nrxd = fl->ifl_size; 2485 caddr_t next_rxd; 2486 2487 2488 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2489 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2490 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2491 next_rxd = calc_next_rxd(fl, cidx); 2492 prefetch(next_rxd); 2493 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2494 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2495 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2496 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2497 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2498 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2499 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2500 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2501 } 2502 2503 static struct mbuf * 2504 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2505 int *pf_rv, if_rxd_info_t ri) 2506 { 2507 bus_dmamap_t map; 2508 iflib_fl_t fl; 2509 caddr_t payload; 2510 struct mbuf *m; 2511 int flid, cidx, len, next; 2512 2513 map = NULL; 2514 flid = irf->irf_flid; 2515 cidx = irf->irf_idx; 2516 fl = &rxq->ifr_fl[flid]; 2517 sd->ifsd_fl = fl; 2518 sd->ifsd_cidx = cidx; 2519 m = fl->ifl_sds.ifsd_m[cidx]; 2520 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2521 fl->ifl_credits--; 2522 #if MEMORY_LOGGING 2523 fl->ifl_m_dequeued++; 2524 #endif 2525 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2526 prefetch_pkts(fl, cidx); 2527 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2528 prefetch(&fl->ifl_sds.ifsd_map[next]); 2529 map = fl->ifl_sds.ifsd_map[cidx]; 2530 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2531 2532 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2533 MPASS(fl->ifl_cidx == cidx); 2534 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2535 2536 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL) { 2537 payload = *sd->ifsd_cl; 2538 payload += ri->iri_pad; 2539 len = ri->iri_len - ri->iri_pad; 2540 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2541 len | PFIL_MEMPTR | PFIL_IN, NULL); 2542 switch (*pf_rv) { 2543 case PFIL_DROPPED: 2544 case PFIL_CONSUMED: 2545 /* 2546 * The filter ate it. Everything is recycled. 2547 */ 2548 m = NULL; 2549 unload = 0; 2550 break; 2551 case PFIL_REALLOCED: 2552 /* 2553 * The filter copied it. Everything is recycled. 2554 */ 2555 m = pfil_mem2mbuf(payload); 2556 unload = 0; 2557 break; 2558 case PFIL_PASS: 2559 /* 2560 * Filter said it was OK, so receive like 2561 * normal 2562 */ 2563 fl->ifl_sds.ifsd_m[cidx] = NULL; 2564 break; 2565 default: 2566 MPASS(0); 2567 } 2568 } else { 2569 fl->ifl_sds.ifsd_m[cidx] = NULL; 2570 *pf_rv = PFIL_PASS; 2571 } 2572 2573 if (unload) 2574 bus_dmamap_unload(fl->ifl_buf_tag, map); 2575 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2576 if (__predict_false(fl->ifl_cidx == 0)) 2577 fl->ifl_gen = 0; 2578 bit_clear(fl->ifl_rx_bitmap, cidx); 2579 return (m); 2580 } 2581 2582 static struct mbuf * 2583 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2584 { 2585 struct mbuf *m, *mh, *mt; 2586 caddr_t cl; 2587 int *pf_rv_ptr, flags, i, padlen; 2588 bool consumed; 2589 2590 i = 0; 2591 mh = NULL; 2592 consumed = false; 2593 *pf_rv = PFIL_PASS; 2594 pf_rv_ptr = pf_rv; 2595 do { 2596 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2597 pf_rv_ptr, ri); 2598 2599 MPASS(*sd->ifsd_cl != NULL); 2600 2601 /* 2602 * Exclude zero-length frags & frags from 2603 * packets the filter has consumed or dropped 2604 */ 2605 if (ri->iri_frags[i].irf_len == 0 || consumed || 2606 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2607 if (mh == NULL) { 2608 /* everything saved here */ 2609 consumed = true; 2610 pf_rv_ptr = NULL; 2611 continue; 2612 } 2613 /* XXX we can save the cluster here, but not the mbuf */ 2614 m_init(m, M_NOWAIT, MT_DATA, 0); 2615 m_free(m); 2616 continue; 2617 } 2618 if (mh == NULL) { 2619 flags = M_PKTHDR|M_EXT; 2620 mh = mt = m; 2621 padlen = ri->iri_pad; 2622 } else { 2623 flags = M_EXT; 2624 mt->m_next = m; 2625 mt = m; 2626 /* assuming padding is only on the first fragment */ 2627 padlen = 0; 2628 } 2629 cl = *sd->ifsd_cl; 2630 *sd->ifsd_cl = NULL; 2631 2632 /* Can these two be made one ? */ 2633 m_init(m, M_NOWAIT, MT_DATA, flags); 2634 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2635 /* 2636 * These must follow m_init and m_cljset 2637 */ 2638 m->m_data += padlen; 2639 ri->iri_len -= padlen; 2640 m->m_len = ri->iri_frags[i].irf_len; 2641 } while (++i < ri->iri_nfrags); 2642 2643 return (mh); 2644 } 2645 2646 /* 2647 * Process one software descriptor 2648 */ 2649 static struct mbuf * 2650 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2651 { 2652 struct if_rxsd sd; 2653 struct mbuf *m; 2654 int pf_rv; 2655 2656 /* should I merge this back in now that the two paths are basically duplicated? */ 2657 if (ri->iri_nfrags == 1 && 2658 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2659 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2660 &pf_rv, ri); 2661 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2662 return (m); 2663 if (pf_rv == PFIL_PASS) { 2664 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2665 #ifndef __NO_STRICT_ALIGNMENT 2666 if (!IP_ALIGNED(m)) 2667 m->m_data += 2; 2668 #endif 2669 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2670 m->m_len = ri->iri_frags[0].irf_len; 2671 } 2672 } else { 2673 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2674 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2675 return (m); 2676 } 2677 m->m_pkthdr.len = ri->iri_len; 2678 m->m_pkthdr.rcvif = ri->iri_ifp; 2679 m->m_flags |= ri->iri_flags; 2680 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2681 m->m_pkthdr.flowid = ri->iri_flowid; 2682 M_HASHTYPE_SET(m, ri->iri_rsstype); 2683 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2684 m->m_pkthdr.csum_data = ri->iri_csum_data; 2685 return (m); 2686 } 2687 2688 #if defined(INET6) || defined(INET) 2689 static void 2690 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2691 { 2692 CURVNET_SET(lc->ifp->if_vnet); 2693 #if defined(INET6) 2694 *v6 = VNET(ip6_forwarding); 2695 #endif 2696 #if defined(INET) 2697 *v4 = VNET(ipforwarding); 2698 #endif 2699 CURVNET_RESTORE(); 2700 } 2701 2702 /* 2703 * Returns true if it's possible this packet could be LROed. 2704 * if it returns false, it is guaranteed that tcp_lro_rx() 2705 * would not return zero. 2706 */ 2707 static bool 2708 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2709 { 2710 struct ether_header *eh; 2711 uint16_t eh_type; 2712 2713 eh = mtod(m, struct ether_header *); 2714 eh_type = ntohs(eh->ether_type); 2715 switch (eh_type) { 2716 #if defined(INET6) 2717 case ETHERTYPE_IPV6: 2718 return !v6_forwarding; 2719 #endif 2720 #if defined (INET) 2721 case ETHERTYPE_IP: 2722 return !v4_forwarding; 2723 #endif 2724 } 2725 2726 return false; 2727 } 2728 #else 2729 static void 2730 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2731 { 2732 } 2733 #endif 2734 2735 static bool 2736 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2737 { 2738 if_t ifp; 2739 if_ctx_t ctx = rxq->ifr_ctx; 2740 if_shared_ctx_t sctx = ctx->ifc_sctx; 2741 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2742 int avail, i; 2743 qidx_t *cidxp; 2744 struct if_rxd_info ri; 2745 int err, budget_left, rx_bytes, rx_pkts; 2746 iflib_fl_t fl; 2747 int lro_enabled; 2748 bool v4_forwarding, v6_forwarding, lro_possible; 2749 2750 /* 2751 * XXX early demux data packets so that if_input processing only handles 2752 * acks in interrupt context 2753 */ 2754 struct mbuf *m, *mh, *mt, *mf; 2755 2756 lro_possible = v4_forwarding = v6_forwarding = false; 2757 ifp = ctx->ifc_ifp; 2758 mh = mt = NULL; 2759 MPASS(budget > 0); 2760 rx_pkts = rx_bytes = 0; 2761 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2762 cidxp = &rxq->ifr_cq_cidx; 2763 else 2764 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2765 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2766 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2767 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2768 DBG_COUNTER_INC(rx_unavail); 2769 return (false); 2770 } 2771 2772 /* pfil needs the vnet to be set */ 2773 CURVNET_SET_QUIET(ifp->if_vnet); 2774 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2775 if (__predict_false(!CTX_ACTIVE(ctx))) { 2776 DBG_COUNTER_INC(rx_ctx_inactive); 2777 break; 2778 } 2779 /* 2780 * Reset client set fields to their default values 2781 */ 2782 rxd_info_zero(&ri); 2783 ri.iri_qsidx = rxq->ifr_id; 2784 ri.iri_cidx = *cidxp; 2785 ri.iri_ifp = ifp; 2786 ri.iri_frags = rxq->ifr_frags; 2787 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2788 2789 if (err) 2790 goto err; 2791 rx_pkts += 1; 2792 rx_bytes += ri.iri_len; 2793 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2794 *cidxp = ri.iri_cidx; 2795 /* Update our consumer index */ 2796 /* XXX NB: shurd - check if this is still safe */ 2797 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2798 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2799 /* was this only a completion queue message? */ 2800 if (__predict_false(ri.iri_nfrags == 0)) 2801 continue; 2802 } 2803 MPASS(ri.iri_nfrags != 0); 2804 MPASS(ri.iri_len != 0); 2805 2806 /* will advance the cidx on the corresponding free lists */ 2807 m = iflib_rxd_pkt_get(rxq, &ri); 2808 avail--; 2809 budget_left--; 2810 if (avail == 0 && budget_left) 2811 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2812 2813 if (__predict_false(m == NULL)) 2814 continue; 2815 2816 /* imm_pkt: -- cxgb */ 2817 if (mh == NULL) 2818 mh = mt = m; 2819 else { 2820 mt->m_nextpkt = m; 2821 mt = m; 2822 } 2823 } 2824 CURVNET_RESTORE(); 2825 /* make sure that we can refill faster than drain */ 2826 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2827 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2828 2829 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2830 if (lro_enabled) 2831 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2832 mt = mf = NULL; 2833 while (mh != NULL) { 2834 m = mh; 2835 mh = mh->m_nextpkt; 2836 m->m_nextpkt = NULL; 2837 #ifndef __NO_STRICT_ALIGNMENT 2838 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2839 continue; 2840 #endif 2841 rx_bytes += m->m_pkthdr.len; 2842 rx_pkts++; 2843 #if defined(INET6) || defined(INET) 2844 if (lro_enabled) { 2845 if (!lro_possible) { 2846 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2847 if (lro_possible && mf != NULL) { 2848 ifp->if_input(ifp, mf); 2849 DBG_COUNTER_INC(rx_if_input); 2850 mt = mf = NULL; 2851 } 2852 } 2853 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2854 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2855 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2856 continue; 2857 } 2858 } 2859 #endif 2860 if (lro_possible) { 2861 ifp->if_input(ifp, m); 2862 DBG_COUNTER_INC(rx_if_input); 2863 continue; 2864 } 2865 2866 if (mf == NULL) 2867 mf = m; 2868 if (mt != NULL) 2869 mt->m_nextpkt = m; 2870 mt = m; 2871 } 2872 if (mf != NULL) { 2873 ifp->if_input(ifp, mf); 2874 DBG_COUNTER_INC(rx_if_input); 2875 } 2876 2877 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2878 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2879 2880 /* 2881 * Flush any outstanding LRO work 2882 */ 2883 #if defined(INET6) || defined(INET) 2884 tcp_lro_flush_all(&rxq->ifr_lc); 2885 #endif 2886 if (avail) 2887 return true; 2888 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2889 err: 2890 STATE_LOCK(ctx); 2891 ctx->ifc_flags |= IFC_DO_RESET; 2892 iflib_admin_intr_deferred(ctx); 2893 STATE_UNLOCK(ctx); 2894 return (false); 2895 } 2896 2897 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2898 static inline qidx_t 2899 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2900 { 2901 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2902 qidx_t minthresh = txq->ift_size / 8; 2903 if (in_use > 4*minthresh) 2904 return (notify_count); 2905 if (in_use > 2*minthresh) 2906 return (notify_count >> 1); 2907 if (in_use > minthresh) 2908 return (notify_count >> 3); 2909 return (0); 2910 } 2911 2912 static inline qidx_t 2913 txq_max_rs_deferred(iflib_txq_t txq) 2914 { 2915 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2916 qidx_t minthresh = txq->ift_size / 8; 2917 if (txq->ift_in_use > 4*minthresh) 2918 return (notify_count); 2919 if (txq->ift_in_use > 2*minthresh) 2920 return (notify_count >> 1); 2921 if (txq->ift_in_use > minthresh) 2922 return (notify_count >> 2); 2923 return (2); 2924 } 2925 2926 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2927 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2928 2929 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2930 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2931 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2932 2933 /* forward compatibility for cxgb */ 2934 #define FIRST_QSET(ctx) 0 2935 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2936 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2937 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2938 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2939 2940 /* XXX we should be setting this to something other than zero */ 2941 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2942 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2943 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2944 2945 static inline bool 2946 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2947 { 2948 qidx_t dbval, max; 2949 bool rang; 2950 2951 rang = false; 2952 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2953 if (ring || txq->ift_db_pending >= max) { 2954 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2955 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 2956 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2957 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2958 txq->ift_db_pending = txq->ift_npending = 0; 2959 rang = true; 2960 } 2961 return (rang); 2962 } 2963 2964 #ifdef PKT_DEBUG 2965 static void 2966 print_pkt(if_pkt_info_t pi) 2967 { 2968 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2969 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2970 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2971 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2972 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2973 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2974 } 2975 #endif 2976 2977 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2978 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2979 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2980 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2981 2982 static int 2983 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2984 { 2985 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2986 struct ether_vlan_header *eh; 2987 struct mbuf *m; 2988 2989 m = *mp; 2990 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2991 M_WRITABLE(m) == 0) { 2992 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2993 return (ENOMEM); 2994 } else { 2995 m_freem(*mp); 2996 DBG_COUNTER_INC(tx_frees); 2997 *mp = m; 2998 } 2999 } 3000 3001 /* 3002 * Determine where frame payload starts. 3003 * Jump over vlan headers if already present, 3004 * helpful for QinQ too. 3005 */ 3006 if (__predict_false(m->m_len < sizeof(*eh))) { 3007 txq->ift_pullups++; 3008 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3009 return (ENOMEM); 3010 } 3011 eh = mtod(m, struct ether_vlan_header *); 3012 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3013 pi->ipi_etype = ntohs(eh->evl_proto); 3014 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3015 } else { 3016 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3017 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3018 } 3019 3020 switch (pi->ipi_etype) { 3021 #ifdef INET 3022 case ETHERTYPE_IP: 3023 { 3024 struct mbuf *n; 3025 struct ip *ip = NULL; 3026 struct tcphdr *th = NULL; 3027 int minthlen; 3028 3029 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3030 if (__predict_false(m->m_len < minthlen)) { 3031 /* 3032 * if this code bloat is causing too much of a hit 3033 * move it to a separate function and mark it noinline 3034 */ 3035 if (m->m_len == pi->ipi_ehdrlen) { 3036 n = m->m_next; 3037 MPASS(n); 3038 if (n->m_len >= sizeof(*ip)) { 3039 ip = (struct ip *)n->m_data; 3040 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3041 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3042 } else { 3043 txq->ift_pullups++; 3044 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3045 return (ENOMEM); 3046 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3047 } 3048 } else { 3049 txq->ift_pullups++; 3050 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3051 return (ENOMEM); 3052 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3053 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3054 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3055 } 3056 } else { 3057 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3058 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3059 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3060 } 3061 pi->ipi_ip_hlen = ip->ip_hl << 2; 3062 pi->ipi_ipproto = ip->ip_p; 3063 pi->ipi_flags |= IPI_TX_IPV4; 3064 3065 /* TCP checksum offload may require TCP header length */ 3066 if (IS_TX_OFFLOAD4(pi)) { 3067 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3068 if (__predict_false(th == NULL)) { 3069 txq->ift_pullups++; 3070 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3071 return (ENOMEM); 3072 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3073 } 3074 pi->ipi_tcp_hflags = th->th_flags; 3075 pi->ipi_tcp_hlen = th->th_off << 2; 3076 pi->ipi_tcp_seq = th->th_seq; 3077 } 3078 if (IS_TSO4(pi)) { 3079 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3080 return (ENXIO); 3081 /* 3082 * TSO always requires hardware checksum offload. 3083 */ 3084 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3085 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3086 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3087 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3088 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3089 ip->ip_sum = 0; 3090 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3091 } 3092 } 3093 } 3094 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3095 ip->ip_sum = 0; 3096 3097 break; 3098 } 3099 #endif 3100 #ifdef INET6 3101 case ETHERTYPE_IPV6: 3102 { 3103 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3104 struct tcphdr *th; 3105 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3106 3107 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3108 txq->ift_pullups++; 3109 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3110 return (ENOMEM); 3111 } 3112 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3113 3114 /* XXX-BZ this will go badly in case of ext hdrs. */ 3115 pi->ipi_ipproto = ip6->ip6_nxt; 3116 pi->ipi_flags |= IPI_TX_IPV6; 3117 3118 /* TCP checksum offload may require TCP header length */ 3119 if (IS_TX_OFFLOAD6(pi)) { 3120 if (pi->ipi_ipproto == IPPROTO_TCP) { 3121 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3122 txq->ift_pullups++; 3123 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3124 return (ENOMEM); 3125 } 3126 pi->ipi_tcp_hflags = th->th_flags; 3127 pi->ipi_tcp_hlen = th->th_off << 2; 3128 pi->ipi_tcp_seq = th->th_seq; 3129 } 3130 if (IS_TSO6(pi)) { 3131 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3132 return (ENXIO); 3133 /* 3134 * TSO always requires hardware checksum offload. 3135 */ 3136 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3137 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3138 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3139 } 3140 } 3141 break; 3142 } 3143 #endif 3144 default: 3145 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3146 pi->ipi_ip_hlen = 0; 3147 break; 3148 } 3149 *mp = m; 3150 3151 return (0); 3152 } 3153 3154 /* 3155 * If dodgy hardware rejects the scatter gather chain we've handed it 3156 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3157 * m_defrag'd mbufs 3158 */ 3159 static __noinline struct mbuf * 3160 iflib_remove_mbuf(iflib_txq_t txq) 3161 { 3162 int ntxd, pidx; 3163 struct mbuf *m, **ifsd_m; 3164 3165 ifsd_m = txq->ift_sds.ifsd_m; 3166 ntxd = txq->ift_size; 3167 pidx = txq->ift_pidx & (ntxd - 1); 3168 ifsd_m = txq->ift_sds.ifsd_m; 3169 m = ifsd_m[pidx]; 3170 ifsd_m[pidx] = NULL; 3171 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3172 if (txq->ift_sds.ifsd_tso_map != NULL) 3173 bus_dmamap_unload(txq->ift_tso_buf_tag, 3174 txq->ift_sds.ifsd_tso_map[pidx]); 3175 #if MEMORY_LOGGING 3176 txq->ift_dequeued++; 3177 #endif 3178 return (m); 3179 } 3180 3181 static inline caddr_t 3182 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3183 { 3184 qidx_t size; 3185 int ntxd; 3186 caddr_t start, end, cur, next; 3187 3188 ntxd = txq->ift_size; 3189 size = txq->ift_txd_size[qid]; 3190 start = txq->ift_ifdi[qid].idi_vaddr; 3191 3192 if (__predict_false(size == 0)) 3193 return (start); 3194 cur = start + size*cidx; 3195 end = start + size*ntxd; 3196 next = CACHE_PTR_NEXT(cur); 3197 return (next < end ? next : start); 3198 } 3199 3200 /* 3201 * Pad an mbuf to ensure a minimum ethernet frame size. 3202 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3203 */ 3204 static __noinline int 3205 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3206 { 3207 /* 3208 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3209 * and ARP message is the smallest common payload I can think of 3210 */ 3211 static char pad[18]; /* just zeros */ 3212 int n; 3213 struct mbuf *new_head; 3214 3215 if (!M_WRITABLE(*m_head)) { 3216 new_head = m_dup(*m_head, M_NOWAIT); 3217 if (new_head == NULL) { 3218 m_freem(*m_head); 3219 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3220 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3221 DBG_COUNTER_INC(tx_frees); 3222 return ENOMEM; 3223 } 3224 m_freem(*m_head); 3225 *m_head = new_head; 3226 } 3227 3228 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3229 n > 0; n -= sizeof(pad)) 3230 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3231 break; 3232 3233 if (n > 0) { 3234 m_freem(*m_head); 3235 device_printf(dev, "cannot pad short frame\n"); 3236 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3237 DBG_COUNTER_INC(tx_frees); 3238 return (ENOBUFS); 3239 } 3240 3241 return 0; 3242 } 3243 3244 static int 3245 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3246 { 3247 if_ctx_t ctx; 3248 if_shared_ctx_t sctx; 3249 if_softc_ctx_t scctx; 3250 bus_dma_tag_t buf_tag; 3251 bus_dma_segment_t *segs; 3252 struct mbuf *m_head, **ifsd_m; 3253 void *next_txd; 3254 bus_dmamap_t map; 3255 struct if_pkt_info pi; 3256 int remap = 0; 3257 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3258 3259 ctx = txq->ift_ctx; 3260 sctx = ctx->ifc_sctx; 3261 scctx = &ctx->ifc_softc_ctx; 3262 segs = txq->ift_segs; 3263 ntxd = txq->ift_size; 3264 m_head = *m_headp; 3265 map = NULL; 3266 3267 /* 3268 * If we're doing TSO the next descriptor to clean may be quite far ahead 3269 */ 3270 cidx = txq->ift_cidx; 3271 pidx = txq->ift_pidx; 3272 if (ctx->ifc_flags & IFC_PREFETCH) { 3273 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3274 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3275 next_txd = calc_next_txd(txq, cidx, 0); 3276 prefetch(next_txd); 3277 } 3278 3279 /* prefetch the next cache line of mbuf pointers and flags */ 3280 prefetch(&txq->ift_sds.ifsd_m[next]); 3281 prefetch(&txq->ift_sds.ifsd_map[next]); 3282 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3283 } 3284 map = txq->ift_sds.ifsd_map[pidx]; 3285 ifsd_m = txq->ift_sds.ifsd_m; 3286 3287 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3288 buf_tag = txq->ift_tso_buf_tag; 3289 max_segs = scctx->isc_tx_tso_segments_max; 3290 map = txq->ift_sds.ifsd_tso_map[pidx]; 3291 MPASS(buf_tag != NULL); 3292 MPASS(max_segs > 0); 3293 } else { 3294 buf_tag = txq->ift_buf_tag; 3295 max_segs = scctx->isc_tx_nsegments; 3296 map = txq->ift_sds.ifsd_map[pidx]; 3297 } 3298 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3299 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3300 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3301 if (err) { 3302 DBG_COUNTER_INC(encap_txd_encap_fail); 3303 return err; 3304 } 3305 } 3306 m_head = *m_headp; 3307 3308 pkt_info_zero(&pi); 3309 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3310 pi.ipi_pidx = pidx; 3311 pi.ipi_qsidx = txq->ift_id; 3312 pi.ipi_len = m_head->m_pkthdr.len; 3313 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3314 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3315 3316 /* deliberate bitwise OR to make one condition */ 3317 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3318 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3319 DBG_COUNTER_INC(encap_txd_encap_fail); 3320 return (err); 3321 } 3322 m_head = *m_headp; 3323 } 3324 3325 retry: 3326 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3327 BUS_DMA_NOWAIT); 3328 defrag: 3329 if (__predict_false(err)) { 3330 switch (err) { 3331 case EFBIG: 3332 /* try collapse once and defrag once */ 3333 if (remap == 0) { 3334 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3335 /* try defrag if collapsing fails */ 3336 if (m_head == NULL) 3337 remap++; 3338 } 3339 if (remap == 1) { 3340 txq->ift_mbuf_defrag++; 3341 m_head = m_defrag(*m_headp, M_NOWAIT); 3342 } 3343 /* 3344 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3345 * failed to map an mbuf that was run through m_defrag 3346 */ 3347 MPASS(remap <= 1); 3348 if (__predict_false(m_head == NULL || remap > 1)) 3349 goto defrag_failed; 3350 remap++; 3351 *m_headp = m_head; 3352 goto retry; 3353 break; 3354 case ENOMEM: 3355 txq->ift_no_tx_dma_setup++; 3356 break; 3357 default: 3358 txq->ift_no_tx_dma_setup++; 3359 m_freem(*m_headp); 3360 DBG_COUNTER_INC(tx_frees); 3361 *m_headp = NULL; 3362 break; 3363 } 3364 txq->ift_map_failed++; 3365 DBG_COUNTER_INC(encap_load_mbuf_fail); 3366 DBG_COUNTER_INC(encap_txd_encap_fail); 3367 return (err); 3368 } 3369 ifsd_m[pidx] = m_head; 3370 /* 3371 * XXX assumes a 1 to 1 relationship between segments and 3372 * descriptors - this does not hold true on all drivers, e.g. 3373 * cxgb 3374 */ 3375 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3376 txq->ift_no_desc_avail++; 3377 bus_dmamap_unload(buf_tag, map); 3378 DBG_COUNTER_INC(encap_txq_avail_fail); 3379 DBG_COUNTER_INC(encap_txd_encap_fail); 3380 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3381 GROUPTASK_ENQUEUE(&txq->ift_task); 3382 return (ENOBUFS); 3383 } 3384 /* 3385 * On Intel cards we can greatly reduce the number of TX interrupts 3386 * we see by only setting report status on every Nth descriptor. 3387 * However, this also means that the driver will need to keep track 3388 * of the descriptors that RS was set on to check them for the DD bit. 3389 */ 3390 txq->ift_rs_pending += nsegs + 1; 3391 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3392 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3393 pi.ipi_flags |= IPI_TX_INTR; 3394 txq->ift_rs_pending = 0; 3395 } 3396 3397 pi.ipi_segs = segs; 3398 pi.ipi_nsegs = nsegs; 3399 3400 MPASS(pidx >= 0 && pidx < txq->ift_size); 3401 #ifdef PKT_DEBUG 3402 print_pkt(&pi); 3403 #endif 3404 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3405 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3406 DBG_COUNTER_INC(tx_encap); 3407 MPASS(pi.ipi_new_pidx < txq->ift_size); 3408 3409 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3410 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3411 ndesc += txq->ift_size; 3412 txq->ift_gen = 1; 3413 } 3414 /* 3415 * drivers can need as many as 3416 * two sentinels 3417 */ 3418 MPASS(ndesc <= pi.ipi_nsegs + 2); 3419 MPASS(pi.ipi_new_pidx != pidx); 3420 MPASS(ndesc > 0); 3421 txq->ift_in_use += ndesc; 3422 3423 /* 3424 * We update the last software descriptor again here because there may 3425 * be a sentinel and/or there may be more mbufs than segments 3426 */ 3427 txq->ift_pidx = pi.ipi_new_pidx; 3428 txq->ift_npending += pi.ipi_ndescs; 3429 } else { 3430 *m_headp = m_head = iflib_remove_mbuf(txq); 3431 if (err == EFBIG) { 3432 txq->ift_txd_encap_efbig++; 3433 if (remap < 2) { 3434 remap = 1; 3435 goto defrag; 3436 } 3437 } 3438 goto defrag_failed; 3439 } 3440 /* 3441 * err can't possibly be non-zero here, so we don't neet to test it 3442 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3443 */ 3444 return (err); 3445 3446 defrag_failed: 3447 txq->ift_mbuf_defrag_failed++; 3448 txq->ift_map_failed++; 3449 m_freem(*m_headp); 3450 DBG_COUNTER_INC(tx_frees); 3451 *m_headp = NULL; 3452 DBG_COUNTER_INC(encap_txd_encap_fail); 3453 return (ENOMEM); 3454 } 3455 3456 static void 3457 iflib_tx_desc_free(iflib_txq_t txq, int n) 3458 { 3459 uint32_t qsize, cidx, mask, gen; 3460 struct mbuf *m, **ifsd_m; 3461 bool do_prefetch; 3462 3463 cidx = txq->ift_cidx; 3464 gen = txq->ift_gen; 3465 qsize = txq->ift_size; 3466 mask = qsize-1; 3467 ifsd_m = txq->ift_sds.ifsd_m; 3468 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3469 3470 while (n-- > 0) { 3471 if (do_prefetch) { 3472 prefetch(ifsd_m[(cidx + 3) & mask]); 3473 prefetch(ifsd_m[(cidx + 4) & mask]); 3474 } 3475 if ((m = ifsd_m[cidx]) != NULL) { 3476 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3477 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3478 bus_dmamap_sync(txq->ift_tso_buf_tag, 3479 txq->ift_sds.ifsd_tso_map[cidx], 3480 BUS_DMASYNC_POSTWRITE); 3481 bus_dmamap_unload(txq->ift_tso_buf_tag, 3482 txq->ift_sds.ifsd_tso_map[cidx]); 3483 } else { 3484 bus_dmamap_sync(txq->ift_buf_tag, 3485 txq->ift_sds.ifsd_map[cidx], 3486 BUS_DMASYNC_POSTWRITE); 3487 bus_dmamap_unload(txq->ift_buf_tag, 3488 txq->ift_sds.ifsd_map[cidx]); 3489 } 3490 /* XXX we don't support any drivers that batch packets yet */ 3491 MPASS(m->m_nextpkt == NULL); 3492 m_freem(m); 3493 ifsd_m[cidx] = NULL; 3494 #if MEMORY_LOGGING 3495 txq->ift_dequeued++; 3496 #endif 3497 DBG_COUNTER_INC(tx_frees); 3498 } 3499 if (__predict_false(++cidx == qsize)) { 3500 cidx = 0; 3501 gen = 0; 3502 } 3503 } 3504 txq->ift_cidx = cidx; 3505 txq->ift_gen = gen; 3506 } 3507 3508 static __inline int 3509 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3510 { 3511 int reclaim; 3512 if_ctx_t ctx = txq->ift_ctx; 3513 3514 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3515 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3516 3517 /* 3518 * Need a rate-limiting check so that this isn't called every time 3519 */ 3520 iflib_tx_credits_update(ctx, txq); 3521 reclaim = DESC_RECLAIMABLE(txq); 3522 3523 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3524 #ifdef INVARIANTS 3525 if (iflib_verbose_debug) { 3526 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3527 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3528 reclaim, thresh); 3529 3530 } 3531 #endif 3532 return (0); 3533 } 3534 iflib_tx_desc_free(txq, reclaim); 3535 txq->ift_cleaned += reclaim; 3536 txq->ift_in_use -= reclaim; 3537 3538 return (reclaim); 3539 } 3540 3541 static struct mbuf ** 3542 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3543 { 3544 int next, size; 3545 struct mbuf **items; 3546 3547 size = r->size; 3548 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3549 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3550 3551 prefetch(items[(cidx + offset) & (size-1)]); 3552 if (remaining > 1) { 3553 prefetch2cachelines(&items[next]); 3554 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3555 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3556 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3557 } 3558 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3559 } 3560 3561 static void 3562 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3563 { 3564 3565 ifmp_ring_check_drainage(txq->ift_br, budget); 3566 } 3567 3568 static uint32_t 3569 iflib_txq_can_drain(struct ifmp_ring *r) 3570 { 3571 iflib_txq_t txq = r->cookie; 3572 if_ctx_t ctx = txq->ift_ctx; 3573 3574 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3575 return (1); 3576 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3577 BUS_DMASYNC_POSTREAD); 3578 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3579 false)); 3580 } 3581 3582 static uint32_t 3583 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3584 { 3585 iflib_txq_t txq = r->cookie; 3586 if_ctx_t ctx = txq->ift_ctx; 3587 if_t ifp = ctx->ifc_ifp; 3588 struct mbuf **mp, *m; 3589 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3590 int reclaimed, err, in_use_prev, desc_used; 3591 bool do_prefetch, ring, rang; 3592 3593 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3594 !LINK_ACTIVE(ctx))) { 3595 DBG_COUNTER_INC(txq_drain_notready); 3596 return (0); 3597 } 3598 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3599 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3600 avail = IDXDIFF(pidx, cidx, r->size); 3601 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3602 DBG_COUNTER_INC(txq_drain_flushing); 3603 for (i = 0; i < avail; i++) { 3604 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3605 m_free(r->items[(cidx + i) & (r->size-1)]); 3606 r->items[(cidx + i) & (r->size-1)] = NULL; 3607 } 3608 return (avail); 3609 } 3610 3611 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3612 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3613 CALLOUT_LOCK(txq); 3614 callout_stop(&txq->ift_timer); 3615 CALLOUT_UNLOCK(txq); 3616 DBG_COUNTER_INC(txq_drain_oactive); 3617 return (0); 3618 } 3619 if (reclaimed) 3620 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3621 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3622 count = MIN(avail, TX_BATCH_SIZE); 3623 #ifdef INVARIANTS 3624 if (iflib_verbose_debug) 3625 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3626 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3627 #endif 3628 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3629 avail = TXQ_AVAIL(txq); 3630 err = 0; 3631 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3632 int rem = do_prefetch ? count - i : 0; 3633 3634 mp = _ring_peek_one(r, cidx, i, rem); 3635 MPASS(mp != NULL && *mp != NULL); 3636 if (__predict_false(*mp == (struct mbuf *)txq)) { 3637 consumed++; 3638 reclaimed++; 3639 continue; 3640 } 3641 in_use_prev = txq->ift_in_use; 3642 err = iflib_encap(txq, mp); 3643 if (__predict_false(err)) { 3644 /* no room - bail out */ 3645 if (err == ENOBUFS) 3646 break; 3647 consumed++; 3648 /* we can't send this packet - skip it */ 3649 continue; 3650 } 3651 consumed++; 3652 pkt_sent++; 3653 m = *mp; 3654 DBG_COUNTER_INC(tx_sent); 3655 bytes_sent += m->m_pkthdr.len; 3656 mcast_sent += !!(m->m_flags & M_MCAST); 3657 avail = TXQ_AVAIL(txq); 3658 3659 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3660 desc_used += (txq->ift_in_use - in_use_prev); 3661 ETHER_BPF_MTAP(ifp, m); 3662 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3663 break; 3664 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3665 } 3666 3667 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3668 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3669 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3670 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3671 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3672 if (mcast_sent) 3673 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3674 #ifdef INVARIANTS 3675 if (iflib_verbose_debug) 3676 printf("consumed=%d\n", consumed); 3677 #endif 3678 return (consumed); 3679 } 3680 3681 static uint32_t 3682 iflib_txq_drain_always(struct ifmp_ring *r) 3683 { 3684 return (1); 3685 } 3686 3687 static uint32_t 3688 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3689 { 3690 int i, avail; 3691 struct mbuf **mp; 3692 iflib_txq_t txq; 3693 3694 txq = r->cookie; 3695 3696 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3697 CALLOUT_LOCK(txq); 3698 callout_stop(&txq->ift_timer); 3699 CALLOUT_UNLOCK(txq); 3700 3701 avail = IDXDIFF(pidx, cidx, r->size); 3702 for (i = 0; i < avail; i++) { 3703 mp = _ring_peek_one(r, cidx, i, avail - i); 3704 if (__predict_false(*mp == (struct mbuf *)txq)) 3705 continue; 3706 m_freem(*mp); 3707 DBG_COUNTER_INC(tx_frees); 3708 } 3709 MPASS(ifmp_ring_is_stalled(r) == 0); 3710 return (avail); 3711 } 3712 3713 static void 3714 iflib_ifmp_purge(iflib_txq_t txq) 3715 { 3716 struct ifmp_ring *r; 3717 3718 r = txq->ift_br; 3719 r->drain = iflib_txq_drain_free; 3720 r->can_drain = iflib_txq_drain_always; 3721 3722 ifmp_ring_check_drainage(r, r->size); 3723 3724 r->drain = iflib_txq_drain; 3725 r->can_drain = iflib_txq_can_drain; 3726 } 3727 3728 static void 3729 _task_fn_tx(void *context) 3730 { 3731 iflib_txq_t txq = context; 3732 if_ctx_t ctx = txq->ift_ctx; 3733 #if defined(ALTQ) || defined(DEV_NETMAP) 3734 if_t ifp = ctx->ifc_ifp; 3735 #endif 3736 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3737 3738 #ifdef IFLIB_DIAGNOSTICS 3739 txq->ift_cpu_exec_count[curcpu]++; 3740 #endif 3741 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3742 return; 3743 #ifdef DEV_NETMAP 3744 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3745 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3746 BUS_DMASYNC_POSTREAD); 3747 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3748 netmap_tx_irq(ifp, txq->ift_id); 3749 if (ctx->ifc_flags & IFC_LEGACY) 3750 IFDI_INTR_ENABLE(ctx); 3751 else 3752 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3753 return; 3754 } 3755 #endif 3756 #ifdef ALTQ 3757 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3758 iflib_altq_if_start(ifp); 3759 #endif 3760 if (txq->ift_db_pending) 3761 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3762 else if (!abdicate) 3763 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3764 /* 3765 * When abdicating, we always need to check drainage, not just when we don't enqueue 3766 */ 3767 if (abdicate) 3768 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3769 if (ctx->ifc_flags & IFC_LEGACY) 3770 IFDI_INTR_ENABLE(ctx); 3771 else 3772 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3773 } 3774 3775 static void 3776 _task_fn_rx(void *context) 3777 { 3778 iflib_rxq_t rxq = context; 3779 if_ctx_t ctx = rxq->ifr_ctx; 3780 bool more; 3781 uint16_t budget; 3782 3783 #ifdef IFLIB_DIAGNOSTICS 3784 rxq->ifr_cpu_exec_count[curcpu]++; 3785 #endif 3786 DBG_COUNTER_INC(task_fn_rxs); 3787 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3788 return; 3789 more = true; 3790 #ifdef DEV_NETMAP 3791 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3792 u_int work = 0; 3793 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3794 more = false; 3795 } 3796 } 3797 #endif 3798 budget = ctx->ifc_sysctl_rx_budget; 3799 if (budget == 0) 3800 budget = 16; /* XXX */ 3801 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3802 if (ctx->ifc_flags & IFC_LEGACY) 3803 IFDI_INTR_ENABLE(ctx); 3804 else 3805 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3806 DBG_COUNTER_INC(rx_intr_enables); 3807 } 3808 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3809 return; 3810 if (more) 3811 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3812 } 3813 3814 static void 3815 _task_fn_admin(void *context) 3816 { 3817 if_ctx_t ctx = context; 3818 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3819 iflib_txq_t txq; 3820 int i; 3821 bool oactive, running, do_reset, do_watchdog, in_detach; 3822 uint32_t reset_on = hz / 2; 3823 3824 STATE_LOCK(ctx); 3825 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3826 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3827 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3828 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3829 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3830 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3831 STATE_UNLOCK(ctx); 3832 3833 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3834 return; 3835 if (in_detach) 3836 return; 3837 3838 CTX_LOCK(ctx); 3839 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3840 CALLOUT_LOCK(txq); 3841 callout_stop(&txq->ift_timer); 3842 CALLOUT_UNLOCK(txq); 3843 } 3844 if (do_watchdog) { 3845 ctx->ifc_watchdog_events++; 3846 IFDI_WATCHDOG_RESET(ctx); 3847 } 3848 IFDI_UPDATE_ADMIN_STATUS(ctx); 3849 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3850 #ifdef DEV_NETMAP 3851 reset_on = hz / 2; 3852 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3853 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 3854 #endif 3855 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3856 } 3857 IFDI_LINK_INTR_ENABLE(ctx); 3858 if (do_reset) 3859 iflib_if_init_locked(ctx); 3860 CTX_UNLOCK(ctx); 3861 3862 if (LINK_ACTIVE(ctx) == 0) 3863 return; 3864 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3865 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3866 } 3867 3868 3869 static void 3870 _task_fn_iov(void *context) 3871 { 3872 if_ctx_t ctx = context; 3873 3874 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3875 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3876 return; 3877 3878 CTX_LOCK(ctx); 3879 IFDI_VFLR_HANDLE(ctx); 3880 CTX_UNLOCK(ctx); 3881 } 3882 3883 static int 3884 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3885 { 3886 int err; 3887 if_int_delay_info_t info; 3888 if_ctx_t ctx; 3889 3890 info = (if_int_delay_info_t)arg1; 3891 ctx = info->iidi_ctx; 3892 info->iidi_req = req; 3893 info->iidi_oidp = oidp; 3894 CTX_LOCK(ctx); 3895 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3896 CTX_UNLOCK(ctx); 3897 return (err); 3898 } 3899 3900 /********************************************************************* 3901 * 3902 * IFNET FUNCTIONS 3903 * 3904 **********************************************************************/ 3905 3906 static void 3907 iflib_if_init_locked(if_ctx_t ctx) 3908 { 3909 iflib_stop(ctx); 3910 iflib_init_locked(ctx); 3911 } 3912 3913 3914 static void 3915 iflib_if_init(void *arg) 3916 { 3917 if_ctx_t ctx = arg; 3918 3919 CTX_LOCK(ctx); 3920 iflib_if_init_locked(ctx); 3921 CTX_UNLOCK(ctx); 3922 } 3923 3924 static int 3925 iflib_if_transmit(if_t ifp, struct mbuf *m) 3926 { 3927 if_ctx_t ctx = if_getsoftc(ifp); 3928 3929 iflib_txq_t txq; 3930 int err, qidx; 3931 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3932 3933 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3934 DBG_COUNTER_INC(tx_frees); 3935 m_freem(m); 3936 return (ENETDOWN); 3937 } 3938 3939 MPASS(m->m_nextpkt == NULL); 3940 /* ALTQ-enabled interfaces always use queue 0. */ 3941 qidx = 0; 3942 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3943 qidx = QIDX(ctx, m); 3944 /* 3945 * XXX calculate buf_ring based on flowid (divvy up bits?) 3946 */ 3947 txq = &ctx->ifc_txqs[qidx]; 3948 3949 #ifdef DRIVER_BACKPRESSURE 3950 if (txq->ift_closed) { 3951 while (m != NULL) { 3952 next = m->m_nextpkt; 3953 m->m_nextpkt = NULL; 3954 m_freem(m); 3955 DBG_COUNTER_INC(tx_frees); 3956 m = next; 3957 } 3958 return (ENOBUFS); 3959 } 3960 #endif 3961 #ifdef notyet 3962 qidx = count = 0; 3963 mp = marr; 3964 next = m; 3965 do { 3966 count++; 3967 next = next->m_nextpkt; 3968 } while (next != NULL); 3969 3970 if (count > nitems(marr)) 3971 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3972 /* XXX check nextpkt */ 3973 m_freem(m); 3974 /* XXX simplify for now */ 3975 DBG_COUNTER_INC(tx_frees); 3976 return (ENOBUFS); 3977 } 3978 for (next = m, i = 0; next != NULL; i++) { 3979 mp[i] = next; 3980 next = next->m_nextpkt; 3981 mp[i]->m_nextpkt = NULL; 3982 } 3983 #endif 3984 DBG_COUNTER_INC(tx_seen); 3985 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 3986 3987 if (abdicate) 3988 GROUPTASK_ENQUEUE(&txq->ift_task); 3989 if (err) { 3990 if (!abdicate) 3991 GROUPTASK_ENQUEUE(&txq->ift_task); 3992 /* support forthcoming later */ 3993 #ifdef DRIVER_BACKPRESSURE 3994 txq->ift_closed = TRUE; 3995 #endif 3996 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3997 m_freem(m); 3998 DBG_COUNTER_INC(tx_frees); 3999 } 4000 4001 return (err); 4002 } 4003 4004 #ifdef ALTQ 4005 /* 4006 * The overall approach to integrating iflib with ALTQ is to continue to use 4007 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4008 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4009 * is redundant/unnecessary, but doing so minimizes the amount of 4010 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4011 * redundantly queueing to an intermediate mp_ring is swamped by the 4012 * performance limitations inherent in using ALTQ. 4013 * 4014 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4015 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4016 * given interface. If ALTQ is enabled for an interface, then all 4017 * transmitted packets for that interface will be submitted to the ALTQ 4018 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4019 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4020 * update stats that the iflib machinery handles, and which is sensitve to 4021 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4022 * will be installed as the start routine for use by ALTQ facilities that 4023 * need to trigger queue drains on a scheduled basis. 4024 * 4025 */ 4026 static void 4027 iflib_altq_if_start(if_t ifp) 4028 { 4029 struct ifaltq *ifq = &ifp->if_snd; 4030 struct mbuf *m; 4031 4032 IFQ_LOCK(ifq); 4033 IFQ_DEQUEUE_NOLOCK(ifq, m); 4034 while (m != NULL) { 4035 iflib_if_transmit(ifp, m); 4036 IFQ_DEQUEUE_NOLOCK(ifq, m); 4037 } 4038 IFQ_UNLOCK(ifq); 4039 } 4040 4041 static int 4042 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4043 { 4044 int err; 4045 4046 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4047 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4048 if (err == 0) 4049 iflib_altq_if_start(ifp); 4050 } else 4051 err = iflib_if_transmit(ifp, m); 4052 4053 return (err); 4054 } 4055 #endif /* ALTQ */ 4056 4057 static void 4058 iflib_if_qflush(if_t ifp) 4059 { 4060 if_ctx_t ctx = if_getsoftc(ifp); 4061 iflib_txq_t txq = ctx->ifc_txqs; 4062 int i; 4063 4064 STATE_LOCK(ctx); 4065 ctx->ifc_flags |= IFC_QFLUSH; 4066 STATE_UNLOCK(ctx); 4067 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4068 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4069 iflib_txq_check_drain(txq, 0); 4070 STATE_LOCK(ctx); 4071 ctx->ifc_flags &= ~IFC_QFLUSH; 4072 STATE_UNLOCK(ctx); 4073 4074 /* 4075 * When ALTQ is enabled, this will also take care of purging the 4076 * ALTQ queue(s). 4077 */ 4078 if_qflush(ifp); 4079 } 4080 4081 4082 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4083 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4084 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4085 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM) 4086 4087 static int 4088 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4089 { 4090 if_ctx_t ctx = if_getsoftc(ifp); 4091 struct ifreq *ifr = (struct ifreq *)data; 4092 #if defined(INET) || defined(INET6) 4093 struct ifaddr *ifa = (struct ifaddr *)data; 4094 #endif 4095 bool avoid_reset = false; 4096 int err = 0, reinit = 0, bits; 4097 4098 switch (command) { 4099 case SIOCSIFADDR: 4100 #ifdef INET 4101 if (ifa->ifa_addr->sa_family == AF_INET) 4102 avoid_reset = true; 4103 #endif 4104 #ifdef INET6 4105 if (ifa->ifa_addr->sa_family == AF_INET6) 4106 avoid_reset = true; 4107 #endif 4108 /* 4109 ** Calling init results in link renegotiation, 4110 ** so we avoid doing it when possible. 4111 */ 4112 if (avoid_reset) { 4113 if_setflagbits(ifp, IFF_UP,0); 4114 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4115 reinit = 1; 4116 #ifdef INET 4117 if (!(if_getflags(ifp) & IFF_NOARP)) 4118 arp_ifinit(ifp, ifa); 4119 #endif 4120 } else 4121 err = ether_ioctl(ifp, command, data); 4122 break; 4123 case SIOCSIFMTU: 4124 CTX_LOCK(ctx); 4125 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4126 CTX_UNLOCK(ctx); 4127 break; 4128 } 4129 bits = if_getdrvflags(ifp); 4130 /* stop the driver and free any clusters before proceeding */ 4131 iflib_stop(ctx); 4132 4133 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4134 STATE_LOCK(ctx); 4135 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4136 ctx->ifc_flags |= IFC_MULTISEG; 4137 else 4138 ctx->ifc_flags &= ~IFC_MULTISEG; 4139 STATE_UNLOCK(ctx); 4140 err = if_setmtu(ifp, ifr->ifr_mtu); 4141 } 4142 iflib_init_locked(ctx); 4143 STATE_LOCK(ctx); 4144 if_setdrvflags(ifp, bits); 4145 STATE_UNLOCK(ctx); 4146 CTX_UNLOCK(ctx); 4147 break; 4148 case SIOCSIFFLAGS: 4149 CTX_LOCK(ctx); 4150 if (if_getflags(ifp) & IFF_UP) { 4151 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4152 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4153 (IFF_PROMISC | IFF_ALLMULTI)) { 4154 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4155 } 4156 } else 4157 reinit = 1; 4158 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4159 iflib_stop(ctx); 4160 } 4161 ctx->ifc_if_flags = if_getflags(ifp); 4162 CTX_UNLOCK(ctx); 4163 break; 4164 case SIOCADDMULTI: 4165 case SIOCDELMULTI: 4166 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4167 CTX_LOCK(ctx); 4168 IFDI_INTR_DISABLE(ctx); 4169 IFDI_MULTI_SET(ctx); 4170 IFDI_INTR_ENABLE(ctx); 4171 CTX_UNLOCK(ctx); 4172 } 4173 break; 4174 case SIOCSIFMEDIA: 4175 CTX_LOCK(ctx); 4176 IFDI_MEDIA_SET(ctx); 4177 CTX_UNLOCK(ctx); 4178 /* FALLTHROUGH */ 4179 case SIOCGIFMEDIA: 4180 case SIOCGIFXMEDIA: 4181 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4182 break; 4183 case SIOCGI2C: 4184 { 4185 struct ifi2creq i2c; 4186 4187 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4188 if (err != 0) 4189 break; 4190 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4191 err = EINVAL; 4192 break; 4193 } 4194 if (i2c.len > sizeof(i2c.data)) { 4195 err = EINVAL; 4196 break; 4197 } 4198 4199 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4200 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4201 sizeof(i2c)); 4202 break; 4203 } 4204 case SIOCSIFCAP: 4205 { 4206 int mask, setmask, oldmask; 4207 4208 oldmask = if_getcapenable(ifp); 4209 mask = ifr->ifr_reqcap ^ oldmask; 4210 mask &= ctx->ifc_softc_ctx.isc_capabilities; 4211 setmask = 0; 4212 #ifdef TCP_OFFLOAD 4213 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4214 #endif 4215 setmask |= (mask & IFCAP_FLAGS); 4216 setmask |= (mask & IFCAP_WOL); 4217 4218 /* 4219 * If any RX csum has changed, change all the ones that 4220 * are supported by the driver. 4221 */ 4222 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4223 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4224 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4225 } 4226 4227 /* 4228 * want to ensure that traffic has stopped before we change any of the flags 4229 */ 4230 if (setmask) { 4231 CTX_LOCK(ctx); 4232 bits = if_getdrvflags(ifp); 4233 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4234 iflib_stop(ctx); 4235 STATE_LOCK(ctx); 4236 if_togglecapenable(ifp, setmask); 4237 STATE_UNLOCK(ctx); 4238 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4239 iflib_init_locked(ctx); 4240 STATE_LOCK(ctx); 4241 if_setdrvflags(ifp, bits); 4242 STATE_UNLOCK(ctx); 4243 CTX_UNLOCK(ctx); 4244 } 4245 if_vlancap(ifp); 4246 break; 4247 } 4248 case SIOCGPRIVATE_0: 4249 case SIOCSDRVSPEC: 4250 case SIOCGDRVSPEC: 4251 CTX_LOCK(ctx); 4252 err = IFDI_PRIV_IOCTL(ctx, command, data); 4253 CTX_UNLOCK(ctx); 4254 break; 4255 default: 4256 err = ether_ioctl(ifp, command, data); 4257 break; 4258 } 4259 if (reinit) 4260 iflib_if_init(ctx); 4261 return (err); 4262 } 4263 4264 static uint64_t 4265 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4266 { 4267 if_ctx_t ctx = if_getsoftc(ifp); 4268 4269 return (IFDI_GET_COUNTER(ctx, cnt)); 4270 } 4271 4272 /********************************************************************* 4273 * 4274 * OTHER FUNCTIONS EXPORTED TO THE STACK 4275 * 4276 **********************************************************************/ 4277 4278 static void 4279 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4280 { 4281 if_ctx_t ctx = if_getsoftc(ifp); 4282 4283 if ((void *)ctx != arg) 4284 return; 4285 4286 if ((vtag == 0) || (vtag > 4095)) 4287 return; 4288 4289 CTX_LOCK(ctx); 4290 IFDI_VLAN_REGISTER(ctx, vtag); 4291 /* Re-init to load the changes */ 4292 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4293 iflib_if_init_locked(ctx); 4294 CTX_UNLOCK(ctx); 4295 } 4296 4297 static void 4298 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4299 { 4300 if_ctx_t ctx = if_getsoftc(ifp); 4301 4302 if ((void *)ctx != arg) 4303 return; 4304 4305 if ((vtag == 0) || (vtag > 4095)) 4306 return; 4307 4308 CTX_LOCK(ctx); 4309 IFDI_VLAN_UNREGISTER(ctx, vtag); 4310 /* Re-init to load the changes */ 4311 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4312 iflib_if_init_locked(ctx); 4313 CTX_UNLOCK(ctx); 4314 } 4315 4316 static void 4317 iflib_led_func(void *arg, int onoff) 4318 { 4319 if_ctx_t ctx = arg; 4320 4321 CTX_LOCK(ctx); 4322 IFDI_LED_FUNC(ctx, onoff); 4323 CTX_UNLOCK(ctx); 4324 } 4325 4326 /********************************************************************* 4327 * 4328 * BUS FUNCTION DEFINITIONS 4329 * 4330 **********************************************************************/ 4331 4332 int 4333 iflib_device_probe(device_t dev) 4334 { 4335 pci_vendor_info_t *ent; 4336 4337 uint16_t pci_vendor_id, pci_device_id; 4338 uint16_t pci_subvendor_id, pci_subdevice_id; 4339 uint16_t pci_rev_id; 4340 if_shared_ctx_t sctx; 4341 4342 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4343 return (ENOTSUP); 4344 4345 pci_vendor_id = pci_get_vendor(dev); 4346 pci_device_id = pci_get_device(dev); 4347 pci_subvendor_id = pci_get_subvendor(dev); 4348 pci_subdevice_id = pci_get_subdevice(dev); 4349 pci_rev_id = pci_get_revid(dev); 4350 if (sctx->isc_parse_devinfo != NULL) 4351 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4352 4353 ent = sctx->isc_vendor_info; 4354 while (ent->pvi_vendor_id != 0) { 4355 if (pci_vendor_id != ent->pvi_vendor_id) { 4356 ent++; 4357 continue; 4358 } 4359 if ((pci_device_id == ent->pvi_device_id) && 4360 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4361 (ent->pvi_subvendor_id == 0)) && 4362 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4363 (ent->pvi_subdevice_id == 0)) && 4364 ((pci_rev_id == ent->pvi_rev_id) || 4365 (ent->pvi_rev_id == 0))) { 4366 4367 device_set_desc_copy(dev, ent->pvi_name); 4368 /* this needs to be changed to zero if the bus probing code 4369 * ever stops re-probing on best match because the sctx 4370 * may have its values over written by register calls 4371 * in subsequent probes 4372 */ 4373 return (BUS_PROBE_DEFAULT); 4374 } 4375 ent++; 4376 } 4377 return (ENXIO); 4378 } 4379 4380 int 4381 iflib_device_probe_vendor(device_t dev) 4382 { 4383 int probe; 4384 4385 probe = iflib_device_probe(dev); 4386 if (probe == BUS_PROBE_DEFAULT) 4387 return (BUS_PROBE_VENDOR); 4388 else 4389 return (probe); 4390 } 4391 4392 static void 4393 iflib_reset_qvalues(if_ctx_t ctx) 4394 { 4395 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4396 if_shared_ctx_t sctx = ctx->ifc_sctx; 4397 device_t dev = ctx->ifc_dev; 4398 int i; 4399 4400 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES; 4401 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH; 4402 if (ctx->ifc_sysctl_ntxqs != 0) 4403 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4404 if (ctx->ifc_sysctl_nrxqs != 0) 4405 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4406 4407 for (i = 0; i < sctx->isc_ntxqs; i++) { 4408 if (ctx->ifc_sysctl_ntxds[i] != 0) 4409 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4410 else 4411 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4412 } 4413 4414 for (i = 0; i < sctx->isc_nrxqs; i++) { 4415 if (ctx->ifc_sysctl_nrxds[i] != 0) 4416 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4417 else 4418 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4419 } 4420 4421 for (i = 0; i < sctx->isc_nrxqs; i++) { 4422 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4423 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4424 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4425 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4426 } 4427 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4428 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4429 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4430 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4431 } 4432 if (!powerof2(scctx->isc_nrxd[i])) { 4433 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4434 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4435 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4436 } 4437 } 4438 4439 for (i = 0; i < sctx->isc_ntxqs; i++) { 4440 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4441 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4442 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4443 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4444 } 4445 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4446 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4447 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4448 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4449 } 4450 if (!powerof2(scctx->isc_ntxd[i])) { 4451 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4452 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4453 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4454 } 4455 } 4456 } 4457 4458 static void 4459 iflib_add_pfil(if_ctx_t ctx) 4460 { 4461 struct pfil_head *pfil; 4462 struct pfil_head_args pa; 4463 iflib_rxq_t rxq; 4464 int i; 4465 4466 pa.pa_version = PFIL_VERSION; 4467 pa.pa_flags = PFIL_IN; 4468 pa.pa_type = PFIL_TYPE_ETHERNET; 4469 pa.pa_headname = ctx->ifc_ifp->if_xname; 4470 pfil = pfil_head_register(&pa); 4471 4472 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4473 rxq->pfil = pfil; 4474 } 4475 } 4476 4477 static void 4478 iflib_rem_pfil(if_ctx_t ctx) 4479 { 4480 struct pfil_head *pfil; 4481 iflib_rxq_t rxq; 4482 int i; 4483 4484 rxq = ctx->ifc_rxqs; 4485 pfil = rxq->pfil; 4486 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4487 rxq->pfil = NULL; 4488 } 4489 pfil_head_unregister(pfil); 4490 } 4491 4492 static uint16_t 4493 get_ctx_core_offset(if_ctx_t ctx) 4494 { 4495 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4496 struct cpu_offset *op; 4497 uint16_t qc; 4498 uint16_t ret = ctx->ifc_sysctl_core_offset; 4499 4500 if (ret != CORE_OFFSET_UNSPECIFIED) 4501 return (ret); 4502 4503 if (ctx->ifc_sysctl_separate_txrx) 4504 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets; 4505 else 4506 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets); 4507 4508 mtx_lock(&cpu_offset_mtx); 4509 SLIST_FOREACH(op, &cpu_offsets, entries) { 4510 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4511 ret = op->offset; 4512 op->offset += qc; 4513 MPASS(op->refcount < UINT_MAX); 4514 op->refcount++; 4515 break; 4516 } 4517 } 4518 if (ret == CORE_OFFSET_UNSPECIFIED) { 4519 ret = 0; 4520 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4521 M_NOWAIT | M_ZERO); 4522 if (op == NULL) { 4523 device_printf(ctx->ifc_dev, 4524 "allocation for cpu offset failed.\n"); 4525 } else { 4526 op->offset = qc; 4527 op->refcount = 1; 4528 CPU_COPY(&ctx->ifc_cpus, &op->set); 4529 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4530 } 4531 } 4532 mtx_unlock(&cpu_offset_mtx); 4533 4534 return (ret); 4535 } 4536 4537 static void 4538 unref_ctx_core_offset(if_ctx_t ctx) 4539 { 4540 struct cpu_offset *op, *top; 4541 4542 mtx_lock(&cpu_offset_mtx); 4543 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4544 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4545 MPASS(op->refcount > 0); 4546 op->refcount--; 4547 if (op->refcount == 0) { 4548 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4549 free(op, M_IFLIB); 4550 } 4551 break; 4552 } 4553 } 4554 mtx_unlock(&cpu_offset_mtx); 4555 } 4556 4557 int 4558 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4559 { 4560 if_ctx_t ctx; 4561 if_t ifp; 4562 if_softc_ctx_t scctx; 4563 kobjop_desc_t kobj_desc; 4564 kobj_method_t *kobj_method; 4565 int err, msix, rid; 4566 uint16_t main_rxq, main_txq; 4567 4568 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4569 4570 if (sc == NULL) { 4571 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4572 device_set_softc(dev, ctx); 4573 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4574 } 4575 4576 ctx->ifc_sctx = sctx; 4577 ctx->ifc_dev = dev; 4578 ctx->ifc_softc = sc; 4579 4580 if ((err = iflib_register(ctx)) != 0) { 4581 device_printf(dev, "iflib_register failed %d\n", err); 4582 goto fail_ctx_free; 4583 } 4584 iflib_add_device_sysctl_pre(ctx); 4585 4586 scctx = &ctx->ifc_softc_ctx; 4587 ifp = ctx->ifc_ifp; 4588 4589 iflib_reset_qvalues(ctx); 4590 CTX_LOCK(ctx); 4591 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4592 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4593 goto fail_unlock; 4594 } 4595 _iflib_pre_assert(scctx); 4596 ctx->ifc_txrx = *scctx->isc_txrx; 4597 4598 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 4599 ctx->ifc_mediap = scctx->isc_media; 4600 4601 #ifdef INVARIANTS 4602 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4603 MPASS(scctx->isc_tx_csum_flags); 4604 #endif 4605 4606 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS); 4607 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4608 4609 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4610 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4611 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4612 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4613 4614 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4615 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4616 4617 /* XXX change for per-queue sizes */ 4618 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4619 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4620 4621 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4622 MAX_SINGLE_PACKET_FRACTION) 4623 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4624 MAX_SINGLE_PACKET_FRACTION); 4625 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4626 MAX_SINGLE_PACKET_FRACTION) 4627 scctx->isc_tx_tso_segments_max = max(1, 4628 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4629 4630 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4631 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4632 /* 4633 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4634 * but some MACs do. 4635 */ 4636 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4637 IP_MAXPACKET)); 4638 /* 4639 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4640 * into account. In the worst case, each of these calls will 4641 * add another mbuf and, thus, the requirement for another DMA 4642 * segment. So for best performance, it doesn't make sense to 4643 * advertize a maximum of TSO segments that typically will 4644 * require defragmentation in iflib_encap(). 4645 */ 4646 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4647 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4648 } 4649 if (scctx->isc_rss_table_size == 0) 4650 scctx->isc_rss_table_size = 64; 4651 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4652 4653 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4654 /* XXX format name */ 4655 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4656 NULL, NULL, "admin"); 4657 4658 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4659 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4660 device_printf(dev, "Unable to fetch CPU list\n"); 4661 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4662 } 4663 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4664 4665 /* 4666 ** Now set up MSI or MSI-X, should return us the number of supported 4667 ** vectors (will be 1 for a legacy interrupt and MSI). 4668 */ 4669 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4670 msix = scctx->isc_vectors; 4671 } else if (scctx->isc_msix_bar != 0) 4672 /* 4673 * The simple fact that isc_msix_bar is not 0 does not mean we 4674 * we have a good value there that is known to work. 4675 */ 4676 msix = iflib_msix_init(ctx); 4677 else { 4678 scctx->isc_vectors = 1; 4679 scctx->isc_ntxqsets = 1; 4680 scctx->isc_nrxqsets = 1; 4681 scctx->isc_intr = IFLIB_INTR_LEGACY; 4682 msix = 0; 4683 } 4684 /* Get memory for the station queues */ 4685 if ((err = iflib_queues_alloc(ctx))) { 4686 device_printf(dev, "Unable to allocate queue memory\n"); 4687 goto fail_intr_free; 4688 } 4689 4690 if ((err = iflib_qset_structures_setup(ctx))) 4691 goto fail_queues; 4692 4693 /* 4694 * Now that we know how many queues there are, get the core offset. 4695 */ 4696 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 4697 4698 /* 4699 * Group taskqueues aren't properly set up until SMP is started, 4700 * so we disable interrupts until we can handle them post 4701 * SI_SUB_SMP. 4702 * 4703 * XXX: disabling interrupts doesn't actually work, at least for 4704 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4705 * we do null handling and depend on this not causing too large an 4706 * interrupt storm. 4707 */ 4708 IFDI_INTR_DISABLE(ctx); 4709 4710 if (msix > 1) { 4711 /* 4712 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 4713 * aren't the default NULL implementation. 4714 */ 4715 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 4716 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4717 kobj_desc); 4718 if (kobj_method == &kobj_desc->deflt) { 4719 device_printf(dev, 4720 "MSI-X requires ifdi_rx_queue_intr_enable method"); 4721 err = EOPNOTSUPP; 4722 goto fail_queues; 4723 } 4724 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 4725 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4726 kobj_desc); 4727 if (kobj_method == &kobj_desc->deflt) { 4728 device_printf(dev, 4729 "MSI-X requires ifdi_tx_queue_intr_enable method"); 4730 err = EOPNOTSUPP; 4731 goto fail_queues; 4732 } 4733 4734 /* 4735 * Assign the MSI-X vectors. 4736 * Note that the default NULL ifdi_msix_intr_assign method will 4737 * fail here, too. 4738 */ 4739 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 4740 if (err != 0) { 4741 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 4742 err); 4743 goto fail_queues; 4744 } 4745 } else { 4746 rid = 0; 4747 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4748 MPASS(msix == 1); 4749 rid = 1; 4750 } 4751 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4752 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4753 goto fail_queues; 4754 } 4755 } 4756 4757 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4758 4759 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4760 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4761 goto fail_detach; 4762 } 4763 4764 /* 4765 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4766 * This must appear after the call to ether_ifattach() because 4767 * ether_ifattach() sets if_hdrlen to the default value. 4768 */ 4769 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4770 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4771 4772 if ((err = iflib_netmap_attach(ctx))) { 4773 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4774 goto fail_detach; 4775 } 4776 *ctxp = ctx; 4777 4778 NETDUMP_SET(ctx->ifc_ifp, iflib); 4779 4780 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4781 iflib_add_device_sysctl_post(ctx); 4782 iflib_add_pfil(ctx); 4783 ctx->ifc_flags |= IFC_INIT_DONE; 4784 CTX_UNLOCK(ctx); 4785 4786 return (0); 4787 4788 fail_detach: 4789 ether_ifdetach(ctx->ifc_ifp); 4790 fail_intr_free: 4791 iflib_free_intr_mem(ctx); 4792 fail_queues: 4793 iflib_tx_structures_free(ctx); 4794 iflib_rx_structures_free(ctx); 4795 IFDI_DETACH(ctx); 4796 fail_unlock: 4797 CTX_UNLOCK(ctx); 4798 fail_ctx_free: 4799 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4800 free(ctx->ifc_softc, M_IFLIB); 4801 free(ctx, M_IFLIB); 4802 return (err); 4803 } 4804 4805 int 4806 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4807 struct iflib_cloneattach_ctx *clctx) 4808 { 4809 int err; 4810 if_ctx_t ctx; 4811 if_t ifp; 4812 if_softc_ctx_t scctx; 4813 int i; 4814 void *sc; 4815 uint16_t main_txq; 4816 uint16_t main_rxq; 4817 4818 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4819 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4820 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4821 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4822 ctx->ifc_flags |= IFC_PSEUDO; 4823 4824 ctx->ifc_sctx = sctx; 4825 ctx->ifc_softc = sc; 4826 ctx->ifc_dev = dev; 4827 4828 if ((err = iflib_register(ctx)) != 0) { 4829 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4830 goto fail_ctx_free; 4831 } 4832 iflib_add_device_sysctl_pre(ctx); 4833 4834 scctx = &ctx->ifc_softc_ctx; 4835 ifp = ctx->ifc_ifp; 4836 4837 iflib_reset_qvalues(ctx); 4838 CTX_LOCK(ctx); 4839 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4840 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4841 goto fail_unlock; 4842 } 4843 if (sctx->isc_flags & IFLIB_GEN_MAC) 4844 ether_gen_addr(ifp, &ctx->ifc_mac); 4845 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4846 clctx->cc_params)) != 0) { 4847 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4848 goto fail_ctx_free; 4849 } 4850 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4851 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4852 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4853 4854 #ifdef INVARIANTS 4855 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4856 MPASS(scctx->isc_tx_csum_flags); 4857 #endif 4858 4859 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4860 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4861 4862 ifp->if_flags |= IFF_NOGROUP; 4863 if (sctx->isc_flags & IFLIB_PSEUDO) { 4864 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4865 4866 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4867 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4868 goto fail_detach; 4869 } 4870 *ctxp = ctx; 4871 4872 /* 4873 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4874 * This must appear after the call to ether_ifattach() because 4875 * ether_ifattach() sets if_hdrlen to the default value. 4876 */ 4877 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4878 if_setifheaderlen(ifp, 4879 sizeof(struct ether_vlan_header)); 4880 4881 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4882 iflib_add_device_sysctl_post(ctx); 4883 ctx->ifc_flags |= IFC_INIT_DONE; 4884 return (0); 4885 } 4886 _iflib_pre_assert(scctx); 4887 ctx->ifc_txrx = *scctx->isc_txrx; 4888 4889 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4890 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4891 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4892 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4893 4894 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4895 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4896 4897 /* XXX change for per-queue sizes */ 4898 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4899 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4900 4901 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4902 MAX_SINGLE_PACKET_FRACTION) 4903 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4904 MAX_SINGLE_PACKET_FRACTION); 4905 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4906 MAX_SINGLE_PACKET_FRACTION) 4907 scctx->isc_tx_tso_segments_max = max(1, 4908 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4909 4910 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4911 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4912 /* 4913 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4914 * but some MACs do. 4915 */ 4916 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4917 IP_MAXPACKET)); 4918 /* 4919 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4920 * into account. In the worst case, each of these calls will 4921 * add another mbuf and, thus, the requirement for another DMA 4922 * segment. So for best performance, it doesn't make sense to 4923 * advertize a maximum of TSO segments that typically will 4924 * require defragmentation in iflib_encap(). 4925 */ 4926 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4927 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4928 } 4929 if (scctx->isc_rss_table_size == 0) 4930 scctx->isc_rss_table_size = 64; 4931 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4932 4933 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4934 /* XXX format name */ 4935 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4936 NULL, NULL, "admin"); 4937 4938 /* XXX --- can support > 1 -- but keep it simple for now */ 4939 scctx->isc_intr = IFLIB_INTR_LEGACY; 4940 4941 /* Get memory for the station queues */ 4942 if ((err = iflib_queues_alloc(ctx))) { 4943 device_printf(dev, "Unable to allocate queue memory\n"); 4944 goto fail_iflib_detach; 4945 } 4946 4947 if ((err = iflib_qset_structures_setup(ctx))) { 4948 device_printf(dev, "qset structure setup failed %d\n", err); 4949 goto fail_queues; 4950 } 4951 4952 /* 4953 * XXX What if anything do we want to do about interrupts? 4954 */ 4955 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4956 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4957 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4958 goto fail_detach; 4959 } 4960 4961 /* 4962 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4963 * This must appear after the call to ether_ifattach() because 4964 * ether_ifattach() sets if_hdrlen to the default value. 4965 */ 4966 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4967 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4968 4969 /* XXX handle more than one queue */ 4970 for (i = 0; i < scctx->isc_nrxqsets; i++) 4971 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4972 4973 *ctxp = ctx; 4974 4975 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4976 iflib_add_device_sysctl_post(ctx); 4977 ctx->ifc_flags |= IFC_INIT_DONE; 4978 CTX_UNLOCK(ctx); 4979 4980 return (0); 4981 fail_detach: 4982 ether_ifdetach(ctx->ifc_ifp); 4983 fail_queues: 4984 iflib_tx_structures_free(ctx); 4985 iflib_rx_structures_free(ctx); 4986 fail_iflib_detach: 4987 IFDI_DETACH(ctx); 4988 fail_unlock: 4989 CTX_UNLOCK(ctx); 4990 fail_ctx_free: 4991 free(ctx->ifc_softc, M_IFLIB); 4992 free(ctx, M_IFLIB); 4993 return (err); 4994 } 4995 4996 int 4997 iflib_pseudo_deregister(if_ctx_t ctx) 4998 { 4999 if_t ifp = ctx->ifc_ifp; 5000 iflib_txq_t txq; 5001 iflib_rxq_t rxq; 5002 int i, j; 5003 struct taskqgroup *tqg; 5004 iflib_fl_t fl; 5005 5006 /* Unregister VLAN events */ 5007 if (ctx->ifc_vlan_attach_event != NULL) 5008 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5009 if (ctx->ifc_vlan_detach_event != NULL) 5010 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5011 5012 ether_ifdetach(ifp); 5013 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5014 CTX_LOCK_DESTROY(ctx); 5015 /* XXX drain any dependent tasks */ 5016 tqg = qgroup_if_io_tqg; 5017 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5018 callout_drain(&txq->ift_timer); 5019 if (txq->ift_task.gt_uniq != NULL) 5020 taskqgroup_detach(tqg, &txq->ift_task); 5021 } 5022 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5023 if (rxq->ifr_task.gt_uniq != NULL) 5024 taskqgroup_detach(tqg, &rxq->ifr_task); 5025 5026 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5027 free(fl->ifl_rx_bitmap, M_IFLIB); 5028 } 5029 tqg = qgroup_if_config_tqg; 5030 if (ctx->ifc_admin_task.gt_uniq != NULL) 5031 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5032 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5033 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5034 5035 if_free(ifp); 5036 5037 iflib_tx_structures_free(ctx); 5038 iflib_rx_structures_free(ctx); 5039 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5040 free(ctx->ifc_softc, M_IFLIB); 5041 free(ctx, M_IFLIB); 5042 return (0); 5043 } 5044 5045 int 5046 iflib_device_attach(device_t dev) 5047 { 5048 if_ctx_t ctx; 5049 if_shared_ctx_t sctx; 5050 5051 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5052 return (ENOTSUP); 5053 5054 pci_enable_busmaster(dev); 5055 5056 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5057 } 5058 5059 int 5060 iflib_device_deregister(if_ctx_t ctx) 5061 { 5062 if_t ifp = ctx->ifc_ifp; 5063 iflib_txq_t txq; 5064 iflib_rxq_t rxq; 5065 device_t dev = ctx->ifc_dev; 5066 int i, j; 5067 struct taskqgroup *tqg; 5068 iflib_fl_t fl; 5069 5070 /* Make sure VLANS are not using driver */ 5071 if (if_vlantrunkinuse(ifp)) { 5072 device_printf(dev, "Vlan in use, detach first\n"); 5073 return (EBUSY); 5074 } 5075 #ifdef PCI_IOV 5076 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5077 device_printf(dev, "SR-IOV in use; detach first.\n"); 5078 return (EBUSY); 5079 } 5080 #endif 5081 5082 STATE_LOCK(ctx); 5083 ctx->ifc_flags |= IFC_IN_DETACH; 5084 STATE_UNLOCK(ctx); 5085 5086 CTX_LOCK(ctx); 5087 iflib_stop(ctx); 5088 CTX_UNLOCK(ctx); 5089 5090 /* Unregister VLAN events */ 5091 if (ctx->ifc_vlan_attach_event != NULL) 5092 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5093 if (ctx->ifc_vlan_detach_event != NULL) 5094 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5095 5096 iflib_netmap_detach(ifp); 5097 ether_ifdetach(ifp); 5098 iflib_rem_pfil(ctx); 5099 if (ctx->ifc_led_dev != NULL) 5100 led_destroy(ctx->ifc_led_dev); 5101 /* XXX drain any dependent tasks */ 5102 tqg = qgroup_if_io_tqg; 5103 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5104 callout_drain(&txq->ift_timer); 5105 if (txq->ift_task.gt_uniq != NULL) 5106 taskqgroup_detach(tqg, &txq->ift_task); 5107 } 5108 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5109 if (rxq->ifr_task.gt_uniq != NULL) 5110 taskqgroup_detach(tqg, &rxq->ifr_task); 5111 5112 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5113 free(fl->ifl_rx_bitmap, M_IFLIB); 5114 } 5115 tqg = qgroup_if_config_tqg; 5116 if (ctx->ifc_admin_task.gt_uniq != NULL) 5117 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5118 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5119 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5120 CTX_LOCK(ctx); 5121 IFDI_DETACH(ctx); 5122 CTX_UNLOCK(ctx); 5123 5124 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5125 CTX_LOCK_DESTROY(ctx); 5126 device_set_softc(ctx->ifc_dev, NULL); 5127 iflib_free_intr_mem(ctx); 5128 5129 bus_generic_detach(dev); 5130 if_free(ifp); 5131 5132 iflib_tx_structures_free(ctx); 5133 iflib_rx_structures_free(ctx); 5134 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5135 free(ctx->ifc_softc, M_IFLIB); 5136 unref_ctx_core_offset(ctx); 5137 STATE_LOCK_DESTROY(ctx); 5138 free(ctx, M_IFLIB); 5139 return (0); 5140 } 5141 5142 static void 5143 iflib_free_intr_mem(if_ctx_t ctx) 5144 { 5145 5146 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5147 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5148 } 5149 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5150 pci_release_msi(ctx->ifc_dev); 5151 } 5152 if (ctx->ifc_msix_mem != NULL) { 5153 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5154 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5155 ctx->ifc_msix_mem = NULL; 5156 } 5157 } 5158 5159 int 5160 iflib_device_detach(device_t dev) 5161 { 5162 if_ctx_t ctx = device_get_softc(dev); 5163 5164 return (iflib_device_deregister(ctx)); 5165 } 5166 5167 int 5168 iflib_device_suspend(device_t dev) 5169 { 5170 if_ctx_t ctx = device_get_softc(dev); 5171 5172 CTX_LOCK(ctx); 5173 IFDI_SUSPEND(ctx); 5174 CTX_UNLOCK(ctx); 5175 5176 return bus_generic_suspend(dev); 5177 } 5178 int 5179 iflib_device_shutdown(device_t dev) 5180 { 5181 if_ctx_t ctx = device_get_softc(dev); 5182 5183 CTX_LOCK(ctx); 5184 IFDI_SHUTDOWN(ctx); 5185 CTX_UNLOCK(ctx); 5186 5187 return bus_generic_suspend(dev); 5188 } 5189 5190 5191 int 5192 iflib_device_resume(device_t dev) 5193 { 5194 if_ctx_t ctx = device_get_softc(dev); 5195 iflib_txq_t txq = ctx->ifc_txqs; 5196 5197 CTX_LOCK(ctx); 5198 IFDI_RESUME(ctx); 5199 iflib_if_init_locked(ctx); 5200 CTX_UNLOCK(ctx); 5201 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5202 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5203 5204 return (bus_generic_resume(dev)); 5205 } 5206 5207 int 5208 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5209 { 5210 int error; 5211 if_ctx_t ctx = device_get_softc(dev); 5212 5213 CTX_LOCK(ctx); 5214 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5215 CTX_UNLOCK(ctx); 5216 5217 return (error); 5218 } 5219 5220 void 5221 iflib_device_iov_uninit(device_t dev) 5222 { 5223 if_ctx_t ctx = device_get_softc(dev); 5224 5225 CTX_LOCK(ctx); 5226 IFDI_IOV_UNINIT(ctx); 5227 CTX_UNLOCK(ctx); 5228 } 5229 5230 int 5231 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5232 { 5233 int error; 5234 if_ctx_t ctx = device_get_softc(dev); 5235 5236 CTX_LOCK(ctx); 5237 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5238 CTX_UNLOCK(ctx); 5239 5240 return (error); 5241 } 5242 5243 /********************************************************************* 5244 * 5245 * MODULE FUNCTION DEFINITIONS 5246 * 5247 **********************************************************************/ 5248 5249 /* 5250 * - Start a fast taskqueue thread for each core 5251 * - Start a taskqueue for control operations 5252 */ 5253 static int 5254 iflib_module_init(void) 5255 { 5256 return (0); 5257 } 5258 5259 static int 5260 iflib_module_event_handler(module_t mod, int what, void *arg) 5261 { 5262 int err; 5263 5264 switch (what) { 5265 case MOD_LOAD: 5266 if ((err = iflib_module_init()) != 0) 5267 return (err); 5268 break; 5269 case MOD_UNLOAD: 5270 return (EBUSY); 5271 default: 5272 return (EOPNOTSUPP); 5273 } 5274 5275 return (0); 5276 } 5277 5278 /********************************************************************* 5279 * 5280 * PUBLIC FUNCTION DEFINITIONS 5281 * ordered as in iflib.h 5282 * 5283 **********************************************************************/ 5284 5285 5286 static void 5287 _iflib_assert(if_shared_ctx_t sctx) 5288 { 5289 int i; 5290 5291 MPASS(sctx->isc_tx_maxsize); 5292 MPASS(sctx->isc_tx_maxsegsize); 5293 5294 MPASS(sctx->isc_rx_maxsize); 5295 MPASS(sctx->isc_rx_nsegments); 5296 MPASS(sctx->isc_rx_maxsegsize); 5297 5298 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5299 for (i = 0; i < sctx->isc_nrxqs; i++) { 5300 MPASS(sctx->isc_nrxd_min[i]); 5301 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5302 MPASS(sctx->isc_nrxd_max[i]); 5303 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5304 MPASS(sctx->isc_nrxd_default[i]); 5305 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5306 } 5307 5308 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5309 for (i = 0; i < sctx->isc_ntxqs; i++) { 5310 MPASS(sctx->isc_ntxd_min[i]); 5311 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5312 MPASS(sctx->isc_ntxd_max[i]); 5313 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5314 MPASS(sctx->isc_ntxd_default[i]); 5315 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5316 } 5317 } 5318 5319 static void 5320 _iflib_pre_assert(if_softc_ctx_t scctx) 5321 { 5322 5323 MPASS(scctx->isc_txrx->ift_txd_encap); 5324 MPASS(scctx->isc_txrx->ift_txd_flush); 5325 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5326 MPASS(scctx->isc_txrx->ift_rxd_available); 5327 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5328 MPASS(scctx->isc_txrx->ift_rxd_refill); 5329 MPASS(scctx->isc_txrx->ift_rxd_flush); 5330 } 5331 5332 static int 5333 iflib_register(if_ctx_t ctx) 5334 { 5335 if_shared_ctx_t sctx = ctx->ifc_sctx; 5336 driver_t *driver = sctx->isc_driver; 5337 device_t dev = ctx->ifc_dev; 5338 if_t ifp; 5339 5340 _iflib_assert(sctx); 5341 5342 CTX_LOCK_INIT(ctx); 5343 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5344 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5345 if (ifp == NULL) { 5346 device_printf(dev, "can not allocate ifnet structure\n"); 5347 return (ENOMEM); 5348 } 5349 5350 /* 5351 * Initialize our context's device specific methods 5352 */ 5353 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5354 kobj_class_compile((kobj_class_t) driver); 5355 driver->refs++; 5356 5357 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5358 if_setsoftc(ifp, ctx); 5359 if_setdev(ifp, dev); 5360 if_setinitfn(ifp, iflib_if_init); 5361 if_setioctlfn(ifp, iflib_if_ioctl); 5362 #ifdef ALTQ 5363 if_setstartfn(ifp, iflib_altq_if_start); 5364 if_settransmitfn(ifp, iflib_altq_if_transmit); 5365 if_setsendqready(ifp); 5366 #else 5367 if_settransmitfn(ifp, iflib_if_transmit); 5368 #endif 5369 if_setqflushfn(ifp, iflib_if_qflush); 5370 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5371 5372 ctx->ifc_vlan_attach_event = 5373 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5374 EVENTHANDLER_PRI_FIRST); 5375 ctx->ifc_vlan_detach_event = 5376 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5377 EVENTHANDLER_PRI_FIRST); 5378 5379 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5380 ctx->ifc_mediap = &ctx->ifc_media; 5381 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5382 iflib_media_change, iflib_media_status); 5383 } 5384 return (0); 5385 } 5386 5387 static int 5388 iflib_queues_alloc(if_ctx_t ctx) 5389 { 5390 if_shared_ctx_t sctx = ctx->ifc_sctx; 5391 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5392 device_t dev = ctx->ifc_dev; 5393 int nrxqsets = scctx->isc_nrxqsets; 5394 int ntxqsets = scctx->isc_ntxqsets; 5395 iflib_txq_t txq; 5396 iflib_rxq_t rxq; 5397 iflib_fl_t fl = NULL; 5398 int i, j, cpu, err, txconf, rxconf; 5399 iflib_dma_info_t ifdip; 5400 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5401 uint32_t *txqsizes = scctx->isc_txqsizes; 5402 uint8_t nrxqs = sctx->isc_nrxqs; 5403 uint8_t ntxqs = sctx->isc_ntxqs; 5404 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5405 caddr_t *vaddrs; 5406 uint64_t *paddrs; 5407 5408 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5409 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5410 5411 /* Allocate the TX ring struct memory */ 5412 if (!(ctx->ifc_txqs = 5413 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5414 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5415 device_printf(dev, "Unable to allocate TX ring memory\n"); 5416 err = ENOMEM; 5417 goto fail; 5418 } 5419 5420 /* Now allocate the RX */ 5421 if (!(ctx->ifc_rxqs = 5422 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5423 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5424 device_printf(dev, "Unable to allocate RX ring memory\n"); 5425 err = ENOMEM; 5426 goto rx_fail; 5427 } 5428 5429 txq = ctx->ifc_txqs; 5430 rxq = ctx->ifc_rxqs; 5431 5432 /* 5433 * XXX handle allocation failure 5434 */ 5435 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5436 /* Set up some basics */ 5437 5438 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5439 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5440 device_printf(dev, 5441 "Unable to allocate TX DMA info memory\n"); 5442 err = ENOMEM; 5443 goto err_tx_desc; 5444 } 5445 txq->ift_ifdi = ifdip; 5446 for (j = 0; j < ntxqs; j++, ifdip++) { 5447 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5448 device_printf(dev, 5449 "Unable to allocate TX descriptors\n"); 5450 err = ENOMEM; 5451 goto err_tx_desc; 5452 } 5453 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5454 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5455 } 5456 txq->ift_ctx = ctx; 5457 txq->ift_id = i; 5458 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5459 txq->ift_br_offset = 1; 5460 } else { 5461 txq->ift_br_offset = 0; 5462 } 5463 /* XXX fix this */ 5464 txq->ift_timer.c_cpu = cpu; 5465 5466 if (iflib_txsd_alloc(txq)) { 5467 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5468 err = ENOMEM; 5469 goto err_tx_desc; 5470 } 5471 5472 /* Initialize the TX lock */ 5473 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5474 device_get_nameunit(dev), txq->ift_id); 5475 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5476 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5477 5478 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5479 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5480 if (err) { 5481 /* XXX free any allocated rings */ 5482 device_printf(dev, "Unable to allocate buf_ring\n"); 5483 goto err_tx_desc; 5484 } 5485 } 5486 5487 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5488 /* Set up some basics */ 5489 5490 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5491 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5492 device_printf(dev, 5493 "Unable to allocate RX DMA info memory\n"); 5494 err = ENOMEM; 5495 goto err_tx_desc; 5496 } 5497 5498 rxq->ifr_ifdi = ifdip; 5499 /* XXX this needs to be changed if #rx queues != #tx queues */ 5500 rxq->ifr_ntxqirq = 1; 5501 rxq->ifr_txqid[0] = i; 5502 for (j = 0; j < nrxqs; j++, ifdip++) { 5503 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5504 device_printf(dev, 5505 "Unable to allocate RX descriptors\n"); 5506 err = ENOMEM; 5507 goto err_tx_desc; 5508 } 5509 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5510 } 5511 rxq->ifr_ctx = ctx; 5512 rxq->ifr_id = i; 5513 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5514 rxq->ifr_fl_offset = 1; 5515 } else { 5516 rxq->ifr_fl_offset = 0; 5517 } 5518 rxq->ifr_nfl = nfree_lists; 5519 if (!(fl = 5520 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5521 device_printf(dev, "Unable to allocate free list memory\n"); 5522 err = ENOMEM; 5523 goto err_tx_desc; 5524 } 5525 rxq->ifr_fl = fl; 5526 for (j = 0; j < nfree_lists; j++) { 5527 fl[j].ifl_rxq = rxq; 5528 fl[j].ifl_id = j; 5529 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5530 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5531 } 5532 /* Allocate receive buffers for the ring */ 5533 if (iflib_rxsd_alloc(rxq)) { 5534 device_printf(dev, 5535 "Critical Failure setting up receive buffers\n"); 5536 err = ENOMEM; 5537 goto err_rx_desc; 5538 } 5539 5540 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5541 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5542 M_WAITOK); 5543 } 5544 5545 /* TXQs */ 5546 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5547 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5548 for (i = 0; i < ntxqsets; i++) { 5549 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5550 5551 for (j = 0; j < ntxqs; j++, di++) { 5552 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5553 paddrs[i*ntxqs + j] = di->idi_paddr; 5554 } 5555 } 5556 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5557 device_printf(ctx->ifc_dev, 5558 "Unable to allocate device TX queue\n"); 5559 iflib_tx_structures_free(ctx); 5560 free(vaddrs, M_IFLIB); 5561 free(paddrs, M_IFLIB); 5562 goto err_rx_desc; 5563 } 5564 free(vaddrs, M_IFLIB); 5565 free(paddrs, M_IFLIB); 5566 5567 /* RXQs */ 5568 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5569 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5570 for (i = 0; i < nrxqsets; i++) { 5571 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5572 5573 for (j = 0; j < nrxqs; j++, di++) { 5574 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5575 paddrs[i*nrxqs + j] = di->idi_paddr; 5576 } 5577 } 5578 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5579 device_printf(ctx->ifc_dev, 5580 "Unable to allocate device RX queue\n"); 5581 iflib_tx_structures_free(ctx); 5582 free(vaddrs, M_IFLIB); 5583 free(paddrs, M_IFLIB); 5584 goto err_rx_desc; 5585 } 5586 free(vaddrs, M_IFLIB); 5587 free(paddrs, M_IFLIB); 5588 5589 return (0); 5590 5591 /* XXX handle allocation failure changes */ 5592 err_rx_desc: 5593 err_tx_desc: 5594 rx_fail: 5595 if (ctx->ifc_rxqs != NULL) 5596 free(ctx->ifc_rxqs, M_IFLIB); 5597 ctx->ifc_rxqs = NULL; 5598 if (ctx->ifc_txqs != NULL) 5599 free(ctx->ifc_txqs, M_IFLIB); 5600 ctx->ifc_txqs = NULL; 5601 fail: 5602 return (err); 5603 } 5604 5605 static int 5606 iflib_tx_structures_setup(if_ctx_t ctx) 5607 { 5608 iflib_txq_t txq = ctx->ifc_txqs; 5609 int i; 5610 5611 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5612 iflib_txq_setup(txq); 5613 5614 return (0); 5615 } 5616 5617 static void 5618 iflib_tx_structures_free(if_ctx_t ctx) 5619 { 5620 iflib_txq_t txq = ctx->ifc_txqs; 5621 if_shared_ctx_t sctx = ctx->ifc_sctx; 5622 int i, j; 5623 5624 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5625 iflib_txq_destroy(txq); 5626 for (j = 0; j < sctx->isc_ntxqs; j++) 5627 iflib_dma_free(&txq->ift_ifdi[j]); 5628 } 5629 free(ctx->ifc_txqs, M_IFLIB); 5630 ctx->ifc_txqs = NULL; 5631 IFDI_QUEUES_FREE(ctx); 5632 } 5633 5634 /********************************************************************* 5635 * 5636 * Initialize all receive rings. 5637 * 5638 **********************************************************************/ 5639 static int 5640 iflib_rx_structures_setup(if_ctx_t ctx) 5641 { 5642 iflib_rxq_t rxq = ctx->ifc_rxqs; 5643 int q; 5644 #if defined(INET6) || defined(INET) 5645 int err, i; 5646 #endif 5647 5648 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5649 #if defined(INET6) || defined(INET) 5650 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) { 5651 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5652 TCP_LRO_ENTRIES, min(1024, 5653 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 5654 if (err != 0) { 5655 device_printf(ctx->ifc_dev, 5656 "LRO Initialization failed!\n"); 5657 goto fail; 5658 } 5659 } 5660 #endif 5661 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5662 } 5663 return (0); 5664 #if defined(INET6) || defined(INET) 5665 fail: 5666 /* 5667 * Free LRO resources allocated so far, we will only handle 5668 * the rings that completed, the failing case will have 5669 * cleaned up for itself. 'q' failed, so its the terminus. 5670 */ 5671 rxq = ctx->ifc_rxqs; 5672 for (i = 0; i < q; ++i, rxq++) { 5673 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5674 tcp_lro_free(&rxq->ifr_lc); 5675 } 5676 return (err); 5677 #endif 5678 } 5679 5680 /********************************************************************* 5681 * 5682 * Free all receive rings. 5683 * 5684 **********************************************************************/ 5685 static void 5686 iflib_rx_structures_free(if_ctx_t ctx) 5687 { 5688 iflib_rxq_t rxq = ctx->ifc_rxqs; 5689 int i; 5690 5691 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5692 iflib_rx_sds_free(rxq); 5693 #if defined(INET6) || defined(INET) 5694 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5695 tcp_lro_free(&rxq->ifr_lc); 5696 #endif 5697 } 5698 free(ctx->ifc_rxqs, M_IFLIB); 5699 ctx->ifc_rxqs = NULL; 5700 } 5701 5702 static int 5703 iflib_qset_structures_setup(if_ctx_t ctx) 5704 { 5705 int err; 5706 5707 /* 5708 * It is expected that the caller takes care of freeing queues if this 5709 * fails. 5710 */ 5711 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5712 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5713 return (err); 5714 } 5715 5716 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5717 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5718 5719 return (err); 5720 } 5721 5722 int 5723 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5724 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5725 { 5726 5727 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5728 } 5729 5730 #ifdef SMP 5731 static int 5732 find_nth(if_ctx_t ctx, int qid) 5733 { 5734 cpuset_t cpus; 5735 int i, cpuid, eqid, count; 5736 5737 CPU_COPY(&ctx->ifc_cpus, &cpus); 5738 count = CPU_COUNT(&cpus); 5739 eqid = qid % count; 5740 /* clear up to the qid'th bit */ 5741 for (i = 0; i < eqid; i++) { 5742 cpuid = CPU_FFS(&cpus); 5743 MPASS(cpuid != 0); 5744 CPU_CLR(cpuid-1, &cpus); 5745 } 5746 cpuid = CPU_FFS(&cpus); 5747 MPASS(cpuid != 0); 5748 return (cpuid-1); 5749 } 5750 5751 #ifdef SCHED_ULE 5752 extern struct cpu_group *cpu_top; /* CPU topology */ 5753 5754 static int 5755 find_child_with_core(int cpu, struct cpu_group *grp) 5756 { 5757 int i; 5758 5759 if (grp->cg_children == 0) 5760 return -1; 5761 5762 MPASS(grp->cg_child); 5763 for (i = 0; i < grp->cg_children; i++) { 5764 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5765 return i; 5766 } 5767 5768 return -1; 5769 } 5770 5771 /* 5772 * Find the nth "close" core to the specified core 5773 * "close" is defined as the deepest level that shares 5774 * at least an L2 cache. With threads, this will be 5775 * threads on the same core. If the shared cache is L3 5776 * or higher, simply returns the same core. 5777 */ 5778 static int 5779 find_close_core(int cpu, int core_offset) 5780 { 5781 struct cpu_group *grp; 5782 int i; 5783 int fcpu; 5784 cpuset_t cs; 5785 5786 grp = cpu_top; 5787 if (grp == NULL) 5788 return cpu; 5789 i = 0; 5790 while ((i = find_child_with_core(cpu, grp)) != -1) { 5791 /* If the child only has one cpu, don't descend */ 5792 if (grp->cg_child[i].cg_count <= 1) 5793 break; 5794 grp = &grp->cg_child[i]; 5795 } 5796 5797 /* If they don't share at least an L2 cache, use the same CPU */ 5798 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5799 return cpu; 5800 5801 /* Now pick one */ 5802 CPU_COPY(&grp->cg_mask, &cs); 5803 5804 /* Add the selected CPU offset to core offset. */ 5805 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5806 if (fcpu - 1 == cpu) 5807 break; 5808 CPU_CLR(fcpu - 1, &cs); 5809 } 5810 MPASS(fcpu); 5811 5812 core_offset += i; 5813 5814 CPU_COPY(&grp->cg_mask, &cs); 5815 for (i = core_offset % grp->cg_count; i > 0; i--) { 5816 MPASS(CPU_FFS(&cs)); 5817 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5818 } 5819 MPASS(CPU_FFS(&cs)); 5820 return CPU_FFS(&cs) - 1; 5821 } 5822 #else 5823 static int 5824 find_close_core(int cpu, int core_offset __unused) 5825 { 5826 return cpu; 5827 } 5828 #endif 5829 5830 static int 5831 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5832 { 5833 switch (type) { 5834 case IFLIB_INTR_TX: 5835 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5836 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5837 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5838 case IFLIB_INTR_RX: 5839 case IFLIB_INTR_RXTX: 5840 /* RX queues get the specified core */ 5841 return qid / CPU_COUNT(&ctx->ifc_cpus); 5842 default: 5843 return -1; 5844 } 5845 } 5846 #else 5847 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5848 #define find_close_core(cpuid, tid) CPU_FIRST() 5849 #define find_nth(ctx, gid) CPU_FIRST() 5850 #endif 5851 5852 /* Just to avoid copy/paste */ 5853 static inline int 5854 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5855 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5856 const char *name) 5857 { 5858 device_t dev; 5859 int co, cpuid, err, tid; 5860 5861 dev = ctx->ifc_dev; 5862 co = ctx->ifc_sysctl_core_offset; 5863 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX) 5864 co += ctx->ifc_softc_ctx.isc_nrxqsets; 5865 cpuid = find_nth(ctx, qid + co); 5866 tid = get_core_offset(ctx, type, qid); 5867 if (tid < 0) { 5868 device_printf(dev, "get_core_offset failed\n"); 5869 return (EOPNOTSUPP); 5870 } 5871 cpuid = find_close_core(cpuid, tid); 5872 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 5873 name); 5874 if (err) { 5875 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 5876 return (err); 5877 } 5878 #ifdef notyet 5879 if (cpuid > ctx->ifc_cpuid_highest) 5880 ctx->ifc_cpuid_highest = cpuid; 5881 #endif 5882 return (0); 5883 } 5884 5885 int 5886 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5887 iflib_intr_type_t type, driver_filter_t *filter, 5888 void *filter_arg, int qid, const char *name) 5889 { 5890 device_t dev; 5891 struct grouptask *gtask; 5892 struct taskqgroup *tqg; 5893 iflib_filter_info_t info; 5894 gtask_fn_t *fn; 5895 int tqrid, err; 5896 driver_filter_t *intr_fast; 5897 void *q; 5898 5899 info = &ctx->ifc_filter_info; 5900 tqrid = rid; 5901 5902 switch (type) { 5903 /* XXX merge tx/rx for netmap? */ 5904 case IFLIB_INTR_TX: 5905 q = &ctx->ifc_txqs[qid]; 5906 info = &ctx->ifc_txqs[qid].ift_filter_info; 5907 gtask = &ctx->ifc_txqs[qid].ift_task; 5908 tqg = qgroup_if_io_tqg; 5909 fn = _task_fn_tx; 5910 intr_fast = iflib_fast_intr; 5911 GROUPTASK_INIT(gtask, 0, fn, q); 5912 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5913 break; 5914 case IFLIB_INTR_RX: 5915 q = &ctx->ifc_rxqs[qid]; 5916 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5917 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5918 tqg = qgroup_if_io_tqg; 5919 fn = _task_fn_rx; 5920 intr_fast = iflib_fast_intr; 5921 GROUPTASK_INIT(gtask, 0, fn, q); 5922 break; 5923 case IFLIB_INTR_RXTX: 5924 q = &ctx->ifc_rxqs[qid]; 5925 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5926 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5927 tqg = qgroup_if_io_tqg; 5928 fn = _task_fn_rx; 5929 intr_fast = iflib_fast_intr_rxtx; 5930 GROUPTASK_INIT(gtask, 0, fn, q); 5931 break; 5932 case IFLIB_INTR_ADMIN: 5933 q = ctx; 5934 tqrid = -1; 5935 info = &ctx->ifc_filter_info; 5936 gtask = &ctx->ifc_admin_task; 5937 tqg = qgroup_if_config_tqg; 5938 fn = _task_fn_admin; 5939 intr_fast = iflib_fast_intr_ctx; 5940 break; 5941 default: 5942 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 5943 __func__); 5944 return (EINVAL); 5945 } 5946 5947 info->ifi_filter = filter; 5948 info->ifi_filter_arg = filter_arg; 5949 info->ifi_task = gtask; 5950 info->ifi_ctx = q; 5951 5952 dev = ctx->ifc_dev; 5953 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5954 if (err != 0) { 5955 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 5956 return (err); 5957 } 5958 if (type == IFLIB_INTR_ADMIN) 5959 return (0); 5960 5961 if (tqrid != -1) { 5962 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 5963 q, name); 5964 if (err) 5965 return (err); 5966 } else { 5967 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 5968 } 5969 5970 return (0); 5971 } 5972 5973 void 5974 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 5975 { 5976 struct grouptask *gtask; 5977 struct taskqgroup *tqg; 5978 gtask_fn_t *fn; 5979 void *q; 5980 int err; 5981 5982 switch (type) { 5983 case IFLIB_INTR_TX: 5984 q = &ctx->ifc_txqs[qid]; 5985 gtask = &ctx->ifc_txqs[qid].ift_task; 5986 tqg = qgroup_if_io_tqg; 5987 fn = _task_fn_tx; 5988 break; 5989 case IFLIB_INTR_RX: 5990 q = &ctx->ifc_rxqs[qid]; 5991 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5992 tqg = qgroup_if_io_tqg; 5993 fn = _task_fn_rx; 5994 break; 5995 case IFLIB_INTR_IOV: 5996 q = ctx; 5997 gtask = &ctx->ifc_vflr_task; 5998 tqg = qgroup_if_config_tqg; 5999 fn = _task_fn_iov; 6000 break; 6001 default: 6002 panic("unknown net intr type"); 6003 } 6004 GROUPTASK_INIT(gtask, 0, fn, q); 6005 if (irq != NULL) { 6006 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6007 q, name); 6008 if (err) 6009 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 6010 irq->ii_res, name); 6011 } else { 6012 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 6013 } 6014 } 6015 6016 void 6017 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6018 { 6019 6020 if (irq->ii_tag) 6021 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6022 6023 if (irq->ii_res) 6024 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6025 rman_get_rid(irq->ii_res), irq->ii_res); 6026 } 6027 6028 static int 6029 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6030 { 6031 iflib_txq_t txq = ctx->ifc_txqs; 6032 iflib_rxq_t rxq = ctx->ifc_rxqs; 6033 if_irq_t irq = &ctx->ifc_legacy_irq; 6034 iflib_filter_info_t info; 6035 device_t dev; 6036 struct grouptask *gtask; 6037 struct resource *res; 6038 struct taskqgroup *tqg; 6039 gtask_fn_t *fn; 6040 int tqrid; 6041 void *q; 6042 int err; 6043 6044 q = &ctx->ifc_rxqs[0]; 6045 info = &rxq[0].ifr_filter_info; 6046 gtask = &rxq[0].ifr_task; 6047 tqg = qgroup_if_io_tqg; 6048 tqrid = irq->ii_rid = *rid; 6049 fn = _task_fn_rx; 6050 6051 ctx->ifc_flags |= IFC_LEGACY; 6052 info->ifi_filter = filter; 6053 info->ifi_filter_arg = filter_arg; 6054 info->ifi_task = gtask; 6055 info->ifi_ctx = q; 6056 6057 dev = ctx->ifc_dev; 6058 /* We allocate a single interrupt resource */ 6059 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_rxtx, 6060 NULL, info, name)) != 0) 6061 return (err); 6062 GROUPTASK_INIT(gtask, 0, fn, q); 6063 res = irq->ii_res; 6064 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6065 6066 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6067 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6068 "tx"); 6069 return (0); 6070 } 6071 6072 void 6073 iflib_led_create(if_ctx_t ctx) 6074 { 6075 6076 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6077 device_get_nameunit(ctx->ifc_dev)); 6078 } 6079 6080 void 6081 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6082 { 6083 6084 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6085 } 6086 6087 void 6088 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6089 { 6090 6091 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6092 } 6093 6094 void 6095 iflib_admin_intr_deferred(if_ctx_t ctx) 6096 { 6097 #ifdef INVARIANTS 6098 struct grouptask *gtask; 6099 6100 gtask = &ctx->ifc_admin_task; 6101 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 6102 #endif 6103 6104 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6105 } 6106 6107 void 6108 iflib_iov_intr_deferred(if_ctx_t ctx) 6109 { 6110 6111 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6112 } 6113 6114 void 6115 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 6116 { 6117 6118 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6119 name); 6120 } 6121 6122 void 6123 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6124 const char *name) 6125 { 6126 6127 GROUPTASK_INIT(gtask, 0, fn, ctx); 6128 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6129 name); 6130 } 6131 6132 void 6133 iflib_config_gtask_deinit(struct grouptask *gtask) 6134 { 6135 6136 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6137 } 6138 6139 void 6140 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6141 { 6142 if_t ifp = ctx->ifc_ifp; 6143 iflib_txq_t txq = ctx->ifc_txqs; 6144 6145 if_setbaudrate(ifp, baudrate); 6146 if (baudrate >= IF_Gbps(10)) { 6147 STATE_LOCK(ctx); 6148 ctx->ifc_flags |= IFC_PREFETCH; 6149 STATE_UNLOCK(ctx); 6150 } 6151 /* If link down, disable watchdog */ 6152 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6153 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6154 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6155 } 6156 ctx->ifc_link_state = link_state; 6157 if_link_state_change(ifp, link_state); 6158 } 6159 6160 static int 6161 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6162 { 6163 int credits; 6164 #ifdef INVARIANTS 6165 int credits_pre = txq->ift_cidx_processed; 6166 #endif 6167 6168 if (ctx->isc_txd_credits_update == NULL) 6169 return (0); 6170 6171 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6172 BUS_DMASYNC_POSTREAD); 6173 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6174 return (0); 6175 6176 txq->ift_processed += credits; 6177 txq->ift_cidx_processed += credits; 6178 6179 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6180 if (txq->ift_cidx_processed >= txq->ift_size) 6181 txq->ift_cidx_processed -= txq->ift_size; 6182 return (credits); 6183 } 6184 6185 static int 6186 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6187 { 6188 iflib_fl_t fl; 6189 u_int i; 6190 6191 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6192 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6193 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6194 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6195 budget)); 6196 } 6197 6198 void 6199 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6200 const char *description, if_int_delay_info_t info, 6201 int offset, int value) 6202 { 6203 info->iidi_ctx = ctx; 6204 info->iidi_offset = offset; 6205 info->iidi_value = value; 6206 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6207 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6208 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 6209 info, 0, iflib_sysctl_int_delay, "I", description); 6210 } 6211 6212 struct sx * 6213 iflib_ctx_lock_get(if_ctx_t ctx) 6214 { 6215 6216 return (&ctx->ifc_ctx_sx); 6217 } 6218 6219 static int 6220 iflib_msix_init(if_ctx_t ctx) 6221 { 6222 device_t dev = ctx->ifc_dev; 6223 if_shared_ctx_t sctx = ctx->ifc_sctx; 6224 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6225 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6226 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6227 6228 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6229 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6230 6231 if (bootverbose) 6232 device_printf(dev, "msix_init qsets capped at %d\n", 6233 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6234 6235 /* Override by tuneable */ 6236 if (scctx->isc_disable_msix) 6237 goto msi; 6238 6239 /* First try MSI-X */ 6240 if ((msgs = pci_msix_count(dev)) == 0) { 6241 if (bootverbose) 6242 device_printf(dev, "MSI-X not supported or disabled\n"); 6243 goto msi; 6244 } 6245 6246 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6247 /* 6248 * bar == -1 => "trust me I know what I'm doing" 6249 * Some drivers are for hardware that is so shoddily 6250 * documented that no one knows which bars are which 6251 * so the developer has to map all bars. This hack 6252 * allows shoddy garbage to use MSI-X in this framework. 6253 */ 6254 if (bar != -1) { 6255 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6256 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6257 if (ctx->ifc_msix_mem == NULL) { 6258 device_printf(dev, "Unable to map MSI-X table\n"); 6259 goto msi; 6260 } 6261 } 6262 6263 admincnt = sctx->isc_admin_intrcnt; 6264 #if IFLIB_DEBUG 6265 /* use only 1 qset in debug mode */ 6266 queuemsgs = min(msgs - admincnt, 1); 6267 #else 6268 queuemsgs = msgs - admincnt; 6269 #endif 6270 #ifdef RSS 6271 queues = imin(queuemsgs, rss_getnumbuckets()); 6272 #else 6273 queues = queuemsgs; 6274 #endif 6275 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6276 if (bootverbose) 6277 device_printf(dev, 6278 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6279 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6280 #ifdef RSS 6281 /* If we're doing RSS, clamp at the number of RSS buckets */ 6282 if (queues > rss_getnumbuckets()) 6283 queues = rss_getnumbuckets(); 6284 #endif 6285 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6286 rx_queues = iflib_num_rx_queues; 6287 else 6288 rx_queues = queues; 6289 6290 if (rx_queues > scctx->isc_nrxqsets) 6291 rx_queues = scctx->isc_nrxqsets; 6292 6293 /* 6294 * We want this to be all logical CPUs by default 6295 */ 6296 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6297 tx_queues = iflib_num_tx_queues; 6298 else 6299 tx_queues = mp_ncpus; 6300 6301 if (tx_queues > scctx->isc_ntxqsets) 6302 tx_queues = scctx->isc_ntxqsets; 6303 6304 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6305 #ifdef INVARIANTS 6306 if (tx_queues != rx_queues) 6307 device_printf(dev, 6308 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6309 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6310 #endif 6311 tx_queues = min(rx_queues, tx_queues); 6312 rx_queues = min(rx_queues, tx_queues); 6313 } 6314 6315 vectors = rx_queues + admincnt; 6316 if (msgs < vectors) { 6317 device_printf(dev, 6318 "insufficient number of MSI-X vectors " 6319 "(supported %d, need %d)\n", msgs, vectors); 6320 goto msi; 6321 } 6322 6323 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6324 tx_queues); 6325 msgs = vectors; 6326 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6327 if (vectors != msgs) { 6328 device_printf(dev, 6329 "Unable to allocate sufficient MSI-X vectors " 6330 "(got %d, need %d)\n", vectors, msgs); 6331 pci_release_msi(dev); 6332 if (bar != -1) { 6333 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6334 ctx->ifc_msix_mem); 6335 ctx->ifc_msix_mem = NULL; 6336 } 6337 goto msi; 6338 } 6339 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6340 vectors); 6341 scctx->isc_vectors = vectors; 6342 scctx->isc_nrxqsets = rx_queues; 6343 scctx->isc_ntxqsets = tx_queues; 6344 scctx->isc_intr = IFLIB_INTR_MSIX; 6345 6346 return (vectors); 6347 } else { 6348 device_printf(dev, 6349 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6350 err); 6351 if (bar != -1) { 6352 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6353 ctx->ifc_msix_mem); 6354 ctx->ifc_msix_mem = NULL; 6355 } 6356 } 6357 6358 msi: 6359 vectors = pci_msi_count(dev); 6360 scctx->isc_nrxqsets = 1; 6361 scctx->isc_ntxqsets = 1; 6362 scctx->isc_vectors = vectors; 6363 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6364 device_printf(dev,"Using an MSI interrupt\n"); 6365 scctx->isc_intr = IFLIB_INTR_MSI; 6366 } else { 6367 scctx->isc_vectors = 1; 6368 device_printf(dev,"Using a Legacy interrupt\n"); 6369 scctx->isc_intr = IFLIB_INTR_LEGACY; 6370 } 6371 6372 return (vectors); 6373 } 6374 6375 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6376 6377 static int 6378 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6379 { 6380 int rc; 6381 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6382 struct sbuf *sb; 6383 const char *ring_state = "UNKNOWN"; 6384 6385 /* XXX needed ? */ 6386 rc = sysctl_wire_old_buffer(req, 0); 6387 MPASS(rc == 0); 6388 if (rc != 0) 6389 return (rc); 6390 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6391 MPASS(sb != NULL); 6392 if (sb == NULL) 6393 return (ENOMEM); 6394 if (state[3] <= 3) 6395 ring_state = ring_states[state[3]]; 6396 6397 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6398 state[0], state[1], state[2], ring_state); 6399 rc = sbuf_finish(sb); 6400 sbuf_delete(sb); 6401 return(rc); 6402 } 6403 6404 enum iflib_ndesc_handler { 6405 IFLIB_NTXD_HANDLER, 6406 IFLIB_NRXD_HANDLER, 6407 }; 6408 6409 static int 6410 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6411 { 6412 if_ctx_t ctx = (void *)arg1; 6413 enum iflib_ndesc_handler type = arg2; 6414 char buf[256] = {0}; 6415 qidx_t *ndesc; 6416 char *p, *next; 6417 int nqs, rc, i; 6418 6419 nqs = 8; 6420 switch(type) { 6421 case IFLIB_NTXD_HANDLER: 6422 ndesc = ctx->ifc_sysctl_ntxds; 6423 if (ctx->ifc_sctx) 6424 nqs = ctx->ifc_sctx->isc_ntxqs; 6425 break; 6426 case IFLIB_NRXD_HANDLER: 6427 ndesc = ctx->ifc_sysctl_nrxds; 6428 if (ctx->ifc_sctx) 6429 nqs = ctx->ifc_sctx->isc_nrxqs; 6430 break; 6431 default: 6432 printf("%s: unhandled type\n", __func__); 6433 return (EINVAL); 6434 } 6435 if (nqs == 0) 6436 nqs = 8; 6437 6438 for (i=0; i<8; i++) { 6439 if (i >= nqs) 6440 break; 6441 if (i) 6442 strcat(buf, ","); 6443 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6444 } 6445 6446 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6447 if (rc || req->newptr == NULL) 6448 return rc; 6449 6450 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6451 i++, p = strsep(&next, " ,")) { 6452 ndesc[i] = strtoul(p, NULL, 10); 6453 } 6454 6455 return(rc); 6456 } 6457 6458 #define NAME_BUFLEN 32 6459 static void 6460 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6461 { 6462 device_t dev = iflib_get_dev(ctx); 6463 struct sysctl_oid_list *child, *oid_list; 6464 struct sysctl_ctx_list *ctx_list; 6465 struct sysctl_oid *node; 6466 6467 ctx_list = device_get_sysctl_ctx(dev); 6468 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6469 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6470 CTLFLAG_RD, NULL, "IFLIB fields"); 6471 oid_list = SYSCTL_CHILDREN(node); 6472 6473 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6474 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6475 "driver version"); 6476 6477 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6478 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6479 "# of txqs to use, 0 => use default #"); 6480 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6481 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6482 "# of rxqs to use, 0 => use default #"); 6483 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6484 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6485 "permit #txq != #rxq"); 6486 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6487 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6488 "disable MSI-X (default 0)"); 6489 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6490 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6491 "set the RX budget"); 6492 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6493 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6494 "cause TX to abdicate instead of running to completion"); 6495 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6496 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6497 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6498 "offset to start using cores at"); 6499 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6500 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6501 "use separate cores for TX and RX"); 6502 6503 /* XXX change for per-queue sizes */ 6504 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6505 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6506 mp_ndesc_handler, "A", 6507 "list of # of TX descriptors to use, 0 = use default #"); 6508 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6509 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6510 mp_ndesc_handler, "A", 6511 "list of # of RX descriptors to use, 0 = use default #"); 6512 } 6513 6514 static void 6515 iflib_add_device_sysctl_post(if_ctx_t ctx) 6516 { 6517 if_shared_ctx_t sctx = ctx->ifc_sctx; 6518 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6519 device_t dev = iflib_get_dev(ctx); 6520 struct sysctl_oid_list *child; 6521 struct sysctl_ctx_list *ctx_list; 6522 iflib_fl_t fl; 6523 iflib_txq_t txq; 6524 iflib_rxq_t rxq; 6525 int i, j; 6526 char namebuf[NAME_BUFLEN]; 6527 char *qfmt; 6528 struct sysctl_oid *queue_node, *fl_node, *node; 6529 struct sysctl_oid_list *queue_list, *fl_list; 6530 ctx_list = device_get_sysctl_ctx(dev); 6531 6532 node = ctx->ifc_sysctl_node; 6533 child = SYSCTL_CHILDREN(node); 6534 6535 if (scctx->isc_ntxqsets > 100) 6536 qfmt = "txq%03d"; 6537 else if (scctx->isc_ntxqsets > 10) 6538 qfmt = "txq%02d"; 6539 else 6540 qfmt = "txq%d"; 6541 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6542 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6543 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6544 CTLFLAG_RD, NULL, "Queue Name"); 6545 queue_list = SYSCTL_CHILDREN(queue_node); 6546 #if MEMORY_LOGGING 6547 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6548 CTLFLAG_RD, 6549 &txq->ift_dequeued, "total mbufs freed"); 6550 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6551 CTLFLAG_RD, 6552 &txq->ift_enqueued, "total mbufs enqueued"); 6553 #endif 6554 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6555 CTLFLAG_RD, 6556 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6557 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6558 CTLFLAG_RD, 6559 &txq->ift_pullups, "# of times m_pullup was called"); 6560 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6561 CTLFLAG_RD, 6562 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6563 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6564 CTLFLAG_RD, 6565 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6566 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6567 CTLFLAG_RD, 6568 &txq->ift_map_failed, "# of times DMA map failed"); 6569 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6570 CTLFLAG_RD, 6571 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6572 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6573 CTLFLAG_RD, 6574 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6575 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6576 CTLFLAG_RD, 6577 &txq->ift_pidx, 1, "Producer Index"); 6578 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6579 CTLFLAG_RD, 6580 &txq->ift_cidx, 1, "Consumer Index"); 6581 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6582 CTLFLAG_RD, 6583 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6584 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6585 CTLFLAG_RD, 6586 &txq->ift_in_use, 1, "descriptors in use"); 6587 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6588 CTLFLAG_RD, 6589 &txq->ift_processed, "descriptors procesed for clean"); 6590 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6591 CTLFLAG_RD, 6592 &txq->ift_cleaned, "total cleaned"); 6593 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6594 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6595 0, mp_ring_state_handler, "A", "soft ring state"); 6596 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6597 CTLFLAG_RD, &txq->ift_br->enqueues, 6598 "# of enqueues to the mp_ring for this queue"); 6599 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6600 CTLFLAG_RD, &txq->ift_br->drops, 6601 "# of drops in the mp_ring for this queue"); 6602 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6603 CTLFLAG_RD, &txq->ift_br->starts, 6604 "# of normal consumer starts in the mp_ring for this queue"); 6605 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6606 CTLFLAG_RD, &txq->ift_br->stalls, 6607 "# of consumer stalls in the mp_ring for this queue"); 6608 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6609 CTLFLAG_RD, &txq->ift_br->restarts, 6610 "# of consumer restarts in the mp_ring for this queue"); 6611 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6612 CTLFLAG_RD, &txq->ift_br->abdications, 6613 "# of consumer abdications in the mp_ring for this queue"); 6614 } 6615 6616 if (scctx->isc_nrxqsets > 100) 6617 qfmt = "rxq%03d"; 6618 else if (scctx->isc_nrxqsets > 10) 6619 qfmt = "rxq%02d"; 6620 else 6621 qfmt = "rxq%d"; 6622 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6623 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6624 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6625 CTLFLAG_RD, NULL, "Queue Name"); 6626 queue_list = SYSCTL_CHILDREN(queue_node); 6627 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6628 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6629 CTLFLAG_RD, 6630 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6631 } 6632 6633 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6634 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6635 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6636 CTLFLAG_RD, NULL, "freelist Name"); 6637 fl_list = SYSCTL_CHILDREN(fl_node); 6638 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6639 CTLFLAG_RD, 6640 &fl->ifl_pidx, 1, "Producer Index"); 6641 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6642 CTLFLAG_RD, 6643 &fl->ifl_cidx, 1, "Consumer Index"); 6644 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6645 CTLFLAG_RD, 6646 &fl->ifl_credits, 1, "credits available"); 6647 #if MEMORY_LOGGING 6648 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6649 CTLFLAG_RD, 6650 &fl->ifl_m_enqueued, "mbufs allocated"); 6651 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6652 CTLFLAG_RD, 6653 &fl->ifl_m_dequeued, "mbufs freed"); 6654 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6655 CTLFLAG_RD, 6656 &fl->ifl_cl_enqueued, "clusters allocated"); 6657 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6658 CTLFLAG_RD, 6659 &fl->ifl_cl_dequeued, "clusters freed"); 6660 #endif 6661 6662 } 6663 } 6664 6665 } 6666 6667 void 6668 iflib_request_reset(if_ctx_t ctx) 6669 { 6670 6671 STATE_LOCK(ctx); 6672 ctx->ifc_flags |= IFC_DO_RESET; 6673 STATE_UNLOCK(ctx); 6674 } 6675 6676 #ifndef __NO_STRICT_ALIGNMENT 6677 static struct mbuf * 6678 iflib_fixup_rx(struct mbuf *m) 6679 { 6680 struct mbuf *n; 6681 6682 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6683 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6684 m->m_data += ETHER_HDR_LEN; 6685 n = m; 6686 } else { 6687 MGETHDR(n, M_NOWAIT, MT_DATA); 6688 if (n == NULL) { 6689 m_freem(m); 6690 return (NULL); 6691 } 6692 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6693 m->m_data += ETHER_HDR_LEN; 6694 m->m_len -= ETHER_HDR_LEN; 6695 n->m_len = ETHER_HDR_LEN; 6696 M_MOVE_PKTHDR(n, m); 6697 n->m_next = m; 6698 } 6699 return (n); 6700 } 6701 #endif 6702 6703 #ifdef NETDUMP 6704 static void 6705 iflib_netdump_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6706 { 6707 if_ctx_t ctx; 6708 6709 ctx = if_getsoftc(ifp); 6710 CTX_LOCK(ctx); 6711 *nrxr = NRXQSETS(ctx); 6712 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6713 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6714 CTX_UNLOCK(ctx); 6715 } 6716 6717 static void 6718 iflib_netdump_event(if_t ifp, enum netdump_ev event) 6719 { 6720 if_ctx_t ctx; 6721 if_softc_ctx_t scctx; 6722 iflib_fl_t fl; 6723 iflib_rxq_t rxq; 6724 int i, j; 6725 6726 ctx = if_getsoftc(ifp); 6727 scctx = &ctx->ifc_softc_ctx; 6728 6729 switch (event) { 6730 case NETDUMP_START: 6731 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6732 rxq = &ctx->ifc_rxqs[i]; 6733 for (j = 0; j < rxq->ifr_nfl; j++) { 6734 fl = rxq->ifr_fl; 6735 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6736 } 6737 } 6738 iflib_no_tx_batch = 1; 6739 break; 6740 default: 6741 break; 6742 } 6743 } 6744 6745 static int 6746 iflib_netdump_transmit(if_t ifp, struct mbuf *m) 6747 { 6748 if_ctx_t ctx; 6749 iflib_txq_t txq; 6750 int error; 6751 6752 ctx = if_getsoftc(ifp); 6753 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6754 IFF_DRV_RUNNING) 6755 return (EBUSY); 6756 6757 txq = &ctx->ifc_txqs[0]; 6758 error = iflib_encap(txq, &m); 6759 if (error == 0) 6760 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6761 return (error); 6762 } 6763 6764 static int 6765 iflib_netdump_poll(if_t ifp, int count) 6766 { 6767 if_ctx_t ctx; 6768 if_softc_ctx_t scctx; 6769 iflib_txq_t txq; 6770 int i; 6771 6772 ctx = if_getsoftc(ifp); 6773 scctx = &ctx->ifc_softc_ctx; 6774 6775 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6776 IFF_DRV_RUNNING) 6777 return (EBUSY); 6778 6779 txq = &ctx->ifc_txqs[0]; 6780 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6781 6782 for (i = 0; i < scctx->isc_nrxqsets; i++) 6783 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6784 return (0); 6785 } 6786 #endif /* NETDUMP */ 6787