1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 120 /* 121 * File organization: 122 * - private structures 123 * - iflib private utility functions 124 * - ifnet functions 125 * - vlan registry and other exported functions 126 * - iflib public core functions 127 * 128 * 129 */ 130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 131 132 #define IFLIB_RXEOF_MORE (1U << 0) 133 #define IFLIB_RXEOF_EMPTY (2U << 0) 134 135 struct iflib_txq; 136 typedef struct iflib_txq *iflib_txq_t; 137 struct iflib_rxq; 138 typedef struct iflib_rxq *iflib_rxq_t; 139 struct iflib_fl; 140 typedef struct iflib_fl *iflib_fl_t; 141 142 struct iflib_ctx; 143 144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 145 static void iflib_timer(void *arg); 146 147 typedef struct iflib_filter_info { 148 driver_filter_t *ifi_filter; 149 void *ifi_filter_arg; 150 struct grouptask *ifi_task; 151 void *ifi_ctx; 152 } *iflib_filter_info_t; 153 154 struct iflib_ctx { 155 KOBJ_FIELDS; 156 /* 157 * Pointer to hardware driver's softc 158 */ 159 void *ifc_softc; 160 device_t ifc_dev; 161 if_t ifc_ifp; 162 163 cpuset_t ifc_cpus; 164 if_shared_ctx_t ifc_sctx; 165 struct if_softc_ctx ifc_softc_ctx; 166 167 struct sx ifc_ctx_sx; 168 struct mtx ifc_state_mtx; 169 170 iflib_txq_t ifc_txqs; 171 iflib_rxq_t ifc_rxqs; 172 uint32_t ifc_if_flags; 173 uint32_t ifc_flags; 174 uint32_t ifc_max_fl_buf_size; 175 uint32_t ifc_rx_mbuf_sz; 176 177 int ifc_link_state; 178 int ifc_watchdog_events; 179 struct cdev *ifc_led_dev; 180 struct resource *ifc_msix_mem; 181 182 struct if_irq ifc_legacy_irq; 183 struct grouptask ifc_admin_task; 184 struct grouptask ifc_vflr_task; 185 struct iflib_filter_info ifc_filter_info; 186 struct ifmedia ifc_media; 187 struct ifmedia *ifc_mediap; 188 189 struct sysctl_oid *ifc_sysctl_node; 190 uint16_t ifc_sysctl_ntxqs; 191 uint16_t ifc_sysctl_nrxqs; 192 uint16_t ifc_sysctl_qs_eq_override; 193 uint16_t ifc_sysctl_rx_budget; 194 uint16_t ifc_sysctl_tx_abdicate; 195 uint16_t ifc_sysctl_core_offset; 196 #define CORE_OFFSET_UNSPECIFIED 0xffff 197 uint8_t ifc_sysctl_separate_txrx; 198 199 qidx_t ifc_sysctl_ntxds[8]; 200 qidx_t ifc_sysctl_nrxds[8]; 201 struct if_txrx ifc_txrx; 202 #define isc_txd_encap ifc_txrx.ift_txd_encap 203 #define isc_txd_flush ifc_txrx.ift_txd_flush 204 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 205 #define isc_rxd_available ifc_txrx.ift_rxd_available 206 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 209 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 210 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 211 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 212 eventhandler_tag ifc_vlan_attach_event; 213 eventhandler_tag ifc_vlan_detach_event; 214 struct ether_addr ifc_mac; 215 }; 216 217 void * 218 iflib_get_softc(if_ctx_t ctx) 219 { 220 221 return (ctx->ifc_softc); 222 } 223 224 device_t 225 iflib_get_dev(if_ctx_t ctx) 226 { 227 228 return (ctx->ifc_dev); 229 } 230 231 if_t 232 iflib_get_ifp(if_ctx_t ctx) 233 { 234 235 return (ctx->ifc_ifp); 236 } 237 238 struct ifmedia * 239 iflib_get_media(if_ctx_t ctx) 240 { 241 242 return (ctx->ifc_mediap); 243 } 244 245 uint32_t 246 iflib_get_flags(if_ctx_t ctx) 247 { 248 return (ctx->ifc_flags); 249 } 250 251 void 252 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 253 { 254 255 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 256 } 257 258 if_softc_ctx_t 259 iflib_get_softc_ctx(if_ctx_t ctx) 260 { 261 262 return (&ctx->ifc_softc_ctx); 263 } 264 265 if_shared_ctx_t 266 iflib_get_sctx(if_ctx_t ctx) 267 { 268 269 return (ctx->ifc_sctx); 270 } 271 272 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 273 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 274 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 275 276 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 277 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 278 279 typedef struct iflib_sw_rx_desc_array { 280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 281 struct mbuf **ifsd_m; /* pkthdr mbufs */ 282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 283 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 284 } iflib_rxsd_array_t; 285 286 typedef struct iflib_sw_tx_desc_array { 287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 288 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 289 struct mbuf **ifsd_m; /* pkthdr mbufs */ 290 } if_txsd_vec_t; 291 292 /* magic number that should be high enough for any hardware */ 293 #define IFLIB_MAX_TX_SEGS 128 294 #define IFLIB_RX_COPY_THRESH 128 295 #define IFLIB_MAX_RX_REFRESH 32 296 /* The minimum descriptors per second before we start coalescing */ 297 #define IFLIB_MIN_DESC_SEC 16384 298 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 299 #define IFLIB_QUEUE_IDLE 0 300 #define IFLIB_QUEUE_HUNG 1 301 #define IFLIB_QUEUE_WORKING 2 302 /* maximum number of txqs that can share an rx interrupt */ 303 #define IFLIB_MAX_TX_SHARED_INTR 4 304 305 /* this should really scale with ring size - this is a fairly arbitrary value */ 306 #define TX_BATCH_SIZE 32 307 308 #define IFLIB_RESTART_BUDGET 8 309 310 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 311 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 312 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 313 314 struct iflib_txq { 315 qidx_t ift_in_use; 316 qidx_t ift_cidx; 317 qidx_t ift_cidx_processed; 318 qidx_t ift_pidx; 319 uint8_t ift_gen; 320 uint8_t ift_br_offset; 321 uint16_t ift_npending; 322 uint16_t ift_db_pending; 323 uint16_t ift_rs_pending; 324 /* implicit pad */ 325 uint8_t ift_txd_size[8]; 326 uint64_t ift_processed; 327 uint64_t ift_cleaned; 328 uint64_t ift_cleaned_prev; 329 #if MEMORY_LOGGING 330 uint64_t ift_enqueued; 331 uint64_t ift_dequeued; 332 #endif 333 uint64_t ift_no_tx_dma_setup; 334 uint64_t ift_no_desc_avail; 335 uint64_t ift_mbuf_defrag_failed; 336 uint64_t ift_mbuf_defrag; 337 uint64_t ift_map_failed; 338 uint64_t ift_txd_encap_efbig; 339 uint64_t ift_pullups; 340 uint64_t ift_last_timer_tick; 341 342 struct mtx ift_mtx; 343 struct mtx ift_db_mtx; 344 345 /* constant values */ 346 if_ctx_t ift_ctx; 347 struct ifmp_ring *ift_br; 348 struct grouptask ift_task; 349 qidx_t ift_size; 350 uint16_t ift_id; 351 struct callout ift_timer; 352 353 if_txsd_vec_t ift_sds; 354 uint8_t ift_qstatus; 355 uint8_t ift_closed; 356 uint8_t ift_update_freq; 357 struct iflib_filter_info ift_filter_info; 358 bus_dma_tag_t ift_buf_tag; 359 bus_dma_tag_t ift_tso_buf_tag; 360 iflib_dma_info_t ift_ifdi; 361 #define MTX_NAME_LEN 32 362 char ift_mtx_name[MTX_NAME_LEN]; 363 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 364 #ifdef IFLIB_DIAGNOSTICS 365 uint64_t ift_cpu_exec_count[256]; 366 #endif 367 } __aligned(CACHE_LINE_SIZE); 368 369 struct iflib_fl { 370 qidx_t ifl_cidx; 371 qidx_t ifl_pidx; 372 qidx_t ifl_credits; 373 uint8_t ifl_gen; 374 uint8_t ifl_rxd_size; 375 #if MEMORY_LOGGING 376 uint64_t ifl_m_enqueued; 377 uint64_t ifl_m_dequeued; 378 uint64_t ifl_cl_enqueued; 379 uint64_t ifl_cl_dequeued; 380 #endif 381 /* implicit pad */ 382 bitstr_t *ifl_rx_bitmap; 383 qidx_t ifl_fragidx; 384 /* constant */ 385 qidx_t ifl_size; 386 uint16_t ifl_buf_size; 387 uint16_t ifl_cltype; 388 uma_zone_t ifl_zone; 389 iflib_rxsd_array_t ifl_sds; 390 iflib_rxq_t ifl_rxq; 391 uint8_t ifl_id; 392 bus_dma_tag_t ifl_buf_tag; 393 iflib_dma_info_t ifl_ifdi; 394 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 395 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 396 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 397 } __aligned(CACHE_LINE_SIZE); 398 399 static inline qidx_t 400 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 401 { 402 qidx_t used; 403 404 if (pidx > cidx) 405 used = pidx - cidx; 406 else if (pidx < cidx) 407 used = size - cidx + pidx; 408 else if (gen == 0 && pidx == cidx) 409 used = 0; 410 else if (gen == 1 && pidx == cidx) 411 used = size; 412 else 413 panic("bad state"); 414 415 return (used); 416 } 417 418 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 419 420 #define IDXDIFF(head, tail, wrap) \ 421 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 422 423 struct iflib_rxq { 424 if_ctx_t ifr_ctx; 425 iflib_fl_t ifr_fl; 426 uint64_t ifr_rx_irq; 427 struct pfil_head *pfil; 428 /* 429 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 430 * the command queue consumer index. Otherwise it's unused. 431 */ 432 qidx_t ifr_cq_cidx; 433 uint16_t ifr_id; 434 uint8_t ifr_nfl; 435 uint8_t ifr_ntxqirq; 436 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 437 uint8_t ifr_fl_offset; 438 struct lro_ctrl ifr_lc; 439 struct grouptask ifr_task; 440 struct callout ifr_watchdog; 441 struct iflib_filter_info ifr_filter_info; 442 iflib_dma_info_t ifr_ifdi; 443 444 /* dynamically allocate if any drivers need a value substantially larger than this */ 445 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 446 #ifdef IFLIB_DIAGNOSTICS 447 uint64_t ifr_cpu_exec_count[256]; 448 #endif 449 } __aligned(CACHE_LINE_SIZE); 450 451 typedef struct if_rxsd { 452 caddr_t *ifsd_cl; 453 iflib_fl_t ifsd_fl; 454 } *if_rxsd_t; 455 456 /* multiple of word size */ 457 #ifdef __LP64__ 458 #define PKT_INFO_SIZE 6 459 #define RXD_INFO_SIZE 5 460 #define PKT_TYPE uint64_t 461 #else 462 #define PKT_INFO_SIZE 11 463 #define RXD_INFO_SIZE 8 464 #define PKT_TYPE uint32_t 465 #endif 466 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 467 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 468 469 typedef struct if_pkt_info_pad { 470 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 471 } *if_pkt_info_pad_t; 472 typedef struct if_rxd_info_pad { 473 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 474 } *if_rxd_info_pad_t; 475 476 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 477 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 478 479 480 static inline void 481 pkt_info_zero(if_pkt_info_t pi) 482 { 483 if_pkt_info_pad_t pi_pad; 484 485 pi_pad = (if_pkt_info_pad_t)pi; 486 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 487 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 488 #ifndef __LP64__ 489 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 490 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 491 #endif 492 } 493 494 static device_method_t iflib_pseudo_methods[] = { 495 DEVMETHOD(device_attach, noop_attach), 496 DEVMETHOD(device_detach, iflib_pseudo_detach), 497 DEVMETHOD_END 498 }; 499 500 driver_t iflib_pseudodriver = { 501 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 502 }; 503 504 static inline void 505 rxd_info_zero(if_rxd_info_t ri) 506 { 507 if_rxd_info_pad_t ri_pad; 508 int i; 509 510 ri_pad = (if_rxd_info_pad_t)ri; 511 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 512 ri_pad->rxd_val[i] = 0; 513 ri_pad->rxd_val[i+1] = 0; 514 ri_pad->rxd_val[i+2] = 0; 515 ri_pad->rxd_val[i+3] = 0; 516 } 517 #ifdef __LP64__ 518 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 519 #endif 520 } 521 522 /* 523 * Only allow a single packet to take up most 1/nth of the tx ring 524 */ 525 #define MAX_SINGLE_PACKET_FRACTION 12 526 #define IF_BAD_DMA (bus_addr_t)-1 527 528 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 529 530 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 531 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 532 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 533 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 534 535 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 536 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 537 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 538 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 539 540 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 541 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 542 543 void 544 iflib_set_detach(if_ctx_t ctx) 545 { 546 STATE_LOCK(ctx); 547 ctx->ifc_flags |= IFC_IN_DETACH; 548 STATE_UNLOCK(ctx); 549 } 550 551 /* Our boot-time initialization hook */ 552 static int iflib_module_event_handler(module_t, int, void *); 553 554 static moduledata_t iflib_moduledata = { 555 "iflib", 556 iflib_module_event_handler, 557 NULL 558 }; 559 560 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 561 MODULE_VERSION(iflib, 1); 562 563 MODULE_DEPEND(iflib, pci, 1, 1, 1); 564 MODULE_DEPEND(iflib, ether, 1, 1, 1); 565 566 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 567 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 568 569 #ifndef IFLIB_DEBUG_COUNTERS 570 #ifdef INVARIANTS 571 #define IFLIB_DEBUG_COUNTERS 1 572 #else 573 #define IFLIB_DEBUG_COUNTERS 0 574 #endif /* !INVARIANTS */ 575 #endif 576 577 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 578 "iflib driver parameters"); 579 580 /* 581 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 582 */ 583 static int iflib_min_tx_latency = 0; 584 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 585 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 586 static int iflib_no_tx_batch = 0; 587 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 588 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 589 590 591 #if IFLIB_DEBUG_COUNTERS 592 593 static int iflib_tx_seen; 594 static int iflib_tx_sent; 595 static int iflib_tx_encap; 596 static int iflib_rx_allocs; 597 static int iflib_fl_refills; 598 static int iflib_fl_refills_large; 599 static int iflib_tx_frees; 600 601 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 602 &iflib_tx_seen, 0, "# TX mbufs seen"); 603 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 604 &iflib_tx_sent, 0, "# TX mbufs sent"); 605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 606 &iflib_tx_encap, 0, "# TX mbufs encapped"); 607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 608 &iflib_tx_frees, 0, "# TX frees"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 610 &iflib_rx_allocs, 0, "# RX allocations"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 612 &iflib_fl_refills, 0, "# refills"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 614 &iflib_fl_refills_large, 0, "# large refills"); 615 616 617 static int iflib_txq_drain_flushing; 618 static int iflib_txq_drain_oactive; 619 static int iflib_txq_drain_notready; 620 621 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 622 &iflib_txq_drain_flushing, 0, "# drain flushes"); 623 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 624 &iflib_txq_drain_oactive, 0, "# drain oactives"); 625 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 626 &iflib_txq_drain_notready, 0, "# drain notready"); 627 628 629 static int iflib_encap_load_mbuf_fail; 630 static int iflib_encap_pad_mbuf_fail; 631 static int iflib_encap_txq_avail_fail; 632 static int iflib_encap_txd_encap_fail; 633 634 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 635 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 637 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 638 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 639 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 640 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 641 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 642 643 static int iflib_task_fn_rxs; 644 static int iflib_rx_intr_enables; 645 static int iflib_fast_intrs; 646 static int iflib_rx_unavail; 647 static int iflib_rx_ctx_inactive; 648 static int iflib_rx_if_input; 649 static int iflib_rxd_flush; 650 651 static int iflib_verbose_debug; 652 653 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 654 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 655 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 656 &iflib_rx_intr_enables, 0, "# RX intr enables"); 657 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 658 &iflib_fast_intrs, 0, "# fast_intr calls"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 660 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 662 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 664 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 666 &iflib_rxd_flush, 0, "# times rxd_flush called"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 668 &iflib_verbose_debug, 0, "enable verbose debugging"); 669 670 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 671 static void 672 iflib_debug_reset(void) 673 { 674 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 675 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 676 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 677 iflib_txq_drain_notready = 678 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 679 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 680 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 681 iflib_rx_unavail = 682 iflib_rx_ctx_inactive = iflib_rx_if_input = 683 iflib_rxd_flush = 0; 684 } 685 686 #else 687 #define DBG_COUNTER_INC(name) 688 static void iflib_debug_reset(void) {} 689 #endif 690 691 #define IFLIB_DEBUG 0 692 693 static void iflib_tx_structures_free(if_ctx_t ctx); 694 static void iflib_rx_structures_free(if_ctx_t ctx); 695 static int iflib_queues_alloc(if_ctx_t ctx); 696 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 697 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 698 static int iflib_qset_structures_setup(if_ctx_t ctx); 699 static int iflib_msix_init(if_ctx_t ctx); 700 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 701 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 702 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 703 #ifdef ALTQ 704 static void iflib_altq_if_start(if_t ifp); 705 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 706 #endif 707 static int iflib_register(if_ctx_t); 708 static void iflib_deregister(if_ctx_t); 709 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 710 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 711 static void iflib_init_locked(if_ctx_t ctx); 712 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 713 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 714 static void iflib_ifmp_purge(iflib_txq_t txq); 715 static void _iflib_pre_assert(if_softc_ctx_t scctx); 716 static void iflib_if_init_locked(if_ctx_t ctx); 717 static void iflib_free_intr_mem(if_ctx_t ctx); 718 #ifndef __NO_STRICT_ALIGNMENT 719 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 720 #endif 721 722 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 723 SLIST_HEAD_INITIALIZER(cpu_offsets); 724 struct cpu_offset { 725 SLIST_ENTRY(cpu_offset) entries; 726 cpuset_t set; 727 unsigned int refcount; 728 uint16_t offset; 729 }; 730 static struct mtx cpu_offset_mtx; 731 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 732 MTX_DEF); 733 734 DEBUGNET_DEFINE(iflib); 735 736 #ifdef DEV_NETMAP 737 #include <sys/selinfo.h> 738 #include <net/netmap.h> 739 #include <dev/netmap/netmap_kern.h> 740 741 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 742 743 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 744 745 /* 746 * device-specific sysctl variables: 747 * 748 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 749 * During regular operations the CRC is stripped, but on some 750 * hardware reception of frames not multiple of 64 is slower, 751 * so using crcstrip=0 helps in benchmarks. 752 * 753 * iflib_rx_miss, iflib_rx_miss_bufs: 754 * count packets that might be missed due to lost interrupts. 755 */ 756 SYSCTL_DECL(_dev_netmap); 757 /* 758 * The xl driver by default strips CRCs and we do not override it. 759 */ 760 761 int iflib_crcstrip = 1; 762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 763 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 764 765 int iflib_rx_miss, iflib_rx_miss_bufs; 766 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 767 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 768 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 769 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 770 771 /* 772 * Register/unregister. We are already under netmap lock. 773 * Only called on the first register or the last unregister. 774 */ 775 static int 776 iflib_netmap_register(struct netmap_adapter *na, int onoff) 777 { 778 if_t ifp = na->ifp; 779 if_ctx_t ctx = ifp->if_softc; 780 int status; 781 782 CTX_LOCK(ctx); 783 IFDI_INTR_DISABLE(ctx); 784 785 /* Tell the stack that the interface is no longer active */ 786 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 787 788 if (!CTX_IS_VF(ctx)) 789 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 790 791 iflib_stop(ctx); 792 793 /* 794 * Enable (or disable) netmap flags, and intercept (or restore) 795 * ifp->if_transmit. This is done once the device has been stopped 796 * to prevent race conditions. 797 */ 798 if (onoff) { 799 nm_set_native_flags(na); 800 } else { 801 nm_clear_native_flags(na); 802 } 803 804 iflib_init_locked(ctx); 805 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 806 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 807 if (status) 808 nm_clear_native_flags(na); 809 CTX_UNLOCK(ctx); 810 return (status); 811 } 812 813 static int 814 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 815 { 816 struct netmap_adapter *na = kring->na; 817 u_int const lim = kring->nkr_num_slots - 1; 818 u_int head = kring->rhead; 819 struct netmap_ring *ring = kring->ring; 820 bus_dmamap_t *map; 821 struct if_rxd_update iru; 822 if_ctx_t ctx = rxq->ifr_ctx; 823 iflib_fl_t fl = &rxq->ifr_fl[0]; 824 uint32_t refill_pidx, nic_i; 825 #if IFLIB_DEBUG_COUNTERS 826 int rf_count = 0; 827 #endif 828 829 if (nm_i == head && __predict_true(!init)) 830 return 0; 831 iru_init(&iru, rxq, 0 /* flid */); 832 map = fl->ifl_sds.ifsd_map; 833 refill_pidx = netmap_idx_k2n(kring, nm_i); 834 /* 835 * IMPORTANT: we must leave one free slot in the ring, 836 * so move head back by one unit 837 */ 838 head = nm_prev(head, lim); 839 nic_i = UINT_MAX; 840 DBG_COUNTER_INC(fl_refills); 841 while (nm_i != head) { 842 #if IFLIB_DEBUG_COUNTERS 843 if (++rf_count == 9) 844 DBG_COUNTER_INC(fl_refills_large); 845 #endif 846 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 847 struct netmap_slot *slot = &ring->slot[nm_i]; 848 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 849 uint32_t nic_i_dma = refill_pidx; 850 nic_i = netmap_idx_k2n(kring, nm_i); 851 852 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 853 854 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 855 return netmap_ring_reinit(kring); 856 857 fl->ifl_vm_addrs[tmp_pidx] = addr; 858 if (__predict_false(init)) { 859 netmap_load_map(na, fl->ifl_buf_tag, 860 map[nic_i], addr); 861 } else if (slot->flags & NS_BUF_CHANGED) { 862 /* buffer has changed, reload map */ 863 netmap_reload_map(na, fl->ifl_buf_tag, 864 map[nic_i], addr); 865 } 866 slot->flags &= ~NS_BUF_CHANGED; 867 868 nm_i = nm_next(nm_i, lim); 869 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 870 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 871 continue; 872 873 iru.iru_pidx = refill_pidx; 874 iru.iru_count = tmp_pidx+1; 875 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 876 refill_pidx = nic_i; 877 for (int n = 0; n < iru.iru_count; n++) { 878 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma], 879 BUS_DMASYNC_PREREAD); 880 /* XXX - change this to not use the netmap func*/ 881 nic_i_dma = nm_next(nic_i_dma, lim); 882 } 883 } 884 } 885 kring->nr_hwcur = head; 886 887 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 888 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 889 if (__predict_true(nic_i != UINT_MAX)) { 890 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 891 DBG_COUNTER_INC(rxd_flush); 892 } 893 return (0); 894 } 895 896 /* 897 * Reconcile kernel and user view of the transmit ring. 898 * 899 * All information is in the kring. 900 * Userspace wants to send packets up to the one before kring->rhead, 901 * kernel knows kring->nr_hwcur is the first unsent packet. 902 * 903 * Here we push packets out (as many as possible), and possibly 904 * reclaim buffers from previously completed transmission. 905 * 906 * The caller (netmap) guarantees that there is only one instance 907 * running at any time. Any interference with other driver 908 * methods should be handled by the individual drivers. 909 */ 910 static int 911 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 912 { 913 struct netmap_adapter *na = kring->na; 914 if_t ifp = na->ifp; 915 struct netmap_ring *ring = kring->ring; 916 u_int nm_i; /* index into the netmap kring */ 917 u_int nic_i; /* index into the NIC ring */ 918 u_int n; 919 u_int const lim = kring->nkr_num_slots - 1; 920 u_int const head = kring->rhead; 921 struct if_pkt_info pi; 922 923 /* 924 * interrupts on every tx packet are expensive so request 925 * them every half ring, or where NS_REPORT is set 926 */ 927 u_int report_frequency = kring->nkr_num_slots >> 1; 928 /* device-specific */ 929 if_ctx_t ctx = ifp->if_softc; 930 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 931 932 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 933 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 934 935 /* 936 * First part: process new packets to send. 937 * nm_i is the current index in the netmap kring, 938 * nic_i is the corresponding index in the NIC ring. 939 * 940 * If we have packets to send (nm_i != head) 941 * iterate over the netmap ring, fetch length and update 942 * the corresponding slot in the NIC ring. Some drivers also 943 * need to update the buffer's physical address in the NIC slot 944 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 945 * 946 * The netmap_reload_map() calls is especially expensive, 947 * even when (as in this case) the tag is 0, so do only 948 * when the buffer has actually changed. 949 * 950 * If possible do not set the report/intr bit on all slots, 951 * but only a few times per ring or when NS_REPORT is set. 952 * 953 * Finally, on 10G and faster drivers, it might be useful 954 * to prefetch the next slot and txr entry. 955 */ 956 957 nm_i = kring->nr_hwcur; 958 if (nm_i != head) { /* we have new packets to send */ 959 pkt_info_zero(&pi); 960 pi.ipi_segs = txq->ift_segs; 961 pi.ipi_qsidx = kring->ring_id; 962 nic_i = netmap_idx_k2n(kring, nm_i); 963 964 __builtin_prefetch(&ring->slot[nm_i]); 965 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 966 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 967 968 for (n = 0; nm_i != head; n++) { 969 struct netmap_slot *slot = &ring->slot[nm_i]; 970 u_int len = slot->len; 971 uint64_t paddr; 972 void *addr = PNMB(na, slot, &paddr); 973 int flags = (slot->flags & NS_REPORT || 974 nic_i == 0 || nic_i == report_frequency) ? 975 IPI_TX_INTR : 0; 976 977 /* device-specific */ 978 pi.ipi_len = len; 979 pi.ipi_segs[0].ds_addr = paddr; 980 pi.ipi_segs[0].ds_len = len; 981 pi.ipi_nsegs = 1; 982 pi.ipi_ndescs = 0; 983 pi.ipi_pidx = nic_i; 984 pi.ipi_flags = flags; 985 986 /* Fill the slot in the NIC ring. */ 987 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 988 DBG_COUNTER_INC(tx_encap); 989 990 /* prefetch for next round */ 991 __builtin_prefetch(&ring->slot[nm_i + 1]); 992 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 993 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 994 995 NM_CHECK_ADDR_LEN(na, addr, len); 996 997 if (slot->flags & NS_BUF_CHANGED) { 998 /* buffer has changed, reload map */ 999 netmap_reload_map(na, txq->ift_buf_tag, 1000 txq->ift_sds.ifsd_map[nic_i], addr); 1001 } 1002 /* make sure changes to the buffer are synced */ 1003 bus_dmamap_sync(txq->ift_buf_tag, 1004 txq->ift_sds.ifsd_map[nic_i], 1005 BUS_DMASYNC_PREWRITE); 1006 1007 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1008 nm_i = nm_next(nm_i, lim); 1009 nic_i = nm_next(nic_i, lim); 1010 } 1011 kring->nr_hwcur = nm_i; 1012 1013 /* synchronize the NIC ring */ 1014 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1015 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1016 1017 /* (re)start the tx unit up to slot nic_i (excluded) */ 1018 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1019 } 1020 1021 /* 1022 * Second part: reclaim buffers for completed transmissions. 1023 * 1024 * If there are unclaimed buffers, attempt to reclaim them. 1025 * If none are reclaimed, and TX IRQs are not in use, do an initial 1026 * minimal delay, then trigger the tx handler which will spin in the 1027 * group task queue. 1028 */ 1029 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1030 if (iflib_tx_credits_update(ctx, txq)) { 1031 /* some tx completed, increment avail */ 1032 nic_i = txq->ift_cidx_processed; 1033 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1034 } 1035 } 1036 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1037 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1038 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1039 iflib_timer, txq, txq->ift_timer.c_cpu); 1040 } 1041 return (0); 1042 } 1043 1044 /* 1045 * Reconcile kernel and user view of the receive ring. 1046 * Same as for the txsync, this routine must be efficient. 1047 * The caller guarantees a single invocations, but races against 1048 * the rest of the driver should be handled here. 1049 * 1050 * On call, kring->rhead is the first packet that userspace wants 1051 * to keep, and kring->rcur is the wakeup point. 1052 * The kernel has previously reported packets up to kring->rtail. 1053 * 1054 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1055 * of whether or not we received an interrupt. 1056 */ 1057 static int 1058 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1059 { 1060 struct netmap_adapter *na = kring->na; 1061 struct netmap_ring *ring = kring->ring; 1062 if_t ifp = na->ifp; 1063 iflib_fl_t fl; 1064 uint32_t nm_i; /* index into the netmap ring */ 1065 uint32_t nic_i; /* index into the NIC ring */ 1066 u_int i, n; 1067 u_int const lim = kring->nkr_num_slots - 1; 1068 u_int const head = kring->rhead; 1069 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1070 struct if_rxd_info ri; 1071 1072 if_ctx_t ctx = ifp->if_softc; 1073 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1074 if (head > lim) 1075 return netmap_ring_reinit(kring); 1076 1077 /* 1078 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far. 1079 */ 1080 1081 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1082 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1083 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1084 } 1085 1086 /* 1087 * First part: import newly received packets. 1088 * 1089 * nm_i is the index of the next free slot in the netmap ring, 1090 * nic_i is the index of the next received packet in the NIC ring, 1091 * and they may differ in case if_init() has been called while 1092 * in netmap mode. For the receive ring we have 1093 * 1094 * nic_i = rxr->next_check; 1095 * nm_i = kring->nr_hwtail (previous) 1096 * and 1097 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1098 * 1099 * rxr->next_check is set to 0 on a ring reinit 1100 */ 1101 if (netmap_no_pendintr || force_update) { 1102 int crclen = iflib_crcstrip ? 0 : 4; 1103 int error, avail; 1104 1105 for (i = 0; i < rxq->ifr_nfl; i++) { 1106 fl = &rxq->ifr_fl[i]; 1107 nic_i = fl->ifl_cidx; 1108 nm_i = netmap_idx_n2k(kring, nic_i); 1109 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1110 rxq->ifr_id, nic_i, USHRT_MAX); 1111 for (n = 0; avail > 0; n++, avail--) { 1112 rxd_info_zero(&ri); 1113 ri.iri_frags = rxq->ifr_frags; 1114 ri.iri_qsidx = kring->ring_id; 1115 ri.iri_ifp = ctx->ifc_ifp; 1116 ri.iri_cidx = nic_i; 1117 1118 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1119 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1120 ring->slot[nm_i].flags = 0; 1121 bus_dmamap_sync(fl->ifl_buf_tag, 1122 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1123 nm_i = nm_next(nm_i, lim); 1124 nic_i = nm_next(nic_i, lim); 1125 } 1126 if (n) { /* update the state variables */ 1127 if (netmap_no_pendintr && !force_update) { 1128 /* diagnostics */ 1129 iflib_rx_miss ++; 1130 iflib_rx_miss_bufs += n; 1131 } 1132 fl->ifl_cidx = nic_i; 1133 kring->nr_hwtail = nm_i; 1134 } 1135 kring->nr_kflags &= ~NKR_PENDINTR; 1136 } 1137 } 1138 /* 1139 * Second part: skip past packets that userspace has released. 1140 * (kring->nr_hwcur to head excluded), 1141 * and make the buffers available for reception. 1142 * As usual nm_i is the index in the netmap ring, 1143 * nic_i is the index in the NIC ring, and 1144 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1145 */ 1146 /* XXX not sure how this will work with multiple free lists */ 1147 nm_i = kring->nr_hwcur; 1148 1149 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1150 } 1151 1152 static void 1153 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1154 { 1155 if_ctx_t ctx = na->ifp->if_softc; 1156 1157 CTX_LOCK(ctx); 1158 if (onoff) { 1159 IFDI_INTR_ENABLE(ctx); 1160 } else { 1161 IFDI_INTR_DISABLE(ctx); 1162 } 1163 CTX_UNLOCK(ctx); 1164 } 1165 1166 1167 static int 1168 iflib_netmap_attach(if_ctx_t ctx) 1169 { 1170 struct netmap_adapter na; 1171 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1172 1173 bzero(&na, sizeof(na)); 1174 1175 na.ifp = ctx->ifc_ifp; 1176 na.na_flags = NAF_BDG_MAYSLEEP; 1177 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1178 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1179 1180 na.num_tx_desc = scctx->isc_ntxd[0]; 1181 na.num_rx_desc = scctx->isc_nrxd[0]; 1182 na.nm_txsync = iflib_netmap_txsync; 1183 na.nm_rxsync = iflib_netmap_rxsync; 1184 na.nm_register = iflib_netmap_register; 1185 na.nm_intr = iflib_netmap_intr; 1186 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1187 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1188 return (netmap_attach(&na)); 1189 } 1190 1191 static void 1192 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1193 { 1194 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1195 struct netmap_slot *slot; 1196 1197 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1198 if (slot == NULL) 1199 return; 1200 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1201 1202 /* 1203 * In netmap mode, set the map for the packet buffer. 1204 * NOTE: Some drivers (not this one) also need to set 1205 * the physical buffer address in the NIC ring. 1206 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1207 * netmap slot index, si 1208 */ 1209 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1210 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1211 NMB(na, slot + si)); 1212 } 1213 } 1214 1215 static void 1216 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1217 { 1218 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1219 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1220 struct netmap_slot *slot; 1221 uint32_t nm_i; 1222 1223 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1224 if (slot == NULL) 1225 return; 1226 nm_i = netmap_idx_n2k(kring, 0); 1227 netmap_fl_refill(rxq, kring, nm_i, true); 1228 } 1229 1230 static void 1231 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on) 1232 { 1233 struct netmap_kring *kring; 1234 uint16_t txqid; 1235 1236 txqid = txq->ift_id; 1237 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1238 1239 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1240 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1241 BUS_DMASYNC_POSTREAD); 1242 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1243 netmap_tx_irq(ctx->ifc_ifp, txqid); 1244 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1245 if (hz < 2000) 1246 *reset_on = 1; 1247 else 1248 *reset_on = hz / 1000; 1249 } 1250 } 1251 } 1252 1253 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1254 1255 #else 1256 #define iflib_netmap_txq_init(ctx, txq) 1257 #define iflib_netmap_rxq_init(ctx, rxq) 1258 #define iflib_netmap_detach(ifp) 1259 1260 #define iflib_netmap_attach(ctx) (0) 1261 #define netmap_rx_irq(ifp, qid, budget) (0) 1262 #define netmap_tx_irq(ifp, qid) do {} while (0) 1263 #define iflib_netmap_timer_adjust(ctx, txq, reset_on) 1264 #endif 1265 1266 #if defined(__i386__) || defined(__amd64__) 1267 static __inline void 1268 prefetch(void *x) 1269 { 1270 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1271 } 1272 static __inline void 1273 prefetch2cachelines(void *x) 1274 { 1275 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1276 #if (CACHE_LINE_SIZE < 128) 1277 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1278 #endif 1279 } 1280 #else 1281 #define prefetch(x) 1282 #define prefetch2cachelines(x) 1283 #endif 1284 1285 static void 1286 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1287 { 1288 iflib_fl_t fl; 1289 1290 fl = &rxq->ifr_fl[flid]; 1291 iru->iru_paddrs = fl->ifl_bus_addrs; 1292 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1293 iru->iru_idxs = fl->ifl_rxd_idxs; 1294 iru->iru_qsidx = rxq->ifr_id; 1295 iru->iru_buf_size = fl->ifl_buf_size; 1296 iru->iru_flidx = fl->ifl_id; 1297 } 1298 1299 static void 1300 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1301 { 1302 if (err) 1303 return; 1304 *(bus_addr_t *) arg = segs[0].ds_addr; 1305 } 1306 1307 int 1308 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1309 { 1310 int err; 1311 device_t dev = ctx->ifc_dev; 1312 1313 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1314 align, 0, /* alignment, bounds */ 1315 BUS_SPACE_MAXADDR, /* lowaddr */ 1316 BUS_SPACE_MAXADDR, /* highaddr */ 1317 NULL, NULL, /* filter, filterarg */ 1318 size, /* maxsize */ 1319 1, /* nsegments */ 1320 size, /* maxsegsize */ 1321 BUS_DMA_ALLOCNOW, /* flags */ 1322 NULL, /* lockfunc */ 1323 NULL, /* lockarg */ 1324 &dma->idi_tag); 1325 if (err) { 1326 device_printf(dev, 1327 "%s: bus_dma_tag_create failed: %d\n", 1328 __func__, err); 1329 goto fail_0; 1330 } 1331 1332 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1333 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1334 if (err) { 1335 device_printf(dev, 1336 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1337 __func__, (uintmax_t)size, err); 1338 goto fail_1; 1339 } 1340 1341 dma->idi_paddr = IF_BAD_DMA; 1342 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1343 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1344 if (err || dma->idi_paddr == IF_BAD_DMA) { 1345 device_printf(dev, 1346 "%s: bus_dmamap_load failed: %d\n", 1347 __func__, err); 1348 goto fail_2; 1349 } 1350 1351 dma->idi_size = size; 1352 return (0); 1353 1354 fail_2: 1355 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1356 fail_1: 1357 bus_dma_tag_destroy(dma->idi_tag); 1358 fail_0: 1359 dma->idi_tag = NULL; 1360 1361 return (err); 1362 } 1363 1364 int 1365 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1366 { 1367 if_shared_ctx_t sctx = ctx->ifc_sctx; 1368 1369 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1370 1371 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1372 } 1373 1374 int 1375 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1376 { 1377 int i, err; 1378 iflib_dma_info_t *dmaiter; 1379 1380 dmaiter = dmalist; 1381 for (i = 0; i < count; i++, dmaiter++) { 1382 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1383 break; 1384 } 1385 if (err) 1386 iflib_dma_free_multi(dmalist, i); 1387 return (err); 1388 } 1389 1390 void 1391 iflib_dma_free(iflib_dma_info_t dma) 1392 { 1393 if (dma->idi_tag == NULL) 1394 return; 1395 if (dma->idi_paddr != IF_BAD_DMA) { 1396 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1397 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1398 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1399 dma->idi_paddr = IF_BAD_DMA; 1400 } 1401 if (dma->idi_vaddr != NULL) { 1402 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1403 dma->idi_vaddr = NULL; 1404 } 1405 bus_dma_tag_destroy(dma->idi_tag); 1406 dma->idi_tag = NULL; 1407 } 1408 1409 void 1410 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1411 { 1412 int i; 1413 iflib_dma_info_t *dmaiter = dmalist; 1414 1415 for (i = 0; i < count; i++, dmaiter++) 1416 iflib_dma_free(*dmaiter); 1417 } 1418 1419 static int 1420 iflib_fast_intr(void *arg) 1421 { 1422 iflib_filter_info_t info = arg; 1423 struct grouptask *gtask = info->ifi_task; 1424 int result; 1425 1426 DBG_COUNTER_INC(fast_intrs); 1427 if (info->ifi_filter != NULL) { 1428 result = info->ifi_filter(info->ifi_filter_arg); 1429 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1430 return (result); 1431 } 1432 1433 GROUPTASK_ENQUEUE(gtask); 1434 return (FILTER_HANDLED); 1435 } 1436 1437 static int 1438 iflib_fast_intr_rxtx(void *arg) 1439 { 1440 iflib_filter_info_t info = arg; 1441 struct grouptask *gtask = info->ifi_task; 1442 if_ctx_t ctx; 1443 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1444 iflib_txq_t txq; 1445 void *sc; 1446 int i, cidx, result; 1447 qidx_t txqid; 1448 bool intr_enable, intr_legacy; 1449 1450 DBG_COUNTER_INC(fast_intrs); 1451 if (info->ifi_filter != NULL) { 1452 result = info->ifi_filter(info->ifi_filter_arg); 1453 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1454 return (result); 1455 } 1456 1457 ctx = rxq->ifr_ctx; 1458 sc = ctx->ifc_softc; 1459 intr_enable = false; 1460 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1461 MPASS(rxq->ifr_ntxqirq); 1462 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1463 txqid = rxq->ifr_txqid[i]; 1464 txq = &ctx->ifc_txqs[txqid]; 1465 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1466 BUS_DMASYNC_POSTREAD); 1467 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1468 if (intr_legacy) 1469 intr_enable = true; 1470 else 1471 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1472 continue; 1473 } 1474 GROUPTASK_ENQUEUE(&txq->ift_task); 1475 } 1476 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1477 cidx = rxq->ifr_cq_cidx; 1478 else 1479 cidx = rxq->ifr_fl[0].ifl_cidx; 1480 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1481 GROUPTASK_ENQUEUE(gtask); 1482 else { 1483 if (intr_legacy) 1484 intr_enable = true; 1485 else 1486 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1487 DBG_COUNTER_INC(rx_intr_enables); 1488 } 1489 if (intr_enable) 1490 IFDI_INTR_ENABLE(ctx); 1491 return (FILTER_HANDLED); 1492 } 1493 1494 1495 static int 1496 iflib_fast_intr_ctx(void *arg) 1497 { 1498 iflib_filter_info_t info = arg; 1499 struct grouptask *gtask = info->ifi_task; 1500 int result; 1501 1502 DBG_COUNTER_INC(fast_intrs); 1503 if (info->ifi_filter != NULL) { 1504 result = info->ifi_filter(info->ifi_filter_arg); 1505 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1506 return (result); 1507 } 1508 1509 GROUPTASK_ENQUEUE(gtask); 1510 return (FILTER_HANDLED); 1511 } 1512 1513 static int 1514 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1515 driver_filter_t filter, driver_intr_t handler, void *arg, 1516 const char *name) 1517 { 1518 struct resource *res; 1519 void *tag = NULL; 1520 device_t dev = ctx->ifc_dev; 1521 int flags, i, rc; 1522 1523 flags = RF_ACTIVE; 1524 if (ctx->ifc_flags & IFC_LEGACY) 1525 flags |= RF_SHAREABLE; 1526 MPASS(rid < 512); 1527 i = rid; 1528 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1529 if (res == NULL) { 1530 device_printf(dev, 1531 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1532 return (ENOMEM); 1533 } 1534 irq->ii_res = res; 1535 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1536 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1537 filter, handler, arg, &tag); 1538 if (rc != 0) { 1539 device_printf(dev, 1540 "failed to setup interrupt for rid %d, name %s: %d\n", 1541 rid, name ? name : "unknown", rc); 1542 return (rc); 1543 } else if (name) 1544 bus_describe_intr(dev, res, tag, "%s", name); 1545 1546 irq->ii_tag = tag; 1547 return (0); 1548 } 1549 1550 /********************************************************************* 1551 * 1552 * Allocate DMA resources for TX buffers as well as memory for the TX 1553 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1554 * iflib_sw_tx_desc_array structure, storing all the information that 1555 * is needed to transmit a packet on the wire. This is called only 1556 * once at attach, setup is done every reset. 1557 * 1558 **********************************************************************/ 1559 static int 1560 iflib_txsd_alloc(iflib_txq_t txq) 1561 { 1562 if_ctx_t ctx = txq->ift_ctx; 1563 if_shared_ctx_t sctx = ctx->ifc_sctx; 1564 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1565 device_t dev = ctx->ifc_dev; 1566 bus_size_t tsomaxsize; 1567 int err, nsegments, ntsosegments; 1568 bool tso; 1569 1570 nsegments = scctx->isc_tx_nsegments; 1571 ntsosegments = scctx->isc_tx_tso_segments_max; 1572 tsomaxsize = scctx->isc_tx_tso_size_max; 1573 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1574 tsomaxsize += sizeof(struct ether_vlan_header); 1575 MPASS(scctx->isc_ntxd[0] > 0); 1576 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1577 MPASS(nsegments > 0); 1578 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1579 MPASS(ntsosegments > 0); 1580 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1581 } 1582 1583 /* 1584 * Set up DMA tags for TX buffers. 1585 */ 1586 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1587 1, 0, /* alignment, bounds */ 1588 BUS_SPACE_MAXADDR, /* lowaddr */ 1589 BUS_SPACE_MAXADDR, /* highaddr */ 1590 NULL, NULL, /* filter, filterarg */ 1591 sctx->isc_tx_maxsize, /* maxsize */ 1592 nsegments, /* nsegments */ 1593 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1594 0, /* flags */ 1595 NULL, /* lockfunc */ 1596 NULL, /* lockfuncarg */ 1597 &txq->ift_buf_tag))) { 1598 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1599 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1600 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1601 goto fail; 1602 } 1603 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1604 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1605 1, 0, /* alignment, bounds */ 1606 BUS_SPACE_MAXADDR, /* lowaddr */ 1607 BUS_SPACE_MAXADDR, /* highaddr */ 1608 NULL, NULL, /* filter, filterarg */ 1609 tsomaxsize, /* maxsize */ 1610 ntsosegments, /* nsegments */ 1611 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1612 0, /* flags */ 1613 NULL, /* lockfunc */ 1614 NULL, /* lockfuncarg */ 1615 &txq->ift_tso_buf_tag))) { 1616 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1617 err); 1618 goto fail; 1619 } 1620 1621 /* Allocate memory for the TX mbuf map. */ 1622 if (!(txq->ift_sds.ifsd_m = 1623 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1624 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1625 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1626 err = ENOMEM; 1627 goto fail; 1628 } 1629 1630 /* 1631 * Create the DMA maps for TX buffers. 1632 */ 1633 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1634 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1635 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1636 device_printf(dev, 1637 "Unable to allocate TX buffer DMA map memory\n"); 1638 err = ENOMEM; 1639 goto fail; 1640 } 1641 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1642 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1643 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1644 device_printf(dev, 1645 "Unable to allocate TSO TX buffer map memory\n"); 1646 err = ENOMEM; 1647 goto fail; 1648 } 1649 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1650 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1651 &txq->ift_sds.ifsd_map[i]); 1652 if (err != 0) { 1653 device_printf(dev, "Unable to create TX DMA map\n"); 1654 goto fail; 1655 } 1656 if (!tso) 1657 continue; 1658 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1659 &txq->ift_sds.ifsd_tso_map[i]); 1660 if (err != 0) { 1661 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1662 goto fail; 1663 } 1664 } 1665 return (0); 1666 fail: 1667 /* We free all, it handles case where we are in the middle */ 1668 iflib_tx_structures_free(ctx); 1669 return (err); 1670 } 1671 1672 static void 1673 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1674 { 1675 bus_dmamap_t map; 1676 1677 if (txq->ift_sds.ifsd_map != NULL) { 1678 map = txq->ift_sds.ifsd_map[i]; 1679 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1680 bus_dmamap_unload(txq->ift_buf_tag, map); 1681 bus_dmamap_destroy(txq->ift_buf_tag, map); 1682 txq->ift_sds.ifsd_map[i] = NULL; 1683 } 1684 1685 if (txq->ift_sds.ifsd_tso_map != NULL) { 1686 map = txq->ift_sds.ifsd_tso_map[i]; 1687 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1688 BUS_DMASYNC_POSTWRITE); 1689 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1690 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1691 txq->ift_sds.ifsd_tso_map[i] = NULL; 1692 } 1693 } 1694 1695 static void 1696 iflib_txq_destroy(iflib_txq_t txq) 1697 { 1698 if_ctx_t ctx = txq->ift_ctx; 1699 1700 for (int i = 0; i < txq->ift_size; i++) 1701 iflib_txsd_destroy(ctx, txq, i); 1702 1703 if (txq->ift_br != NULL) { 1704 ifmp_ring_free(txq->ift_br); 1705 txq->ift_br = NULL; 1706 } 1707 1708 mtx_destroy(&txq->ift_mtx); 1709 1710 if (txq->ift_sds.ifsd_map != NULL) { 1711 free(txq->ift_sds.ifsd_map, M_IFLIB); 1712 txq->ift_sds.ifsd_map = NULL; 1713 } 1714 if (txq->ift_sds.ifsd_tso_map != NULL) { 1715 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1716 txq->ift_sds.ifsd_tso_map = NULL; 1717 } 1718 if (txq->ift_sds.ifsd_m != NULL) { 1719 free(txq->ift_sds.ifsd_m, M_IFLIB); 1720 txq->ift_sds.ifsd_m = NULL; 1721 } 1722 if (txq->ift_buf_tag != NULL) { 1723 bus_dma_tag_destroy(txq->ift_buf_tag); 1724 txq->ift_buf_tag = NULL; 1725 } 1726 if (txq->ift_tso_buf_tag != NULL) { 1727 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1728 txq->ift_tso_buf_tag = NULL; 1729 } 1730 if (txq->ift_ifdi != NULL) { 1731 free(txq->ift_ifdi, M_IFLIB); 1732 } 1733 } 1734 1735 static void 1736 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1737 { 1738 struct mbuf **mp; 1739 1740 mp = &txq->ift_sds.ifsd_m[i]; 1741 if (*mp == NULL) 1742 return; 1743 1744 if (txq->ift_sds.ifsd_map != NULL) { 1745 bus_dmamap_sync(txq->ift_buf_tag, 1746 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1747 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1748 } 1749 if (txq->ift_sds.ifsd_tso_map != NULL) { 1750 bus_dmamap_sync(txq->ift_tso_buf_tag, 1751 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1752 bus_dmamap_unload(txq->ift_tso_buf_tag, 1753 txq->ift_sds.ifsd_tso_map[i]); 1754 } 1755 m_free(*mp); 1756 DBG_COUNTER_INC(tx_frees); 1757 *mp = NULL; 1758 } 1759 1760 static int 1761 iflib_txq_setup(iflib_txq_t txq) 1762 { 1763 if_ctx_t ctx = txq->ift_ctx; 1764 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1765 if_shared_ctx_t sctx = ctx->ifc_sctx; 1766 iflib_dma_info_t di; 1767 int i; 1768 1769 /* Set number of descriptors available */ 1770 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1771 /* XXX make configurable */ 1772 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1773 1774 /* Reset indices */ 1775 txq->ift_cidx_processed = 0; 1776 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1777 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1778 1779 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1780 bzero((void *)di->idi_vaddr, di->idi_size); 1781 1782 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1783 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1784 bus_dmamap_sync(di->idi_tag, di->idi_map, 1785 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1786 return (0); 1787 } 1788 1789 /********************************************************************* 1790 * 1791 * Allocate DMA resources for RX buffers as well as memory for the RX 1792 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1793 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1794 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1795 * Since we use use one entry in iflib_sw_rx_desc_array per received 1796 * packet, the maximum number of entries we'll need is equal to the 1797 * number of hardware receive descriptors that we've allocated. 1798 * 1799 **********************************************************************/ 1800 static int 1801 iflib_rxsd_alloc(iflib_rxq_t rxq) 1802 { 1803 if_ctx_t ctx = rxq->ifr_ctx; 1804 if_shared_ctx_t sctx = ctx->ifc_sctx; 1805 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1806 device_t dev = ctx->ifc_dev; 1807 iflib_fl_t fl; 1808 int err; 1809 1810 MPASS(scctx->isc_nrxd[0] > 0); 1811 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1812 1813 fl = rxq->ifr_fl; 1814 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1815 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1816 /* Set up DMA tag for RX buffers. */ 1817 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1818 1, 0, /* alignment, bounds */ 1819 BUS_SPACE_MAXADDR, /* lowaddr */ 1820 BUS_SPACE_MAXADDR, /* highaddr */ 1821 NULL, NULL, /* filter, filterarg */ 1822 sctx->isc_rx_maxsize, /* maxsize */ 1823 sctx->isc_rx_nsegments, /* nsegments */ 1824 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1825 0, /* flags */ 1826 NULL, /* lockfunc */ 1827 NULL, /* lockarg */ 1828 &fl->ifl_buf_tag); 1829 if (err) { 1830 device_printf(dev, 1831 "Unable to allocate RX DMA tag: %d\n", err); 1832 goto fail; 1833 } 1834 1835 /* Allocate memory for the RX mbuf map. */ 1836 if (!(fl->ifl_sds.ifsd_m = 1837 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1838 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1839 device_printf(dev, 1840 "Unable to allocate RX mbuf map memory\n"); 1841 err = ENOMEM; 1842 goto fail; 1843 } 1844 1845 /* Allocate memory for the direct RX cluster pointer map. */ 1846 if (!(fl->ifl_sds.ifsd_cl = 1847 (caddr_t *) malloc(sizeof(caddr_t) * 1848 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1849 device_printf(dev, 1850 "Unable to allocate RX cluster map memory\n"); 1851 err = ENOMEM; 1852 goto fail; 1853 } 1854 1855 /* Allocate memory for the RX cluster bus address map. */ 1856 if (!(fl->ifl_sds.ifsd_ba = 1857 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1858 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1859 device_printf(dev, 1860 "Unable to allocate RX bus address map memory\n"); 1861 err = ENOMEM; 1862 goto fail; 1863 } 1864 1865 /* 1866 * Create the DMA maps for RX buffers. 1867 */ 1868 if (!(fl->ifl_sds.ifsd_map = 1869 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1870 device_printf(dev, 1871 "Unable to allocate RX buffer DMA map memory\n"); 1872 err = ENOMEM; 1873 goto fail; 1874 } 1875 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1876 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1877 &fl->ifl_sds.ifsd_map[i]); 1878 if (err != 0) { 1879 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1880 goto fail; 1881 } 1882 } 1883 } 1884 return (0); 1885 1886 fail: 1887 iflib_rx_structures_free(ctx); 1888 return (err); 1889 } 1890 1891 1892 /* 1893 * Internal service routines 1894 */ 1895 1896 struct rxq_refill_cb_arg { 1897 int error; 1898 bus_dma_segment_t seg; 1899 int nseg; 1900 }; 1901 1902 static void 1903 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1904 { 1905 struct rxq_refill_cb_arg *cb_arg = arg; 1906 1907 cb_arg->error = error; 1908 cb_arg->seg = segs[0]; 1909 cb_arg->nseg = nseg; 1910 } 1911 1912 /** 1913 * _iflib_fl_refill - refill an rxq free-buffer list 1914 * @ctx: the iflib context 1915 * @fl: the free list to refill 1916 * @count: the number of new buffers to allocate 1917 * 1918 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 1919 * The caller must assure that @count does not exceed the queue's capacity. 1920 */ 1921 static uint8_t 1922 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1923 { 1924 struct if_rxd_update iru; 1925 struct rxq_refill_cb_arg cb_arg; 1926 struct mbuf *m; 1927 caddr_t cl, *sd_cl; 1928 struct mbuf **sd_m; 1929 bus_dmamap_t *sd_map; 1930 bus_addr_t bus_addr, *sd_ba; 1931 int err, frag_idx, i, idx, n, pidx; 1932 qidx_t credits; 1933 1934 sd_m = fl->ifl_sds.ifsd_m; 1935 sd_map = fl->ifl_sds.ifsd_map; 1936 sd_cl = fl->ifl_sds.ifsd_cl; 1937 sd_ba = fl->ifl_sds.ifsd_ba; 1938 pidx = fl->ifl_pidx; 1939 idx = pidx; 1940 frag_idx = fl->ifl_fragidx; 1941 credits = fl->ifl_credits; 1942 1943 i = 0; 1944 n = count; 1945 MPASS(n > 0); 1946 MPASS(credits + n <= fl->ifl_size); 1947 1948 if (pidx < fl->ifl_cidx) 1949 MPASS(pidx + n <= fl->ifl_cidx); 1950 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1951 MPASS(fl->ifl_gen == 0); 1952 if (pidx > fl->ifl_cidx) 1953 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1954 1955 DBG_COUNTER_INC(fl_refills); 1956 if (n > 8) 1957 DBG_COUNTER_INC(fl_refills_large); 1958 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1959 while (n--) { 1960 /* 1961 * We allocate an uninitialized mbuf + cluster, mbuf is 1962 * initialized after rx. 1963 * 1964 * If the cluster is still set then we know a minimum sized packet was received 1965 */ 1966 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 1967 &frag_idx); 1968 if (frag_idx < 0) 1969 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1970 MPASS(frag_idx >= 0); 1971 if ((cl = sd_cl[frag_idx]) == NULL) { 1972 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1973 break; 1974 1975 cb_arg.error = 0; 1976 MPASS(sd_map != NULL); 1977 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 1978 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 1979 BUS_DMA_NOWAIT); 1980 if (err != 0 || cb_arg.error) { 1981 /* 1982 * !zone_pack ? 1983 */ 1984 if (fl->ifl_zone == zone_pack) 1985 uma_zfree(fl->ifl_zone, cl); 1986 break; 1987 } 1988 1989 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 1990 sd_cl[frag_idx] = cl; 1991 #if MEMORY_LOGGING 1992 fl->ifl_cl_enqueued++; 1993 #endif 1994 } else { 1995 bus_addr = sd_ba[frag_idx]; 1996 } 1997 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 1998 BUS_DMASYNC_PREREAD); 1999 2000 if (sd_m[frag_idx] == NULL) { 2001 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 2002 break; 2003 } 2004 sd_m[frag_idx] = m; 2005 } 2006 bit_set(fl->ifl_rx_bitmap, frag_idx); 2007 #if MEMORY_LOGGING 2008 fl->ifl_m_enqueued++; 2009 #endif 2010 2011 DBG_COUNTER_INC(rx_allocs); 2012 fl->ifl_rxd_idxs[i] = frag_idx; 2013 fl->ifl_bus_addrs[i] = bus_addr; 2014 fl->ifl_vm_addrs[i] = cl; 2015 credits++; 2016 i++; 2017 MPASS(credits <= fl->ifl_size); 2018 if (++idx == fl->ifl_size) { 2019 fl->ifl_gen = 1; 2020 idx = 0; 2021 } 2022 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2023 iru.iru_pidx = pidx; 2024 iru.iru_count = i; 2025 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2026 i = 0; 2027 pidx = idx; 2028 fl->ifl_pidx = idx; 2029 fl->ifl_credits = credits; 2030 } 2031 } 2032 2033 if (i) { 2034 iru.iru_pidx = pidx; 2035 iru.iru_count = i; 2036 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2037 fl->ifl_pidx = idx; 2038 fl->ifl_credits = credits; 2039 } 2040 DBG_COUNTER_INC(rxd_flush); 2041 if (fl->ifl_pidx == 0) 2042 pidx = fl->ifl_size - 1; 2043 else 2044 pidx = fl->ifl_pidx - 1; 2045 2046 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2047 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2048 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2049 fl->ifl_fragidx = frag_idx + 1; 2050 if (fl->ifl_fragidx == fl->ifl_size) 2051 fl->ifl_fragidx = 0; 2052 2053 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2054 } 2055 2056 static __inline uint8_t 2057 __iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2058 { 2059 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2060 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2061 #ifdef INVARIANTS 2062 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2063 #endif 2064 2065 MPASS(fl->ifl_credits <= fl->ifl_size); 2066 MPASS(reclaimable == delta); 2067 2068 if (reclaimable > 0) 2069 return (_iflib_fl_refill(ctx, fl, reclaimable)); 2070 return (0); 2071 } 2072 2073 uint8_t 2074 iflib_in_detach(if_ctx_t ctx) 2075 { 2076 bool in_detach; 2077 2078 STATE_LOCK(ctx); 2079 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2080 STATE_UNLOCK(ctx); 2081 return (in_detach); 2082 } 2083 2084 static void 2085 iflib_fl_bufs_free(iflib_fl_t fl) 2086 { 2087 iflib_dma_info_t idi = fl->ifl_ifdi; 2088 bus_dmamap_t sd_map; 2089 uint32_t i; 2090 2091 for (i = 0; i < fl->ifl_size; i++) { 2092 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2093 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2094 2095 if (*sd_cl != NULL) { 2096 sd_map = fl->ifl_sds.ifsd_map[i]; 2097 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2098 BUS_DMASYNC_POSTREAD); 2099 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2100 if (*sd_cl != NULL) 2101 uma_zfree(fl->ifl_zone, *sd_cl); 2102 if (*sd_m != NULL) { 2103 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2104 uma_zfree(zone_mbuf, *sd_m); 2105 } 2106 } else { 2107 MPASS(*sd_cl == NULL); 2108 MPASS(*sd_m == NULL); 2109 } 2110 #if MEMORY_LOGGING 2111 fl->ifl_m_dequeued++; 2112 fl->ifl_cl_dequeued++; 2113 #endif 2114 *sd_cl = NULL; 2115 *sd_m = NULL; 2116 } 2117 #ifdef INVARIANTS 2118 for (i = 0; i < fl->ifl_size; i++) { 2119 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2120 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2121 } 2122 #endif 2123 /* 2124 * Reset free list values 2125 */ 2126 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2127 bzero(idi->idi_vaddr, idi->idi_size); 2128 } 2129 2130 /********************************************************************* 2131 * 2132 * Initialize a free list and its buffers. 2133 * 2134 **********************************************************************/ 2135 static int 2136 iflib_fl_setup(iflib_fl_t fl) 2137 { 2138 iflib_rxq_t rxq = fl->ifl_rxq; 2139 if_ctx_t ctx = rxq->ifr_ctx; 2140 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2141 int qidx; 2142 2143 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2144 /* 2145 ** Free current RX buffer structs and their mbufs 2146 */ 2147 iflib_fl_bufs_free(fl); 2148 /* Now replenish the mbufs */ 2149 MPASS(fl->ifl_credits == 0); 2150 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2151 if (scctx->isc_rxd_buf_size[qidx] != 0) 2152 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2153 else 2154 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2155 /* 2156 * ifl_buf_size may be a driver-supplied value, so pull it up 2157 * to the selected mbuf size. 2158 */ 2159 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2160 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2161 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2162 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2163 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2164 2165 2166 /* avoid pre-allocating zillions of clusters to an idle card 2167 * potentially speeding up attach 2168 */ 2169 (void) _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2170 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2171 if (min(128, fl->ifl_size) != fl->ifl_credits) 2172 return (ENOBUFS); 2173 /* 2174 * handle failure 2175 */ 2176 MPASS(rxq != NULL); 2177 MPASS(fl->ifl_ifdi != NULL); 2178 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2179 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2180 return (0); 2181 } 2182 2183 /********************************************************************* 2184 * 2185 * Free receive ring data structures 2186 * 2187 **********************************************************************/ 2188 static void 2189 iflib_rx_sds_free(iflib_rxq_t rxq) 2190 { 2191 iflib_fl_t fl; 2192 int i, j; 2193 2194 if (rxq->ifr_fl != NULL) { 2195 for (i = 0; i < rxq->ifr_nfl; i++) { 2196 fl = &rxq->ifr_fl[i]; 2197 if (fl->ifl_buf_tag != NULL) { 2198 if (fl->ifl_sds.ifsd_map != NULL) { 2199 for (j = 0; j < fl->ifl_size; j++) { 2200 bus_dmamap_sync( 2201 fl->ifl_buf_tag, 2202 fl->ifl_sds.ifsd_map[j], 2203 BUS_DMASYNC_POSTREAD); 2204 bus_dmamap_unload( 2205 fl->ifl_buf_tag, 2206 fl->ifl_sds.ifsd_map[j]); 2207 bus_dmamap_destroy( 2208 fl->ifl_buf_tag, 2209 fl->ifl_sds.ifsd_map[j]); 2210 } 2211 } 2212 bus_dma_tag_destroy(fl->ifl_buf_tag); 2213 fl->ifl_buf_tag = NULL; 2214 } 2215 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2216 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2217 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2218 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2219 fl->ifl_sds.ifsd_m = NULL; 2220 fl->ifl_sds.ifsd_cl = NULL; 2221 fl->ifl_sds.ifsd_ba = NULL; 2222 fl->ifl_sds.ifsd_map = NULL; 2223 } 2224 free(rxq->ifr_fl, M_IFLIB); 2225 rxq->ifr_fl = NULL; 2226 free(rxq->ifr_ifdi, M_IFLIB); 2227 rxq->ifr_ifdi = NULL; 2228 rxq->ifr_cq_cidx = 0; 2229 } 2230 } 2231 2232 /* 2233 * Timer routine 2234 */ 2235 static void 2236 iflib_timer(void *arg) 2237 { 2238 iflib_txq_t txq = arg; 2239 if_ctx_t ctx = txq->ift_ctx; 2240 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2241 uint64_t this_tick = ticks; 2242 uint32_t reset_on = hz / 2; 2243 2244 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2245 return; 2246 2247 /* 2248 ** Check on the state of the TX queue(s), this 2249 ** can be done without the lock because its RO 2250 ** and the HUNG state will be static if set. 2251 */ 2252 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2253 txq->ift_last_timer_tick = this_tick; 2254 IFDI_TIMER(ctx, txq->ift_id); 2255 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2256 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2257 (sctx->isc_pause_frames == 0))) 2258 goto hung; 2259 2260 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2261 ifmp_ring_is_stalled(txq->ift_br)) { 2262 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down")); 2263 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2264 } 2265 txq->ift_cleaned_prev = txq->ift_cleaned; 2266 } 2267 #ifdef DEV_NETMAP 2268 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2269 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 2270 #endif 2271 /* handle any laggards */ 2272 if (txq->ift_db_pending) 2273 GROUPTASK_ENQUEUE(&txq->ift_task); 2274 2275 sctx->isc_pause_frames = 0; 2276 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2277 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2278 return; 2279 2280 hung: 2281 device_printf(ctx->ifc_dev, 2282 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2283 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2284 STATE_LOCK(ctx); 2285 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2286 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2287 iflib_admin_intr_deferred(ctx); 2288 STATE_UNLOCK(ctx); 2289 } 2290 2291 static uint16_t 2292 iflib_get_mbuf_size_for(unsigned int size) 2293 { 2294 2295 if (size <= MCLBYTES) 2296 return (MCLBYTES); 2297 else 2298 return (MJUMPAGESIZE); 2299 } 2300 2301 static void 2302 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2303 { 2304 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2305 2306 /* 2307 * XXX don't set the max_frame_size to larger 2308 * than the hardware can handle 2309 */ 2310 ctx->ifc_rx_mbuf_sz = 2311 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2312 } 2313 2314 uint32_t 2315 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2316 { 2317 2318 return (ctx->ifc_rx_mbuf_sz); 2319 } 2320 2321 static void 2322 iflib_init_locked(if_ctx_t ctx) 2323 { 2324 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2325 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2326 if_t ifp = ctx->ifc_ifp; 2327 iflib_fl_t fl; 2328 iflib_txq_t txq; 2329 iflib_rxq_t rxq; 2330 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2331 2332 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2333 IFDI_INTR_DISABLE(ctx); 2334 2335 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2336 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2337 /* Set hardware offload abilities */ 2338 if_clearhwassist(ifp); 2339 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2340 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2341 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2342 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2343 if (if_getcapenable(ifp) & IFCAP_TSO4) 2344 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2345 if (if_getcapenable(ifp) & IFCAP_TSO6) 2346 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2347 2348 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2349 CALLOUT_LOCK(txq); 2350 callout_stop(&txq->ift_timer); 2351 CALLOUT_UNLOCK(txq); 2352 iflib_netmap_txq_init(ctx, txq); 2353 } 2354 2355 /* 2356 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2357 * that drivers can use the value when setting up the hardware receive 2358 * buffers. 2359 */ 2360 iflib_calc_rx_mbuf_sz(ctx); 2361 2362 #ifdef INVARIANTS 2363 i = if_getdrvflags(ifp); 2364 #endif 2365 IFDI_INIT(ctx); 2366 MPASS(if_getdrvflags(ifp) == i); 2367 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2368 /* XXX this should really be done on a per-queue basis */ 2369 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2370 MPASS(rxq->ifr_id == i); 2371 iflib_netmap_rxq_init(ctx, rxq); 2372 continue; 2373 } 2374 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2375 if (iflib_fl_setup(fl)) { 2376 device_printf(ctx->ifc_dev, 2377 "setting up free list %d failed - " 2378 "check cluster settings\n", j); 2379 goto done; 2380 } 2381 } 2382 } 2383 done: 2384 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2385 IFDI_INTR_ENABLE(ctx); 2386 txq = ctx->ifc_txqs; 2387 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2388 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2389 txq->ift_timer.c_cpu); 2390 } 2391 2392 static int 2393 iflib_media_change(if_t ifp) 2394 { 2395 if_ctx_t ctx = if_getsoftc(ifp); 2396 int err; 2397 2398 CTX_LOCK(ctx); 2399 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2400 iflib_init_locked(ctx); 2401 CTX_UNLOCK(ctx); 2402 return (err); 2403 } 2404 2405 static void 2406 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2407 { 2408 if_ctx_t ctx = if_getsoftc(ifp); 2409 2410 CTX_LOCK(ctx); 2411 IFDI_UPDATE_ADMIN_STATUS(ctx); 2412 IFDI_MEDIA_STATUS(ctx, ifmr); 2413 CTX_UNLOCK(ctx); 2414 } 2415 2416 void 2417 iflib_stop(if_ctx_t ctx) 2418 { 2419 iflib_txq_t txq = ctx->ifc_txqs; 2420 iflib_rxq_t rxq = ctx->ifc_rxqs; 2421 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2422 if_shared_ctx_t sctx = ctx->ifc_sctx; 2423 iflib_dma_info_t di; 2424 iflib_fl_t fl; 2425 int i, j; 2426 2427 /* Tell the stack that the interface is no longer active */ 2428 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2429 2430 IFDI_INTR_DISABLE(ctx); 2431 DELAY(1000); 2432 IFDI_STOP(ctx); 2433 DELAY(1000); 2434 2435 iflib_debug_reset(); 2436 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2437 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2438 /* make sure all transmitters have completed before proceeding XXX */ 2439 2440 CALLOUT_LOCK(txq); 2441 callout_stop(&txq->ift_timer); 2442 CALLOUT_UNLOCK(txq); 2443 2444 /* clean any enqueued buffers */ 2445 iflib_ifmp_purge(txq); 2446 /* Free any existing tx buffers. */ 2447 for (j = 0; j < txq->ift_size; j++) { 2448 iflib_txsd_free(ctx, txq, j); 2449 } 2450 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2451 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2452 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2453 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2454 txq->ift_pullups = 0; 2455 ifmp_ring_reset_stats(txq->ift_br); 2456 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2457 bzero((void *)di->idi_vaddr, di->idi_size); 2458 } 2459 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2460 /* make sure all transmitters have completed before proceeding XXX */ 2461 2462 rxq->ifr_cq_cidx = 0; 2463 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2464 bzero((void *)di->idi_vaddr, di->idi_size); 2465 /* also resets the free lists pidx/cidx */ 2466 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2467 iflib_fl_bufs_free(fl); 2468 } 2469 } 2470 2471 static inline caddr_t 2472 calc_next_rxd(iflib_fl_t fl, int cidx) 2473 { 2474 qidx_t size; 2475 int nrxd; 2476 caddr_t start, end, cur, next; 2477 2478 nrxd = fl->ifl_size; 2479 size = fl->ifl_rxd_size; 2480 start = fl->ifl_ifdi->idi_vaddr; 2481 2482 if (__predict_false(size == 0)) 2483 return (start); 2484 cur = start + size*cidx; 2485 end = start + size*nrxd; 2486 next = CACHE_PTR_NEXT(cur); 2487 return (next < end ? next : start); 2488 } 2489 2490 static inline void 2491 prefetch_pkts(iflib_fl_t fl, int cidx) 2492 { 2493 int nextptr; 2494 int nrxd = fl->ifl_size; 2495 caddr_t next_rxd; 2496 2497 2498 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2499 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2500 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2501 next_rxd = calc_next_rxd(fl, cidx); 2502 prefetch(next_rxd); 2503 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2504 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2505 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2506 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2507 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2508 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2509 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2510 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2511 } 2512 2513 static struct mbuf * 2514 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2515 int *pf_rv, if_rxd_info_t ri) 2516 { 2517 bus_dmamap_t map; 2518 iflib_fl_t fl; 2519 caddr_t payload; 2520 struct mbuf *m; 2521 int flid, cidx, len, next; 2522 2523 map = NULL; 2524 flid = irf->irf_flid; 2525 cidx = irf->irf_idx; 2526 fl = &rxq->ifr_fl[flid]; 2527 sd->ifsd_fl = fl; 2528 m = fl->ifl_sds.ifsd_m[cidx]; 2529 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2530 fl->ifl_credits--; 2531 #if MEMORY_LOGGING 2532 fl->ifl_m_dequeued++; 2533 #endif 2534 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2535 prefetch_pkts(fl, cidx); 2536 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2537 prefetch(&fl->ifl_sds.ifsd_map[next]); 2538 map = fl->ifl_sds.ifsd_map[cidx]; 2539 2540 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2541 2542 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2543 irf->irf_len != 0) { 2544 payload = *sd->ifsd_cl; 2545 payload += ri->iri_pad; 2546 len = ri->iri_len - ri->iri_pad; 2547 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2548 len | PFIL_MEMPTR | PFIL_IN, NULL); 2549 switch (*pf_rv) { 2550 case PFIL_DROPPED: 2551 case PFIL_CONSUMED: 2552 /* 2553 * The filter ate it. Everything is recycled. 2554 */ 2555 m = NULL; 2556 unload = 0; 2557 break; 2558 case PFIL_REALLOCED: 2559 /* 2560 * The filter copied it. Everything is recycled. 2561 */ 2562 m = pfil_mem2mbuf(payload); 2563 unload = 0; 2564 break; 2565 case PFIL_PASS: 2566 /* 2567 * Filter said it was OK, so receive like 2568 * normal 2569 */ 2570 fl->ifl_sds.ifsd_m[cidx] = NULL; 2571 break; 2572 default: 2573 MPASS(0); 2574 } 2575 } else { 2576 fl->ifl_sds.ifsd_m[cidx] = NULL; 2577 *pf_rv = PFIL_PASS; 2578 } 2579 2580 if (unload && irf->irf_len != 0) 2581 bus_dmamap_unload(fl->ifl_buf_tag, map); 2582 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2583 if (__predict_false(fl->ifl_cidx == 0)) 2584 fl->ifl_gen = 0; 2585 bit_clear(fl->ifl_rx_bitmap, cidx); 2586 return (m); 2587 } 2588 2589 static struct mbuf * 2590 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2591 { 2592 struct mbuf *m, *mh, *mt; 2593 caddr_t cl; 2594 int *pf_rv_ptr, flags, i, padlen; 2595 bool consumed; 2596 2597 i = 0; 2598 mh = NULL; 2599 consumed = false; 2600 *pf_rv = PFIL_PASS; 2601 pf_rv_ptr = pf_rv; 2602 do { 2603 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2604 pf_rv_ptr, ri); 2605 2606 MPASS(*sd->ifsd_cl != NULL); 2607 2608 /* 2609 * Exclude zero-length frags & frags from 2610 * packets the filter has consumed or dropped 2611 */ 2612 if (ri->iri_frags[i].irf_len == 0 || consumed || 2613 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2614 if (mh == NULL) { 2615 /* everything saved here */ 2616 consumed = true; 2617 pf_rv_ptr = NULL; 2618 continue; 2619 } 2620 /* XXX we can save the cluster here, but not the mbuf */ 2621 m_init(m, M_NOWAIT, MT_DATA, 0); 2622 m_free(m); 2623 continue; 2624 } 2625 if (mh == NULL) { 2626 flags = M_PKTHDR|M_EXT; 2627 mh = mt = m; 2628 padlen = ri->iri_pad; 2629 } else { 2630 flags = M_EXT; 2631 mt->m_next = m; 2632 mt = m; 2633 /* assuming padding is only on the first fragment */ 2634 padlen = 0; 2635 } 2636 cl = *sd->ifsd_cl; 2637 *sd->ifsd_cl = NULL; 2638 2639 /* Can these two be made one ? */ 2640 m_init(m, M_NOWAIT, MT_DATA, flags); 2641 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2642 /* 2643 * These must follow m_init and m_cljset 2644 */ 2645 m->m_data += padlen; 2646 ri->iri_len -= padlen; 2647 m->m_len = ri->iri_frags[i].irf_len; 2648 } while (++i < ri->iri_nfrags); 2649 2650 return (mh); 2651 } 2652 2653 /* 2654 * Process one software descriptor 2655 */ 2656 static struct mbuf * 2657 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2658 { 2659 struct if_rxsd sd; 2660 struct mbuf *m; 2661 int pf_rv; 2662 2663 /* should I merge this back in now that the two paths are basically duplicated? */ 2664 if (ri->iri_nfrags == 1 && 2665 ri->iri_frags[0].irf_len != 0 && 2666 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2667 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2668 &pf_rv, ri); 2669 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2670 return (m); 2671 if (pf_rv == PFIL_PASS) { 2672 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2673 #ifndef __NO_STRICT_ALIGNMENT 2674 if (!IP_ALIGNED(m)) 2675 m->m_data += 2; 2676 #endif 2677 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2678 m->m_len = ri->iri_frags[0].irf_len; 2679 } 2680 } else { 2681 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2682 if (m == NULL) 2683 return (NULL); 2684 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2685 return (m); 2686 } 2687 m->m_pkthdr.len = ri->iri_len; 2688 m->m_pkthdr.rcvif = ri->iri_ifp; 2689 m->m_flags |= ri->iri_flags; 2690 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2691 m->m_pkthdr.flowid = ri->iri_flowid; 2692 M_HASHTYPE_SET(m, ri->iri_rsstype); 2693 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2694 m->m_pkthdr.csum_data = ri->iri_csum_data; 2695 return (m); 2696 } 2697 2698 #if defined(INET6) || defined(INET) 2699 static void 2700 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2701 { 2702 CURVNET_SET(lc->ifp->if_vnet); 2703 #if defined(INET6) 2704 *v6 = V_ip6_forwarding; 2705 #endif 2706 #if defined(INET) 2707 *v4 = V_ipforwarding; 2708 #endif 2709 CURVNET_RESTORE(); 2710 } 2711 2712 /* 2713 * Returns true if it's possible this packet could be LROed. 2714 * if it returns false, it is guaranteed that tcp_lro_rx() 2715 * would not return zero. 2716 */ 2717 static bool 2718 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2719 { 2720 struct ether_header *eh; 2721 2722 eh = mtod(m, struct ether_header *); 2723 switch (eh->ether_type) { 2724 #if defined(INET6) 2725 case htons(ETHERTYPE_IPV6): 2726 return (!v6_forwarding); 2727 #endif 2728 #if defined (INET) 2729 case htons(ETHERTYPE_IP): 2730 return (!v4_forwarding); 2731 #endif 2732 } 2733 2734 return false; 2735 } 2736 #else 2737 static void 2738 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2739 { 2740 } 2741 #endif 2742 2743 static void 2744 _task_fn_rx_watchdog(void *context) 2745 { 2746 iflib_rxq_t rxq = context; 2747 2748 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2749 } 2750 2751 static uint8_t 2752 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2753 { 2754 if_t ifp; 2755 if_ctx_t ctx = rxq->ifr_ctx; 2756 if_shared_ctx_t sctx = ctx->ifc_sctx; 2757 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2758 int avail, i; 2759 qidx_t *cidxp; 2760 struct if_rxd_info ri; 2761 int err, budget_left, rx_bytes, rx_pkts; 2762 iflib_fl_t fl; 2763 int lro_enabled; 2764 bool v4_forwarding, v6_forwarding, lro_possible; 2765 uint8_t retval = 0; 2766 2767 /* 2768 * XXX early demux data packets so that if_input processing only handles 2769 * acks in interrupt context 2770 */ 2771 struct mbuf *m, *mh, *mt, *mf; 2772 2773 NET_EPOCH_ASSERT(); 2774 2775 lro_possible = v4_forwarding = v6_forwarding = false; 2776 ifp = ctx->ifc_ifp; 2777 mh = mt = NULL; 2778 MPASS(budget > 0); 2779 rx_pkts = rx_bytes = 0; 2780 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2781 cidxp = &rxq->ifr_cq_cidx; 2782 else 2783 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2784 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2785 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2786 retval |= __iflib_fl_refill_all(ctx, fl); 2787 DBG_COUNTER_INC(rx_unavail); 2788 return (retval); 2789 } 2790 2791 /* pfil needs the vnet to be set */ 2792 CURVNET_SET_QUIET(ifp->if_vnet); 2793 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2794 if (__predict_false(!CTX_ACTIVE(ctx))) { 2795 DBG_COUNTER_INC(rx_ctx_inactive); 2796 break; 2797 } 2798 /* 2799 * Reset client set fields to their default values 2800 */ 2801 rxd_info_zero(&ri); 2802 ri.iri_qsidx = rxq->ifr_id; 2803 ri.iri_cidx = *cidxp; 2804 ri.iri_ifp = ifp; 2805 ri.iri_frags = rxq->ifr_frags; 2806 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2807 2808 if (err) 2809 goto err; 2810 rx_pkts += 1; 2811 rx_bytes += ri.iri_len; 2812 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2813 *cidxp = ri.iri_cidx; 2814 /* Update our consumer index */ 2815 /* XXX NB: shurd - check if this is still safe */ 2816 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2817 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2818 /* was this only a completion queue message? */ 2819 if (__predict_false(ri.iri_nfrags == 0)) 2820 continue; 2821 } 2822 MPASS(ri.iri_nfrags != 0); 2823 MPASS(ri.iri_len != 0); 2824 2825 /* will advance the cidx on the corresponding free lists */ 2826 m = iflib_rxd_pkt_get(rxq, &ri); 2827 avail--; 2828 budget_left--; 2829 if (avail == 0 && budget_left) 2830 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2831 2832 if (__predict_false(m == NULL)) 2833 continue; 2834 2835 /* imm_pkt: -- cxgb */ 2836 if (mh == NULL) 2837 mh = mt = m; 2838 else { 2839 mt->m_nextpkt = m; 2840 mt = m; 2841 } 2842 } 2843 CURVNET_RESTORE(); 2844 /* make sure that we can refill faster than drain */ 2845 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2846 retval |= __iflib_fl_refill_all(ctx, fl); 2847 2848 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2849 if (lro_enabled) 2850 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2851 mt = mf = NULL; 2852 while (mh != NULL) { 2853 m = mh; 2854 mh = mh->m_nextpkt; 2855 m->m_nextpkt = NULL; 2856 #ifndef __NO_STRICT_ALIGNMENT 2857 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2858 continue; 2859 #endif 2860 rx_bytes += m->m_pkthdr.len; 2861 rx_pkts++; 2862 #if defined(INET6) || defined(INET) 2863 if (lro_enabled) { 2864 if (!lro_possible) { 2865 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2866 if (lro_possible && mf != NULL) { 2867 ifp->if_input(ifp, mf); 2868 DBG_COUNTER_INC(rx_if_input); 2869 mt = mf = NULL; 2870 } 2871 } 2872 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2873 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2874 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2875 continue; 2876 } 2877 } 2878 #endif 2879 if (lro_possible) { 2880 ifp->if_input(ifp, m); 2881 DBG_COUNTER_INC(rx_if_input); 2882 continue; 2883 } 2884 2885 if (mf == NULL) 2886 mf = m; 2887 if (mt != NULL) 2888 mt->m_nextpkt = m; 2889 mt = m; 2890 } 2891 if (mf != NULL) { 2892 ifp->if_input(ifp, mf); 2893 DBG_COUNTER_INC(rx_if_input); 2894 } 2895 2896 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2897 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2898 2899 /* 2900 * Flush any outstanding LRO work 2901 */ 2902 #if defined(INET6) || defined(INET) 2903 tcp_lro_flush_all(&rxq->ifr_lc); 2904 #endif 2905 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 2906 retval |= IFLIB_RXEOF_MORE; 2907 return (retval); 2908 err: 2909 STATE_LOCK(ctx); 2910 ctx->ifc_flags |= IFC_DO_RESET; 2911 iflib_admin_intr_deferred(ctx); 2912 STATE_UNLOCK(ctx); 2913 return (0); 2914 } 2915 2916 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2917 static inline qidx_t 2918 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2919 { 2920 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2921 qidx_t minthresh = txq->ift_size / 8; 2922 if (in_use > 4*minthresh) 2923 return (notify_count); 2924 if (in_use > 2*minthresh) 2925 return (notify_count >> 1); 2926 if (in_use > minthresh) 2927 return (notify_count >> 3); 2928 return (0); 2929 } 2930 2931 static inline qidx_t 2932 txq_max_rs_deferred(iflib_txq_t txq) 2933 { 2934 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2935 qidx_t minthresh = txq->ift_size / 8; 2936 if (txq->ift_in_use > 4*minthresh) 2937 return (notify_count); 2938 if (txq->ift_in_use > 2*minthresh) 2939 return (notify_count >> 1); 2940 if (txq->ift_in_use > minthresh) 2941 return (notify_count >> 2); 2942 return (2); 2943 } 2944 2945 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2946 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2947 2948 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2949 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2950 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2951 2952 /* forward compatibility for cxgb */ 2953 #define FIRST_QSET(ctx) 0 2954 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2955 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2956 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2957 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2958 2959 /* XXX we should be setting this to something other than zero */ 2960 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2961 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2962 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2963 2964 static inline bool 2965 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2966 { 2967 qidx_t dbval, max; 2968 bool rang; 2969 2970 rang = false; 2971 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2972 if (ring || txq->ift_db_pending >= max) { 2973 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2974 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 2975 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2976 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2977 txq->ift_db_pending = txq->ift_npending = 0; 2978 rang = true; 2979 } 2980 return (rang); 2981 } 2982 2983 #ifdef PKT_DEBUG 2984 static void 2985 print_pkt(if_pkt_info_t pi) 2986 { 2987 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2988 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2989 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2990 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2991 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2992 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2993 } 2994 #endif 2995 2996 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2997 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2998 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2999 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3000 3001 static int 3002 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3003 { 3004 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3005 struct ether_vlan_header *eh; 3006 struct mbuf *m; 3007 3008 m = *mp; 3009 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3010 M_WRITABLE(m) == 0) { 3011 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3012 return (ENOMEM); 3013 } else { 3014 m_freem(*mp); 3015 DBG_COUNTER_INC(tx_frees); 3016 *mp = m; 3017 } 3018 } 3019 3020 /* 3021 * Determine where frame payload starts. 3022 * Jump over vlan headers if already present, 3023 * helpful for QinQ too. 3024 */ 3025 if (__predict_false(m->m_len < sizeof(*eh))) { 3026 txq->ift_pullups++; 3027 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3028 return (ENOMEM); 3029 } 3030 eh = mtod(m, struct ether_vlan_header *); 3031 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3032 pi->ipi_etype = ntohs(eh->evl_proto); 3033 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3034 } else { 3035 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3036 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3037 } 3038 3039 switch (pi->ipi_etype) { 3040 #ifdef INET 3041 case ETHERTYPE_IP: 3042 { 3043 struct mbuf *n; 3044 struct ip *ip = NULL; 3045 struct tcphdr *th = NULL; 3046 int minthlen; 3047 3048 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3049 if (__predict_false(m->m_len < minthlen)) { 3050 /* 3051 * if this code bloat is causing too much of a hit 3052 * move it to a separate function and mark it noinline 3053 */ 3054 if (m->m_len == pi->ipi_ehdrlen) { 3055 n = m->m_next; 3056 MPASS(n); 3057 if (n->m_len >= sizeof(*ip)) { 3058 ip = (struct ip *)n->m_data; 3059 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3060 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3061 } else { 3062 txq->ift_pullups++; 3063 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3064 return (ENOMEM); 3065 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3066 } 3067 } else { 3068 txq->ift_pullups++; 3069 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3070 return (ENOMEM); 3071 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3072 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3073 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3074 } 3075 } else { 3076 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3077 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3078 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3079 } 3080 pi->ipi_ip_hlen = ip->ip_hl << 2; 3081 pi->ipi_ipproto = ip->ip_p; 3082 pi->ipi_flags |= IPI_TX_IPV4; 3083 3084 /* TCP checksum offload may require TCP header length */ 3085 if (IS_TX_OFFLOAD4(pi)) { 3086 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3087 if (__predict_false(th == NULL)) { 3088 txq->ift_pullups++; 3089 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3090 return (ENOMEM); 3091 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3092 } 3093 pi->ipi_tcp_hflags = th->th_flags; 3094 pi->ipi_tcp_hlen = th->th_off << 2; 3095 pi->ipi_tcp_seq = th->th_seq; 3096 } 3097 if (IS_TSO4(pi)) { 3098 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3099 return (ENXIO); 3100 /* 3101 * TSO always requires hardware checksum offload. 3102 */ 3103 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3104 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3105 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3106 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3107 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3108 ip->ip_sum = 0; 3109 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3110 } 3111 } 3112 } 3113 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3114 ip->ip_sum = 0; 3115 3116 break; 3117 } 3118 #endif 3119 #ifdef INET6 3120 case ETHERTYPE_IPV6: 3121 { 3122 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3123 struct tcphdr *th; 3124 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3125 3126 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3127 txq->ift_pullups++; 3128 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3129 return (ENOMEM); 3130 } 3131 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3132 3133 /* XXX-BZ this will go badly in case of ext hdrs. */ 3134 pi->ipi_ipproto = ip6->ip6_nxt; 3135 pi->ipi_flags |= IPI_TX_IPV6; 3136 3137 /* TCP checksum offload may require TCP header length */ 3138 if (IS_TX_OFFLOAD6(pi)) { 3139 if (pi->ipi_ipproto == IPPROTO_TCP) { 3140 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3141 txq->ift_pullups++; 3142 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3143 return (ENOMEM); 3144 } 3145 pi->ipi_tcp_hflags = th->th_flags; 3146 pi->ipi_tcp_hlen = th->th_off << 2; 3147 pi->ipi_tcp_seq = th->th_seq; 3148 } 3149 if (IS_TSO6(pi)) { 3150 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3151 return (ENXIO); 3152 /* 3153 * TSO always requires hardware checksum offload. 3154 */ 3155 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3156 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3157 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3158 } 3159 } 3160 break; 3161 } 3162 #endif 3163 default: 3164 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3165 pi->ipi_ip_hlen = 0; 3166 break; 3167 } 3168 *mp = m; 3169 3170 return (0); 3171 } 3172 3173 /* 3174 * If dodgy hardware rejects the scatter gather chain we've handed it 3175 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3176 * m_defrag'd mbufs 3177 */ 3178 static __noinline struct mbuf * 3179 iflib_remove_mbuf(iflib_txq_t txq) 3180 { 3181 int ntxd, pidx; 3182 struct mbuf *m, **ifsd_m; 3183 3184 ifsd_m = txq->ift_sds.ifsd_m; 3185 ntxd = txq->ift_size; 3186 pidx = txq->ift_pidx & (ntxd - 1); 3187 ifsd_m = txq->ift_sds.ifsd_m; 3188 m = ifsd_m[pidx]; 3189 ifsd_m[pidx] = NULL; 3190 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3191 if (txq->ift_sds.ifsd_tso_map != NULL) 3192 bus_dmamap_unload(txq->ift_tso_buf_tag, 3193 txq->ift_sds.ifsd_tso_map[pidx]); 3194 #if MEMORY_LOGGING 3195 txq->ift_dequeued++; 3196 #endif 3197 return (m); 3198 } 3199 3200 static inline caddr_t 3201 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3202 { 3203 qidx_t size; 3204 int ntxd; 3205 caddr_t start, end, cur, next; 3206 3207 ntxd = txq->ift_size; 3208 size = txq->ift_txd_size[qid]; 3209 start = txq->ift_ifdi[qid].idi_vaddr; 3210 3211 if (__predict_false(size == 0)) 3212 return (start); 3213 cur = start + size*cidx; 3214 end = start + size*ntxd; 3215 next = CACHE_PTR_NEXT(cur); 3216 return (next < end ? next : start); 3217 } 3218 3219 /* 3220 * Pad an mbuf to ensure a minimum ethernet frame size. 3221 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3222 */ 3223 static __noinline int 3224 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3225 { 3226 /* 3227 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3228 * and ARP message is the smallest common payload I can think of 3229 */ 3230 static char pad[18]; /* just zeros */ 3231 int n; 3232 struct mbuf *new_head; 3233 3234 if (!M_WRITABLE(*m_head)) { 3235 new_head = m_dup(*m_head, M_NOWAIT); 3236 if (new_head == NULL) { 3237 m_freem(*m_head); 3238 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3239 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3240 DBG_COUNTER_INC(tx_frees); 3241 return ENOMEM; 3242 } 3243 m_freem(*m_head); 3244 *m_head = new_head; 3245 } 3246 3247 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3248 n > 0; n -= sizeof(pad)) 3249 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3250 break; 3251 3252 if (n > 0) { 3253 m_freem(*m_head); 3254 device_printf(dev, "cannot pad short frame\n"); 3255 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3256 DBG_COUNTER_INC(tx_frees); 3257 return (ENOBUFS); 3258 } 3259 3260 return 0; 3261 } 3262 3263 static int 3264 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3265 { 3266 if_ctx_t ctx; 3267 if_shared_ctx_t sctx; 3268 if_softc_ctx_t scctx; 3269 bus_dma_tag_t buf_tag; 3270 bus_dma_segment_t *segs; 3271 struct mbuf *m_head, **ifsd_m; 3272 void *next_txd; 3273 bus_dmamap_t map; 3274 struct if_pkt_info pi; 3275 int remap = 0; 3276 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3277 3278 ctx = txq->ift_ctx; 3279 sctx = ctx->ifc_sctx; 3280 scctx = &ctx->ifc_softc_ctx; 3281 segs = txq->ift_segs; 3282 ntxd = txq->ift_size; 3283 m_head = *m_headp; 3284 map = NULL; 3285 3286 /* 3287 * If we're doing TSO the next descriptor to clean may be quite far ahead 3288 */ 3289 cidx = txq->ift_cidx; 3290 pidx = txq->ift_pidx; 3291 if (ctx->ifc_flags & IFC_PREFETCH) { 3292 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3293 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3294 next_txd = calc_next_txd(txq, cidx, 0); 3295 prefetch(next_txd); 3296 } 3297 3298 /* prefetch the next cache line of mbuf pointers and flags */ 3299 prefetch(&txq->ift_sds.ifsd_m[next]); 3300 prefetch(&txq->ift_sds.ifsd_map[next]); 3301 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3302 } 3303 map = txq->ift_sds.ifsd_map[pidx]; 3304 ifsd_m = txq->ift_sds.ifsd_m; 3305 3306 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3307 buf_tag = txq->ift_tso_buf_tag; 3308 max_segs = scctx->isc_tx_tso_segments_max; 3309 map = txq->ift_sds.ifsd_tso_map[pidx]; 3310 MPASS(buf_tag != NULL); 3311 MPASS(max_segs > 0); 3312 } else { 3313 buf_tag = txq->ift_buf_tag; 3314 max_segs = scctx->isc_tx_nsegments; 3315 map = txq->ift_sds.ifsd_map[pidx]; 3316 } 3317 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3318 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3319 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3320 if (err) { 3321 DBG_COUNTER_INC(encap_txd_encap_fail); 3322 return err; 3323 } 3324 } 3325 m_head = *m_headp; 3326 3327 pkt_info_zero(&pi); 3328 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3329 pi.ipi_pidx = pidx; 3330 pi.ipi_qsidx = txq->ift_id; 3331 pi.ipi_len = m_head->m_pkthdr.len; 3332 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3333 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3334 3335 /* deliberate bitwise OR to make one condition */ 3336 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3337 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3338 DBG_COUNTER_INC(encap_txd_encap_fail); 3339 return (err); 3340 } 3341 m_head = *m_headp; 3342 } 3343 3344 retry: 3345 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3346 BUS_DMA_NOWAIT); 3347 defrag: 3348 if (__predict_false(err)) { 3349 switch (err) { 3350 case EFBIG: 3351 /* try collapse once and defrag once */ 3352 if (remap == 0) { 3353 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3354 /* try defrag if collapsing fails */ 3355 if (m_head == NULL) 3356 remap++; 3357 } 3358 if (remap == 1) { 3359 txq->ift_mbuf_defrag++; 3360 m_head = m_defrag(*m_headp, M_NOWAIT); 3361 } 3362 /* 3363 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3364 * failed to map an mbuf that was run through m_defrag 3365 */ 3366 MPASS(remap <= 1); 3367 if (__predict_false(m_head == NULL || remap > 1)) 3368 goto defrag_failed; 3369 remap++; 3370 *m_headp = m_head; 3371 goto retry; 3372 break; 3373 case ENOMEM: 3374 txq->ift_no_tx_dma_setup++; 3375 break; 3376 default: 3377 txq->ift_no_tx_dma_setup++; 3378 m_freem(*m_headp); 3379 DBG_COUNTER_INC(tx_frees); 3380 *m_headp = NULL; 3381 break; 3382 } 3383 txq->ift_map_failed++; 3384 DBG_COUNTER_INC(encap_load_mbuf_fail); 3385 DBG_COUNTER_INC(encap_txd_encap_fail); 3386 return (err); 3387 } 3388 ifsd_m[pidx] = m_head; 3389 /* 3390 * XXX assumes a 1 to 1 relationship between segments and 3391 * descriptors - this does not hold true on all drivers, e.g. 3392 * cxgb 3393 */ 3394 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3395 txq->ift_no_desc_avail++; 3396 bus_dmamap_unload(buf_tag, map); 3397 DBG_COUNTER_INC(encap_txq_avail_fail); 3398 DBG_COUNTER_INC(encap_txd_encap_fail); 3399 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3400 GROUPTASK_ENQUEUE(&txq->ift_task); 3401 return (ENOBUFS); 3402 } 3403 /* 3404 * On Intel cards we can greatly reduce the number of TX interrupts 3405 * we see by only setting report status on every Nth descriptor. 3406 * However, this also means that the driver will need to keep track 3407 * of the descriptors that RS was set on to check them for the DD bit. 3408 */ 3409 txq->ift_rs_pending += nsegs + 1; 3410 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3411 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3412 pi.ipi_flags |= IPI_TX_INTR; 3413 txq->ift_rs_pending = 0; 3414 } 3415 3416 pi.ipi_segs = segs; 3417 pi.ipi_nsegs = nsegs; 3418 3419 MPASS(pidx >= 0 && pidx < txq->ift_size); 3420 #ifdef PKT_DEBUG 3421 print_pkt(&pi); 3422 #endif 3423 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3424 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3425 DBG_COUNTER_INC(tx_encap); 3426 MPASS(pi.ipi_new_pidx < txq->ift_size); 3427 3428 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3429 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3430 ndesc += txq->ift_size; 3431 txq->ift_gen = 1; 3432 } 3433 /* 3434 * drivers can need as many as 3435 * two sentinels 3436 */ 3437 MPASS(ndesc <= pi.ipi_nsegs + 2); 3438 MPASS(pi.ipi_new_pidx != pidx); 3439 MPASS(ndesc > 0); 3440 txq->ift_in_use += ndesc; 3441 3442 /* 3443 * We update the last software descriptor again here because there may 3444 * be a sentinel and/or there may be more mbufs than segments 3445 */ 3446 txq->ift_pidx = pi.ipi_new_pidx; 3447 txq->ift_npending += pi.ipi_ndescs; 3448 } else { 3449 *m_headp = m_head = iflib_remove_mbuf(txq); 3450 if (err == EFBIG) { 3451 txq->ift_txd_encap_efbig++; 3452 if (remap < 2) { 3453 remap = 1; 3454 goto defrag; 3455 } 3456 } 3457 goto defrag_failed; 3458 } 3459 /* 3460 * err can't possibly be non-zero here, so we don't neet to test it 3461 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3462 */ 3463 return (err); 3464 3465 defrag_failed: 3466 txq->ift_mbuf_defrag_failed++; 3467 txq->ift_map_failed++; 3468 m_freem(*m_headp); 3469 DBG_COUNTER_INC(tx_frees); 3470 *m_headp = NULL; 3471 DBG_COUNTER_INC(encap_txd_encap_fail); 3472 return (ENOMEM); 3473 } 3474 3475 static void 3476 iflib_tx_desc_free(iflib_txq_t txq, int n) 3477 { 3478 uint32_t qsize, cidx, mask, gen; 3479 struct mbuf *m, **ifsd_m; 3480 bool do_prefetch; 3481 3482 cidx = txq->ift_cidx; 3483 gen = txq->ift_gen; 3484 qsize = txq->ift_size; 3485 mask = qsize-1; 3486 ifsd_m = txq->ift_sds.ifsd_m; 3487 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3488 3489 while (n-- > 0) { 3490 if (do_prefetch) { 3491 prefetch(ifsd_m[(cidx + 3) & mask]); 3492 prefetch(ifsd_m[(cidx + 4) & mask]); 3493 } 3494 if ((m = ifsd_m[cidx]) != NULL) { 3495 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3496 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3497 bus_dmamap_sync(txq->ift_tso_buf_tag, 3498 txq->ift_sds.ifsd_tso_map[cidx], 3499 BUS_DMASYNC_POSTWRITE); 3500 bus_dmamap_unload(txq->ift_tso_buf_tag, 3501 txq->ift_sds.ifsd_tso_map[cidx]); 3502 } else { 3503 bus_dmamap_sync(txq->ift_buf_tag, 3504 txq->ift_sds.ifsd_map[cidx], 3505 BUS_DMASYNC_POSTWRITE); 3506 bus_dmamap_unload(txq->ift_buf_tag, 3507 txq->ift_sds.ifsd_map[cidx]); 3508 } 3509 /* XXX we don't support any drivers that batch packets yet */ 3510 MPASS(m->m_nextpkt == NULL); 3511 m_freem(m); 3512 ifsd_m[cidx] = NULL; 3513 #if MEMORY_LOGGING 3514 txq->ift_dequeued++; 3515 #endif 3516 DBG_COUNTER_INC(tx_frees); 3517 } 3518 if (__predict_false(++cidx == qsize)) { 3519 cidx = 0; 3520 gen = 0; 3521 } 3522 } 3523 txq->ift_cidx = cidx; 3524 txq->ift_gen = gen; 3525 } 3526 3527 static __inline int 3528 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3529 { 3530 int reclaim; 3531 if_ctx_t ctx = txq->ift_ctx; 3532 3533 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3534 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3535 3536 /* 3537 * Need a rate-limiting check so that this isn't called every time 3538 */ 3539 iflib_tx_credits_update(ctx, txq); 3540 reclaim = DESC_RECLAIMABLE(txq); 3541 3542 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3543 #ifdef INVARIANTS 3544 if (iflib_verbose_debug) { 3545 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3546 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3547 reclaim, thresh); 3548 3549 } 3550 #endif 3551 return (0); 3552 } 3553 iflib_tx_desc_free(txq, reclaim); 3554 txq->ift_cleaned += reclaim; 3555 txq->ift_in_use -= reclaim; 3556 3557 return (reclaim); 3558 } 3559 3560 static struct mbuf ** 3561 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3562 { 3563 int next, size; 3564 struct mbuf **items; 3565 3566 size = r->size; 3567 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3568 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3569 3570 prefetch(items[(cidx + offset) & (size-1)]); 3571 if (remaining > 1) { 3572 prefetch2cachelines(&items[next]); 3573 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3574 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3575 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3576 } 3577 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3578 } 3579 3580 static void 3581 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3582 { 3583 3584 ifmp_ring_check_drainage(txq->ift_br, budget); 3585 } 3586 3587 static uint32_t 3588 iflib_txq_can_drain(struct ifmp_ring *r) 3589 { 3590 iflib_txq_t txq = r->cookie; 3591 if_ctx_t ctx = txq->ift_ctx; 3592 3593 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3594 return (1); 3595 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3596 BUS_DMASYNC_POSTREAD); 3597 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3598 false)); 3599 } 3600 3601 static uint32_t 3602 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3603 { 3604 iflib_txq_t txq = r->cookie; 3605 if_ctx_t ctx = txq->ift_ctx; 3606 if_t ifp = ctx->ifc_ifp; 3607 struct mbuf *m, **mp; 3608 int avail, bytes_sent, consumed, count, err, i, in_use_prev; 3609 int mcast_sent, pkt_sent, reclaimed, txq_avail; 3610 bool do_prefetch, rang, ring; 3611 3612 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3613 !LINK_ACTIVE(ctx))) { 3614 DBG_COUNTER_INC(txq_drain_notready); 3615 return (0); 3616 } 3617 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3618 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3619 avail = IDXDIFF(pidx, cidx, r->size); 3620 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3621 DBG_COUNTER_INC(txq_drain_flushing); 3622 for (i = 0; i < avail; i++) { 3623 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3624 m_free(r->items[(cidx + i) & (r->size-1)]); 3625 r->items[(cidx + i) & (r->size-1)] = NULL; 3626 } 3627 return (avail); 3628 } 3629 3630 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3631 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3632 CALLOUT_LOCK(txq); 3633 callout_stop(&txq->ift_timer); 3634 CALLOUT_UNLOCK(txq); 3635 DBG_COUNTER_INC(txq_drain_oactive); 3636 return (0); 3637 } 3638 if (reclaimed) 3639 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3640 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3641 count = MIN(avail, TX_BATCH_SIZE); 3642 #ifdef INVARIANTS 3643 if (iflib_verbose_debug) 3644 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3645 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3646 #endif 3647 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3648 txq_avail = TXQ_AVAIL(txq); 3649 err = 0; 3650 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) { 3651 int rem = do_prefetch ? count - i : 0; 3652 3653 mp = _ring_peek_one(r, cidx, i, rem); 3654 MPASS(mp != NULL && *mp != NULL); 3655 if (__predict_false(*mp == (struct mbuf *)txq)) { 3656 consumed++; 3657 continue; 3658 } 3659 in_use_prev = txq->ift_in_use; 3660 err = iflib_encap(txq, mp); 3661 if (__predict_false(err)) { 3662 /* no room - bail out */ 3663 if (err == ENOBUFS) 3664 break; 3665 consumed++; 3666 /* we can't send this packet - skip it */ 3667 continue; 3668 } 3669 consumed++; 3670 pkt_sent++; 3671 m = *mp; 3672 DBG_COUNTER_INC(tx_sent); 3673 bytes_sent += m->m_pkthdr.len; 3674 mcast_sent += !!(m->m_flags & M_MCAST); 3675 txq_avail = TXQ_AVAIL(txq); 3676 3677 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3678 ETHER_BPF_MTAP(ifp, m); 3679 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3680 break; 3681 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3682 } 3683 3684 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3685 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3686 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3687 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3688 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3689 if (mcast_sent) 3690 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3691 #ifdef INVARIANTS 3692 if (iflib_verbose_debug) 3693 printf("consumed=%d\n", consumed); 3694 #endif 3695 return (consumed); 3696 } 3697 3698 static uint32_t 3699 iflib_txq_drain_always(struct ifmp_ring *r) 3700 { 3701 return (1); 3702 } 3703 3704 static uint32_t 3705 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3706 { 3707 int i, avail; 3708 struct mbuf **mp; 3709 iflib_txq_t txq; 3710 3711 txq = r->cookie; 3712 3713 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3714 CALLOUT_LOCK(txq); 3715 callout_stop(&txq->ift_timer); 3716 CALLOUT_UNLOCK(txq); 3717 3718 avail = IDXDIFF(pidx, cidx, r->size); 3719 for (i = 0; i < avail; i++) { 3720 mp = _ring_peek_one(r, cidx, i, avail - i); 3721 if (__predict_false(*mp == (struct mbuf *)txq)) 3722 continue; 3723 m_freem(*mp); 3724 DBG_COUNTER_INC(tx_frees); 3725 } 3726 MPASS(ifmp_ring_is_stalled(r) == 0); 3727 return (avail); 3728 } 3729 3730 static void 3731 iflib_ifmp_purge(iflib_txq_t txq) 3732 { 3733 struct ifmp_ring *r; 3734 3735 r = txq->ift_br; 3736 r->drain = iflib_txq_drain_free; 3737 r->can_drain = iflib_txq_drain_always; 3738 3739 ifmp_ring_check_drainage(r, r->size); 3740 3741 r->drain = iflib_txq_drain; 3742 r->can_drain = iflib_txq_can_drain; 3743 } 3744 3745 static void 3746 _task_fn_tx(void *context) 3747 { 3748 iflib_txq_t txq = context; 3749 if_ctx_t ctx = txq->ift_ctx; 3750 #if defined(ALTQ) || defined(DEV_NETMAP) 3751 if_t ifp = ctx->ifc_ifp; 3752 #endif 3753 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3754 3755 #ifdef IFLIB_DIAGNOSTICS 3756 txq->ift_cpu_exec_count[curcpu]++; 3757 #endif 3758 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3759 return; 3760 #ifdef DEV_NETMAP 3761 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3762 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3763 BUS_DMASYNC_POSTREAD); 3764 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3765 netmap_tx_irq(ifp, txq->ift_id); 3766 if (ctx->ifc_flags & IFC_LEGACY) 3767 IFDI_INTR_ENABLE(ctx); 3768 else 3769 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3770 return; 3771 } 3772 #endif 3773 #ifdef ALTQ 3774 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3775 iflib_altq_if_start(ifp); 3776 #endif 3777 if (txq->ift_db_pending) 3778 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3779 else if (!abdicate) 3780 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3781 /* 3782 * When abdicating, we always need to check drainage, not just when we don't enqueue 3783 */ 3784 if (abdicate) 3785 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3786 if (ctx->ifc_flags & IFC_LEGACY) 3787 IFDI_INTR_ENABLE(ctx); 3788 else 3789 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3790 } 3791 3792 static void 3793 _task_fn_rx(void *context) 3794 { 3795 iflib_rxq_t rxq = context; 3796 if_ctx_t ctx = rxq->ifr_ctx; 3797 uint8_t more; 3798 uint16_t budget; 3799 #ifdef DEV_NETMAP 3800 u_int work = 0; 3801 int nmirq; 3802 #endif 3803 3804 #ifdef IFLIB_DIAGNOSTICS 3805 rxq->ifr_cpu_exec_count[curcpu]++; 3806 #endif 3807 DBG_COUNTER_INC(task_fn_rxs); 3808 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3809 return; 3810 #ifdef DEV_NETMAP 3811 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 3812 if (nmirq != NM_IRQ_PASS) { 3813 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 3814 goto skip_rxeof; 3815 } 3816 #endif 3817 budget = ctx->ifc_sysctl_rx_budget; 3818 if (budget == 0) 3819 budget = 16; /* XXX */ 3820 more = iflib_rxeof(rxq, budget); 3821 #ifdef DEV_NETMAP 3822 skip_rxeof: 3823 #endif 3824 if ((more & IFLIB_RXEOF_MORE) == 0) { 3825 if (ctx->ifc_flags & IFC_LEGACY) 3826 IFDI_INTR_ENABLE(ctx); 3827 else 3828 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3829 DBG_COUNTER_INC(rx_intr_enables); 3830 } 3831 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3832 return; 3833 3834 if (more & IFLIB_RXEOF_MORE) 3835 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3836 else if (more & IFLIB_RXEOF_EMPTY) 3837 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 3838 } 3839 3840 static void 3841 _task_fn_admin(void *context) 3842 { 3843 if_ctx_t ctx = context; 3844 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3845 iflib_txq_t txq; 3846 int i; 3847 bool oactive, running, do_reset, do_watchdog, in_detach; 3848 uint32_t reset_on = hz / 2; 3849 3850 STATE_LOCK(ctx); 3851 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3852 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3853 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3854 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3855 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3856 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3857 STATE_UNLOCK(ctx); 3858 3859 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3860 return; 3861 if (in_detach) 3862 return; 3863 3864 CTX_LOCK(ctx); 3865 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3866 CALLOUT_LOCK(txq); 3867 callout_stop(&txq->ift_timer); 3868 CALLOUT_UNLOCK(txq); 3869 } 3870 if (do_watchdog) { 3871 ctx->ifc_watchdog_events++; 3872 IFDI_WATCHDOG_RESET(ctx); 3873 } 3874 IFDI_UPDATE_ADMIN_STATUS(ctx); 3875 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3876 #ifdef DEV_NETMAP 3877 reset_on = hz / 2; 3878 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3879 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 3880 #endif 3881 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3882 } 3883 IFDI_LINK_INTR_ENABLE(ctx); 3884 if (do_reset) 3885 iflib_if_init_locked(ctx); 3886 CTX_UNLOCK(ctx); 3887 3888 if (LINK_ACTIVE(ctx) == 0) 3889 return; 3890 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3891 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3892 } 3893 3894 3895 static void 3896 _task_fn_iov(void *context) 3897 { 3898 if_ctx_t ctx = context; 3899 3900 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3901 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3902 return; 3903 3904 CTX_LOCK(ctx); 3905 IFDI_VFLR_HANDLE(ctx); 3906 CTX_UNLOCK(ctx); 3907 } 3908 3909 static int 3910 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3911 { 3912 int err; 3913 if_int_delay_info_t info; 3914 if_ctx_t ctx; 3915 3916 info = (if_int_delay_info_t)arg1; 3917 ctx = info->iidi_ctx; 3918 info->iidi_req = req; 3919 info->iidi_oidp = oidp; 3920 CTX_LOCK(ctx); 3921 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3922 CTX_UNLOCK(ctx); 3923 return (err); 3924 } 3925 3926 /********************************************************************* 3927 * 3928 * IFNET FUNCTIONS 3929 * 3930 **********************************************************************/ 3931 3932 static void 3933 iflib_if_init_locked(if_ctx_t ctx) 3934 { 3935 iflib_stop(ctx); 3936 iflib_init_locked(ctx); 3937 } 3938 3939 3940 static void 3941 iflib_if_init(void *arg) 3942 { 3943 if_ctx_t ctx = arg; 3944 3945 CTX_LOCK(ctx); 3946 iflib_if_init_locked(ctx); 3947 CTX_UNLOCK(ctx); 3948 } 3949 3950 static int 3951 iflib_if_transmit(if_t ifp, struct mbuf *m) 3952 { 3953 if_ctx_t ctx = if_getsoftc(ifp); 3954 3955 iflib_txq_t txq; 3956 int err, qidx; 3957 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3958 3959 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3960 DBG_COUNTER_INC(tx_frees); 3961 m_freem(m); 3962 return (ENETDOWN); 3963 } 3964 3965 MPASS(m->m_nextpkt == NULL); 3966 /* ALTQ-enabled interfaces always use queue 0. */ 3967 qidx = 0; 3968 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3969 qidx = QIDX(ctx, m); 3970 /* 3971 * XXX calculate buf_ring based on flowid (divvy up bits?) 3972 */ 3973 txq = &ctx->ifc_txqs[qidx]; 3974 3975 #ifdef DRIVER_BACKPRESSURE 3976 if (txq->ift_closed) { 3977 while (m != NULL) { 3978 next = m->m_nextpkt; 3979 m->m_nextpkt = NULL; 3980 m_freem(m); 3981 DBG_COUNTER_INC(tx_frees); 3982 m = next; 3983 } 3984 return (ENOBUFS); 3985 } 3986 #endif 3987 #ifdef notyet 3988 qidx = count = 0; 3989 mp = marr; 3990 next = m; 3991 do { 3992 count++; 3993 next = next->m_nextpkt; 3994 } while (next != NULL); 3995 3996 if (count > nitems(marr)) 3997 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3998 /* XXX check nextpkt */ 3999 m_freem(m); 4000 /* XXX simplify for now */ 4001 DBG_COUNTER_INC(tx_frees); 4002 return (ENOBUFS); 4003 } 4004 for (next = m, i = 0; next != NULL; i++) { 4005 mp[i] = next; 4006 next = next->m_nextpkt; 4007 mp[i]->m_nextpkt = NULL; 4008 } 4009 #endif 4010 DBG_COUNTER_INC(tx_seen); 4011 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4012 4013 if (abdicate) 4014 GROUPTASK_ENQUEUE(&txq->ift_task); 4015 if (err) { 4016 if (!abdicate) 4017 GROUPTASK_ENQUEUE(&txq->ift_task); 4018 /* support forthcoming later */ 4019 #ifdef DRIVER_BACKPRESSURE 4020 txq->ift_closed = TRUE; 4021 #endif 4022 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4023 m_freem(m); 4024 DBG_COUNTER_INC(tx_frees); 4025 } 4026 4027 return (err); 4028 } 4029 4030 #ifdef ALTQ 4031 /* 4032 * The overall approach to integrating iflib with ALTQ is to continue to use 4033 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4034 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4035 * is redundant/unnecessary, but doing so minimizes the amount of 4036 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4037 * redundantly queueing to an intermediate mp_ring is swamped by the 4038 * performance limitations inherent in using ALTQ. 4039 * 4040 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4041 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4042 * given interface. If ALTQ is enabled for an interface, then all 4043 * transmitted packets for that interface will be submitted to the ALTQ 4044 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4045 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4046 * update stats that the iflib machinery handles, and which is sensitve to 4047 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4048 * will be installed as the start routine for use by ALTQ facilities that 4049 * need to trigger queue drains on a scheduled basis. 4050 * 4051 */ 4052 static void 4053 iflib_altq_if_start(if_t ifp) 4054 { 4055 struct ifaltq *ifq = &ifp->if_snd; 4056 struct mbuf *m; 4057 4058 IFQ_LOCK(ifq); 4059 IFQ_DEQUEUE_NOLOCK(ifq, m); 4060 while (m != NULL) { 4061 iflib_if_transmit(ifp, m); 4062 IFQ_DEQUEUE_NOLOCK(ifq, m); 4063 } 4064 IFQ_UNLOCK(ifq); 4065 } 4066 4067 static int 4068 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4069 { 4070 int err; 4071 4072 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4073 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4074 if (err == 0) 4075 iflib_altq_if_start(ifp); 4076 } else 4077 err = iflib_if_transmit(ifp, m); 4078 4079 return (err); 4080 } 4081 #endif /* ALTQ */ 4082 4083 static void 4084 iflib_if_qflush(if_t ifp) 4085 { 4086 if_ctx_t ctx = if_getsoftc(ifp); 4087 iflib_txq_t txq = ctx->ifc_txqs; 4088 int i; 4089 4090 STATE_LOCK(ctx); 4091 ctx->ifc_flags |= IFC_QFLUSH; 4092 STATE_UNLOCK(ctx); 4093 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4094 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4095 iflib_txq_check_drain(txq, 0); 4096 STATE_LOCK(ctx); 4097 ctx->ifc_flags &= ~IFC_QFLUSH; 4098 STATE_UNLOCK(ctx); 4099 4100 /* 4101 * When ALTQ is enabled, this will also take care of purging the 4102 * ALTQ queue(s). 4103 */ 4104 if_qflush(ifp); 4105 } 4106 4107 4108 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4109 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4110 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4111 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP) 4112 4113 static int 4114 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4115 { 4116 if_ctx_t ctx = if_getsoftc(ifp); 4117 struct ifreq *ifr = (struct ifreq *)data; 4118 #if defined(INET) || defined(INET6) 4119 struct ifaddr *ifa = (struct ifaddr *)data; 4120 #endif 4121 bool avoid_reset = false; 4122 int err = 0, reinit = 0, bits; 4123 4124 switch (command) { 4125 case SIOCSIFADDR: 4126 #ifdef INET 4127 if (ifa->ifa_addr->sa_family == AF_INET) 4128 avoid_reset = true; 4129 #endif 4130 #ifdef INET6 4131 if (ifa->ifa_addr->sa_family == AF_INET6) 4132 avoid_reset = true; 4133 #endif 4134 /* 4135 ** Calling init results in link renegotiation, 4136 ** so we avoid doing it when possible. 4137 */ 4138 if (avoid_reset) { 4139 if_setflagbits(ifp, IFF_UP,0); 4140 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4141 reinit = 1; 4142 #ifdef INET 4143 if (!(if_getflags(ifp) & IFF_NOARP)) 4144 arp_ifinit(ifp, ifa); 4145 #endif 4146 } else 4147 err = ether_ioctl(ifp, command, data); 4148 break; 4149 case SIOCSIFMTU: 4150 CTX_LOCK(ctx); 4151 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4152 CTX_UNLOCK(ctx); 4153 break; 4154 } 4155 bits = if_getdrvflags(ifp); 4156 /* stop the driver and free any clusters before proceeding */ 4157 iflib_stop(ctx); 4158 4159 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4160 STATE_LOCK(ctx); 4161 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4162 ctx->ifc_flags |= IFC_MULTISEG; 4163 else 4164 ctx->ifc_flags &= ~IFC_MULTISEG; 4165 STATE_UNLOCK(ctx); 4166 err = if_setmtu(ifp, ifr->ifr_mtu); 4167 } 4168 iflib_init_locked(ctx); 4169 STATE_LOCK(ctx); 4170 if_setdrvflags(ifp, bits); 4171 STATE_UNLOCK(ctx); 4172 CTX_UNLOCK(ctx); 4173 break; 4174 case SIOCSIFFLAGS: 4175 CTX_LOCK(ctx); 4176 if (if_getflags(ifp) & IFF_UP) { 4177 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4178 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4179 (IFF_PROMISC | IFF_ALLMULTI)) { 4180 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4181 } 4182 } else 4183 reinit = 1; 4184 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4185 iflib_stop(ctx); 4186 } 4187 ctx->ifc_if_flags = if_getflags(ifp); 4188 CTX_UNLOCK(ctx); 4189 break; 4190 case SIOCADDMULTI: 4191 case SIOCDELMULTI: 4192 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4193 CTX_LOCK(ctx); 4194 IFDI_INTR_DISABLE(ctx); 4195 IFDI_MULTI_SET(ctx); 4196 IFDI_INTR_ENABLE(ctx); 4197 CTX_UNLOCK(ctx); 4198 } 4199 break; 4200 case SIOCSIFMEDIA: 4201 CTX_LOCK(ctx); 4202 IFDI_MEDIA_SET(ctx); 4203 CTX_UNLOCK(ctx); 4204 /* FALLTHROUGH */ 4205 case SIOCGIFMEDIA: 4206 case SIOCGIFXMEDIA: 4207 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4208 break; 4209 case SIOCGI2C: 4210 { 4211 struct ifi2creq i2c; 4212 4213 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4214 if (err != 0) 4215 break; 4216 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4217 err = EINVAL; 4218 break; 4219 } 4220 if (i2c.len > sizeof(i2c.data)) { 4221 err = EINVAL; 4222 break; 4223 } 4224 4225 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4226 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4227 sizeof(i2c)); 4228 break; 4229 } 4230 case SIOCSIFCAP: 4231 { 4232 int mask, setmask, oldmask; 4233 4234 oldmask = if_getcapenable(ifp); 4235 mask = ifr->ifr_reqcap ^ oldmask; 4236 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP; 4237 setmask = 0; 4238 #ifdef TCP_OFFLOAD 4239 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4240 #endif 4241 setmask |= (mask & IFCAP_FLAGS); 4242 setmask |= (mask & IFCAP_WOL); 4243 4244 /* 4245 * If any RX csum has changed, change all the ones that 4246 * are supported by the driver. 4247 */ 4248 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4249 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4250 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4251 } 4252 4253 /* 4254 * want to ensure that traffic has stopped before we change any of the flags 4255 */ 4256 if (setmask) { 4257 CTX_LOCK(ctx); 4258 bits = if_getdrvflags(ifp); 4259 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4260 iflib_stop(ctx); 4261 STATE_LOCK(ctx); 4262 if_togglecapenable(ifp, setmask); 4263 STATE_UNLOCK(ctx); 4264 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4265 iflib_init_locked(ctx); 4266 STATE_LOCK(ctx); 4267 if_setdrvflags(ifp, bits); 4268 STATE_UNLOCK(ctx); 4269 CTX_UNLOCK(ctx); 4270 } 4271 if_vlancap(ifp); 4272 break; 4273 } 4274 case SIOCGPRIVATE_0: 4275 case SIOCSDRVSPEC: 4276 case SIOCGDRVSPEC: 4277 CTX_LOCK(ctx); 4278 err = IFDI_PRIV_IOCTL(ctx, command, data); 4279 CTX_UNLOCK(ctx); 4280 break; 4281 default: 4282 err = ether_ioctl(ifp, command, data); 4283 break; 4284 } 4285 if (reinit) 4286 iflib_if_init(ctx); 4287 return (err); 4288 } 4289 4290 static uint64_t 4291 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4292 { 4293 if_ctx_t ctx = if_getsoftc(ifp); 4294 4295 return (IFDI_GET_COUNTER(ctx, cnt)); 4296 } 4297 4298 /********************************************************************* 4299 * 4300 * OTHER FUNCTIONS EXPORTED TO THE STACK 4301 * 4302 **********************************************************************/ 4303 4304 static void 4305 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4306 { 4307 if_ctx_t ctx = if_getsoftc(ifp); 4308 4309 if ((void *)ctx != arg) 4310 return; 4311 4312 if ((vtag == 0) || (vtag > 4095)) 4313 return; 4314 4315 if (iflib_in_detach(ctx)) 4316 return; 4317 4318 CTX_LOCK(ctx); 4319 /* Driver may need all untagged packets to be flushed */ 4320 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4321 iflib_stop(ctx); 4322 IFDI_VLAN_REGISTER(ctx, vtag); 4323 /* Re-init to load the changes, if required */ 4324 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4325 iflib_init_locked(ctx); 4326 CTX_UNLOCK(ctx); 4327 } 4328 4329 static void 4330 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4331 { 4332 if_ctx_t ctx = if_getsoftc(ifp); 4333 4334 if ((void *)ctx != arg) 4335 return; 4336 4337 if ((vtag == 0) || (vtag > 4095)) 4338 return; 4339 4340 CTX_LOCK(ctx); 4341 /* Driver may need all tagged packets to be flushed */ 4342 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4343 iflib_stop(ctx); 4344 IFDI_VLAN_UNREGISTER(ctx, vtag); 4345 /* Re-init to load the changes, if required */ 4346 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4347 iflib_init_locked(ctx); 4348 CTX_UNLOCK(ctx); 4349 } 4350 4351 static void 4352 iflib_led_func(void *arg, int onoff) 4353 { 4354 if_ctx_t ctx = arg; 4355 4356 CTX_LOCK(ctx); 4357 IFDI_LED_FUNC(ctx, onoff); 4358 CTX_UNLOCK(ctx); 4359 } 4360 4361 /********************************************************************* 4362 * 4363 * BUS FUNCTION DEFINITIONS 4364 * 4365 **********************************************************************/ 4366 4367 int 4368 iflib_device_probe(device_t dev) 4369 { 4370 const pci_vendor_info_t *ent; 4371 if_shared_ctx_t sctx; 4372 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4373 uint16_t pci_vendor_id; 4374 4375 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4376 return (ENOTSUP); 4377 4378 pci_vendor_id = pci_get_vendor(dev); 4379 pci_device_id = pci_get_device(dev); 4380 pci_subvendor_id = pci_get_subvendor(dev); 4381 pci_subdevice_id = pci_get_subdevice(dev); 4382 pci_rev_id = pci_get_revid(dev); 4383 if (sctx->isc_parse_devinfo != NULL) 4384 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4385 4386 ent = sctx->isc_vendor_info; 4387 while (ent->pvi_vendor_id != 0) { 4388 if (pci_vendor_id != ent->pvi_vendor_id) { 4389 ent++; 4390 continue; 4391 } 4392 if ((pci_device_id == ent->pvi_device_id) && 4393 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4394 (ent->pvi_subvendor_id == 0)) && 4395 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4396 (ent->pvi_subdevice_id == 0)) && 4397 ((pci_rev_id == ent->pvi_rev_id) || 4398 (ent->pvi_rev_id == 0))) { 4399 4400 device_set_desc_copy(dev, ent->pvi_name); 4401 /* this needs to be changed to zero if the bus probing code 4402 * ever stops re-probing on best match because the sctx 4403 * may have its values over written by register calls 4404 * in subsequent probes 4405 */ 4406 return (BUS_PROBE_DEFAULT); 4407 } 4408 ent++; 4409 } 4410 return (ENXIO); 4411 } 4412 4413 int 4414 iflib_device_probe_vendor(device_t dev) 4415 { 4416 int probe; 4417 4418 probe = iflib_device_probe(dev); 4419 if (probe == BUS_PROBE_DEFAULT) 4420 return (BUS_PROBE_VENDOR); 4421 else 4422 return (probe); 4423 } 4424 4425 static void 4426 iflib_reset_qvalues(if_ctx_t ctx) 4427 { 4428 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4429 if_shared_ctx_t sctx = ctx->ifc_sctx; 4430 device_t dev = ctx->ifc_dev; 4431 int i; 4432 4433 if (ctx->ifc_sysctl_ntxqs != 0) 4434 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4435 if (ctx->ifc_sysctl_nrxqs != 0) 4436 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4437 4438 for (i = 0; i < sctx->isc_ntxqs; i++) { 4439 if (ctx->ifc_sysctl_ntxds[i] != 0) 4440 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4441 else 4442 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4443 } 4444 4445 for (i = 0; i < sctx->isc_nrxqs; i++) { 4446 if (ctx->ifc_sysctl_nrxds[i] != 0) 4447 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4448 else 4449 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4450 } 4451 4452 for (i = 0; i < sctx->isc_nrxqs; i++) { 4453 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4454 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4455 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4456 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4457 } 4458 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4459 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4460 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4461 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4462 } 4463 if (!powerof2(scctx->isc_nrxd[i])) { 4464 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4465 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4466 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4467 } 4468 } 4469 4470 for (i = 0; i < sctx->isc_ntxqs; i++) { 4471 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4472 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4473 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4474 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4475 } 4476 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4477 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4478 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4479 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4480 } 4481 if (!powerof2(scctx->isc_ntxd[i])) { 4482 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4483 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4484 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4485 } 4486 } 4487 } 4488 4489 static void 4490 iflib_add_pfil(if_ctx_t ctx) 4491 { 4492 struct pfil_head *pfil; 4493 struct pfil_head_args pa; 4494 iflib_rxq_t rxq; 4495 int i; 4496 4497 pa.pa_version = PFIL_VERSION; 4498 pa.pa_flags = PFIL_IN; 4499 pa.pa_type = PFIL_TYPE_ETHERNET; 4500 pa.pa_headname = ctx->ifc_ifp->if_xname; 4501 pfil = pfil_head_register(&pa); 4502 4503 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4504 rxq->pfil = pfil; 4505 } 4506 } 4507 4508 static void 4509 iflib_rem_pfil(if_ctx_t ctx) 4510 { 4511 struct pfil_head *pfil; 4512 iflib_rxq_t rxq; 4513 int i; 4514 4515 rxq = ctx->ifc_rxqs; 4516 pfil = rxq->pfil; 4517 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4518 rxq->pfil = NULL; 4519 } 4520 pfil_head_unregister(pfil); 4521 } 4522 4523 static uint16_t 4524 get_ctx_core_offset(if_ctx_t ctx) 4525 { 4526 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4527 struct cpu_offset *op; 4528 uint16_t qc; 4529 uint16_t ret = ctx->ifc_sysctl_core_offset; 4530 4531 if (ret != CORE_OFFSET_UNSPECIFIED) 4532 return (ret); 4533 4534 if (ctx->ifc_sysctl_separate_txrx) 4535 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets; 4536 else 4537 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets); 4538 4539 mtx_lock(&cpu_offset_mtx); 4540 SLIST_FOREACH(op, &cpu_offsets, entries) { 4541 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4542 ret = op->offset; 4543 op->offset += qc; 4544 MPASS(op->refcount < UINT_MAX); 4545 op->refcount++; 4546 break; 4547 } 4548 } 4549 if (ret == CORE_OFFSET_UNSPECIFIED) { 4550 ret = 0; 4551 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4552 M_NOWAIT | M_ZERO); 4553 if (op == NULL) { 4554 device_printf(ctx->ifc_dev, 4555 "allocation for cpu offset failed.\n"); 4556 } else { 4557 op->offset = qc; 4558 op->refcount = 1; 4559 CPU_COPY(&ctx->ifc_cpus, &op->set); 4560 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4561 } 4562 } 4563 mtx_unlock(&cpu_offset_mtx); 4564 4565 return (ret); 4566 } 4567 4568 static void 4569 unref_ctx_core_offset(if_ctx_t ctx) 4570 { 4571 struct cpu_offset *op, *top; 4572 4573 mtx_lock(&cpu_offset_mtx); 4574 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4575 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4576 MPASS(op->refcount > 0); 4577 op->refcount--; 4578 if (op->refcount == 0) { 4579 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4580 free(op, M_IFLIB); 4581 } 4582 break; 4583 } 4584 } 4585 mtx_unlock(&cpu_offset_mtx); 4586 } 4587 4588 int 4589 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4590 { 4591 if_ctx_t ctx; 4592 if_t ifp; 4593 if_softc_ctx_t scctx; 4594 kobjop_desc_t kobj_desc; 4595 kobj_method_t *kobj_method; 4596 int err, msix, rid; 4597 uint16_t main_rxq, main_txq; 4598 4599 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4600 4601 if (sc == NULL) { 4602 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4603 device_set_softc(dev, ctx); 4604 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4605 } 4606 4607 ctx->ifc_sctx = sctx; 4608 ctx->ifc_dev = dev; 4609 ctx->ifc_softc = sc; 4610 4611 if ((err = iflib_register(ctx)) != 0) { 4612 device_printf(dev, "iflib_register failed %d\n", err); 4613 goto fail_ctx_free; 4614 } 4615 iflib_add_device_sysctl_pre(ctx); 4616 4617 scctx = &ctx->ifc_softc_ctx; 4618 ifp = ctx->ifc_ifp; 4619 4620 iflib_reset_qvalues(ctx); 4621 CTX_LOCK(ctx); 4622 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4623 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4624 goto fail_unlock; 4625 } 4626 _iflib_pre_assert(scctx); 4627 ctx->ifc_txrx = *scctx->isc_txrx; 4628 4629 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 4630 ctx->ifc_mediap = scctx->isc_media; 4631 4632 #ifdef INVARIANTS 4633 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4634 MPASS(scctx->isc_tx_csum_flags); 4635 #endif 4636 4637 if_setcapabilities(ifp, 4638 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP); 4639 if_setcapenable(ifp, 4640 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP); 4641 4642 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4643 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4644 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4645 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4646 4647 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4648 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4649 4650 /* XXX change for per-queue sizes */ 4651 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4652 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4653 4654 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4655 MAX_SINGLE_PACKET_FRACTION) 4656 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4657 MAX_SINGLE_PACKET_FRACTION); 4658 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4659 MAX_SINGLE_PACKET_FRACTION) 4660 scctx->isc_tx_tso_segments_max = max(1, 4661 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4662 4663 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4664 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4665 /* 4666 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4667 * but some MACs do. 4668 */ 4669 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4670 IP_MAXPACKET)); 4671 /* 4672 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4673 * into account. In the worst case, each of these calls will 4674 * add another mbuf and, thus, the requirement for another DMA 4675 * segment. So for best performance, it doesn't make sense to 4676 * advertize a maximum of TSO segments that typically will 4677 * require defragmentation in iflib_encap(). 4678 */ 4679 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4680 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4681 } 4682 if (scctx->isc_rss_table_size == 0) 4683 scctx->isc_rss_table_size = 64; 4684 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4685 4686 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4687 /* XXX format name */ 4688 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4689 NULL, NULL, "admin"); 4690 4691 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4692 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4693 device_printf(dev, "Unable to fetch CPU list\n"); 4694 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4695 } 4696 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4697 4698 /* 4699 ** Now set up MSI or MSI-X, should return us the number of supported 4700 ** vectors (will be 1 for a legacy interrupt and MSI). 4701 */ 4702 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4703 msix = scctx->isc_vectors; 4704 } else if (scctx->isc_msix_bar != 0) 4705 /* 4706 * The simple fact that isc_msix_bar is not 0 does not mean we 4707 * we have a good value there that is known to work. 4708 */ 4709 msix = iflib_msix_init(ctx); 4710 else { 4711 scctx->isc_vectors = 1; 4712 scctx->isc_ntxqsets = 1; 4713 scctx->isc_nrxqsets = 1; 4714 scctx->isc_intr = IFLIB_INTR_LEGACY; 4715 msix = 0; 4716 } 4717 /* Get memory for the station queues */ 4718 if ((err = iflib_queues_alloc(ctx))) { 4719 device_printf(dev, "Unable to allocate queue memory\n"); 4720 goto fail_intr_free; 4721 } 4722 4723 if ((err = iflib_qset_structures_setup(ctx))) 4724 goto fail_queues; 4725 4726 /* 4727 * Now that we know how many queues there are, get the core offset. 4728 */ 4729 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 4730 4731 if (msix > 1) { 4732 /* 4733 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 4734 * aren't the default NULL implementation. 4735 */ 4736 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 4737 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4738 kobj_desc); 4739 if (kobj_method == &kobj_desc->deflt) { 4740 device_printf(dev, 4741 "MSI-X requires ifdi_rx_queue_intr_enable method"); 4742 err = EOPNOTSUPP; 4743 goto fail_queues; 4744 } 4745 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 4746 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4747 kobj_desc); 4748 if (kobj_method == &kobj_desc->deflt) { 4749 device_printf(dev, 4750 "MSI-X requires ifdi_tx_queue_intr_enable method"); 4751 err = EOPNOTSUPP; 4752 goto fail_queues; 4753 } 4754 4755 /* 4756 * Assign the MSI-X vectors. 4757 * Note that the default NULL ifdi_msix_intr_assign method will 4758 * fail here, too. 4759 */ 4760 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 4761 if (err != 0) { 4762 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 4763 err); 4764 goto fail_queues; 4765 } 4766 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 4767 rid = 0; 4768 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4769 MPASS(msix == 1); 4770 rid = 1; 4771 } 4772 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4773 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4774 goto fail_queues; 4775 } 4776 } else { 4777 device_printf(dev, 4778 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 4779 err = ENODEV; 4780 goto fail_intr_free; 4781 } 4782 4783 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4784 4785 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4786 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4787 goto fail_detach; 4788 } 4789 4790 /* 4791 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4792 * This must appear after the call to ether_ifattach() because 4793 * ether_ifattach() sets if_hdrlen to the default value. 4794 */ 4795 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4796 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4797 4798 if ((err = iflib_netmap_attach(ctx))) { 4799 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4800 goto fail_detach; 4801 } 4802 *ctxp = ctx; 4803 4804 DEBUGNET_SET(ctx->ifc_ifp, iflib); 4805 4806 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4807 iflib_add_device_sysctl_post(ctx); 4808 iflib_add_pfil(ctx); 4809 ctx->ifc_flags |= IFC_INIT_DONE; 4810 CTX_UNLOCK(ctx); 4811 4812 return (0); 4813 4814 fail_detach: 4815 ether_ifdetach(ctx->ifc_ifp); 4816 fail_intr_free: 4817 iflib_free_intr_mem(ctx); 4818 fail_queues: 4819 iflib_tx_structures_free(ctx); 4820 iflib_rx_structures_free(ctx); 4821 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task); 4822 IFDI_DETACH(ctx); 4823 fail_unlock: 4824 CTX_UNLOCK(ctx); 4825 iflib_deregister(ctx); 4826 fail_ctx_free: 4827 device_set_softc(ctx->ifc_dev, NULL); 4828 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4829 free(ctx->ifc_softc, M_IFLIB); 4830 free(ctx, M_IFLIB); 4831 return (err); 4832 } 4833 4834 int 4835 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4836 struct iflib_cloneattach_ctx *clctx) 4837 { 4838 int err; 4839 if_ctx_t ctx; 4840 if_t ifp; 4841 if_softc_ctx_t scctx; 4842 int i; 4843 void *sc; 4844 uint16_t main_txq; 4845 uint16_t main_rxq; 4846 4847 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4848 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4849 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4850 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4851 ctx->ifc_flags |= IFC_PSEUDO; 4852 4853 ctx->ifc_sctx = sctx; 4854 ctx->ifc_softc = sc; 4855 ctx->ifc_dev = dev; 4856 4857 if ((err = iflib_register(ctx)) != 0) { 4858 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4859 goto fail_ctx_free; 4860 } 4861 iflib_add_device_sysctl_pre(ctx); 4862 4863 scctx = &ctx->ifc_softc_ctx; 4864 ifp = ctx->ifc_ifp; 4865 4866 iflib_reset_qvalues(ctx); 4867 CTX_LOCK(ctx); 4868 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4869 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4870 goto fail_unlock; 4871 } 4872 if (sctx->isc_flags & IFLIB_GEN_MAC) 4873 ether_gen_addr(ifp, &ctx->ifc_mac); 4874 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4875 clctx->cc_params)) != 0) { 4876 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4877 goto fail_ctx_free; 4878 } 4879 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4880 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4881 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4882 4883 #ifdef INVARIANTS 4884 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4885 MPASS(scctx->isc_tx_csum_flags); 4886 #endif 4887 4888 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4889 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4890 4891 ifp->if_flags |= IFF_NOGROUP; 4892 if (sctx->isc_flags & IFLIB_PSEUDO) { 4893 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4894 4895 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4896 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4897 goto fail_detach; 4898 } 4899 *ctxp = ctx; 4900 4901 /* 4902 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4903 * This must appear after the call to ether_ifattach() because 4904 * ether_ifattach() sets if_hdrlen to the default value. 4905 */ 4906 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4907 if_setifheaderlen(ifp, 4908 sizeof(struct ether_vlan_header)); 4909 4910 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4911 iflib_add_device_sysctl_post(ctx); 4912 ctx->ifc_flags |= IFC_INIT_DONE; 4913 CTX_UNLOCK(ctx); 4914 return (0); 4915 } 4916 _iflib_pre_assert(scctx); 4917 ctx->ifc_txrx = *scctx->isc_txrx; 4918 4919 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4920 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4921 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4922 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4923 4924 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4925 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4926 4927 /* XXX change for per-queue sizes */ 4928 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4929 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4930 4931 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4932 MAX_SINGLE_PACKET_FRACTION) 4933 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4934 MAX_SINGLE_PACKET_FRACTION); 4935 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4936 MAX_SINGLE_PACKET_FRACTION) 4937 scctx->isc_tx_tso_segments_max = max(1, 4938 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4939 4940 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4941 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4942 /* 4943 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4944 * but some MACs do. 4945 */ 4946 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4947 IP_MAXPACKET)); 4948 /* 4949 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4950 * into account. In the worst case, each of these calls will 4951 * add another mbuf and, thus, the requirement for another DMA 4952 * segment. So for best performance, it doesn't make sense to 4953 * advertize a maximum of TSO segments that typically will 4954 * require defragmentation in iflib_encap(). 4955 */ 4956 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4957 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4958 } 4959 if (scctx->isc_rss_table_size == 0) 4960 scctx->isc_rss_table_size = 64; 4961 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4962 4963 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4964 /* XXX format name */ 4965 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4966 NULL, NULL, "admin"); 4967 4968 /* XXX --- can support > 1 -- but keep it simple for now */ 4969 scctx->isc_intr = IFLIB_INTR_LEGACY; 4970 4971 /* Get memory for the station queues */ 4972 if ((err = iflib_queues_alloc(ctx))) { 4973 device_printf(dev, "Unable to allocate queue memory\n"); 4974 goto fail_iflib_detach; 4975 } 4976 4977 if ((err = iflib_qset_structures_setup(ctx))) { 4978 device_printf(dev, "qset structure setup failed %d\n", err); 4979 goto fail_queues; 4980 } 4981 4982 /* 4983 * XXX What if anything do we want to do about interrupts? 4984 */ 4985 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4986 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4987 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4988 goto fail_detach; 4989 } 4990 4991 /* 4992 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4993 * This must appear after the call to ether_ifattach() because 4994 * ether_ifattach() sets if_hdrlen to the default value. 4995 */ 4996 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4997 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4998 4999 /* XXX handle more than one queue */ 5000 for (i = 0; i < scctx->isc_nrxqsets; i++) 5001 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 5002 5003 *ctxp = ctx; 5004 5005 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5006 iflib_add_device_sysctl_post(ctx); 5007 ctx->ifc_flags |= IFC_INIT_DONE; 5008 CTX_UNLOCK(ctx); 5009 5010 return (0); 5011 fail_detach: 5012 ether_ifdetach(ctx->ifc_ifp); 5013 fail_queues: 5014 iflib_tx_structures_free(ctx); 5015 iflib_rx_structures_free(ctx); 5016 fail_iflib_detach: 5017 IFDI_DETACH(ctx); 5018 fail_unlock: 5019 CTX_UNLOCK(ctx); 5020 iflib_deregister(ctx); 5021 fail_ctx_free: 5022 free(ctx->ifc_softc, M_IFLIB); 5023 free(ctx, M_IFLIB); 5024 return (err); 5025 } 5026 5027 int 5028 iflib_pseudo_deregister(if_ctx_t ctx) 5029 { 5030 if_t ifp = ctx->ifc_ifp; 5031 iflib_txq_t txq; 5032 iflib_rxq_t rxq; 5033 int i, j; 5034 struct taskqgroup *tqg; 5035 iflib_fl_t fl; 5036 5037 /* Unregister VLAN event handlers early */ 5038 iflib_unregister_vlan_handlers(ctx); 5039 5040 ether_ifdetach(ifp); 5041 /* XXX drain any dependent tasks */ 5042 tqg = qgroup_if_io_tqg; 5043 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5044 callout_drain(&txq->ift_timer); 5045 if (txq->ift_task.gt_uniq != NULL) 5046 taskqgroup_detach(tqg, &txq->ift_task); 5047 } 5048 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5049 callout_drain(&rxq->ifr_watchdog); 5050 if (rxq->ifr_task.gt_uniq != NULL) 5051 taskqgroup_detach(tqg, &rxq->ifr_task); 5052 5053 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5054 free(fl->ifl_rx_bitmap, M_IFLIB); 5055 } 5056 tqg = qgroup_if_config_tqg; 5057 if (ctx->ifc_admin_task.gt_uniq != NULL) 5058 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5059 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5060 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5061 5062 iflib_tx_structures_free(ctx); 5063 iflib_rx_structures_free(ctx); 5064 5065 iflib_deregister(ctx); 5066 5067 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5068 free(ctx->ifc_softc, M_IFLIB); 5069 free(ctx, M_IFLIB); 5070 return (0); 5071 } 5072 5073 int 5074 iflib_device_attach(device_t dev) 5075 { 5076 if_ctx_t ctx; 5077 if_shared_ctx_t sctx; 5078 5079 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5080 return (ENOTSUP); 5081 5082 pci_enable_busmaster(dev); 5083 5084 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5085 } 5086 5087 int 5088 iflib_device_deregister(if_ctx_t ctx) 5089 { 5090 if_t ifp = ctx->ifc_ifp; 5091 iflib_txq_t txq; 5092 iflib_rxq_t rxq; 5093 device_t dev = ctx->ifc_dev; 5094 int i, j; 5095 struct taskqgroup *tqg; 5096 iflib_fl_t fl; 5097 5098 /* Make sure VLANS are not using driver */ 5099 if (if_vlantrunkinuse(ifp)) { 5100 device_printf(dev, "Vlan in use, detach first\n"); 5101 return (EBUSY); 5102 } 5103 #ifdef PCI_IOV 5104 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5105 device_printf(dev, "SR-IOV in use; detach first.\n"); 5106 return (EBUSY); 5107 } 5108 #endif 5109 5110 STATE_LOCK(ctx); 5111 ctx->ifc_flags |= IFC_IN_DETACH; 5112 STATE_UNLOCK(ctx); 5113 5114 /* Unregister VLAN handlers before calling iflib_stop() */ 5115 iflib_unregister_vlan_handlers(ctx); 5116 5117 iflib_netmap_detach(ifp); 5118 ether_ifdetach(ifp); 5119 5120 CTX_LOCK(ctx); 5121 iflib_stop(ctx); 5122 CTX_UNLOCK(ctx); 5123 5124 iflib_rem_pfil(ctx); 5125 if (ctx->ifc_led_dev != NULL) 5126 led_destroy(ctx->ifc_led_dev); 5127 /* XXX drain any dependent tasks */ 5128 tqg = qgroup_if_io_tqg; 5129 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5130 callout_drain(&txq->ift_timer); 5131 if (txq->ift_task.gt_uniq != NULL) 5132 taskqgroup_detach(tqg, &txq->ift_task); 5133 } 5134 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5135 if (rxq->ifr_task.gt_uniq != NULL) 5136 taskqgroup_detach(tqg, &rxq->ifr_task); 5137 5138 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5139 free(fl->ifl_rx_bitmap, M_IFLIB); 5140 } 5141 tqg = qgroup_if_config_tqg; 5142 if (ctx->ifc_admin_task.gt_uniq != NULL) 5143 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5144 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5145 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5146 CTX_LOCK(ctx); 5147 IFDI_DETACH(ctx); 5148 CTX_UNLOCK(ctx); 5149 5150 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5151 iflib_free_intr_mem(ctx); 5152 5153 bus_generic_detach(dev); 5154 5155 iflib_tx_structures_free(ctx); 5156 iflib_rx_structures_free(ctx); 5157 5158 iflib_deregister(ctx); 5159 5160 device_set_softc(ctx->ifc_dev, NULL); 5161 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5162 free(ctx->ifc_softc, M_IFLIB); 5163 unref_ctx_core_offset(ctx); 5164 free(ctx, M_IFLIB); 5165 return (0); 5166 } 5167 5168 static void 5169 iflib_free_intr_mem(if_ctx_t ctx) 5170 { 5171 5172 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5173 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5174 } 5175 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5176 pci_release_msi(ctx->ifc_dev); 5177 } 5178 if (ctx->ifc_msix_mem != NULL) { 5179 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5180 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5181 ctx->ifc_msix_mem = NULL; 5182 } 5183 } 5184 5185 int 5186 iflib_device_detach(device_t dev) 5187 { 5188 if_ctx_t ctx = device_get_softc(dev); 5189 5190 return (iflib_device_deregister(ctx)); 5191 } 5192 5193 int 5194 iflib_device_suspend(device_t dev) 5195 { 5196 if_ctx_t ctx = device_get_softc(dev); 5197 5198 CTX_LOCK(ctx); 5199 IFDI_SUSPEND(ctx); 5200 CTX_UNLOCK(ctx); 5201 5202 return bus_generic_suspend(dev); 5203 } 5204 int 5205 iflib_device_shutdown(device_t dev) 5206 { 5207 if_ctx_t ctx = device_get_softc(dev); 5208 5209 CTX_LOCK(ctx); 5210 IFDI_SHUTDOWN(ctx); 5211 CTX_UNLOCK(ctx); 5212 5213 return bus_generic_suspend(dev); 5214 } 5215 5216 5217 int 5218 iflib_device_resume(device_t dev) 5219 { 5220 if_ctx_t ctx = device_get_softc(dev); 5221 iflib_txq_t txq = ctx->ifc_txqs; 5222 5223 CTX_LOCK(ctx); 5224 IFDI_RESUME(ctx); 5225 iflib_if_init_locked(ctx); 5226 CTX_UNLOCK(ctx); 5227 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5228 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5229 5230 return (bus_generic_resume(dev)); 5231 } 5232 5233 int 5234 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5235 { 5236 int error; 5237 if_ctx_t ctx = device_get_softc(dev); 5238 5239 CTX_LOCK(ctx); 5240 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5241 CTX_UNLOCK(ctx); 5242 5243 return (error); 5244 } 5245 5246 void 5247 iflib_device_iov_uninit(device_t dev) 5248 { 5249 if_ctx_t ctx = device_get_softc(dev); 5250 5251 CTX_LOCK(ctx); 5252 IFDI_IOV_UNINIT(ctx); 5253 CTX_UNLOCK(ctx); 5254 } 5255 5256 int 5257 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5258 { 5259 int error; 5260 if_ctx_t ctx = device_get_softc(dev); 5261 5262 CTX_LOCK(ctx); 5263 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5264 CTX_UNLOCK(ctx); 5265 5266 return (error); 5267 } 5268 5269 /********************************************************************* 5270 * 5271 * MODULE FUNCTION DEFINITIONS 5272 * 5273 **********************************************************************/ 5274 5275 /* 5276 * - Start a fast taskqueue thread for each core 5277 * - Start a taskqueue for control operations 5278 */ 5279 static int 5280 iflib_module_init(void) 5281 { 5282 return (0); 5283 } 5284 5285 static int 5286 iflib_module_event_handler(module_t mod, int what, void *arg) 5287 { 5288 int err; 5289 5290 switch (what) { 5291 case MOD_LOAD: 5292 if ((err = iflib_module_init()) != 0) 5293 return (err); 5294 break; 5295 case MOD_UNLOAD: 5296 return (EBUSY); 5297 default: 5298 return (EOPNOTSUPP); 5299 } 5300 5301 return (0); 5302 } 5303 5304 /********************************************************************* 5305 * 5306 * PUBLIC FUNCTION DEFINITIONS 5307 * ordered as in iflib.h 5308 * 5309 **********************************************************************/ 5310 5311 5312 static void 5313 _iflib_assert(if_shared_ctx_t sctx) 5314 { 5315 int i; 5316 5317 MPASS(sctx->isc_tx_maxsize); 5318 MPASS(sctx->isc_tx_maxsegsize); 5319 5320 MPASS(sctx->isc_rx_maxsize); 5321 MPASS(sctx->isc_rx_nsegments); 5322 MPASS(sctx->isc_rx_maxsegsize); 5323 5324 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5325 for (i = 0; i < sctx->isc_nrxqs; i++) { 5326 MPASS(sctx->isc_nrxd_min[i]); 5327 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5328 MPASS(sctx->isc_nrxd_max[i]); 5329 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5330 MPASS(sctx->isc_nrxd_default[i]); 5331 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5332 } 5333 5334 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5335 for (i = 0; i < sctx->isc_ntxqs; i++) { 5336 MPASS(sctx->isc_ntxd_min[i]); 5337 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5338 MPASS(sctx->isc_ntxd_max[i]); 5339 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5340 MPASS(sctx->isc_ntxd_default[i]); 5341 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5342 } 5343 } 5344 5345 static void 5346 _iflib_pre_assert(if_softc_ctx_t scctx) 5347 { 5348 5349 MPASS(scctx->isc_txrx->ift_txd_encap); 5350 MPASS(scctx->isc_txrx->ift_txd_flush); 5351 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5352 MPASS(scctx->isc_txrx->ift_rxd_available); 5353 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5354 MPASS(scctx->isc_txrx->ift_rxd_refill); 5355 MPASS(scctx->isc_txrx->ift_rxd_flush); 5356 } 5357 5358 static int 5359 iflib_register(if_ctx_t ctx) 5360 { 5361 if_shared_ctx_t sctx = ctx->ifc_sctx; 5362 driver_t *driver = sctx->isc_driver; 5363 device_t dev = ctx->ifc_dev; 5364 if_t ifp; 5365 5366 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0) 5367 _iflib_assert(sctx); 5368 5369 CTX_LOCK_INIT(ctx); 5370 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5371 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5372 if (ifp == NULL) { 5373 device_printf(dev, "can not allocate ifnet structure\n"); 5374 return (ENOMEM); 5375 } 5376 5377 /* 5378 * Initialize our context's device specific methods 5379 */ 5380 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5381 kobj_class_compile((kobj_class_t) driver); 5382 5383 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5384 if_setsoftc(ifp, ctx); 5385 if_setdev(ifp, dev); 5386 if_setinitfn(ifp, iflib_if_init); 5387 if_setioctlfn(ifp, iflib_if_ioctl); 5388 #ifdef ALTQ 5389 if_setstartfn(ifp, iflib_altq_if_start); 5390 if_settransmitfn(ifp, iflib_altq_if_transmit); 5391 if_setsendqready(ifp); 5392 #else 5393 if_settransmitfn(ifp, iflib_if_transmit); 5394 #endif 5395 if_setqflushfn(ifp, iflib_if_qflush); 5396 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 5397 IFF_KNOWSEPOCH); 5398 5399 ctx->ifc_vlan_attach_event = 5400 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5401 EVENTHANDLER_PRI_FIRST); 5402 ctx->ifc_vlan_detach_event = 5403 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5404 EVENTHANDLER_PRI_FIRST); 5405 5406 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5407 ctx->ifc_mediap = &ctx->ifc_media; 5408 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5409 iflib_media_change, iflib_media_status); 5410 } 5411 return (0); 5412 } 5413 5414 static void 5415 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5416 { 5417 /* Unregister VLAN events */ 5418 if (ctx->ifc_vlan_attach_event != NULL) { 5419 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5420 ctx->ifc_vlan_attach_event = NULL; 5421 } 5422 if (ctx->ifc_vlan_detach_event != NULL) { 5423 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5424 ctx->ifc_vlan_detach_event = NULL; 5425 } 5426 5427 } 5428 5429 static void 5430 iflib_deregister(if_ctx_t ctx) 5431 { 5432 if_t ifp = ctx->ifc_ifp; 5433 5434 /* Remove all media */ 5435 ifmedia_removeall(&ctx->ifc_media); 5436 5437 /* Ensure that VLAN event handlers are unregistered */ 5438 iflib_unregister_vlan_handlers(ctx); 5439 5440 /* Release kobject reference */ 5441 kobj_delete((kobj_t) ctx, NULL); 5442 5443 /* Free the ifnet structure */ 5444 if_free(ifp); 5445 5446 STATE_LOCK_DESTROY(ctx); 5447 5448 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5449 CTX_LOCK_DESTROY(ctx); 5450 } 5451 5452 static int 5453 iflib_queues_alloc(if_ctx_t ctx) 5454 { 5455 if_shared_ctx_t sctx = ctx->ifc_sctx; 5456 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5457 device_t dev = ctx->ifc_dev; 5458 int nrxqsets = scctx->isc_nrxqsets; 5459 int ntxqsets = scctx->isc_ntxqsets; 5460 iflib_txq_t txq; 5461 iflib_rxq_t rxq; 5462 iflib_fl_t fl = NULL; 5463 int i, j, cpu, err, txconf, rxconf; 5464 iflib_dma_info_t ifdip; 5465 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5466 uint32_t *txqsizes = scctx->isc_txqsizes; 5467 uint8_t nrxqs = sctx->isc_nrxqs; 5468 uint8_t ntxqs = sctx->isc_ntxqs; 5469 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5470 caddr_t *vaddrs; 5471 uint64_t *paddrs; 5472 5473 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5474 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5475 5476 /* Allocate the TX ring struct memory */ 5477 if (!(ctx->ifc_txqs = 5478 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5479 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5480 device_printf(dev, "Unable to allocate TX ring memory\n"); 5481 err = ENOMEM; 5482 goto fail; 5483 } 5484 5485 /* Now allocate the RX */ 5486 if (!(ctx->ifc_rxqs = 5487 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5488 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5489 device_printf(dev, "Unable to allocate RX ring memory\n"); 5490 err = ENOMEM; 5491 goto rx_fail; 5492 } 5493 5494 txq = ctx->ifc_txqs; 5495 rxq = ctx->ifc_rxqs; 5496 5497 /* 5498 * XXX handle allocation failure 5499 */ 5500 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5501 /* Set up some basics */ 5502 5503 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5504 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5505 device_printf(dev, 5506 "Unable to allocate TX DMA info memory\n"); 5507 err = ENOMEM; 5508 goto err_tx_desc; 5509 } 5510 txq->ift_ifdi = ifdip; 5511 for (j = 0; j < ntxqs; j++, ifdip++) { 5512 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5513 device_printf(dev, 5514 "Unable to allocate TX descriptors\n"); 5515 err = ENOMEM; 5516 goto err_tx_desc; 5517 } 5518 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5519 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5520 } 5521 txq->ift_ctx = ctx; 5522 txq->ift_id = i; 5523 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5524 txq->ift_br_offset = 1; 5525 } else { 5526 txq->ift_br_offset = 0; 5527 } 5528 /* XXX fix this */ 5529 txq->ift_timer.c_cpu = cpu; 5530 5531 if (iflib_txsd_alloc(txq)) { 5532 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5533 err = ENOMEM; 5534 goto err_tx_desc; 5535 } 5536 5537 /* Initialize the TX lock */ 5538 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5539 device_get_nameunit(dev), txq->ift_id); 5540 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5541 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5542 5543 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5544 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5545 if (err) { 5546 /* XXX free any allocated rings */ 5547 device_printf(dev, "Unable to allocate buf_ring\n"); 5548 goto err_tx_desc; 5549 } 5550 } 5551 5552 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5553 /* Set up some basics */ 5554 callout_init(&rxq->ifr_watchdog, 1); 5555 5556 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5557 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5558 device_printf(dev, 5559 "Unable to allocate RX DMA info memory\n"); 5560 err = ENOMEM; 5561 goto err_tx_desc; 5562 } 5563 5564 rxq->ifr_ifdi = ifdip; 5565 /* XXX this needs to be changed if #rx queues != #tx queues */ 5566 rxq->ifr_ntxqirq = 1; 5567 rxq->ifr_txqid[0] = i; 5568 for (j = 0; j < nrxqs; j++, ifdip++) { 5569 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5570 device_printf(dev, 5571 "Unable to allocate RX descriptors\n"); 5572 err = ENOMEM; 5573 goto err_tx_desc; 5574 } 5575 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5576 } 5577 rxq->ifr_ctx = ctx; 5578 rxq->ifr_id = i; 5579 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5580 rxq->ifr_fl_offset = 1; 5581 } else { 5582 rxq->ifr_fl_offset = 0; 5583 } 5584 rxq->ifr_nfl = nfree_lists; 5585 if (!(fl = 5586 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5587 device_printf(dev, "Unable to allocate free list memory\n"); 5588 err = ENOMEM; 5589 goto err_tx_desc; 5590 } 5591 rxq->ifr_fl = fl; 5592 for (j = 0; j < nfree_lists; j++) { 5593 fl[j].ifl_rxq = rxq; 5594 fl[j].ifl_id = j; 5595 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5596 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5597 } 5598 /* Allocate receive buffers for the ring */ 5599 if (iflib_rxsd_alloc(rxq)) { 5600 device_printf(dev, 5601 "Critical Failure setting up receive buffers\n"); 5602 err = ENOMEM; 5603 goto err_rx_desc; 5604 } 5605 5606 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5607 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5608 M_WAITOK); 5609 } 5610 5611 /* TXQs */ 5612 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5613 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5614 for (i = 0; i < ntxqsets; i++) { 5615 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5616 5617 for (j = 0; j < ntxqs; j++, di++) { 5618 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5619 paddrs[i*ntxqs + j] = di->idi_paddr; 5620 } 5621 } 5622 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5623 device_printf(ctx->ifc_dev, 5624 "Unable to allocate device TX queue\n"); 5625 iflib_tx_structures_free(ctx); 5626 free(vaddrs, M_IFLIB); 5627 free(paddrs, M_IFLIB); 5628 goto err_rx_desc; 5629 } 5630 free(vaddrs, M_IFLIB); 5631 free(paddrs, M_IFLIB); 5632 5633 /* RXQs */ 5634 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5635 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5636 for (i = 0; i < nrxqsets; i++) { 5637 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5638 5639 for (j = 0; j < nrxqs; j++, di++) { 5640 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5641 paddrs[i*nrxqs + j] = di->idi_paddr; 5642 } 5643 } 5644 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5645 device_printf(ctx->ifc_dev, 5646 "Unable to allocate device RX queue\n"); 5647 iflib_tx_structures_free(ctx); 5648 free(vaddrs, M_IFLIB); 5649 free(paddrs, M_IFLIB); 5650 goto err_rx_desc; 5651 } 5652 free(vaddrs, M_IFLIB); 5653 free(paddrs, M_IFLIB); 5654 5655 return (0); 5656 5657 /* XXX handle allocation failure changes */ 5658 err_rx_desc: 5659 err_tx_desc: 5660 rx_fail: 5661 if (ctx->ifc_rxqs != NULL) 5662 free(ctx->ifc_rxqs, M_IFLIB); 5663 ctx->ifc_rxqs = NULL; 5664 if (ctx->ifc_txqs != NULL) 5665 free(ctx->ifc_txqs, M_IFLIB); 5666 ctx->ifc_txqs = NULL; 5667 fail: 5668 return (err); 5669 } 5670 5671 static int 5672 iflib_tx_structures_setup(if_ctx_t ctx) 5673 { 5674 iflib_txq_t txq = ctx->ifc_txqs; 5675 int i; 5676 5677 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5678 iflib_txq_setup(txq); 5679 5680 return (0); 5681 } 5682 5683 static void 5684 iflib_tx_structures_free(if_ctx_t ctx) 5685 { 5686 iflib_txq_t txq = ctx->ifc_txqs; 5687 if_shared_ctx_t sctx = ctx->ifc_sctx; 5688 int i, j; 5689 5690 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5691 for (j = 0; j < sctx->isc_ntxqs; j++) 5692 iflib_dma_free(&txq->ift_ifdi[j]); 5693 iflib_txq_destroy(txq); 5694 } 5695 free(ctx->ifc_txqs, M_IFLIB); 5696 ctx->ifc_txqs = NULL; 5697 IFDI_QUEUES_FREE(ctx); 5698 } 5699 5700 /********************************************************************* 5701 * 5702 * Initialize all receive rings. 5703 * 5704 **********************************************************************/ 5705 static int 5706 iflib_rx_structures_setup(if_ctx_t ctx) 5707 { 5708 iflib_rxq_t rxq = ctx->ifc_rxqs; 5709 int q; 5710 #if defined(INET6) || defined(INET) 5711 int err, i; 5712 #endif 5713 5714 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5715 #if defined(INET6) || defined(INET) 5716 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) { 5717 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5718 TCP_LRO_ENTRIES, min(1024, 5719 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 5720 if (err != 0) { 5721 device_printf(ctx->ifc_dev, 5722 "LRO Initialization failed!\n"); 5723 goto fail; 5724 } 5725 } 5726 #endif 5727 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5728 } 5729 return (0); 5730 #if defined(INET6) || defined(INET) 5731 fail: 5732 /* 5733 * Free LRO resources allocated so far, we will only handle 5734 * the rings that completed, the failing case will have 5735 * cleaned up for itself. 'q' failed, so its the terminus. 5736 */ 5737 rxq = ctx->ifc_rxqs; 5738 for (i = 0; i < q; ++i, rxq++) { 5739 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5740 tcp_lro_free(&rxq->ifr_lc); 5741 } 5742 return (err); 5743 #endif 5744 } 5745 5746 /********************************************************************* 5747 * 5748 * Free all receive rings. 5749 * 5750 **********************************************************************/ 5751 static void 5752 iflib_rx_structures_free(if_ctx_t ctx) 5753 { 5754 iflib_rxq_t rxq = ctx->ifc_rxqs; 5755 if_shared_ctx_t sctx = ctx->ifc_sctx; 5756 int i, j; 5757 5758 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5759 for (j = 0; j < sctx->isc_nrxqs; j++) 5760 iflib_dma_free(&rxq->ifr_ifdi[j]); 5761 iflib_rx_sds_free(rxq); 5762 #if defined(INET6) || defined(INET) 5763 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5764 tcp_lro_free(&rxq->ifr_lc); 5765 #endif 5766 } 5767 free(ctx->ifc_rxqs, M_IFLIB); 5768 ctx->ifc_rxqs = NULL; 5769 } 5770 5771 static int 5772 iflib_qset_structures_setup(if_ctx_t ctx) 5773 { 5774 int err; 5775 5776 /* 5777 * It is expected that the caller takes care of freeing queues if this 5778 * fails. 5779 */ 5780 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5781 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5782 return (err); 5783 } 5784 5785 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5786 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5787 5788 return (err); 5789 } 5790 5791 int 5792 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5793 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5794 { 5795 5796 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5797 } 5798 5799 #ifdef SMP 5800 static int 5801 find_nth(if_ctx_t ctx, int qid) 5802 { 5803 cpuset_t cpus; 5804 int i, cpuid, eqid, count; 5805 5806 CPU_COPY(&ctx->ifc_cpus, &cpus); 5807 count = CPU_COUNT(&cpus); 5808 eqid = qid % count; 5809 /* clear up to the qid'th bit */ 5810 for (i = 0; i < eqid; i++) { 5811 cpuid = CPU_FFS(&cpus); 5812 MPASS(cpuid != 0); 5813 CPU_CLR(cpuid-1, &cpus); 5814 } 5815 cpuid = CPU_FFS(&cpus); 5816 MPASS(cpuid != 0); 5817 return (cpuid-1); 5818 } 5819 5820 #ifdef SCHED_ULE 5821 extern struct cpu_group *cpu_top; /* CPU topology */ 5822 5823 static int 5824 find_child_with_core(int cpu, struct cpu_group *grp) 5825 { 5826 int i; 5827 5828 if (grp->cg_children == 0) 5829 return -1; 5830 5831 MPASS(grp->cg_child); 5832 for (i = 0; i < grp->cg_children; i++) { 5833 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5834 return i; 5835 } 5836 5837 return -1; 5838 } 5839 5840 /* 5841 * Find the nth "close" core to the specified core 5842 * "close" is defined as the deepest level that shares 5843 * at least an L2 cache. With threads, this will be 5844 * threads on the same core. If the shared cache is L3 5845 * or higher, simply returns the same core. 5846 */ 5847 static int 5848 find_close_core(int cpu, int core_offset) 5849 { 5850 struct cpu_group *grp; 5851 int i; 5852 int fcpu; 5853 cpuset_t cs; 5854 5855 grp = cpu_top; 5856 if (grp == NULL) 5857 return cpu; 5858 i = 0; 5859 while ((i = find_child_with_core(cpu, grp)) != -1) { 5860 /* If the child only has one cpu, don't descend */ 5861 if (grp->cg_child[i].cg_count <= 1) 5862 break; 5863 grp = &grp->cg_child[i]; 5864 } 5865 5866 /* If they don't share at least an L2 cache, use the same CPU */ 5867 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5868 return cpu; 5869 5870 /* Now pick one */ 5871 CPU_COPY(&grp->cg_mask, &cs); 5872 5873 /* Add the selected CPU offset to core offset. */ 5874 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5875 if (fcpu - 1 == cpu) 5876 break; 5877 CPU_CLR(fcpu - 1, &cs); 5878 } 5879 MPASS(fcpu); 5880 5881 core_offset += i; 5882 5883 CPU_COPY(&grp->cg_mask, &cs); 5884 for (i = core_offset % grp->cg_count; i > 0; i--) { 5885 MPASS(CPU_FFS(&cs)); 5886 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5887 } 5888 MPASS(CPU_FFS(&cs)); 5889 return CPU_FFS(&cs) - 1; 5890 } 5891 #else 5892 static int 5893 find_close_core(int cpu, int core_offset __unused) 5894 { 5895 return cpu; 5896 } 5897 #endif 5898 5899 static int 5900 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5901 { 5902 switch (type) { 5903 case IFLIB_INTR_TX: 5904 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5905 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5906 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5907 case IFLIB_INTR_RX: 5908 case IFLIB_INTR_RXTX: 5909 /* RX queues get the specified core */ 5910 return qid / CPU_COUNT(&ctx->ifc_cpus); 5911 default: 5912 return -1; 5913 } 5914 } 5915 #else 5916 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5917 #define find_close_core(cpuid, tid) CPU_FIRST() 5918 #define find_nth(ctx, gid) CPU_FIRST() 5919 #endif 5920 5921 /* Just to avoid copy/paste */ 5922 static inline int 5923 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5924 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5925 const char *name) 5926 { 5927 device_t dev; 5928 int co, cpuid, err, tid; 5929 5930 dev = ctx->ifc_dev; 5931 co = ctx->ifc_sysctl_core_offset; 5932 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX) 5933 co += ctx->ifc_softc_ctx.isc_nrxqsets; 5934 cpuid = find_nth(ctx, qid + co); 5935 tid = get_core_offset(ctx, type, qid); 5936 if (tid < 0) { 5937 device_printf(dev, "get_core_offset failed\n"); 5938 return (EOPNOTSUPP); 5939 } 5940 cpuid = find_close_core(cpuid, tid); 5941 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 5942 name); 5943 if (err) { 5944 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 5945 return (err); 5946 } 5947 #ifdef notyet 5948 if (cpuid > ctx->ifc_cpuid_highest) 5949 ctx->ifc_cpuid_highest = cpuid; 5950 #endif 5951 return (0); 5952 } 5953 5954 int 5955 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5956 iflib_intr_type_t type, driver_filter_t *filter, 5957 void *filter_arg, int qid, const char *name) 5958 { 5959 device_t dev; 5960 struct grouptask *gtask; 5961 struct taskqgroup *tqg; 5962 iflib_filter_info_t info; 5963 gtask_fn_t *fn; 5964 int tqrid, err; 5965 driver_filter_t *intr_fast; 5966 void *q; 5967 5968 info = &ctx->ifc_filter_info; 5969 tqrid = rid; 5970 5971 switch (type) { 5972 /* XXX merge tx/rx for netmap? */ 5973 case IFLIB_INTR_TX: 5974 q = &ctx->ifc_txqs[qid]; 5975 info = &ctx->ifc_txqs[qid].ift_filter_info; 5976 gtask = &ctx->ifc_txqs[qid].ift_task; 5977 tqg = qgroup_if_io_tqg; 5978 fn = _task_fn_tx; 5979 intr_fast = iflib_fast_intr; 5980 GROUPTASK_INIT(gtask, 0, fn, q); 5981 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5982 break; 5983 case IFLIB_INTR_RX: 5984 q = &ctx->ifc_rxqs[qid]; 5985 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5986 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5987 tqg = qgroup_if_io_tqg; 5988 fn = _task_fn_rx; 5989 intr_fast = iflib_fast_intr; 5990 NET_GROUPTASK_INIT(gtask, 0, fn, q); 5991 break; 5992 case IFLIB_INTR_RXTX: 5993 q = &ctx->ifc_rxqs[qid]; 5994 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5995 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5996 tqg = qgroup_if_io_tqg; 5997 fn = _task_fn_rx; 5998 intr_fast = iflib_fast_intr_rxtx; 5999 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6000 break; 6001 case IFLIB_INTR_ADMIN: 6002 q = ctx; 6003 tqrid = -1; 6004 info = &ctx->ifc_filter_info; 6005 gtask = &ctx->ifc_admin_task; 6006 tqg = qgroup_if_config_tqg; 6007 fn = _task_fn_admin; 6008 intr_fast = iflib_fast_intr_ctx; 6009 break; 6010 default: 6011 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6012 __func__); 6013 return (EINVAL); 6014 } 6015 6016 info->ifi_filter = filter; 6017 info->ifi_filter_arg = filter_arg; 6018 info->ifi_task = gtask; 6019 info->ifi_ctx = q; 6020 6021 dev = ctx->ifc_dev; 6022 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6023 if (err != 0) { 6024 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6025 return (err); 6026 } 6027 if (type == IFLIB_INTR_ADMIN) 6028 return (0); 6029 6030 if (tqrid != -1) { 6031 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6032 q, name); 6033 if (err) 6034 return (err); 6035 } else { 6036 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6037 } 6038 6039 return (0); 6040 } 6041 6042 void 6043 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6044 { 6045 struct grouptask *gtask; 6046 struct taskqgroup *tqg; 6047 gtask_fn_t *fn; 6048 void *q; 6049 int err; 6050 6051 switch (type) { 6052 case IFLIB_INTR_TX: 6053 q = &ctx->ifc_txqs[qid]; 6054 gtask = &ctx->ifc_txqs[qid].ift_task; 6055 tqg = qgroup_if_io_tqg; 6056 fn = _task_fn_tx; 6057 GROUPTASK_INIT(gtask, 0, fn, q); 6058 break; 6059 case IFLIB_INTR_RX: 6060 q = &ctx->ifc_rxqs[qid]; 6061 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6062 tqg = qgroup_if_io_tqg; 6063 fn = _task_fn_rx; 6064 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6065 break; 6066 case IFLIB_INTR_IOV: 6067 q = ctx; 6068 gtask = &ctx->ifc_vflr_task; 6069 tqg = qgroup_if_config_tqg; 6070 fn = _task_fn_iov; 6071 GROUPTASK_INIT(gtask, 0, fn, q); 6072 break; 6073 default: 6074 panic("unknown net intr type"); 6075 } 6076 if (irq != NULL) { 6077 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6078 q, name); 6079 if (err) 6080 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 6081 irq->ii_res, name); 6082 } else { 6083 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 6084 } 6085 } 6086 6087 void 6088 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6089 { 6090 6091 if (irq->ii_tag) 6092 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6093 6094 if (irq->ii_res) 6095 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6096 rman_get_rid(irq->ii_res), irq->ii_res); 6097 } 6098 6099 static int 6100 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6101 { 6102 iflib_txq_t txq = ctx->ifc_txqs; 6103 iflib_rxq_t rxq = ctx->ifc_rxqs; 6104 if_irq_t irq = &ctx->ifc_legacy_irq; 6105 iflib_filter_info_t info; 6106 device_t dev; 6107 struct grouptask *gtask; 6108 struct resource *res; 6109 struct taskqgroup *tqg; 6110 void *q; 6111 int err, tqrid; 6112 bool rx_only; 6113 6114 q = &ctx->ifc_rxqs[0]; 6115 info = &rxq[0].ifr_filter_info; 6116 gtask = &rxq[0].ifr_task; 6117 tqg = qgroup_if_io_tqg; 6118 tqrid = *rid; 6119 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6120 6121 ctx->ifc_flags |= IFC_LEGACY; 6122 info->ifi_filter = filter; 6123 info->ifi_filter_arg = filter_arg; 6124 info->ifi_task = gtask; 6125 info->ifi_ctx = rx_only ? ctx : q; 6126 6127 dev = ctx->ifc_dev; 6128 /* We allocate a single interrupt resource */ 6129 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6130 iflib_fast_intr_rxtx, NULL, info, name); 6131 if (err != 0) 6132 return (err); 6133 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6134 res = irq->ii_res; 6135 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6136 6137 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6138 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6139 "tx"); 6140 return (0); 6141 } 6142 6143 void 6144 iflib_led_create(if_ctx_t ctx) 6145 { 6146 6147 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6148 device_get_nameunit(ctx->ifc_dev)); 6149 } 6150 6151 void 6152 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6153 { 6154 6155 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6156 } 6157 6158 void 6159 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6160 { 6161 6162 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6163 } 6164 6165 void 6166 iflib_admin_intr_deferred(if_ctx_t ctx) 6167 { 6168 6169 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6170 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6171 } 6172 6173 void 6174 iflib_iov_intr_deferred(if_ctx_t ctx) 6175 { 6176 6177 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6178 } 6179 6180 void 6181 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6182 { 6183 6184 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6185 name); 6186 } 6187 6188 void 6189 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6190 const char *name) 6191 { 6192 6193 GROUPTASK_INIT(gtask, 0, fn, ctx); 6194 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6195 name); 6196 } 6197 6198 void 6199 iflib_config_gtask_deinit(struct grouptask *gtask) 6200 { 6201 6202 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6203 } 6204 6205 void 6206 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6207 { 6208 if_t ifp = ctx->ifc_ifp; 6209 iflib_txq_t txq = ctx->ifc_txqs; 6210 6211 if_setbaudrate(ifp, baudrate); 6212 if (baudrate >= IF_Gbps(10)) { 6213 STATE_LOCK(ctx); 6214 ctx->ifc_flags |= IFC_PREFETCH; 6215 STATE_UNLOCK(ctx); 6216 } 6217 /* If link down, disable watchdog */ 6218 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6219 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6220 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6221 } 6222 ctx->ifc_link_state = link_state; 6223 if_link_state_change(ifp, link_state); 6224 } 6225 6226 static int 6227 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6228 { 6229 int credits; 6230 #ifdef INVARIANTS 6231 int credits_pre = txq->ift_cidx_processed; 6232 #endif 6233 6234 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6235 BUS_DMASYNC_POSTREAD); 6236 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6237 return (0); 6238 6239 txq->ift_processed += credits; 6240 txq->ift_cidx_processed += credits; 6241 6242 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6243 if (txq->ift_cidx_processed >= txq->ift_size) 6244 txq->ift_cidx_processed -= txq->ift_size; 6245 return (credits); 6246 } 6247 6248 static int 6249 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6250 { 6251 iflib_fl_t fl; 6252 u_int i; 6253 6254 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6255 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6256 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6257 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6258 budget)); 6259 } 6260 6261 void 6262 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6263 const char *description, if_int_delay_info_t info, 6264 int offset, int value) 6265 { 6266 info->iidi_ctx = ctx; 6267 info->iidi_offset = offset; 6268 info->iidi_value = value; 6269 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6270 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6271 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6272 info, 0, iflib_sysctl_int_delay, "I", description); 6273 } 6274 6275 struct sx * 6276 iflib_ctx_lock_get(if_ctx_t ctx) 6277 { 6278 6279 return (&ctx->ifc_ctx_sx); 6280 } 6281 6282 static int 6283 iflib_msix_init(if_ctx_t ctx) 6284 { 6285 device_t dev = ctx->ifc_dev; 6286 if_shared_ctx_t sctx = ctx->ifc_sctx; 6287 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6288 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6289 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6290 6291 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6292 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6293 6294 if (bootverbose) 6295 device_printf(dev, "msix_init qsets capped at %d\n", 6296 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6297 6298 /* Override by tuneable */ 6299 if (scctx->isc_disable_msix) 6300 goto msi; 6301 6302 /* First try MSI-X */ 6303 if ((msgs = pci_msix_count(dev)) == 0) { 6304 if (bootverbose) 6305 device_printf(dev, "MSI-X not supported or disabled\n"); 6306 goto msi; 6307 } 6308 6309 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6310 /* 6311 * bar == -1 => "trust me I know what I'm doing" 6312 * Some drivers are for hardware that is so shoddily 6313 * documented that no one knows which bars are which 6314 * so the developer has to map all bars. This hack 6315 * allows shoddy garbage to use MSI-X in this framework. 6316 */ 6317 if (bar != -1) { 6318 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6319 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6320 if (ctx->ifc_msix_mem == NULL) { 6321 device_printf(dev, "Unable to map MSI-X table\n"); 6322 goto msi; 6323 } 6324 } 6325 6326 admincnt = sctx->isc_admin_intrcnt; 6327 #if IFLIB_DEBUG 6328 /* use only 1 qset in debug mode */ 6329 queuemsgs = min(msgs - admincnt, 1); 6330 #else 6331 queuemsgs = msgs - admincnt; 6332 #endif 6333 #ifdef RSS 6334 queues = imin(queuemsgs, rss_getnumbuckets()); 6335 #else 6336 queues = queuemsgs; 6337 #endif 6338 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6339 if (bootverbose) 6340 device_printf(dev, 6341 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6342 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6343 #ifdef RSS 6344 /* If we're doing RSS, clamp at the number of RSS buckets */ 6345 if (queues > rss_getnumbuckets()) 6346 queues = rss_getnumbuckets(); 6347 #endif 6348 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6349 rx_queues = iflib_num_rx_queues; 6350 else 6351 rx_queues = queues; 6352 6353 if (rx_queues > scctx->isc_nrxqsets) 6354 rx_queues = scctx->isc_nrxqsets; 6355 6356 /* 6357 * We want this to be all logical CPUs by default 6358 */ 6359 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6360 tx_queues = iflib_num_tx_queues; 6361 else 6362 tx_queues = mp_ncpus; 6363 6364 if (tx_queues > scctx->isc_ntxqsets) 6365 tx_queues = scctx->isc_ntxqsets; 6366 6367 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6368 #ifdef INVARIANTS 6369 if (tx_queues != rx_queues) 6370 device_printf(dev, 6371 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6372 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6373 #endif 6374 tx_queues = min(rx_queues, tx_queues); 6375 rx_queues = min(rx_queues, tx_queues); 6376 } 6377 6378 vectors = rx_queues + admincnt; 6379 if (msgs < vectors) { 6380 device_printf(dev, 6381 "insufficient number of MSI-X vectors " 6382 "(supported %d, need %d)\n", msgs, vectors); 6383 goto msi; 6384 } 6385 6386 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6387 tx_queues); 6388 msgs = vectors; 6389 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6390 if (vectors != msgs) { 6391 device_printf(dev, 6392 "Unable to allocate sufficient MSI-X vectors " 6393 "(got %d, need %d)\n", vectors, msgs); 6394 pci_release_msi(dev); 6395 if (bar != -1) { 6396 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6397 ctx->ifc_msix_mem); 6398 ctx->ifc_msix_mem = NULL; 6399 } 6400 goto msi; 6401 } 6402 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6403 vectors); 6404 scctx->isc_vectors = vectors; 6405 scctx->isc_nrxqsets = rx_queues; 6406 scctx->isc_ntxqsets = tx_queues; 6407 scctx->isc_intr = IFLIB_INTR_MSIX; 6408 6409 return (vectors); 6410 } else { 6411 device_printf(dev, 6412 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6413 err); 6414 if (bar != -1) { 6415 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6416 ctx->ifc_msix_mem); 6417 ctx->ifc_msix_mem = NULL; 6418 } 6419 } 6420 6421 msi: 6422 vectors = pci_msi_count(dev); 6423 scctx->isc_nrxqsets = 1; 6424 scctx->isc_ntxqsets = 1; 6425 scctx->isc_vectors = vectors; 6426 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6427 device_printf(dev,"Using an MSI interrupt\n"); 6428 scctx->isc_intr = IFLIB_INTR_MSI; 6429 } else { 6430 scctx->isc_vectors = 1; 6431 device_printf(dev,"Using a Legacy interrupt\n"); 6432 scctx->isc_intr = IFLIB_INTR_LEGACY; 6433 } 6434 6435 return (vectors); 6436 } 6437 6438 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6439 6440 static int 6441 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6442 { 6443 int rc; 6444 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6445 struct sbuf *sb; 6446 const char *ring_state = "UNKNOWN"; 6447 6448 /* XXX needed ? */ 6449 rc = sysctl_wire_old_buffer(req, 0); 6450 MPASS(rc == 0); 6451 if (rc != 0) 6452 return (rc); 6453 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6454 MPASS(sb != NULL); 6455 if (sb == NULL) 6456 return (ENOMEM); 6457 if (state[3] <= 3) 6458 ring_state = ring_states[state[3]]; 6459 6460 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6461 state[0], state[1], state[2], ring_state); 6462 rc = sbuf_finish(sb); 6463 sbuf_delete(sb); 6464 return(rc); 6465 } 6466 6467 enum iflib_ndesc_handler { 6468 IFLIB_NTXD_HANDLER, 6469 IFLIB_NRXD_HANDLER, 6470 }; 6471 6472 static int 6473 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6474 { 6475 if_ctx_t ctx = (void *)arg1; 6476 enum iflib_ndesc_handler type = arg2; 6477 char buf[256] = {0}; 6478 qidx_t *ndesc; 6479 char *p, *next; 6480 int nqs, rc, i; 6481 6482 nqs = 8; 6483 switch(type) { 6484 case IFLIB_NTXD_HANDLER: 6485 ndesc = ctx->ifc_sysctl_ntxds; 6486 if (ctx->ifc_sctx) 6487 nqs = ctx->ifc_sctx->isc_ntxqs; 6488 break; 6489 case IFLIB_NRXD_HANDLER: 6490 ndesc = ctx->ifc_sysctl_nrxds; 6491 if (ctx->ifc_sctx) 6492 nqs = ctx->ifc_sctx->isc_nrxqs; 6493 break; 6494 default: 6495 printf("%s: unhandled type\n", __func__); 6496 return (EINVAL); 6497 } 6498 if (nqs == 0) 6499 nqs = 8; 6500 6501 for (i=0; i<8; i++) { 6502 if (i >= nqs) 6503 break; 6504 if (i) 6505 strcat(buf, ","); 6506 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6507 } 6508 6509 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6510 if (rc || req->newptr == NULL) 6511 return rc; 6512 6513 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6514 i++, p = strsep(&next, " ,")) { 6515 ndesc[i] = strtoul(p, NULL, 10); 6516 } 6517 6518 return(rc); 6519 } 6520 6521 #define NAME_BUFLEN 32 6522 static void 6523 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6524 { 6525 device_t dev = iflib_get_dev(ctx); 6526 struct sysctl_oid_list *child, *oid_list; 6527 struct sysctl_ctx_list *ctx_list; 6528 struct sysctl_oid *node; 6529 6530 ctx_list = device_get_sysctl_ctx(dev); 6531 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6532 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6533 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 6534 oid_list = SYSCTL_CHILDREN(node); 6535 6536 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6537 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6538 "driver version"); 6539 6540 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6541 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6542 "# of txqs to use, 0 => use default #"); 6543 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6544 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6545 "# of rxqs to use, 0 => use default #"); 6546 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6547 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6548 "permit #txq != #rxq"); 6549 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6550 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6551 "disable MSI-X (default 0)"); 6552 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6553 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6554 "set the RX budget"); 6555 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6556 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6557 "cause TX to abdicate instead of running to completion"); 6558 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6559 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6560 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6561 "offset to start using cores at"); 6562 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6563 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6564 "use separate cores for TX and RX"); 6565 6566 /* XXX change for per-queue sizes */ 6567 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6568 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6569 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6570 "list of # of TX descriptors to use, 0 = use default #"); 6571 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6572 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6573 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6574 "list of # of RX descriptors to use, 0 = use default #"); 6575 } 6576 6577 static void 6578 iflib_add_device_sysctl_post(if_ctx_t ctx) 6579 { 6580 if_shared_ctx_t sctx = ctx->ifc_sctx; 6581 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6582 device_t dev = iflib_get_dev(ctx); 6583 struct sysctl_oid_list *child; 6584 struct sysctl_ctx_list *ctx_list; 6585 iflib_fl_t fl; 6586 iflib_txq_t txq; 6587 iflib_rxq_t rxq; 6588 int i, j; 6589 char namebuf[NAME_BUFLEN]; 6590 char *qfmt; 6591 struct sysctl_oid *queue_node, *fl_node, *node; 6592 struct sysctl_oid_list *queue_list, *fl_list; 6593 ctx_list = device_get_sysctl_ctx(dev); 6594 6595 node = ctx->ifc_sysctl_node; 6596 child = SYSCTL_CHILDREN(node); 6597 6598 if (scctx->isc_ntxqsets > 100) 6599 qfmt = "txq%03d"; 6600 else if (scctx->isc_ntxqsets > 10) 6601 qfmt = "txq%02d"; 6602 else 6603 qfmt = "txq%d"; 6604 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6605 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6606 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6607 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6608 queue_list = SYSCTL_CHILDREN(queue_node); 6609 #if MEMORY_LOGGING 6610 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6611 CTLFLAG_RD, 6612 &txq->ift_dequeued, "total mbufs freed"); 6613 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6614 CTLFLAG_RD, 6615 &txq->ift_enqueued, "total mbufs enqueued"); 6616 #endif 6617 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6618 CTLFLAG_RD, 6619 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6620 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6621 CTLFLAG_RD, 6622 &txq->ift_pullups, "# of times m_pullup was called"); 6623 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6624 CTLFLAG_RD, 6625 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6626 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6627 CTLFLAG_RD, 6628 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6629 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6630 CTLFLAG_RD, 6631 &txq->ift_map_failed, "# of times DMA map failed"); 6632 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6633 CTLFLAG_RD, 6634 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6635 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6636 CTLFLAG_RD, 6637 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6638 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6639 CTLFLAG_RD, 6640 &txq->ift_pidx, 1, "Producer Index"); 6641 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6642 CTLFLAG_RD, 6643 &txq->ift_cidx, 1, "Consumer Index"); 6644 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6645 CTLFLAG_RD, 6646 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6647 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6648 CTLFLAG_RD, 6649 &txq->ift_in_use, 1, "descriptors in use"); 6650 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6651 CTLFLAG_RD, 6652 &txq->ift_processed, "descriptors procesed for clean"); 6653 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6654 CTLFLAG_RD, 6655 &txq->ift_cleaned, "total cleaned"); 6656 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6657 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6658 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6659 mp_ring_state_handler, "A", "soft ring state"); 6660 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6661 CTLFLAG_RD, &txq->ift_br->enqueues, 6662 "# of enqueues to the mp_ring for this queue"); 6663 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6664 CTLFLAG_RD, &txq->ift_br->drops, 6665 "# of drops in the mp_ring for this queue"); 6666 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6667 CTLFLAG_RD, &txq->ift_br->starts, 6668 "# of normal consumer starts in the mp_ring for this queue"); 6669 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6670 CTLFLAG_RD, &txq->ift_br->stalls, 6671 "# of consumer stalls in the mp_ring for this queue"); 6672 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6673 CTLFLAG_RD, &txq->ift_br->restarts, 6674 "# of consumer restarts in the mp_ring for this queue"); 6675 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6676 CTLFLAG_RD, &txq->ift_br->abdications, 6677 "# of consumer abdications in the mp_ring for this queue"); 6678 } 6679 6680 if (scctx->isc_nrxqsets > 100) 6681 qfmt = "rxq%03d"; 6682 else if (scctx->isc_nrxqsets > 10) 6683 qfmt = "rxq%02d"; 6684 else 6685 qfmt = "rxq%d"; 6686 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6687 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6688 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6689 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6690 queue_list = SYSCTL_CHILDREN(queue_node); 6691 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6692 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6693 CTLFLAG_RD, 6694 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6695 } 6696 6697 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6698 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6699 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6700 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 6701 fl_list = SYSCTL_CHILDREN(fl_node); 6702 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6703 CTLFLAG_RD, 6704 &fl->ifl_pidx, 1, "Producer Index"); 6705 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6706 CTLFLAG_RD, 6707 &fl->ifl_cidx, 1, "Consumer Index"); 6708 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6709 CTLFLAG_RD, 6710 &fl->ifl_credits, 1, "credits available"); 6711 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 6712 CTLFLAG_RD, 6713 &fl->ifl_buf_size, 1, "buffer size"); 6714 #if MEMORY_LOGGING 6715 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6716 CTLFLAG_RD, 6717 &fl->ifl_m_enqueued, "mbufs allocated"); 6718 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6719 CTLFLAG_RD, 6720 &fl->ifl_m_dequeued, "mbufs freed"); 6721 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6722 CTLFLAG_RD, 6723 &fl->ifl_cl_enqueued, "clusters allocated"); 6724 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6725 CTLFLAG_RD, 6726 &fl->ifl_cl_dequeued, "clusters freed"); 6727 #endif 6728 6729 } 6730 } 6731 6732 } 6733 6734 void 6735 iflib_request_reset(if_ctx_t ctx) 6736 { 6737 6738 STATE_LOCK(ctx); 6739 ctx->ifc_flags |= IFC_DO_RESET; 6740 STATE_UNLOCK(ctx); 6741 } 6742 6743 #ifndef __NO_STRICT_ALIGNMENT 6744 static struct mbuf * 6745 iflib_fixup_rx(struct mbuf *m) 6746 { 6747 struct mbuf *n; 6748 6749 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6750 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6751 m->m_data += ETHER_HDR_LEN; 6752 n = m; 6753 } else { 6754 MGETHDR(n, M_NOWAIT, MT_DATA); 6755 if (n == NULL) { 6756 m_freem(m); 6757 return (NULL); 6758 } 6759 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6760 m->m_data += ETHER_HDR_LEN; 6761 m->m_len -= ETHER_HDR_LEN; 6762 n->m_len = ETHER_HDR_LEN; 6763 M_MOVE_PKTHDR(n, m); 6764 n->m_next = m; 6765 } 6766 return (n); 6767 } 6768 #endif 6769 6770 #ifdef DEBUGNET 6771 static void 6772 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6773 { 6774 if_ctx_t ctx; 6775 6776 ctx = if_getsoftc(ifp); 6777 CTX_LOCK(ctx); 6778 *nrxr = NRXQSETS(ctx); 6779 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6780 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6781 CTX_UNLOCK(ctx); 6782 } 6783 6784 static void 6785 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 6786 { 6787 if_ctx_t ctx; 6788 if_softc_ctx_t scctx; 6789 iflib_fl_t fl; 6790 iflib_rxq_t rxq; 6791 int i, j; 6792 6793 ctx = if_getsoftc(ifp); 6794 scctx = &ctx->ifc_softc_ctx; 6795 6796 switch (event) { 6797 case DEBUGNET_START: 6798 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6799 rxq = &ctx->ifc_rxqs[i]; 6800 for (j = 0; j < rxq->ifr_nfl; j++) { 6801 fl = rxq->ifr_fl; 6802 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6803 } 6804 } 6805 iflib_no_tx_batch = 1; 6806 break; 6807 default: 6808 break; 6809 } 6810 } 6811 6812 static int 6813 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 6814 { 6815 if_ctx_t ctx; 6816 iflib_txq_t txq; 6817 int error; 6818 6819 ctx = if_getsoftc(ifp); 6820 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6821 IFF_DRV_RUNNING) 6822 return (EBUSY); 6823 6824 txq = &ctx->ifc_txqs[0]; 6825 error = iflib_encap(txq, &m); 6826 if (error == 0) 6827 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6828 return (error); 6829 } 6830 6831 static int 6832 iflib_debugnet_poll(if_t ifp, int count) 6833 { 6834 struct epoch_tracker et; 6835 if_ctx_t ctx; 6836 if_softc_ctx_t scctx; 6837 iflib_txq_t txq; 6838 int i; 6839 6840 ctx = if_getsoftc(ifp); 6841 scctx = &ctx->ifc_softc_ctx; 6842 6843 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6844 IFF_DRV_RUNNING) 6845 return (EBUSY); 6846 6847 txq = &ctx->ifc_txqs[0]; 6848 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6849 6850 NET_EPOCH_ENTER(et); 6851 for (i = 0; i < scctx->isc_nrxqsets; i++) 6852 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6853 NET_EPOCH_EXIT(et); 6854 return (0); 6855 } 6856 #endif /* DEBUGNET */ 6857