1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/jail.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/md5.h> 44 #include <sys/mutex.h> 45 #include <sys/module.h> 46 #include <sys/kobj.h> 47 #include <sys/rman.h> 48 #include <sys/proc.h> 49 #include <sys/sbuf.h> 50 #include <sys/smp.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/syslog.h> 55 #include <sys/taskqueue.h> 56 #include <sys/limits.h> 57 58 #include <net/if.h> 59 #include <net/if_var.h> 60 #include <net/if_types.h> 61 #include <net/if_media.h> 62 #include <net/bpf.h> 63 #include <net/ethernet.h> 64 #include <net/mp_ring.h> 65 #include <net/vnet.h> 66 67 #include <netinet/in.h> 68 #include <netinet/in_pcb.h> 69 #include <netinet/tcp_lro.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/if_ether.h> 72 #include <netinet/ip.h> 73 #include <netinet/ip6.h> 74 #include <netinet/tcp.h> 75 #include <netinet/ip_var.h> 76 #include <netinet/netdump/netdump.h> 77 #include <netinet6/ip6_var.h> 78 79 #include <machine/bus.h> 80 #include <machine/in_cksum.h> 81 82 #include <vm/vm.h> 83 #include <vm/pmap.h> 84 85 #include <dev/led/led.h> 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pci_private.h> 89 90 #include <net/iflib.h> 91 #include <net/iflib_private.h> 92 93 #include "ifdi_if.h" 94 95 #ifdef PCI_IOV 96 #include <dev/pci/pci_iov.h> 97 #endif 98 99 #include <sys/bitstring.h> 100 /* 101 * enable accounting of every mbuf as it comes in to and goes out of 102 * iflib's software descriptor references 103 */ 104 #define MEMORY_LOGGING 0 105 /* 106 * Enable mbuf vectors for compressing long mbuf chains 107 */ 108 109 /* 110 * NB: 111 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 112 * we prefetch needs to be determined by the time spent in m_free vis a vis 113 * the cost of a prefetch. This will of course vary based on the workload: 114 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 115 * is quite expensive, thus suggesting very little prefetch. 116 * - small packet forwarding which is just returning a single mbuf to 117 * UMA will typically be very fast vis a vis the cost of a memory 118 * access. 119 */ 120 121 122 /* 123 * File organization: 124 * - private structures 125 * - iflib private utility functions 126 * - ifnet functions 127 * - vlan registry and other exported functions 128 * - iflib public core functions 129 * 130 * 131 */ 132 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 146 typedef struct iflib_filter_info { 147 driver_filter_t *ifi_filter; 148 void *ifi_filter_arg; 149 struct grouptask *ifi_task; 150 void *ifi_ctx; 151 } *iflib_filter_info_t; 152 153 struct iflib_ctx { 154 KOBJ_FIELDS; 155 /* 156 * Pointer to hardware driver's softc 157 */ 158 void *ifc_softc; 159 device_t ifc_dev; 160 if_t ifc_ifp; 161 162 cpuset_t ifc_cpus; 163 if_shared_ctx_t ifc_sctx; 164 struct if_softc_ctx ifc_softc_ctx; 165 166 struct sx ifc_ctx_sx; 167 struct mtx ifc_state_mtx; 168 169 iflib_txq_t ifc_txqs; 170 iflib_rxq_t ifc_rxqs; 171 uint32_t ifc_if_flags; 172 uint32_t ifc_flags; 173 uint32_t ifc_max_fl_buf_size; 174 175 int ifc_link_state; 176 int ifc_link_irq; 177 int ifc_watchdog_events; 178 struct cdev *ifc_led_dev; 179 struct resource *ifc_msix_mem; 180 181 struct if_irq ifc_legacy_irq; 182 struct grouptask ifc_admin_task; 183 struct grouptask ifc_vflr_task; 184 struct iflib_filter_info ifc_filter_info; 185 struct ifmedia ifc_media; 186 187 struct sysctl_oid *ifc_sysctl_node; 188 uint16_t ifc_sysctl_ntxqs; 189 uint16_t ifc_sysctl_nrxqs; 190 uint16_t ifc_sysctl_qs_eq_override; 191 uint16_t ifc_sysctl_rx_budget; 192 uint16_t ifc_sysctl_tx_abdicate; 193 194 qidx_t ifc_sysctl_ntxds[8]; 195 qidx_t ifc_sysctl_nrxds[8]; 196 struct if_txrx ifc_txrx; 197 #define isc_txd_encap ifc_txrx.ift_txd_encap 198 #define isc_txd_flush ifc_txrx.ift_txd_flush 199 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 200 #define isc_rxd_available ifc_txrx.ift_rxd_available 201 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 202 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 203 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 205 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 206 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 207 eventhandler_tag ifc_vlan_attach_event; 208 eventhandler_tag ifc_vlan_detach_event; 209 uint8_t ifc_mac[ETHER_ADDR_LEN]; 210 char ifc_mtx_name[16]; 211 }; 212 213 214 void * 215 iflib_get_softc(if_ctx_t ctx) 216 { 217 218 return (ctx->ifc_softc); 219 } 220 221 device_t 222 iflib_get_dev(if_ctx_t ctx) 223 { 224 225 return (ctx->ifc_dev); 226 } 227 228 if_t 229 iflib_get_ifp(if_ctx_t ctx) 230 { 231 232 return (ctx->ifc_ifp); 233 } 234 235 struct ifmedia * 236 iflib_get_media(if_ctx_t ctx) 237 { 238 239 return (&ctx->ifc_media); 240 } 241 242 uint32_t 243 iflib_get_flags(if_ctx_t ctx) 244 { 245 return (ctx->ifc_flags); 246 } 247 248 void 249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 250 { 251 252 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 253 } 254 255 if_softc_ctx_t 256 iflib_get_softc_ctx(if_ctx_t ctx) 257 { 258 259 return (&ctx->ifc_softc_ctx); 260 } 261 262 if_shared_ctx_t 263 iflib_get_sctx(if_ctx_t ctx) 264 { 265 266 return (ctx->ifc_sctx); 267 } 268 269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 272 273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 275 276 typedef struct iflib_sw_rx_desc_array { 277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 278 struct mbuf **ifsd_m; /* pkthdr mbufs */ 279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 281 } iflib_rxsd_array_t; 282 283 typedef struct iflib_sw_tx_desc_array { 284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 285 struct mbuf **ifsd_m; /* pkthdr mbufs */ 286 } if_txsd_vec_t; 287 288 289 /* magic number that should be high enough for any hardware */ 290 #define IFLIB_MAX_TX_SEGS 128 291 /* bnxt supports 64 with hardware LRO enabled */ 292 #define IFLIB_MAX_RX_SEGS 64 293 #define IFLIB_RX_COPY_THRESH 128 294 #define IFLIB_MAX_RX_REFRESH 32 295 /* The minimum descriptors per second before we start coalescing */ 296 #define IFLIB_MIN_DESC_SEC 16384 297 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 298 #define IFLIB_QUEUE_IDLE 0 299 #define IFLIB_QUEUE_HUNG 1 300 #define IFLIB_QUEUE_WORKING 2 301 /* maximum number of txqs that can share an rx interrupt */ 302 #define IFLIB_MAX_TX_SHARED_INTR 4 303 304 /* this should really scale with ring size - this is a fairly arbitrary value */ 305 #define TX_BATCH_SIZE 32 306 307 #define IFLIB_RESTART_BUDGET 8 308 309 310 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 311 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 312 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 313 struct iflib_txq { 314 qidx_t ift_in_use; 315 qidx_t ift_cidx; 316 qidx_t ift_cidx_processed; 317 qidx_t ift_pidx; 318 uint8_t ift_gen; 319 uint8_t ift_br_offset; 320 uint16_t ift_npending; 321 uint16_t ift_db_pending; 322 uint16_t ift_rs_pending; 323 /* implicit pad */ 324 uint8_t ift_txd_size[8]; 325 uint64_t ift_processed; 326 uint64_t ift_cleaned; 327 uint64_t ift_cleaned_prev; 328 #if MEMORY_LOGGING 329 uint64_t ift_enqueued; 330 uint64_t ift_dequeued; 331 #endif 332 uint64_t ift_no_tx_dma_setup; 333 uint64_t ift_no_desc_avail; 334 uint64_t ift_mbuf_defrag_failed; 335 uint64_t ift_mbuf_defrag; 336 uint64_t ift_map_failed; 337 uint64_t ift_txd_encap_efbig; 338 uint64_t ift_pullups; 339 uint64_t ift_last_timer_tick; 340 341 struct mtx ift_mtx; 342 struct mtx ift_db_mtx; 343 344 /* constant values */ 345 if_ctx_t ift_ctx; 346 struct ifmp_ring *ift_br; 347 struct grouptask ift_task; 348 qidx_t ift_size; 349 uint16_t ift_id; 350 struct callout ift_timer; 351 352 if_txsd_vec_t ift_sds; 353 uint8_t ift_qstatus; 354 uint8_t ift_closed; 355 uint8_t ift_update_freq; 356 struct iflib_filter_info ift_filter_info; 357 bus_dma_tag_t ift_desc_tag; 358 bus_dma_tag_t ift_tso_desc_tag; 359 iflib_dma_info_t ift_ifdi; 360 #define MTX_NAME_LEN 16 361 char ift_mtx_name[MTX_NAME_LEN]; 362 char ift_db_mtx_name[MTX_NAME_LEN]; 363 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 364 #ifdef IFLIB_DIAGNOSTICS 365 uint64_t ift_cpu_exec_count[256]; 366 #endif 367 } __aligned(CACHE_LINE_SIZE); 368 369 struct iflib_fl { 370 qidx_t ifl_cidx; 371 qidx_t ifl_pidx; 372 qidx_t ifl_credits; 373 uint8_t ifl_gen; 374 uint8_t ifl_rxd_size; 375 #if MEMORY_LOGGING 376 uint64_t ifl_m_enqueued; 377 uint64_t ifl_m_dequeued; 378 uint64_t ifl_cl_enqueued; 379 uint64_t ifl_cl_dequeued; 380 #endif 381 /* implicit pad */ 382 383 bitstr_t *ifl_rx_bitmap; 384 qidx_t ifl_fragidx; 385 /* constant */ 386 qidx_t ifl_size; 387 uint16_t ifl_buf_size; 388 uint16_t ifl_cltype; 389 uma_zone_t ifl_zone; 390 iflib_rxsd_array_t ifl_sds; 391 iflib_rxq_t ifl_rxq; 392 uint8_t ifl_id; 393 bus_dma_tag_t ifl_desc_tag; 394 iflib_dma_info_t ifl_ifdi; 395 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 396 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 397 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 398 } __aligned(CACHE_LINE_SIZE); 399 400 static inline qidx_t 401 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 402 { 403 qidx_t used; 404 405 if (pidx > cidx) 406 used = pidx - cidx; 407 else if (pidx < cidx) 408 used = size - cidx + pidx; 409 else if (gen == 0 && pidx == cidx) 410 used = 0; 411 else if (gen == 1 && pidx == cidx) 412 used = size; 413 else 414 panic("bad state"); 415 416 return (used); 417 } 418 419 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 420 421 #define IDXDIFF(head, tail, wrap) \ 422 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 423 424 struct iflib_rxq { 425 /* If there is a separate completion queue - 426 * these are the cq cidx and pidx. Otherwise 427 * these are unused. 428 */ 429 qidx_t ifr_size; 430 qidx_t ifr_cq_cidx; 431 qidx_t ifr_cq_pidx; 432 uint8_t ifr_cq_gen; 433 uint8_t ifr_fl_offset; 434 435 if_ctx_t ifr_ctx; 436 iflib_fl_t ifr_fl; 437 uint64_t ifr_rx_irq; 438 uint16_t ifr_id; 439 uint8_t ifr_lro_enabled; 440 uint8_t ifr_nfl; 441 uint8_t ifr_ntxqirq; 442 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 443 struct lro_ctrl ifr_lc; 444 struct grouptask ifr_task; 445 struct iflib_filter_info ifr_filter_info; 446 iflib_dma_info_t ifr_ifdi; 447 448 /* dynamically allocate if any drivers need a value substantially larger than this */ 449 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 450 #ifdef IFLIB_DIAGNOSTICS 451 uint64_t ifr_cpu_exec_count[256]; 452 #endif 453 } __aligned(CACHE_LINE_SIZE); 454 455 typedef struct if_rxsd { 456 caddr_t *ifsd_cl; 457 struct mbuf **ifsd_m; 458 iflib_fl_t ifsd_fl; 459 qidx_t ifsd_cidx; 460 } *if_rxsd_t; 461 462 /* multiple of word size */ 463 #ifdef __LP64__ 464 #define PKT_INFO_SIZE 6 465 #define RXD_INFO_SIZE 5 466 #define PKT_TYPE uint64_t 467 #else 468 #define PKT_INFO_SIZE 11 469 #define RXD_INFO_SIZE 8 470 #define PKT_TYPE uint32_t 471 #endif 472 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 473 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 474 475 typedef struct if_pkt_info_pad { 476 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 477 } *if_pkt_info_pad_t; 478 typedef struct if_rxd_info_pad { 479 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 480 } *if_rxd_info_pad_t; 481 482 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 483 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 484 485 486 static inline void 487 pkt_info_zero(if_pkt_info_t pi) 488 { 489 if_pkt_info_pad_t pi_pad; 490 491 pi_pad = (if_pkt_info_pad_t)pi; 492 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 493 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 494 #ifndef __LP64__ 495 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 496 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 497 #endif 498 } 499 500 static device_method_t iflib_pseudo_methods[] = { 501 DEVMETHOD(device_attach, noop_attach), 502 DEVMETHOD(device_detach, iflib_pseudo_detach), 503 DEVMETHOD_END 504 }; 505 506 driver_t iflib_pseudodriver = { 507 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 508 }; 509 510 static inline void 511 rxd_info_zero(if_rxd_info_t ri) 512 { 513 if_rxd_info_pad_t ri_pad; 514 int i; 515 516 ri_pad = (if_rxd_info_pad_t)ri; 517 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 518 ri_pad->rxd_val[i] = 0; 519 ri_pad->rxd_val[i+1] = 0; 520 ri_pad->rxd_val[i+2] = 0; 521 ri_pad->rxd_val[i+3] = 0; 522 } 523 #ifdef __LP64__ 524 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 525 #endif 526 } 527 528 /* 529 * Only allow a single packet to take up most 1/nth of the tx ring 530 */ 531 #define MAX_SINGLE_PACKET_FRACTION 12 532 #define IF_BAD_DMA (bus_addr_t)-1 533 534 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 535 536 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 537 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 538 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 539 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 540 541 542 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 543 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 544 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 545 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 546 547 548 549 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 550 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 551 552 void 553 iflib_set_detach(if_ctx_t ctx) 554 { 555 STATE_LOCK(ctx); 556 ctx->ifc_flags |= IFC_IN_DETACH; 557 STATE_UNLOCK(ctx); 558 } 559 560 /* Our boot-time initialization hook */ 561 static int iflib_module_event_handler(module_t, int, void *); 562 563 static moduledata_t iflib_moduledata = { 564 "iflib", 565 iflib_module_event_handler, 566 NULL 567 }; 568 569 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 570 MODULE_VERSION(iflib, 1); 571 572 MODULE_DEPEND(iflib, pci, 1, 1, 1); 573 MODULE_DEPEND(iflib, ether, 1, 1, 1); 574 575 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 576 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 577 578 #ifndef IFLIB_DEBUG_COUNTERS 579 #ifdef INVARIANTS 580 #define IFLIB_DEBUG_COUNTERS 1 581 #else 582 #define IFLIB_DEBUG_COUNTERS 0 583 #endif /* !INVARIANTS */ 584 #endif 585 586 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 587 "iflib driver parameters"); 588 589 /* 590 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 591 */ 592 static int iflib_min_tx_latency = 0; 593 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 594 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 595 static int iflib_no_tx_batch = 0; 596 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 597 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 598 599 600 #if IFLIB_DEBUG_COUNTERS 601 602 static int iflib_tx_seen; 603 static int iflib_tx_sent; 604 static int iflib_tx_encap; 605 static int iflib_rx_allocs; 606 static int iflib_fl_refills; 607 static int iflib_fl_refills_large; 608 static int iflib_tx_frees; 609 610 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 611 &iflib_tx_seen, 0, "# tx mbufs seen"); 612 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 613 &iflib_tx_sent, 0, "# tx mbufs sent"); 614 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 615 &iflib_tx_encap, 0, "# tx mbufs encapped"); 616 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 617 &iflib_tx_frees, 0, "# tx frees"); 618 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 619 &iflib_rx_allocs, 0, "# rx allocations"); 620 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 621 &iflib_fl_refills, 0, "# refills"); 622 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 623 &iflib_fl_refills_large, 0, "# large refills"); 624 625 626 static int iflib_txq_drain_flushing; 627 static int iflib_txq_drain_oactive; 628 static int iflib_txq_drain_notready; 629 630 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 631 &iflib_txq_drain_flushing, 0, "# drain flushes"); 632 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 633 &iflib_txq_drain_oactive, 0, "# drain oactives"); 634 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 635 &iflib_txq_drain_notready, 0, "# drain notready"); 636 637 638 static int iflib_encap_load_mbuf_fail; 639 static int iflib_encap_pad_mbuf_fail; 640 static int iflib_encap_txq_avail_fail; 641 static int iflib_encap_txd_encap_fail; 642 643 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 644 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 645 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 646 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 647 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 648 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 649 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 650 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 651 652 static int iflib_task_fn_rxs; 653 static int iflib_rx_intr_enables; 654 static int iflib_fast_intrs; 655 static int iflib_rx_unavail; 656 static int iflib_rx_ctx_inactive; 657 static int iflib_rx_if_input; 658 static int iflib_rx_mbuf_null; 659 static int iflib_rxd_flush; 660 661 static int iflib_verbose_debug; 662 663 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 664 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 666 &iflib_rx_intr_enables, 0, "# rx intr enables"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 668 &iflib_fast_intrs, 0, "# fast_intr calls"); 669 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 670 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 671 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 672 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 673 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 674 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 675 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 676 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 677 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 678 &iflib_rxd_flush, 0, "# times rxd_flush called"); 679 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 680 &iflib_verbose_debug, 0, "enable verbose debugging"); 681 682 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 683 static void 684 iflib_debug_reset(void) 685 { 686 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 687 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 688 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 689 iflib_txq_drain_notready = 690 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 691 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 692 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 693 iflib_rx_unavail = 694 iflib_rx_ctx_inactive = iflib_rx_if_input = 695 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 696 } 697 698 #else 699 #define DBG_COUNTER_INC(name) 700 static void iflib_debug_reset(void) {} 701 #endif 702 703 #define IFLIB_DEBUG 0 704 705 static void iflib_tx_structures_free(if_ctx_t ctx); 706 static void iflib_rx_structures_free(if_ctx_t ctx); 707 static int iflib_queues_alloc(if_ctx_t ctx); 708 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 709 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 710 static int iflib_qset_structures_setup(if_ctx_t ctx); 711 static int iflib_msix_init(if_ctx_t ctx); 712 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 713 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 714 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 715 #ifdef ALTQ 716 static void iflib_altq_if_start(if_t ifp); 717 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 718 #endif 719 static int iflib_register(if_ctx_t); 720 static void iflib_init_locked(if_ctx_t ctx); 721 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 722 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 723 static void iflib_ifmp_purge(iflib_txq_t txq); 724 static void _iflib_pre_assert(if_softc_ctx_t scctx); 725 static void iflib_if_init_locked(if_ctx_t ctx); 726 static void iflib_free_intr_mem(if_ctx_t ctx); 727 #ifndef __NO_STRICT_ALIGNMENT 728 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 729 #endif 730 731 NETDUMP_DEFINE(iflib); 732 733 #ifdef DEV_NETMAP 734 #include <sys/selinfo.h> 735 #include <net/netmap.h> 736 #include <dev/netmap/netmap_kern.h> 737 738 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 739 740 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 741 742 /* 743 * device-specific sysctl variables: 744 * 745 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 746 * During regular operations the CRC is stripped, but on some 747 * hardware reception of frames not multiple of 64 is slower, 748 * so using crcstrip=0 helps in benchmarks. 749 * 750 * iflib_rx_miss, iflib_rx_miss_bufs: 751 * count packets that might be missed due to lost interrupts. 752 */ 753 SYSCTL_DECL(_dev_netmap); 754 /* 755 * The xl driver by default strips CRCs and we do not override it. 756 */ 757 758 int iflib_crcstrip = 1; 759 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 760 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 761 762 int iflib_rx_miss, iflib_rx_miss_bufs; 763 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 764 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 765 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 766 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 767 768 /* 769 * Register/unregister. We are already under netmap lock. 770 * Only called on the first register or the last unregister. 771 */ 772 static int 773 iflib_netmap_register(struct netmap_adapter *na, int onoff) 774 { 775 struct ifnet *ifp = na->ifp; 776 if_ctx_t ctx = ifp->if_softc; 777 int status; 778 779 CTX_LOCK(ctx); 780 IFDI_INTR_DISABLE(ctx); 781 782 /* Tell the stack that the interface is no longer active */ 783 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 784 785 if (!CTX_IS_VF(ctx)) 786 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 787 788 /* enable or disable flags and callbacks in na and ifp */ 789 if (onoff) { 790 nm_set_native_flags(na); 791 } else { 792 nm_clear_native_flags(na); 793 } 794 iflib_stop(ctx); 795 iflib_init_locked(ctx); 796 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 797 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 798 if (status) 799 nm_clear_native_flags(na); 800 CTX_UNLOCK(ctx); 801 return (status); 802 } 803 804 static int 805 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 806 { 807 struct netmap_adapter *na = kring->na; 808 u_int const lim = kring->nkr_num_slots - 1; 809 u_int head = kring->rhead; 810 struct netmap_ring *ring = kring->ring; 811 bus_dmamap_t *map; 812 struct if_rxd_update iru; 813 if_ctx_t ctx = rxq->ifr_ctx; 814 iflib_fl_t fl = &rxq->ifr_fl[0]; 815 uint32_t refill_pidx, nic_i; 816 #if IFLIB_DEBUG_COUNTERS 817 int rf_count = 0; 818 #endif 819 820 if (nm_i == head && __predict_true(!init)) 821 return 0; 822 iru_init(&iru, rxq, 0 /* flid */); 823 map = fl->ifl_sds.ifsd_map; 824 refill_pidx = netmap_idx_k2n(kring, nm_i); 825 /* 826 * IMPORTANT: we must leave one free slot in the ring, 827 * so move head back by one unit 828 */ 829 head = nm_prev(head, lim); 830 nic_i = UINT_MAX; 831 DBG_COUNTER_INC(fl_refills); 832 while (nm_i != head) { 833 #if IFLIB_DEBUG_COUNTERS 834 if (++rf_count == 9) 835 DBG_COUNTER_INC(fl_refills_large); 836 #endif 837 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 838 struct netmap_slot *slot = &ring->slot[nm_i]; 839 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 840 uint32_t nic_i_dma = refill_pidx; 841 nic_i = netmap_idx_k2n(kring, nm_i); 842 843 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 844 845 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 846 return netmap_ring_reinit(kring); 847 848 fl->ifl_vm_addrs[tmp_pidx] = addr; 849 if (__predict_false(init) && map) { 850 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 851 } else if (map && (slot->flags & NS_BUF_CHANGED)) { 852 /* buffer has changed, reload map */ 853 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 854 } 855 slot->flags &= ~NS_BUF_CHANGED; 856 857 nm_i = nm_next(nm_i, lim); 858 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 859 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 860 continue; 861 862 iru.iru_pidx = refill_pidx; 863 iru.iru_count = tmp_pidx+1; 864 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 865 866 refill_pidx = nic_i; 867 if (map == NULL) 868 continue; 869 870 for (int n = 0; n < iru.iru_count; n++) { 871 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma], 872 BUS_DMASYNC_PREREAD); 873 /* XXX - change this to not use the netmap func*/ 874 nic_i_dma = nm_next(nic_i_dma, lim); 875 } 876 } 877 } 878 kring->nr_hwcur = head; 879 880 if (map) 881 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 882 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 883 if (__predict_true(nic_i != UINT_MAX)) { 884 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 885 DBG_COUNTER_INC(rxd_flush); 886 } 887 return (0); 888 } 889 890 /* 891 * Reconcile kernel and user view of the transmit ring. 892 * 893 * All information is in the kring. 894 * Userspace wants to send packets up to the one before kring->rhead, 895 * kernel knows kring->nr_hwcur is the first unsent packet. 896 * 897 * Here we push packets out (as many as possible), and possibly 898 * reclaim buffers from previously completed transmission. 899 * 900 * The caller (netmap) guarantees that there is only one instance 901 * running at any time. Any interference with other driver 902 * methods should be handled by the individual drivers. 903 */ 904 static int 905 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 906 { 907 struct netmap_adapter *na = kring->na; 908 struct ifnet *ifp = na->ifp; 909 struct netmap_ring *ring = kring->ring; 910 u_int nm_i; /* index into the netmap kring */ 911 u_int nic_i; /* index into the NIC ring */ 912 u_int n; 913 u_int const lim = kring->nkr_num_slots - 1; 914 u_int const head = kring->rhead; 915 struct if_pkt_info pi; 916 917 /* 918 * interrupts on every tx packet are expensive so request 919 * them every half ring, or where NS_REPORT is set 920 */ 921 u_int report_frequency = kring->nkr_num_slots >> 1; 922 /* device-specific */ 923 if_ctx_t ctx = ifp->if_softc; 924 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 925 926 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 927 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 928 929 930 /* 931 * First part: process new packets to send. 932 * nm_i is the current index in the netmap kring, 933 * nic_i is the corresponding index in the NIC ring. 934 * 935 * If we have packets to send (nm_i != head) 936 * iterate over the netmap ring, fetch length and update 937 * the corresponding slot in the NIC ring. Some drivers also 938 * need to update the buffer's physical address in the NIC slot 939 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 940 * 941 * The netmap_reload_map() calls is especially expensive, 942 * even when (as in this case) the tag is 0, so do only 943 * when the buffer has actually changed. 944 * 945 * If possible do not set the report/intr bit on all slots, 946 * but only a few times per ring or when NS_REPORT is set. 947 * 948 * Finally, on 10G and faster drivers, it might be useful 949 * to prefetch the next slot and txr entry. 950 */ 951 952 nm_i = kring->nr_hwcur; 953 if (nm_i != head) { /* we have new packets to send */ 954 pkt_info_zero(&pi); 955 pi.ipi_segs = txq->ift_segs; 956 pi.ipi_qsidx = kring->ring_id; 957 nic_i = netmap_idx_k2n(kring, nm_i); 958 959 __builtin_prefetch(&ring->slot[nm_i]); 960 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 961 if (txq->ift_sds.ifsd_map) 962 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 963 964 for (n = 0; nm_i != head; n++) { 965 struct netmap_slot *slot = &ring->slot[nm_i]; 966 u_int len = slot->len; 967 uint64_t paddr; 968 void *addr = PNMB(na, slot, &paddr); 969 int flags = (slot->flags & NS_REPORT || 970 nic_i == 0 || nic_i == report_frequency) ? 971 IPI_TX_INTR : 0; 972 973 /* device-specific */ 974 pi.ipi_len = len; 975 pi.ipi_segs[0].ds_addr = paddr; 976 pi.ipi_segs[0].ds_len = len; 977 pi.ipi_nsegs = 1; 978 pi.ipi_ndescs = 0; 979 pi.ipi_pidx = nic_i; 980 pi.ipi_flags = flags; 981 982 /* Fill the slot in the NIC ring. */ 983 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 984 DBG_COUNTER_INC(tx_encap); 985 986 /* prefetch for next round */ 987 __builtin_prefetch(&ring->slot[nm_i + 1]); 988 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 989 if (txq->ift_sds.ifsd_map) { 990 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 991 992 NM_CHECK_ADDR_LEN(na, addr, len); 993 994 if (slot->flags & NS_BUF_CHANGED) { 995 /* buffer has changed, reload map */ 996 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 997 } 998 /* make sure changes to the buffer are synced */ 999 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 1000 BUS_DMASYNC_PREWRITE); 1001 } 1002 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1003 nm_i = nm_next(nm_i, lim); 1004 nic_i = nm_next(nic_i, lim); 1005 } 1006 kring->nr_hwcur = nm_i; 1007 1008 /* synchronize the NIC ring */ 1009 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 1010 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1011 1012 /* (re)start the tx unit up to slot nic_i (excluded) */ 1013 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1014 } 1015 1016 /* 1017 * Second part: reclaim buffers for completed transmissions. 1018 * 1019 * If there are unclaimed buffers, attempt to reclaim them. 1020 * If none are reclaimed, and TX IRQs are not in use, do an initial 1021 * minimal delay, then trigger the tx handler which will spin in the 1022 * group task queue. 1023 */ 1024 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1025 if (iflib_tx_credits_update(ctx, txq)) { 1026 /* some tx completed, increment avail */ 1027 nic_i = txq->ift_cidx_processed; 1028 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1029 } 1030 } 1031 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1032 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1033 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1034 iflib_timer, txq, txq->ift_timer.c_cpu); 1035 } 1036 return (0); 1037 } 1038 1039 /* 1040 * Reconcile kernel and user view of the receive ring. 1041 * Same as for the txsync, this routine must be efficient. 1042 * The caller guarantees a single invocations, but races against 1043 * the rest of the driver should be handled here. 1044 * 1045 * On call, kring->rhead is the first packet that userspace wants 1046 * to keep, and kring->rcur is the wakeup point. 1047 * The kernel has previously reported packets up to kring->rtail. 1048 * 1049 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1050 * of whether or not we received an interrupt. 1051 */ 1052 static int 1053 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1054 { 1055 struct netmap_adapter *na = kring->na; 1056 struct netmap_ring *ring = kring->ring; 1057 uint32_t nm_i; /* index into the netmap ring */ 1058 uint32_t nic_i; /* index into the NIC ring */ 1059 u_int i, n; 1060 u_int const lim = kring->nkr_num_slots - 1; 1061 u_int const head = kring->rhead; 1062 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1063 struct if_rxd_info ri; 1064 1065 struct ifnet *ifp = na->ifp; 1066 if_ctx_t ctx = ifp->if_softc; 1067 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1068 iflib_fl_t fl = rxq->ifr_fl; 1069 if (head > lim) 1070 return netmap_ring_reinit(kring); 1071 1072 /* XXX check sync modes */ 1073 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1074 if (fl->ifl_sds.ifsd_map == NULL) 1075 continue; 1076 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 1077 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1078 } 1079 /* 1080 * First part: import newly received packets. 1081 * 1082 * nm_i is the index of the next free slot in the netmap ring, 1083 * nic_i is the index of the next received packet in the NIC ring, 1084 * and they may differ in case if_init() has been called while 1085 * in netmap mode. For the receive ring we have 1086 * 1087 * nic_i = rxr->next_check; 1088 * nm_i = kring->nr_hwtail (previous) 1089 * and 1090 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1091 * 1092 * rxr->next_check is set to 0 on a ring reinit 1093 */ 1094 if (netmap_no_pendintr || force_update) { 1095 int crclen = iflib_crcstrip ? 0 : 4; 1096 int error, avail; 1097 1098 for (i = 0; i < rxq->ifr_nfl; i++) { 1099 fl = &rxq->ifr_fl[i]; 1100 nic_i = fl->ifl_cidx; 1101 nm_i = netmap_idx_n2k(kring, nic_i); 1102 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 1103 for (n = 0; avail > 0; n++, avail--) { 1104 rxd_info_zero(&ri); 1105 ri.iri_frags = rxq->ifr_frags; 1106 ri.iri_qsidx = kring->ring_id; 1107 ri.iri_ifp = ctx->ifc_ifp; 1108 ri.iri_cidx = nic_i; 1109 1110 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1111 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1112 ring->slot[nm_i].flags = 0; 1113 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1114 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1115 nm_i = nm_next(nm_i, lim); 1116 nic_i = nm_next(nic_i, lim); 1117 } 1118 if (n) { /* update the state variables */ 1119 if (netmap_no_pendintr && !force_update) { 1120 /* diagnostics */ 1121 iflib_rx_miss ++; 1122 iflib_rx_miss_bufs += n; 1123 } 1124 fl->ifl_cidx = nic_i; 1125 kring->nr_hwtail = nm_i; 1126 } 1127 kring->nr_kflags &= ~NKR_PENDINTR; 1128 } 1129 } 1130 /* 1131 * Second part: skip past packets that userspace has released. 1132 * (kring->nr_hwcur to head excluded), 1133 * and make the buffers available for reception. 1134 * As usual nm_i is the index in the netmap ring, 1135 * nic_i is the index in the NIC ring, and 1136 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1137 */ 1138 /* XXX not sure how this will work with multiple free lists */ 1139 nm_i = kring->nr_hwcur; 1140 1141 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1142 } 1143 1144 static void 1145 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1146 { 1147 struct ifnet *ifp = na->ifp; 1148 if_ctx_t ctx = ifp->if_softc; 1149 1150 CTX_LOCK(ctx); 1151 if (onoff) { 1152 IFDI_INTR_ENABLE(ctx); 1153 } else { 1154 IFDI_INTR_DISABLE(ctx); 1155 } 1156 CTX_UNLOCK(ctx); 1157 } 1158 1159 1160 static int 1161 iflib_netmap_attach(if_ctx_t ctx) 1162 { 1163 struct netmap_adapter na; 1164 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1165 1166 bzero(&na, sizeof(na)); 1167 1168 na.ifp = ctx->ifc_ifp; 1169 na.na_flags = NAF_BDG_MAYSLEEP; 1170 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1171 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1172 1173 na.num_tx_desc = scctx->isc_ntxd[0]; 1174 na.num_rx_desc = scctx->isc_nrxd[0]; 1175 na.nm_txsync = iflib_netmap_txsync; 1176 na.nm_rxsync = iflib_netmap_rxsync; 1177 na.nm_register = iflib_netmap_register; 1178 na.nm_intr = iflib_netmap_intr; 1179 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1180 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1181 return (netmap_attach(&na)); 1182 } 1183 1184 static void 1185 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1186 { 1187 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1188 struct netmap_slot *slot; 1189 1190 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1191 if (slot == NULL) 1192 return; 1193 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1194 1195 /* 1196 * In netmap mode, set the map for the packet buffer. 1197 * NOTE: Some drivers (not this one) also need to set 1198 * the physical buffer address in the NIC ring. 1199 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1200 * netmap slot index, si 1201 */ 1202 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1203 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1204 } 1205 } 1206 1207 static void 1208 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1209 { 1210 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1211 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1212 struct netmap_slot *slot; 1213 uint32_t nm_i; 1214 1215 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1216 if (slot == NULL) 1217 return; 1218 nm_i = netmap_idx_n2k(kring, 0); 1219 netmap_fl_refill(rxq, kring, nm_i, true); 1220 } 1221 1222 static void 1223 iflib_netmap_timer_adjust(if_ctx_t ctx, uint16_t txqid, uint32_t *reset_on) 1224 { 1225 struct netmap_kring *kring; 1226 1227 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1228 1229 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1230 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1231 netmap_tx_irq(ctx->ifc_ifp, txqid); 1232 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1233 if (hz < 2000) 1234 *reset_on = 1; 1235 else 1236 *reset_on = hz / 1000; 1237 } 1238 } 1239 } 1240 1241 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1242 1243 #else 1244 #define iflib_netmap_txq_init(ctx, txq) 1245 #define iflib_netmap_rxq_init(ctx, rxq) 1246 #define iflib_netmap_detach(ifp) 1247 1248 #define iflib_netmap_attach(ctx) (0) 1249 #define netmap_rx_irq(ifp, qid, budget) (0) 1250 #define netmap_tx_irq(ifp, qid) do {} while (0) 1251 #define iflib_netmap_timer_adjust(ctx, txqid, reset_on) 1252 1253 #endif 1254 1255 #if defined(__i386__) || defined(__amd64__) 1256 static __inline void 1257 prefetch(void *x) 1258 { 1259 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1260 } 1261 static __inline void 1262 prefetch2cachelines(void *x) 1263 { 1264 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1265 #if (CACHE_LINE_SIZE < 128) 1266 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1267 #endif 1268 } 1269 #else 1270 #define prefetch(x) 1271 #define prefetch2cachelines(x) 1272 #endif 1273 1274 static void 1275 iflib_gen_mac(if_ctx_t ctx) 1276 { 1277 struct thread *td; 1278 MD5_CTX mdctx; 1279 char uuid[HOSTUUIDLEN+1]; 1280 char buf[HOSTUUIDLEN+16]; 1281 uint8_t *mac; 1282 unsigned char digest[16]; 1283 1284 td = curthread; 1285 mac = ctx->ifc_mac; 1286 uuid[HOSTUUIDLEN] = 0; 1287 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN); 1288 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev)); 1289 /* 1290 * Generate a pseudo-random, deterministic MAC 1291 * address based on the UUID and unit number. 1292 * The FreeBSD Foundation OUI of 58-9C-FC is used. 1293 */ 1294 MD5Init(&mdctx); 1295 MD5Update(&mdctx, buf, strlen(buf)); 1296 MD5Final(digest, &mdctx); 1297 1298 mac[0] = 0x58; 1299 mac[1] = 0x9C; 1300 mac[2] = 0xFC; 1301 mac[3] = digest[0]; 1302 mac[4] = digest[1]; 1303 mac[5] = digest[2]; 1304 } 1305 1306 static void 1307 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1308 { 1309 iflib_fl_t fl; 1310 1311 fl = &rxq->ifr_fl[flid]; 1312 iru->iru_paddrs = fl->ifl_bus_addrs; 1313 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1314 iru->iru_idxs = fl->ifl_rxd_idxs; 1315 iru->iru_qsidx = rxq->ifr_id; 1316 iru->iru_buf_size = fl->ifl_buf_size; 1317 iru->iru_flidx = fl->ifl_id; 1318 } 1319 1320 static void 1321 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1322 { 1323 if (err) 1324 return; 1325 *(bus_addr_t *) arg = segs[0].ds_addr; 1326 } 1327 1328 int 1329 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1330 { 1331 int err; 1332 if_shared_ctx_t sctx = ctx->ifc_sctx; 1333 device_t dev = ctx->ifc_dev; 1334 1335 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1336 1337 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1338 sctx->isc_q_align, 0, /* alignment, bounds */ 1339 BUS_SPACE_MAXADDR, /* lowaddr */ 1340 BUS_SPACE_MAXADDR, /* highaddr */ 1341 NULL, NULL, /* filter, filterarg */ 1342 size, /* maxsize */ 1343 1, /* nsegments */ 1344 size, /* maxsegsize */ 1345 BUS_DMA_ALLOCNOW, /* flags */ 1346 NULL, /* lockfunc */ 1347 NULL, /* lockarg */ 1348 &dma->idi_tag); 1349 if (err) { 1350 device_printf(dev, 1351 "%s: bus_dma_tag_create failed: %d\n", 1352 __func__, err); 1353 goto fail_0; 1354 } 1355 1356 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1357 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1358 if (err) { 1359 device_printf(dev, 1360 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1361 __func__, (uintmax_t)size, err); 1362 goto fail_1; 1363 } 1364 1365 dma->idi_paddr = IF_BAD_DMA; 1366 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1367 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1368 if (err || dma->idi_paddr == IF_BAD_DMA) { 1369 device_printf(dev, 1370 "%s: bus_dmamap_load failed: %d\n", 1371 __func__, err); 1372 goto fail_2; 1373 } 1374 1375 dma->idi_size = size; 1376 return (0); 1377 1378 fail_2: 1379 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1380 fail_1: 1381 bus_dma_tag_destroy(dma->idi_tag); 1382 fail_0: 1383 dma->idi_tag = NULL; 1384 1385 return (err); 1386 } 1387 1388 int 1389 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1390 { 1391 int i, err; 1392 iflib_dma_info_t *dmaiter; 1393 1394 dmaiter = dmalist; 1395 for (i = 0; i < count; i++, dmaiter++) { 1396 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1397 break; 1398 } 1399 if (err) 1400 iflib_dma_free_multi(dmalist, i); 1401 return (err); 1402 } 1403 1404 void 1405 iflib_dma_free(iflib_dma_info_t dma) 1406 { 1407 if (dma->idi_tag == NULL) 1408 return; 1409 if (dma->idi_paddr != IF_BAD_DMA) { 1410 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1411 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1412 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1413 dma->idi_paddr = IF_BAD_DMA; 1414 } 1415 if (dma->idi_vaddr != NULL) { 1416 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1417 dma->idi_vaddr = NULL; 1418 } 1419 bus_dma_tag_destroy(dma->idi_tag); 1420 dma->idi_tag = NULL; 1421 } 1422 1423 void 1424 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1425 { 1426 int i; 1427 iflib_dma_info_t *dmaiter = dmalist; 1428 1429 for (i = 0; i < count; i++, dmaiter++) 1430 iflib_dma_free(*dmaiter); 1431 } 1432 1433 #ifdef EARLY_AP_STARTUP 1434 static const int iflib_started = 1; 1435 #else 1436 /* 1437 * We used to abuse the smp_started flag to decide if the queues have been 1438 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1439 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1440 * is set. Run a SYSINIT() strictly after that to just set a usable 1441 * completion flag. 1442 */ 1443 1444 static int iflib_started; 1445 1446 static void 1447 iflib_record_started(void *arg) 1448 { 1449 iflib_started = 1; 1450 } 1451 1452 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1453 iflib_record_started, NULL); 1454 #endif 1455 1456 static int 1457 iflib_fast_intr(void *arg) 1458 { 1459 iflib_filter_info_t info = arg; 1460 struct grouptask *gtask = info->ifi_task; 1461 if (!iflib_started) 1462 return (FILTER_HANDLED); 1463 1464 DBG_COUNTER_INC(fast_intrs); 1465 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1466 return (FILTER_HANDLED); 1467 1468 GROUPTASK_ENQUEUE(gtask); 1469 return (FILTER_HANDLED); 1470 } 1471 1472 static int 1473 iflib_fast_intr_rxtx(void *arg) 1474 { 1475 iflib_filter_info_t info = arg; 1476 struct grouptask *gtask = info->ifi_task; 1477 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1478 if_ctx_t ctx = NULL;; 1479 int i, cidx; 1480 1481 if (!iflib_started) 1482 return (FILTER_HANDLED); 1483 1484 DBG_COUNTER_INC(fast_intrs); 1485 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1486 return (FILTER_HANDLED); 1487 1488 MPASS(rxq->ifr_ntxqirq); 1489 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1490 qidx_t txqid = rxq->ifr_txqid[i]; 1491 1492 ctx = rxq->ifr_ctx; 1493 1494 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1495 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1496 continue; 1497 } 1498 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1499 } 1500 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1501 cidx = rxq->ifr_cq_cidx; 1502 else 1503 cidx = rxq->ifr_fl[0].ifl_cidx; 1504 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1505 GROUPTASK_ENQUEUE(gtask); 1506 else { 1507 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1508 DBG_COUNTER_INC(rx_intr_enables); 1509 } 1510 return (FILTER_HANDLED); 1511 } 1512 1513 1514 static int 1515 iflib_fast_intr_ctx(void *arg) 1516 { 1517 iflib_filter_info_t info = arg; 1518 struct grouptask *gtask = info->ifi_task; 1519 1520 if (!iflib_started) 1521 return (FILTER_HANDLED); 1522 1523 DBG_COUNTER_INC(fast_intrs); 1524 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1525 return (FILTER_HANDLED); 1526 1527 GROUPTASK_ENQUEUE(gtask); 1528 return (FILTER_HANDLED); 1529 } 1530 1531 static int 1532 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1533 driver_filter_t filter, driver_intr_t handler, void *arg, 1534 const char *name) 1535 { 1536 int rc, flags; 1537 struct resource *res; 1538 void *tag = NULL; 1539 device_t dev = ctx->ifc_dev; 1540 1541 flags = RF_ACTIVE; 1542 if (ctx->ifc_flags & IFC_LEGACY) 1543 flags |= RF_SHAREABLE; 1544 MPASS(rid < 512); 1545 irq->ii_rid = rid; 1546 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1547 if (res == NULL) { 1548 device_printf(dev, 1549 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1550 return (ENOMEM); 1551 } 1552 irq->ii_res = res; 1553 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1554 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1555 filter, handler, arg, &tag); 1556 if (rc != 0) { 1557 device_printf(dev, 1558 "failed to setup interrupt for rid %d, name %s: %d\n", 1559 rid, name ? name : "unknown", rc); 1560 return (rc); 1561 } else if (name) 1562 bus_describe_intr(dev, res, tag, "%s", name); 1563 1564 irq->ii_tag = tag; 1565 return (0); 1566 } 1567 1568 1569 /********************************************************************* 1570 * 1571 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1572 * the information needed to transmit a packet on the wire. This is 1573 * called only once at attach, setup is done every reset. 1574 * 1575 **********************************************************************/ 1576 1577 static int 1578 iflib_txsd_alloc(iflib_txq_t txq) 1579 { 1580 if_ctx_t ctx = txq->ift_ctx; 1581 if_shared_ctx_t sctx = ctx->ifc_sctx; 1582 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1583 device_t dev = ctx->ifc_dev; 1584 bus_size_t tsomaxsize; 1585 int err, nsegments, ntsosegments; 1586 1587 nsegments = scctx->isc_tx_nsegments; 1588 ntsosegments = scctx->isc_tx_tso_segments_max; 1589 tsomaxsize = scctx->isc_tx_tso_size_max; 1590 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1591 tsomaxsize += sizeof(struct ether_vlan_header); 1592 MPASS(scctx->isc_ntxd[0] > 0); 1593 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1594 MPASS(nsegments > 0); 1595 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1596 MPASS(ntsosegments > 0); 1597 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1598 } 1599 1600 /* 1601 * Setup DMA descriptor areas. 1602 */ 1603 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1604 1, 0, /* alignment, bounds */ 1605 BUS_SPACE_MAXADDR, /* lowaddr */ 1606 BUS_SPACE_MAXADDR, /* highaddr */ 1607 NULL, NULL, /* filter, filterarg */ 1608 sctx->isc_tx_maxsize, /* maxsize */ 1609 nsegments, /* nsegments */ 1610 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1611 0, /* flags */ 1612 NULL, /* lockfunc */ 1613 NULL, /* lockfuncarg */ 1614 &txq->ift_desc_tag))) { 1615 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1616 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1617 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1618 goto fail; 1619 } 1620 if ((if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) & 1621 (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1622 1, 0, /* alignment, bounds */ 1623 BUS_SPACE_MAXADDR, /* lowaddr */ 1624 BUS_SPACE_MAXADDR, /* highaddr */ 1625 NULL, NULL, /* filter, filterarg */ 1626 tsomaxsize, /* maxsize */ 1627 ntsosegments, /* nsegments */ 1628 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1629 0, /* flags */ 1630 NULL, /* lockfunc */ 1631 NULL, /* lockfuncarg */ 1632 &txq->ift_tso_desc_tag))) { 1633 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1634 1635 goto fail; 1636 } 1637 if (!(txq->ift_sds.ifsd_m = 1638 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1639 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1640 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1641 err = ENOMEM; 1642 goto fail; 1643 } 1644 1645 /* Create the descriptor buffer dma maps */ 1646 if (!(txq->ift_sds.ifsd_map = 1647 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1648 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1649 err = ENOMEM; 1650 goto fail; 1651 } 1652 1653 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1654 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1655 if (err != 0) { 1656 device_printf(dev, "Unable to create TX DMA map\n"); 1657 goto fail; 1658 } 1659 } 1660 return (0); 1661 fail: 1662 /* We free all, it handles case where we are in the middle */ 1663 iflib_tx_structures_free(ctx); 1664 return (err); 1665 } 1666 1667 static void 1668 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1669 { 1670 bus_dmamap_t map; 1671 1672 map = NULL; 1673 if (txq->ift_sds.ifsd_map != NULL) 1674 map = txq->ift_sds.ifsd_map[i]; 1675 if (map != NULL) { 1676 bus_dmamap_unload(txq->ift_desc_tag, map); 1677 bus_dmamap_destroy(txq->ift_desc_tag, map); 1678 txq->ift_sds.ifsd_map[i] = NULL; 1679 } 1680 } 1681 1682 static void 1683 iflib_txq_destroy(iflib_txq_t txq) 1684 { 1685 if_ctx_t ctx = txq->ift_ctx; 1686 1687 for (int i = 0; i < txq->ift_size; i++) 1688 iflib_txsd_destroy(ctx, txq, i); 1689 if (txq->ift_sds.ifsd_map != NULL) { 1690 free(txq->ift_sds.ifsd_map, M_IFLIB); 1691 txq->ift_sds.ifsd_map = NULL; 1692 } 1693 if (txq->ift_sds.ifsd_m != NULL) { 1694 free(txq->ift_sds.ifsd_m, M_IFLIB); 1695 txq->ift_sds.ifsd_m = NULL; 1696 } 1697 if (txq->ift_desc_tag != NULL) { 1698 bus_dma_tag_destroy(txq->ift_desc_tag); 1699 txq->ift_desc_tag = NULL; 1700 } 1701 if (txq->ift_tso_desc_tag != NULL) { 1702 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1703 txq->ift_tso_desc_tag = NULL; 1704 } 1705 } 1706 1707 static void 1708 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1709 { 1710 struct mbuf **mp; 1711 1712 mp = &txq->ift_sds.ifsd_m[i]; 1713 if (*mp == NULL) 1714 return; 1715 1716 if (txq->ift_sds.ifsd_map != NULL) { 1717 bus_dmamap_sync(txq->ift_desc_tag, 1718 txq->ift_sds.ifsd_map[i], 1719 BUS_DMASYNC_POSTWRITE); 1720 bus_dmamap_unload(txq->ift_desc_tag, 1721 txq->ift_sds.ifsd_map[i]); 1722 } 1723 m_free(*mp); 1724 DBG_COUNTER_INC(tx_frees); 1725 *mp = NULL; 1726 } 1727 1728 static int 1729 iflib_txq_setup(iflib_txq_t txq) 1730 { 1731 if_ctx_t ctx = txq->ift_ctx; 1732 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1733 if_shared_ctx_t sctx = ctx->ifc_sctx; 1734 iflib_dma_info_t di; 1735 int i; 1736 1737 /* Set number of descriptors available */ 1738 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1739 /* XXX make configurable */ 1740 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1741 1742 /* Reset indices */ 1743 txq->ift_cidx_processed = 0; 1744 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1745 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1746 1747 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1748 bzero((void *)di->idi_vaddr, di->idi_size); 1749 1750 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1751 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1752 bus_dmamap_sync(di->idi_tag, di->idi_map, 1753 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1754 return (0); 1755 } 1756 1757 /********************************************************************* 1758 * 1759 * Allocate memory for rx_buffer structures. Since we use one 1760 * rx_buffer per received packet, the maximum number of rx_buffer's 1761 * that we'll need is equal to the number of receive descriptors 1762 * that we've allocated. 1763 * 1764 **********************************************************************/ 1765 static int 1766 iflib_rxsd_alloc(iflib_rxq_t rxq) 1767 { 1768 if_ctx_t ctx = rxq->ifr_ctx; 1769 if_shared_ctx_t sctx = ctx->ifc_sctx; 1770 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1771 device_t dev = ctx->ifc_dev; 1772 iflib_fl_t fl; 1773 int err; 1774 1775 MPASS(scctx->isc_nrxd[0] > 0); 1776 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1777 1778 fl = rxq->ifr_fl; 1779 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1780 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1781 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1782 1, 0, /* alignment, bounds */ 1783 BUS_SPACE_MAXADDR, /* lowaddr */ 1784 BUS_SPACE_MAXADDR, /* highaddr */ 1785 NULL, NULL, /* filter, filterarg */ 1786 sctx->isc_rx_maxsize, /* maxsize */ 1787 sctx->isc_rx_nsegments, /* nsegments */ 1788 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1789 0, /* flags */ 1790 NULL, /* lockfunc */ 1791 NULL, /* lockarg */ 1792 &fl->ifl_desc_tag); 1793 if (err) { 1794 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1795 __func__, err); 1796 goto fail; 1797 } 1798 if (!(fl->ifl_sds.ifsd_m = 1799 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1800 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1801 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1802 err = ENOMEM; 1803 goto fail; 1804 } 1805 if (!(fl->ifl_sds.ifsd_cl = 1806 (caddr_t *) malloc(sizeof(caddr_t) * 1807 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1808 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1809 err = ENOMEM; 1810 goto fail; 1811 } 1812 1813 if (!(fl->ifl_sds.ifsd_ba = 1814 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1815 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1816 device_printf(dev, "Unable to allocate rx bus addr memory\n"); 1817 err = ENOMEM; 1818 goto fail; 1819 } 1820 1821 /* Create the descriptor buffer dma maps */ 1822 if (!(fl->ifl_sds.ifsd_map = 1823 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1824 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1825 err = ENOMEM; 1826 goto fail; 1827 } 1828 1829 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1830 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1831 if (err != 0) { 1832 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1833 goto fail; 1834 } 1835 } 1836 } 1837 return (0); 1838 1839 fail: 1840 iflib_rx_structures_free(ctx); 1841 return (err); 1842 } 1843 1844 1845 /* 1846 * Internal service routines 1847 */ 1848 1849 struct rxq_refill_cb_arg { 1850 int error; 1851 bus_dma_segment_t seg; 1852 int nseg; 1853 }; 1854 1855 static void 1856 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1857 { 1858 struct rxq_refill_cb_arg *cb_arg = arg; 1859 1860 cb_arg->error = error; 1861 cb_arg->seg = segs[0]; 1862 cb_arg->nseg = nseg; 1863 } 1864 1865 /** 1866 * rxq_refill - refill an rxq free-buffer list 1867 * @ctx: the iflib context 1868 * @rxq: the free-list to refill 1869 * @n: the number of new buffers to allocate 1870 * 1871 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1872 * The caller must assure that @n does not exceed the queue's capacity. 1873 */ 1874 static void 1875 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1876 { 1877 struct mbuf *m; 1878 int idx, frag_idx = fl->ifl_fragidx; 1879 int pidx = fl->ifl_pidx; 1880 caddr_t cl, *sd_cl; 1881 struct mbuf **sd_m; 1882 struct if_rxd_update iru; 1883 struct rxq_refill_cb_arg cb_arg; 1884 bus_dmamap_t *sd_map; 1885 int n, i = 0; 1886 bus_addr_t bus_addr, *sd_ba; 1887 int err; 1888 qidx_t credits; 1889 1890 sd_m = fl->ifl_sds.ifsd_m; 1891 sd_map = fl->ifl_sds.ifsd_map; 1892 sd_cl = fl->ifl_sds.ifsd_cl; 1893 sd_ba = fl->ifl_sds.ifsd_ba; 1894 idx = pidx; 1895 credits = fl->ifl_credits; 1896 1897 n = count; 1898 MPASS(n > 0); 1899 MPASS(credits + n <= fl->ifl_size); 1900 1901 if (pidx < fl->ifl_cidx) 1902 MPASS(pidx + n <= fl->ifl_cidx); 1903 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1904 MPASS(fl->ifl_gen == 0); 1905 if (pidx > fl->ifl_cidx) 1906 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1907 1908 DBG_COUNTER_INC(fl_refills); 1909 if (n > 8) 1910 DBG_COUNTER_INC(fl_refills_large); 1911 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1912 while (n--) { 1913 /* 1914 * We allocate an uninitialized mbuf + cluster, mbuf is 1915 * initialized after rx. 1916 * 1917 * If the cluster is still set then we know a minimum sized packet was received 1918 */ 1919 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1920 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1921 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1922 if ((cl = sd_cl[frag_idx]) == NULL) { 1923 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1924 break; 1925 1926 cb_arg.error = 0; 1927 MPASS(sd_map != NULL); 1928 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1929 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1930 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 1931 BUS_DMASYNC_PREREAD); 1932 1933 if (err != 0 || cb_arg.error) { 1934 /* 1935 * !zone_pack ? 1936 */ 1937 if (fl->ifl_zone == zone_pack) 1938 uma_zfree(fl->ifl_zone, cl); 1939 break; 1940 } 1941 1942 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 1943 sd_cl[frag_idx] = cl; 1944 #if MEMORY_LOGGING 1945 fl->ifl_cl_enqueued++; 1946 #endif 1947 } else { 1948 bus_addr = sd_ba[frag_idx]; 1949 } 1950 1951 bit_set(fl->ifl_rx_bitmap, frag_idx); 1952 MPASS(sd_m[frag_idx] == NULL); 1953 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1954 break; 1955 } 1956 sd_m[frag_idx] = m; 1957 #if MEMORY_LOGGING 1958 fl->ifl_m_enqueued++; 1959 #endif 1960 1961 DBG_COUNTER_INC(rx_allocs); 1962 fl->ifl_rxd_idxs[i] = frag_idx; 1963 fl->ifl_bus_addrs[i] = bus_addr; 1964 fl->ifl_vm_addrs[i] = cl; 1965 credits++; 1966 i++; 1967 MPASS(credits <= fl->ifl_size); 1968 if (++idx == fl->ifl_size) { 1969 fl->ifl_gen = 1; 1970 idx = 0; 1971 } 1972 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 1973 iru.iru_pidx = pidx; 1974 iru.iru_count = i; 1975 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1976 i = 0; 1977 pidx = idx; 1978 fl->ifl_pidx = idx; 1979 fl->ifl_credits = credits; 1980 } 1981 1982 } 1983 1984 if (i) { 1985 iru.iru_pidx = pidx; 1986 iru.iru_count = i; 1987 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1988 fl->ifl_pidx = idx; 1989 fl->ifl_credits = credits; 1990 } 1991 DBG_COUNTER_INC(rxd_flush); 1992 if (fl->ifl_pidx == 0) 1993 pidx = fl->ifl_size - 1; 1994 else 1995 pidx = fl->ifl_pidx - 1; 1996 1997 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1998 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1999 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2000 fl->ifl_fragidx = frag_idx; 2001 } 2002 2003 static __inline void 2004 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2005 { 2006 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2007 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2008 #ifdef INVARIANTS 2009 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2010 #endif 2011 2012 MPASS(fl->ifl_credits <= fl->ifl_size); 2013 MPASS(reclaimable == delta); 2014 2015 if (reclaimable > 0) 2016 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2017 } 2018 2019 uint8_t 2020 iflib_in_detach(if_ctx_t ctx) 2021 { 2022 bool in_detach; 2023 STATE_LOCK(ctx); 2024 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2025 STATE_UNLOCK(ctx); 2026 return (in_detach); 2027 } 2028 2029 static void 2030 iflib_fl_bufs_free(iflib_fl_t fl) 2031 { 2032 iflib_dma_info_t idi = fl->ifl_ifdi; 2033 uint32_t i; 2034 2035 for (i = 0; i < fl->ifl_size; i++) { 2036 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2037 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2038 2039 if (*sd_cl != NULL) { 2040 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 2041 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 2042 if (*sd_cl != NULL) 2043 uma_zfree(fl->ifl_zone, *sd_cl); 2044 // XXX: Should this get moved out? 2045 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx)) 2046 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 2047 if (*sd_m != NULL) { 2048 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2049 uma_zfree(zone_mbuf, *sd_m); 2050 } 2051 } else { 2052 MPASS(*sd_cl == NULL); 2053 MPASS(*sd_m == NULL); 2054 } 2055 #if MEMORY_LOGGING 2056 fl->ifl_m_dequeued++; 2057 fl->ifl_cl_dequeued++; 2058 #endif 2059 *sd_cl = NULL; 2060 *sd_m = NULL; 2061 } 2062 #ifdef INVARIANTS 2063 for (i = 0; i < fl->ifl_size; i++) { 2064 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2065 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2066 } 2067 #endif 2068 /* 2069 * Reset free list values 2070 */ 2071 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2072 bzero(idi->idi_vaddr, idi->idi_size); 2073 } 2074 2075 /********************************************************************* 2076 * 2077 * Initialize a receive ring and its buffers. 2078 * 2079 **********************************************************************/ 2080 static int 2081 iflib_fl_setup(iflib_fl_t fl) 2082 { 2083 iflib_rxq_t rxq = fl->ifl_rxq; 2084 if_ctx_t ctx = rxq->ifr_ctx; 2085 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2086 2087 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2088 /* 2089 ** Free current RX buffer structs and their mbufs 2090 */ 2091 iflib_fl_bufs_free(fl); 2092 /* Now replenish the mbufs */ 2093 MPASS(fl->ifl_credits == 0); 2094 /* 2095 * XXX don't set the max_frame_size to larger 2096 * than the hardware can handle 2097 */ 2098 if (sctx->isc_max_frame_size <= 2048) 2099 fl->ifl_buf_size = MCLBYTES; 2100 #ifndef CONTIGMALLOC_WORKS 2101 else 2102 fl->ifl_buf_size = MJUMPAGESIZE; 2103 #else 2104 else if (sctx->isc_max_frame_size <= 4096) 2105 fl->ifl_buf_size = MJUMPAGESIZE; 2106 else if (sctx->isc_max_frame_size <= 9216) 2107 fl->ifl_buf_size = MJUM9BYTES; 2108 else 2109 fl->ifl_buf_size = MJUM16BYTES; 2110 #endif 2111 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2112 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2113 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2114 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2115 2116 2117 /* avoid pre-allocating zillions of clusters to an idle card 2118 * potentially speeding up attach 2119 */ 2120 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2121 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2122 if (min(128, fl->ifl_size) != fl->ifl_credits) 2123 return (ENOBUFS); 2124 /* 2125 * handle failure 2126 */ 2127 MPASS(rxq != NULL); 2128 MPASS(fl->ifl_ifdi != NULL); 2129 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2130 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2131 return (0); 2132 } 2133 2134 /********************************************************************* 2135 * 2136 * Free receive ring data structures 2137 * 2138 **********************************************************************/ 2139 static void 2140 iflib_rx_sds_free(iflib_rxq_t rxq) 2141 { 2142 iflib_fl_t fl; 2143 int i; 2144 2145 if (rxq->ifr_fl != NULL) { 2146 for (i = 0; i < rxq->ifr_nfl; i++) { 2147 fl = &rxq->ifr_fl[i]; 2148 if (fl->ifl_desc_tag != NULL) { 2149 bus_dma_tag_destroy(fl->ifl_desc_tag); 2150 fl->ifl_desc_tag = NULL; 2151 } 2152 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2153 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2154 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2155 /* XXX destroy maps first */ 2156 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2157 fl->ifl_sds.ifsd_m = NULL; 2158 fl->ifl_sds.ifsd_cl = NULL; 2159 fl->ifl_sds.ifsd_ba = NULL; 2160 fl->ifl_sds.ifsd_map = NULL; 2161 } 2162 free(rxq->ifr_fl, M_IFLIB); 2163 rxq->ifr_fl = NULL; 2164 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2165 } 2166 } 2167 2168 /* 2169 * MI independent logic 2170 * 2171 */ 2172 static void 2173 iflib_timer(void *arg) 2174 { 2175 iflib_txq_t txq = arg; 2176 if_ctx_t ctx = txq->ift_ctx; 2177 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2178 uint64_t this_tick = ticks; 2179 uint32_t reset_on = hz / 2; 2180 2181 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2182 return; 2183 /* 2184 ** Check on the state of the TX queue(s), this 2185 ** can be done without the lock because its RO 2186 ** and the HUNG state will be static if set. 2187 */ 2188 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2189 txq->ift_last_timer_tick = this_tick; 2190 IFDI_TIMER(ctx, txq->ift_id); 2191 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2192 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2193 (sctx->isc_pause_frames == 0))) 2194 goto hung; 2195 2196 if (ifmp_ring_is_stalled(txq->ift_br)) 2197 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2198 txq->ift_cleaned_prev = txq->ift_cleaned; 2199 } 2200 #ifdef DEV_NETMAP 2201 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2202 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on); 2203 #endif 2204 /* handle any laggards */ 2205 if (txq->ift_db_pending) 2206 GROUPTASK_ENQUEUE(&txq->ift_task); 2207 2208 sctx->isc_pause_frames = 0; 2209 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2210 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2211 return; 2212 hung: 2213 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2214 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2215 STATE_LOCK(ctx); 2216 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2217 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2218 iflib_admin_intr_deferred(ctx); 2219 STATE_UNLOCK(ctx); 2220 } 2221 2222 static void 2223 iflib_init_locked(if_ctx_t ctx) 2224 { 2225 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2226 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2227 if_t ifp = ctx->ifc_ifp; 2228 iflib_fl_t fl; 2229 iflib_txq_t txq; 2230 iflib_rxq_t rxq; 2231 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2232 2233 2234 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2235 IFDI_INTR_DISABLE(ctx); 2236 2237 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2238 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2239 /* Set hardware offload abilities */ 2240 if_clearhwassist(ifp); 2241 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2242 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2243 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2244 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2245 if (if_getcapenable(ifp) & IFCAP_TSO4) 2246 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2247 if (if_getcapenable(ifp) & IFCAP_TSO6) 2248 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2249 2250 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2251 CALLOUT_LOCK(txq); 2252 callout_stop(&txq->ift_timer); 2253 CALLOUT_UNLOCK(txq); 2254 iflib_netmap_txq_init(ctx, txq); 2255 } 2256 #ifdef INVARIANTS 2257 i = if_getdrvflags(ifp); 2258 #endif 2259 IFDI_INIT(ctx); 2260 MPASS(if_getdrvflags(ifp) == i); 2261 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2262 /* XXX this should really be done on a per-queue basis */ 2263 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2264 MPASS(rxq->ifr_id == i); 2265 iflib_netmap_rxq_init(ctx, rxq); 2266 continue; 2267 } 2268 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2269 if (iflib_fl_setup(fl)) { 2270 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2271 goto done; 2272 } 2273 } 2274 } 2275 done: 2276 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2277 IFDI_INTR_ENABLE(ctx); 2278 txq = ctx->ifc_txqs; 2279 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2280 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2281 txq->ift_timer.c_cpu); 2282 } 2283 2284 static int 2285 iflib_media_change(if_t ifp) 2286 { 2287 if_ctx_t ctx = if_getsoftc(ifp); 2288 int err; 2289 2290 CTX_LOCK(ctx); 2291 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2292 iflib_init_locked(ctx); 2293 CTX_UNLOCK(ctx); 2294 return (err); 2295 } 2296 2297 static void 2298 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2299 { 2300 if_ctx_t ctx = if_getsoftc(ifp); 2301 2302 CTX_LOCK(ctx); 2303 IFDI_UPDATE_ADMIN_STATUS(ctx); 2304 IFDI_MEDIA_STATUS(ctx, ifmr); 2305 CTX_UNLOCK(ctx); 2306 } 2307 2308 void 2309 iflib_stop(if_ctx_t ctx) 2310 { 2311 iflib_txq_t txq = ctx->ifc_txqs; 2312 iflib_rxq_t rxq = ctx->ifc_rxqs; 2313 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2314 if_shared_ctx_t sctx = ctx->ifc_sctx; 2315 iflib_dma_info_t di; 2316 iflib_fl_t fl; 2317 int i, j; 2318 2319 /* Tell the stack that the interface is no longer active */ 2320 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2321 2322 IFDI_INTR_DISABLE(ctx); 2323 DELAY(1000); 2324 IFDI_STOP(ctx); 2325 DELAY(1000); 2326 2327 iflib_debug_reset(); 2328 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2329 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2330 /* make sure all transmitters have completed before proceeding XXX */ 2331 2332 CALLOUT_LOCK(txq); 2333 callout_stop(&txq->ift_timer); 2334 CALLOUT_UNLOCK(txq); 2335 2336 /* clean any enqueued buffers */ 2337 iflib_ifmp_purge(txq); 2338 /* Free any existing tx buffers. */ 2339 for (j = 0; j < txq->ift_size; j++) { 2340 iflib_txsd_free(ctx, txq, j); 2341 } 2342 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2343 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2344 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2345 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2346 txq->ift_pullups = 0; 2347 ifmp_ring_reset_stats(txq->ift_br); 2348 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2349 bzero((void *)di->idi_vaddr, di->idi_size); 2350 } 2351 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2352 /* make sure all transmitters have completed before proceeding XXX */ 2353 2354 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2355 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2356 bzero((void *)di->idi_vaddr, di->idi_size); 2357 /* also resets the free lists pidx/cidx */ 2358 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2359 iflib_fl_bufs_free(fl); 2360 } 2361 } 2362 2363 static inline caddr_t 2364 calc_next_rxd(iflib_fl_t fl, int cidx) 2365 { 2366 qidx_t size; 2367 int nrxd; 2368 caddr_t start, end, cur, next; 2369 2370 nrxd = fl->ifl_size; 2371 size = fl->ifl_rxd_size; 2372 start = fl->ifl_ifdi->idi_vaddr; 2373 2374 if (__predict_false(size == 0)) 2375 return (start); 2376 cur = start + size*cidx; 2377 end = start + size*nrxd; 2378 next = CACHE_PTR_NEXT(cur); 2379 return (next < end ? next : start); 2380 } 2381 2382 static inline void 2383 prefetch_pkts(iflib_fl_t fl, int cidx) 2384 { 2385 int nextptr; 2386 int nrxd = fl->ifl_size; 2387 caddr_t next_rxd; 2388 2389 2390 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2391 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2392 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2393 next_rxd = calc_next_rxd(fl, cidx); 2394 prefetch(next_rxd); 2395 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2396 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2397 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2398 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2399 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2400 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2401 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2402 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2403 } 2404 2405 static void 2406 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2407 { 2408 int flid, cidx; 2409 bus_dmamap_t map; 2410 iflib_fl_t fl; 2411 iflib_dma_info_t di; 2412 int next; 2413 2414 map = NULL; 2415 flid = irf->irf_flid; 2416 cidx = irf->irf_idx; 2417 fl = &rxq->ifr_fl[flid]; 2418 sd->ifsd_fl = fl; 2419 sd->ifsd_cidx = cidx; 2420 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2421 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2422 fl->ifl_credits--; 2423 #if MEMORY_LOGGING 2424 fl->ifl_m_dequeued++; 2425 #endif 2426 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2427 prefetch_pkts(fl, cidx); 2428 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2429 prefetch(&fl->ifl_sds.ifsd_map[next]); 2430 map = fl->ifl_sds.ifsd_map[cidx]; 2431 di = fl->ifl_ifdi; 2432 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2433 bus_dmamap_sync(di->idi_tag, di->idi_map, 2434 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2435 2436 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2437 MPASS(fl->ifl_cidx == cidx); 2438 if (unload) 2439 bus_dmamap_unload(fl->ifl_desc_tag, map); 2440 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2441 if (__predict_false(fl->ifl_cidx == 0)) 2442 fl->ifl_gen = 0; 2443 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2444 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2445 bit_clear(fl->ifl_rx_bitmap, cidx); 2446 } 2447 2448 static struct mbuf * 2449 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2450 { 2451 int i, padlen , flags; 2452 struct mbuf *m, *mh, *mt; 2453 caddr_t cl; 2454 2455 i = 0; 2456 mh = NULL; 2457 do { 2458 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2459 2460 MPASS(*sd->ifsd_cl != NULL); 2461 MPASS(*sd->ifsd_m != NULL); 2462 2463 /* Don't include zero-length frags */ 2464 if (ri->iri_frags[i].irf_len == 0) { 2465 /* XXX we can save the cluster here, but not the mbuf */ 2466 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2467 m_free(*sd->ifsd_m); 2468 *sd->ifsd_m = NULL; 2469 continue; 2470 } 2471 m = *sd->ifsd_m; 2472 *sd->ifsd_m = NULL; 2473 if (mh == NULL) { 2474 flags = M_PKTHDR|M_EXT; 2475 mh = mt = m; 2476 padlen = ri->iri_pad; 2477 } else { 2478 flags = M_EXT; 2479 mt->m_next = m; 2480 mt = m; 2481 /* assuming padding is only on the first fragment */ 2482 padlen = 0; 2483 } 2484 cl = *sd->ifsd_cl; 2485 *sd->ifsd_cl = NULL; 2486 2487 /* Can these two be made one ? */ 2488 m_init(m, M_NOWAIT, MT_DATA, flags); 2489 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2490 /* 2491 * These must follow m_init and m_cljset 2492 */ 2493 m->m_data += padlen; 2494 ri->iri_len -= padlen; 2495 m->m_len = ri->iri_frags[i].irf_len; 2496 } while (++i < ri->iri_nfrags); 2497 2498 return (mh); 2499 } 2500 2501 /* 2502 * Process one software descriptor 2503 */ 2504 static struct mbuf * 2505 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2506 { 2507 struct if_rxsd sd; 2508 struct mbuf *m; 2509 2510 /* should I merge this back in now that the two paths are basically duplicated? */ 2511 if (ri->iri_nfrags == 1 && 2512 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2513 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2514 m = *sd.ifsd_m; 2515 *sd.ifsd_m = NULL; 2516 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2517 #ifndef __NO_STRICT_ALIGNMENT 2518 if (!IP_ALIGNED(m)) 2519 m->m_data += 2; 2520 #endif 2521 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2522 m->m_len = ri->iri_frags[0].irf_len; 2523 } else { 2524 m = assemble_segments(rxq, ri, &sd); 2525 } 2526 m->m_pkthdr.len = ri->iri_len; 2527 m->m_pkthdr.rcvif = ri->iri_ifp; 2528 m->m_flags |= ri->iri_flags; 2529 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2530 m->m_pkthdr.flowid = ri->iri_flowid; 2531 M_HASHTYPE_SET(m, ri->iri_rsstype); 2532 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2533 m->m_pkthdr.csum_data = ri->iri_csum_data; 2534 return (m); 2535 } 2536 2537 #if defined(INET6) || defined(INET) 2538 static void 2539 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2540 { 2541 CURVNET_SET(lc->ifp->if_vnet); 2542 #if defined(INET6) 2543 *v6 = VNET(ip6_forwarding); 2544 #endif 2545 #if defined(INET) 2546 *v4 = VNET(ipforwarding); 2547 #endif 2548 CURVNET_RESTORE(); 2549 } 2550 2551 /* 2552 * Returns true if it's possible this packet could be LROed. 2553 * if it returns false, it is guaranteed that tcp_lro_rx() 2554 * would not return zero. 2555 */ 2556 static bool 2557 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2558 { 2559 struct ether_header *eh; 2560 uint16_t eh_type; 2561 2562 eh = mtod(m, struct ether_header *); 2563 eh_type = ntohs(eh->ether_type); 2564 switch (eh_type) { 2565 #if defined(INET6) 2566 case ETHERTYPE_IPV6: 2567 return !v6_forwarding; 2568 #endif 2569 #if defined (INET) 2570 case ETHERTYPE_IP: 2571 return !v4_forwarding; 2572 #endif 2573 } 2574 2575 return false; 2576 } 2577 #else 2578 static void 2579 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2580 { 2581 } 2582 #endif 2583 2584 static bool 2585 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2586 { 2587 if_ctx_t ctx = rxq->ifr_ctx; 2588 if_shared_ctx_t sctx = ctx->ifc_sctx; 2589 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2590 int avail, i; 2591 qidx_t *cidxp; 2592 struct if_rxd_info ri; 2593 int err, budget_left, rx_bytes, rx_pkts; 2594 iflib_fl_t fl; 2595 struct ifnet *ifp; 2596 int lro_enabled; 2597 bool v4_forwarding, v6_forwarding, lro_possible; 2598 2599 /* 2600 * XXX early demux data packets so that if_input processing only handles 2601 * acks in interrupt context 2602 */ 2603 struct mbuf *m, *mh, *mt, *mf; 2604 2605 lro_possible = v4_forwarding = v6_forwarding = false; 2606 ifp = ctx->ifc_ifp; 2607 mh = mt = NULL; 2608 MPASS(budget > 0); 2609 rx_pkts = rx_bytes = 0; 2610 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2611 cidxp = &rxq->ifr_cq_cidx; 2612 else 2613 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2614 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2615 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2616 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2617 DBG_COUNTER_INC(rx_unavail); 2618 return (false); 2619 } 2620 2621 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2622 if (__predict_false(!CTX_ACTIVE(ctx))) { 2623 DBG_COUNTER_INC(rx_ctx_inactive); 2624 break; 2625 } 2626 /* 2627 * Reset client set fields to their default values 2628 */ 2629 rxd_info_zero(&ri); 2630 ri.iri_qsidx = rxq->ifr_id; 2631 ri.iri_cidx = *cidxp; 2632 ri.iri_ifp = ifp; 2633 ri.iri_frags = rxq->ifr_frags; 2634 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2635 2636 if (err) 2637 goto err; 2638 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2639 *cidxp = ri.iri_cidx; 2640 /* Update our consumer index */ 2641 /* XXX NB: shurd - check if this is still safe */ 2642 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2643 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2644 rxq->ifr_cq_gen = 0; 2645 } 2646 /* was this only a completion queue message? */ 2647 if (__predict_false(ri.iri_nfrags == 0)) 2648 continue; 2649 } 2650 MPASS(ri.iri_nfrags != 0); 2651 MPASS(ri.iri_len != 0); 2652 2653 /* will advance the cidx on the corresponding free lists */ 2654 m = iflib_rxd_pkt_get(rxq, &ri); 2655 avail--; 2656 budget_left--; 2657 if (avail == 0 && budget_left) 2658 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2659 2660 if (__predict_false(m == NULL)) { 2661 DBG_COUNTER_INC(rx_mbuf_null); 2662 continue; 2663 } 2664 /* imm_pkt: -- cxgb */ 2665 if (mh == NULL) 2666 mh = mt = m; 2667 else { 2668 mt->m_nextpkt = m; 2669 mt = m; 2670 } 2671 } 2672 /* make sure that we can refill faster than drain */ 2673 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2674 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2675 2676 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2677 if (lro_enabled) 2678 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2679 mt = mf = NULL; 2680 while (mh != NULL) { 2681 m = mh; 2682 mh = mh->m_nextpkt; 2683 m->m_nextpkt = NULL; 2684 #ifndef __NO_STRICT_ALIGNMENT 2685 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2686 continue; 2687 #endif 2688 rx_bytes += m->m_pkthdr.len; 2689 rx_pkts++; 2690 #if defined(INET6) || defined(INET) 2691 if (lro_enabled) { 2692 if (!lro_possible) { 2693 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2694 if (lro_possible && mf != NULL) { 2695 ifp->if_input(ifp, mf); 2696 DBG_COUNTER_INC(rx_if_input); 2697 mt = mf = NULL; 2698 } 2699 } 2700 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2701 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2702 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2703 continue; 2704 } 2705 } 2706 #endif 2707 if (lro_possible) { 2708 ifp->if_input(ifp, m); 2709 DBG_COUNTER_INC(rx_if_input); 2710 continue; 2711 } 2712 2713 if (mf == NULL) 2714 mf = m; 2715 if (mt != NULL) 2716 mt->m_nextpkt = m; 2717 mt = m; 2718 } 2719 if (mf != NULL) { 2720 ifp->if_input(ifp, mf); 2721 DBG_COUNTER_INC(rx_if_input); 2722 } 2723 2724 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2725 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2726 2727 /* 2728 * Flush any outstanding LRO work 2729 */ 2730 #if defined(INET6) || defined(INET) 2731 tcp_lro_flush_all(&rxq->ifr_lc); 2732 #endif 2733 if (avail) 2734 return true; 2735 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2736 err: 2737 STATE_LOCK(ctx); 2738 ctx->ifc_flags |= IFC_DO_RESET; 2739 iflib_admin_intr_deferred(ctx); 2740 STATE_UNLOCK(ctx); 2741 return (false); 2742 } 2743 2744 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2745 static inline qidx_t 2746 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2747 { 2748 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2749 qidx_t minthresh = txq->ift_size / 8; 2750 if (in_use > 4*minthresh) 2751 return (notify_count); 2752 if (in_use > 2*minthresh) 2753 return (notify_count >> 1); 2754 if (in_use > minthresh) 2755 return (notify_count >> 3); 2756 return (0); 2757 } 2758 2759 static inline qidx_t 2760 txq_max_rs_deferred(iflib_txq_t txq) 2761 { 2762 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2763 qidx_t minthresh = txq->ift_size / 8; 2764 if (txq->ift_in_use > 4*minthresh) 2765 return (notify_count); 2766 if (txq->ift_in_use > 2*minthresh) 2767 return (notify_count >> 1); 2768 if (txq->ift_in_use > minthresh) 2769 return (notify_count >> 2); 2770 return (2); 2771 } 2772 2773 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2774 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2775 2776 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2777 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2778 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2779 2780 /* forward compatibility for cxgb */ 2781 #define FIRST_QSET(ctx) 0 2782 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2783 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2784 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2785 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2786 2787 /* XXX we should be setting this to something other than zero */ 2788 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2789 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2790 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2791 2792 static inline bool 2793 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2794 { 2795 qidx_t dbval, max; 2796 bool rang; 2797 2798 rang = false; 2799 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2800 if (ring || txq->ift_db_pending >= max) { 2801 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2802 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2803 txq->ift_db_pending = txq->ift_npending = 0; 2804 rang = true; 2805 } 2806 return (rang); 2807 } 2808 2809 #ifdef PKT_DEBUG 2810 static void 2811 print_pkt(if_pkt_info_t pi) 2812 { 2813 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2814 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2815 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2816 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2817 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2818 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2819 } 2820 #endif 2821 2822 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2823 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2824 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2825 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2826 2827 static int 2828 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2829 { 2830 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2831 struct ether_vlan_header *eh; 2832 struct mbuf *m; 2833 2834 m = *mp; 2835 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2836 M_WRITABLE(m) == 0) { 2837 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2838 return (ENOMEM); 2839 } else { 2840 m_freem(*mp); 2841 DBG_COUNTER_INC(tx_frees); 2842 *mp = m; 2843 } 2844 } 2845 2846 /* 2847 * Determine where frame payload starts. 2848 * Jump over vlan headers if already present, 2849 * helpful for QinQ too. 2850 */ 2851 if (__predict_false(m->m_len < sizeof(*eh))) { 2852 txq->ift_pullups++; 2853 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2854 return (ENOMEM); 2855 } 2856 eh = mtod(m, struct ether_vlan_header *); 2857 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2858 pi->ipi_etype = ntohs(eh->evl_proto); 2859 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2860 } else { 2861 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2862 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2863 } 2864 2865 switch (pi->ipi_etype) { 2866 #ifdef INET 2867 case ETHERTYPE_IP: 2868 { 2869 struct mbuf *n; 2870 struct ip *ip = NULL; 2871 struct tcphdr *th = NULL; 2872 int minthlen; 2873 2874 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2875 if (__predict_false(m->m_len < minthlen)) { 2876 /* 2877 * if this code bloat is causing too much of a hit 2878 * move it to a separate function and mark it noinline 2879 */ 2880 if (m->m_len == pi->ipi_ehdrlen) { 2881 n = m->m_next; 2882 MPASS(n); 2883 if (n->m_len >= sizeof(*ip)) { 2884 ip = (struct ip *)n->m_data; 2885 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2886 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2887 } else { 2888 txq->ift_pullups++; 2889 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2890 return (ENOMEM); 2891 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2892 } 2893 } else { 2894 txq->ift_pullups++; 2895 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2896 return (ENOMEM); 2897 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2898 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2899 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2900 } 2901 } else { 2902 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2903 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2904 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2905 } 2906 pi->ipi_ip_hlen = ip->ip_hl << 2; 2907 pi->ipi_ipproto = ip->ip_p; 2908 pi->ipi_flags |= IPI_TX_IPV4; 2909 2910 /* TCP checksum offload may require TCP header length */ 2911 if (IS_TX_OFFLOAD4(pi)) { 2912 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 2913 if (__predict_false(th == NULL)) { 2914 txq->ift_pullups++; 2915 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2916 return (ENOMEM); 2917 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2918 } 2919 pi->ipi_tcp_hflags = th->th_flags; 2920 pi->ipi_tcp_hlen = th->th_off << 2; 2921 pi->ipi_tcp_seq = th->th_seq; 2922 } 2923 if (IS_TSO4(pi)) { 2924 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2925 return (ENXIO); 2926 /* 2927 * TSO always requires hardware checksum offload. 2928 */ 2929 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 2930 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2931 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2932 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2933 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2934 ip->ip_sum = 0; 2935 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2936 } 2937 } 2938 } 2939 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 2940 ip->ip_sum = 0; 2941 2942 break; 2943 } 2944 #endif 2945 #ifdef INET6 2946 case ETHERTYPE_IPV6: 2947 { 2948 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2949 struct tcphdr *th; 2950 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2951 2952 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2953 txq->ift_pullups++; 2954 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2955 return (ENOMEM); 2956 } 2957 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2958 2959 /* XXX-BZ this will go badly in case of ext hdrs. */ 2960 pi->ipi_ipproto = ip6->ip6_nxt; 2961 pi->ipi_flags |= IPI_TX_IPV6; 2962 2963 /* TCP checksum offload may require TCP header length */ 2964 if (IS_TX_OFFLOAD6(pi)) { 2965 if (pi->ipi_ipproto == IPPROTO_TCP) { 2966 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2967 txq->ift_pullups++; 2968 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2969 return (ENOMEM); 2970 } 2971 pi->ipi_tcp_hflags = th->th_flags; 2972 pi->ipi_tcp_hlen = th->th_off << 2; 2973 pi->ipi_tcp_seq = th->th_seq; 2974 } 2975 if (IS_TSO6(pi)) { 2976 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2977 return (ENXIO); 2978 /* 2979 * TSO always requires hardware checksum offload. 2980 */ 2981 pi->ipi_csum_flags |= CSUM_IP6_TCP; 2982 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2983 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2984 } 2985 } 2986 break; 2987 } 2988 #endif 2989 default: 2990 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2991 pi->ipi_ip_hlen = 0; 2992 break; 2993 } 2994 *mp = m; 2995 2996 return (0); 2997 } 2998 2999 /* 3000 * If dodgy hardware rejects the scatter gather chain we've handed it 3001 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3002 * m_defrag'd mbufs 3003 */ 3004 static __noinline struct mbuf * 3005 iflib_remove_mbuf(iflib_txq_t txq) 3006 { 3007 int ntxd, pidx; 3008 struct mbuf *m, **ifsd_m; 3009 bus_dmamap_t *ifsd_map; 3010 3011 ifsd_m = txq->ift_sds.ifsd_m; 3012 ntxd = txq->ift_size; 3013 pidx = txq->ift_pidx & (ntxd - 1); 3014 ifsd_m = txq->ift_sds.ifsd_m; 3015 ifsd_map = txq->ift_sds.ifsd_map; 3016 m = ifsd_m[pidx]; 3017 ifsd_m[pidx] = NULL; 3018 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[pidx]); 3019 #if MEMORY_LOGGING 3020 txq->ift_dequeued++; 3021 #endif 3022 return (m); 3023 } 3024 3025 static inline caddr_t 3026 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3027 { 3028 qidx_t size; 3029 int ntxd; 3030 caddr_t start, end, cur, next; 3031 3032 ntxd = txq->ift_size; 3033 size = txq->ift_txd_size[qid]; 3034 start = txq->ift_ifdi[qid].idi_vaddr; 3035 3036 if (__predict_false(size == 0)) 3037 return (start); 3038 cur = start + size*cidx; 3039 end = start + size*ntxd; 3040 next = CACHE_PTR_NEXT(cur); 3041 return (next < end ? next : start); 3042 } 3043 3044 /* 3045 * Pad an mbuf to ensure a minimum ethernet frame size. 3046 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3047 */ 3048 static __noinline int 3049 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3050 { 3051 /* 3052 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3053 * and ARP message is the smallest common payload I can think of 3054 */ 3055 static char pad[18]; /* just zeros */ 3056 int n; 3057 struct mbuf *new_head; 3058 3059 if (!M_WRITABLE(*m_head)) { 3060 new_head = m_dup(*m_head, M_NOWAIT); 3061 if (new_head == NULL) { 3062 m_freem(*m_head); 3063 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3064 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3065 DBG_COUNTER_INC(tx_frees); 3066 return ENOMEM; 3067 } 3068 m_freem(*m_head); 3069 *m_head = new_head; 3070 } 3071 3072 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3073 n > 0; n -= sizeof(pad)) 3074 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3075 break; 3076 3077 if (n > 0) { 3078 m_freem(*m_head); 3079 device_printf(dev, "cannot pad short frame\n"); 3080 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3081 DBG_COUNTER_INC(tx_frees); 3082 return (ENOBUFS); 3083 } 3084 3085 return 0; 3086 } 3087 3088 static int 3089 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3090 { 3091 if_ctx_t ctx; 3092 if_shared_ctx_t sctx; 3093 if_softc_ctx_t scctx; 3094 bus_dma_segment_t *segs; 3095 struct mbuf *m_head, **ifsd_m; 3096 void *next_txd; 3097 bus_dmamap_t map; 3098 struct if_pkt_info pi; 3099 int remap = 0; 3100 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3101 bus_dma_tag_t desc_tag; 3102 3103 ctx = txq->ift_ctx; 3104 sctx = ctx->ifc_sctx; 3105 scctx = &ctx->ifc_softc_ctx; 3106 segs = txq->ift_segs; 3107 ntxd = txq->ift_size; 3108 m_head = *m_headp; 3109 map = NULL; 3110 3111 /* 3112 * If we're doing TSO the next descriptor to clean may be quite far ahead 3113 */ 3114 cidx = txq->ift_cidx; 3115 pidx = txq->ift_pidx; 3116 if (ctx->ifc_flags & IFC_PREFETCH) { 3117 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3118 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3119 next_txd = calc_next_txd(txq, cidx, 0); 3120 prefetch(next_txd); 3121 } 3122 3123 /* prefetch the next cache line of mbuf pointers and flags */ 3124 prefetch(&txq->ift_sds.ifsd_m[next]); 3125 prefetch(&txq->ift_sds.ifsd_map[next]); 3126 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3127 } 3128 map = txq->ift_sds.ifsd_map[pidx]; 3129 ifsd_m = txq->ift_sds.ifsd_m; 3130 3131 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3132 desc_tag = txq->ift_tso_desc_tag; 3133 max_segs = scctx->isc_tx_tso_segments_max; 3134 MPASS(desc_tag != NULL); 3135 MPASS(max_segs > 0); 3136 } else { 3137 desc_tag = txq->ift_desc_tag; 3138 max_segs = scctx->isc_tx_nsegments; 3139 } 3140 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3141 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3142 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3143 if (err) { 3144 DBG_COUNTER_INC(encap_txd_encap_fail); 3145 return err; 3146 } 3147 } 3148 m_head = *m_headp; 3149 3150 pkt_info_zero(&pi); 3151 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3152 pi.ipi_pidx = pidx; 3153 pi.ipi_qsidx = txq->ift_id; 3154 pi.ipi_len = m_head->m_pkthdr.len; 3155 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3156 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3157 3158 /* deliberate bitwise OR to make one condition */ 3159 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3160 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3161 DBG_COUNTER_INC(encap_txd_encap_fail); 3162 return (err); 3163 } 3164 m_head = *m_headp; 3165 } 3166 3167 retry: 3168 err = bus_dmamap_load_mbuf_sg(desc_tag, map, m_head, segs, &nsegs, 3169 BUS_DMA_NOWAIT); 3170 defrag: 3171 if (__predict_false(err)) { 3172 switch (err) { 3173 case EFBIG: 3174 /* try collapse once and defrag once */ 3175 if (remap == 0) { 3176 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3177 /* try defrag if collapsing fails */ 3178 if (m_head == NULL) 3179 remap++; 3180 } 3181 if (remap == 1) { 3182 txq->ift_mbuf_defrag++; 3183 m_head = m_defrag(*m_headp, M_NOWAIT); 3184 } 3185 remap++; 3186 if (__predict_false(m_head == NULL)) 3187 goto defrag_failed; 3188 *m_headp = m_head; 3189 goto retry; 3190 break; 3191 case ENOMEM: 3192 txq->ift_no_tx_dma_setup++; 3193 break; 3194 default: 3195 txq->ift_no_tx_dma_setup++; 3196 m_freem(*m_headp); 3197 DBG_COUNTER_INC(tx_frees); 3198 *m_headp = NULL; 3199 break; 3200 } 3201 txq->ift_map_failed++; 3202 DBG_COUNTER_INC(encap_load_mbuf_fail); 3203 DBG_COUNTER_INC(encap_txd_encap_fail); 3204 return (err); 3205 } 3206 ifsd_m[pidx] = m_head; 3207 /* 3208 * XXX assumes a 1 to 1 relationship between segments and 3209 * descriptors - this does not hold true on all drivers, e.g. 3210 * cxgb 3211 */ 3212 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3213 txq->ift_no_desc_avail++; 3214 bus_dmamap_unload(desc_tag, map); 3215 DBG_COUNTER_INC(encap_txq_avail_fail); 3216 DBG_COUNTER_INC(encap_txd_encap_fail); 3217 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3218 GROUPTASK_ENQUEUE(&txq->ift_task); 3219 return (ENOBUFS); 3220 } 3221 /* 3222 * On Intel cards we can greatly reduce the number of TX interrupts 3223 * we see by only setting report status on every Nth descriptor. 3224 * However, this also means that the driver will need to keep track 3225 * of the descriptors that RS was set on to check them for the DD bit. 3226 */ 3227 txq->ift_rs_pending += nsegs + 1; 3228 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3229 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3230 pi.ipi_flags |= IPI_TX_INTR; 3231 txq->ift_rs_pending = 0; 3232 } 3233 3234 pi.ipi_segs = segs; 3235 pi.ipi_nsegs = nsegs; 3236 3237 MPASS(pidx >= 0 && pidx < txq->ift_size); 3238 #ifdef PKT_DEBUG 3239 print_pkt(&pi); 3240 #endif 3241 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3242 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3243 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3244 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3245 DBG_COUNTER_INC(tx_encap); 3246 MPASS(pi.ipi_new_pidx < txq->ift_size); 3247 3248 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3249 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3250 ndesc += txq->ift_size; 3251 txq->ift_gen = 1; 3252 } 3253 /* 3254 * drivers can need as many as 3255 * two sentinels 3256 */ 3257 MPASS(ndesc <= pi.ipi_nsegs + 2); 3258 MPASS(pi.ipi_new_pidx != pidx); 3259 MPASS(ndesc > 0); 3260 txq->ift_in_use += ndesc; 3261 3262 /* 3263 * We update the last software descriptor again here because there may 3264 * be a sentinel and/or there may be more mbufs than segments 3265 */ 3266 txq->ift_pidx = pi.ipi_new_pidx; 3267 txq->ift_npending += pi.ipi_ndescs; 3268 } else { 3269 *m_headp = m_head = iflib_remove_mbuf(txq); 3270 if (err == EFBIG) { 3271 txq->ift_txd_encap_efbig++; 3272 if (remap < 2) { 3273 remap = 1; 3274 goto defrag; 3275 } 3276 } 3277 goto defrag_failed; 3278 } 3279 /* 3280 * err can't possibly be non-zero here, so we don't neet to test it 3281 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3282 */ 3283 return (err); 3284 3285 defrag_failed: 3286 txq->ift_mbuf_defrag_failed++; 3287 txq->ift_map_failed++; 3288 m_freem(*m_headp); 3289 DBG_COUNTER_INC(tx_frees); 3290 *m_headp = NULL; 3291 DBG_COUNTER_INC(encap_txd_encap_fail); 3292 return (ENOMEM); 3293 } 3294 3295 static void 3296 iflib_tx_desc_free(iflib_txq_t txq, int n) 3297 { 3298 uint32_t qsize, cidx, mask, gen; 3299 struct mbuf *m, **ifsd_m; 3300 bus_dmamap_t *ifsd_map; 3301 bool do_prefetch; 3302 3303 cidx = txq->ift_cidx; 3304 gen = txq->ift_gen; 3305 qsize = txq->ift_size; 3306 mask = qsize-1; 3307 ifsd_m = txq->ift_sds.ifsd_m; 3308 ifsd_map = txq->ift_sds.ifsd_map; 3309 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3310 3311 while (n-- > 0) { 3312 if (do_prefetch) { 3313 prefetch(ifsd_m[(cidx + 3) & mask]); 3314 prefetch(ifsd_m[(cidx + 4) & mask]); 3315 } 3316 if ((m = ifsd_m[cidx]) != NULL) { 3317 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3318 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3319 /* XXX we don't support any drivers that batch packets yet */ 3320 MPASS(m->m_nextpkt == NULL); 3321 m_freem(m); 3322 ifsd_m[cidx] = NULL; 3323 #if MEMORY_LOGGING 3324 txq->ift_dequeued++; 3325 #endif 3326 DBG_COUNTER_INC(tx_frees); 3327 } 3328 if (__predict_false(++cidx == qsize)) { 3329 cidx = 0; 3330 gen = 0; 3331 } 3332 } 3333 txq->ift_cidx = cidx; 3334 txq->ift_gen = gen; 3335 } 3336 3337 static __inline int 3338 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3339 { 3340 int reclaim; 3341 if_ctx_t ctx = txq->ift_ctx; 3342 3343 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3344 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3345 3346 /* 3347 * Need a rate-limiting check so that this isn't called every time 3348 */ 3349 iflib_tx_credits_update(ctx, txq); 3350 reclaim = DESC_RECLAIMABLE(txq); 3351 3352 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3353 #ifdef INVARIANTS 3354 if (iflib_verbose_debug) { 3355 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3356 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3357 reclaim, thresh); 3358 3359 } 3360 #endif 3361 return (0); 3362 } 3363 iflib_tx_desc_free(txq, reclaim); 3364 txq->ift_cleaned += reclaim; 3365 txq->ift_in_use -= reclaim; 3366 3367 return (reclaim); 3368 } 3369 3370 static struct mbuf ** 3371 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3372 { 3373 int next, size; 3374 struct mbuf **items; 3375 3376 size = r->size; 3377 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3378 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3379 3380 prefetch(items[(cidx + offset) & (size-1)]); 3381 if (remaining > 1) { 3382 prefetch2cachelines(&items[next]); 3383 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3384 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3385 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3386 } 3387 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3388 } 3389 3390 static void 3391 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3392 { 3393 3394 ifmp_ring_check_drainage(txq->ift_br, budget); 3395 } 3396 3397 static uint32_t 3398 iflib_txq_can_drain(struct ifmp_ring *r) 3399 { 3400 iflib_txq_t txq = r->cookie; 3401 if_ctx_t ctx = txq->ift_ctx; 3402 3403 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3404 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3405 } 3406 3407 static uint32_t 3408 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3409 { 3410 iflib_txq_t txq = r->cookie; 3411 if_ctx_t ctx = txq->ift_ctx; 3412 struct ifnet *ifp = ctx->ifc_ifp; 3413 struct mbuf **mp, *m; 3414 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3415 int reclaimed, err, in_use_prev, desc_used; 3416 bool do_prefetch, ring, rang; 3417 3418 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3419 !LINK_ACTIVE(ctx))) { 3420 DBG_COUNTER_INC(txq_drain_notready); 3421 return (0); 3422 } 3423 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3424 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3425 avail = IDXDIFF(pidx, cidx, r->size); 3426 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3427 DBG_COUNTER_INC(txq_drain_flushing); 3428 for (i = 0; i < avail; i++) { 3429 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3430 m_free(r->items[(cidx + i) & (r->size-1)]); 3431 r->items[(cidx + i) & (r->size-1)] = NULL; 3432 } 3433 return (avail); 3434 } 3435 3436 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3437 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3438 CALLOUT_LOCK(txq); 3439 callout_stop(&txq->ift_timer); 3440 CALLOUT_UNLOCK(txq); 3441 DBG_COUNTER_INC(txq_drain_oactive); 3442 return (0); 3443 } 3444 if (reclaimed) 3445 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3446 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3447 count = MIN(avail, TX_BATCH_SIZE); 3448 #ifdef INVARIANTS 3449 if (iflib_verbose_debug) 3450 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3451 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3452 #endif 3453 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3454 avail = TXQ_AVAIL(txq); 3455 err = 0; 3456 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3457 int rem = do_prefetch ? count - i : 0; 3458 3459 mp = _ring_peek_one(r, cidx, i, rem); 3460 MPASS(mp != NULL && *mp != NULL); 3461 if (__predict_false(*mp == (struct mbuf *)txq)) { 3462 consumed++; 3463 reclaimed++; 3464 continue; 3465 } 3466 in_use_prev = txq->ift_in_use; 3467 err = iflib_encap(txq, mp); 3468 if (__predict_false(err)) { 3469 /* no room - bail out */ 3470 if (err == ENOBUFS) 3471 break; 3472 consumed++; 3473 /* we can't send this packet - skip it */ 3474 continue; 3475 } 3476 consumed++; 3477 pkt_sent++; 3478 m = *mp; 3479 DBG_COUNTER_INC(tx_sent); 3480 bytes_sent += m->m_pkthdr.len; 3481 mcast_sent += !!(m->m_flags & M_MCAST); 3482 avail = TXQ_AVAIL(txq); 3483 3484 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3485 desc_used += (txq->ift_in_use - in_use_prev); 3486 ETHER_BPF_MTAP(ifp, m); 3487 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3488 break; 3489 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3490 } 3491 3492 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3493 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3494 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3495 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3496 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3497 if (mcast_sent) 3498 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3499 #ifdef INVARIANTS 3500 if (iflib_verbose_debug) 3501 printf("consumed=%d\n", consumed); 3502 #endif 3503 return (consumed); 3504 } 3505 3506 static uint32_t 3507 iflib_txq_drain_always(struct ifmp_ring *r) 3508 { 3509 return (1); 3510 } 3511 3512 static uint32_t 3513 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3514 { 3515 int i, avail; 3516 struct mbuf **mp; 3517 iflib_txq_t txq; 3518 3519 txq = r->cookie; 3520 3521 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3522 CALLOUT_LOCK(txq); 3523 callout_stop(&txq->ift_timer); 3524 CALLOUT_UNLOCK(txq); 3525 3526 avail = IDXDIFF(pidx, cidx, r->size); 3527 for (i = 0; i < avail; i++) { 3528 mp = _ring_peek_one(r, cidx, i, avail - i); 3529 if (__predict_false(*mp == (struct mbuf *)txq)) 3530 continue; 3531 m_freem(*mp); 3532 DBG_COUNTER_INC(tx_frees); 3533 } 3534 MPASS(ifmp_ring_is_stalled(r) == 0); 3535 return (avail); 3536 } 3537 3538 static void 3539 iflib_ifmp_purge(iflib_txq_t txq) 3540 { 3541 struct ifmp_ring *r; 3542 3543 r = txq->ift_br; 3544 r->drain = iflib_txq_drain_free; 3545 r->can_drain = iflib_txq_drain_always; 3546 3547 ifmp_ring_check_drainage(r, r->size); 3548 3549 r->drain = iflib_txq_drain; 3550 r->can_drain = iflib_txq_can_drain; 3551 } 3552 3553 static void 3554 _task_fn_tx(void *context) 3555 { 3556 iflib_txq_t txq = context; 3557 if_ctx_t ctx = txq->ift_ctx; 3558 struct ifnet *ifp = ctx->ifc_ifp; 3559 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3560 3561 #ifdef IFLIB_DIAGNOSTICS 3562 txq->ift_cpu_exec_count[curcpu]++; 3563 #endif 3564 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3565 return; 3566 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3567 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3568 netmap_tx_irq(ifp, txq->ift_id); 3569 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3570 return; 3571 } 3572 #ifdef ALTQ 3573 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3574 iflib_altq_if_start(ifp); 3575 #endif 3576 if (txq->ift_db_pending) 3577 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3578 else if (!abdicate) 3579 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3580 /* 3581 * When abdicating, we always need to check drainage, not just when we don't enqueue 3582 */ 3583 if (abdicate) 3584 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3585 if (ctx->ifc_flags & IFC_LEGACY) 3586 IFDI_INTR_ENABLE(ctx); 3587 else { 3588 #ifdef INVARIANTS 3589 int rc = 3590 #endif 3591 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3592 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3593 } 3594 } 3595 3596 static void 3597 _task_fn_rx(void *context) 3598 { 3599 iflib_rxq_t rxq = context; 3600 if_ctx_t ctx = rxq->ifr_ctx; 3601 bool more; 3602 uint16_t budget; 3603 3604 #ifdef IFLIB_DIAGNOSTICS 3605 rxq->ifr_cpu_exec_count[curcpu]++; 3606 #endif 3607 DBG_COUNTER_INC(task_fn_rxs); 3608 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3609 return; 3610 more = true; 3611 #ifdef DEV_NETMAP 3612 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3613 u_int work = 0; 3614 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3615 more = false; 3616 } 3617 } 3618 #endif 3619 budget = ctx->ifc_sysctl_rx_budget; 3620 if (budget == 0) 3621 budget = 16; /* XXX */ 3622 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3623 if (ctx->ifc_flags & IFC_LEGACY) 3624 IFDI_INTR_ENABLE(ctx); 3625 else { 3626 #ifdef INVARIANTS 3627 int rc = 3628 #endif 3629 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3630 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3631 DBG_COUNTER_INC(rx_intr_enables); 3632 } 3633 } 3634 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3635 return; 3636 if (more) 3637 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3638 } 3639 3640 static void 3641 _task_fn_admin(void *context) 3642 { 3643 if_ctx_t ctx = context; 3644 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3645 iflib_txq_t txq; 3646 int i; 3647 bool oactive, running, do_reset, do_watchdog, in_detach; 3648 uint32_t reset_on = hz / 2; 3649 3650 STATE_LOCK(ctx); 3651 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3652 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3653 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3654 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3655 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3656 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3657 STATE_UNLOCK(ctx); 3658 3659 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3660 return; 3661 if (in_detach) 3662 return; 3663 3664 CTX_LOCK(ctx); 3665 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3666 CALLOUT_LOCK(txq); 3667 callout_stop(&txq->ift_timer); 3668 CALLOUT_UNLOCK(txq); 3669 } 3670 if (do_watchdog) { 3671 ctx->ifc_watchdog_events++; 3672 IFDI_WATCHDOG_RESET(ctx); 3673 } 3674 IFDI_UPDATE_ADMIN_STATUS(ctx); 3675 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3676 #ifdef DEV_NETMAP 3677 reset_on = hz / 2; 3678 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3679 iflib_netmap_timer_adjust(ctx, txq->ift_id, &reset_on); 3680 #endif 3681 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3682 } 3683 IFDI_LINK_INTR_ENABLE(ctx); 3684 if (do_reset) 3685 iflib_if_init_locked(ctx); 3686 CTX_UNLOCK(ctx); 3687 3688 if (LINK_ACTIVE(ctx) == 0) 3689 return; 3690 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3691 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3692 } 3693 3694 3695 static void 3696 _task_fn_iov(void *context) 3697 { 3698 if_ctx_t ctx = context; 3699 3700 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3701 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3702 return; 3703 3704 CTX_LOCK(ctx); 3705 IFDI_VFLR_HANDLE(ctx); 3706 CTX_UNLOCK(ctx); 3707 } 3708 3709 static int 3710 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3711 { 3712 int err; 3713 if_int_delay_info_t info; 3714 if_ctx_t ctx; 3715 3716 info = (if_int_delay_info_t)arg1; 3717 ctx = info->iidi_ctx; 3718 info->iidi_req = req; 3719 info->iidi_oidp = oidp; 3720 CTX_LOCK(ctx); 3721 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3722 CTX_UNLOCK(ctx); 3723 return (err); 3724 } 3725 3726 /********************************************************************* 3727 * 3728 * IFNET FUNCTIONS 3729 * 3730 **********************************************************************/ 3731 3732 static void 3733 iflib_if_init_locked(if_ctx_t ctx) 3734 { 3735 iflib_stop(ctx); 3736 iflib_init_locked(ctx); 3737 } 3738 3739 3740 static void 3741 iflib_if_init(void *arg) 3742 { 3743 if_ctx_t ctx = arg; 3744 3745 CTX_LOCK(ctx); 3746 iflib_if_init_locked(ctx); 3747 CTX_UNLOCK(ctx); 3748 } 3749 3750 static int 3751 iflib_if_transmit(if_t ifp, struct mbuf *m) 3752 { 3753 if_ctx_t ctx = if_getsoftc(ifp); 3754 3755 iflib_txq_t txq; 3756 int err, qidx; 3757 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3758 3759 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3760 DBG_COUNTER_INC(tx_frees); 3761 m_freem(m); 3762 return (ENOBUFS); 3763 } 3764 3765 MPASS(m->m_nextpkt == NULL); 3766 /* ALTQ-enabled interfaces always use queue 0. */ 3767 qidx = 0; 3768 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3769 qidx = QIDX(ctx, m); 3770 /* 3771 * XXX calculate buf_ring based on flowid (divvy up bits?) 3772 */ 3773 txq = &ctx->ifc_txqs[qidx]; 3774 3775 #ifdef DRIVER_BACKPRESSURE 3776 if (txq->ift_closed) { 3777 while (m != NULL) { 3778 next = m->m_nextpkt; 3779 m->m_nextpkt = NULL; 3780 m_freem(m); 3781 DBG_COUNTER_INC(tx_frees); 3782 m = next; 3783 } 3784 return (ENOBUFS); 3785 } 3786 #endif 3787 #ifdef notyet 3788 qidx = count = 0; 3789 mp = marr; 3790 next = m; 3791 do { 3792 count++; 3793 next = next->m_nextpkt; 3794 } while (next != NULL); 3795 3796 if (count > nitems(marr)) 3797 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3798 /* XXX check nextpkt */ 3799 m_freem(m); 3800 /* XXX simplify for now */ 3801 DBG_COUNTER_INC(tx_frees); 3802 return (ENOBUFS); 3803 } 3804 for (next = m, i = 0; next != NULL; i++) { 3805 mp[i] = next; 3806 next = next->m_nextpkt; 3807 mp[i]->m_nextpkt = NULL; 3808 } 3809 #endif 3810 DBG_COUNTER_INC(tx_seen); 3811 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 3812 3813 if (abdicate) 3814 GROUPTASK_ENQUEUE(&txq->ift_task); 3815 if (err) { 3816 if (!abdicate) 3817 GROUPTASK_ENQUEUE(&txq->ift_task); 3818 /* support forthcoming later */ 3819 #ifdef DRIVER_BACKPRESSURE 3820 txq->ift_closed = TRUE; 3821 #endif 3822 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3823 m_freem(m); 3824 DBG_COUNTER_INC(tx_frees); 3825 } 3826 3827 return (err); 3828 } 3829 3830 #ifdef ALTQ 3831 /* 3832 * The overall approach to integrating iflib with ALTQ is to continue to use 3833 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 3834 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 3835 * is redundant/unnecessary, but doing so minimizes the amount of 3836 * ALTQ-specific code required in iflib. It is assumed that the overhead of 3837 * redundantly queueing to an intermediate mp_ring is swamped by the 3838 * performance limitations inherent in using ALTQ. 3839 * 3840 * When ALTQ support is compiled in, all iflib drivers will use a transmit 3841 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 3842 * given interface. If ALTQ is enabled for an interface, then all 3843 * transmitted packets for that interface will be submitted to the ALTQ 3844 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 3845 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 3846 * update stats that the iflib machinery handles, and which is sensitve to 3847 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 3848 * will be installed as the start routine for use by ALTQ facilities that 3849 * need to trigger queue drains on a scheduled basis. 3850 * 3851 */ 3852 static void 3853 iflib_altq_if_start(if_t ifp) 3854 { 3855 struct ifaltq *ifq = &ifp->if_snd; 3856 struct mbuf *m; 3857 3858 IFQ_LOCK(ifq); 3859 IFQ_DEQUEUE_NOLOCK(ifq, m); 3860 while (m != NULL) { 3861 iflib_if_transmit(ifp, m); 3862 IFQ_DEQUEUE_NOLOCK(ifq, m); 3863 } 3864 IFQ_UNLOCK(ifq); 3865 } 3866 3867 static int 3868 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 3869 { 3870 int err; 3871 3872 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 3873 IFQ_ENQUEUE(&ifp->if_snd, m, err); 3874 if (err == 0) 3875 iflib_altq_if_start(ifp); 3876 } else 3877 err = iflib_if_transmit(ifp, m); 3878 3879 return (err); 3880 } 3881 #endif /* ALTQ */ 3882 3883 static void 3884 iflib_if_qflush(if_t ifp) 3885 { 3886 if_ctx_t ctx = if_getsoftc(ifp); 3887 iflib_txq_t txq = ctx->ifc_txqs; 3888 int i; 3889 3890 STATE_LOCK(ctx); 3891 ctx->ifc_flags |= IFC_QFLUSH; 3892 STATE_UNLOCK(ctx); 3893 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3894 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3895 iflib_txq_check_drain(txq, 0); 3896 STATE_LOCK(ctx); 3897 ctx->ifc_flags &= ~IFC_QFLUSH; 3898 STATE_UNLOCK(ctx); 3899 3900 /* 3901 * When ALTQ is enabled, this will also take care of purging the 3902 * ALTQ queue(s). 3903 */ 3904 if_qflush(ifp); 3905 } 3906 3907 3908 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3909 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 3910 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 3911 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM) 3912 3913 static int 3914 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 3915 { 3916 if_ctx_t ctx = if_getsoftc(ifp); 3917 struct ifreq *ifr = (struct ifreq *)data; 3918 #if defined(INET) || defined(INET6) 3919 struct ifaddr *ifa = (struct ifaddr *)data; 3920 #endif 3921 bool avoid_reset = FALSE; 3922 int err = 0, reinit = 0, bits; 3923 3924 switch (command) { 3925 case SIOCSIFADDR: 3926 #ifdef INET 3927 if (ifa->ifa_addr->sa_family == AF_INET) 3928 avoid_reset = TRUE; 3929 #endif 3930 #ifdef INET6 3931 if (ifa->ifa_addr->sa_family == AF_INET6) 3932 avoid_reset = TRUE; 3933 #endif 3934 /* 3935 ** Calling init results in link renegotiation, 3936 ** so we avoid doing it when possible. 3937 */ 3938 if (avoid_reset) { 3939 if_setflagbits(ifp, IFF_UP,0); 3940 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 3941 reinit = 1; 3942 #ifdef INET 3943 if (!(if_getflags(ifp) & IFF_NOARP)) 3944 arp_ifinit(ifp, ifa); 3945 #endif 3946 } else 3947 err = ether_ioctl(ifp, command, data); 3948 break; 3949 case SIOCSIFMTU: 3950 CTX_LOCK(ctx); 3951 if (ifr->ifr_mtu == if_getmtu(ifp)) { 3952 CTX_UNLOCK(ctx); 3953 break; 3954 } 3955 bits = if_getdrvflags(ifp); 3956 /* stop the driver and free any clusters before proceeding */ 3957 iflib_stop(ctx); 3958 3959 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 3960 STATE_LOCK(ctx); 3961 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 3962 ctx->ifc_flags |= IFC_MULTISEG; 3963 else 3964 ctx->ifc_flags &= ~IFC_MULTISEG; 3965 STATE_UNLOCK(ctx); 3966 err = if_setmtu(ifp, ifr->ifr_mtu); 3967 } 3968 iflib_init_locked(ctx); 3969 STATE_LOCK(ctx); 3970 if_setdrvflags(ifp, bits); 3971 STATE_UNLOCK(ctx); 3972 CTX_UNLOCK(ctx); 3973 break; 3974 case SIOCSIFFLAGS: 3975 CTX_LOCK(ctx); 3976 if (if_getflags(ifp) & IFF_UP) { 3977 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3978 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 3979 (IFF_PROMISC | IFF_ALLMULTI)) { 3980 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 3981 } 3982 } else 3983 reinit = 1; 3984 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3985 iflib_stop(ctx); 3986 } 3987 ctx->ifc_if_flags = if_getflags(ifp); 3988 CTX_UNLOCK(ctx); 3989 break; 3990 case SIOCADDMULTI: 3991 case SIOCDELMULTI: 3992 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3993 CTX_LOCK(ctx); 3994 IFDI_INTR_DISABLE(ctx); 3995 IFDI_MULTI_SET(ctx); 3996 IFDI_INTR_ENABLE(ctx); 3997 CTX_UNLOCK(ctx); 3998 } 3999 break; 4000 case SIOCSIFMEDIA: 4001 CTX_LOCK(ctx); 4002 IFDI_MEDIA_SET(ctx); 4003 CTX_UNLOCK(ctx); 4004 /* falls thru */ 4005 case SIOCGIFMEDIA: 4006 case SIOCGIFXMEDIA: 4007 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 4008 break; 4009 case SIOCGI2C: 4010 { 4011 struct ifi2creq i2c; 4012 4013 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4014 if (err != 0) 4015 break; 4016 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4017 err = EINVAL; 4018 break; 4019 } 4020 if (i2c.len > sizeof(i2c.data)) { 4021 err = EINVAL; 4022 break; 4023 } 4024 4025 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4026 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4027 sizeof(i2c)); 4028 break; 4029 } 4030 case SIOCSIFCAP: 4031 { 4032 int mask, setmask, oldmask; 4033 4034 oldmask = if_getcapenable(ifp); 4035 mask = ifr->ifr_reqcap ^ oldmask; 4036 mask &= ctx->ifc_softc_ctx.isc_capabilities; 4037 setmask = 0; 4038 #ifdef TCP_OFFLOAD 4039 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4040 #endif 4041 setmask |= (mask & IFCAP_FLAGS); 4042 setmask |= (mask & IFCAP_WOL); 4043 4044 /* 4045 * If any RX csum has changed, change all the ones that 4046 * are supported by the driver. 4047 */ 4048 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4049 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4050 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4051 } 4052 4053 /* 4054 * want to ensure that traffic has stopped before we change any of the flags 4055 */ 4056 if (setmask) { 4057 CTX_LOCK(ctx); 4058 bits = if_getdrvflags(ifp); 4059 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4060 iflib_stop(ctx); 4061 STATE_LOCK(ctx); 4062 if_togglecapenable(ifp, setmask); 4063 STATE_UNLOCK(ctx); 4064 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4065 iflib_init_locked(ctx); 4066 STATE_LOCK(ctx); 4067 if_setdrvflags(ifp, bits); 4068 STATE_UNLOCK(ctx); 4069 CTX_UNLOCK(ctx); 4070 } 4071 if_vlancap(ifp); 4072 break; 4073 } 4074 case SIOCGPRIVATE_0: 4075 case SIOCSDRVSPEC: 4076 case SIOCGDRVSPEC: 4077 CTX_LOCK(ctx); 4078 err = IFDI_PRIV_IOCTL(ctx, command, data); 4079 CTX_UNLOCK(ctx); 4080 break; 4081 default: 4082 err = ether_ioctl(ifp, command, data); 4083 break; 4084 } 4085 if (reinit) 4086 iflib_if_init(ctx); 4087 return (err); 4088 } 4089 4090 static uint64_t 4091 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4092 { 4093 if_ctx_t ctx = if_getsoftc(ifp); 4094 4095 return (IFDI_GET_COUNTER(ctx, cnt)); 4096 } 4097 4098 /********************************************************************* 4099 * 4100 * OTHER FUNCTIONS EXPORTED TO THE STACK 4101 * 4102 **********************************************************************/ 4103 4104 static void 4105 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4106 { 4107 if_ctx_t ctx = if_getsoftc(ifp); 4108 4109 if ((void *)ctx != arg) 4110 return; 4111 4112 if ((vtag == 0) || (vtag > 4095)) 4113 return; 4114 4115 CTX_LOCK(ctx); 4116 IFDI_VLAN_REGISTER(ctx, vtag); 4117 /* Re-init to load the changes */ 4118 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4119 iflib_if_init_locked(ctx); 4120 CTX_UNLOCK(ctx); 4121 } 4122 4123 static void 4124 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4125 { 4126 if_ctx_t ctx = if_getsoftc(ifp); 4127 4128 if ((void *)ctx != arg) 4129 return; 4130 4131 if ((vtag == 0) || (vtag > 4095)) 4132 return; 4133 4134 CTX_LOCK(ctx); 4135 IFDI_VLAN_UNREGISTER(ctx, vtag); 4136 /* Re-init to load the changes */ 4137 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4138 iflib_if_init_locked(ctx); 4139 CTX_UNLOCK(ctx); 4140 } 4141 4142 static void 4143 iflib_led_func(void *arg, int onoff) 4144 { 4145 if_ctx_t ctx = arg; 4146 4147 CTX_LOCK(ctx); 4148 IFDI_LED_FUNC(ctx, onoff); 4149 CTX_UNLOCK(ctx); 4150 } 4151 4152 /********************************************************************* 4153 * 4154 * BUS FUNCTION DEFINITIONS 4155 * 4156 **********************************************************************/ 4157 4158 int 4159 iflib_device_probe(device_t dev) 4160 { 4161 pci_vendor_info_t *ent; 4162 4163 uint16_t pci_vendor_id, pci_device_id; 4164 uint16_t pci_subvendor_id, pci_subdevice_id; 4165 uint16_t pci_rev_id; 4166 if_shared_ctx_t sctx; 4167 4168 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4169 return (ENOTSUP); 4170 4171 pci_vendor_id = pci_get_vendor(dev); 4172 pci_device_id = pci_get_device(dev); 4173 pci_subvendor_id = pci_get_subvendor(dev); 4174 pci_subdevice_id = pci_get_subdevice(dev); 4175 pci_rev_id = pci_get_revid(dev); 4176 if (sctx->isc_parse_devinfo != NULL) 4177 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4178 4179 ent = sctx->isc_vendor_info; 4180 while (ent->pvi_vendor_id != 0) { 4181 if (pci_vendor_id != ent->pvi_vendor_id) { 4182 ent++; 4183 continue; 4184 } 4185 if ((pci_device_id == ent->pvi_device_id) && 4186 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4187 (ent->pvi_subvendor_id == 0)) && 4188 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4189 (ent->pvi_subdevice_id == 0)) && 4190 ((pci_rev_id == ent->pvi_rev_id) || 4191 (ent->pvi_rev_id == 0))) { 4192 4193 device_set_desc_copy(dev, ent->pvi_name); 4194 /* this needs to be changed to zero if the bus probing code 4195 * ever stops re-probing on best match because the sctx 4196 * may have its values over written by register calls 4197 * in subsequent probes 4198 */ 4199 return (BUS_PROBE_DEFAULT); 4200 } 4201 ent++; 4202 } 4203 return (ENXIO); 4204 } 4205 4206 static void 4207 iflib_reset_qvalues(if_ctx_t ctx) 4208 { 4209 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4210 if_shared_ctx_t sctx = ctx->ifc_sctx; 4211 device_t dev = ctx->ifc_dev; 4212 int i; 4213 4214 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES; 4215 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH; 4216 /* 4217 * XXX sanity check that ntxd & nrxd are a power of 2 4218 */ 4219 if (ctx->ifc_sysctl_ntxqs != 0) 4220 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4221 if (ctx->ifc_sysctl_nrxqs != 0) 4222 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4223 4224 for (i = 0; i < sctx->isc_ntxqs; i++) { 4225 if (ctx->ifc_sysctl_ntxds[i] != 0) 4226 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4227 else 4228 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4229 } 4230 4231 for (i = 0; i < sctx->isc_nrxqs; i++) { 4232 if (ctx->ifc_sysctl_nrxds[i] != 0) 4233 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4234 else 4235 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4236 } 4237 4238 for (i = 0; i < sctx->isc_nrxqs; i++) { 4239 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4240 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4241 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4242 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4243 } 4244 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4245 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4246 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4247 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4248 } 4249 } 4250 4251 for (i = 0; i < sctx->isc_ntxqs; i++) { 4252 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4253 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4254 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4255 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4256 } 4257 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4258 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4259 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4260 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4261 } 4262 } 4263 } 4264 4265 int 4266 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4267 { 4268 int err, rid, msix; 4269 if_ctx_t ctx; 4270 if_t ifp; 4271 if_softc_ctx_t scctx; 4272 int i; 4273 uint16_t main_txq; 4274 uint16_t main_rxq; 4275 4276 4277 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4278 4279 if (sc == NULL) { 4280 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4281 device_set_softc(dev, ctx); 4282 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4283 } 4284 4285 ctx->ifc_sctx = sctx; 4286 ctx->ifc_dev = dev; 4287 ctx->ifc_softc = sc; 4288 4289 if ((err = iflib_register(ctx)) != 0) { 4290 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4291 free(sc, M_IFLIB); 4292 free(ctx, M_IFLIB); 4293 device_printf(dev, "iflib_register failed %d\n", err); 4294 return (err); 4295 } 4296 iflib_add_device_sysctl_pre(ctx); 4297 4298 scctx = &ctx->ifc_softc_ctx; 4299 ifp = ctx->ifc_ifp; 4300 4301 iflib_reset_qvalues(ctx); 4302 CTX_LOCK(ctx); 4303 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4304 CTX_UNLOCK(ctx); 4305 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4306 return (err); 4307 } 4308 _iflib_pre_assert(scctx); 4309 ctx->ifc_txrx = *scctx->isc_txrx; 4310 4311 #ifdef INVARIANTS 4312 MPASS(scctx->isc_capabilities); 4313 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4314 MPASS(scctx->isc_tx_csum_flags); 4315 #endif 4316 4317 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS); 4318 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4319 4320 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4321 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4322 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4323 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4324 4325 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4326 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4327 4328 /* XXX change for per-queue sizes */ 4329 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4330 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4331 for (i = 0; i < sctx->isc_nrxqs; i++) { 4332 if (!powerof2(scctx->isc_nrxd[i])) { 4333 /* round down instead? */ 4334 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4335 err = EINVAL; 4336 goto fail; 4337 } 4338 } 4339 for (i = 0; i < sctx->isc_ntxqs; i++) { 4340 if (!powerof2(scctx->isc_ntxd[i])) { 4341 device_printf(dev, 4342 "# tx descriptors must be a power of 2"); 4343 err = EINVAL; 4344 goto fail; 4345 } 4346 } 4347 4348 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4349 MAX_SINGLE_PACKET_FRACTION) 4350 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4351 MAX_SINGLE_PACKET_FRACTION); 4352 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4353 MAX_SINGLE_PACKET_FRACTION) 4354 scctx->isc_tx_tso_segments_max = max(1, 4355 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4356 4357 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4358 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4359 /* 4360 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4361 * but some MACs do. 4362 */ 4363 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4364 IP_MAXPACKET)); 4365 /* 4366 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4367 * into account. In the worst case, each of these calls will 4368 * add another mbuf and, thus, the requirement for another DMA 4369 * segment. So for best performance, it doesn't make sense to 4370 * advertize a maximum of TSO segments that typically will 4371 * require defragmentation in iflib_encap(). 4372 */ 4373 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4374 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4375 } 4376 if (scctx->isc_rss_table_size == 0) 4377 scctx->isc_rss_table_size = 64; 4378 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4379 4380 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4381 /* XXX format name */ 4382 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4383 4384 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4385 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4386 device_printf(dev, "Unable to fetch CPU list\n"); 4387 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4388 } 4389 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4390 4391 /* 4392 ** Now setup MSI or MSI/X, should 4393 ** return us the number of supported 4394 ** vectors. (Will be 1 for MSI) 4395 */ 4396 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4397 msix = scctx->isc_vectors; 4398 } else if (scctx->isc_msix_bar != 0) 4399 /* 4400 * The simple fact that isc_msix_bar is not 0 does not mean we 4401 * we have a good value there that is known to work. 4402 */ 4403 msix = iflib_msix_init(ctx); 4404 else { 4405 scctx->isc_vectors = 1; 4406 scctx->isc_ntxqsets = 1; 4407 scctx->isc_nrxqsets = 1; 4408 scctx->isc_intr = IFLIB_INTR_LEGACY; 4409 msix = 0; 4410 } 4411 /* Get memory for the station queues */ 4412 if ((err = iflib_queues_alloc(ctx))) { 4413 device_printf(dev, "Unable to allocate queue memory\n"); 4414 goto fail; 4415 } 4416 4417 if ((err = iflib_qset_structures_setup(ctx))) 4418 goto fail_queues; 4419 4420 /* 4421 * Group taskqueues aren't properly set up until SMP is started, 4422 * so we disable interrupts until we can handle them post 4423 * SI_SUB_SMP. 4424 * 4425 * XXX: disabling interrupts doesn't actually work, at least for 4426 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4427 * we do null handling and depend on this not causing too large an 4428 * interrupt storm. 4429 */ 4430 IFDI_INTR_DISABLE(ctx); 4431 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4432 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4433 goto fail_intr_free; 4434 } 4435 if (msix <= 1) { 4436 rid = 0; 4437 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4438 MPASS(msix == 1); 4439 rid = 1; 4440 } 4441 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4442 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4443 goto fail_intr_free; 4444 } 4445 } 4446 4447 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4448 4449 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4450 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4451 goto fail_detach; 4452 } 4453 4454 /* 4455 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4456 * This must appear after the call to ether_ifattach() because 4457 * ether_ifattach() sets if_hdrlen to the default value. 4458 */ 4459 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4460 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4461 4462 if ((err = iflib_netmap_attach(ctx))) { 4463 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4464 goto fail_detach; 4465 } 4466 *ctxp = ctx; 4467 4468 NETDUMP_SET(ctx->ifc_ifp, iflib); 4469 4470 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4471 iflib_add_device_sysctl_post(ctx); 4472 ctx->ifc_flags |= IFC_INIT_DONE; 4473 CTX_UNLOCK(ctx); 4474 return (0); 4475 4476 fail_detach: 4477 ether_ifdetach(ctx->ifc_ifp); 4478 fail_intr_free: 4479 fail_queues: 4480 iflib_tx_structures_free(ctx); 4481 iflib_rx_structures_free(ctx); 4482 fail: 4483 iflib_free_intr_mem(ctx); 4484 IFDI_DETACH(ctx); 4485 CTX_UNLOCK(ctx); 4486 4487 return (err); 4488 } 4489 4490 int 4491 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4492 struct iflib_cloneattach_ctx *clctx) 4493 { 4494 int err; 4495 if_ctx_t ctx; 4496 if_t ifp; 4497 if_softc_ctx_t scctx; 4498 int i; 4499 void *sc; 4500 uint16_t main_txq; 4501 uint16_t main_rxq; 4502 4503 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4504 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4505 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4506 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4507 ctx->ifc_flags |= IFC_PSEUDO; 4508 4509 ctx->ifc_sctx = sctx; 4510 ctx->ifc_softc = sc; 4511 ctx->ifc_dev = dev; 4512 4513 if ((err = iflib_register(ctx)) != 0) { 4514 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4515 free(sc, M_IFLIB); 4516 free(ctx, M_IFLIB); 4517 return (err); 4518 } 4519 iflib_add_device_sysctl_pre(ctx); 4520 4521 scctx = &ctx->ifc_softc_ctx; 4522 ifp = ctx->ifc_ifp; 4523 4524 /* 4525 * XXX sanity check that ntxd & nrxd are a power of 2 4526 */ 4527 iflib_reset_qvalues(ctx); 4528 4529 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4530 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4531 return (err); 4532 } 4533 if (sctx->isc_flags & IFLIB_GEN_MAC) 4534 iflib_gen_mac(ctx); 4535 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4536 clctx->cc_params)) != 0) { 4537 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4538 return (err); 4539 } 4540 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4541 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 4542 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO); 4543 4544 #ifdef INVARIANTS 4545 MPASS(scctx->isc_capabilities); 4546 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4547 MPASS(scctx->isc_tx_csum_flags); 4548 #endif 4549 4550 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4551 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4552 4553 ifp->if_flags |= IFF_NOGROUP; 4554 if (sctx->isc_flags & IFLIB_PSEUDO) { 4555 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4556 4557 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4558 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4559 goto fail_detach; 4560 } 4561 *ctxp = ctx; 4562 4563 /* 4564 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4565 * This must appear after the call to ether_ifattach() because 4566 * ether_ifattach() sets if_hdrlen to the default value. 4567 */ 4568 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4569 if_setifheaderlen(ifp, 4570 sizeof(struct ether_vlan_header)); 4571 4572 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4573 iflib_add_device_sysctl_post(ctx); 4574 ctx->ifc_flags |= IFC_INIT_DONE; 4575 return (0); 4576 } 4577 _iflib_pre_assert(scctx); 4578 ctx->ifc_txrx = *scctx->isc_txrx; 4579 4580 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4581 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4582 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4583 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4584 4585 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4586 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4587 4588 /* XXX change for per-queue sizes */ 4589 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4590 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4591 for (i = 0; i < sctx->isc_nrxqs; i++) { 4592 if (!powerof2(scctx->isc_nrxd[i])) { 4593 /* round down instead? */ 4594 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4595 err = EINVAL; 4596 goto fail; 4597 } 4598 } 4599 for (i = 0; i < sctx->isc_ntxqs; i++) { 4600 if (!powerof2(scctx->isc_ntxd[i])) { 4601 device_printf(dev, 4602 "# tx descriptors must be a power of 2"); 4603 err = EINVAL; 4604 goto fail; 4605 } 4606 } 4607 4608 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4609 MAX_SINGLE_PACKET_FRACTION) 4610 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4611 MAX_SINGLE_PACKET_FRACTION); 4612 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4613 MAX_SINGLE_PACKET_FRACTION) 4614 scctx->isc_tx_tso_segments_max = max(1, 4615 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4616 4617 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4618 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4619 /* 4620 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4621 * but some MACs do. 4622 */ 4623 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4624 IP_MAXPACKET)); 4625 /* 4626 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4627 * into account. In the worst case, each of these calls will 4628 * add another mbuf and, thus, the requirement for another DMA 4629 * segment. So for best performance, it doesn't make sense to 4630 * advertize a maximum of TSO segments that typically will 4631 * require defragmentation in iflib_encap(). 4632 */ 4633 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4634 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4635 } 4636 if (scctx->isc_rss_table_size == 0) 4637 scctx->isc_rss_table_size = 64; 4638 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4639 4640 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4641 /* XXX format name */ 4642 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4643 4644 /* XXX --- can support > 1 -- but keep it simple for now */ 4645 scctx->isc_intr = IFLIB_INTR_LEGACY; 4646 4647 /* Get memory for the station queues */ 4648 if ((err = iflib_queues_alloc(ctx))) { 4649 device_printf(dev, "Unable to allocate queue memory\n"); 4650 goto fail; 4651 } 4652 4653 if ((err = iflib_qset_structures_setup(ctx))) { 4654 device_printf(dev, "qset structure setup failed %d\n", err); 4655 goto fail_queues; 4656 } 4657 4658 /* 4659 * XXX What if anything do we want to do about interrupts? 4660 */ 4661 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4662 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4663 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4664 goto fail_detach; 4665 } 4666 4667 /* 4668 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4669 * This must appear after the call to ether_ifattach() because 4670 * ether_ifattach() sets if_hdrlen to the default value. 4671 */ 4672 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4673 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4674 4675 /* XXX handle more than one queue */ 4676 for (i = 0; i < scctx->isc_nrxqsets; i++) 4677 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4678 4679 *ctxp = ctx; 4680 4681 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4682 iflib_add_device_sysctl_post(ctx); 4683 ctx->ifc_flags |= IFC_INIT_DONE; 4684 return (0); 4685 fail_detach: 4686 ether_ifdetach(ctx->ifc_ifp); 4687 fail_queues: 4688 iflib_tx_structures_free(ctx); 4689 iflib_rx_structures_free(ctx); 4690 fail: 4691 IFDI_DETACH(ctx); 4692 return (err); 4693 } 4694 4695 int 4696 iflib_pseudo_deregister(if_ctx_t ctx) 4697 { 4698 if_t ifp = ctx->ifc_ifp; 4699 iflib_txq_t txq; 4700 iflib_rxq_t rxq; 4701 int i, j; 4702 struct taskqgroup *tqg; 4703 iflib_fl_t fl; 4704 4705 /* Unregister VLAN events */ 4706 if (ctx->ifc_vlan_attach_event != NULL) 4707 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4708 if (ctx->ifc_vlan_detach_event != NULL) 4709 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4710 4711 ether_ifdetach(ifp); 4712 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4713 CTX_LOCK_DESTROY(ctx); 4714 /* XXX drain any dependent tasks */ 4715 tqg = qgroup_if_io_tqg; 4716 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4717 callout_drain(&txq->ift_timer); 4718 if (txq->ift_task.gt_uniq != NULL) 4719 taskqgroup_detach(tqg, &txq->ift_task); 4720 } 4721 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4722 if (rxq->ifr_task.gt_uniq != NULL) 4723 taskqgroup_detach(tqg, &rxq->ifr_task); 4724 4725 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4726 free(fl->ifl_rx_bitmap, M_IFLIB); 4727 } 4728 tqg = qgroup_if_config_tqg; 4729 if (ctx->ifc_admin_task.gt_uniq != NULL) 4730 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4731 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4732 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4733 4734 if_free(ifp); 4735 4736 iflib_tx_structures_free(ctx); 4737 iflib_rx_structures_free(ctx); 4738 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4739 free(ctx->ifc_softc, M_IFLIB); 4740 free(ctx, M_IFLIB); 4741 return (0); 4742 } 4743 4744 int 4745 iflib_device_attach(device_t dev) 4746 { 4747 if_ctx_t ctx; 4748 if_shared_ctx_t sctx; 4749 4750 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4751 return (ENOTSUP); 4752 4753 pci_enable_busmaster(dev); 4754 4755 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4756 } 4757 4758 int 4759 iflib_device_deregister(if_ctx_t ctx) 4760 { 4761 if_t ifp = ctx->ifc_ifp; 4762 iflib_txq_t txq; 4763 iflib_rxq_t rxq; 4764 device_t dev = ctx->ifc_dev; 4765 int i, j; 4766 struct taskqgroup *tqg; 4767 iflib_fl_t fl; 4768 4769 /* Make sure VLANS are not using driver */ 4770 if (if_vlantrunkinuse(ifp)) { 4771 device_printf(dev, "Vlan in use, detach first\n"); 4772 return (EBUSY); 4773 } 4774 #ifdef PCI_IOV 4775 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 4776 device_printf(dev, "SR-IOV in use; detach first.\n"); 4777 return (EBUSY); 4778 } 4779 #endif 4780 4781 STATE_LOCK(ctx); 4782 ctx->ifc_flags |= IFC_IN_DETACH; 4783 STATE_UNLOCK(ctx); 4784 4785 CTX_LOCK(ctx); 4786 iflib_stop(ctx); 4787 CTX_UNLOCK(ctx); 4788 4789 /* Unregister VLAN events */ 4790 if (ctx->ifc_vlan_attach_event != NULL) 4791 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4792 if (ctx->ifc_vlan_detach_event != NULL) 4793 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4794 4795 iflib_netmap_detach(ifp); 4796 ether_ifdetach(ifp); 4797 if (ctx->ifc_led_dev != NULL) 4798 led_destroy(ctx->ifc_led_dev); 4799 /* XXX drain any dependent tasks */ 4800 tqg = qgroup_if_io_tqg; 4801 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4802 callout_drain(&txq->ift_timer); 4803 if (txq->ift_task.gt_uniq != NULL) 4804 taskqgroup_detach(tqg, &txq->ift_task); 4805 } 4806 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4807 if (rxq->ifr_task.gt_uniq != NULL) 4808 taskqgroup_detach(tqg, &rxq->ifr_task); 4809 4810 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4811 free(fl->ifl_rx_bitmap, M_IFLIB); 4812 4813 } 4814 tqg = qgroup_if_config_tqg; 4815 if (ctx->ifc_admin_task.gt_uniq != NULL) 4816 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4817 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4818 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4819 CTX_LOCK(ctx); 4820 IFDI_DETACH(ctx); 4821 CTX_UNLOCK(ctx); 4822 4823 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4824 CTX_LOCK_DESTROY(ctx); 4825 device_set_softc(ctx->ifc_dev, NULL); 4826 iflib_free_intr_mem(ctx); 4827 4828 bus_generic_detach(dev); 4829 if_free(ifp); 4830 4831 iflib_tx_structures_free(ctx); 4832 iflib_rx_structures_free(ctx); 4833 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4834 free(ctx->ifc_softc, M_IFLIB); 4835 STATE_LOCK_DESTROY(ctx); 4836 free(ctx, M_IFLIB); 4837 return (0); 4838 } 4839 4840 static void 4841 iflib_free_intr_mem(if_ctx_t ctx) 4842 { 4843 4844 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4845 pci_release_msi(ctx->ifc_dev); 4846 } 4847 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4848 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4849 } 4850 if (ctx->ifc_msix_mem != NULL) { 4851 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4852 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4853 ctx->ifc_msix_mem = NULL; 4854 } 4855 } 4856 4857 int 4858 iflib_device_detach(device_t dev) 4859 { 4860 if_ctx_t ctx = device_get_softc(dev); 4861 4862 return (iflib_device_deregister(ctx)); 4863 } 4864 4865 int 4866 iflib_device_suspend(device_t dev) 4867 { 4868 if_ctx_t ctx = device_get_softc(dev); 4869 4870 CTX_LOCK(ctx); 4871 IFDI_SUSPEND(ctx); 4872 CTX_UNLOCK(ctx); 4873 4874 return bus_generic_suspend(dev); 4875 } 4876 int 4877 iflib_device_shutdown(device_t dev) 4878 { 4879 if_ctx_t ctx = device_get_softc(dev); 4880 4881 CTX_LOCK(ctx); 4882 IFDI_SHUTDOWN(ctx); 4883 CTX_UNLOCK(ctx); 4884 4885 return bus_generic_suspend(dev); 4886 } 4887 4888 4889 int 4890 iflib_device_resume(device_t dev) 4891 { 4892 if_ctx_t ctx = device_get_softc(dev); 4893 iflib_txq_t txq = ctx->ifc_txqs; 4894 4895 CTX_LOCK(ctx); 4896 IFDI_RESUME(ctx); 4897 iflib_init_locked(ctx); 4898 CTX_UNLOCK(ctx); 4899 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4900 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4901 4902 return (bus_generic_resume(dev)); 4903 } 4904 4905 int 4906 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4907 { 4908 int error; 4909 if_ctx_t ctx = device_get_softc(dev); 4910 4911 CTX_LOCK(ctx); 4912 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4913 CTX_UNLOCK(ctx); 4914 4915 return (error); 4916 } 4917 4918 void 4919 iflib_device_iov_uninit(device_t dev) 4920 { 4921 if_ctx_t ctx = device_get_softc(dev); 4922 4923 CTX_LOCK(ctx); 4924 IFDI_IOV_UNINIT(ctx); 4925 CTX_UNLOCK(ctx); 4926 } 4927 4928 int 4929 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 4930 { 4931 int error; 4932 if_ctx_t ctx = device_get_softc(dev); 4933 4934 CTX_LOCK(ctx); 4935 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 4936 CTX_UNLOCK(ctx); 4937 4938 return (error); 4939 } 4940 4941 /********************************************************************* 4942 * 4943 * MODULE FUNCTION DEFINITIONS 4944 * 4945 **********************************************************************/ 4946 4947 /* 4948 * - Start a fast taskqueue thread for each core 4949 * - Start a taskqueue for control operations 4950 */ 4951 static int 4952 iflib_module_init(void) 4953 { 4954 return (0); 4955 } 4956 4957 static int 4958 iflib_module_event_handler(module_t mod, int what, void *arg) 4959 { 4960 int err; 4961 4962 switch (what) { 4963 case MOD_LOAD: 4964 if ((err = iflib_module_init()) != 0) 4965 return (err); 4966 break; 4967 case MOD_UNLOAD: 4968 return (EBUSY); 4969 default: 4970 return (EOPNOTSUPP); 4971 } 4972 4973 return (0); 4974 } 4975 4976 /********************************************************************* 4977 * 4978 * PUBLIC FUNCTION DEFINITIONS 4979 * ordered as in iflib.h 4980 * 4981 **********************************************************************/ 4982 4983 4984 static void 4985 _iflib_assert(if_shared_ctx_t sctx) 4986 { 4987 MPASS(sctx->isc_tx_maxsize); 4988 MPASS(sctx->isc_tx_maxsegsize); 4989 4990 MPASS(sctx->isc_rx_maxsize); 4991 MPASS(sctx->isc_rx_nsegments); 4992 MPASS(sctx->isc_rx_maxsegsize); 4993 4994 MPASS(sctx->isc_nrxd_min[0]); 4995 MPASS(sctx->isc_nrxd_max[0]); 4996 MPASS(sctx->isc_nrxd_default[0]); 4997 MPASS(sctx->isc_ntxd_min[0]); 4998 MPASS(sctx->isc_ntxd_max[0]); 4999 MPASS(sctx->isc_ntxd_default[0]); 5000 } 5001 5002 static void 5003 _iflib_pre_assert(if_softc_ctx_t scctx) 5004 { 5005 5006 MPASS(scctx->isc_txrx->ift_txd_encap); 5007 MPASS(scctx->isc_txrx->ift_txd_flush); 5008 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5009 MPASS(scctx->isc_txrx->ift_rxd_available); 5010 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5011 MPASS(scctx->isc_txrx->ift_rxd_refill); 5012 MPASS(scctx->isc_txrx->ift_rxd_flush); 5013 } 5014 5015 static int 5016 iflib_register(if_ctx_t ctx) 5017 { 5018 if_shared_ctx_t sctx = ctx->ifc_sctx; 5019 driver_t *driver = sctx->isc_driver; 5020 device_t dev = ctx->ifc_dev; 5021 if_t ifp; 5022 5023 _iflib_assert(sctx); 5024 5025 CTX_LOCK_INIT(ctx); 5026 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5027 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5028 if (ifp == NULL) { 5029 device_printf(dev, "can not allocate ifnet structure\n"); 5030 return (ENOMEM); 5031 } 5032 5033 /* 5034 * Initialize our context's device specific methods 5035 */ 5036 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5037 kobj_class_compile((kobj_class_t) driver); 5038 driver->refs++; 5039 5040 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5041 if_setsoftc(ifp, ctx); 5042 if_setdev(ifp, dev); 5043 if_setinitfn(ifp, iflib_if_init); 5044 if_setioctlfn(ifp, iflib_if_ioctl); 5045 #ifdef ALTQ 5046 if_setstartfn(ifp, iflib_altq_if_start); 5047 if_settransmitfn(ifp, iflib_altq_if_transmit); 5048 if_setsendqready(ifp); 5049 #else 5050 if_settransmitfn(ifp, iflib_if_transmit); 5051 #endif 5052 if_setqflushfn(ifp, iflib_if_qflush); 5053 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5054 5055 ctx->ifc_vlan_attach_event = 5056 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5057 EVENTHANDLER_PRI_FIRST); 5058 ctx->ifc_vlan_detach_event = 5059 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5060 EVENTHANDLER_PRI_FIRST); 5061 5062 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 5063 iflib_media_change, iflib_media_status); 5064 5065 return (0); 5066 } 5067 5068 5069 static int 5070 iflib_queues_alloc(if_ctx_t ctx) 5071 { 5072 if_shared_ctx_t sctx = ctx->ifc_sctx; 5073 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5074 device_t dev = ctx->ifc_dev; 5075 int nrxqsets = scctx->isc_nrxqsets; 5076 int ntxqsets = scctx->isc_ntxqsets; 5077 iflib_txq_t txq; 5078 iflib_rxq_t rxq; 5079 iflib_fl_t fl = NULL; 5080 int i, j, cpu, err, txconf, rxconf; 5081 iflib_dma_info_t ifdip; 5082 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5083 uint32_t *txqsizes = scctx->isc_txqsizes; 5084 uint8_t nrxqs = sctx->isc_nrxqs; 5085 uint8_t ntxqs = sctx->isc_ntxqs; 5086 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5087 caddr_t *vaddrs; 5088 uint64_t *paddrs; 5089 5090 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5091 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5092 5093 /* Allocate the TX ring struct memory */ 5094 if (!(ctx->ifc_txqs = 5095 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5096 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5097 device_printf(dev, "Unable to allocate TX ring memory\n"); 5098 err = ENOMEM; 5099 goto fail; 5100 } 5101 5102 /* Now allocate the RX */ 5103 if (!(ctx->ifc_rxqs = 5104 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5105 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5106 device_printf(dev, "Unable to allocate RX ring memory\n"); 5107 err = ENOMEM; 5108 goto rx_fail; 5109 } 5110 5111 txq = ctx->ifc_txqs; 5112 rxq = ctx->ifc_rxqs; 5113 5114 /* 5115 * XXX handle allocation failure 5116 */ 5117 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5118 /* Set up some basics */ 5119 5120 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 5121 device_printf(dev, "failed to allocate iflib_dma_info\n"); 5122 err = ENOMEM; 5123 goto err_tx_desc; 5124 } 5125 txq->ift_ifdi = ifdip; 5126 for (j = 0; j < ntxqs; j++, ifdip++) { 5127 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 5128 device_printf(dev, "Unable to allocate Descriptor memory\n"); 5129 err = ENOMEM; 5130 goto err_tx_desc; 5131 } 5132 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5133 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5134 } 5135 txq->ift_ctx = ctx; 5136 txq->ift_id = i; 5137 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5138 txq->ift_br_offset = 1; 5139 } else { 5140 txq->ift_br_offset = 0; 5141 } 5142 /* XXX fix this */ 5143 txq->ift_timer.c_cpu = cpu; 5144 5145 if (iflib_txsd_alloc(txq)) { 5146 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5147 err = ENOMEM; 5148 goto err_tx_desc; 5149 } 5150 5151 /* Initialize the TX lock */ 5152 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 5153 device_get_nameunit(dev), txq->ift_id); 5154 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5155 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5156 5157 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 5158 device_get_nameunit(dev), txq->ift_id); 5159 5160 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5161 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5162 if (err) { 5163 /* XXX free any allocated rings */ 5164 device_printf(dev, "Unable to allocate buf_ring\n"); 5165 goto err_tx_desc; 5166 } 5167 } 5168 5169 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5170 /* Set up some basics */ 5171 5172 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 5173 device_printf(dev, "failed to allocate iflib_dma_info\n"); 5174 err = ENOMEM; 5175 goto err_tx_desc; 5176 } 5177 5178 rxq->ifr_ifdi = ifdip; 5179 /* XXX this needs to be changed if #rx queues != #tx queues */ 5180 rxq->ifr_ntxqirq = 1; 5181 rxq->ifr_txqid[0] = i; 5182 for (j = 0; j < nrxqs; j++, ifdip++) { 5183 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 5184 device_printf(dev, "Unable to allocate Descriptor memory\n"); 5185 err = ENOMEM; 5186 goto err_tx_desc; 5187 } 5188 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5189 } 5190 rxq->ifr_ctx = ctx; 5191 rxq->ifr_id = i; 5192 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5193 rxq->ifr_fl_offset = 1; 5194 } else { 5195 rxq->ifr_fl_offset = 0; 5196 } 5197 rxq->ifr_nfl = nfree_lists; 5198 if (!(fl = 5199 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5200 device_printf(dev, "Unable to allocate free list memory\n"); 5201 err = ENOMEM; 5202 goto err_tx_desc; 5203 } 5204 rxq->ifr_fl = fl; 5205 for (j = 0; j < nfree_lists; j++) { 5206 fl[j].ifl_rxq = rxq; 5207 fl[j].ifl_id = j; 5208 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5209 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5210 } 5211 /* Allocate receive buffers for the ring */ 5212 if (iflib_rxsd_alloc(rxq)) { 5213 device_printf(dev, 5214 "Critical Failure setting up receive buffers\n"); 5215 err = ENOMEM; 5216 goto err_rx_desc; 5217 } 5218 5219 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5220 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 5221 } 5222 5223 /* TXQs */ 5224 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5225 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5226 for (i = 0; i < ntxqsets; i++) { 5227 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5228 5229 for (j = 0; j < ntxqs; j++, di++) { 5230 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5231 paddrs[i*ntxqs + j] = di->idi_paddr; 5232 } 5233 } 5234 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5235 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 5236 iflib_tx_structures_free(ctx); 5237 free(vaddrs, M_IFLIB); 5238 free(paddrs, M_IFLIB); 5239 goto err_rx_desc; 5240 } 5241 free(vaddrs, M_IFLIB); 5242 free(paddrs, M_IFLIB); 5243 5244 /* RXQs */ 5245 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5246 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5247 for (i = 0; i < nrxqsets; i++) { 5248 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5249 5250 for (j = 0; j < nrxqs; j++, di++) { 5251 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5252 paddrs[i*nrxqs + j] = di->idi_paddr; 5253 } 5254 } 5255 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5256 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 5257 iflib_tx_structures_free(ctx); 5258 free(vaddrs, M_IFLIB); 5259 free(paddrs, M_IFLIB); 5260 goto err_rx_desc; 5261 } 5262 free(vaddrs, M_IFLIB); 5263 free(paddrs, M_IFLIB); 5264 5265 return (0); 5266 5267 /* XXX handle allocation failure changes */ 5268 err_rx_desc: 5269 err_tx_desc: 5270 rx_fail: 5271 if (ctx->ifc_rxqs != NULL) 5272 free(ctx->ifc_rxqs, M_IFLIB); 5273 ctx->ifc_rxqs = NULL; 5274 if (ctx->ifc_txqs != NULL) 5275 free(ctx->ifc_txqs, M_IFLIB); 5276 ctx->ifc_txqs = NULL; 5277 fail: 5278 return (err); 5279 } 5280 5281 static int 5282 iflib_tx_structures_setup(if_ctx_t ctx) 5283 { 5284 iflib_txq_t txq = ctx->ifc_txqs; 5285 int i; 5286 5287 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5288 iflib_txq_setup(txq); 5289 5290 return (0); 5291 } 5292 5293 static void 5294 iflib_tx_structures_free(if_ctx_t ctx) 5295 { 5296 iflib_txq_t txq = ctx->ifc_txqs; 5297 if_shared_ctx_t sctx = ctx->ifc_sctx; 5298 int i, j; 5299 5300 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5301 iflib_txq_destroy(txq); 5302 for (j = 0; j < sctx->isc_ntxqs; j++) 5303 iflib_dma_free(&txq->ift_ifdi[j]); 5304 } 5305 free(ctx->ifc_txqs, M_IFLIB); 5306 ctx->ifc_txqs = NULL; 5307 IFDI_QUEUES_FREE(ctx); 5308 } 5309 5310 /********************************************************************* 5311 * 5312 * Initialize all receive rings. 5313 * 5314 **********************************************************************/ 5315 static int 5316 iflib_rx_structures_setup(if_ctx_t ctx) 5317 { 5318 iflib_rxq_t rxq = ctx->ifc_rxqs; 5319 int q; 5320 #if defined(INET6) || defined(INET) 5321 int i, err; 5322 #endif 5323 5324 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5325 #if defined(INET6) || defined(INET) 5326 tcp_lro_free(&rxq->ifr_lc); 5327 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5328 TCP_LRO_ENTRIES, min(1024, 5329 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 5330 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 5331 goto fail; 5332 } 5333 rxq->ifr_lro_enabled = TRUE; 5334 #endif 5335 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5336 } 5337 return (0); 5338 #if defined(INET6) || defined(INET) 5339 fail: 5340 /* 5341 * Free RX software descriptors allocated so far, we will only handle 5342 * the rings that completed, the failing case will have 5343 * cleaned up for itself. 'q' failed, so its the terminus. 5344 */ 5345 rxq = ctx->ifc_rxqs; 5346 for (i = 0; i < q; ++i, rxq++) { 5347 iflib_rx_sds_free(rxq); 5348 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5349 } 5350 return (err); 5351 #endif 5352 } 5353 5354 /********************************************************************* 5355 * 5356 * Free all receive rings. 5357 * 5358 **********************************************************************/ 5359 static void 5360 iflib_rx_structures_free(if_ctx_t ctx) 5361 { 5362 iflib_rxq_t rxq = ctx->ifc_rxqs; 5363 5364 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5365 iflib_rx_sds_free(rxq); 5366 } 5367 free(ctx->ifc_rxqs, M_IFLIB); 5368 ctx->ifc_rxqs = NULL; 5369 } 5370 5371 static int 5372 iflib_qset_structures_setup(if_ctx_t ctx) 5373 { 5374 int err; 5375 5376 /* 5377 * It is expected that the caller takes care of freeing queues if this 5378 * fails. 5379 */ 5380 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5381 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5382 return (err); 5383 } 5384 5385 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5386 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5387 5388 return (err); 5389 } 5390 5391 int 5392 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5393 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5394 { 5395 5396 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5397 } 5398 5399 #ifdef SMP 5400 static int 5401 find_nth(if_ctx_t ctx, int qid) 5402 { 5403 cpuset_t cpus; 5404 int i, cpuid, eqid, count; 5405 5406 CPU_COPY(&ctx->ifc_cpus, &cpus); 5407 count = CPU_COUNT(&cpus); 5408 eqid = qid % count; 5409 /* clear up to the qid'th bit */ 5410 for (i = 0; i < eqid; i++) { 5411 cpuid = CPU_FFS(&cpus); 5412 MPASS(cpuid != 0); 5413 CPU_CLR(cpuid-1, &cpus); 5414 } 5415 cpuid = CPU_FFS(&cpus); 5416 MPASS(cpuid != 0); 5417 return (cpuid-1); 5418 } 5419 5420 #ifdef SCHED_ULE 5421 extern struct cpu_group *cpu_top; /* CPU topology */ 5422 5423 static int 5424 find_child_with_core(int cpu, struct cpu_group *grp) 5425 { 5426 int i; 5427 5428 if (grp->cg_children == 0) 5429 return -1; 5430 5431 MPASS(grp->cg_child); 5432 for (i = 0; i < grp->cg_children; i++) { 5433 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5434 return i; 5435 } 5436 5437 return -1; 5438 } 5439 5440 /* 5441 * Find the nth "close" core to the specified core 5442 * "close" is defined as the deepest level that shares 5443 * at least an L2 cache. With threads, this will be 5444 * threads on the same core. If the sahred cache is L3 5445 * or higher, simply returns the same core. 5446 */ 5447 static int 5448 find_close_core(int cpu, int core_offset) 5449 { 5450 struct cpu_group *grp; 5451 int i; 5452 int fcpu; 5453 cpuset_t cs; 5454 5455 grp = cpu_top; 5456 if (grp == NULL) 5457 return cpu; 5458 i = 0; 5459 while ((i = find_child_with_core(cpu, grp)) != -1) { 5460 /* If the child only has one cpu, don't descend */ 5461 if (grp->cg_child[i].cg_count <= 1) 5462 break; 5463 grp = &grp->cg_child[i]; 5464 } 5465 5466 /* If they don't share at least an L2 cache, use the same CPU */ 5467 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5468 return cpu; 5469 5470 /* Now pick one */ 5471 CPU_COPY(&grp->cg_mask, &cs); 5472 5473 /* Add the selected CPU offset to core offset. */ 5474 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5475 if (fcpu - 1 == cpu) 5476 break; 5477 CPU_CLR(fcpu - 1, &cs); 5478 } 5479 MPASS(fcpu); 5480 5481 core_offset += i; 5482 5483 CPU_COPY(&grp->cg_mask, &cs); 5484 for (i = core_offset % grp->cg_count; i > 0; i--) { 5485 MPASS(CPU_FFS(&cs)); 5486 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5487 } 5488 MPASS(CPU_FFS(&cs)); 5489 return CPU_FFS(&cs) - 1; 5490 } 5491 #else 5492 static int 5493 find_close_core(int cpu, int core_offset __unused) 5494 { 5495 return cpu; 5496 } 5497 #endif 5498 5499 static int 5500 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5501 { 5502 switch (type) { 5503 case IFLIB_INTR_TX: 5504 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5505 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5506 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5507 case IFLIB_INTR_RX: 5508 case IFLIB_INTR_RXTX: 5509 /* RX queues get the specified core */ 5510 return qid / CPU_COUNT(&ctx->ifc_cpus); 5511 default: 5512 return -1; 5513 } 5514 } 5515 #else 5516 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5517 #define find_close_core(cpuid, tid) CPU_FIRST() 5518 #define find_nth(ctx, gid) CPU_FIRST() 5519 #endif 5520 5521 /* Just to avoid copy/paste */ 5522 static inline int 5523 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid, 5524 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, const char *name) 5525 { 5526 int cpuid; 5527 int err, tid; 5528 5529 cpuid = find_nth(ctx, qid); 5530 tid = get_core_offset(ctx, type, qid); 5531 MPASS(tid >= 0); 5532 cpuid = find_close_core(cpuid, tid); 5533 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name); 5534 if (err) { 5535 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err); 5536 return (err); 5537 } 5538 #ifdef notyet 5539 if (cpuid > ctx->ifc_cpuid_highest) 5540 ctx->ifc_cpuid_highest = cpuid; 5541 #endif 5542 return 0; 5543 } 5544 5545 int 5546 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5547 iflib_intr_type_t type, driver_filter_t *filter, 5548 void *filter_arg, int qid, const char *name) 5549 { 5550 struct grouptask *gtask; 5551 struct taskqgroup *tqg; 5552 iflib_filter_info_t info; 5553 gtask_fn_t *fn; 5554 int tqrid, err; 5555 driver_filter_t *intr_fast; 5556 void *q; 5557 5558 info = &ctx->ifc_filter_info; 5559 tqrid = rid; 5560 5561 switch (type) { 5562 /* XXX merge tx/rx for netmap? */ 5563 case IFLIB_INTR_TX: 5564 q = &ctx->ifc_txqs[qid]; 5565 info = &ctx->ifc_txqs[qid].ift_filter_info; 5566 gtask = &ctx->ifc_txqs[qid].ift_task; 5567 tqg = qgroup_if_io_tqg; 5568 fn = _task_fn_tx; 5569 intr_fast = iflib_fast_intr; 5570 GROUPTASK_INIT(gtask, 0, fn, q); 5571 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5572 break; 5573 case IFLIB_INTR_RX: 5574 q = &ctx->ifc_rxqs[qid]; 5575 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5576 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5577 tqg = qgroup_if_io_tqg; 5578 fn = _task_fn_rx; 5579 intr_fast = iflib_fast_intr; 5580 GROUPTASK_INIT(gtask, 0, fn, q); 5581 break; 5582 case IFLIB_INTR_RXTX: 5583 q = &ctx->ifc_rxqs[qid]; 5584 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5585 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5586 tqg = qgroup_if_io_tqg; 5587 fn = _task_fn_rx; 5588 intr_fast = iflib_fast_intr_rxtx; 5589 GROUPTASK_INIT(gtask, 0, fn, q); 5590 break; 5591 case IFLIB_INTR_ADMIN: 5592 q = ctx; 5593 tqrid = -1; 5594 info = &ctx->ifc_filter_info; 5595 gtask = &ctx->ifc_admin_task; 5596 tqg = qgroup_if_config_tqg; 5597 fn = _task_fn_admin; 5598 intr_fast = iflib_fast_intr_ctx; 5599 break; 5600 default: 5601 panic("unknown net intr type"); 5602 } 5603 5604 info->ifi_filter = filter; 5605 info->ifi_filter_arg = filter_arg; 5606 info->ifi_task = gtask; 5607 info->ifi_ctx = q; 5608 5609 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5610 if (err != 0) { 5611 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 5612 return (err); 5613 } 5614 if (type == IFLIB_INTR_ADMIN) 5615 return (0); 5616 5617 if (tqrid != -1) { 5618 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name); 5619 if (err) 5620 return (err); 5621 } else { 5622 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5623 } 5624 5625 return (0); 5626 } 5627 5628 void 5629 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 5630 { 5631 struct grouptask *gtask; 5632 struct taskqgroup *tqg; 5633 gtask_fn_t *fn; 5634 void *q; 5635 int irq_num = -1; 5636 int err; 5637 5638 switch (type) { 5639 case IFLIB_INTR_TX: 5640 q = &ctx->ifc_txqs[qid]; 5641 gtask = &ctx->ifc_txqs[qid].ift_task; 5642 tqg = qgroup_if_io_tqg; 5643 fn = _task_fn_tx; 5644 if (irq != NULL) 5645 irq_num = rman_get_start(irq->ii_res); 5646 break; 5647 case IFLIB_INTR_RX: 5648 q = &ctx->ifc_rxqs[qid]; 5649 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5650 tqg = qgroup_if_io_tqg; 5651 fn = _task_fn_rx; 5652 if (irq != NULL) 5653 irq_num = rman_get_start(irq->ii_res); 5654 break; 5655 case IFLIB_INTR_IOV: 5656 q = ctx; 5657 gtask = &ctx->ifc_vflr_task; 5658 tqg = qgroup_if_config_tqg; 5659 fn = _task_fn_iov; 5660 break; 5661 default: 5662 panic("unknown net intr type"); 5663 } 5664 GROUPTASK_INIT(gtask, 0, fn, q); 5665 if (irq_num != -1) { 5666 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name); 5667 if (err) 5668 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5669 } 5670 else { 5671 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5672 } 5673 } 5674 5675 void 5676 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5677 { 5678 if (irq->ii_tag) 5679 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5680 5681 if (irq->ii_res) 5682 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5683 } 5684 5685 static int 5686 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 5687 { 5688 iflib_txq_t txq = ctx->ifc_txqs; 5689 iflib_rxq_t rxq = ctx->ifc_rxqs; 5690 if_irq_t irq = &ctx->ifc_legacy_irq; 5691 iflib_filter_info_t info; 5692 struct grouptask *gtask; 5693 struct taskqgroup *tqg; 5694 gtask_fn_t *fn; 5695 int tqrid; 5696 void *q; 5697 int err; 5698 5699 q = &ctx->ifc_rxqs[0]; 5700 info = &rxq[0].ifr_filter_info; 5701 gtask = &rxq[0].ifr_task; 5702 tqg = qgroup_if_io_tqg; 5703 tqrid = irq->ii_rid = *rid; 5704 fn = _task_fn_rx; 5705 5706 ctx->ifc_flags |= IFC_LEGACY; 5707 info->ifi_filter = filter; 5708 info->ifi_filter_arg = filter_arg; 5709 info->ifi_task = gtask; 5710 info->ifi_ctx = ctx; 5711 5712 /* We allocate a single interrupt resource */ 5713 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5714 return (err); 5715 GROUPTASK_INIT(gtask, 0, fn, q); 5716 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5717 5718 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5719 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx"); 5720 return (0); 5721 } 5722 5723 void 5724 iflib_led_create(if_ctx_t ctx) 5725 { 5726 5727 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5728 device_get_nameunit(ctx->ifc_dev)); 5729 } 5730 5731 void 5732 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5733 { 5734 5735 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5736 } 5737 5738 void 5739 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5740 { 5741 5742 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5743 } 5744 5745 void 5746 iflib_admin_intr_deferred(if_ctx_t ctx) 5747 { 5748 #ifdef INVARIANTS 5749 struct grouptask *gtask; 5750 5751 gtask = &ctx->ifc_admin_task; 5752 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5753 #endif 5754 5755 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5756 } 5757 5758 void 5759 iflib_iov_intr_deferred(if_ctx_t ctx) 5760 { 5761 5762 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5763 } 5764 5765 void 5766 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5767 { 5768 5769 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5770 } 5771 5772 void 5773 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 5774 const char *name) 5775 { 5776 5777 GROUPTASK_INIT(gtask, 0, fn, ctx); 5778 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5779 } 5780 5781 void 5782 iflib_config_gtask_deinit(struct grouptask *gtask) 5783 { 5784 5785 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5786 } 5787 5788 void 5789 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5790 { 5791 if_t ifp = ctx->ifc_ifp; 5792 iflib_txq_t txq = ctx->ifc_txqs; 5793 5794 if_setbaudrate(ifp, baudrate); 5795 if (baudrate >= IF_Gbps(10)) { 5796 STATE_LOCK(ctx); 5797 ctx->ifc_flags |= IFC_PREFETCH; 5798 STATE_UNLOCK(ctx); 5799 } 5800 /* If link down, disable watchdog */ 5801 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5802 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5803 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5804 } 5805 ctx->ifc_link_state = link_state; 5806 if_link_state_change(ifp, link_state); 5807 } 5808 5809 static int 5810 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5811 { 5812 int credits; 5813 #ifdef INVARIANTS 5814 int credits_pre = txq->ift_cidx_processed; 5815 #endif 5816 5817 if (ctx->isc_txd_credits_update == NULL) 5818 return (0); 5819 5820 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5821 return (0); 5822 5823 txq->ift_processed += credits; 5824 txq->ift_cidx_processed += credits; 5825 5826 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5827 if (txq->ift_cidx_processed >= txq->ift_size) 5828 txq->ift_cidx_processed -= txq->ift_size; 5829 return (credits); 5830 } 5831 5832 static int 5833 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5834 { 5835 5836 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5837 budget)); 5838 } 5839 5840 void 5841 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5842 const char *description, if_int_delay_info_t info, 5843 int offset, int value) 5844 { 5845 info->iidi_ctx = ctx; 5846 info->iidi_offset = offset; 5847 info->iidi_value = value; 5848 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5849 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5850 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5851 info, 0, iflib_sysctl_int_delay, "I", description); 5852 } 5853 5854 struct sx * 5855 iflib_ctx_lock_get(if_ctx_t ctx) 5856 { 5857 5858 return (&ctx->ifc_ctx_sx); 5859 } 5860 5861 static int 5862 iflib_msix_init(if_ctx_t ctx) 5863 { 5864 device_t dev = ctx->ifc_dev; 5865 if_shared_ctx_t sctx = ctx->ifc_sctx; 5866 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5867 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5868 int iflib_num_tx_queues, iflib_num_rx_queues; 5869 int err, admincnt, bar; 5870 5871 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 5872 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 5873 5874 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 5875 5876 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5877 admincnt = sctx->isc_admin_intrcnt; 5878 /* Override by tuneable */ 5879 if (scctx->isc_disable_msix) 5880 goto msi; 5881 5882 /* 5883 * bar == -1 => "trust me I know what I'm doing" 5884 * Some drivers are for hardware that is so shoddily 5885 * documented that no one knows which bars are which 5886 * so the developer has to map all bars. This hack 5887 * allows shoddy garbage to use msix in this framework. 5888 */ 5889 if (bar != -1) { 5890 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5891 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5892 if (ctx->ifc_msix_mem == NULL) { 5893 /* May not be enabled */ 5894 device_printf(dev, "Unable to map MSIX table \n"); 5895 goto msi; 5896 } 5897 } 5898 /* First try MSI/X */ 5899 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5900 device_printf(dev, "System has MSIX disabled \n"); 5901 bus_release_resource(dev, SYS_RES_MEMORY, 5902 bar, ctx->ifc_msix_mem); 5903 ctx->ifc_msix_mem = NULL; 5904 goto msi; 5905 } 5906 #if IFLIB_DEBUG 5907 /* use only 1 qset in debug mode */ 5908 queuemsgs = min(msgs - admincnt, 1); 5909 #else 5910 queuemsgs = msgs - admincnt; 5911 #endif 5912 #ifdef RSS 5913 queues = imin(queuemsgs, rss_getnumbuckets()); 5914 #else 5915 queues = queuemsgs; 5916 #endif 5917 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 5918 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 5919 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 5920 #ifdef RSS 5921 /* If we're doing RSS, clamp at the number of RSS buckets */ 5922 if (queues > rss_getnumbuckets()) 5923 queues = rss_getnumbuckets(); 5924 #endif 5925 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 5926 rx_queues = iflib_num_rx_queues; 5927 else 5928 rx_queues = queues; 5929 5930 if (rx_queues > scctx->isc_nrxqsets) 5931 rx_queues = scctx->isc_nrxqsets; 5932 5933 /* 5934 * We want this to be all logical CPUs by default 5935 */ 5936 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 5937 tx_queues = iflib_num_tx_queues; 5938 else 5939 tx_queues = mp_ncpus; 5940 5941 if (tx_queues > scctx->isc_ntxqsets) 5942 tx_queues = scctx->isc_ntxqsets; 5943 5944 if (ctx->ifc_sysctl_qs_eq_override == 0) { 5945 #ifdef INVARIANTS 5946 if (tx_queues != rx_queues) 5947 device_printf(dev, 5948 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 5949 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 5950 #endif 5951 tx_queues = min(rx_queues, tx_queues); 5952 rx_queues = min(rx_queues, tx_queues); 5953 } 5954 5955 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 5956 5957 vectors = rx_queues + admincnt; 5958 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 5959 device_printf(dev, "Using MSIX interrupts with %d vectors\n", vectors); 5960 scctx->isc_vectors = vectors; 5961 scctx->isc_nrxqsets = rx_queues; 5962 scctx->isc_ntxqsets = tx_queues; 5963 scctx->isc_intr = IFLIB_INTR_MSIX; 5964 5965 return (vectors); 5966 } else { 5967 device_printf(dev, 5968 "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 5969 bus_release_resource(dev, SYS_RES_MEMORY, bar, 5970 ctx->ifc_msix_mem); 5971 ctx->ifc_msix_mem = NULL; 5972 } 5973 msi: 5974 vectors = pci_msi_count(dev); 5975 scctx->isc_nrxqsets = 1; 5976 scctx->isc_ntxqsets = 1; 5977 scctx->isc_vectors = vectors; 5978 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 5979 device_printf(dev,"Using an MSI interrupt\n"); 5980 scctx->isc_intr = IFLIB_INTR_MSI; 5981 } else { 5982 scctx->isc_vectors = 1; 5983 device_printf(dev,"Using a Legacy interrupt\n"); 5984 scctx->isc_intr = IFLIB_INTR_LEGACY; 5985 } 5986 5987 return (vectors); 5988 } 5989 5990 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 5991 5992 static int 5993 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 5994 { 5995 int rc; 5996 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 5997 struct sbuf *sb; 5998 const char *ring_state = "UNKNOWN"; 5999 6000 /* XXX needed ? */ 6001 rc = sysctl_wire_old_buffer(req, 0); 6002 MPASS(rc == 0); 6003 if (rc != 0) 6004 return (rc); 6005 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6006 MPASS(sb != NULL); 6007 if (sb == NULL) 6008 return (ENOMEM); 6009 if (state[3] <= 3) 6010 ring_state = ring_states[state[3]]; 6011 6012 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6013 state[0], state[1], state[2], ring_state); 6014 rc = sbuf_finish(sb); 6015 sbuf_delete(sb); 6016 return(rc); 6017 } 6018 6019 enum iflib_ndesc_handler { 6020 IFLIB_NTXD_HANDLER, 6021 IFLIB_NRXD_HANDLER, 6022 }; 6023 6024 static int 6025 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6026 { 6027 if_ctx_t ctx = (void *)arg1; 6028 enum iflib_ndesc_handler type = arg2; 6029 char buf[256] = {0}; 6030 qidx_t *ndesc; 6031 char *p, *next; 6032 int nqs, rc, i; 6033 6034 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 6035 6036 nqs = 8; 6037 switch(type) { 6038 case IFLIB_NTXD_HANDLER: 6039 ndesc = ctx->ifc_sysctl_ntxds; 6040 if (ctx->ifc_sctx) 6041 nqs = ctx->ifc_sctx->isc_ntxqs; 6042 break; 6043 case IFLIB_NRXD_HANDLER: 6044 ndesc = ctx->ifc_sysctl_nrxds; 6045 if (ctx->ifc_sctx) 6046 nqs = ctx->ifc_sctx->isc_nrxqs; 6047 break; 6048 default: 6049 panic("unhandled type"); 6050 } 6051 if (nqs == 0) 6052 nqs = 8; 6053 6054 for (i=0; i<8; i++) { 6055 if (i >= nqs) 6056 break; 6057 if (i) 6058 strcat(buf, ","); 6059 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6060 } 6061 6062 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6063 if (rc || req->newptr == NULL) 6064 return rc; 6065 6066 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6067 i++, p = strsep(&next, " ,")) { 6068 ndesc[i] = strtoul(p, NULL, 10); 6069 } 6070 6071 return(rc); 6072 } 6073 6074 #define NAME_BUFLEN 32 6075 static void 6076 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6077 { 6078 device_t dev = iflib_get_dev(ctx); 6079 struct sysctl_oid_list *child, *oid_list; 6080 struct sysctl_ctx_list *ctx_list; 6081 struct sysctl_oid *node; 6082 6083 ctx_list = device_get_sysctl_ctx(dev); 6084 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6085 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6086 CTLFLAG_RD, NULL, "IFLIB fields"); 6087 oid_list = SYSCTL_CHILDREN(node); 6088 6089 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6090 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 6091 "driver version"); 6092 6093 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6094 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6095 "# of txqs to use, 0 => use default #"); 6096 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6097 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6098 "# of rxqs to use, 0 => use default #"); 6099 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6100 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6101 "permit #txq != #rxq"); 6102 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6103 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6104 "disable MSIX (default 0)"); 6105 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6106 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6107 "set the rx budget"); 6108 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6109 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6110 "cause tx to abdicate instead of running to completion"); 6111 6112 /* XXX change for per-queue sizes */ 6113 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6114 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6115 mp_ndesc_handler, "A", 6116 "list of # of tx descriptors to use, 0 = use default #"); 6117 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6118 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6119 mp_ndesc_handler, "A", 6120 "list of # of rx descriptors to use, 0 = use default #"); 6121 } 6122 6123 static void 6124 iflib_add_device_sysctl_post(if_ctx_t ctx) 6125 { 6126 if_shared_ctx_t sctx = ctx->ifc_sctx; 6127 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6128 device_t dev = iflib_get_dev(ctx); 6129 struct sysctl_oid_list *child; 6130 struct sysctl_ctx_list *ctx_list; 6131 iflib_fl_t fl; 6132 iflib_txq_t txq; 6133 iflib_rxq_t rxq; 6134 int i, j; 6135 char namebuf[NAME_BUFLEN]; 6136 char *qfmt; 6137 struct sysctl_oid *queue_node, *fl_node, *node; 6138 struct sysctl_oid_list *queue_list, *fl_list; 6139 ctx_list = device_get_sysctl_ctx(dev); 6140 6141 node = ctx->ifc_sysctl_node; 6142 child = SYSCTL_CHILDREN(node); 6143 6144 if (scctx->isc_ntxqsets > 100) 6145 qfmt = "txq%03d"; 6146 else if (scctx->isc_ntxqsets > 10) 6147 qfmt = "txq%02d"; 6148 else 6149 qfmt = "txq%d"; 6150 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6151 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6152 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6153 CTLFLAG_RD, NULL, "Queue Name"); 6154 queue_list = SYSCTL_CHILDREN(queue_node); 6155 #if MEMORY_LOGGING 6156 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6157 CTLFLAG_RD, 6158 &txq->ift_dequeued, "total mbufs freed"); 6159 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6160 CTLFLAG_RD, 6161 &txq->ift_enqueued, "total mbufs enqueued"); 6162 #endif 6163 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6164 CTLFLAG_RD, 6165 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6166 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6167 CTLFLAG_RD, 6168 &txq->ift_pullups, "# of times m_pullup was called"); 6169 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6170 CTLFLAG_RD, 6171 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6172 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6173 CTLFLAG_RD, 6174 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6175 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6176 CTLFLAG_RD, 6177 &txq->ift_map_failed, "# of times dma map failed"); 6178 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6179 CTLFLAG_RD, 6180 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6181 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6182 CTLFLAG_RD, 6183 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6184 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6185 CTLFLAG_RD, 6186 &txq->ift_pidx, 1, "Producer Index"); 6187 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6188 CTLFLAG_RD, 6189 &txq->ift_cidx, 1, "Consumer Index"); 6190 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6191 CTLFLAG_RD, 6192 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6193 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6194 CTLFLAG_RD, 6195 &txq->ift_in_use, 1, "descriptors in use"); 6196 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6197 CTLFLAG_RD, 6198 &txq->ift_processed, "descriptors procesed for clean"); 6199 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6200 CTLFLAG_RD, 6201 &txq->ift_cleaned, "total cleaned"); 6202 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6203 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6204 0, mp_ring_state_handler, "A", "soft ring state"); 6205 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6206 CTLFLAG_RD, &txq->ift_br->enqueues, 6207 "# of enqueues to the mp_ring for this queue"); 6208 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6209 CTLFLAG_RD, &txq->ift_br->drops, 6210 "# of drops in the mp_ring for this queue"); 6211 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6212 CTLFLAG_RD, &txq->ift_br->starts, 6213 "# of normal consumer starts in the mp_ring for this queue"); 6214 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6215 CTLFLAG_RD, &txq->ift_br->stalls, 6216 "# of consumer stalls in the mp_ring for this queue"); 6217 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6218 CTLFLAG_RD, &txq->ift_br->restarts, 6219 "# of consumer restarts in the mp_ring for this queue"); 6220 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6221 CTLFLAG_RD, &txq->ift_br->abdications, 6222 "# of consumer abdications in the mp_ring for this queue"); 6223 } 6224 6225 if (scctx->isc_nrxqsets > 100) 6226 qfmt = "rxq%03d"; 6227 else if (scctx->isc_nrxqsets > 10) 6228 qfmt = "rxq%02d"; 6229 else 6230 qfmt = "rxq%d"; 6231 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6232 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6233 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6234 CTLFLAG_RD, NULL, "Queue Name"); 6235 queue_list = SYSCTL_CHILDREN(queue_node); 6236 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6237 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 6238 CTLFLAG_RD, 6239 &rxq->ifr_cq_pidx, 1, "Producer Index"); 6240 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6241 CTLFLAG_RD, 6242 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6243 } 6244 6245 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6246 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6247 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6248 CTLFLAG_RD, NULL, "freelist Name"); 6249 fl_list = SYSCTL_CHILDREN(fl_node); 6250 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6251 CTLFLAG_RD, 6252 &fl->ifl_pidx, 1, "Producer Index"); 6253 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6254 CTLFLAG_RD, 6255 &fl->ifl_cidx, 1, "Consumer Index"); 6256 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6257 CTLFLAG_RD, 6258 &fl->ifl_credits, 1, "credits available"); 6259 #if MEMORY_LOGGING 6260 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6261 CTLFLAG_RD, 6262 &fl->ifl_m_enqueued, "mbufs allocated"); 6263 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6264 CTLFLAG_RD, 6265 &fl->ifl_m_dequeued, "mbufs freed"); 6266 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6267 CTLFLAG_RD, 6268 &fl->ifl_cl_enqueued, "clusters allocated"); 6269 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6270 CTLFLAG_RD, 6271 &fl->ifl_cl_dequeued, "clusters freed"); 6272 #endif 6273 6274 } 6275 } 6276 6277 } 6278 6279 void 6280 iflib_request_reset(if_ctx_t ctx) 6281 { 6282 6283 STATE_LOCK(ctx); 6284 ctx->ifc_flags |= IFC_DO_RESET; 6285 STATE_UNLOCK(ctx); 6286 } 6287 6288 #ifndef __NO_STRICT_ALIGNMENT 6289 static struct mbuf * 6290 iflib_fixup_rx(struct mbuf *m) 6291 { 6292 struct mbuf *n; 6293 6294 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6295 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6296 m->m_data += ETHER_HDR_LEN; 6297 n = m; 6298 } else { 6299 MGETHDR(n, M_NOWAIT, MT_DATA); 6300 if (n == NULL) { 6301 m_freem(m); 6302 return (NULL); 6303 } 6304 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6305 m->m_data += ETHER_HDR_LEN; 6306 m->m_len -= ETHER_HDR_LEN; 6307 n->m_len = ETHER_HDR_LEN; 6308 M_MOVE_PKTHDR(n, m); 6309 n->m_next = m; 6310 } 6311 return (n); 6312 } 6313 #endif 6314 6315 #ifdef NETDUMP 6316 static void 6317 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 6318 { 6319 if_ctx_t ctx; 6320 6321 ctx = if_getsoftc(ifp); 6322 CTX_LOCK(ctx); 6323 *nrxr = NRXQSETS(ctx); 6324 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6325 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6326 CTX_UNLOCK(ctx); 6327 } 6328 6329 static void 6330 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event) 6331 { 6332 if_ctx_t ctx; 6333 if_softc_ctx_t scctx; 6334 iflib_fl_t fl; 6335 iflib_rxq_t rxq; 6336 int i, j; 6337 6338 ctx = if_getsoftc(ifp); 6339 scctx = &ctx->ifc_softc_ctx; 6340 6341 switch (event) { 6342 case NETDUMP_START: 6343 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6344 rxq = &ctx->ifc_rxqs[i]; 6345 for (j = 0; j < rxq->ifr_nfl; j++) { 6346 fl = rxq->ifr_fl; 6347 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6348 } 6349 } 6350 iflib_no_tx_batch = 1; 6351 break; 6352 default: 6353 break; 6354 } 6355 } 6356 6357 static int 6358 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m) 6359 { 6360 if_ctx_t ctx; 6361 iflib_txq_t txq; 6362 int error; 6363 6364 ctx = if_getsoftc(ifp); 6365 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6366 IFF_DRV_RUNNING) 6367 return (EBUSY); 6368 6369 txq = &ctx->ifc_txqs[0]; 6370 error = iflib_encap(txq, &m); 6371 if (error == 0) 6372 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6373 return (error); 6374 } 6375 6376 static int 6377 iflib_netdump_poll(struct ifnet *ifp, int count) 6378 { 6379 if_ctx_t ctx; 6380 if_softc_ctx_t scctx; 6381 iflib_txq_t txq; 6382 int i; 6383 6384 ctx = if_getsoftc(ifp); 6385 scctx = &ctx->ifc_softc_ctx; 6386 6387 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6388 IFF_DRV_RUNNING) 6389 return (EBUSY); 6390 6391 txq = &ctx->ifc_txqs[0]; 6392 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6393 6394 for (i = 0; i < scctx->isc_nrxqsets; i++) 6395 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6396 return (0); 6397 } 6398 #endif /* NETDUMP */ 6399