1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/sockio.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/mutex.h> 44 #include <sys/module.h> 45 #include <sys/kobj.h> 46 #include <sys/rman.h> 47 #include <sys/sbuf.h> 48 #include <sys/smp.h> 49 #include <sys/socket.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/vnet.h> 63 64 #include <netinet/in.h> 65 #include <netinet/in_pcb.h> 66 #include <netinet/tcp_lro.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/if_ether.h> 69 #include <netinet/ip.h> 70 #include <netinet/ip6.h> 71 #include <netinet/tcp.h> 72 #include <netinet/ip_var.h> 73 #include <netinet/netdump/netdump.h> 74 #include <netinet6/ip6_var.h> 75 76 #include <machine/bus.h> 77 #include <machine/in_cksum.h> 78 79 #include <vm/vm.h> 80 #include <vm/pmap.h> 81 82 #include <dev/led/led.h> 83 #include <dev/pci/pcireg.h> 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pci_private.h> 86 87 #include <net/iflib.h> 88 89 #include "ifdi_if.h" 90 91 #if defined(__i386__) || defined(__amd64__) 92 #include <sys/memdesc.h> 93 #include <machine/bus.h> 94 #include <machine/md_var.h> 95 #include <machine/specialreg.h> 96 #include <x86/include/busdma_impl.h> 97 #include <x86/iommu/busdma_dmar.h> 98 #endif 99 100 #include <sys/bitstring.h> 101 /* 102 * enable accounting of every mbuf as it comes in to and goes out of 103 * iflib's software descriptor references 104 */ 105 #define MEMORY_LOGGING 0 106 /* 107 * Enable mbuf vectors for compressing long mbuf chains 108 */ 109 110 /* 111 * NB: 112 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 113 * we prefetch needs to be determined by the time spent in m_free vis a vis 114 * the cost of a prefetch. This will of course vary based on the workload: 115 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 116 * is quite expensive, thus suggesting very little prefetch. 117 * - small packet forwarding which is just returning a single mbuf to 118 * UMA will typically be very fast vis a vis the cost of a memory 119 * access. 120 */ 121 122 123 /* 124 * File organization: 125 * - private structures 126 * - iflib private utility functions 127 * - ifnet functions 128 * - vlan registry and other exported functions 129 * - iflib public core functions 130 * 131 * 132 */ 133 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 134 135 struct iflib_txq; 136 typedef struct iflib_txq *iflib_txq_t; 137 struct iflib_rxq; 138 typedef struct iflib_rxq *iflib_rxq_t; 139 struct iflib_fl; 140 typedef struct iflib_fl *iflib_fl_t; 141 142 struct iflib_ctx; 143 144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 145 146 typedef struct iflib_filter_info { 147 driver_filter_t *ifi_filter; 148 void *ifi_filter_arg; 149 struct grouptask *ifi_task; 150 void *ifi_ctx; 151 } *iflib_filter_info_t; 152 153 struct iflib_ctx { 154 KOBJ_FIELDS; 155 /* 156 * Pointer to hardware driver's softc 157 */ 158 void *ifc_softc; 159 device_t ifc_dev; 160 if_t ifc_ifp; 161 162 cpuset_t ifc_cpus; 163 if_shared_ctx_t ifc_sctx; 164 struct if_softc_ctx ifc_softc_ctx; 165 166 struct sx ifc_ctx_sx; 167 struct mtx ifc_state_mtx; 168 169 uint16_t ifc_nhwtxqs; 170 171 iflib_txq_t ifc_txqs; 172 iflib_rxq_t ifc_rxqs; 173 uint32_t ifc_if_flags; 174 uint32_t ifc_flags; 175 uint32_t ifc_max_fl_buf_size; 176 int ifc_in_detach; 177 178 int ifc_link_state; 179 int ifc_link_irq; 180 int ifc_watchdog_events; 181 struct cdev *ifc_led_dev; 182 struct resource *ifc_msix_mem; 183 184 struct if_irq ifc_legacy_irq; 185 struct grouptask ifc_admin_task; 186 struct grouptask ifc_vflr_task; 187 struct iflib_filter_info ifc_filter_info; 188 struct ifmedia ifc_media; 189 190 struct sysctl_oid *ifc_sysctl_node; 191 uint16_t ifc_sysctl_ntxqs; 192 uint16_t ifc_sysctl_nrxqs; 193 uint16_t ifc_sysctl_qs_eq_override; 194 uint16_t ifc_sysctl_rx_budget; 195 196 qidx_t ifc_sysctl_ntxds[8]; 197 qidx_t ifc_sysctl_nrxds[8]; 198 struct if_txrx ifc_txrx; 199 #define isc_txd_encap ifc_txrx.ift_txd_encap 200 #define isc_txd_flush ifc_txrx.ift_txd_flush 201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 202 #define isc_rxd_available ifc_txrx.ift_rxd_available 203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 209 eventhandler_tag ifc_vlan_attach_event; 210 eventhandler_tag ifc_vlan_detach_event; 211 uint8_t ifc_mac[ETHER_ADDR_LEN]; 212 char ifc_mtx_name[16]; 213 }; 214 215 216 void * 217 iflib_get_softc(if_ctx_t ctx) 218 { 219 220 return (ctx->ifc_softc); 221 } 222 223 device_t 224 iflib_get_dev(if_ctx_t ctx) 225 { 226 227 return (ctx->ifc_dev); 228 } 229 230 if_t 231 iflib_get_ifp(if_ctx_t ctx) 232 { 233 234 return (ctx->ifc_ifp); 235 } 236 237 struct ifmedia * 238 iflib_get_media(if_ctx_t ctx) 239 { 240 241 return (&ctx->ifc_media); 242 } 243 244 void 245 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 246 { 247 248 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 249 } 250 251 if_softc_ctx_t 252 iflib_get_softc_ctx(if_ctx_t ctx) 253 { 254 255 return (&ctx->ifc_softc_ctx); 256 } 257 258 if_shared_ctx_t 259 iflib_get_sctx(if_ctx_t ctx) 260 { 261 262 return (ctx->ifc_sctx); 263 } 264 265 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 266 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 267 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 268 269 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 270 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 271 272 #define RX_SW_DESC_MAP_CREATED (1 << 0) 273 #define TX_SW_DESC_MAP_CREATED (1 << 1) 274 #define RX_SW_DESC_INUSE (1 << 3) 275 #define TX_SW_DESC_MAPPED (1 << 4) 276 277 #define M_TOOBIG M_PROTO1 278 279 typedef struct iflib_sw_rx_desc_array { 280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 281 struct mbuf **ifsd_m; /* pkthdr mbufs */ 282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 283 uint8_t *ifsd_flags; 284 } iflib_rxsd_array_t; 285 286 typedef struct iflib_sw_tx_desc_array { 287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 288 struct mbuf **ifsd_m; /* pkthdr mbufs */ 289 uint8_t *ifsd_flags; 290 } if_txsd_vec_t; 291 292 293 /* magic number that should be high enough for any hardware */ 294 #define IFLIB_MAX_TX_SEGS 128 295 /* bnxt supports 64 with hardware LRO enabled */ 296 #define IFLIB_MAX_RX_SEGS 64 297 #define IFLIB_RX_COPY_THRESH 128 298 #define IFLIB_MAX_RX_REFRESH 32 299 /* The minimum descriptors per second before we start coalescing */ 300 #define IFLIB_MIN_DESC_SEC 16384 301 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 302 #define IFLIB_QUEUE_IDLE 0 303 #define IFLIB_QUEUE_HUNG 1 304 #define IFLIB_QUEUE_WORKING 2 305 /* maximum number of txqs that can share an rx interrupt */ 306 #define IFLIB_MAX_TX_SHARED_INTR 4 307 308 /* this should really scale with ring size - this is a fairly arbitrary value */ 309 #define TX_BATCH_SIZE 32 310 311 #define IFLIB_RESTART_BUDGET 8 312 313 #define IFC_LEGACY 0x001 314 #define IFC_QFLUSH 0x002 315 #define IFC_MULTISEG 0x004 316 #define IFC_DMAR 0x008 317 #define IFC_SC_ALLOCATED 0x010 318 #define IFC_INIT_DONE 0x020 319 #define IFC_PREFETCH 0x040 320 #define IFC_DO_RESET 0x080 321 #define IFC_DO_WATCHDOG 0x100 322 #define IFC_CHECK_HUNG 0x200 323 324 325 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 326 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 327 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 328 struct iflib_txq { 329 qidx_t ift_in_use; 330 qidx_t ift_cidx; 331 qidx_t ift_cidx_processed; 332 qidx_t ift_pidx; 333 uint8_t ift_gen; 334 uint8_t ift_br_offset; 335 uint16_t ift_npending; 336 uint16_t ift_db_pending; 337 uint16_t ift_rs_pending; 338 /* implicit pad */ 339 uint8_t ift_txd_size[8]; 340 uint64_t ift_processed; 341 uint64_t ift_cleaned; 342 uint64_t ift_cleaned_prev; 343 #if MEMORY_LOGGING 344 uint64_t ift_enqueued; 345 uint64_t ift_dequeued; 346 #endif 347 uint64_t ift_no_tx_dma_setup; 348 uint64_t ift_no_desc_avail; 349 uint64_t ift_mbuf_defrag_failed; 350 uint64_t ift_mbuf_defrag; 351 uint64_t ift_map_failed; 352 uint64_t ift_txd_encap_efbig; 353 uint64_t ift_pullups; 354 355 struct mtx ift_mtx; 356 struct mtx ift_db_mtx; 357 358 /* constant values */ 359 if_ctx_t ift_ctx; 360 struct ifmp_ring *ift_br; 361 struct grouptask ift_task; 362 qidx_t ift_size; 363 uint16_t ift_id; 364 struct callout ift_timer; 365 366 if_txsd_vec_t ift_sds; 367 uint8_t ift_qstatus; 368 uint8_t ift_closed; 369 uint8_t ift_update_freq; 370 struct iflib_filter_info ift_filter_info; 371 bus_dma_tag_t ift_desc_tag; 372 bus_dma_tag_t ift_tso_desc_tag; 373 iflib_dma_info_t ift_ifdi; 374 #define MTX_NAME_LEN 16 375 char ift_mtx_name[MTX_NAME_LEN]; 376 char ift_db_mtx_name[MTX_NAME_LEN]; 377 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 378 #ifdef IFLIB_DIAGNOSTICS 379 uint64_t ift_cpu_exec_count[256]; 380 #endif 381 } __aligned(CACHE_LINE_SIZE); 382 383 struct iflib_fl { 384 qidx_t ifl_cidx; 385 qidx_t ifl_pidx; 386 qidx_t ifl_credits; 387 uint8_t ifl_gen; 388 uint8_t ifl_rxd_size; 389 #if MEMORY_LOGGING 390 uint64_t ifl_m_enqueued; 391 uint64_t ifl_m_dequeued; 392 uint64_t ifl_cl_enqueued; 393 uint64_t ifl_cl_dequeued; 394 #endif 395 /* implicit pad */ 396 397 bitstr_t *ifl_rx_bitmap; 398 qidx_t ifl_fragidx; 399 /* constant */ 400 qidx_t ifl_size; 401 uint16_t ifl_buf_size; 402 uint16_t ifl_cltype; 403 uma_zone_t ifl_zone; 404 iflib_rxsd_array_t ifl_sds; 405 iflib_rxq_t ifl_rxq; 406 uint8_t ifl_id; 407 bus_dma_tag_t ifl_desc_tag; 408 iflib_dma_info_t ifl_ifdi; 409 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 410 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 411 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 412 } __aligned(CACHE_LINE_SIZE); 413 414 static inline qidx_t 415 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 416 { 417 qidx_t used; 418 419 if (pidx > cidx) 420 used = pidx - cidx; 421 else if (pidx < cidx) 422 used = size - cidx + pidx; 423 else if (gen == 0 && pidx == cidx) 424 used = 0; 425 else if (gen == 1 && pidx == cidx) 426 used = size; 427 else 428 panic("bad state"); 429 430 return (used); 431 } 432 433 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 434 435 #define IDXDIFF(head, tail, wrap) \ 436 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 437 438 struct iflib_rxq { 439 /* If there is a separate completion queue - 440 * these are the cq cidx and pidx. Otherwise 441 * these are unused. 442 */ 443 qidx_t ifr_size; 444 qidx_t ifr_cq_cidx; 445 qidx_t ifr_cq_pidx; 446 uint8_t ifr_cq_gen; 447 uint8_t ifr_fl_offset; 448 449 if_ctx_t ifr_ctx; 450 iflib_fl_t ifr_fl; 451 uint64_t ifr_rx_irq; 452 uint16_t ifr_id; 453 uint8_t ifr_lro_enabled; 454 uint8_t ifr_nfl; 455 uint8_t ifr_ntxqirq; 456 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 457 struct lro_ctrl ifr_lc; 458 struct grouptask ifr_task; 459 struct iflib_filter_info ifr_filter_info; 460 iflib_dma_info_t ifr_ifdi; 461 462 /* dynamically allocate if any drivers need a value substantially larger than this */ 463 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 464 #ifdef IFLIB_DIAGNOSTICS 465 uint64_t ifr_cpu_exec_count[256]; 466 #endif 467 } __aligned(CACHE_LINE_SIZE); 468 469 typedef struct if_rxsd { 470 caddr_t *ifsd_cl; 471 struct mbuf **ifsd_m; 472 iflib_fl_t ifsd_fl; 473 qidx_t ifsd_cidx; 474 } *if_rxsd_t; 475 476 /* multiple of word size */ 477 #ifdef __LP64__ 478 #define PKT_INFO_SIZE 6 479 #define RXD_INFO_SIZE 5 480 #define PKT_TYPE uint64_t 481 #else 482 #define PKT_INFO_SIZE 11 483 #define RXD_INFO_SIZE 8 484 #define PKT_TYPE uint32_t 485 #endif 486 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 487 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 488 489 typedef struct if_pkt_info_pad { 490 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 491 } *if_pkt_info_pad_t; 492 typedef struct if_rxd_info_pad { 493 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 494 } *if_rxd_info_pad_t; 495 496 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 497 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 498 499 500 static inline void 501 pkt_info_zero(if_pkt_info_t pi) 502 { 503 if_pkt_info_pad_t pi_pad; 504 505 pi_pad = (if_pkt_info_pad_t)pi; 506 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 507 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 508 #ifndef __LP64__ 509 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 510 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 511 #endif 512 } 513 514 static inline void 515 rxd_info_zero(if_rxd_info_t ri) 516 { 517 if_rxd_info_pad_t ri_pad; 518 int i; 519 520 ri_pad = (if_rxd_info_pad_t)ri; 521 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 522 ri_pad->rxd_val[i] = 0; 523 ri_pad->rxd_val[i+1] = 0; 524 ri_pad->rxd_val[i+2] = 0; 525 ri_pad->rxd_val[i+3] = 0; 526 } 527 #ifdef __LP64__ 528 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 529 #endif 530 } 531 532 /* 533 * Only allow a single packet to take up most 1/nth of the tx ring 534 */ 535 #define MAX_SINGLE_PACKET_FRACTION 12 536 #define IF_BAD_DMA (bus_addr_t)-1 537 538 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 539 540 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 541 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 542 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 543 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 544 545 546 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 547 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 548 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 549 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 550 551 552 553 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 554 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 555 556 557 /* Our boot-time initialization hook */ 558 static int iflib_module_event_handler(module_t, int, void *); 559 560 static moduledata_t iflib_moduledata = { 561 "iflib", 562 iflib_module_event_handler, 563 NULL 564 }; 565 566 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 567 MODULE_VERSION(iflib, 1); 568 569 MODULE_DEPEND(iflib, pci, 1, 1, 1); 570 MODULE_DEPEND(iflib, ether, 1, 1, 1); 571 572 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 573 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 574 575 #ifndef IFLIB_DEBUG_COUNTERS 576 #ifdef INVARIANTS 577 #define IFLIB_DEBUG_COUNTERS 1 578 #else 579 #define IFLIB_DEBUG_COUNTERS 0 580 #endif /* !INVARIANTS */ 581 #endif 582 583 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 584 "iflib driver parameters"); 585 586 /* 587 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 588 */ 589 static int iflib_min_tx_latency = 0; 590 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 591 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 592 static int iflib_no_tx_batch = 0; 593 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 594 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 595 596 597 #if IFLIB_DEBUG_COUNTERS 598 599 static int iflib_tx_seen; 600 static int iflib_tx_sent; 601 static int iflib_tx_encap; 602 static int iflib_rx_allocs; 603 static int iflib_fl_refills; 604 static int iflib_fl_refills_large; 605 static int iflib_tx_frees; 606 607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 608 &iflib_tx_seen, 0, "# tx mbufs seen"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 610 &iflib_tx_sent, 0, "# tx mbufs sent"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 612 &iflib_tx_encap, 0, "# tx mbufs encapped"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 614 &iflib_tx_frees, 0, "# tx frees"); 615 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 616 &iflib_rx_allocs, 0, "# rx allocations"); 617 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 618 &iflib_fl_refills, 0, "# refills"); 619 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 620 &iflib_fl_refills_large, 0, "# large refills"); 621 622 623 static int iflib_txq_drain_flushing; 624 static int iflib_txq_drain_oactive; 625 static int iflib_txq_drain_notready; 626 static int iflib_txq_drain_encapfail; 627 628 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 629 &iflib_txq_drain_flushing, 0, "# drain flushes"); 630 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 631 &iflib_txq_drain_oactive, 0, "# drain oactives"); 632 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 633 &iflib_txq_drain_notready, 0, "# drain notready"); 634 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 635 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 636 637 638 static int iflib_encap_load_mbuf_fail; 639 static int iflib_encap_pad_mbuf_fail; 640 static int iflib_encap_txq_avail_fail; 641 static int iflib_encap_txd_encap_fail; 642 643 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 644 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 645 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 646 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 647 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 648 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 649 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 650 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 651 652 static int iflib_task_fn_rxs; 653 static int iflib_rx_intr_enables; 654 static int iflib_fast_intrs; 655 static int iflib_intr_link; 656 static int iflib_intr_msix; 657 static int iflib_rx_unavail; 658 static int iflib_rx_ctx_inactive; 659 static int iflib_rx_zero_len; 660 static int iflib_rx_if_input; 661 static int iflib_rx_mbuf_null; 662 static int iflib_rxd_flush; 663 664 static int iflib_verbose_debug; 665 666 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 667 &iflib_intr_link, 0, "# intr link calls"); 668 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 669 &iflib_intr_msix, 0, "# intr msix calls"); 670 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 671 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 672 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 673 &iflib_rx_intr_enables, 0, "# rx intr enables"); 674 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 675 &iflib_fast_intrs, 0, "# fast_intr calls"); 676 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 677 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 678 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 679 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 680 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 681 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 682 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 683 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 684 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 685 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 686 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 687 &iflib_rxd_flush, 0, "# times rxd_flush called"); 688 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 689 &iflib_verbose_debug, 0, "enable verbose debugging"); 690 691 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 692 static void 693 iflib_debug_reset(void) 694 { 695 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 696 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 697 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 698 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 699 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 700 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 701 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 702 iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 703 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 704 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 705 } 706 707 #else 708 #define DBG_COUNTER_INC(name) 709 static void iflib_debug_reset(void) {} 710 #endif 711 712 713 714 #define IFLIB_DEBUG 0 715 716 static void iflib_tx_structures_free(if_ctx_t ctx); 717 static void iflib_rx_structures_free(if_ctx_t ctx); 718 static int iflib_queues_alloc(if_ctx_t ctx); 719 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 720 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 721 static int iflib_qset_structures_setup(if_ctx_t ctx); 722 static int iflib_msix_init(if_ctx_t ctx); 723 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str); 724 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 725 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 726 static int iflib_register(if_ctx_t); 727 static void iflib_init_locked(if_ctx_t ctx); 728 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 729 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 730 static void iflib_ifmp_purge(iflib_txq_t txq); 731 static void _iflib_pre_assert(if_softc_ctx_t scctx); 732 static void iflib_stop(if_ctx_t ctx); 733 static void iflib_if_init_locked(if_ctx_t ctx); 734 #ifndef __NO_STRICT_ALIGNMENT 735 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 736 #endif 737 738 NETDUMP_DEFINE(iflib); 739 740 #ifdef DEV_NETMAP 741 #include <sys/selinfo.h> 742 #include <net/netmap.h> 743 #include <dev/netmap/netmap_kern.h> 744 745 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 746 747 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 748 749 /* 750 * device-specific sysctl variables: 751 * 752 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 753 * During regular operations the CRC is stripped, but on some 754 * hardware reception of frames not multiple of 64 is slower, 755 * so using crcstrip=0 helps in benchmarks. 756 * 757 * iflib_rx_miss, iflib_rx_miss_bufs: 758 * count packets that might be missed due to lost interrupts. 759 */ 760 SYSCTL_DECL(_dev_netmap); 761 /* 762 * The xl driver by default strips CRCs and we do not override it. 763 */ 764 765 int iflib_crcstrip = 1; 766 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 767 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 768 769 int iflib_rx_miss, iflib_rx_miss_bufs; 770 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 771 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 772 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 773 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 774 775 /* 776 * Register/unregister. We are already under netmap lock. 777 * Only called on the first register or the last unregister. 778 */ 779 static int 780 iflib_netmap_register(struct netmap_adapter *na, int onoff) 781 { 782 struct ifnet *ifp = na->ifp; 783 if_ctx_t ctx = ifp->if_softc; 784 int status; 785 786 CTX_LOCK(ctx); 787 IFDI_INTR_DISABLE(ctx); 788 789 /* Tell the stack that the interface is no longer active */ 790 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 791 792 if (!CTX_IS_VF(ctx)) 793 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 794 795 /* enable or disable flags and callbacks in na and ifp */ 796 if (onoff) { 797 nm_set_native_flags(na); 798 } else { 799 nm_clear_native_flags(na); 800 } 801 iflib_stop(ctx); 802 iflib_init_locked(ctx); 803 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 804 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 805 if (status) 806 nm_clear_native_flags(na); 807 CTX_UNLOCK(ctx); 808 return (status); 809 } 810 811 static int 812 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 813 { 814 struct netmap_adapter *na = kring->na; 815 u_int const lim = kring->nkr_num_slots - 1; 816 u_int head = kring->rhead; 817 struct netmap_ring *ring = kring->ring; 818 bus_dmamap_t *map; 819 struct if_rxd_update iru; 820 if_ctx_t ctx = rxq->ifr_ctx; 821 iflib_fl_t fl = &rxq->ifr_fl[0]; 822 uint32_t refill_pidx, nic_i; 823 824 if (nm_i == head && __predict_true(!init)) 825 return 0; 826 iru_init(&iru, rxq, 0 /* flid */); 827 map = fl->ifl_sds.ifsd_map; 828 refill_pidx = netmap_idx_k2n(kring, nm_i); 829 /* 830 * IMPORTANT: we must leave one free slot in the ring, 831 * so move head back by one unit 832 */ 833 head = nm_prev(head, lim); 834 nic_i = UINT_MAX; 835 while (nm_i != head) { 836 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 837 struct netmap_slot *slot = &ring->slot[nm_i]; 838 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 839 uint32_t nic_i_dma = refill_pidx; 840 nic_i = netmap_idx_k2n(kring, nm_i); 841 842 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 843 844 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 845 return netmap_ring_reinit(kring); 846 847 fl->ifl_vm_addrs[tmp_pidx] = addr; 848 if (__predict_false(init) && map) { 849 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 850 } else if (map && (slot->flags & NS_BUF_CHANGED)) { 851 /* buffer has changed, reload map */ 852 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 853 } 854 slot->flags &= ~NS_BUF_CHANGED; 855 856 nm_i = nm_next(nm_i, lim); 857 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 858 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 859 continue; 860 861 iru.iru_pidx = refill_pidx; 862 iru.iru_count = tmp_pidx+1; 863 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 864 865 refill_pidx = nic_i; 866 if (map == NULL) 867 continue; 868 869 for (int n = 0; n < iru.iru_count; n++) { 870 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma], 871 BUS_DMASYNC_PREREAD); 872 /* XXX - change this to not use the netmap func*/ 873 nic_i_dma = nm_next(nic_i_dma, lim); 874 } 875 } 876 } 877 kring->nr_hwcur = head; 878 879 if (map) 880 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 881 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 882 if (__predict_true(nic_i != UINT_MAX)) 883 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 884 return (0); 885 } 886 887 /* 888 * Reconcile kernel and user view of the transmit ring. 889 * 890 * All information is in the kring. 891 * Userspace wants to send packets up to the one before kring->rhead, 892 * kernel knows kring->nr_hwcur is the first unsent packet. 893 * 894 * Here we push packets out (as many as possible), and possibly 895 * reclaim buffers from previously completed transmission. 896 * 897 * The caller (netmap) guarantees that there is only one instance 898 * running at any time. Any interference with other driver 899 * methods should be handled by the individual drivers. 900 */ 901 static int 902 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 903 { 904 struct netmap_adapter *na = kring->na; 905 struct ifnet *ifp = na->ifp; 906 struct netmap_ring *ring = kring->ring; 907 u_int nm_i; /* index into the netmap ring */ 908 u_int nic_i; /* index into the NIC ring */ 909 u_int n; 910 u_int const lim = kring->nkr_num_slots - 1; 911 u_int const head = kring->rhead; 912 struct if_pkt_info pi; 913 914 /* 915 * interrupts on every tx packet are expensive so request 916 * them every half ring, or where NS_REPORT is set 917 */ 918 u_int report_frequency = kring->nkr_num_slots >> 1; 919 /* device-specific */ 920 if_ctx_t ctx = ifp->if_softc; 921 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 922 923 if (txq->ift_sds.ifsd_map) 924 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 925 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 926 927 928 /* 929 * First part: process new packets to send. 930 * nm_i is the current index in the netmap ring, 931 * nic_i is the corresponding index in the NIC ring. 932 * 933 * If we have packets to send (nm_i != head) 934 * iterate over the netmap ring, fetch length and update 935 * the corresponding slot in the NIC ring. Some drivers also 936 * need to update the buffer's physical address in the NIC slot 937 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 938 * 939 * The netmap_reload_map() calls is especially expensive, 940 * even when (as in this case) the tag is 0, so do only 941 * when the buffer has actually changed. 942 * 943 * If possible do not set the report/intr bit on all slots, 944 * but only a few times per ring or when NS_REPORT is set. 945 * 946 * Finally, on 10G and faster drivers, it might be useful 947 * to prefetch the next slot and txr entry. 948 */ 949 950 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 951 pkt_info_zero(&pi); 952 pi.ipi_segs = txq->ift_segs; 953 pi.ipi_qsidx = kring->ring_id; 954 if (nm_i != head) { /* we have new packets to send */ 955 nic_i = netmap_idx_k2n(kring, nm_i); 956 957 __builtin_prefetch(&ring->slot[nm_i]); 958 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 959 if (txq->ift_sds.ifsd_map) 960 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 961 962 for (n = 0; nm_i != head; n++) { 963 struct netmap_slot *slot = &ring->slot[nm_i]; 964 u_int len = slot->len; 965 uint64_t paddr; 966 void *addr = PNMB(na, slot, &paddr); 967 int flags = (slot->flags & NS_REPORT || 968 nic_i == 0 || nic_i == report_frequency) ? 969 IPI_TX_INTR : 0; 970 971 /* device-specific */ 972 pi.ipi_len = len; 973 pi.ipi_segs[0].ds_addr = paddr; 974 pi.ipi_segs[0].ds_len = len; 975 pi.ipi_nsegs = 1; 976 pi.ipi_ndescs = 0; 977 pi.ipi_pidx = nic_i; 978 pi.ipi_flags = flags; 979 980 /* Fill the slot in the NIC ring. */ 981 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 982 983 /* prefetch for next round */ 984 __builtin_prefetch(&ring->slot[nm_i + 1]); 985 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 986 if (txq->ift_sds.ifsd_map) { 987 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 988 989 NM_CHECK_ADDR_LEN(na, addr, len); 990 991 if (slot->flags & NS_BUF_CHANGED) { 992 /* buffer has changed, reload map */ 993 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 994 } 995 /* make sure changes to the buffer are synced */ 996 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 997 BUS_DMASYNC_PREWRITE); 998 } 999 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1000 nm_i = nm_next(nm_i, lim); 1001 nic_i = nm_next(nic_i, lim); 1002 } 1003 kring->nr_hwcur = head; 1004 1005 /* synchronize the NIC ring */ 1006 if (txq->ift_sds.ifsd_map) 1007 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 1008 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1009 1010 /* (re)start the tx unit up to slot nic_i (excluded) */ 1011 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1012 } 1013 1014 /* 1015 * Second part: reclaim buffers for completed transmissions. 1016 */ 1017 if (iflib_tx_credits_update(ctx, txq)) { 1018 /* some tx completed, increment avail */ 1019 nic_i = txq->ift_cidx_processed; 1020 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1021 } 1022 return (0); 1023 } 1024 1025 /* 1026 * Reconcile kernel and user view of the receive ring. 1027 * Same as for the txsync, this routine must be efficient. 1028 * The caller guarantees a single invocations, but races against 1029 * the rest of the driver should be handled here. 1030 * 1031 * On call, kring->rhead is the first packet that userspace wants 1032 * to keep, and kring->rcur is the wakeup point. 1033 * The kernel has previously reported packets up to kring->rtail. 1034 * 1035 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1036 * of whether or not we received an interrupt. 1037 */ 1038 static int 1039 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1040 { 1041 struct netmap_adapter *na = kring->na; 1042 struct netmap_ring *ring = kring->ring; 1043 uint32_t nm_i; /* index into the netmap ring */ 1044 uint32_t nic_i; /* index into the NIC ring */ 1045 u_int i, n; 1046 u_int const lim = kring->nkr_num_slots - 1; 1047 u_int const head = netmap_idx_n2k(kring, kring->rhead); 1048 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1049 struct if_rxd_info ri; 1050 1051 struct ifnet *ifp = na->ifp; 1052 if_ctx_t ctx = ifp->if_softc; 1053 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1054 iflib_fl_t fl = rxq->ifr_fl; 1055 if (head > lim) 1056 return netmap_ring_reinit(kring); 1057 1058 /* XXX check sync modes */ 1059 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1060 if (fl->ifl_sds.ifsd_map == NULL) 1061 continue; 1062 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 1063 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1064 } 1065 /* 1066 * First part: import newly received packets. 1067 * 1068 * nm_i is the index of the next free slot in the netmap ring, 1069 * nic_i is the index of the next received packet in the NIC ring, 1070 * and they may differ in case if_init() has been called while 1071 * in netmap mode. For the receive ring we have 1072 * 1073 * nic_i = rxr->next_check; 1074 * nm_i = kring->nr_hwtail (previous) 1075 * and 1076 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1077 * 1078 * rxr->next_check is set to 0 on a ring reinit 1079 */ 1080 if (netmap_no_pendintr || force_update) { 1081 int crclen = iflib_crcstrip ? 0 : 4; 1082 int error, avail; 1083 1084 for (i = 0; i < rxq->ifr_nfl; i++) { 1085 fl = &rxq->ifr_fl[i]; 1086 nic_i = fl->ifl_cidx; 1087 nm_i = netmap_idx_n2k(kring, nic_i); 1088 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 1089 for (n = 0; avail > 0; n++, avail--) { 1090 rxd_info_zero(&ri); 1091 ri.iri_frags = rxq->ifr_frags; 1092 ri.iri_qsidx = kring->ring_id; 1093 ri.iri_ifp = ctx->ifc_ifp; 1094 ri.iri_cidx = nic_i; 1095 1096 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1097 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1098 ring->slot[nm_i].flags = 0; 1099 if (fl->ifl_sds.ifsd_map) 1100 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1101 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1102 nm_i = nm_next(nm_i, lim); 1103 nic_i = nm_next(nic_i, lim); 1104 } 1105 if (n) { /* update the state variables */ 1106 if (netmap_no_pendintr && !force_update) { 1107 /* diagnostics */ 1108 iflib_rx_miss ++; 1109 iflib_rx_miss_bufs += n; 1110 } 1111 fl->ifl_cidx = nic_i; 1112 kring->nr_hwtail = netmap_idx_k2n(kring, nm_i); 1113 } 1114 kring->nr_kflags &= ~NKR_PENDINTR; 1115 } 1116 } 1117 /* 1118 * Second part: skip past packets that userspace has released. 1119 * (kring->nr_hwcur to head excluded), 1120 * and make the buffers available for reception. 1121 * As usual nm_i is the index in the netmap ring, 1122 * nic_i is the index in the NIC ring, and 1123 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1124 */ 1125 /* XXX not sure how this will work with multiple free lists */ 1126 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 1127 1128 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1129 } 1130 1131 static void 1132 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1133 { 1134 struct ifnet *ifp = na->ifp; 1135 if_ctx_t ctx = ifp->if_softc; 1136 1137 CTX_LOCK(ctx); 1138 if (onoff) { 1139 IFDI_INTR_ENABLE(ctx); 1140 } else { 1141 IFDI_INTR_DISABLE(ctx); 1142 } 1143 CTX_UNLOCK(ctx); 1144 } 1145 1146 1147 static int 1148 iflib_netmap_attach(if_ctx_t ctx) 1149 { 1150 struct netmap_adapter na; 1151 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1152 1153 bzero(&na, sizeof(na)); 1154 1155 na.ifp = ctx->ifc_ifp; 1156 na.na_flags = NAF_BDG_MAYSLEEP; 1157 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1158 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1159 1160 na.num_tx_desc = scctx->isc_ntxd[0]; 1161 na.num_rx_desc = scctx->isc_nrxd[0]; 1162 na.nm_txsync = iflib_netmap_txsync; 1163 na.nm_rxsync = iflib_netmap_rxsync; 1164 na.nm_register = iflib_netmap_register; 1165 na.nm_intr = iflib_netmap_intr; 1166 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1167 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1168 return (netmap_attach(&na)); 1169 } 1170 1171 static void 1172 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1173 { 1174 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1175 struct netmap_slot *slot; 1176 1177 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1178 if (slot == NULL) 1179 return; 1180 if (txq->ift_sds.ifsd_map == NULL) 1181 return; 1182 1183 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1184 1185 /* 1186 * In netmap mode, set the map for the packet buffer. 1187 * NOTE: Some drivers (not this one) also need to set 1188 * the physical buffer address in the NIC ring. 1189 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1190 * netmap slot index, si 1191 */ 1192 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1193 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1194 } 1195 } 1196 1197 static void 1198 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1199 { 1200 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1201 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1202 struct netmap_slot *slot; 1203 uint32_t nm_i; 1204 1205 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1206 if (slot == NULL) 1207 return; 1208 nm_i = netmap_idx_n2k(kring, 0); 1209 netmap_fl_refill(rxq, kring, nm_i, true); 1210 } 1211 1212 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1213 1214 #else 1215 #define iflib_netmap_txq_init(ctx, txq) 1216 #define iflib_netmap_rxq_init(ctx, rxq) 1217 #define iflib_netmap_detach(ifp) 1218 1219 #define iflib_netmap_attach(ctx) (0) 1220 #define netmap_rx_irq(ifp, qid, budget) (0) 1221 #define netmap_tx_irq(ifp, qid) do {} while (0) 1222 1223 #endif 1224 1225 #if defined(__i386__) || defined(__amd64__) 1226 static __inline void 1227 prefetch(void *x) 1228 { 1229 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1230 } 1231 static __inline void 1232 prefetch2cachelines(void *x) 1233 { 1234 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1235 #if (CACHE_LINE_SIZE < 128) 1236 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1237 #endif 1238 } 1239 #else 1240 #define prefetch(x) 1241 #define prefetch2cachelines(x) 1242 #endif 1243 1244 static void 1245 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1246 { 1247 iflib_fl_t fl; 1248 1249 fl = &rxq->ifr_fl[flid]; 1250 iru->iru_paddrs = fl->ifl_bus_addrs; 1251 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1252 iru->iru_idxs = fl->ifl_rxd_idxs; 1253 iru->iru_qsidx = rxq->ifr_id; 1254 iru->iru_buf_size = fl->ifl_buf_size; 1255 iru->iru_flidx = fl->ifl_id; 1256 } 1257 1258 static void 1259 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1260 { 1261 if (err) 1262 return; 1263 *(bus_addr_t *) arg = segs[0].ds_addr; 1264 } 1265 1266 int 1267 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1268 { 1269 int err; 1270 if_shared_ctx_t sctx = ctx->ifc_sctx; 1271 device_t dev = ctx->ifc_dev; 1272 1273 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1274 1275 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1276 sctx->isc_q_align, 0, /* alignment, bounds */ 1277 BUS_SPACE_MAXADDR, /* lowaddr */ 1278 BUS_SPACE_MAXADDR, /* highaddr */ 1279 NULL, NULL, /* filter, filterarg */ 1280 size, /* maxsize */ 1281 1, /* nsegments */ 1282 size, /* maxsegsize */ 1283 BUS_DMA_ALLOCNOW, /* flags */ 1284 NULL, /* lockfunc */ 1285 NULL, /* lockarg */ 1286 &dma->idi_tag); 1287 if (err) { 1288 device_printf(dev, 1289 "%s: bus_dma_tag_create failed: %d\n", 1290 __func__, err); 1291 goto fail_0; 1292 } 1293 1294 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1295 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1296 if (err) { 1297 device_printf(dev, 1298 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1299 __func__, (uintmax_t)size, err); 1300 goto fail_1; 1301 } 1302 1303 dma->idi_paddr = IF_BAD_DMA; 1304 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1305 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1306 if (err || dma->idi_paddr == IF_BAD_DMA) { 1307 device_printf(dev, 1308 "%s: bus_dmamap_load failed: %d\n", 1309 __func__, err); 1310 goto fail_2; 1311 } 1312 1313 dma->idi_size = size; 1314 return (0); 1315 1316 fail_2: 1317 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1318 fail_1: 1319 bus_dma_tag_destroy(dma->idi_tag); 1320 fail_0: 1321 dma->idi_tag = NULL; 1322 1323 return (err); 1324 } 1325 1326 int 1327 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1328 { 1329 int i, err; 1330 iflib_dma_info_t *dmaiter; 1331 1332 dmaiter = dmalist; 1333 for (i = 0; i < count; i++, dmaiter++) { 1334 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1335 break; 1336 } 1337 if (err) 1338 iflib_dma_free_multi(dmalist, i); 1339 return (err); 1340 } 1341 1342 void 1343 iflib_dma_free(iflib_dma_info_t dma) 1344 { 1345 if (dma->idi_tag == NULL) 1346 return; 1347 if (dma->idi_paddr != IF_BAD_DMA) { 1348 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1349 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1350 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1351 dma->idi_paddr = IF_BAD_DMA; 1352 } 1353 if (dma->idi_vaddr != NULL) { 1354 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1355 dma->idi_vaddr = NULL; 1356 } 1357 bus_dma_tag_destroy(dma->idi_tag); 1358 dma->idi_tag = NULL; 1359 } 1360 1361 void 1362 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1363 { 1364 int i; 1365 iflib_dma_info_t *dmaiter = dmalist; 1366 1367 for (i = 0; i < count; i++, dmaiter++) 1368 iflib_dma_free(*dmaiter); 1369 } 1370 1371 #ifdef EARLY_AP_STARTUP 1372 static const int iflib_started = 1; 1373 #else 1374 /* 1375 * We used to abuse the smp_started flag to decide if the queues have been 1376 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1377 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1378 * is set. Run a SYSINIT() strictly after that to just set a usable 1379 * completion flag. 1380 */ 1381 1382 static int iflib_started; 1383 1384 static void 1385 iflib_record_started(void *arg) 1386 { 1387 iflib_started = 1; 1388 } 1389 1390 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1391 iflib_record_started, NULL); 1392 #endif 1393 1394 static int 1395 iflib_fast_intr(void *arg) 1396 { 1397 iflib_filter_info_t info = arg; 1398 struct grouptask *gtask = info->ifi_task; 1399 if (!iflib_started) 1400 return (FILTER_HANDLED); 1401 1402 DBG_COUNTER_INC(fast_intrs); 1403 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1404 return (FILTER_HANDLED); 1405 1406 GROUPTASK_ENQUEUE(gtask); 1407 return (FILTER_HANDLED); 1408 } 1409 1410 static int 1411 iflib_fast_intr_rxtx(void *arg) 1412 { 1413 iflib_filter_info_t info = arg; 1414 struct grouptask *gtask = info->ifi_task; 1415 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1416 if_ctx_t ctx = NULL;; 1417 int i, cidx; 1418 1419 if (!iflib_started) 1420 return (FILTER_HANDLED); 1421 1422 DBG_COUNTER_INC(fast_intrs); 1423 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1424 return (FILTER_HANDLED); 1425 1426 MPASS(rxq->ifr_ntxqirq); 1427 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1428 qidx_t txqid = rxq->ifr_txqid[i]; 1429 1430 ctx = rxq->ifr_ctx; 1431 1432 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1433 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1434 continue; 1435 } 1436 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1437 } 1438 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1439 cidx = rxq->ifr_cq_cidx; 1440 else 1441 cidx = rxq->ifr_fl[0].ifl_cidx; 1442 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1443 GROUPTASK_ENQUEUE(gtask); 1444 else 1445 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1446 return (FILTER_HANDLED); 1447 } 1448 1449 1450 static int 1451 iflib_fast_intr_ctx(void *arg) 1452 { 1453 iflib_filter_info_t info = arg; 1454 struct grouptask *gtask = info->ifi_task; 1455 1456 if (!iflib_started) 1457 return (FILTER_HANDLED); 1458 1459 DBG_COUNTER_INC(fast_intrs); 1460 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1461 return (FILTER_HANDLED); 1462 1463 GROUPTASK_ENQUEUE(gtask); 1464 return (FILTER_HANDLED); 1465 } 1466 1467 static int 1468 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1469 driver_filter_t filter, driver_intr_t handler, void *arg, 1470 char *name) 1471 { 1472 int rc, flags; 1473 struct resource *res; 1474 void *tag = NULL; 1475 device_t dev = ctx->ifc_dev; 1476 1477 flags = RF_ACTIVE; 1478 if (ctx->ifc_flags & IFC_LEGACY) 1479 flags |= RF_SHAREABLE; 1480 MPASS(rid < 512); 1481 irq->ii_rid = rid; 1482 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1483 if (res == NULL) { 1484 device_printf(dev, 1485 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1486 return (ENOMEM); 1487 } 1488 irq->ii_res = res; 1489 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1490 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1491 filter, handler, arg, &tag); 1492 if (rc != 0) { 1493 device_printf(dev, 1494 "failed to setup interrupt for rid %d, name %s: %d\n", 1495 rid, name ? name : "unknown", rc); 1496 return (rc); 1497 } else if (name) 1498 bus_describe_intr(dev, res, tag, "%s", name); 1499 1500 irq->ii_tag = tag; 1501 return (0); 1502 } 1503 1504 1505 /********************************************************************* 1506 * 1507 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1508 * the information needed to transmit a packet on the wire. This is 1509 * called only once at attach, setup is done every reset. 1510 * 1511 **********************************************************************/ 1512 1513 static int 1514 iflib_txsd_alloc(iflib_txq_t txq) 1515 { 1516 if_ctx_t ctx = txq->ift_ctx; 1517 if_shared_ctx_t sctx = ctx->ifc_sctx; 1518 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1519 device_t dev = ctx->ifc_dev; 1520 int err, nsegments, ntsosegments; 1521 1522 nsegments = scctx->isc_tx_nsegments; 1523 ntsosegments = scctx->isc_tx_tso_segments_max; 1524 MPASS(scctx->isc_ntxd[0] > 0); 1525 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1526 MPASS(nsegments > 0); 1527 MPASS(ntsosegments > 0); 1528 /* 1529 * Setup DMA descriptor areas. 1530 */ 1531 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1532 1, 0, /* alignment, bounds */ 1533 BUS_SPACE_MAXADDR, /* lowaddr */ 1534 BUS_SPACE_MAXADDR, /* highaddr */ 1535 NULL, NULL, /* filter, filterarg */ 1536 sctx->isc_tx_maxsize, /* maxsize */ 1537 nsegments, /* nsegments */ 1538 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1539 0, /* flags */ 1540 NULL, /* lockfunc */ 1541 NULL, /* lockfuncarg */ 1542 &txq->ift_desc_tag))) { 1543 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1544 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1545 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1546 goto fail; 1547 } 1548 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1549 1, 0, /* alignment, bounds */ 1550 BUS_SPACE_MAXADDR, /* lowaddr */ 1551 BUS_SPACE_MAXADDR, /* highaddr */ 1552 NULL, NULL, /* filter, filterarg */ 1553 scctx->isc_tx_tso_size_max, /* maxsize */ 1554 ntsosegments, /* nsegments */ 1555 scctx->isc_tx_tso_segsize_max, /* maxsegsize */ 1556 0, /* flags */ 1557 NULL, /* lockfunc */ 1558 NULL, /* lockfuncarg */ 1559 &txq->ift_tso_desc_tag))) { 1560 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1561 1562 goto fail; 1563 } 1564 if (!(txq->ift_sds.ifsd_flags = 1565 (uint8_t *) malloc(sizeof(uint8_t) * 1566 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1567 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1568 err = ENOMEM; 1569 goto fail; 1570 } 1571 if (!(txq->ift_sds.ifsd_m = 1572 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1573 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1574 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1575 err = ENOMEM; 1576 goto fail; 1577 } 1578 1579 /* Create the descriptor buffer dma maps */ 1580 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1581 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1582 return (0); 1583 1584 if (!(txq->ift_sds.ifsd_map = 1585 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1586 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1587 err = ENOMEM; 1588 goto fail; 1589 } 1590 1591 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1592 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1593 if (err != 0) { 1594 device_printf(dev, "Unable to create TX DMA map\n"); 1595 goto fail; 1596 } 1597 } 1598 #endif 1599 return (0); 1600 fail: 1601 /* We free all, it handles case where we are in the middle */ 1602 iflib_tx_structures_free(ctx); 1603 return (err); 1604 } 1605 1606 static void 1607 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1608 { 1609 bus_dmamap_t map; 1610 1611 map = NULL; 1612 if (txq->ift_sds.ifsd_map != NULL) 1613 map = txq->ift_sds.ifsd_map[i]; 1614 if (map != NULL) { 1615 bus_dmamap_unload(txq->ift_desc_tag, map); 1616 bus_dmamap_destroy(txq->ift_desc_tag, map); 1617 txq->ift_sds.ifsd_map[i] = NULL; 1618 } 1619 } 1620 1621 static void 1622 iflib_txq_destroy(iflib_txq_t txq) 1623 { 1624 if_ctx_t ctx = txq->ift_ctx; 1625 1626 for (int i = 0; i < txq->ift_size; i++) 1627 iflib_txsd_destroy(ctx, txq, i); 1628 if (txq->ift_sds.ifsd_map != NULL) { 1629 free(txq->ift_sds.ifsd_map, M_IFLIB); 1630 txq->ift_sds.ifsd_map = NULL; 1631 } 1632 if (txq->ift_sds.ifsd_m != NULL) { 1633 free(txq->ift_sds.ifsd_m, M_IFLIB); 1634 txq->ift_sds.ifsd_m = NULL; 1635 } 1636 if (txq->ift_sds.ifsd_flags != NULL) { 1637 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1638 txq->ift_sds.ifsd_flags = NULL; 1639 } 1640 if (txq->ift_desc_tag != NULL) { 1641 bus_dma_tag_destroy(txq->ift_desc_tag); 1642 txq->ift_desc_tag = NULL; 1643 } 1644 if (txq->ift_tso_desc_tag != NULL) { 1645 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1646 txq->ift_tso_desc_tag = NULL; 1647 } 1648 } 1649 1650 static void 1651 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1652 { 1653 struct mbuf **mp; 1654 1655 mp = &txq->ift_sds.ifsd_m[i]; 1656 if (*mp == NULL) 1657 return; 1658 1659 if (txq->ift_sds.ifsd_map != NULL) { 1660 bus_dmamap_sync(txq->ift_desc_tag, 1661 txq->ift_sds.ifsd_map[i], 1662 BUS_DMASYNC_POSTWRITE); 1663 bus_dmamap_unload(txq->ift_desc_tag, 1664 txq->ift_sds.ifsd_map[i]); 1665 } 1666 m_free(*mp); 1667 DBG_COUNTER_INC(tx_frees); 1668 *mp = NULL; 1669 } 1670 1671 static int 1672 iflib_txq_setup(iflib_txq_t txq) 1673 { 1674 if_ctx_t ctx = txq->ift_ctx; 1675 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1676 iflib_dma_info_t di; 1677 int i; 1678 1679 /* Set number of descriptors available */ 1680 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1681 /* XXX make configurable */ 1682 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1683 1684 /* Reset indices */ 1685 txq->ift_cidx_processed = 0; 1686 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1687 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1688 1689 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1690 bzero((void *)di->idi_vaddr, di->idi_size); 1691 1692 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1693 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1694 bus_dmamap_sync(di->idi_tag, di->idi_map, 1695 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1696 return (0); 1697 } 1698 1699 /********************************************************************* 1700 * 1701 * Allocate memory for rx_buffer structures. Since we use one 1702 * rx_buffer per received packet, the maximum number of rx_buffer's 1703 * that we'll need is equal to the number of receive descriptors 1704 * that we've allocated. 1705 * 1706 **********************************************************************/ 1707 static int 1708 iflib_rxsd_alloc(iflib_rxq_t rxq) 1709 { 1710 if_ctx_t ctx = rxq->ifr_ctx; 1711 if_shared_ctx_t sctx = ctx->ifc_sctx; 1712 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1713 device_t dev = ctx->ifc_dev; 1714 iflib_fl_t fl; 1715 int err; 1716 1717 MPASS(scctx->isc_nrxd[0] > 0); 1718 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1719 1720 fl = rxq->ifr_fl; 1721 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1722 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1723 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1724 1, 0, /* alignment, bounds */ 1725 BUS_SPACE_MAXADDR, /* lowaddr */ 1726 BUS_SPACE_MAXADDR, /* highaddr */ 1727 NULL, NULL, /* filter, filterarg */ 1728 sctx->isc_rx_maxsize, /* maxsize */ 1729 sctx->isc_rx_nsegments, /* nsegments */ 1730 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1731 0, /* flags */ 1732 NULL, /* lockfunc */ 1733 NULL, /* lockarg */ 1734 &fl->ifl_desc_tag); 1735 if (err) { 1736 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1737 __func__, err); 1738 goto fail; 1739 } 1740 if (!(fl->ifl_sds.ifsd_flags = 1741 (uint8_t *) malloc(sizeof(uint8_t) * 1742 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1743 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1744 err = ENOMEM; 1745 goto fail; 1746 } 1747 if (!(fl->ifl_sds.ifsd_m = 1748 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1749 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1750 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1751 err = ENOMEM; 1752 goto fail; 1753 } 1754 if (!(fl->ifl_sds.ifsd_cl = 1755 (caddr_t *) malloc(sizeof(caddr_t) * 1756 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1757 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1758 err = ENOMEM; 1759 goto fail; 1760 } 1761 1762 /* Create the descriptor buffer dma maps */ 1763 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1764 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1765 continue; 1766 1767 if (!(fl->ifl_sds.ifsd_map = 1768 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1769 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1770 err = ENOMEM; 1771 goto fail; 1772 } 1773 1774 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1775 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1776 if (err != 0) { 1777 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1778 goto fail; 1779 } 1780 } 1781 #endif 1782 } 1783 return (0); 1784 1785 fail: 1786 iflib_rx_structures_free(ctx); 1787 return (err); 1788 } 1789 1790 1791 /* 1792 * Internal service routines 1793 */ 1794 1795 struct rxq_refill_cb_arg { 1796 int error; 1797 bus_dma_segment_t seg; 1798 int nseg; 1799 }; 1800 1801 static void 1802 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1803 { 1804 struct rxq_refill_cb_arg *cb_arg = arg; 1805 1806 cb_arg->error = error; 1807 cb_arg->seg = segs[0]; 1808 cb_arg->nseg = nseg; 1809 } 1810 1811 1812 #ifdef ACPI_DMAR 1813 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1814 #else 1815 #define IS_DMAR(ctx) (0) 1816 #endif 1817 1818 /** 1819 * rxq_refill - refill an rxq free-buffer list 1820 * @ctx: the iflib context 1821 * @rxq: the free-list to refill 1822 * @n: the number of new buffers to allocate 1823 * 1824 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1825 * The caller must assure that @n does not exceed the queue's capacity. 1826 */ 1827 static void 1828 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1829 { 1830 struct mbuf *m; 1831 int idx, frag_idx = fl->ifl_fragidx; 1832 int pidx = fl->ifl_pidx; 1833 caddr_t cl, *sd_cl; 1834 struct mbuf **sd_m; 1835 uint8_t *sd_flags; 1836 struct if_rxd_update iru; 1837 bus_dmamap_t *sd_map; 1838 int n, i = 0; 1839 uint64_t bus_addr; 1840 int err; 1841 qidx_t credits; 1842 1843 sd_m = fl->ifl_sds.ifsd_m; 1844 sd_map = fl->ifl_sds.ifsd_map; 1845 sd_cl = fl->ifl_sds.ifsd_cl; 1846 sd_flags = fl->ifl_sds.ifsd_flags; 1847 idx = pidx; 1848 credits = fl->ifl_credits; 1849 1850 n = count; 1851 MPASS(n > 0); 1852 MPASS(credits + n <= fl->ifl_size); 1853 1854 if (pidx < fl->ifl_cidx) 1855 MPASS(pidx + n <= fl->ifl_cidx); 1856 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1857 MPASS(fl->ifl_gen == 0); 1858 if (pidx > fl->ifl_cidx) 1859 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1860 1861 DBG_COUNTER_INC(fl_refills); 1862 if (n > 8) 1863 DBG_COUNTER_INC(fl_refills_large); 1864 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1865 while (n--) { 1866 /* 1867 * We allocate an uninitialized mbuf + cluster, mbuf is 1868 * initialized after rx. 1869 * 1870 * If the cluster is still set then we know a minimum sized packet was received 1871 */ 1872 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1873 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1874 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1875 if ((cl = sd_cl[frag_idx]) == NULL) { 1876 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1877 break; 1878 #if MEMORY_LOGGING 1879 fl->ifl_cl_enqueued++; 1880 #endif 1881 } 1882 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1883 break; 1884 } 1885 #if MEMORY_LOGGING 1886 fl->ifl_m_enqueued++; 1887 #endif 1888 1889 DBG_COUNTER_INC(rx_allocs); 1890 #if defined(__i386__) || defined(__amd64__) 1891 if (!IS_DMAR(ctx)) { 1892 bus_addr = pmap_kextract((vm_offset_t)cl); 1893 } else 1894 #endif 1895 { 1896 struct rxq_refill_cb_arg cb_arg; 1897 1898 cb_arg.error = 0; 1899 MPASS(sd_map != NULL); 1900 MPASS(sd_map[frag_idx] != NULL); 1901 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1902 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1903 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 1904 BUS_DMASYNC_PREREAD); 1905 1906 if (err != 0 || cb_arg.error) { 1907 /* 1908 * !zone_pack ? 1909 */ 1910 if (fl->ifl_zone == zone_pack) 1911 uma_zfree(fl->ifl_zone, cl); 1912 m_free(m); 1913 n = 0; 1914 goto done; 1915 } 1916 bus_addr = cb_arg.seg.ds_addr; 1917 } 1918 bit_set(fl->ifl_rx_bitmap, frag_idx); 1919 sd_flags[frag_idx] |= RX_SW_DESC_INUSE; 1920 1921 MPASS(sd_m[frag_idx] == NULL); 1922 sd_cl[frag_idx] = cl; 1923 sd_m[frag_idx] = m; 1924 fl->ifl_rxd_idxs[i] = frag_idx; 1925 fl->ifl_bus_addrs[i] = bus_addr; 1926 fl->ifl_vm_addrs[i] = cl; 1927 credits++; 1928 i++; 1929 MPASS(credits <= fl->ifl_size); 1930 if (++idx == fl->ifl_size) { 1931 fl->ifl_gen = 1; 1932 idx = 0; 1933 } 1934 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 1935 iru.iru_pidx = pidx; 1936 iru.iru_count = i; 1937 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1938 i = 0; 1939 pidx = idx; 1940 fl->ifl_pidx = idx; 1941 fl->ifl_credits = credits; 1942 } 1943 1944 } 1945 done: 1946 if (i) { 1947 iru.iru_pidx = pidx; 1948 iru.iru_count = i; 1949 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1950 fl->ifl_pidx = idx; 1951 fl->ifl_credits = credits; 1952 } 1953 DBG_COUNTER_INC(rxd_flush); 1954 if (fl->ifl_pidx == 0) 1955 pidx = fl->ifl_size - 1; 1956 else 1957 pidx = fl->ifl_pidx - 1; 1958 1959 if (sd_map) 1960 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1961 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1962 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 1963 fl->ifl_fragidx = frag_idx; 1964 } 1965 1966 static __inline void 1967 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 1968 { 1969 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 1970 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 1971 #ifdef INVARIANTS 1972 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 1973 #endif 1974 1975 MPASS(fl->ifl_credits <= fl->ifl_size); 1976 MPASS(reclaimable == delta); 1977 1978 if (reclaimable > 0) 1979 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 1980 } 1981 1982 static void 1983 iflib_fl_bufs_free(iflib_fl_t fl) 1984 { 1985 iflib_dma_info_t idi = fl->ifl_ifdi; 1986 uint32_t i; 1987 1988 for (i = 0; i < fl->ifl_size; i++) { 1989 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 1990 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 1991 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 1992 1993 if (*sd_flags & RX_SW_DESC_INUSE) { 1994 if (fl->ifl_sds.ifsd_map != NULL) { 1995 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 1996 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 1997 if (fl->ifl_rxq->ifr_ctx->ifc_in_detach) 1998 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 1999 } 2000 if (*sd_m != NULL) { 2001 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2002 uma_zfree(zone_mbuf, *sd_m); 2003 } 2004 if (*sd_cl != NULL) 2005 uma_zfree(fl->ifl_zone, *sd_cl); 2006 *sd_flags = 0; 2007 } else { 2008 MPASS(*sd_cl == NULL); 2009 MPASS(*sd_m == NULL); 2010 } 2011 #if MEMORY_LOGGING 2012 fl->ifl_m_dequeued++; 2013 fl->ifl_cl_dequeued++; 2014 #endif 2015 *sd_cl = NULL; 2016 *sd_m = NULL; 2017 } 2018 #ifdef INVARIANTS 2019 for (i = 0; i < fl->ifl_size; i++) { 2020 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 2021 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2022 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2023 } 2024 #endif 2025 /* 2026 * Reset free list values 2027 */ 2028 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2029 bzero(idi->idi_vaddr, idi->idi_size); 2030 } 2031 2032 /********************************************************************* 2033 * 2034 * Initialize a receive ring and its buffers. 2035 * 2036 **********************************************************************/ 2037 static int 2038 iflib_fl_setup(iflib_fl_t fl) 2039 { 2040 iflib_rxq_t rxq = fl->ifl_rxq; 2041 if_ctx_t ctx = rxq->ifr_ctx; 2042 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2043 2044 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2045 /* 2046 ** Free current RX buffer structs and their mbufs 2047 */ 2048 iflib_fl_bufs_free(fl); 2049 /* Now replenish the mbufs */ 2050 MPASS(fl->ifl_credits == 0); 2051 /* 2052 * XXX don't set the max_frame_size to larger 2053 * than the hardware can handle 2054 */ 2055 if (sctx->isc_max_frame_size <= 2048) 2056 fl->ifl_buf_size = MCLBYTES; 2057 #ifndef CONTIGMALLOC_WORKS 2058 else 2059 fl->ifl_buf_size = MJUMPAGESIZE; 2060 #else 2061 else if (sctx->isc_max_frame_size <= 4096) 2062 fl->ifl_buf_size = MJUMPAGESIZE; 2063 else if (sctx->isc_max_frame_size <= 9216) 2064 fl->ifl_buf_size = MJUM9BYTES; 2065 else 2066 fl->ifl_buf_size = MJUM16BYTES; 2067 #endif 2068 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2069 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2070 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2071 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2072 2073 2074 /* avoid pre-allocating zillions of clusters to an idle card 2075 * potentially speeding up attach 2076 */ 2077 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2078 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2079 if (min(128, fl->ifl_size) != fl->ifl_credits) 2080 return (ENOBUFS); 2081 /* 2082 * handle failure 2083 */ 2084 MPASS(rxq != NULL); 2085 MPASS(fl->ifl_ifdi != NULL); 2086 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2087 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2088 return (0); 2089 } 2090 2091 /********************************************************************* 2092 * 2093 * Free receive ring data structures 2094 * 2095 **********************************************************************/ 2096 static void 2097 iflib_rx_sds_free(iflib_rxq_t rxq) 2098 { 2099 iflib_fl_t fl; 2100 int i; 2101 2102 if (rxq->ifr_fl != NULL) { 2103 for (i = 0; i < rxq->ifr_nfl; i++) { 2104 fl = &rxq->ifr_fl[i]; 2105 if (fl->ifl_desc_tag != NULL) { 2106 bus_dma_tag_destroy(fl->ifl_desc_tag); 2107 fl->ifl_desc_tag = NULL; 2108 } 2109 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2110 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2111 /* XXX destroy maps first */ 2112 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2113 fl->ifl_sds.ifsd_m = NULL; 2114 fl->ifl_sds.ifsd_cl = NULL; 2115 fl->ifl_sds.ifsd_map = NULL; 2116 } 2117 free(rxq->ifr_fl, M_IFLIB); 2118 rxq->ifr_fl = NULL; 2119 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2120 } 2121 } 2122 2123 /* 2124 * MI independent logic 2125 * 2126 */ 2127 static void 2128 iflib_timer(void *arg) 2129 { 2130 iflib_txq_t txq = arg; 2131 if_ctx_t ctx = txq->ift_ctx; 2132 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2133 2134 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2135 return; 2136 /* 2137 ** Check on the state of the TX queue(s), this 2138 ** can be done without the lock because its RO 2139 ** and the HUNG state will be static if set. 2140 */ 2141 IFDI_TIMER(ctx, txq->ift_id); 2142 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2143 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2144 (sctx->isc_pause_frames == 0))) 2145 goto hung; 2146 2147 if (ifmp_ring_is_stalled(txq->ift_br)) 2148 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2149 txq->ift_cleaned_prev = txq->ift_cleaned; 2150 /* handle any laggards */ 2151 if (txq->ift_db_pending) 2152 GROUPTASK_ENQUEUE(&txq->ift_task); 2153 2154 sctx->isc_pause_frames = 0; 2155 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2156 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 2157 return; 2158 hung: 2159 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2160 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2161 STATE_LOCK(ctx); 2162 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2163 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2164 iflib_admin_intr_deferred(ctx); 2165 STATE_UNLOCK(ctx); 2166 } 2167 2168 static void 2169 iflib_init_locked(if_ctx_t ctx) 2170 { 2171 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2172 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2173 if_t ifp = ctx->ifc_ifp; 2174 iflib_fl_t fl; 2175 iflib_txq_t txq; 2176 iflib_rxq_t rxq; 2177 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2178 2179 2180 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2181 IFDI_INTR_DISABLE(ctx); 2182 2183 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2184 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2185 /* Set hardware offload abilities */ 2186 if_clearhwassist(ifp); 2187 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2188 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2189 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2190 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2191 if (if_getcapenable(ifp) & IFCAP_TSO4) 2192 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2193 if (if_getcapenable(ifp) & IFCAP_TSO6) 2194 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2195 2196 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2197 CALLOUT_LOCK(txq); 2198 callout_stop(&txq->ift_timer); 2199 CALLOUT_UNLOCK(txq); 2200 iflib_netmap_txq_init(ctx, txq); 2201 } 2202 #ifdef INVARIANTS 2203 i = if_getdrvflags(ifp); 2204 #endif 2205 IFDI_INIT(ctx); 2206 MPASS(if_getdrvflags(ifp) == i); 2207 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2208 /* XXX this should really be done on a per-queue basis */ 2209 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2210 MPASS(rxq->ifr_id == i); 2211 iflib_netmap_rxq_init(ctx, rxq); 2212 continue; 2213 } 2214 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2215 if (iflib_fl_setup(fl)) { 2216 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2217 goto done; 2218 } 2219 } 2220 } 2221 done: 2222 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2223 IFDI_INTR_ENABLE(ctx); 2224 txq = ctx->ifc_txqs; 2225 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2226 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2227 txq->ift_timer.c_cpu); 2228 } 2229 2230 static int 2231 iflib_media_change(if_t ifp) 2232 { 2233 if_ctx_t ctx = if_getsoftc(ifp); 2234 int err; 2235 2236 CTX_LOCK(ctx); 2237 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2238 iflib_init_locked(ctx); 2239 CTX_UNLOCK(ctx); 2240 return (err); 2241 } 2242 2243 static void 2244 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2245 { 2246 if_ctx_t ctx = if_getsoftc(ifp); 2247 2248 CTX_LOCK(ctx); 2249 IFDI_UPDATE_ADMIN_STATUS(ctx); 2250 IFDI_MEDIA_STATUS(ctx, ifmr); 2251 CTX_UNLOCK(ctx); 2252 } 2253 2254 static void 2255 iflib_stop(if_ctx_t ctx) 2256 { 2257 iflib_txq_t txq = ctx->ifc_txqs; 2258 iflib_rxq_t rxq = ctx->ifc_rxqs; 2259 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2260 iflib_dma_info_t di; 2261 iflib_fl_t fl; 2262 int i, j; 2263 2264 /* Tell the stack that the interface is no longer active */ 2265 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2266 2267 IFDI_INTR_DISABLE(ctx); 2268 DELAY(1000); 2269 IFDI_STOP(ctx); 2270 DELAY(1000); 2271 2272 iflib_debug_reset(); 2273 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2274 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2275 /* make sure all transmitters have completed before proceeding XXX */ 2276 2277 CALLOUT_LOCK(txq); 2278 callout_stop(&txq->ift_timer); 2279 CALLOUT_UNLOCK(txq); 2280 2281 /* clean any enqueued buffers */ 2282 iflib_ifmp_purge(txq); 2283 /* Free any existing tx buffers. */ 2284 for (j = 0; j < txq->ift_size; j++) { 2285 iflib_txsd_free(ctx, txq, j); 2286 } 2287 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2288 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2289 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2290 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2291 txq->ift_pullups = 0; 2292 ifmp_ring_reset_stats(txq->ift_br); 2293 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2294 bzero((void *)di->idi_vaddr, di->idi_size); 2295 } 2296 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2297 /* make sure all transmitters have completed before proceeding XXX */ 2298 2299 for (j = 0, di = rxq->ifr_ifdi; j < rxq->ifr_nfl; j++, di++) 2300 bzero((void *)di->idi_vaddr, di->idi_size); 2301 /* also resets the free lists pidx/cidx */ 2302 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2303 iflib_fl_bufs_free(fl); 2304 } 2305 } 2306 2307 static inline caddr_t 2308 calc_next_rxd(iflib_fl_t fl, int cidx) 2309 { 2310 qidx_t size; 2311 int nrxd; 2312 caddr_t start, end, cur, next; 2313 2314 nrxd = fl->ifl_size; 2315 size = fl->ifl_rxd_size; 2316 start = fl->ifl_ifdi->idi_vaddr; 2317 2318 if (__predict_false(size == 0)) 2319 return (start); 2320 cur = start + size*cidx; 2321 end = start + size*nrxd; 2322 next = CACHE_PTR_NEXT(cur); 2323 return (next < end ? next : start); 2324 } 2325 2326 static inline void 2327 prefetch_pkts(iflib_fl_t fl, int cidx) 2328 { 2329 int nextptr; 2330 int nrxd = fl->ifl_size; 2331 caddr_t next_rxd; 2332 2333 2334 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2335 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2336 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2337 next_rxd = calc_next_rxd(fl, cidx); 2338 prefetch(next_rxd); 2339 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2340 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2341 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2342 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2343 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2344 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2345 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2346 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2347 } 2348 2349 static void 2350 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2351 { 2352 int flid, cidx; 2353 bus_dmamap_t map; 2354 iflib_fl_t fl; 2355 iflib_dma_info_t di; 2356 int next; 2357 2358 map = NULL; 2359 flid = irf->irf_flid; 2360 cidx = irf->irf_idx; 2361 fl = &rxq->ifr_fl[flid]; 2362 sd->ifsd_fl = fl; 2363 sd->ifsd_cidx = cidx; 2364 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2365 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2366 fl->ifl_credits--; 2367 #if MEMORY_LOGGING 2368 fl->ifl_m_dequeued++; 2369 #endif 2370 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2371 prefetch_pkts(fl, cidx); 2372 if (fl->ifl_sds.ifsd_map != NULL) { 2373 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2374 prefetch(&fl->ifl_sds.ifsd_map[next]); 2375 map = fl->ifl_sds.ifsd_map[cidx]; 2376 di = fl->ifl_ifdi; 2377 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2378 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2379 bus_dmamap_sync(di->idi_tag, di->idi_map, 2380 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2381 2382 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2383 MPASS(fl->ifl_cidx == cidx); 2384 if (unload) 2385 bus_dmamap_unload(fl->ifl_desc_tag, map); 2386 } 2387 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2388 if (__predict_false(fl->ifl_cidx == 0)) 2389 fl->ifl_gen = 0; 2390 if (map != NULL) 2391 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2392 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2393 bit_clear(fl->ifl_rx_bitmap, cidx); 2394 } 2395 2396 static struct mbuf * 2397 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2398 { 2399 int i, padlen , flags; 2400 struct mbuf *m, *mh, *mt; 2401 caddr_t cl; 2402 2403 i = 0; 2404 mh = NULL; 2405 do { 2406 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2407 2408 MPASS(*sd->ifsd_cl != NULL); 2409 MPASS(*sd->ifsd_m != NULL); 2410 2411 /* Don't include zero-length frags */ 2412 if (ri->iri_frags[i].irf_len == 0) { 2413 /* XXX we can save the cluster here, but not the mbuf */ 2414 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2415 m_free(*sd->ifsd_m); 2416 *sd->ifsd_m = NULL; 2417 continue; 2418 } 2419 m = *sd->ifsd_m; 2420 *sd->ifsd_m = NULL; 2421 if (mh == NULL) { 2422 flags = M_PKTHDR|M_EXT; 2423 mh = mt = m; 2424 padlen = ri->iri_pad; 2425 } else { 2426 flags = M_EXT; 2427 mt->m_next = m; 2428 mt = m; 2429 /* assuming padding is only on the first fragment */ 2430 padlen = 0; 2431 } 2432 cl = *sd->ifsd_cl; 2433 *sd->ifsd_cl = NULL; 2434 2435 /* Can these two be made one ? */ 2436 m_init(m, M_NOWAIT, MT_DATA, flags); 2437 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2438 /* 2439 * These must follow m_init and m_cljset 2440 */ 2441 m->m_data += padlen; 2442 ri->iri_len -= padlen; 2443 m->m_len = ri->iri_frags[i].irf_len; 2444 } while (++i < ri->iri_nfrags); 2445 2446 return (mh); 2447 } 2448 2449 /* 2450 * Process one software descriptor 2451 */ 2452 static struct mbuf * 2453 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2454 { 2455 struct if_rxsd sd; 2456 struct mbuf *m; 2457 2458 /* should I merge this back in now that the two paths are basically duplicated? */ 2459 if (ri->iri_nfrags == 1 && 2460 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2461 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2462 m = *sd.ifsd_m; 2463 *sd.ifsd_m = NULL; 2464 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2465 #ifndef __NO_STRICT_ALIGNMENT 2466 if (!IP_ALIGNED(m)) 2467 m->m_data += 2; 2468 #endif 2469 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2470 m->m_len = ri->iri_frags[0].irf_len; 2471 } else { 2472 m = assemble_segments(rxq, ri, &sd); 2473 } 2474 m->m_pkthdr.len = ri->iri_len; 2475 m->m_pkthdr.rcvif = ri->iri_ifp; 2476 m->m_flags |= ri->iri_flags; 2477 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2478 m->m_pkthdr.flowid = ri->iri_flowid; 2479 M_HASHTYPE_SET(m, ri->iri_rsstype); 2480 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2481 m->m_pkthdr.csum_data = ri->iri_csum_data; 2482 return (m); 2483 } 2484 2485 #if defined(INET6) || defined(INET) 2486 static void 2487 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2488 { 2489 CURVNET_SET(lc->ifp->if_vnet); 2490 #if defined(INET6) 2491 *v6 = VNET(ip6_forwarding); 2492 #endif 2493 #if defined(INET) 2494 *v4 = VNET(ipforwarding); 2495 #endif 2496 CURVNET_RESTORE(); 2497 } 2498 2499 /* 2500 * Returns true if it's possible this packet could be LROed. 2501 * if it returns false, it is guaranteed that tcp_lro_rx() 2502 * would not return zero. 2503 */ 2504 static bool 2505 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2506 { 2507 struct ether_header *eh; 2508 uint16_t eh_type; 2509 2510 eh = mtod(m, struct ether_header *); 2511 eh_type = ntohs(eh->ether_type); 2512 switch (eh_type) { 2513 #if defined(INET6) 2514 case ETHERTYPE_IPV6: 2515 return !v6_forwarding; 2516 #endif 2517 #if defined (INET) 2518 case ETHERTYPE_IP: 2519 return !v4_forwarding; 2520 #endif 2521 } 2522 2523 return false; 2524 } 2525 #else 2526 static void 2527 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2528 { 2529 } 2530 #endif 2531 2532 static bool 2533 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2534 { 2535 if_ctx_t ctx = rxq->ifr_ctx; 2536 if_shared_ctx_t sctx = ctx->ifc_sctx; 2537 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2538 int avail, i; 2539 qidx_t *cidxp; 2540 struct if_rxd_info ri; 2541 int err, budget_left, rx_bytes, rx_pkts; 2542 iflib_fl_t fl; 2543 struct ifnet *ifp; 2544 int lro_enabled; 2545 bool lro_possible = false; 2546 bool v4_forwarding, v6_forwarding; 2547 2548 /* 2549 * XXX early demux data packets so that if_input processing only handles 2550 * acks in interrupt context 2551 */ 2552 struct mbuf *m, *mh, *mt, *mf; 2553 2554 ifp = ctx->ifc_ifp; 2555 mh = mt = NULL; 2556 MPASS(budget > 0); 2557 rx_pkts = rx_bytes = 0; 2558 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2559 cidxp = &rxq->ifr_cq_cidx; 2560 else 2561 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2562 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2563 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2564 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2565 DBG_COUNTER_INC(rx_unavail); 2566 return (false); 2567 } 2568 2569 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2570 if (__predict_false(!CTX_ACTIVE(ctx))) { 2571 DBG_COUNTER_INC(rx_ctx_inactive); 2572 break; 2573 } 2574 /* 2575 * Reset client set fields to their default values 2576 */ 2577 rxd_info_zero(&ri); 2578 ri.iri_qsidx = rxq->ifr_id; 2579 ri.iri_cidx = *cidxp; 2580 ri.iri_ifp = ifp; 2581 ri.iri_frags = rxq->ifr_frags; 2582 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2583 2584 if (err) 2585 goto err; 2586 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2587 *cidxp = ri.iri_cidx; 2588 /* Update our consumer index */ 2589 /* XXX NB: shurd - check if this is still safe */ 2590 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2591 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2592 rxq->ifr_cq_gen = 0; 2593 } 2594 /* was this only a completion queue message? */ 2595 if (__predict_false(ri.iri_nfrags == 0)) 2596 continue; 2597 } 2598 MPASS(ri.iri_nfrags != 0); 2599 MPASS(ri.iri_len != 0); 2600 2601 /* will advance the cidx on the corresponding free lists */ 2602 m = iflib_rxd_pkt_get(rxq, &ri); 2603 if (avail == 0 && budget_left) 2604 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2605 2606 if (__predict_false(m == NULL)) { 2607 DBG_COUNTER_INC(rx_mbuf_null); 2608 continue; 2609 } 2610 /* imm_pkt: -- cxgb */ 2611 if (mh == NULL) 2612 mh = mt = m; 2613 else { 2614 mt->m_nextpkt = m; 2615 mt = m; 2616 } 2617 } 2618 /* make sure that we can refill faster than drain */ 2619 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2620 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2621 2622 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2623 if (lro_enabled) 2624 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2625 mt = mf = NULL; 2626 while (mh != NULL) { 2627 m = mh; 2628 mh = mh->m_nextpkt; 2629 m->m_nextpkt = NULL; 2630 #ifndef __NO_STRICT_ALIGNMENT 2631 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2632 continue; 2633 #endif 2634 rx_bytes += m->m_pkthdr.len; 2635 rx_pkts++; 2636 #if defined(INET6) || defined(INET) 2637 if (lro_enabled) { 2638 if (!lro_possible) { 2639 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2640 if (lro_possible && mf != NULL) { 2641 ifp->if_input(ifp, mf); 2642 DBG_COUNTER_INC(rx_if_input); 2643 mt = mf = NULL; 2644 } 2645 } 2646 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2647 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2648 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2649 continue; 2650 } 2651 } 2652 #endif 2653 if (lro_possible) { 2654 ifp->if_input(ifp, m); 2655 DBG_COUNTER_INC(rx_if_input); 2656 continue; 2657 } 2658 2659 if (mf == NULL) 2660 mf = m; 2661 if (mt != NULL) 2662 mt->m_nextpkt = m; 2663 mt = m; 2664 } 2665 if (mf != NULL) { 2666 ifp->if_input(ifp, mf); 2667 DBG_COUNTER_INC(rx_if_input); 2668 } 2669 2670 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2671 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2672 2673 /* 2674 * Flush any outstanding LRO work 2675 */ 2676 #if defined(INET6) || defined(INET) 2677 tcp_lro_flush_all(&rxq->ifr_lc); 2678 #endif 2679 if (avail) 2680 return true; 2681 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2682 err: 2683 STATE_LOCK(ctx); 2684 ctx->ifc_flags |= IFC_DO_RESET; 2685 iflib_admin_intr_deferred(ctx); 2686 STATE_UNLOCK(ctx); 2687 return (false); 2688 } 2689 2690 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2691 static inline qidx_t 2692 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2693 { 2694 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2695 qidx_t minthresh = txq->ift_size / 8; 2696 if (in_use > 4*minthresh) 2697 return (notify_count); 2698 if (in_use > 2*minthresh) 2699 return (notify_count >> 1); 2700 if (in_use > minthresh) 2701 return (notify_count >> 3); 2702 return (0); 2703 } 2704 2705 static inline qidx_t 2706 txq_max_rs_deferred(iflib_txq_t txq) 2707 { 2708 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2709 qidx_t minthresh = txq->ift_size / 8; 2710 if (txq->ift_in_use > 4*minthresh) 2711 return (notify_count); 2712 if (txq->ift_in_use > 2*minthresh) 2713 return (notify_count >> 1); 2714 if (txq->ift_in_use > minthresh) 2715 return (notify_count >> 2); 2716 return (2); 2717 } 2718 2719 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2720 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2721 2722 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2723 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2724 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2725 2726 /* forward compatibility for cxgb */ 2727 #define FIRST_QSET(ctx) 0 2728 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2729 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2730 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2731 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2732 2733 /* XXX we should be setting this to something other than zero */ 2734 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2735 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2736 2737 static inline bool 2738 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2739 { 2740 qidx_t dbval, max; 2741 bool rang; 2742 2743 rang = false; 2744 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2745 if (ring || txq->ift_db_pending >= max) { 2746 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2747 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2748 txq->ift_db_pending = txq->ift_npending = 0; 2749 rang = true; 2750 } 2751 return (rang); 2752 } 2753 2754 #ifdef PKT_DEBUG 2755 static void 2756 print_pkt(if_pkt_info_t pi) 2757 { 2758 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2759 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2760 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2761 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2762 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2763 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2764 } 2765 #endif 2766 2767 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2768 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2769 2770 static int 2771 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2772 { 2773 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2774 struct ether_vlan_header *eh; 2775 struct mbuf *m, *n; 2776 2777 n = m = *mp; 2778 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2779 M_WRITABLE(m) == 0) { 2780 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2781 return (ENOMEM); 2782 } else { 2783 m_freem(*mp); 2784 n = *mp = m; 2785 } 2786 } 2787 2788 /* 2789 * Determine where frame payload starts. 2790 * Jump over vlan headers if already present, 2791 * helpful for QinQ too. 2792 */ 2793 if (__predict_false(m->m_len < sizeof(*eh))) { 2794 txq->ift_pullups++; 2795 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2796 return (ENOMEM); 2797 } 2798 eh = mtod(m, struct ether_vlan_header *); 2799 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2800 pi->ipi_etype = ntohs(eh->evl_proto); 2801 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2802 } else { 2803 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2804 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2805 } 2806 2807 switch (pi->ipi_etype) { 2808 #ifdef INET 2809 case ETHERTYPE_IP: 2810 { 2811 struct ip *ip = NULL; 2812 struct tcphdr *th = NULL; 2813 int minthlen; 2814 2815 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2816 if (__predict_false(m->m_len < minthlen)) { 2817 /* 2818 * if this code bloat is causing too much of a hit 2819 * move it to a separate function and mark it noinline 2820 */ 2821 if (m->m_len == pi->ipi_ehdrlen) { 2822 n = m->m_next; 2823 MPASS(n); 2824 if (n->m_len >= sizeof(*ip)) { 2825 ip = (struct ip *)n->m_data; 2826 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2827 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2828 } else { 2829 txq->ift_pullups++; 2830 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2831 return (ENOMEM); 2832 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2833 } 2834 } else { 2835 txq->ift_pullups++; 2836 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2837 return (ENOMEM); 2838 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2839 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2840 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2841 } 2842 } else { 2843 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2844 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2845 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2846 } 2847 pi->ipi_ip_hlen = ip->ip_hl << 2; 2848 pi->ipi_ipproto = ip->ip_p; 2849 pi->ipi_flags |= IPI_TX_IPV4; 2850 2851 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 2852 ip->ip_sum = 0; 2853 2854 if (IS_TSO4(pi)) { 2855 if (pi->ipi_ipproto == IPPROTO_TCP) { 2856 if (__predict_false(th == NULL)) { 2857 txq->ift_pullups++; 2858 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2859 return (ENOMEM); 2860 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2861 } 2862 pi->ipi_tcp_hflags = th->th_flags; 2863 pi->ipi_tcp_hlen = th->th_off << 2; 2864 pi->ipi_tcp_seq = th->th_seq; 2865 } 2866 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2867 return (ENXIO); 2868 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2869 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2870 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2871 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2872 ip->ip_sum = 0; 2873 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2874 } 2875 } 2876 break; 2877 } 2878 #endif 2879 #ifdef INET6 2880 case ETHERTYPE_IPV6: 2881 { 2882 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2883 struct tcphdr *th; 2884 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2885 2886 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2887 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2888 return (ENOMEM); 2889 } 2890 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2891 2892 /* XXX-BZ this will go badly in case of ext hdrs. */ 2893 pi->ipi_ipproto = ip6->ip6_nxt; 2894 pi->ipi_flags |= IPI_TX_IPV6; 2895 2896 if (IS_TSO6(pi)) { 2897 if (pi->ipi_ipproto == IPPROTO_TCP) { 2898 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2899 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2900 return (ENOMEM); 2901 } 2902 pi->ipi_tcp_hflags = th->th_flags; 2903 pi->ipi_tcp_hlen = th->th_off << 2; 2904 } 2905 2906 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2907 return (ENXIO); 2908 /* 2909 * The corresponding flag is set by the stack in the IPv4 2910 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 2911 * So, set it here because the rest of the flow requires it. 2912 */ 2913 pi->ipi_csum_flags |= CSUM_TCP_IPV6; 2914 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2915 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2916 } 2917 break; 2918 } 2919 #endif 2920 default: 2921 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2922 pi->ipi_ip_hlen = 0; 2923 break; 2924 } 2925 *mp = m; 2926 2927 return (0); 2928 } 2929 2930 static __noinline struct mbuf * 2931 collapse_pkthdr(struct mbuf *m0) 2932 { 2933 struct mbuf *m, *m_next, *tmp; 2934 2935 m = m0; 2936 m_next = m->m_next; 2937 while (m_next != NULL && m_next->m_len == 0) { 2938 m = m_next; 2939 m->m_next = NULL; 2940 m_free(m); 2941 m_next = m_next->m_next; 2942 } 2943 m = m0; 2944 m->m_next = m_next; 2945 if ((m_next->m_flags & M_EXT) == 0) { 2946 m = m_defrag(m, M_NOWAIT); 2947 } else { 2948 tmp = m_next->m_next; 2949 memcpy(m_next, m, MPKTHSIZE); 2950 m = m_next; 2951 m->m_next = tmp; 2952 } 2953 return (m); 2954 } 2955 2956 /* 2957 * If dodgy hardware rejects the scatter gather chain we've handed it 2958 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 2959 * m_defrag'd mbufs 2960 */ 2961 static __noinline struct mbuf * 2962 iflib_remove_mbuf(iflib_txq_t txq) 2963 { 2964 int ntxd, i, pidx; 2965 struct mbuf *m, *mh, **ifsd_m; 2966 2967 pidx = txq->ift_pidx; 2968 ifsd_m = txq->ift_sds.ifsd_m; 2969 ntxd = txq->ift_size; 2970 mh = m = ifsd_m[pidx]; 2971 ifsd_m[pidx] = NULL; 2972 #if MEMORY_LOGGING 2973 txq->ift_dequeued++; 2974 #endif 2975 i = 1; 2976 2977 while (m) { 2978 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 2979 #if MEMORY_LOGGING 2980 txq->ift_dequeued++; 2981 #endif 2982 m = m->m_next; 2983 i++; 2984 } 2985 return (mh); 2986 } 2987 2988 static int 2989 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 2990 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 2991 int max_segs, int flags) 2992 { 2993 if_ctx_t ctx; 2994 if_shared_ctx_t sctx; 2995 if_softc_ctx_t scctx; 2996 int i, next, pidx, err, ntxd, count; 2997 struct mbuf *m, *tmp, **ifsd_m; 2998 2999 m = *m0; 3000 3001 /* 3002 * Please don't ever do this 3003 */ 3004 if (__predict_false(m->m_len == 0)) 3005 *m0 = m = collapse_pkthdr(m); 3006 3007 ctx = txq->ift_ctx; 3008 sctx = ctx->ifc_sctx; 3009 scctx = &ctx->ifc_softc_ctx; 3010 ifsd_m = txq->ift_sds.ifsd_m; 3011 ntxd = txq->ift_size; 3012 pidx = txq->ift_pidx; 3013 if (map != NULL) { 3014 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 3015 3016 err = bus_dmamap_load_mbuf_sg(tag, map, 3017 *m0, segs, nsegs, BUS_DMA_NOWAIT); 3018 if (err) 3019 return (err); 3020 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 3021 count = 0; 3022 m = *m0; 3023 do { 3024 if (__predict_false(m->m_len <= 0)) { 3025 tmp = m; 3026 m = m->m_next; 3027 tmp->m_next = NULL; 3028 m_free(tmp); 3029 continue; 3030 } 3031 m = m->m_next; 3032 count++; 3033 } while (m != NULL); 3034 if (count > *nsegs) { 3035 ifsd_m[pidx] = *m0; 3036 ifsd_m[pidx]->m_flags |= M_TOOBIG; 3037 return (0); 3038 } 3039 m = *m0; 3040 count = 0; 3041 do { 3042 next = (pidx + count) & (ntxd-1); 3043 MPASS(ifsd_m[next] == NULL); 3044 ifsd_m[next] = m; 3045 count++; 3046 tmp = m; 3047 m = m->m_next; 3048 } while (m != NULL); 3049 } else { 3050 int buflen, sgsize, maxsegsz, max_sgsize; 3051 vm_offset_t vaddr; 3052 vm_paddr_t curaddr; 3053 3054 count = i = 0; 3055 m = *m0; 3056 if (m->m_pkthdr.csum_flags & CSUM_TSO) 3057 maxsegsz = scctx->isc_tx_tso_segsize_max; 3058 else 3059 maxsegsz = sctx->isc_tx_maxsegsize; 3060 3061 do { 3062 if (__predict_false(m->m_len <= 0)) { 3063 tmp = m; 3064 m = m->m_next; 3065 tmp->m_next = NULL; 3066 m_free(tmp); 3067 continue; 3068 } 3069 buflen = m->m_len; 3070 vaddr = (vm_offset_t)m->m_data; 3071 /* 3072 * see if we can't be smarter about physically 3073 * contiguous mappings 3074 */ 3075 next = (pidx + count) & (ntxd-1); 3076 MPASS(ifsd_m[next] == NULL); 3077 #if MEMORY_LOGGING 3078 txq->ift_enqueued++; 3079 #endif 3080 ifsd_m[next] = m; 3081 while (buflen > 0) { 3082 if (i >= max_segs) 3083 goto err; 3084 max_sgsize = MIN(buflen, maxsegsz); 3085 curaddr = pmap_kextract(vaddr); 3086 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 3087 sgsize = MIN(sgsize, max_sgsize); 3088 segs[i].ds_addr = curaddr; 3089 segs[i].ds_len = sgsize; 3090 vaddr += sgsize; 3091 buflen -= sgsize; 3092 i++; 3093 } 3094 count++; 3095 tmp = m; 3096 m = m->m_next; 3097 } while (m != NULL); 3098 *nsegs = i; 3099 } 3100 return (0); 3101 err: 3102 *m0 = iflib_remove_mbuf(txq); 3103 return (EFBIG); 3104 } 3105 3106 static inline caddr_t 3107 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3108 { 3109 qidx_t size; 3110 int ntxd; 3111 caddr_t start, end, cur, next; 3112 3113 ntxd = txq->ift_size; 3114 size = txq->ift_txd_size[qid]; 3115 start = txq->ift_ifdi[qid].idi_vaddr; 3116 3117 if (__predict_false(size == 0)) 3118 return (start); 3119 cur = start + size*cidx; 3120 end = start + size*ntxd; 3121 next = CACHE_PTR_NEXT(cur); 3122 return (next < end ? next : start); 3123 } 3124 3125 /* 3126 * Pad an mbuf to ensure a minimum ethernet frame size. 3127 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3128 */ 3129 static __noinline int 3130 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3131 { 3132 /* 3133 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3134 * and ARP message is the smallest common payload I can think of 3135 */ 3136 static char pad[18]; /* just zeros */ 3137 int n; 3138 struct mbuf *new_head; 3139 3140 if (!M_WRITABLE(*m_head)) { 3141 new_head = m_dup(*m_head, M_NOWAIT); 3142 if (new_head == NULL) { 3143 m_freem(*m_head); 3144 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3145 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3146 return ENOMEM; 3147 } 3148 m_freem(*m_head); 3149 *m_head = new_head; 3150 } 3151 3152 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3153 n > 0; n -= sizeof(pad)) 3154 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3155 break; 3156 3157 if (n > 0) { 3158 m_freem(*m_head); 3159 device_printf(dev, "cannot pad short frame\n"); 3160 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3161 return (ENOBUFS); 3162 } 3163 3164 return 0; 3165 } 3166 3167 static int 3168 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3169 { 3170 if_ctx_t ctx; 3171 if_shared_ctx_t sctx; 3172 if_softc_ctx_t scctx; 3173 bus_dma_segment_t *segs; 3174 struct mbuf *m_head; 3175 void *next_txd; 3176 bus_dmamap_t map; 3177 struct if_pkt_info pi; 3178 int remap = 0; 3179 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3180 bus_dma_tag_t desc_tag; 3181 3182 segs = txq->ift_segs; 3183 ctx = txq->ift_ctx; 3184 sctx = ctx->ifc_sctx; 3185 scctx = &ctx->ifc_softc_ctx; 3186 segs = txq->ift_segs; 3187 ntxd = txq->ift_size; 3188 m_head = *m_headp; 3189 map = NULL; 3190 3191 /* 3192 * If we're doing TSO the next descriptor to clean may be quite far ahead 3193 */ 3194 cidx = txq->ift_cidx; 3195 pidx = txq->ift_pidx; 3196 if (ctx->ifc_flags & IFC_PREFETCH) { 3197 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3198 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3199 next_txd = calc_next_txd(txq, cidx, 0); 3200 prefetch(next_txd); 3201 } 3202 3203 /* prefetch the next cache line of mbuf pointers and flags */ 3204 prefetch(&txq->ift_sds.ifsd_m[next]); 3205 if (txq->ift_sds.ifsd_map != NULL) { 3206 prefetch(&txq->ift_sds.ifsd_map[next]); 3207 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3208 prefetch(&txq->ift_sds.ifsd_flags[next]); 3209 } 3210 } else if (txq->ift_sds.ifsd_map != NULL) 3211 map = txq->ift_sds.ifsd_map[pidx]; 3212 3213 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3214 desc_tag = txq->ift_tso_desc_tag; 3215 max_segs = scctx->isc_tx_tso_segments_max; 3216 } else { 3217 desc_tag = txq->ift_desc_tag; 3218 max_segs = scctx->isc_tx_nsegments; 3219 } 3220 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3221 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3222 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3223 if (err) 3224 return err; 3225 } 3226 m_head = *m_headp; 3227 3228 pkt_info_zero(&pi); 3229 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3230 pi.ipi_pidx = pidx; 3231 pi.ipi_qsidx = txq->ift_id; 3232 pi.ipi_len = m_head->m_pkthdr.len; 3233 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3234 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3235 3236 /* deliberate bitwise OR to make one condition */ 3237 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3238 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3239 return (err); 3240 m_head = *m_headp; 3241 } 3242 3243 retry: 3244 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3245 defrag: 3246 if (__predict_false(err)) { 3247 switch (err) { 3248 case EFBIG: 3249 /* try collapse once and defrag once */ 3250 if (remap == 0) { 3251 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3252 /* try defrag if collapsing fails */ 3253 if (m_head == NULL) 3254 remap++; 3255 } 3256 if (remap == 1) 3257 m_head = m_defrag(*m_headp, M_NOWAIT); 3258 remap++; 3259 if (__predict_false(m_head == NULL)) 3260 goto defrag_failed; 3261 txq->ift_mbuf_defrag++; 3262 *m_headp = m_head; 3263 goto retry; 3264 break; 3265 case ENOMEM: 3266 txq->ift_no_tx_dma_setup++; 3267 break; 3268 default: 3269 txq->ift_no_tx_dma_setup++; 3270 m_freem(*m_headp); 3271 DBG_COUNTER_INC(tx_frees); 3272 *m_headp = NULL; 3273 break; 3274 } 3275 txq->ift_map_failed++; 3276 DBG_COUNTER_INC(encap_load_mbuf_fail); 3277 return (err); 3278 } 3279 3280 /* 3281 * XXX assumes a 1 to 1 relationship between segments and 3282 * descriptors - this does not hold true on all drivers, e.g. 3283 * cxgb 3284 */ 3285 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3286 txq->ift_no_desc_avail++; 3287 if (map != NULL) 3288 bus_dmamap_unload(desc_tag, map); 3289 DBG_COUNTER_INC(encap_txq_avail_fail); 3290 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3291 GROUPTASK_ENQUEUE(&txq->ift_task); 3292 return (ENOBUFS); 3293 } 3294 /* 3295 * On Intel cards we can greatly reduce the number of TX interrupts 3296 * we see by only setting report status on every Nth descriptor. 3297 * However, this also means that the driver will need to keep track 3298 * of the descriptors that RS was set on to check them for the DD bit. 3299 */ 3300 txq->ift_rs_pending += nsegs + 1; 3301 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3302 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3303 pi.ipi_flags |= IPI_TX_INTR; 3304 txq->ift_rs_pending = 0; 3305 } 3306 3307 pi.ipi_segs = segs; 3308 pi.ipi_nsegs = nsegs; 3309 3310 MPASS(pidx >= 0 && pidx < txq->ift_size); 3311 #ifdef PKT_DEBUG 3312 print_pkt(&pi); 3313 #endif 3314 if (map != NULL) 3315 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3316 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3317 if (map != NULL) 3318 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3319 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3320 DBG_COUNTER_INC(tx_encap); 3321 MPASS(pi.ipi_new_pidx < txq->ift_size); 3322 3323 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3324 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3325 ndesc += txq->ift_size; 3326 txq->ift_gen = 1; 3327 } 3328 /* 3329 * drivers can need as many as 3330 * two sentinels 3331 */ 3332 MPASS(ndesc <= pi.ipi_nsegs + 2); 3333 MPASS(pi.ipi_new_pidx != pidx); 3334 MPASS(ndesc > 0); 3335 txq->ift_in_use += ndesc; 3336 3337 /* 3338 * We update the last software descriptor again here because there may 3339 * be a sentinel and/or there may be more mbufs than segments 3340 */ 3341 txq->ift_pidx = pi.ipi_new_pidx; 3342 txq->ift_npending += pi.ipi_ndescs; 3343 } else { 3344 *m_headp = m_head = iflib_remove_mbuf(txq); 3345 if (err == EFBIG) { 3346 txq->ift_txd_encap_efbig++; 3347 if (remap < 2) { 3348 remap = 1; 3349 goto defrag; 3350 } 3351 } 3352 DBG_COUNTER_INC(encap_txd_encap_fail); 3353 goto defrag_failed; 3354 } 3355 return (err); 3356 3357 defrag_failed: 3358 txq->ift_mbuf_defrag_failed++; 3359 txq->ift_map_failed++; 3360 m_freem(*m_headp); 3361 DBG_COUNTER_INC(tx_frees); 3362 *m_headp = NULL; 3363 return (ENOMEM); 3364 } 3365 3366 static void 3367 iflib_tx_desc_free(iflib_txq_t txq, int n) 3368 { 3369 int hasmap; 3370 uint32_t qsize, cidx, mask, gen; 3371 struct mbuf *m, **ifsd_m; 3372 uint8_t *ifsd_flags; 3373 bus_dmamap_t *ifsd_map; 3374 bool do_prefetch; 3375 3376 cidx = txq->ift_cidx; 3377 gen = txq->ift_gen; 3378 qsize = txq->ift_size; 3379 mask = qsize-1; 3380 hasmap = txq->ift_sds.ifsd_map != NULL; 3381 ifsd_flags = txq->ift_sds.ifsd_flags; 3382 ifsd_m = txq->ift_sds.ifsd_m; 3383 ifsd_map = txq->ift_sds.ifsd_map; 3384 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3385 3386 while (n-- > 0) { 3387 if (do_prefetch) { 3388 prefetch(ifsd_m[(cidx + 3) & mask]); 3389 prefetch(ifsd_m[(cidx + 4) & mask]); 3390 } 3391 if (ifsd_m[cidx] != NULL) { 3392 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3393 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3394 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3395 /* 3396 * does it matter if it's not the TSO tag? If so we'll 3397 * have to add the type to flags 3398 */ 3399 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3400 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3401 } 3402 if ((m = ifsd_m[cidx]) != NULL) { 3403 /* XXX we don't support any drivers that batch packets yet */ 3404 MPASS(m->m_nextpkt == NULL); 3405 /* if the number of clusters exceeds the number of segments 3406 * there won't be space on the ring to save a pointer to each 3407 * cluster so we simply free the list here 3408 */ 3409 if (m->m_flags & M_TOOBIG) { 3410 m_freem(m); 3411 } else { 3412 m_free(m); 3413 } 3414 ifsd_m[cidx] = NULL; 3415 #if MEMORY_LOGGING 3416 txq->ift_dequeued++; 3417 #endif 3418 DBG_COUNTER_INC(tx_frees); 3419 } 3420 } 3421 if (__predict_false(++cidx == qsize)) { 3422 cidx = 0; 3423 gen = 0; 3424 } 3425 } 3426 txq->ift_cidx = cidx; 3427 txq->ift_gen = gen; 3428 } 3429 3430 static __inline int 3431 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3432 { 3433 int reclaim; 3434 if_ctx_t ctx = txq->ift_ctx; 3435 3436 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3437 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3438 3439 /* 3440 * Need a rate-limiting check so that this isn't called every time 3441 */ 3442 iflib_tx_credits_update(ctx, txq); 3443 reclaim = DESC_RECLAIMABLE(txq); 3444 3445 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3446 #ifdef INVARIANTS 3447 if (iflib_verbose_debug) { 3448 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3449 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3450 reclaim, thresh); 3451 3452 } 3453 #endif 3454 return (0); 3455 } 3456 iflib_tx_desc_free(txq, reclaim); 3457 txq->ift_cleaned += reclaim; 3458 txq->ift_in_use -= reclaim; 3459 3460 return (reclaim); 3461 } 3462 3463 static struct mbuf ** 3464 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3465 { 3466 int next, size; 3467 struct mbuf **items; 3468 3469 size = r->size; 3470 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3471 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3472 3473 prefetch(items[(cidx + offset) & (size-1)]); 3474 if (remaining > 1) { 3475 prefetch2cachelines(&items[next]); 3476 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3477 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3478 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3479 } 3480 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3481 } 3482 3483 static void 3484 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3485 { 3486 3487 ifmp_ring_check_drainage(txq->ift_br, budget); 3488 } 3489 3490 static uint32_t 3491 iflib_txq_can_drain(struct ifmp_ring *r) 3492 { 3493 iflib_txq_t txq = r->cookie; 3494 if_ctx_t ctx = txq->ift_ctx; 3495 3496 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3497 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3498 } 3499 3500 static uint32_t 3501 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3502 { 3503 iflib_txq_t txq = r->cookie; 3504 if_ctx_t ctx = txq->ift_ctx; 3505 struct ifnet *ifp = ctx->ifc_ifp; 3506 struct mbuf **mp, *m; 3507 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3508 int reclaimed, err, in_use_prev, desc_used; 3509 bool do_prefetch, ring, rang; 3510 3511 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3512 !LINK_ACTIVE(ctx))) { 3513 DBG_COUNTER_INC(txq_drain_notready); 3514 return (0); 3515 } 3516 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3517 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3518 avail = IDXDIFF(pidx, cidx, r->size); 3519 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3520 DBG_COUNTER_INC(txq_drain_flushing); 3521 for (i = 0; i < avail; i++) { 3522 m_free(r->items[(cidx + i) & (r->size-1)]); 3523 r->items[(cidx + i) & (r->size-1)] = NULL; 3524 } 3525 return (avail); 3526 } 3527 3528 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3529 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3530 CALLOUT_LOCK(txq); 3531 callout_stop(&txq->ift_timer); 3532 CALLOUT_UNLOCK(txq); 3533 DBG_COUNTER_INC(txq_drain_oactive); 3534 return (0); 3535 } 3536 if (reclaimed) 3537 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3538 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3539 count = MIN(avail, TX_BATCH_SIZE); 3540 #ifdef INVARIANTS 3541 if (iflib_verbose_debug) 3542 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3543 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3544 #endif 3545 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3546 avail = TXQ_AVAIL(txq); 3547 err = 0; 3548 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3549 int rem = do_prefetch ? count - i : 0; 3550 3551 mp = _ring_peek_one(r, cidx, i, rem); 3552 MPASS(mp != NULL && *mp != NULL); 3553 if (__predict_false(*mp == (struct mbuf *)txq)) { 3554 consumed++; 3555 reclaimed++; 3556 continue; 3557 } 3558 in_use_prev = txq->ift_in_use; 3559 err = iflib_encap(txq, mp); 3560 if (__predict_false(err)) { 3561 DBG_COUNTER_INC(txq_drain_encapfail); 3562 /* no room - bail out */ 3563 if (err == ENOBUFS) 3564 break; 3565 consumed++; 3566 DBG_COUNTER_INC(txq_drain_encapfail); 3567 /* we can't send this packet - skip it */ 3568 continue; 3569 } 3570 consumed++; 3571 pkt_sent++; 3572 m = *mp; 3573 DBG_COUNTER_INC(tx_sent); 3574 bytes_sent += m->m_pkthdr.len; 3575 mcast_sent += !!(m->m_flags & M_MCAST); 3576 avail = TXQ_AVAIL(txq); 3577 3578 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3579 desc_used += (txq->ift_in_use - in_use_prev); 3580 ETHER_BPF_MTAP(ifp, m); 3581 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3582 break; 3583 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3584 } 3585 3586 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3587 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3588 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3589 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3590 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3591 if (mcast_sent) 3592 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3593 #ifdef INVARIANTS 3594 if (iflib_verbose_debug) 3595 printf("consumed=%d\n", consumed); 3596 #endif 3597 return (consumed); 3598 } 3599 3600 static uint32_t 3601 iflib_txq_drain_always(struct ifmp_ring *r) 3602 { 3603 return (1); 3604 } 3605 3606 static uint32_t 3607 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3608 { 3609 int i, avail; 3610 struct mbuf **mp; 3611 iflib_txq_t txq; 3612 3613 txq = r->cookie; 3614 3615 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3616 CALLOUT_LOCK(txq); 3617 callout_stop(&txq->ift_timer); 3618 CALLOUT_UNLOCK(txq); 3619 3620 avail = IDXDIFF(pidx, cidx, r->size); 3621 for (i = 0; i < avail; i++) { 3622 mp = _ring_peek_one(r, cidx, i, avail - i); 3623 if (__predict_false(*mp == (struct mbuf *)txq)) 3624 continue; 3625 m_freem(*mp); 3626 } 3627 MPASS(ifmp_ring_is_stalled(r) == 0); 3628 return (avail); 3629 } 3630 3631 static void 3632 iflib_ifmp_purge(iflib_txq_t txq) 3633 { 3634 struct ifmp_ring *r; 3635 3636 r = txq->ift_br; 3637 r->drain = iflib_txq_drain_free; 3638 r->can_drain = iflib_txq_drain_always; 3639 3640 ifmp_ring_check_drainage(r, r->size); 3641 3642 r->drain = iflib_txq_drain; 3643 r->can_drain = iflib_txq_can_drain; 3644 } 3645 3646 static void 3647 _task_fn_tx(void *context) 3648 { 3649 iflib_txq_t txq = context; 3650 if_ctx_t ctx = txq->ift_ctx; 3651 struct ifnet *ifp = ctx->ifc_ifp; 3652 3653 #ifdef IFLIB_DIAGNOSTICS 3654 txq->ift_cpu_exec_count[curcpu]++; 3655 #endif 3656 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3657 return; 3658 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3659 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3660 netmap_tx_irq(ifp, txq->ift_id); 3661 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3662 return; 3663 } 3664 if (txq->ift_db_pending) 3665 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); 3666 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3667 if (ctx->ifc_flags & IFC_LEGACY) 3668 IFDI_INTR_ENABLE(ctx); 3669 else { 3670 #ifdef INVARIANTS 3671 int rc = 3672 #endif 3673 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3674 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3675 } 3676 } 3677 3678 static void 3679 _task_fn_rx(void *context) 3680 { 3681 iflib_rxq_t rxq = context; 3682 if_ctx_t ctx = rxq->ifr_ctx; 3683 bool more; 3684 uint16_t budget; 3685 3686 #ifdef IFLIB_DIAGNOSTICS 3687 rxq->ifr_cpu_exec_count[curcpu]++; 3688 #endif 3689 DBG_COUNTER_INC(task_fn_rxs); 3690 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3691 return; 3692 more = true; 3693 #ifdef DEV_NETMAP 3694 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3695 u_int work = 0; 3696 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3697 more = false; 3698 } 3699 } 3700 #endif 3701 budget = ctx->ifc_sysctl_rx_budget; 3702 if (budget == 0) 3703 budget = 16; /* XXX */ 3704 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3705 if (ctx->ifc_flags & IFC_LEGACY) 3706 IFDI_INTR_ENABLE(ctx); 3707 else { 3708 #ifdef INVARIANTS 3709 int rc = 3710 #endif 3711 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3712 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3713 DBG_COUNTER_INC(rx_intr_enables); 3714 } 3715 } 3716 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3717 return; 3718 if (more) 3719 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3720 } 3721 3722 static void 3723 _task_fn_admin(void *context) 3724 { 3725 if_ctx_t ctx = context; 3726 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3727 iflib_txq_t txq; 3728 int i; 3729 bool oactive, running, do_reset, do_watchdog; 3730 3731 STATE_LOCK(ctx); 3732 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3733 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3734 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3735 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3736 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3737 STATE_UNLOCK(ctx); 3738 3739 if (!running & !oactive) 3740 return; 3741 3742 CTX_LOCK(ctx); 3743 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3744 CALLOUT_LOCK(txq); 3745 callout_stop(&txq->ift_timer); 3746 CALLOUT_UNLOCK(txq); 3747 } 3748 if (do_watchdog) { 3749 ctx->ifc_watchdog_events++; 3750 IFDI_WATCHDOG_RESET(ctx); 3751 } 3752 IFDI_UPDATE_ADMIN_STATUS(ctx); 3753 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3754 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 3755 IFDI_LINK_INTR_ENABLE(ctx); 3756 if (do_reset) 3757 iflib_if_init_locked(ctx); 3758 CTX_UNLOCK(ctx); 3759 3760 if (LINK_ACTIVE(ctx) == 0) 3761 return; 3762 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3763 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3764 } 3765 3766 3767 static void 3768 _task_fn_iov(void *context) 3769 { 3770 if_ctx_t ctx = context; 3771 3772 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3773 return; 3774 3775 CTX_LOCK(ctx); 3776 IFDI_VFLR_HANDLE(ctx); 3777 CTX_UNLOCK(ctx); 3778 } 3779 3780 static int 3781 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3782 { 3783 int err; 3784 if_int_delay_info_t info; 3785 if_ctx_t ctx; 3786 3787 info = (if_int_delay_info_t)arg1; 3788 ctx = info->iidi_ctx; 3789 info->iidi_req = req; 3790 info->iidi_oidp = oidp; 3791 CTX_LOCK(ctx); 3792 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3793 CTX_UNLOCK(ctx); 3794 return (err); 3795 } 3796 3797 /********************************************************************* 3798 * 3799 * IFNET FUNCTIONS 3800 * 3801 **********************************************************************/ 3802 3803 static void 3804 iflib_if_init_locked(if_ctx_t ctx) 3805 { 3806 iflib_stop(ctx); 3807 iflib_init_locked(ctx); 3808 } 3809 3810 3811 static void 3812 iflib_if_init(void *arg) 3813 { 3814 if_ctx_t ctx = arg; 3815 3816 CTX_LOCK(ctx); 3817 iflib_if_init_locked(ctx); 3818 CTX_UNLOCK(ctx); 3819 } 3820 3821 static int 3822 iflib_if_transmit(if_t ifp, struct mbuf *m) 3823 { 3824 if_ctx_t ctx = if_getsoftc(ifp); 3825 3826 iflib_txq_t txq; 3827 int err, qidx; 3828 3829 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3830 DBG_COUNTER_INC(tx_frees); 3831 m_freem(m); 3832 return (ENOBUFS); 3833 } 3834 3835 MPASS(m->m_nextpkt == NULL); 3836 qidx = 0; 3837 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3838 qidx = QIDX(ctx, m); 3839 /* 3840 * XXX calculate buf_ring based on flowid (divvy up bits?) 3841 */ 3842 txq = &ctx->ifc_txqs[qidx]; 3843 3844 #ifdef DRIVER_BACKPRESSURE 3845 if (txq->ift_closed) { 3846 while (m != NULL) { 3847 next = m->m_nextpkt; 3848 m->m_nextpkt = NULL; 3849 m_freem(m); 3850 m = next; 3851 } 3852 return (ENOBUFS); 3853 } 3854 #endif 3855 #ifdef notyet 3856 qidx = count = 0; 3857 mp = marr; 3858 next = m; 3859 do { 3860 count++; 3861 next = next->m_nextpkt; 3862 } while (next != NULL); 3863 3864 if (count > nitems(marr)) 3865 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3866 /* XXX check nextpkt */ 3867 m_freem(m); 3868 /* XXX simplify for now */ 3869 DBG_COUNTER_INC(tx_frees); 3870 return (ENOBUFS); 3871 } 3872 for (next = m, i = 0; next != NULL; i++) { 3873 mp[i] = next; 3874 next = next->m_nextpkt; 3875 mp[i]->m_nextpkt = NULL; 3876 } 3877 #endif 3878 DBG_COUNTER_INC(tx_seen); 3879 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); 3880 3881 GROUPTASK_ENQUEUE(&txq->ift_task); 3882 if (err) { 3883 /* support forthcoming later */ 3884 #ifdef DRIVER_BACKPRESSURE 3885 txq->ift_closed = TRUE; 3886 #endif 3887 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3888 m_freem(m); 3889 } 3890 3891 return (err); 3892 } 3893 3894 static void 3895 iflib_if_qflush(if_t ifp) 3896 { 3897 if_ctx_t ctx = if_getsoftc(ifp); 3898 iflib_txq_t txq = ctx->ifc_txqs; 3899 int i; 3900 3901 STATE_LOCK(ctx); 3902 ctx->ifc_flags |= IFC_QFLUSH; 3903 STATE_UNLOCK(ctx); 3904 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3905 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3906 iflib_txq_check_drain(txq, 0); 3907 STATE_LOCK(ctx); 3908 ctx->ifc_flags &= ~IFC_QFLUSH; 3909 STATE_UNLOCK(ctx); 3910 3911 if_qflush(ifp); 3912 } 3913 3914 3915 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3916 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 3917 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 3918 3919 static int 3920 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 3921 { 3922 if_ctx_t ctx = if_getsoftc(ifp); 3923 struct ifreq *ifr = (struct ifreq *)data; 3924 #if defined(INET) || defined(INET6) 3925 struct ifaddr *ifa = (struct ifaddr *)data; 3926 #endif 3927 bool avoid_reset = FALSE; 3928 int err = 0, reinit = 0, bits; 3929 3930 switch (command) { 3931 case SIOCSIFADDR: 3932 #ifdef INET 3933 if (ifa->ifa_addr->sa_family == AF_INET) 3934 avoid_reset = TRUE; 3935 #endif 3936 #ifdef INET6 3937 if (ifa->ifa_addr->sa_family == AF_INET6) 3938 avoid_reset = TRUE; 3939 #endif 3940 /* 3941 ** Calling init results in link renegotiation, 3942 ** so we avoid doing it when possible. 3943 */ 3944 if (avoid_reset) { 3945 if_setflagbits(ifp, IFF_UP,0); 3946 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING)) 3947 reinit = 1; 3948 #ifdef INET 3949 if (!(if_getflags(ifp) & IFF_NOARP)) 3950 arp_ifinit(ifp, ifa); 3951 #endif 3952 } else 3953 err = ether_ioctl(ifp, command, data); 3954 break; 3955 case SIOCSIFMTU: 3956 CTX_LOCK(ctx); 3957 if (ifr->ifr_mtu == if_getmtu(ifp)) { 3958 CTX_UNLOCK(ctx); 3959 break; 3960 } 3961 bits = if_getdrvflags(ifp); 3962 /* stop the driver and free any clusters before proceeding */ 3963 iflib_stop(ctx); 3964 3965 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 3966 STATE_LOCK(ctx); 3967 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 3968 ctx->ifc_flags |= IFC_MULTISEG; 3969 else 3970 ctx->ifc_flags &= ~IFC_MULTISEG; 3971 STATE_UNLOCK(ctx); 3972 err = if_setmtu(ifp, ifr->ifr_mtu); 3973 } 3974 iflib_init_locked(ctx); 3975 STATE_LOCK(ctx); 3976 if_setdrvflags(ifp, bits); 3977 STATE_UNLOCK(ctx); 3978 CTX_UNLOCK(ctx); 3979 break; 3980 case SIOCSIFFLAGS: 3981 CTX_LOCK(ctx); 3982 if (if_getflags(ifp) & IFF_UP) { 3983 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3984 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 3985 (IFF_PROMISC | IFF_ALLMULTI)) { 3986 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 3987 } 3988 } else 3989 reinit = 1; 3990 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3991 iflib_stop(ctx); 3992 } 3993 ctx->ifc_if_flags = if_getflags(ifp); 3994 CTX_UNLOCK(ctx); 3995 break; 3996 case SIOCADDMULTI: 3997 case SIOCDELMULTI: 3998 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3999 CTX_LOCK(ctx); 4000 IFDI_INTR_DISABLE(ctx); 4001 IFDI_MULTI_SET(ctx); 4002 IFDI_INTR_ENABLE(ctx); 4003 CTX_UNLOCK(ctx); 4004 } 4005 break; 4006 case SIOCSIFMEDIA: 4007 CTX_LOCK(ctx); 4008 IFDI_MEDIA_SET(ctx); 4009 CTX_UNLOCK(ctx); 4010 /* falls thru */ 4011 case SIOCGIFMEDIA: 4012 case SIOCGIFXMEDIA: 4013 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 4014 break; 4015 case SIOCGI2C: 4016 { 4017 struct ifi2creq i2c; 4018 4019 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4020 if (err != 0) 4021 break; 4022 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4023 err = EINVAL; 4024 break; 4025 } 4026 if (i2c.len > sizeof(i2c.data)) { 4027 err = EINVAL; 4028 break; 4029 } 4030 4031 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4032 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4033 sizeof(i2c)); 4034 break; 4035 } 4036 case SIOCSIFCAP: 4037 { 4038 int mask, setmask; 4039 4040 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 4041 setmask = 0; 4042 #ifdef TCP_OFFLOAD 4043 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4044 #endif 4045 setmask |= (mask & IFCAP_FLAGS); 4046 4047 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 4048 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4049 if ((mask & IFCAP_WOL) && 4050 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 4051 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 4052 if_vlancap(ifp); 4053 /* 4054 * want to ensure that traffic has stopped before we change any of the flags 4055 */ 4056 if (setmask) { 4057 CTX_LOCK(ctx); 4058 bits = if_getdrvflags(ifp); 4059 if (bits & IFF_DRV_RUNNING) 4060 iflib_stop(ctx); 4061 STATE_LOCK(ctx); 4062 if_togglecapenable(ifp, setmask); 4063 STATE_UNLOCK(ctx); 4064 if (bits & IFF_DRV_RUNNING) 4065 iflib_init_locked(ctx); 4066 STATE_LOCK(ctx); 4067 if_setdrvflags(ifp, bits); 4068 STATE_UNLOCK(ctx); 4069 CTX_UNLOCK(ctx); 4070 } 4071 break; 4072 } 4073 case SIOCGPRIVATE_0: 4074 case SIOCSDRVSPEC: 4075 case SIOCGDRVSPEC: 4076 CTX_LOCK(ctx); 4077 err = IFDI_PRIV_IOCTL(ctx, command, data); 4078 CTX_UNLOCK(ctx); 4079 break; 4080 default: 4081 err = ether_ioctl(ifp, command, data); 4082 break; 4083 } 4084 if (reinit) 4085 iflib_if_init(ctx); 4086 return (err); 4087 } 4088 4089 static uint64_t 4090 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4091 { 4092 if_ctx_t ctx = if_getsoftc(ifp); 4093 4094 return (IFDI_GET_COUNTER(ctx, cnt)); 4095 } 4096 4097 /********************************************************************* 4098 * 4099 * OTHER FUNCTIONS EXPORTED TO THE STACK 4100 * 4101 **********************************************************************/ 4102 4103 static void 4104 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4105 { 4106 if_ctx_t ctx = if_getsoftc(ifp); 4107 4108 if ((void *)ctx != arg) 4109 return; 4110 4111 if ((vtag == 0) || (vtag > 4095)) 4112 return; 4113 4114 CTX_LOCK(ctx); 4115 IFDI_VLAN_REGISTER(ctx, vtag); 4116 /* Re-init to load the changes */ 4117 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4118 iflib_if_init_locked(ctx); 4119 CTX_UNLOCK(ctx); 4120 } 4121 4122 static void 4123 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4124 { 4125 if_ctx_t ctx = if_getsoftc(ifp); 4126 4127 if ((void *)ctx != arg) 4128 return; 4129 4130 if ((vtag == 0) || (vtag > 4095)) 4131 return; 4132 4133 CTX_LOCK(ctx); 4134 IFDI_VLAN_UNREGISTER(ctx, vtag); 4135 /* Re-init to load the changes */ 4136 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4137 iflib_if_init_locked(ctx); 4138 CTX_UNLOCK(ctx); 4139 } 4140 4141 static void 4142 iflib_led_func(void *arg, int onoff) 4143 { 4144 if_ctx_t ctx = arg; 4145 4146 CTX_LOCK(ctx); 4147 IFDI_LED_FUNC(ctx, onoff); 4148 CTX_UNLOCK(ctx); 4149 } 4150 4151 /********************************************************************* 4152 * 4153 * BUS FUNCTION DEFINITIONS 4154 * 4155 **********************************************************************/ 4156 4157 int 4158 iflib_device_probe(device_t dev) 4159 { 4160 pci_vendor_info_t *ent; 4161 4162 uint16_t pci_vendor_id, pci_device_id; 4163 uint16_t pci_subvendor_id, pci_subdevice_id; 4164 uint16_t pci_rev_id; 4165 if_shared_ctx_t sctx; 4166 4167 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4168 return (ENOTSUP); 4169 4170 pci_vendor_id = pci_get_vendor(dev); 4171 pci_device_id = pci_get_device(dev); 4172 pci_subvendor_id = pci_get_subvendor(dev); 4173 pci_subdevice_id = pci_get_subdevice(dev); 4174 pci_rev_id = pci_get_revid(dev); 4175 if (sctx->isc_parse_devinfo != NULL) 4176 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4177 4178 ent = sctx->isc_vendor_info; 4179 while (ent->pvi_vendor_id != 0) { 4180 if (pci_vendor_id != ent->pvi_vendor_id) { 4181 ent++; 4182 continue; 4183 } 4184 if ((pci_device_id == ent->pvi_device_id) && 4185 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4186 (ent->pvi_subvendor_id == 0)) && 4187 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4188 (ent->pvi_subdevice_id == 0)) && 4189 ((pci_rev_id == ent->pvi_rev_id) || 4190 (ent->pvi_rev_id == 0))) { 4191 4192 device_set_desc_copy(dev, ent->pvi_name); 4193 /* this needs to be changed to zero if the bus probing code 4194 * ever stops re-probing on best match because the sctx 4195 * may have its values over written by register calls 4196 * in subsequent probes 4197 */ 4198 return (BUS_PROBE_DEFAULT); 4199 } 4200 ent++; 4201 } 4202 return (ENXIO); 4203 } 4204 4205 int 4206 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4207 { 4208 int err, rid, msix; 4209 if_ctx_t ctx; 4210 if_t ifp; 4211 if_softc_ctx_t scctx; 4212 int i; 4213 uint16_t main_txq; 4214 uint16_t main_rxq; 4215 4216 4217 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4218 4219 if (sc == NULL) { 4220 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4221 device_set_softc(dev, ctx); 4222 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4223 } 4224 4225 ctx->ifc_sctx = sctx; 4226 ctx->ifc_dev = dev; 4227 ctx->ifc_softc = sc; 4228 4229 if ((err = iflib_register(ctx)) != 0) { 4230 device_printf(dev, "iflib_register failed %d\n", err); 4231 return (err); 4232 } 4233 iflib_add_device_sysctl_pre(ctx); 4234 4235 scctx = &ctx->ifc_softc_ctx; 4236 ifp = ctx->ifc_ifp; 4237 ctx->ifc_nhwtxqs = sctx->isc_ntxqs; 4238 4239 /* 4240 * XXX sanity check that ntxd & nrxd are a power of 2 4241 */ 4242 if (ctx->ifc_sysctl_ntxqs != 0) 4243 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4244 if (ctx->ifc_sysctl_nrxqs != 0) 4245 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4246 4247 for (i = 0; i < sctx->isc_ntxqs; i++) { 4248 if (ctx->ifc_sysctl_ntxds[i] != 0) 4249 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4250 else 4251 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4252 } 4253 4254 for (i = 0; i < sctx->isc_nrxqs; i++) { 4255 if (ctx->ifc_sysctl_nrxds[i] != 0) 4256 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4257 else 4258 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4259 } 4260 4261 for (i = 0; i < sctx->isc_nrxqs; i++) { 4262 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4263 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4264 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4265 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4266 } 4267 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4268 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4269 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4270 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4271 } 4272 } 4273 4274 for (i = 0; i < sctx->isc_ntxqs; i++) { 4275 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4276 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4277 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4278 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4279 } 4280 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4281 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4282 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4283 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4284 } 4285 } 4286 4287 CTX_LOCK(ctx); 4288 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4289 CTX_UNLOCK(ctx); 4290 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4291 return (err); 4292 } 4293 _iflib_pre_assert(scctx); 4294 ctx->ifc_txrx = *scctx->isc_txrx; 4295 4296 #ifdef INVARIANTS 4297 MPASS(scctx->isc_capenable); 4298 if (scctx->isc_capenable & IFCAP_TXCSUM) 4299 MPASS(scctx->isc_tx_csum_flags); 4300 #endif 4301 4302 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4303 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4304 4305 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4306 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4307 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4308 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4309 4310 #ifdef ACPI_DMAR 4311 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4312 ctx->ifc_flags |= IFC_DMAR; 4313 #elif !(defined(__i386__) || defined(__amd64__)) 4314 /* set unconditionally for !x86 */ 4315 ctx->ifc_flags |= IFC_DMAR; 4316 #endif 4317 4318 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4319 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4320 4321 /* XXX change for per-queue sizes */ 4322 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4323 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4324 for (i = 0; i < sctx->isc_nrxqs; i++) { 4325 if (!powerof2(scctx->isc_nrxd[i])) { 4326 /* round down instead? */ 4327 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4328 err = EINVAL; 4329 goto fail; 4330 } 4331 } 4332 for (i = 0; i < sctx->isc_ntxqs; i++) { 4333 if (!powerof2(scctx->isc_ntxd[i])) { 4334 device_printf(dev, 4335 "# tx descriptors must be a power of 2"); 4336 err = EINVAL; 4337 goto fail; 4338 } 4339 } 4340 4341 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4342 MAX_SINGLE_PACKET_FRACTION) 4343 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4344 MAX_SINGLE_PACKET_FRACTION); 4345 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4346 MAX_SINGLE_PACKET_FRACTION) 4347 scctx->isc_tx_tso_segments_max = max(1, 4348 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4349 4350 /* 4351 * Protect the stack against modern hardware 4352 */ 4353 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4354 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4355 4356 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4357 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4358 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4359 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4360 if (scctx->isc_rss_table_size == 0) 4361 scctx->isc_rss_table_size = 64; 4362 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4363 4364 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4365 /* XXX format name */ 4366 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4367 4368 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4369 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4370 device_printf(dev, "Unable to fetch CPU list\n"); 4371 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4372 } 4373 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4374 4375 /* 4376 ** Now setup MSI or MSI/X, should 4377 ** return us the number of supported 4378 ** vectors. (Will be 1 for MSI) 4379 */ 4380 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4381 msix = scctx->isc_vectors; 4382 } else if (scctx->isc_msix_bar != 0) 4383 /* 4384 * The simple fact that isc_msix_bar is not 0 does not mean we 4385 * we have a good value there that is known to work. 4386 */ 4387 msix = iflib_msix_init(ctx); 4388 else { 4389 scctx->isc_vectors = 1; 4390 scctx->isc_ntxqsets = 1; 4391 scctx->isc_nrxqsets = 1; 4392 scctx->isc_intr = IFLIB_INTR_LEGACY; 4393 msix = 0; 4394 } 4395 /* Get memory for the station queues */ 4396 if ((err = iflib_queues_alloc(ctx))) { 4397 device_printf(dev, "Unable to allocate queue memory\n"); 4398 goto fail; 4399 } 4400 4401 if ((err = iflib_qset_structures_setup(ctx))) 4402 goto fail_queues; 4403 4404 /* 4405 * Group taskqueues aren't properly set up until SMP is started, 4406 * so we disable interrupts until we can handle them post 4407 * SI_SUB_SMP. 4408 * 4409 * XXX: disabling interrupts doesn't actually work, at least for 4410 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4411 * we do null handling and depend on this not causing too large an 4412 * interrupt storm. 4413 */ 4414 IFDI_INTR_DISABLE(ctx); 4415 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4416 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4417 goto fail_intr_free; 4418 } 4419 if (msix <= 1) { 4420 rid = 0; 4421 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4422 MPASS(msix == 1); 4423 rid = 1; 4424 } 4425 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4426 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4427 goto fail_intr_free; 4428 } 4429 } 4430 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4431 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4432 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4433 goto fail_detach; 4434 } 4435 if ((err = iflib_netmap_attach(ctx))) { 4436 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4437 goto fail_detach; 4438 } 4439 *ctxp = ctx; 4440 4441 NETDUMP_SET(ctx->ifc_ifp, iflib); 4442 4443 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4444 iflib_add_device_sysctl_post(ctx); 4445 ctx->ifc_flags |= IFC_INIT_DONE; 4446 CTX_UNLOCK(ctx); 4447 return (0); 4448 fail_detach: 4449 ether_ifdetach(ctx->ifc_ifp); 4450 fail_intr_free: 4451 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4452 pci_release_msi(ctx->ifc_dev); 4453 fail_queues: 4454 iflib_tx_structures_free(ctx); 4455 iflib_rx_structures_free(ctx); 4456 fail: 4457 IFDI_DETACH(ctx); 4458 CTX_UNLOCK(ctx); 4459 return (err); 4460 } 4461 4462 int 4463 iflib_device_attach(device_t dev) 4464 { 4465 if_ctx_t ctx; 4466 if_shared_ctx_t sctx; 4467 4468 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4469 return (ENOTSUP); 4470 4471 pci_enable_busmaster(dev); 4472 4473 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4474 } 4475 4476 int 4477 iflib_device_deregister(if_ctx_t ctx) 4478 { 4479 if_t ifp = ctx->ifc_ifp; 4480 iflib_txq_t txq; 4481 iflib_rxq_t rxq; 4482 device_t dev = ctx->ifc_dev; 4483 int i, j; 4484 struct taskqgroup *tqg; 4485 iflib_fl_t fl; 4486 4487 /* Make sure VLANS are not using driver */ 4488 if (if_vlantrunkinuse(ifp)) { 4489 device_printf(dev,"Vlan in use, detach first\n"); 4490 return (EBUSY); 4491 } 4492 4493 CTX_LOCK(ctx); 4494 ctx->ifc_in_detach = 1; 4495 iflib_stop(ctx); 4496 CTX_UNLOCK(ctx); 4497 4498 /* Unregister VLAN events */ 4499 if (ctx->ifc_vlan_attach_event != NULL) 4500 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4501 if (ctx->ifc_vlan_detach_event != NULL) 4502 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4503 4504 iflib_netmap_detach(ifp); 4505 ether_ifdetach(ifp); 4506 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4507 CTX_LOCK_DESTROY(ctx); 4508 if (ctx->ifc_led_dev != NULL) 4509 led_destroy(ctx->ifc_led_dev); 4510 /* XXX drain any dependent tasks */ 4511 tqg = qgroup_if_io_tqg; 4512 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4513 callout_drain(&txq->ift_timer); 4514 if (txq->ift_task.gt_uniq != NULL) 4515 taskqgroup_detach(tqg, &txq->ift_task); 4516 } 4517 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4518 if (rxq->ifr_task.gt_uniq != NULL) 4519 taskqgroup_detach(tqg, &rxq->ifr_task); 4520 4521 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4522 free(fl->ifl_rx_bitmap, M_IFLIB); 4523 4524 } 4525 tqg = qgroup_if_config_tqg; 4526 if (ctx->ifc_admin_task.gt_uniq != NULL) 4527 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4528 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4529 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4530 4531 IFDI_DETACH(ctx); 4532 device_set_softc(ctx->ifc_dev, NULL); 4533 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4534 pci_release_msi(dev); 4535 } 4536 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4537 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4538 } 4539 if (ctx->ifc_msix_mem != NULL) { 4540 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4541 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4542 ctx->ifc_msix_mem = NULL; 4543 } 4544 4545 bus_generic_detach(dev); 4546 if_free(ifp); 4547 4548 iflib_tx_structures_free(ctx); 4549 iflib_rx_structures_free(ctx); 4550 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4551 free(ctx->ifc_softc, M_IFLIB); 4552 free(ctx, M_IFLIB); 4553 return (0); 4554 } 4555 4556 4557 int 4558 iflib_device_detach(device_t dev) 4559 { 4560 if_ctx_t ctx = device_get_softc(dev); 4561 4562 return (iflib_device_deregister(ctx)); 4563 } 4564 4565 int 4566 iflib_device_suspend(device_t dev) 4567 { 4568 if_ctx_t ctx = device_get_softc(dev); 4569 4570 CTX_LOCK(ctx); 4571 IFDI_SUSPEND(ctx); 4572 CTX_UNLOCK(ctx); 4573 4574 return bus_generic_suspend(dev); 4575 } 4576 int 4577 iflib_device_shutdown(device_t dev) 4578 { 4579 if_ctx_t ctx = device_get_softc(dev); 4580 4581 CTX_LOCK(ctx); 4582 IFDI_SHUTDOWN(ctx); 4583 CTX_UNLOCK(ctx); 4584 4585 return bus_generic_suspend(dev); 4586 } 4587 4588 4589 int 4590 iflib_device_resume(device_t dev) 4591 { 4592 if_ctx_t ctx = device_get_softc(dev); 4593 iflib_txq_t txq = ctx->ifc_txqs; 4594 4595 CTX_LOCK(ctx); 4596 IFDI_RESUME(ctx); 4597 iflib_init_locked(ctx); 4598 CTX_UNLOCK(ctx); 4599 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4600 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4601 4602 return (bus_generic_resume(dev)); 4603 } 4604 4605 int 4606 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4607 { 4608 int error; 4609 if_ctx_t ctx = device_get_softc(dev); 4610 4611 CTX_LOCK(ctx); 4612 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4613 CTX_UNLOCK(ctx); 4614 4615 return (error); 4616 } 4617 4618 void 4619 iflib_device_iov_uninit(device_t dev) 4620 { 4621 if_ctx_t ctx = device_get_softc(dev); 4622 4623 CTX_LOCK(ctx); 4624 IFDI_IOV_UNINIT(ctx); 4625 CTX_UNLOCK(ctx); 4626 } 4627 4628 int 4629 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 4630 { 4631 int error; 4632 if_ctx_t ctx = device_get_softc(dev); 4633 4634 CTX_LOCK(ctx); 4635 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 4636 CTX_UNLOCK(ctx); 4637 4638 return (error); 4639 } 4640 4641 /********************************************************************* 4642 * 4643 * MODULE FUNCTION DEFINITIONS 4644 * 4645 **********************************************************************/ 4646 4647 /* 4648 * - Start a fast taskqueue thread for each core 4649 * - Start a taskqueue for control operations 4650 */ 4651 static int 4652 iflib_module_init(void) 4653 { 4654 return (0); 4655 } 4656 4657 static int 4658 iflib_module_event_handler(module_t mod, int what, void *arg) 4659 { 4660 int err; 4661 4662 switch (what) { 4663 case MOD_LOAD: 4664 if ((err = iflib_module_init()) != 0) 4665 return (err); 4666 break; 4667 case MOD_UNLOAD: 4668 return (EBUSY); 4669 default: 4670 return (EOPNOTSUPP); 4671 } 4672 4673 return (0); 4674 } 4675 4676 /********************************************************************* 4677 * 4678 * PUBLIC FUNCTION DEFINITIONS 4679 * ordered as in iflib.h 4680 * 4681 **********************************************************************/ 4682 4683 4684 static void 4685 _iflib_assert(if_shared_ctx_t sctx) 4686 { 4687 MPASS(sctx->isc_tx_maxsize); 4688 MPASS(sctx->isc_tx_maxsegsize); 4689 4690 MPASS(sctx->isc_rx_maxsize); 4691 MPASS(sctx->isc_rx_nsegments); 4692 MPASS(sctx->isc_rx_maxsegsize); 4693 4694 MPASS(sctx->isc_nrxd_min[0]); 4695 MPASS(sctx->isc_nrxd_max[0]); 4696 MPASS(sctx->isc_nrxd_default[0]); 4697 MPASS(sctx->isc_ntxd_min[0]); 4698 MPASS(sctx->isc_ntxd_max[0]); 4699 MPASS(sctx->isc_ntxd_default[0]); 4700 } 4701 4702 static void 4703 _iflib_pre_assert(if_softc_ctx_t scctx) 4704 { 4705 4706 MPASS(scctx->isc_txrx->ift_txd_encap); 4707 MPASS(scctx->isc_txrx->ift_txd_flush); 4708 MPASS(scctx->isc_txrx->ift_txd_credits_update); 4709 MPASS(scctx->isc_txrx->ift_rxd_available); 4710 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 4711 MPASS(scctx->isc_txrx->ift_rxd_refill); 4712 MPASS(scctx->isc_txrx->ift_rxd_flush); 4713 } 4714 4715 static int 4716 iflib_register(if_ctx_t ctx) 4717 { 4718 if_shared_ctx_t sctx = ctx->ifc_sctx; 4719 driver_t *driver = sctx->isc_driver; 4720 device_t dev = ctx->ifc_dev; 4721 if_t ifp; 4722 4723 _iflib_assert(sctx); 4724 4725 CTX_LOCK_INIT(ctx); 4726 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 4727 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 4728 if (ifp == NULL) { 4729 device_printf(dev, "can not allocate ifnet structure\n"); 4730 return (ENOMEM); 4731 } 4732 4733 /* 4734 * Initialize our context's device specific methods 4735 */ 4736 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 4737 kobj_class_compile((kobj_class_t) driver); 4738 driver->refs++; 4739 4740 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 4741 if_setsoftc(ifp, ctx); 4742 if_setdev(ifp, dev); 4743 if_setinitfn(ifp, iflib_if_init); 4744 if_setioctlfn(ifp, iflib_if_ioctl); 4745 if_settransmitfn(ifp, iflib_if_transmit); 4746 if_setqflushfn(ifp, iflib_if_qflush); 4747 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 4748 4749 ctx->ifc_vlan_attach_event = 4750 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 4751 EVENTHANDLER_PRI_FIRST); 4752 ctx->ifc_vlan_detach_event = 4753 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 4754 EVENTHANDLER_PRI_FIRST); 4755 4756 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 4757 iflib_media_change, iflib_media_status); 4758 4759 return (0); 4760 } 4761 4762 4763 static int 4764 iflib_queues_alloc(if_ctx_t ctx) 4765 { 4766 if_shared_ctx_t sctx = ctx->ifc_sctx; 4767 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4768 device_t dev = ctx->ifc_dev; 4769 int nrxqsets = scctx->isc_nrxqsets; 4770 int ntxqsets = scctx->isc_ntxqsets; 4771 iflib_txq_t txq; 4772 iflib_rxq_t rxq; 4773 iflib_fl_t fl = NULL; 4774 int i, j, cpu, err, txconf, rxconf; 4775 iflib_dma_info_t ifdip; 4776 uint32_t *rxqsizes = scctx->isc_rxqsizes; 4777 uint32_t *txqsizes = scctx->isc_txqsizes; 4778 uint8_t nrxqs = sctx->isc_nrxqs; 4779 uint8_t ntxqs = sctx->isc_ntxqs; 4780 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 4781 caddr_t *vaddrs; 4782 uint64_t *paddrs; 4783 4784 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 4785 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 4786 4787 /* Allocate the TX ring struct memory */ 4788 if (!(ctx->ifc_txqs = 4789 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 4790 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4791 device_printf(dev, "Unable to allocate TX ring memory\n"); 4792 err = ENOMEM; 4793 goto fail; 4794 } 4795 4796 /* Now allocate the RX */ 4797 if (!(ctx->ifc_rxqs = 4798 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 4799 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4800 device_printf(dev, "Unable to allocate RX ring memory\n"); 4801 err = ENOMEM; 4802 goto rx_fail; 4803 } 4804 4805 txq = ctx->ifc_txqs; 4806 rxq = ctx->ifc_rxqs; 4807 4808 /* 4809 * XXX handle allocation failure 4810 */ 4811 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 4812 /* Set up some basics */ 4813 4814 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4815 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4816 err = ENOMEM; 4817 goto err_tx_desc; 4818 } 4819 txq->ift_ifdi = ifdip; 4820 for (j = 0; j < ntxqs; j++, ifdip++) { 4821 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4822 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4823 err = ENOMEM; 4824 goto err_tx_desc; 4825 } 4826 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 4827 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 4828 } 4829 txq->ift_ctx = ctx; 4830 txq->ift_id = i; 4831 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 4832 txq->ift_br_offset = 1; 4833 } else { 4834 txq->ift_br_offset = 0; 4835 } 4836 /* XXX fix this */ 4837 txq->ift_timer.c_cpu = cpu; 4838 4839 if (iflib_txsd_alloc(txq)) { 4840 device_printf(dev, "Critical Failure setting up TX buffers\n"); 4841 err = ENOMEM; 4842 goto err_tx_desc; 4843 } 4844 4845 /* Initialize the TX lock */ 4846 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 4847 device_get_nameunit(dev), txq->ift_id); 4848 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 4849 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 4850 4851 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 4852 device_get_nameunit(dev), txq->ift_id); 4853 4854 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 4855 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 4856 if (err) { 4857 /* XXX free any allocated rings */ 4858 device_printf(dev, "Unable to allocate buf_ring\n"); 4859 goto err_tx_desc; 4860 } 4861 } 4862 4863 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 4864 /* Set up some basics */ 4865 4866 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4867 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4868 err = ENOMEM; 4869 goto err_tx_desc; 4870 } 4871 4872 rxq->ifr_ifdi = ifdip; 4873 /* XXX this needs to be changed if #rx queues != #tx queues */ 4874 rxq->ifr_ntxqirq = 1; 4875 rxq->ifr_txqid[0] = i; 4876 for (j = 0; j < nrxqs; j++, ifdip++) { 4877 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4878 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4879 err = ENOMEM; 4880 goto err_tx_desc; 4881 } 4882 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 4883 } 4884 rxq->ifr_ctx = ctx; 4885 rxq->ifr_id = i; 4886 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 4887 rxq->ifr_fl_offset = 1; 4888 } else { 4889 rxq->ifr_fl_offset = 0; 4890 } 4891 rxq->ifr_nfl = nfree_lists; 4892 if (!(fl = 4893 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 4894 device_printf(dev, "Unable to allocate free list memory\n"); 4895 err = ENOMEM; 4896 goto err_tx_desc; 4897 } 4898 rxq->ifr_fl = fl; 4899 for (j = 0; j < nfree_lists; j++) { 4900 fl[j].ifl_rxq = rxq; 4901 fl[j].ifl_id = j; 4902 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 4903 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 4904 } 4905 /* Allocate receive buffers for the ring*/ 4906 if (iflib_rxsd_alloc(rxq)) { 4907 device_printf(dev, 4908 "Critical Failure setting up receive buffers\n"); 4909 err = ENOMEM; 4910 goto err_rx_desc; 4911 } 4912 4913 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4914 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 4915 } 4916 4917 /* TXQs */ 4918 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4919 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4920 for (i = 0; i < ntxqsets; i++) { 4921 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 4922 4923 for (j = 0; j < ntxqs; j++, di++) { 4924 vaddrs[i*ntxqs + j] = di->idi_vaddr; 4925 paddrs[i*ntxqs + j] = di->idi_paddr; 4926 } 4927 } 4928 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 4929 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4930 iflib_tx_structures_free(ctx); 4931 free(vaddrs, M_IFLIB); 4932 free(paddrs, M_IFLIB); 4933 goto err_rx_desc; 4934 } 4935 free(vaddrs, M_IFLIB); 4936 free(paddrs, M_IFLIB); 4937 4938 /* RXQs */ 4939 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4940 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4941 for (i = 0; i < nrxqsets; i++) { 4942 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 4943 4944 for (j = 0; j < nrxqs; j++, di++) { 4945 vaddrs[i*nrxqs + j] = di->idi_vaddr; 4946 paddrs[i*nrxqs + j] = di->idi_paddr; 4947 } 4948 } 4949 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 4950 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4951 iflib_tx_structures_free(ctx); 4952 free(vaddrs, M_IFLIB); 4953 free(paddrs, M_IFLIB); 4954 goto err_rx_desc; 4955 } 4956 free(vaddrs, M_IFLIB); 4957 free(paddrs, M_IFLIB); 4958 4959 return (0); 4960 4961 /* XXX handle allocation failure changes */ 4962 err_rx_desc: 4963 err_tx_desc: 4964 rx_fail: 4965 if (ctx->ifc_rxqs != NULL) 4966 free(ctx->ifc_rxqs, M_IFLIB); 4967 ctx->ifc_rxqs = NULL; 4968 if (ctx->ifc_txqs != NULL) 4969 free(ctx->ifc_txqs, M_IFLIB); 4970 ctx->ifc_txqs = NULL; 4971 fail: 4972 return (err); 4973 } 4974 4975 static int 4976 iflib_tx_structures_setup(if_ctx_t ctx) 4977 { 4978 iflib_txq_t txq = ctx->ifc_txqs; 4979 int i; 4980 4981 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4982 iflib_txq_setup(txq); 4983 4984 return (0); 4985 } 4986 4987 static void 4988 iflib_tx_structures_free(if_ctx_t ctx) 4989 { 4990 iflib_txq_t txq = ctx->ifc_txqs; 4991 int i, j; 4992 4993 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 4994 iflib_txq_destroy(txq); 4995 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 4996 iflib_dma_free(&txq->ift_ifdi[j]); 4997 } 4998 free(ctx->ifc_txqs, M_IFLIB); 4999 ctx->ifc_txqs = NULL; 5000 IFDI_QUEUES_FREE(ctx); 5001 } 5002 5003 /********************************************************************* 5004 * 5005 * Initialize all receive rings. 5006 * 5007 **********************************************************************/ 5008 static int 5009 iflib_rx_structures_setup(if_ctx_t ctx) 5010 { 5011 iflib_rxq_t rxq = ctx->ifc_rxqs; 5012 int q; 5013 #if defined(INET6) || defined(INET) 5014 int i, err; 5015 #endif 5016 5017 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5018 #if defined(INET6) || defined(INET) 5019 tcp_lro_free(&rxq->ifr_lc); 5020 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5021 TCP_LRO_ENTRIES, min(1024, 5022 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 5023 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 5024 goto fail; 5025 } 5026 rxq->ifr_lro_enabled = TRUE; 5027 #endif 5028 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5029 } 5030 return (0); 5031 #if defined(INET6) || defined(INET) 5032 fail: 5033 /* 5034 * Free RX software descriptors allocated so far, we will only handle 5035 * the rings that completed, the failing case will have 5036 * cleaned up for itself. 'q' failed, so its the terminus. 5037 */ 5038 rxq = ctx->ifc_rxqs; 5039 for (i = 0; i < q; ++i, rxq++) { 5040 iflib_rx_sds_free(rxq); 5041 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5042 } 5043 return (err); 5044 #endif 5045 } 5046 5047 /********************************************************************* 5048 * 5049 * Free all receive rings. 5050 * 5051 **********************************************************************/ 5052 static void 5053 iflib_rx_structures_free(if_ctx_t ctx) 5054 { 5055 iflib_rxq_t rxq = ctx->ifc_rxqs; 5056 5057 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5058 iflib_rx_sds_free(rxq); 5059 } 5060 } 5061 5062 static int 5063 iflib_qset_structures_setup(if_ctx_t ctx) 5064 { 5065 int err; 5066 5067 /* 5068 * It is expected that the caller takes care of freeing queues if this 5069 * fails. 5070 */ 5071 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5072 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5073 return (err); 5074 } 5075 5076 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5077 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5078 5079 return (err); 5080 } 5081 5082 int 5083 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5084 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name) 5085 { 5086 5087 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5088 } 5089 5090 #ifdef SMP 5091 static int 5092 find_nth(if_ctx_t ctx, int qid) 5093 { 5094 cpuset_t cpus; 5095 int i, cpuid, eqid, count; 5096 5097 CPU_COPY(&ctx->ifc_cpus, &cpus); 5098 count = CPU_COUNT(&cpus); 5099 eqid = qid % count; 5100 /* clear up to the qid'th bit */ 5101 for (i = 0; i < eqid; i++) { 5102 cpuid = CPU_FFS(&cpus); 5103 MPASS(cpuid != 0); 5104 CPU_CLR(cpuid-1, &cpus); 5105 } 5106 cpuid = CPU_FFS(&cpus); 5107 MPASS(cpuid != 0); 5108 return (cpuid-1); 5109 } 5110 5111 #ifdef SCHED_ULE 5112 extern struct cpu_group *cpu_top; /* CPU topology */ 5113 5114 static int 5115 find_child_with_core(int cpu, struct cpu_group *grp) 5116 { 5117 int i; 5118 5119 if (grp->cg_children == 0) 5120 return -1; 5121 5122 MPASS(grp->cg_child); 5123 for (i = 0; i < grp->cg_children; i++) { 5124 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5125 return i; 5126 } 5127 5128 return -1; 5129 } 5130 5131 /* 5132 * Find the nth "close" core to the specified core 5133 * "close" is defined as the deepest level that shares 5134 * at least an L2 cache. With threads, this will be 5135 * threads on the same core. If the sahred cache is L3 5136 * or higher, simply returns the same core. 5137 */ 5138 static int 5139 find_close_core(int cpu, int core_offset) 5140 { 5141 struct cpu_group *grp; 5142 int i; 5143 int fcpu; 5144 cpuset_t cs; 5145 5146 grp = cpu_top; 5147 if (grp == NULL) 5148 return cpu; 5149 i = 0; 5150 while ((i = find_child_with_core(cpu, grp)) != -1) { 5151 /* If the child only has one cpu, don't descend */ 5152 if (grp->cg_child[i].cg_count <= 1) 5153 break; 5154 grp = &grp->cg_child[i]; 5155 } 5156 5157 /* If they don't share at least an L2 cache, use the same CPU */ 5158 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5159 return cpu; 5160 5161 /* Now pick one */ 5162 CPU_COPY(&grp->cg_mask, &cs); 5163 5164 /* Add the selected CPU offset to core offset. */ 5165 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5166 if (fcpu - 1 == cpu) 5167 break; 5168 CPU_CLR(fcpu - 1, &cs); 5169 } 5170 MPASS(fcpu); 5171 5172 core_offset += i; 5173 5174 CPU_COPY(&grp->cg_mask, &cs); 5175 for (i = core_offset % grp->cg_count; i > 0; i--) { 5176 MPASS(CPU_FFS(&cs)); 5177 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5178 } 5179 MPASS(CPU_FFS(&cs)); 5180 return CPU_FFS(&cs) - 1; 5181 } 5182 #else 5183 static int 5184 find_close_core(int cpu, int core_offset __unused) 5185 { 5186 return cpu; 5187 } 5188 #endif 5189 5190 static int 5191 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5192 { 5193 switch (type) { 5194 case IFLIB_INTR_TX: 5195 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5196 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5197 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5198 case IFLIB_INTR_RX: 5199 case IFLIB_INTR_RXTX: 5200 /* RX queues get the specified core */ 5201 return qid / CPU_COUNT(&ctx->ifc_cpus); 5202 default: 5203 return -1; 5204 } 5205 } 5206 #else 5207 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5208 #define find_close_core(cpuid, tid) CPU_FIRST() 5209 #define find_nth(ctx, gid) CPU_FIRST() 5210 #endif 5211 5212 /* Just to avoid copy/paste */ 5213 static inline int 5214 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid, 5215 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, char *name) 5216 { 5217 int cpuid; 5218 int err, tid; 5219 5220 cpuid = find_nth(ctx, qid); 5221 tid = get_core_offset(ctx, type, qid); 5222 MPASS(tid >= 0); 5223 cpuid = find_close_core(cpuid, tid); 5224 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name); 5225 if (err) { 5226 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err); 5227 return (err); 5228 } 5229 #ifdef notyet 5230 if (cpuid > ctx->ifc_cpuid_highest) 5231 ctx->ifc_cpuid_highest = cpuid; 5232 #endif 5233 return 0; 5234 } 5235 5236 int 5237 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5238 iflib_intr_type_t type, driver_filter_t *filter, 5239 void *filter_arg, int qid, char *name) 5240 { 5241 struct grouptask *gtask; 5242 struct taskqgroup *tqg; 5243 iflib_filter_info_t info; 5244 gtask_fn_t *fn; 5245 int tqrid, err; 5246 driver_filter_t *intr_fast; 5247 void *q; 5248 5249 info = &ctx->ifc_filter_info; 5250 tqrid = rid; 5251 5252 switch (type) { 5253 /* XXX merge tx/rx for netmap? */ 5254 case IFLIB_INTR_TX: 5255 q = &ctx->ifc_txqs[qid]; 5256 info = &ctx->ifc_txqs[qid].ift_filter_info; 5257 gtask = &ctx->ifc_txqs[qid].ift_task; 5258 tqg = qgroup_if_io_tqg; 5259 fn = _task_fn_tx; 5260 intr_fast = iflib_fast_intr; 5261 GROUPTASK_INIT(gtask, 0, fn, q); 5262 break; 5263 case IFLIB_INTR_RX: 5264 q = &ctx->ifc_rxqs[qid]; 5265 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5266 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5267 tqg = qgroup_if_io_tqg; 5268 fn = _task_fn_rx; 5269 intr_fast = iflib_fast_intr; 5270 GROUPTASK_INIT(gtask, 0, fn, q); 5271 break; 5272 case IFLIB_INTR_RXTX: 5273 q = &ctx->ifc_rxqs[qid]; 5274 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5275 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5276 tqg = qgroup_if_io_tqg; 5277 fn = _task_fn_rx; 5278 intr_fast = iflib_fast_intr_rxtx; 5279 GROUPTASK_INIT(gtask, 0, fn, q); 5280 break; 5281 case IFLIB_INTR_ADMIN: 5282 q = ctx; 5283 tqrid = -1; 5284 info = &ctx->ifc_filter_info; 5285 gtask = &ctx->ifc_admin_task; 5286 tqg = qgroup_if_config_tqg; 5287 fn = _task_fn_admin; 5288 intr_fast = iflib_fast_intr_ctx; 5289 break; 5290 default: 5291 panic("unknown net intr type"); 5292 } 5293 5294 info->ifi_filter = filter; 5295 info->ifi_filter_arg = filter_arg; 5296 info->ifi_task = gtask; 5297 info->ifi_ctx = q; 5298 5299 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5300 if (err != 0) { 5301 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 5302 return (err); 5303 } 5304 if (type == IFLIB_INTR_ADMIN) 5305 return (0); 5306 5307 if (tqrid != -1) { 5308 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name); 5309 if (err) 5310 return (err); 5311 } else { 5312 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5313 } 5314 5315 return (0); 5316 } 5317 5318 void 5319 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, char *name) 5320 { 5321 struct grouptask *gtask; 5322 struct taskqgroup *tqg; 5323 gtask_fn_t *fn; 5324 void *q; 5325 int irq_num = -1; 5326 int err; 5327 5328 switch (type) { 5329 case IFLIB_INTR_TX: 5330 q = &ctx->ifc_txqs[qid]; 5331 gtask = &ctx->ifc_txqs[qid].ift_task; 5332 tqg = qgroup_if_io_tqg; 5333 fn = _task_fn_tx; 5334 if (irq != NULL) 5335 irq_num = rman_get_start(irq->ii_res); 5336 break; 5337 case IFLIB_INTR_RX: 5338 q = &ctx->ifc_rxqs[qid]; 5339 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5340 tqg = qgroup_if_io_tqg; 5341 fn = _task_fn_rx; 5342 if (irq != NULL) 5343 irq_num = rman_get_start(irq->ii_res); 5344 break; 5345 case IFLIB_INTR_IOV: 5346 q = ctx; 5347 gtask = &ctx->ifc_vflr_task; 5348 tqg = qgroup_if_config_tqg; 5349 fn = _task_fn_iov; 5350 break; 5351 default: 5352 panic("unknown net intr type"); 5353 } 5354 GROUPTASK_INIT(gtask, 0, fn, q); 5355 if (irq_num != -1) { 5356 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name); 5357 if (err) 5358 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5359 } 5360 else { 5361 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5362 } 5363 } 5364 5365 void 5366 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5367 { 5368 if (irq->ii_tag) 5369 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5370 5371 if (irq->ii_res) 5372 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5373 } 5374 5375 static int 5376 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name) 5377 { 5378 iflib_txq_t txq = ctx->ifc_txqs; 5379 iflib_rxq_t rxq = ctx->ifc_rxqs; 5380 if_irq_t irq = &ctx->ifc_legacy_irq; 5381 iflib_filter_info_t info; 5382 struct grouptask *gtask; 5383 struct taskqgroup *tqg; 5384 gtask_fn_t *fn; 5385 int tqrid; 5386 void *q; 5387 int err; 5388 5389 q = &ctx->ifc_rxqs[0]; 5390 info = &rxq[0].ifr_filter_info; 5391 gtask = &rxq[0].ifr_task; 5392 tqg = qgroup_if_io_tqg; 5393 tqrid = irq->ii_rid = *rid; 5394 fn = _task_fn_rx; 5395 5396 ctx->ifc_flags |= IFC_LEGACY; 5397 info->ifi_filter = filter; 5398 info->ifi_filter_arg = filter_arg; 5399 info->ifi_task = gtask; 5400 info->ifi_ctx = ctx; 5401 5402 /* We allocate a single interrupt resource */ 5403 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5404 return (err); 5405 GROUPTASK_INIT(gtask, 0, fn, q); 5406 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5407 5408 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5409 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx"); 5410 return (0); 5411 } 5412 5413 void 5414 iflib_led_create(if_ctx_t ctx) 5415 { 5416 5417 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5418 device_get_nameunit(ctx->ifc_dev)); 5419 } 5420 5421 void 5422 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5423 { 5424 5425 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5426 } 5427 5428 void 5429 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5430 { 5431 5432 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5433 } 5434 5435 void 5436 iflib_admin_intr_deferred(if_ctx_t ctx) 5437 { 5438 #ifdef INVARIANTS 5439 struct grouptask *gtask; 5440 5441 gtask = &ctx->ifc_admin_task; 5442 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5443 #endif 5444 5445 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5446 } 5447 5448 void 5449 iflib_iov_intr_deferred(if_ctx_t ctx) 5450 { 5451 5452 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5453 } 5454 5455 void 5456 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5457 { 5458 5459 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5460 } 5461 5462 void 5463 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 5464 const char *name) 5465 { 5466 5467 GROUPTASK_INIT(gtask, 0, fn, ctx); 5468 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5469 } 5470 5471 void 5472 iflib_config_gtask_deinit(struct grouptask *gtask) 5473 { 5474 5475 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5476 } 5477 5478 void 5479 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5480 { 5481 if_t ifp = ctx->ifc_ifp; 5482 iflib_txq_t txq = ctx->ifc_txqs; 5483 5484 if_setbaudrate(ifp, baudrate); 5485 if (baudrate >= IF_Gbps(10)) { 5486 STATE_LOCK(ctx); 5487 ctx->ifc_flags |= IFC_PREFETCH; 5488 STATE_UNLOCK(ctx); 5489 } 5490 /* If link down, disable watchdog */ 5491 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5492 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5493 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5494 } 5495 ctx->ifc_link_state = link_state; 5496 if_link_state_change(ifp, link_state); 5497 } 5498 5499 static int 5500 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5501 { 5502 int credits; 5503 #ifdef INVARIANTS 5504 int credits_pre = txq->ift_cidx_processed; 5505 #endif 5506 5507 if (ctx->isc_txd_credits_update == NULL) 5508 return (0); 5509 5510 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5511 return (0); 5512 5513 txq->ift_processed += credits; 5514 txq->ift_cidx_processed += credits; 5515 5516 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5517 if (txq->ift_cidx_processed >= txq->ift_size) 5518 txq->ift_cidx_processed -= txq->ift_size; 5519 return (credits); 5520 } 5521 5522 static int 5523 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5524 { 5525 5526 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5527 budget)); 5528 } 5529 5530 void 5531 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5532 const char *description, if_int_delay_info_t info, 5533 int offset, int value) 5534 { 5535 info->iidi_ctx = ctx; 5536 info->iidi_offset = offset; 5537 info->iidi_value = value; 5538 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5539 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5540 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5541 info, 0, iflib_sysctl_int_delay, "I", description); 5542 } 5543 5544 struct sx * 5545 iflib_ctx_lock_get(if_ctx_t ctx) 5546 { 5547 5548 return (&ctx->ifc_ctx_sx); 5549 } 5550 5551 static int 5552 iflib_msix_init(if_ctx_t ctx) 5553 { 5554 device_t dev = ctx->ifc_dev; 5555 if_shared_ctx_t sctx = ctx->ifc_sctx; 5556 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5557 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5558 int iflib_num_tx_queues, iflib_num_rx_queues; 5559 int err, admincnt, bar; 5560 5561 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 5562 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 5563 5564 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 5565 5566 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5567 admincnt = sctx->isc_admin_intrcnt; 5568 /* Override by global tuneable */ 5569 { 5570 int i; 5571 size_t len = sizeof(i); 5572 err = kernel_sysctlbyname(curthread, "hw.pci.enable_msix", &i, &len, NULL, 0, NULL, 0); 5573 if (err == 0) { 5574 if (i == 0) 5575 goto msi; 5576 } 5577 else { 5578 device_printf(dev, "unable to read hw.pci.enable_msix."); 5579 } 5580 } 5581 /* Override by tuneable */ 5582 if (scctx->isc_disable_msix) 5583 goto msi; 5584 5585 /* 5586 ** When used in a virtualized environment 5587 ** PCI BUSMASTER capability may not be set 5588 ** so explicity set it here and rewrite 5589 ** the ENABLE in the MSIX control register 5590 ** at this point to cause the host to 5591 ** successfully initialize us. 5592 */ 5593 { 5594 int msix_ctrl, rid; 5595 5596 pci_enable_busmaster(dev); 5597 rid = 0; 5598 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) { 5599 rid += PCIR_MSIX_CTRL; 5600 msix_ctrl = pci_read_config(dev, rid, 2); 5601 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 5602 pci_write_config(dev, rid, msix_ctrl, 2); 5603 } else { 5604 device_printf(dev, "PCIY_MSIX capability not found; " 5605 "or rid %d == 0.\n", rid); 5606 goto msi; 5607 } 5608 } 5609 5610 /* 5611 * bar == -1 => "trust me I know what I'm doing" 5612 * Some drivers are for hardware that is so shoddily 5613 * documented that no one knows which bars are which 5614 * so the developer has to map all bars. This hack 5615 * allows shoddy garbage to use msix in this framework. 5616 */ 5617 if (bar != -1) { 5618 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5619 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5620 if (ctx->ifc_msix_mem == NULL) { 5621 /* May not be enabled */ 5622 device_printf(dev, "Unable to map MSIX table \n"); 5623 goto msi; 5624 } 5625 } 5626 /* First try MSI/X */ 5627 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5628 device_printf(dev, "System has MSIX disabled \n"); 5629 bus_release_resource(dev, SYS_RES_MEMORY, 5630 bar, ctx->ifc_msix_mem); 5631 ctx->ifc_msix_mem = NULL; 5632 goto msi; 5633 } 5634 #if IFLIB_DEBUG 5635 /* use only 1 qset in debug mode */ 5636 queuemsgs = min(msgs - admincnt, 1); 5637 #else 5638 queuemsgs = msgs - admincnt; 5639 #endif 5640 #ifdef RSS 5641 queues = imin(queuemsgs, rss_getnumbuckets()); 5642 #else 5643 queues = queuemsgs; 5644 #endif 5645 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 5646 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 5647 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 5648 #ifdef RSS 5649 /* If we're doing RSS, clamp at the number of RSS buckets */ 5650 if (queues > rss_getnumbuckets()) 5651 queues = rss_getnumbuckets(); 5652 #endif 5653 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 5654 rx_queues = iflib_num_rx_queues; 5655 else 5656 rx_queues = queues; 5657 5658 if (rx_queues > scctx->isc_nrxqsets) 5659 rx_queues = scctx->isc_nrxqsets; 5660 5661 /* 5662 * We want this to be all logical CPUs by default 5663 */ 5664 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 5665 tx_queues = iflib_num_tx_queues; 5666 else 5667 tx_queues = mp_ncpus; 5668 5669 if (tx_queues > scctx->isc_ntxqsets) 5670 tx_queues = scctx->isc_ntxqsets; 5671 5672 if (ctx->ifc_sysctl_qs_eq_override == 0) { 5673 #ifdef INVARIANTS 5674 if (tx_queues != rx_queues) 5675 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 5676 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 5677 #endif 5678 tx_queues = min(rx_queues, tx_queues); 5679 rx_queues = min(rx_queues, tx_queues); 5680 } 5681 5682 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 5683 5684 vectors = rx_queues + admincnt; 5685 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 5686 device_printf(dev, 5687 "Using MSIX interrupts with %d vectors\n", vectors); 5688 scctx->isc_vectors = vectors; 5689 scctx->isc_nrxqsets = rx_queues; 5690 scctx->isc_ntxqsets = tx_queues; 5691 scctx->isc_intr = IFLIB_INTR_MSIX; 5692 5693 return (vectors); 5694 } else { 5695 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 5696 } 5697 msi: 5698 vectors = pci_msi_count(dev); 5699 scctx->isc_nrxqsets = 1; 5700 scctx->isc_ntxqsets = 1; 5701 scctx->isc_vectors = vectors; 5702 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 5703 device_printf(dev,"Using an MSI interrupt\n"); 5704 scctx->isc_intr = IFLIB_INTR_MSI; 5705 } else { 5706 device_printf(dev,"Using a Legacy interrupt\n"); 5707 scctx->isc_intr = IFLIB_INTR_LEGACY; 5708 } 5709 5710 return (vectors); 5711 } 5712 5713 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 5714 5715 static int 5716 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 5717 { 5718 int rc; 5719 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 5720 struct sbuf *sb; 5721 char *ring_state = "UNKNOWN"; 5722 5723 /* XXX needed ? */ 5724 rc = sysctl_wire_old_buffer(req, 0); 5725 MPASS(rc == 0); 5726 if (rc != 0) 5727 return (rc); 5728 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 5729 MPASS(sb != NULL); 5730 if (sb == NULL) 5731 return (ENOMEM); 5732 if (state[3] <= 3) 5733 ring_state = ring_states[state[3]]; 5734 5735 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 5736 state[0], state[1], state[2], ring_state); 5737 rc = sbuf_finish(sb); 5738 sbuf_delete(sb); 5739 return(rc); 5740 } 5741 5742 enum iflib_ndesc_handler { 5743 IFLIB_NTXD_HANDLER, 5744 IFLIB_NRXD_HANDLER, 5745 }; 5746 5747 static int 5748 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 5749 { 5750 if_ctx_t ctx = (void *)arg1; 5751 enum iflib_ndesc_handler type = arg2; 5752 char buf[256] = {0}; 5753 qidx_t *ndesc; 5754 char *p, *next; 5755 int nqs, rc, i; 5756 5757 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 5758 5759 nqs = 8; 5760 switch(type) { 5761 case IFLIB_NTXD_HANDLER: 5762 ndesc = ctx->ifc_sysctl_ntxds; 5763 if (ctx->ifc_sctx) 5764 nqs = ctx->ifc_sctx->isc_ntxqs; 5765 break; 5766 case IFLIB_NRXD_HANDLER: 5767 ndesc = ctx->ifc_sysctl_nrxds; 5768 if (ctx->ifc_sctx) 5769 nqs = ctx->ifc_sctx->isc_nrxqs; 5770 break; 5771 default: 5772 panic("unhandled type"); 5773 } 5774 if (nqs == 0) 5775 nqs = 8; 5776 5777 for (i=0; i<8; i++) { 5778 if (i >= nqs) 5779 break; 5780 if (i) 5781 strcat(buf, ","); 5782 sprintf(strchr(buf, 0), "%d", ndesc[i]); 5783 } 5784 5785 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 5786 if (rc || req->newptr == NULL) 5787 return rc; 5788 5789 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 5790 i++, p = strsep(&next, " ,")) { 5791 ndesc[i] = strtoul(p, NULL, 10); 5792 } 5793 5794 return(rc); 5795 } 5796 5797 #define NAME_BUFLEN 32 5798 static void 5799 iflib_add_device_sysctl_pre(if_ctx_t ctx) 5800 { 5801 device_t dev = iflib_get_dev(ctx); 5802 struct sysctl_oid_list *child, *oid_list; 5803 struct sysctl_ctx_list *ctx_list; 5804 struct sysctl_oid *node; 5805 5806 ctx_list = device_get_sysctl_ctx(dev); 5807 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 5808 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 5809 CTLFLAG_RD, NULL, "IFLIB fields"); 5810 oid_list = SYSCTL_CHILDREN(node); 5811 5812 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 5813 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 5814 "driver version"); 5815 5816 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 5817 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 5818 "# of txqs to use, 0 => use default #"); 5819 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 5820 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 5821 "# of rxqs to use, 0 => use default #"); 5822 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 5823 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 5824 "permit #txq != #rxq"); 5825 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 5826 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 5827 "disable MSIX (default 0)"); 5828 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 5829 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 5830 "set the rx budget"); 5831 5832 /* XXX change for per-queue sizes */ 5833 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 5834 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 5835 mp_ndesc_handler, "A", 5836 "list of # of tx descriptors to use, 0 = use default #"); 5837 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 5838 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 5839 mp_ndesc_handler, "A", 5840 "list of # of rx descriptors to use, 0 = use default #"); 5841 } 5842 5843 static void 5844 iflib_add_device_sysctl_post(if_ctx_t ctx) 5845 { 5846 if_shared_ctx_t sctx = ctx->ifc_sctx; 5847 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5848 device_t dev = iflib_get_dev(ctx); 5849 struct sysctl_oid_list *child; 5850 struct sysctl_ctx_list *ctx_list; 5851 iflib_fl_t fl; 5852 iflib_txq_t txq; 5853 iflib_rxq_t rxq; 5854 int i, j; 5855 char namebuf[NAME_BUFLEN]; 5856 char *qfmt; 5857 struct sysctl_oid *queue_node, *fl_node, *node; 5858 struct sysctl_oid_list *queue_list, *fl_list; 5859 ctx_list = device_get_sysctl_ctx(dev); 5860 5861 node = ctx->ifc_sysctl_node; 5862 child = SYSCTL_CHILDREN(node); 5863 5864 if (scctx->isc_ntxqsets > 100) 5865 qfmt = "txq%03d"; 5866 else if (scctx->isc_ntxqsets > 10) 5867 qfmt = "txq%02d"; 5868 else 5869 qfmt = "txq%d"; 5870 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 5871 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5872 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5873 CTLFLAG_RD, NULL, "Queue Name"); 5874 queue_list = SYSCTL_CHILDREN(queue_node); 5875 #if MEMORY_LOGGING 5876 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 5877 CTLFLAG_RD, 5878 &txq->ift_dequeued, "total mbufs freed"); 5879 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 5880 CTLFLAG_RD, 5881 &txq->ift_enqueued, "total mbufs enqueued"); 5882 #endif 5883 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 5884 CTLFLAG_RD, 5885 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 5886 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 5887 CTLFLAG_RD, 5888 &txq->ift_pullups, "# of times m_pullup was called"); 5889 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 5890 CTLFLAG_RD, 5891 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 5892 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 5893 CTLFLAG_RD, 5894 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 5895 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 5896 CTLFLAG_RD, 5897 &txq->ift_map_failed, "# of times dma map failed"); 5898 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 5899 CTLFLAG_RD, 5900 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 5901 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 5902 CTLFLAG_RD, 5903 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 5904 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 5905 CTLFLAG_RD, 5906 &txq->ift_pidx, 1, "Producer Index"); 5907 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 5908 CTLFLAG_RD, 5909 &txq->ift_cidx, 1, "Consumer Index"); 5910 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 5911 CTLFLAG_RD, 5912 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 5913 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 5914 CTLFLAG_RD, 5915 &txq->ift_in_use, 1, "descriptors in use"); 5916 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 5917 CTLFLAG_RD, 5918 &txq->ift_processed, "descriptors procesed for clean"); 5919 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 5920 CTLFLAG_RD, 5921 &txq->ift_cleaned, "total cleaned"); 5922 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 5923 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 5924 0, mp_ring_state_handler, "A", "soft ring state"); 5925 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 5926 CTLFLAG_RD, &txq->ift_br->enqueues, 5927 "# of enqueues to the mp_ring for this queue"); 5928 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 5929 CTLFLAG_RD, &txq->ift_br->drops, 5930 "# of drops in the mp_ring for this queue"); 5931 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 5932 CTLFLAG_RD, &txq->ift_br->starts, 5933 "# of normal consumer starts in the mp_ring for this queue"); 5934 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 5935 CTLFLAG_RD, &txq->ift_br->stalls, 5936 "# of consumer stalls in the mp_ring for this queue"); 5937 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 5938 CTLFLAG_RD, &txq->ift_br->restarts, 5939 "# of consumer restarts in the mp_ring for this queue"); 5940 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 5941 CTLFLAG_RD, &txq->ift_br->abdications, 5942 "# of consumer abdications in the mp_ring for this queue"); 5943 } 5944 5945 if (scctx->isc_nrxqsets > 100) 5946 qfmt = "rxq%03d"; 5947 else if (scctx->isc_nrxqsets > 10) 5948 qfmt = "rxq%02d"; 5949 else 5950 qfmt = "rxq%d"; 5951 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 5952 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5953 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5954 CTLFLAG_RD, NULL, "Queue Name"); 5955 queue_list = SYSCTL_CHILDREN(queue_node); 5956 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5957 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 5958 CTLFLAG_RD, 5959 &rxq->ifr_cq_pidx, 1, "Producer Index"); 5960 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 5961 CTLFLAG_RD, 5962 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 5963 } 5964 5965 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 5966 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 5967 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 5968 CTLFLAG_RD, NULL, "freelist Name"); 5969 fl_list = SYSCTL_CHILDREN(fl_node); 5970 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 5971 CTLFLAG_RD, 5972 &fl->ifl_pidx, 1, "Producer Index"); 5973 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 5974 CTLFLAG_RD, 5975 &fl->ifl_cidx, 1, "Consumer Index"); 5976 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 5977 CTLFLAG_RD, 5978 &fl->ifl_credits, 1, "credits available"); 5979 #if MEMORY_LOGGING 5980 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 5981 CTLFLAG_RD, 5982 &fl->ifl_m_enqueued, "mbufs allocated"); 5983 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 5984 CTLFLAG_RD, 5985 &fl->ifl_m_dequeued, "mbufs freed"); 5986 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 5987 CTLFLAG_RD, 5988 &fl->ifl_cl_enqueued, "clusters allocated"); 5989 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 5990 CTLFLAG_RD, 5991 &fl->ifl_cl_dequeued, "clusters freed"); 5992 #endif 5993 5994 } 5995 } 5996 5997 } 5998 5999 #ifndef __NO_STRICT_ALIGNMENT 6000 static struct mbuf * 6001 iflib_fixup_rx(struct mbuf *m) 6002 { 6003 struct mbuf *n; 6004 6005 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6006 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6007 m->m_data += ETHER_HDR_LEN; 6008 n = m; 6009 } else { 6010 MGETHDR(n, M_NOWAIT, MT_DATA); 6011 if (n == NULL) { 6012 m_freem(m); 6013 return (NULL); 6014 } 6015 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6016 m->m_data += ETHER_HDR_LEN; 6017 m->m_len -= ETHER_HDR_LEN; 6018 n->m_len = ETHER_HDR_LEN; 6019 M_MOVE_PKTHDR(n, m); 6020 n->m_next = m; 6021 } 6022 return (n); 6023 } 6024 #endif 6025 6026 #ifdef NETDUMP 6027 static void 6028 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 6029 { 6030 if_ctx_t ctx; 6031 6032 ctx = if_getsoftc(ifp); 6033 CTX_LOCK(ctx); 6034 *nrxr = NRXQSETS(ctx); 6035 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6036 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6037 CTX_UNLOCK(ctx); 6038 } 6039 6040 static void 6041 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event) 6042 { 6043 if_ctx_t ctx; 6044 if_softc_ctx_t scctx; 6045 iflib_fl_t fl; 6046 iflib_rxq_t rxq; 6047 int i, j; 6048 6049 ctx = if_getsoftc(ifp); 6050 scctx = &ctx->ifc_softc_ctx; 6051 6052 switch (event) { 6053 case NETDUMP_START: 6054 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6055 rxq = &ctx->ifc_rxqs[i]; 6056 for (j = 0; j < rxq->ifr_nfl; j++) { 6057 fl = rxq->ifr_fl; 6058 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6059 } 6060 } 6061 iflib_no_tx_batch = 1; 6062 break; 6063 default: 6064 break; 6065 } 6066 } 6067 6068 static int 6069 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m) 6070 { 6071 if_ctx_t ctx; 6072 iflib_txq_t txq; 6073 int error; 6074 6075 ctx = if_getsoftc(ifp); 6076 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6077 IFF_DRV_RUNNING) 6078 return (EBUSY); 6079 6080 txq = &ctx->ifc_txqs[0]; 6081 error = iflib_encap(txq, &m); 6082 if (error == 0) 6083 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6084 return (error); 6085 } 6086 6087 static int 6088 iflib_netdump_poll(struct ifnet *ifp, int count) 6089 { 6090 if_ctx_t ctx; 6091 if_softc_ctx_t scctx; 6092 iflib_txq_t txq; 6093 int i; 6094 6095 ctx = if_getsoftc(ifp); 6096 scctx = &ctx->ifc_softc_ctx; 6097 6098 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6099 IFF_DRV_RUNNING) 6100 return (EBUSY); 6101 6102 txq = &ctx->ifc_txqs[0]; 6103 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6104 6105 for (i = 0; i < scctx->isc_nrxqsets; i++) 6106 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6107 return (0); 6108 } 6109 #endif /* NETDUMP */ 6110