1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/jail.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/md5.h> 44 #include <sys/mutex.h> 45 #include <sys/module.h> 46 #include <sys/kobj.h> 47 #include <sys/rman.h> 48 #include <sys/proc.h> 49 #include <sys/sbuf.h> 50 #include <sys/smp.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/syslog.h> 55 #include <sys/taskqueue.h> 56 #include <sys/limits.h> 57 58 #include <net/if.h> 59 #include <net/if_var.h> 60 #include <net/if_types.h> 61 #include <net/if_media.h> 62 #include <net/bpf.h> 63 #include <net/ethernet.h> 64 #include <net/mp_ring.h> 65 #include <net/vnet.h> 66 67 #include <netinet/in.h> 68 #include <netinet/in_pcb.h> 69 #include <netinet/tcp_lro.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/if_ether.h> 72 #include <netinet/ip.h> 73 #include <netinet/ip6.h> 74 #include <netinet/tcp.h> 75 #include <netinet/ip_var.h> 76 #include <netinet/netdump/netdump.h> 77 #include <netinet6/ip6_var.h> 78 79 #include <machine/bus.h> 80 #include <machine/in_cksum.h> 81 82 #include <vm/vm.h> 83 #include <vm/pmap.h> 84 85 #include <dev/led/led.h> 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pci_private.h> 89 90 #include <net/iflib.h> 91 #include <net/iflib_private.h> 92 93 #include "ifdi_if.h" 94 95 #if defined(__i386__) || defined(__amd64__) 96 #include <sys/memdesc.h> 97 #include <machine/bus.h> 98 #include <machine/md_var.h> 99 #include <machine/specialreg.h> 100 #include <x86/include/busdma_impl.h> 101 #include <x86/iommu/busdma_dmar.h> 102 #endif 103 104 #include <sys/bitstring.h> 105 /* 106 * enable accounting of every mbuf as it comes in to and goes out of 107 * iflib's software descriptor references 108 */ 109 #define MEMORY_LOGGING 0 110 /* 111 * Enable mbuf vectors for compressing long mbuf chains 112 */ 113 114 /* 115 * NB: 116 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 117 * we prefetch needs to be determined by the time spent in m_free vis a vis 118 * the cost of a prefetch. This will of course vary based on the workload: 119 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 120 * is quite expensive, thus suggesting very little prefetch. 121 * - small packet forwarding which is just returning a single mbuf to 122 * UMA will typically be very fast vis a vis the cost of a memory 123 * access. 124 */ 125 126 127 /* 128 * File organization: 129 * - private structures 130 * - iflib private utility functions 131 * - ifnet functions 132 * - vlan registry and other exported functions 133 * - iflib public core functions 134 * 135 * 136 */ 137 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 138 139 struct iflib_txq; 140 typedef struct iflib_txq *iflib_txq_t; 141 struct iflib_rxq; 142 typedef struct iflib_rxq *iflib_rxq_t; 143 struct iflib_fl; 144 typedef struct iflib_fl *iflib_fl_t; 145 146 struct iflib_ctx; 147 148 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 149 150 typedef struct iflib_filter_info { 151 driver_filter_t *ifi_filter; 152 void *ifi_filter_arg; 153 struct grouptask *ifi_task; 154 void *ifi_ctx; 155 } *iflib_filter_info_t; 156 157 struct iflib_ctx { 158 KOBJ_FIELDS; 159 /* 160 * Pointer to hardware driver's softc 161 */ 162 void *ifc_softc; 163 device_t ifc_dev; 164 if_t ifc_ifp; 165 166 cpuset_t ifc_cpus; 167 if_shared_ctx_t ifc_sctx; 168 struct if_softc_ctx ifc_softc_ctx; 169 170 struct sx ifc_ctx_sx; 171 struct mtx ifc_state_mtx; 172 173 uint16_t ifc_nhwtxqs; 174 175 iflib_txq_t ifc_txqs; 176 iflib_rxq_t ifc_rxqs; 177 uint32_t ifc_if_flags; 178 uint32_t ifc_flags; 179 uint32_t ifc_max_fl_buf_size; 180 int ifc_in_detach; 181 182 int ifc_link_state; 183 int ifc_link_irq; 184 int ifc_watchdog_events; 185 struct cdev *ifc_led_dev; 186 struct resource *ifc_msix_mem; 187 188 struct if_irq ifc_legacy_irq; 189 struct grouptask ifc_admin_task; 190 struct grouptask ifc_vflr_task; 191 struct iflib_filter_info ifc_filter_info; 192 struct ifmedia ifc_media; 193 194 struct sysctl_oid *ifc_sysctl_node; 195 uint16_t ifc_sysctl_ntxqs; 196 uint16_t ifc_sysctl_nrxqs; 197 uint16_t ifc_sysctl_qs_eq_override; 198 uint16_t ifc_sysctl_rx_budget; 199 200 qidx_t ifc_sysctl_ntxds[8]; 201 qidx_t ifc_sysctl_nrxds[8]; 202 struct if_txrx ifc_txrx; 203 #define isc_txd_encap ifc_txrx.ift_txd_encap 204 #define isc_txd_flush ifc_txrx.ift_txd_flush 205 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 206 #define isc_rxd_available ifc_txrx.ift_rxd_available 207 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 208 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 209 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 210 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 211 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 212 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 213 eventhandler_tag ifc_vlan_attach_event; 214 eventhandler_tag ifc_vlan_detach_event; 215 uint8_t ifc_mac[ETHER_ADDR_LEN]; 216 char ifc_mtx_name[16]; 217 }; 218 219 220 void * 221 iflib_get_softc(if_ctx_t ctx) 222 { 223 224 return (ctx->ifc_softc); 225 } 226 227 device_t 228 iflib_get_dev(if_ctx_t ctx) 229 { 230 231 return (ctx->ifc_dev); 232 } 233 234 if_t 235 iflib_get_ifp(if_ctx_t ctx) 236 { 237 238 return (ctx->ifc_ifp); 239 } 240 241 struct ifmedia * 242 iflib_get_media(if_ctx_t ctx) 243 { 244 245 return (&ctx->ifc_media); 246 } 247 248 uint32_t 249 iflib_get_flags(if_ctx_t ctx) 250 { 251 return (ctx->ifc_flags); 252 } 253 254 void 255 iflib_set_detach(if_ctx_t ctx) 256 { 257 ctx->ifc_in_detach = 1; 258 } 259 260 void 261 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 262 { 263 264 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 265 } 266 267 if_softc_ctx_t 268 iflib_get_softc_ctx(if_ctx_t ctx) 269 { 270 271 return (&ctx->ifc_softc_ctx); 272 } 273 274 if_shared_ctx_t 275 iflib_get_sctx(if_ctx_t ctx) 276 { 277 278 return (ctx->ifc_sctx); 279 } 280 281 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 282 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 283 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 284 285 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 286 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 287 288 #define RX_SW_DESC_MAP_CREATED (1 << 0) 289 #define TX_SW_DESC_MAP_CREATED (1 << 1) 290 #define RX_SW_DESC_INUSE (1 << 3) 291 #define TX_SW_DESC_MAPPED (1 << 4) 292 293 #define M_TOOBIG M_PROTO1 294 295 typedef struct iflib_sw_rx_desc_array { 296 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 297 struct mbuf **ifsd_m; /* pkthdr mbufs */ 298 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 299 uint8_t *ifsd_flags; 300 } iflib_rxsd_array_t; 301 302 typedef struct iflib_sw_tx_desc_array { 303 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 304 struct mbuf **ifsd_m; /* pkthdr mbufs */ 305 uint8_t *ifsd_flags; 306 } if_txsd_vec_t; 307 308 309 /* magic number that should be high enough for any hardware */ 310 #define IFLIB_MAX_TX_SEGS 128 311 /* bnxt supports 64 with hardware LRO enabled */ 312 #define IFLIB_MAX_RX_SEGS 64 313 #define IFLIB_RX_COPY_THRESH 128 314 #define IFLIB_MAX_RX_REFRESH 32 315 /* The minimum descriptors per second before we start coalescing */ 316 #define IFLIB_MIN_DESC_SEC 16384 317 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 318 #define IFLIB_QUEUE_IDLE 0 319 #define IFLIB_QUEUE_HUNG 1 320 #define IFLIB_QUEUE_WORKING 2 321 /* maximum number of txqs that can share an rx interrupt */ 322 #define IFLIB_MAX_TX_SHARED_INTR 4 323 324 /* this should really scale with ring size - this is a fairly arbitrary value */ 325 #define TX_BATCH_SIZE 32 326 327 #define IFLIB_RESTART_BUDGET 8 328 329 330 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 331 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 332 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 333 struct iflib_txq { 334 qidx_t ift_in_use; 335 qidx_t ift_cidx; 336 qidx_t ift_cidx_processed; 337 qidx_t ift_pidx; 338 uint8_t ift_gen; 339 uint8_t ift_br_offset; 340 uint16_t ift_npending; 341 uint16_t ift_db_pending; 342 uint16_t ift_rs_pending; 343 /* implicit pad */ 344 uint8_t ift_txd_size[8]; 345 uint64_t ift_processed; 346 uint64_t ift_cleaned; 347 uint64_t ift_cleaned_prev; 348 #if MEMORY_LOGGING 349 uint64_t ift_enqueued; 350 uint64_t ift_dequeued; 351 #endif 352 uint64_t ift_no_tx_dma_setup; 353 uint64_t ift_no_desc_avail; 354 uint64_t ift_mbuf_defrag_failed; 355 uint64_t ift_mbuf_defrag; 356 uint64_t ift_map_failed; 357 uint64_t ift_txd_encap_efbig; 358 uint64_t ift_pullups; 359 360 struct mtx ift_mtx; 361 struct mtx ift_db_mtx; 362 363 /* constant values */ 364 if_ctx_t ift_ctx; 365 struct ifmp_ring *ift_br; 366 struct grouptask ift_task; 367 qidx_t ift_size; 368 uint16_t ift_id; 369 struct callout ift_timer; 370 371 if_txsd_vec_t ift_sds; 372 uint8_t ift_qstatus; 373 uint8_t ift_closed; 374 uint8_t ift_update_freq; 375 struct iflib_filter_info ift_filter_info; 376 bus_dma_tag_t ift_desc_tag; 377 bus_dma_tag_t ift_tso_desc_tag; 378 iflib_dma_info_t ift_ifdi; 379 #define MTX_NAME_LEN 16 380 char ift_mtx_name[MTX_NAME_LEN]; 381 char ift_db_mtx_name[MTX_NAME_LEN]; 382 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 383 #ifdef IFLIB_DIAGNOSTICS 384 uint64_t ift_cpu_exec_count[256]; 385 #endif 386 } __aligned(CACHE_LINE_SIZE); 387 388 struct iflib_fl { 389 qidx_t ifl_cidx; 390 qidx_t ifl_pidx; 391 qidx_t ifl_credits; 392 uint8_t ifl_gen; 393 uint8_t ifl_rxd_size; 394 #if MEMORY_LOGGING 395 uint64_t ifl_m_enqueued; 396 uint64_t ifl_m_dequeued; 397 uint64_t ifl_cl_enqueued; 398 uint64_t ifl_cl_dequeued; 399 #endif 400 /* implicit pad */ 401 402 bitstr_t *ifl_rx_bitmap; 403 qidx_t ifl_fragidx; 404 /* constant */ 405 qidx_t ifl_size; 406 uint16_t ifl_buf_size; 407 uint16_t ifl_cltype; 408 uma_zone_t ifl_zone; 409 iflib_rxsd_array_t ifl_sds; 410 iflib_rxq_t ifl_rxq; 411 uint8_t ifl_id; 412 bus_dma_tag_t ifl_desc_tag; 413 iflib_dma_info_t ifl_ifdi; 414 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 415 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 416 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 417 } __aligned(CACHE_LINE_SIZE); 418 419 static inline qidx_t 420 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 421 { 422 qidx_t used; 423 424 if (pidx > cidx) 425 used = pidx - cidx; 426 else if (pidx < cidx) 427 used = size - cidx + pidx; 428 else if (gen == 0 && pidx == cidx) 429 used = 0; 430 else if (gen == 1 && pidx == cidx) 431 used = size; 432 else 433 panic("bad state"); 434 435 return (used); 436 } 437 438 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 439 440 #define IDXDIFF(head, tail, wrap) \ 441 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 442 443 struct iflib_rxq { 444 /* If there is a separate completion queue - 445 * these are the cq cidx and pidx. Otherwise 446 * these are unused. 447 */ 448 qidx_t ifr_size; 449 qidx_t ifr_cq_cidx; 450 qidx_t ifr_cq_pidx; 451 uint8_t ifr_cq_gen; 452 uint8_t ifr_fl_offset; 453 454 if_ctx_t ifr_ctx; 455 iflib_fl_t ifr_fl; 456 uint64_t ifr_rx_irq; 457 uint16_t ifr_id; 458 uint8_t ifr_lro_enabled; 459 uint8_t ifr_nfl; 460 uint8_t ifr_ntxqirq; 461 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 462 struct lro_ctrl ifr_lc; 463 struct grouptask ifr_task; 464 struct iflib_filter_info ifr_filter_info; 465 iflib_dma_info_t ifr_ifdi; 466 467 /* dynamically allocate if any drivers need a value substantially larger than this */ 468 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 469 #ifdef IFLIB_DIAGNOSTICS 470 uint64_t ifr_cpu_exec_count[256]; 471 #endif 472 } __aligned(CACHE_LINE_SIZE); 473 474 typedef struct if_rxsd { 475 caddr_t *ifsd_cl; 476 struct mbuf **ifsd_m; 477 iflib_fl_t ifsd_fl; 478 qidx_t ifsd_cidx; 479 } *if_rxsd_t; 480 481 /* multiple of word size */ 482 #ifdef __LP64__ 483 #define PKT_INFO_SIZE 6 484 #define RXD_INFO_SIZE 5 485 #define PKT_TYPE uint64_t 486 #else 487 #define PKT_INFO_SIZE 11 488 #define RXD_INFO_SIZE 8 489 #define PKT_TYPE uint32_t 490 #endif 491 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 492 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 493 494 typedef struct if_pkt_info_pad { 495 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 496 } *if_pkt_info_pad_t; 497 typedef struct if_rxd_info_pad { 498 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 499 } *if_rxd_info_pad_t; 500 501 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 502 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 503 504 505 static inline void 506 pkt_info_zero(if_pkt_info_t pi) 507 { 508 if_pkt_info_pad_t pi_pad; 509 510 pi_pad = (if_pkt_info_pad_t)pi; 511 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 512 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 513 #ifndef __LP64__ 514 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 515 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 516 #endif 517 } 518 519 static device_method_t iflib_pseudo_methods[] = { 520 DEVMETHOD(device_attach, noop_attach), 521 DEVMETHOD(device_detach, iflib_pseudo_detach), 522 DEVMETHOD_END 523 }; 524 525 driver_t iflib_pseudodriver = { 526 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 527 }; 528 529 static inline void 530 rxd_info_zero(if_rxd_info_t ri) 531 { 532 if_rxd_info_pad_t ri_pad; 533 int i; 534 535 ri_pad = (if_rxd_info_pad_t)ri; 536 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 537 ri_pad->rxd_val[i] = 0; 538 ri_pad->rxd_val[i+1] = 0; 539 ri_pad->rxd_val[i+2] = 0; 540 ri_pad->rxd_val[i+3] = 0; 541 } 542 #ifdef __LP64__ 543 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 544 #endif 545 } 546 547 /* 548 * Only allow a single packet to take up most 1/nth of the tx ring 549 */ 550 #define MAX_SINGLE_PACKET_FRACTION 12 551 #define IF_BAD_DMA (bus_addr_t)-1 552 553 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 554 555 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 556 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 557 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 558 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 559 560 561 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 562 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 563 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 564 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 565 566 567 568 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 569 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 570 571 572 /* Our boot-time initialization hook */ 573 static int iflib_module_event_handler(module_t, int, void *); 574 575 static moduledata_t iflib_moduledata = { 576 "iflib", 577 iflib_module_event_handler, 578 NULL 579 }; 580 581 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 582 MODULE_VERSION(iflib, 1); 583 584 MODULE_DEPEND(iflib, pci, 1, 1, 1); 585 MODULE_DEPEND(iflib, ether, 1, 1, 1); 586 587 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 588 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 589 590 #ifndef IFLIB_DEBUG_COUNTERS 591 #ifdef INVARIANTS 592 #define IFLIB_DEBUG_COUNTERS 1 593 #else 594 #define IFLIB_DEBUG_COUNTERS 0 595 #endif /* !INVARIANTS */ 596 #endif 597 598 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 599 "iflib driver parameters"); 600 601 /* 602 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 603 */ 604 static int iflib_min_tx_latency = 0; 605 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 606 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 607 static int iflib_no_tx_batch = 0; 608 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 609 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 610 611 612 #if IFLIB_DEBUG_COUNTERS 613 614 static int iflib_tx_seen; 615 static int iflib_tx_sent; 616 static int iflib_tx_encap; 617 static int iflib_rx_allocs; 618 static int iflib_fl_refills; 619 static int iflib_fl_refills_large; 620 static int iflib_tx_frees; 621 622 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 623 &iflib_tx_seen, 0, "# tx mbufs seen"); 624 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 625 &iflib_tx_sent, 0, "# tx mbufs sent"); 626 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 627 &iflib_tx_encap, 0, "# tx mbufs encapped"); 628 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 629 &iflib_tx_frees, 0, "# tx frees"); 630 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 631 &iflib_rx_allocs, 0, "# rx allocations"); 632 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 633 &iflib_fl_refills, 0, "# refills"); 634 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 635 &iflib_fl_refills_large, 0, "# large refills"); 636 637 638 static int iflib_txq_drain_flushing; 639 static int iflib_txq_drain_oactive; 640 static int iflib_txq_drain_notready; 641 static int iflib_txq_drain_encapfail; 642 643 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 644 &iflib_txq_drain_flushing, 0, "# drain flushes"); 645 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 646 &iflib_txq_drain_oactive, 0, "# drain oactives"); 647 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 648 &iflib_txq_drain_notready, 0, "# drain notready"); 649 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 650 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 651 652 653 static int iflib_encap_load_mbuf_fail; 654 static int iflib_encap_pad_mbuf_fail; 655 static int iflib_encap_txq_avail_fail; 656 static int iflib_encap_txd_encap_fail; 657 658 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 659 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 661 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 663 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 665 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 666 667 static int iflib_task_fn_rxs; 668 static int iflib_rx_intr_enables; 669 static int iflib_fast_intrs; 670 static int iflib_intr_link; 671 static int iflib_intr_msix; 672 static int iflib_rx_unavail; 673 static int iflib_rx_ctx_inactive; 674 static int iflib_rx_zero_len; 675 static int iflib_rx_if_input; 676 static int iflib_rx_mbuf_null; 677 static int iflib_rxd_flush; 678 679 static int iflib_verbose_debug; 680 681 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 682 &iflib_intr_link, 0, "# intr link calls"); 683 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 684 &iflib_intr_msix, 0, "# intr msix calls"); 685 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 686 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 687 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 688 &iflib_rx_intr_enables, 0, "# rx intr enables"); 689 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 690 &iflib_fast_intrs, 0, "# fast_intr calls"); 691 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 692 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 693 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 694 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 695 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 696 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 697 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 698 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 699 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 700 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 701 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 702 &iflib_rxd_flush, 0, "# times rxd_flush called"); 703 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 704 &iflib_verbose_debug, 0, "enable verbose debugging"); 705 706 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 707 static void 708 iflib_debug_reset(void) 709 { 710 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 711 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 712 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 713 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 714 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 715 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 716 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 717 iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 718 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 719 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 720 } 721 722 #else 723 #define DBG_COUNTER_INC(name) 724 static void iflib_debug_reset(void) {} 725 #endif 726 727 #define IFLIB_DEBUG 0 728 729 static void iflib_tx_structures_free(if_ctx_t ctx); 730 static void iflib_rx_structures_free(if_ctx_t ctx); 731 static int iflib_queues_alloc(if_ctx_t ctx); 732 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 733 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 734 static int iflib_qset_structures_setup(if_ctx_t ctx); 735 static int iflib_msix_init(if_ctx_t ctx); 736 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str); 737 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 738 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 739 static int iflib_register(if_ctx_t); 740 static void iflib_init_locked(if_ctx_t ctx); 741 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 742 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 743 static void iflib_ifmp_purge(iflib_txq_t txq); 744 static void _iflib_pre_assert(if_softc_ctx_t scctx); 745 static void iflib_if_init_locked(if_ctx_t ctx); 746 #ifndef __NO_STRICT_ALIGNMENT 747 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 748 #endif 749 750 NETDUMP_DEFINE(iflib); 751 752 #ifdef DEV_NETMAP 753 #include <sys/selinfo.h> 754 #include <net/netmap.h> 755 #include <dev/netmap/netmap_kern.h> 756 757 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 758 759 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 760 761 /* 762 * device-specific sysctl variables: 763 * 764 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 765 * During regular operations the CRC is stripped, but on some 766 * hardware reception of frames not multiple of 64 is slower, 767 * so using crcstrip=0 helps in benchmarks. 768 * 769 * iflib_rx_miss, iflib_rx_miss_bufs: 770 * count packets that might be missed due to lost interrupts. 771 */ 772 SYSCTL_DECL(_dev_netmap); 773 /* 774 * The xl driver by default strips CRCs and we do not override it. 775 */ 776 777 int iflib_crcstrip = 1; 778 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 779 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 780 781 int iflib_rx_miss, iflib_rx_miss_bufs; 782 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 783 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 784 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 785 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 786 787 /* 788 * Register/unregister. We are already under netmap lock. 789 * Only called on the first register or the last unregister. 790 */ 791 static int 792 iflib_netmap_register(struct netmap_adapter *na, int onoff) 793 { 794 struct ifnet *ifp = na->ifp; 795 if_ctx_t ctx = ifp->if_softc; 796 int status; 797 798 CTX_LOCK(ctx); 799 IFDI_INTR_DISABLE(ctx); 800 801 /* Tell the stack that the interface is no longer active */ 802 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 803 804 if (!CTX_IS_VF(ctx)) 805 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 806 807 /* enable or disable flags and callbacks in na and ifp */ 808 if (onoff) { 809 nm_set_native_flags(na); 810 } else { 811 nm_clear_native_flags(na); 812 } 813 iflib_stop(ctx); 814 iflib_init_locked(ctx); 815 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 816 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 817 if (status) 818 nm_clear_native_flags(na); 819 CTX_UNLOCK(ctx); 820 return (status); 821 } 822 823 static int 824 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 825 { 826 struct netmap_adapter *na = kring->na; 827 u_int const lim = kring->nkr_num_slots - 1; 828 u_int head = kring->rhead; 829 struct netmap_ring *ring = kring->ring; 830 bus_dmamap_t *map; 831 struct if_rxd_update iru; 832 if_ctx_t ctx = rxq->ifr_ctx; 833 iflib_fl_t fl = &rxq->ifr_fl[0]; 834 uint32_t refill_pidx, nic_i; 835 836 if (nm_i == head && __predict_true(!init)) 837 return 0; 838 iru_init(&iru, rxq, 0 /* flid */); 839 map = fl->ifl_sds.ifsd_map; 840 refill_pidx = netmap_idx_k2n(kring, nm_i); 841 /* 842 * IMPORTANT: we must leave one free slot in the ring, 843 * so move head back by one unit 844 */ 845 head = nm_prev(head, lim); 846 nic_i = UINT_MAX; 847 while (nm_i != head) { 848 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 849 struct netmap_slot *slot = &ring->slot[nm_i]; 850 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 851 uint32_t nic_i_dma = refill_pidx; 852 nic_i = netmap_idx_k2n(kring, nm_i); 853 854 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 855 856 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 857 return netmap_ring_reinit(kring); 858 859 fl->ifl_vm_addrs[tmp_pidx] = addr; 860 if (__predict_false(init) && map) { 861 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 862 } else if (map && (slot->flags & NS_BUF_CHANGED)) { 863 /* buffer has changed, reload map */ 864 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 865 } 866 slot->flags &= ~NS_BUF_CHANGED; 867 868 nm_i = nm_next(nm_i, lim); 869 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 870 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 871 continue; 872 873 iru.iru_pidx = refill_pidx; 874 iru.iru_count = tmp_pidx+1; 875 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 876 877 refill_pidx = nic_i; 878 if (map == NULL) 879 continue; 880 881 for (int n = 0; n < iru.iru_count; n++) { 882 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma], 883 BUS_DMASYNC_PREREAD); 884 /* XXX - change this to not use the netmap func*/ 885 nic_i_dma = nm_next(nic_i_dma, lim); 886 } 887 } 888 } 889 kring->nr_hwcur = head; 890 891 if (map) 892 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 893 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 894 if (__predict_true(nic_i != UINT_MAX)) 895 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 896 return (0); 897 } 898 899 /* 900 * Reconcile kernel and user view of the transmit ring. 901 * 902 * All information is in the kring. 903 * Userspace wants to send packets up to the one before kring->rhead, 904 * kernel knows kring->nr_hwcur is the first unsent packet. 905 * 906 * Here we push packets out (as many as possible), and possibly 907 * reclaim buffers from previously completed transmission. 908 * 909 * The caller (netmap) guarantees that there is only one instance 910 * running at any time. Any interference with other driver 911 * methods should be handled by the individual drivers. 912 */ 913 static int 914 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 915 { 916 struct netmap_adapter *na = kring->na; 917 struct ifnet *ifp = na->ifp; 918 struct netmap_ring *ring = kring->ring; 919 u_int nm_i; /* index into the netmap ring */ 920 u_int nic_i; /* index into the NIC ring */ 921 u_int n; 922 u_int const lim = kring->nkr_num_slots - 1; 923 u_int const head = kring->rhead; 924 struct if_pkt_info pi; 925 926 /* 927 * interrupts on every tx packet are expensive so request 928 * them every half ring, or where NS_REPORT is set 929 */ 930 u_int report_frequency = kring->nkr_num_slots >> 1; 931 /* device-specific */ 932 if_ctx_t ctx = ifp->if_softc; 933 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 934 935 if (txq->ift_sds.ifsd_map) 936 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 937 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 938 939 940 /* 941 * First part: process new packets to send. 942 * nm_i is the current index in the netmap ring, 943 * nic_i is the corresponding index in the NIC ring. 944 * 945 * If we have packets to send (nm_i != head) 946 * iterate over the netmap ring, fetch length and update 947 * the corresponding slot in the NIC ring. Some drivers also 948 * need to update the buffer's physical address in the NIC slot 949 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 950 * 951 * The netmap_reload_map() calls is especially expensive, 952 * even when (as in this case) the tag is 0, so do only 953 * when the buffer has actually changed. 954 * 955 * If possible do not set the report/intr bit on all slots, 956 * but only a few times per ring or when NS_REPORT is set. 957 * 958 * Finally, on 10G and faster drivers, it might be useful 959 * to prefetch the next slot and txr entry. 960 */ 961 962 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 963 pkt_info_zero(&pi); 964 pi.ipi_segs = txq->ift_segs; 965 pi.ipi_qsidx = kring->ring_id; 966 if (nm_i != head) { /* we have new packets to send */ 967 nic_i = netmap_idx_k2n(kring, nm_i); 968 969 __builtin_prefetch(&ring->slot[nm_i]); 970 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 971 if (txq->ift_sds.ifsd_map) 972 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 973 974 for (n = 0; nm_i != head; n++) { 975 struct netmap_slot *slot = &ring->slot[nm_i]; 976 u_int len = slot->len; 977 uint64_t paddr; 978 void *addr = PNMB(na, slot, &paddr); 979 int flags = (slot->flags & NS_REPORT || 980 nic_i == 0 || nic_i == report_frequency) ? 981 IPI_TX_INTR : 0; 982 983 /* device-specific */ 984 pi.ipi_len = len; 985 pi.ipi_segs[0].ds_addr = paddr; 986 pi.ipi_segs[0].ds_len = len; 987 pi.ipi_nsegs = 1; 988 pi.ipi_ndescs = 0; 989 pi.ipi_pidx = nic_i; 990 pi.ipi_flags = flags; 991 992 /* Fill the slot in the NIC ring. */ 993 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 994 995 /* prefetch for next round */ 996 __builtin_prefetch(&ring->slot[nm_i + 1]); 997 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 998 if (txq->ift_sds.ifsd_map) { 999 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1000 1001 NM_CHECK_ADDR_LEN(na, addr, len); 1002 1003 if (slot->flags & NS_BUF_CHANGED) { 1004 /* buffer has changed, reload map */ 1005 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 1006 } 1007 /* make sure changes to the buffer are synced */ 1008 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 1009 BUS_DMASYNC_PREWRITE); 1010 } 1011 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1012 nm_i = nm_next(nm_i, lim); 1013 nic_i = nm_next(nic_i, lim); 1014 } 1015 kring->nr_hwcur = head; 1016 1017 /* synchronize the NIC ring */ 1018 if (txq->ift_sds.ifsd_map) 1019 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 1020 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1021 1022 /* (re)start the tx unit up to slot nic_i (excluded) */ 1023 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1024 } 1025 1026 /* 1027 * Second part: reclaim buffers for completed transmissions. 1028 */ 1029 if (iflib_tx_credits_update(ctx, txq)) { 1030 /* some tx completed, increment avail */ 1031 nic_i = txq->ift_cidx_processed; 1032 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1033 } 1034 return (0); 1035 } 1036 1037 /* 1038 * Reconcile kernel and user view of the receive ring. 1039 * Same as for the txsync, this routine must be efficient. 1040 * The caller guarantees a single invocations, but races against 1041 * the rest of the driver should be handled here. 1042 * 1043 * On call, kring->rhead is the first packet that userspace wants 1044 * to keep, and kring->rcur is the wakeup point. 1045 * The kernel has previously reported packets up to kring->rtail. 1046 * 1047 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1048 * of whether or not we received an interrupt. 1049 */ 1050 static int 1051 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1052 { 1053 struct netmap_adapter *na = kring->na; 1054 struct netmap_ring *ring = kring->ring; 1055 uint32_t nm_i; /* index into the netmap ring */ 1056 uint32_t nic_i; /* index into the NIC ring */ 1057 u_int i, n; 1058 u_int const lim = kring->nkr_num_slots - 1; 1059 u_int const head = netmap_idx_n2k(kring, kring->rhead); 1060 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1061 struct if_rxd_info ri; 1062 1063 struct ifnet *ifp = na->ifp; 1064 if_ctx_t ctx = ifp->if_softc; 1065 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1066 iflib_fl_t fl = rxq->ifr_fl; 1067 if (head > lim) 1068 return netmap_ring_reinit(kring); 1069 1070 /* XXX check sync modes */ 1071 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1072 if (fl->ifl_sds.ifsd_map == NULL) 1073 continue; 1074 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 1075 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1076 } 1077 /* 1078 * First part: import newly received packets. 1079 * 1080 * nm_i is the index of the next free slot in the netmap ring, 1081 * nic_i is the index of the next received packet in the NIC ring, 1082 * and they may differ in case if_init() has been called while 1083 * in netmap mode. For the receive ring we have 1084 * 1085 * nic_i = rxr->next_check; 1086 * nm_i = kring->nr_hwtail (previous) 1087 * and 1088 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1089 * 1090 * rxr->next_check is set to 0 on a ring reinit 1091 */ 1092 if (netmap_no_pendintr || force_update) { 1093 int crclen = iflib_crcstrip ? 0 : 4; 1094 int error, avail; 1095 1096 for (i = 0; i < rxq->ifr_nfl; i++) { 1097 fl = &rxq->ifr_fl[i]; 1098 nic_i = fl->ifl_cidx; 1099 nm_i = netmap_idx_n2k(kring, nic_i); 1100 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 1101 for (n = 0; avail > 0; n++, avail--) { 1102 rxd_info_zero(&ri); 1103 ri.iri_frags = rxq->ifr_frags; 1104 ri.iri_qsidx = kring->ring_id; 1105 ri.iri_ifp = ctx->ifc_ifp; 1106 ri.iri_cidx = nic_i; 1107 1108 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1109 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1110 ring->slot[nm_i].flags = 0; 1111 if (fl->ifl_sds.ifsd_map) 1112 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1113 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1114 nm_i = nm_next(nm_i, lim); 1115 nic_i = nm_next(nic_i, lim); 1116 } 1117 if (n) { /* update the state variables */ 1118 if (netmap_no_pendintr && !force_update) { 1119 /* diagnostics */ 1120 iflib_rx_miss ++; 1121 iflib_rx_miss_bufs += n; 1122 } 1123 fl->ifl_cidx = nic_i; 1124 kring->nr_hwtail = netmap_idx_k2n(kring, nm_i); 1125 } 1126 kring->nr_kflags &= ~NKR_PENDINTR; 1127 } 1128 } 1129 /* 1130 * Second part: skip past packets that userspace has released. 1131 * (kring->nr_hwcur to head excluded), 1132 * and make the buffers available for reception. 1133 * As usual nm_i is the index in the netmap ring, 1134 * nic_i is the index in the NIC ring, and 1135 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1136 */ 1137 /* XXX not sure how this will work with multiple free lists */ 1138 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 1139 1140 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1141 } 1142 1143 static void 1144 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1145 { 1146 struct ifnet *ifp = na->ifp; 1147 if_ctx_t ctx = ifp->if_softc; 1148 1149 CTX_LOCK(ctx); 1150 if (onoff) { 1151 IFDI_INTR_ENABLE(ctx); 1152 } else { 1153 IFDI_INTR_DISABLE(ctx); 1154 } 1155 CTX_UNLOCK(ctx); 1156 } 1157 1158 1159 static int 1160 iflib_netmap_attach(if_ctx_t ctx) 1161 { 1162 struct netmap_adapter na; 1163 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1164 1165 bzero(&na, sizeof(na)); 1166 1167 na.ifp = ctx->ifc_ifp; 1168 na.na_flags = NAF_BDG_MAYSLEEP; 1169 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1170 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1171 1172 na.num_tx_desc = scctx->isc_ntxd[0]; 1173 na.num_rx_desc = scctx->isc_nrxd[0]; 1174 na.nm_txsync = iflib_netmap_txsync; 1175 na.nm_rxsync = iflib_netmap_rxsync; 1176 na.nm_register = iflib_netmap_register; 1177 na.nm_intr = iflib_netmap_intr; 1178 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1179 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1180 return (netmap_attach(&na)); 1181 } 1182 1183 static void 1184 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1185 { 1186 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1187 struct netmap_slot *slot; 1188 1189 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1190 if (slot == NULL) 1191 return; 1192 if (txq->ift_sds.ifsd_map == NULL) 1193 return; 1194 1195 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1196 1197 /* 1198 * In netmap mode, set the map for the packet buffer. 1199 * NOTE: Some drivers (not this one) also need to set 1200 * the physical buffer address in the NIC ring. 1201 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1202 * netmap slot index, si 1203 */ 1204 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1205 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1206 } 1207 } 1208 1209 static void 1210 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1211 { 1212 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1213 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1214 struct netmap_slot *slot; 1215 uint32_t nm_i; 1216 1217 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1218 if (slot == NULL) 1219 return; 1220 nm_i = netmap_idx_n2k(kring, 0); 1221 netmap_fl_refill(rxq, kring, nm_i, true); 1222 } 1223 1224 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1225 1226 #else 1227 #define iflib_netmap_txq_init(ctx, txq) 1228 #define iflib_netmap_rxq_init(ctx, rxq) 1229 #define iflib_netmap_detach(ifp) 1230 1231 #define iflib_netmap_attach(ctx) (0) 1232 #define netmap_rx_irq(ifp, qid, budget) (0) 1233 #define netmap_tx_irq(ifp, qid) do {} while (0) 1234 1235 #endif 1236 1237 #if defined(__i386__) || defined(__amd64__) 1238 static __inline void 1239 prefetch(void *x) 1240 { 1241 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1242 } 1243 static __inline void 1244 prefetch2cachelines(void *x) 1245 { 1246 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1247 #if (CACHE_LINE_SIZE < 128) 1248 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1249 #endif 1250 } 1251 #else 1252 #define prefetch(x) 1253 #define prefetch2cachelines(x) 1254 #endif 1255 1256 static void 1257 iflib_gen_mac(if_ctx_t ctx) 1258 { 1259 struct thread *td; 1260 struct ifnet *ifp; 1261 MD5_CTX mdctx; 1262 char uuid[HOSTUUIDLEN+1]; 1263 char buf[HOSTUUIDLEN+16]; 1264 uint8_t *mac; 1265 unsigned char digest[16]; 1266 1267 td = curthread; 1268 ifp = ctx->ifc_ifp; 1269 mac = ctx->ifc_mac; 1270 uuid[HOSTUUIDLEN] = 0; 1271 bcopy(td->td_ucred->cr_prison->pr_hostuuid, uuid, HOSTUUIDLEN); 1272 snprintf(buf, HOSTUUIDLEN+16, "%s-%s", uuid, device_get_nameunit(ctx->ifc_dev)); 1273 /* 1274 * Generate a pseudo-random, deterministic MAC 1275 * address based on the UUID and unit number. 1276 * The FreeBSD Foundation OUI of 58-9C-FC is used. 1277 */ 1278 MD5Init(&mdctx); 1279 MD5Update(&mdctx, buf, strlen(buf)); 1280 MD5Final(digest, &mdctx); 1281 1282 mac[0] = 0x58; 1283 mac[1] = 0x9C; 1284 mac[2] = 0xFC; 1285 mac[3] = digest[0]; 1286 mac[4] = digest[1]; 1287 mac[5] = digest[2]; 1288 } 1289 1290 static void 1291 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1292 { 1293 iflib_fl_t fl; 1294 1295 fl = &rxq->ifr_fl[flid]; 1296 iru->iru_paddrs = fl->ifl_bus_addrs; 1297 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1298 iru->iru_idxs = fl->ifl_rxd_idxs; 1299 iru->iru_qsidx = rxq->ifr_id; 1300 iru->iru_buf_size = fl->ifl_buf_size; 1301 iru->iru_flidx = fl->ifl_id; 1302 } 1303 1304 static void 1305 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1306 { 1307 if (err) 1308 return; 1309 *(bus_addr_t *) arg = segs[0].ds_addr; 1310 } 1311 1312 int 1313 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1314 { 1315 int err; 1316 if_shared_ctx_t sctx = ctx->ifc_sctx; 1317 device_t dev = ctx->ifc_dev; 1318 1319 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1320 1321 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1322 sctx->isc_q_align, 0, /* alignment, bounds */ 1323 BUS_SPACE_MAXADDR, /* lowaddr */ 1324 BUS_SPACE_MAXADDR, /* highaddr */ 1325 NULL, NULL, /* filter, filterarg */ 1326 size, /* maxsize */ 1327 1, /* nsegments */ 1328 size, /* maxsegsize */ 1329 BUS_DMA_ALLOCNOW, /* flags */ 1330 NULL, /* lockfunc */ 1331 NULL, /* lockarg */ 1332 &dma->idi_tag); 1333 if (err) { 1334 device_printf(dev, 1335 "%s: bus_dma_tag_create failed: %d\n", 1336 __func__, err); 1337 goto fail_0; 1338 } 1339 1340 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1341 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1342 if (err) { 1343 device_printf(dev, 1344 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1345 __func__, (uintmax_t)size, err); 1346 goto fail_1; 1347 } 1348 1349 dma->idi_paddr = IF_BAD_DMA; 1350 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1351 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1352 if (err || dma->idi_paddr == IF_BAD_DMA) { 1353 device_printf(dev, 1354 "%s: bus_dmamap_load failed: %d\n", 1355 __func__, err); 1356 goto fail_2; 1357 } 1358 1359 dma->idi_size = size; 1360 return (0); 1361 1362 fail_2: 1363 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1364 fail_1: 1365 bus_dma_tag_destroy(dma->idi_tag); 1366 fail_0: 1367 dma->idi_tag = NULL; 1368 1369 return (err); 1370 } 1371 1372 int 1373 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1374 { 1375 int i, err; 1376 iflib_dma_info_t *dmaiter; 1377 1378 dmaiter = dmalist; 1379 for (i = 0; i < count; i++, dmaiter++) { 1380 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1381 break; 1382 } 1383 if (err) 1384 iflib_dma_free_multi(dmalist, i); 1385 return (err); 1386 } 1387 1388 void 1389 iflib_dma_free(iflib_dma_info_t dma) 1390 { 1391 if (dma->idi_tag == NULL) 1392 return; 1393 if (dma->idi_paddr != IF_BAD_DMA) { 1394 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1395 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1396 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1397 dma->idi_paddr = IF_BAD_DMA; 1398 } 1399 if (dma->idi_vaddr != NULL) { 1400 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1401 dma->idi_vaddr = NULL; 1402 } 1403 bus_dma_tag_destroy(dma->idi_tag); 1404 dma->idi_tag = NULL; 1405 } 1406 1407 void 1408 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1409 { 1410 int i; 1411 iflib_dma_info_t *dmaiter = dmalist; 1412 1413 for (i = 0; i < count; i++, dmaiter++) 1414 iflib_dma_free(*dmaiter); 1415 } 1416 1417 #ifdef EARLY_AP_STARTUP 1418 static const int iflib_started = 1; 1419 #else 1420 /* 1421 * We used to abuse the smp_started flag to decide if the queues have been 1422 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1423 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1424 * is set. Run a SYSINIT() strictly after that to just set a usable 1425 * completion flag. 1426 */ 1427 1428 static int iflib_started; 1429 1430 static void 1431 iflib_record_started(void *arg) 1432 { 1433 iflib_started = 1; 1434 } 1435 1436 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1437 iflib_record_started, NULL); 1438 #endif 1439 1440 static int 1441 iflib_fast_intr(void *arg) 1442 { 1443 iflib_filter_info_t info = arg; 1444 struct grouptask *gtask = info->ifi_task; 1445 if (!iflib_started) 1446 return (FILTER_HANDLED); 1447 1448 DBG_COUNTER_INC(fast_intrs); 1449 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1450 return (FILTER_HANDLED); 1451 1452 GROUPTASK_ENQUEUE(gtask); 1453 return (FILTER_HANDLED); 1454 } 1455 1456 static int 1457 iflib_fast_intr_rxtx(void *arg) 1458 { 1459 iflib_filter_info_t info = arg; 1460 struct grouptask *gtask = info->ifi_task; 1461 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1462 if_ctx_t ctx = NULL;; 1463 int i, cidx; 1464 1465 if (!iflib_started) 1466 return (FILTER_HANDLED); 1467 1468 DBG_COUNTER_INC(fast_intrs); 1469 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1470 return (FILTER_HANDLED); 1471 1472 MPASS(rxq->ifr_ntxqirq); 1473 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1474 qidx_t txqid = rxq->ifr_txqid[i]; 1475 1476 ctx = rxq->ifr_ctx; 1477 1478 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1479 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1480 continue; 1481 } 1482 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1483 } 1484 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1485 cidx = rxq->ifr_cq_cidx; 1486 else 1487 cidx = rxq->ifr_fl[0].ifl_cidx; 1488 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1489 GROUPTASK_ENQUEUE(gtask); 1490 else 1491 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1492 return (FILTER_HANDLED); 1493 } 1494 1495 1496 static int 1497 iflib_fast_intr_ctx(void *arg) 1498 { 1499 iflib_filter_info_t info = arg; 1500 struct grouptask *gtask = info->ifi_task; 1501 1502 if (!iflib_started) 1503 return (FILTER_HANDLED); 1504 1505 DBG_COUNTER_INC(fast_intrs); 1506 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1507 return (FILTER_HANDLED); 1508 1509 GROUPTASK_ENQUEUE(gtask); 1510 return (FILTER_HANDLED); 1511 } 1512 1513 static int 1514 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1515 driver_filter_t filter, driver_intr_t handler, void *arg, 1516 char *name) 1517 { 1518 int rc, flags; 1519 struct resource *res; 1520 void *tag = NULL; 1521 device_t dev = ctx->ifc_dev; 1522 1523 flags = RF_ACTIVE; 1524 if (ctx->ifc_flags & IFC_LEGACY) 1525 flags |= RF_SHAREABLE; 1526 MPASS(rid < 512); 1527 irq->ii_rid = rid; 1528 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1529 if (res == NULL) { 1530 device_printf(dev, 1531 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1532 return (ENOMEM); 1533 } 1534 irq->ii_res = res; 1535 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1536 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1537 filter, handler, arg, &tag); 1538 if (rc != 0) { 1539 device_printf(dev, 1540 "failed to setup interrupt for rid %d, name %s: %d\n", 1541 rid, name ? name : "unknown", rc); 1542 return (rc); 1543 } else if (name) 1544 bus_describe_intr(dev, res, tag, "%s", name); 1545 1546 irq->ii_tag = tag; 1547 return (0); 1548 } 1549 1550 1551 /********************************************************************* 1552 * 1553 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1554 * the information needed to transmit a packet on the wire. This is 1555 * called only once at attach, setup is done every reset. 1556 * 1557 **********************************************************************/ 1558 1559 static int 1560 iflib_txsd_alloc(iflib_txq_t txq) 1561 { 1562 if_ctx_t ctx = txq->ift_ctx; 1563 if_shared_ctx_t sctx = ctx->ifc_sctx; 1564 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1565 device_t dev = ctx->ifc_dev; 1566 int err, nsegments, ntsosegments; 1567 1568 nsegments = scctx->isc_tx_nsegments; 1569 ntsosegments = scctx->isc_tx_tso_segments_max; 1570 MPASS(scctx->isc_ntxd[0] > 0); 1571 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1572 MPASS(nsegments > 0); 1573 MPASS(ntsosegments > 0); 1574 /* 1575 * Setup DMA descriptor areas. 1576 */ 1577 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1578 1, 0, /* alignment, bounds */ 1579 BUS_SPACE_MAXADDR, /* lowaddr */ 1580 BUS_SPACE_MAXADDR, /* highaddr */ 1581 NULL, NULL, /* filter, filterarg */ 1582 sctx->isc_tx_maxsize, /* maxsize */ 1583 nsegments, /* nsegments */ 1584 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1585 0, /* flags */ 1586 NULL, /* lockfunc */ 1587 NULL, /* lockfuncarg */ 1588 &txq->ift_desc_tag))) { 1589 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1590 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1591 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1592 goto fail; 1593 } 1594 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1595 1, 0, /* alignment, bounds */ 1596 BUS_SPACE_MAXADDR, /* lowaddr */ 1597 BUS_SPACE_MAXADDR, /* highaddr */ 1598 NULL, NULL, /* filter, filterarg */ 1599 scctx->isc_tx_tso_size_max, /* maxsize */ 1600 ntsosegments, /* nsegments */ 1601 scctx->isc_tx_tso_segsize_max, /* maxsegsize */ 1602 0, /* flags */ 1603 NULL, /* lockfunc */ 1604 NULL, /* lockfuncarg */ 1605 &txq->ift_tso_desc_tag))) { 1606 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1607 1608 goto fail; 1609 } 1610 if (!(txq->ift_sds.ifsd_flags = 1611 (uint8_t *) malloc(sizeof(uint8_t) * 1612 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1613 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1614 err = ENOMEM; 1615 goto fail; 1616 } 1617 if (!(txq->ift_sds.ifsd_m = 1618 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1619 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1620 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1621 err = ENOMEM; 1622 goto fail; 1623 } 1624 1625 /* Create the descriptor buffer dma maps */ 1626 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1627 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1628 return (0); 1629 1630 if (!(txq->ift_sds.ifsd_map = 1631 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1632 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1633 err = ENOMEM; 1634 goto fail; 1635 } 1636 1637 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1638 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1639 if (err != 0) { 1640 device_printf(dev, "Unable to create TX DMA map\n"); 1641 goto fail; 1642 } 1643 } 1644 #endif 1645 return (0); 1646 fail: 1647 /* We free all, it handles case where we are in the middle */ 1648 iflib_tx_structures_free(ctx); 1649 return (err); 1650 } 1651 1652 static void 1653 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1654 { 1655 bus_dmamap_t map; 1656 1657 map = NULL; 1658 if (txq->ift_sds.ifsd_map != NULL) 1659 map = txq->ift_sds.ifsd_map[i]; 1660 if (map != NULL) { 1661 bus_dmamap_unload(txq->ift_desc_tag, map); 1662 bus_dmamap_destroy(txq->ift_desc_tag, map); 1663 txq->ift_sds.ifsd_map[i] = NULL; 1664 } 1665 } 1666 1667 static void 1668 iflib_txq_destroy(iflib_txq_t txq) 1669 { 1670 if_ctx_t ctx = txq->ift_ctx; 1671 1672 for (int i = 0; i < txq->ift_size; i++) 1673 iflib_txsd_destroy(ctx, txq, i); 1674 if (txq->ift_sds.ifsd_map != NULL) { 1675 free(txq->ift_sds.ifsd_map, M_IFLIB); 1676 txq->ift_sds.ifsd_map = NULL; 1677 } 1678 if (txq->ift_sds.ifsd_m != NULL) { 1679 free(txq->ift_sds.ifsd_m, M_IFLIB); 1680 txq->ift_sds.ifsd_m = NULL; 1681 } 1682 if (txq->ift_sds.ifsd_flags != NULL) { 1683 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1684 txq->ift_sds.ifsd_flags = NULL; 1685 } 1686 if (txq->ift_desc_tag != NULL) { 1687 bus_dma_tag_destroy(txq->ift_desc_tag); 1688 txq->ift_desc_tag = NULL; 1689 } 1690 if (txq->ift_tso_desc_tag != NULL) { 1691 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1692 txq->ift_tso_desc_tag = NULL; 1693 } 1694 } 1695 1696 static void 1697 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1698 { 1699 struct mbuf **mp; 1700 1701 mp = &txq->ift_sds.ifsd_m[i]; 1702 if (*mp == NULL) 1703 return; 1704 1705 if (txq->ift_sds.ifsd_map != NULL) { 1706 bus_dmamap_sync(txq->ift_desc_tag, 1707 txq->ift_sds.ifsd_map[i], 1708 BUS_DMASYNC_POSTWRITE); 1709 bus_dmamap_unload(txq->ift_desc_tag, 1710 txq->ift_sds.ifsd_map[i]); 1711 } 1712 m_free(*mp); 1713 DBG_COUNTER_INC(tx_frees); 1714 *mp = NULL; 1715 } 1716 1717 static int 1718 iflib_txq_setup(iflib_txq_t txq) 1719 { 1720 if_ctx_t ctx = txq->ift_ctx; 1721 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1722 iflib_dma_info_t di; 1723 int i; 1724 1725 /* Set number of descriptors available */ 1726 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1727 /* XXX make configurable */ 1728 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1729 1730 /* Reset indices */ 1731 txq->ift_cidx_processed = 0; 1732 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1733 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1734 1735 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1736 bzero((void *)di->idi_vaddr, di->idi_size); 1737 1738 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1739 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1740 bus_dmamap_sync(di->idi_tag, di->idi_map, 1741 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1742 return (0); 1743 } 1744 1745 /********************************************************************* 1746 * 1747 * Allocate memory for rx_buffer structures. Since we use one 1748 * rx_buffer per received packet, the maximum number of rx_buffer's 1749 * that we'll need is equal to the number of receive descriptors 1750 * that we've allocated. 1751 * 1752 **********************************************************************/ 1753 static int 1754 iflib_rxsd_alloc(iflib_rxq_t rxq) 1755 { 1756 if_ctx_t ctx = rxq->ifr_ctx; 1757 if_shared_ctx_t sctx = ctx->ifc_sctx; 1758 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1759 device_t dev = ctx->ifc_dev; 1760 iflib_fl_t fl; 1761 int err; 1762 1763 MPASS(scctx->isc_nrxd[0] > 0); 1764 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1765 1766 fl = rxq->ifr_fl; 1767 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1768 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1769 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1770 1, 0, /* alignment, bounds */ 1771 BUS_SPACE_MAXADDR, /* lowaddr */ 1772 BUS_SPACE_MAXADDR, /* highaddr */ 1773 NULL, NULL, /* filter, filterarg */ 1774 sctx->isc_rx_maxsize, /* maxsize */ 1775 sctx->isc_rx_nsegments, /* nsegments */ 1776 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1777 0, /* flags */ 1778 NULL, /* lockfunc */ 1779 NULL, /* lockarg */ 1780 &fl->ifl_desc_tag); 1781 if (err) { 1782 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1783 __func__, err); 1784 goto fail; 1785 } 1786 if (!(fl->ifl_sds.ifsd_flags = 1787 (uint8_t *) malloc(sizeof(uint8_t) * 1788 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1789 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1790 err = ENOMEM; 1791 goto fail; 1792 } 1793 if (!(fl->ifl_sds.ifsd_m = 1794 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1795 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1796 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1797 err = ENOMEM; 1798 goto fail; 1799 } 1800 if (!(fl->ifl_sds.ifsd_cl = 1801 (caddr_t *) malloc(sizeof(caddr_t) * 1802 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1803 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1804 err = ENOMEM; 1805 goto fail; 1806 } 1807 1808 /* Create the descriptor buffer dma maps */ 1809 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1810 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1811 continue; 1812 1813 if (!(fl->ifl_sds.ifsd_map = 1814 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1815 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1816 err = ENOMEM; 1817 goto fail; 1818 } 1819 1820 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1821 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1822 if (err != 0) { 1823 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1824 goto fail; 1825 } 1826 } 1827 #endif 1828 } 1829 return (0); 1830 1831 fail: 1832 iflib_rx_structures_free(ctx); 1833 return (err); 1834 } 1835 1836 1837 /* 1838 * Internal service routines 1839 */ 1840 1841 struct rxq_refill_cb_arg { 1842 int error; 1843 bus_dma_segment_t seg; 1844 int nseg; 1845 }; 1846 1847 static void 1848 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1849 { 1850 struct rxq_refill_cb_arg *cb_arg = arg; 1851 1852 cb_arg->error = error; 1853 cb_arg->seg = segs[0]; 1854 cb_arg->nseg = nseg; 1855 } 1856 1857 1858 #ifdef ACPI_DMAR 1859 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1860 #else 1861 #define IS_DMAR(ctx) (0) 1862 #endif 1863 1864 /** 1865 * rxq_refill - refill an rxq free-buffer list 1866 * @ctx: the iflib context 1867 * @rxq: the free-list to refill 1868 * @n: the number of new buffers to allocate 1869 * 1870 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1871 * The caller must assure that @n does not exceed the queue's capacity. 1872 */ 1873 static void 1874 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1875 { 1876 struct mbuf *m; 1877 int idx, frag_idx = fl->ifl_fragidx; 1878 int pidx = fl->ifl_pidx; 1879 caddr_t cl, *sd_cl; 1880 struct mbuf **sd_m; 1881 uint8_t *sd_flags; 1882 struct if_rxd_update iru; 1883 bus_dmamap_t *sd_map; 1884 int n, i = 0; 1885 uint64_t bus_addr; 1886 int err; 1887 qidx_t credits; 1888 1889 sd_m = fl->ifl_sds.ifsd_m; 1890 sd_map = fl->ifl_sds.ifsd_map; 1891 sd_cl = fl->ifl_sds.ifsd_cl; 1892 sd_flags = fl->ifl_sds.ifsd_flags; 1893 idx = pidx; 1894 credits = fl->ifl_credits; 1895 1896 n = count; 1897 MPASS(n > 0); 1898 MPASS(credits + n <= fl->ifl_size); 1899 1900 if (pidx < fl->ifl_cidx) 1901 MPASS(pidx + n <= fl->ifl_cidx); 1902 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1903 MPASS(fl->ifl_gen == 0); 1904 if (pidx > fl->ifl_cidx) 1905 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1906 1907 DBG_COUNTER_INC(fl_refills); 1908 if (n > 8) 1909 DBG_COUNTER_INC(fl_refills_large); 1910 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1911 while (n--) { 1912 /* 1913 * We allocate an uninitialized mbuf + cluster, mbuf is 1914 * initialized after rx. 1915 * 1916 * If the cluster is still set then we know a minimum sized packet was received 1917 */ 1918 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1919 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1920 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1921 if ((cl = sd_cl[frag_idx]) == NULL) { 1922 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1923 break; 1924 #if MEMORY_LOGGING 1925 fl->ifl_cl_enqueued++; 1926 #endif 1927 } 1928 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1929 break; 1930 } 1931 #if MEMORY_LOGGING 1932 fl->ifl_m_enqueued++; 1933 #endif 1934 1935 DBG_COUNTER_INC(rx_allocs); 1936 #if defined(__i386__) || defined(__amd64__) 1937 if (!IS_DMAR(ctx)) { 1938 bus_addr = pmap_kextract((vm_offset_t)cl); 1939 } else 1940 #endif 1941 { 1942 struct rxq_refill_cb_arg cb_arg; 1943 1944 cb_arg.error = 0; 1945 MPASS(sd_map != NULL); 1946 MPASS(sd_map[frag_idx] != NULL); 1947 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1948 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1949 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 1950 BUS_DMASYNC_PREREAD); 1951 1952 if (err != 0 || cb_arg.error) { 1953 /* 1954 * !zone_pack ? 1955 */ 1956 if (fl->ifl_zone == zone_pack) 1957 uma_zfree(fl->ifl_zone, cl); 1958 m_free(m); 1959 n = 0; 1960 goto done; 1961 } 1962 bus_addr = cb_arg.seg.ds_addr; 1963 } 1964 bit_set(fl->ifl_rx_bitmap, frag_idx); 1965 sd_flags[frag_idx] |= RX_SW_DESC_INUSE; 1966 1967 MPASS(sd_m[frag_idx] == NULL); 1968 sd_cl[frag_idx] = cl; 1969 sd_m[frag_idx] = m; 1970 fl->ifl_rxd_idxs[i] = frag_idx; 1971 fl->ifl_bus_addrs[i] = bus_addr; 1972 fl->ifl_vm_addrs[i] = cl; 1973 credits++; 1974 i++; 1975 MPASS(credits <= fl->ifl_size); 1976 if (++idx == fl->ifl_size) { 1977 fl->ifl_gen = 1; 1978 idx = 0; 1979 } 1980 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 1981 iru.iru_pidx = pidx; 1982 iru.iru_count = i; 1983 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1984 i = 0; 1985 pidx = idx; 1986 fl->ifl_pidx = idx; 1987 fl->ifl_credits = credits; 1988 } 1989 1990 } 1991 done: 1992 if (i) { 1993 iru.iru_pidx = pidx; 1994 iru.iru_count = i; 1995 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1996 fl->ifl_pidx = idx; 1997 fl->ifl_credits = credits; 1998 } 1999 DBG_COUNTER_INC(rxd_flush); 2000 if (fl->ifl_pidx == 0) 2001 pidx = fl->ifl_size - 1; 2002 else 2003 pidx = fl->ifl_pidx - 1; 2004 2005 if (sd_map) 2006 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2007 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2008 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2009 fl->ifl_fragidx = frag_idx; 2010 } 2011 2012 static __inline void 2013 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2014 { 2015 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2016 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2017 #ifdef INVARIANTS 2018 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2019 #endif 2020 2021 MPASS(fl->ifl_credits <= fl->ifl_size); 2022 MPASS(reclaimable == delta); 2023 2024 if (reclaimable > 0) 2025 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2026 } 2027 2028 static void 2029 iflib_fl_bufs_free(iflib_fl_t fl) 2030 { 2031 iflib_dma_info_t idi = fl->ifl_ifdi; 2032 uint32_t i; 2033 2034 for (i = 0; i < fl->ifl_size; i++) { 2035 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2036 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 2037 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2038 2039 if (*sd_flags & RX_SW_DESC_INUSE) { 2040 if (fl->ifl_sds.ifsd_map != NULL) { 2041 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 2042 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 2043 if (fl->ifl_rxq->ifr_ctx->ifc_in_detach) 2044 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 2045 } 2046 if (*sd_m != NULL) { 2047 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2048 uma_zfree(zone_mbuf, *sd_m); 2049 } 2050 if (*sd_cl != NULL) 2051 uma_zfree(fl->ifl_zone, *sd_cl); 2052 *sd_flags = 0; 2053 } else { 2054 MPASS(*sd_cl == NULL); 2055 MPASS(*sd_m == NULL); 2056 } 2057 #if MEMORY_LOGGING 2058 fl->ifl_m_dequeued++; 2059 fl->ifl_cl_dequeued++; 2060 #endif 2061 *sd_cl = NULL; 2062 *sd_m = NULL; 2063 } 2064 #ifdef INVARIANTS 2065 for (i = 0; i < fl->ifl_size; i++) { 2066 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 2067 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2068 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2069 } 2070 #endif 2071 /* 2072 * Reset free list values 2073 */ 2074 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2075 bzero(idi->idi_vaddr, idi->idi_size); 2076 } 2077 2078 /********************************************************************* 2079 * 2080 * Initialize a receive ring and its buffers. 2081 * 2082 **********************************************************************/ 2083 static int 2084 iflib_fl_setup(iflib_fl_t fl) 2085 { 2086 iflib_rxq_t rxq = fl->ifl_rxq; 2087 if_ctx_t ctx = rxq->ifr_ctx; 2088 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2089 2090 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2091 /* 2092 ** Free current RX buffer structs and their mbufs 2093 */ 2094 iflib_fl_bufs_free(fl); 2095 /* Now replenish the mbufs */ 2096 MPASS(fl->ifl_credits == 0); 2097 /* 2098 * XXX don't set the max_frame_size to larger 2099 * than the hardware can handle 2100 */ 2101 if (sctx->isc_max_frame_size <= 2048) 2102 fl->ifl_buf_size = MCLBYTES; 2103 #ifndef CONTIGMALLOC_WORKS 2104 else 2105 fl->ifl_buf_size = MJUMPAGESIZE; 2106 #else 2107 else if (sctx->isc_max_frame_size <= 4096) 2108 fl->ifl_buf_size = MJUMPAGESIZE; 2109 else if (sctx->isc_max_frame_size <= 9216) 2110 fl->ifl_buf_size = MJUM9BYTES; 2111 else 2112 fl->ifl_buf_size = MJUM16BYTES; 2113 #endif 2114 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2115 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2116 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2117 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2118 2119 2120 /* avoid pre-allocating zillions of clusters to an idle card 2121 * potentially speeding up attach 2122 */ 2123 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2124 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2125 if (min(128, fl->ifl_size) != fl->ifl_credits) 2126 return (ENOBUFS); 2127 /* 2128 * handle failure 2129 */ 2130 MPASS(rxq != NULL); 2131 MPASS(fl->ifl_ifdi != NULL); 2132 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2133 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2134 return (0); 2135 } 2136 2137 /********************************************************************* 2138 * 2139 * Free receive ring data structures 2140 * 2141 **********************************************************************/ 2142 static void 2143 iflib_rx_sds_free(iflib_rxq_t rxq) 2144 { 2145 iflib_fl_t fl; 2146 int i; 2147 2148 if (rxq->ifr_fl != NULL) { 2149 for (i = 0; i < rxq->ifr_nfl; i++) { 2150 fl = &rxq->ifr_fl[i]; 2151 if (fl->ifl_desc_tag != NULL) { 2152 bus_dma_tag_destroy(fl->ifl_desc_tag); 2153 fl->ifl_desc_tag = NULL; 2154 } 2155 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2156 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2157 /* XXX destroy maps first */ 2158 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2159 fl->ifl_sds.ifsd_m = NULL; 2160 fl->ifl_sds.ifsd_cl = NULL; 2161 fl->ifl_sds.ifsd_map = NULL; 2162 } 2163 free(rxq->ifr_fl, M_IFLIB); 2164 rxq->ifr_fl = NULL; 2165 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2166 } 2167 } 2168 2169 /* 2170 * MI independent logic 2171 * 2172 */ 2173 static void 2174 iflib_timer(void *arg) 2175 { 2176 iflib_txq_t txq = arg; 2177 if_ctx_t ctx = txq->ift_ctx; 2178 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2179 2180 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2181 return; 2182 /* 2183 ** Check on the state of the TX queue(s), this 2184 ** can be done without the lock because its RO 2185 ** and the HUNG state will be static if set. 2186 */ 2187 IFDI_TIMER(ctx, txq->ift_id); 2188 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2189 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2190 (sctx->isc_pause_frames == 0))) 2191 goto hung; 2192 2193 if (ifmp_ring_is_stalled(txq->ift_br)) 2194 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2195 txq->ift_cleaned_prev = txq->ift_cleaned; 2196 /* handle any laggards */ 2197 if (txq->ift_db_pending) 2198 GROUPTASK_ENQUEUE(&txq->ift_task); 2199 2200 sctx->isc_pause_frames = 0; 2201 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2202 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 2203 return; 2204 hung: 2205 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2206 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2207 STATE_LOCK(ctx); 2208 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2209 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2210 iflib_admin_intr_deferred(ctx); 2211 STATE_UNLOCK(ctx); 2212 } 2213 2214 static void 2215 iflib_init_locked(if_ctx_t ctx) 2216 { 2217 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2218 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2219 if_t ifp = ctx->ifc_ifp; 2220 iflib_fl_t fl; 2221 iflib_txq_t txq; 2222 iflib_rxq_t rxq; 2223 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2224 2225 2226 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2227 IFDI_INTR_DISABLE(ctx); 2228 2229 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2230 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2231 /* Set hardware offload abilities */ 2232 if_clearhwassist(ifp); 2233 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2234 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2235 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2236 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2237 if (if_getcapenable(ifp) & IFCAP_TSO4) 2238 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2239 if (if_getcapenable(ifp) & IFCAP_TSO6) 2240 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2241 2242 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2243 CALLOUT_LOCK(txq); 2244 callout_stop(&txq->ift_timer); 2245 CALLOUT_UNLOCK(txq); 2246 iflib_netmap_txq_init(ctx, txq); 2247 } 2248 #ifdef INVARIANTS 2249 i = if_getdrvflags(ifp); 2250 #endif 2251 IFDI_INIT(ctx); 2252 MPASS(if_getdrvflags(ifp) == i); 2253 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2254 /* XXX this should really be done on a per-queue basis */ 2255 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2256 MPASS(rxq->ifr_id == i); 2257 iflib_netmap_rxq_init(ctx, rxq); 2258 continue; 2259 } 2260 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2261 if (iflib_fl_setup(fl)) { 2262 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2263 goto done; 2264 } 2265 } 2266 } 2267 done: 2268 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2269 IFDI_INTR_ENABLE(ctx); 2270 txq = ctx->ifc_txqs; 2271 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2272 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2273 txq->ift_timer.c_cpu); 2274 } 2275 2276 static int 2277 iflib_media_change(if_t ifp) 2278 { 2279 if_ctx_t ctx = if_getsoftc(ifp); 2280 int err; 2281 2282 CTX_LOCK(ctx); 2283 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2284 iflib_init_locked(ctx); 2285 CTX_UNLOCK(ctx); 2286 return (err); 2287 } 2288 2289 static void 2290 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2291 { 2292 if_ctx_t ctx = if_getsoftc(ifp); 2293 2294 CTX_LOCK(ctx); 2295 IFDI_UPDATE_ADMIN_STATUS(ctx); 2296 IFDI_MEDIA_STATUS(ctx, ifmr); 2297 CTX_UNLOCK(ctx); 2298 } 2299 2300 void 2301 iflib_stop(if_ctx_t ctx) 2302 { 2303 iflib_txq_t txq = ctx->ifc_txqs; 2304 iflib_rxq_t rxq = ctx->ifc_rxqs; 2305 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2306 iflib_dma_info_t di; 2307 iflib_fl_t fl; 2308 int i, j; 2309 2310 /* Tell the stack that the interface is no longer active */ 2311 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2312 2313 IFDI_INTR_DISABLE(ctx); 2314 DELAY(1000); 2315 IFDI_STOP(ctx); 2316 DELAY(1000); 2317 2318 iflib_debug_reset(); 2319 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2320 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2321 /* make sure all transmitters have completed before proceeding XXX */ 2322 2323 CALLOUT_LOCK(txq); 2324 callout_stop(&txq->ift_timer); 2325 CALLOUT_UNLOCK(txq); 2326 2327 /* clean any enqueued buffers */ 2328 iflib_ifmp_purge(txq); 2329 /* Free any existing tx buffers. */ 2330 for (j = 0; j < txq->ift_size; j++) { 2331 iflib_txsd_free(ctx, txq, j); 2332 } 2333 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2334 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2335 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2336 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2337 txq->ift_pullups = 0; 2338 ifmp_ring_reset_stats(txq->ift_br); 2339 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2340 bzero((void *)di->idi_vaddr, di->idi_size); 2341 } 2342 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2343 /* make sure all transmitters have completed before proceeding XXX */ 2344 2345 for (j = 0, di = rxq->ifr_ifdi; j < rxq->ifr_nfl; j++, di++) 2346 bzero((void *)di->idi_vaddr, di->idi_size); 2347 /* also resets the free lists pidx/cidx */ 2348 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2349 iflib_fl_bufs_free(fl); 2350 } 2351 } 2352 2353 static inline caddr_t 2354 calc_next_rxd(iflib_fl_t fl, int cidx) 2355 { 2356 qidx_t size; 2357 int nrxd; 2358 caddr_t start, end, cur, next; 2359 2360 nrxd = fl->ifl_size; 2361 size = fl->ifl_rxd_size; 2362 start = fl->ifl_ifdi->idi_vaddr; 2363 2364 if (__predict_false(size == 0)) 2365 return (start); 2366 cur = start + size*cidx; 2367 end = start + size*nrxd; 2368 next = CACHE_PTR_NEXT(cur); 2369 return (next < end ? next : start); 2370 } 2371 2372 static inline void 2373 prefetch_pkts(iflib_fl_t fl, int cidx) 2374 { 2375 int nextptr; 2376 int nrxd = fl->ifl_size; 2377 caddr_t next_rxd; 2378 2379 2380 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2381 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2382 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2383 next_rxd = calc_next_rxd(fl, cidx); 2384 prefetch(next_rxd); 2385 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2386 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2387 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2388 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2389 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2390 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2391 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2392 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2393 } 2394 2395 static void 2396 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2397 { 2398 int flid, cidx; 2399 bus_dmamap_t map; 2400 iflib_fl_t fl; 2401 iflib_dma_info_t di; 2402 int next; 2403 2404 map = NULL; 2405 flid = irf->irf_flid; 2406 cidx = irf->irf_idx; 2407 fl = &rxq->ifr_fl[flid]; 2408 sd->ifsd_fl = fl; 2409 sd->ifsd_cidx = cidx; 2410 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2411 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2412 fl->ifl_credits--; 2413 #if MEMORY_LOGGING 2414 fl->ifl_m_dequeued++; 2415 #endif 2416 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2417 prefetch_pkts(fl, cidx); 2418 if (fl->ifl_sds.ifsd_map != NULL) { 2419 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2420 prefetch(&fl->ifl_sds.ifsd_map[next]); 2421 map = fl->ifl_sds.ifsd_map[cidx]; 2422 di = fl->ifl_ifdi; 2423 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2424 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2425 bus_dmamap_sync(di->idi_tag, di->idi_map, 2426 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2427 2428 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2429 MPASS(fl->ifl_cidx == cidx); 2430 if (unload) 2431 bus_dmamap_unload(fl->ifl_desc_tag, map); 2432 } 2433 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2434 if (__predict_false(fl->ifl_cidx == 0)) 2435 fl->ifl_gen = 0; 2436 if (map != NULL) 2437 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2438 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2439 bit_clear(fl->ifl_rx_bitmap, cidx); 2440 } 2441 2442 static struct mbuf * 2443 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2444 { 2445 int i, padlen , flags; 2446 struct mbuf *m, *mh, *mt; 2447 caddr_t cl; 2448 2449 i = 0; 2450 mh = NULL; 2451 do { 2452 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2453 2454 MPASS(*sd->ifsd_cl != NULL); 2455 MPASS(*sd->ifsd_m != NULL); 2456 2457 /* Don't include zero-length frags */ 2458 if (ri->iri_frags[i].irf_len == 0) { 2459 /* XXX we can save the cluster here, but not the mbuf */ 2460 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2461 m_free(*sd->ifsd_m); 2462 *sd->ifsd_m = NULL; 2463 continue; 2464 } 2465 m = *sd->ifsd_m; 2466 *sd->ifsd_m = NULL; 2467 if (mh == NULL) { 2468 flags = M_PKTHDR|M_EXT; 2469 mh = mt = m; 2470 padlen = ri->iri_pad; 2471 } else { 2472 flags = M_EXT; 2473 mt->m_next = m; 2474 mt = m; 2475 /* assuming padding is only on the first fragment */ 2476 padlen = 0; 2477 } 2478 cl = *sd->ifsd_cl; 2479 *sd->ifsd_cl = NULL; 2480 2481 /* Can these two be made one ? */ 2482 m_init(m, M_NOWAIT, MT_DATA, flags); 2483 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2484 /* 2485 * These must follow m_init and m_cljset 2486 */ 2487 m->m_data += padlen; 2488 ri->iri_len -= padlen; 2489 m->m_len = ri->iri_frags[i].irf_len; 2490 } while (++i < ri->iri_nfrags); 2491 2492 return (mh); 2493 } 2494 2495 /* 2496 * Process one software descriptor 2497 */ 2498 static struct mbuf * 2499 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2500 { 2501 struct if_rxsd sd; 2502 struct mbuf *m; 2503 2504 /* should I merge this back in now that the two paths are basically duplicated? */ 2505 if (ri->iri_nfrags == 1 && 2506 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2507 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2508 m = *sd.ifsd_m; 2509 *sd.ifsd_m = NULL; 2510 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2511 #ifndef __NO_STRICT_ALIGNMENT 2512 if (!IP_ALIGNED(m)) 2513 m->m_data += 2; 2514 #endif 2515 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2516 m->m_len = ri->iri_frags[0].irf_len; 2517 } else { 2518 m = assemble_segments(rxq, ri, &sd); 2519 } 2520 m->m_pkthdr.len = ri->iri_len; 2521 m->m_pkthdr.rcvif = ri->iri_ifp; 2522 m->m_flags |= ri->iri_flags; 2523 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2524 m->m_pkthdr.flowid = ri->iri_flowid; 2525 M_HASHTYPE_SET(m, ri->iri_rsstype); 2526 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2527 m->m_pkthdr.csum_data = ri->iri_csum_data; 2528 return (m); 2529 } 2530 2531 #if defined(INET6) || defined(INET) 2532 static void 2533 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2534 { 2535 CURVNET_SET(lc->ifp->if_vnet); 2536 #if defined(INET6) 2537 *v6 = VNET(ip6_forwarding); 2538 #endif 2539 #if defined(INET) 2540 *v4 = VNET(ipforwarding); 2541 #endif 2542 CURVNET_RESTORE(); 2543 } 2544 2545 /* 2546 * Returns true if it's possible this packet could be LROed. 2547 * if it returns false, it is guaranteed that tcp_lro_rx() 2548 * would not return zero. 2549 */ 2550 static bool 2551 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2552 { 2553 struct ether_header *eh; 2554 uint16_t eh_type; 2555 2556 eh = mtod(m, struct ether_header *); 2557 eh_type = ntohs(eh->ether_type); 2558 switch (eh_type) { 2559 #if defined(INET6) 2560 case ETHERTYPE_IPV6: 2561 return !v6_forwarding; 2562 #endif 2563 #if defined (INET) 2564 case ETHERTYPE_IP: 2565 return !v4_forwarding; 2566 #endif 2567 } 2568 2569 return false; 2570 } 2571 #else 2572 static void 2573 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2574 { 2575 } 2576 #endif 2577 2578 static bool 2579 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2580 { 2581 if_ctx_t ctx = rxq->ifr_ctx; 2582 if_shared_ctx_t sctx = ctx->ifc_sctx; 2583 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2584 int avail, i; 2585 qidx_t *cidxp; 2586 struct if_rxd_info ri; 2587 int err, budget_left, rx_bytes, rx_pkts; 2588 iflib_fl_t fl; 2589 struct ifnet *ifp; 2590 int lro_enabled; 2591 bool lro_possible = false; 2592 bool v4_forwarding, v6_forwarding; 2593 2594 /* 2595 * XXX early demux data packets so that if_input processing only handles 2596 * acks in interrupt context 2597 */ 2598 struct mbuf *m, *mh, *mt, *mf; 2599 2600 ifp = ctx->ifc_ifp; 2601 mh = mt = NULL; 2602 MPASS(budget > 0); 2603 rx_pkts = rx_bytes = 0; 2604 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2605 cidxp = &rxq->ifr_cq_cidx; 2606 else 2607 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2608 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2609 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2610 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2611 DBG_COUNTER_INC(rx_unavail); 2612 return (false); 2613 } 2614 2615 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2616 if (__predict_false(!CTX_ACTIVE(ctx))) { 2617 DBG_COUNTER_INC(rx_ctx_inactive); 2618 break; 2619 } 2620 /* 2621 * Reset client set fields to their default values 2622 */ 2623 rxd_info_zero(&ri); 2624 ri.iri_qsidx = rxq->ifr_id; 2625 ri.iri_cidx = *cidxp; 2626 ri.iri_ifp = ifp; 2627 ri.iri_frags = rxq->ifr_frags; 2628 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2629 2630 if (err) 2631 goto err; 2632 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2633 *cidxp = ri.iri_cidx; 2634 /* Update our consumer index */ 2635 /* XXX NB: shurd - check if this is still safe */ 2636 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2637 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2638 rxq->ifr_cq_gen = 0; 2639 } 2640 /* was this only a completion queue message? */ 2641 if (__predict_false(ri.iri_nfrags == 0)) 2642 continue; 2643 } 2644 MPASS(ri.iri_nfrags != 0); 2645 MPASS(ri.iri_len != 0); 2646 2647 /* will advance the cidx on the corresponding free lists */ 2648 m = iflib_rxd_pkt_get(rxq, &ri); 2649 if (avail == 0 && budget_left) 2650 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2651 2652 if (__predict_false(m == NULL)) { 2653 DBG_COUNTER_INC(rx_mbuf_null); 2654 continue; 2655 } 2656 /* imm_pkt: -- cxgb */ 2657 if (mh == NULL) 2658 mh = mt = m; 2659 else { 2660 mt->m_nextpkt = m; 2661 mt = m; 2662 } 2663 } 2664 /* make sure that we can refill faster than drain */ 2665 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2666 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2667 2668 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2669 if (lro_enabled) 2670 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2671 mt = mf = NULL; 2672 while (mh != NULL) { 2673 m = mh; 2674 mh = mh->m_nextpkt; 2675 m->m_nextpkt = NULL; 2676 #ifndef __NO_STRICT_ALIGNMENT 2677 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2678 continue; 2679 #endif 2680 rx_bytes += m->m_pkthdr.len; 2681 rx_pkts++; 2682 #if defined(INET6) || defined(INET) 2683 if (lro_enabled) { 2684 if (!lro_possible) { 2685 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2686 if (lro_possible && mf != NULL) { 2687 ifp->if_input(ifp, mf); 2688 DBG_COUNTER_INC(rx_if_input); 2689 mt = mf = NULL; 2690 } 2691 } 2692 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2693 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2694 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2695 continue; 2696 } 2697 } 2698 #endif 2699 if (lro_possible) { 2700 ifp->if_input(ifp, m); 2701 DBG_COUNTER_INC(rx_if_input); 2702 continue; 2703 } 2704 2705 if (mf == NULL) 2706 mf = m; 2707 if (mt != NULL) 2708 mt->m_nextpkt = m; 2709 mt = m; 2710 } 2711 if (mf != NULL) { 2712 ifp->if_input(ifp, mf); 2713 DBG_COUNTER_INC(rx_if_input); 2714 } 2715 2716 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2717 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2718 2719 /* 2720 * Flush any outstanding LRO work 2721 */ 2722 #if defined(INET6) || defined(INET) 2723 tcp_lro_flush_all(&rxq->ifr_lc); 2724 #endif 2725 if (avail) 2726 return true; 2727 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2728 err: 2729 STATE_LOCK(ctx); 2730 ctx->ifc_flags |= IFC_DO_RESET; 2731 iflib_admin_intr_deferred(ctx); 2732 STATE_UNLOCK(ctx); 2733 return (false); 2734 } 2735 2736 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2737 static inline qidx_t 2738 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2739 { 2740 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2741 qidx_t minthresh = txq->ift_size / 8; 2742 if (in_use > 4*minthresh) 2743 return (notify_count); 2744 if (in_use > 2*minthresh) 2745 return (notify_count >> 1); 2746 if (in_use > minthresh) 2747 return (notify_count >> 3); 2748 return (0); 2749 } 2750 2751 static inline qidx_t 2752 txq_max_rs_deferred(iflib_txq_t txq) 2753 { 2754 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2755 qidx_t minthresh = txq->ift_size / 8; 2756 if (txq->ift_in_use > 4*minthresh) 2757 return (notify_count); 2758 if (txq->ift_in_use > 2*minthresh) 2759 return (notify_count >> 1); 2760 if (txq->ift_in_use > minthresh) 2761 return (notify_count >> 2); 2762 return (2); 2763 } 2764 2765 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2766 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2767 2768 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2769 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2770 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2771 2772 /* forward compatibility for cxgb */ 2773 #define FIRST_QSET(ctx) 0 2774 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2775 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2776 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2777 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2778 2779 /* XXX we should be setting this to something other than zero */ 2780 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2781 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2782 2783 static inline bool 2784 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2785 { 2786 qidx_t dbval, max; 2787 bool rang; 2788 2789 rang = false; 2790 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2791 if (ring || txq->ift_db_pending >= max) { 2792 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2793 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2794 txq->ift_db_pending = txq->ift_npending = 0; 2795 rang = true; 2796 } 2797 return (rang); 2798 } 2799 2800 #ifdef PKT_DEBUG 2801 static void 2802 print_pkt(if_pkt_info_t pi) 2803 { 2804 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2805 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2806 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2807 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2808 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2809 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2810 } 2811 #endif 2812 2813 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2814 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2815 2816 static int 2817 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2818 { 2819 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2820 struct ether_vlan_header *eh; 2821 struct mbuf *m, *n; 2822 2823 n = m = *mp; 2824 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2825 M_WRITABLE(m) == 0) { 2826 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2827 return (ENOMEM); 2828 } else { 2829 m_freem(*mp); 2830 n = *mp = m; 2831 } 2832 } 2833 2834 /* 2835 * Determine where frame payload starts. 2836 * Jump over vlan headers if already present, 2837 * helpful for QinQ too. 2838 */ 2839 if (__predict_false(m->m_len < sizeof(*eh))) { 2840 txq->ift_pullups++; 2841 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2842 return (ENOMEM); 2843 } 2844 eh = mtod(m, struct ether_vlan_header *); 2845 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2846 pi->ipi_etype = ntohs(eh->evl_proto); 2847 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2848 } else { 2849 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2850 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2851 } 2852 2853 switch (pi->ipi_etype) { 2854 #ifdef INET 2855 case ETHERTYPE_IP: 2856 { 2857 struct ip *ip = NULL; 2858 struct tcphdr *th = NULL; 2859 int minthlen; 2860 2861 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2862 if (__predict_false(m->m_len < minthlen)) { 2863 /* 2864 * if this code bloat is causing too much of a hit 2865 * move it to a separate function and mark it noinline 2866 */ 2867 if (m->m_len == pi->ipi_ehdrlen) { 2868 n = m->m_next; 2869 MPASS(n); 2870 if (n->m_len >= sizeof(*ip)) { 2871 ip = (struct ip *)n->m_data; 2872 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2873 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2874 } else { 2875 txq->ift_pullups++; 2876 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2877 return (ENOMEM); 2878 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2879 } 2880 } else { 2881 txq->ift_pullups++; 2882 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2883 return (ENOMEM); 2884 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2885 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2886 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2887 } 2888 } else { 2889 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2890 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2891 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2892 } 2893 pi->ipi_ip_hlen = ip->ip_hl << 2; 2894 pi->ipi_ipproto = ip->ip_p; 2895 pi->ipi_flags |= IPI_TX_IPV4; 2896 2897 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 2898 ip->ip_sum = 0; 2899 2900 if (IS_TSO4(pi)) { 2901 if (pi->ipi_ipproto == IPPROTO_TCP) { 2902 if (__predict_false(th == NULL)) { 2903 txq->ift_pullups++; 2904 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2905 return (ENOMEM); 2906 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2907 } 2908 pi->ipi_tcp_hflags = th->th_flags; 2909 pi->ipi_tcp_hlen = th->th_off << 2; 2910 pi->ipi_tcp_seq = th->th_seq; 2911 } 2912 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2913 return (ENXIO); 2914 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2915 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2916 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2917 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2918 ip->ip_sum = 0; 2919 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2920 } 2921 } 2922 break; 2923 } 2924 #endif 2925 #ifdef INET6 2926 case ETHERTYPE_IPV6: 2927 { 2928 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2929 struct tcphdr *th; 2930 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2931 2932 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2933 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2934 return (ENOMEM); 2935 } 2936 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2937 2938 /* XXX-BZ this will go badly in case of ext hdrs. */ 2939 pi->ipi_ipproto = ip6->ip6_nxt; 2940 pi->ipi_flags |= IPI_TX_IPV6; 2941 2942 if (IS_TSO6(pi)) { 2943 if (pi->ipi_ipproto == IPPROTO_TCP) { 2944 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2945 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2946 return (ENOMEM); 2947 } 2948 pi->ipi_tcp_hflags = th->th_flags; 2949 pi->ipi_tcp_hlen = th->th_off << 2; 2950 } 2951 2952 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2953 return (ENXIO); 2954 /* 2955 * The corresponding flag is set by the stack in the IPv4 2956 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 2957 * So, set it here because the rest of the flow requires it. 2958 */ 2959 pi->ipi_csum_flags |= CSUM_TCP_IPV6; 2960 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2961 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2962 } 2963 break; 2964 } 2965 #endif 2966 default: 2967 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2968 pi->ipi_ip_hlen = 0; 2969 break; 2970 } 2971 *mp = m; 2972 2973 return (0); 2974 } 2975 2976 static __noinline struct mbuf * 2977 collapse_pkthdr(struct mbuf *m0) 2978 { 2979 struct mbuf *m, *m_next, *tmp; 2980 2981 m = m0; 2982 m_next = m->m_next; 2983 while (m_next != NULL && m_next->m_len == 0) { 2984 m = m_next; 2985 m->m_next = NULL; 2986 m_free(m); 2987 m_next = m_next->m_next; 2988 } 2989 m = m0; 2990 m->m_next = m_next; 2991 if ((m_next->m_flags & M_EXT) == 0) { 2992 m = m_defrag(m, M_NOWAIT); 2993 } else { 2994 tmp = m_next->m_next; 2995 memcpy(m_next, m, MPKTHSIZE); 2996 m = m_next; 2997 m->m_next = tmp; 2998 } 2999 return (m); 3000 } 3001 3002 /* 3003 * If dodgy hardware rejects the scatter gather chain we've handed it 3004 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3005 * m_defrag'd mbufs 3006 */ 3007 static __noinline struct mbuf * 3008 iflib_remove_mbuf(iflib_txq_t txq) 3009 { 3010 int ntxd, i, pidx; 3011 struct mbuf *m, *mh, **ifsd_m; 3012 3013 pidx = txq->ift_pidx; 3014 ifsd_m = txq->ift_sds.ifsd_m; 3015 ntxd = txq->ift_size; 3016 mh = m = ifsd_m[pidx]; 3017 ifsd_m[pidx] = NULL; 3018 #if MEMORY_LOGGING 3019 txq->ift_dequeued++; 3020 #endif 3021 i = 1; 3022 3023 while (m) { 3024 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 3025 #if MEMORY_LOGGING 3026 txq->ift_dequeued++; 3027 #endif 3028 m = m->m_next; 3029 i++; 3030 } 3031 return (mh); 3032 } 3033 3034 static int 3035 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 3036 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 3037 int max_segs, int flags) 3038 { 3039 if_ctx_t ctx; 3040 if_shared_ctx_t sctx; 3041 if_softc_ctx_t scctx; 3042 int i, next, pidx, err, ntxd, count; 3043 struct mbuf *m, *tmp, **ifsd_m; 3044 3045 m = *m0; 3046 3047 /* 3048 * Please don't ever do this 3049 */ 3050 if (__predict_false(m->m_len == 0)) 3051 *m0 = m = collapse_pkthdr(m); 3052 3053 ctx = txq->ift_ctx; 3054 sctx = ctx->ifc_sctx; 3055 scctx = &ctx->ifc_softc_ctx; 3056 ifsd_m = txq->ift_sds.ifsd_m; 3057 ntxd = txq->ift_size; 3058 pidx = txq->ift_pidx; 3059 if (map != NULL) { 3060 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 3061 3062 err = bus_dmamap_load_mbuf_sg(tag, map, 3063 *m0, segs, nsegs, BUS_DMA_NOWAIT); 3064 if (err) 3065 return (err); 3066 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 3067 count = 0; 3068 m = *m0; 3069 do { 3070 if (__predict_false(m->m_len <= 0)) { 3071 tmp = m; 3072 m = m->m_next; 3073 tmp->m_next = NULL; 3074 m_free(tmp); 3075 continue; 3076 } 3077 m = m->m_next; 3078 count++; 3079 } while (m != NULL); 3080 if (count > *nsegs) { 3081 ifsd_m[pidx] = *m0; 3082 ifsd_m[pidx]->m_flags |= M_TOOBIG; 3083 return (0); 3084 } 3085 m = *m0; 3086 count = 0; 3087 do { 3088 next = (pidx + count) & (ntxd-1); 3089 MPASS(ifsd_m[next] == NULL); 3090 ifsd_m[next] = m; 3091 count++; 3092 tmp = m; 3093 m = m->m_next; 3094 } while (m != NULL); 3095 } else { 3096 int buflen, sgsize, maxsegsz, max_sgsize; 3097 vm_offset_t vaddr; 3098 vm_paddr_t curaddr; 3099 3100 count = i = 0; 3101 m = *m0; 3102 if (m->m_pkthdr.csum_flags & CSUM_TSO) 3103 maxsegsz = scctx->isc_tx_tso_segsize_max; 3104 else 3105 maxsegsz = sctx->isc_tx_maxsegsize; 3106 3107 do { 3108 if (__predict_false(m->m_len <= 0)) { 3109 tmp = m; 3110 m = m->m_next; 3111 tmp->m_next = NULL; 3112 m_free(tmp); 3113 continue; 3114 } 3115 buflen = m->m_len; 3116 vaddr = (vm_offset_t)m->m_data; 3117 /* 3118 * see if we can't be smarter about physically 3119 * contiguous mappings 3120 */ 3121 next = (pidx + count) & (ntxd-1); 3122 MPASS(ifsd_m[next] == NULL); 3123 #if MEMORY_LOGGING 3124 txq->ift_enqueued++; 3125 #endif 3126 ifsd_m[next] = m; 3127 while (buflen > 0) { 3128 if (i >= max_segs) 3129 goto err; 3130 max_sgsize = MIN(buflen, maxsegsz); 3131 curaddr = pmap_kextract(vaddr); 3132 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 3133 sgsize = MIN(sgsize, max_sgsize); 3134 segs[i].ds_addr = curaddr; 3135 segs[i].ds_len = sgsize; 3136 vaddr += sgsize; 3137 buflen -= sgsize; 3138 i++; 3139 } 3140 count++; 3141 tmp = m; 3142 m = m->m_next; 3143 } while (m != NULL); 3144 *nsegs = i; 3145 } 3146 return (0); 3147 err: 3148 *m0 = iflib_remove_mbuf(txq); 3149 return (EFBIG); 3150 } 3151 3152 static inline caddr_t 3153 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3154 { 3155 qidx_t size; 3156 int ntxd; 3157 caddr_t start, end, cur, next; 3158 3159 ntxd = txq->ift_size; 3160 size = txq->ift_txd_size[qid]; 3161 start = txq->ift_ifdi[qid].idi_vaddr; 3162 3163 if (__predict_false(size == 0)) 3164 return (start); 3165 cur = start + size*cidx; 3166 end = start + size*ntxd; 3167 next = CACHE_PTR_NEXT(cur); 3168 return (next < end ? next : start); 3169 } 3170 3171 /* 3172 * Pad an mbuf to ensure a minimum ethernet frame size. 3173 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3174 */ 3175 static __noinline int 3176 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3177 { 3178 /* 3179 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3180 * and ARP message is the smallest common payload I can think of 3181 */ 3182 static char pad[18]; /* just zeros */ 3183 int n; 3184 struct mbuf *new_head; 3185 3186 if (!M_WRITABLE(*m_head)) { 3187 new_head = m_dup(*m_head, M_NOWAIT); 3188 if (new_head == NULL) { 3189 m_freem(*m_head); 3190 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3191 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3192 return ENOMEM; 3193 } 3194 m_freem(*m_head); 3195 *m_head = new_head; 3196 } 3197 3198 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3199 n > 0; n -= sizeof(pad)) 3200 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3201 break; 3202 3203 if (n > 0) { 3204 m_freem(*m_head); 3205 device_printf(dev, "cannot pad short frame\n"); 3206 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3207 return (ENOBUFS); 3208 } 3209 3210 return 0; 3211 } 3212 3213 static int 3214 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3215 { 3216 if_ctx_t ctx; 3217 if_shared_ctx_t sctx; 3218 if_softc_ctx_t scctx; 3219 bus_dma_segment_t *segs; 3220 struct mbuf *m_head; 3221 void *next_txd; 3222 bus_dmamap_t map; 3223 struct if_pkt_info pi; 3224 int remap = 0; 3225 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3226 bus_dma_tag_t desc_tag; 3227 3228 segs = txq->ift_segs; 3229 ctx = txq->ift_ctx; 3230 sctx = ctx->ifc_sctx; 3231 scctx = &ctx->ifc_softc_ctx; 3232 segs = txq->ift_segs; 3233 ntxd = txq->ift_size; 3234 m_head = *m_headp; 3235 map = NULL; 3236 3237 /* 3238 * If we're doing TSO the next descriptor to clean may be quite far ahead 3239 */ 3240 cidx = txq->ift_cidx; 3241 pidx = txq->ift_pidx; 3242 if (ctx->ifc_flags & IFC_PREFETCH) { 3243 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3244 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3245 next_txd = calc_next_txd(txq, cidx, 0); 3246 prefetch(next_txd); 3247 } 3248 3249 /* prefetch the next cache line of mbuf pointers and flags */ 3250 prefetch(&txq->ift_sds.ifsd_m[next]); 3251 if (txq->ift_sds.ifsd_map != NULL) { 3252 prefetch(&txq->ift_sds.ifsd_map[next]); 3253 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3254 prefetch(&txq->ift_sds.ifsd_flags[next]); 3255 } 3256 } else if (txq->ift_sds.ifsd_map != NULL) 3257 map = txq->ift_sds.ifsd_map[pidx]; 3258 3259 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3260 desc_tag = txq->ift_tso_desc_tag; 3261 max_segs = scctx->isc_tx_tso_segments_max; 3262 } else { 3263 desc_tag = txq->ift_desc_tag; 3264 max_segs = scctx->isc_tx_nsegments; 3265 } 3266 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3267 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3268 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3269 if (err) 3270 return err; 3271 } 3272 m_head = *m_headp; 3273 3274 pkt_info_zero(&pi); 3275 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3276 pi.ipi_pidx = pidx; 3277 pi.ipi_qsidx = txq->ift_id; 3278 pi.ipi_len = m_head->m_pkthdr.len; 3279 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3280 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3281 3282 /* deliberate bitwise OR to make one condition */ 3283 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3284 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3285 return (err); 3286 m_head = *m_headp; 3287 } 3288 3289 retry: 3290 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3291 defrag: 3292 if (__predict_false(err)) { 3293 switch (err) { 3294 case EFBIG: 3295 /* try collapse once and defrag once */ 3296 if (remap == 0) { 3297 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3298 /* try defrag if collapsing fails */ 3299 if (m_head == NULL) 3300 remap++; 3301 } 3302 if (remap == 1) 3303 m_head = m_defrag(*m_headp, M_NOWAIT); 3304 remap++; 3305 if (__predict_false(m_head == NULL)) 3306 goto defrag_failed; 3307 txq->ift_mbuf_defrag++; 3308 *m_headp = m_head; 3309 goto retry; 3310 break; 3311 case ENOMEM: 3312 txq->ift_no_tx_dma_setup++; 3313 break; 3314 default: 3315 txq->ift_no_tx_dma_setup++; 3316 m_freem(*m_headp); 3317 DBG_COUNTER_INC(tx_frees); 3318 *m_headp = NULL; 3319 break; 3320 } 3321 txq->ift_map_failed++; 3322 DBG_COUNTER_INC(encap_load_mbuf_fail); 3323 return (err); 3324 } 3325 3326 /* 3327 * XXX assumes a 1 to 1 relationship between segments and 3328 * descriptors - this does not hold true on all drivers, e.g. 3329 * cxgb 3330 */ 3331 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3332 txq->ift_no_desc_avail++; 3333 if (map != NULL) 3334 bus_dmamap_unload(desc_tag, map); 3335 DBG_COUNTER_INC(encap_txq_avail_fail); 3336 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3337 GROUPTASK_ENQUEUE(&txq->ift_task); 3338 return (ENOBUFS); 3339 } 3340 /* 3341 * On Intel cards we can greatly reduce the number of TX interrupts 3342 * we see by only setting report status on every Nth descriptor. 3343 * However, this also means that the driver will need to keep track 3344 * of the descriptors that RS was set on to check them for the DD bit. 3345 */ 3346 txq->ift_rs_pending += nsegs + 1; 3347 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3348 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3349 pi.ipi_flags |= IPI_TX_INTR; 3350 txq->ift_rs_pending = 0; 3351 } 3352 3353 pi.ipi_segs = segs; 3354 pi.ipi_nsegs = nsegs; 3355 3356 MPASS(pidx >= 0 && pidx < txq->ift_size); 3357 #ifdef PKT_DEBUG 3358 print_pkt(&pi); 3359 #endif 3360 if (map != NULL) 3361 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3362 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3363 if (map != NULL) 3364 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3365 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3366 DBG_COUNTER_INC(tx_encap); 3367 MPASS(pi.ipi_new_pidx < txq->ift_size); 3368 3369 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3370 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3371 ndesc += txq->ift_size; 3372 txq->ift_gen = 1; 3373 } 3374 /* 3375 * drivers can need as many as 3376 * two sentinels 3377 */ 3378 MPASS(ndesc <= pi.ipi_nsegs + 2); 3379 MPASS(pi.ipi_new_pidx != pidx); 3380 MPASS(ndesc > 0); 3381 txq->ift_in_use += ndesc; 3382 3383 /* 3384 * We update the last software descriptor again here because there may 3385 * be a sentinel and/or there may be more mbufs than segments 3386 */ 3387 txq->ift_pidx = pi.ipi_new_pidx; 3388 txq->ift_npending += pi.ipi_ndescs; 3389 } else { 3390 *m_headp = m_head = iflib_remove_mbuf(txq); 3391 if (err == EFBIG) { 3392 txq->ift_txd_encap_efbig++; 3393 if (remap < 2) { 3394 remap = 1; 3395 goto defrag; 3396 } 3397 } 3398 DBG_COUNTER_INC(encap_txd_encap_fail); 3399 goto defrag_failed; 3400 } 3401 return (err); 3402 3403 defrag_failed: 3404 txq->ift_mbuf_defrag_failed++; 3405 txq->ift_map_failed++; 3406 m_freem(*m_headp); 3407 DBG_COUNTER_INC(tx_frees); 3408 *m_headp = NULL; 3409 return (ENOMEM); 3410 } 3411 3412 static void 3413 iflib_tx_desc_free(iflib_txq_t txq, int n) 3414 { 3415 int hasmap; 3416 uint32_t qsize, cidx, mask, gen; 3417 struct mbuf *m, **ifsd_m; 3418 uint8_t *ifsd_flags; 3419 bus_dmamap_t *ifsd_map; 3420 bool do_prefetch; 3421 3422 cidx = txq->ift_cidx; 3423 gen = txq->ift_gen; 3424 qsize = txq->ift_size; 3425 mask = qsize-1; 3426 hasmap = txq->ift_sds.ifsd_map != NULL; 3427 ifsd_flags = txq->ift_sds.ifsd_flags; 3428 ifsd_m = txq->ift_sds.ifsd_m; 3429 ifsd_map = txq->ift_sds.ifsd_map; 3430 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3431 3432 while (n-- > 0) { 3433 if (do_prefetch) { 3434 prefetch(ifsd_m[(cidx + 3) & mask]); 3435 prefetch(ifsd_m[(cidx + 4) & mask]); 3436 } 3437 if (ifsd_m[cidx] != NULL) { 3438 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3439 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3440 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3441 /* 3442 * does it matter if it's not the TSO tag? If so we'll 3443 * have to add the type to flags 3444 */ 3445 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3446 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3447 } 3448 if ((m = ifsd_m[cidx]) != NULL) { 3449 /* XXX we don't support any drivers that batch packets yet */ 3450 MPASS(m->m_nextpkt == NULL); 3451 /* if the number of clusters exceeds the number of segments 3452 * there won't be space on the ring to save a pointer to each 3453 * cluster so we simply free the list here 3454 */ 3455 if (m->m_flags & M_TOOBIG) { 3456 m_freem(m); 3457 } else { 3458 m_free(m); 3459 } 3460 ifsd_m[cidx] = NULL; 3461 #if MEMORY_LOGGING 3462 txq->ift_dequeued++; 3463 #endif 3464 DBG_COUNTER_INC(tx_frees); 3465 } 3466 } 3467 if (__predict_false(++cidx == qsize)) { 3468 cidx = 0; 3469 gen = 0; 3470 } 3471 } 3472 txq->ift_cidx = cidx; 3473 txq->ift_gen = gen; 3474 } 3475 3476 static __inline int 3477 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3478 { 3479 int reclaim; 3480 if_ctx_t ctx = txq->ift_ctx; 3481 3482 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3483 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3484 3485 /* 3486 * Need a rate-limiting check so that this isn't called every time 3487 */ 3488 iflib_tx_credits_update(ctx, txq); 3489 reclaim = DESC_RECLAIMABLE(txq); 3490 3491 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3492 #ifdef INVARIANTS 3493 if (iflib_verbose_debug) { 3494 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3495 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3496 reclaim, thresh); 3497 3498 } 3499 #endif 3500 return (0); 3501 } 3502 iflib_tx_desc_free(txq, reclaim); 3503 txq->ift_cleaned += reclaim; 3504 txq->ift_in_use -= reclaim; 3505 3506 return (reclaim); 3507 } 3508 3509 static struct mbuf ** 3510 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3511 { 3512 int next, size; 3513 struct mbuf **items; 3514 3515 size = r->size; 3516 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3517 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3518 3519 prefetch(items[(cidx + offset) & (size-1)]); 3520 if (remaining > 1) { 3521 prefetch2cachelines(&items[next]); 3522 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3523 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3524 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3525 } 3526 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3527 } 3528 3529 static void 3530 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3531 { 3532 3533 ifmp_ring_check_drainage(txq->ift_br, budget); 3534 } 3535 3536 static uint32_t 3537 iflib_txq_can_drain(struct ifmp_ring *r) 3538 { 3539 iflib_txq_t txq = r->cookie; 3540 if_ctx_t ctx = txq->ift_ctx; 3541 3542 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3543 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3544 } 3545 3546 static uint32_t 3547 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3548 { 3549 iflib_txq_t txq = r->cookie; 3550 if_ctx_t ctx = txq->ift_ctx; 3551 struct ifnet *ifp = ctx->ifc_ifp; 3552 struct mbuf **mp, *m; 3553 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3554 int reclaimed, err, in_use_prev, desc_used; 3555 bool do_prefetch, ring, rang; 3556 3557 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3558 !LINK_ACTIVE(ctx))) { 3559 DBG_COUNTER_INC(txq_drain_notready); 3560 return (0); 3561 } 3562 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3563 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3564 avail = IDXDIFF(pidx, cidx, r->size); 3565 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3566 DBG_COUNTER_INC(txq_drain_flushing); 3567 for (i = 0; i < avail; i++) { 3568 m_free(r->items[(cidx + i) & (r->size-1)]); 3569 r->items[(cidx + i) & (r->size-1)] = NULL; 3570 } 3571 return (avail); 3572 } 3573 3574 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3575 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3576 CALLOUT_LOCK(txq); 3577 callout_stop(&txq->ift_timer); 3578 CALLOUT_UNLOCK(txq); 3579 DBG_COUNTER_INC(txq_drain_oactive); 3580 return (0); 3581 } 3582 if (reclaimed) 3583 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3584 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3585 count = MIN(avail, TX_BATCH_SIZE); 3586 #ifdef INVARIANTS 3587 if (iflib_verbose_debug) 3588 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3589 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3590 #endif 3591 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3592 avail = TXQ_AVAIL(txq); 3593 err = 0; 3594 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3595 int rem = do_prefetch ? count - i : 0; 3596 3597 mp = _ring_peek_one(r, cidx, i, rem); 3598 MPASS(mp != NULL && *mp != NULL); 3599 if (__predict_false(*mp == (struct mbuf *)txq)) { 3600 consumed++; 3601 reclaimed++; 3602 continue; 3603 } 3604 in_use_prev = txq->ift_in_use; 3605 err = iflib_encap(txq, mp); 3606 if (__predict_false(err)) { 3607 DBG_COUNTER_INC(txq_drain_encapfail); 3608 /* no room - bail out */ 3609 if (err == ENOBUFS) 3610 break; 3611 consumed++; 3612 DBG_COUNTER_INC(txq_drain_encapfail); 3613 /* we can't send this packet - skip it */ 3614 continue; 3615 } 3616 consumed++; 3617 pkt_sent++; 3618 m = *mp; 3619 DBG_COUNTER_INC(tx_sent); 3620 bytes_sent += m->m_pkthdr.len; 3621 mcast_sent += !!(m->m_flags & M_MCAST); 3622 avail = TXQ_AVAIL(txq); 3623 3624 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3625 desc_used += (txq->ift_in_use - in_use_prev); 3626 ETHER_BPF_MTAP(ifp, m); 3627 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3628 break; 3629 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3630 } 3631 3632 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3633 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3634 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3635 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3636 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3637 if (mcast_sent) 3638 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3639 #ifdef INVARIANTS 3640 if (iflib_verbose_debug) 3641 printf("consumed=%d\n", consumed); 3642 #endif 3643 return (consumed); 3644 } 3645 3646 static uint32_t 3647 iflib_txq_drain_always(struct ifmp_ring *r) 3648 { 3649 return (1); 3650 } 3651 3652 static uint32_t 3653 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3654 { 3655 int i, avail; 3656 struct mbuf **mp; 3657 iflib_txq_t txq; 3658 3659 txq = r->cookie; 3660 3661 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3662 CALLOUT_LOCK(txq); 3663 callout_stop(&txq->ift_timer); 3664 CALLOUT_UNLOCK(txq); 3665 3666 avail = IDXDIFF(pidx, cidx, r->size); 3667 for (i = 0; i < avail; i++) { 3668 mp = _ring_peek_one(r, cidx, i, avail - i); 3669 if (__predict_false(*mp == (struct mbuf *)txq)) 3670 continue; 3671 m_freem(*mp); 3672 } 3673 MPASS(ifmp_ring_is_stalled(r) == 0); 3674 return (avail); 3675 } 3676 3677 static void 3678 iflib_ifmp_purge(iflib_txq_t txq) 3679 { 3680 struct ifmp_ring *r; 3681 3682 r = txq->ift_br; 3683 r->drain = iflib_txq_drain_free; 3684 r->can_drain = iflib_txq_drain_always; 3685 3686 ifmp_ring_check_drainage(r, r->size); 3687 3688 r->drain = iflib_txq_drain; 3689 r->can_drain = iflib_txq_can_drain; 3690 } 3691 3692 static void 3693 _task_fn_tx(void *context) 3694 { 3695 iflib_txq_t txq = context; 3696 if_ctx_t ctx = txq->ift_ctx; 3697 struct ifnet *ifp = ctx->ifc_ifp; 3698 3699 #ifdef IFLIB_DIAGNOSTICS 3700 txq->ift_cpu_exec_count[curcpu]++; 3701 #endif 3702 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3703 return; 3704 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3705 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3706 netmap_tx_irq(ifp, txq->ift_id); 3707 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3708 return; 3709 } 3710 if (txq->ift_db_pending) 3711 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); 3712 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3713 if (ctx->ifc_flags & IFC_LEGACY) 3714 IFDI_INTR_ENABLE(ctx); 3715 else { 3716 #ifdef INVARIANTS 3717 int rc = 3718 #endif 3719 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3720 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3721 } 3722 } 3723 3724 static void 3725 _task_fn_rx(void *context) 3726 { 3727 iflib_rxq_t rxq = context; 3728 if_ctx_t ctx = rxq->ifr_ctx; 3729 bool more; 3730 uint16_t budget; 3731 3732 #ifdef IFLIB_DIAGNOSTICS 3733 rxq->ifr_cpu_exec_count[curcpu]++; 3734 #endif 3735 DBG_COUNTER_INC(task_fn_rxs); 3736 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3737 return; 3738 more = true; 3739 #ifdef DEV_NETMAP 3740 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3741 u_int work = 0; 3742 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3743 more = false; 3744 } 3745 } 3746 #endif 3747 budget = ctx->ifc_sysctl_rx_budget; 3748 if (budget == 0) 3749 budget = 16; /* XXX */ 3750 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3751 if (ctx->ifc_flags & IFC_LEGACY) 3752 IFDI_INTR_ENABLE(ctx); 3753 else { 3754 #ifdef INVARIANTS 3755 int rc = 3756 #endif 3757 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3758 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3759 DBG_COUNTER_INC(rx_intr_enables); 3760 } 3761 } 3762 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3763 return; 3764 if (more) 3765 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3766 } 3767 3768 static void 3769 _task_fn_admin(void *context) 3770 { 3771 if_ctx_t ctx = context; 3772 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3773 iflib_txq_t txq; 3774 int i; 3775 bool oactive, running, do_reset, do_watchdog; 3776 3777 STATE_LOCK(ctx); 3778 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3779 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3780 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3781 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3782 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3783 STATE_UNLOCK(ctx); 3784 3785 if (!running & !oactive) 3786 return; 3787 3788 CTX_LOCK(ctx); 3789 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3790 CALLOUT_LOCK(txq); 3791 callout_stop(&txq->ift_timer); 3792 CALLOUT_UNLOCK(txq); 3793 } 3794 if (do_watchdog) { 3795 ctx->ifc_watchdog_events++; 3796 IFDI_WATCHDOG_RESET(ctx); 3797 } 3798 IFDI_UPDATE_ADMIN_STATUS(ctx); 3799 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3800 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 3801 IFDI_LINK_INTR_ENABLE(ctx); 3802 if (do_reset) 3803 iflib_if_init_locked(ctx); 3804 CTX_UNLOCK(ctx); 3805 3806 if (LINK_ACTIVE(ctx) == 0) 3807 return; 3808 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3809 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3810 } 3811 3812 3813 static void 3814 _task_fn_iov(void *context) 3815 { 3816 if_ctx_t ctx = context; 3817 3818 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3819 return; 3820 3821 CTX_LOCK(ctx); 3822 IFDI_VFLR_HANDLE(ctx); 3823 CTX_UNLOCK(ctx); 3824 } 3825 3826 static int 3827 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3828 { 3829 int err; 3830 if_int_delay_info_t info; 3831 if_ctx_t ctx; 3832 3833 info = (if_int_delay_info_t)arg1; 3834 ctx = info->iidi_ctx; 3835 info->iidi_req = req; 3836 info->iidi_oidp = oidp; 3837 CTX_LOCK(ctx); 3838 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3839 CTX_UNLOCK(ctx); 3840 return (err); 3841 } 3842 3843 /********************************************************************* 3844 * 3845 * IFNET FUNCTIONS 3846 * 3847 **********************************************************************/ 3848 3849 static void 3850 iflib_if_init_locked(if_ctx_t ctx) 3851 { 3852 iflib_stop(ctx); 3853 iflib_init_locked(ctx); 3854 } 3855 3856 3857 static void 3858 iflib_if_init(void *arg) 3859 { 3860 if_ctx_t ctx = arg; 3861 3862 CTX_LOCK(ctx); 3863 iflib_if_init_locked(ctx); 3864 CTX_UNLOCK(ctx); 3865 } 3866 3867 static int 3868 iflib_if_transmit(if_t ifp, struct mbuf *m) 3869 { 3870 if_ctx_t ctx = if_getsoftc(ifp); 3871 3872 iflib_txq_t txq; 3873 int err, qidx; 3874 3875 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3876 DBG_COUNTER_INC(tx_frees); 3877 m_freem(m); 3878 return (ENOBUFS); 3879 } 3880 3881 MPASS(m->m_nextpkt == NULL); 3882 qidx = 0; 3883 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3884 qidx = QIDX(ctx, m); 3885 /* 3886 * XXX calculate buf_ring based on flowid (divvy up bits?) 3887 */ 3888 txq = &ctx->ifc_txqs[qidx]; 3889 3890 #ifdef DRIVER_BACKPRESSURE 3891 if (txq->ift_closed) { 3892 while (m != NULL) { 3893 next = m->m_nextpkt; 3894 m->m_nextpkt = NULL; 3895 m_freem(m); 3896 m = next; 3897 } 3898 return (ENOBUFS); 3899 } 3900 #endif 3901 #ifdef notyet 3902 qidx = count = 0; 3903 mp = marr; 3904 next = m; 3905 do { 3906 count++; 3907 next = next->m_nextpkt; 3908 } while (next != NULL); 3909 3910 if (count > nitems(marr)) 3911 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3912 /* XXX check nextpkt */ 3913 m_freem(m); 3914 /* XXX simplify for now */ 3915 DBG_COUNTER_INC(tx_frees); 3916 return (ENOBUFS); 3917 } 3918 for (next = m, i = 0; next != NULL; i++) { 3919 mp[i] = next; 3920 next = next->m_nextpkt; 3921 mp[i]->m_nextpkt = NULL; 3922 } 3923 #endif 3924 DBG_COUNTER_INC(tx_seen); 3925 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); 3926 3927 GROUPTASK_ENQUEUE(&txq->ift_task); 3928 if (err) { 3929 /* support forthcoming later */ 3930 #ifdef DRIVER_BACKPRESSURE 3931 txq->ift_closed = TRUE; 3932 #endif 3933 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3934 m_freem(m); 3935 } 3936 3937 return (err); 3938 } 3939 3940 static void 3941 iflib_if_qflush(if_t ifp) 3942 { 3943 if_ctx_t ctx = if_getsoftc(ifp); 3944 iflib_txq_t txq = ctx->ifc_txqs; 3945 int i; 3946 3947 STATE_LOCK(ctx); 3948 ctx->ifc_flags |= IFC_QFLUSH; 3949 STATE_UNLOCK(ctx); 3950 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3951 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3952 iflib_txq_check_drain(txq, 0); 3953 STATE_LOCK(ctx); 3954 ctx->ifc_flags &= ~IFC_QFLUSH; 3955 STATE_UNLOCK(ctx); 3956 3957 if_qflush(ifp); 3958 } 3959 3960 3961 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3962 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 3963 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 3964 3965 static int 3966 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 3967 { 3968 if_ctx_t ctx = if_getsoftc(ifp); 3969 struct ifreq *ifr = (struct ifreq *)data; 3970 #if defined(INET) || defined(INET6) 3971 struct ifaddr *ifa = (struct ifaddr *)data; 3972 #endif 3973 bool avoid_reset = FALSE; 3974 int err = 0, reinit = 0, bits; 3975 3976 switch (command) { 3977 case SIOCSIFADDR: 3978 #ifdef INET 3979 if (ifa->ifa_addr->sa_family == AF_INET) 3980 avoid_reset = TRUE; 3981 #endif 3982 #ifdef INET6 3983 if (ifa->ifa_addr->sa_family == AF_INET6) 3984 avoid_reset = TRUE; 3985 #endif 3986 /* 3987 ** Calling init results in link renegotiation, 3988 ** so we avoid doing it when possible. 3989 */ 3990 if (avoid_reset) { 3991 if_setflagbits(ifp, IFF_UP,0); 3992 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING)) 3993 reinit = 1; 3994 #ifdef INET 3995 if (!(if_getflags(ifp) & IFF_NOARP)) 3996 arp_ifinit(ifp, ifa); 3997 #endif 3998 } else 3999 err = ether_ioctl(ifp, command, data); 4000 break; 4001 case SIOCSIFMTU: 4002 CTX_LOCK(ctx); 4003 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4004 CTX_UNLOCK(ctx); 4005 break; 4006 } 4007 bits = if_getdrvflags(ifp); 4008 /* stop the driver and free any clusters before proceeding */ 4009 iflib_stop(ctx); 4010 4011 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4012 STATE_LOCK(ctx); 4013 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4014 ctx->ifc_flags |= IFC_MULTISEG; 4015 else 4016 ctx->ifc_flags &= ~IFC_MULTISEG; 4017 STATE_UNLOCK(ctx); 4018 err = if_setmtu(ifp, ifr->ifr_mtu); 4019 } 4020 iflib_init_locked(ctx); 4021 STATE_LOCK(ctx); 4022 if_setdrvflags(ifp, bits); 4023 STATE_UNLOCK(ctx); 4024 CTX_UNLOCK(ctx); 4025 break; 4026 case SIOCSIFFLAGS: 4027 CTX_LOCK(ctx); 4028 if (if_getflags(ifp) & IFF_UP) { 4029 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4030 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4031 (IFF_PROMISC | IFF_ALLMULTI)) { 4032 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4033 } 4034 } else 4035 reinit = 1; 4036 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4037 iflib_stop(ctx); 4038 } 4039 ctx->ifc_if_flags = if_getflags(ifp); 4040 CTX_UNLOCK(ctx); 4041 break; 4042 case SIOCADDMULTI: 4043 case SIOCDELMULTI: 4044 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4045 CTX_LOCK(ctx); 4046 IFDI_INTR_DISABLE(ctx); 4047 IFDI_MULTI_SET(ctx); 4048 IFDI_INTR_ENABLE(ctx); 4049 CTX_UNLOCK(ctx); 4050 } 4051 break; 4052 case SIOCSIFMEDIA: 4053 CTX_LOCK(ctx); 4054 IFDI_MEDIA_SET(ctx); 4055 CTX_UNLOCK(ctx); 4056 /* falls thru */ 4057 case SIOCGIFMEDIA: 4058 case SIOCGIFXMEDIA: 4059 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 4060 break; 4061 case SIOCGI2C: 4062 { 4063 struct ifi2creq i2c; 4064 4065 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4066 if (err != 0) 4067 break; 4068 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4069 err = EINVAL; 4070 break; 4071 } 4072 if (i2c.len > sizeof(i2c.data)) { 4073 err = EINVAL; 4074 break; 4075 } 4076 4077 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4078 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4079 sizeof(i2c)); 4080 break; 4081 } 4082 case SIOCSIFCAP: 4083 { 4084 int mask, setmask; 4085 4086 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 4087 setmask = 0; 4088 #ifdef TCP_OFFLOAD 4089 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4090 #endif 4091 setmask |= (mask & IFCAP_FLAGS); 4092 4093 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 4094 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4095 if ((mask & IFCAP_WOL) && 4096 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 4097 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 4098 if_vlancap(ifp); 4099 /* 4100 * want to ensure that traffic has stopped before we change any of the flags 4101 */ 4102 if (setmask) { 4103 CTX_LOCK(ctx); 4104 bits = if_getdrvflags(ifp); 4105 if (bits & IFF_DRV_RUNNING) 4106 iflib_stop(ctx); 4107 STATE_LOCK(ctx); 4108 if_togglecapenable(ifp, setmask); 4109 STATE_UNLOCK(ctx); 4110 if (bits & IFF_DRV_RUNNING) 4111 iflib_init_locked(ctx); 4112 STATE_LOCK(ctx); 4113 if_setdrvflags(ifp, bits); 4114 STATE_UNLOCK(ctx); 4115 CTX_UNLOCK(ctx); 4116 } 4117 break; 4118 } 4119 case SIOCGPRIVATE_0: 4120 case SIOCSDRVSPEC: 4121 case SIOCGDRVSPEC: 4122 CTX_LOCK(ctx); 4123 err = IFDI_PRIV_IOCTL(ctx, command, data); 4124 CTX_UNLOCK(ctx); 4125 break; 4126 default: 4127 err = ether_ioctl(ifp, command, data); 4128 break; 4129 } 4130 if (reinit) 4131 iflib_if_init(ctx); 4132 return (err); 4133 } 4134 4135 static uint64_t 4136 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4137 { 4138 if_ctx_t ctx = if_getsoftc(ifp); 4139 4140 return (IFDI_GET_COUNTER(ctx, cnt)); 4141 } 4142 4143 /********************************************************************* 4144 * 4145 * OTHER FUNCTIONS EXPORTED TO THE STACK 4146 * 4147 **********************************************************************/ 4148 4149 static void 4150 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4151 { 4152 if_ctx_t ctx = if_getsoftc(ifp); 4153 4154 if ((void *)ctx != arg) 4155 return; 4156 4157 if ((vtag == 0) || (vtag > 4095)) 4158 return; 4159 4160 CTX_LOCK(ctx); 4161 IFDI_VLAN_REGISTER(ctx, vtag); 4162 /* Re-init to load the changes */ 4163 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4164 iflib_if_init_locked(ctx); 4165 CTX_UNLOCK(ctx); 4166 } 4167 4168 static void 4169 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4170 { 4171 if_ctx_t ctx = if_getsoftc(ifp); 4172 4173 if ((void *)ctx != arg) 4174 return; 4175 4176 if ((vtag == 0) || (vtag > 4095)) 4177 return; 4178 4179 CTX_LOCK(ctx); 4180 IFDI_VLAN_UNREGISTER(ctx, vtag); 4181 /* Re-init to load the changes */ 4182 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4183 iflib_if_init_locked(ctx); 4184 CTX_UNLOCK(ctx); 4185 } 4186 4187 static void 4188 iflib_led_func(void *arg, int onoff) 4189 { 4190 if_ctx_t ctx = arg; 4191 4192 CTX_LOCK(ctx); 4193 IFDI_LED_FUNC(ctx, onoff); 4194 CTX_UNLOCK(ctx); 4195 } 4196 4197 /********************************************************************* 4198 * 4199 * BUS FUNCTION DEFINITIONS 4200 * 4201 **********************************************************************/ 4202 4203 int 4204 iflib_device_probe(device_t dev) 4205 { 4206 pci_vendor_info_t *ent; 4207 4208 uint16_t pci_vendor_id, pci_device_id; 4209 uint16_t pci_subvendor_id, pci_subdevice_id; 4210 uint16_t pci_rev_id; 4211 if_shared_ctx_t sctx; 4212 4213 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4214 return (ENOTSUP); 4215 4216 pci_vendor_id = pci_get_vendor(dev); 4217 pci_device_id = pci_get_device(dev); 4218 pci_subvendor_id = pci_get_subvendor(dev); 4219 pci_subdevice_id = pci_get_subdevice(dev); 4220 pci_rev_id = pci_get_revid(dev); 4221 if (sctx->isc_parse_devinfo != NULL) 4222 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4223 4224 ent = sctx->isc_vendor_info; 4225 while (ent->pvi_vendor_id != 0) { 4226 if (pci_vendor_id != ent->pvi_vendor_id) { 4227 ent++; 4228 continue; 4229 } 4230 if ((pci_device_id == ent->pvi_device_id) && 4231 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4232 (ent->pvi_subvendor_id == 0)) && 4233 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4234 (ent->pvi_subdevice_id == 0)) && 4235 ((pci_rev_id == ent->pvi_rev_id) || 4236 (ent->pvi_rev_id == 0))) { 4237 4238 device_set_desc_copy(dev, ent->pvi_name); 4239 /* this needs to be changed to zero if the bus probing code 4240 * ever stops re-probing on best match because the sctx 4241 * may have its values over written by register calls 4242 * in subsequent probes 4243 */ 4244 return (BUS_PROBE_DEFAULT); 4245 } 4246 ent++; 4247 } 4248 return (ENXIO); 4249 } 4250 4251 static void 4252 iflib_reset_qvalues(if_ctx_t ctx) 4253 { 4254 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4255 if_shared_ctx_t sctx = ctx->ifc_sctx; 4256 device_t dev = ctx->ifc_dev; 4257 int i, main_txq, main_rxq; 4258 4259 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4260 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4261 4262 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES; 4263 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH; 4264 /* 4265 * XXX sanity check that ntxd & nrxd are a power of 2 4266 */ 4267 if (ctx->ifc_sysctl_ntxqs != 0) 4268 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4269 if (ctx->ifc_sysctl_nrxqs != 0) 4270 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4271 4272 for (i = 0; i < sctx->isc_ntxqs; i++) { 4273 if (ctx->ifc_sysctl_ntxds[i] != 0) 4274 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4275 else 4276 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4277 } 4278 4279 for (i = 0; i < sctx->isc_nrxqs; i++) { 4280 if (ctx->ifc_sysctl_nrxds[i] != 0) 4281 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4282 else 4283 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4284 } 4285 4286 for (i = 0; i < sctx->isc_nrxqs; i++) { 4287 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4288 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4289 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4290 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4291 } 4292 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4293 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4294 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4295 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4296 } 4297 } 4298 4299 for (i = 0; i < sctx->isc_ntxqs; i++) { 4300 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4301 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4302 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4303 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4304 } 4305 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4306 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4307 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4308 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4309 } 4310 } 4311 } 4312 4313 int 4314 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4315 { 4316 int err, rid, msix; 4317 if_ctx_t ctx; 4318 if_t ifp; 4319 if_softc_ctx_t scctx; 4320 int i; 4321 uint16_t main_txq; 4322 uint16_t main_rxq; 4323 4324 4325 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4326 4327 if (sc == NULL) { 4328 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4329 device_set_softc(dev, ctx); 4330 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4331 } 4332 4333 ctx->ifc_sctx = sctx; 4334 ctx->ifc_dev = dev; 4335 ctx->ifc_softc = sc; 4336 4337 if ((err = iflib_register(ctx)) != 0) { 4338 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4339 free(sc, M_IFLIB); 4340 free(ctx, M_IFLIB); 4341 device_printf(dev, "iflib_register failed %d\n", err); 4342 return (err); 4343 } 4344 iflib_add_device_sysctl_pre(ctx); 4345 4346 scctx = &ctx->ifc_softc_ctx; 4347 ifp = ctx->ifc_ifp; 4348 4349 iflib_reset_qvalues(ctx); 4350 CTX_LOCK(ctx); 4351 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4352 CTX_UNLOCK(ctx); 4353 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4354 return (err); 4355 } 4356 _iflib_pre_assert(scctx); 4357 ctx->ifc_txrx = *scctx->isc_txrx; 4358 4359 #ifdef INVARIANTS 4360 MPASS(scctx->isc_capenable); 4361 if (scctx->isc_capenable & IFCAP_TXCSUM) 4362 MPASS(scctx->isc_tx_csum_flags); 4363 #endif 4364 4365 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4366 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4367 4368 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4369 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4370 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4371 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4372 4373 #ifdef ACPI_DMAR 4374 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4375 ctx->ifc_flags |= IFC_DMAR; 4376 #elif !(defined(__i386__) || defined(__amd64__)) 4377 /* set unconditionally for !x86 */ 4378 ctx->ifc_flags |= IFC_DMAR; 4379 #endif 4380 4381 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4382 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4383 4384 /* XXX change for per-queue sizes */ 4385 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4386 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4387 for (i = 0; i < sctx->isc_nrxqs; i++) { 4388 if (!powerof2(scctx->isc_nrxd[i])) { 4389 /* round down instead? */ 4390 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4391 err = EINVAL; 4392 goto fail; 4393 } 4394 } 4395 for (i = 0; i < sctx->isc_ntxqs; i++) { 4396 if (!powerof2(scctx->isc_ntxd[i])) { 4397 device_printf(dev, 4398 "# tx descriptors must be a power of 2"); 4399 err = EINVAL; 4400 goto fail; 4401 } 4402 } 4403 4404 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4405 MAX_SINGLE_PACKET_FRACTION) 4406 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4407 MAX_SINGLE_PACKET_FRACTION); 4408 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4409 MAX_SINGLE_PACKET_FRACTION) 4410 scctx->isc_tx_tso_segments_max = max(1, 4411 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4412 4413 /* 4414 * Protect the stack against modern hardware 4415 */ 4416 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4417 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4418 4419 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4420 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4421 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4422 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4423 if (scctx->isc_rss_table_size == 0) 4424 scctx->isc_rss_table_size = 64; 4425 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4426 4427 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4428 /* XXX format name */ 4429 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4430 4431 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4432 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4433 device_printf(dev, "Unable to fetch CPU list\n"); 4434 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4435 } 4436 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4437 4438 /* 4439 ** Now setup MSI or MSI/X, should 4440 ** return us the number of supported 4441 ** vectors. (Will be 1 for MSI) 4442 */ 4443 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4444 msix = scctx->isc_vectors; 4445 } else if (scctx->isc_msix_bar != 0) 4446 /* 4447 * The simple fact that isc_msix_bar is not 0 does not mean we 4448 * we have a good value there that is known to work. 4449 */ 4450 msix = iflib_msix_init(ctx); 4451 else { 4452 scctx->isc_vectors = 1; 4453 scctx->isc_ntxqsets = 1; 4454 scctx->isc_nrxqsets = 1; 4455 scctx->isc_intr = IFLIB_INTR_LEGACY; 4456 msix = 0; 4457 } 4458 /* Get memory for the station queues */ 4459 if ((err = iflib_queues_alloc(ctx))) { 4460 device_printf(dev, "Unable to allocate queue memory\n"); 4461 goto fail; 4462 } 4463 4464 if ((err = iflib_qset_structures_setup(ctx))) 4465 goto fail_queues; 4466 4467 /* 4468 * Group taskqueues aren't properly set up until SMP is started, 4469 * so we disable interrupts until we can handle them post 4470 * SI_SUB_SMP. 4471 * 4472 * XXX: disabling interrupts doesn't actually work, at least for 4473 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4474 * we do null handling and depend on this not causing too large an 4475 * interrupt storm. 4476 */ 4477 IFDI_INTR_DISABLE(ctx); 4478 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4479 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4480 goto fail_intr_free; 4481 } 4482 if (msix <= 1) { 4483 rid = 0; 4484 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4485 MPASS(msix == 1); 4486 rid = 1; 4487 } 4488 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4489 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4490 goto fail_intr_free; 4491 } 4492 } 4493 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4494 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4495 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4496 goto fail_detach; 4497 } 4498 if ((err = iflib_netmap_attach(ctx))) { 4499 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4500 goto fail_detach; 4501 } 4502 *ctxp = ctx; 4503 4504 NETDUMP_SET(ctx->ifc_ifp, iflib); 4505 4506 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4507 iflib_add_device_sysctl_post(ctx); 4508 ctx->ifc_flags |= IFC_INIT_DONE; 4509 CTX_UNLOCK(ctx); 4510 return (0); 4511 fail_detach: 4512 ether_ifdetach(ctx->ifc_ifp); 4513 fail_intr_free: 4514 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4515 pci_release_msi(ctx->ifc_dev); 4516 fail_queues: 4517 iflib_tx_structures_free(ctx); 4518 iflib_rx_structures_free(ctx); 4519 fail: 4520 IFDI_DETACH(ctx); 4521 CTX_UNLOCK(ctx); 4522 return (err); 4523 } 4524 4525 int 4526 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4527 struct iflib_cloneattach_ctx *clctx) 4528 { 4529 int err; 4530 if_ctx_t ctx; 4531 if_t ifp; 4532 if_softc_ctx_t scctx; 4533 int i; 4534 void *sc; 4535 uint16_t main_txq; 4536 uint16_t main_rxq; 4537 4538 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4539 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4540 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4541 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4542 ctx->ifc_flags |= IFC_PSEUDO; 4543 4544 ctx->ifc_sctx = sctx; 4545 ctx->ifc_softc = sc; 4546 ctx->ifc_dev = dev; 4547 4548 if ((err = iflib_register(ctx)) != 0) { 4549 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4550 free(sc, M_IFLIB); 4551 free(ctx, M_IFLIB); 4552 return (err); 4553 } 4554 iflib_add_device_sysctl_pre(ctx); 4555 4556 scctx = &ctx->ifc_softc_ctx; 4557 ifp = ctx->ifc_ifp; 4558 4559 /* 4560 * XXX sanity check that ntxd & nrxd are a power of 2 4561 */ 4562 iflib_reset_qvalues(ctx); 4563 4564 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4565 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4566 return (err); 4567 } 4568 if (sctx->isc_flags & IFLIB_GEN_MAC) 4569 iflib_gen_mac(ctx); 4570 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4571 clctx->cc_params)) != 0) { 4572 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4573 return (err); 4574 } 4575 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4576 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 4577 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO); 4578 4579 #ifdef INVARIANTS 4580 MPASS(scctx->isc_capenable); 4581 if (scctx->isc_capenable & IFCAP_TXCSUM) 4582 MPASS(scctx->isc_tx_csum_flags); 4583 #endif 4584 4585 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4586 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4587 4588 ifp->if_flags |= IFF_NOGROUP; 4589 if (sctx->isc_flags & IFLIB_PSEUDO) { 4590 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4591 4592 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4593 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4594 goto fail_detach; 4595 } 4596 *ctxp = ctx; 4597 4598 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4599 iflib_add_device_sysctl_post(ctx); 4600 ctx->ifc_flags |= IFC_INIT_DONE; 4601 return (0); 4602 } 4603 _iflib_pre_assert(scctx); 4604 ctx->ifc_txrx = *scctx->isc_txrx; 4605 4606 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4607 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4608 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4609 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4610 4611 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4612 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4613 4614 /* XXX change for per-queue sizes */ 4615 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4616 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4617 for (i = 0; i < sctx->isc_nrxqs; i++) { 4618 if (!powerof2(scctx->isc_nrxd[i])) { 4619 /* round down instead? */ 4620 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4621 err = EINVAL; 4622 goto fail; 4623 } 4624 } 4625 for (i = 0; i < sctx->isc_ntxqs; i++) { 4626 if (!powerof2(scctx->isc_ntxd[i])) { 4627 device_printf(dev, 4628 "# tx descriptors must be a power of 2"); 4629 err = EINVAL; 4630 goto fail; 4631 } 4632 } 4633 4634 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4635 MAX_SINGLE_PACKET_FRACTION) 4636 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4637 MAX_SINGLE_PACKET_FRACTION); 4638 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4639 MAX_SINGLE_PACKET_FRACTION) 4640 scctx->isc_tx_tso_segments_max = max(1, 4641 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4642 4643 /* 4644 * Protect the stack against modern hardware 4645 */ 4646 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4647 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4648 4649 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4650 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4651 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4652 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4653 if (scctx->isc_rss_table_size == 0) 4654 scctx->isc_rss_table_size = 64; 4655 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4656 4657 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4658 /* XXX format name */ 4659 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4660 4661 /* XXX --- can support > 1 -- but keep it simple for now */ 4662 scctx->isc_intr = IFLIB_INTR_LEGACY; 4663 4664 /* Get memory for the station queues */ 4665 if ((err = iflib_queues_alloc(ctx))) { 4666 device_printf(dev, "Unable to allocate queue memory\n"); 4667 goto fail; 4668 } 4669 4670 if ((err = iflib_qset_structures_setup(ctx))) { 4671 device_printf(dev, "qset structure setup failed %d\n", err); 4672 goto fail_queues; 4673 } 4674 /* 4675 * XXX What if anything do we want to do about interrupts? 4676 */ 4677 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4678 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4679 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4680 goto fail_detach; 4681 } 4682 /* XXX handle more than one queue */ 4683 for (i = 0; i < scctx->isc_nrxqsets; i++) 4684 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4685 4686 *ctxp = ctx; 4687 4688 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4689 iflib_add_device_sysctl_post(ctx); 4690 ctx->ifc_flags |= IFC_INIT_DONE; 4691 return (0); 4692 fail_detach: 4693 ether_ifdetach(ctx->ifc_ifp); 4694 fail_queues: 4695 iflib_tx_structures_free(ctx); 4696 iflib_rx_structures_free(ctx); 4697 fail: 4698 IFDI_DETACH(ctx); 4699 return (err); 4700 } 4701 4702 int 4703 iflib_pseudo_deregister(if_ctx_t ctx) 4704 { 4705 if_t ifp = ctx->ifc_ifp; 4706 iflib_txq_t txq; 4707 iflib_rxq_t rxq; 4708 int i, j; 4709 struct taskqgroup *tqg; 4710 iflib_fl_t fl; 4711 4712 /* Unregister VLAN events */ 4713 if (ctx->ifc_vlan_attach_event != NULL) 4714 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4715 if (ctx->ifc_vlan_detach_event != NULL) 4716 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4717 4718 ether_ifdetach(ifp); 4719 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4720 CTX_LOCK_DESTROY(ctx); 4721 /* XXX drain any dependent tasks */ 4722 tqg = qgroup_if_io_tqg; 4723 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4724 callout_drain(&txq->ift_timer); 4725 if (txq->ift_task.gt_uniq != NULL) 4726 taskqgroup_detach(tqg, &txq->ift_task); 4727 } 4728 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4729 if (rxq->ifr_task.gt_uniq != NULL) 4730 taskqgroup_detach(tqg, &rxq->ifr_task); 4731 4732 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4733 free(fl->ifl_rx_bitmap, M_IFLIB); 4734 } 4735 tqg = qgroup_if_config_tqg; 4736 if (ctx->ifc_admin_task.gt_uniq != NULL) 4737 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4738 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4739 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4740 4741 if_free(ifp); 4742 4743 iflib_tx_structures_free(ctx); 4744 iflib_rx_structures_free(ctx); 4745 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4746 free(ctx->ifc_softc, M_IFLIB); 4747 free(ctx, M_IFLIB); 4748 return (0); 4749 } 4750 4751 int 4752 iflib_device_attach(device_t dev) 4753 { 4754 if_ctx_t ctx; 4755 if_shared_ctx_t sctx; 4756 4757 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4758 return (ENOTSUP); 4759 4760 pci_enable_busmaster(dev); 4761 4762 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4763 } 4764 4765 int 4766 iflib_device_deregister(if_ctx_t ctx) 4767 { 4768 if_t ifp = ctx->ifc_ifp; 4769 iflib_txq_t txq; 4770 iflib_rxq_t rxq; 4771 device_t dev = ctx->ifc_dev; 4772 int i, j; 4773 struct taskqgroup *tqg; 4774 iflib_fl_t fl; 4775 4776 /* Make sure VLANS are not using driver */ 4777 if (if_vlantrunkinuse(ifp)) { 4778 device_printf(dev,"Vlan in use, detach first\n"); 4779 return (EBUSY); 4780 } 4781 4782 CTX_LOCK(ctx); 4783 ctx->ifc_in_detach = 1; 4784 iflib_stop(ctx); 4785 CTX_UNLOCK(ctx); 4786 4787 /* Unregister VLAN events */ 4788 if (ctx->ifc_vlan_attach_event != NULL) 4789 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4790 if (ctx->ifc_vlan_detach_event != NULL) 4791 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4792 4793 iflib_netmap_detach(ifp); 4794 ether_ifdetach(ifp); 4795 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4796 CTX_LOCK_DESTROY(ctx); 4797 if (ctx->ifc_led_dev != NULL) 4798 led_destroy(ctx->ifc_led_dev); 4799 /* XXX drain any dependent tasks */ 4800 tqg = qgroup_if_io_tqg; 4801 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4802 callout_drain(&txq->ift_timer); 4803 if (txq->ift_task.gt_uniq != NULL) 4804 taskqgroup_detach(tqg, &txq->ift_task); 4805 } 4806 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4807 if (rxq->ifr_task.gt_uniq != NULL) 4808 taskqgroup_detach(tqg, &rxq->ifr_task); 4809 4810 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4811 free(fl->ifl_rx_bitmap, M_IFLIB); 4812 4813 } 4814 tqg = qgroup_if_config_tqg; 4815 if (ctx->ifc_admin_task.gt_uniq != NULL) 4816 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4817 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4818 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4819 4820 IFDI_DETACH(ctx); 4821 device_set_softc(ctx->ifc_dev, NULL); 4822 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4823 pci_release_msi(dev); 4824 } 4825 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4826 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4827 } 4828 if (ctx->ifc_msix_mem != NULL) { 4829 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4830 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4831 ctx->ifc_msix_mem = NULL; 4832 } 4833 4834 bus_generic_detach(dev); 4835 if_free(ifp); 4836 4837 iflib_tx_structures_free(ctx); 4838 iflib_rx_structures_free(ctx); 4839 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4840 free(ctx->ifc_softc, M_IFLIB); 4841 free(ctx, M_IFLIB); 4842 return (0); 4843 } 4844 4845 4846 int 4847 iflib_device_detach(device_t dev) 4848 { 4849 if_ctx_t ctx = device_get_softc(dev); 4850 4851 return (iflib_device_deregister(ctx)); 4852 } 4853 4854 int 4855 iflib_device_suspend(device_t dev) 4856 { 4857 if_ctx_t ctx = device_get_softc(dev); 4858 4859 CTX_LOCK(ctx); 4860 IFDI_SUSPEND(ctx); 4861 CTX_UNLOCK(ctx); 4862 4863 return bus_generic_suspend(dev); 4864 } 4865 int 4866 iflib_device_shutdown(device_t dev) 4867 { 4868 if_ctx_t ctx = device_get_softc(dev); 4869 4870 CTX_LOCK(ctx); 4871 IFDI_SHUTDOWN(ctx); 4872 CTX_UNLOCK(ctx); 4873 4874 return bus_generic_suspend(dev); 4875 } 4876 4877 4878 int 4879 iflib_device_resume(device_t dev) 4880 { 4881 if_ctx_t ctx = device_get_softc(dev); 4882 iflib_txq_t txq = ctx->ifc_txqs; 4883 4884 CTX_LOCK(ctx); 4885 IFDI_RESUME(ctx); 4886 iflib_init_locked(ctx); 4887 CTX_UNLOCK(ctx); 4888 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4889 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4890 4891 return (bus_generic_resume(dev)); 4892 } 4893 4894 int 4895 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4896 { 4897 int error; 4898 if_ctx_t ctx = device_get_softc(dev); 4899 4900 CTX_LOCK(ctx); 4901 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4902 CTX_UNLOCK(ctx); 4903 4904 return (error); 4905 } 4906 4907 void 4908 iflib_device_iov_uninit(device_t dev) 4909 { 4910 if_ctx_t ctx = device_get_softc(dev); 4911 4912 CTX_LOCK(ctx); 4913 IFDI_IOV_UNINIT(ctx); 4914 CTX_UNLOCK(ctx); 4915 } 4916 4917 int 4918 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 4919 { 4920 int error; 4921 if_ctx_t ctx = device_get_softc(dev); 4922 4923 CTX_LOCK(ctx); 4924 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 4925 CTX_UNLOCK(ctx); 4926 4927 return (error); 4928 } 4929 4930 /********************************************************************* 4931 * 4932 * MODULE FUNCTION DEFINITIONS 4933 * 4934 **********************************************************************/ 4935 4936 /* 4937 * - Start a fast taskqueue thread for each core 4938 * - Start a taskqueue for control operations 4939 */ 4940 static int 4941 iflib_module_init(void) 4942 { 4943 return (0); 4944 } 4945 4946 static int 4947 iflib_module_event_handler(module_t mod, int what, void *arg) 4948 { 4949 int err; 4950 4951 switch (what) { 4952 case MOD_LOAD: 4953 if ((err = iflib_module_init()) != 0) 4954 return (err); 4955 break; 4956 case MOD_UNLOAD: 4957 return (EBUSY); 4958 default: 4959 return (EOPNOTSUPP); 4960 } 4961 4962 return (0); 4963 } 4964 4965 /********************************************************************* 4966 * 4967 * PUBLIC FUNCTION DEFINITIONS 4968 * ordered as in iflib.h 4969 * 4970 **********************************************************************/ 4971 4972 4973 static void 4974 _iflib_assert(if_shared_ctx_t sctx) 4975 { 4976 MPASS(sctx->isc_tx_maxsize); 4977 MPASS(sctx->isc_tx_maxsegsize); 4978 4979 MPASS(sctx->isc_rx_maxsize); 4980 MPASS(sctx->isc_rx_nsegments); 4981 MPASS(sctx->isc_rx_maxsegsize); 4982 4983 MPASS(sctx->isc_nrxd_min[0]); 4984 MPASS(sctx->isc_nrxd_max[0]); 4985 MPASS(sctx->isc_nrxd_default[0]); 4986 MPASS(sctx->isc_ntxd_min[0]); 4987 MPASS(sctx->isc_ntxd_max[0]); 4988 MPASS(sctx->isc_ntxd_default[0]); 4989 } 4990 4991 static void 4992 _iflib_pre_assert(if_softc_ctx_t scctx) 4993 { 4994 4995 MPASS(scctx->isc_txrx->ift_txd_encap); 4996 MPASS(scctx->isc_txrx->ift_txd_flush); 4997 MPASS(scctx->isc_txrx->ift_txd_credits_update); 4998 MPASS(scctx->isc_txrx->ift_rxd_available); 4999 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5000 MPASS(scctx->isc_txrx->ift_rxd_refill); 5001 MPASS(scctx->isc_txrx->ift_rxd_flush); 5002 } 5003 5004 static int 5005 iflib_register(if_ctx_t ctx) 5006 { 5007 if_shared_ctx_t sctx = ctx->ifc_sctx; 5008 driver_t *driver = sctx->isc_driver; 5009 device_t dev = ctx->ifc_dev; 5010 if_t ifp; 5011 5012 _iflib_assert(sctx); 5013 5014 CTX_LOCK_INIT(ctx); 5015 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5016 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 5017 if (ifp == NULL) { 5018 device_printf(dev, "can not allocate ifnet structure\n"); 5019 return (ENOMEM); 5020 } 5021 5022 /* 5023 * Initialize our context's device specific methods 5024 */ 5025 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5026 kobj_class_compile((kobj_class_t) driver); 5027 driver->refs++; 5028 5029 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5030 if_setsoftc(ifp, ctx); 5031 if_setdev(ifp, dev); 5032 if_setinitfn(ifp, iflib_if_init); 5033 if_setioctlfn(ifp, iflib_if_ioctl); 5034 if_settransmitfn(ifp, iflib_if_transmit); 5035 if_setqflushfn(ifp, iflib_if_qflush); 5036 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5037 5038 ctx->ifc_vlan_attach_event = 5039 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5040 EVENTHANDLER_PRI_FIRST); 5041 ctx->ifc_vlan_detach_event = 5042 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5043 EVENTHANDLER_PRI_FIRST); 5044 5045 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 5046 iflib_media_change, iflib_media_status); 5047 5048 return (0); 5049 } 5050 5051 5052 static int 5053 iflib_queues_alloc(if_ctx_t ctx) 5054 { 5055 if_shared_ctx_t sctx = ctx->ifc_sctx; 5056 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5057 device_t dev = ctx->ifc_dev; 5058 int nrxqsets = scctx->isc_nrxqsets; 5059 int ntxqsets = scctx->isc_ntxqsets; 5060 iflib_txq_t txq; 5061 iflib_rxq_t rxq; 5062 iflib_fl_t fl = NULL; 5063 int i, j, cpu, err, txconf, rxconf; 5064 iflib_dma_info_t ifdip; 5065 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5066 uint32_t *txqsizes = scctx->isc_txqsizes; 5067 uint8_t nrxqs = sctx->isc_nrxqs; 5068 uint8_t ntxqs = sctx->isc_ntxqs; 5069 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5070 caddr_t *vaddrs; 5071 uint64_t *paddrs; 5072 5073 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5074 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5075 5076 /* Allocate the TX ring struct memory */ 5077 if (!(ctx->ifc_txqs = 5078 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5079 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5080 device_printf(dev, "Unable to allocate TX ring memory\n"); 5081 err = ENOMEM; 5082 goto fail; 5083 } 5084 5085 /* Now allocate the RX */ 5086 if (!(ctx->ifc_rxqs = 5087 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5088 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5089 device_printf(dev, "Unable to allocate RX ring memory\n"); 5090 err = ENOMEM; 5091 goto rx_fail; 5092 } 5093 5094 txq = ctx->ifc_txqs; 5095 rxq = ctx->ifc_rxqs; 5096 5097 /* 5098 * XXX handle allocation failure 5099 */ 5100 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5101 /* Set up some basics */ 5102 5103 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 5104 device_printf(dev, "failed to allocate iflib_dma_info\n"); 5105 err = ENOMEM; 5106 goto err_tx_desc; 5107 } 5108 txq->ift_ifdi = ifdip; 5109 for (j = 0; j < ntxqs; j++, ifdip++) { 5110 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 5111 device_printf(dev, "Unable to allocate Descriptor memory\n"); 5112 err = ENOMEM; 5113 goto err_tx_desc; 5114 } 5115 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5116 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5117 } 5118 txq->ift_ctx = ctx; 5119 txq->ift_id = i; 5120 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5121 txq->ift_br_offset = 1; 5122 } else { 5123 txq->ift_br_offset = 0; 5124 } 5125 /* XXX fix this */ 5126 txq->ift_timer.c_cpu = cpu; 5127 5128 if (iflib_txsd_alloc(txq)) { 5129 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5130 err = ENOMEM; 5131 goto err_tx_desc; 5132 } 5133 5134 /* Initialize the TX lock */ 5135 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 5136 device_get_nameunit(dev), txq->ift_id); 5137 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5138 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5139 5140 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 5141 device_get_nameunit(dev), txq->ift_id); 5142 5143 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5144 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5145 if (err) { 5146 /* XXX free any allocated rings */ 5147 device_printf(dev, "Unable to allocate buf_ring\n"); 5148 goto err_tx_desc; 5149 } 5150 } 5151 5152 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5153 /* Set up some basics */ 5154 5155 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 5156 device_printf(dev, "failed to allocate iflib_dma_info\n"); 5157 err = ENOMEM; 5158 goto err_tx_desc; 5159 } 5160 5161 rxq->ifr_ifdi = ifdip; 5162 /* XXX this needs to be changed if #rx queues != #tx queues */ 5163 rxq->ifr_ntxqirq = 1; 5164 rxq->ifr_txqid[0] = i; 5165 for (j = 0; j < nrxqs; j++, ifdip++) { 5166 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 5167 device_printf(dev, "Unable to allocate Descriptor memory\n"); 5168 err = ENOMEM; 5169 goto err_tx_desc; 5170 } 5171 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5172 } 5173 rxq->ifr_ctx = ctx; 5174 rxq->ifr_id = i; 5175 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5176 rxq->ifr_fl_offset = 1; 5177 } else { 5178 rxq->ifr_fl_offset = 0; 5179 } 5180 rxq->ifr_nfl = nfree_lists; 5181 if (!(fl = 5182 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5183 device_printf(dev, "Unable to allocate free list memory\n"); 5184 err = ENOMEM; 5185 goto err_tx_desc; 5186 } 5187 rxq->ifr_fl = fl; 5188 for (j = 0; j < nfree_lists; j++) { 5189 fl[j].ifl_rxq = rxq; 5190 fl[j].ifl_id = j; 5191 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5192 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5193 } 5194 /* Allocate receive buffers for the ring*/ 5195 if (iflib_rxsd_alloc(rxq)) { 5196 device_printf(dev, 5197 "Critical Failure setting up receive buffers\n"); 5198 err = ENOMEM; 5199 goto err_rx_desc; 5200 } 5201 5202 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5203 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 5204 } 5205 5206 /* TXQs */ 5207 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5208 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5209 for (i = 0; i < ntxqsets; i++) { 5210 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5211 5212 for (j = 0; j < ntxqs; j++, di++) { 5213 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5214 paddrs[i*ntxqs + j] = di->idi_paddr; 5215 } 5216 } 5217 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5218 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 5219 iflib_tx_structures_free(ctx); 5220 free(vaddrs, M_IFLIB); 5221 free(paddrs, M_IFLIB); 5222 goto err_rx_desc; 5223 } 5224 free(vaddrs, M_IFLIB); 5225 free(paddrs, M_IFLIB); 5226 5227 /* RXQs */ 5228 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5229 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5230 for (i = 0; i < nrxqsets; i++) { 5231 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5232 5233 for (j = 0; j < nrxqs; j++, di++) { 5234 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5235 paddrs[i*nrxqs + j] = di->idi_paddr; 5236 } 5237 } 5238 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5239 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 5240 iflib_tx_structures_free(ctx); 5241 free(vaddrs, M_IFLIB); 5242 free(paddrs, M_IFLIB); 5243 goto err_rx_desc; 5244 } 5245 free(vaddrs, M_IFLIB); 5246 free(paddrs, M_IFLIB); 5247 5248 return (0); 5249 5250 /* XXX handle allocation failure changes */ 5251 err_rx_desc: 5252 err_tx_desc: 5253 rx_fail: 5254 if (ctx->ifc_rxqs != NULL) 5255 free(ctx->ifc_rxqs, M_IFLIB); 5256 ctx->ifc_rxqs = NULL; 5257 if (ctx->ifc_txqs != NULL) 5258 free(ctx->ifc_txqs, M_IFLIB); 5259 ctx->ifc_txqs = NULL; 5260 fail: 5261 return (err); 5262 } 5263 5264 static int 5265 iflib_tx_structures_setup(if_ctx_t ctx) 5266 { 5267 iflib_txq_t txq = ctx->ifc_txqs; 5268 int i; 5269 5270 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5271 iflib_txq_setup(txq); 5272 5273 return (0); 5274 } 5275 5276 static void 5277 iflib_tx_structures_free(if_ctx_t ctx) 5278 { 5279 iflib_txq_t txq = ctx->ifc_txqs; 5280 int i, j; 5281 5282 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5283 iflib_txq_destroy(txq); 5284 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 5285 iflib_dma_free(&txq->ift_ifdi[j]); 5286 } 5287 free(ctx->ifc_txqs, M_IFLIB); 5288 ctx->ifc_txqs = NULL; 5289 IFDI_QUEUES_FREE(ctx); 5290 } 5291 5292 /********************************************************************* 5293 * 5294 * Initialize all receive rings. 5295 * 5296 **********************************************************************/ 5297 static int 5298 iflib_rx_structures_setup(if_ctx_t ctx) 5299 { 5300 iflib_rxq_t rxq = ctx->ifc_rxqs; 5301 int q; 5302 #if defined(INET6) || defined(INET) 5303 int i, err; 5304 #endif 5305 5306 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5307 #if defined(INET6) || defined(INET) 5308 tcp_lro_free(&rxq->ifr_lc); 5309 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5310 TCP_LRO_ENTRIES, min(1024, 5311 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 5312 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 5313 goto fail; 5314 } 5315 rxq->ifr_lro_enabled = TRUE; 5316 #endif 5317 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5318 } 5319 return (0); 5320 #if defined(INET6) || defined(INET) 5321 fail: 5322 /* 5323 * Free RX software descriptors allocated so far, we will only handle 5324 * the rings that completed, the failing case will have 5325 * cleaned up for itself. 'q' failed, so its the terminus. 5326 */ 5327 rxq = ctx->ifc_rxqs; 5328 for (i = 0; i < q; ++i, rxq++) { 5329 iflib_rx_sds_free(rxq); 5330 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5331 } 5332 return (err); 5333 #endif 5334 } 5335 5336 /********************************************************************* 5337 * 5338 * Free all receive rings. 5339 * 5340 **********************************************************************/ 5341 static void 5342 iflib_rx_structures_free(if_ctx_t ctx) 5343 { 5344 iflib_rxq_t rxq = ctx->ifc_rxqs; 5345 5346 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5347 iflib_rx_sds_free(rxq); 5348 } 5349 } 5350 5351 static int 5352 iflib_qset_structures_setup(if_ctx_t ctx) 5353 { 5354 int err; 5355 5356 /* 5357 * It is expected that the caller takes care of freeing queues if this 5358 * fails. 5359 */ 5360 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5361 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5362 return (err); 5363 } 5364 5365 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5366 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5367 5368 return (err); 5369 } 5370 5371 int 5372 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5373 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name) 5374 { 5375 5376 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5377 } 5378 5379 #ifdef SMP 5380 static int 5381 find_nth(if_ctx_t ctx, int qid) 5382 { 5383 cpuset_t cpus; 5384 int i, cpuid, eqid, count; 5385 5386 CPU_COPY(&ctx->ifc_cpus, &cpus); 5387 count = CPU_COUNT(&cpus); 5388 eqid = qid % count; 5389 /* clear up to the qid'th bit */ 5390 for (i = 0; i < eqid; i++) { 5391 cpuid = CPU_FFS(&cpus); 5392 MPASS(cpuid != 0); 5393 CPU_CLR(cpuid-1, &cpus); 5394 } 5395 cpuid = CPU_FFS(&cpus); 5396 MPASS(cpuid != 0); 5397 return (cpuid-1); 5398 } 5399 5400 #ifdef SCHED_ULE 5401 extern struct cpu_group *cpu_top; /* CPU topology */ 5402 5403 static int 5404 find_child_with_core(int cpu, struct cpu_group *grp) 5405 { 5406 int i; 5407 5408 if (grp->cg_children == 0) 5409 return -1; 5410 5411 MPASS(grp->cg_child); 5412 for (i = 0; i < grp->cg_children; i++) { 5413 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5414 return i; 5415 } 5416 5417 return -1; 5418 } 5419 5420 /* 5421 * Find the nth "close" core to the specified core 5422 * "close" is defined as the deepest level that shares 5423 * at least an L2 cache. With threads, this will be 5424 * threads on the same core. If the sahred cache is L3 5425 * or higher, simply returns the same core. 5426 */ 5427 static int 5428 find_close_core(int cpu, int core_offset) 5429 { 5430 struct cpu_group *grp; 5431 int i; 5432 int fcpu; 5433 cpuset_t cs; 5434 5435 grp = cpu_top; 5436 if (grp == NULL) 5437 return cpu; 5438 i = 0; 5439 while ((i = find_child_with_core(cpu, grp)) != -1) { 5440 /* If the child only has one cpu, don't descend */ 5441 if (grp->cg_child[i].cg_count <= 1) 5442 break; 5443 grp = &grp->cg_child[i]; 5444 } 5445 5446 /* If they don't share at least an L2 cache, use the same CPU */ 5447 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5448 return cpu; 5449 5450 /* Now pick one */ 5451 CPU_COPY(&grp->cg_mask, &cs); 5452 5453 /* Add the selected CPU offset to core offset. */ 5454 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5455 if (fcpu - 1 == cpu) 5456 break; 5457 CPU_CLR(fcpu - 1, &cs); 5458 } 5459 MPASS(fcpu); 5460 5461 core_offset += i; 5462 5463 CPU_COPY(&grp->cg_mask, &cs); 5464 for (i = core_offset % grp->cg_count; i > 0; i--) { 5465 MPASS(CPU_FFS(&cs)); 5466 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5467 } 5468 MPASS(CPU_FFS(&cs)); 5469 return CPU_FFS(&cs) - 1; 5470 } 5471 #else 5472 static int 5473 find_close_core(int cpu, int core_offset __unused) 5474 { 5475 return cpu; 5476 } 5477 #endif 5478 5479 static int 5480 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5481 { 5482 switch (type) { 5483 case IFLIB_INTR_TX: 5484 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5485 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5486 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5487 case IFLIB_INTR_RX: 5488 case IFLIB_INTR_RXTX: 5489 /* RX queues get the specified core */ 5490 return qid / CPU_COUNT(&ctx->ifc_cpus); 5491 default: 5492 return -1; 5493 } 5494 } 5495 #else 5496 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5497 #define find_close_core(cpuid, tid) CPU_FIRST() 5498 #define find_nth(ctx, gid) CPU_FIRST() 5499 #endif 5500 5501 /* Just to avoid copy/paste */ 5502 static inline int 5503 iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid, 5504 struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, char *name) 5505 { 5506 int cpuid; 5507 int err, tid; 5508 5509 cpuid = find_nth(ctx, qid); 5510 tid = get_core_offset(ctx, type, qid); 5511 MPASS(tid >= 0); 5512 cpuid = find_close_core(cpuid, tid); 5513 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name); 5514 if (err) { 5515 device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err); 5516 return (err); 5517 } 5518 #ifdef notyet 5519 if (cpuid > ctx->ifc_cpuid_highest) 5520 ctx->ifc_cpuid_highest = cpuid; 5521 #endif 5522 return 0; 5523 } 5524 5525 int 5526 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5527 iflib_intr_type_t type, driver_filter_t *filter, 5528 void *filter_arg, int qid, char *name) 5529 { 5530 struct grouptask *gtask; 5531 struct taskqgroup *tqg; 5532 iflib_filter_info_t info; 5533 gtask_fn_t *fn; 5534 int tqrid, err; 5535 driver_filter_t *intr_fast; 5536 void *q; 5537 5538 info = &ctx->ifc_filter_info; 5539 tqrid = rid; 5540 5541 switch (type) { 5542 /* XXX merge tx/rx for netmap? */ 5543 case IFLIB_INTR_TX: 5544 q = &ctx->ifc_txqs[qid]; 5545 info = &ctx->ifc_txqs[qid].ift_filter_info; 5546 gtask = &ctx->ifc_txqs[qid].ift_task; 5547 tqg = qgroup_if_io_tqg; 5548 fn = _task_fn_tx; 5549 intr_fast = iflib_fast_intr; 5550 GROUPTASK_INIT(gtask, 0, fn, q); 5551 break; 5552 case IFLIB_INTR_RX: 5553 q = &ctx->ifc_rxqs[qid]; 5554 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5555 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5556 tqg = qgroup_if_io_tqg; 5557 fn = _task_fn_rx; 5558 intr_fast = iflib_fast_intr; 5559 GROUPTASK_INIT(gtask, 0, fn, q); 5560 break; 5561 case IFLIB_INTR_RXTX: 5562 q = &ctx->ifc_rxqs[qid]; 5563 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5564 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5565 tqg = qgroup_if_io_tqg; 5566 fn = _task_fn_rx; 5567 intr_fast = iflib_fast_intr_rxtx; 5568 GROUPTASK_INIT(gtask, 0, fn, q); 5569 break; 5570 case IFLIB_INTR_ADMIN: 5571 q = ctx; 5572 tqrid = -1; 5573 info = &ctx->ifc_filter_info; 5574 gtask = &ctx->ifc_admin_task; 5575 tqg = qgroup_if_config_tqg; 5576 fn = _task_fn_admin; 5577 intr_fast = iflib_fast_intr_ctx; 5578 break; 5579 default: 5580 panic("unknown net intr type"); 5581 } 5582 5583 info->ifi_filter = filter; 5584 info->ifi_filter_arg = filter_arg; 5585 info->ifi_task = gtask; 5586 info->ifi_ctx = q; 5587 5588 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5589 if (err != 0) { 5590 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 5591 return (err); 5592 } 5593 if (type == IFLIB_INTR_ADMIN) 5594 return (0); 5595 5596 if (tqrid != -1) { 5597 err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name); 5598 if (err) 5599 return (err); 5600 } else { 5601 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5602 } 5603 5604 return (0); 5605 } 5606 5607 void 5608 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, char *name) 5609 { 5610 struct grouptask *gtask; 5611 struct taskqgroup *tqg; 5612 gtask_fn_t *fn; 5613 void *q; 5614 int irq_num = -1; 5615 int err; 5616 5617 switch (type) { 5618 case IFLIB_INTR_TX: 5619 q = &ctx->ifc_txqs[qid]; 5620 gtask = &ctx->ifc_txqs[qid].ift_task; 5621 tqg = qgroup_if_io_tqg; 5622 fn = _task_fn_tx; 5623 if (irq != NULL) 5624 irq_num = rman_get_start(irq->ii_res); 5625 break; 5626 case IFLIB_INTR_RX: 5627 q = &ctx->ifc_rxqs[qid]; 5628 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5629 tqg = qgroup_if_io_tqg; 5630 fn = _task_fn_rx; 5631 if (irq != NULL) 5632 irq_num = rman_get_start(irq->ii_res); 5633 break; 5634 case IFLIB_INTR_IOV: 5635 q = ctx; 5636 gtask = &ctx->ifc_vflr_task; 5637 tqg = qgroup_if_config_tqg; 5638 fn = _task_fn_iov; 5639 break; 5640 default: 5641 panic("unknown net intr type"); 5642 } 5643 GROUPTASK_INIT(gtask, 0, fn, q); 5644 if (irq_num != -1) { 5645 err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name); 5646 if (err) 5647 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5648 } 5649 else { 5650 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5651 } 5652 } 5653 5654 void 5655 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5656 { 5657 if (irq->ii_tag) 5658 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5659 5660 if (irq->ii_res) 5661 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5662 } 5663 5664 static int 5665 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name) 5666 { 5667 iflib_txq_t txq = ctx->ifc_txqs; 5668 iflib_rxq_t rxq = ctx->ifc_rxqs; 5669 if_irq_t irq = &ctx->ifc_legacy_irq; 5670 iflib_filter_info_t info; 5671 struct grouptask *gtask; 5672 struct taskqgroup *tqg; 5673 gtask_fn_t *fn; 5674 int tqrid; 5675 void *q; 5676 int err; 5677 5678 q = &ctx->ifc_rxqs[0]; 5679 info = &rxq[0].ifr_filter_info; 5680 gtask = &rxq[0].ifr_task; 5681 tqg = qgroup_if_io_tqg; 5682 tqrid = irq->ii_rid = *rid; 5683 fn = _task_fn_rx; 5684 5685 ctx->ifc_flags |= IFC_LEGACY; 5686 info->ifi_filter = filter; 5687 info->ifi_filter_arg = filter_arg; 5688 info->ifi_task = gtask; 5689 info->ifi_ctx = ctx; 5690 5691 /* We allocate a single interrupt resource */ 5692 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5693 return (err); 5694 GROUPTASK_INIT(gtask, 0, fn, q); 5695 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5696 5697 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5698 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx"); 5699 return (0); 5700 } 5701 5702 void 5703 iflib_led_create(if_ctx_t ctx) 5704 { 5705 5706 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5707 device_get_nameunit(ctx->ifc_dev)); 5708 } 5709 5710 void 5711 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5712 { 5713 5714 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5715 } 5716 5717 void 5718 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5719 { 5720 5721 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5722 } 5723 5724 void 5725 iflib_admin_intr_deferred(if_ctx_t ctx) 5726 { 5727 #ifdef INVARIANTS 5728 struct grouptask *gtask; 5729 5730 gtask = &ctx->ifc_admin_task; 5731 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5732 #endif 5733 5734 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5735 } 5736 5737 void 5738 iflib_iov_intr_deferred(if_ctx_t ctx) 5739 { 5740 5741 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5742 } 5743 5744 void 5745 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5746 { 5747 5748 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5749 } 5750 5751 void 5752 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 5753 const char *name) 5754 { 5755 5756 GROUPTASK_INIT(gtask, 0, fn, ctx); 5757 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5758 } 5759 5760 void 5761 iflib_config_gtask_deinit(struct grouptask *gtask) 5762 { 5763 5764 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5765 } 5766 5767 void 5768 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5769 { 5770 if_t ifp = ctx->ifc_ifp; 5771 iflib_txq_t txq = ctx->ifc_txqs; 5772 5773 if_setbaudrate(ifp, baudrate); 5774 if (baudrate >= IF_Gbps(10)) { 5775 STATE_LOCK(ctx); 5776 ctx->ifc_flags |= IFC_PREFETCH; 5777 STATE_UNLOCK(ctx); 5778 } 5779 /* If link down, disable watchdog */ 5780 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5781 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5782 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5783 } 5784 ctx->ifc_link_state = link_state; 5785 if_link_state_change(ifp, link_state); 5786 } 5787 5788 static int 5789 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5790 { 5791 int credits; 5792 #ifdef INVARIANTS 5793 int credits_pre = txq->ift_cidx_processed; 5794 #endif 5795 5796 if (ctx->isc_txd_credits_update == NULL) 5797 return (0); 5798 5799 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5800 return (0); 5801 5802 txq->ift_processed += credits; 5803 txq->ift_cidx_processed += credits; 5804 5805 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5806 if (txq->ift_cidx_processed >= txq->ift_size) 5807 txq->ift_cidx_processed -= txq->ift_size; 5808 return (credits); 5809 } 5810 5811 static int 5812 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5813 { 5814 5815 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5816 budget)); 5817 } 5818 5819 void 5820 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5821 const char *description, if_int_delay_info_t info, 5822 int offset, int value) 5823 { 5824 info->iidi_ctx = ctx; 5825 info->iidi_offset = offset; 5826 info->iidi_value = value; 5827 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5828 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5829 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5830 info, 0, iflib_sysctl_int_delay, "I", description); 5831 } 5832 5833 struct sx * 5834 iflib_ctx_lock_get(if_ctx_t ctx) 5835 { 5836 5837 return (&ctx->ifc_ctx_sx); 5838 } 5839 5840 static int 5841 iflib_msix_init(if_ctx_t ctx) 5842 { 5843 device_t dev = ctx->ifc_dev; 5844 if_shared_ctx_t sctx = ctx->ifc_sctx; 5845 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5846 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5847 int iflib_num_tx_queues, iflib_num_rx_queues; 5848 int err, admincnt, bar; 5849 5850 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 5851 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 5852 5853 device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 5854 5855 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5856 admincnt = sctx->isc_admin_intrcnt; 5857 /* Override by global tuneable */ 5858 { 5859 int i; 5860 size_t len = sizeof(i); 5861 err = kernel_sysctlbyname(curthread, "hw.pci.enable_msix", &i, &len, NULL, 0, NULL, 0); 5862 if (err == 0) { 5863 if (i == 0) 5864 goto msi; 5865 } 5866 else { 5867 device_printf(dev, "unable to read hw.pci.enable_msix."); 5868 } 5869 } 5870 /* Override by tuneable */ 5871 if (scctx->isc_disable_msix) 5872 goto msi; 5873 5874 /* 5875 ** When used in a virtualized environment 5876 ** PCI BUSMASTER capability may not be set 5877 ** so explicity set it here and rewrite 5878 ** the ENABLE in the MSIX control register 5879 ** at this point to cause the host to 5880 ** successfully initialize us. 5881 */ 5882 { 5883 int msix_ctrl, rid; 5884 5885 pci_enable_busmaster(dev); 5886 rid = 0; 5887 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) { 5888 rid += PCIR_MSIX_CTRL; 5889 msix_ctrl = pci_read_config(dev, rid, 2); 5890 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 5891 pci_write_config(dev, rid, msix_ctrl, 2); 5892 } else { 5893 device_printf(dev, "PCIY_MSIX capability not found; " 5894 "or rid %d == 0.\n", rid); 5895 goto msi; 5896 } 5897 } 5898 5899 /* 5900 * bar == -1 => "trust me I know what I'm doing" 5901 * Some drivers are for hardware that is so shoddily 5902 * documented that no one knows which bars are which 5903 * so the developer has to map all bars. This hack 5904 * allows shoddy garbage to use msix in this framework. 5905 */ 5906 if (bar != -1) { 5907 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5908 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5909 if (ctx->ifc_msix_mem == NULL) { 5910 /* May not be enabled */ 5911 device_printf(dev, "Unable to map MSIX table \n"); 5912 goto msi; 5913 } 5914 } 5915 /* First try MSI/X */ 5916 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5917 device_printf(dev, "System has MSIX disabled \n"); 5918 bus_release_resource(dev, SYS_RES_MEMORY, 5919 bar, ctx->ifc_msix_mem); 5920 ctx->ifc_msix_mem = NULL; 5921 goto msi; 5922 } 5923 #if IFLIB_DEBUG 5924 /* use only 1 qset in debug mode */ 5925 queuemsgs = min(msgs - admincnt, 1); 5926 #else 5927 queuemsgs = msgs - admincnt; 5928 #endif 5929 #ifdef RSS 5930 queues = imin(queuemsgs, rss_getnumbuckets()); 5931 #else 5932 queues = queuemsgs; 5933 #endif 5934 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 5935 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 5936 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 5937 #ifdef RSS 5938 /* If we're doing RSS, clamp at the number of RSS buckets */ 5939 if (queues > rss_getnumbuckets()) 5940 queues = rss_getnumbuckets(); 5941 #endif 5942 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 5943 rx_queues = iflib_num_rx_queues; 5944 else 5945 rx_queues = queues; 5946 5947 if (rx_queues > scctx->isc_nrxqsets) 5948 rx_queues = scctx->isc_nrxqsets; 5949 5950 /* 5951 * We want this to be all logical CPUs by default 5952 */ 5953 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 5954 tx_queues = iflib_num_tx_queues; 5955 else 5956 tx_queues = mp_ncpus; 5957 5958 if (tx_queues > scctx->isc_ntxqsets) 5959 tx_queues = scctx->isc_ntxqsets; 5960 5961 if (ctx->ifc_sysctl_qs_eq_override == 0) { 5962 #ifdef INVARIANTS 5963 if (tx_queues != rx_queues) 5964 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 5965 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 5966 #endif 5967 tx_queues = min(rx_queues, tx_queues); 5968 rx_queues = min(rx_queues, tx_queues); 5969 } 5970 5971 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 5972 5973 vectors = rx_queues + admincnt; 5974 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 5975 device_printf(dev, 5976 "Using MSIX interrupts with %d vectors\n", vectors); 5977 scctx->isc_vectors = vectors; 5978 scctx->isc_nrxqsets = rx_queues; 5979 scctx->isc_ntxqsets = tx_queues; 5980 scctx->isc_intr = IFLIB_INTR_MSIX; 5981 5982 return (vectors); 5983 } else { 5984 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 5985 } 5986 msi: 5987 vectors = pci_msi_count(dev); 5988 scctx->isc_nrxqsets = 1; 5989 scctx->isc_ntxqsets = 1; 5990 scctx->isc_vectors = vectors; 5991 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 5992 device_printf(dev,"Using an MSI interrupt\n"); 5993 scctx->isc_intr = IFLIB_INTR_MSI; 5994 } else { 5995 device_printf(dev,"Using a Legacy interrupt\n"); 5996 scctx->isc_intr = IFLIB_INTR_LEGACY; 5997 } 5998 5999 return (vectors); 6000 } 6001 6002 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6003 6004 static int 6005 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6006 { 6007 int rc; 6008 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6009 struct sbuf *sb; 6010 char *ring_state = "UNKNOWN"; 6011 6012 /* XXX needed ? */ 6013 rc = sysctl_wire_old_buffer(req, 0); 6014 MPASS(rc == 0); 6015 if (rc != 0) 6016 return (rc); 6017 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6018 MPASS(sb != NULL); 6019 if (sb == NULL) 6020 return (ENOMEM); 6021 if (state[3] <= 3) 6022 ring_state = ring_states[state[3]]; 6023 6024 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6025 state[0], state[1], state[2], ring_state); 6026 rc = sbuf_finish(sb); 6027 sbuf_delete(sb); 6028 return(rc); 6029 } 6030 6031 enum iflib_ndesc_handler { 6032 IFLIB_NTXD_HANDLER, 6033 IFLIB_NRXD_HANDLER, 6034 }; 6035 6036 static int 6037 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6038 { 6039 if_ctx_t ctx = (void *)arg1; 6040 enum iflib_ndesc_handler type = arg2; 6041 char buf[256] = {0}; 6042 qidx_t *ndesc; 6043 char *p, *next; 6044 int nqs, rc, i; 6045 6046 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 6047 6048 nqs = 8; 6049 switch(type) { 6050 case IFLIB_NTXD_HANDLER: 6051 ndesc = ctx->ifc_sysctl_ntxds; 6052 if (ctx->ifc_sctx) 6053 nqs = ctx->ifc_sctx->isc_ntxqs; 6054 break; 6055 case IFLIB_NRXD_HANDLER: 6056 ndesc = ctx->ifc_sysctl_nrxds; 6057 if (ctx->ifc_sctx) 6058 nqs = ctx->ifc_sctx->isc_nrxqs; 6059 break; 6060 default: 6061 panic("unhandled type"); 6062 } 6063 if (nqs == 0) 6064 nqs = 8; 6065 6066 for (i=0; i<8; i++) { 6067 if (i >= nqs) 6068 break; 6069 if (i) 6070 strcat(buf, ","); 6071 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6072 } 6073 6074 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6075 if (rc || req->newptr == NULL) 6076 return rc; 6077 6078 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6079 i++, p = strsep(&next, " ,")) { 6080 ndesc[i] = strtoul(p, NULL, 10); 6081 } 6082 6083 return(rc); 6084 } 6085 6086 #define NAME_BUFLEN 32 6087 static void 6088 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6089 { 6090 device_t dev = iflib_get_dev(ctx); 6091 struct sysctl_oid_list *child, *oid_list; 6092 struct sysctl_ctx_list *ctx_list; 6093 struct sysctl_oid *node; 6094 6095 ctx_list = device_get_sysctl_ctx(dev); 6096 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6097 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6098 CTLFLAG_RD, NULL, "IFLIB fields"); 6099 oid_list = SYSCTL_CHILDREN(node); 6100 6101 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6102 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 6103 "driver version"); 6104 6105 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6106 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6107 "# of txqs to use, 0 => use default #"); 6108 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6109 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6110 "# of rxqs to use, 0 => use default #"); 6111 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6112 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6113 "permit #txq != #rxq"); 6114 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6115 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6116 "disable MSIX (default 0)"); 6117 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6118 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6119 "set the rx budget"); 6120 6121 /* XXX change for per-queue sizes */ 6122 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6123 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6124 mp_ndesc_handler, "A", 6125 "list of # of tx descriptors to use, 0 = use default #"); 6126 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6127 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6128 mp_ndesc_handler, "A", 6129 "list of # of rx descriptors to use, 0 = use default #"); 6130 } 6131 6132 static void 6133 iflib_add_device_sysctl_post(if_ctx_t ctx) 6134 { 6135 if_shared_ctx_t sctx = ctx->ifc_sctx; 6136 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6137 device_t dev = iflib_get_dev(ctx); 6138 struct sysctl_oid_list *child; 6139 struct sysctl_ctx_list *ctx_list; 6140 iflib_fl_t fl; 6141 iflib_txq_t txq; 6142 iflib_rxq_t rxq; 6143 int i, j; 6144 char namebuf[NAME_BUFLEN]; 6145 char *qfmt; 6146 struct sysctl_oid *queue_node, *fl_node, *node; 6147 struct sysctl_oid_list *queue_list, *fl_list; 6148 ctx_list = device_get_sysctl_ctx(dev); 6149 6150 node = ctx->ifc_sysctl_node; 6151 child = SYSCTL_CHILDREN(node); 6152 6153 if (scctx->isc_ntxqsets > 100) 6154 qfmt = "txq%03d"; 6155 else if (scctx->isc_ntxqsets > 10) 6156 qfmt = "txq%02d"; 6157 else 6158 qfmt = "txq%d"; 6159 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6160 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6161 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6162 CTLFLAG_RD, NULL, "Queue Name"); 6163 queue_list = SYSCTL_CHILDREN(queue_node); 6164 #if MEMORY_LOGGING 6165 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6166 CTLFLAG_RD, 6167 &txq->ift_dequeued, "total mbufs freed"); 6168 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6169 CTLFLAG_RD, 6170 &txq->ift_enqueued, "total mbufs enqueued"); 6171 #endif 6172 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6173 CTLFLAG_RD, 6174 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6175 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6176 CTLFLAG_RD, 6177 &txq->ift_pullups, "# of times m_pullup was called"); 6178 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6179 CTLFLAG_RD, 6180 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6181 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6182 CTLFLAG_RD, 6183 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6184 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6185 CTLFLAG_RD, 6186 &txq->ift_map_failed, "# of times dma map failed"); 6187 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6188 CTLFLAG_RD, 6189 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6190 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6191 CTLFLAG_RD, 6192 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6193 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6194 CTLFLAG_RD, 6195 &txq->ift_pidx, 1, "Producer Index"); 6196 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6197 CTLFLAG_RD, 6198 &txq->ift_cidx, 1, "Consumer Index"); 6199 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6200 CTLFLAG_RD, 6201 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6202 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6203 CTLFLAG_RD, 6204 &txq->ift_in_use, 1, "descriptors in use"); 6205 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6206 CTLFLAG_RD, 6207 &txq->ift_processed, "descriptors procesed for clean"); 6208 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6209 CTLFLAG_RD, 6210 &txq->ift_cleaned, "total cleaned"); 6211 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6212 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6213 0, mp_ring_state_handler, "A", "soft ring state"); 6214 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6215 CTLFLAG_RD, &txq->ift_br->enqueues, 6216 "# of enqueues to the mp_ring for this queue"); 6217 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6218 CTLFLAG_RD, &txq->ift_br->drops, 6219 "# of drops in the mp_ring for this queue"); 6220 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6221 CTLFLAG_RD, &txq->ift_br->starts, 6222 "# of normal consumer starts in the mp_ring for this queue"); 6223 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6224 CTLFLAG_RD, &txq->ift_br->stalls, 6225 "# of consumer stalls in the mp_ring for this queue"); 6226 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6227 CTLFLAG_RD, &txq->ift_br->restarts, 6228 "# of consumer restarts in the mp_ring for this queue"); 6229 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6230 CTLFLAG_RD, &txq->ift_br->abdications, 6231 "# of consumer abdications in the mp_ring for this queue"); 6232 } 6233 6234 if (scctx->isc_nrxqsets > 100) 6235 qfmt = "rxq%03d"; 6236 else if (scctx->isc_nrxqsets > 10) 6237 qfmt = "rxq%02d"; 6238 else 6239 qfmt = "rxq%d"; 6240 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6241 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6242 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6243 CTLFLAG_RD, NULL, "Queue Name"); 6244 queue_list = SYSCTL_CHILDREN(queue_node); 6245 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6246 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 6247 CTLFLAG_RD, 6248 &rxq->ifr_cq_pidx, 1, "Producer Index"); 6249 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6250 CTLFLAG_RD, 6251 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6252 } 6253 6254 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6255 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6256 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6257 CTLFLAG_RD, NULL, "freelist Name"); 6258 fl_list = SYSCTL_CHILDREN(fl_node); 6259 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6260 CTLFLAG_RD, 6261 &fl->ifl_pidx, 1, "Producer Index"); 6262 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6263 CTLFLAG_RD, 6264 &fl->ifl_cidx, 1, "Consumer Index"); 6265 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6266 CTLFLAG_RD, 6267 &fl->ifl_credits, 1, "credits available"); 6268 #if MEMORY_LOGGING 6269 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6270 CTLFLAG_RD, 6271 &fl->ifl_m_enqueued, "mbufs allocated"); 6272 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6273 CTLFLAG_RD, 6274 &fl->ifl_m_dequeued, "mbufs freed"); 6275 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6276 CTLFLAG_RD, 6277 &fl->ifl_cl_enqueued, "clusters allocated"); 6278 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6279 CTLFLAG_RD, 6280 &fl->ifl_cl_dequeued, "clusters freed"); 6281 #endif 6282 6283 } 6284 } 6285 6286 } 6287 6288 #ifndef __NO_STRICT_ALIGNMENT 6289 static struct mbuf * 6290 iflib_fixup_rx(struct mbuf *m) 6291 { 6292 struct mbuf *n; 6293 6294 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6295 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6296 m->m_data += ETHER_HDR_LEN; 6297 n = m; 6298 } else { 6299 MGETHDR(n, M_NOWAIT, MT_DATA); 6300 if (n == NULL) { 6301 m_freem(m); 6302 return (NULL); 6303 } 6304 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6305 m->m_data += ETHER_HDR_LEN; 6306 m->m_len -= ETHER_HDR_LEN; 6307 n->m_len = ETHER_HDR_LEN; 6308 M_MOVE_PKTHDR(n, m); 6309 n->m_next = m; 6310 } 6311 return (n); 6312 } 6313 #endif 6314 6315 #ifdef NETDUMP 6316 static void 6317 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 6318 { 6319 if_ctx_t ctx; 6320 6321 ctx = if_getsoftc(ifp); 6322 CTX_LOCK(ctx); 6323 *nrxr = NRXQSETS(ctx); 6324 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6325 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6326 CTX_UNLOCK(ctx); 6327 } 6328 6329 static void 6330 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event) 6331 { 6332 if_ctx_t ctx; 6333 if_softc_ctx_t scctx; 6334 iflib_fl_t fl; 6335 iflib_rxq_t rxq; 6336 int i, j; 6337 6338 ctx = if_getsoftc(ifp); 6339 scctx = &ctx->ifc_softc_ctx; 6340 6341 switch (event) { 6342 case NETDUMP_START: 6343 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6344 rxq = &ctx->ifc_rxqs[i]; 6345 for (j = 0; j < rxq->ifr_nfl; j++) { 6346 fl = rxq->ifr_fl; 6347 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6348 } 6349 } 6350 iflib_no_tx_batch = 1; 6351 break; 6352 default: 6353 break; 6354 } 6355 } 6356 6357 static int 6358 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m) 6359 { 6360 if_ctx_t ctx; 6361 iflib_txq_t txq; 6362 int error; 6363 6364 ctx = if_getsoftc(ifp); 6365 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6366 IFF_DRV_RUNNING) 6367 return (EBUSY); 6368 6369 txq = &ctx->ifc_txqs[0]; 6370 error = iflib_encap(txq, &m); 6371 if (error == 0) 6372 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6373 return (error); 6374 } 6375 6376 static int 6377 iflib_netdump_poll(struct ifnet *ifp, int count) 6378 { 6379 if_ctx_t ctx; 6380 if_softc_ctx_t scctx; 6381 iflib_txq_t txq; 6382 int i; 6383 6384 ctx = if_getsoftc(ifp); 6385 scctx = &ctx->ifc_softc_ctx; 6386 6387 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6388 IFF_DRV_RUNNING) 6389 return (EBUSY); 6390 6391 txq = &ctx->ifc_txqs[0]; 6392 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6393 6394 for (i = 0; i < scctx->isc_nrxqsets; i++) 6395 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6396 return (0); 6397 } 6398 #endif /* NETDUMP */ 6399