1 /*- 2 * Copyright (c) 2014-2017, Matthew Macy <mmacy@nextbsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 35 #include <sys/param.h> 36 #include <sys/types.h> 37 #include <sys/bus.h> 38 #include <sys/eventhandler.h> 39 #include <sys/sockio.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sysctl.h> 50 #include <sys/syslog.h> 51 #include <sys/taskqueue.h> 52 #include <sys/limits.h> 53 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 63 #include <netinet/in.h> 64 #include <netinet/in_pcb.h> 65 #include <netinet/tcp_lro.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/if_ether.h> 68 #include <netinet/ip.h> 69 #include <netinet/ip6.h> 70 #include <netinet/tcp.h> 71 72 #include <machine/bus.h> 73 #include <machine/in_cksum.h> 74 75 #include <vm/vm.h> 76 #include <vm/pmap.h> 77 78 #include <dev/led/led.h> 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pci_private.h> 82 83 #include <net/iflib.h> 84 85 #include "ifdi_if.h" 86 87 #if defined(__i386__) || defined(__amd64__) 88 #include <sys/memdesc.h> 89 #include <machine/bus.h> 90 #include <machine/md_var.h> 91 #include <machine/specialreg.h> 92 #include <x86/include/busdma_impl.h> 93 #include <x86/iommu/busdma_dmar.h> 94 #endif 95 96 /* 97 * enable accounting of every mbuf as it comes in to and goes out of 98 * iflib's software descriptor references 99 */ 100 #define MEMORY_LOGGING 0 101 /* 102 * Enable mbuf vectors for compressing long mbuf chains 103 */ 104 105 /* 106 * NB: 107 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 108 * we prefetch needs to be determined by the time spent in m_free vis a vis 109 * the cost of a prefetch. This will of course vary based on the workload: 110 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 111 * is quite expensive, thus suggesting very little prefetch. 112 * - small packet forwarding which is just returning a single mbuf to 113 * UMA will typically be very fast vis a vis the cost of a memory 114 * access. 115 */ 116 117 118 /* 119 * File organization: 120 * - private structures 121 * - iflib private utility functions 122 * - ifnet functions 123 * - vlan registry and other exported functions 124 * - iflib public core functions 125 * 126 * 127 */ 128 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 129 130 struct iflib_txq; 131 typedef struct iflib_txq *iflib_txq_t; 132 struct iflib_rxq; 133 typedef struct iflib_rxq *iflib_rxq_t; 134 struct iflib_fl; 135 typedef struct iflib_fl *iflib_fl_t; 136 137 struct iflib_ctx; 138 139 typedef struct iflib_filter_info { 140 driver_filter_t *ifi_filter; 141 void *ifi_filter_arg; 142 struct grouptask *ifi_task; 143 void *ifi_ctx; 144 } *iflib_filter_info_t; 145 146 struct iflib_ctx { 147 KOBJ_FIELDS; 148 /* 149 * Pointer to hardware driver's softc 150 */ 151 void *ifc_softc; 152 device_t ifc_dev; 153 if_t ifc_ifp; 154 155 cpuset_t ifc_cpus; 156 if_shared_ctx_t ifc_sctx; 157 struct if_softc_ctx ifc_softc_ctx; 158 159 struct mtx ifc_mtx; 160 161 uint16_t ifc_nhwtxqs; 162 uint16_t ifc_nhwrxqs; 163 164 iflib_txq_t ifc_txqs; 165 iflib_rxq_t ifc_rxqs; 166 uint32_t ifc_if_flags; 167 uint32_t ifc_flags; 168 uint32_t ifc_max_fl_buf_size; 169 int ifc_in_detach; 170 171 int ifc_link_state; 172 int ifc_link_irq; 173 int ifc_watchdog_events; 174 struct cdev *ifc_led_dev; 175 struct resource *ifc_msix_mem; 176 177 struct if_irq ifc_legacy_irq; 178 struct grouptask ifc_admin_task; 179 struct grouptask ifc_vflr_task; 180 struct iflib_filter_info ifc_filter_info; 181 struct ifmedia ifc_media; 182 183 struct sysctl_oid *ifc_sysctl_node; 184 uint16_t ifc_sysctl_ntxqs; 185 uint16_t ifc_sysctl_nrxqs; 186 uint16_t ifc_sysctl_qs_eq_override; 187 188 qidx_t ifc_sysctl_ntxds[8]; 189 qidx_t ifc_sysctl_nrxds[8]; 190 struct if_txrx ifc_txrx; 191 #define isc_txd_encap ifc_txrx.ift_txd_encap 192 #define isc_txd_flush ifc_txrx.ift_txd_flush 193 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 194 #define isc_rxd_available ifc_txrx.ift_rxd_available 195 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 196 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 197 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 198 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 199 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 200 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 201 eventhandler_tag ifc_vlan_attach_event; 202 eventhandler_tag ifc_vlan_detach_event; 203 uint8_t ifc_mac[ETHER_ADDR_LEN]; 204 char ifc_mtx_name[16]; 205 }; 206 207 208 void * 209 iflib_get_softc(if_ctx_t ctx) 210 { 211 212 return (ctx->ifc_softc); 213 } 214 215 device_t 216 iflib_get_dev(if_ctx_t ctx) 217 { 218 219 return (ctx->ifc_dev); 220 } 221 222 if_t 223 iflib_get_ifp(if_ctx_t ctx) 224 { 225 226 return (ctx->ifc_ifp); 227 } 228 229 struct ifmedia * 230 iflib_get_media(if_ctx_t ctx) 231 { 232 233 return (&ctx->ifc_media); 234 } 235 236 void 237 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 238 { 239 240 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 241 } 242 243 if_softc_ctx_t 244 iflib_get_softc_ctx(if_ctx_t ctx) 245 { 246 247 return (&ctx->ifc_softc_ctx); 248 } 249 250 if_shared_ctx_t 251 iflib_get_sctx(if_ctx_t ctx) 252 { 253 254 return (ctx->ifc_sctx); 255 } 256 257 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 258 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 259 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 260 261 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 262 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 263 264 #define RX_SW_DESC_MAP_CREATED (1 << 0) 265 #define TX_SW_DESC_MAP_CREATED (1 << 1) 266 #define RX_SW_DESC_INUSE (1 << 3) 267 #define TX_SW_DESC_MAPPED (1 << 4) 268 269 typedef struct iflib_sw_rx_desc_array { 270 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 271 struct mbuf **ifsd_m; /* pkthdr mbufs */ 272 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 273 uint8_t *ifsd_flags; 274 } iflib_rxsd_array_t; 275 276 typedef struct iflib_sw_tx_desc_array { 277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 278 struct mbuf **ifsd_m; /* pkthdr mbufs */ 279 uint8_t *ifsd_flags; 280 } if_txsd_vec_t; 281 282 283 /* magic number that should be high enough for any hardware */ 284 #define IFLIB_MAX_TX_SEGS 128 285 #define IFLIB_MAX_RX_SEGS 32 286 #define IFLIB_RX_COPY_THRESH 128 287 #define IFLIB_MAX_RX_REFRESH 32 288 /* The minimum descriptors per second before we start coalescing */ 289 #define IFLIB_MIN_DESC_SEC 16384 290 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 291 #define IFLIB_QUEUE_IDLE 0 292 #define IFLIB_QUEUE_HUNG 1 293 #define IFLIB_QUEUE_WORKING 2 294 /* maximum number of txqs that can share an rx interrupt */ 295 #define IFLIB_MAX_TX_SHARED_INTR 4 296 297 /* this should really scale with ring size - this is a fairly arbitrary value */ 298 #define TX_BATCH_SIZE 32 299 300 #define IFLIB_RESTART_BUDGET 8 301 302 #define IFC_LEGACY 0x001 303 #define IFC_QFLUSH 0x002 304 #define IFC_MULTISEG 0x004 305 #define IFC_DMAR 0x008 306 #define IFC_SC_ALLOCATED 0x010 307 #define IFC_INIT_DONE 0x020 308 #define IFC_PREFETCH 0x040 309 #define IFC_DO_RESET 0x080 310 #define IFC_CHECK_HUNG 0x100 311 312 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 313 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 314 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 315 struct iflib_txq { 316 qidx_t ift_in_use; 317 qidx_t ift_cidx; 318 qidx_t ift_cidx_processed; 319 qidx_t ift_pidx; 320 uint8_t ift_gen; 321 uint8_t ift_br_offset; 322 uint16_t ift_npending; 323 uint16_t ift_db_pending; 324 uint16_t ift_rs_pending; 325 /* implicit pad */ 326 uint8_t ift_txd_size[8]; 327 uint64_t ift_processed; 328 uint64_t ift_cleaned; 329 uint64_t ift_cleaned_prev; 330 #if MEMORY_LOGGING 331 uint64_t ift_enqueued; 332 uint64_t ift_dequeued; 333 #endif 334 uint64_t ift_no_tx_dma_setup; 335 uint64_t ift_no_desc_avail; 336 uint64_t ift_mbuf_defrag_failed; 337 uint64_t ift_mbuf_defrag; 338 uint64_t ift_map_failed; 339 uint64_t ift_txd_encap_efbig; 340 uint64_t ift_pullups; 341 342 struct mtx ift_mtx; 343 struct mtx ift_db_mtx; 344 345 /* constant values */ 346 if_ctx_t ift_ctx; 347 struct ifmp_ring *ift_br; 348 struct grouptask ift_task; 349 qidx_t ift_size; 350 uint16_t ift_id; 351 struct callout ift_timer; 352 353 if_txsd_vec_t ift_sds; 354 uint8_t ift_qstatus; 355 uint8_t ift_closed; 356 uint8_t ift_update_freq; 357 struct iflib_filter_info ift_filter_info; 358 bus_dma_tag_t ift_desc_tag; 359 bus_dma_tag_t ift_tso_desc_tag; 360 iflib_dma_info_t ift_ifdi; 361 #define MTX_NAME_LEN 16 362 char ift_mtx_name[MTX_NAME_LEN]; 363 char ift_db_mtx_name[MTX_NAME_LEN]; 364 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 365 #ifdef IFLIB_DIAGNOSTICS 366 uint64_t ift_cpu_exec_count[256]; 367 #endif 368 } __aligned(CACHE_LINE_SIZE); 369 370 struct iflib_fl { 371 qidx_t ifl_cidx; 372 qidx_t ifl_pidx; 373 qidx_t ifl_credits; 374 uint8_t ifl_gen; 375 uint8_t ifl_rxd_size; 376 #if MEMORY_LOGGING 377 uint64_t ifl_m_enqueued; 378 uint64_t ifl_m_dequeued; 379 uint64_t ifl_cl_enqueued; 380 uint64_t ifl_cl_dequeued; 381 #endif 382 /* implicit pad */ 383 384 /* constant */ 385 qidx_t ifl_size; 386 uint16_t ifl_buf_size; 387 uint16_t ifl_cltype; 388 uma_zone_t ifl_zone; 389 iflib_rxsd_array_t ifl_sds; 390 iflib_rxq_t ifl_rxq; 391 uint8_t ifl_id; 392 bus_dma_tag_t ifl_desc_tag; 393 iflib_dma_info_t ifl_ifdi; 394 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 395 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 396 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 397 } __aligned(CACHE_LINE_SIZE); 398 399 static inline qidx_t 400 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 401 { 402 qidx_t used; 403 404 if (pidx > cidx) 405 used = pidx - cidx; 406 else if (pidx < cidx) 407 used = size - cidx + pidx; 408 else if (gen == 0 && pidx == cidx) 409 used = 0; 410 else if (gen == 1 && pidx == cidx) 411 used = size; 412 else 413 panic("bad state"); 414 415 return (used); 416 } 417 418 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 419 420 #define IDXDIFF(head, tail, wrap) \ 421 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 422 423 struct iflib_rxq { 424 /* If there is a separate completion queue - 425 * these are the cq cidx and pidx. Otherwise 426 * these are unused. 427 */ 428 qidx_t ifr_size; 429 qidx_t ifr_cq_cidx; 430 qidx_t ifr_cq_pidx; 431 uint8_t ifr_cq_gen; 432 uint8_t ifr_fl_offset; 433 434 if_ctx_t ifr_ctx; 435 iflib_fl_t ifr_fl; 436 uint64_t ifr_rx_irq; 437 uint16_t ifr_id; 438 uint8_t ifr_lro_enabled; 439 uint8_t ifr_nfl; 440 uint8_t ifr_ntxqirq; 441 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 442 struct lro_ctrl ifr_lc; 443 struct grouptask ifr_task; 444 struct iflib_filter_info ifr_filter_info; 445 iflib_dma_info_t ifr_ifdi; 446 447 /* dynamically allocate if any drivers need a value substantially larger than this */ 448 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 449 #ifdef IFLIB_DIAGNOSTICS 450 uint64_t ifr_cpu_exec_count[256]; 451 #endif 452 } __aligned(CACHE_LINE_SIZE); 453 454 typedef struct if_rxsd { 455 caddr_t *ifsd_cl; 456 struct mbuf **ifsd_m; 457 iflib_fl_t ifsd_fl; 458 qidx_t ifsd_cidx; 459 } *if_rxsd_t; 460 461 /* multiple of word size */ 462 #ifdef __LP64__ 463 #define PKT_INFO_SIZE 6 464 #define RXD_INFO_SIZE 5 465 #define PKT_TYPE uint64_t 466 #else 467 #define PKT_INFO_SIZE 11 468 #define RXD_INFO_SIZE 8 469 #define PKT_TYPE uint32_t 470 #endif 471 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 472 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 473 474 typedef struct if_pkt_info_pad { 475 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 476 } *if_pkt_info_pad_t; 477 typedef struct if_rxd_info_pad { 478 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 479 } *if_rxd_info_pad_t; 480 481 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 482 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 483 484 485 static inline void 486 pkt_info_zero(if_pkt_info_t pi) 487 { 488 if_pkt_info_pad_t pi_pad; 489 490 pi_pad = (if_pkt_info_pad_t)pi; 491 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 492 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 493 #ifndef __LP64__ 494 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 495 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 496 #endif 497 } 498 499 static inline void 500 rxd_info_zero(if_rxd_info_t ri) 501 { 502 if_rxd_info_pad_t ri_pad; 503 int i; 504 505 ri_pad = (if_rxd_info_pad_t)ri; 506 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 507 ri_pad->rxd_val[i] = 0; 508 ri_pad->rxd_val[i+1] = 0; 509 ri_pad->rxd_val[i+2] = 0; 510 ri_pad->rxd_val[i+3] = 0; 511 } 512 #ifdef __LP64__ 513 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 514 #endif 515 } 516 517 /* 518 * Only allow a single packet to take up most 1/nth of the tx ring 519 */ 520 #define MAX_SINGLE_PACKET_FRACTION 12 521 #define IF_BAD_DMA (bus_addr_t)-1 522 523 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 524 "iflib driver parameters"); 525 526 static int iflib_timer_int; 527 SYSCTL_INT(_net_iflib, OID_AUTO, timer_int, CTLFLAG_RW, &iflib_timer_int, 528 0, "interval at which to run per-queue timers (in ticks)"); 529 530 static int force_busdma = 1; 531 SYSCTL_INT(_net_iflib, OID_AUTO, force_busdma, CTLFLAG_RDTUN, &force_busdma, 532 1, "force busdma"); 533 534 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 535 536 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF) 537 538 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx) 539 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx) 540 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx) 541 542 543 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 544 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 545 546 547 /* Our boot-time initialization hook */ 548 static int iflib_module_event_handler(module_t, int, void *); 549 550 static moduledata_t iflib_moduledata = { 551 "iflib", 552 iflib_module_event_handler, 553 NULL 554 }; 555 556 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 557 MODULE_VERSION(iflib, 1); 558 559 MODULE_DEPEND(iflib, pci, 1, 1, 1); 560 MODULE_DEPEND(iflib, ether, 1, 1, 1); 561 562 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 563 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 564 565 #ifndef IFLIB_DEBUG_COUNTERS 566 #ifdef INVARIANTS 567 #define IFLIB_DEBUG_COUNTERS 1 568 #else 569 #define IFLIB_DEBUG_COUNTERS 0 570 #endif /* !INVARIANTS */ 571 #endif 572 573 /* 574 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 575 */ 576 static int iflib_min_tx_latency = 0; 577 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 578 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 579 static int iflib_no_tx_batch = 0; 580 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 581 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 582 583 584 #if IFLIB_DEBUG_COUNTERS 585 586 static int iflib_tx_seen; 587 static int iflib_tx_sent; 588 static int iflib_tx_encap; 589 static int iflib_rx_allocs; 590 static int iflib_fl_refills; 591 static int iflib_fl_refills_large; 592 static int iflib_tx_frees; 593 594 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 595 &iflib_tx_seen, 0, "# tx mbufs seen"); 596 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 597 &iflib_tx_sent, 0, "# tx mbufs sent"); 598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 599 &iflib_tx_encap, 0, "# tx mbufs encapped"); 600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 601 &iflib_tx_frees, 0, "# tx frees"); 602 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 603 &iflib_rx_allocs, 0, "# rx allocations"); 604 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 605 &iflib_fl_refills, 0, "# refills"); 606 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 607 &iflib_fl_refills_large, 0, "# large refills"); 608 609 610 static int iflib_txq_drain_flushing; 611 static int iflib_txq_drain_oactive; 612 static int iflib_txq_drain_notready; 613 static int iflib_txq_drain_encapfail; 614 615 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 616 &iflib_txq_drain_flushing, 0, "# drain flushes"); 617 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 618 &iflib_txq_drain_oactive, 0, "# drain oactives"); 619 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 620 &iflib_txq_drain_notready, 0, "# drain notready"); 621 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 622 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 623 624 625 static int iflib_encap_load_mbuf_fail; 626 static int iflib_encap_txq_avail_fail; 627 static int iflib_encap_txd_encap_fail; 628 629 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 630 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 632 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 634 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 635 636 static int iflib_task_fn_rxs; 637 static int iflib_rx_intr_enables; 638 static int iflib_fast_intrs; 639 static int iflib_intr_link; 640 static int iflib_intr_msix; 641 static int iflib_rx_unavail; 642 static int iflib_rx_ctx_inactive; 643 static int iflib_rx_zero_len; 644 static int iflib_rx_if_input; 645 static int iflib_rx_mbuf_null; 646 static int iflib_rxd_flush; 647 648 static int iflib_verbose_debug; 649 650 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 651 &iflib_intr_link, 0, "# intr link calls"); 652 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 653 &iflib_intr_msix, 0, "# intr msix calls"); 654 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 655 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 657 &iflib_rx_intr_enables, 0, "# rx intr enables"); 658 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 659 &iflib_fast_intrs, 0, "# fast_intr calls"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 661 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 663 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 665 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 666 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 667 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 668 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 669 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 670 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 671 &iflib_rxd_flush, 0, "# times rxd_flush called"); 672 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 673 &iflib_verbose_debug, 0, "enable verbose debugging"); 674 675 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 676 static void 677 iflib_debug_reset(void) 678 { 679 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 680 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 681 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 682 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 683 iflib_encap_load_mbuf_fail = iflib_encap_txq_avail_fail = 684 iflib_encap_txd_encap_fail = iflib_task_fn_rxs = iflib_rx_intr_enables = 685 iflib_fast_intrs = iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 686 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 687 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 688 } 689 690 #else 691 #define DBG_COUNTER_INC(name) 692 static void iflib_debug_reset(void) {} 693 #endif 694 695 696 697 #define IFLIB_DEBUG 0 698 699 static void iflib_tx_structures_free(if_ctx_t ctx); 700 static void iflib_rx_structures_free(if_ctx_t ctx); 701 static int iflib_queues_alloc(if_ctx_t ctx); 702 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 703 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 704 static int iflib_qset_structures_setup(if_ctx_t ctx); 705 static int iflib_msix_init(if_ctx_t ctx); 706 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str); 707 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 708 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 709 static int iflib_register(if_ctx_t); 710 static void iflib_init_locked(if_ctx_t ctx); 711 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 712 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 713 static void iflib_ifmp_purge(iflib_txq_t txq); 714 static void _iflib_pre_assert(if_softc_ctx_t scctx); 715 static void iflib_stop(if_ctx_t ctx); 716 static void iflib_if_init_locked(if_ctx_t ctx); 717 #ifndef __NO_STRICT_ALIGNMENT 718 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 719 #endif 720 721 #ifdef DEV_NETMAP 722 #include <sys/selinfo.h> 723 #include <net/netmap.h> 724 #include <dev/netmap/netmap_kern.h> 725 726 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 727 728 /* 729 * device-specific sysctl variables: 730 * 731 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 732 * During regular operations the CRC is stripped, but on some 733 * hardware reception of frames not multiple of 64 is slower, 734 * so using crcstrip=0 helps in benchmarks. 735 * 736 * iflib_rx_miss, iflib_rx_miss_bufs: 737 * count packets that might be missed due to lost interrupts. 738 */ 739 SYSCTL_DECL(_dev_netmap); 740 /* 741 * The xl driver by default strips CRCs and we do not override it. 742 */ 743 744 int iflib_crcstrip = 1; 745 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 746 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 747 748 int iflib_rx_miss, iflib_rx_miss_bufs; 749 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 750 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 751 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 752 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 753 754 /* 755 * Register/unregister. We are already under netmap lock. 756 * Only called on the first register or the last unregister. 757 */ 758 static int 759 iflib_netmap_register(struct netmap_adapter *na, int onoff) 760 { 761 struct ifnet *ifp = na->ifp; 762 if_ctx_t ctx = ifp->if_softc; 763 int status; 764 765 CTX_LOCK(ctx); 766 IFDI_INTR_DISABLE(ctx); 767 768 /* Tell the stack that the interface is no longer active */ 769 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 770 771 if (!CTX_IS_VF(ctx)) 772 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 773 774 /* enable or disable flags and callbacks in na and ifp */ 775 if (onoff) { 776 nm_set_native_flags(na); 777 } else { 778 nm_clear_native_flags(na); 779 } 780 iflib_stop(ctx); 781 iflib_init_locked(ctx); 782 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 783 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 784 if (status) 785 nm_clear_native_flags(na); 786 CTX_UNLOCK(ctx); 787 return (status); 788 } 789 790 /* 791 * Reconcile kernel and user view of the transmit ring. 792 * 793 * All information is in the kring. 794 * Userspace wants to send packets up to the one before kring->rhead, 795 * kernel knows kring->nr_hwcur is the first unsent packet. 796 * 797 * Here we push packets out (as many as possible), and possibly 798 * reclaim buffers from previously completed transmission. 799 * 800 * The caller (netmap) guarantees that there is only one instance 801 * running at any time. Any interference with other driver 802 * methods should be handled by the individual drivers. 803 */ 804 static int 805 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 806 { 807 struct netmap_adapter *na = kring->na; 808 struct ifnet *ifp = na->ifp; 809 struct netmap_ring *ring = kring->ring; 810 u_int nm_i; /* index into the netmap ring */ 811 u_int nic_i; /* index into the NIC ring */ 812 u_int n; 813 u_int const lim = kring->nkr_num_slots - 1; 814 u_int const head = kring->rhead; 815 struct if_pkt_info pi; 816 817 /* 818 * interrupts on every tx packet are expensive so request 819 * them every half ring, or where NS_REPORT is set 820 */ 821 u_int report_frequency = kring->nkr_num_slots >> 1; 822 /* device-specific */ 823 if_ctx_t ctx = ifp->if_softc; 824 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 825 826 if (txq->ift_sds.ifsd_map) 827 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 828 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 829 830 831 /* 832 * First part: process new packets to send. 833 * nm_i is the current index in the netmap ring, 834 * nic_i is the corresponding index in the NIC ring. 835 * 836 * If we have packets to send (nm_i != head) 837 * iterate over the netmap ring, fetch length and update 838 * the corresponding slot in the NIC ring. Some drivers also 839 * need to update the buffer's physical address in the NIC slot 840 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 841 * 842 * The netmap_reload_map() calls is especially expensive, 843 * even when (as in this case) the tag is 0, so do only 844 * when the buffer has actually changed. 845 * 846 * If possible do not set the report/intr bit on all slots, 847 * but only a few times per ring or when NS_REPORT is set. 848 * 849 * Finally, on 10G and faster drivers, it might be useful 850 * to prefetch the next slot and txr entry. 851 */ 852 853 nm_i = kring->nr_hwcur; 854 pkt_info_zero(&pi); 855 pi.ipi_segs = txq->ift_segs; 856 pi.ipi_qsidx = kring->ring_id; 857 if (nm_i != head) { /* we have new packets to send */ 858 nic_i = netmap_idx_k2n(kring, nm_i); 859 860 __builtin_prefetch(&ring->slot[nm_i]); 861 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 862 if (txq->ift_sds.ifsd_map) 863 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 864 865 for (n = 0; nm_i != head; n++) { 866 struct netmap_slot *slot = &ring->slot[nm_i]; 867 u_int len = slot->len; 868 uint64_t paddr; 869 void *addr = PNMB(na, slot, &paddr); 870 int flags = (slot->flags & NS_REPORT || 871 nic_i == 0 || nic_i == report_frequency) ? 872 IPI_TX_INTR : 0; 873 874 /* device-specific */ 875 pi.ipi_len = len; 876 pi.ipi_segs[0].ds_addr = paddr; 877 pi.ipi_segs[0].ds_len = len; 878 pi.ipi_nsegs = 1; 879 pi.ipi_ndescs = 0; 880 pi.ipi_pidx = nic_i; 881 pi.ipi_flags = flags; 882 883 /* Fill the slot in the NIC ring. */ 884 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 885 886 /* prefetch for next round */ 887 __builtin_prefetch(&ring->slot[nm_i + 1]); 888 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 889 if (txq->ift_sds.ifsd_map) { 890 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 891 892 NM_CHECK_ADDR_LEN(na, addr, len); 893 894 if (slot->flags & NS_BUF_CHANGED) { 895 /* buffer has changed, reload map */ 896 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 897 } 898 /* make sure changes to the buffer are synced */ 899 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 900 BUS_DMASYNC_PREWRITE); 901 } 902 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 903 nm_i = nm_next(nm_i, lim); 904 nic_i = nm_next(nic_i, lim); 905 } 906 kring->nr_hwcur = head; 907 908 /* synchronize the NIC ring */ 909 if (txq->ift_sds.ifsd_map) 910 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 911 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 912 913 /* (re)start the tx unit up to slot nic_i (excluded) */ 914 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 915 } 916 917 /* 918 * Second part: reclaim buffers for completed transmissions. 919 */ 920 if (iflib_tx_credits_update(ctx, txq)) { 921 /* some tx completed, increment avail */ 922 nic_i = txq->ift_cidx_processed; 923 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 924 } 925 return (0); 926 } 927 928 /* 929 * Reconcile kernel and user view of the receive ring. 930 * Same as for the txsync, this routine must be efficient. 931 * The caller guarantees a single invocations, but races against 932 * the rest of the driver should be handled here. 933 * 934 * On call, kring->rhead is the first packet that userspace wants 935 * to keep, and kring->rcur is the wakeup point. 936 * The kernel has previously reported packets up to kring->rtail. 937 * 938 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 939 * of whether or not we received an interrupt. 940 */ 941 static int 942 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 943 { 944 struct netmap_adapter *na = kring->na; 945 struct netmap_ring *ring = kring->ring; 946 uint32_t nm_i; /* index into the netmap ring */ 947 uint32_t nic_i, nic_i_start; /* index into the NIC ring */ 948 u_int i, n; 949 u_int const lim = kring->nkr_num_slots - 1; 950 u_int const head = kring->rhead; 951 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 952 struct if_rxd_info ri; 953 struct if_rxd_update iru; 954 955 struct ifnet *ifp = na->ifp; 956 if_ctx_t ctx = ifp->if_softc; 957 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 958 iflib_fl_t fl = rxq->ifr_fl; 959 if (head > lim) 960 return netmap_ring_reinit(kring); 961 962 /* XXX check sync modes */ 963 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 964 if (fl->ifl_sds.ifsd_map == NULL) 965 continue; 966 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 967 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 968 } 969 /* 970 * First part: import newly received packets. 971 * 972 * nm_i is the index of the next free slot in the netmap ring, 973 * nic_i is the index of the next received packet in the NIC ring, 974 * and they may differ in case if_init() has been called while 975 * in netmap mode. For the receive ring we have 976 * 977 * nic_i = rxr->next_check; 978 * nm_i = kring->nr_hwtail (previous) 979 * and 980 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 981 * 982 * rxr->next_check is set to 0 on a ring reinit 983 */ 984 if (netmap_no_pendintr || force_update) { 985 int crclen = iflib_crcstrip ? 0 : 4; 986 int error, avail; 987 uint16_t slot_flags = kring->nkr_slot_flags; 988 989 for (fl = rxq->ifr_fl, i = 0; i < rxq->ifr_nfl; i++, fl++) { 990 nic_i = fl->ifl_cidx; 991 nm_i = netmap_idx_n2k(kring, nic_i); 992 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 993 for (n = 0; avail > 0; n++, avail--) { 994 rxd_info_zero(&ri); 995 ri.iri_frags = rxq->ifr_frags; 996 ri.iri_qsidx = kring->ring_id; 997 ri.iri_ifp = ctx->ifc_ifp; 998 ri.iri_cidx = nic_i; 999 1000 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1001 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1002 ring->slot[nm_i].flags = slot_flags; 1003 if (fl->ifl_sds.ifsd_map) 1004 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1005 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1006 nm_i = nm_next(nm_i, lim); 1007 nic_i = nm_next(nic_i, lim); 1008 } 1009 if (n) { /* update the state variables */ 1010 if (netmap_no_pendintr && !force_update) { 1011 /* diagnostics */ 1012 iflib_rx_miss ++; 1013 iflib_rx_miss_bufs += n; 1014 } 1015 fl->ifl_cidx = nic_i; 1016 kring->nr_hwtail = nm_i; 1017 } 1018 kring->nr_kflags &= ~NKR_PENDINTR; 1019 } 1020 } 1021 /* 1022 * Second part: skip past packets that userspace has released. 1023 * (kring->nr_hwcur to head excluded), 1024 * and make the buffers available for reception. 1025 * As usual nm_i is the index in the netmap ring, 1026 * nic_i is the index in the NIC ring, and 1027 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1028 */ 1029 /* XXX not sure how this will work with multiple free lists */ 1030 nm_i = kring->nr_hwcur; 1031 if (nm_i == head) 1032 return (0); 1033 1034 iru.iru_paddrs = fl->ifl_bus_addrs; 1035 iru.iru_vaddrs = &fl->ifl_vm_addrs[0]; 1036 iru.iru_idxs = fl->ifl_rxd_idxs; 1037 iru.iru_qsidx = rxq->ifr_id; 1038 iru.iru_buf_size = fl->ifl_buf_size; 1039 iru.iru_flidx = fl->ifl_id; 1040 nic_i_start = nic_i = netmap_idx_k2n(kring, nm_i); 1041 for (i = 0; nm_i != head; i++) { 1042 struct netmap_slot *slot = &ring->slot[nm_i]; 1043 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[i]); 1044 1045 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 1046 goto ring_reset; 1047 1048 fl->ifl_vm_addrs[i] = addr; 1049 if (fl->ifl_sds.ifsd_map && (slot->flags & NS_BUF_CHANGED)) { 1050 /* buffer has changed, reload map */ 1051 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i], addr); 1052 } 1053 slot->flags &= ~NS_BUF_CHANGED; 1054 1055 nm_i = nm_next(nm_i, lim); 1056 fl->ifl_rxd_idxs[i] = nic_i = nm_next(nic_i, lim); 1057 if (nm_i != head && i < IFLIB_MAX_RX_REFRESH) 1058 continue; 1059 1060 iru.iru_pidx = nic_i_start; 1061 iru.iru_count = i; 1062 i = 0; 1063 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1064 if (fl->ifl_sds.ifsd_map == NULL) { 1065 nic_i_start = nic_i; 1066 continue; 1067 } 1068 nic_i = nic_i_start; 1069 for (n = 0; n < iru.iru_count; n++) { 1070 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_sds.ifsd_map[nic_i], 1071 BUS_DMASYNC_PREREAD); 1072 nic_i = nm_next(nic_i, lim); 1073 } 1074 nic_i_start = nic_i; 1075 } 1076 kring->nr_hwcur = head; 1077 1078 if (fl->ifl_sds.ifsd_map) 1079 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1080 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1081 /* 1082 * IMPORTANT: we must leave one free slot in the ring, 1083 * so move nic_i back by one unit 1084 */ 1085 nic_i = nm_prev(nic_i, lim); 1086 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 1087 return 0; 1088 1089 ring_reset: 1090 return netmap_ring_reinit(kring); 1091 } 1092 1093 static void 1094 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1095 { 1096 struct ifnet *ifp = na->ifp; 1097 if_ctx_t ctx = ifp->if_softc; 1098 1099 CTX_LOCK(ctx); 1100 if (onoff) { 1101 IFDI_INTR_ENABLE(ctx); 1102 } else { 1103 IFDI_INTR_DISABLE(ctx); 1104 } 1105 CTX_UNLOCK(ctx); 1106 } 1107 1108 1109 static int 1110 iflib_netmap_attach(if_ctx_t ctx) 1111 { 1112 struct netmap_adapter na; 1113 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1114 1115 bzero(&na, sizeof(na)); 1116 1117 na.ifp = ctx->ifc_ifp; 1118 na.na_flags = NAF_BDG_MAYSLEEP; 1119 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1120 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1121 1122 na.num_tx_desc = scctx->isc_ntxd[0]; 1123 na.num_rx_desc = scctx->isc_nrxd[0]; 1124 na.nm_txsync = iflib_netmap_txsync; 1125 na.nm_rxsync = iflib_netmap_rxsync; 1126 na.nm_register = iflib_netmap_register; 1127 na.nm_intr = iflib_netmap_intr; 1128 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1129 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1130 return (netmap_attach(&na)); 1131 } 1132 1133 static void 1134 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1135 { 1136 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1137 struct netmap_slot *slot; 1138 1139 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1140 if (slot == NULL) 1141 return; 1142 if (txq->ift_sds.ifsd_map == NULL) 1143 return; 1144 1145 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1146 1147 /* 1148 * In netmap mode, set the map for the packet buffer. 1149 * NOTE: Some drivers (not this one) also need to set 1150 * the physical buffer address in the NIC ring. 1151 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1152 * netmap slot index, si 1153 */ 1154 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i); 1155 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1156 } 1157 } 1158 static void 1159 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1160 { 1161 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1162 struct netmap_slot *slot; 1163 struct if_rxd_update iru; 1164 iflib_fl_t fl; 1165 bus_dmamap_t *map; 1166 int nrxd; 1167 uint32_t i, j, pidx_start; 1168 1169 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1170 if (slot == NULL) 1171 return; 1172 fl = &rxq->ifr_fl[0]; 1173 map = fl->ifl_sds.ifsd_map; 1174 nrxd = ctx->ifc_softc_ctx.isc_nrxd[0]; 1175 iru.iru_paddrs = fl->ifl_bus_addrs; 1176 iru.iru_vaddrs = &fl->ifl_vm_addrs[0]; 1177 iru.iru_idxs = fl->ifl_rxd_idxs; 1178 iru.iru_qsidx = rxq->ifr_id; 1179 iru.iru_buf_size = rxq->ifr_fl[0].ifl_buf_size; 1180 iru.iru_flidx = 0; 1181 1182 for (pidx_start = i = j = 0; i < nrxd; i++, j++) { 1183 int sj = netmap_idx_n2k(&na->rx_rings[rxq->ifr_id], i); 1184 void *addr; 1185 1186 fl->ifl_rxd_idxs[j] = i; 1187 addr = fl->ifl_vm_addrs[j] = PNMB(na, slot + sj, &fl->ifl_bus_addrs[j]); 1188 if (map) { 1189 netmap_load_map(na, rxq->ifr_fl[0].ifl_ifdi->idi_tag, *map, addr); 1190 map++; 1191 } 1192 1193 if (j < IFLIB_MAX_RX_REFRESH && i < nrxd - 1) 1194 continue; 1195 1196 iru.iru_pidx = pidx_start; 1197 pidx_start = i; 1198 iru.iru_count = j; 1199 j = 0; 1200 MPASS(pidx_start + j <= nrxd); 1201 /* Update descriptors and the cached value */ 1202 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1203 } 1204 /* preserve queue */ 1205 if (ctx->ifc_ifp->if_capenable & IFCAP_NETMAP) { 1206 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id]; 1207 int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring); 1208 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, t); 1209 } else 1210 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, nrxd-1); 1211 } 1212 1213 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1214 1215 #else 1216 #define iflib_netmap_txq_init(ctx, txq) 1217 #define iflib_netmap_rxq_init(ctx, rxq) 1218 #define iflib_netmap_detach(ifp) 1219 1220 #define iflib_netmap_attach(ctx) (0) 1221 #define netmap_rx_irq(ifp, qid, budget) (0) 1222 #define netmap_tx_irq(ifp, qid) do {} while (0) 1223 1224 #endif 1225 1226 #if defined(__i386__) || defined(__amd64__) 1227 static __inline void 1228 prefetch(void *x) 1229 { 1230 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1231 } 1232 #else 1233 #define prefetch(x) 1234 #endif 1235 1236 static void 1237 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1238 { 1239 if (err) 1240 return; 1241 *(bus_addr_t *) arg = segs[0].ds_addr; 1242 } 1243 1244 int 1245 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1246 { 1247 int err; 1248 if_shared_ctx_t sctx = ctx->ifc_sctx; 1249 device_t dev = ctx->ifc_dev; 1250 1251 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1252 1253 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1254 sctx->isc_q_align, 0, /* alignment, bounds */ 1255 BUS_SPACE_MAXADDR, /* lowaddr */ 1256 BUS_SPACE_MAXADDR, /* highaddr */ 1257 NULL, NULL, /* filter, filterarg */ 1258 size, /* maxsize */ 1259 1, /* nsegments */ 1260 size, /* maxsegsize */ 1261 BUS_DMA_ALLOCNOW, /* flags */ 1262 NULL, /* lockfunc */ 1263 NULL, /* lockarg */ 1264 &dma->idi_tag); 1265 if (err) { 1266 device_printf(dev, 1267 "%s: bus_dma_tag_create failed: %d\n", 1268 __func__, err); 1269 goto fail_0; 1270 } 1271 1272 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1273 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1274 if (err) { 1275 device_printf(dev, 1276 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1277 __func__, (uintmax_t)size, err); 1278 goto fail_1; 1279 } 1280 1281 dma->idi_paddr = IF_BAD_DMA; 1282 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1283 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1284 if (err || dma->idi_paddr == IF_BAD_DMA) { 1285 device_printf(dev, 1286 "%s: bus_dmamap_load failed: %d\n", 1287 __func__, err); 1288 goto fail_2; 1289 } 1290 1291 dma->idi_size = size; 1292 return (0); 1293 1294 fail_2: 1295 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1296 fail_1: 1297 bus_dma_tag_destroy(dma->idi_tag); 1298 fail_0: 1299 dma->idi_tag = NULL; 1300 1301 return (err); 1302 } 1303 1304 int 1305 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1306 { 1307 int i, err; 1308 iflib_dma_info_t *dmaiter; 1309 1310 dmaiter = dmalist; 1311 for (i = 0; i < count; i++, dmaiter++) { 1312 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1313 break; 1314 } 1315 if (err) 1316 iflib_dma_free_multi(dmalist, i); 1317 return (err); 1318 } 1319 1320 void 1321 iflib_dma_free(iflib_dma_info_t dma) 1322 { 1323 if (dma->idi_tag == NULL) 1324 return; 1325 if (dma->idi_paddr != IF_BAD_DMA) { 1326 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1327 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1328 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1329 dma->idi_paddr = IF_BAD_DMA; 1330 } 1331 if (dma->idi_vaddr != NULL) { 1332 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1333 dma->idi_vaddr = NULL; 1334 } 1335 bus_dma_tag_destroy(dma->idi_tag); 1336 dma->idi_tag = NULL; 1337 } 1338 1339 void 1340 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1341 { 1342 int i; 1343 iflib_dma_info_t *dmaiter = dmalist; 1344 1345 for (i = 0; i < count; i++, dmaiter++) 1346 iflib_dma_free(*dmaiter); 1347 } 1348 1349 #ifdef EARLY_AP_STARTUP 1350 static const int iflib_started = 1; 1351 #else 1352 /* 1353 * We used to abuse the smp_started flag to decide if the queues have been 1354 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1355 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1356 * is set. Run a SYSINIT() strictly after that to just set a usable 1357 * completion flag. 1358 */ 1359 1360 static int iflib_started; 1361 1362 static void 1363 iflib_record_started(void *arg) 1364 { 1365 iflib_started = 1; 1366 } 1367 1368 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1369 iflib_record_started, NULL); 1370 #endif 1371 1372 static int 1373 iflib_fast_intr(void *arg) 1374 { 1375 iflib_filter_info_t info = arg; 1376 struct grouptask *gtask = info->ifi_task; 1377 if (!iflib_started) 1378 return (FILTER_HANDLED); 1379 1380 DBG_COUNTER_INC(fast_intrs); 1381 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1382 return (FILTER_HANDLED); 1383 1384 GROUPTASK_ENQUEUE(gtask); 1385 return (FILTER_HANDLED); 1386 } 1387 1388 static int 1389 iflib_fast_intr_rxtx(void *arg) 1390 { 1391 iflib_filter_info_t info = arg; 1392 struct grouptask *gtask = info->ifi_task; 1393 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1394 if_ctx_t ctx; 1395 int i, cidx; 1396 1397 if (!iflib_started) 1398 return (FILTER_HANDLED); 1399 1400 DBG_COUNTER_INC(fast_intrs); 1401 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1402 return (FILTER_HANDLED); 1403 1404 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1405 qidx_t txqid = rxq->ifr_txqid[i]; 1406 1407 ctx = rxq->ifr_ctx; 1408 1409 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1410 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1411 continue; 1412 } 1413 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1414 } 1415 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1416 cidx = rxq->ifr_cq_cidx; 1417 else 1418 cidx = rxq->ifr_fl[0].ifl_cidx; 1419 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1420 GROUPTASK_ENQUEUE(gtask); 1421 else 1422 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1423 return (FILTER_HANDLED); 1424 } 1425 1426 1427 static int 1428 iflib_fast_intr_ctx(void *arg) 1429 { 1430 iflib_filter_info_t info = arg; 1431 struct grouptask *gtask = info->ifi_task; 1432 1433 if (!iflib_started) 1434 return (FILTER_HANDLED); 1435 1436 DBG_COUNTER_INC(fast_intrs); 1437 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1438 return (FILTER_HANDLED); 1439 1440 GROUPTASK_ENQUEUE(gtask); 1441 return (FILTER_HANDLED); 1442 } 1443 1444 static int 1445 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1446 driver_filter_t filter, driver_intr_t handler, void *arg, 1447 char *name) 1448 { 1449 int rc, flags; 1450 struct resource *res; 1451 void *tag = NULL; 1452 device_t dev = ctx->ifc_dev; 1453 1454 flags = RF_ACTIVE; 1455 if (ctx->ifc_flags & IFC_LEGACY) 1456 flags |= RF_SHAREABLE; 1457 MPASS(rid < 512); 1458 irq->ii_rid = rid; 1459 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1460 if (res == NULL) { 1461 device_printf(dev, 1462 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1463 return (ENOMEM); 1464 } 1465 irq->ii_res = res; 1466 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1467 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1468 filter, handler, arg, &tag); 1469 if (rc != 0) { 1470 device_printf(dev, 1471 "failed to setup interrupt for rid %d, name %s: %d\n", 1472 rid, name ? name : "unknown", rc); 1473 return (rc); 1474 } else if (name) 1475 bus_describe_intr(dev, res, tag, "%s", name); 1476 1477 irq->ii_tag = tag; 1478 return (0); 1479 } 1480 1481 1482 /********************************************************************* 1483 * 1484 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1485 * the information needed to transmit a packet on the wire. This is 1486 * called only once at attach, setup is done every reset. 1487 * 1488 **********************************************************************/ 1489 1490 static int 1491 iflib_txsd_alloc(iflib_txq_t txq) 1492 { 1493 if_ctx_t ctx = txq->ift_ctx; 1494 if_shared_ctx_t sctx = ctx->ifc_sctx; 1495 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1496 device_t dev = ctx->ifc_dev; 1497 int err, nsegments, ntsosegments; 1498 1499 nsegments = scctx->isc_tx_nsegments; 1500 ntsosegments = scctx->isc_tx_tso_segments_max; 1501 MPASS(scctx->isc_ntxd[0] > 0); 1502 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1503 MPASS(nsegments > 0); 1504 MPASS(ntsosegments > 0); 1505 /* 1506 * Setup DMA descriptor areas. 1507 */ 1508 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1509 1, 0, /* alignment, bounds */ 1510 BUS_SPACE_MAXADDR, /* lowaddr */ 1511 BUS_SPACE_MAXADDR, /* highaddr */ 1512 NULL, NULL, /* filter, filterarg */ 1513 sctx->isc_tx_maxsize, /* maxsize */ 1514 nsegments, /* nsegments */ 1515 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1516 0, /* flags */ 1517 NULL, /* lockfunc */ 1518 NULL, /* lockfuncarg */ 1519 &txq->ift_desc_tag))) { 1520 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1521 device_printf(dev,"maxsize: %zd nsegments: %d maxsegsize: %zd\n", 1522 sctx->isc_tx_maxsize, nsegments, sctx->isc_tx_maxsegsize); 1523 goto fail; 1524 } 1525 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1526 1, 0, /* alignment, bounds */ 1527 BUS_SPACE_MAXADDR, /* lowaddr */ 1528 BUS_SPACE_MAXADDR, /* highaddr */ 1529 NULL, NULL, /* filter, filterarg */ 1530 scctx->isc_tx_tso_size_max, /* maxsize */ 1531 ntsosegments, /* nsegments */ 1532 scctx->isc_tx_tso_segsize_max, /* maxsegsize */ 1533 0, /* flags */ 1534 NULL, /* lockfunc */ 1535 NULL, /* lockfuncarg */ 1536 &txq->ift_tso_desc_tag))) { 1537 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1538 1539 goto fail; 1540 } 1541 if (!(txq->ift_sds.ifsd_flags = 1542 (uint8_t *) malloc(sizeof(uint8_t) * 1543 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1544 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1545 err = ENOMEM; 1546 goto fail; 1547 } 1548 if (!(txq->ift_sds.ifsd_m = 1549 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1550 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1551 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1552 err = ENOMEM; 1553 goto fail; 1554 } 1555 1556 /* Create the descriptor buffer dma maps */ 1557 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1558 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1559 return (0); 1560 1561 if (!(txq->ift_sds.ifsd_map = 1562 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1563 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1564 err = ENOMEM; 1565 goto fail; 1566 } 1567 1568 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1569 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1570 if (err != 0) { 1571 device_printf(dev, "Unable to create TX DMA map\n"); 1572 goto fail; 1573 } 1574 } 1575 #endif 1576 return (0); 1577 fail: 1578 /* We free all, it handles case where we are in the middle */ 1579 iflib_tx_structures_free(ctx); 1580 return (err); 1581 } 1582 1583 static void 1584 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1585 { 1586 bus_dmamap_t map; 1587 1588 map = NULL; 1589 if (txq->ift_sds.ifsd_map != NULL) 1590 map = txq->ift_sds.ifsd_map[i]; 1591 if (map != NULL) { 1592 bus_dmamap_unload(txq->ift_desc_tag, map); 1593 bus_dmamap_destroy(txq->ift_desc_tag, map); 1594 txq->ift_sds.ifsd_map[i] = NULL; 1595 } 1596 } 1597 1598 static void 1599 iflib_txq_destroy(iflib_txq_t txq) 1600 { 1601 if_ctx_t ctx = txq->ift_ctx; 1602 1603 for (int i = 0; i < txq->ift_size; i++) 1604 iflib_txsd_destroy(ctx, txq, i); 1605 if (txq->ift_sds.ifsd_map != NULL) { 1606 free(txq->ift_sds.ifsd_map, M_IFLIB); 1607 txq->ift_sds.ifsd_map = NULL; 1608 } 1609 if (txq->ift_sds.ifsd_m != NULL) { 1610 free(txq->ift_sds.ifsd_m, M_IFLIB); 1611 txq->ift_sds.ifsd_m = NULL; 1612 } 1613 if (txq->ift_sds.ifsd_flags != NULL) { 1614 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1615 txq->ift_sds.ifsd_flags = NULL; 1616 } 1617 if (txq->ift_desc_tag != NULL) { 1618 bus_dma_tag_destroy(txq->ift_desc_tag); 1619 txq->ift_desc_tag = NULL; 1620 } 1621 if (txq->ift_tso_desc_tag != NULL) { 1622 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1623 txq->ift_tso_desc_tag = NULL; 1624 } 1625 } 1626 1627 static void 1628 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1629 { 1630 struct mbuf **mp; 1631 1632 mp = &txq->ift_sds.ifsd_m[i]; 1633 if (*mp == NULL) 1634 return; 1635 1636 if (txq->ift_sds.ifsd_map != NULL) { 1637 bus_dmamap_sync(txq->ift_desc_tag, 1638 txq->ift_sds.ifsd_map[i], 1639 BUS_DMASYNC_POSTWRITE); 1640 bus_dmamap_unload(txq->ift_desc_tag, 1641 txq->ift_sds.ifsd_map[i]); 1642 } 1643 m_free(*mp); 1644 DBG_COUNTER_INC(tx_frees); 1645 *mp = NULL; 1646 } 1647 1648 static int 1649 iflib_txq_setup(iflib_txq_t txq) 1650 { 1651 if_ctx_t ctx = txq->ift_ctx; 1652 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1653 iflib_dma_info_t di; 1654 int i; 1655 1656 /* Set number of descriptors available */ 1657 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1658 /* XXX make configurable */ 1659 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1660 1661 /* Reset indices */ 1662 txq->ift_cidx_processed = 0; 1663 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1664 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1665 1666 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1667 bzero((void *)di->idi_vaddr, di->idi_size); 1668 1669 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1670 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1671 bus_dmamap_sync(di->idi_tag, di->idi_map, 1672 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1673 return (0); 1674 } 1675 1676 /********************************************************************* 1677 * 1678 * Allocate memory for rx_buffer structures. Since we use one 1679 * rx_buffer per received packet, the maximum number of rx_buffer's 1680 * that we'll need is equal to the number of receive descriptors 1681 * that we've allocated. 1682 * 1683 **********************************************************************/ 1684 static int 1685 iflib_rxsd_alloc(iflib_rxq_t rxq) 1686 { 1687 if_ctx_t ctx = rxq->ifr_ctx; 1688 if_shared_ctx_t sctx = ctx->ifc_sctx; 1689 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1690 device_t dev = ctx->ifc_dev; 1691 iflib_fl_t fl; 1692 int err; 1693 1694 MPASS(scctx->isc_nrxd[0] > 0); 1695 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1696 1697 fl = rxq->ifr_fl; 1698 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1699 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1700 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1701 1, 0, /* alignment, bounds */ 1702 BUS_SPACE_MAXADDR, /* lowaddr */ 1703 BUS_SPACE_MAXADDR, /* highaddr */ 1704 NULL, NULL, /* filter, filterarg */ 1705 sctx->isc_rx_maxsize, /* maxsize */ 1706 sctx->isc_rx_nsegments, /* nsegments */ 1707 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1708 0, /* flags */ 1709 NULL, /* lockfunc */ 1710 NULL, /* lockarg */ 1711 &fl->ifl_desc_tag); 1712 if (err) { 1713 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1714 __func__, err); 1715 goto fail; 1716 } 1717 if (!(fl->ifl_sds.ifsd_flags = 1718 (uint8_t *) malloc(sizeof(uint8_t) * 1719 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1720 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1721 err = ENOMEM; 1722 goto fail; 1723 } 1724 if (!(fl->ifl_sds.ifsd_m = 1725 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1726 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1727 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1728 err = ENOMEM; 1729 goto fail; 1730 } 1731 if (!(fl->ifl_sds.ifsd_cl = 1732 (caddr_t *) malloc(sizeof(caddr_t) * 1733 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1734 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1735 err = ENOMEM; 1736 goto fail; 1737 } 1738 1739 /* Create the descriptor buffer dma maps */ 1740 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1741 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1742 continue; 1743 1744 if (!(fl->ifl_sds.ifsd_map = 1745 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1746 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1747 err = ENOMEM; 1748 goto fail; 1749 } 1750 1751 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1752 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1753 if (err != 0) { 1754 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1755 goto fail; 1756 } 1757 } 1758 #endif 1759 } 1760 return (0); 1761 1762 fail: 1763 iflib_rx_structures_free(ctx); 1764 return (err); 1765 } 1766 1767 1768 /* 1769 * Internal service routines 1770 */ 1771 1772 struct rxq_refill_cb_arg { 1773 int error; 1774 bus_dma_segment_t seg; 1775 int nseg; 1776 }; 1777 1778 static void 1779 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1780 { 1781 struct rxq_refill_cb_arg *cb_arg = arg; 1782 1783 cb_arg->error = error; 1784 cb_arg->seg = segs[0]; 1785 cb_arg->nseg = nseg; 1786 } 1787 1788 1789 #ifdef ACPI_DMAR 1790 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1791 #else 1792 #define IS_DMAR(ctx) (0) 1793 #endif 1794 1795 /** 1796 * rxq_refill - refill an rxq free-buffer list 1797 * @ctx: the iflib context 1798 * @rxq: the free-list to refill 1799 * @n: the number of new buffers to allocate 1800 * 1801 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1802 * The caller must assure that @n does not exceed the queue's capacity. 1803 */ 1804 static void 1805 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1806 { 1807 struct mbuf *m; 1808 int idx, pidx = fl->ifl_pidx; 1809 caddr_t cl, *sd_cl; 1810 struct mbuf **sd_m; 1811 uint8_t *sd_flags; 1812 struct if_rxd_update iru; 1813 bus_dmamap_t *sd_map; 1814 int n, i = 0; 1815 uint64_t bus_addr; 1816 int err; 1817 1818 sd_m = fl->ifl_sds.ifsd_m; 1819 sd_map = fl->ifl_sds.ifsd_map; 1820 sd_cl = fl->ifl_sds.ifsd_cl; 1821 sd_flags = fl->ifl_sds.ifsd_flags; 1822 idx = pidx; 1823 1824 n = count; 1825 MPASS(n > 0); 1826 MPASS(fl->ifl_credits + n <= fl->ifl_size); 1827 1828 if (pidx < fl->ifl_cidx) 1829 MPASS(pidx + n <= fl->ifl_cidx); 1830 if (pidx == fl->ifl_cidx && (fl->ifl_credits < fl->ifl_size)) 1831 MPASS(fl->ifl_gen == 0); 1832 if (pidx > fl->ifl_cidx) 1833 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1834 1835 DBG_COUNTER_INC(fl_refills); 1836 if (n > 8) 1837 DBG_COUNTER_INC(fl_refills_large); 1838 iru.iru_paddrs = fl->ifl_bus_addrs; 1839 iru.iru_vaddrs = &fl->ifl_vm_addrs[0]; 1840 iru.iru_idxs = fl->ifl_rxd_idxs; 1841 iru.iru_qsidx = fl->ifl_rxq->ifr_id; 1842 iru.iru_buf_size = fl->ifl_buf_size; 1843 iru.iru_flidx = fl->ifl_id; 1844 while (n--) { 1845 /* 1846 * We allocate an uninitialized mbuf + cluster, mbuf is 1847 * initialized after rx. 1848 * 1849 * If the cluster is still set then we know a minimum sized packet was received 1850 */ 1851 if ((cl = sd_cl[idx]) == NULL) { 1852 if ((cl = sd_cl[idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1853 break; 1854 #if MEMORY_LOGGING 1855 fl->ifl_cl_enqueued++; 1856 #endif 1857 } 1858 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1859 break; 1860 } 1861 #if MEMORY_LOGGING 1862 fl->ifl_m_enqueued++; 1863 #endif 1864 1865 DBG_COUNTER_INC(rx_allocs); 1866 #if defined(__i386__) || defined(__amd64__) 1867 if (!IS_DMAR(ctx)) { 1868 bus_addr = pmap_kextract((vm_offset_t)cl); 1869 } else 1870 #endif 1871 { 1872 struct rxq_refill_cb_arg cb_arg; 1873 iflib_rxq_t q; 1874 1875 cb_arg.error = 0; 1876 q = fl->ifl_rxq; 1877 MPASS(sd_map != NULL); 1878 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[idx], 1879 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1880 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[idx], BUS_DMASYNC_PREREAD); 1881 1882 if (err != 0 || cb_arg.error) { 1883 /* 1884 * !zone_pack ? 1885 */ 1886 if (fl->ifl_zone == zone_pack) 1887 uma_zfree(fl->ifl_zone, cl); 1888 m_free(m); 1889 n = 0; 1890 goto done; 1891 } 1892 bus_addr = cb_arg.seg.ds_addr; 1893 } 1894 sd_flags[idx] |= RX_SW_DESC_INUSE; 1895 1896 MPASS(sd_m[idx] == NULL); 1897 sd_cl[idx] = cl; 1898 sd_m[idx] = m; 1899 fl->ifl_rxd_idxs[i] = idx; 1900 fl->ifl_bus_addrs[i] = bus_addr; 1901 fl->ifl_vm_addrs[i] = cl; 1902 fl->ifl_credits++; 1903 i++; 1904 MPASS(fl->ifl_credits <= fl->ifl_size); 1905 if (++idx == fl->ifl_size) { 1906 fl->ifl_gen = 1; 1907 idx = 0; 1908 } 1909 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 1910 iru.iru_pidx = pidx; 1911 iru.iru_count = i; 1912 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1913 i = 0; 1914 pidx = idx; 1915 } 1916 fl->ifl_pidx = idx; 1917 1918 } 1919 done: 1920 DBG_COUNTER_INC(rxd_flush); 1921 if (fl->ifl_pidx == 0) 1922 pidx = fl->ifl_size - 1; 1923 else 1924 pidx = fl->ifl_pidx - 1; 1925 1926 if (sd_map) 1927 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1928 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1929 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 1930 } 1931 1932 static __inline void 1933 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 1934 { 1935 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 1936 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 1937 #ifdef INVARIANTS 1938 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 1939 #endif 1940 1941 MPASS(fl->ifl_credits <= fl->ifl_size); 1942 MPASS(reclaimable == delta); 1943 1944 if (reclaimable > 0) 1945 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 1946 } 1947 1948 static void 1949 iflib_fl_bufs_free(iflib_fl_t fl) 1950 { 1951 iflib_dma_info_t idi = fl->ifl_ifdi; 1952 uint32_t i; 1953 1954 for (i = 0; i < fl->ifl_size; i++) { 1955 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 1956 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 1957 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 1958 1959 if (*sd_flags & RX_SW_DESC_INUSE) { 1960 if (fl->ifl_sds.ifsd_map != NULL) { 1961 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 1962 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 1963 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 1964 } 1965 if (*sd_m != NULL) { 1966 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 1967 uma_zfree(zone_mbuf, *sd_m); 1968 } 1969 if (*sd_cl != NULL) 1970 uma_zfree(fl->ifl_zone, *sd_cl); 1971 *sd_flags = 0; 1972 } else { 1973 MPASS(*sd_cl == NULL); 1974 MPASS(*sd_m == NULL); 1975 } 1976 #if MEMORY_LOGGING 1977 fl->ifl_m_dequeued++; 1978 fl->ifl_cl_dequeued++; 1979 #endif 1980 *sd_cl = NULL; 1981 *sd_m = NULL; 1982 } 1983 #ifdef INVARIANTS 1984 for (i = 0; i < fl->ifl_size; i++) { 1985 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 1986 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 1987 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 1988 } 1989 #endif 1990 /* 1991 * Reset free list values 1992 */ 1993 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = 0;; 1994 bzero(idi->idi_vaddr, idi->idi_size); 1995 } 1996 1997 /********************************************************************* 1998 * 1999 * Initialize a receive ring and its buffers. 2000 * 2001 **********************************************************************/ 2002 static int 2003 iflib_fl_setup(iflib_fl_t fl) 2004 { 2005 iflib_rxq_t rxq = fl->ifl_rxq; 2006 if_ctx_t ctx = rxq->ifr_ctx; 2007 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2008 2009 /* 2010 ** Free current RX buffer structs and their mbufs 2011 */ 2012 iflib_fl_bufs_free(fl); 2013 /* Now replenish the mbufs */ 2014 MPASS(fl->ifl_credits == 0); 2015 /* 2016 * XXX don't set the max_frame_size to larger 2017 * than the hardware can handle 2018 */ 2019 if (sctx->isc_max_frame_size <= 2048) 2020 fl->ifl_buf_size = MCLBYTES; 2021 #ifndef CONTIGMALLOC_WORKS 2022 else 2023 fl->ifl_buf_size = MJUMPAGESIZE; 2024 #else 2025 else if (sctx->isc_max_frame_size <= 4096) 2026 fl->ifl_buf_size = MJUMPAGESIZE; 2027 else if (sctx->isc_max_frame_size <= 9216) 2028 fl->ifl_buf_size = MJUM9BYTES; 2029 else 2030 fl->ifl_buf_size = MJUM16BYTES; 2031 #endif 2032 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2033 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2034 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2035 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2036 2037 2038 /* avoid pre-allocating zillions of clusters to an idle card 2039 * potentially speeding up attach 2040 */ 2041 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2042 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2043 if (min(128, fl->ifl_size) != fl->ifl_credits) 2044 return (ENOBUFS); 2045 /* 2046 * handle failure 2047 */ 2048 MPASS(rxq != NULL); 2049 MPASS(fl->ifl_ifdi != NULL); 2050 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2051 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2052 return (0); 2053 } 2054 2055 /********************************************************************* 2056 * 2057 * Free receive ring data structures 2058 * 2059 **********************************************************************/ 2060 static void 2061 iflib_rx_sds_free(iflib_rxq_t rxq) 2062 { 2063 iflib_fl_t fl; 2064 int i; 2065 2066 if (rxq->ifr_fl != NULL) { 2067 for (i = 0; i < rxq->ifr_nfl; i++) { 2068 fl = &rxq->ifr_fl[i]; 2069 if (fl->ifl_desc_tag != NULL) { 2070 bus_dma_tag_destroy(fl->ifl_desc_tag); 2071 fl->ifl_desc_tag = NULL; 2072 } 2073 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2074 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2075 /* XXX destroy maps first */ 2076 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2077 fl->ifl_sds.ifsd_m = NULL; 2078 fl->ifl_sds.ifsd_cl = NULL; 2079 fl->ifl_sds.ifsd_map = NULL; 2080 } 2081 free(rxq->ifr_fl, M_IFLIB); 2082 rxq->ifr_fl = NULL; 2083 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2084 } 2085 } 2086 2087 /* 2088 * MI independent logic 2089 * 2090 */ 2091 static void 2092 iflib_timer(void *arg) 2093 { 2094 iflib_txq_t txq = arg; 2095 if_ctx_t ctx = txq->ift_ctx; 2096 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2097 2098 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2099 return; 2100 /* 2101 ** Check on the state of the TX queue(s), this 2102 ** can be done without the lock because its RO 2103 ** and the HUNG state will be static if set. 2104 */ 2105 IFDI_TIMER(ctx, txq->ift_id); 2106 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2107 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2108 (sctx->isc_pause_frames == 0))) 2109 goto hung; 2110 2111 if (ifmp_ring_is_stalled(txq->ift_br)) 2112 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2113 txq->ift_cleaned_prev = txq->ift_cleaned; 2114 /* handle any laggards */ 2115 if (txq->ift_db_pending) 2116 GROUPTASK_ENQUEUE(&txq->ift_task); 2117 2118 sctx->isc_pause_frames = 0; 2119 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2120 callout_reset_on(&txq->ift_timer, iflib_timer_int, iflib_timer, 2121 txq, txq->ift_timer.c_cpu); 2122 return; 2123 hung: 2124 CTX_LOCK(ctx); 2125 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2126 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2127 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2128 2129 IFDI_WATCHDOG_RESET(ctx); 2130 ctx->ifc_watchdog_events++; 2131 2132 ctx->ifc_flags |= IFC_DO_RESET; 2133 iflib_admin_intr_deferred(ctx); 2134 CTX_UNLOCK(ctx); 2135 } 2136 2137 static void 2138 iflib_init_locked(if_ctx_t ctx) 2139 { 2140 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2141 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2142 if_t ifp = ctx->ifc_ifp; 2143 iflib_fl_t fl; 2144 iflib_txq_t txq; 2145 iflib_rxq_t rxq; 2146 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2147 2148 2149 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2150 IFDI_INTR_DISABLE(ctx); 2151 2152 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2153 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2154 /* Set hardware offload abilities */ 2155 if_clearhwassist(ifp); 2156 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2157 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2158 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2159 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2160 if (if_getcapenable(ifp) & IFCAP_TSO4) 2161 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2162 if (if_getcapenable(ifp) & IFCAP_TSO6) 2163 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2164 2165 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2166 CALLOUT_LOCK(txq); 2167 callout_stop(&txq->ift_timer); 2168 CALLOUT_UNLOCK(txq); 2169 iflib_netmap_txq_init(ctx, txq); 2170 } 2171 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2172 MPASS(rxq->ifr_id == i); 2173 iflib_netmap_rxq_init(ctx, rxq); 2174 } 2175 #ifdef INVARIANTS 2176 i = if_getdrvflags(ifp); 2177 #endif 2178 IFDI_INIT(ctx); 2179 MPASS(if_getdrvflags(ifp) == i); 2180 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2181 /* XXX this should really be done on a per-queue basis */ 2182 if (if_getcapenable(ifp) & IFCAP_NETMAP) 2183 continue; 2184 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2185 if (iflib_fl_setup(fl)) { 2186 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2187 goto done; 2188 } 2189 } 2190 } 2191 done: 2192 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2193 IFDI_INTR_ENABLE(ctx); 2194 txq = ctx->ifc_txqs; 2195 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2196 callout_reset_on(&txq->ift_timer, iflib_timer_int, iflib_timer, 2197 txq, txq->ift_timer.c_cpu); 2198 } 2199 2200 static int 2201 iflib_media_change(if_t ifp) 2202 { 2203 if_ctx_t ctx = if_getsoftc(ifp); 2204 int err; 2205 2206 CTX_LOCK(ctx); 2207 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2208 iflib_init_locked(ctx); 2209 CTX_UNLOCK(ctx); 2210 return (err); 2211 } 2212 2213 static void 2214 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2215 { 2216 if_ctx_t ctx = if_getsoftc(ifp); 2217 2218 CTX_LOCK(ctx); 2219 IFDI_UPDATE_ADMIN_STATUS(ctx); 2220 IFDI_MEDIA_STATUS(ctx, ifmr); 2221 CTX_UNLOCK(ctx); 2222 } 2223 2224 static void 2225 iflib_stop(if_ctx_t ctx) 2226 { 2227 iflib_txq_t txq = ctx->ifc_txqs; 2228 iflib_rxq_t rxq = ctx->ifc_rxqs; 2229 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2230 iflib_dma_info_t di; 2231 iflib_fl_t fl; 2232 int i, j; 2233 2234 /* Tell the stack that the interface is no longer active */ 2235 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2236 2237 IFDI_INTR_DISABLE(ctx); 2238 DELAY(1000); 2239 IFDI_STOP(ctx); 2240 DELAY(1000); 2241 2242 iflib_debug_reset(); 2243 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2244 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2245 /* make sure all transmitters have completed before proceeding XXX */ 2246 2247 /* clean any enqueued buffers */ 2248 iflib_ifmp_purge(txq); 2249 /* Free any existing tx buffers. */ 2250 for (j = 0; j < txq->ift_size; j++) { 2251 iflib_txsd_free(ctx, txq, j); 2252 } 2253 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2254 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2255 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2256 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2257 txq->ift_pullups = 0; 2258 ifmp_ring_reset_stats(txq->ift_br); 2259 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2260 bzero((void *)di->idi_vaddr, di->idi_size); 2261 } 2262 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2263 /* make sure all transmitters have completed before proceeding XXX */ 2264 2265 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++) 2266 bzero((void *)di->idi_vaddr, di->idi_size); 2267 /* also resets the free lists pidx/cidx */ 2268 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2269 iflib_fl_bufs_free(fl); 2270 } 2271 } 2272 2273 static inline caddr_t 2274 calc_next_rxd(iflib_fl_t fl, int cidx) 2275 { 2276 qidx_t size; 2277 int nrxd; 2278 caddr_t start, end, cur, next; 2279 2280 nrxd = fl->ifl_size; 2281 size = fl->ifl_rxd_size; 2282 start = fl->ifl_ifdi->idi_vaddr; 2283 2284 if (__predict_false(size == 0)) 2285 return (start); 2286 cur = start + size*cidx; 2287 end = start + size*nrxd; 2288 next = CACHE_PTR_NEXT(cur); 2289 return (next < end ? next : start); 2290 } 2291 2292 static inline void 2293 prefetch_pkts(iflib_fl_t fl, int cidx) 2294 { 2295 int nextptr; 2296 int nrxd = fl->ifl_size; 2297 caddr_t next_rxd; 2298 2299 2300 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2301 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2302 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2303 next_rxd = calc_next_rxd(fl, cidx); 2304 prefetch(next_rxd); 2305 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2306 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2307 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2308 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2309 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2310 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2311 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2312 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2313 } 2314 2315 static void 2316 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2317 { 2318 int flid, cidx; 2319 bus_dmamap_t map; 2320 iflib_fl_t fl; 2321 iflib_dma_info_t di; 2322 int next; 2323 2324 map = NULL; 2325 flid = irf->irf_flid; 2326 cidx = irf->irf_idx; 2327 fl = &rxq->ifr_fl[flid]; 2328 sd->ifsd_fl = fl; 2329 sd->ifsd_cidx = cidx; 2330 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2331 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2332 fl->ifl_credits--; 2333 #if MEMORY_LOGGING 2334 fl->ifl_m_dequeued++; 2335 #endif 2336 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2337 prefetch_pkts(fl, cidx); 2338 if (fl->ifl_sds.ifsd_map != NULL) { 2339 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2340 prefetch(&fl->ifl_sds.ifsd_map[next]); 2341 map = fl->ifl_sds.ifsd_map[cidx]; 2342 di = fl->ifl_ifdi; 2343 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2344 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2345 bus_dmamap_sync(di->idi_tag, di->idi_map, 2346 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2347 2348 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2349 MPASS(fl->ifl_cidx == cidx); 2350 if (unload) 2351 bus_dmamap_unload(fl->ifl_desc_tag, map); 2352 } 2353 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2354 if (__predict_false(fl->ifl_cidx == 0)) 2355 fl->ifl_gen = 0; 2356 if (map != NULL) 2357 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2358 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2359 } 2360 2361 static struct mbuf * 2362 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2363 { 2364 int i, padlen , flags; 2365 struct mbuf *m, *mh, *mt; 2366 caddr_t cl; 2367 2368 i = 0; 2369 mh = NULL; 2370 do { 2371 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2372 2373 MPASS(*sd->ifsd_cl != NULL); 2374 MPASS(*sd->ifsd_m != NULL); 2375 2376 /* Don't include zero-length frags */ 2377 if (ri->iri_frags[i].irf_len == 0) { 2378 /* XXX we can save the cluster here, but not the mbuf */ 2379 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2380 m_free(*sd->ifsd_m); 2381 *sd->ifsd_m = NULL; 2382 continue; 2383 } 2384 m = *sd->ifsd_m; 2385 *sd->ifsd_m = NULL; 2386 if (mh == NULL) { 2387 flags = M_PKTHDR|M_EXT; 2388 mh = mt = m; 2389 padlen = ri->iri_pad; 2390 } else { 2391 flags = M_EXT; 2392 mt->m_next = m; 2393 mt = m; 2394 /* assuming padding is only on the first fragment */ 2395 padlen = 0; 2396 } 2397 cl = *sd->ifsd_cl; 2398 *sd->ifsd_cl = NULL; 2399 2400 /* Can these two be made one ? */ 2401 m_init(m, M_NOWAIT, MT_DATA, flags); 2402 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2403 /* 2404 * These must follow m_init and m_cljset 2405 */ 2406 m->m_data += padlen; 2407 ri->iri_len -= padlen; 2408 m->m_len = ri->iri_frags[i].irf_len; 2409 } while (++i < ri->iri_nfrags); 2410 2411 return (mh); 2412 } 2413 2414 /* 2415 * Process one software descriptor 2416 */ 2417 static struct mbuf * 2418 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2419 { 2420 struct if_rxsd sd; 2421 struct mbuf *m; 2422 2423 /* should I merge this back in now that the two paths are basically duplicated? */ 2424 if (ri->iri_nfrags == 1 && 2425 ri->iri_frags[0].irf_len <= IFLIB_RX_COPY_THRESH) { 2426 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2427 m = *sd.ifsd_m; 2428 *sd.ifsd_m = NULL; 2429 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2430 #ifndef __NO_STRICT_ALIGNMENT 2431 if (!IP_ALIGNED(m)) 2432 m->m_data += 2; 2433 #endif 2434 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2435 m->m_len = ri->iri_frags[0].irf_len; 2436 } else { 2437 m = assemble_segments(rxq, ri, &sd); 2438 } 2439 m->m_pkthdr.len = ri->iri_len; 2440 m->m_pkthdr.rcvif = ri->iri_ifp; 2441 m->m_flags |= ri->iri_flags; 2442 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2443 m->m_pkthdr.flowid = ri->iri_flowid; 2444 M_HASHTYPE_SET(m, ri->iri_rsstype); 2445 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2446 m->m_pkthdr.csum_data = ri->iri_csum_data; 2447 return (m); 2448 } 2449 2450 static bool 2451 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2452 { 2453 if_ctx_t ctx = rxq->ifr_ctx; 2454 if_shared_ctx_t sctx = ctx->ifc_sctx; 2455 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2456 int avail, i; 2457 qidx_t *cidxp; 2458 struct if_rxd_info ri; 2459 int err, budget_left, rx_bytes, rx_pkts; 2460 iflib_fl_t fl; 2461 struct ifnet *ifp; 2462 int lro_enabled; 2463 2464 /* 2465 * XXX early demux data packets so that if_input processing only handles 2466 * acks in interrupt context 2467 */ 2468 struct mbuf *m, *mh, *mt; 2469 2470 ifp = ctx->ifc_ifp; 2471 #ifdef DEV_NETMAP 2472 if (ifp->if_capenable & IFCAP_NETMAP) { 2473 u_int work = 0; 2474 if (netmap_rx_irq(ifp, rxq->ifr_id, &work)) 2475 return (FALSE); 2476 } 2477 #endif 2478 2479 mh = mt = NULL; 2480 MPASS(budget > 0); 2481 rx_pkts = rx_bytes = 0; 2482 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2483 cidxp = &rxq->ifr_cq_cidx; 2484 else 2485 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2486 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2487 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2488 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2489 DBG_COUNTER_INC(rx_unavail); 2490 return (false); 2491 } 2492 2493 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2494 if (__predict_false(!CTX_ACTIVE(ctx))) { 2495 DBG_COUNTER_INC(rx_ctx_inactive); 2496 break; 2497 } 2498 /* 2499 * Reset client set fields to their default values 2500 */ 2501 rxd_info_zero(&ri); 2502 ri.iri_qsidx = rxq->ifr_id; 2503 ri.iri_cidx = *cidxp; 2504 ri.iri_ifp = ifp; 2505 ri.iri_frags = rxq->ifr_frags; 2506 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2507 2508 if (err) 2509 goto err; 2510 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2511 *cidxp = ri.iri_cidx; 2512 /* Update our consumer index */ 2513 /* XXX NB: shurd - check if this is still safe */ 2514 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2515 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2516 rxq->ifr_cq_gen = 0; 2517 } 2518 /* was this only a completion queue message? */ 2519 if (__predict_false(ri.iri_nfrags == 0)) 2520 continue; 2521 } 2522 MPASS(ri.iri_nfrags != 0); 2523 MPASS(ri.iri_len != 0); 2524 2525 /* will advance the cidx on the corresponding free lists */ 2526 m = iflib_rxd_pkt_get(rxq, &ri); 2527 if (avail == 0 && budget_left) 2528 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2529 2530 if (__predict_false(m == NULL)) { 2531 DBG_COUNTER_INC(rx_mbuf_null); 2532 continue; 2533 } 2534 /* imm_pkt: -- cxgb */ 2535 if (mh == NULL) 2536 mh = mt = m; 2537 else { 2538 mt->m_nextpkt = m; 2539 mt = m; 2540 } 2541 } 2542 /* make sure that we can refill faster than drain */ 2543 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2544 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2545 2546 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2547 while (mh != NULL) { 2548 m = mh; 2549 mh = mh->m_nextpkt; 2550 m->m_nextpkt = NULL; 2551 #ifndef __NO_STRICT_ALIGNMENT 2552 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2553 continue; 2554 #endif 2555 rx_bytes += m->m_pkthdr.len; 2556 rx_pkts++; 2557 #if defined(INET6) || defined(INET) 2558 if (lro_enabled && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2559 continue; 2560 #endif 2561 DBG_COUNTER_INC(rx_if_input); 2562 ifp->if_input(ifp, m); 2563 } 2564 2565 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2566 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2567 2568 /* 2569 * Flush any outstanding LRO work 2570 */ 2571 #if defined(INET6) || defined(INET) 2572 tcp_lro_flush_all(&rxq->ifr_lc); 2573 #endif 2574 if (avail) 2575 return true; 2576 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2577 err: 2578 CTX_LOCK(ctx); 2579 ctx->ifc_flags |= IFC_DO_RESET; 2580 iflib_admin_intr_deferred(ctx); 2581 CTX_UNLOCK(ctx); 2582 return (false); 2583 } 2584 2585 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2586 static inline qidx_t 2587 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2588 { 2589 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2590 qidx_t minthresh = txq->ift_size / 8; 2591 if (in_use > 4*minthresh) 2592 return (notify_count); 2593 if (in_use > 2*minthresh) 2594 return (notify_count >> 1); 2595 if (in_use > minthresh) 2596 return (notify_count >> 3); 2597 return (0); 2598 } 2599 2600 static inline qidx_t 2601 txq_max_rs_deferred(iflib_txq_t txq) 2602 { 2603 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2604 qidx_t minthresh = txq->ift_size / 8; 2605 if (txq->ift_in_use > 4*minthresh) 2606 return (notify_count); 2607 if (txq->ift_in_use > 2*minthresh) 2608 return (notify_count >> 1); 2609 if (txq->ift_in_use > minthresh) 2610 return (notify_count >> 2); 2611 return (2); 2612 } 2613 2614 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2615 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2616 2617 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2618 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2619 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2620 2621 /* forward compatibility for cxgb */ 2622 #define FIRST_QSET(ctx) 0 2623 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2624 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2625 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2626 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2627 2628 /* XXX we should be setting this to something other than zero */ 2629 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2630 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2631 2632 static inline bool 2633 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2634 { 2635 qidx_t dbval, max; 2636 bool rang; 2637 2638 rang = false; 2639 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2640 if (ring || txq->ift_db_pending >= max) { 2641 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2642 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2643 txq->ift_db_pending = txq->ift_npending = 0; 2644 rang = true; 2645 } 2646 return (rang); 2647 } 2648 2649 #ifdef PKT_DEBUG 2650 static void 2651 print_pkt(if_pkt_info_t pi) 2652 { 2653 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2654 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2655 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2656 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2657 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2658 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2659 } 2660 #endif 2661 2662 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2663 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2664 2665 static int 2666 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2667 { 2668 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2669 struct ether_vlan_header *eh; 2670 struct mbuf *m, *n; 2671 2672 n = m = *mp; 2673 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2674 M_WRITABLE(m) == 0) { 2675 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2676 return (ENOMEM); 2677 } else { 2678 m_freem(*mp); 2679 n = *mp = m; 2680 } 2681 } 2682 2683 /* 2684 * Determine where frame payload starts. 2685 * Jump over vlan headers if already present, 2686 * helpful for QinQ too. 2687 */ 2688 if (__predict_false(m->m_len < sizeof(*eh))) { 2689 txq->ift_pullups++; 2690 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2691 return (ENOMEM); 2692 } 2693 eh = mtod(m, struct ether_vlan_header *); 2694 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2695 pi->ipi_etype = ntohs(eh->evl_proto); 2696 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2697 } else { 2698 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2699 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2700 } 2701 2702 switch (pi->ipi_etype) { 2703 #ifdef INET 2704 case ETHERTYPE_IP: 2705 { 2706 struct ip *ip = NULL; 2707 struct tcphdr *th = NULL; 2708 int minthlen; 2709 2710 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2711 if (__predict_false(m->m_len < minthlen)) { 2712 /* 2713 * if this code bloat is causing too much of a hit 2714 * move it to a separate function and mark it noinline 2715 */ 2716 if (m->m_len == pi->ipi_ehdrlen) { 2717 n = m->m_next; 2718 MPASS(n); 2719 if (n->m_len >= sizeof(*ip)) { 2720 ip = (struct ip *)n->m_data; 2721 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2722 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2723 } else { 2724 txq->ift_pullups++; 2725 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2726 return (ENOMEM); 2727 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2728 } 2729 } else { 2730 txq->ift_pullups++; 2731 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2732 return (ENOMEM); 2733 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2734 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2735 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2736 } 2737 } else { 2738 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2739 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2740 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2741 } 2742 pi->ipi_ip_hlen = ip->ip_hl << 2; 2743 pi->ipi_ipproto = ip->ip_p; 2744 pi->ipi_flags |= IPI_TX_IPV4; 2745 2746 if (pi->ipi_csum_flags & CSUM_IP) 2747 ip->ip_sum = 0; 2748 2749 if (pi->ipi_ipproto == IPPROTO_TCP) { 2750 if (__predict_false(th == NULL)) { 2751 txq->ift_pullups++; 2752 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2753 return (ENOMEM); 2754 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2755 } 2756 pi->ipi_tcp_hflags = th->th_flags; 2757 pi->ipi_tcp_hlen = th->th_off << 2; 2758 pi->ipi_tcp_seq = th->th_seq; 2759 } 2760 if (IS_TSO4(pi)) { 2761 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2762 return (ENXIO); 2763 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2764 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2765 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2766 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2767 ip->ip_sum = 0; 2768 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2769 } 2770 } 2771 break; 2772 } 2773 #endif 2774 #ifdef INET6 2775 case ETHERTYPE_IPV6: 2776 { 2777 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2778 struct tcphdr *th; 2779 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2780 2781 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2782 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2783 return (ENOMEM); 2784 } 2785 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2786 2787 /* XXX-BZ this will go badly in case of ext hdrs. */ 2788 pi->ipi_ipproto = ip6->ip6_nxt; 2789 pi->ipi_flags |= IPI_TX_IPV6; 2790 2791 if (pi->ipi_ipproto == IPPROTO_TCP) { 2792 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2793 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2794 return (ENOMEM); 2795 } 2796 pi->ipi_tcp_hflags = th->th_flags; 2797 pi->ipi_tcp_hlen = th->th_off << 2; 2798 } 2799 if (IS_TSO6(pi)) { 2800 2801 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2802 return (ENXIO); 2803 /* 2804 * The corresponding flag is set by the stack in the IPv4 2805 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 2806 * So, set it here because the rest of the flow requires it. 2807 */ 2808 pi->ipi_csum_flags |= CSUM_TCP_IPV6; 2809 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2810 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2811 } 2812 break; 2813 } 2814 #endif 2815 default: 2816 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2817 pi->ipi_ip_hlen = 0; 2818 break; 2819 } 2820 *mp = m; 2821 2822 return (0); 2823 } 2824 2825 static __noinline struct mbuf * 2826 collapse_pkthdr(struct mbuf *m0) 2827 { 2828 struct mbuf *m, *m_next, *tmp; 2829 2830 m = m0; 2831 m_next = m->m_next; 2832 while (m_next != NULL && m_next->m_len == 0) { 2833 m = m_next; 2834 m->m_next = NULL; 2835 m_free(m); 2836 m_next = m_next->m_next; 2837 } 2838 m = m0; 2839 m->m_next = m_next; 2840 if ((m_next->m_flags & M_EXT) == 0) { 2841 m = m_defrag(m, M_NOWAIT); 2842 } else { 2843 tmp = m_next->m_next; 2844 memcpy(m_next, m, MPKTHSIZE); 2845 m = m_next; 2846 m->m_next = tmp; 2847 } 2848 return (m); 2849 } 2850 2851 /* 2852 * If dodgy hardware rejects the scatter gather chain we've handed it 2853 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 2854 * m_defrag'd mbufs 2855 */ 2856 static __noinline struct mbuf * 2857 iflib_remove_mbuf(iflib_txq_t txq) 2858 { 2859 int ntxd, i, pidx; 2860 struct mbuf *m, *mh, **ifsd_m; 2861 2862 pidx = txq->ift_pidx; 2863 ifsd_m = txq->ift_sds.ifsd_m; 2864 ntxd = txq->ift_size; 2865 mh = m = ifsd_m[pidx]; 2866 ifsd_m[pidx] = NULL; 2867 #if MEMORY_LOGGING 2868 txq->ift_dequeued++; 2869 #endif 2870 i = 1; 2871 2872 while (m) { 2873 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 2874 #if MEMORY_LOGGING 2875 txq->ift_dequeued++; 2876 #endif 2877 m = m->m_next; 2878 i++; 2879 } 2880 return (mh); 2881 } 2882 2883 static int 2884 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 2885 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 2886 int max_segs, int flags) 2887 { 2888 if_ctx_t ctx; 2889 if_shared_ctx_t sctx; 2890 if_softc_ctx_t scctx; 2891 int i, next, pidx, err, maxsegsz, ntxd, count; 2892 struct mbuf *m, *tmp, **ifsd_m; 2893 2894 m = *m0; 2895 2896 /* 2897 * Please don't ever do this 2898 */ 2899 if (__predict_false(m->m_len == 0)) 2900 *m0 = m = collapse_pkthdr(m); 2901 2902 ctx = txq->ift_ctx; 2903 sctx = ctx->ifc_sctx; 2904 scctx = &ctx->ifc_softc_ctx; 2905 ifsd_m = txq->ift_sds.ifsd_m; 2906 ntxd = txq->ift_size; 2907 pidx = txq->ift_pidx; 2908 if (force_busdma || map != NULL) { 2909 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 2910 2911 err = bus_dmamap_load_mbuf_sg(tag, map, 2912 *m0, segs, nsegs, BUS_DMA_NOWAIT); 2913 if (err) 2914 return (err); 2915 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 2916 count = 0; 2917 m = *m0; 2918 do { 2919 if (__predict_false(m->m_len <= 0)) { 2920 tmp = m; 2921 m = m->m_next; 2922 tmp->m_next = NULL; 2923 m_free(tmp); 2924 continue; 2925 } 2926 next = (pidx + count) & (ntxd-1); 2927 MPASS(ifsd_m[next] == NULL); 2928 ifsd_m[next] = m; 2929 count++; 2930 tmp = m; 2931 m = m->m_next; 2932 } while (m != NULL); 2933 } else { 2934 int buflen, sgsize, max_sgsize; 2935 vm_offset_t vaddr; 2936 vm_paddr_t curaddr; 2937 2938 count = i = 0; 2939 maxsegsz = sctx->isc_tx_maxsize; 2940 m = *m0; 2941 do { 2942 if (__predict_false(m->m_len <= 0)) { 2943 tmp = m; 2944 m = m->m_next; 2945 tmp->m_next = NULL; 2946 m_free(tmp); 2947 continue; 2948 } 2949 buflen = m->m_len; 2950 vaddr = (vm_offset_t)m->m_data; 2951 /* 2952 * see if we can't be smarter about physically 2953 * contiguous mappings 2954 */ 2955 next = (pidx + count) & (ntxd-1); 2956 MPASS(ifsd_m[next] == NULL); 2957 #if MEMORY_LOGGING 2958 txq->ift_enqueued++; 2959 #endif 2960 ifsd_m[next] = m; 2961 while (buflen > 0) { 2962 max_sgsize = MIN(buflen, maxsegsz); 2963 curaddr = pmap_kextract(vaddr); 2964 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 2965 sgsize = MIN(sgsize, max_sgsize); 2966 segs[i].ds_addr = curaddr; 2967 segs[i].ds_len = sgsize; 2968 vaddr += sgsize; 2969 buflen -= sgsize; 2970 i++; 2971 if (i >= max_segs) 2972 goto err; 2973 } 2974 count++; 2975 tmp = m; 2976 m = m->m_next; 2977 } while (m != NULL); 2978 *nsegs = i; 2979 } 2980 return (0); 2981 err: 2982 *m0 = iflib_remove_mbuf(txq); 2983 return (EFBIG); 2984 } 2985 2986 static inline caddr_t 2987 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 2988 { 2989 qidx_t size; 2990 int ntxd; 2991 caddr_t start, end, cur, next; 2992 2993 ntxd = txq->ift_size; 2994 size = txq->ift_txd_size[qid]; 2995 start = txq->ift_ifdi[qid].idi_vaddr; 2996 2997 if (__predict_false(size == 0)) 2998 return (start); 2999 cur = start + size*cidx; 3000 end = start + size*ntxd; 3001 next = CACHE_PTR_NEXT(cur); 3002 return (next < end ? next : start); 3003 } 3004 3005 static int 3006 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3007 { 3008 if_ctx_t ctx; 3009 if_shared_ctx_t sctx; 3010 if_softc_ctx_t scctx; 3011 bus_dma_segment_t *segs; 3012 struct mbuf *m_head; 3013 void *next_txd; 3014 bus_dmamap_t map; 3015 struct if_pkt_info pi; 3016 int remap = 0; 3017 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3018 bus_dma_tag_t desc_tag; 3019 3020 segs = txq->ift_segs; 3021 ctx = txq->ift_ctx; 3022 sctx = ctx->ifc_sctx; 3023 scctx = &ctx->ifc_softc_ctx; 3024 segs = txq->ift_segs; 3025 ntxd = txq->ift_size; 3026 m_head = *m_headp; 3027 map = NULL; 3028 3029 /* 3030 * If we're doing TSO the next descriptor to clean may be quite far ahead 3031 */ 3032 cidx = txq->ift_cidx; 3033 pidx = txq->ift_pidx; 3034 if (ctx->ifc_flags & IFC_PREFETCH) { 3035 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3036 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3037 next_txd = calc_next_txd(txq, cidx, 0); 3038 prefetch(next_txd); 3039 } 3040 3041 /* prefetch the next cache line of mbuf pointers and flags */ 3042 prefetch(&txq->ift_sds.ifsd_m[next]); 3043 if (txq->ift_sds.ifsd_map != NULL) { 3044 prefetch(&txq->ift_sds.ifsd_map[next]); 3045 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3046 prefetch(&txq->ift_sds.ifsd_flags[next]); 3047 } 3048 } 3049 if (txq->ift_sds.ifsd_map != NULL) 3050 map = txq->ift_sds.ifsd_map[pidx]; 3051 3052 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3053 desc_tag = txq->ift_tso_desc_tag; 3054 max_segs = scctx->isc_tx_tso_segments_max; 3055 } else { 3056 desc_tag = txq->ift_desc_tag; 3057 max_segs = scctx->isc_tx_nsegments; 3058 } 3059 m_head = *m_headp; 3060 3061 pkt_info_zero(&pi); 3062 pi.ipi_len = m_head->m_pkthdr.len; 3063 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3064 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3065 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3066 pi.ipi_pidx = pidx; 3067 pi.ipi_qsidx = txq->ift_id; 3068 3069 /* deliberate bitwise OR to make one condition */ 3070 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3071 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3072 return (err); 3073 m_head = *m_headp; 3074 } 3075 3076 retry: 3077 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3078 defrag: 3079 if (__predict_false(err)) { 3080 switch (err) { 3081 case EFBIG: 3082 /* try collapse once and defrag once */ 3083 if (remap == 0) 3084 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3085 if (remap == 1) 3086 m_head = m_defrag(*m_headp, M_NOWAIT); 3087 remap++; 3088 if (__predict_false(m_head == NULL)) 3089 goto defrag_failed; 3090 txq->ift_mbuf_defrag++; 3091 *m_headp = m_head; 3092 goto retry; 3093 break; 3094 case ENOMEM: 3095 txq->ift_no_tx_dma_setup++; 3096 break; 3097 default: 3098 txq->ift_no_tx_dma_setup++; 3099 m_freem(*m_headp); 3100 DBG_COUNTER_INC(tx_frees); 3101 *m_headp = NULL; 3102 break; 3103 } 3104 txq->ift_map_failed++; 3105 DBG_COUNTER_INC(encap_load_mbuf_fail); 3106 return (err); 3107 } 3108 3109 /* 3110 * XXX assumes a 1 to 1 relationship between segments and 3111 * descriptors - this does not hold true on all drivers, e.g. 3112 * cxgb 3113 */ 3114 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3115 txq->ift_no_desc_avail++; 3116 if (map != NULL) 3117 bus_dmamap_unload(desc_tag, map); 3118 DBG_COUNTER_INC(encap_txq_avail_fail); 3119 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3120 GROUPTASK_ENQUEUE(&txq->ift_task); 3121 return (ENOBUFS); 3122 } 3123 /* 3124 * On Intel cards we can greatly reduce the number of TX interrupts 3125 * we see by only setting report status on every Nth descriptor. 3126 * However, this also means that the driver will need to keep track 3127 * of the descriptors that RS was set on to check them for the DD bit. 3128 */ 3129 txq->ift_rs_pending += nsegs + 1; 3130 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3131 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) { 3132 pi.ipi_flags |= IPI_TX_INTR; 3133 txq->ift_rs_pending = 0; 3134 } 3135 3136 pi.ipi_segs = segs; 3137 pi.ipi_nsegs = nsegs; 3138 3139 MPASS(pidx >= 0 && pidx < txq->ift_size); 3140 #ifdef PKT_DEBUG 3141 print_pkt(&pi); 3142 #endif 3143 if (map != NULL) 3144 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3145 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3146 if (map != NULL) 3147 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3148 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3149 DBG_COUNTER_INC(tx_encap); 3150 MPASS(pi.ipi_new_pidx < txq->ift_size); 3151 3152 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3153 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3154 ndesc += txq->ift_size; 3155 txq->ift_gen = 1; 3156 } 3157 /* 3158 * drivers can need as many as 3159 * two sentinels 3160 */ 3161 MPASS(ndesc <= pi.ipi_nsegs + 2); 3162 MPASS(pi.ipi_new_pidx != pidx); 3163 MPASS(ndesc > 0); 3164 txq->ift_in_use += ndesc; 3165 3166 /* 3167 * We update the last software descriptor again here because there may 3168 * be a sentinel and/or there may be more mbufs than segments 3169 */ 3170 txq->ift_pidx = pi.ipi_new_pidx; 3171 txq->ift_npending += pi.ipi_ndescs; 3172 } else if (__predict_false(err == EFBIG && remap < 2)) { 3173 *m_headp = m_head = iflib_remove_mbuf(txq); 3174 remap = 1; 3175 txq->ift_txd_encap_efbig++; 3176 goto defrag; 3177 } else 3178 DBG_COUNTER_INC(encap_txd_encap_fail); 3179 return (err); 3180 3181 defrag_failed: 3182 txq->ift_mbuf_defrag_failed++; 3183 txq->ift_map_failed++; 3184 m_freem(*m_headp); 3185 DBG_COUNTER_INC(tx_frees); 3186 *m_headp = NULL; 3187 return (ENOMEM); 3188 } 3189 3190 static void 3191 iflib_tx_desc_free(iflib_txq_t txq, int n) 3192 { 3193 int hasmap; 3194 uint32_t qsize, cidx, mask, gen; 3195 struct mbuf *m, **ifsd_m; 3196 uint8_t *ifsd_flags; 3197 bus_dmamap_t *ifsd_map; 3198 bool do_prefetch; 3199 3200 cidx = txq->ift_cidx; 3201 gen = txq->ift_gen; 3202 qsize = txq->ift_size; 3203 mask = qsize-1; 3204 hasmap = txq->ift_sds.ifsd_map != NULL; 3205 ifsd_flags = txq->ift_sds.ifsd_flags; 3206 ifsd_m = txq->ift_sds.ifsd_m; 3207 ifsd_map = txq->ift_sds.ifsd_map; 3208 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3209 3210 while (n--) { 3211 if (do_prefetch) { 3212 prefetch(ifsd_m[(cidx + 3) & mask]); 3213 prefetch(ifsd_m[(cidx + 4) & mask]); 3214 } 3215 if (ifsd_m[cidx] != NULL) { 3216 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3217 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3218 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3219 /* 3220 * does it matter if it's not the TSO tag? If so we'll 3221 * have to add the type to flags 3222 */ 3223 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3224 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3225 } 3226 if ((m = ifsd_m[cidx]) != NULL) { 3227 /* XXX we don't support any drivers that batch packets yet */ 3228 MPASS(m->m_nextpkt == NULL); 3229 3230 m_free(m); 3231 ifsd_m[cidx] = NULL; 3232 #if MEMORY_LOGGING 3233 txq->ift_dequeued++; 3234 #endif 3235 DBG_COUNTER_INC(tx_frees); 3236 } 3237 } 3238 if (__predict_false(++cidx == qsize)) { 3239 cidx = 0; 3240 gen = 0; 3241 } 3242 } 3243 txq->ift_cidx = cidx; 3244 txq->ift_gen = gen; 3245 } 3246 3247 static __inline int 3248 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3249 { 3250 int reclaim; 3251 if_ctx_t ctx = txq->ift_ctx; 3252 3253 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3254 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3255 3256 /* 3257 * Need a rate-limiting check so that this isn't called every time 3258 */ 3259 iflib_tx_credits_update(ctx, txq); 3260 reclaim = DESC_RECLAIMABLE(txq); 3261 3262 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3263 #ifdef INVARIANTS 3264 if (iflib_verbose_debug) { 3265 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3266 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3267 reclaim, thresh); 3268 3269 } 3270 #endif 3271 return (0); 3272 } 3273 iflib_tx_desc_free(txq, reclaim); 3274 txq->ift_cleaned += reclaim; 3275 txq->ift_in_use -= reclaim; 3276 3277 return (reclaim); 3278 } 3279 3280 static struct mbuf ** 3281 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3282 { 3283 int next, size; 3284 struct mbuf **items; 3285 3286 size = r->size; 3287 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3288 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3289 3290 prefetch(items[(cidx + offset) & (size-1)]); 3291 if (remaining > 1) { 3292 prefetch(&items[next]); 3293 prefetch(items[(cidx + offset + 1) & (size-1)]); 3294 prefetch(items[(cidx + offset + 2) & (size-1)]); 3295 prefetch(items[(cidx + offset + 3) & (size-1)]); 3296 } 3297 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3298 } 3299 3300 static void 3301 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3302 { 3303 3304 ifmp_ring_check_drainage(txq->ift_br, budget); 3305 } 3306 3307 static uint32_t 3308 iflib_txq_can_drain(struct ifmp_ring *r) 3309 { 3310 iflib_txq_t txq = r->cookie; 3311 if_ctx_t ctx = txq->ift_ctx; 3312 3313 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3314 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3315 } 3316 3317 static uint32_t 3318 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3319 { 3320 iflib_txq_t txq = r->cookie; 3321 if_ctx_t ctx = txq->ift_ctx; 3322 struct ifnet *ifp = ctx->ifc_ifp; 3323 struct mbuf **mp, *m; 3324 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3325 int reclaimed, err, in_use_prev, desc_used; 3326 bool do_prefetch, ring, rang; 3327 3328 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3329 !LINK_ACTIVE(ctx))) { 3330 DBG_COUNTER_INC(txq_drain_notready); 3331 return (0); 3332 } 3333 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3334 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3335 avail = IDXDIFF(pidx, cidx, r->size); 3336 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3337 DBG_COUNTER_INC(txq_drain_flushing); 3338 for (i = 0; i < avail; i++) { 3339 m_free(r->items[(cidx + i) & (r->size-1)]); 3340 r->items[(cidx + i) & (r->size-1)] = NULL; 3341 } 3342 return (avail); 3343 } 3344 3345 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3346 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3347 CALLOUT_LOCK(txq); 3348 callout_stop(&txq->ift_timer); 3349 CALLOUT_UNLOCK(txq); 3350 DBG_COUNTER_INC(txq_drain_oactive); 3351 return (0); 3352 } 3353 if (reclaimed) 3354 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3355 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3356 count = MIN(avail, TX_BATCH_SIZE); 3357 #ifdef INVARIANTS 3358 if (iflib_verbose_debug) 3359 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3360 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3361 #endif 3362 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3363 avail = TXQ_AVAIL(txq); 3364 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3365 int pidx_prev, rem = do_prefetch ? count - i : 0; 3366 3367 mp = _ring_peek_one(r, cidx, i, rem); 3368 MPASS(mp != NULL && *mp != NULL); 3369 if (__predict_false(*mp == (struct mbuf *)txq)) { 3370 consumed++; 3371 reclaimed++; 3372 continue; 3373 } 3374 in_use_prev = txq->ift_in_use; 3375 pidx_prev = txq->ift_pidx; 3376 err = iflib_encap(txq, mp); 3377 if (__predict_false(err)) { 3378 DBG_COUNTER_INC(txq_drain_encapfail); 3379 /* no room - bail out */ 3380 if (err == ENOBUFS) 3381 break; 3382 consumed++; 3383 DBG_COUNTER_INC(txq_drain_encapfail); 3384 /* we can't send this packet - skip it */ 3385 continue; 3386 } 3387 consumed++; 3388 pkt_sent++; 3389 m = *mp; 3390 DBG_COUNTER_INC(tx_sent); 3391 bytes_sent += m->m_pkthdr.len; 3392 mcast_sent += !!(m->m_flags & M_MCAST); 3393 avail = TXQ_AVAIL(txq); 3394 3395 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3396 desc_used += (txq->ift_in_use - in_use_prev); 3397 ETHER_BPF_MTAP(ifp, m); 3398 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3399 break; 3400 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3401 } 3402 3403 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3404 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3405 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3406 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3407 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3408 if (mcast_sent) 3409 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3410 #ifdef INVARIANTS 3411 if (iflib_verbose_debug) 3412 printf("consumed=%d\n", consumed); 3413 #endif 3414 return (consumed); 3415 } 3416 3417 static uint32_t 3418 iflib_txq_drain_always(struct ifmp_ring *r) 3419 { 3420 return (1); 3421 } 3422 3423 static uint32_t 3424 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3425 { 3426 int i, avail; 3427 struct mbuf **mp; 3428 iflib_txq_t txq; 3429 3430 txq = r->cookie; 3431 3432 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3433 CALLOUT_LOCK(txq); 3434 callout_stop(&txq->ift_timer); 3435 CALLOUT_UNLOCK(txq); 3436 3437 avail = IDXDIFF(pidx, cidx, r->size); 3438 for (i = 0; i < avail; i++) { 3439 mp = _ring_peek_one(r, cidx, i, avail - i); 3440 if (__predict_false(*mp == (struct mbuf *)txq)) 3441 continue; 3442 m_freem(*mp); 3443 } 3444 MPASS(ifmp_ring_is_stalled(r) == 0); 3445 return (avail); 3446 } 3447 3448 static void 3449 iflib_ifmp_purge(iflib_txq_t txq) 3450 { 3451 struct ifmp_ring *r; 3452 3453 r = txq->ift_br; 3454 r->drain = iflib_txq_drain_free; 3455 r->can_drain = iflib_txq_drain_always; 3456 3457 ifmp_ring_check_drainage(r, r->size); 3458 3459 r->drain = iflib_txq_drain; 3460 r->can_drain = iflib_txq_can_drain; 3461 } 3462 3463 static void 3464 _task_fn_tx(void *context) 3465 { 3466 iflib_txq_t txq = context; 3467 if_ctx_t ctx = txq->ift_ctx; 3468 struct ifnet *ifp = ctx->ifc_ifp; 3469 int rc; 3470 3471 #ifdef IFLIB_DIAGNOSTICS 3472 txq->ift_cpu_exec_count[curcpu]++; 3473 #endif 3474 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3475 return; 3476 if ((ifp->if_capenable & IFCAP_NETMAP)) { 3477 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3478 netmap_tx_irq(ifp, txq->ift_id); 3479 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3480 return; 3481 } 3482 if (txq->ift_db_pending) 3483 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); 3484 else 3485 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3486 if (ctx->ifc_flags & IFC_LEGACY) 3487 IFDI_INTR_ENABLE(ctx); 3488 else { 3489 rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3490 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3491 } 3492 } 3493 3494 static void 3495 _task_fn_rx(void *context) 3496 { 3497 iflib_rxq_t rxq = context; 3498 if_ctx_t ctx = rxq->ifr_ctx; 3499 bool more; 3500 int rc; 3501 3502 #ifdef IFLIB_DIAGNOSTICS 3503 rxq->ifr_cpu_exec_count[curcpu]++; 3504 #endif 3505 DBG_COUNTER_INC(task_fn_rxs); 3506 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3507 return; 3508 if ((more = iflib_rxeof(rxq, 16 /* XXX */)) == false) { 3509 if (ctx->ifc_flags & IFC_LEGACY) 3510 IFDI_INTR_ENABLE(ctx); 3511 else { 3512 DBG_COUNTER_INC(rx_intr_enables); 3513 rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3514 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3515 } 3516 } 3517 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3518 return; 3519 if (more) 3520 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3521 } 3522 3523 static void 3524 _task_fn_admin(void *context) 3525 { 3526 if_ctx_t ctx = context; 3527 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3528 iflib_txq_t txq; 3529 int i; 3530 3531 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) { 3532 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3533 return; 3534 } 3535 } 3536 3537 CTX_LOCK(ctx); 3538 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3539 CALLOUT_LOCK(txq); 3540 callout_stop(&txq->ift_timer); 3541 CALLOUT_UNLOCK(txq); 3542 } 3543 IFDI_UPDATE_ADMIN_STATUS(ctx); 3544 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3545 callout_reset_on(&txq->ift_timer, iflib_timer_int, iflib_timer, 3546 txq, txq->ift_timer.c_cpu); 3547 IFDI_LINK_INTR_ENABLE(ctx); 3548 if (ctx->ifc_flags & IFC_DO_RESET) { 3549 ctx->ifc_flags &= ~IFC_DO_RESET; 3550 iflib_if_init_locked(ctx); 3551 } 3552 CTX_UNLOCK(ctx); 3553 3554 if (LINK_ACTIVE(ctx) == 0) 3555 return; 3556 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3557 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3558 } 3559 3560 3561 static void 3562 _task_fn_iov(void *context) 3563 { 3564 if_ctx_t ctx = context; 3565 3566 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3567 return; 3568 3569 CTX_LOCK(ctx); 3570 IFDI_VFLR_HANDLE(ctx); 3571 CTX_UNLOCK(ctx); 3572 } 3573 3574 static int 3575 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3576 { 3577 int err; 3578 if_int_delay_info_t info; 3579 if_ctx_t ctx; 3580 3581 info = (if_int_delay_info_t)arg1; 3582 ctx = info->iidi_ctx; 3583 info->iidi_req = req; 3584 info->iidi_oidp = oidp; 3585 CTX_LOCK(ctx); 3586 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3587 CTX_UNLOCK(ctx); 3588 return (err); 3589 } 3590 3591 /********************************************************************* 3592 * 3593 * IFNET FUNCTIONS 3594 * 3595 **********************************************************************/ 3596 3597 static void 3598 iflib_if_init_locked(if_ctx_t ctx) 3599 { 3600 iflib_stop(ctx); 3601 iflib_init_locked(ctx); 3602 } 3603 3604 3605 static void 3606 iflib_if_init(void *arg) 3607 { 3608 if_ctx_t ctx = arg; 3609 3610 CTX_LOCK(ctx); 3611 iflib_if_init_locked(ctx); 3612 CTX_UNLOCK(ctx); 3613 } 3614 3615 static int 3616 iflib_if_transmit(if_t ifp, struct mbuf *m) 3617 { 3618 if_ctx_t ctx = if_getsoftc(ifp); 3619 3620 iflib_txq_t txq; 3621 int err, qidx; 3622 3623 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3624 DBG_COUNTER_INC(tx_frees); 3625 m_freem(m); 3626 return (ENOBUFS); 3627 } 3628 3629 MPASS(m->m_nextpkt == NULL); 3630 qidx = 0; 3631 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3632 qidx = QIDX(ctx, m); 3633 /* 3634 * XXX calculate buf_ring based on flowid (divvy up bits?) 3635 */ 3636 txq = &ctx->ifc_txqs[qidx]; 3637 3638 #ifdef DRIVER_BACKPRESSURE 3639 if (txq->ift_closed) { 3640 while (m != NULL) { 3641 next = m->m_nextpkt; 3642 m->m_nextpkt = NULL; 3643 m_freem(m); 3644 m = next; 3645 } 3646 return (ENOBUFS); 3647 } 3648 #endif 3649 #ifdef notyet 3650 qidx = count = 0; 3651 mp = marr; 3652 next = m; 3653 do { 3654 count++; 3655 next = next->m_nextpkt; 3656 } while (next != NULL); 3657 3658 if (count > nitems(marr)) 3659 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3660 /* XXX check nextpkt */ 3661 m_freem(m); 3662 /* XXX simplify for now */ 3663 DBG_COUNTER_INC(tx_frees); 3664 return (ENOBUFS); 3665 } 3666 for (next = m, i = 0; next != NULL; i++) { 3667 mp[i] = next; 3668 next = next->m_nextpkt; 3669 mp[i]->m_nextpkt = NULL; 3670 } 3671 #endif 3672 DBG_COUNTER_INC(tx_seen); 3673 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); 3674 3675 if (err) { 3676 GROUPTASK_ENQUEUE(&txq->ift_task); 3677 /* support forthcoming later */ 3678 #ifdef DRIVER_BACKPRESSURE 3679 txq->ift_closed = TRUE; 3680 #endif 3681 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3682 m_freem(m); 3683 } else if (TXQ_AVAIL(txq) < (txq->ift_size >> 1)) { 3684 GROUPTASK_ENQUEUE(&txq->ift_task); 3685 } 3686 3687 return (err); 3688 } 3689 3690 static void 3691 iflib_if_qflush(if_t ifp) 3692 { 3693 if_ctx_t ctx = if_getsoftc(ifp); 3694 iflib_txq_t txq = ctx->ifc_txqs; 3695 int i; 3696 3697 CTX_LOCK(ctx); 3698 ctx->ifc_flags |= IFC_QFLUSH; 3699 CTX_UNLOCK(ctx); 3700 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3701 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3702 iflib_txq_check_drain(txq, 0); 3703 CTX_LOCK(ctx); 3704 ctx->ifc_flags &= ~IFC_QFLUSH; 3705 CTX_UNLOCK(ctx); 3706 3707 if_qflush(ifp); 3708 } 3709 3710 3711 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3712 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | \ 3713 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 3714 3715 static int 3716 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 3717 { 3718 if_ctx_t ctx = if_getsoftc(ifp); 3719 struct ifreq *ifr = (struct ifreq *)data; 3720 #if defined(INET) || defined(INET6) 3721 struct ifaddr *ifa = (struct ifaddr *)data; 3722 #endif 3723 bool avoid_reset = FALSE; 3724 int err = 0, reinit = 0, bits; 3725 3726 switch (command) { 3727 case SIOCSIFADDR: 3728 #ifdef INET 3729 if (ifa->ifa_addr->sa_family == AF_INET) 3730 avoid_reset = TRUE; 3731 #endif 3732 #ifdef INET6 3733 if (ifa->ifa_addr->sa_family == AF_INET6) 3734 avoid_reset = TRUE; 3735 #endif 3736 /* 3737 ** Calling init results in link renegotiation, 3738 ** so we avoid doing it when possible. 3739 */ 3740 if (avoid_reset) { 3741 if_setflagbits(ifp, IFF_UP,0); 3742 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING)) 3743 reinit = 1; 3744 #ifdef INET 3745 if (!(if_getflags(ifp) & IFF_NOARP)) 3746 arp_ifinit(ifp, ifa); 3747 #endif 3748 } else 3749 err = ether_ioctl(ifp, command, data); 3750 break; 3751 case SIOCSIFMTU: 3752 CTX_LOCK(ctx); 3753 if (ifr->ifr_mtu == if_getmtu(ifp)) { 3754 CTX_UNLOCK(ctx); 3755 break; 3756 } 3757 bits = if_getdrvflags(ifp); 3758 /* stop the driver and free any clusters before proceeding */ 3759 iflib_stop(ctx); 3760 3761 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 3762 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 3763 ctx->ifc_flags |= IFC_MULTISEG; 3764 else 3765 ctx->ifc_flags &= ~IFC_MULTISEG; 3766 err = if_setmtu(ifp, ifr->ifr_mtu); 3767 } 3768 iflib_init_locked(ctx); 3769 if_setdrvflags(ifp, bits); 3770 CTX_UNLOCK(ctx); 3771 break; 3772 case SIOCSIFFLAGS: 3773 CTX_LOCK(ctx); 3774 if (if_getflags(ifp) & IFF_UP) { 3775 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3776 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 3777 (IFF_PROMISC | IFF_ALLMULTI)) { 3778 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 3779 } 3780 } else 3781 reinit = 1; 3782 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3783 iflib_stop(ctx); 3784 } 3785 ctx->ifc_if_flags = if_getflags(ifp); 3786 CTX_UNLOCK(ctx); 3787 break; 3788 case SIOCADDMULTI: 3789 case SIOCDELMULTI: 3790 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3791 CTX_LOCK(ctx); 3792 IFDI_INTR_DISABLE(ctx); 3793 IFDI_MULTI_SET(ctx); 3794 IFDI_INTR_ENABLE(ctx); 3795 CTX_UNLOCK(ctx); 3796 } 3797 break; 3798 case SIOCSIFMEDIA: 3799 CTX_LOCK(ctx); 3800 IFDI_MEDIA_SET(ctx); 3801 CTX_UNLOCK(ctx); 3802 /* falls thru */ 3803 case SIOCGIFMEDIA: 3804 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 3805 break; 3806 case SIOCGI2C: 3807 { 3808 struct ifi2creq i2c; 3809 3810 err = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); 3811 if (err != 0) 3812 break; 3813 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 3814 err = EINVAL; 3815 break; 3816 } 3817 if (i2c.len > sizeof(i2c.data)) { 3818 err = EINVAL; 3819 break; 3820 } 3821 3822 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 3823 err = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); 3824 break; 3825 } 3826 case SIOCSIFCAP: 3827 { 3828 int mask, setmask; 3829 3830 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3831 setmask = 0; 3832 #ifdef TCP_OFFLOAD 3833 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 3834 #endif 3835 setmask |= (mask & IFCAP_FLAGS); 3836 3837 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 3838 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 3839 if ((mask & IFCAP_WOL) && 3840 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 3841 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 3842 if_vlancap(ifp); 3843 /* 3844 * want to ensure that traffic has stopped before we change any of the flags 3845 */ 3846 if (setmask) { 3847 CTX_LOCK(ctx); 3848 bits = if_getdrvflags(ifp); 3849 if (bits & IFF_DRV_RUNNING) 3850 iflib_stop(ctx); 3851 if_togglecapenable(ifp, setmask); 3852 if (bits & IFF_DRV_RUNNING) 3853 iflib_init_locked(ctx); 3854 if_setdrvflags(ifp, bits); 3855 CTX_UNLOCK(ctx); 3856 } 3857 break; 3858 } 3859 case SIOCGPRIVATE_0: 3860 case SIOCSDRVSPEC: 3861 case SIOCGDRVSPEC: 3862 CTX_LOCK(ctx); 3863 err = IFDI_PRIV_IOCTL(ctx, command, data); 3864 CTX_UNLOCK(ctx); 3865 break; 3866 default: 3867 err = ether_ioctl(ifp, command, data); 3868 break; 3869 } 3870 if (reinit) 3871 iflib_if_init(ctx); 3872 return (err); 3873 } 3874 3875 static uint64_t 3876 iflib_if_get_counter(if_t ifp, ift_counter cnt) 3877 { 3878 if_ctx_t ctx = if_getsoftc(ifp); 3879 3880 return (IFDI_GET_COUNTER(ctx, cnt)); 3881 } 3882 3883 /********************************************************************* 3884 * 3885 * OTHER FUNCTIONS EXPORTED TO THE STACK 3886 * 3887 **********************************************************************/ 3888 3889 static void 3890 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 3891 { 3892 if_ctx_t ctx = if_getsoftc(ifp); 3893 3894 if ((void *)ctx != arg) 3895 return; 3896 3897 if ((vtag == 0) || (vtag > 4095)) 3898 return; 3899 3900 CTX_LOCK(ctx); 3901 IFDI_VLAN_REGISTER(ctx, vtag); 3902 /* Re-init to load the changes */ 3903 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 3904 iflib_init_locked(ctx); 3905 CTX_UNLOCK(ctx); 3906 } 3907 3908 static void 3909 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 3910 { 3911 if_ctx_t ctx = if_getsoftc(ifp); 3912 3913 if ((void *)ctx != arg) 3914 return; 3915 3916 if ((vtag == 0) || (vtag > 4095)) 3917 return; 3918 3919 CTX_LOCK(ctx); 3920 IFDI_VLAN_UNREGISTER(ctx, vtag); 3921 /* Re-init to load the changes */ 3922 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 3923 iflib_init_locked(ctx); 3924 CTX_UNLOCK(ctx); 3925 } 3926 3927 static void 3928 iflib_led_func(void *arg, int onoff) 3929 { 3930 if_ctx_t ctx = arg; 3931 3932 CTX_LOCK(ctx); 3933 IFDI_LED_FUNC(ctx, onoff); 3934 CTX_UNLOCK(ctx); 3935 } 3936 3937 /********************************************************************* 3938 * 3939 * BUS FUNCTION DEFINITIONS 3940 * 3941 **********************************************************************/ 3942 3943 int 3944 iflib_device_probe(device_t dev) 3945 { 3946 pci_vendor_info_t *ent; 3947 3948 uint16_t pci_vendor_id, pci_device_id; 3949 uint16_t pci_subvendor_id, pci_subdevice_id; 3950 uint16_t pci_rev_id; 3951 if_shared_ctx_t sctx; 3952 3953 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 3954 return (ENOTSUP); 3955 3956 pci_vendor_id = pci_get_vendor(dev); 3957 pci_device_id = pci_get_device(dev); 3958 pci_subvendor_id = pci_get_subvendor(dev); 3959 pci_subdevice_id = pci_get_subdevice(dev); 3960 pci_rev_id = pci_get_revid(dev); 3961 if (sctx->isc_parse_devinfo != NULL) 3962 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 3963 3964 ent = sctx->isc_vendor_info; 3965 while (ent->pvi_vendor_id != 0) { 3966 if (pci_vendor_id != ent->pvi_vendor_id) { 3967 ent++; 3968 continue; 3969 } 3970 if ((pci_device_id == ent->pvi_device_id) && 3971 ((pci_subvendor_id == ent->pvi_subvendor_id) || 3972 (ent->pvi_subvendor_id == 0)) && 3973 ((pci_subdevice_id == ent->pvi_subdevice_id) || 3974 (ent->pvi_subdevice_id == 0)) && 3975 ((pci_rev_id == ent->pvi_rev_id) || 3976 (ent->pvi_rev_id == 0))) { 3977 3978 device_set_desc_copy(dev, ent->pvi_name); 3979 /* this needs to be changed to zero if the bus probing code 3980 * ever stops re-probing on best match because the sctx 3981 * may have its values over written by register calls 3982 * in subsequent probes 3983 */ 3984 return (BUS_PROBE_DEFAULT); 3985 } 3986 ent++; 3987 } 3988 return (ENXIO); 3989 } 3990 3991 int 3992 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 3993 { 3994 int err, rid, msix, msix_bar; 3995 if_ctx_t ctx; 3996 if_t ifp; 3997 if_softc_ctx_t scctx; 3998 int i; 3999 uint16_t main_txq; 4000 uint16_t main_rxq; 4001 4002 4003 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4004 4005 if (sc == NULL) { 4006 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4007 device_set_softc(dev, ctx); 4008 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4009 } 4010 4011 ctx->ifc_sctx = sctx; 4012 ctx->ifc_dev = dev; 4013 ctx->ifc_softc = sc; 4014 4015 if ((err = iflib_register(ctx)) != 0) { 4016 device_printf(dev, "iflib_register failed %d\n", err); 4017 return (err); 4018 } 4019 iflib_add_device_sysctl_pre(ctx); 4020 4021 scctx = &ctx->ifc_softc_ctx; 4022 ifp = ctx->ifc_ifp; 4023 4024 /* 4025 * XXX sanity check that ntxd & nrxd are a power of 2 4026 */ 4027 if (ctx->ifc_sysctl_ntxqs != 0) 4028 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4029 if (ctx->ifc_sysctl_nrxqs != 0) 4030 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4031 4032 for (i = 0; i < sctx->isc_ntxqs; i++) { 4033 if (ctx->ifc_sysctl_ntxds[i] != 0) 4034 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4035 else 4036 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4037 } 4038 4039 for (i = 0; i < sctx->isc_nrxqs; i++) { 4040 if (ctx->ifc_sysctl_nrxds[i] != 0) 4041 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4042 else 4043 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4044 } 4045 4046 for (i = 0; i < sctx->isc_nrxqs; i++) { 4047 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4048 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4049 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4050 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4051 } 4052 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4053 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4054 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4055 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4056 } 4057 } 4058 4059 for (i = 0; i < sctx->isc_ntxqs; i++) { 4060 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4061 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4062 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4063 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4064 } 4065 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4066 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4067 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4068 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4069 } 4070 } 4071 4072 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4073 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4074 return (err); 4075 } 4076 _iflib_pre_assert(scctx); 4077 ctx->ifc_txrx = *scctx->isc_txrx; 4078 4079 #ifdef INVARIANTS 4080 MPASS(scctx->isc_capenable); 4081 if (scctx->isc_capenable & IFCAP_TXCSUM) 4082 MPASS(scctx->isc_tx_csum_flags); 4083 #endif 4084 4085 if_setcapabilities(ifp, scctx->isc_capenable); 4086 if_setcapenable(ifp, scctx->isc_capenable); 4087 4088 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4089 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4090 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4091 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4092 4093 #ifdef ACPI_DMAR 4094 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4095 ctx->ifc_flags |= IFC_DMAR; 4096 #elif !(defined(__i386__) || defined(__amd64__)) 4097 /* set unconditionally for !x86 */ 4098 ctx->ifc_flags |= IFC_DMAR; 4099 #endif 4100 if (force_busdma) 4101 ctx->ifc_flags |= IFC_DMAR; 4102 4103 msix_bar = scctx->isc_msix_bar; 4104 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4105 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4106 4107 /* XXX change for per-queue sizes */ 4108 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4109 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4110 for (i = 0; i < sctx->isc_nrxqs; i++) { 4111 if (!powerof2(scctx->isc_nrxd[i])) { 4112 /* round down instead? */ 4113 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4114 err = EINVAL; 4115 goto fail; 4116 } 4117 } 4118 for (i = 0; i < sctx->isc_ntxqs; i++) { 4119 if (!powerof2(scctx->isc_ntxd[i])) { 4120 device_printf(dev, 4121 "# tx descriptors must be a power of 2"); 4122 err = EINVAL; 4123 goto fail; 4124 } 4125 } 4126 4127 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4128 MAX_SINGLE_PACKET_FRACTION) 4129 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4130 MAX_SINGLE_PACKET_FRACTION); 4131 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4132 MAX_SINGLE_PACKET_FRACTION) 4133 scctx->isc_tx_tso_segments_max = max(1, 4134 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4135 4136 /* 4137 * Protect the stack against modern hardware 4138 */ 4139 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4140 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4141 4142 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4143 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4144 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4145 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4146 if (scctx->isc_rss_table_size == 0) 4147 scctx->isc_rss_table_size = 64; 4148 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4149 4150 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4151 /* XXX format name */ 4152 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4153 /* 4154 ** Now setup MSI or MSI/X, should 4155 ** return us the number of supported 4156 ** vectors. (Will be 1 for MSI) 4157 */ 4158 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4159 msix = scctx->isc_vectors; 4160 } else if (scctx->isc_msix_bar != 0) 4161 /* 4162 * The simple fact that isc_msix_bar is not 0 does not mean we 4163 * we have a good value there that is known to work. 4164 */ 4165 msix = iflib_msix_init(ctx); 4166 else { 4167 scctx->isc_vectors = 1; 4168 scctx->isc_ntxqsets = 1; 4169 scctx->isc_nrxqsets = 1; 4170 scctx->isc_intr = IFLIB_INTR_LEGACY; 4171 msix = 0; 4172 } 4173 /* Get memory for the station queues */ 4174 if ((err = iflib_queues_alloc(ctx))) { 4175 device_printf(dev, "Unable to allocate queue memory\n"); 4176 goto fail; 4177 } 4178 4179 if ((err = iflib_qset_structures_setup(ctx))) { 4180 device_printf(dev, "qset structure setup failed %d\n", err); 4181 goto fail_queues; 4182 } 4183 4184 /* 4185 * Group taskqueues aren't properly set up until SMP is started, 4186 * so we disable interrupts until we can handle them post 4187 * SI_SUB_SMP. 4188 * 4189 * XXX: disabling interrupts doesn't actually work, at least for 4190 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4191 * we do null handling and depend on this not causing too large an 4192 * interrupt storm. 4193 */ 4194 IFDI_INTR_DISABLE(ctx); 4195 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4196 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4197 goto fail_intr_free; 4198 } 4199 if (msix <= 1) { 4200 rid = 0; 4201 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4202 MPASS(msix == 1); 4203 rid = 1; 4204 } 4205 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4206 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4207 goto fail_intr_free; 4208 } 4209 } 4210 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4211 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4212 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4213 goto fail_detach; 4214 } 4215 if ((err = iflib_netmap_attach(ctx))) { 4216 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4217 goto fail_detach; 4218 } 4219 *ctxp = ctx; 4220 4221 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4222 iflib_add_device_sysctl_post(ctx); 4223 ctx->ifc_flags |= IFC_INIT_DONE; 4224 return (0); 4225 fail_detach: 4226 ether_ifdetach(ctx->ifc_ifp); 4227 fail_intr_free: 4228 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4229 pci_release_msi(ctx->ifc_dev); 4230 fail_queues: 4231 /* XXX free queues */ 4232 fail: 4233 IFDI_DETACH(ctx); 4234 return (err); 4235 } 4236 4237 int 4238 iflib_device_attach(device_t dev) 4239 { 4240 if_ctx_t ctx; 4241 if_shared_ctx_t sctx; 4242 4243 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4244 return (ENOTSUP); 4245 4246 pci_enable_busmaster(dev); 4247 4248 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4249 } 4250 4251 int 4252 iflib_device_deregister(if_ctx_t ctx) 4253 { 4254 if_t ifp = ctx->ifc_ifp; 4255 iflib_txq_t txq; 4256 iflib_rxq_t rxq; 4257 device_t dev = ctx->ifc_dev; 4258 int i; 4259 struct taskqgroup *tqg; 4260 4261 /* Make sure VLANS are not using driver */ 4262 if (if_vlantrunkinuse(ifp)) { 4263 device_printf(dev,"Vlan in use, detach first\n"); 4264 return (EBUSY); 4265 } 4266 4267 CTX_LOCK(ctx); 4268 ctx->ifc_in_detach = 1; 4269 iflib_stop(ctx); 4270 CTX_UNLOCK(ctx); 4271 4272 /* Unregister VLAN events */ 4273 if (ctx->ifc_vlan_attach_event != NULL) 4274 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4275 if (ctx->ifc_vlan_detach_event != NULL) 4276 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4277 4278 iflib_netmap_detach(ifp); 4279 ether_ifdetach(ifp); 4280 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4281 CTX_LOCK_DESTROY(ctx); 4282 if (ctx->ifc_led_dev != NULL) 4283 led_destroy(ctx->ifc_led_dev); 4284 /* XXX drain any dependent tasks */ 4285 tqg = qgroup_if_io_tqg; 4286 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4287 callout_drain(&txq->ift_timer); 4288 if (txq->ift_task.gt_uniq != NULL) 4289 taskqgroup_detach(tqg, &txq->ift_task); 4290 } 4291 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4292 if (rxq->ifr_task.gt_uniq != NULL) 4293 taskqgroup_detach(tqg, &rxq->ifr_task); 4294 } 4295 tqg = qgroup_if_config_tqg; 4296 if (ctx->ifc_admin_task.gt_uniq != NULL) 4297 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4298 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4299 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4300 4301 IFDI_DETACH(ctx); 4302 device_set_softc(ctx->ifc_dev, NULL); 4303 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4304 pci_release_msi(dev); 4305 } 4306 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4307 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4308 } 4309 if (ctx->ifc_msix_mem != NULL) { 4310 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4311 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4312 ctx->ifc_msix_mem = NULL; 4313 } 4314 4315 bus_generic_detach(dev); 4316 if_free(ifp); 4317 4318 iflib_tx_structures_free(ctx); 4319 iflib_rx_structures_free(ctx); 4320 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4321 free(ctx->ifc_softc, M_IFLIB); 4322 free(ctx, M_IFLIB); 4323 return (0); 4324 } 4325 4326 4327 int 4328 iflib_device_detach(device_t dev) 4329 { 4330 if_ctx_t ctx = device_get_softc(dev); 4331 4332 return (iflib_device_deregister(ctx)); 4333 } 4334 4335 int 4336 iflib_device_suspend(device_t dev) 4337 { 4338 if_ctx_t ctx = device_get_softc(dev); 4339 4340 CTX_LOCK(ctx); 4341 IFDI_SUSPEND(ctx); 4342 CTX_UNLOCK(ctx); 4343 4344 return bus_generic_suspend(dev); 4345 } 4346 int 4347 iflib_device_shutdown(device_t dev) 4348 { 4349 if_ctx_t ctx = device_get_softc(dev); 4350 4351 CTX_LOCK(ctx); 4352 IFDI_SHUTDOWN(ctx); 4353 CTX_UNLOCK(ctx); 4354 4355 return bus_generic_suspend(dev); 4356 } 4357 4358 4359 int 4360 iflib_device_resume(device_t dev) 4361 { 4362 if_ctx_t ctx = device_get_softc(dev); 4363 iflib_txq_t txq = ctx->ifc_txqs; 4364 4365 CTX_LOCK(ctx); 4366 IFDI_RESUME(ctx); 4367 iflib_init_locked(ctx); 4368 CTX_UNLOCK(ctx); 4369 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4370 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4371 4372 return (bus_generic_resume(dev)); 4373 } 4374 4375 int 4376 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4377 { 4378 int error; 4379 if_ctx_t ctx = device_get_softc(dev); 4380 4381 CTX_LOCK(ctx); 4382 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4383 CTX_UNLOCK(ctx); 4384 4385 return (error); 4386 } 4387 4388 void 4389 iflib_device_iov_uninit(device_t dev) 4390 { 4391 if_ctx_t ctx = device_get_softc(dev); 4392 4393 CTX_LOCK(ctx); 4394 IFDI_IOV_UNINIT(ctx); 4395 CTX_UNLOCK(ctx); 4396 } 4397 4398 int 4399 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 4400 { 4401 int error; 4402 if_ctx_t ctx = device_get_softc(dev); 4403 4404 CTX_LOCK(ctx); 4405 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 4406 CTX_UNLOCK(ctx); 4407 4408 return (error); 4409 } 4410 4411 /********************************************************************* 4412 * 4413 * MODULE FUNCTION DEFINITIONS 4414 * 4415 **********************************************************************/ 4416 4417 /* 4418 * - Start a fast taskqueue thread for each core 4419 * - Start a taskqueue for control operations 4420 */ 4421 static int 4422 iflib_module_init(void) 4423 { 4424 4425 iflib_timer_int = hz / 2; 4426 TUNABLE_INT_FETCH("net.iflib.timer_int", &iflib_timer_int); 4427 return (0); 4428 } 4429 4430 static int 4431 iflib_module_event_handler(module_t mod, int what, void *arg) 4432 { 4433 int err; 4434 4435 switch (what) { 4436 case MOD_LOAD: 4437 if ((err = iflib_module_init()) != 0) 4438 return (err); 4439 break; 4440 case MOD_UNLOAD: 4441 return (EBUSY); 4442 default: 4443 return (EOPNOTSUPP); 4444 } 4445 4446 return (0); 4447 } 4448 4449 /********************************************************************* 4450 * 4451 * PUBLIC FUNCTION DEFINITIONS 4452 * ordered as in iflib.h 4453 * 4454 **********************************************************************/ 4455 4456 4457 static void 4458 _iflib_assert(if_shared_ctx_t sctx) 4459 { 4460 MPASS(sctx->isc_tx_maxsize); 4461 MPASS(sctx->isc_tx_maxsegsize); 4462 4463 MPASS(sctx->isc_rx_maxsize); 4464 MPASS(sctx->isc_rx_nsegments); 4465 MPASS(sctx->isc_rx_maxsegsize); 4466 4467 MPASS(sctx->isc_nrxd_min[0]); 4468 MPASS(sctx->isc_nrxd_max[0]); 4469 MPASS(sctx->isc_nrxd_default[0]); 4470 MPASS(sctx->isc_ntxd_min[0]); 4471 MPASS(sctx->isc_ntxd_max[0]); 4472 MPASS(sctx->isc_ntxd_default[0]); 4473 } 4474 4475 static void 4476 _iflib_pre_assert(if_softc_ctx_t scctx) 4477 { 4478 4479 MPASS(scctx->isc_txrx->ift_txd_encap); 4480 MPASS(scctx->isc_txrx->ift_txd_flush); 4481 MPASS(scctx->isc_txrx->ift_txd_credits_update); 4482 MPASS(scctx->isc_txrx->ift_rxd_available); 4483 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 4484 MPASS(scctx->isc_txrx->ift_rxd_refill); 4485 MPASS(scctx->isc_txrx->ift_rxd_flush); 4486 } 4487 4488 static int 4489 iflib_register(if_ctx_t ctx) 4490 { 4491 if_shared_ctx_t sctx = ctx->ifc_sctx; 4492 driver_t *driver = sctx->isc_driver; 4493 device_t dev = ctx->ifc_dev; 4494 if_t ifp; 4495 4496 _iflib_assert(sctx); 4497 4498 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 4499 4500 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 4501 if (ifp == NULL) { 4502 device_printf(dev, "can not allocate ifnet structure\n"); 4503 return (ENOMEM); 4504 } 4505 4506 /* 4507 * Initialize our context's device specific methods 4508 */ 4509 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 4510 kobj_class_compile((kobj_class_t) driver); 4511 driver->refs++; 4512 4513 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 4514 if_setsoftc(ifp, ctx); 4515 if_setdev(ifp, dev); 4516 if_setinitfn(ifp, iflib_if_init); 4517 if_setioctlfn(ifp, iflib_if_ioctl); 4518 if_settransmitfn(ifp, iflib_if_transmit); 4519 if_setqflushfn(ifp, iflib_if_qflush); 4520 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 4521 4522 ctx->ifc_vlan_attach_event = 4523 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 4524 EVENTHANDLER_PRI_FIRST); 4525 ctx->ifc_vlan_detach_event = 4526 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 4527 EVENTHANDLER_PRI_FIRST); 4528 4529 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 4530 iflib_media_change, iflib_media_status); 4531 4532 return (0); 4533 } 4534 4535 4536 static int 4537 iflib_queues_alloc(if_ctx_t ctx) 4538 { 4539 if_shared_ctx_t sctx = ctx->ifc_sctx; 4540 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4541 device_t dev = ctx->ifc_dev; 4542 int nrxqsets = scctx->isc_nrxqsets; 4543 int ntxqsets = scctx->isc_ntxqsets; 4544 iflib_txq_t txq; 4545 iflib_rxq_t rxq; 4546 iflib_fl_t fl = NULL; 4547 int i, j, cpu, err, txconf, rxconf; 4548 iflib_dma_info_t ifdip; 4549 uint32_t *rxqsizes = scctx->isc_rxqsizes; 4550 uint32_t *txqsizes = scctx->isc_txqsizes; 4551 uint8_t nrxqs = sctx->isc_nrxqs; 4552 uint8_t ntxqs = sctx->isc_ntxqs; 4553 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 4554 caddr_t *vaddrs; 4555 uint64_t *paddrs; 4556 struct ifmp_ring **brscp; 4557 4558 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 4559 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 4560 4561 brscp = NULL; 4562 txq = NULL; 4563 rxq = NULL; 4564 4565 /* Allocate the TX ring struct memory */ 4566 if (!(txq = 4567 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 4568 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4569 device_printf(dev, "Unable to allocate TX ring memory\n"); 4570 err = ENOMEM; 4571 goto fail; 4572 } 4573 4574 /* Now allocate the RX */ 4575 if (!(rxq = 4576 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 4577 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4578 device_printf(dev, "Unable to allocate RX ring memory\n"); 4579 err = ENOMEM; 4580 goto rx_fail; 4581 } 4582 4583 ctx->ifc_txqs = txq; 4584 ctx->ifc_rxqs = rxq; 4585 4586 /* 4587 * XXX handle allocation failure 4588 */ 4589 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 4590 /* Set up some basics */ 4591 4592 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4593 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4594 err = ENOMEM; 4595 goto err_tx_desc; 4596 } 4597 txq->ift_ifdi = ifdip; 4598 for (j = 0; j < ntxqs; j++, ifdip++) { 4599 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4600 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4601 err = ENOMEM; 4602 goto err_tx_desc; 4603 } 4604 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 4605 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 4606 } 4607 txq->ift_ctx = ctx; 4608 txq->ift_id = i; 4609 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 4610 txq->ift_br_offset = 1; 4611 } else { 4612 txq->ift_br_offset = 0; 4613 } 4614 /* XXX fix this */ 4615 txq->ift_timer.c_cpu = cpu; 4616 4617 if (iflib_txsd_alloc(txq)) { 4618 device_printf(dev, "Critical Failure setting up TX buffers\n"); 4619 err = ENOMEM; 4620 goto err_tx_desc; 4621 } 4622 4623 /* Initialize the TX lock */ 4624 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 4625 device_get_nameunit(dev), txq->ift_id); 4626 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 4627 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 4628 4629 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 4630 device_get_nameunit(dev), txq->ift_id); 4631 4632 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 4633 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 4634 if (err) { 4635 /* XXX free any allocated rings */ 4636 device_printf(dev, "Unable to allocate buf_ring\n"); 4637 goto err_tx_desc; 4638 } 4639 } 4640 4641 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 4642 /* Set up some basics */ 4643 4644 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4645 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4646 err = ENOMEM; 4647 goto err_tx_desc; 4648 } 4649 4650 rxq->ifr_ifdi = ifdip; 4651 /* XXX this needs to be changed if #rx queues != #tx queues */ 4652 rxq->ifr_ntxqirq = 1; 4653 rxq->ifr_txqid[0] = i; 4654 for (j = 0; j < nrxqs; j++, ifdip++) { 4655 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4656 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4657 err = ENOMEM; 4658 goto err_tx_desc; 4659 } 4660 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 4661 } 4662 rxq->ifr_ctx = ctx; 4663 rxq->ifr_id = i; 4664 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 4665 rxq->ifr_fl_offset = 1; 4666 } else { 4667 rxq->ifr_fl_offset = 0; 4668 } 4669 rxq->ifr_nfl = nfree_lists; 4670 if (!(fl = 4671 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 4672 device_printf(dev, "Unable to allocate free list memory\n"); 4673 err = ENOMEM; 4674 goto err_tx_desc; 4675 } 4676 rxq->ifr_fl = fl; 4677 for (j = 0; j < nfree_lists; j++) { 4678 fl[j].ifl_rxq = rxq; 4679 fl[j].ifl_id = j; 4680 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 4681 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 4682 } 4683 /* Allocate receive buffers for the ring*/ 4684 if (iflib_rxsd_alloc(rxq)) { 4685 device_printf(dev, 4686 "Critical Failure setting up receive buffers\n"); 4687 err = ENOMEM; 4688 goto err_rx_desc; 4689 } 4690 } 4691 4692 /* TXQs */ 4693 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4694 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4695 for (i = 0; i < ntxqsets; i++) { 4696 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 4697 4698 for (j = 0; j < ntxqs; j++, di++) { 4699 vaddrs[i*ntxqs + j] = di->idi_vaddr; 4700 paddrs[i*ntxqs + j] = di->idi_paddr; 4701 } 4702 } 4703 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 4704 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4705 iflib_tx_structures_free(ctx); 4706 free(vaddrs, M_IFLIB); 4707 free(paddrs, M_IFLIB); 4708 goto err_rx_desc; 4709 } 4710 free(vaddrs, M_IFLIB); 4711 free(paddrs, M_IFLIB); 4712 4713 /* RXQs */ 4714 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4715 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4716 for (i = 0; i < nrxqsets; i++) { 4717 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 4718 4719 for (j = 0; j < nrxqs; j++, di++) { 4720 vaddrs[i*nrxqs + j] = di->idi_vaddr; 4721 paddrs[i*nrxqs + j] = di->idi_paddr; 4722 } 4723 } 4724 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 4725 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4726 iflib_tx_structures_free(ctx); 4727 free(vaddrs, M_IFLIB); 4728 free(paddrs, M_IFLIB); 4729 goto err_rx_desc; 4730 } 4731 free(vaddrs, M_IFLIB); 4732 free(paddrs, M_IFLIB); 4733 4734 return (0); 4735 4736 /* XXX handle allocation failure changes */ 4737 err_rx_desc: 4738 err_tx_desc: 4739 if (ctx->ifc_rxqs != NULL) 4740 free(ctx->ifc_rxqs, M_IFLIB); 4741 ctx->ifc_rxqs = NULL; 4742 if (ctx->ifc_txqs != NULL) 4743 free(ctx->ifc_txqs, M_IFLIB); 4744 ctx->ifc_txqs = NULL; 4745 rx_fail: 4746 if (brscp != NULL) 4747 free(brscp, M_IFLIB); 4748 if (rxq != NULL) 4749 free(rxq, M_IFLIB); 4750 if (txq != NULL) 4751 free(txq, M_IFLIB); 4752 fail: 4753 return (err); 4754 } 4755 4756 static int 4757 iflib_tx_structures_setup(if_ctx_t ctx) 4758 { 4759 iflib_txq_t txq = ctx->ifc_txqs; 4760 int i; 4761 4762 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4763 iflib_txq_setup(txq); 4764 4765 return (0); 4766 } 4767 4768 static void 4769 iflib_tx_structures_free(if_ctx_t ctx) 4770 { 4771 iflib_txq_t txq = ctx->ifc_txqs; 4772 int i, j; 4773 4774 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 4775 iflib_txq_destroy(txq); 4776 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 4777 iflib_dma_free(&txq->ift_ifdi[j]); 4778 } 4779 free(ctx->ifc_txqs, M_IFLIB); 4780 ctx->ifc_txqs = NULL; 4781 IFDI_QUEUES_FREE(ctx); 4782 } 4783 4784 /********************************************************************* 4785 * 4786 * Initialize all receive rings. 4787 * 4788 **********************************************************************/ 4789 static int 4790 iflib_rx_structures_setup(if_ctx_t ctx) 4791 { 4792 iflib_rxq_t rxq = ctx->ifc_rxqs; 4793 int q; 4794 #if defined(INET6) || defined(INET) 4795 int i, err; 4796 #endif 4797 4798 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 4799 #if defined(INET6) || defined(INET) 4800 tcp_lro_free(&rxq->ifr_lc); 4801 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 4802 TCP_LRO_ENTRIES, min(1024, 4803 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 4804 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 4805 goto fail; 4806 } 4807 rxq->ifr_lro_enabled = TRUE; 4808 #endif 4809 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 4810 } 4811 return (0); 4812 #if defined(INET6) || defined(INET) 4813 fail: 4814 /* 4815 * Free RX software descriptors allocated so far, we will only handle 4816 * the rings that completed, the failing case will have 4817 * cleaned up for itself. 'q' failed, so its the terminus. 4818 */ 4819 rxq = ctx->ifc_rxqs; 4820 for (i = 0; i < q; ++i, rxq++) { 4821 iflib_rx_sds_free(rxq); 4822 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 4823 } 4824 return (err); 4825 #endif 4826 } 4827 4828 /********************************************************************* 4829 * 4830 * Free all receive rings. 4831 * 4832 **********************************************************************/ 4833 static void 4834 iflib_rx_structures_free(if_ctx_t ctx) 4835 { 4836 iflib_rxq_t rxq = ctx->ifc_rxqs; 4837 4838 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 4839 iflib_rx_sds_free(rxq); 4840 } 4841 } 4842 4843 static int 4844 iflib_qset_structures_setup(if_ctx_t ctx) 4845 { 4846 int err; 4847 4848 if ((err = iflib_tx_structures_setup(ctx)) != 0) 4849 return (err); 4850 4851 if ((err = iflib_rx_structures_setup(ctx)) != 0) { 4852 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 4853 iflib_tx_structures_free(ctx); 4854 iflib_rx_structures_free(ctx); 4855 } 4856 return (err); 4857 } 4858 4859 int 4860 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 4861 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name) 4862 { 4863 4864 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 4865 } 4866 4867 static int 4868 find_nth(if_ctx_t ctx, cpuset_t *cpus, int qid) 4869 { 4870 int i, cpuid, eqid, count; 4871 4872 CPU_COPY(&ctx->ifc_cpus, cpus); 4873 count = CPU_COUNT(&ctx->ifc_cpus); 4874 eqid = qid % count; 4875 /* clear up to the qid'th bit */ 4876 for (i = 0; i < eqid; i++) { 4877 cpuid = CPU_FFS(cpus); 4878 MPASS(cpuid != 0); 4879 CPU_CLR(cpuid-1, cpus); 4880 } 4881 cpuid = CPU_FFS(cpus); 4882 MPASS(cpuid != 0); 4883 return (cpuid-1); 4884 } 4885 4886 int 4887 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 4888 iflib_intr_type_t type, driver_filter_t *filter, 4889 void *filter_arg, int qid, char *name) 4890 { 4891 struct grouptask *gtask; 4892 struct taskqgroup *tqg; 4893 iflib_filter_info_t info; 4894 cpuset_t cpus; 4895 gtask_fn_t *fn; 4896 int tqrid, err, cpuid; 4897 driver_filter_t *intr_fast; 4898 void *q; 4899 4900 info = &ctx->ifc_filter_info; 4901 tqrid = rid; 4902 4903 switch (type) { 4904 /* XXX merge tx/rx for netmap? */ 4905 case IFLIB_INTR_TX: 4906 q = &ctx->ifc_txqs[qid]; 4907 info = &ctx->ifc_txqs[qid].ift_filter_info; 4908 gtask = &ctx->ifc_txqs[qid].ift_task; 4909 tqg = qgroup_if_io_tqg; 4910 fn = _task_fn_tx; 4911 intr_fast = iflib_fast_intr; 4912 GROUPTASK_INIT(gtask, 0, fn, q); 4913 break; 4914 case IFLIB_INTR_RX: 4915 q = &ctx->ifc_rxqs[qid]; 4916 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 4917 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4918 tqg = qgroup_if_io_tqg; 4919 fn = _task_fn_rx; 4920 intr_fast = iflib_fast_intr; 4921 GROUPTASK_INIT(gtask, 0, fn, q); 4922 break; 4923 case IFLIB_INTR_RXTX: 4924 q = &ctx->ifc_rxqs[qid]; 4925 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 4926 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4927 tqg = qgroup_if_io_tqg; 4928 fn = _task_fn_rx; 4929 intr_fast = iflib_fast_intr_rxtx; 4930 GROUPTASK_INIT(gtask, 0, fn, q); 4931 break; 4932 case IFLIB_INTR_ADMIN: 4933 q = ctx; 4934 tqrid = -1; 4935 info = &ctx->ifc_filter_info; 4936 gtask = &ctx->ifc_admin_task; 4937 tqg = qgroup_if_config_tqg; 4938 fn = _task_fn_admin; 4939 intr_fast = iflib_fast_intr_ctx; 4940 break; 4941 default: 4942 panic("unknown net intr type"); 4943 } 4944 4945 info->ifi_filter = filter; 4946 info->ifi_filter_arg = filter_arg; 4947 info->ifi_task = gtask; 4948 info->ifi_ctx = q; 4949 4950 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 4951 if (err != 0) { 4952 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 4953 return (err); 4954 } 4955 if (type == IFLIB_INTR_ADMIN) 4956 return (0); 4957 4958 if (tqrid != -1) { 4959 cpuid = find_nth(ctx, &cpus, qid); 4960 taskqgroup_attach_cpu(tqg, gtask, q, cpuid, irq->ii_rid, name); 4961 } else { 4962 taskqgroup_attach(tqg, gtask, q, tqrid, name); 4963 } 4964 4965 return (0); 4966 } 4967 4968 void 4969 iflib_softirq_alloc_generic(if_ctx_t ctx, int rid, iflib_intr_type_t type, void *arg, int qid, char *name) 4970 { 4971 struct grouptask *gtask; 4972 struct taskqgroup *tqg; 4973 gtask_fn_t *fn; 4974 void *q; 4975 4976 switch (type) { 4977 case IFLIB_INTR_TX: 4978 q = &ctx->ifc_txqs[qid]; 4979 gtask = &ctx->ifc_txqs[qid].ift_task; 4980 tqg = qgroup_if_io_tqg; 4981 fn = _task_fn_tx; 4982 break; 4983 case IFLIB_INTR_RX: 4984 q = &ctx->ifc_rxqs[qid]; 4985 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4986 tqg = qgroup_if_io_tqg; 4987 fn = _task_fn_rx; 4988 break; 4989 case IFLIB_INTR_IOV: 4990 q = ctx; 4991 gtask = &ctx->ifc_vflr_task; 4992 tqg = qgroup_if_config_tqg; 4993 rid = -1; 4994 fn = _task_fn_iov; 4995 break; 4996 default: 4997 panic("unknown net intr type"); 4998 } 4999 GROUPTASK_INIT(gtask, 0, fn, q); 5000 taskqgroup_attach(tqg, gtask, q, rid, name); 5001 } 5002 5003 void 5004 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5005 { 5006 if (irq->ii_tag) 5007 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5008 5009 if (irq->ii_res) 5010 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5011 } 5012 5013 static int 5014 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name) 5015 { 5016 iflib_txq_t txq = ctx->ifc_txqs; 5017 iflib_rxq_t rxq = ctx->ifc_rxqs; 5018 if_irq_t irq = &ctx->ifc_legacy_irq; 5019 iflib_filter_info_t info; 5020 struct grouptask *gtask; 5021 struct taskqgroup *tqg; 5022 gtask_fn_t *fn; 5023 int tqrid; 5024 void *q; 5025 int err; 5026 5027 q = &ctx->ifc_rxqs[0]; 5028 info = &rxq[0].ifr_filter_info; 5029 gtask = &rxq[0].ifr_task; 5030 tqg = qgroup_if_io_tqg; 5031 tqrid = irq->ii_rid = *rid; 5032 fn = _task_fn_rx; 5033 5034 ctx->ifc_flags |= IFC_LEGACY; 5035 info->ifi_filter = filter; 5036 info->ifi_filter_arg = filter_arg; 5037 info->ifi_task = gtask; 5038 info->ifi_ctx = ctx; 5039 5040 /* We allocate a single interrupt resource */ 5041 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5042 return (err); 5043 GROUPTASK_INIT(gtask, 0, fn, q); 5044 taskqgroup_attach(tqg, gtask, q, tqrid, name); 5045 5046 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5047 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, tqrid, "tx"); 5048 return (0); 5049 } 5050 5051 void 5052 iflib_led_create(if_ctx_t ctx) 5053 { 5054 5055 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5056 device_get_nameunit(ctx->ifc_dev)); 5057 } 5058 5059 void 5060 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5061 { 5062 5063 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5064 } 5065 5066 void 5067 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5068 { 5069 5070 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5071 } 5072 5073 void 5074 iflib_admin_intr_deferred(if_ctx_t ctx) 5075 { 5076 #ifdef INVARIANTS 5077 struct grouptask *gtask; 5078 5079 gtask = &ctx->ifc_admin_task; 5080 MPASS(gtask->gt_taskqueue != NULL); 5081 #endif 5082 5083 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5084 } 5085 5086 void 5087 iflib_iov_intr_deferred(if_ctx_t ctx) 5088 { 5089 5090 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5091 } 5092 5093 void 5094 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5095 { 5096 5097 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5098 } 5099 5100 void 5101 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn, 5102 char *name) 5103 { 5104 5105 GROUPTASK_INIT(gtask, 0, fn, ctx); 5106 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5107 } 5108 5109 void 5110 iflib_config_gtask_deinit(struct grouptask *gtask) 5111 { 5112 5113 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5114 } 5115 5116 void 5117 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5118 { 5119 if_t ifp = ctx->ifc_ifp; 5120 iflib_txq_t txq = ctx->ifc_txqs; 5121 5122 if_setbaudrate(ifp, baudrate); 5123 if (baudrate >= IF_Gbps(10)) 5124 ctx->ifc_flags |= IFC_PREFETCH; 5125 5126 /* If link down, disable watchdog */ 5127 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5128 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5129 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5130 } 5131 ctx->ifc_link_state = link_state; 5132 if_link_state_change(ifp, link_state); 5133 } 5134 5135 static int 5136 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5137 { 5138 int credits; 5139 #ifdef INVARIANTS 5140 int credits_pre = txq->ift_cidx_processed; 5141 #endif 5142 5143 if (ctx->isc_txd_credits_update == NULL) 5144 return (0); 5145 5146 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5147 return (0); 5148 5149 txq->ift_processed += credits; 5150 txq->ift_cidx_processed += credits; 5151 5152 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5153 if (txq->ift_cidx_processed >= txq->ift_size) 5154 txq->ift_cidx_processed -= txq->ift_size; 5155 return (credits); 5156 } 5157 5158 static int 5159 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5160 { 5161 5162 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5163 budget)); 5164 } 5165 5166 void 5167 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5168 const char *description, if_int_delay_info_t info, 5169 int offset, int value) 5170 { 5171 info->iidi_ctx = ctx; 5172 info->iidi_offset = offset; 5173 info->iidi_value = value; 5174 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5175 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5176 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5177 info, 0, iflib_sysctl_int_delay, "I", description); 5178 } 5179 5180 struct mtx * 5181 iflib_ctx_lock_get(if_ctx_t ctx) 5182 { 5183 5184 return (&ctx->ifc_mtx); 5185 } 5186 5187 static int 5188 iflib_msix_init(if_ctx_t ctx) 5189 { 5190 device_t dev = ctx->ifc_dev; 5191 if_shared_ctx_t sctx = ctx->ifc_sctx; 5192 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5193 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5194 int iflib_num_tx_queues, iflib_num_rx_queues; 5195 int err, admincnt, bar; 5196 5197 iflib_num_tx_queues = scctx->isc_ntxqsets; 5198 iflib_num_rx_queues = scctx->isc_nrxqsets; 5199 5200 device_printf(dev, "msix_init qsets capped at %d\n", iflib_num_tx_queues); 5201 5202 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5203 admincnt = sctx->isc_admin_intrcnt; 5204 /* Override by tuneable */ 5205 if (scctx->isc_disable_msix) 5206 goto msi; 5207 5208 /* 5209 ** When used in a virtualized environment 5210 ** PCI BUSMASTER capability may not be set 5211 ** so explicity set it here and rewrite 5212 ** the ENABLE in the MSIX control register 5213 ** at this point to cause the host to 5214 ** successfully initialize us. 5215 */ 5216 { 5217 int msix_ctrl, rid; 5218 5219 pci_enable_busmaster(dev); 5220 rid = 0; 5221 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) { 5222 rid += PCIR_MSIX_CTRL; 5223 msix_ctrl = pci_read_config(dev, rid, 2); 5224 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 5225 pci_write_config(dev, rid, msix_ctrl, 2); 5226 } else { 5227 device_printf(dev, "PCIY_MSIX capability not found; " 5228 "or rid %d == 0.\n", rid); 5229 goto msi; 5230 } 5231 } 5232 5233 /* 5234 * bar == -1 => "trust me I know what I'm doing" 5235 * Some drivers are for hardware that is so shoddily 5236 * documented that no one knows which bars are which 5237 * so the developer has to map all bars. This hack 5238 * allows shoddy garbage to use msix in this framework. 5239 */ 5240 if (bar != -1) { 5241 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5242 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5243 if (ctx->ifc_msix_mem == NULL) { 5244 /* May not be enabled */ 5245 device_printf(dev, "Unable to map MSIX table \n"); 5246 goto msi; 5247 } 5248 } 5249 /* First try MSI/X */ 5250 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5251 device_printf(dev, "System has MSIX disabled \n"); 5252 bus_release_resource(dev, SYS_RES_MEMORY, 5253 bar, ctx->ifc_msix_mem); 5254 ctx->ifc_msix_mem = NULL; 5255 goto msi; 5256 } 5257 #if IFLIB_DEBUG 5258 /* use only 1 qset in debug mode */ 5259 queuemsgs = min(msgs - admincnt, 1); 5260 #else 5261 queuemsgs = msgs - admincnt; 5262 #endif 5263 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) == 0) { 5264 #ifdef RSS 5265 queues = imin(queuemsgs, rss_getnumbuckets()); 5266 #else 5267 queues = queuemsgs; 5268 #endif 5269 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 5270 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 5271 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 5272 } else { 5273 device_printf(dev, "Unable to fetch CPU list\n"); 5274 /* Figure out a reasonable auto config value */ 5275 queues = min(queuemsgs, mp_ncpus); 5276 } 5277 #ifdef RSS 5278 /* If we're doing RSS, clamp at the number of RSS buckets */ 5279 if (queues > rss_getnumbuckets()) 5280 queues = rss_getnumbuckets(); 5281 #endif 5282 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 5283 rx_queues = iflib_num_rx_queues; 5284 else 5285 rx_queues = queues; 5286 /* 5287 * We want this to be all logical CPUs by default 5288 */ 5289 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 5290 tx_queues = iflib_num_tx_queues; 5291 else 5292 tx_queues = mp_ncpus; 5293 5294 if (ctx->ifc_sysctl_qs_eq_override == 0) { 5295 #ifdef INVARIANTS 5296 if (tx_queues != rx_queues) 5297 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 5298 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 5299 #endif 5300 tx_queues = min(rx_queues, tx_queues); 5301 rx_queues = min(rx_queues, tx_queues); 5302 } 5303 5304 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 5305 5306 vectors = rx_queues + admincnt; 5307 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 5308 device_printf(dev, 5309 "Using MSIX interrupts with %d vectors\n", vectors); 5310 scctx->isc_vectors = vectors; 5311 scctx->isc_nrxqsets = rx_queues; 5312 scctx->isc_ntxqsets = tx_queues; 5313 scctx->isc_intr = IFLIB_INTR_MSIX; 5314 5315 return (vectors); 5316 } else { 5317 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 5318 } 5319 msi: 5320 vectors = pci_msi_count(dev); 5321 scctx->isc_nrxqsets = 1; 5322 scctx->isc_ntxqsets = 1; 5323 scctx->isc_vectors = vectors; 5324 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 5325 device_printf(dev,"Using an MSI interrupt\n"); 5326 scctx->isc_intr = IFLIB_INTR_MSI; 5327 } else { 5328 device_printf(dev,"Using a Legacy interrupt\n"); 5329 scctx->isc_intr = IFLIB_INTR_LEGACY; 5330 } 5331 5332 return (vectors); 5333 } 5334 5335 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 5336 5337 static int 5338 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 5339 { 5340 int rc; 5341 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 5342 struct sbuf *sb; 5343 char *ring_state = "UNKNOWN"; 5344 5345 /* XXX needed ? */ 5346 rc = sysctl_wire_old_buffer(req, 0); 5347 MPASS(rc == 0); 5348 if (rc != 0) 5349 return (rc); 5350 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 5351 MPASS(sb != NULL); 5352 if (sb == NULL) 5353 return (ENOMEM); 5354 if (state[3] <= 3) 5355 ring_state = ring_states[state[3]]; 5356 5357 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 5358 state[0], state[1], state[2], ring_state); 5359 rc = sbuf_finish(sb); 5360 sbuf_delete(sb); 5361 return(rc); 5362 } 5363 5364 enum iflib_ndesc_handler { 5365 IFLIB_NTXD_HANDLER, 5366 IFLIB_NRXD_HANDLER, 5367 }; 5368 5369 static int 5370 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 5371 { 5372 if_ctx_t ctx = (void *)arg1; 5373 enum iflib_ndesc_handler type = arg2; 5374 char buf[256] = {0}; 5375 qidx_t *ndesc; 5376 char *p, *next; 5377 int nqs, rc, i; 5378 5379 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 5380 5381 nqs = 8; 5382 switch(type) { 5383 case IFLIB_NTXD_HANDLER: 5384 ndesc = ctx->ifc_sysctl_ntxds; 5385 if (ctx->ifc_sctx) 5386 nqs = ctx->ifc_sctx->isc_ntxqs; 5387 break; 5388 case IFLIB_NRXD_HANDLER: 5389 ndesc = ctx->ifc_sysctl_nrxds; 5390 if (ctx->ifc_sctx) 5391 nqs = ctx->ifc_sctx->isc_nrxqs; 5392 break; 5393 } 5394 if (nqs == 0) 5395 nqs = 8; 5396 5397 for (i=0; i<8; i++) { 5398 if (i >= nqs) 5399 break; 5400 if (i) 5401 strcat(buf, ","); 5402 sprintf(strchr(buf, 0), "%d", ndesc[i]); 5403 } 5404 5405 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 5406 if (rc || req->newptr == NULL) 5407 return rc; 5408 5409 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 5410 i++, p = strsep(&next, " ,")) { 5411 ndesc[i] = strtoul(p, NULL, 10); 5412 } 5413 5414 return(rc); 5415 } 5416 5417 #define NAME_BUFLEN 32 5418 static void 5419 iflib_add_device_sysctl_pre(if_ctx_t ctx) 5420 { 5421 device_t dev = iflib_get_dev(ctx); 5422 struct sysctl_oid_list *child, *oid_list; 5423 struct sysctl_ctx_list *ctx_list; 5424 struct sysctl_oid *node; 5425 5426 ctx_list = device_get_sysctl_ctx(dev); 5427 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 5428 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 5429 CTLFLAG_RD, NULL, "IFLIB fields"); 5430 oid_list = SYSCTL_CHILDREN(node); 5431 5432 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 5433 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 5434 "driver version"); 5435 5436 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 5437 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 5438 "# of txqs to use, 0 => use default #"); 5439 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 5440 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 5441 "# of rxqs to use, 0 => use default #"); 5442 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 5443 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 5444 "permit #txq != #rxq"); 5445 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 5446 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 5447 "disable MSIX (default 0)"); 5448 5449 /* XXX change for per-queue sizes */ 5450 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 5451 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 5452 mp_ndesc_handler, "A", 5453 "list of # of tx descriptors to use, 0 = use default #"); 5454 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 5455 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 5456 mp_ndesc_handler, "A", 5457 "list of # of rx descriptors to use, 0 = use default #"); 5458 } 5459 5460 static void 5461 iflib_add_device_sysctl_post(if_ctx_t ctx) 5462 { 5463 if_shared_ctx_t sctx = ctx->ifc_sctx; 5464 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5465 device_t dev = iflib_get_dev(ctx); 5466 struct sysctl_oid_list *child; 5467 struct sysctl_ctx_list *ctx_list; 5468 iflib_fl_t fl; 5469 iflib_txq_t txq; 5470 iflib_rxq_t rxq; 5471 int i, j; 5472 char namebuf[NAME_BUFLEN]; 5473 char *qfmt; 5474 struct sysctl_oid *queue_node, *fl_node, *node; 5475 struct sysctl_oid_list *queue_list, *fl_list; 5476 ctx_list = device_get_sysctl_ctx(dev); 5477 5478 node = ctx->ifc_sysctl_node; 5479 child = SYSCTL_CHILDREN(node); 5480 5481 if (scctx->isc_ntxqsets > 100) 5482 qfmt = "txq%03d"; 5483 else if (scctx->isc_ntxqsets > 10) 5484 qfmt = "txq%02d"; 5485 else 5486 qfmt = "txq%d"; 5487 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 5488 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5489 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5490 CTLFLAG_RD, NULL, "Queue Name"); 5491 queue_list = SYSCTL_CHILDREN(queue_node); 5492 #if MEMORY_LOGGING 5493 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 5494 CTLFLAG_RD, 5495 &txq->ift_dequeued, "total mbufs freed"); 5496 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 5497 CTLFLAG_RD, 5498 &txq->ift_enqueued, "total mbufs enqueued"); 5499 #endif 5500 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 5501 CTLFLAG_RD, 5502 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 5503 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 5504 CTLFLAG_RD, 5505 &txq->ift_pullups, "# of times m_pullup was called"); 5506 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 5507 CTLFLAG_RD, 5508 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 5509 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 5510 CTLFLAG_RD, 5511 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 5512 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 5513 CTLFLAG_RD, 5514 &txq->ift_map_failed, "# of times dma map failed"); 5515 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 5516 CTLFLAG_RD, 5517 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 5518 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 5519 CTLFLAG_RD, 5520 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 5521 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 5522 CTLFLAG_RD, 5523 &txq->ift_pidx, 1, "Producer Index"); 5524 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 5525 CTLFLAG_RD, 5526 &txq->ift_cidx, 1, "Consumer Index"); 5527 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 5528 CTLFLAG_RD, 5529 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 5530 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 5531 CTLFLAG_RD, 5532 &txq->ift_in_use, 1, "descriptors in use"); 5533 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 5534 CTLFLAG_RD, 5535 &txq->ift_processed, "descriptors procesed for clean"); 5536 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 5537 CTLFLAG_RD, 5538 &txq->ift_cleaned, "total cleaned"); 5539 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 5540 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 5541 0, mp_ring_state_handler, "A", "soft ring state"); 5542 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 5543 CTLFLAG_RD, &txq->ift_br->enqueues, 5544 "# of enqueues to the mp_ring for this queue"); 5545 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 5546 CTLFLAG_RD, &txq->ift_br->drops, 5547 "# of drops in the mp_ring for this queue"); 5548 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 5549 CTLFLAG_RD, &txq->ift_br->starts, 5550 "# of normal consumer starts in the mp_ring for this queue"); 5551 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 5552 CTLFLAG_RD, &txq->ift_br->stalls, 5553 "# of consumer stalls in the mp_ring for this queue"); 5554 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 5555 CTLFLAG_RD, &txq->ift_br->restarts, 5556 "# of consumer restarts in the mp_ring for this queue"); 5557 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 5558 CTLFLAG_RD, &txq->ift_br->abdications, 5559 "# of consumer abdications in the mp_ring for this queue"); 5560 } 5561 5562 if (scctx->isc_nrxqsets > 100) 5563 qfmt = "rxq%03d"; 5564 else if (scctx->isc_nrxqsets > 10) 5565 qfmt = "rxq%02d"; 5566 else 5567 qfmt = "rxq%d"; 5568 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 5569 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5570 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5571 CTLFLAG_RD, NULL, "Queue Name"); 5572 queue_list = SYSCTL_CHILDREN(queue_node); 5573 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5574 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 5575 CTLFLAG_RD, 5576 &rxq->ifr_cq_pidx, 1, "Producer Index"); 5577 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 5578 CTLFLAG_RD, 5579 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 5580 } 5581 5582 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 5583 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 5584 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 5585 CTLFLAG_RD, NULL, "freelist Name"); 5586 fl_list = SYSCTL_CHILDREN(fl_node); 5587 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 5588 CTLFLAG_RD, 5589 &fl->ifl_pidx, 1, "Producer Index"); 5590 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 5591 CTLFLAG_RD, 5592 &fl->ifl_cidx, 1, "Consumer Index"); 5593 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 5594 CTLFLAG_RD, 5595 &fl->ifl_credits, 1, "credits available"); 5596 #if MEMORY_LOGGING 5597 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 5598 CTLFLAG_RD, 5599 &fl->ifl_m_enqueued, "mbufs allocated"); 5600 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 5601 CTLFLAG_RD, 5602 &fl->ifl_m_dequeued, "mbufs freed"); 5603 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 5604 CTLFLAG_RD, 5605 &fl->ifl_cl_enqueued, "clusters allocated"); 5606 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 5607 CTLFLAG_RD, 5608 &fl->ifl_cl_dequeued, "clusters freed"); 5609 #endif 5610 5611 } 5612 } 5613 5614 } 5615 5616 #ifndef __NO_STRICT_ALIGNMENT 5617 static struct mbuf * 5618 iflib_fixup_rx(struct mbuf *m) 5619 { 5620 struct mbuf *n; 5621 5622 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 5623 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 5624 m->m_data += ETHER_HDR_LEN; 5625 n = m; 5626 } else { 5627 MGETHDR(n, M_NOWAIT, MT_DATA); 5628 if (n == NULL) { 5629 m_freem(m); 5630 return (NULL); 5631 } 5632 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 5633 m->m_data += ETHER_HDR_LEN; 5634 m->m_len -= ETHER_HDR_LEN; 5635 n->m_len = ETHER_HDR_LEN; 5636 M_MOVE_PKTHDR(n, m); 5637 n->m_next = m; 5638 } 5639 return (n); 5640 } 5641 #endif 5642