1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 120 /* 121 * File organization: 122 * - private structures 123 * - iflib private utility functions 124 * - ifnet functions 125 * - vlan registry and other exported functions 126 * - iflib public core functions 127 * 128 * 129 */ 130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 131 132 struct iflib_txq; 133 typedef struct iflib_txq *iflib_txq_t; 134 struct iflib_rxq; 135 typedef struct iflib_rxq *iflib_rxq_t; 136 struct iflib_fl; 137 typedef struct iflib_fl *iflib_fl_t; 138 139 struct iflib_ctx; 140 141 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 142 static void iflib_timer(void *arg); 143 144 typedef struct iflib_filter_info { 145 driver_filter_t *ifi_filter; 146 void *ifi_filter_arg; 147 struct grouptask *ifi_task; 148 void *ifi_ctx; 149 } *iflib_filter_info_t; 150 151 struct iflib_ctx { 152 KOBJ_FIELDS; 153 /* 154 * Pointer to hardware driver's softc 155 */ 156 void *ifc_softc; 157 device_t ifc_dev; 158 if_t ifc_ifp; 159 160 cpuset_t ifc_cpus; 161 if_shared_ctx_t ifc_sctx; 162 struct if_softc_ctx ifc_softc_ctx; 163 164 struct sx ifc_ctx_sx; 165 struct mtx ifc_state_mtx; 166 167 iflib_txq_t ifc_txqs; 168 iflib_rxq_t ifc_rxqs; 169 uint32_t ifc_if_flags; 170 uint32_t ifc_flags; 171 uint32_t ifc_max_fl_buf_size; 172 uint32_t ifc_rx_mbuf_sz; 173 174 int ifc_link_state; 175 int ifc_watchdog_events; 176 struct cdev *ifc_led_dev; 177 struct resource *ifc_msix_mem; 178 179 struct if_irq ifc_legacy_irq; 180 struct grouptask ifc_admin_task; 181 struct grouptask ifc_vflr_task; 182 struct iflib_filter_info ifc_filter_info; 183 struct ifmedia ifc_media; 184 struct ifmedia *ifc_mediap; 185 186 struct sysctl_oid *ifc_sysctl_node; 187 uint16_t ifc_sysctl_ntxqs; 188 uint16_t ifc_sysctl_nrxqs; 189 uint16_t ifc_sysctl_qs_eq_override; 190 uint16_t ifc_sysctl_rx_budget; 191 uint16_t ifc_sysctl_tx_abdicate; 192 uint16_t ifc_sysctl_core_offset; 193 #define CORE_OFFSET_UNSPECIFIED 0xffff 194 uint8_t ifc_sysctl_separate_txrx; 195 196 qidx_t ifc_sysctl_ntxds[8]; 197 qidx_t ifc_sysctl_nrxds[8]; 198 struct if_txrx ifc_txrx; 199 #define isc_txd_encap ifc_txrx.ift_txd_encap 200 #define isc_txd_flush ifc_txrx.ift_txd_flush 201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 202 #define isc_rxd_available ifc_txrx.ift_rxd_available 203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 209 eventhandler_tag ifc_vlan_attach_event; 210 eventhandler_tag ifc_vlan_detach_event; 211 struct ether_addr ifc_mac; 212 }; 213 214 void * 215 iflib_get_softc(if_ctx_t ctx) 216 { 217 218 return (ctx->ifc_softc); 219 } 220 221 device_t 222 iflib_get_dev(if_ctx_t ctx) 223 { 224 225 return (ctx->ifc_dev); 226 } 227 228 if_t 229 iflib_get_ifp(if_ctx_t ctx) 230 { 231 232 return (ctx->ifc_ifp); 233 } 234 235 struct ifmedia * 236 iflib_get_media(if_ctx_t ctx) 237 { 238 239 return (ctx->ifc_mediap); 240 } 241 242 uint32_t 243 iflib_get_flags(if_ctx_t ctx) 244 { 245 return (ctx->ifc_flags); 246 } 247 248 void 249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 250 { 251 252 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 253 } 254 255 if_softc_ctx_t 256 iflib_get_softc_ctx(if_ctx_t ctx) 257 { 258 259 return (&ctx->ifc_softc_ctx); 260 } 261 262 if_shared_ctx_t 263 iflib_get_sctx(if_ctx_t ctx) 264 { 265 266 return (ctx->ifc_sctx); 267 } 268 269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 272 273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 275 276 typedef struct iflib_sw_rx_desc_array { 277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 278 struct mbuf **ifsd_m; /* pkthdr mbufs */ 279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 281 } iflib_rxsd_array_t; 282 283 typedef struct iflib_sw_tx_desc_array { 284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 286 struct mbuf **ifsd_m; /* pkthdr mbufs */ 287 } if_txsd_vec_t; 288 289 /* magic number that should be high enough for any hardware */ 290 #define IFLIB_MAX_TX_SEGS 128 291 #define IFLIB_RX_COPY_THRESH 128 292 #define IFLIB_MAX_RX_REFRESH 32 293 /* The minimum descriptors per second before we start coalescing */ 294 #define IFLIB_MIN_DESC_SEC 16384 295 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 296 #define IFLIB_QUEUE_IDLE 0 297 #define IFLIB_QUEUE_HUNG 1 298 #define IFLIB_QUEUE_WORKING 2 299 /* maximum number of txqs that can share an rx interrupt */ 300 #define IFLIB_MAX_TX_SHARED_INTR 4 301 302 /* this should really scale with ring size - this is a fairly arbitrary value */ 303 #define TX_BATCH_SIZE 32 304 305 #define IFLIB_RESTART_BUDGET 8 306 307 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 308 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 309 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 310 311 struct iflib_txq { 312 qidx_t ift_in_use; 313 qidx_t ift_cidx; 314 qidx_t ift_cidx_processed; 315 qidx_t ift_pidx; 316 uint8_t ift_gen; 317 uint8_t ift_br_offset; 318 uint16_t ift_npending; 319 uint16_t ift_db_pending; 320 uint16_t ift_rs_pending; 321 /* implicit pad */ 322 uint8_t ift_txd_size[8]; 323 uint64_t ift_processed; 324 uint64_t ift_cleaned; 325 uint64_t ift_cleaned_prev; 326 #if MEMORY_LOGGING 327 uint64_t ift_enqueued; 328 uint64_t ift_dequeued; 329 #endif 330 uint64_t ift_no_tx_dma_setup; 331 uint64_t ift_no_desc_avail; 332 uint64_t ift_mbuf_defrag_failed; 333 uint64_t ift_mbuf_defrag; 334 uint64_t ift_map_failed; 335 uint64_t ift_txd_encap_efbig; 336 uint64_t ift_pullups; 337 uint64_t ift_last_timer_tick; 338 339 struct mtx ift_mtx; 340 struct mtx ift_db_mtx; 341 342 /* constant values */ 343 if_ctx_t ift_ctx; 344 struct ifmp_ring *ift_br; 345 struct grouptask ift_task; 346 qidx_t ift_size; 347 uint16_t ift_id; 348 struct callout ift_timer; 349 350 if_txsd_vec_t ift_sds; 351 uint8_t ift_qstatus; 352 uint8_t ift_closed; 353 uint8_t ift_update_freq; 354 struct iflib_filter_info ift_filter_info; 355 bus_dma_tag_t ift_buf_tag; 356 bus_dma_tag_t ift_tso_buf_tag; 357 iflib_dma_info_t ift_ifdi; 358 #define MTX_NAME_LEN 16 359 char ift_mtx_name[MTX_NAME_LEN]; 360 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 361 #ifdef IFLIB_DIAGNOSTICS 362 uint64_t ift_cpu_exec_count[256]; 363 #endif 364 } __aligned(CACHE_LINE_SIZE); 365 366 struct iflib_fl { 367 qidx_t ifl_cidx; 368 qidx_t ifl_pidx; 369 qidx_t ifl_credits; 370 uint8_t ifl_gen; 371 uint8_t ifl_rxd_size; 372 #if MEMORY_LOGGING 373 uint64_t ifl_m_enqueued; 374 uint64_t ifl_m_dequeued; 375 uint64_t ifl_cl_enqueued; 376 uint64_t ifl_cl_dequeued; 377 #endif 378 /* implicit pad */ 379 bitstr_t *ifl_rx_bitmap; 380 qidx_t ifl_fragidx; 381 /* constant */ 382 qidx_t ifl_size; 383 uint16_t ifl_buf_size; 384 uint16_t ifl_cltype; 385 uma_zone_t ifl_zone; 386 iflib_rxsd_array_t ifl_sds; 387 iflib_rxq_t ifl_rxq; 388 uint8_t ifl_id; 389 bus_dma_tag_t ifl_buf_tag; 390 iflib_dma_info_t ifl_ifdi; 391 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 392 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 393 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 394 } __aligned(CACHE_LINE_SIZE); 395 396 static inline qidx_t 397 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 398 { 399 qidx_t used; 400 401 if (pidx > cidx) 402 used = pidx - cidx; 403 else if (pidx < cidx) 404 used = size - cidx + pidx; 405 else if (gen == 0 && pidx == cidx) 406 used = 0; 407 else if (gen == 1 && pidx == cidx) 408 used = size; 409 else 410 panic("bad state"); 411 412 return (used); 413 } 414 415 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 416 417 #define IDXDIFF(head, tail, wrap) \ 418 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 419 420 struct iflib_rxq { 421 if_ctx_t ifr_ctx; 422 iflib_fl_t ifr_fl; 423 uint64_t ifr_rx_irq; 424 struct pfil_head *pfil; 425 /* 426 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 427 * the command queue consumer index. Otherwise it's unused. 428 */ 429 qidx_t ifr_cq_cidx; 430 uint16_t ifr_id; 431 uint8_t ifr_nfl; 432 uint8_t ifr_ntxqirq; 433 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 434 uint8_t ifr_fl_offset; 435 struct lro_ctrl ifr_lc; 436 struct grouptask ifr_task; 437 struct iflib_filter_info ifr_filter_info; 438 iflib_dma_info_t ifr_ifdi; 439 440 /* dynamically allocate if any drivers need a value substantially larger than this */ 441 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 442 #ifdef IFLIB_DIAGNOSTICS 443 uint64_t ifr_cpu_exec_count[256]; 444 #endif 445 } __aligned(CACHE_LINE_SIZE); 446 447 typedef struct if_rxsd { 448 caddr_t *ifsd_cl; 449 iflib_fl_t ifsd_fl; 450 qidx_t ifsd_cidx; 451 } *if_rxsd_t; 452 453 /* multiple of word size */ 454 #ifdef __LP64__ 455 #define PKT_INFO_SIZE 6 456 #define RXD_INFO_SIZE 5 457 #define PKT_TYPE uint64_t 458 #else 459 #define PKT_INFO_SIZE 11 460 #define RXD_INFO_SIZE 8 461 #define PKT_TYPE uint32_t 462 #endif 463 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 464 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 465 466 typedef struct if_pkt_info_pad { 467 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 468 } *if_pkt_info_pad_t; 469 typedef struct if_rxd_info_pad { 470 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 471 } *if_rxd_info_pad_t; 472 473 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 474 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 475 476 477 static inline void 478 pkt_info_zero(if_pkt_info_t pi) 479 { 480 if_pkt_info_pad_t pi_pad; 481 482 pi_pad = (if_pkt_info_pad_t)pi; 483 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 484 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 485 #ifndef __LP64__ 486 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 487 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 488 #endif 489 } 490 491 static device_method_t iflib_pseudo_methods[] = { 492 DEVMETHOD(device_attach, noop_attach), 493 DEVMETHOD(device_detach, iflib_pseudo_detach), 494 DEVMETHOD_END 495 }; 496 497 driver_t iflib_pseudodriver = { 498 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 499 }; 500 501 static inline void 502 rxd_info_zero(if_rxd_info_t ri) 503 { 504 if_rxd_info_pad_t ri_pad; 505 int i; 506 507 ri_pad = (if_rxd_info_pad_t)ri; 508 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 509 ri_pad->rxd_val[i] = 0; 510 ri_pad->rxd_val[i+1] = 0; 511 ri_pad->rxd_val[i+2] = 0; 512 ri_pad->rxd_val[i+3] = 0; 513 } 514 #ifdef __LP64__ 515 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 516 #endif 517 } 518 519 /* 520 * Only allow a single packet to take up most 1/nth of the tx ring 521 */ 522 #define MAX_SINGLE_PACKET_FRACTION 12 523 #define IF_BAD_DMA (bus_addr_t)-1 524 525 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 526 527 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 528 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 529 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 530 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 531 532 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 533 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 534 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 535 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 536 537 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 538 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 539 540 void 541 iflib_set_detach(if_ctx_t ctx) 542 { 543 STATE_LOCK(ctx); 544 ctx->ifc_flags |= IFC_IN_DETACH; 545 STATE_UNLOCK(ctx); 546 } 547 548 /* Our boot-time initialization hook */ 549 static int iflib_module_event_handler(module_t, int, void *); 550 551 static moduledata_t iflib_moduledata = { 552 "iflib", 553 iflib_module_event_handler, 554 NULL 555 }; 556 557 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 558 MODULE_VERSION(iflib, 1); 559 560 MODULE_DEPEND(iflib, pci, 1, 1, 1); 561 MODULE_DEPEND(iflib, ether, 1, 1, 1); 562 563 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 564 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 565 566 #ifndef IFLIB_DEBUG_COUNTERS 567 #ifdef INVARIANTS 568 #define IFLIB_DEBUG_COUNTERS 1 569 #else 570 #define IFLIB_DEBUG_COUNTERS 0 571 #endif /* !INVARIANTS */ 572 #endif 573 574 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 575 "iflib driver parameters"); 576 577 /* 578 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 579 */ 580 static int iflib_min_tx_latency = 0; 581 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 582 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 583 static int iflib_no_tx_batch = 0; 584 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 585 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 586 587 588 #if IFLIB_DEBUG_COUNTERS 589 590 static int iflib_tx_seen; 591 static int iflib_tx_sent; 592 static int iflib_tx_encap; 593 static int iflib_rx_allocs; 594 static int iflib_fl_refills; 595 static int iflib_fl_refills_large; 596 static int iflib_tx_frees; 597 598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 599 &iflib_tx_seen, 0, "# TX mbufs seen"); 600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 601 &iflib_tx_sent, 0, "# TX mbufs sent"); 602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 603 &iflib_tx_encap, 0, "# TX mbufs encapped"); 604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 605 &iflib_tx_frees, 0, "# TX frees"); 606 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 607 &iflib_rx_allocs, 0, "# RX allocations"); 608 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 609 &iflib_fl_refills, 0, "# refills"); 610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 611 &iflib_fl_refills_large, 0, "# large refills"); 612 613 614 static int iflib_txq_drain_flushing; 615 static int iflib_txq_drain_oactive; 616 static int iflib_txq_drain_notready; 617 618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 619 &iflib_txq_drain_flushing, 0, "# drain flushes"); 620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 621 &iflib_txq_drain_oactive, 0, "# drain oactives"); 622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 623 &iflib_txq_drain_notready, 0, "# drain notready"); 624 625 626 static int iflib_encap_load_mbuf_fail; 627 static int iflib_encap_pad_mbuf_fail; 628 static int iflib_encap_txq_avail_fail; 629 static int iflib_encap_txd_encap_fail; 630 631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 632 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 634 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 636 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 638 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 639 640 static int iflib_task_fn_rxs; 641 static int iflib_rx_intr_enables; 642 static int iflib_fast_intrs; 643 static int iflib_rx_unavail; 644 static int iflib_rx_ctx_inactive; 645 static int iflib_rx_if_input; 646 static int iflib_rxd_flush; 647 648 static int iflib_verbose_debug; 649 650 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 651 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 652 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 653 &iflib_rx_intr_enables, 0, "# RX intr enables"); 654 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 655 &iflib_fast_intrs, 0, "# fast_intr calls"); 656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 657 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 659 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 661 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 663 &iflib_rxd_flush, 0, "# times rxd_flush called"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 665 &iflib_verbose_debug, 0, "enable verbose debugging"); 666 667 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 668 static void 669 iflib_debug_reset(void) 670 { 671 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 672 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 673 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 674 iflib_txq_drain_notready = 675 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 676 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 677 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 678 iflib_rx_unavail = 679 iflib_rx_ctx_inactive = iflib_rx_if_input = 680 iflib_rxd_flush = 0; 681 } 682 683 #else 684 #define DBG_COUNTER_INC(name) 685 static void iflib_debug_reset(void) {} 686 #endif 687 688 #define IFLIB_DEBUG 0 689 690 static void iflib_tx_structures_free(if_ctx_t ctx); 691 static void iflib_rx_structures_free(if_ctx_t ctx); 692 static int iflib_queues_alloc(if_ctx_t ctx); 693 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 694 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 695 static int iflib_qset_structures_setup(if_ctx_t ctx); 696 static int iflib_msix_init(if_ctx_t ctx); 697 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 698 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 699 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 700 #ifdef ALTQ 701 static void iflib_altq_if_start(if_t ifp); 702 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 703 #endif 704 static int iflib_register(if_ctx_t); 705 static void iflib_deregister(if_ctx_t); 706 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 707 static void iflib_init_locked(if_ctx_t ctx); 708 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 709 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 710 static void iflib_ifmp_purge(iflib_txq_t txq); 711 static void _iflib_pre_assert(if_softc_ctx_t scctx); 712 static void iflib_if_init_locked(if_ctx_t ctx); 713 static void iflib_free_intr_mem(if_ctx_t ctx); 714 #ifndef __NO_STRICT_ALIGNMENT 715 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 716 #endif 717 718 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 719 SLIST_HEAD_INITIALIZER(cpu_offsets); 720 struct cpu_offset { 721 SLIST_ENTRY(cpu_offset) entries; 722 cpuset_t set; 723 unsigned int refcount; 724 uint16_t offset; 725 }; 726 static struct mtx cpu_offset_mtx; 727 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 728 MTX_DEF); 729 730 DEBUGNET_DEFINE(iflib); 731 732 #ifdef DEV_NETMAP 733 #include <sys/selinfo.h> 734 #include <net/netmap.h> 735 #include <dev/netmap/netmap_kern.h> 736 737 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 738 739 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 740 741 /* 742 * device-specific sysctl variables: 743 * 744 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 745 * During regular operations the CRC is stripped, but on some 746 * hardware reception of frames not multiple of 64 is slower, 747 * so using crcstrip=0 helps in benchmarks. 748 * 749 * iflib_rx_miss, iflib_rx_miss_bufs: 750 * count packets that might be missed due to lost interrupts. 751 */ 752 SYSCTL_DECL(_dev_netmap); 753 /* 754 * The xl driver by default strips CRCs and we do not override it. 755 */ 756 757 int iflib_crcstrip = 1; 758 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 759 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 760 761 int iflib_rx_miss, iflib_rx_miss_bufs; 762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 763 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 764 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 765 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 766 767 /* 768 * Register/unregister. We are already under netmap lock. 769 * Only called on the first register or the last unregister. 770 */ 771 static int 772 iflib_netmap_register(struct netmap_adapter *na, int onoff) 773 { 774 if_t ifp = na->ifp; 775 if_ctx_t ctx = ifp->if_softc; 776 int status; 777 778 CTX_LOCK(ctx); 779 IFDI_INTR_DISABLE(ctx); 780 781 /* Tell the stack that the interface is no longer active */ 782 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 783 784 if (!CTX_IS_VF(ctx)) 785 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 786 787 /* enable or disable flags and callbacks in na and ifp */ 788 if (onoff) { 789 nm_set_native_flags(na); 790 } else { 791 nm_clear_native_flags(na); 792 } 793 iflib_stop(ctx); 794 iflib_init_locked(ctx); 795 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 796 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 797 if (status) 798 nm_clear_native_flags(na); 799 CTX_UNLOCK(ctx); 800 return (status); 801 } 802 803 static int 804 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 805 { 806 struct netmap_adapter *na = kring->na; 807 u_int const lim = kring->nkr_num_slots - 1; 808 u_int head = kring->rhead; 809 struct netmap_ring *ring = kring->ring; 810 bus_dmamap_t *map; 811 struct if_rxd_update iru; 812 if_ctx_t ctx = rxq->ifr_ctx; 813 iflib_fl_t fl = &rxq->ifr_fl[0]; 814 uint32_t refill_pidx, nic_i; 815 #if IFLIB_DEBUG_COUNTERS 816 int rf_count = 0; 817 #endif 818 819 if (nm_i == head && __predict_true(!init)) 820 return 0; 821 iru_init(&iru, rxq, 0 /* flid */); 822 map = fl->ifl_sds.ifsd_map; 823 refill_pidx = netmap_idx_k2n(kring, nm_i); 824 /* 825 * IMPORTANT: we must leave one free slot in the ring, 826 * so move head back by one unit 827 */ 828 head = nm_prev(head, lim); 829 nic_i = UINT_MAX; 830 DBG_COUNTER_INC(fl_refills); 831 while (nm_i != head) { 832 #if IFLIB_DEBUG_COUNTERS 833 if (++rf_count == 9) 834 DBG_COUNTER_INC(fl_refills_large); 835 #endif 836 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 837 struct netmap_slot *slot = &ring->slot[nm_i]; 838 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 839 uint32_t nic_i_dma = refill_pidx; 840 nic_i = netmap_idx_k2n(kring, nm_i); 841 842 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 843 844 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 845 return netmap_ring_reinit(kring); 846 847 fl->ifl_vm_addrs[tmp_pidx] = addr; 848 if (__predict_false(init)) { 849 netmap_load_map(na, fl->ifl_buf_tag, 850 map[nic_i], addr); 851 } else if (slot->flags & NS_BUF_CHANGED) { 852 /* buffer has changed, reload map */ 853 netmap_reload_map(na, fl->ifl_buf_tag, 854 map[nic_i], addr); 855 } 856 slot->flags &= ~NS_BUF_CHANGED; 857 858 nm_i = nm_next(nm_i, lim); 859 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 860 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 861 continue; 862 863 iru.iru_pidx = refill_pidx; 864 iru.iru_count = tmp_pidx+1; 865 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 866 refill_pidx = nic_i; 867 for (int n = 0; n < iru.iru_count; n++) { 868 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma], 869 BUS_DMASYNC_PREREAD); 870 /* XXX - change this to not use the netmap func*/ 871 nic_i_dma = nm_next(nic_i_dma, lim); 872 } 873 } 874 } 875 kring->nr_hwcur = head; 876 877 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 878 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 879 if (__predict_true(nic_i != UINT_MAX)) { 880 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 881 DBG_COUNTER_INC(rxd_flush); 882 } 883 return (0); 884 } 885 886 /* 887 * Reconcile kernel and user view of the transmit ring. 888 * 889 * All information is in the kring. 890 * Userspace wants to send packets up to the one before kring->rhead, 891 * kernel knows kring->nr_hwcur is the first unsent packet. 892 * 893 * Here we push packets out (as many as possible), and possibly 894 * reclaim buffers from previously completed transmission. 895 * 896 * The caller (netmap) guarantees that there is only one instance 897 * running at any time. Any interference with other driver 898 * methods should be handled by the individual drivers. 899 */ 900 static int 901 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 902 { 903 struct netmap_adapter *na = kring->na; 904 if_t ifp = na->ifp; 905 struct netmap_ring *ring = kring->ring; 906 u_int nm_i; /* index into the netmap kring */ 907 u_int nic_i; /* index into the NIC ring */ 908 u_int n; 909 u_int const lim = kring->nkr_num_slots - 1; 910 u_int const head = kring->rhead; 911 struct if_pkt_info pi; 912 913 /* 914 * interrupts on every tx packet are expensive so request 915 * them every half ring, or where NS_REPORT is set 916 */ 917 u_int report_frequency = kring->nkr_num_slots >> 1; 918 /* device-specific */ 919 if_ctx_t ctx = ifp->if_softc; 920 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 921 922 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 923 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 924 925 /* 926 * First part: process new packets to send. 927 * nm_i is the current index in the netmap kring, 928 * nic_i is the corresponding index in the NIC ring. 929 * 930 * If we have packets to send (nm_i != head) 931 * iterate over the netmap ring, fetch length and update 932 * the corresponding slot in the NIC ring. Some drivers also 933 * need to update the buffer's physical address in the NIC slot 934 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 935 * 936 * The netmap_reload_map() calls is especially expensive, 937 * even when (as in this case) the tag is 0, so do only 938 * when the buffer has actually changed. 939 * 940 * If possible do not set the report/intr bit on all slots, 941 * but only a few times per ring or when NS_REPORT is set. 942 * 943 * Finally, on 10G and faster drivers, it might be useful 944 * to prefetch the next slot and txr entry. 945 */ 946 947 nm_i = kring->nr_hwcur; 948 if (nm_i != head) { /* we have new packets to send */ 949 pkt_info_zero(&pi); 950 pi.ipi_segs = txq->ift_segs; 951 pi.ipi_qsidx = kring->ring_id; 952 nic_i = netmap_idx_k2n(kring, nm_i); 953 954 __builtin_prefetch(&ring->slot[nm_i]); 955 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 956 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 957 958 for (n = 0; nm_i != head; n++) { 959 struct netmap_slot *slot = &ring->slot[nm_i]; 960 u_int len = slot->len; 961 uint64_t paddr; 962 void *addr = PNMB(na, slot, &paddr); 963 int flags = (slot->flags & NS_REPORT || 964 nic_i == 0 || nic_i == report_frequency) ? 965 IPI_TX_INTR : 0; 966 967 /* device-specific */ 968 pi.ipi_len = len; 969 pi.ipi_segs[0].ds_addr = paddr; 970 pi.ipi_segs[0].ds_len = len; 971 pi.ipi_nsegs = 1; 972 pi.ipi_ndescs = 0; 973 pi.ipi_pidx = nic_i; 974 pi.ipi_flags = flags; 975 976 /* Fill the slot in the NIC ring. */ 977 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 978 DBG_COUNTER_INC(tx_encap); 979 980 /* prefetch for next round */ 981 __builtin_prefetch(&ring->slot[nm_i + 1]); 982 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 983 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 984 985 NM_CHECK_ADDR_LEN(na, addr, len); 986 987 if (slot->flags & NS_BUF_CHANGED) { 988 /* buffer has changed, reload map */ 989 netmap_reload_map(na, txq->ift_buf_tag, 990 txq->ift_sds.ifsd_map[nic_i], addr); 991 } 992 /* make sure changes to the buffer are synced */ 993 bus_dmamap_sync(txq->ift_buf_tag, 994 txq->ift_sds.ifsd_map[nic_i], 995 BUS_DMASYNC_PREWRITE); 996 997 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 998 nm_i = nm_next(nm_i, lim); 999 nic_i = nm_next(nic_i, lim); 1000 } 1001 kring->nr_hwcur = nm_i; 1002 1003 /* synchronize the NIC ring */ 1004 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1005 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1006 1007 /* (re)start the tx unit up to slot nic_i (excluded) */ 1008 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1009 } 1010 1011 /* 1012 * Second part: reclaim buffers for completed transmissions. 1013 * 1014 * If there are unclaimed buffers, attempt to reclaim them. 1015 * If none are reclaimed, and TX IRQs are not in use, do an initial 1016 * minimal delay, then trigger the tx handler which will spin in the 1017 * group task queue. 1018 */ 1019 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1020 if (iflib_tx_credits_update(ctx, txq)) { 1021 /* some tx completed, increment avail */ 1022 nic_i = txq->ift_cidx_processed; 1023 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1024 } 1025 } 1026 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1027 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1028 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1029 iflib_timer, txq, txq->ift_timer.c_cpu); 1030 } 1031 return (0); 1032 } 1033 1034 /* 1035 * Reconcile kernel and user view of the receive ring. 1036 * Same as for the txsync, this routine must be efficient. 1037 * The caller guarantees a single invocations, but races against 1038 * the rest of the driver should be handled here. 1039 * 1040 * On call, kring->rhead is the first packet that userspace wants 1041 * to keep, and kring->rcur is the wakeup point. 1042 * The kernel has previously reported packets up to kring->rtail. 1043 * 1044 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1045 * of whether or not we received an interrupt. 1046 */ 1047 static int 1048 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1049 { 1050 struct netmap_adapter *na = kring->na; 1051 struct netmap_ring *ring = kring->ring; 1052 if_t ifp = na->ifp; 1053 iflib_fl_t fl; 1054 uint32_t nm_i; /* index into the netmap ring */ 1055 uint32_t nic_i; /* index into the NIC ring */ 1056 u_int i, n; 1057 u_int const lim = kring->nkr_num_slots - 1; 1058 u_int const head = kring->rhead; 1059 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1060 struct if_rxd_info ri; 1061 1062 if_ctx_t ctx = ifp->if_softc; 1063 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1064 if (head > lim) 1065 return netmap_ring_reinit(kring); 1066 1067 /* 1068 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far. 1069 */ 1070 1071 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1072 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1073 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1074 } 1075 1076 /* 1077 * First part: import newly received packets. 1078 * 1079 * nm_i is the index of the next free slot in the netmap ring, 1080 * nic_i is the index of the next received packet in the NIC ring, 1081 * and they may differ in case if_init() has been called while 1082 * in netmap mode. For the receive ring we have 1083 * 1084 * nic_i = rxr->next_check; 1085 * nm_i = kring->nr_hwtail (previous) 1086 * and 1087 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1088 * 1089 * rxr->next_check is set to 0 on a ring reinit 1090 */ 1091 if (netmap_no_pendintr || force_update) { 1092 int crclen = iflib_crcstrip ? 0 : 4; 1093 int error, avail; 1094 1095 for (i = 0; i < rxq->ifr_nfl; i++) { 1096 fl = &rxq->ifr_fl[i]; 1097 nic_i = fl->ifl_cidx; 1098 nm_i = netmap_idx_n2k(kring, nic_i); 1099 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1100 rxq->ifr_id, nic_i, USHRT_MAX); 1101 for (n = 0; avail > 0; n++, avail--) { 1102 rxd_info_zero(&ri); 1103 ri.iri_frags = rxq->ifr_frags; 1104 ri.iri_qsidx = kring->ring_id; 1105 ri.iri_ifp = ctx->ifc_ifp; 1106 ri.iri_cidx = nic_i; 1107 1108 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1109 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1110 ring->slot[nm_i].flags = 0; 1111 bus_dmamap_sync(fl->ifl_buf_tag, 1112 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1113 nm_i = nm_next(nm_i, lim); 1114 nic_i = nm_next(nic_i, lim); 1115 } 1116 if (n) { /* update the state variables */ 1117 if (netmap_no_pendintr && !force_update) { 1118 /* diagnostics */ 1119 iflib_rx_miss ++; 1120 iflib_rx_miss_bufs += n; 1121 } 1122 fl->ifl_cidx = nic_i; 1123 kring->nr_hwtail = nm_i; 1124 } 1125 kring->nr_kflags &= ~NKR_PENDINTR; 1126 } 1127 } 1128 /* 1129 * Second part: skip past packets that userspace has released. 1130 * (kring->nr_hwcur to head excluded), 1131 * and make the buffers available for reception. 1132 * As usual nm_i is the index in the netmap ring, 1133 * nic_i is the index in the NIC ring, and 1134 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1135 */ 1136 /* XXX not sure how this will work with multiple free lists */ 1137 nm_i = kring->nr_hwcur; 1138 1139 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1140 } 1141 1142 static void 1143 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1144 { 1145 if_ctx_t ctx = na->ifp->if_softc; 1146 1147 CTX_LOCK(ctx); 1148 if (onoff) { 1149 IFDI_INTR_ENABLE(ctx); 1150 } else { 1151 IFDI_INTR_DISABLE(ctx); 1152 } 1153 CTX_UNLOCK(ctx); 1154 } 1155 1156 1157 static int 1158 iflib_netmap_attach(if_ctx_t ctx) 1159 { 1160 struct netmap_adapter na; 1161 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1162 1163 bzero(&na, sizeof(na)); 1164 1165 na.ifp = ctx->ifc_ifp; 1166 na.na_flags = NAF_BDG_MAYSLEEP; 1167 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1168 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1169 1170 na.num_tx_desc = scctx->isc_ntxd[0]; 1171 na.num_rx_desc = scctx->isc_nrxd[0]; 1172 na.nm_txsync = iflib_netmap_txsync; 1173 na.nm_rxsync = iflib_netmap_rxsync; 1174 na.nm_register = iflib_netmap_register; 1175 na.nm_intr = iflib_netmap_intr; 1176 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1177 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1178 return (netmap_attach(&na)); 1179 } 1180 1181 static void 1182 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1183 { 1184 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1185 struct netmap_slot *slot; 1186 1187 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1188 if (slot == NULL) 1189 return; 1190 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1191 1192 /* 1193 * In netmap mode, set the map for the packet buffer. 1194 * NOTE: Some drivers (not this one) also need to set 1195 * the physical buffer address in the NIC ring. 1196 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1197 * netmap slot index, si 1198 */ 1199 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1200 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1201 NMB(na, slot + si)); 1202 } 1203 } 1204 1205 static void 1206 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1207 { 1208 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1209 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1210 struct netmap_slot *slot; 1211 uint32_t nm_i; 1212 1213 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1214 if (slot == NULL) 1215 return; 1216 nm_i = netmap_idx_n2k(kring, 0); 1217 netmap_fl_refill(rxq, kring, nm_i, true); 1218 } 1219 1220 static void 1221 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on) 1222 { 1223 struct netmap_kring *kring; 1224 uint16_t txqid; 1225 1226 txqid = txq->ift_id; 1227 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1228 1229 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1230 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1231 BUS_DMASYNC_POSTREAD); 1232 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1233 netmap_tx_irq(ctx->ifc_ifp, txqid); 1234 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1235 if (hz < 2000) 1236 *reset_on = 1; 1237 else 1238 *reset_on = hz / 1000; 1239 } 1240 } 1241 } 1242 1243 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1244 1245 #else 1246 #define iflib_netmap_txq_init(ctx, txq) 1247 #define iflib_netmap_rxq_init(ctx, rxq) 1248 #define iflib_netmap_detach(ifp) 1249 1250 #define iflib_netmap_attach(ctx) (0) 1251 #define netmap_rx_irq(ifp, qid, budget) (0) 1252 #define netmap_tx_irq(ifp, qid) do {} while (0) 1253 #define iflib_netmap_timer_adjust(ctx, txq, reset_on) 1254 #endif 1255 1256 #if defined(__i386__) || defined(__amd64__) 1257 static __inline void 1258 prefetch(void *x) 1259 { 1260 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1261 } 1262 static __inline void 1263 prefetch2cachelines(void *x) 1264 { 1265 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1266 #if (CACHE_LINE_SIZE < 128) 1267 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1268 #endif 1269 } 1270 #else 1271 #define prefetch(x) 1272 #define prefetch2cachelines(x) 1273 #endif 1274 1275 static void 1276 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1277 { 1278 iflib_fl_t fl; 1279 1280 fl = &rxq->ifr_fl[flid]; 1281 iru->iru_paddrs = fl->ifl_bus_addrs; 1282 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1283 iru->iru_idxs = fl->ifl_rxd_idxs; 1284 iru->iru_qsidx = rxq->ifr_id; 1285 iru->iru_buf_size = fl->ifl_buf_size; 1286 iru->iru_flidx = fl->ifl_id; 1287 } 1288 1289 static void 1290 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1291 { 1292 if (err) 1293 return; 1294 *(bus_addr_t *) arg = segs[0].ds_addr; 1295 } 1296 1297 int 1298 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1299 { 1300 int err; 1301 device_t dev = ctx->ifc_dev; 1302 1303 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1304 align, 0, /* alignment, bounds */ 1305 BUS_SPACE_MAXADDR, /* lowaddr */ 1306 BUS_SPACE_MAXADDR, /* highaddr */ 1307 NULL, NULL, /* filter, filterarg */ 1308 size, /* maxsize */ 1309 1, /* nsegments */ 1310 size, /* maxsegsize */ 1311 BUS_DMA_ALLOCNOW, /* flags */ 1312 NULL, /* lockfunc */ 1313 NULL, /* lockarg */ 1314 &dma->idi_tag); 1315 if (err) { 1316 device_printf(dev, 1317 "%s: bus_dma_tag_create failed: %d\n", 1318 __func__, err); 1319 goto fail_0; 1320 } 1321 1322 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1323 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1324 if (err) { 1325 device_printf(dev, 1326 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1327 __func__, (uintmax_t)size, err); 1328 goto fail_1; 1329 } 1330 1331 dma->idi_paddr = IF_BAD_DMA; 1332 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1333 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1334 if (err || dma->idi_paddr == IF_BAD_DMA) { 1335 device_printf(dev, 1336 "%s: bus_dmamap_load failed: %d\n", 1337 __func__, err); 1338 goto fail_2; 1339 } 1340 1341 dma->idi_size = size; 1342 return (0); 1343 1344 fail_2: 1345 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1346 fail_1: 1347 bus_dma_tag_destroy(dma->idi_tag); 1348 fail_0: 1349 dma->idi_tag = NULL; 1350 1351 return (err); 1352 } 1353 1354 int 1355 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1356 { 1357 if_shared_ctx_t sctx = ctx->ifc_sctx; 1358 1359 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1360 1361 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1362 } 1363 1364 int 1365 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1366 { 1367 int i, err; 1368 iflib_dma_info_t *dmaiter; 1369 1370 dmaiter = dmalist; 1371 for (i = 0; i < count; i++, dmaiter++) { 1372 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1373 break; 1374 } 1375 if (err) 1376 iflib_dma_free_multi(dmalist, i); 1377 return (err); 1378 } 1379 1380 void 1381 iflib_dma_free(iflib_dma_info_t dma) 1382 { 1383 if (dma->idi_tag == NULL) 1384 return; 1385 if (dma->idi_paddr != IF_BAD_DMA) { 1386 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1387 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1388 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1389 dma->idi_paddr = IF_BAD_DMA; 1390 } 1391 if (dma->idi_vaddr != NULL) { 1392 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1393 dma->idi_vaddr = NULL; 1394 } 1395 bus_dma_tag_destroy(dma->idi_tag); 1396 dma->idi_tag = NULL; 1397 } 1398 1399 void 1400 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1401 { 1402 int i; 1403 iflib_dma_info_t *dmaiter = dmalist; 1404 1405 for (i = 0; i < count; i++, dmaiter++) 1406 iflib_dma_free(*dmaiter); 1407 } 1408 1409 #ifdef EARLY_AP_STARTUP 1410 static const int iflib_started = 1; 1411 #else 1412 /* 1413 * We used to abuse the smp_started flag to decide if the queues have been 1414 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1415 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1416 * is set. Run a SYSINIT() strictly after that to just set a usable 1417 * completion flag. 1418 */ 1419 1420 static int iflib_started; 1421 1422 static void 1423 iflib_record_started(void *arg) 1424 { 1425 iflib_started = 1; 1426 } 1427 1428 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1429 iflib_record_started, NULL); 1430 #endif 1431 1432 static int 1433 iflib_fast_intr(void *arg) 1434 { 1435 iflib_filter_info_t info = arg; 1436 struct grouptask *gtask = info->ifi_task; 1437 int result; 1438 1439 if (!iflib_started) 1440 return (FILTER_STRAY); 1441 1442 DBG_COUNTER_INC(fast_intrs); 1443 if (info->ifi_filter != NULL) { 1444 result = info->ifi_filter(info->ifi_filter_arg); 1445 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1446 return (result); 1447 } 1448 1449 GROUPTASK_ENQUEUE(gtask); 1450 return (FILTER_HANDLED); 1451 } 1452 1453 static int 1454 iflib_fast_intr_rxtx(void *arg) 1455 { 1456 iflib_filter_info_t info = arg; 1457 struct grouptask *gtask = info->ifi_task; 1458 if_ctx_t ctx; 1459 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1460 iflib_txq_t txq; 1461 void *sc; 1462 int i, cidx, result; 1463 qidx_t txqid; 1464 bool intr_enable, intr_legacy; 1465 1466 if (!iflib_started) 1467 return (FILTER_STRAY); 1468 1469 DBG_COUNTER_INC(fast_intrs); 1470 if (info->ifi_filter != NULL) { 1471 result = info->ifi_filter(info->ifi_filter_arg); 1472 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1473 return (result); 1474 } 1475 1476 ctx = rxq->ifr_ctx; 1477 sc = ctx->ifc_softc; 1478 intr_enable = false; 1479 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1480 MPASS(rxq->ifr_ntxqirq); 1481 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1482 txqid = rxq->ifr_txqid[i]; 1483 txq = &ctx->ifc_txqs[txqid]; 1484 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1485 BUS_DMASYNC_POSTREAD); 1486 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1487 if (intr_legacy) 1488 intr_enable = true; 1489 else 1490 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1491 continue; 1492 } 1493 GROUPTASK_ENQUEUE(&txq->ift_task); 1494 } 1495 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1496 cidx = rxq->ifr_cq_cidx; 1497 else 1498 cidx = rxq->ifr_fl[0].ifl_cidx; 1499 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1500 GROUPTASK_ENQUEUE(gtask); 1501 else { 1502 if (intr_legacy) 1503 intr_enable = true; 1504 else 1505 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1506 DBG_COUNTER_INC(rx_intr_enables); 1507 } 1508 if (intr_enable) 1509 IFDI_INTR_ENABLE(ctx); 1510 return (FILTER_HANDLED); 1511 } 1512 1513 1514 static int 1515 iflib_fast_intr_ctx(void *arg) 1516 { 1517 iflib_filter_info_t info = arg; 1518 struct grouptask *gtask = info->ifi_task; 1519 int result; 1520 1521 if (!iflib_started) 1522 return (FILTER_STRAY); 1523 1524 DBG_COUNTER_INC(fast_intrs); 1525 if (info->ifi_filter != NULL) { 1526 result = info->ifi_filter(info->ifi_filter_arg); 1527 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1528 return (result); 1529 } 1530 1531 GROUPTASK_ENQUEUE(gtask); 1532 return (FILTER_HANDLED); 1533 } 1534 1535 static int 1536 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1537 driver_filter_t filter, driver_intr_t handler, void *arg, 1538 const char *name) 1539 { 1540 struct resource *res; 1541 void *tag = NULL; 1542 device_t dev = ctx->ifc_dev; 1543 int flags, i, rc; 1544 1545 flags = RF_ACTIVE; 1546 if (ctx->ifc_flags & IFC_LEGACY) 1547 flags |= RF_SHAREABLE; 1548 MPASS(rid < 512); 1549 i = rid; 1550 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1551 if (res == NULL) { 1552 device_printf(dev, 1553 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1554 return (ENOMEM); 1555 } 1556 irq->ii_res = res; 1557 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1558 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1559 filter, handler, arg, &tag); 1560 if (rc != 0) { 1561 device_printf(dev, 1562 "failed to setup interrupt for rid %d, name %s: %d\n", 1563 rid, name ? name : "unknown", rc); 1564 return (rc); 1565 } else if (name) 1566 bus_describe_intr(dev, res, tag, "%s", name); 1567 1568 irq->ii_tag = tag; 1569 return (0); 1570 } 1571 1572 /********************************************************************* 1573 * 1574 * Allocate DMA resources for TX buffers as well as memory for the TX 1575 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1576 * iflib_sw_tx_desc_array structure, storing all the information that 1577 * is needed to transmit a packet on the wire. This is called only 1578 * once at attach, setup is done every reset. 1579 * 1580 **********************************************************************/ 1581 static int 1582 iflib_txsd_alloc(iflib_txq_t txq) 1583 { 1584 if_ctx_t ctx = txq->ift_ctx; 1585 if_shared_ctx_t sctx = ctx->ifc_sctx; 1586 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1587 device_t dev = ctx->ifc_dev; 1588 bus_size_t tsomaxsize; 1589 int err, nsegments, ntsosegments; 1590 bool tso; 1591 1592 nsegments = scctx->isc_tx_nsegments; 1593 ntsosegments = scctx->isc_tx_tso_segments_max; 1594 tsomaxsize = scctx->isc_tx_tso_size_max; 1595 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1596 tsomaxsize += sizeof(struct ether_vlan_header); 1597 MPASS(scctx->isc_ntxd[0] > 0); 1598 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1599 MPASS(nsegments > 0); 1600 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1601 MPASS(ntsosegments > 0); 1602 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1603 } 1604 1605 /* 1606 * Set up DMA tags for TX buffers. 1607 */ 1608 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1609 1, 0, /* alignment, bounds */ 1610 BUS_SPACE_MAXADDR, /* lowaddr */ 1611 BUS_SPACE_MAXADDR, /* highaddr */ 1612 NULL, NULL, /* filter, filterarg */ 1613 sctx->isc_tx_maxsize, /* maxsize */ 1614 nsegments, /* nsegments */ 1615 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1616 0, /* flags */ 1617 NULL, /* lockfunc */ 1618 NULL, /* lockfuncarg */ 1619 &txq->ift_buf_tag))) { 1620 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1621 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1622 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1623 goto fail; 1624 } 1625 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1626 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1627 1, 0, /* alignment, bounds */ 1628 BUS_SPACE_MAXADDR, /* lowaddr */ 1629 BUS_SPACE_MAXADDR, /* highaddr */ 1630 NULL, NULL, /* filter, filterarg */ 1631 tsomaxsize, /* maxsize */ 1632 ntsosegments, /* nsegments */ 1633 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1634 0, /* flags */ 1635 NULL, /* lockfunc */ 1636 NULL, /* lockfuncarg */ 1637 &txq->ift_tso_buf_tag))) { 1638 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1639 err); 1640 goto fail; 1641 } 1642 1643 /* Allocate memory for the TX mbuf map. */ 1644 if (!(txq->ift_sds.ifsd_m = 1645 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1646 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1647 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1648 err = ENOMEM; 1649 goto fail; 1650 } 1651 1652 /* 1653 * Create the DMA maps for TX buffers. 1654 */ 1655 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1656 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1657 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1658 device_printf(dev, 1659 "Unable to allocate TX buffer DMA map memory\n"); 1660 err = ENOMEM; 1661 goto fail; 1662 } 1663 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1664 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1665 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1666 device_printf(dev, 1667 "Unable to allocate TSO TX buffer map memory\n"); 1668 err = ENOMEM; 1669 goto fail; 1670 } 1671 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1672 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1673 &txq->ift_sds.ifsd_map[i]); 1674 if (err != 0) { 1675 device_printf(dev, "Unable to create TX DMA map\n"); 1676 goto fail; 1677 } 1678 if (!tso) 1679 continue; 1680 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1681 &txq->ift_sds.ifsd_tso_map[i]); 1682 if (err != 0) { 1683 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1684 goto fail; 1685 } 1686 } 1687 return (0); 1688 fail: 1689 /* We free all, it handles case where we are in the middle */ 1690 iflib_tx_structures_free(ctx); 1691 return (err); 1692 } 1693 1694 static void 1695 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1696 { 1697 bus_dmamap_t map; 1698 1699 if (txq->ift_sds.ifsd_map != NULL) { 1700 map = txq->ift_sds.ifsd_map[i]; 1701 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1702 bus_dmamap_unload(txq->ift_buf_tag, map); 1703 bus_dmamap_destroy(txq->ift_buf_tag, map); 1704 txq->ift_sds.ifsd_map[i] = NULL; 1705 } 1706 1707 if (txq->ift_sds.ifsd_tso_map != NULL) { 1708 map = txq->ift_sds.ifsd_tso_map[i]; 1709 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1710 BUS_DMASYNC_POSTWRITE); 1711 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1712 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1713 txq->ift_sds.ifsd_tso_map[i] = NULL; 1714 } 1715 } 1716 1717 static void 1718 iflib_txq_destroy(iflib_txq_t txq) 1719 { 1720 if_ctx_t ctx = txq->ift_ctx; 1721 1722 for (int i = 0; i < txq->ift_size; i++) 1723 iflib_txsd_destroy(ctx, txq, i); 1724 1725 if (txq->ift_br != NULL) { 1726 ifmp_ring_free(txq->ift_br); 1727 txq->ift_br = NULL; 1728 } 1729 1730 mtx_destroy(&txq->ift_mtx); 1731 1732 if (txq->ift_sds.ifsd_map != NULL) { 1733 free(txq->ift_sds.ifsd_map, M_IFLIB); 1734 txq->ift_sds.ifsd_map = NULL; 1735 } 1736 if (txq->ift_sds.ifsd_tso_map != NULL) { 1737 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1738 txq->ift_sds.ifsd_tso_map = NULL; 1739 } 1740 if (txq->ift_sds.ifsd_m != NULL) { 1741 free(txq->ift_sds.ifsd_m, M_IFLIB); 1742 txq->ift_sds.ifsd_m = NULL; 1743 } 1744 if (txq->ift_buf_tag != NULL) { 1745 bus_dma_tag_destroy(txq->ift_buf_tag); 1746 txq->ift_buf_tag = NULL; 1747 } 1748 if (txq->ift_tso_buf_tag != NULL) { 1749 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1750 txq->ift_tso_buf_tag = NULL; 1751 } 1752 if (txq->ift_ifdi != NULL) { 1753 free(txq->ift_ifdi, M_IFLIB); 1754 } 1755 } 1756 1757 static void 1758 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1759 { 1760 struct mbuf **mp; 1761 1762 mp = &txq->ift_sds.ifsd_m[i]; 1763 if (*mp == NULL) 1764 return; 1765 1766 if (txq->ift_sds.ifsd_map != NULL) { 1767 bus_dmamap_sync(txq->ift_buf_tag, 1768 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1769 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1770 } 1771 if (txq->ift_sds.ifsd_tso_map != NULL) { 1772 bus_dmamap_sync(txq->ift_tso_buf_tag, 1773 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1774 bus_dmamap_unload(txq->ift_tso_buf_tag, 1775 txq->ift_sds.ifsd_tso_map[i]); 1776 } 1777 m_free(*mp); 1778 DBG_COUNTER_INC(tx_frees); 1779 *mp = NULL; 1780 } 1781 1782 static int 1783 iflib_txq_setup(iflib_txq_t txq) 1784 { 1785 if_ctx_t ctx = txq->ift_ctx; 1786 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1787 if_shared_ctx_t sctx = ctx->ifc_sctx; 1788 iflib_dma_info_t di; 1789 int i; 1790 1791 /* Set number of descriptors available */ 1792 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1793 /* XXX make configurable */ 1794 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1795 1796 /* Reset indices */ 1797 txq->ift_cidx_processed = 0; 1798 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1799 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1800 1801 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1802 bzero((void *)di->idi_vaddr, di->idi_size); 1803 1804 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1805 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1806 bus_dmamap_sync(di->idi_tag, di->idi_map, 1807 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1808 return (0); 1809 } 1810 1811 /********************************************************************* 1812 * 1813 * Allocate DMA resources for RX buffers as well as memory for the RX 1814 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1815 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1816 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1817 * Since we use use one entry in iflib_sw_rx_desc_array per received 1818 * packet, the maximum number of entries we'll need is equal to the 1819 * number of hardware receive descriptors that we've allocated. 1820 * 1821 **********************************************************************/ 1822 static int 1823 iflib_rxsd_alloc(iflib_rxq_t rxq) 1824 { 1825 if_ctx_t ctx = rxq->ifr_ctx; 1826 if_shared_ctx_t sctx = ctx->ifc_sctx; 1827 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1828 device_t dev = ctx->ifc_dev; 1829 iflib_fl_t fl; 1830 int err; 1831 1832 MPASS(scctx->isc_nrxd[0] > 0); 1833 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1834 1835 fl = rxq->ifr_fl; 1836 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1837 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1838 /* Set up DMA tag for RX buffers. */ 1839 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1840 1, 0, /* alignment, bounds */ 1841 BUS_SPACE_MAXADDR, /* lowaddr */ 1842 BUS_SPACE_MAXADDR, /* highaddr */ 1843 NULL, NULL, /* filter, filterarg */ 1844 sctx->isc_rx_maxsize, /* maxsize */ 1845 sctx->isc_rx_nsegments, /* nsegments */ 1846 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1847 0, /* flags */ 1848 NULL, /* lockfunc */ 1849 NULL, /* lockarg */ 1850 &fl->ifl_buf_tag); 1851 if (err) { 1852 device_printf(dev, 1853 "Unable to allocate RX DMA tag: %d\n", err); 1854 goto fail; 1855 } 1856 1857 /* Allocate memory for the RX mbuf map. */ 1858 if (!(fl->ifl_sds.ifsd_m = 1859 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1860 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1861 device_printf(dev, 1862 "Unable to allocate RX mbuf map memory\n"); 1863 err = ENOMEM; 1864 goto fail; 1865 } 1866 1867 /* Allocate memory for the direct RX cluster pointer map. */ 1868 if (!(fl->ifl_sds.ifsd_cl = 1869 (caddr_t *) malloc(sizeof(caddr_t) * 1870 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1871 device_printf(dev, 1872 "Unable to allocate RX cluster map memory\n"); 1873 err = ENOMEM; 1874 goto fail; 1875 } 1876 1877 /* Allocate memory for the RX cluster bus address map. */ 1878 if (!(fl->ifl_sds.ifsd_ba = 1879 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1880 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1881 device_printf(dev, 1882 "Unable to allocate RX bus address map memory\n"); 1883 err = ENOMEM; 1884 goto fail; 1885 } 1886 1887 /* 1888 * Create the DMA maps for RX buffers. 1889 */ 1890 if (!(fl->ifl_sds.ifsd_map = 1891 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1892 device_printf(dev, 1893 "Unable to allocate RX buffer DMA map memory\n"); 1894 err = ENOMEM; 1895 goto fail; 1896 } 1897 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1898 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1899 &fl->ifl_sds.ifsd_map[i]); 1900 if (err != 0) { 1901 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1902 goto fail; 1903 } 1904 } 1905 } 1906 return (0); 1907 1908 fail: 1909 iflib_rx_structures_free(ctx); 1910 return (err); 1911 } 1912 1913 1914 /* 1915 * Internal service routines 1916 */ 1917 1918 struct rxq_refill_cb_arg { 1919 int error; 1920 bus_dma_segment_t seg; 1921 int nseg; 1922 }; 1923 1924 static void 1925 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1926 { 1927 struct rxq_refill_cb_arg *cb_arg = arg; 1928 1929 cb_arg->error = error; 1930 cb_arg->seg = segs[0]; 1931 cb_arg->nseg = nseg; 1932 } 1933 1934 /** 1935 * _iflib_fl_refill - refill an rxq free-buffer list 1936 * @ctx: the iflib context 1937 * @fl: the free list to refill 1938 * @count: the number of new buffers to allocate 1939 * 1940 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 1941 * The caller must assure that @count does not exceed the queue's capacity. 1942 */ 1943 static void 1944 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1945 { 1946 struct if_rxd_update iru; 1947 struct rxq_refill_cb_arg cb_arg; 1948 struct mbuf *m; 1949 caddr_t cl, *sd_cl; 1950 struct mbuf **sd_m; 1951 bus_dmamap_t *sd_map; 1952 bus_addr_t bus_addr, *sd_ba; 1953 int err, frag_idx, i, idx, n, pidx; 1954 qidx_t credits; 1955 1956 sd_m = fl->ifl_sds.ifsd_m; 1957 sd_map = fl->ifl_sds.ifsd_map; 1958 sd_cl = fl->ifl_sds.ifsd_cl; 1959 sd_ba = fl->ifl_sds.ifsd_ba; 1960 pidx = fl->ifl_pidx; 1961 idx = pidx; 1962 frag_idx = fl->ifl_fragidx; 1963 credits = fl->ifl_credits; 1964 1965 i = 0; 1966 n = count; 1967 MPASS(n > 0); 1968 MPASS(credits + n <= fl->ifl_size); 1969 1970 if (pidx < fl->ifl_cidx) 1971 MPASS(pidx + n <= fl->ifl_cidx); 1972 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1973 MPASS(fl->ifl_gen == 0); 1974 if (pidx > fl->ifl_cidx) 1975 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1976 1977 DBG_COUNTER_INC(fl_refills); 1978 if (n > 8) 1979 DBG_COUNTER_INC(fl_refills_large); 1980 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1981 while (n--) { 1982 /* 1983 * We allocate an uninitialized mbuf + cluster, mbuf is 1984 * initialized after rx. 1985 * 1986 * If the cluster is still set then we know a minimum sized packet was received 1987 */ 1988 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 1989 &frag_idx); 1990 if (frag_idx < 0) 1991 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1992 MPASS(frag_idx >= 0); 1993 if ((cl = sd_cl[frag_idx]) == NULL) { 1994 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1995 break; 1996 1997 cb_arg.error = 0; 1998 MPASS(sd_map != NULL); 1999 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2000 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2001 BUS_DMA_NOWAIT); 2002 if (err != 0 || cb_arg.error) { 2003 /* 2004 * !zone_pack ? 2005 */ 2006 if (fl->ifl_zone == zone_pack) 2007 uma_zfree(fl->ifl_zone, cl); 2008 break; 2009 } 2010 2011 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2012 sd_cl[frag_idx] = cl; 2013 #if MEMORY_LOGGING 2014 fl->ifl_cl_enqueued++; 2015 #endif 2016 } else { 2017 bus_addr = sd_ba[frag_idx]; 2018 } 2019 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2020 BUS_DMASYNC_PREREAD); 2021 2022 if (sd_m[frag_idx] == NULL) { 2023 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 2024 break; 2025 } 2026 sd_m[frag_idx] = m; 2027 } 2028 bit_set(fl->ifl_rx_bitmap, frag_idx); 2029 #if MEMORY_LOGGING 2030 fl->ifl_m_enqueued++; 2031 #endif 2032 2033 DBG_COUNTER_INC(rx_allocs); 2034 fl->ifl_rxd_idxs[i] = frag_idx; 2035 fl->ifl_bus_addrs[i] = bus_addr; 2036 fl->ifl_vm_addrs[i] = cl; 2037 credits++; 2038 i++; 2039 MPASS(credits <= fl->ifl_size); 2040 if (++idx == fl->ifl_size) { 2041 fl->ifl_gen = 1; 2042 idx = 0; 2043 } 2044 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2045 iru.iru_pidx = pidx; 2046 iru.iru_count = i; 2047 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2048 i = 0; 2049 pidx = idx; 2050 fl->ifl_pidx = idx; 2051 fl->ifl_credits = credits; 2052 } 2053 } 2054 2055 if (i) { 2056 iru.iru_pidx = pidx; 2057 iru.iru_count = i; 2058 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2059 fl->ifl_pidx = idx; 2060 fl->ifl_credits = credits; 2061 } 2062 DBG_COUNTER_INC(rxd_flush); 2063 if (fl->ifl_pidx == 0) 2064 pidx = fl->ifl_size - 1; 2065 else 2066 pidx = fl->ifl_pidx - 1; 2067 2068 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2069 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2070 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2071 fl->ifl_fragidx = frag_idx; 2072 } 2073 2074 static __inline void 2075 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2076 { 2077 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2078 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2079 #ifdef INVARIANTS 2080 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2081 #endif 2082 2083 MPASS(fl->ifl_credits <= fl->ifl_size); 2084 MPASS(reclaimable == delta); 2085 2086 if (reclaimable > 0) 2087 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2088 } 2089 2090 uint8_t 2091 iflib_in_detach(if_ctx_t ctx) 2092 { 2093 bool in_detach; 2094 2095 STATE_LOCK(ctx); 2096 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2097 STATE_UNLOCK(ctx); 2098 return (in_detach); 2099 } 2100 2101 static void 2102 iflib_fl_bufs_free(iflib_fl_t fl) 2103 { 2104 iflib_dma_info_t idi = fl->ifl_ifdi; 2105 bus_dmamap_t sd_map; 2106 uint32_t i; 2107 2108 for (i = 0; i < fl->ifl_size; i++) { 2109 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2110 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2111 2112 if (*sd_cl != NULL) { 2113 sd_map = fl->ifl_sds.ifsd_map[i]; 2114 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2115 BUS_DMASYNC_POSTREAD); 2116 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2117 if (*sd_cl != NULL) 2118 uma_zfree(fl->ifl_zone, *sd_cl); 2119 if (*sd_m != NULL) { 2120 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2121 uma_zfree(zone_mbuf, *sd_m); 2122 } 2123 } else { 2124 MPASS(*sd_cl == NULL); 2125 MPASS(*sd_m == NULL); 2126 } 2127 #if MEMORY_LOGGING 2128 fl->ifl_m_dequeued++; 2129 fl->ifl_cl_dequeued++; 2130 #endif 2131 *sd_cl = NULL; 2132 *sd_m = NULL; 2133 } 2134 #ifdef INVARIANTS 2135 for (i = 0; i < fl->ifl_size; i++) { 2136 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2137 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2138 } 2139 #endif 2140 /* 2141 * Reset free list values 2142 */ 2143 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2144 bzero(idi->idi_vaddr, idi->idi_size); 2145 } 2146 2147 /********************************************************************* 2148 * 2149 * Initialize a free list and its buffers. 2150 * 2151 **********************************************************************/ 2152 static int 2153 iflib_fl_setup(iflib_fl_t fl) 2154 { 2155 iflib_rxq_t rxq = fl->ifl_rxq; 2156 if_ctx_t ctx = rxq->ifr_ctx; 2157 2158 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2159 /* 2160 ** Free current RX buffer structs and their mbufs 2161 */ 2162 iflib_fl_bufs_free(fl); 2163 /* Now replenish the mbufs */ 2164 MPASS(fl->ifl_credits == 0); 2165 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2166 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2167 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2168 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2169 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2170 2171 2172 /* avoid pre-allocating zillions of clusters to an idle card 2173 * potentially speeding up attach 2174 */ 2175 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2176 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2177 if (min(128, fl->ifl_size) != fl->ifl_credits) 2178 return (ENOBUFS); 2179 /* 2180 * handle failure 2181 */ 2182 MPASS(rxq != NULL); 2183 MPASS(fl->ifl_ifdi != NULL); 2184 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2185 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2186 return (0); 2187 } 2188 2189 /********************************************************************* 2190 * 2191 * Free receive ring data structures 2192 * 2193 **********************************************************************/ 2194 static void 2195 iflib_rx_sds_free(iflib_rxq_t rxq) 2196 { 2197 iflib_fl_t fl; 2198 int i, j; 2199 2200 if (rxq->ifr_fl != NULL) { 2201 for (i = 0; i < rxq->ifr_nfl; i++) { 2202 fl = &rxq->ifr_fl[i]; 2203 if (fl->ifl_buf_tag != NULL) { 2204 if (fl->ifl_sds.ifsd_map != NULL) { 2205 for (j = 0; j < fl->ifl_size; j++) { 2206 bus_dmamap_sync( 2207 fl->ifl_buf_tag, 2208 fl->ifl_sds.ifsd_map[j], 2209 BUS_DMASYNC_POSTREAD); 2210 bus_dmamap_unload( 2211 fl->ifl_buf_tag, 2212 fl->ifl_sds.ifsd_map[j]); 2213 bus_dmamap_destroy( 2214 fl->ifl_buf_tag, 2215 fl->ifl_sds.ifsd_map[j]); 2216 } 2217 } 2218 bus_dma_tag_destroy(fl->ifl_buf_tag); 2219 fl->ifl_buf_tag = NULL; 2220 } 2221 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2222 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2223 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2224 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2225 fl->ifl_sds.ifsd_m = NULL; 2226 fl->ifl_sds.ifsd_cl = NULL; 2227 fl->ifl_sds.ifsd_ba = NULL; 2228 fl->ifl_sds.ifsd_map = NULL; 2229 } 2230 free(rxq->ifr_fl, M_IFLIB); 2231 rxq->ifr_fl = NULL; 2232 free(rxq->ifr_ifdi, M_IFLIB); 2233 rxq->ifr_ifdi = NULL; 2234 rxq->ifr_cq_cidx = 0; 2235 } 2236 } 2237 2238 /* 2239 * Timer routine 2240 */ 2241 static void 2242 iflib_timer(void *arg) 2243 { 2244 iflib_txq_t txq = arg; 2245 if_ctx_t ctx = txq->ift_ctx; 2246 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2247 uint64_t this_tick = ticks; 2248 uint32_t reset_on = hz / 2; 2249 2250 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2251 return; 2252 2253 /* 2254 ** Check on the state of the TX queue(s), this 2255 ** can be done without the lock because its RO 2256 ** and the HUNG state will be static if set. 2257 */ 2258 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2259 txq->ift_last_timer_tick = this_tick; 2260 IFDI_TIMER(ctx, txq->ift_id); 2261 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2262 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2263 (sctx->isc_pause_frames == 0))) 2264 goto hung; 2265 2266 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2267 ifmp_ring_is_stalled(txq->ift_br)) { 2268 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down")); 2269 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2270 } 2271 txq->ift_cleaned_prev = txq->ift_cleaned; 2272 } 2273 #ifdef DEV_NETMAP 2274 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2275 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 2276 #endif 2277 /* handle any laggards */ 2278 if (txq->ift_db_pending) 2279 GROUPTASK_ENQUEUE(&txq->ift_task); 2280 2281 sctx->isc_pause_frames = 0; 2282 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2283 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2284 return; 2285 2286 hung: 2287 device_printf(ctx->ifc_dev, 2288 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2289 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2290 STATE_LOCK(ctx); 2291 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2292 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2293 iflib_admin_intr_deferred(ctx); 2294 STATE_UNLOCK(ctx); 2295 } 2296 2297 static void 2298 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2299 { 2300 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2301 2302 /* 2303 * XXX don't set the max_frame_size to larger 2304 * than the hardware can handle 2305 */ 2306 if (sctx->isc_max_frame_size <= MCLBYTES) 2307 ctx->ifc_rx_mbuf_sz = MCLBYTES; 2308 else 2309 ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE; 2310 } 2311 2312 uint32_t 2313 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2314 { 2315 2316 return (ctx->ifc_rx_mbuf_sz); 2317 } 2318 2319 static void 2320 iflib_init_locked(if_ctx_t ctx) 2321 { 2322 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2323 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2324 if_t ifp = ctx->ifc_ifp; 2325 iflib_fl_t fl; 2326 iflib_txq_t txq; 2327 iflib_rxq_t rxq; 2328 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2329 2330 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2331 IFDI_INTR_DISABLE(ctx); 2332 2333 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2334 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2335 /* Set hardware offload abilities */ 2336 if_clearhwassist(ifp); 2337 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2338 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2339 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2340 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2341 if (if_getcapenable(ifp) & IFCAP_TSO4) 2342 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2343 if (if_getcapenable(ifp) & IFCAP_TSO6) 2344 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2345 2346 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2347 CALLOUT_LOCK(txq); 2348 callout_stop(&txq->ift_timer); 2349 CALLOUT_UNLOCK(txq); 2350 iflib_netmap_txq_init(ctx, txq); 2351 } 2352 2353 /* 2354 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2355 * that drivers can use the value when setting up the hardware receive 2356 * buffers. 2357 */ 2358 iflib_calc_rx_mbuf_sz(ctx); 2359 2360 #ifdef INVARIANTS 2361 i = if_getdrvflags(ifp); 2362 #endif 2363 IFDI_INIT(ctx); 2364 MPASS(if_getdrvflags(ifp) == i); 2365 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2366 /* XXX this should really be done on a per-queue basis */ 2367 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2368 MPASS(rxq->ifr_id == i); 2369 iflib_netmap_rxq_init(ctx, rxq); 2370 continue; 2371 } 2372 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2373 if (iflib_fl_setup(fl)) { 2374 device_printf(ctx->ifc_dev, 2375 "setting up free list %d failed - " 2376 "check cluster settings\n", j); 2377 goto done; 2378 } 2379 } 2380 } 2381 done: 2382 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2383 IFDI_INTR_ENABLE(ctx); 2384 txq = ctx->ifc_txqs; 2385 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2386 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2387 txq->ift_timer.c_cpu); 2388 } 2389 2390 static int 2391 iflib_media_change(if_t ifp) 2392 { 2393 if_ctx_t ctx = if_getsoftc(ifp); 2394 int err; 2395 2396 CTX_LOCK(ctx); 2397 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2398 iflib_init_locked(ctx); 2399 CTX_UNLOCK(ctx); 2400 return (err); 2401 } 2402 2403 static void 2404 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2405 { 2406 if_ctx_t ctx = if_getsoftc(ifp); 2407 2408 CTX_LOCK(ctx); 2409 IFDI_UPDATE_ADMIN_STATUS(ctx); 2410 IFDI_MEDIA_STATUS(ctx, ifmr); 2411 CTX_UNLOCK(ctx); 2412 } 2413 2414 void 2415 iflib_stop(if_ctx_t ctx) 2416 { 2417 iflib_txq_t txq = ctx->ifc_txqs; 2418 iflib_rxq_t rxq = ctx->ifc_rxqs; 2419 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2420 if_shared_ctx_t sctx = ctx->ifc_sctx; 2421 iflib_dma_info_t di; 2422 iflib_fl_t fl; 2423 int i, j; 2424 2425 /* Tell the stack that the interface is no longer active */ 2426 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2427 2428 IFDI_INTR_DISABLE(ctx); 2429 DELAY(1000); 2430 IFDI_STOP(ctx); 2431 DELAY(1000); 2432 2433 iflib_debug_reset(); 2434 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2435 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2436 /* make sure all transmitters have completed before proceeding XXX */ 2437 2438 CALLOUT_LOCK(txq); 2439 callout_stop(&txq->ift_timer); 2440 CALLOUT_UNLOCK(txq); 2441 2442 /* clean any enqueued buffers */ 2443 iflib_ifmp_purge(txq); 2444 /* Free any existing tx buffers. */ 2445 for (j = 0; j < txq->ift_size; j++) { 2446 iflib_txsd_free(ctx, txq, j); 2447 } 2448 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2449 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2450 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2451 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2452 txq->ift_pullups = 0; 2453 ifmp_ring_reset_stats(txq->ift_br); 2454 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2455 bzero((void *)di->idi_vaddr, di->idi_size); 2456 } 2457 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2458 /* make sure all transmitters have completed before proceeding XXX */ 2459 2460 rxq->ifr_cq_cidx = 0; 2461 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2462 bzero((void *)di->idi_vaddr, di->idi_size); 2463 /* also resets the free lists pidx/cidx */ 2464 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2465 iflib_fl_bufs_free(fl); 2466 } 2467 } 2468 2469 static inline caddr_t 2470 calc_next_rxd(iflib_fl_t fl, int cidx) 2471 { 2472 qidx_t size; 2473 int nrxd; 2474 caddr_t start, end, cur, next; 2475 2476 nrxd = fl->ifl_size; 2477 size = fl->ifl_rxd_size; 2478 start = fl->ifl_ifdi->idi_vaddr; 2479 2480 if (__predict_false(size == 0)) 2481 return (start); 2482 cur = start + size*cidx; 2483 end = start + size*nrxd; 2484 next = CACHE_PTR_NEXT(cur); 2485 return (next < end ? next : start); 2486 } 2487 2488 static inline void 2489 prefetch_pkts(iflib_fl_t fl, int cidx) 2490 { 2491 int nextptr; 2492 int nrxd = fl->ifl_size; 2493 caddr_t next_rxd; 2494 2495 2496 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2497 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2498 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2499 next_rxd = calc_next_rxd(fl, cidx); 2500 prefetch(next_rxd); 2501 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2502 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2503 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2504 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2505 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2506 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2507 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2508 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2509 } 2510 2511 static struct mbuf * 2512 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2513 int *pf_rv, if_rxd_info_t ri) 2514 { 2515 bus_dmamap_t map; 2516 iflib_fl_t fl; 2517 caddr_t payload; 2518 struct mbuf *m; 2519 int flid, cidx, len, next; 2520 2521 map = NULL; 2522 flid = irf->irf_flid; 2523 cidx = irf->irf_idx; 2524 fl = &rxq->ifr_fl[flid]; 2525 sd->ifsd_fl = fl; 2526 sd->ifsd_cidx = cidx; 2527 m = fl->ifl_sds.ifsd_m[cidx]; 2528 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2529 fl->ifl_credits--; 2530 #if MEMORY_LOGGING 2531 fl->ifl_m_dequeued++; 2532 #endif 2533 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2534 prefetch_pkts(fl, cidx); 2535 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2536 prefetch(&fl->ifl_sds.ifsd_map[next]); 2537 map = fl->ifl_sds.ifsd_map[cidx]; 2538 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2539 2540 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2541 MPASS(fl->ifl_cidx == cidx); 2542 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2543 2544 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL) { 2545 payload = *sd->ifsd_cl; 2546 payload += ri->iri_pad; 2547 len = ri->iri_len - ri->iri_pad; 2548 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2549 len | PFIL_MEMPTR | PFIL_IN, NULL); 2550 switch (*pf_rv) { 2551 case PFIL_DROPPED: 2552 case PFIL_CONSUMED: 2553 /* 2554 * The filter ate it. Everything is recycled. 2555 */ 2556 m = NULL; 2557 unload = 0; 2558 break; 2559 case PFIL_REALLOCED: 2560 /* 2561 * The filter copied it. Everything is recycled. 2562 */ 2563 m = pfil_mem2mbuf(payload); 2564 unload = 0; 2565 break; 2566 case PFIL_PASS: 2567 /* 2568 * Filter said it was OK, so receive like 2569 * normal 2570 */ 2571 fl->ifl_sds.ifsd_m[cidx] = NULL; 2572 break; 2573 default: 2574 MPASS(0); 2575 } 2576 } else { 2577 fl->ifl_sds.ifsd_m[cidx] = NULL; 2578 *pf_rv = PFIL_PASS; 2579 } 2580 2581 if (unload) 2582 bus_dmamap_unload(fl->ifl_buf_tag, map); 2583 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2584 if (__predict_false(fl->ifl_cidx == 0)) 2585 fl->ifl_gen = 0; 2586 bit_clear(fl->ifl_rx_bitmap, cidx); 2587 return (m); 2588 } 2589 2590 static struct mbuf * 2591 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2592 { 2593 struct mbuf *m, *mh, *mt; 2594 caddr_t cl; 2595 int *pf_rv_ptr, flags, i, padlen; 2596 bool consumed; 2597 2598 i = 0; 2599 mh = NULL; 2600 consumed = false; 2601 *pf_rv = PFIL_PASS; 2602 pf_rv_ptr = pf_rv; 2603 do { 2604 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2605 pf_rv_ptr, ri); 2606 2607 MPASS(*sd->ifsd_cl != NULL); 2608 2609 /* 2610 * Exclude zero-length frags & frags from 2611 * packets the filter has consumed or dropped 2612 */ 2613 if (ri->iri_frags[i].irf_len == 0 || consumed || 2614 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2615 if (mh == NULL) { 2616 /* everything saved here */ 2617 consumed = true; 2618 pf_rv_ptr = NULL; 2619 continue; 2620 } 2621 /* XXX we can save the cluster here, but not the mbuf */ 2622 m_init(m, M_NOWAIT, MT_DATA, 0); 2623 m_free(m); 2624 continue; 2625 } 2626 if (mh == NULL) { 2627 flags = M_PKTHDR|M_EXT; 2628 mh = mt = m; 2629 padlen = ri->iri_pad; 2630 } else { 2631 flags = M_EXT; 2632 mt->m_next = m; 2633 mt = m; 2634 /* assuming padding is only on the first fragment */ 2635 padlen = 0; 2636 } 2637 cl = *sd->ifsd_cl; 2638 *sd->ifsd_cl = NULL; 2639 2640 /* Can these two be made one ? */ 2641 m_init(m, M_NOWAIT, MT_DATA, flags); 2642 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2643 /* 2644 * These must follow m_init and m_cljset 2645 */ 2646 m->m_data += padlen; 2647 ri->iri_len -= padlen; 2648 m->m_len = ri->iri_frags[i].irf_len; 2649 } while (++i < ri->iri_nfrags); 2650 2651 return (mh); 2652 } 2653 2654 /* 2655 * Process one software descriptor 2656 */ 2657 static struct mbuf * 2658 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2659 { 2660 struct if_rxsd sd; 2661 struct mbuf *m; 2662 int pf_rv; 2663 2664 /* should I merge this back in now that the two paths are basically duplicated? */ 2665 if (ri->iri_nfrags == 1 && 2666 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2667 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2668 &pf_rv, ri); 2669 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2670 return (m); 2671 if (pf_rv == PFIL_PASS) { 2672 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2673 #ifndef __NO_STRICT_ALIGNMENT 2674 if (!IP_ALIGNED(m)) 2675 m->m_data += 2; 2676 #endif 2677 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2678 m->m_len = ri->iri_frags[0].irf_len; 2679 } 2680 } else { 2681 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2682 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2683 return (m); 2684 } 2685 m->m_pkthdr.len = ri->iri_len; 2686 m->m_pkthdr.rcvif = ri->iri_ifp; 2687 m->m_flags |= ri->iri_flags; 2688 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2689 m->m_pkthdr.flowid = ri->iri_flowid; 2690 M_HASHTYPE_SET(m, ri->iri_rsstype); 2691 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2692 m->m_pkthdr.csum_data = ri->iri_csum_data; 2693 return (m); 2694 } 2695 2696 #if defined(INET6) || defined(INET) 2697 static void 2698 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2699 { 2700 CURVNET_SET(lc->ifp->if_vnet); 2701 #if defined(INET6) 2702 *v6 = V_ip6_forwarding; 2703 #endif 2704 #if defined(INET) 2705 *v4 = V_ipforwarding; 2706 #endif 2707 CURVNET_RESTORE(); 2708 } 2709 2710 /* 2711 * Returns true if it's possible this packet could be LROed. 2712 * if it returns false, it is guaranteed that tcp_lro_rx() 2713 * would not return zero. 2714 */ 2715 static bool 2716 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2717 { 2718 struct ether_header *eh; 2719 2720 eh = mtod(m, struct ether_header *); 2721 switch (eh->ether_type) { 2722 #if defined(INET6) 2723 case htons(ETHERTYPE_IPV6): 2724 return (!v6_forwarding); 2725 #endif 2726 #if defined (INET) 2727 case htons(ETHERTYPE_IP): 2728 return (!v4_forwarding); 2729 #endif 2730 } 2731 2732 return false; 2733 } 2734 #else 2735 static void 2736 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2737 { 2738 } 2739 #endif 2740 2741 static bool 2742 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2743 { 2744 if_t ifp; 2745 if_ctx_t ctx = rxq->ifr_ctx; 2746 if_shared_ctx_t sctx = ctx->ifc_sctx; 2747 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2748 int avail, i; 2749 qidx_t *cidxp; 2750 struct if_rxd_info ri; 2751 int err, budget_left, rx_bytes, rx_pkts; 2752 iflib_fl_t fl; 2753 int lro_enabled; 2754 bool v4_forwarding, v6_forwarding, lro_possible; 2755 2756 /* 2757 * XXX early demux data packets so that if_input processing only handles 2758 * acks in interrupt context 2759 */ 2760 struct mbuf *m, *mh, *mt, *mf; 2761 2762 NET_EPOCH_ASSERT(); 2763 2764 lro_possible = v4_forwarding = v6_forwarding = false; 2765 ifp = ctx->ifc_ifp; 2766 mh = mt = NULL; 2767 MPASS(budget > 0); 2768 rx_pkts = rx_bytes = 0; 2769 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2770 cidxp = &rxq->ifr_cq_cidx; 2771 else 2772 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2773 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2774 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2775 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2776 DBG_COUNTER_INC(rx_unavail); 2777 return (false); 2778 } 2779 2780 /* pfil needs the vnet to be set */ 2781 CURVNET_SET_QUIET(ifp->if_vnet); 2782 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2783 if (__predict_false(!CTX_ACTIVE(ctx))) { 2784 DBG_COUNTER_INC(rx_ctx_inactive); 2785 break; 2786 } 2787 /* 2788 * Reset client set fields to their default values 2789 */ 2790 rxd_info_zero(&ri); 2791 ri.iri_qsidx = rxq->ifr_id; 2792 ri.iri_cidx = *cidxp; 2793 ri.iri_ifp = ifp; 2794 ri.iri_frags = rxq->ifr_frags; 2795 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2796 2797 if (err) 2798 goto err; 2799 rx_pkts += 1; 2800 rx_bytes += ri.iri_len; 2801 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2802 *cidxp = ri.iri_cidx; 2803 /* Update our consumer index */ 2804 /* XXX NB: shurd - check if this is still safe */ 2805 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2806 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2807 /* was this only a completion queue message? */ 2808 if (__predict_false(ri.iri_nfrags == 0)) 2809 continue; 2810 } 2811 MPASS(ri.iri_nfrags != 0); 2812 MPASS(ri.iri_len != 0); 2813 2814 /* will advance the cidx on the corresponding free lists */ 2815 m = iflib_rxd_pkt_get(rxq, &ri); 2816 avail--; 2817 budget_left--; 2818 if (avail == 0 && budget_left) 2819 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2820 2821 if (__predict_false(m == NULL)) 2822 continue; 2823 2824 /* imm_pkt: -- cxgb */ 2825 if (mh == NULL) 2826 mh = mt = m; 2827 else { 2828 mt->m_nextpkt = m; 2829 mt = m; 2830 } 2831 } 2832 CURVNET_RESTORE(); 2833 /* make sure that we can refill faster than drain */ 2834 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2835 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2836 2837 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2838 if (lro_enabled) 2839 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2840 mt = mf = NULL; 2841 while (mh != NULL) { 2842 m = mh; 2843 mh = mh->m_nextpkt; 2844 m->m_nextpkt = NULL; 2845 #ifndef __NO_STRICT_ALIGNMENT 2846 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2847 continue; 2848 #endif 2849 rx_bytes += m->m_pkthdr.len; 2850 rx_pkts++; 2851 #if defined(INET6) || defined(INET) 2852 if (lro_enabled) { 2853 if (!lro_possible) { 2854 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2855 if (lro_possible && mf != NULL) { 2856 ifp->if_input(ifp, mf); 2857 DBG_COUNTER_INC(rx_if_input); 2858 mt = mf = NULL; 2859 } 2860 } 2861 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2862 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2863 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2864 continue; 2865 } 2866 } 2867 #endif 2868 if (lro_possible) { 2869 ifp->if_input(ifp, m); 2870 DBG_COUNTER_INC(rx_if_input); 2871 continue; 2872 } 2873 2874 if (mf == NULL) 2875 mf = m; 2876 if (mt != NULL) 2877 mt->m_nextpkt = m; 2878 mt = m; 2879 } 2880 if (mf != NULL) { 2881 ifp->if_input(ifp, mf); 2882 DBG_COUNTER_INC(rx_if_input); 2883 } 2884 2885 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2886 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2887 2888 /* 2889 * Flush any outstanding LRO work 2890 */ 2891 #if defined(INET6) || defined(INET) 2892 tcp_lro_flush_all(&rxq->ifr_lc); 2893 #endif 2894 if (avail) 2895 return true; 2896 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2897 err: 2898 STATE_LOCK(ctx); 2899 ctx->ifc_flags |= IFC_DO_RESET; 2900 iflib_admin_intr_deferred(ctx); 2901 STATE_UNLOCK(ctx); 2902 return (false); 2903 } 2904 2905 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2906 static inline qidx_t 2907 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2908 { 2909 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2910 qidx_t minthresh = txq->ift_size / 8; 2911 if (in_use > 4*minthresh) 2912 return (notify_count); 2913 if (in_use > 2*minthresh) 2914 return (notify_count >> 1); 2915 if (in_use > minthresh) 2916 return (notify_count >> 3); 2917 return (0); 2918 } 2919 2920 static inline qidx_t 2921 txq_max_rs_deferred(iflib_txq_t txq) 2922 { 2923 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2924 qidx_t minthresh = txq->ift_size / 8; 2925 if (txq->ift_in_use > 4*minthresh) 2926 return (notify_count); 2927 if (txq->ift_in_use > 2*minthresh) 2928 return (notify_count >> 1); 2929 if (txq->ift_in_use > minthresh) 2930 return (notify_count >> 2); 2931 return (2); 2932 } 2933 2934 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2935 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2936 2937 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2938 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2939 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2940 2941 /* forward compatibility for cxgb */ 2942 #define FIRST_QSET(ctx) 0 2943 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2944 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2945 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2946 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2947 2948 /* XXX we should be setting this to something other than zero */ 2949 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2950 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2951 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2952 2953 static inline bool 2954 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2955 { 2956 qidx_t dbval, max; 2957 bool rang; 2958 2959 rang = false; 2960 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2961 if (ring || txq->ift_db_pending >= max) { 2962 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2963 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 2964 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2965 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2966 txq->ift_db_pending = txq->ift_npending = 0; 2967 rang = true; 2968 } 2969 return (rang); 2970 } 2971 2972 #ifdef PKT_DEBUG 2973 static void 2974 print_pkt(if_pkt_info_t pi) 2975 { 2976 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2977 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2978 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2979 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2980 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2981 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2982 } 2983 #endif 2984 2985 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2986 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2987 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2988 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2989 2990 static int 2991 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2992 { 2993 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2994 struct ether_vlan_header *eh; 2995 struct mbuf *m; 2996 2997 m = *mp; 2998 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2999 M_WRITABLE(m) == 0) { 3000 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3001 return (ENOMEM); 3002 } else { 3003 m_freem(*mp); 3004 DBG_COUNTER_INC(tx_frees); 3005 *mp = m; 3006 } 3007 } 3008 3009 /* 3010 * Determine where frame payload starts. 3011 * Jump over vlan headers if already present, 3012 * helpful for QinQ too. 3013 */ 3014 if (__predict_false(m->m_len < sizeof(*eh))) { 3015 txq->ift_pullups++; 3016 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3017 return (ENOMEM); 3018 } 3019 eh = mtod(m, struct ether_vlan_header *); 3020 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3021 pi->ipi_etype = ntohs(eh->evl_proto); 3022 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3023 } else { 3024 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3025 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3026 } 3027 3028 switch (pi->ipi_etype) { 3029 #ifdef INET 3030 case ETHERTYPE_IP: 3031 { 3032 struct mbuf *n; 3033 struct ip *ip = NULL; 3034 struct tcphdr *th = NULL; 3035 int minthlen; 3036 3037 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3038 if (__predict_false(m->m_len < minthlen)) { 3039 /* 3040 * if this code bloat is causing too much of a hit 3041 * move it to a separate function and mark it noinline 3042 */ 3043 if (m->m_len == pi->ipi_ehdrlen) { 3044 n = m->m_next; 3045 MPASS(n); 3046 if (n->m_len >= sizeof(*ip)) { 3047 ip = (struct ip *)n->m_data; 3048 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3049 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3050 } else { 3051 txq->ift_pullups++; 3052 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3053 return (ENOMEM); 3054 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3055 } 3056 } else { 3057 txq->ift_pullups++; 3058 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3059 return (ENOMEM); 3060 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3061 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3062 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3063 } 3064 } else { 3065 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3066 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3067 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3068 } 3069 pi->ipi_ip_hlen = ip->ip_hl << 2; 3070 pi->ipi_ipproto = ip->ip_p; 3071 pi->ipi_flags |= IPI_TX_IPV4; 3072 3073 /* TCP checksum offload may require TCP header length */ 3074 if (IS_TX_OFFLOAD4(pi)) { 3075 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3076 if (__predict_false(th == NULL)) { 3077 txq->ift_pullups++; 3078 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3079 return (ENOMEM); 3080 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3081 } 3082 pi->ipi_tcp_hflags = th->th_flags; 3083 pi->ipi_tcp_hlen = th->th_off << 2; 3084 pi->ipi_tcp_seq = th->th_seq; 3085 } 3086 if (IS_TSO4(pi)) { 3087 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3088 return (ENXIO); 3089 /* 3090 * TSO always requires hardware checksum offload. 3091 */ 3092 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3093 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3094 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3095 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3096 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3097 ip->ip_sum = 0; 3098 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3099 } 3100 } 3101 } 3102 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3103 ip->ip_sum = 0; 3104 3105 break; 3106 } 3107 #endif 3108 #ifdef INET6 3109 case ETHERTYPE_IPV6: 3110 { 3111 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3112 struct tcphdr *th; 3113 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3114 3115 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3116 txq->ift_pullups++; 3117 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3118 return (ENOMEM); 3119 } 3120 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3121 3122 /* XXX-BZ this will go badly in case of ext hdrs. */ 3123 pi->ipi_ipproto = ip6->ip6_nxt; 3124 pi->ipi_flags |= IPI_TX_IPV6; 3125 3126 /* TCP checksum offload may require TCP header length */ 3127 if (IS_TX_OFFLOAD6(pi)) { 3128 if (pi->ipi_ipproto == IPPROTO_TCP) { 3129 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3130 txq->ift_pullups++; 3131 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3132 return (ENOMEM); 3133 } 3134 pi->ipi_tcp_hflags = th->th_flags; 3135 pi->ipi_tcp_hlen = th->th_off << 2; 3136 pi->ipi_tcp_seq = th->th_seq; 3137 } 3138 if (IS_TSO6(pi)) { 3139 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3140 return (ENXIO); 3141 /* 3142 * TSO always requires hardware checksum offload. 3143 */ 3144 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3145 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3146 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3147 } 3148 } 3149 break; 3150 } 3151 #endif 3152 default: 3153 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3154 pi->ipi_ip_hlen = 0; 3155 break; 3156 } 3157 *mp = m; 3158 3159 return (0); 3160 } 3161 3162 /* 3163 * If dodgy hardware rejects the scatter gather chain we've handed it 3164 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3165 * m_defrag'd mbufs 3166 */ 3167 static __noinline struct mbuf * 3168 iflib_remove_mbuf(iflib_txq_t txq) 3169 { 3170 int ntxd, pidx; 3171 struct mbuf *m, **ifsd_m; 3172 3173 ifsd_m = txq->ift_sds.ifsd_m; 3174 ntxd = txq->ift_size; 3175 pidx = txq->ift_pidx & (ntxd - 1); 3176 ifsd_m = txq->ift_sds.ifsd_m; 3177 m = ifsd_m[pidx]; 3178 ifsd_m[pidx] = NULL; 3179 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3180 if (txq->ift_sds.ifsd_tso_map != NULL) 3181 bus_dmamap_unload(txq->ift_tso_buf_tag, 3182 txq->ift_sds.ifsd_tso_map[pidx]); 3183 #if MEMORY_LOGGING 3184 txq->ift_dequeued++; 3185 #endif 3186 return (m); 3187 } 3188 3189 static inline caddr_t 3190 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3191 { 3192 qidx_t size; 3193 int ntxd; 3194 caddr_t start, end, cur, next; 3195 3196 ntxd = txq->ift_size; 3197 size = txq->ift_txd_size[qid]; 3198 start = txq->ift_ifdi[qid].idi_vaddr; 3199 3200 if (__predict_false(size == 0)) 3201 return (start); 3202 cur = start + size*cidx; 3203 end = start + size*ntxd; 3204 next = CACHE_PTR_NEXT(cur); 3205 return (next < end ? next : start); 3206 } 3207 3208 /* 3209 * Pad an mbuf to ensure a minimum ethernet frame size. 3210 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3211 */ 3212 static __noinline int 3213 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3214 { 3215 /* 3216 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3217 * and ARP message is the smallest common payload I can think of 3218 */ 3219 static char pad[18]; /* just zeros */ 3220 int n; 3221 struct mbuf *new_head; 3222 3223 if (!M_WRITABLE(*m_head)) { 3224 new_head = m_dup(*m_head, M_NOWAIT); 3225 if (new_head == NULL) { 3226 m_freem(*m_head); 3227 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3228 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3229 DBG_COUNTER_INC(tx_frees); 3230 return ENOMEM; 3231 } 3232 m_freem(*m_head); 3233 *m_head = new_head; 3234 } 3235 3236 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3237 n > 0; n -= sizeof(pad)) 3238 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3239 break; 3240 3241 if (n > 0) { 3242 m_freem(*m_head); 3243 device_printf(dev, "cannot pad short frame\n"); 3244 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3245 DBG_COUNTER_INC(tx_frees); 3246 return (ENOBUFS); 3247 } 3248 3249 return 0; 3250 } 3251 3252 static int 3253 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3254 { 3255 if_ctx_t ctx; 3256 if_shared_ctx_t sctx; 3257 if_softc_ctx_t scctx; 3258 bus_dma_tag_t buf_tag; 3259 bus_dma_segment_t *segs; 3260 struct mbuf *m_head, **ifsd_m; 3261 void *next_txd; 3262 bus_dmamap_t map; 3263 struct if_pkt_info pi; 3264 int remap = 0; 3265 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3266 3267 ctx = txq->ift_ctx; 3268 sctx = ctx->ifc_sctx; 3269 scctx = &ctx->ifc_softc_ctx; 3270 segs = txq->ift_segs; 3271 ntxd = txq->ift_size; 3272 m_head = *m_headp; 3273 map = NULL; 3274 3275 /* 3276 * If we're doing TSO the next descriptor to clean may be quite far ahead 3277 */ 3278 cidx = txq->ift_cidx; 3279 pidx = txq->ift_pidx; 3280 if (ctx->ifc_flags & IFC_PREFETCH) { 3281 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3282 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3283 next_txd = calc_next_txd(txq, cidx, 0); 3284 prefetch(next_txd); 3285 } 3286 3287 /* prefetch the next cache line of mbuf pointers and flags */ 3288 prefetch(&txq->ift_sds.ifsd_m[next]); 3289 prefetch(&txq->ift_sds.ifsd_map[next]); 3290 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3291 } 3292 map = txq->ift_sds.ifsd_map[pidx]; 3293 ifsd_m = txq->ift_sds.ifsd_m; 3294 3295 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3296 buf_tag = txq->ift_tso_buf_tag; 3297 max_segs = scctx->isc_tx_tso_segments_max; 3298 map = txq->ift_sds.ifsd_tso_map[pidx]; 3299 MPASS(buf_tag != NULL); 3300 MPASS(max_segs > 0); 3301 } else { 3302 buf_tag = txq->ift_buf_tag; 3303 max_segs = scctx->isc_tx_nsegments; 3304 map = txq->ift_sds.ifsd_map[pidx]; 3305 } 3306 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3307 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3308 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3309 if (err) { 3310 DBG_COUNTER_INC(encap_txd_encap_fail); 3311 return err; 3312 } 3313 } 3314 m_head = *m_headp; 3315 3316 pkt_info_zero(&pi); 3317 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3318 pi.ipi_pidx = pidx; 3319 pi.ipi_qsidx = txq->ift_id; 3320 pi.ipi_len = m_head->m_pkthdr.len; 3321 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3322 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3323 3324 /* deliberate bitwise OR to make one condition */ 3325 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3326 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3327 DBG_COUNTER_INC(encap_txd_encap_fail); 3328 return (err); 3329 } 3330 m_head = *m_headp; 3331 } 3332 3333 retry: 3334 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3335 BUS_DMA_NOWAIT); 3336 defrag: 3337 if (__predict_false(err)) { 3338 switch (err) { 3339 case EFBIG: 3340 /* try collapse once and defrag once */ 3341 if (remap == 0) { 3342 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3343 /* try defrag if collapsing fails */ 3344 if (m_head == NULL) 3345 remap++; 3346 } 3347 if (remap == 1) { 3348 txq->ift_mbuf_defrag++; 3349 m_head = m_defrag(*m_headp, M_NOWAIT); 3350 } 3351 /* 3352 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3353 * failed to map an mbuf that was run through m_defrag 3354 */ 3355 MPASS(remap <= 1); 3356 if (__predict_false(m_head == NULL || remap > 1)) 3357 goto defrag_failed; 3358 remap++; 3359 *m_headp = m_head; 3360 goto retry; 3361 break; 3362 case ENOMEM: 3363 txq->ift_no_tx_dma_setup++; 3364 break; 3365 default: 3366 txq->ift_no_tx_dma_setup++; 3367 m_freem(*m_headp); 3368 DBG_COUNTER_INC(tx_frees); 3369 *m_headp = NULL; 3370 break; 3371 } 3372 txq->ift_map_failed++; 3373 DBG_COUNTER_INC(encap_load_mbuf_fail); 3374 DBG_COUNTER_INC(encap_txd_encap_fail); 3375 return (err); 3376 } 3377 ifsd_m[pidx] = m_head; 3378 /* 3379 * XXX assumes a 1 to 1 relationship between segments and 3380 * descriptors - this does not hold true on all drivers, e.g. 3381 * cxgb 3382 */ 3383 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3384 txq->ift_no_desc_avail++; 3385 bus_dmamap_unload(buf_tag, map); 3386 DBG_COUNTER_INC(encap_txq_avail_fail); 3387 DBG_COUNTER_INC(encap_txd_encap_fail); 3388 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3389 GROUPTASK_ENQUEUE(&txq->ift_task); 3390 return (ENOBUFS); 3391 } 3392 /* 3393 * On Intel cards we can greatly reduce the number of TX interrupts 3394 * we see by only setting report status on every Nth descriptor. 3395 * However, this also means that the driver will need to keep track 3396 * of the descriptors that RS was set on to check them for the DD bit. 3397 */ 3398 txq->ift_rs_pending += nsegs + 1; 3399 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3400 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3401 pi.ipi_flags |= IPI_TX_INTR; 3402 txq->ift_rs_pending = 0; 3403 } 3404 3405 pi.ipi_segs = segs; 3406 pi.ipi_nsegs = nsegs; 3407 3408 MPASS(pidx >= 0 && pidx < txq->ift_size); 3409 #ifdef PKT_DEBUG 3410 print_pkt(&pi); 3411 #endif 3412 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3413 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3414 DBG_COUNTER_INC(tx_encap); 3415 MPASS(pi.ipi_new_pidx < txq->ift_size); 3416 3417 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3418 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3419 ndesc += txq->ift_size; 3420 txq->ift_gen = 1; 3421 } 3422 /* 3423 * drivers can need as many as 3424 * two sentinels 3425 */ 3426 MPASS(ndesc <= pi.ipi_nsegs + 2); 3427 MPASS(pi.ipi_new_pidx != pidx); 3428 MPASS(ndesc > 0); 3429 txq->ift_in_use += ndesc; 3430 3431 /* 3432 * We update the last software descriptor again here because there may 3433 * be a sentinel and/or there may be more mbufs than segments 3434 */ 3435 txq->ift_pidx = pi.ipi_new_pidx; 3436 txq->ift_npending += pi.ipi_ndescs; 3437 } else { 3438 *m_headp = m_head = iflib_remove_mbuf(txq); 3439 if (err == EFBIG) { 3440 txq->ift_txd_encap_efbig++; 3441 if (remap < 2) { 3442 remap = 1; 3443 goto defrag; 3444 } 3445 } 3446 goto defrag_failed; 3447 } 3448 /* 3449 * err can't possibly be non-zero here, so we don't neet to test it 3450 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3451 */ 3452 return (err); 3453 3454 defrag_failed: 3455 txq->ift_mbuf_defrag_failed++; 3456 txq->ift_map_failed++; 3457 m_freem(*m_headp); 3458 DBG_COUNTER_INC(tx_frees); 3459 *m_headp = NULL; 3460 DBG_COUNTER_INC(encap_txd_encap_fail); 3461 return (ENOMEM); 3462 } 3463 3464 static void 3465 iflib_tx_desc_free(iflib_txq_t txq, int n) 3466 { 3467 uint32_t qsize, cidx, mask, gen; 3468 struct mbuf *m, **ifsd_m; 3469 bool do_prefetch; 3470 3471 cidx = txq->ift_cidx; 3472 gen = txq->ift_gen; 3473 qsize = txq->ift_size; 3474 mask = qsize-1; 3475 ifsd_m = txq->ift_sds.ifsd_m; 3476 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3477 3478 while (n-- > 0) { 3479 if (do_prefetch) { 3480 prefetch(ifsd_m[(cidx + 3) & mask]); 3481 prefetch(ifsd_m[(cidx + 4) & mask]); 3482 } 3483 if ((m = ifsd_m[cidx]) != NULL) { 3484 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3485 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3486 bus_dmamap_sync(txq->ift_tso_buf_tag, 3487 txq->ift_sds.ifsd_tso_map[cidx], 3488 BUS_DMASYNC_POSTWRITE); 3489 bus_dmamap_unload(txq->ift_tso_buf_tag, 3490 txq->ift_sds.ifsd_tso_map[cidx]); 3491 } else { 3492 bus_dmamap_sync(txq->ift_buf_tag, 3493 txq->ift_sds.ifsd_map[cidx], 3494 BUS_DMASYNC_POSTWRITE); 3495 bus_dmamap_unload(txq->ift_buf_tag, 3496 txq->ift_sds.ifsd_map[cidx]); 3497 } 3498 /* XXX we don't support any drivers that batch packets yet */ 3499 MPASS(m->m_nextpkt == NULL); 3500 m_freem(m); 3501 ifsd_m[cidx] = NULL; 3502 #if MEMORY_LOGGING 3503 txq->ift_dequeued++; 3504 #endif 3505 DBG_COUNTER_INC(tx_frees); 3506 } 3507 if (__predict_false(++cidx == qsize)) { 3508 cidx = 0; 3509 gen = 0; 3510 } 3511 } 3512 txq->ift_cidx = cidx; 3513 txq->ift_gen = gen; 3514 } 3515 3516 static __inline int 3517 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3518 { 3519 int reclaim; 3520 if_ctx_t ctx = txq->ift_ctx; 3521 3522 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3523 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3524 3525 /* 3526 * Need a rate-limiting check so that this isn't called every time 3527 */ 3528 iflib_tx_credits_update(ctx, txq); 3529 reclaim = DESC_RECLAIMABLE(txq); 3530 3531 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3532 #ifdef INVARIANTS 3533 if (iflib_verbose_debug) { 3534 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3535 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3536 reclaim, thresh); 3537 3538 } 3539 #endif 3540 return (0); 3541 } 3542 iflib_tx_desc_free(txq, reclaim); 3543 txq->ift_cleaned += reclaim; 3544 txq->ift_in_use -= reclaim; 3545 3546 return (reclaim); 3547 } 3548 3549 static struct mbuf ** 3550 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3551 { 3552 int next, size; 3553 struct mbuf **items; 3554 3555 size = r->size; 3556 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3557 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3558 3559 prefetch(items[(cidx + offset) & (size-1)]); 3560 if (remaining > 1) { 3561 prefetch2cachelines(&items[next]); 3562 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3563 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3564 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3565 } 3566 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3567 } 3568 3569 static void 3570 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3571 { 3572 3573 ifmp_ring_check_drainage(txq->ift_br, budget); 3574 } 3575 3576 static uint32_t 3577 iflib_txq_can_drain(struct ifmp_ring *r) 3578 { 3579 iflib_txq_t txq = r->cookie; 3580 if_ctx_t ctx = txq->ift_ctx; 3581 3582 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3583 return (1); 3584 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3585 BUS_DMASYNC_POSTREAD); 3586 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3587 false)); 3588 } 3589 3590 static uint32_t 3591 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3592 { 3593 iflib_txq_t txq = r->cookie; 3594 if_ctx_t ctx = txq->ift_ctx; 3595 if_t ifp = ctx->ifc_ifp; 3596 struct mbuf *m, **mp; 3597 int avail, bytes_sent, consumed, count, err, i, in_use_prev; 3598 int mcast_sent, pkt_sent, reclaimed, txq_avail; 3599 bool do_prefetch, rang, ring; 3600 3601 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3602 !LINK_ACTIVE(ctx))) { 3603 DBG_COUNTER_INC(txq_drain_notready); 3604 return (0); 3605 } 3606 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3607 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3608 avail = IDXDIFF(pidx, cidx, r->size); 3609 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3610 DBG_COUNTER_INC(txq_drain_flushing); 3611 for (i = 0; i < avail; i++) { 3612 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3613 m_free(r->items[(cidx + i) & (r->size-1)]); 3614 r->items[(cidx + i) & (r->size-1)] = NULL; 3615 } 3616 return (avail); 3617 } 3618 3619 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3620 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3621 CALLOUT_LOCK(txq); 3622 callout_stop(&txq->ift_timer); 3623 CALLOUT_UNLOCK(txq); 3624 DBG_COUNTER_INC(txq_drain_oactive); 3625 return (0); 3626 } 3627 if (reclaimed) 3628 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3629 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3630 count = MIN(avail, TX_BATCH_SIZE); 3631 #ifdef INVARIANTS 3632 if (iflib_verbose_debug) 3633 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3634 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3635 #endif 3636 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3637 txq_avail = TXQ_AVAIL(txq); 3638 err = 0; 3639 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) { 3640 int rem = do_prefetch ? count - i : 0; 3641 3642 mp = _ring_peek_one(r, cidx, i, rem); 3643 MPASS(mp != NULL && *mp != NULL); 3644 if (__predict_false(*mp == (struct mbuf *)txq)) { 3645 consumed++; 3646 continue; 3647 } 3648 in_use_prev = txq->ift_in_use; 3649 err = iflib_encap(txq, mp); 3650 if (__predict_false(err)) { 3651 /* no room - bail out */ 3652 if (err == ENOBUFS) 3653 break; 3654 consumed++; 3655 /* we can't send this packet - skip it */ 3656 continue; 3657 } 3658 consumed++; 3659 pkt_sent++; 3660 m = *mp; 3661 DBG_COUNTER_INC(tx_sent); 3662 bytes_sent += m->m_pkthdr.len; 3663 mcast_sent += !!(m->m_flags & M_MCAST); 3664 txq_avail = TXQ_AVAIL(txq); 3665 3666 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3667 ETHER_BPF_MTAP(ifp, m); 3668 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3669 break; 3670 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3671 } 3672 3673 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3674 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3675 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3676 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3677 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3678 if (mcast_sent) 3679 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3680 #ifdef INVARIANTS 3681 if (iflib_verbose_debug) 3682 printf("consumed=%d\n", consumed); 3683 #endif 3684 return (consumed); 3685 } 3686 3687 static uint32_t 3688 iflib_txq_drain_always(struct ifmp_ring *r) 3689 { 3690 return (1); 3691 } 3692 3693 static uint32_t 3694 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3695 { 3696 int i, avail; 3697 struct mbuf **mp; 3698 iflib_txq_t txq; 3699 3700 txq = r->cookie; 3701 3702 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3703 CALLOUT_LOCK(txq); 3704 callout_stop(&txq->ift_timer); 3705 CALLOUT_UNLOCK(txq); 3706 3707 avail = IDXDIFF(pidx, cidx, r->size); 3708 for (i = 0; i < avail; i++) { 3709 mp = _ring_peek_one(r, cidx, i, avail - i); 3710 if (__predict_false(*mp == (struct mbuf *)txq)) 3711 continue; 3712 m_freem(*mp); 3713 DBG_COUNTER_INC(tx_frees); 3714 } 3715 MPASS(ifmp_ring_is_stalled(r) == 0); 3716 return (avail); 3717 } 3718 3719 static void 3720 iflib_ifmp_purge(iflib_txq_t txq) 3721 { 3722 struct ifmp_ring *r; 3723 3724 r = txq->ift_br; 3725 r->drain = iflib_txq_drain_free; 3726 r->can_drain = iflib_txq_drain_always; 3727 3728 ifmp_ring_check_drainage(r, r->size); 3729 3730 r->drain = iflib_txq_drain; 3731 r->can_drain = iflib_txq_can_drain; 3732 } 3733 3734 static void 3735 _task_fn_tx(void *context) 3736 { 3737 iflib_txq_t txq = context; 3738 if_ctx_t ctx = txq->ift_ctx; 3739 #if defined(ALTQ) || defined(DEV_NETMAP) 3740 if_t ifp = ctx->ifc_ifp; 3741 #endif 3742 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3743 3744 #ifdef IFLIB_DIAGNOSTICS 3745 txq->ift_cpu_exec_count[curcpu]++; 3746 #endif 3747 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3748 return; 3749 #ifdef DEV_NETMAP 3750 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3751 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3752 BUS_DMASYNC_POSTREAD); 3753 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3754 netmap_tx_irq(ifp, txq->ift_id); 3755 if (ctx->ifc_flags & IFC_LEGACY) 3756 IFDI_INTR_ENABLE(ctx); 3757 else 3758 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3759 return; 3760 } 3761 #endif 3762 #ifdef ALTQ 3763 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3764 iflib_altq_if_start(ifp); 3765 #endif 3766 if (txq->ift_db_pending) 3767 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3768 else if (!abdicate) 3769 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3770 /* 3771 * When abdicating, we always need to check drainage, not just when we don't enqueue 3772 */ 3773 if (abdicate) 3774 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3775 if (ctx->ifc_flags & IFC_LEGACY) 3776 IFDI_INTR_ENABLE(ctx); 3777 else 3778 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3779 } 3780 3781 static void 3782 _task_fn_rx(void *context) 3783 { 3784 struct epoch_tracker et; 3785 iflib_rxq_t rxq = context; 3786 if_ctx_t ctx = rxq->ifr_ctx; 3787 bool more; 3788 uint16_t budget; 3789 3790 #ifdef IFLIB_DIAGNOSTICS 3791 rxq->ifr_cpu_exec_count[curcpu]++; 3792 #endif 3793 DBG_COUNTER_INC(task_fn_rxs); 3794 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3795 return; 3796 more = true; 3797 #ifdef DEV_NETMAP 3798 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3799 u_int work = 0; 3800 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3801 more = false; 3802 } 3803 } 3804 #endif 3805 budget = ctx->ifc_sysctl_rx_budget; 3806 if (budget == 0) 3807 budget = 16; /* XXX */ 3808 NET_EPOCH_ENTER(et); 3809 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3810 if (ctx->ifc_flags & IFC_LEGACY) 3811 IFDI_INTR_ENABLE(ctx); 3812 else 3813 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3814 DBG_COUNTER_INC(rx_intr_enables); 3815 } 3816 NET_EPOCH_EXIT(et); 3817 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3818 return; 3819 if (more) 3820 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3821 } 3822 3823 static void 3824 _task_fn_admin(void *context) 3825 { 3826 if_ctx_t ctx = context; 3827 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3828 iflib_txq_t txq; 3829 int i; 3830 bool oactive, running, do_reset, do_watchdog, in_detach; 3831 uint32_t reset_on = hz / 2; 3832 3833 STATE_LOCK(ctx); 3834 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3835 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3836 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3837 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3838 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3839 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3840 STATE_UNLOCK(ctx); 3841 3842 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3843 return; 3844 if (in_detach) 3845 return; 3846 3847 CTX_LOCK(ctx); 3848 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3849 CALLOUT_LOCK(txq); 3850 callout_stop(&txq->ift_timer); 3851 CALLOUT_UNLOCK(txq); 3852 } 3853 if (do_watchdog) { 3854 ctx->ifc_watchdog_events++; 3855 IFDI_WATCHDOG_RESET(ctx); 3856 } 3857 IFDI_UPDATE_ADMIN_STATUS(ctx); 3858 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3859 #ifdef DEV_NETMAP 3860 reset_on = hz / 2; 3861 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3862 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 3863 #endif 3864 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3865 } 3866 IFDI_LINK_INTR_ENABLE(ctx); 3867 if (do_reset) 3868 iflib_if_init_locked(ctx); 3869 CTX_UNLOCK(ctx); 3870 3871 if (LINK_ACTIVE(ctx) == 0) 3872 return; 3873 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3874 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3875 } 3876 3877 3878 static void 3879 _task_fn_iov(void *context) 3880 { 3881 if_ctx_t ctx = context; 3882 3883 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3884 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3885 return; 3886 3887 CTX_LOCK(ctx); 3888 IFDI_VFLR_HANDLE(ctx); 3889 CTX_UNLOCK(ctx); 3890 } 3891 3892 static int 3893 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3894 { 3895 int err; 3896 if_int_delay_info_t info; 3897 if_ctx_t ctx; 3898 3899 info = (if_int_delay_info_t)arg1; 3900 ctx = info->iidi_ctx; 3901 info->iidi_req = req; 3902 info->iidi_oidp = oidp; 3903 CTX_LOCK(ctx); 3904 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3905 CTX_UNLOCK(ctx); 3906 return (err); 3907 } 3908 3909 /********************************************************************* 3910 * 3911 * IFNET FUNCTIONS 3912 * 3913 **********************************************************************/ 3914 3915 static void 3916 iflib_if_init_locked(if_ctx_t ctx) 3917 { 3918 iflib_stop(ctx); 3919 iflib_init_locked(ctx); 3920 } 3921 3922 3923 static void 3924 iflib_if_init(void *arg) 3925 { 3926 if_ctx_t ctx = arg; 3927 3928 CTX_LOCK(ctx); 3929 iflib_if_init_locked(ctx); 3930 CTX_UNLOCK(ctx); 3931 } 3932 3933 static int 3934 iflib_if_transmit(if_t ifp, struct mbuf *m) 3935 { 3936 if_ctx_t ctx = if_getsoftc(ifp); 3937 3938 iflib_txq_t txq; 3939 int err, qidx; 3940 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3941 3942 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3943 DBG_COUNTER_INC(tx_frees); 3944 m_freem(m); 3945 return (ENETDOWN); 3946 } 3947 3948 MPASS(m->m_nextpkt == NULL); 3949 /* ALTQ-enabled interfaces always use queue 0. */ 3950 qidx = 0; 3951 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3952 qidx = QIDX(ctx, m); 3953 /* 3954 * XXX calculate buf_ring based on flowid (divvy up bits?) 3955 */ 3956 txq = &ctx->ifc_txqs[qidx]; 3957 3958 #ifdef DRIVER_BACKPRESSURE 3959 if (txq->ift_closed) { 3960 while (m != NULL) { 3961 next = m->m_nextpkt; 3962 m->m_nextpkt = NULL; 3963 m_freem(m); 3964 DBG_COUNTER_INC(tx_frees); 3965 m = next; 3966 } 3967 return (ENOBUFS); 3968 } 3969 #endif 3970 #ifdef notyet 3971 qidx = count = 0; 3972 mp = marr; 3973 next = m; 3974 do { 3975 count++; 3976 next = next->m_nextpkt; 3977 } while (next != NULL); 3978 3979 if (count > nitems(marr)) 3980 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3981 /* XXX check nextpkt */ 3982 m_freem(m); 3983 /* XXX simplify for now */ 3984 DBG_COUNTER_INC(tx_frees); 3985 return (ENOBUFS); 3986 } 3987 for (next = m, i = 0; next != NULL; i++) { 3988 mp[i] = next; 3989 next = next->m_nextpkt; 3990 mp[i]->m_nextpkt = NULL; 3991 } 3992 #endif 3993 DBG_COUNTER_INC(tx_seen); 3994 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 3995 3996 if (abdicate) 3997 GROUPTASK_ENQUEUE(&txq->ift_task); 3998 if (err) { 3999 if (!abdicate) 4000 GROUPTASK_ENQUEUE(&txq->ift_task); 4001 /* support forthcoming later */ 4002 #ifdef DRIVER_BACKPRESSURE 4003 txq->ift_closed = TRUE; 4004 #endif 4005 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4006 m_freem(m); 4007 DBG_COUNTER_INC(tx_frees); 4008 } 4009 4010 return (err); 4011 } 4012 4013 #ifdef ALTQ 4014 /* 4015 * The overall approach to integrating iflib with ALTQ is to continue to use 4016 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4017 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4018 * is redundant/unnecessary, but doing so minimizes the amount of 4019 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4020 * redundantly queueing to an intermediate mp_ring is swamped by the 4021 * performance limitations inherent in using ALTQ. 4022 * 4023 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4024 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4025 * given interface. If ALTQ is enabled for an interface, then all 4026 * transmitted packets for that interface will be submitted to the ALTQ 4027 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4028 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4029 * update stats that the iflib machinery handles, and which is sensitve to 4030 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4031 * will be installed as the start routine for use by ALTQ facilities that 4032 * need to trigger queue drains on a scheduled basis. 4033 * 4034 */ 4035 static void 4036 iflib_altq_if_start(if_t ifp) 4037 { 4038 struct ifaltq *ifq = &ifp->if_snd; 4039 struct mbuf *m; 4040 4041 IFQ_LOCK(ifq); 4042 IFQ_DEQUEUE_NOLOCK(ifq, m); 4043 while (m != NULL) { 4044 iflib_if_transmit(ifp, m); 4045 IFQ_DEQUEUE_NOLOCK(ifq, m); 4046 } 4047 IFQ_UNLOCK(ifq); 4048 } 4049 4050 static int 4051 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4052 { 4053 int err; 4054 4055 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4056 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4057 if (err == 0) 4058 iflib_altq_if_start(ifp); 4059 } else 4060 err = iflib_if_transmit(ifp, m); 4061 4062 return (err); 4063 } 4064 #endif /* ALTQ */ 4065 4066 static void 4067 iflib_if_qflush(if_t ifp) 4068 { 4069 if_ctx_t ctx = if_getsoftc(ifp); 4070 iflib_txq_t txq = ctx->ifc_txqs; 4071 int i; 4072 4073 STATE_LOCK(ctx); 4074 ctx->ifc_flags |= IFC_QFLUSH; 4075 STATE_UNLOCK(ctx); 4076 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4077 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4078 iflib_txq_check_drain(txq, 0); 4079 STATE_LOCK(ctx); 4080 ctx->ifc_flags &= ~IFC_QFLUSH; 4081 STATE_UNLOCK(ctx); 4082 4083 /* 4084 * When ALTQ is enabled, this will also take care of purging the 4085 * ALTQ queue(s). 4086 */ 4087 if_qflush(ifp); 4088 } 4089 4090 4091 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4092 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4093 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4094 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP) 4095 4096 static int 4097 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4098 { 4099 if_ctx_t ctx = if_getsoftc(ifp); 4100 struct ifreq *ifr = (struct ifreq *)data; 4101 #if defined(INET) || defined(INET6) 4102 struct ifaddr *ifa = (struct ifaddr *)data; 4103 #endif 4104 bool avoid_reset = false; 4105 int err = 0, reinit = 0, bits; 4106 4107 switch (command) { 4108 case SIOCSIFADDR: 4109 #ifdef INET 4110 if (ifa->ifa_addr->sa_family == AF_INET) 4111 avoid_reset = true; 4112 #endif 4113 #ifdef INET6 4114 if (ifa->ifa_addr->sa_family == AF_INET6) 4115 avoid_reset = true; 4116 #endif 4117 /* 4118 ** Calling init results in link renegotiation, 4119 ** so we avoid doing it when possible. 4120 */ 4121 if (avoid_reset) { 4122 if_setflagbits(ifp, IFF_UP,0); 4123 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4124 reinit = 1; 4125 #ifdef INET 4126 if (!(if_getflags(ifp) & IFF_NOARP)) 4127 arp_ifinit(ifp, ifa); 4128 #endif 4129 } else 4130 err = ether_ioctl(ifp, command, data); 4131 break; 4132 case SIOCSIFMTU: 4133 CTX_LOCK(ctx); 4134 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4135 CTX_UNLOCK(ctx); 4136 break; 4137 } 4138 bits = if_getdrvflags(ifp); 4139 /* stop the driver and free any clusters before proceeding */ 4140 iflib_stop(ctx); 4141 4142 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4143 STATE_LOCK(ctx); 4144 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4145 ctx->ifc_flags |= IFC_MULTISEG; 4146 else 4147 ctx->ifc_flags &= ~IFC_MULTISEG; 4148 STATE_UNLOCK(ctx); 4149 err = if_setmtu(ifp, ifr->ifr_mtu); 4150 } 4151 iflib_init_locked(ctx); 4152 STATE_LOCK(ctx); 4153 if_setdrvflags(ifp, bits); 4154 STATE_UNLOCK(ctx); 4155 CTX_UNLOCK(ctx); 4156 break; 4157 case SIOCSIFFLAGS: 4158 CTX_LOCK(ctx); 4159 if (if_getflags(ifp) & IFF_UP) { 4160 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4161 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4162 (IFF_PROMISC | IFF_ALLMULTI)) { 4163 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4164 } 4165 } else 4166 reinit = 1; 4167 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4168 iflib_stop(ctx); 4169 } 4170 ctx->ifc_if_flags = if_getflags(ifp); 4171 CTX_UNLOCK(ctx); 4172 break; 4173 case SIOCADDMULTI: 4174 case SIOCDELMULTI: 4175 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4176 CTX_LOCK(ctx); 4177 IFDI_INTR_DISABLE(ctx); 4178 IFDI_MULTI_SET(ctx); 4179 IFDI_INTR_ENABLE(ctx); 4180 CTX_UNLOCK(ctx); 4181 } 4182 break; 4183 case SIOCSIFMEDIA: 4184 CTX_LOCK(ctx); 4185 IFDI_MEDIA_SET(ctx); 4186 CTX_UNLOCK(ctx); 4187 /* FALLTHROUGH */ 4188 case SIOCGIFMEDIA: 4189 case SIOCGIFXMEDIA: 4190 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4191 break; 4192 case SIOCGI2C: 4193 { 4194 struct ifi2creq i2c; 4195 4196 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4197 if (err != 0) 4198 break; 4199 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4200 err = EINVAL; 4201 break; 4202 } 4203 if (i2c.len > sizeof(i2c.data)) { 4204 err = EINVAL; 4205 break; 4206 } 4207 4208 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4209 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4210 sizeof(i2c)); 4211 break; 4212 } 4213 case SIOCSIFCAP: 4214 { 4215 int mask, setmask, oldmask; 4216 4217 oldmask = if_getcapenable(ifp); 4218 mask = ifr->ifr_reqcap ^ oldmask; 4219 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP; 4220 setmask = 0; 4221 #ifdef TCP_OFFLOAD 4222 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4223 #endif 4224 setmask |= (mask & IFCAP_FLAGS); 4225 setmask |= (mask & IFCAP_WOL); 4226 4227 /* 4228 * If any RX csum has changed, change all the ones that 4229 * are supported by the driver. 4230 */ 4231 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4232 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4233 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4234 } 4235 4236 /* 4237 * want to ensure that traffic has stopped before we change any of the flags 4238 */ 4239 if (setmask) { 4240 CTX_LOCK(ctx); 4241 bits = if_getdrvflags(ifp); 4242 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4243 iflib_stop(ctx); 4244 STATE_LOCK(ctx); 4245 if_togglecapenable(ifp, setmask); 4246 STATE_UNLOCK(ctx); 4247 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4248 iflib_init_locked(ctx); 4249 STATE_LOCK(ctx); 4250 if_setdrvflags(ifp, bits); 4251 STATE_UNLOCK(ctx); 4252 CTX_UNLOCK(ctx); 4253 } 4254 if_vlancap(ifp); 4255 break; 4256 } 4257 case SIOCGPRIVATE_0: 4258 case SIOCSDRVSPEC: 4259 case SIOCGDRVSPEC: 4260 CTX_LOCK(ctx); 4261 err = IFDI_PRIV_IOCTL(ctx, command, data); 4262 CTX_UNLOCK(ctx); 4263 break; 4264 default: 4265 err = ether_ioctl(ifp, command, data); 4266 break; 4267 } 4268 if (reinit) 4269 iflib_if_init(ctx); 4270 return (err); 4271 } 4272 4273 static uint64_t 4274 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4275 { 4276 if_ctx_t ctx = if_getsoftc(ifp); 4277 4278 return (IFDI_GET_COUNTER(ctx, cnt)); 4279 } 4280 4281 /********************************************************************* 4282 * 4283 * OTHER FUNCTIONS EXPORTED TO THE STACK 4284 * 4285 **********************************************************************/ 4286 4287 static void 4288 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4289 { 4290 if_ctx_t ctx = if_getsoftc(ifp); 4291 4292 if ((void *)ctx != arg) 4293 return; 4294 4295 if ((vtag == 0) || (vtag > 4095)) 4296 return; 4297 4298 if (iflib_in_detach(ctx)) 4299 return; 4300 4301 CTX_LOCK(ctx); 4302 IFDI_VLAN_REGISTER(ctx, vtag); 4303 /* Re-init to load the changes */ 4304 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4305 iflib_if_init_locked(ctx); 4306 CTX_UNLOCK(ctx); 4307 } 4308 4309 static void 4310 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4311 { 4312 if_ctx_t ctx = if_getsoftc(ifp); 4313 4314 if ((void *)ctx != arg) 4315 return; 4316 4317 if ((vtag == 0) || (vtag > 4095)) 4318 return; 4319 4320 CTX_LOCK(ctx); 4321 IFDI_VLAN_UNREGISTER(ctx, vtag); 4322 /* Re-init to load the changes */ 4323 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4324 iflib_if_init_locked(ctx); 4325 CTX_UNLOCK(ctx); 4326 } 4327 4328 static void 4329 iflib_led_func(void *arg, int onoff) 4330 { 4331 if_ctx_t ctx = arg; 4332 4333 CTX_LOCK(ctx); 4334 IFDI_LED_FUNC(ctx, onoff); 4335 CTX_UNLOCK(ctx); 4336 } 4337 4338 /********************************************************************* 4339 * 4340 * BUS FUNCTION DEFINITIONS 4341 * 4342 **********************************************************************/ 4343 4344 int 4345 iflib_device_probe(device_t dev) 4346 { 4347 const pci_vendor_info_t *ent; 4348 if_shared_ctx_t sctx; 4349 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4350 uint16_t pci_vendor_id; 4351 4352 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4353 return (ENOTSUP); 4354 4355 pci_vendor_id = pci_get_vendor(dev); 4356 pci_device_id = pci_get_device(dev); 4357 pci_subvendor_id = pci_get_subvendor(dev); 4358 pci_subdevice_id = pci_get_subdevice(dev); 4359 pci_rev_id = pci_get_revid(dev); 4360 if (sctx->isc_parse_devinfo != NULL) 4361 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4362 4363 ent = sctx->isc_vendor_info; 4364 while (ent->pvi_vendor_id != 0) { 4365 if (pci_vendor_id != ent->pvi_vendor_id) { 4366 ent++; 4367 continue; 4368 } 4369 if ((pci_device_id == ent->pvi_device_id) && 4370 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4371 (ent->pvi_subvendor_id == 0)) && 4372 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4373 (ent->pvi_subdevice_id == 0)) && 4374 ((pci_rev_id == ent->pvi_rev_id) || 4375 (ent->pvi_rev_id == 0))) { 4376 4377 device_set_desc_copy(dev, ent->pvi_name); 4378 /* this needs to be changed to zero if the bus probing code 4379 * ever stops re-probing on best match because the sctx 4380 * may have its values over written by register calls 4381 * in subsequent probes 4382 */ 4383 return (BUS_PROBE_DEFAULT); 4384 } 4385 ent++; 4386 } 4387 return (ENXIO); 4388 } 4389 4390 int 4391 iflib_device_probe_vendor(device_t dev) 4392 { 4393 int probe; 4394 4395 probe = iflib_device_probe(dev); 4396 if (probe == BUS_PROBE_DEFAULT) 4397 return (BUS_PROBE_VENDOR); 4398 else 4399 return (probe); 4400 } 4401 4402 static void 4403 iflib_reset_qvalues(if_ctx_t ctx) 4404 { 4405 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4406 if_shared_ctx_t sctx = ctx->ifc_sctx; 4407 device_t dev = ctx->ifc_dev; 4408 int i; 4409 4410 if (ctx->ifc_sysctl_ntxqs != 0) 4411 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4412 if (ctx->ifc_sysctl_nrxqs != 0) 4413 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4414 4415 for (i = 0; i < sctx->isc_ntxqs; i++) { 4416 if (ctx->ifc_sysctl_ntxds[i] != 0) 4417 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4418 else 4419 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4420 } 4421 4422 for (i = 0; i < sctx->isc_nrxqs; i++) { 4423 if (ctx->ifc_sysctl_nrxds[i] != 0) 4424 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4425 else 4426 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4427 } 4428 4429 for (i = 0; i < sctx->isc_nrxqs; i++) { 4430 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4431 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4432 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4433 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4434 } 4435 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4436 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4437 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4438 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4439 } 4440 if (!powerof2(scctx->isc_nrxd[i])) { 4441 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4442 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4443 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4444 } 4445 } 4446 4447 for (i = 0; i < sctx->isc_ntxqs; i++) { 4448 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4449 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4450 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4451 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4452 } 4453 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4454 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4455 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4456 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4457 } 4458 if (!powerof2(scctx->isc_ntxd[i])) { 4459 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4460 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4461 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4462 } 4463 } 4464 } 4465 4466 static void 4467 iflib_add_pfil(if_ctx_t ctx) 4468 { 4469 struct pfil_head *pfil; 4470 struct pfil_head_args pa; 4471 iflib_rxq_t rxq; 4472 int i; 4473 4474 pa.pa_version = PFIL_VERSION; 4475 pa.pa_flags = PFIL_IN; 4476 pa.pa_type = PFIL_TYPE_ETHERNET; 4477 pa.pa_headname = ctx->ifc_ifp->if_xname; 4478 pfil = pfil_head_register(&pa); 4479 4480 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4481 rxq->pfil = pfil; 4482 } 4483 } 4484 4485 static void 4486 iflib_rem_pfil(if_ctx_t ctx) 4487 { 4488 struct pfil_head *pfil; 4489 iflib_rxq_t rxq; 4490 int i; 4491 4492 rxq = ctx->ifc_rxqs; 4493 pfil = rxq->pfil; 4494 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4495 rxq->pfil = NULL; 4496 } 4497 pfil_head_unregister(pfil); 4498 } 4499 4500 static uint16_t 4501 get_ctx_core_offset(if_ctx_t ctx) 4502 { 4503 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4504 struct cpu_offset *op; 4505 uint16_t qc; 4506 uint16_t ret = ctx->ifc_sysctl_core_offset; 4507 4508 if (ret != CORE_OFFSET_UNSPECIFIED) 4509 return (ret); 4510 4511 if (ctx->ifc_sysctl_separate_txrx) 4512 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets; 4513 else 4514 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets); 4515 4516 mtx_lock(&cpu_offset_mtx); 4517 SLIST_FOREACH(op, &cpu_offsets, entries) { 4518 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4519 ret = op->offset; 4520 op->offset += qc; 4521 MPASS(op->refcount < UINT_MAX); 4522 op->refcount++; 4523 break; 4524 } 4525 } 4526 if (ret == CORE_OFFSET_UNSPECIFIED) { 4527 ret = 0; 4528 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4529 M_NOWAIT | M_ZERO); 4530 if (op == NULL) { 4531 device_printf(ctx->ifc_dev, 4532 "allocation for cpu offset failed.\n"); 4533 } else { 4534 op->offset = qc; 4535 op->refcount = 1; 4536 CPU_COPY(&ctx->ifc_cpus, &op->set); 4537 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4538 } 4539 } 4540 mtx_unlock(&cpu_offset_mtx); 4541 4542 return (ret); 4543 } 4544 4545 static void 4546 unref_ctx_core_offset(if_ctx_t ctx) 4547 { 4548 struct cpu_offset *op, *top; 4549 4550 mtx_lock(&cpu_offset_mtx); 4551 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4552 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4553 MPASS(op->refcount > 0); 4554 op->refcount--; 4555 if (op->refcount == 0) { 4556 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4557 free(op, M_IFLIB); 4558 } 4559 break; 4560 } 4561 } 4562 mtx_unlock(&cpu_offset_mtx); 4563 } 4564 4565 int 4566 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4567 { 4568 if_ctx_t ctx; 4569 if_t ifp; 4570 if_softc_ctx_t scctx; 4571 kobjop_desc_t kobj_desc; 4572 kobj_method_t *kobj_method; 4573 int err, msix, rid; 4574 uint16_t main_rxq, main_txq; 4575 4576 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4577 4578 if (sc == NULL) { 4579 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4580 device_set_softc(dev, ctx); 4581 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4582 } 4583 4584 ctx->ifc_sctx = sctx; 4585 ctx->ifc_dev = dev; 4586 ctx->ifc_softc = sc; 4587 4588 if ((err = iflib_register(ctx)) != 0) { 4589 device_printf(dev, "iflib_register failed %d\n", err); 4590 goto fail_ctx_free; 4591 } 4592 iflib_add_device_sysctl_pre(ctx); 4593 4594 scctx = &ctx->ifc_softc_ctx; 4595 ifp = ctx->ifc_ifp; 4596 4597 iflib_reset_qvalues(ctx); 4598 CTX_LOCK(ctx); 4599 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4600 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4601 goto fail_unlock; 4602 } 4603 _iflib_pre_assert(scctx); 4604 ctx->ifc_txrx = *scctx->isc_txrx; 4605 4606 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 4607 ctx->ifc_mediap = scctx->isc_media; 4608 4609 #ifdef INVARIANTS 4610 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4611 MPASS(scctx->isc_tx_csum_flags); 4612 #endif 4613 4614 if_setcapabilities(ifp, 4615 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP); 4616 if_setcapenable(ifp, 4617 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP); 4618 4619 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4620 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4621 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4622 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4623 4624 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4625 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4626 4627 /* XXX change for per-queue sizes */ 4628 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4629 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4630 4631 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4632 MAX_SINGLE_PACKET_FRACTION) 4633 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4634 MAX_SINGLE_PACKET_FRACTION); 4635 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4636 MAX_SINGLE_PACKET_FRACTION) 4637 scctx->isc_tx_tso_segments_max = max(1, 4638 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4639 4640 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4641 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4642 /* 4643 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4644 * but some MACs do. 4645 */ 4646 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4647 IP_MAXPACKET)); 4648 /* 4649 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4650 * into account. In the worst case, each of these calls will 4651 * add another mbuf and, thus, the requirement for another DMA 4652 * segment. So for best performance, it doesn't make sense to 4653 * advertize a maximum of TSO segments that typically will 4654 * require defragmentation in iflib_encap(). 4655 */ 4656 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4657 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4658 } 4659 if (scctx->isc_rss_table_size == 0) 4660 scctx->isc_rss_table_size = 64; 4661 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4662 4663 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4664 /* XXX format name */ 4665 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4666 NULL, NULL, "admin"); 4667 4668 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4669 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4670 device_printf(dev, "Unable to fetch CPU list\n"); 4671 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4672 } 4673 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4674 4675 /* 4676 ** Now set up MSI or MSI-X, should return us the number of supported 4677 ** vectors (will be 1 for a legacy interrupt and MSI). 4678 */ 4679 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4680 msix = scctx->isc_vectors; 4681 } else if (scctx->isc_msix_bar != 0) 4682 /* 4683 * The simple fact that isc_msix_bar is not 0 does not mean we 4684 * we have a good value there that is known to work. 4685 */ 4686 msix = iflib_msix_init(ctx); 4687 else { 4688 scctx->isc_vectors = 1; 4689 scctx->isc_ntxqsets = 1; 4690 scctx->isc_nrxqsets = 1; 4691 scctx->isc_intr = IFLIB_INTR_LEGACY; 4692 msix = 0; 4693 } 4694 /* Get memory for the station queues */ 4695 if ((err = iflib_queues_alloc(ctx))) { 4696 device_printf(dev, "Unable to allocate queue memory\n"); 4697 goto fail_intr_free; 4698 } 4699 4700 if ((err = iflib_qset_structures_setup(ctx))) 4701 goto fail_queues; 4702 4703 /* 4704 * Now that we know how many queues there are, get the core offset. 4705 */ 4706 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 4707 4708 /* 4709 * Group taskqueues aren't properly set up until SMP is started, 4710 * so we disable interrupts until we can handle them post 4711 * SI_SUB_SMP. 4712 * 4713 * XXX: disabling interrupts doesn't actually work, at least for 4714 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4715 * we do null handling and depend on this not causing too large an 4716 * interrupt storm. 4717 */ 4718 IFDI_INTR_DISABLE(ctx); 4719 4720 if (msix > 1) { 4721 /* 4722 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 4723 * aren't the default NULL implementation. 4724 */ 4725 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 4726 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4727 kobj_desc); 4728 if (kobj_method == &kobj_desc->deflt) { 4729 device_printf(dev, 4730 "MSI-X requires ifdi_rx_queue_intr_enable method"); 4731 err = EOPNOTSUPP; 4732 goto fail_queues; 4733 } 4734 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 4735 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4736 kobj_desc); 4737 if (kobj_method == &kobj_desc->deflt) { 4738 device_printf(dev, 4739 "MSI-X requires ifdi_tx_queue_intr_enable method"); 4740 err = EOPNOTSUPP; 4741 goto fail_queues; 4742 } 4743 4744 /* 4745 * Assign the MSI-X vectors. 4746 * Note that the default NULL ifdi_msix_intr_assign method will 4747 * fail here, too. 4748 */ 4749 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 4750 if (err != 0) { 4751 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 4752 err); 4753 goto fail_queues; 4754 } 4755 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 4756 rid = 0; 4757 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4758 MPASS(msix == 1); 4759 rid = 1; 4760 } 4761 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4762 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4763 goto fail_queues; 4764 } 4765 } else { 4766 device_printf(dev, 4767 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 4768 err = ENODEV; 4769 goto fail_intr_free; 4770 } 4771 4772 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4773 4774 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4775 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4776 goto fail_detach; 4777 } 4778 4779 /* 4780 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4781 * This must appear after the call to ether_ifattach() because 4782 * ether_ifattach() sets if_hdrlen to the default value. 4783 */ 4784 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4785 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4786 4787 if ((err = iflib_netmap_attach(ctx))) { 4788 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4789 goto fail_detach; 4790 } 4791 *ctxp = ctx; 4792 4793 DEBUGNET_SET(ctx->ifc_ifp, iflib); 4794 4795 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4796 iflib_add_device_sysctl_post(ctx); 4797 iflib_add_pfil(ctx); 4798 ctx->ifc_flags |= IFC_INIT_DONE; 4799 CTX_UNLOCK(ctx); 4800 4801 return (0); 4802 4803 fail_detach: 4804 ether_ifdetach(ctx->ifc_ifp); 4805 fail_intr_free: 4806 iflib_free_intr_mem(ctx); 4807 fail_queues: 4808 iflib_tx_structures_free(ctx); 4809 iflib_rx_structures_free(ctx); 4810 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task); 4811 IFDI_DETACH(ctx); 4812 fail_unlock: 4813 CTX_UNLOCK(ctx); 4814 iflib_deregister(ctx); 4815 fail_ctx_free: 4816 device_set_softc(ctx->ifc_dev, NULL); 4817 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4818 free(ctx->ifc_softc, M_IFLIB); 4819 free(ctx, M_IFLIB); 4820 return (err); 4821 } 4822 4823 int 4824 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4825 struct iflib_cloneattach_ctx *clctx) 4826 { 4827 int err; 4828 if_ctx_t ctx; 4829 if_t ifp; 4830 if_softc_ctx_t scctx; 4831 int i; 4832 void *sc; 4833 uint16_t main_txq; 4834 uint16_t main_rxq; 4835 4836 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4837 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4838 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4839 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4840 ctx->ifc_flags |= IFC_PSEUDO; 4841 4842 ctx->ifc_sctx = sctx; 4843 ctx->ifc_softc = sc; 4844 ctx->ifc_dev = dev; 4845 4846 if ((err = iflib_register(ctx)) != 0) { 4847 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4848 goto fail_ctx_free; 4849 } 4850 iflib_add_device_sysctl_pre(ctx); 4851 4852 scctx = &ctx->ifc_softc_ctx; 4853 ifp = ctx->ifc_ifp; 4854 4855 iflib_reset_qvalues(ctx); 4856 CTX_LOCK(ctx); 4857 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4858 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4859 goto fail_unlock; 4860 } 4861 if (sctx->isc_flags & IFLIB_GEN_MAC) 4862 ether_gen_addr(ifp, &ctx->ifc_mac); 4863 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4864 clctx->cc_params)) != 0) { 4865 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4866 goto fail_ctx_free; 4867 } 4868 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4869 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4870 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4871 4872 #ifdef INVARIANTS 4873 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4874 MPASS(scctx->isc_tx_csum_flags); 4875 #endif 4876 4877 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4878 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4879 4880 ifp->if_flags |= IFF_NOGROUP; 4881 if (sctx->isc_flags & IFLIB_PSEUDO) { 4882 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4883 4884 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4885 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4886 goto fail_detach; 4887 } 4888 *ctxp = ctx; 4889 4890 /* 4891 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4892 * This must appear after the call to ether_ifattach() because 4893 * ether_ifattach() sets if_hdrlen to the default value. 4894 */ 4895 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4896 if_setifheaderlen(ifp, 4897 sizeof(struct ether_vlan_header)); 4898 4899 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4900 iflib_add_device_sysctl_post(ctx); 4901 ctx->ifc_flags |= IFC_INIT_DONE; 4902 return (0); 4903 } 4904 _iflib_pre_assert(scctx); 4905 ctx->ifc_txrx = *scctx->isc_txrx; 4906 4907 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4908 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4909 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4910 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4911 4912 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4913 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4914 4915 /* XXX change for per-queue sizes */ 4916 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4917 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4918 4919 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4920 MAX_SINGLE_PACKET_FRACTION) 4921 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4922 MAX_SINGLE_PACKET_FRACTION); 4923 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4924 MAX_SINGLE_PACKET_FRACTION) 4925 scctx->isc_tx_tso_segments_max = max(1, 4926 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4927 4928 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4929 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4930 /* 4931 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4932 * but some MACs do. 4933 */ 4934 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4935 IP_MAXPACKET)); 4936 /* 4937 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4938 * into account. In the worst case, each of these calls will 4939 * add another mbuf and, thus, the requirement for another DMA 4940 * segment. So for best performance, it doesn't make sense to 4941 * advertize a maximum of TSO segments that typically will 4942 * require defragmentation in iflib_encap(). 4943 */ 4944 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4945 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4946 } 4947 if (scctx->isc_rss_table_size == 0) 4948 scctx->isc_rss_table_size = 64; 4949 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4950 4951 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4952 /* XXX format name */ 4953 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4954 NULL, NULL, "admin"); 4955 4956 /* XXX --- can support > 1 -- but keep it simple for now */ 4957 scctx->isc_intr = IFLIB_INTR_LEGACY; 4958 4959 /* Get memory for the station queues */ 4960 if ((err = iflib_queues_alloc(ctx))) { 4961 device_printf(dev, "Unable to allocate queue memory\n"); 4962 goto fail_iflib_detach; 4963 } 4964 4965 if ((err = iflib_qset_structures_setup(ctx))) { 4966 device_printf(dev, "qset structure setup failed %d\n", err); 4967 goto fail_queues; 4968 } 4969 4970 /* 4971 * XXX What if anything do we want to do about interrupts? 4972 */ 4973 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4974 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4975 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4976 goto fail_detach; 4977 } 4978 4979 /* 4980 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4981 * This must appear after the call to ether_ifattach() because 4982 * ether_ifattach() sets if_hdrlen to the default value. 4983 */ 4984 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4985 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4986 4987 /* XXX handle more than one queue */ 4988 for (i = 0; i < scctx->isc_nrxqsets; i++) 4989 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4990 4991 *ctxp = ctx; 4992 4993 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4994 iflib_add_device_sysctl_post(ctx); 4995 ctx->ifc_flags |= IFC_INIT_DONE; 4996 CTX_UNLOCK(ctx); 4997 4998 return (0); 4999 fail_detach: 5000 ether_ifdetach(ctx->ifc_ifp); 5001 fail_queues: 5002 iflib_tx_structures_free(ctx); 5003 iflib_rx_structures_free(ctx); 5004 fail_iflib_detach: 5005 IFDI_DETACH(ctx); 5006 fail_unlock: 5007 CTX_UNLOCK(ctx); 5008 iflib_deregister(ctx); 5009 fail_ctx_free: 5010 free(ctx->ifc_softc, M_IFLIB); 5011 free(ctx, M_IFLIB); 5012 return (err); 5013 } 5014 5015 int 5016 iflib_pseudo_deregister(if_ctx_t ctx) 5017 { 5018 if_t ifp = ctx->ifc_ifp; 5019 iflib_txq_t txq; 5020 iflib_rxq_t rxq; 5021 int i, j; 5022 struct taskqgroup *tqg; 5023 iflib_fl_t fl; 5024 5025 /* Unregister VLAN event handlers early */ 5026 iflib_unregister_vlan_handlers(ctx); 5027 5028 ether_ifdetach(ifp); 5029 /* XXX drain any dependent tasks */ 5030 tqg = qgroup_if_io_tqg; 5031 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5032 callout_drain(&txq->ift_timer); 5033 if (txq->ift_task.gt_uniq != NULL) 5034 taskqgroup_detach(tqg, &txq->ift_task); 5035 } 5036 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5037 if (rxq->ifr_task.gt_uniq != NULL) 5038 taskqgroup_detach(tqg, &rxq->ifr_task); 5039 5040 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5041 free(fl->ifl_rx_bitmap, M_IFLIB); 5042 } 5043 tqg = qgroup_if_config_tqg; 5044 if (ctx->ifc_admin_task.gt_uniq != NULL) 5045 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5046 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5047 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5048 5049 iflib_tx_structures_free(ctx); 5050 iflib_rx_structures_free(ctx); 5051 5052 iflib_deregister(ctx); 5053 5054 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5055 free(ctx->ifc_softc, M_IFLIB); 5056 free(ctx, M_IFLIB); 5057 return (0); 5058 } 5059 5060 int 5061 iflib_device_attach(device_t dev) 5062 { 5063 if_ctx_t ctx; 5064 if_shared_ctx_t sctx; 5065 5066 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5067 return (ENOTSUP); 5068 5069 pci_enable_busmaster(dev); 5070 5071 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5072 } 5073 5074 int 5075 iflib_device_deregister(if_ctx_t ctx) 5076 { 5077 if_t ifp = ctx->ifc_ifp; 5078 iflib_txq_t txq; 5079 iflib_rxq_t rxq; 5080 device_t dev = ctx->ifc_dev; 5081 int i, j; 5082 struct taskqgroup *tqg; 5083 iflib_fl_t fl; 5084 5085 /* Make sure VLANS are not using driver */ 5086 if (if_vlantrunkinuse(ifp)) { 5087 device_printf(dev, "Vlan in use, detach first\n"); 5088 return (EBUSY); 5089 } 5090 #ifdef PCI_IOV 5091 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5092 device_printf(dev, "SR-IOV in use; detach first.\n"); 5093 return (EBUSY); 5094 } 5095 #endif 5096 5097 STATE_LOCK(ctx); 5098 ctx->ifc_flags |= IFC_IN_DETACH; 5099 STATE_UNLOCK(ctx); 5100 5101 /* Unregister VLAN handlers before calling iflib_stop() */ 5102 iflib_unregister_vlan_handlers(ctx); 5103 5104 iflib_netmap_detach(ifp); 5105 ether_ifdetach(ifp); 5106 5107 CTX_LOCK(ctx); 5108 iflib_stop(ctx); 5109 CTX_UNLOCK(ctx); 5110 5111 iflib_rem_pfil(ctx); 5112 if (ctx->ifc_led_dev != NULL) 5113 led_destroy(ctx->ifc_led_dev); 5114 /* XXX drain any dependent tasks */ 5115 tqg = qgroup_if_io_tqg; 5116 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5117 callout_drain(&txq->ift_timer); 5118 if (txq->ift_task.gt_uniq != NULL) 5119 taskqgroup_detach(tqg, &txq->ift_task); 5120 } 5121 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5122 if (rxq->ifr_task.gt_uniq != NULL) 5123 taskqgroup_detach(tqg, &rxq->ifr_task); 5124 5125 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5126 free(fl->ifl_rx_bitmap, M_IFLIB); 5127 } 5128 tqg = qgroup_if_config_tqg; 5129 if (ctx->ifc_admin_task.gt_uniq != NULL) 5130 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5131 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5132 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5133 CTX_LOCK(ctx); 5134 IFDI_DETACH(ctx); 5135 CTX_UNLOCK(ctx); 5136 5137 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5138 iflib_free_intr_mem(ctx); 5139 5140 bus_generic_detach(dev); 5141 5142 iflib_tx_structures_free(ctx); 5143 iflib_rx_structures_free(ctx); 5144 5145 iflib_deregister(ctx); 5146 5147 device_set_softc(ctx->ifc_dev, NULL); 5148 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5149 free(ctx->ifc_softc, M_IFLIB); 5150 unref_ctx_core_offset(ctx); 5151 free(ctx, M_IFLIB); 5152 return (0); 5153 } 5154 5155 static void 5156 iflib_free_intr_mem(if_ctx_t ctx) 5157 { 5158 5159 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5160 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5161 } 5162 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5163 pci_release_msi(ctx->ifc_dev); 5164 } 5165 if (ctx->ifc_msix_mem != NULL) { 5166 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5167 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5168 ctx->ifc_msix_mem = NULL; 5169 } 5170 } 5171 5172 int 5173 iflib_device_detach(device_t dev) 5174 { 5175 if_ctx_t ctx = device_get_softc(dev); 5176 5177 return (iflib_device_deregister(ctx)); 5178 } 5179 5180 int 5181 iflib_device_suspend(device_t dev) 5182 { 5183 if_ctx_t ctx = device_get_softc(dev); 5184 5185 CTX_LOCK(ctx); 5186 IFDI_SUSPEND(ctx); 5187 CTX_UNLOCK(ctx); 5188 5189 return bus_generic_suspend(dev); 5190 } 5191 int 5192 iflib_device_shutdown(device_t dev) 5193 { 5194 if_ctx_t ctx = device_get_softc(dev); 5195 5196 CTX_LOCK(ctx); 5197 IFDI_SHUTDOWN(ctx); 5198 CTX_UNLOCK(ctx); 5199 5200 return bus_generic_suspend(dev); 5201 } 5202 5203 5204 int 5205 iflib_device_resume(device_t dev) 5206 { 5207 if_ctx_t ctx = device_get_softc(dev); 5208 iflib_txq_t txq = ctx->ifc_txqs; 5209 5210 CTX_LOCK(ctx); 5211 IFDI_RESUME(ctx); 5212 iflib_if_init_locked(ctx); 5213 CTX_UNLOCK(ctx); 5214 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5215 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5216 5217 return (bus_generic_resume(dev)); 5218 } 5219 5220 int 5221 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5222 { 5223 int error; 5224 if_ctx_t ctx = device_get_softc(dev); 5225 5226 CTX_LOCK(ctx); 5227 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5228 CTX_UNLOCK(ctx); 5229 5230 return (error); 5231 } 5232 5233 void 5234 iflib_device_iov_uninit(device_t dev) 5235 { 5236 if_ctx_t ctx = device_get_softc(dev); 5237 5238 CTX_LOCK(ctx); 5239 IFDI_IOV_UNINIT(ctx); 5240 CTX_UNLOCK(ctx); 5241 } 5242 5243 int 5244 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5245 { 5246 int error; 5247 if_ctx_t ctx = device_get_softc(dev); 5248 5249 CTX_LOCK(ctx); 5250 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5251 CTX_UNLOCK(ctx); 5252 5253 return (error); 5254 } 5255 5256 /********************************************************************* 5257 * 5258 * MODULE FUNCTION DEFINITIONS 5259 * 5260 **********************************************************************/ 5261 5262 /* 5263 * - Start a fast taskqueue thread for each core 5264 * - Start a taskqueue for control operations 5265 */ 5266 static int 5267 iflib_module_init(void) 5268 { 5269 return (0); 5270 } 5271 5272 static int 5273 iflib_module_event_handler(module_t mod, int what, void *arg) 5274 { 5275 int err; 5276 5277 switch (what) { 5278 case MOD_LOAD: 5279 if ((err = iflib_module_init()) != 0) 5280 return (err); 5281 break; 5282 case MOD_UNLOAD: 5283 return (EBUSY); 5284 default: 5285 return (EOPNOTSUPP); 5286 } 5287 5288 return (0); 5289 } 5290 5291 /********************************************************************* 5292 * 5293 * PUBLIC FUNCTION DEFINITIONS 5294 * ordered as in iflib.h 5295 * 5296 **********************************************************************/ 5297 5298 5299 static void 5300 _iflib_assert(if_shared_ctx_t sctx) 5301 { 5302 int i; 5303 5304 MPASS(sctx->isc_tx_maxsize); 5305 MPASS(sctx->isc_tx_maxsegsize); 5306 5307 MPASS(sctx->isc_rx_maxsize); 5308 MPASS(sctx->isc_rx_nsegments); 5309 MPASS(sctx->isc_rx_maxsegsize); 5310 5311 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5312 for (i = 0; i < sctx->isc_nrxqs; i++) { 5313 MPASS(sctx->isc_nrxd_min[i]); 5314 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5315 MPASS(sctx->isc_nrxd_max[i]); 5316 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5317 MPASS(sctx->isc_nrxd_default[i]); 5318 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5319 } 5320 5321 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5322 for (i = 0; i < sctx->isc_ntxqs; i++) { 5323 MPASS(sctx->isc_ntxd_min[i]); 5324 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5325 MPASS(sctx->isc_ntxd_max[i]); 5326 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5327 MPASS(sctx->isc_ntxd_default[i]); 5328 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5329 } 5330 } 5331 5332 static void 5333 _iflib_pre_assert(if_softc_ctx_t scctx) 5334 { 5335 5336 MPASS(scctx->isc_txrx->ift_txd_encap); 5337 MPASS(scctx->isc_txrx->ift_txd_flush); 5338 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5339 MPASS(scctx->isc_txrx->ift_rxd_available); 5340 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5341 MPASS(scctx->isc_txrx->ift_rxd_refill); 5342 MPASS(scctx->isc_txrx->ift_rxd_flush); 5343 } 5344 5345 static int 5346 iflib_register(if_ctx_t ctx) 5347 { 5348 if_shared_ctx_t sctx = ctx->ifc_sctx; 5349 driver_t *driver = sctx->isc_driver; 5350 device_t dev = ctx->ifc_dev; 5351 if_t ifp; 5352 5353 _iflib_assert(sctx); 5354 5355 CTX_LOCK_INIT(ctx); 5356 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5357 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5358 if (ifp == NULL) { 5359 device_printf(dev, "can not allocate ifnet structure\n"); 5360 return (ENOMEM); 5361 } 5362 5363 /* 5364 * Initialize our context's device specific methods 5365 */ 5366 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5367 kobj_class_compile((kobj_class_t) driver); 5368 5369 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5370 if_setsoftc(ifp, ctx); 5371 if_setdev(ifp, dev); 5372 if_setinitfn(ifp, iflib_if_init); 5373 if_setioctlfn(ifp, iflib_if_ioctl); 5374 #ifdef ALTQ 5375 if_setstartfn(ifp, iflib_altq_if_start); 5376 if_settransmitfn(ifp, iflib_altq_if_transmit); 5377 if_setsendqready(ifp); 5378 #else 5379 if_settransmitfn(ifp, iflib_if_transmit); 5380 #endif 5381 if_setqflushfn(ifp, iflib_if_qflush); 5382 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5383 5384 ctx->ifc_vlan_attach_event = 5385 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5386 EVENTHANDLER_PRI_FIRST); 5387 ctx->ifc_vlan_detach_event = 5388 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5389 EVENTHANDLER_PRI_FIRST); 5390 5391 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5392 ctx->ifc_mediap = &ctx->ifc_media; 5393 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5394 iflib_media_change, iflib_media_status); 5395 } 5396 return (0); 5397 } 5398 5399 static void 5400 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5401 { 5402 /* Unregister VLAN events */ 5403 if (ctx->ifc_vlan_attach_event != NULL) { 5404 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5405 ctx->ifc_vlan_attach_event = NULL; 5406 } 5407 if (ctx->ifc_vlan_detach_event != NULL) { 5408 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5409 ctx->ifc_vlan_detach_event = NULL; 5410 } 5411 5412 } 5413 5414 static void 5415 iflib_deregister(if_ctx_t ctx) 5416 { 5417 if_t ifp = ctx->ifc_ifp; 5418 5419 /* Remove all media */ 5420 ifmedia_removeall(&ctx->ifc_media); 5421 5422 /* Ensure that VLAN event handlers are unregistered */ 5423 iflib_unregister_vlan_handlers(ctx); 5424 5425 /* Release kobject reference */ 5426 kobj_delete((kobj_t) ctx, NULL); 5427 5428 /* Free the ifnet structure */ 5429 if_free(ifp); 5430 5431 STATE_LOCK_DESTROY(ctx); 5432 5433 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5434 CTX_LOCK_DESTROY(ctx); 5435 } 5436 5437 static int 5438 iflib_queues_alloc(if_ctx_t ctx) 5439 { 5440 if_shared_ctx_t sctx = ctx->ifc_sctx; 5441 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5442 device_t dev = ctx->ifc_dev; 5443 int nrxqsets = scctx->isc_nrxqsets; 5444 int ntxqsets = scctx->isc_ntxqsets; 5445 iflib_txq_t txq; 5446 iflib_rxq_t rxq; 5447 iflib_fl_t fl = NULL; 5448 int i, j, cpu, err, txconf, rxconf; 5449 iflib_dma_info_t ifdip; 5450 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5451 uint32_t *txqsizes = scctx->isc_txqsizes; 5452 uint8_t nrxqs = sctx->isc_nrxqs; 5453 uint8_t ntxqs = sctx->isc_ntxqs; 5454 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5455 caddr_t *vaddrs; 5456 uint64_t *paddrs; 5457 5458 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5459 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5460 5461 /* Allocate the TX ring struct memory */ 5462 if (!(ctx->ifc_txqs = 5463 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5464 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5465 device_printf(dev, "Unable to allocate TX ring memory\n"); 5466 err = ENOMEM; 5467 goto fail; 5468 } 5469 5470 /* Now allocate the RX */ 5471 if (!(ctx->ifc_rxqs = 5472 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5473 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5474 device_printf(dev, "Unable to allocate RX ring memory\n"); 5475 err = ENOMEM; 5476 goto rx_fail; 5477 } 5478 5479 txq = ctx->ifc_txqs; 5480 rxq = ctx->ifc_rxqs; 5481 5482 /* 5483 * XXX handle allocation failure 5484 */ 5485 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5486 /* Set up some basics */ 5487 5488 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5489 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5490 device_printf(dev, 5491 "Unable to allocate TX DMA info memory\n"); 5492 err = ENOMEM; 5493 goto err_tx_desc; 5494 } 5495 txq->ift_ifdi = ifdip; 5496 for (j = 0; j < ntxqs; j++, ifdip++) { 5497 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5498 device_printf(dev, 5499 "Unable to allocate TX descriptors\n"); 5500 err = ENOMEM; 5501 goto err_tx_desc; 5502 } 5503 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5504 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5505 } 5506 txq->ift_ctx = ctx; 5507 txq->ift_id = i; 5508 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5509 txq->ift_br_offset = 1; 5510 } else { 5511 txq->ift_br_offset = 0; 5512 } 5513 /* XXX fix this */ 5514 txq->ift_timer.c_cpu = cpu; 5515 5516 if (iflib_txsd_alloc(txq)) { 5517 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5518 err = ENOMEM; 5519 goto err_tx_desc; 5520 } 5521 5522 /* Initialize the TX lock */ 5523 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5524 device_get_nameunit(dev), txq->ift_id); 5525 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5526 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5527 5528 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5529 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5530 if (err) { 5531 /* XXX free any allocated rings */ 5532 device_printf(dev, "Unable to allocate buf_ring\n"); 5533 goto err_tx_desc; 5534 } 5535 } 5536 5537 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5538 /* Set up some basics */ 5539 5540 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5541 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5542 device_printf(dev, 5543 "Unable to allocate RX DMA info memory\n"); 5544 err = ENOMEM; 5545 goto err_tx_desc; 5546 } 5547 5548 rxq->ifr_ifdi = ifdip; 5549 /* XXX this needs to be changed if #rx queues != #tx queues */ 5550 rxq->ifr_ntxqirq = 1; 5551 rxq->ifr_txqid[0] = i; 5552 for (j = 0; j < nrxqs; j++, ifdip++) { 5553 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5554 device_printf(dev, 5555 "Unable to allocate RX descriptors\n"); 5556 err = ENOMEM; 5557 goto err_tx_desc; 5558 } 5559 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5560 } 5561 rxq->ifr_ctx = ctx; 5562 rxq->ifr_id = i; 5563 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5564 rxq->ifr_fl_offset = 1; 5565 } else { 5566 rxq->ifr_fl_offset = 0; 5567 } 5568 rxq->ifr_nfl = nfree_lists; 5569 if (!(fl = 5570 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5571 device_printf(dev, "Unable to allocate free list memory\n"); 5572 err = ENOMEM; 5573 goto err_tx_desc; 5574 } 5575 rxq->ifr_fl = fl; 5576 for (j = 0; j < nfree_lists; j++) { 5577 fl[j].ifl_rxq = rxq; 5578 fl[j].ifl_id = j; 5579 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5580 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5581 } 5582 /* Allocate receive buffers for the ring */ 5583 if (iflib_rxsd_alloc(rxq)) { 5584 device_printf(dev, 5585 "Critical Failure setting up receive buffers\n"); 5586 err = ENOMEM; 5587 goto err_rx_desc; 5588 } 5589 5590 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5591 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5592 M_WAITOK); 5593 } 5594 5595 /* TXQs */ 5596 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5597 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5598 for (i = 0; i < ntxqsets; i++) { 5599 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5600 5601 for (j = 0; j < ntxqs; j++, di++) { 5602 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5603 paddrs[i*ntxqs + j] = di->idi_paddr; 5604 } 5605 } 5606 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5607 device_printf(ctx->ifc_dev, 5608 "Unable to allocate device TX queue\n"); 5609 iflib_tx_structures_free(ctx); 5610 free(vaddrs, M_IFLIB); 5611 free(paddrs, M_IFLIB); 5612 goto err_rx_desc; 5613 } 5614 free(vaddrs, M_IFLIB); 5615 free(paddrs, M_IFLIB); 5616 5617 /* RXQs */ 5618 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5619 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5620 for (i = 0; i < nrxqsets; i++) { 5621 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5622 5623 for (j = 0; j < nrxqs; j++, di++) { 5624 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5625 paddrs[i*nrxqs + j] = di->idi_paddr; 5626 } 5627 } 5628 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5629 device_printf(ctx->ifc_dev, 5630 "Unable to allocate device RX queue\n"); 5631 iflib_tx_structures_free(ctx); 5632 free(vaddrs, M_IFLIB); 5633 free(paddrs, M_IFLIB); 5634 goto err_rx_desc; 5635 } 5636 free(vaddrs, M_IFLIB); 5637 free(paddrs, M_IFLIB); 5638 5639 return (0); 5640 5641 /* XXX handle allocation failure changes */ 5642 err_rx_desc: 5643 err_tx_desc: 5644 rx_fail: 5645 if (ctx->ifc_rxqs != NULL) 5646 free(ctx->ifc_rxqs, M_IFLIB); 5647 ctx->ifc_rxqs = NULL; 5648 if (ctx->ifc_txqs != NULL) 5649 free(ctx->ifc_txqs, M_IFLIB); 5650 ctx->ifc_txqs = NULL; 5651 fail: 5652 return (err); 5653 } 5654 5655 static int 5656 iflib_tx_structures_setup(if_ctx_t ctx) 5657 { 5658 iflib_txq_t txq = ctx->ifc_txqs; 5659 int i; 5660 5661 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5662 iflib_txq_setup(txq); 5663 5664 return (0); 5665 } 5666 5667 static void 5668 iflib_tx_structures_free(if_ctx_t ctx) 5669 { 5670 iflib_txq_t txq = ctx->ifc_txqs; 5671 if_shared_ctx_t sctx = ctx->ifc_sctx; 5672 int i, j; 5673 5674 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5675 for (j = 0; j < sctx->isc_ntxqs; j++) 5676 iflib_dma_free(&txq->ift_ifdi[j]); 5677 iflib_txq_destroy(txq); 5678 } 5679 free(ctx->ifc_txqs, M_IFLIB); 5680 ctx->ifc_txqs = NULL; 5681 IFDI_QUEUES_FREE(ctx); 5682 } 5683 5684 /********************************************************************* 5685 * 5686 * Initialize all receive rings. 5687 * 5688 **********************************************************************/ 5689 static int 5690 iflib_rx_structures_setup(if_ctx_t ctx) 5691 { 5692 iflib_rxq_t rxq = ctx->ifc_rxqs; 5693 int q; 5694 #if defined(INET6) || defined(INET) 5695 int err, i; 5696 #endif 5697 5698 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5699 #if defined(INET6) || defined(INET) 5700 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) { 5701 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5702 TCP_LRO_ENTRIES, min(1024, 5703 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 5704 if (err != 0) { 5705 device_printf(ctx->ifc_dev, 5706 "LRO Initialization failed!\n"); 5707 goto fail; 5708 } 5709 } 5710 #endif 5711 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5712 } 5713 return (0); 5714 #if defined(INET6) || defined(INET) 5715 fail: 5716 /* 5717 * Free LRO resources allocated so far, we will only handle 5718 * the rings that completed, the failing case will have 5719 * cleaned up for itself. 'q' failed, so its the terminus. 5720 */ 5721 rxq = ctx->ifc_rxqs; 5722 for (i = 0; i < q; ++i, rxq++) { 5723 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5724 tcp_lro_free(&rxq->ifr_lc); 5725 } 5726 return (err); 5727 #endif 5728 } 5729 5730 /********************************************************************* 5731 * 5732 * Free all receive rings. 5733 * 5734 **********************************************************************/ 5735 static void 5736 iflib_rx_structures_free(if_ctx_t ctx) 5737 { 5738 iflib_rxq_t rxq = ctx->ifc_rxqs; 5739 if_shared_ctx_t sctx = ctx->ifc_sctx; 5740 int i, j; 5741 5742 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5743 for (j = 0; j < sctx->isc_nrxqs; j++) 5744 iflib_dma_free(&rxq->ifr_ifdi[j]); 5745 iflib_rx_sds_free(rxq); 5746 #if defined(INET6) || defined(INET) 5747 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5748 tcp_lro_free(&rxq->ifr_lc); 5749 #endif 5750 } 5751 free(ctx->ifc_rxqs, M_IFLIB); 5752 ctx->ifc_rxqs = NULL; 5753 } 5754 5755 static int 5756 iflib_qset_structures_setup(if_ctx_t ctx) 5757 { 5758 int err; 5759 5760 /* 5761 * It is expected that the caller takes care of freeing queues if this 5762 * fails. 5763 */ 5764 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5765 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5766 return (err); 5767 } 5768 5769 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5770 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5771 5772 return (err); 5773 } 5774 5775 int 5776 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5777 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5778 { 5779 5780 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5781 } 5782 5783 #ifdef SMP 5784 static int 5785 find_nth(if_ctx_t ctx, int qid) 5786 { 5787 cpuset_t cpus; 5788 int i, cpuid, eqid, count; 5789 5790 CPU_COPY(&ctx->ifc_cpus, &cpus); 5791 count = CPU_COUNT(&cpus); 5792 eqid = qid % count; 5793 /* clear up to the qid'th bit */ 5794 for (i = 0; i < eqid; i++) { 5795 cpuid = CPU_FFS(&cpus); 5796 MPASS(cpuid != 0); 5797 CPU_CLR(cpuid-1, &cpus); 5798 } 5799 cpuid = CPU_FFS(&cpus); 5800 MPASS(cpuid != 0); 5801 return (cpuid-1); 5802 } 5803 5804 #ifdef SCHED_ULE 5805 extern struct cpu_group *cpu_top; /* CPU topology */ 5806 5807 static int 5808 find_child_with_core(int cpu, struct cpu_group *grp) 5809 { 5810 int i; 5811 5812 if (grp->cg_children == 0) 5813 return -1; 5814 5815 MPASS(grp->cg_child); 5816 for (i = 0; i < grp->cg_children; i++) { 5817 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5818 return i; 5819 } 5820 5821 return -1; 5822 } 5823 5824 /* 5825 * Find the nth "close" core to the specified core 5826 * "close" is defined as the deepest level that shares 5827 * at least an L2 cache. With threads, this will be 5828 * threads on the same core. If the shared cache is L3 5829 * or higher, simply returns the same core. 5830 */ 5831 static int 5832 find_close_core(int cpu, int core_offset) 5833 { 5834 struct cpu_group *grp; 5835 int i; 5836 int fcpu; 5837 cpuset_t cs; 5838 5839 grp = cpu_top; 5840 if (grp == NULL) 5841 return cpu; 5842 i = 0; 5843 while ((i = find_child_with_core(cpu, grp)) != -1) { 5844 /* If the child only has one cpu, don't descend */ 5845 if (grp->cg_child[i].cg_count <= 1) 5846 break; 5847 grp = &grp->cg_child[i]; 5848 } 5849 5850 /* If they don't share at least an L2 cache, use the same CPU */ 5851 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5852 return cpu; 5853 5854 /* Now pick one */ 5855 CPU_COPY(&grp->cg_mask, &cs); 5856 5857 /* Add the selected CPU offset to core offset. */ 5858 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5859 if (fcpu - 1 == cpu) 5860 break; 5861 CPU_CLR(fcpu - 1, &cs); 5862 } 5863 MPASS(fcpu); 5864 5865 core_offset += i; 5866 5867 CPU_COPY(&grp->cg_mask, &cs); 5868 for (i = core_offset % grp->cg_count; i > 0; i--) { 5869 MPASS(CPU_FFS(&cs)); 5870 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5871 } 5872 MPASS(CPU_FFS(&cs)); 5873 return CPU_FFS(&cs) - 1; 5874 } 5875 #else 5876 static int 5877 find_close_core(int cpu, int core_offset __unused) 5878 { 5879 return cpu; 5880 } 5881 #endif 5882 5883 static int 5884 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5885 { 5886 switch (type) { 5887 case IFLIB_INTR_TX: 5888 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5889 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5890 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5891 case IFLIB_INTR_RX: 5892 case IFLIB_INTR_RXTX: 5893 /* RX queues get the specified core */ 5894 return qid / CPU_COUNT(&ctx->ifc_cpus); 5895 default: 5896 return -1; 5897 } 5898 } 5899 #else 5900 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5901 #define find_close_core(cpuid, tid) CPU_FIRST() 5902 #define find_nth(ctx, gid) CPU_FIRST() 5903 #endif 5904 5905 /* Just to avoid copy/paste */ 5906 static inline int 5907 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5908 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5909 const char *name) 5910 { 5911 device_t dev; 5912 int co, cpuid, err, tid; 5913 5914 dev = ctx->ifc_dev; 5915 co = ctx->ifc_sysctl_core_offset; 5916 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX) 5917 co += ctx->ifc_softc_ctx.isc_nrxqsets; 5918 cpuid = find_nth(ctx, qid + co); 5919 tid = get_core_offset(ctx, type, qid); 5920 if (tid < 0) { 5921 device_printf(dev, "get_core_offset failed\n"); 5922 return (EOPNOTSUPP); 5923 } 5924 cpuid = find_close_core(cpuid, tid); 5925 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 5926 name); 5927 if (err) { 5928 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 5929 return (err); 5930 } 5931 #ifdef notyet 5932 if (cpuid > ctx->ifc_cpuid_highest) 5933 ctx->ifc_cpuid_highest = cpuid; 5934 #endif 5935 return (0); 5936 } 5937 5938 int 5939 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5940 iflib_intr_type_t type, driver_filter_t *filter, 5941 void *filter_arg, int qid, const char *name) 5942 { 5943 device_t dev; 5944 struct grouptask *gtask; 5945 struct taskqgroup *tqg; 5946 iflib_filter_info_t info; 5947 gtask_fn_t *fn; 5948 int tqrid, err; 5949 driver_filter_t *intr_fast; 5950 void *q; 5951 5952 info = &ctx->ifc_filter_info; 5953 tqrid = rid; 5954 5955 switch (type) { 5956 /* XXX merge tx/rx for netmap? */ 5957 case IFLIB_INTR_TX: 5958 q = &ctx->ifc_txqs[qid]; 5959 info = &ctx->ifc_txqs[qid].ift_filter_info; 5960 gtask = &ctx->ifc_txqs[qid].ift_task; 5961 tqg = qgroup_if_io_tqg; 5962 fn = _task_fn_tx; 5963 intr_fast = iflib_fast_intr; 5964 GROUPTASK_INIT(gtask, 0, fn, q); 5965 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5966 break; 5967 case IFLIB_INTR_RX: 5968 q = &ctx->ifc_rxqs[qid]; 5969 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5970 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5971 tqg = qgroup_if_io_tqg; 5972 fn = _task_fn_rx; 5973 intr_fast = iflib_fast_intr; 5974 GROUPTASK_INIT(gtask, 0, fn, q); 5975 break; 5976 case IFLIB_INTR_RXTX: 5977 q = &ctx->ifc_rxqs[qid]; 5978 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5979 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5980 tqg = qgroup_if_io_tqg; 5981 fn = _task_fn_rx; 5982 intr_fast = iflib_fast_intr_rxtx; 5983 GROUPTASK_INIT(gtask, 0, fn, q); 5984 break; 5985 case IFLIB_INTR_ADMIN: 5986 q = ctx; 5987 tqrid = -1; 5988 info = &ctx->ifc_filter_info; 5989 gtask = &ctx->ifc_admin_task; 5990 tqg = qgroup_if_config_tqg; 5991 fn = _task_fn_admin; 5992 intr_fast = iflib_fast_intr_ctx; 5993 break; 5994 default: 5995 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 5996 __func__); 5997 return (EINVAL); 5998 } 5999 6000 info->ifi_filter = filter; 6001 info->ifi_filter_arg = filter_arg; 6002 info->ifi_task = gtask; 6003 info->ifi_ctx = q; 6004 6005 dev = ctx->ifc_dev; 6006 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6007 if (err != 0) { 6008 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6009 return (err); 6010 } 6011 if (type == IFLIB_INTR_ADMIN) 6012 return (0); 6013 6014 if (tqrid != -1) { 6015 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6016 q, name); 6017 if (err) 6018 return (err); 6019 } else { 6020 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6021 } 6022 6023 return (0); 6024 } 6025 6026 void 6027 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6028 { 6029 struct grouptask *gtask; 6030 struct taskqgroup *tqg; 6031 gtask_fn_t *fn; 6032 void *q; 6033 int err; 6034 6035 switch (type) { 6036 case IFLIB_INTR_TX: 6037 q = &ctx->ifc_txqs[qid]; 6038 gtask = &ctx->ifc_txqs[qid].ift_task; 6039 tqg = qgroup_if_io_tqg; 6040 fn = _task_fn_tx; 6041 break; 6042 case IFLIB_INTR_RX: 6043 q = &ctx->ifc_rxqs[qid]; 6044 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6045 tqg = qgroup_if_io_tqg; 6046 fn = _task_fn_rx; 6047 break; 6048 case IFLIB_INTR_IOV: 6049 q = ctx; 6050 gtask = &ctx->ifc_vflr_task; 6051 tqg = qgroup_if_config_tqg; 6052 fn = _task_fn_iov; 6053 break; 6054 default: 6055 panic("unknown net intr type"); 6056 } 6057 GROUPTASK_INIT(gtask, 0, fn, q); 6058 if (irq != NULL) { 6059 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6060 q, name); 6061 if (err) 6062 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 6063 irq->ii_res, name); 6064 } else { 6065 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 6066 } 6067 } 6068 6069 void 6070 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6071 { 6072 6073 if (irq->ii_tag) 6074 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6075 6076 if (irq->ii_res) 6077 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6078 rman_get_rid(irq->ii_res), irq->ii_res); 6079 } 6080 6081 static int 6082 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6083 { 6084 iflib_txq_t txq = ctx->ifc_txqs; 6085 iflib_rxq_t rxq = ctx->ifc_rxqs; 6086 if_irq_t irq = &ctx->ifc_legacy_irq; 6087 iflib_filter_info_t info; 6088 device_t dev; 6089 struct grouptask *gtask; 6090 struct resource *res; 6091 struct taskqgroup *tqg; 6092 gtask_fn_t *fn; 6093 void *q; 6094 int err, tqrid; 6095 bool rx_only; 6096 6097 q = &ctx->ifc_rxqs[0]; 6098 info = &rxq[0].ifr_filter_info; 6099 gtask = &rxq[0].ifr_task; 6100 tqg = qgroup_if_io_tqg; 6101 tqrid = *rid; 6102 fn = _task_fn_rx; 6103 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6104 6105 ctx->ifc_flags |= IFC_LEGACY; 6106 info->ifi_filter = filter; 6107 info->ifi_filter_arg = filter_arg; 6108 info->ifi_task = gtask; 6109 info->ifi_ctx = rx_only ? ctx : q; 6110 6111 dev = ctx->ifc_dev; 6112 /* We allocate a single interrupt resource */ 6113 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6114 iflib_fast_intr_rxtx, NULL, info, name); 6115 if (err != 0) 6116 return (err); 6117 GROUPTASK_INIT(gtask, 0, fn, q); 6118 res = irq->ii_res; 6119 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6120 6121 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6122 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6123 "tx"); 6124 return (0); 6125 } 6126 6127 void 6128 iflib_led_create(if_ctx_t ctx) 6129 { 6130 6131 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6132 device_get_nameunit(ctx->ifc_dev)); 6133 } 6134 6135 void 6136 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6137 { 6138 6139 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6140 } 6141 6142 void 6143 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6144 { 6145 6146 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6147 } 6148 6149 void 6150 iflib_admin_intr_deferred(if_ctx_t ctx) 6151 { 6152 #ifdef INVARIANTS 6153 struct grouptask *gtask; 6154 6155 gtask = &ctx->ifc_admin_task; 6156 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 6157 #endif 6158 6159 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6160 } 6161 6162 void 6163 iflib_iov_intr_deferred(if_ctx_t ctx) 6164 { 6165 6166 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6167 } 6168 6169 void 6170 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6171 { 6172 6173 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6174 name); 6175 } 6176 6177 void 6178 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6179 const char *name) 6180 { 6181 6182 GROUPTASK_INIT(gtask, 0, fn, ctx); 6183 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6184 name); 6185 } 6186 6187 void 6188 iflib_config_gtask_deinit(struct grouptask *gtask) 6189 { 6190 6191 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6192 } 6193 6194 void 6195 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6196 { 6197 if_t ifp = ctx->ifc_ifp; 6198 iflib_txq_t txq = ctx->ifc_txqs; 6199 6200 if_setbaudrate(ifp, baudrate); 6201 if (baudrate >= IF_Gbps(10)) { 6202 STATE_LOCK(ctx); 6203 ctx->ifc_flags |= IFC_PREFETCH; 6204 STATE_UNLOCK(ctx); 6205 } 6206 /* If link down, disable watchdog */ 6207 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6208 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6209 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6210 } 6211 ctx->ifc_link_state = link_state; 6212 if_link_state_change(ifp, link_state); 6213 } 6214 6215 static int 6216 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6217 { 6218 int credits; 6219 #ifdef INVARIANTS 6220 int credits_pre = txq->ift_cidx_processed; 6221 #endif 6222 6223 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6224 BUS_DMASYNC_POSTREAD); 6225 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6226 return (0); 6227 6228 txq->ift_processed += credits; 6229 txq->ift_cidx_processed += credits; 6230 6231 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6232 if (txq->ift_cidx_processed >= txq->ift_size) 6233 txq->ift_cidx_processed -= txq->ift_size; 6234 return (credits); 6235 } 6236 6237 static int 6238 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6239 { 6240 iflib_fl_t fl; 6241 u_int i; 6242 6243 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6244 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6245 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6246 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6247 budget)); 6248 } 6249 6250 void 6251 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6252 const char *description, if_int_delay_info_t info, 6253 int offset, int value) 6254 { 6255 info->iidi_ctx = ctx; 6256 info->iidi_offset = offset; 6257 info->iidi_value = value; 6258 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6259 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6260 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 6261 info, 0, iflib_sysctl_int_delay, "I", description); 6262 } 6263 6264 struct sx * 6265 iflib_ctx_lock_get(if_ctx_t ctx) 6266 { 6267 6268 return (&ctx->ifc_ctx_sx); 6269 } 6270 6271 static int 6272 iflib_msix_init(if_ctx_t ctx) 6273 { 6274 device_t dev = ctx->ifc_dev; 6275 if_shared_ctx_t sctx = ctx->ifc_sctx; 6276 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6277 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6278 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6279 6280 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6281 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6282 6283 if (bootverbose) 6284 device_printf(dev, "msix_init qsets capped at %d\n", 6285 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6286 6287 /* Override by tuneable */ 6288 if (scctx->isc_disable_msix) 6289 goto msi; 6290 6291 /* First try MSI-X */ 6292 if ((msgs = pci_msix_count(dev)) == 0) { 6293 if (bootverbose) 6294 device_printf(dev, "MSI-X not supported or disabled\n"); 6295 goto msi; 6296 } 6297 6298 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6299 /* 6300 * bar == -1 => "trust me I know what I'm doing" 6301 * Some drivers are for hardware that is so shoddily 6302 * documented that no one knows which bars are which 6303 * so the developer has to map all bars. This hack 6304 * allows shoddy garbage to use MSI-X in this framework. 6305 */ 6306 if (bar != -1) { 6307 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6308 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6309 if (ctx->ifc_msix_mem == NULL) { 6310 device_printf(dev, "Unable to map MSI-X table\n"); 6311 goto msi; 6312 } 6313 } 6314 6315 admincnt = sctx->isc_admin_intrcnt; 6316 #if IFLIB_DEBUG 6317 /* use only 1 qset in debug mode */ 6318 queuemsgs = min(msgs - admincnt, 1); 6319 #else 6320 queuemsgs = msgs - admincnt; 6321 #endif 6322 #ifdef RSS 6323 queues = imin(queuemsgs, rss_getnumbuckets()); 6324 #else 6325 queues = queuemsgs; 6326 #endif 6327 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6328 if (bootverbose) 6329 device_printf(dev, 6330 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6331 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6332 #ifdef RSS 6333 /* If we're doing RSS, clamp at the number of RSS buckets */ 6334 if (queues > rss_getnumbuckets()) 6335 queues = rss_getnumbuckets(); 6336 #endif 6337 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6338 rx_queues = iflib_num_rx_queues; 6339 else 6340 rx_queues = queues; 6341 6342 if (rx_queues > scctx->isc_nrxqsets) 6343 rx_queues = scctx->isc_nrxqsets; 6344 6345 /* 6346 * We want this to be all logical CPUs by default 6347 */ 6348 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6349 tx_queues = iflib_num_tx_queues; 6350 else 6351 tx_queues = mp_ncpus; 6352 6353 if (tx_queues > scctx->isc_ntxqsets) 6354 tx_queues = scctx->isc_ntxqsets; 6355 6356 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6357 #ifdef INVARIANTS 6358 if (tx_queues != rx_queues) 6359 device_printf(dev, 6360 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6361 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6362 #endif 6363 tx_queues = min(rx_queues, tx_queues); 6364 rx_queues = min(rx_queues, tx_queues); 6365 } 6366 6367 vectors = rx_queues + admincnt; 6368 if (msgs < vectors) { 6369 device_printf(dev, 6370 "insufficient number of MSI-X vectors " 6371 "(supported %d, need %d)\n", msgs, vectors); 6372 goto msi; 6373 } 6374 6375 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6376 tx_queues); 6377 msgs = vectors; 6378 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6379 if (vectors != msgs) { 6380 device_printf(dev, 6381 "Unable to allocate sufficient MSI-X vectors " 6382 "(got %d, need %d)\n", vectors, msgs); 6383 pci_release_msi(dev); 6384 if (bar != -1) { 6385 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6386 ctx->ifc_msix_mem); 6387 ctx->ifc_msix_mem = NULL; 6388 } 6389 goto msi; 6390 } 6391 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6392 vectors); 6393 scctx->isc_vectors = vectors; 6394 scctx->isc_nrxqsets = rx_queues; 6395 scctx->isc_ntxqsets = tx_queues; 6396 scctx->isc_intr = IFLIB_INTR_MSIX; 6397 6398 return (vectors); 6399 } else { 6400 device_printf(dev, 6401 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6402 err); 6403 if (bar != -1) { 6404 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6405 ctx->ifc_msix_mem); 6406 ctx->ifc_msix_mem = NULL; 6407 } 6408 } 6409 6410 msi: 6411 vectors = pci_msi_count(dev); 6412 scctx->isc_nrxqsets = 1; 6413 scctx->isc_ntxqsets = 1; 6414 scctx->isc_vectors = vectors; 6415 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6416 device_printf(dev,"Using an MSI interrupt\n"); 6417 scctx->isc_intr = IFLIB_INTR_MSI; 6418 } else { 6419 scctx->isc_vectors = 1; 6420 device_printf(dev,"Using a Legacy interrupt\n"); 6421 scctx->isc_intr = IFLIB_INTR_LEGACY; 6422 } 6423 6424 return (vectors); 6425 } 6426 6427 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6428 6429 static int 6430 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6431 { 6432 int rc; 6433 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6434 struct sbuf *sb; 6435 const char *ring_state = "UNKNOWN"; 6436 6437 /* XXX needed ? */ 6438 rc = sysctl_wire_old_buffer(req, 0); 6439 MPASS(rc == 0); 6440 if (rc != 0) 6441 return (rc); 6442 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6443 MPASS(sb != NULL); 6444 if (sb == NULL) 6445 return (ENOMEM); 6446 if (state[3] <= 3) 6447 ring_state = ring_states[state[3]]; 6448 6449 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6450 state[0], state[1], state[2], ring_state); 6451 rc = sbuf_finish(sb); 6452 sbuf_delete(sb); 6453 return(rc); 6454 } 6455 6456 enum iflib_ndesc_handler { 6457 IFLIB_NTXD_HANDLER, 6458 IFLIB_NRXD_HANDLER, 6459 }; 6460 6461 static int 6462 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6463 { 6464 if_ctx_t ctx = (void *)arg1; 6465 enum iflib_ndesc_handler type = arg2; 6466 char buf[256] = {0}; 6467 qidx_t *ndesc; 6468 char *p, *next; 6469 int nqs, rc, i; 6470 6471 nqs = 8; 6472 switch(type) { 6473 case IFLIB_NTXD_HANDLER: 6474 ndesc = ctx->ifc_sysctl_ntxds; 6475 if (ctx->ifc_sctx) 6476 nqs = ctx->ifc_sctx->isc_ntxqs; 6477 break; 6478 case IFLIB_NRXD_HANDLER: 6479 ndesc = ctx->ifc_sysctl_nrxds; 6480 if (ctx->ifc_sctx) 6481 nqs = ctx->ifc_sctx->isc_nrxqs; 6482 break; 6483 default: 6484 printf("%s: unhandled type\n", __func__); 6485 return (EINVAL); 6486 } 6487 if (nqs == 0) 6488 nqs = 8; 6489 6490 for (i=0; i<8; i++) { 6491 if (i >= nqs) 6492 break; 6493 if (i) 6494 strcat(buf, ","); 6495 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6496 } 6497 6498 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6499 if (rc || req->newptr == NULL) 6500 return rc; 6501 6502 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6503 i++, p = strsep(&next, " ,")) { 6504 ndesc[i] = strtoul(p, NULL, 10); 6505 } 6506 6507 return(rc); 6508 } 6509 6510 #define NAME_BUFLEN 32 6511 static void 6512 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6513 { 6514 device_t dev = iflib_get_dev(ctx); 6515 struct sysctl_oid_list *child, *oid_list; 6516 struct sysctl_ctx_list *ctx_list; 6517 struct sysctl_oid *node; 6518 6519 ctx_list = device_get_sysctl_ctx(dev); 6520 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6521 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6522 CTLFLAG_RD, NULL, "IFLIB fields"); 6523 oid_list = SYSCTL_CHILDREN(node); 6524 6525 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6526 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6527 "driver version"); 6528 6529 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6530 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6531 "# of txqs to use, 0 => use default #"); 6532 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6533 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6534 "# of rxqs to use, 0 => use default #"); 6535 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6536 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6537 "permit #txq != #rxq"); 6538 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6539 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6540 "disable MSI-X (default 0)"); 6541 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6542 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6543 "set the RX budget"); 6544 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6545 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6546 "cause TX to abdicate instead of running to completion"); 6547 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6548 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6549 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6550 "offset to start using cores at"); 6551 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6552 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6553 "use separate cores for TX and RX"); 6554 6555 /* XXX change for per-queue sizes */ 6556 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6557 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6558 mp_ndesc_handler, "A", 6559 "list of # of TX descriptors to use, 0 = use default #"); 6560 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6561 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6562 mp_ndesc_handler, "A", 6563 "list of # of RX descriptors to use, 0 = use default #"); 6564 } 6565 6566 static void 6567 iflib_add_device_sysctl_post(if_ctx_t ctx) 6568 { 6569 if_shared_ctx_t sctx = ctx->ifc_sctx; 6570 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6571 device_t dev = iflib_get_dev(ctx); 6572 struct sysctl_oid_list *child; 6573 struct sysctl_ctx_list *ctx_list; 6574 iflib_fl_t fl; 6575 iflib_txq_t txq; 6576 iflib_rxq_t rxq; 6577 int i, j; 6578 char namebuf[NAME_BUFLEN]; 6579 char *qfmt; 6580 struct sysctl_oid *queue_node, *fl_node, *node; 6581 struct sysctl_oid_list *queue_list, *fl_list; 6582 ctx_list = device_get_sysctl_ctx(dev); 6583 6584 node = ctx->ifc_sysctl_node; 6585 child = SYSCTL_CHILDREN(node); 6586 6587 if (scctx->isc_ntxqsets > 100) 6588 qfmt = "txq%03d"; 6589 else if (scctx->isc_ntxqsets > 10) 6590 qfmt = "txq%02d"; 6591 else 6592 qfmt = "txq%d"; 6593 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6594 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6595 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6596 CTLFLAG_RD, NULL, "Queue Name"); 6597 queue_list = SYSCTL_CHILDREN(queue_node); 6598 #if MEMORY_LOGGING 6599 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6600 CTLFLAG_RD, 6601 &txq->ift_dequeued, "total mbufs freed"); 6602 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6603 CTLFLAG_RD, 6604 &txq->ift_enqueued, "total mbufs enqueued"); 6605 #endif 6606 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6607 CTLFLAG_RD, 6608 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6609 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6610 CTLFLAG_RD, 6611 &txq->ift_pullups, "# of times m_pullup was called"); 6612 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6613 CTLFLAG_RD, 6614 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6615 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6616 CTLFLAG_RD, 6617 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6618 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6619 CTLFLAG_RD, 6620 &txq->ift_map_failed, "# of times DMA map failed"); 6621 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6622 CTLFLAG_RD, 6623 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6624 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6625 CTLFLAG_RD, 6626 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6627 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6628 CTLFLAG_RD, 6629 &txq->ift_pidx, 1, "Producer Index"); 6630 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6631 CTLFLAG_RD, 6632 &txq->ift_cidx, 1, "Consumer Index"); 6633 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6634 CTLFLAG_RD, 6635 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6636 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6637 CTLFLAG_RD, 6638 &txq->ift_in_use, 1, "descriptors in use"); 6639 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6640 CTLFLAG_RD, 6641 &txq->ift_processed, "descriptors procesed for clean"); 6642 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6643 CTLFLAG_RD, 6644 &txq->ift_cleaned, "total cleaned"); 6645 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6646 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6647 0, mp_ring_state_handler, "A", "soft ring state"); 6648 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6649 CTLFLAG_RD, &txq->ift_br->enqueues, 6650 "# of enqueues to the mp_ring for this queue"); 6651 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6652 CTLFLAG_RD, &txq->ift_br->drops, 6653 "# of drops in the mp_ring for this queue"); 6654 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6655 CTLFLAG_RD, &txq->ift_br->starts, 6656 "# of normal consumer starts in the mp_ring for this queue"); 6657 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6658 CTLFLAG_RD, &txq->ift_br->stalls, 6659 "# of consumer stalls in the mp_ring for this queue"); 6660 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6661 CTLFLAG_RD, &txq->ift_br->restarts, 6662 "# of consumer restarts in the mp_ring for this queue"); 6663 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6664 CTLFLAG_RD, &txq->ift_br->abdications, 6665 "# of consumer abdications in the mp_ring for this queue"); 6666 } 6667 6668 if (scctx->isc_nrxqsets > 100) 6669 qfmt = "rxq%03d"; 6670 else if (scctx->isc_nrxqsets > 10) 6671 qfmt = "rxq%02d"; 6672 else 6673 qfmt = "rxq%d"; 6674 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6675 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6676 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6677 CTLFLAG_RD, NULL, "Queue Name"); 6678 queue_list = SYSCTL_CHILDREN(queue_node); 6679 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6680 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6681 CTLFLAG_RD, 6682 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6683 } 6684 6685 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6686 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6687 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6688 CTLFLAG_RD, NULL, "freelist Name"); 6689 fl_list = SYSCTL_CHILDREN(fl_node); 6690 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6691 CTLFLAG_RD, 6692 &fl->ifl_pidx, 1, "Producer Index"); 6693 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6694 CTLFLAG_RD, 6695 &fl->ifl_cidx, 1, "Consumer Index"); 6696 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6697 CTLFLAG_RD, 6698 &fl->ifl_credits, 1, "credits available"); 6699 #if MEMORY_LOGGING 6700 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6701 CTLFLAG_RD, 6702 &fl->ifl_m_enqueued, "mbufs allocated"); 6703 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6704 CTLFLAG_RD, 6705 &fl->ifl_m_dequeued, "mbufs freed"); 6706 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6707 CTLFLAG_RD, 6708 &fl->ifl_cl_enqueued, "clusters allocated"); 6709 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6710 CTLFLAG_RD, 6711 &fl->ifl_cl_dequeued, "clusters freed"); 6712 #endif 6713 6714 } 6715 } 6716 6717 } 6718 6719 void 6720 iflib_request_reset(if_ctx_t ctx) 6721 { 6722 6723 STATE_LOCK(ctx); 6724 ctx->ifc_flags |= IFC_DO_RESET; 6725 STATE_UNLOCK(ctx); 6726 } 6727 6728 #ifndef __NO_STRICT_ALIGNMENT 6729 static struct mbuf * 6730 iflib_fixup_rx(struct mbuf *m) 6731 { 6732 struct mbuf *n; 6733 6734 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6735 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6736 m->m_data += ETHER_HDR_LEN; 6737 n = m; 6738 } else { 6739 MGETHDR(n, M_NOWAIT, MT_DATA); 6740 if (n == NULL) { 6741 m_freem(m); 6742 return (NULL); 6743 } 6744 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6745 m->m_data += ETHER_HDR_LEN; 6746 m->m_len -= ETHER_HDR_LEN; 6747 n->m_len = ETHER_HDR_LEN; 6748 M_MOVE_PKTHDR(n, m); 6749 n->m_next = m; 6750 } 6751 return (n); 6752 } 6753 #endif 6754 6755 #ifdef DEBUGNET 6756 static void 6757 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6758 { 6759 if_ctx_t ctx; 6760 6761 ctx = if_getsoftc(ifp); 6762 CTX_LOCK(ctx); 6763 *nrxr = NRXQSETS(ctx); 6764 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6765 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6766 CTX_UNLOCK(ctx); 6767 } 6768 6769 static void 6770 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 6771 { 6772 if_ctx_t ctx; 6773 if_softc_ctx_t scctx; 6774 iflib_fl_t fl; 6775 iflib_rxq_t rxq; 6776 int i, j; 6777 6778 ctx = if_getsoftc(ifp); 6779 scctx = &ctx->ifc_softc_ctx; 6780 6781 switch (event) { 6782 case DEBUGNET_START: 6783 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6784 rxq = &ctx->ifc_rxqs[i]; 6785 for (j = 0; j < rxq->ifr_nfl; j++) { 6786 fl = rxq->ifr_fl; 6787 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6788 } 6789 } 6790 iflib_no_tx_batch = 1; 6791 break; 6792 default: 6793 break; 6794 } 6795 } 6796 6797 static int 6798 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 6799 { 6800 if_ctx_t ctx; 6801 iflib_txq_t txq; 6802 int error; 6803 6804 ctx = if_getsoftc(ifp); 6805 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6806 IFF_DRV_RUNNING) 6807 return (EBUSY); 6808 6809 txq = &ctx->ifc_txqs[0]; 6810 error = iflib_encap(txq, &m); 6811 if (error == 0) 6812 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6813 return (error); 6814 } 6815 6816 static int 6817 iflib_debugnet_poll(if_t ifp, int count) 6818 { 6819 struct epoch_tracker et; 6820 if_ctx_t ctx; 6821 if_softc_ctx_t scctx; 6822 iflib_txq_t txq; 6823 int i; 6824 6825 ctx = if_getsoftc(ifp); 6826 scctx = &ctx->ifc_softc_ctx; 6827 6828 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6829 IFF_DRV_RUNNING) 6830 return (EBUSY); 6831 6832 txq = &ctx->ifc_txqs[0]; 6833 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6834 6835 NET_EPOCH_ENTER(et); 6836 for (i = 0; i < scctx->isc_nrxqsets; i++) 6837 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6838 NET_EPOCH_EXIT(et); 6839 return (0); 6840 } 6841 #endif /* DEBUGNET */ 6842