1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 120 /* 121 * File organization: 122 * - private structures 123 * - iflib private utility functions 124 * - ifnet functions 125 * - vlan registry and other exported functions 126 * - iflib public core functions 127 * 128 * 129 */ 130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 131 132 struct iflib_txq; 133 typedef struct iflib_txq *iflib_txq_t; 134 struct iflib_rxq; 135 typedef struct iflib_rxq *iflib_rxq_t; 136 struct iflib_fl; 137 typedef struct iflib_fl *iflib_fl_t; 138 139 struct iflib_ctx; 140 141 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 142 static void iflib_timer(void *arg); 143 144 typedef struct iflib_filter_info { 145 driver_filter_t *ifi_filter; 146 void *ifi_filter_arg; 147 struct grouptask *ifi_task; 148 void *ifi_ctx; 149 } *iflib_filter_info_t; 150 151 struct iflib_ctx { 152 KOBJ_FIELDS; 153 /* 154 * Pointer to hardware driver's softc 155 */ 156 void *ifc_softc; 157 device_t ifc_dev; 158 if_t ifc_ifp; 159 160 cpuset_t ifc_cpus; 161 if_shared_ctx_t ifc_sctx; 162 struct if_softc_ctx ifc_softc_ctx; 163 164 struct sx ifc_ctx_sx; 165 struct mtx ifc_state_mtx; 166 167 iflib_txq_t ifc_txqs; 168 iflib_rxq_t ifc_rxqs; 169 uint32_t ifc_if_flags; 170 uint32_t ifc_flags; 171 uint32_t ifc_max_fl_buf_size; 172 uint32_t ifc_rx_mbuf_sz; 173 174 int ifc_link_state; 175 int ifc_watchdog_events; 176 struct cdev *ifc_led_dev; 177 struct resource *ifc_msix_mem; 178 179 struct if_irq ifc_legacy_irq; 180 struct grouptask ifc_admin_task; 181 struct grouptask ifc_vflr_task; 182 struct iflib_filter_info ifc_filter_info; 183 struct ifmedia ifc_media; 184 struct ifmedia *ifc_mediap; 185 186 struct sysctl_oid *ifc_sysctl_node; 187 uint16_t ifc_sysctl_ntxqs; 188 uint16_t ifc_sysctl_nrxqs; 189 uint16_t ifc_sysctl_qs_eq_override; 190 uint16_t ifc_sysctl_rx_budget; 191 uint16_t ifc_sysctl_tx_abdicate; 192 uint16_t ifc_sysctl_core_offset; 193 #define CORE_OFFSET_UNSPECIFIED 0xffff 194 uint8_t ifc_sysctl_separate_txrx; 195 196 qidx_t ifc_sysctl_ntxds[8]; 197 qidx_t ifc_sysctl_nrxds[8]; 198 struct if_txrx ifc_txrx; 199 #define isc_txd_encap ifc_txrx.ift_txd_encap 200 #define isc_txd_flush ifc_txrx.ift_txd_flush 201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 202 #define isc_rxd_available ifc_txrx.ift_rxd_available 203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 209 eventhandler_tag ifc_vlan_attach_event; 210 eventhandler_tag ifc_vlan_detach_event; 211 struct ether_addr ifc_mac; 212 }; 213 214 void * 215 iflib_get_softc(if_ctx_t ctx) 216 { 217 218 return (ctx->ifc_softc); 219 } 220 221 device_t 222 iflib_get_dev(if_ctx_t ctx) 223 { 224 225 return (ctx->ifc_dev); 226 } 227 228 if_t 229 iflib_get_ifp(if_ctx_t ctx) 230 { 231 232 return (ctx->ifc_ifp); 233 } 234 235 struct ifmedia * 236 iflib_get_media(if_ctx_t ctx) 237 { 238 239 return (ctx->ifc_mediap); 240 } 241 242 uint32_t 243 iflib_get_flags(if_ctx_t ctx) 244 { 245 return (ctx->ifc_flags); 246 } 247 248 void 249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 250 { 251 252 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 253 } 254 255 if_softc_ctx_t 256 iflib_get_softc_ctx(if_ctx_t ctx) 257 { 258 259 return (&ctx->ifc_softc_ctx); 260 } 261 262 if_shared_ctx_t 263 iflib_get_sctx(if_ctx_t ctx) 264 { 265 266 return (ctx->ifc_sctx); 267 } 268 269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 272 273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 275 276 typedef struct iflib_sw_rx_desc_array { 277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 278 struct mbuf **ifsd_m; /* pkthdr mbufs */ 279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 281 } iflib_rxsd_array_t; 282 283 typedef struct iflib_sw_tx_desc_array { 284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 286 struct mbuf **ifsd_m; /* pkthdr mbufs */ 287 } if_txsd_vec_t; 288 289 /* magic number that should be high enough for any hardware */ 290 #define IFLIB_MAX_TX_SEGS 128 291 #define IFLIB_RX_COPY_THRESH 128 292 #define IFLIB_MAX_RX_REFRESH 32 293 /* The minimum descriptors per second before we start coalescing */ 294 #define IFLIB_MIN_DESC_SEC 16384 295 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 296 #define IFLIB_QUEUE_IDLE 0 297 #define IFLIB_QUEUE_HUNG 1 298 #define IFLIB_QUEUE_WORKING 2 299 /* maximum number of txqs that can share an rx interrupt */ 300 #define IFLIB_MAX_TX_SHARED_INTR 4 301 302 /* this should really scale with ring size - this is a fairly arbitrary value */ 303 #define TX_BATCH_SIZE 32 304 305 #define IFLIB_RESTART_BUDGET 8 306 307 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 308 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 309 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 310 311 struct iflib_txq { 312 qidx_t ift_in_use; 313 qidx_t ift_cidx; 314 qidx_t ift_cidx_processed; 315 qidx_t ift_pidx; 316 uint8_t ift_gen; 317 uint8_t ift_br_offset; 318 uint16_t ift_npending; 319 uint16_t ift_db_pending; 320 uint16_t ift_rs_pending; 321 /* implicit pad */ 322 uint8_t ift_txd_size[8]; 323 uint64_t ift_processed; 324 uint64_t ift_cleaned; 325 uint64_t ift_cleaned_prev; 326 #if MEMORY_LOGGING 327 uint64_t ift_enqueued; 328 uint64_t ift_dequeued; 329 #endif 330 uint64_t ift_no_tx_dma_setup; 331 uint64_t ift_no_desc_avail; 332 uint64_t ift_mbuf_defrag_failed; 333 uint64_t ift_mbuf_defrag; 334 uint64_t ift_map_failed; 335 uint64_t ift_txd_encap_efbig; 336 uint64_t ift_pullups; 337 uint64_t ift_last_timer_tick; 338 339 struct mtx ift_mtx; 340 struct mtx ift_db_mtx; 341 342 /* constant values */ 343 if_ctx_t ift_ctx; 344 struct ifmp_ring *ift_br; 345 struct grouptask ift_task; 346 qidx_t ift_size; 347 uint16_t ift_id; 348 struct callout ift_timer; 349 350 if_txsd_vec_t ift_sds; 351 uint8_t ift_qstatus; 352 uint8_t ift_closed; 353 uint8_t ift_update_freq; 354 struct iflib_filter_info ift_filter_info; 355 bus_dma_tag_t ift_buf_tag; 356 bus_dma_tag_t ift_tso_buf_tag; 357 iflib_dma_info_t ift_ifdi; 358 #define MTX_NAME_LEN 16 359 char ift_mtx_name[MTX_NAME_LEN]; 360 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 361 #ifdef IFLIB_DIAGNOSTICS 362 uint64_t ift_cpu_exec_count[256]; 363 #endif 364 } __aligned(CACHE_LINE_SIZE); 365 366 struct iflib_fl { 367 qidx_t ifl_cidx; 368 qidx_t ifl_pidx; 369 qidx_t ifl_credits; 370 uint8_t ifl_gen; 371 uint8_t ifl_rxd_size; 372 #if MEMORY_LOGGING 373 uint64_t ifl_m_enqueued; 374 uint64_t ifl_m_dequeued; 375 uint64_t ifl_cl_enqueued; 376 uint64_t ifl_cl_dequeued; 377 #endif 378 /* implicit pad */ 379 bitstr_t *ifl_rx_bitmap; 380 qidx_t ifl_fragidx; 381 /* constant */ 382 qidx_t ifl_size; 383 uint16_t ifl_buf_size; 384 uint16_t ifl_cltype; 385 uma_zone_t ifl_zone; 386 iflib_rxsd_array_t ifl_sds; 387 iflib_rxq_t ifl_rxq; 388 uint8_t ifl_id; 389 bus_dma_tag_t ifl_buf_tag; 390 iflib_dma_info_t ifl_ifdi; 391 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 392 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 393 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 394 } __aligned(CACHE_LINE_SIZE); 395 396 static inline qidx_t 397 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 398 { 399 qidx_t used; 400 401 if (pidx > cidx) 402 used = pidx - cidx; 403 else if (pidx < cidx) 404 used = size - cidx + pidx; 405 else if (gen == 0 && pidx == cidx) 406 used = 0; 407 else if (gen == 1 && pidx == cidx) 408 used = size; 409 else 410 panic("bad state"); 411 412 return (used); 413 } 414 415 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 416 417 #define IDXDIFF(head, tail, wrap) \ 418 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 419 420 struct iflib_rxq { 421 if_ctx_t ifr_ctx; 422 iflib_fl_t ifr_fl; 423 uint64_t ifr_rx_irq; 424 struct pfil_head *pfil; 425 /* 426 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 427 * the command queue consumer index. Otherwise it's unused. 428 */ 429 qidx_t ifr_cq_cidx; 430 uint16_t ifr_id; 431 uint8_t ifr_nfl; 432 uint8_t ifr_ntxqirq; 433 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 434 uint8_t ifr_fl_offset; 435 struct lro_ctrl ifr_lc; 436 struct grouptask ifr_task; 437 struct iflib_filter_info ifr_filter_info; 438 iflib_dma_info_t ifr_ifdi; 439 440 /* dynamically allocate if any drivers need a value substantially larger than this */ 441 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 442 #ifdef IFLIB_DIAGNOSTICS 443 uint64_t ifr_cpu_exec_count[256]; 444 #endif 445 } __aligned(CACHE_LINE_SIZE); 446 447 typedef struct if_rxsd { 448 caddr_t *ifsd_cl; 449 iflib_fl_t ifsd_fl; 450 qidx_t ifsd_cidx; 451 } *if_rxsd_t; 452 453 /* multiple of word size */ 454 #ifdef __LP64__ 455 #define PKT_INFO_SIZE 6 456 #define RXD_INFO_SIZE 5 457 #define PKT_TYPE uint64_t 458 #else 459 #define PKT_INFO_SIZE 11 460 #define RXD_INFO_SIZE 8 461 #define PKT_TYPE uint32_t 462 #endif 463 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 464 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 465 466 typedef struct if_pkt_info_pad { 467 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 468 } *if_pkt_info_pad_t; 469 typedef struct if_rxd_info_pad { 470 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 471 } *if_rxd_info_pad_t; 472 473 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 474 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 475 476 477 static inline void 478 pkt_info_zero(if_pkt_info_t pi) 479 { 480 if_pkt_info_pad_t pi_pad; 481 482 pi_pad = (if_pkt_info_pad_t)pi; 483 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 484 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 485 #ifndef __LP64__ 486 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 487 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 488 #endif 489 } 490 491 static device_method_t iflib_pseudo_methods[] = { 492 DEVMETHOD(device_attach, noop_attach), 493 DEVMETHOD(device_detach, iflib_pseudo_detach), 494 DEVMETHOD_END 495 }; 496 497 driver_t iflib_pseudodriver = { 498 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 499 }; 500 501 static inline void 502 rxd_info_zero(if_rxd_info_t ri) 503 { 504 if_rxd_info_pad_t ri_pad; 505 int i; 506 507 ri_pad = (if_rxd_info_pad_t)ri; 508 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 509 ri_pad->rxd_val[i] = 0; 510 ri_pad->rxd_val[i+1] = 0; 511 ri_pad->rxd_val[i+2] = 0; 512 ri_pad->rxd_val[i+3] = 0; 513 } 514 #ifdef __LP64__ 515 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 516 #endif 517 } 518 519 /* 520 * Only allow a single packet to take up most 1/nth of the tx ring 521 */ 522 #define MAX_SINGLE_PACKET_FRACTION 12 523 #define IF_BAD_DMA (bus_addr_t)-1 524 525 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 526 527 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 528 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 529 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 530 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 531 532 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 533 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 534 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 535 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 536 537 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 538 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 539 540 void 541 iflib_set_detach(if_ctx_t ctx) 542 { 543 STATE_LOCK(ctx); 544 ctx->ifc_flags |= IFC_IN_DETACH; 545 STATE_UNLOCK(ctx); 546 } 547 548 /* Our boot-time initialization hook */ 549 static int iflib_module_event_handler(module_t, int, void *); 550 551 static moduledata_t iflib_moduledata = { 552 "iflib", 553 iflib_module_event_handler, 554 NULL 555 }; 556 557 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 558 MODULE_VERSION(iflib, 1); 559 560 MODULE_DEPEND(iflib, pci, 1, 1, 1); 561 MODULE_DEPEND(iflib, ether, 1, 1, 1); 562 563 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 564 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 565 566 #ifndef IFLIB_DEBUG_COUNTERS 567 #ifdef INVARIANTS 568 #define IFLIB_DEBUG_COUNTERS 1 569 #else 570 #define IFLIB_DEBUG_COUNTERS 0 571 #endif /* !INVARIANTS */ 572 #endif 573 574 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 575 "iflib driver parameters"); 576 577 /* 578 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 579 */ 580 static int iflib_min_tx_latency = 0; 581 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 582 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 583 static int iflib_no_tx_batch = 0; 584 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 585 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 586 587 588 #if IFLIB_DEBUG_COUNTERS 589 590 static int iflib_tx_seen; 591 static int iflib_tx_sent; 592 static int iflib_tx_encap; 593 static int iflib_rx_allocs; 594 static int iflib_fl_refills; 595 static int iflib_fl_refills_large; 596 static int iflib_tx_frees; 597 598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 599 &iflib_tx_seen, 0, "# TX mbufs seen"); 600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 601 &iflib_tx_sent, 0, "# TX mbufs sent"); 602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 603 &iflib_tx_encap, 0, "# TX mbufs encapped"); 604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 605 &iflib_tx_frees, 0, "# TX frees"); 606 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 607 &iflib_rx_allocs, 0, "# RX allocations"); 608 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 609 &iflib_fl_refills, 0, "# refills"); 610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 611 &iflib_fl_refills_large, 0, "# large refills"); 612 613 614 static int iflib_txq_drain_flushing; 615 static int iflib_txq_drain_oactive; 616 static int iflib_txq_drain_notready; 617 618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 619 &iflib_txq_drain_flushing, 0, "# drain flushes"); 620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 621 &iflib_txq_drain_oactive, 0, "# drain oactives"); 622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 623 &iflib_txq_drain_notready, 0, "# drain notready"); 624 625 626 static int iflib_encap_load_mbuf_fail; 627 static int iflib_encap_pad_mbuf_fail; 628 static int iflib_encap_txq_avail_fail; 629 static int iflib_encap_txd_encap_fail; 630 631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 632 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 634 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 636 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 638 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 639 640 static int iflib_task_fn_rxs; 641 static int iflib_rx_intr_enables; 642 static int iflib_fast_intrs; 643 static int iflib_rx_unavail; 644 static int iflib_rx_ctx_inactive; 645 static int iflib_rx_if_input; 646 static int iflib_rxd_flush; 647 648 static int iflib_verbose_debug; 649 650 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 651 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 652 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 653 &iflib_rx_intr_enables, 0, "# RX intr enables"); 654 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 655 &iflib_fast_intrs, 0, "# fast_intr calls"); 656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 657 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 659 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 661 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 663 &iflib_rxd_flush, 0, "# times rxd_flush called"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 665 &iflib_verbose_debug, 0, "enable verbose debugging"); 666 667 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 668 static void 669 iflib_debug_reset(void) 670 { 671 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 672 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 673 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 674 iflib_txq_drain_notready = 675 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 676 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 677 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 678 iflib_rx_unavail = 679 iflib_rx_ctx_inactive = iflib_rx_if_input = 680 iflib_rxd_flush = 0; 681 } 682 683 #else 684 #define DBG_COUNTER_INC(name) 685 static void iflib_debug_reset(void) {} 686 #endif 687 688 #define IFLIB_DEBUG 0 689 690 static void iflib_tx_structures_free(if_ctx_t ctx); 691 static void iflib_rx_structures_free(if_ctx_t ctx); 692 static int iflib_queues_alloc(if_ctx_t ctx); 693 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 694 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 695 static int iflib_qset_structures_setup(if_ctx_t ctx); 696 static int iflib_msix_init(if_ctx_t ctx); 697 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 698 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 699 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 700 #ifdef ALTQ 701 static void iflib_altq_if_start(if_t ifp); 702 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 703 #endif 704 static int iflib_register(if_ctx_t); 705 static void iflib_deregister(if_ctx_t); 706 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 707 static void iflib_init_locked(if_ctx_t ctx); 708 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 709 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 710 static void iflib_ifmp_purge(iflib_txq_t txq); 711 static void _iflib_pre_assert(if_softc_ctx_t scctx); 712 static void iflib_if_init_locked(if_ctx_t ctx); 713 static void iflib_free_intr_mem(if_ctx_t ctx); 714 #ifndef __NO_STRICT_ALIGNMENT 715 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 716 #endif 717 718 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 719 SLIST_HEAD_INITIALIZER(cpu_offsets); 720 struct cpu_offset { 721 SLIST_ENTRY(cpu_offset) entries; 722 cpuset_t set; 723 unsigned int refcount; 724 uint16_t offset; 725 }; 726 static struct mtx cpu_offset_mtx; 727 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 728 MTX_DEF); 729 730 DEBUGNET_DEFINE(iflib); 731 732 #ifdef DEV_NETMAP 733 #include <sys/selinfo.h> 734 #include <net/netmap.h> 735 #include <dev/netmap/netmap_kern.h> 736 737 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 738 739 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 740 741 /* 742 * device-specific sysctl variables: 743 * 744 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 745 * During regular operations the CRC is stripped, but on some 746 * hardware reception of frames not multiple of 64 is slower, 747 * so using crcstrip=0 helps in benchmarks. 748 * 749 * iflib_rx_miss, iflib_rx_miss_bufs: 750 * count packets that might be missed due to lost interrupts. 751 */ 752 SYSCTL_DECL(_dev_netmap); 753 /* 754 * The xl driver by default strips CRCs and we do not override it. 755 */ 756 757 int iflib_crcstrip = 1; 758 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 759 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 760 761 int iflib_rx_miss, iflib_rx_miss_bufs; 762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 763 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 764 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 765 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 766 767 /* 768 * Register/unregister. We are already under netmap lock. 769 * Only called on the first register or the last unregister. 770 */ 771 static int 772 iflib_netmap_register(struct netmap_adapter *na, int onoff) 773 { 774 if_t ifp = na->ifp; 775 if_ctx_t ctx = ifp->if_softc; 776 int status; 777 778 CTX_LOCK(ctx); 779 IFDI_INTR_DISABLE(ctx); 780 781 /* Tell the stack that the interface is no longer active */ 782 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 783 784 if (!CTX_IS_VF(ctx)) 785 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 786 787 /* enable or disable flags and callbacks in na and ifp */ 788 if (onoff) { 789 nm_set_native_flags(na); 790 } else { 791 nm_clear_native_flags(na); 792 } 793 iflib_stop(ctx); 794 iflib_init_locked(ctx); 795 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 796 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 797 if (status) 798 nm_clear_native_flags(na); 799 CTX_UNLOCK(ctx); 800 return (status); 801 } 802 803 static int 804 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 805 { 806 struct netmap_adapter *na = kring->na; 807 u_int const lim = kring->nkr_num_slots - 1; 808 u_int head = kring->rhead; 809 struct netmap_ring *ring = kring->ring; 810 bus_dmamap_t *map; 811 struct if_rxd_update iru; 812 if_ctx_t ctx = rxq->ifr_ctx; 813 iflib_fl_t fl = &rxq->ifr_fl[0]; 814 uint32_t refill_pidx, nic_i; 815 #if IFLIB_DEBUG_COUNTERS 816 int rf_count = 0; 817 #endif 818 819 if (nm_i == head && __predict_true(!init)) 820 return 0; 821 iru_init(&iru, rxq, 0 /* flid */); 822 map = fl->ifl_sds.ifsd_map; 823 refill_pidx = netmap_idx_k2n(kring, nm_i); 824 /* 825 * IMPORTANT: we must leave one free slot in the ring, 826 * so move head back by one unit 827 */ 828 head = nm_prev(head, lim); 829 nic_i = UINT_MAX; 830 DBG_COUNTER_INC(fl_refills); 831 while (nm_i != head) { 832 #if IFLIB_DEBUG_COUNTERS 833 if (++rf_count == 9) 834 DBG_COUNTER_INC(fl_refills_large); 835 #endif 836 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 837 struct netmap_slot *slot = &ring->slot[nm_i]; 838 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 839 uint32_t nic_i_dma = refill_pidx; 840 nic_i = netmap_idx_k2n(kring, nm_i); 841 842 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 843 844 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 845 return netmap_ring_reinit(kring); 846 847 fl->ifl_vm_addrs[tmp_pidx] = addr; 848 if (__predict_false(init)) { 849 netmap_load_map(na, fl->ifl_buf_tag, 850 map[nic_i], addr); 851 } else if (slot->flags & NS_BUF_CHANGED) { 852 /* buffer has changed, reload map */ 853 netmap_reload_map(na, fl->ifl_buf_tag, 854 map[nic_i], addr); 855 } 856 slot->flags &= ~NS_BUF_CHANGED; 857 858 nm_i = nm_next(nm_i, lim); 859 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 860 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 861 continue; 862 863 iru.iru_pidx = refill_pidx; 864 iru.iru_count = tmp_pidx+1; 865 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 866 refill_pidx = nic_i; 867 for (int n = 0; n < iru.iru_count; n++) { 868 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma], 869 BUS_DMASYNC_PREREAD); 870 /* XXX - change this to not use the netmap func*/ 871 nic_i_dma = nm_next(nic_i_dma, lim); 872 } 873 } 874 } 875 kring->nr_hwcur = head; 876 877 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 878 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 879 if (__predict_true(nic_i != UINT_MAX)) { 880 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 881 DBG_COUNTER_INC(rxd_flush); 882 } 883 return (0); 884 } 885 886 /* 887 * Reconcile kernel and user view of the transmit ring. 888 * 889 * All information is in the kring. 890 * Userspace wants to send packets up to the one before kring->rhead, 891 * kernel knows kring->nr_hwcur is the first unsent packet. 892 * 893 * Here we push packets out (as many as possible), and possibly 894 * reclaim buffers from previously completed transmission. 895 * 896 * The caller (netmap) guarantees that there is only one instance 897 * running at any time. Any interference with other driver 898 * methods should be handled by the individual drivers. 899 */ 900 static int 901 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 902 { 903 struct netmap_adapter *na = kring->na; 904 if_t ifp = na->ifp; 905 struct netmap_ring *ring = kring->ring; 906 u_int nm_i; /* index into the netmap kring */ 907 u_int nic_i; /* index into the NIC ring */ 908 u_int n; 909 u_int const lim = kring->nkr_num_slots - 1; 910 u_int const head = kring->rhead; 911 struct if_pkt_info pi; 912 913 /* 914 * interrupts on every tx packet are expensive so request 915 * them every half ring, or where NS_REPORT is set 916 */ 917 u_int report_frequency = kring->nkr_num_slots >> 1; 918 /* device-specific */ 919 if_ctx_t ctx = ifp->if_softc; 920 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 921 922 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 923 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 924 925 /* 926 * First part: process new packets to send. 927 * nm_i is the current index in the netmap kring, 928 * nic_i is the corresponding index in the NIC ring. 929 * 930 * If we have packets to send (nm_i != head) 931 * iterate over the netmap ring, fetch length and update 932 * the corresponding slot in the NIC ring. Some drivers also 933 * need to update the buffer's physical address in the NIC slot 934 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 935 * 936 * The netmap_reload_map() calls is especially expensive, 937 * even when (as in this case) the tag is 0, so do only 938 * when the buffer has actually changed. 939 * 940 * If possible do not set the report/intr bit on all slots, 941 * but only a few times per ring or when NS_REPORT is set. 942 * 943 * Finally, on 10G and faster drivers, it might be useful 944 * to prefetch the next slot and txr entry. 945 */ 946 947 nm_i = kring->nr_hwcur; 948 if (nm_i != head) { /* we have new packets to send */ 949 pkt_info_zero(&pi); 950 pi.ipi_segs = txq->ift_segs; 951 pi.ipi_qsidx = kring->ring_id; 952 nic_i = netmap_idx_k2n(kring, nm_i); 953 954 __builtin_prefetch(&ring->slot[nm_i]); 955 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 956 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 957 958 for (n = 0; nm_i != head; n++) { 959 struct netmap_slot *slot = &ring->slot[nm_i]; 960 u_int len = slot->len; 961 uint64_t paddr; 962 void *addr = PNMB(na, slot, &paddr); 963 int flags = (slot->flags & NS_REPORT || 964 nic_i == 0 || nic_i == report_frequency) ? 965 IPI_TX_INTR : 0; 966 967 /* device-specific */ 968 pi.ipi_len = len; 969 pi.ipi_segs[0].ds_addr = paddr; 970 pi.ipi_segs[0].ds_len = len; 971 pi.ipi_nsegs = 1; 972 pi.ipi_ndescs = 0; 973 pi.ipi_pidx = nic_i; 974 pi.ipi_flags = flags; 975 976 /* Fill the slot in the NIC ring. */ 977 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 978 DBG_COUNTER_INC(tx_encap); 979 980 /* prefetch for next round */ 981 __builtin_prefetch(&ring->slot[nm_i + 1]); 982 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 983 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 984 985 NM_CHECK_ADDR_LEN(na, addr, len); 986 987 if (slot->flags & NS_BUF_CHANGED) { 988 /* buffer has changed, reload map */ 989 netmap_reload_map(na, txq->ift_buf_tag, 990 txq->ift_sds.ifsd_map[nic_i], addr); 991 } 992 /* make sure changes to the buffer are synced */ 993 bus_dmamap_sync(txq->ift_buf_tag, 994 txq->ift_sds.ifsd_map[nic_i], 995 BUS_DMASYNC_PREWRITE); 996 997 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 998 nm_i = nm_next(nm_i, lim); 999 nic_i = nm_next(nic_i, lim); 1000 } 1001 kring->nr_hwcur = nm_i; 1002 1003 /* synchronize the NIC ring */ 1004 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1005 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1006 1007 /* (re)start the tx unit up to slot nic_i (excluded) */ 1008 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1009 } 1010 1011 /* 1012 * Second part: reclaim buffers for completed transmissions. 1013 * 1014 * If there are unclaimed buffers, attempt to reclaim them. 1015 * If none are reclaimed, and TX IRQs are not in use, do an initial 1016 * minimal delay, then trigger the tx handler which will spin in the 1017 * group task queue. 1018 */ 1019 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1020 if (iflib_tx_credits_update(ctx, txq)) { 1021 /* some tx completed, increment avail */ 1022 nic_i = txq->ift_cidx_processed; 1023 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1024 } 1025 } 1026 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1027 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1028 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1029 iflib_timer, txq, txq->ift_timer.c_cpu); 1030 } 1031 return (0); 1032 } 1033 1034 /* 1035 * Reconcile kernel and user view of the receive ring. 1036 * Same as for the txsync, this routine must be efficient. 1037 * The caller guarantees a single invocations, but races against 1038 * the rest of the driver should be handled here. 1039 * 1040 * On call, kring->rhead is the first packet that userspace wants 1041 * to keep, and kring->rcur is the wakeup point. 1042 * The kernel has previously reported packets up to kring->rtail. 1043 * 1044 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1045 * of whether or not we received an interrupt. 1046 */ 1047 static int 1048 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1049 { 1050 struct netmap_adapter *na = kring->na; 1051 struct netmap_ring *ring = kring->ring; 1052 if_t ifp = na->ifp; 1053 iflib_fl_t fl; 1054 uint32_t nm_i; /* index into the netmap ring */ 1055 uint32_t nic_i; /* index into the NIC ring */ 1056 u_int i, n; 1057 u_int const lim = kring->nkr_num_slots - 1; 1058 u_int const head = kring->rhead; 1059 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1060 struct if_rxd_info ri; 1061 1062 if_ctx_t ctx = ifp->if_softc; 1063 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1064 if (head > lim) 1065 return netmap_ring_reinit(kring); 1066 1067 /* 1068 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far. 1069 */ 1070 1071 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1072 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1073 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1074 } 1075 1076 /* 1077 * First part: import newly received packets. 1078 * 1079 * nm_i is the index of the next free slot in the netmap ring, 1080 * nic_i is the index of the next received packet in the NIC ring, 1081 * and they may differ in case if_init() has been called while 1082 * in netmap mode. For the receive ring we have 1083 * 1084 * nic_i = rxr->next_check; 1085 * nm_i = kring->nr_hwtail (previous) 1086 * and 1087 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1088 * 1089 * rxr->next_check is set to 0 on a ring reinit 1090 */ 1091 if (netmap_no_pendintr || force_update) { 1092 int crclen = iflib_crcstrip ? 0 : 4; 1093 int error, avail; 1094 1095 for (i = 0; i < rxq->ifr_nfl; i++) { 1096 fl = &rxq->ifr_fl[i]; 1097 nic_i = fl->ifl_cidx; 1098 nm_i = netmap_idx_n2k(kring, nic_i); 1099 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1100 rxq->ifr_id, nic_i, USHRT_MAX); 1101 for (n = 0; avail > 0; n++, avail--) { 1102 rxd_info_zero(&ri); 1103 ri.iri_frags = rxq->ifr_frags; 1104 ri.iri_qsidx = kring->ring_id; 1105 ri.iri_ifp = ctx->ifc_ifp; 1106 ri.iri_cidx = nic_i; 1107 1108 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1109 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1110 ring->slot[nm_i].flags = 0; 1111 bus_dmamap_sync(fl->ifl_buf_tag, 1112 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1113 nm_i = nm_next(nm_i, lim); 1114 nic_i = nm_next(nic_i, lim); 1115 } 1116 if (n) { /* update the state variables */ 1117 if (netmap_no_pendintr && !force_update) { 1118 /* diagnostics */ 1119 iflib_rx_miss ++; 1120 iflib_rx_miss_bufs += n; 1121 } 1122 fl->ifl_cidx = nic_i; 1123 kring->nr_hwtail = nm_i; 1124 } 1125 kring->nr_kflags &= ~NKR_PENDINTR; 1126 } 1127 } 1128 /* 1129 * Second part: skip past packets that userspace has released. 1130 * (kring->nr_hwcur to head excluded), 1131 * and make the buffers available for reception. 1132 * As usual nm_i is the index in the netmap ring, 1133 * nic_i is the index in the NIC ring, and 1134 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1135 */ 1136 /* XXX not sure how this will work with multiple free lists */ 1137 nm_i = kring->nr_hwcur; 1138 1139 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1140 } 1141 1142 static void 1143 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1144 { 1145 if_ctx_t ctx = na->ifp->if_softc; 1146 1147 CTX_LOCK(ctx); 1148 if (onoff) { 1149 IFDI_INTR_ENABLE(ctx); 1150 } else { 1151 IFDI_INTR_DISABLE(ctx); 1152 } 1153 CTX_UNLOCK(ctx); 1154 } 1155 1156 1157 static int 1158 iflib_netmap_attach(if_ctx_t ctx) 1159 { 1160 struct netmap_adapter na; 1161 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1162 1163 bzero(&na, sizeof(na)); 1164 1165 na.ifp = ctx->ifc_ifp; 1166 na.na_flags = NAF_BDG_MAYSLEEP; 1167 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1168 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1169 1170 na.num_tx_desc = scctx->isc_ntxd[0]; 1171 na.num_rx_desc = scctx->isc_nrxd[0]; 1172 na.nm_txsync = iflib_netmap_txsync; 1173 na.nm_rxsync = iflib_netmap_rxsync; 1174 na.nm_register = iflib_netmap_register; 1175 na.nm_intr = iflib_netmap_intr; 1176 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1177 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1178 return (netmap_attach(&na)); 1179 } 1180 1181 static void 1182 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1183 { 1184 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1185 struct netmap_slot *slot; 1186 1187 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1188 if (slot == NULL) 1189 return; 1190 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1191 1192 /* 1193 * In netmap mode, set the map for the packet buffer. 1194 * NOTE: Some drivers (not this one) also need to set 1195 * the physical buffer address in the NIC ring. 1196 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1197 * netmap slot index, si 1198 */ 1199 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1200 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1201 NMB(na, slot + si)); 1202 } 1203 } 1204 1205 static void 1206 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1207 { 1208 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1209 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1210 struct netmap_slot *slot; 1211 uint32_t nm_i; 1212 1213 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1214 if (slot == NULL) 1215 return; 1216 nm_i = netmap_idx_n2k(kring, 0); 1217 netmap_fl_refill(rxq, kring, nm_i, true); 1218 } 1219 1220 static void 1221 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on) 1222 { 1223 struct netmap_kring *kring; 1224 uint16_t txqid; 1225 1226 txqid = txq->ift_id; 1227 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1228 1229 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1230 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1231 BUS_DMASYNC_POSTREAD); 1232 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1233 netmap_tx_irq(ctx->ifc_ifp, txqid); 1234 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1235 if (hz < 2000) 1236 *reset_on = 1; 1237 else 1238 *reset_on = hz / 1000; 1239 } 1240 } 1241 } 1242 1243 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1244 1245 #else 1246 #define iflib_netmap_txq_init(ctx, txq) 1247 #define iflib_netmap_rxq_init(ctx, rxq) 1248 #define iflib_netmap_detach(ifp) 1249 1250 #define iflib_netmap_attach(ctx) (0) 1251 #define netmap_rx_irq(ifp, qid, budget) (0) 1252 #define netmap_tx_irq(ifp, qid) do {} while (0) 1253 #define iflib_netmap_timer_adjust(ctx, txq, reset_on) 1254 #endif 1255 1256 #if defined(__i386__) || defined(__amd64__) 1257 static __inline void 1258 prefetch(void *x) 1259 { 1260 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1261 } 1262 static __inline void 1263 prefetch2cachelines(void *x) 1264 { 1265 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1266 #if (CACHE_LINE_SIZE < 128) 1267 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1268 #endif 1269 } 1270 #else 1271 #define prefetch(x) 1272 #define prefetch2cachelines(x) 1273 #endif 1274 1275 static void 1276 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1277 { 1278 iflib_fl_t fl; 1279 1280 fl = &rxq->ifr_fl[flid]; 1281 iru->iru_paddrs = fl->ifl_bus_addrs; 1282 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1283 iru->iru_idxs = fl->ifl_rxd_idxs; 1284 iru->iru_qsidx = rxq->ifr_id; 1285 iru->iru_buf_size = fl->ifl_buf_size; 1286 iru->iru_flidx = fl->ifl_id; 1287 } 1288 1289 static void 1290 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1291 { 1292 if (err) 1293 return; 1294 *(bus_addr_t *) arg = segs[0].ds_addr; 1295 } 1296 1297 int 1298 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1299 { 1300 int err; 1301 device_t dev = ctx->ifc_dev; 1302 1303 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1304 align, 0, /* alignment, bounds */ 1305 BUS_SPACE_MAXADDR, /* lowaddr */ 1306 BUS_SPACE_MAXADDR, /* highaddr */ 1307 NULL, NULL, /* filter, filterarg */ 1308 size, /* maxsize */ 1309 1, /* nsegments */ 1310 size, /* maxsegsize */ 1311 BUS_DMA_ALLOCNOW, /* flags */ 1312 NULL, /* lockfunc */ 1313 NULL, /* lockarg */ 1314 &dma->idi_tag); 1315 if (err) { 1316 device_printf(dev, 1317 "%s: bus_dma_tag_create failed: %d\n", 1318 __func__, err); 1319 goto fail_0; 1320 } 1321 1322 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1323 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1324 if (err) { 1325 device_printf(dev, 1326 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1327 __func__, (uintmax_t)size, err); 1328 goto fail_1; 1329 } 1330 1331 dma->idi_paddr = IF_BAD_DMA; 1332 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1333 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1334 if (err || dma->idi_paddr == IF_BAD_DMA) { 1335 device_printf(dev, 1336 "%s: bus_dmamap_load failed: %d\n", 1337 __func__, err); 1338 goto fail_2; 1339 } 1340 1341 dma->idi_size = size; 1342 return (0); 1343 1344 fail_2: 1345 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1346 fail_1: 1347 bus_dma_tag_destroy(dma->idi_tag); 1348 fail_0: 1349 dma->idi_tag = NULL; 1350 1351 return (err); 1352 } 1353 1354 int 1355 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1356 { 1357 if_shared_ctx_t sctx = ctx->ifc_sctx; 1358 1359 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1360 1361 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1362 } 1363 1364 int 1365 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1366 { 1367 int i, err; 1368 iflib_dma_info_t *dmaiter; 1369 1370 dmaiter = dmalist; 1371 for (i = 0; i < count; i++, dmaiter++) { 1372 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1373 break; 1374 } 1375 if (err) 1376 iflib_dma_free_multi(dmalist, i); 1377 return (err); 1378 } 1379 1380 void 1381 iflib_dma_free(iflib_dma_info_t dma) 1382 { 1383 if (dma->idi_tag == NULL) 1384 return; 1385 if (dma->idi_paddr != IF_BAD_DMA) { 1386 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1387 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1388 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1389 dma->idi_paddr = IF_BAD_DMA; 1390 } 1391 if (dma->idi_vaddr != NULL) { 1392 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1393 dma->idi_vaddr = NULL; 1394 } 1395 bus_dma_tag_destroy(dma->idi_tag); 1396 dma->idi_tag = NULL; 1397 } 1398 1399 void 1400 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1401 { 1402 int i; 1403 iflib_dma_info_t *dmaiter = dmalist; 1404 1405 for (i = 0; i < count; i++, dmaiter++) 1406 iflib_dma_free(*dmaiter); 1407 } 1408 1409 #ifdef EARLY_AP_STARTUP 1410 static const int iflib_started = 1; 1411 #else 1412 /* 1413 * We used to abuse the smp_started flag to decide if the queues have been 1414 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1415 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1416 * is set. Run a SYSINIT() strictly after that to just set a usable 1417 * completion flag. 1418 */ 1419 1420 static int iflib_started; 1421 1422 static void 1423 iflib_record_started(void *arg) 1424 { 1425 iflib_started = 1; 1426 } 1427 1428 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1429 iflib_record_started, NULL); 1430 #endif 1431 1432 static int 1433 iflib_fast_intr(void *arg) 1434 { 1435 iflib_filter_info_t info = arg; 1436 struct grouptask *gtask = info->ifi_task; 1437 int result; 1438 1439 if (!iflib_started) 1440 return (FILTER_STRAY); 1441 1442 DBG_COUNTER_INC(fast_intrs); 1443 if (info->ifi_filter != NULL) { 1444 result = info->ifi_filter(info->ifi_filter_arg); 1445 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1446 return (result); 1447 } 1448 1449 GROUPTASK_ENQUEUE(gtask); 1450 return (FILTER_HANDLED); 1451 } 1452 1453 static int 1454 iflib_fast_intr_rxtx(void *arg) 1455 { 1456 iflib_filter_info_t info = arg; 1457 struct grouptask *gtask = info->ifi_task; 1458 if_ctx_t ctx; 1459 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1460 iflib_txq_t txq; 1461 void *sc; 1462 int i, cidx, result; 1463 qidx_t txqid; 1464 bool intr_enable, intr_legacy; 1465 1466 if (!iflib_started) 1467 return (FILTER_STRAY); 1468 1469 DBG_COUNTER_INC(fast_intrs); 1470 if (info->ifi_filter != NULL) { 1471 result = info->ifi_filter(info->ifi_filter_arg); 1472 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1473 return (result); 1474 } 1475 1476 ctx = rxq->ifr_ctx; 1477 sc = ctx->ifc_softc; 1478 intr_enable = false; 1479 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1480 MPASS(rxq->ifr_ntxqirq); 1481 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1482 txqid = rxq->ifr_txqid[i]; 1483 txq = &ctx->ifc_txqs[txqid]; 1484 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1485 BUS_DMASYNC_POSTREAD); 1486 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1487 if (intr_legacy) 1488 intr_enable = true; 1489 else 1490 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1491 continue; 1492 } 1493 GROUPTASK_ENQUEUE(&txq->ift_task); 1494 } 1495 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1496 cidx = rxq->ifr_cq_cidx; 1497 else 1498 cidx = rxq->ifr_fl[0].ifl_cidx; 1499 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1500 GROUPTASK_ENQUEUE(gtask); 1501 else { 1502 if (intr_legacy) 1503 intr_enable = true; 1504 else 1505 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1506 DBG_COUNTER_INC(rx_intr_enables); 1507 } 1508 if (intr_enable) 1509 IFDI_INTR_ENABLE(ctx); 1510 return (FILTER_HANDLED); 1511 } 1512 1513 1514 static int 1515 iflib_fast_intr_ctx(void *arg) 1516 { 1517 iflib_filter_info_t info = arg; 1518 struct grouptask *gtask = info->ifi_task; 1519 int result; 1520 1521 if (!iflib_started) 1522 return (FILTER_STRAY); 1523 1524 DBG_COUNTER_INC(fast_intrs); 1525 if (info->ifi_filter != NULL) { 1526 result = info->ifi_filter(info->ifi_filter_arg); 1527 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1528 return (result); 1529 } 1530 1531 GROUPTASK_ENQUEUE(gtask); 1532 return (FILTER_HANDLED); 1533 } 1534 1535 static int 1536 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1537 driver_filter_t filter, driver_intr_t handler, void *arg, 1538 const char *name) 1539 { 1540 struct resource *res; 1541 void *tag = NULL; 1542 device_t dev = ctx->ifc_dev; 1543 int flags, i, rc; 1544 1545 flags = RF_ACTIVE; 1546 if (ctx->ifc_flags & IFC_LEGACY) 1547 flags |= RF_SHAREABLE; 1548 MPASS(rid < 512); 1549 i = rid; 1550 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1551 if (res == NULL) { 1552 device_printf(dev, 1553 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1554 return (ENOMEM); 1555 } 1556 irq->ii_res = res; 1557 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1558 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1559 filter, handler, arg, &tag); 1560 if (rc != 0) { 1561 device_printf(dev, 1562 "failed to setup interrupt for rid %d, name %s: %d\n", 1563 rid, name ? name : "unknown", rc); 1564 return (rc); 1565 } else if (name) 1566 bus_describe_intr(dev, res, tag, "%s", name); 1567 1568 irq->ii_tag = tag; 1569 return (0); 1570 } 1571 1572 /********************************************************************* 1573 * 1574 * Allocate DMA resources for TX buffers as well as memory for the TX 1575 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1576 * iflib_sw_tx_desc_array structure, storing all the information that 1577 * is needed to transmit a packet on the wire. This is called only 1578 * once at attach, setup is done every reset. 1579 * 1580 **********************************************************************/ 1581 static int 1582 iflib_txsd_alloc(iflib_txq_t txq) 1583 { 1584 if_ctx_t ctx = txq->ift_ctx; 1585 if_shared_ctx_t sctx = ctx->ifc_sctx; 1586 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1587 device_t dev = ctx->ifc_dev; 1588 bus_size_t tsomaxsize; 1589 int err, nsegments, ntsosegments; 1590 bool tso; 1591 1592 nsegments = scctx->isc_tx_nsegments; 1593 ntsosegments = scctx->isc_tx_tso_segments_max; 1594 tsomaxsize = scctx->isc_tx_tso_size_max; 1595 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1596 tsomaxsize += sizeof(struct ether_vlan_header); 1597 MPASS(scctx->isc_ntxd[0] > 0); 1598 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1599 MPASS(nsegments > 0); 1600 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1601 MPASS(ntsosegments > 0); 1602 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1603 } 1604 1605 /* 1606 * Set up DMA tags for TX buffers. 1607 */ 1608 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1609 1, 0, /* alignment, bounds */ 1610 BUS_SPACE_MAXADDR, /* lowaddr */ 1611 BUS_SPACE_MAXADDR, /* highaddr */ 1612 NULL, NULL, /* filter, filterarg */ 1613 sctx->isc_tx_maxsize, /* maxsize */ 1614 nsegments, /* nsegments */ 1615 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1616 0, /* flags */ 1617 NULL, /* lockfunc */ 1618 NULL, /* lockfuncarg */ 1619 &txq->ift_buf_tag))) { 1620 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1621 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1622 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1623 goto fail; 1624 } 1625 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1626 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1627 1, 0, /* alignment, bounds */ 1628 BUS_SPACE_MAXADDR, /* lowaddr */ 1629 BUS_SPACE_MAXADDR, /* highaddr */ 1630 NULL, NULL, /* filter, filterarg */ 1631 tsomaxsize, /* maxsize */ 1632 ntsosegments, /* nsegments */ 1633 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1634 0, /* flags */ 1635 NULL, /* lockfunc */ 1636 NULL, /* lockfuncarg */ 1637 &txq->ift_tso_buf_tag))) { 1638 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1639 err); 1640 goto fail; 1641 } 1642 1643 /* Allocate memory for the TX mbuf map. */ 1644 if (!(txq->ift_sds.ifsd_m = 1645 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1646 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1647 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1648 err = ENOMEM; 1649 goto fail; 1650 } 1651 1652 /* 1653 * Create the DMA maps for TX buffers. 1654 */ 1655 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1656 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1657 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1658 device_printf(dev, 1659 "Unable to allocate TX buffer DMA map memory\n"); 1660 err = ENOMEM; 1661 goto fail; 1662 } 1663 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1664 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1665 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1666 device_printf(dev, 1667 "Unable to allocate TSO TX buffer map memory\n"); 1668 err = ENOMEM; 1669 goto fail; 1670 } 1671 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1672 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1673 &txq->ift_sds.ifsd_map[i]); 1674 if (err != 0) { 1675 device_printf(dev, "Unable to create TX DMA map\n"); 1676 goto fail; 1677 } 1678 if (!tso) 1679 continue; 1680 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1681 &txq->ift_sds.ifsd_tso_map[i]); 1682 if (err != 0) { 1683 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1684 goto fail; 1685 } 1686 } 1687 return (0); 1688 fail: 1689 /* We free all, it handles case where we are in the middle */ 1690 iflib_tx_structures_free(ctx); 1691 return (err); 1692 } 1693 1694 static void 1695 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1696 { 1697 bus_dmamap_t map; 1698 1699 if (txq->ift_sds.ifsd_map != NULL) { 1700 map = txq->ift_sds.ifsd_map[i]; 1701 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1702 bus_dmamap_unload(txq->ift_buf_tag, map); 1703 bus_dmamap_destroy(txq->ift_buf_tag, map); 1704 txq->ift_sds.ifsd_map[i] = NULL; 1705 } 1706 1707 if (txq->ift_sds.ifsd_tso_map != NULL) { 1708 map = txq->ift_sds.ifsd_tso_map[i]; 1709 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1710 BUS_DMASYNC_POSTWRITE); 1711 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1712 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1713 txq->ift_sds.ifsd_tso_map[i] = NULL; 1714 } 1715 } 1716 1717 static void 1718 iflib_txq_destroy(iflib_txq_t txq) 1719 { 1720 if_ctx_t ctx = txq->ift_ctx; 1721 1722 for (int i = 0; i < txq->ift_size; i++) 1723 iflib_txsd_destroy(ctx, txq, i); 1724 1725 if (txq->ift_br != NULL) { 1726 ifmp_ring_free(txq->ift_br); 1727 txq->ift_br = NULL; 1728 } 1729 1730 mtx_destroy(&txq->ift_mtx); 1731 1732 if (txq->ift_sds.ifsd_map != NULL) { 1733 free(txq->ift_sds.ifsd_map, M_IFLIB); 1734 txq->ift_sds.ifsd_map = NULL; 1735 } 1736 if (txq->ift_sds.ifsd_tso_map != NULL) { 1737 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1738 txq->ift_sds.ifsd_tso_map = NULL; 1739 } 1740 if (txq->ift_sds.ifsd_m != NULL) { 1741 free(txq->ift_sds.ifsd_m, M_IFLIB); 1742 txq->ift_sds.ifsd_m = NULL; 1743 } 1744 if (txq->ift_buf_tag != NULL) { 1745 bus_dma_tag_destroy(txq->ift_buf_tag); 1746 txq->ift_buf_tag = NULL; 1747 } 1748 if (txq->ift_tso_buf_tag != NULL) { 1749 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1750 txq->ift_tso_buf_tag = NULL; 1751 } 1752 if (txq->ift_ifdi != NULL) { 1753 free(txq->ift_ifdi, M_IFLIB); 1754 } 1755 } 1756 1757 static void 1758 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1759 { 1760 struct mbuf **mp; 1761 1762 mp = &txq->ift_sds.ifsd_m[i]; 1763 if (*mp == NULL) 1764 return; 1765 1766 if (txq->ift_sds.ifsd_map != NULL) { 1767 bus_dmamap_sync(txq->ift_buf_tag, 1768 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1769 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1770 } 1771 if (txq->ift_sds.ifsd_tso_map != NULL) { 1772 bus_dmamap_sync(txq->ift_tso_buf_tag, 1773 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1774 bus_dmamap_unload(txq->ift_tso_buf_tag, 1775 txq->ift_sds.ifsd_tso_map[i]); 1776 } 1777 m_free(*mp); 1778 DBG_COUNTER_INC(tx_frees); 1779 *mp = NULL; 1780 } 1781 1782 static int 1783 iflib_txq_setup(iflib_txq_t txq) 1784 { 1785 if_ctx_t ctx = txq->ift_ctx; 1786 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1787 if_shared_ctx_t sctx = ctx->ifc_sctx; 1788 iflib_dma_info_t di; 1789 int i; 1790 1791 /* Set number of descriptors available */ 1792 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1793 /* XXX make configurable */ 1794 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1795 1796 /* Reset indices */ 1797 txq->ift_cidx_processed = 0; 1798 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1799 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1800 1801 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1802 bzero((void *)di->idi_vaddr, di->idi_size); 1803 1804 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1805 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1806 bus_dmamap_sync(di->idi_tag, di->idi_map, 1807 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1808 return (0); 1809 } 1810 1811 /********************************************************************* 1812 * 1813 * Allocate DMA resources for RX buffers as well as memory for the RX 1814 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1815 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1816 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1817 * Since we use use one entry in iflib_sw_rx_desc_array per received 1818 * packet, the maximum number of entries we'll need is equal to the 1819 * number of hardware receive descriptors that we've allocated. 1820 * 1821 **********************************************************************/ 1822 static int 1823 iflib_rxsd_alloc(iflib_rxq_t rxq) 1824 { 1825 if_ctx_t ctx = rxq->ifr_ctx; 1826 if_shared_ctx_t sctx = ctx->ifc_sctx; 1827 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1828 device_t dev = ctx->ifc_dev; 1829 iflib_fl_t fl; 1830 int err; 1831 1832 MPASS(scctx->isc_nrxd[0] > 0); 1833 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1834 1835 fl = rxq->ifr_fl; 1836 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1837 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1838 /* Set up DMA tag for RX buffers. */ 1839 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1840 1, 0, /* alignment, bounds */ 1841 BUS_SPACE_MAXADDR, /* lowaddr */ 1842 BUS_SPACE_MAXADDR, /* highaddr */ 1843 NULL, NULL, /* filter, filterarg */ 1844 sctx->isc_rx_maxsize, /* maxsize */ 1845 sctx->isc_rx_nsegments, /* nsegments */ 1846 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1847 0, /* flags */ 1848 NULL, /* lockfunc */ 1849 NULL, /* lockarg */ 1850 &fl->ifl_buf_tag); 1851 if (err) { 1852 device_printf(dev, 1853 "Unable to allocate RX DMA tag: %d\n", err); 1854 goto fail; 1855 } 1856 1857 /* Allocate memory for the RX mbuf map. */ 1858 if (!(fl->ifl_sds.ifsd_m = 1859 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1860 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1861 device_printf(dev, 1862 "Unable to allocate RX mbuf map memory\n"); 1863 err = ENOMEM; 1864 goto fail; 1865 } 1866 1867 /* Allocate memory for the direct RX cluster pointer map. */ 1868 if (!(fl->ifl_sds.ifsd_cl = 1869 (caddr_t *) malloc(sizeof(caddr_t) * 1870 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1871 device_printf(dev, 1872 "Unable to allocate RX cluster map memory\n"); 1873 err = ENOMEM; 1874 goto fail; 1875 } 1876 1877 /* Allocate memory for the RX cluster bus address map. */ 1878 if (!(fl->ifl_sds.ifsd_ba = 1879 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1880 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1881 device_printf(dev, 1882 "Unable to allocate RX bus address map memory\n"); 1883 err = ENOMEM; 1884 goto fail; 1885 } 1886 1887 /* 1888 * Create the DMA maps for RX buffers. 1889 */ 1890 if (!(fl->ifl_sds.ifsd_map = 1891 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1892 device_printf(dev, 1893 "Unable to allocate RX buffer DMA map memory\n"); 1894 err = ENOMEM; 1895 goto fail; 1896 } 1897 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1898 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1899 &fl->ifl_sds.ifsd_map[i]); 1900 if (err != 0) { 1901 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1902 goto fail; 1903 } 1904 } 1905 } 1906 return (0); 1907 1908 fail: 1909 iflib_rx_structures_free(ctx); 1910 return (err); 1911 } 1912 1913 1914 /* 1915 * Internal service routines 1916 */ 1917 1918 struct rxq_refill_cb_arg { 1919 int error; 1920 bus_dma_segment_t seg; 1921 int nseg; 1922 }; 1923 1924 static void 1925 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1926 { 1927 struct rxq_refill_cb_arg *cb_arg = arg; 1928 1929 cb_arg->error = error; 1930 cb_arg->seg = segs[0]; 1931 cb_arg->nseg = nseg; 1932 } 1933 1934 /** 1935 * _iflib_fl_refill - refill an rxq free-buffer list 1936 * @ctx: the iflib context 1937 * @fl: the free list to refill 1938 * @count: the number of new buffers to allocate 1939 * 1940 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 1941 * The caller must assure that @count does not exceed the queue's capacity. 1942 */ 1943 static void 1944 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1945 { 1946 struct if_rxd_update iru; 1947 struct rxq_refill_cb_arg cb_arg; 1948 struct mbuf *m; 1949 caddr_t cl, *sd_cl; 1950 struct mbuf **sd_m; 1951 bus_dmamap_t *sd_map; 1952 bus_addr_t bus_addr, *sd_ba; 1953 int err, frag_idx, i, idx, n, pidx; 1954 qidx_t credits; 1955 1956 sd_m = fl->ifl_sds.ifsd_m; 1957 sd_map = fl->ifl_sds.ifsd_map; 1958 sd_cl = fl->ifl_sds.ifsd_cl; 1959 sd_ba = fl->ifl_sds.ifsd_ba; 1960 pidx = fl->ifl_pidx; 1961 idx = pidx; 1962 frag_idx = fl->ifl_fragidx; 1963 credits = fl->ifl_credits; 1964 1965 i = 0; 1966 n = count; 1967 MPASS(n > 0); 1968 MPASS(credits + n <= fl->ifl_size); 1969 1970 if (pidx < fl->ifl_cidx) 1971 MPASS(pidx + n <= fl->ifl_cidx); 1972 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1973 MPASS(fl->ifl_gen == 0); 1974 if (pidx > fl->ifl_cidx) 1975 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1976 1977 DBG_COUNTER_INC(fl_refills); 1978 if (n > 8) 1979 DBG_COUNTER_INC(fl_refills_large); 1980 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1981 while (n--) { 1982 /* 1983 * We allocate an uninitialized mbuf + cluster, mbuf is 1984 * initialized after rx. 1985 * 1986 * If the cluster is still set then we know a minimum sized packet was received 1987 */ 1988 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 1989 &frag_idx); 1990 if (frag_idx < 0) 1991 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1992 MPASS(frag_idx >= 0); 1993 if ((cl = sd_cl[frag_idx]) == NULL) { 1994 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1995 break; 1996 1997 cb_arg.error = 0; 1998 MPASS(sd_map != NULL); 1999 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2000 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2001 BUS_DMA_NOWAIT); 2002 if (err != 0 || cb_arg.error) { 2003 /* 2004 * !zone_pack ? 2005 */ 2006 if (fl->ifl_zone == zone_pack) 2007 uma_zfree(fl->ifl_zone, cl); 2008 break; 2009 } 2010 2011 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2012 sd_cl[frag_idx] = cl; 2013 #if MEMORY_LOGGING 2014 fl->ifl_cl_enqueued++; 2015 #endif 2016 } else { 2017 bus_addr = sd_ba[frag_idx]; 2018 } 2019 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2020 BUS_DMASYNC_PREREAD); 2021 2022 if (sd_m[frag_idx] == NULL) { 2023 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 2024 break; 2025 } 2026 sd_m[frag_idx] = m; 2027 } 2028 bit_set(fl->ifl_rx_bitmap, frag_idx); 2029 #if MEMORY_LOGGING 2030 fl->ifl_m_enqueued++; 2031 #endif 2032 2033 DBG_COUNTER_INC(rx_allocs); 2034 fl->ifl_rxd_idxs[i] = frag_idx; 2035 fl->ifl_bus_addrs[i] = bus_addr; 2036 fl->ifl_vm_addrs[i] = cl; 2037 credits++; 2038 i++; 2039 MPASS(credits <= fl->ifl_size); 2040 if (++idx == fl->ifl_size) { 2041 fl->ifl_gen = 1; 2042 idx = 0; 2043 } 2044 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2045 iru.iru_pidx = pidx; 2046 iru.iru_count = i; 2047 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2048 i = 0; 2049 pidx = idx; 2050 fl->ifl_pidx = idx; 2051 fl->ifl_credits = credits; 2052 } 2053 } 2054 2055 if (i) { 2056 iru.iru_pidx = pidx; 2057 iru.iru_count = i; 2058 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2059 fl->ifl_pidx = idx; 2060 fl->ifl_credits = credits; 2061 } 2062 DBG_COUNTER_INC(rxd_flush); 2063 if (fl->ifl_pidx == 0) 2064 pidx = fl->ifl_size - 1; 2065 else 2066 pidx = fl->ifl_pidx - 1; 2067 2068 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2069 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2070 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2071 fl->ifl_fragidx = frag_idx; 2072 } 2073 2074 static __inline void 2075 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2076 { 2077 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2078 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2079 #ifdef INVARIANTS 2080 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2081 #endif 2082 2083 MPASS(fl->ifl_credits <= fl->ifl_size); 2084 MPASS(reclaimable == delta); 2085 2086 if (reclaimable > 0) 2087 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2088 } 2089 2090 uint8_t 2091 iflib_in_detach(if_ctx_t ctx) 2092 { 2093 bool in_detach; 2094 2095 STATE_LOCK(ctx); 2096 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2097 STATE_UNLOCK(ctx); 2098 return (in_detach); 2099 } 2100 2101 static void 2102 iflib_fl_bufs_free(iflib_fl_t fl) 2103 { 2104 iflib_dma_info_t idi = fl->ifl_ifdi; 2105 bus_dmamap_t sd_map; 2106 uint32_t i; 2107 2108 for (i = 0; i < fl->ifl_size; i++) { 2109 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2110 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2111 2112 if (*sd_cl != NULL) { 2113 sd_map = fl->ifl_sds.ifsd_map[i]; 2114 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2115 BUS_DMASYNC_POSTREAD); 2116 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2117 if (*sd_cl != NULL) 2118 uma_zfree(fl->ifl_zone, *sd_cl); 2119 if (*sd_m != NULL) { 2120 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2121 uma_zfree(zone_mbuf, *sd_m); 2122 } 2123 } else { 2124 MPASS(*sd_cl == NULL); 2125 MPASS(*sd_m == NULL); 2126 } 2127 #if MEMORY_LOGGING 2128 fl->ifl_m_dequeued++; 2129 fl->ifl_cl_dequeued++; 2130 #endif 2131 *sd_cl = NULL; 2132 *sd_m = NULL; 2133 } 2134 #ifdef INVARIANTS 2135 for (i = 0; i < fl->ifl_size; i++) { 2136 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2137 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2138 } 2139 #endif 2140 /* 2141 * Reset free list values 2142 */ 2143 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2144 bzero(idi->idi_vaddr, idi->idi_size); 2145 } 2146 2147 /********************************************************************* 2148 * 2149 * Initialize a free list and its buffers. 2150 * 2151 **********************************************************************/ 2152 static int 2153 iflib_fl_setup(iflib_fl_t fl) 2154 { 2155 iflib_rxq_t rxq = fl->ifl_rxq; 2156 if_ctx_t ctx = rxq->ifr_ctx; 2157 2158 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2159 /* 2160 ** Free current RX buffer structs and their mbufs 2161 */ 2162 iflib_fl_bufs_free(fl); 2163 /* Now replenish the mbufs */ 2164 MPASS(fl->ifl_credits == 0); 2165 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2166 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2167 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2168 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2169 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2170 2171 2172 /* avoid pre-allocating zillions of clusters to an idle card 2173 * potentially speeding up attach 2174 */ 2175 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2176 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2177 if (min(128, fl->ifl_size) != fl->ifl_credits) 2178 return (ENOBUFS); 2179 /* 2180 * handle failure 2181 */ 2182 MPASS(rxq != NULL); 2183 MPASS(fl->ifl_ifdi != NULL); 2184 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2185 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2186 return (0); 2187 } 2188 2189 /********************************************************************* 2190 * 2191 * Free receive ring data structures 2192 * 2193 **********************************************************************/ 2194 static void 2195 iflib_rx_sds_free(iflib_rxq_t rxq) 2196 { 2197 iflib_fl_t fl; 2198 int i, j; 2199 2200 if (rxq->ifr_fl != NULL) { 2201 for (i = 0; i < rxq->ifr_nfl; i++) { 2202 fl = &rxq->ifr_fl[i]; 2203 if (fl->ifl_buf_tag != NULL) { 2204 if (fl->ifl_sds.ifsd_map != NULL) { 2205 for (j = 0; j < fl->ifl_size; j++) { 2206 bus_dmamap_sync( 2207 fl->ifl_buf_tag, 2208 fl->ifl_sds.ifsd_map[j], 2209 BUS_DMASYNC_POSTREAD); 2210 bus_dmamap_unload( 2211 fl->ifl_buf_tag, 2212 fl->ifl_sds.ifsd_map[j]); 2213 bus_dmamap_destroy( 2214 fl->ifl_buf_tag, 2215 fl->ifl_sds.ifsd_map[j]); 2216 } 2217 } 2218 bus_dma_tag_destroy(fl->ifl_buf_tag); 2219 fl->ifl_buf_tag = NULL; 2220 } 2221 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2222 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2223 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2224 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2225 fl->ifl_sds.ifsd_m = NULL; 2226 fl->ifl_sds.ifsd_cl = NULL; 2227 fl->ifl_sds.ifsd_ba = NULL; 2228 fl->ifl_sds.ifsd_map = NULL; 2229 } 2230 free(rxq->ifr_fl, M_IFLIB); 2231 rxq->ifr_fl = NULL; 2232 free(rxq->ifr_ifdi, M_IFLIB); 2233 rxq->ifr_ifdi = NULL; 2234 rxq->ifr_cq_cidx = 0; 2235 } 2236 } 2237 2238 /* 2239 * Timer routine 2240 */ 2241 static void 2242 iflib_timer(void *arg) 2243 { 2244 iflib_txq_t txq = arg; 2245 if_ctx_t ctx = txq->ift_ctx; 2246 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2247 uint64_t this_tick = ticks; 2248 uint32_t reset_on = hz / 2; 2249 2250 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2251 return; 2252 2253 /* 2254 ** Check on the state of the TX queue(s), this 2255 ** can be done without the lock because its RO 2256 ** and the HUNG state will be static if set. 2257 */ 2258 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2259 txq->ift_last_timer_tick = this_tick; 2260 IFDI_TIMER(ctx, txq->ift_id); 2261 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2262 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2263 (sctx->isc_pause_frames == 0))) 2264 goto hung; 2265 2266 if (ifmp_ring_is_stalled(txq->ift_br)) 2267 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2268 txq->ift_cleaned_prev = txq->ift_cleaned; 2269 } 2270 #ifdef DEV_NETMAP 2271 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2272 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 2273 #endif 2274 /* handle any laggards */ 2275 if (txq->ift_db_pending) 2276 GROUPTASK_ENQUEUE(&txq->ift_task); 2277 2278 sctx->isc_pause_frames = 0; 2279 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2280 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2281 return; 2282 2283 hung: 2284 device_printf(ctx->ifc_dev, 2285 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2286 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2287 STATE_LOCK(ctx); 2288 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2289 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2290 iflib_admin_intr_deferred(ctx); 2291 STATE_UNLOCK(ctx); 2292 } 2293 2294 static void 2295 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2296 { 2297 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2298 2299 /* 2300 * XXX don't set the max_frame_size to larger 2301 * than the hardware can handle 2302 */ 2303 if (sctx->isc_max_frame_size <= MCLBYTES) 2304 ctx->ifc_rx_mbuf_sz = MCLBYTES; 2305 else 2306 ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE; 2307 } 2308 2309 uint32_t 2310 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2311 { 2312 2313 return (ctx->ifc_rx_mbuf_sz); 2314 } 2315 2316 static void 2317 iflib_init_locked(if_ctx_t ctx) 2318 { 2319 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2320 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2321 if_t ifp = ctx->ifc_ifp; 2322 iflib_fl_t fl; 2323 iflib_txq_t txq; 2324 iflib_rxq_t rxq; 2325 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2326 2327 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2328 IFDI_INTR_DISABLE(ctx); 2329 2330 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2331 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2332 /* Set hardware offload abilities */ 2333 if_clearhwassist(ifp); 2334 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2335 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2336 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2337 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2338 if (if_getcapenable(ifp) & IFCAP_TSO4) 2339 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2340 if (if_getcapenable(ifp) & IFCAP_TSO6) 2341 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2342 2343 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2344 CALLOUT_LOCK(txq); 2345 callout_stop(&txq->ift_timer); 2346 CALLOUT_UNLOCK(txq); 2347 iflib_netmap_txq_init(ctx, txq); 2348 } 2349 2350 /* 2351 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2352 * that drivers can use the value when setting up the hardware receive 2353 * buffers. 2354 */ 2355 iflib_calc_rx_mbuf_sz(ctx); 2356 2357 #ifdef INVARIANTS 2358 i = if_getdrvflags(ifp); 2359 #endif 2360 IFDI_INIT(ctx); 2361 MPASS(if_getdrvflags(ifp) == i); 2362 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2363 /* XXX this should really be done on a per-queue basis */ 2364 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2365 MPASS(rxq->ifr_id == i); 2366 iflib_netmap_rxq_init(ctx, rxq); 2367 continue; 2368 } 2369 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2370 if (iflib_fl_setup(fl)) { 2371 device_printf(ctx->ifc_dev, 2372 "setting up free list %d failed - " 2373 "check cluster settings\n", j); 2374 goto done; 2375 } 2376 } 2377 } 2378 done: 2379 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2380 IFDI_INTR_ENABLE(ctx); 2381 txq = ctx->ifc_txqs; 2382 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2383 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2384 txq->ift_timer.c_cpu); 2385 } 2386 2387 static int 2388 iflib_media_change(if_t ifp) 2389 { 2390 if_ctx_t ctx = if_getsoftc(ifp); 2391 int err; 2392 2393 CTX_LOCK(ctx); 2394 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2395 iflib_init_locked(ctx); 2396 CTX_UNLOCK(ctx); 2397 return (err); 2398 } 2399 2400 static void 2401 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2402 { 2403 if_ctx_t ctx = if_getsoftc(ifp); 2404 2405 CTX_LOCK(ctx); 2406 IFDI_UPDATE_ADMIN_STATUS(ctx); 2407 IFDI_MEDIA_STATUS(ctx, ifmr); 2408 CTX_UNLOCK(ctx); 2409 } 2410 2411 void 2412 iflib_stop(if_ctx_t ctx) 2413 { 2414 iflib_txq_t txq = ctx->ifc_txqs; 2415 iflib_rxq_t rxq = ctx->ifc_rxqs; 2416 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2417 if_shared_ctx_t sctx = ctx->ifc_sctx; 2418 iflib_dma_info_t di; 2419 iflib_fl_t fl; 2420 int i, j; 2421 2422 /* Tell the stack that the interface is no longer active */ 2423 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2424 2425 IFDI_INTR_DISABLE(ctx); 2426 DELAY(1000); 2427 IFDI_STOP(ctx); 2428 DELAY(1000); 2429 2430 iflib_debug_reset(); 2431 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2432 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2433 /* make sure all transmitters have completed before proceeding XXX */ 2434 2435 CALLOUT_LOCK(txq); 2436 callout_stop(&txq->ift_timer); 2437 CALLOUT_UNLOCK(txq); 2438 2439 /* clean any enqueued buffers */ 2440 iflib_ifmp_purge(txq); 2441 /* Free any existing tx buffers. */ 2442 for (j = 0; j < txq->ift_size; j++) { 2443 iflib_txsd_free(ctx, txq, j); 2444 } 2445 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2446 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2447 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2448 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2449 txq->ift_pullups = 0; 2450 ifmp_ring_reset_stats(txq->ift_br); 2451 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2452 bzero((void *)di->idi_vaddr, di->idi_size); 2453 } 2454 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2455 /* make sure all transmitters have completed before proceeding XXX */ 2456 2457 rxq->ifr_cq_cidx = 0; 2458 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2459 bzero((void *)di->idi_vaddr, di->idi_size); 2460 /* also resets the free lists pidx/cidx */ 2461 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2462 iflib_fl_bufs_free(fl); 2463 } 2464 } 2465 2466 static inline caddr_t 2467 calc_next_rxd(iflib_fl_t fl, int cidx) 2468 { 2469 qidx_t size; 2470 int nrxd; 2471 caddr_t start, end, cur, next; 2472 2473 nrxd = fl->ifl_size; 2474 size = fl->ifl_rxd_size; 2475 start = fl->ifl_ifdi->idi_vaddr; 2476 2477 if (__predict_false(size == 0)) 2478 return (start); 2479 cur = start + size*cidx; 2480 end = start + size*nrxd; 2481 next = CACHE_PTR_NEXT(cur); 2482 return (next < end ? next : start); 2483 } 2484 2485 static inline void 2486 prefetch_pkts(iflib_fl_t fl, int cidx) 2487 { 2488 int nextptr; 2489 int nrxd = fl->ifl_size; 2490 caddr_t next_rxd; 2491 2492 2493 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2494 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2495 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2496 next_rxd = calc_next_rxd(fl, cidx); 2497 prefetch(next_rxd); 2498 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2499 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2500 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2501 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2502 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2503 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2504 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2505 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2506 } 2507 2508 static struct mbuf * 2509 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2510 int *pf_rv, if_rxd_info_t ri) 2511 { 2512 bus_dmamap_t map; 2513 iflib_fl_t fl; 2514 caddr_t payload; 2515 struct mbuf *m; 2516 int flid, cidx, len, next; 2517 2518 map = NULL; 2519 flid = irf->irf_flid; 2520 cidx = irf->irf_idx; 2521 fl = &rxq->ifr_fl[flid]; 2522 sd->ifsd_fl = fl; 2523 sd->ifsd_cidx = cidx; 2524 m = fl->ifl_sds.ifsd_m[cidx]; 2525 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2526 fl->ifl_credits--; 2527 #if MEMORY_LOGGING 2528 fl->ifl_m_dequeued++; 2529 #endif 2530 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2531 prefetch_pkts(fl, cidx); 2532 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2533 prefetch(&fl->ifl_sds.ifsd_map[next]); 2534 map = fl->ifl_sds.ifsd_map[cidx]; 2535 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2536 2537 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2538 MPASS(fl->ifl_cidx == cidx); 2539 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2540 2541 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL) { 2542 payload = *sd->ifsd_cl; 2543 payload += ri->iri_pad; 2544 len = ri->iri_len - ri->iri_pad; 2545 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2546 len | PFIL_MEMPTR | PFIL_IN, NULL); 2547 switch (*pf_rv) { 2548 case PFIL_DROPPED: 2549 case PFIL_CONSUMED: 2550 /* 2551 * The filter ate it. Everything is recycled. 2552 */ 2553 m = NULL; 2554 unload = 0; 2555 break; 2556 case PFIL_REALLOCED: 2557 /* 2558 * The filter copied it. Everything is recycled. 2559 */ 2560 m = pfil_mem2mbuf(payload); 2561 unload = 0; 2562 break; 2563 case PFIL_PASS: 2564 /* 2565 * Filter said it was OK, so receive like 2566 * normal 2567 */ 2568 fl->ifl_sds.ifsd_m[cidx] = NULL; 2569 break; 2570 default: 2571 MPASS(0); 2572 } 2573 } else { 2574 fl->ifl_sds.ifsd_m[cidx] = NULL; 2575 *pf_rv = PFIL_PASS; 2576 } 2577 2578 if (unload) 2579 bus_dmamap_unload(fl->ifl_buf_tag, map); 2580 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2581 if (__predict_false(fl->ifl_cidx == 0)) 2582 fl->ifl_gen = 0; 2583 bit_clear(fl->ifl_rx_bitmap, cidx); 2584 return (m); 2585 } 2586 2587 static struct mbuf * 2588 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2589 { 2590 struct mbuf *m, *mh, *mt; 2591 caddr_t cl; 2592 int *pf_rv_ptr, flags, i, padlen; 2593 bool consumed; 2594 2595 i = 0; 2596 mh = NULL; 2597 consumed = false; 2598 *pf_rv = PFIL_PASS; 2599 pf_rv_ptr = pf_rv; 2600 do { 2601 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2602 pf_rv_ptr, ri); 2603 2604 MPASS(*sd->ifsd_cl != NULL); 2605 2606 /* 2607 * Exclude zero-length frags & frags from 2608 * packets the filter has consumed or dropped 2609 */ 2610 if (ri->iri_frags[i].irf_len == 0 || consumed || 2611 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2612 if (mh == NULL) { 2613 /* everything saved here */ 2614 consumed = true; 2615 pf_rv_ptr = NULL; 2616 continue; 2617 } 2618 /* XXX we can save the cluster here, but not the mbuf */ 2619 m_init(m, M_NOWAIT, MT_DATA, 0); 2620 m_free(m); 2621 continue; 2622 } 2623 if (mh == NULL) { 2624 flags = M_PKTHDR|M_EXT; 2625 mh = mt = m; 2626 padlen = ri->iri_pad; 2627 } else { 2628 flags = M_EXT; 2629 mt->m_next = m; 2630 mt = m; 2631 /* assuming padding is only on the first fragment */ 2632 padlen = 0; 2633 } 2634 cl = *sd->ifsd_cl; 2635 *sd->ifsd_cl = NULL; 2636 2637 /* Can these two be made one ? */ 2638 m_init(m, M_NOWAIT, MT_DATA, flags); 2639 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2640 /* 2641 * These must follow m_init and m_cljset 2642 */ 2643 m->m_data += padlen; 2644 ri->iri_len -= padlen; 2645 m->m_len = ri->iri_frags[i].irf_len; 2646 } while (++i < ri->iri_nfrags); 2647 2648 return (mh); 2649 } 2650 2651 /* 2652 * Process one software descriptor 2653 */ 2654 static struct mbuf * 2655 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2656 { 2657 struct if_rxsd sd; 2658 struct mbuf *m; 2659 int pf_rv; 2660 2661 /* should I merge this back in now that the two paths are basically duplicated? */ 2662 if (ri->iri_nfrags == 1 && 2663 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2664 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2665 &pf_rv, ri); 2666 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2667 return (m); 2668 if (pf_rv == PFIL_PASS) { 2669 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2670 #ifndef __NO_STRICT_ALIGNMENT 2671 if (!IP_ALIGNED(m)) 2672 m->m_data += 2; 2673 #endif 2674 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2675 m->m_len = ri->iri_frags[0].irf_len; 2676 } 2677 } else { 2678 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2679 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2680 return (m); 2681 } 2682 m->m_pkthdr.len = ri->iri_len; 2683 m->m_pkthdr.rcvif = ri->iri_ifp; 2684 m->m_flags |= ri->iri_flags; 2685 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2686 m->m_pkthdr.flowid = ri->iri_flowid; 2687 M_HASHTYPE_SET(m, ri->iri_rsstype); 2688 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2689 m->m_pkthdr.csum_data = ri->iri_csum_data; 2690 return (m); 2691 } 2692 2693 #if defined(INET6) || defined(INET) 2694 static void 2695 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2696 { 2697 CURVNET_SET(lc->ifp->if_vnet); 2698 #if defined(INET6) 2699 *v6 = V_ip6_forwarding; 2700 #endif 2701 #if defined(INET) 2702 *v4 = V_ipforwarding; 2703 #endif 2704 CURVNET_RESTORE(); 2705 } 2706 2707 /* 2708 * Returns true if it's possible this packet could be LROed. 2709 * if it returns false, it is guaranteed that tcp_lro_rx() 2710 * would not return zero. 2711 */ 2712 static bool 2713 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2714 { 2715 struct ether_header *eh; 2716 2717 eh = mtod(m, struct ether_header *); 2718 switch (eh->ether_type) { 2719 #if defined(INET6) 2720 case htons(ETHERTYPE_IPV6): 2721 return (!v6_forwarding); 2722 #endif 2723 #if defined (INET) 2724 case htons(ETHERTYPE_IP): 2725 return (!v4_forwarding); 2726 #endif 2727 } 2728 2729 return false; 2730 } 2731 #else 2732 static void 2733 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2734 { 2735 } 2736 #endif 2737 2738 static bool 2739 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2740 { 2741 if_t ifp; 2742 if_ctx_t ctx = rxq->ifr_ctx; 2743 if_shared_ctx_t sctx = ctx->ifc_sctx; 2744 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2745 int avail, i; 2746 qidx_t *cidxp; 2747 struct if_rxd_info ri; 2748 int err, budget_left, rx_bytes, rx_pkts; 2749 iflib_fl_t fl; 2750 int lro_enabled; 2751 bool v4_forwarding, v6_forwarding, lro_possible; 2752 2753 /* 2754 * XXX early demux data packets so that if_input processing only handles 2755 * acks in interrupt context 2756 */ 2757 struct mbuf *m, *mh, *mt, *mf; 2758 2759 lro_possible = v4_forwarding = v6_forwarding = false; 2760 ifp = ctx->ifc_ifp; 2761 mh = mt = NULL; 2762 MPASS(budget > 0); 2763 rx_pkts = rx_bytes = 0; 2764 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2765 cidxp = &rxq->ifr_cq_cidx; 2766 else 2767 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2768 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2769 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2770 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2771 DBG_COUNTER_INC(rx_unavail); 2772 return (false); 2773 } 2774 2775 /* pfil needs the vnet to be set */ 2776 CURVNET_SET_QUIET(ifp->if_vnet); 2777 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2778 if (__predict_false(!CTX_ACTIVE(ctx))) { 2779 DBG_COUNTER_INC(rx_ctx_inactive); 2780 break; 2781 } 2782 /* 2783 * Reset client set fields to their default values 2784 */ 2785 rxd_info_zero(&ri); 2786 ri.iri_qsidx = rxq->ifr_id; 2787 ri.iri_cidx = *cidxp; 2788 ri.iri_ifp = ifp; 2789 ri.iri_frags = rxq->ifr_frags; 2790 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2791 2792 if (err) 2793 goto err; 2794 rx_pkts += 1; 2795 rx_bytes += ri.iri_len; 2796 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2797 *cidxp = ri.iri_cidx; 2798 /* Update our consumer index */ 2799 /* XXX NB: shurd - check if this is still safe */ 2800 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2801 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2802 /* was this only a completion queue message? */ 2803 if (__predict_false(ri.iri_nfrags == 0)) 2804 continue; 2805 } 2806 MPASS(ri.iri_nfrags != 0); 2807 MPASS(ri.iri_len != 0); 2808 2809 /* will advance the cidx on the corresponding free lists */ 2810 m = iflib_rxd_pkt_get(rxq, &ri); 2811 avail--; 2812 budget_left--; 2813 if (avail == 0 && budget_left) 2814 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2815 2816 if (__predict_false(m == NULL)) 2817 continue; 2818 2819 /* imm_pkt: -- cxgb */ 2820 if (mh == NULL) 2821 mh = mt = m; 2822 else { 2823 mt->m_nextpkt = m; 2824 mt = m; 2825 } 2826 } 2827 CURVNET_RESTORE(); 2828 /* make sure that we can refill faster than drain */ 2829 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2830 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2831 2832 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2833 if (lro_enabled) 2834 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2835 mt = mf = NULL; 2836 while (mh != NULL) { 2837 m = mh; 2838 mh = mh->m_nextpkt; 2839 m->m_nextpkt = NULL; 2840 #ifndef __NO_STRICT_ALIGNMENT 2841 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2842 continue; 2843 #endif 2844 rx_bytes += m->m_pkthdr.len; 2845 rx_pkts++; 2846 #if defined(INET6) || defined(INET) 2847 if (lro_enabled) { 2848 if (!lro_possible) { 2849 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2850 if (lro_possible && mf != NULL) { 2851 ifp->if_input(ifp, mf); 2852 DBG_COUNTER_INC(rx_if_input); 2853 mt = mf = NULL; 2854 } 2855 } 2856 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2857 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2858 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2859 continue; 2860 } 2861 } 2862 #endif 2863 if (lro_possible) { 2864 ifp->if_input(ifp, m); 2865 DBG_COUNTER_INC(rx_if_input); 2866 continue; 2867 } 2868 2869 if (mf == NULL) 2870 mf = m; 2871 if (mt != NULL) 2872 mt->m_nextpkt = m; 2873 mt = m; 2874 } 2875 if (mf != NULL) { 2876 ifp->if_input(ifp, mf); 2877 DBG_COUNTER_INC(rx_if_input); 2878 } 2879 2880 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2881 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2882 2883 /* 2884 * Flush any outstanding LRO work 2885 */ 2886 #if defined(INET6) || defined(INET) 2887 tcp_lro_flush_all(&rxq->ifr_lc); 2888 #endif 2889 if (avail) 2890 return true; 2891 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2892 err: 2893 STATE_LOCK(ctx); 2894 ctx->ifc_flags |= IFC_DO_RESET; 2895 iflib_admin_intr_deferred(ctx); 2896 STATE_UNLOCK(ctx); 2897 return (false); 2898 } 2899 2900 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2901 static inline qidx_t 2902 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2903 { 2904 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2905 qidx_t minthresh = txq->ift_size / 8; 2906 if (in_use > 4*minthresh) 2907 return (notify_count); 2908 if (in_use > 2*minthresh) 2909 return (notify_count >> 1); 2910 if (in_use > minthresh) 2911 return (notify_count >> 3); 2912 return (0); 2913 } 2914 2915 static inline qidx_t 2916 txq_max_rs_deferred(iflib_txq_t txq) 2917 { 2918 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2919 qidx_t minthresh = txq->ift_size / 8; 2920 if (txq->ift_in_use > 4*minthresh) 2921 return (notify_count); 2922 if (txq->ift_in_use > 2*minthresh) 2923 return (notify_count >> 1); 2924 if (txq->ift_in_use > minthresh) 2925 return (notify_count >> 2); 2926 return (2); 2927 } 2928 2929 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2930 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2931 2932 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2933 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2934 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2935 2936 /* forward compatibility for cxgb */ 2937 #define FIRST_QSET(ctx) 0 2938 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2939 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2940 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2941 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2942 2943 /* XXX we should be setting this to something other than zero */ 2944 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2945 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2946 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2947 2948 static inline bool 2949 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2950 { 2951 qidx_t dbval, max; 2952 bool rang; 2953 2954 rang = false; 2955 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2956 if (ring || txq->ift_db_pending >= max) { 2957 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2958 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 2959 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2960 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2961 txq->ift_db_pending = txq->ift_npending = 0; 2962 rang = true; 2963 } 2964 return (rang); 2965 } 2966 2967 #ifdef PKT_DEBUG 2968 static void 2969 print_pkt(if_pkt_info_t pi) 2970 { 2971 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2972 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2973 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2974 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2975 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2976 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2977 } 2978 #endif 2979 2980 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2981 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2982 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2983 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2984 2985 static int 2986 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2987 { 2988 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2989 struct ether_vlan_header *eh; 2990 struct mbuf *m; 2991 2992 m = *mp; 2993 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2994 M_WRITABLE(m) == 0) { 2995 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2996 return (ENOMEM); 2997 } else { 2998 m_freem(*mp); 2999 DBG_COUNTER_INC(tx_frees); 3000 *mp = m; 3001 } 3002 } 3003 3004 /* 3005 * Determine where frame payload starts. 3006 * Jump over vlan headers if already present, 3007 * helpful for QinQ too. 3008 */ 3009 if (__predict_false(m->m_len < sizeof(*eh))) { 3010 txq->ift_pullups++; 3011 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3012 return (ENOMEM); 3013 } 3014 eh = mtod(m, struct ether_vlan_header *); 3015 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3016 pi->ipi_etype = ntohs(eh->evl_proto); 3017 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3018 } else { 3019 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3020 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3021 } 3022 3023 switch (pi->ipi_etype) { 3024 #ifdef INET 3025 case ETHERTYPE_IP: 3026 { 3027 struct mbuf *n; 3028 struct ip *ip = NULL; 3029 struct tcphdr *th = NULL; 3030 int minthlen; 3031 3032 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3033 if (__predict_false(m->m_len < minthlen)) { 3034 /* 3035 * if this code bloat is causing too much of a hit 3036 * move it to a separate function and mark it noinline 3037 */ 3038 if (m->m_len == pi->ipi_ehdrlen) { 3039 n = m->m_next; 3040 MPASS(n); 3041 if (n->m_len >= sizeof(*ip)) { 3042 ip = (struct ip *)n->m_data; 3043 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3044 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3045 } else { 3046 txq->ift_pullups++; 3047 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3048 return (ENOMEM); 3049 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3050 } 3051 } else { 3052 txq->ift_pullups++; 3053 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3054 return (ENOMEM); 3055 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3056 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3057 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3058 } 3059 } else { 3060 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3061 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3062 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3063 } 3064 pi->ipi_ip_hlen = ip->ip_hl << 2; 3065 pi->ipi_ipproto = ip->ip_p; 3066 pi->ipi_flags |= IPI_TX_IPV4; 3067 3068 /* TCP checksum offload may require TCP header length */ 3069 if (IS_TX_OFFLOAD4(pi)) { 3070 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3071 if (__predict_false(th == NULL)) { 3072 txq->ift_pullups++; 3073 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3074 return (ENOMEM); 3075 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3076 } 3077 pi->ipi_tcp_hflags = th->th_flags; 3078 pi->ipi_tcp_hlen = th->th_off << 2; 3079 pi->ipi_tcp_seq = th->th_seq; 3080 } 3081 if (IS_TSO4(pi)) { 3082 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3083 return (ENXIO); 3084 /* 3085 * TSO always requires hardware checksum offload. 3086 */ 3087 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3088 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3089 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3090 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3091 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3092 ip->ip_sum = 0; 3093 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3094 } 3095 } 3096 } 3097 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3098 ip->ip_sum = 0; 3099 3100 break; 3101 } 3102 #endif 3103 #ifdef INET6 3104 case ETHERTYPE_IPV6: 3105 { 3106 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3107 struct tcphdr *th; 3108 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3109 3110 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3111 txq->ift_pullups++; 3112 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3113 return (ENOMEM); 3114 } 3115 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3116 3117 /* XXX-BZ this will go badly in case of ext hdrs. */ 3118 pi->ipi_ipproto = ip6->ip6_nxt; 3119 pi->ipi_flags |= IPI_TX_IPV6; 3120 3121 /* TCP checksum offload may require TCP header length */ 3122 if (IS_TX_OFFLOAD6(pi)) { 3123 if (pi->ipi_ipproto == IPPROTO_TCP) { 3124 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3125 txq->ift_pullups++; 3126 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3127 return (ENOMEM); 3128 } 3129 pi->ipi_tcp_hflags = th->th_flags; 3130 pi->ipi_tcp_hlen = th->th_off << 2; 3131 pi->ipi_tcp_seq = th->th_seq; 3132 } 3133 if (IS_TSO6(pi)) { 3134 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3135 return (ENXIO); 3136 /* 3137 * TSO always requires hardware checksum offload. 3138 */ 3139 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3140 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3141 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3142 } 3143 } 3144 break; 3145 } 3146 #endif 3147 default: 3148 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3149 pi->ipi_ip_hlen = 0; 3150 break; 3151 } 3152 *mp = m; 3153 3154 return (0); 3155 } 3156 3157 /* 3158 * If dodgy hardware rejects the scatter gather chain we've handed it 3159 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3160 * m_defrag'd mbufs 3161 */ 3162 static __noinline struct mbuf * 3163 iflib_remove_mbuf(iflib_txq_t txq) 3164 { 3165 int ntxd, pidx; 3166 struct mbuf *m, **ifsd_m; 3167 3168 ifsd_m = txq->ift_sds.ifsd_m; 3169 ntxd = txq->ift_size; 3170 pidx = txq->ift_pidx & (ntxd - 1); 3171 ifsd_m = txq->ift_sds.ifsd_m; 3172 m = ifsd_m[pidx]; 3173 ifsd_m[pidx] = NULL; 3174 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3175 if (txq->ift_sds.ifsd_tso_map != NULL) 3176 bus_dmamap_unload(txq->ift_tso_buf_tag, 3177 txq->ift_sds.ifsd_tso_map[pidx]); 3178 #if MEMORY_LOGGING 3179 txq->ift_dequeued++; 3180 #endif 3181 return (m); 3182 } 3183 3184 static inline caddr_t 3185 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3186 { 3187 qidx_t size; 3188 int ntxd; 3189 caddr_t start, end, cur, next; 3190 3191 ntxd = txq->ift_size; 3192 size = txq->ift_txd_size[qid]; 3193 start = txq->ift_ifdi[qid].idi_vaddr; 3194 3195 if (__predict_false(size == 0)) 3196 return (start); 3197 cur = start + size*cidx; 3198 end = start + size*ntxd; 3199 next = CACHE_PTR_NEXT(cur); 3200 return (next < end ? next : start); 3201 } 3202 3203 /* 3204 * Pad an mbuf to ensure a minimum ethernet frame size. 3205 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3206 */ 3207 static __noinline int 3208 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3209 { 3210 /* 3211 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3212 * and ARP message is the smallest common payload I can think of 3213 */ 3214 static char pad[18]; /* just zeros */ 3215 int n; 3216 struct mbuf *new_head; 3217 3218 if (!M_WRITABLE(*m_head)) { 3219 new_head = m_dup(*m_head, M_NOWAIT); 3220 if (new_head == NULL) { 3221 m_freem(*m_head); 3222 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3223 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3224 DBG_COUNTER_INC(tx_frees); 3225 return ENOMEM; 3226 } 3227 m_freem(*m_head); 3228 *m_head = new_head; 3229 } 3230 3231 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3232 n > 0; n -= sizeof(pad)) 3233 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3234 break; 3235 3236 if (n > 0) { 3237 m_freem(*m_head); 3238 device_printf(dev, "cannot pad short frame\n"); 3239 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3240 DBG_COUNTER_INC(tx_frees); 3241 return (ENOBUFS); 3242 } 3243 3244 return 0; 3245 } 3246 3247 static int 3248 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3249 { 3250 if_ctx_t ctx; 3251 if_shared_ctx_t sctx; 3252 if_softc_ctx_t scctx; 3253 bus_dma_tag_t buf_tag; 3254 bus_dma_segment_t *segs; 3255 struct mbuf *m_head, **ifsd_m; 3256 void *next_txd; 3257 bus_dmamap_t map; 3258 struct if_pkt_info pi; 3259 int remap = 0; 3260 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3261 3262 ctx = txq->ift_ctx; 3263 sctx = ctx->ifc_sctx; 3264 scctx = &ctx->ifc_softc_ctx; 3265 segs = txq->ift_segs; 3266 ntxd = txq->ift_size; 3267 m_head = *m_headp; 3268 map = NULL; 3269 3270 /* 3271 * If we're doing TSO the next descriptor to clean may be quite far ahead 3272 */ 3273 cidx = txq->ift_cidx; 3274 pidx = txq->ift_pidx; 3275 if (ctx->ifc_flags & IFC_PREFETCH) { 3276 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3277 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3278 next_txd = calc_next_txd(txq, cidx, 0); 3279 prefetch(next_txd); 3280 } 3281 3282 /* prefetch the next cache line of mbuf pointers and flags */ 3283 prefetch(&txq->ift_sds.ifsd_m[next]); 3284 prefetch(&txq->ift_sds.ifsd_map[next]); 3285 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3286 } 3287 map = txq->ift_sds.ifsd_map[pidx]; 3288 ifsd_m = txq->ift_sds.ifsd_m; 3289 3290 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3291 buf_tag = txq->ift_tso_buf_tag; 3292 max_segs = scctx->isc_tx_tso_segments_max; 3293 map = txq->ift_sds.ifsd_tso_map[pidx]; 3294 MPASS(buf_tag != NULL); 3295 MPASS(max_segs > 0); 3296 } else { 3297 buf_tag = txq->ift_buf_tag; 3298 max_segs = scctx->isc_tx_nsegments; 3299 map = txq->ift_sds.ifsd_map[pidx]; 3300 } 3301 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3302 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3303 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3304 if (err) { 3305 DBG_COUNTER_INC(encap_txd_encap_fail); 3306 return err; 3307 } 3308 } 3309 m_head = *m_headp; 3310 3311 pkt_info_zero(&pi); 3312 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3313 pi.ipi_pidx = pidx; 3314 pi.ipi_qsidx = txq->ift_id; 3315 pi.ipi_len = m_head->m_pkthdr.len; 3316 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3317 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3318 3319 /* deliberate bitwise OR to make one condition */ 3320 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3321 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3322 DBG_COUNTER_INC(encap_txd_encap_fail); 3323 return (err); 3324 } 3325 m_head = *m_headp; 3326 } 3327 3328 retry: 3329 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3330 BUS_DMA_NOWAIT); 3331 defrag: 3332 if (__predict_false(err)) { 3333 switch (err) { 3334 case EFBIG: 3335 /* try collapse once and defrag once */ 3336 if (remap == 0) { 3337 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3338 /* try defrag if collapsing fails */ 3339 if (m_head == NULL) 3340 remap++; 3341 } 3342 if (remap == 1) { 3343 txq->ift_mbuf_defrag++; 3344 m_head = m_defrag(*m_headp, M_NOWAIT); 3345 } 3346 /* 3347 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3348 * failed to map an mbuf that was run through m_defrag 3349 */ 3350 MPASS(remap <= 1); 3351 if (__predict_false(m_head == NULL || remap > 1)) 3352 goto defrag_failed; 3353 remap++; 3354 *m_headp = m_head; 3355 goto retry; 3356 break; 3357 case ENOMEM: 3358 txq->ift_no_tx_dma_setup++; 3359 break; 3360 default: 3361 txq->ift_no_tx_dma_setup++; 3362 m_freem(*m_headp); 3363 DBG_COUNTER_INC(tx_frees); 3364 *m_headp = NULL; 3365 break; 3366 } 3367 txq->ift_map_failed++; 3368 DBG_COUNTER_INC(encap_load_mbuf_fail); 3369 DBG_COUNTER_INC(encap_txd_encap_fail); 3370 return (err); 3371 } 3372 ifsd_m[pidx] = m_head; 3373 /* 3374 * XXX assumes a 1 to 1 relationship between segments and 3375 * descriptors - this does not hold true on all drivers, e.g. 3376 * cxgb 3377 */ 3378 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3379 txq->ift_no_desc_avail++; 3380 bus_dmamap_unload(buf_tag, map); 3381 DBG_COUNTER_INC(encap_txq_avail_fail); 3382 DBG_COUNTER_INC(encap_txd_encap_fail); 3383 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3384 GROUPTASK_ENQUEUE(&txq->ift_task); 3385 return (ENOBUFS); 3386 } 3387 /* 3388 * On Intel cards we can greatly reduce the number of TX interrupts 3389 * we see by only setting report status on every Nth descriptor. 3390 * However, this also means that the driver will need to keep track 3391 * of the descriptors that RS was set on to check them for the DD bit. 3392 */ 3393 txq->ift_rs_pending += nsegs + 1; 3394 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3395 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3396 pi.ipi_flags |= IPI_TX_INTR; 3397 txq->ift_rs_pending = 0; 3398 } 3399 3400 pi.ipi_segs = segs; 3401 pi.ipi_nsegs = nsegs; 3402 3403 MPASS(pidx >= 0 && pidx < txq->ift_size); 3404 #ifdef PKT_DEBUG 3405 print_pkt(&pi); 3406 #endif 3407 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3408 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3409 DBG_COUNTER_INC(tx_encap); 3410 MPASS(pi.ipi_new_pidx < txq->ift_size); 3411 3412 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3413 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3414 ndesc += txq->ift_size; 3415 txq->ift_gen = 1; 3416 } 3417 /* 3418 * drivers can need as many as 3419 * two sentinels 3420 */ 3421 MPASS(ndesc <= pi.ipi_nsegs + 2); 3422 MPASS(pi.ipi_new_pidx != pidx); 3423 MPASS(ndesc > 0); 3424 txq->ift_in_use += ndesc; 3425 3426 /* 3427 * We update the last software descriptor again here because there may 3428 * be a sentinel and/or there may be more mbufs than segments 3429 */ 3430 txq->ift_pidx = pi.ipi_new_pidx; 3431 txq->ift_npending += pi.ipi_ndescs; 3432 } else { 3433 *m_headp = m_head = iflib_remove_mbuf(txq); 3434 if (err == EFBIG) { 3435 txq->ift_txd_encap_efbig++; 3436 if (remap < 2) { 3437 remap = 1; 3438 goto defrag; 3439 } 3440 } 3441 goto defrag_failed; 3442 } 3443 /* 3444 * err can't possibly be non-zero here, so we don't neet to test it 3445 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3446 */ 3447 return (err); 3448 3449 defrag_failed: 3450 txq->ift_mbuf_defrag_failed++; 3451 txq->ift_map_failed++; 3452 m_freem(*m_headp); 3453 DBG_COUNTER_INC(tx_frees); 3454 *m_headp = NULL; 3455 DBG_COUNTER_INC(encap_txd_encap_fail); 3456 return (ENOMEM); 3457 } 3458 3459 static void 3460 iflib_tx_desc_free(iflib_txq_t txq, int n) 3461 { 3462 uint32_t qsize, cidx, mask, gen; 3463 struct mbuf *m, **ifsd_m; 3464 bool do_prefetch; 3465 3466 cidx = txq->ift_cidx; 3467 gen = txq->ift_gen; 3468 qsize = txq->ift_size; 3469 mask = qsize-1; 3470 ifsd_m = txq->ift_sds.ifsd_m; 3471 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3472 3473 while (n-- > 0) { 3474 if (do_prefetch) { 3475 prefetch(ifsd_m[(cidx + 3) & mask]); 3476 prefetch(ifsd_m[(cidx + 4) & mask]); 3477 } 3478 if ((m = ifsd_m[cidx]) != NULL) { 3479 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3480 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3481 bus_dmamap_sync(txq->ift_tso_buf_tag, 3482 txq->ift_sds.ifsd_tso_map[cidx], 3483 BUS_DMASYNC_POSTWRITE); 3484 bus_dmamap_unload(txq->ift_tso_buf_tag, 3485 txq->ift_sds.ifsd_tso_map[cidx]); 3486 } else { 3487 bus_dmamap_sync(txq->ift_buf_tag, 3488 txq->ift_sds.ifsd_map[cidx], 3489 BUS_DMASYNC_POSTWRITE); 3490 bus_dmamap_unload(txq->ift_buf_tag, 3491 txq->ift_sds.ifsd_map[cidx]); 3492 } 3493 /* XXX we don't support any drivers that batch packets yet */ 3494 MPASS(m->m_nextpkt == NULL); 3495 m_freem(m); 3496 ifsd_m[cidx] = NULL; 3497 #if MEMORY_LOGGING 3498 txq->ift_dequeued++; 3499 #endif 3500 DBG_COUNTER_INC(tx_frees); 3501 } 3502 if (__predict_false(++cidx == qsize)) { 3503 cidx = 0; 3504 gen = 0; 3505 } 3506 } 3507 txq->ift_cidx = cidx; 3508 txq->ift_gen = gen; 3509 } 3510 3511 static __inline int 3512 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3513 { 3514 int reclaim; 3515 if_ctx_t ctx = txq->ift_ctx; 3516 3517 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3518 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3519 3520 /* 3521 * Need a rate-limiting check so that this isn't called every time 3522 */ 3523 iflib_tx_credits_update(ctx, txq); 3524 reclaim = DESC_RECLAIMABLE(txq); 3525 3526 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3527 #ifdef INVARIANTS 3528 if (iflib_verbose_debug) { 3529 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3530 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3531 reclaim, thresh); 3532 3533 } 3534 #endif 3535 return (0); 3536 } 3537 iflib_tx_desc_free(txq, reclaim); 3538 txq->ift_cleaned += reclaim; 3539 txq->ift_in_use -= reclaim; 3540 3541 return (reclaim); 3542 } 3543 3544 static struct mbuf ** 3545 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3546 { 3547 int next, size; 3548 struct mbuf **items; 3549 3550 size = r->size; 3551 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3552 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3553 3554 prefetch(items[(cidx + offset) & (size-1)]); 3555 if (remaining > 1) { 3556 prefetch2cachelines(&items[next]); 3557 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3558 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3559 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3560 } 3561 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3562 } 3563 3564 static void 3565 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3566 { 3567 3568 ifmp_ring_check_drainage(txq->ift_br, budget); 3569 } 3570 3571 static uint32_t 3572 iflib_txq_can_drain(struct ifmp_ring *r) 3573 { 3574 iflib_txq_t txq = r->cookie; 3575 if_ctx_t ctx = txq->ift_ctx; 3576 3577 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3578 return (1); 3579 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3580 BUS_DMASYNC_POSTREAD); 3581 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3582 false)); 3583 } 3584 3585 static uint32_t 3586 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3587 { 3588 iflib_txq_t txq = r->cookie; 3589 if_ctx_t ctx = txq->ift_ctx; 3590 if_t ifp = ctx->ifc_ifp; 3591 struct mbuf *m, **mp; 3592 int avail, bytes_sent, consumed, count, err, i, in_use_prev; 3593 int mcast_sent, pkt_sent, reclaimed, txq_avail; 3594 bool do_prefetch, rang, ring; 3595 3596 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3597 !LINK_ACTIVE(ctx))) { 3598 DBG_COUNTER_INC(txq_drain_notready); 3599 return (0); 3600 } 3601 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3602 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3603 avail = IDXDIFF(pidx, cidx, r->size); 3604 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3605 DBG_COUNTER_INC(txq_drain_flushing); 3606 for (i = 0; i < avail; i++) { 3607 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3608 m_free(r->items[(cidx + i) & (r->size-1)]); 3609 r->items[(cidx + i) & (r->size-1)] = NULL; 3610 } 3611 return (avail); 3612 } 3613 3614 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3615 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3616 CALLOUT_LOCK(txq); 3617 callout_stop(&txq->ift_timer); 3618 CALLOUT_UNLOCK(txq); 3619 DBG_COUNTER_INC(txq_drain_oactive); 3620 return (0); 3621 } 3622 if (reclaimed) 3623 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3624 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3625 count = MIN(avail, TX_BATCH_SIZE); 3626 #ifdef INVARIANTS 3627 if (iflib_verbose_debug) 3628 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3629 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3630 #endif 3631 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3632 txq_avail = TXQ_AVAIL(txq); 3633 err = 0; 3634 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) { 3635 int rem = do_prefetch ? count - i : 0; 3636 3637 mp = _ring_peek_one(r, cidx, i, rem); 3638 MPASS(mp != NULL && *mp != NULL); 3639 if (__predict_false(*mp == (struct mbuf *)txq)) { 3640 consumed++; 3641 continue; 3642 } 3643 in_use_prev = txq->ift_in_use; 3644 err = iflib_encap(txq, mp); 3645 if (__predict_false(err)) { 3646 /* no room - bail out */ 3647 if (err == ENOBUFS) 3648 break; 3649 consumed++; 3650 /* we can't send this packet - skip it */ 3651 continue; 3652 } 3653 consumed++; 3654 pkt_sent++; 3655 m = *mp; 3656 DBG_COUNTER_INC(tx_sent); 3657 bytes_sent += m->m_pkthdr.len; 3658 mcast_sent += !!(m->m_flags & M_MCAST); 3659 txq_avail = TXQ_AVAIL(txq); 3660 3661 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3662 ETHER_BPF_MTAP(ifp, m); 3663 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3664 break; 3665 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3666 } 3667 3668 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3669 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3670 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3671 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3672 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3673 if (mcast_sent) 3674 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3675 #ifdef INVARIANTS 3676 if (iflib_verbose_debug) 3677 printf("consumed=%d\n", consumed); 3678 #endif 3679 return (consumed); 3680 } 3681 3682 static uint32_t 3683 iflib_txq_drain_always(struct ifmp_ring *r) 3684 { 3685 return (1); 3686 } 3687 3688 static uint32_t 3689 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3690 { 3691 int i, avail; 3692 struct mbuf **mp; 3693 iflib_txq_t txq; 3694 3695 txq = r->cookie; 3696 3697 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3698 CALLOUT_LOCK(txq); 3699 callout_stop(&txq->ift_timer); 3700 CALLOUT_UNLOCK(txq); 3701 3702 avail = IDXDIFF(pidx, cidx, r->size); 3703 for (i = 0; i < avail; i++) { 3704 mp = _ring_peek_one(r, cidx, i, avail - i); 3705 if (__predict_false(*mp == (struct mbuf *)txq)) 3706 continue; 3707 m_freem(*mp); 3708 DBG_COUNTER_INC(tx_frees); 3709 } 3710 MPASS(ifmp_ring_is_stalled(r) == 0); 3711 return (avail); 3712 } 3713 3714 static void 3715 iflib_ifmp_purge(iflib_txq_t txq) 3716 { 3717 struct ifmp_ring *r; 3718 3719 r = txq->ift_br; 3720 r->drain = iflib_txq_drain_free; 3721 r->can_drain = iflib_txq_drain_always; 3722 3723 ifmp_ring_check_drainage(r, r->size); 3724 3725 r->drain = iflib_txq_drain; 3726 r->can_drain = iflib_txq_can_drain; 3727 } 3728 3729 static void 3730 _task_fn_tx(void *context) 3731 { 3732 iflib_txq_t txq = context; 3733 if_ctx_t ctx = txq->ift_ctx; 3734 #if defined(ALTQ) || defined(DEV_NETMAP) 3735 if_t ifp = ctx->ifc_ifp; 3736 #endif 3737 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3738 3739 #ifdef IFLIB_DIAGNOSTICS 3740 txq->ift_cpu_exec_count[curcpu]++; 3741 #endif 3742 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3743 return; 3744 #ifdef DEV_NETMAP 3745 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3746 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3747 BUS_DMASYNC_POSTREAD); 3748 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3749 netmap_tx_irq(ifp, txq->ift_id); 3750 if (ctx->ifc_flags & IFC_LEGACY) 3751 IFDI_INTR_ENABLE(ctx); 3752 else 3753 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3754 return; 3755 } 3756 #endif 3757 #ifdef ALTQ 3758 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3759 iflib_altq_if_start(ifp); 3760 #endif 3761 if (txq->ift_db_pending) 3762 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3763 else if (!abdicate) 3764 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3765 /* 3766 * When abdicating, we always need to check drainage, not just when we don't enqueue 3767 */ 3768 if (abdicate) 3769 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3770 if (ctx->ifc_flags & IFC_LEGACY) 3771 IFDI_INTR_ENABLE(ctx); 3772 else 3773 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3774 } 3775 3776 static void 3777 _task_fn_rx(void *context) 3778 { 3779 iflib_rxq_t rxq = context; 3780 if_ctx_t ctx = rxq->ifr_ctx; 3781 bool more; 3782 uint16_t budget; 3783 3784 #ifdef IFLIB_DIAGNOSTICS 3785 rxq->ifr_cpu_exec_count[curcpu]++; 3786 #endif 3787 DBG_COUNTER_INC(task_fn_rxs); 3788 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3789 return; 3790 more = true; 3791 #ifdef DEV_NETMAP 3792 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3793 u_int work = 0; 3794 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3795 more = false; 3796 } 3797 } 3798 #endif 3799 budget = ctx->ifc_sysctl_rx_budget; 3800 if (budget == 0) 3801 budget = 16; /* XXX */ 3802 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3803 if (ctx->ifc_flags & IFC_LEGACY) 3804 IFDI_INTR_ENABLE(ctx); 3805 else 3806 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3807 DBG_COUNTER_INC(rx_intr_enables); 3808 } 3809 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3810 return; 3811 if (more) 3812 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3813 } 3814 3815 static void 3816 _task_fn_admin(void *context) 3817 { 3818 if_ctx_t ctx = context; 3819 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3820 iflib_txq_t txq; 3821 int i; 3822 bool oactive, running, do_reset, do_watchdog, in_detach; 3823 uint32_t reset_on = hz / 2; 3824 3825 STATE_LOCK(ctx); 3826 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3827 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3828 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3829 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3830 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3831 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3832 STATE_UNLOCK(ctx); 3833 3834 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3835 return; 3836 if (in_detach) 3837 return; 3838 3839 CTX_LOCK(ctx); 3840 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3841 CALLOUT_LOCK(txq); 3842 callout_stop(&txq->ift_timer); 3843 CALLOUT_UNLOCK(txq); 3844 } 3845 if (do_watchdog) { 3846 ctx->ifc_watchdog_events++; 3847 IFDI_WATCHDOG_RESET(ctx); 3848 } 3849 IFDI_UPDATE_ADMIN_STATUS(ctx); 3850 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3851 #ifdef DEV_NETMAP 3852 reset_on = hz / 2; 3853 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3854 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 3855 #endif 3856 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3857 } 3858 IFDI_LINK_INTR_ENABLE(ctx); 3859 if (do_reset) 3860 iflib_if_init_locked(ctx); 3861 CTX_UNLOCK(ctx); 3862 3863 if (LINK_ACTIVE(ctx) == 0) 3864 return; 3865 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3866 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3867 } 3868 3869 3870 static void 3871 _task_fn_iov(void *context) 3872 { 3873 if_ctx_t ctx = context; 3874 3875 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3876 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3877 return; 3878 3879 CTX_LOCK(ctx); 3880 IFDI_VFLR_HANDLE(ctx); 3881 CTX_UNLOCK(ctx); 3882 } 3883 3884 static int 3885 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3886 { 3887 int err; 3888 if_int_delay_info_t info; 3889 if_ctx_t ctx; 3890 3891 info = (if_int_delay_info_t)arg1; 3892 ctx = info->iidi_ctx; 3893 info->iidi_req = req; 3894 info->iidi_oidp = oidp; 3895 CTX_LOCK(ctx); 3896 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3897 CTX_UNLOCK(ctx); 3898 return (err); 3899 } 3900 3901 /********************************************************************* 3902 * 3903 * IFNET FUNCTIONS 3904 * 3905 **********************************************************************/ 3906 3907 static void 3908 iflib_if_init_locked(if_ctx_t ctx) 3909 { 3910 iflib_stop(ctx); 3911 iflib_init_locked(ctx); 3912 } 3913 3914 3915 static void 3916 iflib_if_init(void *arg) 3917 { 3918 if_ctx_t ctx = arg; 3919 3920 CTX_LOCK(ctx); 3921 iflib_if_init_locked(ctx); 3922 CTX_UNLOCK(ctx); 3923 } 3924 3925 static int 3926 iflib_if_transmit(if_t ifp, struct mbuf *m) 3927 { 3928 if_ctx_t ctx = if_getsoftc(ifp); 3929 3930 iflib_txq_t txq; 3931 int err, qidx; 3932 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3933 3934 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3935 DBG_COUNTER_INC(tx_frees); 3936 m_freem(m); 3937 return (ENETDOWN); 3938 } 3939 3940 MPASS(m->m_nextpkt == NULL); 3941 /* ALTQ-enabled interfaces always use queue 0. */ 3942 qidx = 0; 3943 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3944 qidx = QIDX(ctx, m); 3945 /* 3946 * XXX calculate buf_ring based on flowid (divvy up bits?) 3947 */ 3948 txq = &ctx->ifc_txqs[qidx]; 3949 3950 #ifdef DRIVER_BACKPRESSURE 3951 if (txq->ift_closed) { 3952 while (m != NULL) { 3953 next = m->m_nextpkt; 3954 m->m_nextpkt = NULL; 3955 m_freem(m); 3956 DBG_COUNTER_INC(tx_frees); 3957 m = next; 3958 } 3959 return (ENOBUFS); 3960 } 3961 #endif 3962 #ifdef notyet 3963 qidx = count = 0; 3964 mp = marr; 3965 next = m; 3966 do { 3967 count++; 3968 next = next->m_nextpkt; 3969 } while (next != NULL); 3970 3971 if (count > nitems(marr)) 3972 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3973 /* XXX check nextpkt */ 3974 m_freem(m); 3975 /* XXX simplify for now */ 3976 DBG_COUNTER_INC(tx_frees); 3977 return (ENOBUFS); 3978 } 3979 for (next = m, i = 0; next != NULL; i++) { 3980 mp[i] = next; 3981 next = next->m_nextpkt; 3982 mp[i]->m_nextpkt = NULL; 3983 } 3984 #endif 3985 DBG_COUNTER_INC(tx_seen); 3986 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 3987 3988 if (abdicate) 3989 GROUPTASK_ENQUEUE(&txq->ift_task); 3990 if (err) { 3991 if (!abdicate) 3992 GROUPTASK_ENQUEUE(&txq->ift_task); 3993 /* support forthcoming later */ 3994 #ifdef DRIVER_BACKPRESSURE 3995 txq->ift_closed = TRUE; 3996 #endif 3997 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3998 m_freem(m); 3999 DBG_COUNTER_INC(tx_frees); 4000 } 4001 4002 return (err); 4003 } 4004 4005 #ifdef ALTQ 4006 /* 4007 * The overall approach to integrating iflib with ALTQ is to continue to use 4008 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4009 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4010 * is redundant/unnecessary, but doing so minimizes the amount of 4011 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4012 * redundantly queueing to an intermediate mp_ring is swamped by the 4013 * performance limitations inherent in using ALTQ. 4014 * 4015 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4016 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4017 * given interface. If ALTQ is enabled for an interface, then all 4018 * transmitted packets for that interface will be submitted to the ALTQ 4019 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4020 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4021 * update stats that the iflib machinery handles, and which is sensitve to 4022 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4023 * will be installed as the start routine for use by ALTQ facilities that 4024 * need to trigger queue drains on a scheduled basis. 4025 * 4026 */ 4027 static void 4028 iflib_altq_if_start(if_t ifp) 4029 { 4030 struct ifaltq *ifq = &ifp->if_snd; 4031 struct mbuf *m; 4032 4033 IFQ_LOCK(ifq); 4034 IFQ_DEQUEUE_NOLOCK(ifq, m); 4035 while (m != NULL) { 4036 iflib_if_transmit(ifp, m); 4037 IFQ_DEQUEUE_NOLOCK(ifq, m); 4038 } 4039 IFQ_UNLOCK(ifq); 4040 } 4041 4042 static int 4043 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4044 { 4045 int err; 4046 4047 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4048 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4049 if (err == 0) 4050 iflib_altq_if_start(ifp); 4051 } else 4052 err = iflib_if_transmit(ifp, m); 4053 4054 return (err); 4055 } 4056 #endif /* ALTQ */ 4057 4058 static void 4059 iflib_if_qflush(if_t ifp) 4060 { 4061 if_ctx_t ctx = if_getsoftc(ifp); 4062 iflib_txq_t txq = ctx->ifc_txqs; 4063 int i; 4064 4065 STATE_LOCK(ctx); 4066 ctx->ifc_flags |= IFC_QFLUSH; 4067 STATE_UNLOCK(ctx); 4068 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4069 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4070 iflib_txq_check_drain(txq, 0); 4071 STATE_LOCK(ctx); 4072 ctx->ifc_flags &= ~IFC_QFLUSH; 4073 STATE_UNLOCK(ctx); 4074 4075 /* 4076 * When ALTQ is enabled, this will also take care of purging the 4077 * ALTQ queue(s). 4078 */ 4079 if_qflush(ifp); 4080 } 4081 4082 4083 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4084 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4085 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4086 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP) 4087 4088 static int 4089 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4090 { 4091 if_ctx_t ctx = if_getsoftc(ifp); 4092 struct ifreq *ifr = (struct ifreq *)data; 4093 #if defined(INET) || defined(INET6) 4094 struct ifaddr *ifa = (struct ifaddr *)data; 4095 #endif 4096 bool avoid_reset = false; 4097 int err = 0, reinit = 0, bits; 4098 4099 switch (command) { 4100 case SIOCSIFADDR: 4101 #ifdef INET 4102 if (ifa->ifa_addr->sa_family == AF_INET) 4103 avoid_reset = true; 4104 #endif 4105 #ifdef INET6 4106 if (ifa->ifa_addr->sa_family == AF_INET6) 4107 avoid_reset = true; 4108 #endif 4109 /* 4110 ** Calling init results in link renegotiation, 4111 ** so we avoid doing it when possible. 4112 */ 4113 if (avoid_reset) { 4114 if_setflagbits(ifp, IFF_UP,0); 4115 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4116 reinit = 1; 4117 #ifdef INET 4118 if (!(if_getflags(ifp) & IFF_NOARP)) 4119 arp_ifinit(ifp, ifa); 4120 #endif 4121 } else 4122 err = ether_ioctl(ifp, command, data); 4123 break; 4124 case SIOCSIFMTU: 4125 CTX_LOCK(ctx); 4126 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4127 CTX_UNLOCK(ctx); 4128 break; 4129 } 4130 bits = if_getdrvflags(ifp); 4131 /* stop the driver and free any clusters before proceeding */ 4132 iflib_stop(ctx); 4133 4134 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4135 STATE_LOCK(ctx); 4136 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4137 ctx->ifc_flags |= IFC_MULTISEG; 4138 else 4139 ctx->ifc_flags &= ~IFC_MULTISEG; 4140 STATE_UNLOCK(ctx); 4141 err = if_setmtu(ifp, ifr->ifr_mtu); 4142 } 4143 iflib_init_locked(ctx); 4144 STATE_LOCK(ctx); 4145 if_setdrvflags(ifp, bits); 4146 STATE_UNLOCK(ctx); 4147 CTX_UNLOCK(ctx); 4148 break; 4149 case SIOCSIFFLAGS: 4150 CTX_LOCK(ctx); 4151 if (if_getflags(ifp) & IFF_UP) { 4152 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4153 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4154 (IFF_PROMISC | IFF_ALLMULTI)) { 4155 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4156 } 4157 } else 4158 reinit = 1; 4159 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4160 iflib_stop(ctx); 4161 } 4162 ctx->ifc_if_flags = if_getflags(ifp); 4163 CTX_UNLOCK(ctx); 4164 break; 4165 case SIOCADDMULTI: 4166 case SIOCDELMULTI: 4167 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4168 CTX_LOCK(ctx); 4169 IFDI_INTR_DISABLE(ctx); 4170 IFDI_MULTI_SET(ctx); 4171 IFDI_INTR_ENABLE(ctx); 4172 CTX_UNLOCK(ctx); 4173 } 4174 break; 4175 case SIOCSIFMEDIA: 4176 CTX_LOCK(ctx); 4177 IFDI_MEDIA_SET(ctx); 4178 CTX_UNLOCK(ctx); 4179 /* FALLTHROUGH */ 4180 case SIOCGIFMEDIA: 4181 case SIOCGIFXMEDIA: 4182 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4183 break; 4184 case SIOCGI2C: 4185 { 4186 struct ifi2creq i2c; 4187 4188 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4189 if (err != 0) 4190 break; 4191 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4192 err = EINVAL; 4193 break; 4194 } 4195 if (i2c.len > sizeof(i2c.data)) { 4196 err = EINVAL; 4197 break; 4198 } 4199 4200 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4201 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4202 sizeof(i2c)); 4203 break; 4204 } 4205 case SIOCSIFCAP: 4206 { 4207 int mask, setmask, oldmask; 4208 4209 oldmask = if_getcapenable(ifp); 4210 mask = ifr->ifr_reqcap ^ oldmask; 4211 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP; 4212 setmask = 0; 4213 #ifdef TCP_OFFLOAD 4214 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4215 #endif 4216 setmask |= (mask & IFCAP_FLAGS); 4217 setmask |= (mask & IFCAP_WOL); 4218 4219 /* 4220 * If any RX csum has changed, change all the ones that 4221 * are supported by the driver. 4222 */ 4223 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4224 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4225 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4226 } 4227 4228 /* 4229 * want to ensure that traffic has stopped before we change any of the flags 4230 */ 4231 if (setmask) { 4232 CTX_LOCK(ctx); 4233 bits = if_getdrvflags(ifp); 4234 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4235 iflib_stop(ctx); 4236 STATE_LOCK(ctx); 4237 if_togglecapenable(ifp, setmask); 4238 STATE_UNLOCK(ctx); 4239 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4240 iflib_init_locked(ctx); 4241 STATE_LOCK(ctx); 4242 if_setdrvflags(ifp, bits); 4243 STATE_UNLOCK(ctx); 4244 CTX_UNLOCK(ctx); 4245 } 4246 if_vlancap(ifp); 4247 break; 4248 } 4249 case SIOCGPRIVATE_0: 4250 case SIOCSDRVSPEC: 4251 case SIOCGDRVSPEC: 4252 CTX_LOCK(ctx); 4253 err = IFDI_PRIV_IOCTL(ctx, command, data); 4254 CTX_UNLOCK(ctx); 4255 break; 4256 default: 4257 err = ether_ioctl(ifp, command, data); 4258 break; 4259 } 4260 if (reinit) 4261 iflib_if_init(ctx); 4262 return (err); 4263 } 4264 4265 static uint64_t 4266 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4267 { 4268 if_ctx_t ctx = if_getsoftc(ifp); 4269 4270 return (IFDI_GET_COUNTER(ctx, cnt)); 4271 } 4272 4273 /********************************************************************* 4274 * 4275 * OTHER FUNCTIONS EXPORTED TO THE STACK 4276 * 4277 **********************************************************************/ 4278 4279 static void 4280 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4281 { 4282 if_ctx_t ctx = if_getsoftc(ifp); 4283 4284 if ((void *)ctx != arg) 4285 return; 4286 4287 if ((vtag == 0) || (vtag > 4095)) 4288 return; 4289 4290 if (iflib_in_detach(ctx)) 4291 return; 4292 4293 CTX_LOCK(ctx); 4294 IFDI_VLAN_REGISTER(ctx, vtag); 4295 /* Re-init to load the changes */ 4296 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4297 iflib_if_init_locked(ctx); 4298 CTX_UNLOCK(ctx); 4299 } 4300 4301 static void 4302 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4303 { 4304 if_ctx_t ctx = if_getsoftc(ifp); 4305 4306 if ((void *)ctx != arg) 4307 return; 4308 4309 if ((vtag == 0) || (vtag > 4095)) 4310 return; 4311 4312 CTX_LOCK(ctx); 4313 IFDI_VLAN_UNREGISTER(ctx, vtag); 4314 /* Re-init to load the changes */ 4315 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4316 iflib_if_init_locked(ctx); 4317 CTX_UNLOCK(ctx); 4318 } 4319 4320 static void 4321 iflib_led_func(void *arg, int onoff) 4322 { 4323 if_ctx_t ctx = arg; 4324 4325 CTX_LOCK(ctx); 4326 IFDI_LED_FUNC(ctx, onoff); 4327 CTX_UNLOCK(ctx); 4328 } 4329 4330 /********************************************************************* 4331 * 4332 * BUS FUNCTION DEFINITIONS 4333 * 4334 **********************************************************************/ 4335 4336 int 4337 iflib_device_probe(device_t dev) 4338 { 4339 const pci_vendor_info_t *ent; 4340 if_shared_ctx_t sctx; 4341 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4342 uint16_t pci_vendor_id; 4343 4344 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4345 return (ENOTSUP); 4346 4347 pci_vendor_id = pci_get_vendor(dev); 4348 pci_device_id = pci_get_device(dev); 4349 pci_subvendor_id = pci_get_subvendor(dev); 4350 pci_subdevice_id = pci_get_subdevice(dev); 4351 pci_rev_id = pci_get_revid(dev); 4352 if (sctx->isc_parse_devinfo != NULL) 4353 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4354 4355 ent = sctx->isc_vendor_info; 4356 while (ent->pvi_vendor_id != 0) { 4357 if (pci_vendor_id != ent->pvi_vendor_id) { 4358 ent++; 4359 continue; 4360 } 4361 if ((pci_device_id == ent->pvi_device_id) && 4362 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4363 (ent->pvi_subvendor_id == 0)) && 4364 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4365 (ent->pvi_subdevice_id == 0)) && 4366 ((pci_rev_id == ent->pvi_rev_id) || 4367 (ent->pvi_rev_id == 0))) { 4368 4369 device_set_desc_copy(dev, ent->pvi_name); 4370 /* this needs to be changed to zero if the bus probing code 4371 * ever stops re-probing on best match because the sctx 4372 * may have its values over written by register calls 4373 * in subsequent probes 4374 */ 4375 return (BUS_PROBE_DEFAULT); 4376 } 4377 ent++; 4378 } 4379 return (ENXIO); 4380 } 4381 4382 int 4383 iflib_device_probe_vendor(device_t dev) 4384 { 4385 int probe; 4386 4387 probe = iflib_device_probe(dev); 4388 if (probe == BUS_PROBE_DEFAULT) 4389 return (BUS_PROBE_VENDOR); 4390 else 4391 return (probe); 4392 } 4393 4394 static void 4395 iflib_reset_qvalues(if_ctx_t ctx) 4396 { 4397 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4398 if_shared_ctx_t sctx = ctx->ifc_sctx; 4399 device_t dev = ctx->ifc_dev; 4400 int i; 4401 4402 if (ctx->ifc_sysctl_ntxqs != 0) 4403 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4404 if (ctx->ifc_sysctl_nrxqs != 0) 4405 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4406 4407 for (i = 0; i < sctx->isc_ntxqs; i++) { 4408 if (ctx->ifc_sysctl_ntxds[i] != 0) 4409 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4410 else 4411 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4412 } 4413 4414 for (i = 0; i < sctx->isc_nrxqs; i++) { 4415 if (ctx->ifc_sysctl_nrxds[i] != 0) 4416 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4417 else 4418 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4419 } 4420 4421 for (i = 0; i < sctx->isc_nrxqs; i++) { 4422 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4423 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4424 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4425 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4426 } 4427 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4428 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4429 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4430 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4431 } 4432 if (!powerof2(scctx->isc_nrxd[i])) { 4433 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4434 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4435 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4436 } 4437 } 4438 4439 for (i = 0; i < sctx->isc_ntxqs; i++) { 4440 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4441 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4442 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4443 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4444 } 4445 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4446 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4447 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4448 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4449 } 4450 if (!powerof2(scctx->isc_ntxd[i])) { 4451 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4452 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4453 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4454 } 4455 } 4456 } 4457 4458 static void 4459 iflib_add_pfil(if_ctx_t ctx) 4460 { 4461 struct pfil_head *pfil; 4462 struct pfil_head_args pa; 4463 iflib_rxq_t rxq; 4464 int i; 4465 4466 pa.pa_version = PFIL_VERSION; 4467 pa.pa_flags = PFIL_IN; 4468 pa.pa_type = PFIL_TYPE_ETHERNET; 4469 pa.pa_headname = ctx->ifc_ifp->if_xname; 4470 pfil = pfil_head_register(&pa); 4471 4472 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4473 rxq->pfil = pfil; 4474 } 4475 } 4476 4477 static void 4478 iflib_rem_pfil(if_ctx_t ctx) 4479 { 4480 struct pfil_head *pfil; 4481 iflib_rxq_t rxq; 4482 int i; 4483 4484 rxq = ctx->ifc_rxqs; 4485 pfil = rxq->pfil; 4486 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4487 rxq->pfil = NULL; 4488 } 4489 pfil_head_unregister(pfil); 4490 } 4491 4492 static uint16_t 4493 get_ctx_core_offset(if_ctx_t ctx) 4494 { 4495 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4496 struct cpu_offset *op; 4497 uint16_t qc; 4498 uint16_t ret = ctx->ifc_sysctl_core_offset; 4499 4500 if (ret != CORE_OFFSET_UNSPECIFIED) 4501 return (ret); 4502 4503 if (ctx->ifc_sysctl_separate_txrx) 4504 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets; 4505 else 4506 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets); 4507 4508 mtx_lock(&cpu_offset_mtx); 4509 SLIST_FOREACH(op, &cpu_offsets, entries) { 4510 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4511 ret = op->offset; 4512 op->offset += qc; 4513 MPASS(op->refcount < UINT_MAX); 4514 op->refcount++; 4515 break; 4516 } 4517 } 4518 if (ret == CORE_OFFSET_UNSPECIFIED) { 4519 ret = 0; 4520 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4521 M_NOWAIT | M_ZERO); 4522 if (op == NULL) { 4523 device_printf(ctx->ifc_dev, 4524 "allocation for cpu offset failed.\n"); 4525 } else { 4526 op->offset = qc; 4527 op->refcount = 1; 4528 CPU_COPY(&ctx->ifc_cpus, &op->set); 4529 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4530 } 4531 } 4532 mtx_unlock(&cpu_offset_mtx); 4533 4534 return (ret); 4535 } 4536 4537 static void 4538 unref_ctx_core_offset(if_ctx_t ctx) 4539 { 4540 struct cpu_offset *op, *top; 4541 4542 mtx_lock(&cpu_offset_mtx); 4543 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4544 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4545 MPASS(op->refcount > 0); 4546 op->refcount--; 4547 if (op->refcount == 0) { 4548 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4549 free(op, M_IFLIB); 4550 } 4551 break; 4552 } 4553 } 4554 mtx_unlock(&cpu_offset_mtx); 4555 } 4556 4557 int 4558 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4559 { 4560 if_ctx_t ctx; 4561 if_t ifp; 4562 if_softc_ctx_t scctx; 4563 kobjop_desc_t kobj_desc; 4564 kobj_method_t *kobj_method; 4565 int err, msix, rid; 4566 uint16_t main_rxq, main_txq; 4567 4568 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4569 4570 if (sc == NULL) { 4571 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4572 device_set_softc(dev, ctx); 4573 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4574 } 4575 4576 ctx->ifc_sctx = sctx; 4577 ctx->ifc_dev = dev; 4578 ctx->ifc_softc = sc; 4579 4580 if ((err = iflib_register(ctx)) != 0) { 4581 device_printf(dev, "iflib_register failed %d\n", err); 4582 goto fail_ctx_free; 4583 } 4584 iflib_add_device_sysctl_pre(ctx); 4585 4586 scctx = &ctx->ifc_softc_ctx; 4587 ifp = ctx->ifc_ifp; 4588 4589 iflib_reset_qvalues(ctx); 4590 CTX_LOCK(ctx); 4591 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4592 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4593 goto fail_unlock; 4594 } 4595 _iflib_pre_assert(scctx); 4596 ctx->ifc_txrx = *scctx->isc_txrx; 4597 4598 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 4599 ctx->ifc_mediap = scctx->isc_media; 4600 4601 #ifdef INVARIANTS 4602 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4603 MPASS(scctx->isc_tx_csum_flags); 4604 #endif 4605 4606 if_setcapabilities(ifp, 4607 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP); 4608 if_setcapenable(ifp, 4609 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP); 4610 4611 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4612 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4613 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4614 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4615 4616 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4617 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4618 4619 /* XXX change for per-queue sizes */ 4620 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4621 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4622 4623 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4624 MAX_SINGLE_PACKET_FRACTION) 4625 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4626 MAX_SINGLE_PACKET_FRACTION); 4627 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4628 MAX_SINGLE_PACKET_FRACTION) 4629 scctx->isc_tx_tso_segments_max = max(1, 4630 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4631 4632 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4633 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4634 /* 4635 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4636 * but some MACs do. 4637 */ 4638 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4639 IP_MAXPACKET)); 4640 /* 4641 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4642 * into account. In the worst case, each of these calls will 4643 * add another mbuf and, thus, the requirement for another DMA 4644 * segment. So for best performance, it doesn't make sense to 4645 * advertize a maximum of TSO segments that typically will 4646 * require defragmentation in iflib_encap(). 4647 */ 4648 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4649 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4650 } 4651 if (scctx->isc_rss_table_size == 0) 4652 scctx->isc_rss_table_size = 64; 4653 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4654 4655 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4656 /* XXX format name */ 4657 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4658 NULL, NULL, "admin"); 4659 4660 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4661 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4662 device_printf(dev, "Unable to fetch CPU list\n"); 4663 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4664 } 4665 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4666 4667 /* 4668 ** Now set up MSI or MSI-X, should return us the number of supported 4669 ** vectors (will be 1 for a legacy interrupt and MSI). 4670 */ 4671 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4672 msix = scctx->isc_vectors; 4673 } else if (scctx->isc_msix_bar != 0) 4674 /* 4675 * The simple fact that isc_msix_bar is not 0 does not mean we 4676 * we have a good value there that is known to work. 4677 */ 4678 msix = iflib_msix_init(ctx); 4679 else { 4680 scctx->isc_vectors = 1; 4681 scctx->isc_ntxqsets = 1; 4682 scctx->isc_nrxqsets = 1; 4683 scctx->isc_intr = IFLIB_INTR_LEGACY; 4684 msix = 0; 4685 } 4686 /* Get memory for the station queues */ 4687 if ((err = iflib_queues_alloc(ctx))) { 4688 device_printf(dev, "Unable to allocate queue memory\n"); 4689 goto fail_intr_free; 4690 } 4691 4692 if ((err = iflib_qset_structures_setup(ctx))) 4693 goto fail_queues; 4694 4695 /* 4696 * Now that we know how many queues there are, get the core offset. 4697 */ 4698 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 4699 4700 /* 4701 * Group taskqueues aren't properly set up until SMP is started, 4702 * so we disable interrupts until we can handle them post 4703 * SI_SUB_SMP. 4704 * 4705 * XXX: disabling interrupts doesn't actually work, at least for 4706 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4707 * we do null handling and depend on this not causing too large an 4708 * interrupt storm. 4709 */ 4710 IFDI_INTR_DISABLE(ctx); 4711 4712 if (msix > 1) { 4713 /* 4714 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 4715 * aren't the default NULL implementation. 4716 */ 4717 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 4718 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4719 kobj_desc); 4720 if (kobj_method == &kobj_desc->deflt) { 4721 device_printf(dev, 4722 "MSI-X requires ifdi_rx_queue_intr_enable method"); 4723 err = EOPNOTSUPP; 4724 goto fail_queues; 4725 } 4726 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 4727 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4728 kobj_desc); 4729 if (kobj_method == &kobj_desc->deflt) { 4730 device_printf(dev, 4731 "MSI-X requires ifdi_tx_queue_intr_enable method"); 4732 err = EOPNOTSUPP; 4733 goto fail_queues; 4734 } 4735 4736 /* 4737 * Assign the MSI-X vectors. 4738 * Note that the default NULL ifdi_msix_intr_assign method will 4739 * fail here, too. 4740 */ 4741 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 4742 if (err != 0) { 4743 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 4744 err); 4745 goto fail_queues; 4746 } 4747 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 4748 rid = 0; 4749 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4750 MPASS(msix == 1); 4751 rid = 1; 4752 } 4753 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4754 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4755 goto fail_queues; 4756 } 4757 } else { 4758 device_printf(dev, 4759 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 4760 err = ENODEV; 4761 goto fail_intr_free; 4762 } 4763 4764 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4765 4766 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4767 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4768 goto fail_detach; 4769 } 4770 4771 /* 4772 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4773 * This must appear after the call to ether_ifattach() because 4774 * ether_ifattach() sets if_hdrlen to the default value. 4775 */ 4776 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4777 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4778 4779 if ((err = iflib_netmap_attach(ctx))) { 4780 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4781 goto fail_detach; 4782 } 4783 *ctxp = ctx; 4784 4785 DEBUGNET_SET(ctx->ifc_ifp, iflib); 4786 4787 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4788 iflib_add_device_sysctl_post(ctx); 4789 iflib_add_pfil(ctx); 4790 ctx->ifc_flags |= IFC_INIT_DONE; 4791 CTX_UNLOCK(ctx); 4792 4793 return (0); 4794 4795 fail_detach: 4796 ether_ifdetach(ctx->ifc_ifp); 4797 fail_intr_free: 4798 iflib_free_intr_mem(ctx); 4799 fail_queues: 4800 iflib_tx_structures_free(ctx); 4801 iflib_rx_structures_free(ctx); 4802 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task); 4803 IFDI_DETACH(ctx); 4804 fail_unlock: 4805 CTX_UNLOCK(ctx); 4806 iflib_deregister(ctx); 4807 fail_ctx_free: 4808 device_set_softc(ctx->ifc_dev, NULL); 4809 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4810 free(ctx->ifc_softc, M_IFLIB); 4811 free(ctx, M_IFLIB); 4812 return (err); 4813 } 4814 4815 int 4816 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4817 struct iflib_cloneattach_ctx *clctx) 4818 { 4819 int err; 4820 if_ctx_t ctx; 4821 if_t ifp; 4822 if_softc_ctx_t scctx; 4823 int i; 4824 void *sc; 4825 uint16_t main_txq; 4826 uint16_t main_rxq; 4827 4828 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4829 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4830 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4831 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4832 ctx->ifc_flags |= IFC_PSEUDO; 4833 4834 ctx->ifc_sctx = sctx; 4835 ctx->ifc_softc = sc; 4836 ctx->ifc_dev = dev; 4837 4838 if ((err = iflib_register(ctx)) != 0) { 4839 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4840 goto fail_ctx_free; 4841 } 4842 iflib_add_device_sysctl_pre(ctx); 4843 4844 scctx = &ctx->ifc_softc_ctx; 4845 ifp = ctx->ifc_ifp; 4846 4847 iflib_reset_qvalues(ctx); 4848 CTX_LOCK(ctx); 4849 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4850 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4851 goto fail_unlock; 4852 } 4853 if (sctx->isc_flags & IFLIB_GEN_MAC) 4854 ether_gen_addr(ifp, &ctx->ifc_mac); 4855 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4856 clctx->cc_params)) != 0) { 4857 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4858 goto fail_ctx_free; 4859 } 4860 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4861 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4862 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4863 4864 #ifdef INVARIANTS 4865 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4866 MPASS(scctx->isc_tx_csum_flags); 4867 #endif 4868 4869 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4870 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4871 4872 ifp->if_flags |= IFF_NOGROUP; 4873 if (sctx->isc_flags & IFLIB_PSEUDO) { 4874 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4875 4876 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4877 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4878 goto fail_detach; 4879 } 4880 *ctxp = ctx; 4881 4882 /* 4883 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4884 * This must appear after the call to ether_ifattach() because 4885 * ether_ifattach() sets if_hdrlen to the default value. 4886 */ 4887 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4888 if_setifheaderlen(ifp, 4889 sizeof(struct ether_vlan_header)); 4890 4891 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4892 iflib_add_device_sysctl_post(ctx); 4893 ctx->ifc_flags |= IFC_INIT_DONE; 4894 return (0); 4895 } 4896 _iflib_pre_assert(scctx); 4897 ctx->ifc_txrx = *scctx->isc_txrx; 4898 4899 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4900 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4901 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4902 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4903 4904 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4905 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4906 4907 /* XXX change for per-queue sizes */ 4908 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4909 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4910 4911 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4912 MAX_SINGLE_PACKET_FRACTION) 4913 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4914 MAX_SINGLE_PACKET_FRACTION); 4915 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4916 MAX_SINGLE_PACKET_FRACTION) 4917 scctx->isc_tx_tso_segments_max = max(1, 4918 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4919 4920 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4921 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4922 /* 4923 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4924 * but some MACs do. 4925 */ 4926 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4927 IP_MAXPACKET)); 4928 /* 4929 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4930 * into account. In the worst case, each of these calls will 4931 * add another mbuf and, thus, the requirement for another DMA 4932 * segment. So for best performance, it doesn't make sense to 4933 * advertize a maximum of TSO segments that typically will 4934 * require defragmentation in iflib_encap(). 4935 */ 4936 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4937 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4938 } 4939 if (scctx->isc_rss_table_size == 0) 4940 scctx->isc_rss_table_size = 64; 4941 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4942 4943 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4944 /* XXX format name */ 4945 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4946 NULL, NULL, "admin"); 4947 4948 /* XXX --- can support > 1 -- but keep it simple for now */ 4949 scctx->isc_intr = IFLIB_INTR_LEGACY; 4950 4951 /* Get memory for the station queues */ 4952 if ((err = iflib_queues_alloc(ctx))) { 4953 device_printf(dev, "Unable to allocate queue memory\n"); 4954 goto fail_iflib_detach; 4955 } 4956 4957 if ((err = iflib_qset_structures_setup(ctx))) { 4958 device_printf(dev, "qset structure setup failed %d\n", err); 4959 goto fail_queues; 4960 } 4961 4962 /* 4963 * XXX What if anything do we want to do about interrupts? 4964 */ 4965 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4966 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4967 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4968 goto fail_detach; 4969 } 4970 4971 /* 4972 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4973 * This must appear after the call to ether_ifattach() because 4974 * ether_ifattach() sets if_hdrlen to the default value. 4975 */ 4976 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4977 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4978 4979 /* XXX handle more than one queue */ 4980 for (i = 0; i < scctx->isc_nrxqsets; i++) 4981 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4982 4983 *ctxp = ctx; 4984 4985 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4986 iflib_add_device_sysctl_post(ctx); 4987 ctx->ifc_flags |= IFC_INIT_DONE; 4988 CTX_UNLOCK(ctx); 4989 4990 return (0); 4991 fail_detach: 4992 ether_ifdetach(ctx->ifc_ifp); 4993 fail_queues: 4994 iflib_tx_structures_free(ctx); 4995 iflib_rx_structures_free(ctx); 4996 fail_iflib_detach: 4997 IFDI_DETACH(ctx); 4998 fail_unlock: 4999 CTX_UNLOCK(ctx); 5000 iflib_deregister(ctx); 5001 fail_ctx_free: 5002 free(ctx->ifc_softc, M_IFLIB); 5003 free(ctx, M_IFLIB); 5004 return (err); 5005 } 5006 5007 int 5008 iflib_pseudo_deregister(if_ctx_t ctx) 5009 { 5010 if_t ifp = ctx->ifc_ifp; 5011 iflib_txq_t txq; 5012 iflib_rxq_t rxq; 5013 int i, j; 5014 struct taskqgroup *tqg; 5015 iflib_fl_t fl; 5016 5017 /* Unregister VLAN event handlers early */ 5018 iflib_unregister_vlan_handlers(ctx); 5019 5020 ether_ifdetach(ifp); 5021 /* XXX drain any dependent tasks */ 5022 tqg = qgroup_if_io_tqg; 5023 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5024 callout_drain(&txq->ift_timer); 5025 if (txq->ift_task.gt_uniq != NULL) 5026 taskqgroup_detach(tqg, &txq->ift_task); 5027 } 5028 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5029 if (rxq->ifr_task.gt_uniq != NULL) 5030 taskqgroup_detach(tqg, &rxq->ifr_task); 5031 5032 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5033 free(fl->ifl_rx_bitmap, M_IFLIB); 5034 } 5035 tqg = qgroup_if_config_tqg; 5036 if (ctx->ifc_admin_task.gt_uniq != NULL) 5037 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5038 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5039 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5040 5041 iflib_tx_structures_free(ctx); 5042 iflib_rx_structures_free(ctx); 5043 5044 iflib_deregister(ctx); 5045 5046 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5047 free(ctx->ifc_softc, M_IFLIB); 5048 free(ctx, M_IFLIB); 5049 return (0); 5050 } 5051 5052 int 5053 iflib_device_attach(device_t dev) 5054 { 5055 if_ctx_t ctx; 5056 if_shared_ctx_t sctx; 5057 5058 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5059 return (ENOTSUP); 5060 5061 pci_enable_busmaster(dev); 5062 5063 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5064 } 5065 5066 int 5067 iflib_device_deregister(if_ctx_t ctx) 5068 { 5069 if_t ifp = ctx->ifc_ifp; 5070 iflib_txq_t txq; 5071 iflib_rxq_t rxq; 5072 device_t dev = ctx->ifc_dev; 5073 int i, j; 5074 struct taskqgroup *tqg; 5075 iflib_fl_t fl; 5076 5077 /* Make sure VLANS are not using driver */ 5078 if (if_vlantrunkinuse(ifp)) { 5079 device_printf(dev, "Vlan in use, detach first\n"); 5080 return (EBUSY); 5081 } 5082 #ifdef PCI_IOV 5083 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5084 device_printf(dev, "SR-IOV in use; detach first.\n"); 5085 return (EBUSY); 5086 } 5087 #endif 5088 5089 STATE_LOCK(ctx); 5090 ctx->ifc_flags |= IFC_IN_DETACH; 5091 STATE_UNLOCK(ctx); 5092 5093 /* Unregister VLAN handlers before calling iflib_stop() */ 5094 iflib_unregister_vlan_handlers(ctx); 5095 5096 iflib_netmap_detach(ifp); 5097 ether_ifdetach(ifp); 5098 5099 CTX_LOCK(ctx); 5100 iflib_stop(ctx); 5101 CTX_UNLOCK(ctx); 5102 5103 iflib_rem_pfil(ctx); 5104 if (ctx->ifc_led_dev != NULL) 5105 led_destroy(ctx->ifc_led_dev); 5106 /* XXX drain any dependent tasks */ 5107 tqg = qgroup_if_io_tqg; 5108 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5109 callout_drain(&txq->ift_timer); 5110 if (txq->ift_task.gt_uniq != NULL) 5111 taskqgroup_detach(tqg, &txq->ift_task); 5112 } 5113 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5114 if (rxq->ifr_task.gt_uniq != NULL) 5115 taskqgroup_detach(tqg, &rxq->ifr_task); 5116 5117 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5118 free(fl->ifl_rx_bitmap, M_IFLIB); 5119 } 5120 tqg = qgroup_if_config_tqg; 5121 if (ctx->ifc_admin_task.gt_uniq != NULL) 5122 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5123 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5124 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5125 CTX_LOCK(ctx); 5126 IFDI_DETACH(ctx); 5127 CTX_UNLOCK(ctx); 5128 5129 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5130 iflib_free_intr_mem(ctx); 5131 5132 bus_generic_detach(dev); 5133 5134 iflib_tx_structures_free(ctx); 5135 iflib_rx_structures_free(ctx); 5136 5137 iflib_deregister(ctx); 5138 5139 device_set_softc(ctx->ifc_dev, NULL); 5140 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5141 free(ctx->ifc_softc, M_IFLIB); 5142 unref_ctx_core_offset(ctx); 5143 free(ctx, M_IFLIB); 5144 return (0); 5145 } 5146 5147 static void 5148 iflib_free_intr_mem(if_ctx_t ctx) 5149 { 5150 5151 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5152 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5153 } 5154 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5155 pci_release_msi(ctx->ifc_dev); 5156 } 5157 if (ctx->ifc_msix_mem != NULL) { 5158 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5159 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5160 ctx->ifc_msix_mem = NULL; 5161 } 5162 } 5163 5164 int 5165 iflib_device_detach(device_t dev) 5166 { 5167 if_ctx_t ctx = device_get_softc(dev); 5168 5169 return (iflib_device_deregister(ctx)); 5170 } 5171 5172 int 5173 iflib_device_suspend(device_t dev) 5174 { 5175 if_ctx_t ctx = device_get_softc(dev); 5176 5177 CTX_LOCK(ctx); 5178 IFDI_SUSPEND(ctx); 5179 CTX_UNLOCK(ctx); 5180 5181 return bus_generic_suspend(dev); 5182 } 5183 int 5184 iflib_device_shutdown(device_t dev) 5185 { 5186 if_ctx_t ctx = device_get_softc(dev); 5187 5188 CTX_LOCK(ctx); 5189 IFDI_SHUTDOWN(ctx); 5190 CTX_UNLOCK(ctx); 5191 5192 return bus_generic_suspend(dev); 5193 } 5194 5195 5196 int 5197 iflib_device_resume(device_t dev) 5198 { 5199 if_ctx_t ctx = device_get_softc(dev); 5200 iflib_txq_t txq = ctx->ifc_txqs; 5201 5202 CTX_LOCK(ctx); 5203 IFDI_RESUME(ctx); 5204 iflib_if_init_locked(ctx); 5205 CTX_UNLOCK(ctx); 5206 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5207 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5208 5209 return (bus_generic_resume(dev)); 5210 } 5211 5212 int 5213 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5214 { 5215 int error; 5216 if_ctx_t ctx = device_get_softc(dev); 5217 5218 CTX_LOCK(ctx); 5219 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5220 CTX_UNLOCK(ctx); 5221 5222 return (error); 5223 } 5224 5225 void 5226 iflib_device_iov_uninit(device_t dev) 5227 { 5228 if_ctx_t ctx = device_get_softc(dev); 5229 5230 CTX_LOCK(ctx); 5231 IFDI_IOV_UNINIT(ctx); 5232 CTX_UNLOCK(ctx); 5233 } 5234 5235 int 5236 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5237 { 5238 int error; 5239 if_ctx_t ctx = device_get_softc(dev); 5240 5241 CTX_LOCK(ctx); 5242 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5243 CTX_UNLOCK(ctx); 5244 5245 return (error); 5246 } 5247 5248 /********************************************************************* 5249 * 5250 * MODULE FUNCTION DEFINITIONS 5251 * 5252 **********************************************************************/ 5253 5254 /* 5255 * - Start a fast taskqueue thread for each core 5256 * - Start a taskqueue for control operations 5257 */ 5258 static int 5259 iflib_module_init(void) 5260 { 5261 return (0); 5262 } 5263 5264 static int 5265 iflib_module_event_handler(module_t mod, int what, void *arg) 5266 { 5267 int err; 5268 5269 switch (what) { 5270 case MOD_LOAD: 5271 if ((err = iflib_module_init()) != 0) 5272 return (err); 5273 break; 5274 case MOD_UNLOAD: 5275 return (EBUSY); 5276 default: 5277 return (EOPNOTSUPP); 5278 } 5279 5280 return (0); 5281 } 5282 5283 /********************************************************************* 5284 * 5285 * PUBLIC FUNCTION DEFINITIONS 5286 * ordered as in iflib.h 5287 * 5288 **********************************************************************/ 5289 5290 5291 static void 5292 _iflib_assert(if_shared_ctx_t sctx) 5293 { 5294 int i; 5295 5296 MPASS(sctx->isc_tx_maxsize); 5297 MPASS(sctx->isc_tx_maxsegsize); 5298 5299 MPASS(sctx->isc_rx_maxsize); 5300 MPASS(sctx->isc_rx_nsegments); 5301 MPASS(sctx->isc_rx_maxsegsize); 5302 5303 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5304 for (i = 0; i < sctx->isc_nrxqs; i++) { 5305 MPASS(sctx->isc_nrxd_min[i]); 5306 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5307 MPASS(sctx->isc_nrxd_max[i]); 5308 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5309 MPASS(sctx->isc_nrxd_default[i]); 5310 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5311 } 5312 5313 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5314 for (i = 0; i < sctx->isc_ntxqs; i++) { 5315 MPASS(sctx->isc_ntxd_min[i]); 5316 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5317 MPASS(sctx->isc_ntxd_max[i]); 5318 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5319 MPASS(sctx->isc_ntxd_default[i]); 5320 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5321 } 5322 } 5323 5324 static void 5325 _iflib_pre_assert(if_softc_ctx_t scctx) 5326 { 5327 5328 MPASS(scctx->isc_txrx->ift_txd_encap); 5329 MPASS(scctx->isc_txrx->ift_txd_flush); 5330 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5331 MPASS(scctx->isc_txrx->ift_rxd_available); 5332 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5333 MPASS(scctx->isc_txrx->ift_rxd_refill); 5334 MPASS(scctx->isc_txrx->ift_rxd_flush); 5335 } 5336 5337 static int 5338 iflib_register(if_ctx_t ctx) 5339 { 5340 if_shared_ctx_t sctx = ctx->ifc_sctx; 5341 driver_t *driver = sctx->isc_driver; 5342 device_t dev = ctx->ifc_dev; 5343 if_t ifp; 5344 5345 _iflib_assert(sctx); 5346 5347 CTX_LOCK_INIT(ctx); 5348 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5349 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5350 if (ifp == NULL) { 5351 device_printf(dev, "can not allocate ifnet structure\n"); 5352 return (ENOMEM); 5353 } 5354 5355 /* 5356 * Initialize our context's device specific methods 5357 */ 5358 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5359 kobj_class_compile((kobj_class_t) driver); 5360 5361 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5362 if_setsoftc(ifp, ctx); 5363 if_setdev(ifp, dev); 5364 if_setinitfn(ifp, iflib_if_init); 5365 if_setioctlfn(ifp, iflib_if_ioctl); 5366 #ifdef ALTQ 5367 if_setstartfn(ifp, iflib_altq_if_start); 5368 if_settransmitfn(ifp, iflib_altq_if_transmit); 5369 if_setsendqready(ifp); 5370 #else 5371 if_settransmitfn(ifp, iflib_if_transmit); 5372 #endif 5373 if_setqflushfn(ifp, iflib_if_qflush); 5374 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5375 5376 ctx->ifc_vlan_attach_event = 5377 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5378 EVENTHANDLER_PRI_FIRST); 5379 ctx->ifc_vlan_detach_event = 5380 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5381 EVENTHANDLER_PRI_FIRST); 5382 5383 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5384 ctx->ifc_mediap = &ctx->ifc_media; 5385 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5386 iflib_media_change, iflib_media_status); 5387 } 5388 return (0); 5389 } 5390 5391 static void 5392 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5393 { 5394 /* Unregister VLAN events */ 5395 if (ctx->ifc_vlan_attach_event != NULL) { 5396 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5397 ctx->ifc_vlan_attach_event = NULL; 5398 } 5399 if (ctx->ifc_vlan_detach_event != NULL) { 5400 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5401 ctx->ifc_vlan_detach_event = NULL; 5402 } 5403 5404 } 5405 5406 static void 5407 iflib_deregister(if_ctx_t ctx) 5408 { 5409 if_t ifp = ctx->ifc_ifp; 5410 5411 /* Remove all media */ 5412 ifmedia_removeall(&ctx->ifc_media); 5413 5414 /* Ensure that VLAN event handlers are unregistered */ 5415 iflib_unregister_vlan_handlers(ctx); 5416 5417 /* Release kobject reference */ 5418 kobj_delete((kobj_t) ctx, NULL); 5419 5420 /* Free the ifnet structure */ 5421 if_free(ifp); 5422 5423 STATE_LOCK_DESTROY(ctx); 5424 5425 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5426 CTX_LOCK_DESTROY(ctx); 5427 } 5428 5429 static int 5430 iflib_queues_alloc(if_ctx_t ctx) 5431 { 5432 if_shared_ctx_t sctx = ctx->ifc_sctx; 5433 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5434 device_t dev = ctx->ifc_dev; 5435 int nrxqsets = scctx->isc_nrxqsets; 5436 int ntxqsets = scctx->isc_ntxqsets; 5437 iflib_txq_t txq; 5438 iflib_rxq_t rxq; 5439 iflib_fl_t fl = NULL; 5440 int i, j, cpu, err, txconf, rxconf; 5441 iflib_dma_info_t ifdip; 5442 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5443 uint32_t *txqsizes = scctx->isc_txqsizes; 5444 uint8_t nrxqs = sctx->isc_nrxqs; 5445 uint8_t ntxqs = sctx->isc_ntxqs; 5446 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5447 caddr_t *vaddrs; 5448 uint64_t *paddrs; 5449 5450 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5451 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5452 5453 /* Allocate the TX ring struct memory */ 5454 if (!(ctx->ifc_txqs = 5455 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5456 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5457 device_printf(dev, "Unable to allocate TX ring memory\n"); 5458 err = ENOMEM; 5459 goto fail; 5460 } 5461 5462 /* Now allocate the RX */ 5463 if (!(ctx->ifc_rxqs = 5464 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5465 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5466 device_printf(dev, "Unable to allocate RX ring memory\n"); 5467 err = ENOMEM; 5468 goto rx_fail; 5469 } 5470 5471 txq = ctx->ifc_txqs; 5472 rxq = ctx->ifc_rxqs; 5473 5474 /* 5475 * XXX handle allocation failure 5476 */ 5477 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5478 /* Set up some basics */ 5479 5480 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5481 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5482 device_printf(dev, 5483 "Unable to allocate TX DMA info memory\n"); 5484 err = ENOMEM; 5485 goto err_tx_desc; 5486 } 5487 txq->ift_ifdi = ifdip; 5488 for (j = 0; j < ntxqs; j++, ifdip++) { 5489 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5490 device_printf(dev, 5491 "Unable to allocate TX descriptors\n"); 5492 err = ENOMEM; 5493 goto err_tx_desc; 5494 } 5495 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5496 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5497 } 5498 txq->ift_ctx = ctx; 5499 txq->ift_id = i; 5500 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5501 txq->ift_br_offset = 1; 5502 } else { 5503 txq->ift_br_offset = 0; 5504 } 5505 /* XXX fix this */ 5506 txq->ift_timer.c_cpu = cpu; 5507 5508 if (iflib_txsd_alloc(txq)) { 5509 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5510 err = ENOMEM; 5511 goto err_tx_desc; 5512 } 5513 5514 /* Initialize the TX lock */ 5515 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5516 device_get_nameunit(dev), txq->ift_id); 5517 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5518 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5519 5520 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5521 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5522 if (err) { 5523 /* XXX free any allocated rings */ 5524 device_printf(dev, "Unable to allocate buf_ring\n"); 5525 goto err_tx_desc; 5526 } 5527 } 5528 5529 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5530 /* Set up some basics */ 5531 5532 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5533 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5534 device_printf(dev, 5535 "Unable to allocate RX DMA info memory\n"); 5536 err = ENOMEM; 5537 goto err_tx_desc; 5538 } 5539 5540 rxq->ifr_ifdi = ifdip; 5541 /* XXX this needs to be changed if #rx queues != #tx queues */ 5542 rxq->ifr_ntxqirq = 1; 5543 rxq->ifr_txqid[0] = i; 5544 for (j = 0; j < nrxqs; j++, ifdip++) { 5545 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5546 device_printf(dev, 5547 "Unable to allocate RX descriptors\n"); 5548 err = ENOMEM; 5549 goto err_tx_desc; 5550 } 5551 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5552 } 5553 rxq->ifr_ctx = ctx; 5554 rxq->ifr_id = i; 5555 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5556 rxq->ifr_fl_offset = 1; 5557 } else { 5558 rxq->ifr_fl_offset = 0; 5559 } 5560 rxq->ifr_nfl = nfree_lists; 5561 if (!(fl = 5562 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5563 device_printf(dev, "Unable to allocate free list memory\n"); 5564 err = ENOMEM; 5565 goto err_tx_desc; 5566 } 5567 rxq->ifr_fl = fl; 5568 for (j = 0; j < nfree_lists; j++) { 5569 fl[j].ifl_rxq = rxq; 5570 fl[j].ifl_id = j; 5571 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5572 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5573 } 5574 /* Allocate receive buffers for the ring */ 5575 if (iflib_rxsd_alloc(rxq)) { 5576 device_printf(dev, 5577 "Critical Failure setting up receive buffers\n"); 5578 err = ENOMEM; 5579 goto err_rx_desc; 5580 } 5581 5582 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5583 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5584 M_WAITOK); 5585 } 5586 5587 /* TXQs */ 5588 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5589 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5590 for (i = 0; i < ntxqsets; i++) { 5591 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5592 5593 for (j = 0; j < ntxqs; j++, di++) { 5594 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5595 paddrs[i*ntxqs + j] = di->idi_paddr; 5596 } 5597 } 5598 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5599 device_printf(ctx->ifc_dev, 5600 "Unable to allocate device TX queue\n"); 5601 iflib_tx_structures_free(ctx); 5602 free(vaddrs, M_IFLIB); 5603 free(paddrs, M_IFLIB); 5604 goto err_rx_desc; 5605 } 5606 free(vaddrs, M_IFLIB); 5607 free(paddrs, M_IFLIB); 5608 5609 /* RXQs */ 5610 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5611 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5612 for (i = 0; i < nrxqsets; i++) { 5613 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5614 5615 for (j = 0; j < nrxqs; j++, di++) { 5616 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5617 paddrs[i*nrxqs + j] = di->idi_paddr; 5618 } 5619 } 5620 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5621 device_printf(ctx->ifc_dev, 5622 "Unable to allocate device RX queue\n"); 5623 iflib_tx_structures_free(ctx); 5624 free(vaddrs, M_IFLIB); 5625 free(paddrs, M_IFLIB); 5626 goto err_rx_desc; 5627 } 5628 free(vaddrs, M_IFLIB); 5629 free(paddrs, M_IFLIB); 5630 5631 return (0); 5632 5633 /* XXX handle allocation failure changes */ 5634 err_rx_desc: 5635 err_tx_desc: 5636 rx_fail: 5637 if (ctx->ifc_rxqs != NULL) 5638 free(ctx->ifc_rxqs, M_IFLIB); 5639 ctx->ifc_rxqs = NULL; 5640 if (ctx->ifc_txqs != NULL) 5641 free(ctx->ifc_txqs, M_IFLIB); 5642 ctx->ifc_txqs = NULL; 5643 fail: 5644 return (err); 5645 } 5646 5647 static int 5648 iflib_tx_structures_setup(if_ctx_t ctx) 5649 { 5650 iflib_txq_t txq = ctx->ifc_txqs; 5651 int i; 5652 5653 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5654 iflib_txq_setup(txq); 5655 5656 return (0); 5657 } 5658 5659 static void 5660 iflib_tx_structures_free(if_ctx_t ctx) 5661 { 5662 iflib_txq_t txq = ctx->ifc_txqs; 5663 if_shared_ctx_t sctx = ctx->ifc_sctx; 5664 int i, j; 5665 5666 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5667 for (j = 0; j < sctx->isc_ntxqs; j++) 5668 iflib_dma_free(&txq->ift_ifdi[j]); 5669 iflib_txq_destroy(txq); 5670 } 5671 free(ctx->ifc_txqs, M_IFLIB); 5672 ctx->ifc_txqs = NULL; 5673 IFDI_QUEUES_FREE(ctx); 5674 } 5675 5676 /********************************************************************* 5677 * 5678 * Initialize all receive rings. 5679 * 5680 **********************************************************************/ 5681 static int 5682 iflib_rx_structures_setup(if_ctx_t ctx) 5683 { 5684 iflib_rxq_t rxq = ctx->ifc_rxqs; 5685 int q; 5686 #if defined(INET6) || defined(INET) 5687 int err, i; 5688 #endif 5689 5690 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5691 #if defined(INET6) || defined(INET) 5692 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) { 5693 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5694 TCP_LRO_ENTRIES, min(1024, 5695 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 5696 if (err != 0) { 5697 device_printf(ctx->ifc_dev, 5698 "LRO Initialization failed!\n"); 5699 goto fail; 5700 } 5701 } 5702 #endif 5703 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5704 } 5705 return (0); 5706 #if defined(INET6) || defined(INET) 5707 fail: 5708 /* 5709 * Free LRO resources allocated so far, we will only handle 5710 * the rings that completed, the failing case will have 5711 * cleaned up for itself. 'q' failed, so its the terminus. 5712 */ 5713 rxq = ctx->ifc_rxqs; 5714 for (i = 0; i < q; ++i, rxq++) { 5715 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5716 tcp_lro_free(&rxq->ifr_lc); 5717 } 5718 return (err); 5719 #endif 5720 } 5721 5722 /********************************************************************* 5723 * 5724 * Free all receive rings. 5725 * 5726 **********************************************************************/ 5727 static void 5728 iflib_rx_structures_free(if_ctx_t ctx) 5729 { 5730 iflib_rxq_t rxq = ctx->ifc_rxqs; 5731 if_shared_ctx_t sctx = ctx->ifc_sctx; 5732 int i, j; 5733 5734 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5735 for (j = 0; j < sctx->isc_nrxqs; j++) 5736 iflib_dma_free(&rxq->ifr_ifdi[j]); 5737 iflib_rx_sds_free(rxq); 5738 #if defined(INET6) || defined(INET) 5739 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5740 tcp_lro_free(&rxq->ifr_lc); 5741 #endif 5742 } 5743 free(ctx->ifc_rxqs, M_IFLIB); 5744 ctx->ifc_rxqs = NULL; 5745 } 5746 5747 static int 5748 iflib_qset_structures_setup(if_ctx_t ctx) 5749 { 5750 int err; 5751 5752 /* 5753 * It is expected that the caller takes care of freeing queues if this 5754 * fails. 5755 */ 5756 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5757 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5758 return (err); 5759 } 5760 5761 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5762 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5763 5764 return (err); 5765 } 5766 5767 int 5768 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5769 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5770 { 5771 5772 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5773 } 5774 5775 #ifdef SMP 5776 static int 5777 find_nth(if_ctx_t ctx, int qid) 5778 { 5779 cpuset_t cpus; 5780 int i, cpuid, eqid, count; 5781 5782 CPU_COPY(&ctx->ifc_cpus, &cpus); 5783 count = CPU_COUNT(&cpus); 5784 eqid = qid % count; 5785 /* clear up to the qid'th bit */ 5786 for (i = 0; i < eqid; i++) { 5787 cpuid = CPU_FFS(&cpus); 5788 MPASS(cpuid != 0); 5789 CPU_CLR(cpuid-1, &cpus); 5790 } 5791 cpuid = CPU_FFS(&cpus); 5792 MPASS(cpuid != 0); 5793 return (cpuid-1); 5794 } 5795 5796 #ifdef SCHED_ULE 5797 extern struct cpu_group *cpu_top; /* CPU topology */ 5798 5799 static int 5800 find_child_with_core(int cpu, struct cpu_group *grp) 5801 { 5802 int i; 5803 5804 if (grp->cg_children == 0) 5805 return -1; 5806 5807 MPASS(grp->cg_child); 5808 for (i = 0; i < grp->cg_children; i++) { 5809 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5810 return i; 5811 } 5812 5813 return -1; 5814 } 5815 5816 /* 5817 * Find the nth "close" core to the specified core 5818 * "close" is defined as the deepest level that shares 5819 * at least an L2 cache. With threads, this will be 5820 * threads on the same core. If the shared cache is L3 5821 * or higher, simply returns the same core. 5822 */ 5823 static int 5824 find_close_core(int cpu, int core_offset) 5825 { 5826 struct cpu_group *grp; 5827 int i; 5828 int fcpu; 5829 cpuset_t cs; 5830 5831 grp = cpu_top; 5832 if (grp == NULL) 5833 return cpu; 5834 i = 0; 5835 while ((i = find_child_with_core(cpu, grp)) != -1) { 5836 /* If the child only has one cpu, don't descend */ 5837 if (grp->cg_child[i].cg_count <= 1) 5838 break; 5839 grp = &grp->cg_child[i]; 5840 } 5841 5842 /* If they don't share at least an L2 cache, use the same CPU */ 5843 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5844 return cpu; 5845 5846 /* Now pick one */ 5847 CPU_COPY(&grp->cg_mask, &cs); 5848 5849 /* Add the selected CPU offset to core offset. */ 5850 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5851 if (fcpu - 1 == cpu) 5852 break; 5853 CPU_CLR(fcpu - 1, &cs); 5854 } 5855 MPASS(fcpu); 5856 5857 core_offset += i; 5858 5859 CPU_COPY(&grp->cg_mask, &cs); 5860 for (i = core_offset % grp->cg_count; i > 0; i--) { 5861 MPASS(CPU_FFS(&cs)); 5862 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5863 } 5864 MPASS(CPU_FFS(&cs)); 5865 return CPU_FFS(&cs) - 1; 5866 } 5867 #else 5868 static int 5869 find_close_core(int cpu, int core_offset __unused) 5870 { 5871 return cpu; 5872 } 5873 #endif 5874 5875 static int 5876 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5877 { 5878 switch (type) { 5879 case IFLIB_INTR_TX: 5880 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5881 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5882 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5883 case IFLIB_INTR_RX: 5884 case IFLIB_INTR_RXTX: 5885 /* RX queues get the specified core */ 5886 return qid / CPU_COUNT(&ctx->ifc_cpus); 5887 default: 5888 return -1; 5889 } 5890 } 5891 #else 5892 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5893 #define find_close_core(cpuid, tid) CPU_FIRST() 5894 #define find_nth(ctx, gid) CPU_FIRST() 5895 #endif 5896 5897 /* Just to avoid copy/paste */ 5898 static inline int 5899 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5900 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5901 const char *name) 5902 { 5903 device_t dev; 5904 int co, cpuid, err, tid; 5905 5906 dev = ctx->ifc_dev; 5907 co = ctx->ifc_sysctl_core_offset; 5908 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX) 5909 co += ctx->ifc_softc_ctx.isc_nrxqsets; 5910 cpuid = find_nth(ctx, qid + co); 5911 tid = get_core_offset(ctx, type, qid); 5912 if (tid < 0) { 5913 device_printf(dev, "get_core_offset failed\n"); 5914 return (EOPNOTSUPP); 5915 } 5916 cpuid = find_close_core(cpuid, tid); 5917 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 5918 name); 5919 if (err) { 5920 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 5921 return (err); 5922 } 5923 #ifdef notyet 5924 if (cpuid > ctx->ifc_cpuid_highest) 5925 ctx->ifc_cpuid_highest = cpuid; 5926 #endif 5927 return (0); 5928 } 5929 5930 int 5931 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5932 iflib_intr_type_t type, driver_filter_t *filter, 5933 void *filter_arg, int qid, const char *name) 5934 { 5935 device_t dev; 5936 struct grouptask *gtask; 5937 struct taskqgroup *tqg; 5938 iflib_filter_info_t info; 5939 gtask_fn_t *fn; 5940 int tqrid, err; 5941 driver_filter_t *intr_fast; 5942 void *q; 5943 5944 info = &ctx->ifc_filter_info; 5945 tqrid = rid; 5946 5947 switch (type) { 5948 /* XXX merge tx/rx for netmap? */ 5949 case IFLIB_INTR_TX: 5950 q = &ctx->ifc_txqs[qid]; 5951 info = &ctx->ifc_txqs[qid].ift_filter_info; 5952 gtask = &ctx->ifc_txqs[qid].ift_task; 5953 tqg = qgroup_if_io_tqg; 5954 fn = _task_fn_tx; 5955 intr_fast = iflib_fast_intr; 5956 GROUPTASK_INIT(gtask, 0, fn, q); 5957 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5958 break; 5959 case IFLIB_INTR_RX: 5960 q = &ctx->ifc_rxqs[qid]; 5961 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5962 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5963 tqg = qgroup_if_io_tqg; 5964 fn = _task_fn_rx; 5965 intr_fast = iflib_fast_intr; 5966 GROUPTASK_INIT(gtask, 0, fn, q); 5967 break; 5968 case IFLIB_INTR_RXTX: 5969 q = &ctx->ifc_rxqs[qid]; 5970 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5971 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5972 tqg = qgroup_if_io_tqg; 5973 fn = _task_fn_rx; 5974 intr_fast = iflib_fast_intr_rxtx; 5975 GROUPTASK_INIT(gtask, 0, fn, q); 5976 break; 5977 case IFLIB_INTR_ADMIN: 5978 q = ctx; 5979 tqrid = -1; 5980 info = &ctx->ifc_filter_info; 5981 gtask = &ctx->ifc_admin_task; 5982 tqg = qgroup_if_config_tqg; 5983 fn = _task_fn_admin; 5984 intr_fast = iflib_fast_intr_ctx; 5985 break; 5986 default: 5987 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 5988 __func__); 5989 return (EINVAL); 5990 } 5991 5992 info->ifi_filter = filter; 5993 info->ifi_filter_arg = filter_arg; 5994 info->ifi_task = gtask; 5995 info->ifi_ctx = q; 5996 5997 dev = ctx->ifc_dev; 5998 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5999 if (err != 0) { 6000 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6001 return (err); 6002 } 6003 if (type == IFLIB_INTR_ADMIN) 6004 return (0); 6005 6006 if (tqrid != -1) { 6007 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6008 q, name); 6009 if (err) 6010 return (err); 6011 } else { 6012 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6013 } 6014 6015 return (0); 6016 } 6017 6018 void 6019 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6020 { 6021 struct grouptask *gtask; 6022 struct taskqgroup *tqg; 6023 gtask_fn_t *fn; 6024 void *q; 6025 int err; 6026 6027 switch (type) { 6028 case IFLIB_INTR_TX: 6029 q = &ctx->ifc_txqs[qid]; 6030 gtask = &ctx->ifc_txqs[qid].ift_task; 6031 tqg = qgroup_if_io_tqg; 6032 fn = _task_fn_tx; 6033 break; 6034 case IFLIB_INTR_RX: 6035 q = &ctx->ifc_rxqs[qid]; 6036 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6037 tqg = qgroup_if_io_tqg; 6038 fn = _task_fn_rx; 6039 break; 6040 case IFLIB_INTR_IOV: 6041 q = ctx; 6042 gtask = &ctx->ifc_vflr_task; 6043 tqg = qgroup_if_config_tqg; 6044 fn = _task_fn_iov; 6045 break; 6046 default: 6047 panic("unknown net intr type"); 6048 } 6049 GROUPTASK_INIT(gtask, 0, fn, q); 6050 if (irq != NULL) { 6051 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6052 q, name); 6053 if (err) 6054 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 6055 irq->ii_res, name); 6056 } else { 6057 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 6058 } 6059 } 6060 6061 void 6062 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6063 { 6064 6065 if (irq->ii_tag) 6066 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6067 6068 if (irq->ii_res) 6069 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6070 rman_get_rid(irq->ii_res), irq->ii_res); 6071 } 6072 6073 static int 6074 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6075 { 6076 iflib_txq_t txq = ctx->ifc_txqs; 6077 iflib_rxq_t rxq = ctx->ifc_rxqs; 6078 if_irq_t irq = &ctx->ifc_legacy_irq; 6079 iflib_filter_info_t info; 6080 device_t dev; 6081 struct grouptask *gtask; 6082 struct resource *res; 6083 struct taskqgroup *tqg; 6084 gtask_fn_t *fn; 6085 void *q; 6086 int err, tqrid; 6087 bool rx_only; 6088 6089 q = &ctx->ifc_rxqs[0]; 6090 info = &rxq[0].ifr_filter_info; 6091 gtask = &rxq[0].ifr_task; 6092 tqg = qgroup_if_io_tqg; 6093 tqrid = *rid; 6094 fn = _task_fn_rx; 6095 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6096 6097 ctx->ifc_flags |= IFC_LEGACY; 6098 info->ifi_filter = filter; 6099 info->ifi_filter_arg = filter_arg; 6100 info->ifi_task = gtask; 6101 info->ifi_ctx = rx_only ? ctx : q; 6102 6103 dev = ctx->ifc_dev; 6104 /* We allocate a single interrupt resource */ 6105 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6106 iflib_fast_intr_rxtx, NULL, info, name); 6107 if (err != 0) 6108 return (err); 6109 GROUPTASK_INIT(gtask, 0, fn, q); 6110 res = irq->ii_res; 6111 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6112 6113 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6114 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6115 "tx"); 6116 return (0); 6117 } 6118 6119 void 6120 iflib_led_create(if_ctx_t ctx) 6121 { 6122 6123 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6124 device_get_nameunit(ctx->ifc_dev)); 6125 } 6126 6127 void 6128 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6129 { 6130 6131 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6132 } 6133 6134 void 6135 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6136 { 6137 6138 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6139 } 6140 6141 void 6142 iflib_admin_intr_deferred(if_ctx_t ctx) 6143 { 6144 #ifdef INVARIANTS 6145 struct grouptask *gtask; 6146 6147 gtask = &ctx->ifc_admin_task; 6148 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 6149 #endif 6150 6151 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6152 } 6153 6154 void 6155 iflib_iov_intr_deferred(if_ctx_t ctx) 6156 { 6157 6158 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6159 } 6160 6161 void 6162 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6163 { 6164 6165 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6166 name); 6167 } 6168 6169 void 6170 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6171 const char *name) 6172 { 6173 6174 GROUPTASK_INIT(gtask, 0, fn, ctx); 6175 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6176 name); 6177 } 6178 6179 void 6180 iflib_config_gtask_deinit(struct grouptask *gtask) 6181 { 6182 6183 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6184 } 6185 6186 void 6187 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6188 { 6189 if_t ifp = ctx->ifc_ifp; 6190 iflib_txq_t txq = ctx->ifc_txqs; 6191 6192 if_setbaudrate(ifp, baudrate); 6193 if (baudrate >= IF_Gbps(10)) { 6194 STATE_LOCK(ctx); 6195 ctx->ifc_flags |= IFC_PREFETCH; 6196 STATE_UNLOCK(ctx); 6197 } 6198 /* If link down, disable watchdog */ 6199 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6200 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6201 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6202 } 6203 ctx->ifc_link_state = link_state; 6204 if_link_state_change(ifp, link_state); 6205 } 6206 6207 static int 6208 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6209 { 6210 int credits; 6211 #ifdef INVARIANTS 6212 int credits_pre = txq->ift_cidx_processed; 6213 #endif 6214 6215 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6216 BUS_DMASYNC_POSTREAD); 6217 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6218 return (0); 6219 6220 txq->ift_processed += credits; 6221 txq->ift_cidx_processed += credits; 6222 6223 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6224 if (txq->ift_cidx_processed >= txq->ift_size) 6225 txq->ift_cidx_processed -= txq->ift_size; 6226 return (credits); 6227 } 6228 6229 static int 6230 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6231 { 6232 iflib_fl_t fl; 6233 u_int i; 6234 6235 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6236 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6237 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6238 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6239 budget)); 6240 } 6241 6242 void 6243 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6244 const char *description, if_int_delay_info_t info, 6245 int offset, int value) 6246 { 6247 info->iidi_ctx = ctx; 6248 info->iidi_offset = offset; 6249 info->iidi_value = value; 6250 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6251 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6252 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 6253 info, 0, iflib_sysctl_int_delay, "I", description); 6254 } 6255 6256 struct sx * 6257 iflib_ctx_lock_get(if_ctx_t ctx) 6258 { 6259 6260 return (&ctx->ifc_ctx_sx); 6261 } 6262 6263 static int 6264 iflib_msix_init(if_ctx_t ctx) 6265 { 6266 device_t dev = ctx->ifc_dev; 6267 if_shared_ctx_t sctx = ctx->ifc_sctx; 6268 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6269 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6270 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6271 6272 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6273 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6274 6275 if (bootverbose) 6276 device_printf(dev, "msix_init qsets capped at %d\n", 6277 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6278 6279 /* Override by tuneable */ 6280 if (scctx->isc_disable_msix) 6281 goto msi; 6282 6283 /* First try MSI-X */ 6284 if ((msgs = pci_msix_count(dev)) == 0) { 6285 if (bootverbose) 6286 device_printf(dev, "MSI-X not supported or disabled\n"); 6287 goto msi; 6288 } 6289 6290 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6291 /* 6292 * bar == -1 => "trust me I know what I'm doing" 6293 * Some drivers are for hardware that is so shoddily 6294 * documented that no one knows which bars are which 6295 * so the developer has to map all bars. This hack 6296 * allows shoddy garbage to use MSI-X in this framework. 6297 */ 6298 if (bar != -1) { 6299 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6300 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6301 if (ctx->ifc_msix_mem == NULL) { 6302 device_printf(dev, "Unable to map MSI-X table\n"); 6303 goto msi; 6304 } 6305 } 6306 6307 admincnt = sctx->isc_admin_intrcnt; 6308 #if IFLIB_DEBUG 6309 /* use only 1 qset in debug mode */ 6310 queuemsgs = min(msgs - admincnt, 1); 6311 #else 6312 queuemsgs = msgs - admincnt; 6313 #endif 6314 #ifdef RSS 6315 queues = imin(queuemsgs, rss_getnumbuckets()); 6316 #else 6317 queues = queuemsgs; 6318 #endif 6319 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6320 if (bootverbose) 6321 device_printf(dev, 6322 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6323 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6324 #ifdef RSS 6325 /* If we're doing RSS, clamp at the number of RSS buckets */ 6326 if (queues > rss_getnumbuckets()) 6327 queues = rss_getnumbuckets(); 6328 #endif 6329 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6330 rx_queues = iflib_num_rx_queues; 6331 else 6332 rx_queues = queues; 6333 6334 if (rx_queues > scctx->isc_nrxqsets) 6335 rx_queues = scctx->isc_nrxqsets; 6336 6337 /* 6338 * We want this to be all logical CPUs by default 6339 */ 6340 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6341 tx_queues = iflib_num_tx_queues; 6342 else 6343 tx_queues = mp_ncpus; 6344 6345 if (tx_queues > scctx->isc_ntxqsets) 6346 tx_queues = scctx->isc_ntxqsets; 6347 6348 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6349 #ifdef INVARIANTS 6350 if (tx_queues != rx_queues) 6351 device_printf(dev, 6352 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6353 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6354 #endif 6355 tx_queues = min(rx_queues, tx_queues); 6356 rx_queues = min(rx_queues, tx_queues); 6357 } 6358 6359 vectors = rx_queues + admincnt; 6360 if (msgs < vectors) { 6361 device_printf(dev, 6362 "insufficient number of MSI-X vectors " 6363 "(supported %d, need %d)\n", msgs, vectors); 6364 goto msi; 6365 } 6366 6367 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6368 tx_queues); 6369 msgs = vectors; 6370 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6371 if (vectors != msgs) { 6372 device_printf(dev, 6373 "Unable to allocate sufficient MSI-X vectors " 6374 "(got %d, need %d)\n", vectors, msgs); 6375 pci_release_msi(dev); 6376 if (bar != -1) { 6377 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6378 ctx->ifc_msix_mem); 6379 ctx->ifc_msix_mem = NULL; 6380 } 6381 goto msi; 6382 } 6383 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6384 vectors); 6385 scctx->isc_vectors = vectors; 6386 scctx->isc_nrxqsets = rx_queues; 6387 scctx->isc_ntxqsets = tx_queues; 6388 scctx->isc_intr = IFLIB_INTR_MSIX; 6389 6390 return (vectors); 6391 } else { 6392 device_printf(dev, 6393 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6394 err); 6395 if (bar != -1) { 6396 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6397 ctx->ifc_msix_mem); 6398 ctx->ifc_msix_mem = NULL; 6399 } 6400 } 6401 6402 msi: 6403 vectors = pci_msi_count(dev); 6404 scctx->isc_nrxqsets = 1; 6405 scctx->isc_ntxqsets = 1; 6406 scctx->isc_vectors = vectors; 6407 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6408 device_printf(dev,"Using an MSI interrupt\n"); 6409 scctx->isc_intr = IFLIB_INTR_MSI; 6410 } else { 6411 scctx->isc_vectors = 1; 6412 device_printf(dev,"Using a Legacy interrupt\n"); 6413 scctx->isc_intr = IFLIB_INTR_LEGACY; 6414 } 6415 6416 return (vectors); 6417 } 6418 6419 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6420 6421 static int 6422 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6423 { 6424 int rc; 6425 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6426 struct sbuf *sb; 6427 const char *ring_state = "UNKNOWN"; 6428 6429 /* XXX needed ? */ 6430 rc = sysctl_wire_old_buffer(req, 0); 6431 MPASS(rc == 0); 6432 if (rc != 0) 6433 return (rc); 6434 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6435 MPASS(sb != NULL); 6436 if (sb == NULL) 6437 return (ENOMEM); 6438 if (state[3] <= 3) 6439 ring_state = ring_states[state[3]]; 6440 6441 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6442 state[0], state[1], state[2], ring_state); 6443 rc = sbuf_finish(sb); 6444 sbuf_delete(sb); 6445 return(rc); 6446 } 6447 6448 enum iflib_ndesc_handler { 6449 IFLIB_NTXD_HANDLER, 6450 IFLIB_NRXD_HANDLER, 6451 }; 6452 6453 static int 6454 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6455 { 6456 if_ctx_t ctx = (void *)arg1; 6457 enum iflib_ndesc_handler type = arg2; 6458 char buf[256] = {0}; 6459 qidx_t *ndesc; 6460 char *p, *next; 6461 int nqs, rc, i; 6462 6463 nqs = 8; 6464 switch(type) { 6465 case IFLIB_NTXD_HANDLER: 6466 ndesc = ctx->ifc_sysctl_ntxds; 6467 if (ctx->ifc_sctx) 6468 nqs = ctx->ifc_sctx->isc_ntxqs; 6469 break; 6470 case IFLIB_NRXD_HANDLER: 6471 ndesc = ctx->ifc_sysctl_nrxds; 6472 if (ctx->ifc_sctx) 6473 nqs = ctx->ifc_sctx->isc_nrxqs; 6474 break; 6475 default: 6476 printf("%s: unhandled type\n", __func__); 6477 return (EINVAL); 6478 } 6479 if (nqs == 0) 6480 nqs = 8; 6481 6482 for (i=0; i<8; i++) { 6483 if (i >= nqs) 6484 break; 6485 if (i) 6486 strcat(buf, ","); 6487 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6488 } 6489 6490 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6491 if (rc || req->newptr == NULL) 6492 return rc; 6493 6494 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6495 i++, p = strsep(&next, " ,")) { 6496 ndesc[i] = strtoul(p, NULL, 10); 6497 } 6498 6499 return(rc); 6500 } 6501 6502 #define NAME_BUFLEN 32 6503 static void 6504 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6505 { 6506 device_t dev = iflib_get_dev(ctx); 6507 struct sysctl_oid_list *child, *oid_list; 6508 struct sysctl_ctx_list *ctx_list; 6509 struct sysctl_oid *node; 6510 6511 ctx_list = device_get_sysctl_ctx(dev); 6512 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6513 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6514 CTLFLAG_RD, NULL, "IFLIB fields"); 6515 oid_list = SYSCTL_CHILDREN(node); 6516 6517 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6518 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6519 "driver version"); 6520 6521 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6522 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6523 "# of txqs to use, 0 => use default #"); 6524 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6525 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6526 "# of rxqs to use, 0 => use default #"); 6527 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6528 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6529 "permit #txq != #rxq"); 6530 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6531 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6532 "disable MSI-X (default 0)"); 6533 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6534 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6535 "set the RX budget"); 6536 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6537 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6538 "cause TX to abdicate instead of running to completion"); 6539 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6540 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6541 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6542 "offset to start using cores at"); 6543 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6544 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6545 "use separate cores for TX and RX"); 6546 6547 /* XXX change for per-queue sizes */ 6548 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6549 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6550 mp_ndesc_handler, "A", 6551 "list of # of TX descriptors to use, 0 = use default #"); 6552 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6553 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6554 mp_ndesc_handler, "A", 6555 "list of # of RX descriptors to use, 0 = use default #"); 6556 } 6557 6558 static void 6559 iflib_add_device_sysctl_post(if_ctx_t ctx) 6560 { 6561 if_shared_ctx_t sctx = ctx->ifc_sctx; 6562 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6563 device_t dev = iflib_get_dev(ctx); 6564 struct sysctl_oid_list *child; 6565 struct sysctl_ctx_list *ctx_list; 6566 iflib_fl_t fl; 6567 iflib_txq_t txq; 6568 iflib_rxq_t rxq; 6569 int i, j; 6570 char namebuf[NAME_BUFLEN]; 6571 char *qfmt; 6572 struct sysctl_oid *queue_node, *fl_node, *node; 6573 struct sysctl_oid_list *queue_list, *fl_list; 6574 ctx_list = device_get_sysctl_ctx(dev); 6575 6576 node = ctx->ifc_sysctl_node; 6577 child = SYSCTL_CHILDREN(node); 6578 6579 if (scctx->isc_ntxqsets > 100) 6580 qfmt = "txq%03d"; 6581 else if (scctx->isc_ntxqsets > 10) 6582 qfmt = "txq%02d"; 6583 else 6584 qfmt = "txq%d"; 6585 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6586 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6587 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6588 CTLFLAG_RD, NULL, "Queue Name"); 6589 queue_list = SYSCTL_CHILDREN(queue_node); 6590 #if MEMORY_LOGGING 6591 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6592 CTLFLAG_RD, 6593 &txq->ift_dequeued, "total mbufs freed"); 6594 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6595 CTLFLAG_RD, 6596 &txq->ift_enqueued, "total mbufs enqueued"); 6597 #endif 6598 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6599 CTLFLAG_RD, 6600 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6601 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6602 CTLFLAG_RD, 6603 &txq->ift_pullups, "# of times m_pullup was called"); 6604 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6605 CTLFLAG_RD, 6606 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6607 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6608 CTLFLAG_RD, 6609 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6610 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6611 CTLFLAG_RD, 6612 &txq->ift_map_failed, "# of times DMA map failed"); 6613 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6614 CTLFLAG_RD, 6615 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6616 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6617 CTLFLAG_RD, 6618 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6619 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6620 CTLFLAG_RD, 6621 &txq->ift_pidx, 1, "Producer Index"); 6622 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6623 CTLFLAG_RD, 6624 &txq->ift_cidx, 1, "Consumer Index"); 6625 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6626 CTLFLAG_RD, 6627 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6628 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6629 CTLFLAG_RD, 6630 &txq->ift_in_use, 1, "descriptors in use"); 6631 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6632 CTLFLAG_RD, 6633 &txq->ift_processed, "descriptors procesed for clean"); 6634 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6635 CTLFLAG_RD, 6636 &txq->ift_cleaned, "total cleaned"); 6637 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6638 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6639 0, mp_ring_state_handler, "A", "soft ring state"); 6640 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6641 CTLFLAG_RD, &txq->ift_br->enqueues, 6642 "# of enqueues to the mp_ring for this queue"); 6643 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6644 CTLFLAG_RD, &txq->ift_br->drops, 6645 "# of drops in the mp_ring for this queue"); 6646 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6647 CTLFLAG_RD, &txq->ift_br->starts, 6648 "# of normal consumer starts in the mp_ring for this queue"); 6649 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6650 CTLFLAG_RD, &txq->ift_br->stalls, 6651 "# of consumer stalls in the mp_ring for this queue"); 6652 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6653 CTLFLAG_RD, &txq->ift_br->restarts, 6654 "# of consumer restarts in the mp_ring for this queue"); 6655 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6656 CTLFLAG_RD, &txq->ift_br->abdications, 6657 "# of consumer abdications in the mp_ring for this queue"); 6658 } 6659 6660 if (scctx->isc_nrxqsets > 100) 6661 qfmt = "rxq%03d"; 6662 else if (scctx->isc_nrxqsets > 10) 6663 qfmt = "rxq%02d"; 6664 else 6665 qfmt = "rxq%d"; 6666 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6667 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6668 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6669 CTLFLAG_RD, NULL, "Queue Name"); 6670 queue_list = SYSCTL_CHILDREN(queue_node); 6671 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6672 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6673 CTLFLAG_RD, 6674 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6675 } 6676 6677 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6678 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6679 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6680 CTLFLAG_RD, NULL, "freelist Name"); 6681 fl_list = SYSCTL_CHILDREN(fl_node); 6682 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6683 CTLFLAG_RD, 6684 &fl->ifl_pidx, 1, "Producer Index"); 6685 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6686 CTLFLAG_RD, 6687 &fl->ifl_cidx, 1, "Consumer Index"); 6688 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6689 CTLFLAG_RD, 6690 &fl->ifl_credits, 1, "credits available"); 6691 #if MEMORY_LOGGING 6692 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6693 CTLFLAG_RD, 6694 &fl->ifl_m_enqueued, "mbufs allocated"); 6695 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6696 CTLFLAG_RD, 6697 &fl->ifl_m_dequeued, "mbufs freed"); 6698 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6699 CTLFLAG_RD, 6700 &fl->ifl_cl_enqueued, "clusters allocated"); 6701 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6702 CTLFLAG_RD, 6703 &fl->ifl_cl_dequeued, "clusters freed"); 6704 #endif 6705 6706 } 6707 } 6708 6709 } 6710 6711 void 6712 iflib_request_reset(if_ctx_t ctx) 6713 { 6714 6715 STATE_LOCK(ctx); 6716 ctx->ifc_flags |= IFC_DO_RESET; 6717 STATE_UNLOCK(ctx); 6718 } 6719 6720 #ifndef __NO_STRICT_ALIGNMENT 6721 static struct mbuf * 6722 iflib_fixup_rx(struct mbuf *m) 6723 { 6724 struct mbuf *n; 6725 6726 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6727 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6728 m->m_data += ETHER_HDR_LEN; 6729 n = m; 6730 } else { 6731 MGETHDR(n, M_NOWAIT, MT_DATA); 6732 if (n == NULL) { 6733 m_freem(m); 6734 return (NULL); 6735 } 6736 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6737 m->m_data += ETHER_HDR_LEN; 6738 m->m_len -= ETHER_HDR_LEN; 6739 n->m_len = ETHER_HDR_LEN; 6740 M_MOVE_PKTHDR(n, m); 6741 n->m_next = m; 6742 } 6743 return (n); 6744 } 6745 #endif 6746 6747 #ifdef DEBUGNET 6748 static void 6749 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6750 { 6751 if_ctx_t ctx; 6752 6753 ctx = if_getsoftc(ifp); 6754 CTX_LOCK(ctx); 6755 *nrxr = NRXQSETS(ctx); 6756 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6757 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6758 CTX_UNLOCK(ctx); 6759 } 6760 6761 static void 6762 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 6763 { 6764 if_ctx_t ctx; 6765 if_softc_ctx_t scctx; 6766 iflib_fl_t fl; 6767 iflib_rxq_t rxq; 6768 int i, j; 6769 6770 ctx = if_getsoftc(ifp); 6771 scctx = &ctx->ifc_softc_ctx; 6772 6773 switch (event) { 6774 case DEBUGNET_START: 6775 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6776 rxq = &ctx->ifc_rxqs[i]; 6777 for (j = 0; j < rxq->ifr_nfl; j++) { 6778 fl = rxq->ifr_fl; 6779 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6780 } 6781 } 6782 iflib_no_tx_batch = 1; 6783 break; 6784 default: 6785 break; 6786 } 6787 } 6788 6789 static int 6790 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 6791 { 6792 if_ctx_t ctx; 6793 iflib_txq_t txq; 6794 int error; 6795 6796 ctx = if_getsoftc(ifp); 6797 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6798 IFF_DRV_RUNNING) 6799 return (EBUSY); 6800 6801 txq = &ctx->ifc_txqs[0]; 6802 error = iflib_encap(txq, &m); 6803 if (error == 0) 6804 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6805 return (error); 6806 } 6807 6808 static int 6809 iflib_debugnet_poll(if_t ifp, int count) 6810 { 6811 if_ctx_t ctx; 6812 if_softc_ctx_t scctx; 6813 iflib_txq_t txq; 6814 int i; 6815 6816 ctx = if_getsoftc(ifp); 6817 scctx = &ctx->ifc_softc_ctx; 6818 6819 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6820 IFF_DRV_RUNNING) 6821 return (EBUSY); 6822 6823 txq = &ctx->ifc_txqs[0]; 6824 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6825 6826 for (i = 0; i < scctx->isc_nrxqsets; i++) 6827 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6828 return (0); 6829 } 6830 #endif /* DEBUGNET */ 6831