1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/pfil.h> 63 #include <net/vnet.h> 64 65 #include <netinet/in.h> 66 #include <netinet/in_pcb.h> 67 #include <netinet/tcp_lro.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/if_ether.h> 70 #include <netinet/ip.h> 71 #include <netinet/ip6.h> 72 #include <netinet/tcp.h> 73 #include <netinet/ip_var.h> 74 #include <netinet/netdump/netdump.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 120 /* 121 * File organization: 122 * - private structures 123 * - iflib private utility functions 124 * - ifnet functions 125 * - vlan registry and other exported functions 126 * - iflib public core functions 127 * 128 * 129 */ 130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 131 132 struct iflib_txq; 133 typedef struct iflib_txq *iflib_txq_t; 134 struct iflib_rxq; 135 typedef struct iflib_rxq *iflib_rxq_t; 136 struct iflib_fl; 137 typedef struct iflib_fl *iflib_fl_t; 138 139 struct iflib_ctx; 140 141 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 142 static void iflib_timer(void *arg); 143 144 typedef struct iflib_filter_info { 145 driver_filter_t *ifi_filter; 146 void *ifi_filter_arg; 147 struct grouptask *ifi_task; 148 void *ifi_ctx; 149 } *iflib_filter_info_t; 150 151 struct iflib_ctx { 152 KOBJ_FIELDS; 153 /* 154 * Pointer to hardware driver's softc 155 */ 156 void *ifc_softc; 157 device_t ifc_dev; 158 if_t ifc_ifp; 159 160 cpuset_t ifc_cpus; 161 if_shared_ctx_t ifc_sctx; 162 struct if_softc_ctx ifc_softc_ctx; 163 164 struct sx ifc_ctx_sx; 165 struct mtx ifc_state_mtx; 166 167 iflib_txq_t ifc_txqs; 168 iflib_rxq_t ifc_rxqs; 169 uint32_t ifc_if_flags; 170 uint32_t ifc_flags; 171 uint32_t ifc_max_fl_buf_size; 172 uint32_t ifc_rx_mbuf_sz; 173 174 int ifc_link_state; 175 int ifc_link_irq; 176 int ifc_watchdog_events; 177 struct cdev *ifc_led_dev; 178 struct resource *ifc_msix_mem; 179 180 struct if_irq ifc_legacy_irq; 181 struct grouptask ifc_admin_task; 182 struct grouptask ifc_vflr_task; 183 struct iflib_filter_info ifc_filter_info; 184 struct ifmedia ifc_media; 185 186 struct sysctl_oid *ifc_sysctl_node; 187 uint16_t ifc_sysctl_ntxqs; 188 uint16_t ifc_sysctl_nrxqs; 189 uint16_t ifc_sysctl_qs_eq_override; 190 uint16_t ifc_sysctl_rx_budget; 191 uint16_t ifc_sysctl_tx_abdicate; 192 uint16_t ifc_sysctl_core_offset; 193 #define CORE_OFFSET_UNSPECIFIED 0xffff 194 uint8_t ifc_sysctl_separate_txrx; 195 196 qidx_t ifc_sysctl_ntxds[8]; 197 qidx_t ifc_sysctl_nrxds[8]; 198 struct if_txrx ifc_txrx; 199 #define isc_txd_encap ifc_txrx.ift_txd_encap 200 #define isc_txd_flush ifc_txrx.ift_txd_flush 201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 202 #define isc_rxd_available ifc_txrx.ift_rxd_available 203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 209 eventhandler_tag ifc_vlan_attach_event; 210 eventhandler_tag ifc_vlan_detach_event; 211 struct ether_addr ifc_mac; 212 char ifc_mtx_name[16]; 213 }; 214 215 216 void * 217 iflib_get_softc(if_ctx_t ctx) 218 { 219 220 return (ctx->ifc_softc); 221 } 222 223 device_t 224 iflib_get_dev(if_ctx_t ctx) 225 { 226 227 return (ctx->ifc_dev); 228 } 229 230 if_t 231 iflib_get_ifp(if_ctx_t ctx) 232 { 233 234 return (ctx->ifc_ifp); 235 } 236 237 struct ifmedia * 238 iflib_get_media(if_ctx_t ctx) 239 { 240 241 return (&ctx->ifc_media); 242 } 243 244 uint32_t 245 iflib_get_flags(if_ctx_t ctx) 246 { 247 return (ctx->ifc_flags); 248 } 249 250 void 251 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 252 { 253 254 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 255 } 256 257 if_softc_ctx_t 258 iflib_get_softc_ctx(if_ctx_t ctx) 259 { 260 261 return (&ctx->ifc_softc_ctx); 262 } 263 264 if_shared_ctx_t 265 iflib_get_sctx(if_ctx_t ctx) 266 { 267 268 return (ctx->ifc_sctx); 269 } 270 271 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 272 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 273 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 274 275 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 276 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 277 278 typedef struct iflib_sw_rx_desc_array { 279 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 280 struct mbuf **ifsd_m; /* pkthdr mbufs */ 281 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 282 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 283 } iflib_rxsd_array_t; 284 285 typedef struct iflib_sw_tx_desc_array { 286 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 287 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 288 struct mbuf **ifsd_m; /* pkthdr mbufs */ 289 } if_txsd_vec_t; 290 291 292 /* magic number that should be high enough for any hardware */ 293 #define IFLIB_MAX_TX_SEGS 128 294 #define IFLIB_RX_COPY_THRESH 128 295 #define IFLIB_MAX_RX_REFRESH 32 296 /* The minimum descriptors per second before we start coalescing */ 297 #define IFLIB_MIN_DESC_SEC 16384 298 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 299 #define IFLIB_QUEUE_IDLE 0 300 #define IFLIB_QUEUE_HUNG 1 301 #define IFLIB_QUEUE_WORKING 2 302 /* maximum number of txqs that can share an rx interrupt */ 303 #define IFLIB_MAX_TX_SHARED_INTR 4 304 305 /* this should really scale with ring size - this is a fairly arbitrary value */ 306 #define TX_BATCH_SIZE 32 307 308 #define IFLIB_RESTART_BUDGET 8 309 310 311 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 312 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 313 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 314 struct iflib_txq { 315 qidx_t ift_in_use; 316 qidx_t ift_cidx; 317 qidx_t ift_cidx_processed; 318 qidx_t ift_pidx; 319 uint8_t ift_gen; 320 uint8_t ift_br_offset; 321 uint16_t ift_npending; 322 uint16_t ift_db_pending; 323 uint16_t ift_rs_pending; 324 /* implicit pad */ 325 uint8_t ift_txd_size[8]; 326 uint64_t ift_processed; 327 uint64_t ift_cleaned; 328 uint64_t ift_cleaned_prev; 329 #if MEMORY_LOGGING 330 uint64_t ift_enqueued; 331 uint64_t ift_dequeued; 332 #endif 333 uint64_t ift_no_tx_dma_setup; 334 uint64_t ift_no_desc_avail; 335 uint64_t ift_mbuf_defrag_failed; 336 uint64_t ift_mbuf_defrag; 337 uint64_t ift_map_failed; 338 uint64_t ift_txd_encap_efbig; 339 uint64_t ift_pullups; 340 uint64_t ift_last_timer_tick; 341 342 struct mtx ift_mtx; 343 struct mtx ift_db_mtx; 344 345 /* constant values */ 346 if_ctx_t ift_ctx; 347 struct ifmp_ring *ift_br; 348 struct grouptask ift_task; 349 qidx_t ift_size; 350 uint16_t ift_id; 351 struct callout ift_timer; 352 353 if_txsd_vec_t ift_sds; 354 uint8_t ift_qstatus; 355 uint8_t ift_closed; 356 uint8_t ift_update_freq; 357 struct iflib_filter_info ift_filter_info; 358 bus_dma_tag_t ift_buf_tag; 359 bus_dma_tag_t ift_tso_buf_tag; 360 iflib_dma_info_t ift_ifdi; 361 #define MTX_NAME_LEN 16 362 char ift_mtx_name[MTX_NAME_LEN]; 363 char ift_db_mtx_name[MTX_NAME_LEN]; 364 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 365 #ifdef IFLIB_DIAGNOSTICS 366 uint64_t ift_cpu_exec_count[256]; 367 #endif 368 } __aligned(CACHE_LINE_SIZE); 369 370 struct iflib_fl { 371 qidx_t ifl_cidx; 372 qidx_t ifl_pidx; 373 qidx_t ifl_credits; 374 uint8_t ifl_gen; 375 uint8_t ifl_rxd_size; 376 #if MEMORY_LOGGING 377 uint64_t ifl_m_enqueued; 378 uint64_t ifl_m_dequeued; 379 uint64_t ifl_cl_enqueued; 380 uint64_t ifl_cl_dequeued; 381 #endif 382 /* implicit pad */ 383 384 bitstr_t *ifl_rx_bitmap; 385 qidx_t ifl_fragidx; 386 /* constant */ 387 qidx_t ifl_size; 388 uint16_t ifl_buf_size; 389 uint16_t ifl_cltype; 390 uma_zone_t ifl_zone; 391 iflib_rxsd_array_t ifl_sds; 392 iflib_rxq_t ifl_rxq; 393 uint8_t ifl_id; 394 bus_dma_tag_t ifl_buf_tag; 395 iflib_dma_info_t ifl_ifdi; 396 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 397 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 398 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 399 } __aligned(CACHE_LINE_SIZE); 400 401 static inline qidx_t 402 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 403 { 404 qidx_t used; 405 406 if (pidx > cidx) 407 used = pidx - cidx; 408 else if (pidx < cidx) 409 used = size - cidx + pidx; 410 else if (gen == 0 && pidx == cidx) 411 used = 0; 412 else if (gen == 1 && pidx == cidx) 413 used = size; 414 else 415 panic("bad state"); 416 417 return (used); 418 } 419 420 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 421 422 #define IDXDIFF(head, tail, wrap) \ 423 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 424 425 struct iflib_rxq { 426 /* If there is a separate completion queue - 427 * these are the cq cidx and pidx. Otherwise 428 * these are unused. 429 */ 430 qidx_t ifr_size; 431 qidx_t ifr_cq_cidx; 432 qidx_t ifr_cq_pidx; 433 uint8_t ifr_cq_gen; 434 uint8_t ifr_fl_offset; 435 436 if_ctx_t ifr_ctx; 437 iflib_fl_t ifr_fl; 438 uint64_t ifr_rx_irq; 439 struct pfil_head *pfil; 440 uint16_t ifr_id; 441 uint8_t ifr_lro_enabled; 442 uint8_t ifr_nfl; 443 uint8_t ifr_ntxqirq; 444 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 445 struct lro_ctrl ifr_lc; 446 struct grouptask ifr_task; 447 struct iflib_filter_info ifr_filter_info; 448 iflib_dma_info_t ifr_ifdi; 449 450 /* dynamically allocate if any drivers need a value substantially larger than this */ 451 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 452 #ifdef IFLIB_DIAGNOSTICS 453 uint64_t ifr_cpu_exec_count[256]; 454 #endif 455 } __aligned(CACHE_LINE_SIZE); 456 457 typedef struct if_rxsd { 458 caddr_t *ifsd_cl; 459 iflib_fl_t ifsd_fl; 460 qidx_t ifsd_cidx; 461 } *if_rxsd_t; 462 463 /* multiple of word size */ 464 #ifdef __LP64__ 465 #define PKT_INFO_SIZE 6 466 #define RXD_INFO_SIZE 5 467 #define PKT_TYPE uint64_t 468 #else 469 #define PKT_INFO_SIZE 11 470 #define RXD_INFO_SIZE 8 471 #define PKT_TYPE uint32_t 472 #endif 473 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 474 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 475 476 typedef struct if_pkt_info_pad { 477 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 478 } *if_pkt_info_pad_t; 479 typedef struct if_rxd_info_pad { 480 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 481 } *if_rxd_info_pad_t; 482 483 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 484 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 485 486 487 static inline void 488 pkt_info_zero(if_pkt_info_t pi) 489 { 490 if_pkt_info_pad_t pi_pad; 491 492 pi_pad = (if_pkt_info_pad_t)pi; 493 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 494 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 495 #ifndef __LP64__ 496 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 497 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 498 #endif 499 } 500 501 static device_method_t iflib_pseudo_methods[] = { 502 DEVMETHOD(device_attach, noop_attach), 503 DEVMETHOD(device_detach, iflib_pseudo_detach), 504 DEVMETHOD_END 505 }; 506 507 driver_t iflib_pseudodriver = { 508 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 509 }; 510 511 static inline void 512 rxd_info_zero(if_rxd_info_t ri) 513 { 514 if_rxd_info_pad_t ri_pad; 515 int i; 516 517 ri_pad = (if_rxd_info_pad_t)ri; 518 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 519 ri_pad->rxd_val[i] = 0; 520 ri_pad->rxd_val[i+1] = 0; 521 ri_pad->rxd_val[i+2] = 0; 522 ri_pad->rxd_val[i+3] = 0; 523 } 524 #ifdef __LP64__ 525 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 526 #endif 527 } 528 529 /* 530 * Only allow a single packet to take up most 1/nth of the tx ring 531 */ 532 #define MAX_SINGLE_PACKET_FRACTION 12 533 #define IF_BAD_DMA (bus_addr_t)-1 534 535 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 536 537 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 538 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 539 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 540 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 541 542 543 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 544 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 545 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 546 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 547 548 549 550 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 551 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 552 553 void 554 iflib_set_detach(if_ctx_t ctx) 555 { 556 STATE_LOCK(ctx); 557 ctx->ifc_flags |= IFC_IN_DETACH; 558 STATE_UNLOCK(ctx); 559 } 560 561 /* Our boot-time initialization hook */ 562 static int iflib_module_event_handler(module_t, int, void *); 563 564 static moduledata_t iflib_moduledata = { 565 "iflib", 566 iflib_module_event_handler, 567 NULL 568 }; 569 570 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 571 MODULE_VERSION(iflib, 1); 572 573 MODULE_DEPEND(iflib, pci, 1, 1, 1); 574 MODULE_DEPEND(iflib, ether, 1, 1, 1); 575 576 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 577 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 578 579 #ifndef IFLIB_DEBUG_COUNTERS 580 #ifdef INVARIANTS 581 #define IFLIB_DEBUG_COUNTERS 1 582 #else 583 #define IFLIB_DEBUG_COUNTERS 0 584 #endif /* !INVARIANTS */ 585 #endif 586 587 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 588 "iflib driver parameters"); 589 590 /* 591 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 592 */ 593 static int iflib_min_tx_latency = 0; 594 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 595 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 596 static int iflib_no_tx_batch = 0; 597 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 598 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 599 600 601 #if IFLIB_DEBUG_COUNTERS 602 603 static int iflib_tx_seen; 604 static int iflib_tx_sent; 605 static int iflib_tx_encap; 606 static int iflib_rx_allocs; 607 static int iflib_fl_refills; 608 static int iflib_fl_refills_large; 609 static int iflib_tx_frees; 610 611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 612 &iflib_tx_seen, 0, "# tx mbufs seen"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 614 &iflib_tx_sent, 0, "# tx mbufs sent"); 615 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 616 &iflib_tx_encap, 0, "# tx mbufs encapped"); 617 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 618 &iflib_tx_frees, 0, "# tx frees"); 619 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 620 &iflib_rx_allocs, 0, "# rx allocations"); 621 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 622 &iflib_fl_refills, 0, "# refills"); 623 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 624 &iflib_fl_refills_large, 0, "# large refills"); 625 626 627 static int iflib_txq_drain_flushing; 628 static int iflib_txq_drain_oactive; 629 static int iflib_txq_drain_notready; 630 631 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 632 &iflib_txq_drain_flushing, 0, "# drain flushes"); 633 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 634 &iflib_txq_drain_oactive, 0, "# drain oactives"); 635 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 636 &iflib_txq_drain_notready, 0, "# drain notready"); 637 638 639 static int iflib_encap_load_mbuf_fail; 640 static int iflib_encap_pad_mbuf_fail; 641 static int iflib_encap_txq_avail_fail; 642 static int iflib_encap_txd_encap_fail; 643 644 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 645 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 646 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 647 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 648 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 649 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 650 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 651 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 652 653 static int iflib_task_fn_rxs; 654 static int iflib_rx_intr_enables; 655 static int iflib_fast_intrs; 656 static int iflib_rx_unavail; 657 static int iflib_rx_ctx_inactive; 658 static int iflib_rx_if_input; 659 static int iflib_rxd_flush; 660 661 static int iflib_verbose_debug; 662 663 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 664 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 666 &iflib_rx_intr_enables, 0, "# rx intr enables"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 668 &iflib_fast_intrs, 0, "# fast_intr calls"); 669 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 670 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 671 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 672 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 673 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 674 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 675 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 676 &iflib_rxd_flush, 0, "# times rxd_flush called"); 677 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 678 &iflib_verbose_debug, 0, "enable verbose debugging"); 679 680 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 681 static void 682 iflib_debug_reset(void) 683 { 684 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 685 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 686 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 687 iflib_txq_drain_notready = 688 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 689 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 690 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 691 iflib_rx_unavail = 692 iflib_rx_ctx_inactive = iflib_rx_if_input = 693 iflib_rxd_flush = 0; 694 } 695 696 #else 697 #define DBG_COUNTER_INC(name) 698 static void iflib_debug_reset(void) {} 699 #endif 700 701 #define IFLIB_DEBUG 0 702 703 static void iflib_tx_structures_free(if_ctx_t ctx); 704 static void iflib_rx_structures_free(if_ctx_t ctx); 705 static int iflib_queues_alloc(if_ctx_t ctx); 706 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 707 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 708 static int iflib_qset_structures_setup(if_ctx_t ctx); 709 static int iflib_msix_init(if_ctx_t ctx); 710 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 711 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 712 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 713 #ifdef ALTQ 714 static void iflib_altq_if_start(if_t ifp); 715 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 716 #endif 717 static int iflib_register(if_ctx_t); 718 static void iflib_init_locked(if_ctx_t ctx); 719 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 720 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 721 static void iflib_ifmp_purge(iflib_txq_t txq); 722 static void _iflib_pre_assert(if_softc_ctx_t scctx); 723 static void iflib_if_init_locked(if_ctx_t ctx); 724 static void iflib_free_intr_mem(if_ctx_t ctx); 725 #ifndef __NO_STRICT_ALIGNMENT 726 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 727 #endif 728 729 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 730 SLIST_HEAD_INITIALIZER(cpu_offsets); 731 struct cpu_offset { 732 SLIST_ENTRY(cpu_offset) entries; 733 cpuset_t set; 734 unsigned int refcount; 735 uint16_t offset; 736 }; 737 static struct mtx cpu_offset_mtx; 738 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 739 MTX_DEF); 740 741 NETDUMP_DEFINE(iflib); 742 743 #ifdef DEV_NETMAP 744 #include <sys/selinfo.h> 745 #include <net/netmap.h> 746 #include <dev/netmap/netmap_kern.h> 747 748 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 749 750 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 751 752 /* 753 * device-specific sysctl variables: 754 * 755 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 756 * During regular operations the CRC is stripped, but on some 757 * hardware reception of frames not multiple of 64 is slower, 758 * so using crcstrip=0 helps in benchmarks. 759 * 760 * iflib_rx_miss, iflib_rx_miss_bufs: 761 * count packets that might be missed due to lost interrupts. 762 */ 763 SYSCTL_DECL(_dev_netmap); 764 /* 765 * The xl driver by default strips CRCs and we do not override it. 766 */ 767 768 int iflib_crcstrip = 1; 769 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 770 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 771 772 int iflib_rx_miss, iflib_rx_miss_bufs; 773 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 774 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 775 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 776 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 777 778 /* 779 * Register/unregister. We are already under netmap lock. 780 * Only called on the first register or the last unregister. 781 */ 782 static int 783 iflib_netmap_register(struct netmap_adapter *na, int onoff) 784 { 785 struct ifnet *ifp = na->ifp; 786 if_ctx_t ctx = ifp->if_softc; 787 int status; 788 789 CTX_LOCK(ctx); 790 IFDI_INTR_DISABLE(ctx); 791 792 /* Tell the stack that the interface is no longer active */ 793 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 794 795 if (!CTX_IS_VF(ctx)) 796 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 797 798 /* enable or disable flags and callbacks in na and ifp */ 799 if (onoff) { 800 nm_set_native_flags(na); 801 } else { 802 nm_clear_native_flags(na); 803 } 804 iflib_stop(ctx); 805 iflib_init_locked(ctx); 806 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 807 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 808 if (status) 809 nm_clear_native_flags(na); 810 CTX_UNLOCK(ctx); 811 return (status); 812 } 813 814 static int 815 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 816 { 817 struct netmap_adapter *na = kring->na; 818 u_int const lim = kring->nkr_num_slots - 1; 819 u_int head = kring->rhead; 820 struct netmap_ring *ring = kring->ring; 821 bus_dmamap_t *map; 822 struct if_rxd_update iru; 823 if_ctx_t ctx = rxq->ifr_ctx; 824 iflib_fl_t fl = &rxq->ifr_fl[0]; 825 uint32_t refill_pidx, nic_i; 826 #if IFLIB_DEBUG_COUNTERS 827 int rf_count = 0; 828 #endif 829 830 if (nm_i == head && __predict_true(!init)) 831 return 0; 832 iru_init(&iru, rxq, 0 /* flid */); 833 map = fl->ifl_sds.ifsd_map; 834 refill_pidx = netmap_idx_k2n(kring, nm_i); 835 /* 836 * IMPORTANT: we must leave one free slot in the ring, 837 * so move head back by one unit 838 */ 839 head = nm_prev(head, lim); 840 nic_i = UINT_MAX; 841 DBG_COUNTER_INC(fl_refills); 842 while (nm_i != head) { 843 #if IFLIB_DEBUG_COUNTERS 844 if (++rf_count == 9) 845 DBG_COUNTER_INC(fl_refills_large); 846 #endif 847 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 848 struct netmap_slot *slot = &ring->slot[nm_i]; 849 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 850 uint32_t nic_i_dma = refill_pidx; 851 nic_i = netmap_idx_k2n(kring, nm_i); 852 853 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 854 855 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 856 return netmap_ring_reinit(kring); 857 858 fl->ifl_vm_addrs[tmp_pidx] = addr; 859 if (__predict_false(init)) { 860 netmap_load_map(na, fl->ifl_buf_tag, 861 map[nic_i], addr); 862 } else if (slot->flags & NS_BUF_CHANGED) { 863 /* buffer has changed, reload map */ 864 netmap_reload_map(na, fl->ifl_buf_tag, 865 map[nic_i], addr); 866 } 867 slot->flags &= ~NS_BUF_CHANGED; 868 869 nm_i = nm_next(nm_i, lim); 870 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 871 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 872 continue; 873 874 iru.iru_pidx = refill_pidx; 875 iru.iru_count = tmp_pidx+1; 876 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 877 refill_pidx = nic_i; 878 for (int n = 0; n < iru.iru_count; n++) { 879 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma], 880 BUS_DMASYNC_PREREAD); 881 /* XXX - change this to not use the netmap func*/ 882 nic_i_dma = nm_next(nic_i_dma, lim); 883 } 884 } 885 } 886 kring->nr_hwcur = head; 887 888 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 889 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 890 if (__predict_true(nic_i != UINT_MAX)) { 891 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 892 DBG_COUNTER_INC(rxd_flush); 893 } 894 return (0); 895 } 896 897 /* 898 * Reconcile kernel and user view of the transmit ring. 899 * 900 * All information is in the kring. 901 * Userspace wants to send packets up to the one before kring->rhead, 902 * kernel knows kring->nr_hwcur is the first unsent packet. 903 * 904 * Here we push packets out (as many as possible), and possibly 905 * reclaim buffers from previously completed transmission. 906 * 907 * The caller (netmap) guarantees that there is only one instance 908 * running at any time. Any interference with other driver 909 * methods should be handled by the individual drivers. 910 */ 911 static int 912 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 913 { 914 struct netmap_adapter *na = kring->na; 915 struct ifnet *ifp = na->ifp; 916 struct netmap_ring *ring = kring->ring; 917 u_int nm_i; /* index into the netmap kring */ 918 u_int nic_i; /* index into the NIC ring */ 919 u_int n; 920 u_int const lim = kring->nkr_num_slots - 1; 921 u_int const head = kring->rhead; 922 struct if_pkt_info pi; 923 924 /* 925 * interrupts on every tx packet are expensive so request 926 * them every half ring, or where NS_REPORT is set 927 */ 928 u_int report_frequency = kring->nkr_num_slots >> 1; 929 /* device-specific */ 930 if_ctx_t ctx = ifp->if_softc; 931 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 932 933 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 934 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 935 936 /* 937 * First part: process new packets to send. 938 * nm_i is the current index in the netmap kring, 939 * nic_i is the corresponding index in the NIC ring. 940 * 941 * If we have packets to send (nm_i != head) 942 * iterate over the netmap ring, fetch length and update 943 * the corresponding slot in the NIC ring. Some drivers also 944 * need to update the buffer's physical address in the NIC slot 945 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 946 * 947 * The netmap_reload_map() calls is especially expensive, 948 * even when (as in this case) the tag is 0, so do only 949 * when the buffer has actually changed. 950 * 951 * If possible do not set the report/intr bit on all slots, 952 * but only a few times per ring or when NS_REPORT is set. 953 * 954 * Finally, on 10G and faster drivers, it might be useful 955 * to prefetch the next slot and txr entry. 956 */ 957 958 nm_i = kring->nr_hwcur; 959 if (nm_i != head) { /* we have new packets to send */ 960 pkt_info_zero(&pi); 961 pi.ipi_segs = txq->ift_segs; 962 pi.ipi_qsidx = kring->ring_id; 963 nic_i = netmap_idx_k2n(kring, nm_i); 964 965 __builtin_prefetch(&ring->slot[nm_i]); 966 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 967 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 968 969 for (n = 0; nm_i != head; n++) { 970 struct netmap_slot *slot = &ring->slot[nm_i]; 971 u_int len = slot->len; 972 uint64_t paddr; 973 void *addr = PNMB(na, slot, &paddr); 974 int flags = (slot->flags & NS_REPORT || 975 nic_i == 0 || nic_i == report_frequency) ? 976 IPI_TX_INTR : 0; 977 978 /* device-specific */ 979 pi.ipi_len = len; 980 pi.ipi_segs[0].ds_addr = paddr; 981 pi.ipi_segs[0].ds_len = len; 982 pi.ipi_nsegs = 1; 983 pi.ipi_ndescs = 0; 984 pi.ipi_pidx = nic_i; 985 pi.ipi_flags = flags; 986 987 /* Fill the slot in the NIC ring. */ 988 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 989 DBG_COUNTER_INC(tx_encap); 990 991 /* prefetch for next round */ 992 __builtin_prefetch(&ring->slot[nm_i + 1]); 993 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 994 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 995 996 NM_CHECK_ADDR_LEN(na, addr, len); 997 998 if (slot->flags & NS_BUF_CHANGED) { 999 /* buffer has changed, reload map */ 1000 netmap_reload_map(na, txq->ift_buf_tag, 1001 txq->ift_sds.ifsd_map[nic_i], addr); 1002 } 1003 /* make sure changes to the buffer are synced */ 1004 bus_dmamap_sync(txq->ift_buf_tag, 1005 txq->ift_sds.ifsd_map[nic_i], 1006 BUS_DMASYNC_PREWRITE); 1007 1008 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1009 nm_i = nm_next(nm_i, lim); 1010 nic_i = nm_next(nic_i, lim); 1011 } 1012 kring->nr_hwcur = nm_i; 1013 1014 /* synchronize the NIC ring */ 1015 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1016 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1017 1018 /* (re)start the tx unit up to slot nic_i (excluded) */ 1019 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1020 } 1021 1022 /* 1023 * Second part: reclaim buffers for completed transmissions. 1024 * 1025 * If there are unclaimed buffers, attempt to reclaim them. 1026 * If none are reclaimed, and TX IRQs are not in use, do an initial 1027 * minimal delay, then trigger the tx handler which will spin in the 1028 * group task queue. 1029 */ 1030 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1031 if (iflib_tx_credits_update(ctx, txq)) { 1032 /* some tx completed, increment avail */ 1033 nic_i = txq->ift_cidx_processed; 1034 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1035 } 1036 } 1037 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1038 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1039 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1040 iflib_timer, txq, txq->ift_timer.c_cpu); 1041 } 1042 return (0); 1043 } 1044 1045 /* 1046 * Reconcile kernel and user view of the receive ring. 1047 * Same as for the txsync, this routine must be efficient. 1048 * The caller guarantees a single invocations, but races against 1049 * the rest of the driver should be handled here. 1050 * 1051 * On call, kring->rhead is the first packet that userspace wants 1052 * to keep, and kring->rcur is the wakeup point. 1053 * The kernel has previously reported packets up to kring->rtail. 1054 * 1055 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1056 * of whether or not we received an interrupt. 1057 */ 1058 static int 1059 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1060 { 1061 struct netmap_adapter *na = kring->na; 1062 struct netmap_ring *ring = kring->ring; 1063 iflib_fl_t fl; 1064 uint32_t nm_i; /* index into the netmap ring */ 1065 uint32_t nic_i; /* index into the NIC ring */ 1066 u_int i, n; 1067 u_int const lim = kring->nkr_num_slots - 1; 1068 u_int const head = kring->rhead; 1069 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1070 struct if_rxd_info ri; 1071 1072 struct ifnet *ifp = na->ifp; 1073 if_ctx_t ctx = ifp->if_softc; 1074 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1075 if (head > lim) 1076 return netmap_ring_reinit(kring); 1077 1078 /* 1079 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far. 1080 */ 1081 1082 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1083 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1084 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1085 } 1086 1087 /* 1088 * First part: import newly received packets. 1089 * 1090 * nm_i is the index of the next free slot in the netmap ring, 1091 * nic_i is the index of the next received packet in the NIC ring, 1092 * and they may differ in case if_init() has been called while 1093 * in netmap mode. For the receive ring we have 1094 * 1095 * nic_i = rxr->next_check; 1096 * nm_i = kring->nr_hwtail (previous) 1097 * and 1098 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1099 * 1100 * rxr->next_check is set to 0 on a ring reinit 1101 */ 1102 if (netmap_no_pendintr || force_update) { 1103 int crclen = iflib_crcstrip ? 0 : 4; 1104 int error, avail; 1105 1106 for (i = 0; i < rxq->ifr_nfl; i++) { 1107 fl = &rxq->ifr_fl[i]; 1108 nic_i = fl->ifl_cidx; 1109 nm_i = netmap_idx_n2k(kring, nic_i); 1110 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1111 rxq->ifr_id, nic_i, USHRT_MAX); 1112 for (n = 0; avail > 0; n++, avail--) { 1113 rxd_info_zero(&ri); 1114 ri.iri_frags = rxq->ifr_frags; 1115 ri.iri_qsidx = kring->ring_id; 1116 ri.iri_ifp = ctx->ifc_ifp; 1117 ri.iri_cidx = nic_i; 1118 1119 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1120 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1121 ring->slot[nm_i].flags = 0; 1122 bus_dmamap_sync(fl->ifl_buf_tag, 1123 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1124 nm_i = nm_next(nm_i, lim); 1125 nic_i = nm_next(nic_i, lim); 1126 } 1127 if (n) { /* update the state variables */ 1128 if (netmap_no_pendintr && !force_update) { 1129 /* diagnostics */ 1130 iflib_rx_miss ++; 1131 iflib_rx_miss_bufs += n; 1132 } 1133 fl->ifl_cidx = nic_i; 1134 kring->nr_hwtail = nm_i; 1135 } 1136 kring->nr_kflags &= ~NKR_PENDINTR; 1137 } 1138 } 1139 /* 1140 * Second part: skip past packets that userspace has released. 1141 * (kring->nr_hwcur to head excluded), 1142 * and make the buffers available for reception. 1143 * As usual nm_i is the index in the netmap ring, 1144 * nic_i is the index in the NIC ring, and 1145 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1146 */ 1147 /* XXX not sure how this will work with multiple free lists */ 1148 nm_i = kring->nr_hwcur; 1149 1150 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1151 } 1152 1153 static void 1154 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1155 { 1156 struct ifnet *ifp = na->ifp; 1157 if_ctx_t ctx = ifp->if_softc; 1158 1159 CTX_LOCK(ctx); 1160 if (onoff) { 1161 IFDI_INTR_ENABLE(ctx); 1162 } else { 1163 IFDI_INTR_DISABLE(ctx); 1164 } 1165 CTX_UNLOCK(ctx); 1166 } 1167 1168 1169 static int 1170 iflib_netmap_attach(if_ctx_t ctx) 1171 { 1172 struct netmap_adapter na; 1173 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1174 1175 bzero(&na, sizeof(na)); 1176 1177 na.ifp = ctx->ifc_ifp; 1178 na.na_flags = NAF_BDG_MAYSLEEP; 1179 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1180 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1181 1182 na.num_tx_desc = scctx->isc_ntxd[0]; 1183 na.num_rx_desc = scctx->isc_nrxd[0]; 1184 na.nm_txsync = iflib_netmap_txsync; 1185 na.nm_rxsync = iflib_netmap_rxsync; 1186 na.nm_register = iflib_netmap_register; 1187 na.nm_intr = iflib_netmap_intr; 1188 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1189 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1190 return (netmap_attach(&na)); 1191 } 1192 1193 static void 1194 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1195 { 1196 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1197 struct netmap_slot *slot; 1198 1199 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1200 if (slot == NULL) 1201 return; 1202 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1203 1204 /* 1205 * In netmap mode, set the map for the packet buffer. 1206 * NOTE: Some drivers (not this one) also need to set 1207 * the physical buffer address in the NIC ring. 1208 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1209 * netmap slot index, si 1210 */ 1211 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1212 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1213 NMB(na, slot + si)); 1214 } 1215 } 1216 1217 static void 1218 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1219 { 1220 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1221 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1222 struct netmap_slot *slot; 1223 uint32_t nm_i; 1224 1225 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1226 if (slot == NULL) 1227 return; 1228 nm_i = netmap_idx_n2k(kring, 0); 1229 netmap_fl_refill(rxq, kring, nm_i, true); 1230 } 1231 1232 static void 1233 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on) 1234 { 1235 struct netmap_kring *kring; 1236 uint16_t txqid; 1237 1238 txqid = txq->ift_id; 1239 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1240 1241 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1242 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1243 BUS_DMASYNC_POSTREAD); 1244 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1245 netmap_tx_irq(ctx->ifc_ifp, txqid); 1246 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1247 if (hz < 2000) 1248 *reset_on = 1; 1249 else 1250 *reset_on = hz / 1000; 1251 } 1252 } 1253 } 1254 1255 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1256 1257 #else 1258 #define iflib_netmap_txq_init(ctx, txq) 1259 #define iflib_netmap_rxq_init(ctx, rxq) 1260 #define iflib_netmap_detach(ifp) 1261 1262 #define iflib_netmap_attach(ctx) (0) 1263 #define netmap_rx_irq(ifp, qid, budget) (0) 1264 #define netmap_tx_irq(ifp, qid) do {} while (0) 1265 #define iflib_netmap_timer_adjust(ctx, txq, reset_on) 1266 1267 #endif 1268 1269 #if defined(__i386__) || defined(__amd64__) 1270 static __inline void 1271 prefetch(void *x) 1272 { 1273 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1274 } 1275 static __inline void 1276 prefetch2cachelines(void *x) 1277 { 1278 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1279 #if (CACHE_LINE_SIZE < 128) 1280 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1281 #endif 1282 } 1283 #else 1284 #define prefetch(x) 1285 #define prefetch2cachelines(x) 1286 #endif 1287 1288 static void 1289 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1290 { 1291 iflib_fl_t fl; 1292 1293 fl = &rxq->ifr_fl[flid]; 1294 iru->iru_paddrs = fl->ifl_bus_addrs; 1295 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1296 iru->iru_idxs = fl->ifl_rxd_idxs; 1297 iru->iru_qsidx = rxq->ifr_id; 1298 iru->iru_buf_size = fl->ifl_buf_size; 1299 iru->iru_flidx = fl->ifl_id; 1300 } 1301 1302 static void 1303 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1304 { 1305 if (err) 1306 return; 1307 *(bus_addr_t *) arg = segs[0].ds_addr; 1308 } 1309 1310 int 1311 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1312 { 1313 int err; 1314 device_t dev = ctx->ifc_dev; 1315 1316 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1317 align, 0, /* alignment, bounds */ 1318 BUS_SPACE_MAXADDR, /* lowaddr */ 1319 BUS_SPACE_MAXADDR, /* highaddr */ 1320 NULL, NULL, /* filter, filterarg */ 1321 size, /* maxsize */ 1322 1, /* nsegments */ 1323 size, /* maxsegsize */ 1324 BUS_DMA_ALLOCNOW, /* flags */ 1325 NULL, /* lockfunc */ 1326 NULL, /* lockarg */ 1327 &dma->idi_tag); 1328 if (err) { 1329 device_printf(dev, 1330 "%s: bus_dma_tag_create failed: %d\n", 1331 __func__, err); 1332 goto fail_0; 1333 } 1334 1335 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1336 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1337 if (err) { 1338 device_printf(dev, 1339 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1340 __func__, (uintmax_t)size, err); 1341 goto fail_1; 1342 } 1343 1344 dma->idi_paddr = IF_BAD_DMA; 1345 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1346 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1347 if (err || dma->idi_paddr == IF_BAD_DMA) { 1348 device_printf(dev, 1349 "%s: bus_dmamap_load failed: %d\n", 1350 __func__, err); 1351 goto fail_2; 1352 } 1353 1354 dma->idi_size = size; 1355 return (0); 1356 1357 fail_2: 1358 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1359 fail_1: 1360 bus_dma_tag_destroy(dma->idi_tag); 1361 fail_0: 1362 dma->idi_tag = NULL; 1363 1364 return (err); 1365 } 1366 1367 int 1368 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1369 { 1370 if_shared_ctx_t sctx = ctx->ifc_sctx; 1371 1372 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1373 1374 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1375 } 1376 1377 int 1378 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1379 { 1380 int i, err; 1381 iflib_dma_info_t *dmaiter; 1382 1383 dmaiter = dmalist; 1384 for (i = 0; i < count; i++, dmaiter++) { 1385 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1386 break; 1387 } 1388 if (err) 1389 iflib_dma_free_multi(dmalist, i); 1390 return (err); 1391 } 1392 1393 void 1394 iflib_dma_free(iflib_dma_info_t dma) 1395 { 1396 if (dma->idi_tag == NULL) 1397 return; 1398 if (dma->idi_paddr != IF_BAD_DMA) { 1399 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1400 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1401 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1402 dma->idi_paddr = IF_BAD_DMA; 1403 } 1404 if (dma->idi_vaddr != NULL) { 1405 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1406 dma->idi_vaddr = NULL; 1407 } 1408 bus_dma_tag_destroy(dma->idi_tag); 1409 dma->idi_tag = NULL; 1410 } 1411 1412 void 1413 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1414 { 1415 int i; 1416 iflib_dma_info_t *dmaiter = dmalist; 1417 1418 for (i = 0; i < count; i++, dmaiter++) 1419 iflib_dma_free(*dmaiter); 1420 } 1421 1422 #ifdef EARLY_AP_STARTUP 1423 static const int iflib_started = 1; 1424 #else 1425 /* 1426 * We used to abuse the smp_started flag to decide if the queues have been 1427 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1428 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1429 * is set. Run a SYSINIT() strictly after that to just set a usable 1430 * completion flag. 1431 */ 1432 1433 static int iflib_started; 1434 1435 static void 1436 iflib_record_started(void *arg) 1437 { 1438 iflib_started = 1; 1439 } 1440 1441 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1442 iflib_record_started, NULL); 1443 #endif 1444 1445 static int 1446 iflib_fast_intr(void *arg) 1447 { 1448 iflib_filter_info_t info = arg; 1449 struct grouptask *gtask = info->ifi_task; 1450 int result; 1451 1452 if (!iflib_started) 1453 return (FILTER_STRAY); 1454 1455 DBG_COUNTER_INC(fast_intrs); 1456 if (info->ifi_filter != NULL) { 1457 result = info->ifi_filter(info->ifi_filter_arg); 1458 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1459 return (result); 1460 } 1461 1462 GROUPTASK_ENQUEUE(gtask); 1463 return (FILTER_HANDLED); 1464 } 1465 1466 static int 1467 iflib_fast_intr_rxtx(void *arg) 1468 { 1469 iflib_filter_info_t info = arg; 1470 struct grouptask *gtask = info->ifi_task; 1471 if_ctx_t ctx; 1472 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1473 iflib_txq_t txq; 1474 void *sc; 1475 int i, cidx, result; 1476 qidx_t txqid; 1477 1478 if (!iflib_started) 1479 return (FILTER_STRAY); 1480 1481 DBG_COUNTER_INC(fast_intrs); 1482 if (info->ifi_filter != NULL) { 1483 result = info->ifi_filter(info->ifi_filter_arg); 1484 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1485 return (result); 1486 } 1487 1488 ctx = rxq->ifr_ctx; 1489 sc = ctx->ifc_softc; 1490 MPASS(rxq->ifr_ntxqirq); 1491 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1492 txqid = rxq->ifr_txqid[i]; 1493 txq = &ctx->ifc_txqs[txqid]; 1494 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1495 BUS_DMASYNC_POSTREAD); 1496 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1497 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1498 continue; 1499 } 1500 GROUPTASK_ENQUEUE(&txq->ift_task); 1501 } 1502 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1503 cidx = rxq->ifr_cq_cidx; 1504 else 1505 cidx = rxq->ifr_fl[0].ifl_cidx; 1506 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1507 GROUPTASK_ENQUEUE(gtask); 1508 else { 1509 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1510 DBG_COUNTER_INC(rx_intr_enables); 1511 } 1512 return (FILTER_HANDLED); 1513 } 1514 1515 1516 static int 1517 iflib_fast_intr_ctx(void *arg) 1518 { 1519 iflib_filter_info_t info = arg; 1520 struct grouptask *gtask = info->ifi_task; 1521 int result; 1522 1523 if (!iflib_started) 1524 return (FILTER_STRAY); 1525 1526 DBG_COUNTER_INC(fast_intrs); 1527 if (info->ifi_filter != NULL) { 1528 result = info->ifi_filter(info->ifi_filter_arg); 1529 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1530 return (result); 1531 } 1532 1533 GROUPTASK_ENQUEUE(gtask); 1534 return (FILTER_HANDLED); 1535 } 1536 1537 static int 1538 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1539 driver_filter_t filter, driver_intr_t handler, void *arg, 1540 const char *name) 1541 { 1542 int rc, flags; 1543 struct resource *res; 1544 void *tag = NULL; 1545 device_t dev = ctx->ifc_dev; 1546 1547 flags = RF_ACTIVE; 1548 if (ctx->ifc_flags & IFC_LEGACY) 1549 flags |= RF_SHAREABLE; 1550 MPASS(rid < 512); 1551 irq->ii_rid = rid; 1552 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1553 if (res == NULL) { 1554 device_printf(dev, 1555 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1556 return (ENOMEM); 1557 } 1558 irq->ii_res = res; 1559 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1560 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1561 filter, handler, arg, &tag); 1562 if (rc != 0) { 1563 device_printf(dev, 1564 "failed to setup interrupt for rid %d, name %s: %d\n", 1565 rid, name ? name : "unknown", rc); 1566 return (rc); 1567 } else if (name) 1568 bus_describe_intr(dev, res, tag, "%s", name); 1569 1570 irq->ii_tag = tag; 1571 return (0); 1572 } 1573 1574 1575 /********************************************************************* 1576 * 1577 * Allocate DMA resources for TX buffers as well as memory for the TX 1578 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1579 * iflib_sw_tx_desc_array structure, storing all the information that 1580 * is needed to transmit a packet on the wire. This is called only 1581 * once at attach, setup is done every reset. 1582 * 1583 **********************************************************************/ 1584 static int 1585 iflib_txsd_alloc(iflib_txq_t txq) 1586 { 1587 if_ctx_t ctx = txq->ift_ctx; 1588 if_shared_ctx_t sctx = ctx->ifc_sctx; 1589 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1590 device_t dev = ctx->ifc_dev; 1591 bus_size_t tsomaxsize; 1592 int err, nsegments, ntsosegments; 1593 bool tso; 1594 1595 nsegments = scctx->isc_tx_nsegments; 1596 ntsosegments = scctx->isc_tx_tso_segments_max; 1597 tsomaxsize = scctx->isc_tx_tso_size_max; 1598 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1599 tsomaxsize += sizeof(struct ether_vlan_header); 1600 MPASS(scctx->isc_ntxd[0] > 0); 1601 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1602 MPASS(nsegments > 0); 1603 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1604 MPASS(ntsosegments > 0); 1605 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1606 } 1607 1608 /* 1609 * Set up DMA tags for TX buffers. 1610 */ 1611 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1612 1, 0, /* alignment, bounds */ 1613 BUS_SPACE_MAXADDR, /* lowaddr */ 1614 BUS_SPACE_MAXADDR, /* highaddr */ 1615 NULL, NULL, /* filter, filterarg */ 1616 sctx->isc_tx_maxsize, /* maxsize */ 1617 nsegments, /* nsegments */ 1618 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1619 0, /* flags */ 1620 NULL, /* lockfunc */ 1621 NULL, /* lockfuncarg */ 1622 &txq->ift_buf_tag))) { 1623 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1624 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1625 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1626 goto fail; 1627 } 1628 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1629 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1630 1, 0, /* alignment, bounds */ 1631 BUS_SPACE_MAXADDR, /* lowaddr */ 1632 BUS_SPACE_MAXADDR, /* highaddr */ 1633 NULL, NULL, /* filter, filterarg */ 1634 tsomaxsize, /* maxsize */ 1635 ntsosegments, /* nsegments */ 1636 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1637 0, /* flags */ 1638 NULL, /* lockfunc */ 1639 NULL, /* lockfuncarg */ 1640 &txq->ift_tso_buf_tag))) { 1641 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1642 err); 1643 goto fail; 1644 } 1645 1646 /* Allocate memory for the TX mbuf map. */ 1647 if (!(txq->ift_sds.ifsd_m = 1648 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1649 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1650 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1651 err = ENOMEM; 1652 goto fail; 1653 } 1654 1655 /* 1656 * Create the DMA maps for TX buffers. 1657 */ 1658 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1659 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1660 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1661 device_printf(dev, 1662 "Unable to allocate TX buffer DMA map memory\n"); 1663 err = ENOMEM; 1664 goto fail; 1665 } 1666 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1667 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1668 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1669 device_printf(dev, 1670 "Unable to allocate TSO TX buffer map memory\n"); 1671 err = ENOMEM; 1672 goto fail; 1673 } 1674 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1675 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1676 &txq->ift_sds.ifsd_map[i]); 1677 if (err != 0) { 1678 device_printf(dev, "Unable to create TX DMA map\n"); 1679 goto fail; 1680 } 1681 if (!tso) 1682 continue; 1683 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1684 &txq->ift_sds.ifsd_tso_map[i]); 1685 if (err != 0) { 1686 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1687 goto fail; 1688 } 1689 } 1690 return (0); 1691 fail: 1692 /* We free all, it handles case where we are in the middle */ 1693 iflib_tx_structures_free(ctx); 1694 return (err); 1695 } 1696 1697 static void 1698 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1699 { 1700 bus_dmamap_t map; 1701 1702 map = NULL; 1703 if (txq->ift_sds.ifsd_map != NULL) 1704 map = txq->ift_sds.ifsd_map[i]; 1705 if (map != NULL) { 1706 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1707 bus_dmamap_unload(txq->ift_buf_tag, map); 1708 bus_dmamap_destroy(txq->ift_buf_tag, map); 1709 txq->ift_sds.ifsd_map[i] = NULL; 1710 } 1711 1712 map = NULL; 1713 if (txq->ift_sds.ifsd_tso_map != NULL) 1714 map = txq->ift_sds.ifsd_tso_map[i]; 1715 if (map != NULL) { 1716 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1717 BUS_DMASYNC_POSTWRITE); 1718 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1719 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1720 txq->ift_sds.ifsd_tso_map[i] = NULL; 1721 } 1722 } 1723 1724 static void 1725 iflib_txq_destroy(iflib_txq_t txq) 1726 { 1727 if_ctx_t ctx = txq->ift_ctx; 1728 1729 for (int i = 0; i < txq->ift_size; i++) 1730 iflib_txsd_destroy(ctx, txq, i); 1731 if (txq->ift_sds.ifsd_map != NULL) { 1732 free(txq->ift_sds.ifsd_map, M_IFLIB); 1733 txq->ift_sds.ifsd_map = NULL; 1734 } 1735 if (txq->ift_sds.ifsd_tso_map != NULL) { 1736 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1737 txq->ift_sds.ifsd_tso_map = NULL; 1738 } 1739 if (txq->ift_sds.ifsd_m != NULL) { 1740 free(txq->ift_sds.ifsd_m, M_IFLIB); 1741 txq->ift_sds.ifsd_m = NULL; 1742 } 1743 if (txq->ift_buf_tag != NULL) { 1744 bus_dma_tag_destroy(txq->ift_buf_tag); 1745 txq->ift_buf_tag = NULL; 1746 } 1747 if (txq->ift_tso_buf_tag != NULL) { 1748 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1749 txq->ift_tso_buf_tag = NULL; 1750 } 1751 } 1752 1753 static void 1754 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1755 { 1756 struct mbuf **mp; 1757 1758 mp = &txq->ift_sds.ifsd_m[i]; 1759 if (*mp == NULL) 1760 return; 1761 1762 if (txq->ift_sds.ifsd_map != NULL) { 1763 bus_dmamap_sync(txq->ift_buf_tag, 1764 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1765 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1766 } 1767 if (txq->ift_sds.ifsd_tso_map != NULL) { 1768 bus_dmamap_sync(txq->ift_tso_buf_tag, 1769 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1770 bus_dmamap_unload(txq->ift_tso_buf_tag, 1771 txq->ift_sds.ifsd_tso_map[i]); 1772 } 1773 m_free(*mp); 1774 DBG_COUNTER_INC(tx_frees); 1775 *mp = NULL; 1776 } 1777 1778 static int 1779 iflib_txq_setup(iflib_txq_t txq) 1780 { 1781 if_ctx_t ctx = txq->ift_ctx; 1782 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1783 if_shared_ctx_t sctx = ctx->ifc_sctx; 1784 iflib_dma_info_t di; 1785 int i; 1786 1787 /* Set number of descriptors available */ 1788 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1789 /* XXX make configurable */ 1790 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1791 1792 /* Reset indices */ 1793 txq->ift_cidx_processed = 0; 1794 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1795 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1796 1797 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1798 bzero((void *)di->idi_vaddr, di->idi_size); 1799 1800 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1801 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1802 bus_dmamap_sync(di->idi_tag, di->idi_map, 1803 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1804 return (0); 1805 } 1806 1807 /********************************************************************* 1808 * 1809 * Allocate DMA resources for RX buffers as well as memory for the RX 1810 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1811 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1812 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1813 * Since we use use one entry in iflib_sw_rx_desc_array per received 1814 * packet, the maximum number of entries we'll need is equal to the 1815 * number of hardware receive descriptors that we've allocated. 1816 * 1817 **********************************************************************/ 1818 static int 1819 iflib_rxsd_alloc(iflib_rxq_t rxq) 1820 { 1821 if_ctx_t ctx = rxq->ifr_ctx; 1822 if_shared_ctx_t sctx = ctx->ifc_sctx; 1823 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1824 device_t dev = ctx->ifc_dev; 1825 iflib_fl_t fl; 1826 int err; 1827 1828 MPASS(scctx->isc_nrxd[0] > 0); 1829 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1830 1831 fl = rxq->ifr_fl; 1832 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1833 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1834 /* Set up DMA tag for RX buffers. */ 1835 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1836 1, 0, /* alignment, bounds */ 1837 BUS_SPACE_MAXADDR, /* lowaddr */ 1838 BUS_SPACE_MAXADDR, /* highaddr */ 1839 NULL, NULL, /* filter, filterarg */ 1840 sctx->isc_rx_maxsize, /* maxsize */ 1841 sctx->isc_rx_nsegments, /* nsegments */ 1842 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1843 0, /* flags */ 1844 NULL, /* lockfunc */ 1845 NULL, /* lockarg */ 1846 &fl->ifl_buf_tag); 1847 if (err) { 1848 device_printf(dev, 1849 "Unable to allocate RX DMA tag: %d\n", err); 1850 goto fail; 1851 } 1852 1853 /* Allocate memory for the RX mbuf map. */ 1854 if (!(fl->ifl_sds.ifsd_m = 1855 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1856 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1857 device_printf(dev, 1858 "Unable to allocate RX mbuf map memory\n"); 1859 err = ENOMEM; 1860 goto fail; 1861 } 1862 1863 /* Allocate memory for the direct RX cluster pointer map. */ 1864 if (!(fl->ifl_sds.ifsd_cl = 1865 (caddr_t *) malloc(sizeof(caddr_t) * 1866 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1867 device_printf(dev, 1868 "Unable to allocate RX cluster map memory\n"); 1869 err = ENOMEM; 1870 goto fail; 1871 } 1872 1873 /* Allocate memory for the RX cluster bus address map. */ 1874 if (!(fl->ifl_sds.ifsd_ba = 1875 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1876 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1877 device_printf(dev, 1878 "Unable to allocate RX bus address map memory\n"); 1879 err = ENOMEM; 1880 goto fail; 1881 } 1882 1883 /* 1884 * Create the DMA maps for RX buffers. 1885 */ 1886 if (!(fl->ifl_sds.ifsd_map = 1887 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1888 device_printf(dev, 1889 "Unable to allocate RX buffer DMA map memory\n"); 1890 err = ENOMEM; 1891 goto fail; 1892 } 1893 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1894 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1895 &fl->ifl_sds.ifsd_map[i]); 1896 if (err != 0) { 1897 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1898 goto fail; 1899 } 1900 } 1901 } 1902 return (0); 1903 1904 fail: 1905 iflib_rx_structures_free(ctx); 1906 return (err); 1907 } 1908 1909 1910 /* 1911 * Internal service routines 1912 */ 1913 1914 struct rxq_refill_cb_arg { 1915 int error; 1916 bus_dma_segment_t seg; 1917 int nseg; 1918 }; 1919 1920 static void 1921 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1922 { 1923 struct rxq_refill_cb_arg *cb_arg = arg; 1924 1925 cb_arg->error = error; 1926 cb_arg->seg = segs[0]; 1927 cb_arg->nseg = nseg; 1928 } 1929 1930 /** 1931 * rxq_refill - refill an rxq free-buffer list 1932 * @ctx: the iflib context 1933 * @rxq: the free-list to refill 1934 * @n: the number of new buffers to allocate 1935 * 1936 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1937 * The caller must assure that @n does not exceed the queue's capacity. 1938 */ 1939 static void 1940 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1941 { 1942 struct if_rxd_update iru; 1943 struct rxq_refill_cb_arg cb_arg; 1944 struct mbuf *m; 1945 caddr_t cl, *sd_cl; 1946 struct mbuf **sd_m; 1947 bus_dmamap_t *sd_map; 1948 bus_addr_t bus_addr, *sd_ba; 1949 int err, frag_idx, i, idx, n, pidx; 1950 qidx_t credits; 1951 1952 sd_m = fl->ifl_sds.ifsd_m; 1953 sd_map = fl->ifl_sds.ifsd_map; 1954 sd_cl = fl->ifl_sds.ifsd_cl; 1955 sd_ba = fl->ifl_sds.ifsd_ba; 1956 pidx = fl->ifl_pidx; 1957 idx = pidx; 1958 frag_idx = fl->ifl_fragidx; 1959 credits = fl->ifl_credits; 1960 1961 i = 0; 1962 n = count; 1963 MPASS(n > 0); 1964 MPASS(credits + n <= fl->ifl_size); 1965 1966 if (pidx < fl->ifl_cidx) 1967 MPASS(pidx + n <= fl->ifl_cidx); 1968 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1969 MPASS(fl->ifl_gen == 0); 1970 if (pidx > fl->ifl_cidx) 1971 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1972 1973 DBG_COUNTER_INC(fl_refills); 1974 if (n > 8) 1975 DBG_COUNTER_INC(fl_refills_large); 1976 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1977 while (n--) { 1978 /* 1979 * We allocate an uninitialized mbuf + cluster, mbuf is 1980 * initialized after rx. 1981 * 1982 * If the cluster is still set then we know a minimum sized packet was received 1983 */ 1984 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 1985 &frag_idx); 1986 if (frag_idx < 0) 1987 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1988 MPASS(frag_idx >= 0); 1989 if ((cl = sd_cl[frag_idx]) == NULL) { 1990 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1991 break; 1992 1993 cb_arg.error = 0; 1994 MPASS(sd_map != NULL); 1995 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 1996 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 1997 BUS_DMA_NOWAIT); 1998 if (err != 0 || cb_arg.error) { 1999 /* 2000 * !zone_pack ? 2001 */ 2002 if (fl->ifl_zone == zone_pack) 2003 uma_zfree(fl->ifl_zone, cl); 2004 break; 2005 } 2006 2007 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2008 sd_cl[frag_idx] = cl; 2009 #if MEMORY_LOGGING 2010 fl->ifl_cl_enqueued++; 2011 #endif 2012 } else { 2013 bus_addr = sd_ba[frag_idx]; 2014 } 2015 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2016 BUS_DMASYNC_PREREAD); 2017 2018 if (sd_m[frag_idx] == NULL) { 2019 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 2020 break; 2021 } 2022 sd_m[frag_idx] = m; 2023 } 2024 bit_set(fl->ifl_rx_bitmap, frag_idx); 2025 #if MEMORY_LOGGING 2026 fl->ifl_m_enqueued++; 2027 #endif 2028 2029 DBG_COUNTER_INC(rx_allocs); 2030 fl->ifl_rxd_idxs[i] = frag_idx; 2031 fl->ifl_bus_addrs[i] = bus_addr; 2032 fl->ifl_vm_addrs[i] = cl; 2033 credits++; 2034 i++; 2035 MPASS(credits <= fl->ifl_size); 2036 if (++idx == fl->ifl_size) { 2037 fl->ifl_gen = 1; 2038 idx = 0; 2039 } 2040 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2041 iru.iru_pidx = pidx; 2042 iru.iru_count = i; 2043 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2044 i = 0; 2045 pidx = idx; 2046 fl->ifl_pidx = idx; 2047 fl->ifl_credits = credits; 2048 } 2049 } 2050 2051 if (i) { 2052 iru.iru_pidx = pidx; 2053 iru.iru_count = i; 2054 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2055 fl->ifl_pidx = idx; 2056 fl->ifl_credits = credits; 2057 } 2058 DBG_COUNTER_INC(rxd_flush); 2059 if (fl->ifl_pidx == 0) 2060 pidx = fl->ifl_size - 1; 2061 else 2062 pidx = fl->ifl_pidx - 1; 2063 2064 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2065 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2066 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2067 fl->ifl_fragidx = frag_idx; 2068 } 2069 2070 static __inline void 2071 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2072 { 2073 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2074 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2075 #ifdef INVARIANTS 2076 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2077 #endif 2078 2079 MPASS(fl->ifl_credits <= fl->ifl_size); 2080 MPASS(reclaimable == delta); 2081 2082 if (reclaimable > 0) 2083 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2084 } 2085 2086 uint8_t 2087 iflib_in_detach(if_ctx_t ctx) 2088 { 2089 bool in_detach; 2090 STATE_LOCK(ctx); 2091 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2092 STATE_UNLOCK(ctx); 2093 return (in_detach); 2094 } 2095 2096 static void 2097 iflib_fl_bufs_free(iflib_fl_t fl) 2098 { 2099 iflib_dma_info_t idi = fl->ifl_ifdi; 2100 bus_dmamap_t sd_map; 2101 uint32_t i; 2102 2103 for (i = 0; i < fl->ifl_size; i++) { 2104 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2105 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2106 2107 if (*sd_cl != NULL) { 2108 sd_map = fl->ifl_sds.ifsd_map[i]; 2109 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2110 BUS_DMASYNC_POSTREAD); 2111 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2112 if (*sd_cl != NULL) 2113 uma_zfree(fl->ifl_zone, *sd_cl); 2114 // XXX: Should this get moved out? 2115 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx)) 2116 bus_dmamap_destroy(fl->ifl_buf_tag, sd_map); 2117 if (*sd_m != NULL) { 2118 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2119 uma_zfree(zone_mbuf, *sd_m); 2120 } 2121 } else { 2122 MPASS(*sd_cl == NULL); 2123 MPASS(*sd_m == NULL); 2124 } 2125 #if MEMORY_LOGGING 2126 fl->ifl_m_dequeued++; 2127 fl->ifl_cl_dequeued++; 2128 #endif 2129 *sd_cl = NULL; 2130 *sd_m = NULL; 2131 } 2132 #ifdef INVARIANTS 2133 for (i = 0; i < fl->ifl_size; i++) { 2134 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2135 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2136 } 2137 #endif 2138 /* 2139 * Reset free list values 2140 */ 2141 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2142 bzero(idi->idi_vaddr, idi->idi_size); 2143 } 2144 2145 /********************************************************************* 2146 * 2147 * Initialize a receive ring and its buffers. 2148 * 2149 **********************************************************************/ 2150 static int 2151 iflib_fl_setup(iflib_fl_t fl) 2152 { 2153 iflib_rxq_t rxq = fl->ifl_rxq; 2154 if_ctx_t ctx = rxq->ifr_ctx; 2155 2156 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2157 /* 2158 ** Free current RX buffer structs and their mbufs 2159 */ 2160 iflib_fl_bufs_free(fl); 2161 /* Now replenish the mbufs */ 2162 MPASS(fl->ifl_credits == 0); 2163 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2164 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2165 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2166 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2167 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2168 2169 2170 /* avoid pre-allocating zillions of clusters to an idle card 2171 * potentially speeding up attach 2172 */ 2173 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2174 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2175 if (min(128, fl->ifl_size) != fl->ifl_credits) 2176 return (ENOBUFS); 2177 /* 2178 * handle failure 2179 */ 2180 MPASS(rxq != NULL); 2181 MPASS(fl->ifl_ifdi != NULL); 2182 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2183 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2184 return (0); 2185 } 2186 2187 /********************************************************************* 2188 * 2189 * Free receive ring data structures 2190 * 2191 **********************************************************************/ 2192 static void 2193 iflib_rx_sds_free(iflib_rxq_t rxq) 2194 { 2195 iflib_fl_t fl; 2196 int i, j; 2197 2198 if (rxq->ifr_fl != NULL) { 2199 for (i = 0; i < rxq->ifr_nfl; i++) { 2200 fl = &rxq->ifr_fl[i]; 2201 if (fl->ifl_buf_tag != NULL) { 2202 if (fl->ifl_sds.ifsd_map != NULL) { 2203 for (j = 0; j < fl->ifl_size; j++) { 2204 if (fl->ifl_sds.ifsd_map[j] == 2205 NULL) 2206 continue; 2207 bus_dmamap_sync( 2208 fl->ifl_buf_tag, 2209 fl->ifl_sds.ifsd_map[j], 2210 BUS_DMASYNC_POSTREAD); 2211 bus_dmamap_unload( 2212 fl->ifl_buf_tag, 2213 fl->ifl_sds.ifsd_map[j]); 2214 } 2215 } 2216 bus_dma_tag_destroy(fl->ifl_buf_tag); 2217 fl->ifl_buf_tag = NULL; 2218 } 2219 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2220 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2221 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2222 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2223 fl->ifl_sds.ifsd_m = NULL; 2224 fl->ifl_sds.ifsd_cl = NULL; 2225 fl->ifl_sds.ifsd_ba = NULL; 2226 fl->ifl_sds.ifsd_map = NULL; 2227 } 2228 free(rxq->ifr_fl, M_IFLIB); 2229 rxq->ifr_fl = NULL; 2230 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2231 } 2232 } 2233 2234 /* 2235 * MI independent logic 2236 * 2237 */ 2238 static void 2239 iflib_timer(void *arg) 2240 { 2241 iflib_txq_t txq = arg; 2242 if_ctx_t ctx = txq->ift_ctx; 2243 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2244 uint64_t this_tick = ticks; 2245 uint32_t reset_on = hz / 2; 2246 2247 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2248 return; 2249 /* 2250 ** Check on the state of the TX queue(s), this 2251 ** can be done without the lock because its RO 2252 ** and the HUNG state will be static if set. 2253 */ 2254 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2255 txq->ift_last_timer_tick = this_tick; 2256 IFDI_TIMER(ctx, txq->ift_id); 2257 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2258 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2259 (sctx->isc_pause_frames == 0))) 2260 goto hung; 2261 2262 if (ifmp_ring_is_stalled(txq->ift_br)) 2263 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2264 txq->ift_cleaned_prev = txq->ift_cleaned; 2265 } 2266 #ifdef DEV_NETMAP 2267 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2268 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 2269 #endif 2270 /* handle any laggards */ 2271 if (txq->ift_db_pending) 2272 GROUPTASK_ENQUEUE(&txq->ift_task); 2273 2274 sctx->isc_pause_frames = 0; 2275 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2276 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2277 return; 2278 hung: 2279 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2280 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2281 STATE_LOCK(ctx); 2282 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2283 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2284 iflib_admin_intr_deferred(ctx); 2285 STATE_UNLOCK(ctx); 2286 } 2287 2288 static void 2289 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2290 { 2291 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2292 2293 /* 2294 * XXX don't set the max_frame_size to larger 2295 * than the hardware can handle 2296 */ 2297 if (sctx->isc_max_frame_size <= MCLBYTES) 2298 ctx->ifc_rx_mbuf_sz = MCLBYTES; 2299 else 2300 ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE; 2301 } 2302 2303 uint32_t 2304 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2305 { 2306 return (ctx->ifc_rx_mbuf_sz); 2307 } 2308 2309 static void 2310 iflib_init_locked(if_ctx_t ctx) 2311 { 2312 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2313 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2314 if_t ifp = ctx->ifc_ifp; 2315 iflib_fl_t fl; 2316 iflib_txq_t txq; 2317 iflib_rxq_t rxq; 2318 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2319 2320 2321 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2322 IFDI_INTR_DISABLE(ctx); 2323 2324 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2325 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2326 /* Set hardware offload abilities */ 2327 if_clearhwassist(ifp); 2328 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2329 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2330 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2331 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2332 if (if_getcapenable(ifp) & IFCAP_TSO4) 2333 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2334 if (if_getcapenable(ifp) & IFCAP_TSO6) 2335 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2336 2337 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2338 CALLOUT_LOCK(txq); 2339 callout_stop(&txq->ift_timer); 2340 CALLOUT_UNLOCK(txq); 2341 iflib_netmap_txq_init(ctx, txq); 2342 } 2343 2344 /* 2345 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2346 * that drivers can use the value when setting up the hardware receive 2347 * buffers. 2348 */ 2349 iflib_calc_rx_mbuf_sz(ctx); 2350 2351 #ifdef INVARIANTS 2352 i = if_getdrvflags(ifp); 2353 #endif 2354 IFDI_INIT(ctx); 2355 MPASS(if_getdrvflags(ifp) == i); 2356 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2357 /* XXX this should really be done on a per-queue basis */ 2358 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2359 MPASS(rxq->ifr_id == i); 2360 iflib_netmap_rxq_init(ctx, rxq); 2361 continue; 2362 } 2363 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2364 if (iflib_fl_setup(fl)) { 2365 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2366 goto done; 2367 } 2368 } 2369 } 2370 done: 2371 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2372 IFDI_INTR_ENABLE(ctx); 2373 txq = ctx->ifc_txqs; 2374 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2375 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2376 txq->ift_timer.c_cpu); 2377 } 2378 2379 static int 2380 iflib_media_change(if_t ifp) 2381 { 2382 if_ctx_t ctx = if_getsoftc(ifp); 2383 int err; 2384 2385 CTX_LOCK(ctx); 2386 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2387 iflib_init_locked(ctx); 2388 CTX_UNLOCK(ctx); 2389 return (err); 2390 } 2391 2392 static void 2393 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2394 { 2395 if_ctx_t ctx = if_getsoftc(ifp); 2396 2397 CTX_LOCK(ctx); 2398 IFDI_UPDATE_ADMIN_STATUS(ctx); 2399 IFDI_MEDIA_STATUS(ctx, ifmr); 2400 CTX_UNLOCK(ctx); 2401 } 2402 2403 void 2404 iflib_stop(if_ctx_t ctx) 2405 { 2406 iflib_txq_t txq = ctx->ifc_txqs; 2407 iflib_rxq_t rxq = ctx->ifc_rxqs; 2408 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2409 if_shared_ctx_t sctx = ctx->ifc_sctx; 2410 iflib_dma_info_t di; 2411 iflib_fl_t fl; 2412 int i, j; 2413 2414 /* Tell the stack that the interface is no longer active */ 2415 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2416 2417 IFDI_INTR_DISABLE(ctx); 2418 DELAY(1000); 2419 IFDI_STOP(ctx); 2420 DELAY(1000); 2421 2422 iflib_debug_reset(); 2423 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2424 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2425 /* make sure all transmitters have completed before proceeding XXX */ 2426 2427 CALLOUT_LOCK(txq); 2428 callout_stop(&txq->ift_timer); 2429 CALLOUT_UNLOCK(txq); 2430 2431 /* clean any enqueued buffers */ 2432 iflib_ifmp_purge(txq); 2433 /* Free any existing tx buffers. */ 2434 for (j = 0; j < txq->ift_size; j++) { 2435 iflib_txsd_free(ctx, txq, j); 2436 } 2437 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2438 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2439 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2440 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2441 txq->ift_pullups = 0; 2442 ifmp_ring_reset_stats(txq->ift_br); 2443 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2444 bzero((void *)di->idi_vaddr, di->idi_size); 2445 } 2446 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2447 /* make sure all transmitters have completed before proceeding XXX */ 2448 2449 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2450 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2451 bzero((void *)di->idi_vaddr, di->idi_size); 2452 /* also resets the free lists pidx/cidx */ 2453 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2454 iflib_fl_bufs_free(fl); 2455 } 2456 } 2457 2458 static inline caddr_t 2459 calc_next_rxd(iflib_fl_t fl, int cidx) 2460 { 2461 qidx_t size; 2462 int nrxd; 2463 caddr_t start, end, cur, next; 2464 2465 nrxd = fl->ifl_size; 2466 size = fl->ifl_rxd_size; 2467 start = fl->ifl_ifdi->idi_vaddr; 2468 2469 if (__predict_false(size == 0)) 2470 return (start); 2471 cur = start + size*cidx; 2472 end = start + size*nrxd; 2473 next = CACHE_PTR_NEXT(cur); 2474 return (next < end ? next : start); 2475 } 2476 2477 static inline void 2478 prefetch_pkts(iflib_fl_t fl, int cidx) 2479 { 2480 int nextptr; 2481 int nrxd = fl->ifl_size; 2482 caddr_t next_rxd; 2483 2484 2485 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2486 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2487 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2488 next_rxd = calc_next_rxd(fl, cidx); 2489 prefetch(next_rxd); 2490 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2491 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2492 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2493 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2494 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2495 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2496 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2497 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2498 } 2499 2500 static struct mbuf * 2501 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2502 int *pf_rv, if_rxd_info_t ri) 2503 { 2504 bus_dmamap_t map; 2505 iflib_fl_t fl; 2506 caddr_t payload; 2507 struct mbuf *m; 2508 int flid, cidx, len, next; 2509 2510 map = NULL; 2511 flid = irf->irf_flid; 2512 cidx = irf->irf_idx; 2513 fl = &rxq->ifr_fl[flid]; 2514 sd->ifsd_fl = fl; 2515 sd->ifsd_cidx = cidx; 2516 m = fl->ifl_sds.ifsd_m[cidx]; 2517 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2518 fl->ifl_credits--; 2519 #if MEMORY_LOGGING 2520 fl->ifl_m_dequeued++; 2521 #endif 2522 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2523 prefetch_pkts(fl, cidx); 2524 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2525 prefetch(&fl->ifl_sds.ifsd_map[next]); 2526 map = fl->ifl_sds.ifsd_map[cidx]; 2527 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2528 2529 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2530 MPASS(fl->ifl_cidx == cidx); 2531 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2532 2533 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL) { 2534 payload = *sd->ifsd_cl; 2535 payload += ri->iri_pad; 2536 len = ri->iri_len - ri->iri_pad; 2537 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2538 len | PFIL_MEMPTR | PFIL_IN, NULL); 2539 switch (*pf_rv) { 2540 case PFIL_DROPPED: 2541 case PFIL_CONSUMED: 2542 /* 2543 * The filter ate it. Everything is recycled. 2544 */ 2545 m = NULL; 2546 unload = 0; 2547 break; 2548 case PFIL_REALLOCED: 2549 /* 2550 * The filter copied it. Everything is recycled. 2551 */ 2552 m = pfil_mem2mbuf(payload); 2553 unload = 0; 2554 break; 2555 case PFIL_PASS: 2556 /* 2557 * Filter said it was OK, so receive like 2558 * normal 2559 */ 2560 fl->ifl_sds.ifsd_m[cidx] = NULL; 2561 break; 2562 default: 2563 MPASS(0); 2564 } 2565 } else { 2566 fl->ifl_sds.ifsd_m[cidx] = NULL; 2567 *pf_rv = PFIL_PASS; 2568 } 2569 2570 if (unload) 2571 bus_dmamap_unload(fl->ifl_buf_tag, map); 2572 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2573 if (__predict_false(fl->ifl_cidx == 0)) 2574 fl->ifl_gen = 0; 2575 bit_clear(fl->ifl_rx_bitmap, cidx); 2576 return (m); 2577 } 2578 2579 static struct mbuf * 2580 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2581 { 2582 struct mbuf *m, *mh, *mt; 2583 caddr_t cl; 2584 int *pf_rv_ptr, flags, i, padlen; 2585 bool consumed; 2586 2587 i = 0; 2588 mh = NULL; 2589 consumed = false; 2590 *pf_rv = PFIL_PASS; 2591 pf_rv_ptr = pf_rv; 2592 do { 2593 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2594 pf_rv_ptr, ri); 2595 2596 MPASS(*sd->ifsd_cl != NULL); 2597 2598 /* 2599 * Exclude zero-length frags & frags from 2600 * packets the filter has consumed or dropped 2601 */ 2602 if (ri->iri_frags[i].irf_len == 0 || consumed || 2603 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2604 if (mh == NULL) { 2605 /* everything saved here */ 2606 consumed = true; 2607 pf_rv_ptr = NULL; 2608 continue; 2609 } 2610 /* XXX we can save the cluster here, but not the mbuf */ 2611 m_init(m, M_NOWAIT, MT_DATA, 0); 2612 m_free(m); 2613 continue; 2614 } 2615 if (mh == NULL) { 2616 flags = M_PKTHDR|M_EXT; 2617 mh = mt = m; 2618 padlen = ri->iri_pad; 2619 } else { 2620 flags = M_EXT; 2621 mt->m_next = m; 2622 mt = m; 2623 /* assuming padding is only on the first fragment */ 2624 padlen = 0; 2625 } 2626 cl = *sd->ifsd_cl; 2627 *sd->ifsd_cl = NULL; 2628 2629 /* Can these two be made one ? */ 2630 m_init(m, M_NOWAIT, MT_DATA, flags); 2631 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2632 /* 2633 * These must follow m_init and m_cljset 2634 */ 2635 m->m_data += padlen; 2636 ri->iri_len -= padlen; 2637 m->m_len = ri->iri_frags[i].irf_len; 2638 } while (++i < ri->iri_nfrags); 2639 2640 return (mh); 2641 } 2642 2643 /* 2644 * Process one software descriptor 2645 */ 2646 static struct mbuf * 2647 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2648 { 2649 struct if_rxsd sd; 2650 struct mbuf *m; 2651 int pf_rv; 2652 2653 /* should I merge this back in now that the two paths are basically duplicated? */ 2654 if (ri->iri_nfrags == 1 && 2655 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2656 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2657 &pf_rv, ri); 2658 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2659 return (m); 2660 if (pf_rv == PFIL_PASS) { 2661 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2662 #ifndef __NO_STRICT_ALIGNMENT 2663 if (!IP_ALIGNED(m)) 2664 m->m_data += 2; 2665 #endif 2666 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2667 m->m_len = ri->iri_frags[0].irf_len; 2668 } 2669 } else { 2670 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2671 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2672 return (m); 2673 } 2674 m->m_pkthdr.len = ri->iri_len; 2675 m->m_pkthdr.rcvif = ri->iri_ifp; 2676 m->m_flags |= ri->iri_flags; 2677 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2678 m->m_pkthdr.flowid = ri->iri_flowid; 2679 M_HASHTYPE_SET(m, ri->iri_rsstype); 2680 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2681 m->m_pkthdr.csum_data = ri->iri_csum_data; 2682 return (m); 2683 } 2684 2685 #if defined(INET6) || defined(INET) 2686 static void 2687 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2688 { 2689 CURVNET_SET(lc->ifp->if_vnet); 2690 #if defined(INET6) 2691 *v6 = VNET(ip6_forwarding); 2692 #endif 2693 #if defined(INET) 2694 *v4 = VNET(ipforwarding); 2695 #endif 2696 CURVNET_RESTORE(); 2697 } 2698 2699 /* 2700 * Returns true if it's possible this packet could be LROed. 2701 * if it returns false, it is guaranteed that tcp_lro_rx() 2702 * would not return zero. 2703 */ 2704 static bool 2705 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2706 { 2707 struct ether_header *eh; 2708 uint16_t eh_type; 2709 2710 eh = mtod(m, struct ether_header *); 2711 eh_type = ntohs(eh->ether_type); 2712 switch (eh_type) { 2713 #if defined(INET6) 2714 case ETHERTYPE_IPV6: 2715 return !v6_forwarding; 2716 #endif 2717 #if defined (INET) 2718 case ETHERTYPE_IP: 2719 return !v4_forwarding; 2720 #endif 2721 } 2722 2723 return false; 2724 } 2725 #else 2726 static void 2727 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2728 { 2729 } 2730 #endif 2731 2732 static bool 2733 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2734 { 2735 if_ctx_t ctx = rxq->ifr_ctx; 2736 if_shared_ctx_t sctx = ctx->ifc_sctx; 2737 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2738 int avail, i; 2739 qidx_t *cidxp; 2740 struct if_rxd_info ri; 2741 int err, budget_left, rx_bytes, rx_pkts; 2742 iflib_fl_t fl; 2743 struct ifnet *ifp; 2744 int lro_enabled; 2745 bool v4_forwarding, v6_forwarding, lro_possible; 2746 2747 /* 2748 * XXX early demux data packets so that if_input processing only handles 2749 * acks in interrupt context 2750 */ 2751 struct mbuf *m, *mh, *mt, *mf; 2752 2753 lro_possible = v4_forwarding = v6_forwarding = false; 2754 ifp = ctx->ifc_ifp; 2755 mh = mt = NULL; 2756 MPASS(budget > 0); 2757 rx_pkts = rx_bytes = 0; 2758 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2759 cidxp = &rxq->ifr_cq_cidx; 2760 else 2761 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2762 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2763 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2764 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2765 DBG_COUNTER_INC(rx_unavail); 2766 return (false); 2767 } 2768 2769 /* pfil needs the vnet to be set */ 2770 CURVNET_SET_QUIET(ifp->if_vnet); 2771 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2772 if (__predict_false(!CTX_ACTIVE(ctx))) { 2773 DBG_COUNTER_INC(rx_ctx_inactive); 2774 break; 2775 } 2776 /* 2777 * Reset client set fields to their default values 2778 */ 2779 rxd_info_zero(&ri); 2780 ri.iri_qsidx = rxq->ifr_id; 2781 ri.iri_cidx = *cidxp; 2782 ri.iri_ifp = ifp; 2783 ri.iri_frags = rxq->ifr_frags; 2784 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2785 2786 if (err) 2787 goto err; 2788 rx_pkts += 1; 2789 rx_bytes += ri.iri_len; 2790 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2791 *cidxp = ri.iri_cidx; 2792 /* Update our consumer index */ 2793 /* XXX NB: shurd - check if this is still safe */ 2794 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2795 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2796 rxq->ifr_cq_gen = 0; 2797 } 2798 /* was this only a completion queue message? */ 2799 if (__predict_false(ri.iri_nfrags == 0)) 2800 continue; 2801 } 2802 MPASS(ri.iri_nfrags != 0); 2803 MPASS(ri.iri_len != 0); 2804 2805 /* will advance the cidx on the corresponding free lists */ 2806 m = iflib_rxd_pkt_get(rxq, &ri); 2807 avail--; 2808 budget_left--; 2809 if (avail == 0 && budget_left) 2810 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2811 2812 if (__predict_false(m == NULL)) 2813 continue; 2814 2815 /* imm_pkt: -- cxgb */ 2816 if (mh == NULL) 2817 mh = mt = m; 2818 else { 2819 mt->m_nextpkt = m; 2820 mt = m; 2821 } 2822 } 2823 CURVNET_RESTORE(); 2824 /* make sure that we can refill faster than drain */ 2825 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2826 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2827 2828 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2829 if (lro_enabled) 2830 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2831 mt = mf = NULL; 2832 while (mh != NULL) { 2833 m = mh; 2834 mh = mh->m_nextpkt; 2835 m->m_nextpkt = NULL; 2836 #ifndef __NO_STRICT_ALIGNMENT 2837 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2838 continue; 2839 #endif 2840 rx_bytes += m->m_pkthdr.len; 2841 rx_pkts++; 2842 #if defined(INET6) || defined(INET) 2843 if (lro_enabled) { 2844 if (!lro_possible) { 2845 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2846 if (lro_possible && mf != NULL) { 2847 ifp->if_input(ifp, mf); 2848 DBG_COUNTER_INC(rx_if_input); 2849 mt = mf = NULL; 2850 } 2851 } 2852 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2853 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2854 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2855 continue; 2856 } 2857 } 2858 #endif 2859 if (lro_possible) { 2860 ifp->if_input(ifp, m); 2861 DBG_COUNTER_INC(rx_if_input); 2862 continue; 2863 } 2864 2865 if (mf == NULL) 2866 mf = m; 2867 if (mt != NULL) 2868 mt->m_nextpkt = m; 2869 mt = m; 2870 } 2871 if (mf != NULL) { 2872 ifp->if_input(ifp, mf); 2873 DBG_COUNTER_INC(rx_if_input); 2874 } 2875 2876 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2877 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2878 2879 /* 2880 * Flush any outstanding LRO work 2881 */ 2882 #if defined(INET6) || defined(INET) 2883 tcp_lro_flush_all(&rxq->ifr_lc); 2884 #endif 2885 if (avail) 2886 return true; 2887 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2888 err: 2889 STATE_LOCK(ctx); 2890 ctx->ifc_flags |= IFC_DO_RESET; 2891 iflib_admin_intr_deferred(ctx); 2892 STATE_UNLOCK(ctx); 2893 return (false); 2894 } 2895 2896 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2897 static inline qidx_t 2898 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2899 { 2900 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2901 qidx_t minthresh = txq->ift_size / 8; 2902 if (in_use > 4*minthresh) 2903 return (notify_count); 2904 if (in_use > 2*minthresh) 2905 return (notify_count >> 1); 2906 if (in_use > minthresh) 2907 return (notify_count >> 3); 2908 return (0); 2909 } 2910 2911 static inline qidx_t 2912 txq_max_rs_deferred(iflib_txq_t txq) 2913 { 2914 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2915 qidx_t minthresh = txq->ift_size / 8; 2916 if (txq->ift_in_use > 4*minthresh) 2917 return (notify_count); 2918 if (txq->ift_in_use > 2*minthresh) 2919 return (notify_count >> 1); 2920 if (txq->ift_in_use > minthresh) 2921 return (notify_count >> 2); 2922 return (2); 2923 } 2924 2925 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2926 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2927 2928 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2929 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2930 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2931 2932 /* forward compatibility for cxgb */ 2933 #define FIRST_QSET(ctx) 0 2934 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2935 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2936 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2937 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2938 2939 /* XXX we should be setting this to something other than zero */ 2940 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2941 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2942 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2943 2944 static inline bool 2945 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2946 { 2947 qidx_t dbval, max; 2948 bool rang; 2949 2950 rang = false; 2951 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2952 if (ring || txq->ift_db_pending >= max) { 2953 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2954 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 2955 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2956 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2957 txq->ift_db_pending = txq->ift_npending = 0; 2958 rang = true; 2959 } 2960 return (rang); 2961 } 2962 2963 #ifdef PKT_DEBUG 2964 static void 2965 print_pkt(if_pkt_info_t pi) 2966 { 2967 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2968 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2969 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2970 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2971 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2972 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2973 } 2974 #endif 2975 2976 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2977 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2978 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2979 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2980 2981 static int 2982 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2983 { 2984 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2985 struct ether_vlan_header *eh; 2986 struct mbuf *m; 2987 2988 m = *mp; 2989 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2990 M_WRITABLE(m) == 0) { 2991 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2992 return (ENOMEM); 2993 } else { 2994 m_freem(*mp); 2995 DBG_COUNTER_INC(tx_frees); 2996 *mp = m; 2997 } 2998 } 2999 3000 /* 3001 * Determine where frame payload starts. 3002 * Jump over vlan headers if already present, 3003 * helpful for QinQ too. 3004 */ 3005 if (__predict_false(m->m_len < sizeof(*eh))) { 3006 txq->ift_pullups++; 3007 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3008 return (ENOMEM); 3009 } 3010 eh = mtod(m, struct ether_vlan_header *); 3011 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3012 pi->ipi_etype = ntohs(eh->evl_proto); 3013 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3014 } else { 3015 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3016 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3017 } 3018 3019 switch (pi->ipi_etype) { 3020 #ifdef INET 3021 case ETHERTYPE_IP: 3022 { 3023 struct mbuf *n; 3024 struct ip *ip = NULL; 3025 struct tcphdr *th = NULL; 3026 int minthlen; 3027 3028 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3029 if (__predict_false(m->m_len < minthlen)) { 3030 /* 3031 * if this code bloat is causing too much of a hit 3032 * move it to a separate function and mark it noinline 3033 */ 3034 if (m->m_len == pi->ipi_ehdrlen) { 3035 n = m->m_next; 3036 MPASS(n); 3037 if (n->m_len >= sizeof(*ip)) { 3038 ip = (struct ip *)n->m_data; 3039 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3040 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3041 } else { 3042 txq->ift_pullups++; 3043 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3044 return (ENOMEM); 3045 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3046 } 3047 } else { 3048 txq->ift_pullups++; 3049 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3050 return (ENOMEM); 3051 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3052 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3053 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3054 } 3055 } else { 3056 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3057 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3058 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3059 } 3060 pi->ipi_ip_hlen = ip->ip_hl << 2; 3061 pi->ipi_ipproto = ip->ip_p; 3062 pi->ipi_flags |= IPI_TX_IPV4; 3063 3064 /* TCP checksum offload may require TCP header length */ 3065 if (IS_TX_OFFLOAD4(pi)) { 3066 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3067 if (__predict_false(th == NULL)) { 3068 txq->ift_pullups++; 3069 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3070 return (ENOMEM); 3071 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3072 } 3073 pi->ipi_tcp_hflags = th->th_flags; 3074 pi->ipi_tcp_hlen = th->th_off << 2; 3075 pi->ipi_tcp_seq = th->th_seq; 3076 } 3077 if (IS_TSO4(pi)) { 3078 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3079 return (ENXIO); 3080 /* 3081 * TSO always requires hardware checksum offload. 3082 */ 3083 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3084 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3085 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3086 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3087 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3088 ip->ip_sum = 0; 3089 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3090 } 3091 } 3092 } 3093 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3094 ip->ip_sum = 0; 3095 3096 break; 3097 } 3098 #endif 3099 #ifdef INET6 3100 case ETHERTYPE_IPV6: 3101 { 3102 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3103 struct tcphdr *th; 3104 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3105 3106 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3107 txq->ift_pullups++; 3108 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3109 return (ENOMEM); 3110 } 3111 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3112 3113 /* XXX-BZ this will go badly in case of ext hdrs. */ 3114 pi->ipi_ipproto = ip6->ip6_nxt; 3115 pi->ipi_flags |= IPI_TX_IPV6; 3116 3117 /* TCP checksum offload may require TCP header length */ 3118 if (IS_TX_OFFLOAD6(pi)) { 3119 if (pi->ipi_ipproto == IPPROTO_TCP) { 3120 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3121 txq->ift_pullups++; 3122 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3123 return (ENOMEM); 3124 } 3125 pi->ipi_tcp_hflags = th->th_flags; 3126 pi->ipi_tcp_hlen = th->th_off << 2; 3127 pi->ipi_tcp_seq = th->th_seq; 3128 } 3129 if (IS_TSO6(pi)) { 3130 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3131 return (ENXIO); 3132 /* 3133 * TSO always requires hardware checksum offload. 3134 */ 3135 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3136 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3137 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3138 } 3139 } 3140 break; 3141 } 3142 #endif 3143 default: 3144 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3145 pi->ipi_ip_hlen = 0; 3146 break; 3147 } 3148 *mp = m; 3149 3150 return (0); 3151 } 3152 3153 /* 3154 * If dodgy hardware rejects the scatter gather chain we've handed it 3155 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3156 * m_defrag'd mbufs 3157 */ 3158 static __noinline struct mbuf * 3159 iflib_remove_mbuf(iflib_txq_t txq) 3160 { 3161 int ntxd, pidx; 3162 struct mbuf *m, **ifsd_m; 3163 3164 ifsd_m = txq->ift_sds.ifsd_m; 3165 ntxd = txq->ift_size; 3166 pidx = txq->ift_pidx & (ntxd - 1); 3167 ifsd_m = txq->ift_sds.ifsd_m; 3168 m = ifsd_m[pidx]; 3169 ifsd_m[pidx] = NULL; 3170 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3171 if (txq->ift_sds.ifsd_tso_map != NULL) 3172 bus_dmamap_unload(txq->ift_tso_buf_tag, 3173 txq->ift_sds.ifsd_tso_map[pidx]); 3174 #if MEMORY_LOGGING 3175 txq->ift_dequeued++; 3176 #endif 3177 return (m); 3178 } 3179 3180 static inline caddr_t 3181 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3182 { 3183 qidx_t size; 3184 int ntxd; 3185 caddr_t start, end, cur, next; 3186 3187 ntxd = txq->ift_size; 3188 size = txq->ift_txd_size[qid]; 3189 start = txq->ift_ifdi[qid].idi_vaddr; 3190 3191 if (__predict_false(size == 0)) 3192 return (start); 3193 cur = start + size*cidx; 3194 end = start + size*ntxd; 3195 next = CACHE_PTR_NEXT(cur); 3196 return (next < end ? next : start); 3197 } 3198 3199 /* 3200 * Pad an mbuf to ensure a minimum ethernet frame size. 3201 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3202 */ 3203 static __noinline int 3204 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3205 { 3206 /* 3207 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3208 * and ARP message is the smallest common payload I can think of 3209 */ 3210 static char pad[18]; /* just zeros */ 3211 int n; 3212 struct mbuf *new_head; 3213 3214 if (!M_WRITABLE(*m_head)) { 3215 new_head = m_dup(*m_head, M_NOWAIT); 3216 if (new_head == NULL) { 3217 m_freem(*m_head); 3218 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3219 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3220 DBG_COUNTER_INC(tx_frees); 3221 return ENOMEM; 3222 } 3223 m_freem(*m_head); 3224 *m_head = new_head; 3225 } 3226 3227 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3228 n > 0; n -= sizeof(pad)) 3229 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3230 break; 3231 3232 if (n > 0) { 3233 m_freem(*m_head); 3234 device_printf(dev, "cannot pad short frame\n"); 3235 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3236 DBG_COUNTER_INC(tx_frees); 3237 return (ENOBUFS); 3238 } 3239 3240 return 0; 3241 } 3242 3243 static int 3244 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3245 { 3246 if_ctx_t ctx; 3247 if_shared_ctx_t sctx; 3248 if_softc_ctx_t scctx; 3249 bus_dma_tag_t buf_tag; 3250 bus_dma_segment_t *segs; 3251 struct mbuf *m_head, **ifsd_m; 3252 void *next_txd; 3253 bus_dmamap_t map; 3254 struct if_pkt_info pi; 3255 int remap = 0; 3256 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3257 3258 ctx = txq->ift_ctx; 3259 sctx = ctx->ifc_sctx; 3260 scctx = &ctx->ifc_softc_ctx; 3261 segs = txq->ift_segs; 3262 ntxd = txq->ift_size; 3263 m_head = *m_headp; 3264 map = NULL; 3265 3266 /* 3267 * If we're doing TSO the next descriptor to clean may be quite far ahead 3268 */ 3269 cidx = txq->ift_cidx; 3270 pidx = txq->ift_pidx; 3271 if (ctx->ifc_flags & IFC_PREFETCH) { 3272 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3273 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3274 next_txd = calc_next_txd(txq, cidx, 0); 3275 prefetch(next_txd); 3276 } 3277 3278 /* prefetch the next cache line of mbuf pointers and flags */ 3279 prefetch(&txq->ift_sds.ifsd_m[next]); 3280 prefetch(&txq->ift_sds.ifsd_map[next]); 3281 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3282 } 3283 map = txq->ift_sds.ifsd_map[pidx]; 3284 ifsd_m = txq->ift_sds.ifsd_m; 3285 3286 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3287 buf_tag = txq->ift_tso_buf_tag; 3288 max_segs = scctx->isc_tx_tso_segments_max; 3289 map = txq->ift_sds.ifsd_tso_map[pidx]; 3290 MPASS(buf_tag != NULL); 3291 MPASS(max_segs > 0); 3292 } else { 3293 buf_tag = txq->ift_buf_tag; 3294 max_segs = scctx->isc_tx_nsegments; 3295 map = txq->ift_sds.ifsd_map[pidx]; 3296 } 3297 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3298 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3299 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3300 if (err) { 3301 DBG_COUNTER_INC(encap_txd_encap_fail); 3302 return err; 3303 } 3304 } 3305 m_head = *m_headp; 3306 3307 pkt_info_zero(&pi); 3308 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3309 pi.ipi_pidx = pidx; 3310 pi.ipi_qsidx = txq->ift_id; 3311 pi.ipi_len = m_head->m_pkthdr.len; 3312 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3313 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3314 3315 /* deliberate bitwise OR to make one condition */ 3316 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3317 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3318 DBG_COUNTER_INC(encap_txd_encap_fail); 3319 return (err); 3320 } 3321 m_head = *m_headp; 3322 } 3323 3324 retry: 3325 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3326 BUS_DMA_NOWAIT); 3327 defrag: 3328 if (__predict_false(err)) { 3329 switch (err) { 3330 case EFBIG: 3331 /* try collapse once and defrag once */ 3332 if (remap == 0) { 3333 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3334 /* try defrag if collapsing fails */ 3335 if (m_head == NULL) 3336 remap++; 3337 } 3338 if (remap == 1) { 3339 txq->ift_mbuf_defrag++; 3340 m_head = m_defrag(*m_headp, M_NOWAIT); 3341 } 3342 /* 3343 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3344 * failed to map an mbuf that was run through m_defrag 3345 */ 3346 MPASS(remap <= 1); 3347 if (__predict_false(m_head == NULL || remap > 1)) 3348 goto defrag_failed; 3349 remap++; 3350 *m_headp = m_head; 3351 goto retry; 3352 break; 3353 case ENOMEM: 3354 txq->ift_no_tx_dma_setup++; 3355 break; 3356 default: 3357 txq->ift_no_tx_dma_setup++; 3358 m_freem(*m_headp); 3359 DBG_COUNTER_INC(tx_frees); 3360 *m_headp = NULL; 3361 break; 3362 } 3363 txq->ift_map_failed++; 3364 DBG_COUNTER_INC(encap_load_mbuf_fail); 3365 DBG_COUNTER_INC(encap_txd_encap_fail); 3366 return (err); 3367 } 3368 ifsd_m[pidx] = m_head; 3369 /* 3370 * XXX assumes a 1 to 1 relationship between segments and 3371 * descriptors - this does not hold true on all drivers, e.g. 3372 * cxgb 3373 */ 3374 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3375 txq->ift_no_desc_avail++; 3376 bus_dmamap_unload(buf_tag, map); 3377 DBG_COUNTER_INC(encap_txq_avail_fail); 3378 DBG_COUNTER_INC(encap_txd_encap_fail); 3379 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3380 GROUPTASK_ENQUEUE(&txq->ift_task); 3381 return (ENOBUFS); 3382 } 3383 /* 3384 * On Intel cards we can greatly reduce the number of TX interrupts 3385 * we see by only setting report status on every Nth descriptor. 3386 * However, this also means that the driver will need to keep track 3387 * of the descriptors that RS was set on to check them for the DD bit. 3388 */ 3389 txq->ift_rs_pending += nsegs + 1; 3390 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3391 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3392 pi.ipi_flags |= IPI_TX_INTR; 3393 txq->ift_rs_pending = 0; 3394 } 3395 3396 pi.ipi_segs = segs; 3397 pi.ipi_nsegs = nsegs; 3398 3399 MPASS(pidx >= 0 && pidx < txq->ift_size); 3400 #ifdef PKT_DEBUG 3401 print_pkt(&pi); 3402 #endif 3403 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3404 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3405 DBG_COUNTER_INC(tx_encap); 3406 MPASS(pi.ipi_new_pidx < txq->ift_size); 3407 3408 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3409 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3410 ndesc += txq->ift_size; 3411 txq->ift_gen = 1; 3412 } 3413 /* 3414 * drivers can need as many as 3415 * two sentinels 3416 */ 3417 MPASS(ndesc <= pi.ipi_nsegs + 2); 3418 MPASS(pi.ipi_new_pidx != pidx); 3419 MPASS(ndesc > 0); 3420 txq->ift_in_use += ndesc; 3421 3422 /* 3423 * We update the last software descriptor again here because there may 3424 * be a sentinel and/or there may be more mbufs than segments 3425 */ 3426 txq->ift_pidx = pi.ipi_new_pidx; 3427 txq->ift_npending += pi.ipi_ndescs; 3428 } else { 3429 *m_headp = m_head = iflib_remove_mbuf(txq); 3430 if (err == EFBIG) { 3431 txq->ift_txd_encap_efbig++; 3432 if (remap < 2) { 3433 remap = 1; 3434 goto defrag; 3435 } 3436 } 3437 goto defrag_failed; 3438 } 3439 /* 3440 * err can't possibly be non-zero here, so we don't neet to test it 3441 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3442 */ 3443 return (err); 3444 3445 defrag_failed: 3446 txq->ift_mbuf_defrag_failed++; 3447 txq->ift_map_failed++; 3448 m_freem(*m_headp); 3449 DBG_COUNTER_INC(tx_frees); 3450 *m_headp = NULL; 3451 DBG_COUNTER_INC(encap_txd_encap_fail); 3452 return (ENOMEM); 3453 } 3454 3455 static void 3456 iflib_tx_desc_free(iflib_txq_t txq, int n) 3457 { 3458 uint32_t qsize, cidx, mask, gen; 3459 struct mbuf *m, **ifsd_m; 3460 bool do_prefetch; 3461 3462 cidx = txq->ift_cidx; 3463 gen = txq->ift_gen; 3464 qsize = txq->ift_size; 3465 mask = qsize-1; 3466 ifsd_m = txq->ift_sds.ifsd_m; 3467 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3468 3469 while (n-- > 0) { 3470 if (do_prefetch) { 3471 prefetch(ifsd_m[(cidx + 3) & mask]); 3472 prefetch(ifsd_m[(cidx + 4) & mask]); 3473 } 3474 if ((m = ifsd_m[cidx]) != NULL) { 3475 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3476 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3477 bus_dmamap_sync(txq->ift_tso_buf_tag, 3478 txq->ift_sds.ifsd_tso_map[cidx], 3479 BUS_DMASYNC_POSTWRITE); 3480 bus_dmamap_unload(txq->ift_tso_buf_tag, 3481 txq->ift_sds.ifsd_tso_map[cidx]); 3482 } else { 3483 bus_dmamap_sync(txq->ift_buf_tag, 3484 txq->ift_sds.ifsd_map[cidx], 3485 BUS_DMASYNC_POSTWRITE); 3486 bus_dmamap_unload(txq->ift_buf_tag, 3487 txq->ift_sds.ifsd_map[cidx]); 3488 } 3489 /* XXX we don't support any drivers that batch packets yet */ 3490 MPASS(m->m_nextpkt == NULL); 3491 m_freem(m); 3492 ifsd_m[cidx] = NULL; 3493 #if MEMORY_LOGGING 3494 txq->ift_dequeued++; 3495 #endif 3496 DBG_COUNTER_INC(tx_frees); 3497 } 3498 if (__predict_false(++cidx == qsize)) { 3499 cidx = 0; 3500 gen = 0; 3501 } 3502 } 3503 txq->ift_cidx = cidx; 3504 txq->ift_gen = gen; 3505 } 3506 3507 static __inline int 3508 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3509 { 3510 int reclaim; 3511 if_ctx_t ctx = txq->ift_ctx; 3512 3513 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3514 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3515 3516 /* 3517 * Need a rate-limiting check so that this isn't called every time 3518 */ 3519 iflib_tx_credits_update(ctx, txq); 3520 reclaim = DESC_RECLAIMABLE(txq); 3521 3522 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3523 #ifdef INVARIANTS 3524 if (iflib_verbose_debug) { 3525 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3526 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3527 reclaim, thresh); 3528 3529 } 3530 #endif 3531 return (0); 3532 } 3533 iflib_tx_desc_free(txq, reclaim); 3534 txq->ift_cleaned += reclaim; 3535 txq->ift_in_use -= reclaim; 3536 3537 return (reclaim); 3538 } 3539 3540 static struct mbuf ** 3541 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3542 { 3543 int next, size; 3544 struct mbuf **items; 3545 3546 size = r->size; 3547 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3548 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3549 3550 prefetch(items[(cidx + offset) & (size-1)]); 3551 if (remaining > 1) { 3552 prefetch2cachelines(&items[next]); 3553 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3554 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3555 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3556 } 3557 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3558 } 3559 3560 static void 3561 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3562 { 3563 3564 ifmp_ring_check_drainage(txq->ift_br, budget); 3565 } 3566 3567 static uint32_t 3568 iflib_txq_can_drain(struct ifmp_ring *r) 3569 { 3570 iflib_txq_t txq = r->cookie; 3571 if_ctx_t ctx = txq->ift_ctx; 3572 3573 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3574 return (1); 3575 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3576 BUS_DMASYNC_POSTREAD); 3577 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3578 false)); 3579 } 3580 3581 static uint32_t 3582 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3583 { 3584 iflib_txq_t txq = r->cookie; 3585 if_ctx_t ctx = txq->ift_ctx; 3586 struct ifnet *ifp = ctx->ifc_ifp; 3587 struct mbuf **mp, *m; 3588 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3589 int reclaimed, err, in_use_prev, desc_used; 3590 bool do_prefetch, ring, rang; 3591 3592 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3593 !LINK_ACTIVE(ctx))) { 3594 DBG_COUNTER_INC(txq_drain_notready); 3595 return (0); 3596 } 3597 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3598 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3599 avail = IDXDIFF(pidx, cidx, r->size); 3600 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3601 DBG_COUNTER_INC(txq_drain_flushing); 3602 for (i = 0; i < avail; i++) { 3603 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3604 m_free(r->items[(cidx + i) & (r->size-1)]); 3605 r->items[(cidx + i) & (r->size-1)] = NULL; 3606 } 3607 return (avail); 3608 } 3609 3610 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3611 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3612 CALLOUT_LOCK(txq); 3613 callout_stop(&txq->ift_timer); 3614 CALLOUT_UNLOCK(txq); 3615 DBG_COUNTER_INC(txq_drain_oactive); 3616 return (0); 3617 } 3618 if (reclaimed) 3619 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3620 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3621 count = MIN(avail, TX_BATCH_SIZE); 3622 #ifdef INVARIANTS 3623 if (iflib_verbose_debug) 3624 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3625 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3626 #endif 3627 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3628 avail = TXQ_AVAIL(txq); 3629 err = 0; 3630 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3631 int rem = do_prefetch ? count - i : 0; 3632 3633 mp = _ring_peek_one(r, cidx, i, rem); 3634 MPASS(mp != NULL && *mp != NULL); 3635 if (__predict_false(*mp == (struct mbuf *)txq)) { 3636 consumed++; 3637 reclaimed++; 3638 continue; 3639 } 3640 in_use_prev = txq->ift_in_use; 3641 err = iflib_encap(txq, mp); 3642 if (__predict_false(err)) { 3643 /* no room - bail out */ 3644 if (err == ENOBUFS) 3645 break; 3646 consumed++; 3647 /* we can't send this packet - skip it */ 3648 continue; 3649 } 3650 consumed++; 3651 pkt_sent++; 3652 m = *mp; 3653 DBG_COUNTER_INC(tx_sent); 3654 bytes_sent += m->m_pkthdr.len; 3655 mcast_sent += !!(m->m_flags & M_MCAST); 3656 avail = TXQ_AVAIL(txq); 3657 3658 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3659 desc_used += (txq->ift_in_use - in_use_prev); 3660 ETHER_BPF_MTAP(ifp, m); 3661 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3662 break; 3663 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3664 } 3665 3666 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3667 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3668 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3669 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3670 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3671 if (mcast_sent) 3672 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3673 #ifdef INVARIANTS 3674 if (iflib_verbose_debug) 3675 printf("consumed=%d\n", consumed); 3676 #endif 3677 return (consumed); 3678 } 3679 3680 static uint32_t 3681 iflib_txq_drain_always(struct ifmp_ring *r) 3682 { 3683 return (1); 3684 } 3685 3686 static uint32_t 3687 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3688 { 3689 int i, avail; 3690 struct mbuf **mp; 3691 iflib_txq_t txq; 3692 3693 txq = r->cookie; 3694 3695 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3696 CALLOUT_LOCK(txq); 3697 callout_stop(&txq->ift_timer); 3698 CALLOUT_UNLOCK(txq); 3699 3700 avail = IDXDIFF(pidx, cidx, r->size); 3701 for (i = 0; i < avail; i++) { 3702 mp = _ring_peek_one(r, cidx, i, avail - i); 3703 if (__predict_false(*mp == (struct mbuf *)txq)) 3704 continue; 3705 m_freem(*mp); 3706 DBG_COUNTER_INC(tx_frees); 3707 } 3708 MPASS(ifmp_ring_is_stalled(r) == 0); 3709 return (avail); 3710 } 3711 3712 static void 3713 iflib_ifmp_purge(iflib_txq_t txq) 3714 { 3715 struct ifmp_ring *r; 3716 3717 r = txq->ift_br; 3718 r->drain = iflib_txq_drain_free; 3719 r->can_drain = iflib_txq_drain_always; 3720 3721 ifmp_ring_check_drainage(r, r->size); 3722 3723 r->drain = iflib_txq_drain; 3724 r->can_drain = iflib_txq_can_drain; 3725 } 3726 3727 static void 3728 _task_fn_tx(void *context) 3729 { 3730 iflib_txq_t txq = context; 3731 if_ctx_t ctx = txq->ift_ctx; 3732 #if defined(ALTQ) || defined(DEV_NETMAP) 3733 if_t ifp = ctx->ifc_ifp; 3734 #endif 3735 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3736 3737 #ifdef IFLIB_DIAGNOSTICS 3738 txq->ift_cpu_exec_count[curcpu]++; 3739 #endif 3740 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3741 return; 3742 #ifdef DEV_NETMAP 3743 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3744 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3745 BUS_DMASYNC_POSTREAD); 3746 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3747 netmap_tx_irq(ifp, txq->ift_id); 3748 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3749 return; 3750 } 3751 #endif 3752 #ifdef ALTQ 3753 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3754 iflib_altq_if_start(ifp); 3755 #endif 3756 if (txq->ift_db_pending) 3757 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3758 else if (!abdicate) 3759 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3760 /* 3761 * When abdicating, we always need to check drainage, not just when we don't enqueue 3762 */ 3763 if (abdicate) 3764 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3765 if (ctx->ifc_flags & IFC_LEGACY) 3766 IFDI_INTR_ENABLE(ctx); 3767 else { 3768 #ifdef INVARIANTS 3769 int rc = 3770 #endif 3771 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3772 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3773 } 3774 } 3775 3776 static void 3777 _task_fn_rx(void *context) 3778 { 3779 iflib_rxq_t rxq = context; 3780 if_ctx_t ctx = rxq->ifr_ctx; 3781 bool more; 3782 uint16_t budget; 3783 3784 #ifdef IFLIB_DIAGNOSTICS 3785 rxq->ifr_cpu_exec_count[curcpu]++; 3786 #endif 3787 DBG_COUNTER_INC(task_fn_rxs); 3788 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3789 return; 3790 more = true; 3791 #ifdef DEV_NETMAP 3792 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3793 u_int work = 0; 3794 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3795 more = false; 3796 } 3797 } 3798 #endif 3799 budget = ctx->ifc_sysctl_rx_budget; 3800 if (budget == 0) 3801 budget = 16; /* XXX */ 3802 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3803 if (ctx->ifc_flags & IFC_LEGACY) 3804 IFDI_INTR_ENABLE(ctx); 3805 else { 3806 #ifdef INVARIANTS 3807 int rc = 3808 #endif 3809 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3810 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3811 DBG_COUNTER_INC(rx_intr_enables); 3812 } 3813 } 3814 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3815 return; 3816 if (more) 3817 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3818 } 3819 3820 static void 3821 _task_fn_admin(void *context) 3822 { 3823 if_ctx_t ctx = context; 3824 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3825 iflib_txq_t txq; 3826 int i; 3827 bool oactive, running, do_reset, do_watchdog, in_detach; 3828 uint32_t reset_on = hz / 2; 3829 3830 STATE_LOCK(ctx); 3831 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3832 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3833 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3834 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3835 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3836 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3837 STATE_UNLOCK(ctx); 3838 3839 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3840 return; 3841 if (in_detach) 3842 return; 3843 3844 CTX_LOCK(ctx); 3845 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3846 CALLOUT_LOCK(txq); 3847 callout_stop(&txq->ift_timer); 3848 CALLOUT_UNLOCK(txq); 3849 } 3850 if (do_watchdog) { 3851 ctx->ifc_watchdog_events++; 3852 IFDI_WATCHDOG_RESET(ctx); 3853 } 3854 IFDI_UPDATE_ADMIN_STATUS(ctx); 3855 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3856 #ifdef DEV_NETMAP 3857 reset_on = hz / 2; 3858 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3859 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 3860 #endif 3861 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3862 } 3863 IFDI_LINK_INTR_ENABLE(ctx); 3864 if (do_reset) 3865 iflib_if_init_locked(ctx); 3866 CTX_UNLOCK(ctx); 3867 3868 if (LINK_ACTIVE(ctx) == 0) 3869 return; 3870 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3871 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3872 } 3873 3874 3875 static void 3876 _task_fn_iov(void *context) 3877 { 3878 if_ctx_t ctx = context; 3879 3880 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3881 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3882 return; 3883 3884 CTX_LOCK(ctx); 3885 IFDI_VFLR_HANDLE(ctx); 3886 CTX_UNLOCK(ctx); 3887 } 3888 3889 static int 3890 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3891 { 3892 int err; 3893 if_int_delay_info_t info; 3894 if_ctx_t ctx; 3895 3896 info = (if_int_delay_info_t)arg1; 3897 ctx = info->iidi_ctx; 3898 info->iidi_req = req; 3899 info->iidi_oidp = oidp; 3900 CTX_LOCK(ctx); 3901 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3902 CTX_UNLOCK(ctx); 3903 return (err); 3904 } 3905 3906 /********************************************************************* 3907 * 3908 * IFNET FUNCTIONS 3909 * 3910 **********************************************************************/ 3911 3912 static void 3913 iflib_if_init_locked(if_ctx_t ctx) 3914 { 3915 iflib_stop(ctx); 3916 iflib_init_locked(ctx); 3917 } 3918 3919 3920 static void 3921 iflib_if_init(void *arg) 3922 { 3923 if_ctx_t ctx = arg; 3924 3925 CTX_LOCK(ctx); 3926 iflib_if_init_locked(ctx); 3927 CTX_UNLOCK(ctx); 3928 } 3929 3930 static int 3931 iflib_if_transmit(if_t ifp, struct mbuf *m) 3932 { 3933 if_ctx_t ctx = if_getsoftc(ifp); 3934 3935 iflib_txq_t txq; 3936 int err, qidx; 3937 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3938 3939 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3940 DBG_COUNTER_INC(tx_frees); 3941 m_freem(m); 3942 return (ENETDOWN); 3943 } 3944 3945 MPASS(m->m_nextpkt == NULL); 3946 /* ALTQ-enabled interfaces always use queue 0. */ 3947 qidx = 0; 3948 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3949 qidx = QIDX(ctx, m); 3950 /* 3951 * XXX calculate buf_ring based on flowid (divvy up bits?) 3952 */ 3953 txq = &ctx->ifc_txqs[qidx]; 3954 3955 #ifdef DRIVER_BACKPRESSURE 3956 if (txq->ift_closed) { 3957 while (m != NULL) { 3958 next = m->m_nextpkt; 3959 m->m_nextpkt = NULL; 3960 m_freem(m); 3961 DBG_COUNTER_INC(tx_frees); 3962 m = next; 3963 } 3964 return (ENOBUFS); 3965 } 3966 #endif 3967 #ifdef notyet 3968 qidx = count = 0; 3969 mp = marr; 3970 next = m; 3971 do { 3972 count++; 3973 next = next->m_nextpkt; 3974 } while (next != NULL); 3975 3976 if (count > nitems(marr)) 3977 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3978 /* XXX check nextpkt */ 3979 m_freem(m); 3980 /* XXX simplify for now */ 3981 DBG_COUNTER_INC(tx_frees); 3982 return (ENOBUFS); 3983 } 3984 for (next = m, i = 0; next != NULL; i++) { 3985 mp[i] = next; 3986 next = next->m_nextpkt; 3987 mp[i]->m_nextpkt = NULL; 3988 } 3989 #endif 3990 DBG_COUNTER_INC(tx_seen); 3991 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 3992 3993 if (abdicate) 3994 GROUPTASK_ENQUEUE(&txq->ift_task); 3995 if (err) { 3996 if (!abdicate) 3997 GROUPTASK_ENQUEUE(&txq->ift_task); 3998 /* support forthcoming later */ 3999 #ifdef DRIVER_BACKPRESSURE 4000 txq->ift_closed = TRUE; 4001 #endif 4002 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4003 m_freem(m); 4004 DBG_COUNTER_INC(tx_frees); 4005 } 4006 4007 return (err); 4008 } 4009 4010 #ifdef ALTQ 4011 /* 4012 * The overall approach to integrating iflib with ALTQ is to continue to use 4013 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4014 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4015 * is redundant/unnecessary, but doing so minimizes the amount of 4016 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4017 * redundantly queueing to an intermediate mp_ring is swamped by the 4018 * performance limitations inherent in using ALTQ. 4019 * 4020 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4021 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4022 * given interface. If ALTQ is enabled for an interface, then all 4023 * transmitted packets for that interface will be submitted to the ALTQ 4024 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4025 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4026 * update stats that the iflib machinery handles, and which is sensitve to 4027 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4028 * will be installed as the start routine for use by ALTQ facilities that 4029 * need to trigger queue drains on a scheduled basis. 4030 * 4031 */ 4032 static void 4033 iflib_altq_if_start(if_t ifp) 4034 { 4035 struct ifaltq *ifq = &ifp->if_snd; 4036 struct mbuf *m; 4037 4038 IFQ_LOCK(ifq); 4039 IFQ_DEQUEUE_NOLOCK(ifq, m); 4040 while (m != NULL) { 4041 iflib_if_transmit(ifp, m); 4042 IFQ_DEQUEUE_NOLOCK(ifq, m); 4043 } 4044 IFQ_UNLOCK(ifq); 4045 } 4046 4047 static int 4048 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4049 { 4050 int err; 4051 4052 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4053 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4054 if (err == 0) 4055 iflib_altq_if_start(ifp); 4056 } else 4057 err = iflib_if_transmit(ifp, m); 4058 4059 return (err); 4060 } 4061 #endif /* ALTQ */ 4062 4063 static void 4064 iflib_if_qflush(if_t ifp) 4065 { 4066 if_ctx_t ctx = if_getsoftc(ifp); 4067 iflib_txq_t txq = ctx->ifc_txqs; 4068 int i; 4069 4070 STATE_LOCK(ctx); 4071 ctx->ifc_flags |= IFC_QFLUSH; 4072 STATE_UNLOCK(ctx); 4073 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4074 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4075 iflib_txq_check_drain(txq, 0); 4076 STATE_LOCK(ctx); 4077 ctx->ifc_flags &= ~IFC_QFLUSH; 4078 STATE_UNLOCK(ctx); 4079 4080 /* 4081 * When ALTQ is enabled, this will also take care of purging the 4082 * ALTQ queue(s). 4083 */ 4084 if_qflush(ifp); 4085 } 4086 4087 4088 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4089 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4090 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4091 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM) 4092 4093 static int 4094 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4095 { 4096 if_ctx_t ctx = if_getsoftc(ifp); 4097 struct ifreq *ifr = (struct ifreq *)data; 4098 #if defined(INET) || defined(INET6) 4099 struct ifaddr *ifa = (struct ifaddr *)data; 4100 #endif 4101 bool avoid_reset = FALSE; 4102 int err = 0, reinit = 0, bits; 4103 4104 switch (command) { 4105 case SIOCSIFADDR: 4106 #ifdef INET 4107 if (ifa->ifa_addr->sa_family == AF_INET) 4108 avoid_reset = TRUE; 4109 #endif 4110 #ifdef INET6 4111 if (ifa->ifa_addr->sa_family == AF_INET6) 4112 avoid_reset = TRUE; 4113 #endif 4114 /* 4115 ** Calling init results in link renegotiation, 4116 ** so we avoid doing it when possible. 4117 */ 4118 if (avoid_reset) { 4119 if_setflagbits(ifp, IFF_UP,0); 4120 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4121 reinit = 1; 4122 #ifdef INET 4123 if (!(if_getflags(ifp) & IFF_NOARP)) 4124 arp_ifinit(ifp, ifa); 4125 #endif 4126 } else 4127 err = ether_ioctl(ifp, command, data); 4128 break; 4129 case SIOCSIFMTU: 4130 CTX_LOCK(ctx); 4131 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4132 CTX_UNLOCK(ctx); 4133 break; 4134 } 4135 bits = if_getdrvflags(ifp); 4136 /* stop the driver and free any clusters before proceeding */ 4137 iflib_stop(ctx); 4138 4139 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4140 STATE_LOCK(ctx); 4141 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4142 ctx->ifc_flags |= IFC_MULTISEG; 4143 else 4144 ctx->ifc_flags &= ~IFC_MULTISEG; 4145 STATE_UNLOCK(ctx); 4146 err = if_setmtu(ifp, ifr->ifr_mtu); 4147 } 4148 iflib_init_locked(ctx); 4149 STATE_LOCK(ctx); 4150 if_setdrvflags(ifp, bits); 4151 STATE_UNLOCK(ctx); 4152 CTX_UNLOCK(ctx); 4153 break; 4154 case SIOCSIFFLAGS: 4155 CTX_LOCK(ctx); 4156 if (if_getflags(ifp) & IFF_UP) { 4157 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4158 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4159 (IFF_PROMISC | IFF_ALLMULTI)) { 4160 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4161 } 4162 } else 4163 reinit = 1; 4164 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4165 iflib_stop(ctx); 4166 } 4167 ctx->ifc_if_flags = if_getflags(ifp); 4168 CTX_UNLOCK(ctx); 4169 break; 4170 case SIOCADDMULTI: 4171 case SIOCDELMULTI: 4172 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4173 CTX_LOCK(ctx); 4174 IFDI_INTR_DISABLE(ctx); 4175 IFDI_MULTI_SET(ctx); 4176 IFDI_INTR_ENABLE(ctx); 4177 CTX_UNLOCK(ctx); 4178 } 4179 break; 4180 case SIOCSIFMEDIA: 4181 CTX_LOCK(ctx); 4182 IFDI_MEDIA_SET(ctx); 4183 CTX_UNLOCK(ctx); 4184 /* falls thru */ 4185 case SIOCGIFMEDIA: 4186 case SIOCGIFXMEDIA: 4187 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 4188 break; 4189 case SIOCGI2C: 4190 { 4191 struct ifi2creq i2c; 4192 4193 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4194 if (err != 0) 4195 break; 4196 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4197 err = EINVAL; 4198 break; 4199 } 4200 if (i2c.len > sizeof(i2c.data)) { 4201 err = EINVAL; 4202 break; 4203 } 4204 4205 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4206 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4207 sizeof(i2c)); 4208 break; 4209 } 4210 case SIOCSIFCAP: 4211 { 4212 int mask, setmask, oldmask; 4213 4214 oldmask = if_getcapenable(ifp); 4215 mask = ifr->ifr_reqcap ^ oldmask; 4216 mask &= ctx->ifc_softc_ctx.isc_capabilities; 4217 setmask = 0; 4218 #ifdef TCP_OFFLOAD 4219 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4220 #endif 4221 setmask |= (mask & IFCAP_FLAGS); 4222 setmask |= (mask & IFCAP_WOL); 4223 4224 /* 4225 * If any RX csum has changed, change all the ones that 4226 * are supported by the driver. 4227 */ 4228 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4229 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4230 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4231 } 4232 4233 /* 4234 * want to ensure that traffic has stopped before we change any of the flags 4235 */ 4236 if (setmask) { 4237 CTX_LOCK(ctx); 4238 bits = if_getdrvflags(ifp); 4239 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4240 iflib_stop(ctx); 4241 STATE_LOCK(ctx); 4242 if_togglecapenable(ifp, setmask); 4243 STATE_UNLOCK(ctx); 4244 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4245 iflib_init_locked(ctx); 4246 STATE_LOCK(ctx); 4247 if_setdrvflags(ifp, bits); 4248 STATE_UNLOCK(ctx); 4249 CTX_UNLOCK(ctx); 4250 } 4251 if_vlancap(ifp); 4252 break; 4253 } 4254 case SIOCGPRIVATE_0: 4255 case SIOCSDRVSPEC: 4256 case SIOCGDRVSPEC: 4257 CTX_LOCK(ctx); 4258 err = IFDI_PRIV_IOCTL(ctx, command, data); 4259 CTX_UNLOCK(ctx); 4260 break; 4261 default: 4262 err = ether_ioctl(ifp, command, data); 4263 break; 4264 } 4265 if (reinit) 4266 iflib_if_init(ctx); 4267 return (err); 4268 } 4269 4270 static uint64_t 4271 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4272 { 4273 if_ctx_t ctx = if_getsoftc(ifp); 4274 4275 return (IFDI_GET_COUNTER(ctx, cnt)); 4276 } 4277 4278 /********************************************************************* 4279 * 4280 * OTHER FUNCTIONS EXPORTED TO THE STACK 4281 * 4282 **********************************************************************/ 4283 4284 static void 4285 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4286 { 4287 if_ctx_t ctx = if_getsoftc(ifp); 4288 4289 if ((void *)ctx != arg) 4290 return; 4291 4292 if ((vtag == 0) || (vtag > 4095)) 4293 return; 4294 4295 CTX_LOCK(ctx); 4296 IFDI_VLAN_REGISTER(ctx, vtag); 4297 /* Re-init to load the changes */ 4298 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4299 iflib_if_init_locked(ctx); 4300 CTX_UNLOCK(ctx); 4301 } 4302 4303 static void 4304 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4305 { 4306 if_ctx_t ctx = if_getsoftc(ifp); 4307 4308 if ((void *)ctx != arg) 4309 return; 4310 4311 if ((vtag == 0) || (vtag > 4095)) 4312 return; 4313 4314 CTX_LOCK(ctx); 4315 IFDI_VLAN_UNREGISTER(ctx, vtag); 4316 /* Re-init to load the changes */ 4317 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4318 iflib_if_init_locked(ctx); 4319 CTX_UNLOCK(ctx); 4320 } 4321 4322 static void 4323 iflib_led_func(void *arg, int onoff) 4324 { 4325 if_ctx_t ctx = arg; 4326 4327 CTX_LOCK(ctx); 4328 IFDI_LED_FUNC(ctx, onoff); 4329 CTX_UNLOCK(ctx); 4330 } 4331 4332 /********************************************************************* 4333 * 4334 * BUS FUNCTION DEFINITIONS 4335 * 4336 **********************************************************************/ 4337 4338 int 4339 iflib_device_probe(device_t dev) 4340 { 4341 pci_vendor_info_t *ent; 4342 4343 uint16_t pci_vendor_id, pci_device_id; 4344 uint16_t pci_subvendor_id, pci_subdevice_id; 4345 uint16_t pci_rev_id; 4346 if_shared_ctx_t sctx; 4347 4348 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4349 return (ENOTSUP); 4350 4351 pci_vendor_id = pci_get_vendor(dev); 4352 pci_device_id = pci_get_device(dev); 4353 pci_subvendor_id = pci_get_subvendor(dev); 4354 pci_subdevice_id = pci_get_subdevice(dev); 4355 pci_rev_id = pci_get_revid(dev); 4356 if (sctx->isc_parse_devinfo != NULL) 4357 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4358 4359 ent = sctx->isc_vendor_info; 4360 while (ent->pvi_vendor_id != 0) { 4361 if (pci_vendor_id != ent->pvi_vendor_id) { 4362 ent++; 4363 continue; 4364 } 4365 if ((pci_device_id == ent->pvi_device_id) && 4366 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4367 (ent->pvi_subvendor_id == 0)) && 4368 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4369 (ent->pvi_subdevice_id == 0)) && 4370 ((pci_rev_id == ent->pvi_rev_id) || 4371 (ent->pvi_rev_id == 0))) { 4372 4373 device_set_desc_copy(dev, ent->pvi_name); 4374 /* this needs to be changed to zero if the bus probing code 4375 * ever stops re-probing on best match because the sctx 4376 * may have its values over written by register calls 4377 * in subsequent probes 4378 */ 4379 return (BUS_PROBE_DEFAULT); 4380 } 4381 ent++; 4382 } 4383 return (ENXIO); 4384 } 4385 4386 static void 4387 iflib_reset_qvalues(if_ctx_t ctx) 4388 { 4389 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4390 if_shared_ctx_t sctx = ctx->ifc_sctx; 4391 device_t dev = ctx->ifc_dev; 4392 int i; 4393 4394 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES; 4395 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH; 4396 /* 4397 * XXX sanity check that ntxd & nrxd are a power of 2 4398 */ 4399 if (ctx->ifc_sysctl_ntxqs != 0) 4400 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4401 if (ctx->ifc_sysctl_nrxqs != 0) 4402 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4403 4404 for (i = 0; i < sctx->isc_ntxqs; i++) { 4405 if (ctx->ifc_sysctl_ntxds[i] != 0) 4406 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4407 else 4408 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4409 } 4410 4411 for (i = 0; i < sctx->isc_nrxqs; i++) { 4412 if (ctx->ifc_sysctl_nrxds[i] != 0) 4413 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4414 else 4415 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4416 } 4417 4418 for (i = 0; i < sctx->isc_nrxqs; i++) { 4419 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4420 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4421 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4422 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4423 } 4424 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4425 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4426 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4427 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4428 } 4429 } 4430 4431 for (i = 0; i < sctx->isc_ntxqs; i++) { 4432 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4433 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4434 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4435 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4436 } 4437 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4438 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4439 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4440 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4441 } 4442 } 4443 } 4444 4445 static void 4446 iflib_add_pfil(if_ctx_t ctx) 4447 { 4448 struct pfil_head *pfil; 4449 struct pfil_head_args pa; 4450 iflib_rxq_t rxq; 4451 int i; 4452 4453 pa.pa_version = PFIL_VERSION; 4454 pa.pa_flags = PFIL_IN; 4455 pa.pa_type = PFIL_TYPE_ETHERNET; 4456 pa.pa_headname = ctx->ifc_ifp->if_xname; 4457 pfil = pfil_head_register(&pa); 4458 4459 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4460 rxq->pfil = pfil; 4461 } 4462 } 4463 4464 static void 4465 iflib_rem_pfil(if_ctx_t ctx) 4466 { 4467 struct pfil_head *pfil; 4468 iflib_rxq_t rxq; 4469 int i; 4470 4471 rxq = ctx->ifc_rxqs; 4472 pfil = rxq->pfil; 4473 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4474 rxq->pfil = NULL; 4475 } 4476 pfil_head_unregister(pfil); 4477 } 4478 4479 static uint16_t 4480 get_ctx_core_offset(if_ctx_t ctx) 4481 { 4482 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4483 struct cpu_offset *op; 4484 uint16_t qc; 4485 uint16_t ret = ctx->ifc_sysctl_core_offset; 4486 4487 if (ret != CORE_OFFSET_UNSPECIFIED) 4488 return (ret); 4489 4490 if (ctx->ifc_sysctl_separate_txrx) 4491 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets; 4492 else 4493 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets); 4494 4495 mtx_lock(&cpu_offset_mtx); 4496 SLIST_FOREACH(op, &cpu_offsets, entries) { 4497 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4498 ret = op->offset; 4499 op->offset += qc; 4500 MPASS(op->refcount < UINT_MAX); 4501 op->refcount++; 4502 break; 4503 } 4504 } 4505 if (ret == CORE_OFFSET_UNSPECIFIED) { 4506 ret = 0; 4507 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4508 M_NOWAIT | M_ZERO); 4509 if (op == NULL) { 4510 device_printf(ctx->ifc_dev, 4511 "allocation for cpu offset failed.\n"); 4512 } else { 4513 op->offset = qc; 4514 op->refcount = 1; 4515 CPU_COPY(&ctx->ifc_cpus, &op->set); 4516 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4517 } 4518 } 4519 mtx_unlock(&cpu_offset_mtx); 4520 4521 return (ret); 4522 } 4523 4524 static void 4525 unref_ctx_core_offset(if_ctx_t ctx) 4526 { 4527 struct cpu_offset *op, *top; 4528 4529 mtx_lock(&cpu_offset_mtx); 4530 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4531 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4532 MPASS(op->refcount > 0); 4533 op->refcount--; 4534 if (op->refcount == 0) { 4535 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4536 free(op, M_IFLIB); 4537 } 4538 break; 4539 } 4540 } 4541 mtx_unlock(&cpu_offset_mtx); 4542 } 4543 4544 int 4545 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4546 { 4547 int err, rid, msix; 4548 if_ctx_t ctx; 4549 if_t ifp; 4550 if_softc_ctx_t scctx; 4551 int i; 4552 uint16_t main_txq; 4553 uint16_t main_rxq; 4554 4555 4556 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4557 4558 if (sc == NULL) { 4559 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4560 device_set_softc(dev, ctx); 4561 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4562 } 4563 4564 ctx->ifc_sctx = sctx; 4565 ctx->ifc_dev = dev; 4566 ctx->ifc_softc = sc; 4567 4568 if ((err = iflib_register(ctx)) != 0) { 4569 device_printf(dev, "iflib_register failed %d\n", err); 4570 goto fail_ctx_free; 4571 } 4572 iflib_add_device_sysctl_pre(ctx); 4573 4574 scctx = &ctx->ifc_softc_ctx; 4575 ifp = ctx->ifc_ifp; 4576 4577 iflib_reset_qvalues(ctx); 4578 CTX_LOCK(ctx); 4579 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4580 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4581 goto fail_unlock; 4582 } 4583 _iflib_pre_assert(scctx); 4584 ctx->ifc_txrx = *scctx->isc_txrx; 4585 4586 #ifdef INVARIANTS 4587 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4588 MPASS(scctx->isc_tx_csum_flags); 4589 #endif 4590 4591 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS); 4592 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4593 4594 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4595 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4596 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4597 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4598 4599 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4600 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4601 4602 /* XXX change for per-queue sizes */ 4603 device_printf(dev, "Using %d tx descriptors and %d rx descriptors\n", 4604 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4605 for (i = 0; i < sctx->isc_nrxqs; i++) { 4606 if (!powerof2(scctx->isc_nrxd[i])) { 4607 /* round down instead? */ 4608 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4609 err = EINVAL; 4610 goto fail_iflib_detach; 4611 } 4612 } 4613 for (i = 0; i < sctx->isc_ntxqs; i++) { 4614 if (!powerof2(scctx->isc_ntxd[i])) { 4615 device_printf(dev, 4616 "# tx descriptors must be a power of 2"); 4617 err = EINVAL; 4618 goto fail_iflib_detach; 4619 } 4620 } 4621 4622 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4623 MAX_SINGLE_PACKET_FRACTION) 4624 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4625 MAX_SINGLE_PACKET_FRACTION); 4626 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4627 MAX_SINGLE_PACKET_FRACTION) 4628 scctx->isc_tx_tso_segments_max = max(1, 4629 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4630 4631 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4632 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4633 /* 4634 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4635 * but some MACs do. 4636 */ 4637 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4638 IP_MAXPACKET)); 4639 /* 4640 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4641 * into account. In the worst case, each of these calls will 4642 * add another mbuf and, thus, the requirement for another DMA 4643 * segment. So for best performance, it doesn't make sense to 4644 * advertize a maximum of TSO segments that typically will 4645 * require defragmentation in iflib_encap(). 4646 */ 4647 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4648 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4649 } 4650 if (scctx->isc_rss_table_size == 0) 4651 scctx->isc_rss_table_size = 64; 4652 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4653 4654 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4655 /* XXX format name */ 4656 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4657 NULL, NULL, "admin"); 4658 4659 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4660 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4661 device_printf(dev, "Unable to fetch CPU list\n"); 4662 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4663 } 4664 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4665 4666 /* 4667 ** Now set up MSI or MSI-X, should return us the number of supported 4668 ** vectors (will be 1 for a legacy interrupt and MSI). 4669 */ 4670 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4671 msix = scctx->isc_vectors; 4672 } else if (scctx->isc_msix_bar != 0) 4673 /* 4674 * The simple fact that isc_msix_bar is not 0 does not mean we 4675 * we have a good value there that is known to work. 4676 */ 4677 msix = iflib_msix_init(ctx); 4678 else { 4679 scctx->isc_vectors = 1; 4680 scctx->isc_ntxqsets = 1; 4681 scctx->isc_nrxqsets = 1; 4682 scctx->isc_intr = IFLIB_INTR_LEGACY; 4683 msix = 0; 4684 } 4685 /* Get memory for the station queues */ 4686 if ((err = iflib_queues_alloc(ctx))) { 4687 device_printf(dev, "Unable to allocate queue memory\n"); 4688 goto fail_intr_free; 4689 } 4690 4691 if ((err = iflib_qset_structures_setup(ctx))) 4692 goto fail_queues; 4693 4694 /* 4695 * Now that we know how many queues there are, get the core offset. 4696 */ 4697 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 4698 4699 /* 4700 * Group taskqueues aren't properly set up until SMP is started, 4701 * so we disable interrupts until we can handle them post 4702 * SI_SUB_SMP. 4703 * 4704 * XXX: disabling interrupts doesn't actually work, at least for 4705 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4706 * we do null handling and depend on this not causing too large an 4707 * interrupt storm. 4708 */ 4709 IFDI_INTR_DISABLE(ctx); 4710 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4711 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4712 goto fail_queues; 4713 } 4714 if (msix <= 1) { 4715 rid = 0; 4716 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4717 MPASS(msix == 1); 4718 rid = 1; 4719 } 4720 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4721 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4722 goto fail_queues; 4723 } 4724 } 4725 4726 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4727 4728 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4729 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4730 goto fail_detach; 4731 } 4732 4733 /* 4734 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4735 * This must appear after the call to ether_ifattach() because 4736 * ether_ifattach() sets if_hdrlen to the default value. 4737 */ 4738 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4739 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4740 4741 if ((err = iflib_netmap_attach(ctx))) { 4742 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4743 goto fail_detach; 4744 } 4745 *ctxp = ctx; 4746 4747 NETDUMP_SET(ctx->ifc_ifp, iflib); 4748 4749 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4750 iflib_add_device_sysctl_post(ctx); 4751 iflib_add_pfil(ctx); 4752 ctx->ifc_flags |= IFC_INIT_DONE; 4753 CTX_UNLOCK(ctx); 4754 return (0); 4755 4756 fail_detach: 4757 ether_ifdetach(ctx->ifc_ifp); 4758 fail_intr_free: 4759 iflib_free_intr_mem(ctx); 4760 fail_queues: 4761 iflib_tx_structures_free(ctx); 4762 iflib_rx_structures_free(ctx); 4763 fail_iflib_detach: 4764 IFDI_DETACH(ctx); 4765 fail_unlock: 4766 CTX_UNLOCK(ctx); 4767 fail_ctx_free: 4768 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4769 free(ctx->ifc_softc, M_IFLIB); 4770 free(ctx, M_IFLIB); 4771 return (err); 4772 } 4773 4774 int 4775 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4776 struct iflib_cloneattach_ctx *clctx) 4777 { 4778 int err; 4779 if_ctx_t ctx; 4780 if_t ifp; 4781 if_softc_ctx_t scctx; 4782 int i; 4783 void *sc; 4784 uint16_t main_txq; 4785 uint16_t main_rxq; 4786 4787 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4788 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4789 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4790 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4791 ctx->ifc_flags |= IFC_PSEUDO; 4792 4793 ctx->ifc_sctx = sctx; 4794 ctx->ifc_softc = sc; 4795 ctx->ifc_dev = dev; 4796 4797 if ((err = iflib_register(ctx)) != 0) { 4798 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4799 goto fail_ctx_free; 4800 } 4801 iflib_add_device_sysctl_pre(ctx); 4802 4803 scctx = &ctx->ifc_softc_ctx; 4804 ifp = ctx->ifc_ifp; 4805 4806 /* 4807 * XXX sanity check that ntxd & nrxd are a power of 2 4808 */ 4809 iflib_reset_qvalues(ctx); 4810 CTX_LOCK(ctx); 4811 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4812 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4813 goto fail_unlock; 4814 } 4815 if (sctx->isc_flags & IFLIB_GEN_MAC) 4816 ether_gen_addr(ifp, &ctx->ifc_mac); 4817 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4818 clctx->cc_params)) != 0) { 4819 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4820 goto fail_ctx_free; 4821 } 4822 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4823 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 4824 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO); 4825 4826 #ifdef INVARIANTS 4827 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4828 MPASS(scctx->isc_tx_csum_flags); 4829 #endif 4830 4831 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4832 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4833 4834 ifp->if_flags |= IFF_NOGROUP; 4835 if (sctx->isc_flags & IFLIB_PSEUDO) { 4836 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4837 4838 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4839 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4840 goto fail_detach; 4841 } 4842 *ctxp = ctx; 4843 4844 /* 4845 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4846 * This must appear after the call to ether_ifattach() because 4847 * ether_ifattach() sets if_hdrlen to the default value. 4848 */ 4849 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4850 if_setifheaderlen(ifp, 4851 sizeof(struct ether_vlan_header)); 4852 4853 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4854 iflib_add_device_sysctl_post(ctx); 4855 ctx->ifc_flags |= IFC_INIT_DONE; 4856 return (0); 4857 } 4858 _iflib_pre_assert(scctx); 4859 ctx->ifc_txrx = *scctx->isc_txrx; 4860 4861 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4862 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4863 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4864 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4865 4866 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4867 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4868 4869 /* XXX change for per-queue sizes */ 4870 device_printf(dev, "Using %d tx descriptors and %d rx descriptors\n", 4871 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4872 for (i = 0; i < sctx->isc_nrxqs; i++) { 4873 if (!powerof2(scctx->isc_nrxd[i])) { 4874 /* round down instead? */ 4875 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4876 err = EINVAL; 4877 goto fail_iflib_detach; 4878 } 4879 } 4880 for (i = 0; i < sctx->isc_ntxqs; i++) { 4881 if (!powerof2(scctx->isc_ntxd[i])) { 4882 device_printf(dev, 4883 "# tx descriptors must be a power of 2"); 4884 err = EINVAL; 4885 goto fail_iflib_detach; 4886 } 4887 } 4888 4889 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4890 MAX_SINGLE_PACKET_FRACTION) 4891 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4892 MAX_SINGLE_PACKET_FRACTION); 4893 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4894 MAX_SINGLE_PACKET_FRACTION) 4895 scctx->isc_tx_tso_segments_max = max(1, 4896 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4897 4898 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4899 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4900 /* 4901 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4902 * but some MACs do. 4903 */ 4904 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4905 IP_MAXPACKET)); 4906 /* 4907 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4908 * into account. In the worst case, each of these calls will 4909 * add another mbuf and, thus, the requirement for another DMA 4910 * segment. So for best performance, it doesn't make sense to 4911 * advertize a maximum of TSO segments that typically will 4912 * require defragmentation in iflib_encap(). 4913 */ 4914 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4915 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4916 } 4917 if (scctx->isc_rss_table_size == 0) 4918 scctx->isc_rss_table_size = 64; 4919 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4920 4921 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4922 /* XXX format name */ 4923 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4924 NULL, NULL, "admin"); 4925 4926 /* XXX --- can support > 1 -- but keep it simple for now */ 4927 scctx->isc_intr = IFLIB_INTR_LEGACY; 4928 4929 /* Get memory for the station queues */ 4930 if ((err = iflib_queues_alloc(ctx))) { 4931 device_printf(dev, "Unable to allocate queue memory\n"); 4932 goto fail_iflib_detach; 4933 } 4934 4935 if ((err = iflib_qset_structures_setup(ctx))) { 4936 device_printf(dev, "qset structure setup failed %d\n", err); 4937 goto fail_queues; 4938 } 4939 4940 /* 4941 * XXX What if anything do we want to do about interrupts? 4942 */ 4943 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4944 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4945 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4946 goto fail_detach; 4947 } 4948 4949 /* 4950 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4951 * This must appear after the call to ether_ifattach() because 4952 * ether_ifattach() sets if_hdrlen to the default value. 4953 */ 4954 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4955 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4956 4957 /* XXX handle more than one queue */ 4958 for (i = 0; i < scctx->isc_nrxqsets; i++) 4959 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4960 4961 *ctxp = ctx; 4962 4963 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4964 iflib_add_device_sysctl_post(ctx); 4965 ctx->ifc_flags |= IFC_INIT_DONE; 4966 CTX_UNLOCK(ctx); 4967 return (0); 4968 fail_detach: 4969 ether_ifdetach(ctx->ifc_ifp); 4970 fail_queues: 4971 iflib_tx_structures_free(ctx); 4972 iflib_rx_structures_free(ctx); 4973 fail_iflib_detach: 4974 IFDI_DETACH(ctx); 4975 fail_unlock: 4976 CTX_UNLOCK(ctx); 4977 fail_ctx_free: 4978 free(ctx->ifc_softc, M_IFLIB); 4979 free(ctx, M_IFLIB); 4980 return (err); 4981 } 4982 4983 int 4984 iflib_pseudo_deregister(if_ctx_t ctx) 4985 { 4986 if_t ifp = ctx->ifc_ifp; 4987 iflib_txq_t txq; 4988 iflib_rxq_t rxq; 4989 int i, j; 4990 struct taskqgroup *tqg; 4991 iflib_fl_t fl; 4992 4993 /* Unregister VLAN events */ 4994 if (ctx->ifc_vlan_attach_event != NULL) 4995 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4996 if (ctx->ifc_vlan_detach_event != NULL) 4997 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4998 4999 ether_ifdetach(ifp); 5000 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5001 CTX_LOCK_DESTROY(ctx); 5002 /* XXX drain any dependent tasks */ 5003 tqg = qgroup_if_io_tqg; 5004 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5005 callout_drain(&txq->ift_timer); 5006 if (txq->ift_task.gt_uniq != NULL) 5007 taskqgroup_detach(tqg, &txq->ift_task); 5008 } 5009 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5010 if (rxq->ifr_task.gt_uniq != NULL) 5011 taskqgroup_detach(tqg, &rxq->ifr_task); 5012 5013 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5014 free(fl->ifl_rx_bitmap, M_IFLIB); 5015 } 5016 tqg = qgroup_if_config_tqg; 5017 if (ctx->ifc_admin_task.gt_uniq != NULL) 5018 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5019 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5020 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5021 5022 if_free(ifp); 5023 5024 iflib_tx_structures_free(ctx); 5025 iflib_rx_structures_free(ctx); 5026 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5027 free(ctx->ifc_softc, M_IFLIB); 5028 free(ctx, M_IFLIB); 5029 return (0); 5030 } 5031 5032 int 5033 iflib_device_attach(device_t dev) 5034 { 5035 if_ctx_t ctx; 5036 if_shared_ctx_t sctx; 5037 5038 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5039 return (ENOTSUP); 5040 5041 pci_enable_busmaster(dev); 5042 5043 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5044 } 5045 5046 int 5047 iflib_device_deregister(if_ctx_t ctx) 5048 { 5049 if_t ifp = ctx->ifc_ifp; 5050 iflib_txq_t txq; 5051 iflib_rxq_t rxq; 5052 device_t dev = ctx->ifc_dev; 5053 int i, j; 5054 struct taskqgroup *tqg; 5055 iflib_fl_t fl; 5056 5057 /* Make sure VLANS are not using driver */ 5058 if (if_vlantrunkinuse(ifp)) { 5059 device_printf(dev, "Vlan in use, detach first\n"); 5060 return (EBUSY); 5061 } 5062 #ifdef PCI_IOV 5063 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5064 device_printf(dev, "SR-IOV in use; detach first.\n"); 5065 return (EBUSY); 5066 } 5067 #endif 5068 5069 STATE_LOCK(ctx); 5070 ctx->ifc_flags |= IFC_IN_DETACH; 5071 STATE_UNLOCK(ctx); 5072 5073 CTX_LOCK(ctx); 5074 iflib_stop(ctx); 5075 CTX_UNLOCK(ctx); 5076 5077 /* Unregister VLAN events */ 5078 if (ctx->ifc_vlan_attach_event != NULL) 5079 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5080 if (ctx->ifc_vlan_detach_event != NULL) 5081 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5082 5083 iflib_netmap_detach(ifp); 5084 ether_ifdetach(ifp); 5085 iflib_rem_pfil(ctx); 5086 if (ctx->ifc_led_dev != NULL) 5087 led_destroy(ctx->ifc_led_dev); 5088 /* XXX drain any dependent tasks */ 5089 tqg = qgroup_if_io_tqg; 5090 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5091 callout_drain(&txq->ift_timer); 5092 if (txq->ift_task.gt_uniq != NULL) 5093 taskqgroup_detach(tqg, &txq->ift_task); 5094 } 5095 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5096 if (rxq->ifr_task.gt_uniq != NULL) 5097 taskqgroup_detach(tqg, &rxq->ifr_task); 5098 5099 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5100 free(fl->ifl_rx_bitmap, M_IFLIB); 5101 } 5102 tqg = qgroup_if_config_tqg; 5103 if (ctx->ifc_admin_task.gt_uniq != NULL) 5104 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5105 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5106 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5107 CTX_LOCK(ctx); 5108 IFDI_DETACH(ctx); 5109 CTX_UNLOCK(ctx); 5110 5111 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5112 CTX_LOCK_DESTROY(ctx); 5113 device_set_softc(ctx->ifc_dev, NULL); 5114 iflib_free_intr_mem(ctx); 5115 5116 bus_generic_detach(dev); 5117 if_free(ifp); 5118 5119 iflib_tx_structures_free(ctx); 5120 iflib_rx_structures_free(ctx); 5121 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5122 free(ctx->ifc_softc, M_IFLIB); 5123 unref_ctx_core_offset(ctx); 5124 STATE_LOCK_DESTROY(ctx); 5125 free(ctx, M_IFLIB); 5126 return (0); 5127 } 5128 5129 static void 5130 iflib_free_intr_mem(if_ctx_t ctx) 5131 { 5132 5133 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5134 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5135 } 5136 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5137 pci_release_msi(ctx->ifc_dev); 5138 } 5139 if (ctx->ifc_msix_mem != NULL) { 5140 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5141 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5142 ctx->ifc_msix_mem = NULL; 5143 } 5144 } 5145 5146 int 5147 iflib_device_detach(device_t dev) 5148 { 5149 if_ctx_t ctx = device_get_softc(dev); 5150 5151 return (iflib_device_deregister(ctx)); 5152 } 5153 5154 int 5155 iflib_device_suspend(device_t dev) 5156 { 5157 if_ctx_t ctx = device_get_softc(dev); 5158 5159 CTX_LOCK(ctx); 5160 IFDI_SUSPEND(ctx); 5161 CTX_UNLOCK(ctx); 5162 5163 return bus_generic_suspend(dev); 5164 } 5165 int 5166 iflib_device_shutdown(device_t dev) 5167 { 5168 if_ctx_t ctx = device_get_softc(dev); 5169 5170 CTX_LOCK(ctx); 5171 IFDI_SHUTDOWN(ctx); 5172 CTX_UNLOCK(ctx); 5173 5174 return bus_generic_suspend(dev); 5175 } 5176 5177 5178 int 5179 iflib_device_resume(device_t dev) 5180 { 5181 if_ctx_t ctx = device_get_softc(dev); 5182 iflib_txq_t txq = ctx->ifc_txqs; 5183 5184 CTX_LOCK(ctx); 5185 IFDI_RESUME(ctx); 5186 iflib_if_init_locked(ctx); 5187 CTX_UNLOCK(ctx); 5188 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5189 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5190 5191 return (bus_generic_resume(dev)); 5192 } 5193 5194 int 5195 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5196 { 5197 int error; 5198 if_ctx_t ctx = device_get_softc(dev); 5199 5200 CTX_LOCK(ctx); 5201 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5202 CTX_UNLOCK(ctx); 5203 5204 return (error); 5205 } 5206 5207 void 5208 iflib_device_iov_uninit(device_t dev) 5209 { 5210 if_ctx_t ctx = device_get_softc(dev); 5211 5212 CTX_LOCK(ctx); 5213 IFDI_IOV_UNINIT(ctx); 5214 CTX_UNLOCK(ctx); 5215 } 5216 5217 int 5218 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5219 { 5220 int error; 5221 if_ctx_t ctx = device_get_softc(dev); 5222 5223 CTX_LOCK(ctx); 5224 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5225 CTX_UNLOCK(ctx); 5226 5227 return (error); 5228 } 5229 5230 /********************************************************************* 5231 * 5232 * MODULE FUNCTION DEFINITIONS 5233 * 5234 **********************************************************************/ 5235 5236 /* 5237 * - Start a fast taskqueue thread for each core 5238 * - Start a taskqueue for control operations 5239 */ 5240 static int 5241 iflib_module_init(void) 5242 { 5243 return (0); 5244 } 5245 5246 static int 5247 iflib_module_event_handler(module_t mod, int what, void *arg) 5248 { 5249 int err; 5250 5251 switch (what) { 5252 case MOD_LOAD: 5253 if ((err = iflib_module_init()) != 0) 5254 return (err); 5255 break; 5256 case MOD_UNLOAD: 5257 return (EBUSY); 5258 default: 5259 return (EOPNOTSUPP); 5260 } 5261 5262 return (0); 5263 } 5264 5265 /********************************************************************* 5266 * 5267 * PUBLIC FUNCTION DEFINITIONS 5268 * ordered as in iflib.h 5269 * 5270 **********************************************************************/ 5271 5272 5273 static void 5274 _iflib_assert(if_shared_ctx_t sctx) 5275 { 5276 MPASS(sctx->isc_tx_maxsize); 5277 MPASS(sctx->isc_tx_maxsegsize); 5278 5279 MPASS(sctx->isc_rx_maxsize); 5280 MPASS(sctx->isc_rx_nsegments); 5281 MPASS(sctx->isc_rx_maxsegsize); 5282 5283 MPASS(sctx->isc_nrxd_min[0]); 5284 MPASS(sctx->isc_nrxd_max[0]); 5285 MPASS(sctx->isc_nrxd_default[0]); 5286 MPASS(sctx->isc_ntxd_min[0]); 5287 MPASS(sctx->isc_ntxd_max[0]); 5288 MPASS(sctx->isc_ntxd_default[0]); 5289 } 5290 5291 static void 5292 _iflib_pre_assert(if_softc_ctx_t scctx) 5293 { 5294 5295 MPASS(scctx->isc_txrx->ift_txd_encap); 5296 MPASS(scctx->isc_txrx->ift_txd_flush); 5297 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5298 MPASS(scctx->isc_txrx->ift_rxd_available); 5299 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5300 MPASS(scctx->isc_txrx->ift_rxd_refill); 5301 MPASS(scctx->isc_txrx->ift_rxd_flush); 5302 } 5303 5304 static int 5305 iflib_register(if_ctx_t ctx) 5306 { 5307 if_shared_ctx_t sctx = ctx->ifc_sctx; 5308 driver_t *driver = sctx->isc_driver; 5309 device_t dev = ctx->ifc_dev; 5310 if_t ifp; 5311 5312 _iflib_assert(sctx); 5313 5314 CTX_LOCK_INIT(ctx); 5315 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5316 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5317 if (ifp == NULL) { 5318 device_printf(dev, "can not allocate ifnet structure\n"); 5319 return (ENOMEM); 5320 } 5321 5322 /* 5323 * Initialize our context's device specific methods 5324 */ 5325 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5326 kobj_class_compile((kobj_class_t) driver); 5327 driver->refs++; 5328 5329 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5330 if_setsoftc(ifp, ctx); 5331 if_setdev(ifp, dev); 5332 if_setinitfn(ifp, iflib_if_init); 5333 if_setioctlfn(ifp, iflib_if_ioctl); 5334 #ifdef ALTQ 5335 if_setstartfn(ifp, iflib_altq_if_start); 5336 if_settransmitfn(ifp, iflib_altq_if_transmit); 5337 if_setsendqready(ifp); 5338 #else 5339 if_settransmitfn(ifp, iflib_if_transmit); 5340 #endif 5341 if_setqflushfn(ifp, iflib_if_qflush); 5342 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5343 5344 ctx->ifc_vlan_attach_event = 5345 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5346 EVENTHANDLER_PRI_FIRST); 5347 ctx->ifc_vlan_detach_event = 5348 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5349 EVENTHANDLER_PRI_FIRST); 5350 5351 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 5352 iflib_media_change, iflib_media_status); 5353 5354 return (0); 5355 } 5356 5357 5358 static int 5359 iflib_queues_alloc(if_ctx_t ctx) 5360 { 5361 if_shared_ctx_t sctx = ctx->ifc_sctx; 5362 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5363 device_t dev = ctx->ifc_dev; 5364 int nrxqsets = scctx->isc_nrxqsets; 5365 int ntxqsets = scctx->isc_ntxqsets; 5366 iflib_txq_t txq; 5367 iflib_rxq_t rxq; 5368 iflib_fl_t fl = NULL; 5369 int i, j, cpu, err, txconf, rxconf; 5370 iflib_dma_info_t ifdip; 5371 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5372 uint32_t *txqsizes = scctx->isc_txqsizes; 5373 uint8_t nrxqs = sctx->isc_nrxqs; 5374 uint8_t ntxqs = sctx->isc_ntxqs; 5375 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5376 caddr_t *vaddrs; 5377 uint64_t *paddrs; 5378 5379 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5380 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5381 5382 /* Allocate the TX ring struct memory */ 5383 if (!(ctx->ifc_txqs = 5384 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5385 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5386 device_printf(dev, "Unable to allocate TX ring memory\n"); 5387 err = ENOMEM; 5388 goto fail; 5389 } 5390 5391 /* Now allocate the RX */ 5392 if (!(ctx->ifc_rxqs = 5393 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5394 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5395 device_printf(dev, "Unable to allocate RX ring memory\n"); 5396 err = ENOMEM; 5397 goto rx_fail; 5398 } 5399 5400 txq = ctx->ifc_txqs; 5401 rxq = ctx->ifc_rxqs; 5402 5403 /* 5404 * XXX handle allocation failure 5405 */ 5406 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5407 /* Set up some basics */ 5408 5409 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5410 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5411 device_printf(dev, 5412 "Unable to allocate TX DMA info memory\n"); 5413 err = ENOMEM; 5414 goto err_tx_desc; 5415 } 5416 txq->ift_ifdi = ifdip; 5417 for (j = 0; j < ntxqs; j++, ifdip++) { 5418 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5419 device_printf(dev, 5420 "Unable to allocate TX descriptors\n"); 5421 err = ENOMEM; 5422 goto err_tx_desc; 5423 } 5424 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5425 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5426 } 5427 txq->ift_ctx = ctx; 5428 txq->ift_id = i; 5429 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5430 txq->ift_br_offset = 1; 5431 } else { 5432 txq->ift_br_offset = 0; 5433 } 5434 /* XXX fix this */ 5435 txq->ift_timer.c_cpu = cpu; 5436 5437 if (iflib_txsd_alloc(txq)) { 5438 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5439 err = ENOMEM; 5440 goto err_tx_desc; 5441 } 5442 5443 /* Initialize the TX lock */ 5444 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 5445 device_get_nameunit(dev), txq->ift_id); 5446 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5447 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5448 5449 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 5450 device_get_nameunit(dev), txq->ift_id); 5451 5452 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5453 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5454 if (err) { 5455 /* XXX free any allocated rings */ 5456 device_printf(dev, "Unable to allocate buf_ring\n"); 5457 goto err_tx_desc; 5458 } 5459 } 5460 5461 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5462 /* Set up some basics */ 5463 5464 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5465 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5466 device_printf(dev, 5467 "Unable to allocate RX DMA info memory\n"); 5468 err = ENOMEM; 5469 goto err_tx_desc; 5470 } 5471 5472 rxq->ifr_ifdi = ifdip; 5473 /* XXX this needs to be changed if #rx queues != #tx queues */ 5474 rxq->ifr_ntxqirq = 1; 5475 rxq->ifr_txqid[0] = i; 5476 for (j = 0; j < nrxqs; j++, ifdip++) { 5477 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5478 device_printf(dev, 5479 "Unable to allocate RX descriptors\n"); 5480 err = ENOMEM; 5481 goto err_tx_desc; 5482 } 5483 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5484 } 5485 rxq->ifr_ctx = ctx; 5486 rxq->ifr_id = i; 5487 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5488 rxq->ifr_fl_offset = 1; 5489 } else { 5490 rxq->ifr_fl_offset = 0; 5491 } 5492 rxq->ifr_nfl = nfree_lists; 5493 if (!(fl = 5494 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5495 device_printf(dev, "Unable to allocate free list memory\n"); 5496 err = ENOMEM; 5497 goto err_tx_desc; 5498 } 5499 rxq->ifr_fl = fl; 5500 for (j = 0; j < nfree_lists; j++) { 5501 fl[j].ifl_rxq = rxq; 5502 fl[j].ifl_id = j; 5503 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5504 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5505 } 5506 /* Allocate receive buffers for the ring */ 5507 if (iflib_rxsd_alloc(rxq)) { 5508 device_printf(dev, 5509 "Critical Failure setting up receive buffers\n"); 5510 err = ENOMEM; 5511 goto err_rx_desc; 5512 } 5513 5514 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5515 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5516 M_WAITOK); 5517 } 5518 5519 /* TXQs */ 5520 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5521 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5522 for (i = 0; i < ntxqsets; i++) { 5523 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5524 5525 for (j = 0; j < ntxqs; j++, di++) { 5526 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5527 paddrs[i*ntxqs + j] = di->idi_paddr; 5528 } 5529 } 5530 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5531 device_printf(ctx->ifc_dev, 5532 "Unable to allocate device TX queue\n"); 5533 iflib_tx_structures_free(ctx); 5534 free(vaddrs, M_IFLIB); 5535 free(paddrs, M_IFLIB); 5536 goto err_rx_desc; 5537 } 5538 free(vaddrs, M_IFLIB); 5539 free(paddrs, M_IFLIB); 5540 5541 /* RXQs */ 5542 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5543 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5544 for (i = 0; i < nrxqsets; i++) { 5545 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5546 5547 for (j = 0; j < nrxqs; j++, di++) { 5548 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5549 paddrs[i*nrxqs + j] = di->idi_paddr; 5550 } 5551 } 5552 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5553 device_printf(ctx->ifc_dev, 5554 "Unable to allocate device RX queue\n"); 5555 iflib_tx_structures_free(ctx); 5556 free(vaddrs, M_IFLIB); 5557 free(paddrs, M_IFLIB); 5558 goto err_rx_desc; 5559 } 5560 free(vaddrs, M_IFLIB); 5561 free(paddrs, M_IFLIB); 5562 5563 return (0); 5564 5565 /* XXX handle allocation failure changes */ 5566 err_rx_desc: 5567 err_tx_desc: 5568 rx_fail: 5569 if (ctx->ifc_rxqs != NULL) 5570 free(ctx->ifc_rxqs, M_IFLIB); 5571 ctx->ifc_rxqs = NULL; 5572 if (ctx->ifc_txqs != NULL) 5573 free(ctx->ifc_txqs, M_IFLIB); 5574 ctx->ifc_txqs = NULL; 5575 fail: 5576 return (err); 5577 } 5578 5579 static int 5580 iflib_tx_structures_setup(if_ctx_t ctx) 5581 { 5582 iflib_txq_t txq = ctx->ifc_txqs; 5583 int i; 5584 5585 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5586 iflib_txq_setup(txq); 5587 5588 return (0); 5589 } 5590 5591 static void 5592 iflib_tx_structures_free(if_ctx_t ctx) 5593 { 5594 iflib_txq_t txq = ctx->ifc_txqs; 5595 if_shared_ctx_t sctx = ctx->ifc_sctx; 5596 int i, j; 5597 5598 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5599 iflib_txq_destroy(txq); 5600 for (j = 0; j < sctx->isc_ntxqs; j++) 5601 iflib_dma_free(&txq->ift_ifdi[j]); 5602 } 5603 free(ctx->ifc_txqs, M_IFLIB); 5604 ctx->ifc_txqs = NULL; 5605 IFDI_QUEUES_FREE(ctx); 5606 } 5607 5608 /********************************************************************* 5609 * 5610 * Initialize all receive rings. 5611 * 5612 **********************************************************************/ 5613 static int 5614 iflib_rx_structures_setup(if_ctx_t ctx) 5615 { 5616 iflib_rxq_t rxq = ctx->ifc_rxqs; 5617 int q; 5618 #if defined(INET6) || defined(INET) 5619 int i, err; 5620 #endif 5621 5622 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5623 #if defined(INET6) || defined(INET) 5624 tcp_lro_free(&rxq->ifr_lc); 5625 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5626 TCP_LRO_ENTRIES, min(1024, 5627 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 5628 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 5629 goto fail; 5630 } 5631 rxq->ifr_lro_enabled = TRUE; 5632 #endif 5633 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5634 } 5635 return (0); 5636 #if defined(INET6) || defined(INET) 5637 fail: 5638 /* 5639 * Free RX software descriptors allocated so far, we will only handle 5640 * the rings that completed, the failing case will have 5641 * cleaned up for itself. 'q' failed, so its the terminus. 5642 */ 5643 rxq = ctx->ifc_rxqs; 5644 for (i = 0; i < q; ++i, rxq++) { 5645 iflib_rx_sds_free(rxq); 5646 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5647 } 5648 return (err); 5649 #endif 5650 } 5651 5652 /********************************************************************* 5653 * 5654 * Free all receive rings. 5655 * 5656 **********************************************************************/ 5657 static void 5658 iflib_rx_structures_free(if_ctx_t ctx) 5659 { 5660 iflib_rxq_t rxq = ctx->ifc_rxqs; 5661 5662 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5663 iflib_rx_sds_free(rxq); 5664 } 5665 free(ctx->ifc_rxqs, M_IFLIB); 5666 ctx->ifc_rxqs = NULL; 5667 } 5668 5669 static int 5670 iflib_qset_structures_setup(if_ctx_t ctx) 5671 { 5672 int err; 5673 5674 /* 5675 * It is expected that the caller takes care of freeing queues if this 5676 * fails. 5677 */ 5678 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5679 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5680 return (err); 5681 } 5682 5683 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5684 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5685 5686 return (err); 5687 } 5688 5689 int 5690 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5691 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5692 { 5693 5694 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5695 } 5696 5697 #ifdef SMP 5698 static int 5699 find_nth(if_ctx_t ctx, int qid) 5700 { 5701 cpuset_t cpus; 5702 int i, cpuid, eqid, count; 5703 5704 CPU_COPY(&ctx->ifc_cpus, &cpus); 5705 count = CPU_COUNT(&cpus); 5706 eqid = qid % count; 5707 /* clear up to the qid'th bit */ 5708 for (i = 0; i < eqid; i++) { 5709 cpuid = CPU_FFS(&cpus); 5710 MPASS(cpuid != 0); 5711 CPU_CLR(cpuid-1, &cpus); 5712 } 5713 cpuid = CPU_FFS(&cpus); 5714 MPASS(cpuid != 0); 5715 return (cpuid-1); 5716 } 5717 5718 #ifdef SCHED_ULE 5719 extern struct cpu_group *cpu_top; /* CPU topology */ 5720 5721 static int 5722 find_child_with_core(int cpu, struct cpu_group *grp) 5723 { 5724 int i; 5725 5726 if (grp->cg_children == 0) 5727 return -1; 5728 5729 MPASS(grp->cg_child); 5730 for (i = 0; i < grp->cg_children; i++) { 5731 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5732 return i; 5733 } 5734 5735 return -1; 5736 } 5737 5738 /* 5739 * Find the nth "close" core to the specified core 5740 * "close" is defined as the deepest level that shares 5741 * at least an L2 cache. With threads, this will be 5742 * threads on the same core. If the shared cache is L3 5743 * or higher, simply returns the same core. 5744 */ 5745 static int 5746 find_close_core(int cpu, int core_offset) 5747 { 5748 struct cpu_group *grp; 5749 int i; 5750 int fcpu; 5751 cpuset_t cs; 5752 5753 grp = cpu_top; 5754 if (grp == NULL) 5755 return cpu; 5756 i = 0; 5757 while ((i = find_child_with_core(cpu, grp)) != -1) { 5758 /* If the child only has one cpu, don't descend */ 5759 if (grp->cg_child[i].cg_count <= 1) 5760 break; 5761 grp = &grp->cg_child[i]; 5762 } 5763 5764 /* If they don't share at least an L2 cache, use the same CPU */ 5765 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5766 return cpu; 5767 5768 /* Now pick one */ 5769 CPU_COPY(&grp->cg_mask, &cs); 5770 5771 /* Add the selected CPU offset to core offset. */ 5772 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5773 if (fcpu - 1 == cpu) 5774 break; 5775 CPU_CLR(fcpu - 1, &cs); 5776 } 5777 MPASS(fcpu); 5778 5779 core_offset += i; 5780 5781 CPU_COPY(&grp->cg_mask, &cs); 5782 for (i = core_offset % grp->cg_count; i > 0; i--) { 5783 MPASS(CPU_FFS(&cs)); 5784 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5785 } 5786 MPASS(CPU_FFS(&cs)); 5787 return CPU_FFS(&cs) - 1; 5788 } 5789 #else 5790 static int 5791 find_close_core(int cpu, int core_offset __unused) 5792 { 5793 return cpu; 5794 } 5795 #endif 5796 5797 static int 5798 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5799 { 5800 switch (type) { 5801 case IFLIB_INTR_TX: 5802 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5803 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5804 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5805 case IFLIB_INTR_RX: 5806 case IFLIB_INTR_RXTX: 5807 /* RX queues get the specified core */ 5808 return qid / CPU_COUNT(&ctx->ifc_cpus); 5809 default: 5810 return -1; 5811 } 5812 } 5813 #else 5814 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5815 #define find_close_core(cpuid, tid) CPU_FIRST() 5816 #define find_nth(ctx, gid) CPU_FIRST() 5817 #endif 5818 5819 /* Just to avoid copy/paste */ 5820 static inline int 5821 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5822 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5823 const char *name) 5824 { 5825 device_t dev; 5826 int co, cpuid, err, tid; 5827 5828 dev = ctx->ifc_dev; 5829 co = ctx->ifc_sysctl_core_offset; 5830 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX) 5831 co += ctx->ifc_softc_ctx.isc_nrxqsets; 5832 cpuid = find_nth(ctx, qid + co); 5833 tid = get_core_offset(ctx, type, qid); 5834 MPASS(tid >= 0); 5835 cpuid = find_close_core(cpuid, tid); 5836 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 5837 name); 5838 if (err) { 5839 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 5840 return (err); 5841 } 5842 #ifdef notyet 5843 if (cpuid > ctx->ifc_cpuid_highest) 5844 ctx->ifc_cpuid_highest = cpuid; 5845 #endif 5846 return 0; 5847 } 5848 5849 int 5850 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5851 iflib_intr_type_t type, driver_filter_t *filter, 5852 void *filter_arg, int qid, const char *name) 5853 { 5854 device_t dev; 5855 struct grouptask *gtask; 5856 struct taskqgroup *tqg; 5857 iflib_filter_info_t info; 5858 gtask_fn_t *fn; 5859 int tqrid, err; 5860 driver_filter_t *intr_fast; 5861 void *q; 5862 5863 info = &ctx->ifc_filter_info; 5864 tqrid = rid; 5865 5866 switch (type) { 5867 /* XXX merge tx/rx for netmap? */ 5868 case IFLIB_INTR_TX: 5869 q = &ctx->ifc_txqs[qid]; 5870 info = &ctx->ifc_txqs[qid].ift_filter_info; 5871 gtask = &ctx->ifc_txqs[qid].ift_task; 5872 tqg = qgroup_if_io_tqg; 5873 fn = _task_fn_tx; 5874 intr_fast = iflib_fast_intr; 5875 GROUPTASK_INIT(gtask, 0, fn, q); 5876 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5877 break; 5878 case IFLIB_INTR_RX: 5879 q = &ctx->ifc_rxqs[qid]; 5880 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5881 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5882 tqg = qgroup_if_io_tqg; 5883 fn = _task_fn_rx; 5884 intr_fast = iflib_fast_intr; 5885 GROUPTASK_INIT(gtask, 0, fn, q); 5886 break; 5887 case IFLIB_INTR_RXTX: 5888 q = &ctx->ifc_rxqs[qid]; 5889 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5890 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5891 tqg = qgroup_if_io_tqg; 5892 fn = _task_fn_rx; 5893 intr_fast = iflib_fast_intr_rxtx; 5894 GROUPTASK_INIT(gtask, 0, fn, q); 5895 break; 5896 case IFLIB_INTR_ADMIN: 5897 q = ctx; 5898 tqrid = -1; 5899 info = &ctx->ifc_filter_info; 5900 gtask = &ctx->ifc_admin_task; 5901 tqg = qgroup_if_config_tqg; 5902 fn = _task_fn_admin; 5903 intr_fast = iflib_fast_intr_ctx; 5904 break; 5905 default: 5906 panic("unknown net intr type"); 5907 } 5908 5909 info->ifi_filter = filter; 5910 info->ifi_filter_arg = filter_arg; 5911 info->ifi_task = gtask; 5912 info->ifi_ctx = q; 5913 5914 dev = ctx->ifc_dev; 5915 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5916 if (err != 0) { 5917 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 5918 return (err); 5919 } 5920 if (type == IFLIB_INTR_ADMIN) 5921 return (0); 5922 5923 if (tqrid != -1) { 5924 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 5925 q, name); 5926 if (err) 5927 return (err); 5928 } else { 5929 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 5930 } 5931 5932 return (0); 5933 } 5934 5935 void 5936 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 5937 { 5938 struct grouptask *gtask; 5939 struct taskqgroup *tqg; 5940 gtask_fn_t *fn; 5941 void *q; 5942 int err; 5943 5944 switch (type) { 5945 case IFLIB_INTR_TX: 5946 q = &ctx->ifc_txqs[qid]; 5947 gtask = &ctx->ifc_txqs[qid].ift_task; 5948 tqg = qgroup_if_io_tqg; 5949 fn = _task_fn_tx; 5950 break; 5951 case IFLIB_INTR_RX: 5952 q = &ctx->ifc_rxqs[qid]; 5953 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5954 tqg = qgroup_if_io_tqg; 5955 fn = _task_fn_rx; 5956 break; 5957 case IFLIB_INTR_IOV: 5958 q = ctx; 5959 gtask = &ctx->ifc_vflr_task; 5960 tqg = qgroup_if_config_tqg; 5961 fn = _task_fn_iov; 5962 break; 5963 default: 5964 panic("unknown net intr type"); 5965 } 5966 GROUPTASK_INIT(gtask, 0, fn, q); 5967 if (irq != NULL) { 5968 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 5969 q, name); 5970 if (err) 5971 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 5972 irq->ii_res, name); 5973 } else { 5974 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 5975 } 5976 } 5977 5978 void 5979 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5980 { 5981 5982 if (irq->ii_tag) 5983 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5984 5985 if (irq->ii_res) 5986 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 5987 rman_get_rid(irq->ii_res), irq->ii_res); 5988 } 5989 5990 static int 5991 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 5992 { 5993 iflib_txq_t txq = ctx->ifc_txqs; 5994 iflib_rxq_t rxq = ctx->ifc_rxqs; 5995 if_irq_t irq = &ctx->ifc_legacy_irq; 5996 iflib_filter_info_t info; 5997 device_t dev; 5998 struct grouptask *gtask; 5999 struct resource *res; 6000 struct taskqgroup *tqg; 6001 gtask_fn_t *fn; 6002 int tqrid; 6003 void *q; 6004 int err; 6005 6006 q = &ctx->ifc_rxqs[0]; 6007 info = &rxq[0].ifr_filter_info; 6008 gtask = &rxq[0].ifr_task; 6009 tqg = qgroup_if_io_tqg; 6010 tqrid = irq->ii_rid = *rid; 6011 fn = _task_fn_rx; 6012 6013 ctx->ifc_flags |= IFC_LEGACY; 6014 info->ifi_filter = filter; 6015 info->ifi_filter_arg = filter_arg; 6016 info->ifi_task = gtask; 6017 info->ifi_ctx = ctx; 6018 6019 dev = ctx->ifc_dev; 6020 /* We allocate a single interrupt resource */ 6021 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 6022 return (err); 6023 GROUPTASK_INIT(gtask, 0, fn, q); 6024 res = irq->ii_res; 6025 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6026 6027 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6028 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6029 "tx"); 6030 return (0); 6031 } 6032 6033 void 6034 iflib_led_create(if_ctx_t ctx) 6035 { 6036 6037 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6038 device_get_nameunit(ctx->ifc_dev)); 6039 } 6040 6041 void 6042 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6043 { 6044 6045 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6046 } 6047 6048 void 6049 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6050 { 6051 6052 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6053 } 6054 6055 void 6056 iflib_admin_intr_deferred(if_ctx_t ctx) 6057 { 6058 #ifdef INVARIANTS 6059 struct grouptask *gtask; 6060 6061 gtask = &ctx->ifc_admin_task; 6062 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 6063 #endif 6064 6065 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6066 } 6067 6068 void 6069 iflib_iov_intr_deferred(if_ctx_t ctx) 6070 { 6071 6072 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6073 } 6074 6075 void 6076 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 6077 { 6078 6079 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6080 name); 6081 } 6082 6083 void 6084 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6085 const char *name) 6086 { 6087 6088 GROUPTASK_INIT(gtask, 0, fn, ctx); 6089 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6090 name); 6091 } 6092 6093 void 6094 iflib_config_gtask_deinit(struct grouptask *gtask) 6095 { 6096 6097 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6098 } 6099 6100 void 6101 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6102 { 6103 if_t ifp = ctx->ifc_ifp; 6104 iflib_txq_t txq = ctx->ifc_txqs; 6105 6106 if_setbaudrate(ifp, baudrate); 6107 if (baudrate >= IF_Gbps(10)) { 6108 STATE_LOCK(ctx); 6109 ctx->ifc_flags |= IFC_PREFETCH; 6110 STATE_UNLOCK(ctx); 6111 } 6112 /* If link down, disable watchdog */ 6113 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6114 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6115 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6116 } 6117 ctx->ifc_link_state = link_state; 6118 if_link_state_change(ifp, link_state); 6119 } 6120 6121 static int 6122 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6123 { 6124 int credits; 6125 #ifdef INVARIANTS 6126 int credits_pre = txq->ift_cidx_processed; 6127 #endif 6128 6129 if (ctx->isc_txd_credits_update == NULL) 6130 return (0); 6131 6132 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6133 BUS_DMASYNC_POSTREAD); 6134 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6135 return (0); 6136 6137 txq->ift_processed += credits; 6138 txq->ift_cidx_processed += credits; 6139 6140 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6141 if (txq->ift_cidx_processed >= txq->ift_size) 6142 txq->ift_cidx_processed -= txq->ift_size; 6143 return (credits); 6144 } 6145 6146 static int 6147 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6148 { 6149 iflib_fl_t fl; 6150 u_int i; 6151 6152 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6153 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6154 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6155 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6156 budget)); 6157 } 6158 6159 void 6160 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6161 const char *description, if_int_delay_info_t info, 6162 int offset, int value) 6163 { 6164 info->iidi_ctx = ctx; 6165 info->iidi_offset = offset; 6166 info->iidi_value = value; 6167 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6168 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6169 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 6170 info, 0, iflib_sysctl_int_delay, "I", description); 6171 } 6172 6173 struct sx * 6174 iflib_ctx_lock_get(if_ctx_t ctx) 6175 { 6176 6177 return (&ctx->ifc_ctx_sx); 6178 } 6179 6180 static int 6181 iflib_msix_init(if_ctx_t ctx) 6182 { 6183 device_t dev = ctx->ifc_dev; 6184 if_shared_ctx_t sctx = ctx->ifc_sctx; 6185 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6186 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 6187 int iflib_num_tx_queues, iflib_num_rx_queues; 6188 int err, admincnt, bar; 6189 6190 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6191 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6192 6193 if (bootverbose) 6194 device_printf(dev, "msix_init qsets capped at %d\n", 6195 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6196 6197 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6198 admincnt = sctx->isc_admin_intrcnt; 6199 /* Override by tuneable */ 6200 if (scctx->isc_disable_msix) 6201 goto msi; 6202 6203 /* First try MSI-X */ 6204 if ((msgs = pci_msix_count(dev)) == 0) { 6205 if (bootverbose) 6206 device_printf(dev, "MSI-X not supported or disabled\n"); 6207 goto msi; 6208 } 6209 /* 6210 * bar == -1 => "trust me I know what I'm doing" 6211 * Some drivers are for hardware that is so shoddily 6212 * documented that no one knows which bars are which 6213 * so the developer has to map all bars. This hack 6214 * allows shoddy garbage to use MSI-X in this framework. 6215 */ 6216 if (bar != -1) { 6217 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6218 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6219 if (ctx->ifc_msix_mem == NULL) { 6220 device_printf(dev, "Unable to map MSI-X table\n"); 6221 goto msi; 6222 } 6223 } 6224 #if IFLIB_DEBUG 6225 /* use only 1 qset in debug mode */ 6226 queuemsgs = min(msgs - admincnt, 1); 6227 #else 6228 queuemsgs = msgs - admincnt; 6229 #endif 6230 #ifdef RSS 6231 queues = imin(queuemsgs, rss_getnumbuckets()); 6232 #else 6233 queues = queuemsgs; 6234 #endif 6235 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6236 if (bootverbose) 6237 device_printf(dev, 6238 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6239 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6240 #ifdef RSS 6241 /* If we're doing RSS, clamp at the number of RSS buckets */ 6242 if (queues > rss_getnumbuckets()) 6243 queues = rss_getnumbuckets(); 6244 #endif 6245 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6246 rx_queues = iflib_num_rx_queues; 6247 else 6248 rx_queues = queues; 6249 6250 if (rx_queues > scctx->isc_nrxqsets) 6251 rx_queues = scctx->isc_nrxqsets; 6252 6253 /* 6254 * We want this to be all logical CPUs by default 6255 */ 6256 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6257 tx_queues = iflib_num_tx_queues; 6258 else 6259 tx_queues = mp_ncpus; 6260 6261 if (tx_queues > scctx->isc_ntxqsets) 6262 tx_queues = scctx->isc_ntxqsets; 6263 6264 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6265 #ifdef INVARIANTS 6266 if (tx_queues != rx_queues) 6267 device_printf(dev, 6268 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6269 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6270 #endif 6271 tx_queues = min(rx_queues, tx_queues); 6272 rx_queues = min(rx_queues, tx_queues); 6273 } 6274 6275 device_printf(dev, "Using %d rx queues %d tx queues\n", 6276 rx_queues, tx_queues); 6277 6278 vectors = rx_queues + admincnt; 6279 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6280 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6281 vectors); 6282 scctx->isc_vectors = vectors; 6283 scctx->isc_nrxqsets = rx_queues; 6284 scctx->isc_ntxqsets = tx_queues; 6285 scctx->isc_intr = IFLIB_INTR_MSIX; 6286 6287 return (vectors); 6288 } else { 6289 device_printf(dev, 6290 "failed to allocate %d MSI-X vectors, err: %d - using MSI\n", 6291 vectors, err); 6292 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6293 ctx->ifc_msix_mem); 6294 ctx->ifc_msix_mem = NULL; 6295 } 6296 msi: 6297 vectors = pci_msi_count(dev); 6298 scctx->isc_nrxqsets = 1; 6299 scctx->isc_ntxqsets = 1; 6300 scctx->isc_vectors = vectors; 6301 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6302 device_printf(dev,"Using an MSI interrupt\n"); 6303 scctx->isc_intr = IFLIB_INTR_MSI; 6304 } else { 6305 scctx->isc_vectors = 1; 6306 device_printf(dev,"Using a Legacy interrupt\n"); 6307 scctx->isc_intr = IFLIB_INTR_LEGACY; 6308 } 6309 6310 return (vectors); 6311 } 6312 6313 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6314 6315 static int 6316 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6317 { 6318 int rc; 6319 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6320 struct sbuf *sb; 6321 const char *ring_state = "UNKNOWN"; 6322 6323 /* XXX needed ? */ 6324 rc = sysctl_wire_old_buffer(req, 0); 6325 MPASS(rc == 0); 6326 if (rc != 0) 6327 return (rc); 6328 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6329 MPASS(sb != NULL); 6330 if (sb == NULL) 6331 return (ENOMEM); 6332 if (state[3] <= 3) 6333 ring_state = ring_states[state[3]]; 6334 6335 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6336 state[0], state[1], state[2], ring_state); 6337 rc = sbuf_finish(sb); 6338 sbuf_delete(sb); 6339 return(rc); 6340 } 6341 6342 enum iflib_ndesc_handler { 6343 IFLIB_NTXD_HANDLER, 6344 IFLIB_NRXD_HANDLER, 6345 }; 6346 6347 static int 6348 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6349 { 6350 if_ctx_t ctx = (void *)arg1; 6351 enum iflib_ndesc_handler type = arg2; 6352 char buf[256] = {0}; 6353 qidx_t *ndesc; 6354 char *p, *next; 6355 int nqs, rc, i; 6356 6357 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 6358 6359 nqs = 8; 6360 switch(type) { 6361 case IFLIB_NTXD_HANDLER: 6362 ndesc = ctx->ifc_sysctl_ntxds; 6363 if (ctx->ifc_sctx) 6364 nqs = ctx->ifc_sctx->isc_ntxqs; 6365 break; 6366 case IFLIB_NRXD_HANDLER: 6367 ndesc = ctx->ifc_sysctl_nrxds; 6368 if (ctx->ifc_sctx) 6369 nqs = ctx->ifc_sctx->isc_nrxqs; 6370 break; 6371 default: 6372 panic("unhandled type"); 6373 } 6374 if (nqs == 0) 6375 nqs = 8; 6376 6377 for (i=0; i<8; i++) { 6378 if (i >= nqs) 6379 break; 6380 if (i) 6381 strcat(buf, ","); 6382 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6383 } 6384 6385 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6386 if (rc || req->newptr == NULL) 6387 return rc; 6388 6389 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6390 i++, p = strsep(&next, " ,")) { 6391 ndesc[i] = strtoul(p, NULL, 10); 6392 } 6393 6394 return(rc); 6395 } 6396 6397 #define NAME_BUFLEN 32 6398 static void 6399 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6400 { 6401 device_t dev = iflib_get_dev(ctx); 6402 struct sysctl_oid_list *child, *oid_list; 6403 struct sysctl_ctx_list *ctx_list; 6404 struct sysctl_oid *node; 6405 6406 ctx_list = device_get_sysctl_ctx(dev); 6407 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6408 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6409 CTLFLAG_RD, NULL, "IFLIB fields"); 6410 oid_list = SYSCTL_CHILDREN(node); 6411 6412 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6413 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6414 "driver version"); 6415 6416 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6417 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6418 "# of txqs to use, 0 => use default #"); 6419 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6420 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6421 "# of rxqs to use, 0 => use default #"); 6422 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6423 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6424 "permit #txq != #rxq"); 6425 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6426 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6427 "disable MSI-X (default 0)"); 6428 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6429 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6430 "set the rx budget"); 6431 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6432 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6433 "cause tx to abdicate instead of running to completion"); 6434 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6435 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6436 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6437 "offset to start using cores at"); 6438 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6439 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6440 "use separate cores for TX and RX"); 6441 6442 /* XXX change for per-queue sizes */ 6443 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6444 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6445 mp_ndesc_handler, "A", 6446 "list of # of tx descriptors to use, 0 = use default #"); 6447 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6448 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6449 mp_ndesc_handler, "A", 6450 "list of # of rx descriptors to use, 0 = use default #"); 6451 } 6452 6453 static void 6454 iflib_add_device_sysctl_post(if_ctx_t ctx) 6455 { 6456 if_shared_ctx_t sctx = ctx->ifc_sctx; 6457 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6458 device_t dev = iflib_get_dev(ctx); 6459 struct sysctl_oid_list *child; 6460 struct sysctl_ctx_list *ctx_list; 6461 iflib_fl_t fl; 6462 iflib_txq_t txq; 6463 iflib_rxq_t rxq; 6464 int i, j; 6465 char namebuf[NAME_BUFLEN]; 6466 char *qfmt; 6467 struct sysctl_oid *queue_node, *fl_node, *node; 6468 struct sysctl_oid_list *queue_list, *fl_list; 6469 ctx_list = device_get_sysctl_ctx(dev); 6470 6471 node = ctx->ifc_sysctl_node; 6472 child = SYSCTL_CHILDREN(node); 6473 6474 if (scctx->isc_ntxqsets > 100) 6475 qfmt = "txq%03d"; 6476 else if (scctx->isc_ntxqsets > 10) 6477 qfmt = "txq%02d"; 6478 else 6479 qfmt = "txq%d"; 6480 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6481 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6482 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6483 CTLFLAG_RD, NULL, "Queue Name"); 6484 queue_list = SYSCTL_CHILDREN(queue_node); 6485 #if MEMORY_LOGGING 6486 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6487 CTLFLAG_RD, 6488 &txq->ift_dequeued, "total mbufs freed"); 6489 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6490 CTLFLAG_RD, 6491 &txq->ift_enqueued, "total mbufs enqueued"); 6492 #endif 6493 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6494 CTLFLAG_RD, 6495 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6496 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6497 CTLFLAG_RD, 6498 &txq->ift_pullups, "# of times m_pullup was called"); 6499 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6500 CTLFLAG_RD, 6501 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6502 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6503 CTLFLAG_RD, 6504 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6505 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6506 CTLFLAG_RD, 6507 &txq->ift_map_failed, "# of times dma map failed"); 6508 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6509 CTLFLAG_RD, 6510 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6511 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6512 CTLFLAG_RD, 6513 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6514 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6515 CTLFLAG_RD, 6516 &txq->ift_pidx, 1, "Producer Index"); 6517 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6518 CTLFLAG_RD, 6519 &txq->ift_cidx, 1, "Consumer Index"); 6520 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6521 CTLFLAG_RD, 6522 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6523 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6524 CTLFLAG_RD, 6525 &txq->ift_in_use, 1, "descriptors in use"); 6526 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6527 CTLFLAG_RD, 6528 &txq->ift_processed, "descriptors procesed for clean"); 6529 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6530 CTLFLAG_RD, 6531 &txq->ift_cleaned, "total cleaned"); 6532 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6533 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6534 0, mp_ring_state_handler, "A", "soft ring state"); 6535 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6536 CTLFLAG_RD, &txq->ift_br->enqueues, 6537 "# of enqueues to the mp_ring for this queue"); 6538 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6539 CTLFLAG_RD, &txq->ift_br->drops, 6540 "# of drops in the mp_ring for this queue"); 6541 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6542 CTLFLAG_RD, &txq->ift_br->starts, 6543 "# of normal consumer starts in the mp_ring for this queue"); 6544 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6545 CTLFLAG_RD, &txq->ift_br->stalls, 6546 "# of consumer stalls in the mp_ring for this queue"); 6547 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6548 CTLFLAG_RD, &txq->ift_br->restarts, 6549 "# of consumer restarts in the mp_ring for this queue"); 6550 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6551 CTLFLAG_RD, &txq->ift_br->abdications, 6552 "# of consumer abdications in the mp_ring for this queue"); 6553 } 6554 6555 if (scctx->isc_nrxqsets > 100) 6556 qfmt = "rxq%03d"; 6557 else if (scctx->isc_nrxqsets > 10) 6558 qfmt = "rxq%02d"; 6559 else 6560 qfmt = "rxq%d"; 6561 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6562 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6563 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6564 CTLFLAG_RD, NULL, "Queue Name"); 6565 queue_list = SYSCTL_CHILDREN(queue_node); 6566 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6567 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 6568 CTLFLAG_RD, 6569 &rxq->ifr_cq_pidx, 1, "Producer Index"); 6570 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6571 CTLFLAG_RD, 6572 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6573 } 6574 6575 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6576 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6577 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6578 CTLFLAG_RD, NULL, "freelist Name"); 6579 fl_list = SYSCTL_CHILDREN(fl_node); 6580 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6581 CTLFLAG_RD, 6582 &fl->ifl_pidx, 1, "Producer Index"); 6583 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6584 CTLFLAG_RD, 6585 &fl->ifl_cidx, 1, "Consumer Index"); 6586 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6587 CTLFLAG_RD, 6588 &fl->ifl_credits, 1, "credits available"); 6589 #if MEMORY_LOGGING 6590 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6591 CTLFLAG_RD, 6592 &fl->ifl_m_enqueued, "mbufs allocated"); 6593 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6594 CTLFLAG_RD, 6595 &fl->ifl_m_dequeued, "mbufs freed"); 6596 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6597 CTLFLAG_RD, 6598 &fl->ifl_cl_enqueued, "clusters allocated"); 6599 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6600 CTLFLAG_RD, 6601 &fl->ifl_cl_dequeued, "clusters freed"); 6602 #endif 6603 6604 } 6605 } 6606 6607 } 6608 6609 void 6610 iflib_request_reset(if_ctx_t ctx) 6611 { 6612 6613 STATE_LOCK(ctx); 6614 ctx->ifc_flags |= IFC_DO_RESET; 6615 STATE_UNLOCK(ctx); 6616 } 6617 6618 #ifndef __NO_STRICT_ALIGNMENT 6619 static struct mbuf * 6620 iflib_fixup_rx(struct mbuf *m) 6621 { 6622 struct mbuf *n; 6623 6624 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6625 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6626 m->m_data += ETHER_HDR_LEN; 6627 n = m; 6628 } else { 6629 MGETHDR(n, M_NOWAIT, MT_DATA); 6630 if (n == NULL) { 6631 m_freem(m); 6632 return (NULL); 6633 } 6634 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6635 m->m_data += ETHER_HDR_LEN; 6636 m->m_len -= ETHER_HDR_LEN; 6637 n->m_len = ETHER_HDR_LEN; 6638 M_MOVE_PKTHDR(n, m); 6639 n->m_next = m; 6640 } 6641 return (n); 6642 } 6643 #endif 6644 6645 #ifdef NETDUMP 6646 static void 6647 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 6648 { 6649 if_ctx_t ctx; 6650 6651 ctx = if_getsoftc(ifp); 6652 CTX_LOCK(ctx); 6653 *nrxr = NRXQSETS(ctx); 6654 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6655 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6656 CTX_UNLOCK(ctx); 6657 } 6658 6659 static void 6660 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event) 6661 { 6662 if_ctx_t ctx; 6663 if_softc_ctx_t scctx; 6664 iflib_fl_t fl; 6665 iflib_rxq_t rxq; 6666 int i, j; 6667 6668 ctx = if_getsoftc(ifp); 6669 scctx = &ctx->ifc_softc_ctx; 6670 6671 switch (event) { 6672 case NETDUMP_START: 6673 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6674 rxq = &ctx->ifc_rxqs[i]; 6675 for (j = 0; j < rxq->ifr_nfl; j++) { 6676 fl = rxq->ifr_fl; 6677 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6678 } 6679 } 6680 iflib_no_tx_batch = 1; 6681 break; 6682 default: 6683 break; 6684 } 6685 } 6686 6687 static int 6688 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m) 6689 { 6690 if_ctx_t ctx; 6691 iflib_txq_t txq; 6692 int error; 6693 6694 ctx = if_getsoftc(ifp); 6695 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6696 IFF_DRV_RUNNING) 6697 return (EBUSY); 6698 6699 txq = &ctx->ifc_txqs[0]; 6700 error = iflib_encap(txq, &m); 6701 if (error == 0) 6702 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6703 return (error); 6704 } 6705 6706 static int 6707 iflib_netdump_poll(struct ifnet *ifp, int count) 6708 { 6709 if_ctx_t ctx; 6710 if_softc_ctx_t scctx; 6711 iflib_txq_t txq; 6712 int i; 6713 6714 ctx = if_getsoftc(ifp); 6715 scctx = &ctx->ifc_softc_ctx; 6716 6717 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6718 IFF_DRV_RUNNING) 6719 return (EBUSY); 6720 6721 txq = &ctx->ifc_txqs[0]; 6722 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6723 6724 for (i = 0; i < scctx->isc_nrxqsets; i++) 6725 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6726 return (0); 6727 } 6728 #endif /* NETDUMP */ 6729